1982_Fairchild_Linear_Division_Products 1982 Fairchild Linear Division Products
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1982 LINEAR DIVISION PRODUCTS
FAIRCHILO
A Schlumberger Company
©
1982 Fairchild Camera and Instrument Corporation' 313 Fairchild Drive, Mountain View, California 94042 • Printed in U.S.A.
Fairchild reserves the right to make changes in the circuitry or specifications in this book at any time without notice.
Manufactured under one of the following U.S. Patents: 2981877, 3015048, 3064167, 3108359, 3117260, other patents pending.
Fairchild cannot assume responsibility for use of any circuitry described other than circuitry entirely embodied in a Fairchild product.
No other circuit patent licenses are implied.
Printed in U.S.A. 610000 100M January 1982
Introduction
Product specifications in this data book cover the current standard linear product line. The data sheets
included are organized in sections by type of product-Operational Amplifier, Comparator, Voltage
Regulator, Interface, Data Acquisition, Telecommunication, and Special Function. In addition, a
separate section covers hybrid voltage regulators.
Basic product specifications are listed on each data sheet, including maximum ratings, electrical
characteristics, performance curves, and packaging information. For many products, typical applications and test circuits are also included. A separate section on packaging includes detailed
information about the various packages available. The codes included on each data sheet indicate
the specific package(s) offered for the product.
An industry cross reference 'keys Fairchild linear products to direct replacements and functional
equivalents offered by other major linear product manufacturers. In addition, there is an alpha-numeric
product listing including all basic part numbers. Electrical, temperature, and package variations as
indicated by suffixes are not included in the alpha-numeric listing. These variations are indicated on the
data sheet referenced under Order Information. An explanation of the part numbering method appears
at the beginning of the packaging section.
Information about high reliability linear products and any other product information may be obtained
from a local sales office or by contacting:
Fairchild Linear Products
Marketing Department MS 4-370
313 Fairchild Drive
Mountain View, California 94042
Any inquiries involving the hybrid voltage regulators included in this data book should be directed to:
Fairchild Hybrid Products
Marketing Department MS 19-1425
369 Whisman Road
Mountain View, California 94042
The specifications included in this data book are as current and correct as could reasonably be determined at time of printing. Any errors noted by users, whether involving content or omission, can be
directed to Linear Marketing at the above address; such information would be appreciated.
FAIRCHILD
Table of Contents
A Schlumberger Company
Section One
Page
Alpha Numeric Index .......................... 1-3
Industry Cross Reference ...................... 1-5
Ordering Information ......................... 1-10
Section Two
Voltage Regulators
Testing ...................................... 2-3
Thermal Considerations ........................ 2-7
~A7800 Series .............................. 2-14
~A78MOO Series ............................ 2-28
~A78LOO Series ............................. 2-43
~A109, ~A209, ~A309 ........................ 2-51
~A7900 Series .............................. 2-57
~A 79MOO Series ............................ 2-66
~A78G, ~A79G .............................. 2-74
~A78MG, ~A79MG ........................... 2-84
~A723 ..................................... 2-94
~A105, ~A205, ~A305, ~A305A, ~A376 ....... 2-102
~A 117, ~A217, ~A317 ...................... 2-109
~A431 .................................... 2-115
~A78S40 .................................. 2-119
~A494 .................................... 2-126
Section Three
Hybrid Voltage Regulators
~A78H05A ................................... 3-3
~A78P05 .................................... 3-7
~A78H12A .................................. 3-11
~A78HGA .................................. 3-15
~A79HG .................................... 3-19
SH323, SH223, SH123 ....................... 3-23
SH1605 ..................................... 3-27
'Section Four
Operational Amplifiers
Testing ...................................... 4-3
~A709 ...................................... 4-9
~A714 , ........................... , ........ 4-17
~A715 ..................................... 4-25
~A725 ..................................... 4-33
~A739, ~A749 .............................. 4-44
~A741 ..................................... 4-55
~A747 ..................................... 4-64
~A748 ..................................... 4-73
~A759 ..................................... 4-83
~A771,ILA772, ~A774 ....................... .4-92
~A776 ..................................... 4-99
Section Four
Operational Amplifiers (Cont.)
Page
~A791 ...... , ............................. 4-109
~A798 .................................... 4-115
~A 101, ~A201 ............................. 4-121
~A101A, ~A201A, ~A301A ................... 4-123
~A107, ~A207, ~A307 ...................... 4-131
~A108/A, ~A208/A, ~A308/A ............... 4-137
~A318 .................................... 4-145
~A124, ~A224, ~A324, ~A2902 .............. 4-151
~A 148, ~A248, ~A348 ..................... .4-156
~A1458, ~A1558 ........... , ............... 4-161
~A3303, ~A3403 ........................... 4-166
~A4136 ................................... 4-174
Section Five
Comparators
~A710 ...................................... 5-3
~A711 ..................................... 5-10
~A734 ..................................... 5-16
~A760 ..................................... 5-26
~A 111, ~A311 .............................. 5-33
~A 139, ~A239, ~A339, ~A290 1, ~A3302 ........ 5-40
~A193, ~A293, ~A393, ~A2903 ................ 5-49
Section Six
Interface
~A9614 ..................................... 6-3
~A9615 ................... , ................ 6-10
~A9616 .................................... 6-17
~A9627, ~A9627C .......... , ................ 6-22
~A9636A ................................... 6-27
~A9637 A ................................... 6-31
~A9638 .................................... 6-35
~A 1488 .................................... 6-38
~A 1489, ~A 1489A ........................... 6-42
~A75107A, ~A75107B, ~A75108B ............. 6-46
~A55/75110A .............................. 6-55
~A75150 ................................... 6-59
~A75154 .................. , ................ 6-63
~A9640 (26S10) ............................ 6-69
~A3448A ................................... 6-72
~A8T26A, ~A8T28 ........................... 6-78
~A9643 .................................... 6-84
~A9645 (3245) .............................. 6-87
~A9665/6/7 /8 ............................. 6-90
~A75450/60/70 ............................ 6-96
~A75491, ~A75492 ......................... 6-114
~A438 .................................... 6-118
Table of Contents continued next page
Table of Contents
Section Seven
Data Acquisition
Page
,uA9650 ..................................... 7-3
,uA9706 ..................................... 7-9
,uA9708 .................................... 7-14
,uA 198, ,uA298, ,uA398 ........................ 7-21
,uA565 ..................................... 7-26
,uA571 ..................................... 7-33
,uA080 1 (OAC-08) ........................... 7-42
,uA0802 (MC 1508/1408) ..................... 7 -51
Section Ten
Page
Hi Rei Processing ........................... 10-3
Section Eleven
Package Outlines ........................... 11-3
Section Twelve
Fairchild Sales Offices ...................... 12-3
Section Eight
Telecommunications
,uA3680
,uA5116
,uA5151
,uA5156
..................................... 8-3
..................................... 8-7
.................................... 8-18
.................................... 8-29
Section Nine
Special Functions
,uA555 ...................................... 9-3
,uA556 ...................................... 9-9
,uA726 ..................................... 9-15
,uA727 ..................................... ~18
,uA733 ..................................... 9-22
,uA 757 ..................................... 9-29
,uA2240 .................................... 9-36
,uA3086 .................................... 9-46
,uA7392 .................................... 9-51
I=AIRCHILD
A Schlumberger Company
Indices, Cross Reference
and Order Information
'~
"
,
",
"
,
,
e
'
"
,~
','"
>~,
,
Data Acquisition'
Tilecommunications '
"
,HI, .,.. P~aJng
,
'
~
"
,
'
,
/,'
,
,
'
1-2
Alpha Numeric Index
F=AIRCHIL.O
A Schlumberger Company
Device
Description
Page
Device
Description
Page
""A8T26A
""A8T28A
""A78G
""A78HGA
""A78H05A
""A78H12A
""A78L05A
""A78L62A
""A78L82A
""A78L98A
""A78L12A
""A78L15A
""A78M05
""A78M06
""A78M08
""A78M12
""A78M15
""A78M24
""A78MG
""A78P05
""A78S40
""A79G
""A79HG
""A79M05
""A79M08
""A79M12
""A79M15
""A79MG
""Al0l
""Al01A
""Al05
""A 107
""A 108
""Al08A
""A 109
""A 111
""Al17
""A124
""A139
""A148
""A 193
""A 193A
""A198
""A201
""A201A
""A207
""A208
""A208A
""A209
""A217
""A224
""A239
""A239A
Interface
Interface
Voltage Regulator
Hybrid Voltage Regulator
Hybrid Voltage Regulator
Hybrid Voltage Regulator
Voltage Regulator
Voltage Regulator
Voltage Regulator
Voltage Regulator
Voltage Regulator
Voltage Regulator
Voltage Regulator
Voltage Regulator
Voltage Regulator
Voltage Regulator
Voltage Regulator
Voltage Regulator
Voltage Regulator
Hybrid Voltage Regulator
Voltage Regulator
Voltage Regulator
Hybrid Voltage Regulator
Voltage Regulator
Voltage Regulator
Voltage Regulator
Voltage Regulator
Voltage Regulator
Operational Amplifier
Operational Amplifier
Voltage Regulator
Operational Amplifier
Operational Amplifier
Operational Amplifier
Voltage Regulator
Comparator
Voltage Regulator
Operational Amplifier
Comparator
Operational Amplifier
Comparator
Comparator
Data Acquisition
Operational Amplifier
Operational Amplifier
Operational Amplifier
Operational Amplifier
Operational Amplifier
Voltage Regulator
Voltage Regulator
Operational Amplifier
Comparator
Comparator
6-78
6-78
2-74
3-15
3-3
3-11
2-43
2-43
2-43
2-43
2-43
2-43
2-28
2-28
2-28
2-28
2-28
2-28
2-84
3-7
2-119
2-74
3-19
2-66
2-66
2-66
2-66
2-84
4-121
4-123
2-102
4-131
4-137
4-137
2-51
5-33
2-109
4-151
5-40
4-156
5-49
5-49
7-21
4-121
4-123
4-131
4-137
4-137
2-51
2-109
4-151
5-40
5-40
""A248
""A293
""A293A
""A298
""A301A
""A305
""A305A
""A307
""A308
""A308A
""A309
""A311
""A317
""A318
""A324
""A339
""A339A
""A348
""A376
""A393
""A393A
""A398
""A431A
""A438
""A494
""A555
""A556
""A565
""A571
""A709
""A709A
""A709C
""A710
""A711
""A714
""A715
""A723
""A725
""A725A
""A726
""A727
""A 733
""A734
""A739
""A741
""A747
""A748
""A749
""A757
""A759
""A760
""A771
""A772
Operational Amplifier
Comparator
Comparator
Data Acquisition
Operational Amplifier
Voltage Regulator
Voltage Regulator
Operational Amplifier
Operational Amplifier
Operational Amplifier
Voltage Regulator
Comparator
Voltage Regulator
Operational Amplifier
Operational Amplifier
Comparator
Comparator
Operational Amplifier
Voltage Regulator
Comparator
Comparator
Data Acquisition
Voltage Regulator
Interface
Voltage Regulator
Special Function
Special Function
Data Acquisition
Data Acquisition
Operational Amplifier
Operational Amplifier
Operational Amplifier
Comparator
Comparator
Operational Amplifier
Operational Amplifier
Voltage Regulator
Operational Amplifier
Operational Amplifier
Special Function
Special Function
Special Function
Comparator
Operational Amplifier
Operational Amplifier
Operational Amplifier
Operational Amplifier
Operational Amplifier
Special Function
Operational Amplifier
Comparator
Operational Amplifier
Operational Amplifier
4-156
5-49
5-49
7-21
4-123
2-102
2-102
4-131
4-137
4-137
2-51
5-33
2-109
4-145
4-151
5-40
5-40
4-156
2-102
5-49
5-49
7-21
2-115
6-118
2-126
9-3
9-9
7-26
7-33
4-9
4-9
4-9
5-3
5-10
4-17
4-25
2-94
4-33
4-33
9-15
9-18
9-22
5-16
4-44
4-55
4-64
4-73
4-44
9-29
4-83
5-26
4-92
4-92
1-3
II
Alpha Numeric Index
Device
Description
Page
Device
Description
Page
IlA774
IlA776
IlA791
IlA798
IlA0801
IlA0802
IlA1458
IlA1488
IlA1489
IlA1558
IlA2240
IlA2901
IlA2902
IlA2903
IlA3086
IlA3302
IlA3303
IlA3403
IlA3448
IlA3680
IlA4136
IlA5116
IlA5151
IlA5156
IlA7392
IlA7805
IlA7806
IlA7808
IlA7885
IlA7812
IlA7815
IlA7818
IlA7824
IlA7905
IlA7908
IlA7912
IlA7915
IlA9614
IlA9615
IlA9616
IlA9627
IlA9636A
IlA9637A
IlA9638
IlA9640
IlA9643
IlA9645
IlA9650
IlA9665
IlA9666
IlA9667
IlA9668
IlA9706
IlA9708
IlA55107A
IlA55110A
IlA75107A
IlA75107B
IlA75108B
IlA75110A
IlA75150
IlA75154
Operational Amplifier
Operational Amplifier
Operational Amplifier
Operational Amplifier
Data Acquisition
Data Acquisition
Operational Amplifier
Interface
Interface
Operational Amplifier
Special Function
Comparator
Operational Amplifier
Comparator
Special Function
Comparator
Operational Amplifier
Operational Amplifier
Interface
Telecommunication
Operational Amplifier
Telecommunication
Telecommunication
Telecommunication
Special Function
Voltage Regulator
Voltage Regulator
Voltage Regulator
Voltage Regulator
Voltage Regulator
Voltage Regulator
Voltage Regulator
Voltage Regulator
Voltage Regulator
Voltage Regulator
Voltage Regulator
Voltage Regulator
Interface
Interface
Interface
Interface
Interface
Interface
Interface
Interface
Interface
Interface
Data Acquisition
Interface
Interface
Interface
Interface
Data Acquisition
Data Acquisition
Interface
Interface
Interface
Interface
Interface
Interface
Interface
Interface
4-92
4-99
4-109
4-115
7-42
7-51
4-161
6-38
6-42
4-161
9-36
5-40
4-151
5-49
9-46
5-40
4-166
4-166
6-72
8-3
4-174
8-7
8-18
8-29
9-51
2-14
2-14
2-14
2-14
2-14
2-14
2-14
2-14
2-57
2-57
2-57
2-57
6-3
6-10
6-17
6-22
6-27
6-31
6-35
6-69
6-84
6-87
7-3
6-90
6-90
6-90
6-90
7-9
7-14
6-46
6-55
6-46
6-46
6-46
6-55
6-59
6-63
IlA75450B
IlA75451A
IlA75451B
IlA75452A
IlA75452B
IlA75453A
IlA75453B
IlA75461
IlA75462
IlA75471
IlA75472
IlA75491
IlA75492
SH123
SH223
SH323
SH1605
Interface
Interface
Interface
Interface
Interface
Interface
Interface
Interface
Interface
Interface
Interface
Interface
Interface
Hybrid Voltage
Hybrid Voltage
Hybrid Voltage
Hybrid Voltage
6-96
6-96
6-96
6-96
6-96
6-96
6-96
6-96
6-96
6-96
6-96
6-114
6-114
3-23
3-23
3-23
3-27
1-4
Regulator
Regulator
Regulator
Regulator
Industry
Cross Reference Guide
FAIRCHILD
A Schlumberger Company
Part
Number
Fairchild
Equivalent
Fairchild
Equivalent
AMD (Cont.)
AMD
715DC
715HC
715DM
715HM
723DC
723DM
723HC
723HM
723PC
725HC
725HM
733DC
733DM
733HC
733HM
741FM
741HC
741HM
741AFM
741AHM
741EHC
747DC
747DM
747HC
747HM
747PC
747ADM
747AHM
747EDC
747EHC
748HC
748HM
AM1408L6
AM1408L7
AM1408L8
AM1458H
AM1508L8
AM1558H
DAC-08CQ
DAC-08EQ
DAC-08Q
LM101H
LM101AH
LM105H
LM108H
LM108AH
LM111H
LM124D
Part
Number
J.lA715DC
J.lA715HC
J.lA715DM
J.lA715HM
J.lA723DC
J.lA723DM
J.lA723HC
J.lA723HM
J.lA723PC
J.lA725HC
J.lA725HM
J.lA733DC
J.lA733DM
J.lA733HC
J.lA733HM
J.lA741FM
J.lA741HC
J.lA741HM
J.lA741AFM
J.lA741AHM
J.lA741EHC
J.lA747DC
J.lA747DM
J.lA747HC
J.lA747HM
J.lA747PC
J.lA747ADM
J.lA747AHM
J.lA747EDC
J.lA747EHC
J.lA748HC
J.lA748HM
J.lA0802CDC
J.lA0802BDC
J.lA0802ADC
J.lA1458HC
J.lA0802DM
J.lA1558HM
J.lA0801CDC
J.lA0801EDC
J.lA0801DM
J.lA101HM
J.lA101AHM
J.lA105HM
J.lA108HM
J.lA1 08AHM
J.lA111HM
J.lA124DM
LM139D
LM139AD
LM201H
LM201AH
LM208H
LM208AH
LM224D
LM239D
LM239AD
LM301AH
LM305H
LM305AH
LM308H
LM308AH
LM311H
LM324D
LM324N
LM339D
LM339N
LM339AD
LM339AN
Part
Number
Fairchild
Equivalent
INTERSIL (Cont.)
J.lA139DM
J.lA139ADM
J.lA201HC
J.lA201AHM
J.lA208HM
J.lA208AHM
J.lA224DV
J.lA239DC
J.lA239ADC
J.lA301AHC
J.lA305HC
J.lA305AHC
J.lA308HC
J.lA308AHC
J.lA311HC
J.lA324DC
J.lA324PC
J.lA339DC
J.lA339PC
J.lA339ADC
J.lA339APC
INTERSIL
ICL 108LNTY
ICL741CHSPA
ICL 7 41 MHSTY
LM101AH
LM105H
LM108H
LM108AH
LM111H
LM124J
LM301AH
LM301AN
LM305H
LM308H
LM308N
LM308AH
LM308AN
LM311H
LM311N
LM324J
LM324N-14
NE555N
NE556N
J.lA723DC
J.lA723DM
J.lA723HC
J.lA108HM
J.lA741TC
J.lA741HM
J.lA101AHM
J.lA105HM
J.lA108HM
J.lA108AHM
J.lA111HM
J.lA124DM
J.lA301AHC
J.lA301ATC
J.lA305HC
J.lA308HC
J.lA308TC
J.lA308AHC
J.lA308ATC
J.lA311HC
J.lA311TC
J.lA324DC
J.lA324PC
J.lA555TC
J.lA556PC
J.lA723DC
J.lA723DM
J.lA723HC
·Note
Not exact package replacement
1-5
J.lA723HM
J.lA723PC
J.lA733HC
J.lA733HM
J.lA741FM
J.lA741HC
J.lA741HM
J.lA741TC
J.lA748HC
J.lA748HM
J.lA748TC
J.lA723HM
J.lA723PC
J.lA733HC
J.lA733HM
J.lA741FM
J.lA741HC
J.lA741HM
J.lA741TC
J.lA748HC
J.lA748HM
J.lA748TC
MOTOROLA
LM101AH
LM105HM
LM108H
LM108AH
LM109K
LM111H
LM111J-8
LM117K
LM124J
LM139J
LM139AJ
LM201AH
LM208H
LM208AH
LM209K
LM217K
LM224J
LM239AJ
LM239J
LM293H
LM293AH
LM301AH
LM301AN
LM305H
LM308AH
LM308AN
LM308H
LM308N
LM309K
LM311H
LM311J-8
LM311N
LM317K
LM317T
LM324J
J.lA101AHM
J.lA105HM
J.lA108HM
J.lA1 08AHM
J.lA109KM
J.lA111HM
J.lA111RM
J.lA117KM
J.lA124DM
J.lA139DM
J.lA139ADM
J.lA201AHM
J.lA208HM
J.lA208AHM
J.lA209KM
J.lA217UV
J.lA224DV
J.lA239ADC
J.lA239DC
*J.lA293RC
*J.lA293ARC
J.lA301AHC
J.lA301ATC
J.lA305HC
J.lA308AHC
J.lA308ATC
J.lA308HC
J.lA308TC
J.lA309KC
J.lA311HC
J.lA311RC
J.lA311TC
J.lA317KC
J.lA317UC
J.lA324DC
•
Industry Cross Reference Guide
Part
Number
Fairchild
Equivalent
MOTOROLA (Cont.)
LM339AJ
ILA339ADC
LM339J
ILA339DC
LM393AN
ILA393ATC
LM393N
ILA393TC
LM710CH
ILA710HC
LM711CH
ILA711HC
LM723CH
ILA723HC
LM723CJ
ILA723DC
LM741CH
ILA741HC
LM741CN
ILA741TC
LM2901N
ILA2901PC
LM2902N
ILA2902PV
LM2903N
ILA2903TC
MC1408L6
ILA0802CDC
MC1408L7
ILA0802BDC
MC1408L8
ILA0802ADC
MC1408P6
ILA0802CPC
MC1408P7
ILA0802BPC
MC1408P8
ILA0802APC
MC1411P
ILA9665PC
MC1412P
ILA9666PC
MC1413P
ILA9667PC
MC1416P
ILA9668PC
MC1455P1
ILA555TC
MC1458CG
ILA1458CHC
MC1458CP1
ILA1458CTC
MC1458CU
ILA1458CRC
MC1458G
ILA1458HC
MC1458P1
ILA1458TC
MC1458U
ILA1458RC
MC1488L
ILA1488DC
MC1488P
ILA1488PC
MC1489L
ILA1489DC
MC1489P
ILA1489PC
MC1489AL
ILA1489ADC
MC1489AP
ILA1489APC
MC1508L8
ILA0802DM
MC1558G
ILA1558HM
MC1558U
ILA1558RM
MC1709CP1
ILA709TC
MC1709CP2
ILA709PC
MC1709G
ILA709HM
MC1710CG
ILA710HC
MC1710CL
ILA710DC
MC1710CP
ILA710PC
MC1710G
ILA710HM
MC1710L
ILA710DM
MC1711CG
ILA711HC
MC1711CL
ILA711DC
MC1711CP
ILA711PC
MC1711G
ILA711HM
MC1711L
ILA711DM
MC1723CG
ILA723HC
MC1723CL
ILA723DC
MC1723CP
ILA723PC
MC1723G
ILA723HM
MC1723L
ILA723DM
MC1733G
ILA733HM
MC1733L
ILA733DM
Part
Number
Fairchild
Equivalent
MOTOROLA (Cont.)
MC1733CG
ILA733HC
MC1733CL
ILA733DC
MC1741CG
ILA741HC
MC1741CP1
ILA741TC
MC1741CU
ILA741RC
MC1741G
ILA741HM
MC1747CG
ILA747HC
MC1747CL
ILA747DC
MC1747CP2
ILA747PC
MC1747G
ILA747HM
MC1747L
ILA747DM
MC1748CG
ILA748HC
MC1748CP1
ILA748TC
MC1748G
ILA748HM
MC1776CG
ILA776HC
MC1776CP1
ILA776TC
MC1776G
ILA776HM
MC3302L
ILA3302DC
MC3302P
ILA3302PC
MC3303P
ILA3303PC
MC3386P
ILA3086PC
MC3403L
ILA3403DC
MC3403P
ILA3403PC
MC3440AP
ILA9640PC
MC3443P
ILA9640PC
MC3448AL
ILA3448ADC
MC3448AP
ILA3448APC
MC3456P
ILA556PC
MC3458P1
ILA798TC
MC3488AP
ILA9636AT
MC3558U
*ILA798TC
MC55107L
ILA55107ADM
MC75107L
ILA75107ADC
MC75107P
ILA75107APC
MC75450P
ILA75450BPC
MC75451U
ILA75451ARC
MC75452U
ILA75452ARC
MC75453U
ILA75453ARC
MC75461P
ILA75461TC
MC75462P
ILA75462TC
MC75491P
ILA75491 PC
MC75492P
ILA75492PC
MC7805K
ILA7805KM
MC7805CK
ILA7805KC
MC7805CT
ILA7805UC
MC7806CK
ILA7806KC
MC7806CT
ILA7806UC
MC7812K
ILA7812KM
MC7812CK
ILA7812KC
MC7812CT
ILA7812UC
MC7815K
ILA7815KM
MC7815CK
ILA7815KC
MC7815CT
ILA7815UC
MC7818K
ILA7818KM
MC7818CK
ILA7818KC
MC7818CT
ILA7818UC
MC7824K
ILA7824KM
MC7824CK
ILA7824KC
MC7824CT
ILA7824UC
-Note
Not exact package replacement
1-6
Part
Number
Fairchild
Equivalent
MOTOROLA (Cont.)
MC78L05ACP
ILA78L05AWC
MC78L 12ACP
ILA78L 12AWC
MC78L 15ACP
ILA78L 15AWC
MC78M05CG
ILA78M05HC
MC78M05CT
ILA78M05UC
MC78M06CG
ILA78M06HC
MC78M06CT
ILA78M06UC
MC78M08CG
ILA78M08HC
MC78M08CT
ILA78M08UC
MC78M12CG
ILA78M12HC
MC78M12CT
ILA78M12UC
MC78M15CT
ILA78M15UC
MC78M24CT
ILA78M24UC
MC7905CK
ILA7905KC
MC7905CT
ILA7905UC
MC7908CK
ILA7908KC
MC7908CT
ILA7908UC
MC7912CK
ILA7912KC
MC7912CT
ILA7912UC
MC7915CK
ILA7915KC
MC7915CT
ILA7915UC
MC8T26AP
ILA8T26APC
MC8T26AL
ILA8T26ADC
MC8T28AP
ILA8T28PC
MC8T28AL
ILA8T28DC
SN75451BP
*ILA75451BTC
SN75452BP
ILA75452BTC
SN75453BP
ILA75453BTC
ILA710HC
ILA710HC
ILA711HC
ILA711HC
ILA723DC
ILA723DC
ILA723HC
ILA723HC
ILA723PC
ILA723PC
ILA741HC
ILA741HC
ILA741TC
ILA741TC
NATIONAL
DS75107J
DS75107N
DS75108N
DS75450N
DS75451J-8
DS75451N
DS75452J-8
DS75452N
DS75453J-8
DS75453N
DS75461N
DS75462N
DS75491N
DS75492N
DS8T26AJ
DS8T28J
LF351N
LF353N
LF398H
LM101AH
LM105H
LM108H
ILA75107ADC
ILA75107APC
ILA75108BPC
ILA75450BPC
ILA75451 ARC
ILA75451ATC
ILA75452ARC
ILA75452ATC
ILA75453ARC
ILA75453ATC
ILA75461TC
ILA75462TC
ILA75491PC
ILA75492PC
ILA8T26ADM
ILA8T28DM
ILA771TC
ILA772TC
ILA398HC
ILA101AHM
ILA105HM
ILA108HM
Industry Cross Reference Guide
Part
Number
Fairchild
Equivalent
NATIONAL (Cont.)
LM108H
LM109K
LM111H
LM124J
LM139J
LM139AJ
LM140K-5.0
LM140K-8.0
LM140K-12
LM140K-15
LM140K-18
LM140K-24
LM201AH
LM208H
LM208AH
LM209K
LM224J
LM239J
LM239AJ
LM301AH
LM301AN
LM305H
LM305AH
LM308H
LM308N
LM308AH
LM308AN
LM309K
LM311H
LM311J-8
LM311N
LM317K
LM317T
LM324J
LM324N
LM339J
LM339N
LM339AJ
LM339AN
LM340K-5.0
LM340T-5.0
LM340K-6.0
LM340K-8.0
LM340K-12
LM340T-12
LM340K-15
LM340T-15
LM340K-18
LM340K-24
LM348J
LM348N
LM376N
LM393N
LM555CN
LM556CN
LM709H
LM709CH
LM709CN
LM709CN-8
J.LA108AHM
J.LA109KM
J.LA111HM
J.LA124DM
J.LA139DM
J.LA139ADM
J.LA7805KM
J.LA7808KM
J.LA7812KM
J.LA7815KM
J.LA7818KM
J.LA7824KM
J.LA201AHM
J.LA208HM
J.LA208AHM
J.LA209KM
J.LA224DV
J.LA239DC
J.LA239ADC
J.LA301AHC
J.LA301ATC
J.LA305HC
J.LA305AHC
J.LA308HC
J.LA308TC
J.LA308AHC
J.LA308ATC
J.LA309KC
J.LA311HC
J.LA311RC
J.LA311TC
J.LA317KC
J.LA317UC
J.LA324DC
J.LA324PC
J.LA339DC
J.LA339PC
J.LA339ADC
J.LA339APC
J.LA7805KC
J.LA7805UC
J.LA7806KC
J.LA7808KC
J.LA7812KC
J.LA7812UC
J.LA7815KC
J.LA7815UC
J.LA7818KC
J.LA7824KC
J.LA348DC
J.LA348PC
J.LA376TC
J.LA393TC
J.LAb55TC
J.LA556PC
J.LA709HM
J.LA709HC
J.LA709PC
J.LA709TC
Part
Number
Fairchild
Equivalent
Part
Number
Fairchild
Equivalent
NATIONAL (Cont.)
NATIONAL (Cont.)
LM709AH
LM710H
LM710CH
LM710CN
LM711H
LM711CH
LM711CN
LM723H
LM723J
LM723CH
LM723CJ
LM723CN
LM725H
LM725CH
LM725CN
LM733H
LM733CH
LM733CN
LM741H
LM741AH
LM741CH
LM741CJ
LM741CN
LM741EH
LM741EN
LM747H
LM747J
LM747AH
LM747AJ
LM747CH
LM747CJ
LM747CN
LM747EH
LM747EJ
LM748H
LM748CH
LM748CN
LM760CH
LM1458H
LM1458J
LM1458N
LM1558H
LM1558J
LM2901N
LM2901J
LM2903N
LM3086N
LM3302J
LM3302N
LM7805CK
LM7805CT
LM7812CK
LM7812CT
LM7815CK
LM7815CT
LM78L05ACZ
LM78L 12ACZ
LM78L 15ACZ
LM78M05CP
LM78M12CP
LM78M15CP
LM7905CK
LM7905CT
LM7912CK
LM7912CT
LM7915CK
LM7915CT
LM7905CH
LM7912CH
LM7915CH
J.LA709AHM
J.LA710HM
J.LA710HC
J.LA710PC
J.LA711HM
J.LA711HC
J.LA711PC
J.LA723HM
J.LA723DM
J.LA723HC
J.LA723DC
J.LA723PC
J.LA725HM
J.LA725HC
J.LA725TC
J.LA733HM
J.LA733HC
J.LA733PC
J.LA741HM
J.LA741AHM
J.LA741HC
J.LA741RC
J.LA741TC
J.LA741EHC
J.LA741 ETC
J.LA747HM
J.LA747DM
J.LA747AHM
J.LA747ADM
J.LA747HC
J.LA747DC
J.LA747PC
J.LA747EHC
J.LA747EDC
J.LA748HM
J.LA748HC
J.LA748TC
J.LA760HC
J.LA1458HC
J.LA1458RC
J.LA1458TC
J.LA1558HM
J.LA1558RM
J.LA2901PC
J.LA2901DC
J.LA2903TC
J.LA3086PC
J.LA3302DC
J.LA3302PC
J.LA7805KC
J.LA7805UC
J.LA7812KC
J.LA7812UC
J.LA7815KC
J.LA7815UC
J.LA78L05AWC
J.LA78L 12AWC
J.LA78L 15AWC
°J.LA78M05UC
·Note
Not exact package replacement
1-7
°J.LA78M12UC
°J.LA78M15UC
J.LA7905KC
J.LA7905UC
J.LA7912KC
J.LA7912UC
J.LA7915KC
J.LA7915UC
J.LA79M05AHC
J.LA79M12AHC
J.LA79M15AHC
PMI
CMP-03AJ
CMP-03AZ
CMP-04BY
CMP-04FY
DAC-08Q
DAC-08Q
DAC-08CP
DAC-08CP
DAC-08CQ
DAC-08CQ
DAC-08EP
DAC-08EP
DAC-08EQ
DAC-08EQ
DAC1408A-6P
DAC1408A-6Q
DAC1408A-7P
DAC1408A-7Q
DAC1408A-8P
DAC 1408A-8Q
DAC1508A-8Q
OP-07J
OP-07CJ
OP-07EJ
PM108J
PM108AJ
PM111J
PM111Z
PM139Y
PM208J
PM208AJ
PM308J
PM308P
PM308AJ
PM308AP
PM311J
PM311Z
PM339Y
PM339AY
PM725J
PM725CJ
PM725CP
PM741J
PM741CJ
PM741CZ
PM1458J
J.LA111HM
J.LA111RM
J.LA139DM
J.LA239DC
J.LA0801DM
J.LA0802DM
J.LA0801CPC
J.LA0802BPC
J.LA0801CDC
J.LA0802BDC
J.LA0801EPC
J.LA0802APC
J.LA0801EDC
J.LA0802ADC
J.LA0802CPC
J.LA0802CDC
J.LA0802BPC
J.LA0802BDC
J.LA0802APC
J.LA0802ADC
J.LA0802DM
J.LA714HM
J.LA714HC
J.LA714EHC
J.LA108HM
J.LA108AHM
J.LA111HM
J.LA111RM
J.LA139DM
J.LA208HM
J.LA208AHM
J.LA308HC
J.LA308TC
J.LA308AHC
J.LA308ATC
J.LA311HC
J.LA311RC
J.LA339DC
J.LA339ADC
J.LA725HM
J.LA725HC
J.LA725TC
J.LA741HM
J.LA741HC
J.LA741RC
J.LA1458HC
Industry Cross Reference Guide
Part
Number
Fairchild
Equivalent
PMI (Cont.)
PM1458Z
PM1558J
PM1558Z
ILA1458RC
ILA1558HM
ILA1558RM
SIGNETICS
LM101AH
LMlllH
LM124F
LM139F
LM193FE
LM201AN
LM224N
LM224F
LM301AN
LM324N
LM324F
LM339N
LM339F
LM2901F
LM2901N
LM2903FE
LM2903N
MC1458FE
MC1458H
MC1458N
MC1488N
MC1488F
MC1489N
MC1489F
MC1489AN
MC1489AF
MC1558H
MC1558FE
MC3302N
MC3302F
NE5501
ULN2001N
ULN2003F
ULN2003N
ULN2004F
ULN2004N
ILA723F
ILA723H
ILA723CF
ILA723CH
ILA723CN
ILA733F
pA733H
ILA733CF
ILA733CH
ILA733CN
ILA741FE
ILA741CFE
ILA741CN
ILA747F
ILA747H
ILA747CF
pA747CH
ILA747CN
ILA748CN
ILA101AHM
ILA 1l1HM
ILA124DM
ILA139DM
pA193RM
'ILA201AHM
/LA224PV
ILA224DV
ILA301ATC
ILA324PC
ILA324DC
ILA339PC
ILA339DC
ILA2901DC
ILA2901PC
ILA2903RC
ILA2903TC
ILA1458RC
ILA1458HC
ILA1458TC
ILA1488PC
ILA 1488DC
ILA1489PC
pA1489DC
ILA1489APC
ILA1489ADC
ILA1558HM
ILA1558RM
ILA3302PC
ILA3302DC
ILA9665PC
ILA9665PC
ILA9667DC
ILA9667PC
ILA9668DC
pA9668PC
ILA723DM
ILA723HM
ILA723DC
pA723HC
ILA723PC
ILA733DM
pA733HM
ILA733DC
ILA733HC
ILA733PC
ILA741RM
ILA741RC
ILA741TC
ILA747DM
ILA747HM
ILA747DC
pA747HC
pA747PC
ILA748TC
Part
Number
Fairchild
Equivalent
SILICON
GENERAL
SG10H
SG101AT
SG105T
SG108T
SG108AT
SG109K
SGllH
SG117K
SG124J
SG139J
SG139AJ
SG20H
SG201AT
SG208T
SG208AT
SG209K
SG2l7P
SG224J
SG224N
SG239J
SG239N
SG239AJ
SG239AN
SG301AM
SG301AT
SG305T
SG305AT
SG308M
SG308T
SG308AM
SG308AT
SG309K
SG3l1M
SG311T
SG317K
SG317P
SG324J
SG324N
SG339J
SG339N
SG339AJ
SG339AN
SG555M
SG556N
SG710J
SG710T
SG710CN
SG710CT
SG711J
SG711T
SG711CJ
SG711CN
SG711CT
SG723CJ
SG723CT
SG723J
SG723T
SG723CN
ILA 101HM
pAl01AHM
ILA105HM
ILA108HM
ILA108AHM
ILA109KM
ILA111HM
ILAl17KM
ILA l24DM
ILA139DM
ILA 139ADM
ILA201HC
ILA201AHM
ILA208HM
pA208AHM
ILA209KM
ILA217UV
ILA224DV
ILA224PV
ILA239DC
pA239PC
ILA239ADC
ILA239APC
ILA301ATC
ILA301AHC
ILA305HC
ILA305AHC
ILA308TC
ILA308HC
ILA308ATC
ILA308AHC
ILA309KC
ILA31HC
ILA311HC
ILA317KC
ILA317UC
ILA324DC
ILA324PC
ILA339DC
ILA339PC
ILA339ADC
ILA339APC
ILA555TC
ILA556PC
ILA710DM
pA710HM
ILA710PC
ILA710HC
ILA711DM
ILA711HM
ILA711DC
ILA711PC
ILA711HC
ILA723DC
ILA723HC
ILA723DM
ILA723HM
ILA723PC
'N ote
Not exact package replacement
1-8
Part
Number
Fairchild
Equivalent
SILICON
GENERAL (Cont.)
SG733J
ILA733DM
SG733T
ILA733HM
SG733CJ
ILA733DC
SG733CN
ILA733PC
SG733CT
ILA733HC
SG741F
ILA741FM
SG741T
ILA741HM
SG741CM
ILA741TC
SG747J
ILA747DM
SG747T
ILA747HM
SG747CJ
ILA747DC
SG747CN
ILA747PC
SG747CT
ILA747HC
SG748T
ILA748HM
SG748CM
ILA748TC
SG748CT
ILA748HC
SG1458M
ILA1458TC
SG1458T
ILA1458HC
SG1458CM
pA1458CTC
SG1458CT
ILA1458CHC
SG1488J
ILA1488DC
SG1489J
ILA1489DC
SG1489AJ
ILA l489ADC
SG1558T
ILA1558HM
SG2001J
'ILA9665PC
SG2002J
ILA9666DC
SG2003J
ILA9667DC
SG3086J
ILA3086DC
SG3086N
ILA3086PC
SG3302J
ILA3302DC
SG3302N
ILA3302PC
SG7805K
ILA7805KM
SG7805CK
ILA7805KC
SG7805CP
ILA7805UC
SG7808K
ILA7808KM
SG7808CK
ILA7808KC
SG7808CP
ILA7808UC
SG7812K
ILA7812KM
SG78l2CK
ILA7812KC
SG7812CP
pA7812UC
SG7815K
ILA7815KM
SG7815CK
ILA7815KC
SG7815CP
ILA7815UC
SG7818K
ILA7818KM
SG7818CK
ILA7818KC
SG7818CP
ILA7818UC
SG7824K
ILA7824KM
SG7824CK
pA7824KC
SG7824CP
ILA7824UC
SG7905K
ILA7905KM
SG7905CK
ILA7905KC
SG7905CP
ILA7905UC
SG7908K
ILA7908KM
SG7908CK
ILA7908KC
SG7908CP
ILA7908UC
SG7912K
ILA7912KM
SG7912CK
ILA7912KC
SG7912CP
ILA7912UC
Industry Cross Reference Guide
Part
Number
Fairchild
Equivalent
SILICON
GENERAL (Cont.)
SG7915K
SG7915CK
SG7915CP
SG75450BCN
SG75451BCM
SG75451BCY
SG75452BCM
SG75452BCY
SG75453BCM
SG75453BCY
SG75461CM
SG75462CM
TEXAS
INSTRUMENTS
AM26S10CJ
AM26S10CN
LM101AJ
LM105L
LM111JG
LM124J
LM139J
LM139AJ
LM148J
LM193JG
LM201AJG
LM209LA
LM217KC
LM224J
LM224N
LM239J
LM239N
LM248J
LM293JG
LM293P
LM301AP
LM305L
LM305AL
LM309LA
LM311JG
LM311P
LM317KC
LM318JG
LM324J
LM324N
LM339AJ
LM339AN
LM339J
LM339N
LM348J
LM348N
LM376P
LM393JG
LM393P
LM2901J
LM2901N
LM2902N
LM2903JG
-
ILA7915KM
ILA7915KC
ILA7915UC
ILA75450BPC
ILA75451BTC
ILA75451BRC
ILA75452BTC
ILA75452BRC
ILA75453BTC
ILA75453BRC
ILA75461TC
ILA75462TC
ILA9640DC
ILA9640PC
·ILA101AHM
ILA105HM
ILA 111RM
ILA124DM
ILA139DM
ILA139ADM
ILA148DM
ILA193RM
·ILA201AHM
·ILA209KM
ILA217UV
ILA224DV
ILA224PV
ILA239DC
ILA239PC
ILA248DC
ILA293RC
ILA293TC
ILA301ATC
ILA305HC
ILA305AHC
·ILA309KC
ILA311RC
ILA311TC
ILA317UC
·ILA318HC
ILA324DC
ILA324PC
ILA339ADC
ILA339APC
ILA339DC
ILA339PC
ILA348DC
ILA348PC
ILA376TC
ILA393RC
ILA393TC
ILA2901DC
ILA2091PC
ILA2902PV
ILA2903RC
Part
Number
Fairchild
Equivalent
TEXAS
INSTRUMENTS (Cont.)
LM2903P
ILA2903TC
MC1458JG
ILA1458RC
MC1458P
ILA1458TC
MC1558JG
ILA1558RM
NE555P
ILA555TC
NE556N
ILA556PC
RC4136J
ILA4136DC
RC4136N
ILA4136PC
SA555P
ILA555TC
SN55107AJ
ILA55107ADM
SN55110AJ
ILA55110ADM
SN75107AJ
ILA75107ADC
SN75107AN
ILA75107APC
SN75107BJ
ILA75107BDC
SN75107BN
ILA75107BPC
SN75108BN
ILA75108BPC
SN75110AJ
ILA75110ADC
SN75110AN
ILA75110APC
SN75114J
ILA9614DC
SN75114N
ILA9614PC
SN75115J
ILA9615DC
SN75115N
ILA9615PC
SN75150N
ILA75150PC
SN75150P
ILA75150TC
SN75154J
ILA75154DC
SN75154N
ILA75154PC
SN75188J
ILA1488DC
SN75188N
ILA1488PC
SN75189J
ILA1489DC
SN75189N
ILA1489PC
SN75189AJ
ILA1489ADC
SN75189AN
ILA1489APC
SN75450BN
ILA75450BPC
SN75451BJG
ILA75451BRC
SN75451BP
ILA75451BTC
SN75452BJG
ILA75452BRC
SN75452BP
ILA75452BTC
SN75453BJG
ILA75453BRC
SN75453BP
ILA75453BTC
SN75461P
ILA75461TC
SN75462P
ILA75462TC
SN75471P
ILA75471TC
SN75472P
ILA75472TC
SN75491N
ILA75491PC
SN75492N
ILA75492PC
TL081ACJG
ILA771 ARC
TL081ACP
ILA771ATC
TL081BCJG
ILA771BRC
TL081BCP
ILA771BTC
TL081CJG
ILA771RC
TL081CP
ILA771TC
TL431CLP
ILA431AWC
TL494CN
ILA494PC
TL494CJ
ILA494DC
TL494MJ
ILA494DM
ULN2001AN
ILA9665PC
ULN2002AJ
ILA9666DC
ULN2002AN
ILA9666PC
'Note
Not exact package replacement
1·9
Part
Number
Fairchild
Equivalent
TEXAS
INSTRUMENTS (Cont.)
ULN2003AJ
ILA9667DC
ULN2003AN
ILA9667PC
ULN2004AJ
ILA9668DC
ULN2004AN
ILA9668PC
ILA709MU
ILA709FM
ILA709AMU
ILA709AFM
ILA709CP
ILA709TC
ILA710DC
ILA710CJ
ILA710CN
ILA710PC
ILA710MJ
ILA710DM
ILA711PC
ILA711CN
ILA711MJ
ILA711DM
ILA723CJ
ILA723DC
ILA723PC
ILA723CN
ILA723MJ
ILA723DM
ILA733CJ
ILA733DC
ILA733CN
ILA733PC
ILA733DM
ILA733MJ
ILA741CJG
ILA741RC
ILA741CP
ILA741TC
ILA741RM
ILA741MJG
ILA747DC
ILA747C
ILA747CN
ILA747PC
ILA747MJ
ILA747DM
ILA748TC
ILA748CP
ILA2240CJ
ILA2240DC
ILA2240CN
ILA2240PC
ILA7805CKC
ILA7805UC
ILA7808CKC
ILA7808UC
ILA7812UC
ILA7812CKC
ILA7815UC
ILA7815CKC
ILA7818CKC
ILA7818UC
ILA7824UC
ILA7824CKC
ILA7885CKC
ILA7885UC
ILA78L05AWC
ILA78L05CLP
ILA78L 12AWC
ILA78L12CLP
ILA78L15CLP
ILA78L 15AWC
ILA78M05UC
ILA78M05CKC
ILA78M06UC
ILA78M06CKC
ILA78M08CKC
ILA78M08UC
ILA78M12UC
ILA78M12CKC
ILA78M15CKC
ILA78M15UC
ILA78M24CKC
ILA78M24UC
ILA7905UC
ILA7905CKC
ILA7908UC
ILA7908CKC
ILA7912UC
ILA7912CKC
ILA7915CKC
ILA7915UC
ILA 79M05AUC
ILA79M05CKC
ILA 79M08AUC
ILA79M08CKC
ILA79M12CKC
ILA 79M 12AUC
ILA 79M 15AUC
ILA79M 15CKC
9614CJ
ILA9614DC
9614CN
ILA9614PC
9615CJ
ILA9615DC
9615CN
ILA9615PC
•
Ordering Information
FAIRCHILD
A Schlumberger Company
Device Identification
Three basic units of information are contained in the
ordering code.
fLA741
Device Type
T
Package Type
All Fairchild standard catalog linear circuits will be
marked as shown in the following example.
C
Temperature Range
fLA710DC
F Date Code
Device Type
This group of alpha numeric characters defines the device
including functional and electrical characteristics, alpha
suffixes are added to further delineate electrical options.
Package Type
One alpha suffix represents the basic package style.
D
Dual In-line (Hermetic, Ceramic)
F
Flatpak (Hermetic)
H
Metal Package
J
Dual In-Line (Side Brazed)
K
Metal Power Package (TO-3)
P
Dual In-Line (Molded)
8-lead DIP (Hermetic, Ceramic)
R
S
Metal Package (Hybrid only)
T
8-lead DIP (Molded)
Power Package (Molded, TO-220)
U
U1 = Power Package (Molded)
W = Molded Package (TO-92 Outline)
Different outlines exist within each package style to
accommodate various die sizes and number of leads.
Specific dimensions for each package can be found in the
Package Outline section of this catalog, listed by online
code. These specific codes are referenced on each data
sheet.
Temperature Range
One alpha suffix represents one of the following three
basic temperature grades in common use. Exact values
and conditions are specified on the device data sheets.
c
~
Commercial
M
O°C to + 70/75°C
Military
- 55°C to + 125°C
-55°Cto + 85°C
v
~
Industflal
- 20°C to 85°C
-40°Cto +85°C
Examples
fLA741 FM This number code indicates a fLA741
Operational Amplifier in a flatpak with military
temperature rating capability.
fLA725EHC This number code indicates a fLA725
Instrumentation Operational Amplifier, electrical option
E, in a metal package with a commercial temperature
rating capability.
1-10
FAIRCHILD
A Schlumberger Company
2-2
Voltage Regulator
Testing
FAIRCHILD
A Schlumberger Company
Linear Products
Testing Voltage Regulators
All Fairchild voltage regulators are factory-tested with
automated equipment to ascertain that they meet or
exceed guaranteed specifications. The testing
equipment operates at relatively high speeds and
automatically measures output voltage tolerances,
line and load regulation, quiescent current, shortcircuit current, and a long list of other voltage
regulator parameters. To adequately interpret
published voltage regulator specifications, it is
advisable to have some understanding of the testing
as performed at Fairchild. This is also important for
customer incoming inspection, as some correlation is
necessary between factory testing and customer
acceptance testing.
Fairchild must be established. In this case, the
temperature coefficients of each regulator type
must be considered.
3-Termlnal Regulators
Testing of 3-terminal regulators is performed at input
voltages that reflect actual use conditions. The
input-output voltage differential considers all of the
variations associated with nominal, unregulated power
supplies. For example, a 12 V regulator (/tA7812)
test uses a 7 V I/O voltage differential and considers
the following parameters.
Device Input/Output Voltage Differential-2 V Nom.
Line Voltage Reference-10%
Filtered Supply Ripple-100f0
Line Regulation-1 0%
Diode Drop and Source Impedance
Variations-1 V
Individual parameter tests performed on Fairchild
voltage regulators require only a few milliseconds, so
a complete regulator test can be accomplished in a
fraction of a second. Such short testing times mean
that the device junction temperature is very close to
ambient. If the devices were tested under steadystate conditions, costs would unfortunately increase,
and the increased expense would be passed on to the
customer. Consequently, published parameters are
based on fast testing and usually specified with a
constant junction temperature of 25°C. Exceptions are
noted in the individual data sheet tables.
This is expressed in the following equation.
VIN
= VOUT(max) + (VIN - VOUT) + Ripple
+ Line Reg + Vo
= 12.6V+2V+ 1.46V+ 1.6V+ 1 V
= 18.66 V
A 12 V regulator, then, is not only tested with a guard
band, but the input voltage range used allows for
greater variation than is present in actual operating
conditions. All Fairchild 3-terminal regulator tests are
based on similar practical considerations.
When a regulator is operated with high dissipation,
however, the effect of temperature drift must be
evaluated or at least considered. For example, a
/tA7805 1 ampere positive voltage regulator with a
junction temperature of 25°C, a 10 V input, and a load
current variation of 1.5 A has a guaranteed load
regulation of less than 50 mV for military-grade units
and less than 100 mV for commercial-grade units.
Under steady-state testing conditions, as opposed
to pulsed testing conditions, junction temperature
would increase by 30°C to 55°C (based on a
4°C/W junction-to-case thermal resistance and
an infinite heat sink.) The /tA7805 regulator has a
temperature coefficient of -1.1 mV / °C, so a 30°C
junction-temperature increase means an output
voltage drift of -33 mY. This drift must be
considered if load regulation is being measured under
steady-state conditions.
Figure 2-1 shows a self-contained load-pulsing circuit
that can be used for measuring load regulation of
either a positive or negative regulator. The /tA555
timer operates in the astable mode as a free-running
multivibrator. Transistors 02 and 04, along with the
load resistors RL, provide the required loading across
the regulator outputs. The on and off times of 02 and
04 are set by potentiometers R2 and R4. Transistors
02 and 04 must be capable of handling the load
current levels to be measured. Line regulation of
positive or negative regulators can be measured using
the circuits in Figure 2-2. Here a pulse generator
switches the input voltages between VIN (min) and
VIN (max) but a similar arrangement could be used by
substituting a /tA555 timer for the pulse generator.
Incoming inspection tests should accommodate these
conditions. One approach would be to duplicate the
testing procedure used by manufacturing; i.e.,
maintain a constant junction temperature of 25°C. If
steady-state testing is performed during acceptance
evaluation, a correlation between the method used
in incoming inspection and the method used by
2-3
Fig.2-1
Self-Contained Load Regulation Test Circuit for Positive or Negative Regulators
POSITIVE
7T035V
ON
~A78M05
OUT
INPUT
+S.
o
+
C1
IOOpF
o
o
r---J----,
••
posmVE ON
260 k NEGATIVE OFF
COM
C'
01.uF
C3
03,1.1F
.,
I
'.3·~
~k
AL+
.....
I
II
(+1
I
MONITOR
I
..l. VOUl
+
SOD /.IF
-----------.,
o
Q4
..-
+
CO
ON
p.A78M05
.,
o
0
IL
o
NEQATIVE
INPUT
Line Regulation Test Circuits
a. For Positive Regulators
VON (MAX) - - - - - - - - - -.....-....,
390
{l
p---t IN R:g~~~~~R
VON ( M I N ) - - - - - - I ) I - - - - + -............
OUT 1--....- -....-
COM
0.J'l.
TO PULSE
RL
GENERATOR
b. For Negative Regulators
50 {l
+
100 {l
0"'1.1"
270 pF
TO PULSE
GENERATOR
390 II
....-t)t-- -VON (MIN)
L . . . - -.....- - - - V O N (MAX)
2·4
1
~F
RL
+ Vour
0
:
___ ,IN ____ .JI
o
o
-5.
SCOPE
TRIGGERING
Fig. 2-2
I
r---.J----,
I
COM
I
24n
OUT
o
I
I
I
- ~ -. -1 OUT R:~~~!~~R
C'
1._
COM
-7 TO-35Y
I
:
I
I
IL.. ___COM
-, ____ J I
.l. VOUT (-)
MONITOR
C'
IN
- ~ - -r - ~ OUT R:g~~~i~A
1k
Ripple Rejection
Ripple rejection is the ratio (in dB) of the regulator
input ac component (or the output of the sine wave
generator) to the output ac component of the device
under test. Its measurement is quite straightforward.
The 5 k potentiometers in both circuits provide the
bias necessary to produce the dc level of the input
voltage to the regulator. The sine-wave generators are
used to produce the ac component of the regulator
input voltage.
Ripple rejection of Fairchild regulators is normally
specified at a load current of 30 to 50% of the rated
output of the device. This is more realistic than the
20 mA or so specified by some other manufacturers.
A regulator with good ripple rejection at low output
currents maY.not necessarily maintain this feature at
moderate-to-high current levels unless special effort
is made during the layout of the integrated circuit to
keep the reference circuit on isotherms (equal
temperature lines) and away from the heat source
(series-pass element).
Life Test and Burn-In (See Figure 2-4)
Burn-in information is provided here as a guide to
perform regulator life testing. The burn-in performed
by Fairchild is based on the thermal resistance of the
regulator package. The power dissipation level is
selected so that the junction temperature is near the
maximum specified level (150°C for most products).
The power level is then determined based on the
chosen ambient. In general, burn-in is performed at
25°C ambient without a heat sink but it can also be
done with a heat sink or a different ambient.
Figure 2-3 shows two simple circuits for measuring
ripple rejection of positive and negative regulators.
Fig. 2-3
Ripple Rejection Measurement Circuits
a. For Positive Regulators
+
5k
2N6123
SINE WAVE
GENERATOR
+-----p__--1IN
R;2~~~~~R
OUT
1-----1p-----1~- VOUT
COM
1k
RL+
b. For Negative Regulators
+
Fig.2-4
Burn-In Circuit for ILA7805 Regulator In TO-220 Package
IN
.33 ~F
7805
COM
1
2-5
OUT
;
0.1
~F
RL
30 II
Example: Determine a burn-in circuit, operating at a
25°C ambient, for a ILA7805 in the TO-220 package.
From the data sheet:
OJA = 65°C/W max
TJ (max) - TA
Po = -"---;;-OJ-A--'-
Note that the value of the load resistor chosen here
(30 fl) is arbitrary. Any other value giving output
currents within the rating of the device could be used.
If the burn-in is to be performed at more than one
temperature, selecting a common load resistor for all
temperatures and changing the input voltage to give
the required power dissipations simplifies the design
and construction of the burn-in fixtures.
1506~ 25 = 1.92 W
If RL = 30 fl and the effects of 10 are neglected,
Po
= (VIN -
VOUT
VOUT)
RL
or
VIN = Po
RL
-VOUT
+ VOUT = 16.5 V
If the same circuit is used at an ambient of 125 0 C,
VIN = Po
RL
VOUT
+ V OUT
150-125
X
65
30
5
+5
= 7.3 V
2·6
Thermal Considerations
FAIRCHILD
A Schlumberger Company
To fully utilize the various available regulator
packages, sufficient attention must be paid to proper
heat removal. For efficient thermal management, the
user must rely on important parameters supplied by
the manufacturer, such as junction-to-case and
junction-to-ambient thermal resistance and maximum
operating junction temperature. The device
temperature depends on the power dissipation level,
the means for removing the heat generated by this
power dissipation and the temperature of the body
(heat sink) to which this heat is removed.
Thermal Evaluation Of Regulators
To measure thermal resistance, the difference
between the junction temperature and the chosen
reference temperature, case, sink or ambient, must be
determined. Ambient or sink temperature
measurement is straightforward. For casetemperature measurement, the device should have a
sufficiently large heat sink and the power level should
be close to the specified rating of the package-die
combination. The case or tab temperature can be
measured by an infrared microradiometer or by using a
thermocouple soldered to a point in the center of the
case or tab at the tab-heat-sink interface as close to
the die as practical.
Figure 6- t shows a simplified equivalent circuit for a
typical semiconductor device in equilibrium. The
power diSSipation, which is analogous to current flow
in electrical terms, is caused by a heat source similar
to a voltage source. Temperature is analogous to
voltage potential and thermal resistance to ohmic
resistance. Extending the analogy of Ohm's law to
OJA(tot)
= 0JC + OCS + USA =
Measurement of the junction temperature,
unfortunately, is not as simple and involves some
calibrations. There are several methods available for
junction-temperature measurement; the two most
commonly used are described here.
TJ - TA
Po
Thermal Shutdown Method
With this method, the thermal shutdown temperature
of each device is used as the thermometer in
determining the thermal resistance. The device is first
heated externally, with as little internal power
dissipation as practical, until it reaches thermal
shutdown. Then, with the device mounted on a heat
sink, the regulator is powered externally until it
reaches thermal shutdown again. With some
packages, the ambient of the device and its heat sink
may have to be elevated sufficiently to force the
regulator into shutdown. The thermal resistance of the
device can then be calculated by using
Thermal resistance, then, is the rise in the
temperature of a package above some reference level
per unit of power dissipation in that package, usually
expressed in degrees centigrade per watt. The
reference temperature may be ambient or it may be
the temperature of a heat sink to which the package is
connected. There are several factors that affect
thermal resistance including die size, the size of the
heat source on the die (series-pass transistor in an Ie
regulator), die-attach material and thickness,
leadframe material, construction and thickness.
Fig. 6·1.
TJ - TC
Po
Simplified Thermal Circuit
where 0JC is the junction-to-case thermal resistance
TJ is the measured thermal shutdown
temperature
TC is the measured case temperature
Po is the power dissipated to force the device
into shutdown and is equal to
.--_ _ _ _,,.. _ _ _..... TJ JUNCTION TEMPERATURE
POWER (P)
8JC JUNCTION-TO-CASE
THERMAL RESISTANCE
Tc CASE TEMPERATURE
HEAT
SOURCE
8CS CASE·TO-SINK
THERMAL RESISTANCE
(V IN - VOUT) lOUT
TS SINK TEMPERATURE
+ VIN 10
10 is the quiescent current of the device and
can be neglected for low thermal resistance
packages such as the TO-3 and TO-220.
8SA SINK-TO-AMBIENT
THERMAL RESISTANCE
'--_ _ _ _ _ _ _ _. . TA AMBIENT TEMPERATURE
2·7
•
Substrate or Isolation Diode Method
The second method of thermal-resistance
measurement utilizes the isolation diodes within the
integrated circuits as temperature sensing element' .
Under normal operating conditions. the substrate
diodes are reverse biased and separate or "isolate"
active as well as passive components within an
integrated circuit. (See Figure 6-2). When the
regulator is reverse biased and a constant current is
forced through the device between the input terminal
and ground. the substrate diodes become forward
biased; naturally. when the forward drop is measured.
the diode with the highest temperature (lowest
forward drop) is detected. Measurement of the
thermal resistance of the regulator then involves two
steps:
Measuring the junction temperature. The device is
powered through a switching circuit S 1 at a duty
cycle greater than 99% (Figure 6-3); thus the device
is electrically heated until it reaches equilibrium.
During short measuring intervals « 1% duty cycle).
the switching circuit de-energizes the device and
the forward drop of the substrate diode is measured
at the previously calibrated ISUBS current level. This
voltage drop must be measured as soon as possible
(several microseconds) after the removal of the
power pulse to avoid inaccurate readings due to
cooling of the chip. Diode 01 prevents reverse
current from flowing through the load resistor RL
during the substrate-diode measuring interval. Since
the change in the isolation diode drop is assumed to
be linear with temperature. the measured voltage
drop can be converted to its corresponding junction
temperature by interpolation or extrapolation.
Thermal resistance can then be calculated by the
same formula used in the thermal-shutdown method.
Calibrating the substrate diode at a fixed ISUBS
level in an oven or bath at two temperatures.
preferably near the device operating junction
temperature. It is assumed that this voltage drop
changes linearly with temperature.
Heat Sink Requirements
When is a heat sink necessary. and what type of a
heat sink should one use? The answers to these
questions depend on reliability and cost requirements.
Heat sinking is necessary to keep the operating
junction temperature TJ of the regulator below the
'For more detailed explanation of this method, see Fairchild
Application Note 205, "Thermal Evaluation of Integrated
Circuits". For p,A723 thermal considerations, see page 3·29.
Fig, 6-2
Monolithic Transistor Isolation
COLLECTOR
SUBSTRATE DIODES
+
+
SUBSTRATE
EMIITER
EM lITER
Equivalent Circuit
Cross-sectional Diagram Showing Two Monolithic
Transistors Isolated by Substrate Diodes
Fig, 6-3
Thermal ReSistance Measurement Circuit Using Substrate Diode Technique
+
ISUBS
VOUT
DUT
OUTPUT 1--+--0
D1
COMMON
2-8
COLLECTOR
specified maximum value. Since semiconductor
reliability improves as operating junction temperature
is lowered, a reliability I cost compromise is usually
made in the device design.
TJ(max)-Maximum operating junction temperature,
specified by the manufacturer.
OJC, OJA-Junction-to-case and junction-to-ambient
thermal resistance values, also specified
by the regulator manufacturer.
Ocs-Case-to-heat-sink thermal resistance which, for
large packages, can range from about 0.2°C/W
to about 1°C/W depending on the quality of the
contact between the package and the heat sink.
0SA-Heat-sink-to-ambient thermal resistance,
specified by heat-sink manufacturer.
Table 6-1 is a tabulation by package of the various
regulators available from Fairchild. It also lists the
average and maximum values of thermal resistance for
the regulator chip-package combinations and can be
used as a guide in selecting a suitable package when
designing a regulator circuit.
Maximum permissible dissipation without a heat sink
is determined by
Thermal characteristics of voltage-regulator chips and
packages determine that some form of heat sinking is
mandatory whenever the power dissipation exceeds
the following.
0.67 W for the TO-39 package
0.69 W for the TO-92 package
1.56 W for the Mini Batwing and Power Watt (similar to
TO-202) packages
1.8 W for the TO-220 package
2.8 W for the TO-3 package
If the device dissipation Po exceeds this figure, a heat
sink is necessary. The total required thermal
resistance may then be calculated.
OJA(tot)
at 25°C ambient or lower power levels at ambients
above 25°C.
= OJC + OCS + OSA =
TJ(max) - TA(max)
Po
Case-to-sink and sink-to-ambient thermal resistance
information on commercially available heat sinks is
normally provided by the heat sink manufacturer. A
summary of some commercially available heat sinks is
shown in Table 6-2. However, if a chassis or other
conventional surface is used as a heat sink, Figure 6-4
can be used as a guide to estimate the required
surface area.
To choose or design a heat sink, the designer must
determine the following regulator parameters.
PO(msx)-Maximum power dissipation: (V IN - VOUT)
lOUT + VIN 10
TA(max)-Maximum ambient temperature the regulator
will encounter during operation.
Fig. 6-4
TJ(max) - TA(max)
OJA
Po (max) =
Heat Sink Material Selection Guide
SURFACE AREA
(SOTH SIDES OF THE HEAT SINK)
SQUARE INCHES
1IIIIIIIIIIiiliilIIIIII 111I1I11I1I11I1I1iiI~ 1111111111"11111111111111111111111111111111111111111111111111111
3
4
:
3/32"
6
7
7 6
7
65
5
44
3
40 5060
251 5
3 2
6543
215
6
3
5
4
80
2
1
1
25
11111111111111111111111111111111111 11111111
3/32"
II
2
III I
I
7
6
8
5
76
4
5
3
4
25
35
2
3252
1IIIljllllllllllWllllllllillillllllliJillllllllllllililliti
3/32"
1"11111111"111"111""1""1"1111111 II I I I I II III
3/16"
/
66
5 5
4
4
111111111 Ii 1111111 111111111111111
;
II
5
32 6 2 5 2 2
II I I I II I " 111111
THERMAL RESISTANCE IN °C/W
To determine either area reqUired or thermal resistance of a given area, draw
a vertical line between the top (or area) hne down to the mateflal 01 interest.
2-9
COPPER.
HORIZONTALLYMOUNTED
COPPER.
VERTICALLYMOUNTED
I
111111111111111111111111111111111111111111 II 1111111
3/16"
3/32"
20 2530
11111111"111"111111"1111111111"1"111111111111111111111 I
7
THICKNESS
THICKNESS
15
1IIIIIlillhliillllllllllllllllllllllllllllllllllili I 11111111
3/16"
THICKNESS
8 10
11111111111111111111111111111111111111111111111111111111111111111 I I ! III
3/16"'
THICKNESS
5
ALUMINUM.
HORIZONTALLYMOUNTED
ALUMINUM.
VERTICALLY MOUNTED
Table 6-1
Thermal Resistance (liJC, liJA) By Device and Package'
Resistances Listed as Follows:
liJC (TVP) liJC (MAX) In 0C/W
liJA (TVP) liJA (MAX)
Reg,Type
Pos,
3-Term
Neg.
3-Term
lOUT
(A)
~A78LXX
0.1
~A78MXX
0.5
~A 109, ~A209
~A309, 5 V
1
~A78XX
1
3.5 5.5
40 45
78H05, 5 V
5
1.52.0
37 40
~A78HXX
5
2.0 2.5
32 38
~A79MXX
0.5
~A79XX
1
~A1051
Pos.
Adj.
to
~A723
0.125
~A78MG
0.5
4-TERM
4-TERM
~A79MG
0.5
~A79G
Power
Watt
U1'
1
TO-39
H
20
40
140 190
3.05.0
62 70
18
25
120 185
3.5 5.5
40 45
3.0 5.0
60 65
3.0 5.0
62 70
18
25
120 185
3.0 5.0
60 65
3.5 5.5
40 45
8
6
7580
4.0 6.0
4447
1
5
4-TERM.
TO-220
U
0.045
~A78HG
4-TERM.
4-Lead
TO-3
K
0.012
305/376
~A78G
Neg.
Adj.
TO-3
K
Device
No.!Series
6
8
7580
2.0 2.5
32 38
6
8
7580
4.0 6.0
44 47
Note
'Similar to TO-202
2-10
8
6
7580
4-Lead
TO-39
H
TO-92
W
-
TO-99
8-Lead TO-S
H
TO-100
10-Lead TO-S
H
TO-116
14-Pin Plastic
0
TO-116
14-Pin Ceramic
0
8 Pin
Minidip
T
-
160 180
•
-
25
40
150 190
-
160 190
-
25
50
150 190
-
150 190
18
25
125 185
25
18
125 185
2-11
-
-
125 160
When using larger packages, be sure the heat sink
surface is flat and free from ridges or high spots.
Check the regulator package for burrs or peened-over
corners. Regardless of the smoothness and flatness
of the package and heat-sink contact, air pockets
between them are unavoidable unless a lubricant is
used. Therefore, for good thermal conduction, use a
thin layer of thermal lubricant such as Dow Corning
DC-340, General Electric 662 or Thermacote
by Thermalloy.
How to Choose a Heat Sink-Example
Determine the heat sink required for a regulator which
has the following system requirements:
Operating ambient temperature range: 0°C-60°C
Maximum junction temperature: 125°C
Maximum output current: BOO mA
Maximum input to output differential: 10 V
From Table 6-1, the choice is narrowed down to the
/LA7BOO family, available in TO-3 and TO-220
packages. The TO-220 package is sufficent (lower
cost, better thermal resistance).
OJe
In some applications, especially with negative
regulators, it is desirable to electrically insulate the
regulator case from the heat sink. Hardware kits for
this purpose are commercially available for such
packages as the TO-3 and TO-220. They generally
consist of a 0.003 to 0.005 inch thick piece of mica or
bonded fiberglass to electrically isolate the two
surfaces, yet provide a thermal path between them.
As expected, the thermal resistance will increase but,
as in the direct metal-to-metal joint, some
improvement can be realized by using thermal
lubricant on each side of the mica.
= 5°C/W maximum (from data sheet
or Table 6-1)
BJA(tot) = OJC
Bes
+ OSA =
+ OCS + BSA =
125 - 60
O.B X 10 - 5 = 3.13°C/W
Assuming Bes = 0.13°C/W then BSA = 3°C/W
If the regulator is mounted on a heat sink with fins, the
most efficient heat transfer takes place when the fin is
in a vertical plane, as this type of mounting forces the
heat transfer from fin to air in a combination of
radiation and convection.
This thermal resistance value can be achieved by
using either 22 square inches of 3/16 inch thick
vertically mounted aluminum (Figure 6-4) or a
commercial heat sink (Table 6-2).
Tips for Better Regulator Heat Sinking
Avoid placing heat-dissipating components such as
power resistors next to regulators.
If it is necessary to bend any of the regulator leads,
handle them carefully to avoid straining the package.
Furthermore, lead bending should be restricted since
repeated bending will fatigue and eventually
break the leads.
When using low dissipation packages such as TO-5,
TO-39, and TO-92, keep lead lengths to a minimum
and use the largest possible area of the printed board
traces or mounting hardware to provide a heat
dissipation path for the regulator.
Table 6-2. Heat Sink Selection Guide
This list is only representative. No attempt has been made to provide a complete list of all heat sink manufacturers.
All values are typical as given by manufacturer or as determined from characteristic curves supplied by
manufacturer.
BSA Approx.
(OC/W)
TO-3 Packages
0.4 (9" length)
0.4-0.5 (6"
length)
0.56-3.0
0.6 (7.5" length)
0.7-1.2 (5-5.5"
length)
1.0-5.4 (3"
length)
0SA Approx.
(OC/W)
Manufacturer and Type
1.9
2.1
2.3-4.7
4.2
4.5
Thermalloy (Extruded) 6590
Series
Thermalloy (Extruded) 6660, 6560
Series
Wakefield 400 Series
Thermalloy (Extruded) 6470
Series
Thermalloy (Extruded) 6423,
6443, 6441, 6450 Series
Thermalloy (Extruded) 6427,
6500,6123,6401,6403,6421,
6463,6176,6129,6141,6169,
6135, 6442 Series
4.B-7.5
5-6
5-10
5.6
5.9-10
6
6.4
6.5-7.5
B
2-12
Manufacturer and Type
IERC E2 Series (Extruded)
IERC E 1, E3 Series (Extruded)
Wakefield 600 Series
IERC HP3 Series
Staver V3-5·2
Thermalloy 6001 Series
IERC HP3 Series
Thermalloy 6013 Series
Staver V3-3-2
Wakefield 6BO Series
Wakefield 390 Series
Staver V3-7-224
IERC UP Series
Staver Vl-5
Table 6-2. (Cont.)
8SA Approx.
(OC/W)
8SA Approx_
(OC/W)
Manufacturer and Type
8.1
8.8
9.5
9.5-10.5
9.8-13.9
10
11
Staver V3·5
Staver V3·7·96
Staver V3·3
IERC LA Series
Wakefield 630 Series
Staver Vl-3
Thermalloy 6103, 6117 Series
TO-220 Packages
4.2
5-6
6.4
6.5-7.5
7.1
8.1
8.8
9.5
10
12.5-14.2
13
15
15.1-17.2
16
18
19
20
20
25
(See Note 1)
IERC HP3 Series
IERC HP 1 Series
Staver V3-7-225
IERC VP Series
Thermalloy 6070 Series
Staver V3-5
Staver V3-7-96
Staver V3-3
Thermalloy 6032, 6034 Series
Staver V4-3-192
Staver V5-1
Thermalloy 6030 Series
Staver V 4-3-128
Thermalloy 6072,6106 Series
Thermalloy 6038,6107 Series
IERC PB Series
Staver V6-2
Thermalloy 6025 Series
IERC PA Series
TO-92 Packages
30
46
50
57
65-5
72
85
Staver F2-7
Staver F5-7A, F5-8-1
IERC RUR Series
Staver F5-7D
IERC RU Series
Staver Fl-7
Thermalloy 2224 Series
Mini Batwing
10
10.6
11.7
13
20
26
Thermalloy
Thermalloy
Thermalloy
Thermalloy
Thermalloy
Thermalloy
6069
6068
6067
6066
6062
6064
Manufacturer and Type
TO-S and TO-39 Packages
Thermalloy 1101, 1103 Series
12
Wakefield 260-5 Series
12-16
15
Staver V3A-5
Thermalloy 1116, 1121, 1123
22
Series
Thermalloy 1130, 1131, 1132
22
Series
Staver F5-5C
24
Thermalloy 2227 Series
25
IERC Thermal Links
26-30
Wakefield 200 Series
27-83
Staver F5-5B
28
Thermalloy 2228 Series
34
IERC Clip Mount Thermal Link
35
Thermalloy 2215 Series
39
Thermalloy 2205 Series
41
Staver F5-5A
42
Wakefield 296 Series
42-65
Staver F6-5, F6-5L
46
50
Thermalloy 2225 Series
IERC Fan Tops
50-55
Thermalloy 2211 Series
53
Thermalloy 2210 Series
55
Thermalloy 1129 Series
56
Thermalloy 2230, 2235 Series
58
Thermalloy 2226 Series
60
Staver Fl-5
68
72
Thermalloy 1115 Series
Power Watt (similar to TO-202)
Packages (See Note 2)
12.5-14.2
Staver V4-3-192
Thermalloy 6063 Series
13
13
Staver V5-1
15.1-17.2
Staver V4-3-128
19
Thermalloy 6106 Series
20
Staver V6-2
24
Thermalloy 6047 Series
25
Thermalloy 6107 Series
37
IERC PAl-7CB with PVC-1B Clip
40-42
Staver F7-3
40-43
Staver F7-2
IERC PA2-7CB with PVC-1B Clip
42
42-44
Staver F7-1
Series
Series
Series
Series
Series
Series
Notes
1. Most TO-3 heat sinks can also be used with TO-220 packages
with appropriate hole patterns.
2. Most TO-220 heat sinks can be used with the Power Watt
package.
IERC: 135 W. Magnolia Blvd., Burbank, CA 91502
Staver Co., Inc.: 41-51 N. Saxon Ave., Bay Shore, N.Y. 11706
Thermalloy Inc.: 2021 W. Valley View Lane, Dallas, TX 75234
Wakefield Engineering, Inc.: Audubon Rd., Wakefield, MA 01880
2·13
•
J-LA 7800 Series
3-Terminal Positive
Voltage Regulators
FAIRCHIL.D
A Schlumberger Company
Linear Products
Connection Diagram
TO-3 Package
Description
The /LA7800 series of monolithic 3-Terminal Positive
Voltage Regulators is constructed using the Fairchild
Planar epitaxial process. These regulators employ
internal current-limiting, thermal-shutdown and safearea compensation, making them essentially
indestructible. If adequate heat sinking is provided,
they can deliver over 1 A output current. They are
intended as fixed voltage regulators in a wide range of
applications including local (on card) regulation for
elimination of distribution problems associated with
single point regulation. In addition to use as fixed
voltage regulators. these devices can be used with
external components to obtain adjustable output
voltages and currents.
•
•
•
•
•
•
•
COMMON 3
(Top View)
Order Information
Type
Package
/LA7805
Metal
/LA7806
Metal
/LA7808
Metal
/LA7812
Metal
/LA7815
Metal
/LA7818
Metal
/LA7824
Metal
/LA7805C
Metal
/LA7806C
Metal
/LA7808C
Metal
IlA7812C
Metal
/LA7815C
Metal
/LA7818C
Metal
/LA7824C
Metal
OUTPUT CURRENT IN EXCESS OF 1 A
NO EXTERNAL COMPONENTS
INTERNAL THERMAL OVERLOAD PROTECTION
INTERNAL SHORT CIRCUIT CURRENT LIMITING
OUTPUT TRANSISTOR SAFE-AREA
COMPENSATION
AVAILABLE IN THE TO-220 AND THE
TO-3 PACKAGE
OUTPUT VOLTAGES OF 5,6,8,8.5,12,15,18,
AND 24 V
Absolute Maximum Ratings
Input Voltage (5 V through 18 V)
(24 V)
Internal Power Dissipation
Storage Temperature Range
Operating Junction
Temperature Range
/LA7800
IlA7800C
Pin Temperature
Soldering, 60s time limit
TO-3 Package
Soldering, 10s time limit
TO-220 Package
~
35 V
40 V
Interna"y Limited
-65°C to +150°C
Code
HJ
HJ
HJ
HJ
HJ
HJ
HJ
HJ
HJ
HJ
HJ
HJ
HJ
HJ
Connection Diagram
To-220 Package
r
Part No.
/LA7805KM
/LA7806KM
IlA7 808KM
/LA7812KM
/LA7815KM
/LA7818KM
/LA7824KM
/LA7805KC
/LA7806KC
IlA7 808KC
/LA7812KC
/LA7815KC
/LA7818KC
/LA7824KC
OUTPUT
~II~
i 2'0..0.
-55°C to +150°C
O°C to +125°C
~-
~ INPUT
'---COMMON
(Side View)
Order Information
Type
Package
/LA7805C
Molded Power
/LA7806C
Molded Power
/LA7808C
Molded Power
IlA7885C
Molded Power
/LA7812C
Molded Power
/LA7815C
Molded Power
IlA7818C
Molded Power
IlA7824C
Molded Power
2-14
Pack
Pack
Pack
Pack
Pack
Pack
Pack
Pack
Code
GH
GH
GH
GH
GH
GH
GH
GH
Part No.
IlA7805UC
IlA7806UC
/LA7808UC
/LA7885UC
/LA7812UC
IlA7815UC
/LA7818UC
/LA7824UC
,."A7800 Series
EqUlval.nt~c:lr~c:u:lt~______-t-______lr-___Jr:-:-=-T___r_'NPuT (1)
2-15
#LA7800 Series
~A7805
Electrical Characteristics
=
=
VIN
10 V, lOUT
500 mA, -55°C ~ TJ ~ 150°C, CIN
unless otherwise specified.
= 0.33 ~F, COUT = 0.1 ~F,
Characteristic
Condition (Note)
Min
Typ
Max
Unit
Output Voltage
TJ
= 25°C
TJ = 25°C
4.8
5.0
5.2
V
50
mV
Line Regulation
= 25°C
7V
~
VIN
~
25 V
3
8V
~
VIN
~
12 V
1
25
mV
5 mA ~ lOUT ~ 1.5 A
15
100
mV
250 mA ~ lOUT ~ 750 mA
5
25
mV
5.35
V
Load Regulation
TJ
Output Voltage
8.0 V ~ VIN ~ 20 V
5 mA ~ lOUT ~ 1.0 A
P ~ 15W
Quiescent Current
TJ
Iwith line
Quiescent Current Change I
with load
= 25°C
6.0
mA
8 V ~ VIN ~ 25 V
4.2
0.8
mA
5 mA ~ lOUT ~ 1.0 A
0.5
mA
40
~V/VOUT
= 25°C,
10 Hz ~ f ~ 100 kHz
Output Noise Voltage
TA
Ripple Rejection
= 120 Hz, 8 V ~ VIN ~
lOUT = 1.0 A, TJ = 25°C
f = 1 kHz
TJ = 25°C, VIN = 35 V
TJ = 25°C
f
Dropout Voltage
Output Resistance
Short-Circuit Current
Peak Output Current
Average Temperature Coefficient of
Output Voltage
~A7805C
Electrical Characteristics
4.65
lOUT
18 V
8
78
68
2.0
1.3
0.75
1.2
A
2.2
3.3
A
0.4
mV/oC/
0.3
VOUT
1-550 C ~ TJ ~ +25°C
=
VIN
10 V, lOUT 500 mA, O°C ~ TJ ~ 125°C, CIN
unless otherwise specified.
V
mQ
17
= 5 mA I+25°C ~ TJ ~ +150°C
=
dB
2.5
= 0.33 ~F, COUT = 0.1 ~F,
Characteristic
Condition (Note)
Min
Typ
Max
Unit
Output Voltage
= 25°C
TJ = 25°C
4.8
5.0
5.2
V
Line Regulation
TJ
= 25°C
7 V ~ VIN ~ 25 V
3
100
mV
8 V ~VIN ~ 12 V
1
50
mV
5 mA ~ lOUT ~ 1.5 A
15
100
mV
250 mA ~ lOUT ~ 750 mA
5
50
mV
5.25
V
Load Regulation
TJ
Output Voltage
7 V ~ VIN ~ 20 V
5 mA ~ lOUT ~ 1.0 A
P ~ 15W
Quiescent Current
TJ
Iwith line
Quiescent Current Change I
with load
7V
5 mA ~ lOUT ~ 1.0 A
Output Noise Voltage
TA
100 kHz
Ripple Rejection
f
18 V
Dropout Voltage
Output Resistance
Short-Circuit Current
Peak Output Current
Average Temperature Coefficient of
4.75
= 25°C
~
VIN
4.2
~
25 V
= 25°C, 10 Hz ~ f ~
= 120 Hz, 8 V ~ VIN ~
lOUT = 1.0 A, TJ = 25°C
f = 1 kHz
TJ = 25°C, VIN = 35 V
TJ = 25°C
lOUT'" 5 mA, O°C ~ TJ ~ 125°C
Output Voltage
2·16
62
8.0
mA
1.3
mA
0.5
mA
40
~V
78
dB
2.0
V
17
mQ
750
mA
2.2
A
1.1
mV/oC
J.LA 7800 Series
JLA7806C
Electrical Characteristics
VIN = 11 V, lOUT = 500 mA, O°C ::5 TJ ::5 125°C, CIN
unless otherwise specified.
Typ
Max
Unit
5.75
6.0
6.25
V
5
120
mV
9 V ::5 VIN ::5 13 V
1.5
60
mV
Condition (Note)
Output Voltage
TJ
Load Regulation
= 25°C
TJ
= 25°C
8 V ::5 VIN ::5 25 V
TJ
= 25°C
5 mA ::5 lOUT ::5 1.5 A
14
120
mV
250 mA ::5 lOUT ::5 750 mA
4
60
mV
6.3
V
8.0
mA
8 V ::5 VIN ::5 25 V
1.3
mA
5 mA ::5 lOUT ::5 1.0 A
0.5
mA
Output Voltage
8 V ::5 VIN ::5 21 V
5 mA ::5 lOUT ::5 1.0 A
P ::5 15 W
Quiescent Current
TJ
Quiescent Current Change
IIwith line
with load
5.7
= 25°C
4.3
= 25°C, 10 Hz::5 f::5
= 120 Hz, 9 V ::5 VIN ::5
lOUT = 1.0 A, TJ = 25°C
f = 1 kHz
TJ = 25°C, VIN = 35 V
TJ = 25°C
Output Noise Voltage
TA
100 kHz
Ripple Rejection
f
19 V
Dropout Voltage
Output Resistance
Short-Circuit Current
Peak Output Current
Average Temperature Coefficient of
JLF,
Min
Characteristic
Line Regulation
= 0.33 JLF, COUT = 0.1
lOUT
= 5 mA, O°C
::5 TJ ::5 125°C
Output Voltage
Nole
1. For all tables, all characteristics except nOise voltage and
ripple rejection ratio are measured usong pulse techniques
(tw .:'S 10 ms, duty cycle .:'S 5%). Output voltage changes due
to changes on internal temperature must be taken into account
separately.
2-17
59
45
JLV
75
dB
2.0
V
19
mrl
550
mA
2.2
A
0.8
mV/oC
•
JLA 7800 Series
/LA7808
Electrical Characteristics
=
=
VIN
14 V, lOUT
500 mA, -55°C:::::: TJ :::::: 150°C, CIN
unless otherwise specilied.
= 0.33/LF, COUT = 0.1
/LF,
Characteristic
Condition (Note)
Min
Typ
Max
Output Voltage
TJ
7.7
Line Regulation
= 25°C
TJ = 25°C
Load Regulation
TJ
Output Voltage
11.5 V :::::: VIN :::::: 23 V
5 mA :::::: lOUT:::::: 1.0 A
P:::::: 15 W
Quiescent Current
T.!
6.0
mA
I with line
Quiescent Current Change I
with load
11.5 V :::::: VIN :::::: 25 V
0.8
mA
5 mA :::::: lOUT:::::: 1.0 A
0.5
mA
Output Noise Voltage
TA
40
/LV IVOUT
Ripple Rejection
1
8.0
8.3
V
10.5 V:::::: VIN :::::: 25 V
6.0
80
mV
11 V :::::: VIN :::::: 17 V
2.0
40
mV
5mA::::::loUT:::::: 1.5A
12
100
mV
250 mA :::::: lOUT:::::: 750 mA
4.0
40
mV
8.4
V
Output Resistance
Short-Circuit Current
Peak Output Current
Average Temperature Coefficient 01
Output Voltage
lOUT = 5 mA
=
7.6
= 25°C
4.3
= 25°C, 10 Hz:::::: I:::::: 100 kHz
= 120 Hz, 11.5 V:::::: VIN:::::: 21.5 V
lOUT = 1.0 A, TJ = 25°C
f = 1 kHz
TJ = 25°C, VIN = 35 V
TJ = 25°C
Dropout Voltage
/LA7808C
Electrical Characteristics
= 25°C
Unit
8
62
72
2.0
dB
2.5
16
1.3
1.2
A
2.2
3.3
A
0.4
mV lOCI
0.3
VOUT
I+25°C :::::: TJ :::::: 150°C
=
mQ
0.75
I-55°C:::::: TJ :::::: +25°C
VIN
14 V, lOUT
500 mA, O°C :::::: TJ :::::: 125°C, CIN
unless otherwise specilied.
V
= 0.33/LF, COUT =
0.1 /LF.
Characteristic
Condition (Note)
Min
Typ
Max
Output Voltage
TJ
= 25°C
TJ = 25°C
7.7
8.0
8.3
V
10.5 V :::::: VIN :::::: 25 V
6.0
160
mV
11 V:::::: VIN :::::: 17 V
2.0
80
mV
Line Regulation
Load Regulation
TJ
= 25°C
Unit
5 mA :::::: lOUT:::::: 1.5 A
12
160
mV
250 mA :::::: lOUT:::::: 750 mA
4.0
80
mV
8.4
V
Output Voltage
10.5 V :::::: VIN :::::: 23 V
5 mA :::::: lOUT:::::: 1.0 A
P:::::: 15 W
Quiescent Current
TJ
8.0
mA
I with line
Quiescent Current Change I
with load
10.5 V :::::: VIN :::::: 25 V
1.0
mA
5 mA :::::: lOUT:::::: 1.0 A
0.5
Output Noise Voltage
Ripple Rejection
Dropout Voltage
Output Resistance
Short-Circuit Current
Peak Output Current
Average Temperature Coefficient 01
7.6
= 25°C
4.3
= 25°C, 10 Hz:::::: I:::::: 100 kHz
1 = 120 Hz, 11.5 V :::::: VIN :::::: 21.5 V
lOUT = 1.0 A, TJ = 25°C
1 = 1 kHz
TJ = 25°C, VIN = 35 V
TJ = 25°C
TA
lOUT = 5 mA, O°C:::::: TJ:::::: 125°C
Output Voltage
2·18
56
mA
52
/LV
72
dB
2.0
V
16
mQ
450
mA
2.2
A
0.8
mV/oC
/-LA 7800 Series
/LA7885C
Electrical Characteristics
VIN = 15 V, lOUT = 500 rnA, -55°C :S TJ :S 150°C, CIN
unless otlierwise specilied.
Typ
Max
Unit
8.5
8.85
V
6.0
170
rnV
11 V :S VIN :S 17 V
2.0
85
rnV
TJ
= 25°C
TJ
= 25°C
10.5 V :S VIN :S 25 V
TJ
= 25°C
5 rnA :S IOUT:S 1.5 A
12
170
rnV
250 rnA :S lOUT :S 750 rnA
4.0
85
rnV
8.9
V
8.0
rnA
10.5 V :S VIN :S 25 V
1.0
rnA
5 rnA:S IOUT:S 1.0 A
0.5
rnA
Output Voltage
11 V :S VIN :S 23.5 V
5 rnA:S IOUT:S 1.0 A
P :S 15 W
Quiescent Current
TJ
Quiescent Current Change
IIwith line
with load
TA
1
Output Resistance
Short-Circuit Current
Peak Output Current
Average Temperature Coefficient 01
8.1
= 25°C
4.3
= 25°C, 10 Hz :S 1 :S 100 kHz
= 120 Hz, 11.5 V :S VIN :S 21.5 V
lOUT = 1.0 A, TJ = 25°C
1 = 1 kHz
TJ = 25°C, VIN = 35 V
TJ = 25°C
Output Noise Voltage
Ripple Rejection
Dropout Voltage
= 0.1
Min
Condition (Note)
Output Voltage
Load Regulation
COUT
8.15
Characteristic
Line Regulation
= 0.33/LF,
lOUT
= 5 rnA, O°C
:S TJ :S 125°C
Output Voltage
Note
1 For all tables, all characteristics except noise voltage and
ripple rejection ratio are measured using pulse techniques
(tw S lams, duty cycle s 5%). Output voltage changes due
to changes in internal temperature must be taken into account
separately
2·19
56
55
/LV
70
dB
2.0
V
16
rnQ
/LF,
450
rnA
2.2
A
0.8
rnV/oC
•
f.LA 7800 Series
#L A7812
Electrical Characteristics
VIN = 19 V, lOUT = 500 mA, -55°C
unless otherwise specified.
::s TJ ::s 150°C, CIN = 0.33 #LF, COUT = 0.1 #LF,
Characteristic
Condition (Note)
Min
Typ
Max
Unit
Output Voltage
TJ = 25°C
11.5
12.0
12.5
V
Line Regulation
TJ = 25°C
::s VIN ::s 30 V
::s VIN ::s 22 V
5 mA ::s lOUT ::s 1.5 A
TJ = 25°C
250 mA ::s lOUT ::s 750 mA
15.5 V ::s VIN ::s 27 V
11.4
5 mA ::s lOUT ::s 1.0 A
P ::s 15 W
Load Regulation
Output Voltage
14.5 V
10
120
mV
16 V
3.0
60
mV
12
120
mV
4.0
60
mV
12.6
V
Quiescent Current
TJ = 25°C
I with line
Quiescent Current Change I
with load
::s VIN ::s 30 V
5 mA ::s lOUT ::s 1.0 A
TA = 25°C, 10 Hz ::s f ::s 100 kHz
f = 120 Hz, 15 V ::s VIN ~ 25 V
Output Noise Voltage
Ripple Rejection
4.3
15 V
8
61
lOUT = 1.0 A, TJ = 25°C
2.0
Output Resistance
f = 1 kHz
18
Short-Circuit Current
TJ = 25°C, VIN = 35 V
0.75
Peak Output Current
TJ = 25°C
Average Temperature Coefficient of
::s TJ ::s +25°C
lOUT = 5 mA
I+25°C ::s TJ ::s 150°C
Output Voltage
mA
mA
0.5
mA
40
#LV IVOUT
dB
71
Dropout Voltage
1.3
6.0
0.8
2.2
I-55°C
2.5
V
mQ
1.2
A
3.3
A
0.4
my/oCt
0.3
VOUT
#L A7812C
Electrical Characteristics
VIN = 19 V, lOUT = 500 mA, O°C
unless otherwise specified.
::s TJ::S 125°C, CIN = 0.33 #LF, COUT = 0.1 #LF,
Characteristic
Condition (Note)
Min
Typ
Output Voltage
TJ = 25°C
11.5
12.0
12.5
V
10
240
mV
3.0
120
mV
12
240
mV
4.0
120
mV
12.6
V
8.0
mA
1.0
mA
0.5
mA
Line Regulation
Load Regulation
Output Voltage
::s VIN ::s 30 V
TJ = 25°C
16 V ::s VIN ::s 22 V
5 mA ::s lOUT ::s 1.5 A
TJ = 25°C
250 mA ::s lOUT ::s 750 mA
14.5 V ::s VIN ::s 27 V
11.4
5 mA ::s IOUT::S 1.0 A
P ::s 15 W
14.5 V
Quiescent Current
TJ = 25°C
I with line
Quiescent Current Change I
with load
::s VIN ::s 30 V
5 mA ::s lOUT ::s 1.0 A
TA = 25°C, 10 Hz ::s f ::s 100 kHz
f = 120 Hz, 15 V ::s VIN ::s 25 V
Output Noise Voltage
Ripple Rejection
4.3
14.5 V
75
55
71
Max
Unit
#LV
dB
Dropout Voltage
lOUT = 1.0 A, TJ = 25°C
2.0
V
Output Resistance
f = 1 kHz
18
mQ
Short-Circuit Current
TJ = 25°C, VIN = 35 V
350
mA
Peak Output Current
TJ = 25°C
2.2
A
1.0
mV/oC
Average Temperature Coefficient of
lOUT = 5 mA, O°C
::s TJ ::s 125°C
Output Voltage
2·20
f.LA 7800 Series
~A7815
Electrical Characteristics
VIN = 23 V, lOUT = 500 mA, -55°C :S TJ :S 150°C, CIN = 0.33
unless otherwise specified
~F,
COUT = 0.1
~F,
Characteristic
Condition (Note)
Min
Typ
Max
Output Voltage
TJ = 25°C
14.4
15.0
15.6
V
17.5 V :S VIN :S 30 V
11
150
mV
20 V :S VIN :S 26 V
3
75
mV
5 mA :S lOUT :S 1.5 A
12
150
mV
250 mA :S lOUT :S 750 mA
4
75
mV
15.75
V
6.0
mA
18.5 V :S VIN :S 30 V
0.8
mA
5 mA :S IOUT:S 1.0 A
0.5
mA
40
~V/VOUT
Line Regulation
TJ = 25°C
Load Regulation
TJ = 25°C
Output Voltage
18.5 V :S VIN :S 30 V
5 mA :S lOUT :S 1.0 A
P:S 15 W
Quiescent Current
TJ = 25°C
Quiescent Current Change
IIwith line
with load
14.25
4.4
Output Noise Voltage
TA = 25°C, 10 Hz:s f:S 100 kHz
Ripple Rejection
f = 120 Hz, 18.5 V :S VIN :S 28.5 V
8
60
70
Dropout Voltage
lOUT = 1.0 A, TJ = 25°C
2.0
Output Resistance
f = 1 kHz
19
Short-Circuit Current
TJ = 25°C, VIN = 35 V
Peak Output Current
TJ = 25°C
Average Temperature Coefficient of
Output Voltage
lOUT = 5 mA
dB
2.5
2.2
V
mfl
0.75
1.3
Unit
A
3.3
A
1-550 C :S TJ:S +25°C
0.4
mV lOCI
I+25°C:S TJ :S +150°C
0.3
VOUT
~A7815C
Electrical Characteristics
VIN = 23 V, lOUT = 500 mA, O°C :S TJ :S 125°C, CIN = 0.33 ~F, COUT = 0.1 ~F,
unless otherwise specified.
Characteristic
Condition (Note)
Min
Typ
Max
Unit
Output Voltage
TJ = 25°C
14.4
15.0
15.6
V
Line Regulation
TJ = 25°C
Load Regulation
TJ = 25°C
17.5 V :S VIN :S 30 V
11
300
mV
20 V :S VIN :S 26 V
3
150
mV
5 mA:S IOUT:S 1.5 A
12
300
mV
250 mA :S lOUT :S 750 mA
4
150
mV
15.75
V
Output Voltage
17.5 V :S VIN :S 30 V
5 mA ~ lOUT :S 1.0 A
P:S 15 W
Quiescent Current
TJ = 25°C
8.0
mA
.
Iwith line
QUiescent Current Change I
17.5 V :S VIN :S 30 V
1.0
mA
5 mA :S IOUT:S 1.0 A
0.5
with load
Output Noise Voltage
14.25
4.4
TA = 25°C, 10 Hz:s f:S 100 kHz
mA
90
~V
70
dB
Ripple Rejection
f = 120 Hz, 18.5 V :S VIN :S 28.5 V
Dropout Voltage
lOUT = 1.0 A, TJ = 25°C
2.0
V
Output Resistance
f = 1 kHz
19
mfl
Short-Circuit Current
TJ = 25°C, VIN = 35 V
230
A
Peak Output Current
TJ=25°C
2.1
A
lOUT = 5 mA, O°C :S TJ :S125°C
1.0
mV/oC
Average Temperature Coefficient of
Output Voltage
2·21
54
•
J.LA 7 800 Series
/tA78l8
Electrical Characteristics
=
=
VIN
27 V, lOUT
500 rnA, -55°C :s TJ :s 150°C, CIN
unless otherwise specified.
= 0.33 /.IF, COUT = 0.1
/.IF,
Characteristic
Condition (Note)
Min
Typ
Max
Unit
Output Voltage
TJ
17.3
V
Line Regulation
= 25°C
TJ = 25°C
Load Regulation
TJ
Output Voltage
22 V :s VIN :s 33 V
5 rnA :s IOUT:S 1.0 A
P :s 15 W
Quiescent Current
TJ
Iwith line
Quiescent Current Change I
with load
22 V :s VIN :s 33 V
0.8
rnA
5 rnA :s IOUT:S 1.0 A
0.5
rnA
Output Noise Voltage
TA
40
/.IV /VOUT
Ripple Rejection
f
Output Resistance
Short-Circuit Current
Peak Output Current
Average Temperature Coefficient of
Output Voltage
Electrical Characteristics
18.7
15
180
mV
24 V :s VIN :s 30 V
5.0
90
mV
5 rnA :s lOUT :s 1.5 A
12
180
mV
250 rnA :s lOUT :s 750 rnA
4.0
90
mV
18.9
V
6.0
rnA
lOUT
=
17.1
= 25°C
4.5
= 25°C, 10 Hz:S f:S 100 kHz
= 120 Hz, 22 V :s VIN :s 32 V
lOUT = 1.0 A, TJ = 25°C
f = 1 kHz
TJ = 25°C, VIN = 35 V
TJ = 25°C
Dropout Voltage
/.IA78l8C
= 25°C
18.0
21 V :s VIN :s 33 V
= 5 rnA
8
69
59
dB
V
2.0
22
2.5
mfl
0.75
1.2
A
2.2
3.3
A
1+250 C:S TJ:S +150°C
0.4
mV/oC/
\-55°C :s TJ:S +25°C
0.3
VOUT
1.3
=
VIN
27 V, lOUT 500 rnA, O°C :s TJ :s 125°C, CIN
unless otherwise specified.
= 0.33 /.IF, COUT = 0.1
/.IF,
Characteristic
Condition (Note)
Min
Typ
Max
Unit
Output Voltage
TJ
= 25°C
TJ = 25°C
17.3
18.0
18.7
V
21V:SVIN:S33V
15
360
mV
Line Regulation
24 V :s VIN :s 30 V
5.0
180
mV
5 rnA :s IOUT:S 1.5 A
12
360
mV
250 rnA :s lOUT :s 750 rnA
4.0
180
mV
18.9
V
8.0
rnA
21 V :s VIN :s 33 V
1.0
rnA
5 mA:s IOUT:S 1.0 A
0.5
= 25°C
Load Regulation
TJ
Output Voltage
21 V :s VIN :s 33 V
5 rnA :s IOUT:S 1.0 A
P:S 15 W
Quiescent Current
TJ
Quiescent Current Change
IIwith line
with load
17.1
= 25°C
4.5
rnA
Dropout Voltage
= 25°C, 10 Hz:s f:S 100 kHz
f = 120 Hz, 22 V :s VIN :s 32 V
lOUT = 1.0 A, TJ = 25°C
2.0
V
Output Resistance
f = 1 kHz
22
mfl
Short-Circuit Current
TJ
= 25°C, VIN = 35 V
= 25°C
lOUT = 5 rnA, O°C:S TJ :S125°C
200
rnA
Peak Output Current
TJ
2.1
A
1.0
mV/oC
Output Noise Voltage
Ripple Rejection
Average Temperature Coefficient of
TA
Output Voltage
2·22
53
110
/.IV
69
dB
JLA 7800 Series
~A7824
Electrical Characteristics
=
=
VIN
33 V, lOUT 500 rnA, -55°C :5 TJ:5 150°C, CIN
unless otherwise specified.
= 0.33 ~F, COUT = 0.1 ~F,
Characteristic
Condition (Note)
Min
Typ
Max
Output Voltage
TJ
23.0
24.0
25.0
V
Line Regulation
= 25°C
TJ = 25°C
27 V :5 VIN :5 38 V
18
240
mV
30 V :5 VIN :5 36 V
6
120
mV
Load Regulation
TJ
5 rnA :5 IOUT:5 1.5 A
12
240
mV
250 rnA :5 lOUT :5 750 rnA
4
120
mV
Output Voltage
28 V :5 VIN :5 38 V
5 rnA :5 IOUT:5 1.0 A
P :5 15 W
25.2
V
Quiescent Current
TJ
Quiescent Current Change
IIwith line
with load
4.6
rnA
28 V :5 VIN :5 38 V
rnA
5 rnA :5 lOUT :5 1.0 A
0.5
rnA
40
~V/VOUT
= 25°C, 10 Hz :5 f:5 100 kHz
= 120 Hz, 28 V :5 VIN :5 38 V
lOUT = 1.0 A, TJ = 25°C
f = 1 kHz
TJ = 25°C, VIN = 35 V
TJ = 25°C
TA
f
Output Resistance
Short-Circuit Current
Peak Output Current
Average Temperature Coefficient of
Output Voltage
Electrical Characteristics
= 25°C
6.0
Output Noise Voltage
Dropout Voltage
22.8
0.8
Ripple Rejection
~A7824C
= 25°C
Unit
lOUT
=
= 5 rnA
8
56
66
2.0
dB
2.5
28
V
mO
0.75
1.2
2.2
3.3
A
1-550 C :5 TJ:5 +25°C
0.4
mV/oC/
I+25°C:5 TJ:5 +150°C
0.3
VOUT
1.3
=
VIN
33 V, lOUT 500 rnA, O°C :5 TJ :5 125°C, CIN
unless otherwise specified.
A
= 0.33 ~F, COUT = 0.1
Characteristic
Condition (Note)
Min
Typ
Max
Output Voltage
TJ
= 25°C
TJ = 25°C
23.0
24.0
25.0
V
Line Regulation
= 25°C
27 V :5 VIN :5 38 V
18
480
30 V :5 VIN :5 36 V
6
240
mV
5 rnA :5 IOUT:5 1.5 A
12
480
mV
250 rnA :5 lOUT :5 750 rnA
4
240
mV
25.2
V
TJ
Output Voltage
27 V :5 VIN :5 38 V
5 rnA :5 IOUT:5 1.0 A
P:5 15 W
Quiescent Current
TJ
Iwith line
Quiescent Current Change I
27 V :5 VIN :5 38 V
with load
Ripple Rejection
Dropout Voltage
Output Resistance
Short-Circuit Current
Peak Output Current
Average Temperature Coefficient of
Unit
mV
Load Regulation
Output Noise Voltage
~F,
22.8
= 25°C
4.6
TA
Output Voltage
2-23
rnA
1.0
rnA
0.5
5 rnA :5 IOUT:5 1.0 A
= 25°C, 10 Hz :5 f :5 100 kHz
f = 120 Hz, 28 V :5 VIN :5 38 V
lOUT = 1.0 A, TJ = 25°C
f = 1 kHz
TJ = 25°C, VIN = 35 V
TJ = 25°C
lOUT = 5 rnA, O°C :5 TJ :S125°C
8.0
50
rnA
170
~V
66
dB
2.0
V
28
mO
150
rnA
2.1
A
1.5
mV/oC
•
/-LA 7800 Series
Typical Performance Curves
Worst Case Power Dissipation
Versus Ambient Temperature
(TO-3)
100
I I LIMIT FOR 7,.0"-
50
.0
;0:
I
z
o
~
i
:0 30
20 -6HS
.....
is 20
I.
10
0.5
03
02
'00
eAT SINI(
I
I
z
o
i'-.,
DHs ".. 1$oC/it
.........
25
".\
75
(JHS""IS o
o0
I I I
4 -
OJC
3 -
6JA
5°C/W
65°C/W
: -
T,J
MAi - ','O.C,
2.
50
~
J--
j
'0 ,
FREQUENCY -
5
I
c
I
~f-.
0
i
::::-
B
5
!;
o ~
,
~
.....~
m
I
~ "-~
I I
0
'0
15
20
I
I I
25
INPUT/OutPUT DIFFERENTIAL -
!i!
~o
26
50
75
100 125 160 175
"c
40
E
~,.~INPUT VOLTAGE
30
20
1
I I
w
10
1
"
~
r- -r-
C
OUTPUT VOLTAGE
!i!
I
I
:>
l-
-10
0
-20
10
I- lOUT
ri
!O
20
= 500 mA
OU ; ,
!i!
~
r- f - -
DEYIATION
I-
i!:
:>
I' VI
o
10
V
12
TIME -~.
Quiescent Current as a
Function of
Input Voltage
2
c
I I
E
I
I
l-
i:i
~
= 20 rnA
"" 25°C
:>
...
......
r-f-' !-"'
Ie
:>
g
V
~80~ -
~ou; , ~ v'
f-'LTJ
Z
~
c
f50
E
I-
0
0
\.
.
0
~:;
•
0
/
0
o
'0
20
.0
30
TIME -
~s
2-24
50
60
>
I
w
!:;
=1500 mA
0
~OL~A~E
f-r- OUTP~T
DEVIATION
~
20
Q
=100 mA
1
-2
30
V
~
0
>
1
~
1
25
JUNCTION TEMPERATURE _
~80J -
LOAD CURRENT
w
"
I·" ::::r
( '$0
5
50
Line Transient Response
t+t-
I
I
~
:-.
lj,
DROPOUT CONDITIONS
o-75
z
z
o
r- ~p.::!!.!!!.A
0
~
= 10 V
VouT=5V
.....
<$."
I
~~"
--~~
'OUr ""
I fO ",":0'-
0'
150
I
V'N
7..15
~ ',r..·c
/'
o
:>
Load Transient Response
~I
~
"
1780~-
INPUT VOLTAGE -
Hz
I
I
I'" ~
I
o
o
100 k
Peak Output Current as a
Function of Input/Output
Differential Voltage
r--.
.....
~
0
125
v 'A ~OUT
/ h ~ i',lyIT
o
'" 8 V TO 18 V
"
10
i!:
:>
IJJ",
VOUT '" 5 V
lOUT '" 500 mA
0
100
= 25°C
~
t
'00
-.... ~ ::-
J,VOUT == 5% OF Your
75
!i!
'0
:>
II
~
lill ~5·i, II
I-
I'
!O
Jou, I, ,'v
f-- TJ
w
o
"-
15
Q
I I~"'" f'. ",\
2
J~o~
,.
v"
~
0=---1<0 HEAT
r-r-.
20
~
i:ia:
178xJ_
r-...
..... r-
20
~
'''s~
Dropout Characteristics
w
~
1
I
AMBIENT TEMPERATURE _ °C
a:
"'
0
"r--..
-L:r~
CIW
"c
Ripple Rejection as a
Function of Frequency
'00
0
OHS
o
'.0
'25
'00
25
>
o~
i ',
'\
AMBIENT TEMPERATURE _
oz
~
I"'- ".\
5°C/W
65°CfW
50
I I LIMIT FOR 7800C- I -
, o=-
i
TI""I"iO• C I
1
50
0
30
2o
•
I
'''sl. SOCIIt
"t-
~
O' ,,,
'JC
-
0
o- -.l.
30
(TQ-220)
;0:
10
Dropout Voltage as a
Function of
Junction Temperature
Worst Case Power Dissipation
Versus Ambient Temperature
0
10
15
20
25
INPUT VOLTAGE -
30
V
35
/-LA 7800 Series
Typical Performance Curyes (ConI.)
Output Voltage as a
Function of
Junction Temperature
Current Limiting Characteristics
6
17"~-
178121-
2
12
5
>
1 12 1
w
"~
~
12
....... r-.,
0
~
~
o
3
r--...
..........
t-
VIN
.175
'" 19 V
12 V
'r" 1= 21 mAl
Your
11
50
0
25
o
SO
75
V"
1
I
=0
25
100 125 150 175
'" 10 V
VOUT '"
1=
T"I
o
1
l~!~ I=I,~I~
10
_f-
TC"'08
12
l/
16
20
6
_~" 1= ,:' I
VOUT =
..
E
I
1780~ -
5 V
4 4-loUT '" 500 mA
1
lOUT
~
20 mA
~
«
42
"o
~
4
r- t--
0
~
,
3
1111 I 1111
1 k
10 k
FREQUENCY -
100 k
II
-
g •
lOUT - 500 mA
100
24
A
Quiescent Current as a
Function of Temperature
7~J5
VOUT = 5 V
T,
'" 25"C
C,
= 0 I'F
v
OUTPUT CURRENT -
Output Impedance as a
Function of Frequency
,
5
04
JUNCTION TEMPERATURE _ "C
10
•
....... r-.,
11 9
6
1 M
75
50
Hz
25
0
25
50
75 100 125 150 175
JUNCTION TEMPERATURE _
ac
Note
The other !lA7eOO series devices have similar curves.
DC Parameter Test Circuit
Y,N
0.331'F
0.1 I'F
Although the internal power dissipation is limited, the
junction temperature must be kept below the maximum
specified temperature (150°C for 7800, 125°C for
7800C) in order to meet data sheet specifications. To
calculate the maximum junction temperature or heat
sink required, the following thermal resistance values
should be used:
Your
Design Considerations
The ILA7800 fixed voltage regulator series has
thermal-overload protection from excessive power
dissipation, internal short circuit protection which
limits the regulator's maximum current, and output
transistor safe area-compensation for reducing the
output current as the voltage across the pass
transistor is increased.
Package
Typ
I!JC
°C/W
Max
I!JC
°C/W
Typ
I!JA
°C/W
Max
I!JA
°C/W
TO-3
3.5
5.5
40
45
TO-220
3.0
5.0
60
65
PO(MAX) =
2·25
TJ(Max) - TA
TJ(Max) - TA
I!JC + I!CA
or
I!JA
(Without heat sink)
JLA7800 Series
(JCA = (JCS
+ (JSA
High Input Voltage Circuits
solving for TJ: TJ = T A + Po «(JJC + (JCA)
or T A + PO(JJA (Without heat sink)
2
1-=-....- - - - Your
Y,N --'"'V'>Ar_>---t
0.33 !,F
where TJ = Junction Temperature
TA = Ambient Temperature
Po = Power Dissipation
(JJC = Junction-to-case-thermal resistance
• (JCA = Case-to-ambient thermal resistance
(JCS = Case-to-heat sink to thermal resistance
(JSA = Heat sink-to-ambient thermal resistance
(JJA = Junction-to-ambient thermal resistance
NOTE 3
'----__1t----.
C2
NOTE 2
2
...-....--Vour
V'N-_---,.
Typical Applications
Fixed Output Regulator
Positive and Negative Regulator
Y,N ----~...-~
1-=-....- - - - Your
r-..._-_--OUTPUT
Notes
1. To specify an output voltage, substItute voltage value for "XX."
2. Bypass capacitors are recommended for optimum stability and
transient response, and should be located as close as
possible to the regulator.
'--_---4>__-_--_--QUTPUT
High Current Voltage Regulator
01
101
Y,N _ ...._ _....;2:..N613;3_ _ _ _ _-_ _ _ _ _---.
R1
3.0 II
lOUT (MAX)
..:. .
Il2;...........==~
I-'
Your
{3(Q 1);::0: IOUT(Max)
IREG(Max)
R1 =
0.9
IREG
,8 (Q 1) VBE(Q 1)
(,8 + 1) - IOUT(Max)
IREG(Max)
Dual Supply
Operational Amplifier Supply (± 15 V @ 1_0 A)
+20 V
INPUT --~t-"'-t
1-=-....___...._______ +15
V
OUTPUT
GND-~...-e---~-.--~~._---1~._-----GND
1N4001 OR
EOUIVALENT
-15 V
r---1~---4~-----OUTPUT
2-26
f.lA7800 Series
High Output Current,
Short Circuit Protected
01
Rsc
INPUT
2N6132
~-----....,
02
2N6124
1-"-+......Rl
3 (1
0.8
RSC= ISC
Rl
=
IREG(Max)
0.33
~F
OUTPUT
0.1
~F
,8 VSE(Q1)
(,8 + 1) - IOUT(Max)
Positive and Negative Regulator
~~----~'--+OUTPUT
~~------
2·27
__----~~----~--OUTPUT
J,tA78MOO Series
3-Terminal Positive
Voltage Regulators
FAIRCHILD
A Schlumberger Company
Linear Products
Description
The /.LA78MOO series of 3-Terminal Medium Current
Positive Voltage Regulators is constructed using the
Fairchild Planar epitaxial process. These regulators
employ internal current-limiting, thermal-shutdown and
safe-area compensation making them essentially
indestructible. If adequate heat sinking is provided,
they can deliver in excess of 500 mA output current.
They are intended as fixed voltage regulators in a
wide range of applications including local or on-card
regulation for elimination of noise and distribution
problems associated with single point regulation. In
addition to use as fixed voltage regulators, these
devices can be used with external components to
obtain adjustable output voltages and currents.
Connection Diagram
TO-39 Package
OUT
COMM
1
2
3
(Top View)
Order Information
Type
Package
/.LA78M05
Metal
/.LA78M06
Metal
/.LA78M08
Metal
/.LA78M12
Metal
/.LA78M15
Metal
/.LA78M24
Metal
IlA78M05C
Metal
/.LA78M06C
Metal
/.LA78M08C
Metal
/.LA78M12C
Metal
/.LA78M15C
Metal
•
•
•
•
•
OUTPUT CURRENT IN EXCESS OF 0.5 A
NO EXTERNAL COMPONENTS
INTERNAL THERMAL-OVERLOAD PROTECTION
INTERNAL SHORT-CIRCUIT CURRENT LIMITING
OUTPUT TRANSISTOR SAFE-AREA
COMPENSATION
• AVAILABLE IN JEDEC TO-220 AND
TO-39 PACKAGES
• OUTPUT VOLTAGES OF 5 V, 6 V, 8 V, 12 V, 15 V,
AND 24 V
• MILITARY AND COMMERCIAL
TEMPERATURE RANGE
Absolute Maximum Ratings
Input Voltage
(5 V through 15 V)
(20 V, 24 V)
Internal Power Dissipation
Storage Temperature Range
TO-39
TO-220
Operating Junction
Temperature Range
/.LA78MOO
/.LA78MOOC
Pin Temperatures
(Soldering, 60 s time limit)
TO-39
(Soldering, 10 s time limit)
TO-220
IN
Code
FC
FC
FC
FC
FC
FC
FC
FC
FC
FC
FC
Part No.
/.LA78M05HM
/.LA78M06HM
/.LA78M08HM
/.LA78M12HM
/.LA78M15HM
/.LA78M24HM
/.LA78M05HC
/.LA78M06HC
/.LA78M08HC
/.LA78M12HC
/.LA78M15HC
Connection Diagram
TO-220 Package
COMMON
~I ~Il~COMM
35 V
40 V
Internally Limited
-65°C to
-55°C to
+ 150°C
+
150°C
(Side View)
-55°C to + 150°C
O°C to + 125°C
Order Information
Type
Package
/.LA78M05C Molded Power
/.LA78M06C Molded Power
/.LA78M08C Molded Power
/.LA78M12C Molded Power
IlA78M15C Molded Power
/.LA78M24C Molded Power
2-28
Pack
Pack
Pack
Pack
Pack
Pack
Code Part No.
GH
/.LA78M05UC
/.LA78M06UC
GH
/.LA78M08UC
GH
/.LA78M12UC
GH
/.LA78M15UC
GH
/.LA78M24UC
GH
JLA78MOO Series
Equivalent Circuit
, . . - - . - - - - - - . - - - - - - . . - - - - _ . _ - _ . _ - - - . - - - I N P U T (1)
R4
100 k
R18
500
012
R11
0.3
R5
r _ , _ - - - - + - - - + - - - - - + - . _ - - + - O U T P U T (2)
3.3 k
R6
2.7 k
R7
500
.......- _ + _ - -........-
L--~___<~___<~-
~A78M05
Electrical Characteristics
=
--+--_ _---4_ _ _ COMMON (3)
........
=
VIN
10 V, lOUT
350 mA, -55°C :::5 TJ :::5 150°C, CIN
unless otherwise specified.
Min
Typ
Max
Unit
4.8
5.0
5.2
V
7 V :::5 VIN :::5 25 V,
lOUT 200 mA
3.0
50
mV
8 V :::5 VIN :::5 20 V,
lOUT
200 mA
1.0
25
mV
5 mA :::5 lOUT :::5 500 mA
20
50
mV
5 mA :::5 lOUT :::5 200 mA
10
25
mV
5.3
V
Characteristic
Condition (Note)
Output Voltage
TJ
Line Regulation
TJ
= 25°C
=
= 25°C
=
= 25°C
Load Regulation
TJ
Output Voltage
8 V :::5 VIN :::5 20 V,
5 mA :::5 lOUT :::5 350 mA
Quiescent Current
TJ
Iwith line
Quiescent Current Change I
with load
8 V :::5 VIN :::5 25 V, lOUT
5 mA :::5 lOUT :::5 350 mA
Output Noise Voltage
TA
Ripple Rejection
Dropout Voltage
Short-Circuit Current
Peak Output Current
Average Temperature Coefficient of
Output Voltage
4.7
= 25°C
= 25°C,
f = 120 Hz,
4.5
= 200 mA
8
10 Hz:::5 f:::5 100 kHz
= 100 mA
lOUT = 300 mA,
TJ = 25°C
lOUT
8 V :::5 VIN:::5 18 V
= 25°C, lOUT = 350 mA
TJ = 25°C, VIN = 35 V
TJ = 25°C
= 5 mA
7.0
mA
0.8
mA
0.5
mA
40
~V IVOUT
dB
62
62
80
dB
2.0
2.5
V
300
600
mA
0.7
1.4
A
1-55°C:::5 TJ:::5 +25°C
0.4
I+25°C:::5 TJ:::5 +150°C
0.3
mV / °C/
VOUT
TA
lOUT
= 0.33 ~F, COUT = O.l~F,
Note
All characteristics except noise voltage and ripple rejection
ratio are measured using pulse techniques (TW ,.; 10 ms, duty
0.5
cycle,.; 5%). Output voltage changes due to changes in
Internal temperature must be taken into account separately.
2-29
JLA 78MOO Series
J.LA78M05C
Electrical Characteristics
=
VIN = 10 V, lOUT 350 mA, O°C.::s TJ.::s 125°C, CIN
otherwise specified.
Characteristic
Condition (Note)
Output Voltage
TJ
= 25°C
Line Regulation
TJ
= 25°C
= 0.33 J.LF, COUT = 0.1 J.LF, unless
Min
Typ
Max
Unit
4.8
5.0
5.2
V
7 V .::s VIN .::s 25 V,
lOUT
200 mA
3.0
100
mV
8 V .::s VIN .::s 25 V,
lOUT
200 mA
1.0
50
mV
5 mA .::s lOUT .::s 500 mA
20
100
mV
5 mA .::s lOUT .::s 200 mA
10
50
mV
5.25
V
=
=
Load Regulation
TJ
= 25°C
Output Voltage
7 V .::s VIN .::s 20 V,
5 mA .::s lOUT .::s 350 mA
Quiescent Current
TJ
Iwith line
Quiescent Current Change I
8 V .::s VIN .::s 25 V, lOUT
with load
Output Noise Voltage
Ripple Rejection
4.75
= 25°C
4.5
= 200 mA
5 mA .::s lOUT .::s 350 mA
= 25°C,
1 = 120 Hz,
TA
10 Hz .::s 1 .::s 100 kHz
lOUT
=
lOUT
300 mA,
62
TJ
25°C
=
8 V .::s VIN .::s 18 V
= 25°C
= 25°C, VIN = 35 V
TJ = 25°C
lOUT = 5 mA
40
= 100 mA 62
8.0
mA
0.8
mA
0.5
mA
J.LV
dB
80
dB
Dropout Voltage
TA
2.0
V
Short-Circuit Current
TJ
300
mA
700
mA
1.0
mV/oC
Peak Output Current
Average Temperature Coelficient 01
Output Voltage
Note
All characteristics except noise voltage and ripple rejection
ratIo are measured using pulse techniques (TW :5 10 ms, duty
cycle :5 5%). Output voltage changes due to changes in
internal temperature must be taken into account separately.
2·30
""A78MOO Series
/LA78M06
Electrical Characteristics
=
=
VIN
11 V, lOUT
350 mA, -55°C :5 TJ :5 150°C, CIN
unless otherwise specified.
Characteristic
Condition (Note)
Output Voltage
TJ
Line Regulation
TJ
= 25°C
Min
Typ
Max
Unit
5.75
6.0
6.25
V
8 V :5 VIN :5 25 V,
lOUT
200 mA
5.0
60
mV
9 V :5 VIN :5 20 V,
lOUT
200 mA
1.5
30
mV
5 mA :5 lOUT :5 500 mA
20
60
mV
5 mA :5 lOUT :5 200 mA
10
30
rnV
6.3
V
7.0
mA
0.8
mA
=
= 25°C
=
Load Regulation
TJ
= 25°C
Output Voltage
9 V :5 VIN :5 21 V,
5 mA :5 lOUT :5 350 rnA
Quiescent Current
TJ
Quiescent Current Change
IIwith line
with load
Output Noise Voltage
Ripple Rejection
= 0.33 /LF, COUT = 0.1 /LF,
5.7
= 25°C
4.5
9 V :5 VIN :5 25 V, lOUT
= 200 mA
5 mA :5 lOUT :5 350 mA
TA
= 25°C,
10 Hz :5 f:5 100 kHz
lOUT
f = 120 Hz,
9 V :5 VIN :5 19 V
= 100 mA
=
8
= 25°C, lOUT = 350 mA
= 25°C, VIN = 35 V
TJ = 25°C
mA
40
/LV IVOUT
59
lOUT
300 mA,
59
TJ
25°C
=
0.5
dB
80
dB
Dropout Voltage
TA
2.0
2.5
V
Short-Circuit Current
TJ
300
600
mA
Peak Output Current
Average Temperature Coefficient of
Output Voltage
lOUT
= 5 mA
1-55°C:5 TJ:5 +25°C
I +25°C :5 TJ :5 +150°C
Note
All characteristics except noise voltage and ripple rejection
ratio are measured using pulse techniques (TW .s 10 ms, duty
0.5
0.7
1.4
A
.4
rnV lOCI
VOUT
.3
cycle .s 5%). Output voltage changes due to changes in
IOternal temperature must be taken into account separately.
2·31
#LA 78MOO Series
~A78M06C
Electrical Characteristics
=
=
VIN
11 V, lOUT 350 mA, O°C :5 TJ :5 125°C, CIN
otherwise specified.
= 0.33 ~F, COUT = 0.1 ~F, unless
Min
Typ
Max
Unit
5.75
6.0
6.25
V
8 V :5 VIN :5 25 V,
lOUT
200 mA
5.0
100
mV
9 V :5 VIN :5 25 V,
lOUT
200 mA
1.5
50
mV
5 mA :5 lOUT :5 500 mA
20
120
mV
5 mA :5 lOUT :5 200 mA
10
60
mV
6.3
V
8.0
mA
0.8
mA
0.5
mA
Characteristic
Condition (Note)
Output Voltage
TJ
= 25°C
Line Regulation
TJ
= 25°C
=
=
= 25°C
Load Regulation
TJ
Output Voltage
8 V :5 VIN :5 21 V,
5 mA :5 lOUT :5 350 mA
Quiescent Current
TJ
Iwith line
Quiescent Current Change I
9 V :5 VIN :5 25 V, lOUT
with load
Output Noise Voltage
Ripple Rejection
5.7
= 25°C
4.5
= 200 mA
5 mA :5 lOUT :5 350 mA
= 25°C,
f = 120 Hz,
TA
10 Hz:5 f:5 100 kHz
= 100 mA
lOUT = 300 mA,
TJ = 25°C
lOUT
9 V :5 VIN :5 19 V
= 25°C
= 25°C, VIN = 35 V
TJ = 25°C
lOUT = 5 mA
45
59
59
~V
dB
80
dB
Dropout Voltage
TA
2.0
V
Short-Circuit Current
TJ
270
mA
700
mA
0.5
mV/oC
Peak Output Current
Average Temperature Coefficient of
Output Voltage
Note
All characterostics except noise voltage and rippla raJection
ratio ara measured uSing pulse techmques (TW .:s 10 ms, duty
cycle .:s 5%). Output voltage changes due to changes In
Internal temperature must be taken into account separately.
2-32
#LA 78MOO Series
#tA78M08
Electrical Characteristics
VIN = 14 V, lOUT = 350 mA, -55°C :5 TJ:5 150°C, CIN = 0.33 #IF, COUT = 0.1 #IF,
unless otherwise specified.
Characteristic
Condition (Note)
Min
Typ
Max
Unit
Output Voltage
TJ = 25°C
7.7
8.0
8.3
V
10.5 V :5 VIN :5 25 V,
lOUT = 200 mA
6.0
60
mV
11 V :5 VIN :5 20 V,
lOUT = 200 mA
2.0
30
mV
5 mA :5 lOUT :5 500 mA
25
80
mV
5 mA :5 lOUT :5 200 mA
10
40
mV
8.4
V
TJ = 25°C
Line Regulation
Load Regulation
TJ = 25°C
Output Voltage
11.5 V:5 VIN:5 23 V,
5 mA :5 lOUT :5 350 mA
TJ = 25°C
Quiescent Current
Quiescent Current Change
7.6
I with line
Iwith load
Output Noise Voltage
4.6
11.5 V :5 VIN :5 25 V, lOUT = 200 mA
5 mA :5 lOUT :5 350 mA
TA = 25°C, 10 Hz:5 f:5 100 kHz
8
7.0
mA
0.8
mA
0.5
mA
40
#tV IVOUT
lOUT = 100 mA 56
f = 120 Hz,
dB
lOUT = 300 mA,
11.5 V :5 VIN :5 21.5 V TJ = 25°C
56
80
Dropout Voltage
TA = 25°C, lOUT = 350 mA
2.0
2.5
Short-Circuit Current
TJ = 25°C, VIN = 35 V
300
600
mA
Peak Output Current
TJ = 25°C
0.7
1.4
A
Average Temperature Coefficient of
Output Voltage
lOUT = 5 mA
Ripple Rejection
0.5
I-55°C :5 TJ :5 +25°C
I+25°C :5 TJ :5 + 150°C
Note
All characteristics except noise voltage and ripple rejectIon
ratIo are measured using pulse techniques (TW ~ 10 ms, duty
dB
0.4
V
mV/oC
0.3
cycle ~ 5%). Output voltage changes due to changes in
internal temperature must be taken into sccount separately.
2·33
•
~A 78MOO Series
"A78M08C
Electrical Characteristics
VIN = 14 V, lOUT = 350 mA, O°C::S TJ::S 125°C, CIN
otherwise specified.
Characteristic
Condition (Note)
Output Voltage
TJ
Line Regulation
TJ
Load Regulation
TJ
= 25°C
= 25°C
= 25°C
Unit
7.7
V
6.0
100
mV
11 V ::s VIN ::s 25 V,
lOUT = 200 mA
2.0
50
mV
25
160
mV
10
80
mV
8.4
V
8.0
mA
5 mA
5 mA
::s lOUT ::s 500 mA
::s lOUT ::s 200 mA
TJ
Ripple Rejection
Max
8.3
Quiescent Current
Output Noise Voltage
Typ
8.0
10.5 V ::s VIN ::s 23 V,
5 mA ::s lOUT ::s 350 mA
.II
Min
10.5 V ::s VIN ::s 25 V,
lOUT = 200 mA
Output Voltage
with line
Quiescent Current Change
'
with load
= 0.33 "F, COUT = 0.1 "F, unless
7.6
= 25°C
4.6
::s VIN ::s 25 V, lOUT = 200 mA
::s lOUT ::s 350 mA
TA = 25°C, 10 Hz ::s f ::s 100 kHz
10.5 V
0.8
mA
5 mA
0.5
mA
f
= 120 Hz,
11.5 V
::s
VIN
= 100 mA
lOUT = 300 mA,
TJ = 25°C
lOUT
::s 21.5 V
= 25°C
= 25°C, VIN = 35 V
TJ = 25°C
lOUT = 5 mA
52
"V
dB
80
dB
56
56
Dropout Voltage
TA
2.0
V
Short-Circuit Current
TJ
250
mA
700
mA
0.5
mV/oC
Peak Output Current
Average Temperature Coefficient of
Output Voltage
Note
All characteristics except noise voltage and ripple rejection
ratio are measured using pulse techniques (Tw ~ 10 ms, duty
cycle ~ 5%). Output voltage changee due to changes in
'"ternal temperature must be taken into account separately.
2-34
JLA 78MOO Series
#tA78M12
Electrical Characteristics
VIN = 19 V, lOUT = 350 mA, -55°C :5 TJ :5 150°C, CIN = 0.33ILF, COUT = 0.1 ILF,
unless otherwise specified.
Characteristic
Condition (Note)
Min
Typ
Max
Unit
Output Voltage
TJ = 25°C
11.5
12
12.5
V
14.5 V :5 VIN :5 30 V,
lOUT = 200 mA
8.0
60
mV
16 V :5 VIN :5 25 V,
lOUT = 200 mA
2.0
30
mV
5 mA :5 lOUT :5 500 mA
25
120
mV
5 mA :5 lOUT :5 200 mA
10
60
mV
12.6
V
7.0
mA
0.8
mA
TJ = 25°C
Line Regulation
TJ = 25°C
Load Regulation
Output Voltage
15.5 V :5 VIN:5 27 V,
5 mA :5 lOUT :5 350 mA
Quiescent Current
TJ = 25°C
Quiescent Current Change
IIwith line
with load
Output Noise Voltage
Ripple Rejection
Dropout Voltage
11.4
4.8
15 V :5 VIN :5 30 V, lOUT = 200 mA
5 mA :5 lOUT :5 350 mA
TA = 25°C, 10 Hz :5 f :5 100 kHz
8
0.5
mA
40
#tV/VOUT
dB
lOUT = 100 mA 55
f = 120 Hz,
lOUT = 300 mA,
55
TJ = 25°C
15 V :5 VIN :5 25 V
80
dB
TA = 25°C, lOUT = 350 mA
2.0
2.5
V
Short-Circuit Current
TJ = 25°C, VIN = 35 V
300
600
mA
Peak Output Current
TJ = 25°C
1.4
A
0.4
mV/oC/
VOUT
Average Temperature Coefficient of
Output Voltage
lOUT = 5 mA
0.5
i-55°C:5 TJ :5 +25°C
I+25°C :5 TJ:5 +150°C
Note
All characteristics except noise voltage and ripple rejection
ratio are measured using pulse techniques (TW .:s 10 ms, duty
0.7
0.3
cycle .:s 6%). Output voltage changes due to changes in
internal temperature must be taken into account separately.
2·36
•
p.A78MOO Series
#A78M12C
Electrical Characteristics
VIN = 19 V, lOUT = 350 mA, O°C 5: TJ 5: 125°C, CIN
otherwise specified.
Characteristic
Condition (Note)
Output Voltage
TJ
Line Regulation
TJ
Load Regulation
TJ
= 25°C
= 25°C
= 25°C
= 0.33 #F, COUT = 0.1 #F, unless
Min
Typ
Max
Unit
11.5
12
12.5
V
14.5 V 5: VIN 5: 30 V,
lOUT = 200 mA
8.0
100
mV
16 V 5: VIN 5: 30 V,
lOUT = 200 mA
2.0
50
mV
5 mA 5: lOUT 5: 500 mA
25
240
mV
5 mA 5: lOUT 5: 200 mA
10
120
mV
12.6
V
8.0
mA
0.8
mA
Output Voltage
14.5 V 5: VIN 5: 27 V,
5 mA 5: lOUT 5: 350 mA
Quiescent Current
TJ
Iwith line
Quiescent Current Change I
14.5 V 5: VIN 5: 30 V, lOUT
Output Noise Voltage
TA
11.4
= 25°C
4.8
= 200 mA
with load 5 mA 5: lOUT 5: 350 mA
Ripple Rejection
= 25°C,
f = 120 Hz,
0.5
10 Hz 5: f 5: 100 kHz
lOUT
= 100 mA
75
55
lOUT = 300 mA,
55
TJ = 25°C
15 V 5: VIN 5: 25 V
= 25°C
= 25°C, VIN = 35 V
TJ = 25°C
lOUT = 5 mA
mA
#V
dB
80
dB
Dropout Voltage
TA
2.0
V
Short-Circuit Current
TJ
240
mA
700
mA
1.0
mV/oC
Peak Output Current
Average Temperature Coefficient of
Output Voltage
Note
All characteristics except noise voltage and ripple rejection
ratio are measured using pulse techniques (TW .:5 10 ms, duty
cycle .:5 5%). Output voltage changes due to changes in
internal temperature must be taken into account separately.
2·36
~A78MOO
Series
~A78M15
Electrical Characteristics
Y,N = 23 V, lOUT = 350 mA, -55°C S TJ S 150°C, C,N = 0.33
unless otherwise specified.
~F,
COUT = 0.1
Characteristic
Condition (Note)
Min
Typ
Max
Unit
Output Voltage
TJ=25°C
14.4
15
15.6
V
17.5 V S Y,N S 30 V,
lOUT = 200 mA
10
60
mV
20 V S Y,N S 30 V,
lOUT = 200 mA
3.0
30
mV
5 mA S lOUT S 500 mA
25
150
mV
5 mA S lOUT S 200 mA
10
75
mV
15.75
V
Line Regulation
TJ = 25°C
Load Regulation
TJ = 25°C
~F,
Output Voltage
18.5 V S Y,N S 30 V,
5 mA S lOUT S 350 mA
Quiescent Current
TJ = 25°C
7.0
mA
.
Iwith line
QUiescent Current Change I
18.5 V S Y,N S 30 V, lOUT = 200 mA
0.8
mA
5 mA S lOUT S 350 mA
0.5
mA
40
~V/VOUT
with load
Output Noise Voltage
Ripple Rejection
14.25
4.8
TA = 25°C, 10 Hz S f S 100 kHz
8
lOUT = 100 mA 54
f= 120Hz,
dB
lOUT = 300 mA,
18.5 V S Y,N S 28.5 V TJ = 25°C
54
70
Dropout Voltage
TA = 25°C
2.0
2.5
V
Short-Circuit Current
TJ = 25°C, Y,N = 35 V
300
600
mA
Peak Output Current
TJ = 25°C
1.4
Average Temperature Coefficient of
Output Voltage
I-550C S TJ S +25°C
lOUT = 5 mA +25°C S TJ S +150°C
A
mV/oC
VOUT
0.5
0.7
dB
0.4
0.3
Note
cycle .:s 5%). Output voltage changes due to changes in
Internal temperature must be taken into account separately.
All characteristics except noise voltage and ripple rejection
ratio are measured using pulse techniques (TW .:s 10 ms, duty
2-37
•
p,A 78MOO Series
"A78M15C
Electrical Characteristics
VIN = 23 V, lOUT = 350 mA, O°C ~ TJ ~ 125°C, CIN = 0.33 "F, COUT = 0.1 "F, unless
otherwise specified.
Characteristic
Condition (Note)
Min
Typ
Max
Unit
Output Voltage
TJ = 25°C
14.4
15
15.6
V
17.5 V ~ VIN ~ 30 V,
lOUT = 200 mA
10
100
mV
20 V ~ VIN ~ 30 V,
lOUT = 200 mA
3.0
50
mV
Line Regulation
TJ = 25°C
5 mA
~
lOUT
~
500 mA
25
300
mV
5 mA
~
lOUT
~
200 mA
10
150
mV
15.75
V
Load Regulation
TJ = 25°C
Output Voltage
17.5 V ~ VIN ~ 30 V,
5 mA ~ lOUT ~ 350 mA
Quiescent Current
TJ = 25°C
Quiescent Current Change
with line
IIwith
load
Output Noise Voltage
Ripple Rejection
17.5 V
5 mA
~
~
4.8
VIN
~
30 V, lOUT = 200 mA
lOUT
~
350 mA
TA = 25°C, 10 Hz
~
VIN
~
f
~
100 kHz
~
lOUT = 300 mA,
54
28.5 V TJ = 25°C
8.0
mA
0.8
mA
0.5
mA
90
"V
dB
70
dB
lOUT = 100 mA 54
f= 120Hz,
18.5 V
14.25
Dropout Voltage
TA = 25°C
2.0
V
Short-Circuit Current
TJ = 25°C, VIN = 35 V
240
mA
Peak Output Current
TJ = 25°C
700
mA
Average Temperature Coefficient of
Output Voltage
lOUT = 5 mA
1.0
mV/oC
Note
All characteristics except noise voltage and ripple rejection
ratio are measured using pulse techniques (TW :$ 10 ms, duty
cycle :$ 5%). Output voltage changes due to changes in
internal temperature must be taken into account separately.
2-38
JLA 78MOO Series
I'A78M24
Electrical Characteristics
VIN = 33 V, lOUT = 350 mA, -55°C :S TJ :S 150°C, CIN = 0.33I'F, COUT = 0.1 I'F,
unless otherwise specified.
Characteristic
Condition (Note)
Min
Typ
Max
Unit
Output Voltage
TJ = 25°C
23
24
25
V
60
mV
TJ=25°C
27 V :S VIN :S 38 V,
lOUT 200 mA
10
Line Regulation
30 V S VIN:S 36 V,
lOUT = 200 mA
5.0
30
mV
5 mA :S lOUT :S 500 mA
30
240
mV
5 mA :S lOUT :S 200 mA
10
120
mV
25.2
V
=
Load Regulation
TJ = 25°C
Output Voltage
28 V :S VIN :S 38 V,
5 mA :S lOUT :S 350 mA
Quiescent Current
Quiescent Current Change
22.8
5.0
7.0
mA
0.8
mA
5 mA :S lOUT :S 350 mA
0.5
mA
TA = 25°C, 10 Hz :S f :S 100 kHz
40
I'VIV OUT
dB
TJ = 25°C
I with line
Iwith load
Output Noise Voltage
Ripple Rejection
28 V :S VIN :S 38 V, lOUT
= 200 mA
8
lOUT = 100 mA 50
f = 120 Hz,
lOUT = 300 mA,
50
TJ = 25°C
28 V :S VIN :S 38 V
70
dB
Dropout Voltage
TA = 25°C, lOUT = 350 mA
2.0
2.5
V
Short-Circuit Current
TJ = 25°C, VIN = 35 V
300
600
mA
Peak Output Current
TJ = 25°C
0.7
1.4
mA
mV/oC
VOUT
Average Temperature Coefficient of
Output Voltage
lOUT = 5 mA
0.5
I-55°C :S TJ :S +25°C
I+25°C:S TJ:S +150°C
Note
All characteristics except noise voltage and ripple rejection
ratio are measured using pulse techniques (Tw ~ 10 ms, duty
0.4
0.3
cycle ~ 5%). Output voltage changes due to changes in
intemsl temperature must be taken into account separately.
2-39
J.LA 78MOO Series
~A78M24C
Electrical Characterl8tlc8
VIN = 33 V, lOUT = 350 rnA, O°C
otherwise specified.
= 25°C
= 25°C
Max
Unit
25
V
27 V ~ VIN ~ 38 V,
lOUT = 200 rnA
10
100
mV
28 V ~ VIN ~ 38 V,
lOUT = 200 rnA
5.0
50
mV
5 rnA
~
lOUT
~
500 rnA
30
480
mV
5 rnA
~
lOUT
~
200 rnA
10
240
mV
25.2
V
8.0
rnA
0.8
rnA
TJ
Output Voltage
27 V ~ VIN ~ 38 V,
5 rnA ~ lOUT ~ 350 rnA
Quiescent Current
TJ
Iwith line
Quiescent Current Change I
27 V
~
VIN
with load 5 rnA
~
lOUT
Output Noise Voltage
TA
Short·Circuit Current
Peak Output Current
Average Temperature Coefficient of
Output Voltage
= 0.33 ~F, COUT = 0.1 ~F, unless
24
= 25°C
Load Regulation
Dropout Voltage
125°C, CIN
Typ
TJ
Ripple Rejection
~
23
Condition (Note)
Output Voltage
TJ
TJ
Min
Characterl8tlc
Line Regulation
~
22.8
= 25°C
= 25°C,
f = 120 Hz,
28 V
~
VIN
5.0
~
38 V, lOUT
~
= 200 rnA
0.5
350 rnA
10 Hz
~
f
~
100 kHz
= 100 rnA
lOUT = 300 rnA,
TJ = 25°C
lOUT
~
38 V
= 25°C, lOUT = 350 rnA
TJ = 25°C, VIN = 35 V
TJ = 25°C
lOUT = 5 rnA
TA
Note
All characteristics except noise voltage and ripple rejection
ratio are measured using pulse techniques (TW .:5 10 ms, duty
170
50
50
rnA
~V
dB
70
dB
2.0
V
240
rnA
700
rnA
1.2
mV/oC
cycle .:5 5%). Output voltage changes due to changes in
internsl temperature must be taken into account separately.
2·40
J,LA78MOO Series
Typical Performance Curves
Worst Case Power Dissipation
Versus Ambient Temperature
TO-39
,.
.l
711MOOC
5.0
;0 40
30
r-:-. ~~81"'o\"
'1'=1·· C)W ~ ~
20
i 1. r-~
"
~
.
!: 10
=
;;
a:
SH$ = 2O"C/W
... 5
..
I
~ 20
>=
,!,~ ~
AI,.. "/fl(
;
0.4
••
I
••
•
~\\
\"...
"
8JC = 25°C/W
PO\MAX) =- 7 5 W
1
25
so
100
75
1\\'
125
AMBIENT TEMPERATURE _
01
I
:>
u
AMBIENT TEMPERATURE _ °C
7805
12.18
"
0.8
.AI-
:-.;:: ~'=-~~>
"~
~.
I'~
:>
04
"
~
~
.,....;1-
1~18Q~OC ~ "
~~
~
O'
o
o
10
I 12.01
I
I
15
20
'0
>
I
•0
w
"i:!
100
S
>
r
0
,iUT 140 mA
~
f1'
II
:>
o •.0
5
Or--... V~ 1::7
I
10 T
= 100 mA
0
fl
•
II
20
40
••0
INPUT VOLTAGE -
80
-75 -50 -25
lOOk
10
V
-75
~ ...+'
'0
.... f~
,
....
~
I'''I~
~
t- f-,..'OUT "" 0 InA
•
•
I-VIN
-so
-25
0
25
50
I
75 100 125 150 175
JUNCTION TEMPERATURE _ °C
Not.
Other IlA78MOO Series devices have similar curves.
2-41
50 75 100 125 150 175
°c
7~MJ.
= 10 V
VouT==5Y
LOAD CURRENT
2
1
1-10
OUTPUT VOLTAGE
DEVIATION
V
I
DROPOUT CONDITIONS
or VyT
75
Load Transient Response
f-
r- :r-- F:::: b
0
JUNCTION TEMPERATURE _
I
I'-- to.....
o I-ivoul = j'"
111
0
10k
Dropout Voltage as a
Function of
Junction Temperature
')'MJS-
5
.5i C
40
1k
5
JouT L L
lOUT
"64
T(IIITi III
10
........
11 ..
== 500 mA
FREQUENCY - Hz
Dropout Characteristics
t- TJ
K
~ 1192
o
V" = 8 V TO 18 V
Your'" 5 V
INPUT OUTPUT DIFFERENTIAL _ V
0
........
.
r"
25
.......
>
lOUT
150
J'ML
= 12 V
= 5 mA
~ 11.98
•0
125
r...
~ '::.:
i
a:
100
L..Iv
12.12 f--I UT
w
~
r" ~1;,1'=:::
:>
>
..
~
....
_fo...
J-.
I-V!N
Your
80
•. 8
75
Output Voltage as a
Function of
Junction Temperature
Ripple Rejection as a
Function of Frequency
,.
50
AMBIENT TEMPERATURE-"C
100
I-
0.
I-
25
25
"c
12
I-
0.5
04
2 03
O'
150
Peak Output Current as a
Function of Input-Output
Differential Voltage
.
.ill
Power Watt (UIC)
Worst Case Power Dissipation
Versus Ambient Temperature
I-
LIMIT FOR
4. t...==-I-/,,,..
"""t-!"'".~"
~ 30 r-5.•
~
Worst Case Power Dissipation
Versus Ambient Temperature
TO-220
1
•
10
20
..
30
TIME -
14
50
..
~A78MOO
Series
Typical Performance Curves (Cont.)
Line Transient Response
..
~
I
I
I
INPUT VO TAOE
3.
)IM~.
~
~
~
w
~
••
I- 1-1-
OUTPUT VOLTAGE
DEVIATION
1-1-
.
•
>
.
I
~
~
...
!
-10 ~ TJ
'" 25°e
lOUT "" 500 mA
o
-2.
7~MJ.-
Ie
"
U
..~
10
..•
1/
...
~
u
..
_
!!!
0
45
4.4
•
l
I
.......
4.
4.2
:;
"
o
••
12
"
•
•
4.
INPUT YOLTAGE -
Package
Typ
(JJC
Max
(JJC
Typ
(JJA
Max
(JJA
TO-39
TO-220
Power Watt
18
3
6
25
5
120
60
70
160
65
75
8
TJ (Max) - TA
(JJC + (JCA
or
TJ (Max) - TA
(JJA
(Without a heat Sink)
"
25
0
25
50
75 100 125 150 1715
AMBIENT TEMPERATURE -
Y
"c
Where TJ = Junction Temperature
TA = Ambient Temperature
Po = Power Dissipation
(JJC = Junction to case thermal resistance
(JCA Case-to-ambient thermal resistance
(JCS Case-to-heat sink to resistance
(JSA Heat sink-to-ambient thermal resistance
(JJA Junction-to-ambient thermal resistance
=
=
=
=
Typical Applications
Fixed Output Regulator
INPUT --'""VV'Ir~~-t
0.331'F
NOTE 2
..2;......,....._ _ _ OUTPUT
+C2
NOTE 2
Not••
1. To specify an output voltage. substitute voltage value for "XX".
2. Bypass Capacitors are recommended for optimum stability and
transient response and should be located as close as possible
to the regulator.
(JSA
Solving for TJ: TJ
-75 -so
5101520253035
Po.
Although the internal power dissipation is limited, the
junction temperature must be kept below the maximum
specified temperature (150°C for 78MOO, 125°C for
78MOOC) in order to meet data sheet specifications.
To calculate the maximum junction temperature or
heat sink required, the following thermal resistance
values should be used:
= (JCS +
= 2DO mA
I .1
IG
Design Considerations
The !LA78MOO fixed voltage regulator series has
thermal-overload protection from excessive power,
internal short circuit protection which limits the
circuit's maximum current, and output transistor safearea compensation for reducing the output short
circuit current as the voltage across the pass
transistor is increased.
(JCA
47 t- Jour
4.
TIME -
Po (MAX) =
JIM~-
I=.J v I
'.1 r-J,.
VouT=5V
;
I
~
Ie
~~oUTI=1YI
•
Joul=~Y'
== 20 mA
s. f--!LT, == 2S°C
Quiescent Current as a
Function of Temperature
E
·,
5
g •
~::)
..
••
20
Quiescant Current as a
Function of
Input Voltage
=TA + Po «(JJC+(JCA) or TA + Po (JJA
(Without a heat sink)
2-42
p,A 78LOO Series
3-Terminal Positive
Voltage Regulators
FAIRCHILD
A Schlumberger Company
Linear Products
Connection Diagram
TO-92 Package
Description
The ~A78LOO series of 3-Terminal Positive Voltage
Regulators is constructed using the Fairchild
Planar epitaxial process. These regulators employ
internal current-limiting and thermal-shutdown, making
them essentially indestructible. If adequate heat
sinking is provided, they can deliver up to 100 mA
output current. They are intended as fixed voltage
regulators in a wide range of applications including
local or on-card regulation for elimination of noise and
distribution problems associated with single-point
regulation. In addition, they can be used with power
pass elements to make high-current voltage
regulators. The ~A78LOO used as a Zener
diode/resistor combination replacement, offers an
effective output impedance improvement of typically
two orders of magnitude, along with lower quiescent
current and lower noise.
(Top View)
Order Information
Type
Package
~A78L05AC
Molded
~A78L62AC
Molded
~A78L82AC
Molded
~A78L09AC
Molded
~A78L 12AC
Molded
~A78L 15AC
Molded
•
•
•
•
•
•
OUTPUT CURRENT UP TO 100 rnA
NO EXTERNAL COMPONENTS
INTERNAL THERMAL OVERLOAD PROTECTION
INTERNAL SHORT CIRCUIT CURRENT LIMITING
AVAILABLE IN JEDEC TO-92
OUTPUT VOLTAGES OF 5 V, 6_2 V, 8.2 V, 9 V,
12 V, 15 V
• OUTPUT VOLTAGE TOLERANCES OF ±5%
OVER THE TEMPERATURE RANGE
Absolute Maximum Ratings
Input Voltage
5.0 V to 15 V
Internal Power Dissipation
Storage Temperature Range
Operating Junction
Temperature Ranges
~A78LOOC (Commercial)
Pin Temperatures
(Soldering, 10 s)
35 V
Internally Limited
-55°C to + 150°C
O°C to
+ 125°C
260°C
2-43
~~~~~~---------
Code
EI
EI
EI
EI
EI
EI
Part No.
~A78L05AWC
~A78L62AWC
~A78L82AWC
~A78L09AWC
~A78L 12AWC
~A78L 15AWC
~A 78LOO
Series
Equivalent Circuit
........- - - - - - - - - - - - - - - _ - _ - - - - - I N P U T
017
R21
1K
R23
3.3!l
OUTPUT
:.:
~
;f~f~f~t
« ;i:f:f~f
...
c.
c:i
0
ri
:.:
...I
03
Rs
0.834 K
~-~---~--~~~--__~-----~----------COMMON
#LA78L05AC and #LA78L05AV (Note 2)
Electrical Characteristics VIN
10 V, lOUT 40 mA, O°C :::s TJ
unless otherwise specified. (Note 1)
=
=
:::s
125°C, CIN
= 0.33 #LF, COUT = 0.1 #LF,
Characteristic
Condition
Min
Typ
Max
Output Voltage
TJ
4.8
5.0
5.2
V
Line Regulation
= 25°C
TJ = 25°C
55
150
mV
45
100
mV
Load Regulation
TJ
11
60
mV
5.0
30
mV
4.75
5.25
V
4.75
5.25
V
5.5
mA
= 25°C
7V
Output Voltage
:::s VIN:::S 20 V
8 V :::s VIN:::S 20 V
1 mA :::s IOUT:::S 100 mA
1 mA :::s lOUT :::s 40 mA
1 mA :::s lOUT :::s 40 mA
7V
:::s
VIN:::S 20 V
7 V :::s VIN
(Note 3)
:::s
VMax
1 mA
:::s
lOUT
:::s
70 mA
2.0
Quiescent Current
Quiescent Current
Change
Iwith line
Iwith load
Output Noise Voltage
:::s VIN:::S 20 V
:::s lOUT :::s 40 mA
TA = 25°C, 10 Hz :::s f :::s
8V
1.5
mA
1 mA
0.1
mA
Temperature Coefficient of
VOUT
lOUT
Ripple Rejection
f
120 Hz, 8 V
TJ
25°C
Dropout Voltage
Peak Output / Short-Circuit
Current
Notes on I'A78L 15 page.
Unit
100 kHz
= 5 mA
=
=
TJ = 25°C
TJ = 25°C
:::s
VIN
:::s
18 V,
2·44·
41
40
#LV
-0.65
mV/oC
49
dB
1.7
V
140
mA
JLA 78LOO Series
J.LA78L62AC
Electrical Characteristics
VIN = 12 V, lOUT = 40 mA, O°C :5 TJ :5 125°C, CIN = 0.33 !tF, COUT = 0.1 J.LF,
unless otherwise specified. (Note 1)
Characteristic
Condition
Min
Typ
Max
Output Voltage
TJ = 25°C
5.95
6.2
6.45
V
8.5 V :5 VIN :5 20 V
65
175
mV
9 V :5 VIN :5 20 V
55
125
mV
1 mA :5 lOUT :5 100 mA
13
80
mV
1 mA :5 lOUT :5 40 mA
6.0
40
mV
Unit
Line Regulation
TJ=25°C
Load Regulation
TJ = 25°C
8.5 V :5 VIN :5 20 V
1 mA :5 lOUT :5 40 mA
5.90
6.5
V
Output Voltage
8.5 V :5 VIN :5 VMax
(Note 3)
1 mA :5 lOUT :5 70 mA
5.90
6.5
V
5.5
mA
8.0 V :5 VIN :5 20 V
1.5
mA
1 mA :5 lOUT :5 40 mA
0.1
mA
2.0
Quiescent Current
Quiescent Current
Change
Iwith line
Iwith load
Output Noise Voltage
TA = 25°C, 10 Hz :5 f:5 100 kHz
50
!tV
Temperature Coefficient of
VOUT
lOUT = 5 mA
-0.75
mV/oC
Ripple Rejection
f = 120 Hz, 10 V :5 VIN :5 20 V,
TJ = 25°C
46
dB
Dropout Voltage
TJ = 25°C
1.7
V
Peak Output / Short-Circuit
Current
TJ = 25°C
140
mA
J.LA78L82AC
Electrical Characteristics
40
VIN = 14 V, lOUT = 40 mA, O°C :5 TJ :5 125°C, CIN = 0.33 J.LF, COUT = 0.1 J.LF,
unless otherwise specified. (Note 1)
Characteristic
Condition
Output Voltage
TJ = 25°C
Line Regulation
TJ = 25°C
Load Regulation
TJ = 25°C
Output Voltage
Min
Typ
Max
7.87
8.2
8.53
V
11 V :5 VIN :5 23 V
80
175
mV
12 V :5 VIN :5 23 V
70
125
mV
1 mA :5 IOUT:5 100 mA
15
80
mV
1 mA :5 lOUT :5 40 mA
8.0
40
mV
11 V :5 VIN :5 23 V
1 mA :5 lOUT :5 40 mA
7.8
8.5
V
11 V :5 VIN :5 VMax
(Note 3)
1 mA :5 lOUT :5 70 mA
7.8
8.6
V
5.5
mA
1.5
mA
Quiescent Current
Quiescent Current
Change
2.1
Iwith line
Iwith load
Unit
12 V :5 VIN :5 23 V
0.1
1 mA :5 lOUT :5 40 mA
mA
Output Noise Voltage
TA = 25°C, 10 Hz:5 f:5 100 kHz
60
J.LV
Temperature Coefficient of
VOUT
lOUT = 5 mA
-0.8
mV/oC
Ripple Rejection
f = 120 Hz, 12 V :5 VIN :5 22 V,
TJ = 25°C
45
dB
Dropout Voltage
TJ = 25°C
1.7
V
Peak Output / Short-Circuit
Current
TJ = 25°C
140
mA
Noles on jtA78L 15 page.
2-45
39
•
~A 78LOO
ItA78L09AC
Electrical Characteristics
=
Series
=
VIN
15 V, lOUT 40 rnA, O°C :5 TJ :5 125°C, CIN
unless otherwise specified. (Note 1)
= 0.331tF, COUT = 0.11tF,
Characteristic
Condition
Min
Output Voltage
= 25°C
TJ = 25°C
8.64
TJ
Line Regulation
Load Regulation
TJ
Output Voltage
= 25°C
Max
Unit
9.0
9.36
V
11.5 V :5 VIN :5 24 V
90
200
mV
13 V :5 VIN :5 24 V
100
150
mV
1 mA:5 IOUT:5 100 rnA
20
90
mV
45
mV
11.5 V :5 VIN :5 24 V 1 rnA :5 lOUT :5 40 rnA
8.55
10
9.45
V
11.5 V :5 VIN:5 VMax
1 rnA :5 lOUT :5 70 rnA
(Note 3)
8.55
9.45
V
1 rnA :5 lOUT :5 40 rnA
5.5
rnA
11.5 V :5 VIN :5 24 V
1.5
rnA
1 rnA :5 lOUT :5 40 rnA
0.1
rnA
Quiescent Current
Quiescent Current
Change
Typ
2.1
Iwith line
Iwith load
= 25°C, 10 Hz :5 f :5 100 kHz
lOUT = 5 rnA
f = 120 Hz, 15 V :5 VIN :5 25 V,
TJ = 25°C
TJ = 25°C
TJ = 25°C
Output Noise Voltage
TA
Temperature Coefficient of
VOUT
Ripple Rejection
Dropout Voltage
Peak Output / Short-Circuit
Current
ItA78L12AC
Electrical Characteristics
=
=
38
VIN
19 V, lOUT
40 rnA, O°C :5 TJ :5 125°C, CIN
unless otherwise specified. (Note 1)
70
ltV
-0.9
mV/oC
44
dB
1.7
V
140
rnA
= 0.33 ItF, COUT = 0.11tF,
Characteristic
Condition
Min
Typ
Max
Unit
Output Voltage
TJ
= 25°C
TJ = 25°C
11.5
12
12.5
V
120
250
mV
16 V :5 VIN :5 27 V
100
200
mV
1 rnA :5 lOUT :5 100 rnA
20
100
mV
1 rnA :5 lOUT :5 40 rnA
10
50
mV
Line Regulation
Load Regulation
TJ
Output Voltage
14.5 V :5 VIN :5 27 V
= 25°C
14.5 V :5 VIN :5 27 V 1 rnA :5 lOUT :5 40 rnA
11.4
12.6
V
14.5 V :5 VIN :5 VMax
1 rnA :5 lOUT :5 70 rnA
(Note 3)
11.4
12.6
V
Quiescent Current
Quiescent Current
Change
2.1
Iwith line
Iwith load
Output Noise Voltage
Temperature Coefficient of
VOUT
Ripple Rejection
Dropout Voltage
Peak Output / Short-Circuit
Current
16 V :5 VIN :5 27 V
1 rnA :5 lOUT :5 40 rnA
= 25°C, 10 Hz :5 f :5 100 kHz
lOUT = 5 rnA
f = 120 Hz, 15 V :5 VIN :5 25 V,
TJ = 25°C
TJ = 25°C
TJ = 25°C
TA
Notes on I'A78L 15 page.
2·46
37
5.5
rnA
1.5
rnA
0.1
rnA
80
ltV
-1.0
mV/oC
42
dB
1.7
V
140
rnA
p,A 78LOO Series
/LA78L 15AC
Electrical Characteristics
VIN = 23 V, lOUT = 40 mA, O·C .:s TJ
unless otherwise specified. (Note 1)
.:s
125·C, CIN
= 0.33 /LF, COUT = 0.1 /LF,
Characteristic
Condition
Min
Typ
Max
Unit
Output Voltage
TJ
= 25·C
TJ = 25·C
14.4
15
15.6
V
17.5 V
130
300
mV
20 V
110
250
mV
25
150
mV
12
75
mV
14.25
15.75
V
14.25
15.75
V
5.5
mA
1.5
mA
0.1
mA
Line Regulation
Load Regulation
TJ
= 25·C
17.5 V
Output Voltage
.:s VIN .:s 30 V
.:s VIN .:s 30 V
1 mA .:s lOUT .:s 100 mA
1 mA .:s lOUT .:s 40 mA
1 mA .:s lOUT .:s 40 mA
.:s
VIN
17.5 V .:s VIN
(Note 2)
.:s
.:s
30 V
VMax
1 mA
.:s lOUT .:s
70 mA
Quiescent Current
Quiescent Current
Change
2.2
Iwith line
.:s VIN .:s 30 V
1 mA .:s lOUT .:s 40 mA
TA = 25·C, 10 Hz .:s f .:s
20 V
Iwith load
Output Noise Voltage
Temperature Coefficient of
VOUT
lOUT
Ripple Rejection
f = 120 Hz, 18.5 V
TJ = 25·C
100 kHz
= 5 mA
.:s
VIN
.:s 28.5 V,
34
= 25·C
TJ = 25·C
Dropout Voltage
TJ
Peak Output / Short-Circuit
Current
Not••
1. The maximum steady state usable output current and input
voltage are very dependent on the heat sinking and I or lead
length of the package. The data above represent pulse test
90
/LV
-1.3
mV/·C
39
dB
1.7
V
140
mA
conditions with junction temperatures as indicated at the
initiation of tests.
2. Power Dissipation :S .75 W.
Typical Performance Curves
Quiescent Current as a
Function of
Input Voltage
7D
1
..
.
.....""
~
I
z
:>
"
••
••
2.
10
o
50
10
15
1
I~
I
I
20
25
30
INPUT VOLTAGE - Y
.- ---......
78~05
.2
t-
I
•
6
3•
Quiescent Current as a
Function of Temperature
•
>
I
~~
.
f--
_f-r-
z
"
J.LO~ -
YOUT =SOY
= 40 mA
= 25°C
TJ
••
Dropout Voltage as a
Function of
Junction Temperature
lOUT - 70
!--
'OUT
m~
= 40
",l
-
-~UT-10,"A--= F -
•
t.LJ-
•• .......
• .......
........
3•
........
•
........
'\.
2
_ DROPOUT CONDITIONS
..
.l.VOUT = 511!. OF YOUT
•
25
75
'00
JUNCTION TEMPERATURE _ °C
Not.
Other "A78LOO Series devices have similar curves.
2-47
i\
v," "" 10 V
0 - YOUT =5V
5
'26
•
'i
U
'
I· "l mA
2.
••
7'
AMBIENT t::EMPEAATURE _
100
cc
125
#LA 78LOO Series
Typical Performance Curves (Cont.)
Ripple Rejection as a
Function of Frequency
Dropout Characteristics
.0
Jouo ~.J
r>
I
.
g~
~
o
1
60
!8LO!-
T( i"jC
'8
I~UT ~,olmA
~
z
o
W
~
'"
i'"
'\...IOUT = 100 mA
lOUT'" 40 mA ........
.0
'0
•. 0
INPUT VOLTAGE -
1
~
~
100
'0
g
0
20
"
I-- YiN
= 8 Y to 18 V
YOUT =5V
lOUT = 40 mA
0'0
'00
,.
200
,
I
0
~
00
~
20
~
1
~
2
DEVIATION
1'1
1
OJ
02
:Oyv
•
,2.
60
~:~::.; BOARD,
50
75
I
100
Design Considerations
The ~A78L series regulators have thermal overload
protection from excessive power, internal short-circuit
protection which limits each circuit's maximum
current, and output transistor safe-area protection for
reducing the output current as the voltage across
each pass transistor is increased.
""=~
125
150
Thermal Considerations
The TO-92 molded package manufactured by Fairchild
is capable of unusually high power dissipation due to
the lead frame design. However, its thermal
capabilities are generally overlooked because of a
lack of understanding of the thermal paths from the
semiconductor junction to ambient temperature. While
thermal resistance is normally specified for the device
mounted 1 cm above an infinite heat sink, very little
has been mentioned of the options available to
improve on the conservatively rated thermal
capability.
Although the internal power dissipation is limited, the
junction temperature must be kept below the maximum
specified temperature (125°) in order to meet data
sheet specifications. To calculate the maximum
junction temperature or heat sink required, the
following thermal resistance values should be used:
TO-92
12
TIME-,..s
AMBIENT TEMPERATURE _ °C
TIME-#!II
Package
c-+10
~ 4" ~EAD LENGTHI~
00
50
-200 b
I"?I
0 12S"LEAD LENGTH
FROM PC BOARD,
0 1 t-- FREE AIR
~ 002
40
1
WITH 72°CIW/AT SINK
~ 00
ill
30
f
0125" LEAD LENGTH
FROM PC BOARD.
0"""
•
= r-ill
OUTPUT VOLTAGE
20
1 1
1 1
lOUT = 100 mA (RESISTIVE LOAD)
YOUT =5V
I I
is
I- ~~UT :
-2
o
10
I OUT:~V~:'::~~AGE_ - f -
I
i
~ ,
o
100 k
'0 •
-100
2
,
,
TO-92 Worst Case Power
Dissipation Versus
Ambient Temperature
.
r-+-
~
o
FREQUENCY - Hz
z
o
~
~ 200
V
i.LO~
1
LOAD CURRENT
300
.0
'0
Load-Transient Response
>
I
~
i'L~-
1 1
INPUT VOLTAGE
~
r-ITJIII ~r·111I
J
2.0
'00
I
.0
;;J
W<
.. 0
~.l~;-
I
'"
40
Line Transient Response
'00
Typ
Max
Typ
Max
8JC
8JC
8JA
8JA
160
175
An explanation of the thermal paths of the TO-92 will
allow the designer to determine the thermal stress he
is applying in any given application.
2-48
J-LA 78LOO Series
shortening the lead length from package base to
mounting medium. However, one point must be kept
in mind. The lead thermal path includes a thermal
resistance, /lSA, from the pins at the mounting point
to ambient, that is, the mounting medium. /lLA is
then equal to /lLS + /lSA. The new model is shown
in Figure 2.
The TO·92 Package
The TO-92 package thermal paths are complex. In
addition to the path through the molding compound to
ambient temperature, there is another path through
the pins, in parallel with the case path, to ambient
temperature, as shown in Figure 1.
The total thermal resistance in this model is then:
/lJA
=
In the case of a socket, /lSA could be as high as
270°C/W, thus causing a net increase in /lJA and a
consequent decrease in the maximum dissipation
capability. Shortening the lead length may return the
net /lJA to the original value, but pin sinking would not
be accomplished.
(/lJC + /lCA) (/lJL + /lLA)
/lJC + /lCA + /lJL + /lLA
Where:/lJC = thermal resistance of the case between
the regulator die and a point on the case
directly above the die location.
/lCA
In those cases where the regulator is inserted into a
copper clad printed circuit board, it is advantageous
to have a maximum area of copper at the entry points
of the pins. While it would be desirable to rigorously
define the effect of PC board copper, the real world
variables are too great to allow anything more than a
few general observations.
=thermal resistance between the case
and air at ambient temperature.
/lJL = thermal resistance from transistor die
through the collector lead to a point
1/16 inch below the regulator case.
/lLA = total thermal resistance of the
collector-base-emitter pins to
ambient temperature.
/lJA
=junction to
The best analogy for PC board copper is to compare it
with parallel resistors. Beyond some pOint, additional
resistors are not significantly effective; beyond some
point, additional copper area is not effective.
ambient thermal resistance.
TO·92 Thermal Equivalent Circuit
(Pin at Other Than Ambient Temperature)
Fig. 2
TO·92 Thermal Equivalent Circuit
Flg_ 1
fiJC
t
PE (WATTS)
t
filS
PE (WATTS)
eCA
eSA
TA
TA
'----~--~:II~--~
'----~t------i:III------l
Methods of Heat Sinking
With two external thermal resistances in each leg of a
parallel network available to the circuit designer as
variables, he can choose the method of heat sinking
most applicable to his particular situation. To
demonstrate, consider the effect of placing a small
72°C/W flag type heat sink, such as the Staver
F1-70-2, on the 78LXX molded case. The heat sink
effectively replaces the /lCA (Figure 2) and the new
thermal resistance, /I'JA, is
/I' JA
High Dissipation Applications
VOUT
~
C2
Rl
240 !l V,
= 145 ° C / W (assuming. 125 inch lead length)
V,N
The net change of 15°C/W increases the allowable
power dissipation to 0.86 W with an inserted cost of
1-2 cents. A still further decrease in /lJA could be
achieved by using a heat sink rated at 46°C/W, such
as the Staver FS-7A. Also, if the case sinking does not
provide an adequate reduction in total /lJA, the other
external thermal resistance, /lLA, may be reduced by
Cl
0.33pF
2·49
1
IL
-
VOUT
2
C2
0.1 pF
Il
10-30mA
RL
#LA 78LOO Series
When it is necessary to operate a ~A78LOO regulator
with a large input-output differential voltage, the
addition of series resistor A 1 will extend the output
current range of the device by sharing the total power
dissipation between A1 and the regulator.
Typical Applications
INPUT - - -.....--'-t
Cl
0.331'F
NOTE 2
A1 = VIN(Min) - VOUT - 2.0 V
IL(Max) + 10
Aegulator power dissipation at maximum input voltage
and maximum load current is now
= (V 1 -
VOUT) IL(Max)
+ V 1 10
where
V 1 = VIN(Max) - (IL(Max)
+ la) A 1
The presence of A 1 will affect load regulation
according to the equation:
load regulation (at constant VIN)
= load regulation (at constant V1)
+ (line regulation, mV per V)
X (AI) X (~IL).
As an example, consider a 15 V regulator with a
supply voltage of 30 ± 5 V, required to supply a
maximum load current of 30 mAo 10 is 4.3 mA, and
minimum load current is to be 10 mAo
A1 = 25 - 15 - 2 = 34.3 :;;: 240 n
30 + 4.3
8
V 1 35 - (30 + 4.3).24
35 -8.2
26.8 V
=
=
PO(Max) = (26.8 - 15) 30
= 354
=
+ 26.8 (4.3)
+ 115
= 470 mW, which permit operation up to 70°C
in most applications.
Line regulation of this circuit is typically 110 mV for an
input range of 25-35 V at a constant load current;
i.e. 11 mV IV.
Load regulation
C2
O.lI'F
NOTE 2
Notes
1. To specify an output voltage. substitute voltage value for "00".
2. Bypass Capacitors are recommended for optimum stability and
transient response and should be located as close as possible
to the regulator.
where la is the regulator quiescent current.
PO(Max)
2
t-'-.....- - - OUTPUT
= constant V 1 load regulation
(typically 10 mV, 10-30 mA IL)
+ (11
mV IV) X 0.24 X 20 mA
(typically 53 mV)
= 63 mV for a load current change of
20 mA at a constant VIN of 30 V.
2-50
~A109·~A209·~A309
FAIRCHILD
5 Volt Regulator
A Schlumberger Company
Linear Products
Description
The /.LA 109, /.LA209, and /.LA309 are complete 5 Volt
Regulators constructed using the Fairchild Planar
epitaxial process. These regulators employ internal
current limiting, thermal shutdown and safe-area
compensation making them essentially indestructible.
They are intended for use as local regulators,
eliminating noise and distribution problems associated
with single point regulation. If adequate heat sinking is
provided, they can provide over 1 A output current.
The /.LA109, /.LA209, and /.LA309 are intended primarily
for use with TTL and DTL logic and are completely
specified under worst case conditions to match the
power supply requirements of these logic families. In
addition to use as a fixed 5 V regulator, these devices
can be used with external components to obtain
adjustable output voltages and currents and as the
power pass element in precision regulators.
Connection Diagram
TO-3 Package
•
(Top View)
Case is connected to ground.
Order Information
Type
Package
/.LA 109
Metal
/.LA209
Metal
/.LA309
Metal
• OUTPUT CURRENT IN EXCESS OF 1 A
• SPECIFIED TO MATCH WORST CASE TTL AND
DTL REQUIREMENTS
• NO EXTERNAL COMPONENTS
• INTERNAL THERMAL-OVERLOAD PROTECTION
• OUTPUT TRANSISTOR SAFE-AREA
COMPENSATION
Absolute Maximum Ratings
Input Voltage
Internal Power Dissipation
Storage Temperature Range
Operating Junction
Temperature Range
Military Grade (/.LA 109)
Industrial Grade (/.LA209)
Commercial Grade (/.LA309)
Temperature (Soldering, 60 s)
35 V
Internally Limited
-65°C to +150°C
-55°C to +150°C
-25°C to +150°C
O°C to 125°C
300°C
2-51
Code
HJ
HJ
HJ
Part No_
/.LA109KM
/.LA209KM
/.LA309KC
~A109·~A209·~A309
Equivalent Circuit
r---~~--------------~--------------~--------~------~----~~---1
R4
100 kn
R1B
500 n
R8
R9
100 n
100 II
INPUT
R13
10 kll
08 ~----~-----r=
014
012
R12
180 II
R5
3.3 kn
Rll
0.3 II
.J---
r:
TJ ==
45
100 125 150
150°1VI
VI; f-T"
/ VITI ~55"IC
~125.C
0
50
J,
w
"<~
--r- r=:
5
INPUT VOLTAGE -
V
Quiescent Current as a
Function of
Input Voltage
10
T"
CL
E
...
49
v"
"
-15 -50
=
0
ffi
w
\
10 V
20 mA
25
I
........
'\
~
g
25°C
0
< 5.01-+-+-+-+-+++-+-+-+-+--1
t'-- i'...
50
•
>
:J
25
25
IL
I-
~
0
20
A
Output Noise Voltage as a
Function of Frequency
1
~
r--
5.5
JUNCTION TEMPERATURE _ °C
Hz
~150"C
INPUT VOLTAGE -
( 101 mY
25
15
10
Hz
40
50
--
~ "'"""'-..."
Dropout Characteristic
&
h"'200::
I·
50
1 M
0
75
TJ == -55°C
VOUT=45V
Dropout Voltage
>
o
I.
510 11
r:
500 mA
o
10
1oor--..,..,..-.,-----,--.,-----,
20
...:J
/.c
FREQUENCY -
Ripple Rejection as a
Function of Frequency
w
Yr---
..-
AMBIENT TEMPERATURE _ °C
FREQUENCY -
r- ~
~
i
~
c 3.0
...I
"
~
g
w
'"
(;
0
'"'"
o
1
:J
/
~ 4.01-¥-+-+-++++-+-+-+-+--I
~
:;
Z
25
50
75
100 125 150
JUNCTION TE""PERATURE _ °C
I
o
001
10
100
1k
FREQUENCY - Hz
2-54
10 k
3.0 5! '-'--''''0--'--'15:--''-:2'="0-'--2'''5--'-':30--'-'35
INPUT VOLTAGE -
Y
~A109·~A209·~A309
Typical Performance Curves for /LA 109 and /LA209 (Cont.)
Quiescent Current as a
Function of Temperature
48
v,; lL
=
~
46
E
...I
44
~
...
42
ffi
0
ffi
il!
:;
"
. /I -
V
V
4.0
-
~=O
r:::: ~ .....
~L=1A
•
38
36
~75
~50
~25
0
25
50
75
100 125 150
JUNCTION TEMPERATURE _ DC
Typical Performance Curves for /LA309
Output Voltage as a
Function of
Junction Temperature
10
1
,
4. 0
V'N
TA
~ .......
I
w 50
"~
~ 49
"
VIN = 10 V
= 20 mA
I,
/
§
100
75
't===: 1:=1,
~ f--I,
.
~
80
.
~
-
1 k
10 k
100 k
5.0
10
20
15
25
INPUT VOLTAGE -
TJ
='
"'"
30
55
I 5.0
w
........
125°~ ~
~
1.01-=::f-----;I-'=-..;;.=--+-'=-i
05~--~----+---_+--~~-.~
== 200 mA
TJ =
g
5~ 45
p
1 k
10 k
FREQUENCY -
100 k
Hz
1 M
°0~--~2~5--~~~---7~5~~1~00~~,25
JUNCTION TEMPERATURE _
2·55
ac
125O~
/;
o"
== 10 V
=
35
Dropout Characteristic
>
1\\
...........
V
==-
" 3Vr
100
r----...
201'-_....
i< 40
20
10
...........
iL
I--
...........
t----., To = "d·c
I
Hz
\
~Vr
TJ = 2SoC_
-.K
0
1 M
Dropout Voltage
= 25"C
i!.
t--- YIN
J
r---...
o
100
25r----r----r----r----~--_,
,,"J
.,./
z
;:
0
500 mA
FREQUENCY -
1\
-
"l!:
"o
I -.......
VQUT=45V
JUNCTION TEMPERATURE _ °C
100
20 rnA
,
10
Ripple Rejection as a
Function of Frequency
2. 0
o
...
/
.........
(
a:
1050
3.
...I
ffi
""
4.8
25
:~.~=
~
........
g
5
o
Peak Output Current as a
Function of
Output Voltage
Output Impedance as a
Function of Frequency
40
5
VI
TJ = 25"C
-r
II
INPUT VOLTAGE - Y
=1,
A
~A109·~A209·~A309
Typical Performance Curves for jlA309 (Cont.)
Quiescent Current as a
Function of
Input Voltage
•.0
I,
.
E
I
>-55
~
~
\.~o~ :.-
:J
(,)
ffi
~ 5,0
~
10
~ 200imA
YIN
I--
10
~
TJ = 12[C
1
15
20
25
00 1
10
INPUT VOLTAGE ..... V
4.5
100
1 k
FREQUENCY -
Typical Applications
Fixed 5 V Regulator
INPUT--.-"I
10 V
,,=~~
50
lL"" l -
J
-=::: ~"""""'=O
-
1
4. 5
50
25°C
0
"-
/
I
•. 0
TJ
C,
-
-
Quiescent Current as a
Function of
Junction Temperature
Output Noise Voltage as a
Function of Frequency
OUTPUT
SV
Cl
0.22 MF
NOTE
Note
Bypass capacitors are recommended for optimum stability and
transient response and should be located as close as possible to
the regulator.
2·56
Hz
10k
o
25
50
75
100
JUNCTION TEMPERATURE _ °C
125
J.lA 7900 Series
3-Terminal Negative
Voltage Regulators
I=AIRCHILC
A Schlumberger Company
Linear Products
Description
The IlA7900 series of Monolithic 3-Terminal Negative
Regulators is manufactured using the Fairchild Planar
epitaxial process. These negative regulators are
intended as complements to the popular IlA7800
series of positive voltage regulators, and they
are available in the same voltage options from
-5 to -15 V. The 7900s employ internal currentlimiting, safe-area protection, and thermal shutdown,
making them virtually indestructible.
Connection Diagram
TO-3 Package
'"Q"'
•
COMMON
(Top View)
•
•
•
•
•
•
OUTPUT CURRENT IN EXCESS OF 1 A
INTERNAL THERMAL-OVERLOAD PROTECTION
INTERNAL SHORT-CIRCUIT CURRENT LIMITING
OUTPUT TRANSISTOR SAFE-AREA
COMPENSATION
AVAILABLE IN THE TO-220 AND
THE TO-3 PACKAGE
OUTPUT VOLTAGES ARE 5, 8,12 and 15 V
Absolute Maximum Ratings
Input Voltage
(5 V through 18 V)
Internal Power Dissipation
Storage Temperature Range
TO-3 (Aluminum or Steel)
TO-220
Operating Junction
Temperature Range
Military (IlA7900)
Commercial (IlA7900C)
Pin Temperature
TO-3 (Soldering, 60 s)
TO-220 (Soldering, 10 s)
Order Information
Type
Package
IlA7905
Metal
IlA7908
Metal
IlA 7912
Metal
IlA7915
Metal
IlA7905C
Metal
IlA7908C
Metal
IlA7912C
Metal
IlA7915C
Metal
-35 V
Internally Limited
Code
HJ
HJ
HJ
HJ
HJ
HJ
HJ
HJ
Part No.
IlA7905KM
IlA7908KM
IlA7912KM
IlA7915KM
IlA7905KC
IlA7908KC
IlA7912KC
IlA7915KC
Connection Diagram
TO-220 Package
-65°C to +150°C
-55°C to +150°C
@>I
-55°C to +150°C
O°C to +125°C
'--,N
(Top View)
Order Information
Type
Package
IlA7905C
Molded Power
IlA7908C
Molded Power
Molded Power
IlA7912C
Molded Power
IlA7915C
Note
The conventIon for NegatIve Regulators IS the Algebraic value,
thus -15 IS less than -10 V.
2-57
Pack
Pack
Pack
Pack
Code Part No.
GH
IlA7905UC
GH
IlA7908UC
IlA7912UC
GH
IlA7915UC
GH
,."A7900 Series
Equivalent Circuit
r-----.---------------.---------~--~----------------~--------------~r_--------~----~-COMMON
1
R2
Uk
D2
R25
4.Sk
TO 6.3 k
R23
4k
04
Rl
7.8k
R20
17.2k
I
I
R24
I
II
1.7k
T018k
-12VTO
-24 V
R4
2.2k
I OPTIONS
-1/ .-----I---If--------I
OUTPUT
2
RS
420
01
020
R19
S.3k
R14
2.3k
R16
4.7k
R17
3k
R21
17k
R30
200
R22
0.04
R13
O.os
INPUT
3
2-58'
/.LA 7900 Series
~A7905
Electrical Characteristics
VIN = -10 V,IOUT = 500 mA, CIN = 2 ~F, COUT = 1 ~F, -55°C:::; TJ:::; 150°C, unless
otherwise specified.
Characteristic
Condition (Note)
Min
Typ
Max
Unit
Output Voltage
TJ = 25°C
-4.8
-5.0
-5.2
V
Line Regulation
TJ = 25°C
-7 V :::; VIN :::; -25 V
3
50
mV
-8 V :::; VIN :::; -12 V
1
25
mV
5 mA :::; lOUT:::; 1.5 A
15
100
mV
250 mA :::; lOUT:::; 750 mA
5
25
mV
-5.30
V
Load Regulation
TJ = 25°C
Output Voltage
-8.0 V :::; VIN :::; -20 V
5 mA :::; lOUT:::; 1.0 A
p:::; 15 W
Quiescent Current
TJ = 25°C
2.0
mA
Iwith line
Quiescent Current Change I
with load
-8 V :::; VIN :::; -25 V
1.3
mA
5 mA :::; lOUT:::; 1.0 A
0.5
mA
Output Noise Voltage
TA = 25°C, 10 Hz:::; I:::; 100 kHz
80
~V!VOUT
Ripple Rejection
1 = 120 Hz, -8 V :::; VIN :::; -18 V
Dropout Voltage
lOUT = 1.0 A, TJ = 25°C
Peak Output Current
TJ = 25°C
-4.70
1.0
25
54
1.3
60
dB
1.1
2.3
2.1
3.3
A
V
Average Temperature Coefficient 01
Output Voltage
lOUT = 5 mA, -55°C:::; TJ:::; 150°C
0.3
mV lOCI
VOUT
Short·Circuit Current
VIN = -35 V, TJ = 25°C
1.2
A
~A7905C
Electrical Characteristics
VIN = -10 V, lOUT = 500 mA, CIN = 2
otherwise specified.
~F,
COUT = 1 ~F, O°C:::; TJ:::; 125°C, unless
.
Characteristic
Condition (Note)
Min
Typ
Max
Unit
Output Voltage
TJ = 25°C
-4.8
-5.0
-5.2
V
Line Regulation
TJ
-7 V :::; VIN :::; -25 V
3.0
100
mV
= 25°C
TJ = 25°C
Load Regulation
-8 V :::; VIN :::; -12 V
1.0
50
mV
5 mA :::; lOUT:::; 1.5 A
15
100
mV
250 rnA:::; lOUT:::; 750 mA
5.0
50
mV
-5.25
V
Output Voltage
-7 V :::; VIN :::; -20 V
5 mA :::; lOUT:::; 1.0 A
p:::; 15 W
Quiescent Current
TJ = 25°C
Iwith line
Quiescent Current Change]
-7 V :::; VIN :::; -25 V
with load
-4.75
1.0
5 mA :::; lOUT:::; 1.0 A
Output Noise Voltage
TA = 25°C, 10 Hz:::; 1 :::; 100 kHz
Ripple Rejection
1 = 120 Hz, -8 V:::; VIN:::; -18 V
2.0
mA
1.3
mA
0.5
54
mA
125
~V
60
dB
Dropout Voltage
lOUT = 1.0 A. TJ = 25°C
1.1
V'
Peak Output Current
TJ = 25°C
2.1
A
Average Temperature Coefficient 01
Output Voltage
lOUT = 5 mAo O°C :::; TJ :::; 125°C
0.4
mV/oC
Note
1. All characteristics except noise voltage and ripple rejection
ratio are measured using pulse techniques (tW :$ 10 ms, duty
cycle :$ 5%). Output voltage changes due to changes in
internal temperature must be taken into account separately.
2-59
.,
•
J-LA 7900 Series
/LA7908
Electrical Characteristics
=
=
VIN -14 V,IOUT 500 mA, CIN
otherwise specified.
= 2/LF, COUT = 1/LF, -55°C:5 TJ:5
150°C, unless
Characteristic
Condition (Note)
Min
Typ
Max
Unit
Output Voltage
TJ
-7.7
-8.0
-8.3
V
Line Regulation
= 25°C
TJ = 25°C
-10.5 V :5 VIN :5 -25 V
6.0
80
mV
-11 V :5 VIN :5 -17 V
2.0
40
mV
Load Regulation
TJ
5 mA:5 IOUT:5 1.5 A
12
100
mV
250 mA :5 lOUT :5 750 mA
4.0
40
mV
-8.4
V
2.0
mA
= 25°C
Output Voltage
-11.5 V :5 VIN :5 -23 V
5 mA :5 IOUT:5 1.0 A
p:5 15 W
Quiescent Current
TJ
-7.6
= 25°C
1.0
Iwith line
Quiescent Current Change I
with load
-11.5 V :5 VIN :5 -25 V
1.0
mA
5 mA:5 IOUT:5 1.0 A
0.5
mA
Output Noise Voltage
TA
80
/LVIVOUT
Ripple Rejection
f
Dropout Voltage
= 25°C, 10 Hz:5 f:5 100 kHz
= 120 Hz, -11.5 V :5 VIN :5 -21.5 V
lOUT = 1.0 A, TJ = 25°C
Peak Output Current
TJ
= 25°C
Average Temperature Coefficient of
Output Voltage
lOUT
Short-Circuit Current
VIN
/LA7908C
Electrical Characteristics
25
54
1.3
= 5 mA, -55°C
60
2.3
2.1
3.3
A
0.3
mV/oC/
VOUT
1.2
A
:5 TJ:5 150°C
= -35 V, TJ = 25°C
=
=
VIN
-14 V, lOUT
500 mA, CIN
otherwise specified.
dB
1.1
= 2 /LF, COUT = 1 /LF, O°C :5 TJ :5
V
125°C, unless
Characteristic
Condition (Note)
Min
Typ
Max
Unit
Output Voltage
TJ = 25°C
-7.7
-8.0
-8.3
V
Line Regulation
TJ=25°C
-10.5 V :5 VIN :5 -25 V
6.0
160
mV
-11 V :5 VIN :5 -17 V
2.0
80
mV
5 mA :5 lOUT :5 1.5 A
12
160
mV
250 mA :5 lOUT :5 750 mA
4.0
80
mV
-8.4
V
2.0
mA
Load Regulation
TJ = 25°C
Output Voltage
-10.5 V :5 VIN :5 -23 V
5 mA :5 IOUT:5 1.0 A
P :5 15 W
Quiescent Current
TJ = 25°C
-7.6
1.0
Iwith line
Quiescent Current Change I
with load
-10.5 V :5 VIN :5 -25 V
1.0
mA
5 mA:5 IOUT:5 1.0 A
0.5
mA
Output Noise Voltage
TA = 25°C, 10 Hz :5 f :5 100 kHz
Ripple Rejection
f = 120 Hz, -11.5 V :5 VIN:5 -21.5 V
Dropout Voltage
200
/LV
60
dB
lOUT = 1.0 A, TJ = 25°C
1.1
V
Peak Output Current
TJ=25°C
2.1
A
Average Temperature Coefficient of
Output Voltage
lOUT
0.6
mV/oC
= 5 mA, O°C
:5 TJ :5 125°C
Note
1. All characteristics except noise voltage and ripple rejectoon
ratio are measured using pulse techniques (tw :oS 10 ms, duty
cycle :oS 5%). Output voltage changes due to changes 10
IOternal temperature must be taken into account separately
2·60
54
JLA 7900 Series
ItA7912
Electrical Characteristics
VIN = -19 V, lOUT = 500 mA, CIN = 2 ItF, COUT = 1 ItF, -55 ° C ~ T J :s 150 ° C, unless
otherwise specified.
Characteristic
Condition (Note)
Min
Typ
Max
Output Voltage
TJ = 25°C
-11.5
-12.0
-12.5
V
10
120
mV
3.0
60
mV
12
120
mV
4.0
60
mV
-12.6
V
Line Regulation
TJ = 25°C
Load Regulation
TJ = 25°C
-14.5 V
~
VIN
5 mA
:s
lOUT
~
1.5 A
250 mA ~ lOUT ~ 750 mA
Output Voltage
Quiescent Current
TJ = 25°C
Iwith line
Quiescent Current Change I
with load
-15 V
5 mA
Output Noise Voltage
TA = 25°C, 10 Hz
~
Ripple Rejection
f = 120 Hz, -15 V
:s
Dropout Voltage
lOUT = 1.0 A, TJ = 25°C
Peak Output Current
-30 V
-16V~VIN~-22V
-15.5 V ~ VIN:S -27 V
5 mA ~ lOUT ~ 1.0 A
P :s 15 W
-11.4
3.0
mA
VIN
~
-30 V
1.0
mA
lOUT
~
1.0 A
0.5
mA
80
ItVIVOUT
:s
~
~
1.5
Unit
~
f
100 kHz
VIN:S -25 V
25
54
1.3
TJ = 25°C
60
dB
1.1
2.3
2.1
3.3
A
V
Average Temperature Coefficient of
Output Voltage
lOUT = 5 mA, -55°C ~ TJ:S 150°C
0.3
mV / °C/
VOUT
Short-Circuit Current
VIN = -35 V, TJ = 25°C
1.2
A
ItA7912C
Electrical Characteristics
VIN = -19 V, lOUT = 500 mA, CIN = 2 ItF, COUT = 1 ItF, O°C ~ TJ
otherwise specified.
Characteristic
Condition (Note)
Output Voltage
TJ=25°C
Line Regulation
TJ = 25°C
Load Regulation
TJ = 25°C
-14.5 V
~
VIN
:s
250 mA
lOUT
~
Output Voltage
-14.5 V :s VIN ~ -27 V
5 mA :s lOUT ~ 1.0 A
P ~ 15 W
Quiescent Current
TJ = 25°C
Iwith line
Quiescent Current Change I
-14.5 V
with load
5 mA
~
Typ
-11.5
-12.0
-12.5
V
10
240
mV
3.0
120
mV
1.5 A
12
240
mV
~
4.0
120
mV
-12.6
V
3.0
mA
~
-30 V
750 mA
-11.4
1.5
VIN:S -30 V
:s lOUT ~
1.0 A
Output Noise Voltage
TA = 25°C, 10 Hz
Ripple Rejection
f=
Dropout Voltage
Peak Output Current
Average Temperature Coefficient of
Output Voltage
~
lOUT
:s f :s
125°C, unless
Min
-16V:SVIN~-22V
5 mA
:s
100 kHz
Max
Unit
1.0
mA
0.5
mA
300
ltV
60
dB
lOUT = 1.0 A, TJ = 25°C
1.1
V
TJ = 25°C
2.1
120Hz,-15V:SVIN~-25V
lOUT = 5 mA, O°C:S TJ:S 125°C
Note
1. All characteristics except noise voltage and ripple rejection
ratio are measured using pulse techniques (tw :s: 10 ms. duty
cycle :s: 5%). Output voltage changes due to changes in
internal temperature must be taken into account separately.
2·61
54
0.8
A
mV/oC
•
JlA 7900 Series
/LA7915
Electrical Characteristics
=
=
= 2/LF, COUT = 1/LF, -55°C S
VIN -23 V, lOUT 500 mA, CIN
otherwise specified.
TJ S 150°C, unless
Characteristic
Condition (Note)
Min
Typ
Max
Unit
Output Voltage
= 25°C
TJ = 25°C
-14.4
-15.0
-15.6
V
TJ
s -30 V
s -26 V
5 mA s lOUT s 1.5 A
TJ = 25°C
250 mA s lOUT s 750 mA
-18.5 V s VIN s -30 V
5 mA s lOUT s 1.0 A
P s 15W
Line Regulation
Load Regulation
Output Voltage
Quiescent Current
-17.5 V
-20 V
s
s
VIN
VIN
5 mA
Output Noise Voltage
TA
-18.5 V
s
s
lOUT
s
s
lOUT = 1.0 A, TJ = 25°C
Peak Output Current
TJ = 25°C
Average Temperature Coefficient of
Output Voltage
lOUT = 5 mA, -55°C
Short-Circuit Current
VIN
Condition (Note)
Output Voltage
TJ
s
TJ
s
= 25°C
TJ = 25°C
= 25°C
-17.5 V
-20 V
5 mA
s
s
s
250 mA
s
VIN
VIN
lOUT
s
s
s
lOUT
-17.5 V s VIN s -30 V
5 mA s lOUT s 1.0 A
P s 15 W
Quiescent Current
75
mV
-15.75 V
TJ
dB
2.3
V
2.1
3.3
A
-1.0
1.3
mV lOCI
VOUT
1.2
A
s
Typ
Max
-14.4
-15.0
-15.6
V
11
300
mV
-30 V
mV
mV
s
4.0
150
mV
750 mA
-14.25
-15.75 V
= 120 Hz, -18.5 V s VIN s
= 1.0 A, TJ = 25°C
TJ = 25°C
100 kHz
f
-28.5 V
lOUT
lOUT = 5 mA, O°C
s
Note
1. All characteristics except noise voltage and ripple rejection
ratio are measured using pulse techniques (t w ::S 10 ms, duty
cycle ::S 5%). Output voltage changes due to changes in
internal temperature must be taken into account separately.
2·62
3.0
mA
1.0
mA
0.5
s
TJ
s
Unit
150
1.0 A
f
125°C, unless
Min
-30 V
s
s
300
Ripple Rejection
s
TJ
12
TA = 25°C, 10 Hz
lOUT
/LV IVOUT
3.0
Output Noise Voltage
s
s
mA
80
1.1
1.5
VIN
mA
0.5
1.5 A
5 mA
s
mA
1.0
60
1 /LF, O°C
= 25°C
-17.5 V
3.0
-26 V
Iwith line
Quiescent Current Change I
with load
Average Temperature Coefficient of
Output Voltage
54
150°C
= 2/LF, COUT =
Output Voltage
Peak Output Current
4.0
= -35 V, TJ = 25°C
Characteristic
Dropout Voltage
mV
25
1.3
VIN = -23 V, lOUT = 500 mA, CIN
otherwise specified.
TJ
150
1.0 A
Dropout Voltage
Load Regulation
12
-30 V
Ripple Rejection
Line Regulation
mV
mV
1.5
VIN
= 25°C, 10 Hz s f s 100 kHz
f = 120 Hz, -18.5 V s VIN s -28.5 V
/LA7915C
Electrical Characteristics
150
75
-14.25
TJ = 25°C
Iwith line
Quiescent Current Change I
with load
11
3.0
125°C
54
mA
375
/LV
60
dB
1.1
V
2.1
A
1.0
mV/oC
JLA 7900 Series
Typical Performance Curves
Worst Case Power
Dissipation as a
Function of
Ambient Temperature (TO-220)
100
J
50
40
30
;0
LIMIT FOR JiA7900C
Worst Case Power
Dissipation as a
Function of
Ambient Temperature (TO-3)
--
ro~::-;---'
~
~ 50 r- ,.....J. T8"S_-'· C1W
-7S"C/1V
if
3D
20
;0
~
4.0
10
Q 50
; 40
iii 3.0
~
30
~
20
10
S
20 ror
~ 1.0
~
~l
I'-
11
os
0.4
03 r-8JC
02 f- ~JA
........
........
"\l\
'\ l\
5"C/W
c/w
65"
PO(MAX} 15W
0.1
50
25
7S
100
125
"
i:::::: [ - NO HEAT SINI(
c
I I
10
I I
;0
o
05
o. 04
03
02
-(lJC
_
~)JA =
30
~
25
........
i
-DOS
!i~
-015
~ -020
YOUT'" -5 0 V AND
:J:±-r-
-Sot--
VOUT ",-12 VAND -15 y-
20
~
15
~
5
o
IOr=rmj
0
100
II
~
i
I II
o
10
J!t:.!;.t.DS: '
10
I
~
"
10k
10k
lOUT = 100 mA
YouT=-50Y
TJ=25"C
,
~
'30: " ""~
"\
15
20
COUT= 25/-1F
~~~~'~~~
,
111111111
10
30
25
100
>
".o.
"0
lOOk
o
1
,
,
10M
100M
.
1
o ~
"
!/"
1
1
1
30
2·63
~
or
1
40
50
INPUT VOLTAGE
30
1
20
10
1
1
g
1
TIME-I-Is
20
1
>
E
I
'\.
1
20
1M
40
!
I
V
10
lOOk
Line Transient Response
1
I
-1
10k
1
I
T
YOIL TAGE
f-L- f-0UTPUT
DEVIATION
Q
1k
FREQUENCY - Hz
1
-2
100
,
~,
I
.
"
.
•
75100125150
Output Impedance as a
Function of Frequency
f'
LOAD CURRENT
~
!:;
lOUT = 200mA
t
Q
\
.lVIN = 10 V pk-pk
I II
!
50
'Cour=10/-IF
SOLID TANTALUM
0
I'
lruy=-s.o'Y
AND -8 0 Y
TJ=25"C
o
V'N"'10V
VOUT = 5V
>=
~
25
~
I" :-.,
z
0
""........
...." r--,I"'
'11
1
II
20
25
~('4
rt-
JUNCTION TEMPERATURE- C
.'~.
~
"
I'-.
L~ :--. ",
>
II
'r l',orVT 1
C
Load Transient Response
V~f~ lSV
40
<0",
04
150
f
DROPOUT CONDITIONS
INPUTJOUTPUT OIFFERENTIAL- Y
III
II
0
'll
or
-....
~"
75 100 125 150 175
Ripple Rejection as a
Function of Frequency
60
125
0
1"'1-.:
50
lou
f00~
I
JUNCTION TEMPERATURE-" C
1
100
75
:::: t-
~111.q- ~
..... ::::1Z..<'oQ"'4
~
10
o
25
I
........ ~
I---
JO~
__ lOur
~ 06
VIN=VOUT-50V
-75 -50 -25
z
o
,\1'
55"C/W
~
~
....
5o. 08
5
~
'\ 1\
45° C/W
50
~
.~
:;j
-0.10
........
........
10
0.15
~
10
~
Peak Output Current as a
Function of Input-Output
Differential Voltage
~ 0.20
~
fE
ffi
AMBIENT TEMPERATURE _
Output Voltage as a
Function of
Junction Temperature
~
r-.
~
POIMAx)~15W
01
25
150
J 12
~
Q
ffi
>
e 8NFINI"rE ~EAr SINK
i= ......!8HS "'soCIW
i= ...J0l<1--7So C;IV ........
AMBIENT TEMPERATURE-" C
1::
14
I LIMIT FOR "A7900C l-
50
40
INFINITE HEAT SINK
20
Dropout Voltage as a
Function of
Junction Temperature
z
0
>=
~
.
"
.
".
Q
i -i - -
OUTP~T VOLTAGE+- rDEVIATION
I
~
o.
1
";!
I
10
~
!:;
"0
60
>
.
~
~
!
·10
lOUT =- 500 mA
VOUT =- 5 V
-20
o
10
TIME -
1-15
12
/.LA 7900 Series
Typical Performance Curves (Cont.)
Ripple Rejection as a
Function of Output Voltages
Qule8cent Current a8 a
Function of Temperature
Quiescent Current as a
Function of Input Voltage
23
25
V"I=V~u,-Jov
'OY=lmA
M~t-t-t-+-+-+-+-+-~
,,19
I
ffi
ll!
il...
~
!;j
::>
o
-c
vo!,J2vlND~'5l- c-r-.;,:;
.........
E
15
i!Z
r--.I'....
11
YOUT '" -5.0 Y AND -8 0
0.7
03
-75
-so
NOMINAl OUTPUT VOLTAGE- V
-25
0
25
50
75
VLT=tsv
15
il...
ffi1.D
u
"-
-r-.
2,0
E
I
r
~
V""- ......
L
.",
-5.0 V
5
o
05
o
100 125 150 175
0510152025303540
AMBIENTTEMPERATURE-oC
Design Considerations
The JlA7900 fixed voltage regulator series has
thermal-overload protection from excessive power
dissipation, internal short-circuit protection which
limits the circuit's maximum current, and output
transistor safe-area compensation for reducing the
output current as the voltage across the pass
transistor is increased.
VOUT
~
INPUTVOLTAGE-Y
Typical Applications
Bypass capacitors are recommended for stable
operation of the JlA7900 series of regulators over the
input voltage and output current ranges. Output
bypass capacitors will improve the transient response
of the regulator.
The bypass capacitors, (2 JlF on the input, 1 JlF on the
output) should be ceramic or solid tantalum which
have good high frequency characteristics. If aluminum
electrolytics are used, their values should be 10 JlF or
larger. The bypass capacitors should be mounted with
the shortest leads, and if possible, directly across the
regulator terminals.
Although the internal power dissipation is limited, the
junction temperature must be kept below the maximum
specified temperature (150'C for 7900, 125'C for
7900C) in order to meet data sheet specifications. To
calculate the maximum junction temperature or heat
sink required, the following thermal resistance values
should be used:
Fixed Output Regulator
Package
Typ
IJJC
'C/W
Max
IJJC
'C/W
Typ
IJJA
'C/W
Max
IJJA
'C/W
TO-3
3.5
5.5
40
45
TO-220
3.0
5.0
60
65
:......t
VIN _ _ _3
I-_--VOUT
1.0 l'F
High Current Voltage Regulator
TJ (Max) - TA
or
PO(MAX) = OJC + DCA
IJCA = IJCS
lOUT
r -__- - - - - _ - V O U T
+ IJSA (Without heat sink)
Solving for TJ: TJ = TA + Po (IJJC
Where TJ =
TA =
Po =
IJJA
IJJC
8CA
8cS
8SA
VIN-.......-""""'"
+ IJCA)
r1.
or TA + POIJJA (Without heat sink)
Junction Temperature
Ambient Temperature
Power Dissipation
Junction-to-Ambient Thermal Resistance
Junction-to-Case Thermal Resistance
Case-to-Ambient Thermal Resistance
Case-to-Heat Sink Thermal Resistance
Heat Sink-to-Ambient Thermal
Resistance
=
=
=
=
=
R1 = VSE(al)
IREG
2-64
lal
= ,6(Q1)IREG
0 1'F
JLA 7900 Series
High Output Current, Foldback Current Limited
......-'VI/'v-_--+"""-
VIN ......-
~------_-VOUT
R1
611
1.0!,F
•
High Output Current, Short·Circuit Protected
~------_-VOUT
R1
611
RSC
= VBE(Q2)
Isc
Operational Amplifier Supply (± 15 V @ 1.0 A)
+20 V
INPUT --~~'i
~~
___
~
_ _ _ _ _ _ +15V
OUTPUT
1N4001 OR
EQUIVALENT
-15 V
~--e---~-----OUTPUT
2-65
J.LA 79MOO Series
3-Terminal Negative
Voltage Regulators
FAIRCHILD
A Schlumberger Company
Linear Products
Description
The ILA79MOO series of 3-Terminal Medium Current
Negative Voltage Regulators are constructed using
the Fairchild Planar epitaxial process. These
regulators employ internal current limiting, thermal
shutdown and safe-area compensation making them
essentially indestructible. If adequate heat sinking is
provided. they can deliver up to 500 mA output
current. They are intended as fixed voltage regulators
in a wide range of applications including local
(on-card) regulation for elimination of noise and
distribution problems associated with single point
regulation. In addition to use as fixed voltage
regulators, these devices can be used with
external components to obtain adjustable output
voltages and currents.
Connection Diagram
TO-39 Package
COMM
1
Order Information
Type
Package
ILA79M05
Metal
ILA79M05C
Metal
ILA79M08
Metal
ILA79M08C
Metal
ILA79M12
Metal
ILA79M12C
Metal
ILA79M15
Metal
ILA79M15C
Metal
OUTPUT CURRENT IN EXCESS OF 0_5 A
INTERNAL THERMAL-OVERLOAD PROTECTION
INTERNAL SHORT CIRCUIT CURRENT LIMITING
OUTPUT TRANSISTOR SAFE-AREA
COMPENSATION
• AVAILABLE IN JEDEC TO-220
AND TO-39 PACKAGES
• OUTPUT VOLTAGES OF -5 V. -8 V, -12 V, and
-15V
-24 V
Internal Power Dissipation
Storage Temperature Range
TO-39
TO-220
Operating Junction
Temperature Range
TO-39
Military (ILA79MOO)
Commercial (ILA79MOOC)
TO-220
Commercial (ILA79MOOC)
Pin Temperature
(Soldering, 60 s) TO-39
(Soldering, 10 s) TO-220
IN
3
(Top View)
•
•
•
•
Absolute Maximum Ratings
Input Voltage
-5 V through -15 V
OUT
2
Code
FC
FC
FC
FC
FC
FC
FC
FC
Part No.
ILA79M05HM
ILA79M05AHC
ILA79M08HM
ILA79M08AHC
ILA79M12HM
ILA79M 12AHC
ILA79M15HM
ILA79M15AHC
Connection Diagram
TO-220 Package
-35 V
-40 V
Internally Limited
-65°C to +150°C
-55°C to +125°C
(Side View)
-55°C to +150°C
O°C to +125°C
Order Information
Type
Package
ILA79M05C Molded Power
ILA79M08C Molded Power
ILA79M12C Molded Power
ILA79M15C Molded Power
300°C
230°C
2·66
Pack
Pack
Pack
Pack
Code
GH
GH
GH
GH
Part No.
ILA79M05AUC
ILA79M08AUC
ILA79M12AUC
ILA79M15AUC
J.LA 79MOO Series
Equivalent Circuit
r-----~----------~------~--~------------_.------------~--------~--~-COMMON
1
R2
14k
R2S
4Sk
TOG 3k
R23
4k
R24
17k
T018k
RS
420
OUTPUT
01
2
R22
01
R30
200
R13
02
~----+-----+-----~----~~~~------------~--~~~----------~~----~~INPUT
3
/LA79M05HM
Electrical Characteristics
VIN = -10 V,IOUT = 350 rnA, -55°C::5 TJ::5 150°C, CIN = 2 /LF, COUT = 1 /LF, unless
otherwise specified. Notes 1 and 2
Characteristic
Condition (Note 3)
Min
Typ
Max
Unit
Output Voltage
TJ=25°C
-5.2
-5.0
-4.8
V
Line Regulation
TJ = 25°C
1-25 V ::5 VIN ::5 -7 V
7.0
50
mV
1-18 V ::5 VIN ::5 -8 V
Load Regulation
3.0
30
mV
TJ = 25°C, 5 rnA ::5 IOUT::5 500 rnA
75
100
mV
TJ = 25°C, 5 rnA ::5 lOUT ::5 350 rnA
50
Output Voltage
-25 V ::5 VIN ::5 -7 V
5 rnA ::5 lOUT ::5 350 rnA, PD ::5 4 W
Quiescent Current
TJ = 25°C
Iwith line
Quiescent Current Change 1
with load
-25 V ::5 VIN ::5 -8 V
5 rnA ::5 lOUT ::5 350 rnA
Output Noise Voltage
TA = 25°C, 10 Hz ::5 f ::5 100 kHz
Ripple Rejection
-4.75 V
1.0
IlOUT = 100 rnA
IlOUT = 300 rnA, TJ = 25°C
25
-18 V ::5 VIN::5 -8 V,
50
f = 120 Hz
54
Dropout Voltage
TJ = 25°C
Short-Circuit Current
TJ = 25°C, VIN = -35 V
0.5
lOUT = 5 rnA -55°C::5 TJ::5 +150°C
Notes on 79M05A page.
2-67
2.0
rnA
0.4
rnA
0.4
rnA
80
/LV IVOUT
dB
dB
60
1.1
Peak Output Current
Average Temperature Coefficient of
Output Voltage
-5.25
mV
0.65
2.3
V
0.6
A
1.4
A
0.3
mV / °C/
VOUT
JLA79MOO Series
p.A79M05AHC AND p.A79M05AUC
Electrical Characteristics VIN = -10 V, lOUT = 350 mA, -O°C ::5 TJ::5 125°C, CIN = 2 p.F, COUT = 1 p.F, unless
otherwise specified.
Characteristic
Condition (Note 3)
Min
Typ
Max
Unit
Output Voltage
TJ = 25°C
-5.2
-5.0
-4.8
V
Line Regulation
TJ = 25°C
1-25 V ::5 VIN ::5 -7 V
7.0
50
mV
1-18 V ::5 VIN ::5 -8 V
3.0
30
mV
TJ = 25°C, 5 mA::5 IOUT::5 500 mA
75
100
mV
TJ = 25°C, 5 mA::5 IOUT::5 350 mA
50
Load Regulation
-25 V ::5 VIN ::5 -7 V
5 mA ::5 lOUT ::5 350 mA, Po ::5 4 W
Output Voltage
TJ = 25°C
Quiescent Current
Quiescent Current Change
-5.25
1with line
Iwith load
Output Noise Voltage
mV
-4.75 V
1.0
2.0
mA
-25 V ::5 VIN ::5 -8 V
0.4
mA
5 mA ::5 lOUT ::5 350 mA
0.4
TA = 25°C, 10 Hz ::5 f ::5 100 kHz
mA
125
p.V
f = 120 Hz 1lOUT = 300 mA, TJ = 25°C 54
60
dB
Dropout Voltage
TJ = 25°C
1.1
V
Short-Circuit Current
TJ = 25°C, VIN = -30 V
140
mA
650
mA
0.4
mV/oC
Ripple Rejection
-18 V ::5 VIN ::5 -8 V, 1lOUT = 100 mA 50
Peak Output Current
Average Temperature Coefficient of
Output Voltage
lOUT = 5 mA
Notes
1. See Test CIrcuit.
2. The convenllon for negative regulators is the algebraIc values,
thus -15 V is less than -10 V
3 All characteristics except noise voltage and ripple rejection
ratio are measured using pulse techOlques 020
I
~g
1k
c
Output Impedance as a
Function of Frequency
0.15
\
25° C
.lJLl.JJJJ..l..illL.LlJlLL1wu
IIII..L11111llJ.
11l..lll.,J
"
100 125 150 175
JUNCTION TEMPERATURE -
"
1\
300
100
I I I I
75
"'"
•
40 0
~
0200
~YOUT
2
600
I
1
t--t--- r--
•
~
~
.oo
I
2
Peak Output Current as a
Function of Input-Output
Differential Voltage
Output Voltage as a
Function of
Junction Temperature
Dropout Voltage as a
Function of
Junction Temerature
, .f--+I\-"-I---+-..,....A~,.,,-t_+--I
VOUT- -5V
05;~-+--4-~--~--~-+--4-~
200 mA
vol'" =1 5 v I
2.
40
80
TIME -
1'5
2-72
••
10.
0,L.--~~,.--~,5L--2L.--2L5--~~~$--~4.
INPUT VOLTAGE-V
J.tA 79MOO Series
Typical Performance Curves (Cont.)
Worst Case Power Dissipation
Versus Ambient
Temperature TO-39
Quiescent Current as a
Function of Temperature
Worst Case Power Dissipation
Versus Ambient
Temperature TO-220
1.
23
-...
VIN '" VOUT -5 V
'JUT ;1200 mA
~ 19
I
;0
......... VOUT-
~
"r-.....
1
1
I
12VTO 24V
~
........
-...
VOUT--SVTO-8V
5
o. 7
..
3
-75
50
25
2S
so
-
10
ffi
OS
~
-...
~
$1"'1(
"'I"-
SINK
"-
•
04
.3
.2 r ~~; ~ ~:;o ~~
AMBIENT TEMPERATURE- 0 C
Typ
Max
Typ
Max
fJJC
fJJC
fJJA
fJJA
TO-39
18.0
25
120
160
TO-220
3.0
5.0
60
65
100
125
7S
AMBIENT TEMPERATURE- 0 C
150
=
=
=
Typical Applications
Bypass capacitors are recommended for stable
operation of the 79MOO series of regulators over the
input voltage and output current ranges. Output
bypass capacitors will improve the transient response
of the regulator.
Although the internal power dissipation' is limited, the
junction temperature must be kept below the maximum
specified temperature (150°C for 79MOO, 125°C for
79MOOAC and 79MOOC) in order to meet data sheet
specifications. To calculate the maximum junction
temperature or heat sink required, the following
thermal resistance values should be used:
Package
so
Where T J = Junction Temperature
TA = Ambient Temperature
Po = Power Dissipation
8JC = Junction-to-case thermal resistance
8CA
Case-to-ambient thermal resistance
8CS
Case-to-heat sink thermal resistance
8SA = Heat sink-to-ambient thermal resistance
8JA
Junction-to-ambientthermal resistance
The safe-area protection network may cause the
device to latch-up if the output is shorted and the
regulator is operating with high input voltages. This
mode of operation will not damage the device.
However, power (input voltage or the load) must be
interrupted momentarily for the device to recover from
the latched condition.
The bypass capacitors, (2 ~F on the input, 1 ~F on the
output) should be ceramic or solid tantalum which
have good high frequency characteristics. If aluminum
electrolytics are used, their values should be 10 ~F
or larger. The bypass capactiors should be mounted
with the shortest leads, and if possible, directly
across the regulator terminals.
Fixed Output Regulator
3
T J (Max)
2.0 MF
or
~ 1::
MA79MOO
2
VOUT
~ i== 1.0 I'F
1
(Without a heat sink)
=
HEAT
Pj
0
5
l-f - -
o
5
71IG
30
"~
5~
30
78G
INPUT VOLTAGE
o
~
~
o
25
! "~I
~
"~
0
>
OUTPUT VOLTAGE
DEVIATION
~
~
i!O
~
::>
"::>
~
20
I
r.
15
~
~
::>
,
0
" t'-.I'\
["-.,1"'
"'::--..
10
0
1
o
o
12
V
"~~. ',,~m
P
IOUT= SOOmA
10
io'
5
~~,I.~~ i"\
VOUT~SV
o
79G
~
~"
I
~
Your 50V
TJ=25°C
lOUT = 100mA
~",~
05
-1 0
-20
Quiescent Current vs
Input Voltage
10
15
f
20
25
30
0
10
INPUT-OUTPUT DIFFERENTIAL-V
15
20
25
30
35
40
INPUTVQLTAGE-¥
Typical Performance Curves for JLA79G (Cont.)
Control Current vs Temperature
Differential Control Voltage vs
Input Voltage
0
0
r-- I"--
79G
9
-2 0
8
"I
07
ffi
06
ll!
a
05
~
0
~
03
1\
i"""
"'-
2
VIN=-10Y
VouF'-5V
r-- !".
""
1
lOUT -=0 -350 rnA
75
50
25
0
2S
V
0
i'
?~;
0
'"
50
75
°v
-1 0
lOUT
r---
"0'
SOOmA
V
~
-8 0
I'"
19G
VOUT-'-50V
"f:t~~
'\
4
0
YIN-lOY
r-..
-6 0
~
"
0
79G
-4 0
\
Differential Control Voltage vs
Output Current
V
V
VouT=50V
100 125 150 175
-1 2
50
10
15
2S
20
30
INPUT VOLTAGE- V
JUNCTION TEMPERATURE- 0 C
Ripple Rejection vs
Output Voltage
600
400
800
1000
OUTPUT CURRENT -rnA
Dropout Voltage vs
Junction Temperature
80
0
200
Ripple Rejection vs Frequency
14
19G
79G
7lG
12
70
60
-r-.. r- lour~14
10
';-...
I'.
........
r- r--~~ t" -
8
'I'.
so
.......
C~~mITlONS
4 -'o\,Fr' O]0J'
10
15
20
OUTPUT VOLTAGE- V
25
30
75
~
rAi r-.....
IOU,.~
1
o
,.
•
tOY
VouT=5V
20
30
40
I
10 ~
,...
-5
.
5
~
OUTPUT VOLTAGE
DEVIATION
g
5
1\
\i
•
~
!
lOUT 5O(JmA
VouT=5V
40
60
eo
100
Design Considerations
The 78G and 79G adjustable voltage regulators have
an output voltage which varies from VCONTROL to
typically
ILA78G Test Circuit 1
OUT
VOUT
Y,N -2 V by VOUT
CONTROL
f---<
COMM
:;:
o. 1 "F
0.33 " F
R2
+10
COMM
= VCONTROL
(Al
+ A2)
A2
The nominal reference in the 78G is 5.0 V and
79G is -2.23 V. If we allow 1.0 rnA to flow in the
control string to eliminate bias current effects, we can
make A2 = 5 kfl in the 78G. The output voltage is then:
VOUT = (A 1 + A2) V, where A 1 and A2 are in kfls.
Rl
78G
IN
>
\
20
50
Test Circuits
-----
15
i\
Q
Q
~2
II
Z
o
1
YIN
INPUTYOLTAGE
Example:
If A2 = 5 kfl and Al = 10 kfl then
VOUT = 15 V nominal, for the 78G
~
A2 = 2.2 kfl and Al = 12.8 kfl then
VOUT = -15.2 nominal, for the 79G
R1 + R2)
VOUT = ( -R-2- VCONTROL
By proper wiring of the feedback resistors, load
regulation of the device can be improved significantly.
VCONTROL Nominal = 5 V
Both 78G and 79G regulators have thermal-overload
protection from excessive power, internal short-circuit
protection which limits each circuit's maximum
current, and output transistor safe-area protection for
reducing the output current as the voltage across
each pass transistor is increased.
ILA79G Test Circuit 2
OUT
I"
F
79G
VOUT
Rl
CONTROL
I---<
COMM
--;:: 1
r
R2
tlO
COMM
l
R1 + R2)
VOUT = ( ~ VCONTROL
VCONTROL Nominal = -2.23 V
Recommended R2 current "" 1 rnA
.". R2 = 5 kil (78/G)
R2 = 2.2 kil (79/G)
2~81
J.LA78G • J.LA79G
/-IA78G and /-IA79G
TO-3 Package
Worst Case Power Dissipation vs
Ambient Temperature
Test Circuit
Design Considerations (Cont.)
Although the internal power dissipation is limited, the
junction temperature must be kept below the maximum
specified temperature in order to meet data sheet
specifications. To calculate the maximum junction
temperature or heat sink required, the following
thermal resistance values should be used:
100
I LIMIT78G/79G- t,"~,
f- f-
Typ
°C/W
Max
°C/W
Typ
°C/W
Max
°C/W
Package
fiJC
fiJC
Power Watt
TO-3
7.5
11
fiJA
75
fiJA
80
4.0
6
44
47
8,
It- I-
,.1
::~.'!O/k
8,s~~
~~
.......
8M "'" aleC(It
"-
.......
"Or. .~ -...... "- ~~
0
t-... I'\: ~
I
IW
fJJA=4rC/W
fiJC-6°
TJ (max) - TA
TJ (max) - TA
or
Po (max) =
IJ JA
fiJC + fiCA
(Without a heat Sink)
IJCA = fics
Solving for TJ:
1
PDMAX~15W
25
=
150
Basic Positive Regulator
Where TJ Junction Temperature
TA = Ambient Temperature
Po = Power Dissipation
IJJA Junction to ambient thermal resistance
IJJC = Junction to case thermal resistance
fiCA = Case to ambient thermal resistance
IJcs = Case to heat sink resistance
IJSA = Heat sink to ambient thermal resistance
OUT 1--_._-_- +VOUT
=
+V,N ......_ - - ! I N 78G
CONTROL
COMMON
/-IA78G and /-IA79G
Power Tab (U1) Package
Worst Case Power Dissipation
vs Ambient Temperature
LIMIT 78GI79G
125
Typical Applications For /-IA78G
Bypassing of the input and output (0.33 /-IF and
0.1 /-IF, respectively) is necessary,.
TJ = TA + Po (IJJC + IJCA) or
TA + PolJJA (Without heat sink)
T
100
AMBIENT TEMPERATURE _ 0 C
+ IJSA
100
75
50
vOUT
= vCOUNT
R1
R2
( R1R+2R2)
lPositive 5 to 30 V Adjustable Regulator
--
f- f10
I~
10
l- I-/}JC.'
'''F~lJ
0tfs'~so 'e"'~/f
8H~
I",
NOHEA.TSIN
I
OUT I--<_........-
"-
-.....
~
r.....
"- \'
5 k
I"...
rC/w
.
+V,N ......---~ IN 78G
"'
r-.... i'\:
(/JA= 8O°C/W
PoMAX=15W
i'
75
100
125
150
AMBIENT TEMPERATURE- C
Q
2-82
.......-+VOUT
JLA78G • JLA79G
Typical Applications for
~A78G
(Cont.)
Positive High-Current Short-Circuit
Protected Regulator
Positive 5 V to 30 V Adjustable Regulator
lOUT> 5.0 A
01
V,N
-1--------------,
1>4DA-.
OUT~--'--~--~
!a L 2N6124
IN
78G
.33/1oFI
OUT
31l
IN 78G
+32 V
I '" 22DmA_
D.33/1oF
CONTROL
COMMON
-
L:
+VOUT
25 k
VOUT
;;Of 0 .1
/IoF
5 k
1
-
-
External series pass device is not short circuit protected.
Positive High-Current Short-Circuit
Protected Regulator
Rsc
2N6124
01
2N6124
-
OUT I -_ _............-+VOUT
31l
+VIN -
IOUTIMAXI
.....W\r-<.......--_---, -o2S
. o
0
4
~
1.
2.
15
5
"
2
••
1'",
o
YIN = 10 V
Your=SOY
'~U;
•
3.
25
Differential Control
Voltage as a
Function of
Output Current
2
II
,.
,/
•
l"-
i
~
"' 5~ t--t~ 1
g
o
•
•
I
2••
60.
400
OUTPUT CURRENT -
•••
45
1000
~4+~-+~~~!_~-+_7:.Ud~
!1l
~
t- ~•• LA
I-t--- j:::
t::: ~ri iA
125
Q
C
t-t-
M
;;]
;
it;;
+-
60~+H-+-++~~~H+-+-++H~
~
40~+H-+-++~~~H+-+-++H~
2.
!
~~u~ ~;o 18 V
l---++-I+-++-++--I
150
FREQUENCY - Hz
2-88
•
10
2.
15
OUTPUT VOLTAGE -
25
3.
V
Load Transient Response
4
z
o
~
~
LOAD CURRENT
1
2
"I
1
•
I
1
~
~
o
J'M"1b
111
o
g
I I
V'N = ,. v I
vo",=5V
>
I
~
lOUT == 500 mA
TJ = 25°C
DROPOUT CONDITIONS
.lVOUT = SOlo OF YOUT
100
•• 1-H:l:J::;oj..+4~+++-++-+-+++H
I
lOUT"" 500 rnA
75
1\
rnA
Ripple Rejection as a
Function of Frequency
i-t--- t-
5.
\
5.
-200
3.
25
JUNCTION TEMPERATURE -
\
TJ == 25°C
10T~1-
25
N
55
-17 5
i
I
z
o
150
be
lOUT = 200 mA
6.
-150
7BYG
1
t--.....
, •• r-rrrr-rTTTr,--,--rrr-r-rTT1--'
r-I- r-
125
7SMG
85
:;-125
'E
~
75
7.
100
5
~
"N.
••
t-....... ~~$OC
I
Dropout Voltage as a
Function of
Junction Temperature
~
........
r
INPUT VOLTAGE - V
o 2 .1-
100
I
/
,/
2.
15
r-.....
~ -75
I
TJ == 125°C
['-...
-5.
I
2
85
7aMG
YOVT = 5 V
-25
4
75
Ripple Rejection as a
Function of
Output Voltage
YIN -10 V
78MG
•
•
5.
AMBIENT TEMPERATURE _
Differential Control
Voltage as a
Function of
Input Voltage
•
~~
7351mf
25
INPUT ·OUTPUT DIFFERENTIAL - V
lOUT = 500 mA
YOUT == 5.0 V
r"'1'-... ......
I
r---...
~I--- I- OUTPUT VOL T]GE
DEVIATION
0
\/ I
1
I
-2
1
,.
2.
3.
TIME -
I\-
4.
~s
Z
~
a:
:J
c.>
~
I
o
l-
50
6.
JLA78MG • JLA79MG
Performance Curves For ",A78MG (Cont.)
Line Transient Response
40
E
I
I INPUT
30
z
0
;:
"
~w
1
>
I
20
1
I
I
w
"~
,
10
""~
g
' - - [ - OUTPUT VOLTAGE
[-
DEVIATION
o
-c--
...>
~
i!O
...
...::>~
20
IVO~T~~ -~i'M~
I
>
-10
lOUT == 500 mA
0
YOUT = 5 V
-20
.tI
1--
o
10
12
TIME -.u8
Typical Performance Curves for ",A79MG
Peak Output Current as a
Function of Input-Output
Differential Voltage
Quiescent Current as a
Function of Input Voltage
-15
.00
~
::I
.......
/'
600
400
~
300
!:;
o
200
\
100
DOC < TJ
o
...
<
IiS!
\
10
20
15
I........ r--.I
I'--
-40
-5
!
-12
-20
-25
25
30
35
40
Ii" j35Li
25
50
75
r---.. . .
100
125
150
JUNCTION TEMPERATURE- DC
Ripple Rejection as a
Function of
Output Voltage
79MG
79MG
,,/'
'8
V
0
..;"-"
I
2.0
~
V
/
70
I
z
~
...
60
~
400
600
OUTPUT CURRENT -
2-89
.00
mA
1000
'Our
f":,~"o
,"'4
w
[--[-
r-.....
50
40
200
'I'
;:
~
0
-30
"
YOUT = -50 V
o
o
.0
~
I
V
-15
20
.ov
10
INPUT VOLTAGE-V
-15
3.0
-.0
-10
-10
VIN=10Y
~
i
I""
02
1
VouT=50V
'"
I",
YIN = 10 V
40
'N~~
I
~ -60
-10
~
INPUT VOLTAGE - V
79~G
J
E
·50
03
~
Differential Control
Voltage as a
Function of
Output Current
"-
lOUT ==·2 A
YOUT == -50
~
o
U
V
Differential Control
Voltage as a
Function of
Input Voltage
~
04
::>
u
V
0
30
25
INPUT-OUTPUT DIFFERENTIAL -
>
...
i
./
-05
,
"T 05
/
125°C
o
-20
V
/
::>
u
ili
06
/
-10
a:
1\
79MG
/
E
...
U
~
79MG
TJ = 25°C
lOUT = -2 A
"I
'" '\.
500
07
YOUT - -50 V
79MG
700
~
I
Control Current as a
Function of Temperature
,~
o
10
15
20
OUTPUT VOLTAGE -
25
V
30
~A78MG
Performance Curves For
~A79MG
Dropout Voltage as a
Function of
Junction Temperature
1
>
I
i= 0.9
08
is
~
07
!;
o
06
~
~
Load Transient Response
79MG
79MG
LOAD CURRENT
!ll
.....
'0
I
0
~"'.
~,..."
IOUi"" 1
>=
~
.,......
'"w~
'ou r-",,<.
j,VOUT = 5%
50
O~TPJT
VblT1GE - DEVIATION
0
.0
I
!!,
I
'"
.......
o~ V~UT I
25
60
OJ
.....
~
~"'.
~I'--f'
I \
I
z
IOur",,~
o
2
I
05
o.
79MG
I
10
:I
~
It
(Cont.)
Ripple Rejection as a
Function of Frequency
IOU~500lmA - f -
r-i'-.
• ~A79MG
1
2
75
I
_~lN =10 V
100
125
10
150
100
JUNCTION TEMPERATURE _ °C
Ik
10 k
VOU'15~
10
100 k
I
20
30
.0
50
TIME-I's
FREQUENCY - Hz
~A78MG
and ~A79MG
Power Watt (U1)
Worst Case Power
Dissipation Versus
Ambient Temperature
Line Transient Response
100
79MG
~
INPUT VOLTAGE
I
z
I
o
~
o
w
~
-5
~
\
;0
~
\
J""'Irt
DEVIATION
I
I
10
~
'"
10
~
is
~_
~ "" 200CIW S.,
20
60
.0
100
--
i'-.
0.5
o.
-
03
02
TIME-,..s
100C
ltd "El 1""- ....... r-.,. f\
-~" i'..:
r-
12°C/W
'JC
POI MAX) "" 7 5 W
I
1
25
50
75
100
125
150
AMBIENT TEMPERATURE _ °C
Both 78MG and 79MG regulators have thermal
overload protection from excessive power, internal
short circuit protection which limits each circuit's
maximum current, and output transistor safe area
protection for reducing the output current as the
voltage across each pass transistor is increased.
Design Considerations
The 78MG and 79MG variable voltage regulators have
an output voltage which varies from VCONTROL to
(R1 + R2)
typically VIN -2 V by VOUT = VCONTROL
R2
The nominal reference in the 78MG is 5.0 V and 79MG
is -2.23 V. If we allow 1.0 mA to flow in the control
string to eliminate bias current effects, we can make
R2 = 5 kQ in the 78MG. The output voltage is then:
VOUT = (R1 + R2) Volts, where R1 and R2 are in kQs.
Example:
.-
I~FlNiTE ~EA~ SINt.
-5
\i
.0
LIMITS FOR C GRADE-
;g = ~
~ r<"'- ~ t--
vor=!"v I
20
I
-
o
lOUT'" 200 mA
0,
50
40
30
20
10
r- r- r-OUT~UT ~OL+AGE
!;
5
I
I
15
Although the internal power dissipation is limited, the
junction temperature must be kept below the maximum
specified temperature in order to meet data sheet
specifications. To calculate the maximum junction
temperature or heat sink required, the following
thermal resistance values should be used:
If R2 = 5 kQ and R1 = 10 kQ then
VOUT = 15 V nominal, for the 78MG;
R2 = 2.2 kQ and R1 = 12.8 kQ then
VOUT = -15.2 V nominal, for the 79MG.
By proper wiring of the feedback resistors, load
regulation of the devices can be improved
significantly.
2·90
Typical
Max
Typical
Max
Package
OJC
OJC
OJA
OJA
Power Watt
8.0
12.0
70
75
~A78MG· ~A79MG
PO(Max) =
Positive S to 30 V Adjustable Regulator
lOUT> 1.SA
TJ(Max) - TA
IJJC + IJCA or
(Without a heat sink) IJCA = IJCS
+ IJSA
Solving for TJ: TJ = TA + Po (IJJC
or TA + POIJJA (Without heat sink)
Where
,...-----,.
01 I> 1.5 A_
2N5124
+ IJCA)
+32
TJ = Junction Temperature
TA = Ambient Temperature
Po = Power Dissipation
IJJC
Junction-to-case thermal resistance
IJCA = Case-to-ambient thermal resistance
IJCS = Case-to-heat sink thermal resistance
IJSA Heat sink-to-ambient thermal
resistance
IJJA = Junction-to-ambient thermal resistance
OUT
Rl
5 n
v
120100mA0.33
+VOUT
IN 78MG
CONTROL
COMMON
~F
0.1
~F
5 k
=
•
=
R1
Typical Applications for ~A78MG
Bypass capacitors are recommended for stable
operation of the ~A78MG over the input voltage and
output current ranges. Output bypass capacitors will
improve the transient response of the regulator.
(1VSE(Ql)
IR(Max) «(3) -I(OUT)
± 10 V, SOO rnA Dual Tracking Regulator
1--........-_-+10 V
+15
The bypass capacitors, (0.33 ~F on the input, 0.1 ~F
on the output) should be ceramic or solid tantalum
which have good high frequency characteristics. The
bypass capacitors should be mounted with the
shortest leads, and if possible, directly across the
regulator terminals.
v -..._---1
0.33
78MG
5 k
~F
7.23
Basic Positive Regulator
2.0
~F
1.0
~F
79MG
OUT
IN 78MG
+VIN
0.33
~F
CONTROL I - COMMON
;
1
+VOUT
-15 V ' - - - - j
0 .1
~F
Note
External senes pass device
R2
R1
V
IS
not short CirCUit protected.
Positive High-Current Short-Circuit
Protected Regulator
RsC
VOUT = VCONT (
1-.......- - - -10
Rl
01
r.::
2N7:5"'12:-:4:------,
+ R2)
R2
Q2
2N290S
Positive S to 30 V Adjustable Regulator
51!
t-~~---~+VOUT
IOUT(MAX)
Rl
OUT 1-1~""""-""--+VOUT
+VIN--1~-4IN 78MG
0.33
~F
CONTROL
COMMON
25 k
0.1
~F
5k
(3VSE(Ql)
R1 = VR(Max) «(3 + 1) -IOUT(Max)
If load .s not ground referenced, connect reverse biased diodes
from outputs to ground.
2·91
JlA78MG· JlA79MG
Typical Applications for 79MG
Bypass capacitors are recommended for stable
operation of the JLA79MG over the input voltage and
output current ranges. Output bypass capacitors will
improve the transient response of the regulator.
Output Waveform
30V-------
/
/
/
/
The bypass capacitors, (2 JLF on the input, 1 JLF on the
output) should be ceramic or solid tantalum which
have good high frequency characteristics. If aluminum
electrolytics are used, their values should be 10 JLF ·or
larger. The bypass capacitors should be mounted with
the shortest leads, and if possible, directly across the
regulator terminals.
~64 STEPS
5vI
Ov----------------Positive High-Current Voltage Regulator
Negative High-Current Short-Circuit
Protected Regulator
External Series Pass (a)
Rsc
01
2N6121
+VIN ---<~--f IN OUT 1---_£
78MG
CONTROL
COMMON
02
2N2222
+VOUT
t-t-t-'-t--VOUT
6 II
-VIN ......HM......----,.,......,........~
R1
IRIMAX)
2.0 ~F
R1
IO~)
25 k
1.0
R2
2.2 k
j3VBE(Q1)
R1 = IR(Max) (/3) -IOUT(Max)
Basic Negative Regulator
OUT
Short-Circuit limit (b)
2.0
+VIN
0.33 ~F
I
-=-
IN
VOUT
IN 79MG
~
F*
CONTROL
r------o
1.0
~F
COMMON
1
OUT I-~_-i:.
78MG
R1
_L..
1'R2
_....
CONTROL
COMMON
L - -....._-+VOUT
VOUT = -VCONT (
R1
R1
+ R2)
R2
-30 V to -2.2 V Adjustable Regulator
OUT~t--...-...,...--VOUT
-VIN
2.0
~F
IN 79MG
CONTROL
COMMON
1.0
2.2 k
2-92
~F
~F
JLA78MG· JLA79MG
Negative High-Current Voltage Regulator
External Series Pass
79MG Test Circuit 2
OUT
--~~IN
OUT~~~L
IN
2N6124
79MG
Rl
CONTROL
COMM
-VOUT
CONTROL
COMMON
79MG
~_~_-VOUT
1 I'F
Rl
R2
R2
+ R2)
= ( R1 R2
VCONTROL
VCONTROL Nominally = -2.23 V
VOUT
78MG Test Circuit 1
OUT
-~
IN
VOUT
78MG
CONTROL
COMM
Recommended R2 current "'" 1 mA
... R2 = 5 kU (78MG)
R2 = 2.2 kU (79MG)
Rl
;::;;;; O.
~
0.33 I' F~
~IQ
R2
~
VOUT
+ R2)
= ( R1 R2
VCONTROL
VCONTROL Nominally = 5 V
2-93
•
Il A723
FAIRCHILD
Precision Voltage
Regulator
A Schlumberger Company
Linear Products
Connection Diagram
10-Pin Metal
Description
The IJ,A723 is a Monolithic Voltage Regulator
constructed using the Fairchild Planar epitaxial
process. The device consists of a temperaturecompensated reference amplifier, error amplifier,
power-series pass transistor and current-limit
circuitry. Additional NPN or PNP pass elements may
be used when output currents exceeding 150 mA are
required. Provisions are made for adjustable current
limiting and remote shutdown. In addition to the above,
the device features low standby current drain, low
temperature drift and high ripple rejection. The IJ,A723
is intended for use with positive or negative supplies
as a series, shunt, switching or floating regulator.
Applications include laboratory power supplies,
isolation regulators for low level data amplifiers, logic
card regulators, small instrument power supplies,
airborne systems and other power supplies for digital
and linear circuits.
•
•
•
•
•
CURRENT
LIMIT
v(Top View)
Pin 5 connected to case.
Order Information
Type
Package
IJ,A723
Metal
IJ,A723C
Metal
POSITIVE OR NEGATIVE SUPPLY OPERATION
SERIES, SHUNT, SWITCHING OR
FLOATING OPERATION
0.01% LINE AND LOAD REGULATION
OUTPUT VOLTAGE ADJUSTABLE FROM
2 TO 37 V
OUTPUT CURRENT TO 150 mA WITHOUT
EXTERNAL PASS TRANSISTOR
Absolute Maximum Ratings
Pulse Voltage from V+ to V-,
(50 ms) (IJ,A723)
Continuous Voltage from
V+ to VInpull Output Voltage
Differential
Differential Input Voltage
Voltage Between Non-Inverting
Input and VCurrent from Vz
Current from VREF
Internal Power Dissipation
(Note)
Metal
DIP
Storage Temperature Range
Operating Temperature Range
Military (IJ,A723)
Commercial (IJ,A723C)
Pin Temperature (Soldering)
Metal, Ceramic DIP (60 s)
Molded DIP (10 s)
Code
5X
5X
Part No.
IJ,A723HM
IJ,A723HC
Connection Diagram
14-Pin DIP
14
NC
CURRENT
LIMIT
50 V
CURRENT
SENSE
40 V
-IN
40 V
±5V
+IN
+8V
25 mA
15 mA
VREF
v-
800 mW
1000 mW
-65°C to +150°C
(Top View)
Order Information
Type
Package
IJ,A723
Ceramic DIP
IJ,A723C
Ceramic DIP
IJ,A723C
Molded DIP
-55°C to +125°C
O°C to +70°C
Notes on following pages.
2-94
Code
6B
6B
9B
Part No.
IJ,A723DM
IJ,A723DC
IJ,A723PC
J.LA723
Block Diagram
FREQUENCY
COMPENSATION
V+
TEMPERATURE
COMPENSATED
ZENER
Vc
INVERTING
INPUT
ERROR
AMPLIFIER
">--'--VREF
NON-INVERTING
INPUT
Your
•
Vz
VOLTAGE
REFERENCE
AMPLIFIER
CURRENT
LIMITER
V-
Equivalent Circuit
V+
R1
R3
500 Il
25 kll
Vc
03
01
Your
03
6.2 V
Vz
....- - - - - - - COMPENSATION
'}-_ _ _ _ _ _ _ ~I~~:ENT
R8
5 kll
~
VREF
NON-INVERTING VINPUT
Note
1. Rating applies to ambient temperatures up to 25°C. Above
25 ° C ambient derate based on the following thermal
resistance values:
OJA
Max
190
90
105
'Typ
TO-5
150
Molded DIP 80
Ceramic DIP 95
2-95
INVERTING
INPUT
_______________ CURRENT
SENSE
p,A723
/lA723
Electrical Characteristic
Characteristic
TA = 25°C, VIN = V+ = Vc = 12 V, V- = 0, VOUT = 5 V, IL = 1 mA, Rsc = 0,
C1 = 100 pF, CREF = 0, unless otherwise specified. Divider impedance as seen by error
amplifier::5 10 kfl connected shown in Figure 1. Line and load regulation specifications
are given for the condition of constant chip temperature. Temperature drifts must be
taken into account separately for high dissipation conditions.
VIN
Line Regulation
Min
Condition
VIN
= 12 V to VIN = 15 V
= 12 V to VIN = 40 V
Typ
Max
0.01
0.1
%VO
0.02
0.2
%VO
0.3
%VO
-55°C::5 TA::5 + 125°C, VIN = 12VtoVIN= 15V
Load Regulation
Ripple Rejection
Average Temperature
Coefficient
of Output Voltage
Short Circuit Current Limit
Reference Voltage
Reference Voltage
Change With Load
Output Noise Voltage
0.03
IL = 1 mA to IL = 50 mA
-55°C::5 TA::5 + 125°C, IL = 1 mA to IL = 50 mA
0.15
%VO
0.6
%VO
f = 50 Hz to 10kHz
74
dB
f = 50 Hz to 10 kHz, CREF = 5/lF
86
dB
-55°C::5 TA::5 +125°C
0.002
= 10 fl, Vo = 0
IREF = 0.1 mA
IREF = 0.1 mA to 5 mA
BW = 100 Hz to 10 kHz, CREF = 0
65
RSC
6.95
BW = 100 Hz to 10 kHz, CREF = 5/lF
7.15
0.015
7.35
V
20
mV
20
/lVrms
2.5
/lVrms
2.3
IL = 0, VIN = 30 V
%/oC
mA
%/1000 hrs
0.1
Long Term Stability
Standby Current Drain
Unit
3.5
mA
Input Voltage Range
9.5
40
V
Output Voltage Range
2.0
37
V
Input / Output Voltage
Differential
3.0
38
V
2·96
J.LA723
J.LA723C
Electrical Characteristic
Characteristic
TA = 25°C, VIN = V+ = Vc = 12 V, V- = 0, Your = 5 V, IL = 1 rnA, Rsc = 0,
Cl
100 pF, CREF
0, unless otherwise specified. Divider impedance as seen by
error amplifier :::5 10 kfl connected as shown in Figure 1. Line and load regulation
specifications are given for the condition of constant chip temperature. Temperature
drifts must be taken into account separately for high dissipation conditions.
=
=
Typ
Max
Unit
= 12 V to VIN = 15 V
VIN = 12 V to VIN = 40 V
O°C:::5 TA:::5 70°C, VIN = 12 V to VIN = 15 V
IL = 1 rnA to IL = 50 rnA
O°C :::5 TA:::5 70°C, IL = 1 rnA to IL = 50 rnA
f = 50 Hz to 10kHz
f = 50 Hz to 10 kHz, CREF = 5 J.LF
0.01
0.1
%Vo
0.1
0.5
%Vo
0.3
%Vo
0.2
%VO
0.6
%VO
O°C :::5 TA :::5 70°C
0.003
Min
Condition
VIN
Line Regulation
Load Regulation
Ripple Rejection
Average Temperature
Coefficient
of Output Voltage
Short Circuit Current Limit
Reference Voltage
Reference Voltage
Change With Load
Output Noise Voltage
= 10 fl, Vo = 0
= 0.1 rnA
IREF = 0.1 rnA to 5 rnA
BW = 100 Hz to 10 kHz, CREF = 0
BW = 100 Hz to 10 kHz, CREF = 5 J.LF
0.03
6.80
86
dB
0.015
7.15
IL
= 0, VIN = 30 V
%/oC
rnA
7.50
V
20
mV
20
J.LVrms
2.5
J.LVrms
0.1
Long Term Stability
Standby Current Drain
dB
65
RSC
IREF
74
2.3
%/1000 hrs
4.0
rnA
Input Voltage Range
9.5
40
V
Output Voltage Range
2.0
37
V
Inpull Output Voltage
Differential
3.0
38
V
2·97
•
p,A723
Typical Performance Curves for J.lA723 and J.lA723C
Line Regulation as a
Function of
Input/Output
Voltage Differential
Current Limiting
Characteristics as a
Function of
Junction Temperature
1-+-+--+---1I-+-+-Y~UO
l +5 y
Asc '" 0
1
+O.21-+-+-I-+-+-!_TA
.'lV
5
+25°C
"
~
~
~
~
-0.11-+-+-/-+-+--1-+-+-+-1
0
-
ffi
~
120
i"""; ~
W
"!:;<
I::I
-40
(YIN -
YOUT) -
+20
·20
v
+60
+100
+140
I
Z
o
~
~
2o I
z
o
11
2.0
0
o
w
~~U~OLTAGE
/
~
l - I-
~
".0
5
-40~
15
v
~
g
I-T r I
·5
YOUT) -
w
"
1- ',
o
1j
-20~
= +12 V
!-VIN
YOUT '" +5 V
'" 1 mA
-20
::I
T,
'" 25·C
(YIN -
15
25
35
45
.se
00
T,
= +25°C
= 50 rnA
I,
~
~
o
v
g
25°C
25
·30
I
0
35
45
Your = +5 V
= +12 Y
y,"
>
I
I
40
=
10
4
INPUT VOLTAGE
+011-+-+--+-t-+--+-!-+-+--+
go
== +12 V
YOUT = +S V
= 40 rnA
I,
y"
Output Impedance as a
Function of Frequency
6D
>
E
-20
I
z
TIME-,..s
Line Transient Response
+0.2 r-T".---,-r-T"--r-y-,-.---,
o
~
~
Q
.'( 1
JUNCTION TEMPERATURE _ °C
Load Regulation as a
Function of
Input/Output
Voltage Differential
-10
T,
\
-8.0
·5
o
1('\
\
()
O. 3
·60
o
E
o<~
I
~
1-+-+-I-+-+--1-IL
~
200
%
~f'
>
==
'" +3 V
=
Load Transient Response
O. 8
+0.3,.,-,-r-T"-r-Y-,-.,-,-,
'~
"
10
Z
C,
<
'"F
0
!
...::I
~
V
D1
::I
0
."
0.01
1DO
1k
10k
1M
100 k
FREQUENCY - Hz
TIME-J.ls
Typical Performance Curves for J.lA723
Maximum Load Current as a
Function of
Input-Output Voltage Differential
2DO
I
ToL, l,.l.
RTH ""
-
160
~
I
I-
~
'"()
::I
120
r~~A~:~T=S~~K~w
-
~
4D
o
=
l"-. .......
+125°C
"4..
o
-0.05
r---.: .......
t'-...
Z
5
10
-0.1
-0 2
20
~ r-....
·c r- ~
,.
30
40
50
INPUT·OUTPUT VOLTAGE DIFFERENTIAL - V
'SSoC
i"--
_Rr r I
20
40
so
OUTPUT CURRENT - mA
2·98
so
-005
r;;;:: ::--
~
......
~
I
~
f--
~S'C
t<~~
"i-l~$·C ~::::.
-01
r---
5
::I
~ -015
r--...
5 V
-0.1 51-your'"
VIN
'" +12 V
'-....
~
-......:. ~1<).
::I
~
It!::::::-
1
~C
~'-
o
,TA"'" +25°C
I
I
5
so
TA
+0.05
~
~
~
Load Regulation Characteristics
With Current Limiting
+005
1_
150°C/W
\
\
Load Regulation Characteristics
Without Current Limiting
100
·02 I-~our "" 5 V
VIN
'" +12 V
-025
l-i
o
sC
1
1'I
0
0
10
15
20
OUTPUT CURRENT - mA
25
30
f.LA723
Typical Performance Curves (Cont.)
Load Regulation Characteristics
With Current Limiting
,
vL, 1. vi
"""II~
~
V'N
'" +12 V
Ase
= 10 U
I -01
.
5 ••
, ,
w
JOUT I" V;EF
1 ,,".
••
"~ ••
0
>
Z
5~
!il
,.
,.
>
1
~~
"
Current LImiting Characteristics
Standby Current Drain as a
Function of
Input Voltage
.....-
I-
1\ '\
\ ~\
-02
-.
~ -~\
-<14
n
•
••
n
"
••
••
OUTPUT CURRENT - rnA
" f- -
:!;
f-
:.
r-
..
•• ,
=:
~r- -
+12 V
..
••
OUTPUT CURRENT -rnA
,.
TA
=:
+25°C
~c
.....-"'"
.. ,..
50
TA = -S5°e
~
/
n
f-~OUT '" +5 V
VIN
/
;or- -
0
~~n~\f ~-"0 --
3
••
;t t--;t
"!:!
••
" f-"
f-~
~. ••
r~ n
1
r"Jc I'· il
1
••
••
"~
2.
.
30
INPUT VOLTAGE - V
5.
Typical Performance Curves for ",A723C
Maximum Load Current as a
Function of
Input/Output Voltage Differential
2.•
..
LML "1'50Je
,
1
1
I-
\
120
ill
il!
=:
150°C/W
=:
80 mW
~
z
o
TA = 70°C
~
~
,.
••
".!il
2.
1
....
....,
.
3.
200
1T"~'" I"
.. II
,
.ill
••
=:
111°CIW
=
80 mW
•
\
r- -
••
l
r
••
1
-.
OUTPUT CURRENT - rnA
+. ,
~
.... ~
o
r--.
5
~
3.
5.
INPUT-OUTPUT VOL TAGE DIFFERENTIAL - V
~
02 - :~UT : :!2vV
-<12
r-
~~
-:toe ~
OUTPUT CURRENT - mAo
2-99
.
.""
'00
mA
0."-
'i
••
w 30
.0
Q
Z
t;
3•
TA == +25°C
~~
0
<
1
•0
.
•0
1
, ">OYf'"
,.
'0
IZ
>
•
•-"I" 7'0 i"
• .0
Standby Current Drain as a
Function of
Input Voltage
5.
V~UT ~ V'~,
E
1
••
I
f-+--+-+--f-~ ~
OUTPUT CURRENT -
I
I"'-'
~
o. f-+--+-+-f-II
o.
'" +12 V
=10U"-
t, "O°c l
1'..q ""2$0
2.
~
'00
1 1
1 1
"~ -01
I>
.~
t, i >.oC 1
,.
...
f-+-+--+-+-~:
>
"e:
"0w
<
5
-
••
JouTI" 15 vi _
YIN
Rse
'"1
z
'\
.
••
-
\
o ••
~
ATH
PSTANDBY
\
§
-...~:-;;:~
Load Regulation Characteristics
With Current Limiting
12~Oe 1 _
DIP PACKAGE
(NO HEAT SINK)
I
120
r-!' ""oC r--
Your = +5 V
V'N = +12 V
-<12
50
Maximum Load Current as a
Function of
Input/Output Voltage Differential
~
-
'0
"<~ ••
0
>
INPUT-OUTPUT VOLTAGE DIFFERENTIAL - V
~
>
1
~ -01
25°C
Current LImiting Characteristics
w
TA - DoC
;::
\1\.
••
-"'r--:
'"1
\
\
B 80
~
1
ATH
PSTANDBV
METAL CAN PACKAGE
(NO HEAT SINK)
I
Load Regulation Characteristics
Without Current LImiting
,.
•o
0
10
.0
TA
~
TA == +7QOC
3.
INPUT VOLTAGE - V
- f-
40
5•
p,A723
Typical Applications
Fig. 1
Fig. 2
Basic Low Voltage Regulator
(VOUT= 2 to 7 V)
Basic High Voltage Regulator
(VOUT = 7 to 37 V)
V,N
v+
v+
Vc
Vc
VREF
YOUT
VOUT
YREF
~A723
Rl
Rsc
R3
REGULATED
OUTPUT
CL
~A723
Rsc
CL J---4--'V'____........
csJ----i
CS
Rl
R3
Cl
100 pF
R2
CRE'I
-=
~~~~~TED
R2
-=
Typical Performance
Regulated Output Voltage
Line Regulation (~VIN = 3 V)
Load Regulation (~IL = 50 rnA)
Typical Performance
Regulated Output Voltage
Line Regulation (~VIN = 3 V)
Load Regulation (~IL = 50 rnA)
5V
0.5mV
1.5 mV
Note
15 V
1.5 mV
4.5mV
Note
Rl R2
R3 = R 1 + R2 for minimum temperature drift.
Rl R2
R3 = Rl + R2 for minimum temperature drift.
R3 may be eliminated for minimum component count.
Fig. 3
Fig. 4
Negative Voltage Regulator
V,N
Positive Voltage Regulator (External npn
Pass Transistor)
V,N
RS
2 kn
YREF
Vz
~A723
R4
3 kH
t - -.......-i:. ~~4898
CL
Rsc
REGULATED
OUTPUT
CS
N.!.
R3
3 kn
Rl
V-
Rl
Cl
100 pF
R2
'-----4---4-------1--<........ ~~~~~~TED
Typical Performance
Regulated Output Voltage
Line Regulation (~VIN = 3 V)
Load Regulation (~IL = 100 rnA)
Typical Performance
Regulated Output Voltage
Line Regulation (~VIN = 3 V)
Load Regulation (~IL = 1 A)
-15 V
1 mV
2 mV
+15 V
1.5 mV
15 mV
Note 4
Notes
1. Figures in parentheses may be used if R 1 I R2 divider IS placed
on opposite side of error amp.
2. Replace Rl IR2 in figures with divider shown in Figure 8.
3. V+ must be connected to a +3 V or greater supply.
4. For metal can applications where Vz is required, an external
6.2 V zener diode should be connected in series with VOUT
2-100
ILA723
Typical Applications (Cont.)
Fig. 5
Positive Voltage Regulator (External pnp
Pass Transistor)
Fig.6
Foldback Current Limiting
Y,N
V+
Vc
VAEF
Rsc
30 n
VOUT
Vc
V+
REGULATED
OUTPUT
R3
2.7 kn
VOUT
VREF
R1
pA723
CL
cs
R1
"A723
56 kn
NI
INV
Rsc
cs
R2
REGULATED
OUTPUT
INV
N.I.
R'
CL
'::'
R2
Typical Performance
Regulated Output Voltage
Line Regulation (~VIN
3 V)
Load Regulation (~IL = 1 A)
+5V
=
Fig. 7
Typical Performance
Regulated Output Voltage
Line Regulation (~VIN = 3 V)
Load Regulation (~IL = 10 mAl
Short-Circuit Current
0.5 mV
5 mV
Fig. 8
Remote Shutdown Regulator with
Current Limiting
Output Voltage Adjust
Y,N
R1
V+
Vc
Rsc
VRH
REGULATED
OUTPUT
VOUT
P1
4 - - - NON-INVERTING
INPUT
NOTE 2
R1
>L A723
CL
R2
cs
NI
R2
INV
t:=-4~~i'1':'-'"'WIr-CCSL
R' LOGIC
2 kfl
INPUT
Notes
Current limit transistor may be used for shutdown If current
limiting IS not required. Add if VOUT > 10 V
Typical Performance
Regulated Output Voltage
Line Regulation (~VIN
3 V)
Load Regulation (~IL = 50 mAl
=
+5 V
0.5 mV
1.5 mV
2·101
+5 V
0.5 mV
1 mV
20 mA
•
JLA 105 • JLA305
JLA305A • JLA376
Voltage Regulators
FAIRCHILD
A Schlumberger Company
Linear Products
Connection Diagram
a-Pin 'Metal Package
Description
The 10S/30S/30SA/376 are Monolithic Positive
Voltage Regulators constructed using the Fairchild
Planar epitaxial process. Applications for these
devices include both linear and switching regulator
circuits with output voltages greater than 4.S V. These
devices will not oscillate when confronted with varying
resistive and reactive loads and will start reliably
regardless of the load within the ratings of the circuit.
They also feature fast response to both load and line
transients. Used independently, the 10S/30S will
supply 12 mA, the 30SA, 4S mA and 376, 2S mAo The
10S is specified for the military temperature range
(-SSOC to +12S0C) and the 30S/376/30SA are
specified for O°C to +70°C operation. The
10S/30S/30SA are in an a-pin TO-S package and the
376 is available in the space and cost saving DIP.
REG
OUT
BOOSTER
6
FEEDBACK
COMMON
(Top View)
Order Information
Type
Package
p,A10S
Metal
p,A30S
Metal
p,A30SA
Metal
• LOW STANDBY CURRENT DRAIN
• ADJUSTABLE OUTPUT VOLTAGE FROM
4.S TO 40 V
• HIGH OUTPUT CURRENTS EXCEEDING 10 A
WITH EXTERNAL COMPONENTS
• LOAD REGULATION BETTER THAN 0.1%, FULL
LOAD WITH CURRENT LIMITING
• DC LINE REGULATION GUARANTEED
ATO.03%/V
• RIPPLE REJECTION OF 0.01%/V
Absolute Maximum Ratings
Input Voltage
p,A10S,p,A30SA
p,A30S,p,A376
Input 1Output Voltage
Differential
Internal Power Dissipation
(Note 1)
p,A 10S, p,A30S,
p,A30SA,p,A376
Operating Temperature Range
Military (p,A 10S)
Commercial (p,A30S,
p,A30SA, p,A376)
Storage Temperature Range
Metal
DIP
Pin Temperature
Metal soldering (60 s)
DIP Soldering (1-0 s)
2
OUT
Code
SW
SW
SW
Part No.
p,A10SHM
p,A30SHC
p,A30SAHC
Connection Diagram
a-Pin DIP
CURRENT LIMIT
REG OUT
COMP
BOOSTER OUT
so V
UNREGIN
FEEDBACK
COMMON
REF BYPASS
(TOp View)
40 V
Order Information
Type
Package
p,A376
Molded DIP
40V
SOOmW
4S0mW
-6S0C to +1S0°C
-SsoC to +12SoC
Notes
L Rating applies to ambient temperatures up to lO·C. Above
70·C ambient derate linearly at 6.25 mW /·C for the metal can
and 5.6 mW /·C for the mini Dip.
2-102
Code
9T
Part No.
p,A376TC
Equivalent Circuit
. . . - - - - - - - - - - - - -......- - - - - - - - - - . . - - - - - -......-=-3 UNREGULATED INPUT
r-~~----~--~
BOOSTER OUTPUT
'--'WI..-_'W..-+---'-' CURRENT LIMIT
~------8::'REGULATED OUTPUT
, ' - _ - - - -_ _- - - - - ' - 7 COMPENSATION
SHUTDOWN
R3
6.8k
6 FEEDBACK
:l-_-I_____-+_......__.::.
' - - - - - t - - - - t - - - - - _ > - - - - - - " - 5 REFERENCE BYPASS
'--_~>---......--------_~---------_~---------~4 COMMON
Pin Connections Shown are for Metal Package
p.A105
Electrical Characteristics
TA = 25°C unless otherwise specified (Note 2)
Characteristic
Condition
Max
Unit
8.5
50
V
Output Voltage Range
4.5
40
V
Output/Input Voltage
Differential
3.0
30
V
Load Regulation (Note 3)
Line Regulation
o !5 IL !5
Min
Typ
Input Voltage Range
12 mA
RSC = 100, TA = 25°C
0.02
0.05
%
RSC = 100, TA = 125°C
0.03
0.1
%
RSC = 100, TA = -55°C
0.03
0.1
%
0.025
0.06
%IV
0.015
0.03
%IV
VIN - VO!5 5 V
VIN - Vo
>
5V
Ripple Rejection
CREF = 10 p.F, f = 120 Hz
0.003
0.01
%/V
Temperature Stability
(Note 5)
-55°C !5 TA !5 125°C
0.3
1.0
%
1.7
1.81
Feedback Sense Voltage
Output Noise Voltage
1.63
10 Hz !5 f !5 10 kHz
CREF = 0
CREF
Current Limit Sense
Voltage (Note 4)
RSC = 100, TA = 25°C,
Vo=OV
Standby Current Drain
VIN = 50 V
>
O. 1 p.F
225
Long Term Stability
Notes
2. These specificaltons apply for input and output voltages within
the ranges given, and for a divider Impedance seen by the
feedback terminal of 2 k!l, unless otherwise specified. The
load and Ime regulation specifIcatIons are for constant junction
temperature. Temperature drift effects must be taken into
account separately when the unit IS operating under condItions
of high dissipation.
3. The output currents given. as well as the load regulatIon. can
be increased by the addition of external transistors. The
V
0.005
%
0.002
%
300
375
mV
0.8
2.0
mA
0.1
1.0
%
Improvement factor will be roughly equal to the composite
current gam of the added transIstors.
4. With no external pass transIstor.
5. Temperature Stability IS defined as the percentage change in
output voltage for a thermal variation from room temperature to
either temperature extreme.
2·103
•
~A105 • ~A305 • ~A305A • ~A376
",,305
Electrical Characteristics
TA = 25°C unless otherwise specified (Note 2)
Characteristic
Condition
Min
Typ
Max
Unit
Input Voltage Range
8.5
40
V
Output Voltage Range
4.5
30
V
Outputllnput Voltage
Differential
3.0
30
V
Rsc
Load Regulation (Note 3)
o ~ IL ~
12 mA
Rsc
= 100, TA = 25°C
= 150, TA = 70°C
0.02
(}'05
%
0.03
0.1
%
%
0.03
0.1
VIN- Vo~ 5V
0.025
0.06
%IV
VIN -Vo> 5V
0.015
0.03
%IV
Ripple Rejection
CREF = 10 /IoF, f = 120 Hz
0.003
0.01
%/V
Temperature Stability
(Note 5)
O°C ~ TA ~ 70°C
0.3
1.0
%
1.7
1.81
Rsc = 100, TA = O°C
Line Regulation
'.
1.63
Feedback Sense Voltage
~
f
~
10 kHz
V
CREF = 0
0.005
%
CREF > 0.1 /IoF
0.002
%
Output Noise Voltage
10 Hz
Current Limit Sense
Voltage (Note 4)
RSC = 100, TA = 25°C
Vo= OV
Standby Current Drain
VIN = 40 V
225
Long Term Stability
300
375
mV
0.8
2.0
mA
0.1
1.0
%
Typ
Max
Unit
",,305A
Electrical Characteristics
TA = 25°C unless otherwise specified (Note 2)
Characteristic
Condition
Min
Input Voltage Range
8.5
50
V
Output Voltage Range
4.5
40
V
Output/Input Voltage
Differential
3.0
30
V
= 0 0, TA =
= 00, TA =
25°C
0.02
0.2
%
70°C
0.03
0.4
%
0.03
0.4
%
VIN - Vo ~ 5V
0.025
0.06
%/V
VIN - Vo > 5V
Q.015
0.03
%IV
Rsc
Load Regulation
o ~ IL ~ 45 mA
Rsc
Rsc = 00, TA "i' O°C
Line Regulation
= 10 /IoF, f =
Ripple Rejection
CREF
Temperature Stability
(Note 5)
O°C ~ TA ~ 70°C
0.003
120 Hz
Feedback Sense Voltage
Output Noise Voltage
1.55
10 Hz
~
f
~
10 kHz
%/V
0.3
1.0
1.7
1.85
%
V
=0
0.005
%
CREF > 0.1 /IoF
0.002
%
CREF
Current Limit Sense
Voltage (Note 4)
RSC = 100, TA = 25°C,
Vo= OV
Standby Current Drain
VIN
225
= 50 V
Long Term Stability
Notes on following page.
2-104
300
375
mV
p.8
2.0
mA
0.1
1.0
%
~A105 • ~A305 • ~A305A • ~A376
~A376
Electrical Characteristics
O°C:$ TA :$70°C
Characteristic
Condition
Typ
Min
Max
Unit
Input Voltage Range
9.0
40
V
Output Voltage Range
5.0
37
V
Output/Input Voltage
Differential
3.0
30
V
= 00. TA = 25°C
RSC = 0 O. TA = 70°C
0.2
%
0.5
%
Rsc = 00. TA = O°C
0.5
%
TA = 25°C
0.03
%IV
O°C :$ TA :$ 70°C
RSC
o :$ IL :$ 25 mA
Load Regulation
Line Regulation
0.1
%IV
Ripple Rejection
f
= 120 Hz. TA = 25°C
0.1
%IV
Standby Current Drain
VIN = 30 V. TA =25°C
2.5
mA
1.80
V
Reference Voltage
1.60
1.72
Current Limit Sense
Voltage
360
•
mV
Note.
2. These specifications apply for input and output voltages within
the ranges given, and for a divider impedance seen by the
feedback terminal of 2 kll, unless otherwise specified. The
load and line regulation specifications are for constant junction
temperature. Temperature drift effects must be taken into
account separately when the unit is operating under conditions
of high diSSipation.
3. The output currents given, as well as the load regulation, can
be increased by the addition of external transistors. The
improvement factor will be roughly equal to the composite
current gain of the added transistors.
4 With no external pass transistor.
5 Temperature Stability IS defmed as the percentage change in
output voltage for a thermal variation from room temperature to
either temperature extreme.
Typical Performance Curves for
~105/~305/~A305A
Current Limiting
Characteristics
Load Regulation
f
~.~~.. ...... TA=1!rC
; -D.Ol
........ -~ ....................
!
~1--r~-.'.-.,~~1-~~
....
~ -D.02~+-+-t-+-+'''::''''+-I--i
T.:-..·C ••••••••
~
I
..•....
Short Circuit Current as a
Function of Temperatur~
I
Ii D.·f-+--~H~
U
~C=~H
I-f-+-+++---+--+-+-+-+-I
!:
~
1--t---il:;11
o!~:o!
~;-~!-~
r- lit-I-II
--
o! f-- o!t-f--
-003~+-+-t-+-+-+-+---l
_....
f-- ".c:O-+-+-+-+--+--I
o
I 1
5
10
15
, LOAD CURRENT-mA
ao
1
1
.........
>
f- "'c=lO II+-i+++-+-t-t---l
O~O~~lO~~ao~~ao~~~~~~..·
OUTPUT CURRENT-mA
2·105
10
-
11-......
........ ~=151l
r--. .....
-l r--
",c:i"
r--....
"
t- f:::- ........
1
75
50
2S
0
25
50
75
TEMPEAATURE_oC
100
125 150
p,A 105 • p,A305 • p,A305A • p,A376
Performance Curves for
p.A 10S/p.A30S/p.A30SA (Cont.)
Current Limiting Characteristics
Current Limit Sense Voltage as a
Function of Temperature
.s
..
.:•••:••.••~
\. ...
I
~ -.oo
...
~ ...
Ii
~
~
!
0
\
.......
I'-..
.. ...
!iIU
•
.. .. ..
10
••
7S 50
25
i
.... ~
50
75
75
50
25
,
....
25
50
75
100
.-,
125
TEMPERATURE_OC
Regulator Dropout Voltage
r-
-
~
TEMPERATURE_oC
t'ri I
10
TA = -55 0
1.1
I. ,.
...
8
..
..
./
3.
U
~-r
TA=125"C
.........................
•• !:1O--''--:
..:--.L--:..!:-..J......--!:
..:--.L-~..
INPUTVOLTAGE-Y
Transient Response
.. r--,--r-~--~-,---,
1-----1--+--1--+ RseLoH-
4.
I ...
e ......................
···········~A~ ...~~C~~+--1
! . . ~:~:::: ......
45
~
,--±-.-:..!;-":\..,..-,766--:...!:--:!'..
Standby Current Drain as
Function of
Input Voltage
,
CREF"'O
Minimum Output Voltage as a
Function of Temperature
>
I
"_'=76~_..::--_:
..
..
10
OUTPUT VOLTAGE-V
INPUT-OUTPUT VOLTAGE DIFFERENTIAL-V
'3 r--,-.....,.-,--.,....--,.-,--.--,
~V 1---t-+--+---1f--+-VJ.,,.
Asc=1GU'
IL""5rnA····· ......
..........
'lOy
1 1
./
0
100 1as 110
YOUT
_~REF"'10~f
s.
... •
~
TA 25°C
V
7.
IS
,
.... ~
I
0
"'
.......
Supply Voltage Rejection as a
Function of
Input/Output Voltage Differential
YO~Y=4!V-
>
I'-..
TEMPERATURE_oC
Minimum Input Voltage as a
Function of Temperature
••
-........
a
LOAD CURRENT-rnA
~~
.......
~
-0,08
-.,
........
••
I:
!;
I!:::>
.... 1'-..
IU
ill
~ -
R1 '" 1.11 VOUT , _
\
D-5
~
....
IA1/•• ~I"1I 1-
'.0
IU
' \ ••••• TA- -SS"C
-
3•
.J:SSJA-
>
I
I
Optimum Divider
Resistance Values
./
V
V
/
/
I -..
~
76 ... m
TEMPEAATURE-o C
2-106
I
I--~~-+--r-+--~---1
I
~.
.. ..
VOUT~lOV
r=-~L~. +--t---t--t-1-j
~~ ... ..:::= ~L ~"F ---f---+ IFL=20mA
Asc ~10 II
o
•
.lYIN=5Y
LINE
IU
.. I---'"
76 .. ..
>
I
INL=1.0mA
LOAD
~.........
~\:.......~~.~:.j.1Dv..
I
-... ~.--~--1D~--~-=..~_~I~..
TIME-Io!s
~A105 • ~A305 • ~A305A • ~A376
Typical Performance Curves for 1tA376
Current Limiting Characteristics
Load Regulation
"I
iii
Ii
iiig
~
g
I
I I
I I
.z
1
..
•
3D
.....
i'" ......
-
0.300
!.~
~
iii
"'
,.....
8
i! ••
..
70
~ "'I---F'''''"-;-'~-'::::+-r--.-+-+-t----'H
........
of ::::: .•....
-d i-tr"'f·:;,···
..k..
1O
""-ITYSj
:"I··•....::-1
•• - H
..... .
•
•
•7 11
i
i
I
2.
•
-C,=.
•
...... C. = ... >
..
,..
INL=10mA_
1,OUT =lOY ..... .
nME-~.
2.2f-
•
•
2.
Supply Voltages Rejection as a
Function of
Input/Output Voltage Differential
R2=.!.l!!.!!l
Vo-1.72
VOUT=t72X(~+1)
• \
2.
.......
·~4.~~
...-...~.·~L~~~~~
\
z.3
,,41-+-+--+--+--+-+-+-I--...,H
•• "
IF~C==20mA-
1 I 1 1 1 1
1 \
25
-+--+--1--1
R1=111YOVT(tcU)
Z•
" • L....-!:--'-...L.:..:-1-....J...-50
±-..L...-=70:---'L......J
AMBIENT TEMPERATURE_oC
400
>Y'N=5V
YOUT f'DY
-4DD!:-.--'--1D=----JL---:!:
..,---....J...-~..
70
Optimum Divider Resistance
120I-+-+--+,<\-+--+-+-+-I-H
"8
i
50
2.
-
~
;t
~
......
.sc; •• " +-+--t--t
AMBIENT TEMPERATURE-DC
z.
g "8
i "7
gIY
,,/
~
AMBIENT TEMPERATURE_oC
Regulator Dropout Voltage
-
L .. _
i •
g •
5
50
3DU.
I\.
LINE
I
•
25
101121125
Transient Response
•
7
YOUT=5V
VOJT = sly -
3
7
....
..... 1-"
INPUT VOLTAGE-V
2
I
........
035D
'50
3D
Minimum Input Voltage as a
Function of Temperature
>
1-1-'"
...1 /
.. ..
.1
10
-~
j.... - I -
1/
OUTPUT CURRENT-mA
lol5m~0400
g
i
~-r
~ ....
"'" L
.... ..... .;:;~~.;t~.:
• ..oI!!!! ... ............1 1
I I
>
i:::;
VOUT=t)V
~ "'"
i
~~
Current Limit Sense Voltage as a
Function of Temperature
I
1
'.10
'.70
•..
10
~
i
TA-ODe
LOAD CURRENT-mA
~
...1
l ...
f-I
T.="·C- r.
T.=7O"C-
.....r.J........
=
....
....
~C!101!-
.'I--t-H-+-+-+-H-I.lSI1••.1-
...
Standby Current Drain as a
Function of
Input Voltage TA 25°C
-~
..... I--t-t-r:.....'"Iood:-+++++-i
"t
10
11
20
25
OUTPUTVOLTAGE-Y
2·107
--..
•.OIDI-I-I-t-t-HHI--HI--H
.... f..,
3D
•
10
15
25
INPUT·OUTPUTYOLTAGE DIFfeRENTIAL
3D
•
p,A 105 • p,A305 • p,A305A • p,A376
Typical Appllcatlon8
Ba8ic P081tlve Regulator With Current Limiting
Rsc
r--"N"--'-:'=~~---1r-VOUT
R1
V'N.......:=~~.:.:....:":O
R2
CREF
VOUT"" 1.72 Rl
+ R2
R2
V
ISC "" VSENSE rnA
Rse
2-108
JLA 117 • JLA217 • JLA317
FAIRCHILD
3-Terminal Positive
Adjustable Regulators
A Schlumberger Company
Linear Products
Connection Diagram
To-3 Package
Description
The /LA 117 is a 3-Terminal Adjustable Positive Voltage
Regulator capable of supplying in excess of 1.5 A over
an output voltage range of 1.2 V to 37 V. This voltage
regulator is exceptionally easy to use and requires
only two external resistors to set the output voltage.
Further, it employs internal current-limiting, thermalshutdown and safe-area compensation, making it
essentially blow-out proof.
OUTPUT 3
The /LA 117 series serves a wide variety of
applications including local, on-card regulation. This
device also makes an especially simple adjustable
switching regulator, and a programmable output
regulator; or by connecting a fixed resistor between
the adjustment and output, the /LA 117 series can be
used as a precision current regulator.
(TOp View)
Order Information
Type
Package
/LA317
Metal
/LA 117
Metal
• OUTPUT CURRENT IN EXCESS OF 1_5 A IN To-3
AND TO-220 PACKAGES
• OUTPUT ADJUSTABLE BETWEEN
1_2 V AND 37 V
• INTERNAL THERMAL-OVERLOAD PROTECTION
• INTERNAL SHORT-CIRCUIT CURRENT-LIMITING
CONSTANT TEMPERATURE
• OUTPUT TRANSISTOR SAFE-AREA
COMPENSATION
• FLOATING OPERATION FOR HIGH-VOLTAGE
APPLICATIONS
• STANDARD 3-PIN TRANSISTOR PACKAGES
• AVAILABLE IN MILITARY TEMPERATURE RANGE
Absolute Maximum Ratings
Input-Output Voltage Differential
Power Dissipation
Operating Junction Temperature
Military (/LA 117)
Automotive (jLA217)
Commercial (/LA317C)
Storage Temperature
TO-3 Steel
TO-220
Pin Temperature
TO-3 Package
(Soldering, 60 s Time Limit)
TO-220 Package
(Soldering, 10 s Time Limit)
Code
HJ
HJ
Part No_
/LA317KC
/LA 117KM
Connection Diagram
TO-220 Package
(Top View)
Order Information
Type
Package
/LA317
Molded Power Pack
/LA217
Molded Power Pack
40 Vdc
Internally Limited
-55°C to +150°C
-40°C to +125°C
O°C to +125°C
-65°C to +150°C
-55°C to +150°C
2·109
---~~--~~~
•
Code
GH
GH
Part No_
/LA317UC
/LA217UV
JLA 117 • JLA217 • JLA317
Schematic Diagram
~
310
v
v
""~
"
v
'"'
~
125 k
135
124 k
>-4:::~f-r:~;:1--
>-
-....
r
3Dpi'
36.
5"
110
67"
(F
......
'----
.......
"'"
......
24 "
'2 ~6.3V
100
~
~56"
~'20
230
J31D
30 pF
(
12~
V,N
3
170
160
V
~I-
63V
~~
~
510
13.
200
6.8 k
-r
63!
"- ~
105
126 k
51.
4
>-01
VOU
ADJUST
2·110
~A 117
Electrical Characteristics
• ~A217 • ~A317
VI - Vo = 5 V; 10 = 0.5 A for K and U Packages
TJ = Operating Temperature (see Note 1); IMax and PMax per Note 2;
unless otherwise specified.
/LA117 1217
Min Typ
Max Unit
0.01
0.02
0.01
0.04 %/V
0.02
0.05
0.02
0.07 %/V
5
15
5
25
5 V
0.1
0.3
0.1
0.5
%VO
VO:::::; 5 V
20
50
20
70
mV
~
0.3
1
0.3
1.5
%VO
50
100
50
100 /LA
0.2
5
0.2
5
Condition
Line Regulation
Reg Line (Note 3, 7)
TA = 25°C, 3 V:::::; VI - VO:::::; 40 V
3 V :::::; VI - Vo :::::; 40 V
Regulation
Reg Load Load
(Note 3)
VO:::::; 5 V
TA = 25°C,
10 mA :::::; 10 :::::; IMax
Vo
10 mA :::::; 10 :::::; IMax
/LA317
Max Min Typ
Symbol Characteristic
Vo
~
5V
IAdi
Adjustment Pin Current
~IAdi
Adjustment Pin Current
Change
2.5 V :::::; VI - Vo :::::; 40 V
10 mA :::::; IL :::::; IMax, PO:::::; PMax
VRef
Reference Voltage
(Note 4)
3 V :::::; VI - Vo :::::; 40 V
10 mA :::::; 10 :::::; IMax, Po :::::; PMax
TS
Temperature Stability
IL(Min)
Minimum Load Current
to Maintain Regulation
IMax
Maximum Output
Current
1.20 1.25
1.30 1.20 1.25
0.7
3.5
VI - Vo = 40 V
VI - Vo :::::; 15 V, Po :::::; PMax
K and U Packages
1.5
VI - Vo = 40 V, Po :::::; PMax,
TA = 25°C K and U Packages
0.25 0.4
2.2
1.5
TA = 25°C, 10 Hz:::::; f:::::; 10 kHz
RR
Ripple Rejection
(Note 5)
Vo = 10 V,
f = 120 Hz
S
Long-Term Stability,
TJ = Thigh
(Note 6)
TA = 25°C for
Endpoint Measurements
0.3
1
ROJC
Thermal Resistance
Junction to Case
K Package (TO-3)
2.3
3
Without CAdi
U Package (TO-220)
10
mA
2.2
A
RMS Noise, % of Vo
= 10/LF
%VO
0.15 0.4
N
CAdi
3.5
/LA
1.30 V
0.7
5
mV
66
0.003
0.003
65
65
80
66
%VO
dB
80
0.3
1
2.3
3
%1.0 k
Hrs
°C/W
5
Notes
4 Selected devices with tightened tolerance reference
voltage available.
5 CAdI' when used, IS connected between the adjustment
pin and ground.
6 Since Long-Term Stability cannot be measured on each deVice
before shipment, this specification is an engineering estimate
of average stability from lot to lot.
7. lOUT; 0.5 A for VI - Vo .oS 25 V and IMax for VI - Vo ~ 25 V.
1 ,.,A 117 Operating Junction Temperature Range;
-55'C to +150'C
,.,A217 Operating Junction Temperature Range;
-25'C to +120'C
2. IMax ; 1 5 A for K (TO-3) and U (TO-220) Packages
PMax ; 20 W for K (TO-3) and U (TO-220) Packages
3. Load and line regulation are specified at constant Junction
temperature Changes in Vo due to heating effects must be
taken Into account separately. Pulse testing with low duty
cycle is used.
2-111
•
~A 117· ~A217· ~A317
Typical Performance Curves
Load Regulation
0.'
..
Adjustment Pin Current
Current Limit
70
4
VI = 15 V
Yo = 10 Y
'1,65
2
w
ILL oslA
I
= 1:&'A- l- t-
Il
~ -0.2
-""
..........
~
~ -0.4
1'-...
5
S
-0.•
,
c
/ TJ ::: 25"C
~ f\.
a:
""
.-
2
I
. -D.'
~
-1.0
-75
-so
o
-25
0
25
50
75 100 125 150
~
"'
J
~
20
10
T J. JUNCTION TEMPERATURE _ °C
~
TJ::: -S5°e
1/'"~
TI160'r
~
If-
.§
o
Ii'l
3
~
a:
i
" ""
j
..
./
V
I-
-
V
45
II
40
35
_75
40
30
•
~
,
-
60
-so
-21
0
25
50
75 100 125 150
TJ' JUNCTION TEMPERATURE _·C
VI - Yo. INPUT/OUTPUT
VOLTAGE DIFFERENTIAL - Vdc
Dropout Voltage
Minimum Operating Current
Temperature Stability
5.0
1.260
3.0
.6.Yo"" 100 mY
.}
51
II
2.S
..........
IL=USA
./
I .•
-
II
0
25
SO
75
........
1.240
"".ffi
~ 1.230
,:
100
"121 150
1.220
_7&
~
.
i.
I
i
i
40
20
0
r-
-so
-25
0
25
50
I
.,1-
I--
15
10
T~'5II"C
~/
\. /
.,3- ".
~
/
- :;;; ?'
2.0
I~ ~
rr
II
TJ = 2"C
10
oc
30
20
40
VI - V()t INPUTfOUTPUT
VOLTAGE DIFr:ERENTIAL - VdC
Ripple Rejection as a
Function of Frequency
120
,
{JJ)J.
!.
= 15 Y
Vo = lOY
VI
21
30
35
0
001
,
f"" 120 Hz
TJ = 250C
0.1
10
10. OUTPUT CURRENT - A
2·112
Il = SOD mA
I/~
i
d,
0
20
1---
/
VI = l5Y
I\. TJ=WC
Yo = lOY
\
f-~ITHOUT~
1"\1
40
\1\
'\..
i 20
CAdi = 10 1J.F
VI - Yo - 5 V
Vo. OUTPUT VOLTAGE - Y
CAdi"" 10 p.F
13 ..
I
WITHOUT CAdi
20
2.5
TJ "" _Sloe
100
10
IL = SOD mA
t. 120 Hz
TJ = we
15
3.0
00
100 125 150
TJ. JUNCTION TEMPERATURE -
I---
10
75
Ripple Rejection as a
Function of
Output Current
!
3 .•
05
..........
Ripple Rejection as a
Function of
Output Voltage
IC• d,
a:
"
!i"..
;
T J. JUNCTION TEMPERATURE - ·C
100
~
a:
I
....... ~ ........ ......
IL '" 200 RIA
1.!!. 7& -50 -25
E 40
..... ........
v'"
250
r- ~ :---.
.................. .::::: r-; ~
1-1'=1"1
c
r
V
IL '" SOOmA
II'
_c
g
.....
......... _,,=I.U
2.0
01S
>w
>~
4 .•
,
>
0
10
100
1k
10k
lOOk
f. FREQUENCY - Hz
1 II
10M
pA117·pA217·pA317
Typical Performance Curves (Cont.)
Output Impedance
10
,
10
o
w
"~>
F=~~ """" \50VV
~~L "" 500 rnA
TJ""25"C
1
L
,
5'
>z
/
~~
::»
ow
.0
/
/
..-
10 J
10
-
V
/
J
CAd) = 10pF
b-
10k
tOOk
1M
05
0
-0 5
w
_1 01-
"~>
"z"
'\
(\
\
0
C:~
-1
:;
~~
3
0
~
/1'-
05
0
20
10
30
Rl
240
~
VI
15 V
Vo:::: 10 V
INL 7 50 rnA
0
40
\
TJ=25'C
I
II
'\,
1 /LF
,.V
R2
-
\
10
20
30
-
VOUT
/L A117
1+
Rl
VREF
ADJUST
R2
+ Fi1)
+ IAdj R2
-IAdJ
Smce 'Adj is controlled to less than 100 p.A, the error associated
with this term is negligible m most applications.
\
t'PROG
VOU T
R2
_L...
Basic Circuit Operation
The p,A 117 is a 3·terminal floating regulator. In
operation, the p,A 117 develops and maintains a
nominal 1.25 V reference (VREF) between its output
and adjustment terminals. This reference voltage is
converted to a programming current (lProg) by R 1 (see
Figure 1), and this constant current flows through R2
to ground. The regulated output voltage is given by:
(1 + *)
40
Basic Circuit Configuration
C'N IS required if regulator is located an appreciable distance
from power supply filter.
= VREF
r-- b-
t, TIME - MS
Fig. 1.
VOUT
I,
rr-
Since the p,A 117 is a floating regulator, it is only the
voltage differential across the circuit which is
important to performance, and operation at high
voltages with respect to ground is possible.
CO UT
VOUT = 1.25 V (1
C L - 0, WITHOUT CAd)
Since the current from the adjustment terminal (lAdj)
represents an error term in the equation, the p,A 117
was designed to controllAdj to less than 0 and keep it
constant. To do this, a" quiescent operating current is
returned to the output terminal. This imposes the
requirement for a minimum load current. If the load
current is less than this minimum, the output voltage
will rise.
VO UT
ADJUST
5
j,ts
/L AI17
CIN
I--I--
-~
\
2
5
Standard Application
0.1 /LF
... ~
5Q
.....
10
Typical Applications
IAdJ •
C L :::: 1 MF,CMJ:::: 10!,-F
1
::»
I"
ILl
2
>z
-1 5
f, FREQUENCY - Hz
r--
\
II
t, TIME -
V IN
"
;:>
5,
'" ,
= 10 V
IL = SOmA
TJ = 25°C
Vo
I--
I I
I
CL :::: 1 j.tF, CAdI = 10 j.tF
\.
J
w
...
-."
1k
100
C L '" 0, WITHOUT CAd)
10
~
5'
>w
I
15
"'0
WITHOUT CAd)
,
Load Transient Response
Line Transient Response
,
VRef = 1.25 V TYPICAL
+ IAdj R2
2·113
•
JLA 117 • JLA217 • JLA317
Load Regulation
The /.IA 117 is capable of providing extremely good
load regulation, but a few precautions are needed to
obtain maximum performance. For best performance,
the programming resistor (Rl) should be connected
as close to the regulator as possible to minimize line
drops which effectively appear in series with the
reference, thereby degrading regulation. The ground
end of R2 can be returned near the load ground to
provide remote ground sensing and improve
load regulation.
Figure 2 shows the /.IA 117 with the recommended
protection diodes for output voltages in excess of
25 V or high capacitance values (Co> 25/.1F,
CAdi> 10 /.IF). Diode 01 prevents Co from
discharging through the IC during an input short
circuit. Diode 02 protects against capacitor CAdi
discharging through the IC during an output short
circuit. The combination of diodes Oland 02 prevents
CAdi from discharging through the IC during an input
short circuit.
Fig. 2.
Voltage Regulator with Protection Diode.
External Capacitor.
A 0.1 /.IF disc or 1.0 /.IF tantalum input bypass
capacitor (CIN) is recommended to reduce the
sensitivity to input line impedance.
01
IN4002
VO UT
The adjustment terminal may be bypassed to ground
to improve ripple rejection. This capacitor (CAdi)
prevents ripple from being amplified as the output
voltage is increased. A 10 /.IF capacitor should
improve ripple rejection about 15 dB at 120 Hz in a
10 V application.
R1
02
IN4002
+
ADJUST
Although the /.IA 117 is stable with no output
capacitance, like any feedback circuit, certain values
of external capacitance can cause excessive ringing.
An output capacitance (Co) in the form of a 1.0 /.IF
tantalum or 25 /.IF aluminum electrolytic capacitor on
the output swamps this effect and insures stability.
I - - - - -......--~
R2
Protection Diode.
When external capacitors are used with any IC
regulator it is sometimes necessary to add protection
diodes to prevent the capacitors from discharging
through low current pOints into the regulator.
2-114
Co
~A431
F=AIRCHILD
Adjustable Precision
Shunt Regulator
A Schlumberger Company
Linear Products
Connection Diagram
TO-92 Package
Description
The JlA431 is a 3-terminal Adjustable Shunt Regulator
with guaranteed temperature stability over the entire
temperature range of operation. The output voltage
may be set at any level greater than 2.5 V (VREF) up
to 36 V merely by selecting two external resistors that
act as a voltage divided network. Due to the sharp
turn-on characteristics this device is an excelient
replacement for many zener diode applications.
REF
(2)
~'A,"OO'
ANODE
•
(1)
(3)
This product wili operate over the entire temperature
range of -55°C to +125°C. This includes the unique
automotive range of -40°C to +85°C.
(Top View)
Order Information
Type
Package
JlA431 C
Molded
• AVERAGE TEMPERATURE COEFFICIENT
50 ppm/oC
• TEMPERATURE COMPENSATED FOR
OPERATION OVER THE FULL
TEMPERATURE RANGE
• PROGRAMMABLE OUTPUT VOLTAGE
• FAST TURN-ON RESPONSE
• LOW OUTPUT NOISE
Code
EI
Absolute Maximum Ratings
Cathode Voltage
Continuous Cathode Current
37 V
-10 mA to
+150 mA
-.5 V
Reference Voltage
Reference Input Current
Operating Temperature Range
JlA431C
Storage Temperature Range
TO-92 Molded
Power Dissipation
TO-92 Molded
Pin Temperature (Soldering)
TO-92 Molded (lOs)
Operating Conditions
Cathode Voltage, Vz
Cathode Current, Iz
10 mA
775mW
260°C
Min
VREF
1 mA
Equivalent Circuit
r -______________________________~--~r_--~--_.--1 CATHODE
(v z)
C2
R6
12 k
R7
12 k
R3
2.5 k
04
02
01
R2
1k
R5
640 !l
R1
3.3 !l
2 ANODE
(GND)
2-115
Part No.
JlA431AWC
Max
37 V
100 mA
~A431
Electrical Characteristics
At 25°C ambient temperature unless otherwise noted
/LA431C
Condition
Min
Typ
Max
Unit
Reference Voltage
Vz = VREF, liN = 10 mA
(Figure 1)
2.440
2.495
2.550
V
VOEV
Deviation of Reference
Input Voltage Over
Temperature
Vz
VREF, liN
10 mA,
TA = full range,
See Note 1 (Figure 1)
a
17
mV
AVREF
AVZ
Ratio of the
Change in Reference
Voltage to the Change
in Cathode Voltage
Iz = 10 mA
(Figure 2)
Vz from VREF
to 10V
-1.4
-2.7
mVIV
Vz from
10 V to 36 V
-1
-2
mV/V
IREF
Reference Input
Current
R1 = 10 kfl, R2
00,
liN = 10 mA (Figure 2)
2
4
/LA
alREF
Deviation of
Reference Input
Current over
Temperature
R1 = 10 kfl, R2 =
liN = 10 mA,
TA = Full Range
(Figure 2)
0.4
1.2
/LA
IZ(MIN)
Minimum Cathode
Current for
Regulation
Vz = VREF (Figure 1)
0.4
1
mA
IZ(OFF)
Off-State Current
Vz = 36 V, VREF = 0 V
(Figure 3)
0.3
1
/LA
rz
Dynamic Output
Impedance
Vz = VREF,
Frequency = 0 Hz,
See Note 2 (Figure 1)
.75
fl
Symbol
Characteristic
VREF
=
=
=
00,
Notes
1. Oeviation of reference input voltage. VOEV. is defined as the
maximum variation of the reference input voltage over the full
temperature range.
aVREF can be positive or negative depending
on whether the slope is positive or negative.
Example: VOEV = 8 mY. VREF = 2495 mY.
T2 -T 1 = 70°C. slope is positive
---..
.....
-----:::;-
G489~~V] 10'
aVREF =
~
= +46 ppm/oC
2. The dynamic output impedance. rZ. is
defined as:
tl.VZ
T,
rz=~
TEMPERATURE
When the device is programmed with two external resistors. Rl
and R2. (see Figure 2). the dynamic output impedance of the
overall circuit. rz'. is defined as:
The average temperature coefficient of the
reference input voltage. aVREF. is defined as:
ppm
[
10'
10'
aVREF - - = + VMax - VMin
+ [
VOEV
°C
- VREF (at 25°CU
- - L"REF (at 25°CiJ
1 _
T2- T l
:l
rz'
T2- T l
where T2 -Tl = full temperature change.
2-116
=
tl.VZ'
tl.IZ'
[
"'"
Rl]
rz
1+
R2
#LA431
Typical Performance Curvea
Input Current aa a Function of
Dynamic Impedance aa a
Function of Frequency
Vz
,.
TA= 2!rC
Vz = YREF
e::
500
'1
I
w
I
... 400
ii3
300
I
~
I
"az
Iz MIN
'00
•
!!
~
1j
1;
/
/
I
Ie
J
il!200
I
,.
/
I
.!'
. ..
•,
Yz - CATHODE VOlTAGE _ V
~
,
/
./
'00.
FREQUENCY - Hz
,.M
'M
1 kll
SOil
Thermal Information
~
'000
tide = 10 mA
"-
-=-
","'~
'"
Range of Inatablllty
.........
........
70
,.~-
. """ .........
TEMPERATURE _
r--c
E
I
'25
!i
w
-c
II:
II:
..""...
"i!!
STABLE
I
z
Input Current aa a Function of
Vz
CLOAD
..liN
1
I
!i
'OO~-4---+---+---+--~--~
230 Il
!
i ~r--+--~~~-+--+-~
CLOAD
I
~
Yz - CATHODE VOLTAGE - y
2-117
•
~A431
DC Test Circuits
Fig. 1 Test Circuit For Vz
= VREF
Fig. 3
IIN~
Test Circuit for Off-State Current
INPUT-.l\lV"'""_--VZ
INPUT-f\NIr-_--vz
.--.......,~
-~
liz
--'t'
_L.
Fig. 2
Test Circuit For Vz
> VREF
INPU T
Vz
R1
IREF
--+-- ~~tl z
R2
t
.... ~
VREF
t
_L..
Vz
= VREF (1
+ R1/R2) +IREFe R1
2-118
t
Iz OFF
J.LA78S40
Universal Switching
Regulator Subsystem
FAIRCHILD
A Schlumberger Company
Linear Products
Description
The ~A78S40 is a Monolithic Regulator Subsystem
consisting of all the active building blocks necessary
for switching regulator systems. The device consists
of a temperature-compensated voltage reference, a
duty-cycle controllable oscillator with an active
current limit circuit, an error amplifier, high-current,
high-voltage output switch, a power diode and an
uncommitted operational amplifier. The device can
drive external npn or pnp transistors when currents in
excess of 1.5 A or voltages in excess of 40 V are
required. The device can be used for step-down, stepup or inverting switching regulators as well as for
series pass regulators. It features wide supply voltage
range, low standby power dissipation, high efficiency
and low drift. It is useful for any stand-alone, low part
count switching system and works extremely well in
battery operated systems.
Connection Diagram
16-Pln DIP
• STEP-UP, STEP DOWN OR INVERTING
SWITCHING REGULATORS
• OUTPUT ADJUSTABLE FROM 1.3 to 40 V
• PEAK CURRENTS TO 1.5 A WITHOUT
EXTERNAL TRANSISTORS
• OPERATION FROM 2.5 to 40 V INPUT
• LOW STANDBY CURRENT DRAIN
• 80 dB LINE AND LOAD REGULATION
• HIGH GAIN, HIGH CURRENT, INDEPENDENT
OPAMP
• PULSE WIDTH MODULATION WITH NO DOUBLE
PULSING
Order Information
Type
Package
~A78S40
Ceramic DIP
~A78S40
Ceramic DIP
~A78S40
Molded DIP
16
SWITCH COLLECTOR
OIODE CATHODE
DRIVER COLLECTOR
DIODE ANODE
14
SWITCH EMITTER
Ipk SENSE
OP AMP OUTPUT
Vee
OP AMP SUPPLY
TIMING CAPACITOR
OPAMP NON- 6
INVERTING INPUT
GROUND
OP AMP
COMPARATOR
INVERTING INPUT 8
INVERTING INPUT
REFERENCE
COMPARATOR NONVOLTAGE ~I_ _ _ _ _.INVERTING INPUT
(Top View)
Code
Part No.
68
68
98
~A78S40DM
~A78S40DC
~A78S40PC
Block Diagram
COMPARATOR
NON-INVERTING
INPUT
~---
COMPARATOR
INVERTING
INPUT
Vee
TIMING
CAPACITOR
___ 1___
9
10
13 BIAS
Ipk
SENSE
DRIVER
COLLECTOR
GROUND
SWITCH
COLLECTOR
___ 8 _________ ,
12
14
11
15
16
I
I
I
I
I
I
I
I
I
I
I
U-l-!
REFERENCE
VOLTAGE
OP AMP
INVERTING
INPUT
OP AMP
SUPPLY
OP AMP
OUTPUT
2-119
SWITCH
DIODE
DIODE
EMITTER CATHODE ANODE
•
J.LA78S40
Absolute Maximum Ratings
Input Voltage from V+ to VInput Voltage from V+
Op Amp to VCommon Mode Input Range
(Error Amplifier and Op Amp)
Differential Input Voltage (Note 1)
Output-Short Circuit Duration
(Op Amp)
Current from VREF
Voltage from Switch
Collectors to GND
Voltage from Switch
Emitters to GND
Voltage from Switch
Collectors to Emitter
Voltage from Power Diode
to GND
Reverse Power Diode
Voltage
Current through Power Switch
Current through Power Diode
Internal Power Dissipation
(Note 2)
Molded DIP
Ceramic DIP
Storage Temperature Range
Operating Temperature Range
Military (/LA78S40M)
Commercial (/LA 78S40C)
Pin Temperature
Ceramic DIP (Soldering, 60 s)
Molded DIP (Soldering, 10 s)
40 V
40 V
-0.3 to V+
±30 V
continuous
10 mA
40 V
40 V
40 V
40 V
40 V
1.5 A
1.5 A
1500 mW
1000 mW
-65°C to +150°C
-55°C to 125°C
O°C to 70°C
300°C
260°C
Notes
1. For supply voltages less than 30 V, the absolute maximum
voltage is equal to the supply voltage.
2 Ratings apply to 25·C ambient, derate ceramic DIP at
8 mW /·C and plastic DIP at 14 mW / ·C.
The current limit modifies the ON time. The current
limit is activated when a 300 mV potential appears
between pin 13 (Vee) and pin 14 (I pk). This potential
is intended to result when designed for peak current
flows through Rse. When the peak current is reached
the current limit is turned on. The current limit circuitry
provides for a quick end to ON time and the immediate
start of OFF time. Generally the oscillator is free
running but the current limit action tends to reset the
timing cycle.
Increasing load results in more current limited ON
time and less OFF time. The switching frequency
increases with load current.
VD is the forward voltage drop across the internal
power diode. It is listed on the data sheet as 1.25 V
typical, 1.5 V maximum. If an external diode is used,
then its own forward voltage drop must be used for YD.
Vs is the voltage across the switch element (output
transistors 01 and 02) when the switch is closed
or on. This is listed on the data sheet as output
saturation voltage.
Output saturation voltage 1 - defined as the
switching element voltage for 02 and 01 in
the Darlington configuration with collectors tied
together. On the data sheet this applies to Figure 1,
the step down mode.
Output saturation voltage 2 - switching element
voltage for just 01 used as a transistor switch.
This applies to Figure 2 of the data sheet, the
step-up mode.
For the inverting mode, Figure 3, the saturation
voltage of the external transistor should be used
for VS.
Functional Description
The /LA78S40 is a variable frequency, variable duty
cycle device. The initial switching frequency is set by
the timing capacitor. The initial duty cycle is 6: 1.
This switching frequency and duty cycle can be
modified by two mechanisms-the current limit
circuitry (lpk sense) and the comparator.
The comparator modifies the OFF time. When the
output voltage is correct, the comparator output is in
the HIGH state and has no effect on the circuit
operation. If the output voltage is too high then the
comparator output goes LOW. In the LOW state the
comparator inhibits the turn on of the output stage
switching transistors. As long as the comparator is
LOW the system is in OFF time. As the output current
rises the OFF time decreases. As the output current
nears its maximum the OFF time approaches its
minimum value. The comparator can inhibit several ON
cycles, one ON cycle or any portion of an ON cycle.
Once the ON cycle has begun the comparator cannot
inhibit until the beginning of the next ON cycle.
2-120
JLA78S40
Electrical Characteristics
Characteristic
VIN = 5.0 V, VOp Amp
otherwise specified.
= 5.0 V, TA = Operating temperature range, unless
ICondition
IMin ITyp IMax IUnit
General Characteristics
Supply Voltage
Supply Current
(Op Amp Disconnected)
Supply Current Op Amp
Connected
2.5
= 5.0 V
= 40 V
VIN = 5.0
VIN = 40 V
40
V
3.5
5.0
mA
mA
4.0
5.5
mA
mA
1.245
1.310
V
0.04
0.2
mVIV
0.2
0.5
mV/mA
1.8
2.3
VIN
VIN
Reference Section
0< TA < 70°C #A78S40C
= 1.0 mA
Reference Voltage
IREF
Reference Voltage Line
Regulation
VIN = 3.0 V to VIN
TA = 25°C
Reference Voltage Load
Regulation
IREF
-55°C < TA < 125°C
#A78S40M
1.180
= 40 V, IREF = 1.0 mA,
= 1.0 mA to IREF = 10 mA, TA = 25°C
Oscillator Section
= 5.0 V, TA = 25°C
= 40 V. TA = 25°C
VIN = 5.0 V, TA = 25°C
VIN = 40 V, TA = 25°C
VIN = 5 V, TA = 25°C
Charging Current
VIN
20
50
#A
Charging Current
VIN
20
70
#A
150
250
#A
150
350
#A
Discharge Current
Discharge Current
Oscillator Voltage Swing
tonltoff
Current Limit Section
Current Limit Sense
Voltage
TA
0.5
V
6.0
#s/#s
= 25°C
mV
Output Switch Section
Output Saturation
Voltage 1
ISW
Output Saturation
Voltage 2
Isw
Output Transistor hFE
Output Leakage Current
= 1.0 A.
Figure 1
= 1.0A, Figure 2
IC = 1.0 A, VCE = 5.0 V, TA = 25°C
VOUT = 40 V. TA = 25°C
1.1
1.3
V
0.45
0.7
V
70
10
nA
Power Diode
Forward Voltage Drop
10 = 1.0 A
Diode Leakage Current
Vo
V
= 40 V, TA = 25°C
nA
Comparator
Common Mode Voltage
Range
= VREF
= VREF
VCM = VREF
TA = 25°C
Power Supply Rejection
Ratio
VIN
Input Offset Voltage
Input Bias Current
Input Offset Current
VCM
1.5
15
VCM
35
200
nA
5.0
75
nA
0
= 3.0 V to 40 V. TA = 25°C
70
mV
V+ -2 V
96
dB
2·121
.-.':..----
-~--
-
- .---~~-.
...------
•
#LA78S40
Electrical Characteristics
VIN = 5.0 V, VOp Amp = 5.0 V, TA = Operating temperature range, unless
otherwise specified.
Characteristic
Condition
Typ
Min
Max
Unit
mV
Output Operational
Amplifier
Input Offset Voltage
VCM = 2.5 V
4.0
15
Input Bias Current
VCM = 2.5 V
30
200
nA
Input Offset Current
VCM = 2.5 V
5.0
75
nA
Voltage Gain +
RL = 2.0 k to GND; Va = 1.0 to 2.5 V,
TA = 25°C
25 k
250 k
VIV
Voltage Gain -
RL = 2.0 k to V+ Op Amp;
Va = 1.0 to 2.5 V, TA = 25°C
25 k
250 k
VIV
Common Mode Voltage
Range
TA = 25°C
0
Common Mode Rejection
Ratio
VCM = 0 to 3.0 V, TA = 25°C
76
100
dB
Power Supply Rejection
Ratio
V+ Op Amp = 3.0 to 40 V, TA = 25°C
76
100
dB
Output Source Current
TA = 25°C
75
150
rnA
Output Sink Current
TA = 25°C
10
35
rnA
Slew Rate
TA = 25°C
0.6
V//J.s
Output LOW Voltage
IL = -5.0 rnA, TA = 25°C
1.0
V
V+OP
Amp
-3.0 V
IL = 50 rnA, TA = 25°C
Output HIGH Voltage
V+ -2 V
V
Design Formulas
Characteristic
Step Down
Inverting
Step Up
+ Vo -
VOUT
IPk
2IOUT(Max)
Rsc
0.33/1pk
2 IOUT(Max) •
Ion
VOUT
+ Vo
VOUT
L
loff
+ Vo -
CT (I'F)
VOUT
45 X 10 5 10ff (I'S)
Co
IIN(Avg)
(Max load
ConditIon)
+ Vo
VIN
~
2
.
IVOUTI
VIN
•
toft
+ Vo
VOUT
VOUT
+ Vo
VIN - Vs
-VIN
.
+ Vo
Vs + Vo
- VIN
IVOUTI
VIN -
•
I'H
toft
L
1'8
+ Vo
21pk •
VOUT
VOUT
2
+ Vo -
I'F
(lpk -lOUT)
toft
Vnppl e
~
VOUT
•
Ipk •
45 X 10 510ff~S)
(Ipk - lOUT)
21pk •
.
+ Vo
IPk
2
+ loff)
8 V"pple
VIN - Vs
VIN - Vs
45 X 10 5 10ff(1'8)
Ipk • (ton
Efficiency
VOUT
+ Vo
IVOUTI
Ipk • L
+ Vo
A
[)
VIN
Ipk
Ipk • L
10ff
- Vs
VIN - Vs
VIN - Vs
VOUT
•
+ Vo -
VOUT
+ Vo
IPk
+ IVOUT I + Vo
0.331 pk
VIN - Vs - VOUT
loff
VIN
2 IOUT(Max) •
VIN - Vs
o 331pk
-
Unit
Vs
VIN - Vs
---
Vs
VIN
Ipk
-2
.
• loff
I'F
V"pple
•
IVOUTI
VIN
2
IVOUTI
VOUT
+ Vo
+ Vo
+ I VOUT I + Vo
A
- Vs
H
2·122
J,tA78S40
Fig. 1.
Typical Step-Down Performance
TA = 25°C
Fig. 2.
Typical Step-Up Operational Performance
TA 25°C
=
Rse
V"
2' V
Rse
V"
10 V
033 !1
Vee
~
rElIAS -
---
300 /JH
033 Jl
CT
00111F
rYVY"o
CT
~'~
-~-- - - - -
Vee
I
lal~-
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
+----t:
I
01
I
01
~
6
I
I
I
I
I~:-R---'I
I
I
I
I
I
I
I
I
I
jJ.A78S40
C-1
I""
I
I
I
I
I
I
__
r--~"'(V02
I
I
I
I
I
I
_E __ ~8~!
- --
I
CT
I"
t-r-
OSCILLATOR
:
1
....._ _C
...
V01
,.....
I
I
I
I
I
r--......
r--r--;I~~
I
I~o/
,..A78S40
..--t---I~
I
I
~
iA I
~ ~E:R~N:~ ~AMP __ ___ ~_J
I
Your
1.3 V
I
-OP
011
10 V
YOUT
L
300 /lH
R2
12k
Characteristic
R1
85k
Condition
lOUT = 200 rnA
20 :5 VIN :5 30 V
5 rnA:5 lOUT
lOUT :5 300 rnA
Max Output Current VOUT = 9.5 V
Output Ripple
lOUT = 200 rnA
Efficiency
lOUT = 200 rnA
Standby Current
lOUT = 200 rnA
Output Voltage
Line Regulation
Load Regulation
2' V
R1
R2
12 k
CO
I'OO
230 k
_F
Typical
Value
Characteristic
10 V
1.5 rnV
Output Voltage
Line Regulation
Load Regulation
Condition
Typical
Value
25 V
lOUT = 50 rnA
5 V :5 VIN :5 15 V 4.0 rnV
5 rnA :5 lOUT
2.0 rnV
lOUT :5 100 rnA
160 rnA
Max Output Current VOUT
23.75 V
30 rnV
Output Ripple
lOUT = 50 rnA
79%
Efficiency
lOUT = 50 rnA
2.6 rnA
Standby Current
lOUT = 50 rnA
3.0 rnV
500 rnA
50 rnV
74%
2.8 rnA
=
Noles
1 For lOUT 2: 200 mA use external diode to limit on chip
power dissipation
2 It'is recommended that the internal reference (pin 8) be
bypassed by a 0.1 /IF capacitor directly to (pin 11) the ground
point of the /lA78S40.
2-123
•
J,LA78S40
Fig. 3.
Typical Inversion Operational Performance
TA
= 25°C
Typical Performance Curves
300 MH
CT as a Function of toff
R"c
V'N
12 V
033 !l
47 0
[7
VIN = 5 V
TA "'- 25"C
Vee
IeIAS -
-
--
_ll __
47
---I
I
I
I
I
I
I
I
I
I
7
/
I
I
I
I
I
i/
047
V
/
10
I
100
1000
toll - /-'-5
I
I
I
I
VREF as a Function of TJ
1220
121
• \\
121 6
121 4
VOUT
-15 V
112k
VIN
\
25k
121 0
Co
l200 pF
--
--
1212
5V
=
•
120
1206
1204
1202
Characteristic
Condition
Typical
Value
1200
-50
-25
0
25
TJ _.
-15 V
lOUT = 100 rnA
8 V :5 VIN :5 18 V 5.0 rnV
5 rnA:5 lOUT
3.0 rnV
lOUT :5 150 rnA
Max Output Current VOUT = 14.25 V
160 rnA
Output Ripple
lOUT = 100 rnA
20 rnV
Efficiency
lOUT
100 rnA
70%
Standby Current
lOUT = 100 rnA
2.3 rnA
50
75
100
125
'c
Output Voltage
Line Regulation
Load Regulation
=
Idlscharge as a Function of VIN
250
TA
=
/
25°C
./
V
20 0
150
2-124
1/
V-
o
10
20
30
40
50
JLA78S40
Typical Performance Curves (Cont.)
VS ense as a Function of VIN
400
TA '" 25°C
350
f~ 300
--
I-- I--
~
>
250
200
o
10
20
30
40
50
Typical Pulse Width Modulator Application
2N605-,1'--_ _ _ _ _ _-t--I100 ~H
FREQ.20 KHz
30Vln
1800
+
1.6 K
.004
~F
I100~F
-=-
I
r--I
I
I
I
I
I
I
I
I
I
MBR4030
SHOTIKY
10
9
12
13
,,
I
,,
I
IL ___
22 K
~~~Ar~~--~------------------------~----------~-5V
5A
8.2 K
.01
11~F
-=-
.02
~F
JOK
.005
~F
-=~F
2·125
JlA494
Pulse Width Modulated
Control Circuit
F=AIRCHILO
A Schlumberger Company
Linear Products
Connection Diagram
1S-Pln DIP
Description
The ~A494 is a monolithic integrated circuit which
includes all the necessary building blocks for the
design of pulse width modulated (PWM) switching
power supplies, including push-pull, bridge and series
configurations. The device can operate at switching
frequencies between 1.0 kHz and 300 kHz and output
voltages up to 40 V. The ~A494C is specified over an
operating temperature range of QOC to 7QoC and the
~A494M is specified over an operating temperature
range of -55°C to 125°C.
NON-INV
INPUT
NON-INV
INPUT
INV
INPUT
COMPEN/ 3
t----I
PWM COMP
INPUT
DEAD 4
TIME
................. ""'CONTROL 5
•
UNCOMMITTED OUTPUT TRANSISTORS
CAPABLE OF 200 mA SOURCE OR SINK
• ON-CHIP ERROR AMPLIFIERS
• ON-CHIP 5 V REFERENCE
• INTERNAL PROTECTION FROM DOUBLE
PULSING OF OUTPUTS WITH NARROW PULSE
WIDTHS OR WITH SUPPLY VOLTAGES BELOW
SPECIFIED LIMITS
• DEAD TIME CONTROL COMPARATOR
• OUTPUT CONTROL SELECTS SINGLE-ENDED OR
PUSH-PULL OPERATION
• EASILY SYNCHRONIZED (SLAVED) TO
OTHER CIRCUITS
INV
INPUT
VREF
OUTPUT
CONTROL
CT
Vee
C2
GROUND
E2
C1
E1
(Top View)
Order Information
Type
Package
/J-A494C
Ceramic DIP
/J-A494C
Molded DIP
/J-A494M
Ceramic DIP
Code
6A
9A
6A
Part No_
/J-A494DC
~A494PC
/J-A494DM
Equivalent Circuit
OUTPUT
CONTROL
PULSE STEERING
FLIP FLOP
RT~6~________~--------'
-----1
Cr _ _ _
OSCILLATOR
5
C2
12
16
ERROR
AMP
2
ERROR
15 AMP
3
COMPENSATION/ PWM
COMPARATOR INPUT
2-126
"~,,
14
Vee
VREF
7 Gnd
~A494
Absolute Maximum Ratings
Power Supply Voltage (Vcc)
Voltage From Any Pin to Ground
(except pin 8 and pin 11)
Output Collector Voltage
(VC1, VC2)
Peak Collector Current
(IC 1 and IC2)
Internal Power Dissipation (Note)
Molded DIP
Ceramic DIP
Storage Temperature Range
Operating Temperature Range
Pin Temperature
Ceramic DIP (Soldering, 60 s)
Molded DIP (Soldering, 10 s)
IlA494C
42 V
VCC + 0.3 V
42 V
250 mA
1500 mW
1000 mW
-65°C to + 150°C
O°C to 70°C
3OO·C
260·C
Functional Description
The basic oscillator (switching) frequency is
controlled by an external resistor (Rr) and
capacitor (Cr). The relationship between the values of
Rr Cr and frequency is shown in Figure 10.
The dead time control prevents on-state overlap of
the output transistors as can be seen in Figure 5. The
dead time is approximately 3 to 5% of the total period
if the dead time control (pin 4) is grounded. This dead
time can be increased by connecting the dead time
control to a voltage up to 5 V.
The level of the sawtooth wave form is compared with
an error voltage by the pulse width modulated
comparator. The output of the PWM Comparator
directs the pulse steering flip flop and the output
control logic.
The frequency response of the error amps
(Figure 11) can be modified by using external
resistors and capacitors. These components are
typically connected between the compensation
terminal (pin 3) and the inverting input of the error
amps (pin 2 or pin 15).
The error voltage is generated by the error amplifier.
The error amplifier boosts the voltage difference
between the output and the 5 V internal reference.
See Figure 7 for error amp sensing techniques. The
second error amp is typically used to implement
current limiting.
The switching frequency of two or more IlA494 circuits
can be synchronized. The timing Capacitor, Cr is
connected as shown in Figure 8. Charging current is
provided by the master circuit. Discharging is through
all the circuits slaved to the master. Rr is required
only for the master circuit.
The output control logic (pin 13) selects either pushpull or single-ended operation of the output transistors
(see Figure 6).
Recommended Operating Conditions
IlA494C
Symbol
Characteristic
Min
Max
Unit
VCC
VIN
7.0
40
V
VC1, VC2
IC1,IC2
Power Supply Voltage
Voltage on Any Pin Except Pins 8 and 11
(Referenced to Ground)
Output Voltage
Output Collector Current
-0.3
-0.3
VCC +0.3
40
200
CT
Timing Capacitor
RT
foac
TA
Timing Resistor
Oscillator Frequency
Operating Ambient Temperature Range
V
V
mA
pF
IlF
kU
kHz
°C
470
1.8
1.0
0
Note
Ratings apply at 25°C, above 25°C ambient derate Hermetic DIP
at 8 mW/oC and Plastic DIP at 14 mW/oC
2-127
10
500
300
+70
•
~A494
~A494C
Electrical Characterl8tlc8 Recommended Operating Conditions per above except Vee = 15 V, f08c = 10 kHz,
TA = 0 to 70·C unless otherwise specified.
Symbol
Characteri8tic
Unit
Condition
Reference Section
= 1.0 mA
5.0
5.25
V
2.0
25
mV
Temperature Coefficient of
O°C < TA < 70°C
Reference Voltage
0.01
0.03
%I·C
Load Regulation of
Reference Voltage
1.0
15
mV
4.75
VREF
Reference Voltage
IREF
Regline
Line Regulation of
Reference Voltage
7.0 V < Vee < 40 V
TCVREF
Regload
1
20
Z
~
cL = 0
10
~
V
)t--..
50
i'-
I
"""'\
0.1
~
g
1
-
CL
110
100
1k
10 k
LOAD FREQUENCY - Hz
'\
20
'\
1\
10
0.01
10
30
1,\
p.F JANT
10
1
a:
w
40
~
Cl -Ol;J.Fj
20
~
~
is
~
0 05
.
/
1\
~
100 k
1M
o
10
50 100
500
1k
FREQUENCY - Hz
3-4
5 k 10 k
-25
0
25
50
75
100
CASE TEMPERATURE _·C
125
150
,uA78H05 • ,uA78H05A
Typical Performance Curves (Cont.)
Short Circuit Current
Dropout Voltage
Quiescent Current
,.
5
--
~
TJ=-lc X
r-..
"""-
TJ "'75OC,,",
.........
"
...........
••
.,.
(
...........T, = 2SOC
,
"
2•
3D
/
Line Regulation
'our=5A
~-10~---+-H--+----i-----r---1
i-~
i
,.
~ -30I----+-IIf---+---I----+---I
g
§5
~
YOUT, ~
25
25
5V
-00.~----~~~'.~--~'5~---~L----J25
Iv
•
, •
i
Load Regulation
•
125
100
150
Ripple Rejection
VIN = 10 Y
CL 01 p.F
=
""
>
INPUT VOLTAGE _ V
75
,~
rt1our=SA
1-,00
i
00
JUNcnON TEMPERATURE _ "C
'DO
~
,
'll
z
0
80
1=
III
IOUT
;J
a: 80
II!
o
20
40
80
3A
IQUTlsA
, ,.
PULSE WIDTH nME _ ,.,.1
Load Transient Response
l
40
~
80 100
YIN = lOY
CL = O.1,.,.F
I
~
5 ,•
-40
-
pr-
,
'5
" -00
I-----+-ff--+----+----+----I
Iourl = 3 Af---
I
100
, 00
I
IouT=2A
Line Transient Response
:e
5V
=
1aur=5A
" TJ = 25"C
INPUT VOLTAGE _ V
INPUT VOLTAGE - V
>
-
~J=''''c
••
35
Your
>
I
100
1k
I\.
"V
"-
~
10k
lOOk
'M
INPUT FREQUENCY - Hz
Output Voltage
Deviation vs
Junction Temperature
'l: ~ '-""""""-'-''''-'''''''''''''-''''-v"',.-=-,'''.-v''
100 I--+-+-If---+-+-+--"~l =O.l,.,.F
~
>
~-,.~---t~~~--~-----r----1
;-2.~---t----+---~~~~~__1
w
"
~-30
~ I-+-+-;,/f-i-t--+--+--+-I--t
"-'00
5
5-~~-+~~+-~-+~~
.
o
ill
~
l!I
-00
r-l. . . . .;f--t~~;$:~'
~UT:.:.=
=SA r-;::
2A
C
~
g-'00 1---+--+--1--+--+--+--+--1
I!
5
1-,00 1---+--+--1--+--+--+--+--1
§-40
-00 '--_-'-_--...J'--_-'--_---'_ _..J
•
o 20 40 eo 80 100
OUTPUT CURRENT _ A
PULSE WIDTH nilE _ ILl
3-5
JUNCTION TEMPERATURE _ ·C
J,LA78H05 • J,LA78H05A
Test Circuit
Fixed Output Voltage
1
SOLID
TANTALUM
+
I'A78H05
I'A78H05A
C1N
2
VOUT
+
...... CL
3
0.1
11'F
.1
Design Considerations
These devices have thermal-overload protection from
excessive power and internal short-circuit protection
which limits the circuit's maximum current. Thus, the
devices are protected from overload abnormalities.
Although the internal power dissipation is limited, the
junction temperature must be kept below the maximum
specified temperature (150°C). It is recommended by
the manufacturer that the maximum junction"
temperature be kept as low as possible for increased
reliability. To calculate the maximum junction
temperature or heat sink required, the following
thermal resistance values should be used:
Package
Typ
Max
OJC
TO-3
OJC
1.8
PO(max) =
OCA
Where:
TJ
TA
Po
OJC
OCA
OCS
OSA
The devices are designed to operate without external
compensation components. However, the amount of
external filtering of these voltage regulators depends
upon the circuit layout. If in a specific application the
regulator is more than four inches from the filter
capacitor, a 1 /LF solid tantalum capacitor should be
used at the input. A 0.1 /LF capacitor should be used
at the output to reduce transients created by fast
switching loads, as seen in the basic test circuit.
These filter capacitors must be located as close to
the regulator as possible.
Caution: Permanent damage can result from forcing
the output voltage higher than the input voltage. A
protection diode from output to input should be used if
this condition exists.
2.5
TJ(max) - TA
OJC + OCA
= OCS + OSA
Solving for TJ:
TJ = TA + Po (OJC
COMMON
+ OCA)
= Junction Temperature
= Ambient Temperature
= Power Dissipation
= Junction-to-case thermal resistance
= Case-to-ambient thermal resistance
= Case-to-heat sink thermal resistance
= Heat sink-to-ambient thermal resistance
3·6
JlA78P05
5-Volt 10-Amp
Voltage Regulator
FAIRCHILD
A Schlumberger Company
Hybrid Products
Connection Diagram
To-3 Metal Package
Description
The /lA78P05 3-terminal positive 5 V regulator,
consisting of a monolithic control chip driving a seriespass transistor, is capable of delivering 10 A. This
hybrid device is virtually blow-out proof and contains
all the protection features inherent in monolithic
regulators such as internal short-circuit current
limiting, thermal overload and safe-area protection. If
the safe-operating area is exceeded, the device shuts
down rather than failing or damaging other system
components (Note 1). This feature eliminates costly
output circuitry and overly conservative heat sinks
typical of high-current regulators built with discrete
components. The /lA78P05 is packaged in a
hermetically sealed TO-3 providing 70 W
power dissipation.
•
• 10 A OUTPUT CURRENT
• INTERNAL THERMAL OVERLOAD PROTECTION
• INTERNAL SHORT CIRCUIT CURRENT LIMIT
• LOW DROPOUT VOLTAGE (TYPICALLY 2_3 V@
10 A)
• 70 W POWER DISSIPATION
• PIN-FOR-PIN COMPATIBLE WITH THE /lA78H05,
/lA78H05A AND SH323
• STEEL TO-3 PACKAGE
(Top View)
Order Information
Type
Package
/lA78P05
Metal
/lA78P05
Metal
Note
1 This voltage regulator offers output transistor safe-area
protection However, to maintain full protecllon, the device
must be operated within the maximum Input·to-output voltage
differential ratings as listed on this data sheet under "Absolute
Maximum Ratings." For applications violating these limits,
device will not be fully protected.
Part No.
/lA78P05SC
/lA78P05SM
Code
6N
6N
Block Diagram
T
I
START
CIRCUIT
T
CURRENT SOURCE
I
VOLTAGE
REGULATOR
I
-~
r--
7
VIN
THERMAL
SHUTDOWN
R
1',
1
1
SHORT.
CIRCUIT
PROTECTION
....
L
~
........
Rsc
IJ
2
VOUT
3
COMMON
3-7
~A78P05
Absolute Maximum Ratings
Input Voltage
Input-to-Output Voltage
Differential, Output ShortCircuited
Internal Power Dissipation
Operating Junction
Temperature
,uA78P05
Electrical Characteristics
40 V
Military Temperature Range
,uA78P05SM
Commercial Temperature
Range ,uA78P05SC
Storage Temperature Range
Pin Temperature
(Soldering, 60 s)
35 V
70 W @ 25°C Case
150°C
TJ
-55°C to +150°C
O°C to +150°C
-55°C to +150°C
300°C
= 25°C, VIN = 10 V, lOUT = 2.0 A unless otherwise specified
Limits
Symbol
Characteristic
Condition
VOUT
Output Voltage
lOUT
~VOUT
Line Regulation (Note 2)
VIN
~VOUT
Load Regulation (Note 2)
10 mA
~VOUT
Load Regulation (Note 2)
10 mA
la
Quiescent Current
lOUT
RR
Ripple Rejection
=0
lOUT = 1.0 A, f = 120 Hz, 5.0 Vpk-pk
Vn
Output Noise
10Hz
VOO
Dropout Voltage (Note 3)
los
Short-Circuit Current Limit
= 2.0 A
= 8 to 25 V
lOUT
lOUT
:s::
:s::
lOUT
:s::
Min
Typ
Max
Unit
4.85
5.0
5.25
V
5A
10UT:S:: 10 A
:s:: f :s::
10
50
mV
25
40
mV
50
75
mV
3.4
10
mA
60
dB
100 kHz
40
= 5.0 A
= 10 A
,uVRMS
2.0
2.3
V
2.5
3.0
V
14
Notes
2. Load and hne regulation are specified at constant junction
temperature. Pulse testing is required with a pulse width
~ 1 ms and a duty cycle ~ 5%. Full Kelvin connection
methods must be used to measure these parameters.
Apk
3. Dropout Voltage is the input-output voltage differential
that causes the output voltage to decrease by 5% of its
initial value.
Typical Performance Curves
Output Noise Voltage
10
v"
f'--
C,
05
--
-- f---
:
r
10 V
0
-t
) .........
1/
l1'
i
100
CL
I
soo
1k
FREOUENCY - Hz
1
10 k
,'\
[\
20
I\.
10
o
1
10
100
1k
10 k
LOAD FREQUENCY _ Hz
3-8
\
10 iJ.F JANT
10
5 k
30
Cl =01/J.F/
20
50
\
40
C,"O ""\
-
I\.
50
20
5.0
10
\
60
50
10
005
001
70
lOUT"" 1 A
YIN"" 10V
'-
I'--.
Maximum Power Dissipation
100
--
--c--
r01
Output Impedance
100 k
1M
-25
0
25
50
75
100
CASE TEMPERATURE _
0
125
c
150
~A78P05
Typical Performance Curves (Cont.)
Short Circuit Current
.
c
...I
.ill ,.
--
::>
0
...
~
12
::>
0
~
.
."
ili
Dropout Voltage
Quiescent Current
18
.
E
T,
"'-
TJ;
~
25°C
~
3
T,
75°C
J,o c "- ~
~"250C
(
r--
-
TJ
=
loLl-
.....
-~
25° C
lOUT - 5 A
"-1
lOUT - 2 A
2
10
::>
1
0
I
<;
1
0
•o
0
810
20
30
INPUT VOLTAGE -
V
IOUT lo. 5 A -
-
Z
o
~
~ -60
...~
1-+-+--,p1o"\';",,-=-'lS-"A+-+_l'+---t_l
'i-
!li
1--+-+-+-+-+-+-+-+__+_1
0
.
.,
~ -80
-100
o
10
20
15
z
~
80
,d'A ~
t;
201--+-+-r-~-+-r-+-+__+_I
~
151-+-+-t-+-t-1--~-I-__t_l
~
10~~-+-+-+-+-1--+_~__+_I
o
25
5a: 60
~
ii:
lOUT
40
Load Regulation
.
."
~
TJ I -2S"C
TJ~ ~
Z
0
T,
;::
1~
>
E
I
w
lSA ~ ~
l"-V
-150
...
w
~
=
"-
I/"
~
o
10
A
100 k
1M
Hz
IO~' - Jo A
t--
.....
lOUT - 2 A
-50
0
w
~ -100
0
>
12
...::>
e:::> -150
0
0
10 k
- --
I
z
.
".
-04
...
...~::>
1- 10 V
1k
YIN = 10 V
'E
0
Z
VIN
10 V
;::
".:r
...
~::> -200
100
Output Voltage
Deviation vs
Junction Temperature
CL = 0 1 IlF
z
u -02
I
OUTPUT CURRENT -
10
50
YIN
:r
.
w
-250
1
INPUT FREQUENCY -
::>
0
0
I
20
80 100
04
02
."
~
-100
0
~
60
Load Transient Response
.......... ""'-
E
I -50
40
PULSE WIDTH TIME -/,5
INPUT VOLTAGE-V
>
20
150
CL = 01/-lF
~
o
125
°C
V 1N =10V
-100
o
::>
100
I
100
~ -200
l>
75
120
5
::>
50
Ripple Rejection
!I
5
-
lOUT - 10 A
r
~
25
JUNCTION TEMPERATURE -
200
~
>
w
25
V
r-"'T'"--r-,...--.---r-,...-.,.....,.....,---,
~ 100 1-+-+_IlJ~1,_ou_,+'_'_0I-A-+~I~ == 01~ ~F
lOUT 02 A
c
20
15
Line Transient Response
:e
~ -40
10
INPUT VOLTAGE -
Line Regulation
E
I ·20
)
35
0
o
20
40
60
80 100
PULSE WIDTH TIME -1-'5
3-9
-200
-50
-25
25
50
75
100
JUNCTION TEMPERATURE -
125
Q
C
150
•
J,LA78P05
Basic Test Circuit
2
"A78P05
VIN
SOLID
TANTALUM
VOUT
+
+
C IN
11'F
CL
0.1 jLF
3
COMMON
-=Design Considerations
This device has thermal-overload protection from
excessive power and internal short-circuit protection
which limits the circuit's maximum current. Thus, the
devices are protected from overload abnormalities.
Although the internal power dissipation is limited, the
junction temperature must be kept below the maximum
specified temperature (150°C). It is recommended by
the manufacturer that the maximum junction
temperature be kept as low as possible for increased
reliability. To calculate the maximum junction
temperature or heat sink required, the following
thermal resistance values should be used:
Package
TO-3
Typ
Max
8JC
8JC
1.5
1.8
The /LA78P05 is designed to operate without external
compensation components. However, the amount of
external filtering of this voltage regulator depends
upon the circuit layout. If in a specific application the
regulator is more than four inches from the filter
capacitor, a 1 /LF solid tantalum capacitor should be
used at the input. A 0.1 /LF capacitor should be used
at the output to reduce transients created by fast
switching loads, as seen in the basic test circuit.
These filter capacitors must be located as close to
the regulator as possible.
Caution: Permanent damage can result from forcing
the output voltage higher than the input voltage. A
protection diode from output to input should be used if
this condition exists.
TJ(max) - TA
8JC + 8CA
Po (max)
=
8CA
= 8cS
+ 8SA
Solving for TJ:
TJ
= TA + Po (8JC
+ 8CA)
Where:
TJ
TA
Po
8JC
8CA
8cs
8SA
= Junction Temperature
= Ambient Temperature
=
=
=
=
=
Power Dissipation
Junction-to-case thermal resistance
Case-to-ambient thermal resistance
Case-to-heat sink thermal resistance
Heat sink-Io-ambient thermal resistance
3-10
f.lA78H12A
5-Amp Voltage
Regulator
FAIRCHILO
A Schlumberger Company
Hybrid Products
Description
The J,LA78H12A is a hybrid regulator with 12.0 V
fixed output and 5.0 A output capability. It has the
inherent characteristics of the monolithic 3-terminal
regulators; i.e., full thermal overload, short-circuit and
safe-area protection. All devices are packaged in
hermetically sealed TO-3s providing 50 W power
dissipation. If the safe operating area is exceeded,
the device shuts down, rather than failing or damaging
other system components (Note 1). This feature
eliminates costly output circuitry and overly
conservative heat sinks typical of high-current
regulators built from discrete components.
•
•
•
•
•
•
Connection Diagram
TO-3 Metal Package
•
5.0 A OUTPUT CURRENT
INTERNAL CURRENT AND THERMAL OVERLOAD
PROTECTION
INTERNAL SHORT CIRCUIT PROTECTION
LOW DROPOUT VOLTAGE (TYPICALLY 2.3 V @
5.0 A)
50 W POWER DISSIPATION
STEEL TO-3 PACKAGE
COMMON
OtlTPUT 2
(Top View)
Order Information
Type
Package
J,LA78H12A
Metal
J,LA78H12A
Metal
Note
1. ThIs voltage regulator offers output transIstor safe· area
protecllon However. to maintain full protecllon. the devIce
must be operated wIthin the maximum input·to·output voltage
differentIal ratings, as listed on thIs data sheet under "Absolute
MaxImum Ratings." For applicatIons violatIng these limits,
devIce WIll not be fully protected.
Part No.
J,LA78H12ASC
J,LA78H12ASM
Code
GN
GN
Block Diagram
I
I
START
CIRCUIT
I
VOLTAGE
REGULATOR
V,N
T
CURRENT SOURCE
a
I
-:::L
/'"
r-
THERMAL
SHUTDOWN
1
R
......
......
V
1
SHORT
CIRCUIT
PROTECTION
K
r-....
Rsc
IJ
2
VOUT
3
COMMON
3·11
~A78H12A
Absolute Maximum Ratings
Input Voltage
Input-to-Output Voltage
Differential, Output ShortCircuited
Internal Power Dissipation
Operating Junction
Temperature
Military Temperature Range
40 V
Commercial Temperature
Range
35 V
50 W @ 25°C Case
Storage Temperature Range
Pin Temperature
(Soldering, 60 s)
~A78H12ASC
O°C to +150°C
-55°C to +150°C
~A78H12ASM
~A7812A
TJ = 25°C, VIN = 19 V, lOUT = 2.0 A unless otherwise specified
Electrical Characteristics
Limits
Symbol
Characteristic
Condition
Min
11.5
VOUT
Output Voltage
lOUT = 2.0 A
AVOUT
Line Regulation (Note 2)
VIN = 16 to 25 V
AVOUT
Load Regulation (Note 2)
10 mA
10
Quiescent Current
lOUT = 0, VIN = 17 V
RR
Ripple Rejection
lOUT = 1.0 A, f = 120 Hz, 5.0 Vpk-pk 60
Vn
Output Noise
10 Hz
Voo
Dropout Voltage (Note 3)
lOS
Short-Circuit Current Limit
~
~
lOUT
f
~
~
5.0 A
Typ
Max
Unit
V
12
12.5
20
120
mV
20
120
mV
3.7
10
mA
dB
100 kHz, VIN = 17V
75
VRMS
lOUT = 5.0 A
2.3
2.5
V
lOUT = 3.0 A
2.0
2.3
V
7.0
12.0
Apk
Notes
2. Load and line regulation are specified at constant Junction
temperature. Pulse testing is required with a pulse width
oS 1 ms and a duty cycle oS 5%. Full Kelvin connection
methods must be used to measure these parameters.
3. Dropout Voltage ,s the IOpuHo·output voltage d,fferent,al
that causes the output voltage to decrease by 5% of ,ts
IO,t,al value.
Typical Performance Curves
Output Impedance
1.0
IOUT=1A
YIN = lilY
50
0.'
t..
C L :=: 0 __
/
. / CL
CL
i
10
100
1k
'I"-
50
r-
0.1
0
III 0.05
J1'
=0.1.F/
~
,
g
.........
~
0
10 p.F rANT.
1.0
1
60
VIN = 19V
CL = 0
I
~
)
1.0
Maximum Power Dissipation
Output Noise Voltage
100
10k
LOAD FREQUENCY - Hz
lOOk
1M
0.01
10
50 100
500
1k
FREQUENCY - Hz
3-12
5 k 10 k
0
_25
0
25
""""[\1,\
50
75
100
CASE TEMPERATURE - ·C
125
150
j.tA78H12A
Typical Performance Curves (Cont.)
Quiescent Current
Short Circuit Current
.
.
...
.ffi..
,
I
TJ •
4
.-
3
:>
...
"
~
u
".ili
0
•1.
t--TJ
to-....
t:;:; ~
20
1
::e
=
2A
/
10
..
15
lour=5A
, -1·~---+----+--444~~-r----1
~
~ 100
,
50
w
~ -so•
h lour=5A
II
I"
U
~
>-a~---+----4-~~~---+--~
l!i
25
!:;
>
1-.. ~+----+--++-+----+-----I
w
-30
-M.L----~--~1.--~-,L5----~~---J~
,
IOUT
II
1
•
-~
25
lL
z
~
1
60
80 100
Load Transient Response
,.200
'd3A G
..
2.
0_100
1
1.
~
100
1k
10 k
100 k
1M
INPUT FREQUENCY - Hz
Output Voltage
Deviation vs
Junction Temperature
VIN - 19V
I
!:;
~ -200
,
P".
.
o
OUTPUT CURRENT - A
"V
1 l"-
IOUTLSA
I\,
w
i
150
VIN = ltV
CL = O.llJ.f
VIN - 19V
C L = 01IJ.F
100
125
~
so
.
40
100
IOUT~lA
~ so
~
20
75
1
100
,
!g
PULSE WIDTH nMe - itS
,
50
Ripple Rejection
0
o
F-"
IOUT-2A
120
20
INPUT VOLTAGE - V
Load Regulation
T- 3 A r--
I
i3
.!i1 •
i •
Q
'OUT-SA
VIN = 10V
CL = O.lIJ.F
~-100
~---+----+--444----+----1
i!!
g
-
~
JUNCTION TEMPERATURE _ °C
13
l'j
,
"
Line Transient Response
rr1==:±==:1
>
INPUT VOLTAGE - V
Y
Line Regulation
lOUT
~J.m.c
TJ :: 25°C
./
4.
30
....
2
TJ = 25°C
INPUT VOLTAGE -
J...c " ~
If
u
:;
Dropout Voltage
5
12
20
40
eo
80 100
PULSE WIDTH TIME - /oiA
3·13
-200-so
-25
25
'OUT-2A
T-SA
50
75
...;;;;::
100
JUNCTION TEMPERATURE _ °C
125
150
•
JLA78H12A
Basic Test Circuit
1
2
MA78H12A
SOLID
TANTALUM
VOUT
r
+
+
CIN
1 /LF
3
0.1 IJ-F
.1
COMMON
Design Considerations
This device has thermal-overload protection from
excessive power and internal short-circuit protection
which limits the circuit's maximum current. Thus, the
device is protected from overload abnormalities.
Although the internal power dissipation is limited, the
junction temperature must be kept below the maximum
specified temperature (150°C). It is recommended by
the manufacturer that the maximum junction
temperature be kept as low as possible for increased
reliability. To calculate the maximum junction
temperature or heat sink required, the following
thermal resistance values should be used:
Package
TO-3
Po (max) =
0CA
Typ
Max
°JC
°JC
1.8
2.5
The devices are designed to operate without external
compensation components. However, the amount of
external filtering of these voltage regulators depends
upon the circuit layout. If in a specific application the
regulator is more than four inches from the filter
capacitor, a 1 J.tF solid tantalum capacitor should be
used at the input. A 0.1 J.tF capacitor should be used
at the output to reduce transients created by fast
switching loads, as seen in the basic test circuit.
These filter capacitors must be located as close to
the regulator as possible.
Caution: Permanent damage can result from forcing
the output voltage higher than the input voltage. A
protection diode from output to input should be used if
this condition exists.
TJ(max) - TA
0JC + 0CA
= OCS + 0SA
Solving for TJ:
TJ =TA+PO(OJC+OJA)
Where:
T J = Junction Temperature
T A = Ambient Temperature
Po = Power Dissipation
0JC = Junction-to-case thermal resistance
0CA = Case-to-ambient thermal resistance
0CS = Case-to-heat sink thermal resistance
0SA = Heat sink-to-ambient thermal resistance
3-14
J.1A78HGA
Positive Adjustable
5-Amp Voltage Regulator
FAIRCHILO
A Schlumberger Company
Hybrid Products
Description
The IlA78HGA is an adjustable 4-terminal positive
voltage regulator capable of supplying in excess
of 5.0 A over a 5.0 V to 24 V output range. Only
two external resistors are required to set the
output voltage.
Connection Diagram
TO-3 Metal Package
The IlA78HGA is packaged in a hermetically sealed
TO-3, providing 50 W power dissipation. The regulator
consists of a monolithic chip driving a discrete seriespass element. A beryllium-oxide substrate is used in
conjunction with an isothermal layout to optimize the
thermal characteristics of each device and still
maintain electrical isolation between the various
chips. This unique circuit design limits the maximum
junction temperature of the power output transistor to
provide full automatic thermal overload protection. If
the safe operating area is ever exceeded (Note 1),
the device simply shuts down rather than failing or
damaging other system components. This feature
eliminates the need to design costly regulators built
from discrete components.
•
OUTPUT 2
(Top View)
•
•
•
•
•
•
•
•
5.0 A OUTPUT CURRENT
INTERNAL CURRENT AND THERMAL LIMITING
INTERNAL SHORT CIRCUIT CURRENT LIMIT
LOW DROPOUT VOLTAGE (TYPICALLY 2.3 V @
5.0 A)
50 W POWER DISSIPATION
ELECTRICALLY NEUTRAL CASE
STEEL TO-3 PACKAGE
ALL PIN-FOR-PIN COMPATIBLE WITH IlA78HG
Order Information
Type
Package
IlA78HGA
Metal
IlA78HGA
Metal
Code
JA
JA
Part No.
IlA78HGASC
IlA78HGASM
Block Diagram-Positive Adjustable Voltage Regulator
T
I
I
START
CIRCUIT
CURRENT SOURCE
VOLTAGE
REGULATOR
I
-tL
V
.----
V'N
THERMAL
SHUTDOWN
1
R
"- "&.
1
SHORT
CIRCUIT
PROTECTION
r-K
r-....
R~~
2
VOUT
3
CONTROL
4
COMMON
Notes on following pages
3·15
I-LA78HGA
Absolute Maximum Ratings
Input Voltage
Internal Power Dissipation
Maximum Input-to-Output
Voltage
Differential Output Short
Circuit
Operating Junction
Temperature
Military Temperature Range
I-IA78HGASM
Electrical Characteristics
40 V
50 W @ 25°C Case
Commercial Temperature
Range
I-IA78HGASC
Storage Temperature Range
Pin Temperature
(Soldering, 60 s)
35 V
O°C to +150°C
-55°C to +150°C
TJ = 25°C, VIN = 10 V, lOUT = 2.0 A unless otherwise specified
Limits
Symbol
Characteristic
Condition (Note 3)
Min
VOUT
Output Voltage (Note 4)
lOUT = 2.0 A, VIN = VOUT + 3.5 V
5.0
Typ
~VOUT
Line Regulation (Note 2)
VIN = 7.5 to 25 V
~VOUT
Load Regulation (Note 2)
10 mA :S lOUT :S 5.0 A
IQ
Quiescent Current
lOUT = 0
RR
Ripple Rejection
lOUT = 1.0 A, f = 210 Hz, 5.0 Vpk.pk 60
Vn
Output Noise
10 Hz :S f :S 100 kHz,
VIN = VOUT + 5.0 V
50
VDD
Dropout Voltage (Note 5)
lOUT = 5.0 A
2.3
2.5
V
lOUT = 3.0 A
2.0
2.3
V
los
Short-Circuit Current Limit
VIN = 15 V
7.0
12.0
Apk
Vc
Control Pin Voltage
5.0
5.25
V
Unit
24
V
0.2%
1%
V
0.2%
1%
V
3.4
10
mA
dB
4.85
Notes
1. This voltage regulator offers output transistor safe·area
protection. However, to maintain full protectIon, the device
must be operated within the maximum input·to·output voltage
differential rating listed on the data sheet under" Absolute
Maximum Ratings." For applications violating these limits,
device will not be fully protected.
2. Load and line regulation are specified at constant iunction
temperature. Pulse testing IS required with a pulse width
::s 1 ms and a duty cycle ::s 5%. Full Kelvin connection
methods must be used to measure these parameters.
Max
,uVRMS
3. The performance characteristIcs of the adjustable series
(I'A78HGA) is specified for VOUT = 5.0 V, unless
otherwise noted.
Rl + R2
4. VOUT is defmed as VOUT = --R-2- (VCONT) where Rl
and R2 are defined in the Basic Test Circuit diagram.
5. Dropout Voltage is the input·output voltage differential that
causes the output voltage to decrease by 5% of its
mitial value.
Typical Performance Curves
Output Impedance
Output Noise Voltage
100
10
IOUT-1A
VOUT '" 5 V
10 V
V"
50
~,
Maximum Power Dissipation
V 1N
=10V
VOUT = 5 V
CL - 0
0.5
60
50
40
20
"
CL "" 0--.
10
)r-.,.
50
Tl'
/
CL - 0 1
2.0
CL
1 JLFI
'0
100
1k
10 k
LOAD FREQUENCY - Hz
30
20
fLF..i
""1\1'\
10
ANT
1.0
10
r--
100 k
1M
001
10
so
100
500
1k
FREQUENCY - Hz
3·16
5 k 10 k
~
W
75
1\
1'\
100
CASE TEMPERATURE -
~C
1~
1~
,uA78HGA
Typical Performance Curves (Cont.)
Short Circuit Current
Dropout Voltage
Quiescent Current
10
Your;o SV
,
>
c
,
ffi
c
4~--+--+---t-~~~_1
~
3
,
E
r-.....
""u::>
"'-..
"'-..
t:
::>
TJ ""
u
~TJ-25°C
75°~"
"
"
f".,.,
~
~
o
o
8 10
20
"B
"
"'-..
30
TJ = 2SO C
~
2r--~-~--1--_t-~
Io
1~-f+--+---t--+-_1
10
35
~25
..
'5
7&
::=po
100
125
150
Ripple Rejection
120
Irv
~uT=5A
~
iii
= Zit.
JUNCTION TEMPERATURE - ·C
Line Transient Response
IOUT-2A
>
25
louT= 3 It. lour
INPUT VOLTAGE - V
INPUT VOLTAGE _ V
Line Regulation
20
15
I
II
iour=5A
_10 r---t--ti--1--_t--+----1
i
!rlour = 3A
~
r-- ~~OUT
-20 r---t--ti--1--_t---+----1
w
VIN = 10 V
YOUT = 5 V
CL = 0.1 J!lF
lOU! = SAl-
k'},
= 1A
§ 80
V
~
"
i"
§5
-40
20
40
80
80
PULSE WIDTH nMe -
INPUT VOLTAGE - V
100
~8
200
'Dur
40
1
10
lsA ~ ~
I
100
1k
l"-V
10 k
YIN = 10 V
~-10~--+~~~--t--+-~
z
!-20~--+--+--_t~~~~~
W
"~-30~--+--+---t--+~~
I~L
W
~
1M
Output Voltage
Deviation vs
Junction Temperature
..
YIN = 10 V
, 100 ~-+--+-f-+--+_t--ft-VOUT = 5V
>
100 k
INPUT FREQUENCY - Hz
Load Transient Response
~
CL =Olj.!F_
'ada ~
..
20
VOUT",SV
~
~
~ -30 r---t--ti--1--_t--+----1
~
Load Regulation
YIN = 10 Y
I
100
,OUT
= 01 j,LF
"-100 r-+-+--Itl /'-t~-I--+--1-+-l
5
5 V
I~UT.::12A
....
e-200~+--+-+~f-+-+-+-4-~
g
I
I
r=5A
F=
c
g
...::>
§
-40
-500~--~-~--~--~-~
OUTPUT CURRENT - A
-200
o
20
40
60
80 100
PULSE WIDTH nMe - }'s
3-17
-50 -25
25
50
75
100
JUNCTION TEMPERATURE _ °C
125
150
J.LA78HGA
Test Circuit
Adjustable Output Voltage
2
vour
1
C 1N =
2~F 1
SOLID
TANTA LUM
~A78HGA
+
R1
CONTROL
+
3
~
CL" 1.0
':
~
F
4
R2
COMMO N
Design Considerations
This device has thermal-overload protection from
excessive power and internal short-circuit protection
which limits the circuit's maximum current. Thus, the
device is protected from overload abnormalities.
Although the internal power dissipation is limited, the
junction temperature must be kept below the maximum
specified temperature (150°C). It is recommended by
the manufacturer that the maximum junction
temperature be kept as low as possible for increased
reliability. To calculate the maximum junction
temperature or heat sink required, the following
thermal resistance values should be used:
This device is designed to operate without external
compensation components. However, the amount of
external filtering of this voltage regulator depends
upon the circuit layout. If in a specific application the
regulator is more than four inches from the filter
capacitor, a 1 iLF solid tantalum capacitor should be
used at the input. A 0.1 iLF capacitor should be used
at the output to reduce transients created by fast
switching loads, as seen in the basic test circuit.
These filter capacitors must be located as close to
the regulator as possible.
Caution: Permanent damage can result from forcing
the output voltage higher than the input voltage. A
protection diode from output to input should be used if
this condition exists.
Typ
Package
OJC
TO-3
1.8
2.5
Voltage Output
The device has an adjustable output voltage from
5.0 V to 24 V which can be programmed by the
external resistor network (potentiometer or two fixed
resistors) using the relationship
TJ(max) - TA
OJC + 0CA
PD(MAX)
=
OCA
= OCS
+ OSA
VOUT
Solving for TJ:
TJ = TA + PD (OJC
= VCONTROL
+ R2)
( R1 R2
Example: If R 1 = 0 fl and R2 = 5 kfl, then
VOUT
5 V nominal.
Or, if R 1 = 10 kfl and R2 = 5 kfl, then
VOUT = 15 V.
+ 0CA)
=
Where:
TJ
= Junction Temperature
TA
Ambient Temperature
Po
= Power Dissipation
OJC
= Junction-to-case thermal resistance
OCA
= Case-to-ambient thermal resistance
OSA
= Heat sink-to-ambient thermal resistance
OCS
= Case-to-heat sink thermal resistance
=
3-18
JLA79HG
5 A Negative Adjustable
Voltage Regulator
FAIRCHILD
A Schlumberger Company
Hybrid Products
Connection Diagram
4-Pin Metal Package
Description
The !LA79HG is an adjustable 4-terminal negative
voltage regulator capable of supplying in excess of
-5 A over a -24 V to -2.11 V output range. The
!LA 79HG hybrid voltage regulator has been designed
with all the inherent characteristics of the monolithic
4-terminal regulator; i.e., full thermal overload and
short circuit protection. The !LA79HG is packaged in a
hermetically-sealed 4-pin TO-3 package providing
50 W power dissipation. The regulator consists of a
monolithic chip driving a discrete-series pass element
and short circuit detection transistors.
•
-5_0 A OUTPUT CURRENT
INTERNAL CURRENT AND THERMAL OVERLOAD
PROTECTION
• INTERNAL SHORT CIRCUIT CURRENT LIMIT
• LOW DROP-OUT VOLTAGE (TYPICALLY 2_2 V
@5_0A)
• 50 W POWER DISSIPATION
• ELECTRICALLY NEUTRAL CASE
• STEEL TO-3 CASE
•
•
(Top View)
Order Information
Type
Package
!LA79HG
Metal
!LA79HG
Metal
Part No_
!LA79HGSC
!LA79HGSM
Code
JA
JA
Block Diagram
4
I
1
START-UP
CIRCUIT
-
< SHO RTCIRCUIT
SENS E RESISTOR
CURRENT
SOURCE
THERMAL
SHUTDOWN-
J
I
VOLTAGE
REFERENCE
,---
-v UNREGULATED
r--
SHORT
CIRCUIT
LIMIT
f-
1' . . . . . .
......................
~
7'
1'- . . . . . .
................
OUTP UT
SISTOR
ITRA:
OUTPUT
2
1
3-19
CONTROL
COMMON
p,A79HG
Absolute Maximum Ratings
Input Voltage
Internal Power Dissipation
Maximum Input-to-Output
Voltage Differential
Operating Junction
Temperature Range
/LA79HG
Electrical Characteristics
-40 V
50 W @ 25°C Case
Storage Temperature Range
Pin Temperature
(Soldering, 60 s)
-55°C to + 150°C
300°C
-35 V
O°C to +150°C
TJ = 25°C, VIN = -10 V and lOUT = -2.0 A unless otherwise specified.
Limits
Characteristic
Min
Input Voltage Range
-40
Nominal Output Voltage Range
-24
Typ
Output Voltage Tolerance
Max
Unit
-7.0
V
Condition
-2.11
4
V
VIN = VOUT -5 V
%(VOUT) -40 V :S VIN :S -7 V
Line Regulation
0.4
1.0
%(VOUT) -40 V :S VIN :S -7 V
Load Regulation
0.7
1.0
%(VOUT)
Control Pin Current
3.0
Quiescent Current
-5.0
/LA
mA
Ripple Rejection
50
dB
Output Noise Voltage
200
/LV
Dropout Voltage
2.2
-8
Short Circuit Current Limit
Control Pin Voltage
(Reference)
-2.35
VIN = VOUT -10 V,
-10 mA :S lOUT :S -5.0 A
VIN = -10 V
-18 V:S VIN:S -8.5 V
VOUT = -5 V, f = 120 Hz
10 Hz :S f :S 100 kHz,
VOUT = -5.0 V
V
lOUT = -5 A
-12
A
VIN=-15V
-2.11
V
VIN=-10V
Typical Performance Curves
Short Circuit Current
-10
60
2~C
50
-8
"\
1\
1\
l\
75°C
40
-6
30
-4
20
-2
10
o
o
-5
-10
-15
Dropout Voltage
Quiescent Current
-20
-25
-30
-35
0
_25
lOUT'" -SA
lOUT"" -2A
1,\
0
25
50
75
100
125
150
oL--L__L--L~L-~~L-~
-25
0
25
50
75
100
125
JUNCTION TEMPERATURE _ "C
INPUT VOLTAGE - V
CASE TEMPERATURE _ °C
3·20
150
J.!A79HG
Typical Performance Curves (Cont.)
Line Transient Response
~
Load Regulation
f-+-+----1I-+_+-+YOUT = -50 V
20
lour::: -30A
10f-+-+----11-+_+____1--+-+_+~
w
Load Transient Response
~ 0f-+-+--.11-+-+---i--.....+-+--1
~-101-+-+----1~+_-t--1--f-+_+__1
[
8-~f-+-+----11-+_+____1--+-+_+~
>
~-10~~-+--11-+-+----1--~+-+~
~
!:;
g-20f-+-+----1I-+_+----1--+-+_+~
i
~
' - 25°C
'-7SOC
1- 10
~
-" \.
125"C
fi
>-20
~
w
"~-30
g
!-40
-so
1
o
-2
-1
PULSE WIDTH TIME - ~s
-,
_3
Output Voltage Deviation vs
Junction Temperature
PULSE WIDTH TIllE - Id
Control Current
vs Temperature
Differential Control Voltage
vs Input Voltage
07
YIN
~
Ii
.
= -40V
~
_SA
w -so
j$
"g
06
-20
f--+--+-I-+--+----i--+__1
§
~
"
5
rr
0
t\
0'
B
VIN
JUNCTION TEMPERATURE -
"c
o
25
so
75
rr
rr
"
-.
~
0
ffi
.- ~
25°C
-2
~
~
~
75°C
~
_1
o
-5
-10 -15
-20
125
JUNCTION TEMPERATURE _ ·C
:;
"
100
_25 -30 -35 -40
INPUT VOLTAGE - V
3·21
-8.0
-10
1'r--.
-S
~
<2
'f'i'f~
Maximum Power Dissipation
. -,
~
1'1"-
= 10V
= -S.OY
Your
o
r--.. r-.....
~_60
1'1'
!i 02
I.......
TJ = 25"C .....
E
1'1'
D.'
0.1
-200 L---L_L----L_.L.---L_..L-'_
25
50
75
100 125 150
-25
!iw
r--.
>-4.0
rr
~-1~f__+--+--f-_+--+-____1--+~
E
r--- t---
E OS
-2A
•
• •
-S
OUTPUT CURRENT _ A
150
"
louT = -2A
VOUT = _5.OY
-12
-50
-10
-15
-20
-25
INPUT VOLTAGE - V
-30
,uA79HG
Basic Test Circuit, Adjustable Output Voltage
3
VOUT
4
/LA79HG
CONTROL
C IN ; 2/L F
SOLID
TANTALUM
Rl
+
+
2
~!::: CL'" 1.O/L F
~
1
R2
COMM ON
(Rl
+ R2)
VOUT ~ VCONT'--R-2-
Design Considerations
This device has thermal overload protection from
excessive power and internal short circuit protection
which limits the circuit's maximum current. Thus, the
device is protected from overload abnormalities.
Although the internal power dissipation is limited, the
junction temperature must be kept below the maximum
specified temperature (150°C). It is recommended by
the manufacturer that the maximum junction
temperature be kept as low as possible for increased
reliability. To calculate the maximum junction
temperature or heat sink required, the following
thermal resistance values should be used.
Package
TO-3
Typ
Max
IiJC
IiJC
2.5
1.8
PO(MAX)
=
IiCA = lics
switching loads, as seen in the basic test circuit.
These filter capacitors must be located as close to
the regulator as possible.
Caution: Permanent damage can result from forcing
the output voltage higher than the input voltage. A
protection diode from output to input should be used if
this condition exists.
Voltage Output
The device has an adjustable output voltage from
-2.11 to -24 V which can be programmed by the
external resistor network (potentiometer or two fixed
resistors) using the relationship:
VOUT = VCONTROL
+ R2)
R2
Example: If R 1 = 0 Q and R2 = 5 kQ, then
VOUT = -2.11 V nominal.
Or, if R1 = 12.8 kQ and R2 = 2.1 kQ then
VOUT = -15 V.
TJ(MAX) - TA
IiJC + IiCA
+ liSA
Solving for T J:
TJ = TA + Po (IiJC
( R1
+ IiCA)
Where:
T J = Junction Temperature
TA
Ambient Temperature
Po
Power Dissipation
8JC = Junction-to-case thermal resistance
IiCA = Case-to-ambient thermal resistance
IiCS = Case-to-heat sink thermal resistance
liSA = Heat sink-to-ambient thermal resistance
=
=
The device is designed to operate without external
compensation components. However, the amount of
external filtering of these voltage regulators depends
upon the circuit layout. If in a specific application the
regulator is more than four inches from the filter
capacitor, a 2 JtF solid tantalum capacitor should be
used at the input. A 1 JtF capacitor should be used at
the output to reduce transients created by fast
3-22
1
SH323 • SH223 • SH 123
5 A, 3 V
Voltage Regulator
FAIRCHILD
A Schlumberger Company
Hybrid Products
Description
The SH232 is a hybrid regulator with 5.0 V fixed output
and 3.0 A output capability. It has the inherent
characteristics of the monolithic 3-terminal regulators,
i.e., full thermal overload, short circuit and safe area
protection. All devices are packaged in hermetically
sealed TO-3s providing 50 W power dissipation. If the
safe operating area is exceeded, the device shuts
down rather than failing or damaging other system
components (Note 1). This feature eliminates costly
output circuitry and overly conservative heat sinks
typical of high-current regulators built from
discrete components.
Connection Diagram
2-Pin Metal Package
•
•
•
3.0 A OUTPUT CURRENT
INTERNAL CURRENT AND THERMAL
OVERLOAD PROTECTION
• INTERNAL SHORT CIRCUIT PROTECTION
• LOW DROPOUT VOLTAGE (TYPICALLY 2.0 V
@3.0A)
• 50 W POWER DISSIPATION
• STEEL TO-3 PACKAGE
• ALL PIN-FOR-PIN COMPATIBLE WITH THE
LM323, SG323
(Top View)
Order Information
Type
Package
SH323
Metal
SH223
Metal
SH123
Metal
Code
GN
GN
GN
Part No.
SH323SC
SH223SV
SH123SM
Block Diagram
I
I
START
CIRCUIT
I
CURRENT SOURCE
VOLTAGE
REGULATOR
I
~d..
r-
~
VIN
THERMAL
SHUTDOWN
~,
1
1
SHORT
CIRCUIT
PROTECTION
R
.....
~
.....
Rsc
1
2
Vour
3
COMMON
3·23
SH323 • SH223 • SH 123
Absolute Maximum Ratings
Input Voltage
Input-to-Output Voltage
Differential
Output Short Circuited
Internal Power Dissipation
Operating Junction Temperature
Industrial Temperature Range
SH223SV
Military Temperature Range
SH123SM
Commercial Temperature Range
SH323SC
Storage Temperature Range
Pin Temperature
(Soldering, 60 s)
40 V
35 V
50 W @ 25°C Case
150°C
O°C to +150°C
-55°C to +150°C
TJ = 25°C, VIN = 10 V, lOUT = 2.0 A unless otherwise specified.
Electrical Characteristics
Limits
Symbol
Characteristic
Min
Typ
Max
Unit
Condition
VOUT
Output Voltage
4.85
5.0
5.25
~VOUT
Line Regulation (Note 2)
25
lOUT = 2.0 A
VIN = 7.5 to 25 V
~VOUT
Load Regulation (Note 2)
10
Quiescent Current
Ripple Rejection
10
10
3.0
V
mV
50
10
mV
rnA
2.3
12.0
jLVRMS 10 Hz :$ f :$ 100 kHz, VIN = 10 V
V
lOUT = 3 A
VIN = 10 V
Apk
RR
dB
60
40
Output Noise
Dropout Voltage (Note 3)
Short Circuit Current Limit
Vn
Voo
los
2.0
7.0
Notes
1. ThIs voltage regulator offers output transistor safe area
protectIon. However, to maIntaIn full protectIon. the device
must be operated within the maxImum Input-to-output voltage
differentIal ratmgs, as hsted on thIs data sheet under" Absolute
MaxImum Ratmgs." For applicatIons vlolatmg these 10m ItS,
devIce will not be fully protected
2. Load and hne regulatIon are specIfIed at constant JunctIon
10 rnA :$ lOUT :$ 3.0 A
lOUT = 0
lOUT = 1.0 A, f = 120 Hz, 5.0 Vpk-pk
temperature Pulse testmg IS required wIth a pulse wIdth
::s 1 ms and a duty cycle ::s 5% Full Kelvin connection
methods must be used to measure these parameters
3. Dropout Voltage IS the mput·output voltage dIfferential that
causes the output voltage to decrease by 5% of ItS
mltial value
Typical Performance Curves
.
Short Circuit Current
Dropout Voltage
MaxImum Power Dissipation
I.
>
I
I-
50
"'-
I--...
'-...
TJ
1\
""""TJ = 25"C
= 7SOC,""
.........
.....,
I"""1""'-.
••
810
20
INPUT VOLTAGE _ Y
30
'\
35
I.
•
_25
0
25
50
'\
75
CASE TEMPERATURE _ ·C
3-24
~
'\
100
IOUT=2A
-
F-
1
!!
1\
125
I
i•
~loL.l
150
_25
0
25
50
75
100
125
JUNCTION TEMPERATURE - ·C
150
SH323 • SH223 • SH 123
Typical Performance Curves (ConI.)
Line Regulation
>
E
IOUT=2A
>
w
E -10
120
50
V
>-
"e: -50
5
~
w
>
-30
I
0
I
"'"
"
"
%
0
10
15
20
~
IOUT'=3A
l\.
'"
a:
10
40
o
25
...........
>
r--.....
60
80
I
J
> 100
w
1
10
TJ -l25°C-f---/
TJ = 2SOC ---"
tOOk
1M
so
VIN=10V
~
~
~ -so
e:-l00
5
~
'"
Ii?
10k
VOUT vs Junction Temperature
/'
~ -50
-30
lk
I\"
%
/
100
INPUT FREQUENCY - Hz
Cl=Ol~F
50
~
r-- ~
~
20
100
VIN = toV
E
VIN-lOV
____
~25OC
-10
i'lw
40
Load Transient Response
~
~
:;: -20
20
PULSE WIDTH TIME _ P.s
Load Regulation
~ -100
~-40
-
IOUT=2A
r-
5
~ _150
5
o
-so
o
o
OUTPUT CURRENT - A
20
40
60
-200
80 100
-so
10
IOUT=1A
VIN = tOv
so
05
~
"t'-
v"
C,
I
TJ
,.
If
~
C L = 0 """'\
""
I
W
10
"
!
)
50
> 005
n'
/
"0
~
........
./C,=OI.F/
20
CL
""
1
10
100
1k
t-
~
1
)
10 p.F TANT
I
10
01
10 k
LOAD FREQUENCY - Hz
I
100 k
1M
001
10
so
00
100
500
1k
FREQUENCY - Hz
3-25
75
100
125
150
Quiescent Current
10 V
0
~
20
50
JUNCTION TEMPERATURE _ °C
Output Noise Voltage
100
25
-25
PULSE WIDTH TIME - ILS
Output Impedance
~
..
!!,
INPUT VOLTAGE _ V
'~"
~
OJ
a:
20
i!O
0
Q
eo
~
-so
1j
z
Z
0
Z
0
~
~
w
>
>~ -40
"~
100
I'u
%
~
VIN = tOV
CL=OlILF
,..
I
Z
;;: -20
~
VIN = 10 V
CL = 01 ~F
r')I OUT =3A
25
"
o'" -25
I
Z
0
"~
Ripple Rejection
Line Transient Response
5 k 10 k
~
J5'C "-
,&
~
~
~~125'C
TJ=25°C
I
10
15
INPUT VOLTAGE - V
20
25
•
SH323 • SH223 • SH 123
Test Circuit
Fixed Output Voltage
1
2
SH323
SOLID
TANTALUM
VOUT
*
+
+
CIN
1 /LF
3
-L
Design Considerations
Caution: Permanent damage can result from forcing
the output voltage higher than the input voltage. A
protection diode from output to input should be used if
this condition exists.
Max
BJC
TO-3
PO(MAX)
BCA
1.8
=
= OCS
2.5
TJ(MAX) - TA
BJC
BCA
+
+ OSA
Solving for TJ:
TJ = TA + Po (OJC
COMMON
The device is designed to operated without external
compensation components. However, the amount of
external filtering of this voltage regulator depends
upon the circuit layout. If in a specific application the
regulator is more than four inches from the filter
capacitor, a 1 ILF solid tantalum capacitor should be
used at the input. A 0.1 ILF capacitor should be used
at the output to reduce transients created by fast
switching loads, as seen in the basic test circuit.
These filter capacitors must be located as close to
the regulator as possible.
This device has thermal overload protection from
excessive power and internal short circuit protection
which limits the circuit's maximum current. Thus, the
device is protected from overload abnormalities.
Although the internal power dissipation is limited, the
junction temperature must be kept below the maximum
specified temperature (150°C). It is recommended by
the manufacturer that the maximum junction
temperature be kept as low as possible for increased
reliability. To calculate the maximum junction
temperature or heat sink required, the following
thermal resistance values should be used.
Package
CL F
0.1
/-L
+ 0CA)
Where:
Junction Temperature
TJ
Ambient Temperature
TA
Power Dissipation
Po
Junction-to-case thermal resistance
OJC
Case-Io-ambient thermal resislance
OCA
Case-to-heat sink thermal resistance
OCS
Heat sink-to-ambient thermal resistance
OSA
3-26
SH1605
5 A Efficient
Switching Regulator
FAIRCHIL.O
A Schlumberger Company
Hybrid Products
Description
The SH1605 is a hybrid switching regulator with high
output current capabilities. It incorporates a
temperature-compensated voltage reference, a dutycycle controllable oscillator, error amplifier, high
current-high voltage output switch, and a power diode.
The SH 1605 can supply 5 A of regulated output
current over a wide range of output voltage.
•
•
•
•
•
Connection Diagram
S-Pin TO-3 Type
ERROR
AMPLIFIER
INPUT
STEP DOWN SWITCHING REGULATOR
OUTPUT ADJUSTABLE FROM 3_0 TO 30 V
5 A OUTPUT CURRENT
HIGH EFFICIENCY
UP TO 150 W OUTPUT POWER
Absolute Maximum Ratings
VIN - VOUT(mm)
Input Voltage
Output Current
Operating Temperature T J
Internal Power Dissipation
Storage Temperature Range
Duty Cycle
V 7 -8
17 -8
•
VOUT
STEERING
DIODE (ANODE)
TA = 25°C unless
otherwise specified
5V
35 V Max
6A
150°C
20W
-65°C to +150°C
20 :s D :s 80%
60 V
6A
Case
= Ground
Order Information
Type
SH1605
Package
Metal
Code
8G
Block Diagram
1----------------------,
I
I
7
~._~------~CASE
I
I
I
I
I
L ______________________
3-27
I
~
Part No_
SH1605S
SH1605
Electrical Characteristics
Tc = 25°C, VIN = 15 V unless otherwise specified.
SH1605
Symbol
Characteristics
Conditions
VOUT
Output Voltage
VIN 2: Va
Vs
Switch Saturation
lOUT
lOUT
VF
Diode On Voltage
Vcc
Supply Voltage
IRO
Diode Reverse Current
10
Quiescent Current
Min
+ 5 V, 10 = 2 A
Typ
Max
Units
30.0
V
1.5
1.0
2.0
1.2
V
V
2.2
1.6
2.8
2.0
V
V
3.0
= 5.0 A,
= 2.0 A
lOUT = 5.0 A,
lOUT = 2.0 A
10
= 25 V
lOUT = 0.2 A
VRO
35
V
2.0
IJ-A
30
mA
Reference and Oscillator Section
V3
Voltage on Pin 3
2.5
V
6V3/T
V3 Temperature Coefficient
150
ppm/oC
14
Charging Current-Pin 4
25
IJ-A
V4
Voltage Swing-Pin 4
0.5
V
114
Discharging Current-Pin 4
225
IJ-A
Switching Characteristics
Symbol
Characteristics
Conditions
tr
Voltage Rise Time
tj
Voltage Fall Time
lOUT
lOUT
ts
Storage Time
td
Delay Time
Min
Typ
Max
Units
lOUT = 2.0 A
lOUT = 5.0 A
700
1.8
ns
IJ-s
= 2.0 A
= 5.0 A
lOUT = 5.0 A
lOUT = 5.0 A
700
900
ns
ns
2.6
IJ-S
2.5
IJ-S
Thermal Characteristics
Po
Power Dissipation
lOUT = 5.0 A
VOUT = 10 V
16
W
."
Efficiency
VOUT = 10V,
lOUT = 5 A
75
%
°J-C
Thermal Resistance
4.5
°C/W
Notes
1 fiC-A' Typical is 30°C/W for natural convection COOling.
2. For heatsinking requirements see power derating curve.
3·28
SH1605
Power Derating Curve
Design Equations
••
.
Efficiency (1/)
=
POUT X 100
I\.
Transistor DC Losses (PT) = lOUT X Vs tON
•
tOFF
Diode DC Losses (PO) = lOUT X VF tON + tOFF
\
0
'\.
5
Drive Circuit Losses (DL)
00
30
60
90
120
tON
+ tOFF
=
VIN2
tON
300 X tON + tOFF
'\150
Switching Losses Transistor:
tr + tf
(Ps) = VIN X lOUT 2(tON + tOFF)
CASE TEMPERATURE-oC
Transistor Duty Cycle
Diode Duty Cycle
=
Power Inductor (PL)
=
tON
tON
+ tOFF
tOFF
tON + tOFF
VOUT
=~
=1-
VOUT
~
= IOUT2 X RL (Winding Resistance)
Efficiency:
VOUT lOUT
(1/) = VOUT lOUT
3-29
+ PT + Po + DL + Ps + PL
X 100
SH1605
Design Considerations
Figure 1 is a typical design of a step-down switching
regulator using the SH1605.
The output capacitor can now be determined
as follows:
CO(min) = (8 f(min) Vripple(max»
Nominal Design Objectives
VOUT = +5 V
Line Regulation = 2%
IOUT(max) = 5.0 A
Load Regulation = 2%
IOUT(min) = 1.0 A
Ripple (max) = 0.1 Vpk-pk
VIN = 12 to 18 V
Efficiency = 70%
2
(8 X 7.7 X 103) X (1 X 10
The maximum acceptable ESR is therefore
Vripple(max)
ESR(max) = ~Il(max) = 0.025f!
First, R3 is calculated from Equation 5:
R3
=
(2 X 103)(VOUT - 2.5)
2.5
= 2 kf!
Normally, the minimum capacitance value should be
increased considerably if a low ESR capacitor
is not used.
Since the required IOUT(min) is 1 A to maintain
continouous operation, the peak-to-peak current
excursion must be equal to 2 A or less, i.e.,
~Il
As a final step for minimizing switching transients at
the device input, a low ESR capacitor must be used for
decoupling purposes between the input terminal
and ground.
= 2 IOUT(min)
To calculate the value of the inductor, assume the
nominal on time of the system as 60 fJ,s. This value is
chosen keeping the efficiency / component-size tradeoff in mind. From Equation 1.
L1
=
( VIN -~IlVOUT) ton
10
= ""2 (6
X 10- 5 )
1)
= 325 fJ,F
= 300 fJ,H
where VIN(nom) = 15 V, ton = 60 fJ,S
One very important element in achieving the optimum
performance in a switching regulator is to insure the
inductor is kept below the specified saturation limits.
The SH1605 is a highly versatile building block for
high current, step-down switching regulator systems.
However, to attain optimum performance and reliability
the following guidelines should be followed:
• Keep operating period long, relative to the device
switching times, for optimum efficiency.
• Insure that the inductor stays out of saturation and
minimize the series resistance.
• Use high quality capacitors for input and output to
minimize ripple and noise.
Fig. 1
Design Example
-..--_--tS r - - - - - - - - ,
Since the timing capacitor controls the 60 fJ,S on time,
CT can be determined using Equation 7:
300 ILH
SH160S
CT
=
(ton)(le)
~V
where Ie
CASE
= 25 fJ,A nominal per data sheet.
.OO331J.F
sov
The final step is to determine the requirements for the
output capacitor Co to obtain the desired value of
ripple voltage. Consideration must be given to the
absolute value of Co as well as the internal effective
series resistance (ESR). Since the capacitor size is
inversely proportional to the operating frequency, the
lowest frequency of operation must be calculated.
Minimum operating frequency can be determined by
using ~Il(max) vs ~11(nom) in Equation 9.
1
Minimum Frequency
1.3 X 10 4
7.7 kHz
=
Note
CirCUIt Performance
VIN = 12-18 V
VOUT = 506 V
Load Reg = 50 mV (1 A ~ lOUT ~ 5 A)
Lone Reg = 50 mV (12 V ~ VIN 18 V)
SH1605 must be mounted on a heat sonk wIth a maxImum thermal
resIstance of
Al?: 2kn
-55°C s: TA S +125°C
60>
~
~
0
>
V
~
0
>
I
•
~
.l.
12
11
5
L
~
i--" .....
"''''~ I-
1-1-'
10
V
14
13
-I-
---t:::
10
15
,
I
I
Vs - .!.15 V
R, - 10 k!l
~
0
TA - -55°~~'
50
~
g
~
~,.
o
o
o
•
10
11
,
0.2
0
02 04 06 08 10
o
"
Z
r-
30 k
-. r-.,
20>
II"'-i-
-kJ"J
I
I-
Vs -- +9V
~
60
20
20
11
--
100
60
0
12
14
13
15
T,
0
~15 J
t-25 C
Q
/'
24
'>
22
::>
20
~
18
~
Vs
28
26
/
/
0
~
$
~
>
TEMPERATURE _
140
j
16
14
II
12
10
01
02
c
05
10
LOAD RESISTANCE -
Input Bias Current as a
Function of
Supply Voltage
500
10
9
Output Voltage Swing as a
Function of
load Resistance
~ ~S"'.!:7S"
mY
Input Bias Current as a
Function of
Ambient Temperature
20
SUPPLY VOLTAGE --I:V
......
50 k
10
INPUT YOLTAGE -
-I-
o·
40
15
>
I
~ 40 k
~
_t-
30
~
I
15
10 0.8 06 04
14
>
z
~
f.- I-
~\""\~u'"
60
~:V
50>
~
I
-10
13
12
Voltage Gain as a
Function of
Ambient Temperature
:c
TA '-- 25°C
I
50
~
RLI-l01kn
j
o
g
Z
70
II
80
~
i!i
SUPPLY VOLTAGE -
TA - +125°C
J--
>
I
[lot-
-
~
1'!
50
15
- -
rp
"'~
;;;'
..,..~
Il"!!>-1.>"
-5;'C ~ T! ~ 1'251C
10
:
f.-~
~
SUPPLY VOLTAGE - "!:Y
Voltage Transfer Characteristic
f-
~_'\()~
20
~
o
i--"
I I
I
25
~
12
I
I
I
l1
I
I I
v
i--"
20 >
10
.YI
v
40 >
30>
>
./
.l~~
50>
is
~
30
I I
I I
I~ V
z
Input Common Mode Voltage
Range as a
Function of Supply Voltage
Output Voltage Swing as a
Function of Supply Voltage
k!l
Input Offset Current as a
Function of
Ambient Temperature
105
50
TA"" +25°C
~ 400
I
;
300
~
200
~
-
'\
\.
"100
r-....
0
60
20
20
.....
-
60
TEMPERATURE _
0
c
100
140
40
f.- _I--'"
I-f-
\
30
1\
20
\
85
10
60
o
•
10
11
12
13
SUPPLY VOLTAGE - ±V
4·12
14
15
60
20
,"20
r- .....
60
TEMPERATURE _
100
0
c
140
j.tA709
Typical Performance Curves for j.tA709A (Cont.)
Input Resistance as a
Function of
Ambient Temperature
Common Mode Rejection
Ratio as a Function of
Ambient Temperature
Power Consumption as a
Function of
Ambient Temperature
50
112
90
Rs _10k!!
Vs
'15 V
30
~
11 0
i1
"'oz
~
~
108
r--- ........
~
/
~
i
"'
!j
z
I
z
~
ti:
........
70
........
~
~
05
i
03
z
o
60
U
l-
~
C
10
r- ........
80
I
z
o
~
106
C
o
vV
I
"'w
~
~
104
50
o
u
1
102
20
60
20
60
140
100
TEMPERATURE _
0
12
-JVE~~
"!::0
~
TA
=
E
I
1
J
If- ,'5E TIMf
06
04
02
~
0
u
50
V
ffi
~
I
.
~
~
..... ~
30
~
10
05
10
15
20
9
2S
......
10
10
I
1/
~
f;'
....... V
",~\vo;;.-v
V
10
11
13
12
SUPPLY VOLTAGE -
TIME-J.1s
140
c
Ys=+15Y
./
,/
~
iilz
100
60
f::T' - 2S°C
~",+V
,..",Pr
70
20
100
V
90
20
Slew Rate as a Function of
Closed-Loop Gain
Using Recommended
Compensation Networks
V
z
0
60
TEMPERATURE -
2S"C
TA"'"' 25°C
~
40
140
100
QC
110
VS=~'5~_
10
08
so
28
Power Consumption as a
Function of
Supply Voltage
I-
~
28
TEMPERATURE -
Transient Response
14
60
c
14
1
15
10
±V
100
1000
CLOSED-LOOP GAIN
Typical Performance Curves for j.tA709 and j.tA709C
Power Consumption as a
Function of
Supply Voltage
110
Voltage Transfer Characteristic
,.
V
TA '" 25°C
Ys-±15V
Rl '" 10k!!
,/
~
E
90
~+V
+~~
I
z
~
7
0
iil
8
30
>
I
J~
5.0
I-
"
~
10
0
11
12
13
14
+Y
Q
15
~
I
08
l-
ii
!!iu"'
~
J
If'
-5.0
0
SUPPLY VOLTAGE -
TA - 2S C
I
w
"e
~
f-""
10
Vs=±15Y
I I
TA - +125 b C
§!
",~\V~
~
,/
50
"'
~
./
L""
,/
~
10
10
I
I
I If"
I fll
TA = -55°C". l"-
Input Bias Current as a
Function of
Ambient Temperature
06
"'
04
."
I-
r
!!:
.......
02
!1.
-15
-10 -08 -06 -.04 -02
0
0.2 04
INPUT VOLTAGE -
4-13
mY
06
0.8 1.0
r- t--
o
60
20
20
80
TEMPERATURE -
100
Q
C
140
}lA709
Typical Performance Curves for IlA709 and IlA709C (Cont.)
10
200
120
VA = :t15 V
~ 160
DB
:i
a: 120
~
~
~
80
$
~
""
40
-60
-20
~
r-- I-100
60
20
TEMPERATURE -
I
,
Vo 0;15
~
...
~
o"
~
~
~
I
/
26
/'
4
~
"o
~
I
6
4
~
/
2
02
05
LOAD RESISTANCE -
5
~
"
o
~'2.\<.n
...
.->-
50
w
>
11
10
12
14
13
3r--.
I-
3~
I-'"
11
w
15
>
i
150
7
125
5
12
SUPPLY VOLTAGE -
13
14
-+:.v
15
~
6
~ 1-1- .....
'po
I--
*'9
~""
/...(
I- VC~
~~O'lO
7l; f-o~8."
~
:O"'/l)1"1t
04
I I I
I I I
11
L
t2
¥FC-
L~~
..... t--.,
R~sPo
10
25
Frequency Characteristics
as a Function
of Ambient Temperature
;.1::9 V '$ yo c= .:15 V
~ ccosy-'r
11
20
15
",s
20
I
I I I
Oo~9"""
10
10
TIME -
fi 91- f-)EJ ~."
g
0
~O'Il\01'\,\
17 5
05
=V
cl
III
I
~~:i~~~-
I
I
I
f- RISETIM~
I
06
fi
02
9
140
c
,-
10
~ DB
50
~
...
",\~\"'\lt/l~
/1::: .-~
T,'25-
I-t- I-t-
I-
II
_,o~
0
~L~~
12
g 04
5
1-1-1200
14
I
100
60
Transient Response
I
- I - "'\~\~
20
20
60
TEMPERATURE _
0
TA = 25°C
...
140
Frequency Characteristics as a
Function of
Supply Voltage
225
0
°C
SUPPLY VOLTAGE -
25 0
~
100
60
I I
I
0
k!)
Input Bias Current as a
Function of
Supply Voltage
I-I-
60
0
25
10
--
I--
~ --
a:
~
d-C~T,I'-H
o
10
01
o
20
Z
/
0
V
-20
Cl
~
/
2
~
Output Voltage Swing as a
Function of Supply Voltage
>
80
~
TEMPERATURE -
J
-l-
z
~
;'
0
-60
140
TA -" +25°C
,
02
30
Cl
Z
........v
"C
Output Voltage Swing as a
Function of
load Resistance
0
0.4
~
100
I
'/
/
... v
'"
o
>
06
>!
...
~
./
I
iii
!!i
0
~
Vs=±15V
Vs '" :!12 V
...I
iu
ff!
Power Consumption as a
Function of
Ambient Temperature
Input Resistance as a
Function of
Ambient Temperature
Input Offset Current as a
Function of
Ambient Temperature
12
13
SUPPLY VOLTAGE -
4·14
14
.v
15
0
-60
-20
20
60
TEMPERATURE _ °C
100
140
J.1A709
Typical Performance Curves for J.lA709 and J.lA709C (Cont.)
Voltage Gain as a
Function of
Supply Voltage (709C only)
15k
2 kn
+70°C
-5S~C
<
V
"
"~
w 10 k
~
:...-
0
~
is
5k
o
"
"~
w
~
..... 1--'"
is
g
I
10 k
10
11
12
14
13
SUPPLY VOLTAGE -
15
9
"z~
80
"g~
60
w
--
10
11
12
i--
40
Z
o
~
~
8
14
13
SUPPLY VOLTAGE -
-tv
1.--1--'"
--
to\\N't.'U'"
o
g
"""'~-
I
~70°C
,....-
w
V
20 k
I
w
k-'
40 k
I
T,
10
,/
...l,'¢
~-;:
50 k
30 k
O°C
1/
I
Z
~
0
9
Q
<
""'V
...!.¢;::;--
~
.,- TA"':: r125 C
60 k
..... V
I
V
RL _ 2 kn
<
Z
g
12
10k
R,
QOC, TA
Input Common Mode Voltage
Range as a Function of
Supply Voltage
Voltage Gain as a
Function of
Supply Voltage (709 only)
20
o
15
9
~_V
10
12
11
SUPPLY VOLTAGE -
14
13
15
•v
Frequency Compensation Curves For All Types
Open-Loop Frequency
Response for Various
Values of Compensation
Frequency Response for Various
Closed Loop Gains
Output Voltage Swing as a
Function of Frequency for
Various Compensation Networks
>
I
"~
Z
2'
"e:
20
:>
0
~
<15 V
2S u C
2.
16
12
~
.0
~
40
~
FREQUENCY -
FReQUENCY - Hz
Hz
FREQUENCY -
Test Circuits
Frequency Compensation Circuit
Transient Response Circuit
10 kll
R2
R2
>--p-.A./'I/'v~-~....-
Vour
Note
Use R2 = 50 n when the amplifier ,s
operated w,th capacitive loading
Note
Pon numbers on this and all succeeding
circuits apply to metal can
or mon, DIP package.
4-15
Hz
•
p,A709
Input Breakdown-Protection
Protection Circuits
R1
Output Short-Circuit Protection
01
R1
6
20011
R2
Supply Overvoltage-Protection
v+
Latch-Up Protection
R1
R2
01
R1
01
6
>~~-EOUT
EIN --'VV........._
Pm numbers apply to metal can or mml DIP package only.
4-16
JlA714
Precision Operational
Amplifier
FAIRCHILD
A Sehlumberger Company
Linear Products
Description
The JtA714 is a Monolithic Instrumentation Operational
Amplifier constructed using the Fairchild Planar
epitaxial process. It is intended for precise, low-level
signal amplification applications where low noise, low
drift and accurate closed-loop gain are required. The
offset null capability, low-power consumption, very
high-voltage gain as well as wide power-supply
voltage range provide superior performance for a wide
range of instrumentation applications.
•
•
•
•
•
•
•
•
Connection Diagram
8-Pin Metal Package
-IN
LOW OFFSET VOLTAGE 75 JtV
LOW OFFSET VOLTAGE DRIFT 1.3 JtV/oC
LOW BIAS CURRENT ± 3.0 nA
LOW INPUT NOISE CURRENT 0.17 pAl yHz
@ 1.0 kHz MAX
HIGH OPEN LOOP GAIN 500,000 TYPICALLY
LOW INPUT OFFSET CURRENT 2.8 nA MAX
HIGH COMMON MODE REJECTION 110 dB MIN
WIDE POWER SUPPLY RANGE ± 3.0 TO ± 22 V
Absolute Maximum Ratings
JtA714,JtA714E,JtA714C
Supply Voltage
Internal Power Dissipation
(Note 1)
Metal Package
Differential Input Voltage
Input Voltage (Note 2)
Storage Temperature Range
Metal Package
Operating Temperature Range
Military
Commercial
Pin Temperature
Metal Package (Soldering, 60 s)
JtA714L
Supply Voltage
Internal Power Dissipation
(Note 1)
Metal Package
Differential Input Voltage
Input Voltage (Note 2)
Storage Temperature Range
Metal Package
Operating Temperature Range
Military
Commercial
Pin Temperature
Metal Package (Soldering, 60 s)
>---(JOUT
v(Top View)
Order Information
Type
Package
714
Metal
714E
Metal
714C
Metal
714L
Metal
Code
5W
5W
5W
5W
Part No.
JtA714HM
JtA714EHC
JtA714HC
JtA714LHC
±22 V
500mW
±30 V
±22 V
-65°C to +150°C
-55°C to +125°C
O°C to +70°C
300°C
± 18 V
500mW
±30 V
± 18 V
-65°C to +150°C
O°C to +70°C
300°C
Noles
1. Ratings applies to ambient temperature to 70 oe. Above
TA = 70 0 e derate linearly 6.3 mW/oe.
2. For supply voltage less than ± 22 V, the absolute maximum
Input voltage IS equal to the supply voltage.
4-17
J.LA714
Equivalent Circuit
,
A2A'
~
r--o~UlL
~~
".
'"
e,
Q10>-
a"
a,'(~
'"
I
a~,a.~a·~a"
INPUT
1""~~'
a"
"
NPUT
'"
e,
~~
".
e,
C<
~
o,.~
a"
a"
:-;:J,
1Q42
a,,~a..
'"
'"
LKo"
'"
."
'"
,~15
a..
o,,~
a"
'"
....--
Q35>- ".
"
J. 'ia,
a"
"
~
~
0"
a"
SUPPLY
'"
a.
"
F>O$ITIVE
)Q33
"
~
Q30(
R2S'
a..
".
'"
a":::t-
"
J
.
OUTPUT
a,.
0,"
".
".
'"
.
NEGATIVE
SUPPLY
R2A and R2B are electronically adjusted on chip at the factory for
minimum offset voltage
4-18
J.LA714
J.LA714
Electrical Characteristics
These specifications apply for Vs = ± 15 V, TA = 25°C.
714
Characteristic
Condition
Min
Input Offset Voltage
(Note 3), Rs = 50 fl, VCM = 0.0 V
Long Term Input Offset Voltage Stability
(Note 4), RS = 50 fl, VCM = 0.0 V
0.2
1.0
Input Offset Current
VCM = 0.0 V
0.4
2.8
Typ
Max
30
75
Input Bias Current
VCM = 0.0 V
± 1.0
±3.0
Input Noise Voltage
0.1 Hz to 10 Hz (Note 5)
0.35
0.6
Input Noise Voltage Density
fa = 10 Hz (Note 5)
fa = 100 Hz (Note 5)
fa = 1000 Hz (Note 5)
10.3
10.0
9.6
18.0
13.0
11.0
Input Noise Current
0.1 Hz to 10 Hz (Note 5)
14
30
Input Noise Current Density
fa = 10 Hz (Note 5)
fa = 100 Hz (Note 5)
fa = 1000 Hz (Note 5)
0.32
0.14
0.12
0.80
0.23
0.17
Input Resistance-Differential Mode
20
Input Resistance-Common Mode
60
200
Input Voltage Range
± 13.0
± 14.0
110
126
Common Mode Rejection Ratio
VCM = ± 13 V, Rs = 50 fl
Power Supply Rejection Ratio
Vs= ±3.0Vto ±18V,RS=50fl
100
110
RL 2: 2.0 kfl, Va = -10 V to +10 V
200
500
RL 2: 500 fl, Va = -0.5 V to +0.5 V
Vs= ±3.0V
150
500
Large Signal Voltage Gain
Maximum Output Voltage Swing
Slewing Rate
RL 2: 10 kfl
± 12.5
± 13.0
RL 2: 2.0 kfl
± 12.0
± 12.8
RL2: 1.0kfl
± 10.5
± 12.0
RL 2: 2.0 kfl
0.17
Closed Loop Bandwidth
AVCL = +1.0
0.6
Open Loop Output Resistance
Va = 0 V, 10 = 0 A
60
Va = 0 V
75
120
Vs = ±3.0 V, Va = 0 V
4.0
6.0
Power Consumption
Offset Adjustment Range
Rp = 20 kfl
±4.0
The following specifications apply for Vs = ± 15 V, -55°C
~
TA
~
+125°C
Input Offset Voltage
(Note 3), RS = fl, VCM = 0.0 V
60
200
Average Input Offset Voltage Drift
Without External Trim
RS = 50 n, VCM = 0.0 V
0.3
1.3
(Note 5), Rp = 20 kn, RS = 50 n
0.3
1.3
Input Offset Current
VCM = 0.0 V
1.2
5.6
Average Input Offset Current Drift
VCM = 0.0 V
8.0
50
Input Bias Current
VCM = 0.0 V
±2.0
±6.0
Average Input Bias Current Drift
VCM = 0.0 V
13
50
With External Trim
Input Voltage Range
± 13.0
± 13.5
123
Common Mode Rejection Ratio
VCM = ± 13 V, RS = 50 n
106
Power Supply Rejection Ratio
Vs= ±3.0Vto ±18V,RS=50n
94
106
Large Signal Voltage Gain
RL 2: 2.0 kn, Va = -10 V to +10 V
150
400
Maximum Output Voltage Swing
RL 2: 2.0 kn
± 12.0
± 12.6
4-19
p,A714
Min
15
714E
Typ
Max
714C
Typ
Max
714L
Typ
30
75
60
Max
Unit
150
100
250
0.3
1.5
IlV
0.4
2.0
0.5
3.0
0.5
IlV/mo.
3.8
0.8
6.0
5.0
20
nA
± 1.2
±4.0
± 1.8
±7.0
6.0
±30
0.35
0.6
0.38
0.65
10.3
10.0
9.6
18.0
13.0
11.0
10.5
10.2
9.8
20.0
13.5
11.5
"14
30
15
0.32
0.14
0.12
0.80
0.23
0.17
0.35
0.15
0.13
50
Min
8.0
Min
10.5
10.2
9.8
nV/VHZ
35
15
pA pop
0.90
0.27
0.18
0.35
0.15
0.13
pA/VHZ
33
MQ
120
GQ
8.0
33
120
160
nA
IlVP-P
± 13.0
± 14.0
± 13.0
± 14.0
± 13.0
± 14.0
V
106
123
100
120
100
120
dB
94
107
90
104
90
104
dB
200
500
120
400
100
300
150
500
100
400
50
150
± 12.5
± 13.0
± 12.0
± 13.0
± 12.0
± 13.0
± 12.0
± 12.8
± 11.5
± 12.8
± 11.0
± 12.8
± 10.5
± 12.0
± 12.0
± 12.0
0.17
0.17
0.17
0.6
0.6
0.6
MHz
60
60
60
Q
V/mV
V
V/IlS
75
120
80
150
100
180
4.0
6.0
4.0
8.0
5.0
12
±4.0
±4.0
The following specifications apply for Vs =
±4.0
mW
mV
± 15 V, ooe :::; TA :::; 70 e
0
45
130
85
250
400
IlV
0.3
1.3
0.5
1.8
1.0
3.0
Ilv/oe
0.3
1.3
0.4
1.6
0.9
5.3
1.6
8.0
8.0
40
8.0
35
12
nA
50
20
100
pA/oe
IlV / °e
± 1.5
±5.5
±2.2
±9.0
±15
±60
nA
13
35
18
50
35
150
pA/oe
± 13.0
± 13.5
± 13.0
± 13.5
± 13.0
± 13.5
V
103
123
97
120
94
120
dB
90
104
86
100
83
100
dB
180
450
100
400
80
400
V/mV
± 12.0
± 12.6
± 11.0
± 12.6
± 10.0
± 12.6
V
4·20
JLA714
Typical Performance Curves
Untrimmed Offset Voltage
Versus Temperature
Trimmed Offset Voltage
Versus Temperature
>~ 90
>~ 30
,
w
"!:ic
g
Iii
ii!i
/
80
Vs - :t15V
R
70
=
100
60
50
40
I--"
I'..
w
3c
30
..~
10
/
I'..
/
V-::A714
Iii
20
~
~
-50
50
100
I
II 0/
~ I\@ @
~\\
~
5OJ
UI
~ ~A714
~
10
12
~ .A714l
• ~714C
i!igo
..d- V
>
w 20
C
i
"!:ic
g
J.C.A714~
16
Vas TRIMMED TO < 5.0 p.Y
NULLING p?T = ~O kn
w
If.A714C
n
Offset Voltage Stability
Versus Time
II
/(J)
...
C
o:!
-B
-12
-16
1
2
3
TEMPERATURE _ °C
1000
4
5
6
7
B
25
TA
';.
BOO
.."~
§
600
400
-
L.-- f -
z
~
0
200
50
TEMPERATURE - "C
100
w
~g
Iii
...~
'"
!!!
..
10
:z:
(.)
-50
,
20
z
0
-20
Vs"" :t15V
';.
25
~ ,.
S
.
".
!!!
!!!
w
11 12
1 25'C
tJ.A714
~,
W
Warm-Up Drift
30
,
w
~
g
9
TIME-MONTHS
Offset Voltage Change
Due to Thermal Shock
Open Loop Gain
Versus Temperature
¥ilNbmL~NE
-4
~
100
50
- ~~l.:'b":.':NE
Q
£~
-50
TEMPERATURE _ °C
TREND LINE
I='T'": ~~l.:'bmL~Nl- ~~l.tbmo1Nl
;::
E
'\l Ij'
..
'"
i'"
02IJ.Vl mo
~l.}'bmaJNE
,
w
';.
!!!
w
"li:z:
DEY1CE IMMERSED
' / IN 70'0 OIL BATH
20
40
.. ..
nMe - SECONDS
Notes
3. Input offset voltage measurements are performed by
automated test equipment approximately 0.5 seconds after
application of power.
4. Long term input offset voltage stability refers to the averaged
trend of VOS versus time over extended periods after the first
(.)
100
20
15
r
A 14C " ,
IJ.
.... 714E
10
..-:
U ;..--
If
,
",A714
TIME AFTER POWER SUPPLY TURN-ON - MINUTES
30 days of operation. Parameter is not 100% tested. 90% of
the units meet this specification.
5. Parameter IS not 100% tested; 90% of the units meet
thIS specificatIon.
4-21
•
~A714
Typical Performance Curves (Cont.)
Maximum Error Versus
Source Resistance
Maximum Error Versus
Source Resistance
Maximum Error Versus
Source Resistance
~
~
:;
10
1.0
TA "" 25°C
Vs = ±1S y
~
192
0.8
$
~
~
~
~ ",A714E
·~714C
i
a:
~
O.
a:
~a:
:I
""'~
o
01
10
10
~
~ 06
a:
a:
100
a: ••
..~ ••
a:
Input Bias Current
Versus Temperature
-
~
~A714
i
i •
0.1
/
'.0
Ys - ±15 V
.........
lr-- -
..
0
r
~
~
r-:A714E
20
. ,.
"
A7
"
1000
~
.
"~
.,..
I
.
!!!
-30
=0
1
./
1
./
-20
-10
130
;:~1:15VI
....,
,.0 ~
~A714C
/
0
••
10
30
30
CMRR Versus Frequency
./
..~
.,.
V
DIFFERENTIAL INPUT VOLTAGE
- 1•
r--
100
10
L.o
/
... 7.0 nA (P,A714C)/
~Z -30
'.0
50
EXCLUDED
Rs
,/
Input Wideband Noise
Versus Bandwidth
(O.1 Hz to Frequency Indicated)
THERMAL NOISE OF SOURCERESISTORS INCLUDED
r-
i'-.[\ ~
-30
./
I
~ -10
TEMPERATURE _ "C
,.
VDIF~
..;; 1.~ V
Ie ... 3.0 nA (p,A714)
!!!
.0
100
Ys - :t15Y
TA "" HOC
~
JLA714C
I~
100
0
~
S
'\
. ••
-l.! ll., ~ 20l ~~k
.;:::: t-
>
,.
TEMPERATURE - QC
Input Spot Noise Voltage
Versus Frequency
po..
i!;
~
1\
p.A714
!!!
50
30
10
Iii
,/
1
~
a:
a:
10
MATCHED OR UNMATCHED SOURCE RESISTANCE - k!1
aa:
u
-
10
.0
IZ
- -
/
Input Bias Current
Versus Differential Input Voltage
••
~
3
II
../
JLA714E
Input Offset Current
Versus Temperature
Ys = ±15 V
1
•
JLA714C
1.
10
I
/
/
MATCHED OR UNMATCHED SOURCE RESISTANCE - kO
MATCHED OR UNMATCHED SOURCE RESISTANCE - kO
2
O"C,.,. TA "" 70"e
Ys = ±15 Y
08
!!!
~
/~
.. O.
I
/
·~714
0&
12
-5S°C "" fA'" 125"C
Vs = ±15 V
11.
i
Iv~ J±IUt
TA = 250C
I\t\
-11(10
r'\~
I
I
a:
90
80
,.,.
~A714
v.
,.
+15 Y
TA = 25"C
,,~
V"
f-
.,
O. 1
100
FREQUENCY - Hz
1000
,.
70
r10
10
BANDWIDTH - kHz
4-22
'.0
••
10
100
,.
FREQUENCY - Hz
10k
lOOk
JLA714
Typical Performance Curves (Cont.)
Open Loop Gain Versus
Power Supply Voltage
PSRR Versus Frequency
120
~A 10 kbLJ
JW4
11 0
i
I\t\
1\
~
.
9
~
70
t\
0
10
10
ill,
100
/'
~
1k
ill,
z
c
"
~
b--.
0
4
c
llJ
g
20
±.
..e
..'"
'"
w
w
w
l\..
"~
100
lK
10k
100k
,
:iii
a:
~
10
10
1
30
"
"
2.
3.
~
u
!:
u
!!;
u
.AJ,4
-
1000
100
.."ili
60
v- - v
1
Ys = :!:1S V
.\
~~
"""-
0
40
1M
20
f--
1.
-_®
YiN
-
~
~~IN (PIN 3)
3)
i
= -10 mY, Yo = +15 V
(Pli =,
+10
V' V, =
-1
5 V
o
TIME fROM OUTPUT BEING SHORTED-MINUTES
4-23
10M
NEGATIVE SWING
1
II
II
10
LOAD RESISTOR TO GROUND - kO
TA = 25°C
,:.
TOTAL SUPPLY VOLTAGE, Y+ to
I
1\
a:
20
100k
pls,Ll JJ.lll
1.
"z
12
E
I
"
o
10k
II III
TA = 25°C
Y,N = ±10 mY
i
.
..15
0
10
1k
p.A714
16
Output Short-Circuit Current
Versus Time
IL
is
100
f- Ys =±15Y
,
FREQUENCY - kHz
'"
..
10
20
>
o
".
~
10
0
1M
=¥:71~5°C
100
"
Output Voltage Versus
Load Resistance
2D
...
5"
1DOD
E
"-
FREQUENCY - Hz
Vs = ±15 V
TA = 25°C
>
Power Consumption Versus
Power Supply
Z
01
.171~11111
t-
24
FREQUENCY - Hz
.
..
±20
::!:15
0
"\
"-
-40
:<:10
C
~~
10
40
9z
\
..
,
r'\.
200
Maximum Undistorted Output
Versus Frequency
C
U
r-....
POWER SUPPLY VOLTAGE - V
Vs = ±15 V
TA = 25°C
~
".
Vs = ±15V
TA =25°C
w
o
~A711
•0
80
0
o
10k
Closed Loop Response For
Various Gain Configurations
100
.........
400
FREQUENCY - Hz
so
r'\.
C
~
o
.17141
i"'-.....
z
-...... :--..
600
~
t\
0
01
l"-
800
100
..
120
t£A714
r-TA '" 25°C
.~i,~C
ill, ..
I
Open Loop Frequency Response
1000
•
JLA714
Test Circuits
Optional Offset Nulling Circuit
Ro
Offset Voltage Test Circuit
20kO
;;>-oo.......--v+
200 kO
500
INPUT { :
OUTPUT
vLow Frequency Noise Test Circuit
+15V
100 0
>6'--....._3.Jo.3>/V1kO..--......_
1000
r
2.SMO
Input Referred Noise
OUTPUT
4 .7 1-'F
(",10 Hz Filter)
V
5 mV/cm
25,000
25,000
= __0_ = - - - = 200 nV/cm
4·24
JlA715
High-Speed
Operational Amplifier
FAIRCHIL.O
A Schlumberger Company
Linear Products
Description
The IlA715 is a High-Speed, High-Gain, Monolithic
Operational Amplifier constructed using the Fairchild
Planar epitaxial process. It is intended for use in a
wide range of applications where fast signal
acquisition or wide bandwidth is required. The IlA715
features fast settling time, high slew rate, low offsets
and high output swing for large signal applications. In
addition, the device displays excellent temperature
stability and will operate over a wide range of supply
voltages. The IlA715 is ideally suited for use in AID
and D I A converters, active filters, deflection
amplifiers, video amplifiers, phase-locked loops,
multiplexed analog gates, precision comparators,
sample and holds and general feedback applications
requiring dc wide bandwidth operation.
Connection Diagram
1o-Pin Metal Package
• HIGH SLEW RATE-100 Vllls
• FAST SETTLING TIME-SOO ns
• WIDE BANDWIDTH-65 MHz
• WIDE OPERATING SUPPLY RANGE
• WIDE INPUT VOLTAGE RANGES
Order Information
Type
Package
IlA 715
Metal
IlA 715C
Metal
Absolute Maximum Ratings
Supply Voltage
Internal Power Dissipation
(Note 1)
Metal
DIP
Differential Input Voltage
Input Voltage (Note 2)
Storage Temperature Range
Operating Temperature Range
Military (IlA715)
Commercial (IlA 715C)
Pin Temperature (Soldering, 60 s)
COMP1A
v(Top View)
Part No_
IlA7 15HM
IlA715HC
Code
5X
5X
Connection Diagram
14-Pin DIP
± 18 V
14
500 mW
670mW
± 15 V
± 15 V
-65°C to +150°C
-55°C to +125°C
O°C to +70°C
300°C
COMP1A
COMP2B
COMP1B
v+
CASCO DE
COMP2A
-IN
OUTPUT
+IN
v-
NC
NC
NC
NC
(Top View)
Order Information
Type
Package
IlA715
Ceramic DIP
IlA715C
Ceramic DIP
Notes
1 Rating applies to ambient temperature up to 70°C. Above
70°C ambient derate linearly at 6.3 mW I °c for metal package
and 8.3 mW 1°C for the DIP.
2. For supply voltages less than ± 15 V, the absolute maximum
input voltage IS equal to the supply voltage.
4-25
Code
6A
6A
Part No.
IlA715DM
IlA715DC
•
I-LA715
Equivalent Circuit
r-----------._------~r_----------._------------~------._------._------._------,_~V+
R6
2 kll
R18
• kll
R19
4 kn
R24
10 kn
+-__________i-________r-__________f-__
~COMP2B
1 kll
10
R7
COMP1A--JV~----.
400
n
COMP 1B
R20
50
2
R
INVERTING _3_...,,1,..,.-<
INPUT
400 II
CASCODE
R8
25 kn
R2
400
n
6
15 pF
OUT
R27
50 n
n 4
NONINVERTING
INPUT
R15
2 kll
R16
300 II
~--~~--_4
R17
500 n
R22
300n
________________________
All pin numbers shown refer to 1O-pon metal package
4-26
R23
3 kn
R25
75 n
5
_4------~----~----_4---V-
JLA715
ItA715 and ItA715C
Electrical Characteristics
Characteristic
Vs = +
- 15 V TA = 25°C unless otherwise specified
ItA715
Typ
Condition
Min
Max
Input Offset Voltage
Rs::s 10 kQ
ItA715C
Typ
Min
Max
Unit
2.0
5.0
2.0
7.5
mV
Input Offset Current
70
250
70
250
nA
Input Bias Current
400
750
0.4
1.5
1.0
itA
MQ
±12
V
Input Resistance
1.0
Input Voltage Range
Large Signal Voltage Gain
±10
RL::::: 2 kQ, VOUT
=
± 10 V
±12
± 10
15,000 30,000
10,000 30,000
Output Resistance
75
Supply Current
5.5
7.0
5.5
10
Power Consumption
165
210
165
300
Settling Time (Unity Gain)
VOUT
Transient
Response
(Unity Gain)
VIN
Rise Time
= ±5 V
800
= 400 mV
Overshoot
= 100
Av = 10
Av = 1 (non-inverting)
Av = 1 (inverting)
Av
Slew Rate
800
60
30
75
25
40
25
50
38
18
10
100
mW
ns
%
VIItS
VIItS
Vllts
V I itS
70
38
rnA
ns
30
70
15
Q
75
18
100
The following apply for TA High to Low (Note 4)
Input Offset Voltage
Input Offset Current
Input Bias Current
RS::S 10 kQ
7.5
10
mV
= High
TA = Low
TA = High
TA = Low
250
250
nA
800
750
nA
750
1500
nA
4.0
7.5
itA
TA
Common Mode Rejection
Ratio
RS::S 10 kQ
Supply Voltage Rejection
Ratio
RS ::s 10 kQ
Large Signal Voltage Gain
Output Voltage Swing
RL::::: 2 kQ, VOUT
RL::::: 2 kQ
74
45
=
± 10 V
10,000
±10
Note
3. Specification applies to TA = 25°C only.
4. For I'A715 -55°C:oS TAoS 125°C
For I'A715C DOC:oS TAoS 7DoC
4·27
74(3)
92
92(3)
45(3)
300
dB
400(1) ltV IV
8,000
±13
±10
±13
V
•
p.,A715
Typical Performance Curves for ",A 715
Supply Voltage Rejection
Ratio as a Function of
Ambient Temperature
Open Loop Gain as a
Function of
Ambient Temperature
so.
VS~±l~V
RL=20kn
'0
-
Z
.
~30
10
160
~
140
~
120
-'0
80
40
2.
w
"
2
..
10kJl
10
~
I'....
t"-
•
•
0
,
r---
15
I
60
~
120
~
80
0
4
RL
t"-
,\
t;
~
v/"L
-
Vs=±15V
-'0
eo
40
°C
TEMPERATURE -
25
Rsl~ ,,1,"
100
"B
•
•
~
~OJ
t"-
•
20
o
180
z
o
•I-
9
~
•
200
~
Slew Rate as a
Function of Temperature
TEMPERATURE _
0
.0
120
80
40
TEMPERATURE _
C
0
120
c
Typical Performance Curves for ",A715C
Common Mode Rejection
Ratio as a Function of
Ambient Temperature
Supply Voltage Rejection
Ratio as a Function of
Ambient Temperature
Open Loop Gain as a
Function of
Ambient Temperature
100
~
m
u
I
o
~
100
I
I--+-+--+-f-+-+-+-If-+---l
g
.
t;
~
z
~
90
1l
80
~
/
~
..........
~
f-~+-+-I-+-+-+--+~k---l
~
f+/+-+-+-l-+-+-+--I-H
~
z
g
8
rol--+-+-+---j-t---l--+--+-I----l
10.1---t-+-t--If--t-+--;
0~0--~'0--~2O~~~~~'~0--~SO~~6~0~70
TEMPERATURE _
0
c
TEMPERATURE _
Slew Rate as a
Function of Temperature
°c
110
I
g
~
25
t
I
Z
0
20
w
.
r-- t----...
t;
~
100
~sOoloL;_
15
~
..
..1lz
....
g
80
~.
Vs
-
=
±15 V
0
10
0
o~~_~_~_~~_~--J
010203040506070
TEMPERATURE _ °C
70
.
10
20
30
so
40
TEMPERATURE _
4-28
0
c
~
. , ..........
.
...........
'0
20
o
--
010203040506070
TEMPERATURE -
Common Mode Rejection
Ratio as a Function of
Ambient Temperature
!!i
~
g
~
R~510k!~ _
Vs"'±15V
80
..
7•
~
c
JLA715
Typical Performance Curves for jlA715 and jlA715C
Open Loop Gain as a
Function of Frequency
120
Vs
+15 V
TA -= 25°C
--00
'9
I
z
w
.
.!i!
40
""
"~
"
o..~'1,11
~~..,...~~-
'1l
'b
"
'?..
Z
I
,1\
"
IIII
10k
1M
lOOk
10M
100
10k
1k
SOU
I
80~+#~++ij-~~~fH~~~
.
10M
FREQUENCY -
Output Swing as a
Function of Frequency for
Various Closed Loop
Gain Configurations
30
>
I
25
!"
20
!~ .. 1=t#t=t=F**=t=l*fflffif+H
~+#~++ij-~~~tttH*tti
40
~ 2o~+#~++ij-~~~tttH-+tti
~
15
~
10
FREQUENCY -
II
o
~40I-++H-+-H1H-+ttt-+t+tH-H1tl
g
~
30
2.0
6
10
0001
1.0
0.1
0.01
10
50
FREQUENCY - MHz
Large Signal Pulse
Response for Gain 10
•. 0
i
I
4.0
w
I
\
I
~
3.0
~O
2
g
!\
I
o
Vs=±15V
TA = 25°C
so
\
I
1o
-10
kHz
10
MHz
Vs=±15V
TA == 25°C
40
~
FREQUENCY -
01
A
50
...
1\
-320
6.0
g
1\
~ -240
Unity Gain Large Signal
Pulse Response
~ .. I-+~+-H1+-l-+ttt-+t+tH-H1tl
1\
~
FREQUENCY -
>
I
Vs=±15V
TA = 25°C
N COMP
-400
om
•
I
GAIN 1(10
i
o.~
80~~~~~-+~,4-~H-H~
"
!30-160
i
100 rr1"TT"-rTTlT""'T-,-1"TT"....nTl'""T""T1"T1
~20~~~~~-+H+-4-~H-H~
m -80
1111
II
GAIN 10
'9
"
1111
1111
GAIN 1
kHz
Common Mode Rejection
Ratio as a Function of
Frequency
....
Rl "'10 ktl
6
~~~~~0.Lm~U-~~~1~0~~'0~~~'
Hz
Open Loop Phase as a
Function of Frequency
Vs ±15 v
TA '" 2S°C
!;
~
01':-k~"'-::107kJ..J..lJ'=100:'::-::'k..w-:-''::M~~1~0::MUJ.~'00 M
SOM
Hz
z
~
o
~
1M
Vs=±15V
H-Ht+++It-1I-tttt--t-!~ : ~~gMP
.
lOOk
FREQUENCY -
r-'T"TT1"-.-"TT"'-'r-TT'TT"-'-M"Tr-r-,-m
~
I
IIII
Hz
Supply Voltage
Rejection Ratio as a
Function of Frequency
~
1111
GAIN 1
-20
FREQUENCY -
~
GAIN 10
20
,~
-20
1k
2
~
1'1\
I III
20
r0
>
IIII
GAI~I 100
40
z
\
...,,~
100 rrnr..-rrrrr"TTTrrr1"TT"-.-nrr1
25°C
GAIN 1.000
60
II
0
9
TA
100
80
Open Loop Response With
Compensation Necessary for
Various Closed Loop Gain
Configurations
Closed Loop Frequency
Response for Various Gain
Configurations
80
IIJ, _I "ls lv
IIII
0
-1.0
400
800
TIME - ns
4·29
1200
1800
\
1.0
\
o
200
400
600
800
1000 1200 1400 1600
T1ME- ns
JLA71S
Typical Performance Curves for ILA715 and ILA715C (Cont.)
Slew Rate as a
Function of the
Closed Loop Gain
Large Signal Pulse
Response for Gain 100
60
Vs
~
TA
~
100
-1::15 V
25"C
Slew Rate as a
Function of
Supply Voltage
,---,-rrr-,-.--rrr-'--'
Ys - :!"15 Y
I
40
t1
1
w
"
30
g
20
_
1.0
Il
~O
/
6Of-~+H--f-++i7'''--~--1
200
400
600
800
20
1600
16
12
~
I'
I'
0~1-~~~~1~0-~~~~'00=-~
10
CLOSED LOOP GAIN
18
14
SUPPLY VOLTAGE -
Voltage Follower
22
V
Voltage Offset Null Circuit
v+
v+
50 kll
FD100
5OO~~~~-+--+--+--1-~
'" ..0
/\
1
90M
/
!,..o"'l-i-'""'-H+--+--+-H-+-+---i
TIME -ns
Voltage Follower
Transient Response
/
1
:
~ 4Of-~-bj..VF-~_/++H-_~--1
1000 1200 1400
~
Rl = 10 kit
NO COMP
w
~
o
/
20
w
~
-1.0
T,I" 2'!C
RL = 10kn
0
>
24
I--++-H--I---I-+-I-+TA = 25°C
V"
~300f---fi--+--j--+-+--j---1
o
200
100
~-II+/!-+--+-+---I--+~
f-ff,,=='=::::-l-+-+--j---1
I i RIS~I TIME
4
100
150
200
250
300
7
51 11.0
2.0
nF
,t-r,-'O%I
50
+
350
TIME-ns
v~
nF
-= -
Note
Pin numbers apply to metal package.
Inverting Unity Gain
Large Signal Pulse Response
2.0
5 kll
Vsl~ ±1~ v
~
Vs = :!:15 V
TA = 25"C
VIN '-- 400 mV
TA = 25°C
>
1
g
Small Signal Pulse Response
Inverting Unity Gain
High Slew Rate Circuit
'E
INPUT
1
w
20
5~ -4.0
OUTPUT
-200
~
~
,
:>
0
-400
-15 V
2.5 kll
~400
g
:>
It..
-6.0
"~
\
\
400
800
1200
"
IV
160
1600
TIME - " ,
TIME - ns
4-30
320
480
J.LA715
Frequency Compensation Circuit
Non-Inverting Compensation Components Values
C1
Closed
Loop
Gain
1000
100
10 (Note)
C1
C2
C3
10 pF
50pF
1
250 pF
100 pF
500pF
1000 pF
500 pF
2000pF
1000 pF
C2
Note
For gam 10, compensation may be simplified by removmg C2, C3
and adding a 200 pF capacitor (C4) between Pm 7 and 10
C3
I I
Suggested Values of
Compensation Capacitors as a
Function of the
Closed Loop Gain
Vs=±15V
~1000
I
~
z
~
o
~
u '00
"1;-
•
C,
"
c~···.
c,
.....
t-
Co
.....
.....
....
'0,L.....L...J....L.L-,J,-o.....L...J....L.L-'oo~J.....J...u..~'ooo
CLOSED LOOP GAIN
Layout Instructions
Layout- The layout should be such that stray
capacitance is minimal.
Supplies-The supplies should be adequately
bypassed, Use of 0,1 J.!F high quality ceramic
capacitors is recommended.
Ringing-Excessive ringing (long acquisition time)
may occur with large capacitive loads. This may be
reduced by isolating the capacitive load with a
resistance of 100 n. Large source resistances may
also give rise to the same problem and this may be
decreased by the addition of a capacitance across
the feedback resistance. A value of around 50 pF for
unity gain configuration and around 3.0 pF for gain 10
should be adequate.
Latch·Up- This may occur when the amplifier is used
as a voltage follower. The inclusion of a diode
between pins 6 and 2 with the cathode toward pin 2 is
the recommended preventive measure.
4·31
J.LA715
Typical Applications
Wide Band Video Amplifier With
75 Q Coax Cable Drive Capability
0.5 pF
10
VIDEO OUTPUT
TO 75 !l COAX
75 !l
'\
-10
o dB-
255 mVpk - pkOUT
SI-'A pk- pk
-20
bUT
1\
\
~v
750 Jl
500 II
75 !l
NOISE
= 2
RMS
pk - fk SIG/R~S NOISE I'" 42 dB
-40
0001
001
01
FREQUENCY -
10
100
MHz
75 l!
~
EQUIVALENT CIRCUIT
FOR IMAGE ORTHICON
2N3638
51 kll
750
To·l
-=
High Speed Integrator
20
15
10
1 1\
,/'NPUT
5 \
0
5
•
-1
J
1\
\
l\ V
~
-15
1\
°I'T
-20
10
~
20
3.0
40
5.
TIME-j.ls
4-32
II
10 kll
500 Jl
I ~~"'...A,f
0
g
~
80
RL
0
i
0
±
Vas'" 5jJ.V at 25°C
--
~
--
~
06
~
t;
...
"
-50
08
I
w
~
o
I-04
- -
I--
-
~
w
2kH
Vs= ±15V
15IV
=e
~
~
I-ys I.
50
~o
100
0
~
~
~
±5V
Vs
w
Unnulled Input Offset
Voltage as a
Function of Temperature
Nulled Input Offset
Voltage as a
Function of Temperature
~
" -100
o"
02
Z
J:
60
0
10
20
'0
40
TEMPERTURE _
50
.0
10
70
20
ac
30
40
TEMPERATURE _
50
60
70
o
o
10
20
"c
30
40
TEMPERATURE _
50
60
70
ac
Typical Performance Curves for all Types (Unless Otherwise Specified)
8
8
Vs= ±1SV
7~
\
4
,
100
Vs=±1SV
7
•\
5
Input Bias Current as a
Function of Temperature
IlA725A and IlA725
Input Offset Current as a
Function of Temperature
IlA725C and IlA725E
Input Offset Current as a
Function of Temperature
IlA725A and IlA725
°l~
5
0 1,
0
"-
1
'-......... t---...
2
1'--
20
60
TEMPERATURE _
~
Vs=
t--
0
0
20
"
Vs= +20V
~vs ='±1SV
100
ac
140
10
20
30
40
TEMPERATURE _
4-37
50
ac
60
70
0
-60
±10~ ~
Vs == ±sJ.?
1
0
60
&.
~~
4
j\
2
6
-20
20
.0
TEMPERATURE _ "C
--.;::
100
140
p,A725
Typical Performance Curves for all Types (Cant.)
Input Bias Current as a
Function of Temperature
IlA725C and IlA725E
Supply Voltage Rejection
Ratio as a
Function of Temperature
Common Mode
Rejection Ratio as a
Function of Temperature
100
Vs = :t 1SV
m
Vs = :t 15V
~
':l
6 1-=r-=F1--+-f-+-+-9~ol---I
80
S
z
...I
i.
g 100 1-+-+---I~+-+--+~+-+-+----1
60
~
40
f---
0-
;;
~ov
~
Vs == :t 15V
~V-
Vs = ±5V
o
o
20
30
40
50
TEMPERATURE -
40
~
36
~
32
w
~
~
~
60
70
Vs
24
20
16
Vs
m
I
+
l
:t
12
o
-R\ > 2tO
- 20
20
TEMPERATURE "C
140 , - - , - - , - - - - , - - , - - - - , - - - ,
TA = 25°C
~z
115 V
"
w
80
0
''""
I I
I 60I
~
16
~
w
~
/'
12
3
0-
;;
'oz"
8"'"
5
I
>
20 l,v al t = 0
."
w
...=>
0
0-
--
10
20
'v
I-+--+---I-+--+~;: 2::~V
20
10
\
;;
;;
:i"l:
I
400
600
TIME - HAS
4-38
r-...
w
~LlNE
200
1M
30 1-+-+---i--t--tPREVIOUS Vas ~ ,/,v
~
0
of--
SUPPLY VOlTAGE-
<:
:;;
0/
0
1QOk
11
~
l/'
o
10k
':;
,/
W
o
I
1k
Stabilization Time of Input
Offset Voltage From
Power Turn On
0
//
>
100
I 100
SOURCE RESISTANCE _
TA=40"C
0
10
V
v,l: ±115 vi
Vas
000 1
20
15
Input Offset Voltage
Drift as a
Function of Time
V
AVGL
w
60
SUPPLY VOLTAGE-
,/
00 1
o
40
TA = 25"C
I
0-
o
3
0
20
l,ooo
o
140
Common Mode Input
Voltage Range as a
Function of Supply Voltage
I 10000
I
.
0
100
AVCL
1
"w
"':;
0
'0z"
TA = 25°C
~
z
;;:
100
~
Jov
0
I
"
120
TEMPERATURE - °C
~
DC Closed Loop
Voltage Gain Error as a
Function of Source Resistance
I
0
Vs = ± 5V
-60
°6LO~-_~20~-2~0-L-~60~L-,~0~0-L-,~40
TEMPERATURE _ °C
~
I I
6
~
20V
0
=>
o
~
:t
~6~0~~_~20~~2~0~--6~0~L-'~0~0-L-'~40
Common Mode Rejection
Ratio as a
Function of Supply Voltage
I I
28
...
~
Vs =
601-t--II---+~t-+-+~I-+-+---i
"C
Output Voltage Swing as a
Function of Temperature
z
80f-t--II---+~t-+-+~I-+-+---i
120
800
1000
'ON
"
TIME FROM POWER APPLICATION - MIN
JLA72S
Typical Performance Curves for all Types (Cont.)
Change In Input Offset Voltage
Due to Thermal
Shock as a Function of Time
Input Noise Voltage as a
Function of Frequency
0
10·'
~
>
e- I~;.c:.
25"C
I
J
0
VS = ~15V
PREVIOUS QUIESCENT _
1-= tTPLj
-20
40
'0
80
60
100
I
'"
..
~
g
"
10"
1k
100
is
z
~
100k
.
g
.
~
.'"
.'""'"
0:
1k
10'
z
100
10k
TAl :=,2r~
o
...z
"o.
~
!
/
10V
1V
I.
l100mY
'imj(
.
~g
.
10
100
1k
10k
FREQUENCY -
Hz
6
100k
1M
1
=1
~~"
/
,=
V
/
/
10
100
'"Iz
4-39
100k
fl
500
I"
;0
E
I 400
725Aand 725
z
2
:
~
~~~ f-:
v~
VlL[ '>~
FREOUENCY -
10k
800
FREQ COMPENSATION
AVCL
r-1k
Absolute Maximum Power
Dissipation as a
Function of Ambient Temperature
~5
10
10"
Equivalent Input Ripple
Voltage Due to Power
Supply Ripple as a
Function of Frequency
t
10
Jill
10
FREQUENCY -
[l
II FREe COMPENSATION
AVCL = 1
,7
I
10
lOOk
Ys = ± 15
TA = 25"C
t"' 1kHz·-
,
I"< 'Od"'kl:~~
Nit I 111
10
lOOk
VS -!!: 15V
EXTERNAL COMMON MODE
NOISE VOLTAGE
8
is
10kHz
-rnn'
10
I
100kHz
SOURCE RESISTANCE -
10
v
1 J.l- V
01
100
10k
Hz
4
,
'l:
10Hz
1k
Noise Figure as a Function of
Source Resistance
V
10Hz
100
FREQUENCY -
Vs = ,'5V
10dB
0
I
,
10
100k
~ti~~~~=lT~Ai+'~5:0C~~st~
Equivalent Input Noise
Voltage Due to External
Common Mode Noise as a
Function of Frequency
~
10k
Hz
Narrow Band Spot Noise
Figure Contours
25"C
ill
...I
,. ,,~mm!~
10"
10
V~ l~j5V
10
Vs
+15Y
TA _ 25"C -
10·'
FREQUENCY -
Broad Band Noise for
Various Bandwidths
~
'''''ijiBm~
I 10·'I-t-tlH-H-++++-++Ht-t-t-t+H
10·'
TIME FROM HEAT APPLICATION - S
~
:z:
;;
::Ii
-1 0
TA
=
~ 10-'
"'"
:il"z
0
~
it=:
15
is
Ves'S '"V
0
+
'Soc,
w
II
t--
Vs
.
g~
..
II
TA
Input Noise Current as a
Function of Frequency
1k
illis
300
"" ~
725 E and 725 C
'"~ '00
~
100
0
'5
45
85
105
85
TEMPERATURE -
"C
125
•
ILA725
Typical Performance Curves for all Types (Cont.)
Open Loop Voltage Gain
as a Function of
Frequency Using Recommended
Compensation Networks
Power Consumption as a
Function of Temperature
r- l"'-
160
140
~I
z
~
-
100
:- I-- "-
..
!!i •0
z
8 60
'"w
~
100.
I
~
800
E
"~
VOUT
0
VS"" ±15V
TA"" 25°C
100/~
~
=>
2 kll
47 II
J
150 pF
0.1 ~F
/
40 0
...>=>
0
/
90%
I
w
6
RL "" 2 kll
CL '" 150pF
o
RISIETljE
-400
I
-=
-=
AVi L=
to
TIME-",s
Pm numbers are shown for metal package only.
Typical Applications
Precision Amplifier
AVCL = 1000
50 Mll
90 kll
500 kll
.,N
•
10 kll
6
500 kll
eOUT
1
Pin numbers are shown for metal package only.
Characteristics
AV = 1000 = 60 dB
DC Gain Error = 0.05%
Bandwidth = 1 kHz for -0.05% error
Dill. Input Res. = 1 Mil
Typical amplifying capability
elN = 10 IJ.V on VCMI = 1.0 V
Caution: Minimize Stray Capacitance
Active Filter-Band Pass With 60 dB Gain
Active Filter Frequency Response
.001
50 Mil
~F
470 II
ex
100
A,
+.
DC)(2' C,/C.) (
2
1 )
'3
R3
f
Rs
-r
12rrfo C3
80
I
~
I
z
1-+10 -
I
80
!il
--~~--
39 !l
= R4
= R5
Gain =
R6
R2
--vv..--.,
50 k!l
+
5 k!l
+ (3..£!2.)
R3
DC GAINS = 1000
BANDWIDTH = DC TO 540 Hz
EQUIVALENT INPUT NOISE = 0.24 IlVrms
Pin numbers are shown for metal package only.
Notes
'Indicates ± 1% metal film resistors recommended for
temperature stability.
Pin numbers are shown for metal package only.
4·42
OUTPUT
f.£A725
Instrumentation Amplifier With High Common
Mode Rejection
R2
10 kll
Rl
47 kll
R6
100 kll
~--~~~--
OUTPUT
INPUTS
270 II
R3
10 kll
R5
10 kll
R7
100 kll
Rl
R6
•
R3
R4 for best CMRR
R3; R4
Rl ;R6; 10R3
R6
Gam;
R7
Pm numbers are shown for metal package only.
4-43
JlA739 • JlA749
Dual Audio Operational
Amplifier / Preamplifier
FAIRCHILO
A Schlumberger Company
Linear Products
Connection Diagram
a-Pin Metal Package
Description
The p,A739 and p,A749 consist of two identical HighGain Operational Amplifiers constructed on a single
silcon chip using the Fairchild Planar epitaxial
process. These 3-stage amplifiers use Class A PNP
transistor output stages with uncommitted collectors.
This enables a variety of loads to be employed for
general purpose applications from dc to 10 MHz,
where two high performance operational amplifiers
are required. In addition, the outputs may be wired-OR
for use as a dual comparator or they may function as
diodes in low threshold rectifying circuits such as
absolute value amplifiers, peak detectors, etc.
y+
y-
•
•
•
•
•
•
•
SINGLE OR DUAL SUPPLY OPERATION
LOW POWER CONSUMPTION
HIGH GAIN, 25,000 V IV
LARGE COMMON MODE RANGE, +11 V, -13 V
EXCELLENT GAIN STABILITY VS.
SUPPLY VOLTAGE
NO LATCH-UP
OUTPUT SHORT CIRCUIT PROTECTED
Absolute Maximum Ratings
Supply Voltage
(p,A749, p,A749C, p,A739)
(p,749D)
Internal Power Dissipation
(Note 1)
Metal Package
DIP
Differential Input Voltage
Input Voltage (Note 2)
(p,A749, p,A749C, p,A739)
(p,A749D)
Storage Temperature Range
Metal Package and
Ceramic DIP
Molded DIP
Operating Temperature Range
Pin Temperature
Metal Package, Ceramic DIP
(Soldering, 60 s)
Molded DIP (Soldering, 10 s)
Output Short Circuit Duration,
TA = 25°C (Note 3)
(Top View)
Pm 4
IS
connected to case.
Order Information
Type
Package
p,A749D
Metal
Code
5W
Part No.
p,A749DHC
Connection Diagram
14-Pin DIP
± 18 V
± 12 V
500mW
650mW
±5V
± 15 V
± 12 V
-65°C to +150°C
-55°C to +125°C
O°C to +70°C
300°C
260°C
(TOp View)
30 seconds
Order Information
Type
Package
p,A739C
Ceramic DIP
p,A739C
Molded DIP
p,A749C
Ceramic DIP
p,A749C
Molded DIP
Notes
1. Rating applies to ambient temperatures up to 70·C. Above
70·C ambient derate linearly at 8.3 mW I·C for the Ceramic
DIP.
2 For supply voltages less than ± 15 V, the absolute maximum
input voltage is equal to the supply voltage.
3. Short circuit may be to ground or either supply
4·44
Code
6A
9A
6A
9A
Part No.
p,A739DC
p,A739PC
p,A749DC
p,A749PC
J.lA739 • J.lA749
Equivalent Circuit
V+
14
R6
200 II
R5
R26
200 II
R25
9 kll
9 kll
R1
10 kll
07
R2
10 kll
R9
15 kll
R21
10 kll
R22
10 kll
027
05
025
13
1
OUTPUT
A
I
I
I
I
I
I
l
06
5 k <.
l
". 5k
026
(pA739~
only)
OUTPUT
B
I
I
I
L_
R4
1.7 kll
I
--'
3
OUTPUT
LAG A
1~~
R24
1.7kll
4
10 11
'-v-"
INPUT
LAG A
NON-INVERTING
INPUT A
V6
INVERTING
INPUT B
INVERTING
INPUT A
'-v-"
9
INPUT
LAG B
NON-INVERTING
INPUT B
Pm numbers for DIP only.
4-45
12
OUTPUT
LAG B
•
JlA739·
~A749
IlA749C, IlA749D and IlA739E
Electrical Characteristics V+ = ± 15 V, RL = 5 kn to Pin 7, TA = 25°C unless otherwise specified
Characteristic
Condition
Input Offset Voltage
RS =200 n
Input Offset Current
Input Bias Current
Input Resistance
Large Signal Voltage Gain
VOUT = ± 10 V
Positive Output Voltage Swing
Negative Output Voltage Swing
Output Resistance
f = 1.0 kHz
Common Mode Rejection Ratio
RS = 200 n, VIN = +11.5 V to -13.5 V
Supply Voltage Rejection Ratio
RS = 200 n
Input Voltage Range
Internal Power Dissipation
VOUT = 0
Supply Current
VOUT = 0
Broadband Noise Figure
Rs = 10 kn, BW = 10Hz to 10kHz
Turn On Delay (See Figure 3)
Open Loop, VIN = ± 20 mV
Turn Off Delay (See Figure 3)
Open Loop, VIN = ± 20 mV
Slew Rate (unity gain) (See Figure 2)
Cj = 0.02 IlF, Rj = 33 n, C2 = 10 pF
Channel Separation (See Figure 4)
Rs = 1 kn, f = 10 kHz
The following specifications apply for V+ = ±4.0 V, RL = 10 kn to Pin 7, TA = 25°C
Input Offset Voltage
Rs = 200 n
Input Offset Current
Input Bias Current
Supply Current
,
VOUT = 0
Internal Power Dissipation
VOUT = 0
Large Signal Voltage Gain
VOUT = ±2.0 V
Positive Output Voltage Swing
Negative Output Voltage Swing
The following specifications apply for TA = THIGH to TLOW, Vs = ± 15 V, RL = 5 kn to Pin 7.
Large Signal Voltage Gain
VOUT = ± 10 V, TA = HIGH
VOUT= ±10V,TA=LOW
Positive Output Voltage Swing
Negative Output Voltage Swing
Input Offset Voltage
Input Offset Current
Rs = 200 n
TA = HIGH
TA = LOW
Input Bias Current
TA = HIGH
TA = LOW
Input Offset Voltage Drift
RS = 200 n, +25°C:::; TA:::; HIGH
RS = 200 n, LOW:::; TA:::; +25°C
4-46
f.LA739 • f.LA749
/LA749D vee = ±6 V
/LA749C
/LA739C
RL = 10 K
Min
Typ
Max
Typ
Max
Typ
Max
Units
1.0
6.0
1.0
10
1.0
6.0
50
750
50
600
50
1000
0.3
1.5
0.3
1.5
0.3
2.0
mV
nA
/LA
Min
Min
50
150
50
150
37
150
kll
15,000
50,000
10,000
20,000
6,500
20,000
+12
+13
+4.5
+5.0
+12
+13
-15
-5.5
-6.0
-14
-15
V/V
V
V
5.0
kll
70
90
70
90
dB
-14
5.0
70
10
90
50
-13
350
+ 11
180
330
9.0
14
50
-4
2.0
100
+2.5
3.0
50
-10
4.5
9.0
14
/LV/V
V
mW
mA
2.5
2.5
2.0
dB
.2
.2
.2
/LS
.3
.3
.3
/LS
1.0
1.0
1.0
V//1-S
140
140
140
dB
6.0
1.0
6.0
50
600
50
1000
.3
1.5
300
2.5
2.5
20
15,000
+11
20
60,000
2,500
15,000
+2.5
+2.8
+2.5
+2.8
-3.6
-4.0
-3.6
-4.0
8,000
40,000
15,000
50,000
+12
+13
-14
-15
1.0
9.0
.05
1.5
.05
1.5
.3
3.0
.3
3.0
mV
nA
/1-A
mA
mW
V/V
V
V
V/V
V/V
V
V
mV
/LA
/1-A
/1-A
/1-A
/1-V /oC
/LV/oC
3.0
3.0
4-47
•
J.LA739 • J.LA749
j.tA749C, j.tA749D and j.tA739C
Electrical Characteristics (Cont.)
V+ = ± 15 V, RL = 5 kfl to Pin 7, TA = 25°C unless otherwise specified
Characteristics
Condition
~
+25°C
Input Offset Current Drift
Input Bias Current Drift
TA
LOW
~
TA
~
+25°C
LOW
~
TA
~
HIGH
VOUT = 0, TA =HIGH
Supply Current
= LOW
= 0, TA = HIGH
VOUT = 0, TA = LOW
VOUT = 0, TA
VOUT
Internal Power Dissipation
The following specifications apply for THIGH to T LOW, Vs = ± 4.5 V, RL = 10 kfl to Pin 7.
Input Offset Voltage
Rs = 200 fl
Input Offset Current
VOUT = ±2.0 V, TA =
Large Signal Voltage Gain
VOUT = ±2.0 V, TA =
Positive Output Voltage Swing
Negative Output Voltage Swing
Typical Performance Curves for j.tA749C and j.tA739C
Open Loop Frequency
Response Using
Recommended
Compensation Networks
Closed Loop Gain as a
Function of Frequency
90
70 rT11T-rrTTrTTr"--rr=v+:--o -::,,,,"'''''V
!II
ITA ~ 25°C
==
i-t+fi''-r'"rnA-i'i-r;.:.:.r-t*lAL 5kfl
!II
.0 1-ttH-+Htf-+-t+tt-f-++W~Hf1-1
~
TO PIN 7
I
~
".
~
.
301-++H-+H+H--++++-H-+l+-lt-1tHl-l
o
~
! 'O~~~~~~#-~~~~~
r-.
60
".
~
.
~
o
o
~
c, -
300 pF. A1 - 470 ,
R1 = 150
C, =001 ",F,R, =33£
0 C, = 0 1 ",F, R1 = 4.7 n
c,
II!
o
1 -120
Y+ - ;+-15 v
TA '" 25°C
AL "'" 5kn
PIN 7
o
1k
10 k
100 k
FREQUENCY -
Hz
TO PIN 7
100 k
'M
'OM
1M
=
Av =0 dB,C,
"..
'~~-H~~,+i~q-++#-+-++~
i~
eo
~ ~~-H~~~~-t+H~-ttH~
0.1 /IF, Rl ""4.7 n
Hz
=':-!,.
M
Hz
2 ••
v+ = :±-15 v
RL=5kHTO PIN 7
'\
,.S
,"~
'.2
.~
I'
••
~
.... ~
BANDWIDTH
-2.
-
SLEW RATE
-...[
••
•...
10 M
FREQUENCY -
eo
o. ~ !::
••:LU"-:":-..!..l.J.'-::,-=-.:-'...llJ.::,.'=".::'-.=:',:;"M
25°C
H-t+H-+-++H-++++- TO PIN 7
4·48
!~_Al""'50ttli:rt~:ma
c, R~!~;~' h
20 dB,
Change of AC Characteristics
With Temperature
::t15 V
==
AL == 5kH
'50
it Av
FREQUENCY -
v+
!II
=
60 dB, C, "" 300 pF,
Av "" 40 dB, C, = 0 001 I-'F,
i:I
:E
=
H-ttt-+-t-ffi---fRl =470 nf1tt-b"I>f9
FREQUENCY -
Open Loop Phase Shift
Without Compensation
P
= 1000 pF,
~ 50~~~~~~~~~T~'~2~'~'CJ
20
...
o
r-.
30
Hz
-60
1\"--
i'
'00
i"-
~(.~."-«
:;;
-30
FREQUENCY -
.o~~+Jl-
~OoO~~~q
+"'' .'. <0
. ~~
r--
Output Capability as a
Function of
Frequency and Compensation
w 100 r-rm--.-rrnr-r-rrn-rr-rv
",+-.-+,"","".V""'
s.
TEMPERATURE _ °C
....
100
140
p,A739 • p,A749
~749D
~A749C
RL
Typ
Min
vee = ±6 V
Typ
Min
Max
~A739C
= 10 K
Max
Min
Typ
Max
Units
.5
nA/oe
2.0
nA/oe
4.0
nA/oe
10
mA
10
mA
100
mW
200
mW
1.5
7.0
mV
50
1,000
nA
VIV
VIV
V
V
8,000
15,000
+2.5
+2.8
-3.6
-4.0
Typical Performance Curves for
Open Loop Frequency
Response Using
Recommended
Compensation Networks
Closed Loop Gain as a
Function of Frequency
70
i ..
[[ [ [ [ [i r
I
~
~
so
.. co
~
Ii!
o~
30
i
.0
U
0
....
I
Y+ = ±IV
TA '" 25°C
RL
= 10kll
!Il
I
'.
t'
"w
"
\
II
i
\
10
30
.0
;;!
10
Z
\
~
100 k
1M
FREQUENCY -
10 M
'. '"
~
~
~
"
10 k
1M
100 M
"t!
g.
9
~
o
o
1-4
V
5
5
.s=~
/
20
It
V '"
Vs _+4V
1/
"'v"-
1.
2
LOAD RESISTANCE - kfl
Hz
Tl
25 0
h
ai-- RL TO PIN4
•
•
t
a
~
I
1.
1M
100 •
Typical Output Voltage
As a Function of
Supply Voltage
f-
/
25
11- -
10.
i/
30
~
~ ~;-
FREQUENCY -
~
I
I
.~
~
,.
01
100
... "'"
-.;.
~~
0.'
,
~\
~~~-
05
Hz
;;k ~
~~T~;1~4
..
V
10 M
',,-.~
0
!\
oI- ~~ ~ ~~zv RMS
I
'
on
100 k
z co
~ 35
I
\'.!,
CI
> 10
Open Loop Voltage Gain
As a Function of
Load Resistance
45 ......
THD-05'A1
~
\
5
SUPPLY VOLTAGE-
.
.."
.."
'" '"
FREOUENCY -
~
RL
~
0
I
1k
Hz
Open Loop Voltage Gain
As a Function of
Supply Voltage
~
,
100 M
V+ =- ±IV
r" = 25 G e
10ktl
50
>
I
~ '0
D
'~
I
on
-10
10 k
~..
""'!-fI: .~~
40
;;!
'.
q~
50
"iii
TA=25°C
RL=10kll
~
~~,...
•
70
Z
cl,1 ~ ~..J. ~J.~, ~ ~ ~l
-10
1k
10
Y+ - ±6V
ao
:c a.
c~I!~.J~~~!R,I =I~ n
[1111111
Output Voltage Swing as a
Function of Frequency for
Various Compensation Networks
90
C,'~,..I.~.I~~ =1.~lr\
•
~A749D
~
,..C
~\.-..,'lSl.
~'J.II.'f.\.'
..........:
./.
....~
~
~
I--- I--
4
,.
0
20
SUPPLY VOLTAGE -
,.
~y
4·49
-.-----~.-.~
~-.--
-
-:.-,,----.---~
JlA739· JlA749
Typical Performance Curves for ,uA749D (Cont.)
Total Supply Current
As a Function of
Supply Voltage
Open Loop Gain
As a Function of
Temperature
Total Power Dissipation
As a Function of
Supply Voltage and Load
300
16
vo'_-o I
"Iz
r----.
60
"
"'
E
Nvr--..
w
0
~
~
~
*201.;1)1;:
0
40
f--
~
0
3
~
0
Rc- 10k!l
2{)
v,
Oc
24 kJl
12
---
r---:;t-- r-
u
V
~
iii
V
~
...-...-
l'
g
v,
'. V
oL--J~-l
o
~
w
~
TEMPERATURE _
0
TO
4
TA =25°C
/
~
E
I 2••
1
I - ---t\-~'()~
I - -r;;: -20kJl
.p/
---
0
c
~
~
100
11
V
V
..- r--
~ >--....-: l:::::== Fo-
o F-
V;~_10'Y
~ t--I
4
10
V
/'
<-~X
V
"L
. / ~'v:-9
£
in
!!!
I
ro
c
r-- ~~ Pt~
f--vo=ov
z
~~~~~
__- L__~__~__~~
~
10
-
/f
1
1,_-- 7"'"
?
o.'c'
10
~
-6V_
R, - 51 kJl
Vc
I
14 r-TA-25QC
RL TQPIN4
12
10
SUPPLY VOLTAGE _
SUPPLY VOLTAGE - ±V
-.-v
Typical Performance Curves for ,uA749 and ,uA749C
Common Mode Range
As a Function of
Supply Voltage
Input Noise Voltage as a
Function of Frequency
Input Noise Current as a
Function of Frequency
10.
10.
V+ = ±15 V
50
I"w
Rs = 100 n
~
"~
"~
~
Z
W
".
w
-
101-50
~
~
li>
i
TA = 25"C
.ili
~
~
~
w
C
.,W
0
~
z
<;
z
""c
"'~
0
U
4
12
10
SUPPLYVQLTAGE-
10
"'<;z
05
ili"'
100
10
-v
10k
1k
FREQUENCY -
100 k
Hz
......
1.0
..
r--r--.
1
10
10'
1k
10k
FREQUENCY - Hz
Open Loop 180· Phase
Shift Frequency as a
Function of
Supply Voltage
Absolute Maximum Power
Dissipation as a
Function of Temperature
10
5'
0
W
Common Mode Range as a
Function of
Supply Voltage
800
I
TA "'" 25°C
f--+-+-I'--t-+-+--tRLTO PIN5k!l
7
--
=
I
>
I
w
"z~
w
0
~
\
2
o
>
V
w
o
~
z
74"
749C
0
o
""oo
1
0
-60
1
-20
20
60
AMBIENT TEMPERATURE -
'"
"C
140
SUPPLY VOLTAGE - V
4-50
~'±\!'v
As = 100 n
TA = 25°C
:J
0.1
10
v1
5'
SUPPLY YOl T AGE -
:tv
100 k
JlA 739 • JlA 749
Typical Performance Curves for #A749 and IlA749C (Cant.)
Typical Output Voltage as a
Function of
Supply Voltage
32
T.' = ,,·b
>
.
".
!:i
. ,.
2•
'/'
>
,,"""
:0
~
AV
:0
0
"~
..
YOUT = 0
~II:
o
10
12
14
SUPPLY VOLTAGE -
16
12~-+--t--~~9---+--t--1
:0
u
>-
t
o
iil
~
e
~
~
2
I
.~
"~
.g
.,..'>-
'fr1--~
'
16r-_'+'T_O__PlrN_'~r-~__~
~
.
I
z
~
.;
~
Total Supply Current as a
Function of
Supply Voltage
TA == 25°C
~
~V
....~
0
/ /'
,.
t-- AL TO PIN 7
I
Open Loop Voltage Gain as a
Function of
Load Resistance
~
°0~-~-~~1~0-·:'~2-~-~~'.·
18
±V
LOAD RESIST ANeE -
Total Power Dissipation as a
Function of Supply
Voltage and Load
SUPPLY VOLTAGE -
kn
Open Loop Voltage Gain as a
Function of
Supply Voltage
150
100
7'r-~1-~~~~~-4--+-~
o
z ,.0
..
eo
~~
40 ,
>
o
,.
10-
~ 120
§" 100
o
~
z
~
o
SUPPLY VOLTAGE -:tV
Y+"'" :t15 y
~ 180
- '00
TA = HOC
~ '25~-t--+--t-+~~'f--t--l
.
200
YOUT = 05 Vrms
Your = 0 5 Vrms
1 kHz
.=
AL TO PIN 7
~
g
•
Open Loop Gain as a
Function of Temperature
175r--,--,-..,..--r-.,--..---.
~
:tV
-
AL TO PIN 7
1
'"
."
!'·~·:J'fJ
If(",;r::;.. - ~
0
....
~
~
RL-25kn
20
-20
18
r - I-
A
.
0
16
1
~'l>
0
20
1
'00
'40
TEMPERATURE _ °C
SUPPLY VOLTAGE -!:.Y
Typical Performance Curves for #A739C
Input Offset Current and
Bias Current as
Functions of Temperature
05
\
00
'1
I
:::
1\
o'
§
\
"-
70.
1
1,
....
o
I
,......
r-BIAS CURRENT
-..1. J"'""-- ...i..
20
1\
00
TEMPERATURE _ °C
100
25°C
~
10-23 1.-11-hf+--f-Hf+-++I++-+-++HH
~
~
10-24 Hl-hf+--+"N:I+-++I++-+-++HH
.
II:
~ 10-25 Hl-hf+--f-Hf+-++I++-+-++HH
OFFSET CURRENT
\
±15 v
100 n
!
n-
I
Ys
As
TA
~ 10-221ij~~aiiii~~i~
~
!!
749C
-20
_
!!i
02
U
Input Noise Current as a
Function of Frequency
"~ ., 10-21~Im~~i~~~~f]~~
~15V_
~~ ;I~;n
/'
~II:
Input Noise Voltage as a
Function of Frequency
~ ~Ef~~f3~~~~~~3f~
I
~ 'O-26~10
:I
140
FREQUENCY -
4·51
Hz
100
1k
FREQUENCY -
10k
Hz
lOOk
J,LA739 • J,LA749
Typical Performance Curves for ILA739C (Cont.)
Wide Band Input Noise
Voltage as a
Function of Temperature
Wide Band Input Noise
Current as a
Function of Temperature
Common Mode Range as a
Function of
Supply Voltage
••• ,.--,--,--..,...--r---.--,----.
BW
-==
20 TO 50 kHz
I--+-+-+--vsAs .", 100
±15 Y
n
-
=
1.
.ill
.
".
'50
I
,~
u
!!
0
z
10
20
30
40
50
60
50
10
70
20
30
40
50
80
70
TEMPERATURE -"C
TEMPERATURE _ "C
Typical Output Voltage as a
Function of
Supply Voltage
SUPPLY VOLTAGE -
Output Capability as a
Function of
Supply Voltage
V
Total Supply Current as a
Function of
Supply Voltage
Yo = 0
TA = 25"C
~
,.~_RL+T_O_P~'N~7_+
I
>
~
I
~
u
"z
~
12r--+--b~~~.
iiii
I
~
..
·4~~--~--'~.--~"~-'~4--~'~.~'.·
SUPPLY VOLTAGE -
SUPPLY VOLTAGE -
tV
Total Power DisSipation as a
Function of Supply
Voltage and Load
•••
z
2
i
z
.
~ 15k
.~I--+-+--~7t.
ii ••• I---l---l7~ffL,j,L-+-+---i
I
~ '~I-~~~~+--I--+-+---i
10
12
SUPPLY VOLTAGE -
vol •••
14
±V
1.
18
"~
10 k
t.,_
....... i-"'"
-:::
-
-
Vs '" :t1S Y
~~ ~OOk~=rms_
3D
AL - 10 kH
RL
RL
10
5 kU
12
4-52
RL TO GND
........
r---....
~
,. •
3 kU
SUPPLY VOLTAGE -
•
.. •
~
••
•4
~:;02~~~
14
tV
16
18
±Y
Open Loop Gain as a
Function of Temperature
40.
1= 10kHz
•••
.....
1--+-+----11E
I
SUPPLY VOLTAGE -
Open Loop Voltage Gain as a
Function of
Supply Voltage
Yo = 0
TA = 25°C -l--+-4-h~v---l
RL TO PIN 7
~~-~-,~.-~,~.-,~.-~,.~~,.
tV
AL
W
20
.........
t-
",1 10 kll
~
~
~
TEMPERATURE -"C
60
rn
J.LA739 • J.LA749
Typical Performance Curves for
~739C
(Cont.)
Input Offset Current and
Bias Current as a
Function of Temperature
..•
... .........
c
i
Vs=±1SV
........
·'<4e
~~",.
03
~
-r--
5.2
.,
I-- '=== 0,..
10
20
RENT
30
40
50
10
70
TEMPERATURE _ °C
•
Typical Applications
Stereo Phono Preamplifier-RIAA Equalized
+30 V
0.0022 "F
0.1 "F
0.0022 "F
t
470 kll
150 kll
150 kll
9
5 "F/25 V
OUTPUT A -
5 "F/25 V
....-_tl-:-+....~~
>1~3.....+-Ifo-_""'- OUTPUT B
-=- 1 Mll
lMll
~¥~.' :::
kll 11.2kll
INPUTA
INPUTB
Typical Performance
Gain 40 dB at 1 kHz, RIAA equalized
Input overload paint, 80 mV rms
Noise Level, 2 p.V referred to Input
Signal to noise ratio, 74 dB below 10 mW
Channel separation @ 1 kHz, 80 dB
4·53
-=-
~"""-I'v---'
f.LA 739 • f.LA 7 49
Typical Applications (Cont.)
Stereo Tape Preamplifier
1.2 kll
1.5M
I
TAPE HEAD
80
~~
V+ = 12 V
100~F/15V
70
r-....
III
5
~F/9
'"
V
>----------lr--
Z
;;:
60
~ i'.
CI
w
CI
750 kll
~
10 kll
50
o
>
5000
pF
15 kll
,,~
40
4000 pF
100
Mil
TO
SIDE B
1000
10,000 20,000
FREQUENCY - kHz
1.2
OPTIONAL FEEDBACK
TONE COMPENSATION
Typical Performance
Gain at 1 kHz
Output Voltage Swing
Power Consumpllon
":;"
4·54
60 dB
2.8 V rms
30mW
J-LA741
I=AIRCHIL.O
Operational Amplifier
A Schlumberger Company
Linear Products
Connection Diagram
S-Pin Metal Package
Description
The ~A741 is a high performance Monolithic
Operational Amplifier constructed using the Fairchild
Planar epitaxial process. It is intended for a wide
range of analog applications. High common mode
voltage range and absence of latch-Up tendencies
make the ~A741 ideal for use as a voltage follower.
The high gain and wide range of operating voltage
provides superior performance in integrator, summing
amplifier, and general feedback applications.
NC
>-~DOUT
-IN
•
•
•
•
NO FREQUENCY COMPENSATION REQUIRED
SHORT-CIRCUIT PROTECTION
OFFSET VOLTAGE NULL CAPABILITY
LARGE COMMON MODE AND DIFFERENTIAL
VOLTAGE RANGES
• LOW POWER CONSUMPTION
• NO LATCH-UP
(Top View)
PIn 4 connected to case
Order Information
Type
Package
~A741
Metal
~A741A
Metal
~A741C
Metal
~A741E
Metal
Connection Diagram
1o-Pln Flatpak
NC
-OFFSET
NULL
1 •
10
2
9
NC
+IN
v-
NC
8
-IN
OUT
6
Code
3F
3F
Part No.
5W
5W
5W
5W
~A741HM
~A741AHM
~A741HC
~A741EHC
+OFFSET
NULL
(Top View)
Order Information
Type
Package
~A741
Flatpak
~A741A
Flatpak
Code
Connection Diagram
S-Pin DIP
v+
4
5
•
v-
Part No.
~A741FM
~A741AFM
-OFFSET
NULL
NC
-IN
v+
+IN
OUT
+OFFSET
NULL
v-
(Top View)
Order Information
Type
Package
~A741C
Molded DIP
~A741C
Ceramic DIP
Code
Part No.
9T
6T
~A741TC
~A741RC
4·55
------
--------
/lA741
Absolute Maximum Ratings
Supply Voltage
~A741A,~A741,~A741E
~A741C
Internal Power Dissipation
(Note 1)
Metal Package
DIP
Flatpak
Differential Input Voltage
Input Voltage (Note 2)
Storage Temperature Range
Metal Package and Flatpak
DIP
Operating Temperature Range
Military (~A741A, ~A741)
-55°C to +125°C
Commercial (~A741E, ~A741C) O°C to +70°C
Pin Temperature (Soldering 60 s)
Metal Package, Flatpak, and
Ceramic DIP
Molded DIP (10 s)
Output Short Circuit Duration
(Note 3)
Indefinite
±22 V
± 18 V
500MW
310 mW
570mW
±30 V
± 15 V
-65°C to +150°C
-55°C to +125°C
~--------------------------------------------------------------------------------Equivalent Circuit
INVERTING INPUT
r1~-------r----~--------~----------~---'--------------------~~V+
NON·
INVERTING
INPUT
R6
27
n
OUTPUT
R7
22 n
OFFSET
NULL
OFFSET
NULL
Notes
2 For supply voltages less than ± 15 V, the absolute maximum
Input voltage is equal to the supply voltage.
3 Short circUit may be to ground or either supply Rating applies
to +125·e case temperature or 75·e ambient temperature.
1 Rating applies to ambient temperatures up to 70·C. Above
70·e ambient derate linearly at 6 3 mW /·e for the metal
package, 7.1 mW /·C for the flatpak, and 5.6 mW /·e for
the DIP
4·56
J-LA741
/.LA741 and /.LA741C
Electrical Characteristics
Vs = ± 15 V, TA = 25°C unless otherwise specified
/.LA741C
/.LA741
Typ
Max
Typ
Max
Unit
1.0
5.0
2.0
6.0
mV
Input Offset Current
20
200
20
200
nA
Input Bias Current
80
500
80
500
nA
30
150
30
150
/.LV/V
Characteristic
Condition
Input Offset Voltage
RS S
Power Supply Rejection Ratio
Vs
Vs
Min
10 kQ
= +10,
= +20,
-20
-10 V, Rs
= 50 Q
Min
2.0
Mil
Input Capacitance
1.4
1.4
pF
Offset Voltage
Adjustment Range
±15
± 15
mV
±12
±13
V
70
90
dB
25
mA
20k
200k
Input Resistance
.3
2.0
.3
Input Voltage Range
Common Mode
Rejection Ratio
Rs S
10 kQ
Output Short Circuit Current
25
Large Signal Voltage Gain
RL 2: 2 kQ, VOUT
=±
10 V
50k
200k
75
Output Resistance
Output Voltage Swing
75
Q
V
RL 2: 10 kQ
±12
±14
RL 2: 2 kQ
±10
±13
V
Supply Current
1.7
2.8
1.7
2.8
mA
Power Consumption
50
85
50
85
mW
Transient
Response
(Unity Gain)
IRise Time
IOvershoot
VIN = 20 mV, RL
CL S 100 pF
= 2 kQ,
Bandwidth (Note 4)
Slew Rate
RL 2: 2 kQ
Notes
4 Calculated value from BW(MHz)
=
035
Rise Time (I's)
5 All VCC = 15 V for I'A741 and I'A741C
6. Maximum supply current for all devices
25°C = 28 rnA
125°C = 2.5 rnA
-55°C = 33 rnA
4·57
.3
.3
/.LS
5.0
5.0
%
1.0
1.0
MHz
.5
.5
V//.Ls
•
J.LA741
ILA741 and ILA741C
Electrical Characteristics (Cant.)
The following specifications apply over the range of -55 ° C :::; TA :::; 125 ° C
for ILA741 , O°C -<: TA -<: 70°C for ILA741C
ILA741
Characteristic
Input Offset Voltage
Condition
Min
Typ
Max
ILA741C
Typ
Min
Max
7.5
RS:::; 10 kf!
1.0
6.0
= +125°C
TA = -55°C
7.0
200
85
500
TA
= +125°C
TA = -55°C
TA
Input Voltage Range
Common Mode
Rejection Ratio
Rs:::; 10 kf!
nA
Output Voltage Swing
Large Signal Voltage Gain
Supply Current
Power Consumption
.5
ILA
.3
1.5
±13
ILA
V
70
90
dB
± 15
Vs
Vs
= +10,
= +20,
RL
~
RL
~
-20;
-10 V, RS
30
= 50 f!
10 kf!
± 12
± 14
2 kf!
±10
± 13
= 2 kf!, VOUT = ±
TA = +125°C
TA = -55°C
TA = +125°C
TA = -55°C
RL
10 V
Notes
0.35
4 Calculated value from BW(MHz) = Rise Time (I's)
5. All VCC = 15 V for I'A741 and I'A741C.
6. Maximum supply current for all devices
25°C = 28 rnA
125°C = 2.5 rnA
-55°C = 33 rnA
4·58
nA
.03
± 12
Adjustment for Input Offset
Voltage
Supply Voltage
Rejection Ratio
nA
nA
800
Input Bias Current
mV
mV
300
Input Offset Current
Unit
± 15
150
mV
ILV / V
V
±10
25k
±13
V
15k
1.5
2.5
2.0
3.3
mA
45
75
mW
60
100
mW
mA
JlA741
JlA741A and JlA741E
Electrical Characteristics
Vs = ± 15 V, TA = 25°C unless otherwise specified.
JlA741A/E
Characteristic
Condition
Input Offset Voltage
Rs
S;
Min
50 Il
Typ
Max
0.8
3.0
mV
15
JlV/oC
30
nA
Average Input Offset Voltage Drift
Input Offset Current
3.0
Average Input Offset Current Drift
Input Bias Current
Vs
RS
Power Supply Rejection Ratio
= +10,
= 50 Il
-20; Vs
= +20 V,
-10 V,
Output Short Circuit Current
10
= ±20 V
Vs = ±20 V
Vs = ± 20 V, RL = 2 kll,
VOUT = ± 15 V
Power Consumption
Vs
Input Impedance
Large Signal Voltage Gain
Transient Response
(Unity Gain)
0.5
nA/oC
30
80
nA
15
50
JlV/V
25
40
mA
80
150
6.0
Mil
50
200
V/mV
0.25
0.8
I Overshoot
6.0
20
Slew Rate (Unity Gain)
VIN
=±
10 V
The following specifications apply over the range of -55°C
and DoC S; TA S; 70°C for the 741E.
S;
TA
S;
mW
1.0
I Rise Time
Bandwidth (Note 4)
Unit
JlS
%
.437
1.5
MHz
0.3
0.7
V/Jls
125°C for the 741A,
Input Offset Voltage
4.0
mV
Input Offset Current
70
nA
Input Bias Current
210
Common Mode Rejection Ratio
Adjustment For Input Offset Voltage
Vs
Vs
= ±20 V, VIN = ±
= ±20 V
15 V, RS
= 50 Il
80
= ±20 V
JlA741A
mA
I-55°C
165
mW
I +125°C
135
mW
150
JlA741E
Input Impedance
Vs
=
Output Voltage Swing
Vs
= ±20 V
±20 V
IRL = 10 kll
IRL = 2 kll
Vs = ± 20 V, RL
VOUT = ± 15 V
Large Signal Voltage Gain
Vs = ± 5 V, RL
VOUT = ±2 V
= 2 kll,
= 2 kll,
Notes
4. Calculated value from' BW(MHz)
=
0.35
Rise Time (I's)
5. All VCC = 15 V for I'A741 and I'A741C
6. Maximum supply current for all devices
25°C = 28 rnA
125°C = 25 rnA
-55°C = 33 rnA
4-59
mV
40
10
Vs
nA
dB
10
Output Short Circuit Current
Power Consumption
95
mW
0.5
Mil
±16
V
±15
V
32
V/mV
V/mV
10
V/mV
•
JLA741
Typical Performance Curves for I'A741A and I'A741
Open Loop Voltage Gain as a
Function of
Supply Voltage
"5
~
/
'1105
>
~
~ 100
." ..
~
"
!
3.
~
-5S0C $: TA
-ALl2kll
~
16
8.
~
8
~
12
2.
18
/'
./
-5SoC i= TA
+125 C
S;
Q
11
/'
"
/'
24
6 12
SUPPLY VOLTAGE -
•
.. ,
+12SoC
32
3
Input Common Mode
Voltage as a
Function of Supply Voltage
/'
5 2•
""
V
90
I
~ 28
"'~
I
§!
••
~A =' ..·b
"0
Output Voltage Swing as a
Function of
Supply Voltage
~ 12
'"~
/'
/
•
1
~>
Y
/
8
.. •
/'"
~
V
..o~ 4/
o
/'
z
2
4
•
,.
10
±V
SUPPLY VOLTAGE -
" •
2.
,.
~v
2.
15
'v
SUPPLY VOLTAGE -
Typical Performance Curves for I'A741E and I'A741C
Open Loop Voltage Gain as a
Function of
Supply Voltage
..
,
TA
'"
C
"~
e
4
75
7.
o
2
4
6
8
10
12
14
SUPPLY VOLTAGE -
16
18
20
-:':Y
•
•
/
V
./
20
15
10
SUPPLY VOLTAGE -
2/
•
'
C
o
2.
t>---....- -...-VOUT
0..
I
... 12
~
8
I
I
I
RL
..
~
~
70
RISE I'ME-
~
z
..~
Vs - ±15 V
TA eo 25°C
RL '" 2 kl!
-
o
CL - 100 pF
05
10
TIME -
15
20
"
25
,,8
'\
~ 60
UJ 50
'o"
Ys - 1±15 V
TA = 25°C
'\.
80
.. 4
r-=: ,...
'\
•
30
'\
•
2
•
10
100
1 k
10 k
FREQUENCY -
4-60
2.
tV
,
I .0
24
16
,.
Common Mode Rejection
Ratio as a
Function of Frequency
28
~
,.
SUPPLY VOLTAGE -
±V
Transient Response
Test Circuit
Transient Response
/'
/
/'
2
8
DOC ',; TA S t70°C
/'
•
V
C_
V
0
0
Q
L
8
> 8.
.
,
~:c~ ~ ~~I::O +10
2
V
85
.
•
V
/
z
C
." ••
25°C
~
~
.5
I
~
Input Common Mode
Voltage Range as a
Function of Supply Voltage
Output Voltage Swing as a
Function of
Supply Voltage
100 k
Hz
1 M 10 M
f..LA741
Typical Performance Curves for ,uA 7 41 E and ,uA 7 41 C (Cont.)
Frequency Characteristics as a
Function of
Supply Voltage
Voltage Follower Large
Signal Pulse Response
Voltage Offset Null Circuit
14.---,---,---,---,---,----,
I
w
=>
w
~
;!
~ 10r---+---1-~~~~~~==~
,r=ta:t:ttttD
'-OUTPUT
2
f--+-,,'-/~-t---It-t+--\-++-+--l
6> 0f--+.~~--~~-+~--t-~-1
J
~
INPUT_i
\
v-8f--t-+-++-+-+-t-jI--H
06~5---L--~,0--~--~,5~~--~20
SUPPLY VOLTAGE -
-10 '-~O-;'':-O-;!;20:-:'':-O-::40:-:5'=0---:''':-:''=0-:!'':-:!90
=V
TIME -!-,S
•
Typical Performance Curves for ,uA741A, ,uA741 , ,uA741E and ,uA741C
Power Consumption as a
Function of
Supply Voltage
100
T, _
3t
E
I
"
z
0
~
~
Z
0
"'"
"
/'
40
~
li' 20
o
vV"
5
V
/
10,
2~OC /
10, k
/
10,
z
vs
"-
010,
~
w
o
~
~
g
V
10
20
15
+25a~-
5
"-
,
10
"-
0
"-
10
100
1 k
10 k
FREQUENCY -
"- \
100 k
1 M
TA
~
"
10
100
1 k
10 k
100 k
1 M
10 M
Hz
Output Resistance as a
Function of Frequency
1 00
25°C
"0 r-rn'-;-TTrr-'-TT"1T,-,-rrr,
R"
e
~
\
FREQUENCY -
10M
50
Vs V
TA -= +25 Q C
-180
10 M
Hz
Input Resistance and Input
Capacitance as a
Function of Frequency
~
~'5
\
-13 5
10-
~V
Input Offset Current as a
Function of
Supply Voltage
0
l ~ ~ 151 v
TA'=
1
SUPPLY VOLTAGE -
Open Loop Phase
Response as a
Function of Frequency
Open Loop Voltage Gain as a
Function of Frequency
500
f--H-1+-+-tt+t-+++*++Ht-1
'00
f--H-1+-+-tt+t-+++*++Ht-1
40
~
"~ V
1 M
1
=>
'00 f-H1+-+-++++-+++-++-++I-++-l
30
C"
o
1
100 k
~
it
200
f-H1+-+-++++-+++-++-++l-t\I/y
20
~
10
5
10
20
15
SUPPLY VOLTAGE -
-t-V
10k
100
0
1 k
10k
FREQUENCY -
4-61
100 k
Hz
1 M
FREQUENCY -
Hz
IlA741
Typical Performance Curves for ILA741A, ILA741 , ILA741E and ILA741C (Cont.)
Output Voltage Swing as a
Function of
Load Resistance
26
T,
1
~
22
2
~
o
600
0
R, - 10 kll
8
16
6
~
4
2
~
1
I
,
2
z
o
400
~
300
ffi
, J
05
10
50
20
10
r-'Ok
, k
'00
k!l
o
, M
100 k
FREQUENCY -
25
10-15 f-t+fP'I-o:Htt-++ftt-++Itt~
a~
w
~
~
10- 161--t+1+-+-++++-+-H*++Ht-l
g
~ 10
17
f-t+I+-+++++-++ftt-++Itt-
~
10-18
L-.l...LU-..L.LJ..LL..J......LJ.J..J...-'---"-l.ll_
10
100
1 k
10 k
FREQUENCY -
(;
~
~
{/j
10- 24
10 -25
:l
z~ 10-'"
~~ma=t~
f-H-H-+-++tt--t--titt-++t-t+-i
.~~fH~;f~~~~E;~EB~
10
100 k
100
Hz
1 k
10 k
FREQUENCY -
l25
Broadband Noise for
Various Bandwidths
f-t+I'k:-+-t+tt--t-+ftt-++H+-i
10-23
105
85
65
AMBIENT TEMPERATURE
f-H-H-+-t+tt--t--titt-++t-t+-i
I 10-n
45
Hz
Input Noise Current as a
Function of Frequency
~
~
"
~
0
02
w
~
~
200
~
W
IlA741E AND
J. 36
.......
25"C
24
~
Output Voltage Swing as a
Function of Frequency
I----
v, - le,,1 v
> 26
Absolute Maximum Power
Dissipation as a
Function of
Ambient Temperature
10
~-
0
10
10-100
~
I
w
V
Uz
1/
10.10 kHz
;o.i kH~ V
1
'"
"
z
"'o ,
0
~
~
100 k
1
10'
1 k
10k
SOURCE RESISTANCE -
Hz
100 k
q
Typical Performance Curves for ILA741A and ILA741
Input Bias Current as a
Function of
Ambient Temperature
Output Short-Circuit
Current as a
Function of
Ambient Temperature
Input Resistance as a
Function of
Ambient Temperature
200
'00
v,
·15 V
"'EI 3.1"'
50
0
35
,I, v
vs
30
....",
ffi
v
'00
0
0"'-
r-- r-- I-
30
-
0
-60
-20
20
60
TEMPERATURE _ "C
'00
140
"
I--"
~
I ....
-60
I'-,
'-'
"-
~
VV
, 0
1"-
~ 25
~
20
t:--..
[j
v-
~
015
ili
-20
20
60
TEMPERATURE _ °C
4·62
'00
'40
10
-60
-20
20
60
TEMPERATURE _ °C
100
"'
140
~A741
Typical Performance Curves for
Input Offset Current as a
Function of
Ambient Temperature
,
and
~A741
(Cont.)
Power Consumption as a
Function of
Ambient Temperature
,J. y
Ys 1=
~A741A
Frequency Characteristics as a
Function of
Ambient Temperature
•
Vs==±20Y
I Vs =
'20
2
2
•
.......
·•
r-- r--..
•
\
~
,
r--. r--. t-
2
•
2D
-20
100
140
..
-
Typical Performance Curves for
Input Bias Current as a
Function of
Ambient Temperature
~A741E
2.
-2D
....... ....
••
100
BO
140
and
-
~
!
-
t-- r--
20
•
10
20
30
I--
40
50
60
70
10
~
I
z
~
~
.•
.• --
30
40
50
60
r-....
I"'- ..........
2
10
20
30
40
50
TEMPERATURE _ DC
60
70
10
10
20
30
20
100
140
~c
r--
•
-
40
50
TEMPERATURE _ DC
4-63
30
40
50
80
'00
.......
70
60
70
"C
.........
/
I-:;: :::::-
V
V
SLEW RATE
~o~~
~ol
•••
...
/
Vs = ±15 v
......
III
•
•
I I
Frequency Characteristics as a
Function of
Ambient Temperature
10.
4
~8D
0.
•
".
..........
7
........
TEMPERATURE -
.........
8•
•
10
•
•
r-- t--
..........
-c
Output Short Circuit Current as a
Function of
Ambient Temperature
Vs==±20V
.........
20
TEMPERATURE -
Power Consumption as a
Function of
Ambient Temperature
e.
,
TEMPERATURE _ DC
'00
.........
•
•
•
2.
-2.
-BO
Vs == ±15 V
- -
I
!<
DO
Input Offset Current as a
Function of
Ambient Temperature
•
c-Ys
•
.-•
~ 80
iii
I ('''I~
~A741C
'15 V
. ,.
oo~
<9~",
TEMPERATURE -
Input Resistance as a
Function of
Ambient Temperature
Vs == "t15 V
~ 80
~ P" c~1
;-
TEMPERATURE _ DC
TEMPERATURE _ DC
G
s\t.'i4
<~L~w"lTE
•
BO
'00
-- --
•
II)~
~
~"t:
r--. r-....
•
t15 V
~r~o~:-
o
fz
10
20
30
40
50
TEMPERATURE _ °C
eo
70
J-LA747
Dual
Operational Amplifier
FAIRCHILO
A Schlumberger Company
Linear Products
Description
The /-tA747 is a pair of high performance Monolithic
Operational Amplifiers constructed using the Fairchild
Planar epitaxial process. They are intended for a wide
range of analog applications where board space or
weight are important. High common mode voltage
range and absence of latch-up make the /-tA747 ideal
for use as a voltage follower. The high gain and wide
range of operating voltage provides superior
performance in integrator, summing amplifier, and
general feedback applications. The /-tA747 is short
circuit protected and requires no external components
for frequency compensation. The internal 6 dB / octave
roll-off insures stability in closed loop applications.
For single amplifier performance, see /-tA741
data sheet.
•
•
•
•
•
•
Connection Diagram
1o-Pin Metal Package
NC
v(Top View)
v + A IS internally connected to V
/lA747E, and /lA747C.
NO FREQUENCY COMPENSATION REQUIRED
SHORT-CIRCUIT PROTECTION
OFFSET VOLTAGE NULL CAPABILITY
LARGE COMMON MODE AND DIFFERENTIAL
VOLTAGE RANGES
LOW POWER CONSUMPTION
NO LATCH-UP
Absolute Maximum Ratings
Supply Voltage
Military
(/-tA747A, /-tA747, /-tA747E)
Commercial (/-tA747C)
Internal Power Dissipation
(Note 1)
Metal Package
DIP
Differential Input Voltage
Input Voltage (Note 2)
Voltage Between Offset
Null and VStorage Temperature Range
Operating Temperature Range
Military (/-tA747A, /-tA747)
Commercial (/-tA747E, /-tA747C)
Pin Temperature (Soldering)
Metal and Ceramic DIP (60 s)
Molded DIP (10 s)
Output Short Circuit Duration
(Note 3)
Order Information
Type
Package
/-tA747
Metal
/-tA747A
Metal
/-tA747C
Metal
/-tA 74 7E
Metal
+ B for /lA747A.
/lA747.
Part No_
/-tA747HM
/-tA747AHM
/-tA747HC
/-tA747EHC
Code
5X
5X
5X
5X
Connection Diagram
14-Pin DIP
±22 V
± 18 V
500 mW
670mW
±30 V
± 15 V
-IN A
OFFSET NULL A
+IN A
v+
+ OFFSET
NULL A
OUT A
v±0.5 V
-65°C to +150°C
NC
+OFFSET
NULL B
-55°C to +125°C
O°C to 70°C
300°C
260°C
Indefinite
A
OUT B
+IN B
v+
-IN B
OFFSET NULL B
B
(Top View)
Order Information
Type
Package
/-tA747
Ceramic DIP
Ceramic DIP
/-tA747A
Ceramic DIP
/-tA747C
Molded DIP
/-tA747C
Ceramic DIP
/-tA747E
Notes on following pages.
4-64
Code
6A
6A
6A
9A
6A
Part No_
/-tA747DM
/-tA747ADM
/-tA747DC
/-tA747PC
/-tA747EDC
IlA747
Equivalent Circuit (1/2 of circuit shown)
INVERTING
INPUT
r1~------+---~~-------'----------~--~------------------~'--V+
NONINVERTING
INPUT
R6
n
27
OUTPUT
R7
22
n
OFFSET
NULL
R1
1 kll
R3
50 kll
R9
R2
50 kll
1 kll
R11
50 kn
~---+--~---+----~------~--~----~--~--~~----~--6---~VOFFSET
NULL
Notes
1. Ratong applies to ambient temperatures up to 70 ° C. Above
70°C ambient derate linearly at 6.3 mW/oC for the Metal
Package and 7 1 mW / °C for the DIP
2 For supply voltages less than ± 15 V, the absolute maximum
onput voltage IS equal to the supply voltage
3 Short CirCUit may be to ground or either supply. Rallng applies
to +125°C case temperature or 75°C ambient temperature.
4·65
---~
..
--------
•
J.LA747
/-LA747 and /-LA747C
Electrical Characteristics
Vs = +
- 15 V TA = 25°C unless otherwise specified
/-LA747
/-LA747C
Typ
Max
Typ
Max
1.0
5.0
1.0
6.0
mV
Input Offset Current
20
200
20
200
nA
Input Bias Current
80
500
80
500
nA
Vs = +10, -20;
Power Supply Rejection Ratio
Vs = +20, -10V, RS = 5011
30
150
30
150
/-LV/V
Characteristic
Condition
Input Offset Voltage
RS S 10 kll
Min
.3
Input Resistance
2.0
Min
.3
Unit
2.0
Mil
Input Capacitance
1.4
1.4
pF
Offset Voltage
Adjustment Range
±15
±15
mV
25
mA
Output Short Circuit Current
Large Signal Voltage Gain
25
RL 2: 2 kll, VOUT = ± 10 V
50k
200k
25k
200k
It
Output Resistance
75
Supply Current (Total)
3.4
5.6
3.9
5.6
mA
Power Consumption (Total)
100
170
100
170
mW
Transient
Response
(Unity Gain)
IRise Time
IOvershoot
VIN = 20 mV, RL = 2 kit,
CL S 100 pF
Bandwidth (Note 4)
Slew Rate
RL 2: 2 kit
Channel Separation
75
.3
.3
/-LS
5.0
5.0
%
1.0
1.0
MHz
.5
.5
V//-Ls
120
120
dB
The following specifications apply over the range of -55 ° CsT A s 125 ° C for /-LA 7 4 7,
O°CsTAS 70°Cfor/-LA747C
Input Offset Voltage
Input Offset Current
1.0
RS s 10 kit
6.0
TA = +125°C
7.0
200
TA = -55°C
85
500
1.0
7.5
mV
7.0
300
nA
nA
nA
30
Input Bias Current
TA = +125°C
TA = -55°C
Input Voltage Range
Common Mode
Rejection Ratio
Rs s 10 kit
Supply Voltage
Rejection Ratio
Vs = +10, -20;
Vs = +20, -10 V, RS = 5011
.03
.5
.3
1.5
800
nA
/-LA
/-LA
± 12
±13
±12
±13
V
70
90
70
90
dB
30
150
30
150
/-LV/V
RL 2: 10 kll
± 12
±14
± 12
±14
V
RL 2: 2 kll
±10
± 13
± 10
±13
V
Large Signal Voltage Gain
RL 2: 2 kit, VOUT = ± 10 V
25k
Supply Current (Total)
TA = +125°C
3.0
5.0
TA = -55°C
4.0
6.6
Output Voltage Swing
15k
4.0
mA
Calculated value from BW(MHz)
200
mW
TA = +125°C
90
150
mW
TA = -55°C
120
200
mW
Note
4
mA
mA
120
Power Consumption (Total)
6.6
=
035
Rise Time (I-'s)
4-66
J.LA747
J.LA747A and J.LA747E
Electrical Characteristics
±5 V
~
Vs
~
±20 V, TA = 25°C unless otherwise specified.
J.LA747A/E
Typ
Max
Unit
0.8
3.0
mV
15
J.LV/oC
30
nA
J.LA747E
TA = 25°C to 70°C
TA = O°C to 25°C
0.2
0.5
J.LA747A
TA = 25°C to 125°C
TA = -55°C to O°C
0.2
0.5
nA/oC
nA/oC
nA/oC
nA/oC
30
80
nA
15
50
J.LVIV
Characteristic
Condition
Input Offset Voltage
Rs
~
Min
50 Q
Average Input Offset Voltage Drift
Input Offset Current
3
Average Input Offset Current Drift
Input Bias Current
Power Supply Rejection Ratio
Vs = +10, -20; Vs = +20 V, -10 V,
RS = 50 Q
Common Mode Rejection Ratio
Vs = ±20 V, VIN = ± 15 V, RS = 50 Q
80
Adjustment For Input Offset Voltage
Vs = ±20 V
10
J.LA747A
10
25
40
rnA
J.LA747E
10
25
35
rnA
160
300
1.0
6
mW
MQ
0.25
0.8
J.LS
6
20
%
Output Short Circuit Current
Power Consumption
Vs = ±20 V
Input Impedance
Vs= ±20V
Large Signal Voltage Gain
Transient Response
(Unity Gain)
I Rise Time
I Overshoot
dB
mV
Vs = ±20 V, RL = 2 kQ, VOUT = ± 15 V 50
VIN = 20 mV, RL = 2 kQ, CL
~
100 Vs
Bandwidth (Note 4)
Slew Rate (Unity Gain)
95
VIN = ± 10 V
The following specifications apply over the range of -55°C
O°C~TA~ 70°CforJ.LA747E
~
TA
~
V/mV
0.437
1.5
0.3
0.7
MHz
V/J.Ls
125°C for J.LA747A,
Input Offset Voltage
4.0
mV
Input Offset Current
70
nA
Input Bias Current
210
nA
40
rnA
I-55°C
330
mW
I +125°C
270
mW
Output Short Circuit Current
Power Consumption
10
VS= ±20V
.....
J.LA747E
Input Impedance
VS= ±20V
Output Voltage Swing
VS= ±20V
Large Signal Voltage Gain
Channel Separation
J.LA747A
330
lRL =
10 kQ
IRL = 2 kQ
mW
0.5
MQ
± 16
V
±15
V
Vs = ±20 V, RL = 2 kQ, VOUT = ± 15 V 32
V/mV
Vs= ±5V,RL=2kQ,VOUT= ±2V
10
V/mV
Vs = ±20 V
100
dB
Note
035
4 Calculated value from· BW{MHz) = RIse TIme (I's)
4-67
~~~----.
•
J.LA747
Typical Performance Curves for /J-A747A and /J-A747
Input Bias Current as a
Function of
Ambient Temperature
Output Short Circuit
Current as a
Function of
Ambient Temperature
Input Resistance as a
Function of
Ambient Temperature
..
,
2••
Vs = :t15 v
•
:i
I
w
~ 100
~
........
•-6.
r--
--
..
50
~
30
t"-
2.
-2.
TEMPERATURE _ °C
..,-
Input Offset Current as a
Function of
Ambient Temperature
~ 20
"-
U
~
..
we
TEMPERATURE _
f'..
:;
,
6.
2.
-2.
I"--.
~
~
-6.
14.
"-
~
I ....
,.
,
6.
V
v
30
~ 25
""
l-
~
.""'-
~
-
30
~
"-
~
"z
•
35
~ ±1~ v
vs
5.
15
•-6.
1
14.
2.
-2.
..
,
6.
TEMPERATURE _
14.
°C
Frequency Characteristics as a
Function of
Ambient Temperature
Power Consumption as a
Function of
Ambient Temperature
14
14
Ys - :t15 v
~
~ 10
o
~
\
~
•
6
•
-6.
-- --
2.
-2.
........
~
........
••
•
..
,
6.
r-
:i'
I-14.
Il_
........
r- ........
-6.
2.
-2.
TEMPERATURE _ °C
..
,
6.
TEMPERATURE _
14.
=- :!:15 V
....~
~
~rr,\t,~"'i.
~
o
"ffi
Vs
12
• ......
8
z
""'- r--
Ys '" ::!:20 V
12.
r--.. '~L~WR~TE
.....,:P' c~
:::
!
o..~
84"O.. ~:c-
I 'I'"
I
.6
-2.
-6.
..
,I
6.
2.
TEMPERATURE _
DC
°C
14.
Typical Performance Curves for /J-A747E and IJ.A747C
Input Bias Current as a
Function of
Ambient Temperature
..
Input Offset Current as a
Function of
Ambient Temperature
Input Resistance as a
Function of
Ambient Temperature
,.
,
Vs, -= ::1:15, V
vc
f-"
5.
- •o
..- ..-
~
•
r-
r--
20
30
40
TEMPERATURE -
SO
QC
60
70
r---
-
•
Vs '"
10
:1-15 V
,
7.
•
10
20
30
40
TEMPERATURE _
4-68
50
°C
t5
60
1
V
70
10
20
30
40
50
TEMPERATURE _ °C
60
70
JLA747
Typical Performance Curves for J.lA747E and J.lA747C (Cont.)
Output Short-Circuit
Current as a
Function of
Ambient Temperature
Power Consumption as a
Function of
Ambient Temperature
,.•
..
~
I
z
o
•
~ 8
"ii:
8
'"w
70
.
•
Vs"':!:20V
1 2•
I
...........
---- ----
ill'"
2
'"'"o
:J
!:
:J
•
...........
•
........
...........
o
~
22
r-.....
""
~
••
~
Frequency Characteristics
as a Function of
Ambient Temperature
~
•
10
20
30
40
50
80
•
•
70
10
TEMPERATURE _ °C
20
30
40
50
60
••51---t--+-+-t-~
70
TEMPERATURE _ °C
TEMPERATURE _ °C
Typical Performance Curves for J.lA747A, J.lA747C, J.lA747 and J.lA747E
Power Consumption
as a Function of
Supply Voltage
Open Loop Voltage
Gain as a
Function of Frequency
..
,
,.'
TA
,
/
=1 25oC
80
I
z
~IO
..ii:
8
/'
40
V
~
•
/"
1.
5
I"
1"-
,.-
W
~ 10 2
g
1.+V
'"
100 k
\
1 M
-180
1
10 M
w
o
z
10
100
1 k
10 k 100 k
FREQUENCY -
Hz
••
50.l-ttlH-+-ttlH-+-t+H-+-++fH
1
1 M
::l
C'N
.'"
~ 100 k
1
i!!
5
1.
,. k
15
SUPPLY VOLTAGE -
20
+V
100
10 M
RIN
;
'"~ 20
1 M
Hz
Output Resistance as a
Function of Frequency
"
-
V r-
i'
-135
1
r-
S
,.
10 k
,. M
~
I ••
i!!
1 k
~15
V
+2SoC
\
I
"-
Y,
TA
:l
il:
Input Resistance and
Input Capacitance as a
Function of Frequency
TA = 25°C
30
100
1\
w-tO
,
10
5.
~
1"-
FREQUENCY -
Input Offset Current as a
Function of
Supply Voltage
~
-45
,.
2.
15
SUPPLY VOLTAGE -
§'"
== :!:1S' Y
TA = +25 0 ( : -
•"
./
20
v}
I---..
" 103
V
i5
..~
/
/
10'
Open Loop Phase
Response as a
Function of Frequency
•
1
1k
10 k
FREQUENCY -
4-69
100 k
Hz
1 M
FREQUENCY -
Hz
•
p,A747
Typical Performance Curves for JLA747A, JLA747C, JLA747 and JLA747E (Cont.)
Output Voltage Swing
as a Function of
Load Resistance
..
..."z.•
>
vs
128
Ii
!;
TA
='±lJ
v'
25°C
~~~r-~~r-~rnr-r-~~
~
,-
=::
Ys '" ±15 V
>
~20
0, a
II
~ 16
e>l
14
.. 1.
01
2s·e
!
28
H-ttt-H-ttt-t-f-tlt-t-f-tlt--i
~
24
H-+++-H-+++-tl.\r+-I-tt--++I-tt----i
~
•• H-+++-H-+++-+-tt-,,*-++Ht-i
~
~
"H-+++-H-+++-+-N1+-+-f-tlt--i
aH-tt+-H-+++-t-rHt-t-Hrlt--i
.. 4H-+++-H-+++-t-H-f+tI.~+I-tt----i
/
a
=::
RL = 10 kU
~ lsH-+++-H-+++-~Hrl+-+-Hrlt--i
II
•
~ 1
3sH-tt1H-++++-+-+HtTA
~ 32
V
•
Input Noise Voltage
Density as a
Function of Frequency
Output Voltage Swing as a
Function of Frequency
02
05
10
20
LOAD RESISTANCE -
50
~.~.~~-:lJ....~UJ...""l.~.-'-UJ...,~•...,r'~'~~lM
10
kn
FREQUENCY -
1D181,~.-"-,UJ...-;1:;;
••;-'-'UJ...-;1"'.;-'-u..L-;,t.;:"
• .I.-J-~100 k
FREQUENCY -
Hz
Hz
Typical Performance Curves for
JLA747 and p.A747C
Input Noise Current
Density as a
Function of Frequency
~
..
Common Mode Rejection
Ratio as a
Function of Frequency
Broadband Noise for
Various Bandwidths
•
'·-20~~m~~~~
Vs
TA
+15 Y
2soe
.
~
I 10-22 HH-f+-HH-f+-+-H-f+-+-H-f+--1
o
§~ 10-23~~~~~~~~~~~~~
~~~~
o~
R=t
:10-24~~~s~~~~~~~~
~ ~
•
1
10 -
,.
f-
'~
"'""
100 kHz
10 kHz
,. _l"HI,
'"
gz 10-2S I-f-tl+-+-f-tl+-+-f-tl+-+-f-tl+-l
7
Z
o
50
~
5
~
~
~
8
1
1• •
1k
SOURCE RESISTANCE -
100 k
n
TA "" 2S·C--
" -""
S•
'"
Hz
Vs =- :!.15 V
8
II:
:E
FREQUENCY -
.••
•
-""
. •
" ..
.. ••
V
:I
10-261_~.-'-UJ.-:,""
..-'-UJ.-:,J....-'-w..",,1.~.-'-u..L-:-::'100 k
,.•
.
-""
1
•
10
100
1 k
10 k
FREQUENCY -
100 k
1 M
Hz
Typical Performance Curves for JLA747 and JLA747C (Cont.)
Voltage Follower Large
Signal Pulse Response
Transient Response
Frequency Characteristics
as a Function of
Supply Voltage
28
Vs - ±15 v
TA '" 25°C
•
Al
'E
I
~
1a
•
1
::J
o
4
=
2 kH
CL = 100 pF
~
20
8...
>
I
I
O:>~
I
II
- lifo. f:M.
10%
OUTPUT
if
INPUT
i
~\
~
~
~~+-+-+~--~~~~--~
-4
"
-t
~+-+-+~--t-+~-t'~--~
1-r---+-+---+--I----1f-'
...t-"_".+"_l.....-+i-----1f-----I
-81-+-+-+-+-++-+-f----jH
10
TIME -,uS
15
20
25
-1~1!o:.--!:.--:,'=".-+.
••~.."...,..!::--.!.."...,50!::--:7."...,8!:.~..
TIME
-Il'
4-70
SUPPLY VOLTAGE -
±V
10 M
J.LA747
Test Circuits
Transient Response Test Circuit
Voltage Offset Null Circuit
>=-.....- .....--VOUT
RL
t
v-
Typical Applications
Quadrature Oscillator
C2
820 pF
1%
C3
820 pF
1%
SINE
OUTPUT
R3
190 kll
1%
•
+15 V
>-4_....._COSINE
R2
OUTPUT
180 kll
1%
Rl
R4
190 kll
-15 V
190 kll
1%
1
Cl
820 pF
1%
f
=
1
2". ylC2R2C3R3
(R1C1
= R2C2)
Tracking Positive and
Negative Voltage References
R4
12 kll
01
6.2 V
V+
R5
10 kll
RS
10 kll
V+
NEGATIVE
REGULATED
OUTPUT
R3
180 kll
-12 V
V-
Rl
10 kll
V-
IL :5 5 rnA
SOURCE
OR SINK
R2
11 kll
Positive Output
= V01
R1 + R2
x --R-2-
Negative Output = -PositIve Output x
4·71
R6
As
J.LA747
Analog Multiplier
+15 V
CURRENT SOURCE
R2
20 kll
1%
Rl
20 kll
1%
AMPLIFIER
R14
25.8 kll'
1%
lN963B
-=
Rll
12 kll'
1%
+15 V
EIN 1
-15 V
+15 V
MULTIPLIER
2N2920
OR
I'A726
R5
5 kll
1%
R12
12 kll'
1%
EOUT
R15
25.8 kll'
1%
EIN 2
-15 V
R4
15 kll
1%
R3
20 kll
1%
R7
150 kll
Rl0
150 kll
ZERO ADJUST
-15 V
+15 V
'Matched 10 01%
EOUT
=
100EIN 1 x EIN2
Compressor IExpander Amplifiers
R
01
R2
10 kll
R
D2
R5
R
+15 V
1 kll
D3
Rl
COMPRESSOR
IN PUT --''''1"'k....
ll......,
EXPANDER
INPUT
R3
10 kll
EXPANDER
OUTPUT
R
-15 V
-=
COMPRESSOR
ftr
-=-
Notes
1. Maximum Compression Expansion Ratio = R / R (10 kll > R 2: 0)
2. Diodes 01 through 04 are matched F0666 or Equivalent
4-72
EXPANDER
JlA748
Operational Amplifier
FAIRCHILD
A Schlumberger Company
Linear Products
Description
The JlA748 is a High Performance Monolithic
Operational Amplifier constructed using the Fairchild
Planar epitaxial process. It is intended for a high wide
range of analog applications where tailoring of
frequency characteristics is desirable. High common
mode voltage range and absence of latch·up make the
JlA748 ideal for use as a voltage follower. The high
gain and wide range of operating voltages provide
superior performance in integrator, summing amplifier,
and general feedback applications. The JlA748 is
short circuit protected and has the same pin
configuration as the popular JlA 7 41 operational
amplifier. Unity gain frequency compensation is
achieved by means of a single 30 pF capacitor.
Connection Diagram
8-Pin Metal Package
>---{) OUT
-IN
•
v(TOp View)
•
•
•
•
•
SHORT CIRCUIT PROTECTION
OFFSET VOLTAGE NULL CAPABILITY
LARGE COMMON MODE AND DIFFERENTIAL
VOLTAGE RANGES
LOW POWER CONSUMPTION
NO LATCH-UP
Pm 4 connected to case
Order Information
Type
Package
JlA748
Metal
ILA748C
Metal
Absolute Maximum Ratings
Supply Voltage
±22 V
Internal Power Dissipation
(Note 1)
Metal Package
500mW
DIP
310 mW
Flatpak
570 mW
Differential Input Voltage
±30 V
Input Voltage (Note 2)
± 15 V
Storage Temperature Range
Metal Package
-65°C to +150°C
DIP
-55°C to +125°C
Operating Temperature Range
Military (JlA 7 48)
-55°C to +125°C
Commercial (JlA748C)
O°C to +70°C
Pin Temperature (Soldering 60 s)
Metal Package
300°C
Molded DIP (lOs)
260°C
Output Short Circuit Duration
Indefinite
(Note 3)
Code
Part No.
JlA748HM
ILA748HC
5W
5W
Connection Diagram
8-Pin DIP
8
OFFSET
NULL
FREO
COMP
-IN
v+
+IN
OUT
OFFSET
NULL
v-
(Top View)
Order Information
Type
Package
ILA748C
Molded DIP
Code
9T
Part No.
JlA748TC
Notes
1 Ratmg applies to ambient temperatures up to 70'C Above
70°C ambient derate linearly at 6 3 mW / °c for metal package,
5 6 mW / °C for the DIP
2 For supply voltages less than ± 15 V, the absolute maximum
mput voltage 10 equal to the supply voltage
3 Short circuit may be to ground or either supply Ratmg applies
to +125°C case temperature or +75°C ambient temperature
4·73
- - - - - - - _.. -
/-LA748
Equivalent Circuit
INVERTING INPUT -
COMP OFFSET NULL
COMP
r--------------+-+--_1~------._------_1~~~--+_--------------t_- V+
NON-INVERT
INPUT +
R6
2711
OUTPUT
R5
40 kll
R7
2211
OFFSET NULL
V+
300 II
017
023~---+--~~--~--~----t-.
011
R1
1 kll
R3
50 kll
R2
1 kll
R4
R9
10 kll
50 kll
4-74
R8
100 II
R11
50 kll
f.LA748
/LA748 and /LA78A
Electrical Characteristics
Vs
Characteristic
Input Offset Voltage
= +- 15 V
TA
= 25°C
Cc
= 30 pF unless otherwise specified
/LA748A
Typ
Min
0.5
Condition
Rs:::; 10 kf!
Max
2.0
/LA748
Min
Typ
1.0
Max
5.0
Unit
mV
Input Offset Current
2.0
10
20
200
nA
Input Bias Current
20
75
80
500
nA
Input Resistance
2.0
10.0
0.3
2.0
Mf!
Input Capacitance
3.0
2.0
pF
Offset Voltage
Adjustment Range
±25
±15
mV
Large Signal Voltage Gain
RL;:::: 2 kf!, VOUT
=
± 10 V
50 k
Output Resistance
250 k
50 k
100
150 k
VIV
75
f!
Output Short-Circuit Current
±25
Supply Current
1.9
2.8
1.9
2.8
mA
Power Consumption
60
85
60
85
mW
Transient
Response
(Voltage
Follower,
Gain of 1)
Rise Time
Overshoot
VIN = 20 mV, Cc = 30 pF,
RL = 2 kf!, CL :::; 100 pF
Slew Rate (Voltage
Follower, Gain of 1)
RL;:::: 2 kf!
Transient
Response
(Voltage
Follower,
Gain of 10)
VIN = 20 mV, Cc = 3.5 pF,
RL = 2 kf!, CL :::; 100 pF
Rise Time
Overshoot
Slew Rate (Voltage
Follower, Gain of 10)
RL ;:::: 2 kf!, Cc
25
mA
0.3
0.3
/LS
5.0
5.0
%
0.5
0.5
V//Ls
0.2
0.2
/LS
5.0
5.0
%
5.5
V//Ls
= 3.5 pF
The following specifications apply for -55 ° C :::; TA :::; 125 ° C
Input Offset Voltage
Input Offset Current
Input Bias Current
RS:::; 10 kf!
0.5
= HIGH
TA = LOW
TA = HIGH
TA = LOW
TA
Input Voltage Range
Common Mode
Rejection Ratio
RS:::; 10 kf!
Supply Voltage
Rejection Ratio
RS:::; 10 kf!
Large Signal Voltage Gain
Output Voltage Swing
RL;:::: 2 kf!, VOUT
RL;:::: 10 kf!
± 10 V
Supply Current
Power Consumption
= HIGH
TA = LOW
TA = HIGH
TA = LOW
4·75
mV
200
nA
25
50
500
nA
0.1
0.03
0.5
/LA
0.1
0.3
1.5
/LA
V
dB
± 13
± 12
80
95
70
90
100
25 k
±10
RL;:::: 2 kf!
6.0
10
± 13
±12
TA
1.0
25
±12
13
=
3.0
30
150
25 k
±14
± 12
±13
±10
/LV IV
VIV
± 14
V
± 13
V
1.5
2.5
1.5
2.5
2.0
3.3
2.0
3.3
mA
mA
40
75
45
75
mW
60
100
60
100
mW
•
,."A748
p,A748C
Electrical Characteristics
Vs
= ± 15 V, TA = 25°C, Cc = 30 pF unless otherwise specified.
p,A748C
Typ
Max
Unit
2.0
6.0
mV
Input Offset Current
20
200
nA
Input Bias Current
80
500
nA
Characteristic
Condition
Input Offset Voltage
RS .::;; 10 kfl
Min
Input Resistance
0.3
Input Capacitance
Offset Voltage Adjustment Range
2.0
Mfl
2.0
pF
± 15
mV
150 k
VIV
Output Resistance
75
fl
Output Short-Circuit Current
25
Supply Current
1.9
2.8
Power Consumption
60
85
Large Signal Voltage Gain
Transient Response
(Voltage Follower,
Gain of 1)
RL 2:: 2 kfl, VOUT
Rise Time
Overshoot
Slew Rate (Voltage
Follower, Gain of 1)
Transient Response
(Voltage Follower,
Gain of 10)
Rise Time
Overshoot
Slew Rate (Voltage
Follower, Gain of 10)
=
± 10 V
20 k
mA
mA
mW
VIN = 20 mV, Cc = 30 pF,
RL = 2 kfl, CL .::;; 100 pF
0.3
p,s
5.0
%
RL 2:: 2 kfl
0.5
V/p,s
VIN = 20 mV, Cc = 3.5 pF,
RL = 2 kfl, CL .::;; 100 pF
0.2
p,s
5.0
%
5.5
V/p,s
RL 2:: 2 kfl, Cc
= 3.5 pF
The following specification apply for O°C .::;; TA'::;; 70°C
Input Offset Voltage
Input Offset Current
RS'::;; 10 kfl
2.0
= HIGH
TA = LOW
TA
Input Voltage Range
Common Mode Rejection Ratio
RS .::;; 10 kfl
Supply Voltage Rejection Ratio
RS .::;; 10 kfl
Large Signal Voltage Gain
RL 2:: 2 kfl, VOUT
RL 2:: 10 kfl
Output Voltage Swing
RL 2:: 2 kfl
Supply Current
Power Consumption
= HIGH
TA = LO
TA = HIGH
TA = LO
TA
4·76
± 10 V
mV
nA
800
p,A
± 12
± 13
V
70
90
dB
30
=
7.5
300
150
15,000
± 12
± 10
p,V IV
VIV
± 14
± 13
V
V
1.5
2.5
mA
2.0
3.3
mA
45
75
mW
60
100
mW
p,A748
Typical Performance Curves for I'A748
Input Bias Current as a
Function of
Ambient Temperature
...
•
10.
V5~.,JV
... \
~.
35
±~ v
..... ~
i
I
I-
V51=
••
1!
.
..""~
".
\
I
3•
;
10
e~
\
I-
100
~ .....
;E
..
r-...
~
......
..
•
Output Short Circuit
Current as a
Function of
Ambient Temperature
Input Resistance as a
Function of
Ambient Temperature
100
.
E
I
./
~
II!
G
.//
/
~
••
~
•.3
iii
.
••
140
TEMPERATURE _ DC
Input Offset Current as a
Function of
Supply Voltage
.. .
100
3D
i'..
25
" I'.. r'\.
20
'5
••-60
.40
TEMPERATURE _
.
Vs=±1SY
I
I-
.ill
""
i
3D
20
;E
~
3D
~
II:
20
~
I......
0
0
."
I-
I
I
."
I-
••
••
~
i8
i
-
••
;E
••
I
--.
••±v
.00
'40
CD
70
.. 1-r......
r- ..........
50
40
30
-80
..
-20
TEMPERATURE _ "C
SUPPLY VOLTAGE -
140
c
0
Vs=±15Y
AL '"
40
"
100
Power Consumption as a
Function of
~mblent Temperature
50
1!
..
-20
TEMPERATURE _ DC
Input Offset Current as a
Function of
Ambient Temperature
1!
Vs="!:5V
" ........
TEMPERATURE -
100
140
"C
Typical Perfomance Curves for I'A748C
Input Bias Current as a
Function of
Ambient Temperature
...
10
.....
'20
""
..
~
l-
i
r--....
i
;E
+15 V
Vs=±15Y
7•
I
!zw
32
Vs
VS-±15V
...
1
.
Output Short Circuit
Current as a
Function of
Ambient Temperature
Input Resistance as a
Function of
Ambient Temperature
--
I
~
z
j!
-
.5~
.
;E
••
20
30
40
TEMPERATURE _
50
0
c
60
70
,/
" " i'-
3.
.,,- ,/"
2.
40
10
......~
V
••
...
,/"
,/"
18
010203040506070
TEMPERATURE _ "C
4·77
•
10
..
3D
40
50
TEMPERATURE _ "C
.........
.........
..
70
p,A748
Typical Perfomance Curves for ItA748C (Cont.)
Input Offset Current as a
Function of
Supply Voltage
Input Offset Current as a
Function of
Ambient Temperature
Power Consumption as a
Function of
Ambient Temperature
.0
Vs= ~15V
0
Ys"'+15V
Fk=
I
:>
l)"
Hz
10.
r"
c
1'\...
; '•• 1
'<
RL-2kU
Cc~3pF
g 20 1---+-+--+--+---'+----'
'~_l
......•..
..... \
-0. !---,,!::.-,=.,:---=,.::-,---;""::--":'::.'-'=":---='.7
1110.
n
FREQUENCY -
'20 r--r-,--,--,-,-"""-"
-tsl~~lv
TA =:we
jL= 10 kil
32
Hz
Open Loop Voltage Gain as a
Function of Frequency for Various
Gain/Compensation Options
Output Voltage Swing as a
Function of Frequency
.~-r--r-~--'--'--'--'
30~'
,.
SOURCE RESISTANCE -
FREQUENCY - Hz
Open Loop Phase Response
as a Function of Frequency
".
\
Z
C
60
~ 40~+~~~-~*~-k~-,F~~~~-'~,t,,-i--I
., ............. ~
~
~ 1025
'I
Rs ~ 50
~ eo f---+-"'.,.......-'........r-,,-t--+-+--I
•••••••••• " " "
i"
10-10 kHz
iii
0:
W 1024
~
10-100 ....
510:
iii
Z
V;~±'5~
TA~+"·C-
_L
~~!-~~~
I
8
Hz
'2Or--r-,--,:---,-,--.-,
!
..·c
~~~~
10 181~
• ..J....I.u....-=1OO::-'-.LLL-:':':.~.L.I.L-:,.~.:-'-w..==,.. k
1110
Ys
TA
~~~~tt~~~~~~~
TEMPERATURE _ DC
Broad Band Noise for
Various Bandwidths
i
..~
...
15
~
110"
~
10
!Iig ,."
Input Noise Current as a
Function of Frequency
,."
~
.~
",1),
..
H.-++HH+H-+-++++-+-+-+++--1
I
C(~III
20
10 14
~
.
("o,,~
-m
Input Noise Voltage as a
Function of Frequency
11.r---.--.--r---'-"T""-r-~
Vs=±15Y
r<;:;-r
....... r-.. ~ ~E~RAi.
TEMPERATURE _
~
jl748C Frequency Characteristics
as a Function of
Ambient Temperature
'DO ~~~~-+--+'ll eo
I
24
,.
I\CC=3PF
\CC~~PF\
~
60
~
.. I--+-+--Ir---~.~~
~ .. I---+-+--+--+---''k-''ri't--!
~
r
•
1k
10.
...r--
r--
,
FREQUENCY -
4·79
'M
Hz
10M
FREQUENCY -
Hz
,."A748
Typical Perfomance Curves for ,uA748 and ,uA748C (Cont.)
Frequency Response for Various
Closed Loop Gains
Compensation Capacitance as a
Function of
Closed Loop Voltage Gain
Input Resistance and Input
Capacitance as a
Function of Frequency
50
100
%.
20
I
~
I
Z
;;
"w
"
~
1l
80
60
Cc -='2 pF
40
z
10
~
50
~
Cc=lpF
Vs +15 V
TA = 25°C
RL = 2 k!l
\
'a
"\ \
"-
Z
o
fi
§! 20
8~
cc =~PF~ ':-••••
CC=~OPF
-20
100
10
/
20
(CL
,~
100 pF)
~
"'
20% OVERSHOOT
(CL::S 20 pF)
10k
lOOk
1M
10
10M
Hz
20
-....:::: ~
30
40
~
~
!!;
..... ~
50
60
CLOSED LOOP VOLTAGE GAIN -
Voltage Fo"ower Transient
Response (Gain of 1)
~
~ 100 k1-t+H---+-++-I+-+-HH+-+-+++IHl 0 ~
~
10
~
j!
Z
~
s
lk
FREQUENCY -
~ lMI-t+H---+-++-I+-+-HH+-+-+~Hl0 ~
NO OVERSHOOT
70
dB
FREQUENCY -
Transient Response Test Circuit
Hz
Voltage Fo"ower
Large-Signal Pulse Response
10
8
Vs~±15V
TA '" 25°C
RL = 2 kn
24
-
CL
o
~
R,ser ME -
RL
Vs -'- ±15 V
TA - 25°C
RL ~ 2 k!l
25
Common Mode Rejection
Ratio as a
Function of Frequency
5001-t+H---+-++-I+-++f-++-+-++HH
~
:>
200
z
OJ
a:
50
~
100
..
8
10 k
FREQUENCY -
100k
Hz
70
60
v!-±"Iv-
\.
TA = 25°C
CL-=30pF-
\.
\.
:g 40
o
.. '0
I
1k
90
80
o
~
0
0
100
I
o
!ia:
400
Z
~
'"
O~TPUT
0
0
o
I
INPUT
~
I
cc,
~
10
~
\
~
,
'r
<
V
I
~
~
TIME-"s
100
...a:
~
:>
-2
-1
20
15
"S
~
300
!I
,1
Cc=30pF
J
6f:: i -
Output Resistance as a
Function of Frequency
"~
§!
CL rOPF
f------
10
I
I
...
TIME -
w
~
~
U
f--
>
I
1M
\.
20
10
0
10
100
lk
10k
FREQUENCY -
4-80
lOOk
Hz
1M
10M
j-
~
~
~
~
f.LA748
Typical Performance Curves for ILA748 and ILA748C (Cont.)
Large Signal Feed Forward
Transient Response
Feed Forward Compensation
10 kll
2Sr-r-~~-+-+-+~-r-H~
10 kfl
V'N - - . . , . . , . , . - -.....4...--......;-1
\
>:...........---.-VOUT
-25 0!:--L--:,:-o-'--!,,:-'--'3:':0:-'---'4':-0-L-:S:O--'--:'"
CL
I10 P F
5 pF
3.0 kll
RESPONSE TIME - I-'S
150 pF
•
Voltage Offset Null Circuit
5.1
Mil
1"",,
5.1 Mil
10 mil
. . . . . . .""'_-V25 kil
Suggested
Alternate
Typical Applications
Pulse Width Modulator
Rl
+~'~
R2
__1"10"0,,krll_~_ _ _ _ _ _ _ _10....0....k...!_l--,
+15 V -15 V
....-------jf--
VOUT
'e = 211" R2 Cl
R3
10 kll
C1
0.47
~F
1
'n = 211" Rl Cl
I
R4
=
100 k!l
R5
100 !l
1
211" R2 C2
'e < 'n < 'unity gain
01
6.2 V
02
6.2 V
4·81
p,A748
Typical Applications (Cont.)
Circuit for Operating the JlA748 Without a
Negative Supply
Practical Differentiator
C2
R2
R1
R2
+20 V
+15 V -15 V
R1
Y,N
1
C1
---\l'llv-----jl-.....--=:...t
6
>~""'--VOUT
VOUT
R3
":" 30 pF
4·82
fJ,A759
F=AIRCHIL.O
Power Operational
Amplifier
A Schlumberger Company
Linear Products
Description
The J,lA759 is a High Performance Monolithic
Operational Amplifier constructed using the Fairchild
Planar Epitaxial process. The amplifier provides
325 rnA output current and features small signal
characteristics better than the J,lA 7 41. The amplifier is
designed to operate from a single or dual power
supply and the input common mode range includes the
negative supply. The high gain and high output power
provide superior performance whenever an
operational amplifier is needed. The J,lA759 employs
internal current limiting, thermal shutdown and safearea compensation making it essentially
indestructible. It is intended for a wide range of
applications including voltage regulators, audio
amplifiers, servo amplifiers and power drivers.
Connection Diagram
a-Pin Metal Package
•
•
•
•
Pm 4 connected to case
•
NC
>-"""<1 OUT
-IN
v(Top View)
OUTPUT CURRENT-325 mA MINIMUM
INTERNAL SHORT-CIRCUIT CURRENT LIMITING
INTERNAL THERMAL-OVERLOAD PROTECTION
INTERNAL OUTPUT TRANSISTORS
SAFE-AREA PROTECTION
INPUT COMMON MODE VOLTAGE RANGE
INCLUDES GROUND OR NEGATIVE SUPPLY
Order Information
Type
Package
J,lA759
Metal
J,lA759C
Metal
Code
5W
5W
Part No.
J,lA759HM
J,lA759HC
Connection Diagram
Power Watt Package
Absolute Maximum Ratings
Supply Voltage
Between V+ and V36V
Differential Input Voltage (Note 1) 30 V
(V- -0.3 V) to V+
Input Voltage (Note 1)
Internal Power Dissipation
(Note 2)
Internally Limited
Operating Junction
Temperature Range
Military (J,lA749)
-55°C to +150°C
Commercial (J,lA759C)
O°C to +125°C
Storage Temperature Range
4-Pin Power Watt (U1)
-55°C to +150°C
8-Pin TO-99 (H)
-65°C to + 150°C
Pin Temperature
4-Pin Power Watt (U1)
(Soldering, 10 s)
260°C
8-Pin TO-99 (H)
(Soldering, 60 s)
300°C
(Top View)
Order Information
Type
Package
J,lA759C
Power Watt
Notes
1. For a supply voltage less than 30 V between V+ and V-, the
absolute maximum mput voltage IS equal to the supply voltage.
2 Although the internal power diSSipation is limited, the junction
temperature must be kept below the maximum speCified
temperature in order to meet data sheet speCifications. To
calculate the maximum Junction temperature or heat smk
required, use the thermal resistance values on page 3
4·83
Code
8Z
Part No.
J,lA759U1C
p,A759
Equivalent Circuit
= +- 15 V, TJ = 25 ° C unless otherwise specified
Electrical Characteristics
Vs
Characteristic
Condition
Input Offset Voltage
Rs::; 10 kQ
IlA759
Typ
Min
Max
IlA759C
Typ
Min
Max
Unit
1.0
3.0
1.0
6.0
mV
Input Offset Current
5.0
30
5.0
50
nA
Input Bias Current
50
150
50
250
nA
Input Resistance
0.25
Input Voltage Range
Large Signal Voltage Gain
RL ~ 50 Q, VOUT
= ± 10 V
0.25
1.5
+13 to +13 to
-VS
-VS
200 k
50 k
Supply Current
12
1.5
MQ
+13 to +13 to
-VS
-VS
25 k
18
V
200 k
12
VIV
18
mA
Peak Output Current
3 V ::; I Vs - VOUT I < 10 V
Short Circuit Current
Ivs - vOUTI = 30 V
±200
±200
mA
Transient
Response
(Unity Gain)
RL ~ 50 Q
300
300
ns
Risetime
±325
±500
±325
±500
mA
Overshoot RL ~ 50 Q
5.0
10
%
RL ~ 50 Q
0.6
0.5
V/lls
1.0
1.0
MHz
Slew Rate
Unity Gain Bandwidth
The following specifications apply for -55°C -< TJ -< 150°C (IlA759), or 0° -< TJ -< 125°C (IlA759C)
Input Offset Voltage
4.5
7.5
RS::; 10 kQ
mV
Input Offset Current
60
100
nA
Input Bias Current
300
400
nA
Common Mode
Rejection Ratio
Rs::; 10 kQ
80
100
70
100
dB
Power Supply
Rejection Ratio
RS::; 10 kQ
80
100
80
100
dB
Large Signal Voltage Gain
RL ~ 50 Q, VOUT
25 k
200 k
25 k
200 k
VIV
Output Voltage Swing
RL ~ 50 Q
±10
± 12.5
± 10
± 12.5
V
=±
10 V
4·84
p,A759
Package
Type Max
Typ
Max
Power Watt (U1)
Metal Can (H)
liJC
°C/W
8.0
30
liJA
°C/W
75
120
liJA
°C/W
80
185
PO(MAX)
liJC
°C/W
12
40
Mounting Hints
Metal Can Package (~A759HC/~A759HM)
The ~A759 in the 8-Pin TO-99 metal can package must
be used with a heat sink. With ± 15 V power supplies,
the ~A759 can dissipate up to 540 mW in its quiescent
(no load) state. This would result in a 100°C rise in
chip temperature to 125°C (assuming a 25°C ambient
temperature). In order to avoid this problem, it is
advisable to use either a slip on or stud mount heat
sink with this package. If a stud mount heat sink is
used, it may be necessary to use insulating washers
between the stud and the chassis because the case
of the ~A759 is internally connected to the negative
power supply terminal.
TJ(MAX) - TA
TJ(MAX) - TA
liJC + liCA
or
liJA
=
(Without a heat sink)
liCA = lics
+ liSA
Solving for TJ: TJ = TA + Po (liJC
(Without heat sink)
Where:
+ liCA) or TA + POliJA
Power Watt Package (~A759U1C)
The ~A759U1C is designed to be attached by the tab
to a heat sink. This heat sink can be either one of the
many heat sinks which are commercially available, a
piece of metal such as the equipment chassis, or a
suitable amount of copper foil as on a double sided PC
board. The important thing to remember is that the
negative power supply connection to the op amp must
be made through the tab. Furthermore, adequate heat
sinking must be provided to keep the chip temperature
below 125°C under worst case load and ambient
temperature conditions.
= Junction Temperature
TJ
TA
Po
liJA
= Ambient Temperature
= Power Dissipation
= Junction to ambient
thermal resistance
liJC
= Junction to case
liCA
= Case to ambient
liCS
= Case to heat sink
thermal resistance
= Heat sink to ambient
thermal resistance
thermal resistance
liSA
thermal resistance
Typical Performance Curves
Frequency Response at
Various Closed
Loop Gain Settings
. r--
Open Loop Gain and
Phase Response as a
Function of Frequency
100
80
70
100
'\
90
i:
~
..
0
'\
0
1'\
\
50
40
10 1
102
103
104
I\.
'\
0
105
FREQUENCY-Hz
lOS
100
60
"
103
104
105
FREQUENCY-Hz
4·85
106
•
f
0
5
15
\
I!:"
10
20
I')...
40
"\
102
..
40
I\.
10 1
:
BO
1\
-10
..
30
40
100
I\.
'\
10
107
PHA~-
'\.
\
0
"''\1\
10
100
./
0
Vs= ±15V
fA = 25°C
RL = son
160
I'\.
\
0
I"\.
~ 30
!i! ..
'\.
•
I 80
t - ,/~AIN
o '\
1\
'II ..
Output Voltage as a
Function of Frequency
107
10'
10"
10'
FREQUENCY-Hz
10'
10'
4
J.LA759
Typical Performance Curves (Cont.)
p.p Output Voltage as a
Function of
Load Resistance
30
~~ =
21S0C
10
I
II'
Vs
±15V
RL=50n
~; ~ ~O:¢F
V
10
I
- 4
I
I
I
TJ = 150"C
Ii
10
1000
20
30
40
Vs = :t15V
son
RL
20V p_p
1.0
10
I
f = 1 kHz
~~ ~! ~~~~~:g~8n)
=1
J,...
60
.02
04
en
-
L"oID6
1
II I
10'
1
00 01
02
16
n
32
n
05
FREQUENCY-Hz
Noise Current as a
Function of Frequency
08
1.0
1.2
Input Noise Voltage as a
Function of Frequency
/I
Vs
TA
=±
1S V
2S"C
I I
RL
=
06
I
1
V
103
RISeTIME 0.22 f,lS
TIME-f.ls
10
10'
0
Total Harmonic Distortion as a
Function of
Power Output
Av
Av-20D6
50
I
I
0
TIME-Ils
Total Harmonic Distortion as a
Function of Frequency
1
30
0
LOAD RESISTANCE-J!
10
\-\
40
--
-6
I
100
r.......
90%
--\.
I
II
-2
r
50
~
OUTPUT
INPUT/"
I
IJI
1
= SO!l
fA"" 25"C
RL
V
III
III'.
15
o
=
Vs = :t15V
V.
1\/
>0.. 20
_
Voltage Follower
Transient Response
Vs = ±15V
II
25
~
Voltage Follower
Large Signal
Pulse Response
0.1
/
02
05 1.0
2
5
10
POWER OUTPUT-W
FREQUENCY-Hz
Output Short Circuit
Current as a
Function of
Junction Temperature
Peak Output Current as a
Function of
Output Voltage
800
Power supply-single 36 V
Temperature T J '" 25" C
0
500
I"--... .........,
0
0
I"--... .........,
400
I"--...
.........
300
I"--...
.........
1.....-1-...
V
V
1/
./
7
200
100
100
-50
FREQUENCY· Hz
50
100
JUNCTION TEMPERATURE-C
4·86
150
12
18
24
OUTPUT VOLTAGE-V
30
p,A759
Paralleling #'A759 Power OP Amps
Offset Null Circuit
0.50
VOUT
v0.50
Audio Applications
Low Cost Phono Amplifier
C2
10 pF
•
R3
25 k
v+
R1
47 k
~
CRYSTAL
CARTRIDGE'T
~''J~
1
CONT
V-
CONTROL
-=
Speaker
Impedance
(ohms)
Output
Power
(watts)
Min
Supply
(volts)
VoutP-P
4
8
16
32
.18
.36
.72
1.44
9
12
15
25
2.4
4.8
9.6
19.2
(volts)
Headphone Amplifier
~------------'-----------V+
VIN
180pF
22 k
10 k
2.2 k
4·87
----
-
-~
.--~-
...
--~
p,A759
Bidirectional Intercom System Using the
Power OP Amp
~A759
+12 V
2k
+12 V
t-......_+,10JLF
BALANCE
25 k
16 !1
25 JLF
(
:~II
VOLUME
2.7 k
-12 V
(-
:-11
-
+12 V
10 JLF
25 k
TONE
CONTROL
(OPTIONAL)
-=-
1
BALANCE
16!1
25 JLF
VOLUME
2.7 k
-12 V
-=Features
•
•
•
Circuit Simplicity
1 Watt of Audio Output
Duplex operation with only one two-wire cable
as interconnect.
4·88
TONE
CONTROL
(OPTIONAL)
JLA759
AC Servo Amplifier - Bridge Type
High Slew Rate Power OP Amp/Audio Amp
C
30
5k
50 k
VIN --.;iI-.J\,fI~""'----'lM--.
+28 V
n
10 pF
5.1 k
10 k
+28 V --A.JI/'V"....,--t
VOUT
-::-
5k
PO(MAX) (8 11) ~ 18 W
5.1 k
+28 V
5k
o
2 PHASE
SERVOMOTOR
3011
-13 V
*0.47 p.F
10 k
Features
• High Slew Rate 9 V I /ls
• High 3 dB Power Bandwidth 85 kHz
• 18 Watts Output Power Into an 8 D Load.
• Low Distortion - .2%, 10 VRMS, 1 kHz Into 8 D
Features
• Gain of 10
• Use of /lA759 Means Simple inexpensive Circuit
Design Consideration
• Av 2:: 10
Design Considerations
• 325 rnA Max Output Current
Servo Applications
DC Servo Amplifiers
5k
50 k
1
SERVOMOTOR
Features
• Circuit Simplicity
• One Chip Means Excellent Reliability
Design Considerations
IOUT:S 325 mA
•
4·89
----.-~--
--
•
f.LA759
Regulator Applications
Adjustable Dual Tracking Regulator
+VIN
+7 V to +35 V
-*
GND
1 JLF
I
2 JLF
-VIN
+VOUT
< 2 k
COMMON
CONTROL
IN
----1
1 JLF
5.6
1%
125k
79MG
-7 VI0-35 V
5.6 k
1%
OUT
Features
• Wide Output Voltage Range (± 2.2 to ± 30 V)
• Excellent Load Regulation .iVOUT < ±5 mV for
.iIOUT = ± 0.2 A
• Excellent Line Regulation .iOUT < ± 2 mV for
.iVIN = 10 V
4-90
"
-VOUT
J.LA759
Regulator Applications (Con't)
10 Amp - 12 Volt Regulator
VIN
1~25V--~----~-------------'
R1
12
Q1
2N2907
l
Q2
2N6125
R2
2k
Q3
SE9300
I
I
L
Q4
2N2612
+
151'F
l@25V
R4
0.03
n
t------. Your
12 k
=
12V
R5
9.1 k
R6
3k
Features
• Excellent Load and Line Regulation
• Excellent Temperature Coefficient-Depends
Largely on Tempco of the Reference Zener
4·91
.~----.-.---~----~
•
~A771·~A772·~A774
FAIRCHILD
Operational
Amplifier Family
A Schlumberger Company
Linear Products
J.l.A772 Connection Diagram
S-Pin DIP
Description
These monolithic JFET Input Operational Amplifiers
incorporate well-matched ion-implanted JFETS on the
same chip with standard bipolar transistors. The key
features of these op amps are low input bias currents
in the sub nanoamp range plus high slew rate (13 V / J.l.s
typically) and wide bandwidth (3.0 MHz typically).
•
•
•
•
LOW INPUT BIAS CURRENT-200 pA
LOW INPUT OFFSET CURRENT-100 pA
HIGH SLEW RATE -13 V / J.l.S TYPICALLY
WIDE BANDWIDTH-3.0 MHz TYPICALLY
-INA
OUTB
+INA
-INB
y
+INB
J.l.A771 Connection Diagram
B-Pin DIP
(Top View)
OFFSET
NULL
NC
-IN
y+
+IN
OUT
Order Information
Type
Package
J.l.A772AM
Ceramic
J.l.A772BM
Ceramic
J.l.A772A
Ceramic
J.l.A772B
Ceramic
J.l.A772
Ceramic
J.l.A772 A
Molded
J.l.A772B
Molded
J.l.A772
Molded
OFFSET
NULL
y-
Code
6T
6T
6T
6T
6T
9T
9T
9T
6T
9T
Code
6T
6T
6T
6T
6T
9T
9T
9T
Part No.
J.l.A772ARM
J.l.A772BRM
J.l.A772ARC
J.l.A772BRC
J.l.A772RC
J.l.A772ATC
J.l.A772BTC
J.l.A772TC
J.l.A774 Connection Diagram
14-Pin DIP
(Top View)
Order Information
Type
Package
J.l.A771AM
Ceramic
IlA771BM
Ceramic
J.l.A771A
Ceramic
J.l.A771 B
Ceramic
J.l.A771
Ceramic
J.l.A 771 A
Molded
J.l.A771B
Mo~ed
J.l.A771
Molded
J.l.A771L
Ceramic
J.l.A 771 L
Molded
y+
OUTA
OUTA
Part No.
J.l.A771ARM
IlA771BRM
J.l.A771ARC
J.l.A771BRC
J.l.A771RC
J.l.A771ATC
J.l.A771BTC
J.l.A771TC
J.l.A771LRC
J.l.A771 LTC
-IN A
+IN A
V+
+IN B
-IN B
OUT B
(Top View)
Order Information
Type
Package
J.l.A774L
Ceramic
J.l.A 77 4L
Molded
4·92
Code
6A
9A
Part No.
J.l.A774LDC
J.l.A774LPC
J.LA771 • J.LA772 • J.LA774
Absolute Maximum Ratings
Supply Voltage
Internal Power Dissipation
(Note 1)
Ceramic DIP
Molded DIP Package
Differential Input Voltage
Input Voltage Range (Note 2)
Output Short-Circuit Duration
Storage Temperature Range
Ceramic
Molded
± 18 V
Operating Temperature Range
Commercial
~AF77XA,~AF77XB,
~AF77X, ~AF77XL
670 mW
310 mW
±30 V
± 16 V
continuous
O°C to +70°C
Military
~AF77XAM,~AF77XBM
Pin Temperature
Molded DIP (Soldering, 10 s)
Ceramic DIP (Soldering, 60 s)
-55°C to +125°C
260°C
300°C
-65°C to +150°C
-55°C to +125°C
Equivalent Circuit
.---------------~----------~~--------~--------------------~----~~--~-v+
R,
R2
R3
R4
•
NOTE
R17
NOTE
R18
~~~--~~_+~--~~--4-+_----4-~--~~------~----------------~-------4--~V-
OFFSET NULL
OFFSET NULL
NOTE
NOTE
Note
I'A771 only
Notes
1. Rating applies to ambIent temperatures up to 70 D e above
TA = 70 De 5.6 mW / De for the minI DIP and 8.3 mW / De for
the DIP
2 Unless otherwIse specIfIed the absolute maxImum negatIve
Input voltage IS equal to the negatIve power supply voltage.
4-93
p,A771 • p,A772 • p,A774
DC Electrical Characteristics-Commercial Grade Devices
Symbol
Characteristic
Condition
The Following Specifications Apply for Vs
Unit
= ± 15 V, TA = 25°C
= 10 kn
= 25°C
(Notes 3, 4)Tj = 25°C
Vos
Input Offset Voltage
(Note 3) RS
10.0
15.0
mV
lOS
Input Offset Current
(Notes 3, 4) Tj
100
100
pA
18
Input
RIN
Input Resistance
AVOL
Large Signal
Voltage Gain
Isc
Short Circuit Current
IS
Supply Current
Bi~s
Current
50
200
50
10 12
Vo
= ± 10 V
RL
= 2 kn
50
100
50
25
Per Amplifier
The Following Specifications Apply for Vs
200
pA
10 12
n
100
V/mV
25
mA
2.8
2.8
mA
13
20
mV
= ± 15 V, O°C :$ TA 70°C
= 10 kn
Vos
Input Offset Voltage
(Note 3)
~Vos/~T
Average TC of
Input Offset Voltage
Rs
los
Input Offset Current
(Notes 3,4)
4.0
18
Input Bias Current
(Notes 3,4)
8.0
AVOL
Large Signal
Voltage Gain
Vo
= ± 10 V,
Vo
Output Voltage Swing
RL
RL
= 10 kn
= 2 kn
VCM
Input Common Mode
Voltage Range
CMRR
Common Mode
Rejection Ratio
Rs
= 10 kn
70
70
dB
PSRR
Supply Voltage
Rejection Ratio
RS
= 10 kn
70
70
dB
IS
Supply Current
Per Amplifier
RS
= 10 kn
10
RL
= 2 kn
25
± 12
±10
±12
±10
+15
-12
± 11
3.0
Notes
3 YOS. Ie and lOS are measured at YCM = O.
4. The Input bIas currents are junctIon leakage currents whIch
approxImately double for every 10'C increase In the lunction
temperature. TJ Due to limIted productIon test tIme, the Input
bIas currents measured are correlated to JunctIon temperature.
In normal operatIon the JunctIon temperature roses above the
ambIent temperature as a result of Internal power dlssipatoon,
,
25
± 11
j.LV/oC
10
4.0
nA
8.0
nA
1,.,
V/mV
V
V
+15
-12
V
3.0
mA
Po TJ = TA = 8JA Po where 8JA is the thermal resistance from
JunctIon to ambIent. Use of a heat sInk IS recommended If Input
bIas current IS to be kept to a minImum.
5 Supply voltage rejectIon ratIo IS measured for both supply
magnItudes Increasing or decreaSIng sImultaneously In
accordance with common practice.
4-94
J,LA771 • J,LA772 • J,LA774
DC Electrical Characteristics-Commercial Grade Devices
Symbol
Characteristic
Condition
Unit
The Following Specifications Apply for Vs = ± 15 V, TA = 25°C
= 10 kfl
= 25°C
4) Tj = 25°C
Vas
Input Offset Voltage
(Note 3) RS
2.0
5.0
lOS
Input Offset Current
(Notes 3, 4) TJ
50
50
pA
IS
Input Bias Current
(Notes 3,
100
pA
RIN
Input Resistance
AVOL
Large Signal
Voltage Gain
ISC
Short Circuit Current
Is
Supply Current
50
100
50
10 12
Va
=±
10 V
RL
= 2 kfl
50
100
50
10 12
fl
100
V/mV
25
25
Per Amplifier
mV
rnA
2.8
2.8
rnA
4.0
7.0
mV
The Following Specifications Apply for Vs = ± 15 V, O°C S TA 70°C
= 10 kfl
Vas
Input Offset Voltage
(Note 3)
~VOS/~T
Average TC of
Input Offset Voltage
Rs
lOS
Input Offset Current
(Notes 3,4)
2.0
2.0
nA
IS
Input Bias Current
(Notes 3, 4)
4.0
4.0
nA
AVOL
Large Signal
Voltage Gain
Va
=±
Va
Output Voltage Swing
RL
RL
= 10 kfl
= 2 kfl
VCM
Input Common Mode
Voltage Range
CMRR
Common Mode
Rejection Ratio
RS
= 10 kfl
80
80
dB
PSRR
Supply Voltage
Rejection Ratio
Rs
= 10 kfl
80
80
dB
IS
Supply Current
Per Amplifier
RS
= 10 kfl
10 V,
10
RL
= 2 kfl
jlV 1°C
10
25
25
V/mV
±12
±10
± 12
±10
V
V
±11
+15
-12
±11
3.0
+15
-12
V
3.0
rnA
Notes
Po TJ ; T A ; IIJA Po where IIJA IS the thermal resistance from
Junction to ambient Use of a heat Sink IS recommended If Input
bias current IS to be kept to a minimum
5 Supply voltage rejection ratio IS measured for both supply
magnitudes increasing or decreaSing simultaneously In
3 VOS. IS and lOS are measured at VCM ; 0
4 The Input bias currents are Junction leakage currents which
approximately double for every 10'C Increase In the Junction
temperature. TJ Oue to limited production test time. the Input
bias currents measured are correlated to Junction temperature
In normal operation the Junction temperature rises above the
accordance With common practice
ambient temperature as a result of Internal power diSSipation.
4·95
•
JlA771 • JlA772 • JlA774
DC Electrical Characteristics-Military Grade Devices
Symbol
Characteristic
Unit
Condition
The Following Specifications Apply for Vs = ± 15 V, TA = 25°C
Vos
Input Offset Voltage
RS = 10 kQ
(Note 3)
5.0
2.0
50
mV
50
pA
100
pA
los
Input Offset Current
(Notes 3, 4) Tj = 25°C
Is
Input Bias Current
(Notes 3,4) TJ = 25°C
RIN
Input Resistance
AVOL
Large Signal
Voltage Gain
Vo = ± 10 V,
Vo
Output Voltage Swing
RL = 10 kQ
RL = 2 kQ
VCM
Input Common Mode
Voltage Range
CMRR
Common Mode
Rejection Ratio
RS = 10 kQ
80
80
dB
PSRR
Supply Voltage
Rejection Ratio
RS = 10 kQ
80
80
dB
Is
Supply Current
Per Amplifier
50
100
50
10 12
RL = 2 kQ
::s
Q
50
50
V/mV
±12
±10
± 12
±10
V
V
±11
The Following Specifications Apply for Vs = ± 15 V, -55°C
10 12
+15
-12
±11
+15
-12
V
2.8
2.8
mA
5.0
8.0
mV
TA 125°C
(Note 3)
Vos
Input Offset Voltage
RS = 10 kQ
~Vos/~T
Average TC of
Input Offset Voltage
RS = 10 kQ
los
Input
(Notes 3,4)
20
20
nA
Is
Input Bias:Current
(Notes 3,4)
50
50
nA
AVOL
Large Signal
Voltage Gain
Vo = ± 10 V
Vo
Output Voltage Swing
CMRR
Offs~t
Current
10
IlVo IC
10
25
25
V/mV
RL = 10 kQ
RL = 2 kQ
±12
±10
±12
±10
V
V
Common Mode
Rejection Ratio
RS = 10 kQ
80
80
dB
PSRR
Supply Voltage
Rejection Ratio
RS = 10 kQ
80
80
dB
IS
Supply Current
Per Amplifier
Commercial and Military
AC Electrical Characteristics
RL = 2 kQ
3.4
3.4
mA
V S = ± 15 V, TA = 25 ° C
All Grades
Symbol
Characteristic
Condition
Min
SR
Slew Rate
(Figure 1)
13
V / IlS
GBW
Gain Bandwidth
Product
(Figure 2)
3.0
MHz
en
Equivalent Input
Noise Voltage
RS = 100 Q, f = 1000 Hz
16
nV/VHz
in
Equivalent Input
Noise Current
f = 1000 Hz
0.01
pA/VHz
Notes on preceding page
4-96
Typ
Max
Unit
J.LA 771 • J.LA 772 • J.LA 77 4
Typical Performance Curves
Output Voltage Swing vs.
Load Resistance
Output Voltage Swing vs.
Supply Voltage
JO
Open Loop
Frequency Response
0
r,
140
I--
-15V
25°C
V,
I
/
120
V
allOO
g.-30
/
5
0
Z
"
~
045
'\~~r-
0
60
Z
40
w
"'~"
20
o
05
01
50
10
10
SUPPLY VOLTAGE -
OUTPUT lOA.D - !l
TA
lK
10K
lOOK
1M
10M
100M
FREQUENCY - Hz
•
Slew Rate vs.
Temperature
25
Vs
llil 1lv
r-Rl
100
V
II
28
10
20
Gain Bandwidth
Product vs.
Temperature
Maximum Undistorted
Output vs. Frequency
"
15
10
180
'\
020
o
-135
"
"-
./
0
"
'\0&"
~
0
090
"
~~
g
/
1/
80
~
G
/
11
~
0
V
20
10K
"-
25°C
~
5
" '-.
\
.....
t-- -......,
10K
~
"- t--
1
1M
lOOK
"
10
o
1K
!15V
5
75
10M
-50
FREQUENCY - Hz:
25
25
50
75
100
125
AMBIENT TEMPERATURE - 'C
Small Signal Pulse Response
75
50
25
25
50
75
100
125
AMBIENT TEMPERATURE -' C
Input Bias Current
vs. Temperature
Bias Current
Warm-up Change
0
r, I "ocl
0
~
50
E
Vs =1",,:lSV
1M
Vs -- 415V
R, ~ 20
Cl = lOOpl
f\ ......
I
90%f T
0
/
0
/
0
0
~
~
I
~
()
,
lO'1l
10K
1K
"iii
100
ir~
10
~
I
1
25
50
75
100
TIME - NS
125
150
~150~-+--+-~--~--~-+--+-~
/
V
o
RISETIME =60
0
/
~100K
-
/
./'
i-"""
-50
25
25
50
75
CASE TEMPERATURE _ °C
4 97
0
100
125
TIME AFTER POWER SUPPLY TURN-ON -
MINUTES
•
p,A771 • p,A772 • p,A774
Typical Performance Curves (Cont.)
Maximum Common Mode
Input Voltage vs.
Supply Voltage
.
g~
.
0
Ys=±15Y
15
C
.,Ji.t,.~
o
'"
~
>
;:
5
in
.. /
V
~
50r--r~--t--r-1--t--r-i
/
~~:7
10
~'IJ"
.
Supply Current vs.
Temperature
~o
/ /
A.,."'i
+0;~
20r--r-1--+--r-1--+--r-1
10r--r-1--+--r-1--+--r-1
/
~
0
10
..0
15
-so
-25
0
25
50
75
100
125
AMBIENT TEMPERATURE _ 0 c
SUPPLY VOLTAGE· =V
Test Circuit
Input Offset Voltage Null Circuit (JLA771 only)
vTypical Applications
Fig. 1. Unity Gain Amplifier
Fig. 2. Gain-of-10 Inverting Amplifier
10 kfl
4·98
JLA776
Multi-Purpose
Programmable Op Amp
FAIRCHIL.D
A Schlumberger Company
Linear Products
Description
The IlA776 Programmable Operational Amplifier is
constructed using the Fairchild Planar epitaxial
process. High input impedance, low supply currents,
and low input noise over a wide range of operating
supply voltages coupled with programmable electrical
characteristics result in an extremely versatile
amplifier for use in high accuracy, low power
consumption analog applications. Input noise voltage
and current, power consumption, and input current can
be optimized by a single resistor or current source
that sets the chip quiescent current for nano watt
power consumption or for characteristics similar to
the IlA741. Internal frequency compensation, absence
of latch-up, high slew rate and short circuit current
protection assure ease of use in long time integrators,
active filters, and sample and hold circuits.
Connection Diagram
S-Pin Metal Package
ISET
>-~OOUT
-IN
v(Top View)
Order Information
Type
Package
IlA776
Metal
IlA776C
Metal
• MICROPOWER CONSUMPTION
• ± 1.2 V to ± 1S V OPERATION
• NO FREQUENCY COMPENSATION REQUIRED
• LOW INPUT BIAS CURRENTS
• WIDE PROGRAMMING RANGE
• HIGH SLEW RATE
• LOW NOISE
• SHORT-CIRCUIT PROTECTION
• OFFSET NULL CAPABILITY
• NO LATCH-UP
Code
5W
5W
Part No.
IlA776HM
IlA776HC
Connection Diagram
S-Pin DIP
8
OFFSET
NULL
ISET
-IN
v+
+IN
OUT
OFFSET
NULL
v-
(Top View)
Order Information
Type
Package
IlA776C
Molded DIP
4·99
-----._-----
Code
9T
Part No.
IlA776TC
•
JlA776
Absolute Maximum Ratings
Supply Voltage
± 18 V
Internal Power
Dissipation (Note 1)
500 mW
Metal Package
310 mW
DIP
Differential Input Voltage ± 30 V
Input Voltage (Note 2)
± 15 V
Voltage Between Offset
Null and V±0.5 V
ISET (Maximum Current
at ISET)
500 IlA
VSET (Maximum Voltage
to Ground at ISET)
(V+ -2.0 V)
Storage Temperature
Metal Package
DIP
Operating Temperature
Military (IlA776)
Commercial (IlA 776C)
Pin Temperature
(Soldering)
Metal Package (60 s)
DIP(10s)
Output Short Circuit
Duration (Note 3)
:s
VSET
:s
-65°C to +150°C
-55°C to +125°C
-55°C to +125°C
O°C to +70°C
300°C
260°C
Indefinite
V+
Equivalent Circuit
ISET
.---------------~~----_.----~----~--~------._------------------~-------v+
R3
2 kn
INVERTING
INPUT
R4
50 II
Cl
R5
100 II
OUTPUT
R7
100 n
OFFSET
NULL
OFFSET
NULL
R6
100 II
RS
50 II
Q24
Rl
R2
10 kll
10 kll
~----~--------~----~~----~--~--------~~----------------~------V-
Notes
3. Short Circuit may be to ground or either supply. Rating applies
to +125°C case temperature or +75°C ambient temperature
for ISET :'5 30 !lA.
1. Ratmg applies to ambient temperatures up to 70°C. Above
70°C ambient derate linearly at 6.3 mW / °C for Metal Can.
8.3 mW / °C for the DIP, and 5.6 mW / °C for the Mmi DIP
2. For supply voltages less than ± 15 V, the absolute maximum
mput voltage is equal to the supply voltage.
4·100
JlA776
± 15 V Operation for IJ.A776
Electrical Characteristics TA = 25 ° C, unless otherwise specified.
ISET
Condition
= 1.51J.A
Min
Typ
'SET
Min
= 15IJ.A
Typ
Characteristic
Input Offset Voltage
Rs :::5 10 kll
2.0
Max
5.0
Input Offset Current
Rs :::5 10 kll
0.7
3.0
2.0
15
nA
2.0
7.5
15
5.0
50
nA
Input Bias Current
Input Resistance
50
2.0
Input Capacitance
Offset Voltage
Adjustment Range
9.0
Large Signal Voltage Gain
= ± 10 V
= ± 10 V
RL ;::: 75 kll, Your
RL ;::: 5 kll, Your
5.0 k
3.0
Supply Current
20
Power Consumption
Slew Rate
Output Voltage Swing
= 20 mV, RL ;::: 5 kll,
= 100 pF
± 12
Input Bias Current
Supply Voltage
Rejection Ratio
Large Signal Voltage Gain
Output Voltage Swing
18
mV
V/V
25
160
= +125°C
TA = -55°C
TA = +125°C
TA = -55°C
RL ;::: 75 kll, Your
RL;::: 75 kll
IJ.S
%
0.8
V/lJ.s
V
± 13
V
6.0
6.0
mV
15
nA
10
40
nA
7.5
50
nA
120
nA
±10
= ± 10 V
70
90
25
RS:::5 10 kll
150
V
90
25
dB
150
IJ.VIV
100 k
75 k
V/V
±10
±10
V
Supply Current
30
200
Power Consumption
0.9
6.0
4·101
IJ.A
mW
0.35
10
20
70
180
5.0
±10
RS :::510 kll
VIV
Il
mA
5.4
±10
TA
Input Voltage Range
Common Mode
Rejection Ratio
pF
± 14
RL ;::: 5 kll
The following specifications apply -55°C -< TA -< +125°C
Input Offset Voltage
RS :::5 10 kll
Input Offset Current
mil
100 k 400 k
1.0 k
12
1.6
0
0.1
RL ;::: 5 kll
RL;::: 75 kll
Unit
mV
2.0
0.75
Rise Time VIN
Overshoot CL
Max
5.0
200 k 400 k
Output Resistance
Output Short-Circuit Current
Transient
Response
(unity gain)
2.0
IJ.A
mW
•
JLA776
± 3 V Operation For p,A776
Electrical Characteristics TA = 25°C , unless otherwise specified
ISET
= 1.5 p,A
ISET
= 15 p,A
Min
Typ
Max
Unit
2.0
5.0
mV
3.0
2.0
15
nA
7.5
15
50
5.0
nA
Mg
2.0
pF
18
mV
Typ
Max
2.0
5.0
Input Offset Current
0.7
Input Bias Current
2.0
Input Resistance
50
Input Capacitance
Offset Voltage
Adjustment Range
2.0
9.0
Characteristic
Condition
Input Offset Voltage
Rs:5 10 kg
Large Signal Voltage Gain
Min
= ± 1V
=± 1V
RL ~ 75 kg, Your
RL
~
5 kg, Your
50 k
200 k
V/V
50 k
200 k
V/V
g
Output Resistance
Output Short-Circuit Current
5.0 k
Supply Current
13
20
130
160
p,A
Power Consumption
78
120
780
960
p,W
Transient
Response
(unity gain)
3.0
Rise Time VIN = 20 mV, RL
100 pF
Overshoot CL
Slew Rate
=
RL
~
~
5 kg,
5 kg
Input Bias Current
p,s
0.6
0
5
010
0.03
0.35
V/p,s
6.0
6.0
mV
15
nA
TA = -55°C
10
40
nA
TA = +125°C
7.5
50
nA
120
nA
TA
= +125°C
= -55°C
20
± 1.0
Common Mode
Rejection Ratio
Rs :510 kg
Supply Voltage
Rejection Ratio
Rs:5 10 kg
Output Voltage Swing
rnA
5.0
TA
Input Voltage Range
Large Signal Voltage Gain
5.0
3.0
The following specifications apply for -55°C --< TA --< +125°C
Rs:5 10 kg
Input Offset Voltage
Input Offset Current
1.0 k
70
± 1.0
86
25
=± 1V
= ± 1V
RL
~
75 kg, Your
RL
RL
~
~
5 kg, VOUT
75 kg
RL
~
5 kg
70
150
V
86
25
dB
150
25 k
p,VIV
VIV
VIV
25 k
±2.0 ±2.4
V
± 1.9 ±2.1
V
p,A
Supply Current
25
180
Power Consumption
150
1080 p,W
4-102
J.LA776
± 15 V Operation for J.LA 776C
Electrical Characteristics TA = 25 ° C, unless otherwise specified
ISET
= 1.5 J.LA
ISET = 15 J.LA
Typ
Max
Typ
Max
2.0
6.0
2.0
6.0
mV
0.7
6.0
2.0
25
nA
Input Bias Current
2.0
10
15
50
nA
Input Resistance
50
5.0
Mn
Input Capacitance
2.0
2.0
pF
Offset Voltage
Adjustment Range
9.0
18
mV
400 k
V/V
kn
Conditions
Characteristic
Input Offset Voltage
Min
Rs ::5 10 kn
Input Offset Current
Large Signal Voltage Gain
Your = ± 10 V
Your = ± 10 V
50 k
RL 2: 75 kn,
RL 2: 5 kn,
Min
VIV
400 k
50 k
Output Resistance
5.0
1.0
Output Short-Circuit Current
3.0
12
Supply Current
20
30
Power Consumption
Transient
Response
(unity gain)
=
VIN
20 mV, RL 2: 5 kn,
Overshoot CL ::5 100 pF
Slew Rate
Output Voltage Swing
RL ::5 5 kn
±12
RL 2: 75 kn
0.35
10
J.LS
%
0.1
0.8
V/J.Ls
± 14
V
±10
= +70°C
TA = O°C
TA = +70°C
TA = O°C
TA
Input Voltage Range
RS ::5 10 kn
Supply Voltage
Rejection Ratio
RS ::5 10 kn"
Large Signal Voltage Gain
RL 2: 75 kn,
Output Voltage Swing
RL 2: 75 kn
70
= ± 10 V
V
7.5
7.5
mV
25
nA
10
40
nA
10
50
nA
20
100
nA
V
±10
90
25
Your
±13
6.0
±10
Common Mode
Rejection Ratio
5.7
70
200
90
25
50 k
50 k
± 10
±10
dB
200
V
35
200
Power Consumption
1.05
6.0
4-103
--~
.. -
----~
.------
J.LVIV
VIV
Supply Current
..
J.LA
mW
1.6
RL 2: 5 kn
Input Bias Current
mA
190
0
The following specifications apply O°C -< TA -< +70°C
Input Offset Voltage
RS ::5 10 kn
Input Offset Current
160
0.9
Rise Time
Unit
J.LA
mW
•
JLA776
±3 V Operation For /LA776C
Electrical Characteristics TA = 25 ° C, unless otherwise specified
Characteristic
Condition
Input Offset Voltage
Rs ::5 10 kn
ISET = 1.5 /LA
ISET = 15 /LA
Min
Min
Typ
Max
Typ
Max
2.0
6.0
2.0
6.0
mV
0.7
6.0
2.0
25
nA
Input Bias Current
2.0
10
15
50
nA
Input Resistance
50
5.0
mn
Input Capacitance
Offset Voltage
Adjustment Range
2.0
2.0
pF
9.0
18
mV
Input Offset Current
Large Signal Voltage Gain
±1V
RL
~
75 kn, VOUT =
RL
~
5 kn, Your = ± 1 V
25 k
200 k
Unit
VIV
25 k
200 k
VIV
kn
Output Resistance
5.0
1.0
Output Short-Circuit Current
3.0
5.0
Supply Current
13
20
130
170
/LA
Power Consumption
78
120
780
1020
/LW
Transient
Response
(unity gain)
VIN = 20 mV, RL
Overshoot CL ::5 100 pF
Rise Time
Slew Rate
~
5 kn,
RL ::5 5 kn
3.0
0.6
0
5
/LS
%
0.03
0.35
V / /LS
The following specifications apply for O°C -< TA -< +70°C
Input Offset Voltage
RS ::5 10 kn
Input Offset Current
Input Bias Current
TA = +70°C
7.5
mV
6.0
25
nA
10
40
nA
TA = +70°C
10
50
nA
100
nA
TA = O°C
20
± 1.0
Common Mode
Rejection Ratio
Rs ::510 kn
Supply Voltage
Rejection Ratio
Rs ::5 10 kn
Output Voltage Swing
7.5
TA = O°C
Input Voltage Range
Large Signal Voltage Gain
mA
RL
~
70
75 kn, Your = ± 1 V
~
70
86
25
RL ~ 5 kn, Your = ± 1 V
RL ~ 75 kn
RL
± 1.0
200
V
86
25
dB
200
25 k
/LV IV
V/V
25 k
VIV
±2.0 ±2.4
V
±2.0 ±2.1
5 kn
V
Supply Current
25
180
Power Consumption
150
1080 /LW
4-104
/LA
JLA776
Typical Performance Curves for IJ.A776 and IJ.A776C
Input Bias Current as a
Function of
Set Current
10
Input Bias Current as a
Function of
Ambient Temperature
0
LIJJ5.J I III
o
"'30 V < Vs
<'
Input Offset Current as a
Function of
Ambient Temperature
5
+3~V~VS!:!:1Jy
+1' V
1.1
0
1/
"-
•
o1
001
01
10
o
-eo
100
w
"
i
...
~
o
~1 ~ 2;.C I I I I
';.
::!:30 V :S Ys :S 1:18 V
."
v!
I 400
=
g
0
140
-60
~
r-....
i',
...0
~
i!!
......
!
w
0
./
-10 0
"~ -200 _/"
~
%
}'0v l,_
'"
20
100
60
140
Input Noise Voltage as a
Function of
Set Current
£
~
10-".~9
TA
25°C
+30 Y:S Ys < +18 Y
f
1 kHz
.lot
1 Hz
10-13
I
."
.
W
V
100
-20
-
TEMPERATURE _ °C
V
200
-
I"....!.,LJ5'A- r-
- -
ISET '" 15,u.A
!:; 300
~ -300
"h..
,-
100
000
w
I""'-
~ -100
i!!
!:;
10-14
0
>
V
w
10-15
:>
g
z
i
10- 1 6
%
(J
0_ 30
5
10
ISET -
10-1
.
'!'(ISE)·
~
1S IlA)
W
o"'z
.
~ 10-1 6
:>
g
" '-
.........
c:
'"
...I
z
:>
~
!!!
z
0
10-25 ~
-
0
10-1
,
10
100
10 k
1 k
FREQUENCY -
Hz
10-17
00.
10-27
100 k
IJA
100
\.
w
0
z
:>
~
100
10
SET CURRENT -
Optimum Source Resistor for
Minimum Noise as a
Function of Set Current
"
z
w
-
01
ISET -
(J
0
I
15 lolA)
140
.iii
...
"" 25°C
. ,..::l 10-291-H-f+-++H+4TA
if
~;E~~~~~!E+3~oivll<~v~s~<~+~,,~v:,t
c:
In2(ISET '" 15 ,u.A)
In2(ISEl
100
£
. .
.15
\:
I I I
z
,.
::l
60
.,
151,AI±:::
e~21ISE! I
g
20
Input Noise Current as a
Function of Set Current
TA '" 25°C
5
-20
TEMPERATURE _ °C
IJ.A
1+3olv ,J,,±\.v
w
"~ 10-1
0
-eo
100
SET CURRENT -
Input Noise Voltage and
Current as a
Function of Frequency
£
eo
20
NSET"'5/J.A
2
15ET=15.u.6:_
-20
I"
C-
Change in Input Offset
Voltage as a Function of
Ambient Temperature (Unnulled)
300
10 0
-
15 jJ.A
TEMPERATURE _ °C
Change in Input Offset
Voltage as a Function of
Set Current
500
=
"- I'
--
ISET - SEY CURRENT - J.l.A
';.
IseT
l'o..
/
\
3
"-
V
,
'310vlvs~ "lv
4\
4 ......
~
1
0
z
.lot
1 Hz
11kHz
10-30
001
01
ISET -
10
SET CURRENT -
4-105
jl.A
100
o1
001
10
01
ISET -
SET CURRENT -
jl.A
100
•
JLA776
Typical Performance Curves for p.A776 and p.A776C (Cont.)
Output Voltage Swing as a
Function of
Load Resistance
..
.
"
""
11
0
K. ""
'Yj i '5t
~
Ys=±15Y
I-
~
~
UL.!.v
6
"Irc
~
~
I-
1S "A S ISET S 151lA
•••
....
1111
•••
lOAD RESISTANCE -
o"
1111
'M
~
~
.... •
~
~
9 200 .i.--'
I-"'
z
r,OD •
~~5=1'7~ ~!~SET:S; 15 ,uA~
~.
.
,ai-""
2
.V
:0;.00
b
ISET '" 1 5 j.lA
!
~
±9
_12
+
_15
+
:c
"~
Rl == 5 kll "",
" ....
........
".,.
2.
2•
12M
15ET"'15",,- ~ ~
RL=75kfl
•o.
_18
+
••
ISET -
SET CURRENT -
600
±3Q v:s Vs:S 18 Y
TA = 25°C
400
2••
..
'00
•••
'1'
....
•
•..
-
ISET -; 15 "A
Vs
+15 V
Vs
±30 V-I--
•
•
~=±A ~ ~ Il-
..... .....
Rl=75kn
2.
-2D
100
80
~ BOO
~
~800
>
r-r-r-+-+-+-+-1-1--r~
i .. I-+-~-+~t-+-~-+~-~
. ~~~:;~~f:~v~s;-;±~. ~~;;;~~
ISET '" 15 pA
.1
Vs
±3.0 v
~~.~~-2O~~~2D~~~..~~~
...
~~
...
TEMPERATURE _ °C
V
Iii
/
~
•••••
~
~
"~
IseT -
••
SET CURRENT -
4-106
/J.A
~.c '2~.C
1
~
•
40
~
••
/
I
•
-20
-
Ys=±15V
..1·',-..
InltialOllyt
Vt"i
(J
'00
•••
J.tA
-- --
~200
•
SET CURRENT -
Thermal Response of Input Offset
Voltage to Step
Change of
Case Temperature
+18 Y
10
••
ISET -
.20 -
-""""
•••
140
Standby Supply Current as a
Function of
Set Current
<
~ f-of-
•
TEMPERATURE _ °C
.... F~;O :5;~s
.00
p.A
Power Supply Rejection
Ratio as a Function of
Set Current
,
RL=Sr n I
1M
.9g ... •
z
~
o
Supply Current as a
Function of
Ambient Temperature
... r-.,.-,......,.-,-,-,......,.-,-r-,
1 _
CIlI
•
V
~ET=15I'A'
~
TEMPERATURE _ °C
B
1/
Vs = ±15 Y
_~SET == 15 p.A
i-'
v/ ./
Vs-±30V
•
'4M
•
~
10
Z
:!:6
Vs - ±15
~
RL '" 5 kU
~
_3
+
I I
1 M
~
V
~~
8
g
V
Open Loop Voltage Gain as a
Function of
Ambient Temperature
z
o
....
=T~ ~ J~·c
~
I
W
SUPPLY VOLTAGE -
•
~400
4
RL "" 5 kfl
Ys=±30V
••• •
500
•
ISET =-',5 J.lA
n
Open Loop Voltage Gain as a
Function of
Ambient Temperature
z
•• M
TA '" 25°C
! 2•
•
~"
1.1
.2
:l"
>
I
ISET = 15 JJA
V
Gain-Bandwidth Product as a
Function of
Set Current
2
I"'" -+-T"
Vs "" ±15 Y
i
."i
,.·c ......
TA
>
I
Output Voltage Swing as a
Function of
Supply Voltage
2.
4.
<
TIME FROM HEAT APPLICATION -
•
,."A776
Typical Performance Curves for /lA776 and /lA776C (Cont.)
Stabilization Time of Input
Offset Voltage From
Power On
Input Offset Voltage
Drift as a
Function of Time
':.
.~
..
"
~ 100
I
!:;
0
~
1/
-10
I;;
~
l';
-20
.
..
".
!!;
!!;
z
J:
=
~'1 ~_
0
TA = 12S"C
8
I'll
0
1
Ys
>
J
...::>
Js
o
V
1/
>
Slew Rate as a
Function of
Set Current
5
60
It
o
~
40
/
V
IV
1
VS - ±3.0
!!;
-30
/
..
TA = 25°C
"~
Vs=±15V
-40
InTal
0
-1
0
1
2
3
I"·et\ YO'i l' 0('V
ge
4
5
6
7
20
I
9
0
200
TIME FROM POWER APPLICATION - MIN
400
TIME -
Set Current as a
Function of
Set Resistor
600
800
1000
0001
001
V
HRS
v+
ISET
10 M
......
.>
1 M
100 k
II
10
k
" ....
Vs = ±3 yt-
l!"
10 Y_
-II ir" 'f
GjD
10
100
10
± 1.5 V
1.7 MO
170 kO
±3.0V
3.6MO
360 kO
V+ -0.7
ISET = RSET
±6.0V
7.5 MO
750 kO
where RSET is connected to ground.
± 15 V
20MO
2.0 MO
Note
The /lA776 may be operated with RSET
connected to ground or V-
.
I
32
"~
24
...>::>
11
0
V""-
40
I!:::>
0
Ys=±15Y
ISET = 15 Jl.A
= 5 kn
CL = 100 pF
I
'k
I
I
I
I
I--
-I
15
TIME -
v-
15/lA
.6
E
ISET =
-0.7 RSET
1.5/lA
Voltage Follower Transient
Response (Unity Gain)
41
p.A
Vs
ISET -p.A
>
100
10
SET CURRENT -
ISET Equations
100 M
Vs - +15 Y
01
ISET -
Quiescent Current Setting Resistor
(ISET to V-)
....
V
1/
00 1
v
II
J:
o
8
.c.
+15 Y
TREND LINE
25
JI.'
4·107
where RSET
IS
connected to V-
•
JLA776
Biasing Circuits
Voltage Offset Null Circuit
Resistor Biasing
>---6
3
100 k!l
~·-_-v-
2
Your
RSET
FET Current Source Biasing
v-
"::"
2
6
3
RSET Connected to Ground
v+
1----vG
Your
v-
3
RSEr
Transient Response
Test Circuit
vRSET Connected to Vo Recommended for supply voltages less than ± 6 V.
>-....- _ - - - Your
Transistor Current Source Blasing
RL
2
6
3
v-
r---vs
v-
4-108
J.LA791
FAIRCHILD
Power
Operational Amplifier
A Schlumberger Company
Linear Products
Connection Diagram
10-Pin Metal Package
Description
The IlA791 is a High Performance Monolithic
Operational Amplifier constructed using the Fairchild
Planar Epitaxial process with input characteristics
similar to the IlA 741 operational amplifier and 1A
available output current. It is intended for use in a wide
variety of applications including audio amplifiers,
servo amplifiers, and power supplies. The high gain
and high output power capability provide superior
performance wherever an operational amplifier I power
booster combination is required. The IlA791 is
thermal-overload and short-circuit protected.
v(SHORTED
TO CASE)
-IN
"""-Ir-"""",J +IN
v+
CURRENT SENSE
•
•
•
•
•
CURRENT OUTPUT TO 1 A
SHORT-CIRCUIT PROTECTION
OFFSET VOLTAGE NULL CAPABILITY
NO LATCH UP
LARGE COMMON MODE AND DIFFERENTIAL
MODE RANGES
• THERMAL-OVERLOAD PROTECTION
(Top View)
Order Information
Type
Package
IlA791C
Metal
IlA 791
Metal
Code
5H
5H
Part No.
IlA791KC
IlA791KM
Equivalent Circuit
V
COMPENSATION
2
4
08
R13
NON-INVERTING
INPUT
CURRENT
SENSE
R5
t--------t-- 3
R7
5 pF
r~----i OUTPUT
THERMAL
SHUTDOWN
03~--~E-------~
1
R9
R10
D2
~--.,.....--+---~-'i::'013
06
Q7
OFFSET
ADJUST
8
R12
Rl
R2
R3
R4
R6
,.
v-
COMPENSATION
Note
Pin connections shown are for metal can.
4·109
J.LA791
Absolute Maximum Ratings
Supply Voltage
Military (j.lA791)
Commercial (j.lA791C)
Peak Output Current
Continuous Internal Power
Dissipation (Total Package)
(Note 1)
Peak Internal Power Dissipation
(Per Output Transistor for
t :$ 5 s, Note 2)
Differential Input Voltage
Input Voltage (Note 3)
Voltages between offset
Null and VOperating Junction Temperature
Military (j.lA791)
Commercial (j.lA791C)
Storage Temperature
Metal Package
Pin Temperature
Metal Package (Soldering,
60 s max.)
j.lA791 and j.lA791C
Electrical CharacteristiCs
Vs
±22 V
± 18 V
1.25 A
.Internally Limited
Notes
1 Thermal resistance of the packages (without a heat sink)
15 W
±30 V
± 15 V
Package
±0.5 V
-55°C to +150°C
O°C to +125°C
Junction
to Case
Typ
Max
TO·3
4
280°C
Output Short Circuit Current
40
°CtW
= ± 15 V, TJ = 25°C unless otherwise specified
j.lA791
Output Voltage Swing
35
Unit
2. Under short circuit conditions, the safe operating area and dc
power dissIpation limitations must be observed.
3. For supply voltages less than ± 15 V, the absolute maxImum
input voltage is equal to the supply voltage.
-65°C to +150°C
Characteristic
Condition
Input Offset Voltage
Rs:$ 10 kO
Input Offset Current
Input Bias Current
Input Resistance
Offset Voltage
Adjustment Range
Input Voltage Range
Common Mode
Rejection Ratio
Power Supply Rejection Ratio
Large Signal Voltage Gain
6
Junction
to Ambient
Typ
Max
=
=
=
=
=
Min
Typ
0.3
1.0
20
80
2.0
Max
5.0
200
500
j.lA791C
Typ
Min
2.0
20
80
0.3
1.0
± 15
± 12
±13
± 12
70
=
=
Supply Current (Zero Signal)
50k
50 k
± 12
±10
mV
± 13
V
dB
150
j.lVtV
30
VIV
VIV
V
V
mA
mA
mA
20 k
20 k
± 11.5 ±14
±10 ± 12.2
1000
500
25
4·110
MO
70
±14
± 12.2
1000
500
Units
mV
nA
nA
± 15
150
=
=
AL
1 kO, VOUT
± 10 V
RL
100, VOUT
± 10 V
Rse 0, RL
1 kO
10 0
Rse 0, RL
Ase 0.7 0
Rse = 1.50
Max
6.0
200
500
JLA791
IlA791 and IlA791C
Electrical Characteristics (Cont.)
The following specifications apply for -55°C :5 TJ :5 150°C
IlA791
Typ
Min
Characteristic
Condition
Input Offset Voltage
Rs:5 10 kn
Input Offset Current
Input Bias Current
Common Mode
Rejection Ratio
Power Supply Rejection Ratio
70
Output Voltage Swing
Max
7.5
300
800
Units
mV
nA
nA
70
dB
150
150
IlV/V
VIV
VIV
V
V
mA
15 k
15 k
±10
±10
25 k
25 k
±10
±10
RL = 1 kn, VOUT = ± 10 V
RL = 10 kn, VOUT = ± 10 V
Rsc= 0, RL = 1 kn
RSC = 0, RL = 10 kn
Large Signal Voltage Gain
}lA791C
Typ
Min
Max
6
500
1.5
Supply Current (Zero Signal)
30
30
•
Typical Performance Curvea for
IlA791 and IlA791C
Input Blaa Current aa a
Function of
Junction Temperature
3.0
150
V=~15V
:\
v=
...
~ 100
a:
--
"
0
20
TJ -
20
~
~
60
100
o
140
180
--80
\
!;
-20
20
&0
100
I
~ 25
140
180
!-IV
1I
II
o"
f-
I/.
lour.:: 0
~ 50
"-............
TJ -
Voltage Gain aa a
Function of
Power Supply Voltage
:3a:
\.
50
JUNCTION TEMPERATURE _ °C
I
I
!!! 75
~
r--
•
;!
!;
.........
12
~15 v
1\
t;
\
0
Output Realatance aa a
Function of
Frequency (Open Loop)
1100
i:l
\.
0
50
60
Input Offaet Current aa a
Function of
Junction Temperature
lOUT::' 0
II
•
100
1 k
10 k
100 k
FREQUENCY -
JUNCTION TEMPERATURE _ °C
Power Supply Rejection Ratio aa a
Function of Frequency
75
TJ '"
.0
~5~C
TJ:
.
80
. / ~.oc
~V
r-.
10-1
,,/ V
40
15
20
POWER SUPPLY VOLTAGE -
25
±V
30
1.
=
TJ
+\~Iv
25"C
I
,
"
2'
10
vi
10-1
60
!~oc
II
V ~ ~15 Y
T, = 25°C
t--
10 M
Input Nolae Voltage aa a
Function of Frequency
10-1 3
100
1 M
Hz
10-' 6
100
1 k
10 k
FREQUENCY -
4-111
Hz
100 k
1 M
1.
..
,
I
1. k
1 k
FREQUENCV -
Hz
100 k
J.tA791
Typical Performance Curves for
#A791 and #A791C (Cont.)
Total Noise (20 Hz-20 kHz) as a
Function of
Junction Temperature
Input Noise Current as a
Function of Frequency
,
10 ,
100 kll
25°C
V
0
"15 V
3
r=: G11N
I
.". ",A791
2D Hz -
10
20 kHz
R,
R,
R,
GAIN - 1000
GAIN - 100
GAIN
10
GAIN -
100 Jl
1k!1
10 kJl
~oo
10
100
10 k
1k
FReQUENCY -
100 k
-20
Hz
TJ -
g
100
o
75
il
5
"
'I I
V
td < 20
w
~ 75
/ I
~
g
...~
II
I
I
:3
o
r-
/
-15
-os
-10
lOUT -
I
...
1000
05
ii
s
"'- ...........
0
as
Rsc -
A
Power Bandwidth as a
Function of
Closed Loop Gain
10
15
100
V
~ 25 0
co
o
30
·50
(1
~
z
10
25
CLOSED LOOP GAIN
100
130 Jl
C--
I -- r-=:
75
100
125
°C
I--
~
"~ 40
CLOSED LOOP GAIN
100
RL = 110 TJ = 25°C
I,
5 pF
~
~
10
tl
UI =1":5 I
Cc
> 60
4-112
1'57- C--
Cc - 0
.... I--
o
V
1
10
50
III
III
0
~100
~
•
Rse
~ I-
JUNCTION TEMPERATURE -
z
,/
V
--
--
-
~ !I
160
w
•L
~ ........
I
-25
,.
"~ 80
:l
1500
-.::mA
- r
Rse.
TJ -
~
Q
-t 10
1250
Voltage Gain as a
Function of Open Loop
Frequency Response
2S C
/'
~
--~
--
112<1
:I: 100 k
~
o
TJ -2SoC-
=
"I
ffi
r--....
v; ";5V_
v', ' 11!"II
RL
TJ
1000
--
~
25
750
r---
i:i
Slew Rate as a
Function of
Closed Loop Gain
1 M
500
--
-
750
~ 500
20
J1
...........
:;
CURRENT SENSE RESISTOR -
-1'5
OUTPUT CURRENT -
['---.
...
25 0
10
OUTPUT CURRENT -
~a
\
75 0
~
o
20
<
250
I 1000
(j 500
/
Vto
"E
~
:;
~
I
IV
de
1-75
1250
:3
Rsc"'30U
Short Circuit Current as a
Function of
Case Temperature
~125 0
~
o
lOUT -
...
de
v
-Rsc
140
1500
>
I
1~15
Rsc-062n
25
100
60
..-
I-
I
20
r-- r--
JUNCTION TEMPERATURE _ °C
Short Circuit Current as a
Function of
Current Sense Resistor. RsC
Output Safe Operating
Area per Output Transistor
--...JVVv-.....--VOUT
Notes
3.0 V to 27 V regulator
500 rnA output current
DC Servo Amplifier
5 k
50 k
10 pF
r
+15 V
3.911
SIZE 8 OR 9 12 Vdc
SERVOMOTOR
AC Servo Amplifier Bridge Type
5 k
VIN
50 k
0--1 t--'V'I'v---...,...---.JV'.I'v-----,
10 k
+28 V --.....,..,.,.--.....-------1
5 k
o
SERVOMOTOR
1.5 II
10 k
4·114
JlA798
Dual Operational
Amplifier
FAIRCHIL.D
A Schlumberger Company
Linear Products
Connection Diagram
8-Pln Mini DIP
Description
The /LA798 is a monolithic pair of independent, high
gain, internally frequency compensated operational
amplifiers designed to operate from a single power
supply or dual power supplies over a wide range of
voltages. The common mode input range includes the
negative supply, thereby eliminating the necessity for
external biasing components in many applications.
The output voltage range also includes the negative
power supply voltage. They are constructed using the
Fairchild Planar epitaxial process.
•
•
•
•
•
•
•
•
•
•
v+
OUT A
INPUT COMMON MODE VOLTAGE RANGE
INCLUDES GROUND OR NEGATIVE SUPPLY
OUTPUT VOLTAGE CAN SWING NEAR GROUND
OR NEGATIVE SUPPLY
INTERNALLY COMPENSATED
WIDE POWER SUPPLY RANGE SINGLE SUPPLY
OF 3.0 TO 36 V
DUAL SUPPLY OF ± 1.5 V TO ± 18 V
CLASS AB OUTPUT STAGE FOR MINIMAL
CROSSOVER DISTORTION
SHORT CIRCUIT PROTECTED OUTPUT
HIGH OPEN LOOP GAIN 200 k
EXCEEDS 1458 TYPE PERFORMANCE
OPERATION SPECIFIED AT ± 15 V AND +5 V
POWER SUPPLIES
HIGH OUTPUT CURRENT SINK CAPABILITY
0.8 mA AT VOUT = 400 mV
-IN A
OUT B
+IN A
-IN B
v-
+IN B
(Top View)
Order Information
Type
Package
/LA798C
Molded DIP
Part No.
/LA798TC
Code
9T
Equivalent Circuit (1/2 of circuit shown)
V+~--------------
__
~
______________________
~
______
~
______
~
________- ,
R1
1 k
INVERTING
INPUT
2 (6)
V_~4~__~____~____~____~~+-
____
~~
__________ ______ __ ____ __ __
3 (5)
NON-INVERTING INPUT
4·115
~
~
~
~
~
~
•
J.LA798
Absolute Maximum Ratings
Supply Voltage Between
V+ and V36 V
Differential Input Voltage (Note 1) ±30 V
-0.3 V (V-) to V+
Input Voltage (V-) (Note 1)
310 mW
Internal Power Dissipation
(Note 2)
Operating Temperature Range
Commercial (C)
O°C to +70°C
Storage Temperature Range
-55°C to +125°C
260°C
Pin Temperature
(Note 5)
(Soldering, 10 s)
Output Short Circuit Duration
Notes
1. For supply voltage less than 30 V between V+ and V-. the
absolute maximum input voltage is equal to the supply voltage.
2. Rating applies to ambient temperature up to 70 oe. Above
TA = 70 oe, derate linearly 5.6 mw/oe for the Molded DIP.
3. Not to exceed maximum package power dissipation.
4. Output wIll swing to ground.
5. Indefinite on shorts to ground or V- supply. Shorts to V+
supply may result in power dissipation exceeding the absolute
maximum rating.
4-116
p,A798
~A798C
Electrical Character/stlcs
Vs = ± 15, V, TA = 25°C unless otherwise noted.
Typ
Max
Input Offset Voltage
2.0
6.0
mV
Input Offset Current
10
50
nA
-50
-250
nA
Characteristic
Min
Condition
Input Bias Current
Input Impedance
f = 20 Hz
Input Common Mode Voltage Range
Unit
0.3
1.0
MQ
+13
to
-VS
+13.5
to
-Vs
V
Common Mode Rejection Ratio
RS:$ 10 kQ
70
90
dB
Large Signal Open Loop
Voltage Gain
VOUT = ± 10 V, RL = 2 kQ
20
200
V/mV
Power Bandwidth
Ay = 1, RL = 2 kQ, VOUT = 20 V pk-pk
9.0
kHz
Small Signal Bandwidth
Ay = 1, RL = 10 kQ, VOUT = 50 mV
1.0
MHz
Slew Rate
Ay= 1,VIN=-10Vto+l0V
0.6
V/~s
Rise Time
Ay = 1, RL = 10 kQ, VOUT = 50 mV
0.3
~s
Fall Time
Ay = 1, RL = 10 kQ, VOUT = 50 mV
0.3
~s
Overshoot
Ay= 1,RL= 10kQ,VOUT=50mV
20
%
Phase Margin
Ay = 1, RL = 2 kQ, CL = 200 pF
60
Degree
Crossover Distortion
VIN = 30 mV pk-pk, VOUT = 2 V pk-pk
f = 10 kHz
0.1
%
Output Voltage Range
RL = 10 kQ
RL = 2 kQ
± 13
± 12
±14
± 13.5
V
V
Individual Output Short Circuit Current (Notes 3,4)
±10
±30
mA
Q
Output Impedance
f = 20 Hz
800
Power Supply Rejection Ratio
Positive
Negative
30
30
150
150
~V!V
~V!V
Power Supply Current
VOUT = 0, RL =
2.0
4.0
mA
Channel Separation
f = 1 kHz to 20 kHz (Input Referenced)
00
-120
dB
The following specifications apply for O°C :$ TA:$ 70°C
7.5
Input Offset Voltage
Average Temperature Coefficient of
Input Offset Voltage
~V/oC
10
Input Offset Current
200
Average Temperature Coefficient of
Input Offset Current
nA
pA/oC
50
-400
Input Bias Current
mV
nA
Large Signal Open Loop
Voltage Gain
RL = 2 kQ, VOUT = ± 10 V
15
V/mV
Output Voltage Range
RL = 2 kQ
±10
V
Notes
3. Not to exceed maximum package power dissipation.
4. Indefinite on shorts to ground or V- supply. Shorts to V+
supply may result In power dissipation exceeding the absolute
maximum rating.
4-117
•
f.LA798
Vs = ±5.0 V and Ground, TA = 25°C unless otherwise noted.
Electrical Characteristics
Typ
Max
Unit
Input Offset Voltage
2.0
7.5
mV
Input Offset Current
10
50
nA
Input Bias Current
-80
-250
nA
Characteristic
Condition
Large Signal Open Loop
Voltage Gain
Min
RL
= 2 kQ
20
RL
= 10 kQ
= 10 kQ, 5.0 V :::; Vs :::;
4.0
(V+)
-1.5
V/rnV
200
150
Power Supply Rejection Ratio
Output Voltage Range (Note 5)
RL
Output Sink Current
= 1.0 V,
VIN
VOUT
30 V
= 200 rnV
J.LV/V
V pk-pk
V pk-pk
0.35
Power Supply Current
rnA
2.0
4.0
rnA
Note
5. Output will swing to ground.
Typical Performance Curves
Sinewave Response
Av
'\
~
/\
"
=
f
w
CJ
I.
\,
~
g
.ir
!5
.--...
--..;
'"' '"'
T,le I,J.~
'5
VS
;- 20
~
~
30
100
.1
J V
Large Signal Open Loop
Voltage Gain as a
Function of Frequency
Output Voltage as a
Function of Frequency
15
10
50
-5 0
10k
50 j.ts/DIV
"
"-
-
100 k
10k
FREQUENCY -
Output Swing as a
Function of
Supply Voltage
Vs
TA
"t15 V
100
RL -" 10 k!l
o
.--...
=c
10M
T,I =
,J.e
100
0
75
0
50
10
10
100
10k
J,
= 1±15
10 k
100 k
10M
Hz
Input Bias Current as a
Function of
Supply Voltage
Input Bias Current as a
Function of Temperature
0
-20 UJ.ll.J-LllLl,J..l.lL.1..llILL,-LllLL.illLJ
FREQUENCY -
Hz
'15 V
25°C
f+1+Io.t-+l4HI+l-fHI+l++-+-ttfH-+t1+---1
~_
50ttti:1:ttti:jj
0
/
V
F-
V
I"-
.0 1-+--+--l--l--+~I-l--+--I---1
'5
/
o '
o 2.0
40 60
80 10
12
14
"
18
V+ AND V- POWER SUPPLY VOLTAGES -
20
V
0
-75 -55 -35 -15 5.0
25
45
TEMPERATURE -
4-118
65
Q
C
85 105 125
30 0L-,:1:.0,.-1''''0"",.LO-o,:L.0-+
1O-""1L, -,:L.-,L16,---J'.~20
V+ AND V- POWER SUPPLY VOLTAGES -
V
IlA798
Wein Bridge Oscillator
Typical Applications
50 k
Multiple Feedback Bandpass Filter
r----~~~---~-VOUT
10 k
1
+
1'0
VREF
VREF
=-
2
-=- R
V+
c
"F
R
j.
fa = center frequency
j.
BW = Bandwidth
Rink!!
C
In
fa
=
211'RC
"F
fa
0= BW
<
10
High Impedance Differential Amplifier
o
Cl
= C2 ="3
Rl
R3
= R2 = 1
= 90 2
- 1
R6
}
VI
Use scaling factors in these expressions.
R2
>---VOUT
If source Impedance IS high or varies, filter may be preceded
with voltage follower buffer to stabilize filter parameters
Rl
Design example:
given: 0
5, fa
1 kHz
Let Rl = R2 = 10 k!!
then R3 = 9(5)2 - 10
R3 = 215 k!!
5
C
'3 1.6 nF
=
=
=
R3
R4
=
R5
Comparator With Hysteresis
V2
R2
R7
Rl
VREF
V,N
-.1\11"""---1
-------1
V_ou-l,o"li·l
>_.....
VOL
V,NL
I
Your
R2
R5
V,NH
VREF
Rl
VINH = Rl + R2 (VOH - VREF) + VREF
Gain
Rl
H = Rl + R2 (VOH VOL)
=
Rl + R2
4CRfR 1 if R3 =
= C (1 + a +b)(V2 -VI)
R6
== R7 for best CMRR
Rl = R4
R2 = R5
Rl
VINL = Rl + R2 (VOL - VREF) + VREF
f
•
=
for fa
1 kHz
R = 16 k!!
C = 0.01 "F
R2Rl
Fi2+"R1
4·119
=
R6
2Rl
R2 (1 + AS)
= C (1
+ a + b)
..-_ _..AyI\A___- ___-SQUARE
OUTPUT
Rt
L---4--VREF
4-120
WAVE
,uA 101 • ,uA201
General Purpose
Operational Amplifiers
I=AIRCHILO
A Schlumberger Company
Linear Products
Connection Diagram
a-Pin Metal Package
Description
The J.l.A 1Oland J.l.A20 1 are General Purpose Monolithic
Operational Amplifiers constructed using the
Fairchild Planar epitaxial process. They are intended
for a wide range of analog applications where tailoring
of frequency characteristics is desirable. The J.l.A 101
and J.l.A20 1 compensate easily with a single external
component. High common mode voltage range and
absence of "latch-up" make the J.l.A 101 and J.l.A201
ideal for use as voltage followers. The high gain and
wide range of operating voltages provide superior
performance in integrator, summing amplifier, and
general feedback applications. The J.l.A 101 and J.l.A201
are short-circuit protected and have the same
pin configuration as the popular J.l.A741 , J.l.A748
and J.l.A709.
>---'-C~ OUT
-IN
v(Top View)
Pm 4 connected to case
•
•
•
•
•
SHORT-CIRCUIT PROTECTION
OFFSET VOLTAGE NULL CAPABILITY
LARGE COMMON-MODE AND DIFFERENTIAL
VOLTAGE RANGES
LOW POWER CONSUMPTION
NO LATCH-UP
Order Information
Type
Package
J.l.A101
Metal
J.l.A201
Metal
Code
5W
5W
Part No.
J.l.A 101HM
J.l.A201HC
Equivalent Circuit
COMP NULL
COMP
r-----------~------~--_1------------+_~------------_.-----------V+
INVERTING INPUT NON-INVERTING INPUT +
--r-----------+------c
--i----------C"
'-----t---......-----
OUTPUT
R8
1 kn
'-----~~~---4--~__--I---------------~----------------+---~------~----------vR4
250 fl
OFFSET NULL
4·121
•
f.lA 10 1 • f.lA20 1
Absolute Maximum Ratings
Supply Voltage
Internal Power Dissipation
(Note 1)
Metal Package
Differential Input Voltage
Input Voltage (Note 2)
Storage Temperature Range
Metal Package
/LA101
Electrical Characteristics
/LA201
Electrical Characteristics
Characteristic
Input Offset Voltage
±22 V
Operating Temperature Range
(Note 3)
Military (/LA 101)
-55°C to +125°C
Commercial (/LA20 1)
O°C to +70°C
Pin Temperature (Soldering, 60 s) 300°C
500 mW
±30 V
± 15 V
±5.0 V
:0;
VS:O; ±20 V, TA = 25°C, unless otherwise specified.
+50
V -< Vs -< +
- 15 V, TA = 25°C
/LA101
Typ
Condition
Min
1.0
Max
5.0
Input Offset Current
40
Input Bias Current
120
Rs:O; 10 kf!
Input Resistance
Supply Current
300
Vs = ±20 V
2.0
Max
7.5
200
100
500
nA
500
0.25
1.5
/LA
kf!
800
1.8
/LA201
Typ
Min
100
1.8
Vs = ± 15 V
Large Signal Voltage Gain
Vs = ± 15 V
VOUT = ± 10 V, RL 2: 2 kU
The following specifications apply over -55°C
400
3.0
:0;
50
160
20
3.0
150
Unit
mV
mA
V/mV
TJ:O; 125°C for /LA10l, O°C:O; TJ:O; 70°C for /LA201.
Input Offset Voltage
RS:O; 10 kf!
Average Temperature
Coefficient of Input
RS
:0;
50 f!
3.0
6.0
/LV 1°C
Offset Voltage
RS
:0;
10 kf!
6.0
10.0
/LV 1°C
6.0
10
mV
TA =
10
200
50
400
nA
TA =
100
500
150
750
nA
Average Temperature
Coefficient of Input
Offset Current
+25 :0; TA :0; max
min :0; TA:O; +25°C
0.Q1
0.02
0.1
0.2
0.01
0.02
0.3
0.6
nA/oC
nA/oC
Input Bias Current
TA = -55°C
0.28
1.5
0.32
2.0
Supply Current
TA = +125°C, Vs = ±20 V
1.2
2.5
/LA
mA
Large Signal Voltage Gain
Vs = ± 15 V, VOUT = ± 10 V
RL 2: 2 kf!
Output Voltage Swing
Vs = ± 15 V
Input Voltage Range
Vs = ± 15 V
± 12
Common Mode
Rejection Ratio
RS
:0;
10 kf!
70
90
65
90
dB
Supply Voltage
Rejection Ratio
Rs
:0;
10 kf!
70
90
70
90
dB
Input Offset Current
IRL =
IRL =
15
25
V/mV
10 kf!
±12
±14
±12
±14
V
2 kf!
±10
±13
±10
± 13
V
Notes
1 Rating applies to ambient temperature up to 70°C. Above
70°C ambient derate linearly at 6.3 mW / °C for the Metal Can.
2. For supply voltages less than ± 15 V, the absolute maximum
input voltage is equal to the supply voltage.
±12
V
3. Short circuit may be to ground or either supply. The 101 ratings
apply to +125°C case temperature or +75°C ambient
temperature. The 201 ratings apply to case temperatures
up to +70°C.
4-122
p,A 101A • p,A201A •
p,A301A General-Purpose
Operational Amplifiers
FAIRCHILO
A Sehlumberger
Company
Linear Products
Connection Diagram
S-Pin Metal Package
Description
The /LA 10 1A, /LA20 1A and /LA30 1A are GeneralPurpose Monolithic Operational Amplifiers
constructed using the Fairchild Planar epitaxial
process. These integrated cirucuits are intended for
applications requiring low input offset voltage or low
input offset current. The accuracy of long interval
integrators, timers and sample and !lold circuits is
improved due to the low drift and low bias currents of
the /LA 101A, /LA201A, or /LA301A. Frequency response
may be matched to the individual circuit need with one
external capacitor. The absence of "latch-up" coupled
with internal short-circuit protection make the /LA 10 1A,
/LA201A and /LA301A virtually foolproof.
-IN
>-----=1D OUT
V(Top View)
•
•
•
•
•
LOW OFFSET CURRENT AND VOLTAGE
LOW OFFSET CURRENT DRIFT
LOW BIAS CURRENT
SHORT CIRCUIT PROTECTED
LOW POWER CONSUMPTION
Absolute Maximum Ratings
Supply Voltage
Military and Instrument
(/LA 10 1A and /LA20 1A)
Commercial (/LA30 1A)
Internal Power Dissipation
(Note 1)
Metal Package
DIP
Differential Input Voltage
Input Voltage (Note 2)
Storage Temperature Range
Metal Package
DIP
Operating Temperature Range
Military (/LA 10 1A)
Instrument (/LA20 1A)
Commercial (/LA30 1A)
Pin Temperature (Soldering)
Metal Package (60 s)
DIP (10 s)
Output Short Circuit Duration
(Note 3)
PIO 4 connected to case
Order Information
Type
Package
/LA101A
Metal
/LA201A
Metal
/LA30 1A
Metal
Part No.
/LA101AHM
/LA201AHM
/LA301HC
Connection Diagram
S-Pin DIP
±22 V
± 18
Code
SW
SW
SW
V
sao
mW
310 mW
±30 V
± 1S V
OFFSET NULL
(COMP)
FREQ
COMP
-IN
OUT
+IN
-64°C to +1S0°C
-SsoC to +12SoC
OFFSET
NULL
v-
-SsoC to +12SoC
-2SoC to +E1SoC
O°C to +70°C
(Top View)
300°C
260°C
Order Information
Type
Package
/LA301A
Molded DIP
Indefinite
Noles
1. RatlOg applies to ambient temperature up to 70 o e. Above
70 0 e ambient derate linearly at 6.3 mW / °e for the metal
package, 5.6 mW / °e for the DIP.
2. For supply voltage less than ± 15 V. the absolute maxImum
input voltage is equal to the supply voltage.
3. Short circuit may be to ground or either supply. lOlA and 201A
ratings apply to +125°e case temperature or +75°e ambient
temperature. 301A ratings apply for case temperatures to 70 o e.
4-123
Code
9T
Part No.
/LA30 1ATC
•
p,A 101A • p,A201A • p,A301A
Equivalent Circuit
COMPo
NUll
COMPo
~----------~-------+--+----4--------~---------------+------V+
I N VERTING IN PUT ~
NON·INVERTING INPUT
---+-----------+-------£
+----+--------["
R11
25 (]
'---+--+-OUTPUT
Q11
RS
RS
R7
40 krl
40 krl
80 kO
R8
1 kO
L---~--~
__
~~
__
~~~
______________4-__________________
OFFSET NUll
4·124
~
____4-__
~
_____ V_
JLA 101A • JLA201A • JLA301A
Electrical Characteristics
TA = +25 ° C unless otherwise noted. Unless otherwise specified, these
specifications apply for supply voltages from ± 5.0 V to ± 20 V for the /LA 10 1A and
/LA20 1A, and from ± 5.0 V to ± 15 V for the 301 A.
/LA101A,/LA201A
Symbol
Characteristic
Condition
Rs ::S 10 kfl
Min
Typ
Max
/LA301A
Min
Typ
Max
Unit
VIO
Input Offset Voltage
0.7
2.0
2.0
7.5
mV
110
Input Offset Current
1.5
10
3.0
50
nA
118
Input Bias Current
30
75
70
250
nA
rj
Input Resistance
1.5
4.0
1.8
Icc, lEE
Supply Current
VeeIVEE= ±20V
Vee/VEE = ± 15 V
Av
Large Signal
Voltage Gain
VeelVEE ± 15 V, Vo =
± 10 V, RL > 2.0 kfl
0.5
2.0
1.8
50
Mfl
3.0
160
25
3.0
160
rnA
V/mV
The following specifications apply over the operating temperature range.
VIO
Input Offset Voltage
110
Input Offset Current
RS::S 10 kfl
3.0
10
mV
20
70
nA
Average Temperature
.:lVlo/.:lT Coefficient of
Input Offset Voltage
TA (min) ::S T A ::S TA(max)
3.0
15
6.0
30
/LV/oC
.:lIIO/.:lT
Average Temperature
Coefficient of
Input Offset Current
+25°C ::S TA::S TA (max)
TA (min) ::S TA ::S 25°C
0.01
0.02
0.1
0.2
0.01
0.02
0.3
0.6
nA/oC
18
Input Bias Current
300
nA
Av
Large Signal
Voltage Gain
VeelVEE = ± 15 V, Vo =
± 10 V, RL 2: 2.0 kfl
VI
Input Voltage Range
VeelVEE = ±20 V
VeelVEE = ± 15 V
±15
CMRR
Common-Mode
Rejection Ratio
RS ::S 10 kfl
80
96
70
90
dB
PSSR
Supply Voltage
Rejection Ratio
Rs ::S 10 kfl
80
96
70
96
dB
Vo
Output Voltage Swing
VeelVEE = ± 15 V, RL = 10 kfl ± 12
RL = 2.0 kfl
± 10
±14
±13
± 12
±10
±14
±13
V
IcC, lEE
Supply Currents
TA = TA (max)
Vee/VEE = ±20 V
1.2
100
25
15
V/mV
V
±12
4·125
2.5
rnA
•
JJ,A 101A· JJ,A201A· JJ,A301A
Typical Performance Curves for
Input Voltage Range as a
Function of
Supply Voltage
~A101A
~A201A
and
Output Swing as a
Function of
Supply Voltage
20
Voltage Gain as a
Function of
Supply Voltage
0
100
- 55'"C:s; 'TA S 125'"C
>
./
+116
...
./
"..z 12
'"w
g
...
"
J!:
8
..
/'~"'~
./
0-
"z~
:$:I;~
\~
~
v
z 88
"I
f'\.
1M
10 M
.,m
Vs
"-
...:J:
90~
~
TA "'" 25°C
r-~S = ±15V
C1 = 30pF
C2=300pF
10M
180
TA "" 25°C
f-- ......
100
225
I
1
15
SUPPLYVOLTAGE- ±V
100
225
Gi'N<:=: I---
f..- f-
TWO POLE
~~
20
\~
-I-'"
70
120
",-y
~i'"
,
0
.. ..
15
TA'" 25°C
Vs=+15V
~~~ PHASE /
I
82
7.
Open Loop
Frequency Response
,,~~
!g80
"
"~
~
10
Open Loop
Frequency Response
120
88
w
SUPPLVVOLTAGE- ±V
Typical Performance Curves for
>
.. .
~
15
/
I
w
"w
20
Voltage Gain as a
Function of Supply Voltage
20
D"C:s; TA s looe
~
15
~A301A
Output Swing as a
Function of Supply Voltage
Input Voltage Range as a
Function of Supply Voltage
J!:
10
SUPPLYVOLTAGE- '!:;V
SUPPLY VOLTAGE- ±V
~V
SUPPL,YVOLTAGE-
",,,,,,, V
7'
78
0
5
V
~
.,.?-'
/'
f--
"~ 82
",'I<
~~\~:$'
o
V
~"
TA :s 125°C
'""I
..~
10
:s;
9'
) / /'
"
/"
~ :~~
&2:./
qO~
f--
~
15
>
/
~'" V
- 55°C
-55°CsTAS 125°C
±15V
...
rv
»
GA'~)..
0
0
0
"-
FEE'l FORiARD
-20
100
1k
2 25
180 :J:
",Hi,E
0
10
=
10k
lOOk
1M
FREQUENCY - Hz
J
~
1 35~
"I
90 ~
~
45
10M 100M
.,Hl
J,LA 101A • J,LA201A· J,LA301A
Typical Performance Curves for /-LA101A, /-LA201A and /-LA301A (Cont.)
,.
,.
LI2~'U
> 12
..
.
'\
> 12
+
"iz
8
\
0-
=>
~
[\
C, = 30pF\
o
.
~
SINGLE POLE
> 12
\
"
\
8
vu+Ut
TA :::; 25"C
\
\
+
\C1 = 3pF
16
Vs = ±15V
TA = 25"C
Cl = 30pF
C2 = 300pF
VS"" ± 15V
"iz
Large Signal
Frequency Response
Large Signal
Frequency Response
Large Signal
Frequency Response
"zi
.
.
8
0-
=>
\
o
0-
FEED FORWARD
o=>
TWO POLE
I'..
0
...... t-
i't--
100k
1M
10k
1k
t-
0
10M
1M
100k
10k
FREQUENCY - Hz
o
Voltage Follower
Pulse Response
Hz
•
Inverter Pulse Response
10
10
10
10M
FREQUENCY -
FREQUENCY - Hz
Voltage Follower
Pulse Response
""- r-
1M
100 k
,
OUTPUT
I--
1\
I
I
I
-
>
I
"z
~
~
OUTPUT
0
I
g -4
r-
-6
l\
-6
SINGLE POLE
IIINPUT
I
OUTPUT
~
TWO POLE
INPUT
I
FEEDFORWARD
-8
-8
-10
-10
~
~
~
TIME -
~
00
ro
o
~
10
~
30
~
~
TIME -
jJS
~
ro
-----r
TA:::;
20
T,
z
C
~
.
" 100
!--
p----
b?'
~ I-- r--
-
~
~
\ 1'\ "'\
...
~
80
10
15
SUPPLY VOLTAGE -
20
± V
5
1\
15
10
SUPPLY VOLTAGE -
4-127
20
±Y
o
o
10
15
OUTPUT CURRENT -
... >...
"Cl ;n n
>
&n
125°C
90
5
~
Vs= ±15V
>
TA
ro
~
"s
25°C
05
o
~
~ r--....
55°C
~,
g
30
Current Limiting
15
~ 110
~
TIME -
IS5 0 C
~ f---"" r:;:: 2S"C
10
",S
120
25
TA = 25"C
~S=t'5t-
a
~
Voltage Gain as a
Function of
Supply Voltage
Supply Voltage Current as
Function of
Supply Voltage
-
-6
-8
10
I
g -4
-10
o
I
0
"~-2
TA = 2S"C
Vs= ±15V
Cl =30pF
C2=300pF
- ..,
- - - il' -
"z
I----
I \
"
-
>
!\
.. -2
~
I
\
I
-
/
I
\
I
r-
r
INPUT
20
mA
25
30
p,A 101A • p,A201A • p,A301A
Typical Performance Curves for
~A101, ~A201
50
100
0
80
1As- r-
0
20
!i
10
Input Noise Voltage
vs Frequency
5
601-- 1--8 ,"'-
r--
(Cont.)
Input Current
vs Temperature
(~A301A only)
Input Current
vs Temperature
(~A 101A and ~A201A only)
~
~A301
and
I--
""- I-
.......
I
I'
0
.,
0
t-..
0
TA~25'C
~
i"'-
8
4
3
I'--
2
OFFSET
-r--
1
0
~
~
~
-
~
0
6
41:::::::- f-OFFSET
2
~
1<10
20
~
60
40
80
100
TEMPERATURE _ °C
4
"-
10-26
10
120
10-26
10.
100
10
100'
"-
'"
'" "- rz~
~-:-
I"
ot-~~;~~
10
100
1k
10k
FREQUENCY -
lOOk
Hz.
V
,
Av=1
V
,
2
"1M
Av = 1000
1'-""
f--f---
" ~"-... '\ I\..
r- ~~~:~!fION
100'
Hz
80
~
80
10M
40
RsJkU
TA '= 25°C
'" '"
~±10V
VCM~:rV~
i/
I"'-"
10-3
10
1<10
V
V
SINGLE POLE
COMPENSAnoN
C,=30pF
-
TA"'25°C
5mA l
' OU
r+
1k
10k
FREQUENCY -
4·128
lOOk
Hz
W
1<10
1k
10k
FREQUENCY - Hz
Closed Loop Output Impedance
vs Frequency
I~~
f----'
10.
1k
FREQUENCY -
Power Supply Rejection
vs Frequency
- I--.
~W
-
20
FREQUENCY - Hz
100
100
t
......
1.
100
~
~
5
I'
100'
Common Mode Rejection
vs Frequency
4
1\
10'
FREQUENCY - Hz
Input Noise Current
vs Frequency
(~A301A only)
Input Noise Current
vs Frequency
(~A 101A and ~A201A only)
5
,.
6
~
TEMPERATURE - °C
1M
lOOk
1M
p,A 101A • p,A201A • p,A301A
Compensation Circuits
(All pin numbers shown refer to B-Pin metal package)
Typical Applications
(All pin numbers shown refer to B-Pin metal package)
Single Pole Compensation
Fast Voltage Follower
R2
R1
-VIN
VOUT
VOUT
VIN
R3
+VIN
R1 C 8
Power Bandwidth: 15 kHz
Slew Rate: 1 V / 1'8
C1~ R1+ R2
C s = 30 pF
Inverting Amplifier With Balancing Circuit
Two Pole Compensation
Rl
R2
INPUT--~~~----~~r------'
R2
R1
6
>-----OUTPUT
R4
5.1 MD
>~"",,-VOUT
~
SMD
.J:.
C1
30 pF
Nole
May be zero or equal to parallel combination of R 1 and R2 for
minimum offset.
R 1Cs
Cl~ R 1 +R2
Voltage Comparator for Driving or
DTL Integrated Circuits
C s = 30 pF
C2 = 10 Cl
Feedforward Compensation
OUTPUT
C2
R2
R1
VIN
----JVlIv-_.....--I
6
>---VOUT
R3
C,
150 pF
4·129
•
f,LA 101A • f,LA201A • f,LA301A
Typical Applications (Cont.)
(All pin numbers shown refer to B-Pin metal package)
Low Frequency Square Wave Generator
Practical Differentiator
R1
1M
C2
R2
LOW
, - - - - - i -__ 'IMPEDANCE
'C1
+ 15V
-15V
OUTPUT
R1
>----'1."1\.....----+... CLAMPED
VI N
OUTPUT
R3
C1
--'vVv---i t--+---1
6
>'--.....
-VOUT
D1,6.2V
D2,6.2V
• Adjust C 1 lor frequency
Circuit for Operating Without a Negative Supply
R1
R2
1= __1_
c
+20V
1
.J
1
fh = 211" R 1C 1
1
6
=
I
VIN
fc
VOUT
R3
"::"
C1
30pF
211"R 2 C 1
t
4·130
<
211"R2C 2
fh
<
lunity gain
~A107·~A207·~A307
FAIRCHIL.O
General Purpose
Operational Amplifiers
A Schlumberger Company
Linear Products
Description
The j.lA 107 General Purpose Operational Amplifier
series is constructed using the Fairchild Planar
epitaxial process. Advanced processing techniques
have reduced the 107 input current an order of
magnitude below industry standards such as the
j.lA709 while still replacing, pin-for-pin, j.lA709, j.lA 10 1,
j.lA 10 1A, and j.lA 7 41. The j.lA 107, !1A207, and j.lA307
offer better accuracy, internal compensation, and
lower noise for high impedance circuit applications
while providing features similar to the j.lA 10 1A. The
low input currents allow the device to be used in slowcharge applications such as long period integrators,
slow ramps, and sample-and-hold circuits. The j.lA207
is identical to the j.lA 107 except that the j.lA207
performance is guaranteed from -25°C to +85°C
while the j.lA 107 performance is guaranteed over a
-55 ° C to + 125 ° C temperature range. The j.lA307 is
guaranteed over a O°C to + 70°C temperature range.
•
•
•
•
•
Connection Diagram
a-Pin Metal Package
NC
•
v(Top View)
Pin 4 connected to case
Order Information
Type
Package
j.lA107
Metal
j.lA207
Metal
j.lA307
Metal
LOW OFFSET VOLTAGE
LOW INPUT CURRENT
LOW OFFSET CURRENT
GUARANTEED DRIFT CHARACTERISTICS
GUARANTEED OFFSETS OVER COMMON MODE
RANGE
Absolute Maximum Ratings
Supply Voltage
Military and Instrument (j.lA 107
and j.lA207)
Commercial (j.lA307)
Internal Power Dissipation
(Note 1)
Metal Package
Molded DIP
Differential Input Voltage
Input Voltage (Note 2)
Storage Temperature Range
Metal Package
Molded DIP
Operating Temperature Range
Military (j.lA 107)
Instrument (j.lA207)
Commercial (j.lA307)
Pin Temperature (Soldering)
Metal Package (60 s)
Molded DIP (10 s)
Output Short Circuit Duration
(Note 3)
>--.....:.c:J OUT
-IN
Part No_
j.lA107HM
j.lA207HM
j.lA307HC
Code
5W
5W
5W
a-Pin Molded DIP
±22 V
± 18 V
500 mW
310mW
±30 V
± 15 V
NC
NC
-~
v+
rlN
OUT
V
NC
(Top View)
-65°C to +150°C
-55°C to +125°C
Order Information
Type
Package
j.lA307
Molded DIP
-55°C to +125°C
-25°C to +85°C
O°C to +70°C
300°C
260°C
Indefinite
Notes on following page
4-131
Code
9T
Part No.
j.lA307TC
~A107·~A207·~A307
Equivalent Circuit
7
r-~--------------9---------~-----------------1~-----------1~--V+
R7
4.5 kll
INVERTING
INPUT
6 OUTPUT
R10
30kll
R1
R3
1 kll
50kll
R12
50 kll
R2
1 kll
R11
50 n
4
~----~----~----~------~~--~----~--~----------~--~
Noles
1 Rallng applies to ambient temperalures up to 70°C Above
70 ° C ambient derate linearly at 6 3 mW 1 0 C for metal package
and 5 6 mW 1°C lor Ihe molded DIP
2 For supply voltages less than ± 15 V. Ihe absolute maximum
Input vollage IS equal to the supply voltage
3 Continuous short CirCUit IS allowed with IlA307 for case
temperatures to 70°C and ambient temperatures to 55°C
4-132
~A107·~A207·~A307
!lAl07 1!lA207
Electrical Characteristics
±5.0 V
-s
Vs::O:: ±20 V, TA = 25°C unless otherwise specified.
Characteristics
Conditions
Input Offset Voltage
Rs::o:: 50 kll
Min
Typ
Max
Units
0.7
2.0
mV
Input Offset Current
1.5
10
nA
Input Bias Current
30
75
nA
1.5
Input Resistance
Supply Current
Vs = ±20 V
Large Signal Voltage Gain
Vs=±15V
VOUT = ± 10 V, RL 2: 2 kll
4.0
Mil
3.0
1.8
160
50
V/mV
The following applies for 55 ° C -<: T A -<: 125 ° C unless otherwise specified
Input Offset Voltage
RS::O:: 50 kll
Average Temperature
Coefficient of Input
Offset Voltage
3.0
Input Offset Current
Average Temperature
Coefficient of Input
Offset Current
mA
3.0
mV
15
!lV/oC
20
nA
25°C ::0:: TA::O:: 125°C
0.01
0.1
nA/oC
-55°C ::0:: TA::O:: 25°C
0.02
0.2
nA/oC
100
nA
2.5
mA
Input Bias Current
Supply Current
TA = +125°C, Vs = ±20 V
Large Signal Voltage Gain
Vs = ± 15 V, VOUT = ± 10 V
RL 2: 2 kll
Output Voltage Swing
Vs = ± 15 V
Input Voltage Range
Vs = ±20 V
±15
Common Mode
Rejection Ratio
RS::O:: 50 kn
80
96
dB
Supply Voltage
Rejection Ratio
RS::O:: 50 kll
80
96
dB
lRL =
1.2
25
10 kll
IRL = 2 kll
V/mV
± 12
±14
V
±10
±13
V
V
Guaranteed Performance Curves for !lA 107 and !lA207
Input Voltage Range
vs Supply Voltage
Output Swing vs
Supply Voltage
Voltage Gain vs
Supply Voltage
..
,
20
20
'6
L
<,'"
12
1/
V
,~'f.V
,/"
~/
"",<>&'
f - - _flO
~«,.
V
'0
,/
~
V
1
'0
~1-1
15
SUPPLY VOLTAGE--tV
20
~
"'," "I
~\¥o.
~V
'/
94
I
••
~
z
;;
-:'l.'f.~ -
" .2 f--- r--"'\""
/
"~ V
~,
...-
w
-55QC::oITA","~125QC_
207 -25 C:_/A:::S5i C
0
0,
.
~
107
~~i =;~:g:,_~~:_- !!:~c ~
o
5
/'
15
/'
1
'0
15
SUPPLY VOLTAGE - ±V
4-133
20
76
1 - - - + _ + - 1 0 7 -55°CS TA-:O 125°C_
20\ 2S° C r,,·5;C
70 5~---1--..",:-o--"---'':-5-...L---,I"
SUPPLY VOLTAGE -:rV
•
~A107·~A207·~A307
/l-A307
Electrical Characteristics
s:
±5.0 V
Vs
s:
± 15 V, TA = 25°C unless otherwise specified.
Typ
Max
Units
2.0
7.5
mV
Input Offset Current
3.0
50
nA
Input Bias Current
70
250
nA
Characteristics
Conditions
Input Offset Voltage
Rs
s:
Min
50 kQ
0.5
Input Resistance
MQ
2.0
1.8
Supply Current
Vs = ± 15 V
Large Signal Voltage Gain
VS= ±15V
VOUT = ± 10 V, RL 2: 2 kQ
3.0
160
25
V/mV
The following specifications apply for O°C -<: TA -<: 70°C
Input Offset Voltage
Rs s: 50 kQ
Average Temperature
Coefficient of Input
Offset Voltage
10
mV
30
/l-V 1°C
70
nA
0.01
0.3
nA/oC
0.02
0.6
nA/oC
300
nA
6.0
Input Offset Current
Average Temperature
Coefficient of Input
Offset Current
25°C
O°C
s:
s:
TA
TA
s:
s:
mA
70°C
25°C
Input Bias Current
Large Signal Voltage Gain
Vs = ± 15 V, VOUT = ± 10 V
RL 2: 2 kQ
Output Voltage Swing
Vs = ± 15 V
Input Voltage Range
Vs = ± 15 V
Common Mode
Rejection Ratio
RS
s:
50 kQ
70
90
dB
Supply Voltage
Rejection Ratio
Rs
s:
50 kQ
70
96
dB
IRL =
IRL =
15
V/mV
10 kQ
±12
±14
V
2 kQ
±10
±13
V
±12
V
Guaranteed Performance Curves for /l-A307
Input Voltage Range
vs Supply Voltage
Voltage Gain vs
Supply Voltage
Output Swing vs
Supply Voltage
2.
I ••
20
16
,.......
94
15
,.......
12
~o~*
17'
~
.",.""
•
5
V
.1~~~
.",.'"
. / f-"'"
~V V
",\~'f'\.-"'""
~
I. r 1" 1'·'1c
15
SUPPLY VOLTAGE --j:.V
,....... f-"'"
I.
~
•
5
:;...
82
".- ~\
rr
SUPPLY VOLTAGE -
4-134
I--
76
I.
15
~
v
-
88
,.
5
-
..
\~
l-
rCI T, 1'·'1I.
SUPPLY VOLTAGE -
15
tV
~A107·~A207·~A307
Typical Performance Curves for f.lA 107 and f.lA207
Voltage Gain vs
Supply Voltage
Input Current vs
Supply Voltage
40
~
110
"1\_ ~5S°c..
I
z
~
"w
"~
100
V
.... ?
~
g
90
-
~
TA-2.r C
-
:- ........
30
':!
20
ffi
10
I
•
r---.
......
~
~
..........
-
V,.:+15V
~
'\
~
I 100
I
TA=125°C
TA.25O~
...::>
o
I!:::>
50
0
~
o
20
r- """'=::: ::::---
~
~
15
.
::>
TA-125°C
10
./~
150
"~
1
80
Current Limiting
50
120
75
50
25
25
50
75
100
125
10
AMBIENT TEMPERATURE_o C
SUPPLY VOLTAGE _ ±V
15
25
20
30
OUTPUT CURRENT - +mA
•
Typical Performance Curves for f.lA307
Voltage Gain vs
Supply Voltage
Input Noise Current
vs Frequency
Input Current vs
Ambient Temperature
100
120
-
80
SIAS
~
I
80
110
-
z
"w
"~
I
SoC
I-'~~
~
\
':! •0
100
0
~
o
~
>
,
10
100
1k
10 k
80
lOOk
•
15
10
SUPPLY VOLTAGE -
OFFSET
2
I
•
FREQUENCY - Hz
TEMPERATURE _
150
~ T.J25 C
i
0
I
w
"I
I"
g
w
'"
i5
~
I!:
::>
0
~
::>
g
z
~
~
10
1\
...::>~
t'-r-.
w
10.0
"z
......
z
10- 2
TAJO~ ~
>
"~
,
5.0
-v5'
"'V
1
,
10- 1
100
1k
FREQUENCY - Hz
10k
100'
80
c
Input Noise Voltage
vs Frequency
10- 1 5
5
0
Typical Performance Curves for
f.lA107, f.lA207,.f.lA307 (Cont)
Input Noise Current
vs Frequency
1"\
60
40
20
±V
Typical Performance Curves for f.lA307 (Cont.)
Current Limiting
•
~
90
10-2
20
~
::>
10
100
1k
FREQUENCY - Hz
4-135
10k
100 •
10
15
2'
20
OUTPUT CURRENT -
± mA
30
~A107·~A207·~A307
Typical Performance Curves for
~A 107, ~A207 and ~A307 (Cont.)
Large Signal
Frequency Response
Open Loop
Frequency Response
16
120
TA=25°C
TA=25°C
........
lDO
'll
I
80
"'"
.0
z
"'- ~
40
'Ii
i"
I"
10
100
~
lK
'"
8
I
-
4
\
, ....•.. _ -
1\
~
INPUT
\
~
/
OUTPUT
"'~
\
V
-2r-~+*+\-+-+-+~1H-~-b~
g
-.1--+."::...::(.."::...::j.Yl=+=:J=++--+-l
-4~+-1-~-b-+-+~~~~
1'1'-
\
10K lOOK 1M
FREQUENCY - Hz
6~+-1-~-b-+-+~~~~
~
z
~
20
1
>
12
I
g
-20
Vs=±15V
Vs,,-:!:.15V
w
'~"
Voltage Follower
Pulse Response
10M
o
lK
10K
lOOK
TIME-",s
FREQUENCY -- Hz
Typical Applications
Non-Inverting Amplifier
Non-Inverting AC Amplifier
R2
R2
10M
6
>----4>-Your
Rl
>6~4--Vour
1M
Rl
R3
910K
"::"
V,N
R1 + R2
VOUT = --R-1- VIN
R1 + R2
VOUT = --R-1-
Inverting Amplifier
RIN = R3
R2
III
>6::..----<'-_ Your
R2
VOUT =
R1
VIN
RIN = R1
4-136
VIN
JLA10S/A· JLA20S/A·
JLA30S/A Super Beta
Operational Amplifiers
FAIRCHILO
A Schlumberger Company
Linear Products
Description
The IlA 108 Super Beta Operational Amplifier series is
constructed using the Fairchild Planar epitaxial
process. High input impedance, low noise, low-input
offsets, and temperature drift are made possible
through use of super beta processing, making the
device suitable for applications requiring high
accuracy and low-drift performance. The IlA 108A
series is specially selected for extremely low offset
voltage and drift, and high common-mode rejection,
giving superior performance in applications where
offset nulling is undesirable. Increased slew rate
without performance compromise is available through
use of feedforward compensation techniques,
maximizing performance in high-speed sample-andhold circuits and precision high-speed summing
amplifiers. The wide supply range and excellent
supply voltage rejection assure maximum flexibility in
voltage follower, summing, and general
feedback applications.
•
•
•
•
•
Connection Diagram
8-Pin Metal Package
-IN
v(Top View)
Order Information
Type
Package
Metal
IlA108A
Metal
IlA 108
Metal
IlA208A
Metal
IlA208
Metal
IlA308A
Metal
IlA308
GUARANTEED LOW INPUT
OFFSET CHARACTERISTICS
HIGH INPUT IMPEDANCE
LOW OFFSET CURRENT
LOW BIAS CURRENT
OPERATION OVER WIDE SUPPLY RANGE
Absolute Maximum Ratings
Supply Voltage
IlA 108A, IlA 108,
IlA208A,IlA208
IlA308A,IlA308
Internal Power Dissipation
(Note 1)
Metal Package
DIP
Differential Input Current (Note 2)
Input Voltage (Note 3)
Storage Temperature Range
Operating Temperature Range
Military (IlA 108A, IlA 108)
Industrial (IlA208A, IlA208)
Commercial (IlA308A, IlA308)
Pin Temperature (Soldering)
Metal (60 s)
DIP (10 s)
Output Short Circuit Duration
(Note 4)
>-----["
Notes
1. Rating applies to ambient temperatures up to 70·C ambient
derate linearly at 6.3 mW I·e for metal package, 8.3 mW I·e
for the DIP.
2. The inputs are shunted with back·to·back diodes for
overvoltage protection. Therefore, excessive current will flow if
a differential Input voltage in excess of 1 V is applied between
the inputs unless adequate limiting resistance is used.
3. For supply voltages less than ± 15 V, the absolute maximum
input voltage is equal to the supply voltage.
4. Short circUit may be to either supply or ground. Rating applies
to operation up to the maximum operating temperature range.
4·138
JLA 10S/A • JLA20S/A • JLA30S/A
J1,A 10S1 A and J1,A20SI A
Electrical Characteristics
Unless otherwise noted these specifications apply for supply voltages of
+5.0V
V, TA = +25°C.
--< Vs --< +20
-
J1,A10SA
J1,A20SA
J1,A10S
J1,A20S
Symbol
Characteristic
Typ
Max
Typ
Max
Unit
VIO
Input Offset Voltage
0.3
0.5
0.7
2.0
mV
110
Input Offset Current
0.05
0.2
0.05
0.2
nA
lIB
q
Input Bias Current
O.S
2.0
0.8
2.0
ICC, lEE
AVOL
Input Resistance
Power Supply Currents
Vee = +20 V, VEE = -20 V
Large Signal Voltage Gain
Vee = IVEEI = +15 V,
Vo =± 10 V, RL 2:: 10 kfl
Min
30
70
±0.3
80
Min
30
±0.6
300
70
±0.3
50
nA
Mfl
±0.6
300
mA
V/mV
The following specifications apply over the operating temperature range. (Note 5)
VIO
Input Offset Voltage
1.0
3.0
mV
110
Input Offset Current
0.4
0.4
nA
Average Temperature Coefficient
LlVIOIL\T of Input Offset Voltage
TA(min) ::S TA ::S TA(max)
1.0
5.0
3.0
15
J1,V/oC
Llilo I Ll T
Average Temperature Coefficient
of Input Offset Current
0.5
2.5
0.5
2.5
pA/oC
liS
Input Bias Current
0.8
3.0
3.0
nA
AVOL
Large Signal Voltage Gain
Vee = IVEEI = +15 V,
Vo = ± 10 V, RL = 10 kfl
VIR
CMRR
Input Voltage Range
Vee = IVEEI = +15 V
Common-Mode Rejection Ratio
40
25
V/mV
± 13.5
± 13.5
V
96
110
85
100
dB
96
110
80
96
dB
± 13
±14
V
PSSR
Power Supply Voltage
Rejection Ratio
VOR
Output Voltage Range
± 13
Vee = IVEEI = +15 V, RL = 10 kfl
±14
Icc, lEE
Supply Current (T A = TA[max»
±0.15
Note
5 For the
I'A 1OS / A specifications apply over -55' C ::5 TA ::5
125'C For the I'A20S/ A specifications apply over -25'C ::5
TA:::: S5'C.
4-139
±0.4
±0.15
±0.4
mA
•
j..LA 1OS/A • j..LA20S/A • j..LA30S/A
~A308/A
Electrical Characteristics
Unless otherwise noted these specifications apply for supply voltages of
+50 V --< Vee --< +15 V and -50 V>
+25°C
- -15 V TA
- VEE>
=
~A308A
~A308
Typ
Max
Typ
Max
Unit
VIO
Input Offset Voltage
0.3
0.5
2.0
7.5
mV
110
Input Offset Current
0.2
1.0
0.2
1.0
nA
118
Input Bias Current
1.5
7.0
1.5
7.0
q
Input Resistance
Symbol Characteristic
ICC. lEE
AVOL
Min
40
10
Power Supply Currents
Vee = +15 V. VEE = -15 V
Large Signal Voltage Gain
Vee = +15 V. VEE = -15 V.
Vo
± 10 V. RL 2: 10 kQ
10
±0.3
nA
40
±O.S
300
BO
=
Min
MQ
±0.3
±O.B
mA
300
25
V/mV
The following specifications apply over O°C S TA S 70°C
VIO
Input Offset Voltage
0.73
10
mV
110
Input Offset Current
1.5
1.5
nA
Average Temperature Coefficient
D.VIOI D.T of Input Offset Voltage
T A(min) s TA s TA(max)
1.0
5.0
6.0
30
~V/oC
D.IIOI D. T
Average Temperature Coefficient
of Input Offset Current
2.0
10
2.0
10
pA/oC
118
Input Bias Current
10
nA
10
Large Signal Voltage Gain
Vee = +15 V. VEE = -15 V.
Vo
± 10 V. RL 2: 10 kQ
Input Voltage Range
Vee = +15 V. VEE = -15 V
Common-Mode Rejection Ratio
RS s 50 kQ
AVOL
=
VIR
CMRR
60
15
V/mV
± 13.5
± 13.5
V
96
110
SO
100
dB
PSSR
Supply Voltage Rejection Ratio
Rs s 50 kQ
96
110
BO
96
dB
VOR
Output Voltage Range
Vee = +15 V. VEE = -15 V.
RL
10 kQ
±13
±14
±13
± 14
V
=
Typical Performance Curves for
Input Noise Voltage as 8
Function of Frequency
~A 108
Series
Power Supply Rejection 88 8
Function of Frequency
120,--,--,---,---,--...,
Vs = + 15V
1000
Open Loop
Frequency Response
120
100
r"":
C'=13PF~
r-.....
Cj _ 30pF-
400
80
Rs
1M
II I I
100
Rs
40
-
r-- h~
~,('>,
r-- ....
l-
i
10
100
1k
FREQUENCY - Hz
,- .,,,
GAIN _ _ -lOOk
1k
10k
lOOk
FREOUENCY - Hz
4-140
1M
10M
1
10
100
135
'
90
'\.
4
,
Cj = 30pF~ ~.
-20
10k
1
80
~\
PHASE _ _ _
I
,,~
"-,'\.
20
I
!i
I
Cs _100pF
'\.
40
100k
Rs - 0
10
~
10-
"
!OOO, C, 130 pF
I
TA = 25°C
lOUT = 1 mA
Vs =
1'5
Cf =
0
100
Cf=3pF
1\
lk
10k
lOOk
FREQUENCY -
1M
30~~
"
2
10k
1k
10M
1\
-
~
-
/
INPUT
\
2
-
4
,
I
T,
Vs
2'oC -=;
:t
15V
E' =lOP~ -
-1 0
1M
-
OUTPUT
V
\
B
100 k
FREQUENCY -
Hz
r- - I f
-
0
"'"~
:-
I! I
V
10 2
10
4
~
\
' A v = 1,Ct = 30pF
IJ
,
>
I
2:
Av "" lCOD,C! '" OpF
/
,
0
B
Vs= :t15V
\
12
l()O
~
o
Voltage Follower
Pulse Response
- 20 0
20
40
60
Hz
80
TIME -
100 120 140 160 180
j1S
•
Typical Performance Curves for ILA 108A, ILA 108, ILA208A and ILA208 (Unless Otherwise Specified)
Input Currents as a
Function of
Ambient Temperature
~ 100
1k
I
5
'"
.........
0
~
N08A/ IOB
~
5
g
SIAS 208AJ208
~;>
;>
5
O~ r-- ~All08
35
15
5
25
45
65
85
105
II
1.0
S
120
2~81208A ~25"C I~ TA:S 85"C
1M
10o
90
/
,
L
10
T
Z
~
!;
~
o
10
15
SUPPLYVOLTAGE- ±V
20
r\
o
'00
,..I
~
""
:l:
"'"
I
OUTPUT CURRENT -
4-141
,,_I_ ..oc
"l.
400
300
V
200
V-
>~
T'i-tC
0
800
........
\
100M
n
Supply Current as a
Function of
Supply Voltage ILA 108
Vs=±1SY
........
10M
1M
INPUT RESISTANCE -
Ti = Oc
Ti = i'oc
"
~ .. oc
"=-
\
>
"
-
II
10
100 k
n
Output Swing as a
Function of
Output Current ILA 108
!
ffi1f;08l108A' _55°C s T, < 125°C
~,ocl< T~ < ,8f;c
208I20fA
100M
10M
INPUT RESISTANCE -
I"'
~
TA < 125°C
1
~
r--1081208
10
Q
100k
15
V-
"'
0
Cj = 0
f = 100Hz
TA ~5"C
11 0 _
~_55°C
~ 'A - I
,/'""'
t:
V
ffi1f;08l108A _55°C <
AMBIENT TEMPERATURE _ °C
Voltage Gain as a
Function of
Supply Voltage ILA 108
~
100
~
/
108A1208A
5
125
"~
I
r-'08l208
~
OFFSET 208A/20B
/
a;
~
0
S5
~
t
.
,
v.
10
Iii
,..o
"~
,..
0
01
Maximum Drift Error
Maximum Offset Error
0
V
100
,
o
± mA
..........
v
T1 = ,,·c
I--
TA _loc
I--
10
15
SUPPlYVOLTAGE- ±V
20
JLA 10S/A • JLA20S/A • JLA30S/A
Typical Performance Curves for ILA308A and ILA308 (Unless Otherwise Specified)
Input Current as a
Function of
Ambient Temperature
Maximum Offset Error ILA308
•
> 1000
1000
T;I,~!c
E
3
Maximum Drift Error ILA308
I
O°C < TA < 70 0
/
e
w
~
I
....
ill
o~
....
'r-- t--
~
BIAS
1
g
0
i
0.25;>-
...........
~ 0.20
r--
~~
!!;
0.1 5
01 0
0
10
20
30
.a
i>
-
50
80
ffi
~
~
8D
"A",,2SoC_
110
~
w
g
r--t:::i = 10· e -
!""".;; r--..; ~
-
1\
10
TA, = 70
0
e
T!I -r'~·c
I-'"
./'
/
0
100
t
5
10
15
SUPPLY VOLTAGE-
+v
o-+'!,ll
--r
0
~·c
1.0
lOOk
100M
I I
1M
10M
100M
INPUT RESISTANCE - 0
400
Vs'.j5V
3SO
1\'
1.
I
.... ,so
z
~
.#
~200
T'Ol.C-
..---
........
..----
L
~
300
T,
TA
r
c
= 70 0 e
o
/
>-
~ 15
/'
0
'" 100
so
o
o
20
=MAX,MUM
Q
1 I
90
/
Supply Current as a
Function of
Supply Voltage
15
:c
"c
"~
10M
1M
Cf"" 0
f=1ooHz
T."O~
ill
Ii:
a:Q
III
Output Swing as a
Function of
Output Current
120
I
z
I'
~
INPUT RESISTANCE -
Voltage Gain as a
Function of
Supply Voltage
100
I
f--~YP'CAL
1.0
,100k
TEMPERATURE - DC
'll
V
o r-MAX'MUM
~
'"l?
./
....=>
!!;
70
I'
o
.
V
o
100
0
10
OUTPUT CURRENT -
15
20
SUPPLY VOlTAGE- ±V
± mA
Standard Compensation Circuits
R2
R2
R1
INVERTING --'IIII'v-_--t
INPUT
R3
NON·INVERTING --'I/'>N----1
INPUT
R1
INVERTING --'IIII'v---I
INPUT
. - - - - OUTPUT
R3
NON·INVERTING -"V'If'y---I
INPUT
4·142
OUTPUT
JLA 10S/A • JLA20S/A • JLA30S/A
Guarding
Extra care must be taken in the assembly of printed
circuit boards to take full advantage of the low input
currents of the J.lA 108 amplifier. Boards must be
thoroughly cleaned with TCE or alcohol and blown dry
with compressed air. After cleaning, the boards
should be coated with epoxy or silicone rubber to
prevent contamination.
Feedforward Compensation
Higher Slew Rate and
Wider Bandwidth
Standard Feedforward
C2
R1
10 kll
5 pF
INPUT--~~~----~Ir-----,
Even with properly cleaned and coated boards,
leakage currents may cause trouble at 125°C,
particularly since the input pins are adjacent to pins
that are at supply potentials. This leakage can be
significantly reduced by uSing guarding to lower the
voltage difference between the inputs and adjacent
metal runs. Input guarding of the S-pin TO-99 package
is accomplished by using a 10-pin circle, with the pins
of the device formed so that the holes adjacent tt;> the
inputs are empty when it is inserted in the b.oard. The
guard, which is a conductive ring surrounding the
inputs, is connected to a low impedance point that is
at approximately the same voltage as the inputs .
Leakage currents from high voltage pins are then
absorbed by the guard.
~~~OUTPUT
The pin configuration of the dual in-line package is
designed to facilitate guarding, since the pins
adjacent to the inputs are not used (this is
different from the standard J.lA741 and J.lA101A
pin configuration).
Open Loop Voltage Gain
120
100
e
80
--...
FOR~ARD
" , I"
FEEJ
C~PENSATION
'\
I
"'(
'\
80
"w
1
10
100
1k
t?""- 1
"- ~HASE
),-"
I-COMPS;;::T~~~
-20
f--
35
"
" ""
I:
'"
~
180
to k
FREQUENCY -
,,"OAIN
00
45
,I'\.
1"'..."
100 k
1M
10 M
Hz
Feedforward Compensation for Decoupllng Load Capacitance
R2
Rs>10kll
100 kll
INPUT~~~~-'-'----------~~--------~
R4
>6::.....~.;.50"'0"'1l.--_....._ OUTPUT
CL
75 pF
to 0.01
4·143
~F
•
JLA 10S/A • JLA20S/A • JLA30S/A
Inverting Amplifier
Board Layout for Input Guarding
With TO-99 Package
R2
Rl
INPUT -'l/V\r-.......- - -........' V V ' _ - - - - - ,
COMPENSATION
__~-OUTPUT
Follower
R3'
(Bottom View)
OUTPUT
INPUT ---~-+--I
Non-Inverting Amplifier
R2
OUTPUT
Rl
4·144
J.LA318
FAIRCHILD
High-Speed
Operational Amplifier
A Schlumberger Company
Linear Products
Description
The #A318 is a Precision High-Speed Operational
Amplifier designed for applications requiring wide
bandwidth and high slew rate. It features a factor of
ten increase in speed over general purpose devices
without sacrificing dc performance.
Connection Diagram
8-Pin Metal Package
COMPENSATION-2
The #A318 has internal unity gain frequency
compensation. This simplifies its application since no
external components are necessary for operation.
However, unlike most internally compensated
amplifiers, external frequency compensation may be
added for optimum performance. For inverting
applications, feedforward compensation will boost the
slew rate to over 150 V I #s and almost double the
bandwidth. Overcompensation can be used with the
amplifier for greater stability when maximum
bandwidth is not needed. Further, a single capacitor
can be added to reduce the 0.1% settling time to
under 1 #s.
v(Top View)
Order Information
Type
Package
ILA318
Metal
Code
5W
Part No_
#A318HC
The high speed and fast settling time of this op amp
makes it useful in aId converters, oscillators, active
filters, sample-and-hold circuits or general-purpose
amplifiers. This device is easy to apply and offers a
better ac performance than industry standards such
as the #A709.
•
•
•
•
•
•
•
15 MHz SMALL SIGNAL BANDWIDTH
GUARANTEED 50 V / #s SLEW RATE
MAXIMUM BIAS CURRENT OF 500 nA
OPERATES FROM SUPPLIES OF ± 5 V TO ± 20 V
INTERNAL FREQUENCY COMPENSATION
INPUT AND OUTPUT OVERLOAD PROTECTED
PIN COMPATIBLE WITH GENERAL PURPOSE
OPAMPS
Absolute Maximum Ratings
Supply Voltage
Power Dissipation (Note 1)
Differential Input Current (Note 2)
Input Voltage (Note 3)
Output Short Circuit Duration
Operating Temperature Range
Storage Temperature Range
Pin Temperature (Soldering, 60 s)
±20 V
500mW
±10 mA
± 15 V
Indefinite
O°C to +70°C
-65°C to +150°C
300°C
Notes
1 Tile maxImum junction temperature of the !LA318 IS 150·C for
operating at elevated temperatures. The package
must be derated based on a thermal resIstance of 150· C / W.
Juncllon to ambient or 45·C/W. Juncllon to case.
2 The onputs are shunte~ WIth back-to-back diodes for
overvoltage protection. Therefore. excessive current will flow
if a differential input voltage In excess of 1 V IS applied
between the inputs unless some limIting resIstance IS used.
3 For supply voltages less than ± 15 V. the absolute maximum
onput voltage IS equal to the supply voltage.
4-145
--
_. --- - - -
----
•
p,A318
Equivalent Cilcuit
BAUCOMP-3
BAL/COMP-1
COMP-2
1
5
(
\
'c,
\
R.
22k
~
)
t---
~n
R5
2.2k
Rl0
140k
013
V
Q15~~
JOk
30k
7
010t-.
VI
(']~
OC2
I
f-K
03:::
IN
3
a.:::
,.. ..
..
K05
~01
Rl
13k
.----
R5
44·
qa
T
v-
R.
8k
r~
l038
I5k
:f-
~
R23
lOll
~
- ~a32
2.
R
30
•
OUT
R21
3k
~033
45E
030
~~lE
R3
37k
8E
'E
035
-10pF
~
-10 PFJ
07r-
R22
~~~23~
~
~12
1E
017
35E
Q18
35'
R2.
~
R2
12k
-25pF
Cl
-25 pF
~
~02
75k
'--
I~
2
R25
Rl1;E~C2
R12
75k
011 1...1
IN
·~J037
~~6.)
r4
014
8
rl
022
~023
R14
1.Sk
1E
01.e-.E
a20~ I
"r
'~~'
021
2E
R18
:2~ :~v
K028
02.
027
5E
Rl'
15k
14Sk
4·146
02.
~rE
R20
loon
• v-
~A318
~A318
Electrical Characteristics
±5 V :5 VS :5 ±20 V. TA
Characteristic
= +25·C
Condition
Typ
Max
Unit
Input Offset Voltage
4
10
mV
Input Offset Current
30
200
nA
Input Bias Current
150
500
Min
Input Resistance
0.5
Supply Current
M!l
10
5
= ± 15 V. Your = ± 10 V. RL;::: 2 k!l
Vs = ± 15 V. Av = 1
Vs = ± 15 V
Large Signal Voltage Gain
Vs
Slew Rate
Small Signal Bandwidth
The following specifications apply for O·C
<
TA
<
nA
3
mA
25
200
V/mV
50
70
V/~s
15
MHz
+70·C
Input Offset Voltage
15
mV
Input Offset Current
300
nA
Input Bias Current
750
= ± 15 V. Your = ± 10 V. RL;::: 2 k!l
Vs = ± 15 V. RL = 2 k!l
Vs = ± 15 V
Large Signal Voltage Gain
Vs
Output Voltage Swing
Input Voltage Range
nA
20
V/mV
± 12
±13
V
± 11.5
V
Common-Mode Rejection Ratio
70
100
dB
Supply Voltage Rejection Ratio
65
80
dB
Typical Performance Curves
Input Current
Voltage Gain
200
100
l1S
5.
BIAS
100
TA:::
11.
50
~
.•
<>
80
ere
105
~
TA
JUPPLY
TA = 25-<:
\
20
TA = 7O"C
OFF,SET
100
I•
10
20
30
40
TEMPERATURE _
so
°c
60
70
..
= 25"C
.......
. ~t'TIVE
.. I--NEGATIVES~
~
1\
".
3.
2.
•
Power Supply Rejection
1\
'\,
~.
5
I.
,.
SUPPLY VOLTAGE -
4·147
-20
20
+Y
100
1k
10k
lOOk
FREQUENCY -
Hz
1M
"
10M
JLA318
Typical Performance Curves (Cont.)
Input Noise Voltage
.
TA = 25°C
VS"" "!:15Y
~
1000
1
120
irl
~
RS = 100k
'00
11-
'"
'"C
80
TA
~
10
IIII
,.
100
"
100
1k
10k
:>
">
it
"
Hz
,
-
/
\J
~
,
100
-V
1•
'l'
~
-400
Vs -
lOOk
1M
0
4
10
20
15
-800
25
-08 -0.6 -04 -02
mA
15
r--
l
70
0
TEMPERATURE _ °C
~
g
10
20
30
40
--
so
TEMPERATURE _ °C
4-148
80
70
lmY
,/
l-
80
14
l00 my}
'"
90
NEGATIVE SLEW
06
V
,~~~
I
Ys= :t-16Y
Rs "" AI' = 10 kll
C f = 5pF
I
04
10
>
~
02
Inverter Settling Time
110
11
0
DIFFERENTIAL INPUT -
Voltage Follower Slew Rate
120 ,--r--;--,--,.-,.-,--,
20
\
\
1"5 V
OUTPUT CURRENT -
"
~
1\
\
0
~ 100
Z
:>
\
~
:>
,.
~
\
:>
l-
II
".z
1\
I-
POSITIVE SLEW
":cI
200
TA"'25OC-
FREQUENCY -- Hz
l!
20
V
400
T A = 7..e-
0
Unity Gain Bandwidth
15
10
"
V
10k
10
5
800
z
Av=;/
TA ,70"C
Input Current
12
r--
/
f-- !--
45
40
14
AJ = 1000
/T.=\5'1: \
--
SUPPLY VOLTAGE -
Current Limiting
Vs "' ~15 V
TA =25"C
\"k-
ii:
10M
1M
tOOk
FREQUENCY -
Closed Loop Output Impedance
~
~
\
20
Hz
",-/
~
\.
40
o
100.
/- ~
I-
~
0
= ..
E
I 50
0
I
10.
FREQUENCY -
..
e-
= l00n,Rs = 1 k
II
3
10
Z
= 25°C
oC
~
~ 30
~A J
RS:::: 2 kn
"
.0
0
!!!
55
-
100
I
z
0
;::
~
Supply Current
Common, Mode Rejection
3000
Y, ""5 V
ii
5
I;
o
_1
r~~ :~5~
AF'" 5 ktl
CF= 10pF
',I'
l00C 1\.
Y
or-nmf 'm
_1 5
003
01
03
TIME - liS
lmY
Il
08
~A318
Typical Performance Curves (Cant.)
Large Signal
Frequency Response
Open Loop
Frequency Response
14
TA
I.
~
\
10
"
Z
!II
\
1\
4
o
!
C!l
80
"
~>
40
.
~
I
eo
06M
1M
2M
5M
10M
20M
SOM
~
I
~
!
~
6
Ys == "':15 Y
100
i
!\
."~
10
100
lk
~
3M
10M
tOOk
1M
>
>
20
30M
JI
100M
FREQUENCY - Hz
10k
IS
FREQUENCY -
T'-I~-
-.0-0'
100M
o.
01
1.0
11
14
Inverter Pulse Response
.0
Y
16
•••
.. i
,
135
M
90
iI
PHASV
"\
tOOk
~
Ys"'- +15 V
"
.. n
>
1M
"
I
4
!
a
\-
~
I
.-
-I'
FEEDFORWAAD
Vs 1=
0.1
0.3
r-
TA = aee
-16
-.0-0.1
10M 100M
-
/OUTPUT
I
\
\
\
L:
\.
h
- .- ._,.. rINPUT
~
Gj'N\
1k
-8
-II
1
'-./
100
II
-4
TIME - ",
FfEDFOrWARr
-'010
INPUT JOUTPUT
-"-
Hz
"", "-
.- '0-- ~
I
1\
-I'
10M
Ys =
["..
FEEOPORWARD
1M
10k
"c~
0
t.~"C
..
"~
0
4
-......
80
40
c
o
.
\
1~
---.
--I
~
".iz
1
K' -'"
120
iA ~ ~-hl
.
"
1
Open Loop
Frequency Response
-
10
16
PHJEj
FREQUENCY -
Large Signal
Frequency Response
"
I
"'-
FREQUENCY - Hz
14
A ••
20
-20
'0
iVs " :t15
~c
y-
"",
I
i!:
6
--.
100
Vs == "-15 V
~
~
120
.1'54 J
Voltage Follower
Pulse Response
05
07
"i
v
o.
nME-~.
Hz
Auxiliary Circuits
Feedforward Compensation For
Greater Inverting Slew Rate
Compensation for Minimum Settling Time
5 pF
5k
10k
3k
5k
INPUT
10k
-"""''1'<--4-...- ,
INPUT
OUTPUT
-"""''1'<--_'''1
OUTPUT
5k
Slew and settling time to 0.1% for a 10 V step change is 800 ns.
Slew rate tYPically 150 V / /lS.
Balance CirCUit necessary for increased slew.
4·149
~A318
Offset Balancing
Isolating Large Capacitive Loads
v+
AF
,..---""'I'v--.....-
.....-
OUTPUT
200 k
AS
INPUT
--""'I'v-+--I
Overcompensation
Typical Applications
Fast Voltage Follower
Weln Bridge Sine Wave OSCillator
5pF
A1
750
10k
>'-<1-.....L1'
A2
.ok
1'>
Fast Summing Amplifier
5pF
5k
INPUT 2
10 k
L 1 = 10
=
R2 R3
Cl = C2
5k
INPUT 2
v-
14 rnA bulb ELDEMA 1869
1
1= 2... R2 Cl
Differential Amplifier
10 k
10k
INPUT
10 k
INPUT
10k
4-150
OUTPUT
JLA 124 • JLA224 • JLA324
JLA2902 Quad
Operational Amplifiers
FAIRCHILO
A Schlumberger Company
Linear Products
Description
The JJ.A 124 series of Quad Operational Amplifiers
consists of four independent high-gain, internally
frequency-compensated operational amplifiers
designed to operate from a single power supply or
dual power supplies over a wide range of voltages.
The common mode input range includes the negative
supply, thereby eliminating the necessity for external
biasing components in many applications. The output
voltage range also includes the negative power supply
voltage. They are constructed using the Fairchild
Planar epitaxial process.
•
•
•
•
•
Connection Diagram
14-Pin DIP
OUT A
OUT 0
-IN A
-IN 0
+IN A
+IN 0
v+
INPUT COMMON MODE VOLTAGE RANGE
INCLUDES GROUND OR NEGATIVE SUPPLY
OUTPUT VOLTAGE CAN SWING TO GROUND OR
NEGATIVE SUPPLY
FOUR INTERNALLY COMPENSATED
OPERATIONAL AMPLIFIERS IN A
SINGLE PACKAGE
WIDE POWER SUPPLY RANGE SINGLE OF 3.0 V
to 30 V DUAL SUPPLY OF ± 1_5 V to ± 16 V
POWER DRAIN SUITABLE FOR
BATTERY OPERATION
v-
OR GND
+IN B
+IN C
-IN B
-IN C
OUT B
OUT C
(Top View)
Order Information
Type
Package
JJ.A 124
Ceramic DIP
JJ.A224
Molded DIP
JJ.A224
Ceramic DIP
JJ.A324
Molded DIP
JJ.A324
Ceramic DIP
JJ.A2902
Molded DIP
Code
6A
6A
9A
6A
9A
9A
Part No_
JJ.A124DM
JJ.A224PV
JJ.A224DV
JJ.A324PC
p.A324DC
JJ.A2902PV
Equivalent Circuit (1/4 of circuit shown)
OUTPUT
~------------.-----------.---~~--------.------+-+------.----v+
+-+------------~~-----,
3. S.
10.12
INPUTS
4-151
J.LA 124 • J.LA224 • J.LA324 • J.LA2902
Absolute Maximum Ratings
Supply Voltage Between V+
and V32
Differential Input Voltage (Note 1) 32
Input Voltage (V-) (Note 1)
-0.3 V (V-) to V+
Internal Power Dissipation
(Note 2)
670mW
Operating Temperature Range
-55°C to +125°C
/J.A124
-25°C to +85°C
/J.A224
O°C to +70°C
/J.A324
/J.A2902
-40°C to +85°C
Storage Temperature Range
-55°C to +125°C
Molded DIP
-65°C to +150°C
Ceramic DIP
Pin Temperature (Soldering)
260°C
Molded DIP (lOs)
Ceramic DIP (60 s)
300°C
Notes
1. Tlow = -55°C for jtA124
Thigh = +125°e for jtA124
= -40°C for jtA2902
= +85°e for jtA2902
= -25°C for jtA224
and jtA224
= ooe for jtA324
= +70 oe for jtA324
2. The input common-mode voltage or either Input signal voltage
should not be allowed to go negative by more than 0.3 V. The
upper end of the common-mode voltage range is Vee - 1.5 V,
but either or both inputs can go to +32 V without damage
(+26 V for jtA2902).
3. Short circUits from the output to Vee can cause excessive
heating and eventual destruction. Destructive dissipation can
result from Simultaneous shorts on all amplifiers.
4-152
~A124·~A224·~A324·~A2902
IJ.A 124, IJ.A224 and IJ.A324
Electrical Characteristics
Vee
= 5.0 V,
VEE
= GND, TA = 25°C unless otherwise noted.
IJ.A124/IJ.A224
Symbol
Via
Characteristic
Condition
Input Offset Voltage
Vee = 5.0 V to 30 V
Vie = 0 V to Vee -1.5 V,
Va"", 1.4 V, Rs = 0 f!
TA = Thigh to Tlow (Note 1)
Average Temperature
AVIO/AT Coefficient of Input
Offset Voltage
110
Input Offset Current
Alia/AT
Average Temperature
Coefficient of
Input Offset Current
liS
Input Bias Current
VieR
Input Common-Mode
Voltage Range
(Note 2)
Min
2.0
5.0
7.0
= Thigh to Tlow (Note
1)
TA
= Thigh to Tlow (Note
1)
TA
= Thigh to Tlow (Note
1)
10
= Thigh to Tlow (Note
Vee = 30 V
Vee = 30 V
TA = Thigh to Tlow (Note
1)
-45
-40
TA
AVOL
Large Signal OpenLoop Voltage Gain
RL
TA
Channel Separation
1.0 kHz :5 f :5 20 kHz,
Input Referenced
CMMR
Common-Mode
Rejection Ratio
Rs:5 10 kf!
PSSR
Power Supply
Rejection Ratio
VOH
Output Voltage-High
1)
IJ.A324
Min
7.0
3.0
Differential Input
Voltage Range
Typ
Max
Unit
2.0
7.0
9.0
mV
= 2.0 kf!, Vee = 15 V,
= Thigh to Tlow (Note 1)
30
5.0
± 100
-150
-300
-45
-50
10+
Output Source Current
(VID = +1.0 V, Vee = 15 V)
TA = Thigh to Tlow (Note 1)
10-
Output Sink Current
VID = -1.0 V, Vee
15 V
TA = Thigh to Tlow (Note 1)
VID
-1.0 V, Va = 200 mV
los
Output Short Circuit to
Ground (Note 3)
=
=
(T A = Thigh to Tlow) (Note 1)
Vee = 30 V, Va
0 V,
RL = 00
Vee = 5 V, Va = 0 V,
RL = 00
=
Power Supply Current
Notes
1. Tlow = -55'e for I'A124
Thigh = +125'e for I'A124
-40'e for I'A2902
+85'e for I'A2902
= -25'e for I'A224
and I'A224
= 0' e for I'A324
= +70'e for I'A324
2. The input common-mode voltage or either ,"put signal voltage
should not be allowed to go negative by more than 0.3 V The
-250
nA
-500
28.5
0
28.5
0
28
0
28
50
25
100
Vee
25
15
nA
pA/oC
0
100
V
V
V/mV
-120
dB
70
85
65
70
dB
65
100
65
100
dB
28
26
27
28
(TA = Thigh to Tlow) (Note 1)
26
Vee = 30 V, RL = 2 kf!
27
Vee = 30 V, RL = 10 kf!
Vee = 5.0 V, RL = 10 kf!,
TA = Thigh to Tlow (Note 1)
50
150
10
-120
Output Voltage-Low
IJ.V/oC
7.0
Vee
VOL
=
Max
TA
VIDR
lee
Typ
5.0
V
5.0
20
20
mV
20
10
40
20
20
10
40
20
rnA
10
5
12
20
8
50
10
5
12
20
8
50
rnA
rnA
IJ.A
40
60
40
60
1.5
3.0
1.5
3.0
0.7
1.2
0.7
1.2
rnA
rnA
upper end of the common-mode voltage range is Vee - 1.5 v,
but either or both inputs can go to +32 V without damage
(+26 V for I'A2902).
3 Short cirCUits from the output to Vee can cause excessive
heatong and eventual destructoon. Destructive diSSipation can
result from simultaneous shorts on all amplifiers.
=
4-153
p,A 124 • p,A224 • p,A324 • p,A2902
/LA2902
Electrical Characteristics
(Cont.) Vee = 5.0 V, VEE = GND, TA = 25°C unless otherwise noted.
/LA2902
Symbol
VIO
Min
Characteristic
Condition
Input Offset Voltage
Vee = 5.0 V to 26 V, Vie = 0 V
to Vee -1.5 V, Va """ 1.4 V, Rs = 0 Q
TA = 25°C
T A = Thigh to Tlow (Note 1)
Average Temperature
.:lVIO/.:lT Coefficient of Input
Offset Voltage
5.0
45
TA = Thigh to Tlow (Note 1)
10
TA = Thigh to Tlow (Note 1)
-45
-50
Average Temperature
Coefficient of
Input Offset Current
liB
Input Bias Current
VieR
Input Common-Mode
Voltage Range
(Note 2)
VIDR
Differential Input
Voltage Range
AVOL
Large Signal OpenLoop Voltage Gain
RL = 2.0 kQ, Vee = 15 V,
For Large Va Swing,
TA = Thigh to Tlow (Note 1)
Channel Separation
1.0 kHz :S f :S 20 kHz,
Input Referenced
CMMR
Common-Mode
Rejection Ratio
RS:S 10 kQ
PSSR
Power Supply
Rejection Ratio
VOH
Output Voltage-High
Output Source Current
10-
Output Sink Current
lOS
Output Short Circuit to
Ground (Note 3)
lee
Power Supply Current
7.0
10
TA = Thigh to Tlow (Note 1)
.:lIla 1.:IT
10+
2.0
7.0
Input Offset Current
Output Voltage-Low
Max
T A = Thigh to Tlow (Ndte 1)
110
VOL
Typ
Vee = 26 V
Vee = 26 V, TA = Thigh to Tlow
0
0
15
(T A = Thigh to Tlow) (Note 1)
Vee = 26 V, RL = 2 kQ
Vee = 26 V, RL
10 kQ
=
=
=
(VID = +1.0 V, Vee = 15 V)
=
VID = -1.0 V, Vee
15 V
TA
Thigh to Tlow (Note 1)
=
(T A = Thigh to Tlow) (Note 1)
Vee = 26 V, Va
0 V, RL
(Xl
Vee = 5 V, Va
0 V, RL = (Xl
=
=
Notes
1. Tlow = -55°C for "A 124
Thigh = +125°e for "A124
= +85°e for "A2902
= -40°C for "A2902
= -25°C for "A224
and "A224
= ooe for "A324
= +70 oe for "A324
2. The Input common-mode voltage or either input signal voltage
should not be allowed to go negative by more than 0.3 V. The
=
mV
/LV 1 ° C
50
200
nA
pA/oC
-250
-500
nA
24.5
24
V
Vee
V
100
V/mV
-120
dB
50
70
dB
50
100
dB
22
23
24
Vee
5.0 V, RL :S 10 kQ,
TA
Thigh to Tlow (Note 1)
TA = Thigh to Tlow (Note 1)
Unit
V
5.0
20
10
40
20
10
5
20
100
mV
rnA
rnA
8
40
60
rnA
1.5
0.7
3.0
1.2
rnA
upper end of the common-mode voltage range is Vee - 1 5 V,
but either or both inputs can go to +32 V without damage
(+26 V for "A2902).
3. Short circuits from the output to Vee can cause excessive
heating and eventual destruction. Destructive dissipation can
result from simultaneous shorts on all amplifiers.
4-154
~A124·~A224.~A324.~A2902
Typical Performance Curves
Large Signal Open Loop Voltage Gain as a
Function of Frequency
'I
120
~
130
,
"w
"
.~
0
9
z
~
0
;I
z
V~ J11.IV_
TA
..
.
..
~
= 25"C_
......
......
......
~
20
......
r-....
~
10
100
1.0k
FREQUENCY -
V+ = +5 YdC
10+ -
I
"0I
j
t
01
ry
OUTPUT SOURCE CURRENT -
100
.. ~1.
,
".
.55
mAde
10 -
001
"
!:;
10
0
>
'0
50
I II T = ~25'C I III
01
10
OUTPUT SINK CURRENT -
_50
10k
100
mAde
Input Bias Current as a
Function of Temperature
w 20
200
!i!
r---
V
~
10
Input Bias Current as a
Function of
Supply Voltage
1i
,
ffiII:
170
§
160
u
......
"-
~
150
-/
o
o
20 4.0 6.0 80 10
12
14
16
18
20
V+ AND V-. POWER SUPPLY VOLTAGES - y
o
-75-55-35155025456585105125
TEMPERATURE - C
4-155
,
i
i
100
/
50
10M
Hz
Vs 1= .\5V
300
~
--
lOOk
180
= aoc_
30
"
10k
FREQUENCY -
400
TA
I'
0
w
i.5
20
>
+
VI I"
0001
Rl = 10kU
TA = 2S8 C
I
1.
~
V~=I,n
1\
25
w
001
10
01
.
>
~I
v.
~
Output Swing as a
Function of
Supply Voltage
I,
".
.."......
IIIIIIII
g
TiiliT
001
y+
V+
!:;
'0'
0.001
= +15 Vdc
= +30 Vdc
;
w
INDEPENDENT OF 'y~
1
30
I
...• ~
IIll
Output Voltage as a
Function of Frequency
10
!1"
5
10M
lOOk
Output Characteristics
Current Sinking
Output Characteristics
Current Sourcing
IIII I "" I
10k
Hz
o
o
2.0 40 60 80 10
12
14
1. 1.
20
V+ AND V-, POWER SUPPLY VOLTAGES - Y
f.lA 148 • f.lA248 • f.lA348
I=AIRCHILO
Quad Operational
Amplifiers
A Schlumberger Company
Linear Products
Connection Diagram
14 Pin DIP
Description
The j.tA 148 series is a true quad j.tA 7 41. It consists of
four independent, high-gain, internally-compensated,
low-power operational amplifiers which have been
designed to provide functional characteristics
identical to those of the familiar j.tA 7 41 operational
amplifier. In addition, the total supply current for all
four amplifiers is comparable to the supply current of a
single j.tA741 type op amp.
OUT A
-IN A
+IN A
V+
Other features include input offset currents and input
bias current which are much less than those of a
standard j.tA741. Also, excellent isolation between
amplifiers has been achieved by independently
biasing each amplifier and using layout techniques
which minimize thermal coupling.
•
•
•
•
•
•
•
•
•
•
+IN B
-IN B
OUT B
j.tA741 OP AMP OPERATING CHARACTERISTICS
LOW SUPPLY CURRENT DRAIN
CLASS AB OUTPUT STAGE-NO
CROSSOVER DISTORTION
PIN COMPATIBLE WITH THE j.tA324 & j.tA3403
LOW INPUT OFFSET VOLTAGE-1 mV TYP
LOW INPUT OFFSET CURRENT -4 nA TYP
LOW INPUT BIAS CURRENT-30 nA TYP
GAIN BANDWIDTH PRODUCT FOR
j.tA148 (UNITY GAIN)-1.0 MHz TYP
HIGH DEGREE OF ISOLATION BETWEEN
AMPLIFIERS-120 dB
OVERLOAD PROTECTION FOR INPUTS
AND OUTPUTS
(Top View)
Order Information .
Type
Package
j.tA 148
Ceramic DIP
j.tA248
Ceramic DIP
j.tA348
Ceramic DIP
j.tA348
Molded DIP
Code
6A
6A
6A
9A
Part No.
j.tA148DM
j.tA248DC
j.tA348DC
j.tA348PC
Absolute Maximum Ratings
Supply Voltage
Differential Input Voltage
Input Voltage
Output Short·Circuit
Duration (Note 1)
Power Dissipation (Po at
25°C) and Thermal
Resistance (OJA), (Note 2)
Molded DIP
Po
8JA
Ceramic DIP
Po
8JA
Operating Temperature
Storage Temperature
Pin Temperature (Soldering)
Molded DIP (lOs)
Ceramic DIP (60 s)
j.tA148
±22 V
±44V
±22 V
j.tA248
± 18 V
±36 V
± 18 V
j.tA348
± 18 V
±36 V
± 18 V
continuous
continuous
continuous
670 mW
100°C/W
-55°C
8I
o
15
"'!::
z!
o~
"'ocw
"'"
~~
r . /1/
10
/
d l-t-125 d
:5 TA
/
1/
Negative Common Mode
Input Voltage Limit as a
Function of Supply Voltage
-2. r--,---,---,--r--,--,
1/
I
w>
8I
~
I
•
!f;! 5
~
-10 1--!--I>-/-'#1---+---+---1
5>
Av
Vo
I
I
NEGATIVE SUPPLY VOLTS -
,.
1
>
I
•
I
/
J,i
Ys = ±15 V
RL === 2 k
TA
25°C
=
'"'7V'N
'00
"c-'.!or~
>
,.
.,.••
TIME
-~.
=-
,.
V'N
.
08
i
08
!'"
04
!
I
llllill III iI
,.. 1111111,. 1U , •
..
02
Hz
Inverting Large Signal
Pulse Response
v!.±~v_
RL=2k
Vo
1
II
•
\
~
1«
MEAN NOISE CURRENT
20
,.
~
w
•
••
MEAN NOISE VOL TAOEI
FREQUENCY -
vb
I
G
\
"
Z
10
n
V
Large Signal Pulse Response
= 2S C
1\
&0
1\
•,.
2.
~
~
o
"
V
Vs = !o15 Y
TA
80
14;0:
£!
w 100
g~
,.
"Z
120
I
Z
~
15
~ I±l~ U
V5 1
TA = 25°C
::l
z
~ -10
g
-15 f--t----1----1---t-:h~---1
"'~
",w
Small Signal Pulse Response
,.•
~
8~
,.
..
,
~ 140
~i
POSITIVE SUPPL Y VOLTS -
Input Noise Voltage and
Noise Current as a
Function of Frequency
,.....
,.
~Z~~oc-
\
\
II
'"'?""
•
V,N
10
••
12•
TIME -
Jl8
4-159
180
200
o
20
40
so
80 100 120 140 180 180 200
TIME -
~s
J.LA 148 • J.LA248 • J.LA348
Typical Performance Curves (Cont.)
Supply Current as a
Function of Power
Supply Voltage
Input Bias Current as a
Function of
Ambient Temperature
•
Output Voltage Swing as a
Function of
Supply Voltage
0
50
80
>
I
0
"
5
+25.~,<......
3
2
1
~
0
4
V
>-
0
0
--:::::: ~ ~
or0
0
15
5
5
1
.."::!
10 Vs-
-t;::;- ~ l.:---
~
.
"
~
o
\-s•.c
\\
+r\
,.
o~
.
+125°C
10
2.
20
OUTPUT SOURCE CURRENT -
~"
o
z
~
t\-
0
f'..
-1 0
100
1 k
10 k
FREQUENCV -
100 k
Hz
1 M
J
15 V
25
20
30
mA
-25
-30
FREQUENCY -
-38
01
Hz
Gain Band Width as a
Function of Temperature
1DO
90
80
.
70
10k
50
"-\
r1>1
."..".
10 M
TA=25°C
PHASE
-10
-15
v~-\sV
1111
IIILIl
......,.~
-5
-20
""
25
Output Impedance as a
Function of Frequency
Gain as a Function of Frequency
'8
"
15
10
OUTPUT SINK CURRENT -
1\
o
20
V
0
mA
10
",
15
10
SUPPLY VOLTAGE -
+125°C
15
0
o
1\~ l'o-,-sJ.c
30
t\-
ICJ
105 125
QC
-5
20
I'-
85
V
+25°1\ f"\
-10
"iil
Ys - lS V
TA = 25 C C
"
65
V
10
V
Ie
CMRR and Open Loop
Frequency Response as a
Function of Frequency
0'
45
Vs
>
1\
0
25
-15
"z I::----
'l\
5
-5
V
20
>-
Output Voltage as a
Function of Sink Current
r'\,r\
25°C
V
0
t- f:;:E=='
TeMPERATURE -
>
I
=
V
30
0
~~5VS
.......
S
55 -35 -15
20
Ys '" 15 V
0
10
-
~~--
V
Output Voltage as a
Function of Source Current
o
'II
I
",so
'-..20V5
0
10
SUPPLY VOLTAGE -
11 0
~:>
.......
ot'-,
~ ......-> I--
TA
40
Z
40
GAIN
30
20
l
2k
\
FREQUENCY -
MHz
10
:l!
~
..~
:0
III
l!
2
I
3.0
S
;
z
~
20
"',48
10
.".
4·160
10
10
0
-55
·35
·15
5
25
45
TEMPERATURE -
85
ac
85
105 125
JLA 1458 • JLA 1558 Dual
Internally Compensated
Operational Amplifiers
F=AIRCHILO
A Schlumberger Company
Linear Products
Connection Diagram
8-Pin Metal Package
Description
The /LA 14581 /LA 1558 are a monolithic pair of Internally
Compensated High Performance Amplifiers
constructed using the Fairchild Planar epitaxial
process. They are intended for a wide range of analog
applications where board space or weight are
important. High common mode voltage range and
absence of "latch-up" make the /LA14581/LA1558
ideal for use as voltage followers. The high gain and
wide range of operating voltage provides superior
performance in integrator, summing amplifier and
general feedback applications.
Vee+
Vee-
The /LA 14581 /LA 1558 are short-circuit protected and
require no external components for frequency
compensation. The internal 6 db 1octave roll-off
insures stability in closed loop applications. For single
amplifier performance, see the /LA741 data sheet.
(Top View)
Order Information
Type
Package
/LA 1458
Metal
/LA 1458C
Metal
/LA 1558
Metal
The Fairchild /LA 14581 /LA 1558 slew rate has been
improved to 0.81/Ls typical.
• NO FREQUENCY COMPENSATION REQUIRED
• SHORT-CIRCUIT PROTECTION
• LARGE COMMON-MODE AND DIFFERENTIAL
VOLTAGE RANGES
• LOW POWER CONSUMPTION
• NO LATCH-UP
• MINI DIP PACKAGE
Absolute Maximum Ratings
Supply Voltage
Military (/LA1558)
Commercial (/LA 1458 and
/LA 1458C)
Internal Power Dissipation
(Note 1)
Metal Package
DIP
Differential Input Voltage (Note 2)
Common-Mode Input Swing
(Note 2)
Output Short Circuit Duration
(Note 3)
Storage Temperature Range
Operating Temperature Range
Military (/lA 1558)
Commercial (/LA 1458 and
/LA 1458C)
Pin Temperature (Soldering, 60 s)
Metal Package
Mini DIP (Soldering, 10 s)
Part No_
/LA 1458HC
/LA1458CHC
/LA 1558HM
Code
5W
5W
5W
•
Connection Diagram
a-Pin DIP
Vee+
OUTA
-IN A
OUTB
+INA
-IN B
Vee-
+IN B
±22 V
± 18 V
(Top View)
500 mW
310mW
±30 V
Order Information
Type
Package
/LA 1458
Ceramic DIP
/LA 1458
Molded DIP
/LA 1458C
Ceramic DIP
/LA 1458C
Molded DIP
/lA 1558
Ceramic DIP
± 15 V
Indefinite
-65°C to +150°C
Part No_
/LA 1458RC
/LA 1458TC
/LA1458CRC
/LA 1458CTC
/LA 1558RM
Code
6T
9T
6T
9T
6T
Notes on following pages.
4-161
.----------~
..
~-
..
.---- ----
-~-~---.-.--
JLA 1458 • JLA 1558
Equivalent Circuit
(Each Amplifier)
.....- - - t _ - - - - - - - - - - - - t _ - + V c c
r--t------;p-----~------
R6
27 II
OUTPUT
NON-INVERTING
INPUT
R7
22 II
INVE~J~~~---t--+----;---'
R5
39 kll
300
R1
R3
R2
R4
1 kll
50 kl!
1 kll
5 kll
L----~--~--~
__
30pFr---t-----t------------,
!l
R11
50 kll
----~--~---4_--~~-~----~--~-~~--VCC
Notes
1. Rating applies to ambient temperatures up to 70°C. Above
70°C ambient derate linearly at 63 mW / °C for the Metal
Package and 5.6 mW / °C for the mini DIP.
2 For supply voltages less than ± 15 V, the absolute maximum
Input voltage IS equal to the supply voltage.
3. Short CirCUit may be to ground or either supply. Rating applies
to + 125°C case temperature or 70°C ambient temperature.
4-162
JlA 1458 • JlA 1558
Electrical Characteristics
V S = ± 15 V T A = 25 0 C unless otherwise specified
Characteristic
Condition
Input Offset Voltage
RS:S 10 kll
~A1458C
~A1458
Min
Typ
Max
2.0
Input Offset Current
Input Bias Current
Differential Input Impedance
Parallel Input Resistance
Parallel Input Capacitance
Common-Mode Input
Impedance
0.3
f = 20 Hz,
Open Loop
f = 20 Hz
Common-Mode Input
Voltage Swing
Equivalent Input
Noise Voltage
Common-Mode
Rejection Ratio
±12
AV = 100
Rs = 10 kll
f = 1.0 kHz
BW = 1.0 Hz
Min
Max
Typ
Max
6.0
2.0
10
1.0
5.0
mV
.03
0.2
.03
0.3
0.03
0.2
~A
0.2
0.5
0.2
0.7
0.2
0.5
~A
70
Min
Unit
1.0
1.0
1.0
Mil
6.0
6.0
6.0
pF
200
200
200
Mil
±13
V
45
nV/yHz
90
dB
±13
±11
45
f = 100 Hz
~A1558
Typ
0.3
±13
±12
45
90
60
90
70
•
Open-Loop
VOUT = ± 10 V
20 k 100 k
20 k 100 k
50 k 200 k
V IV
_V_o_lta_g~e__
G_a_in__________~R~L~=
__2_.0__
kll
____~----~--~----+----r---4----+----r--~----+_----Av = 1
RS = 2.0 kll
Power Bandwidth
14
14
14
kHz
THD:s 5%
VOUT = 20 Vpk-pk
Unity Gain Crossover
Frequency (Open Loop)
1.1
1.1
1.1
MHz
Phase Margin
(Open Loop)
65
65
65
Degrees
dB
Gain Margin
11
11
11
Slew Rate
AV = 1
0.8
0.8
0;8
Output Impedance
f = 20 Hz
75
75
75
20
20
20
mA
± 14
V
Short-Circuit Output
Current
Output Voltage Swing
Power Supply Sensitivity
Vcc- = Constant
V cc+ = Constant
Power Supply Current
Power Dissipation
RL
=
±14
: 11
±14
± 12
RS:S 10 kll
30
150
30
1+
2.3
5.6
2.3
8.0
1-
2.3
5.6
2.3
8.0
VOUT = 0
70
170
70
240
The following specifications apply for 0 0 C
Input Offset Voltage
±12
10 kll
<
TA
<
150
~V IV
2.3
5.0
mA
2.3
5.0
mA
70
150
mW
30
70 0 C (~A 1458 and ~A 1458C) -55 0 C :S T A :S 125 0 C (~A 1558)
RS:S 10 kQ
Input Offset Current
Input Bias Current
Open-Loop
Voltage Gain
VOUT = ± 10 V
RL = 2.0 kQ
15 k
Output Voltage Swing
RL = 2 kQ
±1O
Average Temperature
Coefficient of Input
Offset Voltage
RS = 50 Il
± 13
15
4-163
7.5
12
6.0
mV
0.3
0.4
0.5
~A
0.8
1.0
1.5
~A
15 k
25 k
±9.0 ±13
± 10
15
VIV
± 13
V
15
~V/oC
•
llA 1458 • llA 1558
Typical Performance Curves for p.A 1458, p.A 1458C and p.A 1558
Vcc+ = +15 V, VCC- = -15 V, TA = 25°C unless otherwise noted
Open-Loop Voltage Gain as a
Function of
Power Supply Voltages
Power Bandwidth
(Large Signal Swing as a
Function of Frequency)
Output Voltage Swing as a
Function of
Load Resistance
120
2
!g
115
8
281Ittttl~~~~~
Z
110
4
~24~-1-1-tiT~t---r-~-H~
;;:
~
105
"~
100
!;
..o
g
~
o
9'
V
!;
85
40
60
90
15
12
18
POWER SUPPLY VOL.TAGE -
"
"~
w
140
g
;-20
-20
10
100
V
I I I II
10
'\
100 k
10 k
FREQUENCY -
LOAD RESISTANCE -
Hz
Power Dissipation as a
Function of
Power Supply Voltage
!l
Output Noise as a
Function of
Source Resistance
10 0
0
0
0
0
0
·100
t60
1111
10
'-120
t80
::;5 80r-~--t---H
RL = 2 k
VOLTAGE FOLLOWER
:::15 V SUPPLlES
THO < 5%
o
21
Open-Loop Frequency Response
z
;;:
5 12 r---t--,t---H
2
0
!8
~ 20r--1-1-t~+tt~~~ri-HitH
""~ 16 r---+--t-ft
6
90
80
30
1\
0
.-V
~
~
'"
10
100
10k
~
10 k
FREQUENCY -
~
Vo
~-
0-
L
V
V
0
0
0
0
0
0
[\
0
100 k 10M 10 M
20
Hz
60
10
14
18
POWER SUPPLY VOLTAGE -
22
V
SOURCE RESISTANCE -
11
Typical Applications
High-Impedance, High-Gain Inverting Amplifier
Quadrature Oscillator
v+
C2
C3
820 pF
1%
SINE
OUTPUT
820 pF
1%
01
+15 V
02
+15 V
>-.........._~COSINE
OUTPUT
R2
180 kll
1%
R
R1
1%
Note
1
f;
2... yC2R2C3R3
4-164
(R1C1 ; R2C2)
190 kll
1%
:r
C1
820 pF
1%
/-LA 1458 • /-LA 1558
Typical Applications (Cont.)
Compressor IExpander Amplifiers
01
R
R2
10 kll
Rl
+15 V
COMPRESSOR ......lv..kl\ll,.....~
INPUT
R3
10 kll
R
02
COMPRESSOR
OUTPUT
R5
03
R
1 kll
+15 V
R4
10 kll
EXPANDER
INPUT
>-----......
-<}-- ---<}-+-.......'VY-_-.....'"""4 > ___ EXPANDER
1/2
OUTPUT
MA1558
-15 V
R
04
EXPANDER
COMPRESSOR
Notes
MaxImum compression expansIon ratIo = R 11 R (10 kSl > R 2: 0)
DIodes 01 through 04 are matched FD6666 or equIvalent
Analog Multiplier
+15
v
R13
1.5 kll
1%
CURRENT SOURCE
lN9638
R2
20 kll
1%
AMPLIFIER
R14
25.8 kW
1%
R12
12 k!l
1%
Rl
20 kll
1%
> __...
E~OUT
1/2 MA1558
R5
-15 V
R3
20 kll
1%
5 kll
1%
-liN
R4
15 kll
1%
R7
150 kll
Rl0
150 kll
-15 V
• Matched to O. 1%
EOUT
=
100 EINl x EIN2
4-165
ZERO ADJUST
+15 V
•
~A3303 • ~A3403 Quad
FAIRCHILO
Operational Amplifiers
A Schlumberger Company
l,
Linear Products
Description
The !lA3303 and IlA3403 are Monolithic Quad
Operational Amplifiers consisting of four independent
high·gain, internally frequency·compensated
operational amplifiers designed to operate from a
single power supply or dual power supplies over a
wide range of voltages. The common mode input range
includes the negative supply, thereby eliminating the
necessity for external biasing components in many
applications. They are constructed using the Fairchild
Planar epitaxial process.
•
•
•
•
•
•
•
•
Connection Diagram
14-Pin DIP
OUT A
~IN
OUT 0
A
~IN
+IN A
+IN 0
v+
INPUT COMMON MODE VOLTAGE RANGE
INCLUDES GROUND OR NEGATIVE SUPPLY
OUTPUT VOLTAGE CAN SWING TO GROUND OR
NEGATIVE SUPPLY
FOUR INTERNALLY COMPENSATED
OPERATIONAL AMPLIFIERS IN A
SINGLE PACKAGE
WIDE POWER SUPPLY RANGE SINGLE SUPPLY
OF 3.0 TO 36 V
DUAL SUPPLY of ± 1.5 TO ± 18 V
CLASS AB OUTPUT STAGE FOR MINIMAL
CROSSOVER DISTORTION
SHORT CIRCUIT PROTECTED OUTPUTS
HIGH OPEN LOOP GAIN 200 k
'fA741 OPERATIONAL AMPLIFIER
TYPE PERFORMANCE
0
v~
OR GND
+IN B
+IN C
B
-IN C
~IN
OUT B
OUT C
(Top View)
Order Information
Type
Package
!lA3303
Molded DIP
!lA3403
Ceramic DIP
!lA3403
Molded DIP
Code
9A
6A
9A
Part No.
!lA3303PC
!lA3403DC
!lA3403PC
Equivalent Circuit (1 14 of circuit shown)
OUTPUT
r-------------~--------~~--~--~----~------+_~----~---V+
NONINVERTING _~f-----------++------,
INPUT
3,5,
10,12
INVERTING
INPUT
2,6,
9.13
11
~~~~------~--~--~--~--+---~----~--~~--~--~------~~----~~-V
(GROUND)
4-166
ILA3303 • ILA3403
Absolute Maximum Ratings
Supply Voltage Between V+
and VDifferential Input Voltage
(Note 1)
Input Voltage (V-) (Note 1)
Internal Power Dissipation
(Note 2)
Operating Temperature Range
/LA3303
/LA3403
Electrical Characteristics
Storage Temperature Range
Molded Package
Ceramic Package
pfn Temperature (Soldering)
Molded Package (10 s)
Ceramic Package (60 s)
36 V
±30 V
-0.3 V(V-) to V+
670 mW
-55°C to +125°C
-65°C to +150°C
260°C
300°C
Notes
1. For supply Voltage less than 30 V between V+ and V-. the
absolute maximum input voltage is equal to the supply voltage.
2. Rating applies to ambient temperature up to 70°C. derate
linearly at 8.3 mW 1°C.
-40°C to +85°C
O°C to +70°C
Vs = ± 15 V. TA = 25°C unless otherwise noted.
/L3303
Characteristic
Condition
Min
Typ
Max
Input Offset Voltage
2.0
8.0
mV
Input Offset Current
30
75
nA
200
-500
nA
Input Bias Current
Input Impedance
f = 20 Hz
0.3
Input Common Mode Voltage Range
.:s
1.0
Unit
MQ
+12 to +12.5
-Vs
to -VS
V
70
90
dB
20
200
V/mV
Common Mode Rejection Ratio
RS
Large Signal Open
Loop Voltage Gain
VOUT = ± 10 V. RL = 2 kQ
Power Bandwidth
AV = 1. RL = 2 kQ. VOUT = 20 V pk-pk
18
kHz
Small Signal Bandwidth
Av= 1.RL= 10kQ.VOUT=50mV
1.0
MHz
10 kQ
Slew Rate
AV = 1. VIN = -10 V to + 10 V
0.6
V//Ls
Rise Time
Av = 1. RL = 10 kQ. VOUT = 50 mV
0.3
/LS
Fall Time
Av = 1. RL = 10 kQ, VOUT = 50 mV
0.3
/LS
Overshoot
AV = 1, RL = 10 kQ, VOUT = 50 mV
5.0
Phase Margin
Av = 1, RL = 2 kQ, CL = 200 pF
60
%
Degree
Crossover Distortion at f = 10kHz
VIN = 30 mV pk-pk, VOUT = 2 V pk-pk
Output Voltage Range
RL = 10 kQ
RL = 2 kQ
± 12
± 10
± 10
Individual Output Short Circuit Current (Note 3)
1.0
%
12.5
12
V
V
± 30
± 45
rnA
Q
30
30
150
150
2.8
7.0
/LV IV
/LV IV
rnA
10
mA
Output Impedance
f = 20 Hz
80
Power Supply Rejection Ratio
Positive
Negative
Power Supply Current
VOUT = 0, RL = co
The following specification apply for -55 ° C -< TA -< + 125 ° C
Input Offset Voltage
Storage Temperature Coefficient
of Input Offset Voltage
10
Input Offset Current
/LV 1°C
250
Average Temperature Coefficient
of Input Offset Current
50
Input Bias Current
nA
pA/oC
-1000 nA
Large Signal Open
Loop Voltage Gain
RL = 2 kQ, VOUT = ± 10 V
15
V/mV
Output Voltage Range
RL = 2 kQ
± 10
V
4·167
•
JLA3303 • JLA3403
Electrical Characteristic
Vs = +5.0 V, Vs- = Gnd, TA = 25°C unless otherwise noted.
/LA3303
Characteristic
Min
Condition
Typ
Max
Unit
Input Offset Voltage
10
mV
Input Offset Current
75
nA
Input Bias Current
-500
nA
Large Signal Open
Loop Voltage Gain
RL = 2 krl
20
RL = 10 krl
RL = 10 krl, 5.0 V .:::s Vs .:::s 30 V
3.5
(V+)
-1.7
Power Supply Rejection Ratio
Output Voltage Range (Note 4)
150
Power Supply Current
2.5
Channel Separation
Electrical Characteristics
V/mV
200
f = 1 kHz to 20 kHz (Input Referenced)
7.0
-120
/LV IV
V pk-pk
V pk-pk
mA
dB
Vs = ± 15 V, TA = 25°C unless otherwise noted
/LA3403
Typ
Max
Input Offset Voltage
2.0
8.0
mV
Input Offset Current
30
50
nA
-200
-500
nA
Characteristic
Condition
Min
Input Bias Current
Input Impedance
f = 20 Hz
Input Common Mode Voltage
Range
Unit
0.3
1.0
Mrl
+13
to
-Vs
+13.5
to
-Vs
V
Common Mode Rejection
Ratio
Rs.:::s 10 krl
70
90
dB
Large Signal Open
Loop Voltage Gain
VOUT = ± 10 V, RL = 2 krl
20
200
V/mV
Power Bandwidth
Av = 1, RL = 2 krl,
VOUT = 20 V pk-pk
9.0
kHz
Slew Rate
Av= 1,RL= 10krl,
VOUT = 50 mV
Av= 1,VIN=-10Vto+10V
0.6
V I /LS
Rise Time
Av=
1,RL= 10krl,
VOUT = 50 mV
0.3
/LS
Fall Time
Av = 1, RL = 10 krl,
VOUT = 50 mV
0.3
/Ls
Overshoot
Av = 1, RL = 10 krl,
VOUT = 50 mV
5.0
%
Phase Margin
Av = 1, RL = 2 krl,
CL = 200 pF
60
Degree
Crossover Distortion at
f = 10 kHz
VIN = 30 mV pk-pk,
VOUT = 2 V pk-pk
Output Voltage Range
RL = 10 krl
RL = 2 krl
± 12
±10
± 13.5
± 13
Individual Output Short Circuit
Current
(Note 3)
± 10
±30
Output Impedance
f = 20 Hz
80
Power Supply Rejection Ratio
Positive
Negative
30
30
150
150
Power Supply Current
VOUT = 0, RL =
2.8
7.0
Small Signal Bandwidth
00
4·168
1.0
MHz
1.0
%
V
V
±45
mA
rl
/LV/V
/LV IV
mA
~A3303 • ~A3403
Electrical Characteristics
Vs =
± 15 V, -55°C
S TA
s
+125°C
/LA3403
Characteristic
Min
Condition
Typ
Input Offset Voltage
Average Temperature
Coefficient of Input
Offset Voltage
Max
Unit
10
mV
10
/LV 1°C
Input Offset Current
200
Average Temperature
Coefficient of Input
Offset Current
nA
pA/oC
50
-800
Input Bias Current
Large Signal Open
Loop Voltage Range
RL
Output Voltage Range
RL
Electrical Characteristics
Vs
= 2 kfl, VOUT = ±
= 2 kfl
= +5.0 V,
Vs-
10 V
nA
15
V/mV
± 10
V
= G, TA = 25°C unless otherwise noted.
/LA3403
Typ
Max
Unit
Input Offset Voltage
2.0
10
mV
Input Offset Current
30
50
nA
Input Bias Current
-200
-500
nA
Characteristic
Condition
Large Signal Open
Loop Voltage Gain
RL
Min
= 2 kfl
20
200
Power Supply Rejection Ratio
Output Voltage Range
(Note 4)
RL
RL
= 10 kfl
= kfl, 5.0 V S
Vs S 30 V
3.5
(V+)
-1.7
Power Supply Current
7.0
2.5
f = 1 kHz to 20 kHz (Input
Referenced)
Channel Separation
V/mV
/LV/V
V pk-pk
V pk-pk
150
Notes
3. Not to exceed maximum package power dissipation.
rnA
-120
dB
4. Output will sWing to ground.
Typical Performance Curves
Large Signal Open Loop
Voltage Gain as a
Function of Frequency
Output Voltage as a
Function of Frequency
Sine Wave Response
0
Av '" 100
(
"
'I' /' If
Vs """ ±15 V
RL = 10 kO
0
l
IV IV U IV \
r...
h
,,-..
..-..;
TA = 25°C
5
5
'\
o.
"r-
r.
NOTE Clas. AB output stage produces
-201·"0,ua-t'0;-ll''-:'~00l..lJL';-!;0:-tk..Ll'-;:'0~kl..J.J.';':;!;''~kJ..C,~.0 M
FREQUENCY -
dlstortlonles. sinew."e
50 "s/DIV
Hz
10 k
FREOUENCY -
4·169
100 k
Hz
10M
•
JLA3303 • JLA3403
Typical Performance Curves (Cont.)
Output Swing as a
Function of
Supply Voltage
Input Bias Current as a
Function of
Supply Voltage
Input Bias Current as a
Function of Temperature
40
t
~
=125°~_
400
J,
=
180
~'5~-
;f
300
I 30
w
"~
w 20
>
~
-
200
~o
IL
10
100
/
:J
"
r--.....,
/
o
00
2.0 4.0 60 80
10
12
14
16
V+ AND VPOWER SUPPLY VOLTAGES -
18
20
o
-75 -55 -35 -15 50
25
45
65
15°0
85 105 125
20 40 60 80
10
12
14
16
V t AND y._,
POWER SUPPLY VOLTAGES -
TEMPERATURE _ °C
V
18
20
V
Typical Applications
Multiple Feedback Bandpass Filter
Wein Bridge Oscillator
50 kll
r-----~~~----_.---VOUT
~~~~--e-R~3
R1
C2
10 kll
VREF
1
2
C
-v+
R
R
fo '= center frequency
BW = Bandwidth
R in kfl
C '" I'F
fo
0= BW
1
fo
<
C1 = C2 =
= 2".RC
10
o
=
for fo
1 kHz
R = 16 kfl
C = 0.011'F
Comparator With Hysteresis
"3
HYSTERESIS
R2
R1 = R2 = 1 }
R8 = 90 2 - 1
Use scaling factors," these expressions.
VOHEffL
VOUT VOUT
I
VOL
VINL I V,NH
R1
-"""...,...,.----t
Y,N ----------4
VREF
If source impedance is high or varies, filter may be preceded with
voltage follower buffer to stabilize filter parameters.
Design example:
given: 0 = 5, fo = 1 kHz
Let R 1 = R2 = 10 kfl
then R3 = 9(5)2 - 10
R3 = 215 kfl
C =
C
5
3' =
I
VREF
R1
VINL = R1
1.6 nF
+
R2 (VOL - VREF)
R1
VINH = R1
H
4-170
=
+ R2
(VOH - VREF)
R1
R1
+ R2
(VOH - VOL)
+
VREF
+ VREF
~A3303 • ~A3403
Typical Applications (Cont.)
High Impedance Differential Amplifier
AC Coupled Inverting Amplifer
RS
Rt
100 kll
VI
R2
Vour
Co
Rl
R2
100 kll
R3
V+ -I/V"I"'-~
Cl
+
R4
10"F
R
I
RS
V2
R7
VOUT = C(1
R2
As
+ a + b)(V2
RI
AV
=Ri"
AV
= 10 (as shown)
•
Voltage Reference
- VI)
R6
== R7 lor best CMRR
V+
Rl = R4
R2 = R5
R2
10 kll
VOUT
Gain =
R6
As
(
1
2Rl )
+ R3
= C (1 + a + b)
Rl
10 kll
AC Coupled Non-Inverting Amplifier
Rl
100 kll
R2
1 Mll
Rl
VOUT
=
VOUT
="2 VCC
Rl
+ R2
(V+
=""""2
as shown
)
1
Ground Referencing a Differential Input Signal
Rl
1 Mll
RS
100 kll
Your
R2
VA
1 M!l
R3
Av
= 11
1 Mll
(as shown)
4·171
JLA3303 • JLA3403
Typical Applications (ConI.)
Voltage Controlled Oscillator
0.05 ~F
R1
100 k!!
51 k!!
10k!!
OUTPUT 1
R2
50 k!!
~
OUTPUT 2
10 kll
Function Generator
VAEF
=
1
2
TRIANGLE WAVE
OUTPUT
v+
R2
SQUARE WAVE
300 kll
OUTPUT
VREF
R
100 kll
' - - -......-VREF
Rl + R2
f = 4CRfR 1
if
R2Rl
R3 = R2 + R 1
Pulse Generator
Rl
1N914
VOUT
R2
150 kn
R3
100 kll
R5
+
11 n
L.J L-
100 kll...J
o
'W,de Control Voltage Range.
OVDC ~ Vc ~ 2 (V+ - 1.5 VDC)
4·172
JLA3303 • JLA3403
Typical Applications (Cont.)
Bi-Quad Filter
R
R
C
Cl
VIN
c
R2
100 kll
100 kll
--f ......_..JVv.,-~
100 kll
BANDPASS
OUTPUT
VREF
VREF
VREF
R3
Rl
R2
Cl
f---NOTCH OUTPUT
VREF
•
BW
0=
fa"
where
TBP = Center Frequency Gain
TN =Bandpass Notch Gain
I
'0 = 2.-RC
RI = OR
R1
R2 = TBP
R3 = TNR2
C1 = 10 C
Example'
= 1000 Hz
BW = 100 Hz
'0
TBP = 1
TN = I
R = 160 kll
RI = 1.6 Mil
R2=1.6MU
R3= 1.6 Mil
C = 0.001 JlF
4·173
ILA4136
Quad Operational
Amplifiers
FAIRCHILO
A Schlumberger Company
Linear Products
Connection Diagram
14-Pin DIP
Description
The ~A4136 Monolithic Quad Operational Amplifiers
consists of four independent high gain, internal
frequency compensated operational amplifiers. The
specifically designed low noise input transistors allow
the ~A4136 to be used in low noise signal processing
applications such as audio preamplifiers and signal
conditioners. They are constructed using the Fairchild
Planar Epitaxial process. The simplified output stage
completely eliminates crossover distortion under any
load conditions, has large source and sink capacity,
and is short circuit protected. A novel current source
stabilizes output parameters over a wide power supply
voltage range.
-IN A,.. ---'_---,
+IN A
UNITY GAIN BANDWIDTH 3 MHz
CONTINUOUS SHORT CIRCUIT PROTECTION
NO FREQUENCY COMPENSATION REQUIRED
NO LATCH-UP
LARGE COMMON MODE AND DIFFERENTIAL
VOLTAGE RANGES
• ~A741 OPERATIONAL AMPLIFIER
TYPE PERFORMANCE
• PARAMETER TRACKING OVER
TEMPERATURE RANGE
• GAIN AND PHASE MATCH
BETWEEN AMPLIFIERS
OUT A
OUT D
OUT B
v+
+IN B
OUTC
-IN B
+IN C
v-
-IN C
•
•
•
•
•
(Top View)
Order Information
Type
Package
~A4136
Ceramic DIP
~A4136C
Ceramic DIP
~A4136C
Molded DIP
Code
6A
6A
9A
Part No.
~A4136DM
~A4136DC
~A4136PC
Equivalent Circuit (114 of circuit shown)
11
v,~------~~----------~--~~--------------~------~~--,
Rl
87 k
OS~----------+-~~=---------------+-~~~
+-_____-------['
all
R6
50
INVERTING
INPUT
R8
100
3,4,10,12 OUTPUT
R4
50 k
NONINVERTING
INPUT
R9
68 k
R2
S k
R3
5 k
RS
50 k
~~--~--~----~------~--------------~----~------~----~--~
4-174
J.LA4136
Pin Temperature
Molded Package (10 s)
Ceramic Package (60 s)
Absolute Maximum Ratings
Supply Voltage
±22 V
I£A4136
I£A4136C
± 18 V
Differential Input Voltage (Note 1) ±30 V
Input Voltage (Note 1)
± 15 V
Internal Power Dissipation
(Note 2)
670mW
Output Short Circuit Duration
(Note 3)
Indefinite
Operating Temperature Range
-55°C to +125°C
1£A4136
I£A4136C
O°C to +70°C
Storage Temperature range
Molded Package
-55°C to +125°C
Ceramic Package
-65°C to +150°C
Electrical Characteristics
TA
Notes
1. For supply voltage less than ± 15 V, the absolute maximum
Input voltage IS equal to the supply voltage
2 Rating applies to ambient temperature up to 7D·e Above
T A = 7D·e, derate linearly at 8 3 mW I·e
3 Short CircUit may be to ground, one amplifier only
Ise = 45 rnA (TYPical)
= 25°C , Vs = +- 15 V unless otherwise specified
I£A4136
Characteristic
Condition
Input Offset Voltage
Rs.::5 10 kf!
Min
Input Offset Current
Input Bias Current
Input Resistance
Large Signal Voltage Gain
Output Voltage Swing
=±
10 V
Transient Response
(Unity Gain)
Overshoot
Unity Gain Bandwidth
Unit
5.0
0.5
6.0
mV
5.0
40
200
500
5.0
40
5.0
200
500
nA
nA
0.3
20 k
Mf!
300 k
±12
± 14
V
RL ~ 2 kf!
±10
± 12
± 13
±14
± 10
± 12
±13
±14
V
V
RS.::5 10 kf!
70
90
70
90
dB
RS.::5 10 kf!
Channel Separation
(Open Loop)
100)
(Gain
F
30
150
30
150
I£V IV
210
340
210
340
mW
= 2 kf!,
0.13
0.13
I£S
=
= 2 kf!,
5.0
5.0
%
3.0
1.5
3.0
1.0
VII's
105
105
dB
105
105
dB
VIN
20 mV, RL
CL.::5 100 pF
RL
"
=
VIN
20 mV, RL
CL.::5 100 pF
Slew Rate (Unity Gain)
=
Max
0.5
5.0
50 k 300 k
± 12 ± 14
Power Consumption
Transient Response
(Unity Gain)
Risetime
Max
0.3
RL ~ 2 kf!, VOUT
RL ~ 10 kf!
Input Voltage Range
Common Mode
Rejection Ratio
Supply Voltage
Rejection Ratio
I£A4136C
Typ
Min
Typ
~
2 kf!
= 10 kHz, RS = 1 kf!
f = 10 kHz, RS = 1 kf!
MHz
The following specifications apply for -55°C .::5 TA.::5 +125°C for I£A4136: O°C .::5 TA.::5 +70°C for I£A4136C.
Input Offset Voltage
RS.::5 10 kf!
Input Offset Current
Input Bias Current
Large Signal Voltage Gain
Output Voltage Swing
Power Consumption
RL ~ 2 kf!, VOUT
RL ~ 2 kf!
Vs
± 15 V
=±
10 V
=
TA = High
TA = Low
4·175
6.0
7.5
mV
500
1500
300
800
nA
nA
25 k
15 k
±12
± 10
V
180
300
180
300
mW
240
400
240
400
mW
•
~A4136
Typical Performance Curves
Input Bias Current as a
Function of
Ambient Temperature
..
,
!-Ys
1
Input Offset Current as a
Function of
Ambient Temperature
•
1 J
Vs =
i15
Ls
v
Common Mode Range as a
Function of
Supply Voltage
r--
80
I
!<
i 6•
i3
..
40
!
•
;
~
•
•
-
•
r--
•
•
10
20
30
40
50
60
...... ----
•
70
10
TEMPERATURE _ GC
~
w
"
~
g
•
•
•
•
•
•
Ys
"'
•
600
"'I'\.
4
3
~400
'I'\.
'I'\.
~
"'
1 k
50
10
70
SUPPLY VOLTAGE -
°C
=1+ 15 V
24
~
I 220
10 k
FREOUENCY -
100 k
1 M
10 M
i
•
t--
f5
~
10
Hz
Typical Output Voltage as a
Function of
Supply Voltage
20
30
40
SO
TEMPERATURE _ °C
80
• T, =12.J C I
26
•
Ys '" ±15 v
V
4
2
.
• /
•,
SUPPLY VOLTAGE -
±V
r-- I--
200
•
18
180
20
30
40
SO
TEMPERATURE _ °C
i"co
...
:>
...
:>
.
."
...
".
0
~
II
,.
4·176
70
TA = 25°C
3& Vs = ±1SV
RL = 2 kn
32
2.
.••
16
1•
1\
0
LOAD RESISTANCE -
80
4.
>
I
•
•
~
t---.
10
t-
I---'
Z
!;
o
Y
Output Voltage Swing as a
Function of Frequency
/
2
~
.......
70
Output Voltage Swing
as a Function of
Load Resistance
>
"
8
It "" 21r.{J
1+15
o Vs =
z
o
~
... •
±V
Power Consumption as a
Function of
Ambient Temperature
•
•
-2
100
40
z
I'\.
10
30
Open Loop Gain as a
Function of Temperature
BOO
III •
z
20
TEMPERATURE _
Open Loop Voltage Gain as a
Function of Frequency
,.•
,..1-
I--
.
,
kn
~
1'1
•
•
100
I'-1•
1••
FREQUENCY -
100 •
HI
1 M
JLA4136
Typical Performance Curves (Cont.)
Quiesent Current as a
Function of
Supply Voltage
10
TA
1
8
J
..-
~
~
B
!ii
o"
2
12
SUPPLY VOLTAGE -
15
"0
r-
•
18
."...... -.
II
0
-025
10% RISE
TIME
025
:tv
050
TA
Vs
AL
CL
075
10
10
~
1 10~~-+~~+-~~-+H+~++~
I
30
.0
•
140
,. jW-.J.
0
'II
I 10o
Z
o
~
r-.~
LIJ l•.l
Vs=±15V
so
.
~
::: 80
w
~ 10
!l! •0
l!
oz
"
10
100
,.
FREQUENCY -
10.
07
100
10
Hz
1k
10.
100 k
Hz
06 rAv = 40 dB
Distortion as a Function of
Frequency VOUT = 1 Vrms
~
OS
'"I
f -= 1 kHz
Rs = 1 kU
Ys=±30Y
AIAA COMPENSATION
o.
Z
0
~
0:
OS
0
0
in o.
o.
Ci
I
"
..
iii 03
0
C
J:
O.
...:J0
...
01
./
J
00~~,0~.~0~3~0:.~0~stO~.~0:7tO~870-.~0~,0
OUTPUT VOLTAGE
"iii0
'"
:iJ:
...:J
...0
03
02
1\
01
1..1
o
10
100
10.
1k
FREQUENCY -
4-177
Hz
10
100
"
FREQUENCY -
07
Ys = ±1S v
RL ,. 2 k
'"I
z
10
FREQUENCY -
=
20
0
100 k
Total Harmonic Distortion as a
Function of
Output Voltage f
1 kHz
0:
20
TIME -~.
Channel Separation
~
Q
l-
-10
100 1"""T-m-r-rr-n-,-r-rrT"""T-rrrr.,...,..,.,,,.....,
~100~+H-+~~+-~~-+H+~++~
I
if
-4
1\
•
-8
125
Input Noise Current as a
Function of Frequency
I~
··• ,
• -
./
-lI
== 25~C
== -15 V
= 2 k!l
= 100 pF
I
I
I
I
~s
TIME -
Input Noise Voltage as a
Function of Frequency
II
I
~
I
8
•
0
...!1!
~--
~
I
2
±15 V
.-
w
-j .0%
16
I
0:
i
Ys
4
0
I
"
10
TA = 25°C
25°C
8
~
0:
i"
Voltage Follower Large Signal
Pulse Response
Transient Response
100 k
10 •
Hz
100.
f.LA4136
Typical Applications
400 Hz Lowpass Butterworth Active Filter
10 k
20 k
620
n
INPUT'--~--~r--4-~AA~~--------------~AA__------------------~------------JV~--------~~--OUTPUT
0.331'F
1 k
1 k
-I
I
12
I
I
I
II'A41 36
I
_______
-----t--
+ _____
o 331'F
O.331'F
1 62 k
1.62 k
1 k
1k
o 331'F
Differential Input Instrumentation Amplifier with
High Common Mode Rejection
R2'
10 k
R6t
100 k
0.1%
1%
OUTPUT
Rl
~
R4
R2 ~ R5
R6 ~ R7
t 'MATCHING DETERMINES CMRR
R3
10 k
1%
A
V
R4
45 k
1%
R5'
10 k
0.1%
R7t
100 k
0.1%
4-178
~ R6 il ~
R2 \
1...B.l)
R3
13.2 k
~A4136
Typical Applications (Cont.)
Analog Multiplier / Divider
-15 v
10 k
10 k
i
10 k
D.
LM103
Q,.
10 k
E1
10 k
2
6
EOUT ~
E1 E2
E3
-=-
1 k
6
10 k
-=-
10 k
-=Q2'
10 k
10 k
E3
E2
1 k
6
02
IN457
10 k
10 k
-=-
-=-
-=-
-=1 kHz Bandpass Active Filter
390 k
v+
O.OlI1F
120 k
V+
V,N
VOUT
390 k
39 k
O.OlI1F
620
(1
-=-
-=620 k
-=-
r
100 k
100 k
1Ol1F
-=-
-=V+
4·179
•
/-LA4136
Typical Applications (Cant.)
Full-Wave Rectifier and Averaging Filter
20 k
2,0%k
2.5 k
DC
1%
r--------------~~----------------JVV'v-~~C~A~L-.-OUTPUT
4.7 flF
INP~~-!jHI-+~-""''v-----.JVI/'v----...,
4.7 flF
2,0%k
4.7 flF
'0 k
1%
D2
FD 6666
5.' k
'1) k
Notch Filter Using the !J.A4136 as a Gyrator
Multiple Aperture Window Discriminator
R2
30 k
V4-1---~
INPUT
OUTPUT
,..------,
TRIM R. SUCH THAT
R'
R3
-=-R2
2 R4
C,
V3
0,
7.5 k
R4
C2
R4
' flF
V,
VIN
V,
Notch Frequency as a Function of C1
03
'0 k
VIN <
, k
v,
I
I
'00
'0
00001
"
0001
00'
0'
, 0
C1 - CAPACITOR - IJF
4·180
V,
<
V3
FAIRCHILO
A SchlLimberger Oompany
.
.'
,
Voltage Regutatol'$
.Hybrid Voliage Regulators
Operational Amplifler~
Comparators
Data Acquisition
.Telecommunications
' .
.'
Special Functions •
I
HI Rei Processing·
Package Outlines
F.alrchitd Sales. Offices. "\. .
/'
,
~
5-2
jlA710
High-Speed
Differential Comparator
FAIRCHILO
A Schlumberger Company
Linear Products
Description
The J.lA 710 is a Differential Voltage Comparator
intended for applications requiring high accuracy and
fast response times. It is constructed on a single
silicon chip using the Fairchild Planar epitaxial
process. The device is useful as a variable threshold
Schmitt trigger, a pulse-height discriminator, a voltage
comparator in high-speed a / d converters, a memory
sense amplifier or a high noise immunity line receiver.
The output of the comparator is compatible with all
integrated logic forms.
•
Connection Diagram
8-Pin Metal Package
v+
5 mV MAXIMUM OFFSET VOLTAGE
v-
• 5 J.lA MAXIMUM OFFSET CURRENT
•
•
1000 MINIMUM VOLTAGE GAIN
20 J.lV/oC MAXIMUM OFFSET VOLTAGE DRIFT
(Top View)
Pin 4 connected to case
Absolute Maximum Ratings
Positive Supply Voltage
Negative Supply Voltage
Peak Output Current
Differential Input Voltage
Input Voltage
Internal Power Dissipation
(Note 1)
Metal Package
Molded DIP
Storage Temperature Range
Metal Package, Ceramic DIP
Molded DIP
Operating Temperature Range
Military (J.lA710)
Commercial (J.lA71OC)
Pin Temperature (Soldering)
Metal Package, Ceramic DIP
(60 s)
Molded DIP (10 s)
+14.0 V
-7.0 V
10 rnA
±5.0 V
±7.0 V
Order Information
Type
Package
J.lA710
Metal
J.lA710C
Metal
Part No_
J.lA71OHM
J.lA710HC
Code
5W
5W
Connection Diagram
14-Pin DIP
500 mW
670 mW
-65°C to +150°C
-55°C to +125°C
-55°C to +125°C
O°C to +70°C
300°C
260°C
NC
NC
GND
NC
+IN
NC
-IN
v+
NC
NC
v-
OUT
NC
NC
(Top View)
Order Information
Type
Package
J.lA710
Ceramic DIP
J.lA710C
Ceramic DIP
J.lA710C
Molded DIP
Notes
1 Rating applies to ambient temperatures up to 70°C Above
70°C ambient derate linearly at 6.3 mW / °C for metal package,
83 mW/oC for DIPs
5-3
Code
6A
6A
9A
Part No_
IlA710DM
J.lA71ODC
IlA710PC
•
p,A710
Equivalent Circuit
r--------------1~----~------~._---V+
R4
2.8 kD
R3
1.1 kD
05
R2
500 D
R1
500 D
02
6.2 V
OUTPUT
NONINVERTING
INPUT
---+---------£
02
01
6.2 V
INVERTING
INPUT
GROUND
R8
100 !l
R7
68 !l
~------------~-----v-
5-4
f,LA710
!LA710
Electrical Characteristics
TA = 25°C, V+ = 12.0 V, V- = -6.0 V unless otherwise specified.
Typ
Max
Unit
0.6
2.0
mV
Input Offset Current
0.75
3.0
!LA
Input Bias Current
13
20
!LA
Characteristic
Input Offset Voltage
Condition (Note 2)
RS
~
Min
200 Q
Voltage Gain
1250
Output Resistance
Output Sink Current
~VIN 2:
2.0
5 mV, VOUT = 0
Response Time (Note 3)
1700
200
Q
2.5
mA
40
ns
The following specifications apply for -55°C -< TA -< +125°C
RS ~ 200 Q
Input Offset Voltage
3.0
mV
RS = 50 Q, TA = 25°C to TA = +125°C
RA = 50 Q. TA = 25°Cto TA = -55°C
3.5
2.7
10
10
!LV 1°C
!LV 1°C
0.25
1.8
3.0
7.0
!LA
!LA
5.0
15
25
75
nA/oC
27
45
!LA
Input Voltage Range
= +125°C
= -55°C
TA = 25°C to TA = +125°C
TA = 25°C to TA -55°C
TA = -55°C
V- = -7.0V
Common Mode Rejection Ratio
Rs
Average Temperature Coefficient
of Input Offset Voltage
Input Offset Current
Average Temperature Coefficient
of Input Offset Current
Input Bias Current
TA
TA
~
200 Q
±5.0
80
V
100
dB
±5.0
Differential Input Voltage Range
Voltage Gain
nA/oC
V
1000
3.2
4.0
V
-0.5
0
V
0.5
1.0
1.7
2.3
5 mV, 0
Output LOW Voltage
~VIN 2:
5 mV
Output Sink Current
TA
TA
Positive Supply Current
VOUT ~ 0
5.2
9.0
mA
Negative Supply Current
VOUT
= GND, Inverting Input = +5 mV
VOUT = GND, Inverting Input = + 10 mV
4.6
7.0
mA
90
150
mW
lOUT
~
-1.0
~VIN 2:
Power Consumption
~
2.5
Output HIGH Voltage
5.0 mA
= +125°C, ~VIN 2: 5 mV, VOUT = 0
= -55°C, ~VIN 2: 5mV, VOUT = 0
mA
mA
Notes
2 The Input offset voltage and input offset current are specIfied
for a logic threshold voltage as follows For 710, 1.8 V at
-55'C, 1.4 V at +25'C, 10 V at +125'C. For 710C. 1.5 V at
O'C, 14 V at +25'C, and 1.2 V at +70'C.
3. The response time specified IS for a 100 mV input step with
5 mV overdrive.
5·5
J,LA710
JLA710C
Electrical Characteristics
TA
= 25°C, V+ = 12.0 V, V- = -6.0 V unless otherwise specified
Characteristic
Condition (Note 2)
Input Offset Voltage
RA:5 200 Q
Typ
Max
Unit
1.6
5.0
mV
Input Offset Current
1.8
5.0
JLA
Input Bias Current
16
25
JLA
Min
Voltage Gain
1000
Output Resistance
~V'N 2: 5 mV, VOUT
Output Sink Current
1.6
= 0
Response Time (Note 2)
1500
200
Q
2.5
mA
40
ns
The following specifications apply for 0 ° C --< TA --< + 70 ° C
Input Offset Voltage
RS:5 200 Q
Average Temperature Coefficient
of Input Offset Voltage
RS
= 50 Q, TA = O°C to TA = +70°C
6.5
mV
5.0
20
JLV/oC
7.5
JLA
15
24
50
100
nA/oC
nA/oC
25
40
JLA
Input Offset Current
Input Voltage Range
= 25°C to TA = +70°C
= 25°C to TA = O·C
TA = O°C
V = -7.0 V
±5.0
Common Mode Rejection Ratio
RA:5 200 Q
70
Average Temperature Coefficient
of Input Offset Current
Input Bias Current
TA
TA
98
Differential Input Voltage Range
±5.0
Voltage Gain
800
~V'N
Output HIGH Voltage
dB
V
2.5
3.2
4.0
V
-1.0
-0.5
0
V
VOUT:5 0
5.2
9.0
mA
= GND, Inverting Input = +5 mV
VOUT = GND, Inverting Input = + 10 mV
4.6
7.0
mA
90
150
mW
2: 5 mV, 0 :5 lOUT :5 5.0 mA
Output LOW Voltage
~V'N 2: 5 mV
Output Sink Current
~VIN
Positive Supply Current
Negative Supply Current
2: 5 mV, VOUT
=0
0.5
mA
VOUT
Power Comsumption
V
Notes on preceding page
Typical Performance Curves for JLA710
Voltage Transfer Characteristic
0
1800
c---~,-I12VI
V
-80 V
V
0
T,
TA
//1
=
125°C
1600
50
30
"
2000
L
\
1500
10
30
50
/"
/"
i--
-':;;("
J,~
~_<;o"
~
.,.- V ;!;/"'
.,.-V
1000/
\
,/
500
1300
10
INPUT VOLTAGE-mY
._ V
'\
\
.,.--
I-- T~ ~ 2'I,C
2500
1400
0
3000
=
1500
VI
0
Voltage Gain as a
Function of
Supply Voltages
_J+
~ ~2 v 1._
v- -60 V
TA "" 25°C
III
-
i'-
1700
!.
'II V~
'I';
Il
55°C
0
0
Voltage Gain as a
Function of
Ambient Temperature
60
-20
20
60
TEMPERATURE-OC
5·6
100
140
10
11
12
13
POSITIVE SUPPLY VOLTAGE-Y
14
JLA710
Typical Performance Curves for
Input Bias Current as a
Function of
Ambient Temperature
50
(Cont.)
Input Offset Current as a
Function of
Ambient Temperature
2'
~~ ;~~>
Common Mode Rejection
Ratio as a Function of
Ambient Temperature
104
t,
l2v.I._
v- "- -60 V
1\
1
40
'"i
~A710
I
30
"
<.>
~
20
"'
10
I'
."
:::o
-
...............
~
60
20
100
60
20
~
~
5
90
~
8
85
......
,/
~
il!
I"--
2
~
5
80
60
20
so
20
•
•6'
~
40
"'
30
~
o
~
"~
"o
20
10
0
2Jmt
I I
10mV
1111
2. ~v
I
V
II/V
~
5QiV
>
100
~~
50
!!:~
g
vi"" +12 V
V-=-6DV
T,=rl
c
g
'E
~I
..""'
"
!~
'\ iY'
r-~OmV
~10
60
TIME-nl
80
100
120
~
.
NEGATIVE OUTPUT LEVEL
1
~
2.
20
so
100
140
TEMPERATURE-OC
Common Mode Pulse RellPonse
I'-
10'
V+"'+12V
50
y- == -60 V
Tr=rl
>
1
40
10
I- r!:E~THAES"OLO
I
r- I20mV
0
20
~
""'"
r:::
10
"~
"0
-10
.. f
140
Response Time for
Various Input Overdrives
> 4.
~ 3.
2QmY
.\ r-~ 2.
50mV
I
,~
20
•
100
60
140
o"
TEMPERATURE-OC
Response Time for
Various Input Overdrives
~
10
20
100
~~SITivEJ.
WJ-~+ ~1'2VI._
~EVEL v ~-60V
.
•
-60 V
"
20
so
Output Voltage Levels as a
Function of
Ambient Temperature
t-.....
15
140
100
2.
20
~
TEMPERATURE-OC
.........
TEMPERATUAE-OC
>
I
• 6.
4
I
•
"-
o
140
J,~ \2V I_
25
"~
.........
5
r-..
g
,. ..
100
v- -
"<.>
'"
~..
3
I
~
~
5
V-=-6DY
I_
r-.....
z
6'
20
I
r-....
..
Output Sink Current as a
Function of
Ambient Temperature
J,= \2v l _
.
......
TEMPERATURE-OC
Power Consumption as a
Function of
Ambient Temperature
~
I
100
<.>
20
TEMPERATUAE-OC
100
"- I.......
.........
•so
~
\2v l
V
-70Y
-SOV:-:oVCM_ TSOV_
~
6
i!:o '
.........
14.
102
§
"'
I--
o
'\
10
~
r-..
~
\
<.>
"'"
o
i
I
~
~
ffi
il!
L
ill
20
4{)
60
TIME-ns
5-7
80
100
C
120
40
so
TIME-n.
120
16.
•
f,lA710
Typical Performance Curves for ILA710C
Voltage Transfer Characteristic
1700
0
-
I--
"",f.!I
TA! ",Ie
0
1600
'/
0
I
0
TA= 70 0
- 50
"
~g
1500
1400
r=i
10
60
i-
30
50
~
30
i3
....
'"~
0
30
40
50
1'-.
~
"-
l!;
i"-....
o
20
O~
15
V~"
12~._
V-=-60V
..
I'
0
10
20
30
40
50
60
70
10
20
40
-
~
w
g
'5
-- ---
-
'"
Z
~
80
30
0
10
20
30
40
50
TEMPERATURE-DC
60
70
60
70
vl=12~._
-I--
'.0
r--.
~f---+--+-+-4--t--f---+
t--------- POSlTliE OUYUT LiVEL
LOGI~ THR~SHOLJ VOLTAGE- t---
10
t---t-----+-~f__-~--+-~
94f--+--+-+-+--+--f----1
NEGATIVE OUTPUT LEVEL
8
75
50
V-~-60V
f---+-+-.j--- -5.0 V~VCM:S +50 V_
'"oz 9,r-r-
§
40
Output Voltage Levels as a
Function of
Ambient Temperature
:t
90
30
TEMPERATURE_oC
-
Q 100
95
I--
.......
Output Sink Current as a
Function of
Ambient Temperature
"iilz
'"~
2
~
TEMPERATURE_oC
z
0
......,
i?
70
--
25
(l
...0
0
U
V-=-60V
~
it
Power Consumption as a
Function of
Ambient Temperature
ii:
vl=12~_
30
I
'"
14
13
35
vl=12~._
-60 V
TEMPERATURE-oC
100
12
11
Common Mode Rejection Ratio
as a Function of
Ambient Temperature
!z
~
60
I
POSITIVE SUPPLY VOLTAGE-V
~
10
,..- e-
V
o/
10
~
30
20
120
40 0
4
u
---
r-- t--
g
---
,..-l -
V
v- =
''""
10
E
I
i'--
£.'
/~
...
/" /T
~/'l
....-
800 /
20
_
::>
0
1600
010203040506070
0
;0
r-...
I'
i?
l!;
.........
Input Offset Current as a
Function of
Ambient Temperature
vl=12~
,
"w
~
V--
TEMPERATURE_oC
V--=-60V
Jz
2000
1200
50
Input Bias Current as a
Function of
Ambient Temperature
"
Z
;;
............
T~ = ,,!c
'40 0
= 12 V
INPUT VOLTAGE-mV
~
V--~-60V
1300
v+
- 1.0
30
e
I
A
-1 0
z
;;
,",-
VII
2800
V~=12~_
--
TA - DOC
0
Voltage Gain as a
Function of
Supply Voltages
Voltage Gain as a
Function of
Ambient Temperature
92 0:----f.1O:--:'!::0---::3'="0---:''':--'*'0---:''=0---:!70
TEMPERATURE_oC
5-8
I
-1 0
10
20
30
40
50
TEMPERATURE_oC
60
70
~A710
Typical Performance Curves for jlA710C (Cont.)
Response Time for
Various Input Overdrives
>",1
~
...g
~
o
4.
3.
,.
20
2J m~
I I
10mV
Response Time for
Various Input Overdrives
>
1
'II
~
I11I
V1
/~ I'-~. ~VrI
"-
5°iY
r-
:;
Do
!~
3.
~ 2.
g ,.
...
"...
" ,. r- I
~
vl"'+12v
100
v-
-= -60 V
Tj =I25T
I I
50
g
20
40
60
TIME-ns
80
100
>
E
... 1
"'"
~"
!S
""
'\
I\Jo
..
,
V+"'+12Y
y- '" -60 V
>
20
40
60
TIME-ns
80
y- ~ -8 V
A =25G C -
5On~
_
20mV
5.
r
.--f('>--
SOmY
I
t=I+12~_
•
•
2DmV
0
120
Common Mode Pulse Response
I
r-.
'i
r-,10mV
0
-10
I
... 1
"",
CJ
4.
rrl
100
C
120
-
-IYCM
-
-
f--
-
.
•
•
I
4.
..
120
160
TIME-n.
•
5-9
J,tA711
FAIRCHIL.D
Dual High-Speed
Differential Comparator
A Sehlumberger Company
Linear Products
Connection Diagram
1O-Pln Metal Package.
Description
The JLA711 is a Dual, Differential Voltage Comparator
featuring high accuracy, fast response times, large
input voltage range, low power consumption and
compatibility with practically all integrated logic
forms. When used as a sense amplifier, the threshold
voltage can be adjusted over a wide range, almost
independent of the integrated circuit characteristics.
Independent strobing of each comparator channel is
provided, and pulse stretching on the output is easily
accomplished. Other applications of the dual
comparator include a window discriminator in pulse
height detectors and a double-ended limit detector
for automatic Go I No-Go test equipment. The JLA711,
which is similar to the JLA710 differential comparator,
is constructed using the Fairchild Planar
epitaxial process.
v+
v(Top View)
Pin 5 connected to case
• FAST RESPONSE TIME-40 ns TYPICAL
• 5 mV MAXIMUM OFFSET VOLTAGE
• 10 JLA MAXIMUM OFFSET CURRENT
• INDEPENDENT COMPARATOR STROBING
Order Information
Type
Package
JLA 711
Metal
JLA711C
Metal
Code
5X
5X
Part No.
JLA711HM
JLA711HC
Absolute Maximum Ratings
Positive Supply Voltage
Negative Supply Voltage
Peak Output Current
Differential Input Voltage
Input Voltage
Strobe Voltage
Internal Power Dissipation
(Note 1)
Metal
DIP
Operating Temperature Range
Military (JLA711)
Commercial (JLA711C)
Storage Temperature Range
Pin Temperature
Metal Package, Ceramic DIP
Molded DIP (Soldering, 10 s)
Connection Diagram
14·Pin DIP
+14 V
-7.0 V
50 rnA
±5.0 V
±7.0V
o to +S.O V
NC
-IN A
+INA
500mW
S70mW
v-
-55°C to +125°C
O°C to +70°C
-S5°C to +150°C
+IN B
NC
(Top View)
Order Information
Type
Package
JLA 711
Ceramic DIP
JLA711C
Ceramic DIP
JLA711 C
Molded DIP
Note.
1. Ratong applies to ambient temperatures up to 70·e. Above
70·e ambient derate linearly at 6.3 mW I·e for the metal
package, 8.3 mW I·e for the DIP.
5·10
Code
SA
SA
9A
Part No.
JLA711DM
JLA711DC
JLA711PC
JLA711
Equivalent Circuit
STROBEl
STROBE 2
~----'-----------------~-----+-----9-----;----~~----------------~----~----V+
R4
4.3kll
R5
R15
4.3kll
R14
4.3kll
4.3kll
R2
R12
910ll
910ll
Rl
910ll
INVERTING
INPUT,
R13
910!!
01
013
NON-INVERTING
INPUT,
INVERTING
INPUT2
NON-INVERTING
INPUT2
Rl0
12011
R9
120!!
~----------------~~----------------------~---------------V-
5-11
•
p,A711
/LA711
Electrical Characteristics
TA
Characteristic
Input Offset Voltage
Input Offset Current
= 25°C, V+ = 12 V, V- = -6.0 V unless otherwise specified
Min
Condition
= +1.4 V, Rs:S.
VOUT = +1.4 V, Rs:S.
VOUT = +1.4 V
VOUT
200 Q, VCM
=0
200 Q
Input Bias Current
Voltage Gain
750
Typ
Max
Unit
1.0
3.5
mV
1.0
5.0
mV
0.5
10.0
/LA
25
75
/LA
1500
Response Time (Note 2)
40
ns
Strobe Release Time
12
ns
Input Voltage Range
V-
= -7.0 V
Differential Input Voltage Range
±5.0
V
±5.0
V
Output Resistance
Output HIGH Voltage
VIN 2: 10 mV
Loaded Output HIGH Voltage
VIN 2: 10 mV, 10
Output LOW Voltage
Strobed Output Level
4.5
= 5 mA
2.5
3.5
VIN 2: 10 mV
-1.0
-0.5
VSTROBE :S. 0.3 V
-1.0
Output Sink Current
VIN 2: 10 mV, VOUT 2: 0
Strobe Current
VSTROBE
= 100 mV
1.2
Positive Supply Current
VOUT = Ground,lnverting Input
8.6
Negative Supply Current
Q
200
0.5
= +5 mV
VOUT = Ground, Inverting Input = +5 mV
5.0
V
0
V
0
V
V
0.8
mA
2.5
mA
mA
3.9
Power Consumption
130
mA
200
mW
The following specifications apply for -55°C :S. TA:S. +125°C
Rs:S. 200 Q, VCM = 0
4.5
mV
RS:S. 200 Q
6.0
mV
Input Offset Current (Note 3)
20
/LA
Input Bias Current
150
/LA
Input Offset Voltage (Note 3)
Temperature Coefficient of
Input Offset Voltage
5.0
Voltage Gain
500
Notes
2 The response time specified (see definitions) is for a 100 mV
step mput with 5 mV overdrive.
3. The Input offset voltage is specified for a logic threshold
as follows:
711. 1.8 V at -55°C. 1.4 V at +25°C. 1.0 V at +125°C711C: 15 Vat O°C. 1.4 V at +25°C. 1.2 V at +70°C
5·12
/LV/oC
J.LA711
~A711C
Electrical Characteristics
TA
= 25°C, V+ = 12 V, V- = -6.0 V unless otherwise specified
Characteristic
Condition
Input Offset Voltage
VOUT
Input Offset Current
Min
= +1.4 V, RS::5 200n, VCM = 0
VOUT = +1.4 V, Rs::5 200 n
VOUT = +1.4 V
Input Bias Current
700
Voltage Gain
Typ
Max
Unit
1.0
5.0
mV
1.0
7.5
mV
0.5
15
~A
25
100
~A
1500
Response Time (Note 2)
40
ns
Strobe Release Time
12
ns
Input Voltage Range
V-
= -7.0 V
±5.0
Differential Input Voltage Range
V
±5.0
Output Resistance
V
200
4.5
Output HIGH Voltage
VIN 2::: 10 mV
Loaded Output HIGH Voltage
VIN 2::: 10 mV, 10
Output LOW Voltage
Strobed Output Level
= 5 rnA
2.5
3.5
VIN 2::: 10 mV
-1.0
-0.5
VSTROBE ::5 0.3 V
-1.0
Output Sink Current
VIN 2::: 10 mV, VOUT 2::: 0
0.5
Strobe Current
VSTROBE
Positive Supply Current
VOUT Ground, Inverting Input
Negative Supply Current
= 100 mV
5.0
0
V
0
V
rnA
2.5
rnA
3.9
130
rnA
rnA
8.6
Power Consumption
V
V
0.8
1.2
= + 10 mV
VOUT Ground, Inverting Input = + 10 mV
n
230
mW
The following specifications apply for O°C ::5 TA::5 +70°C
=0
6.0
mV
10
mV
Input Offset Current (Note 3)
25
~A
Input Bias Current
150
~A
Input Offset Voltage (Note 3)
Rs ::5 200 n, VCM
Rs ::5 200 n
Temperature Coefficient of
Input Offset Voltage
5.0
Voltage Gain
500
Notes
2. The response time specified (see definitions) is for a 100 mV
step input with 5 mV overdrive.
3. The input offset voltage is specified for a logic threshold
as follows;
711; 1.8Vat-55°C, 1.4Vat+25°C, 1.0Vat+125°C711C; 1.5 V at O°C, 1.4 V at +25°C, 1.2 V at +70°C
5·13
~V/oC
•
J.LA711
Typical Performance Curves
Voltage Transfer
Characteristic /-LA 711
0
0
l
"
g~
...
40
1//
'/..
t-125°C,---
30
l
T, - -55 C
D
"r!g
1//,
,0
Ii
10
VI
TA
co
~25°C
~
!;
//1
o
1//
0
I
>
ilV
it
!;
o
=- +12 V
V-=-60Y
f/I
"J. ~ T'I +70 C
1
8.,
0
20
J.
fI
30
10
10
30
50
1600
0
1+12
TA--'25"C
1200
-60
10
10
30
30
"
"~
w
20
10mV
0
v,
g
''\
I"-
100
50
'/
V-+~+12V= -60Y
100
g
50
it
0
V
T'i'i'c,40
2Q
50
~ +25ol c
--------x=
'" ~
~
1600
,,"
/
1200
,....-
/" /
,...
i~
~
g
20
10
I
r~
-
1
I
I
~
r-,..
o-
.
20
w
1
0
-
1
1
1
1
40
g
, 0
"~
trr .
...
f-.-
-SOy
,.,~ 5~
J C.-i---r$?~~h~
:;. '%",
r/
'/
...
~
0
50
TA= 25°C,_
40
.0........ ,
~
I I
200
100
TIME-ns
1
300
400
500
Vou'
Strobe Release Time for
Various Input Overdrives
>
~+ ~12 ~
\
V-=-60~-·--0
I'\.
30
~
10
~
,
!
........ r--
"~
g
0
LLl-
/
" '0
o
I.........
20
V-=-6QV
TA = 25°C _
V
20
50mY
10
!;
5o :~
--..., '/ ~
~
60
20
20
100
50
TEMPERATURE _
5-14
0
C
140
20mV
I""
10
OmV
Jmv t-I
-1
0
160
l
~
\
30
120
~+-
~
'II
~
~
14
Input Bias Current as a
Function of
Ambient Temperature
~+c~12L
V-=-60V
I
50
120
y- =- -60 V
TA = 25°C
ICc
f-
1
13
12
11
1 100
TIME-ns
I I I I
40
80
Y+ "" +12 V
60
-'0
10
50n
_
i
g
I
1
E"
-
"~
1
60
TIME-ns
",,
E
/
2000
140
510m~
J
Output Pulse Stretching
With Capacitive Loading
400
-20
1
++ !IVr..
l
T,
,400
~
'\
1300
~
"~
2800
~
'\
" '\
20
~
'\
1400
$!
...
50
V-=-60~~
1500
30
~
Voltage Gain as a
Function of
Supply Voltages
~+
"
40
~
INPUT VOLTAGE-mY
Voltage Gain as a
Function of
Ambient Temperature
1700
50
~
a
u
10
INPUT VOLTAGE - mY
g
//.
-1 0
50
"w
"~
I
0
-1 0
Z
~
~
TA=O"C
30
Response Time for
Various Input Overdrives
>
I
f-- V+
~V
I
1
V-=-60Y
T,
50
I
~v+ ~+12V
>
Voltage Transfer
Characteristic /-LA 711 C
20
TIME-ns
,.
40
50
JLA711
Typical Performance Curves (Cont.)
Power Consumption as a
Function of
Ambient Temperature
140
L~'2L
y- '" -60Y
130
I-"'"
120
.
-
r---
I-"'"
20
20
..
'" f',.
100
140
5·15
it
Il A734
Precision Voltage
Comparator
FAIRCHILI:J
A Schlumberger Company
Linear Products
Connection Diagram
1o-Pln Metal Package
Description
The JA.A734 is a Pre'cision Voltage Comparator
constructed on a single silicon chip using the Fairchild
Planar epitaxial process. It is specifically designed for
high accuracy level sensing and measuring
applications. The JA.A734 is extremely useful for
analog-to-digital converters with 12-bit accuracies
and one mega-bit conversion rates. Maximum
resolution is obtained by high gain, low input offset
current, and low ,input offset voltage. Its superior
temperature stability can be improved by offset nulling
which further reduces offset voltage drift. Balanced or
unbalanced supply operation and standard TTL logic
cornpatibility enhance the JA.A734 versatility.
+IN
Ne
PULL-UP
RESISTOR
OFFSET
OUT
NULL
v(Top View)
•
•
•
•
•
•
•
CONSTANT INPUT IMPEDANCE OVER
DIFFERENTIAL INPUT RANGE
HIGH INPUT IMPEDANCE-55 MU
LOW DRIFT-3_5 JA.VI"C
HIGH GAIN-60 k
BALANCED OFFSET NULL CAPABILITY
WIDE SUPPLY VOLTAGE RANGE- ±5 V
to ± 18 V
TTL COMPATIBLE
Order Information
Type
Package
JA.A734
Metal
JA.A734C
Metal
Part No.
JA.A734HM
JA.A734HC
Connection Diagram
14-Pin DIP
=
TA
2SoC unless
specified otherwise
Supply Voltage
± 18 V
lOrnA
Peak Output Current
Differential Input Voltage
± 10 V
Input Voltage Range (Note 1)
± 13 V
Voltage Between Offset Null
and V±O.S V
Internal Power Dissipation
(Note 2)
Metal Package
SOOmW
Ceramic DIP
670mW
Operating Temperature Range
-SSoC to +12SoC
Military (JA.A734)
Commercial (JA.A734C)
O°C to +70°C
Storage Temperature Range
-6SoC to +150°C
Metal Can, DIP
Pin Temperature (Soldering,
60 s Max)
300°C
Absolute Maximum Ratings
Code
5N
5N
Ne
PULL-UP
RESISTOR
Ne
OUT
v+
GND
Ne
vOFFSET
+IN
NULL
Ne
Ne
-IN
OFFSET
NULL
(Top View)
Order Information
Type
Package
JA.A734
Ceramic DIP
JA.A734C
Ceramic DIP
Notes
1. Ratmg apploes for ± 15 V supplies, For other supply voltages
the rating IS within 2 V of either supply,
2 Rating applies to ambient temperatures up to 70·C, Above
70·C ambient derate linearly at 6 3 mW I·C for metal package.
S 3 mW/·C for DIP,
5·16
Code
SA
SA
Part No.
JA.A734DM
JA.A734DC
Il A734
Equivalent Circuit
09~
,....
R6
6.0 k
R5
2.4 k
07
'-.J
,...,
R3
3.5 k
a/
.........
R4
3.5 k
OS
r
05
06
'f'"
PULL-UP
R9
10 k
OUT
"r-...
R11
....
012
2.7 k
GND
04
r
011
R10
740
R2
3.5 k
"
01
,.--
~010
R1
3.5 k
(-)
RS
400
R7
200
R12
19 k
..&
/1
03 ..........
02
R13
52
(+)
'-l
~
,...,017
,..., 016
R1B
3.6 k
'-.J
,...,014
R15
3.6 k
R17
110
R19
'-.J
,..., 015
R16
1
R14
110
'-.I
013(
2.0 k
v-
2.0 k
OFFSET NULL
OFFSET NULL
5-17
J.LA734
IlA734C Electrical Characteristics
TA = 25°C, Pin 8 tied to +15 V, unless otherwise specified, V±
(Note 3)
Characteristic
Condition
Input Offset Voltage
Rs::::; 50 kQ
Min
Input Offset Current
Input Bias Current
Typ
Max
± 15V.
Unit
1.1
5.0
mV
3.5
25
nA
30
100
nA
55
MQ
Input Capacitance
3.0
pF
Offset Voltage Adjustment Range
8.5
mV
60 k
V/V
Input Resistance
Large Signal Voltage Gain
7.0
RL = 1.5 kQ to +5.0 V
35 k
Positive Supply Current
Output LOW
4.0
5.0
Negative Supply Current
Output LOW
1.5
2.0
mA
Power Consumption-Output LOW
82
105
mW
Transient Response
RL = 1.5 kQ to +5.0 V
5 mV Overdrive, 100 mV Pulse
mA
ns
200
The following specifications apply for O°C ::::; TA ::::; +70°C
Input Offset Voltage
1.2
7.5
mV
4.0
45
nA
RS::::; 50 Q
3.5
20
IlV 1°C
TA = +25°C to +70°C
0.02
0.3
nA/oC
TA = +25°C to O°C
0.05
0.75
nA/oC
RS::::; 50 kQ
Input Offset Current
Average Input Offset Voltage Drift
Without External Trim
Average Input Offset Current Drift
Input Bias Current
Large Signal Voltage Gain
150
nA
25 k
VIV
Input Common Mode Voltage Range
± 10
V
Differential Input Voltage Range
±10
V
Common Mode Rejection Ratio
Rs::::; 50 kQ
70
Supply Voltage Rejection Ratio
VS= ±5Vto ±18V
RS::::; 50 kQ
Output HIGH Voltage
lOUT = 0.080 mA
7.0
lOUT = 0.080 mA, Va = +5.0 V
2.4
Output LOW Voltage
RL = 1.5 kQ to +5.0 V
dB
100
6.0
100
IlV/V
V
5.0
V
0.4
V
Positive Supply Current
Output LOW
7.0
mA
Negative Supply Current
Output LOW
2.5
mA
Power Dissipation-Output LOW
145
mW
ISINK = 3.2 mA
Note
3. Pin numbers refer to metal package.
5·18
IlA734
/lA734 Electrical Characteristics
TA = 25°C, Pin 8 tied to +15 V, unless otherwise specified, V± = ± 15 V.
(Note 3)
Characteristic
Condition
Input Offset Voltage
Rs ::; 50 kfl
Min
Typ
Max
Unit
0.9
3.0
mV
Input Offset Current
1.5
10
nA
Input Bias Current
28
50
nA
Input Resistance
20
Input Capacitance
Offset Voltage Adjustment Range
Large Signal Voltage Gain
RL = 1.5 kfl to +5.0 V
35 k
Positive Supply Current
Output LOW
60
Mfl
3.0
pF
8.5
mV
70 k
VIV
4.0
5.0
mA
Negative Supply Current
Output LOW
1.5
2.0
mA
Power Consumption-Output LOW
82
105
mW
Transient Response
RL = 1.5 kfl to +5.0 V
5 mV Overdrive, 100 mV Pulse
200
ns
The following specifications apply for -55 ° C ::; TA ::; + 125 ° C
Input Offset Voltage
RS ::; 50 kfl
Input Offset Current
1.1
4.0
mV
3.0
20
nA
Average Input Offset Voltage Drift
Without External Trim
RS ::; 50 kfl
2.5
15
/lV/oC
Average Input Offset Current Drift
TA = +25°C to +125°C
TA = +25°C to -55°C
0.01
0.05
0.1
0.4
nA/oC
nA/oC
150
nA
Input Bias Current
Large Signal Voltage Gain
RL = 1.5 kfl to +5.0 V
Input Common Mode Voltage Range
Differential Input Voltage Range
25 k
VIV
±10
V
±10
Common Mode Rejection Ratio
RS ::; 50 kfl
70
Supply Voltage Rejection Ratio
Vs = ±5 V to ± 18 V
Rs ::; 50 kfl
Output HIGH Voltage
lOUT =0.080 mA
lOUT = 0.080 mA, Va = +5.0 V
Output LOW Voltage
ISINK = 3.2 mA
V
100
5.0
dB
100
/lV/V
5.0
V
V
0.4
V
Positive Supply Current
Output LOW
7.0
mA
Negative Supply Current
Output LOW
2.5
mA
Power Dissipation-Output LOW
145
mW
Note
3. Pin numbers refer to metal package.
5·19
7.0
2.4
J.LA734
Typical Performance Curves For ILA734 and ILA734C
Transfer
Characteristics
80
Vs
Un-Nulled Input Offset Voltage vs.
Ambient Temperature
~500r-'--r-'--r--r~--r-'--r-'
0
=-
:!::15V
Vs =
PINSTIEDTO +15V
RL"" 15knTIEDTO +5V
>
~
~
I
w
~ 4.0
g
~
"-
1\ /
...
l..\ II
O 2.0
V
o
- 400 - 300 - 200 - 100
~
"
'h---t
0
100
200
300
1
o
~1
NON· INVERTING
INPUT
400
"
O. 6
-80
~
;
-20
20
60
140
100
i'-
20
..-
100
60
350
"
I
iVS=±15V~
%
0
4.40
~
<
~ 8.15
:-f-r-.
"i 810
I
"~
V
g 805
... l ...... v
w
c-
VSI"~,v p- I---/-
'-
410~
400
20
20
60
~
~
I
<
800
-60
,.
%
.........
:>
430 ~
4 20
r> t--.
.
;
-6
10
-2
1\
I
i...
~
80
~
60
~
o
40
\
1\
z
......
- 20
100
AMBIENT TEMPERATURE _ °C
140
"
> 325
E
H--
- 60
-20
" l'l!
~ 300
0
>
.........
9
...:>
...
.
is
275
./
0
0
4
0
v
250
I
I
~
22'
-60
-20
20
60
100
AMBIENT TEMPERATURE - "C
5-20
:=
25°C
_
+1Sy :::: V,.,- t:2:1EN
- f--
PIN8TIED10
0
I
.......
TA
V1'N> 10mV
L
~+
;.
140
Output Voltage Low
vs. Sink Current
800
X
I
100
60
VIS"I±15~
PIN8T1EDTQV+ ISNK=32mA
w
--:--
o
AMBIENT TEMPERATURE _ °C
Output Low Voltage vs.
Supply Voltage and Ambient
Temperature
PIN8T1EOTOV+
lo=80J1A
.,
;,oJ,J" ~15~-
~ 10
DIFFERENTIAL \NPUTVOLTAGE - V
Output High Voltage vs.
Supply Voltage and Ambient
Temperature
~
V~A == ~~:cv
-10
140
AMBIENT TEMPERATURE _ °C
> 820
AMBIENT TEMPERATURE _ °C
~
0
'- .......
- 20
:.--
0
.........
10
-60
L-~_-2~O-J--2LO~--6~0--L-'~0-O-L-'~40
Input Offset Current vs.
Ambient Temperature
,
20
0
'"
'- ~ !--
, ,0
~
o
w
O.8
,
I
"
"
12
!Z
"-
~200~~-P~~~~~~~4--+-1
~ 100r-4-~~~+--r~~~4--+-1
40
30
~
45
~ 50
:>
~ 30°r-~~-1--t--r-+--r-17~-1
o
.....- ...-;t:~0"
0,-
400
g
Input Bias Current vs.
Differential Input Voltage
±L,'vsJ ±lL
~ 40
~
AMBIENT TEMPERATURE _ °C
Input Bias Current vs.
Ambient Temperature
'"~"
"~S"lOCkE
2
INPUT VOLTAGE - JAV
60
I
w
15V
I-"
I-"
,-/
C;1 4
g
I~
INVERTING INPUT \
16
:!::
--
18
E
> 6.0
Input Offset Voltage Change vs.
Ambient Temperature Nulled to
Zero at 25°C
V- ::::V
V
100
10
140
SINK CURRENT - rnA
/lA734
Typical Performance Curves for
Voltage Gain vs. Ambient
Temperature
120k
~A734
and
~A734C
Positive and Negative
Supply Currents vs. Ambient
Temperature
Voltage Gain vs. Supply
Voltage
55
I
Vs == ±15V
(Cont.)
TA=2S"C
RL = 15kflTIEDTO +5V
70 k
RL == 1S!1TIEDTO +5V
r~U~1 ~~~Vj
100 k
~
~
~
8Dk
~
6Dk
f--
~
E
~
I,
w
:;
'" 4 5
!\
I
~
z
~
'"
SDk
w
.......
t-
40k
"~
--
I\.
t'....
~
20
- 20
60
100
±s
140
-
"'- r-...
±7
± 11
±9
Response Time For
Various Input
Overdrives
Response Time For
Various Input
Overdrives
>
I
>
I
"~
~
.
6
4
~
=>
o
1
~~N!?~~~TIIED~O ~15!V
1
TA=25°C
I
Vs=+15V
2
---..V V 1
10 mV -fJ 1/ I'- 2 mV
/ V" f-r- 5 mV
E
~
g
0
6
~
4
~
2
o
I
>
I
w
w
~
20mV-
~
=>
>
E
I
w
"~
100
~
50
.
~
ir -100
~
=>
160
240
320
400
TIME - ns
20 mV--
,...,\
10mV
f-
o
>
.
~
=>
~
o
>
E
I
w
6
pIN8~IE~TO'+1~V '
I
RL = 10kTIEDTO +15V
TA = 25°C
Vs"=±15V
II
/
I
!-PI '/A '"" 2 mV
r- - 20~V
I
'/
'
5~V
2f- -10mV 1= f-h
~/,
I
4
r/
0
"
>
6
4
20 mY
10 mV./
240
320
-50
~ 50
160
240
TIME- ns
320
400
"
~
TRENb LlN'E
o
2
0
,
1
II
10
V
V
0
200
400
\'
\
\,\
1\
-U
T1
Vr
10
l5.J
t
\ ,\
O!"
'--~
~
~
'mV
240
TlME-ns
5-21
-s
o
....- ~-
)/
1
~ -10
0
160
1000
800
f"!
~
I
~
80
600
HOURS
w
15V
I\~ ,.--2mV
1\\ \
400
TIME -
Stabilization Time of
Input Offset Voltage
From Power Turn-On
0;,-
-100
80
f---
2
~
~
is =,'0"
~
I
"
s ='±15'V
TA = 125°C-
~
~V c-
"
160
E
w
140
J
l 30
":;'" 2,
~
8
~ 100
"
5
,
TIME - ns
~
100
w
80
~g
60
":z:z /
'" 'If
>
"
20
~
~
o
~
05
-60
III I
Is
I 1
J J
20
AMBIENT TEMPERATURE _ °C
0
"
:;
'"
-..... ""
Input Offset Voltage
Drift vs. Time
\" :--tt---
>
I
:;"'"
15
15
I \""t-2 mV
~\
>
8
±
\'
Response Time For
Various Input
Overdrives
I
13
PIN80PEN
RL = 15knTlEDTO +5V
TA "" 25"C
+15V
V
Response Time For
Various Input
Overdrives
w
i25
J.....l--1"
~f=(li8TlrDTb ':;5 VI
j.....{"
~N8hpE~I_ - - -
"
Z
0
80
:!:
o
-50
"
5 ..... 1-"'"
v
SUPPLY VOLTAGE -
AMBIENT TEMPERATURE -"C
w
r
50 k
20k
-60
1
'"
f--
320
400
Vs = :!:1SV
Rs=SO[!
-
Z
~ -15
w
"~ -20
:z:
" -25
",0 = ,14\
IN!TlA~OF~SET ~OL1AGEI < 1 iV
40
80
120
TIME FROM POWER APPLICATION -
160
s
f.tA734
Typical Performance Curves for ILA734 and ILA734C (Cont.)
Response Time For
Various Input
Overdrives
0
10 my
0
20 mV- ~
E
II
>
I
~ 60
~o
1'r-2 mV
~c-
~
SmV
Ii , J I
0
>
H.J
Response Time For
Various Input
Overdrives
rl
g
II
>
0
E
I
w
I
w
~~ -5
PIN8T1EDTO +1SV
RL::; 15k(lTlEDTO +5V
TA == 2S Q C
Vs = :t15V
0
"
60
160
240
TIME -
320
ns
~
~
I
\
0
PIN8TIEDTO +15V
50
~
0
VSI"
1
15 IV
I
I
I
80
160
I
1-
I I
240
320
400
TIME- ns
Vs= :t15V
VIN = ± tOVRis == 100 kll
j:: 100
-..
...-I -
~
Z
o
"
~
~
;;J
/
'"c
o
'oz"
0
w
/
"~ or- -
~/
I
~~ : ~55o~n TIED TO + 5 V _
o
I
~ 200
""
\
5 mV
11 0
!;
w
-
I
I\- -2mV
~
I
w
""
20
J
Common Mode Rejection
Ratio vs. Ambient Temperature
h- -;,te
~o
\
20 mV_ ~,\
10mV
!;
300
~ 100
0
4
"
400
Thermal Response of
Input Offset Voltage
To Step Change of Case
Temperature
>
I
\,\
"':;" 100
0
~-10 0
I
I \\
Vs= ±15V
Rs = SOn
-
Vo = 14 V
I
'NllTIAiOFrETIVOliAGi < 1rV
20
40
60
TIME FROM HEAT APPLICATION -
60
'"
8'"
I
-
C-
7o
60
-60
SECONDS
-20
20
60
AMBIENT TEMPERATURE -
Test Circuits
Offset Null Circuit
v+
v5-22
100
gc
140
JlA734
AC Test Circuit
Typical Applications (Cont.)
SCOPE
VERTICAL
Level Detector With Hysteresis
115 V
"A"
V+
INPUT
Rs
Y,N -""VI,,.,,.---t
~-...~VOUT
50 fl
VR1
R2
VOUT
-15 V
5011
7V
150 k!l
r---~~----~--~VVV----4JrS1~+15V
~VHYS
[[
0.2 V
Vo (MAX)
__
i
Vo (MIN)
VREF
Typical Applications
RS
=
Strobe Circuitry
VHYS
R1 R2
R 1 + R2 FOR MINIMUM OFFSET
=
R1 [VO MAX - Vo MINI
R1 + R2
V+
High Power Output Circuits
10
V+
>,~..--------- VOUT
.---.""'- STRO BE
RL
2 kll
VOUT
Alternate Strobe Circuitry
V+
>~..-------- VOUT
STROBE 1
STROBE 2
V-
• y, 9944
5·23
J.LA734
Free Running Oscillator
Typical Applications (Cont.)
+15 V
Precision Dual Limit Go No Go Tester
1 kfl
20 kll
VIN-_--I
>"'-------_.VAEF'
+15 V
VOUT
VOUTPUT
V-
c
VREF2
-15 V
-=-
V-
2 kfl'
Voltage Controlled Oscillator
18 kfl
68 kfl
30 kll
+15 V
c ~ 80 x 10-61
'AdJusls
VAEF < 0
V,N > 0
VOUT 1
OV
VAEF
10 I,
12
r5JS!SJ
V-
7.0V-W-,nr
0.2
v ______ ~
ov
-.lllf
10
11
~
I.12
5-24
IlA734
Typical Applications (Cant.)
Pulse Width Discriminator
Frequency Divider and Staircase Generator
C
C2
STAIRCASE
OUTPUT
Your
R
Vour
v,
v-
v-
v-
l[
7.0V
-- 0.2 V
IVREF I= 2VO + N [3.5T + 2VO T in Seconds
Vo for FJT 1000
~
VOUT Pulse Appears
C1C~IN ]
Whenever T
>
R C V2
V1
031 V
Phase Meter
v·
VOUT
v,~
20 k!l
10 It
V2~
VAVG~
21l'VAVG
VOUT, PEAK
-1l'
'" > 0
5-25
V2~
VOUT _ _ __
VOUT
VAVG------r-:b
'" >
0
JlA760
High-Speed
Differential Comparator
F=AIRCHILD
A Schlumberger Company
Linear Products
Connection Diagram
8-Pin Metal Package
Description
The IlA760 is a Differential Voltage Comparator
offering considerable speed improvement over the
IlA 710 family and operation from symmelric supplies
of from ± 4.5 V to ± 6.5 V. The IlA760 can be used in
high-speed analog-Io-digital conversion systems and
as a zero crossing detector in disc file and tape
amplifiers. The IlA760 output features balanced rise
and fall times for minimum skew and close matching
between the complementary outputs. The outputs are
TTL compatible with a minimum sink capability of two
gate loads.
•
•
•
•
•
v+
IP2
v-
GUARANTEED HIGH SPEED-25 ns MAX
GUARANTEED DELAY MATCHING ON
BOTH OUTPUTS
COMPLEMENTARY TTL COMPATIBLE OUTPUTS
HIGH SENSITIVITY
STANDARD SUPPLY VOLTAGES
(Top View)
PIO 4 connected to case
Order Information
Type
Package
IlA760
Metal
IlA760C
Metal
Connection Diagram
14-Pin DIP
Code
5W
5W
Part No_
IlA760HM
IlA760HC
NC
Connection Diagram
8-Pin DIP
NC
NC
NC
IP 2
IP 2
IP 1
IP 1
v-
0
v'
2
7
3
6
4
5
V-
NC
8
OP 1
OP 2
GND
(Top View)
(TOp View)
Order Information
Type
Package
IlA760
Ceramic DIP
IlA760C
Ceramic DIP
Code
6A
6A
Order Information
Type
Package
IlA760
Ceramic DIP
IlA760C
Ceramic DIP
Part No_
IlA760DM
IlA7 60DC
5-26
Code
6T
6T
Part No_
IlA760RM
IlA760RC
p,A760
Absolute Maximum Ratings
Positive Supply Voltage
Negative Supply Voltage
Peak Output Current
Differential Input Voltage
Input Voltage
Internal Power Dissipation
(Note 1)
Metal Package
DIP
+8V
-8V
10 mA
±5V
V+ ~ VIN
~
Operating Temperature Range
Military (~A760)
Commercial (~A760C)
Storage Temperature Range
Metal and Ceramic DIP
Molded DIP
Pin Temperature (Soldering)
Metal and Ceramic DIP
(60 s)
Molded DIP
V-
500mW
670mW
-55°C to 125°C
O°C to 70°C
-65°C to 150°C
-55°C to 125°C
Equivalent Circuit
r-~----'-----~----~------------------~----~--------~~--~----------'-- v'
OUTPUT 1
INPUT 1
GROUND
INPUT 2
OUTPUT 2
R3
350n
RS
350 11
R7
350
n
R8
100
n
R12
300n
R13
4 kn
Note
1. Ratings applies to ambIent temperatures up to 70 oe. Above
70 0 e ambient derate linearly at 6.3 mWfoe for metal package
and 8.3 mW foe for the ceramIc DIP. For molded DIP, derate at
6.7 mWfoe above 30 0 e ambient temperature.
5-27
R14
3500
•
JLA760
~A760
Electrical Characteristics
Vs = ±4.5 V to ±6.5 V, TA
otherwise specified.
Characteristic
Condition
Input Offset Voltage
Rs.:o; 200
= -55°C to +125°C, TA = 25°C for typical figures unless
Min
n
Typ
Max
Unit
1.0
6.0
mV
~A
Input Offset Current
0.5
7.5
Input Bias Current
8.0
60
= VOH
Output Resistance (either output)
VOUT
Response Time
(Note 3), TA
(Note 2), TA
= 25°C
= 25°C
18
(Note 4)
Response Time Difference between
Outputs
(tpd of +VIN1) - (tpd of -VIN2)
(tpd of +VIN2) - (tpd of -VIN1)
(tpd of +VIN1) - (tpd of +VIN2)
(tpd of -VIN1) - (tpd of -VIN2)
Input Resistance
Input Capacitance
Average Temperature Coefficient
of Input Offset Voltage
Average Temperature Coefficient
of Input Offset Current
Input Voltage Range
(Note
(Note
(Note
(Note
2),
2),
2),
2),
= 25°C
= 25°C
= 25°C
= 25°C
Output LOW Voltage (either output)
Positive Supply Current
Negative Supply Current
ns
25
ns
= 1 MHz
f = 1 MHz
RS = 50 n, TA = -55°C to
TA = +125°C
TA = 25°C to TA = +125°C
TA = 25°C to TA = -55°C
Vs = ±6.5 V
f
o .:0; lOUT .:0; 5.0 rnA
Vs = ±5.0 V
lOUT = 80 ~A, Vs = ±4.5 V
ISINK = 3.2 rnA
Vs = ±6.5 V
Vs = ±6.5 V
Notes
2. Response time measured from the 50% pOint of a 30 mVp·p
10 MHz sinusoidal input to the 50% pOint of the output
3. Response time measured from the 50% pOint of a 2 Vpk-pk
10 MHz sinusoidal Input to the 50% pOint of the output
ns
5.0
5.0
7.5
7.5
±4.0
Differential Input Voltage Range
Output HIGH Voltage (either output)
30
16
TA
TA
TA
TA
2.4
2.4
~A
n
100
ns
ns
ns
ns
12
kn
8.0
pF
3.0
~V/oC
2.0
7.0
nA/oC
nA/oC
±4.5
V
±5.0
V
3.2
3.0
V
V
0.25
0.4
V
18
32
rnA
9.0
16
rnA
4. Response time measured from the start of a 100 mV Input step
with 5 mV overdrive to the time when the output crosses the
logic threshold.
5-28
J,tA760
IlA760C
Electrical Characteristics
Vs = ±4.5 V to 6.5 V, TA = O°C to 70°C, TA = 25°C for typical figures unless
otherwise specified.
Characteristic
Condition
Input Offset Voltage
Rs:::; 200 fl
Min
Typ
Max
Unit
1.0
6.0
mV
Input Offset Current
0.5
7.5
IlA
Input Bias Current
8.0
60
IlA
= VOH
Output Resistance (either output)
VOUT
Response Time
(Note 2), TA = 25°C
(Note 3), T A = 25°C
(Note 4)
Response Time Difference between
Outputs
(tpd of +V,N1) - (tpd of -V,N2)
(tpd of +V,N2) - (tpd of -V,N1)
(tpd of +V,N1) - (tpd of +V,N2)
(tpd of -V,N1) - (tpd of -V,N2)
(Note
(Note
(Note
(Note
f
Input Capacitance
f
Average Temperature Coefficient
of Input Offset Voltage
RS
Input Voltage Range
TA
TA
TA
TA
18
= 25°C
= 25°C
= 25°C
= 25°C
= 50 fl, TA = O°C to TA = +70°C
TA = 25°C to TA = +70°C
TA = 25°C to TA = O°C
Vs = ±6.5 V
±4.0
Differential Input Voltage Range
Positive Supply Current
Negative Supply Current
Vs = ±6.5 V
Output LOW Voltage (either output)
ns
ns
ns
5.0
5.0
10
10
ns
ns
ns
ns
12
kfl
8.0
pF
3.0
IlV 1°C
5.0
10
nA/oC
nA/oC
±4.5
V
±5.0
o :::; 'OUT:::; 5.0 rnA
Vs = ±5.0 V
lOUT = 80 IlA, Vs =
ISINK = 3.2 rnA
Vs = ±6.5 V
Output HIGH Voltage (either output)
fl
30
25
16
= 1 MHz
= 1 MHz
Input Resistance
Average Temperature Coefficient
of Input Offset Current
2),
2),
2),
2),
100
Notes
2. Response time measured from the 50% point of a 30 mVp·p
10 MHz sonusoldal onput to the 50% point of the output.
3 Response time measured from the 50% point of a 2 Vpk.pk
10 MHz sinusoidal input to the 50% point of the output.
±4.5 V
2.4
2.5
3.2
3.0
V
V
0.25
0.4
V
18
34
rnA
9.0
16
rnA
4. Response time measured from the start of a 100 mV input step
with 5 mV overdrive to the time when the output crosses the
logic threshold.
5·29
•
JlA760
Typical Performance Curves
Response Time for
Various Input Overdrives
>
>
v~ ~ ±51V
I
w
TA=
"~
2OmV--.,
0
>
~
~
10
o.ff#
~
~
~
20 mV
~
"0
;::
w
100
...~
50
~
50
11
~
20
30
TIME - ns
30
I
tpd+
;::
w
Ip,
!l!
10
-
3Q
2
35
ns
I--+-+--+-t-v' .,Vs-±65V
............ ..
>
i
Voltage Transfer Characteristic
>
w
"~
"~
g
~
~
5
§
"o
Ii'
........
-
-~
o
10
20
50
100
200
INPUT VOLTAGE -
500 1000 2000
INPUT VOLTAGE -
mVpk-pk
Voltage Gain as a
Function of
Supply Voltage
INPUT VOLTAGE -
mV
Voltage Gain as a
Function of
Ambient Temperature
7,000
4,000
I 6,000
z
~
5,000
/~
~ 4,000
~
3,000
2,000
/
/'
---
>
,/"
;0
;0
V
""
~
,. "
~
t'-..
"-
"~
Vs~±65V
"-
t'-..
iiicr
I'"
cr
"0
I'...
.......
....... t--,
~
=
.......
~
~
~
il
2,000
o
±45
l - i'-..
~w 3,000
/
12
Vs=±5V
TA'" 25°C
8,000
mY
Input Bias Current as a
Function of
Ambient Temperature
9,000
>
mVpk-pk
I
I
w
!
12
10
INPUT VOLTAGE -
Vs-±5V
1
...........
25
1-
Q
w
20
Voltage Transfer Characteristic
10 MHz SINE WAVE INPUTS
TA""25 C
::--..,
2.
15
TIME -
v~~±;vl II
I
10
10
3S
Response Time as a
Function of
Input Voltage
--
I
IPd-
I
";:;
15
20
~
I
I
~
10
-
'"z
~
I
Q
I
30
;
I
~
il
~
~2iv
>
E
100
I
I
10 MHz SINE WAVE INPUTS = 25 C
TI
'~
10 mY
V;~;5VI
TA=25°C-
~5mv
~
~
.
,..,
~
E
I
~
"~
~
2~V
~
">
0
w
40
V;~±5~
I
25°C~
:-- 5mV
mv-" 'fIj-
Response Time as a
Function of
Input Voltage
Response Time for
Various Input Overdrives
±5Q
±55
SUPPLY VOLTAGE -
±60
V
±65
60
2.
6.
TEMPERATURE _ °C
5-30
100
140
•
-60
-20
20
60
TEMPERATURE _
100
0
C
140
J,LA760
Typical Performance Curves (Cont.)
Response Time as a
Function of
Ambient Temperature
Input Offset Current as a
Function of
Ambient Temperature
,.
"1
I
!za:W
a
~
08
\
30
.6
Vs=±5Y
vo~ @ iOUT ~ ••lmA
25
-= !---
'\
04
>
I
.- ......-
~
g
>-- .-
-tpd+
......
fpd-
•
-2.
2.
so
TEMPERATURE _
100
e
•-so
140
C
-20
20
so
140
100
AMBIENT TEMPERATURE _
0
30
Ys=±5V
TA=25"C
25
20
25
20
/
~
a:
15
~
,.
50
100
200
CAPACITIVE LOAD - pF
,.
10
~~4'-:.C-L-""±'~0c-L--±.~.-.L-""±6"".•C-.L-~±6 •
SUPPLY VOLTAGE -
50
K
V
5·31
100
20D
---
>--
l/
V
CAPACITIYE LOAD - pF
Common Mode Range as a
Function of
Supply Voltage
14.
100
_ °C
Ys=±l5Y
TA = 25°C
/
W
!I!
so
TEMPERA~RE
14
/
W
,.
20
16
YS=±5Y:i
I
,. ,.
;::
W
VOL@ 'SINK ~ 32 mA
-20
Input Bias Current as a
Function of
Differential Input Voltage
TA = 25°C
I
•-so
AMBIENT
30
I-
~e
C
Fall Time as a
Function of
Capacitive Load
Rise Time as a
Function of
Capacitive Load
I- I-- ~OQICtHIf
I
......... .....,
i .2
-
I
=30 mY k-pk, f = 10 MHz -
YIN
o
~
v;~±~.• vITO,I..J
Vs""±6~V
\.
Output Voltage Levels as a
Function of
Ambient Temperature
v
I"'-- r-...
20
/'~
.........
~
40
rso
---so
t-
DIFFERENTIAL INPUT VOLTAGE - mV
100
j.LA760
Typical Applications
Line Receiver With High Common Mode Range
Rs
Fast Positive Peak Detector
INPUT
-.AJ\f>r~WI,-----1o--i
OUTPUT
INPUT
-"VItv---------,r-:-l
OUTPUT
Common mode range
=
RS
± 4 x 50 V
RS
Differential Input sensitivity = 5 x 50 mV
Level Detector with Hysteresis
PI must be adjusted for optimum common mode reJection.
100kn
For RS = 200 n
Common mode range = ± 16 V
Sensitivity = 20 mV
OUTPUTj:
,-''Mr-1-'"'' .,~----1r--OUTPUT
I
High-Speed 3-Bit AID Converter
o
MSB
Zero Crossing Detector
v+
FD666
5 k11
INPUT -.,....-..., ""'oc---I>I-,---I!-~--1R ~~--- OUTPUT
0.75 Y
.,,-c-_.,-_ OUTPUT
R3
100 n
son
1.25 V
R'n
100
Total Delay = 30 ns
Input frequency = 300 Hz to 3 MHz
Minimum input voltage = 20 mVpk-pk
1.75 V
R'
100 0
2.25 V
R6
100 0
2.75 V
R7
100 0
soo
R8
3500
+.v
Input voltage range: 3.5 V
TYPical conversion speed: 30 ns
Pin numbers shown are for Metal Package only.
5-32
~A 111
• ~A311
Voltage Comparators
FAIRCHILD
A Schlumberger Company
Linear Products
DESCRIPTION
The J.LA 111 and J.LA311 are monolithic, low input current
Voltage Comparators, each constructed using the
Fairchild Planar epitaxial process. The J.LA 111 series
operates from the single 5 V integrated circuit logic
supply to the standard ± 15 V operational amplifier
supplies. The J.LA 111 series is intended for a wide
range of applications including driving lamps or relays
and switching voltages up to 50 V at currents as high
as 50 mAo The output stage is compatible with RTL,
DTL, TTL and MOS logic. The input stage current can
be raised to increase input slew rate.
•
•
•
•
•
•
Connection Diagram
B-Pin Metal Package
v+
v-
LOW INPUT BIAS CURRENT 150 nA MAX (111),
250 nA MAX (311)
LOW INPUT OFFSET CURRENT 20 nA MAX
(111),50 nA MAX (311)
DIFFERENTIAL INPUT VOLTAGE ±30 V
POWER SUPPLY VOLTAGE SINGLE 5.0 V
SUPPLY TO ± 15 V
OFFSET VOLTAGE NULL CAPABILITY
STROBE CAPABILITY
Absolute Maximum Ratings
Voltage Between V+ and VTerminals
Output to V- (J.LA 111)
(J.LA311 )
Ground to VDifferential Input Voltage
Input Voltage (Note 1)
Internal Power Dissipation
(Note 2)
Output Short,Circuit Duration
Storage Temperature Range
Metal and
Ceramic DIP
Molded DIP
Operating Temperature Range
Military (J.LA 111)
Commercial (J.LA311)
Pin Temperature (Soldering)
Metal and Ceramic (60 s)
Molded (10 s)
BALANCE!
STROBE
+IN
(Top View)
Order Information
Type
Package
J.LA111
Metal
J.LA311
Metal
Code
5W
5W
Part No. •
J.LA 111HM
J.LA311HC
Connection Diagram
B-Pin Mini DIP
8
36 V
50 V
40 V
30 V
±30 V
± 15 V
v+
GND
500mW
10 s
+IN
OUT
-IN
BALANCE!
STROBE
v-
BALANCE
(Top View)
-65°C to +150°C
-55°C to +125°C
Order Information
Type
Package
J.LA 111
Ceramic DIP
J.LA311
Ceramic DIP
J.LA311
Molded DIP
-55°C to +125°C
O°C to +70°C
Notes
1 ThIs rating applies for ± 15 V supplies. The positive input
voltage limit IS 30 V above the negatIve supply. The negatIve
IOput voltage limit IS equal to the negative supply voltage or
30 V below the positive supply. whichever is less.
2. RatIng applies to ambient temperatures up to 70'C. Above
70'C ambient derate linearly at 6.3 mV! 'c to Metal Package.
8.3 mW! 'c for mini DIP.
5-33
Code
6T
6T
9T
Part No.
J.LA111RM
J.LA311RC
J.LA311TC
~A 111
• ~A311
Equivalent Circuit
BALANCE
r---~--~~'---~---+----~----~-------;~-;~----------------~-----V+
R9
500 !!
:J-+---_OUTPUT
R11
130 !l
Q15
R12
600 {l
R13
4 n
'----t----+-GROUND
JLA111
Electrical Characteristics
Vs = ± 15 V, TA = -55°C to +125°C unless otherwise specified. (Note 3)
Typ
Max
Unit
0.7
3.0
mV
TA = 25°C
4.0
10
nA
Input Bias Current
TA = 25°C
60
100
nA
Voltage Gain
TA=25°C
200
V/mV
Response Time (Note 5)
TA = 25°C
200
ns
Saturation Voltage
VIN ~ -5 mY, lOUT = 50 mA
TA=25°C
0.75
Strobe On Current
TA = 25°C
3.0
Output Leakage Current
VIN ~ 5 mY, VOUT = 35 V
TA = 25°C
0.2
Input Offset Voltage (Note 4)
RS
Characteristic
Condition
Input Offset Voltage (Note 4)
TA = 25°C, RS
Input Offset Current (Note 4)
~
Min
~
50 kQ
50 kQ
Input Offset Current (Note 4)
Input Bias Current
Input Voltage Range
1.5
V
mA
10
nA
4.0
mV
20
nA
150
nA
±14
V
V+ ~ 4.5 V, V- = 0
VIN ~ -6 mY, ISINK ~ 8 mA
0.23
0.4
V
Output Leakage Current
VIN ~ 5 mY, VOUT = 35 V
0.1
0.5
JLA
Positive Supply Current
TA = 25°C
5.1
6.0
mA
Negative Supply Current
TA = 25°C
4.1
5.0
mA
Saturation Voltage
Notes on following pages.
5-34
JlA 111 • JlA311
IlA311
Electrical Characteristics
Vs = ± 15 V, TA = O°C to + 70°C unless otherwise specified. (Note 3)
Characteric
Condition
Min
Typ
Max
Unit
Input Offset Voltage (Note 4)
TA = 25°C, RS :5 50 kfl
2.0
7.5
rnV
Input Offset Current (Note 4)
TA=25°C
6.0
50
nA
250
Input Bias Current
TA=25°C
100
Voltage Gain
TA=25°C
200
V/rnV
nA
Response Time (Note 5)
TA = 25°C
200
ns
Saturation Voltage
VIN :5 -10 rnV, lOUT = 50 rnA
TA = 25°C
0.75
Strobe On Current
TA = 25°C
3.0
Output Leakage Current
VIN 2: 10 rnV, VOUT = 35 V
TA=25°C
0.2
Input Offset Voltage (Note 4)
RS :5 50 kfl
1.5
V
rnA
50
nA
10
rnV
Input Offset Current (Note 4)
70
nA
Input Bias Current
300
nA
Input Voltage Range
±14
V
Saturation Voltage
V+ 2: 4.5 V, V- = 0
VIN:5 -10 rnV, ISINK:5 8 rnA
0.23
0.4
V
Positive Supply Current
TA = 25°C
5.1
7.5
rnA
TA=25°C
4.1
5.0
rnA
Negative Supply Current
Notes
3. The offset voltage, offset current and bias current
specifications apply for any supply voltage from a single
5 V supply up to ± 15 V supplies.
4. The offset voltages and offset currents given are the maximum
values required to drive the output within a volt of either supply
with a 1 rnA load. Thus, these parameters define an error band
and take into account the worst case effects of voltage gain
and input impedance.
5 The response time specified (see definitions) is for a 100 mV
Input step with 5 mV overdrive.
Typical Performance Curves for IlA 111
Input Bias Current as a
Function of Temperature
40 0
vs~±1'5V
I
Offset Voltage as a
Function of
Input Resistance
Input Offset Current as a
Function of Temperature
> 100
30
VS"" ±15V
TA _ 25"C
E
I
w
'"
0
RAISEO·
~
"-
'-
20 0
~ 10
t;
~
"
.........
~
'-...
100
0
-55 -35 -15
'-
NORMAL
~
RAISED"
l'!
..........
r--
~
t--
NORMAL
o
5
25
45
TEMPERATURE -
65
"c
85
105125
I
-55 -35 -15
5
25
45
TEMPERTURE -
65
85
°C
• PinS 5, 6 and 8 are shorted.
5·35
105125
~
os
5l
1
MAXIMUM
TYPICAL
.........
;!
Im~lvoYtl'i11
o1
10k
100 k
10M
1M
INPUT RESISTANCE -
n
•
JLA 111 • JLA311
Typical Performance Curves for J.LA 111
Input Bias Current as a
Function of
Differential Input Voltage
180
.
V;:I ,115~
160
TA '" 25°C
...'"
i
120
§ 100
,
80
~
10
",,"-
~
30
l\.
o
EMITTER
FOLLOWER
-f-
-8
-4
12
DIFFERENTIAL INPUT VOLTAGE -
"-'\
RL = Soon
J
-55 -35 -1S
16
25
45
65
85
105 125
1.0
0.5
DIFFERENTIAL INPUT VOLTAGE _ mV
Supply Current as a
Function of Temperature
Leakage Current as a
Function of Temperature
10 '
Vs=±1SV
07
-0.5
-1.0
TEMPERATURE _ "C
V
Output Saturation Voltage
as a Function of
Output Current
Vs
+15V
7"
.... ; /
~06
-"""V
.v
w
~ 05
\A''\
OUTPUT
10
-
o
I
I
20
-16 -12
TA = 25"C
I
~20
I--
v; : aJv
I
40
~
-
04
:!l: 40
{
>
-
w
iii
~ 60
RL = 1 kG
V++=50V
50
"o '!.:,..
"z~
"oo 02
Q
OUT~UT ';:: -~
N01RMAi
0.5
ffi
~
60
~~=~~~~g[~AGES -
>
I
~ 140
~
Output Voltage as a
Function of
Differential Input Voltage
Common Mode Limits as a
Function of Temperature
-
T A "" - 55"C
~O.4
~
4~~.J-/C;/#;;?''-f-+-.-J_--I
v
10- 8
...
UT=50V/
ffi
a~
/' /"
~03~+'~~·~···-+-+-4--+-+-+-~
"'.
r--~
~02 ..Ll'~TA: 25'C'-+-+--1-+--1
lO-
w
/'
"
/'
V'N
";:2
~
~10-1 0
15V
./
0.1 f'..7.'+-+--1-+-+--1--+-+--+--1
OL-~_L-~~~~~
20
10
30
OUTPUT CURRENT -
50
40
__k--L~
-55 -35 -15
10- 1
,V
25
105125
'5
45
TEMPERATURE _ °C
rnA
105
65
125
TEMPERATURE _ °C
Typical Performance Curves for J.LA311
Input Bias Current as a
Function of Temperature
500
~ 400
I--
...zI
w 300
§
o
'"~ 200
...=>
-
Input Offset Current as a
Function of Temperature
V~: ,;5VI
RAISEO*-
r-
-
10
.,~
NORMAL
10
20
30
40
50
TEMPERATURE
• Pins 5, 6 and 8 are shorted.
60
70
--
1
, , 5V_
'E
~
i-- r--
i
o~
I
.,...
I--
..
z
w
NORMAL
~
30
40
50
TEMPERATURE _ °C
• Pons 5, 6 and 8 are shorted.
5-36
60
70
+,
M(XIMUM
TYPICAL
1
~
0
i
/
10
~
20
25°C
g
51
10
TA
1
w
RAl;:-
ffi
"'
""'ol:i:i
Vsl :
I'---
"li
~
z
100
'-..
...I
~
o
o
0
o
- 100
Offset Voltage as a
Function of Input Resistance
, I
1
10k
I1111 IT vOl +1 iWi
I
100 k
1M
INPUT RESISTANCE -
10M
n
1LA 111 • 1LA311
Typical Performance Curves for IlA311 (Cont.)
Input Bias Current as a
Function of
Differential Input Voltage
20
~17 5
~
!
~ 12 5
0
10
iii
~
,
5
" ''';'''''-i =
::;
"~
"o
:
I
i
I
0
-8
04
10
12
-4
o
16
10
"0
~
--
5
c-+- -+-
~
-
02
--
--;:/ V
-;7
-
--
tt
t
i/
01
o
o
,
10
l-30
20
-
40
OUTPUT CURRENT -
~10
70
ac
'\
~~~TP:Tl~:UT
'"I
I-
<.>
~ f=-
"'" ,
F=
c-~
I
30
40
50
f---
~
10
20
TEMPERATURE _
rnA
60
70
-~~
::.:: 10--\
;
,f--~
25
35
ac
-
45
=
55
TEMPERTURE _ °C
Strobe Circuit
3 kll ____ v+
~~.N'-
TTL
STROBE
1 kll
STROBING
OFFSET BALANCING
5-37
-=-
-
-- - - -
Typical Applications
Offset Null Circuit
~
INPUTVIN = 15V- -
w
10-1
50
-
=- ==
ffi
I
10
mV
V
./
10- ,
POSITIVE SUPPLY
NEGATIVE SUPPLY
40V
1---
~- 1----
pur HIGH
05
10--8
-
°r
I
~05
Leakage Currents as a
Function of Temperature
I
--
1'\
I '\
I
DIFFERENTIAL INPUT VOL TAGE -
L
- f- I--:-- - -I---
/I
60
Vs= ;r15V
'/
-
~o 3
~
SO
TA = 25°C
./'
>0 4
o
40
Supply Current as a
Function of Temperature
./'
o
Z
30
10
-!-
w
20
TEMPERATURE _
Saturation Voltage as a
Function of Current
>
I
I
V++=40V
t\.
<.>
,
•
"-
RL = soon
o
DIFFERENTIAL INPUT VOLTAGE - 'Ii
7
EMITTER
FOLLOWER
~ 20 OUTPUT
~
~
2
i
30
'""
~
-16 -'12
I 06
g
-RL = lkO
(
If ,
If
;:"
,,""-
r-
NORMAL OUTPUT
I 40
w
,
o
z
I
1 1
I--
>
I
i"~ 10
i
c~
!
= 30V
TA = 25°C
w
•
5
I-- Vs
50
5
>
I
:
., 0H- W.
7
~O
:
!
I
60
:~~~~~~g[~AGES -
Vs = :t15V
TA == 2S O C
,
150
ffi
~
+
:~
22
Output Voltage as a
Function of
Differential Input Voltage
Common Mode Limits as a
Function of Temperature
75
•
}LA 111 • }LA311
Typical Applications (Cont.)
Zero Crossing Detector
Driving MOS Logic
Increasing Input Stage Current'
r-........--v+
R2
3 k
v+ ~ 5 V
INPUT
8
7
TO
MOS
R3 LOGIC
10 k
4
-=-
-10 V
-=-
+15 V
Rl
~ 5 V
~
Negative Peak Detector
Adjustable Low Voltage
Reference Supply
v+
v-
'Solid tantalum
Note
'Increases typical common mode slew rate from
7.0 V//LS to 18 V//Ls.
R4
--1r--....--'W.......---1r-",/V'..---,
3.9 k
500
OUTPUT
R310 k
INPUT-vvv-.......
Rl
2 k
VOUT
-15 V
2N3904
'Solid tantalum
Digital Transmission Isolator
V+
R2
1 k
Cl
1.5
V+
~F
~
~
5.0 V
5 V
R5
R6
1 k
5 k
2
'Solid tantalum
Positive Peak Detector
TTL
OUTPUT
+15 V
Rl
100
I
FROM
TTL
GATE
INPUT
-15
v--<__......
'Solid tantalum
5·38
lk
#LA 111 • #LA311
Relay Driver with Strobe
Typical Applications (Cont.)
V++
Strobing of Both Input
And Output Stages
FROM D/A NETWORK
TTL
STROBE
Rl
1 k
TTL STROBE
• Typical input current is 50 pA
with Inputs strobed off.
• Absorbs Inductive kickback of relay
and protects Ie from severe voltage
transients on V++ line.
Precision Photodiode Comparator
Switching Power Amplifier
Rl
,---~----~~------'----'-+5V
INPUT
3.9 k
Rl
~PT100
R3
Ql
~~VV~
10 k
__~ 2N6125
1 k
3
R2 V-
TTL
OUTPUT
R3 100 k
-=-
OUTPUT
100 k
R2'
25 k
R4
47
• R2 sets the comparison level.
At companson, the photodlode has
less than 5 mV across It, decreasing
leakages by an order of magnitude
~----~----~~~V-
Switching Power Amplifier
JOI
R1620
",2N6125
OUTPUT
.-
R2
620
8 7
r l
R3
620
"::r
~(,
R4
300 k
R5
510
R6
39 k
R12
620
I
I
I
3 6
11~
v+
02~
2N6125
1
Rll
620
...-,
6'3
7 8 ......_
~111~
RIO
620
112
R13
300 k
R9
39 k
R14
510
R8
15 k
INPUT
if
1 pF
022
R7
15 k
5-39
REFERENCE
•
f.lA 139 - f.lA239 - f.lA339
f.lA2901-f.lA3302
FAIRCHILO
A Schlumberger Company
Quad Comparators
Linear Products
Description
The J.LA 139 series consists of four independent
precision voltage comparators designed specifically
to operate from a single power supply. Operation from
split power supplies is also possible and the low
power supply current drain is independent of the
supply voltage range. Darlington connected pnp input
stages allow the input common-mode voltage to
include ground.
•
•
•
•
•
•
•
•
Connection Diagram
14-Pin DIP
...--------.14
OUTPUT 2
OUTPUT 3
OUTPUT 1
OUTPUT 4
v+
SINGLE SUPPLY OPERATION +2.0 V TO +36 V
DUAL SUPPLY OPERATION ± 1.0 V TO ± 18 V
ALLOW COMPARISON OF VOLTAGES NEAR
GROUND POTENTIAL
LOW CURRENT DRAIN 800 J.LA TYP
COMPATIBLE WITH ALL FORMS OF LOGIC
LOW INPUT BIAS CURRENT 25 nA TYP
LOW INPUT OFFSET CURRENT ± 5 nA TYP
LOW OFFSET VOLTAGE ±2 mV
Schematic Diagram
GND
INPUT 1-
INPUT 4+
INPUT 1+
INPUT 4-
INPUT 2-
INPUT 3+
INPUT 2+
INPUT 3-
(Top View)
Order Information
Type
Package
J.LA 139A
Ceramic DIP
J.LA139
Ceramic DIP
J.LA239A
Ceramic DIP
J.LA239A
Molded DIP
J.LA239
Ceramic DIP
J.LA239
Molded DIP
J.LA339A
Ceramic DIP
J.LA339A
Molded DIP
J.LA339
Ceramic DIP
J.LA339
Molded DIP
J.LA290 1
Ceramic DIP
J.LA290 1
Molded DIP
J.LA3302
Ceramic DIP
J.LA3302
Molded DIP
-INPUT
OUTPUT
5-40
Code
6A
6A
6A
9A
6A
9A
6A
9A
6A
9A
6A
9A
6A
9A
Part No.
J.LA139ADM
J.LA139DM
J.LA239ADC
J.LA239APC
J.LA239DC
J.LA239PC
J.LA339ADC
J.LA339APC
J.LA339DC
J.LA339PC
J.LA2901DC
J.LA2901PC
J.LA3302DC
J.LA3302PC
J.LA 139 Series· J.LA290 1 • J.LA3302
Absolute Maximum Ratings
ILA139/ILA239/ILA339
ILA139A/ILA239A/ILA339A
ILA2901
Supply Voltage, v+
Differential Input Voltage
Input Voltage Range
Power Dissipation (Note 1) 9A, 6A
Output Short Circuit to GND, (Note 2)
Input Current (VIN < -0.3 V), (Note 3)
Operating Temperature Range
ILA339,ILA339A
ILA239,ILA239A
ILA139,ILA139A
ILA2901,ILA3302
Storage Temperature Range
Pin Temperature (Soldering)
Ceramic DIP (60 s)
Molded DIP (10 s)
36 V or ± 18 V
36 V
-0.3 V to +36 V
1W
Continuous
50 mA
ILA3302
28 V or ± 14 V
28 V
-0.3 V to +28 V
1W
Continuous
50mA
O°C to +70°C
-25°C to +85°C
-55°C to +125°C
-40°C to +85°C
-65°C to +150°C
•
Factors Important to Maximum Ratings and
Electrical Characteristics
Notes
1. For operating at high temperatures, the /LA339/ /LA339A,
/LA2901, IlA3302 must be derated based on a 125'e
maximum Junction temperature and a thermal resistance of
125'e/W which applies for the device soldered on a printed
circuit board, operating on a still air ambient The /LA 139 and
IlA 139A must be derated based on a 150' e maximum junction
temperature. The low bias dissipation and the "ON-OFF"
characterostlc of the outputs keeps the chip dlsslpatoon very
small (PO :oS 100 mW), provided the output transistors are
allowed to saturate.
2. Short circuits from the output to V+ can cause excessive
heating and eventual destruction. The maximum output
current IS approximately 20 mA independent of the
magnitude of V+
5
6
7
3. This onput current will exist only when the voltage at any of the
Input leads is droven negative. It is due to the collector-base
Junction of the Input pnp transistors becomong forward biased
and thereby acting as input diode clamps. In addition to diode
action, there is also lateral npn parasitic transistor action on
the Ie chip. This transistor action can cause the output
voltages of the comparators to go to the V+ voltage level or
to ground for a large over-drive, for the time duration that an
onput IS droven negative. This IS not destructove and normal
output states will reestablish when the input voltage, which IS
negative, again returns to a value greater than -0.3 V.
4. These specifications apply for V+ = 5.0 V and
-55'e:oS TA:oS +125'e, unless otherwise stated. With the
/LA239 / /LA239A, all temperature specifications are limited to
8
9
10
5-41
-25'e:oS TA:oS +85'e, the IlA339//LA339A temperature
specifications are limited to o'e :oS TA :oS -70'e, and the
IlA290 I, /LA3302 temperature range is
-40'e:oS TA:oS +85'e.
The direct lOP of the input current IS out of the Ie due to the
pnp onput stage. This current IS essentoally constant,
independent of the state of the output so no loading change
eXists on the reference or input lines.
The Input common-mode voltage or either Input signal voltage
should not be allowed to go negative by more than 0.3 V. The
upper end of the common-mode voltage range IS V+ - 1 5 V,
but either or both onputs can go to +30 V without damage.
The response time specified is for a 100 mV input step With
5 mV overdrive. For larger overdrive signals 300 ns can be
obtained; see typical performance characterostics section
Positive excursions of onput voltage may exceed the power
supply level. As long as the other voltage remains Within the
common-mode range, comparator will provide a proper output
state. The low input voltage state must not be less than
-0.3 V or 0.3 V below the magnitude of the negative power
supply, If used.
At output sWitch point, Vo "" 1.4 V, RS = 0!1 with V+ from
5 V; and over the full input common-mode range
OVtoV+-15V.
For onput signals that exceed Vee, only the overdriven
comparator is affected. With a 5 V supply, VIN should be
limited to 25 V maximum and a limiting resistor should be
used on all inputs that might exceed the positive supply
JLA 139 Series· JLA2901 • JLA3302
Electrical Characteristics
Characteristic
V+ = 5 V
(Note 4)
Condition
/LA139A
Min Typ
Input Offset Voltage TA = 25°C (Note 9)
Input Bias Current
IIN(+) or IIN(-) with
Output in Linear Range.
TA = 25°C (Note 5)
Supply Current
/LA239A,/LA339A
Min Typ Max
± 1.0 ±2.0
25
Input Offset Current IIN(+) - IIN(-).
TA = 25°C
Input Common-Mode TA = 25°C
(Note 6)
Voltage Range
Max
100
±5.0 ±25
RL = 00 on all
Comparators.
TA = 25°C
0.8
±2.0 ±5.0
25
25
250
±5.0 ±50
2.0
Max
± 1.0 ±2.0
V+ -1.5 0
0
/LA139
Min Typ
±5.0 ±25
V+ -1.5 0
0.8
100
2.0
Unit
mV
nA
nA
V+-1.5 V
0.8
2.0
mA
RL = 00. V+ = 30 V.
TA = 25°C
Voltage Gain
Large Signal
Response Time
Response Time
RL ~ 15 kfl.
V+ = 15 V. (To
Support Large Vo
Swing) TA = 25°C
50
200
50
200
200
V/mV
VIN = TTL Logic Swing.
Vref = 1.4 V.
VRL = 5.0 V.
RL = 5.1 kfl.
TA = 25°C
300
300
300
ns
VRL = 5.0 V.
RL = 5.1 kfl.
TA = 25°C (Note 7)
1.3
1.3
1.3
/Ls
Output Sink Current VIN(-) ~ 1.0 V.
6.0 16
VIN(+) = O.
VO:::; 1.5 V. TA = 25°C
Saturation Voltage VIN(-) ~ 1.0 V.
VIN(+) = O.
250
ISINK :::; 4.0 mAo
TA=25°C
VIN(+) ~ 1.0 V.
VIN(-) = O.
Vo = 30 V.
TA=25°C
Input Offset Voltage (Note 9)
Output Leakage
Current
6.0 16
400
250
6.0 16
400
250
mA
400
mV
200
200
200
nA
4.0
4.0
9.0
mV
± 100
± 150
± 100
nA
300
400
300
nA
V+ -2.0 0
V+ -2.0 0
V+ -2.0 V
VIN(-) ~ 1.0 V.
VIN(+) = O.
ISINK:::; 4 mA
700
700
700
mV
Output Leakage
Current
VIN(-) ~ 1.0 V.
VIN(+) = O.
Vo = 30 V
1.0
1.0
1.0
/LA
Differential Input
Voltage
Keep all VINs ~ 0 V
(or V-. if used)
(Note 8)
V+
V+
36
V
Input Offset Current IIN(+) - IIN(-)
Input Bias Current
IIN(+) or IIN(-)
with Output in
Linear Range
Input Common-Mode
Voltage Range
Saturation Voltage
0
Notes on following page
5-42
~A 139 Series • ~A2901 • ~A3302
Electrical Characteristics
Characteristic
V+ = 5 V
(Note 4)
Condition
.uA239,.uA339
Min Typ Max
Input Offset Voltage TA = 25°C (Note 9)
Input Bias Current
IIN( +) or IIN( _) with
Output in Linear Range,
TA = 25°C (Note 5)
Input Offset Current IIN(+) - IIN(-),
TA = 25°C
Input Common-Mode TA = 25°C
(Note 6)
Voltage Range
Supply Current
.uA2901
Min Typ
Large Signal
Response Time
Response Time
Output Sink Current
Saturation Voltage
mV
25
25
25
nA
250
Rl ~ 15 kf!,
V+ = 15 V, To
Support Large Vo
Swing, T A = 25°C
200
VIN = TTL Logic
Swing, Vref = 1.4 V,
VRl = 5.0 V,
Rl = 5.1 kf!,
TA = 25°C
300
VRl = 5.0 V,
Rl = 5.1 kf!,
TA = 25°C (Note 7)
1.3
2.0
25
VIN(-) ~ 1.0 V,
6.0 16
VIN(+) = 0,
VO::S 1.5 V, TA = 25°C
250
VIN(+) ~ 1.0 V,
VIN(-) = 0,
Vo = 30 V,
TA = 25°C
Input Offset Voltage (Note 9)
Input Offset Current IINC+) - IINC-)
Input Bias Current
IIN(+) or IIN(-)
with Output in
Linear Range
Input Common-Mode
Voltage Range
0
250
±5.0 ±50
V+ -1.5 0
0.8
Output Leakage
Current
Unit
±3.0 ±20
0
VIN(-) ~ 1.0 V,
VIN(+) = 0,
ISINK ::S 4.0 mA,
TA=25°C
Max
±2.0 ±7.0
Rl = 00, V+ = 30 V,
TA = 25°C
Voltage Gain
.uA3302
Min Typ
±2.0 ±5.0
±5.0 ±50
Rl = 00 on all
Comparators,
TA=25°C
Max
±5.0 ± 100
V+ -1.5 0
0.8
2.0
1.0
2.5
100
500
V+ -1.5 V
0.8
2
nA
2.0
mA
30
V/mV
300
300
ns
1.3
1.3
.uS
6.0 16
2.0 16
400
400
200
200
250
mA
500
mV
200
nA
9.0
9.0
15
40
mV
± 150
50
200
300
nA
400
200
500
1000
nA
V+ -2.0 0
V+ -2.0 V
700
700
mV
V+ -2.0 0
VIN(-) ~ 1.0 V,
VIN(+) = 0,
ISINK ::S 4 mA
700
Output Leakage
Current
VIN(-) ~ 1.0 V,
VIN(+) = 0,
Vo = 30
1.0
1.0
1.0
.u A
Differential Input
Voltage
Keep all VINs ~ 0 V
(or V-, if used)
(Note 8)
36
V+
V+
V
Saturation Voltage
Notes on following page
5-43
400
•
p,A 139 Series • p,A290 1 • p,A3302
Typical Performance Curves for p,A 139/ p,A239/ p,A339/ p,A 139A, p,A239A/ p,A339A/ p,A3302
--
0
.
,.08
E
,;-
1
~
0
:::i
04
/
o.,
.;-
a
~
'/
I--
80
TA-55°C
-- -
Tl
+'r c -
I
13
~
o
40
~
2
RL='"
1--;:; o,J
o~1
40
0
i'"
.0
+
100 mV
0
0
0
1
'~"=
20mV
0
>
40
T~
30
>1
~a
5~
VOUT-
-
\.
,..
~E
""
"0
~I
»
0
Ty 25ic
-100
10
~T:'+f~'t-
10
15
20
o.
~
20
10
r
I
~
"i
1
o
J
VIN
-50 -100
-r T
2
05
c -
-
I
~"
-
VOUT
I
10
TIME-iiS
5-44
15
r,
0Tr +2S C
o
o
01
10
10
lo-OUTPUT SINK CURRENT-rnA
n
+
TAi-S50C-
C'if7
1%:/
001
/srnv
I
I
0
~
/~ V
h~
'i".
> 000
II
/20mV
1
00
"
40
30
20
INPUT OVERDRIVE = 100 mV
1"
~6
05
~
Response Time for Various
Input Overdrives-Positive
Transition
50 mV = INPUT OVERDRIVE
"5V 1
1
o
V-I--SUPPlY VOlTAGE-V
0
0
~
+1j5 0 C
SUPPLY VOlTAGE-V
1
TAT-t125~
~
I
o
o
0
0
z
o
~
I
Response Time for Various
Input Overdrives-Negative
Transition
10
>
TA--55°C
~
z
I
I
30
.
w
80
I'
-=t +1JsoC
20
0
1
n
~
..
I
-:tI]
-+7~OC_
/'"
>
VIN(CM)= OV
RIN(CM)"=109
-t:1 J-
I-I--
10
Output Saturation Voltage
Input Current
Supply Current
20
7""
100
itA 139 Series • ItA2901 • ItA3302
Typical Performance Curves for ILA2901
Supply Current
Input Current
Output Saturation Voltage
80
RL
V
"
1
10
0-
~
"0"
~
~
./'
/"
08
-
V
I-
./
f-"""
/
10
1
"
1
~+2JOC~
......-
06
TA
I
-t~o,~
//-
E
>
""-;A-C-40°C
/
=."
12
II
I
1
l
'"
~
TA
-
'0
o
40
r-
0
5 0 mV -" INPUT OVERDRIVE
>
>1
T~
~~
g~
>~
0-0-
0.0
""
001
40
20
10
0
100
+5V 1
.~
.
20mV
30
+:
mv\
\
»
0
I
TA
15
_I850CL
"o
TA
....
0
-
0
0
-= 25JC
~I
I
, 0
Ij
~
0-
30
40
~1
oo
11
05
/
~r
,aV
"'
~V
~V
.
~
T~-O°C
iA=-rO
C -
r--
~
/SrnV
I
/20mV
I
II
1
1+50v
_
..~.,
J
VOUT
I-- t-
10
TIME-l1s
5-45
001
01
10
OUTPUT SINK CURRENT -
100
rnA
•
I
(I
r
-T'YC
~
001
10 -
+
50 e-----
T;= +2SbC",,-
1
~~
o
> 000
'0
"N
~TA=+85°C
0-
1
INPUT aVERlJRIVE = 100 mV
0
1
10
Tj: f--
0
1
0
50
05
;::
~
Response Time for Various
Input Overdrives-Positive
Transition
I ;..
~100
COC
/.
1
~
z
o
"
S
10
VOUT -
1 ~
~6
;"
V+-SUPPLY VOLTAGE-V
Response Time for Various
Input Overdrives-Negative
Transition
1
I
I
I
o
V+ - SUPPLY VOLTAGE - V
0
w
40
~
z
I
I
~
"0
0-
-r:-e+8;'C
20
60
0
1
-'40°C
I
I
15
, 0
J.tA 139 Series • J.tA290 1 • J.tA3302
Application Information
Typical Applications (V+
The /-LA 139 series are high-gain, wide-bandwidth
devices which, like most comparators, can easily
oscillate if Ihe output lead is inadvertently allowed to
capacitively couple to the inputs via stray
capacitance. This shows up only during the output
voltage transition intervals as the comparator
changes slates. Power supply bypassing is not
required to solve this problem. Standard pc board
layout is helpful as it reduces stray input-output
coupling. Reducing Ihe inpul resistors 10 < 10 k!1
reduces the feedback signal levels and finally, adding
even a small amount (1.0 to 10 mY) of positive
feedback (hysteresis) causes such a rapid transition
that oscillations due to stray feedback are not
possible. Simply socketing the IC and attaching
resistors 10 the pins will cause input / output
oscillations during the small transition intervals unless
hysteresis is used. If the input signal is a pulse
waveform, with relatively fast rise and fall times,
hysteresis is not required.
AND Gate
= 15 V)
V+
30k
100k
100 k
B-Wv-_-......--I
100k
C~\IVI.---'
v;::r
"0" "1"
OR Gate
V+
200 k
All pins of any unused comparators should
be grounded.
3.0 k
100 k
A
100 k
The bias network of the /-LA 139 series establishes a
drain current which is independent of the magnitude of
the power supply voltage over the range of
2 V to 30 V.
B
100 k
C
v~:r
-=
"0" "1"
It is usually unnecessary to use a bypass capacitor
across the power supply line.
Monostable Multivibrator
V+
The differential input voltage may be larger than V+
with:>ut damaging the device. Protection should be
provided to prevent the input voltages from going
more negative than -0.3 V (at 25°C). An input
clamp diode can be used as shown in the
applications section.
ol ---j f-....--...4----i
10 k
100pF
PW
1ms _ _--V+
to
~
+VIN
to tt
1N914
The output of the /-LA 139 series is the uncommitted
collector of a grounded-emitter npn output transistor.
Many collectors can be tied together to provide wiredOR output function. An output pull-up resistor can be
connected to any available power supply voltage
within the permitted supply voltage range and there is
no restriction on this voltage due to the magnitude of
the voltage which is applied to the V+ terminal of the
/-LA 139 package. The output can also be used as a
simple SP / ST switch to ground (when a pull-up
resistor is not used). The amount of current which the
output device can sink is limited by the drive available
(which is independent of V+) and the (J of this device.
When the maximum current limit is reached
(approximately 16 mAl, the output transistor will come
out of saturation and the output voltage will rise very
rapidly. The output saturation voltage is limited by the
approximately 60 !1 saturation resistance of the output
transistor. The low offset voltage of the output
transistor (1 mY) allows the output to clamp
essentially to ground level for small load currents.
Vo
0.001 F
1.0M
Bistable Multivibrator
V+
15k
100k
51k
V+:::rL
o
5-46
100k
R--~~~--~
Vo
o
J,LA 139 Series • J,LA290 1 • J,LA3302
Typical Applications (V+ = 15 V) (Con!.)
Monostable Multivibrator with Input Lock-Out
V+
15 k
1.0M
100 k
40}J.S~+
-fEo "s
+4V
to 11
1
Vo
240 k
62 k
Time Delay Generator
V+
10 k
15 k
3.0 k
200 k
10 M
10 k
V03
Vo+::,rV3
to
13
51 k
INPUT GATING
SIGNAL
VC1
10 k
10 k
V02
Vo+::r-
to 12
3.0 k
51 k
v+
10 M
----------",-.;a-
10 k
t
v;::r
Vet
10 11
I
V01
V,
-1--
51 k
5-47
•
p,A 139 Series • p,A290 1 • p,A3302
Typical Applications (V+ = 15 V) (Cont.)
Wired-OR Outputs
Squarewave Oscillator
V+
V+
4.3 k
3.0 k
100 k
f=100kHz
Vo
Vo
100 k
Large Fan-In AND Gate
V+
3.0 k
lOOk
10 k
VOUT
Pulse Generator
A
V+
B--KI---
>=
-=;:A
+125° C
rT
•o
40
"""-.
10
TA.=+25°C
r+tt-
20
30
I
.m
I
o
>.00
~ '/
,t%V
40
om
h~
1(=-55O~_
I
"TA= f-25°C
0'
'0
'00
la-OUTPUT SINK CURRENT-mA
V+ -SUPPLY VOLTAGE_V
SUPPLY VOLTAGE- Y
~7
~~
5
z
20
TA-+125°~
iI! •,
1
I-
,-
'0
!l
a:
.
'0
I
R(NleMI '" 109 I!
I
~
30
>
VINICMI-=
1
"L •
20
Output Saturation Voltage
.
.
a . _,Tw1
T
I
I
,.
••
55°C
{TI wti-'T
,.. .....I~
8/
JLA 193/293/393
Typical Performance Curves for I'A2903
Supply Current
·
......-
,,-
,- ......-
,,-
8
~---4O"C
V
RL "" ...
2
-
I I
l-t+J.c-
~ !--
-
,.""
V
1
I
!Zw
I,...- ~~wJ
r I
I I
I,...-
6
Output Saturation Voltage
Input Current
20
a:
a:
u
:>
i
..
..
..
TA
TAr:
--
20
~
.
y- -SUPPLY VOLTAGE-V
ii! • ,
T,
,.
o
o
-,85'c
I
5
I-
~
1
20
..
30
Typical Performance Curves For All Devices
•
•
•
•
•
•
•,...
50 mY = INPUT OVERDRIVE
I
+s. I
Response Time for Various
Input Overdrives
Positive Transition
I
0
I
~.. =
20m.
YOUT -
100m.
-
I I .,.
-'00
.s
,.
TIME-p.I
I I
T}~2SJC
-I -I
,s
2..
•
..
•
•
0
0
INPUT OVERDRIVE'" 100 mY
~
Hom.
I I
"" L
""I I
J
SmY
I~;
J
YIN
-100
r- r-Ti' e
05
I
n
I
r
- r-
,.
TIME-p..
5-53
-
+.".
YOUT
I I I
15
TA=+25°C
~
~V
V
..,a: .,
>.om
10 -
V+ -SUPPLY YOLTAGE- V
Response Time for Various
Input Overctrives
Negative Transition
~ .m
5
/
I
o
/.
r--;rA = +,8So C
l-
:>
30
•
,
~
TA-O·C
.
f-T!:- ,J'e
I I
~
I
I
I-
iI!
I
>
I
-4Q°C
2.
lO ~
\0.
~
~
&V
r
T~""O°C
TA-=-r Cr-- 10
OUTPUT SINK CURRENT - mA
'00
JLA 193/293/393 • JLA2903
The differential input voltage may be larger than V+
without damaging the device. Protection should be
provided to prevent the input voltages from going
negative more than -0.3 V (at 25°C). An input
clamp diode can be used as shown in the
applications section.
Application Information
The itA 193 series are high-gain, wide-bandwidth
devices which, like most comparators, can easily
oscillate if the output lead is inadvertently allowed to
capacitively couple to the inputs via stray
capacitance. This shows up only during the output
voltage transition intervals as the comparator
changes states. Power supply bypassing is not
required to solve this problem. Standard pc board
layout is helpful as it reduces stray input-output
coupling. Reducing the input resistors to less than
10 kQ reduces the feedback signal levels and finally,
adding even a small amount (1.0 to 10 mY) of positive
feedback (hysteresis) causes such a rapid transition
that oscillations due to stray feedback are not
possible. Simply socketing the IC and attaching
resistors to the pins will cause input-output
oscillations during the small transition intervals unless
hysteresis is used. If the input signal is a pulse
waveform, with relatively fast rise and fall times,
hysteresis is not required. All pins of any unused
omparators should be grounded.
The output of the itA 193 series is the uncommitted
collector of a grounded-emitter npn output transistor.
Many collectors can be tied together to provide an
output ORing function. An output pull-up resistor can
be connected to any available power supply voltage
within the permitted supply voltage range and there is
no restriction on this voltage due to the magnitude of
the voltage which is applied to the V+ terminal of the
itA 193 package. The output can also be used as a
simple SPST switch to ground (when a pull-up resistor
is not used). The amount of current which the output
device can sink is limited by the drive available (which
is independent of V+) and the {J of this device. When
the maximum current limit is reached (approximately
16 rnA), the output transistor will come out of
saturation and the output voltage will rise very rapidly.
The output saturation voltage is limited by the
approximately 60 Q saturation resistance of the output
transistor. The low offset voltage of the output
transistor (1 mY) allows the output to clamp
essentially to ground level for small load currents.
The bias network of the itA 193 series establishes a
drain current which is independent of the magnitude of
the power supply voltage over the range of from 2 V
to 30 V. It is unnecessary to use a bypass capacitor
across the power supply line.
Typical Applications (V+ = 15 V)
Bi-Stable Multivibrator
One-Shot Multivibrator
V+
V+
ol --jf--___.......--1
10k
100pF
to
15k
PW
_ --V+
;:fE:
1 ms-.
~VIN
to
1N914
tt
o
V~:.:rL
s
100 k
5
..rt:o
-'VV'v-li-......-j
R
Va
V+=n..
o
0001 F
10M
1N914
5-54
R
100k
-""","v-<~-~
Vo
15V
I=AIRCHILO
A Schlumberger Company
6-2
JLA9614
Dual Differential
Line Driver
FAIRCHILD
A Schlumberger Company
Interface Products
Connection Diagram
16-Pin DIP
Description
The JLA9614 is a TTL compatible Dual Differential Line
Driver. It is designed to drive transmission lines either
differentially or single-ended, back-matched or
terminated. The outputs are similar to TTL, with the
active pull-up and the pull-down split and brought out
to adjacent pins. This allows multiplex operation
(Wired-OR) at the driving site in either the singleended mode via the uncommitted collector, or in the
differential mode by use of the active pull-ups on one
side and the uncommitted collectors on the other (See
Applications). The active pull-up is short-circuit
protected and offers a low output impedance to allow
back-matching. The two pairs of outputs are
complementary, providing NAND and AND functions of
the inputs and adding greater flexibility. The input and
output levels are TTL compatible with clamp diodes
provided at both input and output to handle line
transients.
ACTIVE
PULL UP AI
OUT AI
OUTA2
ACTIVE
PULL UP A2
12 ACTIVE
PULL UP Bl
INAI
INA2
IN B3
INA3
IN B2
GND
IN Bl
(Top View)
Order Information
Type
Package
JLA9614
Ceramic DIP
JLA9614C
Ceramic DIP
JLA9614C
Molded DIP
• SINGLE 5 V SUPPLY
• TTL COMPATIBLE INPUTS
• OUTPUT SHORT CIRCUIT PROTECTION
• INPUT CLAMP DIODES
• OUTPUT CLAMP DIODES FOR TERMINATION OF
LINE TRANSIENTS
• COMPLEMENTARY OUTPUTS FOR NAND AND
OPERATION
• UNCOMMITTED COLLECTOR OUTPUTS FOR
WIRED-OR APPLICATION
• MILITARY TEMPERATURE RANGE
Absolute Maximum Ratings
(above which the useful life may be impaired)
Storage Temperature Range
-65° C to + 150° C
Vee Pin Potential to Ground Pin -0.7 V to +7.0 V
-0.5 V to +5.5 V
Input Voltage
Voltage Supplied to Outputs
(Open Collector)
-0.5 V to +12 V
Pin Temperature
Ceramic DIP, Flatpak
(Soldering, 60 s)
300°C
Molded DIP (Soldering, 10 s)
260°C
Internal Power Dissipation (Note) 670mW
Operating Temperature Range
Military (JLA9614)
-55°Cto +125°C
Commercial (JLA9614C)
0° C to +70° C
Note
For Ceramic DIP, rating applies to ambient temperatures up to
70· C, above 70· C derate linearly at 8.3 mW /. C. For the
Flatpak, derate linearly at 7 1 mW /. C above 60· C.
6·3
Code
68
68
98
Part No_
JLA9614DM
JLA9614DC
JLA9614PC
•
p,A9614
Equivalent Circuit (1 /2 of circuit)
r-~t-~t-~t-----~t-----~t-~t-~t-------t-----------t---t-----------t----1~---16
Vee
R19
540
01
025
t-----<024
C4
03
R22
4k
ACTIVE
PULL UP 12, 4------....-
....- - - - - '
R23
OUTPUT 1 3 , 3 - - -....- - ,
10
C3
02
R1
R16
4k
Uk
' - - - - 4 > - - - + - 1 , 15 ACTIVE
PULL UP
...---9'-2,14 OUTPUT
04
R21
1k
9,5-----------1___________J
-+___+ __--+
INPUTS 10,
11,76----------i------1------I
_____
Jr------~--~1-~r-----------------------~
":"
6·4
}
TOOTHER
DRIVER
~A9614
!LA9614
Electrical Characteristics
Vee = 5.0 V +
- 10%.
-55°C
Symbol
Characteristic
VOL
Output LOW Voltage
VOH1
Output HIGH Voltage
VOH2
Min
+25°C
Max
Min
400
+125°C
Typ
Max
200
400
Min
Max
Unit
Condition
400
mV
IOL = 40 mA
Vee = 4.5 V
2.4
2.4
3.2
2.4
V
2.0
2.0
2.6
2.0
V
-40
-90
-120
10
100
Ise
Output Short Circuit
Current
leEX
Output Leakage Current
IF
Input Forward Current
IR
Input Reverse Current
VIL
Input LOW Voltage
VIH
Input HIGH Voltage
VOLe
Clamped Output
LOW Voltage
-0.8
lee
Supply Current
Imax
-1.60
0.8
200
IOH = -10 mA,
Vee = 4.5 V
IOH = -20 mA,
Vee = 4.5 V
mA
VOUT = 0.0 V
Vee = 5.5 V
!LA
VeEX = 12.0 V
Vee = 5.5 V
-1.10 -1.60
-1.60 mA
VF = 0.4 V
Vee = 5.5 V
35
60
100
!LA
VR = 4.5 V
Vee = 5.5 V
1.3
1.5
0.8
0.8
V
Vee = 5.5 V
V
Vee = 4.5 V
-1.5
V
IOLe = -40 mA
Vee = 5.5 V
34
50
mA
Supply Current
46
65
mA
tpLH
Turn-Off Time
14
20
ns
CL = 30 pF
Vee = 5.0 V
tpHL
Turn-On Time
18
20
ns
See AC Circuit
VM = 1.5 V
VeD
Input Clamp
Diode Voltage
V
Vee = 4.5 V
lie = -12 mA
2.0
2.0
-1.0
6-5
2.0
-1.5
Inputs = 0 V
Vee = 5.5 V
Inputs = 0 V
V max = 7.0 V
•
J,LA9614
!LA9614C
Electrical Characteristics
Vee = 5.0 V +
- 5%.
O"C
+25°C
Symbol
Characteristic
VOL
Output LOW Voltage
VOH1
Min
Output HIGH Voltage
VOH2
Max
Min
450
+75°C
Typ
Max
200
450
Min
Max
Unit
Condition
450
mV
IOL = 40 mA
Vee = 4.75 V
2.4
2.4
3.2
2.4
V
IOH = -10 mA,
Vee = 4.75 V
2.0
2.0
2.6
2.0
V
IOH = -40 mA,
Vee = 4.75 V
-40
-90
-120
mA
VOUT = 0.0 V
Vee = 5.25 V
10
100
!LA
VeEX = 5.25 V
Vee = 5.25 V
Ise
Output Short Circuit
Current
leEX
Output Leakage
Current
IF
Input Forward Current
IR
Input Reverse Current
VIL
Input LOW Voltage
VIH
Input HIGH Voltage
VOLe
Clamped Output
LOW Voltage
-0.8
-1.5
V
lee
Supply Current
33
50
mA
Imax
Supply Current
46
70
mA
tpLH
Turn-Off Time
14
30
ns
iPHL
Turn-On Time
18
30
ns
Veo
Input Clamp
Diode Voltage
-1.0
-1.5
V
-1.60
0.8
2.0
2.0
200
-1.10 -1.60
-1.60 mA
VF = 0.45 V
Vee = 5.25 V
35
60
100
/lA
VR = 4.5 V
Vee = 5.25 V
1.3
0.8
V
Vee
V
Vee = 4.75 V
1.5
0.8
2.0
= 5.25 V
IOLe = -40 mA
Vee = 5.25 V
Inputs = 0 V
Vee = 5.25
Inputs = 0 V
Vmax = 7.0 V
CL = 30 pF
Vee = 5.0 V
See AC Circuit
VM = 1.5 V
Vee = 4.75 V
lie = -12 mA
Typical Performance Curves
Active Pull Down Output
LOW Current vs
Output LOW Voltage
'00
TA - 25°C
1&
80
Vcc~5SV
~
Ycc=SOY
~
60
~
40
20
Active Pull-Up Output
HIGH Current vs
Output HIGH Voltage
35
~
vc1c
3.
.ffi
Vrc=45V
.'
, '"
01
0.2
25
~
~ -60 1---+--+--'\r-+-ft--M.~t--1
e
03
04
0.5
YOl-OUTPUTYOLTAGE-Y
06
07
-80
15
10
~
o
-
V~" N'o LdAO
5.V
~I-"
2.
~40
a:
a:
~
J
Logic Levels vs
Ambient Temperature
1---+--+--+--::;lE-7f-'7"4-t-"'l
-100 O!---,--"'-:.--,--,:':--....1,,.--:-L,--'--""
••
OUTPUT HIGH VOLTAGE _ V
6-6
.5
•
-60
VOL@loL'""'4OmA
I I
20
0
20
60
100
TA -AMBIENT TEMPERATUAE-" C
140
JLA9614
Typical Performance Curves (Cont.)
Supply Current vs
Supply Voltage
Supply Current vs
Temperature
60
Supply Current vs
Operating Frequency
40
NO LOAD
TA 25°C
1/
0
,$
.E 35
IL
o
o
~
40
~
30
~
I'
'060
10
80
Vee-SUPPLY VDLTAGE-V
20
100
60
>
30
~
~
g:
..
1
"g
1!
..
/'
20
IPHL
1-
10
0
60
TA-12S0C
40
T -'SOCT -
-
55~C
30
..::::
.
.-- ~v
~ 20
20
0
20
60
100
10
20
50
10
Transfer Characteristics vs
Supply Voltage
50;--,---r--,---,---r--,---,
Vee 55V
I..-> 40
V" 50V
~g 30
Vee 45V
1
0
§10
140
05
~ 20
0
~
~
>
TA-AMBIENTTEMPERATURE-OC
02
.it
::>
'"
'"
01
f-FREQUENCY-MHz
VCC-"'SOV
~
~
20
140
0
Z
b
V
:,....--'
o
0
20
Transfer Characteristics vs
Temperature
f
Q
40
T A-AMBIENT TEMPERATURE- 0 C
Propagation Delay Time vs
Temperature
j
i
::>
~25
60
/
60
G
r
I
'0
E
I
~
a
30pF"-
.. 80
It
::>
I
;
vee l lov
el
OUTPUTS OPEN
I
~~~
;
100
5L I
~
,J.."-,. "0
0
veJ
00~;0~5~~'~0::'lt51=j'=0==j'=5==3!0==3j5
YIN -INPUT VOLTAGE- V
6·7
10
°0~·0~5~·1~0"~'~5--'~0--~'~5--J3:0·--~35
YIN-INPUT YOLTAGE-V
•
~A9614
AC Test Circuit and Waveforms
Vee
Vee
16
8
51 !l
1
5%
-=-
-=-
I
VOUT
(A)
'oo"A'
I
HtPLH
tPHL
~rM----------------~
Inpul Pulse
Frequency = 500 kHz
Amphlude = 3.0 ± 0 1 V
Pulse Widlh = 110 ± 10 ns
Ir = I, ::s 5.0 ns
6-8
-=-
~A9614
Typical Applications
Differential Mode Expansion Multiplex Operation
+5 V
O<--------TWISTEO-PAIR L l N E - - - - - - - - -..
~1
100n
foll
..
•
10
3
SHIELD OR COMMON GROUND CONNECTION
11
Only one driver
IS
enabled at one time
Expand by tYing NAND active pull-down outputs together and by
tYing AND active pull-up outputs together. The drivers can be
inhibited by taking one Input to ground
Simplex -- Differential Operation
V
5:~CC-'16
1/2~1' ~
':3
DATA
INPurs
I_ _ _ _ _ _ _
I~wr,;-
L,IN_E_____________
___
P
SHIELD OR COMMON GROUND
CONNECTION
See /iA9615 data sheet for operation of /iA9615
Typical Reflection Diagram
.M
vL2.dv
25°C
TA
Ilol S~A)E du)pJ OL~E
=
~ 120
CHARACTERISTICS
I
a~
~
,
40
40
::>
II
:t
o
~
,£-120
cc
1j2~15
+
7
;
6
r
200
v
~TWISTED-PAIR~
HIGH STATE OUTPUT :>EVICE
CilAfjRT'iS1U
-'00
10
Your -OUTPUT VOLTAGE - V
See /i9621 data sheet for usage of reflection diagram
6-9
~2
1•
i
3
DATA
1 OUTPUT
,uA9615
Dual Differential
Line Receiver
F=AIRCHILO
A Sehlumberger Company
Interface Products
Connection Diagram
16-Pin DIP
Description
The 9615 is a Dual Differential Line Receiver designed
to receive differential digital data from transmission
lines and operate over the military and industrial
temperature ranges using a single 5 V supply. It can
receive differential data in the presence of high level
(± 15 V) common mode voltages and deliver
undisturbed TTL logic to the output.
The response time can be controlled by use of an
external capacitor. A strobe and a 130 \! terminating
resistor are provided at the inputs. The output has an
uncommitted collector with an active pull-up available
on an adjacent pin to allow either wire-OR or active
pull-up TTL output configuration.
•
•
•
•
•
•
•
•
vee
OUT A
ACTIVE
PULL UP A
STROBEA
OUTB
14 ACTIVE
PULL UP B
RESPA
STROBE B
A+
RESP B
B+
1300
A-
1300
'---~
GND
TTL COMPATIBLE OUTPUT
HIGH COMMON MODE VOLTAGE RANGE
CHOICE OF AN UNCOMMITTED COLLECTOR OR
ACTIVE PULL-UP
STROBE
FULL MILITARY TEMPERATURE RANGE
SINGLE 5 V SUPPLY VOLTAGES
FREQUENCY RESPONSE CONTROL
130 f! TERMINATING RESISTOR
I
B-
(Top View)
Order Information
Type
Package
",A9615
Ceramic DIP
",A9615C
Ceramic DIP
",A9615C
Molded DIP
Absolute Maximum Ratings
above which the useful
life may be impaired
Storage Temperature
-65°C to +150°C
Vee Pin Potential to Ground Pin
-0.5 V to +7.0 V
Input Voltage Referred to Ground
(Pins 5, 6, 7, 9, 10,11)
±20 V
Voltage Applied to Outputs for
HIGH output State without
Active Pull-Up
-0.5 V to +13.2 V
Voltage Applied to Strobe
-0.5 V to +5.5 V
Pin Temperature Range
Ceramic DIP, Flatpak
(Soldering, 60 s)
300°C
Molded DIP (Soldering, 10 s)
260°C
Internal Power Dissipation (Note) 670 mW
Operating Temperature Range
Military (9615)
-55°C to +125°C
Commercial (9615C)
O°C to +70°C
Note
For CeramIc DIP. rating applies to ambient temperatures up to
70°C; above 70°C derate linearly at 8.3 mW 1°C. For the Flatpak.
derate linearly at 7.1 mW 1°C above 60°C.
6-10
Code
6B
6B
9B
Part No.
",A9615DM
",A9615DC
",A9615PC
JLA9615
Equivalent Circuit (Y2 ILA9615)
16 Vee
RESPONSE
CONTROLS
STROBES
164k
1.Sk
~ ~
~
r
164k
-
8.36k
5k
f-K
3k
~!;
(T---r(~O)
L--
soon
7k
7k
"".,
v
""
"-
~
~~
J
~(9J
30 !l
J
2k
2.6k
INPUTS
IN PUTS
(12)
1
~
26k
8.36k
~t;
27k
3M
(13) 1"1
..~
SOOn
........
".,
~~
K
r
.".
ACTIVE
PULL·
UP
20n
(14)
2
1
(15)
OUTPUTS
2.5k
rK
1.5k
'----
"-..t
~;z:
300n
13211
300n
150n
150n
150n
TOOT HER
REeEI VER
I
BGND
6-"
•
~A9615
~A9615
Electrical Characteristics
Vee = 5.0 V ± 10%.
T 25°C
Typ
Min
Max
T = +125OC
Min
Max
0.40
0.18
0.40
0.40
Characteristic
VOL
Output LOW Voltage
VOH
Output HIGH Voltage
leEX
Output Leakage
Current
Ise
Output Shorted
Current
liN
Input Current
IIN(ST)
Strobe Input Current
IIN(R-e)
Response Control
Input Current
VeM
Common Mode Voltage -15
IR(ST)
Strobe Input
Leakage Current
RIN
Input Resistor
VTH" •
Differential Input
Threshold Voltage
=
T = -55°C
Min
Max
Symbol
2.2
2.4
2.4
3.2
100
-15
V
V
200
-80
p.A
mA
-0.49 -0.7
-0.9
+15
-39
Unit Condition
-0.7
mA
-1.15 -2.4
mA
-1.2
-3.4
mA
-15
± 17.5 +15
-15
2.0
+15
V
5.0
p.A
77
130
167
-500 500
-500
80
500
-500
500
mV
-1.0
-1.0
+1.0
-1.0
1.0
V
1.0
0
Power Supply Current
28.7
50
mA
tPLH
Turn-Off Time
30
50
ns
tpHL
Turn-On Time
30
50
ns
Icc
:
Notes
'VOIFF is a differential input voltage referred from "+IN A" to
"-IN A" and from "+IN B" to "-IN B" .
• • Connect Output "An to Active Pull-up "A" and Output "B" to
Active Pull-up "B".
Vee = 4.5 V,
VOUT = ••
IOL = 15.0 mA,
'VOIFF = 0.5 V
Vee = 4.5 V,
VOUT = ••
IOH = -5.0 mA,
'VOIFF'" -0.5 V
VeEX = 12 V,
'VOIFF = Vee
Vee = 4.5 V
Vee = 5.5 V,
"Vse = 0 V,
'VOIFF = -0.5 V
Vee = 5.5 V,
VIN = 0.4 V
Other Input = 5.5 V
Vee = 5.5 V,
VIN = 0.4 V
'VOIFF = 0.5 V
Vee = 5.5 V,
'VOIFF = 0.5 V
Vee = 5.0 V,
'VOIFF = 1.0 V
Vee = 4.5 V,
'VOIFF = -0.5 V
VR = 4.5 V
Vee = 5.0 V,
VIN(R) = 1.0 V,
+Input = GND
VeM = 0 V
Vee = 5.0V ±10%
-155 VeM
VeM5+15V
Vee = 5.0V ±10%
Vee = 5.5 V,
-Inputs = 0 V,
+Inputs = 0.5 V
RL = 3.9 kO,
Vee = 5.0 V,
CL = 30 pF,
Figure 1
RL = 3900,
Vee = 5.0 V,
CL = 30 pF,
Figure 1
••• See input· output tranafer characteristic graphs on
following pages.
6-12
,uA9615
!LA9615C
Electrical Characteristics
Vee
= 5.0 V
T = 25°C
Min
Min
Symbol
Characteristic
VOL
Output LOW Voltage
VOH
Output HIGH Voltage
leE X
Output Leakage
Current
Ise
Output Shorted
Current
liN
Input Current
IIN(ST)
Strobe Input Current
IIN(R·e)
Response Control
Input Current
VeM
Common Mode Voltage -15
IR(ST)
Strobe Input
Leakage Current
RIN
VTH" •
± 5%.
T = O"C
Max
0.45
2.4
2.4
Max
0.25
0.45
3.3
Min
-14
Unit
Condition
0.45
V
Vee = 4.75 V,
VOUT = ••
IOL = 15.0 mA,
'VOIFF = 0.5 V
V
Vee = 4.75 V,
VOUT = ••
IOH = -5.0 mA,
'VOIFF = -0.5 V
!LA
VeEX = 5.25 V,
'VOIFF = Vee
Vee = 4.75 V
mA
Vee = 5.25 V,
• 'Vse = 0 V,
'VOIFF = -0.5 V
mA
Vee = 5.25 V,
VIN = 0.45 V; Other
Input = 5.25 V
200
-100
-0.9
+15
Max
2.4
100
-0.49 -0.7
-0.7
-1.15 -2.4
mA
-1.2
-3.4
mA
-15
± 17.5 +15
-15
5.0
Input Resistor
Differential Input
Threshold Voltage
T = 70°C
Typ
Vee = 5.25 V,
VIN = 0.45 V
'VOIFF 0.5 V
Vee = 5.25 V,
• VOIFF = 0.5 V
=
+15
V
Vee = 5.0 V,
'VOIFF = 1.0 V
10
!LA
Vee = 4.75 V,
'VOIFF = -0.5 V
VR = 4.5 V
n
Vee = 5.0 V,
VIN(R) = 1.0 V,
+Input = GND
74
130
179
80
500
-500
500
mV
VeM = 0 V
Vee = 5.0V ±5%
1.0
-1.0
1.0
V
-15:5 VeM
VeM:5 +15 V
Vee = 5.0 V ±5%
-500
500
-500
-1.0
1.0
-1.0
lee
Power Supply Current
28.7
50
mA
Vee = 5.25 V,
+Inputs = 0.5 V,
-Inputs = 0 V
tpLH
Turn-Off Time
30
75
ns
RL = 3.9 kn,
Vee = 5.0 V,
CL "" 30 pF,
Figure t
tpHL
Turn-On Time
30
75
ns
RL = 390 n,
Vee = 5.0 V,
CL = 30 pF,
Figure 1
Notes
'VOIFF is a differential input voltage referred from "+IN A" to
"-IN A" and from "+IN e" to "-IN e".
• • Connect Output "A" to Active Pull· up "A" and Output "e" to
Active Pull·up "e".
••• See input-output transfer characteristic graphs on
following pages .
6·13
•
JLA9615
Typical Performance Curves for
Output LOW Voltage as a
Function of
Output LOW Current
300
~
~
~A9615C
0
>
I
Output HIGH Voltage as a
Function of
Ambient Temperature
~ ~Jl..
I--
~
3.0
~
.~.!!. ......
~
20
05
o
20
10
lOt-OUTPUT LOW CURRENT-rnA
so
-
VIN
0
Ycc
vJe
+
~_
30
..
-40
TA==25°C
0-
-<
-:::"
<
V,N
0
~-
-
-
;<
<
~
o-
<
0
0
r-- ~III
;<
;<
~- ~
" " "
"l
0
01
02
-0'
VIN-INPUTVOLTAGE-V
Strobe Input/Output Transfer
Characteristic as a Function
Of Ambient Temperature
YCC
~
30
~
20
02
o.
02
o
o
Output Voltage as a
Function of
Common Mode Voltage
cc
55V
1/
1 1
q ~III
/
/
0
...
~
" " 20"
10
L
UNTESTED INPUT = 0 y
TA=25°C
0
\
;<
.0
30
Vee 50V
0
0
0
20
Input Current as a
Function of
Input Voltage
0
150V
10
YIN-STROBE INPUT VOLTAGE-V
:'\.
or-- r--
140
I ved=55t
r---r-0
100
~ .0 Vee 50V
!/ ~.:!.!.v,
0
r
so
20
50
0
~
0
TA=~OC
>
I
YIN-INPUT YOLTAGE- V
...
-20
TA-AMBIENT TEMPERATURE_o C
~ 10
0
-01
-so
!:j
o0
-0.2
VOtFF=05V
0
Vee
1S0V
so
0
-
{ Vcc=4.5Y
IOL=15mA
Strobe Input/Output
Transfer Characteristic as a
Function of VCC
Input/Output Transfer
Characteristics as a
Function of Temperature
I I I
"'
20
_lOt
IOH- OUTPUT HIGH CURRENT -rnA
Input/Output Transfer
Characteristics as a
Function of VCC
IoH'" SOmA
YOtFF=05Y
o
o
15
YOH
:J
I
10
--
0
~ 10
5.0
.....
5
~
0
::trJu~
TA=2S"C
~S5"
~
g30 I"'-
-
35
I I
I I
-
.0 I'-...
I'---
A
~ YC~=5.0V -
and
Output HIGH Voltage as a
Function of
Output HIGH Current
T.='... C
Vcc"'45Y
~A9615
-.
VPIFF==20Y
30
YIN-STROBE INPUTVOLTAGE-Y
.0
Vee=O.oV
-25
-15
1
'" 1
OS
15
YCM-COMMON MODE VOLTAGE-V
6-14
0
/
V
-s 0
25
-25
15
-5
0
5
VIN-INPUTVOLTAGE
15
25
~A9615
Typical Performance Curves for ,uA9615 and ,uA9615C (Cont.)
Power Supply Current as a
Function of
Power Supply Voltage
70
WITHIACTIV~ PULL!UP
Power Supply Current as a
Function of
Ambient Temperature
"EI
Vee
-INPUTS=OV
o
./
10
20
~
70
50
50
50
0
K'"
w'1H
40
iil
30
~~s=ov
-'NiuTS=tcc
Vcc-55V
'"
~
......
-
30
;-
INbuT!vee-= II'TT(I
+
20
I
.9
I'RL=39kllee) I
0
[t
10
0..-
--
4.0
1
50
60
70
o
-50
IPHL
cy,or
RL=39D!';_
0
20
0
20
50
100
140
0
-50
20
lA-AMBIENT TEMPERATURE-o C
~-
L-11
V V
REjiSTOR PULltP
30
Vee - POWER SUPPLY VOLTAGE- V
Fig. 1
l~cc=s'OV
VIN=-3V TO+3V
C,~tOpV
"~
U
\V V
/
o
~
V
+ INPUTS =
/..
70
TA"'25°C
CONNECTED TO ACTIVE
PULL DOWN ONLY
\
Switching Time as a
Function of
Ambient Temperature
0
20
II
60
-
'-
100
140
TA -AMBIENT TEMPERATURE- 0 C
Switching Time Test Circuit and Waveforms
Vee
,----....,.-+---+3.0 V
0.0 V
------3.0 V
-
.....
~-
VIN~
~----~--~~~-VOUT
=:IPH't
L
VOUT
~~
t,_+3.0V
0.0 V
~~H ':=-
3.0V
~. -3.0V
_ _ _~
1.5V
("USE Y,N OR YiN GROUND OTHER INPUT)
STROBE AND RESPONSE ARE
LEFT OPEN
Fig. 2
INA+=t>--oOUTA
INA-
VERTICAL ~ 2.0 VlDIV. HORIZONTAL ~ 50 no/DIV.
Photograph of a 9615 switching differential data in the presence
of h,gh common mode nOise.
6·15
•
JLA9615
Typical Applications
Fig. 3
Standard Usage
DRIVER SYSTEM
RECEIVER SYSTEM
LINE
9615
Fig. 4
Frequency Response Control
TTL LOGIC
Frequency Response as a
Function of Capacitance
10M
vc~mv
TA" 25°C
1M
RESPONSE
CONTROL PIN
100 k
10k
Notes
CR > .01 /LF may cause slowing of rise and fall tomes of
the output
Due to the mechanIsm of Inductoon of dlfferentoal nOIse, the
use of the response control IS not normally needed
k
100
0001
001
01
10
CR-CAPACITANCE-"f
6-16
10
~A9616
FAIRCHILD
Triple EIA RS-232-C/
MIL-STD-188C Line Driver
A Schlumberger Company
Interface Products
Connection Diagram
14-Pln
Description
The 9616 is a Triple Line Driver which meets the
electrical interface specifications of EIA RS-232-C
and CCITT V.24 and/or MIL-STD-188C (by the
appropriate device selection). Each driver converts
TTLlDTL logic levels to EIA/CCITT and/or MIL-STD188C logic levels for transmission between data
terminal equipment and data communications
equipment. The output slew rate is internally limited
and can be lowered by an external capacitor; all
output currents are short-circuit limited. The outputs
are protected against RS-232-C fault conditions. A
logic HIGH on the inhibit terminal interrupts signal
transfer and forces the output to a VOL (EIA/CCITT
MARK) state.
INA1
INA2
INHIBIT A
OUTA
INC
INHIBITC
GND
(Top View)
For the complementary function, see the 9617 Triple
EIA RS-232-C Line Receiver and the 9627 Dual EIA
RS-232-C and MIL-STD-188C Line Receiver.
Order Information
Type
Package
J.LA9616
Ceramic DIP
J.LA9616C
Ceramic DIP
J.LA9616E
Ceramic DIP
J.LA9616C
Molded DIP
J.LA9616E
Molded DIP
•
•
INTERNAL SLEW RATE LIMITING
MEETS EIA R5-232-C AND CCITT V_24 ANDIOR
MIL-STD-188C
• LOGIC TRUE INHIBIT FUNCTION
• OUTPUT SHORT-CIRCUIT CURRENT LIMITING
• OUTPUT VOLTAGE LEVELS INDEPENDENT OF
SUPPLY VOLTAGES
Absolute Maximum Ratings
Supply Voltage
Input or Inhibit Voltage
Output Signal Voltage
Internal Power Dissipation
(Note 1)
Storage Temperature Range
Operating Temperature Range
RS-232 MIL-STD-188 (9616)
RS-232 (9616C)
RS-232 MIL-STD-188 (9616E)
Pin Temperatures
Ceramic DIP (Soldering, 60 s)
Molded DIP (Soldering, 10 s)
Truth Table
1
2
± 15 V
-1.5 V to +6.0 V
± 15 V
L
H
L
H
L
L
H
H
670mW
-65°C to +150°C
X
X
Truth Table
x=
Note
1. For Ceramic and Molded DIP above
8.3 mW/oC.
Sections A and B
Input
-55°C to +125°C
O°C to 70°C
O°C to 70°C
eo°c derate linearly at
6·17
Part No.
J.LA9616DM
J.LA9616DC
J.LA9616EDC
j.LA9616PC
J.LA9616EPC
Code
6A
6A
6A
9A
9A
Inhibit
Output
L
L
L
L
H
H
H
H
L
L
Section C
Input
Inhibit
Output
L
H
L
H
L
L
H
H
H
L
L
L
output not dependent on Input
6
~A9616
Equivalent Circuit (One of three channels)
V+
I
I NOTE
.I.
¥
I
I
015
3,6,11
14
INHIBIT
Vee,
R9
017
R5
3.6k!l
10.7 !l
018
01
R7
35 !l
.....-------+----1
4,9,10
OUTPUT
GNO • A
7
NOTE."
GNO
---i< .. - - - - -......---+---....- -.. .
R3
R4
40011
1.2k!l
8 I Vee-
I
".I.".
-¥-
: NOTE
V
Nota
Three external diodes in series with VCC+, VCC- and GND are
required 10 meet the ± 2.0 V requirement
6-18
~A9616 AND ~A9616E, RS-232-C and MIL-STD-188C
DC Characteristics Vee = ± 12 V ± 10%; Rl ;:::: 3 kfl. See Test Circuit, unless otherwise specified. (Note 2)
Symbol
Characteristic
Condition
Min
Typ
Max
VOH
Output HIGH Voltage
VINl and/or VIN2 = VINHIBIT = 0.8 V
5.0
6.0
7.0
V
VOL
Output LOW Voltage
VIN 1 = VIN2 = VINHIBIT = 2.0 V
-7.0
-6.0
-5.0
V
Ripple Rejection
Power Supply Ripple = 2.4 Vp-p, f=400 Hz
Output HIGH Voltage to
Output LOW Voltage
Magnitude Matching Error
Ise+
Positive Output Short
Circuit Current
Rl = 0 fl,VINl and/or
VIN2 = VINHIBIT = 0.8 V
-45
Ise-
Negative Output Short
Circuit Current
Rl = 0 fl, VINl = VIN2 = VINHIBIT = 2.0 V +12
VIH
Input HIGH Voltage
Vil
Input LOW Voltage
IIH
Input HIGH Current
III
Input LOW Current
1+
Positive Supply Current
L
Negative Supply Current
om of
0.25
VOH
to
VOL
VOUT
±10
%
-25
-12
rnA
+25
+45
rnA
2.0
V
VINl = VIN2 = 2.4 V
VINI = VIN2 = 5.5 V
VINI = VIN2 = 0.4 V
0.8
V
40
~A
1.0
-1.6
-1.2
15
25
VINI = VIN2 = VINHIBIT = 2.0 V
7.5
15
VINI = VIN2 = VINHIBIT = 0.8 V
-1.0
0
VINI = VIN2 = VINHIBIT = 2.0 V
-25
-15
~Il
Output Resistance, Power On
Rl = 6 kfl,
ROUT
Output Resistance, Power Off
-2.0 V :::5 VOUT :::5 +2.0 V (Notes 4 and 5) 300
= 10 rnA
rnA
rnA
VIN 1 = VIN2 = VINHIBIT = 0.8 V
ROUT
Unit
rnA
rnA
75
fl
fl
~A9616
AND ~A9616E, RS-232-C and MIL-STD-188C
AC Characteristics 0:::5 TA :::5 70° C, (Notes 2 and 3)
Symbol
Characteristic
Condition
Min
Typ
Max
Unit
Positive Slew Rate
:::5 Cl :::5 2500 pF, Rl ;:::: 3 kfl
4.0
15
30
V/~s
:::5 Cl :::5 2500 pF, Rl ;:::: 3 kfl
-30
-15
-4.0
V/~s
Negative Slew Rate
o pF
o pF
tPlH
Propagation Delay Time
No Load
740
ns
tpHl
Propagation Delay Time
No Load
740
ns
Notes
2. The operating temperature range for the 9616 is -55°C to
+ 125°C and 9616E is O°C to +70°C.
3. An external capacitor may be needed to meet signal wave
shaping requirements of MIL·STD·188C at the applicable
modulation rate. No external capacitor is needed to
meet RS-232-C over the operating temperature range of
O°C to +70°C.
4. All Input and supply pins grounded.
5. Three external diodes in series with VCC+. VCC- and GND
are required to meet the ± 2.0 V requirement
6-19
•
JLA9616
9616C, EIA RS-232-C
DC Characteristics Vee = ± 12 V ± 10%, over operating temperature range. See Test Circuit, RL
otherwise specified.
= 3 kD, unless
Symbol
Characteristic
Condition
Min
Typ
Max
= VINHIBIT = 0.8 V
= VIN2 = VINHIBIT = 2.0 V
RL = 0 D, VINl and/or
VIN2 = VINHIBIT = 0.8 V
RL = 0 D, VINl = VIN2 = VINHIBIT = 2.0 V
Unit
VOH
Output HIGH Voltage
VINl and/or VIN2
5.0
6.0
7.5
V
VOL
Output LOW Voltage
VINl
-7.5
-6.0
-5.0
V
Ise+
Positive Output
Short-Circuit Current
Ise-
Negative Output
Short-Circuit Current
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
IIH
Input HIGH Current
IlL
Input LOW Current
-25
mA
25
mA
2.0
= VIN2 = 2.4 V
= VIN2 = 5.5 V
VINI = VIN2 .. 0.4 V
VINl = VIN2 = VINHIBIT = 0.8 V
VINl = VIN2 = VINHIBIT = 2.0 V
VIN 1 = VIN2 = VINHIBIT = 0.8 V
VINl = VIN2 = VINHIBIT = 2.0 V
V
VINl
VINl
1+
Positive Supply Current
L
Negative Supply Current
ROUT
Output Resistance, P,ower Off -2.0 V
-1.6
0.8
V
40
1.0
/-IA
mA
-1.2
mA
15
22
7.5
13
-1.0
0
-22
-15
mA
::s VOUT ::s +2.0 V (Notes 4 and 5) 300
9616C, EIA RS-232-C
AC Characteristics 0 --< TA --< 70°C, (Note 6)
Symbol Characteristics
Conditions
Min
mA
D
Typ
Max
Unit
Negative Slew Rate
o pF ::s CL ::s
o pF ::s CL ::s
tpLH
Propagation Delay Time
No Load
740
ns
tpHL
Propagation Delay Time
No Load
740
ns
Positive Slew Rate
2500 pF, RL ~ 3 kD
4.0
15
30
V//-IS
2500 pF, RL ~ 3 kD
-30
-15
-4.0
V//-IS
Notes
4 All mput and supply pins grounded,
5 Three external diodes 10 series with VCC+. VCC- and GND
are required to meet the ± 2.0 V requirement
6 The operating temperature range lor the 9616 is -55·C to
+125·C and 9616E is O·C to +70·C.
6-20
~A9616
AC Test Circuit
VIN 1
1/39616
Voltage Waveforms
INPUT
10R2
(INHIBIT = LOW)
OV
~
1.5V
VOH ________~~~
OUTPUT
OV----------~_+~--~,_----------------~~~~~-If
Note
Omil VIN2 for channel "C".
Inpul: Frequency = 50 kHz
Pulse Width = 20 P.s
Ir and If = 10 ± 5 ns
•
6·21
J.LA9627 • J.LA9627C
RS-232C/MIL-STD-188C
Dual Line Receivers
FAIRCHILD
A Schlumberger Company
Interface Products
Description
The 9627 is a Dual Line Receiver which meets the
electrical interface specifications of EIA RS-232C and
MIL-STD-188C. The input circuitry accommddates
± 25 V input signals and the differential inputs allow
user selection of either inverting or non-inverting logic
for the receiver operation. The 9627 provides both a
selectable hysteresis range and selectable receiver
input resistance. When pin 1 is tied to Vee, the typical
switching points are at +2.6 V and -2.6 V, thus
meeting RS-232-C requirements. When pin 1 is open,
the typical switching points are at +50 IJ.A and
-50 IJ.A, thus satisfying the requirements to MIL-STD188C LOW level interface. Connecting the RIN pin to
the (-) input yields an input impedance in the range of
3 kQ to 7 kQ and satisfies RS-232-C requirements;
leaving RIN unconnected, the input resistance will be
greater than 6 kQ to satisfy MIL-STD-188C.
Connection Diagram
16-PinDIP
The output circuitry is TTL/DTL compatible and will
allow "collector-dotting" to generate the wire-OR
function. A TTL / DTL strobe is also provided for each
receiver. The EIA failsafe mode of operation is shown
in the application section of this data sheet.
"Internal Connectionmake no connection to this pm.
16
HYSTERESIS
OUTA
STROBE A
RIN A
RIN B
HNA
GND
Vee-
(Top View)
Order Information
Type
Package
IJ.A 9627
Ceramic DIP
IJ.A9627C
Ceramic DIP
1J.A.9627C
Molded DIP
•
•
•
•
•
•
•
EIA RS-232-C INPUT STANDARDS
MIL-STD-188C INPUT STANDARDS
VARIABLE HYSTERESIS CONTROL
HIGH COMMON-MODE REJECTION
RIN CONTROL (5 kQ OR 10 kQ)
WIRED-OR CAPABILITY
CHOICE OF INVERTING AND
NON-INVERTING INPUTS
• OUTPUTS AND STROBE nL COMPATIBLE
Absolute Maximum Ratings
Vee+ to Ground
Vee- to Ground
Input Voltage Referred to
Ground Pin
Strobe to Ground Voltage
Maximum Applied Output Voltage
Storage Temperature Range
Operating Temperature Range
Military (9627)
Commercial (9627C)
Internal Power Dissipation
(Note 1)
Pin Temperature
Ceramic DIP, (Soldering, 60 s)
Molded DIP (Soldering, 10 s)
Vee.
o V to +15 V
o V to -15 V
±25 V
-0.5 V to +5.5 V
-0.5 V to +15 V
-65°C to +150°C
-55°C to +125°C
O°C to +70°C
730mW
Notes
1. Above 65°C ambient temperature, derate linearly at
8.3 mW/oC
6·22
Code
68
68
98
Part No.
IJ.A9627DM
IJ.A9627DC
IJ.A9627PC
J,LA9627 • J,LA9627C
Equivalent Circuit (1 /2 of circuit shown)
vcc' ________________~~----~~----~~----_.--------------------~----._------~~---------16
R11
1.28 kIl
C1
R10
7OO1l
R43
700H
R9
700ll
7, 10 --~__4t_.,
R1
8kll
R2
11.3 kll
R4
2 kll
R42
7.6kll
6,11
R34
11.3kll
R41
3.2kll
07
R17
2.4 kll
R24
5.3kH
R22
1.12 kll
R25
450 II
R23
450 Il
R26
450ll
VCC-~9--------~----~----~----~----~--------------4---------~~------~------~-------4-R29
3.76kll
=
=
=
=
C 1 C2
C3
C4
1 1 pF
Pin 4 and 13 = Internal connection
6·23
•
~A9627 • ~A9627C
#A9627
DC Characteristics
Vcc+ = 12 V ± 10%, Vcc- = -12 V ± 10% over Operating Temperature Range,
unless otherwise specified.
MIL • STD • 188C
Symbol
Characteristic
VOL
Output LOW Voltage
VOH
Output HIGH Voltage
Isc
Output Shorted Current
IIH
Input HIGH Current (Strobe)
(Strobe)
Condition
(Pins 6 and 11 Open, Inverting
Inputs Open, Pin 1 Open)
Vcc+ = +10.8 V, Vcc- = -13.2 V
Non-Inverting Input = +0.6 V,
IOH = -0.5 mA
ITH+
Positive Threshold Current
VOUT
ITH-
Negative Threshold Current
VOUT
1+
Positive Supply Current
L
Negative Supply Current
= 2.4 V
= 0.4 V
Unit
0.4
V
V
Vcc+ = +10.8 V,
Vs = 2.4 V
Vcc- = -13.2 V
Non-Inverting Input = +0.6 V Vs = 5.5 V
Input Resistance
Max
2.4
Vcc+ = +13.2 V, Vcc- = -10.8 V
Non-Inverting Input = +0.6 V
Outputs Grounded
RIN
VIH
Input HIGH Voltage (Strobe)
(Strobe)
Typ
Vcc+ = +10.8 V, VCC- = -13.2 V
Non-Inverting Input = -0.6 V,IOL = 6.4 mA
Vcc+ = +13.2 V, Vcc- = -13.2 V
Non-Inverting Input = +3.0 V or -3.0 V
VIL
Input LOW Voltage (Strobe)
(Strobe)
Min
3.0
mA
40
#A
1.0
mA
kg
6.0
100
-100
= -0.6 V
VNon-lnverting Input = +0.6 V
Vcc+ = +13.2 V, Vcc- = -10.8 V
VNon-lnverting Input = -0.6 V
ITA = +125°C (9627)
VNon-lnverting Input = +0.6 V
ITA = +125°C (9627)
#A
#A
0.8
VNon-lnverting Input
2.0
V
V
18
12.4
-16
mA
mA
-11.4
RS·232C
Condition
(Non-Inverting Inputs Connected to
Ground, RIN Inputs Connected to Inverting
Inputs, Pin 1 Connected to Vcc-)
Min
Symbol
Characteristic
RIN
Input Resistance
VIN
VIN
Open Circuit
VIN
Input Voltage
VTH+
Positive Threshold Voltage
VTH-
Negative Threshold Voltage
AC Characteristics
TA - +25°C, Vcc+
Symbol
Characteristic
tpLH
Propagation Delay Time
tpHL
Propagation Delay Time
= +3.0 V to +25 V
= -3.0 V to -25 V
Typ
Max
3.0
3.0
7.0
7.0
Unit
kg
kg
-2.0
2.0
V
+3.0
V
-3.0
V
= +12 V, Vcc- = -12 V, MIL-STD-188C. RS-232C
Typ
Max
Unit
See AC Teat Circuit
60
250
na
See AC Teat Circuit
84
250
na
Min
Condition
6-24
p,A9627 • p,A9627C
AC Test Circuit and Waveforms
Threshold Current Matching Circuit
Vou-
+5.0 V
VIN_----!
VIN
7(10)
6(11)
5(12)
47011
Vcc+~VCC-
1 6 - - - Vcc+~12V
ADJUST POT TO ACHIEVE POSITIVE THRESHOLD CURRENT
AND NEGATIVE THRESHOLD CURRENT MATCHING
8~GND
9 - - - Vcc-~ -12V
PIN10PEN
Note.
15 pF includes jig capacitance
All diodes are FD777 or equivalent
PRR =10 kHz,
PW=50MS,
Ir=I,=5 no
•
+-.1
VOUT _ _ _ _
EIA R5-232C Interface with Failsafe Receiver
(Pin 1 Connected to VCC-)
-'~
1/39616
DATA 2
INHIBIT
r----
DATA OUT IS LOW
IF INPUT IS OPEN. OR
INPUT IS SHORTED TO AB. OR
DRIVER POWER IS OFF.
EIA RS-232C
INTERFACE----I
>
DATA OUT
)
10kn
+5V
SIGNAL COMMON
RETURN
CIRCUIT
6·25
Vcc-
p,A9627 • p,A9627C
MIL-STD-188C Interface
(Pin 1 Open)
1/69N04/7404
I~~T:T -I >,.........."
DATA OUT
(NOT~~»__
>-----,
.::SI:.:G::;N::Al::C:;,O:::M::;M:::.O:::N"---_-7)
470 l!
~
RETURN
PIN 1 OPEN
~
Vcc+
Capacitor for transmitter waveshapmg at applicable modulation
rate
6-26
50 k!l
Vcc-
,uA9636A
Dual Programmable
Slew Rate Line Driver
EIA RS-423 Driver
FAIRCHILO
A Schlumberger Company
Interface Products
Connection Diagram
a-Pin DIP
Description
The IlA9636A is a TTL/CMOS compatible, dual,
single-ended, line driver which has been specifically
designed to satisfy the requirements of
EIA Standard RS-423.
WAVESHAPE
CONTROL
Vcc+
IN A
OUT A
IN B
OUT B
GND
Vcc -
The IlA9636A is suitable for use in digital data
transmission systems where signal wave shaping is
desired. The output slew rates are jointly controlled by
a single external resistor connected between the
wave shaping control (WS) pin and ground. This
eliminates any need for external filtering of the output
signals. Output voltage levels and slew rates are
independent of power supply variations. Current
limiting is provided in both output states. The IlA9636A
is designed for nominal power supplies of ± 12 V.
(Top View)
Order Information
Type
Package
IlA9636A
Ceramic DIP
IlA9636A
Ceramic DIP
IlA9636A
Molded DIP
Inputs are TTL compatible with input current loading
low enough (1/10 UL) to be also compatible with
CMOS logic. Clamp diodes are provided on the inputs
to limit transients below ground.
• PROGRAMMABLE SLEW RATE LIMITING
• MEETS EIA RS-423 REQUIREMENTS
• COMMERCIAL OR MILITARY TEMPERATURE
RANGE
• OUTPUT SHORT CIRCUIT PROTECTION
• TTL AND CMOS COMPATIBLE INPUTS
RS-423
System Application
Vcc+
TWISTED PAIR
OR
FLAT CABLE
Vcc-
Note
Newer versions will not require the external diode and
normal opera lion IS not Impaired if the diode IS absent
6-27
+ 5.0 V
Code
6T
6T
9T
Part No.
IlA9636ARM •
IlA9636ARC
IlA9636ATC
,uA9636A
TA = 25°C unless
otherwise noted
Vcc+ Pin Potential to Ground Pin VCC- to + 15 V
VCC- Pin Potential to Ground Pin +0.5 to -15 V
VCC+ Pin Potential to VCC- Pin 0 to +30 V
Output Potential to Ground Pin
± 15 V
Output Source Current
-150 rnA
Output Sink Current
150 rnA
Internal Power Dissipation (Note 1)
9T Molded DIP
1.3 W
1.15 W
6T Ceramic DIP
Operating Temperature
Military (9636ARM)
Commercial (9636ARC / ATC)
Storage Temperature
Pin Temperature
Molded DIP (Soldering, 10 s)
Ceramic DIP (Soldering, 60 s)
Absolute Maximum Ratings
-55°C to 125° C
O°C to 70° C
-65° C to 150° C
260° C
300°C
Noles
1. Derate at 7,7 mW/oC for ambient temperature above 25°C for
6T package and derate 11,1 mW / ° C for 9T package.
!LA9636A
Recommended Operating Conditions
!LA9636ARM
!LA9636ARC,!LA9636ATC
Characteristic
Min
Typ
Max
Min
Typ
Max
Unit
Positive Supply Voltage (Vcc+)
Negative Supply Voltage (VCC-)
Operating Ambient Temperature (T A)
Wave Shaping Resistance (RwS)
10.8
-13.2
-55
10
12
-12
25
13.2
-10.8
125
500
10.8
-13.2
0
10
12
-12
25
13.2
-10.8
70
1000
V
V
°C
kfl
!LA9636A
Electrical Characteristics
Over recommended temperature supply voltage and wave shaping resistance ranges
unless noted.
Characteristic
Condition
Min
Typ
Max
Unit
VOHI
vOH2
VOH3
Output HiGH Voltage
RL to GND (RL
RL to GND (RL
RL to GND (RL
5.0
5.0
4.0
5.6
5.6
5.5
6.0
6.0
6.0
V
V
V
VOlt
VOL2
VOL3
Output LOW Voltage
= 00)
= 3 kfl)
= 450 fl)
RL to GND (RL = 00)
RL to GND (RL = 3 kfl)
RL to GND (RL = 450 fl)
-6.0
-6.0
-6.0
-5.7
-5.6
-5.4
-5.0
-5.0
-4.0
V
V
V
Ro
Output Resistance
25
50
n
Isc+
ISC-
Output Short Circuit Current
Output Short Circuit Current
-60
60
-15
150
rnA
rnA
100
!LA
0.8
V
V
Symbol
lOX
Output Leakage Current
VIH
VIL
Input HiGH Voltage
Input LOW Voltage
s RL
VOUT = 0 V, VIN = 0 V
VOUT = 0 V, VIN = 2.0 V
VOUT = ±6 V, Power-Off
450 n
(Note 2)
-150
15
-100
2.0
= 15 rnA
VCD
Input Clamp Diode
liN
IlL
Input LOW Current
IIH
Input HIGH Current
ICC+
Positive Supply Current
ICC-
Negative Supply Current
= 0.4 V
VIN = 2.4 V
VIN = 5.5 V
Vcc+ = +12 V, VCC- = -12 V
RL = 00, RwS = 100 kn, VIN = 0 V
VCC+ = +12 V, VCC- = -12 V
RL = 00, RwS = 100 kn, VIN = 0 V
VIN
Notes
2. Only one output should be shorted at a time.
6·28
-1.5
-1.1
V
-80
-16
!LA
-18
1.0
10
10
100
!LA
!LA
13
18
rnA
-13
rnA
~A9636A
~A9636A
AC Characteristics
Symbol
TA = 25°C, Vee = ± 12 V
Characteristic
Output Fall Time
tf
Min
Typ
Max
= 10 kfl
= 100 kfl
= 500 kfl
= 1000 kfl
RWS = 10 kfl
RwS = 100 kfl
RwS = 500 kfl
RWS = 1000 kfl
0.8
8.0
40
80
1.1
11
55
110
1.4
14
70
140
0.8
8.0
40
80
1.1
11
55
110
1.4
14
70
140
Rws
RWS
RWS
RWS
Output Rise Time
tr
± 10%, see AC Test Circuit
Condition
Unit
~s
~s
~s
~s
~s
~s
~s
~s
Typical Performance Curves
Input/Output Transfer
Characteristic vs Temperature
I
"~
200
f--+-+-+-t~+-+=~s 45~O~lkll
150 -Bws
100
40
50
125¢C
f~
~
-50
25"C
-100
-20
0
O'C
55°C
08
16
12
Output Current vs
Output Voltage (Power Off)
100
I
80
::>
0
...
-20
~
~
I
20
)
I
20
~
10
::>
-80
0r-+-,r-+-t~+-+-+~r-~
u
~ -10
-55°C
g
-20 I-+-+-+-t~+--!V-'N-+O-V+-+--l
-30 r-HIt-+-+-+/-rt--.l+-.l-II-+--i
I~- 25°C
-40b=*"LI--+...-4-F==F=F:::.j.~1--l
3
1
4
5
-4
-2
0
2
OUTPUT VOLTAGE -
4
6
V
-5~lLO--'_8-_6'--_..L.4---'_2'--.l.-...J2'--.1.4--'6-"'-8--"0
6
OUTPUT VOLTAGE -
v;, ~ ~12 J
8
10
o- r-
1,000
,
55'Cf:
100
,
~LOGIC
Icc-
VIN = 1
-
VIN = 1
-10
~
-20
Ice~
'LOGIC_
VIN = 0
-
V
Transition Time vs RwS
LOGIC
JiVIN =
10
Wc'l1
25°C
70°C & 125°C
-30
I I
I I
-40
~6
20
§
~
-
J~OGIC
o
iil
-8
30t=l==~t:5::$~::t:~=t~
~
~
Rws"'"' 100 k!l-
~
-40
::>
0
-60
-100
-10
11"'-
30
~
100 kll
-12 V
~ 10
40
- r-
~
TA -= 25"C
Supply Current vs Temperature
II
Vee' - VIN - 0
F0600 DIODE CONNECTED
IN SERIES WITH Vee PIN
r- -
u
4Of--+-+-+-t~+-+vcc,
INPUT YOlTAGE-V
INPUT VOLTAGE-V
40
Rws
---...
o
18
Output Current vs
Output Voltage (Power On)
25°C -----i
-200
04
~
-55°C
vi
I - - 125°C
-60
...I
co
112
12V
100 kll
-150
-40
60
0
vee
125°C
60
70°C
I!:::>
~Ivccl
I-+-+-+-t~+-+~~~- ~ ~l~\V
20
...~::>
Input Current vs Input Voltage
55
25
70
TEMPERATURE _ °C
6·29
125
1
V
10 k 20 k 50 k 100 k
Rws -
300 k
1M
3M
WAVE SHAPING RESISTANCE -
JI
•
~A9636A
AC Test Circuit and Waveforms
+12 V
7 (6)
><:>-...;.....;.....- - - _ - - VOUT
V,N--.....-...;.....;-I
51 !l
450 !l
CL
30 pF
-12 V
CL -
VIN
Ampiliude 3 0 V
Offsel 0 V
Pulse W,dlh 500 I'S
PRR 1 kHz
Includes Jig and probe capacilance
I r . If
6-30
10 ns
,uA9637A
Dual Differential
Line Receiver
FAIRCHIL.O
A Schlumberger Company
Interface Products
Description
The J.lA9637 A is a Schottky Dual Differential Line
Receiver which has been specifically designed to
satisfy the requirements of EIA Standards RS-422
and RS-423. In addition, the J.lA9637 A satisfies the
requirements of MIL-STD 188-114 and is compatible
with the International Standard CCITT
recommendations. The pA9637 A is suitable for use as
a line receiver in digital data systems, using either
single-ended or differential, unipolar or bipolar
transmission. It requires a single 5 V power supply
and has Schottky TTL compatible outputs. The
J.lA9637 A has an operational input common mode
range ± 7 V either differentially or to ground.
Connection Diagram
a-Pin DIP
vcc+
IN A+
OUT A
IN A-
OUT B
IN B+
GND
IN B-
Top View
•
•
•
•
•
•
•
•
DUAL CHANNELS
SINGLE 5 V SUPPLY
SATISFIES EIA STANDARDS RS-422 AND RS-423
BUILT IN ± 35 mV HYSTERESIS
HIGH COMMON MODE RANGE
HIGH INPUT IMPEDANCE
TTL COMPATIBLE OUTPUT
SCHOTTKY TECHNOLOGY
Absolute Maximum Ratings
Order Information
Type
Package
pA9637 A
Ceramic DIP
pA9637 A
Ceramic DIP
J.lA9637 A
Molded DIP
TA = 25°C unless
otherwise noted
Supply Voltage (Vee Potential
to Ground)
-0.5 V to 7.0 V
Input Potential to Ground Pin
± 15 V
Differential Input Voltage
± 15 V
-0.5 V to 5.5 V
Output Potential to Ground Pin
Output Sink Current
50 rnA
Internal Power Dissipation (Note 1)
6T Ceramic DIP
1. 15 W
9T Molded DIP
1.3 W
Operating Temperature
pA9637ARM
-55°C to 125°C
pA9637ARC,pA9637ATC
O°C to 70°C
Storage Temperature
-65°C to 150°C
Pin Temperature
Ceramic DIP (Soldering, 30 s)
Molded DIP (Soldering, 10 s)
6-31
Code
6T
6T
9T
Part No.
J.lA9637ARM
pA9637ARC
J.lA9637ATC
•
f.LA9637A
Equivalent Circuit
,---~--------~--------------~--------~-------'---'---------'-----VeCT
R25
R7
R8
R24
R14
R15
R23
08
R11
R18
R3
Vee
2,3
t--------<,-I:.
017
R16
+IN _7-,-,5--.....-.N'V'-_---I-------t------.
R6
020
R19
RS
-=
GND
~A9637A
Recommended Operating Conditions
~A9637ARC,~A9637ATC
~A9637ARM
Characteristic
Min
Typ
Max
Min
Typ
Max
Unit
Supply Voltage (Vee>
Operating Ambient Temperature (T A)
4.5
-55
5.0
25
5.5
125
4.75
0
5.0
25
5.25
70
V
6·32
°c
Vo
JLA9637A
JLA9637A
Electrical Characteristics
Over recommended temperature and supply voltage ranges, unless otherwise noted.
Symbol
Characteristic
Condition (1)
Min
VTH
Differential Input
Threshold Voltage
-7.0 V ::5 VeM ::5 7.0 V (3)
VTH(R)
Differential Input
Threshold Voltage
liN
Input Current
VOL
Output LOW Voltage
Max
Unit
-0.2
0.2
V
-7.0 V ::5 VeM ::5 7.0 V (4)
-0.4
0.4
V
VIN = 10 V, 0 ::5 Vee ::5 5.5 V (5)
VIN = -10 V, 0::5 Vee::5 5.5 V (5)
1.1
-3.25 -1.6
3.25
rnA
rnA
0.5
V
= 20 rnA, Vee = Min
IOH = -1.0 rnA, Vee = Min
VOUT = 0 V, Vee = Max (6)
Vee = Max, VIN(+) = 0.5 V,
VIN(-) = GND, (Both outputs low)
VeM = ± 7 V (See curves)
0.35
IOL
VOH
Output HIGH Voltage
Ise
Output Short Circuit Current
Icc
Supply Current
VHYST
Input Hysteresis
Typ
2.5
3.5
-40
-75
-100
rnA
35
50
rnA
V
70
mV
JLA9637A
AC Characteristics
Vee = 5 V, TA = 25°C
Symbol
Characteristic
Condition (1)
IpLH
Propagation Delay Time
LOW to HIGH
tpHL
Propagation Delay Time
HIGH to LOW
Typ
Max
Unit
See AC Test Circuit
15
25
ns
See AC Test Circuit
13
25
ns
Noles
2 Use Min I Max values specified In recommended
operating conditIOns
3. TYPical limits are at Vce = 5 a v and 25°e
4. VDIFF (Differenlial Input Voltage) = (VIN+) - (VIN-)
VCM (Common Mode Input Voltage) = (VIN+) or (VIN-)
Min
•
5 500!l ± 1% In series with Inputs
6 The input not under test IS lied 10 ground
7 Only one output should be shorted al a time.
Typicallnput/Output
Transfer Characteristics
Vcc-·S2SV
VJc"'475Y
Ir-
I
I
I
: VeM
I
I
1
o
100
..
:
I
oov~
VCM '" ±7V
:
I
I
I
I
I
I
VCM~OV"""":
I
I
I
I:
I
3
!
1
..
I
I
0
100
100
INPUT VOLTAGE-mY
.
.
1~=~7V
I
I
I
I
..
INPUT VOLTAGE-mV
6·33
100
J-LA9637A
AC Test Circuit and
Waveforms
Vee
~
5V
Vee
VOUT
~
5 V
+O.5V
8(6)
V,N
392 n
V,N
51 0
-O.5V
7(5)
CL
15 pF
3.92 kn
CL Includes jig and probe capacitance. All diodes are
F0700 or equivalent.
VIN
Amplitude' 1 0 V
Offset· 0.5 V
Pulse Width: 100 ns
PRR. 5 MHz
tr If = S 5 ns
Typical Application
RS-422 System Application (FIPS 1020) Differential Simplex Bus Transmission
TWISTED PAIR
OR
FLAT CABLE
+5V
+5V
~
...JL
DUAL RS·422 LINE DRIVER
+5V
Note
Rt 2: 50 n for RS·422 operatton
Rt combined wilh Input impedance of receIvers must be greater
than 90 n.
6-34
JLA9638 Dual High-Speed
Differential Line Driver
(EIA-RS-422)
FAIRCHILD
A Schlumberger Company
Interface Products
Description
The 9638 is a Schottky, TTL-compatible Dual Channel
Differential Line Driver, designed specifically to meet
the EIA-RS-422 specifications. It is designed to
provide unipolar differential drive to twisted-pair or
parallel-wire transmission lines. The inputs are TTL
compatible. The outputs are similar to totem-pole
TTL outputs, with active pull-up and pull-down. The
device features a short-circuit protected active pull-up
with low output impedance and is specified to drive
50 n transmission lines at high speed. The mini DIP
provides high package density.
•
•
•
•
•
•
•
•
•
•
•
•
Connection Diagram
a·Pin DIP
SINGLE 5 V SUPPLY
SCHOTTKY TECHNOLOGY
TTL AND CMOS·COMPATIBLE INPUTS
OUTPUT SHORT·CIRCUIT PROTECTION
INPUT CLAMP DIODES
COMPLEMENTARY OUTPUTS
MINIMUM OUTPUT SKEW « 1 ns TYPICAL)
50 mA OUTPUT DRIVE CAPABILITY FOR 50 n
TRANSMISSION LINES
MEETS EIA·RS·422 SPECIFICATIONS
PROPAGATION DELAY OF LESS THAN 10 ns
"GLITCH LESS" DIFFERENTIAL OUTPUT
DELAY TIME STABLE WITH Vee AND
TEMPERATURE VARIATIONS
« 2 ns TYPICAL) (FIGURE 3)
Absolute Maximum Ratings
Vee Pin Potential to Ground Pin
Input Voltage
Internal Power Dissipation
Operating Temperature
9638RM
9638RC,9638TC
Storage Temperature
Pin Temprature
Molded DIP (Soldering, 10 s)
Ceramic DIP (Soldering, 30 s)
Vee
CH.1
OUTB
INCH.1
CH.1
OUT A
INCH.2
CH.2
OUTB
GND
CH.2
OUT A
(Top View)
Order Information
Type
Package
ILA9638
Ceramic DIP
ILA9638
Ceramic DIP
ILA9638
Molded DIP
Code
6T
6T
9T
Part No.
ILA9638RM
ILA9638RC
ILA9638TC
-0.5 V to +7.0 V
-0.5 V to +7.0 V
800mW
-55·Cto +125·C
O· C to 70· C
-65· C to +150· C
260· C
300·C
6·35
-.----:.-=-------.-------.--"~~--- --.
---"'-".---------==------
-~--
•
#LA9638
Recommended Operating Conditions
9638RM
Typ
Min
4.5
5.0
Symbol Characteristic
Supply Voltage
Vee
Output HIGH Current
10H
Output LOW Current
10L
Ambient Temperature
TA
Electrical Characteristics
Max
5.5
-50
50
125
-55
9638RC,9638TC
Min
Typ
Max
4.75
5.0
5.25
-50
50
0
70
Unit
V
mA
mA
°C
Over recommended ambient temperature, unless otherwise noted
Symbol
Characteristic
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
VI
Clamped Input Voltage
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
liN
Input Current at Maximum
Input Voltage
IIH
Input HIGH Current
IlL
Input LOW Current
lOS
Short-Circuit Output Curren
Condition (Notes 1 and 2)
Min
Typ
Max
9638RC,9638TC
0.8
9638RM
0.7
= Min, liN = -18 mA
Vee = Min,
10H = -10 mA
VIH = VIH Min,
VIL = VIL Max 10H = -40 mA
Vee = Min, VIH = VIH Min,
VIL = VIL Max, 10L = 40 mA
Vee = Max, VIN Max = 5.5 V
Vee = Max, VIH = 2.7 V
Vee = Max, VIL = 0.5 V
Vee = Max, Vour = 0 V
-1.0
Vee
Terminated Output Voltage
Vr, Vr
Vr - Vr Output Balance
See Figure 1
VOS.VOS Output Offset Voltage
Vos-Vos Output Offset Balance
<
Vx
2.5
-1.2
<
Output Leakage Current
-0.25 V
lee
Supply Current
(both drivers)
All input at 0 V, Vee
V
V
3.5
V
2.0
0.5
V
50
/LA
25
/LA
-200
/LA
-150
mA
0.4
3.0
0.4
V
V
V
100
/LA
65
mA
Typ
Max
Unit
10
10
10
10
20
20
20
20
ns
ns
ns
ns
-50
V
2.0
Ix
Unit
V
2.0
6.0 V
= 5.5 V, no load
45
AC Characteristics
Symbol
tpHL
tpLH
tf
tr
Characteristic
Min
Condition
Propagation Delay
Fall Time, 90% - 10%
Rise Time, 10% - 90%
Skew Between Outputs
tpA-tPB
A and B
TA
RL
= 25°C, CL = 15 pF (Note 2),
= 100 fl, See Figure 2
1
Notes
1 Use minimum and maximum values specified in recommended
operating conditions.
2. TYPical limits are at Vee = 5.0 and TA = 25°e.
6·36
ns
~A9638
DC Test Circuit
Fig. 1
Terminated Output Voltage
and Output Balance
+
50 II
Y,N
VT
50 II
Fig. 2
AC Test Circuit and Voltage Waveform
~-----'------~------VOUT
Y,N
___1.5....11
RL
100 II
ICL
Y,N
•
-=VCiU'T
90%
I CL
IPLH
VOUT-VOUT------,'
•
Notes
1 The pulse generator has the following characteristics
ZOUT = 50 12, PRR = 500 kHz
tw = 100 ns, tr :$ 5 ns
2 CL Includes probe and Jig capacitance
Fig. 3
Typical Delay Characteristics
,.
,.
14
14
-
12
,.
~
•o
f--
50
2S
0
25
50
75
100
-
12
,.
--
t--
•
125
3
vcc-v
AMBIENT TEMPEAATURE_oC
6·37
t-
JlA1488
RS-232C
Quad Line Driver
FAIRCHILD
A Schlumberger Company
Interface Products
Connection Diagram
14-Pln DIP
Description
The /LA 1488 is an EIA RS-232C specified Quad Line
Driver. This device is used to interface data terminals
with data communications equipment. The /LA 1488 is a
pin-for-pin replacement of the MC 1488.
VeeINA
• CURRENT LIMITED OUTPUT- ± 10 mA TYP
• POWER-OFF SOURCE IMPEDANCE
300nMIN
• SIMPLE SLEW RATE CONTROL WITH
EXTERNAL CAPACITOR
• FLEXIBLE OPERATING SUPPLY RANGE
OUT A
IN B1
IN B2
OUTB
Absolute Maximum Ratings (at 25°C unless
otherwise noted)
Power Supply Voltages
+15 V
vee+
-15 V
VCC-15 Vdc to +7.0 Vdc
Input Voltage Range (VIR)
Output Signal Voltage
± 15 Vdc
Continuous Total Power
Dissipation (Note 1)
800mW
Operating Temperature
O°C to 70 0 e
-65°C to +150°C
Storage Temperature
Pin Temperatures
Ceramic DIP (Soldering,
60 s)
300°C
Molded DIP (Soldering,
10 s)
260°C
GND
(Top View)
Order Information
Type
Package
/LA 1488
Ceramic DIP
/LA 1488
Molded DIP
14
V e c . - - . . - - - - - -.....- -.....- - - - - ,
6.2 k
PINS 4, 9, 12 OR 2
INPUTS
9A
Part No.
/LA1488DC
/LA 1488PC
Notes
1 Above 60°C ambient temperatures. derate linearly at
83 mW/oC
Circuit Schematic ('A of Circuit Shown)
8.2 k
Code
6A
{-+n-.,
PINS 5, 10, 13
300
OUTPUT
PINS 6, 8,
11 OR 3
GND7""l
10 k
1
Vee- - - - -_ _-_----~>__--'
6-38
JlA1488
DC Characteristics
Vcc+ = +9.0 V ± 1%, Vccunless otherwise noted
Symbol Characteristic
IlL
Input LOW Current
IIH
Input HIGH Current
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
Positive Output Short-Circuit Current
ROUT
Output Resistance
Negative Output Short-Circuit Current
Positive Supply Current
Icc-
Negative Supply Current
Pc
Power Consumption
AC Characteristics
Vcc+
± 1%, TA
= 0 to +70°C,
Condition
Fig
=0
VIH = 5.0 V
VIL = 0.8 V, RL = 3.0 kQ
VCC+ = +9.0 V, VCC- = -9.0 V
VIL = 0.8 V, RL = 3.0 kQ
VCC+ = +13.2 V,
Vcc- = -13.2 V
VIH = 1.9 V, RL = 3.0 kQ
Vcc+ = +9.0 V, VCC- = -9.0 V
VIH = 1.9 V, RL = 3.0 kQ
Vcc+ = +13.2 V,
Vcc- = -13.2 V
VIL = 0.8 V (Note 2)
VIH = 1.9 V (Note 2)
Vcc+ = VCC- = 0 V,
Vo = ±2.0 V
RL = co
VIH = 1.9 V, Vcc+ = +0.9 V
VIL = 0.8 V, VCC- = +9.0 V
VIH = 1.9 V, VCC+ = +12 V
VIL = 0.8 V, VCC+ = +12 V
VIH = 1.9 V, Vcc+ = +15 V
VIL = 0.8 V, VCC+ = +15 V
RL = co
VIH = 1.9 V, VCC- = -9.0 V
VIL = 0.8 V, VCC- = -9.0 V
VIH = 1.9 V, VCC- = -12 V
VIL = 0.8 V, VCC- = -12 V
VIH = 1.9 V, VCC- = -15 V
VIL = 0.8 V, VCC- = -15 V
VCC+ = 9.0 V, VCC- = -9.0 V
VCC+ = 12 V, VCC- = -12 V
1
VIL
los+
los-
Icc+
= -9.0 V
= +9.0 V
Symbol Characteristic
± 1%, Vcc-
= -9.0 V
-+ 1%, TA
Condition
tpLH
tpHL
Propagation Delay Time
RL
= 3.0 kQ, CL = 15 pF
tf
tr
Fall Time
Rise Time
RL
= 3.0 kQ, CL = 15 pF
Notes
2 MaxImum Package Power DIssIpatIon may be exceeded If all
outputs are shorted sImultaneously
6-39
Min
Typ
Max Unit
1.0
1.6
1
10
2
+6.0
+7.0
2
+9.0
+10.5
2
-6.0
-7.0
2
-9.0
-10.5
3
3
+6.0
-6.0
+10
-10
4
300
rnA
/LA
V
V
5
rnA
rnA
Q
+15
+4.5
+19
+5.5
+20
+6.0
+25
+7.0
+34
+12
-13
-17 rnA
-18
5
+12
-12
rnA
-15
-23
-15
-34
-2.5
/LA
rnA
/LA
rnA
rnA
333
576
mW
= 25°C
Fig
Min
Typ
6
220
70
Max Unit
350
ns
175
6
70
55
75
,100
ns
JLA1488
Typical Performance Curves
Transfer Characteristics as a
Function of
Power Supply Voltage
2
r>
Vee
±6 V
l
"~
...!1::>
12
+9 v
50_, o
E
I
...
i
\
V"~VO"'
\
-40
~::>
3 kll
0
J II II
0'
04
16
19
-12
-20
-16
20
\..
~
I-- I-I Vee·~:t9 -=
\
il:
iil
0
40
v"
-or VO"~S
f'
-=-
~
vee
0
-75
125
75
TEMPERATURE -
Q
10
10
10
100
DC Test Circuits
Fig. 1
Input Current
+9 V -9 V
14
5
2
4
10
9
12
13
7
?I
t
IIH
+5 V
==
1000
CAPACITANCE-pF
C
Vee
90 V
loe
TEMPERATURE- 0 C
\
12
'0
08 V
-50 ~-+-+--+-+--+--l---+~
16
\
"~
'"
~
'0
Output Slew Rate as a
Function of
Load Capacitance
!1
o
V
-80
1000
~
los
·90Y
19~-=
V"
i\
F= ~
OUTPUT VOLTAGE-V
Maximum Operating
Temperature as a Function of
Power Supply Voltage
l
I\:~
v
INPUT VOLTAGE-V
>
Vee
~
n\..O~~\~~
08 V
12
'O~-+-~-+-~-+-~-+~
'\
\
v"
2
t-..
\.
40
::>
...u
-
1""-
~
I I
0
12.--__: : : - , - - , - - , - - , - - , - - , - - - - ,
20
I I
+1i V
vee,
01-- Vee
Short-Circuit Output
Current as a
Function of Temperature
Output Voltage and Current
Limiting Characteristics
1
6-40
i\
10,000
JLA1488
Fig. 3
Output Short-Circuit Current
Fig. 5
Power-Supply Currents
VCC+ Vcc-
VCC+
14
+1.9 V
10s-1
2
3
4
6
+1.9 V
2
VIH!
4
7
9
9
los.
12
-=
11
V,L
+0.8 V
12
+0.8 V
Vcc-
Fig. 4
Output Resistance (Power-off)
Fig. 6
-o-I3-k
AC Test Circuit and Voltage Waveform
Y,N
3
-1I-=
VOUT
1sPF
CL
4
-=
6
1'S:3V
VOUT
8
±2 Vdc
9
Y,N
~
tPHL
11
10
VOUT - - -.......
13
Ir and If are measured 10% 10 90%
6-41
RL
-------oV
•
f.lA 1489 • f.lA 1489A
RS-232C
Quad Line Receivers
FAIRCHILD
A Sehlumberger Company
Interface Products
Description
The !LA 1489 and the !LA 1489A are EIA RS-232C
specified Quad Line Receivers. These devices are
used to interface data terminals with data
communications equipment. The !LA 1489 and !LA 1489A
are pin-for-pin replacements of the MC 1489 and
MC 1489A respectively.
•
•
•
•
Connection Diagram
14-Pin DIP
IN A
OUT A
INPUT RESISTANCE 3.0 kfl to 7.0 kfl
INPUT SIGNAL RANGE ± 30 V
INPUT THRESHOLD HYSTERESIS BUILT IN
RESPONSE CONTROL
a) LOGIC THRESHOLD SHIFTING
b) INPUT NOISE FILTERING
Absolute Maximum Ratings
Power Supply Voltage
Input Voltage Range
Output Load Current
Continuous Total Power
Dissipation (Note 1)
Operating Temperature
Storage Temperature
Pin Temperatures
Ceramic DIP (Soldering, 60 s)
Molded DIP (Soldering, 10 s)
vee
RESPONSE 2
CONTROL A 3
IN B
RESPONSE 5
CONTROL B
9 RESPONSE
8 CONTROL C
OUT B
GND
+10Vdc
±30 Vdc
20 mA
OUTC
(Top View)
Order Information
Type
Package
!LA 1489
Ceramic DIP
!LA 1489
Molded DIP
/-LA 1489A
Ceramic DIP
!LA 1489A
Molded DIP
800 mW
O°C to 70°C
-65°C to + 175°C
Notes
1 Above 60°C ambient temperature. derate linearly at
83 mw/'e
Circuit Schematic (1/4 of circuit shown)
14
. . . - - _ -...........;..;.Vce
1.6 kll
RESPONSE _2_ _ _ _ _ _ _..........R"'F...,...-+_-.
CONTROL
OUTPUT
3.55 kll
INPUT --iVV\r-1r--..........- - - i : .
10 kll
7
~-....._ - - -....._~~-~--GND
6·42
Code
6A
9A
6A
9A
Part No.
!LA 1489DC
!LA 1489PC
/-LA 1489ADC
!LA 1489APC
JLA 1489 • JLA 1489A
DC Characteristics
Vee = 5.0 V ± 1%, response control pin is open, TA = O°C to 70°C
unless otherwise noted.
Symbol Characteristic
Condition
IIH
Positive Input Current
VIH = 25 V
VIH = 3.0 V
IlL
Negative Input Current
VIL = -25 V
VIL = -3.0 V
VIHL
Input Turn-on Threshold Voltage
VILH
Input Turn-off Threshold Voltage
VOH
Output HIGH Voltage
IlA1489
VOL :S 0.45 V
IlA 1489A
TA=25°C,
VOH 2: 2.5 V,
IL = -0.5 mA
IlA1489
Output LOW Voltage
Output Short-circuit Current
lee
Power Supply Current
Pe
Power Consumption
-3.6
-0.43
-8.3
1.0
1.75
1.5
1.95
2.25
mA
mA
V
1.25
0.75
2
Unit
V
0.75
0.8
1.25
2.6
4.0
5.0
V
0.45
V
2
0.2
3.0
VIH = 5.0 V
4
20
26
mA
VIH = 5.0 V
4
100
130
mW
Unit
Vee = 50 V +
- 1%, TA = 25°C
Condition
Fig
RL = 3.9 kfl
Propagation Delay Time
1
Max
3
VIL = 3.0 V, IL = 10 mA
5
RL = 390 fl
tPHL
1
8.3
IlA14 89A
Symbol Characteristic
tPLH
Typ
2
Input open circuit, IL = -0.5 mA
VOL
Min
3.6
0.43
2
VIH = 0.75 V, IL = -0.5 mA
los
AC Characteristics
TA =25°C,
Fig
tr
Rise Time
RL = 3.9 kfl
tf
Fall Time
RL = 390 fl
5
Min
mA
Typ
Max
25
85
25
50
120
175
10
20
ns
ns
Typical Performance Curves
Input Current as a
Function of
Input Voltage
Input Threshold Voltage as a
Function of
Temperature
24
10
I I I
r- t- ".'''~, )- -
20
60
V
20
""-..;....;,.!'!~IL
./
-
./
V
1-'41489A Vic H
y"
-10
15
08
Y
-60
-25
r-- ~\rIHL
J.l A1489 V ILH
./
50
0
50
INPUT VOLTAGE-V
-
6
-20
,/
Input Threshold Voltage as a
Function of
Power Supply Voltage
I
4
15
I
0
25
60
IlA1489A
I
60
TEMPERATURE - " C
6·43
--
10 1--_-f_4...:.y,::::"'...:.,Ar.;.;'.;;:48;;..9+--+--i
______ ,VI_H (=9=='A~'4~891:==j:==f==I
120
POWER SUPPLY VOLTAGE-V
•
~A1489
• ~A1489A
Performance Curves (Cont.)
IJ.A 1489A Input Threshold
Voltage Adjustment
IJ.A 1489 Input Threshold
Voltage Adjustment
...
VTH=+50Y
50
..
~
)'\H
}IHL
30
§!
~
j!:
:>
0
5.~VrTH+=~+~5_.V-r~~I-,~r-VT~H_=~-5r·~V
y
~
> 40
I
•• r-'--r-r-,~c-r-~'--r-,
RT=..SOkll
RT-<>C>
RT=-11kH
III
Ai~
RT= 5 kn
AT
-=- YTH
'0
1
10
/
RT = 13 kH
VT1=+rv
-1 .... 1
_~T=11kn
I
1
1'"y r I I I
o
-10
-30
30
-1 ~3!-::.~......J~:--.!-....L...-::3':.-'---'-:.'='
......
•.0
INPUT VOLTAGE-Y
INPUT YOLTAGE-V
Test Circuits
Fig. 1
Fig. 3
Input Current
Output Short-Circuit Current
Vee
+5.0 V
V'N
14
14
,.
10
"
12
13
L....---~--1
Fig. 2
11
13
Fig. 4
Output Voltage and Input Threshold Voltage
I
Power Supply Current
Vee
VIHL
Icc
VILH
YIHLO
OPEN 0
50 V
+50V
VILH
14
14
r
10
,.
10
,.
13
VOH
13
-:
Ii
6-44
11
/.LA 1489 • /.LA 1489A
Fig. 5
Fig. 6
AC Test Circuit and Voltage Waveforms
Rl
Response Control Node
VR
50 V
ALL DIODES FD600
OR EQUIVALENT
VOUT
1/4 /1A 1489A
Note
CT = 15 pf = Total parasitic capacitance, which includes probe
and Jig capacitance.
Notes
Capacitor IS for noise filtering
Resistor is for threshold shifting
I, AND If
MEASURED 10%- 90%
•
6-45
f.lA55/751 07Aef.lA751 078
f.lA751 088
Dual Line Receivers
FAIRCHILD
A Schlumberger Company
Interface Products
Connection Diagram
14-Pin DIP
Description
The devices in this series are high-speed, twochannel Line Receivers with common voltage supply
and ground terminals. They are designed to detect
input signals of 25 mV (or greater) amplitude and
convert the polarity of the signal into appropriate TTL
compatible output logic levels. They feature high-input
impedance and low-input currents which induce very
little loading on the transmission line making these
devices ideal for use in party line systems. The
receiver input common mode voltage range is ± 3 V
but can be increased 10' ± 15 V by the use of input
attenuators. Separate or common strobes are
available. The 55/75107 circuits feature an active
pull-up (totem-pole output). The 751 08B circuit
features an open collector output configuration that
permits wired-OR connections. The receivers are
designed to be used with the 55110/75110A line
drivers. These line receivers are useful in high-speed
balanced, unbalanced and party-line transmission
systems and as data comparators.
INAl
IN A2
NC
OUTA
STROBE A
STROBE
GND
(Top View)
Order Information
Type
Package
/-LA551 07 A
Ceramic DIP
/-LA75107A
Ceramic DIP
/-LA75107A
Molded DIP
IlA75107B
Ceramic DIP
/-LA75107B
Molded DIP
IlA75108B
Molded DIP
• HIGH SPEED
• STANDARD SUPPLY VOLTAGES
• DUAL CHANNELS
• HIGH COMMON-MODE REJECTION RATIO
• HIGH INPUT IMPEDANCE
• HIGH INPUT SENSITIVITY
• INPUT COMMON-MODE VOLTAGE RANGE
OF ±3 V
• SEPARATE OR COMMON STROBES
• WIRED-OR OUTPUT CAPABILITY
• HIGH dc NOISE MARGINS
• STROBE INPUT CLAMP DIODES
• INPUT IS DIODE PROTECTED AGAINST POWEROFF LOADING ON B VERSIONS DEVICES
Absolute Maximum Ratings
Supply Voltage (Note 1) .
±7V
Internal Power Dissipation
(Note 3)
670mW
Differential Input Voltage (Note 2) ±6V
Common Mode Input Voltage
(Note 1)
±5V
Strobe Input Voltage (Note 1)
5.5 V
Operating Temperature Range
55107A
-55°C to +125°C
75107A/107B/108B
O°C to +70°C
Storage Temperature Range
-65°C to +150°C
Pin Temperature
Ceramic DIP
(Soldering, 60 s)
300°C
Molded DIP (Soldering, 10 s)
260°C
Code
6A
6A
9A
6A
9A
9A
Part No_
/-LA55107ADM
J.tA75107ADC
/-LA75107APC
/-LA75107BDC
/-LA75107BPC
/-LA75108BPC
Notes
1. These voltages are with respect to network ground terminal.
2. These voltage values are at the noninverting (+) terminal with
respect to the inverting (-) terminal.
3. For Ceramic DIP rating applies to ambient temperatures up to
70°C, above 70·C derate linearly at 8.3 mW I ·C.
6-46
J,lA55/75107A • J,lA751078
J,lA751 088
Equivalent Circuit
14
Vee· -"'--~---1r---"'--~-----"""'r---
Rll
120!!
~--t-- ~
.......
Rl
lkO
R2
1 k!!
R5
R8
4000
4k!!
--,
I
r--';
1.8k!~
I
-~10
I
R9
R6
4.2kO
R12
4kO
AI -'-f---1r
INPUTS {
ZI
R7
760n
Z2
t----oUTA
+--......;...GNO
RIO
1kn
1
A2~2~r----~----J
L---.--------+-~~-STROBEA
R3
3k!1
+-__________+-_......;...6 STROBE
13
Vee
R16
3 k!l
R17
3kn
r-------.....----+---~ STROBE B
B2
INPUTS
11
{
Z3
Bl +
R23
lkn
Z4
12
~~~~l
t- -
-~027
R14
tkO
R15
1 kO
R18
4000
R21
4kn
R22
9
"'---OUTB
028
I
'1.. __ ..I
1.8 k!l R24
-----4~--.....------......----......- -........ -~---l
L - _.....- -.....
Note
Components shown wIth dashed lines are applicable to the
55107A and 751078 only. See description tor dIfferences
between A and 8 verSIons
Pin 3 not connected
6·47
•
J,LA55/75107A • J,LA75107B
J,LA75108B
Truth Table
Circuit Differences Between A and B Versions
The essential difference between the 55/75107 A and
75107B versions is shown in the following
schematics of the input stage:
"A" Version
Differential
Inputs
Strobes
A-B
G
VID 2': 25 mV
Lor H Lor H H
Vee- - - . . - - _ - - . . - - - - ,
Lor H L
-25 mV
<
VID
VID ::; -25 mV
A
<
25 mV L
H
Output
S
H
Lor H H
H
Indeterminate
H
Lor H L
L
Lor H H
H
H
L
B----+---....
Recommended Combinations of
Input Voltage for
Line Receivers
"B" Version
Vee - - _ - _ - - . . - - - - ,
A
+ __.J
B -_ _
INPUT -B-TO-GROUND VOLTAGE- V
The input protection diodes are useful in certain partyline systems which may have multiple Vcc+ power
supplies and, in which case, may be operated with
some of the Vcc+ supplies turned off. In such a
system, if a supply is turned off and allowed to go to
ground, the equivalent input circuit connected to that
supply would be as follows:
"A" Version
INPUT~I
~
~J-
"B" Version
This would be a problem in specific systems which
might possibly have the transmission lines biased to
some potential greater than 1.4 V. Since this is not a
widespread application problem, both the A and B
versions will be available. The ratings and .
characteristic specifications of the B versions are the
same as those of the A versions.
6-48
JLA55/75107A • JLA75107B
JLA75108B
55/75107A,751078
DC Characteristics Ratings apply over full ambient temperature range with VCC+
otherwise noted (Notes 4 & 6)
Symbol
Characteristic
Condition
IIH
Input HIGH Current
IlL
Input LOW Current
= 0.5 V, VCM = -3 V to +3 V
= -2 V, VCM = -3 V to +3 V
VGATE = 2.4 V
VGATE = VCC+
VGATE = 0.4 V
VSTROBE = 2.4 V
VSTROBE = Vcc+
VSTROBE = 0.4 V
IL = -400 /lA,
Vcc+ = MIN
VCM = -3 V to +3 V Vcc- = MIN
ISINK = 16 mA,
Vcc+ = MIN
VCM = -3 V to +3 V Vcc- = MIN
VOUT = 0 (Note 5)
VOUT = VOH, IL = 0, TA = 25°C
VOUT = VOH, IL = 0, TA = 25°C
IIH(G)
Gate Input HIGH Current
IIL(G)
Gate Input LOW Current
IIH(S)
Strobe Input HIGH Current
IIL(S)
Strobe Input LOW Current
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
ISC
Short-Circuit Output Current
ICC+
Positive Supply Current
Icc-
Negative Supply Current
55/75107A,751078
AC Characteristics Vcc+
= +5 V,
Min
VDIFF
= Max and VCC- = Max, unless
Typ
Max
Unit
30
75
/lA
VDIFF
Vcc-
= -5 V,
RL
= 39011,
CL
= 50
-10
/lA
40
/lA
1.0
mA
-1.6
mA
80
/lA
2.0
mA
-3.2
mA
2.4
V
-18
pF, TA
0.4
V
-70
mA
18
30
mA
-8.4
-15
mA
= 25°C. See Test Circuit
ns
tPLH(D)
17
25
tpHdD)
17
25
ns
10
15
ns
10
15
ns
tPLH(S)
Propagation Delay Time
tpHL(S)
Notes
4 For 55107 A guaranteed supply voltage range IS
± 4 5 V to ± 5 5 V Operating temperature range IS
-55°C ~ TA ~ +125°e
For 75107A18 and 751088 guaranteed supply voltage range IS
± 475 V to ± 525 V. Operating temperature range IS
ooe ~ TA ~ 70°C
5 Not more than one (1) output should be shorted at a time
6 Vee- Max Implies Vee- ; -5.5 V or -5 25 V. depending on
deVice type
6·49
•
JlA55/75107A • JlA751078
JlA751 088
751088
DC Characteristics
Ratings apply over full ambient temperature range with VCC+ = Max
Max, unless otherwise noted (Notes 4 & 6)
and Vcc-
=
Symbol
Characteristic
Condition
IIH
Input HIGH Current
VOIFF
IlL
Input LOW Current
IIH(G)
Gate Input HIGH Current
IlL (G)
Gate Input LOW Current
IIH(S)
Strobe Input HIGH Current
IIL(S)
Strobe Input LOW Current
VOL
Output LOW Voltage
IOH
Output HIGH Current
Icc+
Positive Supply Current
Icc-
Negative Supply Current
751088
AC Characteristics
Vcc+
= +5 V,
Min
= 0.5 V, VCM = -3 V to +3 V
VOIFF = -2 V, VCM = -3 V to +3 V
VGATE = 2.4 V
VGATE = VCC+
VGATE = 0.4 V
VSTROBE = 2.4 V
VSTROBE = VCC+
VSTROBE = 0.4 V
ISINK = 16 mA,
Vcc+ = MIN
VCM = -3 V to +3 V Vcc- = MIN
Vcc+ = MIN
VOUT = VCC+
Vcc- = MIN
VOUT = VOH, IL = 0, TA = 25°C
VOUT = VOH, IL = 0, T A = 25°C
= -5 V, RL = 390 fl,
Vcc-
CL
Typ
Max
Unit
30
75
J.lA
-10
J.lA
40
J.lA
mA
1.0
-1.6
mA
SO
2.0
J.lA
mA
-3.2
mA
0.4
V
250
J.lA
1S
30
mA
-S.4
-15
mA
= 15 pF, TA = 25"C. See Test Circuit
tpLH(D)
19
25
ns
tpHL(D)
19
25
ns
13
20
ns
13
20
ns
Propogation Delay Time
tPLH(S)
tpHLCS)
Noles
4. For 55107A guaranteed supply voltage range is
± 45 V to ± 5.5 V. Operating temperature range is
-55°C S; TA S; + 125°C.
For 75107 A / Band 751 08B guaranteed supply voltage range
±4.75 V to ±5.25 V. Operating temperature range IS
DoC S; T A S; 70°C.
5. Not more than one (1) output should be shorted at a time.
6. Vee- Max implies Vee- = -5.5 V or -5.25 V, depending on
device type.
IS
Typical Performance Curves
Input HIGH Current
Into 1A or 2A vs
Ambient Temperature
Output Voltage vs
Differential Input Voltage
100
lsJS8
75188
I--
30
0
5 vi
vee- - sv
Vcc~
Vee_ -0 -5 V
;: INPuTs
INjUTS . 75107AJ8
I
.. i~~g~~/B ..1
15
I
0
j"--...
-,-5V
Vee - -5V
-
N~10
30
-20
10
0
10
20
~25°C
30
DIFFERENTIAL INPUT VOLTAGE-mV
40
on
w
~
0
~
w
AMBIENT TEMPERATURE _
6-50
I
r-- ;5107A!B ....1
I
751088
:-. -..;
tee
40
ls-
I--
I
o
I
I
20
5S107A/B
TA
=--sv
25
80
N~NvJRTINl -
INvelTINt
vcc~
High Logic Level
Supply Current vs
Ambient Temperature
n
0
~
c
_
'I
5
on
w
~
0
~
w
n
AMBIENT TEMPERATURE-DC
~
_
~A55/75107A
~A75107B
•
~A75108B
Performance Curves (Cont.)
55/75107A,75107B
Propagation Delay Time
(Differential Inputs) vs
Ambient Temperature
75108B Propagation Delay Time
LOW-to-HIGH Level vs
Ambient Temperature
120
Vee-
Vcc.=5V
35
!
I
~
~
Q
~
If
• 100
20
15
ik
!Ii~
.....-j
80
:!! so
!i
~
,.
~
~
25
•
25
~
~
~
~
AMBIENTTEMPERATURE-oC
I
!
5
:!!
3S -
1'"
25
20
i ,.
15
~~
20
I
~
.,./
I--
r
~
15
o
1
II:
RL-1950n
R,
I~
3900n
•
I
•
25
~
~
108
•
m
-75
-50
-25
25
50
75
100
125
AMBIENT TEMPERATUAE-" C
t-" k::::
:~~-~~~
30
25
~
20
Z
;. ,."
f
H
tPLH(S)
0
If
-
..... 75107A1S ....1
2
0
•
CL=15pF
F=
Ii
Y
~V
""--75108B
tPLH(S)
tpHLIS)
~
Vcc·=5V
Ycc-.=-sv
Rl'=39DJI
CL"'50pF
30
II
."...
55/75107A,75107B
Propagation Delay Time
(Strobe Inputs) vs
Ambient Temperature
Vcc·=5V
3'
~
_~108.-I
5
AMBIENTTEMPERATURE_oC
75108B Propagation Delay Time
(Strobe Inputs) vs
Ambient Temperature
!
1T
~
30
! -RLI~3911
5
I
rol..J.
•
m
-- J
T
--!'fo'"
40
f 2.
•
I--
R,L ,••L
~
tPHL(D)
vcc!= ••1
Ycc- =-5V
c'I"O·1
•
--+:
II
5
V
... 75107A/B-.J
~1'08.I-l
AJJU
I
30
~
r;
CL=1SpF
CL=50pF
25
5V
vcc-=-sv
~:~~-~~IV
75108B Propagation Delay Time
HIGH-to-LOW Level vs
Ambient Temperature
I
I
-;-HLIS)
.-
·7~5~~~7.25~~.~25~~ro~~7~'-='00~12'
AMBIENT TEMPEAATURE- "C
AMBIENT TEMPERATURE-o C
Voltage Waveforms
~,nomv
INPUTAl -..Ill00mv
STROBE
INPUT
A OR S
\____
,,-----200mV
C~
--+---11--~~
OV
tp2--l
I
3V
tPLH(DI_
OUTPUTA
VOL
6-51
--
--
-- ------------
ILA55/75107A • ILA75107B
ILA75108B
AC Test Circuit
OUTPUT
55107A
75107A/B
DIFFERENTIAL
INPUT
390 Ii
STROBE A
-=
SEE NOTE4
COMMON
STROBE STROBE B
390 Ii
.....~-.....- ' l M -.....- _ - - - - - ~5~ri:~T
50 Ii
STROBE
INPUT
SEE NOTE 2
Cl
-----------------------------------~----_+--~~~
I
SEE NOTE 3
15PF
VCCt -- +5.0 V
Noles
1 The pulse generators have the following characteristics
ZOUT = 50 12, tr = tf = 10 ± 5 ns, tpl = 500 ns, PRR = 1 MHz,
tp2 = 1 ~s, PRR = 500 kHz
2 Strobe Input pulse IS applied to Strobe A when Inputs A l-A2
are being tested to common Strobe when Inputs A l-A2 or
61-62 are being tested, and to Strobe 6 when Inputs 61-62 are
being tested.
3 CL Includes probe and Jig capacitance
4 All diodes are 1N916
Application
The 55175107 A dual line circuits are designed
specifically for use in high-speed data transmission
systems that utilize balanced, terminated transmission
lines such as twisted-pair lines, The system operates
in the balanced mode, so that noise induced on one
line is also induced on the other. The noise appears
common-mode at the receiver input terminals where
it is rejected. The ground connection between the
line driver and receiver is not part of the signal circuit
so that system performance is not affected by
circulating ground currents.
Data is impressed on the balanced-line system by
unbalancing the line voltages with the driver output
current. The driven line is selected by appropriate
driver-input logic levels. The voltage difference
is approximately:
VOIFF
=
1 /2 IOUT(on) . RT
High series line resistance will cause degradation of
the signal. The receivers, however, will detect signals
as low as 25 mV (or less). For normal line resistances,
data may be recovered from lines of several thousand
feet in length.
The unique driver output circuit allows terminated
transmission lines to be driven at normal line
impedances, High-speed system operation is ensured
since line reflections are virtually eliminated when
terminated lines are used. Cross-talk is minimized by
low signal amplitudes and low line impedances.
Line-termination resistors (RT) are required only at the
extreme ends of the line. For short lines, termination
resistors at the receiver only may prove adequate.
The signal amplitude will then be approximately:
The typical data delay in a system is approximately
(30 + 1.3L) ns, where L is the distance in feet
separating the driver and receiver. This delay includes
one gate delay in both the driver and receiver,
VOIFF "'" IOUT(on) . RT
6-52
J,LA55/75107A • J,LA75107B
J,LA75108B
Basic Balanced-Line Transmission System
RT
RT
RT
TWISTED-PAIR OR EQUIVALENT
TRANSMISSION LINE
DATA
Zo
2RT
INPUT
1
2
STROBES
INHIBIT
A
~I
C
RECEIVER
Data-Bus or Party-Line System
TWISTED-PAIR LINE
P
RT
RT
RT
RT
LOCATION 2
DATA
INPUT
DRIVER 1
DRIVER 3
DRIVER 4
INHIBIT
A
C
A
C
LOCATION 1
The strobe feature of the receivers and the inhibit
feature of the drivers allow the 55/75107 A dual line
circuits to be used in data-bus or party-line systems.
In these applications, several drivers and receivers
may share a common transmission line. An enabled
driver transmits data to all enabled receivers on the
line while other drivers and receivers are disabled.
Data is thus time-multiplexed on the transmission line.
The 55/75107A device specifications allow widely
varying thermal and electrical environments at the
various driver and receiver locations. The data-bus
system offers maximum performance at minimum cost.
The receiver threshold level is established by
applying a dc reference voltage to one receiver input
terminal. The signal from the transmission line is
applied to the remaining input. The reference voltage
should be optimized so that signal swing is
symmetrical about it for maximum noise margin. The
reference voltage should be in the range of -3.0 V to
+3.0 V. It can be provided by a voltage supply or by a
voltage divider from an available supply voltage.
Unbalanced or Single-line Systems
INPUT =t>--rro-551751D7A/B
OR
The 55/75107A dual line circuits may also be used
in unbalanced or single-line systems. Although these
systems do not offer the same performance as
balanced systems for long lines, they are adequate
for very short lines where environment noise
is not severe.
OUTPUT
VREF
STROBES
6·53
-~~----
- - - - - ---- -
-~------~-~~~~~-
J,tA55/75107A • J,tA75107B
J,tA75108B
Precautions in the Use of 55/75107A and
751088 Dual Line Receivers
The following precaution should be observed when
using or testing 55175107 A line circuits.
Increasing Common-Mode Input
Voltage Range of Receiver
R1
R2
When only one receiver in a package is being used, at
least one of the differential inputs of the unused
receiver should be terminated at some voltage
between -3.0 V and +3.0 V, preferably at ground.
Failure to do so will cause improper operation of the
unit being used because of common bias circuitry for
the current sources of the two receivers.
R2
R1
751088 Wired-OR Output Connections
The 55175107A and 75108B line receivers feature
a common-mode input voltage range of ± 3.0 V. This
satisfies the requirements for all but the noisiest
system applications. For these severe noise
environments, the common-mode range can be
extended by the use of external input attenuators.
Common-mode input voltages can in this way be
reduced to ± 3.0 V at the receiver input terminals.
Differential data signals will be reduced
proportionately. Input sensitivity, input impedance and
delay times will be adversely affected.
Jo--H"""}--
The 75108B line receivers feature an open-collectoroutput circuit that can be connected in the DOT-OR
logic configuration with other 75108B outputs. This
allows a level of logic to be implemented without
additional logic delay.
6·54
OUTPUT
~A55/75110A
FAIRCHILD
Dual Line Drivers
A Schlumberger Company
Interface Products
Connection Diagram
14-Pin DIP
Description
The ~A55110A and ~A75110A have improved output
current regulation with supply voltage and temperature
variations. The higher current outputs allow data to be
transmitted over longer lines. These drivers offer
optimum performance when used with the ~A55107A,
~A75107A and ~A75108B line receivers.
IN lA
IN 18
INHIC
These drivers feature independent channels with
common voltage supply and ground terminals. The
significant difference between the two drivers is in the
output current specificaiton. The driller circuits feature
a constant output current that is switched to either of
two output terminals by the appropriate logic levels at
the input terminals. The output current can be
switched off (inhibited) by LOW logic levels on the
inhibit inputs.
INH 2C
•
•
•
•
•
•
•
A
X
X
L
X
H
Inhibitor
OUT 2Y
Code
6A
6A
9A
Part No.
IlA55110ADM
~A7511OADC
~A75110APC
Outputs
B
X
C
L
D
X
Y
OFF
Z
X
X
L
X
H
H
H
L
OFF
OFF
H
OFF
H
ON
ON
H
OFF
H
OUT 2Z
GND
Absolute Maximum Ratings
Over operating temperature range, unless
otherwf~e specified
7V
Supply voltage, Vcc+ (Note 1)
-7 V
Supply voltage, VccInput voltage (any input)
5.5 V
Outpu't voltage (any output)
-5 V to 12 V
Continuous totaL dissipation at
TA = 25~C (Noh!' 2)
Cerami'c DIP
900mW
1700 mW
Molqed DIP
Operafing temperature range
-55°C to 125°C
~A55110A
~A75110A
O°C to 70°C
Storage temperature range
-65°C to 150°C
Pin temperature
300°C
Ceramic DIP Soldering (60 s)
Molded PIP Soldering (10 s)
260°C
Function Table
Logic
IN 28
Order Information
Type
Package
~A5511 OA
Ceramic DIP
~A75110A
Ceramic DIP
~A75110A
Molded DIP
NO OUTPUT TRANSIENTS ON POWER-UP OR
DOWN
IMPROVED STABILITY OVER SUPPLY VOLTAGE
AND TEMPERATURE RANGES
CONSTANT-CURRENT,
HIGH-IMPEDANCE OUTPUTS
HIGH SPEED 15 ns
STANDARD SUPPLY VOLTAGES
INHIBITOR AVAILABLE FOR DRIVER SELECTION
HIGH COMMON-MODE OIJTPUT VOLTAGE
RANGE (-3 V to 10 V)
TTL INPUT COMPATIBILITY
Inputs
INH 0
(Top View)
The inhibit feature is provided so the circuits can be
used in party-line or data-bus applications. A strobe or
inhibitor, common to both drivers, is included for
increased driver-logic versatility. The output current in
the inhibited mode, 10(0ff), is specified so that
minimum line loading is induced when the driver is
used In a party-line system with other drivers. The
output impedance of the driver in the inhibited mode is
very high; the output impedance of output transistor is
biased to cutoff.
•
Vee·
IN2A
OFF
Notes
1 Voltage values are with respect to network ground termonal.
2 For operation above 25°C ambient temperature, derate
ceramic pIP at 8 mW/oC and molded DIP at 14 mW/oC
OFF
ON
H = HIGH, L = LOW, X = Don't Care
6-55
---------,"
~---~,-"
•
~A55/75110A
Recommended Operating Conditions
(Note 3)
75110A
55110A
Characteristic
Min
Typ
Max
Min
Typ
Max
Unit
Supply Voltage Vcc+
Supply Voltage VccPositive Common Mode Output Voltage
4.5
-4.5
5
-5
5.5
-5.5
4.75
-4.75
5
-5
5.25
-5.25
V
0
Negative Common Mode Output Voltage
0
-55
10
-3
0
10
-3
125
0
70
0
Operating Ambient Temperature Range
Electrical Characteristics
V
V
V
°C
Over Recommended Operating Ambient Temperature Range (unless otherwise noted)
55110A/75110A
Symbol
Characteristic
Condition (Note 4)
VIH
Input HIGH voltage
VIL
Input LOW voltage
Min
Typ (5)
VIC
Input clamp voltage
Vcc± = MIN, liN = -12 rnA
10(on)
On-state
output current
Vcc± = MAX, VOUT = 10 V
Vcc± = MIN, VOUT = -3 V
12
12
10(011)
Off-state output current
II
IIH
IlL
Input current
at maximum
input voltage
Input
HIGH
Current
A, B or C
Inputs
D Input
Input
LOW
Current
A, B or C
Inputs
Supply current from
Icc+(olf) Vcc+ with driver
inhibited
Supply current from
ICC-(olf) VCC- with driver
inhibited
V
-1.5
V
15
rnA
J.LA
1
rnA
Vcc± = MAX, VIN = 5.5 V
2
40
Vcc± = MAX, VIN = 2.4 V
J.LA
80
-3
rnA
Vcc± = MAX, VIN = 0.4 V
-6
Vcc±
= MAX,
A & B inputs at 0.4 V,
C & D inputs at 2 V
35
-34
-50
21
rnA
A, B, C, & D inputs
at 0.4 V
Vcc+ = 5 V , V'cc-
23
rnA
Vcc± = MAX,
-17
= - 5 V, TA=
Symbol Characteristic
Propagation Delay Time, LOW to HIGH
tpLH
tpLH
Propagation Delay Time, HIGH to LOW
Propagation Delay Time, LOW to HIGH
tpHL
Propagation Delay Time, HIGH to LOW
tpHL
0.8
100
Vcc+ = MIN, VOUT = 10 V
D Input
Supply current from
ICC-(on) VCC- with driver
enabled
AC Character'stlcs
I
6.5
D input
Supply current from
ICC+(on) Vcc+ with driver
enabled
Unit
V
-0.9
A, B or C
Inputs
Max
2
From
To
(Input) (Output) Condition
A or B
Cor D
Notes
3. When usmg only one channel of the hne drivers, the other
channel should be mhiblted and I or its outputs grounded.
4. For condItIons shown as MIN or MAX, use appropriate value
V or Z
Vor Z
CL = 40 pF,
RL = 50 n
See Figures
Min
Typ
Max
Unit
9
15
ns
9
16
13
15
25
ns
ns
25
ns
speCIfied under recommended operating conditions.
5 All typical values are VCC+ = 5 V, VCC- = -5 V, TA = 25°C
6·56
j,tA55/75110A
Characteristic Measurement Information
vcc~
~
I
I -:::l::-
_ _......._
_ _.......__~__
OUr,:UT
OU~UT
RL
50 II
TO OTHER CHANNEL
I
L.---I---~
The pulse generators have the following characteristics
ZOUT = 50!.l, tr = tr = 10 ±5 ns, tw1 = 500 ns, PRR = 1 MHz,
tw2 = 1 ms, PRR = 500 kHz
CL Includes probe and Jig capacitance
For simplicity, only one channel and the inhibitor connections
are shown
AC Test Circuit and Waveforms
/ \
LOGIC
INPUT
AOR B
3V
OV
Iw2
3V
INHIBITOR
INPUT
COR 0
50%
OV
tpLH
tPHL
OFF
OUTPUT
Y
ON
OFF
f
OUTPUT
Z
ON
tPLH
6-57
•
j.LA55/75110A
Typical Applications
Simplex Operation
DATA IN
+
DATA OUT
INHIBIT
SHIELD OR COMMON GROUND RETURN
Half-Duplex Operation
PORT
ENABLES --~_-'
P
~__r - -
PORT
ENABLES
DATA
IN --~_-'
SHIELD OR
COMMON GROUND
RETURN
DATA
OUT
DATA
OUT
Notes
1 All drivers are I'A7511OA or I'A55110A. Receivers are
I'A75107A or I'A75108B. Twisted-pair or coaxial transmission
hne should be used for minimum nOise and cross talk.
2 When only one driver In a package IS being used, the outputs of
the other driver should either be grounded or inhibited to
reduce power dissipation.
6-58
~A75150
FAIRCHIL.D
Dual Line Driver
A Schlumberger Company
Interface Products
Connection Diagram
14-Pin DIP
Description
The 75150 is a monolithic Dual Line Driver designed to
satisfy the requirements of the standard interface
between data terminal equipment and data
communication equipment as defined by EIA Standard
RS-232-C. A rate of 20,000 bits per second can be
transmitted with a full 2500 pF load. Other
applications are in data-transmission systems using
relatively short single lines, in level translators, and for
driving MOS devices. The logic input is compatible
with most TTL and DTL families. Operation is from
+ 12 V and -12 V power supplies.
•
•
•
•
•
•
•
NC
STROBE
INAl
INA2
GND
NC
NC
WITHSTANDS SUSTAINED OUTPUT SHORTCIRCUIT TO ANY LOW-IMPEDANCE VOLTAGE
BETWEEN -25 V AND +25 V
2.0,us MAX TRANSITION TIME THROUGH THE
+3.0 V TO -3.0 V TRANSITION REGION UNDER
FULL 2500 pF LOAD
INPUTS COMPATIBLE WITH MOST TTL AND
DTL FAMILIES
COMMON STROBE INPUT
INVERTING OUTPUT
SLEW RATE CAN BE CONTROLLED WITH AN
EXTERNAL CAPACITOR AT THE OUTPUT
STANDARD SUPPLY VOLTAGES ± 12 V
Absolute Maximum Ratings
Supply Voltage Vcc+
(See Note 1)
Supply Voltage Vcc(See Note 1)
Input Voltage (See Note)
Applied Output Voltage
(See Note)
Operating Temperature
Storage Temperature Range
Pin Temperature
Molded, (Soldering, 10 s)
(Top View)
Order Information
Type
Package
,uA75150
Molded DIP
Part No.
,uA75150PC
Code
9A
Connection Diagram
B-Pin DIP
STROBE
over operating ambient
temperature range,
unless otherwise
noted.
15 V
Vee·
INAl
OUTAl
INA2
OUTA2
GND
Vee-
-15 V
15 V
(Top View)
±25 V
O°C to 70°C
-65°C to 150°C
Order Information
Type
Package
,uA75150
Molded DIP
Noles
1 Voltage values are wIth respect to network ground terminal.
Recommended Operating Conditions
Min Typ
10.8 12
Supply Voltage Vcc+
-10.8 -12
Supply Voltage VccInput Voltage, VI
0
Applied Output Voltage, Vo
Operating Ambient
0
Temperature, TA
Max
Unit
13.2 V
-13.2V
5.5
V
±15 V
70
°C
6-59
Code
9T
Part No.
,uA75150TC
•
JLA75150
Schematic (each line driver)
Vee.
~13~------'------1__------------~t-------~t------,-------------------,
TO OTHER - - - -.....
LINE DRIVER
INPUT
11 kll
15 kll
10 kll
15 kll
_3.;.'-4---------tO-
STROBE---------9--K
TO OTHER _ - - -.....
LINE DRIVER
11,12
OUTPUT
4.5 kll
5
GND -----~--~~-~
TO OTHER - - - -.....
LINE DRIVER
Vee-
~10~
-+________________ __________ ______4-__
______~__________1-____
~
TO OTHER _ - - -.....
LINE DRIVER
Component values shown are nominal
Pins 1, 6, 7, 8, 9, and 14 = not connected
Pin connections are for 14·lead DIP
6-60
~
~
~A75150
DC Characteristics
TA
= 0 to 70°C , unless otherwise specified (Note 2)
Symbol
Characteristic
Test
Figure Condition
Min
VIH
Input HIGH Voltage
1
2.0
VIL
Input LOW Voltage
2
VOH
Output HIGH Voltage
2
VOL
Output LOW Voltage
1
IIH
Input HIGH Current
3
IlL
Input LOW Current
los
Short-Circuit
Output Current
=
=
=
=
5.0
=
=
=
=
=
= 13.2 V,
Vcc- = -13.2 V,
VI = 0.4
ICCH+
Supply Current from
Vcc+, Output High
ICCH-
Supply Current from
Vcc-, Output HIGH
ICCL+
Supply Current from
Vcc+, Output LOW
ICCL-
Supply Current from
Vcc-, Output LOW
AC Characteristics
Vee+
5
10
Strobe Input
2.0
20
Data Input
-1.0
-1.6
Strobe Input
-2.0
-3.2
V
/lA
mA
2.0
10
22
mA
= 25°C
Vcc+ = 13.2 V, Vcc- = -13.2 V,
VI = 3 V, RL = 3 kQ,
-1.0
-10
mA
8.0
17
mA
-9.0
-20
mA
Min
Typ
Max
Unit
0.2
1.4
2.0
/LS
0.2
1.5
2.0
40
/lS
ns
TA
-3.0
mA
15
-15
= 25°C
= 12 V, Vee - = -12 V, TA = 25°C
Test
Figure Condition
Characteristic
tTLH
Transition Time, Output LOW to HIGH
tTHL
Transition Time, Output HIGH to LOW
tTLH
Transition Time, Output LOW to HIGH
tTHL
tpLH
Transition Time, Output HIGH to LOW
tpHL
Propagation Delay Time,
Output HIGH to LOW
Propagation Delay Time,
Output LOW to HIGH
= 2500 pF,
RL = 3 kQ to 7 kQ
CL = 15 pF,
CL
6
6
6
Notes
2 The algebraIc conventIon where the most-posItIve (least·
negatIve) limIt IS deSIgnated as maxImum is used on th,s data
sheet for logIC levels only, e.g, when -5 V IS the maXImum, the
tYPIcal value IS a more negatIve voltage. All tYPIcal values are
at VCC+
12 V, VCC-12 V, TA 25°C.
=
V
8.0
= 25 V
Vo = -25 V
VCC+ = 13.2 V,
VCC- = -13.2 V Vo = 0 V, VI = 3 V
Vo = 0 V, VI = 0 V
Vcc+ = 13.2 V, Vcc- = -13.2 V,
VI = 3 V, RL = 3 kQ,
Symbol
=
V
1.0
TA
5
0.8
-5.0
Vo
4
Unit
-8.0
=
Vcc-13.2 V,
VI 2.4 V
Max
V
r
Vcc+
10.8 V, Vcc-10.8 V,
VIH
2 V, RL
3 kQ to 7 kQ
Data Input
Vcc+
13.2 V,
Vcc+
3
=
Vcc+
10.8 V, Vcc-13.2 V,
VIL
0.8 V, RL
3 kQ to 7 kQ
Typ
=
6-61
RL
= 7 kQ
20
ns
CL
= 15 pF,
60
ns
RL
= 7 kQ
45
ns
•
JLA75150
Typical Performance Curve
Fig.4
lOS
3V
Typical Output Current vs
Applied Output Voltage
Jee.l"v'
20
Vec·
Vcc-
1
r ---
(NOTE)
l~
v,',.Jv
15 r--Vcc-=~12V'--i-F1l-+-+-I
l
~
i
1
TA=25°C
>--I--Vo
.-'
I
10
"t-t--+-:H+++-tiH--+-I
:tt: . . .
I"
U
o _r-"!--
-
~--
R,o 7kll
I-+-++-+-+---l-+f-"'
. . .~ ~L '" 31kO
• -10 I-+-++-+-+---l-+I-+-+-I
II
-15I-+-+-t;;:j.....-~I-+-+-I
lOS IS tested for both Input conditions at each of the specified
output conditions.
yoi'"
Fig.5
-~2~5--~20--~15~-,~O--5~O~0~5-0-,~O-,~5~20~25
ICCH+. ICCH-. ICCL+. ICCLVee.
Vo-APPLIED OUTPUT VOLTAGE-V
Vce-
+I
r~---
ICCH"', leel ...
Test Circuits
it.,
ICCH-. IcCL-
I
V,-....-+--i
Fig. 1
3kll
• Arrows ondlcate actual direction of current flow. Current Into a
termonal IS a posillve value
Fig. 6
Switching Characteristics
Test Circuit
Fig. 2
3V
Vce.
Vce-
rl---l,
PULSE
I
GENERATOR t--~I:-L-.J
(SEE NOTE 1)
I
I
>--t-t--......-
L_-1-_...J
I
OUTPUT
(SEE
CL NOTE 2)
Voltage Waveforms
Each onput IS tested separately
•
I
~<;:10ns
Fig. 3
~=---~=c-t-
IIH. IlL
90%
Vee.
~
'H
-.
V,
hL -
Vec-
__
r l---l,
R=D--t+
SEE
NOTE
I
--1--
I
-------
• , ...
~
I
~IPLH~
I
I
------------~I
.JI
I
I
I
OUTPUT
-3V
Note
When tesllng IIH, the other onput IS at 3 V, when testong IlL, the
other onput IS open
3V
I~---------ov
,-4----5O,I.Is---.I
L..-IPHL
OPEN
•
~~r:
I
I
IL
I
I
goo/a
INPUT
-3V
!
Notes
1. The pulse generator has the followong characterostics duty
cycle oS 50%, ZOUT "'" 50 Il.
2 CL oncludes probe and Jig capacitance
6-62
JLA75154
RS-232C
Quad Line Receiver
FAIRCHILD
A Schlumberger Company
Interface Products
Description
The 75154 is a monolithic Quad Line Receiver
designed to satisfy the requirements of the standard
interface between data terminal equipment and data
communication equipment as defined by EIA Standard
RS-232C. Other applications are for relatively short,
single-line, point-to-point data transmission and for
level translators. Operation is normally from a single
5 V supply; however, a built-in option allows operation
from a 12 V supply without the use of additional
components. The output is compatible with most TTL
and DTL circuits when either supply voltage is used.
Connection Diagram
16-Pin DIP
In normal operation, the threshold control terminals
are connected to the VCCl terminal, pin 15, even if
power is being supplied via the alternate VCC2
terminal, pin 16. This provides a wide hysteresis loop
which is the difference between the positive-going and
negative-going threshold voltages. In this mode of
operation, if the input voltage goes to zero, the output
voltage will remain LOW or HIGH as determined by the
previous input.
(Top View)
Order Information
Type
Package
IlA 75154
Ceramic DIP
IlA 75154
Molded DIP
For fail-safe operation, the threshold-control terminals
are open. This reduces the hysteresis loop by causing
the negative-going threshold voltage to be above
zero. The positive-going threshold voltage remains
above zero as it is unaffected by the disposition of the
threshold terminals. In the fail-safe mode, if the input
voltage goes to zero or an open-circuit condition, the
output will go HIGH regardless of the previous
input condition.
Code
68
98
Absolute Maximum Ratings
Normal Supply Voltage
(Pin 15), VCCl (Note 1)
Alternate Supply Voltage
(Pin 16), VCC2 (Note 1)
Input Voltage (Note 1)
Continuous Total Power
Dissipation (Note 2)
Operating Temperature Range
Storage Temperature Range
Pin Temperatures
Molded DIP (Soldering, 10 s)
Ceramic DIP (Soldering, 60 s)
The 75154 is characterized for operation from 00 C
to 70 0 C.
• INPUT RESISTANCE-3 kl1 TO 7 kl1 OVER FULL
RS-232C VOLTAGE RANGE
• INPUT THRESHOLD ADJUSTABLE TO MEET
FAIL-SAFE REQUIREMENTS WITHOUT USING
EXTERNAL COMPONENTS
• BUILT-IN HYSTERESIS FOR INCREASED
NOISE IMMUNITY
• INVERTING OUTPUT COMPATIBLE WITH
DTL OR TTL
• OUTPUT WITH ACTIVE PULL-UP FOR
SYMMETRICAL SWITCHING SPEEDS
• STANDARD SUPPLY VOLTAGES-5 V OR 12 V
Part No_
Il A75154DC
Il A75154PC
7V
14 V
±25 V
800 mW
O°C to 70°C
-65°C to 150°C
260°C
300°C
Recommended Operating Conditions
Normal Supply Voltage
(Pin 15), VCCl
Alternate Supply Voltage
(Pin 16), VCC2
Input Voltage
Normalized Fan Out from
Each Output, N
Operating Ambient
Temperature Range
Min
Typ
Max
Unit
4.5
5
5.5
V
10.8
12
13.2 V
± 15 V
10
a
70
Notes
1. Voltage values are wIth respect to the network
ground termmal.
2. Above 60°C ambIent temperature, derate hnearly
at 8.3 mW / °C.
6·63
DC
•
/-LA75154
Equivalent Circuit
---------1
'---I
COMMON TO 4 CIRCUITS
I
I
I
I
I
16
SEE
N~Ci~ -+---~--,
BELOW
32kn
Veel .;::15,--+_ _ _~
1 OF 4 RECEIVERS
1,2,
THRESHOLD
CONTROL
_3,_14-+-_¥v-~.--,
10, 11, 12, 13
+---+- OUTPUT
4,5.6,7
5kD
5 k!l
4 2 kn
INPUT -+_Vv'--+--~--1[
I
GND-+------~
I
I
L ___ ~
27 k!!
I
1 kn
I
I
L _________ ~
Notes
Component values shown are normal.
When uSing VCCI (pm 15), VCC2 (pin 16) may be left open or
shorted to V CC 1· When using V CC2, VCC 1 must be left open or
connected to the threshold control pins.
DC Characteristics
TA = 0 to 70°C unless otherwise specified (Note 5)
Symbol
Characteristic
Test
Figure Condition
Min
V,H
Input HIGH Voltage
1
3.0
V,L
Input LOW Voltage
-3.0
Positive-Going
Threshold Voltage Fail-Safe Operation
1
VT-
Normal Operation
Negative-Going
Threshold Voltage Fail-Safe Operation
1
VT+ - VT-
Hysteresis
VOH
Output HIGH Voltage
1
10H = -400 J.LA
VOL
Output LOW Voltage
1
10L = 16 mA
~V, = -25 V to -14 V
Normal Operation
Fail-Safe Operation
Input Resistance
1
2
3.0
-3.0
-1.1
0
0.8
1.4
3.0
0.8
3.3
6.0
0
0.8
2,2
2.4
3,5
0.4
5.0
7.0
7.0
3.0
5.0
6.0
~V,
= 3 V to 14 V
3.0
5.0
~VI
= 14 V to 25 V
V
V
V
V
V
0.23
3.0
V
kll
7.0
3.0
5.0
7.0
0
0.2
2.0
V
VeC1 = 5.5 V, V, = -5 V -10
-20
-40
mA
VCC1 = 5.5 V, TA = 25°C
20
35
VCC2 = 13.2 V,
TA=25°C
23
40
los
Short-Circuit Output Current (Note 3)
4
ICCI
Supply Current from VCC1
6-64
2.2
= -14 V to -3 V
I, = 0
Notes on following pages.
0.8
= -3 V to 3 V
3
Supply Current from VCC2
3.0
~VI
Open-Circuit Input Voltage
ICC2
2.2
~V,
V, (open)
5
0.8
3.0
Unit
V
1
Normal Operation
VT+
RI
Typ(4) Max
mA
~A75154
AC Characteristics
VCCl
= 50 V , TA = 25°C , n = 10
Test
Figure Condition
Symbol
Characteristic
tPLH
Propagation Delay Time, LOW-to-HIGH
22
ns
tPHL
Propagation Delay Time, HIGH-to-LOW
20
ns
tTLH
Transition Time, LOW-to-HIGH
9.0
ns
tTHL
Transition Time, HIGH-to-LOW
6.0
ns
Min
CL = 50 pF, RL = 390 Q
6
Typ
Max
Unit
Typical Characteristics
Output Voltage Versus Input Voltage
VCC1=50V
TA == 25°C
J,
NORMAL
O~~I~A~6~ -+-
OPERATION
n
VT-
VT_
----Jt
1
VT·
JL
n
n
"
25
INPUTVOLTAGE-Y
•
Note
For normal operation. the threshold controls are connected to
V CC 1, Pin 15. For fall· safe operation, the threshold controls are
open
Notes
3. Not more than one output should be shorted at a time.
4. All typical values are at VCCI
5 V. TA
25°C.
5. The algebraic convention where the most-positive (leastnegative) limit is designated as maximum is used in this data
sheet for logic and threshold levels only. e.g .. when -3 V is the
maximum. the minimum limit is a more-negative voltage.
=
=
6-65
JLA75154
DC Test Circuits
o 13.2 V
55V 0
10H
VI. Vr
liN
I
---1---
L
GND
Note
Arrows indicate actual direction of current flow. Current Into a
terminal IS a positive value.
Test Table
VCC1
VCC2
(Pin 15)
(Pin 16)
IOH
4.5 V
Open
IOH
Open
10.8 V
Open
IOH
5.5 V
Open
0.8 V
Open
IOH
Open
13.2 V
VOH
Note 6
Pin 15
IOH
5.5 V and T
Open
IOH
T
13.2 V
Open
Test
Measure
In
T
Out
Open-circuit input
VOH
Open
Open
(fail safe)
VOH
Open
Open
VT+ min,
VOH
0,8 V
VT- min (fail safe)
VOH
VT + min (normal)
VOH
Note 6
Pin 15
VIL max,
VOH
-3V
Pin 15
IOH
5.5 V and T
VT - min (normal)
VOH
-3 V
Pin 15
IOH
T
13.2 V
VIH min, VT + max,
VOL
~V
Open
IOL
4.5 V
Open
VT- max (fail safe)
VOL
3V
Open
IOL
Open
10.8 V
VIH min, VT+ max
VOL
3V
Pin 15
IOL
4.5 V and T
Open
(normal)
VOL
3V
Pin 15
IOL
T
10.8 V
VOL
Note 7
Pin 15
IOL
5.5 V and T
Open
VOL
Note 7
Pin 15
IOL
T
13.2 V
VT - max (normal)
Notes
6. Momentarily apply -5 V, then 0.8 V.
7. Momentarily apply 5 V, then ground.
6·66
J.LA75154
DC Test Circuits (Cont)
Fig.2
R,
Fig.4
lOS
OPEN
55V
OPEN
OPEN
_k--.b_~
Vee1
50V
Fig.5
Rl
I
OUTI
I
L
Nole
Each output
VCC2
IS
---T--- J
I
~ los
GND
tested separately
ICC
Test Table
T
VCC1
VCC2
(Pin 15)
(Pin 16)
Open
5V
Open
Open
GNO
Open
Open
Open
Open
Pin 15
T and 5 V
Open
GNO
GNO
Open
Open
Open
12 V
Open
Open
GIliO
Pin 15
T
12 V
Pin 15
T
GNO
Pin 15
T
Open
Fig. 3
--t
VI (open)
0
55V:1
0--<:>
50V
Noles
All four hne receivers are tested simultaneously.
Arrows indicate actual directIOn of current flow. Current Into a
terminal IS a positive value
132V
OPEN
~T
15
-
Veel
J
16
VCC2 -
1
R1
I
OUTI
>0----':::0:.;1-
VllOPENll
iL----j---
J
OPEN
Test Table
T
VCC1
(Pin 15)
VCC2
(Pin 16)
Open
5.5 V
Open
Pin 15
5.5 V
Open
Open
Open
13.2 V
Pin 15
T
13.2 V
>c>-----i-- OPEN
6-67
•
JLA75154
AC Characteristics
Test Circuit
INPUT
5.0V
OPEN
15
i---T---Vee1
PULSE
GENERATOR
NOTE1
OUTPUT
OPEN
-~-~-I
Vee2
I
RL ~ 390!l
R1
liN
I
L ----r---- J
GND
Notes
1 The pulse generalor has Ihe following charaClerlSllcs:
ZOUT = 50 ~!, IW = 200 ns, duly cycle 00; 20%
2 CL includes probe and Jig capacllance.
3 All diodes are 1N3064.
Voltage Waveforms
6-68
I
CL~50PF
NOTE 2
jlA9640/26S10
F=AIRCHILO
Quad General-Purpose
Bus Transceiver
A Schlumberger Company
Interface Products
Description
The JLA9640 is a High-Speed Quad Bus Transceiver.
Each driver output, which is capable of sinking 100 rnA
at 0.8 V, is connected internally to the high-speed bus
receiver in addition to being connected to the package
pin. The receiver has a Schottky TTL output capable
of driving ten Schottky TTL unit loads. The bus output
is capable of driving lines having 100 Q impedance.
Connection Diagram
16-Pin DIP
GND1
BUSA
RECEIVER
OUT A
DRIVER
IN A
DRIVER
IN B
RECEIVER
OUT B
The line can be terminated at both ends and still give
considerable noise margin at the receiver. The
receiver typical switching point is 2.0 V.
RECEIVER
OUT D
13 DRIVER
IN D
4
5
6
STROBE
DRIVER
10
IN C
RECEIVER
9
OUT C
7
BUSB
The JLA9640 features advanced Schottky processing
to minimize propagation delay. The device package
also has two ground pins to improve ground current
handling and allow close decoupling between Vee and
ground at the package. Both GND1 and GND2 should
be tied to the ground bus external to the
device package.
LOGICGND
BUSC
(Top View)
Order Information
Type
Package
JLA9640
Ceramic DIP
JLA9640
Ceramic DIP
JLA9640
Molded DIP
The JLA9640 is a pin for pin replacement for
the AM26S 1O.
•
•
INPUT TO BUS IS INVERTING
QUAD HIGH-SPEED OPEN COLLECTOR
BUS TRANSCEIVERS
• DRIVER OUTPUTS CAN SINK 100 mA AT
0_8 V MAXIMUM
• ADVANCED SCHOTTKY PROCESSING
• PNP INPUTS TO REDUCE INPUT LOADING
Absolute Maximum Ratings
Supply Voltage to
Ground Potential
DC Voltage Applied to
Outputs for High
Output State
DC Input Voltage
Output Current, into Bus
Output Current, into Outputs
(Except Bus)
DC Input Current
Operating Temperature
JLA9640DM
JLA9640DC / PC
Storage Temperature
Pin Temperatures
Molded DIP (Soldering 10 s)
Ceramic DIP (Soldering 60 s)
3
Code
6B
6B
9B
Part No.
JLA9640DM
JLA9640DC
JLA9640PC
Truth Table
Inputs
Strobe
H
L
-0.5 V to +7 V
Outputs
Driver INA-D
BusA_D Receiver OutA_D
L
L
H
L
L
H
L
H
H
x
y
y
= HIGH Voltage Level
= LOW Voltage Level
x = Don't Care
Y
-0.5 V to +Vee Max
-0.5 V to +5.5 V
200 rnA
= Voltage Level of Bus (Assumes control by
another bus transceiver)
30 rnA
-30 rnA to +5.0 rnA
-55°C to +125°C
O°C to +70°C
-65°C to +150°C
6-69
•
JLA9640/26S10
Recommended Operating Conditions
Military (4)
Commercial (5)
Characteristic
Min
Typ
Positive Supply Voltage
Operating Ambient Temperature - TA
4.50
-55
5.0
+25
DC Characteristics
Min
Typ
Max
Unit
5.5
+125
4.75
5.0
+25
5.25
+70
V
0
Condition (Note 1)
Output HIGH
Voltage
Vee = MIN.
IOH = -1.0 mAo
(Receiver Outputs)
Mil (4)
Min
Typ (2)
2.5
3.4
2.7
3.4
Max
VOL
Output LOW Voltage
(Receiver Outputs)
VIH
Input HIGH Level
(Except Bus)
Guaranteed Input Logic HIGH
for all inputs
VIL
Input LOW Level
(Except Bus)
Guaranteed Input Logic LOW
for all inputs
VI
Input Clamp Voltage
(Except Bus)
Vee
IlL
Input LOW Current
Vee = MAX.
VIN = 0.4 V
ENABLE
-0.36
DATA
-0.54
IIH
Input HIGH Current
Vee = MAX.
VIN = 2.7 V
ENABLE
20
DATA
30
IIH
Input HIGH Current
VCC
VIN
Vee = MAX
Enable = GND
V
100
45
70
mA
IJ.A
IJ.A
mA
mA
= +25°C. Vee = 5.0 V
Symbol
Characteristic
Condition
tpLH. tpHl
Data Input to Bus
tpLH. tpHl
Enable Input to Bus
RS
Cs
tpHL. tpHl Bus to Receiver Out
Bus
-1.2
-60
Power Supply Current
(All Bus Outputs LOW)
Bus
V
-18
ICCl
tr
0.8
-55
Comm (5)
V
V
-20
(Note 3)
tf
2.0
= MAX. VIN = 5.5 V
Mil (4)
Vce = MAX
Output Short-Circuit
Current (Except Bus)
TA
0.5
= MIN. liN = -18 mA
Ise
Unit
V
= VIL or VIH Comm (5)
Vee = MIN. IOl = 20 mA
VIN = VIL or VIH
AC Characteristics
°C
Over operating temperature & voltage range. unless otherwise specified.
Symbol Characteristic
VOH
Max
Min
= 50 n.
= 50 pF (Note 6)
RS = 50 n. RL = 280 n.
Cs = 50 pF. CL = 15 pF (Note 6)
RS = 50 n.
Cs = 50 pF (Note 6)
Notes
1. For conditions shown as Min or Max. use the appropriate value
specified under Electrical Characteristics for the applicable
device type.
2. Typical limits are at VCC = 5.0 V. 25°C ambient
and maximum loading.
Typ
Max
10
15
ns
14
18
ns
10
15
ns
Unit
4.0
10
ns
2.0
4.0
ns
3. Not more than one output should be shorted at a time. Duration
of the short-Circuit test should not exceed one second.
4. Military temperature range, ceramic DIP
5. Commercial temperature range, ceramic or molded DIP
6. Includes probe and Jig capacitance.
6-70
j
/lA9640/26S10
Bus Input/Output Characteristics
Symbol Characteristic
Output LOW Voltage
Vee
= Min
Cornrn (Note 5)
10
Bus Leakage Current
Vee
= Max
Mil (Note 4)
Cornrn (Note 5)
(Power On)
10FF
Bus Leakage Current
(Power Off)
Vo
VTH
Receiver Input
HIGH Threshold
Bus Enable
Vee = Max
= 2.4 V
VTL
Receiver Input
LOW Threshold
Bus Enable
Vee = Min
= 2.4 V
Fig. 1
Max
10L
0.33
0.5
10L
0.42
0.7
0.51
0.8
0.33
0.5
0.42
0.7
0.51
0.8
Min
Mil (Note 4)
VOL
Typ (2)
Condition (Note 1)
= 40 rnA
= 70 rnA
10L = 100 rnA
10L = 40 rnA
10L = 70 rnA
10L = 100 rnA
Vo = 0.8 V
Vo = 4.5 V
Vo = 4.5 V
OM
2.0
2.4
DC,PC
2.0
2.25
OM
1.6
2.0
DC,PC
1.75
2.0
AC Test Circuit
RECEIVER
OUT
Vee
Rl
280 Q
CB
50pF
NOTE
I
Cl
BUS
TEST
POINT
Note
Includes probe and JIg capacItance.
Fig. 2
Waveforms
RECEIVER OUT
TEST POINT
6-71
I
NOTE
15PF
/-LA
100
100
TEST
POINT
V
-50
200
= 4.5 V
Vee
Unit
ALL DIODES
lN916 OR
EQUIVALENT
/-LA
V
V
~A3448A
FAIRCHILD
Quad Instrumentation
Bus (GPIB) Transceiver
A Schlumberger Company
Interface Products
Connection Diagram
16-Pin DIP
Description
is a 3-state bidirectional Quad Bus
Transceiver operating from a single +5 V supply. It
interfaces between TTL or MOS logic and the IEEE
Standard Instrumentation Bus (488-1975), often
referred to as GPIB. The required bus termination is
internally provided.
~A3448A
BUSA
PULL-UP 4
ENABLE
INPUTA-B 5
DATAB
Truth Table
Info. Flow
Comments
Bus ..... Data
Data ..... Bus
Data ..... 8us
Active Pull-Up
Open Collector
DATAC
Order Information
Type
Package
JlA3448A
Molded DIP
JlA3448A
Ceramic DIP
-65 to +150°C
X
1
0
BUS C
(Top View)
o to +70°C
Enable
. .TOlL---'
SEND/REC.
INPUT C
7.0 V
5.5 V
150 mA
150°C
0
1
1
BUS 0
PULL-UP
ENABLE
INPUT CoD
SEND/REC.
INPUT B
TA = 25°C unless
otherwise noted
Send/Rec.
DATA 0
--.c='L---'
BUSB
• 3-STATE OUTPUTS
• SCHOTTKY TECHNOLOGY
• HIGH IMPEDANCE INPUTS
• RECEIVER HYSTERESIS-6DO mV
• SINGLE +5 V SUPPLY
• POWER UP/POWER DOWN PROTECTION
• NO BUS LOADING WHEN POWER IS REMOVED
Power Supply Voltage
Input Voltage
Driver Output Current
Junction Temperature
Operating Ambient
Temperature Range
Storage Temperature Range
Pin Temperatures
Molded DIP (Soldering, 10 s)
Ceramic DIP (Soldering, 60 s)
Vee
15 SEND/REC.
INPUT 0
DATA A
The receivers have built-in input hysteresis to improve
noise margin, and their input loading follows the bus
standard specifications.
Absolute Maximum Ratings
16
SEND/REC.
INPUT A
-
x = Don't Care
6-72
Code
98
78
Part No.
JlA3448APC
JlA3448ADC
JlA3448A
DC Characteristics
Symbol
Unless otherwise noted, 4.75
TA = 25°C, VCC = 5.0 V
Characteristic
VCC :::; 5.25 V and 0:::; TA:::; 70°C; typical values are at
Condition
Min
Bus Pin Open, VIN(S/R)
IBUS = -12 mA
VB US
Bus Voltage
VIC(BUS)
IBUS
v:::;
= 0.8 V
Bus Current
5.0 V :::; VBUS :::; 5.5 V
VBUS = 0.5 V
VCC = 0 V, 0 V :::; VBUS :::; 2.75 V
Typ
Max
Unit
2.75
3.7
-1.5
V
V
0.7
-1.3
2.5
-3.2
+0.04
mA
mA
mA
= 0.8 V
= 0.8 V, LOW to HIGH
400
600
HIGH to LOW
0.8
1.6
1.0
Receiver Input Hysteresis
VIN(S/R)
VILH(R)
VIHL(R)
Receiver Input Threshold
VIN(S/R)
VIN(S/R)
VOH(R)
Receiver Output HIGH Voltage VIN(S/R) = 0.8 V, 10H(R)
VBUS = 2.0 V
= -800 p,A
VOL(R)
Receiver Output LOW Voltage VIN(S/R) = 0.8 V, 10L(R)
VSUS = 0.8 V
= 16 mA
10S(R)
Receiver Output Short-Circuit
Current
= 2.0 V
VIH(O)
= 0.8 V,
VIN(S/R)
= 0.8 V,
Driver Input HIGH Voltage
VIN(S/R)
VIL(O)
Driver Input LOW Voltage
VIN(S/R)
liN (D)
IIB(O)
Driver Input Current
Data Pins
= 2.0 V
= 2.0 V
= VIN(E) = 2.0 V
VIN(S/R)
0.5 V :::; VIN(O) :::; 2.7 V
VIN(O) = 5.5 V
IIN(S/R)
IIB(S/R)
Input Current
Send / Receive
liN (E)
IIB(E)
VB US
mV
1.8
2.7
V
V
V
-15
0.5
V
-75
mA
2.0
V
0.8
V
200
40
200
p,A
A
0.5 V :::; VIN(S/R) :5 2.7 V
VIN(S/R) = 5.5 V
-100
20
100
p,A
p,A
Input Current
Enable
0.5 V :::; VIN(E) :::; 2.7 V
VIN(E) = 5.5 V
-200
20
100
p,A
p,A
VIC (D)
Driver Input Clamp Voltage
VIN(S/R)
-1.5
V
VOH(O)
Driver Output HIGH Voltage
VOL (D)
Driver Output LOW Voltage
(Note)
10S(0)
Output Short·Circuit Current
ICCL
ICCH
Power Supply Current
= 2.0 V, IIC(O) = -18 mA
VIN(S/R) = 2.0 V, VIH(O) = 2.0 V
VIH(E) = 2.0 V, IOH = -5.2 mA
VIN(S/R)
2.5
V
= 2.0 V, 10L(0) = 48 mA
VIN(S/R) = 2.0 V, VIH(O)
VIH(E) = 2.0 V
= 2.0 V,
0.5
V
-120
V
63
106
85
125
mA
-30
Listening Mode, All Receivers On
Talking Mode, All Drivers On
Note
A modIficatIon of the IEEE 488·1975 Bus Standard changes
VOL (D) from 0.4 to 0.5 V maximum to permit the use of
Schottky technology.
AC Characteristics VCC
Symbol Characteristic
tpLH(O)
tpHL(O)
tpLH(R)
tpHL(R)
=5 0 V
TA
= 25 ° C unless otherwise noted
Condition
Typ
Max
Unit
Propagation Delay of Driver
Output LOW to HIGH
Output HIGH to LOW
Min
10
11
15
17
ns
ns
Propagation Delay of Receiver
Output LOW to HIGH
Output HIGH to LOW
20
16
25
23
ns
ns
6-73
•
JLA3448A
AC Characteristics (Cont.) Vee
Symbol
Characteristic
tPHZ(R)
tpZH(R)
tpLZ(R)
tpZL(R)
= 5.0 V, TA = 25
0
C unless otherwise noted
Typ
Min
Max
Unit
Propagation Delay Time-Send/Receiver to Data
Logic HIGH to Third State
Third State to Logic HIGH
Logic LOW to Third State
Third State to Logic LOW
30
30
30
30
ns
ns
ns
ns
tpHZ(D)
tpZH(D)
tpLZ(D)
tpZL(D)
Propagation Delay Time-Send/Receiver to Bus
Logic HIGH to Third State
Third State to Logic HIGH
Logic LOW to Third State
Third State to Logic LOW
30
30
30
30
ns
ns
ns
ns
tpOFF(E)
tpON(E)
Turn-On Time-Enable to Bus
Pull-Up Enable to Open Collector
Open Collector to Pull-Up Enable
30
20
ns
ns
Typical Performance Curves
Typical Receiver
Hysteresis Characteristics
Vee'" 5 ov
140
Vee == 5 0 v
TA
Typical Bus Load Line
-----,f-+---+-l--+---l
25°C
.
"
g~30f-4--+--~4--4--++~-j
.
2.
"I
~2
•
~4
•
--
....
~
520r-~-+--r---j-~--++~-j
~
o
I
~
~1.
~12
~14
~4
VIN -
INPUT VOLTAGE -
•
V
-2.
20
VBUS -
BUS VOLTAGE -
AC Test Circuits and Waveforms
Bus Input to Data Output (Receiver)
TO SCOPE
(INPUT)
TO SCOPE
(OUTPUT)
50V
240
n
~tPLHIR)
OUTPUT
CLO
30 pF
lN916
OR
EQUIV
(NOTE)
SENOI
-=- REC
f = 10 MHz
tTLH = tTHL :oS 5 0 ns (10%-90%)
Duty Cycle = 50%
"Includes Jl9 and probe capacitance
6-74
15 V
40
V
60
~A3448A
AC Test Circuits and Waveforms (Cont.)
Data Input to Bus Output (Driver)
TO SCOPE
(INPUT)
TO SCOPE
(OUTPUT)
3.0
v
~
2.3 V
INPUT
15V
ORENA~
SEND/
L-....-+--+
REC
38.3!l
I='PLHIOI
~/;'OV
BUS
PULL-UP ENABLE
==--
f = 1.0 MHz
tTLH = tTHL :s 5.0 ns (10%-90%)
Duty Cycle = 50%
CLI30PF
(NOTE)
·Includes Jig and probe capacitance
Send/Receive Input to Bus
Output (Driver)
30
TO SCOPE
(OUTPUT
v
~.
ZH
f:=VOH
90%
SEND/REC
;;~: I: ;~'P_H_Z(_O_'
ZH
TO SCOPE
(INPUT)
ov
______________________J.
ZL
DATA
F'"
~.
2.0 V
___VZ____"_O_V________-+__,
-VZ"" 1.1 V
51 !l
CL*
PULSE
480
n
13.511
------1--':
-=-
10%
------------------
11 V
f = 1.0 MHz
CL = 1 5 pF (Includes Jig and probe capacitance)
tTLH = tTHL :s 5.0 ns (10%-90%)
Duty Cycle = 50%
6-75
•
~A3448A
AC Test Circuits and Waveforms (Cont.)
Send/Receive Input to
Data Output (Receiver)
TO SCOPE
(OUTPUT)
::1.
50 V
280 II
~..
tPZHIRI-"
DATA
BUS
SEND/REC
90%
OUTPUT
HIGH
TO OPEN
ZH
ZL
rr
3.0
v
OV
VOH
OV
TO SCOPE
(INPUT)
51 n
PULSE
CL
= 1 5 pF
CL'
3 kH
---+-"';
10%
f = 1.0 MHz
(Includes Jig and probe capacitance)
tTLH = tTHL ::5 5.0 ns (10%-90%)
Duty Cycle = 50%
Enable Input to Bus Output (Driver)
30
TO SCOPE
(OUTPUT)
v
ENABLE
1.5 V
INPUT~
tPON(E)
DATA
SENDIREC
OUTPUT
TO SCOPE
(INPUT)
51
n
CL'
480
n
t
j'"
f=1.0MHz
tTLH = tTHL ::5 5.0 ns (10%-90%)
Duty Cycle = 50%
CL = 1 5 pF (Includes Ji9 and probe capacitance)
6-76
I
0V
-iIPOFFIEI
-"='""
Voe
J-LA3448A
Simple System Configuration
15 V
,---I
I
T/R2
4- "A3448A
I
I
EOl
EO,
DBo-DBl
00-07
TiFf,
BUS
MANAGEMENT
SRO
SRO
REN
REN
R/IN
R/IN
F6802
OR
F6800
MPU
IFe
IFe
ATN
ATN
NDAC
DAe
RSo-RS2
IRO
BUS
HANDSHAKE
CI)
NRFD
RFD
DAV
DAV
::>
F68488
GPIA
ID
..."'~
'....."
DlO,
mo
0108
.-+------+---r-~ffi7
w
w
!!!
DATA
TRIG +--+----~
Notes
1. Although the I'A3448A transceivers are non-inverting, the
488-1975 bus callouts appear inverted with respect to the
F68488 pin designations. This is because the 488-1975
Standard is defined for negative logiC, while all F6800 MPU
components make use of positive logic format.
2. Unless proper considerations are provided, it is recommended
that the pull-up enable pins on the I'A3448As be grounded,
selecting the open-collector mode.
6-77
•
JLA8T26A • JLA8T28
Quad 3-State
Bus Transceivers
FAIRCHILD
A Schlumberger Company
Interface Products
Connection Diagrams
16-Pin DIP
Description
,uAST26A and ,uAST2S are Quad 3-State 8us
Transceivers featuring MPU or MOS compatibility.
80th parts feature high-impedance pnp inputs and
high-speed operation made possible by the use of
Schottky transistor technology.
,uABT26A
RECEIVER
ENABLE
INPUT
RECEIVER
OUTPUT 1
These devices are useful as bus extenders in systems
employing the F6S00, F3S70 or other comparable
MPU families. Maximum input current of 200 ,uA at the
device input pins assures proper operation despite
limited drive capability of the MPU chip.
BUS 1
DRIVER
INPUT 1
DRIVER
INPUT 4
RECEIVER
OUTPUT 3
BUS 2
DRIVER
INPUT 2
• ,uA8T26A-INVERTING BUS
• ,uA8T28- NON-INVERTING
• MPU COMPATIBLE
• HIGH-IMPEDANCE pnp INPUTS
• HIGH-SPEED SCHOTTKY TECHNOLOGY
• +5 V SINGLE SUPPLY OPERATION
• 3-STATE DRIVERS AND RECEIVERS
Power Supply Voltage (Vee)
Input Voltage (VI)
Junction Temperature (T J)
Ceramic DIP
Molded DIP
Operating Temperature
Storage Temperature
Pin Temperature
Molded DIP (Soldering, 10 s)
Ceramic DIP (Soldering, 60 s)
BUS 4
RECEIVER
OUTPUT 2
The ,uAST26A / 2S are identical to the NEST26A / 2S or
the MCST26A / 2S.
Absolute Maximum Ratings
Vee
15 DRIVER
ENABLE
14 INPUT
RECEIVER
OUTPUT 4
BUS 3
DRIVER
INPUT 3
GND
(Top View)
Order Information
Type
Package
,uAST26A
Ceramic DIP
,uAST26A
Ceramic DIP
,uAST26A
Molded DIP
TA = 25°C unless
otherwise noted
S.O V
Code
68
68
Part No.
,uAST26ADM
,uAST26ADC
,uAST26APC
98
5.5 V
Connection Diagram
,uABT2B
175°C
150°C
-55°C to +125°C
-65°C to +150°C
RECEIVER
ENABLE
INPUT
RECEIVER
OUTPUT 1
Vee
15 DRIVER
ENABLE
14 INPUT
RECEIVER
OUTPUT 4
BUS 1
DRIVER
INPUT 1
BUS 4
RECEIVER
OUTPUT 2
DRIVER
INPUT 4
RECEIVER
OUTPUT 3
BUS 2
DRIVER
INPUT 2
BUS 3
DRIVER
INPUT 3
GND
(Top View)
Order Information
Type
Package
,uAST2S
Ceramic DIP
,uA8T2S
Ceramic DIP
,uAST2S
Molded DIP
6·78
Code
68
68
98
Part No.
,uAST2SDM
,uAST2SDC
,uAST2SPC
J.LA8T26A • J.LA8T28
Bidirectional Bus Application
TO OTHER
DRIVERS/RECEIVERS
RECEIVER
OUTPUTS
1
( RECEIVER
DRIVER
INPUTS
1
(DRIVER
DRIVER
ENABLE
DC Characteristics
\ OUTPUTS
\ INPUTS
RECEIVER
ENABLE
DRIVER
ENABLE
4.75 V .:S Vee .:S 5.25 V for ooe .:S T A .:S 70 oe, and 4.5 V .:S Vee .:S 5.5 V
for -55 ° C .:S T A .:S + 125 ° C, unless otherwise noted
Symbol
Characteristic
Max
Unit
IIL(RE)
IIL(DE)
IIL(D)
IlL (B)
Input Current, LOW Logic State
Receiver Enable Input, VIL(RE) = 0.4 V
Driver Enable Input, VIL(DE) = 0.4 V
Driver Input, VIL(D) = 0.4 V
Bus Receiver Input, VIL(B) = 0.4 V
-200
-200
-200
-200
p.A
IIL(D)DIS
Input Disabled Current, LOW Logic State
Driver Input, VIL(D) = 0.4 V
-25
p.A
IIH(RE)
IIH(DE)
IIH(D)
IIH(B)
Input Current, HIGH Logic State
Receiver Enable Input, VIH(RE) = 5.25 V
Driver Enable Input, VIH(DE) = 5.25 V
Driver Input, VIH(D) = 5.25 V
Receiver Input, VIH(B) = 5.25 V (p.A8T26 only)
25
25
25
100
p.A
VIL(RE)
VIL(DE)
VIL(D)
VIL(B)
Input Voltage, LOW Logic State
Receiver Enable Input
Driver Enable Input
Driver Input
Receiver Input
0.85
0.85
0.85
0.85
V
VIH(RE)
VIH(DE)
VIH(D)
VIH(B)
Input Voltage, HIGH Logic State
Receiver Enable Input
Driver Enable Input
Driver Input
Receiver Input
VOL(B)
VOL(R)
Output Voltage, LOW Logic State
Bus Driver Output, IOL(B) = 48 rnA
Receiver Output, IOL(R) = 20 rnA
VOH(B)
VOH(R)
IOHL(B)
IOHL(R)
Min
Typ
2.0
2.0
2.0
2.0
V
0.5
0.5
Output Voltage, HIGH Logic State
Bus Driver Output, IOH(B) = -10 rnA
2.4
Receiver Output, IOH(R) = -2.0 rnA
2.4
Receiver Output, IOH(R) = -100 p.A, vee = 5.0 V 3.5
Output Disabled Leakage Current
HIGH Logic State
Bus Driver Output, VOH(B) = 2.4 V
Receiver Output, VOH(R) = 2.4 V
3.1
3.1
V
100
100
6·79
V
p.A
•
#LA8T26A • #LA8T28
DC Characteristics (Cont.)
4.75 V :5 Vcc :5 5.25 V for QOC :5 TA:5 70°C, and 4.5 V :5 VCC:5 5.5 V
for -55°C -< TA -< +125°C, unless otherwise noted
Max
Unit
10ll(B)
10ll(R)
Output Disabled Leakage Current
LOW Logic State
Bus Output, VOl(B)
0.5 V
Receiver Output, VOl(R)
0.5 V
-100
-100
p,A
VIC(DE)
VIC(RE)
VIC(D)
Input Clamp Voltage
Driver Enable Input IIC(DE)
-12 mA
Receiver Enable Input IIC(RE)
-12 mA
Driver Input IIC(D)
-12 mA
-1.0
-1.0
-1.0
V
10S(B)
10S(R)
Output Short·Circuit Current, VCC
Bus Driver Output
Receiver Output
80
50
-150
-75
mA
Icc
Power Supply Current
VCC 5.25 V
50
87
mA
Symbol
Characteristic
Min
=
Typ
=
=
=
=
= 5.25 V, Note
-50
-30
=
Note
Only one output may be short-circuited at a time
p,A8T26A AC Characteristics
Unless otherwise noted, specifications apply at TA
and VCC = 5.0 V.
= 25 ° C
Symbol
Characteristic
Figure
Typ
Max
Unit
tplH(R)
Propagation Delay Time from Receiver (Bus)
Input to HIGH Logic State Receiver Output
1
9
14
ns
tpHl(R)
Propagation Delay Time from Receiver (Bus)
Input to LOW Logic State Receiver Output
1
6
14
ns
tplH(D)
Propagation Delay Time from Driver Input to
HIGH Logic State Driver (Bus) Output
2
10
14
ns
tPHl(D)
Propagation Delay Time from Driver Input to
LOW Logic State Driver (Bus) Output
2
10
14
ns
tplZ(RE)
Propagation Delay Time from Receiver Enable
Input to HIGH Impedance (Open) Logic State
Receiver Output
3
10
15
ns
tpZl(RE)
Propagation Delay Time from Receiver Enable
Input to LOW Logic Level Receiver Output
3
15
20
ns
tplZ(DE)
Propagation Delay Time from Driver Enable Input
to HIGH Impedance Logic State Driver
(Bus) Output
4
15
20
ns
tpZl(DE)
Propagation Delay Time from Driver Enable
Input to LOW Logic State Driver (Bus) Output
4
19
25
ns
p,A8T28 AC Characteristics
Symbol
TA
= 25°C, VCC = 5.0 V unless otherwise specified.
Characteristic
tplH(R)
tpHl(R)
Propagation Delay Time-Receiver (Cl
tplH(D)
tpHl(D)
Propagation Delay Time-Driver (Cl
tpZl(RE)
Propagation Delay Time-Receiver Enable
(Cl 30 pF)
= 30 pF)
= 300 pF)
=
Figure
Typ
Max
Unit
5
-12
-9
17
17
ns
6
-13
-13
17
17
ns
-18
23
-13
18
-21
28
-18
23
7
tplZ(RE)
tpZl(DE)
Propagation Delay Time-Driver Enable
(Cl 300 pF)
=
8
tplZ(DE)
6·80
ns
ns
#LA8T26A • #LA8T28
Fig. 1 #A8T26A Test Circuit and Waveforms for
Propagation Delay Time from Bus
(Receiver) Input to Receiver Output,
tpLH(R) and tpHL(R)
TO SCOPE
(OUTPUT)
TO SCOPE
(INPUT)
Fig. 3
#A8T26A Test Circuit and Waveforms for
Propagation Delay Time from Receiver
Enable Input to Receiver Output,
tpLZ(RE) and tpZL(RE)
TO SCOPE
(INPUT)
26V
RECEIVER EN""""ABIE"
INPUT
TO SCOPE
(OUTPUT)
2.6 V
92 i!
5.0 V
2.4 k
240
n
1N916
OR EaUIV
It
51
n
PULSE
GENERATOR
13k
30 pF
tTLH
hLH '550 ns
<~
5.0 ns
26V-------i--~~~-------~~
OV--"';"...I\
oV~_"",,""'"
• 3.5 V
VOH - - - - - - , .
Val
-------'----~,N~P~U~T:-:P~U~L~SE~FR:-:E:-:QJUENCy ~ 5 0 MHz
---------------i----:;_---------'\
V O l - - - - - -......
10%
INPUT PULSE FREOUENCY -=- 5 0 MHz
DUTY CYCLE - 50%
DUTY CYCLE = 50%
Fig. 2
#A8T26A Test Circuit and Waveforms for
Propagation Delay Time from Driver
Input to Bus (Driver) Output, tpLH(D)
and tpHL(D)
TO SCOPE
(INPUT)
26 V
TO SCOPE
(OUTPUT)
Fig. 4
26V
TO SCOPE
(INPUT)
DRIVER
ENABLE
INPUT
#A8T26A Test Circuit and Waveforms for
Propagation Delay Time from Driver
Enable Input to Driver (Bus) Output,
tpLZ(DE) and tpZL(DE)
TO SCOPE
+2.6 V
(OUTPUT) 50 V
30 !l
DRIVER
DRIVER
INPUT
ENABLE
INPUT
DRIVER
51 fl
51 !l
300 pF
INPUT
RECEIVER
ENABLE
hLH :::; 5 0 ns
INPUT
tTLH
:s 5 0
ns
INPUT
oV _ _
';:';'~
INPUT
VOH----...;........
OV--="I
IpZLIDEI
·3.5 V----...;..-,.
Val
---------------~-----,-N:-:P-U~T~P~U:-:LS:-:E:-:F:-:R:-:E~QJU.ENCy"50MHZ
OUTPUT
DUTY CYCLE = 50%
-=__-=______
Val _____________ ' -_ _ _ _ _ _
;J" 10%
INPUT PULSE FREQUENCY
50 MHz
DUTY CYCLE
50%
6-81
•
p,A8T26A • p,A8T28
Fig. 5
~A8T28
Test Circuit and Waveforms for
Propagation Delay Time from Bus
(Receiver) Input to Receiver Output,
tpLH(R) and tpHL(R)
TO SCOPE
(INPUT)
TO SCOPE
(INPUT)
RECEIVER
Fig. 6
Test Circuit and Waveforms for
Propagation Delay Time from Driver
Input to Bus (Driver) Output, tpLH(D)
and tpHL(D)
26V
TO SCOPE
(INPUT)
26 V
ENABLE
INPUT
~A8T28
TO SCOPE
(OUTPUT)
DRIVER
ENABLE
INPUT
92 l!
2.6 V
30 n
1N916
OR eaulv
DRIVER
INPUT
RECEIVER
OUTPUT
13 k
51!!
30 pF
hHL < 5 0 ns
26 V
26V---:::::-li.
15 V
INPUT
INPUT
10%
ov----
oV---Vo~-----,
Vo~
---------,
OUTPUT
VOl---------,~----------------,
VOL
INPUT PULSE FREOUENCY -= 10 MHz
DUTY CYCLE = 50%
Fig. 7
---------,~-----------,
INPUT PULSE FREQUENCY
10 MHz
DUTY CYCLE
50%
~A8T28 Test Circuit and Waveforms for Propagation Delay Time from
Receiver Enable Input to Receiver Output, tpLZ(RE) and tpZL(RE)
TO SCOPE
(INPUT)
TO SCOPE
(OUTPUT)
RECEIVER
ENABLE
50V
PULSE
GENERATOR
51 !l
50 k
trLH
240 !!
24k
RECEIVER
OUTPUT
30 pF
1N916
OR eQUIV
s; 5.0 ns
2.6V
----t-:r.::::::-------~=~
INPUT
OV--=.II
'35V--------t-~~------------_.,.
50 MHz
OUTPUT
DUTY CYCLE
VOL _ _ _ _ _ _.;;;T1O%
6-82
50%
JLA8T26A • JLA8T28
Fig. 8
~A8T28 Test Circuit and Waveforms for Propagation Delay Time from
Driver Enable Input to Driver (Bus) Output, tpLZ(DE) and tpZL(DE)
TO SCOPE
(INPUT)
TO SCOPE
DRIVER
+26 V
50
(OUTPUT)
ENABLE
INPUT
v
24.
70
n
DRIVER
PULSE
(BUS)
OUTPUT
GENERATOR
RECEIVER
50.
ENABLE
300 pF
1N918
OR EQUIV
INPUT
ITLH~SOns
INPUT
oV---"'I
• 3.5 V ----...;..""""
INPUT PULSE FREQUENCV == 50 MHz
DUTY CYCLE = 50%
OUTPUT
VOL - - - - - - - ,,_ _ _ _ _ _ _ _ _.-J 10%
•
6-83
----------~
---
._-----
JLA9643
Dual TTL To
MOS/CCD Driver
I=AIRCHILD
A Schlumberger Company
Interface Products
Description
The ILA9643 is a Dual Positive-Logic "AND" TTL-toMOS Driver. The ILA9643 is a functional replacement
of the SN75322 with one important exception: the two
external pnp transistors are no longer needed for
operation. The ILA9643 is also a functional
replacement for the 75363 with the important
exception that the VCC3 supply is not needed. The pin
connections normally used for the external pnp
transistors are purposely not internally connected to
the ILA9643.
•
•
•
•
•
•
•
•
•
Connection Diagram
S-Pin DIP
tNA
Vee1
E
SATISFIES CCD MEMORY AND DELAY
LINE REQUIREMENTS
DUAL POSITIVE-LOGIC TTL-TO-MOS DRIVER
OPERATES FROM STANDARD BIPOLAR AND
MOS SUPPLY VOLTAGES
HIGH-SPEED SWITCHING
TTL AND DTL COMPATIBLE INPUTS
SEPARATE DRIVER ADDRESS INPUTS WITH
COMMON STROBE
VOH AND VOL COMPATIBLE WITH POPULAR
MOS RAMs
DOES NOT REQUIRE EXTERNAL pnp
TRANSISTORS OR VCC3
VOH MINIMUM IS VCC2 - 0_5 V
OUTA
tNS
Vee2
GND
OUTS
(Top View)
Order Information
Type
Package
ILA9643
Molded DIP
Absolute Maximum Ratings
Over operating ambient temperature range unless
otherwise noted
Supply Voltage Range of VCC1
(Note 1)
-0.5 V to 7 V
Supply Voltage Range of VCC2
-0.5 V to 15 V
Input Voltage
5.5 V
Inter-Input Voltage (Note 2)
5.5 V
Continuous Total Dissipation at
1000 mW
TA = 25°C
Operating Temperature Range
O°C to 70°C
Storage Temperature Range
-65°C to 150°C
Pin Temperature
Molded DIP (Soldering, 10 s)
Notes
1. Voltage values are wIth respect to network ground termonal
unless otherwise noted.
2. This rating applies between any two inputs of anyone of
the gates.
6·84
Code
9T
Part No_
ILA9643TC
JLA9643
Recommended Operating Conditions
Characteristic
Min Typ
4.75 5.0
Supply Voltage, VCC1
4.75
0
Supply Voltage, VCC2
Operating Temperature, TA
Electrical Characteristics
12
Max Unit
5.25 V
15
V
70
°C
Over recommended ranges of VCC1, VCC2 and operating ambient temperature unless
otherwise noted.
Symbol Characteristic
Condition
Min
Typ(3)
Max
Unit
0.8
V
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
liN
Input Current at Maximum VCC1 = 5.25 V, VCC2 = 11.4 V
Input Voltage
VIN = 5.25 V
IIH
Input HIGH Current
VIN = 2.4 V
IlL
Input LOW Current
VIN = 0.4 V
ICC1(L)
Supply Current from VCC1 VCC1 = 5.25 V
All Outputs LOW
VCC2 = 12.6 V
No Load
15
19
mA
ICC2(L)
Supply Current from VCC2
VCC2 = 12.6 V
All Outputs LOW
VCC1 = 5.25 V
5.5
9.5
mA
Supply Current from VCC1 VCC1 = 5.5 V
ICC1(H) All Outputs HIGH
VCC2 = 13.2 V
No Load
9.0
13
mA
Supply Current from VCC2
VCC2 = 12.6 V
ICC2(H) All Outputs HIGH
VCC1 = 5.25 V
5.5
9.5
mA
AC Characteristics
2.0
IOH = -400 /LA
V
VCC2- 0.5 VCC2 - 0.2
V
IOL = 10 mA
0.4
0.5
V
IOL = 1.0 mA
0.2
0.3
V
0.1
mA
A Inputs
40
E Inputs
80
A Inputs
0.5
E Inputs
- 1.0
/LA
mA
VCC1 = 5.0 V, VCC2 = 12 V, TA = 25°C
Symbol
Characteristic
tOLH
tOHL
Delay Time
tTLH
Rise Time
tTHL
Fall Time
tTLH
Rise Time
tTHL
Fall Time
tPLHAtpLHS
tpHLAtpHLS
Skew between outputs
Aand B
Condition
CL = 300 pF
Delay Time
RSERIES = 0
CL = 300 pF
RSERIES = 10 n
=
Typ
Max
Unit
5.0
9.0
17
ns
5.0
9.0
17
ns
6.0
17
6.0
8.0
11
11
17
ns
ns
14
20
ns
8.0
14
20
ns
0.5
Note
3. All tYPIcal values are at VCCI
5.0 V, VCC2
T A = 25· C unless otherwise noted.
Min
= 12 V, and
6-85
ns
•
JLA9643
AC Test Circuit and Waveforms
YCCl = 5Y
YCC2 = 12V
Y,N
)--\M--1I--- Your
2.4V
-::'
<10ns-\
I
Y'N
-I
l-
I
I
1-<10ns
I
"...---
~~---0.5~s---7.j
10%
l=
I ---.I
tDHL-I . -IYour
I--trHL
I
i
tpHL
l-tTLH
I:~ I
v
0.
-I'''------+--tlpLL~_=r - - - - VOL
The pulse generator has the following characteristics:
PRR = 1 MHz, ZOUT - 50 n
CL includes probe and jig capacitance.
6·86
J,lA9645 I 3245
F=AIRCHIL.O
Quad TTL-to-MOS/CCD
Driver
A Schlumberger Company
Interface Products
Description
The ~A9645/3245 is a High-Speed Driver intended to
be used as a clock (high-level) driver for 18 or 22-pin
dynamic NMOS RAMs. It also satisfies the nonoverlapping 2-phase clock drive requirements for CCD
memories like the F464 (64K) RAM.
Connection Diagram
l6-Pin DIP
The device features two common enable inputs, a
refresh select input and a clock control input. Internal
gating structure is organized so that all four drivers
may be deactivated for standby operation, or single
driver may be activated for read /write operation or all
four drivers may be activated for refresh operation.
INA
IN
C
E,
R
E2
INS
IN
(Top View)
Order Information
Type
Package
~A9645
Ceramic DIP
~A9645
Molded DIP
Logic Diagram
OUTB
S --+--OIr--~_4_+_+--1
OUTC
C --+--OIr--~_+_+_+-I
IN
i5
Part No_
~A9645PC/3245
~A9645DC / 3245
Inputs
I Address
Control
OUTA
INA -----0\
IN
Code
78
98
Truth Table
E1-------------.--~
IN
C
NC
GNO
INTERCHANGEABLE WITH INTEL 3245
FOUR HIGH-SPEED, HIGH-CURRENT DRIVERS
CONTROL LOGIC OPTIMIZED FOR MOS RAMs
SATISFIES CCD MEMORY AND DELAY LINE
DRIVE REQUIREMENTS
TTL AND DTL COMPATIBLE INPUTS
HIGH-VOLTAGE SCHOTTKY TECHNOLOGY
E2-----------._4--~._~
i5
OUTC
OUTB
The ~A9645/3245 is a pin-for-pin replacement of the
Intel 3245 Quad TTL-to-MOS Driver, with substantially
reduced dc power dissipation.
•
•
OUTO
OUT A
The circuit is designed to operate on nominal +5 V
and + 12 V power supplies and contains input and
output clamp diodes to minimize line reflections.
•
•
•
•
Vee
Voo
C
E2
E1
INPUT
REFRESH
H
X
X
X
X
H
X
X
X
X
H
X
X
X
X
X
X
L
L
L
L
H
L
H
L
L
X
L
H = HIGH
L = LOW
X = Don" Care
OUTO
-+--<:Jl
R --+--o,jL~
c-------..J
6-87
X
X
Output
L
L
L
L
H
H
•
•
jlA9645/3245
Absolute Maximum Ratings
Temperature Under Bias
Storage Temperature
Supply Voltage, Vee
Supply Voltage, Voo
All Input Voltages
DC Characteristics
TA
-1Q°C
-65°C
-0.5 V
-0.5 V
-1.0 V
to
to
to
to
to
= O°C to 70°C,
+70°C
+150°C
+7.0 V
+14.0 V
Voo
Vee
= 5.0 V
Symbol
Characteristic
Condition
IFD
Inp'!!. !:.o~
...'"0
0
TYPICAL
(SINGLE DEVICE) -
200
,,
I
'
I '
I,
"
05
'"
~
/
~ f-'
~
o
300
a
o
I
100
I
I
,II
V
ILA9667 Input Current vs
Input Voltage
0
V
/
5
0
5
,,
MAX
/ '
V,
/,
,
L"
"
V
V
V
26
•
11
12
400 '-"""TTT"'-"'T'""'T""""'T'"-r---r--..,
"EI
:e'"
g:
300
~
i;l
300
a
u
::j
0
~
~
0
~
200
~
m
200
~
~
m
~
~
g
80
100
J
' 'JCIW
"
Peak Collector Current vs
Duty Cycle and Number of
Outputs (Ceramic Package)
::>
,
~
5 r-KOVAR lEj FRAME
VIN-INPUT VOLTAGE-V
ili
'\
100
0
DUTY CYCLE - %
6-93
,
I .........
, "
10
DUTY CYCLE - %
24
~EVICELIMIT
o~
","
TVP
0
60
22
60'C/W
V ,
40
20
~ COPPER LEAD FRAME
400
100
20
18
5
V
./
E
~
16
"
f-'
Allowable Average
Package Power Dissipation vs
Ambient Temperature
,
...I
~
14
TVP'
Peak Collector Current vs
Duty Cycle and Number of
Outputs (Molded Package)
...'"0
12
0
liN -INPUT VOlTAGE- rnA
0
o
"
YIN -INPUT VOLTAGE - V
20
0
C
600
ILA9668 Input Current vs
Input Voltage
,,
MAX/
400
,,
/,
5
TVP
,,
V
liN -INPUT CURRENT -I1-A
VCElsat)-SATURATION VOLTAGE-V
5
V
/
V
200
15
10
MAX
0
V
I
I
~
/LIMIT
I
I
,,
.L
5
V
I
0
20
L
MAxi
TYPICAL,
::>
I
400
~
0
...I
ili
g:
I
ili
0
~
I
1-..1
20
V
I
50
,
,,
,,
100
AMBIENT TEMPERATURE - ' C
,
,
,
','
150
J.LA9665/6/7/8
Test Circuits
Figure 4
Figure 1a
OPEN +SOV
OPEN -SOY
OPEN
I.,.
Figure 1b
Figure 5
OPEN
OPEN -SO V
I
Figure 2
Figure 6
OPEN
+SOV
OPEN
Figure 3
Figure 7
OPEN
t~>O--- OPEN
6·94
--[>C>-1r-DI--l
J[A9665/6/7/8
Typical Applications
Buffer for Higher Current Loads
PMOS to Load
+vss
+v
~vcc
16
16
15
2
l
3
14
4
13
5
2
15
3
14
4
9666
13
12
9667
12
6
11
7
10
PMOS
OUTPUT
8
9
9
TTL
OUTPUT
-=
TTL to Load
-v
•
16
15
3
14
4
5
6
13
9668
12
11
200l!
10
8
6-95
jlA75450/S0/70
FAIRCHILD
Series Dual
Peripheral Drivers
A Schlumberger Company
Interface Products
Description
The ~A75400 series of devices are Dual
High-Speed General-Purpose Interface Drivers that
convert TTL and DTL logic levels to high-current drive
capability. The ~A75450B features two TTL NAND
gates and two uncommitted transistors. The
~A75451A, ~A75452A, and ~A75453A feature two
standard series 74 TTL gates in AND, NAND, OR and
NOR configurations respectively, driving the base of
two high voltage, high current, uncommitted collector
output transistors.
•
•
•
•
•
NO LATCH-UP UP TO 55 V
HIGH OUTPUT CURRENT CAPABILITY
TTL OR DTL INPUT COMPATIBILITY
INPUT CLAMP DIODES
+5 V SUPPLY VOLTAGE
The ~A75400 series offers flexibility in designing highspeed logic buffers, power drivers, lamp drivers, line
drivers, MOS drivers, clock drivers and
memory drivers.
Absolute Maximum Ratings
~A75451A/B
~A75452A/B
~A75453A/B
I-IA75450B
Supply Voltage, Vee, Note 1
7V
7V
Input Voltage, Note 1
5.5 V
5.5 V
Inter-emitter Voltage, Note 2
5.5 V
5.5 V
Vee to Substrate Voltage, Note 6
35 V
Collector to Substrate Voltage, Note 6
35 V
Collector to Base Voltage
35 V
Collector to Emitter Voltage, Note 3
30 V
Emitter to Base Voltage
5V
Output Voltage Notes 1 and 4
Continuous Collector Current, Note 5
~A75461
~A75462
I-IA75471
I-IA75472
Table 2
300 mA
Continuous Output Current, Note 5
300 mA
Continuous Total Power Dissipation, Note 7
800mW
800mW
Operating Ambient Temperature Range
O°C to 70°C
O°C to 70°C
Storage Temperature Range
-65°C to +150°C
-65°C to +150°C
Pin Temperature
Molded DIP (Soldering, 10 s)
Ceramic DIP (Soldering, 60 s)
260°C
300°C
260°C
300°C
Notes on follOWing page
6-96
~A75450/60/70
Test Table 1
Series
Operating Temperature Range and
Supply Voltage Range
/LA75000 Series
Temperature, TA
O°C to 70°C
Supply Voltage, Vee
+4.75 V to +5.25 V
Test Table 2
/LA7545XA
/LA7545XB
/LA75461
/LA75462
Maximum Output, VOH
30 V
35 V
80 V
Maximum, Latch-up, Vs
20 V
30V
55 V
/LA75471
/LA75472
~A75450B
Dual Positive AND Peripheral Drivers
Connection Diagram
14-Pin DIP
Equivalent Circuit
Vee
Vee
GATE
4k
INA
Uk
130
IN B
OUT B
OUT A
1B
IE
2B
lC
2C
1E
2E
GND
INA
lC
1k
SUB
SUB
G
(Top View)
4 k
1.6 k
130
Logic Function
Positive Logic Z = XV (gate only)
Z = XV (gate and transistor)
2C
Order Information
Type
Package
/LA75450B
Molded DIP
Code
9A
OUT
B
Part No.
/LA75450BPC
IN B I - f - - t - - i
2E
~-+-~--~-~~--------GND
All resistor values In ohms
Notes
1 Voltage values are with respect to network ground terminal
unless otherwise specified
2 This IS the voltage between two emillers of a multiple-em Iller
Input transistor
3 This value applies when the base-em Iller resistance (RBE)IS
equal to or less than 500 II
4 This IS the maximum voltage which should be applied to any
output when It IS In the off state
5 Both halves of these dual CirCUitS may conduct rated
current Simultaneously
6 For the I'A75450 only, the substrate (Pin 8), must always be at
the most negative deVice voltage for proper operation
7 Above 60 0 e ambient temperature, derate linearly at
8 3 mW / ° C for Ceramic DIP and Molded DIP For the Molded
Mini DIP and Ceramic Mini DIP, derate at 6 7 mW / °C
above 30°C
6-97
•
j.£A75450/60/70 Series
/-tA75450B
Electrical Characteristics
Guaranteed over operating temperature range and supply voltage range, use test
table 1, unless otherwise indicated
TTL Gates
Symbol Characteristic
Test
Figure Condition
Min
2
VIH
Input HIGH Voltage
1
Vil
Input LOW Voltage
2
VCD
Input Clamp Diode Voltage
3
VOH
Output HIGH Voltage
2
Val
Output LOW Voltage
1
II
Input Current
at Maximum
Input Voltage
4
VCC
= Max, VIN = 5.5 V
IIH
Input HIGH Current
4
VCC
= Max, VIN = 2.4 V
III
Input LOW Current
3
VCC
= Max, VIN = 0.4 V
lOS
Short-Circuit Output Current,
Note 2
5
VCC
ICCH
Supply Current, Output HIGH
ICCl
Supply Current, Output LOW
= Max
= Max, VIN = 0 V
= Max, VIN = 5 V
/-tA75450B
Electrical Characteristics
= Min, liN = -12 mA
VCC = Min, Vil = 0.8 V
10H = -400/-tA
VCC = Min, VIN = 2 V
10l = 16 mA
Input A
Input G
Input A
Input G
VCC
6
VCC
2.4
Unit
V
0.8
-1.5
VCC
Input A
Input G
Typ(1) Max
3.3
0.22
V
V
V
0.4
V
1
mA
2
40
80
-1.6
-3.2
-18
-55
2
4
6
11
/-t A
mA
mA
mA
Guaranteed over operating temperature range and supply voltage range, use test
table 1, unless otherwise indicated
Output Transistors
Min
Symbol
Characteristic
Condition
V(SR)CSO
Collector to Base
Breakdown Voltage
Ic
= 100 /-tA,
IE
V(SR)CER
Collector to Base
Breakdown Voltage
Ic
= 100 /-tA,
RSE
V(SR)ESO
Emitter to Base
Breakdown Voltage
IE
hFE
Static Forward Current
Transfer Ratio, Note 3
VSE(sat)
Base to Emitter Voltage,
Note 3
VCE(sat)
Collector to Emitter Saturation
Voltage, Note 3
=0
= 500 Q
= 100 /-tA, Ic = 0
VCE = 3 V, Ic = 100 mA, TA = 25°C
VCE = 3 V, IC = 300 mA, TA = 25°C
VCE = 3 V, Ic = 100 mA
VCE = 3 V, Ic = 300 mA
Is = 10 mA, Ic = 100 mA
IS = 30 mA, IC = 300 mA
Is = 10 mA, IC = 100 mA
IS = 30 mA, Ic = 300 mA
Notes
1 All tYPIcal values are at Vec = 5 V. TA = 25°C
2 Not more than one output should be shorted at a tIme
3 These parameters must be measured uSIng the pulse
techniques tw = 300 liS. duty cycle:::; 2%
Typ (1) Max
Unit
35
V
30
V
5
V
25
30
20
25
0.85
1.0
V
1.05
1.2
V
0.25
0.4
V
0.5
0.7
V
4 Voltage and current values shown are nommal, exact values
vary slightly WIth transIstor parameter
6·98
/-LA75450/60170 Series
I'A75450B
AC Characteristics
Vee = 5 V, TA = 25°C
TTL Gates
Symbol Characteristic
TpLH
tpHL
Propagation Delay Time,
LOW to HIGH
Propagation Delay Time,
HIGH to LOW
I'A75450B
Test
Figure Condition
12
Min
CL = 15 pF, RL = 400
Typ
Max
Unit
12
22
ns
8
15
ns
n
Output Transistors
Symbol Characteristic
td
Delay Time
tr
Rise Time
ts
Storage Time
tf
Fall Time
Test
Figure Condition (Note 3)
13
Min
Ie = 200 mA, VBE(oft) = -1 V
IB( 1) = 20 mA, IB(2) = -40 mA
CL = 15 pF, RL = 50 n
Typ
Max
Unit
8
12
15
ns
20
ns
7
15
ns
6
15
ns
Unit
Gates and Transistors Combined
Symbol Characteristic
tpLH
Propagation Delay Time, LOW to HIGH
tpHL
Propagation Delay Time, HIGH to LOW
tTLH
Transition Time, LOW to HIGH
tTHL
Transition Time, HIGH to LOW
VOH
HIGH Level Output Voltage After Switching
Test
Figure Condition
Min
Ie = 200 mA,
CL=15pF,
RL = 50 n
14
Vs = 20 V,
Ie = 300 mA
RBE = 500 n
15
Vs - 6.5
Typ
Max
20
30
ns
20
30
ns
7
12
ns
9
15
ns
mV
Notes
1. All tYPical values are at Vee = 5 V, T A = 25°e
2 Not more than one output should be shorted at a time
3 These parameters must be measured uSing the pulse
techniques tw = 300 I1S, duty cycle ~ 2%
4
Voltage and current values shown are nommal, exact values
vary slightly with transistor parameter
6-99
•
J.LA75450/60/70 Series
J.LA75451A/B • J.LA75461 • J.LA75471
Dual Positive AND Peripheral Drivers
Truth Table
Connection Diagram
8-Pin DIP
Inputs
8
IN A1
Vee
IN A2
IN B2
OUT A
IN B1
GND
H
Output
x
y
L
L
H
H
L
H
L
H
= HIGH Level, L = LOW
z
L
L
L
H
Level
OUT B
(Top View)
Order Information
Type
Package
IlA75451A
Molded DIP
IlA75451A
Ceramic DIP
IlA 75451 B
Molded DIP
IlA75451 B
Ceramic DIP
IlA75461
Molded DIP
IlA75471
Molded DIP
Code
9T
6T
9T
6T
9T
9T
Part No.
IlA75451ATC
IlA75451ARC
IlA75451BTC
IlA75451BRC
IlA75461TC
IlA75471TC
Equivalent Circuit (Each Driver)
.----_-_~----Vcc
1.Sk
4k
130
OUTPUT
INPUTS!
1_-+-_....
2
1k
500
~-+---~~--+-+--~--GND
Component values shown are nominal All resistor values
In
ohms
6·100
(on state)
(on state)
(on state)
(off state)
f.lA75450/60170 Series
IlA75451A/B
Electrical Characteristics
Guaranteed over operating temperature range and supply voltage range, use test
table 1.
IlA75451A
Symbol Characteristic
Test
Figure Condition (Note 1) Min
VIH
Input HIGH Voltage
7
VIL
Input LOW Voltage
7
VCD
Input Clamp
Diode Voltage
10H
Output HIGH Current 7
8
Output LOW Voltage 7
liN
= -12
Input Current at
Maximum Input
Min
Typ
Max
2.0
= Min,
VCC
mA
VCC = Min,
VIH = 2 V, Note 2
0.25
Unit
V
0.8
0.8
V
-1.5
-1.5
V
100
100
IlA
0.4
0.25
0.4
10L = 100 mA
V
VCC = Min
VIL = 0.8 V,
10L
II
Max
2.0
VCC = Min,
VIL = 0.8 V,
VOL
Typ
IlA75451B
0.5
0.7
0.5
= 300 mA
0.7
9
Vcc = Max,
VIN = 5.5 V
1.0
1.0
mA
40
40
IlA
Voltage
IIH
Input HIGH Current
9
Vcc = Max,
VIN = 2.4 V
IlL
Input LOW Current
8
Vcc = Max,
VIN = 0.4 V
-1.0
-1.6
-1.0
-1.6
mA
ICCH
Supply Current,
Output High
VCC = Max,
VIN = 5 V
7.0
11
7.0
11
mA
Vcc = Max,
VIN = 0 V
52
65
52
65
mA
Typ
Max
Unit
ICCL
Supply Current
Output LOW
IlA75451A/B
AC Characteristics
10
Vcc = 5 V, T A = 25 C
0
IlA75451A
Symbol Characteristic
tpLH
Propagation Delay
Time, LOW to HIGH
tpHL
Propagation Delay
Time, HIGH to LOW
tTLH
Transition Time,
LOW to HIGH
tTHL
Transition Time,
HIGH to LOW
VOH
Voltage After
Test
Figure Condition
14
HIGH Level Output
Switching
15
Min
10 = 200 mA,
CL = 15 pF,
RL = 50 Q
10 = 300 mA,
Note 3
Vs - 6.5
Notes
1. All tYPical values are at Vee = 5 V, TA = 25"e
2 VOH = 30 V for I'A75451A and B, 35 V for I'A75461, 80 V
for I'A75471
3
6·101
IlA75451B
Typ
Max
Min
20
55
18
25
ns
20
40
18
25
ns
8
20
5
8
ns
12
20
7
12
ns
Vs - 6.5
mV
Vs = 20 V for I'A75451A and B, 30 V for I'A75461, 55 V for
I'A75471
•
j.LA75450/60/70 Series
J.lA75461/J.lA75471
Electrical Characteristics
Guaranteed over operating temperature range and supply voltage range, use test
table 1, page 1.
J.lA75461
Test
Figure Condition (Note 1) Min
Symbol Characteristic
VIH
Input HIGH Voltage
7
VIL
Input LOW Voltage
7
VCD
Input Clamp
Didde Voltage
8
10H
Output HIGH Current 7
VOL
Output LOW Voltage 7
J.lA75471
Typ
Max
Min
Typ
Max
Unit
0.8
V
-1.5
V
100
J.lA
V
2.0
2.0
0.8
VCC = Min,
liN = -12 mA
-1.2
Vcc = Min,
VIH = 2 V, Note 2
-1.5
-1.2
100
VCC = Min,
VIL = 0.8 V,
10L = 100 mA
.16
VCC = Min,
VIL = 0.8 V
10L = 300 mA
.35
0.4
0.16
0.4
V
0.7
0.35
0.7
II
Input Current at
Maximum Input
Voltage
9
Vcc = Max,
VI = 5.5 V
1.0
1.0
mA
IIH
Input HIGH Current
9
Vcc = Max,
VI = 2.4 V
40
40
J.lA
IlL
Input LOW Current
8
Vcc = Max,
VI = 0.4 V
-1.0
-1.6
-1.0
-1.6
mA
ICCH
Supply Current,
Output High
VCC = Max,
VI = 5 V
8.0
11
8.0
11
mA
VCC = Max,
VIH = 0 V
61
76
61
76
mA
Typ
Max
Unit
ICCL
10
Supply Current
Output LOW
J.lA75461/J.lA75471
AC Characteristics
Vcc
= 5 V, TA = 25
0
C
J.lA75471
J.lA75461
Symbol Characteristic
tPLH
Propagation Delay
Time, LOW to HIGH
tpHL
Propagation Delay
Time, HIGH to LOW
tTLH
Transition Time,
LOW to HIGH
tTHL
Transition Time,
HIGH to LOW
VOH
HIGH Level Output
Voltage After
Switching
Test
Figure Condition
14
15
Min
10 = 200 mA,
CL = 15 pF,
RL = 50 Q
10 = 300 mA,
Note 3
Typ
Max
35
55
35
55
ns
25
40
25
40
ns
8
20
8.0
20
ns
10
20
10
20
ns
Vs - 10
Min
mV
Vs - 18
Noles
1 All typical values are at Vee = 5 V, TA = 25°e
2 VOH = 30 V for ~A75451A and S, 35 V for ~A75461, 80 V
3
Vs = 20 V for
~A75471
for~A75471
6·102
~A75451A
and S, 30 V for
~A75461,
55 V for
~A75450/60/70
~A75452A/B
Series
• ~A75472
Dual Positive NAND Peripheral Driver
•
~A75462
Connection Diagram
a-Pin DIP
Truth Table
Inputs
8
Output
2
IN Al
Vee
IN A2
IN B2
L
L
H
H
L
OUT A
IN Bl
H
H
GND
L
H
H
H
L
(off
(off
(off
(on
state)
state)
state)
state)
H = HIGH Level, L = LOW Level
OUT B
(Top View)
Order Information
Type
Package
!1A75452A
Molded DIP
!1A75452A
Ceramic DIP
Molded DIP
!1A754528
!1A754528
Ceramic DIP
!1A 75461
Ceramic DIP
!1A75471
Ceramic DIP
Code
9T
6T
9T
6T
6T
6T
Part No.
!1A75452ATC
!1A75452ARC
!1A754528TC
!1A754528RC
!1A7 5461TC
!1A75471TC
Equivalent Circuit (Each Driver)
...---_----_-_----Vee
1.6 k
4 k
1.6 k
130
OUTPUT
INPUTSl
-2-;-.......
~-+---~~--4--+--~~-~-GND
Component values shown are nominal All resistor values
In
ohms
6-103
•
j1A75450/60170 Series
IlA75452A/B
Electrical Characteristics
Guaranteed over operating temperature range and supply voltage range, use test
table 1, page 1, unless otherwise indicated.
IlA75452A
Symbol Characteristic
Test
Figure Condition (Note 1) Min
VIH
Input HIGH Voltage
7
VIL
Input LOW Voltage
7
VCD
Input Clamp
Diode Voltage
10H
Output HIGH Current 7
VOL
8
Output LOW Voltage 7
Typ
IlA75452B
Max
Min
Typ
Max
2
2
Unit
V
0.8
0.8
V
VCC = Min,
liN = -12 mA
-1.5
-1.5
V
Vcc = Min
VIL = 0.8 V, Note 2
100
100
IlA
Vcc = Min,
VIH = 2 V
10L = 100 mA
0.25
Vcc = Min,
VIH = 2 V
10L = 300 mA
0.5
0.4
0.25
0.4
V
0.7
0.5
0.7
II
Input Current at
Maximum Input
Voltage
9
VCC = Max,
VIN = 5.5 V
1.0
1.0
mA
IIH
Input HIGH Current
9
Vcc = Max,
VIN = 2.4 V
40
40
IlA
IlL
Input LOW Current
8
VCC = Max,
VIN = 0.4 V
-1.0
-1.6
-1.0
-1.6
mA
ICCH
Supply Current,
Output HIGH
VCC = Max,
VIN = a V
11
14
11
14
mA
VCC = Max,
VIN = 5 V
56
71
56
71
mA
Typ
Max
Unit
ICCL
Supply Current
Output LOW
10
IlA75452AIIlA75452B
AC Characteristics Vcc = 5 V, T A = 25 0 C
IlA75452A
Symbol Characteristic
tpLH
Propagation Delay
Time. LOW to HIGH
tpHL
Propagation Delay
Time, HIGH to LOW
tTLH
Transition Time,
LOW to HIGH
tTHL
Transition Time,
HIGH to LOW
VOH
HIGH Level Output
Voltage After
Switching
Test
Figure Condition
14
15
Min
10 = 200 mA,
CL = 15 pF,
RL = 50 Q
10 = 300 mA,
Note 3
IlA55175452B
Typ
Max
25
65
25
35
ns
25
50
22
35
ns
8
25
5
8
ns
12
20
7
12
ns
Vs - 6.5
Min
Vs - 6.5
mV
Notes
1 All typical values are at Vec ; 5 V. T A; 25°C
2 VOH; 30 V for I'A75452A and S, 35 V for I'A75462, 80 V
3
VS; 20 V for I'A75452A and S, 30 V for I'A75462, 55 V
for I'A75472.
for I'A75472
6·104
~A75450/60/70
/-LA754621/-LA75472
Electrical Characteristics
Guaranteed over operating temperature range and supply voltage range, use test
table 1, page 1, unless otherwise indicated.
/-LA75462
Test
Figure Condition (Note 1) Min
Symbol Characteristic
VIH
Input HIGH Voltage
7
VIL
Input LOW Voltage
7
VCO
Input Clamp
Diode Voltage
10H
Output HIGH Current 7
VOL
Series
/-LA75472
Typ
Max
2
Min
Typ
2.0
VCC = Min,
liN = -12 rnA
-1.2
VCC = Min
VIL = 0.8 V, Note 2
Output LOW Voltage 7
-1.5
-1.2
100
VCC = Min
VIH = 2 V
10L = 100 rnA
0.16
VCC = Min,
VIH = 2 V
10L = 300 rnA
0.35
0.4
Unit
V
0.8
8
Max
0.16
0.8
V
-1.5
V
100
/-LA
0.4
V
0.7
0.35
0.7
II
Input Current at
Maximum Input
Voltage
9
VCC = Max,
VIN = 5.5 V
1.0
1.0
rnA
IIH
Input HIGH Current
9
VCC = Max,
VIN = 2.4 V
40
40
/-LA
IlL
Input LOW Current
8
VCC = Max,
VIN = 0.4 V
-1.0
-1.6
-1.0
-1.6
rnA
ICCH
Supply Current,
Output HIGH
VCC = Max,
VIN = 0 V
13
17
13
17
rnA
VCC = Max,
VIN = 5 V
65
76
65
76
rnA
Typ
Max
Unit
ICCL
10
Supply Current
Output LOW
/-LA754621/-LA75472
AC Characteristics
Vcc
= 5 V,
TA
= 25°C
/-LA75462
Test
Figure Condition
Symbol Characteristic
tpLH
Propagation Delay
Time, LOW to HIGH
tPHL
Propagation Delay
Time, HIGH to LOW
tTLH
Transition Time,
LOW to HIGH
tTHL
Transition Time,
HIGH to LOW
VOH
HIGH Level Output
Voltage After
Switching
Min
=
10
200 rnA,
CL = 15 pF,
RL = 50 n
14
=
10
300 rnA,
Note 3
15
Vs - 10
/-LA75472
Typ
Max
50
65
45
65
ns
40
50
30
50
ns
12
25
13
25
ns
15
20
10
20
ns
Min
Vs - 18
Notes
=
=
3
1 All tYPIcal values are at Vee
5 V, TA
25°e.
2 vOH = 30 V for I'A75452A and B, 35 V for I'A75462,
80 V for I'A75472.
6·105
Vs = 30 V for I'A75462 and 55 V for I'A75472
mV
•
~A75450/60/70
Series
~A75453A/B
Dual Positive OR Peripheral Drivers
Connection Diagram
a-Pin DIP
Truth Table
Inputs
8
IN Al
Vee
IN A2
IN 82
OUT A
IN 81
GND
H
OUT 8
~
Output
1
2
L
L
H
H
L
H
L
H
HIGH Level, L
~
LOW Level
(Top View)
Order Information
Type
Package
IlA75453A
Ceramic DIP
IlA75453A
Molded DIP
IlA75453B
Ceramic DIP
IlA75453B
Molded DIP
Code
6T
9T
6T
9T
Part No.
IlA75453ARC
IlA75453ATC
IlA75453BRC
IlA75453BTC
Equivalent Circuit (Each Driver)
r----_...----~---t_----vee
.::.:-;r-----;~-_t-------'
'"'""\.
~--+---~-------~---;~-~'GND
Component values shown are nominal All resistor values
In
ohms
6-106
L
H
H
H
(on
(off
(off
(off
state)
state)
state)
state)
,uA75450/60/70 Series
JiA75453A/B
Electrical Characteristics
Guaranteed over operating temperature range and supply voltage range, use test
table 1, page 1, unless otherwise indicated.
Test
Figure Condition
Symbol Characteristic
Min
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
VeD
Input Clamp
Diode Voltage
8
Vee = Min,
liN = -12 rnA
10H
Output HIGH Current
7
Vee = Min, VOH
VIH = 2 V
VOL
Output LOW Voltage
7
2
7
7
II
Input Current at Maximum
Input Voltage
IIH
V
100
JiA
= 30 V
0.4
Vee = Min, VIL
10L = 300 rnA
= 0.8 V
0.5
0.7
9
Vee
IlL
Input LOW Current
8
Vee
leeH
Supply Current, Output HIGH
ICCL
Supply Current, Output LOW
Vcc
-1.5
0.25
Input HIGH Current
JiA75453A/B
AC Characteristics
V
= 0.8 V
Vee
Vee
Vce
Unit
V
0.8
Vee = Min, VIL
10L = 100 rnA
9
11
Typ
(Note) Max
V
= Max, VIN = 5.5 V
= Max, VIN = 2.4 V
= Max, VIN = 0.4 V
= Max, VIN = 5 V
= Max, VIN = 5 V
1.0
rnA
40
-1.6
JiA
rnA
8.0
11
rnA
54
68
rnA
Typ
Max
Unit
-1.0
= 5 V, TA = 25°C
JiA75453B
JiA75453A
Symbol Characteristic
tpLH
Propagation Delay
Time, LOW to HIGH
tPHL
Propagation Delay
Time, HIGH to LOW
tTLH
Transition Time,
LOW to HIGH
tTHL
Transition Time,
HIGH to LOW
VOH
HIGH Level Output
Voltage After
Switching
Test
Figure Condition
14
15
10
CL
RL
Vs
10
Min
= 200 rnA,
= 15 pF,
= 50 n
= 20 V,
= 300 rnA
Typ
Max
20
55
18
25
ns
20
40
16
25
ns
8
25
5
8
ns
12
25
7
12
ns
Vs - 6.5
Notes
1 All tYPical values are at Vee = 5 V. TA = 25°e
2 VOH = 30 V for IlA75453A and 8
3
Min
Vs - 6.5
Vs = 20 V for "A75452A and 8
6·107
---_.-
~
..
--
mV
•
,uA75450/60/70 Series
Characteristics Measurement Information
Fig.4
DC Test Circuit (Note)
Fig. 1
II. IIH
Vee
VIH, VOL
Vcc
VI-----r,
t
IOL
VIH
-=--..,
SUB
-"""f-.,-)c>--.....
I
OPEN
GND
Eaeh Input IS tested separately
1
Fig.5
lOS
Vee
Both Inputs are tested simultaneously
Fig. 2
VIL, VOH
Vce
SUB
i
GND
~IOS
IOH
VIL-----i
Eaeh gate IS tested separately
VOH
Fig. 6
11
-=
ICCH, ICCl
V I - -....- - i
SUB
Eaeh Input IS tested separately
Fig.3
OPEN
GND
Veo, IlL
4.5 V
Vee
Both gates are tested simultaneously
OPEN
Vee
~
A
CIRCUIT y
UNDER
VIH
VIL
B
TEST
~OL
t
Notes
1 Eaeh Input IS tested separately.
2
VOH
SEE
TEST
TABLE
VOL
1I
When testing V CD. Input not under test IS open
-=
Note
Arrows indicate actual direction of current flow Current Into a
terminal IS a posllive value
Note
Eaeh Input IS tested separately.
6-108
-=
/-LA75450/60/70 Series
Characteristics Measurement Information (Cont.)
Fig. 10
ICCH, ICCL for AND,
NAND Circuits
Test Table 2
Vee
Input
Under
Test
Other
Input
Apply
Measure
/LA754X1
VIH
VIL
VIH
Vee
VOH
IOL
IOH
VOL
/LA754X2
VIH
VIL
VIH
Vee
IOL
VOH
VOL
IOH
/LA754X3
VIH
VIL
GND
VOH
IOL
IOH
VOL
Circuit
Fig. 8
lceH ~
Output
VIL
OPEN
~leeL
1
I
I
I
V,--.--t---t
IL _ _ _
VCO, IlL
Vee
4.5
Both gates are tested simultaneously
v--~---.
Fig. 11
CIRCUIT Y
OPEN
UNDER
B,A TEST
ICCH, ICCL for OR, NOR Circuits
Vee
IceH+
~eCL
OPEN
r
V,----t--t
I
L ___
Notes
1 Each Input IS tested separately
2 When testing IlL IlA75400, the Input not under test
IS grounded For all other CirCUitS It IS at 4 5 V
3 When testing VCD, Input not under test IS open
Fig.9
Both gates are tested simultaneously
II,IIH
Vee
III hH
V,
-A,B
CIRCUIT y
UNDER
B,A TEST
OPEN
Each Input IS tested separately.
6-109
I
I
I
J
•
J,tA75450/60170 Series
Characteristics Measurement Information
Switching Characteristics
Fig. 12
Propagation Delay Times, Each Gate
(ILA55450, ILA75450 Only)
Test Circuit
INPUT
Vee
OUTPUT
5V
2.4 V
PULSE
GENERATOR~~__- {__~
(See Nole 1)
Voltage Waveforms
~~T. "" J r-_9 0'~_'1_0_n._:~
=1 __
IPLH
Jr
1/
-
OUTPUT _ _ _ _
Notes
1 The pulse generator has the fOllowing characteristics
PRR = 1 MHz, ZOUT = 50 II
2 CL Includes probe and Jig capacitance
3 All diodes are FD777
6-110
i-IPHL
~,,"v
___:::
~A75450/60/70
Series
Characteristics Measurement Information
Switching Characteristics (Cant.)
Fig. 13
Switching Times, Each Transistor
(,uA75450 Only)
Test Circuit
10 V
-1 V
INPUT
1 kll
RL
= 50
II
.----.----.--OUTPUT
O.lI'F
CL = 15 pF
(See Note 2)
62 II
Voltage Waveforms
------r.90~~~oW--r---------------3V
INPUT----~r-
:55 ns
j
1.5V
10%
~~----OV
_:55nsl_
~+-
~___________~
I /~10~%~-Notes
1 The pulse generator has the follOWing characteristics'
duty cycle :oS 1010, ZOUT "" 50!l
2 CL Includes probe and Jig capacitance
6·111
•
IlA75450/60170 Series
Characteristics Measurement Information
Switching Characteristics (Cont.)
Fig. 14 Switching Times of Complete Drivers
Test Circuit
INPUT
10V
2.4 V
.....-_-OUTPUT
PULSE
GENERATOR . -.....
(See Note 1)
CIRCUIT
UNDER
TEST
(See Note 2)
--+--1
GND
SUB
CL ~ 15 pF
(See Note 3)
0.4 V
Voltage Waveforms
-I
INPUT
"A75450
"A75451
"A75453
l
10%
:,..------3
V
90%
I
.I~~ -",.,
10%
~--------------~~-~.-------------OV
""
1I'!!9'!!'OO!!'k-----INPUT
"A75452
3V
90%
1.5V
~1~OO~~
______
OV
tPLH_1
VOH
OUTPUT
50%
-
I
10%
10%
''----------.;..".,j(-------VOL
tTLH_i I -
Noles
1 The pulse generator has the following charactenstlcs
PRR = 1 MHz, ZOUT "" 50!l
2 When testing I'A75450, connect output Y to transistor
base with a 500!! resistor to ground
3 CL Includes probe and Jig capaCitance
6·112
,uA75450/60/70 Series
Characteristics Measurement Information
SWitching Characteristics (Cont.)
Fig. 15
Latch-up Test of Complete Drivers
Test Circuit
Vs = 20 to 55 V
(See Table 2)
INPUT
5V
2.4 V
L---~~--~~OUTPUT
PULSE
GENERATOR
(See Note 1)
1-+----+---1
CIRCUIT
UNDER
TEST
(See Note 2)
GND
SUB
CL = 15 pF
(See Note 3)
0.4 V
Vs = 20 to 55 V
(see Table 2)
VOltage Waveforms
INPUT
"A75450
"A75451
"A75453
l
10%
~9~0~%----------3 V
I
~----------------------------~-~.---------------OV
~--------------40~S----------~.~!
~-----~90~,~~1_-_510ns
3V
1.B
~1_0_~_,___________
OUTPUT
\
Notes
The pulse generator has the following characteristics
PRR = 125kHz, ZOUT "" 50 n
2 When testing I'A 75450, connect output Y to transistor
base with a 500 II resistor from there to ground, and ground the
substrate terminal.
3 CL Includes probe and Jig capacitance
6·113
ov
•
JlA75491 • JlA75492
MOS to LED Segment
and Digit Drivers
FAIRCHILD
A Schlumberger Company
Interface Products
Description
The 75491 LED Quad Segment Digit Driver interfaces
MOS signals to common cathode LED displays. High
output current capability makes the devices ideal in
time multiplex systems using segment address or digit
scan method of driving LEDs to minimize the number of
drivers required.
Connection Diagrams
14-Pin DIP
ILA75491
The 75492 Hex LED/Lamp Driver converts MOS
signals to high output currents lor LED display digit
select or lamp select. The high output current
capability makes this device ideal in time multiplex
systems using segment address or digit scan
method of driving LEDs to minimize the number of
drivers required.
ILA75491
• 50 mA SOURCE OR SINK CAPABILITY
• LOW INPUT CURRENTS FOR
MOS COMPATIBILITY
• LOW STANDBY POWER
• FOUR HIGH GAIN DARLINGTON CIRCUITS
(Top View)
Order Information
Type
Package
ILA75491
Molded DIP
ILA75492
• 250 mA SINK CAPABILITY
• MOS COMPATIBLE INPUTS
• LOW STANDBY POWER
• SIX HIGH GAIN DARLINGTON CIRCUITS
Code
9A
Part No.
ILA75491PC
ILA75492
1Y
2Y
Truth Tables
GND
ILA75491
INPUTS
1A-4A
OUTPUTS
1E-4E
OUTPUTS
1C-4C
L
L
H
H
H
L
3A
3Y
4Y
(Top View)
ILA75492
H
INPUTS 1A-6A
OUTPUTS 1Y-6Y
L
H
H
L
Order Information
Type
Package
ILA75492
Molded DIP
= HIGH Level, L = LOW Level
6-114
Code
9A
Part No.
ILA75492PC
J.LA75491 e J.LA75492
Absolute Maximum Ratings
Supply Voltage
Input Voltage (Note 1)
Collector (Output) Voltage
(Note 2)
Collector (Output) to Input
Voltage
Emitter to Ground Voltage
(VIN ~ 5.0 V) 75491
Emitter to Input Voltage 75491
Continuous Collector Current
75491,
75492
Collector Output Current
(75492) all collectors
Continuous Total Power
Dissipation (Note 3)
10 V
-5.0 to VSS
Operating Temperature Range
Storage Temperature Range
Pin Temperature
Molded DIP (Soldering, 10 s)
10 V
O°C to 70°C
-55°C to +125°C
lOV
lOV
5.0 V
Noles
1 The Input IS the only device terminal which may be negative
50 mA
250 mA
with respect to ground
2 Voltage values are with respect to network ground terminal
unless otherWise noted
3 Above 60°C ambient temperature, derate linearly
at83mW/'C
600 rnA
800 mW
Equivalent Circuit (112 of IoIA75491)
COLLECTOR
INPUT
COLLECTOR
4kn
4kn
INPUT----.-~~--~_[
6kn
6kll
7kn
•
7kn
Vss----4~--------+_------~--~~._~
GND
EMITTER
EMITTER
Equivalent Circuit (1 13 of lolA 7 5492)
OUTPUT
INPUT
4.4kll
INPUT - - - -....--VVV--4.-i:
OUTPUT
4.4kll
7kll
7 kO
4301l
TO
NEXT
DRIVER
r-------4~.-~--_;--------.---~--~~
Vss----~------------~~----~
L -_ _ _..-_TO
NEXT
DRIVER
GND
6·115
TO NEXT
DRIVER
JLA75491 e JLA75492
~A75491
DC Characteristics
Vss
Symbol Characteristic
VCEL
ICH
= 10 V, TA = O°C to 70°C unless otherwise specified
Condition
LOW Level Collector
to Emitter Voltage
= 8.5 V through 1.0 kfl
= 50 mA, VE = 5.0 V
VE = 0,
VCH = 10 V
VIN = 0.7 V
VE = 0,
VCH = 10 V
liN = 40 ~A
VIN
IOL
Collector HIGH Current
II
Input Current at Maximum
VIN
Input Voltage
IER
Reverse Biased
Emitter Current
Iss
Supply Current
~A75491
AC Characteristics
Min
VIN = 8.5 V through 1.0 kfl
IOL = 50 mA, VE = 5.0 V,
TA = 25°C
IC
= 10 V
IOL
= 200 fl, VINH = 4.5 V
CL = 15 pF, VE = 0
Propagation Delay Time
tpLH
RL
= 6.5 V through 1.0 kfl
= 250 mA, TA = 25°C
VIN = 6.5 V through 1.0 kfl
IOL = 250 mA
VOH = 10 V
liN = 40 ~A
VOH = 10 V
VIN = 0.5 V
II
Input Current at Maximum
VIN
Input Voltage
ISS
Supply Current
Vss
= 10 V
V
0.9
1.5
V
100
~A
100
~A
3.3
mA
100
~A
1.0
mA
Typ
Max
Unit
20
ns
100
ns
Condition
tpHL
RL
Propagation Delay Time
IOL
Typ
Max
Unit
0.9
1.2
V
0.9
1.5
V
200
~A
200
~A
2.0
= 20 mA
3.3
1.0
mA
Min
= 39 fl, VIN = 7.5 V
CL = 15 pF
Typ
Max
Unit
30
ns
300
ns
Test Circuit
7.SV
PULSE
1k1l
GENERATOR 1----'\1"""'........
(SEE NOTE 1)
mA
= 7.5 V, TA = 25°C
Symbol Characteristic
tpLH
Min
VIN
IOL
Output HIGH Current
AC Characteristics
Min
Condition
Output LOW Voltage
~A75492
1.2
Vss = 10 V, TA = O°C to 70°C unless otherwise specified
Symbol Characteristic
IOH
0.9
Vss = 7.5 V, TA = 25°C
tpHL
VOL
Unit
= 0, VIN = 0, VE = 5.0 V
Condition
DC Characteristics
Max
2.0
= 20 mA
Symbol Characteristic
~A75492
Typ
>C:>--+-_-VOUT
Notes
1 The pulse generator has the following characteristics.
n.
ZOUT = 50
PRR = 100 kHz. tw = 1 ,",S
2 CL Includes probe and ilg capacitance.
6-116
p;A75491 • p;A75492
Waveform
VOL _ _ _ _ _ ' -_ _ _ _ _ _ _- J
Typical Application
to twelve digits of a 7-segment display plus decimal
point may be displayed using only three 75491 and
two 75492 drivers.
Interfacing Between MOS Calculator Circuit and
LED Multi-Digit Display
This example of time multiplexing the individual digits in
a visible display minimizes display circuitry. Up
,--.1:----,
I
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Vss
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RL
Vss
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QUAD SEGMENT
DRIVER
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6·117
6
~A438
FAIRCHILD
Serial Input LCD Driver
A Schlumberger Company
Interface Products
Connection Diagram
4Q-Pin DIP
Description
The ILA438 is a CMOS/LSI circuit that drives an LCD
display, usually under microprocessor control. The
part acts as a "smart" peripheral that drives up to 32
LCD segments. It needs only three control lines due to
its serial input construction. It latches the data to be
displayed and relieves the microprocessor from the
task of generating the required waveforms. The ILA438
can drive any standard or custom parallel drive LCD
display whether it be field effect or dynamic
scattering, 7, 9, 13 or 16 segment characters,
decimals, leading + or -, or special symbols. Several
ILA438s can be cascaded. The ac frequency of the
LCD waveforms can be supplied by the user or can be
generated by attaching a capacitor to the LCD ~ input,
which controls the frequency of an internal oscillator.
+VDD
LOAD
SEG 32
SEG31
SEG 30
SEG29
7
SEG 28
$&.G27
The ILA438 can also be used as a column driver in a
multiplexed LCD display. In this application it acts
as a "dumb" peripheral since timing and refresh must
be 'supplied externally.
• DRIVES UP TO 32 LCD SEGMENTS OF
ARBITRARY CONFIGURATION
• CMOS CONSTRUCTION FOR
WIDE SUPPLY VOLTAGE RANGE
LOW-POWER OPERATION
HIGH-NOISE IMMUNITY
WIDE TEMPERATURE RANGE
• CMOS, NMOS, AND TTL COMPATIBLE INPUTS
• CASCADABLE
• CHOICE OF ON-CHIP OR
EXTERNAL OSCILLATOR
• REQUIRES ONLY 3-CONTROL LINES
Absolute Maximum Ratings
Supply Voltage, VOO
Input Voltage, (CLK, Data In,
Load Inputs)
SEG 19
SEG10
SEG11
SEG12
-0.3Vto 15V
SEG 14
+Voo -15 V to
+VOO + 0.3 V
Input Voltage (LCD ~ Input)
-0.3 V to +VOO
+0.3 V
Storage Temperature Range
-65°C to +125°C
Operating Temperature Range
-40°C to +70°C
Pin Temperature (Soldering, 60 s) 300°C
(Top View)
Order Information
Type
Package
ILA438
Ceramic DIP
6-118
Code
61
Part No.
1LA438JC
,uA438
Block Diagram
CLK-----.
32-BIT STATIC SHIFT REGISTER
DATAIN--....
LOAD--....
DATA OUT
32 LATCHES
32 SEGMENT DRIVERS
LCD
32 OUTPUTS
Electrical Characteristics
~
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~
~~~~~~ANE
Voo = +5 V unless otherwise specified
Symbol
Characteristics
Voo
Supply Voltage
Condition
1001
1002
Supply Current
VIH
Input HIGH Level
VIL
IL
Input LOW Level
Input Current
CI
Input Capacitance
RON
Segment Output Impedance
RON
Backplane Output
Impedance
RON
Data Out Output
Impedance
f
Clock Rate
50% Duty Cycle
dc
tos
Data Set-up Time
Data change to
Clock falling edge
150
LCDc/> Osc at
LCDc/> Driven
Min
Max
3
13
< 15 kHz
60
10
0.5 VOO
Clock
Data
Load
VOO-15
IL = 10 J.LA
Voo
0.2 Voo
5
Unit
V
J.LA
J.LA
V
V
5
J.LA
pF
40
kfl
3
kfl
3
kfl
1.5
MHz
ns
tOH
Data Hold Time
100
ns
tpw
Load Pulse Width
200
ns
tpd
Data Out Propagation Delay
VIH
LCDc/> Input HIGH Level
VIL
IL
LCDc/> Input LOW Level
LCDc/> Input Current
CL = 15 pF
500
0.1 VOO
5
Driven
6·119
ns
V
0.9 VOO
V
J.LA
•
JLA438
Applications
1. The shift register loads, shifts, and outputs on the
falling edge of Clock.
2. A logic 1 on Data In causes a segment to be visible.
3. A logic 1 on Load causes a parallel load of the data
in the shift register into the latches that control the
segment drivers.
4. If LCD is driven it is in phase with the
Backplane Output.
5. To cascade units, (a) connect the Data Out of one
chip to Data In of next chip, and (b) either connect
Backplane of one chip to LCD of all other chips
(thus one capacitor provides frequency control for
all chips) or connect LCD of all chips to a
common driving signal. If the former is chosen,
don't tie all backplanes together Gust use one of
them) and drive LCD with a Backplane output that
doesn't go to the actual backplane. (This reduces
the dc component of driving signals).
6. The supply voltage of the ,uA438 is equal to half the
peak-to-peak driving voltage of the LCD. If the
,uA438 supply voltage is less than the swing of the
controlling logic signals, the positive supply leads
of the logic circuitry and the ,uA438 should be tied
in common, not the ground (or negative) supply
leads. Be careful that input level specifications
are met.
7. The LCD pin can be used in two modes, driven
or oscillating. If LCD is driven, the circuit will
sense this condition and pass the LCD input to
the backplane output. If the LCD pin is allowed to
oscillate, its frequency is inversely proportional to
capacitance and the LCD driving waveforms have a
frequency 28 slower than the oscillator itself. The
approximate relationship is fout(Hz) = 2500/ c(pF).
8. Avoid changing Data In when clock is falling. Avoid
changing Load when clock is falling.
9. The number of a segment corresponds to how many
clock pulses have occurred since its data was
present at the input. For example, the data on
SEG 19 was the Data In 19 clock pulses earlier.
6-120
F=AIRCHILO
A Schlumberger Company
YOItage ReguJatcus .•......•
.Hybti
I '"
•
1.31
•
.
•
i"-,
1.300
9
1.29
~
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~~
""
ill
~ 075
;!:
0."
;!:
50 - 25
0
25, 50
75
TA - AMBIENT TEMPERATURE -
0.2
1.6
.1-- I--
100 125
V
TS
r
= Tin (2 EourfLSB)
=10pFRL
LOAD RESISTANCE - kO
Full Scale Output Current
Drift as a Function of
Ambient Temperature
~
I--
,/
10
rnA
-
~
0.004
a:
o
0.002
"
!;
V- = -15V
,.,/
~
~ -000 2
::l
~
o
1.28s
1 rnA MSe CURRENT
_v+ = 5.0 V
~.
.
1.290
V
---
r-
/
-0.00 4
•
;!. -000
4.'
-1'
"C
0
2.0
./
,/
~ /'
!V
•
1.280
0.25
A/'
~V
U)
0.00
I 1.30
~
,,~
S
TA = 25"C
1.31 0
>
~ P'"
,«
0.6
>=
Input Logic Threshold
Voltage as a Function of
Supply Voltage
91.00
75
1.6
1.4
1.2
V
:E
k.•'T
MSB CURRENT -
V+ "" 5.0 V
"" ""
1.0
~~
'!l.
~
I--
10·81
2.0
v- = -15V
.......
1.2
-
12'81T
"~ 0.4
0
o
1.2
Input Logic Threshold
Voltage as a Function of
Ambient Temperature
~
l - I- t -
•
1.0
~
-
"z •
U)
0
!;1
=
>=
0
.
•
I
1 rnA MSB CURRENT
rV+ = S.OV
V - "" 15V
0.8 f--TA "" 25"C
= 5.0V
= 15V
TA 25"C
v-
~ 12
.
1.0
SUMMING JUNCTION LOAD
•
15
I
'"
>= 4
• v+
17
SUMMING JUNCTION LOAD
60
Settling Time as a
Function of Load Resistance
(0 to FSI Output ± 112 LSB)
...
'.0
-15
-1.
SUPPLYVQlTAGE - V
-0,008
-75 -50 -25
0
25
SO
75
TEMPERATURE - ·C
100 125
Typical DC Test Circuit
BIT INPUTS
R8
100k ±O.P/o;>
5,
ZERO
ADJUST
.•• e F
1
100
t----.¥v---s5 k
R'
10k
R4
8Dk
Notes
1. Required resistor ratio tolerances of R 1-R5 to test the various
grades are as follows:
9650-1C, R5 to R2 to R 1- ±0.005%, R3 to R 1- ±0.01%,
R4 to R 1- ±0.02%.
9650-2C, R5 to R2 to R 1- ± 0.025%, R3 to R 1- ± 0.05%,
R4 to R 1- ± O. 1%.
R3
40k
R2
20k
R1
10k
5k
9650-3C, R5 to R2 to R 1- ±0.1%, R3 to R 1-±0.2%,
R4 to R 1-±0.4%.
2. S1 closed and S2 open for output current (all Bits off)
tests only.
7-6
,uA9650
Typical Applications
Voltage to Frequency Converter
+5V
J1::::::fl
CP
15k
FREQUENCY
OUT
50 kHz MAX
FD333
DC
20k
IN
OTO +10V
12
10 k
10 k
1
Ax
'O "F
v-
a-Bit d / a Converter
EOUT
15k
10 V
VREF
7-7
2k
•
~A9650
Typical Applications (Cont.)
8-Blt aid Converter
SERIAL DATA
CLOCKOUTPUT
J. I I I I
-
-
0, A, 03
CLOCK
Y
~
~.
1/4:,'"
CEP 9318 UP
l 4 J 0CET BINARY TC
CP
CP COUNTER
8
-< K A a 0 - -
MR
1/.1002
~.
PE Po P1 P2 P3
II
f"]
a
;-- J
....
.... r.-
l
co NVERSION
co MPLETE
SE RIAL DATA
OUTPUT
CP
~KBOp--.... 8
8
...
1/4:00~
,,.
II.::;;'
E
D
Ao
AI
u
A,
833.
8-BIT ADDRESSABLE LATCH
C01,3'
5
8
h
7
---.:t
L....-
LSB
PARALLEL
DATA
OUTPUT
10V
FULL SCALE ADJ
VREF
11
MSB
,MA728
31'
5k
L....---
-
8k
+5V
"'- 6 4
~~8
'Q I"
-
"'- 18 •
1
3C
10
3
,
J.LA9650
3C
""::-7
1
10
-12
5
14 13 11 5
10k 20k 40k 80k
15
k f 8 1510k" 20k1340k11BOk
30pF
-=-
I'A9850
L,
lOol
~
. r==
~8
-:F'7
8
,
3
~~
1 'A:34:
-15V
10k
-15V
QUAD2°~D
FD777:2
s::
J
::s ~FD777
5k
ANALOG
INPUT
Note
Digital GND indicated by
Analog GND indicated by
lOOk
...L..
7-8
15k
100n
'k
-=1k
220k
-15V
f.LA9706 a-Channel,
12-Bit D / A Converters
I=AIRCHILO
A Schlumberger Company
Data Aquisition Products
Connection Diagram
14-Pin DIP
Description
The jJ.A9706 is a d / a converter which allows a
microprocessor system to interface and control
analog systems. The jJ.A9706 is programmed by 9-bit
words, accepted in a serial format, providing
conversions on all channels simultaneously and
continuously as long as the oscillator signal is
present. Digital-to-analog conversion is accomplished
using a pulse-width ratio technique for directly
contrOlling the duty cycle of the output pulse streams.
Each channel, when appropriately filtered, supplies
6-bit resolution, or 64 discrete analog levels.
By properly summing two outputs, the resolution
may be controlled up to 12 bits, or 4096 discrete
levels. Each channel output maintains 12-bit, or
± .01% full-scale, accuracy.
•
•
•
•
•
•
•
•
•
14
W/R
DATA CLOCK
05
VDD (+V)
00
(Top View)
Order Information
Type
Package
jJ.A9706
Molded DIP
jJ.A9706
Ceramic DIP
Absolute Maximum Ratings
Digital Input Range
Output Sink or
Source Current
Operating Temperature
Storage Temperature
Pin Temperature (Soldering)
Ceramic DIP (60 s)
Molded DIP (10 s)
06
DATA INPUT
MICROPROCESSOR COMPATIBLE
CMOS TECHNOLOGY
LOW COST
INDEPENDENT CHANNEL OPERATION
LINEARITY ±O.01%
EXPANDABLE TO 12-BIT RESOLUTION
INTERNAL MEMORY
SINGLE SUPPLY +5 V
EXCELLENT STABILITY NO ADJUSTMENTS
Voo Relative to VSS
OSC INPUT
(-V) Vss
-0.3 V to 5.5 V
-0.3 V to Voo +0.3 V
25 mA
O°C to 85°C
-65°C to +150°C
7·9
Code
9A
7A
Part No.
jJ.A9706PC
jJ.A9706DC
•
JLA97 06
Functional Diagram
OSC
INPUT
DISABLE
a:
....
'"
'"
(;
'"....a:
II.
i
'"
....
'"a:
...::>'"
II.
iii
d>
III
oil
6 x 8 RAM
z
OUTPUTS
a::
J:
(J
'"
'"CCJ
'"
0
oJ
(J
DATA
DATA
INPUT
8
Cl
..:
>I:
DATA
CLOCK
DATA
OUT
wiR"
Functional Description
The /lA9706 consists of seven functional blocks: a
6-bit binary counter, a pulse distributor called a
priority encoder, 6 x 8 RAM, 1-of-8 channel address
decoder, 6-to-1 channel-data multiplexer, 9-bit input
shift register, and a set of eight output buffers.
open-collector TTL or CMOS logic that produces a
square-wave signal with a frequency in the range of
50 kHz to 2 MHz. The time intervals (binary-weighted
pulse widths) generated by the counter are decoded
by the priority encoder which serves two functions.
First, it ensures that each of the six time intervals
(control pulses) is used once during the conversion
cycle. Second, it distributes the control pulses to both
the channel-data multiplexer and to the columnaddress inputs of the 6 x 8 RAM.
The pulse-width-ratio conversion scheme divides the
conversion cycle into binary-weighted time intervals
and associates each time interval with a bit position in
the 6-bit control word. The control word residing in
RAM is then addressed, bit by bit, each bit addressed
for the associated time interval. The value of each bit,
"1" or "0," controls the output, HIGH or LOW, during
this time interval (see Figure 1). In this manner, an
output pulse stream is generated with a duty cycle
defined by the control word. When the pulse stream is
filtered, a dc value is extracted that is proportional to
the duty cycle of the pulse stream and, hence,
proportional to the control word.
The channel-data multiplexer is enabled during the
write mode so that the 6-bit control word may be
written. The 6 x 8 RAM provides the storage capability
required for the converter to operate independently of
the microprocessor, once the control information has
been transferred. Since the control information is
stored in RAM, simultaneous conversions continue on
all eight channels, unaided by the microprocessor
unless changes are required. This is accomplished by
addressing a single bit in each of the control words
and reading the results out in parallel during each time
The 6-bit counter generates the fundamental time
intervals for the system and may be driven by any
7·10
1LA9706
interval in the conversion cycle. The total cycle time,
which is the sum of the six binary-weighted time
intervals plus a unit interval (64 clock periods),
requires 128 oscillator periods, since the basic
oscillator frequency is divided by a factor of two
before driving the counter. Conversions may be
completed in as little as 64 J.LS when operating at a
2 MHz clock rate. The control words read from the
RAM are directed to the output buffers, six of which
have 1 kO and two have 50 0 output impedances. In
general, these buffers should drive load impedances
larger than the output impedance to reduce the errors
caused by the finite output impedance.
control word (channel data) and the 3-bit channel
address are serially transferred to the 9-bit shift
register on the HIGH-to-LOW transitions of the data
clock (Figure 2). The data clock has a maximum
frequency of 125 kHz with a minimum HIGH and LOW
time of 4 J.Ls. Once the nine bits of data have been
transferred into the shift register, the data clock must
remain static until the write operation is completed to
prevent the data from being shifted out of the register.
The write mode may be selected after a minimum
setup time of 1 J.LS and is enabled by a HIGH-going
W IR control pulse. This sets an internal latch that
enables the channel-address decoder, which decodes
the 3-bit binary channel address, therefore effecting
the transfer of the 6-bit control word from the input
register to RAM via the channel-data multiplexer at
the beginning of the next conversion cycle. The W IR
pulse has two restrictions: first, it must be equal to
or greater than 4 J.Ls in duration; second, it must be
less than 128/fosc . This latter restriction is necessary
to eliminate the possibility of multiple loads occurring
from a single W IR pulse that could lead to incorrect
control-word transfers under certain conditions.
Each output is capable of providing 64 discrete output
levels representing 6-bit resolution. Since each output
pulse stream is accurate to 12 bits, it is possible to
sum two outputs and expand the resolution to 12 bits,
providing 4096 discrete output levels. This may be
easily accomplished by weighing one of the outputs by
a factor of 1/64 before summing.
Loading data is a simple procedure that does not
affect the conversion cycle. For the J.LA9706, the 6-bit
Fig. 1
Output Cycle Example
LSB
MSB
o
o
o
(DECIMAL 21) = RAM CONTENT
ONE OUTPUT CYCLE
i
~r------------------------------------~~,------------------------------------~,
II
::.Izl. . .
_4_......
8 OSC CYCLES
16 OSC CYCLES
II
32 OSC CYCLES
I
64 OSC CYCLES
...
- ------...I~
~14--------------------------------------128CYCLES------------------------------~.I
TIME
Fig. 2
OUTPUT
VOLTS
1
J.LA9706 Input Timing and Format
FIRST BIT
IN
LAST BIT
CHANNEL ADDRESS IN
CHANNEL DATA
DATA INPUT
DATA
CLOCK
Fl.,:/R
----------------------------------------------------------------------------~
TIME_
7·11
I
I
•
1LA97 06
/LA9706
Electrical Characteristics
Voo = +5 V, Vss = 0 V, TA = O°C to +70°C, lose = 100 kHz
Symbol
Characteristic
Typ
Max
Unit
Ro
Output Resistance (Channels 4 & 5)
30
50
Ro
Output Resistance (Channels 0, 1, 2, 3, 6, 7)
300
1000
n
n
Min
lose
Oscillator Frequency
50
tH
Data Clock HIGH Time
4
tL
Data Clock LOW Time
4
tW/R
W / R Pulse Width
4
Error
2000
kHz
/LS
/LS
128/fose
/LS
Linearity
0.01
%
VIH
Voltage Input HIGH
2.7
V
VIL
Voltage Input LOW
100
Power Supply Current
200
/LA
liN
Input Current
50
/LA
CIN
Input Capacitance
tr
Input Rise Time
1.0
/LS
0.8
V
40
8
pF
t,
Input Fall Time
1.0
/LS
ts
Input Set-up Time
1.0
/LS
Typical Applications
+5 V
+Voo
~
5 V
00
t---~W/R
0,
DATA
1/0 PORT
"P
{
CLOCK
DATA
INPUT
02
03
TYPICAL OF EIGHT CHANNELS
"A9706
50 k
50 k
o4t--------~~-,-~~,-----~~P~~A~~~LOAD
C2LO
MCHKZ t---~ OSC 05
INPUT
06
07
Vss
7-12
J.LA9706
Typical Applications (Cont.)
Fa Object Code Subroutine
Enter with Ro = data to be output to 9706
Rl
address to be output to 9706
entry
H'100'
=
=
Ml00 - 130
M0100 = 20
M0108 = BO
MOllO = 24
MOl18 = 50
M0120 = 43
M0128 = 94
M0130 = lC
F8 Object Code
Exit
= return.
20
20
OC
42
52
E3
52
OF
BO
12
70
20
20
BO
24
52
51
OB
04
40
02
94
53
BO
53
22
BO
EF
40
20
20
FE
40
41
18
OF
07
18
12
50
18
BO
Port
Port
Port
Port
0
0
0
0
bit
bit
bit
bit
0
1
2
3
= Data Input
= Data Clock
= W /R'
= Scope Trigger
destroyed Ro. R 1. R2. R3. Acc
Varactor Tuned 12-Bit Receiver System
VDD
"0
,o"'{
~
5 V
W/R
.........
DATA
CLOCK
DATA
INPUT
TO
OTHER
CONTROLS
~A9706
~p
CLOCK
OSC
INPUT V
t--.JV'.t'It-_- AUDIO LEVEL
CONTROL
I
7-13
TO
VARACTOR
~A9708
8-Bit ~p
6-Channel
Compatible AID
Converter
FAIRCHILD
A Schlumberger Company
Data Aquisition Products
Description
The ~A9708 is a single slope 8-bit, 6-channel ADC
subsystem that provides all of the necessary analog
functions for a microprocessor-based data control
system. The device uses a microprocessor system
like the F3870 or F6800 to provide the necessary
addressing, timing and counting functions and includes
a 1-of-8 decoder, 8-channel analog multiplexer,
sample and hold, ramp integrator, precision ramp
reference, and a comparator on a single
monolithic chip.
•
•
•
•
•
•
•
•
•
Connection Diagram
16·Pln DIP
MPU COMPATIBLE
EXCELLENT LINEARITY OVER FULL
TEMPERATURE RANGE ±O.20/0 MAXIMUM
TYPICAL 300 ~s CONVERSION TIME
PER CHANNEL
WIDE DYNAMIC RANGE INCLUDES GROUND
AUTO·ZERO AND FULL·SCALE
CORRECTION CAPABILITY
RATIOMETRIC CONVERSION-NO PRECISION
REFERENCE REQUIRED
SINGLE·SUPPLY OPERATION
TTL COMPATIBLE
DOES NOT REQUIRE ACCESS TO DATA BUS OR
ADDRESS BUS
(Top View)
Order Information
Type
Package
~A9708
Ceramic DIP
~A9708
Ceramic DIP
~A9708
Molded DIP
Code
7B
7B
9B
Block Diagram
RAMP START
(FROM MPU)
r---------------------- ------------------1
3
I
I
h
II
1
15 1
SAMPLE
7 RAMP STOP
(TO MPU)
I IREF
+
AND RAMP
AMPLIFIER
COMPARATOR
ANALOG
INPUTS
CONSTANT
CURRENT
SOURCE
-=-
VeE
1-0F-8
AODRESS DECODER
I
I
c______
• Patent Pending
--r·-----------· -. _
I
~~. ----~ ~-;-.;;.;.;;;.:;;;;."'
Vee
VREF +Vcc
7·14
-
Part No.
~A9708DM
~A9708DC
~A9708PC
JLA9708
Absolute Maximum Ratings
Supply Voltage (VeC>
Comparator Output (Ramp Stop)
Analog Input Range
Digital Input Range
Output Sink Current
Operating Temperature Range
#A9708PC,#A9708DC
#A9708DM
Storage Temperature Range
Continuoua Total Dissipation
Ceramic DIP Package
Molded DIP Package
Pin Temperature,
Ceramic DIP (Soldering, SO s)
Molded DIP (Soldering, 10 s)
For applications that require auto-zero or autocalibration, (See Figures 2-5) line select address
0, 0, 0 and 1, 1, 1 may be used in conjunction with the
arithmetic capability of the microprocessor to provide
ground and scaling factors. Address 0, 0, 0 internally
connects the input of the ramp generator to ground
and may be used for zero offset correction in
subsequent conversions. Address 1, 1, 1 internally
connects the input of the ramp generator to the
voltage reference, VREF, and may be used for scale
factor correction in subsequent conversions. For the
following, refer to the Functional Block Diagram.
18 V
-0.3 V to +18 V
-0.3 V to 30 V
-0.3 V to 30 V
10 mA
O°C to 70°C
-55°C to 125°C
-S5°C to +150°C
900mW
1000 mW
Recommended Operating Conditions
Characteristic
Min Typ
Supply Voltage (VeC>
4.75 5.0
Reference Voltage (VREF)" 2.8
Ramp Capacitor (CH)
300
Reference Current (IR)
12
Analog Input Range
0
Ramp Stop
Output Current
Six separate external analog voltage inputs may come
into terminals 11-16 and the specific analog input to be
converted is selected via address terminals Ao-A2.
The analog input voltage level is transferred to the
external ramp capacitor connected to pin 4 when the
input to the ramp start terminal (pin 3) is at a logic 0
(See Figure 1). The time to charge the capacitor is the
acquisition time which is a function of the output
impedance of an amplifier internal to the a/ d converter
and the value of the capaCitor. After charging the
external capacitor the ramp start terminal is switched
to a logic 1 which introduces a high impedance
between the analog input voltage and the
external capacitor.
Max Unit
15
V
5.25 V
pF
50
#A
VREF V
1.S
mA
Note
'2 V :$ VREF:$ (Vee -2 V)
The capacitor begins to discharge at a controlled
rate. The controlled rate of discharge (ramp) is
established by the external reference voltage, the
external reference resistor, the value of the external
capacitor and the internal leakage of the a/ d
converter. Connected to the capaCitor terminal is a
comparator internal to the a/ d converter with its
output going to the ramp stop terminal (pin 7). The
comparator output is a logic one when the capacitor is
charged and switches to a logic 0 when the capacitor
is in a discharged state. The ramp time is from the
time when ramp start goes HIGH (logic "1") to when
ramp stop goes LOW (logic "0"). The microprocessor
must be programmed to determine this conversion
time. The ideal (no undesirable internal source
impedances, leakage paths, errors on levels where
comparator switches or delay time) conversion time is
calculated as follows:
Channel Selection
Input Address Line
A2
A1
Ao
Selected
Analog Input
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Ground
11
12
13
14
15
16
VREF
Functional Description
This Analog to Digital Converter is a single-slope 8-bit,
S-channel a/ d converter that provides all of the
necessary analog functions for a microprocessorbased data/control system. The device uses the
processor system to provide the necessary
addressing, timing and counting functions and includes
a 1-of-8 decoder, 8-channel analog multiplexer,
sample and hold, precision current reference, ramp
integrator and comparator on a single monolithic chip.
CH
Ramp Time
Where
VI
= VI IR
= Analog Input Voltage being measured
CH = External Ramp Capacitor
Vee - VREF
RREF
Where
= Power Supply Voltage
VREF = Reference Voltage
Vee
RREF
= Reference Resistor
In actual use the errors due to a nonideal aId
converter can be minimized by using a microprocessor
to make the calculations. (See Figures 1 through 4 )
7·15
JLA9708
Auto-Zero and Full-Scale Features
Fig. 3
Fig. 1 Ideal Transfer Function
Transfer Functions with
Zero-Correction Added
COUNT
COUNT
2561--------"71
N"Fs 1----------....",.......--
N'I-------:;:oo......-
12.1--------,.('
.--
INPUT
VREF
VI"
VREF
INPUT
VREF
n' = n - nz
n' Has Full·Scale Error
No Zero Offset
No Full·Scale Error
Fig. 4
VIN
Count (n) = -V-- x 256
REF
Transfer Function with both Zero and
Full-Scale Correction Added
COUNT
Fig. 2
Transfer Function with Zero and
Full-Scale Error
N"FS
1-----------:".....
COUNT
NI------",r"
NFSI-_ _ _ _ _ _ _ _
~~~
N I------:".,..~
VI"
Nz
256
nil = (n - nz)
VIN
VREF
INPUT
nF.S. -:/= 256
nZ -:/= 0
(n) Has Both Full·Scale and Zero Errors
7-16
x (nF.S. - nz)
VREF
INPUT
~A9708
Electrical Characteristic
Over recommended operating conditions, -55°C:S TA:S +125°C, for /LA970BDM and
O°C :S TA:S +70°C for /LA970BDC or /LA970BPC; unless otherwise specified.
Symbol Characteristic
Min
Condition
Typ
Max Unit
±0.3 %
EA
Conversion Accuracy
Over entire temperature range
(Note 1)
ER
Linearity
Applies to anyone channel
(Note 2)
±O.OB ±0.2 %
VOSM
Multiplexer Input Offset Voltage
Channel ON
2.0
4.0
mV
te
Conversion Time Per Channel
Analog Input = 0 V to VREF
CH = 300 pF, IREF = 50/LA
296
350
/LS
tA
Acquisition Time
CH
20
40
/LS
IA
Acquisition Current
to
Ramp Start Delay Time
= 1000 pF
±0.2
150
tM
Multiplexer Address Time
VIH
Digital Input HIGH Voltage
Ao, Al, A2, ramp start
VIL
Digital Input LOW Voltage
Ao, Al, A2, ramp start
IS
Analog Input Current
Channel ON or OFF
IlL
Input LOW Current
Ao, Al, A2, ramp start
Ao,
100
/LA
ns
1.0
/LS
2.0
V
O.B
= 0.4 V
A 1, A2, ramp start = 5.5 V
-3.0
-1.0
-15
-5
V
/LA
/LA
IIH
Input HIGH Current
1.0
lOS
Input Offset Current
/LA
3.0
10H
Comparator Logic "1" Output
Leakage Current
/LA
VOH
= 15 V
10
/LA
VOL
Comparator Logic "0"
Output Voltage
10L
= 1.6 mA
0.4
V
PSRR
Power Supply Rejection Ratio
(Note 3)
40
dB
Cross Talk Between Any
Two Channels
(Note 4)
60
dB
lee
Power Supply Current
Vee
CIN
Input Capacitance
3.0
pF
COUT
Comparator Output Capacitance
5.0
pF
1.0
= 5 V to
Notes
1. ConversIon accuracy is defined as the deviations from a
straight lone drawn between the points defined by channel
address 000 (0 scale) and channel address 111 (full scale) for
all channels.
2. Linearoty IS defined as the deVIation from a straight line drawn
between the a and full scale points for each channel.
15 V, 10
=0
7.5
15
mA
3 Power supply reiec.tion ratio is defined as the conversIon
error controbuted by power supply voltage variations while
resolving mId scale on any channel.
LlVCH
4 Cross Talk between channels = 20 log ~
7-17
•
~A9708
Fig. 3
Test Circuits
Fig. 1
linearity/Acquisition Time/Conversion
Time Test Circuit
Equivalent Timing Waveform for Test
Circuits and Applications
475 V
I-IA-1
"~m::
Ao
h
Vee
IJ
12
14
Is
16
Ii----iff-f- - - - - -
+2V - - - ,
~r-'
V,"+07V~
I
I
CAPACITOR
VOLTAGE
OV
vcc~
0.4 V
+4.75 V +4.75 V
f~
I
Fig. 4
~IR-I~-
RAMP STOP
I.
-
-
---+----~
I
I '--------------
0.7V---
Static Measurements
1 - - - - , c - - -...·-11
Ao
Fig. 2
11
Vee
12
b
14
15
Is
pA9708
Slow Speed Evaluation Circuit for
Ratlometrlc Operation
ANALOG INPUTS
~
__
~A~
_ _ _ _ _ __
ALL COMPONENTS
'------y------J +5 V
±10%
+5 V +15 V
VIL, VIH. IIL,IIH
Ao
11
Vee
12
b
14
15
16
+5 V
}.IA970B
Al
RAMP
RAMP
A2 STARTCH GND RREFSTOPVREF
Typical Applications
2>
Application Suggestions and Formulas
1. The capacitor node impedance is approximately
30 J,LQ and should have no parallel resistance for
proper operation.
2. tR when VIN = 0 V will be finite (Le., the
comparator will always toggle for VIN 2:: 0 V).
3. The ramp stop output is open collector, and an
external pull-up resistor is required.
4. All digital inputs and outputs are TTL compatible.
5. For proper operation, timing commences on the
o to 1 transition of ramp start and terminates on
the 1 to 0 transition of ramp stop.
CH
6. tA 2: 150 J,LA _ IR x VREF
33>
CONTROL 1/0 FROM MPU
(TIMING COMPATIBLE WITH FIGURE 1)
Input Timing:
tA> 400
VREF
IR
=
=
J,LS
kQ
)
( 2 kQ3.3
+ 3.3 kQ 5 V
5-3.1
100 kQ
tR Imax
= 3.1
= 19 J,LA
7. tR (ramp time)
= full scale ramp time
8. IR =
0.01 x 10- 6
19 x 10 6 x 3.1 = 1.6 ms
CH
= -IR
x VIN tR I
'max
CH
= -IR
x VREF
Vee - VREF
RREF
9. 2 V ::5 VREF ::5 (Vee - 2 V)
10. Address lines Ao, A1, A2 must be stable
throughout the sampling interval, tAo
11. Pin 6 (RREF) should be bypassed to ground via a
0.02 J,LF capacitor
Note
For evaluation purposes, the ramp start timing generation can be
Implemented with a IlA555 timer (astable operation) or MPU
evaluation kit, and a time Interval meter for ramp time
measurement. The TIM meter will measure the time between
the 0 to 1 transition of the ramp start and the 1 to 0 transition of
the ramp stop. The ramp stop is open collector, and must have an
external pull· up resistor to Vee.
7·18
p;A9708
Typical Applications (Cont.)
Microprocessor Considerations
Several alternatives exist from a hardware/software
standpoint in microprocessor based systems using
the I'A9708.
a. The subtractions are single
op code instructions.
b. The full scale correction uses a multiply by 256
and can be accomplished by a shift left 8 bits
(usually one instruction) or placing (n - nz) in
the MSB register and setting the LSB register to
zero, for the double precision divide.
c. The divisor (nF.S. - nz) of the MSB register will
always be zero.
1. The ramp time measurement may be implemented
in software using a register increment, followed by
a branch back depending on the status of the
ramp stop.
2. Alternately, the ramp stop may be tied into the
interrupt structure in systems containing a
programmable binary timer. This scheme has the
following advantages:
These schemes have the following advantages:
a. No access to the data bus or address bus is
required, by the aId system.
b. 4110 bits completely support the aId system.
c. Since auto full scale/auto zero are implemented
in software and long term drift (aging) effects
are eliminated.
d. Software overhead is minimal (typically
30 bytes).
e. Where ratiometric operation is permissible, the
4 external components may be ± 5% tolerance,
including the power supply.
a. The CPU is not committed during the ramp
time interval.
b. It requires only 4 bits of an I/O port for
control signals.
3. The auto-zero / auto-full-scale (see Figures 2-5)
should use double precision, rounded (as opposed
to truncated) arithmatics. Several points are
worth noting:
Fig. 1
Ratlometrlc Strain Gage Sensor/Controller
Vcc+
Fa
SYSTEM
RAMP
START
'2
COMP
A3
Ia
.,
p.A970B
'5
A,
..,
3851
I/O POAT
A,
CAP
"
1-1>--'1iV'r-- Vcc+
VREF
A2
-::'
OUTPUT
Note
~VI
= (Applied Force) and can be Linearized (if necessary) in Fa Software.
7-19
JLA9708
Typical Applications (Cont.)
Fig. 2
Opaque Solution Controller
SENSOR
Vee"
Vcc+
.-J
.3
vr+
F8
SYSTEM
N
h
RAMP
START
_'2
COMP
PHOTO
RESISTOR
-(
D·,
-"
-"
.,
vcc+
-::-
A3
~A9708
1-'5
A,
,-'6
CAP
IREF
VREF
GND
.2
J-
3851
I/O PORT
A2
'R-
F
Vcc+
CONTROL
CIRCUITS
Applications
Ramp Current
Beverage Brewers / Dispensers
Chemical Solution Control
Automatic Liquid Mixing Control
VI
i~
= IR = Vee
(
R1
R1
+ R2
) (_1_)
Ra
= (RX ~ RS) Vee+
Ramp Time
7·20
= VI
(~:) = (RX ~ RS) (1 + :~) (CHRa)
f.,tA198/298/398
FAIRCHILO
Monolithic Sample and
Hold Amplifiers
A Schlumberger Company
Data Acquisition Products
General Description
The /-IA 198! 298! 398 are Monolithic Sample and
Hold Amplifiers which utilize BI-FET technology to
obtain ultra-high dc accuracy with fast acquisition of
signal and low droop rate. Operating as a unity gain
follower, dc gain accuracy is 0.002% typical and
acquisition time is typically 4 /-IS to 0.1 %. A bipolar
input stage is used to achieve low offset voltage and
wide bandwidth. Input offset adjust is accomplished
with a single pin and does not degrade input offset
drift. The wide bandwidth allows the /-IA 198 to be
included inside the feedback loop of 1 MHz op amps
without having stability problems. Input impedance of
10 10 Q allows high source impedances to be used
without degrading accuracy.
Connection Diagram
8-Pin Metal Package
LOGIC
OFFSET
ADJUST
v(Top View)
P-channel junction FETs are combined with bipolar
devices in the output amplifier to give droop rates as
low as 5 mV ! min with a 1 /-IF hold capacitor. The
JFETs have much lower noise than MOS devices used
in previous designs and do not exhibit high
temperature instabilities. The overall design
guarantees excellent feedthrough rejection from input
to output in the hold mode even for input signals equal
to the supply voltages.
Order Information
Type
Package
/-IA 198
Metal
/-I A 298
Metal
/-I A 398
Metal
Code
5W
5W
5W
Part No.
/-I A 198HM
/-IA298HC
/-IA398HC
Connection Diagram
8-Pin DIP
8
•
•
•
OPERATES FROM ±5 V TO ± 18 V SUPPLIES
ACQUISITION TIME TO .1% TYPICALLY 4 /-IS
TTL, PMOS, CMOS COMPATIBLE LOGIC INPUT
1.4 V DIFFERENTIAL THRESHOLD
• 0.5 mV TYPICAL HOLD STEP AT CH = 0.01 /-IF
• LOW INPUT OFFSET
• 0.002% GAIN ACCURACY
• LOW OUTPUT NOISE IN HOLD MODE
• HIGH SUPPLY REJECTION RATIO IN SAMPLE
OR HOLD
• WIDE BANDWIDTH
v+
LOGIC
OFFSET
ADJUST
LOGIC
REFERENCE
INPUT
v-
OUTPUT
(Top View)
Functional Diagram
Order Information
Type
Package
/-IA 198
Molded
/-IA298
Molded
/-IA398
Molded
OFFSET
2
~OUTPUT
LOGIC±=[>LOGIC 7
- - - -
300
REFERENCE
HOLD
CAPACITOR
7-21
Code
6T
6T
6T
Part No.
/-IA198RM
/-IA298RC
/-IA398RC
JLA 198 • JLA298 • JLA398
Absolute Maximum Ratings
Supply Voltage
Power Dissipation (Package
Limitation) (Note 1)
Operating Ambient Temperature
Range
j.tA198
j.tA298
j.tA398
Storage Temperature Range
Input Voltage
± 18 V
500 mW
-65°C to +150°C
Equal to Supply
Voltage
Logic-to-Logic Reference
Differential Voltage (Note 2)
Output Short Circuit Duration
Hold Capacitor Short Circuit
Duration
Pin Temperature (Soldering, 10 s)
-55°C to +125°C
-25°C to +85°C
O°C to +70°C
+7 V, -30 V
Indefinite
10 s
300°C
j.tA 198/j.tA 298/j.tA398
Electrical Characteristics
j.tA198/j.tA298
j.tA398
Min
Min
Typ
Max
Typ
Max
Unit
TJ = 25°C
Full Temperature Range
1
3
5
2
7
10
mV
mV
TJ = 25°C
Full Temperature Range
5
25
75
10
50
100
nA
nA
Input Impedance
TJ = 25°C
10 10
10 10
Q
Gain Error
TJ=25°C,RL=10k
Full Temperature Range
0.005
0.002
0.02
0.01
0.004
0.02
%
%
Feedthrough Attenuation
Ratio at 1 kHz
TJ = 25°C, CH = 0.01 j.tF
V7 = V8 = 0 V
90
dB
Output Impedance
TJ = 25°C, "HOLD" mode
Full Temperature Range
Characteristic
Conditions (Note 3)
Input Offset Voltage
(Note 6)
Input Bias Current
(Note 6)
86
TJ = 25°C, CH = 0.01 j.tF,
VOUT = 0
TJ ~ 25°C
"HOLD" Step (Note 4)
Supply Current (Note 6)
96
80
0.5
2
4
0.5
4
6
Q
Q
0.5
2.0
1.0
2.5
mV
4.5
5.5
4.5
6.5
mA
Logic and Logic Reference
Input Current
TJ = 25°C
2
10
2
10
j.tA
Leakage Current into Hold
Capacitor (Note 6)
TJ = 25°C (Note 5)
Hold Mode
30
100
30
200
pA
~VOUT
4
4
j.ts
CH = 0.01 j.tF
20
20
j.ts
Hold Capacitor Charging
Current
VIN - VOUT = 2 V
5
5
mA
Supply Voltage Rejection
Ratio
VOUT = 0
80
110
80
110
dB
Differential Logic Threshold
TJ = 25°C
0.8
1.4
0.8
1.4
Acquisition Time to 0.1 %
= 10 V, CH = 1000 pF
2.4
2.4
V
Notes
4 Hold step is sensitive to stray capacitive coupling between
mput logic signals and the hold capacitor. 1 pF, for instance,
Will create an additional 0 5 mV step with a 5 V logiC swing and
a 0.01 "F hold capacitor. Magnitude of the hold step IS
inversely proportional to capacitor value
5. Leakage current IS measured at a junction temperature of
25°C. The effects of junction temperature rise due to power
diSSipation or elevated ambient can be calculated by doubling
the 25°C value for each 11°C mcrease in chip temperature.
Leakage is guaranteed over full input Signal range.
6. These parameters guaranteed over a supply voltage range of
±5to ±18V.
1. The maximum junction temperature of the "A198IS 150°C, for
the "A298 IS 115°C, and for the "A398 IS 100·C. When
operating at elevated ambient temperature. the TO-5 package
must be derated based on a thermal resistance (0ja) of
150° C/W and the R package at (0ja) of 130· C/W.
2. Although the differential voltage may not exceed the limits
given, the common-mode voltage on the logiC pms may be
equal to the supply voltages Without causing damage to the
circuit. For proper logic operation, however, one of the logiC
pins must always be at least 2 V below the positive supply and
3 V above the negative supply.
3 Unless otherWise specified, the following conditions apply. Unit
is in "sample" mode, Vs = ± 15 V, TJ = 25°C, -11.5 V:'S VIN
:'S + 11.5 V, CH = 0.01 "F, and RL = 10 kfl. LogiC reference
voltage
0 V and logiC voltage
2.5 V.
=
=
7-22
~A198 • ~A298 • ~A398
Typical Performance Curves
250
22
L\jOUT::; 1 mY
175
NEGATIVE
!I!
~
INPUT
125
STEP
100
75
50
25
o
/
-
-50
V
~
-
25
V
V
V
t..VIN
=
HOLD MODE
0
10 V
/
1
V
MYLAR
/'
TIME
CONS TANT
'~ E:~5Y:~~:;':-~:EENE
HYSTERESIS
10-
,
POSITIVE
f--
INPUT
STEP
II IIIII
1
25
YOUT' 0
10
./
V
~
Vs - + 5
POLYPROPYLENE
AND POL VSTYR ENE
TIME CONSTANT
~ t='HYST~RVi~:
V
200
100
100
V
5f-V} ~ v_l~ 15 ~
150
Leakage Current
Into Hold Capacitor
Capacitor Hysteresis
Aperture Time
50
7S
125
JUNCTION TEMPERATURE -
Dynamic Sampling Error
100
,
II
01
150
SAMPLE TIME -
°C
10
-50
100
10
1/
-25
25
50
7S
100 125
JUNCTION TEMPERATURE -
ms
150
"C
Gain Error
Output Droop Rate
1
'E
I
w
~
5>
~
e:
"o~
0
,
TJ
~
2S C
Q
RL = 10 k
SAMPLE MODE
-
06
04
02
-- -
;::;:::;:-
;..-
-0 2
~ -0 4
g -0
... •
•
~ -08
i!!
1
-15
INPUT SLEW RATE -
Hold Step
V/ms
-10
-5
5
2
V+ ~ y. = 1S V
SETTLING TO 1 mY
!l!
6
I -5
4
2
~
0
,
6
--'"
~V
1
w
--
l--- j..---"
5
"
CH
75
100
JUNCTION TEMPERATURE -
7-23
125
'C
150
-0
...
CH
i!!
I
"
50
IIg~? 001
o
z
25
H!'~ lJ..~F1~
K
2
mm
~ -1 0
C
- 25
111m I
8
V
4
0
-50
0
1k
JJ.F
CH~O
v-
o
B
='6IH~
..,z
:i
6
o
c::
o ~
5
1~lrF
• ,.:l!
JJ.F
3o ~
iil
1I
I 111111
1/
10 k
,
,
7o
CH ~,?,1 /.IF
I
15
V
Phase and Gain
(Input to Output,
Small Signal)
"Hold" Settling Time
8
10
INPUT VOLTAGE -
HOLD CAPACITOR
2o
1
Cti
1M
100 k
FREQUENCY -
Hz
0
10M
E
J-LA 198 • J-LA298 • J-LA398
Typical Performance Curves (Cont.)
Output Short-Circuit Current
j.~I!I~5°C
'" v~ '"
vWll=ov
140HI-H+HI~+++1+IIII--Hv+
.....
4
"
2
1
ffi 10
8r-...
rr:
rr:
"u
•
4
2
0
-50
160
160 r-n-rmm--n.,.,.,,.,..-rTT1mm,.....,,,,TmII
•
~
Output Noise
Power Supply Rejection
0
8'
~OURCING
- -f',.
r--
SINKING
!g 120HI-H+HI~+++1+IIII-+tHttttt-t-tttttttt
120
IIII-t-tttttttt
01 1001ot-:+F*j.jjjt--t+!-!t!!II.",.!-±8I:1!!!f
~~~,IJ,l~E SUPPLY
100
t"-
~
80
~
60
~
40
~
....... .......
140
15 V
l~
t-H1-tf11,"",:±I-tf
NJ!Hti1IIt-1t+1tttttt--HifHtttI
~
~
NEGATIVE SUPPLY
w
I"
Z
AMPLE
MODE
'"0 40
t-H-I4+l!III-+++++lIII-+t+!lII.-l-#-HltII
~
o~+H~~~~~+mffi-~~
25
SO
75
100
125
20
10
150
cc
FREQUENCY -
1k
-130
5
.
~ 1.4
~
...........
0
.........
5
%
fil
r......
~ 08
.......
-....:r"~
0.2
o
- 25
25
50
75
100
125 150
JUNCTION TEMPERATURE - "C
-15
!g -100
~~
..........
~04
~
CH '"
...... ~"J"'7POo
rr:
0
Y7B '" 0
-110
,
1
08
- ••
o
..........
---
10
-10
INPUT VOLTAGE -
-1111 iTlII
S -80
...........
o~
-90
1"
c"
1000 pF
-70
-60
-so
1
15
10
100
1k
10 k
FREQUENCY - Hz
V
Typical Applications
Acquisition Time
X1 Sample and Hold
YIN
0
V+
O+10V
TJ '" 25"C
ANALOG
INPUT
5V-r
OV....J
looo.~~~iiiiiiji~~~~iiii
0,001
0.01
CH -
HOLD CAPACITOR -
1sl!y
p _p
YIN =
TJ '" 25°C
~ 1.2
f',.
v- '"
v+ '" 10
V
-120
~16
~
~ 10
100 k
10k
Hz
Feedthrough Rejection
Ratio (Hold Mode)
~ 1.8
0
-50
100
FREQUENCY -
5
-1 5
llillJIJ
Hz
Hold Step vs
Input Voltage
Input Bias Current
-1
"HOLD"
MODE
60
o
-25
JUNCTION TEMPERATURE _
5
80
01
",F
7-24
~~GIC
INPUT
v-
5 OUTPUT
100 k
1M
JlA198 • JlA298 • JlA398
Typical Applications (Cont.)
X1000 Sample and Hold
lN457
R3
1M
1%
15 V
10:~
OFFSET
ADJUST
f
R2
__...J1/2I/My-....._--t
R4
1k
1%
-15 V
VOUT
Notes
For lower gams, the /lA 108 must be frequency compensated
100
Use
~pF from comp 2 to ground
=
Sample and Difference Circuit
(Output Follows Input in Hold Mode)
Differential Hold
~
VB - - - - -
~
I
VOUT ::::: VB
I
VIN
~
(HOLD MODE)
0,01 pF
V,N
+>
Vs-=-
T
-----1 f-'W'v--I---'
I
1k
M
...J
r
RESET
'-TRACK
I
I
I
,..I.,
Capacitor Hysteresis Compensation
V+
, .,. /
, VCM \
V-
I
~
.....-OUTPUT
>~-
Rl
200 k
LOGIC
Notes
'Select for tome constant Cl
=
T
100 k
•• Adjust for amplitude
7-25
IL
Vs WHEN IN
HOLD MODE
(Vs + VCM)
WHEN IN
SAMPLE MODE
•
~A565
FAIRCHIL.O
Digital to Analog
Converter
A Schlumberger Company
Data Acquisition Products
Connection Diagram
24-Pin DIP
Description
The ItA565 is a fast 12-bit digital-to-analog converter
combined with a high stability voltage reference on a
single monolithic chip. The ItA565 chip uses 12
precision, high speed bipolar current steering
switches, control amplifier, laser-trimmed thin film
resistor network, and buried zener voltage reference
to produce a high accuracy analog output current.
24
The internal buried zener reference is laser-trimmed to
10.00 V with a ± 1% maximum error. The reference
voltage is available externally and can supply up to
1.5 mA beyond that required for the reference and
bipolar offset resistors.
•
•
•
NC
BIT21N
Vcc(+15V)
BIT31N
REFOUT(+10V ±1%)
BIT4IN
ANALOG COM
BIT51N
/LA565
BIT61N
VEE (-15V)
BIT7IN
BIPOLAR OFFSET IN
BlT81N
DAC OOT(-2 mA F.s.)
BIT91N
10VSPAN R
BIT lOIN
20 V SPAN R
BITlllN
DIGITAL COM
The ItA565 is available in four performance grades.
The ItA565J and K are specified for use over the 0 to
70°C temperature range and the ItA565S ancl T .
grades are specified for the -55 to + 125"C range.
•
•
BITl (MSB) IN
REFERENCE IN
The chip also contains additional SiCr thin film
resistors which can be used either with an external op
amp to provide a precision voltage output or as input
resistors for a successive approximation A / D
converter. The resistors are matched to the internal
ladder network to guarantee a low gain temperature
coefficient and are laser-trimmed for minimum full
scale and bipolar offset errors.
•
•
NC
BIT 12 (LSB) IN
(Top View)
Order Information
Type
Package
ItA565J Ceramic (Side
ItA565K Ceramic (Side
ItA565S Ceramic (Side
ItA565T Ceramic (Side
SINGLE CHIP CONSTRUCTION
VERY HIGH SPEED, SETTLES TO 1 12 LSB
in 200 ns
FULL SCALE SWITCHING TIME-30 ns
HIGH STABILITY BURIED ZENER REFERENCE
ON CHIP
MONOTONICITY GUARANTEED OVER
TEMPERATURE
LINEARITY GUARANTEED OVER
TEMPERATURE-1I2 LSB MAX (ItA565K, T)
LOW POWER, 225 mW INCLUDING REFERENCE
7-26
Brazed)
Brazed)
Brazed)
Brazed)
Code
7R
7R
7R
7R
Part No_
ItA565JJC
ItA565KJC
ItA565SJM
ItA565TJM
,uAS6S
Absolute Maximum Ratings
Vee to Digital Common
VEE to Digital Common
Analog Common to Digital
Common
Voltage on DAC Output (Pin 9)
Digital Inputs (Pins 13 to 24) to
Digital Com
Ref In to Analog Common
Bipolar Offset to Analog Common
10 V Span R to Analog Common
20 V Span R to Analog Common
± 12 V
Ref Out
Indefinite short to either Common
Momentary Short to Vee
Power Dissipation
1000 mW
Operating Temperature: J, K
O°C to +70°C
S, T
-55°C to +125°C
Storage Temperature
-65°C to +150°C
Pin Temperature (Soldering)
Ceramic DIP (60 s)
300°C
Oto+18V
Oto-18V
±1V
-3 to +12 V
-1.0
± 12
± 12
± 12
to +7.0 V
V
V
V
Block Diagram
Vee
REF OUT
4
BIPOLAR OFFSET
3
8
I'A565
10 V
9.95 k
.-_-+1;.;.1_
20 V SPAN
5k
~_--f..:.10,,--
19.95 k
DAC
ANA
-
10
.--=+-_-+..JVVv---i
lOUT = 4 x IREF x CODE
COM
5k
9
DAC
8k
12
DIG
VEE
COM
MSB
- - - - - - - - - _ _ LSB
INPUT BITS 1 - 12
Internal Simplified Schematic
7·27
10 V SPAN
OUT
•
~A565
~A565
Electrical Characteristics
Vee = +15 V , VEE = -15 V TA = +25°C , unless otherwise specified
Characteristic
Condition
~A565J,
Data Input
Voltage
Data Input
Current
Bit ON
Logic "1"
Min
S (Note 1)
Typ
+2.0
Bit OFF
Logic "0"
+5.5
+2.0
T (Note 1)
Typ
Max
Units
+5.5
V
+0.8
V
Bit ON
Logic "1"
+120
+260
+120
+260
~A
Bit OFF
Logic "0"
+35
+75
+35
+75
~A
12
Bits
Unipolar
All bits on
-1.6
-2.0
-2.4
12
-1.6
-2.0
-2.4
rnA
Bipolar
All bits on or off
±0.8
± 1.0
± 1.2
±0.8
± 1.0
± 1.2
rnA
6
8
10
6
8
10
kfl
0.01
0.05
0.01
0.02
% of F.S.
0.05
0.15
0.05
0.1
Output Resistance
(exclusive of span resistors)
Output Offset
Min
+0.8
Resolution
Output Current
~A565K,
Max
Unipolar
Bipolar
R2 = 50 fl fixed (Note 1)
25
Output Capacitance
Output Compliance Voltage
Imin to Imax
-1.5
+10
±%
±'h
(0.006) (0.012)
Accuracy (error relative to
full scale)
±l-2
Tmin to Tmax
Tmin to Tmax
±%
(0.012) (0.018)
±l-2
Differential Nonlinearity
25
±%
Monotonicity
Guaranteed
-1.5
±J.a
% of F.S.
pF
+10
V
±%
LSB
(0.003) (0.006) % of F.S.
±%
±l-2
LSB
(0.006) (0.012) % of F.S.
±%
±l-2
LSB
Monotonicity
Guaranteed
Temperature Coefficient of
Unipolar Zero
Tmin to Tmax
1
2
1
2
ppm! °C
Temperature Coefficient of
Bipolar Zero
Tmin to Tmax
5
10
5
10
ppm! °C
Temperature Coefficient of
Gain (Full Scale)
Tmin to Tmax
15
30
10
20
ppm! °C
Temperature Coefficient of
Differential Nonlinearity
Tmin to Tmax
2
Settling Time to l-2 LSB
All Bits ON-to-OFF
or OFF-to-ON
200
Note
1. Imin and 1m ax are -55°C and 125°C for I'A565S and I'A565T.
1m," and Imax are O°C and 70°C for I'A565J and I'A565K.
7-28
2
400
200
ppm! °C
400
ns
JLA565
Typical Performance Curve
used, excellent performance can be obtained in many
situations without trimming (an op amp with less than
0.5 mV max offset voltage should be used to keep
offset errors below 1-2 LSB). If a 50 n fixed resistor is
substituted for the 100 n trimmer, unipolar zero will
typically be within ± 1-2 LSB (plus op amp offset), and
full scale accuracy will be within 0.1 % (0.25% max).
Substituting a 50 n resistor for the 100 n bipolar offset
trimmer will give a bipolar zero error typically within
± 2 LSB (0.05%).
Typical Negative Compliance
Range vs. Negative Supply
J
IOUT-OmA/
The /.LA 771 is recommended for buffered voltage
output applications which require a settling time to
± 1-2 LSB of two microseconds. The feedback
capacitor is shown with the optimum value for each
application; this capacitor is required to compensate
for the 25 pF DAC output capacitance.
'y/
KUT=-2mA
Typical Applications
This unipolar configuration (Figure 1) will provide a
unipolar 0 to + 10 V output range. In this mode, the
bipolar terminal, pin 8, should be grounded if not used
for trimming.
Buffered Voltage
The standard current-to-voltage conversion
connections using an operational amplifier are shown
in Fig. 1 with the preferred trimming techniques. If a
low offset operational amplifier (/.LA714L, /.LA725A) is
Step I, Zero Adjust
Turn all bits OFF and adjust zero trimmer, R 1, until the
output reads 0.000 volts (1 LSB
2.44 mY). In most
cases this trim is not needed, but pin 8 should then be
connected to pin 5.
16.5V
13.5V
NEGAnVE SUPPLY - VEE
Fig_ 1
=
0 to +10 V Unipolar Voltage Output
+15V
100 kll
R1
50kll
+15V
100ll
vee
REF OUT
BIPOLAR OFF
4
R2
100n
3
8
10V
/LAS6S
-15V
-=
11
9.95k
20VSPAN
-=
5k
10
10 V SPAN
Sk
DAC
ANA
COM
lOUT
~
'0
= 4 x IREF x CODE
8k
2.4kll
CODE INPUT
7
VEE
-15V
·DIG
COM
12
24 -
-
-
-
-
-
-
-
-
13
MSB ------------------~.~ ~B
• DIgItal and analog common must have a common current return path.
See tYPIcal applicatIons continued for proper connections.
7-29
9
DAC
OUT
p,A565
Typical Applications (Cont.)
provided at the 20 V span R terminal, pin 11. For a 5 V
span (0 to +5 or ± 2.5), the two 5 k resistors are used
in parallel by shorting pin 11 to pin 9 and connecting
pin 10 to the op amp output and the bipolar offset
either to ground for unipolar or to REF OUT for the
bipolar range. For the ± 10 V range (20 V span) use
the 5 k resistors in series by connecting only pin 11 to
the op amp output and the bipolar offset connected as
shown. The ± 10 V option is shown in Figure 3.
Step II, Gain Adjust
Turn all bits ON and adjust 100 Q gain trimmer, R2,
until the output is 9.9976 V. (Full scale is adjusted to
1 LSB less than nominal full scale of 10.000 V.) If a
10.2375 V full scale is desired (exactly 2.5 mV / bit),
insert a 120 Q resistor in series with the gain resistor
at pin 10 to the op amp output.
Figure 2, bipolar configuration, will provide a bipolar
output voltage from -5.000 to +4.9976 V, with
positive full scale occurring with all bits ON (all" 1"s).
Internal/External Reference Use
The !lA565 has an internal low-noise buried zener
diode reference which is trimmed for absolute
accuracy and temperature coefficient. This reference
is buffered and optimized for use in a high speed DAC
and will give long-term stability equal or superior to
the best discrete zener reference diodes. The
performance of the !lA565 is specified with the
internal reference driving the DAC since all trimming
and testing (especially for full scale and bipolar) are
done in this configuration.
Step I, Offset Adjust
Turn OFF all bits. Adjust 100 Q trimmer R 1, to give
-5.000 V output
Step II, Gain Adjust
Turn ON all bits, adjust 100 Q gain trimmer to give a
reading of +4.9976 V.
Please note that it is not necessary to trim the op amp
to obtain full accuracy at room temperature. In most
bipolar situations, an op amp trim is unnecessary
unless the untrimmed offset drift of the op amp
is excessive.
The !lA565 can be used with an external reference,
but may not have sufficient trim range to
accommodate a reference which does not match the
internal reference.
The internal reference has sufficient buffering to drive
external circuitry in addition to the reference currents
required for the DAC (typically 0.5 mA to REF IN and
1.0 mA to BIPOLAR OFFSET IN, if used). A minimum of
The !lA565 can also be easily configured for a unipolar
o to +5 V range or ± 2.5 V and ± 10 V bipolar ranges
by using the additional 5 k application resistor
Fig_ 2
±5
V Bipolar Voltage Output
R1
100 n
+15 V
REF OUT
vee
4
BIPOLAR OFF
3
8
R2
100
n
10V
/LA565
9.95 k
.-_--t.;.;11--, 20 V SPAN
-=-
5k
10
19.95 k
REFIN
5k
DAC
ANA
COM
10 V SPAN
0.5 mA
-
10
,....::.5+--~_....."""1v-_-t
lOUT
=
4
x IREF x CODE
9
8k
DAC
OUT
1---4
2.4 kl!
7
VeE
-15 V
'DIG
12
COM
MSB
- - - - - - - - - _ . LSB
• Digital and analog common must have a common current return path
See typical applications continued for proper connections
7-30
~A565
can be separated by up to 200 mV without any loss in
performance. There may be some loss in linearity
beyond that level. Up to ± 1 V can be tolerated
between the ground lines without damage to the
device. If the /LA565 is to be used in a system in which
the two grounds will be ultimately connected at some
distance from the device, it is recommended that
parallel back-to-back diodes be connected between
the ground lines near the device to prevent a
fault condition.
Typical Applications (Cont.)
1.5 mA is available for driving external circuits. The
reference is typically trimmed to ± 0.2%, then tested
and guaranteed to ± 1.0% max error. The temperature
coefficient is comparable to that of the full scale TC
for a particular grade.
Digital Input Considerations
The /LA565 uses a standard positive true straight
binary code for unipolar outputs (all "l"s give full
scale output), and an offset binary code for bipolar
output ranges. In the bipolar mode, with all "O"s on the
inputs, the output will go to negative full scale; with
100 ... 00 (only the MSB on), the output will be 0.00 V;
with all "l"s, the output will go to positive full scale.
The analog common at pin 5 is the ground reference
point for the internal reference and is thus the "high
quality" ground for the /LA565: it should be connected
directly to the analog reference point of the system.
The digital common at pin 12 can be connected to the
most convenient ground reference pOint; analog power
return is preferred, but digital ground is acceptable. If
digital common contains high frequency noise beyond
200 mV, this noise may feed through the converter, so
that some caution will be required in applying
these grounds.
The threshold of the digital input circuitry is set at
1.4 V and does not vary with supply voltage. The input
lines can interface with any type of 5 V logic, TTLlDTL
or CMOS, and hl\ve sufficiently low input currents to
interface easily with unbuffered CMOS logic. The
configuration of the input circuit is shown in Figure 4.
The input line can be modelled as a 30 kO resistance
connected to -0.7 V rail.
Output Voltage Compliance
The /LA565 has a typical output compliance range from
-2 to +10 V. The current-steering output stages will
be unaffected by changes in the output terminal
voltage over that range. However, there is an
equivalent output impedance of 8 k in parallel with
25 pF at the output terminal which produces an
Application of Analog and Digital Commons
The /LA565 brings out separate analog and digital
grounds to allow optimum connections for low noise
and high speed performance. The two ground lines
Fig. 3
± 10 V Bipolar Voltage Output
A1
+15V
Vcc
3
4
100n
BlPOLAAOFF
8
A2
100n
p.A565
10V
11
9.95k
20VSPAN
5k
t-_-t...;10,- 10 V sPAN
5k
9
DAC
DAC
OUT
lOUT
= 4" IREF )( CODE
1---.1
CODE INPUT
7
VEe
-15V
'DIG
COM
12
LSB
MSB
'DIgital and analog common must have a common current return path.
See typical applications continued for proper connections.
7·31
JLA565
Fig. 4
Typical Applications (Cont.)
equivalent error current if the voltage deviates from
analog common. This is a linear effect which does not
change with input code. Operation beyond the
compliance limits may cause either output stage
saturation or breakdown which results in nonlinear
performance. Compliance limits are not affected by
the positive power supply. but are a function of output
current and negative supply. as shown in the Typical
Performance Curve.
Equivalent Digital Input Circuit
DIGITAL
INPUTS
(PlNS13T024)
I
DIGITAL
COM
7·32
I
5PF
-=-
1
30kfl
"",-O.7V
L-.._ _ _
""
TO LOGIC
JlA571
Analog to Digital
Converter
FAIRCHIL.O
A Schlumberger Company
Data Acquisition Products
Description
The /lA571 is a 10-bit successive approximation A / 0
converter consisting of a DAC, voltage reference,
clock, comparator, successive approximation register
and output buffers-all fabricated on a single chip. No
external components are required to perform a full
accuracy 10-bit conversion in 25 /ls.
Connection Diagram
18-Pin DIP
BIT 8
BIT 7
The device offers true 10-bit accuracy and exhibits no
missing codes over its entire operating temperature
range.
BIT 6
BIT 5
BIT 4
Operation is guaranteed with -15 V and +5 V to
+ 15 V supplies. The device will also operate with
a -12 V supply.
BIT 3
BIT 2
Operating on supplies of +5 V to ± 15 V, the /lA571
will accept analog inputs of 0 to +10 V, unipolar or
± 5 V bipolar, externally selectable. As the BLANK and
CONVERT input is driven LOW, the 3-state outputs will
be open and a conversion starts. Upon completion of
the conversion, the DATA READY line will go LOW and
the data will appear at the output. Pulling the BLANK
and CONVERT input HIGH blanks the outputs and
readies the device for the next conversion. The j.lA571
executes a true 10-bit conversion with no missing'
codes in approximately 25 /ls.
.
MS13 BIT 1
(Top VIew)
Order Information
Type
Package
/lA571 J
Ceramic DIP
j.tA571K
Ceramic DIP
/lA571 S
Ceramic DIP
The j.tA571 is available in two versions for the 0 to
+70°C temperature range, the /lA571J and K. The
/lA571 S guarantees 10-bit accuracy and no missing
codes from -55°C to +125°C. All three grades are
packaged in an 18-pin ceramic DIP.
•
•
•
•
•
•
V+
COMPLETE AID CONVERTER WITH REFERENCE
AND CLOCK
FAST SUCCESSIVE APPROXIMATION
CONVERSION-25/ls
NO MISSING CODES OVER TEMPERATURE
DIGITAL MULTIPLEXING-3-STATE OUTPUTS
18-PIN CERAMIC DIP
LOW COST MONOLITHIC CONSTRUCTION
7-33
Code
FD
FD
FD
Part No.
/lA571JJC
/lA571KJC
j.tA571SJD
J.LA571
Absolute Maximum Ratings
V+ to Digital Common
V- to Digital Common
Analog Common to Digital
Common
Analog Input to Analog Common
Control Inputs
Digital Outputs (Blank Mode)
o to + 7 V
o to -16.5 V
Power Dissipation
Operating Temperature
Storage Temperature
Pin Temperature (Soldering)
Ceramic DIP (60 s)
±lV
± 15 V
o to V+
Oto V+
800mW
O°C to +70°C
-55°C to +125°C
300°C
Block Diagram
V-
I
I
10
12
DIGITAL
COMMON
BLANK &
CONVERT CONTROL
I
I
16
111
B
ANALOG IN
13
+ C
9
r--
5k
L
L
.....
L
......
.....
I---
f-14
ANALOG
COMMON
#-14-
r0--
-
BIPOLAR
OFFSET
CONTROL
-
+
10 BIT
CURRENT
OUTPUT
DAC
-
COMPARATOR
-
15
---
-----
----
"A571
I
L
......
L
10 BIT
SAR
r-----..,
I
I
I
INT
I
CLOCK
I
I
L _____ J
7·34
8
7
6
5
DATA
OUTPUTS
4
L
L
.....
3
2
L
.....
TEMPERATURE COMPENSATED
BURIED ZENER REFERENCE
AND DAC CONTROL
MSB
t
I
L
.....
L
3 STATE
BUFFERS
17
1
18
LSB
p,A571
J.LA571
Electrical Characteristics
V+ = +5 V, V- = -15 V, TA = +25°C, all voltages measured with respect to digital
common unless otherwise specified
Characteristic
Resolution
J.LA571JJC
Typ
Min
Condition
Max
J.LA571KJC
Typ
Min
Max
Units
Bits
±1
±Y2
LSB
±1
±Y2
LSB
10
Relative Accuracy (Note 1)
Tmin to Tmax
Full Scale Calibration (Note 2) With 15 Q Resistor in Series
with Analog Input
10
±2
±2
LSB
LSB
Unipolar Offset
±1
±Y2
Bipolar Offset
±1
±Y2
LSB
10
Bits
10
Differential Nonlinearity
(Note 3)
10
9
Tmin to Tmax
Temperature Coefficient of
Unipolar Offset
Tmin to Tmax
Temperature Coefficient of
Bipolar Offset
Tmin to Tmax
Temperature Coefficient of
Full Scale Calibration
Tmin to Tmax with 15 Q
Resistor or 50 Q Trimmer
CMOS Pos. Supply ± 13.5 V :s V+ :s +16.5 V
Power
Supply
TTL Pos. Supply
+4.5 V :s V+ :s 5.5 V
Rejection Negative Supply
-16.5 V :s V+ :s -13.5 V
±1
44
22
±2
±1
44
22
LSB
ppm/oC
LSB
ppm/oC
±4
±2
88
44
LSB
ppm/oC
±1
LSB
±2
±1
LSB
±2
±1
7
LSB
kQ
Analog Input Resistance
3
Analog
Input
Ranges
Unipolar
Bipolar
Unipolar
Positive True
Binary
Positive True
Binary
Bipolar
Positive True
Offset Binary
Positive True
Offset Binary
3.2
3.2
rnA
0.5
0.5
rnA
Output
Coding
= 0.4 V max, Tmin to Tmax
Output Sink Current
VOUT
Output Source Current
(Bit Outputs) (Note 4)
VOUT = 2.4 V min, Tmin to Tmax
5
Bits
±2
7
3
0
10
0
10
V
-5
+5
-5
+5
V
Output Leakage When
Blanked
±40
o :s VIN :s
Blank & Convert Input
±40 J.LA
40
V+
Blank-Logic "1"
2.0
40
2.0
Convert-Logic "0"
15
+4.5
-12
IV+
Iv-
Notes
1. Relative accuracy is defined as the deviation of the code
transition points from the Ideal transfer point on a straight line
from zero to the full scale of the device.
2. Full scale calibration is guaranteed trimmable to zero with an
external 50 f! potentiometer 10 place of the 15 f! fixed resistor.
Full scale IS defined as 10 V minus 1 LSB, or 9.990 V.
25
30
15
+5.5 +4.5
-16.5 -12
J.LA
V
0.8
Conversion Time
Operating Range
5
25
0.8
V
30
J.LS
+16.5 V
-16.5 V
3. Info commg.
4. The data output lines have active pull· ups to source 0.5 rnA.
The DATA READY line IS open collector with a nominal 6 kf!
mternal pull·up resistor.
7·35
J.LA571
/LA571
Electrical Characteristics (Cont.)
V+ = +5 V, V- = -15 V, TA = +25°C, all voltages measured with respect to
digital common, unless otherwise specified
/LA571KDC
/LA571JDC
Typ
Max
V+ = +5 V
2
10
V+ = +15V
5
V-=-15V
9
V+ = +5 V
5
Condition
Characteristic
Operating Current-Blank
Mode
Operating Current-Convert
Mode
/LA571
Electrical Characteristics
Min
Typ
Max
Units
2
10
mA
10
5
10
mA
15
9
15
mA
Min
5
mA
V+ = +15 V
10
10
mA
V- = -15 V
10
10
mA
V+ = +5 V, V- = -15 V, TA = +25°C, all voltages measured with respect to digital
common, unless otherwise specified
/LA571SDM
Characteristic
Condition
Min
Resolution
Typ
Max
10
Relative Accuracy (Note 1)
Full Scale Calibration (Note 2)
T min to Tmax
With 15 Q Resistor in
Series with Analog Input
Units
Bits
±1
LSB
±1
LSB
±2
LSB
Unipolar Offset
±1
LSB
Bipolar Offset
±1
LSB
Differential Nonlinearity (Note 3)
10
Tmin to Tmax
Temperature Coefficient of
Bipolar Offset
Tmin to Tmax
Temperature Coefficient of
Full Scale Calibration
Tmin to Tmax, with 15 Q Fixed
Resistor or 50 Q Trimmer
20
±2
20
Output Coding
±5
LSB
ppm/oC
LSB
ppm/oC
50
LSB
ppm/oC
TTL Pos. Supply +4.5 V ::; V+ ::; 5.5 V
±2
LSB
Neg. Supply
±2
7
LSB
kQ
10
±5
V
V
-16.5 V::; V+ ::; -13.5 V
Analog Input Resistance
Analog Input
Ranges
Bits
±2
Temperature Coefficient of
Unipolar Offset
Power Supply
Rejection
Bits
10
Tmin to Tmax
3
5
Unipolar
Bipolar
0
-5
Unipolar
Positive True Binary
Bipolar
Positive True Offset
Binary
Output Sink Current
VOUT = 0.4 V max, Tmin to Tmax
3.2
mA
Output Source Current (Bit Outputs)
(Note 4)
VOUT = 2.4 V min, Tmin to Tmax
0.5
mA
Notes
1. Relative accuracy is defined as the deviation of the code
transition pomts from the Ideal transfer pOint on a straight line
from zero to the full scale of the device.
2. Full scale calibration is guaranteed tnmmable to zero with an
external 50 G potentiometer m place of the 15 n fixed resistor.
Full scale is defined as 10 V minus 1 LSB, or 9.990 V.
3. Info coming.
4. The data output lines have active pull-ups to source 0.5 mAo
The DATA READY line is open collector with a nominal 6 kG
mternal pull-up resistor.
7-36
IlA571
ttA571
Electrical Characteristics (Cont.)
V+ = +5 V, V- = -15 V, TA = +25°C, all voltages measured with respect to
digital common, unless otherwise specified
ttA571SDM
Characteristic
Condition
Min
Typ
Max
Unit
Output Leakage When Blanked
±40
Blank & Convert Input
±40
tt A
tt A
V
V
Blank-Logic" 1"
2.0
Convert-Logic "0"
0.8
15
Conversion Time
Operating Range
+4.5
IV+
Iv-
Operating Current-Convert Mode
30
+5.5
-16.5
-12
Operating Current-Blank Mode
V+ = +5 V
2
10
V+ = +15V
V- = -15V
5
10
9
15
V+ = +5 V
5
V+=+15V
10
V-=-15V
10
Typical Applications
tt S
V
V
mA
mA
mA
mA
mA
mA
inserted in series with the input signal, the input
current at the full scale input voltage can be trimmed
down to match the DAC full scale current as precisely
as desired. However, for many applications the
nominal 9.99 V full scale can be achieved to sufficient
accuracy by simply inserting a 15 Q resistor in series
with the analog input to pin 13. Typical full scale
calibration error will then be about ± 2 LSB or ± 0.2%.
If the more precise calibration is desired, a 50 Q
trimmer should be used instead. Set the analog input
at 9.990 V, and set ther trimmer so that the output
code is just at the transition between 1111111110 and
1111111111. Each LSB will then have a weight of
9.766 mY. If a nominal full scale of 10.24 V is desired
(which makes the LSB exactly 10.00 mY), a 100 Q
resistor in series with a 100 Q trimmer (or a 200 Q
trimmer with good resolution) should be used. Of
course, larger full scale ranges can be arranged by
using a larger input resistor, but linearity and full
Standard ttA571 Operation
The ttA571 contains all the active components
required to perform a complete AID conversion. For
most situations, all that is necessary is connection of
the power supply (+5 and -15), the analog input, and
the conversion start pulse. But, there are some
features and special connections which should be
considered for achieving optimum performance. The
functional pin-out is shown in the connection diagram.
Full Scale Calibration
The 5 kQ thin film input resistor is laser trimmed to
produce a current which matches the full scale current
of the internal DAC-plus about 0.3%-when a full
scale analog input voltage of 9.990 V (10 V-l LSB)
is applied at the input. The input resistor is trimmed in
this way so that if a fine trimming potentiometer is
Fig_ 1
25
Standard ttA571 Connections
18
DIGITAL COM
SHORT TO COMMON)
BIPOLAR ( FOR UNIPOLAR,
CONTROL
OPEN FOR BIPOLAR
ANALOG COM (TOLERATES 200mV)
TO DIGITAL COM
~----~~--r--o~ANALOGIN
RIN
150 FIXED OR
50 n VARIABLE
(SEE TEXT)
MSB
(Top View)
7-37
JLA571
Typical Applications (Cont.)
In normal operation the Analog Common terminal may
generate transient currents of up to 2 mA during a
conversion. In addition, a static current of about 2 mA
will flow into Analog Common in the unipolar mode
after a conversion is complete. An additional 1 mA will
flow in during a blank interval with zero analog input.
The Analog Common current will be modulated by the
variations in input signal.
scale temperature coefficient may be compromised if
the external resistor becomes a sizeable percentage
of 5 kQ.
Bipolar Operation
The standard unipolar 0 to + 10 V range is obtained by
shorting the bipolar offset control pin to digital
common. If the pin is left open, the bipolar offset
current will be switched into the comparator summing
node, giving a -5 V to +5 V range with an offset
binary output code. (-5.00 V in will give a 10-bit code
of 0000000000; an input of 0.00 V results in an output
code of 1000000000 and 4.99 V at the input yields the
1111111111 code). The bipolar offset control input is
not directly TTL compatible, but a TTL interface for
logic control can be constructed as shown in Figure 2.
The absolute maximum voltage rating between the two
commons is ± 1 V. We recommend the connection of a
parallel pair of back-to-back protection diodes between the commons if they are not connected locally.
Zero Offset
The apparent zero point of the /-lA571 can be adjusted
by inserting an offset voltage between the Analog
Common of the device and the actual signal return or
signal common. Figure 3 illustrates two methods of
providing this offset. Figure 3A shows how the
converter zero may be offset by up to ± 3 bits to
correct the device initial offset and / or input signal
offsets. As shown, the circuit gives approximately
symmetrical adjustment in unipolar mode. In
bipolar mode R2 should be omitted to obtain a
symmetrical range.
Common Mode Range
The /-lA571 provides separate Analog and Digital
Common connections. The circuit will operate properly
with as much as ± 200 mV of common mode range
between the two commons. This permits more flexible
control of system common bussing and digital and
analog returns.
Fig. 2
Bipolar Offset Controlled by Logic Gate
+5V
B +
C
DRt----!
AIN
AeOM
I
I
BIPOLAR
OFFSET
CONTROL
I
I
TTL
GATE
~A571
5 VCOM:
10 BITS
I
I
DATA
\
\
DeoM
15 V COM
30 k
Q
-15 V
Gate Output = 1 Unipolar 0-10 V Input
Range Gate Ouput = 0 Bipolar ± 5 V Input Range
7-38
JLA571
Typical Applications (Cont.)
Fig. 3a
Zero Offset ADJ ± 3-Bit Range
Fig. 3b
AIN
~
INPUT
'"\., SIGNAL
JI2-Bit Zero Offset
AIN
~
"A571
I,A571
INPUT
'"\., SIGNAL
ACOM
ACOM
R1
R1
10 Q
R2
7.5 k
R3
4.7 k
I
R4
10k
+ 15 V
I
-15V
Note
DUring a conversion. transient currents from the Analog Common
terminal will disturb the offset voltage. Capacitive decoupling
should not be used around the offset network. These transients
Will settle as appropriate during a conversion. Capacitive
Fig.4
COMMON
SIGNAL
S IGNAL COMMON
2.7H
OR 511
POT
decoupling will "pump up" and fall to settle resulting In converSion
errors. Power supply decoupling which returns to analog signal
common should go to the signal Input side of the resistive
offset network.
ILA571 Transfer Curve-Unipolar Operation (Approximate Bit Weights Shown for Illustration,
Nominal Bit Weights - 9.766 mY)
Offset Characteristics with 2.7 in series with
Analog Common
Nominal Characteristics referred to
Analog Common
r-----
.-I
I
I
I
0000000100
-
0000000011
c-
=> 0000000010
f-
0000000001
l-
0000000100 f-
UJ
c
0
UJ
c
000000001 1'-
0
0
0
....
....
=>
=>
II.
....=>
•
I
I
II.
....
0000000010 I -
0
0
000000000 11-
0000000000
I
oV
10 mV
I
30mV
I
I
OOOOOOOOOOOV
50mV
INPUT VOLTAGE
I
10mV
I
I
30mV
I
I
50mV
INPUT VOLTAGE
the transfer characteristics. The nominal 2 rnA Analog
Common current is not closely controlled in
manufacture. If high accuracy is required, a 5 11
potentiometer (connected as a rheostat) can be used
as R2. Additional negative offset range may be
obtained by using larger values of R2. Of course, if the
zero transition pOint is changed, the full scale
transition point will also move. Thus, if an offset of
Jl2LSB is introduced, full scale trimming as described
on previous page should be done with an analog input
of 9.985 V.
Figure 4 shows the nominal transfer curve near zero
for a ILA571 in unipolar mode. The code transitions are
at the edges of the nominal bit weights. In some
applications it will be preferable to offset the code
transitions so that they fall between the nominal bit
weights, as shown in the offset characteristics. This
offset can easily be accomplished as shown in
Figure 38. At balance (after a conversion)
approximately 2 rnA flows into the Analog Common
terminal. A 2.7 11 resistor in series with this terminal
will result in approximately the desired JI2 bit offset of
7·39
JLA571
allows the device to be easily operated in a variety of
systems with differing control modes. The two most
common control modes, the Convert Pulse Mode, and
the Multiplex Mode, are illustrated here.
Typical Applications (Cont.)
Control and Timing of the #A571
There are several important timing and control
features on the #A571 which must be understood
precisely to allow optimum interface to
microprocessor or other types of control systems. All
of these features are shown in the timing diagram in
Figure 5.
Convert Pulse Mode
In this mode, data is present at the output of the
converter at all times except when conversion is
taking place. Figure 6 illustrates the timing of this
mode. The BLANK and CONVERT line is normally LOW
and conversions are triggered by a positive pulse.
The normal stand-by situation is shown at the left end
of the drawing. The BLANK and CONVERT (B & C) line
is held HIGH, the output lines will be "open", and the
DATA READY (DR) line will be HIGH. This mode is the
lowest power state of the device (typically 150 mW).
When the B & C line is br2.!!9ht LOW, the conversion
cycle is initiated; but the DR and data lines do not
change state. When the conversion cycle is complete
(typically 25 #s), the DR line goes LOW, and within
500 ns, the data lines become active with the
new data.
Multiplex Mode
In this mode the outputs are blanked except when the
device is selected for conversion and readout; this
timing shown in Figure 7.
This operating mode allows multiple #A571 devices to
drive common data lines. All BLANK and CONVERT
lines are held HIGH to keep the outputs blanked. A
single #A571 is selected, its BLANK and CONVERT
line is driven LOW and at the end of conversion, which
is indicated by DATA READY going LOW, the
conversion result will be present at the outputs. When
this data has been read from the 10-bit bus, BLANK
and CONVERT is restored to the blank mode to clear
the data bus for other converters. When several
#A571's are multiplexed in sequence, a new
conversion may be started in one #A571 while data is
being read from another. As long as the data is read
and the first #A571 is cleared within 15 #s after the
start of conversion of the second #A571, no data
overlap will occur.
About 1.5 ~ after the B & C line is again brought
HIGH, the DR line will go HIGH and the data lines will
go open. When the B & C line is again brought LOW, a
new conversion will begin. The minimum pulse width
for the B & C line to blank previous data and start a
new conversion is 2 #s. If the B & C line is brought
HIGH du~ a conversion, the conversion will stop,
and the DR and data lines will not change. If a 2 #s or
longer pulse is applied to the B & C line during a
conversion, the converter will clear and start a new
conversion cycle.
Control Modes with BLANK and CONVERT
The timing sequence of the #A571 discussed above
Fig.5
#A571 Timing and Control Sequence
PULSE BLANKS
DATA OUTPUTS
ON RISING EDGE
AND STARTS
CONVERSION
ON FALLING EDGE
BLANKS DATA
OUTPUTS
BlK (CONV.)
INPUT
START-..
--~-J-!
CONVERSION ....
CONVERSION
TIME
DAT~~iADY
~
5oon5-1
(max)
DATA
OUT
1\ \
FU
11.5~S
INDICATES
DATA READY
NEW DATA READY
~~
BLANK
(OPEN)
ONE
OR
ZERO
7·40
BLANK
(OPEN)
ONE
OR
ZERO
BLANK
(OPEN)
,uA571
Typical Applications (Cont.)
Fig. 6
Convert Pulse Mode
CONVERSION
BlK (CONV.) _ _ _ _
~rtlSE
CONVERSION
INTERVAL
/'
OUTPUTS
Fig. 7
~'''YYm.___
PREVIOUS
__
D_AT_A__
BLANK
(~~E,,~~
NEW
....;D.;.A;..T,;.;A~_ _ __
Multiplex Mode
CONVERSION
STARTS
1/
CONVERSION
ENDS
r/
OUTPUTS
7·41
FENDDATA
READOUT
p,A0801 (DAC-08) Series
8-Bit Multiplying 0/ A
Converters
I=AIRCHILO
A Schlumberger Company
Data Aquisition Products
Description
The !LA0801, !LA0801E and !LA0801C are 8-bit
multiplying Digital-to-Analog Converters constructed
using the Fairchild Planar epitaxial process. Advanced
circuit design achieves very high speed performance
with outstanding applications capability and low cost.
The !LA0801 is specified for the military temperature
range (-55 ° C to + 125 ° C) and the !LA080 1E and
!LA0801C are specified for O°C to +70°C operation.
The !LA0801 series are pin-for-pin replacements of the
DAC-08 and DAC0800 series.
Connection Diagram
16-Pin DIP
VLe
lOUT
Vee-
lOUT
(MS6) 61
62
• FAST SETTLING TIME TO 1/2 LSB 85 ns
• FULL SCALE CURRENT PRE MATCHED
TO ±1 LSB
• DIRECT INTERFACE TO TTL, CMOS, ECL, HTL,
PMOS,DTL
• LINEARITY TO ± 0.19% MAX OVER
TEMPERATURE RANGE
• HIGH OUTPUT COMPLIANCE -10 V TO +18 V
• TRUE AND COMPLEMENTED OUTPUTS
• WIDE RANGE MULTIPLYING CAPABILITY
• LOW FULL SCALE CURRENT DRIFT
+10 ppm/DC TYP
• WIDE POWER SUPPLY RANGE ± 4.5 V TO
±18V
• LOW POWER CONSUMPTION 33 mW @ ± 5 V
• EXTERNAL COMPENSATION FOR
MAX BANDWIDTH
• LOWCOST
63
64
(Top View)
Order Information
Type
Package
!LA0801
Ceramic DIP
!LA0801E
Ceramic DIP
!LA080 1E
Molded DIP
!LA080 1C
Ceramic DIP
!LA080 1C
Molded DIP
Code
68
68
98
68
98
Part No.
!LA0801DM
!LA0801EDC
!LA0801EPC
!LA0801CDC
!LA0801CPC
Equivalent Circuit and Pin
Connection Diagram
MS6
61
LS6
62
63
5
65
66
67
68
-
~~~__-r~__;-~__~__-+~__;-~-+.-__+-4
..--11--+.......-r-+-~++-~I-+~-+-+-......+-+-ri+-.-~2
VAEF( -)
15
16
3
COMPlvee-
7-42
lOUT
lOUT
JLA0801 SERIES
Absolute Maximum Ratings
Vee+ to Vce36 V
Logic Inputs
Vee- to Vee- plus 36 V
VLC
Vee- to Vee+
Reference Inputs
(V14, V15)
Vec- to Vee+
Reference Input
Differential Voltage
(V14toV15)
±18V
Reference Input
Current IREF (14)
5.0 mA
Power Dissipation
500 mW
Derate above 90°C
(Ceramic DIP)
8.3 mW/oC
Operating
Temperature Range
~A0801
~A0801E, ~A0801C
Storage Temperature
Range
Pin Temperature
Ceramic DIP,
(Soldering, 60 s)
Molded DIP
(Soldering, 10 s)
-55°C to +125°C
O°C to +70°C
-65°C to +150°C
300°C
260°C
Electrical Characteristics
These specifications apply for Vee = ± 15 V, IREF = 2.0 mA, TA = -55°C to +125°C for ~A0801,
TA = O°C to 70°C for ~A0801E, ~A0801C. Output characteristics refer to both lOUT and lOUT.
Symbol
ts
Min
Typ
Max
Unit
Resolution
8
8
8
bits
Monotonicity
8
8
8
bits
±0.19
±0.39
%FS
Characteristic
Condition
Non-linearity
~A0801,~A0801E
~A0801C
Settling Time
To ±M. LSB,
all bits
switched ON
or OFF
TA = 25°C
~A0801
~A0801E,~A0801C
85
150
Each bit
35
60
All bits switched
35
60
ns
ns
±10
±50
ppm/oC
+18
V
1.990
2.040
mA
~A0801,~A0801E
± 1.0
±8.0
~A0801C
±2.0
±16
~A0801,~A0801E
0.2
2.0
~A0801C
0.2
4.0
Propagation Delay
TCIFS
Full Scale Temperature
Coefficient
Voe
Output Voltage Compliance
Full scale current change
ROUT> 20 mSl
IFS4
Full Scale Current
VREF
= 10.000 V,
R14, R15
= 5.000 kSl
TA = 25°C
IFSS
Full Scale Symmetry
IFS4 -IFS2
IzS
Zero Scale Current
= 25°C
135
ns
tpLH,
tpHL
TA
85
< M. LSB, -10
~A0801E
~A080 1, ~A080 1C
7·43
1.940
~A
~A
JLA080 1 SERIES
Electrical Characteristics (Cont.)
These specifications apply for Vee = ± 15 V, IREF = 2.0 rnA, TA = -55°C to +125°C for ~A0801,
TA = O°C to 70°C for ~A0801E, ~A0801C. Output characteristics refer to both lOUT and lOUT.
Symbol
IFSR
Characteristic
Condition
Output Current Range
R14, 15 = 5.000 kO
VREF = +15.00 V, Vee- = -10 V
VREF = +25.0 V, Vee- = -12 V
Typ
Min
Max
Unit
2.1
rnA
4.2
rnA
0.8
V
V
-10
10
~A
~A
VIL
VIH
Logic Input LOW Voltage
Logic Input HIGH Voltage
VLe = 0 V
IlL
IIH
Logic Input LOW Current
Logic Input HIGH Current
VLe = 0 V, VIN = -10 V to +0.8 V
VIN = 2.0 V to 18 V
VIS
Logic Input Swing
Vee- = -15 V
-10
+18
V
VTHR
Logic Threshold Range
Vee = ± 15 V
-10
+13.5
V
115
dlldt
Reference Bias Current
-3.0
~A
2.0
-2.0
0.002
-1.0
Reference Input Slew Rate
8.0
4.0
rnA/~s
PSSIFS+ Power Supply Sensitivity
PSSIFS-
Vee+ = 4.5 V to 18 V
Vee- = -4.5 V to -18 V
IREF = 1.0 rnA
0.0003
0.002
0.01
0.01
1+
1-
Vee = ±5.0 V, IREF = 1.0 rnA
2.3
-4.3
3.8
-5.8
Vee+ = +5.0 V, Vee- = -15 V,
IREF = 2.0 rnA
2.4
-6.4
3.8
-7.8
Vee = ± 15 V, IREF = 2.0 rnA
2.5
-6.5
3.8
-7.8
Vee = ±5.0 V, IREF = 1.0 rnA
33
48
Vee+ = +5.0 V, Vee- = -15 V,
IREF = 2.0 rnA
108
136
Vee = ± 15 V, IREF = 2.0 rnA
135
174
1+
1-
Power Supply Current
1+
1-
Power Dissipation
Po
0f010f0
0f010f0
rnA
rnW
rnW
rnW
Typical Performance Curves
Full Scale Current as a
Function of Reference Current
5.
TAl '" T~IN 16 TMIAX
f-~
4.
ALL BITS "HIGH"
i 2.
V
~
,.
V
/
/
/
V
3.2
ICC-
LARGE SIGNAL ~
r-YIN '" 2 0 Vpk-pk
CENTERED AT +1 0 y
•
f-- f-~1
~1
2.0
30
40
REFERENCE CURRENT - mA
1
o I- ~1! = ~15 '" 1.0 kH
Rl:55OQU
ALL BITS MON"
50
4
01
02
1\
'I
1St
05
10
FREQUENCY -
20
MHz
2.4
O
~
1\
50
I
II
IREr-2~mA
I
12
IREF
.8
I
.4
10
I
Ycc- - -5.0 V
I ..
,
,\
vcJ~ ~ +j5 V
vcJ~ ~ -J5 V
..I 2.
\
I
I-VRi5~tVi C~
10
ALL BITS "ON"
28
./ \
/""\
VLlMITFOA
= -15 Y
I
TA = TMIN TO TMAX
~EN=T~~~~~;:P!200 mY -
1..1
I"'-UMIT FOR
iCC ~I ~5·IV
Reference AMP
Common Mode Range
SMALL SIGNAL
1'1 I
I
!i 3.
o
Reference Input
Frequency Response
10mA
I
IREF -O.2mA
•
-14
-10
-6
-2 0 2
&
10
Note
Positive common mode renge is
always (Vee-l +1.5V
7·44
14
18
Y15, REFERENCE COMMON MODE VOLTAGE - Y
~A080 1
SERIES
Typical Performance Curves (Cont.)
Output Current as a
Function of Output Voltage
(Output Voltage Compliance)
32
TA
>=
~
24
..~
"
.0
I
Vcc-
-15
vvcc~ =
I
vcr
-5.0 Y
~
0
1.
O.
-14
-10
-6
~
r--..
t--...
1.2
> ,.
I
w •0
~
r--...
~
~
IREF
D2mA
RANGE FOR Vcc- = 15 Y
IREF520mA
(FOR OTHER Vcc- OR 'REF,
SEE FIGURE 12)
0
0_ 4 •0
I
10
r- ~ERjl••'~LE ~U,.l,UT~OL+AG~_
4. 0
~
0
1.0mA
-2 0 2
,.
l •
IREF
I
04
o
+15Y
I
u
20
•
'REr=2imA
r
16
2.0
I
TMIN TO TMAX
ALL BITS "ON"
2.'
Output Voltage Compliance as a
Function of Temperature
VTH - VLcas a
Function of Temperature
04
14
18
o
-.
-50
150
100
50
TEMPERATURE _
OUTPUT VOLTAGE - V
0
0
-1 2
-50
50
c
100
150
TEMPERATURE _ °C
Note
Positive common mode range is
always (Vcc+l -1.5V
Bit Transfer
Characteristics
Power Supply Current as a
Function of VCC-
4
0
ALL BITS "HIGH" OR "LOW"
IRE; = .01mA
•
~
0
81
0
I
I•
•
u
~
!;
o
0
0
82
>
>
'I'
II
• >s- f--- +-8
84
'i
-40
0
83
II
o.
-1'
I I I
IR'i 'IOj
1-
I I I
t
IRE -1 0mj
I
0
I I I
,.
40
III
20
LOGIC INPUT VOLTAGE - V
-40
-8.0
...I
•.0
I-
Ycc- '" -15 V
'REF
~
50
"!:;
0
40
..~
30
I
1+
-1'
70r-~-r-+--r-t-~-t~--~
20mA
a:
1-
1
ALL BITS "HIGH" OR "LOW"
.
E
IREF - D2mA
0 4 ~- f--- 1--'"
0
Power Supply Current as a
Function of Temperature
-1.
Vcc- - NEGATIVE POWER SUPPLY - Vile
-20
Vcc+
=
+15 v
1+
.0
10
-50
50
100
150
TEMPERATURE _ °C
See Note below.
Power Supply Current as a
Function of VCC+
ALL BITS "HIGH" OR "LOW"
40
•0
.
,
18
Note
B 1 through B8 have identical transfer characteristics. Bits are
fully switched, with less than 1/2 LSB error. At less than ± 100
mV from actual threshold, these switching points are guaranteed
to lie between 0.8 and 2.0 V over the operating temperature range
(VLC = 0.0 V)
.0
Ycc+ - POSmVE POWER SUPPLY - Ydc
7·45
•
~A0801
SERIES
Test Circuits
Fig. 1
Settling Time Measurement
+5V
FOR TURN-ON, Vl = 2.7 V
FOR TURN-OFF, Vl = 0.7 V ...._ _.....,
VCl
0.7 V
15 k
RREF
+VREF
100 k
-15 V
TO D.U.T.
"A0801
R15
15
13
2
16
3
"":"
0.01"F"":"
0.1"F
0.1"F
-15 V
:t
J
+15 V
Typical Applications
Fig. 1
Basic Positive Aeference Operation
MSB
LSB
IFS "'"
B1 B2 B3 B4 B5 B6 B7 B8
-
+ iO = IFS
For all logic states
10
IREF
+VREF
+VREF
255
RREF X 256
VREF(')
5 6 7
89101112
14
RREF
(R14)
"A0801
VREF(-)
15 3
R15
16
0.1"F
t
10
iO
For fixed reference, TTL operation,
typical values are:
VREF
+10.000 V
RREF
6.000 k
R15"'" RREF
Cc = O.OlIlF
=
=
13
COMP
"":"
4
,2
Cc
VlC
0.1"F
VLC
"":"
Vcc-
Vcc,
7·46
=0 V (GROUND)
JLA080 1 SERIES
Typical Applications (Cont.)
Fig. 2
Recommended Full Scale Adjustment Circuit
Fig. 3
Basic Negative Reference Operation
LOW T.C.
4.5 k
RREF
-
IREFI-) ~ 2 mA
~1
R15
Y
<~--.---I15
-YREF ---'"","-115
APPROX
5k
'---.~
IFS "'"
-VREF
255
RREF X 256
Note
RREF sets IFS; R15 is for bias current cancellation.
Fig. 4
Basic Unipolar Negative Operation
MSB
LSB
B1 B2 B3 B4 B5 B6 B7 B8
4
IREF
~
2.000 mA
Eo
5.000 kll
10
-::-
MA0801
14
10
5.000kll
2
Eo
B1
B2
B3
B4
B5
B6
B7
B8
lornA
lornA
1
1
1
1
1
1
1
1
1
1
1
0
1.992
1.984
.000
.008
Eo
-9.960
-9.920
EO
1
1
1
1
0
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
1
0
1
1.008
1.000
.992
.984
.992
1.000
-5.040
-5.000
-4.960
-4.920
-4.960
-5.000
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
.008
.000
1.984
1.992
.040
.000
-9.920
-9.960
Full Scale
Full Scale - LSB
Half Scale + LSB
Half Scale
Half Scale - LSB
Zero Scale
Zero Scale
+ LSB
7·47
-
.000
.040
~A080 1 SERIES
Typical Applications (Cont.)
Fig. 5
High Noise Immunity Current To Voltage Conversion
B1 B2 B3 B4 B5 B6 B7 B8
5k
5k
+10 V -""V'''''''---f
10
">....- -
"A0801
Eo
10
VREFI-I
Vcc+
VLC
5k
5k
-=•
•
•
•
•
+15 V
-=-
-15 V
ECM
Provides isolation from ground loops
Symmetrical ± 10 V output
Useful within systems between boards
True complementary / differential current transmission
High speed analog signal transmission
81
Pos Full Scale
Pos Full Scale - LSB
82
83
84
1
1
1
1
1
1
(+) Zero Scale
(-) Zero Scale
1
0
0
1
0
1
0
1
Neg Full Scale + LSB
Neg Full Scale
0
0
0
0
0
0
0
0
Fig. 6
85
o
1
o
o
86
87
88
EO
1
1
1
1
1
0
+9.920
+9.840
0
1
0
1
0
1
+0.040
-0.040
0
0
0
0
1
0
-9.840
-9.920
Basic Bipolar Output Operation
+10.000
v
10.000 kll
10
IREF(+ I
~
2.00
~
14
4
Eo
10
EO
"A0801
10.000 kll
2
81
Pos Full Scale
Pos Full Scale - LSB
B2
B3
B4
85
1
1
1
B6
87
1
88
EO
EO
1
0
9.920
9.840
+10.000
+ 9.920
Zero Scale + LSB
Zero Scale
Zero Scale - LSB
1
1
0
0
0
1
0
0
1
0
0
1
0
0
1
0
0
0
0
1
1
0
1
0.080
0.000
+ 0.080
+ 0.160
+ 0.080
0.000
Neg Full Scale + LSB
Neg Full Scale
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
+ 9.920
+10.000
9.840
9.920
7-48
,uA0801 SERIES
Typical Applications (Cont.)
Fig. 7
Positive Low Impedance Output Operation
RL
Eo
"A0801
IFS
~
255 IAEF
256
For complementary output (operation as negative logic DAC),
connect inverting input of Op-Amp to iQ (Pin 2); connect 10 (Pin 4)
to ground.
Fig. 8
Negative Low Impedance Output Operation
>-<11>--- Eo
41----_-1
--10
"A0801
--10
2
RL
255
IFS ~ 256 IAEF
For complementary output (operation as negative logic DAC),
connect inverting input of Op-Amp to iQ (Pin 2); connect 10 (Pin 4)
to ground.
Fig. g
Pulsed Reference Operation
+VAEF
I
I:>
~ RAEF
i
RIN
ov
I
OPTIONAL RESISTOR
FOR OFFSET INPUTS
JL -~M"-""----<""'-I14
Rp
REO
~ 200
15
TYPICAL VALUES:
RIN = 5 k
+VIN = 10 V - = - - : : NO CAP
7-49
lOUT
,uA0801 SERIES
Typical Applications (Cont.)
Fig. 10 Accommodating Bipolar References
+VREF
RREF
~IRrE_F_ _ _ _ _ _ _ _.,
RREF
......'Mr----t 14
+VREF
~
"""W.,..---t
14
R'5 (OPTIONAL)
15
HIGH INPUT _
IMPEDANCE
RREF ~ R'5
+VREF must be above peak positive swing of VIN
IREF 2: peak negative swing of liN
Fig. 11
Interfacing With Various Logic Families
VTH ~ VLe + 1.4 V
+15 V CMOS, HTL, HNIL
VTH ~ +7.5 V
TTL,DTL
VTH ~ +1.4 V
+12 V TO
+15 V
PMOS
VTH ~ 0 V
+15 V
1N4148
9.1 k
VLe
6.2 V
ZENER
6.2 k
10 k
-5 V TO -10 V
-- -
-
-
-+-;-V-;;-M~
VTH
---+--- ----- -
~ +2.8 V
I
I
I
VTH ~ +5.0 V
I
I
+10 V
I
-1OkECL--- - - -
~ -1.29 V
VTH
1.3 k
I
I
VLe
T- ~ I
I
I
+10 V CMOS
I
6.2 k
I
I
I
I
I
3.6 k
I
I
V~
0.1 MF
1N4148
I
I
I
I
VLe
3.9 k
1k
I
I
-= -=
I
I
-5.2 V
Note
Do not exceed negative logic input range of DAC
Cross Reference Information
Part No.
Temperature Range
Nonlinearity
~AOSO 1DM (DAC-OSQ)
~AOSO 1EDC (DAC-OSEQ)
-55°C to
O°C 10
O°C 10
O°C 10
O°C 10
±O.19%
±O.19%
±O.19%
±O.39%
±O.39%
~AOSO 1EPC
~AOSO 1CDC
~AOS01CPC
(DAC-OSEP)
(DAC-OSCQ)
(DAC-OSCP)
+125°C
+70°C
+70°C
+70°C
+70°C
7·50
-- -
---
~AOS02
(MC150Sf140S)
Series S-Bit Multiplying
Of A Converter
FAIRCHILD
A Schlumberger Company
Data Aquisition Products
Connection Diagram
16-Pin DIP
Description
The ILA0802, ILA0802A, ILA08028 , and
ILA0802C are monolithic 8-bit multiplying
Digital-to-Analog Converters constructed using the
Fairchild Planar Epitaxial process. It is designed for
use where the output current is a linear product of an
8-bit digital word and an analog input voltage. The
ILA0802 is specified for the military temperature range
(-55°C to +125°C) and the ILA0802A, ILA08028
and ILA0802C are specified for O°C to 70°C operation.
The ILA0802 series are pin-for- pin replacements for the
MC 1508 / 1408 and SSS 1408 devices.
•
•
•
•
•
•
•
•
•
•
•
VeelOUT
(MSB)
VREF(-
(Top View)
Order Information
Type
Package
ILAOS02
Ceramic DIP
ILAOS02A
Ceramic DIP
ILAOS02A
Molded DIP
ILAOS028
Ceramic DIP
ILAOS028
Molded DIP
ILAOS02C
Ceramic DIP
ILAOS02C
Molded DIP
l-'!.:!4hr-------,
VREF(-)
16
COMP
REFERENCE
CURRENT
AMPLIFIER
15
Code
68
68
98
68
98
68
98
Part No_
ILA0802DM
ILA0802ADC
ILA0802APC
ILAOS028DC
ILAOS028PC
ILAOS02CDC
ILA0802CPC
Additional Order Information
Relative
Temperature
Type
Range
Accuracy
ILAOS02
(MC 150SL -S)
-55°C to +125°C ±0.19%
ILAOS02A
±0.19%
(MC140SL-S)
O°C to +70°C
ILAOS028
±0.39%
(MC140SL-7)
O°C to +70°C
ILA0802C
±0.7S%
(MC 140SL-6)
O°C to +70°C
GND
Vcc~
(LSB)
As
1
'3
A,
A6
Equivalent Circuit
R-2R LADDER
COMP
GND
RELATIVE ACCURACY ± 0_ 1% ERROR
MAXIMUM ILA0802H
RELATIVE ACCURACY ±0_19% ERROR
MAXIMUM ILA0802, ILA0802A
7 AND 6-BIT ACCURACY AVAILABLE
ILA0802B,ILA0802C
FAST SETTLING TIME TO 1/2 LSB-85 ns
NON-INVERTING DIGITAL INPUTS ARE TTL AND
CMOS COMPATIBLE
OUTPUT VOLTAGE SWING +0_5 V to -5_0 V
HIGH-SPEED MULTIPLYING INPUT SLEW RATE
4_0 mAIlls
STANDARD SUPPLY VOLTAGES +5_0 V AND
-5_0 V TO -15 V
LOW FULL SCALE CURRENT DRIFT
+10 PPM/oC TYPICALLY
LOW POWER CONSUMPTION 33 mW @ ± 5 V
LOWCOST
RANGE
CONTROL
16
RANGE
CONTROL
-Vcc.CURRENT SOURCE PAIR
7-51
•
~A0802
=
Absolute Maximum Ratings
Electrical Characteristics
Symbol
Er
Operating Temperature Range
TA
+25°C unless
otherwise noted
5.5 V
-16.5 V
Vee+
VeeDigital Input Voltage
(5 V to 12 V)
Applied Output Voltage
Reference Current (114)
Reference Amplifier Inputs
(V14, V15)
Series
~A0802
-55°C to +125°C
~A0802A, ~A0802B,
~A0802C
O°C to +70°C
Storage Temperature Range
Pin Temperatures
Ceramic DIP
(Soldering, 60 s)
Molded DIP (Soldering, 10 s)
+5.5 "
0.5 V to -5.2 V
5.0 mA
300°C
260°C
5.5 V, -16.5 V
Vee+ = +5.0 V, Vee- = -15 V, VREF/R14 = 2.0 mA,
All digital inputs at HIGH logic level.
Characteristic
Figure
Relative Accuracy (Error Relative to Full Scale 10)
3
Min
~A0802
Typ
Max
Unit
%
~A0802,~A0802A
~A0802B (Note 1)
~A0802C (Note 1)
±0.19
±0.39
±0.78
ts
Setting Time to Within ~ LSB
(includes tpLH) (T A +25°C) ( Note 2)
=
= +25°C
4
85
135
4
30
100
tpLH, tpHL
Propagation Delay Time TA
TClo
Output Full Scale Current Drift
Digital Input Logie Levels (MSB)
HIGH Level, Logie "1"
LOW Level, Logic "0"
2
VIH
VIL
2
IIH
IlL
Digital Input Current (MSB)
HIGH Level, VIH - 5.0 V
LOW Level, VIL - 0.8 V
115
Reference Input Bias Current (Pin 15)
2
2
lOR
Output Current Range
Vee = -5.0 V
Vee = -6.0 to -15 V
10
Output Current
VREF = 2.000 V, R14 = 1000 Q
2
10(min)
Output Current (All bits LOW)
2
2
Va
Output Voltage Compliance
(Er.:5 0.19% at T A +25°C)
Vee-5 V
Vee- below -10 V
SR IREF
PSRR(-)
Reference Current Slew Rate
5
lee+
lee-
Power Supply Current
(All bits LOW)
2
VeeR+
VeeR-
Power Supply Voltage Range
(TA = +25°C)
2
2
PD
Power Dissipation
All bits LOW
Vee-5.0 V
Vee- = -15 V
All bits HIGH
Vee- = -5.0 V
Vee-15 V
=
TA = -55°C to 125°C.
ns
ns
PPMloC
±20
V
2.0
0.8
=
mA
0
-0.4
0.04
-0.8
-1.0
-5.0
~A
0
0
2.0
2.0
2.1
4.2
mA
1.9
1.99
2.1
mA
mA
0
4.0
~A
V
-0.55, +0.4
-5.0, +0.5
4.0
Output Current Power Supply Sensitivity
+4.5
-4.5
=
0.5
2.7
~A!V
+13.5
-7.5
+22
-13.0
mA
+5.0
-15
+5.5
-16.5
V
mW
105
190
90
160
=
Notes
1. All current switches are tested to guarantee at least 50% of
rated output current.
2. All bits switched.
7·52
mA//.Ls
170
305
JLA0802 Series
Test Circuits
Fig. 1
Notation Definitions
Vee
lice I
13
Notes
Typical Values' R14 = R15 = 1 k
t
t
-
VREF = +20 V
C = 15 pF
I"
A,
"
A2
A3
DIGITAL
INPUTS
A,
MA0802
SERIES
As
-
,.
VREF(-)
R1'
V 1 and 11 apply to Inputs Al thru AS
"s
R1'
Vo
11
M
A8
The resistor tied to pin 15 IS to temperature compensate the bias
current and may not be necessary for all applications.
10
A6
OUTPUT
12
10 = K [
.-
+
+h
V'i
AI
A3
A5
A6
A7
32 + 64 + "'i28 +
+
Icc-t
A2
A4
"'2 + 4"' + ""'8 + 16
AS
256
J
VREF
Vcc-
where K '"
""R'i'4
and AN = "1" If AN is at HIGH level
AN = "0" If AN IS at LOW level
Fig. 2
Relative Accuracy Test Circuit
MSB
A,
A2
A3
A4
As
-
A6
-
12-81T
D/A
CONVERTER
(±O.02 %)
ERROR MAX)
!..!£..+10 V OUTPUT
5k
A,
-
A8
A9 Ai0A11 A12
LSB
VREF
100
I I I I
=2 V
1
W 101 • F
950
R1'
MSB
,.
vy+
13
5
6
7
8
8-BIT COUNTER
9
MA0802
SERIES
to
11
12
LS:k!~11
Vcc-
7-53
~
50 k
e-~
:A714
-=-
ERROR
(1 V= 1%)
~A0802
Series
Test Circuits (Cont.)
Fig. 3
Transient Response and Settling Time
24V
•.4Vt==q..________
2.V
Ycc+
+2.0 V
1.4 V
+~==
tr = ti::; 10 ns
0.1
,.
~F
SETTLING TIME
FOR FIGURE 4
~A0802
FOR SETTLING TIME
SERIES
MEASUREMENT.
(ALL BITS SWI1CHES
LOW TO HIGH)
'"
. 16
Is = 300 ns TYPICAL
TO :t1/2 LBS
Your
12
5.1 + - - - l l f -......- - - -.. 15 pF
-=
TRANSIENT
RESPONSE
1_ co:;; 25 pF
RL = 50!l
PIN 4 TO GND
mV -100
- L'PLH
0.1 ;.tF
VCC~
Applications
• Tracking aId Converters
• Successive Approximation aId Converters
• 2 1/2 Digit Panel Meters and DVMs
• Waveform Synthesis
• Sample and Hold
• Peak Detector
• Programmable Gain and Attenuation
• CRT Character Generation
• Audio Digitizing and Decoding
\.. Programmable Power Supplies
"'iI Analog·Digital Multiplication
• Digital·Digital Multiplication
• Analog-Digital Division
• Digital Addition and Subtraction
• Speech Compression and Expansion
• Stepping Motor Drive
Fig. 1
USE RL TO GND FOR
TURN OFF
MEASUREMENT
Positive VREF
Vcc+
R14 '" R15
(+)
VREF
..l"\..
Vcc-
7-54
~A0802
Series
Applications (Cont.)
Use with Current-to-Voltage Converting
OPAMP
Fig. 3
20Vdc
R14 "" R15 "" 1 0 kJl
Ro -= SO kn
VREF =
Vee'
MSB
A,
13
5
,.
VREF
R1'
A2
A3
A,
As
As
A,
As
,.
/-IA0802
SERIES
Ro
Adjust VREF R14 or RO so that
level is equal to 9.961 Volts.
11
12
Vo
LSe
V
o
=
3.Y...
1k
(5
Vo with
kl...!. + ...!. + ...!. + ....!...
L2
4
8
+....!...+....!...+ _1_+ _1_1
32
VCC~
64
128
= 10V 255 = 9.961 V
256
7-55
256J
16
all digital inputs at HIGH
FAIRCHILD
A Schlumberger Company
;
"
Telecommunications
- ....
,'
8-2
JLA3680 Quad
Telephone Relay Driver
FAIRCHIL.O
A Schlumberger Company
Telecommunication Products
Description
The 3680 relay driver is a monolithic integrated circuit
designed to interface -48 V relays to TTL or other
logic systems in telephony applications. The device
has a 50 mA source capability and operates from
-48 V battery power. The quad configuration
increases board density in typical line card
applications. Since there can be considerable noise
and IR drop between logic ground and battery ground,
these drivers are designed to operate with a high
common-mode range (± 20 V referenced to battery
ground~. Also, each driver has common-mode range
sepafn\te from the other drivers in the package. low
differ.ential input current (typically 100 p,A) draws low
power from the driving circuit. Differential inputs
permit either inverting or non-inverting operation. A
clamp network is incorporated in the driver outputs,
eliminating the need for an external network to quench
the high voltage inductive backswing caused when the
relay is turned off. A fail-safe feature is incorporated
to insure that the driver will be off if the VIN+ input or
both inputs are open. Standby power (driver off) is
very low, typically 50 p,W per driver.
Connection Diagram
14-Pin DIP
A+
BAT NEG
Input Voltage
(BAT NEG ~ -50 V)
Differential Input Voltage
(VIN+ - VIN-)
Output Current (ll :::; 5 H)
Output Current (Rl)
Power Dissipation
(85°C still air with package
soldered in PC board)
Ceramic DIP
Molded DIP
Pin Temperature (soldering)
Ceramic DIP (60 s)
Molded DIP (10 s)
Storage Temperature
A-
AOUT
B-
BOUT
B+
c+
COUT
DOUT
c-
BAT NEG
D+
D-
(Top View)
Order Information
Type
Package
p,A3680
Ceramic DIP
p,A3680
Molded DIP
• -48 V BATTERY OPERATION
• 50 mA OUTPUT CAPABILITY
• TTL/CMOS-COMPATIBLE COMPARATOR INPUT
• HIGH COMMON-MODE INPUT VOLTAGE RANGE
• VERY LOW INPUT CURRENT
• FAIL-SAFE DISCONNECT FEATURE
• BUILT-IN OUTPUT CLAMP DIODE
Absolute Maximum Ratings
BATGND
Code
6A
9A
Part No.
p,A3680DC
p,A3680PC
Logic Diagram
A+=C>-
AOUT
A-
(Notes 1 and 2)
Max
Min
+0.5 V
-70 V
+20 V
BAT NEG -0.5 V
B+=C>c+=C>-
±20 V
50 mA
100 mA
BOUT
B-
COUT
c-
D+=C>-
650 mW
930mW
D-
300°C
260°C
-65°C to +150°C
Notes on following pages.
8·3
DOUT
•
}1A3680
Circuit Schematic (1 /4 of circuit shown)
...----..--......--..---- ~~~
R1
VIN+
-_t_--"">/\r----,
VIN-
-+---..--C
05
06
06
07
R6
Vour
03
R3
L-_ _
Electrical Characteristics
~-~---~~----------~-:~~
Over Recommended Operating Conditions unless specified otherwise.
Typical values for BAT NEG = -52 V, and TA = 25°C.
Min
Conditions
Typ
Max
Unit
1.3
2.0
V
Symbol
Characteristic
VIH
Logic "1" Differential Input
Voltage
VIL
Logic "0" Differential Input
Voltage
IINH
Logic "1" Input Current
IINL
Logic "0" Input Current
VOL
Output On Voltage
IOFF
Output Leakage
IFS
Fail-Safe Output Leakage
= 2 V, VIN- = 0
= 7 V, VIN- = 0
VIN+ = 0.4 V, VIN- = 0
VIN+ = -7 V, VIN- = 0
IOL = 50 mA
VOUT = BAT NEG
VOUT = BAT NEG (Inputs open)
ILC
Output Clamp Leakage
Current
VOUT
Vc
Output Clamp Voltage
Vp
Positive Output Clamp Voltage
ICLAMP = -50 mA, Referenced to
BAT GND
0.9
1.2
IB(ON)
Supply Current
All drivers On
-2
-4.4
mA
IB(OFF)
Supply Current
All drivers Off
-1
-100
IlA
tpD(ON)
Propagation Delay to
Driver On
L
= 1H, RL = 1k, VIN = 3 V pulse
1
10
IlS
Propagation Delay to
tpD(OFF) Driver Off
L
= 1H, RL = 1k, VIN = 3 V pulse
1
10
IlS
0.8
40
375
VIN+
VIN+
= BAT GND
ICLAMP = +50 mA, Referenced to
BAT NEG
Notes
1. Absolute Maximum Ratings are those values beyond which the
safety of the device cannot be guaranteed. Except for
operating temperature range, they are not meant to imply that
1.3
-2.1
-1.2
V
100
1000
Il A
IlA
+0.01 +5
-1
-100
IlA
IlA
-1.6
V
+2
+100
IlA
+2
+100
IlA
-2
-100
IlA
-0.9
V
V
the device should be operated at these limits. The electrical
characteristic table includes conditions for actual device
operation.
2. All voltages are with respect to BAT GND.
8-4
~A3680
Recommended Operating Conditions
Characteristic
Min
Max
Unit
Battery Voltage (BAT NEG)
-60
-10
V
Input Voltage
-10
+10
V
Logic On Voltage (VIN+ - VIN-)
+10
V
Logic Off Voltage (VIN+ - VIN-)
+2
-10
+0.8
V
Temperature Range
-25
+85
°C
DC Test Circuit
t
liN
VIN
9
BAT NEG
-52 V
8·5
•
JLA3680
AC Test Circuit and Waveforms
r--r:::,
1
1 13
VIN {
~-+~----~--Vo
--_--=..,,-1
=1k
RL
L = 1H
L _ _ _ _ ...l
9
BAT NEG
-52 V
" d
ov
\
~------------------~
+3V
I-
I
__
I
tpd(on)
__
,:~",,}C
-52V
'--f---tPd-(O-ff)-
'\~
•
-
Typical Applications
+5V
i--'~-i
11
...::;
1
10-----'-1--1
113
2
1
1
1
114 "A3680
1
1
L ____ -.J
9
~---------'
-48 V
8-6
---r
L
48 VRELAyi
COIL.
50 mAo MAX
JLA5116
JL255-Law Companding
Codec
FAIRCHILD
A Schlumberger Company
Telecommunication Products
Description
The 5116 is a monolithic CMOS Companding Codec
containing both an analog-to-digital converter and a
digital-to-analog converter which have transfer
characteristics conforming to the ~255-Law
companding code. This device performs a coderdecoder function designed to meet the needs of the
telecommunications industry for per-channel voicefrequency codecs used in PCM systems. Digital input
and output are in serial format using sign-plusmagnitude coding. Actual transmission and reception
of a-bit data words containing the analog information
is done at a 64 kb / s to 2.1 Mb / s rate with analog
signal sampling occurring at an a kHz rate. A SYNC
pulse input is provided for synchronizing transmission
and reception of multichannel information being
multiplexed over a single transmission line.
•
•
•
•
•
•
•
•
Connection Diagram
16-Pin DIP
16
ANALOG
INPUT
VREF(+)
15
v+
VREF(-)
14
ANALOG
13 GROUND
ANALOG
12 OUTPUT
DIGITAL
INPUT
11
DIGITAL
GROUND
10 RCV
_ CLOCK
9
RCV
SYNC
vNC
MASTER 5
CLOCK
XMIT
SYNC
XMIT
CLOCK
DIGITAL
OUTPUT
EXCEEDS 03 CHANNEL BANK SPECIFICATIONS
LOW POWER DISSIPATION 30 mW TYPICAL
SYNCHRONOUS/ASYNCHRONOUS OPERATION
ON-CHIP S/H CIRCUIT
ON-CHIP OFFSET NULL CIRCUIT
SEPARATE ANALOG AND DIGITAL GROUNDS
64 kb/s to 2.1 Mb/s SERIAL DATA RATE
±5V POWER SUPPLY OPERATION
(Top View)
Order Information
Type
Package
~A5116
Ceramic DIP
~A 5116
Ceramic DIP
(Side Brazed)
Code
Part No.
DC
FW
~A5116
FB
~A5116
JC
Block Diagram
TRANSMIT (ENCODE)
•
RECEIVE (DECODE)
CONTROL
8-13
BIT
DIGITAL
COMPANDER
ENe/DEC
SWITCHES
DIGITAL
INPUT
ENe/DEC
CONTROL
DIGITAL
OUTPUT
TRANSMIT
CLOCK
6
TRANSMIT
SYNC
5
MASTER
CLOCK
PIn 4 = not connected
8-7
1.
RECEIVE
CLOCK
9
RECEIVE
SYNC
JLA5116
Absolute Maximum Ratings (Note)
Supply Voltage (V+)
+6
Supply Voltage (V-)
-6
Analog Input Range
V- :5 VIN :5 V+
Digital Input Range
-0.5 V :5 VIN :5 V+
Reference Voltage
VREF(+)
-0.5 V :5 VREF (+) :5 V+
Reference Voltage
V- :5 VREF(-) :5 0.5 V
VREF(-)
Operating Temperature
O°C to 70°C
Range
Storage Temperature
Range
-65°C to +125°C
Pin Temperature
260°C
(Soldering, 10 s)
Note
Stresses above those listed under" Absolute Maximum Ratings"
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any
other conditions beyond those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability. Standard CMOS handling procedures should be
employed to avoid possible damage to device.
Functional Description (Refer to Block Diagram)
edge of XMIT Clock, XMIT SYNC will determine
when the first positive edge of the internal clock will
occur. In this event, the hold time for the first clock
pulse is measured from the positive edge of
XMIT SYNC.
Positive and Negative Reference Voltages,
(VREF(+) and VREF(-) Pins 16 and 15)
These inputs provide the conversion references for
the digital-to-analog converters in the 5116. VREF(+)
and VREF(-) must maintain 100 ppM/oC regulation
over the operating temperature range. Variation of the
reference directly affects system gain.
RCV SYNC, Pin 9 (Refer to Figure 3 for the Timing
Diagram)
This input is synchronized with RCV Clock, and serial
data is clocked in by RCV Clock. Duration of the RCV
SYNC pulse is approximately eight RCV Clock
periods. The conversion from digital-to-analog starts
after the negative edge of RCV SYNC pulse (refer to
Figure 6). The negative edge of RCV SYNC should
occur before the 9th positive clock edge to insure that
only eight bits are clocked in. RCV SYNC must stay
LOW for 17 Master Clocks (minimum) before the next
digital word is to be received (Refer to Figure 11).
Analog Input, Pin 1
Voice-frequency analog signals which are bandwidthlimited to 4 kHz are input at this pin. Typically, they are
then sampled at an a kHz rate (Refer to Figure 6). The
Analog Input must remain between VREF(+) and
VREF(-) for accurate conversion.
Master Clock, Pin 5
This signal provides the basic timing and control
signals required for all internal conversions. It does
not have to be synchronized with RCV SYNC, RCV
Clock, XMIT SYNC or XMIT Clock and is not internally
related to them.
XMIT SYNC, Pin 6 (Refer to Figure 2 for the Timing
Diagram)
This input is synchronized with XMIT Clock. When
XMIT SYNC goes HIGH, the Digital Output is activated
and the AID conversion begins on the next positive
edge of Master Clock. The conversion by Master
Clock can be asynchronous with XMIT Clock. The
serial output data is clocked out by the positive edges
of XMIT Clock. The negative edge of XMIT SYNC
causes the Digital Output to become 3-state. XMIT
SYNC must go LOW for at least 1 Master Clock prior
to the transmission of the next digital word. (Refer to
Figure 10.)
RCV Clock, Pin 10 (Refer to Figure 3 for Timing
Diagram)
The on-chip a-bit shift register for the 5116 is
loaded at the clock rate present on this pin. Clock
rates of 64 kHz to 2.1 MHz can be used for RCV Clock.
Valid data should be applied to the digital input before
the positive edge of the internal clock (refer to
Figure 7). This set-up time, trds allows the data to be
transferred into the Master of a' master-slave flip-flop.
The positive edge of the internal clock transfers the
data to the slave of the master-slave flip-flop. A hold
time, trdh, is required to complete this transfer. If
the rising edge of RCV SYNC occurs after the first
riSing edge of RCV Clock, RCV SYNC will determine
when the first positive edge of internal clock will
occur. In this event, the set-up and hold times for the
first clock pulse should be measured from the positive
edge of RCV SYNC.
XMIT Clock, Pin 7 (Refer to Figure 2 for the Timing
Diagram)
The on-chip a-bit output shift register of the 5116 is
unloaded at the clock rate present on this pin. Clock
rates of 64 kHz to 2.1 MHz can be used for XMIT
Clock. The positive edge of the internal clock
transfers the data from the master to the slave of a
master-slave flip-flop (refer to Figure 7). If the
positive edge of XMIT SYNC occurs after the positive
Digital Output, Pin 8
The 5116 output register stores the a-bit encoded
sample of the Analog Input. This a-bit word is shifted
out under control of XMIT SYNC and XMIT Clock.
When XMIT SYNC is LOW, the Digital Output is an
open circuit. When XMIT SYNC is HIGH, the state of
the Digital Output is determined by the value of the
output bit in the serial shift register. The output is
composed of a sign bit, 3 chord bits, and 4 step bits.
8-8
,uA5116
The sign bit indicates the polarity of the Analog Input
while the chord and step bits indicate the magnitude.
In the first chord, the step bit has a value of 0.6 mV. In
the second chord, the step bit has a value of 1.2 mV.
This doubling of the step value continues for each of
the next six successive chords.
Table 1
1.
2.
3.
4.
5.
6.
7.
8.
Each chord has a specific value and the step bits,
16 in each chord, specify the displacement from that
value (refer to Table 1. Thus the output, which
follows the J.L255-Law, has resolution that is
proportional to the input level rather than to full
scale. This provides the resolution of a 12-bit a / d
converter at low input levels and that of a 6-bit
converter as the input approaches full scale. The
transfer characteristic of the a / d converter (J.L255-Law
Encoder) is shown in Figure 8.
Digital Output Code for 5116
Chord Code
Chord Value
Step Value
000
001
010
011
100
101
110
111
0.0 mV
10.11 mV
30.3 mV
70.8 mV
151.7 mV
313 mV
637 mV
1.284 V
0.613 mV
1.226 mV
2.45 mV
4.90 mV
9.81 mV
19.61 mV
39.2 mV
78.4 mV
Example:
1
011
Sign Bit Chord
0010 = +70.8 mV + (2 x 4.90 mV)
Step Bits
If the sign bit were a zero, then both plus signs would
be changed to minus signs.
Digital Input, Pin 12
The 5116 input register accepts the 8-bit sample of an
analog value and loads it under control of RCV SYNC
and RCV Clock. The timing diagram is shown in Figure
3. When RCV SYNC goes HIGH, the 5116 uses RCV
Clock to clock the serial data into its input register.
RCV SYNC goes LOW to indicate the end of serial
input data. The eight bits of the input data have the
same functions described for the Digital Output. The
transfer characteristic of the d / a converter (J.L255-Law
Decoder) is shown in
Figure 9.
Analog Output, Pin 13
The Analog Output is in the form of voltage steps
(100% duty cycle) having amplitude equal to the
analog sample which was encoded. This waveform
is then filtered with an external low-pass filter with
(sin x) / x correction to recreate the sampled
voice signal.
•
Operation of Codec With 64 kHz XMIT IRCV
Clock Frequencies
XMIT / RCV SYNC must not be allowed to remain at a
logic "1" state. XMIT SYNC is required to be at a logic
"0" state for one Master Clock period (minimum)
before the next digital word is transmitted. RCV SYNC
is required to be at a logic "0" state for 17 Master
Clock periods (minimum) before the next digital word
is received (refer to Figures 10 and 11).
Offset Null
The offset null feature of the 5116 eliminates longterm drift errors and conversion errors due to
temperature changes by going through an offset
adjustment cycle before every conversion, thus
guaranteeing accurate a / d conversion for inputs near
ground. There is no offset adjust of the output
amplifier since the output is intended to be ac-coupled
to the external filter and the resultant dc error
(VOFFSET /0) will have no effect. The sign bit is not
used to null the Analog Input. Therefore, for an Analog
Input of 0 V, the sign bit will be stable.
8-9
J.LA5116
Electrical Operating Characteristics
Power Supply Requirements
Symbol
Characteristic
Min
Typ
Max
Unit
V+
Positive Supply Voltage
4.75
5.0
5.25
V
V-
Negative Supply Voltage
-5.25
-5.0
-4.75
V
VREF(+)
Positive Reference Voltage (Note 1)
2.375
2.5
2.625
V
VREF(-)
Negative Reference Voltage (Note 1)
-2.625
-2.5
-2.375
V
Max
Unit
DC Characteristics
V+
= 5 V. V- = -5 v. VREF(+) = 2.5 V. VREF (-) = -2.5 V.
Characteristic
R,NAS
Analog Input Resistance During
Sampling (Note 2)
2
R'NANS
Analog Input Resistance Non-Sampling
100
C'NA
Analog Input Capacitance
150
250
VOFFSETII
Analog Input Offset Voltage
±1
±8
mV
ROUTA
Analog Output Resistance
20
50
n
IOUTA
Analog Output Current
VOFFSET/O
Analog Output Offset Voltage
±200
±850
mV
IlL
Logic Input LOW Current (V,N = 0.8 V)
Digital Input, Clock Input. SYNC Input
(Note 3)
±0.1
±10
/LA
I'H
Logic Input HIGH Current (V,N = 2.4 V)
Digital Input. Clock Input, SYNC Input
(Note 3)
-0.25
-0.8
mA
COO
Digital Output Capacitance
8
12
pF
±0.1
±10
/LA
IDOL
Digital Output Leakage Current
VOL
Digital Output LOW Voltage (Note 4)
VOH
Digital Output HIGH Voltage (Note 4)
1+
Min
Typ
Symbol
0.25
kn
Mn
0.5
pF
mA
0.4
V
V
3.9
Positive Supply Current
4
10
1-
Negative Supply Current
2
6
mA
IREF+
Positive Reference Current
4
20
/LA
IREF-
Negative Reference Current
4
20
/LA
8-10
mA
JLA5116
AC Characteristics
Refer to Figures 2 and 3.
Symbol
Characteristic
Min
Typ
Max
Unit
fm
Master Clock Frequency
1.5
1.544
2.1
MHz
fr, fx
RCV, XMIT Clock Frequency
0.064
1.544
2.1
MHz
PWclk
Clock Pulse Width (MASTER, XMIT, RCV)
200
trc, tfc
Clock Rise, Fall Time (MASTER, XMIT, RCV
25% of
PWclk
ns
t rs , tfs
SYNC Rise, Fall Time (XMIT, RCV)
25% of
PWclk
ns
tOlr, tOlf
Data Input Rise, Fall Time
25% of
PWclk
ns
ns
twsx, twsr
SYNC Pulse Width (XMIT, RCV)
8
fx(fr)
tps
SYNC Pulse Period (XMIT,RCV)
125
hcs
t xcsn
XMIT Clock-to-XMIT SYNC Delay (Note 5)
XMIT Clock-to-XMIT SYNC
ILs
ILS
50% of
tfcCtrs)
ns
200
ns
(Negative Edge) Delay
t xss
XMIT SYNC Set-Up Time
200
txdd
XMIT Data Delay (Note 4)
0
200
ns
ns
txdp
XMIT OAT A Present (Note 4)
0
200
ns
txdt
XMIT Data Three State (Note 4)
150
ns
tdof
Digital Output Fall Time (Note 4)
50
ns
tdor
Digital Output Rise Time (Note 4)
50
ns
RCV SYNC-to-RCV Clock Delay (Note 5)
50%
trcCtfs)
trds
RCV Data Set-Up Time (Note 6)
50
ns
trdh
RCV Data Hold Time (Note 6)
200
ns
trcs
RCV Clock-to-RCV SYNC Delay
200
ns
trss
RCV SYNC Set-Up Time (Note 6)
200
tsao
RCV SYNC-to-Analog Output Delay
7
Slew+
Analog Output Positive Slew Rate
1
Slew-
Analog Output Negative Slew Rate
1
ILS
V/ILS
V/ILS
Droop
Analog Output Droop Rate
25
ILV IllS
tsrc
Notes
1. +VREF and -VREF must be matched within ± 1% in order
to meet system requirements.
2. Sampling is accomplished by charging the internal capacitor to
within 1/2 LSB (::s 300 /LV) in 20 /Ls. Therefore, the external
source resistance must be 3 kO or less. The equivalent circuit
during sampling is shown in Figure 1.
3. The 5116 will source current through an internal 6 kO
resistor to help pull up the TTL output. When a transition from a
ns
ns
"1" to a "0" takes place, the user must sink the "1" current
until reaching the "0" level.
4. Driving one 74L or 74LS TTL load plus 30 pF with
IOH = -100 /LA, IOL = 500/LA.
5. This delay is necessary to avoid overlapping Clock and SYNC.
6. The first bit of data is loaded when SYNC and Clock are both
"1" during bit time 1 as shown on RCV timing diagram.
8·11
•
pA5116
System Characteristics
Refer to Figures 4 and 5
Symbol
Characteristic
Min
Typ
SID
Signal-to-Distortion
35
29
24
39
34
29
GT
Gain Tracking
NIC
TLP
Fig. 1
Max
Unit
Condition
dB
dB
dB
Analog Input
Analog Input
Analog Input
±0.1
±0.1
±0.2
±0.4
±0.8
±2.5
dB
dB
dB
Idle Channel Noise
10
18
dBrnCO
= 0 to -30 dBmO
= -40 dBmO
= -45 dBmO
Analog Input = +3 to -37 dBmO
Analog Input = -37 to -50 dBmO
Analog Input = -50 to -55 dBmO
Analog Input = 0 V
Transmission Level Point
+4
dB
600 fl
Equivalent Circuit During Sampling
CODEC
SAMPLE
SOURCE
1 GATE
RES'STANcer RESISTANCE
~3k
L
~5k
I
150 OFt
Fig. 2
Transmitter Section Timing
2.4 V
1.4 V
INITIAL DATA
NOT VALID
~--------------------~v~----------------------~
PCM DATA PRESENT
Note
All rise and fall times are measured from 0.4 V and 2.4 V. All delay
times are measured from 1.4 V.
8·12
~A5116
Fig. 3
Receiver Section Timing
RCV
SYNC
.:A~N~A~L~O~G~O~U~T;P~U~T
______________________________________________________________________________________________
~~
\.
Note
All rise and fall times are measured from 0.4 V and 2.4 V. All delay
times are measured from 1.4 V.
Fig. 4
SID Ratio vs Input Level
Fig. 5
Gain Tracking Performance
0
4
0
3
I 60
2
'l!
z
o
;:: 5 0
a:
o
Iii
1i
o
.
I-
....
'3l-J-
+1
1 --'05
42 40
42
40
40
3h
~9----,
30
3i
~ 2Of-
~
t- 03
iii
"z
..g 0 t-- tFi'---':2f'
51161--t--
::t<34
2
CHANNEL BANK
a:
I-
Z
......"""23
r;;
"
SPECIFICATIONS
0
-10
-20
-30
-os
-2
r
g~ANNEt BANIK
01_
-01
~,;\l
,L t--t-5116-
Spr'FlrTIOr
-3
-3
0
+3 0
1
;;:
N5-
-40
-50
t--
I
4
-60
+'0
INPUT LEVEL - dBmO
-10
-20
-30
-40
INPUT lEVEL - dBmO
8-13
50
-60
-70
•
~A5116
Fig.6
AID, DIA Conversion Timing
~
~------------------------------------------_125"'------------------------------------."i~
_
1-
:;SYNC \ ' - - -_ _ _ _ _ _
"" 15-20 IJ.I
SAMPLE AND HOLD
SAMPLE TIME
• 32 MASTER CLOCKS
ENABLE SAA
SAR
CONTINUES
SAR REQUIRES
• 128 MASTER CLOCKS
----------------/
Rev SYNC
----------------------------~/
Fig.7
Data Input/Output Timing
Fig. 8
I~ 200 n.~
REQUIRED FOR DATA TO TRANSFER
• - FROM MASTER TO SLAVE
XMIT
INTERNAL
CLOCK
I
I!!
::>
I!:
\/VALIDDATA
_I
-..,
~-~200n.
~.
AID Converter (J,£255-Law Encoder)
Transfer Characteristic for 5116
11111111
11110000
11100000
11010000
11000000
10110000
,,-
10100000
10010000
5..J ~-00000000 00010000
REQUIRED TO TRANSFER DATA
FROM MASTER TO SLAVE
j!
S
==~I~~----==~~~-
1...-50 na
ANALOG OUTPUT UPDATED
REQUIRED TO LOAD MASTER
00100000
0011 0000
01000000
01010000
01100000
011100bO
VALID INCOMING DATA
01111111
5116
DIGITAL
OUT
XMIT SYNC
XMIT CLOCK
DIGITAL IN
RCV SYNC
RCV CLOCK
8-14
./
-
ANALOG INPUT
f-""
JLA5116
Flg.9
D/A Converter (1'255·Law Decoder)
Transfer Characteristic for 5116
F
II
+O.5VREF
IJ
/
V
II
DIGITAL INPUTS
Fig. 10 64 kHz Operation, Transmitter Section Timing
~1·~-------------------------------------125"·----------------------------------~·~1________
~
:::JI
XMIT
---.J
I
-1
~PWClk
,----
1 MASTER
CLOCK
PERIOD
(MIN)
WORD)
~--------------------------~v~--------------------------------~
PCM DATA PRESENT
Note
All rise and fall times are measured from 0.4 V and 2.4 V. All delay
times are measured from 1.4 V.
8-15
•
ILA5116
Fig. 11
64 kHz Operation, Receiver Section Timing
\"".o--______________
u
--.j.\
'2$.S _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
i---
::J
I
'7 MASTER
CLOCK PERIODS~
(MIN)
~
Note
All rise and fall limes are measured from 0.4 V and 2.4 V. All delay
limes are measured from 1.4 V.
Performance Evaluation
When all the above requirements are met, the set-up
of Figure 12 permits the measurement of synchronous
system performance over a wide range of Analog
Inputs. The data register and ideal decoder provide a
means of checking the encoder portion of the 5116
independently of the decoder section. To test the
system in the asynchronous mode, Master Clock
should be separated from XMIT Clock, and Master
Clock should be separated from RCV Clock. XMIT
Clock and RCV Clock are separated also.
The equipment connections shown in Figure 12
can be used to evaluate the performance of the
5116. An analog signal provided by the HP3551 A
Transmission Test Set is connected to the Analog
Input (Pin 1) of the 5116. The Digital Output of the
codec is tied back to the Digital Input and the Analog
Output is fed through a low-pass filter to the HP3551 A.
Remaining pins of the 5116 are connected as follows:
1. RCV SYNC is tied to XMIT SYNC.
2. XMIT Clock is tied to Master Clock. The signal is
inverted and tied to RCV Clock.
The following timing signals are required:
1. Master Clock
2.048 MHz
2. XMIT SYNC repetition rate
8 kHz
3. XMIT SYNC width = 8 XMIT Clock periods
=
=
8·16
JlA5116
Fig. 12 System Characterlstlca Teat Configuration
-------,
I
1.004 kHz
SIGNAL
SOURCE
I
I
I
114 DIGITAL
INPUT
1
DIGITAL
8
IDEAL
DECODER
(NOTE)
DATA
REGISTER
OUTPUT
ANALOG
INPUT
ANALOG 13
OUTPUT
I
I
I
SYSTEM
5118
.\
JODER
ONLY
I
I
I
IL _ _ _ _ _
..,
I
I
:
1.004 kHz
NOUT -
L~
NOTCH
FILTER
FILTER
I
I
I
3851A
I
I
------------ I-...J
SOUT
+ NOUT
Note
The ideal decoder consists DI a digital decDmpander and a 13·bit
precIsion DAC
•
8·17
JLA5151
JL255-Law Companding
Codec
FAIRCHILD
A Schlumberger Company
Telecommunications Products
Connection Diagram
24-Pin DIP
Description
The 5151 is a monolithic CMOS Companding Codec
which contains two sections: (1) an analog-to-digital
converter which has a transfer characteristic
conforming to the standard 1'255 companding Law,
and (2) a digital-to-analog converter which also
conforms to the 1'255 companding Law.
OIGITAL
OUTPUT
XMIT
CLOCK
AlB SEL
(XMIT)
B SIGNAL
IN
A SIGNAL
IN
These two sections form a coder-decoder which is
designed to meet the needs of the telecommunications industry for per-channel voice-frequency codecs
used in 03 Channel Bank and PBX systems. Digital
input and output are in serial format. Actual
transmission and reception of a-bit data words
containing the analog information is done at a 64 kb/s
to 2.1 Mb/s rate with analog signal sampling occurring
at an a kHz rate. A SYNC pulse input is provided for
synchronizing transmission and reception of
multichannel information being multiplexed over a
single transmission line.
2
3
4
5
6
RCVSYNC
RCV 7
CLOCK
AlB SEL 8
(RCV)
A SIGNAL 9
OUT
B SIGNAL 10
OUT
DIGITAL 11
INPUT
DIGITAL 12
GROUND
• EXCEEDS D3 CHANNEL BANK SPECIFICATIONS
• LOW POWER DISSIPATION 30 mW TYPICAL
• SYNCHRONOUS/ASYNCHRONOUS OPERATION
• ON-CHIP S/H CIRCUIT
• ON-CHIP OFFSET NULL CIRCUIT
• SEPARATE ANALOG AND DIGITAL GROUNDS
• 64 kb/s TO 2.1 Mb/s SERIAL DATA RATE
• ZERO CODE SUPPRESSION
• ±5 V POWER SUPPLY OPERATION
(Top View)
Order Information
Type
Package
I'A~151
Ceramic DIP
I'A:5151
Ceramic DIP
(Side Brazed)
Code
7L
Part No.
I'A5151DC
7R
I'A5151JC
Block Diagram
TRAfIISMiT (ENCODE)
RECEIVE (DECODE)
CONTROL
8-13
BIT
DIGITAL
COMPANDER
,.
ANALOG
OUTPUT
11
DIGITAL
INPUT
A
g~G,!~~~_':t-
9
,.
_____-I
B SIGNAL
OUTPUT
A SIGNAL 5
INPUT-=t--<>"1---_ _ _--.J
B
s~:=~~
4
22
7
MASTER
CLOCK
Pins 15. 16, and 24
SIGNAL
OUTPUT
=not connected.
8·18
RECEIVE
CLOCK
6
RECEIVE
SYNC
8 AlB
SELECT
RECEIYE
J.LAi5151
Absolute Maximum Ratings (Note)
Supply Voltage (V+)
+6 V
-6 V
Supply Voltage (V-)
V- ::5 VIN ::5 V+
Analog Input Range
Digital Input Range
-0.5 V ::5 VIN ::5 V+
Reference Voltage
VREF(+)
-0.5 V ::5 VREF(+)::5 V+
Reference Voltage
VREF(-)
V- ::5 VREF(-) ::5 0.5 V
Operating Temperature
Range
O°C to 70°C
Storage Temperature
Range
-55°C to +125°C
Pin Temperature
(Soldering, 10 s)
260°C
Note
Stresses above those listed under" Absolute Maximum Ratongs"
may cause permanent damage to the device. This is a stress
ratong only and functional operation 01 the device at these or any
other conditions beyond those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability. Standard CMOS handling procedures should be
employed to avoid possible damage to device.
Functional Description (Refer to Block Diagram)
XMIT Clock, XMIT SYNC will determine when the first
positive edge of the Internal Clock will occur. In this
event, the hold time for the first clock pulse is
measured from the positive edge of XMIT SYNC.
Positive and Negative Reference Voltages
(VREF(+) and VREF(-) Pins 19 and 18)
These inputs provide the conversion references for
the digital-to-analog converters in the 5151. VREF( +)
and VREF(-) must maintain 100 ppM/ °C regulation
over the operating temperature range. Variation of the
reference directly affects system gain.
RCV ISYNC, Pin 6 (Refer to Figure 3 for the
Timing Diagram)
This input is synchronized with RCV Clock, and
serial data is clocked in by RCV Clock. Duration of the
RCV SYNC pulse is approximately eight RCV Clock
periods. The conversion from digital-to-analog
starts after the negative edge of RCV SYNC pulse
(refer to Figure 6). The negative edge of RCV SYNC
should occur before the 9th positive clock edge to
insure that only eight bits are clocked in. RCV SYNC
must stay LOW for 17 Master clocks (minimum) before
the next digital word is to be received. (refer to Figure 11)
Analog Input, Pin 20
Voice-frequency analog signals which are bandwidthlimited to 4 kHz are input at this pin. Typically, they
are then sampled at an S kHz rate (Refer to Figure 6 ).
The analog input must remain between VREF(+) and
VREF(-) for accurate conversion.
Master Clock, Pin 22
This signal provides the basic timing and control
signals required for all internal conversions. It does
not have to be synchronized with RCV SYNC, RCV
Clock, XMIT SYNC or XMIT Clock and is not internally
related to them.
RCV Clock, Pin 7 (Refer to Figure 3 for
Timing Diagram)
The on-chip S-bit shift register for the 5151 is loaded
at the clock rate present on this pin. Clock rates of
64 kHz to 2.1 MHz can be used for RCV Clock. Valid
data should be applied to the Digital Input before
the positive edge of the internal clock (refer to
Figure 7). This set-up time, trds, allows the data to be
transferred into the master of a master-slave flip-flop.
The positive edge of the Internal Clock transfers the
data to the slave of the master-slave flip-flop. A hold
time, trdh, is required to complete this transfer. If the
rising edge of RCV SYNC occurs after the first rising
edge of RCV Clock, RCV SYNC will determine when
the first positive edge of Internal Clock will occur. In
this event, the set-up and hold times for the first clock
pulse should be measured from the positive edge of
RCV SYNC.
XMIT SYNC, Pin 23 (Refer to Figure 2 for the Timing
Diagram)
This input is synchronized with XMIT Clock. When
XMIT SYNC goes HIGH, the digital output is activated
and the a / d conversion begins on the next positive
edge of Master clock. The conversion by Master
Clock can be asynchronous with XMIT Clock. The
serial output data is clocked out by the positive edges
of XMIT Clock. The negative edge of XMIT SYNC
causes the digital output to become 3-state. XMIT
SYNC must go LOW for at least 1 master clock
prior to the transmission of the next digital word.
(Refer to Figure 10.)
Digital Output, Pin 1
The 5151 output register stores the S-bit encoded
sample of the analog input. This S-bit word is shifted
out under control of XMIT SYNC and XMIT Clock.
When XMIT SYNC is LOW, the Digital Output is an
open circuit. When XMIT SYNC is HIGH, the state of
the Digital Output is determined by the value of the
output bit in the serial shift register. The output is
composed of a sign bit, 3 chord bits, and 4 step bits.
The sign bit indicates the polarity of the Analog
XMIT Clock, Pin 2 (Refer to Figure 2 for the
Timing Diagram)
The on-chip S-bit output shift register of the 5151 is
unloaded at the clock rate present on this pin. Clock
rates of 64 kHz to 2.1 MHz can be used for XMIT
Clock. The positive edge of the Internal Clock
transfers the data from the master to the slave of a
If the positive
master-slave flip-flop (refer to Figure
edge of XMIT SYNC occurs after the positive edge of
n.
8-19
•
:
(RCV) routes the signal bit to A Signal Out while a
negative transition routes the signal bit (bit B) to B
Signal Out. Refer to Figure 12.
Input while the chord and step bits indicate the
magnitude. In the first chord, the step bit has a value
of 0.6 mY. In the second chord, the step bit has a
value of 1.2 mY. This doubling of the step value
continues for each of the six successive chords.
AlB SEL (RCV), Pin 8
This input routes the signalling bit, bit 8, either to A
Signal Out or to B Signal Out as described in the AlB
Signal Out paragraph above, and should be changed
only at the start of the 6th and 12th frames as shown
in Figure 13.
Each chord has a specific value and the step bits, 16
in each chord, specify the displacement from that
value (refer to Table 1). Thus the output, which follows
the /J255·Law, has resolution that is proportional to
the input level rather than to full scale. This provides
the resolution of a 12-bit a I d converter at low input
levels and that of a 6-bit converter as the input
approaches full scale. The transfer characteristic
of the aid converter (WLaw Encoder) is shown
in Figure 8.
AlB SEL (XMIT), Pin 3
This input selects either A Signal In or B Signal In as
described in the AlB Signal In paragraph above, and
should be changed only at the start of the 6th and
12th frames as shown Figure 13.
Offset Null
The offset null feature of the 5151 eliminates longterm drift errors and conversion errors due to
temperature changes by going through an offset
adjustment cycle before every conversion, thus
guaranteeing accurate a I d conversion for inputs
near ground. There is no offset adjust of the
output amplifier. Since the output is intended to be
ac-coupled to the external filter, the resultant dc error
(VOFFSET /0) will have no effect. The sign bit is not
used to null the Analog Input. Therefore, for an Analog
Input of 0 V, the sign bit will be stable.
Digital Input, Pin 11
The 5151 input register accepts the 8-bit sample of an
analog value and loads it under control of RCV SYNC
and RCV Clock. The timing diagram is shown in
Figure 3. When RCV SYNC goes HIGH, the 5151 uses
RCV Clock to clock the serial data into its input
register. RCV SYNC goes LOW to indicate the end of
serial input data. The eight bits of the input data have
the same functions described for the Serial Output.
The transfer characteristic of the d I a converter
(wLaw Decoder) is shown in Figure 9.
Analog Output, Pin 14
The Analog Output is in the form of voltage steps
(100% duty cycle) having amplitude equal to the
analog sample which was encoded. This waveform
is then filtered with an external low-pass filter
with (sin x) I x correction to recreate the sampled
voice signal. When the Bth bit of the word is a
signalling bit, it is assigned a value of 1/2 step. This
results in a lower system quantization error rate than
would result if the bit were arbitrarily set to 0 (no step)
or,1 (full step).
Table 1
\~
Operation of Codec With 64 kHz XMIT IRCV
Clock Frequencies
XMIT IRCV SYNC must not be allowed to remain at a
logic" 1" state. XMIT SYNC is required to be at a logic
"0" state for 1 master clock period (minimum) before
the next digital word is transmitted. RCV SYNC is
required to be at a logic "0" state for 17 master clock
periods (minimum) before the next digital word is
received (refer to Figures 10 and 11).
Digital Output Code: wLaw
Chord Code
Chord Value
Step Value
1.
2.
3.
4.
5.
6.
7.
B.
O.OmV
10.11 mV
30.3mV
70.8mV
151.7 mV
313 mV
637mV
1.284 V
0.613
1.226
2.45
4.90
9.81
19.61
39.2
7B.4
111
110
101
100
011
010
001
000
Example:
1
100
Sign Bit Chord
mV
mV
mV
mV
mV
mV
mV
mV
1101 = +70.8 mV + (2 x 4.90 mY)
Step Bits
If the sign bit were a zero, then both plus signs would
be changed to minus signs.
AlB Signal In, Pins 4 and 5
These two pins allow insertion of signalling information
into the transmitted data stream. The inserted
information occurs as the Bth bit (LSB) in the
transmitted word. A positive transition occurring on
A I B SEL (XMIT) selects A Signal In while a negative
transition selects B Signal In.
AlB Signal Out, Pins 9 and 10
These two pins are provided to output received
signalling information. A positive transition on AlB SEL
8-20
ILA5151
Electrical Operating Characteristics
Power Supply Requirements
Symbol
Characteristic
Min
Typ
Max
Unit
V+
Positive Supply Voltage
4.75
5.0
5.25
V
V-
Negative Supply Voltage
-5.25
-5.0
-4.75
V
VREF(+)
Positive Reference Voltage (Note 1)
2.375
2.5
2.625
V
VREF(-)
Negative Reference Voltage (Note 1)
-2.625
-2.5
-2.375
V
DC Characteristics
Symbol
V+
= 5.0 V, V- = -5.0 V, VREF(+) = 2.5 V, VREF (-) = -2.5 V.
Min
Characteristic
Typ
Max
Unit
RINAS
Analog Input Resistance During
Sampling (Note 2)
2
RINANS
Analog Input Resistance Non-Sampling
100
CINA
Analog Input Capacitance
150
VOFFSET/I
Analog Input Offset Voltage
±1
±8
mV
ROUTA
Analog Output Resistance
20
50
Q
kQ
MQ
250
pF
IOUTA
Analog Output Current
VOFFSET/O
Analog Output Offset Voltage
±200
±850
mV
III
Logic Input LOW Current (VIN = 0.8 V)
Digital Input, Clock Input, SYNC Input
(Note 3)
±0.1
±10
J.l.A
IIH
Logic Input HIGH Current (VIN = 2.4 V)
Digital Input, Clock Input, SYNC Input
(Note 3)
-0.25
-0.8
mA
0.25
mA
0.5
COO
Digital Output Capacitance
8
12
pF
IDOL
Digital Output Leakage Current
±0.1
±10
J.l.A
VOL
Digital Output LOW Voltage (Note 4)
0.4
V
VOH
Digital Output HIGH Voltage (Note 4)
1+
Positive Supply Current
4
10
mA
V
3.9
1-
Negative Supply Current
2
IREF+
Positive Reference Current
4
6
20
J.l.A
IREF-
Negative Reference Current
4
20
J.l.A
8-21
mA
..
•
JLA5151
AC Characteristics
Reier to Figures 2 and 3.
Symbol
Characteristic
Min
Typ
Max
Unit
1m
Master Clock Frequency
1.5
1.544
2.1
MHz
fr, Ix
RCV, XMIT Clock Frequency
0.064
1.544
2.1
MHz
PWeik
Clock Pulse Width (MASTER, XMIT, RCV)
200
tre , tie
t rs , tis
tdir, tdil
Clock Rise, Fall Time (MASTER, XMIT, RCV)
ns
SYNC Rise, Fall Time (XMIT, RCV)
25% 01
PWeik
ns
Digital Input Rise, Fall Time
25% 01
PWeik
ns
t wsx , twsr
SYNC Pulse Width (XMIT RCV)
tps
SYNC Pulse Period (XMIT,RCV)
t xes
t xesn
ns
25% 01
PWeik
8
jlS
Ix(fr)
125
XMIT Clock-to-XMIT SYNC Delay (Note 5)
XMIT Clock-to-XMIT SYNC
jlS
50% 01
tle(trs)
ns
200
ns
(Negative Edge) Delay
hss
XMIT SYNC Set-Up Time
200
txdd
XMIT Data Delay (Note 4)
0
200
ns
txdp
XMIT DATA Present (Note 4)
0
200
ns
150
ns
ns
txdt
XMIT Data Three State (Note 4)
tdol
Digital Output Fall Time (Note 4)
50
ns
tdor
Digital Output Rise Time (Note 4)
50
ns
tsre
RCV SYNC-to-RCV Clock Delay (Note 5)
50% 01
tre(tls)
trds
RCV Data Set-Up Time (Note 6)
50
ns
trdh
RCV Data Hold Time (Note 6)
200
ns
tres
RCV Clock-to-RCV SYNC Delay
200
ns
trss
RCV SYNC Set-Up Time (Note 6)
200
ns
7
ns
tsao
RCV SYNC-to-Analog Output Delay
tAIBI
AlB Signalling Input Set-Up Time
tAIB SH
AlB Select Hold Time
200
ns
tAIBSS
AlB Select Setup Time
400
ns
tAIBO
AlB Signalling Output Delay
200
Slew+
Analog Output Positive Slew Rate
1
V/jls
Slew-
Analog Output Negative Slew Rate
1
V I IlS
Droop
Analog Output Droop Rate
25
jlV/jls
jlS
200
Notes
1. +VREF and -VREF must be matched within ± 1% in order to
meet system requirements.
2. Sampling is accomplished by charging the internal capacitor to
within 1/2 lSB (:5 300 /lV) in 20 /lS. Therefore, the external
source resistance must be 3 kf! or less. The equivalent circuit
during sampling is shown in Figure 1.
3. The 5156 will source current through an internal 6 kf! resistor
to help pull up the TTL output. When a transition from" 1 " to "0"
300
ns
ns
takes place, the user must sink the" 1" current until reaching
the "0" level.
4. Driving one 74l or 74lS TTL load plus 30 pF with
IOH = -100 /lA, IOl = 500/lA.
5. This delay is necessary to avoid overlapping Clock and SYNC.
6. The first bit of data is loaded when SYNC and Clock are both
"1" during bit time 1 as shown on RCV timing diagram.
8·22
~A5151
System Characteristics
Refer to Figures 4 and 5.
Symbol
Characteristic
Min
Typ
SID
Signal-to-Distortion
35
29
24
39
34
29
GT
Gain Tracking
NIC
TLP
Max
Unit
Condition
dB
dB
dB
Analog Input
Analog Input
Analog Input
Analog
Input = +3 to -37 dBmO
Analog
Input = -37 to -50 dBmO
Analog
Input = -50 to -55 dBmO
±0.1
±0.4
dB
±O.1
±O.B
dB
±0.2
±2.5
dB
Idle Channel Noise
10
18
dBrnCO
Analog Input
Transmission Level Point
+4
dB
eoon
= 0 to -30 dBmO
= -40 dBmO
= -45 dBmO
=0 V
Fig_ 1 Equivalent Circuit During Sampling
CODEC
SAMPLE
SOURCE
20 GATE
RESISTANceF RESISTANCE
~3k
Fig. 2
L.
~5k
1
150 PFi
Transmitter Section Timing
2.4 V
1.4 V
•
PCM OAT A PRESENT
Note
All rise and fall times are measured from 0.4 V and 2.4 V. All delay
times are measured from 1.4 V.
8·23
~A5151
Fig. 3
Receiver Section Timing
24 V
14 V
Rev
SYNC
~A~N~A~L~O~G~O~U~T~P~U~T
--11.-
______________________________________________________________________________________________
\.
Note
All rise and fall times are measured from 0.4 V and 2.4 V. All delay
times are measured from 1.4 V
Fig.4
SID Ratio
VB
Fig. 5
Input Level
Gain Tracking Performance
80
.."
70
+3
r-L r-
I 60
Z
g 50
II:
o
t;
is
~
....
42 40
42
40
40
313
3
~ 2C I-
.
i~SlSlr-r-
CHANNEL BANK
Z
+3 0
-10
-20
-30
INPUT LEVEL -
1 -05
;;
2jl:;;I-~_
"
SPECIFICATIONS
0
----..bF!!~~i~
(J
II:
I-
~ ~3
1-03
+1
1 +05
Z
34
30
u;
";;
-2
~~~NNEl BANIK
-01
-0.1_
~1;\1
5151-
)
SPjC'F'iAT'OjS
-3
-3
-40
-so
4
-60
+10
dBmO
-10
-20
-30
INPUT LEVEL -
8-24
-40
-so
dBmO
I
-60
-70
,uA5151
Fig.6
AID, DIA Conversion Timing
~~~-------------------------------------------125"'------------------------------------.'l~
-t=~::_2~\.-_----
_____--Jl"""--
SAMPLE AND HOLD
SAMPLE TIME
"" 32 MASTER CLOCKS
ENABLE SAR
SAR REQUIRES
"" 128 MASTER CLOCKS
--------------~/
SAR
CONTINUES
RCVSYNC
------------------------------~I
Fig. 7
Data InputlOutput Timing
Ir- 200 ns-,. --
XMIT
INTERNAL
CLOCK
I
Fig. 8
ANALOG OUTPUT UPDATED
AID Converter (wLaw Encoder)
Transfer Characteristic
10000000
10001111
10011111
10101111
10111111
'1001111
11011111
REQUIRED FOR DATA TO TRANSFER
FROM MASTER TO SLAVE
.,I~
IL
.....
.L.
l-
E11111111 l11101111
\KVALID DATA
_ _-..,._--J
........l
--"-'I
~_
-200"$
r----'
..J
~
REQUIRED TO TRANSFER DATA
FROM MASTER TO SLAVE
a
==~rl--~---===~==~
1....--50
is
ns REQUIRED TO LOAD MASTER
01111111
01101111
01011111
01001111
00111111
00101111
00011111
00001111
OOOOOOXX
VALID INCOMING DATA
-YREF
-0.5 VREF
YIN -
Signalling = 1.XX = 01
Signalling = O.XX = 10
No Signalling, XX = 10
5151
DIGITAL
OUT
XMIT SYNC
XMIT CLOCK
DIGITALIN
RCV SYNC
RCV CLOCK
8-25
+0.5 VREF
ANALOG INPUT -
V
+VAEF
,uA5151
Fig. g
D / A Converter (wLaw Decoder)
Transfer Characteristic
+VREFt-H-t-t-+++++-hH-t-t-+-i
~
+0 5 VAEF
.
t-H-t-t-+++++-hH-t-tJ4 -l
!:;
....
:::>
o
9
V
~ -0.5 VREFhf-V+++-+-H-+-+-+++++-H
I
-VREFf-hHH-t-+++++-hHH-t-l
DIGITAL INPUTS
Signalling = LXX = 01
Signalling
o.XX
10
No Signalling
XX
10
=
Fig. 10
=
=
=
64 kHz Operation, Transmitter Section Timing
~1~'-------------------------------------------125pS'----------------------------------------'"i~1
XMITI~------------~U~
::::J
-1 r'~~~~~
(MIN)
f----PWClk
~------------------------------yr------------------------------------PCM DATA PRESENT
Note
All nse and fall times are measured from 0.4 V and 2.4 V All delay
times are measured from 1.4 V.
8-26
,uA5151
Fig. 11
64 kHz Operation, Receiver Section Timing
fool·I----------------'25"·----------------.j~1
Ui---
~
!
17 MASTER
CLOCK PERIODS-,
(MIN)
~
Note
All rise and fall times are measured from 0.4 V and 2.4 V. All delay
times are measured from 1.4 V.
Fig. 12
AlB Select Timing
--------,
,..----------
lc..
~
TIME SLOT 2'
:~S:::.-
XMITSYNC
Y_ _ _ _ _ _T:E~::'" _ _ _ _
-
1.'·--------------,L
Y
RCV SYNC
TIME SLOT'
I~
XMIT
CLOCK
AlB SELECT (XMIT)
AlB SELECT (RCV)
1.4 V
_'A/9'-1
"oo_~ b=
'_'_YJ~
_A_/B_'N____________J)lr;-.-Y-----------
_A_S_'G_N_A_L_O_U_T_O_R_B_S_'_G_NA_L_O_UT
____________
8-27
JLA5151
Fig. 13
Signalling Timing Requirements for
Performance Evaluation
2. RCV SYNC is tied to XMIT SYNC.
3. XMIT Clock is tied to Master Clock. The signal is
inverted and tied to RCV Clock.
Rev SYNC
6
12
6
12
I IIIIIIIII II I II I III II IIII
The following timing signals are required:
1. Master Clock = 1.544 MHz
2. XMIT SYNC repetition rate = 8 kHz
3. XMIT SYNC width
8 Master Clock periods
(XMIT)
AlB SELECT (RCV)
=
I
Additional timing signals are shown in Figure 13.
A SIGNAL IN
When all the above requirements are met, the set-up
of Figure 14 permits the measurement of synchronous
system performance over a wide range of Analog
Inputs. The data register and ideal decoder provide a
means of checking the encoder portion of the 5151
independently of the decoder section. To test the
system in the asynchronous mode, Master Clock
should be separated from XMIT Clock and from RCV
Clock; XMIT Clock and RCV Clock are separated also.
B SIGNAL IN
Performance Evaluation
The equipment connections shown in Figure 14 can be
used to evaluate the performance of the 5151. An
Analog signal provided by the HP3551A Transmission
Test Set is connected to the Analog Input (Pin 20) of
the 5151. The Digital Output of the codec is tied back
to the Digital Input, and the Analog Output is fed
through a low-pass filter to the HP3551 A. Remaining
pins of the 5151 are connected as follow$:
1. AlB SEL (RCV) is tied to AlB SEL (XMIT).
Fig. 14
Some experimental results obtained with the 5151 are
shown in Figures 4 and 5. In each case, both the
measured results and the corresponding 03 Channel
Bank specifications are shown. The 5151 exceeds the
requirements for Signal-to-Distortion ratio (Figure 4)
and for Gain Tracking (Figure 5).
System Characteristics
Test Configuration
1"-
-------1
I
1.004 kHZ':
SIGNAL
SOURCE
I
I
.!!..
20
DIGITAL
DIGITAL
INPUT
1
INPUT
ANALOG
OUTPUT
I
I
I
,.
SYSTEM
5151
I
I
I
IL _ _ _ _ _ -,
I
~
(NOTE)
ANALOG
I
NOUT
IDEAL
DECODER
DATA
REGISTER
OUTPUT
I
I
1.004 kHz
1
I
NOTCH
FILTER
------------
3551A
SOUT
FiLTER
I
I
_..J
+ NOUT
Note
The ideal decoder consists of a digital decompander and a
13-bit precision DAC.
8-28
\
JODER
ONLY
J.lA5156
A-Law Companding
Codec
FAIRCHIL.D
A Schlumberger Company
Telecommunication Products
Description
The 5156 is a monolithic CMOS Companding Codec
which contains two sections: (1) an analog-to-digital
converter which has a transfer characteristic
conforming to the standard A-Law companding code,
and (2) a digital-to-analog converter which also
conforms to the A-Law code.
Connection Diagram
16-Pin DIP
ANALOG
INPUT
v+
VAEF(-)
14
ANALOG
13 GROUND
ANALOG
OUTPUT
12 DIGITAL
INPUT
11 DIGITAL
GROUND
10 RCV
CLOCK
9 RCV
SYNC
V-
These two sections form a coder-decoder which is
designed to meet the needs of the telecommunications industry for per-channel voice-frequency
codecs used in PCM systems. Digital input and output
are in serial format. Actual transmission and reception
of a-bit data words containing the analog information
is done at a 64 kb/s to 2.1 Mb/s rate with analog
signal sampling occurring at an a kHz rate. A SYNC
pulse input is provided for synchronizing transmission
and reception of multi-channel information being
multiplexed over a single transmission line.
NC
MASTER
CLOCK
XMIT 6
SYNC
XMIT 7
CLOCK
DIGITAL
OUTPUT
(Top View)
• EXCEEDS CCITT SPECIFICATIONS
• EVEN-ORDER BIT INVERSION DATA FORMAT
• LOW POWER DISSIPATION 30 mW TYPICAL
• SYNCHRONOUS/ASYNCHRONOUS OPERATION
• ON-CHIP S/H CIRCUIT
• ON-CHIP OFFSET NULL CIRCUIT
• SEPARATE ANALOG AND DIGITAL GROUNDS
• 64 kb/s TO 2.1 Mb/s SERIAL DATA RATE
• ±5 V POWER SUPPLY OPERATION
Order Information
Type
Package
~A5156
Ceramic DIP
~A5156
Ceramic DIP
(Side Brazed)
Code
Part No_
FW
~A5156DC
FB
I'A5156JC
•
Block Diagram
TRANSMIT (ENCODE)
1
CONTROL
RECEIVE (DECODE)
8-13
ANALOG
BIT
DIGITAL
COMPANDER
INPUT
DIGITAL
INPUT
DIGITAL
OUTPUT
5
TRANSMIT
CLOCK
TRANSMIT
SYNC
MASTER
CLOCK
Pin 4 = not connected
8-29
10
RECEIVE
CLOCK
9
RECEIVE
SYNC
JLA5156
Absolute Maximum Ratings (Note)
Supply Voltage (V+)
+6 V
Supply Voltage (V-)
-6 V
V- ~ VIN ~ V+
Analog Input Range
Digital Input Range
-0.5 V ~ VIN ~ V+
Reference Voltage
-0.5 V ~ VREF(+) ~ V+
VREF(+)
Reference Voltage
V- ~ VREF(-) ~ 0.5 V
VREF(-)
Operating Temperature
Range
O°C to 70°C
Storage Temperature
Range
-55°C to +125°C
Pin Temperature
(Soldering, 10 s)
260°C
Note
Stresses above those listed under "Absolute Maximum Ratings"
may cause permanent damage to the device. This IS a stress
rating only and functional operation of the device at these or any
other conditions beyond those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum ratong conditions for extended periods may affect
device reliability. Standard CMOS handling procedures should be
employed to avoid possible damage to device.
XMIT Clock, XMIT SYNC will determine when the first
positive edge of the Internal Clock will occur. In this
event, the hold time for the first clock pulse is
measured from the positive edge of XMIT SYNC.
Functional Description (Refer to Block Diagram)
Positive and Negative Reference Voltages
(VREF(+) and VREF(-) Pins 16 and 15)
These inputs provide the conversion references for
the digital-to-analog converters in the 5156. VREF(+)
and VREF(-) must maintain 100 ppMI °C regulation
over the operating temperature range. Variation of the
reference directly affects system gain.
RCV SYNC, Pin 9 (Refer to Figure 3 for the
Timing Diagram)
This input is synchronized with RCV Clock, and serial
data is clocked in by RCV Clock. Duration of the RCV
SYNC pulse is approximately eight RCV Clock
periods. The conversion from digital-to-analog starts
after the negative edge of RCV SYNC pulse (refer to
Figure 6). The negative edge of RCV SYNC should
occur before the 9th positive clock edge to insure that
only eight bits are clocked in. RCV SYNC must stay
LOW for 17 Master Clocks (minimum) before the next
digital word is to be received. (refer to Figure 11).
Analog Input, Pin 1
Voice-frequency analog signals which are bandwidthlimited to 4 kHz are input at this pin. Typically, they are
then sampled at an S kHz rate (Refer to Figure 6). The
analog input must remain between VREF(+) and
VREF(-) for accurate conversion.
Master Clock, Pin 5
This signal provides the basic timing and control
signals required for all internal conversions. It does
not have to be synchronized with RCV SYNC, RCV
Clock, XMIT SYNC or XMIT Clock and is not internally
related to them.
RCV Clock, Pin 10 (Refer to Figure 3 for
Timing Diagram)
The on-chip S-bit shift register for the 5156 is loaded
at the clock rate present on this pin. Clock rates of
64 kHz to 2.1 MHz can be used for RCV Clock. Valid
data should be applied to the digital input before the
positive edge of the internal clock (refer to Figure
This set-up time, trds, allows the data to be
transferred into the master of a master-slave flip-flop.
The positive edge of the Internal Clock transfers the
data to the slave of the master-slave flip-flop. A
hold time, trdh, is required to complete this transfer.
If the rising edge of RCV SYNC occurs after the first
rising edge of RCV Clock, RCV SYNC will determine
when the first positive edge of Internal Clock will
occur. In this event, the set-up and hold times for the
first clock pulse should be measured from the positive
edge of RCV SYNC.
n.
XMIT SYNC, Pin 6 (Refer to Figure 2 for the
Timing Diagram)
This input is synchronized with XMIT Clock. When
XMIT SYNC goes HIGH, the digital output is activated
and the AID conversion begins on the next positive
edge of Master Clock. The conversion by Master
Clock can be asynchronous with XMIT Clock. The
serial output data is clocked out by the positive edges
of XMIT Clock. The negative edge of XMIT SYNC
causes the digital output to become 3-state. XMIT
SYNC must go LOW for at least 1 master clock prior
to the transmission of the next digital word.
(Refer to Figure 10.)
Digital Output, Pin 8
The 5156 output register stores the 8-bit encoded
sample of the analog input. This 8-bit word is shifted
out under control of XMIT SYNC and XMIT Clock.
When XMIT SYNC is LOW, the Digital Output is an
open circuit. When XMIT SYNC is HIGH, the state of
the Digital Output is determined by the value of the
output bit in the serial shift register. The output is
composed of a sign bit, 3 chord bits, and 4 step bits.
The sign bit indicates the polarity of the Analog Input
XMIT Clock, Pin 7 (Refer to Figure 2 for the
Timing Diagram)
The on-Chip S-bit output shift register of the 5156 is
unloaded at the clock rate present on this pin. Clock
rates of 64 kHz to 2.1 MHz can be used for XMIT
Clock. The positive edge of the Internal Clock
transfers the data from the master to the slave of a
master-slave flip-flop (refer to Figure 7). If the positive
edge of XMIT SYNC occurs after the positive edge of
8·30
~A5156
Table 1
while the chord and step bits indicate the magnitude.
In the first two chords, the step bit has a value of 1.2
mY. In the third chord, the step bit has a value of 2.4
mY. This doubling of the step value continues for each
of the five successive chords.
1.
2.
3.
4.
5.
6.
7.
8.
Each chord has a specific value and the step bits,
16 in each chord, specify the displacement from that
value (refer to Table 1). Thus the output, which follows
the A-Law, has resolution that is proportional to the
input level rather than to full scale. This provides the
resolution of a 12-bit a / d converter at low input levels
and that of a 6-bit converter as the input approaches
full scale. The transfer characteristic of the a / d
converter (A-Law Encoder) is shown in Figure 8.
Digital Output Code: A-Law
Chord Code
Chord Value
Step Value
101
100
111
110
001
000
011
010
0.0 mV
20.1 mV
40.3 mV
80.6 mV
161.1 mV
332 mV
645 mV
1.289 V
1.221 mV
1.221 mV
2.44 mV
4.88 mV
9.77 mV
19.53 mV
39.1 mV
78.1 mV
Example:
1
110
Sign Bit Chor.d
Digital Input, Pin 12
The 5156 input register accepts the 8-bit encoded
analog value and loads it under control of RCV SYNC
and RCV Clock. The timing diagram is shown in
Figure 3. When RCV SYNC goes HIGH, the 5156 uses
RCV Clock to clock the serial data into its input
register. RCV SYNC goes LOW to indicate the end of
serial input data. The eight bits of the input data have
the same functions described for the Digital Output.
The transfer characteristic of the d / a converter
(A-Law Decoder) is shown in Figure 9.
0111 = +80.6 mV + (2 x 4.88 mY)
Step Bits
If the sign bit were zero, then both plus Signs would be
changed to minus signs.
Analog Output, Pin 13
The Analog Output is in the form of voltage steps
(100% duty cycle) having amplitude equal to the
analog sample which was encoded. This waveform
is then filtered with an external low-pass filter
with (sin x) / x correction to recreate the sampled
voice signal.
Operation of Codec With 64 kHz XMIT fRCV Clock
Frequencies
XMIT /RCV SYNC must not be allowed to remain at a
logic "1" state. XMIT SYNC is required to be at a logic
"a .. state for 1 master clock period (minimum) before
the next digital word is transmitted. RCV SYNC is
required to be at a logic "a .. state for 17 master clock
periods (minimum) before the next digital word is
received (refer to Figures 10 and 11).
Offset Null
The offset null feature of the 5156 eliminates
long-term drift errors and conversion errors due to
temperature changes by going through an offset
adjustment cycle before every conversion, thus
guaranteeing accurate a / d conversion for inputs
near ground. There is no offset adjust of the output
amplifier. Since the output is intended to be
ac-coupled to the external filter, the resultant dc error
(VOFFSET /0) will have no effect. The sign bit is not
used to null the Analog Input. Therefore, for an Analog
Input of a v, the sign bit will be stable.
8-31
J.LA5156
Electrical Operating Characteristics
Power Supply Requirements
Symbol
Characteristic
Min
Typ
Max
Unit
V+
V-
Positive Supply Voltage
4.75
-5.25
5.0
-5.0
5.25
-4.75
V
VREF(+)
Positive Reference Voltage (Note 1)
Negative Reference Voltage (Note 1)
2.5
-2.5
2.625
-2.375
V
VREFh)
2.375
-2.625
Max
Unit
Negative Supply Voltage
DC Characteristics
V+
V
V
= 5.0 V. V- = -5.0 v. VREF(+) = 2.5 v. VREF(-) = -2.5 V.
Min
Symbol
Characteristic
RINAS
Analog Input Resistance During
Sampling (Note 2)
RINANS
Analog Input Resistance Non-Sampling
CINA
Analog Input Capacitance
VOFFSETJI
Analog Input Offset Voltage
ROUTA
Analog Output Resistance
IOUTA
Analog Output Current
0.25
Typ
2
kO
100
150
MO
250
pF
±1
20
±8
50
0
0.5
mV
mA
±200
±850
mV
±0.1
±10
p.A
-0.25
-0.8
mA
8
±0.1
12
pF
±10
0.4
p.A
VOFFSET/O
Analog Output Offset Voltage
IlL
Logic Input LOW Current (V IN 0.8 V)
Digital Input. Clock Input. SYNC Input
(Note 3)
IIH
Logic Input HIGH Current (VIN
2.4 V)
Digital Input. Clock Input. SYNC Input
(Note 3)
COO
Digital Output Capacitance
IDOL
Digital Output Leakage Current
VOL
Digital Output LOW Voltage (Note 4)
VOH
Digital Output HIGH Voltage (Note 4)
1+
1-
Positive Supply Current
4
10
mA
Negative Supply Current
Positive Reference Current
6
20
mA
IREF+
2
4
p.A
IREF-
Negative Reference Current
4
20
p.A
=
=
3.9
8-32
V
V
~A5156
AC Characteristics
Refer to Figures 2 and 3.
Symbol
Characteristic
Min
Typ
Max
Unit
fm
Master Clock Frequency
1.5
2.048
2.1
MHz
fr, fx
RCV, XMIT Clock Frequency
0.064
2.048
2.1
MHz
PWclk
Clock Pulse Width (MASTER, XMIT, RCV)
200
trc , tfc
trs, tfs
tdlr, tdlf
ns
25% of
Clock Rise, Fall Time (MASTER, XMIT, RCV)
PWclk
SYNC Rise, Fall Time (XMIT, RCV)
PWclk
SYNC Pulse Width (XMIT RCV)
tps
SYNC Pulse Period (XMIT RCV)
ns
25% of
Data Input Rise, Fall Time
twsx , twsr
ns
25% of
PWclk
8
ns
fx(fr)
/.IS
125
/.IS
50% of
t xcs
XMIT Clock-to-XMIT SYNC Delay (Note 5)
t xcsn
XMIT Clock-to-XMIT SYNC
(Negative Edge) Delay
t xss
XMIT SYNC Set-Up Time
200
txdd
XMIT Data Delay (Note 4)
0
200
ns
txdp
XMIT Data Present (Note 4)
0
200
ns
txdt
XMIT Data Three State (Note 4)
150
ns
tdof
Digital Output Fall Time (Note 4)
tdor
Digital Output Rise Time (Note 4)
ns
tfc(trs)
ns
200
ns
50
ns
50
ns
50%
tsrc
RCV SYNC-to-RCV Clock Delay (Note 5)
trds
RCV Data Set-Up Time (Note 6)
50
ns
trdh
RCV Data Hold Time (Note 6)
200
ns
trcs
RCV Clock-to-RCV SYNC Delay
200
ns
trss
RCV SYNC Set-Up Time (Note 6)
200
tsao
RCV SYNC-to-Analog Output Delay
7
/.IS
Slew+
Analog Output Positive Slew Rate
1
V//.Is
Slew-
Analog Output Negative Slew Rate
1
V//.Is
Droop
Analog Output Droop Rate
25
/.IV//.Is
ns
trc(tfs)
ns
Notes
takes ptace, the user must sink the" 1" current untli reaching
the "0" level.
4. Driving one 74L or 74LS TTL load plus 30 pF with
and -VREF must be matched within ± 1% in order to
meet system requirements.
2. Sampling is accomplished by charging the internal capacitor to
within 1/2 LSB (~ 300 !LV) in 20 !LS. Therefore, the external
source resistance must be 3 kf! or less. The equivalent circuit
during sampling is shown in Figure 1.
3. The 5156 will source current through an internal 6 kf! resistor
to help pull up the TTL output. When a transition from" 1" to "0"
1. +VREF
IOH = -100 !LA, IOL = 500 !LA.
5. This delay is necessary to avoid overlapping Clock and SYNC.
6. The first bit of data is loaded when SYNC and Clock are both
" 1" during bit time 1 as shown on ReV timing diagram.
8·33
J.LA5156
System Characteristics
Refer to Figures 4 and 5
Symbol
Characteristic
Min
Typ
SID
Signal-to-Distortion
35
29
24
39
34
29
GT
Gain Tracking
±0.1
±0.1
±0.2
±0.4
±O.S
±2.5
dB
dB
dB
NIC
TLP
Idle Channel Noise
-SO
-72
dBmO
= 0 to -30 dBmO
= -40 dBmO
= -45 dBmO
Analog Input = +3 to -40 dBmO
Analog Input = -40 to -50 dBmO
Analog Input = -5f) to -55 dBmO
Analog Input = 0 V
Transmission Level Point
+4
dBm
soon
Fig. 1
Max
Equivalent Circuit During Sampling
co DEC
SAMPLE
SOURCE
1 GATE
RESISTANCE
RESISTANCE
r
~3k
~
~5k
150
Fig. 2
T
PFI
Transmitter Section Timing
2.4 V
1.4 V
PCM DATA PRESENT
Note
All rise and fall times are measured from 0.4 V and 2.4 V. All delay
times are measured from 1.4 V.
8·34
Unit
Condition
dB
dB
dB
Analog Input
Analog Input
Analog Input
~A5156
Fig. 3
Receiver Section Timing
~~
~
~~~--------------------------------~~
Note
All rise and fall times are measured from 0.4 V and 2.4 V. All delay
times are measured from 1.4 V.
Fig. 4
SID Ratio
Input Level
V8
Fig. 5
Gain Tracking Performance
80
..
i
z
o
70
+3
60
~
I
j: 50
co:
o
~40
Q
.e...
42 40
42
4
3t:<~156_~
;3
34
30
3
:c
i7i'-,<3
~ 20
iii
CCITT
SPECIFICATIONS
0
+3 0
-10
-20
-30
+j)5
"z
~(_.o!'t~ -0.1
or
.::B 0 ~
-0.5
z
22f-~-
"
-1
celTT
-2
+1
-01_
"'":;;.l;\"i
-1 ~-5156-
SJECIFI~ATIJNS
-3
-3
-40
-50
-,+10
-60
INPUT LEVEL - dBmO
-10
-20
-30
-40
-50
INPUT LEVEL - dBmO
8-35
I
I
-60
-70
JLA5156
Fig. 6
A/D, 0/ A Conversion Timing
t;=====~'----------------------------------------------125".------------------------------------~"1
-t-=~~:-2~1....-------------I)'SAMPLE AND HOLD
SAMPLE TIME
• 32 MASTER CLOCKS
~------------------------------·80".--------------------~
ENABLE SAR
SAR REQUIRES
SAR
CONTINUES
. 128 MASTER CLOCKS
--------------~/
RCV SYNC
------------------------------~I
Fig.7
Data Input/Output Timing
I 200 ns~
r- --
XMIT
INTERNAL
CLOCK
J
Fig.8
ANALOG OUTPUT UPDATED
A/D Converter (A-Law Encoder) Transfer
Characteristic
,,-
10101010
10100101
10110101
10000101
REQUIRED FOR DATA TO TRANSFER
FROM MASTER TO SLAVE
10010101
11100101
11110101
'101010111100 0101
\VVALIDDATA
~I
----...,
___ 200 ns
~.
01010101 i 0100 0101
REQUIRED TO TRANSFER DATA
FROM MASTER TO SLAVE
01110101
01100101
==~~I--~--~==~~~
00010101
00000101
1.....--50 ns REQUIRED TO LOAD MASTER
00110101
00100101
00101010
VALID INCOMING DATA
- VREF
"
+0.5 VREF
0.5 VREF
+VREF
ANALOG INPUT
Fig.9
~A5156
0/ A Converter (A-Law Decoder) Transfer
Characteristic
DIGITAL
OUT
+VREFH,,-+-I-++++-+-H,-+-I--i
XMIT SYNC
XMIT CLOCK
..
~
+0.5 VREFHH-t-+-+++++-t-H-t-+-'I'.,
~
o
DIGITAL IN
"
o
i
Rev SYNC
Rev CLOCK
-0.5
VREFHH,-+-I-++++-+-H,-+-I--I
II
-VAEFH,,-+-I-++++-+-HH-+-I--I
00
°1°
00
o~
DIGITAL INPUTS
8·36
ILA5156
Fig. 10 64 kHz Operation, Transmitter Section Timing
~14::::::::::::::::::::::::::::::::::::::::~_1_25_"_.::::::::::::::::::::::::::::::::::::~~.~I_________
U
I
:::J
XMIT
1 r-1~~~~~
J.---PWClk
(MIN)
~----------------------------~yr------------------------------------~
3-STATE
PCM DATA PRESENT
Note
All nse and fall times are measured from 0.4 V and 2 4 V. All delay
times are measured from 1.4 V.
Fig. 11
64 kHz Operation, Receiver Section Timing
1-o14~-------______125"· ____----------~·1
Ur---
::J
17 MASTER
I
CLOCK PERIODS-+j
~
(MIN)
•
Note
All nse and fall times are measured from 0.4 V and 2.4 V. All delay
limes are measured from 1 4 V.
8-37
~A5156
Performance Evaluation
The equipment connections shown in Figure 12 can be
used to evaluate the performance of the 5156. An
analog signal provided by the HP3552A Transmission
Test Set is connected to the Analog Input (Pin 1) of
the 5156. The Digital Output of the codec is tied back
to the Digital Input and the Analog Output is fed
through a low-pass filter to the HP3552A. Remaining
pins of the 5156 are connected as follows:
1. RCV SYNC is tied to XMIT SYNC.
2. XMIT Clock is tied to Master Clock. The signal is
inverted and tied to RCV Clock.
When all the above requirements are met, the set-up
of Figure 12 permits the measurement of synchronous
system performance over a wide range of Analog
Inputs. The data register and ideal decoder provide a
means of checking the encoder portion of the 5156
independently of the decoder section. To test the
system in the asynchronous mode, Master Clock
should be separated from XMIT Clock and from RCV
Clock; XMIT Clock and RCV Clock are separated also.
The following timing signals are required:
1. Master Clock
2.048 MHz
2. XMIT SYNC repetition rate
8 kHz
3. XMIT SYNC width
8 XMIT Clock periods
=
=
Fig_ 12
=
System Characteristics Test Configuration
r-
----'---1
I
800 Hz
SIGNAL
SOURCE
I
I
.£..
1
DIGITAL
DIGITAL 8
INPUT
OUTPUT
ANALOG
OUTPUT
I
13
SYSTEM
5156
I
I
I
I
L _ _ _ _ _ ....,
I
NOUT
I
HP
---i
DECODER
(NOTE)
ANALOG
INPUT
I
I
I
I
I
IDEAL
DATA
REGISTER
I
I
800 Hz
NOTCH
FILTER
I
FILTER
L_ 3551A
-----------SOUT
I
I
_...J
+ Hour
Note
The ideal decoder consists of a digital decompander and a 13-bit
precision DAC.
8-38
JODER
ONLY
FAIRCHILO
A Schlumberger Company
,
'
,
Volltscle Regulaie>rs
HybridVohage Reg ..lators,'
C"
'
"
"',
(",,.
,
,Operational' Amplifiers
Cdmparators "
0... Acquisition', '
,Telecommunications
Special Functions
HiRe! Processing
,Fairchild Sales Offices '
9-2
~A555
FAIRCHILO
Single Timing Circuit
A Schlumberger Company
Special Function Products
Description
The ~A555 Timing Circuit is a very stable controller for
producing accurate time delays or oscillations. In the
time delay mode, the delay time is precisely controlled
by one external resistor and one capacitor; in the
oscillator mode, the frequency and duty cycle are both
accurately controlled with two external resistors and
one capacitor. By applying a trigger signal, the timing
cycle is started and an internal flip-flop is set,
immunizing the circuit from any further trigger signals.
To interrupt the timing cycle a reset signal is applied
ending the time-out.
Connection Diagrams
a-Pin DIP
GND
Vee
TRIGGER
DISCHARGE
THRESHOLD
OUT
CONTROL
VOL TAGE
RESET
The output, which is capable of sinking or sourcing
200 rnA, is compatible with TTL circuits and can drive
relays or indicator lamps.
•
•
•
•
•
•
•
•
(Top View)
Order Information
Type
Package
~A555
Molded DIP
TIMING CONTROL, NS TO HOURS
ASTABLE OR MONOSTABLE OPERATING MODES
ADJUSTABLE DUTY CYCLE
200 mA SINK OR SOURCE OUTPUT CURRENT
TTL OUTPUT DRIVE CAPABILITY
TEMPERATURE STABILITY OF 0.005% PER °C
NORMALLY ON OR NORMALLY OFF OUTPUT
DIRECT REPLACEMENT FOR SE555/NE555
Code
9T
Part No.
~A555TC
Block Diagram
~_-------------l
Vee5 kll
DISCHARGE
THRESHOLD"""T-+---I
CONTROL
VOLTAGE
R
FLIP-FLOP
5 kll
TRIGGER
-+-+--1
Q
5 INHIBIT/
RESET
Vee
__.__--.- OUTPUT
I
I
I
5 kll
I
r
RESET~----------------~
L-
I
I
------------1
9-3
•
p,A555
JLA555
Electrical Characteristics
Characteristic
TA = 25°C, Vee = +5.0 V to +15 V, unless otherwise specified
Min
Condition
Supply Voltage
Supply Current
Timing Error
Initial Accuracy
Drift with Temperature
mA
mA
10
15
RA, RS = 1 kQ to 100 kQ
1.0
%
50
ppm/oC
C = 0.1 JLF (Note 2)
0.1
%V
2/3
X Vee
Vee = 15 V
5.0
V
Vee = 5.0 V
1.67
V
0.5
0.4
Reset Voltage
0.7
JLA
1.0
0.1
Reset Current
Output Voltage Drop (LOW)
V
3.0
Trigger Current
Control Voltage Level
Unit
16
Vcc = 5.0 V, RL = cc
Vee=15V,RL=CC
LOW State (Note 1)
Threshold Voltage
Threshold Current
Max
6.0
Drift with Supply Voltage
Trigger Voltage
Typ
4.5
0.1
0.25
JLA
Vee = 15 V
9.0
10
11
V
Vee = 5.0 V
2.6
Note 3
3.33
4.0
V
Vee = 15 V, ISINK = 10 mA
0.1
0.25
V
ISINK = 50 mA
0.4
0.75
V
ISINK = 100 mA
2.0
2.5
V
ISINK = 200 mA
2.5
V
V
Vee = 5.0 V, ISINK = 8.0 mA
Output Voltage Drop (HIGH)
V
mA
ISINK = 5.0 mA
0.25
ISOUReE = 200 mA, Vee = 15 V
12.5
0.35
V
V
ISOURCE = 100 mA, Vcc = 15 V
12.75
13.3
V
Vee = 5.0 V
2.75
3.3
V
Rise Time of Output
100
ns
Fall Time of Output
100
ns
Notes
1. Supply Current is typically 1.0 rnA less when output is HIGH.
2. Tested at VCC = 5.0 V and VCC = 15 V.
3. This will determine the maximum value of RA + RS' For
15 V operation, the maximum total R = 20 MG.
4. For operating at elevated temperatures, the device must
be derated based on a + 125°C maximum junction
temperature and a thermal resistance of + 150 0 C/W
JunctIOn to ambient
9·4
ILA555
Absolute Maximum Ratings
Supply Voltage
Power Dissipation (Note 1)
Operating Temperature Range
Storage Temperature Range
Pin Temperature (Soldering, 10 s)
+18 V
600 mW
O°C to +70°C
-65°C to +150°C
260°C
Equivalent Circuit
FM
VCC~B
__
~
________
~
____________
~
__
~
________- .________
R4
1 k
~
__- .______- .____
RB
5 k
~
____
~
____- ,
R12
6B k
THRESHOLD 6
OUTPUT
TRIGGER
-=-------------+------_C"
_C"
-=-
RESET ...;4~______
DISCHARGE -'-------,
R5
10 k
R6
100 k
R7
R10
5k
100 k
GND~1______~___+~--------~--~~--~-------4--------~--~-------J
•
Note
1. Supply Current is typically 1.0 rnA less when output is HIGH.
9-5
ILA555
Typical Performance Curves
Minimum Pulse Width
Required for Triggering
Total Supply Current vs
Supply Voltage
150
10
~ 125
c 80
1
Q
~
50
i
25
'z"
. ,.",.
I...~
.....
o
o
~
$-~
~
il'"> 4.0
~
.,." 100e
01
02
V
./
t5
12
TA = 25 C
Q
0
/
c
5
~ 0,4
"0" t-s VIVI" 11' v
o
15
10
10
V
Vee'" 15 V
~
5.0
.
110
50
g
TA = 25°C
......-
SINK CURRENT -
> 1005
~
Q
~ 100 0
,
TA == 2S C
Q
,/"
V
50
10
100
10
mA
50
10
SINK CURRENT -
Delay Time vs
Ambient Temperature
50
100
mA
Propagation Delay vs
Voltage Level of Trigger Pulse
1015
250 f--t-+---1---1-+-t--I-+-l
1010
1.010
~
5.0
mA
'015
~
"5
.. 0 1
o
SINK CURRENT -
Delay Time vs Supply Voltage
...
V
00 1
0.01
1.0
100
J
"~
"~ 01
10
I
>
10
o
0.01
1.0
100
mA
Low Output Voltage vs
Output Sink Current
~
o
50
10
10
...
/'
50
SOURCE CUARENT -
g
o. 1
25°C
o
>
~
=
> 06
Vee'" 10 V
i-""
TA
!::j 08
Low Output Voltage vs
Output Sink Current
>
~
14
10
~
::;
16
~ 10
SUPPLY VOLTAGE -
o
~~
~
.g
~
5.0
Yee '" 5 V
1
,/
o
0
. ,.
> 18
V
x Vee - LOWEST VOLTAGE LEVEL
OF TRIGGER PULSE
Low Output Voltage vs
Output Sink Current
20
/'
2.0
0.'
0.3
V
1/
./
~60
i
75
T1=2~OC V /'
E
j!: 100
~
~
High Output Voltage vs
Output Source Current
-
\
\
~
~
099
1005
~~r--
~~
1000
--
r-
r--
0995
'"oz
0990
,
o
~ 150
~
:100~~~~~-~-~-+-+-~
o
if
0.990
098
~ 200 f---+-+~~,-+-~'-t-+-t
oj
50
0985
10
SUPPLY VOLTAGE -
15
V
20
-50
-25
0
25
50
7S
100
AMBIENT TEMPERATURE _ DC
9-6
125
x Vee - LOWEST VOLTAGE LEVEL
OF TRIGGER PULSE
,uA555
Typical Applications
Monostable Operation
In the monostable mode, the timer functions as a oneshot. Referring to Figure 1 the external capacitor is
initially held discharged by a transistor inside
the timer.
capacitor and causes the cycle to start over. The
timing cycle now starts on the positive edge of the
reset pulse. During the time the reset pulse is applied,
the output is driven to its LOW state.
When a negative trigger pulse is applied to pin 2,
the flip-flop is set, releasing the short circuit
across the external capacitor and driving the output
HIGH. The voltage across the capacitor increases
R 1C 1. When
exponentially with the time constant T
the voltage across the capacitor equals % Vee, the
comparator resets the flip-flop which then discharges
the capacitor rapidly and drives the output to its LOW
state. Figure 2 shows the actual waveforms generated
in this mode of operation.
The circuit triggers on a negative-going input signal
when the level reaches l1! Vee. Once triggered, the
circuit remains in this state until the set time has
elapsed, even if it is triggered again during this
interval. The duration of the output HIGH state is given
by t = 1.1 R 1C 1 and is easily determined by Figure 3.
Notice that since the charge rate and the threshold
level of the comparator are both directly proportional
to supply voltage, the timing interval is independent of
supply. Applying a negative pulse simultaneously to
the Reset terminal (pin 4) and the Trigger terminal
(pin 2) during the timing cycle discharges the external
=
When Reset is not used, it should be tied high to avoid
any possibility of false triggering.
Fig_ 1
+Vee
~
5 TO 15 V - - - - - - - - r - - - - - - ,
Rl
RESET---
TRIGGER----oJ
~A555
OUTPUT - - - - o J
r
Fig. 2
Fig.3
CONTROL
VOLTAGE
001 }.IF
Time Delay vs R1 and C1
•
1= 01 ms/DIV
!!:!.."'fL:il v~_ - n h
I
I
I
"i
~ 1.0
o
Z
;!
~ 01
OUTPUT YOLTAGE = 5.0 V/OIV
J
J
V
/
10- ',...l
-
CAPACITOR VOLTAGE
R1
=
I I
~
~
o 01
/
I+--+';---b'<--+>"'--I~-+---j
...J L_ i,J
2.0 VlDIY
TIME DELAY
91 kH, C1 = 001 }18
~ 16
~
V
0
o
>
I;;
_10QC
~
2
~
50
o
01
x Vee -
02
03
5.0
04
10
SUPPLY VOLTAGE -
LOWEST VOLTAGE LEVEL
OF TRIGGER PULSE
Low Output Voltage
Output Sink Current
"00
5 V
Vee
/ --
TA '" 25°C
I
w 10
~
=
10 V
>
>
~ 10r-~~~-r---r---r-r~r--1
w
~
TA
~25°C
50
10
50
TA = 25°C
/"'
o
OO~~0--~~~5~0--~10~~--~~570--7.'00
100
(
~
I;;
0.0 1
I;;
V
o
SINK CURRENT -
mA
Delay Time vs
Supply Voltage
00 1
10
300
'010
101 0
250
;;j
\
-
I-
r--
100 5
--
1000
099 5
~ 0995
~
---- - --
098 5
0985
10
SUPPLY VOLTAGE -
15
Y
20
-so
~
o
0
25
50
75
100
AMBIENT TEMPERATURE _ °C
9·12
100
I)
200
T'-O·~V
f-T,
~ 150
125
0
25·C
~
::'00
" ~v
~
'/
<
o
g;
o
-25
50
mA
I
50
099 0
0.990
10
Propagation Delay vs
Voltage Level of Trigger Pulse
101 5
\
/
SINK CURRENT -
Delay Time vs
Ambient Temperature
w
50
mA
1015
1000
100
J
"<~
~01r-~r-~~~~~---r-r-rr--1
-""
SINK CURRENT -
~
50
rnA
I 10
"~
,,/
00 1
10
~
10
Vee = 15 V
>
>- 1.005
50
Low Output Voltage vs
Output Sink Current
o
~
I-
::s
:!l
I' vr 11' v
10
Vee
'"
5 V
SOURCE CURRENT -
10
o
4
V
Low Output Voltage vs
Output Sink Current
VB
25°C
•
0
10
15
=
06
00 2
o
o
"~ 01
o"
1
TA
4
~1
~ 0
V
k::::: ~"-
1
trl
o
01
02
03
x Yee - lOWEST VOLTAGE LEVEL
OF TRIGGER PULSE
0.4
p,A556
Typical Applications
Monostable Operation
In the monostable mode, the timer functions as a
one-shot. Referring to Figure 1 the external capacitor
is initially held discharged by a transistor inside
the timer.
circuit remains in this state until the set time has
elapsed, even if it is triggered again during this
interval. The duration of the output HIGH state is given
by t = 1.1 R 1C 1 and is easily determined by Figure 3.
Notice that since the charge rate and the threshold
level of the comparator are both directly proportional
to supply voltage, the timing interval is independent of
supply. Applying a negative pulse simultaneously to
the Reset terminal (pin 4) and the Trigger terminal
(pin 6) during the timing cycle discharges the external
capacitor and causes the cycle to start over. The
timing cycle now starts on the positive edge of the
reset pulse. During the time the reset pulse is applied,
the output is driven to its LOW state.
When a negative trigger pulse is applied to pin 6, the
flip-flop is set, releasing the short circuit across the
external capacitor and drives the output HIGH. The
voltage across the capacitor, increases exponentially
with the time constant T = R 1C 1. When the voltage
across the capacitor equals 2/3 Vee, the comparator
resets the flip-flop which then discharges the
capacitor rapidly and drives the output to its LOW
state. Figure 2 shows the actual waveforms generated
in this mode of operation.
When Reset is not used, it should be tied high to avoid
any possibility of false triggering.
The circuit triggers on a negative-going input signal
when the level reaches 1/3 Vee. Once triggered, the
Fig. 1
+vcc
~ 5 TO 15 V ---------~----__.,
RESET---
4
R1
14
TRIGGER - - - 0 1
1/2 556
OUTPUT - - - 0 1 5
2
3
7
Fig. 2
I
CONTROL
VOLTAGE
0.Q1 "F
Fig. 3
t == Q1 mS/DIV
~".!-:lV~r-
l
h - I--11
l U
101--+-+--t7''--f7'''-+r--I
1.0
OUTPUT VOLTAGE'" 5.0 Y/DIV
J
'/
J
V
V1
I--
W
-
CAPACITOR VOLTAGE
..J
0.1
J
0.01 f7"--+r-~'---V---Ir--+--I
..... ..J
2.0 VlDIV
A1 '" 9 1 kll. C1 == 0.01 .... F, AL '" 1.0 kJl
TIME DELAY
9-13
•
JLA556
Typical Applications (Cont.)
Astable Operation
When the circuit is connected as shown in Figure 4
(pins 2 and 6 connected) it triggers itself and free runs
as a multivibrator. The external capacitor charges
through R1 and R2 and discharges through R2 only.
Thus the duty cycle may be precisely set by the ratio
of these two resistors.
and the discharge time (output LOW) by:
In the astable mode of operation, C 1 charges and
discharges between 1 / 3 Vee and 2/3 Vee. As in the
triggered mode, the charge and discharge times and
therefore frequency are independent of the
supply voltage.
The frequency of oscillation is then:
1
1.44
f = T = (R 1 + 2R2) C 1
Figure 5 shows actual waveforms generated in this
mode of operation.
The duty cycle is given by:
R2
0= R1 + 2R2
t2 = 0.693 (R2) C1
Thus the total period T is given by:
T = t1
and may be easily found by Figure 6.
The charge time (output HIGH) is given by:
t1 = 0.693 (R1
+ t2 = 0.693 (R1 + 2R2) C1
+ R2) C1
Fig. 4
+vcc
~
5 TO 15 V
Rl
1
14
4
5
OUTPUT
1
1/2556
co NTROL
vo
~.~~:~
r
I
-
R2
2
3
7
6
I
1
Cl
Fig. 6 Free Running Frequency vs
R1, R2 and C1
Fig. 5
1- 05 mS/OIV
outu) VOJAai ~ t vtv
...,
~,.~~~---t\~~---1~-+-4
I I I I
I 1\ V \; /
CAPACITOR VOLTAGE
,. ~-P~---t\;--~---1--+--l
u
!
~
.,
\, V \; V
~
1.0 VlDIV
FREE RUNNING FREQUENCY -
R1 '" A2 '" 4.' kfl, Cl '" 0 1 pf. RL '" 1 kn
9-14
Hz
f.lA726
F=AIRCHILO
Temperature-Controlled
Differential Pair
A Schlumberger Company
Special Function Products
Connection Diagram
10-Pin Metal Package
Description
The /LA726 is a Monolithic Transistor Pair in a high
thermal-resistant package, held at a constant
temperature by active temperature regulator circuitry.
The transistor pair displays the excellent matching,
close thermal coupling and fast thermal response
inherent in monolithic construction. The high gain and
low standby dissipation of the regulator circuit permits
tight temperature control over a wide range of ambient
temperatures. It is intended for use as an input stage
in very-low-drift dc amplifiers, replacing complex
chopper-stabilized amplifiers. It is also useful as the
nonlinear element in logarithmic amplifiers and
multipliers where the highly predictable exponential
relation between emitter-base voltage and collector
current is employed. The device is constructed on a
single silicon chip using the Fairchild Planar process.
Absolute Maximum Ratings
Operating Temperature Range
Military (/LA726)
Commercial (/LA726C)
Storage Temperature Range
Pin Temperature
( Soldering 60 s)
Supply Voltage
Internal Power Dissipation
E2
Bl
El
v(Top View)
Order Information
Type
Package
/LA726
Metal
/LA726C
Metal
Code
5U
5U
-55°C to +125°C
O°C to +85°C
-65°C to +150°C
300°C
± 18 V
500mW
Maximum Ratings for Each Transistor
Collector-to-Emitter Voltage,
VCEO
30 V
Collector-to-Base Voltage, VCBO 40 V
Collector-to-Substrate Voltage,
40 V
VCIO
Emitter-to-Base Voltage, VEBO
5V
Collector Current, IC
5 mA
~____~______~8~V+
Equivalent Circuit
TEMPADJ~6~--------~-------------------.----~
Rl
HIl
R2
21 kll
c134
Bl 2
Part No_
/LA726HM
/LA726HC
Dl
6.2 V
01
El 3
::~02
E2~
02
6.2 V
R3
4.8 kll
R4
2k1l
RS
lOll
~
__________
~
______
9-15
~
__________________
~~S~v_
•
J.LA726
",A726
Electrical Characteristics
Min:S TA:S Max, Vs =
± 15 V, Radj = 62 kn unless otherwise specified.
",A726
Characteristic
Condition
Input Offset Voltage
10 ",A :S Ic :S 100 ",A,
VCE = 5 V, Rs :S 50 n
",A726C
Typ
Max
Unit
1.0
3.0
mV
10
100
nA
50
400
nA
50
300
nA
500
250
1000
nA
0.3
6.0
0.3
6.0
mV
IC = 100 ",A, 5 V :S VCE :S 25 V,
Rs:S 10 kn
0.3
6.0
0.3
6.0
mV
Input Offset Voltage Drift
10 ",A :S Ic :S 100 ",A, VCE = 5 V,
Rs:S 50 n, +25OC :S TA :S Max
0.2
1.0
0.2
2.0
",V/oC
Input Offset Voltage Drift
10 ",A:S Ic :S 100 ",A, VCE = 5 V,
Rs :S 50 n, Min :S TA :S +25°C
0.2
1.0
0.2
2.0
",V/oC
Input Offset Current
Average Input Bias Current
Offset Voltage Change
Typ
Max
1.0
2.5
IC = 10 ",A, VCE = 5 V
10
50
IC = 100 ",A, VCE = 5 V
50
200
Ic = 10 ",A, VCE = 5 V
50
150
Ic = 100 ",A, VCE = 5 V
Ic = 10 ",A, 5 V :S VCE :S 25 V,
RS:S 100 kn
250
Min
Min
IC = 10 ",A, VCE = 5 V
10
10
pA/oC
IC = 100 ",A, VCE = 5 V
30
30
pA/oC
Supply Voltage
Rejection Ratio
10 ",A :S Ic :S 100 ",A, Rs :S 50 n
25
25
",V/V
Low Frequency Noise
Ic = 10 ",A, VeE =5V, RS:S 50 n
BW = .001 Hz to 0.1 Hz
4.0
4.0
",V pop
Broadband Noise
IC = 10 ",A, VeE = 5 V. RS:S 50 n
BW = 0.1 Hz to 10 kHz
10
10
",V pop
Long-term Drift
10 ",A :S Ie :S 100 ",A, VCE = 5 V,
Rs :S 50 n, TA = 25°C
5.0
5.0
",VI
week
High Frequency Current Gain
f=20 MHz,lc= 100 ",A, VCE = 5 V 1.5
3.5
Output Capacitance
IE = 0, Vce = 5 V
1.0
1.0
pF
Emitter Transition
Capacitance
IE
1.0
1.0
pF
Collector Saturation Voltage
Ie = 100 ",A, Ic = 1 mA
Input Offset Current Drift
= 100 ",A
1.5
0.5
3.5
1.0
0.5
Typical Performance Curves for ",A726
Current Gain as a
Function of
Collector Current
1000
Supply Current as a
Function of
Ambient Temperature
y~~ ~ s.oly
20
I III
=
800
.I
I
. .1.
Vs= ±15V_
RadJ =620
Vs= ±15V
RadJ
62kO
16
- 55°C:s; TA::S; + 125°C
600
400
",
V
V
12
"'"
t-...
"'
"
t-...
I"'
./
200
'100p.A
1 rnA
o
-60
10mA
20
20
60
TEMPERATURE _ °C
COLLECTOR CURRENT
9-16
r-...
100
140
1.0
V
JLA726
Typical Performance Curves for IlA726C (Cont.)
Supply Current as a
Function of
Ambient Temperature
Current Gain as a
Function of
Collector Current
1000
~CE ~
Vs
z
;;
..'"
=
±15V
RadJ :::: 75 kn
DOC ~ TA $ 85°C
800
600
10
5.0 ~ 1 1 1 _
-
8.0
0:
0:
400
::>
.
;'i
V
"
.......
" "'-
::>
"
i
4.0
::>
200
~
.........
~
L..-----15V
R7
75kn
R4
50n
C1
R8
5nF
1.5kn
R6
50kn
ALL RESISTORS 1 %
9·17
-15V
•
J.lA727
Temperature-Controlled
Differential Preamplifier
F=AIRCHILO
A Schlumberger Company
Special Function Products
Connection Diagram
10-Pin Metal Package
Description
The Ji,A727 is a monolithic, fixed gain, Differential
Input / Output Preamplifier, constructed with the
Fairchild Planar epitaxial process, mounted in a high
thermal resistance package, and held at constant
temperature by active regulator circuitry. The high
gain and low-standby dissipation of the regulator
circuit give tight temperature control over a wide
ambient temperature range. The device is intended for
use as a self-contained input stage in very low drift dc
amplifiers, replacing complex chopper-stabilized
amplifiers in such applications as thermo-couple
bridges, strain-gauge transducers, and
a / d converters.
•
•
•
FREQ COMP 1
..........-----+-"-<~ OUT 2
IN 2
IN 1
v(Top View)
VERY LOW OFFSET DRIFTS
HIGH INPUT IMPEDANCE 300 Mfl
WIDE COMMON MODE RANGE CMRR = 100 dB
Order Information
Type
Package
Ji,A727
Metal
Ji,A727C
Metal
Absolute Maximum Ratings
Operating Temperature Range
Military (Ji,A727)
-55°C to +125°C
Commercial (Ji,A727C)
-20°C to +85°C
Storage Temperature Range
-65°C to +150°C
Pin Temperature (Soldering, 60 s) 300°C
Internal Power Dissipation
500 mW
Supply Voltage
(Amplifier and Heater)
± 18 V
Differential Input Voltage
± 10 V
Common Mode Input Voltage
± 15 V
Code
5U
5U
Part No_
Ji,A727HM
Ji,A727HC
Equivalent Circuit
VA+
R2
21 kH
FREQ COMP 1
R1
1 kn
.22
300 Jl
,. --t---'lNV--1
D2
.3
48 kH
Q1. r-----fE--.::.:.:.-4::--=.::--~F'------...::::'_:31---'
••
10 kll
~------+--~--~-----~--+------+--~--~--~~
9-18
J-LA727
/LA727
Electrical Characteristics
-55°C:.5 TA:.5 +125°C, VH+
otherwise specified.
Characteristic
Condition
Input Offset Voltage
RS :.5 50 n
= +15 V, V- = -15 V, RADJ = 330 kn,
Min
unless
Typ
Max
Unit
2.0
10
mV
nA
Input Offset Current
2.5
15
Input Bias Current
12
40
nA
RS:.5 50 n, +25°C :.5 TA:.5 +125°C
0.6
1.5
/LV/oC
RS:.5 50 n, -55°C :.5 TA:.5 +25°C
0.6
1.5
/LV /oC
+25°C:.5 TA:.5 +125°C
2.0
pA/oC
-55°C :.5 TA:.5 +25°C
2.0
pA/oC
-55°C :.5 TA:.5 +125°C
15
pA/oC
Differential Input Resistance
300
Mn
Common-Mode Input Resistance
1000
Mn
Input Offset Voltage Drift
Input Offset Current Drift
Input Bias Current Drift
Input Voltage Range
±12
Supply Voltage Rejection Ratio
RS:.5 100 kn
Common-Mode Rejection Ratio
RS:.5 100 kn
80
Output Resistance
Output Common-Mode Voltage
-6.0
±13
V
80
/LV IV
100
dB
1.0
4.0
kn
-5.0
-4.0
V
Differential Output Voltage Swing
±5.0
±7.0
±10
V
Output Sink Current
10
30
80
/LA
5.0
10
/LV//LA
100
250
Differential Load Rejection
Differential Voltage Gain
60
= 10 Hz to 500 Hz, Rs :.5
Low Frequency Noise
BW
Long Term Drift
RS:.5 50 n
Amplifier Supply Current
TA
Heater Supply Current
TA
= +25°C
= +25°C
50 n
3.0
/LVrms
5.0
/LV /week
1.0
2.0
mA
10
15
mA
•
9-19
f.LA727
JlA727C
Electrical Characteristics
-20°C:::; TA:::; +85°C, VH+
otherwise specified.
= VA+ = +15 V, V- = -15 V, RADJ = 1 Mfl,
Characteristic
Condition
Min
Input Offset Voltage
Rs :::; 50 fl
unless
Typ
Max
Unit
2.0
10
mV
Input Offset Current
2.5
25
nA
Input Bias Current
12
75
nA
0.6
3.0
JlV 1°C
Input Offset Voltage Drift
RS:::; 50 fl
pA/oC
Input Offset Current Drift
2.0
Input Bias Current Drift
15
pA/oC
Differential Input Resistance
300
Mfl
Common Mode Input Resistance
1000
Mfl
±12
Input Voltage Range
Supply Voltage Rejection Ratio
Rs :::; 100 kfl
Common Mode Rejection Ratio
Rs:::; 100 kfl
70
± 13
V
80
JlV IV
100
Output Resistance
dB
1.0
4.0
kfl
V
Output Common Mode Voltage
-7.0
-5.0
-4.0
Differential Output Voltage Swing
±3.0
±7.0
±10
V
Output Sink Current
10
30
80
JlA
Differential Load Rejection
5.0
15
JlV I JlA
Differential Voltage Gain
100
250
50
Low Frequency Noise
BW
Long Term Drift
Amplifier Supply Current
TA
Heater Supply Current
= 10 Hz to 500 Hz, RS :::;
50 fl
3.0
JlVrms
Rs :::; 50 fl
5.0
JlV Iweek
= +25°C
TA = +25°C
1.0
2.0
mA
10
15
mA
Typical Performance Curves
Noise Voltage vs Frequency
10- 1
Noise Current vs Frequency
1 M
v; =I"JI) I
!
10 h
10 23
10 ,
10 '
H+t-H-H-++-+--++IH-+-tt++-1
10 24
16
100
1 k
FREQUENCY -
10 k
Hz
100 k
10-26
10
r--.
1k
"
100
100 k
10 k
......
10-25
"10
V
VS"'!15V
RADJ =- 330 kn
RADJ :; 330 k!!
10
Spot Noise Contours
,
1 k
FREOUENCY -
9·20
10 k
Hz
100 k
100
10
lA'1 II I
f
{
Vs = :!:15 Y
RAOJ "" 330 k! I
.d.± .....
I\,
"
......
• d.
10 dB
"
1~.
b
20 dB
i-
i
100
1k
FREQUENCY -
10 k
Hz
100 k
p,A727
Typical Performance Curves (Cont.)
Power Consumption vs
Ambient Temperature
Relative Chip Temperature vs
Ambient Temperature
Recommended RADJ
vs Maximum
Ambient Temperature
1000
2
8
1\
1
10
f-
I)
06
\
:
'0
30
'"
90
70
-
-
;!
"- I"-
;0
~ 200
Vs - 715 V
-60
130
-20
-00
·20
ac
AMBIENT TEMPERATURE _
C
>_i"""'
...
=0
68
-
IJ.A
-20
"
+20
+100
+140
AMBIENT TEMPERATURE-"C
Amplifier Current vs
Supply Voltage
IADJ '" 68
IADJ '" 68 iJ.A
.
".
>-
1
.
g
I-
o
o
,.
0
~ 12~~+-+-~-+-+~~~+-+-~-1
r--
'"'"
:J
r-- .......
,.,.
Z
o
I)
.......
oI)
..
ffi08~t-+-~-r-+-i~~t-+-~-r-1
r--
,.~
r-
l-
ii'
4
IJ.A
~ 16~+-+-~-+-+~r-~+-+-~-+-+
~
I)
"04~t-+-~-r-+-i~r-t-+-~-r-1
I-
:J
o
o
-10
9
10
11
12
13
14
SUPPLY VOLTAGE- ±V
Differential Voltage
Gain vs
Supply Voltage
.
ffi
""-
-10
z
~
;
Z
0400
I)
Output Common-Mode
Voltage vs
Supply Voltage
IAOJ
,.,.
o
:J
-10
20
o •
.,.
.
j: 600
o
110
~
1
z
...-r-
"-
o
-20
Input Common-Mode
Voltage Range vs
Supply Voltage
S
>
Y Y
~ ~ I--"
g
......
MAXIMUM AMBIENT TEMPERATURE -
." ,.
:!
.
" 12
-
z
~
I
02
~ 800
1
1'-1
>
l
RADJ ~ 330 kll
1M!!\
205 Mil
RAOJ
I-
\
:.
:J
RADJ ~
.'"
.
~
.z~
.
\
_, 14
~
20
v; ..:,v
--, 330 k!l
RADJ
+15 V
Vo
15
9
10
11
12
13
SUPPLY VOLTAGE -
14
15
Open Loop Frequency
Response for Various
Values of Compensation
0
VS~I~15V
I III 11111
NO COMPENSATION
1111
1 40
z
;;
11111
l1iN.
,
Required RADJ for Constant
IADJ vs Supply Voltage
I
I
I
IADJ '" 68 "A
u
~V
SUPPLY VOLTAGE -
~V
I;'"
".
.
S
.
"
l-
>
~
C1 = 005 I-'F, R1
0
2
=
20 k!l
I III IliN-.
I III
0
C1
~
1111
~I005
I-'F, R1 """ 0
~
'"~ -20
1i
-4 0
11
SUPPLY VOLTAGE -
-v
12
13
SUPPLY VOLTAGE -
9-21
14
-:!:.V
15
10
100
1 k
10k
FREQUENCY -
100 k
Hz
1 M
•
f.lA733
Differential Video
Amplifier
FAIRCHILO
A Sehlumberger Company
Linear Products
Description
The J.LA733 is a monolithic two-stage Differential Input,
Differential Output Video Amplifier constructed using
the Fairchild Planar epitaxial process. Internal
series-shunt feedback is used to obtain wide
bandwidth, low-phase distortion, and excellent gain
stability. Emitter follower outputs enable the device
to drive capacitive loads and all stages are
current-source biased to obtain high-power supply and
common-mode rejection ratios. It offers fixed gains of
10, 100 or 400 without external components, and
adjustable gains from 10 to 400 by the use of a single
external resistor. No external frequency compensation
components are required for any gain option. The
device is particularly useful in magnetic tape or disc
file systems using phase or NRZ encoding and in high
speed thin film or plated wire memories. Other
applications include general purpose video and pulse
amplifiers where wide bandwidth, low phase shift, and
excellent gain stability are required.
Connection Diagram
10-Pin Metal Package
•
•
•
•
Order Information
Type
Package
J.LA733
Metal
J.LA733C
Metal
G2A
GAIN SELECT
v+
G28
OUT 1
GAIN SELECT
v(Top View)
Note
Pm 5 connected to case
120 MHz BANDWIDTH
250 kQ INPUT RESISTANCE
SELECTABLE GAINS OF 10, 100, AND 400
NO FREQUENCY COMPENSATION REQUIRED
Absolute Maximum Ratings
Supply Voltage
Differential Input Voltage
Common Mode Input Voltage
Output Current
Internal Power Dissipation
(Note 1)
Metal Package
DIP
Operating Temperature Range
Military (IlA733)
Commercial (J.LA733C)
Storage Temperature Range
Pin Temperature (Soldering)
Metal Package (60 s)
Ceramic DIP (60 s)
Molded DIP (10 s)
IN 2
Code
5X
5X
Part No.
J.LA733HM
J.LA733HC
Connection Diagram
14-Pin DIP
±8V
±5V
±6V
10 rnA
IN 2
NC
G28
500 mW
670 mW
G,s
-55°C to +125°C
O°C to +70°C
-65°C to +150°C
v-
v+
NC
NC
OUT 2
OUT 1
(Top View)
Order Information
Type
Package
IlA733
Ceramic DIP
IlA733C
Ceramic DIP
J.LA 733C
Molded DIP
Note
1 Rating applies to ambient temperatures up to 70 o e. Above
70 0 e ambient derate linearly at 6.3 mW I °e for the Metal and
8.3 mW / °e for the DIP.
9·22
Code
6A
6A
9A
Part No.
J.LA733DM
J.LA733DC
J.LA733PC
JLA733
Equivalent Circuit
v+
GAIN
Rl
R2
2.4 kl!
2.4 kl!
G1A
SELECT /
G2A
v-
9·23
/-LA733
!LA733 and !LA733C
Electrical Characteristics
Characteristic
TA
= 25°C , Vs = +60
V unless otherwise specified
-
Condition
Differential Voltage Gain
Gain 1, Note 2
Gain 2, Note 3
Gain 3, Note 4
Bandwidth
Gain 1
Gain 2
Gain 3
RS
Risetime
Gain 1
Gain 2
Gain 3
RS
Propagation Delay
Gain 1
Gain 2
Gain 3
RS
Max
Min
Typ
Max
300
90
9.0
500
110
11
250
80
8.0
400
100
10
600
120
12
40
90
120
40
90
120
MHz
MHz
MHz
= 50 n, VOUT = 1 Vp_p
10.5
4.5
2.5
10
10.5
4.5
2.5
12
ns
ns
ns
7.5
6.0
3.6
10
7.5
6.0
3.6
10
ns
ns
ns
= 50 n, VOUT = 1 Vp_p
20
Gain 2
4.0
30
250
10
2.0
Input Offset Current
Input Bias Current
Input Noise Voltage
400
100
10
Unit
= 50 n
Input Resistance
Gain 1
Gain 2
Gain 3
Input Capacitance
!LA733C
!LA733
Typ
Min
RS = 50 n,
BW = 1 kHz to 10 MHz
2.0
=±
=±
Supply Voltage
Rejection Ratio
Gain 2
I1VS
= ±0.5 V
1 V, f :=:; 100 kHz
1 V, f = 5 MHz
pF
3.0
0.4
5.0
!LA
9.0
20
9.0
30
!LA
12
± 1.0
VCM
VCM
kn
kn
kn
0.4
12
Input Voltage Range
Common Mode
Rejection Ratio
Gain 2
Gain 2
4.0
30
250
!LV rms
± 1.0
V
60
86
60
60
86
60
dB
dB
50
70
50
70
dB
Output Offset Voltage
Gain 1
Gain 2 and Gain 3
0.6
0.35
1.5
1.0
3.4
0.6
0.35
1.5
1.5
V
V
2.4
2.9
3.4
V
Output Common Mode
Voltage
2.4
2.9
Output Voltage Swing
3.0
4.0
3.0
4.0
Output Sink Current
2.5
3.6
2.5
3.6
rnA
20
Q
Output Resistance
20
Power Supply Current
18
Notes
2. Gain Select pins G 1A and G 1B connected together.
3. Gam Select pins G2A and G2B connected together.
4. All Gain Select pins open.
9-24
24
18
Vpk-pk
24
rnA
J.LA733
/LA733 and /LA733C
Electrical Characteristics (Cont)
Characteristic
Differential Voltage Gain
Gain 1, Note 2
Gain 2, Note 3
Gain 3, Note 4
Input Resistance
Gain 2
Input Offset Current
Input Bias Current
Input Voltage Range
Common Mode
Rejection Ratio
Supply Voltage
Rejection Ratio
Output Offset Voltage
Gain 1
Gain 2 and Gain 3
Output Swing
The following specifications apply for min -< TA -< max
Condition
/LA733
Typ
Min
Max
/LA733C
Min Typ
Max
200
80
8.0
600
120
12
250
80
8.0
600
120
12
8.0
8.0
k!l
5.0
40
6.0
40
± 1.0
± 1.0
/LA
/LA
V
50
50
dB
50
50
dB
1.5
1.2
1.5
2.5
Output Sink Current
Positive Supply Current
Unit
2.8
2.2
V
Vpk-pk
2.5
27
mA
mA
27
Note&
2 Gain Select pins G 1A and G 18 connected together
3. Gam Select pins G2A and G2B connected together.
4. All Gain Select pins open.
Typical Performance Curves
Phase Shift vs Frequency
~
""
5
•
Phase Shift vs Frequency
•
GAIN 2
Ys "" ~6 V
TA " 2S e c
-so
f::: ~~
Vs '" ±6 V
TA -= 25°C
,
'I
\
•
•
-1.
"-
~
-2.•
I......
•o
-2
•
•
1
2
3
4
5
FREQUENCY -
&
7
MHz
8
9
10
-35
~
,.
50 100
FREQUENCY -
9-25
~
40
~
30
~
"I
"\~~. 5
Vs ~ ttl V
TA '" 25°C
GAN 1
GAIN 2
\\
g
~
-20
~50
Z
"~- -
-250
•
6.
.
~\
-15
i'..
5
Voltage Gain vs Frequency
MHz
i
500 1000
0"
i!l
~
10
~Ui
0
GAIN 3
.,.
-- ~~
1'\
50 100
FREQUENCY -
MHz
500 1000
•
J..tA733
Typical Performance Curves (eont.)
Output Voltage Swing
vs Frequency
Common Mode Rejection
Ratio vs Frequency
100
'II
0
j:
c
a:
Z
0
j:
0
~a:
00w
0',.Z"
"00
GAIN 2
Ys '" ±I V
TA ~ 2S"C
90
'0
70
60
50
.0
30
20
10
010 k
~
10 M
1 M
100 M
vs'=
I
>
~20
0
0
V
)t'
Io
-V
20
40
5
,.
"7
V
y
.5.
....-4.
..
GAIHa-
r-
~4 ...(.r-r~
TEMPERATURE _
30 35
±IV
...
v,
±ov
g 06~T_A,=__-5+50_C~-i"f-~T_A+=_'~'5rOC-+~
> 12~+--r-+~r-t-+-t-+-1-r~
Il.t=j~~~=t~~~~~~~~
V
~
~w
'40
DOC
,
TA "" 70 0
-021-1t--+hl-+--+~--+-+-+~
-5
0
5
10
15
20
25
30
35
TIME -
~ ~T~ t~i50C
0
•
•
•
14
III
2
~
TA
5
10
= 70"C
~=.oC
-"i ~1=1 ••o
IT! ~ 1,2SOC- III
50 100
FREQUENCY -
MHz
9-26
n.
Voltage Gain vs Supply Voltage
±6 V
RL == 1 kfl
4
,
~~'~5--~I.~-~5~~~5~'~.~'5~'~0~'~5~90-J"
ns
•
~90
o
TA
08
J
e
ii •'1-~-+-1rl..--t-~-+-1f-+--i
J
0
~
!
\
ac
25
+,
w
100
20
Vs
Gain Versus Frequency
vs Temperature
0
Ys ==
3
..
15
n.
Vs
z
20
10
TIME -
~ D.41-~-+-1h-..Jr/,+_T,A_=_'+5_0C~-+~
TIME -
I~ 11-
-
5
D.
2
-0 •
-0.•-15 -10
10 100 120 140 180 180 200
\
0."
0
Pulse Response
vs Temperature
r!
>
o
\
-10 -5
MHz
!:i04
-" \ ......
-0'
-0'-15
GAIN 2
TA = 25"C
1.
w
Vs = ±I V
"
500 1000
I RL'" 1 kJl
"~:.:
11
0'-
50 100
,..
>
I
Voltage Gain vs Temperature
-I-
o
1.'
DIFFERENTIAL INPUT VOLTAGE - mY
• \
I.'0
502
18
JV
V
10
.
\
0'0
01
A1N 1
I
5 04
1\
20
FREQUENCY -
./
;::
.
J ..<
II I....
>
Pulse Response vs
Supply Voltage
;60
~40
fil30
r
Hz
TA = 25"C
GAIN 2
260
GAIN 2
0 0.6
::>
100 k
GAN 3
w
I 10
g
.
>
~ O.
"!:ic 30
~
aoe
12
: 40
r-.,
Ys = ±6 Y
TA =
RL = 1 kn
14
I
70
,
TA = 25°C
1-+++t-+-+-HIt-+RL = 1kU
"z so
Differential Overdrive
Recovery Time
~
Ys=±6V
it 60
>
i
FREQUENCY -
~
Pulse Response
1.'
500 1000
TA '" 25°C
13
12
/'
1
f-
0 - 0 ..'M3
o\~_r--
,...
.:::: ~,
,.,4- I--.f+'
'5 /
"
V
•
SUPPLY VOLTAGE -
-tv
J.tA733
Typical Performance Curves (Cont.)
Output Voltage and
Current Swing vs
Supply Voltage
Output Voltage Swing
vs Load Resistance
Gain Versus Frequency
vs Supply Voltage
60r-'-rrr-~-;,,~-;~~~-,
0
GAIN 2
T, - 25°C
>
c
"Z
15 0
V
E
~
~ SOr-~r+r-+--r~+--r-T~'r~T2T5T'C-;
0
,/
0
~
;....-;
....~....'
.o~
0
o~
k:: c::::
V
Z
~ 40r-~t+r-+--t-H~-t--rtTT-;
V
,/
~ 3o~~~~~;f~~~~~++~
,/
ffi
c"
...
so
30
60
TA
80
FREQUENCY -
Input Resistance
vs Temperature
0
I
Vs = ±6 V
;;
"w
0
"~
g
0
~
ill
0
~is
V
20
1 20
10
0
I".
0/
f'.
,.
100
SOURCE RESISTANCE -
,.
0
10
10 •
100
R adj -
Jl
Supply Current
vs Temperature
10.
28
TA = 25'C
20
c
c
4
/
E
19
I
E 18
::: 1/
"o 17
........
~
t-..... .......
"a
I'
~
~
16
20
/
V
16
,/
12
15
/
14
~60
IL
~20
20
60
TEMPERATURE -
100
QC
140
•/
3
SUPPLY YOl TAGE -
9-27
±Y
l/'
/V
V
~60
-20
0
20
100
60
TEMPERATURE _
Jl
Ys = ±6 V
./
V
0
Supply Current vs
Supply Voltage
1
ILV
100
~
>=
0
30
0
i5!
GAIN 2
0
Z
c
SO
MHz
0
0
~
10 k
Q
2S"C
=
±8 V
h~~V
Vs = ±6 V
TA = 2S C
BW = 10 MHz
I-
"..
!;
5 k
VS'" :!:6 V
170
w
Vs
n
1000
i III
GAiN
w
'"oZ
500 1 k
Voltage Gain vs RADJ
100
6
100 200
LOAD RESISTANCE -
+V
Input Noise Voltage
vs Source Resistance
90
50
10
80
70
SUPPLY VOLTAGE -
~
r
"
Z
;;;
0
g
20r-~t+r-~-t-H~-t,.rtTT-;
f iw~ 10~1-ttr-+--t-H+--tI\~~~~
0
~
,,~
g
140
ac
•
Il A73 3
Typical Applications
Oscillator Frequency for Various Capacitor Values
10 7
,
106
IL
........
105
w
U 10'
z
«
t-
o
«
a.. 103
«
u
u
10 2
~
~
Q.
1 kn
t-
_____ MEASURED
~
CALCULATED
~~
620 n MA73~
~ ........
~~
f--T-I
~
""'" ~
IlJ
f
f
~
liT
~
2(Rl
10
~~
1
+ R2)CL, [AV ~-1]
Rl + R2
~r-.
~
f " 3.4 x 103C
1
100
1.0 k
100 k
10 k
FREQUENCY -
9-28
Hz
1 M
10 M
f.lA757
Gain-Controlled
IF Amplifier
FAIRCHIL.O
A Schlumberger Company
Special Function Products
Connection Diagram
14-Pin DIP
Description
The IlA757 is a monolithic high performance, Gain
Controlled IF Amplifier constructed using the Fairchild
Planar epitaxial process. The amplifier contains two
different sections which may be operated
independently, or in cascade, from audio frequencies
to 25 MHz. The IlA757 is intended primarily as a high
gain controlled, intermediate frequency amplifier in AM
or FM communications receivers. It also has excellent
performance when operated in FM receivers as a
limiting amplifier.
+IN A
DECOUPLE
AGC 1
AGC 2
GND
DECOUPLE
•
•
•
•
•
70 dB GAIN AT 10.7 MHz
70 dB AGC RANGE AT 10.7 MHz
300 mV INPUT SIGNAL CAPABILITY
CONSTANT I/O IMPEDANCE WITH AGC
STABLE GAIN WITH SUPPLY VOLTAGE AND
TEMPERATURE AT ALL LEVELS OF
GAIN REDUCTION
Absolute Maximum Ratings
Supply Voltage
Voltage at any Output Terminal
Voltage at either AGC Terminal
Note 1
Differential Voltage at either Input
(Pins 1 and 14, Pins 2 and 10)
Internal Power Dissipation
Note 2
Storage Temperature Range
Operating Temperature Range
Pin Temperature (Soldering, 60 s)
-OUT B
(Top View)
Order Information
Type
Package
IlA757C
Ceramic DIP
Code
6A
Part No.
IlA757DC
+15 V
+24 V
± 12 V
±5V
670 mW
-65°C to +150°C
O°C to +70°C
300°C
•
Noles
1. For supply voltages less than + 12 V, the absolute maximum
voltage at either AGC terminal IS equal to the supply voltage.
2 Rating applies to ambient temperatures up to 70°C. Above
70°C ambient derate linearly at 8.3 mW / °c.
9-29
jlA757
Equivalent Circuit
OUTPUT 8
+
OUTPUT A
'2
V+
SHIELD 9
INPUT B
'I'
I
'0
I
J'"
900 !l
.........
'"
700 !l
'3
DECO UPLE
"-.I
V
....
'"
5 kfl
.....
kn
r
[:l-rK
5 k!l
OECOUP LE
2
300
n
300
'--
n
3
3 kn
~
3 kll
200 Jl
11 k!l
200 Jl
400 !I
kn
~~
13
25
kn
kI'
11
>-
5 kH
3.5
r-
v
K
....-
5 k!l
-
.....
kn
~
>-
r--AGC 1
11
V
5
kn
,.
INPUT A
"-.I
",
5
V
~
15 kll
v
5
I
I
I
300
300
n
n
8kO
~
D-J-~
n
5 kn
T
~
11 kH
3 kll
~
.........
200 !l
200
n
40011
I
•
5
AGe 2
9-30
GROUND
V
1--..
1
6 kfl
4 k!l
150 !l
DECOUPLE
n
p,A757
/lA757
Electrical Characteristics
Characteristic
Supply Current
V+ = + 12 V, TA = 25 0 C , unless otherwise specified
Test
Circuit Min
Condition
VAGC 1,2 = +0.8 V
VAGC 12= +3.0 V
Internal Power Dissipation VAGC
VAGC
Voltage Gain at
VAGC
no Reduction
VAGC
Voltage Gatn at Partial
VAGC
Gain Reducjlion
VAGC
Voltage Galin at
VAGC
Full Gain Reduction
VAGC
Current into either
VAGC
AGC Terminal
1 2 = +0.8 V
1'2 = +3.0 V
Typ
Max
Typ
Max
Unit
1
13
17
17
20
14
18
17
22
mA
mA
1
170
200
210
240
170
220
210
270
mW
mW
1,2 = +0.8 V, f = 500 kHz 2
1 2 = +0.8 V, f = 10.7 MHz 2
1,2 = +1.7 V, f = 500 kHz 2
12= +1.7 V, f = 10.7 MHz 2
65
60
74
70
20
39
37
46
2.0
1.0
1
15
1,2 = +3.0 V, f = 500 kHz 2
12= +3.0 V, f = 10.7 MHz 2
1,2 = +3.0 V
Min
65
60
74
70
20
39
37
46
dB
dB
10
8
2.0
1.0
10
8
dB
dB
50
15
50
/lA
dB
dB
Gain Reduction
Sensitivity
VAGC 1,2 = +1.7 V, f = 500 kHz
2
50
50
dBIV
Input Voltage for -3 dB
Limiting at Output
VAGC 1,2 = +0.8 V, f = 500 kHz
2
0.5
0.5
mV
Intermodulation Products
Two-tone signal
f1 = 500 kHz, e1 = 100 mV
f2 = 510 kHz, e2 = 100 mV
lOUT = 1 mA pop
2
-50
-50
dB
5.0
4.5
kQ
kQ
2.5
2.2
2.5
2.2
pF
pF
Section 1
Input Resistance at either VAGC
Input Terminal
VAGC
Input Capacitance at
VAGC
either Input Terminal
VAGC
1 = +0.8 V, f = 10.7 MHz
1 = +3.0 V, f = 10.7 MHz
1 = +0.8 V, f = 10.7 MHz
1 = +3.0 V, f = 10.7 MHz
3.0
5.0
4.5
3.0
Output Resistance
VAGC 1 = +0.8 V, f = 10.7 MHz
VAGC 1 = +3.0 V, f = 10.7 MHz
100
100
100
100
kQ
kQ
Output Capacitance
VAGC 1 = +0.8 V, f = 10.7 MHz
VAGC 1 = +3.0 V, f = 10.7 MHz
2.6
2.2
2.6
2.2
pF
pF
Forward Transadmittance
VAGC 1 = +0.8 V, f = 500 kHz
VAGC 1 = +0.8 V, f = 10.7 MHz
14
13
14
13
mmho
mmho
Peak-to-Peak
Output Current
VAGC 1 = +3.0 V, f = 500 kHz
Output in full limiting
0.4
mA
Output Saturation Voltage lOUT = 0.1 mA, VAGC 1 = +3.0 V
RS = 1.0 kQ, f = 10.7 MHz
Noise Figure
RS = 1.0 kQ, f = 500 kHz
Interfering Signal Voltage Carrier signal, fc = 500 kHz
at Input for 1.0%
Interfering signal, fj = 510 kHz
Cross Modulation
lOUT = 0.5 mAp-p, VAGC 1 = +0.8 V
9-31
0.25 0.4
8.0
0.25
9.0
8.0
9.0
V
8.0
8.0
8.0
8.0
dB
dB
15
15
mV
•
p,A757
Section 2
Electrical Characteristics (Cont.)
V+
Characteristic
Condition
Input Resistance
VAGC 2
VAGC 2
Input Capacitance
Output Resistance at
either Output Terminal
Output Capacitance at
either Output Terminal
Forward Transadmittance
Quiescent Output Current
at either Output Terminal
Peak-to-Peak Current at
either Output Terminal
= + 12 V, TA = 25°C, unless otherwise specified
Test
Circuit Min
= +0.8 V, f = 10.7 MHz
= +3.0 V, f = 10.7 MHz
VAGC 2 = +0.8 V, f = 10.7 MHz
VAGC 2 = +3.0 V, f = 10.7 MHz
VAGC 2 = +0.8 V, f = 10.7 MHz
VAGC 2 = +3.0 V, I = 10.7 MHz
VAGC 2 = +0.8 V, f = 10.7 MHz
VAGC 2 = +3.0 V, f = 10.7 MHz
VAGC 2 = +0.8 V, f = 500 kHz
VAGC 2 = +0.8 V, f = 10.7 MHz
VAGC 2 = +3.0 V
VAGC 2 = +3.0 V, f = 500 kHz
3.0
Output in lull limiting
Vs
Characteristic
Supply Current
Internal Power Dissipation
Voltage Gain at no Gain
Reduction
Voltage Gain at Partial
Gain Reduction
Voltage Gain at Full Gain
Reduction
Current into either
AGC Terminal
Typ
3.0
5.0
4.5
kn
kr!
2.5
2.2
2.5
2.2
pF
pF
26
20
26
20
kn
kn
2.2
2.5
2.2
2.5
pF
pF
440
280
440
280
mmho
mmho
Max
3.5
1.7
2.4
3.5
mA
3.8
4.8
7.0
3.8
4.8
7.0
mA
5.0
6.0
5.0
6.0
V
o dB Gain Reduction
0.5
0.8
1.0
30 dB Gain Reduction
60 dB Gain Reduction
0.5
0.8
1.0
dB/V
dB/V
dBIV
V + = + 12 V, TA = + 125 ° C, unless otherwise specilied
Test
Circuit
Condition
= +0.8 V
= +3.0 V
VAGC 1,2 = +0.8 V
VAGC 1 2 = +3.0 V
VAGC 1,2 = +0.8 V, f = 500 kHz
VAGC 1 2 = +0.8 V, I = 10.7 MHz
VAGC 1,2 = +1.7 V, f = 500 kHz
VAGC 1.2 = +3.0 V, I = 500 kHz
VAGC 1 2 = +3.0 V, f = 10.7 MHz
VAGC 1,2 = +3.0 V
VAGC 1,2
VAGC 1 2
Typ
Max
Unit
1
14
17
17
20
mA
mA
1
170
200
210
240
mW
mW
Min
71
62
dB
dB
2
35
dB
2
2
2.0
-1.0
15
dB
dB
1
15
50
/LA
2
2
55
Section 1
Peak-to-Peak Output
Current
VAGC 1 = +3.0 V, f = 500 kHz
Output in lull limiting
Output Saturation Voltage
lOUT
= 0.1
0.2
mA, VAGC 1 = +3.0 V
mA
0.4
8.0
9.4
V
1.7
2.8
3.5
mA
3.8
5.6
7.0
mA
6.0
7.0
V
Section 2
Quiescent Output Current
at either Output Terminal
VAGC 2
Peak-to-Peak Current at
either Output Terminal
Output in full limiting
Output Saturation Voltage
at either Output Terminal
= +3.0 V
VAGC 2 = +3.0 V, f = 500 kHz
lOUT
= 1.0 mA, VAGC 2 = +3.0 V
9-32
Unit
2.4
= 1.0 mA, VAGC 2 = +3.0 V
= 12 V to 15 V
/LA757
Electrical Characteristics (Cont.)
Min
Max
1.7
Output Saturation Voltage
at either Output Terminal lOUT
Power Supply Sensitivity
Typ
5.0
4.5
I1 A757
/LA757
Electrical Characteristics
V+
Characteristic
Condition
Supply Current
VAGC 1,2 = +0.8 V
VAGC 1 2 = +3.0 V
1
Internal Power Dissipation
VAGC 1,2 = +0.8 V
VAGC 1 2 = +3.0 V
1
Voltage Gain at no Gain
Reduction
VAGC 1,2 = +0.8 V, I = 500 kHz
VAGC 12= +0.8 V, I = 10.7 MHz
2
2
Voltage Gain at Partial
Gain Reduction
VAGC 1,2 = +1.7 V, f = 500 kHz
Voltage Gain at Full
Gain Reduction
Current into either
AGC Terminal
= +12 V, TA = -55°C, unless otherwise specilied
Test
Circuit
Min
55
Typ
Max
Unit
10
14
17
20
mA
mA
120
170
210
240
mW
mW
68
64
dB
dB
2
28
dB
VAGC 1,2 = +3.0 V, f = 500 kHz
VAGC 1 2 = +3.0 V, f = 10.7 MHz
2
2
2.0
-3.0
15
dB
dB
VAGC 1,2 = +3.0 V
1
30
70
/LA
Section 1
Peak-to-Peak Output
Current
VAGC 1 = +3.0 V, I = 500 kHz
Output in lull limiting
Output Saturation Voltage
lOUT = 0.1 mA, VAGC 1 = +3.0 V
0.2
0.4
mA
8.0
9.0
V
Section 2
Quiescent Output Current
at either Output Terminal
VAGC 2 = +3.0 V
1.0
1.7
3.5
mA
Peak-to-Peak Current at
either Output Terminal
VAGC 2 = +3.0 V, f = 500 kHz
Output in lull limiting
2.3
3.4
7.0
mA
Output Saturation Voltage
at either Output Terminal
lOUT = 1.0 mA, VAGC 2 = +3.0 V
4.0
6.0
V
•
9-33
Il A757
Typical Performance Curves
Section 1
Forward Transadmittance
vs Frequency
I D dB REFERENCE
o dB
•
•
II
10 dB GAIN REDUCTION
~
10
I
"
II
•
20 dB GAIN REDUCTION
~ 20
I
z
"~
,lo
~ 14 mmho
GAtN REDUCTiON
I
w
U
II
•
•
•
••
30 dB GAIN REDUCTION
3D
w
>
;::
~
TA -= 25°C
V - ·12 V
40
50
10
20
50
"f
10
75
t
';
20
FREQUENCY -
f-f-50
100
~
--.. r-.....
lAPALTAN~E
40k
lJDU~
IG"'~N IRJDUC~ ['\
10 dS!
3
3. k
3. dBI ~A!N IRlouCT1:'
I'--
ro
W
~
~
•
2•
~
c:
I.
~ 20
I
z
o
~::>
iil
'"
z
;;c
+125°C-l
~ r--
f
."
~
"•::;
z
"onI
~
~
::>
0
8••
=1
+1
o
SOD
Jv
rz
"E
18
I
VAGC
16
'" 14
B
\\
>
~
ro
~
50
~
~~
}JA7S7
VAGC -
2.5
V
3D
3.5
40
3/
A"
12
./
V
8
2.0
f
V
~
I.
v·
I.
16•
•
~B
2.
POWER SUPPLY VOLTAGE -
9,34
14.
I ••
"C
I, = 510 kHz
V· '" ~12 V
---
13
6.
T, co +2SoC
•
t A757
12
"- 12 V
sao kHz
""I
2.
-6.
o
Two Tone 1M Distortion Products
vs Input Signal Level
I.
:, I " .:" k~'
TA = 25°C
11
100
Gt lN 7EoYCTlFN fT '15OC
TEMPERATURE _
V
V'
SO
MHz
;A7S~ I
20
dB
V
V
~A757
i'"
V f.--
VAGC = 1 /
~
t
+125°C
15
~
2.
~
55°C
10
2
I t 757
GAIN REDUCTION -
\
OS
g
•• k
>-
+25°C
w
--~
60
"~ 30
cAJAc'T1NcE
W
20
J I II I
I--+I'· dlB GflN ~Eo~CTli'N iT ~I'"ci
1
I L l J. I
3. dB GAIN REo'lCTIiN fT TOCI
z
;;:
20 k
•
10
•l-r
••
" 4.
.......... ~AICE
I. k f.-
-'- -12 V
Voltage Gain vs Temperature
8.
o dB GAIN REDUCTION AT +25°~ I
2S0~
>- 15k
SO
FREOUENCY -
!g
">-
20
MHz
~ 25 k
~
V
"-
6. 10
100
T,
'"
V' = +12 V
f = 107 MHz
z
~
TEST CIRCUIT 2
" 6.
r
50
20
22
3.
..
,.
10
25°C
~
Power Supply Current
vs Supply Voltage
v,l
~55·C
+2~·C- ~
40
50
2G
~
'\ "'"
40 dB
A7S7
dB
Gain Reduction vs
Gain Control Voltage
I 1h
I GAlN IR~OUCTIION
'\
~
1
ro
~
50
GAIN REDUCTION -
"
O2
TA
IRJDUCTI~N ' \
'\
IJ.A757
•
I
il
x 1°1-3
62
III'h.
20 dB GAiN
20 dB
3Sk
:
TA "'" 2S"C
Y-=+12V
f =1107 ~Hz
25k
GAlN
Section 2 Output
Resistance and Capacitance
vs Gain Reduction
0:
!t
o dB0Gd:'NR:~~~~~~~N=-
TA "- 25°C
V+ "'- +12 V
3. k
- r--
~ 35 k
jmio!
- 440
FREQUENCY -
4
I
w 45 k
!il
~
~EFERENCE
dB
GAIN REOUCTION
MHz
55k
!ESIJANcl
o dB
10
Section 1 and 2 Input
Resistance and Capacitance
vs Gain Reduction
SOk
Product of Sections 1 and 2
Forward Transadmittance
vs Frequency
Section 2
Forward Transadmittance
vs Frequency
14
V
15
•
10
30 mA pp
10
20mApp
./
rJ
/
I I
/
lo=10mApp
./
I I
50
"A757
10
INPUT LEVEL -
50
100
mV
•••
f.LA757
Test Circuit
Test Circuit 1 (Note)
+12 V
Note
For 10 7 MHz measurements, interstage capacItance and Section
2 output capacitMce are tuned out. Pm 9 should be connected
to GND.
Test Circuit 2 (Note)
INPUT A
+12V
~1'''' J
0.1 MF
14
0.1 MF
13
12
50 II
+----+....,
11
10
TOP VIEW
L..---- 7 V) and low values of timing capacitor
(C < 0.1 f,LF), the pulse width of TBO may be too
narrow to trigger the counter section. This can be
corrected by connecting a 300 pF capacitor from
TBO (pin 14) to ground (pin 9).
-55°C to +125°C
O°C to 70°C
300°C
260°C
Note
•
Reset (pin 10) stops the time-base oscillator.
•
Outputs 00 ... 0128 (pins 1-8) sink 2 mA current
with VOL:::; 0.4 V.
•
For use with external clock, minimum clock pulse
amplitude should be 3 V, with greater than 1 f,LS
pulse duration.
Above 25 ° C ambient derate Imearly at 6 2 mW 1 0 C for Package
Code 0 and at 5 3 mW I °c for Package Code P
Functional Description
(Figure 1 and Block Diagram, page 1)
When power is applied to the J,tA2240 with no trigger
or reset inputs, the circuit starts with all outputs HIGH.
Application of a positive-going trigger pulse to TRIG,
Pin 11, initiates the timing cycle. The Trigger input
activates the time-base oscillator, enables the
counter section and sets the counter outputs LOW.
The time-base oscillator generates timing pulses with
a period T = 1 RC. These clock pulses are counted by
the binary counter section. The timing sequence is
completed when a positive-going reset pulse is
applied to R, pin 10.
Fig_ 1
Logic Symbol
11
VCC
GND
Trigger TRIG (pin 11) sets all outputs LOW.
15
1
2
3
4
5
6
7
8
Timing Diagram of Output Waveforms
rn~~
INPUT
11
~_1...._ _ _ _ _ _ _ _ _ _ _ _ _ _ t PIN
I
TIME BASE
~I~T~~T
1111111111111111111 II III
hn.nnnn.rulnnn.
COUNTER
OUTPUTS
_tPIN1
h . . n n n . . n . . n . . . _ 1 PIN 2
h_. . .C]_
. ........_ ...CJ_--'-_...C]_--' _
h
1 PIN 3
'_IPIN4
h_....L.________......_ _ _ _ I PIN 5
Important Operating Information
•
VREG
= Pm 16
= Pin 9
Fig_ 2
In most timing applications, one or more of the counter
outputs are connected to the Reset terminal with S 1
closed (Figure 3). The circuit starts timing when a
trigger is applied and automatically resets itself to
complete the timing cycle when a programmed count
is completed. If none of the counter outputs are
connected back to the Reset terminal (switch S 1
open), the circuit operates in an astable or freerunning mode, following to a trigger input.
Reset R (pin 10) sets all outputs HIGH.
MOD
~A2240
Figure 2 gives the timing sequence of output
waveforms at various circuit terminals, subsequent to
a trigger input. When the circuit is in a Reset state,
both the time-base and the counter sections are
disabled and all the counter outputs are HIGH.
•
RC
TRIG
14
Ground connection is pin 9.
12
10
Once triggered, the circuit is immune from additional
trigger inputs until the timing cycle is completed
or a reset input is applied. If both the reset and
trigger are activated simultaneously, the trigger
takes precedence.
•
13
9-37
•
,uA2240
Fig. 3
Basic Circuit Connection for Timing Applications
Monostable: S 1 Closed Astable: S 1 Open
. . . - - - - - - - - - _ - - - Vee
TRIGGER
J1...
RESET
J1...
20 k
47 k
TRIGGER
.Jl
____
o--r~~-+~~~~~~--~_+--OUTPUT
SI
1 T < To < 255 T
WHERE T = RC
Fig. 4
~
-i To I+-
Operation with External Sync Signal
Tp...j
I-
0.3 T < Tp < 0.8 T
o~-±p
0.1
~F
~lt-J\I\I......_ _
12.... ~A2240
INPUT
5.1 k
SYNC
I-Ts-J
Circuit Controls
can be synchronized to an external clock by applying
a sync pulse to MOD, pin 12, as shown in Figure 4.
Recommended sync pulse widths and amplitudes are
also given.
Counter Outputs (00 ... 0128, pins 1 thru 8)
The binary counter outputs are buffered open-collector
type stages, as shown in the block diagram. Each
output is capable of sinking 2 mA at 0.4 V VOL. In the
Reset condition, all the counter outputs are HIGH or in
the non-conducting state. Following a trigger input, the
outputs change state in accordance with the timing
diagram of Figure 2. The counter outputs can be used
individually, or can be connected together in a
wired-OR configuration, as described in the
programming section.
The time base can be synchronized by setting the
time-base period T to be an integer multiple of the
sync pulse period, Ts. This can be done by choosing
the timing components Rand C at pin 13 such that:
T
Reset and Trigger Inputs (R and TRIG, pins
10 and 11)
The circuit is reset or triggered with positive'going
control pulses applied to pins 10 and 11 respectively.
The threshold level for these controls is approximately
two diode drops (""" 1.4 V) above ground. Minimum
pulse widths for reset and trigger inputs are shown in
the Performance Curves. Once triggered, the circuit is
immune to additional trigger inputs until the end of the
timing cycle.
= RC = (Ts/m)
where
m is an integer, 1 :5 m :5 10
Figure 5 gives the typical pull·in range for harmonic
synchronization for various values of harmonic
modulus, m. For m < 10, typical pull-in range is
greater than ± 4% of time-base frequency.
RC Terminal (pin 13)
The time-base period T is determined by the external
RC network connected to RC, pin 13. When the time
base is triggered, the waveform at pin 13 is an
exponential ramp with a period T = 1.0 RC.
Modulation and Sync Input (MOD, pin 12)
The oscillator time-base period, T, can be modulated
by applying a dc voltage to MOD, pin 12
(see Performance Curves). The time-base oscillator
9-38
~A2240
Fig. 5
Typical Pull-in Range for
Harmonic Synchronization
.e:
.=
."
o
±20
±16
'o~"
".I
j
is operated with an external time base. The counter
section triggers on the negative-going edge of the
timing or clock pulses generated at TBO, pin 14. The
trigger threshold for the counter section is "." + 1.4 V .
The counter section can be disabled by clamping the
voltage level at pin 14 to ground.
±12
~
~
8
4
\
'"
........
When using high supply voltages (Vee> 7 V) and a
small-value timing capacitor (C < 0.1 /IF), the pulse
width of the time-base output at pin 14 may be too
narrow to trigger the counter section. This can be
corrected by connecting a 300 pF capacitor from
pin 14 to ground.
I'--
"
10
12
Regular Output (VREG, pin 15)
The regulator output VREG is used internally to drive
the binary counter and the control logic. This terminal
can also be used as a supply to additional /lA2240
circuits when several timer circuits are cascaded
(see Figure
to minimize power dissipation. For
circuit operation with an external clock, VREG can be
used as the Vee input terminal to power down the
internal time base and reduce power dissipation.
When supply voltages less than 4.5 V are used with
the internal time-base, pin 15 should be shorted to
pin 16.
RATIO OF TIME-BASE PERIOD TO
SYNC·PULSE PERIOD - TfT!
Time-Base Output (TBO, pin 14)
The time·base output is an open-collector type stage
as shown in the block diagram, and requires a 20 kQ
pull-up resistor to pin 15 for proper circuit operation. In
the Reset state, the time·base output is HIGH. After
triggering, it produces a negative-going pulse train
with a period T Re, as shown in the diagram of
Figure 2. The time-base output is internally connected
to the binary-counter section and can also serve as
the input for the external clock signal when the circuit
n
=
Fig. 6
Cascaded Operation for Long Delays
vee
vee
vee
RL
47 k
R
10 k
c
I
TRIGGER
-~I-ITRIG
1 k
RC
RC
MOD
MOD
TRIG
"A2240 #1
VREG
"A2240 #2
VREG
R
RESET----~--_+--------------------~----~~~-4-4~~~~~+-4------4---0UTPUT
47 k
Vee = Pin 16
GND = Pin 9
9-39
•
JLA2240
Fig. 7
Low Power Operation of Cascaded Timers
Vee
Vee
R
Vee
RL
47 k
30 k
ric
I
TRIGGER
...n..
""'- TRIG
RC
~A2240
RESET
J'1...
#1
I
I
I
MOD
RC
MOD
-
TRIG
~A2240
VREG ~
R
TBO 00 02 04 08 0'6 032064 0'28
rlllllilL
.
...
N
#2
VREG
-R
TBO 00 02 04 080'6 032064 0,28
-I
150 k
=
Vee
Pm 16
GND = Pm 9
9-40
-
J,LA2240
/LA2240 and /LA2240C
Electrical Characteristics
Characteristic
Condition
Unit
General Characteristics
Supply Voltage
For Vee ~ 4.5 V, Short Pin 15
to Pin 16
Supply Current
Total Circuit
Vee
Vee
4.0
= 5 V, VTR = 0, VRS = 5 V
= 15 V, VTR = 0, VRS = 5 V
Measured at Pin 15, Vee
Vee
15 V
=
=5 V
4.1
6.0
4.0
6.0
16
3.5
12
1
Counter Only
Regulator Output, VReg
15
4.4
6.3
6.6
4.0
13
1.5
3.9
5.8
15
V
7.0
18
mA
mA
mA
4.4
6.3
6.8
V
V
5.0
%
ppm/oC
ppm/oC
0.3
%/V
Time Base Section
Timing Accuracy
Temperature Drift
= 0, VTR = 5 V (Note 1)
Vee = 5 V'looc ~ TJ ~ 750C
Vee = 15 V
VRS
~
Supply Drift
Vee
Max Frequency
R
Modulation Voltage Level
Measured at Pin 12
Vee 5 V
Vee
15 V
Recommended Range of
Timing Components
Timing Resistor, R
Timing Capacitor, C
8 V (See Curves)
= 1 kfl, C = 0.007 /LF
=
=
0.5
2.0
5.0
150
80
300
200
80
0.05
0.2
0.08
100
130
3.00
3.5
10.5
130
4.0
2.80
3.50
10.5
kHz
4.20
V
V
(See Performance Curves)
0.001
0.007
10
0.001
1000 0.01
10
Mfl
1000 /LF
Trigger/Reset Controls
Trigger
Trigger Threshold
Trigger Current
Impedance
Response Time
Measured at Pin 11, VRS
Reset
Reset Threshold
Reset Current
Impedance
Response Time
Measured at Pin 10, VTR
VRS
=0
= 0, VTR = 2 V
Note 2
VTR
1.4
8.0
25
1.0
2.0
1.4
10
25
1.0
2.0
V
/LA
kfl
/LS
1.4
8.0
25
0.8
2.0
1.4
10
25
0.8
2.0
V
/LA
kfl
/LS
=0
= 0, VRS = 2 V
Note 2
Counter Section
Max Toggle Rate
=
=
VRS 0, VTR
5V
Measured at Pin 14
0.8
Input Impedance
Input Threshold
Output
Rise Time
Fall Time
Sink Current
Leakage Current
1.0
1.5
1.5
MHz
20
20
kfl
1.4
V
180
180
4.0
0.01
ns
ns
mA
/LA
1.4
1.0
Measured at Pins 1 through 8
Rl
= 3 kfl, Cl = 10 pF
Val
VOH
~
3.0
0.4 V
= 15 V
Notes
1. Tlmmg error solely Introduced by I'A2240. measured as % of
Ideal time base period of T = 1.00 Re.
180
180
5.0
0.01
2.0
8.0
15
2. Propagallon delay from application of trigger (or reset) input to
corresponding state change in counter output at Pin 1.
9·41
--
--~
. . ~-----
-
- - - : . - - - --~--
-
•
JLA2240
Typical Performance Curves
Supply Current vs
Supply Voltage in Reset Condition
Recommended Range of
Timing Component Values
1/
1 ••
I"
/
i
/
V
V
~100
Iii
~
"z .0
I
!
8
10
12
SUPPLY VOLTAGE -
14
18
18
V
TIMING CAPACITOR -
Minimum Trigger Pulse Width
vs Trigger and Reset Amplitude
...
Time Base Period vs External RC
.0 M,.----,----:
11
TIME BASE PERIOD
IIF
Minimum Trigger /
Retrigger Timing vs
Timing Capacitor
Time Base Period Drift
vs Supply Voltage
+a.0
+7S-C
+25°C
.~
..
I +2.
!!;
i!i +•.
I
Ire
~
.......
+7S·C
+2I-C-
o·c
...'.0
'.5
1.5
!.
~
o
0
\
c
f'....
..
-0
I0-'.
Yee =1
I
I
:I 1.0
~
0.5
V
./'
/
+2.0
+2.0
vee! 15 V
C =~'"F
-
2
~
...............
-10
!.
~R=1kn
R='~
"-
~
-3 0
25
'00
I
...............
~ -2.0
Y
•
0+1.0
.
0
MODULATION VOLTAGE -
,
!
1:1 +1.0
~..
!
o.
TIMING CAPACITOR - p.F
V
Yee 5 Y
C=O.1pF
I
V
0.'!F"""-r1f--
Time Base Period
VB Temperature
I
yj
:I
:>
••
12
SUPPLY VOLTAGE -
..
I
i
10
Time Base Period
vs Temperature
2.1
2.0
- r---r---
E
II: •.01--~1,.t~~'1---+_-___j
~
TRIGGER OR RElET AMPLITUDE - V
Normalized Change in
Time Base Period
vs Modulation Voltage
= 0.1 pF
R = 10 kn
-2.0•
a.o
'01---t---417"-='"~+----t
~
0\
50
7.
TEMPERATURE _ ·C
9-42
'00
!
0--
~
-1.0
.
Rl,oM~
~ -2.0
~
-a.0
••
•0
TEMPERATURE _ DC
7•
.00
JLA2240
Monostable Operation
Astable Operation
The jLA2240 can be operated in its astable or freerunning mode by disconnecting the Reset terminal
(pin 10) from the counter outputs. Two typical circuits
are shown in Figures 8 and 9. The circuit in Figure 8
operates in its free-running mode with external trigger
and reset signals. It starts counting and timing
following a trigger input until an external reset pulse is
applied. Upon application of a positive-going reset
signal to pin 10, the circuit reverts back to its Reset
state. This circuit is essentially the same as that of
Figure 3 with the feedback switch S 1 open.
Precision Timing
In precision timing applications, the jLA2240 is used
in its monostable or self-resetting mode. The
generalized circuit connection for this application is
shown in Figure 3. The output is normally HIGH and
goes LOW following a trigger input. It remains LOW for
the time duration, TO, and then returns to the HIGH
state_ The duration of the timing cycle To is given as:
TO
= nT = NRC
=
where T
RC is the time-base period as set by the
choice of timing components at RC pin 13 (see
Performance Curves) and n is an integer in the range
of 1 :$ n :$ 255 as determined by the combination of
counter outputs 00 ... 0128, pins 1 through 8,
connected to the output bus.
The circuit of Figure 9 is designed for continuous
operation. It self-triggers automatically when the
power supply is turned on, and continues to operate in
its free-running mode indefinitely. In astable or freerunning operation, each of the counter outputs can be
used individually as synchronized oscillators, or
they can be interconnected to generate complex
pulse patterns.
Counter-Output Programming
The binary-counter outputs, 00 ... 0128, pins
1 through 8 are open-collector type stages and can be
shorted together to a common pull-up resistor to form
a wired-OR connection; the combined output will be
LOW as long as anyone of the outputs is LOW. The
time delays associated with each counter output can
be added together. This is done by simply shorting the
outputs together to form a common output bus as
shown in Figure 3. For example, if only pin 6 is
connected to the output and the rest left open, the
total duration of the timing cycle, TO, is 32 T. Similarly,
if pins 1, 5, and 6 are shorted to the output bus, the
total time delay is To = (1 + 16 + 32) T = 49 T. In this
manner, by proper choice of counter terminals
connected to the output bus, the timing cycle can be
programmed to be 1 T:$ TO :$ 255 T.
Binary Pattern Generation
In astable operation, as shown in Figure 8, the output
of the jLA2240 appears as a complex pulse pattern.
The waveform of the output pulse train can be
determined directly from the timing diagram of
Figure 2 which shows the phase relations between the
counter outputs. Figures 10 and 11 show some of the
complex pulse patterns that can be generated. The
pulse pattern repeats itself at a rate equal to the
period of the highest counter bit connected to the
common output bus. The minimum pulse width
contained in the pulse train is determined by the
lowest counter bit connected to the output.
Ultra Long Time-Delay Application
Two jLA2240 units can be cascaded as shown in
Figure 6 to generate extremely long time delays.
Total timing cycle of two cascaded units can be
256 RC to TO
65,536 RC in
programmed from To
256 discrete ~teps by selectively shorting one or more
of the counter outputs from Unit 2 to the output bus. In
this application, the Reset and the Trigger terminals of
both units are tied together and the Unit 2 time base is
disabled. Normally, the output is HIGH when the
system is reset. On triggering, the output goes LOW
where it remains for a total of (256)2 or 65,536 cycles
of the time-base oscillator.
=
=
In cascaded operation, the time-base section of Unit 2
can be powered down to reduce power consumption
by using the circuit connection of Figure 7. In this
case, the Vee terminal (pin 16) of Unit 2 is left open,
and the second unit is powered from the regulator
output of Unit 1 by connecting the VREG (pin 15) of
both units together.
9-43
~A2240
Fig. 8
Operation with Trigger and Reset Inputs
Vee
RL
10 k
R
0.01
C
l
l
TRIGGER
..I1.
~F
MOD
RC
TRIG
~A2240
VREG
RESET
20 k
..I1.
..................................- ...-+- OUTPUT
=
Vee
Pin 16
GND = Pin 9
Fig. 9
Free-Running or Continuous Operation
Vee
Vee
10 k
Vee
RL
10 k
R
C
MOD
RC
Vee = Pm 16
GND = Pin 9
TRIG
VREG
20 k
......6-6-......................-
-+- OUTPUT
...
Fig. 10 Binary Pulse Patterns Obtained by
Shorting Various Counter Outputs
A. 2 PIN PATTERNS
JUUUUl
Il111UL-Jl1l1Ul
--itt-j+- - t - -t
1-+13T
T = RC
PINS 1 AND 2 SHORTED
B. 3 PIN PATTERN
~~
--ITt-
8T
7T
______~M~__
3T 1--\+5T+\ ""'1-1-----:21T-----...,.,1Ooj1
PINS 1, 3, AND 5 SHORTED
()
,
'..l'
9-44
,uA2240
Fig. 11
Continuous Free-run Operation Examples of Output
Vee
Vee
AC
MOD
j.LA2240
YAEG
-Ii!:I-
AC WAVEFOAM
TIME-BASE OUTPUT
0, OUTPUT
1YYYYYY1/ /fYYYYYYYl
I I I I I I 1/ /
IIIIIIII
rlSUlJ/ / --uuuu-
I!__
'---~~"""""''''''''''''--+--1i
I......._--
256 AC
----trL.1
JUL/
/---IlIl.
I.
.1
256RC
t//--IL.1
j·~Fl ..
I.--
Vee = Pm 16
GND = Pin 9
256 AC
~//----FL
I..
.1
256 AC
9-45
------
~
-----
~A3086
FAIRCHILD
General-Purpose
Transistor Array
A Schlumberger Company
Special Function Products
Connection Diagram
14-Pin DIP
Description
contains a differentially connected pair and
three individually isolated transistors. The part is
designed for general-purpose, low-power applications
for consumer and industrial applications_
~A3086
Cl
Bl
•
•
•
•
LOW INPUT OFFSET VOLTAGE
WIDEBAND OPERATION
LOW NOISE
MATCHED DIFFERENTIAL AMPLIFIER
Absolute Maximum Ratings
Power Dissipation (Note 1)
At TA = 25°C
At TA = 25°C to 55°C
At TA = 25°C
At TA = 25°C to 55°C
Voltages and Currents
Collector-to-Emitter Voltage,
VCEO
Collector-to-Base Voltage,
VCBO
Collector-to-Substrate Voltage,
VCIO (Note 3)
Emitter-to-Base Voltage, VEBO
Collector Current, Ic
Temperature Range
Operating Temperature
Storage Temperature
Pin Temperature (Soldering)
Ceramic DIP (60 s)
Molded DIP (10 s)
El,2
B2
C2
Each Transistor
B3
300mW
300mW
750 mW (Note 2)
750 mW (Note 2)
E3
Order Information
Type
Package
Molded DIP
~A3086
Ceramic DIP
~A3086
15 V
Code
9A
6A
Part No_
~A3086PC
IlA3086DC
20 V
Logic Diagram
20 V
5V
50mA
C5
14
E5
SUBSTRATE B5
13
12
C4
11
E4
10
B4
9
-40°C to +85°C
-55°C to +125°C
5
Cl
Noles
1. Derate at 5 mW I·e for TA > 85·C.
2. Total package.
3. Substrate must be connected to the most negative voltage to
maintain normal operation.
9-46
Bl
El,2
B2
C2
B3
C3
8
~A3086
/-lA3086
Electrical Characteristics
Symbol
TA = 25°C unless otherwise specified
Characteristic
Condition
Min
Typ
= 10 /-lA, IE = 0
20
60
V
Ic
= 1 rnA, IB = 0
15
24
V
Ic
= 10 /-lA,
20
60
V
5.0
7.0
V
Collector-to-Base
V(BR)CBO Breakdown Voltage
IC
Collector-to-Emitter
V(BR)CEO Breakdown Voltage
V(BR)CIO
Collector-to-Substrate
Breakdown Voltage
Emitter-to-Base
V(BR)EBO Breakdown Voltage
ICBO
Collector Cutoff Current
Ic
=0
= 10 /-lA, IC = 0
VCB = 10 V, IE = 0
VCE = 10 V, IB = 0
IE
ICEO
Collector Cutoff Current
hFE
Static Forward CurrentTransfer Ratio
(Static Beta)
VCE
=3 V
Input Offset Current
for Matched Pair
01 and 0211101-11021
VCE
= 3 V, IC = 1 rnA
Base-to-Emitter Voltage
VCE
=3 V
Magnitude of Input Offset
Voltage for Differential
Pair IVBE1-VBE21
VCE
Magnitude of Input Offset
Voltage for Isolated
Transistors 1VBE3-VBE41
IVBE4-VBE51,lvBE5-VBE31
V CE
VBE
~VBE
-;rr
Temperature Coefficient of
VCE
Base-to-Emitter Voltage
VCE(sat)
Collector-to-Emitter
Saturation Voltage
I~VlOl
~T
NF
IB
= 10 rnA
= 1 rnA
= 10/-lA
40
Unit
0.002
100
nA
See
Curve
5.0
/-lA
100
100
54
0.3
/-lA
0.715
0.800
V
= 3 V, IC = 1 rnA
0.45
mV
= 3 V, IC = 1 rnA
0.45
mV
= 3 V,
-1.9
mV/oC
0.23
V
1.1
/-lV/oC
3.25
dB
IE
IE
Ic
= 1 rnA
= 1 rnA, IC = 10 rnA
Temperature Coefficient of
Magnitude of Input-Offset
VCE
Voltage
Low Frequency
Noise Figure
IC
Ic
IC
Max
= 3 V, IC = 1 rnA
f = 1 kHz, VCE = 3 V,
IC = 100 /-lA, RS = 1 kQ
9-47
= 1 rnA
= 10 rnA
•
JLA3086
f.tA3086 .
Electrical Characteristics
Symbol
Characteristic
hIe
Forward CurrentTransfer Ratio
TA
= 25
0
C unless otherwise specified
Condition
Typ
Min
Max
Unit
Low Frequency, Small-Signal Equivalent-Circuit Characteristics
110
hoe
Short-Circuit
Input Resistance
Open-Circuit
Output Conductance
hre
Open-Circuit Reverse
Voltage-Transfer Ratio
hie
f = 1 kHz, VeE
kQ
15.6
f.tmho
1.8 x 10- 4
Vie
Y oe
Admittance
Characteristics:
Forward Transfer
Admittance
Input Admittance
Output Admittance
Y re
Reverse Transfer
Admittance
fT
Gain-Bandwidth Product
VeE
CES
Emitter-to-Base
Capacitance
VES
Ces
Collector-to-Base
Capacitance
Cel
Collector-to-Substrate
Capacitance
Yle
3.5
= 3 V, Ie = 1 mA
31 - j1.5
f
= 1 MHz, VeE = 3 V, Ie = 1 mA
0.3
+ jO.04
+ jO.03
0.001
See
Curve
= 3 V, Ie = 3 mA
= 3 V, IE = 0
550
MHz
0.6
pF
Ves = 3 V, Ie = 0
0.58
pF
Ves = 3 V, Ie = 0
2.8
pF
300
Typical Performance Curves
Noise Figure vs
Collector Current
2.
V~E 13.~ V
!-- As
I«~
== SOD n
== 25°C
TA
15
,,~' r--
~<)
,.<>
,.
. 0/1
~---
•
V
o~
1r;:
[
0.01 0.02
= 1000 n
= 25°C
I
15
0 05
01
0.2
COLLECTOR CURRENT -
O.S
rnA
1.0
-~ r--.
/
,.~
,<
/
V
.,"
R<)
~
K
L
10
I~
~oo k~l
'" ~5°C
~./y
V
COLLECTOR CURRENT -
9-48
:
2.
,.
/ 1 kHz
V
005
r-- :~E
25 I--TA
15
10 kHz
001 002
Noise Figure vs
Collector Current
3.
•
/'
kHz
--...-r
10 kHz
I
0.01 002
0.05
01
02
COLLECTOR CURRENT -
I
05
mA
10
~A3086
Typical Performance Curves (Cent.)
Forward Transfer Admittance
vs Frequency
I
COMMON-EMITTER CIRCUIT, BASE INPUT
-~TA
== 25<1C
VeE'" 3.0 V
'" 1.0 mA
40
."
E
1
30
'"
.. 0
wZ
~~
,,-!e
1
~I
0",
\
0
~o
oz
z<
-
",
00
~Z
01 0.2
0.5
1
2
5
10
FREQUENCY -
20
~l
Ie
~
I
II
,I.)
I~:~~IO~ j~:~~l
~
0
~'"
~o
09
0
V
~<
~~
/1
90
OZ
0:;:
."
Base-to-Emitter Voltage
Characteristic vs
Ambient Temperature for
Each Transistor
>
1
II
zZ
0<
AMBIENT TEMPERATURE _ °C
hV 1\
Q
0
Q"
I
10
Ves
MHz
1
vJ, ~ ~I. v
I
3
~'"
00
0
10-
Static Forward Current-Transfer
and Beta Ratio for
Transistors 01,02 vs
Emitter Current
120
5
1
1
~
!::
b o,
E
t;1
~
~
o
b co
-1.5
1
IJ
'I
== 10 mA
Ie
"'~
OE
:i
0
"
-05
Q
0
J,
COMMON-EMITTER CIRCUIT, BASE INPUT
TA '" 2S C
VeE == 30 V
;
Collector-to-Base Cutoff Current
vs Ambient Temperature
for Each Transistor
1.0 rnA
'gre IS SMALL AT FREQUENCIES
L SS THAN 500 MHz
~
05
FREQUENCY -
COMMON-EMITTER CIRCUIT, BASE INPUT
TA '" 25°C
VeE'" 3 0 V
'"o
~ g 05
0
0102
50 100 200
5
L
MH:z
Reverse Transfer Admittance
vs Frequency
~5
~~
'""
~
/
1
/
-20
(,)
ffi~
/
-z".o
I'
-10
~
15
/
~"
~~
~o
..!::
o
~
0i!i
o~
.;~
~
Output Admittance
vs Frequency
COMMON-EMITTER CIRCUIT, BASE INPUT
TA == 25°C
VeE'" 3.0 V
Ie
'" 1 0 rnA
b"
~
'" E
!;1E
20
<'"
..
0
~~
Input Admittance
vs Frequency
•
V"
/4
./
3
./
/
,I
Ii
Ii
1
INPU~ IOfFSET VOLTAGE . /
40.Q1 0.02
Ii0 05 0.1
o
:>
I I
0.2
0.5
EMITTER CURRENT -
•
1
rnA
10
o
J,LA3086
Typical Performance Curves (Cont.)
Input Offset Current for Matched
Transistor Pair 01, 02
vs Collector Current
Input Offset Voltage for
Differential Pair and
Paired Isolated Transistors
vs Ambient Temperature
4
VeE"" 3.0 V
5
.z.
a:
a:
:>
u
to
~
TA
- 25°C
3
'E
I
~
D.'
•
vc~
_I~.-
"3.J v
-
to
~
D.'
!;
z
.
0.05
t-
-
0.02
~
!
O.O~.':-D':-D:-'.D"""""D.':::05"'D~.'''--:D.::-.'"""'=D.':-,~,--:,-'-'C':--:-!'D
COLLECTOR CURRENT -
mA
0.1
25
vd, J.DJ
'" 25°C
TA
BOO
600
400
V
r-
"....
f
'00
o
0.1
2
3
4
5
8
1
COLLECTOR CURRENT -
8
75
AMBIENT TEMPERATURE -
Gain-Bandwidth Product
vs Collector Current
'000
50
9
10
mA
9·50
.-
-
mt
0.25
-25
'" 3.5 kn
hoe "" 15.6 J,lmho
..:.:..
'hr:'"
,~
-50
J
"110
TA " 'S'C : h" " 1.88 • 10-'
,
0
-75
vc't "'" 3.0
V h"
1 kHr:- hie
h
~ 0.50
V
100
~
> 0.7
D.'
Normalized h Parameters
vs Collector Current
100 125
GC
AT/t_
hoe
......
~V
1
/'
h"
ho,
D.'0.011/,;"
.0.02
hI,
~t-
V
h"
0.05 0.1 0.2
0.5
,
1
COLLECTOR CURRENT -
mA
10
,uA7392
DC Motor Speed
Control Circuit
I=AIRCHILO
A Schlumberger Company
Special Function
Description
The IlA7392 is designed for precision, closed-loop,
motor speed control systems. It regulates the speed
of capstan drive motors in automotive and portable
tape players and is useful in a variety of industrial and
military control applications, e.g., floppy disc drive
systems and data cartridge drive systems. The device
is constructed using the Fairchild Planar
epitaxial process.
Connection Diagram
14-Pin DIP
INPUTS
OUTPUT EMITTER
MOTOR DRIVE
OUTPUT
10
CLAMPING DIODE
V+
PULSE TIMING
REGULATOR
OUTPUT
PULSE OUTPUT
(Top View)
Order Information
Type
Package
IlA7392C
Ceramic DIP
IlA7392C
Molded DIP
Code
6A
9A
Part No.
IlA7392DC
IlA7392PC
Thermal Data
Thermal Resistance, Junction to Ambient
Molded (9A) 70°C/W Typ, 80°C/W Maximum
Ceramic (6A) 100°C/W Typ, 120°C/W Maximum
•
Absolute Maximum Ratings
Supply Voltage (V+), Vg,
V1Q, V11
N/C
TACH INPUT (+)
PRECISION PERFORMANCE
HIGH-CURRENT PERFORMANCE
WIDE RANGE TACHOMETER INPUT
THERMAL SHUTDOWN, OVER-VOLTAGE AND
STALL PROTECTION
INTERNAL REGULATOR
WIDE SUPPLY VOLTAGE RANGE 6_3 V TO 16 V
Regulator Output Current, 18
Voltage Applied to Pin 6
(Tachometer Pulse Timing)
Voltage Applied Between Pins 3
and 5 (Tachometer Inputs)
Continuous Current through
Pins 11 and 12 Motor Drive
Output ON
Repetitive Surge Current through
Pins 11 and 12 (Motor Drive ON)
Repetitive Surge Current through
Pins 10 and 11 (Motor
Drive OFF)
Power Dissipation
Storage Temperature Range
Operating Temperature Range
Pin Temperature (Soldering)
Ceramic DIP (60 s)
Molded DIP (10 s)
H
GND
Thermal and over-voltage shutdown are included for
self-protection, and a "stall-timer" feature allows the
motor to be protected from burn-out during extended
mechanical jams.
•
•
STALL TIMER
TACH INPUT (-)
The IlA7392 compares actual motor speed to an
externally presettable reference voltage. The motor
speed is determined by frequency to voltage
conversion of the input signal provided by the
tachometer generator. The result of the comparison
controls the duty cycle of the pulse width modulated
switching motor drive output stage to close the
system's negative feedback loop.
•
•
•
•
14
MOTOR
DRIVER (+)
24 V
15 rnA
7V
±6V
0.3 A
1.0 A
0.3 A
Internally Limited
-55°C to +150°C
-40°C to +85°C
9·51
~A7392
Block Diagram
SUPPLY
r-~~--~-----,--VOLTAGE
V+
I
SPEED
ADJUST
PULSE TIMING
t
MOTOR
DRIVER
INPUTS
I
PULS
V+
CLAMPING
r-________________~6~O~U~T~P~U~T~7--_T2~(~-,)--f(~+~)1~-----------------9~__-r1~O_,DIODE
TACHOMETER
INPUTS
(+)5
Y ..(
J;
rv
AJU
GENERATOR
(-::))331-....J>v'V'lf'r---;...._P_U_LS_E...,J
I
I
I
I
FREQUENCY TO
VOLTAGE CONVERTER
V+
8
REGULATOR
OUTPUT
I
I
I
I
I
PROTECTIVE
CIRCUITS
VOLTAGE REGULATOR
SECTION
I
~--~I---------------------------------------------------'STALLTIMER
IL_______________ I
~
9-52
_________
~
J.LA7392
#A7392
Electrical Characteristics
V+ = 14.5 V, TA = 25°C, unless otherwise noted
Voltage Regulator Section (Test Circuit 1)
Characteristic
Condition
Power Supply Current
Excluding Current into Pin 11
Min
Regulator Output Voltage
4.5
Typ
Max
Unit
7.5
10
rnA
5.0
5.5
V
20
50
mV
mV
Regulator Output Line
Regulation (.iVa)
V+ from 10 V to 16 V
V+ from 6.3 V to 16 V
6.0
12
Regulator Output Load
Regulation (.iVa)
la from 10 rnA to 0
40
Electrical Characteristics
mV
V + = 14.5 V, TA = 25 ° C, unless otherwise noted
Frequency to Voltage Converter Section (Test Circuit 2)
Characteristic
Condition
Min
Typ
Max
Unit
1.0
10
#A
10
25
50
mVpk
20
50
100
mVpk-pk
300
500
Q
50
55
%Va
Tachometer (-) Input Bias Voltage
2.4
Tachometer (+) Input Bias Current
V5 = V3
Tachometer Input Positive Threshold
(V5 - V3)
Tachometer Input Hysteresis
Pulse Timing ON Resistance
V6 = 1 V
Pulse Timing Switch Threshold
45
V
Output Pulse Rise Time
0.3
Output Pulse Fall Time
0.1
Pulse Output LOW Saturation (V7)
0.13
0.25
V
Pulse Output HIGH
Saturation (Va - V7)
0.12
0.2
V
-260
-180
#A
#s
#s
Pulse Output HIGH Source Current
V7 = 1 V
Frequency-to-Voltage Conversion
Supply Voltage Stability (Note 1)
VFV = 0.25 Va (Note 2)
V+ from 10 V to 16 V
0.1
%
Frequency-to-Voltage Conversion
Temperature Stability (Note 3)
VFV = 0.25 Va (Note 2)
TA from -40°C to +85°C
0.3
%
Electrical Characteristics
-340
V+ = 14.5 V, TA = 25°C, unless otherwise noted
Motor Drive Section (Test Circuit 3)
Characteristic
Condition
Min
Typ
Max
±20
mV
0.1
10
#A
2.5
V
1.6
V
#A
Input Offset Voltage
Input Bias Current
Common-Mode Range
0.8
Motor Drive Output Saturation
1.3
111 = 300 rnA
Unit
Motor Drive Output Leakage
V11 = Vl0 = 16 V
5
Flyback Diode Leakage
VlO= 16V,Vll =OV
30
#A
Flyback Diode Clamp Voltage
111 = 300 rnA
Motor Drive Output Off
1.3
V
Notes
1. Frequency·to-Voltage Conversion, Supply Voltage Stability IS
defined as.
VFV(16 V)
VS(16 V)
VFV(10 V)
VS(10V)
+
VFV(14.5 V)
VS(14 5 V)
1.1
3. Frequency-to·Voltage Conversion Temperature Stability is
defined as·
VFV(S5°C)
VS(S5°C)
x 100%
2 VFV IS the Integrated dc output voltage from the pulse
generator (Pin 7)
9·53
VFV(-40°C)
VS(-40°C)
VFV(25°C)
VS(25°C)
x 100%
•
,uA7392
~A7392
Electrical Characteristics (Cant.)
= 14.5 V, T~ = 25°C, unless otherwise noted
V+
Protective Circuits (Test Circuit 4)
;'
1
Typ
Min
Max
Unit
Characteristic
Condition
Thermal Shutdown
Junction Temperature
Note 4
Overvoltage Shutdown
Note 4
18
21
24
Stall Timer Threshold Voltage
Note 5
2.5
2.9
3.5
V
Stall Timer Threshold Current
Note 5
0.3
3.0
~A
160
°C
V
Notes
5. If stall timer protection
be grounded.
4 "Motor Drive" circuitry is disabled when these limits are
exceeded. If the condition continues for the duration set by the
external stall timer components, the circuit is latched off until
reset by temporanly opening the power supply input line.
not required, Pin 14 should
IS
Typical Performance Curves
Overvoltage Shutdown Voltage vs
Junction Temperature
Stall Timer Threshold Voltage vs
Junction Temperature
>
I 2
..
..
.
~
!:;
g
•
~22
,r-
~2
....
S 30
101
"-
"'
26
i
"~
i•
1
ii
ti
1
"-
24
-25
0
25
50
75
100
JUNCTION TEMPERATURE -
125
150
-25
25
50
75
ffi
Supply Current vs
Supply Voltage
'"
;::
"
100
JUNCTION TEMPERATURE -
"C
~
125
0:
0:
il
i
0
..
n
~
.
g
.
"
~
I
I
~
I
,/'
:3
o
16
SUPPLY VOLTAGE -
20
Y
24
'jF(5'f-
I
o
/
51
V
50
/
g
2
12
~
52
0:40
I
oj
m
54
I
•
~
Regulator Output Voltage vs
Junction Temperature
> 53
I-"'"
I
•
~
JUNCTION TEMPERATURE _ °C
0
..Ii
--
,
°C
~J ~125'~-
1
I
0
~
150
"- I.........
02
~
Regulator Output Voltage vs
Supply Voltage
'2
'\
04
~ 03
~
22
2D
-50
\
05
::!
:;I
•
~
,
ill,
06
g
;::
~
1\
~
~ 28
~
-50
i'-
Q
:
..15
y+ '" 145V
V+ '" 145
g~ 32
-
01
3•
" 34
23
Stall Timer Threshold Current vs
Junction Temperature
12
16
SUPPLY VOLTAGE -
9·54
20
V
24
48
""~ 47
4.
/
V
~
vi'" 14'j y~
0
..
~
n
~
m
JUNCTION TEMPERATURE _ "C
~
J.LA7392
Typical Performance Curves (Cont.)
Tachometer Input Hysteresis vs
Junction Temperature
Flyback Diode (03) Current vs
Flyback Diode Voltage
•
~
.00
I S6
~
VJ=14!SV I
4
::;
./
E52
~
~
50
~
::; 4
iU
/'"
• -----
~ 500
"
~
o
o
400
/
5300
U
""'200
.
t
4
Vj= 14 V-
42
-50
I
~
V
~
4
I &00
!z
V
"o 46
~
TJ == TA = 25°C-
'" 700
E
/"
-25
25
SO
75
100
125
I
~
~,oo
150
./
o
o
JUNCTION TEMPERATURE _ °C
FLYBACK DIODE VOLTAGE -
Motor Drive Output on Voltage vs
Ambient Temperature
Motor Drive Output on Current vs
Motor Drive Output on Voltage
"" 1600
E
~
"6
vI ,.Is v I
I
w 144
=
1400
TJ '" TA '" 25°C-
iii
!i
~ 142
g
~ 120'"
"Z 1000
U
o
~
!:;
~ 140
~
600
400
/
>
/
/
~
eo
'"
200
o
...
...~
/
800
a:Q
V
o
/
138
~"
136
~
134
./
~
o
15
/
132
'" 130
L
Test Circuit 1
14
13
12
-=-
11
5
10
6
9
7
8
REGULATOR VOLTAGE
V
-25
25
50
75
100
AMBIENT TEMPERATURE -
Test Circuits
4
V
,/""
-50
MOTOR DRIVE OUTPUT ON VOLTAGE - V
2
/'
":"
9-55
°C
125
150
ttA7392
Test Circuits (Cont.)
Test Circuit 2
20 kll
TACH INPUT
VOLTAGES
(-)
(+)
100 II
+
14
10 V-=-
10 kll
13
O.lI'F
100 II
TACH
INPUT
VOLTAGE
ADJUST
V = 0.3 Vp- p,
INOM
=
12
AC
4
11
5
10
6
9
1000 Hz
TACH
' - - - - - - - DC INPUT
100 kll
+
7
(INTEGRATED
FREQ-TO-VOLTAGE 111'F
CONVERTER
OUTPUT VOLTAGE)
PULSE
OUTPUT----...I
VOLTAGE
1 ·0025 1'F
8
100 kll
-= PULSE
14.5 V
1
'::"
TIMING
VOLTAGE
Typical Application Using Magnetic Tachometer
330 kll
9.1 kll
Rs
~
ch
SPEED
ADJUST
100 kll
10 kll
.01 I'F
::!:
J
2 kll
+
~
RF
100 kll
1
14
2
13
3
12
4
-5
-6
CF
"~~
l°h
9
I
~~
I
I
I
Rp
'::"
100 kll
I
7
r
-
CP
8~
o
1
5
10 V TO 16 V
F
1'
I
Typical Comp onent Values:
•
1
Cp = 4 RpF
=
CF
10 Cp to 1000 Cp depending on
system requirements
2 X stall time-out
Cs
=
RS
RMotor 2::: 5 Q
9-56
TACHOM ETER
(I = NOMI NAL
TACHOM ETER
FREQUEN CY)
FAIRCHILD
A Schlumberger Company
comp~ralO~>,.-,.",:. "<: " ::' ,:" :':~ .
,
,
,~' "
, ',.'
'
,---"t
,
,
T.lacornmunica~ons
"
Hi Rei Processing
i=ailchild SalH Q,ffrces "
,"
10-2
Hi Rei Processing
FAIRCHILD
A Schlumberger Company
JAN Qualified (MIL-M-38510) Level"B" Program
The JAN Program offers the customer a standard of
product processing, quality and reliability that is well
documented by the manufacturer and monitored by the
Defense Electronics Supply Center (DESC) of the U.S.
Government. The products are manufactured in the U.S.
in a government certified facility to the requirements of
MIL-M-38510 and individual product specifications as
called out in the MIL-M-38510 "Slash Sheets". The DESC
certification is based on standardized documentation for
design, processing, test methods, laboratory suitability
and personnel training. Facilities and documentation are
audited by DESC prior to certification and periodically
thereafter.
Hi Rei Processing
High Reliability (Hi Rei) processing to MIL-M-38510 & MILSTD-883 is performed by a totally dedicated Business
Unit within the Linear Division of Fairchild to serve the
unique Linear components requirements of our various
military customers. Fairchild Linear has been committed
to the Linear Hi Rei program for many years and intends to
continue to maintain a leadership position in that market
segment.
The Hi Rei program offers three levels of processing flows
as noted below that would normally satisfy a majority of
customer requirements.
• JAN-Level "B"-Full compliance to MIL-M-38510 JAN
program & OPL listings as published
by Defense Electronics Supply Center
(DESC), Ohio
• "OB" Flow -Conformance to Level "B" process
requirements of MIL-STD-883 to
Fairchild MIL temperature range data
sheet electricals.
-Compliance to Class "s" process
• Class "s"
requirements of MIL-M-38510 & MILSTD-883 including all wafer lot
acceptance criteria.
Fairchild Linear maintains a very active JM 3856 Oualified
Products List (OPL) Program and has maintained a
leadership position in the total number of Linear OPL's for
many years.
An outline of the JAN M38510 Class "B" flow is given in
Figure 1.
Linear 'QB' Flow (MIL-STD-883 Level "B")
Fairchild's 'OB' process flow can fill customer needs when
a desired product is not available on JAN OPL or when
system requirements call for a cost effective but reliable
alternative to the full JAN program. The product is processed to MIL-STD-883 methods as specified in Figure 3.
Electrical testing is performed to Fairchild data sheet limits
for appropriate electrical grade and Burn-In is performed
per Fairchild Standard Schematics.
Details of the above flows will be provided in the following
pages where each flow will be discussed separately.
• Custom Processing
-While the intent of the Linear Hi
Rei program is to standardize as
much as possible for cost
effective processing around
these three flows, certain
customer requirements may
dictate special processing. These
customer requirements are met
by "HL" specifications within the
Hi Rei organization. These HL's
reflect all the unique requirements of a customer drawing
and must be separately negotiated with our marketing department for acceptability of device
parameters and process requirements before an order is
entered by Fairchild.
Class "S" Flow
Fairchild Linear offers a complete capability to fulfill all
processing requirements of Class "s" at wafer fabrication,
assembly and environmental screening and test/finish on
selected popular devices. These acceptance criteria meet
all requirements called out in MIL-M-38510 and MIL-STD883 for Class "s" products. It is our intent to standardize
the processing of Class "s" products to the 'HS' flow
shown in Figures 4A-4C so that customer requirements
for Class "s" can be minimized.
10·3
HI Rei Processing
Fig. 1 JAN M38510 Process Flow
Class
8
MIL-STD-8838
Test Methods
Description
Preseal Visual
MTD2010
Condo B. Optimum Visual Criteria
Preseal Visual
Cond.B
Bond Strength
MTD2011
Bond strength is monitored on a sample
basis three times per shift per machine
Bond Strength
Cond.D
Seal
Devices are hermetically sealed for
compliance to MIL-STD-883 requirements
High Temp Storage
MTD 1008
Condo C Tstg
Seal
Bake
Cond.CMin
24 Hrs.
= 150°C
I
Condo C - 65°/150°C 10 cycles
Temp Cycle
Cond.C
Constant Acceleration
MTD 2001 (Note 1)
Condo E 30000 G's X" X", Y" Y2
Centrifuge
Condo E
Y,Only
Hermetic Seal
MTD 1014 (Note 1)
Condo B Fine-Radiflo 5x10- 8 cc/sec
Condo C Gross-FC43/Hot 10-3 cc/sec or
Gross-FC78Nacuum 10- 5 cc/sec
Hermeticity
Cond.AlB
Cond.C
Pre Burn-in
Electrical
25°C dc electrical testing
to remove rejects prior to
submission to burn-in screen
Pre B/I Elect
25°Cdc
Burn-in Screen
MTD 1015 (Note 2)
Cond A, Cond B, Cond C
Cond D, Cond E, Cond F
Post Burn-in
Electrical
Post Burn-in electrical screening to cull
out devices which failed as a result of
burn-in. Test Parameters may include
25°C dc, 125°C dc, 55°C dc, 25°C dc,
25°C ac and 25°C Functional tests
Quality Conformance
Inspection
MTD5005
Group A Electrical Characteristics
Group B Package oriented Tests
Group C Life Tests-Periodic Conformance
Group D: Environmental Tests Periodic Conformance
External Visual
MTD2009
3X, 10X magnification Verify dimensions,
configuration, lead structure, marking
and workmanship
Temperature Cycle
MTD1010
I
Reliability
Ordering
Burn In
160 Hrs 125°C
Figure of Merit
Part Number
Part Marking
Notes
1. Not Applicable for TO-3 Cans
2. Time Temperature Curve (method 1015) may be used.
Pst B/I Elect
25°C dc 10% PDA
OtherDC&AC
tests per slash
sheet requirement
1
Quality
Conformance
GpAandB
External
Visual
100%
15
JM38510/
10101BCB
JM38510/
10101BCB
3. RELIABILITY Figure of Merit is the Reliability Improvement
Factor from RADC Reliability Notebook, Vol. II,
RADC-TR-67-108, TableXII-6, page 419.
10·4
Hi Rei Processing
Fig. 2
JAN Part Numbering System
J
101
M 38510/
B
01
~
G
~
T
JAN Designator
Lead Finish
Defines
Device
Type
Cannot be marked with "J"
unless qualified on Part I
or Part II of QPL-38510
c
A Hot Solder DIP
B Tin Plate
C Gold Plate
X Any of the above
Processing Level
General Procurement Spec.
S
B
C
Refers to Detail Spec
Package Type
1010pAmps
102 Voltage Regulators
103 Comparators
104 Interface
106 Voltage Followers
1073-Terminal Voltage Regulators
108 Transistor Arrays
109 Timers
110 Quad Op Amps
1.12 Quad Comparators
113 D/A Converters
115 Negative Voltage Regulators
117 Adjustable Voltage Regulators
A 14-pin % x % Flatpak
B 14-pin % x 'Ie Flatpak
C 14-pin % x % DIP
D 14-pin % x % Flatpak
E 16-pin%x%DIP
F 16-pin % x % Flatpak
G 8-pin Can
H 10-pin % x % Flatpak
I 10-pin Can
J 24-pin V2 x 1% DIP
K 24-pin % x % Flatpak
L 24-pin % x '/2 Flatpak
X 3-pin TO-5 Can
Y 2-pin TO-3 Can
Z 24-pin % x % Flatpak
Linear JAN Generic Part Numbers-Examples
JM3851 01
01
02
03
04
101
741
747
101A
108A
9614
9615
78M12
78M15
102
723
103
710
104
55107
106
102
107
109
108
711
78M05
05
06
07
08
09
7805
7812
7815
7824
7912
7915
111
3045
109
555
556
110
148
149
112
139
113
DAC08
115
79M05
117
78MG
79M12
4136
79M15
117H
124
7905
117K
Note
Dated material. Please contact Fairchild for latest revisions.
10-5
10
•
Hi Rei Processing
Fig.3
QB Flow MIL-STD-883 Level-B
Class
B
MIL·STD·883B
Test Methods
Description
Preseal Visual
MTD2010
Condo B. Optimum Visual Criteria
Preseal Visual
Cond.B
Bond Strength
MTD2011
Bond strength is monitored on a sample
basis three times per shift per machine
Bond Strength
Cond.D
Seal
Devices are hermetically sealed for
compliance to MIL·STD-883 requirements
High Temp Storage
MTD 1008
Condo CTstg = 150°C
Bake
Cond.CMin
24 Hrs.
Condo C -65°/150°C 10 cycles
Temp Cycle
Cond.C
Constant Acceleration
MTD 2001 (Note 1)
Condo E 30000 G's X" X2, Y" Y2
Centrifuge
Condo E
Y,Only
Hermetic Seal
MTD 1014 (Note 1)
Cond. B Fine-Radiflo 5x10- s cclsec
Condo C Gross-FC43/Hot 10 -3 cc/sec or
Gross-FC78Nacuum 10-s cc/sec
Hermeticity
Cond.AlB
Cond.C
Pre Burn-in
Electrical
25°C dc electrical testing
to remove rejects prior to
submission to burn-in screen
Pre BII Elect
25°Cdc
Burn-in Screen
MTD 1015 (Note 2)
Cond A, Cond B, Cond C
Cond D, Cond E, Cond F
Post Burn-in
Electrical
Post Burn-in electrical screening to cull
out devices which failed as a result of
burn-in. Test Parameters may include
25°C dc, 125°C dc, 55°C dc, 25°C dc,
25°C ac and 25°C Functional tests
Quality Conformance
Inspection
MTD5005
Group A Electrical Characteristics
Group B Package oriented Tests
Group C Life Tests-Periodic Conformance
Group D: Environmental Tests Periodic Conformance
Quality
Conformance
Gp A and B
External Visual
MTD2009
3X, 10X magnification Verify dimensions,
configuration, lead structure, marking
and workmanship
Generic Data
Available
GpCandD
Seal
I
Temperature Cycle
MTD 1010
I
Burn In
160 Hrs 125°C
Post BII Elect
25°C dc & Funct
125°Cdc
-55°Cdc
25°C ac Sample if
apply per Data Sheet
I
Notes
1. Not applicable for T0-3 Cans.
2. Time Temperature Curve (method 1015) may be used.
10-6
Hi Rei Processing
Class "S" Processing
The Linear Division has designed a Class"S" flow for all
processing steps from Wafer Fabrication through
Assembly, Test, Burn-In and Finish that will meet the
requirements of majority of customers as well as the
applicable military specifications and thus reduce the need
for custom Level "s" process flows.
Fig.4A
The flow charts that follow provide the major steps and
acceptance criteria utilized for the processes and should
form the basis for any Level "s" business negotiations with
Linear Marketing. These flow charts will also provide a
prospective customer with Fairchild Linear's capabilities in
Level "s" processing.
Class S: Minimum Wafer Lot Acceptance Steps
CV TEST WAFERS FOR
EVAPORATOR
CLEANLINESS
AU THICKNESS
MEASUREMENT
TOP SIDE METAL
THICKNESS
MEASUREMENT
SAMPLE PROBE
TEST FOR
DIFFUSION
PARAMETERS
100% ELECT
DIE SORT
WAFERS
VISUAL INSPECTION"
ACCEPTANCE FOR DIE
BANK WITH FULL
TRACEABILITY
SEM ACCEPTANCE OF METAL
PATTERN; MIL-STD-883
METHOD 2018
CLASS "s" DIE
INVENTORY
•
GLASSIVATION THICKNESS
MEASUREMENT
Note
All wafer lot acceptance is done per MIL-STO-883 Method 5007,
Table I.
10-7
Hi Rei Processing
Fig.48
Class S Assembly Flow
INCOMING CLASS "S"
WAFERS WITH TRACE ABILITY
DIE VISUAL
CONDITION "A"
'-..,..~ METHOD 2010
DIE ATTACH
DIE SHEAR
MONITOR
METHOD 2019
BOND PULL
MONITOR
METHOD 2011 '-_~
WIRE BOND
NON-DESTRUCTIVE
BOND PULL
METHOD 2023
INTERNAL VISUAL
CONDITION "A"
METHOD 2010
QC INTERNAL VISUAL CONDITION "A"
CUSTOMER SOURCE PRE-CAP
IF REQUIRED
SEAL
Note
Piece part traceability maintained when required.
10-8
Hi Rei Processing
Fig.4C
Class S Test, Burn-In and
Final Acceptance
Class S Environmental and
Finish Processing
ASSEMBLED CLASS "S" LOT
600-1000 PIECE MAX. AT SERIALIZATION
PRE-BURN-IN ELECTRICAL
25°C READ AND RECORD (DC ONLY)
STABILIZATION BAKEMETHOD 1008
CONDITIONC
BURN-IN 240 HOURS AT 125°C OR
PER FIGURE 1015-1 OF MIL-STD-883
TEMPERATURE C'VCLlNGMETHOD 1010
CONDITIONC
POST-BURN-IN ELECTRICAL
25°C READ AND RECORD
CONSTANT ACCELERATIONMETHOD 2001-Y,
CONDITIONE
POST-BURN-IN ELECTRICAL
+ 125°C AND - 55°C SCREEN
VISUAL INSPECTIONMETHOD 2009
FINE AND GROSS LEAK TEST
METHOD 1014
PARTICLE IMPACT NOISE
DETECTION (PIND)METHOD 2020
CONDITION A ONLY
GROUP A-QUALITY CONFORMANCE
INSPECTION 25°C, +125°C, -55°C, AC
METHOD 5005
FINE AND GROSS LEAK TESTMETHOD 1014
RADIOGRAPHIC
(X-RAY) (2 VIEWS)
METHOD 2012
EXTERNAL VISUAL AND PACK
SERIALIZATION AND MARKING
(4 CHAR. MAX. AND ON FLATPACK
SERIALIZATION ON BonOM ONLY)
LOTQCI
INSPECTION
PER METHOD 5005
SHIP
•
Note
This is a general overview flow and specific packages may have
unique requirements other than specified.
10-9
FAIRCHILD
A Schlumberger Company
11·2
Package Outlines
FAIRCHIL.D
A Schlumberger Company
1o-Pin Flatpak
In Accordance with JEDEC TO-91
==:~~I:~:
':IF
~.___. . ~.370
:=1=1:::==:::11:
:~~~ ~~ ~~l+--I
(9 40)
.250 (6 35)
~
._L. L,"(O "" I--.~""~
.004 (0 102)
.020 (0 508)
3F
Notes
Pons are tin'plated alloy 42
HermetIcally sealed alumona package
Package weIght is 0.26 grams
f
.070 (1 78)
.050 (127)
.240 (6 10)
10-Pin Metal Package
Similar to JEDEC TO-3
.100 (2 54)
.380 (9 65)
.350 (8 90)
1 .08012 03)
J...
f-----CI+r~~~~;=~IJJ~~S~E~AT~IN~G
I
PLANE
.300 (7 26)
.250~r
35) _~ ~ ~ ~~
5H
Notes
Base IS heavy gold plated over
nickel plated steel
Can is nickel plated steel
Pons are heavy gold plated over
nickel plated alloy 52
All pins electrically isolated from
case wIth glass
Package weIght IS 17 grams
• Similar to JEDEC TO·3 except for number of
pons, pin length and pin diameter
II .033 (0 84)
I-- .028 (0 71) DIA
-+j
1.197 (30 40)
-1.177!2990)-1
.600 (15 24)
.580 (14 73)
GLASS
-(10 PLACES)
.161 (409)
.151 (384)DIA
2 HOLES
~.180(4
57)
.150 (3 81) R
2 PLACES
All dImensIons on onches bold and mIllimeters (parentheses)
11·3
Package Outlines
10-Pin Metal Package
In Accordance with JEDEC TO-100
S-Pin Metal Package
In Accordance with JEDEC TO-99
1-_____..... 370 (9 40)DIA
.370 (9 40)
.350 (8 89)
DIA
.350(889)
1- :~~~ l: g~:I J
.335 (8 51)DIA-1+_----j
.315 (8 00)
lOlA
+
.040 (102)
.020 (0 51)
+
t
== C:;;;:::;;:::;;::::;:;;:J~
=~i
I
.040(102)
.020 (0 51)
.185 (4 70)
REF.
.165(4YPLANE
~
[I]
SEATING
-r--i--PLANE
.040 (102) .565 (14 35)
.010 (0 25) .5.0 (12 70)
~
t
.185 (4 70)
165 (4 19)
-t 1
t
8 PINS
.019 (0 48)
.016 (0 41)
DIA
t
nn n nn
UU U
uu
REF PLANE
SEATING PLANE
.040 (102) .565 (14 35)
.010 (0 25) .500 (12 70)
t
GLASS
t.
T.P.
5U
5W
Notes
Pms are extra heavy gold-plated kovar
Ten pms
Eyelet is extra heavy gold-plated kovar, glass
foiled with ceramic standoff
Can is grade A nickel
High RTH package
Package weight is 1.32 grams
Notes
Pms are tin-plated over nickel plated kovar
Seven pms thru, pm no 4 connected to case
Eyelet IS nickel plated kovar, glass filled with
ceramic standoff, tm plated outside metal
surface
Can IS grade A nickel, tm plated outside
surface
Package weight IS 1 22 grams
5X
Notes
Pms are lin-plated over nickel-plated kovar
Nme pms thru, pm 5 IS connected to case
Eyelet IS nickel plated kovar, glass filled with
ceramic standoff, tin plated outside metal
surface
Can IS grade A nickel, tm plated outside
surface
Package weight IS 1.32 grams
5Y
Notes
Pms are tin-plated over nickel plated kovar
Ten pms
Eyelet IS nickel plated kovar, glass filled with
ceramiC standoff, tin plated outside metal
surface
Can IS grade A nickel, tm plated outside
surface
Package weight IS 1.32 grams
All dimensions in mches bold and millimeters (parentheses)
11-4
Package Outlines
14-Pin Ceramic Dual In-Line
In Accordance with JEDEC TO-116
.025 R (0 635)
"""-NOM
6A,8A
Noles
PinS are tin-plated alloy 42
Pms are Intended for insertIon In hole rows
on 300 (7 620) centers
They are purposely shipped with "positive"
misalignment to facilitate insertion
Board-drilling dimenSions should equal your
practice for 020 (0 508) diameter pin
Hermetically sealed alumina package
Package weight IS 2 0 grams
525)1~
1-.375 (9
NOM
0
15
00
16-Pin Ceramic Dual In-Line
.785 (19 939)
750 (19 050)
----I
I
:~;;;;i: : : : : : : J~~""~"
~ ~
r-
I
68,88
Noles
PinS are tin-plated alloy 42
PinS are Intended for Insertion
.065 (1651)
045 (1 143)
.320 (8 128)-1
..- 290 (7 366) I
.-~~''"'"'
200 (5 080)
MAX
+
.150 (3 840)
. 125 (3175)
J--
-_- - - - - - - -- - -
Il
I
I
~--
I
-1'"
.110 (2 794)
.090 (2 286)
.037 (0 940)
.029 (0 686)
STANDOFF
WIDTH
-
-
,---,---,---.1
.020 (0 508)
~
S~.4\TING
f PLANE
-',
---:1
~~
.020 (0 508)
.016 (0 406)
375 (9 525)
NOM
045 (1 143)
.015 (0 381)
All dimensions In Inches bold and millimeters (parentheses)
11-5
In
hole rows
on 300 centers (7 62)
Units are purposely shipped with "positive"
misalignment to faCilitate msertlon
Board-drlllmg dimenSions should equal your
practice for .020 (0 508) diameter pm
Hermetically sealed alumma package
Package weight IS 2 0 grams
• The 037 - 027 (0 940-0 686) dimenSion
does not apply to the corner pms
•
Package Outlines
40-Pin Ceramic Dual In-Line
Side Brazed
r---In n
1
2020 (55 880) ---.~
1980 (50 292)
20
025 (0 6350)
590 (14 986)
~
C,,2,,'. . . .....,"".,.....,.,;ffi....
R
L_
'i'R;r;!;.............-...,....
565
~~~;;~
060(1 524)
040(1016)
~~:~~NG j
61
L
II
Notes
610(15494)
590(14986)
;~g~~~~:;
11-dJ
PinS material nickel gold-plated kovar
Cap IS kovar
Base
F="1r=~
IS
ceramic
CavIty size IS 310 X 310
Package weIght IS 6 5 gram
~~~~~~~~~~~IIW~~~~~~~~~I!!~ ~ Lg~~~g;~~~) j
--J
175 (4 445)
125(3175)
,:
----J
-I
1I
110(2794)1
045 (1 143)
040(1016)
090 (2 286»)
TYP
'i
II
---
~
085 (2 159)
075(1905)
020 (0 508)
016 (0 406)
TVP
675(17145)
MAX
8-Pin Ceramic Dual In-Line
1.392 (9 957),
IA
.374 (9 500)
I'll
I
.261 (6629)
.243 (6 172)
.025 R (0 635)
NOM
-~ ~--.-.-.........rr!
6T,8P
15°
0°
.012 (0 305)
.009 (0 229)
STANDOFF
WIDTH
.110 (2 794)
.050 (2 286)
All dImensIons In Inches bold and millimeters (parentheses)
11-6
Notes
PinS are tin-plated alloy 42
PinS are Intended for Insertion in hole rows
on 300 centers
Units are purposely shIpped WIth "posItive"
mIsalignment to facIlitate Insertion
Board-drilling dImensions should equal your
practIce for 020 (0.508) dIameter pin
HermetIcally sealed alumina package
Package weight IS 1 0 grams
Package Outlines
14-Pin Ceramic Dual In-Line
Similar to JEDEC TO-116
r--.
I !\
I
!\
7B5 ( 1 9 . 9 3 9 ) - - 1
:750(19050),
A A
I
7
.025 R (0 635)
.2Bl (7.137)
.263 (6 680)
:;"'---NOM
7A
Notes
Pms are tm·plated alloy 42
Pms are lOt ended for msertlon 10 hole rows
on 300 (7.62) centers
Units are purposely shipped with "positive"
misalignment to facilitate insertion
Board·drillmg dimensions should equal your
practice for 020 (0 508) diameter pm
Hermetically sealed alumina package
Package weight IS 1522 grams
Similar to JEDEC TO·116 except for
package width
L~..,.....,.-.........,...........-........-r~
.065 (1651)_1
.045 (1 143)
16-Pin Ceramic Dual In-Line
78
Notes
Pms are tm-plated alloy 42
Pms are mtended for mserlion In hole rows
on 300 (7.62) centers
Units are purposely shipped with "posllive"
misalignment to faCilitate msertlon
Board-drilling dimensions should equal your
practice for 020 (0 508) diameter pm
Hermetically sealed alumma package
Package weight IS 2.2 grams
'The 037- 027 (0.940-0.686) dimension
does not apply to the corner pms
~ ~.065(1651)
.045 (1 143)
~
.200 (5 080) b=o;::=;=;:::::;==;:::r=;:::::;==;:::;=o;::=;=;;::::::r=;'::l
MAX
~
t--: ,
i
I
.150(3810)
.125(3175) ~
.110(2794)
.030 (2 286)
.037 (0940)
.027 (0686)
STANDOFF
WIDTH
All dimensions In mches bold and millimeters (parentheses)
11-7
Package Outlines
24-Pin Ceramic Dual In-line
r---
1.284 (32 61)
1.238 (3145)----j
11\1\1\1
(SEE NOTE)"
\1\1\1\
1
I
7L
.025 (064)
NOM
.546 (13 87)
.514 (13 06)
(SEE NOTE)"
~~~~~~~~
---I
L
.100 (2 54)
.060 (153)
~~;:;;;;;:;~~:;:;:;:;;l)
1=
618 (15 70)--1
1,.610 (15 49)
.050 (1
27)
.025
(064)
,~
f
.110 (2 79)
.090 (2.29)
TYP
1
-j
II
.037 (094)
.027 (068)
STANDOFF WIDTH
TYP
r·
SEATING
PLANE
,I
Notes
Pons are ton-plated alloy 42 or equivalent
Package material is alumona
Pons ontended for onsertion in hole rows on
.600 centers (15.24)
They are purposely shipped "positive"
misalignment to facilitate insertion
Cavity size is .245 X .245 (6.22 X 6.22)
Package weight IS 7.1 grams
These dimensions include misalignment and
glass over-run etc.
ThiS dimenSion is measured from centerline to
centerlone of pons
.020 (0 51)
-II-- .016 (0 41)
I.....
TYP
14-Pin Ceramic Dual In-Line
I----:~~g
.
1--_..
g: ~~~ - - - - · 1
450 (11 43)
.420 (1067)
D
--1I
-.--~~~~~~~~~~~~
.301 (765)
.275 (6 98)
V
.050(127)
RADIUS
7N
_t__ L....C8::.-..:::;;;:::::c:;::::;::::r:;:=r;:;:::.-,::::..~
L
'M" ~,~" '" ~.::::: ;~i
.065 (165)_1
.045(114)
rn
.110 (2 79)
.260 (6 60)
.045 (114)
~.025(064)
t--=l ¥ li~M
III II U--!- ~~:~~G :~~g~~~
.165 (419)
.125 (3 18)
I
,
1----1
__
.110 (2 79)
.037 (094)
.090 (2 29)
.027 (069)
STANDOFF
WIDTH
--III......020 (0 51)
.016 (0 41)
I\-.310 (7 87)-1I
.290 (7 37)
All dimensions in inches bold and millimeters (parentheses)
11-8
Notes
Pins are gold-plated kovar
Base is alumina
Lid is gold-plated kovar
Pins are ontended for insertion in hole rows
on .300" centers (7.62)
Board-drilling dimensions should equal your
practice for .020 (0.51) inch diameter pin
Package weight is 1.3 grams
Package Outlines
24-Pin Ceramic Dual In-Line
Side Brazed
r
"-
1.212 (30 785)
•
1.188(30175)--'-1
,
f
1211109 8 76 5 4 3 2 1
.025 (0635)
~R
590(14986)
.565 (14 351)
L__
7R
131415161718192021222324
[.500(12700)J
.480(12192)
....Il.060 (1 524) j.610 ( 1
494)
;t5
.040 (1016)
.590 (14 986)
.095 (2 413)
.065 (1 651)
,06011524)
SEATI~:0Ii01mmmm~q
*
T
PLANE
II
----T--+
I
·f· I
.125(3175)
MIN
I
~
.160 (4 064)
.110(2794)
Iii ~h
__
.110(2794)
.090 (2 286)
TYP
-.------1
.450 (11 43)
.250 (6 35)
I
r
.500 (12 700)
.480 (12192)
-
Base IS ceramic
Cavity size IS 250 X 250
Package weight IS 3 85 gram
.011 (0279)
.009 (0 229)
~.675J~~415)~
.045(1143) .020(0508)
.040 (1016) .016 (0 406)
TYP
TYP
a-Pin Metal Package
Similar to JEDEC TO-3
1--
Notes
Pms are nickel gold-plated kovar
Cap IS kovar
.875 (22 225) DlA MAX
1
I
.100(254)
.085 (216)
....l
,
+-~I=:~I==~====~~=~~=~~~~===~:::=t==::lt ~~:~~NG
.~~g l~ ~~~
.L.________
~ ~ -II~~
.042 (1 07) DIA 8 PLACES
.039 (0 99) TYP
BG
Notes
PinS are gold-plated kovar
7 pinS through. pin 4 connected to case
Package weight IS 1 22 grams
. 188 (4 78) R MAX.
2 PLACES
All dimenSions In Inches bold and millimeters (parentheses)
11-9
•
Package Outlines
4-Pin Molded Single Wing
.405 (10 29)
.365 (9 27)
.265 (6 73)
.235 (5 97)
.150 (3 81)
.100 (2 54)
8Z
II
;;;;==W==>===::::I..-l
T [
'---....l,---I...u ;:;
060 (1 52)
.045 (114)
.030 (0 76)
.023 (0 58)
.024 (0 61)
.018 (046)
Package matenal IS plastic
Package weight IS 1 2 grams
::~g ~~ ~~~ ==F=~fj'l-!*(,-~=-=!~",!=:...=-,=l)!_I~_;;;_;;;_;;;-;;;-~;;;-~;;;-;;;-;;;-;;;-~=+t-*L--.
r
Notes
Pins are tin plated copper alloy
Mounting tab IS electrically Insulated from pinS
Mounting tab IS tin plated copper alloy
Board-drilling dimenSions should equal your
practice for 033 (0 84) d,ameler pinS
This package IS Intended to be mounted With
the tab flush With the top of the P C board or
heat sink A no 4 screw may be used to
secure the package Thermal compound IS
recommended
.068(173)
.038 (097)
14-Pin Molded Dual In-Line
In Accordance with JEDEC TO-116
1-----.
760 (19 3 0 ) - - - - 1
I
A A >740(1880)~ 1\ 1\ I
~l:~ ::::::: ~~:'"'"'"
II
---I I--
'.060 (1 52)
.040 (1 02)
SEATING
PLANE
[020 (0 51)
MIN
9A
Notes
PinS are solder dipped copper alloy
PinS are Intended for insertion In hole rows
on 300 (7 62) centers
Units are purposely shipped With "positive"
misalignment to faCilitate insertion
Board-drilling dimensions should equal your
prachce for 020 (0 51) diameter pin
Package material IS plastic
Package weight IS a 9 grams
All dimensions In Inches bold and millimeters (parentheses)
11-10
Package Outlines
16-Pin Molded Dual In-Line
.760 (19 3 0 ) - - - - - 1
.740 (18 80)
1
r"-I r'\ !l I
8
.260 (6 60)
.240 (610)
.030 (0 76)
NOM
~~9~~~"=T~~=T~~1~6~
~
.180 (4 57) hr-r-r-.-.-.-r-r-r---.r-r--r-r---.--.-r-1
MAX
SEATING
PLANE
.150 (3 81)
.125 (318)
98
Notes
Pms are solder dIpped copper alloy
PIns are Intended for msertlon m hole rows
on 300 (7 62) centers
Unots are purposely shIpped with "poslllve"
mIsalignment to facilitate mserllon
Board-drilling dImensIons should equal your
practIce for 020 (0 51) dIameter pIn
Package material IS plastIc
Package weIght IS 1 0 grams
All dImensIons In mches bold and mIllimeters (parentheses)
11-11
Package Outlines
a-Pin Molded Dual In-Line
f
.030 (0 76) R
NOM
.260 (6 60)
.240 (610)
!
5
060 (1 52)
9T
Notes
PinS are solder dipped copper alloy
PinS are Intended for insertion In hole rows
on 300 (7 62) centers
Units are purposely shipped With "positive"
misalignment to facilitate insertion
Board-dniling dimenSions shOlJld equal your
practice for 020 (0 51) diameter pin
Package matenal IS plastic
Package weight IS 0.6 gram
8
I
.040(102) ....
t
/::::r,"""",..=r-,:;::r-.::l~130(330)
.110 (2 79)
SEATING
PLANE
===-.-1-50-(3-8-1-)
f---"Y,
.125 (318)
f
.020 (0 51)
MIN
.050 (127)
.025 (0 64)
L.375 (9 53)_1
NOM
I
I
3-Pin Molded Package
Similar to JEDEC TO-92
I..-.195 (4 95)-i
I .175 (4 45) I
T
.190 (4 83)
.170 (4 32)
,,
/
I
\
I
-~,
SEATING
PLANE
EI
.055
.045
.105
.095
(140)
(114)
(2 67)
(2 41)
Notes
PinS are solder dipped copper alloy
Pin no 2 connected to die pad
Package matenalls plastic
Package weight IS 0 19 gram
• Similar to JEDEC TO-92 except for pin
dimenSions
--4----~
I-' 185 (4 70)-1
I .155 (3 94) I
-,----- r-----;.
.019 (0 48)
---.i.015 (0 38)
-+
LEAD NO.3
LEAD NO.2
LEAD NO. 1
.105 (2 67)
.080 (2 03)
All dimenSions In Inches bold and millimeters (parentheses)
11-12
Package Outlines
16-Pin Ceramic Dual In-Line
- - - - . 8 0 8 (20 532) _ _ _ _ _ 1
.792 (20 117)
1_ _
I
L·510 (12 954)
.490(12446)-
1_
.100(2540)
:c:~:]: ~~
FB
Notes
Pms are nIckel alloy 42 or kovar
Base IS alumma
Cap IS alumma
Pms are mtended for msertion in hole rows
on .300" centers
Board drilling dimenSIons should equal your
practice for .020" dIameter lead
Pm finIshes avallable-tlO or gold plate
Cavity size is .220 X 280
.310 (7 874)
.290 (7 366)
.283 (7 188)
.166 (4 216) .094 (2 388)
""1"':£ "!."'! ~~:::';:;~~=;:~::;;:;;;::=;"",.0:f3;~~~~NG
~I ~I:,,(O..,
.125(3175)
.110 (2 794)
.090 (2 286)
TYP & NONACCUM
MIN
~
~.016 (0 406)
.065 (1 651)
.045 (1.143)
1.277 (7 036)'1
L-...J
.012 (0 305~ .....
.010 (0 254)
\ •. 310 (7 874)
.290 (7 366)
,I
--
t·
2-Pin Metal Package
Similar to JEDEC TO-39
3 70 (940)
.350 (8 8 9 ) DIA
I_:~~~ ~~ g~~I .1
DIA
.034 (0 864)
.017 (0432)
+
=:::t== t::;::::::;;::::::;:~
--,-t.185 (4 70)
.165 (419)
--+'
Fe
-SEATING PLANE
Notes
PIOS are gold plated kovar
Pins 1 and 2 are electrically isolated
WIth glass
Pm no 3 connected to case
Eyelet is gold plated kovar
Can IS grade A nickel
Package weight is 1.23 grams
• SImilar to JEDEC TO-39 except for
can height
.565 (14.35)
3 PINS_
.500 (12 70)
0.19 (0 48)
0.16(041)
U
DIA
1+-----+-.200 (5 08)
T.P.
n
O_ _t<--
GLASS
All dimenSIons m inches bold and millimeters (parentheses)
11-13
•
Package Outlines
18·Pin Ceramic DIP
Side-Brazed
GI-
'910(23114)
.890 (22.606)
.434(11.024)
.428 (10.8712)-1
.155 (3 937) .090 (2 286)
.110 (2 794) .070 (1.778)
.045 (1.143)
-t---:=t=F====================::L-----. .025 (0 635)
~
.160 (4.064)
.140 (3 556)
~~
~~
FD
Notes
Pons are nickel alloy 42 or kovar
Base IS alumona
Cap IS alumona
Pons are ontended for onsertion on hole rows on
.300" centers
Board dnillng dimenSIons should equal your
practIce for .020" dIameter lead
Pon fonlshes avaIlable-tin or gold plate
Cavity sIze IS 220 X 280
All dImenSIons In Inches bold end mllhmeters (parentheses)
11·14
SEATING
PLANE
t
.054 (1372)
TYP
.020 (0 508) TYP
.016 (0 406)
.012 (0.305)
.009 (0.229)_ ......
TYP
I
1-.310 (7 874!_
.290 (7 366)
Package Outlines
16-Pin Ceramic Dual In-Line
.025 R (0 635)
NOM
.320 (8 128)
.290 (7 366)
~I
.040 (1 016)
---------------..
.20~~5X080)
.150 (3 810)
.125 (3
1~:)10
(2 794) ,
.090 (2 286)
.O~O (0 5~:~ TING
..J..... PLANE
It
~
..,
.020 (0 508)
~016 (0 406)
.045 (1 143)
.015 (0 381)
~ .375 (9 525)~
1NOM
15'
./
0'
FW
Notes
PinS are tin·plated alloy 42
PinS are Intended for Insertion In hole rows
on 300" centers
They are purposely shipped with "positive"
misalignment to facIlitate insertion
Board·drilling dimenSions should equal your
practice for .020 Inch diameter Pin
Hermetically sealed alumina package
Package weight is 2 2 grams
'The 037 - .027 (0 940-0 686) dimension
does not apply to the corner pinS
•
All dimenSions in Inches bold and millimeters (parentheses)
11·15
Package Outlines
3-Pin Molded Package
Similar to JEDEC TO-220
610(1549)~t
_
580(1473)
120 (3 05)
100 (254) -
I
250 (6 35)
200 (5 08) •
--t..------I
«(
415(1054)
395
03)
540(1372)_
.500(1270)
•
I
110 (2 79)
~~~.090~(2
rt
:iii:
29j)
1.210(533)
320(813)
300
62)
0
190 (4 83)
060 (1 52)
045 (1 14)
145 (3 68) DIA
141 (358)
265 (6 73)
, .235 (5 97)
1
~~~ ~: ;~-~-'-----f----+!I
_ _ _--L_ _ _. -
SEATING
PLANE
b:4c::::J.~
-
)'"=====:=J=*'="
115 (2 92)
___..J_____~::::~_ __._iL .085 (2 16)
.055 (140)
045 (1 14)
030 (0 76)
013 (0 33)
t
-....--~
1_
t .....J
. -I
SECTION
.040 (102)
.025 (0 64)
x-x
GH
Notes
Pins are solder dipped over nickel plated
copper alloy
Pin 2 IS electncal contact with the
mounling tab
Mounting tab IS nickel plated copper alloy
Package matenal IS plastic
Package weight IS 2.0 grams
All dimenSions In Inches bold and millimeters (parentheses)
11-16
Package Outlines
4-Pin Metal Package
Similar to JEDEC TO-3
r-
~:::g~~~)~
.835 (2121)
.805 (20 45)
OIA
.325 (8 26)
.275 (6 98)
-.I:
.125 (318)
105 (2 67)
::::=I4:I==::;;=:;;:=='~'
C'
TSEATING PLANE
GK
Notes
Base IS nickel plated alummum
Can IS alummum
Pms are gold plated over nickel plated
alloy 52
All pms electrically isolated from case
with glass
Package weight IS 7 4 grams
• Similar to JEDEC TO·3 except for number
of pms
II .043 (1 09) OIA
---i I-- .038 (0 97)
1--___-1-_.675 (17
14)
.655 (16 64)
PIN 2
2 HOLES
.161 (409)
.151 (384)
.180 (4 57) R
.150 (381)
'---.--',,---- 525 (13 34) R
.480 (12 19)
2-Pin Metal Package
Similar to JEDEC TO-3
1_.
56)_1
.'"r~ rr+-r.L..------',-+,,~:{
.293 (7 44)
)
t
770 (19
MAX OIA
SEATING PLANE
70)
f
.400 (10 16) MIN
~
GN
Notes
Pms 1 and 2 electrically Isolated from case
Case IS third electrical connections
PIN 2
161 (409) OIA
.151 (384)
2 PLACES
.188 (4 78) MAX
2 PLACES
All dimensions m mches bold and millimeters (parentheses)
11·17
Package Outlines
2-Pin Metal Package
In Accordance with JEDEC TO-3
.295 (7 49)
.265 (6 73)
_
~
SEATlN~
r·
780 (19.81)1
.7600(IAI930)
.057(1.45)
.037 (094)
PL....
A-NE----O"'-+..,.....,=*
HJ
.450 (1143)
.400 (10 16)
Notes
Base IS nickel plated steel
Can IS nickel plated steel
Pins are solder dipped over nickel plated
alloy 52
Pins 1 and 2 electrically isolated from case
with glass
Case is third electrical connection
Package weight IS 9 2 grams
t
.161 (409) OIA
.151 (384)
2 HOLES
.180 (4.57) R
.150 (3.81)
2 PLACES
.525 (13 34) R
.480 (12 19)
4-Pin Metal Package
Similar to JEDEC TO-3
~_I
.770 (19 56)
MAX
r
.293 (7 44)
.273 (693)
.421 (10 69)!
MIN
_
~;~~g~~g;-
Ii
Ii
~ ~
f..1
I
:
_III--
I
+
SEATING
ii ITa6:~;;0~
MAX
.041 (1 04) OIA
.037 ( 940)
JA
_ _ 1.197 (30 4 0 ) _
1 177 (29 90)
PIN 1
Notes
PinS are solder dipped alloy 52
All pinS electrically Isolated from case
1_---""·675(1714)
.655 (16 64)
PIN 2
2 HOLES
161 (409)
.151 (384)
177(45)R
2 PLACES
.470 (1194)
PIN 3
DIA PIN
CIRCLE
525(1334)
MAX
All dimenSions In Inches boid ana millimeterS (parenthesesi
11-18
I=AIRCHIL.D
A Schlumberger Company
I
Fairchild Sales Offices
12-2
A Schlumberger Company
Sales
Offices
United States and
Canada
Alabama
Huntsville Office
500 Wynn Drive, SUite 511
Huntsville, Alabama 35805
Tel 205-837-8960
Indiana
Ft Wayne Office
2118 Inwood Drive, SUite 111
Ft Wayne, Indiana 46815
Tel 219-483-6453 TWX 810-332-1507
North Carolina
Raleigh Office
1100 Navaho Drive. SUite 112
Raleigh, North Carolina 27609
Tel 919-876-9643
Arizona
Phoenix Office
2255 West Northern Road, SUite Bl12
Phoenix, Arizona 85021
Tel 602-864-1000 TWX 910-951-1544
Indianapolis OffIce
7202 N Shadeland, Room 205
Castle POint
Indianapolis, Indiana 46250
Tel 317-849-5412 TWX 810-260- t 793
Ohio
Dayton Office
5045 North Main Street, SUite 105
Dayton, OhiO 45414
Tel 513-278-8278 TWX 810-459-1803
Kansas
Kansas City Office
8600 West 110th Street, SUite 209
Overland Park, Kansas 66210
Tel 913-649-3974
Oklahoma
Tulsa Office
9810 East 42nd Street, SUite 127
Tulsa, Oklahoma 74145
Tel 918-627-1591
Maryland
Columbia Office
1000 Century Plaza, SUite 225
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Tel 301-730-1510 TWX 710-826-9654
Oregon
Portland Office
8285 S W Nimbus Avenue. SUite 138
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Tel 503-641-7871 TWX 910-467-7842
Massachusetts
Framingham Office
5 Speen Street
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Tel 617-872-4900 TWX 710-380-0599
Pennsylvania
Philadelphia Office'
2500 Office Center
2500 Maryland Road
Willow Grove, Pennsylvania 19090
Tel 215-657-2711
FAIRCHILD
California
Los Angeles Office'
Crocker Bank Bldg
15760 Ventura Blvd, SUite 1027
Encino, California 91436
Tel 213-990-9800 TWX 910-495-1776
San Diego Office'
7867 Convoy Court, SUite 312
San Diego, California 92111
Tel 714-279-7961 TWX 910-335-1512
Santa Ana Office'
1570 Brookhollow Drive, SUite 206
Santa Ana, California 92705
Tel 714-557-7350 TWX 910-595-1109
Santa Clara Office'
3333 Bowers Avenue, SUite 299
Santa Clara, California 95051
Tel 408-987-9530 TWX 910-338-0241
Colorado
Denver Office
7200 East Hampden Avenue, SUite 206
Denver, Colorado 80224
Tel 303-758-7924
Connecticut
Danbury Office
57 North Street, #206
Danbury, Connecticut 06810
Tel 203-744-4010
Florida
Ft Lauderdale Office
Michigan
Detroit Offlce*
21999 Farmington Road
Farmington Hills, Michigan 48024
Tel 313-478-7400 TWX 810-242-2973
Minnesota
Minneapolis Office'
4570 West 77th Street, Room 356
Minneapolis, Minnesota 55435
Tel 612-835-3322 TWX 910-576-2944
New Jersey
New Jersey Office
Vreeland Plaza
41 Vreeland Avenue
Totowa, New Jersey 07511
Tel 201-256-9006
Tennessee
Knoxville Office
Executive Square II
9051 Executive Park Drive. SUite 502
Knoxville. Tennessee 37923
Tel 615,691-4011
Texas
Austin Office
9027 North Gate Blvd, SUite 124
Austin. Texas 78758
Tel 512-837-8931
Dallas Office
1702 North Collins Street, SUite 101
Richardson. Texas 75081
Tel 214-234-3391 TWX 910-867-4757
Executive Plaza, SUIte 112
1001 Northwest 62nd Street
Ft Lauderdale, Florida 33309
Tel 305-771-0320 TWX 510-955-4098
Orlando OfficeCrane's Roost Office Park
399 Whooping Loop
Altamonte Springs, Flonda 32701
Tel 305-834-7000 TWX 810-850-0152
Georgia
Atlanta Sales Office
Interchange Park, Bldg
4183 N E Expressway
Atlanta, Georgia 30340
Tel 404-939-7683
illinois
Itasca Office
500 Park Blvd, SUite 575
Itasca, IllinOIS 60143
Tel 312-773-3300
New Mexico
Albuquerque Office
North Budding
2900 LouIsiana N E South G2
Albuquerque, New MexICO 87110
Tel 505-884-5601 TWX 910-379-6435
New York
Fairport Office
815 Ayrault Road
Fairport, New York 14450
Tel 716-223-7700
MelVille Office
275 Broadhollow Road, SUite 219
MelVille, New York 11747
Tel 516-293-2900 TWX 510-224-6480
Poughkeepsie Office
19 DavIs Avenue
Poughkeepsie, New York 12603
Tel 914-473-5730 TWX 510-248-0030
'Field Application Engineer
12-3
Houston Office
9896 Blssonnet-2 .. SUite 470
Houston, Texas 77036
Tel 713-771-3547 TWX 910-881-8278
Canada
Toronto Regional Office
2375 Steeles Avenue West, SUite 203
Downsvlew, Ontario M3J 3A8. Canada
Tel 416-665-5903 TWX 610-491-1283
I=AIRCHILC
A Schlumberger Company
Australia
Fairchild Australia Pty Ltd
Branch Office Third Floor
F A I Insurance BUilding
619 Pacific Highway
St Leonards 2065
New South Wales, Australia
Tel ,02,-439-5911
Telex AA20053
Austria and Eastern Europe
Fairchild Electronics
A-1010 W,en
Schwedenplatz 2
Tel 0222 635821 Telex 75096
Benelux
Fairchild Semiconductor
Ruysdaelbaan 35
5613 Dx Eindhoven
The Netherlands
Tel 00-31-40-446909 Telex 00-1451024
Brazil
Fairchild Sernlconductores Uda
Calxa Postal 30407
Rua Alagoas, 663
01242 Sao Paulo, Brazil
Tel 66-9092 Telex 011-23831
Cable FAIRLEC
France
Fairchild Camera & Instrument S A
121, Avenue d'italle
75013 Pans, France
Tel 331-584-55 66
Telex 0042 200614 or 260937
Germany
Fairchild Camera and Instrument GmBH
Dalmlerstrasse 15
International
Sales
Offices
Hong Kong
Fairchild Semiconductor I HK Ltd
135 HOI Bun Road
Kwun Tong
Kowloon, Hong Kong
Tel 3-440233 and 3-890271
Telex HKG-531
I
Italy
Fairchild Semlconductton, SPA
Via Flamem8 Veechla 653
00191 Roma, Italy
Tel 06 327 4006 Telex 63046 I FAI R ROM,
Fairchild Semlconducttorl SPA
Vlale Corsica 7
20133 Milano, Italy
Tel 296001-5 Telex 843-330522
Japan
Fairchild Japan Corporation
Pol a Bldg
1-15-21, Shlbuva
Shlbuya-Ku, Tokyo 150, Japan
Tel 034008351 Telex 242173
Fairchild Japan Corporation
Yotsubashl Chua Bldg
1-4-26, Shlnmachl
NIShl-Ku, Osaka 550, Japan
Tel 06-541-6138/9
Korea
Fairchild Semlkor Ltd
K2 219-6 Gar! Bong Dong
Young Dung Po-Ku
Seoul 150-06, Korea
Tel 85-0067 Telex FAIRKOR 22705
I
mailing address',
Munich, Germany
Fairchild Camera and Instrument GmBH
Oeltzenstrasse 15
3000 Hannover
W Germany
Tel 0511 17844 Telex 0922922
Singapore
Fairchild Semiconductor Pty Ltd
No 11, Lorong 3
Toa Payoh
Singapore 12
Tel 531-066 Telex FAIRSIN-RS 21376
Taiwan
Fairchild Semiconductor Ltd
HSletsu Bldg, Room 502
47 Chung Shan North Road
Sec 3 Taipei, Taiwan
Tel 573205 thru 573207
United Kingdom
Fairchild Camera and Instrument Ltd
Semiconductor DIvISion
230 High Street
Potters Bar
Hertfordshlre EN6 5BU
England
Tel 070751111 Telex 262835
Fairchild Semiconductor Ltd
17 Victoria Street
Cralgshlll
LIvingston
West Lothian, Scotland - EH54 5BG
Tel LIvingston 050632891 Telex 72629
GEC-Falrchlld Ltd
Chester High Road
Neston
Central POBox 2806
8046 Garchlng Hochbruck
Tel ,089,320031 Telex 524831 fair d
Scandinavia
Fairchild Semiconductor AB
Svartengsgatan 6
S-11620 Stockholm
Sweden
Tel 8-449255 Telex 17759
Mexico
Fairchild Mexlcana SA
Blvd Adolofo Lopez Mateos No 163
MexIco 19, D F
Tel 905-563-5411 Telex 017-71-038
Fairchild Camera and Instrument GmBH
Poststrasse 37
7251 Leonberg
W Germany
Tel 0715241026 Telex 07245711
12-4
South Wlrral L643UE
Cheshire, England
Tel 051-336-3975 Telex 629701
Source Exif Data:
File Type : PDF File Type Extension : pdf MIME Type : application/pdf PDF Version : 1.3 Linearized : No XMP Toolkit : Adobe XMP Core 4.2.1-c043 52.372728, 2009/01/18-15:56:37 Create Date : 2013:08:20 17:56:21-08:00 Modify Date : 2013:08:20 22:18:16-07:00 Metadata Date : 2013:08:20 22:18:16-07:00 Producer : Adobe Acrobat 9.55 Paper Capture Plug-in Format : application/pdf Document ID : uuid:37d9b422-c19a-ea46-a07b-03030295470e Instance ID : uuid:8ecb0448-1d90-e04c-9b71-0fb176539e8e Page Layout : SinglePage Page Mode : UseNone Page Count : 716EXIF Metadata provided by EXIF.tools