1982_Fairchild_Microprocessor_Products_Data_Book 1982 Fairchild Microprocessor Products Data Book
User Manual: 1982_Fairchild_Microprocessor_Products_Data_Book
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© 1982 Fairchild
3420 Central Expressway
Santa Clara CA 95051
I=AIRCHILD
A 5chlumberger Company
The Advance Product Information designation on a
Fairchild publication indicates that the product described is
not characterized. The specifications presented are based
on design goals or preliminary part evaluation and, as they
are subject to change, are not guaranteed. Fairchild
Microprocessor Division should be contacted for current
information on these products.
The information furnished in this publication is believed to
be accurate and reliable. However, Fairchild cannot assume
responsibility for its use, or for use of any circuitry described, other than circuitry entirely embodied in a Fairchild product. No license is granted or implied under any Fairchild
patents, patents, or trademarks.
Fairchild reserves the right to make changes in the circuitry
or specifications presented in this publication at any time
and without notice.
iii
iv
Table of Contents
Section 1 Introduction
General. ..................................................................................... 1-3
Product Line ................................................................................. 1-3
Data Book ................................................................................... 1-3
Section 2 Ordering and Package Information
General. .................................................................................. , .. 2-3
Temperature Range ............................................................... : .......... 2-3
Package Types and Outlines .................................................................. 2-3
Section 3 F8 Microcomputer Family
General. ..................................................................................... 3-3
Memory Interface Devices .................................................................... 3-3
Input/Output Devices ......................................................................... 3-3
Bus Structure ................................................................................ 3-3
Instruction Set. .............................................................................. 3-3
F3850 Central Processing Unit. ............................................................... 3-7
F3851/F3856 Program Storage Unit .......................................................... 3-31
F3852 Dynamic Memory Interface/F3853 Static Memory Interface .............................. 3-55
F3854 Direct Memory Access Controller...................................................... 3-77
F38T56 Program Storage Unit. ..................•............................................ 3-87
F3861 Peripheral Input/Output. .............................................................. 3-97
F3871 Peripheral Input/Output. ............................................................. 3-109
Section 4 Controller Family
F387X Family ................................................................................ 4-3
F3870X Family ............................................................................... 4-3
Part Numbers ................................................................................ 4-4
Descriptions ................................................................................. 4-4
F3870 Single-Chip Microcomputer. ........................................................... 4-5
F3870A/F3870B High-Speed Single-Chip Microcomputer...................................... 4-27
F38C70 Single-Chip Microcomputer.......................................................... 4-29
F38E70 Single-Chip Microcomputer.......................................................... 4-47
F3872/F38L72 Single-Chip Microcomputer. ................................................... 4-67
F38700 Central Processing Unit. ............................................................. 4-91
F38701 Single-Chip Microcomputer.......................................................... 4-95
F38752 Analog Interface Unit. ............................................................... 4-99
F38753 Power Control Unit. ................................................................ 4-103
F38754 Peripheral Input/Output. ............................................................ 4-105
v
Table of Contents
Section 5
F6800 Microprocessor Family
General. ...................................................................................... 5-3
Instruction Set. ............................................................................... 5-3
.F6800/F68BOO B-Bit Microprocessing Unit. ...................................................... 5-11
F6801/F6803 Single-Chip Microcomputer....................................................... 5-51
F6802/F68821F6808MicroprocessorWith Clock and RAM ......................................... 5-57
F6809 Central Processing Unit. ................................................................ 5-81
F6810/F68A10/F68B10 128 x B-Bit Static RAM .................................................. 5-83
F6820 Peripheral Interface Adaptor............................................................. 5-89
F68211F68A211F68B21 Peripheral Interface Adaptor............................................. 5-103
F6840/F68A40/F68B40 Programmable Timer................................................... 5-115
F6844 Direct Memory Access Controller....................................................... 5-131
F6845/F6845A CRT Controller................................................................. 5-151
F6846 ROM-1I0-Timer........................................................................ 5-175
F6847 Video Display Generator............................................................... 5-195
F6850/F68A50/F68B50 Asynchronous Communications Interface Adaptor........................ 5-207
F68521F68A521F68B52 Synchronous Serial Data Adaptor........................................ 5-219
F6854/F68A54/F68B54 Advanced Data Link Controller........................................... 5-239
F3846/F6856 Synchronous Protocol Communications Controller................................. 5-263
F38456/F68456 Multiple Protocol Communications Controller.................................... 5-293.
F68488 General Purpose Interface Adaptor.............................................. , ...... 5-297
Section 6
16·Blt 13L Bipolar Microprocessor Family
General. ....................................................................................... 6-3
Instruction Set. ............................................................................... 6-3
F9443 Floating Point Processor....................................................... , ........ 6-13
F9444 Memory Management and Protection Unit. ............................................... 6-15
F9445 16-Bit Bipolar Microprocessor........................................................... 6-17
F9446 Dynamic Memory Controller............................................................. 6-45
F9447 110 Bus Controller...................................................................... 6-47
F9448 Programmable Multiport Interface........................................................ 6-55
F9449 Multiple Data Channel Controller.......................... ;., .. -' ......... , ...... ; ........ 6-61
F9450 Single-Chip Microprocessor............................................................. 6-75
F9451 Memory Management Unit. ............................................................. 6-77
F9452 Block Protect RAM ..................................................................... 6-79
F9470 Console Controller..................................................................... 6-81
vi
Table of Contents
Section 7 F16000 Microprocessor Family
General. ...................................................................................... 7-3
Addressing ................. _................................................................. 7-3
Virtual Memory.......................................................................... '" ... 7-3
Symmetry ..................................................................................... 7-3
High-Level Language Support ................................................................... 7-4
Modularity .................................................................................... 7-4
Slave Processors .............................................................................. 7-4
System Protection ............................................................................. 7-4
Future Expansion .............................................................................. 7-4
F16032 High Performance Central Processing Unit. ............................................... 7-7
F16081 Floating Point Unit. ................................................................... 7-13
F16082 Memory Management Unit. ............................................................ 7-15
F16105 Very Intelligent Peripheral Controller.................................................... 7-17
F16201 Timing Control Unit. ................................................................... 7-19
F16202 Interrupt Control Unit. ................................................................. 7-21
F16203 Channel Controller.................................................................... 7-23
F16204 Bus Arbiter........................................................................... 7-25
F16413 CRT Controller........................................................................ 7-27
F16425 Packet Switching Frame Level Controller................................................ 7-31
F16456 Multiple Protocol Communications Controller............................................ 7-35
F16457 Data Encryption Circuit. ............................................................... 7-39
F16488 GPIB Controller....................................................................... 7-41
Section 8
F3532/F68332/F3533 32K ROM .................................................................. 8-5
F3564 64K ROM .............................................................................. 8-11
F3565 64K ROM .............................................................................. 8-13
F3566 64K ROM .............................................................................. 8-15
F3568 64K ROM .............................................................................. 8-17
F3569 64K ROM .............................................................................. 8-19
F3570 64K ROM .............................................................................. 8-21
F35316/F68316 16K ROM ...................................................................... 8-23
Section 9 Development Systems and Software
EMUTRAC .................................................................................... 9-5
Formulator.................................................................................... 9-9
FS-1 ......................................................................................... 9-11
PEP-45 ...................................................................................... 9-15
PEP-68 ...................................................................................... 9-17
PEP-387X .................................................................................... 9-25
Software ..................................................................................... 9-27
vii
Table of Contents
Section 10 Applications
Matrix Printer................................................................................ 10·5
PLL System ................................................................................. 10·19
Solar Controller............................................................................. 10·31
Section 11
Resource and Training Centers
Section 12
Sales Offices
viii
INTRODUCTION
1tlI2 IORDERING AND PACKAGE
~ INFORMATION
1C!JIF8 MICROCOMPUTER FAMILY
1 0 1 CONTROLLER FAMILY
~ IF6800 MICROPROCESSOR FAMILY
1
101F16000 MICROPROCESSOR FAMILY
~ IROM PRODUCTS
1
InIg I DEVELOPMENT SYSTEMS AND
L!J SOFTWARE
[!QJ
1
I APPLICATIONS
IITDIRESOURCE AND TRAINING CENTERSI
I~ISALES OFFICES
Section 1
Introduction
General
capabilities by interconnection with external devices.
A microprocessor is essentially an integrated circuit logic
replacement device that performs the functions of the central processing unit (CPU) of a computer system. The
overall task of the microprocessor is to receive digital data
and store it for later processing, to perform arithmetic and
logic operations on the data in accordance with instructions contained in a stored program, and to present the
results of these operations to the user through some form
of output mechanism.
The Fairchild Microprocessor Division product line encompasses microprocessors and their support devices, singleand multi-chip microcomputers, and systems to emulate
and develop hardware and software.
Product Line
The Microprocessor Division product line includes a wide
range of devices to meet the specific needs of four broad
application areas:
The program is a definable and non-varying specification for
any given application. It normally resides in a read only
memory (ROM) or program storage unit (PSU). Variable data
that is to be operated upon by the microprocessor is normally stored in a random access memory (RAM) or other
transient data storage element.
Although architectural details vary depending upon
manufacturer and technology, a typical microprocessor
comprises the following functional areas:
1.
Instruction decoding to interpret program
instructions.
2.
An arithmetic and logic unit (ALU) to perform binary
addition, subtraction, etc., and Boolean logic
operations.
3.
Registers to temporarily store frequently manipulated
data.
4.
Address buffers to provide the next program
instruction address.
5.
Input/output (1/0) buffers to read information into
or write information out of the microprocessor.
1.
a-bit microprocessors
2.
a-bit single-chip microcomputers
3.
16-bit microprocessors
4.
Development aids
Within these areas, the Division offers a blend of innovative, state-of-the-art devices and proven, wellestablished devices. For example, the members of the
F6800 family, and of the F8 family, can be configured to
create a variety of 8-bit computer systems that have a wide
range of capabilities. Similarly, the F9445 family components can create extremely fast 16-bit computer systems
that are exceptionally resistant to harsh environments, and
the F16000 family members can be used in configurations
that are ideally suited to communications applications. (The
F16000 has a 16-bit 1/0 structure and a 32-bit
internal architecture.)
To the user, the Microprocessor Division line represents a
single source of cost-effective solutions to the full
spectrum of application problems.
Data Book
Microprocessors are generally used in conjunction with
support devices that perform timing, program and transient
data memory, 110 signal interface, and other functions. A
wide range of configurations is possible with a
microprocessor and its related devices; each configuration
represents a full microcomputer system.
This data book presents a complete technical description
of the Fairchild Microprocessor Division product line.
Where devices have been characterized, specific information is presented in the form of data sheets. Information on
partially characterized devices, and on devices currently
under development, is in the form of advance product information sheets. More complete data can be obtained from
the Product Marketing Department.
A single-chip microcomputer incorporates CPU, memory,
1/0, control, and other functions into one integrated circuit.
Typically, such devices have facilities for enhancement of
1-3
II
Introduction
1-4
I
[!J
IINTRODUCTION
ICTIIF8 MICROCOMPUTER FAMILY
101CONTROLLER FAMILY
1~IF6800 MICROPROCESSOR FAMILY
101F16000 MICROPROCESSOR FAMILY
I
w
I ROM PRODUCTS
Inlg I DEVELOPMENT SYSTEMS AND
L!J SOFTWARE
I
~ I APPLICATIONS
I[I!JIRESOURCE AND TRAINING CENTERSI
I
~ I SALES OFFICES
Section 2
Ordering and Packaging Information
General
Package Types and Outlines
Specific ordering codes, as well as the temperature ranges
and package types available, are included in each data
sheet of sections 3 through 8.
The basic package type of a device, such as dual·in·line
plastic or dual·in-line ceramic, is indicated by the ordering
code for that device. To accommodate various die sizes and
pin numbers, different package forms exist within each
package type.
Temperature Range
The package forms indicated by device ordering codes are
illustrated in the following detailed outline drawings.
The basic temperature ranges typically available are:
C
L
M
Commercial (O°C to 75°C)
Automotive (- 40°C to 85°C)
Military (- 55°C to 125°C)
24·Pin Ceramic Dual·ln·Line
T-
t=
1.290 (32.7661_------'
-I
1.235(31.369)
I
12
I
.030 (0.762) R
.570 (14.478)
.020 (05081
.515 (13.081)
L~~~~~
_~
1_," .100 (2 540)
.040 (1 ,Q16l
.190 (4.826)
.140 (3.556)
,063 (1.544)
I ~.'.{D'6131
L
'
'--.L SEATING
+=, , f'II
.200 (5,0801-1
.100 (2540)
I
,r--
.110 (2.794)
.090 (2.286)
,
I
PLANE
I .037 {D,9401 IL·020 (05081
1-.027 (0.686)-11- .016 (O.40B)
STANDOFF
WIDTH
(190~1_ i
I .750
r---MAX
TYP
NOTES:
All dimensions are in inches bold and millimeters (parentheses).
Pin material is nickel gold-plated kovar.
Cap is kovar.
Base is ceramic.
Package weight is 6.5 grams.
2-3
-j
II
Ordering and Packaging
Information
24-Pin Plastic DIP
1.260 (320041
---'.240 (314961
f
.050 R (1271
.035 (8891
I
.560 (142241
.540 (13.716)
.090 (22861
.065 (16511
II
Jmmmm ;~~~~NG
.160(4.06)
.045 NOM
(1.14)
---
.145 (136831
-
.020 (5081
~MIN
.130(3301
.115(2.9211
I, (2i~9041 ·1
~:
.037(9401
-j 1-.027(.6861
-'1 ~ .090
(22861
.020 (5081
I
+i~-.016(4061
I-
STANDOFF
WIDTH
NOTES:
All dimensions are in inches bold and millimeters (parentheses).
Pins are tin·plated kovar.
Package material is plastic.
28·Pin Ceramic Dual·ln·Line
r - - - - - - 1 . 4 7 0 (37.34)~
I
1\ 1\1\ I
1.450 (36.a3) 1\ 1\ 1\ 1\ 1\ I
-r-14
1
.030 (0.76)
.020 (0.51) RADIUS
.570 (14.48)
'5~~n-~~~~~~rTrTrn-n,T~
.190 (4.83)
.~~~~;;~~:;~~~;;~~
\(-~~~'"
.037 (0.94) ____
.027 , WRITE)
4.
Three interrupt lines (PRI IN, PRI OUT, INT REO)
Instruction Set
The instruction set of a microprocessor or microcomputer
is the software tool used to shape the device or system for
a particular application. The F8 instruction set is divided
into four functional groups:
Memory Interface Devices
When required by the application, the F3851 PSU may be
replaced by an F3852 Dynamic Memory Interface (DMI) or
F3853 Static Memory Interface (SMI). Both of these devices
interpret control Signals output by the F3850 and generate
the standard address and control Signals required by
off·the-shelf dynamic and static memory devices.
1.
Input/Output
2.
Arithmetic/Logical
3.
Address Register Control
4.
Indirect Scratchpad Address Register (ISAR) and
Status Control
The F3854 Direct Memory Interface (OMA) device is used in
The F8 instruction set is presented in table 3·1.
3·3
II
Fa Microcomputer
Family
Table 3-1 F8 Instruction Set
Instruction Description
ADC
AI
AM
AMD
AS
ASD
Instruction Description
Add Accumulator to Data Counter
Add Immediate to Accumulator
Add (Binary) Memory to Accumulator
Add (Decimal) Memory to Accumulator
Add (Binary) Scratchpad Memory
to Accumulator
Add (Decimal) Scratchpad Memory
to Accumulator
JMP
Branch Immediate
LI
LIS
LlSL
LlSU
LM
LNK
LR
Load Immediate
Load Immediate Short
Load Lower Octal Digit of ISAR
Load Upper Octal Digit of ISAR
Load Accumulator'trom Memory
Link Carry to Accumulator
Load Register
BC
BF
BM
BNC
BNO
BNZ
BP
BR
BR7
BT
BZ
Branch on Carry
Branch on false
Branch on Negative
Branch if No Carry
Branch if No Overflow
Branch if Not Zero
Branch if Positive
Unconditional Sninch
Branch on ISAR
Branch on True
Branch on Zero
NI
NM
NOP
NS
AND Immediate
Logical AND from Memory
No Operation
Logical AND from Scratchpad Memory
01
OM
OUT
OUTS
OR Immediate
Logical OR from Memory
Output Long Address
Output Short Address
CI
CLR
Compare Immediate
Clear Accumulator
PI
PK
COM
Complement
POP
Call to Subroutine Immediate
Call to Subroutine Direct and Return from
Subroutine Direct
Return from Subroutine
DCI
01
OS
Load Data Counter Immediate
Disable Interrupt
Dessement Scratch pad Memory Content
SL
SR
ST
Shift Left
Shift Right
Store to Memory
EI
Enable Interrupt
IN
INC
INS
Input Long Address
Increment Accumulator
Input Short Address
XDC
XI
XM
XS
Exchange Data Counters
Ekxclusive-OR Immediate
Exclusive-OR from Memory
Exclusive-OR from Scratch pad Memory
3-4
Fa Microcomputer
Family
Descriptions
Following is data that describes the members of the F8
microcomputer system family.
F8 FAMILY ORGANIZATION
II
F3850
CENTRAL PROCESSING
UNIT
F3851
PROGRAM
STORAGE UNIT
F3852
DYNAMIC MEMORY
INTERFACE
F3853
STATIC MEMORY
INTERFACE
F3854
DIRECT MEMORY
ACCESS CONTROLLER
F3856
PROGRAM
STORAGE UNIT
F38T56
PROGRAM
STORAGE UNIT
F3861
PERIPHERAL
INPUT/OUTPUT
F3871
PERIPHERAL
INPUT/OUTPUT
3-5
Fa Microcomputer
Family
3-6
F3850
Central Processing Unit (CPU)
Microprocessor Product
Description
The Fairchild F3850 is the Central Processing Unit (CPU) for
the F8 8-Bit Microprocessor family. The F3850 contains more
than 70 instructions in its instruction set and operates on 8-bit
units of information.
•
•
•
•
• 8-Blt Arithmetic and Logic Unit, Supporting Both Binary and
Decimal Arithmetic
• Interrupt Control LogiC
• Power-on Reset Logic
• Clock Generation Logic Within the CPU Chip, With Crystal
and External Clock Generation
• More Than 70 Instructions
• +5 V and +12 V Power Supplies
• Low Power Dissipation (Typically Less Than 330 mW)
N-channellsoplanar MOS Technology
2 p's Cycle Time
64-Byte Scratchpad on the CPU Chip
lINo Bidirectional, 8-Bit 1/0 Ports, with Output Latches
Connection Diagram
Signal Functions
CLOCK
LINES
110
PORT
LINES
-------------
¢
WRITE
XTLX
--
ICB
ROMeo
XTLY
ROMe l
XTLZ
ROMe 2
XTLZ
- - } INTERRUPT
--+LINES
--
WRITE
XTLZ
Voo
XTLY
EXT RES
CONTROL
LINES
ROMe 3
1/000
1/0 01
EXT RES
1/002
1/003
DB,
1/004
DB,
1/0 05
DB,
liDos
1/007
1/010
1/0 11
------
INTREQ
1/0 12
DB,
DB,
DBs
DB,
DB,
1/013
1/0 14
1/°15
1/0 16
Vss
Voo
Voo
----------------
RESET
DB,
1/0 16
DATA
BUS
LINES
ilo 17
DB,
DB,
1/0 00
1/007
Vss
ROMeo
-- )~.
(Top View)
1/0 17
3-7
II
F3850
The contents of the instruction register are decoded by control
unit logic, which generates signals to enable specific sequences
of logic operations within the CPU chip. In response to the contents of the instruction register, the control unit also generates
five signals, ROMCothrough ROMC4 , that control operations
throughout the microprocessor system.
Device Organization
The logical organization and pins for the F3850 CPU are
illustrated in Figure 1.
Arithmetic and Logic Unit
The arithmetic and logic unit (ALU) provides all data manipulating
logic for the F3850. It contains logic that operates on a single 8-bit
source data word or combines two 8-bit words of source data to
generate a single 8-bit result. Additional information is reported in
status flags, where appropriate.
Accumulator
The accumulator is a general-purpose 8-bit data register.
which is the most common data source and results destination
fortheALU.
Operations performed on two units of source data include addition,
compare, and the Boolean operations (AND, OR, Exclusive-OR).
The two sources are input to the ALU through the left and right
multiplexer buses; the result is placed on the result bus.
Scratchpad and ISAR
The scratchpad provides 64 8-bit registers that may be used
as general-purpose RAM memory (see Figure 2).
Operations performed on a single 8-bit unit of source data include
complement, increment, decrement, shift right, shift left, and clear.
The source is input to the ALU through either the left or right multiplexer bus; the result is placed on the result bus.
Figure 2 F8 Programming Model
- . . . - BIT NO.
Instruction Register
The CPU contains registers for storing various types of data.
The instruction register holds an 8-bit code, which defines the
operations to be performed by the CPU.
HI
NOT INCREMENTED
OR DECREMENTED
LO
L
•
~
INCREMENTED AND
DECREMENTED
Figure 1 F38S0 CPU Logical Organization
RESULTS BUS
l
,.....
_I
ACCUMULATOR
I- r--I-§
~
-
-- . --
ALU
I-
-'
:>
-I
L
111
I
;r
>=
-'
:>
:I!
I
Voo VGG Vss
a:
w
><
w
.....
r'"
l-
J:
INSTRUCTION
l
1
INTERNAL OAT A BUS
1
1/0 PORTA
I
I
t
IIOPORTB
1I
I--- "a:
L-
t-
DATA BUFFER
--
1I0os
-
DB.
-I
1--....
ISAR
CONTROL
UNIT
LOGIC
INTERRUPT
LOGIC
POWER
ON
DETECT
CLOCK
CIRCUITS
I
t t -t t t t
11007
I-
:>
:I!
STATUS(W)
64 x8~BIT
SCRATCHPAD
REGISTERS
U>
~
ROMeo
DB,
3·8
~
ROMC4
1
INT
REO
~ ~
I CB
EXT RES
xL! lv 1JTE
XTLX
F3850
The indirect scratchpad address register (ISAR) is a 6-bit register
used to address the 64 scratchpad registers.
i.e .• the ISAR is assumed to hold the address of the scratch pad
byte that is to be referenced.
The first 16 scratch pad bytes can be identified either by instructions without using the ISAR or referenced through the ISAR.
The remaining scratchpad bytes are referenced through the ISAR;
The ISAR may be visualized as holding two octal digits. HI and LO.
as illustrated in Figure 3. This division of the ISAR is important.
since a number of instructions increment or decrement the con-
Figure 3
II
tSAR Register
ACCUMULATOR
0
LR r, A
r---~~----~~
CPU
GENERAL
REGISTERS
ISAR
11~2
REGISTER
ADDRESS
POINTER
LRJ,W
J
LRW,J
A
H
10
B
H
11
C
K
12
D
K
13
0
14
0
15
ZERO - - - - - - '
POP
CARRY - - - - - SIGN - - - - - - -
15
LRP,K
15
10
16
3F
63
DATA COUNTER
LRDC,H
LRH,DC
LRDC.O
LR O. DC
MEMORY
ADDRESS
POINTER
3-9
LRK,P
STACK POINTER
F3850
and program memory address registers that are maintained on
the F3851, F3852, and F3853 Chips. Figure 4 identifies the data
transfers that can be implemented by executing a single F8
instruction. For example, the illustration:
tents of the ISAR, when referencing scratchpad bytes through the
ISAR. This makes it easy to reference a buffer consisting of contiguous scratchpad bytes. However, only the low-order octal digit
(LO) Is incremented or decremented; thus ISAR is incremented
from 0'27'* to 0'20', not to 0'30'. Similarly, ISAR is decremented
from 0'20' to 0'27', not to 0'17'. This feature of the ISAR is very
useful in that it greatly simplifies many program sequences.
W register of F3850 CPU - J
means that a single instruction can move the contents of the W
(or status) register to scratch pad register 9 (J register). Another
single instruction can move data in the opposite direction.
Selected scratchpad registers are reserved for direct communication with other registers within the F8 system, as illustrated in
Figure 4.
Status Registers
The status (W) register holds five status flags. Table 1 summarizes
the way each flag is used. Note that status flags are selectively
modified following execution of different instructions. See the
"Instruction Execution" section for a discussion of the way
individual F8 instructions modify status flags.
Scratchpad register 9 (0'11 ') is used as temporary storage for
the CPU stetus register (W register). Scratchpad registers 10
through 15 (0'12' through 0'17') communicate directly with data
'The notation O'nn' represents an octal number.
Figure 4 F3850 CPU Scretchpad Registers
SCRATCHPAD
BYTE ADDRESS
SCRATCHPAD
DECIMAL OCTAL
§
W REGISTER OF F3850 CPU _ _
J
OC REGISTER OF F3851 PSU.( H ( HU
F3852 DMI AND F3853 SMI - ( HL
L~l
PCOORPC1(STACK)REGISTEROFF3851
PSU F3852 DMI AND F3853 SMI \
11
10
12
11
13
12
14
H
15
KU
t KL
DC OR PCO REGISTER OF F3851} (QU
PSU F3852 DMI AND F3853 SMI
QL
i
3-10
14
16
15
17
16
20
56
72
59
73
60
74
61
75
62
76
63
77
F3850
Overflow (0 Blt)-When the results of an ALU operation are
being interpreted as a signed binary number, since the high-order
bit (bit 7) represents the sign of the number, some method must
be provided for indicating a carry out of the highest numeric bit
(bit 6). This is done using the 0 bit. After arithmetic operations,
the 0 bit is set to the Exclusive-OR of a carry out of bits 6 and 7.
The simplification of signed binary arithmetic is described in the
F8 and F3870 Guide to Programming; examples are presented
below:
-+-- BIT NO.
I
C
B
o
Z
I I I
C
STATUS REGISTER (W)
LSIGN
~
L
CARRY
ZERO
7 654 3 2 1 0 -
OVERFLOW
Accumulator contents:
Value added:
Sum:
INTERRUPT MASTER
ENABLE
Bit Number
10110011
01110001
11100100
Sign (S Blt)-When the results of an ALU operation are being
interpreted as a signed binary number, the high-order bit (bit 7)
represents the sign of the number. At the conclusion of instructions that may modify the accumulator bit 7, the S bit is set to
the complement of the accumulator bit 7.
There is a carry out of bit 6 and a carry out of bit 7, so the 0 bit is
reset to 0 (1 $1 = 0). The C bit is set to 1.
Table 1 Summary of Status Bits
There is a carry out of bit 6, but no carry out of bit 7; the 0 bit is
set to 1 (1 $ a= 1). The C bit is reset to O.
Accumulator contents:
Value added:
Sum:
OVERFLOW = CARRY? + CARRY6
ZERO
= ALU? ALU6 ALU 5 ALU4 ALU3 ALU2 ALU 1
ALUo
CARRY
= CARRY?
SIGN
= ALU?
Accumulator contents:
Value added:
Sum:
a-
Control Unit
The control unit decodes the contents of the instruction register
and generates two sets of control signals. These Signals are
transparent to the user.
Five control signals (ROMCo through ROMC4) are output by
the control unit to identify operations that other chips of the Fa
family must perform. These signals are described in the "ROMC
Signals" section.
Bit Number
01100101
01110110
a 1 1 a 1 1 01 1
There is no carry, so C is reset to O.
C 7 65 43 21a
Accumulator contents:
1
111 1
Value added:
1101000 1
Sum: 1 110 1.110
aa
a
-
Bit Number
Interrupts (ICB Blt)-External logic can alter program execution
sequence within the CPU by interrupting ongoing operations.
However, interrupts are allowed only when the ICB is set to 1;
interrupts are disallowed when the ICB is reset to O.
Carry (C Blt)-The C bit may be visualized as an extension of an
a-bit data unit; i.e., the ninth of a 9-bit data unit. When two bytes
are added, and the sum is greater than 255, then the carry out of
the high-order bit appears in the C bit; e.g.:
C 765 43 21
76543210 01100111
00100100
1 a aa 1 a 1 1
Interrupt Logic
This logic handles the interrupt requests. For a complete
description refer to the "Interrupt" discussion within the
"Instruction Execution" section.
Bit Number
a
Power on Detect
When the External Reset (EXT RES) signal is pulled low and then
returned high, or when power is turned on, the power on detect
logic sets the PC registers to 0, causing a program originating at
memory location to be executed. Also, the interrupt control
status bit is set low, inhibiting interrupt acknowledgement. The
system is locked in an idle state while EXT RES is held low.
rhere is a carry, so C is set to 1.
Zero (Z blt)-The Z bit is set whenever an arithmetic or logical
operation generates a zero result. The Z bit is reset to when an
arithmetic or logical operation could have generated a zero result
but did not.
a
a
3-11
II
F3850
Signal Descriptions
The F3850 input and output signals are described in Table 2.
Table 2 F3850 Signal DeliCriptions
Mnemonic
Name
Pin No.
Description
Clock
output
drive the slave XTLY input.
Figure 5 Crystal Mode Clock Generation
Figure 6 External Mode Clock Generation
Vss
Vss
XTLZ
~
C,
XTLY
XTLY
T
F3850
CPU
XTLX
XTtX
1 c,
T
EXTERNAL
CLOCK
Vss
3-13
F3850
CPU
II
F3850
ROMe Signals·
The CPU logic uses the five ROMC signals to identify operations
that devices must perform during any instruction cycle. The 32
possible ROMC states are described in the "ROMC Signal
Functions" section. The state of the ROMC signals and the
operation they identify last through one instruction cycle.
Figure 7 illustrates the timing characteristics of the clock
signal needed for external mode clock generation and the
timing c~aracterlstlcs of the q, and WRITE signals generated
by the CPu.
Timing Signal Outputs
In response to the three clock mode inputs, the F3850 CPU
outputs two timing signals: clock signal", and instruction cycle
control signal WRITE. As shown in Figure 7, q, is the signal used
to synchronize the entire microprocessor system. The WRITE
signal defines the duration of each machine cycle. Refer to the
"Instruction Execution" section. Parameters and specifications for
the timing signals are detailed in the "Timing Characteristics"
section.
The general distribution of logic among devices of the F8 family
and general data movements associated with instruction execution
are given in the F8 and F3870 Guide to Programming.
Memory addressing logic is located on the F3851 Program
Storage Unit (PSU), the F3852 Dynamic Memory Interface
(DMI), and the F3853 Static Memory Interface (SMI) devices.
Each of these devices contains registers to address programs
(PCO and PC1) or data (DCO or DC1). The F3851 PSU does
not have a DC1 register.
Instruction Execution
The F3850 CPU logic oontrols instruction execution through
the q, and WRITE timing signals, plus the five ROMC control
lines. Devices external to the F3850 CPU must respond directly
to these signals.
Unlike other microprocessors, the F385D CPU does not output
addresses at the start of memory access sequences; a simple
command to access the memory location addressed by PCO or
DCO is sufficient, since the device receiving the memory access
command contains PCO and DCD registers. (The PC1 and DC1
are buffer registers for PCO and DCO.)
Instruction Cycle
All instructions are executed in cycles that are timed by the trailing
edge of WRITE.
Moving memory addressing logic from the CPU to memory
(and memory interface) devices simplifies CPU logic; however, it
creates the potential for devices to compete when responding to
memory access commands.
There are two types of instruction cycle: the short cycle, which is
four q, periods long, and the long cycle, which is sixq, periods long.
The long cycle Is sometimes referred to as 1.5 cycles. Figure 7
illustrates the short cycle (PoNs) and the long cycle (PWd. Note
that WRITE high appears only at the end of an instruction cycle.
There will be as many PCO and DCO registers in a microcomputer
system as there are PSU, DMI, and SMI devices; the ambiguity
of which unit will respond to a memory read or write command is
resolved by ensuring that all PCD and OCD registers contain the
same information at all times. Every PSU, OMI, and SMI device
The simplest instructions of the F8 instruction set execute in one
short cycle. The most complex instruction (PI)"requires two short
CYCles plus three long cycles.
Figure 7 . Clock Generation Timing Signals
~
WRITE
-r- ~-==t
---If
.I+F-
td
- '- - - - pw.
N~ _ _ _--iL __ - ~-----..JL --- ~""-.------0-1
~~.~I~.~-.. ----------__----__------PWL------~+-----------------~·I
3-14
F3850
As referenced in the "ROMC Signal Functions" section, each
ROMC state is identified by individual signal line states (1 for
high, 0 for low), and by a two-digit hexadecimal code. The
hexadecimal code is used to identify ROMC states throughout
this data sheet. Also given in the "ROMC Signal Functions" section
is the instruction cycle length (short or long) implied by each code,
plus the way in which codes must be interpreted by the other
F8devices.
has a unique address space, i.e., a unique block of memory
addresses within which it responds to memory access
commands.
For example, an F3851 PSU may have an address space of
H'OOOO' through H'03FF'; an F3852 DMI may have an address
space of H'0400' through H'07FF'. If a microcomputer system has
these two memory devices and no others, then the F3851 PSU
will respond to memory access commands when the PCO or DCO
registers (whichever are identified as the address source) contain
a value between H'OOOO' and H'03FF'; the F3852 DMI will
respond to addresses in the range H'0400' through H'07FF'. No
device will respond to addresses beyond H'07FF', even though
such addresses may exist in PCO and/or DCO.
Instruction Execution Sequence
Every instruction execution sequence ends with an instruction
code being fetched from memory to identify the next instruction
cycle. The instruction code is loaded into the CPU instruction
register, out of which it is decoded by the CPU control unit logic.
An instruction fetch is executed during the last instruction cycle
of the previous instruction, as illustrated in Figure 9.
Each device compares its address space with the contents of PCO
and DCO, whichever is identified as the address source, and only
responds to a memory access command if the contents of PCO or
DCO is within the device's address space.
There is a group of F8 instructions that cause operations to occur
entirely within the F3850 CPU. These instructions do not use the
data bus, therefore can execute in one cycle. Since one-cycle instructions do not use the data bus, no ROMC state needs to be
generated for the one-cycle instruction being executed; therefore,
as illustrated in Figure 9, ROMC state 0 is specified, causing the
instruction fetch of the next instruction.
If all memory address registers (PCO, PC1, DCO, and DC1) are to
contain the same information, then ROMC states that require any
of these registers' contents to be modified must be acted upon by
all devices containing any of these four registers. If devices are
not to compete when an ROMC state specifies that a memory
access must be performed, then only a device whose address
space includes the identified memory address must respond to
the ROMC state.
Multi-cycle instructions must end with a cycle that does not use
the data bus; ROMC state 0 is specified at the beginning of this
last instruction cycle, causing the next instruction to be fetched.
Following an instruction fetch, CPU logic decodes the fetched
instruction code and executes the specified instruction. There
are Five types of instruction cycles that can follow.
As illustrated in Figure 8, the five ROMC signals that define the
ROMC state are output early in the instruction cycle and are maintained stable for the duration of the instruction cycle; i.e., only one
ROMC state can be specified per instruction cycle. Therefore,
devices can only be called upon to perform one instruction execution related operation per one instruction cycle.
1. Operations may all be internal to the CPU. This will be the last
or the only cycle for an instruction, and will specify ROMC
state 0, as illustrated in Figure 9.
Figure 8 ROMC Timing Signals Output by F3850 CPU
1_ td,
WRITE
\ ~____________~L ___ ~___~/r---,
_____\~
1...-- ---'1
LONG CYCLE
Id3
ROMe
________________J)(r---------------S-T-A-Bl-E--------------3-15
II
F3850
Figure 9A Short Cycle Instruction Felch
XTLY
td,
WRITE
-r- p~-::::I
1- ld,
_--J~I-PW'--I-'
N1----'-------------J
~_ __
-----PWL--,--.,.---------+lrl
-
-
I
-_ _ _ _ _; . . . 1_ - - , .
ROMC
I
){~'___________________T_R_U_E_RO_M_C_S_TA_T_E_D__________________~I~I-------
1
--------------------------~il_ld3~
II
~-~I
I
X
I
OP CODE FOR NEXT 1
INSTRUCTIOIII
____________________________________________________- J
I
ONE CYCLE OF THE SINGLE, LONG
CYCLE OS IIliSTRUCTION
(DECREMENT SCRATCHPAD)
IIIEXT
INSTRUC!'ON
I
Figure 9B Long Cycle Instruction Felch (During DS Only)
XTLY
ld,~P~-j
WRITE
_~AI
11-.:....-:-:-ld,----PWs-----.1
N------~I
_PW'-!I
I
ROMC
TRUE ROMC STATED
I :'
II'
I
______________________
II
II
----------------------;..1----""'""x
I-- !do --I
DATA
BUS
NII...-_ __
1- tdb, ----! 1
~-----------------------------------J){'-----O-P-C-OD-E-F-O-R-NE-X-T-IN-ST-R-U-CT-IO-N-----ONE CYCLE OF A SIIliGLE CYCLE
INSTRUCTIOI>j, OR ,LAST CYCLE OF A
MULTICYCLE INSTRUCTION
3-16
IIIEXT
I,NSTRUCTION
F3850
2. Data may be transferred between the F38S0 CPU and
Refer to the "Instruction Cycle Execution and Timing" section for
a list of the instruction cycles and their associated ROMC state.
memory devices. See the "Referencing Memory" section.
3. Data may be transferred from one memory device to all
memory devices. The CPU is not the transmitter or the
receiver of data in this transfer. See the "Memory-to-Memory
Data Transfers" section.
4. Data may be transferred to or from an I/O port, as described
in the "Input/Output Interfacing" section.
5. An interrupt may be acknowledged, as described in the
"Interrupts" section.
Referencing Memory
Memory may be referenced during an instruction cycle either to
transfer the data from the CPU to a memory word or to transfer
data from a memory word to the CPU. A memory reference
occurs as shown in Figure 10.
If data is being output by the CPU, then the delay before data output is stable will be tdb 1 when data comes from the accumulator;
the instruction cycle will be long. The delay before data output is
stable will be tdb2 when data comes from the.scratchpad; the
instruction cycle in this case will also be long.
Every F8 instruction is executed as one, or a sequence of,
standard instruction cycles. Timing for the standard instruction
cycles is illustrated in Figures 9, 10, 11 and 12
Figure 10 Memory Reference Timing
PWL
-I
1_:- - - - - P W s - - - - - - - - I
(WRITE)
J,.---~~------------------.JI1
N
1
~I-~----------------~bl----------------~
'1
DATA BUS (1)
1._--- ~D
1
1
1
1
X
I
L
I
1
(HIGH IMPEDANCE)
1
- - - - - -••
I
1
X1
DATA BUS (1)
~I-~---------~~-----------.·1
STABLE
I
XI-
DATA BUS
I-
X
DATA BUS
X
(1) liming for CPU outputting data onto the data bus.
-I
·1
DATA STABLE
lDATA BUS
tdb4
tdbs
td""
1
'1
DATA STABLE
(2) There are four possible cases when inpulling data to the CPU. via the data bus
lines which depend on the data path and the destination in the CPU, as follows:
Delay tdb, is the delay when data is coming from the accumulator.
tdb3: Destination -IR (instruction Fetch)
tdb,: Destination - Accumulator (with ALU operation - AM)
tdbs: Destination - Scratchpad (LR K,P etc.)
tdb6 : Destination - Accumulator (no ALU operation - LM)
Delay tdb 2 is the delay when data is coming from the scratch pad (or from a
memory device).
Delay tdbo is the delay for the CPU to stop driving the data bus.
In each case a stable data hold time of 50 ns from the WRITE reference point
is required.
3·17
•
F3850
Figure 11
Timing for Data Input or Output at 1/0 Port Pini
XI"
(WRITE)...!
I
I
I
I
I
PWs
I"
I
1/0(1)
I,u
DATA MAY CHANGE
STABLE
X
-rll-
Ih
~ II
I
DATA MAY CHANGE
I
I.
·1
I"
DATA
FROM
OLD
OUTS
1/0(2) ______________~~--------------------------J){~-------N-EW--D-A-T-A------~~------------------------I
(1) This represents the timing for data at the 1/0 pin during the execution of the
INS instruction, i.e., the CPU is inputting.
(2) This represents the timing for data being output by the CPU at the 110 pin.
Figure 12 Interrupt Signals TIming
PWs
I"
WRITE-'!
"",,- PW2
I
j'iI.
PWL
·1
N
I
ROMC
ICB(1)
~~~J
I
I
X
i' X
Id.
I
I"
INTREQ(2)
-I
I
I
I
I
I
I
I
I
I
I
Is,
EXT RES
'-·1
TRUE
~Ids:j
INT REQ (2)
/
,"
·1
I
"
(1) The ICB signal will go from a 1 to a 0 following the execution of the E1 instruction and will go from a 0 to a 1 following either the execution of the 01 instruction or the CPU's acknowledqement of an interrupt.
(2) This is an input to the CPU chip and is generated by a PSU or F3853 M1 chip
The open drain outputs of these chips are all wire-AN Oed together on this
line with the pull-up being located on the CPU chip. For a 0 to 1 transition the
delay is measured to 2.0 V.
.
.
3-18
F3850
If data is being input to the CPU, then the delay before incoming
data must be stable depends on the destination of the data, as
illustrated in Figure 10.
1/0 port pin is a ''wire-AND'' structure between an internal latch
and an external signal, if any. The latch is always loaded directly
frorn the accumulator.
The type of data transfer is identified by the ROMC state that is
output at the beginning of the instruction cycle.
Each F8 1/0 pin can be set high or low under program control.
If a 1 (high) is presented at the latch, then gate (b) turns on and
gate (a) turns off, so that P is at Vss (low). If a a (low) is presented
at the latch, then gate (a) turns on and gate (b) turns off, so that P •
is at VDD (high).
The instruction fetch may also be viewed as a memory reference
operation where the destination is the instruction register. Timing
for this case is illustrated in Figure 9.
When outputting data through an 1/0 port, the pin can be
connected directly to a TTL gate input ("TTL Device Input"
in Figure 13). Data is input to the pin from a "TTL Device
Output" in Figure 13.
Memory-to-Memory Data Transfers
In response to appropriate ROMC states, data can be transferred from one memory device to all memory devices during
one instruction cycle. For example, data can be transferred
from a memory byte within (or controlled by) one memory
device, to one byte of an address register (PCa or DCa) within
all memory devices.
Three ROMC states (C, E, and 11) specify operations of this type,
and Figure 10 illustrates timing for the data transfer.
In Figure to, tdb2 is the delay until data from memory or a
memory address register is stable on the data bus.
In normal operation, high or low levels at P drive the external
TTL device input transistor (d). If a low level is set at P, transistor
(d) conducts current through the path J, 1, P, and FET(b). This is
transferred as a low level to the rest of the circuits in the TTL
device and results in a high or low level at the output of the
device, depending on its characteristics. If the level at P is set
high, transistor (d) does not conduct current, and a high level is
transferred by (d).
InputlOutput Interfacing
Programmed I/O in the F8 microcomputer system is influenced
by the design of the 1/0 port pins. As illustrated in Figure 13, each
When data is input to the 1/0 pin, high or low levels at a drive the
hysteresis circuit in the port and result in logic ones or zeros being
transferred to the accumulator.
Figure 13
F8 1/0 Port Bit
1------
-----------1
I
Voo
I
Voo
I
I
I
II
I
1- _ _ _ _ _ _
TTL DEVICE INPUT
LATCH
[0------
Vss
L -_ _ _ _ _- ,
I
I
I
I
L _____ _
HYSTERESIS CIRCUIT
TTL DEVICE OUTPUT
(OPEN-COLLECTOR)
3-19
F3850
Since the I/O pin and the TTL device output at 0 are wire-ANDed,
it is possible for the state of one to affect the transfer of data out
from the I/O pin or in from the TTL device output. For example, if
the latch in the I/O port is set so that the pin is clamped low by
(b), then the level at 0 cannot pull P high. Conversely, if P is
clamped to a low level by (c), setting the latch for a high level
has no effect.
-
nothing happens until the next interruptable instruction comes to
the end of execution. In the case of the EXT RES signal,
execution of the interrupt routine begins in the machine cycle
immediately following that in which the signal goes low, provided that the setup time specified in Figure 12 has been met. The
EXT RES signal response logic ignores the ICB signal.
In response to the INT REO signal being low, when the CPU
acknowledges the interrupt, itforces thelCB signal high and
initiates instruction cycles with ROMC states 1C, OF, 13, and 00, in
that order. This causes program execution to branch to the interrupting device's address vector.
- All I/O port bits should be set for a high level, before data input; to
- prevent incoming logic zeros from being "masked" by logic ones
present at the port from previous outputs. In some instances, the
ability to mask bits of a port to logic 1 is useful. (Note that logic 1
becomes a 0 V electrical level at the I/O pin; logic 0 corresponds
to a high electrical level.)
In response to the EXT RES signal being low, when the CPU
acknowledges the interrupt, it forces the ICB signal high, then
initiates Instruction cycles with ROMC states 1C, 08, and 00, in
that order. This causes program execution to branch to memory
locationO.
The F8 CPU can execute two types of programmed I/O
operation:
1) I/O ilia the two CPU ports (0 and 1)
2) I/O via ports on the other deviCes
The Ice signal is pulled low by the E1 instruction and is returned
high by the 01 instruction.
InpuVOutput operations that use the two CPU I/O ports execute
in two instruction cycles. During the first cycle, the fetched
instruction is decoded; the data bus is unused. In this cycle data
is either sent from the accumulator-to the I/O latch or enabled
from the I/O pin to theaecumulator, depending on whether the
instruction is an output or an input. At the falling edge of the
WRITE signal (marking the end of the first cycle and beginning of
the second cycle), the data is strobed into either the latch (OUTS)
or the accumulator (INS), respectively. The second cycle is then
used by the CPU for its next instruction fetch. Figure 11 illustrates
I/O timing.
Instruction Set Summary
The F3850 CPU instruction set is summarized in Table 3. This section does not attempt to give complete directions for programming
the F8 microcomputer system; it explains signals and timing
associated with the execution of every instruction. Refer to F8
and F387D Guide to Programming for programming details.
The columns used in Table 3 are described below.
Op Code-The Op Code is the instruction mnemonic that
appears in the mnemonic field of an assembly language
instruction and identifies the instruction.
Note that for the data input (INS) the setup and hold times
specified are with respect to the WRITE pulse occurring at the
end of the first cycle in the two-cycle instruction. For output data
(OUTS) the delay is specified with respect to the falling edge
of the WRITE signal marking the beginning of the second cycle in
the two-cycle instruction.
Operand (8)-lf the instruction contains any information in the
operand field of the assembly language source code, the information is shown in this column. Arrows identify the portion of
object code that represents the operand field. Any portion of
object code that doeSnot"representthe operand fieid must
represent the mnemonic field. Table 4 eXplains symbology used
in the operand field.
InpuVOutput instructions that address I/O ports with an I/O port
address greater than H'OF' occupy two bytes; the first byte
specifies an IN or OUT instruction, while the second byte
provides the I/O port address. Required timing at I/O port pins is
given in the section of this data sheet that describes the device
containing the addressed I/O port.
Object CocIe-This is the hexadecimal representation of the
Interrupts
There are three CPU signals with interrupt processing; timing
for all signals is illustrated in Figure 12.
instruction's object code. The first byte of object code, or in
some cases the first hexadecimal digit of object code, represents
the Op Code. The operand is represented by the second and third
bytes of object code, if present, or in some cases by the second
hexadecimal digit of the first object code byte. Refer to Table 4 for
symbology used in the object code field.
An interrupt sequence is initiated by pulling either the INT REO
signal or the EXT RES signal low, In the case of the INT REO
signal nothing happens unless the ICB signal is low. Also,
Cycle-This column identifies each instruction cycle for every
instruction. Every cycle is listed on a separate horizontal line and
is identified by the letter S for a short (four clock period) cycle or
3·20
F3850
Cycle
the letter L for a long (six clock period) cycle. Thus, the entry
o
S
1
2
3S
3L
4
5
6
represents an instruction that executes in one short cycle. The
entry
S
L
S
Represents
Figure 8
tdb 1 in Figure 10
tdb 2 in Figure 10
tdb3 in Figure 9A
tdb3 in Figure 98
tdb4 in Figure 10
tdb s in Figure 10
tdbs in Figure 10
II
Status Flags-Status flags are identified as follows:
represents an instruction that executes in three cycles: the first is
a short cycle; the second is a long cycle; the third (and last) is a
short cycle.
O-Overflow
Z-Zero
G-Carry
S-8ign
ROMC State-This is the state, as identified in the "ROMC Signal
Functions" section, that is output by the F3850 CPU in the early
stages of the instruction cycle.
Within each column, symbology is used as follows:
o
Timing-Timing for all instructions, except INS and OUTS
accessing 1/0 ports 0 and 1, can be created out of Figures 9 and
10. For the exceptions, Figure 11 is required.
1/0
Status not affected
Status set to 0
Status set to either 1 or O,depending on the results
of the instruction'S execution
Interrupt-An "x" in this column identifies an instruction that
disallows interrupts at the end of the instruction's execution. A
"y" identifies cycles in which the ICB is reset to 0 (cleared).
The ROMC lines are always set after a delay of td3, as shown in
Figure 9. The only timing variations for each instruction cycle are
data bus timing variations. Therefore, data bus timing is defined
using the delays tdb 1 through tdbs. With the exception of tdb3,
these time delays are unambiguous in that they are keyed to
either the leading edge or the trailing edge of the WRITE signal
high, for a long or short instruction cycle, as illustrated in Figure
10. There are two cases for tdb3, however, as illustrated in Figure
9. These are identified in Table 4 as 3S for Figure 9A and 3L for
Figure 98; tdb 1 through tdbs are otherwise identified by the
numbers 1 through 6.
Function-The effect of each instruction cycle is described in
this column using symbology given in Table 4.
Instruction Cycle Execution and Timing
Table 3 lists the instruction cycles, plus the ROMC state
associated with each cycle, for every F8 instruction. Note that
instructions are described in the table by order of ascending
instruction (first byte) object code. Table 4 lists the symbology
used in Table 3.
Cycles that do not use the data bus are identified by 0 in the
timing column; Figure 8 illustrates timing in this case.
Table 3 Instruction Cycle Execution and Timing
Op
Code
Operand(s)
Object
Code
Cycle
LR
LR
LR
LR
LR
LR
LR
LR
A,KU
A,KL
A,QU
A,QL
KU,A
KL,A
QU,A
QL,A
00
01
02
03
04
05
06
07
S
S
S
S
S
S
S
S
ROMC
State
0
0
0
0
0
0
0
0
Status Flags
Timing
0
Z
C
S
3S
3S
3S
3S
3S
3S
3S
3S
-
-
-
-
-
-.
-
3·21
-
-
-
-
-
-
-
Interrupt
Function
A A A A r12
r13
r14
r15
(r12)
(r13)
(r14)
(r15)
- (A)
- (A)
- (A)
- (A)
F3850
Table 3 Instruction Cycle Execution and TIming (Continued)
Op
Code
Operand(s)
Object
Code
lR
K,P
08
lR
P,K
09
ROMC
State
Timing
0
Z
C
S
7
B
0
15
18
0
0
0
12
14
0
17
14
0
6
9
0
16
19
0
16
19
0
6
9
0
0
5
5
3S
2
2
3S
3S
3S
2
2
3S
2
2
3S
3
5
3S
2
2
3S
2
2
3S
5
5
3S
3S
-
-
-
-
r12 - (PC1U)
r13 - (PC1l)
-
PC1U - (r12)
PC1l- (r13)
-
A- (ISAR)
ISAR- (A)
PC1 - (PCO);
PCOl - (r13)
PCOU - (r12)
lR
H,OC
11
SR
1
12
l
l
S
l
l
S
S
S
l
l
S
l
l
S
l
l
S
l
l
S
l
l
S
l
l
S
S
Sl
1
13
S
0
SR
4
14
S
Sl
4
15
lM
16
ST
17
lR
lR
PK
lR
lR
lR
lR
A,IS
IS, A
PO,a
a,oc
oC,a
OC,H
OA
OB
OC
00
OE
OF
10
COM
18
lNK
01
19
1A
EI
POP
1B
1C
Status Flags
Cycle
-
-
-
-
-
~
-
-
-
-
-
-
-
-
-
-
-
0
1/0
0
1
3S
0
1/0
0
1/0
0
3S
0
1/0
0
1
S
0
3S
0
1/0
0
1/0
l
S
l
S
S
2
0
5
0
0
6
3S
1
3S
3S
-
-
S
S
S
S
S
S
S
0
1C
0
1C
0
4
3S
0
3S
0
3S
0
-
-
-
-
-
-
-
-
-
OCOU - (r14)
OCOl - (r15)
-
OCOU - (r10)
OCOl - (r1l)
-
-
0
1/0
0
1/0
1/0
1/0
1/0
1/0
-
-
0
-
3S
-
-
-
3-22
-
-'
r1O- (OCOU)
r11 - (OCOl)
-
-
-
PCOl- (r15)
PCOU - (r14)
r14- (OCOU)
r15 - (OCOl)
-
-
-
x
-
-
-
Function
-
-
-
Interrupt
Shift (A) right one bit
position (zero fill)
Shift (A) left one bit
position (zero fill)
Shift (A) right four bit
positions (zero fill)
Shift (A) left four bit
positions (zero fil!) .
A - «OCO»
-
(OC)-(A)
-
-
y
A - (A) Ee H'FF'
Complement
accumulator
A- (A) + (C)
Clear ICB
Set ICB
x
PCO- (PC1)
x
F3850
'nIble 3
Op
Code
InslNctlon Cycle Execution and nmlng (Continued)
Operand(s)
Object
Code
LR
W,J
10
LR
INC
LI
J,W
1E
1F
20
aa
21
aa
22
aa
23
aa
24
aa
25
aa
aa
L
NI
ar
01
ala
XI
ala
AI
ala
CI
IN
OUT
PI
ala
PP
PP
jijj
I
JMP
jijj
I
OCI
pii
I
Nap
XOC
26
PP
27
PP
28
ii
jj
29
ii
ii
2A
ii
ii
2B
2C
t
3
Cycle
ROMC
Slate
8
8
8
8
L
8
L
8
L
8
L
8
L
8
L
8
1C
0
0
0
3
0
3
0
3
0
3
0
3
0
3
0
Status Flags
FuncUon
Timing
0
Z
C
S
0
38
38
38
6
38
4
38
4
38
4
38
4
38
4
110
110
110
110
-
-
-
110
110
-
-
r9- (W)
A- (A) + 1
A- H'aa'
110
A - (A) v H'aa'
3S
-
110
-
-
110
-
0
110
-
-
0
110
0
-
1/0
110
0
-
-
110
-
0
0
0
-
110
-
110
-
-
110
110
110
-
-
-
110
0
110
3
1B
0
3
1A
0
3
0
C
14
0
3
C
14
0
11
3
E
3
0
0
10
0
0
2
6
38
2
1
38
6
0
2
1
38
6
2
1
2
0
2
0
38
0
0
0
3L
-
-
110
110
1/0
110
-
3S
-
-
-
-
-
-
-
-
-
-
-
08
~
LR
A'r
y
8
0
38
-
-
LR
f,A
5f
8
0
3S
-
Ll8U
~
sr
8
0
38
-
-
-
-
3·23
x
A - (A) v H'aa'
A - (A) EEl H'aa'
A - (A) + H'aa'
-
L
L
8
L
L
8
L
8
L
L
8
L
L
L
8
L
8
L
8
8
8
8
8
L
-
W- (r9)
110
110
-
110
-
-
InlerNpt
-
Perform H'aa' + (A)
+ 1. Do not save result,
but modify status flags
to reflect result.
OB- PP
A - (1/0 Port PP)
OB-PP
1/0 Port PP - (A)
x
A-H'ii'
PC1 - (PCO) + 1
PCOL- H'jj'
PCOU - (A)
-
-
-
x
A-H'ii'
PCOL- H'jj'
PCOU - (A)
x
OCOU- ii
(increment PCO)
OCOL- jj
(increment PCO)
-
-
OCo:= OC1
r - (r) + H'FF' Decrement
scratchpad byte
A- (r)
r- (A)
ISARU -O'e'
•
F3850
'nIbIe 3 InstNCllon Cycle ExecuUon and Timing (Continued)
Op
Code
Operand(s)
,
LlSL
?
LIS
BT
e'li
AM
Cycle
ROMe
Slate
nmlng
0
Z
C
S
68+?
S
0
3S
-
-
-
7f
S
0
3S
-
M
S
1C
0
ii
S
3
0
-
-
-
-
S
S
L
0
1C
1
3S
0
2
-
-
-
-
1/0
1/0
1/0
1/0
88
AMO
89
8A
NM
OM
8B
XM
8C
CM
80
AOC
BR7
BF
INS
INS
OUTS
OUTS
8E
il
l,II.
00r1
Status Flags
Object
Code
8F
ii
gj.
ii
AO,A1
4
thru
15
00r1
A4
thru
AF
BO,B1
4
thru
15
B4
thru
BF
S
L
S
L
0
2
0
2
3S
4
3S
4
S
L
S
L
S
L
S
L
S
0
2
0
2
0
2
0
2
0
3S
4
L
S
S
S
L
S
S
L
S
S
S
S
S
S
L
L
S
S
S
L
L
S
A
0
3
0
1
0
1C
1
0
1C
3
0
1C
0
1C
1B
0
1C
0
1C
1A
0
1
3S
0
3S
2
-
-
-
-
1/0
1/0
1/0
-
-
-
110
0
1/0
-
-
0
110
1/0
1/0
-
-
0
0
-
3S
-
4
3S
110
1/0
4
3S
4
3S
0
2
3S
0
0
0
-
3S
-
0
0
3S
0
6
3S
0
3S
0
1
3S
0
-
-
3·24
-
-
-
-
110
1/0
-
-
A- H'oa'
Test e A W register
Res = Oso PCO = (PCO)
-
-
0
110
-
-
0
0
-
-
+2
Test e A W register
Res ~ 0 so PCO = (PCO)
+ H'ii' + 1
-
-
Function
ISARL- O'e'
-
1/0
1/0
1/0
-
3S
-
Interrupt
A - (A) + ((OCO)) Binary,
OCO- (DC) + 1
A - (A) + ((OCO)) Decimal,
OCO - (OCO) + 1
A - (A) A ((OCO));
OCO - (OCO) + 1
A - (A) A ((OCO));
OCO - (OCO) + 1
A - (A) EB ((OCO));
OCO - (OCO) + 1
Set status flags on basis
of ((DC)) + (A) + 1;
OCO - (OCO) + 1
DC - (~C) + (A)
-
-
PCO - (PCO) + 2
because (ISARL) = 7
PCO - (PCO) + H'ii' + 1
because (ISARL) ~ 7
Test tAW. register
Res = 0 so PCO = (PCO)
+ H'ii' + 1
Test tAW. register
Res ~ Oso PCO = (PCO) + 2
1/0
A - (I/O PortOor1)
-
-
110
-
DB - Port address (4 thru 15)
A - (Port 4 thru 15)
I/O Port 0 or 1 - (A)
DB - Port address (4 thru 15)
x
Port (4 thru 15) (A)
F3850
Table 3
Instruction Cycle Execution and Timing (Continued)
Op
Code
Status Flags
Timing
0
Z
C
S
r
Cr
S
0
3S
1/0
110
1/0
1/0
A - (A)
+ (r) Binary
ASD
r
Dr
1C
0
0
0
3S
3S
1/0
1/0
110
1/0
-
-
-
A - (A)
-
+ (r) Decimal
0
1/0
0
1/0
A- (A) ED (r)
0
1/0
0
110
A - (A) v (r)
-
IDLE
PCOl - In!. address
(lower byte); PC1 - PCO
PCOU - In!. address
(upper byte)
Operand(s)
Cycle
XS
r
Er
S
S
S
NS
r
Fr
S
0
3S
xx
L
l
1C
OF
0
2
-
l
13
2
-
S
S
l
S
0
1C
B
0
3S
0
1
3S
-
RESET
Table 4
xx
-
-
-
Interrupt
-
-
-
-
-
-
y
-
-
-
x
-
-
-
-
-
-
-
y
x
Function
IDLE
PCO - 0, PC1 - PCO
Instruction Execution and Timing Symbology
Symbol
A
(A)
a
aa
bb
Binary
C
DB
DCO
DCOl
DCOU
DC1
Decimal
H
ROMC
State
AS
INTRPT
e
Object
Code
Interpretation
The accumulator
The complement of accumulator contents
A single hexadecimal digit being interpreted as
data
Two hexadecimal digits being interpreted as a
single byte of data or as the high order byte of 16
bits of data
Two hexadecimal digits being interpreted as the
low order byte of 16 bits of data
Binary arithmetic specified
The carry status flag
FB system data bus
The primary data counter register
The low order byte of the primary data counter
register
The high order byte of the primary data counter
register
The secondary data counter register
Decimal arithmetic specified
A single octal digit being interpreted as data
Scratchpad bytes 10 and 11
Two hexadecimal digits being interpreted as the
high order byte of a 16-bit address oras a simple
byte address displacement
Symbol
Interpretation
ISAR
ISARL
ISARU
The 6-bit scratchpad address register
The low order three bits of ISAR
The high order three bits of ISAR
Scratchpad byte 9
Two hexadecimal digits being interpreted as the
low order byte ola 16-bit address
Scratchpad bytes 12 and 13
Scratchpad byte 13
Scratchpad byte 12
The overflow status flag
A single hexadecimal digit being interpreted as an
I/O port address (O-15)
Two hexadecimal digits being interpreted as an I/O
port address (0-255)
The program counter register
The low order byte of the program counter register
The high order byte of the program counter
register
The stack register
The low order byte of the stack register
The high order byte of the stack register
Scratchpad bytes 14 and 15
Scratchpad byte 15
Scratchpad byte 14
J
jj
K
Kl
KU
o
P
PP
PCO
PCOl
PCOU
PC1
PC1l
PC1U
Q
Ql
QU
3·25
•
F3850
Table 4 Instruction Execution and Timing Symbology (Continued)
Interpretation
Symbol
Single hexadecimal digit interpreted as scratch pad
address:
4 = 0 through B for locations 0 through B in
scratchpad
r = C for ISAR as address source with no change.
after access
r D for ISAR as address source with
ISARL = ISARL + 1 after access
r = E for ISAR as address source with
ISARL = ISARL-1 after access
r = F is not allowed
The sign status flag
A single hexadecimal digit identifying a status
condition that is tested by a Branch on
Condition instruction
The status register
=
S
W
Interpretation
Symbol
Z
1\
v
Ea
0
(()
+
The zero status flag
The logical OR of a-bit quantities on each side of
this symbol is specified
The logical AND of a-bit quantities on each side of
this symbol is specified
The logical Exclusive-OR of a-bit quantities on
each side of this symbol is specified
The value to the right of this symbol is to be loaded
into the location specified on the left of this symbol
The contents of the location within the brackets is
specified
The contents of the memory word addressed by
the contents of the location within the double
brackets is specified
The binary address of a-bit quantities on each side
of this symbol is specified
ROMC SIgnal Functions
Table 5 describes the ROMC signals and their functions.
Table 5 ROMC Signal Functions
ROMe
Cycle
4 3 2 1 0 HEX Length
o0
0 0 0
00
S,L
o0
001
01
i..
00010
02
L
o0
0 1 1
03
L,S
00 1 00
00101
o0 1 1 0
o0 1 1 1
o 1 000
04
05
06
07
08
S
L
L
L
L
a
09
L
OA
OB
L
L
1 001
o1
o1
0 1 0
0 1 1
Function
Instruction Fetch. The device whose address space includes the contents of the PCO register must
place on the data bus the op code addressed by PCO; then all devices increment the contents of PCO.
The device whose address space includes the cOntents of the PCO register must place on the data bus
the contents of the memory location addressed by PCO; then all devices add the a-bit value on the data
bus, as a signed binary number, to PCO.
The device whose DCO addresses a memory word within the address space of that device must
p1ace-on tlTe-uata- bus the contents of the memory location addressed 'by DCO;then-all-devices
increment DCO.
Similar to 00, except that it is used for Immediate Operand fetches (using PCO) instead of
.
instruction fetches.
Copy the
clock periods, or every 3.953 milliseconds for a 500
nanosecond clock.
For example, a value of 200 (11001000, or H'C8') loaded
into the programmable timer becomes 215 timer counts.
The timer therefore times out in 3.33 milliseconds, if the
period of clock signal cI> is 500 nanoseconds.
If the timer is actually loaded with a zero value, it times
out in 24 counts, whereas once it has timed out it next
times out in 255 counts (I.e., a time·out is not the same
as counting down to zero).
A value of 255 (H'FF') loaded into a programmable timer
stops the timer.
All timers run continuously, unless they have been
stopped by loading H'FF' into the timer. Upon timing out,
3·60
F3852/F3853
Fig. 5 Memory Refresh and DMA Timing During Long·Cycle Memory Read, with Address Out of Data Counter
3.0 tis
-I
\
WRITE
1.021ls
1.251'5
l--450ns
ADDRESS LINES
FOR REFRESH
1;::600 n o _
CPU AD DR
-
1.2Sp.s
ADDRESS LINES
FOR DMA
CPUADDR
REFRESH ADDR
_400n'~DMAADDR_
200ns ~.
I
530 ns
HIGH IMPEDANCE
300 ns
DATA BUS
DATA STABLE FROM RAM
2.05 {tS
1.25/-1s
CPU READ
CPU SLOT
-
V
_450no'-.1
170 ns
[..-
\
2.27 ItS
~
MEMIDLE
MEMIDLE
FOR DMA
-
200 ns
~
-
2.2Sp.s
~
750 ns
CYCLE REO
!~SOi~
250 ns
I~
\-
3.25 1l5
-I
-I
1.0/ls
'600 ns for DUDM.
Fig. 6 Timer Block Diagram
PRESET TO GIVE TIMER CLK
AFTER TWO ADDITIONAL'" PERIODS
WHENEVER TIMER IS LOADED
JAM 8 BITS PARALLEL
IF LOADED
DECODE TIMER STATE
'FE' AS TIME-OUT>
____~
T3
~~-n~~~~-_a_~_4~G~T5=~
T7
3-61
II
F3852/F3853
Depending on the contents of the interrupt control
register, the SMI interrupt control logic can be accepting
timer interrupts or external interrupts, or neither, but
never both.
When the timer and timer interrupt are being set to time
a new interval, the timer must always be loaded before
enabling the timer interrupt; loading the timer clears any
pending timer interrupts. When the timer interrupt is
enabled, any pending timer interrupt is acknowledged
and forwarded to the CPU. Since the timer runs
continuously, unless stopped under program control,
enabling the timer before loading a time count can
cause errors.
The OC and 00 I/O ports are used for the interrupt
address vector upper and lower bytes, respectively. They
can be written into and read from using the I/O
instructions.
Since only three device pins are available for use by
interrupt logic, there is no priority out signal. This means
that if an SMI is in an interrupt priority daisy chain, it
must be the last device in the chain or external logic
must generate a PRI OUT signal as shown in Figure 8.
Figure 7 illustrates a possible signal sequence for a
timer that is initially loaded with 200, then allowed to
run continuously.
Fig. 7 Time·Out and Interrupt Request Timing
The SMI interrupt address vector consists of two
programmable I/O ports. The interrupt address vector is
set under program control, rather than being a mask
option (as with the F385l PSU). Even though the SMI
interrupt address vector is programmable, bit 7 is still set
to 0 for a timer interrupt, or to 1 for an external interrupt.
f.--3.3 ms -*0---3.953 ms-_-t---3.953 ms _ _
A
-·r
D
~"l
D
-'r
Address Contentions
When a OMlor SMI is present in an F8 system that
includes a PSU, address contentions occur while using
the XDC instruction.
D
A - 200 LOADeD INTO TIMER
B - FIRST TIME OUT
C - SECOND AND SUBSEQUENT TlME·OUTS
D - INTERRUPT SERVICE ROUTINES BEING ENTERED BY CPU
1,.12,13 - INTERVALS BETWEEN TIME·OUT INTERRUPT REQUEST REACHING
INTERRUPT LOGIC AND SERVICE ROUTINES BEING ENTERED BY CPU
The XDC instruction (ROMC state TO) causes the
contents of data counters DCO and DCl to be
exchanged; having no DCl register, the PSU does not
respond to this instruction. Therefore, the PSU and
memory interface devices can have different values in
their DCO registers, and each value can be within the
different address spaces of the two memory devices. An
instruction that requires data to be output from the DCO
register may then cause two devices to simultaneously
place different data on the data bus.
Interrupt Logic
The interrupt control register or I/O port (OE) can be used
to enable or disable interrupts. Data is loaded into the
register or placed at the OE port using an OUT or OUTS
instruction; data cannot be read out of the register
or port.
Fig. 8 PRI OUT Signal GeneTation
The data at the 1/0 port is interpreted as follows:
8'XXXXXXOO'
8'XXXXXX01'
Disable all interrupts
Enable external interrupt, disable timer
interrupt
The contents of the interrupt control register are
interpreted as:
8'XXXXXX10'
8'XXXXXX11'
10K
Vcc---~A-----~~--~
Disable all interrupts
Disable external interrupt, enable timer
interrupt
In the above, "X" represents "don't care" binary digits.
3-62
F3852/F3853
Signal Descriptions
The SMI and DMI signals are described in Table 2.
Table 2 SMI/DMI Signal Descriptions
Mnemonic
Pin No.
Description
Name
Clock
cf>
2
Clock
WRITE
3
Clock
Clock inputs from the F3B50 CPU.
Address
15-B,
25-32
Address
Sixteen outputs through which an address is transmitted
to dynamic RAM. The address may come from the PCO or
DCO registers.
16-19,
21-24
Data Bus
Eight bidirectional lines that link the DMI/SMI with all other
devices in the FB system. Only data moving to or from the
address registers and 1/0 ports uses the data bus pins.
CPU READ
34
CPU Read
An output signal that, when high, specifies that data is to be
read out of a RAM location. When low, the signal is off; this
does not specify a write operation (the write operation is
specified by a RAM WRITE low signal).
CPU SLOT
5
CPU Slot
A DMI bidirectional signal that, when high, identifies portions
of an instruction execution cycle during which the F3B50 CPU
is reading out of or writing into RAM. When 0 is loaded into
port D and the CPU SLOT signal is held low by external logic,
the address line drivers and RAM WRITE driver go to a highimpedance state.
CYCLE REO
7
Cycle Request
An output signal that identifies each memory access period
within an instruction cycle by making a high-to-Iow transition at
the start of the memory access period. Does not identify events
that are to occur during the memory access period.
ADDR o-ADDR 15
Data Bus
DBo-DB?
Timing
The CYCLE REO signal is a divide-by-2 of cf> during all ROMC
states except ROMC state 05 (store-in-memory); it can be used
to generate the clock signals required by many dynamic RAMs.
MEMIDLE
4
Memory Idle
A DMI output that identifies portions of an instruction
execution cycle during which the FB system is not accessing
memory to read, write, or refresh. The MEMIDLE signal
therefore identifies the portion of an instruction cycle that is
available for DMA operations. The DMI can inhibit DMA by
holding MEMIDLE constantly low. The address drivers and RAM
WRITE driver are always in a high-impedance state when
MEMIDLE is high, so that a DMA device may drive the address
lines at this time.
3-63
II
F3852/F3853
Table 2 SMI/DMI Signal Descriptions (Cont.)
Mnemonic
Pin No.
Description
Name
Interrupt
EXT iN
7
External
Interrupt
An SMI input signal; a high·to-Iow transition is interpreted as
an interrupt request from an external device.
INT REO
4
Interrupt
Request
An SMI output signal that becomes the INT REO input to the
F3850 CPU. Must be output low to interrupt the CPU; this only
occurs if PRI iN is low and SMI interrupt control logic is
requesting an interrupt.
PRI iN
5
Priority In Line
An SMI input signal that, when low, sets the INT REO output
low in response to an interrupt.
35-39
Read Only
Memory Control
Five input lines that are the control signals output by the
F3850 CPU.
6
Random Access
Memory Write
An output signal that, when low, specifies data is to be written
into a RAM location. When high, the signal is off; this does not
necessarily specify a read operation.
33
Register Orive
A bidirectional line that, when used as an input, can be
clamped low by an external open-collector gate to prevent the
OMlor SMI from placing a byte from its PC1 or OCO register
onto the data bus. The OMI supplies an internal pull-up
resistor. When used as an output, REGOR can control data bus
buffers. The OMI internally clamps REGOR low except during
those ROMC states in which the OMI is required to place a
byte out of the PC1 or OCO registers, or either of its two
control registers (110 ports), onto the data bus.
Voo
40
Power Supply
Nominal + 5 Vdc
VGG
1
Power Supply
Nominal + 12 Vdc
Vss
20
Ground
Common power and signal return
Control
ROMC o-ROMC 4
Write
RAM WRITE
Register
REGOR
Power
DMIISMI Signal Timing
The OMI and SMI receive timing signals from the F3850
CPU, then output timing signals used by the dynamic
RAM and an F3854 OMA device, if present. Figures 9
and 10 illustrate the timing signals for the OMI and
SMI, respectively.
Within an instruction cycle, there may be either two or
three memory access periods, depending on whether the
instruction cycle is long or short. A memory access
period is equivalent to two clock periods, and is
identified by a CYCLE REO Signal, which is a divide-by-2
of . Whether the instruction cycle is short or long
depends on the source and destination of the data being
transmitted during instruction execution.
Timing of the F3853SMI INT REO, PRI IN, and EXT iN
interrupt Signals is identical to that of the F3851 PSU;
the remaining Signals have the same timing as the OMI,
except for the address lines.
3-64
F3852/F3853
Fig. 9 F3852 OMI Timing Signals
WRITE
~f----------- A03----------~
f.o-f---------IA02-----------'l~
I
IA01~
X
ADDL~~~~
I
:~==-==-==-~~=_IAO,_
----;::'-"1
IA05
lADs
y;;-r--'\.)(~~--R-EF-·--I------,.~
r-
REF.
.1
,~,~o E:?"'~ ~------I4-------------------CPUSLOT
MEMIDLE
t----------,.,
~r;~~~~I-M1~-~--IM~-S3~~~~~~~~~~1~·~-----
*ICS1
_
J
'\,f------- ~\
l---I::-\.~tC_Y-2=-~/.14-IM3-ICY3=_IM,
-=--~-----~1-:~~
.
~I
-1j
r
'\ ---- - I
t
C
Y
1
r-----~:-ICY'-----------IIWR1
t
IWR3]~
:.- --IWR,--------.J.!
t==
"'" -- t - -~=:1'---IRG2-=-~~__J1- -----------------r:
CYCLE REO
~-----c-
,-
}:_
!:=
1--<_-----------------tWA2
tD,
DATA BUS
INPUT
.,
-----------------------------~X'-------------
----ID'----1
~--------------------------------------------~
'-"14
DATA BUS
OUTPUT
-----------------------~ ~~----------------------------------------------------~
During the first memory access period, the device
outputs the contents of pca onto the address lines
(ADDR o-ADDR 15)·
If the assumed logic proves to be correct, or if no
memory access is to occur, the second access period
can be used for memory refresh or DMA.
In effect, the logic begins by assuming that a memory
read is to occur, with the memory address provided
by pca.
If the instruction decoded by the CPU specifies a
memory read with another memory address, the DMI
wastes the first access period; in this case, the
instruction cycle is always long. The required memory
access is performed during the second access and
memory refresh occurs, or DMA is implemented, in the
third access period.
While the pca contents are being. output on the address
lines, the control unit (in parallel) decodes the ROMC
state that has been received from the CPU.
3·65
•
F3852/F3853
Fig. 10 F3853 SMI Timing Signals
\.
WRITE
~--,
1'-_______________-L/____...l\......____LI-.,..___\~_
j.-- t
ADDRESS
LINES
I
CPU READ
RAM WRITE
REGDR
AD1
:=::J
vr----------~f
~
-1i-".:-=--=--=--=--=--=--=--=--=--:---IAD4-------.. .:~ 1.-------------------I:==tCR'~
tCR2
tWR, jr-----------------------
:~:
tWR2___,__~~t====tWR~':J
1:==._-=-=-:tRG,~=_=.~~~! ___________________ _
_ _ _
_1~+--:~~~~~~t~RG~2~~~~tD~4~~~~-~~~~~~~X---.--------------____
DATA BUS
INPUT _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _...J
~1·-------tD7
~
DATA BUS - - - - - - - - - - - - - - - - - - - - -
------------------
-----------------...J..
OUTPUT _ _ _ _
I-tR;=iI..-_ _ _~_ _ _ _~I·_-_-_t_R2-=-~--+ix
~.":~
{:,..J
_ _~~-------------------~~--------'~
_ _ _----'lir-.
tEX--l
EXTINT
'---
3·66
F3852/F3853
If a memory write instruction is decoded, no access
periods are available for memory refresh or DMA.
The implications of this relaxed data bus timing
parameter are that slower static memories may be used
with the SMI; on the other hand, memory controlled by
an SMI cannot be accessed by an F3854 DMA. Another
implication is that a latching type buffer is not needed
between memory and the data bus.
Four variations of the instruction cycle result. The timing
diagrams (Figures 11-18) illustrating the four variations
represent worst cases and assume td 2 = 150 ns. The four
variations are:
~
Instruction Execution
1. The instruction fetch. The memory address originates
in program counter pca, and the instruction cycle is
short. (Timing is shown in Figures 11 and 12.)
The DMI and SMI respond to signals that are output by . . .
the F385a CPU in the course of implementing instruction
cycles. The actions taken by the DMI and SMI during
instruction execution are a function of the ROMC state.
2. An immediate operand fetch. The memory address
originates in program counter pca, and the instruction
cycle is long. (Timing is shown in Figures 13 and 14.)
Data Output by RAM
Figures 11 through 16 illustrate the worst-case timing
when RAM, controlled by the DMI, outputs data onto the
data bus. (In these figures, it is assumed that the CPU
SLOT Signal is used to strobe the RAM data into the data
bus latches.)
3. A data fetch. A data bYle is output from an address
register, or the memory address originates in data
counter DCO; therefore, the instruction cycle is long.
(Timing is shown in Figures 15 and 16.)
4. A memory write. Data is written into the RAM location
addressed by DCO. (Timing is shown in Figures 17
and 18.)
.
The CPU READ signal is output high by the SMIIDMI to
enable transfer of data from the data bus buffers to the
data bus. Dynamic RAM has its own connection to the
data bus through buffer/latches; data is not transferred
through the DMI/SMI. (A CPU READ high signal is active
when its respective data bus drivers are turned on.)
The CPU SLOT and MEMIDLE signals identify the way a
memory access period is being used. When the F3850
CPU is accessing memory, the CPU SLOT signal is high;
RAM WRITE and the address lines are driven at this time.
When
SLOT
When
SLOT
Data Output by the DMI/SMI
The REGDR signal defines the address space of the
address registers. If an ROMC state received by the
DMI/SMI requires data to be output from an address
register, the device becomes the selected data source if
the REGDR signal is allowed to go high.
memory is available for DMA access, the CPU
Signal is low and the MEMIDLE signal is high.
the DMI is refreshing dynamic memory, the CPU
and MEMIDLE signals are both low.
The DMI logic is able to achieve two memory accesses
within one instruction cycle.
Data Input to RAM
Figures 15 and 1-6 illustrate timing when data is written
into RAM. Data is transferred through 3-state buffers on
the data bus and into. RAM. The RAM WRITE signal is
pulsed low by the DMI/SMI to enable the transfer of data
off the data bus into RAM. The 3-state buffers or
multiplexers between the data bus and RAM WRITE data
lines are necessary if DMA sources are also allowed to
write into RAM.
Buffer/latches are placed on the F8 data bus I.ines
between the RAM and the F8 system to hold the data
fetched· during the first access.
The SMI, without memory refresh and DMA capabilities,
does not generate three timing signals (CPU SLOT,
CYCLE REO, and MEMIDLE). These device pins are
instead used by interrupt logic.
Data Input to the DMI/SMI
Address contention is created by having duplicate
address registers. One method for resolving the
contention is to force every memory device to read data
into its address registers whenever an ROMC state
specifies any such operation. Address space concepts
therefore do not apply when data is read into the
address registers.
Since the DMI does not access memory within a Single
memory access period, as identified by the CPU SLOT
signal, data bus timing is relaxed when using the SMI as
compared to the DMI. Worst-case timing for the four
possible machine cycles is explained in the "DMI/SMI
Signal Timing" section.
.&
3-67
F38521F3853
Fig. 11 DMI Timing Signals Output During Short·Cycle Memory Read, with Address from Program Counter
JI+--r--2.0".----+i~
WRITE
-if~:----~~~___________________________JI'~------\k~--------------___
1-450 .0---1-500 ..--I
ADDRESS LINES
)(It'--------------ST-A-B-LE--------------
f.---770 .1'" 100 .I--.j
DATA BUS ___
~--------------J)(~-------D-A-TA-S-T-A-BL-E-F-RO-M-RA-M-------
~1.------__1.25__"·===~~~"1
F~····~.
r
CPU READ
CPU SLOT
-1170:.1MEMIDLE
CYCLE REQ
11.~27~"!·::::::::::~·~1
\~. _-----Jf
~"=tlr-"I
-~\1"___f~-"""'\'________
U..r
'600 nsfor DUDM.
Fig. 12 SMI Timing Signals Output During Short·Cycle Memory Read, with Address from Program Counter
.~~~---------------------~o".----------------------:l~
WRITE - ' "
1\ _ _ _----J1'~-----.1~:_ _
....!::;,::-~.. -~---------------ST-A-B-LE--------------,
DATA BUS
CPU READ
__
~ ----~-1~-~- -~- - - - - - - - - -1.-3-".~ ~- _-_-_-_-_-_-_-_~ JI\j~IJ
__
_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_--_
DATA STABLE FROM RAM
__ .•
~:.--\-~1.25~".;-_-_~}-------------------1----- .I'-+!
450
'600 ns for DUDM.
3·68
F3852/F3853
Fig. 13 DMI Timing Signals Output During Long·Cycle Memory Read, with Address Out of Program Counter
WRITE
r
-J
---J-;----.J'l
x_"_ _ _
3'0_".
_
_-
~450n.~~~on8~~-----------------------------------------------------------~
STABLE
ADDRESS LINES
DATA BUS ____
CPU READ
CPU SLOT
MEMIDLE
CYCLE REO
, ~-77-0-n-.~-1-00-n-·-----'-----I-----------------------------------------~---------------------------I)(~---------------D-AT-A-S-T-AB-L-E-F-RO-M--RA_M
______________
~I___.~-::"~_~
\ _ _----11
~170[
\
oon8~50n.~F
~
~.
1
_1250 n.
1.0 ".----..-:------.....J
.
n
\'---_ __
'600 ns for DUDM.
Fig. 14 SMI Timing Signals Output During Long-Cycle Memory Read, with Address Out of Program Counter
-_ _-----JI
~"'~ ",: ..-+=-·y_____________________________
w"'~ - {
\I-~~_-_
-_3'_0"8
'--
ST_A_B_LE_____________________________
DATA BUS
CPU READ
~I~._.~_~~~~~~~~~~~_1._65_"_.~~~~~~~~~~~j~~J
________________
___-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_
~...
STABLE DATA FROM RAM
~1.~--------_-_1_.2_5"_.__________:Jr---------------------------------------
~450ns'}
'600 ns for DUDM.
3·69
•
F3852/F3853
Fig. 15 DMI Timing Signals Output During Long·Cycle Memory Read, with Address Out of Data Counter
WRITE
-t=
i
450 ns ~I:
ADDRESS LINES
~
1.25/A s
L...
DATA BUS
CPU READ
CPU SLOT
2.151015
1=
1.25 JJS
~170n,r....)
Jt
j
STABLE
900 ns
~I
~
DATA STABLE FROM RAM
170 nSl I-
~}
.2.27/As
200 ns
~
750n0=1-
-J"
/
f
I"
MEMIDLE
CYCLEREQ
l
3.0/As
I
I--
250no\
1.0"0
)
/
\
/
Fig. 16 SMI Timing Signals Output During Long·Cycle Memory Read, with Address Out of Data Counter
WRITE
- - 3 . 0 " S - - /------.j~
JI4---I;"
450_n_s~:J:I:"':~ :~-_:~-_:~-_:~ -:'~ -1~.2~5~"0~ -=-~ - ~ - ~ - :~-_:..t-I_-...- - - - - - - - - - - - - - - _-_-_STABLE
-_-_-_-_-_~-_-_-_~_______
ADDRESS LINES
-==]~~~~~::;~;;:==~~~1'"""';;;;;;~9~00~n~S;;;;=-=-:W~1
2.15"s
~
DATA BUS _ I:
CPU READ
~~~ ,a.
}
3-70
DATA STABLE FROM
RAM
F3852/F3853
Fig. 17 DMI Timing Signals Output During a Write·to·Memory
WRITE - {
450 ns
~;
/
1.251'5
X
ADDRESS LINES
I·
1.3 fls
I"
CPU READ
I-
MEMIDLE
STABLE
X
DATA BUS
RAM WRITE
l
3.01'5
Cj l-----'!
-----1
1.85/-15
200 ns
MIN
f--
•
2.31-15 MAX
~450ns}
~170~_
~ 750ns==t
J 250n\ 1.0"S
II
DATA STABLE FROM CPU
200ns~
CYCLE REa
~
/
\..
Fig. 18 SMI Timing Signals Output During a Write·to·Memory
3.0
WRITE
\1"
~L
450 ns
-I"
/
1.25
l
f.ls
ADDRESS LINES
I-
1.3
j.ls
1.85/-15 MIN
RAM WRITE
ICPU READ
STABLE
*
DATA BUS
J ..
\L
).Is
2.3
j.ls
MAX
~450ns)
3-71
t
DATA STABLE FROM CPU
3~~~S1
~200ns~
}--_.../
•
MIN
F3852/F3853
Timing Characteristics
The timing characteristics of the DMI and SMI are
described in Tab/es 3 and 4, respectively.
Table 3 DMI Output Signals Timing Characteristics
Vss=OV, Voo= +5V ±5%, VGG= +12V ±5%, T A = O·Cto +70·C.
Symbol
Pt/>
tad 1
tad 2
tad 3
tad 4
tad s
tad 6
tcrl
tcr2
tcs;
tCS2
tcs3
tml
tm2
tm3
tm4
tcy,
tCY2
tCY3
tCY4
twrl
twr2
twr3
twr4
trgl
trg2
td 4
td 7
Nole.
Characteristic
Min
t/> Clock Period
Address Delay if PCO
Address Delay to High Z (Short Cycle With DMAOn)
Address Delay to Refresh (Short Cycle With REF On)
Address Delay if DC
Address Delay to High Z (Long Cycle With DMA On)
Address Delay to Refresh (Long Cycle With REF On)
CPU READ - Delay
CPU READ + Delay
CPU SLOT + Delay
CPU SLOT - Delay (PCO Access)
CPU SLOT - Delay (DC Access)
MEMIDLE+ Delay (PCO Access)
MEMIDLE- Delay (PCO Access)
MEMIDLE+ Delay (DC Access)
MEMIDLE- Delay (DC Access) .
WRITE to CYCLE REO - Delay
WRITE to CYCLE REO + Delay
CYCLE REO + to + Edge Delay
CYCLE REO- to- Edge Delay
RAM WRITE - Delay
RAM WRITE + Delay
RAM WRITE Pulse Width
RAM WRITE to High-Z Delay
REGDR - Delay
REGDR + Delay
WRITE to Data Bus Input Delay
WRITE to Data Bus Output Delay
0.5
50
tcs2+ 50
tcs2+ 50
2Pt/>+50- td 2
tcs3+50
tcs3+50
50
2Pt/>+50-td 2
80- td 2
2Pt/>+60- td 2
4Pt/>+60- td 2
2Pt/>+50- td 2
4Pt/>+50- td 2
4Pt/>+50-td 2
6Pt/>+50- td 2
80- td 2
Pt/>+80- td 2
1. CL =50 pF
2. CL=l00pF
3. C L =500 pF
4. CYCLE REO Is a dlvlde-by·2 01 -
REGISTER PCl
t
PROGRAM
COUNTER pea
5 HIGH ORDER
ADDRESS BITS
PAGE SELECT
~I
I
r
110 PORT
ADDRESS SELECT
I
~
II
'-
3-89
PRIIN
--+- 10
I-- INT REa--+- 9
EXT INT --+- 5
--
-
------------
DBo
DB.
DB2
DB3
DB,
DBs
DB,
DB,
.-
Ai
a-
I
=+21
22
=+27
28
=+33
34
= + 340'
I
~
~ Ai
A3
AS
Ao
=+="
=+=
=+=
=+= ~7
24
25
30
3'
3.
STROBE--+- 12
El
______________==
L.-
=+!
PRIOUT--+- 6
.-
110 PORTA
0
0
STACK
DATA BUFFER
.
•
I
I
I
LOWER BYTE
I
I
I
I
I
I
==
...-
I
I
~s-·-
So
--+- 20
~
~
~
=+= ~~
=+= ~~
e;
"
=+=~:
~RI~ ~ ~
3
F38T56
Signal Descriptions
The PSU input and output signals are described in Table 1.
Table 1 PSU Signal Descriptions
Mnemonic
Name
Description
Clock
The two clock Input signals originate at the F3850 CPU.
19,24
25,30
31,36
37,2
1/0 Ports A
Bidirectional ports through which the PSU communicates
with logic external to the microprocessor system.
20,23,
I/O Ports B
Pin No.
Clock
ell
8
110 Ports
I/0Ao I/OA7
1/0 Ba-
26,29
1/0 ~31, 35
38,1
Control
ROMCo ROMC4
Data Bus
DBa -
17,16
15, 14
13
Read Only
Memory
Control
Input signals that originate at the F3850 CPU and control
internal functions of the PSU
21,22,
27,28,
Data Bus
Bidirectional three·state lines that link the PSU to all other
devices within the microprocessor system.
Data Bus
Drive
A low output, open drain signal that indicates the data bus
currently contains data flowing from the PSU.
D~
33,34,
DBDR
39,40,
11
Strobe
STROBE
12
Interrupt
EXTINT
5
External
Interrupt
A high·to-Iow transition on this Input signal is interpreted as
an interrupt request from an external device.
INT REO
9
Interrupt
Request
This output signal is the INT REO Input to the F3850 CPU; it
must be output low to Interrupt the CPU, which occurs only if
PRI IN is low and PSU Interrupt control logic is requesting an
Interrupt.
Priority In
Unless this input is low, the PSU will not set thelNT REO
signal low In response to an interrupt.
Priority
Out
This output signal becomes the PRI IN signal to the next
device In the interrupt.prlo~ity daisy chain; it is output high
unless the PRI IN signal is entering the PSU low and the PSU
Is not requesting an interrupt.
Power Supply
Power Supply
Ground
+5V(± 5%)
+12V(± 5%)
System ground - 0 V; Voo and V~G are referenced to Vss'
PAliN
PRIOUT
10
6
Strobe
..
This output signal provides a positive pulse when I/O port is
being read by an input instruction or is being updated by an
'output instruction (F38T56).
Power
Voo
VGG
Vss
4
3
18
.3-90
F38T56
3. Or the trailing edge transition of the EXT INT pin when
in the pulse width measurement mode is executed.
Conditions 2 and 3 are explained in more detail.
1. When the timer interrupt request is acknowledged by
the CPU.
2. When a new load of the modulo-N register is performed.
The interrupt priority sequence is discussed in a
separate section.
An OUT or OUTS instruction to the timer loads the contents of the accumulator to both the timer and the 8-bit
modulo-N register, reset the prescaler, and clears any
previously stored timer interrupt request. As previously
noted, the timer is an 8-bit down counter clocked by the
prescaler the interval timer mode and in the pulse width
measurement mode. The prescaler is not used in the event
counter mode. The modulo-N register is a buffer for saving
the value most recently outputted to Port XXXXXX11. The
modulo-N register is used in all three timer modes.
Consider an example in which the modulo-N register is
•
loaded with H'64 (decimal 100). The timer interrupt request
latch is set at the 100th count following the timer start, and
the timer interrupt request latch is repeatedly set on
precise 100 count intervals. If the prescaler is set at .;- 40,
the timer interrupt request latch is set every 4000 clock
periods. For a 2-MHz clock, this setting produces 2-ms
intervals.
Interval Timer Mode
The range of possible intervals is from 2 to 51,200 clock
periods (1 lAs to 25.6 ms for a 2 MHz clock). However, approximately 50 clock periods is a practical minimum,
because the time between setting the interrupt request
latch and the execution of the first instruction of the interrupt service routine is at least 29 periods (the response
time is dependent upon how many privileged instructions
are encountered when the request occurs). Establishing
time intervals greater than 51,200 clock periods is a simple matter of using the timer interrupt service routine to
count the number of interrupts and saving the result in one
or more of the scratchpad registers until the desired interval is achieved. With this technique, virtually any time
interval or several time intervals can be generated.
When ICP bit 4 is. cleared (logic 0) and at least one prescale
bit is set, the timer operates in the interval timer mode.
When bit 3 of the ICP is set, the timer starts counting down
from the modulo-N value. After counting down to H'01', the
timer returns to the modulo-N value at the next count. On
the transition from H'01' to H'N', the timer sets a timer interrupt request latch. Note that the interrupt request latch
is set by the transition of H'N' in the timer, thus allowing a
full 256 counts if the modulo-N register is preset to H'OO'. If
bit 1 of the ICP is set and PRI IN is low, the interrupt request is passed to the F3850 CPU. However, if bit 1 of the
ICP is a logic 0, the interrupt request is not passed on to
the CPU. If bit 1 is subsequently set, the interrupt request
is then passed. Only two events can reset the timer
interrupt request latch.
Fig. 3 Timer and Interrupt Control Port Block Diagram
PRESCALER
CLOCK
-;-2. 5, 10, 20, 40, 100. or 200
INTERRUPT
CONTROL
PORT
(PORT XXXXXX10)
EVENT COUNTER MODE ~
2 PRE SCALE
-..-- 5 PRESCALE
...~ 10 PRESCALE
.............
- 20 PRESCAlE
.......-
- 40 PRESCALE
-'- 100 ,PRESCALE
200 PRE SCALE
44-----
4~3
2[1L~
L~X:~TR::~
L
INTERRUPT ENABLE
TIMER INTERRUPT ENABLE
EXT INT ACTIVE LEVEL
I
.. START/STOP TIMER
____
PULSE WIDTH/INTERVAL TIMER
3-91
F38T56
The timer can be read at any time and in any mode using
an input instruction (IN or INS) and can take place "on the
fly" without interfering with normal timer operation. Also,
the timer can be stopped at any time by clearing bit 3 of
the ICP. The timer holds its current contents indefinitely
and resumes counting when bit 3 is again set. Recall,
however, that the prescaler is reset whenever the ti mer is
stopped; thus, a series of starting and stopping results in a
cumulative truncation error.
modulo-N value are easily measured by using the timer in·
terrupt service routine to store the number of timer interrupts in one or more scratch pad registers.
A summary of other timer errors is given in the timing section of this specification. For a free-running timer in the interval timer mode, the time interval between any two interrupt requests can be in error by plus or minus six clock
periods, although the cumulative error over many intervals
is zero. The prescaler and timer generate preCise intervals
for setting the timer interrupt request latch, but the time
out can occur at any time within a machine cycle. (The
timer has two types of machine cycles; short cycles con·
sisting of four clock periods and long cycles consisting
of six clock periods.) The write clock corresponds to a
machine cycle. Interrupt requests are synchronized with the
write.clock, thus giving rise to the possible plus or minus
six error. Additional errors may arise due to the interrupt
request occurring while a privileged instruction or multicycle instruction is being executed. Nevertheless, for most
applications, all the above errors are negligible, especially if
the desired time interval is greater than one ms.
Event Counter Mode
As for accuracy, the actual pulse duration is typically slight·
Iy longer than the measured value, because the status of
the prescaler is not readable and is reset when the timer is
stopped. Thus, for maximum accuracy, it is advisable to use
a small division setting for the prescaler.
When ICP bit 4 is cleared and all prescale bits (ICP bits 5,
6, and 7) are cleared, the timer operates in the event
counter mode, used for counting pulses applied to the EXT
INT pin. If ICP bit 3 is set, the timer decrements on each
transition from the inactive level to the active level of the
EXT INT pin. Although the prescaler is not used in this
mode as in the other two timer modes, the timer can be
read at any time and stopped at any time by clearing ICP
bit 3, ICP bit 1 functions as previously described, and the
timer interrupt request latch is set on the timer's transition
from H '01' to H'N'.
Normally ICP bit 0 should be kept cleared in the event
counter mode; otherwise, external interrupts are generated
on the transition from the inactive level to the active level
of the EXT INT pin.
For the event counter mode, the minimum pulse width reo
quired on EXT INT is two clock periods, and the minimum
inactive time is two clock periods, therefore, the max·
imum repetition rate is 500 Hz.
Pulse Width Measurement Mode
When ICP bit 4 is set (logic 1) and at least one prescale bit
is set, the timer operates in the pulse width measurement
mode. This mode is used to accurately measure the dura·
tion of a pulse applied to the EXT INT pin. The timer is
stopped and the prescaler is reset whenever
INT is at
its inactive level. The active level of EXT INT is defined by
ICP bit 2: if cleared, EXT INT is active low; if set,
INT is
active high. If ICP bit 3 is set, the prescaler and timer start
counting when EXT INT transitions to the active level.
When EXT INT returns to the inactive level, the timer stops,
the prescaler resets, and, if ICP bit 0 is set, an external interrupt request latch is set. (Unlike timer interrupts, external
interrupts are not latched if the ICP interrupt enable is
not set).
External Interrupts
rn
When the timer is in the interval timer mode, the EXT INT
pin is available for non-timer related interrupts. If ICP bit 0
is set, an external interrupt request latch is set when there
is a transition from the inactive level to the active level of
EXT INT. (EXT INT is an edge-triggered input.) The interrupt
request is latched until either acknowledged by the CPU or
until ICP bit 0 is cleared (unlike timer interrupt requests,
which remain latched even when ICP bit 1 is cleared).
External interrupts are handled in the same fashion when
the timer is in the pulse width measurement mode or in the
event counter mode, except that only in the pulse width
measurement mode the external interrupt request latch is
set on the trailing edge of EXT INT (that is, on the
transition from the active level to the inactive level).
rn
As in the interval timer mode, the timer can be read at any
time and stopped at any time by clearing ICP bit 3, the
prescaler and ICP bit 1 function as previously described
and the timer still functions as an 8-bit binary down counter
with the timer interrupt request latch being set on the
timer's transition from H'01' to H'N'. Note that the EXT INT
pin has nothing to do with loading the timer; automatically
starts and stops the timer and generates external interrupts. Pulse widths longer than the prescale value times the
Interrupt Handling
Figure 4 is a block diagram of the interrupt interconnection
for a typical F8 system. Each PSU and each PIO has a PRI
3-92
F38T56
IN and a PRI 0iJi line so that they can be daisy chained
together in any order to form a priority level of interrupts.
the five control lines. The requesting local Interrupt circuit
sends a 16-bit interrupt address vector (from the interrupt
address generator) onto the data bus in two consecutive
bytes. The address is made available to the program
counter via the address demultiplexer circuits. The address
is simultaneously made available to all other devices connected to the data bus. It is the address of the next instruction to be executed. The program counter (PO) of each
memory device is set with this new address, while the
stack register (P) is loaded with the previous contents of
the program counter. The information in P is lost, and the
next instruction to be executed is thus determi ned by the
value of the interrupt address vector.
When a PIO receives an interrupt (either timer or external),
it pulls its PRI OUT output high, signaling all lower priority
peripherals that it has a higher .priority interrupt request
pending on the CPU. Also, when the PIO's PRI iN input is
pulled high by a higher priority peripheral, signaling the PIO
that there is a still higher priority interrupt request, it
passes that signal along by pulling its PRI OUT high. When
the CPU processes an interrupt request it commands the
interrupting device to place its interrupt vector address on
the data bus. Only that device whose PRI iN is low and that
has an interrupt request pending responds. Should there be
another lower priority device with a pending request, it does
not respond at that time because its PRI iN input is high.
The interrupt control bit (ICB) of the CPU )Ioaded in the W
register) allows interrupts to be recognized. Clearing the
ICB prevents acknowledgement of interrupts. The ICB is
cleared during power on and external reset and after an interrupt is acknowledged. The interrupt status of the PSU,
PIO, or MI devices is not affected by the execution of the
disable interrupt (01) instruction. At the conclusion of most
instructions, the fetch logic checks the state of the inter·
rupt request line. If an interrupt occurs the next instruction
fetch cycle is suspended and the system is forced into an
interrupt sequence.
If there is both a timer interrupt request and an external interrupt request when the CPU starts to process the
requests, the timer interrupt is handled first.
Within each local interrupt control circuit is a 16·bit interrupt address vector. This vector is the address to which the
program counter is set after an interrupt is acknowledged
and hence is the address of the first executable instruction
of the interrupt routine. The F38T56 has an interrupt ad·
dress that is particular to the version of the F38T56
selected by the user.
Mask Option Formats
Mask options must be submitted to Fairchild
Microprocessor Division before device manufacture. The
data to be stored in permanent memory may be submitted
in the form of an EPROM or HP2644/Hp2645 cartridge (Formulator format only). Other options must be specified on
the Fairchild ROM Code Entry Form, available from a
Fairchild representative.
Fifteen bits are fixed: bits 0 through 6 and 8 through 15. Bit
7 is dependent upon the type of interrupt. This bit is a 0
for internal timer generated interrupts and a 1 for external
interrupts. When the interrupt logic sends an interrupt request signal and the CPU is enabled to service it, the nor·
mal state sequence of the CPU is interrupted at the end of
an instruction. The CPU signals the interrupt circuits via
Fig. 4 F8 Interrupt Interconnection
CONTROL LINES
r---------,
CPU
ICB
...--------,
PSU/PIO
PSu/PIO
1
2
PRIORITY
PIO
(n)
SMI
PRIORITY
L - - - - - - - - - E X T E R N A L INTERRUPT LINES--------~
3·93
F38T56
Table 2 PSU DC Characteristics
Symbol
Parameter
Signal
Min
Max
V IH
Vil
VOH
VOL
IIH
10l
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Input High Current
Input Low Current
Data Bus (DBo-DB7)
2.9
Vss
3.9
Vss
Voo
0.8
Voo
0.4
3.0
-3.0
V
V
V
V
,..A
,..A
10H
10l
VIN
VIN
= -100,..A
= 1.6 mA
= Voo , 3-State Mode
= Vss' 3-State Mode
VIH
Vil
Il
Input High Voltage
Input Low Voltage
Leakage Current
Clock Lines (" WRITE)
4.0
Vss
Voo
0.8
3.0
V
V
,..A
VIN
= Voo
VIH
Vil
Il
Input High Voltage
Input Low Voltage
Leakage Current
Priority In and Control
Lines (PRI iN, ROMC oROMC4 )
3.5
Vss
Voo
0.8
3.0
V
V
,..A
VIN
VOH
VOL
Output High Voltage
Output Low Voltage
Priority Out (PRI OUT)
3.9
Vss
Voo
0.4
V
V
10H
10l
= Voo
= - 100 ,..A
= 1oo,..A
VOH
VOL
Il
Output High Voltage
Output Low Voltage
Leakage Current
Interrupt (INT REO)
Vss
0.4
3.0
V
V
,..A
Open Drain Output Note 1
1.0 mA
10l
VIN
Voo
VOH
VOL
Il
Output High Voltage
Output Low Voltage
Leakage Current
Data Bus Drive (DBDR)
Vss
0.4
3.0
V
,..A
External Pull-up
2.0 mA
10l
VIN
Voo
VOH
VOL
Input High Voltage
Output Low Voltage
STROBE
3.9
Vss
Voo
0.4
V
V
VIH
Vil
Vil
Input High Voltage
Input Low Voltage
Input Low Current
External Interrupt
(EXT INT)
2.9
Vss
Voo
0.8
-1.6
V
V
mA
VOH
VOH
VOL
VIH
Vil
III
Output High Voltage
Output High Voltage
Output Low Voltage
Input High Voltage
Input Low Voltage
Input Low Current
I/O Port Option A
(Standard Pull-Up)
3.9
2.9
Vss
2.9
Vss
Voo
Voo
0.4
Voo
0.8
-1.6
V
V
V
V
V
mA
VOH
VOL
VIH
Vil
Output High Voltage
Output Low Voltage
Input High Voltage
Input Low Voltage
I/O Port Option B
(Open Drain)
VOH
VOL
Output High Voltage
Output Low Voltage
I/O Port Option C
(Driver Pull-Up)
F3851 1.0
Vss
Voo
0.8
V
V
V
4.0
Vss
Voo
0.4
V
V
Vss
2.9
0.4
Units Test Conditions
=
=
=
=
10H = 1.0 mA
10l = 2.0 mA
liN = -130,..A
(Internal Pull-up)
VIN = 0.4 V
10H = - 30 ,..A, Note 5
10H = -150,..A
10l = 1.6 mA
Internal Pull-up to Voo,
Note 3
VIN
0.4 V, Note 4
=
External Pull-up
10l
2.0 mA, Note 3
=
10H
10l
Notes:
1. Pull-up resister to Voo on CPU.
2. Positive current Is defined as conventional current flowing into the pin referenced.
3. Hysteresis input circuit provides additional 0.3 V noise immunity, while internal/external pull-up provides TIL compatibility.
4. Measured while I/O port is outpulling a high level.
5. Guaranteed, but not tested.
3-94
= -1.0 mA
= 2.0 mA
F38T56
DC Characteristics
The dc characteristics of the PSU device are given in
table 2.
Supply Currents
VSS = 0 V
VOO
+5V ±5%
VGG = +12V ±5%
TA = O·C to + 70·C
=
Symbol
Parameter
100
IGG
Min
Typ
Max
Units
VooCurrent
28
60
mA
f
= 2 MHz, Outputs
VGGCurrent
10
30
mA
f
= 2 MHz, Outputs
Unloaded
Unloaded
Absolute Maximum Ratings
These are stress ratings only, and
functional operation at these ratings
or under any conditions above those
indicated in this data sheet is not implied. Exposure to the absolute max·
imum rating conditions for extended
periods of time may affect device
reliability, and exposure to stresses
greater than those listed may cause
permanent damage to the device.
Supply voltage VGG
Supply voltage Voo
1/0 port open drain option
Other 110 port options
All inputs and outputs
Storage temperature
Ambient temperature, under
bias
-0.3 V,
-0.3 V,
-0.3 V,
-0.3 V,
-0.3 V,
- 55·C,
+15V
+7V
+ 15 V
+7 V
+7 V
+ 150·C
O·C, + 70·C
Thermal resistance values:
Plastic:
BJA (Junction to ambient)
9Jc(Junction to case)
Ceramic:
9JA (Junction to ambient)
BJC (Junction to case)
Test
Conditions
= 60·CN'J (Still Air)
= 42·CN'J
= 48·CN'J (Still Air)
= 33·CN'J
3·95
•
F38T56
Recommended Operating Ranges
The recommended operating ranges of the PSU devices are
shown below.
Supply Voltage (VDD)
Part
Number
F38T56
MIN
+4.75 V
Supply Voltage VCG
TYP
MAX
+5V
+ 5.25 V
MIN
+ 11.4 V
TYP
MAX
+12 V
+12.6 V
Ordering Information
C
L
M
Part Number
Package
Temperature·
F38T56
F38T56
F38T56
F38T56
F38T56
F38T56
Ceramic
Ceramic
Ceramic
Plastic
Plastic
Plastic
C
L
DC
DL
OM
PC
PL
PM
M
C
L
M
= Commercial Temperature Range O·C to + 70·C
= Limited Temperature Range
- 40·C to + 85°C
= Military Temperature Range - 55·C to + 125°C
3·96
Vss
OV
F3861
Peripheral Input/Output
Microprocessor Product
Connection Diagram
Description
The Fairchild F3861 Peripheral Input/Output (PIO) device
provides two B-bit I/O ports, external interrupt, and a programmable timer. An 8-bit wide bidirectional data bus
transfers I/O data bytes between the F3870 Central
Processing Unit (CPU) and the PIO.
•
•
•
•
•
•
EXT INT
PiiiOUT
WRITE
DBs
lI
ROMC o
ROMC,
3-97
}
INTERRUPT
}
POWER
F3861
Device Organization
System Clock Timing
The peripheral input/output device includes 1/0 logic, timer
iogic, interrupt logic, data bus logic and control logic, as
illustrated in figure 1.
All timing within th!il F3861.PI0 is controlled by.the ell and
WRITE signals, which .areinput from the F3850 CPU. Refer
to the F3850 data sheet ·for a,description of these clock
signals. The WRITE clock. refreshes and updates PIO
registers, which are dynamic. The ell clock also drives the
programmable timer.
The interrupt logic responds to an interrupt request signal
originating from internal timer logic or an external device.
Based on priority considerations, tlie interrupt request is
passed on to the F3850 CPU. The programmable timer uses
a polynomial shift register in conjunction with interrupt
logic to generate real-time intervals.
1/0 Ports
Signal Descriptions
The F3861 input and output signals are described in table 1.
The PIO has two bidirectional 8-bit 1/0 ports used to
transmit data between itself and external devices. In binary
notation, the address for port A is XXXXXXOO and for port B
is XXXXXX01, where the X binary digits are the unique 1/0
port select code for the PIO (see table 2). For example, if
the port select code is 000001, port A may be called port 4
and port B· may be called port 5. (The PIO port select. code
is never designated as all Os, since ports 0 and 1 are reserved for the F3850 CPU.) In addition, the interrupt control Port
(ICP) is addressed as port XX>
WRITE
1/0 Ports
I/OAg-
1/0 A7
1/0 Bo
-
1/0 B7
Control
ROMCo
ROMC4
Data Bus
DBa DB7
3-99
•
F3861
Port Pin Description
An output instruction (OUT or OUTS) causes the contents
of the CPU accumulator (ACC) to be latched into the ad·
dressed port. An input instruction (IN or INS) transfers the
contents of the port to the ACC (port S is an exception that
is described later). The 1/0 pins on the PIO are logically
inverted; the schematic of an 1/0 pin and available output
drive options are shown in figure 2. Each output pin has an
output latch that holds the data last output to that pin. The
1/0 ports of the PIO are configured in the standard
pull·up option.
When outputting data through an 1/0 port, the pin can be
connected directly to a TTL gate input; data is input to the
pin from a TTL device output. Since the 1/0 pin and the TTL
device output are wire-ANDed, it Is possible for the state of
one to affect the transfer of data out from the 1/0 pin or in
from the TTL device output. In most cases, therefore, 1/0
port bits should be set for a high level (logic 0) before data
input to prevent Incoming logic zeros from being masked
by logic ones present at the port from previous outputs.
However, the ability to mask bits of a port to logic 1 is
useful during some input functions.
Programmable Timer
Figure 2
110 Pin Diagram with Output Buffer Options
The 8·bit shift register, addressable as an 1/0 port, functions
as a polynomial timer. This timer is loaded with a value of
delay; it counts down this value of delay and, after the
programmed interval, generates an interrupt through the
interrupt logic of the PIO.
z0
.
;:
TIL
a:
"Ii:
Z
0
u
a:
~
i
ta:
0
ta:
0
.. ...
Q
0
w
a:
g
The OUT or OUTS instruction is used to load the interval
value into the programmable timer; the port number is
H'OT, H'OS', H'23', or H'2T, as appropriate. The timer times
out after a time interval given by the product
H>....,.-I~T
::>
PIN
(period of CIl clock)
I;
x
(timer counts)
x
31
The timer continues to run after a time-out; subsequent
time-outs occur at intervals of 7905 CIl clock periods. The
timer does not run if it is loaded with the value H'FF'.
Interrupt Logic
The interrupt logic block is programmed by output instruc·
tions to the interrupt control port (port H'06', H'OA', H'22', or
H'2S', as appropriate). Only the least significant two bits are
used; their interpretation is as follows.
Contents of ICP
STANDARD
OUTPUT
OPEN DRAIN
OUTPUT
Interpretation
DIRECT DRIVE
OUTPUT'
Each 1/0 port pin is a wire-AND structure between an inter·
nal output data latch and the external signal. The latch is
loaded from the data bus. The output latches are not
initialized by the system reset sequence.
S'XXXXXXOO'
S'XXXXXX01'
Disable all interrupts
Enable external interrupt, disable
timer interrupt
S'XXXXXX10'
S'XXXXXX11'
Disable all interrupts
Disable external interrupt, enable
timer interrupt
Note: The X designation represents "don't care" binary digits.
3·100
F3861
Figure 3 PIO Data Bus Timing
--I
WRITE
td,
I-I
I
--I
td2
r-
_---Jt-~-~\I------....JI.. ____ _
\I...-_. . .,r_-_-_-_""'\L-.
PW2
LONG CYCLE
~td3-----1
ROMC
STABLE
td7
-I
X
DATA BUS OUTPUT
~I
td4
DATA BUS INPUT
STABLE
td7
DBDR
(START OF
DATA OUT)
STABLE
-
-I
\
~f~--------------------------------------------------
tda
DBDR (END OF
___________________
DATA OUT IN
SUBSEQUENT CYCLE)
Instruction Execution
The PIO responds to signals that are output by the F3850
CPU in the course of implementing instruction cycles.
Figure 3 illustrates timing during PIO data output to the
data bus. This timing applies whenever a PIO is the data
source. The PIO places data on the data bus, even in the
worst case, in time for the setup required by any F3850
CPU destination. The PIO receives a byte input from the
data bus when commanded by an output instruction to load
one of its two 1/0 ports or internal registers. Data bus timing requirements for input to the PIO are also shown in
figure 3; signal characteristics are given in the "Timing
Characteristics" section. The data bus drive (DB DR) signal
is low while data output by the PIO is stable on the data
bus. Thus, a DB5R low signal indicates that the data bus
currently contains data flowing from a PIO. For systems
with more than one program storage unit (PSU) or PIO, the
DBDR output signals may be wire-ORed and the result used
as a bus data flow direction indicator. The i5Bi5R signal
may remain low until timing interval td of the next
instruction cycle following the one in which DBDR was
set low.
3-101
The PIO device executes the OUT instruction in the same
manner as the OUTS instruction; the same is true for the IN
and INS instructions. The difference between the long- and
short-form instructions is only in the source of the
1/0 address.
The F8 inputloutput instructions place the 1/0 port address
on the data bus during one instruction cycle and then use
the data bus in the following instruction cycle to do the
actual 1/0 data movement. The read only memory control
(ROMC) lines coming from the F3850 CPU signal the PIO
that an 1/0 data movement is occurring during the current
instruction cycle. Therefore, the PIO needs to recognize
whether the contents of the data bus during the instruction
cycle just prior matched any of its four aSSigned 1/0 addresses, wherever the ROMC lines indicate an 1/0 transfer.
The address select logic constantly monitors the data bus
for a match to any of the four addresses and holds the
information of a match through the following cycle.
Input instructions that select a port cause the contents of
the selected port to be placed on the data bus during the
input cycle. Only the two 1/0 ports (lowest two addresses)
II
F3861
The interrupt address is unique to the version of the PIO
device selected by the user. Fifteen bits are fixed: bits a
through 6 and bits 8 through 15. Bit 7 (2') is dependent on
the type of interrupt. This bit is a a for internal timergenerated interrupts and a 1 for external interrupts. When
the interrupt logic sends an interrupt request signal and the
CPU is enabled to service it, the normal state sequence of
the CPU is interrupted at the end of an instruction. The
CPU signals the interrupt circuits through the five ROMC
lines. The requesting local interrupt circuit sends a 16-bit
interrupt address vector (from the interrypt address
generator) onto the data bus in two consecutive bytes. The
address is made available to the program counter through
the address demultiplexer circuits. It is simultaneously
made available to all other devices connected to the data
bus and is the address of the next instruction to be ex·
ecuted. The program counter of each memory device is set
with this new address while the stack register is loaded
with the previous contents of the program counter. The information i.n the program counter is lost. Thus, the next instruction to be executed is determined by the value of the
interrupt address vector.
respond to input instructions. Output instructions that
select a port transfer the contents of the data bus to that
port. Outputs of the latches change at the end of the 110
transfer cycle.
Interrupt Handling
A typical F8 system interrupt interconnection is shown in
figure 4. Each PSU and PIO has a PRI iN and PRI OUT line
so that they can be daisy-chained together in any order to
form a priority level of interrupts. When a PIO receives an
interrupt (either timer or external), it pulls its Pm OUT out·
put signal high, signaling all lower priority peipherals that it
has a higher priority interrupt request pending on the CPU.
Also, when the PIO device PRI iN input signal is pulled high
by a higher priority peripheral, signaling the PIO that there
is a still higher priorfty interrupt request, it passes that
signal along by pulling its Pm OUT signal high. When the
CPU processes an interrupt request, it commands the inter·
rupting device to place its interrupt vector address on the
data bus. Only the device with a PRI iN signal low and an
interrupt request pending responds. Should there be
another lower priority device with a pending request, it does
not respond at that time because its PRI iN input signal is
high.
The interrupt control bit (ICB) of the CPU (loaded in the W
register) allows interrupts to be recognized. Clearing the
ICB prevents acknowledgement of interrupts. The ICB is
cleared during power-on, during external reset, and after an
interrupt is acknowledged. The interrupt status of the PSU,
PIO, or memory interface (MI) device is not affected byex·
ecution of the disable interrupt (01) instruction from the
CPU. At the conclusion of most instructions, the fetch logic
checks the state of the intern,lpt request line. If an inter·
rupt, occurs the next instruction fetch cycle is suspended
and the system is forced into an interrupt sequence.
If there are both a timer interrupt request and an external
interrupt request when the CPU starts to process the requests, the timer interrupt is handled first.
Within each local interrupt control circuit is a 16-bit interrupt address vector. This vector is the address to which the
program counter is set after an interrupt is acknowledged
and is therefore the address of the first executable instruction of the interrupt routine.
Figure 4 Fa System Interrupt Interconnection
r -_________C~O~N~TROL-~L~IN~E~S--------~
CPU
PSU/PIO
1
ICB
PSu/PIO
2
PIO
(n)
SMI
L-_-'--________ EXTERNAL INTERRUPT L l N E S - - - - - - - - - . - - l
3-102
F3861
Interrupt Sequence
In figure 5, the dashed lines on the EXT INT (EI) timing illustrate the last opportunity for the EXT INT Signal to cause
the last cycle of a non protected instruction to become a
freeze cycle. The freeze cycle is a short cycle (four CII clock
periods) in all cases except where B is the decrement
scratchpad instruction, in which case the freeze cycle is a
long cycle (six CII clock periods).
Figure 5 details the interrupt sequence that occurs, whether
the interrupt request is from an external source through the
00 iNf pin or from the PIO device internal timer. Events
are labeled A through G.
Event A
An interrupt request must satisfy a set-up time requirement.
If not satisfied, the INT REO signal delays gOing low until
the next negative edge of the WRITE clock.
The INT REa Signal goes low on the next negative edge of
the WRITE signal if both the PRI iN signal is low and the
appropriate interrupt enable bit of the ICP Is set.
Event C
This is a no-operation (NO-OP) long cycle, allowing time for
the PRI IN/PRI OUT chain to settle. At a 2-Mhz CII clock rate,
a total of seven PIO, PSU, or MI devices can be daisychained without the need for look-ah.ead logic.
Event B
Event B represents the instruction being executed when the
interrupt occurs. The last cycle of B Is normally the instruction fetch for the next cycle. However, if B is not a privileged instruction and the CPU interrupt control bit is set, the
last cycle becomes a freeze cycle raher than a fetch. At the
end of the freeze cycle the interrupt request latches are inhibited from altering the interrupt daisy chain so that
sufficient time is allowed for the daisy chain to settle.
Event D
In PSU circuits, the program counter (PO) is pushed to the
stack register (P) to save the return address. The interrupting PIO places the lower eight bits of the interrupt vector
address onto the data bus. This is always a long cycle.
If B is a privileged instruction, the instruction fetch is not
replaced by a freeze cycle; instead, the fetch is performed
and the next Instruction is executed. Although unlikely to
be encountered, a series of privileged instructions would be
executed sequentially. One more instruction (a protected instruction) is executed after the last privileged instruction.
The last cycle of the protected instruction then performs
the freeze.
Figure 5
Event E
In this long cycle, the PIO places the upper eight bits of the
interrupt vector address onto the data bus. .
Interrupt Sequence
FREEZE
CYCLE
WRITE
EXT INT OR
TIMER INTERRUPT
1
I'I
1 1-1
1
-- A
--';'1- - -
-i-1
4---;
~:
I
III
PRIOUT _ - - - : - - ' ____ ..J
I. . .rl_ -I-J
I
PRI OUT OF NEXTPIO _ _ _ _ _ _ _
3-103
I
II
F3861
Event F
In this short cycle, the PIO interrupting interrupt request
latch is cleared. Also,the CPU interrupt control bit is
cleared, thus disabling interrupts until an EI instruction is
performed. Additionally, during Event F, fhe PAlIN/PRI OUT
daisy-chain freeze is removed, since the interrupt vector
address has been passed to the CPU. Another action is the
fetch of the instruction from the interrupt address.
Table 4 PIO Functions Versus ROMC States
ROMC State
Binary
Hex
Event G
This event starts executing the first instruction of the
interrupt service routine.
Summary of Interrupt Sequence
For the PIO, the interrupt response time is defined as the
iNT signal
time elapsed between the occurrence of the
going active (or the timer transition to H'N') and the beginning of execution of the first instruction of the interrupt
service routine. The interrupt response time is a variable
dependent on what the microprocessor is doing when the
Interrupt request occurs.
PIO Functions
01111
OF
If this circuit is Interrupting and is
highest in the priority chain, move
lower half of interrupt vector into
the data bus.
10000
10
Place interrupt circuitry in an inhibit state that prevents altering
the interrupt priority chain.
10011
13
If the contents of the data bus in
the prior cycle was an address of
110 ports on this device, move the
current contents of the data bus
into the appropriate port (110 A, I/O
B, timer or control).
11011
1B
If the contents of the data bus in
the prior cycle was an address of
110 ports on this device, move the
contents of the appropriate I/O
port onto the data bus (110 A
or I/O B).
m
As shown in figure 5, the minimum interrupt response time
is three long cycles plus two short cycles plus one write
clock pulse width plus a set-up time of an EXT INT signal
prior to the leading edge of the write pulse, a total of 27
clock periods plus the set-up time. At 2 MHz, this is 14.25
/AS. Although the maximum could theoretically be infinite, a
practical maximum is 35 ,..s (based on the interrupt request
occurring near the beginning of a PI and LR K, P sequence).
+
Timing Charscteristlcs
ROMC States
Timing signals are Illustrated in figures 3, 6, and 7; the
signal timing characteristics are presented in table 5.
Table 4 shows the function performed by the PIO device for
each ROMC command. Each function is performed entirely
within one machine cycle (one cycle of ~he WRITE clock).
All other ROMC states are decoded as NO-OP:
Figure 6 F3861 Input/Output TI"1jng
WRITEJ
INPUT (1)
\----~Jrf--------~j
~tsu--1
------~--~------------DATA MAY CHANGE
\-00---
DATA STABLE
\!'----I---- -----J
th
ir-----DATA MAY CHANGE
tsP--+j
OUTPUT (2)
~--------------------------(STANDARD
PULL.UP) _ _ _ _ _ _ _ _ _ _ _ _ _
~
2.9 V
STABLE
3-104
F3861
Figure 7 F3861 Interrupt Logic Timing
_______-J/
,I
I
\,
LONG CYCLE
ROMC
STABLE
t------tr2-----+j
~-------------------------+------t-Pd--4~
PAliN
tpr~
~tex
EXT
iNr
-----------------------~\
~--------------------------------
Note: Timing measurements are made at valid logic level to valid logic level of the signals references, unless otherwise noted.
3·105
II
F3861
Table 5 F3861 Timing Characteristics
The ac characteristics are VSS = OV, VCC = + 5V( ± 5%),
TA = 0 C to + 70·C.
Symbol
Parameter
Min
P
PW1
td 1
td 2
td4
PW2
PWs
PW L
td 3
Period
Pulse Width
to WRITE + Delay
to WRITE - Delay
WRITE to DB Input Delay
WRITE Pulse Width
WRITE Period; Short
WRITE Period; Long
WRITE to ROMC Delay
WRITE to DB Output Delay
WRITE to DBDR - Delay
WRITE to DBDR + Delay
WRITE to ltfl: REO - Delay
WRITE to INT REO + Delay
PRI IN to INT REO - Delay
PRIIN to INT REO + Delay
PRI IN to PRI OUT - Delay
PRI IN to PRI OUT + Delay
WRITE to PRI OUT + Delay
WRITE to PRI OUT - Delay
WRITE to Output Stable
0.5
180
60
60
I/O Setup Time
I/O Hold Time
EXT INT Setup Time
1.3
0
400
td 7
tda
tr1
tr2
tpr1
tpr2
tpd 1
tpd2
tpd 3
tpd 4
'tsp
't su
'th
*tex
Typ
P-1OO
Units
Test
Conditions
10
P-180
250
225
2P+ 1.0
P
51-'s
ns
ns
ns
I-'s
ns
550
ns
2P+850-t~
430
430
240
240
ns
ns
ns
ns
ns
ns
CL = 100 pF
Open Drain
CL = 100 pF(1)
CL = 100 pF (3)
CL = 100 pF (2)
CL = 100 pF
365
700
640
2.5
ns
ns
ns
I-'s
CL = 50 pF
CL = 50 pF
C L = 50 pF
CL =50 pF
Standard
Pull-up
t r,t f = ns typo
CL = 100 pF
= 100 pF
ct.
tro t f = 50 ns typo
4P
6P
2P + 100 - td 2
2P+ 200
200
I-'s
ns
ns
Notes:
1. Assume Priority In was enabled (PRI iN = 0) in the previous F8 cycle
before the interrupt is detected in the PIO.
2. The PSU has an interrupt pending before priority in is enabled.
3. Assume the pin is tied to the INT REQ input of the F3850 CPU.
4. The starred * parameters in the table represent those most frequently
of importance when interfacing to an F8 system. Other parameters are
typically those that are relevant between Fa chips and are not normally
of concern to the user.
5.
Max
Input and output capacitance is 3 to 5 pF typical on all pins except
VGG , and VSS'
VOO '
3-106
F3861
DC Characteristics
The dc characteristics of the F3861 PIO are supplied in
tableS.
Table 6 F3861 PIO DC Characteristics
Symbol
Parameter
Signal
Min
Max
Units
VIH
Vil
VOH
VOL
IIH
10l
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Input High Current
Input Low Current
Data Bus (DBO-DB7)
3.5
Vss
3.9
Vss
Voo
0.8
Voo
0.4
1
-1
V
V
V
V
p.A
p.A
10H
10l
VIN
VIN
VIH
Vil
Il
Input High Voltage
Input Low Voltage
Leakage Current
Clock Lines
(
Part
Number
F3861
Min
Typ
+4.75 V
+5V
Max
+ 5.25 V
Min
Typ
+11.4 V
+12 V
Max
+ 12.6 V
Vss
OV
Ordering Information
Part Number
Package
Temperature Range
F3861
F38610L
F38610M
*F3861 PC
F3861 PL
F3831 PM
Ceramic
Ceramic
Ceramic
Plastic
Plastic
Plastic
C
L
M
=
=
C
Commericial Temperature Range O· to + 70·C
L = Limited Temperature Range - 40·C to + 85·C
M
Military Temperature Range - 55·C to + 125·C
* Version A, B, C, 0, and E are stocked items.
C
L
M
3·108
F3871
Peripherallnput/Output
Microprocessor Product
Connection Diagram
Description
The Fairchild F3871 Peripheral InputlOutput (PIO) device
provides two 8-bit 110 ports, external interrupt, and a programmable timeL An 8-bit-wide bidirectional data bus transfers 110 data bytes between the F3870 Central Processing
Unit (CPU) and the PIO.
i7
DB,
liD 7fi
DB.
I/O
The PIO is used in systems that require the 110 capability
and interrupt functions of the F3851 PSU, but do not need
the read-only memory (ROM) storage of the PSU. The PIO is
pin-compatible with the PSU.
The F3871 has the same improved timer and ready strobe
output as the F3870 CPU; therefore, for software compatibility with the F3870, the F3871 PIO should be used in the F8
multichip configurations.
VGG
liD ii6
Voo
110 A;;
miNT
liD
PRIOUT"
iiOBs
WRITE
DBs
¢
DB.
I/OB.
INT REO
PiiiiN
The F3871 is manufactured using isoplanar N-channel
silicon-gate technology; therefore, power dissipation is very
low (less than 200 mW)-
• 16 Bidirectional, Individually Controlled I/O Lines
Organized as Two B-Bit Ports
.110 Strobe
• Programmable Timer - Preset, Start, Stop, and ReadBack Ability: Selectable Timer Count Rates
• Full Interrupt Level- Daisy-Chain Expandable,
Independent Interrupt Address Vectors lor Timer and
Extemal Interrupt
• Pulse Width Measurement Capability
• +5 V and +12 V Power Supplies
• 2 M Hz Operation
• TTL and LSTTL Compatible
• Low Power Dissipation, Typically Less Than 200 mW
3-109
10
iiOA:;
Diiffii
11
I/0Al
STROBE
12
1/083
ROMe,
13
DB,
ROMe,
14
DB,
ROMe,
15
liD
110 A>
ii2 .
ROMe,
16
ROMeo
17
I/O
Vss
18
liDS,
I/OAO
19
DB,
So
20
DBa
liD
II
A6
A,
"
F3871
Signal Functions
110
PORTS
STROBE
Figure 1
F3871 Block Diagram
1/0 PORTA
110 PORT B
110 PORT A
110 PORT B
DATA
BUS
DBDR
INTERRUPT
VECTOR ADDRESS
PROGRAMMABLE
TIMER
ROM
CONTROL
LINES
EXTERNAL
INTERRUPT
INTERRUPT
CONTROL
INTERRUPT
LOGIC
PRIORITY IN
PRIORITY OUT
INTERRUPT
REQUEST
VGG
VDD
GND
...
WRITE
3-110
F3871
Table 1
F3871 Signal Descriptions
Pin No.
Name
Description
8
7
Clock
The two clock input signals that originate at the
F3850 CPU.
19,24,25,
30,31,36,
37,2
20,23,26,
29,31,35,
38,1
110 Ports A
Bidirectional ports through which the PIO
communicates with logic external to the
microprocessor system.
17,16,15,
14, 13
Read·Only
Memory Control
Input signals that originate at the F3850 CPU
control internal functions of the PIO.
DBo-D~
21,22,27,
28,33,34,
39,40
Data Bus
Bidirectional 3-state lines that link the PIO to all
other devices within the microprocessor system.
DBDR
11
Data Bus Drive
A low output, open drain signal that indicates the
data bus currently contains data flowing from the
PIO.
Strobe
STROBE
12
Strobe
Provides a sin~ow~tput pulse after valid data
is present on 110 Ao-IIO A7 during an output
instruction.
Interrupt
EXTINT
5
External Interrupt
A high·to·low transition on this input signal is
interpreted as an interrupt request from an
external device.
INTREO
9
Interrupt Request
This output signal is the INT REQ input to the
F3850 CPU; it must be out))ut low to interrupt the
CPU, which occurs only if PRI IN is low and PIO
interrupt control logic is requesting an interrupt.
PRIIN
10
Priority In
Unl~input signal is low, the PIO will not set
the INT REO signal low in response to an
interrupt.
PRIOUT
6
Priority Out
This output signal becomes the PRIIN signal to
the next device in the interrupt'priority daisy
ch",in; it is output high unless the PRI IN signal is
entering the PIO low and the PIO is not requesting
an interrupt.
Voo
4
Power Supply
VGG
Vss
3
18
Power Supply
+5 V (±5%)
+12V(±5%)
Mnemonic
Clock
+
WRITE
110 Ports
110 Ao-I/O A7
110 Bo-IIO B7
Control
ROMCo-ROMC4
110 Ports B
Data Bus
Power
System ground - 0 V; Voo and VGG are referenced
to Vss.
Ground
3·111
II
F3871
DevIce Organization
F3871 PIO Port Addresses
Table 2
The peripheral input/output device Includes 1/0 logic, timer
logic, Interrupt logic, data bus logic, and control logic, as
Illustrated, ill figure 1.
'
The interrupt logic responds to an Interrupt request signal
originating from internal timer logic or an external device.
Based on priority conSiderations, the interrupt request is
passed on to the F3850 CPU._
Address
Assl nedTo
XXXXXXOO
XXXXXX01
XXXXXX10
XXXXXX11
1/0 Port A
1/0 Port B
Interrupt Control Register
Programmable Timer
The port and interrupt address vector aSSignments for the
F3871 are given in table 3.
The programmable timer uses a polynomial shift register in
conjunction with interrupt logic to generate real·time
intervals.
Table 3
F3871 Port and Address Assignments (HEX)
Interrupt
The 8-bit data bus in the PIO Is the main path for transfer of
information between the F3850 CPU and other devices in
the Fa microprocessor system. The device has four preassigned 1/0 port addresses: the lowest two are assigned to
the two 1/0 ports, A and B, and are used to transfer data to
and from external devices. The other two 1/0 addresses are
assigned to two internal registers of the PIO that control
interrupt logiC and are treated as 1/0 ports.
Version
3871E
3871F
3871G
3871H
Addresses
-Output Type
TImer
4-7
4-7
4-7
8-B
Standard
Direct Drive
Open Drain
Standard
0020
0020
0020
4420
External
ooAO
OOAO
OOAO
44AO
Port Pin Description
the CPU accumulator (ACC) to be latched into the addressed port. An input instruction (IN or INS) transfers the contents of the port to the ACC (port 6 is an exception that is
described in the "Timer and Interrupt Control Port" section).
The 110 pins on the PIO are logically inverted; the schematic
of an 110 pin and available output drive options are shown
in figure 2. Each output pin has an output latch that holds
the data last output to that pin. The 110 ports of the PIO are
configured in the standard pull-up option.
The F3871 input and output signals are described in table 1.
System Clock TIming
+
All timing within the PIO is controlled by the and WRIl:E
signals input from the F3850 CPU. (Refer to the F3850data
sheet for a description of these clock signals.) The WRITE
clock refreshes and updates PIO registers, which are
dynamiC. The clock drives sequencing logic to precharge
Interrupt logic. The clock also drives the progralTlmable
timer.
1/0
Port
'An output instruction (OUT or OUTS) causes the contents of
Signal Descriptions.
+
Address Ve<:t()f
Port
The ~ output is always configured in a manner similar to a standard output, except that it is capable of driving
three TTL loads.
+
POrtss
Each 110 port pin is a wire-AND structure between an internal output data latch and the exterhal signal. The latch is
loaded from the data bus. The output latches are not initialized by the system reset sequence.
The PIOhas two-bidirectional 8-bit 1/0 ports used to trans·
mit data between it and external devices. In binary notation,
the address for port A is XXXXXXOO and for port B is XXXX·
XX01, where the, X binary digits are the unique 110 port
select code for the PIO (see table 2). For example, if the port
select code is 000001, port A can be clliled port 4 and port B
can be called port 5. (The PIO port select code Is never
deSignated as all "O"s, since ports 0 and 1 are reserved for
the F3850 CPU.) In addition, the interrupt control port (ICP)
is addressed as port XXXXXX10 and the binary timer is
addressed as port XXXXXX11, which become ports 6 and 7,
respectively, for the port select code example just given.
When transmitting data through an 1/0 port, the pin can be
connected directly to a TTL gate input; data is input to the
pin from a TTL device output. Since the 110 pin and the TTL
device output are wire-ANDed, it is possible for the state of
one to affect the transfer of data out frOm the I/O pin or in
from the TTL device output. In 'most cases, 110 port bits
should, therefore, be set for a high level (logic 0), before
data input; to prevent Incoming logic "O"s from being
masked by logic "1"s present at the port from previous
outputs. However, the ability to mask bits of a port to logic
1 is useful during some input functions.
3-112
F3871
Rgure 2 F3871 1/0 Pin Diagram with Output Buffer Options
z0
~
TTL
a:
110
:::l
"ii:
Z
0
u
a:
...0!
PORT
PIN
..
l-
I-
0
0
Q
Q
a:
a:
.. ..
w 0
a: -'
!.
Ii
OPEN DRAIN
OUTPUT
STANDARD
OUTPUT
DIRECT DRIVE
OUTPUT
Figure 3 F3871 11mer and Interrupt Control Port Block
Diagram
PRESCALER
';-2, 5, 10, 20, 40, 100, or 200
INTER~UPT
CONTROL
PORT
(PORT XXXXXX10)
EVENT COUNTER MODE_
.;- 2 PRESCALE
_
-7 5 PRESCALE
-4-.;- 10 PRESCALE
_
.;- 20 PRESCALE
_
.;- 40 PRESCALE
_
.;- 100 PRESCALE
_
.;- 200 PRESCALE
_
4~ug3.
2~i
L~X:~TR::~
L
INTERRUPT ENABLE
TIMER INTERRUPT ENABLE
EXT INT ACTIVE LEVEL
.
START/STOP TIMER
PULSE WIDTH/INTERVAL TIMER
3-113
•
F3871
3. On the trailing edge transition of the EXT INT pin,
when In the pulse width measurement mode.
Strobe
An output ready strobe is associated with port A. This flag
is used to signal a peripheral device that the F3871 has just
completed an output of new data to port A. Since the strobe
provides a single low pulse shortly after the output operation is completed, either edge can be used to signal the
peripheral. The STROBE signal Is also used as an input
strobe by performing a dummy output of Hoo'to port A
after completing the input operation.
An OUT or OUTS Instruction to the timer loads the contents
of the accumulator (the Interval value) to both the timer and
the 8-bit modulo·N register, resets the prescaler, and clears
any previously stored timer interrupt request. The timer Is
clocked by the prescaler In the interval timer mode and in
the pulse width modulator mode; the prescaler Is not used in
the event counter mode. The modulo·N register is a buffer
that saves the value most recently output to port XXXXXX11
and is used in all three timer modes.
Timer and Interrupt Control Port
The timer is software·programmable to operate in one of
three modes: the interval timer mode, the pulse width
measurement mode, and the event counter mode. As shown
in figure 3, an 8-bit register (interrupt control port), a programmable prescaler, and an 8-bit modulo·N register are
associated with the timer.
Interval Timer Mode
When ICP bit 4 is cleared (logic 0) and at least one prescale
bit is set, the timer operates In the interval timer mode.
When bit 3 of the ICP Is set, the timer starts counting down
from the modulo-N value. After counting down to H'01~ the
timer returns to the modulo·N value at the next count. On
the transltron from H'01' to H'N~ the timer sets a timer Inter·
rupt request latch. Note that the interrupt request latch Is
set by the transition of H'N' in the timer, thus allowing a full
256 counts If the modulo·N register is preset to Hoo~
The desired timer mode, prescale value, timer start and
stop, active level of the external interrupt pin, and local
interrupt enable or disable are selected by the proper bit
configuration output from the accumulator to the interrupt
control port (port XXXXXX10),with an OUT or OUTS
instruction.
If bit 1 of the ICP is set and the PRiTN signal is low, the
interrupt request is passed to the F3850 CPU. However, if bit
1 of the ICP is a logic 0, the interrupt request is not passed
on to the CPU. If bit 1 is subsequently set, the Interrupt
request is. then passed to the CPU. Only two events reset the
timer Interrupt request latch:
1. Acknowledgement by the CPU of the timer interrupt
request.
Interrupt Control Port
A special situation exists when reading the ICP with an IN or
INS instruction. The accumulator is not loaded with the contents of the ICP; instead, accumulator bits 0 through 6 are
loaded with "O"s, while bit 7 is loaded with the logic level be·
ing applied to the EXT INT pin, thus determining the status
of the EXT INT signal without servicing an external interrupt
request. This capability Is useful in two ways: establishing a
high·speed polled handshake procedure and using the EXT
INT pin as an extra input pin if external interrupts are not
required and if the timer is used only in the interval timer
mode. However, if it Is desirable to read the contents of the
ICP, one of the 64scratchpad registers is used to save a
copy of material written to the ICP.
2. Performance of a new load operation of the modulo-N
register.
(The interrupt priority sequence is discussed in the
"Interrupt Sequence" section.)
For example, if the modulo-N register is loaded with H'64'
(decimal 100), the timer interrupt request latch is set at the
100th count following the timer start, and the timer interrupt
request latch is repeatedly set on precise 1QO.count intervals. If the prescaler Is set at + 40, the timer Interrupt
request latch is set every 4000 + clock periods. For a 2 MHz 4
clock, this setting produces 2 ms Intervals.
The timer clock rate in the interval timer mode is determined
by the frequency of the + clock and by the division value
selected for the prescaler. If ICP bit 5 is set and bits 6 and 7
are cleared, the prescaler divides + by two. If bit 6 or 7 is
individually set, the prescaler divides + by five or twenty,
respectively. Combinations of bits 5,"6; and 7 can also be
selected. For example, if bits 5 and 7 are set while 6 Is
cleared, the prescaler divides by 40. Thus, possible prescaler
values are +2, +5, +10, +20, +40, +100, and +200.
The range of possible intervals is from 2 to 51,200 + clock
periods (1 lAs to 25.6 ms for a 2 MHz ~Iock). However,
approximately 50+ clock periods I.s a practical minimum,
because the time between setting the Interrupt request latch
and the execution of the first instruction of the Interrupt
service routine Is at least 29 clock periods (the response
time is dependent on how many privileged Instructions are
encountered when the request occurs). To establish time
+
Any of three conditions causes the prescaler to reset:
1. When the timer is stopped by clearing ICP bit 3.
+
2. When an output instruction to the timer (port XXXXXX11)
Is executed.
3·114
2
F3871
+
As in the interval timer mode, the timer C!ln be read at any
time and can be stopped at any time by clearing ICP bit 3,
the prescaler, and ICP bit 1 functions as previously described. The timer still functions as an 8-bit binary down
counter with the timer interrupt request latch set on the
timer's transition from H2'01'to H'N'. Note that the EXT INT
pin is not involved with loading the timer; its action Is that
of automatically starting and stopping the timer and·of generating external Interrupts. Pulse widths longer than the prescale value times the mod.ulo-N value are easily measured
by using the timer interrupt service routine to store the number of timer interrupts in one or more scatchpad registers.
intervals greater than 51,200 clock periods, use the timer
interrupt service routine to count the number of interrupts,
saving the result in one or more of the scratchpad registers
until the desired interval is achieved. With this technique,
virtually any time interval, or several time intervals, can
be generated.
The F3871 timer can be read at any time and in any mode,
using an input instruction (IN or INS), and can take place
"on-the-fly" without interfering with nOrmal timer operation.
The timer can be stopped at any time by clearing bit 3 of the
ICP. The timer holds its current contents indefinitely and
resumes counting when bit 3 is set again. The prescaler is
reset whenever the timer is stopped; thus, a series of starting and stopping results In a cumulative truncation error.
For a free-running timer in the interval timer mode, the time
interval between any two interrupt requests can be in error
by plus or minus six clock periods, although the cumulative error over many intervals Is zero. The prescaler and timer
generate precise intervals for setting the timer interrupt
request latch, but the time-out can occur at any. time within
a machine cycle. (There are two types of machine cycles:
short cycles that consist of four clock periods and long
cycles that consist of six clock periods.) The write clock
corresponds to a machine cycle. Interrupt requests are synchronized with the write clock, thus creating the possible
plus or minus six error. Additional errors can arise if the
interrupt request occurs while a privileged instruction or
multicycle instruction is being executed. However, for most
applications, all of the above errors are negligible, espeCially
If the desired time interval is greater than one ms. Other
timer errors are summarized in the "Timing Characteristics"
section.
+
+
+
+
Pulse Width Measurement Mode
When ICP bit 4 Is set (logic 1) and at least one prescale bit
is set, the timer operates in the pulse width measurement
mode. This mode Is used to accurately measure a pulse
duration applied to the EXT INT pin. The tinier is stopped
and the prescaler is reset whenelierthe EXT INTpin is at its
inactive level. The active level of the EXT INT pin is defined
by ICP bit 2: if cleared, the EXT INT pin is active low; if set,
the EXT INT pin is active high. If ICP bit 3 Is set, the prescaler and timer start counting when the EXT INT signal
goes through a transition to the active level.
The actual pulse duration is typically slightly longer than
the measured value, because the status of the prescaler is
not readable and is reset when the timer is stopped. Thus,
for maximum accuracy, using a small division setting for
the prescaler Is advisable.
Event Counter Mode
When ICP bit 4 is cleared and all prescale bits (ICP bits 5, 6,
and 7) are cleared, the timer operates in the event counter
mode. This mode is used for counting pulses applied to the
EXT INT pin. If ICP bit 3 is set, the timer decrements on
each transition from the inactive level to .the active level of
the EXT INT pin. The prescaler is not used in this mode. As
in the other two timer modes, the timer can be read at any
time and can be stopped at any time by clearing ICP bit 3.
ICP bit 1 functions as previously described, and the timer
interrupt request latch is set on the timer's transition from
H'01' to H'N~
Normally, ICP bit 0 is kept cleared In the event counter
mode; otherwise, external interrupts are generated on the
transition from the inactive level to the active level of the
EXT INTpin.
For the event counter mode, the minimum pulse width
required on EXT INT is two clock periods, and the minimum Inactive time is two clock periods; the maximum
repetition rate Is 500 Hz.
+
+
External Interrupts
~
When the timer Is in the interval timer mode, the EXT INT
pin is available for non-tlmer-related interrupts. If ICP bit 0 is
set, an external Interrupt request latch is set when there Is a
transition from the Inactive level to the active level of the
EXT INT pin. (The EXT INT pin Is an edge-triggered input.)
The .interrupt request Is latched either until acknowledged
by the CPU or until ICP bit 0 is cleared (unlike timer Interrupt requests that remain latched even when ICP bit 1 Is
cleared).
When the EXT INT pin returns to the inactive level, the timer
stops, the prescaler resets, and, if ICP bit 0 is set, an external Interrupt request latch Is set. (Unlike timer interrupts,
external interrupts are not latched if the ICP interrupt
enable Is not set.)
3·115
3
F3871
input cycle. Only the two I/O ports Oowest two addresses)
respond to input instructions. Output instructions that
select a port transfer the contents of the data bus to that
port. Outputs of the latches change at the end of the I/O
transfer cycle.
External interrupts are handled In the same manner when
the timer Is in the pulse width measurement mode or in the
event counter mode, except that in the pulse width measurement mode only, the external Interrupt request latch is
set on the trailing edge of the EXT INT signal (I.e_, on the
transition from the active level to the inactive level)_
Interrupt Handling
Instruction execution
A typical F8 system interrupt interconnection is shown in
figure 4. Each PSU and PIO has a PRI IN and a PRI OUT line
so that they can be daisy-chained together in any order to
form a priority level of interrupts. When a PIO receives an
Interrupt (either timer or external), it pulls its PRI OUT output
Signal high, Signaling all lower priority peripherals that it
has a higher priority interrupt request pending on the CPU.
When the PIO device's PRI IN input signal is pulled high by
a higher priority peripheral, Signaling the PIO that there is a
still higher priority interrupt request pending, It passes that
Signal along by pulling its PRI OUT signal high. When the
CPU processes an interrupt request, it commands the interrupting device to place its interrupt vector address on the
data bus. Only the device with a PRIIN signal low and an
Interrupt request pending responds. Should there be another
lower priority device with a pending request, it does not
respond at that time because Its PRI IN input Signal is high.
The PIO responds to signals that are output by the F3850
CPU in the course of implementing instruction cycles_ The
PIO places data on the data bus, even In the worse case, in
time for the setup required by any F3850 CPU destination.
The PIO receives a byte input from the data bus when commanded by an output instruction to load one of its two 1/0
ports or Internal registers.
The data bus drive signal (DBDR) is low while data output
by the PIO is stable on the data bus. Thus, a DBDR low signal indicates that the data bus currently contains data flowing from a PIO. For systems with more than one program
storage unit (PSU) or PIO, the DBDR output signal can be
wire.QRed and the result used as a bus data flow direction
indicator. The DBDR signal can remain low until timing
Interval t~6~he next Instruction cycle following the one
in which
was set low.
If there' is both a timer interrupt request and an external
interrupt request when the CPU starts to process the
requests, the timer Interrupt is handled first.
The PIO device executes the OUT instruction in the same
manner as it does the OUTS instruction; the same is true
for the IN and INS instructions. The difference between the
long- and short-form instructions is found only in the source
of the I/O address.
Within each local interrupt control circuit is a 16-bit interrupt
address vector. This vector is the address to which the progr.am counter is set after an interrupt is acknowledged and
is, therefore, the address of the first executable instruction
of the interrupt routine.
The F8 inputloutput instructioris piacethe 1/0 port address
on the data bus during one instruction cycle and then use
the data bus in the following instruction cycle to do the
actual 1/0 data movement. The Read-Only Memory Control
(ROMC) lines coming from the F3850 CPU signal the PIO
that an I/O data movement is occurring during the current
instruction cycle. Therefore, the PIO needs to recognize
whether the contents of the data bus during the instruction
cycles just prior matches any of its four assigned I/O
addresses wherever the ROMC lines Indicate an I/O transfer. The address select logic constantly monitors the data
bus for a match to any of the four addresses and holds the
information of a match through the following cycle.
The interrupt address is unique to the version of the PIO
dev.ice selected by the user. Fifteen bits are fixed: bits 0
through 6 and bits 8 through 15. Bit 7 (21) is dependent
on the type of interrupt. This bit is a 0 for internal timergenerated interrupts and a 1 for external interrupts.
When the interrupt logiC sends an interrupt request signal
and the CPU is enabled to service it, the normal state sequence of the CPU is interrupted at the end of an instruction. The CPU signals the interrupt circuits through the five
ROMC lines. The requesting local interrupt circuit sends a
16-bit interrupt address vector (from the interrupt address
generator) onto the data bus in two consecutive bytes.
Input instructions that select a port cause the contents of
the selected port to be placed on the data bus during the
3·116
F3871
The CPU allows interrupts after all F8 instructions except
the following:
The address is made available to the program counter
through the address demultiplexer circuits. It is simultaneously made available to all other devices connected to the
data bus. It is the address of the next instruction to be executed. The program counter of each memory device is set
with this new address while the stack register is loaded
with the previous contents of the program counter. The
information in the program counter is lost. Thus, the next
instruction to be executed is determined by the value of
the interrupt address vector.
(PK)
(PI)
(POp)
POP
(JMp)
(OUTS)
JUMP
OUTPUT SHORT
(Excluding OUTS 00 and 01)
OUTPUT
SETICB
LOAD THE STATUS REGISTER
FROM SCRATCH PAD
(OUT)
(EI)
(LRW,J)
The interrupt control bit (ICB) of the CPU (loaded in the W
register) allows interrupts to be recognized. Clearing the ICB
prevents acknowledgement of interrupts. The ICB is cleared
during power-on and external reset, and after an interrupt is
acknowledged. The interrupt status of the PSU, PIO, or
memory interface (MI) devices is not affected by execution
of the disable interrupt (01) Instruction. At the conclusion of
most instructions, the fetch logic checks the state of the
interrupt request line. If there is an interrupt, the next
instruction fetch cycle is suspended and the system is
forced into an interrupt sequence.
PUSH K
PUSH IMMEDIATE
POWER ON
As a result, it is possible to perform one more instruction
after each of the above CPU instructions without being
interrupted.
Figure 4 Fa System Interrupt Interconnection
~_________C~O~N~TROLrL~IN_E~S________~
CPU
ICB
PSU/PIO
PSU/PIO
1
2
PRIORITY
PIO
(n)
SMI
PRIORITY
L -_______________ EXTERNAL INTERRUPT L I N E S - - - - - - - - - - - - - - - '
3-117
•
F3871
Interrupt Sequence
Figure 5 details the interrupt sequence that occurs whether
the interrupt request is from an external source through the
EXT INT pin or from the PIO device's internal timer. The
events in the sequence are labeled A through G.
encountered, a series of priviledged instructions would be
executed sequentially. One more instruction (a protected
instruction) is executed after the last priviledged instruction.
The last cycle of the protected instruction then performs
the freeze.
Event A
An interrupt request must satisfy a set-up time requirement.
If not satisfied, the INT REO signal delays going low until
the next negative edge of the write clock.
The dashed lines on the EXT INT timing in figure 5, illustrate
the last opportunity for the EXT INT signal to cause the last
cycle of a nonprotected instruction to become a freeze
cycle. The freeze cycle is a short cycle (four clock periods)
in all cases except where B is the decrement scratch pad
instruction, in which case the freeze cycle is a long cycle
(six clock periods).
+
Event B
Event B represents the instruction being executed when the
interrupt occurs. The last cycle of B is normally the instruction fetch for the next cycle. However, if B is not a privileged
instruction and the CPU interrupt control bit is set, the last
cycle becomes a freeze cycle rather than a fetch. At the end
of the freeze cycle, the interrupt request latches are inhibited from altering the interrupt daisy chain so that sufficient
time is allowed for the daisy chain to settle.
+
The INT REO signal goes low on the next negative edge of
WRITE if both the PRIIN signal is low and the appropriate
interrupt enable bit of the ICP is set.
Event C
This is a nooOperation (NO-OP) long cycle, allowing time for
the PRIIN/PRI OUT chain to settle. At a 2MHz clock rate, a
total of seven PIO, PSU, or MI devices can be daisy-chained
without the need for look-ahead logic.
+
If B is a privileged instruction, the instruction fetch is not
replaced by a freeze cycle; instead, the fetch is performed
and the next instruction is executed. Although unlikely to be
Figure 5 F3871 Interrupt Sequence
FREEZE
CYCLE
WRITE
1 1-1
1111
I - -"1 --II--l
--';'1--__
A
1
EXTINTOR
TIMER INTERRUPT
4--- i
PRIOUT
r-i<1
I •
II
1
_ _ _ _ _:.....I _ _ _ _ .J
I. . .r"_ -I-J
PRIOUTOFNEXTPIO _ _ _ _ _ _ _
3-118
F3871
Summary of Intenupt Sequence
For the PIO, the interrupt response time is defined as the
time elapsed between the occurrence of the EXT INT signal
going active (or the timer transition to H'N? and the beginning of execution of the first instruction of the interrupt
service routine. The interrupt response time is a variable
dependent on what the microprocessor is doing when the
interrupt request occurs.
Event 0
In PSU circuits, the program counter (PO) is pushed to the
stack register (P) to save the return address. The interrupting
PIO places the lower eight bits of the interrupt vector
address onto the data bus. This is always a long cycle.
Event E
In this long cycle, the PIO places the upper eight bits of the
interrupt vector address onto the data bus.
As shown in figure 5, the minimum interrupt response time
is three long cycles plus two short cycles plus one WRITE
clock pulse width plus a setup time of an EXT INT signal
before the leading edge of the WRITE pulse-a total of 27
clock periods plus the setup time. At 2 MHz, this is 14.25 f.ls.
Although the maximum could theoretically be infinite, a
practical maximum is 35 f.ls (based on the interrupt request
occurring near the beginning of a PI and LR K, P sequence).
Event F
In this short cycle, the PIO interrupting interrupt request
latch is cleared. Also, the CPU interrupt control bit is
cleared, thus disabling interrupts until an EXT INT Instruction is performed. Additionally, during Event F, the PRI
IN/PRI OUT daisy-chaln freeze is removed, since the interrupt vector address has been passed to the CPU. Another
action is the fetch of the instruction from the interrupt
address.
ROMCStates
Table 4 shows the function performed by the PIO device for
each ROMC command. Each function is performed entirely
within one machine cycle (one cycle of the write clock). All
other ROMC states are decoded as NO-oP.
Event G
This event starts executing the first instruction of the
interrupt service routine.
Table 4
•
+
PIO Functions Versus ROMC States
ROMC State
PIO Functions
Binary
Hex
01000
08
Reset command. Load port A, port B, timer, and interrupt control port with H'OO'.
01111
OF
If this circuit is interrupting and is highest in the priority chain, move lower half of
interrupt vector into the data bus.
10000
10
Place interrupt circuitry in an inhibit state that prevents altering the interrupt priority
chain.
10011
13
If this circuit is interrupting and is highest in the priority chain, move upper half of
interrupt vector into the data bus and reset the interrupt circuit.
11010
1A
If the contents of the data bus in the prior cycle was an address of 110 ports on this
d.evice, move the current contents of the data bus into the appropriate port (110 A, 110 B,
timer, or control).
11011
1B
If the contents of the data bus in the prior cycle was an address of 110 ports on this
device, move the contents of the appropriate 110 port onto the data bus (110 A or 110 B).
3·119
F3871
Timing Characteristics
Load timer to read timer error
(Notes 1,2) ....................... -5t+ to -(Ipse +18t+)
Load timer to interrupt request error
(Notes 1,3) .................•............ -2t+to -9t+
Timing signals are illustrated in figures 6 through 10, and
the signal characteristics are presented in tables 5 through
9. Definitions for the timing characteristics are as follows:
Pulse Width Measurement Mode
Measurement accuracy (Note 4). . . . . . .. +t+ to - (tpsc + 2t+)
Minimum pulse width of EXT INipln .................. 2t+
Error = Indicated Time Value - Actual Time Value
tpse = t+ x Prescale Value
Event Counter Mode
Minimum active time of the EXT INT pin ............... 2 t+
Minimum Inactive time of the EXT INT pin ............. 2t+
Interval Timer Mode
Single interval error, free running (Note 3) ............ ±6t+
Cumulative interval error, free running (Note 3) ........... 0
Error between two timer reads (Note 2) .......... ±(tpse + t+)
Start timer to slop timer error
(Notes 1,4). . . . . . . . . . . . . . . . . . . . . . . . .. + t+ to -(t pse + t+)
Start timer to read timer error
(Notes 1,2) ........................ -5t+to -(t pse + 71+)
Slart timer to Interrupt request error
(Notes1,3) ............................. -2t+to -8t+
Load timer 10 stop timer error (Note 1) .... +t+ to -(t pse +2t+)
NOTES
1. All times that entail
loading, starting, or stopping the timer are referenced
from the end of the last machine cycle of the OUT or OUTS Instruction.
2. All times that entail reading the timer are referenced from the end of the
3.
4.
last machine cycle of the IN or INS Instruction.
All times that entail the generation of an Interrupt request are referenced
from the start of the machine cycle In which the appropriate Interrupt
request latch is set. Additional time elapses if the Interrupt request occurs
during a privileged or multlcycle instruction.
Error can be cumulative if operation is repetitively performed.
Agure 6 F3871 Clock Timing
CLOCK TIMING
-J-~-f-~1~----,Ir--~
WRITE
-..J
"i'~- ~ }i
-----J
I..
.
PWl
I..
PW'------_-
TIMING
ALL TIMING SPECIFIED AT Vss = 0 V, Voo = + 5 V ± 5%, Voo = + 12 V ± 5%
3-120
\.r
l
F3871
Figure 7 F3871 Strobe TIming
WRITE
-1~-I/0r-
II
__---J~,...i- -
1/0 PORT OUTPUT
----,.1,1-:-
-ISL---V--
STROBE (PORT A ONLYI
Figure 8 F3871 Input TIming
WRITEJ\
-.!
tSA2
r-
--iIHRlj-
X
ROMe
ISD4-
DATA BUS
181102_
IHlPORT8
~tHD3
-------- I
-------..... _r-....
t_____
=======x
3-121
IHU02
x:=.
F3871
Figure 9 F3871 Output TIming
)
OUTPUT TIMING
WRffE
_
/'
\~--:-----;-I~/
J
------b:I.:.-:
1~-10:,~----~-- ,.-_~ ____ _
y
C
D8DR _ _ _ _ _ _ _ _ _
,/
\L ________ .I
...
\. ___ _
.. 11--I.D2~ I-IoHD'
~
VAUD
)()-----~(\,._ _ __
IdDR.,
DATA
\~____
tct03
..
I
Figure 10 F3871 Interrupt TIming
INTERRUPT TIMING
/
WRITE
1+-"'£11
ACTIVE LOW
EXT INT
ACTIVE HIGH
'---_____XI ===
~I~I\I
-
.
PRIO~
II
_IdPO'_1
v. ---1IdPO,
~r-------~u-----~--~\
_~__- - - - - - - II
"
PRI O~ OF NEXT PIO IN CHAIN
(PAl iN TO Piil
DELAY)
':-_
IdPO'~
/
8tl¥
?
-I
1~'R2
,
3-122
-./
II
1d~021-
\L
F3871
Table 5
F3871 Clock Timing Characteristics
Symbol
Parameter
Min.
Typ,
P+
Clock Period
0.5
Po
P1
Low time
180
High time
180
PW
WRITE Clock Period
4P+
PWo
PW1
WRITE Clock Period
6P+
t dw1
tdwO
Table 6
F3871 Strobe Timing Characteristics
Symbol
Parameter
tIlO-S
WRITE Pulse Width
Max.
Units
10
,..5
Conditions
ns
ns
Short cycle
Long cycle
P+-100
+ - to WRITE + delay
P+
250
ns
+ - to WRITE - delay
225
ns
Min.
Max.
Units
Port Output to STROBE delay
3t+-1000
3t++250
ns
tSL
STROBE Pulse Width, Low
8t+ -250
12t++250
ns
tw-IIO
WRITE to I/O Port Output Valid
1000
ns
Comments
Note 1
Note 2
NOTES
1. Load is 50 pF plus 3 standard TTL inputs.
2. Load is 50 pF plus 1 standard TTL input.
Table 7F3871 Input Timing Characteristics
Symbol
Parameter
tSR2
ROMC Valid Measured from Fall of WRITE
tHR1
ROMC Required HOld After Fall of WRITE
tSD4
Data Bus Setup Time
Min.
20
Typ.
Max.
Units
550
ns
ns
ns
tHD3
Data Input Hold Time
20
ns
tSl/02
I/O Input Setup Time
1.3
ns
t HI/02
I/O Input Hold Time
20
ns
3-123
Conditions
II
F3871
Table 8
F3871 Output Timing Characteristics
Symbol
Parameter
tlDRl
WRITE to DBDR Floating
tdDRl
+to DBDR 1-0
tdDR2
WRITE to DBDR 1-0
Min.
Typ.
200
Max.
Units
400
ns
Conditions
625
ns
CL = 100 pF; RL = 12.5 kQ
2PH
625tdwO
ns
CL =1oo pF; RL=12.5 kQ
ns
CL =1oo pF
2P++
700tdwO
ns
CL =1oopF
tdD3
WRITE to Data Valid
tOHD2
Guaranteed Data Hold Time After
Fall of WRITE
Table 9
F3871 Interrupt Timing Characteristics
Symbol
Parameter
Min.
tSEll
EXT INT Setup Time
750
tHEI
EXT INT Hold Time
30
tdlR2
WRITE to INT REO Delay
430
ns
CL =1OO"pF
tPOl
WRITE to PRI OUT Delay
640
ns
CL =50pF
tdP02
PRIIN to PRI OUT Delay
350
ns
CL =50 pF
tliRl
WRITE to INT REO Float by PIO
640
ns
Open Drain Output
Max.
VDD
0.8
VDD
Units
V
V
V
V
V
,..A
",.A
pF
2P+tdWO
2P+400
ns
30
Typ.
!
Max.
Units
Conditions
ns
ns
",
DC Characteristics
The DC characteristics of the F3871 PIO are supplied in table 10.
Table 10
Symbol
V1H
V1L
VOH
VOH
VOL
IIH
IOL
C1
F3871 DC Characteristics
Parameter
Input High Voltage
Input Low Voltage
Output High Voltage
Output High Voltage
Output Low Voltage
Input High Current
Input Low Current
Input Capacitance
Signal
,
Min.
2.0
Vss
3.9
2.4
Data Bus (DBo -DBr)
0.4
1.0
-1.0
10
3·124
Test Conditions
IOH = -1oo,..A
IOH =1oo,..A, VGG=5V±5%
IOL=1.6mA
V1N = 6 V, 3-state mode
V1N = Vss, 3-state mode
3-state mode
F3871
Table 10
F3871 DC Characteristics
Symbol
VIH
VIL
IL
CI
VIH
VIL
IL
CI
VOH
VOL
VOH
VOL
IL
CI
VOH
VOL
IL
CI
VIH
VIL
IIH
IlL
CI
VOH
VOL
VOH
VOL
VIH
VIL
IlL
CI
VOH
VOL
VIH
VIL
IL
CI
VOH
VOL
10H
Parameter
Input High Voltage
Input Low Voltage
Leakage Current
Input Capacitance
Signal
Clock Lines
Input High Voltage
Input Low Voltage
Leakage Current
Input Capacitance
Priority In and Control
Lines (PRI IN, ROMCo ROMC4)
3.5
Vcc
Output High Voltage
Output Low Voltage
Priority out (PRI OUT)
Output High Voltage
Output Low Voltage
Leakage Current
Input Capacitance
Interrupt Request
(lNT REO)
Output High Voltage
Output Low Voltage
Leakage Current
Input Capacitance
Data Bus Drive (DBDR)
Input
Input
Input
Input
Input
External Interrupt
(EXT INT)
High Voltage
Low Voltage
High Current
Low Current
Capacitance
(+, WRITE)
Min.
Max.
Units
2.0
Vcc
Voo
0.8
±1.0
10
V
V
~
pF
Voo
0.8
1.0
10
V
V
~
pF
3.9
Vss
Voo
0.4
V
V
Vss
0.4
1.0
10
V
V
~
pF
Open Drain Output'
10L =0.8 rnA
VIN = 6 V. Output Device Off
Output Device Off
Vss
0.4
1.0
10
V
,..A
pF
External Pull·up
IOL=1.8rnA
VIN = 6 V. Output Device Off
Output Device Off
2.0
10
V
V
,..A
~
pF
Voo
0.4
V
V
Voo
0.4
Voo
0.8
1.0
10
V
V
V
V
rnA
pF
0.4
6.0
0.8
1.0
10
V
V
V
~
pF
Voo
0.4
-9.0
V
V
rnA
0.8
-1.6
100
Output High Voltage
Output Low Voltage
Strobe (STROBE)
Output High Voltage
Output Low Voltage
Input High Voltage
Input Low Voltage
Input Low Current
Input Capacitance
I/O Port Option A
(Standard Pull·up)
Output High Voltage
Output Low Voltage
Input High Voltage
Input Low Voltage
Leakage Current
Input CapaCitance
I/O Port Option B
(Open Drain)
Output High Voltage
Output Low Voltage
Output High Current
I/O Port Option C
(Driver Pu lI·up)
2.4
Vss
2.4
Vss
2.0
Vss
Vss
2.0
Vss
1.5
Vss
-1.5
NOTES
1. Pull·up resistor to Voo on CPU.
2. Measured with a high·level I/O port output.
3. Positive current is defined as ccnventlonal current flowing into the pin referenced.
4. Vss=O V. Voo= +5 V ±5%. VGG= +12 V ±5%. TA=O'C to +70'C unless otherwise noted.
3·125
~
Test Conditions
VIN = Vss to +6 V
VIN =Vss to +6 V
10H= -1M~
10L= -1.8 rnA
External Pull·ups Exist
Internal
VIN =0.4 V
VIN =2.4 V
10H= -300~
IOL=5.0rnA
10H = -100,..A
10L =1.8 rnA
Internal Pull'up to Voo
VIN =O.4 V2
External Pull·up
IOL=1.8rnA
VIN = 6 V. Output Device Off
10H= -1.5 rnA
IOL=1.8rnA
VOH =0.7 V to 1.5 V
•
F3871
The supply currents are given in table 11.
Table 11
Supply Currents
Min.
Symbol
Parameter
Typ.
Max.
Units
100
Voo Current
30
70
mA
f
IGG
VGG Current
10
18
mA
f = 2 MHz, Outputs Unloaded
These are stress ratings only, and functional operation at
these ratings, or under any conditions above those indicated in this data sheet, is not implied. Exposure to the
absolute maximum rating conditions for extended periods
of time may affect device reliability, and exposure to
stresses greater than those listed may cause permanent
damage to the device.
Part Number
+15V, -0.3V
+7V, -0.3V
- 600 lolA, + 225 lolA
+7V, -0.3V
-55·C, +150·C
O·C, +70·C
VGG
Voo
External Interrupt Input
All Other Inputs and Outputs
Storage Temperature
Operating Temperature
Voo
Supply
Voltage
VGG
Vss
Typ.
Max.
+4.75 V
+SV
+5.25 V
+11.4 V
+12V
F3871 DC
Ceramic
Ceramic
C
L
F3871DM
Ceramic
M
'F3871PC
Plastic
F3871PL
Plastic
C
L
F3871 PM
Plastic
M
·Versions E, F, ,G, and H are stocked items.
The recommended operating ranges of the PIO devices are
shown below.
+12.6 V
OV
3-126
Temperature
Range
F3871DL
=
Recommended Operating Ranges
Min.
Package
C
Commercial Temperature Range 0' to +70'C
L = Limited Temperature Range -40'C to +85'C
M = Military Temperature Range -55'C to +125'C
NOTE: All voltages are with respect to Vss.
Parameter
=2 MHz, Outputs Unloaded
Ordering Information
Absolute Maximum Ratings
Symbol
Conditions
CD
1
IINTPlOI!)UCTION
r;;-l2 IOPlDERING AND PACKAGE
1. ~ .INFOPIMATION
IwIF8 MICROCOMPUTER FAMILY
4
CONTROLLER FAMILY
1[!]IF880EI MICROPPIOCUSOR FAMILY
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L!J IMICROPROCESSOR
FAMILY
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TRA~ING CEN~ERSI
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'';1''
Section 4
Controller Family
F387X Family
, function (see figure 4-2), allowing semi-custom design of
microcomputers for specific market applications.
The Fairchild F387X family of devices represents a line of
complete, 8-bit microcomputers on single MOS integrated
circuits (see figure 4-1)_ Fabricated using Fairchild doublelon-Implanted, N-channel silicon-gate technology and advanced circuit design techniques, the F387X family offers
maximum cost-effectiveness in a variety of logic
replacement and control applications.
Figure 4-2 F38701 Functional Diagram
•
Figure 4-1 F387X Family Organization
F3870 SINGLE·CHIP MICROCOMPUTER
F3870AIF3870B HIGH·SPEED SINGLE·CHIP MICROCOMPUTER
F38C70 SINGLE·CHIP M'ICROCOMPUTER
AID
DIA
C
F38E70 SINGLE·CHIP MICROCOMPUTER
o
N
F38721F38L72 SINGLE·CHIP MICROCOMPUTER
V
E
R
T
E
R
All F387X family microcomputers execute the Fa instruction set of more than 70 commands. They are available with
a wide range of memory types and sizes, allowing the
designer to select the best combination of RAM and ROM
for a particular application. The F387X devices are also
available with special types of 1/0.
DIGITAL
110
The F387X family devices are all pin-compatible, permitting
easy system upgrading by replacement of one device in an
application with another family member having greater
quantities of RAM or ROM, special 1/0 functions, or all
three. Because of this simple upgrading, an F387X-based
microcomputer can be enhanced or expanded in many different ways without affecting system printed circuit board,
enclosure, or power supply requirements.
ADVANCED CONTROLLER
APPLICATIONS
The first single-chip microcomputer designed using the
modular concept Is the F38701, in which a core CPU, RAM,
ROM, analog Interface unit, power control unit, and digital
110 module are all integrated on the device_ As the library of
modules grows, the customer will be able to specify the
types of modules needed in a particular microcomputer.
The Fairchild F387X single-chip microcomputer family is
recognized as an industry standard in logic replacement
and control. The devices have been designed into, and successfully used in, a wide range of applications requiring
intelligent control.
A series of design modules, the F387XX series, Is used to
emulate the functions desired in a final Single-chip device.'
The F387XX devices currently defined are:
F3870X Family
F38700
F38752
F38753
F38754
F38755
The F3870X family is a new generation of single-chip controllers that uses a modular approach to microcomputer
design. This approach depends upon a core F387X-type
CPU and modular 110 features designed as a single-chip
4-3
CPU
Analog Interface Unit (AIU)
Power Control Unit (PCU)
Digital 1/0 Module (010)
Serial 1/0 Module (SIO)
Controller Family
Part Numbers
Descriptions
Because of the on·going growth of the F387X family, a new
numbering system for these devices has been developed
by Fairchild:
Following is data that describes the members of the F387X
and F3870X single-chip microcomputer families.
F38
Technology/Option _ _ _ _ _ _ _ _ _ _......
T
F3870X Emulation Devices
Omit
C
E
L
7X
= NMOS
=
=
=
CMOS
EPROM
Low·power stand·by option
(F3872 only)
F38700
CENTRAL
PROCESSING UNIT
Speed G r a d e - - - - - - - - - - - - - -.....
Omit = Standard
= 1.33 us cycle time
A
B
= 1 us cycle time
ROM size - - - - - - - - - - - - - - - -......
1
1024 bytes
2
2048 bytes
3
3072 bytes
4
4032 or 4096 bytes
F38754
PERIPHERAL
INPUT/OUTPUT
=
=
=
Many users are familiar with the previous F387X device
numbering system. To assist them, a cross·reference guide
is provided in table 4·1.
Table 4·1 F387X Number Cross·Reference Guide
Old Number
New Number
F3870-1K
F3870
F3870·1
F3870-2
F3872-3K
F3872
F3872 with Power·Down Option
F3872-3
F3872-4
F38L72-4
F3876-1K
F3876
F3876 with Power-Down Option
F3872-1
F3872-2
F38L72·1
F3878-3K
F3878
F38E70
F38C70
F38701
F3870-3
F3870-4
F38E70-2
F38C70-2
F38701-2
F38753
POWER CONTROL
UNIT
F38752
ANALOG
INTERFACE UNIT
4-4
F3870
Single-Chip Microcomputer
Microprocessor Product
Description
Connection Diagram
The Fairchild single-chip microcomputer series offers a
variety of circuits to serve the high-volume, cost-sensitive
controller market. The F3870 is a complete 8-bit
microcomputer on a single MOS integrated circuit. The
F3870 can execute the F8 instruction set of more than 70
commands, allowing expansion into multi-chip
configurations with software compatibility. The device
features 64 bytes of scratchpad RAM, a programmable
binary timer, 32 bits of 110, a single +5 V power supply
requirement, and a choice of 1K, 2K, 3K, or 4K of ROM.
40-Pin DIP
XTL,
VDD
XTL2
RESET
EXT tNT
POo
POl
po-,
po,
STROBE
1'40
Poi 1
Utilizing Fairchild's double-ion-implanted, N-channel
silicon-gate technology and advanced circuit design
techniques, the single-chip F3870 offers maximum cost
effectiveness in a wide range of control and logic
replacement applications.
P42
1'43
P44
1'45
P46
•
•
•
•
•
•
•
•
•
•
P47
Single-Chip Microcomputer
Software-Compatible with F8 Family
1024-, 2048-, 3072-, or 4096-Byte Programmable ROM
64-Byte Scratchpad RAM
32-Bit (4-Port) TTL-Compatible 1/0
Programmable Binary Timer:
Interval Timer Mode
Pulse Width Measurement Mode
Event Counter Mode
External Interrupt
Crystal, LC, RC, or External Time Base
Low Power (275 mW, Typical)
Single +5 V:t 10% Power Supply
po,
PO,
P05
PO,
vss
(Top View)
Signal Functions
The functions of the F3870 inputs and outputs are
described in Table 1.
4-5
F3870
Signal Functions
CLOCK { XTL,
DEVICE (
CONTROL
Device Organization
This section describes the basic functiQnal elements of
the F3870 shown in Figures 1 and 2.
P40
XTL2
P41
EXTINT
P42
P43
RESET
P44
TEST
pas
Main Control Logic
1/0 PORT 4
The instruction register (IR) receives the operation code
(op code) of the instruction to be executed from the
program ROM via the data bus. During all op code
fetches, eight bits are latched into the IR.Some
instructions are completely specified by the upper four
bits of .the op code; in such instructions, the lower four
bits are an immediate register address or an immediate
4-bit operand. Once latched into the IR, the main control
log.ic decodes the instruction and provides the necessary
control gating signals to all circ.uit elements.
P46
po"
I
1/0 PORTO
PO,
PO,
PO,
PO,
POs
Ps;,
P51
P52
PS,
po"
PS,
P07
PS,
Pio
Pi,
Pi,
1/0 PORT 1
Pa7
P13
Pi4
Pis
Pi.
Pi,
1/0 PORT 5
P56
PS,
ROM Address Registers
There are four 12-bit registers associated with the
program ROM of the F3870. (In the F3870-1, -2, and -3, thE
12-bit registers can address more memory space than is
physically available on the chip; user caution is advised.
Older versions of the F387D-1 and -2, predating date code
8213, may have 11-bit registers; contact Fairchild if you
have any questions.) These are the program counter (PO),
the stack register (P), the data counter (DC), and the
auxiliary data counter (DC1). The program counter is
used to address instructions or immediate operands. The
stack register is used to save the contents of PO during
an interrupt or ·subroutine call. Thus, P contains the
return address at which processing.is to resume upon
completion of the subroutine or the interrupt routine.
VDD
vSS
The data counter is used to address data tables. This
register is autoincrementing. Of the two data counters,
only DC can access the ROM. However, the XDC
instruction allows DC and DC1 to be exchanged.
Associated with the F3870 address registers is a 12-bit
adderlincrementer. This logic element is used to
increment PO or DC when required and is also used to
add displacements to PO on relative branches or to add
the data bus contents to DC in the add data counter
(ADC) instruction.
Program ROM
The microcomputer program and data constants are
stored in the program ROM, which may be 1024 x 8
(F3870-1), 2048 x 8 (F3870-2), 3072 x 8 (F3870-3),
or 4096 x 8 (F3870-4) bytes. When a ROM access is
required, the appropriate address register (PO or DC) is
gated onto the ROM address bus and the ROM output is
gated onto the main data bus. The first byte in the ROM
is location zero.
4-6
F3870
Table 1
Signal Functions
Mnemonic
Device Control
EXTINT
Pin No.
Name
Description
38
External
Interrupt
Software·programmable input that is also used in conjunction with the
timer for pulse width measurement and event counting.
RESET
39
External
Reset
Input that may be used to externally reset the F3870. When pulled low,
the F3870 resets; when then allowed to go high, the F3870 begins
program execution at program location H'OOOO'.
TEST
21
Test Line
An input used only in testing the F3870. For normal circuit operation,
TEST is left unconnected or grounded.
7
Ready
Strobe
Normally high output that provides a single low pulse after valid data is
present on the P4 o-P4? pins during an output instruction.
1, 2
Time Base
Inputs to which a crystal (1 MHz to 4 MHz), LC network, RC network, or
external single·phase clock may be connected.
3-6, 8-19,
22-37
1/0 Ports
Thirty·two bidirectional lines that can be individually used as either
TTL·compatible inputs or latched outputs.
Power
Voo
40
Power
Input
+5 V ± 10% power supply
Vss
20
Ground
Signal and power ground
Clock
STROBE
XTL"
XTL2
I/O Ports
POO-PO?
P1 o-P1?
P4 o-P4?
P5s-P5?
Fig. 1
Scratchpad and ISAR
The scratch pad provides 64 8·bit registers that may be
used as general·purpose RAM. The indirect scratchpad
address register (ISAR) is a 6·bit register used to address
the 64 registers. All 64 registers may be accessed using
the ISAR. In addition, the lower order 12 registers may
also be directly addressed.
F3870 Architecture
The ISAR can be visualized as holding two octal digits.
This division of the ISAR is important, since a number of
instructions increment or decrement only the least
significant three bits of the ISAR when referencing
scratchpad bytes via the ISAR. This makes it easy to
reference a buffer consisting of contiguous scratchpad
bytes. For example, when the low·order octal digit is
incremented or decremented, the ISAR is incremented
from octal 27 to 20 or is decremented from octal
20 to 27. This feature of the ISAR is very useful in
many program sequences. All six bits of the ISAR
may be loaded at one time, or either half may be
loaded independently.
ACCUMULATOR
TEST 1
PROGRAM
COUNTER
STACK REGISTER
DATA COUNTER 0
DATA COUNTER 1
EXTINT
2048x 8
EPROM
Vee
GND
4·7
•
F3170
Fig. 2
F3870 Block Diagram
II PORT 6
INTERRUPT
CONTROL
REGISTER
ROM
ADDRESS
PROGRAM
REGISTERS
ROM
po, P, DC, DC'
L-;:::===~...--....
POo-3
_ _ i'Oi-4
INDIRECT
--ffi-5
L-----'\I SCRATCHPAD 1----"'1 SCRATCHPAD
ADDRESS
110 PORT 0
REGISTERS
.......-...... P03-6
..---.. P04-19
_ _ 1iOs-.8
......--... 1506-17
REGISTER
............ P07-16
====! :=:~:~~
, 110 PORT.
&
STATUS
:=:~:~:
. - - . 1514-22
--1'f5-23
--1'f6-24
-1'i7-25
_ _ i'40-8
ALU
====! .-.-...1'iIi-9
110 PORT 4
_ _ ffi-.o
_ _ ffi-l1
_ _ ffi-.2
~P45-13
_1'46-.4
_J!47-.5
:::=:E=~--:--7
+
-S1'IiOR
PSO-33
_l'5i-32
~P52-31
110 PORT 5
...--..... P53-30
_
ii54-29
~:~;
L-___..... :::::
-
P57-28
operations (using the data presented on the two Input
buses). and provides the result on the .result bus. The
arithmetic operations that can be performed in the ALU
are binary add, decimal adjust, add with carry,
decrement, and increment. The logic operations that can
be performed are AND, OR, exclusive·OR, ones
complement, shift right, and shift left. Besides providing
the result on the result bus, the ALU also provides four
signals presenting the status of the result. These
Signals, stored in the status register (W), represent the
CARRY, OVERFLOW, SIGN, and ZERO conditions of the
result of the operation,
Scratchpad registers 9 through 15 (decimal) are given
mnemonic names (J, H, K, and 0) because of special
linkages between these registers and other registers,
such as the stack register. These special linkages
facilitate the implementation of multi·level interrupts and
subroutine nesting. For example, the instruction LR K, P
stores the lower eight bits of the stack register in
register 13 (Klower, orKL) and stores the upper four bits
of P in register 12 (K upper, or KU).
Arithmetic and Logic Unit (ALU)
After receiving commands from the main control logic,
the ALU performs the required arithmetic or logic
4-8
F3870
An output ready strobe is associated with port 4. This
flag may be used to signal a peripheral device that the
F3870 has just completed a single low pulse shortly after
the output operation is completely finished, so either
edge may be used to signal the peripheral. This STROBE
signal may also be used to request new input
information from a peripheral simply by doing a dummy
output of H '00' to port 4 after completing the
input operation.
Accumulator
The accumulator (ACC) is the principal register for data
manipulation within the F3870. The ACC serves as one
input to the ALU for arithmetic or logical operation. The
results of ALU operations are stored in the ACC.
Status Register
The status register (also referred to as the W register)
holds five status flags, as follows:
Timer and Interrupt Control Port
The timer is an 8-bit binary down counter that is
software-programmable to operate in one of three
modes: the interval timer mode, the pulse width
measurement mode, or the event counter mode; the timer
characteristics are described in Table 2. As shown in
Figure 4, associated with the timer is an 8-bit register
called the interrupt control port, a programmable
prescaler, and an 8-bit modulo-N register; a functional
logic diagram is shown in Figure 5.
STATUS REGISTER (W)
SIGN
CARRY
' - - - - - - ZERO
' - - - - - - - - OVERFLOW
' - - - - - - - - - I N T E R R U P T CONTROL BIT
The desired timer mode, prescale value, starting and
stopping the timer, active level of the EXT INT pin, and
local enabling or disabling of interrupts are selected by
outputting the proper bit configuration from the
accumulator to the ICP (port 6) with an OUT or OUTS
instruction. Bits within the ICP are defined as follows:
Summary of Status Bit
OVERFLOW
ZERO
CARRY 7 (±) CARRY 6
ALU 7 /\ ALU 6 /\ ALU s /\ ALU4
ALU3 /\ ALU 2 /\ ALU, /\ ALUo
CARRY
Interrupt Control Port (Port 6)
SIGN
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
The interrupt control bit (ICB) of the status register may
be used to allow or disallow interrupts in the F3870. This
bit is not the same as the two interrupt enable bits in the
interrupt control port (ICP). If the ICB is set and the
F3870 interrupt logic communicates an interrupt request
to the CPU section, the interrupt is acknowledged and
processed upon completion of the first non-privileged
instruction. If the ICB is cleared, an interrupt request is
not acknowledged or processed until the ICB is set.
0- External Interrupt Enable
1-Timer Interrupt Enable
2-EXT INTActive Level
3-Start/Stop Timer
4- Pulse Widthllnterval Timer
5- -;- 2 Timer Prescale Values
6- -;- 5 Timer Prescale Values
7 - -;- 20 Timer Prescale Values
A special situation exists when reading the ICP with an
IN or INS instruction. The accumulator is not loaded with
the contents of the ICP; instead, accumulator bits 0
through 6 are loaded with zeros, while bit 7 is loaded
with the logic level being applied to the EXT INT pin,
thus allowing the status of the EXT INT pin to be
determined without the necessity of servicing an external
interrupt request. This capability is useful in establishing
a high-speed, polled handshake procedure or for using
EXT INT as an extra input pin if external interrupts are
not required and the timer is used only in the interval
timer mode.
1/0 Ports
The F3870 provides four complete bidirectional 110 ports;
these are ports 0, 1, 4, and 5. In addition, the interrupt
control register is addressed as port 6 and the binary
timer is addressed as port 7. An output instruction (OUT
or OUTS) causes the contents of the ACC to be latched
into the addressed port. An input instruction (IN or INS)
transfers the contents of the port to the ACC (port 6 is
an exception that is described later). The 1/0 pins on the
F3870 are logically inverted. The schematic of an 1/0 pin
and conceptual illustrations of available output drive
options are shown in Figure 3.
.=
4-9
4
F3870
Fig. 3
1/0 Port Diagram
VDD
PORT
I/O
PIN
STANDARD
OUTPUT
OPEN DRAIN
OUTPUT
DIRECT DRIVE
OUTPUT
Ports 0 and 1 are standard output type only.
Ports 4 and 5 may be any of the three output options, each pin individually assignable to any port.
The STROBE output is always configured similar to a standard output, except that it is capable of driving three TIL loads.
Fig.4
Timer and Interrupt Control Port Block Diagram
PRESCALER
EXTERNAL
TIME
BASE
-0-2, 5, 10, 20, 40, 100, or 200
EVENT COUNTER MODE
+ 2 PRESCALE
+ 5 PRESCALE
+10 PRESCALE
+ 20 PRESCAlE
+ 40 PRESCALE
+ 100 PRESCALE
+ 20Il PRESCA.LE
INT
REO
8 BITS
INTERRUPT
CONTROL
PORT
(PORT 6)
4.,-
_
_
_
_
_
-
o
1
o
1
o
1
o
4~..
2Ll~
L-.Ex:~TR::.~
L
ug3
INTERRUPT ENABLE
TIMER INTERRUPT ENABLE
EXT INT ACTIVE LEVEL
START/STOP TIMER
1
PULSE WIDTH/INTERVAL TIMER
4·10
EXT
INT
Fig. 5
Timer/lnterrupt Functional Diagram
FROM INTERRUPT CONTROL PORT
82 I 84
83
85
8.
87
'INS T
80 I 81
~
TIMER
INTERRUPT
TIME
BASE
"LOADS INTERRUPT
VECTOR H '020' UPON
COMPLETION OF THE
FIRST NON* PRIVILEGED
INSTRUCTION
!
ACKNOWLEDGE
TIMER
~
INTERRUPT
'OUTS 7'
'I'
=
"......
PULSE WIDTH MODE
Co)
011
o
....I""L
EXTERNAL
INTERRUPT
INPUT
JL
'01'
ACKNOWLEDGE
EXTERNAL
INTERRUPT
II
F3870
Table 2
Timer Characteristics
Characteristic
Value
Interval Timer Mode
Single Interval Error, Free·Running (Note 3)
± 6t
Cumulative Interval Error, Free·Running (Note 3)
Error Between Two
Tim~r
Reads (Note 2)
0
± (tpsc + t to - (tpsc + t to - (tpsc + 7t
to - 8t
+ t¢ to - (t psc + 2t to - (tpsc + 8t to - 9t
Pulse Width Measurement Mode
Measurement Accuracy (Note 4)
+ t to - (tpsc + 2t
Event Counter Mode
Minimum Active Time of EXT INT Pin
2t
Minimum Inactive Time of EXT INT Pin
2t¢
Oellnltlons
Error = indicated time value - actual time value
tpsc = t x prescale value
Notes
1. All times that entail loading, starting, or stopping the timer are referenced from the end of the last machine cycle of the OUT or OUTS instruction.
2. All times that entail reading the timer are referenced from the end of the last machine cycle of the IN or INS instruction.
3. All times that entail the generation of an interrupt request are referenced from the start of the machine cycle in which the appropriate interrupt request
latch is set. Additional time may elapse if the interrupt request occurs during a privileged or multi·cycle instruction.
4. Error may be cumulative if operation is repetitively performed.
The rate at which the timer is clocked in the interval
timer mode is determined by the frequency of an internal
¢ clock and by the division value selected for the
prescaler. (The internal clock operates at one·half the
external time base frequency.) If ICP bit 5 is set and bits
6 and 7 are cleared, the prescaler divides by 2.
Likewise, if bit 6 or 7 is individually set, the prescaler
divides ¢ by 5 or 20, respectively. Combinations of bits 5,
6, and 7 may also be selected. For example, if bits 5 and
7 are set while bit 6 is cleared, the prescaler divides by
40. Thus, possible prescaler values are: .;. 2, .;. 5, .;. 10,
.;. 20, .,. 40, .;. 100, and.;. 200.
explained in the following paragraphs.
An OUT or OUTS instruction to port 7 loads the contents
of the accumulator into both the timer and the 8-bit
modulo·N register, resets the prescaler, and clears any
previously stored timer interrupt request. As previously
noted, the timer is an 8·bit down counter that is clocked
by the prescaler in the interval timer mode and in the
pulse width measurement mode. The prescaier is not
used in the event counter mode. The modulo·N register
is a buffer whose function is to save the value that was
most recently output to port 7. The modulo·N register is
used in all three timer modes.
Any of three conditions cause the prescaler to be
reset: whenever the timer is stopped by clearing ICP
bit 3, on execution of an output instruction to port 7 (the
timer is assigned port address 7), or on the trailing edge
transition of the EXT INT pin when in the pulse width
measurement mode. These last two conditions are
Interval Timer Mode - When ICP bit 4 is cleared (logic 0)
and at least one prescale bit is set, the timer operates in
the interval timer mode. When bit 3 of the ICP is set, the
timer starts counting .down from the modulo·N value.
After counting down to H '01', the timer returns to the
4·12
F3870
error over many intervals is zero. The prescaler and timer
generate precise intervals for setting the timer interrupt
request latch, but the time-out may occur at any time
within a machine cycle. (There are two types of machine
cycles: short cycles that consist of four clock periods,
and long cycles that consist of 6 clock periods.) In the
multi-chip F8 family, there is a signal referred to as the
write clock, which corresponds to a machine cycle.
Interrupt requests are synchronized with the internal
write clock, thus giving rise to the possible ± 6 error.
Additional errors may arise due to the interrupt request
occurring while a privileged instruction or multi-cycle
instruction is being executed. Nevertheless, for most
applications, all of the above errors are negligible,
especially if the desired time interval is greater than
1 ms.
modulo-N value at the next count. On the transition from
H '01' to H' N', the timer sets a timer interrupt request
latch. Note that the interrupt request latch is set by the
transition of H' N' in the timer, thus allowing a full 256
counts if the modulo-N register is preset to H '00'. If bit
1 of the ICP is set, the interrupt request is passed to the
CPU section of the F3870. However, if bit 1 of the ICP is
a logic 0, the interrupt request is not passed, but the
interrupt request latch remains set. If ICP bit 1 is
subsequently set, the interrupt request is then passed to
the CPU. Only two events can reset the timer interrupt
request latch: when the timer interrupt request is
acknowledged by the CPU, or when a new load of the
modulo-N register is performed.
Consider an example in which the modulo-N register
is loaded with H '64' (decimal 100). The timer interrupt
request latch is set at the 100th count following the
timer start, and the timer interrupt request latch is
repeatedly set on precise 100-count intervals. If the
prescaler is set at .,. 40, the timer interrupt request
latch is set every 4000 clock periods. For a 2 MHz
clock (4 MHz time base frequency), this produces
2 ms intervals.
Pulse Width Measurement Mode - When ICP bit 4 is set
(logic 1) and at least one prescale bit is set, the timer
operates in the pulse width measurement mode. This
mode is used for accurately measuring the duration of a
pulse applied to the EXT INT pin. The timer is stopped
and the prescaler is reset when the EXT INT pin is at its
inactive level. The active level of EXT INT is defined by
ICP bit 2: if cleared, EXT INT is active-low; if set, EXT
INT is active-high. If ICP bit 3 is set, the prescaler and
timer start counting when EXT INT transfers to the active
level. When EXT INT returns to the inactive level, the
timer stops, the prescaler resets, and, if ICP bit 0 is set,
an external interrupt request latch is set. (Unlike timer
interrupts, external interrupts are not latched if the ICP
interrupt enable bit is not set.)
The range of possible intervals is from 2 to 51,200
clock periods (1 ",s to 25.6 ms for a 2 MHz clock).
However, approximately 50 periods is a practical
minimum because the time between setting the interrupt
request latch and the execution of the first instruction of
the interrupt service routine is at least 29 periods (the
response time is dependent upon how many privileged
instructions are encountered when the request occurs).
To establish time intervals greater than 51,200 clock
periods is simply a matter of using the timer interrupt
service routine to count the number of interrupts, saving
the result in one or more of the scratchpad registers
until the desired interval is achieved. With this
technique, virtually any time interval, or several time
intervals, may be generated.
As in the interval timer mode, the timer may be read at
any time, or may be stopped at any time by clearing ICP
bit 3, the prescaler and the ICP bit 1 function as
previously described; the timer still functions as an 8-bit
binary down counter with the timer interrupt request
latch being set on the timer's transition from H '01 ' to
H' N' (modulo-N value). Note that the EXT INT pin has
nothing to do with loading the timer; its action is that of
automatically starting and stopping the timer and of
generating external interrupts. Pulse widths longer than
the prescaler value times the modulo-N value are easily
measured by using the timer interrupt service routine to
store the number of timer interrupts in one or more
scratchpad registers.
The timer may be read at any time and in any mode using
an input instruction (IN 7 or INS 7); this may take place
on-the-fly without interfering with normal timer operation.
The timer may also be stopped at any time by clearing
bit 3 of the ICP. The timer holds its current contents
indefinitely and resumes counting when bit 3 is again
set. The prescaler, however, is reset whenever the timer
is stopped; thus, a series of starts and stops results in a
cumulative truncation error.
As for accuracy, the actual pulse duration is typically
slightly longer than the measured value because the
status of the prescaler is not readable and is reset when
the timer is stopped. Thus, for maximum accuracy, it is
advisable to use a small-division setting for the
prescaler.
For a free-running timer in the interval timer mode, the
time interval between any two interrupt requests may be
in error by ± 6 clock periods, although the cumulative
4-13
4
F3870
Event Counter Mode - When ICP bit 4 is cleared and all
prescale bits (ICP bits 5, 6, and 7) are cleared, the timer
operates in the event counter mode. This mode is used
for counting pulses applied to the EXT INT pin. If ICP bit
3 is set, the timer decrements on each transition from
the inactive level to the active level of the EXT INT pin.
The prescaler is not used in this mode but, as in the
other two timer modes, the timer may be read at any
time, or may be stopped at any time by clearing ICP bit
3; ICP bit 1 functions are previously described, and the
timer interrupt request latch is set on the timer's
transition from H '01' to H 'N' (modulo-N value).
When an interrupt is allowed, the CPU requests that the
interrupting element pass its interrupt vector address to
the program counter via the data bus. The vector address
for a timer interrupt is H' 20'; the vector address for an
external interrupt is H 'OAO'. After the vector address is
passed to the program counter, the CPU sends an
acknowledge Signal to the appropriate interrupt request
latch, which clears that latch. The execution of the
interrupt serVice routine then commences. The return
address of the original program is automatically saved .in
the stack register, P.
Power-On Clear
The F3870 contains power-on clear circuitry to
automatically reset the internal logic following the
application of external power. Since many variations
of power supply circuitry exist, Fairchild cannot
guarantee that the power-on clear will operate under
every power-up condition.
Normally, ICP bit 0 should be kept cleared in the event
counter mode; otherwise, external interrupts are
generated on the transition from the inactive level to the
active level of the EXT INT pin.
For the event counter mode; the minimum pulse width
required on the EXT INT pin is 2 clock periods, and the
minimum inactive time is 2 clock periods; therefore,
the maximum repetition rate is 500 Hz.
The power-on clear circuitry contains on-chip sensors to
monitor various conditions. The following conditions
must be satisfied before the power-reset sequence is
allowed to start:
1. Supply voltage must be above a certain value, typically
+ 3 V to +4 V.
2. The clocks of the device must be functioning.
3. The substrate bias must reach a certain level.
External Interrupts
When the timer is in the interval timer mode, the EXT INT
pin is available for non-timer-related interrupts. If ICP bit
o is set, an external interrupt request latch is set when
there is a transition from the inactive level to the active
level of the EXT INT pin (EXT INT is an edge-triggered
input). The interrupt request is latched until either
acknowledged by the CPU or ICP bit 0 is cleared (unlike
timer interrupt requests, which remain latched even when
ICP bit 1 is cleared). External interrupts are handled in
the same fashion when the timer is in the pulse width
measurement mode or in the event counter mode, except
that in the pulse width measurement mode the external
interrupt request latch is set on the trailing edge of the
EXT INT input; that is, on the transition from the active
level to the inactive level.
All three conditions must be met before the power-on
clear circuitry initiates a reset cycle. However, these
conditions can be satisfied even with a supply voltage of
as low as 3 volts. The latest versions of the F3870 have a
modified delay circuit that gives a typicaldelay.of 500,.s
(with a 4 MHz crystal) after the above conditions are met.
This is an improvement over the earlier F3870 versions.
Since the F3870 is only guaranteed to operate at a
supply voltage of 4.5 V or greater, the user must ensure
that the supply voltage is at least 4.5 V when the F3870
initiates the reset cycle. For power supplies having a
slow rise time, an external RC network can be converted
to the external reset input of the F3870 to hold the
device in a reset state long enough to allow the power
supply to reach a voltage of 4.5 V.
Interrupt Handling
When either a timer or an external interrupt request is
communicated to the CPU section of the F3870, it is
acknowledged and processed at the completion of the
first non-privileged instruction if the interrupt control bit
of the status register is set. If the interrupt control bit is
not set, the interrupt request continues either until the
interrupt control bit is set and the CPU acknowledges
the interrupt or until the interrupt request is cleared as
previously described.
+5V
R
EXTERNAL RESET
F3870
If there are a timer interrupt request and an external
interrupt request when the CPU starts to process the
requests, the timer interrupt is handled first.
4-14
F3870
External Reset
When the RESET input is low, the contents of the
program counter are pushed to the stack register and the
program counter and the ICB of the status register are
cleared. The original stack register contents are lost. As
with power-on clear, ports 4, 5, 6, and 7 are loaded with
H '00'. The contents of all other registers and ports are
unchanged. When RESET is high, the first program
instruction is fetched from ROM location H '0000'.
Fig. 6
F3870 Clock Configurations
Crystal Mode
External Mode
OPEN
AT CUT 1 - 4 MHz
Test Logic
Special test logic is implemented to allow access to the
internal main data bus for test purposes.
EXTERNAL
CLOCK
LC Mode
RC Mode
Vee
~L
~*
In .normal operation, the TEST pin is unconnected or is
connected to ground. When TEST is placed at a level of
from 2.8 V to 3.0 V, port 4 becomes an output of the
internal data bus and port 5 becomes a wired-OR input to
the internal data bus. The data appearing on the port 4
pins is logically true, whereas input data forced on port 5
must be logically false. When TEST is placed at a high
level (8.8 V to 9.0 V), the ports act as described above
and, additionally, the program ROM is prevented from
driving the data bus. In this mode, operands and
instructions may be forced externally through port 5
instead of being accessed from the program ROM. When
TEST is in either the TTL state or the high state, STROBE
ceases its normal function and becomes a cycle clock
(identical to the F8 mUlti-chip system write clock, except
inverted).
CEXTERNAl.
(OPTIONAL-CAN
.L BE OMITTED)
L_.,€-_J
CEXTE.NAL (OPTIOIijAL)
Minimum R = 4kO
Minimum L=O.l mH
Minimum Q= 40
C = 20.5 pF ± 2.5 pF + CEXTERNAL
Maximum CEXTERNAL = 30 pF
1
f MIN " 1.1 RC+65ns
1
f MAX " 1.0RC+15ns
Timing complexities render the capabilities associated
with the TEST pin impractical for use in a user
application, but these capabilities are sufficient to
enable Fairchild to implement a rapid method for
thoroughly testing the F3870.
C= 10 pF ± 1.3 pF + CEXTERNAL
1
f=--
- 2",f[C
Example with CEXTERNAL = 0
Example with CEXTERNAL = 0
R= 15 kO± 5%
f" 2.9 MHz± 26%
f " 3.0 MHz± 10%
L=0.3 mH± 10%
Instruction Set
The F3870 executes the entire instruction set of the
multi-chip F8 family (F3850 family), as shown in Table 3.
Of course, the STORE instrllction is of little use in the
F3870 because only read-only memory exists in the
addressing range of the data counter (the data counter,
however, is incremented if STORE is executed).
F3870 Clocks
The time bases for the F3870 may originate from one of
four external sources; the four external configurations
are shown in Figure 6. There is an internal 26.5 pF
capacitor between XTL 1 and GND, and also between
XTL 2 and GND. Thus, external capacitors are not
required. In all external clock modes, the external time
base frequency is divided by 2 to form the internal
clock.
A summary of programmable registers and ports is given
in Figure 7.
Also, for convenient reference, a programming model of
the F3870 is given in Figure 8.
4-15
•
F3870
Table 3
F3870 Instruction Set
Accumulator Group Instructions
Operation
Add Carry
Add Immediate
AND Immediate
Clear
Compare Immediate
Complement
Exclusive OR Immediate
Increment
Load Immediate
Load Immediate Short
OR Immediate
Shift Left One
Shift Left Four
Shift Right One
Shift Right Four
Mnemonic
OP Code
LNK
AI
NI
CLR
CI
COM
XI
INC
LI
LIS
01
SL
SL
SR
SR
Operand
ii
ii
ii
jj
ii
i
ii
1
4
1
4
Function
ACC-(ACC)+ CRY
ACC-(ACC) + H'ii'
ACC-(ACC) A H'ii'
ACC-H'OO'
H'ii' + (ACC) + 1
ACC-(ACC) .. H'FF'
ACC-(ACC) .. H'ii'
ACC-(ACC)+ 1
ACC-H'ii'
ACC-H'Oi'
ACC-(ACC) V H'ii'
SHIFT LEFT 1
SHIFT LEFT 4
SHIFT RIGHT 1
SHIFT RIGHT 4
Machine
Code
Bytes
Cycles
19
24 ii
21 ii
70
25 ii
18
23 ii
IF
20 ii
7i
22 ii
13
15
12
14
1
2
2
1
2
1
2
1
2
1
2
1
1
1
1
1
2.5
2.5
1
2.5
1
2.5
1
2.5
1
2.5
1
1
1
1
Status Bits
OVF ZERO CRY
SIGN
110
110
0
110
110
110
110
110
0
110
110
I/O
I/O
0
0
110
110
I/O
110
110
I/O
0
0
I/O
I/O
I/O
I/O
I/O
-
-
-
-
-
0
0
0
0
0
I/O
I/O
I/O
110
I/O
0
0
0
0
0
-
I/O
I/O
I/O
1
1
Branch Instructions
(In All Conditional Branches, PO (PO) + 2 if the Test Conditions Are Not Met. Execution Is Complete in 30 Cycles.)
Operation
Branch
Branch
Branch
Branch
on
on
on
on
Carry
Positive
Zero
True
Mnemonic
OP Code
Operand
BC
BP
BZ
BT
aa
aa
aa
t,aa
Function
PO-[(PO)+
PO-[(PO)+
PO-[(PO) +
PO-[(PO) +
1)+ H'aa'
1)+ H'aa'
I) + H'aa'
I) + H'aa'
if
if
if
if
CRY= 1
SIGN= 1
ZERO = 1
any test is true
Machine
Code
Byte.
Cycle.
82 aa
81 aa
84 aa
8t aa
2
2
2
2
3.5
3.5
3.5
3.5
Status Bits
OVF ZERO CRY
-
-
-
-
-
-
-
-
SIGN
-
-
t=TEST CONDITION
I
22
I 2'
2°
I
I
IZERO I CRY I SIGN I
Branch
Branch
Branch
Branch
Branch
if
if
if
if
if
Negative
No Carry
No Overflow
Not Zero
False Test
BM
BNC
BNO
BNZ
BF
aa
aa
aa
aa
t,aa
PO-[(PO)+
PO-[(PO) +
PO-[(PO)+
PO-[(PO)+
PO-[(PO)+
1)+ H'aa' if SIGN = 0
I) + H'aa' if CARRY", 0
1)+ H'aa' if OVF=O
1)+ H'aa' if ZERO=O
1)+ H'aa' if all false test bits
91 aa
92 aa
98 aa
94 aa
9t aa
2
2
2
2
2
3.5
3.5
3.5
3.5
3.5
8F aa
2
90 aa
29 aaaa
2
3
2.5
2.0
3.5
5.5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
t = TEST CONDITION
I
23
1
I
22
I OVF ZERO
Branch if ISAR (Lower) 7
BR7
aa
Branch Relative
Jump·
BR
JMP
aa
aaaa
I
2'
I
2°
I
ICRY I SIGN I
PO-[(PO)+ 1)+ H'aa' if ISARLH
PO-(PO)+2 if ISARL=7
PO-[(PO)+ 1)+ H'aa'
PO-H'aaaa'
-
-
-
-
-
-
-
Memory Reference Instructions (In All Memory Reference Instructions, the Data Counter Is Incremented DC-DC.1.)
Operation
Add Binary
Add Decimal
AND
Compare
Exclusive OR
Load
Logical OR
Store
Mnemonic
OP Code
AM
AMD
NM
CM
XM
LM
OM
ST
Operand
Function
ACC-(ACC) + [(DC))
ACC-(ACC)+ [(DC)]
ACC-(ACC) A [(DC))
[(DC)) + (ACC) + 1
ACC-(ACC) .. [(DC))
ACC-[(DC))
ACC-(ACC) V [(DC))
(DC)-(ACC)
·Prlvlleged instruction
Note
JMP and PI change accumulator contents to the high byte address.
4-16
Machine
Code
Bytes
Cycles
88
89
8A
80
8C
16
8B
17
1
1
1
1
1
1
1
1
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
Status Bits
OVF ZERO CRY
SIGN
I/O
I/O
I/O
110
I/O
110
I/O
0
I/O
0
I/O
110
110
I/O
110
I/O
I/O
0
I/O
0
-
-
-
0
I/O
0
I/O
-
-
-
-
-
F3870
Table 3
F3870 Instruction Set (Con!.)
Address Register Group Instructions
Operation
Mnemonic
OP Code
Add to Data Counter
Call to Subroutine
Call to Subroutine Immediate
Exchange DC
Load Data Counter
Load Data Counter
Load DC Immediate
Load Program Counter
Load Stack Register
Return From Subroutine
Store Data Counter
Store Data Counter
Store Stack Register
ADC
PK"
PI"
XDC
LR
LR
DCI
LR
LR
POP"
LR
LR
LR
Operand
aaaa
DC,Q
DC,H
aaaa
PO,Q
P,K
Q,DC
H,DC
K,P
Function
DC-(DC)+ (ACC)
P-(PO); POU-(r12); PL-(r13)
P-(P); PO- H'aaaa't
DC-DC1
DCU-(r14); DCL-(r15)
DCU-(r10); DCL-(r11)
DC-H'aaaa'
POU-(r14); POL-(r15)
PU-(r12); PL-(r13)
PO-(P)
r14-(DCU); r15-(DCL)
r10-(DCU); r11-(DCL)
r12-(PU); r13-(P)
Machine
Code
Byte.
Cycle.
8E
OC
28 aaaa
2C
OF
10
2A aaaa
OD
09
1C
OE
11
08
1
1
3
1
1
1
3
1
1
1
1
1
1
2.5
4
6.5
2
4
4
6
4
4
2
4
4
4
Machine
Code
Byte.
Cycle.
06
07
Fr
Er
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
1.5
1
1
1
1
1
1
1
1
1
1
1
1
Machine
Code
Byte.
Cycle.
1A
1B
26 aa
Aa
OB
01101a""
01100a""
1D
2B
27 aa
Ba
OA
1E
1
1
2
1
1
1
1
1
1
2
1
1
1
2
2
4
4"""
1
1
1
2
1
4
4"""
1
1
Statu. Bit.
OVF ZERO CRY
-
-
-
-
-
-
-
-
SIGN
-
-
Scratchpad Register Instructions (Refer to Scratch pad Addressing Modes.)
Operation
Mnemonic
OP Code
Operand
AS
ASD
DS
LR
LR
LR
LR
LR
LR
LR
LR
LR
LR
NS
XS
r
r
r
A,r
A,KU
A,KL
A,QU
A,QL
r,A
KU,A
KL,A
QU,A
QL,A
r
r
Mnemonic
OP Code
Operand
Add Binary
Add Decimal
Decrement
Load
Load
Load
Load
Load
Load
Load
Load
Load
Load
AND
Exclusive OR
Function
ACC-(ACC) + (r)
ACC-(ACC)+ tr)
r-(r) + H'FF
ACC-(r)
ACC-(r12)
ACC-(r13)
ACC-(r14)
ACC-(r15)
r-(ACC)
r12-(ACC)
r13-(ACC)
r14-(ACC)
r15-(ACC)
ACC-(ACC) A (r)
ACC-(ACC)., (r)
Cr
Dr
3r
4r
00
01
02
03
5r
04
05
Statu. Bit.
OVF ZERO CRY
SIGN
1/0
1/0
1/0
110
110
1/0
1/0
1/0
1/0
110
1/0
1/0
-
-
-
-
-
0
0
-
-
-
-
-
-
-
1/0
1/0
0
0
1/0
1/0
Miscellaneous Instructions
Operation
Disable Interrupt
Enable Interrupt"
Input
Input Short
Load ISAR
Load ISAR Lower
Load ISAR Upper
Load Status Register"
No·Operation
Output
Output Short
Store ISAR
Store Status Register
DI
EI
IN
INS
LR
LlSL
LlSU
LR
NOP
OUT
OUTS
LR
LR
aa
a
IS,A
a
a
W,J
aa
a
A,IS
J,W
Function
RESET ICB
SET ICB
ACC-(INPUT PORT aa)
ACC-(INPUT PORT a)
ISAR-(ACC)
ISARL-a
ISARU-a
W-(r9)
PO-(PO)+ 1
OUTPUT PORT aa-(ACC)
OUTPUT PORT a-(ACC)
ACC-(ISAR)
r9-(W)
*Privileged instruction
""3·bit octal digit
"" "Two machine cycles for CPU ports
tContents of ACC destroyed
4·17
Statu. Bits
OVF ZERO CRY
SIGN
-
-
-
-
0
0
1/0
1/0
0
0
1/0
1/0
-
-
-
-
-
1/0
1/0
110
1/0
-
-
-
-
-
-
II
F3870
Table 3
F3870 Instruction Set (Cont.)
Notes
Each lower case character represents a hexadecimal digit.
Each cycle equals four machine clock periods.
Lower case denotes variables specified by the programmer.
J
K
KL
KU
PO
POL
POU
P
PL
PU
a
aL
au
Function D811"ltons
is replaced by
()
the contents of
(-)
binary ones complement of
+
arithmetic add (binary or decimal)
m
logical OR exclusive
A
logical AND
V
logical OR inclusive
H'#'
hexadecimal digit
Register
a
A
DC
DCl
DCL
DCU
H
i and ii
ICB
IS
ISAR
ISARL
ISARU
Names
address variable
accumulator
data counter (indirect address register)
data counler #1 (auxiliary data counter)
least significant eight bits of data counteraddressed
most significant eight bits of data counter addressed
scratchpad register #10 and #11
immediate operand
interrupt control bit
indirect scratchpad address register
indirect scratchpad address register
least significant three bits of ISAR
most significant three bits of ISAR
W
scratchpad register #9
registers #12 and #13
register #13
registe'r #12
program counter
least significant eight bits of program counter
most significant eight bits of program counter
stack register
least significant eight bits of program counter
most significant eight bits of active stack register
registers #14 and #15
register #15
register #14
scratchpad register (any address through 11)
status register
Scratchpad Addressing Modes (Machine Code Format)
r= C
(hexadecimal) register addressed by ISAR (unmodified)
r= 0
(hexadecimal) register addressed by ISAR; ISARL incremented
r= E
(hexadecimal) register addressed by ISAR; ISARL decremented
(no operation performed)
r= F
r= O-B (hexadecimal) register 0 through 11 addressed directly from the
instruction
Status Register
no change in condition
1/0
is set to 1 or 0, depending on conditions
CRY
carry flag
Mask Options
3. Input/output ports 0 and 1 can be specified either
cleared or unaltered following an external reset.
4. External interrupt and external reset can be specified to
have or omit an internal pull·up resistor.
5. The I/O port output option choices are: the standard
pull·up (option A), the open drain (option B), and the
driver pull·up (option C).
The ROM array may contain object program code and/or
tables of nonvarying data. Every F3870 is implemented
using a custom mask that specifies the state of every
ROM bit, as well as certain address mask options that are
,external to the ROM array. The following mask options are
specified:
1, The 1024, 2048, 3072, or 4096 bytes of ROM storage.
This reflects programs and permanent data tables
stored in the PSU memory.
2. Input/output ports can be any of the following three
configurations:
a. Standard pull·up
b. Open drain
c. Direct drive
The format for mask options must be submitted to
Fairchild Microprocessor Division before device
manufacture. The data,to be stored in permanent memory
may be submitted in the form of an EPROM or
HP2644/HP264S cartridge (Formulator format only), Other
options must be specified on the Fairchild ROM Code
Entry Form, available from a Fairchild representative.
4·18
F3870
Fig. 7
Programmable Registers and Ports
ACCUMULATOR
I
I
A
Ii I I Ie I I
STATUS
REGISTER W
0
z
DEC
I
4 3
INDIRECT
SCRATCHPAO
ADDRESS
REGISTER
BYTE ADDRESS
OCT
HEX
SCRATCH PAD
S
0
I
IS
11
AUX DATA
COUNTER
11
lOCI
DATA
COUNTER
I
DC
1~
10
H 1
1 Hl
11
13
KU
12
1
Kl
13
"IS
0 1
1
au
"
al
1
11
A
HU
16
IS
16
17
10
20
11
STACK
REGISTER
PROGRAM
COUNTER
I
P
S8
3A
72
11
S9
3.
73
I
60
3C
7'
61
3D
7S
62
3E
76
63
3'
77
PO
.,NARV
TIMER
PORT 7
I/O PORT 0
INTERRUPT
CONTROL
PORT 6
I/O PORT 1
PORT
I/O PORT.
I
~--------~~~
I/O PORT S
4·19
Fig. 8
Programmiag Medel
r--------------------------.~I
OUTS 7
AOC
INS·7
el ~. •
ST..A.T.V.S.,--
~
Ol • .
LNO
OUTS 6
INS~6
1PO)
tSAR
OUTS P. (P
0.1.4,5)
INS"P,-,P 0.1.4.5)
lISU
110
POATS
(4)
5 V VOLTS
lOGIC'O'
ON I/O
PINS
SCRATCHPAO
REGISTERS
AYX DATA
COUNTER
,.0
LA
....
Iii
~
(IS)3:1.
+
I.
I I
I
(90)
....
os·
PROGRAM
ROM
HEX
OCTAL
* These instructions sel status
<
_ _ _ _........,1 RESET t,.l1$f.,..P09 to P and
then clears PO, 1C8 -bit 01 W.
EXTERNAL INTERRUPT
and¥orts 4. 5,6, and 7.
tt
The "alue of the externat Inle:f'JUpt input is tHded 10
bit .7 of the accumulator (with bits 0 throu9h 6 loaded
with UfOS) when the klsttucHon 'INS 6' is execLited.
This insthlction -Ilso sets status.
po, p. DC, and DC1 .... 12·bU registers.
INPUT ( ..S-V '" LOGIC 1)
Note:
The instructions PI and PI< are shown in two sequential parts (PI1, PI2, and PK1, PK2).
• • (00
I....
o
F3870
Supplementary Notes
This nomenclature is used to be consistent with the
assembly language mnemonics.
For total software compatibility when expanding into a
multi·chip configuration, the F3871 Peripheral
Input/Output circuit should be used. The F3871 has the
same improved timer (binary count, readable, and three
modes of operation) and ready strobe outputs as
the F3870.
For the F3870, execution of an INS or OUTS instruction
requires two machine cycles for ports 0 and 1, whereas
ports 4 and 5 require four machine cycles.
When an external reset of the F3870 occurs, PO pushes
into P and the old contents of P are lost. It must be
noted that an external reset is recognized at the start of
the machine cycle and not necessarily at the end of an
instruction. Thus, if the F3870 is executing a multi·cycle
instruction, that instruction is not completed and the
contents of P upon reset may not necessarily be the
address of the instruction that would have been
executed next. It may, for example, point to an
immediate operand if the reset occurred during the
second cycle of an L1 or C1 instruction. Additionally,
several instructions (JMP, P1, PK, LR, PO and Q) as well
as the interrupt acknowledge sequence modify PO in
parts. That is, they alter PO by loading first one part, then
the other, and the entire operation takes more than one
cycle. Should reset occur during this modification
process, the value pushed into P is part of the old PO
(the as·yet unmodified part) and part of the new PO
(already·modified part). Thus, care should be taken
(perhaps by external gating) to ensure that reset does not
occur at an undesirable time if any significance is to be
given to the contents of P after a reset occurs.
The interrupt control bit of the status register is
automatically reset when an interrupt request is
acknowledged. It is then the programmer's responsibility
to determine when the ICB is again to be set (by
executing the E1 instruction). This action prevents an
interrupt service routine from being interrupted unless
the programmer so desires.
When reading the interrupt control port (port 6), bit 7 of
the accumulator is loaded with the actual logic level
being applied to the EXT INT pin, regardless of the
status of ICP bit 2 (the EXT INT active level bit); that is, if
the EXT INT pin is at + 5 V, bit 7 of the accumulator is
set to a logic 1, but if the EXT INT pin is at ground,
accumulator bit 7 is reset to logic O.
In Table 3, the number of cycles shown is "nominal
machine cycles." A nominal machine cycle is defined as
4 q, clock periods, thus requiring 2/1-s for a 2 MHz clock
frequency (4 MHz external time base frequency).
Table 3 also uses the following nomenclature for
register names:
F8 -F3870
PC o = PO
PC 1 = P
DC c = DC
DC 1 = DC1
Program Counter
Stack Register
Data Counter
Auxiliary Data Counter
4·21
4
F3870
Timing Characteristics
The F3870 timing characteristics are described in Table 4
and illustrated in Figures 9 and 10.
Table 4
Timing Characteristics
Signal
XTL 1
XTL 2
eI>
WRITE
I/O
Symbol
Characteristic
Min
Max
Unit
250
1000
ns
External Clock Pulse Width, high
90
700
ns
External Clock Pulse Width, low
100
700
ns
to(EX)
Time Base Period, All External Modes
tEx(H)
tEx(L)
tel>
Internal eI> Clock Period
2tel>
tw
Internal WRITE Clock Period
4tel>
Stel>
t dllO
Output Delay from Internal WRITE Clock
t sllO
Input Setup Time to WRITE Clock
tllOS
Output Valid to STROBE Delay
tSL
STROBE low Time
tRH
RESET Hold Time, low
3~
8t~
-20
EXTINT
tEH
EXT INT Hold Time, Inactive State
C IN
Input Capacitance:
I/O Ports, RESET, EXT INT
CXTL
Input Capacitance: XTL 1, XTL 2
1000
3t~
ns
12~
ns
+2 0
+20
Note 1
ns
Stel>
+ 750
ns
To Trigger
Interrupt
2tel>
ns
To Trigger Timer;
Note 2
7
pF
Unmeasured Pins
Returned to Vss;
Note 4
29.5
pF
Unmeasured Pins
Returned to Vss;
Note 4
Notes
load is 50 pF plus one standard TTL input; S'i'RciiiE load is 50 pF plus three standard TTL inputs.
2. Specification is applicable when the timer is in the interval limer mode.
3. TA=O·C to +70·C, Voo= +5 V±10%, 1/0 power dissipation '" 100 mW, unless otherwise noted.
4. TA=25·C, f=2 MHz.
4·22
50 pF Plus One
TTL Load
St~
23.5
1. 1/0
ns
ns
+ 70
EXT INT Hold Time, Active. State
4 MHz-1 MHz
Short Cycle
Long Cycle
1000
-1 00
STROBE
RESET
0
Notes
F3870
Fig. 9
Timing Diagrams
EXTERNAL CLOCK
INTERNAL (b CLOCK
•
liD PORT OUTPUT
--""\\
r--
LtRH·-J
EXT INT
ICPBIT
{
dt-: L
---:I
ICP BIT 2"'
Note
All measurements are referenced to VIL max, VIH min, VOL max, or VOH min
4·23
tEH
F3870
Fig. 10
Port Input/Output Timing Diagrams
A. Input on Port 4 or 5
INTERNAL
WRITE
CLOCK
IN OR
INS
OPCOOE
FETCHED
PORT ADDA.
PLACED ON
DATA BUS
PORT DATA
DRIVEN ON TO
DATA BUS
NEXT
OPCODE
FETCHED
PORTPIN$
·Cycle timing shown for 4 MHz external clock
B. Output on Port 4 or 5
INTERNAL
WRITE
CLOCK
OUT OR
OUTS
OPCODE
FETCHED
PORT AODR.
ACCUMULATOR
CONTENTS
ON DATA BUS
ON DATA
BUS
POATPINS
NEXT
OPCODE
FETCHED
----+--'
STAYS LOW
FOR TWO WRITE
CYCLES
STRoiIE
(ACTIVE FOR
PORT 4 ONLY)
tI/O-S
500 ns' MIN
·Cycle timing shown for 4 MHz external clock
c.
Input on Port 0 or 1
D. Output on Port 0 or 1
INTERNAL
INTERNAL
WRITE
CLOCK
WRITE
CLOCK
PORT PINS
·Cycle timing shown for 4 MHz external clock
----+--'
·Cycle timing shown for 4 MHz: external clock
4·24
F3870
IiIC Characteristics
Absolute Maximum Ratings
The dc characteristics of the F3870 are described in
Table 5.
These are stress ratings only, and functional operation at
these ratings, or under any conditions above those
indicated in this data sheet, is not Implied. Exposure to
the absolute maximum rating conditions for extended
periods of time may affect device reliability, and
exposure to stresses greater than those listed may cause
permanent damage to the device.
Voltage on any Pin with Respect to
Ground (Except Open-Drain Pins)
Voltage on any Open-Drain Pin
Power Dissipation
Ambient Temperature Under Bias
Storage Temperature
"abla 5
&ymbO.1
DS Charaoterlstlcs
-1.0V, +7V
-1.0V, +13.2V
1.5W
O'C, + 70 'C
- 55'C, + 150'C
TA=O'C to + 70'C, Vee= + 5 V;l:.10%, 1/0 power dissipation :;;100 mW
Characteristic
Min
Max
Unit
Conditions
lee
Power Supply CurreAt
100
mA
Outputs Open
Po
VIHEX
Pewer Dissipation
550
mW
Outputs Open
External Cleck Input HIGH Vol·tage
2.4
5.8
V
VII-HEX
IHEX
External Clock Input LOW Voltage
-0.3
0.6
V
IILEX
VIH
External Cleck Input LOW CurreAt
Input HIGH Vol-tage
VIL
Input LOW Voltage
IIH
Input HIGH Current ('Except Open-Drain
aAd Direct-I!),rive 110 Ports)
100
p.A
V IH = 2.4 V, Internal Pull-Up
IlL
Input LOW Current (-Except Open-Drain
ana Direct-E>rive Ports)
-1.6
mA
V IL =0.4 V
p.A
Pull·Down, Device Off, VOH=13.2 V
p.A
VoH =2.4 V
mA
VoH =0.7 V to 1.5 V
mA
p.A
Vo \.=O.4 V
Vo H=2.4 V
mA
Vo\.=0.4 V
External Clock I·nput HIGH Current
ILoa
Leakage CurreRt (OpeR-Drain Ports)
IOH
Output HIGH Current (Except
Open-Drain and Direct-Drive Perts)
10HDD
Output Drive Current (Direct-Drive Ports)
10L
Output LOW Current
IOHS
Out-put HIGH Current (STROBE Output)
10LS
Output LOW Current (STROBE Output)
100
p.A
VIHEX :;:2.4 V
-100
p.A
VILEX =0.6 V
2.0
5.B
V
-0.3
O,B
V
;1:.10
-100
-1.5
1.B
-300
5.0
4-25
-B.O
•
F3870
Ordering Information
Order Code
Package
Temperature Range'
F3870DC
Ceramic
C
F3870Dl.
Ceramic
l.
F3870DM
Ceramic
M
C
F3870PC
Plastic
F3870Pl.
Plastic
L
F3870PM
Plastic
M
'C", CommerCIal Temperature Range O'C to + 70'C
L", Limited Temperature Range ~40'C to +85'C
M:= Military TempE1rature Range - 55'C to + 125'C
4·26
F3870AlF3870B
High-Speed Single-Chip
Microcomputer
Microprocessor Product
Advance Product Information
Description
The Fairchild F3870A and F3870B are advancements in the
F3870 series of single-chip microcomputers. The F3870A
and F3870B offer higher instruction execution speed,
thereby improving the throughput of the microcomputer.
•
Fully Hardware- and Software- Compatible with the
F3870 Series of Microcomputers
•
The F3870A Offers An Instruction Cycle Time of 1.33
"sec, and the F3870B Cycle Time is 1 "sec.
•
Mask Option Internal Clock Divider
Unit
Clock Crystal Frequency
Without
With
Internal + 2
Internal + 2
F3870
F3870A
F3870B
3 MHz
4 MHz
•
Cycle
Time
4 MHz
6 MHz
8 MHz
For additional information, see the F3870 data sheet
4-27
F3870AI F3870B
4-28
F38C70
Single-Chip
Microcomputer
Microprocessor Product
Connection Diagram
40-Pin DIP
Description
The Fairchild F38C70 8-bit single-chip microcomputer is a
member of the F387X series; it executes all of the F8
instruction set and is software-compatible with the F3870.
Additional power-save instructions provide two different
power-save modes.
XTLl
Vee
XTl2
RESET
EXT INT
POo
P'o
Implemented in ion-implanted CMOS doublepoly silicongate technology, the F38C70 offers maximum cost effectiveness in a wide range of applications requiring very low
power consumption.
p,.
po,
PII:J
P'2
STROBE
Ph
1'40
P4i
P50
ps,
P42
I'4i
P52
1'53
More than 70 commands of the F8 instruction set are
executed by the single-chip microcomputer, which features
2048 bytes of ROM, 64 bytes of scratch pad RAM, a programmable timer, 32 bits of 1/0, and a single + 5 V
power supply.
II
P54
P5s
P56
•
•
•
•
•
•
•
•
•
•
•
•
•
Single CMOS Integrated Circuit
Software-Compatible with F8 and F3870
2048-Byte Mask Programmable ROM
64·Byte Scratch pad RAM
32-Bit 1/0 with Four Options
8·Bit Programmable Timer with 16-Bit
Programmable Prescaler
External Interrupt
Crystal, LC, RC, or External Clock
Single + 5 V (:t 10%) Power Supply
Power·Save (PS) and Power-Save All (PSA)
Modes
Option for all Short Machine Cycles
Direct Replacement for F3870
Low Power (50 mW typ., 5 mW in PS mode,
0.5 mW in PSA mode)
P57
Ph
P06
P'6
P05
~/Ao
PO,
Vss
TEST
(Top View)
Signal Functions
CLOCK
{~
___
XTL1
XTL,
110
PORT
PORT
ADDRESS
INTERRUPTI
RESET
STROBE
TEST
4-29
Vcc~
Vss ....-
L-_ _ _ _---I
l
POWER
F38C70
Figure 1
Block Diagram
INTERRUPT
ADDRESS
VECTOR
XTL2-1
XTL 1 -2
RESET-39
TEST-21
i'00-3
PO;-4
ROM
ADDRESS
REGISTERS
PO, P, DC, DC1
;:;0;-5
;;0;-6
I/O PORTO
P04-19
FiOS-18
POe-17
L..,._ _ _.....JI4--- P07-16
~~~"
ii"i':;-36
INDIRECT
SCRATHPAD
ADDRESS
REGISTER
ii12-35
P1;-34
--~-22
P1,-23
P16_24
..........--. P1 7-25
P4;,-8
P4;-9
I/O PORT 4
P4;-10
P43-11
P4;-12
P4,-13
~-14
i>.!;-15
..
_~==::;-:-:--=
STROBE-7
Ps;;-33
P5,-32
P5,-31
ii5,-30
I/O PORT 5
Ps.;-29
iiSs-28
P5;-27
Ps;-26
4·30
F38C70
Main Control Logic
contiguous scratchpad bytes. For example, when the ioworder octal digit is incremented or decremented, the ISAR
is incremented from octal 27 (0'27) to 0'20' or is
decremented from 0'20' to 0'27'. This feature of the ISAR is
very useful in many program sequences.
The instruction register (IR) receives the operation code
(OP code) of the instruction to be executed from the program ROM through the data bus. Eight bits are latched into
the IR during all OP code fetches. Some instructions are
completely specified by the upper four bits of the OP code;
in these instructions, the lower four bits are an immediate
register address or an immediate 4-bit operand. Once latched into the IR, the main control logic decodes the instruction and provides the necessary control gating signals to all
circuit elements.
All six bits of the ISAR can be loaded at one time, or either
half can be loaded independently.
The decimal scratch pad registers (9 through 15) are given
mnemonic names (J, H, K, and Q) because of special
linkages between these and other registers, such as the
stack register. These special linkages simplify the performance of multi-level interrupts and subroutine nesting. For
example, the instruction LR K,P stores the lower eight bits
of the stack register into register 13 (K lower, or KL) and
stores the upper three bits of P into register 12
(K upper, or KU).
ROM Address Registers
Four 12-bit registers are associated with the program ROM:
program counter PO, stack register P, data counter DCO,
and auxiliary data counter DC1. The program counter is used to address instructions or immediate operands; the
stack register is used to save the contents of PO during an
interrupt or subroutine call. Thus, P contains the return address at which processing is to resume upon completion of
the subroutine or the interrupt routine.
Arithmetic and Logic Unit (ALU)
After receiving commands from the main control logic, the
ALU performs the required arithmetic or logic operations
(using the data presented on the two input buses) and provides the result on the result bus. The arithmetic operations
performed in the ALU are binary add, decimal adjust, add
with carry, decrement, and increment. The logic operations
performed are AND, OR, exclusive-OR, ones complement,
shift right, and shift left. The ALU also provides four signals
presenting the status of the result. These Signals, stored in
status register W, represent the carry, overflow, sign, and
zero condition of the operation.
The data counter is used to address data tables. This
register is autoincrementing. Of the two data counters, only
DCO can access the ROM; however, the XDC instruction
allows DCO and DC1 to be exchanged.
Associated with the address registers is a 12-bit adderl
incrementer. This logic element is used to increment PO
or DC when required and to add displacements to PO on
relative branches or to add the data bus contents to DCO in
the add data counter (ADC) instruction.
Accumulator
The accumulator (ACC) is the prinicpal register for data
manipulation within the F38C70. The ACC serves as one input to the ALU for arithmetic or logic operations; the
results of ALU operations are stored in the ACC.
Program ROM
The microcomputer program and data constants are stored
in the 2048 X 8 byte program ROM. When a ROM access is
required, the appropriate address register (PO or DCO) is
gated onto the ROM address bus and the ROM output is
gated onto the main data bus. The first byte in the ROM is
location zero.
Status Register
The status fY'l) register holds five status flags:
BIT NO.
Scratchpad and ISAR
The scratch pad provides 64 8-bit registers that can be used
as general purpose RAM memory. The indirect scratchpad
address register (ISAR) is a 6-bit register used to address
the 64 registers. All 64 registers can be accessed using the
ISAR. In addition, the lower order 12 registers can also be
directly addressed.
SUMMARY OF STATUS BITS
OVERFLOW=CARRY1. CARRYs
CARRY
= ALU7 A KCOs A AlU s A AiJJ 4 11.
ALU311. AiJJ 2 A ALUl 11. AUiO'
= CARRY 1
SIGN
=ALU7
ZERO
SIGN
CARRY
'-----ZERO
' - - - - - - OVERFLOW
'-------~.
The ISAR can be visualized as holding two octal digits. This
division of the ISAR is important, since a number of instructions increment or decrement only the least significant
three bits of the ISAR when referencing scratch pad bytes
through the ISAR. This simplifies referencing a buffer of
4-31
INTERRUPT CONTROL BIT
•
,
F38C70
Interl'\lpt Control Bit
The interrupt control bit (ICB) is used to allow or disallow
interrupts in the F38C70. (This bit is not the same as the
two interrupt enable bits in the interrupt control port.) If the
ICB is set and the F38C70 interrupt logic communicates an
interrupt request to the CPU section, the interrupt is
acknowledged and processed upon completion of the first
non-privileged instruction. If the ICB is cleared, an interrupt
request is not acknowledged or processed until the ICB is
set again.
An output ready strobe is associated with port 4. This flag
is used to signal a peripheral device that the F38C70 has
just completed an output of new data to port 4. Because
the strobe provides a single low pulse shortly after the output operation Is complete, either edge can be used to
signal the peripheral. The STROBE signal is also used to request new input information ·from a peripheral by performing a dummy output of H'OO' to port 4 after completing the
input operation.
Four output drive options are available for the F38C70 I/O
ports. Individual bits of the four I/O ports are configured as
1/0 Ports
The F38C70provides four complete bidirectional
put ports: 0, 1, 4, and 5. In addition, the interrupt
port Is addressed as port 6, and the binary timer
ed as port 7. Ports 8 and 9 are the l6-bit holding
the timer prescaler.
input/outcontrol
is addressregister for
An output instruction (OUT or OUTS) causes the contents
of the ACC to be latched into the addressed port. An input
instruction (IN or INS) transfers the contents olthe port to
the ACC (port 6, an exception, is described in the "Timer
and Interrupt Control Port") section. The I/O buffers on the
F38C70 are logically inverted.
Figure 2.
1.
Open drain
2.
CMOS 3-state push-pull buffer
3.
TIL-compatible
4.
CMOS push-pull buffer
For the 3-state push-pull buffer, the I/O pin goes 3-state
when executing an INS instruction to that port and remains
in 3-state until an OUTS instruction is executed to that port.
Timer and Interrupt Control Port Block Diagram
EXTERNAL
TlNlE
BASE
+2
3
p0
EVENT COUNTER NlODE ...--..
__
... 2 PRESCALE
__
0
.;. 5 PRESCALE
__
0
... 10 PRESCALE
___
1
+ 20 PRESCALE
_1
.;. 40 PRESCALE
.;. 100 PRESCALE
-+- 1
.;. 200 PRESCALE
1 17ANOlpORT18
+ 200 PRESCALE
USE 16·SIT DATA IN
PORT 8 AND PORT 9
1
NlOOULO-N REGISTER
B-BITS
INTERRUPT
LOGIC
2
1
TINIER INTERRUPT ENABLE
0
1
0
LATCH
0 __ BIT NO.
II IL.=~ 00'"'' '~-"~4"
01
EXT INT ACTIVE LEVEL
1
EXTERNAL
INTERRUPT
REQUEST
LATCH
STARTISTOP TINIER
0
AN~
1---0-1 1~1~RU~~T
n
INTERRUPT
CONTROL
PORT
(PORT 6)
TINIER
TINIER
8·BIT DOWN COUNTER
(PORT
CLOCK
PRESCALER
PORTL
9-=-O------
PULSE WIDTH/INTERVAL TINIER
EXT
llANO PORT 8 OR PORT 9 • 0
INT
AS PRESCALER VALUE
4-32
INT
REQ
F38C70
Timer and Interrupt Control Port
The timer is an 8-bit binary down counter that is softwareprogrammable to operate in one of three modes: interval
timer, pulse width measurement, or event counter. As
shown in figure 2, an 8-bit register (interrupt control port), a
programmable 16-bit prescaler, and an 8-bit modulo-N
register are associated with the timer.
prescaler values are.,. 2, .,. 5, .,. 10, .,. 20,'" 40, .,. 100, and
.,. 200. If bits 5, 6, and 7 of the interrupt control port are set,
and the contents of either of the two prescaler registers are
not zero, the timer uses the value that is held in the two
registers as a 16-bit prescaler value.
The timer mode, prescale value, timer start and stop, active
level of the EXT INT pin, and interrupt local enable/disable
are selected by the proper bit configuration output from the
accumulator to interrupt control port 6 with an OUT or
OUTS instruction. Bits within the interrupt control port are
defined as follows:
1.
When the timer is stopped by clearing ICP bit 3
2.
When an output instruction to port 7 (the timer is
assigned Port Address 7) is executed
3.
On the trailing edge transition of the EXT INT pin
when in the pulse width measurement mode
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Any of three conditions will cause the prescaler to be reset:
=
=
0
External interrupt enable
1
Timer interrupt enable
2 = EXT INT active level
3 = Start/stop timer
Pulse width/internal timer
4
5
2 Prescaler control
6 = .,. 5 Prescaler control
7 = .,. 20 Prescaler control
An OUT or OUTS instruction to port 7 loads the contents of
the accumulator to both the timer and the 8-bit modulo-N
register, resets the prescaler, and clears any previously
stored timer interrupt request. The timer is an 8-bit downcounter clocked by the prescaler in both the interval timer
mode and the pulse width measurement mode. The
prescaler is not used in the event counter mode. The
modulo-N register is used as a buffer in all three timer
modes. Its function is to save the value that was most
recently output to port 7.
=
= .,.
Timer
The F38C70 timer, like the F3870, is an 8-bit programmable
down counter. However, the F38C70 has two additional 8-bit
registers (ports 8 and 9) that can be accessed by output instructions. These registers can be used to generate very
long interval timer interrupts or any desired prescaler value.
Interval Timer Mode
When ICP bit 4 is cleared (logic 0) and at least one prescale
bit is set, the timer operates in the interval timer mode.
When bit 3 of the ICP is set, the timer starts counting down
from the modulo-N value. After counting down to H'01', the
timer returns to the modulo-N value at the next count. On
the transition from H'01' to H'N', the timer sets a timer interrupt request latch. Note that the interrupt request latch
is set by the transition of H'N' in the timer, thus allowing a
full 256 counts if the modulo-N register is preset to H'OO'.
A special situation exists when reading the interrupt control
port with an IN or INS instruction). The accumulator is not
loaded with the content of the ICP; instead, accumlator bits
o through 6 are loaded with zeros, and bit 7 is loaded with
the logic level being applied to the EXT INT pin. Thus, the
status of EXT INT can be determined without needing to
service an external interrupt request. This capability is
useful in establishing a high-speed polled handshake procedure or for using EXT INT as an extra input pin if external
interrupts are not required and the timer is used only in the
interval timer mode.
If bit 1 of the ICP is set, the interrupt request is passed on
to the CPU section of the F38C70. However, if bit 1 of the
ICP is a logic 0, the interrupt request is not passed on the
the CPU section, although the interrupt request latch remains set. If ICP bit 1 is subsequently set, the interrupt
request is then passed on to the CPU section. (The interrupt request is acknowledged by the CPU section only if
ICB is set.) Only two events reset the timer interrupt request latch: the timer interrupt request is acknowledged by
the CPU section, or a new load of the modulo-N register
is performed.
The rate at which the timer is clocked in the interval timer
mode is determined by the frequency of an internal CI> clock
and by the division value selected for the prescaler. (The internal CI> clock operates at one-half the external time base
frequency.) Assuming ports 8 and 9 have been loaded with
zeros, if ICP bit 5 is set and bits 6 and 7 are cleared, the
prescaler divides CI> by two. In the same manner, if bit 6 or 7
is individually set, the prescaler divides CI> by 5 or 20,
respectively. Combinations of bits 5, 6, and 7 may also be
selected. For example, if bits 5 and 7 are set, while 6 is
cleared, the prescaler will divide by 40. Thus, possible
If the modulo-N register is loaded with H'64' (decimal 100),
the timer interrupt request latch is set at the 100th count
following the timer start and the latch is repeatedly set on
precise 100-count intervals. If the prescaler is set at .,. 40,
the timer interrupt request latch is set every 4000 CI> clock
4-33
F38C70
periods. For a 2·mHz clock (4-mHz time base frequency),
this produces 2 ms intervals.
If ports 8 and 9 are loaded with zeros, the range of possible
intervals is from 2 to 51,200 clock periods (1 "s to 25.6
ms for a 2-mHz clock). However, approximately 50
periods is a practical minimum, because the time between
setting the interrupt request latch and the execution of the
first instruction of the interrupt service routine is at least
29 periods (the response time is dependent on how many
privileged instructions are encountered when the
request occurs).
To establish time intervals greater than 51,200 clock
periods, the 16-bit prescaler or the timer interrupt service
routine can be used to count the number of interrupts, saving the result in one or more of the scratchpad registers until the desired interval is achieved. Virtually any time
interval, or several time intervals, can be generated using
this technique.
The timer is read at any time and in any mode, using an input instruction (IN 7 or INS 7), and can take place "on-thefly" without interfering in normal timer operation. Also, the
timer can be stopped at any time by clearing bit 3 of the
ICP. The timer holds its current contents indefinitely and
resumes counting when bit 3 is set again. The prescaler is
reset whenever the timer is stopped; thus, a series of
starting arid stopping results in a cumulative
truncation error.
its inactive level. The active level of EXT INT is defined by
ICP bit 2: if cleared, EXT INT is active low; if set, EXT INT is
active high.
If ICP bit 3 is set, the prescaler and timer start counting
when EXT INT transfers to the active level. When EXT INT
returns to the inactive level, the timer stops, the prescaler
resets, and, if ICP bit 0 is s.et, an external interrupt request
latch is set. (Unlike timer interrupts, external interrupts are
not latched if the ICP interrupt enable. bit is not set.)
As in the interval timer mode, the timer can be read at any
time and can be stopped at any time by clearing ICP bit 3
(the prescaler and ICP bit 1 function as described in the interval timer mode section). The timer still functions as an
8-bit binary down counter with the interrupt request latch
set on the timer's transition from H'01' to H'N' (modulo-N
value). Note that the EXT INT pin has nothing to do with
loading the timer; its action is that of automatically starting
and stopping the timer and of generating external interrupts. Pulse widths longer than the prescale value times the
modulo-N value are easily measured by using the timer interrupt service routine to store the number of timer
interrupts in one or more scratch pad registers.
The actual pulse duration is typically slightly longer than
the measured value, because the prescaler status is not
readable and is reset when the timer is stopped. Thus, for
maximum accuracy, it is advisable to use a small
division setting for the prescaler.
For a free-running timer in the interval timer mode, the time
interval between any two interrupt requests can be in error
by ± 6 clock periods, although the cumulative error over
many intervals is zero. The prescaler and timer generate
precise intervals for setting the timer interrupt request
latch, but the time out can occur at any time within a
machine cycle. (There are two machine cycle types: short,
which consist of 4 clock periods, and long, which consist
of 6 clock periods.) The Fairchild multi-chip F8 family has
a write clock Signal that corresponds to a machine cycle.
Interrupt requests are synchronized with the internal write
clock, thus providing the possible ± 6 error. Additional
errors may arise if the interrupt request occurs while a
privileged instruction or multi-cycle instruction is being
executed. Nevertheless, for most applications, all the above
errors are negligible, especially if the desired time interval
is greater than one ms.
Event Counter Mode
When ICP bit 4 is cleared and all prescale bits (ICP bits 5,
6, and 7) are cleared, the timer operates in the event
counter mode. This mode is used for counting pulses applied to the EXT INT pin. If ICP bit 3 is set, the timer will
decrement on each transition from the inactive level to the
active level of the EXT INT pin. The prescaler is not used in
this mode. As in the other two timer modes, the timer can
be read at any time and can be stopped at any time by
clearing ICP bit 3, ICP bit 1 functions as previously described, and the timer interrupt request latch is set on. the
timer's transition from H'01' to H'N' (modulo-N value).
Pulse Width Measurement Mode
When ICP bit 4 is set (logic 1) and at least one prescale bit
is set, the timer operates in the pulse width measurement
mode. This mode is used to accurately measure the duration of a pulse applied to the EXTINT pin. The timer is
stopped and the prescaler is reset whenever EXT INT is at
For the. event counter mode, the minimum pulse width required on EXT INT is 2 clock periods and the minimum
inactive time is 2 clock periods; therefore, the maximum
repetition rate is 500 Hz.
Normally, ICP bit 0 should be kept cleared in the .event
counter mode; otherwise, external interrupts are generated
on the transition from the inactive level to the active level
of the EXT INT pin.
F38C70
The power-on clear circuitry contains on-Chip sensors to
monitor various conditions. The following conditions must
be satisfied before the power-reset sequence is allowed
to start:
External Interrupts
When the timer is in the interval timer mode, the EXT INT
pin is available for non-timer related interrupts. If ICP bit 0
is set,· an external interrupt request latch is set for a transition from the inactive level to the active level of EXT INT.
(The EXT INT signal is an edge-triggered input.) The interrupt request is latched either until acknowledged by the
CPU section or until ICP bit 0 is cleared (unlike timer interrupt requests that remain latched even when ICP bit 1 is
cleared).
External interrupts are handled in the same fashion when
the timer is in the pulse width measurement mode or in the
event counter mode, except that when in the pulse width
measurement mode, the external interrupt request latch is
set on the trailing edge of EXT INT (that is, on the transition from the active level to the Inactive level).
1.
Supply voltage must be above a certain value,
typically + 3 V to + 4 V.
2.
The clocks of the device must be functioning.
3.
The substrate bias must reach a certain level.
All three conditions must be met before the power-on clear
circuitry initiates a reset cycle. However, these conditions
can be satisfied even with a supply voltage of as low as 3
volts. The latest versions of the F38C70 have a modified
delay circuit that gives a typical delay of 500 ,..s (with a 4
mHz crystal) after the above conditions are met. This is an
improvement over the earlier F38C70 versions.
Interrupt Handling
When either a timer or an external interrupt request is communicated to the CPU section of the F38C70, it is
acknowledged and processed at the completion of the first
non-privileged instruction if the interrupt control bit of the
status register is set. If the interrupt control bit is not set,
the interrupt request continues either until the interrupt
control bit is set and the CPU Section acknowledges the interrupt or until the interrupt request is cleared (as previously described).
Since the F38C70 is only guaranteed to operate at a supply
voltage of 4.5 V or greater, the user must ensure that the
supply voltage is at least 4.5 V when the F38C70 initiates
the reset cycle. For power supplies having a slow rise time,
an external RC network can be converted to the external
reset input of the F38C70 to hold the device in a reset state
long enough to allow the power supply to reach a voltage
of 4.5 V. For example:
+5V
If a timer interrupt request and an external interrupt request
occur simultaneously, when the CPU section starts to pro·
cess the requests, the timer interrupt is
handled first.
F387X
When an interrupt is allowed, the CPU section requests
that the interrupting element pass its interrupt vector address to the program counter through the data bus. The
vector address for a timer interrupt is H'020'. "the vector address for external interrupts is H'OAO'. After the vector address is passed to the program counter, the CPU section
sends an acknowledge signal to the appropriate interrupt
request latch, which clears that latch. The interrupt service
routine executes; the return address of the original program
is automatically stored in stack
register P.
EXTERNAL RESET
External Reset
When the 'RESET signal is taken low, the contents of the
program counter are pushed to the stack register and the
program counter and the ICB of the status register are
cleared. The original stack register contents are lost. As
with power-on clear, ports 4, 5, 6, and 7 are loaded with
H'OO'. The contents of all other registers and ports are unchanged. When the RESET signal is taken high, the first
program instruction is fetched from ROM location H'OOOO'.
Power·On Clear
The F38C70 contains power-on clear circuitry to
automatically reset the internal logic following the application of external power. Since many variations of power sup·
ply circuitry exist, Fairchild cannot guarantee that the
power-on clear will operate under every power-up condition.
4-35
F38C70
Figure 3 Clock Configurations
ATCUT1-4MHz
Im,l
OPEN
OPEN
EXTERNAL
CLOCK
Vee
E2JR*
-±-
CEXTERNAL
L_.,t-_ J
(OPTIONAL-CAN
BE OMITTED)
CEXTERNAL (OPTIONAL)
Minimum R=4kO
Example with CEXTERNAL = 0
C '" 20.5 pF ± 2.5 pF +CEXTERNAL
R=15kO±5%
f " 2.9 MHz±26%
C = 10 pF ± .1.3 pF + CEXTERNAL
1
f= - -
- 2".J[C
1
f MIN " 1.1 RC+65ns
Minimum L=0.1 mH
Minimum Q = 40
Example with CEXTERNAL = 0
L = 0.3 mH ± 10%
Maximum CEXTEANAL = 30 pF
f MAX " 1.0 RC+ 15 ns
f " 3.0 MHz± 10%
Test Logic
The TEST pit:! capabilities are impractical for user applications because of timing complexities; however these
capabilities are sufficient to enable Fairchild to implement
rapid methods for thoroughly testing the F38C70.
Special test logic is implemented to allow acceSs to the internal main data bus for test purposes. In normal operation,
the TEST pin must be connected to ground. When the TEST
signal is set to VO.o' port 4 becomes an output of the internal data QUs and port .5 becomes a wired-OR input to the internal data bus. The data appearing on the port 4 pins is
logically true, whereas input data forced on port 5 must be
logically false. When the TEST signal is set to one-half the
level of Vcc (Vcc/2), the ports act as above and the 2K X 8
program ROM is prevented from driving the data bus. In
this mode, operands and instructions are forced externally
through port 5 instead of being accessed from the program
ROM. When the TEST signal is in either the Voo/2 or the
high state, the STROBE signal ceases its normal function
and becomes a cycle clock (identical to the F8 mUlti-chip
system write clock, except inverted).
Clocks
The time bases for the F38C70 originate from one of four
external sources by mask options. These four configurations are illustrated in figure 3. External capacitors are not
required. In all external clock modes, the external time basE
frequency is divided by two to form the internal clock.
The selection of clock configurations is by mask options.
4-36
F38C70
Figure 4 F38C70 Programmable Registers and Ports
ACCUMULATOR
BYTE ADORESS
STATUS
REGISTER W
~f::::S=C=R:AT=C=H=P=A=D:=:~OI
7
4 3
O:C
HEX
OCT
0
11
10
~~~~¢:: 1 DC1
01_
H
L--------I
10
g~1~TER I
0
I
DC
1 HHUL
A
11
12
13
1 KU
12
C
l'
KL
13
0
15
K
Q
1"
U
l'
1 :L
15
17
16
1"
20
58
3A
72
59
3B
73
60
3C
7'
61
30
75
62
3E
76
63
3F
77
16
10
1
STACK
REGISTER L_P_ _ _ _ _ _ _ _...J
10
PROGRAM
COUNTER
0
I
PO
I
L-_ _ _ _ _---I
7
INTERRUPT
CONTROL
PORT
I
0
PORT 6
I
I
0
BINARY
TIMER
PORT 7
PRESCALER
LSW
PORT 8
PRESCALER
MSW
PORT 9
0
7
I
1/0 PORT 0
I
1/0 PORT 1
110 PORT'
lSTROBE
110 PORT 5
4-37
•
F38C70
Figure 5
PS Instruction
PS INSTRUCTION
_~r-_'WAKE UP'
1FETCH INSTRUCTION
FROM LOCATION
ZERO
Figure 6
EXTERNAL INTERRUPT
~
TIMED OUT
~
TIMER INTERRUPT TIMER INTERRUPT
EXTERNAL INTERRUPT
EXTERNAL INTERRUPT
ENArED
DISArED.
ENArED
DljBLED
SERVICE EXTERNAL
INTERRUPT
FETCH tlEXT
INSTRUCTION
SERVICE TIMER
INTERRUPT
FETCH NEXT
INSTRUCTION
PSA Instruction
PSA INSTRUCTION
I
EXTERNAL RESET
I
FETCH INSTRUCTION
FROM LOCATION
ZERO
EXTERNAL INTERRUPT
~
I
I
EXTERNAL INTERRUPT
ENABLED
SERVICE EXTERNAL
INTERRUPT
4-38
EXTERNAL INTERRUPT
DISABLED
FETCH NEXT
INSTRUCTION
F38C70
Power-Save All Mode
When the power-save all instruction (mnemonic PSA, Op
code 2F) is executed, the F38C70 halts all its operations
and goes into a power-save mode (refer to Figures 5 and 6).
The microcomputer is returned to the previous operating
status by an external reset or an external interrupt. Both the
timer and prescaler are reset when PSA is executed, except
in the event counter mode.
Instruction Set
The F38C70 executes the entire instruction set of the F3870
family. In addition, two instructions exclusive to the F38C70
allow the F38C70 to further reduce its power consumption
by entering into one of two power-save modes.
A summary of programmable registers and ports is shown
in Figure 4. Table 1 lists the F38C70 instruction set and
F8·compatible instructions.
In returning from either power-save mode, the microcomputer exercises the interrupt routine or continues with the
next instruction, depending on whether the interrupt is
enabled.
Power-Save Mode
When the power-save instruction (mnemonic PS, OP code
2D) is executed, the F38C70 halts all its operations except
the timer and interrupts. The microcomputer is returned to
the operating status by an external reset, an external interrupt, or a timer interrupt (as the timer is timed out).
If the return is by an external reset, the microcomputer
restarts from the reset mode.
Table 1 F38C70 Instruction Set and Fa-Compatible Instructions
Accumulator Group Instructions
Operation
Add Carry
Add .mmediate
And Immediate
Clear
Compare Immediate
Complement
Exclusive or
Immediate
Increment
Load Immediate
Load Immediate Short
Or Immediate
Shift Left One
Shift Left Four
Shift Right One
Shift Right Four
Mnemonic
OP Code
LNK
AI
NI
CLR
CI
COM
XI
INC
LI
LIS
01
SL
SL
SR
SR
Operand
Function
ii
ACC - (ACC) + CRY
ACC - (ACC) H 'ii'
ACC -+ (ACC) H 'ii'
ACC -+ H'OO'
H'ii'
ACC -+ (ACC) eH'FF'
ACC -+ (ACC) e H ii
ii
1
ii
1
4
1
4
ACC
ACC
ACC
ACC
Shift
Shift
Shift
Shift
ii
ii
ii
(ACC) + 1
H'ii'
-+ H'Oi'
-+ (ACC) V H 'ii'
Left 1
Left 4
Right 1
Right 4
-+
-+
4-39
Machine
Code
Bytes
Cycles
Status Bits
OVF Zero CRY Sign
19
24ii
21ii
70
25ii
18
23 ii
1
2
2
1
2
1
2
1
2.5
2.5
1
2.5
1
2.5
1/0 1/0 1/0 110
1/0 1/0 1/0 1/0
0 1/0 0 1/0
1F
20 ii
7i
22ii
13
15
12
14
1
2
1
2
1
1
1
1
1
2.5
1
2.5
1
1
1
1
1/0 1/0 1/0 1/0
1/0 1/0 1/0 1/0
0 1/0 0 1/0
0 1/0
0 1/0
0
0
0
0
0
1/0
1/0
1/0
1/0
1/0
-
-
-
-
0
0
0
0
0
1/0
1/0
1/0
1/0
1/0
•
F38C70
Table 1 F38C70 Instruction Set and F8·Compatible Instructions (Continued)
Branch Instructions (In all conditional branches, PO (PO) + 2 if the test conditions are not met.
Execution is complete in 30 cycles.)
Operation
Mnemonic
OP Code
Operand
Branch on Carry
BC
aa
Branch on Positive
Branch on Zero
BP
BZ
aa
aa
Branch on True
BT
t,aa
Status Bits
Cycles OVF Zero CRY Sign
Machine
Code
Bytes
82 aa
2
3.5
-
-
-
-
81aa
84aa
2
2
3.5
3.5
-
-
-
-
-
-
8t aa
2
3.5
-
-
- -
1] + H'aa'if
91aa
2
3.5
1] + H'aa'if
92 aa
2
3.5
1] + H'aa' if
98 aa
2
3.5
1] + H'aa' if
94 aa
2
3.5
1] + H'aa' if all
9t aa
2
3.5
8Faa
2
2.5
-
-
-
2.0
90 aa
29 aaa
2
3
3.5
5.5
Function
PO .... [(PO) + 1] + H'aa' if
CRY = 1
PO-- [(PO) + 1] + H'aa' if
PO -. [(PO) + 1] + H'aa' if
Zero = 1
PO .... [(PO) + 1] + H'aa'if
any test is true
1 . TEST CONDITION
Branch if Negative
BM
aa
Branch if No Carry
BNC
aa
Branch if No Overflow
BNO
aa
Branch if Not Zero
BNZ
aa
BF
t.aa
Branch if False Test
PO .... [(PO) +
Sign
0
PO .... [(PO) +
Carry 0
PO .... [(PO)i +
OVF
0
PO .... [(PO) +
Zero
0
PO .... [(PO) +
false test bits
=
'*
=
=
1
23
1OVF
Branch If
ISAR(Lower)7
BR7
aa
Branch Relative
Jump'
BR
JMP
aa
aaaa
= TEST CONDITION
122
121
ZERO CRY
20
1 SIGN
PO+- [(PO) + 1]+ H'aa' if ISARL
'!!,7
PO .... (PO) + 2 if ISARL
7
PO .... [(PO) + 1] + H'aa'
PO .... H'aaa'
=
ft
Privileged instruction
Note
JMP and P1 change accumulator contents to the high byte address.
4·40
-
F38C70
Table 1 F38C70 Instruction Set and FIJ.Compatible Instructions (Continued)
Memory Reference Instructions (In all memory reference instructions, the data counter is incremented DC .....DC Operation
Add Binary
Add Decimal
AND
COMPARE
EXCLUSIVE OR
LOAD
LOGICAL OR
STORE
Mnemonic
OP Code Operand Function
ACC+-(ACC) + [(DC»)
ACC+-(ACC) + [(DC»)
ACC ..... (ACC)A[(DC))
[(DC») + (ACC) + 1
ACC .....(ACC) ED [(DC))
ACC .....[(DC))
ACC .....(ACC) lI[(DC»)
(DC) .....(ACC)
AM
AMD
NM
CM
XM
LM
OM
ST
1.)
Machine
Code
Bytes
Cycles
88
89
8A
80
8C
16
8B
17
1
1
1
1
1
1
1
1
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
Machine
Code
Bytes
Cycles
Status Bits
OVF Zero CRY Sign
Status Bits
OVF Zero CRY Sign
1/0
1/0
0
1/0
0
1/0 1/0 1/0
1/0 110 1/0
1/0 0 1/0
110 110 1/0
1/0 0 1/0
- - -0
-
1/0
0
1/0
- --
Address Register Group Instructions
Operation
Add to Data Counter
Call to Subroutine
Call to Subroutine
Immediate
Exchange DC
Load Data Counter
Load Data Counter
Load DC Immediate
Load Program Counter
Load Stack Register
Return From
Subroutine
Store Data Counter
Store Data Counter
Store Stack Register
Mnemonic
OP Code
Operand
ADC
PK
Function
DC .....(DC) :+- (ACC)
P+-(PO)CI>POU .....(r12) +
PL.....(r13)
p .....(P) PO"'" H'aaaa'
8E
DC
1
1
2.5
4
- - - - - - -
28aaaa
3
6.5
- - - -
*
PI
aaaa
XDC
LR
LR
DCI
LR
LR
POP
DC,a
DC,H
aaaa
pO,a
P,K
DCWC1
DCU .....(r14), DCL .....(r15)
DCU .....(r10), DCL .....(r11)
DC ..... H·aaaa'
POU .....(r14), POL .....(r15)
PU .....(r12), PL .....(r13)
PO\P
2C
OF
10
2Aaaaa
OD
09
1C
1
1
1
3
1
1
1
2
4
4
6
4
4
2
-
LR
LR
LR
a,DC
H,DC
K,P
r14 .....(DCU), r15 .....(DCL)
r10 .....(DCU), r11 .....(DCL)
r12 .....(PU), r13 ..... P
OE
11
08
1
1
1
4
4
4
- - - - - - - - - -
4·41
-
-
-
-
F38C70
Table 1 F38C70 Instruction Set and Fa-Compatible Instructions (Continued)
Scratchpad Register Instructions (refer to scratch pad addressing modes.)
Operation
Add Binary .
Add Decimal
Decrement
Load
Load
Load
Load
Load
Load
Load
Load
Load
Load ..And
Exclusive Or
Mnemonic
OP Code
Operand
AS
ASD
OS
LR
LR
LR
LR
LR
LR
LR
LR
LR
LR
NS
XS
r
r
r
A,r
A,KlJ
A,KL
A,QU
A,QL
r,A
KU,A
KL,A
QU,A
QL,A
r
r
I
Machine
Code
Function
ACC(ACC) + (I}
ACC-(ACC) + (r)
r-(r) + H'FF'
ACC-(r)
AC-(r12)
ACC-(r13)
ACC-(r14)
ACC-(r1S)
r-(ACC)
r12-(ACC)
r13-(ACC)
r14-(ACC)
r1S-(ACC)
. ACC-(ACC)A(r)
ACC-(ACC)$(r)
4-42
Cr
Dr
Sr
4r
00
01
02
03
Sr
04
OS
06
07
Fr
Er
Bytes
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Cycles
1
2
1.S
1
1
1
1
1
1
1
1
1
1
1
1
Status Bits
OVF Zero CRY Sign
1/0 1/0 1/0 1/0·
1/0 110 1/0 1/0
1/0 1/0 1/0 1/0
-
0
0
- --- - -- -- -- -- -- -- -- --
1/0
1/0
0
0
1/0
1/0
F38C70
Table 1 F38C70 Instruction Set and F8-Compatlble Instructions (Continued)
Miscellaneous Instructions
Mnemonic
OPCode
Operation
Disable Interrupt
Enable Interrupt"
Input
Input Short
Load ISAR
Load ISAR Lower
Load ISAR Upper
Load statusreglster
No-Operation
OUTPUT
OUTPUT Short
Store ISAR
Store Status Reg
PoWer Save
Power Save All
Operand
01
EI
IN
INS
LR
lISL
lISU
LR
Nop
OUT
OUTS
LR
LR
PS
PSA
Machine
Code
Function
aa
a
IS.A
a
a
Reset ICB
SET ICB
ACC - (Input PORT aa)
ACC - (Input PORT a)
ISAR-(ACC)
ISARL-a
ISARU -a
W.J
W-(r9)
aa
a
A.15
J.W
PO-(PO) +1
OUTPUT PORT aa ... (ACC)
OUTPUT PORT a ... (ACC)
ACC-(ISAR)
r9'" (W)
Halt Internal Clock
Halt Internal Clock and Timer
1A
1B
26aa
Aa
OB
01101a""
01100""
10
2B
27 aa
Ba
OA
1E
20
2F
Bytes
Cycles
1
1
2
2
2
1
4***
1
1
1
2
1
1
1
1
1
2
1
1
1
1
1
4
1
4
4**·
1
1
-3
3
Status Bits
OVF Zero C~Y $Ign
-0 110- -a 110
-0 110 0 110
- - - - - - - 110 110 110 110
- - - - -.... ,-- -'
- - - - - - - - - - - - - - -
-
• Privileged instruction
":Jobit octal dlgli
'
•• ·Two machine cycles for CPU ports
Notes
Each lower case character represents a hexadecimal digit.
Each cyCle equals four machine clock periods.
Lower case denotes variables specified by programmer.
J
K
Kl
KU
PO
POL
POU
Function dellnltlons
()
(.)
+
•
H'#
is replaced by
the content. of
binary ones complement of
arithmetic edd (binary or decimal)
logical OR exclusive
logical AND
logical OR Inclusive
hexedecimal digit
P
Pl
PU
a
al
au
r
W
scratchpad register #
registers #12 and #13
register #13
register #12
program counter
least significant eight bits of program counter
most significant eight bits of program counter
stack register
least significant eight bits of program counter
most significant eight bits of active stack register
registers #14 and #15
register #15
register #14
scralchpad/register (any address through 11)
status register
Regl..... Names
Scratchped Add.....ng Model (Machine Code Format)
a
r = C
r
0
DC
DCI
DCl
DCU
H
I and II
ICB
IS
ISAR
ISARl
ISARU
address variable
A
accumulator
data counter (Indirect address register)
data counter 111 (auxiliary data counter)
least significant eight bits of data counter addressed
most significant eight bits of data counter addressed
scratchpad register #10 and #11
Immediate operand
interrupt control bit
Indirect scratchpad address register
Indirect scratchpad address register
least significant three bits of ISAR
most significant three bits of ISAR
=
r = E
r =F
r = ()'B
Status Reglst..
1110
CRY
443
- - ,_ .. -
-
-----
-
'-~--
(hexadecimal) register addressed by ISAR (unmodified)
(hesadeclmal) register addressed by ISAR, ISARl Incremented
(hexadeCimal) Register addressed by ISAR, ISARl decremented
(no operation performed)
(hexadecimal) register 0 through 11 addressed directly
from the instruction
no change in condition
Is set to 1 or 0 depending on conditions
carry flag
•
For the F38070,eKecutlon ef an INS or OUTS instruction
requires two l1;Iachlne cycles for ports a and 1, whereas
ports 4 an 5 require four maehlfle cycles. When an external
reset of the F38C70 occurs, ~ is stored in P and the old
oontents of II' are lost. Nlilte that an external reset Is
recognized at the start 0f N'le m.hlne cycle and not
naeesserily at the end of afl Instl'l:lCtlan. Thus, If the F38C70
is executing a mul1l-cycleiflstNcNon, that Inatructhrm Is not
completeC!l, and the canterns af 11', upGn r1!lset, may nlilt
necessarily be the a\!ldress of the Instructi&1'\ that wauld
have been executed next. They may, flilrexample, paint ta
an immediate operand, if N'Ie reset occurreC!l during the second cycle of an LI or CI Instruction. Alllditionally, several
instructiGlns (JM'P, PI, PK, LPI, ~, 0) as well as the Inter·
rupt acknowleC!lge s8liluence, meetify PO in parts. That is,
they alter PO lily first loadlnil ane part, then the GtfIer part,
and the efltire operation takes more than Glne cycle. Shliluld
reset occur during this ""edl·ficat·ion prlilCess, the value
stored In II' becomes part of the GIld PO (the not yet
modlfleC!l part), and part af tl'le new PO (already modified
part). Thus, care sheulEi lie taken (iilerhaps lily external
gating) to ensure that reset d_ not IilCcur at an
undesirable time, If any si,nmcance is tlil be
given to the contents af II' after a reset occurs.
Supplementary Not..
The interrupt control bit of the status register is
automatically reset when an Interrupt request is
acknowledged. It is then the programmer's responsibility to
determine when iCB wilf again be set (by executing an EI
Instruction). This action prevents an interrupt service routine
from being interrupted, unless the prOgrammer so etesires.
When reading the interrupt control port (port 6), bit 7 of·the
accumulator 1, loaded with the actual logic level being ap.plied to the EXT INT pin, regardless of the status of lOP bit
2 (the EXT INT active level bit); that is, If EXT INT Is at + 5
V, bit 7 of the accumulator Is set to a logic 1, but If EXT
INT Is at Vss ' the accumulator bit 7 is reseUo logic O.
In the Instruction set summary (table 1), the number of
cycles shown are nominal machine cycles. A nominal cycle
Is defined as 4 III clock periOds, thus requiring 2 fAS for a
2·mHz clock frequency (4·mHz external time base frequen·
cy). When deslreet, the long maChine cycles can be altered
to short machine cycles by mask option.
The following nomenclature for register names Is used for
consistency with the assembly language mnemonics:
F8
F38C1O
Pee
PC,
P
DCa
DC,
DC
DC1
PO
If desired, theF38C1O can elteci"te all instNctlons in short
cycles via mask optlofls tG Improve the execu·tian speed of
the device.
Aegla'er
program counter
stack register
data counter
auxiliary data counter
4-44
F38C70
Signal Descriptions
The F38C70 input and output signals are described in
Table 2.
Table 2 F38C70 Signal Descriptions
Mnemonic
Pin No.
Name
Description
Clock
XTL,
XTl:!
1
Clock
The time base inputs to which a crystal (1 to 4 mHz), LC
network, RC network, or an external single-phase clock
is connected.
1/0 Ports
POo- P07
P1o- P07
P4o-
P47
P5o-
P57
"
3,4,5,
6, 19, 18
17,16
37,36,
35,34,
22,23,
24,25
8,9,10,
11, 12,
13, 14, 15,
33,32,
31,30,
29,28,
27, 26
Port Address
The 32 ports are individually used as either TIL-compatible
inputs or as latched outputs.
Port Address
1/0 Port
110 Port
Interrupt/Reset
EXTINT
38
External
Interrupt
The active state of the external interrupt signal is software
programmable; it is also used in conjunction with the timer
for pulse width measurement and event counting.
RESET
39
Reset
This input signal is used to reset the F38C70 externally.
When the signal is allowed to go low, the F38C70 resets.
When subsequently allowed to go high, the F38C70 begins
program execution at location H'OOOO'.
Strobe
STROBE
7
Strobe
This output pin, iNhich is normally high, provides a single
low pulse after valid data is present on the P4o- P47 pins
during an output instruction. .
Test
TEST
21
Test
An input signal used only in testing the F38C70. For
normal circuit function, this pin must be connected
to ground.
20
40
Ground
Power $upply
Common power and signal return
Power supply input signal, + 5 (± 10%)
Power
Vss
Vee
4-45
V
F38C70
DC Characteristics
The, characteristics of the F38C70 are provided in
table 3.
Table 3 F38C70 DC Charaterllticl TA =0' to 70'C, Vcc =5V ± 10%, I/O Power Dissipatlon:smW
Symbol
Parameter
Max
Unit
Te.t Condltloris
Icc
Power Supply Current
TBD
mA
Outputs Open
Po
Power Dissipation
TBD
mW
Outputs Open
Min
5.8
V
VIHEX
External Clock Input High Voltage
2.4
VILHEX
External Clock Input Low Voltage
-0.3
IHEX
External Clock Input High Current
100
,..A
-100
,..A
0.6
V
=2.4 V
VILEX = 0.6 V
VIHEx
ILEX
External Clock Input Low Current
VIH
Input High Voltage
2.0
Vcc + 0.3
VIL
Input Low Voltage
-0.3
0.8
IIH
Input High Current (except 3state option)
100
,..A
VIH
=2.4 V, internal pull·up
IlL
Input Low Current (except open
drain and direct drive ports)
-1.6
mA
VIL
=0.4 V
±10
,..A
o"
ILOD
Leakage Current
10H
Output High Current (except open
drain and direct drive ports) std.
IOHDO
Output Drive Current (push-pull)
Output Low Current
IOHS
Output High Current (STROBE Output)
IOLS
Output Low Current (STROBE Output)
TBD
-1.5
mA
mA
1.8
-300
,..A
mA
5.0
VIN " Vcc
VO H
2.4 V
=
VOH = 0.7 V to 1.5 V
VOL = 0.4 V
VOH = 2.4 V
VOL =0.4 V
Ordering Information
Absolute Maximum Ratlngl
These are stress ratings only, and functional operation at
these ratings, or under any conditions above those in·
dicated in this data sheet, is not Implied. Exposure to the
absolute maximum rating conditions for extended periods
of time may affect device reliability, and exposure to
stresses greater than those listed may cause permanent
damage to the device.
Temperature (Ambient) Under Bias
Storage Temperature
Voltage on Any Pin with Respect
to Ground (Except Open Drain Pins)
Power Dissipation
V
,..A
-100
IOL
V
O'C,
- 55'C,
-0.3 V,
Part
Number
F38C70DC
F38C70DL
F38C70DM
F38C70PC
F38C70PL
F38C70PM
+ 70'C'
+ 150°C
Vcc +0.3 V
·c
L
M
1W
4-46
Temperatura
Package
Ceramic
Ceramic
Ceramic
Plastic
Plastic
Plastic
= Commercial Temperature Range o·c to + 7O·C
= Military Temperature Range· 55·C 10 + 125·C
=Umlted Temperature Range - x prescale value
Interval Timer Mode
Single interval error, free-running (note 3)
± 6t
Cumulative interval error, free-running (note 3)
0
Error between two timer reads (note 2)
± (tpsc + t to - (tpsc + t to - (tpsc + 7t to - 8t
Load timer to stop timer error
+ t to - (tpsc + 2t to - (tpsc + 8t to - 9t
(notes 1, 3)
Pulse Width Measurement Mode
Measurement accuracy (note 4)
Minimum pulse width of EXT INT pin
A special situation exists when reading the interrupt
control port (with an IN or INS instruction). The
accumulator is not loaded with the content of the ICP;
instead, accumulator bits 0 through 6 are loaded with Os,
while bit 7 is loaded with the logic level being applied to
the EXT INT pin, thus allowing the status of EXT INT to
be determined without the necessity of servicing an
external interrupt request. This capability is useful in
establishing a high-speed polled handshake procedure or
for using EXT INT as an extra input pin if external
interrupts are not required and the timer is used only in
the interval timer mode.
The rate at which the timer is clocked in the interval
timer mode is determined by the frequency of an internal
clock and by the division value selected for the
prescaler. (The internal clock operates at one-half the
external time base frequency.) If ICP bit 5 is set and bits
6 and 7 are cleared, the prescaler divides by two.
Likewise, if bit 6 or 7 is individually set, the prescaler
divides by 5 or 20, respectively. Combinations of bits 5,
6, and 7 may also be selected. For example, if bits 5 and
7 are set while 6 is cleared, the prescaler divides by 40.
Thus, possible prescaler values are ... 2, ... 5, ... 10, ... 20,
-+- 40, +100, and + 200.
+ t to - (tpsc + 2t
2t
2t
Not••
1. All times that entail loading, starting, or stopping the limer are
referenced from the end of the last machine cycle of the OUT or
OUTS Instruction.
2. All limes that entail reading the timer are referenced from the end of
the last machine cycle of the IN or INS instruction.
3. All times that entail the generation of an interrupt request are
referenced from the start of the machine cycle in which the
appropriate interrupt request latch is set. Additional time may elapse if
,the interrupt request occurs during a privileged or multi-cycle
.instruction.
4. Error may be cumulative if operation is repetitively performed.
Any of three conditions causes the prescaler to be reset:
when the timer is stopped by clearing the ICP bit 3, on
execution of an output instruction to port 7 (the timer is
assigned port address 7), or on the trailing edge
transition of the EXT INT pin when in the pulse width
measurement mode. These last two conditions are
explained in more detail below.
The desired timer mode, prescale value, starting and
stopping the timer, active level of EXT INT pin, and local
enabling or disabling of interrupts are selected by
outputting the proper bit configuration from the
accumulator to the interrupt control port (port 6) with an
OUT or OUTS instruction. Bits within the interrupt
control port are defined as follows:
An OUT or OUTS instruction to port 7 loads the content
of the accumulator to both the timer and the 8-bit
modulo-N register, resets the prescaler, and clears any
previously stored timer interrupt request. As previously
noted, the timer is an 8-bit down counter that is clocked
by the prescaler in the interval timer mode and in the
pulse width measurement mode_ The prescaler is not
used in the event counter mode. The modulo-N register
is a buffer whose function is to save the value that was
most recently output to port 7. The modulo-N register is
used in all three timer modes.
4-52
Fig. 4 Timer/Interrupt Functional Diagram
FROM INTERRUPT CONTROL PORT
82 I B4
B3
B5
B6
80 181
B7
TIMER
INTERRUPT-
~LOADS
INTERRUPT
VECTOR H '020' UPON
COMPLETION OF THE
FIRST NON·PRIVILEGED
INSTRUCTION
...
ACKNOWLEDGE
c:n
TIMER
INTERRUPT
'"
"T1
'I' =PULSE WIDTH MODE
(0)
x prescale value
Noles
1. All times that entail loading, starting, or stopping the timer are referenced from the end of the last machine cycle of the OUT or OUTS instruction.
2. All times that entail reading the timer are referenced from the end of the last machine cycle of the IN or INS instruction.
3. All times that entail the generation of an interrupt request are referenced from the start of the machine cycle in which the appropriate interrupt request
latch is set. Additional time may elapse if the interrupt request occurs during a privileged or multi-cycle instruction.
4. Error may be cumulative if operation is repetitively performed.
4-73
F3872/F38L72
the contents of the ICP; instead, accumulator bits 0
through 6 are loaded with zeros, while bit 7 is loaded
with the logic level being· applied to the EXT INT pin,
thus allowing the status of the EXT INT pin to be
determined without the necessity of servicing an external
interrupt request. This capability is useful in establishing
a high-speed, polled handshake procedure or for using
EXT !NT as an extra input pin if external interrupts are
not required and the timer is used only in the interval
timer mode.
An OUT or OUTS instruction to port 7 loads the contents
of the accumulator into both the timer and the 8·bit
modulo-N register, resets the prescaler, and clears any
previously stored timer interrupt request. As previously
noted, the timer is an 8-bit down counter that is clocked
by the prescaler in the interval timer mode and in the
pulse width measurement mode. The prescaler is not
used in the event counter mode. The modulo-N register
is a buffer whose function is to save the value that was
most recently output to port 7. The modulo-N register is
used in all three timer modes.
The rate at which the timer is clocked in the interval
timer mode is determined by the frequency of an internal
q, clock and by the division value selected for the
prescaler. (The internal clock operates at one-half the
external time base frequency.) If ICP bit 5 is set and bits
6 and 7 are cleared, the prescaler divides q, by 2.
Likewise, if bit 6 or 7 is individually set, the prescaler
divides q, by 5 or 20, respectively. Combinations of bits 5,
6, and 7 may also be selected. For example, if bits 5 and
7 are set while bit 6 is cleared, the prescaler divides by
40. Thus, possible prescaler values are: -;- 2, -;- 5, -;- 10,
-;- 20, -;- 40, + 100, and -;- 200.
Interval Timer Mode - When ICP bit 4 is cleared (logic 0)
and at least one prescale bit is set, the timer operates in
the interval timer mode. When bit 3 of the ICP is set, the
timer starts counting down from the modulo-N value.
After counting down to H '01', the timer returns to the
modulo-Nvalue at the next count. On the transition from
H '01' to H' N', the timer sets a timer interrupt request
latch. Note that the interrupt request latch is set by the
transition of H 'N' in the timer, thus allowing a full 256
counts if the modulo-N register is preset to H'OO'. If bit
1 of the ICP is set, the interrupt request is passed to the
CPU section of the F3872. However, if bit 1 of the ICP is
a logic 0, the interrupt request is not passed, but the
interrupt request latch remains set. If ICP bit 1 is
subsequently set, the interrupt request is then passed to
the CPU. Only two events can reset the timer interrupt
request latch: when the timer interrupt request is
acknowledged by the CPU, or when a new load of the
modulo-N register is performed.
Any of three conditions cause the prescaler to be
reset: whenever the timer is stopped by clearinglCP
bit 3, on execution of an output instruction to port 7 (the
timer is assigned port address 7), or on the trailing edge
transition of the EXT INT pin when in the pulse width
measurement mode. These last two conditions are
explained in the following paragraphs.
Fig. 4
Timer and Interrupt Control Port Block Diagram
PRESCALER
EXTERNAL
TIME
BASE
CLOCK
2, 5, 10, 20, 40, 100, or 200
INT
REO
INTERRUPT
CONTROL
PORT
(PORT 6)
l
3
EVENT COUNTER MODE ____
+ 2 PRESCALE
----
..;. 5 PRESCAlE
+ 10 PRESCALE
+20 PRESCALE
+40 PRESCALE
+ 100 PRESCALE
+200 PRESCALE
-4--
0
____
0
_
1
____
1
____·1
_
1
l_ L L
2
1
0 . . - BIT NO.
I
EXTERNAL INTERRUPT ENABLE
I
TIMER INTERRUPT ENABLE
~ EXT INT ACTIVE LEVEL
- - - - . . START/STOP TIMER
L _________________
PULSE WIDTHIINTERVAl TIMER
4-74
EXT
INT
Fig. 5
Timer/Interrupt Functional Diagram
FROM INTERRUPT CONTROL PORT
82 I 84
85
83
8.
80 I 81
87
'1' SELECTS
TIMER
INTERRUPT'
TIME
BASE
'LOADS INTEARUPT
VECTOR H '020' UPON
COMPLETION OF THE
FIRST NON- PRIVILEGED
INSTRUCTION
..,.
ACKNOWLEDGE
TIMER
INTERRUPT
.:...
01
"'TI
'I' = PULSE WIDTH MODE
Co)
011
.......
.IL
~
"'TI
EXTERNAL
INTERRUPT
INPUT
Co)
011
r-
...JL
.......
N
t LOADS INTERAUPT
VECTOR H 'DAD' UPON
COMPLETION OF THE
FIRST NON· PRIVILEGED
INSTRUCTION
''01'
ACKNOWLEDGE
EXTERNAL
INTERRUPT
II
F38721F38L72
Consider an example in which the modulo-N register
is loaded with H '64' (decimal 100). The timer interrupt
request latch is set at the 100th count following the
timer start, and the timer interrupt request latch is
repeatedly set on precise 100-count intervals. If the
prescaler is set at + 40, the timer interrupt request
latch is set every 4000 clock periods; For a 2 MHz
clock (4 MHz time base frequencyj, this produces
2 ms intervals.
Pulse Width Measurement Mode - When ICP bit 4 is set
(logiC 1) and at least one prescale bit is set, the timer
operates in the pulse width measurement mode. This '
mode is used for accurately measuring the duration of a
pulse applied to the EXT INT pin. The timer is stopped
and the prescaler is reset when the EXT INT pin is at its
inactive level. The active level of EXT INT is defined by
ICP bit 2: if cleared, EXT INT is active-low; if set, EXT
INT is active-high. If ICP bit 3 is set, the prescaler and
timer start counting when EXT INT transfers to the active
level. When EXT INT returns to the inactive level, the
timer stops, the prescaler resets, and, if ICP bit 0 is set,
an external interrupt request latch is set. (Unlike timer
interrupts, external interrupts are not latched if the ICP
interrupt enable bit is not set.)
The range of possible intervals is from 2 to 51,200
clock periods (1 p,s to 25.6 ms for a 2 MHz clock).
However, approximately 50 periods is a practical
minimum because the time between setting the interrupt
request latch and the execution of the first instruction of
the interrupt service routine is at least 29 periods (the
response time is dependent upon how many privileged
instructions are encountered when the request occurs).
To establish time intervals greater than 51,200 clock
periods is simply a matter of using th~ timer interrupt
service routine to count the number of interrupts, saving
the result in one or more of the scratchpad registers
until the desired interval is achieved. With this
technique, virtually any time interval, or several time
intervals, may be generated.
As in the interval timer mode, the timer may be read at
any time, or may be stopped at any time by clearing ICP
bit 3, the prescaler and the ICP bit 1 function as
previously described; the timer still functions as an 8-bit
binary down counter with the timer interrupt request
latch being set on the timer's transition from H '01' to
H' N' (modulo-N value). Note that the EXT INT pin has
nothing to do with loading the timer; its action is that of
automatically starting and stopping the timer and of
generating external interrupts. Pulse widths longer than
the prescaler value times the modulo-N value are easily
measured by using the timer interrupt service routine to
store the number of timer interrupts in one or more
scratch pad registers.
The timer may be read at any time and in any mode using
an input instruction (IN 7 or INS 7); this may take place
on-the-fly without interfering with normal timer operation.
The timer may also be stopped at any time by clearing
bit 3 of the ICP. The timer holds its current contents
indefinitely and resumes counting when bit 3 is again
set. The prescaler, however, is reset whenever the timer
is stopped; thus, a series of starts and stops results in a
cumulative truncation error.
As for accuracy, the actual pulse duration is typically
slightly longer than the measured value because the
status of the prescaler is not readable and is reset when
the timer is stopped. Thus, for maximum accuracy, it is
advisable to use a small-division setting for the
prescaler.
For a free-running timer in the interval timer mode, the
time interval between any two interrupt 'requests may be
in error by ± 6 clock periods, although the cumulative
error over many intervals is zero. The prescaler and timer
generate precise intervals for setting the timer interrupt
request latch, but the time-out may occur at any time
within a machine cycle. (There are two types of machine
cycles: short cycles that consist of four clock periods,
and long cycles that consist of 6 clock periods.) In the
multi-chip F8 family, there is a signal referred to as the
write clock, which corresponds to a machine cycle.
Interrupt requests are synchronized with the internal
write clock, thus giving rise to the possible ± 6 error.
Additional errors may arise due to the interrupt request
occurring while a privileged instruction or multi-cycle
instruction is being executed. Nevertheless, for most
applications, all of the above errors are negligible,
especially if the desired time interval is greater than
1 ms.
When ICP bit 4 is cleared and all
prescale bits (ICP bits 5, 6, and 7) are cleared, the timer
operates in the event counter mode. This mode is used
for counting pulses applied to the EXT INT pin. If ICP bit
3 is set, the timer decrements on each transition from
the inactive level to the active level of the EXT INT pin.
The prescaler is not used in this mode but, as in the
other two timer modes, the timer may be read at any
time, or may be stopped at any time by clearing ICP bit
3; ICP bit 1 functions are previously described, and the
timer interrupt request latch is set on the timer's
transition from H '01' to H 'N' (modulo-N value).
Event Counter Mode -
Normally, ICP bit 0 should be kept cleared in the event
counter mode; otherwise, external interrupts are
generated on the, transition from the inactive level to the
active level of the EXT INT pin.
4-76
F3872/F38L72
guarantee that the power-on clear will operate under
every power-up condition.
For the event counter mode, the minimum pulse width
required on the EXT INT pin is 2 q, clock periods, and the
minimum inactive time is 2 q, clock periods; therefore,
the maximum repetition rate is 500 Hz.
The power-on clear circuitry contains on-Chip sensors to
monitor various conditions. The following conditions
must be satisfied before the power-reset sequence is
allowed to start:
External Interrupts
When the timer is in the interval timer mode, the EXT INT
pin is available for non-timer-related interrupts. If ICP bit
o is set, an external interrupt request latch is set when
there is a transition from the inactive level to the active
level of the EXT INT pin (EXT INT is an edge-triggered
input). The interrupt request is latched until either
acknowledged by the CPU or ICP bit 0 is cleared (unlike
timer interrupt requests, which remain latched even when
ICP bit 1 is cleared). External interrupts are handled in
the same fashion when the timer is in the pulse width
measurement mode or in the event counter mode, except
that in the pulse width measurement mode the external
interrupt request latch is set on the trailing edge of the
EXT INT input; that is, on the transition from the active
level to the inactive level.
1. Supply voltage must be above a certain value, typically
+ 3 V to + 4 V.
2. The clocks of the device must be functioning.
3. The substrate bias must reach a certain level.
All three conditions must be met before the power-on
clear circuitry initiates a reset cycle. However, these
conditions can be satisfied even with a supply voltage of
as low as 3 volts. The latest versions of the F3872 have a
modified delay circuit that gives a typical delay of 500 p's
(with a 4 MHz crystal) after the above conditions are met.
This is an improvement over the earlier F3872 versions.
Since the F3872 is only guaranteed to operate at a
supply voltage of 4.5 V or greater, the user must ensure
that the supply voltage is at least 4.5 V when the F3872
initiates the reset cycle. For power supplies having a
slow rise time, an external RC network can be converted
to the external reset input of the F3872 to hold the
device in a reset state long enough to allow the power
supply to reach a voltage of 4.5 V.
Interrupt Handling
When either a timer or an external interrupt request is
communicated to the CPU section of the F3872, it is
acknowledged and processed at the completion of the
first non·privileged instruction if the interrupt control bit
of the status register is set. If the interrupt control bit is
not set, the interrupt request continues either until the
interrupt control bit is set and the CPU acknowledges
the interrupt or until the interrupt request is cleared as
previously described.
+5V
R
If there are a timer interrupt request and an external
interrupt request when the CPU starts to process the
requests, the timer interrupt is handled first.
EXTERNAL RESET
F3872
When an interrupt is allowed, the CPU requests that the
interrupting element pass its interrupt vector address to
the program counter via the data bus. The vector address
for a timer interrupt is H '20'; the vector address for an
external interrupt is H 'DAD'. After the vector address is
passed to the program counter, the CPU sends an
acknowledge signal to the appropriate interrupt request
latch, which clears that latch. The execution of the
interrupt service routine then commences. The return
address of the original program is automatically saved in
the stack register, P.
External Reset
When the RESET input is low, the contents of the
program counter are pushed to the stack register and the
program counter and the ICB of the status register are
cleared. The original stack register contents are lost. As
with power-on clear, ports 4, 5, 6, and 7 are loaded with
H' 00'. The contents of all other registers and ports are
unchanged. When RESET is high, the first program
instruction is fetched from ROM location H '0000'.
Power·On Clear
The F3872 contains power-on clear circuitry to
automatically reset the internal logic following the
application of external power. Since many variations
of power supply circuitry exist, Fairchild cannot
Test Logic
SpeCial test logic is implemented to allow access to the
internal main data bus for test purposes.
4-77
•
F38721F38L72
In normal operation, the TEST pin is unconnected or is
connected to ground. When TEST is placed at a level of
from 2.8 V to 3.0 V, port 4 becomes an output of the
internal data bus and port 5 becomes a wired-OR input to
the internal data bus. The data appearing on the port 4
pins is logically true, whereas input data forced on port 5
must be logically false. When TEST is placed at a high
level (8.8 V to 9.0 V), the ports act a~ described above
and, additionally, the program ROM is prevented from
driving the data bus. In this mode, operands and
instructions. may be forced externally through port 5
instead of being accessed from the program ROM. When
TEST is in either the TTL state or the high state, STROBE
ceases its normal function and becomes a cycle clock
(identical to the F8 multi-chip system write clock, except
inverted).
Two modes are recommended for powering .oown. In the
first mode (see Figure 6A), the processor must be
interrupted early enough to save all necessary data
before the Vee falls below the minimum level. After the
save is done, the RESETIRAMPRT pin can fall. This
prevents any further RAM accesses; Voo may then fall.
The second mode (see Figure 68) may be used if a
special save data routine is not needed. External
interrupt need not be used, and the only requirement to
save the RAM data is that RAMPRT be low for Voo drops
below 4.5 V. For example, if a few key variables are to be
stored in power-down RAM and it is desired that these
be saved during a loss of power, two copies of each
variable are kept with an associated flag in the powerdown RAM; thus, no interrupt and save routine is
necessary. The method of updating a variable is
as follows:
Timing complexities render the capabilities associated
with the TEST pin impractical for use in a user
application, but these capabilities are sufficient to
enable Fairchild to implement a rapid method for
thoroughly testing the F3872.
.
Clear Flag Word 1
Update Variable (Copy 1)
Set Flag Word 1
Clear Flag Word 2
Update Variable (Copy 2)
Set Flag Word 2
Standby Power.Option
If the standby power option is not selected, bits 0 and 1
of port 0 can be read from and written to. If the standby
power-down option is selected, port 0 bit 1. is readable
only; bit 0 remains both readable and writeable via
software, although it is not connected to a package lead.
The standby power source {Vsel is connected to pin 4. (A
0.01 I'F capacitor must be connected to pin 3; the
purpose of this capacitor is to decouple noise coupled to
the substrate of the circuit when Voo is switched off and
on.) Nickel-cadmium batteries (typical voltage of three
series cells is 3.6 V) are recommended for use as the
standby power source, since the F3872 can automatically
trickle charge three such cells. If more than three cells in
series are used, a charging circuit must be provided
outside the F3872. When the RESET/RAMPRT pin is
brought low, the standby RAM (64 8-bit words in PO/DC
address spaces 4032 to 4096 10, or FC0 16 to FFFlel is
disabled from being read from or written to. The RAM
itself is also switched from Voo power to the VSB power..
Execution may terminate at any time, even during the
update of a variable of flag word, causing that byte in
scratchpad to be "bad" data. There is always a "good"
data byte that contains either the most recent or nextmost recent value .of the variable. Any copy of the
variable in which the flag word is set is a good data byte.
While this method significantly encumbers the data
storage process, it eliminates the need for a power fail
interrupt, which reduces external circuitry and leaves the
external interrupt pin completely free for other uses.
In either power-down mode, the RESETIRAMPRT Signal
should be held low until Voo is above the minimum level
when power returns.
4-78
F3872/F38L72
Fig. 6
Standby Power Option Modes
A. Data Save Routine, Vsa .. 3.2 V
VDD SUSTAINED BY CAPACITOR OR
BATTERY UNTIL A1mIIT BROUGHT LOW
VDD----------~------~
MAIN POWER SUPPLY
FAILURE DETECTED
--_/
-_/
1
EXT INT - - - - - - - - - \
RESETIRAMPRT
-----------~-----~
DATA SAVE
MUST BE DONE
HERE
B. No Save Routine, Vsa .. 3.2 V
VDD------------~
MAIN POWER
FAILURE DETECTED
RAMPRTIRESET-------------~~~
,
/
_ _ _ _ _ _ _, _ - - - - -....
____________________
4·79
~~----------------------~~
II
F3872/F38L72
F3872 Clocks
Fig. 7
F3872 Clock Configurations
External Mode
Crystal Mode
The time bases for the F3872 may originate from one of
four external sources; the four external configurations
are shown in Figure 7. There is an internal 26.5 pF
capacitor between XTL 1 and GND, and also between
XTL2 and GND. Thus, external capacitors are not
required. In all external clock modes, the external time
base frequency is divided by 2 to form the internal
clock.
OPEN
ATCUT1-4MHz
EXTERNAL
CLOCK
+
Instruction Set
LC Mode
RC Mode
vee
The F3872 executes the entire instruction set of the
multi·chip Fa family (F3850 family), as shown in Tab/e 3.
Of course,the STORE instruction only accesses memory
in locations FFO-FFF (the data counter, however, is
incremented each time STORE is executed).
~R
*
~
CEXTERNAL
(OPTIONAL-CAN
BE OMITTED)
L_-lf-_J
CEXTERNAL (OPTIONAL)
A summary of programmable registers and ports is given
in Figure 8.
Also, for convenient reference, a programming model of
the F3872 is given in Figure 9.
Mask Options
Minimum R=4kO
Minimum L=O.l mH
Minimum Q=40
C = 20.5 pF ± 2.5 pF + CEXTERNAL
Maximum CEXTERNAL = 30 pF
1
f M1N ", 1.1 RC+65ns
C,,10pF±1.3pF+CEXTERNAL
1
The ROM array may contain object program code and/or
tables of nonvarying data. Every F3872 is implemented
using a custom mask that specifies the state of every
ROM bit, as well as certain address mask options that
are external to the ROM array. The following mask
options are specified:
f MAX '" 1.0RC+15ns
1. The 1024, 2048, 3072, or 4096 bytes of ROM storage.
This reflects programs and permanent data tables
.
stored in the PSU memory.
2. Input/output ports can be any of the following three
configurations:
a. Standard pull-up
b. Open drain
c. Direct drive
3. Input/output ports 0 and 1 can be specified either
cleared or unaltered following an external reset.
4. External interrupt and external reset can be specified
to have or omit an internal pull-up resistor.
5. The I/O port output option choices are: the standard
pull-up (option A), the open drain (option B), and the
driver pull-up (option C).
1
f '" 2".v'[C
Example with CEXTERNAL = 0
Example with CEXTERNAL =
R,,15kO±5%
f '" 2.9 MHz± 26%
L,,0.3mH±10%
f '" 3.0 MHz± 10%
°
HP2644/HP2645 cartridge (Formulator format only). Other
options must be specified on the Fairchild ROM Code
Entry Form, available from a Fairchild representative.
Supplementary Notes
For total software compatibility when expanding into a
multi-chip configuration, the F3871 Peripheral
Input/Output circuit should be used. The F3871 has the
same improved timer (binary count, readable, and three
modes of operation) and ready strobe outputs as
the F3872.
The interrupt control bit of the status register is
automatically reset when an interrupt request is
acknowledged. It is then the programmer's responsibility
to determine when the ICB is again to be set (by
executing the E1 instruction). This action prevents an
interrupt service routine from being interrupted unless
the programmer so desires.
The format for mask options must be submitted to
Fairchild Microprocessor Division before device
manufacture. The data to be stored in permanent
memory may be submitted in the form of an EPROM or
4-80
F3872/F38L72
Table 3
F3872 Instruction Set
Accumulator Group Instructions
Operation
Add Carry
Add Immediate
AND Immediale
Clear
Compare Immediale
Complemenl
Exclusive OR Immediate
Increment
Load Immediale
Load Immediate Shari
OR Immediale
Shift Left One
Shift Left Four
Shift Righi One
Shlfl Righi Four
Mnemonic
OP Code
LNK
AI
NI
CLR
CI
COM
XI
INC
LI
LIS
01
SL
SL
SR
SR
Operand
ii
ii
ii
ii
ii
i
ii
1
4
1
4
Function
ACC-(ACC)+ CRY
ACC-(ACC) + H'ii'
ACC-(ACC) A H'ii'
ACC-H'OO'
H'ii' + (ACC) + 1
ACC-(ACC) .. H'FF'
ACC-(ACC) .. H'ii'
ACC-(ACC)+ 1
ACC-H'ii'
ACC-H'Oi'
ACC-(ACC) V H'ii'
SHIFT LEFT 1
SHIFT LEFT 4
SHIFT RIGHT 1
SHIFT RIGHT 4
Machine
Code
Bytes
Cycles
19
24 ii
21 ii
70
25 ii
18
23 ii
IF
20 ii
7i
22 il
13
15
12
14
1
2
2
1
2
1
2
1
2
1
2
1
1
1
1
1
2.5
2.5
1
2.5
1
2.5
1
2.5
1
2.5
1
1
1
1
Status Bits
OVF ZERO CRY
SIGN
1/0
1/0
0
1/0
1/0
1/0
110
1/0
0
110
1/0
1/0
110
0
0
1/0
110
1/0
1/0
1/0
1/0
0
0
.1/0
1/0
1/0
1/0
110
110
110
110
1
1
-
-
--
0
0
0
0
0
110
110
110
110
110
0
0
0
0
0
-
-
-
Branch Instructions
(In All Conditional Branches, PO (PO) + 2 if the Test Conditions Are Not Met. Execution Is Complete in 30 Cycles.)
Operation
Branch
Branch
Branch
Branch
on
on
on
on
Carry
Posilive
Zero
True
Mnemonic
OP Code
Operand
BC
BP
BZ
BT
aa
aa
aa
I,aa
Function
PO-((PO)+
PO-((PO)+
PO-((PO)+
PO-((PO)+
lJ+
lJ+
lJ+
lJ +
H'aa'
H'aa'
H'aa'
H'aa'
if
if
if
if
CRY= 1
SIGN= 1
ZERO= 1
any lesl is Irue
Machine
Code
Byte.
Cycle.
OVF
82 aa
81 aa
84 aa
81 aa
2
2
2
2
3.5
3.5
3.5
3.5
-
StatuI Bltl
ZERO CRY
SIGN
--
-
-
-
--
-
-
-
-
I = TEST CONDITION
I 22 I 21 I 2° I
IZERO ICRY ISIGN I
Branch
Branch
Branch
Branch
Branch
if
if
if
if
if
Negalive
No Carry
No Overflow
Nol Zero
False Tesl
BM
BNC
BNO
BNZ
BF
aa
aa
aa
aa
I,aa
PO-((PO)+
PO-((PO)+
PO-((PO) +
PO-((PO)+
PO-((PO)+
lJ+
lJ+
lJ +
lJ+
lJ+
H'aa' if SIGN=O
H'aa' if CARRY"O
H'aa' if OVF = 0
H'aa' if ZERO=O
H'aa' if all false lesl bils
91 aa
92 aa
98 aa
94 aa
91 aa
2
2
2
2
2
3.5
3.5
3.5
3.5
3.5
8F aa
2
90 aa
29 aaaa
2
2.5
2.0
3.5
5.5
-
-
-
-
-
-
-
-
-
--
I = TEST CONDITION
I 23 I 22 I 21 I 2° I
I OVF IZERO I CRY I SIGN I
Branch if ISAR (Lower) 7
BR7
aa
Branch Relalive
Jump'
BR
JMP
aa
aaaa
PO-((PO)+ lJ+ H'aa' if ISARL,,7
PO-(PO)+2 if ISARL= 7
PO-((PO) + lJ + H'aa'
PO-H'aaaa'
3
-
-
Memory Reference Instructions ((n All Memory Reference Instructions , the Data Counter (s Incremented DC- DC.1 )
Operation
Add Binary
Add Decimal
AND
Compare
Exclusive OR
Load
Logical OR
Siore
Mnemonic
OP Code
AM
AMD
NM
CM
XM
LM
OM
ST
Function
Operand
ACC-(ACC) + ((DC)]
ACC-(ACC)+ ((DC)]
ACC-(ACC) A ((Dc)J
[(DC)] + (ACC) + 1
ACC-(ACC) .. ((DC)J
ACC-((Dc)J
ACC-(ACC) V ((DC])
(DC)-(ACC)
• Pnvlleged ,"slruchon
Note
JMP and PI change accumulalor conlenls 10 Ihe high byle address.
4·81
Machine
Code
Byte.
Cycles
88
89
8A
8D
8C
16
86
17
1
1
1
1
1
1
1
1
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
StatuI Bits
OVF ZERO CRY
SIGN
110
110
110
110
110
110
110
0
110
110
110
110
110
110
-
-
-
0
110
0
-
-
110
110
0
110
0
-
0
-
110
•
F38721F38L72
Table 3
F3872 Instruction Set (Cont.)
Address Register Group Instructions
Ope... tlon
Mnemonic
OP Code,
Add to Data Counter
Call to Subroutine
Call to Subroutine Immediate
Exchange DC
Load Data Counter
Load Data Counter
Load DC Immediate
Load Program Counter
Load Stack Register
Return From Subroutine
Store Data Counter
Store Data Counter
Store Stack Register
ADC
PK'
PI'
XDC
LR
LR
DCI
LR
LR
POP'
LR
LR
LR
Ope... nd,
aaaa
DC,a
DC,H
aaaa·
PO,a
P,K
a,DC
H,DC
K,P
Function "
DC-(DC)+ (ACC)
P-(PO); POU-(r12); PL-(r13)
P-(P); PO- H'aaaa'*
DC-DC1
DCU-(r14); DCL-(r15)
DCU-(r10); DCL-(r11)
DC-H'aaaa'
POU-(r14); POL-(r15)
PU-(r12); PL-(r13)
PO-(P)
r14-(DCU); r15-(DCL)
r10-(DCU); r11-(DCL)
r12-(PU); r13-(P)
Machine
Cod.
Byte.
Cycle.
8E
OC
28 aaaa
2C
OF
10
2Aaaaa
00
09
1C
OE
11
08
1
1
3
1
1
1
3
1
1
1
1
1
1
2,5
4
6.5
2
4
4
6
4
4
2
4
4
4
Machine
Code
Byte.
Cycle.
Cr
Dr
3r
4r
00
01
02
03
5r
04
05
06
07
Fr
Er
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
1,5
1
1
1
1
1
1
1
1
1
1
1
1
Machine
Cod.
Byte.
Cycle.
11'.
1B
26 aa
Aa
OB
01101a"
01100a"
10
2B
27 aa
Ba
01'.
1E
1
1
2
1
1
1
1
1
1
2
1
1
1
2
2
4
4'"
1
1
1
2
1
4
4'"
1
1
Status Bits
OVF ZERO CRY SIGN
-,
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-'
-
-
-
-
-
-
~
--,
-
Scratchpad Register Instructions (Refer to Scratch pad AddreSSing Modes)
Operation
Mnemonic
OPCode
Add Binary
Add Decimal
Decrement
Load
Load
Load
Load
Load
Load
Load
Load
Load
Load
ANp
Exclusive OR
AS
ASD
Ope ...nd
LR
LR
LR
LR
LR
LR
LR
LR
LR
LR
NS
XS
r
'r
r
A,r
A,KU
A,KL
A,aU
A,aL
r,A
KU,A
KL,A
aU,A
aL,A
r
r
Mnemonic
OP Cod.
Ope...nd
oS
Function
ACC-(ACC)+(r)
ACC-(ACC)+(r)
r-(r)+ H'FF'
ACC-(r)
ACC-(r12)
ACC-(r13)
ACC-(r14),
ACC-(r15)
r-(ACC)
r12-(ACC)
r13-(ACC)
r14-(ACC)
r15-(ACC)
ACC-(ACC) A (r),
ACC-(ACC) .. (r)
Status Bit.
OVF ZERO CRY SIGN
i/O
flo
110
1/0
110
110
1/0
1/0
1/0
1/0
1/0
1/0
-
-
-
-
-
-
-
0
0
-
-
-
-
-
-
1/0
1/0
0
0
1/0
1/0
-
-
-
-
Miscellaneous Instructions
Op.... tion
Disable Interrupt
Enable: Interrupt'
Input
Input Short
Load ISAR
Load ISAR Lower
Load ISAR Upper
Load Status Regis,te,r: '
No-Operation
Output ,"
Output Short
Store ISAR
StQre Status Register
01
EI
IN
INS
, LR
LISL
,LlSlJ
LR
NOP
OUT
OUTS
LR
LR
aa
a
IS,A
a
a
W,J
aa
a
A,IS
J,W
Function
RESET ICB
SET ICB
ACC-(INPUT PORT aa)
ACC-(INPUT PORT a)
ISAR-(ACC)
"ISARL-a
ISARU-a
W-(r9)
PO-(PO)+ 1
OUTPUT PORT aa-(ACC)
OUTPUT PORT a-(ACC) ,
ACC-(ISAR)
r9-(W)
! 'Privileged
instructIon
','3·bit octal digit
.. 'Two machine cycles for CPU ports
*Contents of ACC destroyed
4-82
Status Bits
OVF ZERO CRY SIGN
-
-
0
0
110
110
1/0
-
-
-
-
110
-
-
0
0
-
1/0
-
1/0
' 110
-
-
110
-
-
F3872/F38L72
Table 3
F3872 Instruction Set (Cont.)
Nota.
Each lower case character represents a hexadecimal digit.
Each cycle equals four machine clock periods.
lower case denotes variables specified by the programmer.
K
Kl
KU
PO
POL
POU
P
Pl
PU
a
al
au
r
W
Function Dallnltons
is replaced by
the contents of
binary ones complement of
+
arithmetic add (binary or decimal)
..
logical OR exclusive
A
logical AND
V
logical OR inclusive
H','
hexadecimal digit
()
(-)
Regllter
a
A
DC
DC1
DCl
DCU
H
i and ii
ICB
Name.
address variable
accumulator
data counter (indirect address register)
data counter 111 (auxiliary data counter)
least significant eight bits of data counter addressed
most significant eight bits of data counter addressed
scratchpad register '10 and 1111
immediate operand
Interrupt control bit
IS
indirect scratchpad address register
ISAR
ISARl
ISARU
indirect scratchpad address register
least significant three bits of ISAR
most significant three bits of ISAR
Scratchpad Addressing Modes (Machine Code Format)
r= C
(hexadecimal) register addressed by ISAR (unmodified)
r= D
(hexadecimal) register addressed by ISAR; ISARl incremented
r= E
(hexadecimal) register addressed by ISAR; ISARl decremented
(no operation performed)
r= F
r = O-B (hexadecimal) register 0 through 11 addressed directly from the
instruction
Status Raglster
no change in condition
110
is set to 1 or 0, depending on conditions
CRY
carry flag
When reading the interrupt control port (port 6), bit 7 of
the accumulator is loaded with the actual logic level
being applied to the EXT INT pin, regardless of the
status of ICP bit 2 (the EXT INT active. level bit); that is, if
the EXT INT pin is at + 5 V, bit 7 of the accumulator is
set to a logic 1, but if the EXT INT pin is at ground,
accumulator bit 7 is reset to logic O.
For the F3872, execution of an INS or OUTS instruction
requires two machine cycles for ports 0 and 1, whereas
ports 4 and 5 require four machine cycles.
When an external reset of the F3872 occurs, PO pushes
into P and the old contents of P are lost. It must be
noted that an external reset is recognized at the start of
the machine cycle and not necessarily at the end of an
instruction. Thus, if the F3872 is executing a multi-cycle
instruction, that instruction is not completed and the
contents of P upon reset may not necessarily be the
address of the instruction that would have been
executed next. It may, for example, point to an
immediate operand if the reset occurred during the
second cycle of an L1 or C1 instruction. Additionally,
several instructions (JMP, P1, PK, LR, PO and 0) as well
as the interrupt acknowledge sequence modify PO in
parts. That is, they alter PO by loading first one part, then
the other, and the entire operation takes more than one
cycle. Should reset occur during this modification
process, the value pushed into P is part of the old PO
(the as-yet unmodified part) and part of the new PO
(already-modified part). Thus, care should be taken
(perhaps by external gating) to ensure that reset does not
occur at an undesirable time if any significance is to be
given to the contents of P after a reset occurs.
In Table 3, the number of cycles shown is "nominal
machine cycles." A nominal machine cycle is defined as
4", clock periods, thus requiring 2,.s for a 2 MHz clock
frequency (4 MHz external time base frequency).
Table 3 also uses the following nomenclature for
register names:
F8 -F3872
PCo= PO
PC 1 = P
DC o= DC
DC 1 = DC1
scratchpad register 119
registers '12 and 1113
register '13
register 1112
program counter
least significant eight bits of program counter
most significant eight bits of program counter
stack register
least significant eight bits of program counter
most significant eight bits of active stack register
registers 1114 and #15
register #15
register '14
scratchpad register (any address through 11)
status register
Program Counter
Stack Register
Data Counter
Auxiliary Data Counter
This nomenclature is used to be consistent with the
assembly language mnemonics.
4·83
•
F38721F38L72
Fig. 8
Programmable Registers and Ports
7
ACCUMULATOR:
I
I
A
1~10121CISI
STA'TUS
REGISTtR W
8YTE ADDRESS
SCRATCHPAD
DEC
I
• 3
INDIRECT
SCAATCHPAO
ADDRESS
REGISTER
0
HEX
f
IS
11
'AU X DATA
COUNTER
I,
11
DC"
HU
10
A
12
Hl
KU
11
8
13
12
C
I.
Kl
13
D
15
OU
I.
Ol
'5
H
I
11
DATA
COUNTER
OCT
0
16
0
DC
16
17
10
20
58
3A
7.
59
38
73
60
3C
7.
61
30
75
62
3E
76
63
3F
77
11
STACK
REGISTER
I
P
11
PROGRAM
COUNTER
I
PO
0
BINARY
TIMER
PORT 7
110 PORT 0
INTERRUPT
CONTROL
PORT
PORT 6
110 PORT 1
110 PORT 4
110 PORT 5
4·84
I
L-
STROBE
Fig. 9
Programming Model
r---------------o>--!I
OUTS 7
ODC
INS·7
EI ~ STATUS,.......LN.
~
DI,
OUTS 6
INS-6
(PO)
ISAR
OUTS P. (P
LISU
0.1.4.5)
INS·P. (P 0,1,4.5)
110
PORTS
(')
5 V VOLTS
LOGIC '0'
ON 110
PINS
SCRATCHPAD
REGISTERS
AUX DATA
COUNTER
....
Q,
m 14
U'1
H
11
U 12
L 13
¥-*I
Q
T1
LR
LR
I'
I.
• (PO)
."
I" (IS)=:-1 I.
Co)
CO
.....
DS·
U1i
PROGRAM
ROM
~
."
~
~
N
Jf
OCTAL
HEX
• These inslructions set status
t
H '000'
EXTERNAL INTERRUPT
INPUT (·5 Y '" LOGIC 1)
RESET transfers P09 to P and
then clears PO, Ica bit of W,
and ports 4, 5, 8, and 7.
tt
The value 01 the extemal interrupt Input Is loaded to
bit 7 of the accumulator (wflh bits 0 through fj loaded
with zeros) when the InstrucHon 'INS 6' Is executed.
This Instruction also sets status.
Sl(De)
PO. P, DC. and DC1 are 12·bit registers.
Note:
The instructions PI and PK are shown in two sequential parts (PI1, P12, and PK1, PK2).
II
RAM
64x'
"FCO"H
TD
"FFP'H
F38721F38L72
Timing Characteristics
The F3872 timing characteristics are described in Table 4
and illustrated in Figures 10 and 11.
Table 4
Timing Characteristics
Signal
Symbol
Characteristic
Min
Max
Unit
tJEX)
Time Base Period, Ail External Modes
250
1000
ns
tEx(H)
External Clock Pulse Width, High
90
700
ns
tEx(L)
External Clock Pulse Width, Low
100
700
ns
q,
tq,
Internal
WRITE
tw
Internal WRITE Clock Period
tdl/O
Output Delay from Internal WRITE Clock
tsllO
Input Setup Time to WRITE Clock
tllos
Output Valid to STROBE Delay
3,&
-1 00
+20
tSl
S'i"FiO'BE Low Time
8t;
-20
+20
tRH
RESET Hold Time, Low
XTL,
XTL2
110
q, Clock Period
2tq,
4tq,
6tq,
STROBE
RESET
EXT INT Hold Time, Inactive Stafe
C IN
Input Capacitance:
1/0 Ports, REm, EXT INT
RAMPRT, TEST
CXTL
Input Capacitance: XTL" XTL 2
1000
1000
3t~
ns
12~
ns
6t~
ns
6tq,
ns
2tq,
23.5
Not••
,. I/O load is 50 pF plus one standard TTL input; STROBE load is 50 pF plus three standard TTL inputs.
2. Specification is applicable when the timer Is in the interval timer mode.
3. TA=2S·C,f=2MHz.
+ 70'C, IIcc'" + 5 II ± '0%, 110 power dissipation s mW, unless otherwise noted.
4. fA" O'C to
4-86
ns
50 pF Plus One
TIL Load
ns
+750
tEH
4 MHz-1 MHz
Short Cycle
Long Cycle
+70
EXT INT Hold Time, Active State
EXTINT
0
Notes
ns
Note 1
To Trigger
Interrupt
To Trigger Timer;
Note 2
7
pF
Unmeasured Pins
Returned to Vss;
Note 3
29.5
pF
Unmeasured Pins
Returned to Vss;
Note 3
F38721F38L72
Fig.10
Timing Diagrams
EXTERNAL CLOCK
INTERNAL
(.~
CLOCK
•
1/0 PORT OUTPUT
EXT INT
{
2~1
E
'CPB'TJ
ICP BIT
IEH
L
::I
Not.
All measurements are referenced to VIL max. VIH min. VOL max, or VOH min
Absolute Maximum Ratings
These are stress ratings only, and functional operation at
these ratings, or under any conditions above those
indicated in this data sheet, is not implied. Exposure to
the absolute maximum rating conditions for extended
periods of time may affect device reliability, and
exposure to stresses greater than those listed may cause
permanent damage to the device.
Voltage on any Pin with Respect to
Ground(Except Open·Drain Pins)
Voltage on any Open·Drain Pin
Power Dissipation
Ambient Temperature Under Bias
Storage Temperature
-1.0V, + 7V
-1.0V,+13.2V
1.5W
O°C, + 70°C
- 55°C, + 150°C
4-87
F38721F38L72
Fig; 11
Port Input/Output Timing Diagrams
A. Input on Port 4 or 5
INTERNAL
WRITE
CLOCK
II OR
INS
OPCODE
FETCHED
PORT DATA
DRIVEN ON TO
DATA BUS
PORT ADDR.
PLACED ON
DATA BUS
PORT PINS
NEXT
OPCODE
FETCHED
------'
·Cycle timing shown for 4 MHz external clock
B. Output on Port 4 or 5
INTERNAL
WRITE
CLOCK
OUT OR
OUTS
OPCODE
FETCHED
PORTADDR.
ON DATA
BUS
NEXT
OPCODE
FETCHED
ACCUMULATOR
CONTENTS
ON DATA BUS
PORT PINS
___
-+-J~~---
STAYS LOW
FOR TWO WRITE
CYCLES
S'i'AOaE
(ACTIVE FOR
PORT 4 ONLY)
II/O·S
5OOn8* MIN
·Cycle timing shown tor 4 MHz external clock
D. Output on Port 0 or 1
C. Input on Port 0 or 1
INTERNAL
llTERNAL
WRITE
CLOCK
WRITE
CLOCK
-1-_.1
PORT PINS _ _ _ _ _
·Cycle timing shown for 4 MHz external clock
·Cycle timing shown for -4 MHz external clock
4-88
F3872/F38L72
DC Characteristics
The dc characteristics of the F3872 are described in
Table 5.
Table 5
Symbol
DC Characteristics
Characteristic
Min
Max
Unit
Conditions
Icc
Power Supply Current
100
rnA
Outputs Open
Po
Power Dissipation
500
mW
Outputs Open
VIHEX
External Clock Input High Voltage
2.4
5.8
V
VILHEX
External Clock Input Low Voltage
-0.3
0.6
V
IHEX
External Clock Input High Current
100
p.A
VIHEX=V OO
IILEX
V IH
External Clock Input Low Current
-100
p.A
VILEX = Vss
Input High Voltage RESET, EXT INT
5.8
V
-0.3
0.8
V
2.0
13.2
V
mA
VIL=O.4V
Note 1
p.A
V IN = 13.2 V
VIN=O.O V
Note 2
-100
-30
p.A
Vo H=2.4 V
VOH= 3.9 V
- 0.1
mA
Vo H=2.4 V
mA
Vo H= 1.5 V
mA
Vo H= 0.7 V
2.0
V IL
Input Low Voltage RESET, EXT INT
VIHOO
Input High Voltage (Open·Drain Ports)
IlL
Input Low Current RESET, EXT INT
-1.6
ILOO
Leakage Current (Open·Drain Ports)
10
- 5.0
10H
Output High Current RESET, EXT INT
10HOO
Output High Current
(Direct·Drive Ports)
-1.5
-8.5
10L
Output Low Current
10HS
RESET and EXT INT Have Internal Schmitt
Triggers Giving Minimum 0.2 V Hysteresis
1.8
mA
VOL =O.4 V
Output High Current (STROBE Output)
-300
p.A
Vo H=2.4 V
10LS
Output Low Current (STROBE Output)
5.0
VIHRPR
RAMPRT Input High Level
1.9
5.8
V
Guaranteed 0.1 V less than V IH for RESET
-0.3
0.4
V
Guaranteed 0.1 V less than VIL for RESET
3.2
5.5
V
6.0
3.7
mA
mA
VsB =5.5 V
VSB = 3.2 V
-15
mA
mA
VSB= 3.8 V
VSB= 3.2 V
600
60
mW
mW
All Pins
Any One Pin, Note 3
VILRPR
RAMPRT Input Low Level
V SB
Standby Voo for RAM
ISB
Standby Current
ICHG
Trickle Charge Available on VSB with
Voo - 4.5 to 5.5 V
POlO
Power Dissipated by I/O Pins
mA
-0.8
Vo L = 0.4 V
Notes
RESET or EXT INT programmed with standard pull·up.
RESET or EXT INT programmed without standard pull·up.
Power dissipation of 110 pins is calculated by l: (Voo - VIL ) (IIILI)+ l: (Voo - VoH )(lIoHI)+ l: (VOL) (I OL )'
TA ; O·C to + 70·C, Voo; + 5 V ± 10%, 110 power dissipation" 100 mW.
1.
2.
3.
4.
4·89
•
F38721F38L72
Ordering Information
Ordereode
Package
Temperature Range·
F3872DC, F38L72DC
Ceramic
C
F3872DL, F38L72DL
Ceramic
L
F3872DM, F38L72DM
Ceramic
M
F3872PC,
C
F38L72PC
Plastic
F3872PL, F38L72PL
Plastic
L
F3872PM, F38L72PM
Plastic
M
'C= Commercial Temperature Range O'C to + 70'C
L= Limited Temperature Range -40'C to +85'C
M = Military Temperature Range - 55'C to + 125'C
4·90
F38700
Central Processing Unit
Advance Product Information
Microprocessor Product
Description
Connection Diagram
The Fairchild F38700 is a complete 8-bit central
processing unit (CPU) for the Fairchild F387XX
microprocessor family. Fabricated with double-ionimplanted, N-channel, silicon-gate technology, the
F38700 has 64 bytes of scratchpad register and an 8-bit
accumulator. It contains interrupt logic to serve the onchip external interrupt, the timer interrupt, and interrupts
from peripherals. It also has a nonmaskable interrupt
input having higher priority than other interrupts. Unlike
the F8 series microprocessor, the F38700 program and
data counters are inside the CPU, and the 16-bit address
bus can address 65K bytes of external memory. Figure 1
is a block diagram of the F38700 CPU.
•
•
•
•
•
•
•
•
•
•
•
8-Bit Word Size
Compatibility with F8 and F387X Software
64-Byte Scratchpad Register
Programmable Binary Timer with Interrupt
External Interrupt
On-Chip Clock Generation
TTL-Compatible Inputs and Outputs
8-Bit Data Bus and 16-Blt Address Bus
Direct Memory Access (DMA) Capability
40-Pin DIP
Nonmaskable Interrupt
Signal Functions
CPU
38700
IAK
BGT
4>
4>W
4-91
F38700
Figure 1 F38700 Block Diagram
....
II
DATA BUS
V
~
0~
r
"-
)
v
STATUS
REGISTER
(W)
ACCUMULATOR
(ACC)
~
k
Iv'
YBUS
MUX
(Y)
~
SHIFT
RIGHT/
LEFT
ADDER
LOGIC
(ALU)
0
~
I
I~
A
I
<: IBI'EiITERNAL
<=
XBUS
MUX
(X)
DATA BUS'
SCRATCH PAD
REGISTERS
(RAM)
¢=
INDIRECT
SCRATCHPAD
ADDRESSING
REG (ISAR)
r-~
PC/DC ADDER
{'r
Vt-
~
II
INSTRUCTIONAL
REGISTER
(lR)
I--
'./"
CONTROL ROM
(CROM)
{'r
PC/DC REGISTER
NMI/F
CONTROL
LOGIC
~
I
I
JI
(ICP)
1/06
(TMR)
1107
D,
4·92
I
~rrv
~
y-
0
~
./
ADDRESS BUS
MUX
lJ
~ERNALADDRESS
BUS'
F38700
Signal Descriptions
The F38700 signals are described in table 1.
Table 1
F38700 Signal Descriptions
Pin No.
Name
Description
7·16
24-29
Address
Active-higH, three-state output signals that form a 16-bit
address bus for up to 64K bytes of memory. The lower eight
bits of the address contain the 1/0 address during an 1/0
instruction.
BGT
19
Bus Grant
An active-low output signal used in conjunction with a bus
request. Indicates to the requesting device that the data and
address buses and the write and read Signals have been set t o
their high-impedance state.
BRO
17
Bus Request
An input signal informing the CPU that another device
requests the control of the memory bus.
20, 38
System Clocks
An output to other devices on the bus for system clocking.
2, 3
Crystal
Connections
Input signals connected to a crystal to drive the internal clock
oscillator.
30-37
Data Lines
Active-high, three-state inputloutput signals that form an 8-bit,
bidirectional data bus.
IAK
4
Interrupt
Acknowledge
An active-low output signal from the CPU to its peripherals
indicating that It Is ready for the Interrlipt. The peripheral
requesting service responds by outputting the upper and lowe
interrupt address vectors on the data bus.
INT REO
39
Interrupt
Request
An active-low Input signal informs the CPU that one of its
peripherals requires service.
6
I/O Enable
An active-low signal indicating that the CPU Is executing an
instruction and that the 1/0 port whose address is the same
as the lower eight bits of the address bus should respond.
Mnemonic
Address
Ao· A15
Bus
Clock
4I,4IW
Crystal
XTL1, XTL2
Data
Do - 0 7
Interrupt
Input/Output
10E
4-93
•
F38700
Name
Description
18
Nonmaskable
Interrupti
Instruction fetch
An external·interrupt, negative·edge·trigger input that cannot
be turned off by software.
Vee
1
Power
+ 5 V (± 10%) power supply input
Vss
Read Enable
21
Ground
o V ground reference
RD
22
Read
An active·low signal that indicates data is to be read out of a
memory location of 1/0 port.
RSTI
40
Reset In
An external reset to the CPU specifying that HEX«I>«I> be
loaded into the program counter.
RSTO
5
. Reset Out
Mnemonic
Nonmaskable
Interrupt
NMI/F
Pin No.
Power
Reset
A synchronous reset output signal from the CPU to the rest of
the system.
Write Enable
WR
23
Write
An active·low signal that indicates data on the data bus is to
be written into a memory location or an 1/0 port.
Mode Fllp·Flop
The MFF is reset to zero when a reset or power·on reset
operation occurs. Resetting the MFF makes all the long
cycles into short cycles and allows the F38700 timing to
again be completely compatible with that of the F3870.
The mode fIIp·flop (MFF) is a special feature of the
F38700 that, when set, reduces INS, OUTS, and interrupt
routines by one long machine cycle (1.5 times the normal
cycle). It should be noted that the OUTS instruction is no
longer privileged when the MFF is set. Table 2 presents
the instructions associated with the MFF.
Table 2.
MFF Instructions
Operation
Mnemonic
Function
Machine
Code
Byte
d,cle
Set MFF
SM
MFF-1
2D
1
1
Reset MFF
RM
MFF-O
2E
1
1
Compare 1/0 F
CPF
(II OF) + (ACe) + 1
2F
1
2.5
4·94
OVF
Status
ZERO CRY
0/1
0/1
0/1
SGN
0/1
F38701
Single-Chip Microcomputer
Advance Product Information
Microprocessor Product
Description
Signal Functions
The Fairchild F38701 Single Chip Microcomputer, a
controller-oriented device, is a complete 8-blt microcomputer on a single MOS integrated circuit. The device
features 2048 bytes of mask-programmable ROM, 64
bytes of scratchpad RAM, a programmable binary timer,
16 bidirectional 110 bits, five analog 110 pins, a zerocrossing detector, seven ac drive pins with phase control
and zero-crossing switching capabilities, a serial 110 port
with block and data gate, and a single + 5 volt power
supply.
•
•
•
•
•
•
•
•
•
•
•
•
•
RESET {
TEST
INTERRUPT
DIGITAL
TIME BASE {
84 x 8 Scratchpad Memory
Programmable Timer
External Interrupt
2K x 8 ROM
Two 8·Blt Parallel Digital 1/0 Channels
One Handshake Serial Digital 1/0 Channel
Five Analog 110 Channels
Seven AC Power Control Outputs with Phase Control
and Zero·Crosslng Switching Capabilities
Real-Time Counter
Programmable Interrupt Vector
4O·Pln Package
Single + 5 V Power Supply
Crystal, LC, RC, and Extemal Clock Modes
POWER (
CONTROL
ZERO CROSSING
POWER {
F38701 Slngle·Chlp Microprocessor
SIGNAL DESCRIPTIONS
Mnemonic
Name
Description
Analog Lines
Five bidirectional analog lines that are used either as AID inputs or as
DIA outputs.
Digital Lines
Bidirectional lines that are individually used as TTL-compatible inputs or
as latched outputs.
Analog
AIOo - AI04
Digital
0100 - DlO15
4-95
•
F38701
Mnemonic
Power
Name
Description
Vee
Power Supply
+5V(±10%)
Vss
Ground
Digital ground
VAA
Ground
Analog ground
Power Control
Lines
Seven output drivers that may be used to control loads in the zerocrossing or phase control modes.
External Interrupt
An external interrupt input whose active state is software-programmable
It is also used with the timer for pulse width measurement and event
counting.
RST
Reset
An external reset input that, when pulled low, resets the F38701. When
allowed to go high, the F38701 begins program execution at program
location H'OOOO'.
TEST
Test Circuit
An input used only in testing the F38701. For normal circuit functions
this pin is unconnected or grounded.
SOC
Serial Data Clock
Bidirectional signal that clocks data in and out of the serial data port;
one bit of data is shifted in our out for each data clock pulse.
SOT
Serial Data
A bidirectional serial data line that shifts data in and out, least
significant bit first, synchronous with the data clock.
STE
Serial Data Gate
When the bidirectional data gate is high, both the data clock and the
serial data port are enabled.
Time Base
The time base inputs to which a crystal (1-4 MHz), LC network, RC
network, or an external Single-phase clock are connected.
Zero Crossing
Input
An input signal that senses zero crossings. This Signal is used to sense
the 50/60 Hz line or as an external sensor input.
Power Control
ACo - ACs
Reset Test Interrupt
INT
Reset Test Interrupt
Serial Data
Time Base
XL1
XL2
Zero Crossing
ZC
4-96
F38701
Serial Port
AC Output Control
The serial interface consists of three bidirectional lines:
the data line sends and receives data; the data clock is a
synchronous pulse used to clock the serial data in and
out of the chip; and the data transfer enable is high
during the time when valid data is on the serial interface
lines. The serial interface is operated in the master or
slave mode. In either mode, the CPU can send or receive
data.
The seven ac output bits (ACo - ACe) perform the
following functions.
The selected ac output bits are triggered after a
programmable delay time from the zero crossing of the
ac line, and remain on until turned off by the program.
Real-Time Clock
Phase Control Mode
The real·time clock consists of a divide-by-50/60 and a
divide-by-60 cascade counter. The clock generates an
internal interrupt on zero crossings, seconds, and
minutes. These interrupts are under program control.
The duty cycle register is loaded with the value
corresponding to the desired firing angle; the output(s)
are activated when the register reaches its terminal
count, and remain activated until the next zero crossing.
Power Control Ports
Analog-Input/Output Channels
The seven ac outputs are individually capable of sinking
20 mA of current when driven separately; only four of any
seven can be turned on at rated current at anyone time.
Five input channels operate in different modes selected
by setting the appropriate bits in port D, which is the
control port used by the AID converter and the analog
multiplexer. Anyone of the five channels can be
selected and converted from a 0.5 V to (V oo -0.5) V analog
input, to an 8-bit digital equivalent, in less than 100
microseconds. The results are stored in the appropriate
port. Completion is signaled by an internal interrupt.
Zero-Crossing Detection
The zero-crossing input is tied to the 50/60 Hz line
through a resistor. This input, which monitors the power
line and generates an interrupt (depending on how the
control register is set up), can be one of the following:
positive-going zero crossing, negative-going zero
crossing, both positive and negative zero crossing,
seconds, or minutes.
The zero-crossing (ZC) detector also supplies the input
for the interval timers and to the ac output circuitry.
Zero-Crossing Drive Mode
The D/A mode can output an analog signal through any
one of the five analog 1/0 lines. The D/A has an 8-bit
resolution. The selected D/A channels are refreshed
every 600 microseconds or less, except during an analog
rea~ or write period.
In the AID mode, the selected analog line is like the
digital equivalent after the AID conversion is performed.
The results of this conversion are stored in port F. After
the conversion, an internal interrupt is generated,
indicating the conversion is complete.
•
F38701
I
I .
I
4-98
F38752
Analog Interface Unit
Advance Product Information
Microprocessor Product
Description
•
•
•
•
•
•
•
Designed to operate with the F38700 CPU, the Fairchild
F38752 Analog Interface Unit (AIU) contains a fivechannel ana!og-to-digital (AID) or digital-to-analog (D/A)
converter (see figure 1)_ The AID conversion is
accomplished using a successive approximation
technique, and the DIA conversion is accomplished
using a charge redistribution technique with binaryweighted capacitors_ The" F38752 also contains interrupt
logic to support daisy-chain Interrupt functions.
AID or DIA Conversion Capability for Each Channel
8-Bit Resolution for All Five Channels
Conversion Time of 24 lAs per Channel
Programmable Interrupt Vector by Strap-Pin Selection
Daisy-Chain Interrupt Control
Single + 5 V Power Supply
40-Pin Package
Figure 1 38752 Block Diagram
AI03 AIOI
AI04 AI02 AIOD
R8
Vss
SliSf
REGISTER
ADDRESS
DECODER
CONTROL REGISTER
RS
DATA REGISTER
R4
DATA REGISTER
R3
DATA REGISTER
R2
DATA REGISTER
Rl
DATA REGISTER
RD
BUFFER
DATA BUS
Iili
Viii
MS
A2
AI
CPU READIWRITE
INTERFACE
INTERRUPT
CONTROL
DATA BUS
INTERFACE
AD_
DBS
DB3
DBI
DB7
DB8
DB4
DB2
DBO
4-99
F38752
Signal Descriptions
Table 1
The signals for the F38752 are described in table 1.
Mnemonic
Name
Description
DBo - DB7
Data Bus
Bidirectional data, status,
and control information
Aa - A2
Register
Address
Data, status, and control
register selection inputs
AIOo-AI0 4
Analog
Channels
Bidirectional analog lines
4>W
Clock
Input from the CPU
SRST
Synchronized
Reset
Active-low input
MS
Module
Select
Active-high input
RD
Read Enable
Active-low input
WR
Write Enable
Active-low input
INT
Interrupt
Request
Active-low output
IAI
Interrupt
Acknowledge
Active-low input for the
daisy chain
lAO
Interrupt
Acknowledge
Active-low output for the
daisy chain
STs,STs'
ST7
Strap Pins
Active-low strapping for
the programmable
interrupt vector
Voo
Power Input
+ 5 V power supply input
Vss
Ground
o V reference
VAA
Ground
o V reference
F38752 Signal Descriptions
Registers
The F38752 has eight registers numbered 0 through 7.
The first five are data registers; number 5 is the control
register, number 6 the status register, and number 7 the
buffer register. All have read and write capability except
register 6 and register 7, which can only be read. Table 2
describes the registers, and table 3 gives their CPU
addresses.
4·100
for the
internal analog circuitry
F38752
Table 2
Addressable Register Format
Register
Number
Register
Name
Bit
Description
RO
Data
0-7
Data for channel 0
R1
Data
0-7
Data for channel 1
R2
Data
0-7
Data for channel 2
R3
Data
0-7
Data for channel 3
R4
Data
0-7
Data for channel 4
R5
Control
0
= D/A mode, 0
= D/A mode, 0
1 = D/A mode, 0
1 = D/A mode, 0
1 = D/A mode, 0
1
2
3
4
1
1
=
=
=
=
=
AID mode for channel 1
AID mode for channel 2
AID mode for channel 3
AID mode for channel 4
5
Mode
Bit
Interrupt mode
R6
•
AID mode for channel 0
6
5
6
0
0
1
1
0
1
0
1
MC multichannel interrupt
DASC D/A single channel
ADSC AID single channel
ALLSC All single channels
7
1 = Interrupt enable, 0 = Interrupt disable
Status
0
1 = Channel 0 selected; 0 = Channel 0 not selected
(read only)
1
1 = Channel 1 selected; 0 = Channel 1 not selected
2
1 = Channel 2 selected; 0 = Channel 2 not selected
3
1 = Channel 3 selected; 0 = Channel 3 not selected
4
1 = Channel 4 selected; 0 = Channel 4 not selected
5
Bit
Interrupt mode
6
R7
6
5
0
0
1
1
0
1
0
1
7
1 = Interrupt enable, 0 = Interrupt disable
0-7
AID; results of last analog conversion
0-7
D/A; data for present conversion
Buffer read {
4-101
Mode
MC multichannel interrupt
DASC D/A single channel
ADSC AID Single channel
ALLSC All single channels
I
F38752
Table 3
Register Address
Operation Description .
Register
Name
MS
A2
A1
AO
0
1
Data
Data
Data
Data
Data
Control
Status
Buffer
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
2
3
4
5
6
7
All five channels are multiplexed. Writing into the control
register initiates the conversion starting with channel 0
and sequencing through channel 4. It continuously
performs the conversion unless the interrupt is enabled.
Wheri AD interrupts are selected, register 7 must be read
to continue to the next channel. When DA interrupts are
selected, register 6 must be read.
4·102
F38753
Power Control Unit
Microprocessor Product
Advance Product Information
Description
Signal Functions
The Fairchild F38753 Power Control Unit (PCU) is
designed to operate with the F38700 CPU. It has eight
current-sinking high outputs that may be used to directly
drive opto-Isolators or trlacs. The on-chip logic allows
zero-crossing switching, delayed switching, and phase
control without CPU intervention. The F38753 PCU
contains logic to provide seconds and minutes counting
in either 50-Hz or 60-Hz operations.
CLOCK {
ADDRESS
I
..
DB•
..WR
DB,
A.
A,
DB.
A.
DB,
DB,
A,
DB,
DATA BUS
DB.
SYNCHRONIZED
RESET
The PCU internal Interrupt logic implements first-come
first-served interrupts. The Interrupt request latch is
reset after the first read signal Is input. If the first
Interrupt request is the minute transition, the minute
interrupt has the highest priority, the second Interrupt
has the next highest priority, and the positive zerocrossing (ZC) Interrupt has the lowest priority, if all three
Interrupt control bits are set.
INTERRUPT
Eight ac Control Outputs, Each with Current Sinking
Capability of 20 mA
• Four Output Modes: Zero-Crossing Switching,
Positive and Negative Delayed Swltchlngs, and Phase
Firing
Capability of Programming Each Output Differently
Separate Output On·Off Control
• Capability of Programming Outputs to be Pulsed by
Internal Clock
• Four Real-Time Interrupts: Positive Zero Crossing,
Negative Zero CrOSSing, Second, and Minute
•
•
I
I
iNT
ill
1AO
DB,
zc
ZERO CROSSING
. ACo
AC,
AC.
AC,
CE
WR
RD
AC,
POWER {
vcc
vss
So
TEST
TID
CHIP
CONTROL
•
SRS'f
EXTERNAL
CONTROL
AC,
AC.
AC,
s,
s.
Signal Descriptions
Name
Description
Address Bus
Input lines that are used to select the Internal registers, which are
addressed as I/O ports.
CE
Chip Select
An actlve·low Input signal that Indicates the CPU is trying to read from
or write to the PCU Internal registers.
RD
Read Enable
An input Signal that indicates the CPU Is performing a read operation.
WR
Write Enable
An Input signal that indicates the CPU i.s performing a write operation.
Mnemonic
Address
Ao-A3
Chip Control
4-103
F38753
Signal Descriptions
Mnemonic
Clock
Name
Description
4>
System Clock
A clock input signal originating at the CPU.
4>WR
Clock
The clock input from the CPU.
Data Bus
Bidirectional 3-state lines that link the PIO to all other devices within the
microprocessor system.
Power
Control Lines
Seven output drivers that may be used to control loads in the zerocrossing or phase control modes.
IAI
Interrupt
Acknowledge
An input signal from the CPU that indicates the CPU is ready to service
the PCU interrupt.
lAO
Interrupt
Acknowledge
Output
An output signal that is connected to the interrupt acknowledge input of
other chips in a daisy-chain to establish interrupt priority.
Interrupt
Request
An output signal to the CPU; a logical low means the chip requires
service from the CPU.
Vee
Power Supply
+ 5 V (± 10%) power input
Vss
Ground
o V input
Strap/Interrupt
Address Selection
Three active·low input signals that select the internal address and the
interrupt address vectors.
Synchronized
Reset
An active-low input signal that resets the internal logic of the CPU.
Test Circuit
An active·low input used only in testing theF38753 PCU. For normal
circuit functions this pin in unconnected or grounded.
Zero Crossing
Input
3-5 V POp, 50/60 Hz ac main signal.
Data Bus
DBo-DB7
External Control
AC o-AC7
Interrupt
INT
Power
Strap Pins
SO·S2
Synchronized Reset
SRST
Test
TEST
Zero Crossing
ZC
4·104
F38754
Peripherallnput/Output
Microprocessor Product
Advance Product Information
Signal Functions
Description
The Fairchild F38754 Peripheral Input/Output (PIO)
device two 8-bit 1/0 ports with TTL-compatible outputs. It
has one 8-blt serial 1/0 serial 1/0 channel for communicating with other microprocessors or for driving other
peripheral devices that accept serial data. The PIO has
on-chip Interrupt logic that may be used to interrupt the
CPU through the serial data port.
.... 0110
PAc>
PA,
Plio
PA,
PAo
PA,
PAs
• Two 8-Blt ParrallelllO Ports, Providing 16
Bidirectional TTL-Compatible 1/0 Lines
• One 8-Blt Serial 110 with Handshake and
Programmable Data Transfer Rate
• Different Interrupt Vectors for Transmit and Receive
Operations
PA7
PB.
PB,
1/0 PORTS
PB.
PB.
PB,
PBs
PB.
•
PB7
lAO
INTERRUPT ACKNOWLEDGE
OUTPUT
m
!RiC
m
So
STRAPIINTERRUPT
ADDRESS SELECTION
CC
SS
Signal Descriptions
Mnemonic
Name
Description
Address Bus
Input lines used to select the internal registers, which are addressed as
1/0 ports.
Chip Select
An active-low input signal that Indicates the CPU Is trying to read from 0
write to the PIO internal registers.
System Clock
Clock input signal originating at the CPU.
Data Bus
Bidirectional 3-state lines that link the PIO to all other devices. within the
microprocessor system.
Address
Ao-A,
Chip
CE
Clock
ell
Data Bus
DBa - DB7
4-105
F38754
Mnemonic
Interrupt
Name
Deacrlption
INT
Interru pt Req U$st
An output signal to the CPU; a logical low means the chip requires
service from the CPU.
IAI
Interrupt
Acknowledge
Aniilput signal from the CPU that indicates the CPu is ready to service
the PCU interrupt.
Interrupt
Acknowledge
Output
An output signal that is connected to the Interrupt acknowledge input
of other chips in a daisy·chain to establish fnterrupt priority:
pAc· PA7
PBe - PB7
Power
I/O Ports
Bidirectional ports through which the PIO communications with logic
external to the microprocessor system.
Vce
Power Supply
+5 V (±10%)
Vss
Read Enable
Ground
System ground - 0 V
RD
Read Enable
An input signal that indicates the CPU is performing a read operation.
SOC
Serial Data Clock
A bidirectional signal that clocks data in and out -of the serial data port;
one bit of data Is shifted In or out for each data clock pulse.
SOT
Serial Data
A bidirectional serial data line that shifts data in and out, least
significant bit first, synchronous with the data clock.
STE
Serial Data Gate
When the bidirectional data gate is high, both the data clock and the,
serial data port are enabled.
:
Interrupt
Acknowledge,
Output
lAO
110 Ports
Serial Data
,Strap/,Interrupt
Address Selection
So
,
'
Strap/Interrupt
Address Selection,
Three active low input signals that select the internal address and the
interrupt addr!lss vectors.
Write Enable
An Input signal that Indicates the CPU Is performaing a write operation.
Write Enable
WR
4,106
[!J
1
I INTRODUCTION
!,;l2 IORDERING AND PACKAGE
~ INFORMATION
1C!JIF8 MICROCOMPUTER FAMILY
1 0 1 CONTROLLER FAMILY
F6800 MICROPROCESSOR FAMILY
101F16000 MICROPROCESSOR FAMILY
I[!]
I ROM PRODUCTS
Inlg 1DEVELOPMENT SYSTEMS AND
L!J SOFTWARE
I[!QJ
I[!IJ
I[!!]
1APPLICATIONS
I RESOURCE AND TRAINING CENTERSI
1SALES OFFICES
Section 5
F6800 Microprocessor Family
General
The Fairchild F6800 microprocessor family is a set of 8·bit
MOS devices that offers a complete and constantly growing
selection of microprocessors having a powerful instruction
set. As shown in figure 5·1, the F6800 family now includes
seven different CPUs (described in table 5·1), supported by
such circuits as synchronous and asynchronous controllers
for data communications, timers, a direct memory access
controller, CRT controllers, RAMs, ROMs, and EPROMs
(described in table 5·2).
Table 5·1 F6800 Microprocessor Family CPUs
Device No.
F6800
F6801
F6802
F6803
F6808
F6809
F6882
External
No. of Power
Pins Supply Addressing
40
40
40
40
40
40
40
+5V
+5V
+5V
+5V
+5V
+5V
+5V
64K
64K
64K
64K
64K
64K
64K
Data
Length
(Bits)
Clock
8
8
8
8
8
8
8
No
Yes
Yes
Yes
Yes
Yes
Yes
No. of
Basic
Instructions
Bytes
(RAM)
Bytes
(ROM)
128
128
128
-
82
72
82
59
-
72
128
72
2K
-
-
No. of
1/0
Lines
31
-
13
-
Other
110
Timer
Serial
Serial
-
-
16·Bit
-
16·Bit
-
Table 5·2 F6800 Peripheral Devices
Type
Number
Name
Comment
General·Purpose
F6820
Twenty I/O Lines
General·Purpose
F6821
General·Purpose
General·Purpose
F6840
F68488
Peripheral Interface
Adapter
Peripheral Interface
Adapter
Programmable Timer Module
General·Purpose
Interface Adapter
Special Function
F6844
Special Function
Special Function
Special Function
F6845
F6846
F6847
Data Communications
F6850
Data Communications
F6852
Data Communications
F6854
Data Communications
F6856/
F3846
F68456/
F38456
Asynchronous Communications
Interface Adapter
Synchronous Serial Data
Adapter
Advanced Data Link
Controller
Synchronous Communications
Protocol Controller
Multi·Protocol
Communications Controller
F6810
128 x 8·Bit Static RAM
Data Communications
Memory
Direct Memory Access
Controller
CRT Controller
ROM, I/O, Timer
Video Display Generator
5·3
Twenty I/O Lines
Three·to 16-Bit Timers
IEEE·488 Bus Controller
Three I/O Channels
Available in Interlace or Non·lnterlace
2K x 8 ROM, Parallel 110, Timer
Low·Cost Video Controller
HDLC/SDLC
HDLC/SDLC/BTSYNC
HDLC/SDLC/BISYNC/ASYNC
•
F6800 Microprocessor
Family
Figure 5·1 F6800 Family Organization
F6802/F6808/F6882
MICROPROCESSOR WITH
CLOCK AND RAM r-----L....J.-----,
F6800
MICROPROCESSING
UNIT
F6610
STATIC RAM
F8820
PERIPHERAL
INTERFACE ADAPTOR
F6840
PROGRAMMABLE
TIMER
F6844
DIRECT MEMORY
ACCESS CONTROLLER
F6845/F6645A
CRT CONTROLLER
F6846
ROM·I/O·TIMER
F6847
VIDEO DISPLAY
GENERATOR
F6850
ASYNCHRONOUS
COMMUNICATIONS
INTERFACE ADAPTOR
F6852
SYNCHRONOUS
SERIAL DATA
ADAPTOR
F6854
ADVANCED DATA
LINK CONTROLLER
F3646/F6856
SYNCHRONOUS
PROTOCOL COMMUNICATIONS
CONTROLLER
F38456/F68456
MULTIPLE PROTOCOL
COMMUNICATIONS
CONTROLLER
F68468
GENERAL PURPOSE
INTERFACE ADAPTOR
5·4
F6800 Microprocessor
Family
Instruction Set
Figure 5-3 F6801/F6803 Programming Model
Because a single instruction set is inadequate for the
number and flexibility of devices in the F6800 family, it has
been necessary to develop three such sets, each serving a
portion of the family.
7
0
I
15
I
I
X
I
8·BIT ACCUMULATORS A AND B OR
16·BIT DOUBLE ACCUMULATOR D
0
~
~
The basic instruction set, comprising 72 instructions, is
supported by the F6800, F6802, F6808, and F6882; figure 5-2
is the associated programming model. An expanded instruction set, consisting of the basic set plus several additional instructions, is supported by the F6801 and F6803;
figure 5-3 illustrates the associated programming model.
The expanded instruction set is upward-compatible with the
basic set (that is, programs written using either are interchangeable, provided that the additional instructions are
not involved). Both the basic and expanded instruction sets
are described in table 5-3.
07
1;5-m----~----------l----------~---m---iiJ
INDEX REGISTER (X)
0
I
~
STACK POINTER (SP)
0
I
r:,l":'tr:":'l'":'T.:"I"':=r:::.0
PC
PROGRAM COUNTER (PC)
CONDITION CODE
REGISTER (CCRj
CARRY/BORROW FROM MSB
OVERFLOW
ZERO
'----NEGATiVE
......---INTERRUPT
' - - - - - - H A L F CARRY (from Bit 3)
Figure 5-4 F6809 Programming Model
The instruction set supported by the high-performance
F6809 is similar in structure to the basic and expanded
sets, but is not upward-compatible. It is greatly enhanced to
take fullest advantage of the powerful F6809 architecture.
Figure 5-4 illustrates the F6809 programming model and
table 5-4 describes the instruction set.
INDEX REGISTER (X)
)
IN DEX REGISTER (Y)
HARDWARE STACK (S)
...._ _ _ _ _....;...PC;;..._ _ _ _ _...... PROGRAM COUNTER
Figure 5-2 F6800/F6802IF68081F6882 Programming Model
7
I
7
I
15
I
I
o
I
ACCUMULATOR A
D
0
ACCB
15
I
15
I
-====A===~===B===~ACCUMULATORS
0
ACCA
IX
ACCUMULATOR B
...._ _...:D;.:.P_ _....... DIRECT PAGE REGISTER
INDEX REGISTER (X)
r:E:-r:F~Hr:""'r.:"Il':'I'::r~ CONDITION CODE
o
PC
,
(CC) REGISTER
PROGRAM COUNTER (PC)
1!
o
I
SP
CARRY/BORROW
OVERFLOW
......---ZERO
'------NEGATIVE
'-------INTERRUPT MASK
STACK POINTER (SP)
o
1 H I
N.Z V C . CONDITION CODE REGISTER (CCR)
CARRY (from Bit 7)
......- - - - - H A L F CARRY
OVERFLOW
ZERO
NEGATIVE
INTERRUPT MASK
HALF CARRY (from Bit 3)
' - - - - - - - F A S T INTERRUPT MASK
' - - - - - - - - - E N T I R E STATE ON STACK
5-5
•
F6800 Microprocessor
Family
Table 5-3 Basic and Expanded Instruction Sets
Instruction
Description
ABA
*ABX
ADC
ADD
*ADDD
AND
ASL
*ASLD
ASR
Add Accumulators
Add Accumulator B to Index Register
Add With Carry
Add
Add Double Accumulator to Memory; Leave Sum In Double Accumulator
Logical AND
Arithmetic Shift Left
Double Accumulator Shift Left; Clear LSB; Shift MSB into C-Bit
Arithmetic Shift Right
BCC
BCS
BEO
BFE
BGT
BHI
*BHS
BIT
BLE
*BLO
BLS
BLT
BMI
BNE
BPL
BRA
'BRN
BSR
BVC
BVS
Branch if Carry Clear
Branch if Carry Set
Branch if Equal To Zero
Branch if Greater Than or Equal To Zero
Branch if Greater Than
Branch if Higher Than
Branch if Higher Than or Same As
Bit Test
Branch if Less Than or Equal To
Branch if Lower Than
Branch if Lower Than or Same As
Branch if Less Than Zero
Branch if Minus
Branch if Not Equal To Zero
Branch if Plus
Branch Always
Branch Never
Branch to Subroutine
Branch if Overflow Clear
Branch if Overflow Set
CBA
CLC
CLI
CLR
CLV
CMP
COM
CPX
'CPX
Compare Accumulators
Clear Carry
Clear Interrupt Mask
Clear
Clear Overflow
Compare
Complement
Compare Index Register
Compare Index Register; Permits Use With Any Conditional Branch Instruction
DAA
DEC
DES
DEX
Decimal Adjust
Decrement
Decrement Stack Pointer
Decrement Index Register
EOR
Exclusive OR
'F6801/F6803 Only
5-6
F6800 Microprocessor
Family
Table 5·3 Basic and Expanded Instruction Sets (Cont.)
Instruction
INC
INS
INX
I
Description
Increment
Increment Stack Pointer
Increment Index Register
JMP
JSR
*JSR
Jump
Jump to Subroutine
Additional Addressing Mode Direct
LDA
*LDD
LDS
LDX
*LSL
*LSLD
LSR
* LSRD
Load Accumulator
Load Double Accumulator from Memory
Load Stack Pointer
Load Index Register
Memory or Accumulator Shift Left; Clear LSB; Shift MSB into C·Bit
Double Accumulator Shift Left; Clear LSB; Shift MSB into C·Bit
Logical Shift Right
Double Accumulator Shift Right; Clear MSB; Shift LSB into C·Bit
*MUL
Multiply Accumulators; Leave Product in Double Accumulator
NEG
NOP
Negate
No Operation
ORA
Inclusive OR Accumulator
PSH
*PSHX
PUL
*PULX
RJOL
ROR
RTI
RTS
SBA
SBC
SEC
SEI
SEV
STA
*STD
STS
STX
SUB
*SUBD
SWI
Push Data
Push Index Register to Stack
Pull Data
Pull Index Register from Stack
Rotate
Rotate
Return
Return
Left
Right
from Interrupt
from Subroutine
Subtract Accumulators
Subtract With Carry
Set Carry
Set Interrupt Mask
Set Overflow
Store Accumulator
Store Double Accumulator
Store Stack Register
Store Index Register
Subtract
Subtract Double Accumulator; Leave Difference in Double Accumulator
Software Interrupt
* F6801/F6803 Only
5·7
•
F6800 Microprocessor
Family
Table 5-3 Basic and Expanded Instruction Sets (Cont.)
Instruction
Description
TAB
TAP
TBA
TPA
TST
TSX
TXS
Transfer Accumulators
Transfer Accumulators to Condition Code Register
Transfer Accumulators
Transfer Condition Code Register to Accumulator
Test
Transfer Stack Pointer to Index Register
Transfer Index Register to Stack Pointer
WAI
Wait for Interrupt
*F6801/F6805 Only
Table 5·4 F6809 Instruction Set
Instruction
Description
ABX
ADCA,ADCB
ADDA,ADDB
ADDD
ANDA,ANDB
ANDCC
ASl, ASLA
ASlB
ASR, ASRA,
ASRB
Add Accumulator B to Index Register
Add Memory to Accumulator With Carry
Add Memory to Accumulator
Add Memory to Accumulator D
AND Memory With Accumulator
AND Condition Code Register
Arithmetic Shift left of Accumulator or Memory
BCC, lBCC
BCS,lBCS
BEO,lBEO
BGE, lBGE
BGT,lBGT
BHI, lBHI
BHS,lBHS
BITA, BITB
BlE,lBlE
BlO, lBlO
BlS, lBlS
BlT, lBlT
BMI, lBMI
BNE, lBNE
BPl, lBPl
BRA, lBRA
BRN, lBRN
BSR,lBSR
BVC,lBVC
BVS,lBVS
Branch if Carry Clear
Branch if Carry Set
Branch if Equal To
Branch if Greater Than or Equal To
Branch if Greater Than
Branch if Higher
Branch if Higher Than or Same As
Bit Test Memory With Accumulator
Branch if less Than or Equal To
Branch if lower
Branch if lower Than or Same As
Branch if less Than
Branch if Minus
Branch if Not Equal To
Branch if Plus
Branch Always
Branch Never
Branch to Subroutine
Branch if Overflow Clear
Branch if Overflow Set
ClR, ClRA,
ClRB
CMPA CMPB
Clear Accumulator or Memory location
Arithmetic Shift Right of Accumulator or Memory
Compare Memory from Accumulator
5-8
F6800 Microprocessor
Family
Table 5·4 F6809 Instruction Set (Cont.)
Instruction
Description
CMPD
CMPS, CMPU
CMPX, CMPY
COM, COMA,
COMB
CWAI
Compare Memory from Accumulator D
Compare Memory from Stack Pointer
Compare Memory from Index Register
Complement Accumulator or Memory Location
DAA
DEC, DECA,
DECB
Decimal Adjust Accumulator A
Decrement Accumulator or Memory Location
EORA, EORB
EXG D, R
EXG R1, R2
,Exclusive OR Memory With Accumulator
Exchange D With X, Y, S, U, or PC
Exchange R1 With R2 (R1, R2 = A,B, CC, DP)
AND Condition Code Register; Wait for Interrupt
INC, INCA,
INCB
Increment Accumulator or Memory Location
JMP
JSR
Jump
Jump to Subroutine
LDA, LDB
LDD
LDS, LDU
LDX, LDY
LEAS,LEAU
LEAX,LEAY
LSL, LSLA,
LSLB
LSR, LSRA,
LSRB
Load Accumulator from Memory
Load Accumulator D from Memory
Load Stack Pointer from Memory
Load Index Register from Memory
Load Effective Address into Stack Pointer
Load Effective Address into Index Register
Logical Shift Left Accumulator or Memory Location
MUL
Unsigned Multiply
NEG, NEGA,
NEGB
NOP
Negate Accumulator or Memory
No Operation
ORA,ORB
ORCC
OR Memory With Accumulator
OR Condition Code Register
PSHS
PSHU
PULS
PULU
Push A, B, CC, DP, D, X, Y, U, or PC onto hardware stack
Push a, B, CC, DP, D, X, Y, U, or PC onto user stack
Pull A, B, CC, DP, D, X, Y, U, or PC fro hardware stack
'pull A, B, CC, DP, D, X, Y, U, or PC from user stack
ROL, ROLA,
ROLB
ROR, RORA,
RORB
RTI
RTS
Rotate Accumulator or Memory Left
Logical Shift Right Accumulator or Memory Location
Rotate Accumulator or Memory Right
Return from Interrupt
Return from Subroutine
5·9
II
F6800 Microprocessor
Family
Table 5·4 Instruction Set (Cont.)
Instruction
Description
SBCA, SBCB
SEX
STA,STB
Subtract Memory from Accumulator With Borrow
Sign Extend Accumulator B into Accumulator A
Store Accumulator to Memory
Store Accumulator D to Memory
Store Stack Pointer to Memory
Store Index Register to Memory
Subtract Memory from Accumulator
Subtract Memory from Accumulator D
Software Interrupt
STD
STS, STU
STX,STY
SUBA,SUBB
SUBD
SWI SWI2,
SWI3
SYNC
TFR D, R
TFR R, D
TFR R1, R2
TST, TSTA,
TSTB
Synchronize With Interrupt Line
Transfer D to X, Y, S, U, or PC
Transfer X, Y, S, U, or PC to D
Transfer R1 to R2
Test Accumulator or Memory Location
Descriptions
Following is data that describes the members of the F6800 microprocessor family.
5·10
F6800/F68AOO/F68BOO
8-Bit Microprocessing Unit
Microprocessor Product
Description
The F6800 is a monolithic 8-bit microprocessing unit (MPU)
forming the central control function for the Fairchild F6800
family. Compatible with TTL, the F6800, as with all F6800
system parts, requires only one +5.0 V power supply and no
external TTL devices for bus interface.
Logic Symbol
33 32 31 30 29 28 27 26
Ao
The F6800 is capable of addressing 65K bytes of memory
with its 16-bit address lines. The 8-bit data bus is
bidirectional as well as 3-state, making direct memory
addressing and multiprocessing applications realizable.
37
.'.,
F6800
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
8-Bit Parallel Processing
Bidirectional Data Bus
16-Bit Address Bus - 65K Bytes of Addressing
72 Instructions - Variable Length
7 Addressing Modes - Direct, Relative, Immediate,
Indexed, Extended, Implied and Accumulator
Variable Length Stack
Vectored Restart
Maskable Interrupt Vec;tor
Separate Non-Maskable Interrupt - Internal Registers
Saved in Stack
6 Internal Registers - 2 Accumulators, Index
Register, Program Counter, Stack Pointer, and
Condition Code Register
Direct Memory Addressing (DMA) and Multiple
Processor Capability
Simplified Clocking Characteristics
Clock Rates 1 MHz (F6800), 1_5 MHz (F68AOO), and
2 MHz (F68BOO)
Simple Bus Interface Without TTL
Halt and Single Instruction Execution Capability
Pin Names
0 0 -0 7
HALT
1>1,1>2
IRQ
NMI
DBE
TSC
RESET
VMA
BA
Ao-A'5
R/W
Vee
Vss
36
OBE
39
TSC
40
RESET
34
Vcc= Pin 8
Vss= Pins 1, 21
Connection Diagram
40-Pin DIP
v__
RESET
.,
HALT
TSC
N.C •
.'
IRQ
VMA
Bidirectional Data Bus
Halt Input
Clock Inputs
Interrupt Request Input
Non-Maskable Interrupt Input
Data Bus Enable Input
3-State Control Input
Reset Input
Valid Memory Address Output
Bus Available Output
Address Bus Outputs
Read/Write Output
+5 V Power Supply Input
Ground
OBE
NMI
N.C.
BA
RiW
Vee
Do
Ao
0,
A,
0,
A.
03
A3
0,
A4
D.
As
Oa
Ao
D?
A,
A1S
Aa
A14
A.
Au
AlO
A12
vs_
Au
(Top View)
5-11
A,
10
A.
11
A:l
12
A,
13
As
A,
,.
A,
16
Aa
17
A,
18
AlO
19
14
Au
20
A12
22
Au
23
A14
24
A1S
25
•
F6800/F68AOO/F68BOO
Block Diagram
CLOCK,.,
CLOCK,.,
RESET
NON-MASKABLE INTERRUPT (NMI)
HALT
INTERRUPT REOUEST (IRO)
3-STATE CONTROL (TSC)
OATA BUS ENABLE (DBE)
BUS AVAILABLE (BA)
VALID MEMORY ADDRESS (VMA)
READ/WRITE (R/W)
MPU Signal Description
Address Bus (Ao-A 1s)
Sixteen pins are used for the address bus. The outputs are
3-state bus drivers capable of driving one standard TTL load
and 90 pF. When the output is turned off, it is essentially an
open circuit. This permits the MPU to be used in DMA
applications. Putting TSC in its HIGH state forces the
address bus to go into the 3-state mode.
Proper operation of the MPU requires that certain control and
timing signals be provided to accomplish 'specific functions
and that other signal lines be monitored to determine the
state of the processor.
Clocks Phase One a,nd Phase Two (CP1,2)
Two pins are used for a 2-phase non-overlapping clock that
runs at the Vcc voltage level.
Data Bus (00-07)
Eight pins are used for the data bus. It is bidirectional,
transferring data to and from the memory and peripheral
devices. It also has 3-state output buffers capable of driving
one standard TTL load and 130 pF. The data bus is placed in
the 3-state mode when DBE is LOW.
Figure 27 shows the microprocessor clocks, and the Clock
Timing table shows the static and dynamic clock
specifications. The HIGH level is specified at VIHC and the
LOW level is specified at VILC. The allowable clock
frequency is specified by f (frequency). The minimum 1 and
2 HIGH level pulse widths are specified by PWH (pulse
width HIGH time). To guarantee the required access time for
the peripherals, the clock up time, t ut , is specified. Clock
separation, td, is measured at a maximum voltage of Vov
(overlap voltage). This allows for a multitude of clock
variations at the system frequency rate.
Data Bus Enable (DBE)
This input is the 3-state control signal for the MPU data bus
and will enable the bus drivers when in the HIGH state. This
input is TTL-compatible; however, in normal operation it
would be driven by the phase'two clock. During an MPU read
cycle, the data bus drivers will be disabled internally. When it
is desired that another device control the data bus, such as
5-12
F6800/F68AOO/F68BOO
Fig. 1
MPU Flow Chart
WAI
•
CONDITION CODE
REGISTER
z
V
C
'ITEMP' 1·BIT
BUFFER REGISTER
N
Notes
1. Reset is recognized at any position in the flowchart.
2. Instructions which affect the I·Bit act· upon a one·bit buffer
register, "ITMP". This has the effect of delaying any clearing of the
I·Bit one clock time. Setting the I· Bit, however, is not delayed.
3. Refer to tables 8 through 13 for details of instruction execution.
5·13
F6800/F68AOO/F68BOO
in Direct Memory Access (DMA) applications, DBE should be
held LOW.
cycles are required for the processor to stabilize in
preparation for restarting. During these eight cycles, VMA
will be in an indeterminate state so any devices that are
enabled by VMA which could accept a false write during this
time (such as a battery-backed RAM) must be disabled until
VMA is forced LOW after eight cycles. RESET can go HIGH
asynchronously with the system clock any time after the
eighth cycle.
If additional data set-up or hold time is required on an MPU
write, the DBE down time can be decreased as shown in
Figure 29 (DBE 0/= q,2). The minimum down time for DBE is
tOSE as shown and must occur within q, I up time. The
minimum delay from the trailing edge of DBE to the trailing
edge of q, I is tOBEO' By skewing DBE with respect to E in this
manner, data set-up or hold time can be increased.
Reset timing is sh.own in Figure 2 and the Read/Write Timing
table. The maximum rise and fall transition times are
specified by tPCr and tpCt. If RESET is HIGH at tpcs
(processor control set-up time) as shown in Figure 2 in any
given cycle, then the restart sequence will begin on the next
cycle as shown. The RESET control line may also be used to
reinitialize the MPU system at any time during its operation.
This is accomplished by pulsing RESET LOW for the duration
of a minimum of three complete q,2 cycles. The Reset pulse
can be completely asynchronous with the MPU system clock
and will be recognized during q,2 if set-up time tpcs is met.
Bus Available (BA)
The Bus Available signal will normally be in the LOW state;
when activated, it will go to the HIGH state, indicating that
the microprocessor has stopped and that the address bus is
available. This will occur if the HALT line is in the LOW state
or the processor is in the WAIT state as a result of the
execution of a WAIT instruction. At such time, all 3-state
output drivers will go to their OFF state and other outputs to
their normally inactive level. The processor is removed from
the WAIT state by the occurrence of a maskable (mask bit I
= "0") or nonmaskable interrupt. This output is capable of
driving one standard TTL load and 30 pF. H TSC is in the
HIGH state, Bus Available will be LOW.
Interrupt Request (IRQ)
This level-sensitive input requests that an interrupt sequence
be generated within the machine. The processor will wait
until it completes the current instruction that is being
executed before it recognizes the request. At that time, if the
interrupt mask bit in the condition code register is not set,
the machine will begin an interrupt sequence. The index
register, program counter, accumulators, and condition code
register are stored away on the stack. Next the MPU will
respond to the interrupt request by setting the interrupt mask
bit HIGH so that further interrupts may occur. At the end of
the cycle, a 16-bit address will be loaded that points to a
vectoring address which is located in memory locations
FFF8 and FFF9. An address loaded at these locations
causes the MPU to branch to an interrupt routine in memory.
Interrupt timing is shown in Figure 3.
Read/Write (R/W)
This TTL -compatible output signals the peripherals and
memory devices whether the MPU is in a Read (HIGH) or
Write (LOW) state. The normal standby state of this signal is
Read (HIGH). 3-State Control (TSC) going HIGH will turn
Read/Write to the OFF (high-impedance) state. Also, when
the processor is halted, it will be in the OFF state. This
output is capable of driving one standard TTL load
and 90 pF.
Reset (RESET)
The RESET input is used to reset and start the MPU from a
power-down condition resulting from a power failure or initial
start-up of the processor. This input can also be used to
reinitialize the machine at any time after start-up.
The HALT line must be in the HIGH state for interrupts to be
serviced. Interrupts will be latched internally while HALT
is LOW.
If a HIGH level is detected in this input, this will signal the
MPU to begin the reset sequence. During the reset
sequence, the contents of the last two locations (FFFE,
FFFF) in memory will be loaded into the program counter to
point to the beginning of the reset routine. During the reset
routine, the interrupt mask bit is set and must be cleared
under program control before the MPU can be interrupted by
IRQ. While RESET is LOW (assuming a minimum of eight
clock cycles have occurred) the MPU output signals will be
in the following states: VMA = LOW, BA = LOW, data bus =
high impedance, R/W = HIGH (read state), and the address
bus will contain the reset address FFFE. Figure 2 illustrates
a power-up sequence using the RESET control line. After the
power supply reaches 4.75 V a minimum of eight clock
The IRQ has a high-impedance pullup device internal to the
chip; however, a 3 kQ external resistorto Vcc should be
used for wire-OR and optimum control of interrupts.
Non-Maskable Interrupt (NMI) and Wait for Interrupt (WAI)
The F6800 is capable of handling two types of interrupts:
maskable (IRQ) as described earlier, and non-maskable
(NMI). IRQ ismaskable by the interrupt mask in the condition
code register while NMI is not n,~.skable. The handling of
th.ese interrupts by the MPU is the same except that each
has its own vector address. The behavior of the MPU when
interrupted is shown in Figure 3 which details the MPU
response to an interrupt while the MPU is executing the
5-14
F6800/F68AOO/F68BOO
Fig. 2
Reset Timing
1 CYO~LE 1
.,
POWER ON
SWITCH
POWER
SUPPLY
02
1
03
#7
1
1
#8
1
#9
1"+21n+3
1 n +1
1
JlJL...I4~
is
j
-
'5
::
55
5S
5.25 V
'4.75 V
--I
In+4In+51
L-
tpcs
ADDRESS
BUS
FFFE
FFFE
FFFF
R/Vi
~~~~~~~~~\~~~~~~'l~\\'l~"''l~~~~~~@~\~~~:~~'l~~~~~~~~~"'~~~~~~V~"""---'Hj-------------
VMA
~~~~~\\~~\~~~~~~~_ _ _~~j--_ _ _~I
DATA BUS
~~%~~~\\\~~~\~~\\~\\\~t\~
PC
8~1S
PC 0·7
~
BA
FIRST
INSTRUCTION
\~\\~\\\\~\\i~~~~--------~'S~----------------------------~SI5S--------_________
~
Fig. 3
•
NEW PC
=
INDETERMINATE
Interrupt Timing
.,
1
CY#~LE
1
02
1
#3
1
#4
1
os
1
#6
1
#7
1
#8
1
#9
1
#10
1
#11
1
#12
I
#13
I
014
I
015
I
ADDRESS ----~,---,,--~~--~--~~--~---U~--U_--_V--~U_--~~--~,_--~--~,_-
BUS
SPIn - 1) SPIn - 2) SPIn - 3) SPIn - 4) SPIn - 5) SPIn - 6) SPIn - 7) FFF8
FFF9
NEW PC
ADDRESS ADDRESS ADDRESS
fRO
OR NMI
INTERRUPT
MASK
INST (x)
PC 0·7
PC 8·15
X 0·7
X 8·15
R/Vi
VMA
5·15
ACCA
ACCB
CCR
NEW PC 8·15 NEW PC 0·7 FIRST INST OF
ADDRESS
ADDRESS
INTERRUPT ROUTINE
F6800/F68AOO/F68BOO
control program. The interrupt shown could be either IRQ or
NMI and can be asynchronous with respect to 2. The
interrupt is shown going LOW at time tpcs in cycle # 1 which
precedes the first cycle of an instruction (OP code fetch).
This instruction is not executed, but instead, the program
counter (PC), index register (IX), accumulators (ACCX), and
the condition code register (CCR) are pushed onto the stack.
will reach the high impedance state at tTSO (3'state delay),
with VMA being forced LOW. In this example, the data bus is
also in the high impedance state while 2 is being held LOW
since DBE = 2. At this time, a DMA transfer could occur on
cycles #3 and #4. When TSC is returned LOW, the MPU
address and R/W lines return to the bus. Because it is too
late in cycle #5 to access memory, this cycle is dead and
used for synchronization. Program execution resumes in
cycle #6.
The Interrupt Mask bit is set to prevent further interrupts. The
address of the interrupt service routine is then fetched from
FFFC, FFFD for an NMI interrupt and from FFF8, FFF9 for an
IRQ interrupt. Upon completion of the interrupt service
routine, the execution of RTI will pull the PC, IX, ACCX, and
CCR off of the stack; the Interrupt Mask bit is restored to its
condition prior to Interrupts.
Valid Memory Address (VMA)
This output indicates to peripheral devices that there is a
valid address on the address bus. In normal operation, this
signal should be utilized for enabling peripheral interfaces
such as the PIA and ACIA. This signal is not 3·state. One
standard TTL load and 90 pF may be directly driven by this
active HIGH signal.
Figure 4 is a similar interrupt sequence, except in this case,
a WAIT instruction has been executed in preparation for the
interrupt. This technique speeds up the MPU's response to
the interrupt because the stacking of the PC, IX, ACCX, and
the CCR is already done. While the MPU is waiting for the
interrupt, Bus Available will go HIGH indicating the following
states of the control lines: VMA is LOW, and the address
bus, R/W and data bus are all in the high impedance state.
After the interrupt occurs, it is serviced as
previously described.
Table 1
HALT
When this level sensitive input is in the LOW state, all
activity in the machine will be halted.
The HALT line provides an input to the "MPU to allow control
of program execution by an outside sowce. If HALT is HIGH,
the MPU will execute the instructions; if it is LOW, the MPU
will go to a halted, or idle, mode. A response signal, Bus
Available (BA) provides an indication of the current MPU
status. When BA is LOW, the MPU is in the process of
executing the control program; if BA is HIGH, the MPU has
halted and all internal activity has stopped.
Memory Map for Interrupt Vectors
Vector
Description
MS
LS
FFFE
FFFF
Restart
FFFC
FFFD
Non-maskable Interrupt
FFFA
FFFB
Software Interrupt
FFF8
FFF9
Interrupt Request
When BA is HIGH, the address bus, data bus, and R/W line
will be in a high impedance state, effectively removing the
MPU from the system bus. VMA is forced LOW so that the
floating system bus will not activate any device on the bus
that is enabled by VMA.
Refer to Figure 4 for program flow for Interrupts.
While the MPU is halted, all program activity is stopped, and
if either an NMI or IRQ interrupt occurs, it will be latched into
the MPU and acted on as soon as the MPU is taken out of
the halted mode. If a RESET command occurs while the
MPU is halted, the following states occur: VMA = LOW,
BA = LOW, data bus = high impedance, R/W = HIGH (read
state), and the address bus will contain address FFFE as
long as RESET is LOW. As soon as the HALT line goes HIGH,
the MPU will go to locations FFFE and FFFF for the address
of the reset routine.
3-State Control (TSC)
When the 3-State Control (TSC) line is a logic" 1", the
address bus and the R/W line are placed in a high
impedance state. VMA and BA are forced LOW when TSC =
"1" to prevent false reads or writes on any device enabled
by VMA. It is necessary to delay program execution while
TSC is held HIGH. This is done by insuring that no transitions
of 1 (or 2) occur during this period. (Logic levels of the
clocks are irrelevant so long as they do not change.) Since
the MPU is a dynamic device, the 1 clock can be stopped
for a maximum time PWH without destroying data within the
MPU. TSC then can be used in a short Direct Memory
Access (DMA) application.
Figure 6 shows the timing relationships involved when halting
the MPU. The instruction illustrated is a I-byte, 2·cycle
instruction such as CLRA. When HALT goes LOW, the MPU
will halt after completing execution of the current instruction.
The transition of HALT must occur tpcs before the trailing
edge of 1 of the last cycle of an instruction (Point A of
Figure 5 shows the effect of TSC on the MPU. TSC must
have its transitions at tTSE (3-state enable) while holding 1
HIGH and ¢2 LOW as shown. The address bus and R I W line
5-16
F6800/F68AOO/F68BOO
Fig. 4
Wait Instruction Timing
I
.2
n+l
I n+2 I n+3 I n+4 I n+5 I
NEW pc
ADDRESS
-+____~::::){::::~:::>C::::
ADDRESS~~:)C:::~::::~-+
__~~__
BUS~'"
INSTRUCTION
SPIn)
SPIn - 1) SPIn - 4) SPIn - 5) SPIn - 8)
SPIn - 7)
FFF8
FFF9
R/iN
VMA
INTERRUPT
MASK
FIRST INST
OF INTERRUPT
ROUTINE
IRQ OR NMI
DATA BUS
~.~x=~~~~=x=c~~
~~~
BA
PC 0-7
PC 8-15
ACCA
ACCB
CCR
I11'5-
NEW PC 8-15 NEW PC 0-7
ADDRESS
ADDRESS
--------------------------~S:5~--------------~--~I~ .. \'------
Note
Midrange waveform indicate's high-impedance state.
5-17
F6800/F68AOO/F68BOO
Fig. 5
3·State Control Timing
CYCLE
#1
#.
#3
#2
#6
#5
#7
#8
#9
.'
SYSTEM
trSD
tTSD
ADDRESS
BUS
R/Vi
VMA
-"~
__~+-~
________________
~~
DATA BUS
<1>2
= DBE
TSC
ITSE
Fig. 6
Halt and Single Instruction Execution for System Debug
INSTRUCTION
FETCH
.,
I
BA
VMA
ss
INSTRUCTION
IEXECUTE I
I,______r-
:::x:::::J<'y=-......---.ljS:5~_ _ _-J1
FETCH
EXECUTE
<
ADDRESS
BUS
ADOR M +1
DATA
BUS
INST
INST
X
Note
Midrange waveform indicates high impedance state.
5·18
X
)
F6800/F68AOO/F68BOO
Figure 6). HALT must not go LOW any time later than the
minimum tpcs specified.
arithmetic logic unit operation: negative (N), zero (Z),
overflow (V), carry from bit 7 (C), and half carry from bit 3
(H). These bits of the condition code register are used as
testable conditions for the conditional branch instructions. Bit
4 is the interrupt mask bit (I). The unused bits of the
condition code register (bit 6 and bit 7) are ones.
The fetch of the OP code by the MPU is the first cycle of the
instruction. If HALT had not been LOW at Point A, but went
LOW during <1>2 of that cycle, the MPU would have halted
after completion of the following instruction. BA will go HIGH
by time tSA (bus available delay time) after the last
instruction cycle. At this time, VMA is LOW and R/W,
address bus, and the data bus are in the
high-impedance state.
MPU Instruction Set
The F6800 instructions are described in detail in the F6800
Programming Manual. This section will provide a brief
introduction and discuss their use in developing F6800
control programs. The F6800 has a set of 72 different
executable source instructions. Included are binary and
decimal arithmetic, logical, shift, rotate, load, store,
conditional or unconditional branch, interrupt and stack
manipulation instructions.
To debug programs it is advantageous to step through
programs instruction by instruction. To do this, HALT must be
brought HIGH for one MPU cycle and then returned LOW as
shown at Point B of Figure 6. Again, the transitions of HALT
must occur tpcs before the trailing edge of the next 1,
indicating that the Address Bus, Data Bus, VMA and R/W
lines are back on the bus. A single-byte, 2-cycle instruction
such as LSR is used for this example also. During the first
cycle, the instruction Y is fetched from address M + 1. BA
returns HIGH at tSA on the last cycle of the instruction
indicating the MPU is off the bus. If instruction Y had been
three cycles, the width of the BA LOW time would have been
increased by one cycle.
Each of the 72 executable instructions of the source
language assembles into one to three bytes of machine
code. The number of bytes depends on the particular
instruction and on the addressing mode. (The addressing
modes which are available for use with the various executive
instructions are discussed later.)
The coding of the first (or only) byte corresponding to an
executable instruction is sufficient to identify the instruction
and the addressing mode. The hexadecimal equivalents of
the binary codes, which result from the translation of the 72
instructions in all valid modes of addressing, are shown in
Table 2. There are 197 valid machine codes, 59 of the 256
possible codes being unassigned.
MPU Registers
The MPU has three 16-bit registers and three 8-bit registers
available for use by the programmer (Figure
n.
Program Counter
The program counter is a 2-byte (16 bits) register that points
to the current program address.
When an instruction translates into two or three bytes of
code, the second byte, or the second and third bytes
contain(s) an operand, an address, or information from which
an address is obtained during execution.
Stack Pointer
The stack pointer is a 2-byte register that contains the
address of the next available location in an external pushdown I pop-up stack. This stack is normally a random access
read I write memory that may have any location (address)
that is convenient. In those applications that require storage
of information in the stack when power is lost, the stack must
be nonvolatile.
Microprocessor instructions are often divided into three
general classifications: (1) memory reference, so called
because they operate on specific memory locations; (2)
operating instructions that function without needing a memory
reference; (3) II instructions for transferring data between
the microprocessor and peripheral devices.
a
Index Register
The index register is a 2-byte register that is used to store
data or a 16-bit memory address for the Indexed mode of
memory addressing.
In many instances, the F6800 performs the same operation
on both its internal accumulators and the external memory
locations. In addition, the F6800 interface adapters (PIA and
ACIA) allow the MPU to treat peripheral devices exactly like
other memory locations, hence, no 110 instructions as such
are required. Because of these features, other
classifications are more suitable for introducing the F6800's
instruction set: (1) accumulator and memory operations; (2)
program control operations; (3) condition code
register operations.
Accumulators
The MPU contains two 8-bit accumulators that are used to
hold operands and results from an arithmetic logic unit (ALU).
Condition Code Register
The condition code register indicates the results of an
5-19
•
F6800/F68AOO/F68BOO
Fig. 7
Programming Model of The Microprocessing Unit
ACCA
ACCUMULATOR A
AceB
ACCUMULATOR B
15
IX
INDEX REGISTER
15
PC
PROGRAM COUNTER
SP
STACK POINTER
15
CONDITION CODe
REGISTER
CARRY (FROM 'BIT 7)
OVERFLOW
ZERO
L -_ _ _ NEGATIVE
' - - - - - INTERRUPT MASK
L
_ _ _ _ _ _ HALF CARRY (FROM BIT 3)
Table 2
Microprocessor Instruction Set-Alphabetic Sequence
ABA
ADC
ADD
AND
ASL
ASR
Add Accumulators
Add with Carry
Add
Logical And
Arithmetic Shift Left
Arithmetic Shift Right
BCC
BCS
BEQ
BGE
BGT
BHI
BIT
BLE
BLS
BLT
BMI
BNE
BPL
BRA
BSR
BVC
BVS
Branch if Carry Clear
Branch if Carry Set
Branch if Equal to Zero
Branch if Greater or Equal Zero
Branch if Greater than Zero
Branch if Higher
Bit Test
Branch if Less or Equal
Branch if Lower or Same
Branch if Less than Zero
Branch if Minus
Branch if Not Equal to Zero
Branch if. Plus
BranchAlways
Branch to Subroutine
Branch if Overflow Clear
Branch if Overflow Set
CBA
CLC
CLI
CLR
Compare Accumulators
Clear Carry
Clear Interrupt Mask
Clear
CLV
CMP
COM
CPX
Clear Overflow
Compare
Complement
Compare Index Register
DAA
DEC
DES
DEX
Decimal Adjust
Decrement
Decrement Stack Pointer
Decrement Index Register
ROR
RTI
RTS
Rotate Right
Return from Interrupt
Return from Subroutine
Subtract Accumulators
Subtract with Carry
Set Carry
Set Interrupt Mask
Set Overflow
Store Accumulator
Store Stack Register
Store Index Register
Subtract
Software Interrupt
Transfer Accumulators
Transfer Accumulators to Condition
Code Reg.
Transfer Accumulators
Transfer Condition Code Reg. to
Accumulator
Test
Transfer Stack Pointer to Index
Register
Transfer Index Register to Stack
Pointer
EOR
Exclusive OR
INC
INS
INX
Increment
Increment Stack Pointer
Increment Index Register
SBA
SBC
SEC
SEI
SEV
STA
STS
STX
SUB
SWI
JMP
JSR
Jump
Jump to Subroutine
TAB
TAP
LDA
LDS
LDX
LSR
Load Accumulator
Load Stack Pointer
Load Index Register
LogicarShift Right
TBA
TPA
NEG
NOP
Negate
No Operation
ORA
Inclusive OR Accumulator
TXS
PSH
PUL
Push Data
Pull Data
WAI
ROL
Rotate Left
5-20
TST
TSX
Wait for Interrupt
F6800/F68AOO/F68BOO
Table 3
Hexadecimal Values of Machine Codes
00
01
02
03
04
05
06
07
08
09
OA
OB
OC
00
OE
OF
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
10
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
20
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
NOP
RTI
3D
TAP
TPA
INX
OEX
CLV
SEV
CLC
SEC
Cli
SEISBA
CBA
TAB
TBA
OAA
ABA
BRA
REL
BHI
BLS
BCC
BCS
BNE
BEQ
BVC
BVS
BPL
BMI
BGE
BLT
BGT
BLE
TSX
INS
PUL
PUL
DES
TXS
PSH
PSH
REL
REL
REL
REL
REL
REL
REL
REL
REL
REL
REL
REL
REL
REL
RTS
A
B
A
B
3E
3F
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
40
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
50
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
60
6E
6F
70
71
72
73
74
75
WAI
SWI
NEG
A
COM A
LSR A
ROR
ASR
ASL
ROL
DEC
A
A
A
A
A
INC
TST
A
A
CLR
NEG
A
B
COM
LSR
B
B
ROR
ASR
ASL
ROL
DEC
B
B
B
B
B
INC
TST
B
B
CLR
NEG
B
INO
COM
LSR
INO
INO
ROR
ASR
ASL
ROL
DEC
INO
INO
INO
INO
INO
INC
TST
JMP
CLR
NEG
INO
INO
INO
INO
EXT
COM
LSR
EXT
EXT
B1
B2
B3
B4
B5
B6
INC
EXT B7
TST
EXT B8
JMP
EXT· B9
CLR
EXT BA
SUB A IMM BB
CMP A IMM BC
SBC A IMM BO
BE
AND A IMM BF
BIT
A IMM CO
LOA A IMM C1
C2
EOR A IMM C3
AOC A IMM C4
ORA A IMM C5
ADD A IMM C6
CPX A IMM C7
BSR
REL C8
IMM C9
LOS
CA
SUB A OIR CB
CMP A OIR CC
SBC A OIR CD
CE
AND A OIR CF
BIT
A OIR
DO
01
LOA A OIR
STA A OIR
02
EOR A OIR
03
AOC A OIR
04
ORA A OIR
05
ADD A OIR 06
OIR
CPX
07
08
LOS
OIR
09
OA
STS
OIR
SUB A INO DB
CMP A INO DC
SBC A INO DO
DE
A4 AND A INO
OF
A5 BIT
A INO EO
A6 LOA A INO E1
A7 STA A INO E2
A8 EOR A INO E3
A9 AOC A INO E4
AA ORA A INO E5
AB ADD A INO E6
AC CPX
INO E7
INO E8
AD JSR
INO E9
AE LOS
AF STS
INO EA
BO SUB A EXT EB
76
77
78
79
7A
7B
7C
70
7E
7F
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
80
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
90
9E
9F
AO
A1
A2
A3
ROR
ASR
ASL
ROL
DEC
EXT
EXT
EXT
EXT
EXT
CMP
SBC
A EXT
A EXT
AND
BIT
LOA
STA
EOR
AOC
ORA
ADD
CPX
JSR
LOS
STS
SUB
CMP
SBC
A
A
A
A
A
A
A
A
AND
BIT
LOA
B IMM
B IMM
B IMM
EOR
AOC
ORA
ADD
B
B
B
B
EXT
EXT
EXT
EXT
EXT
EXT
EXT
EXT
EXT
EXT
EXT
EXT
B IMM
B IMM
B IMM
EC
ED
EE
EF
FO
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FO
FE
FF
LOX
STX
SUB
CMP
SBC
INO
INO
B EXT
B EXT
B EXT
AND
BIT
LOA
STA
AOC
AOC
ORA
ADD
B
B
B
B
B
B
B
B
LOX
STX
IMM
IMM
IMM
IMM
LOX
IMM
SUB
CMP
SBC
B OIR
B OIR
B OIR
AND
BIT
LOA
STA
EOR
AOC
ORA
ADD
B
B
B
B
B
B
B
B
LOX
STX
SUB
CMP
SBC
OIR
OIR
B INO
B IND.
B INO
OIR
OIR
OIR
OIR
OIR
OIR
OIR
OIR
AND B INO
BIT
B INO
LOA B INO
STA - B INO
EOR B INO
AOC B INO
ORA B INO
ADD B INO
Notes
1. Addressing Modes:
A
B
= Accumulator A
= Accumulator B
IMM
OIR
2. Unassigned code indicated by an asterisk (.)
5·21
--------~-
= Immediate
= Direct
REL
= Relative
INO
= Indexed
EXT
EXT
EXT
EXT
EXT
EXT
EXT
EXT
EXT
EXT
•
F6800/F68AOO/F68BOO
Table 4 Accumulator and Memory Operations
The accumulator and memory operations and their effect on the CCR are shown in Table 4.
Included are Arithmetic Logic, Data Test and Data Handling instructions.
Add .... ing Mod••
Operations
Add
Immed
Direct
Index
Boolean/Arithmetic Operation
Extnd
Impliad
(All register labels
OP
- = OP - = OP - = OP - = OP - =
ADDA
86
2
2 9B
3
2 AB
5
ADDB
CB
2
2 .DB
3
2
EB
5
2 BB
2· FB
refer to contents
Condo Code Reg ••
S
4
3
2
1
0
H
I
N
Z
V
C
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
R
I
I
R
I
I
R
I
I
R
R
S
R
R
S
R
R
R
S
R
R
I
I
I
I
I
I
I
I
4
3
A + M-A
I
4
3
B + M-B
I
A+B-A
I
Add Acmltrs
ABA
Add with Carry
ADCA
89
2
2
99
3
2
A9
5
2
B9
4
3
A+M+C-A
I
ADCB
C9
2
2
D9
3
2
E9
5
2
F9
4
3
B+M+C-B
I
And
Bit Test
I
Mnemonic
Clear
Compare
lB
2
1
ANOA
84
2
2
94 ·3
2
A4
5
2
B4
4
3
A. M - A
AN DB
C4
2
2
D4
3
2
E4
5
2
F4
4
3
B. M - B
BITA
85
2
2
95
3
2
A5
5
2
B5
4
3
A·M
BITB
C5
2
2
D5
3
2
E5
5
2
F5
4
3
B·M
6F
7
2
7F
6
3
CLR
4F
2
1
00 - A
CLRB
5F
2
1
00 - B
CMPA
81
2
2
91
3
2
A1
5
2
B1
4
3
A-M
CMPB
Cl
2
2
D1
3
2
E1
5
2
F1
4
3
B-M
63
·7
2
73
6
3
Compare Acmltrs
CBA
Complement, Is
COM
11
2
1
43
2
1
A-A
53
2
1
B-B
OO-M-M
Complement, 2s
NEG
(Negate)
NEGA
40
2
1
OO-A-A
NEGB
50
2
1
OO-B-B
Decimal Adjust, A
DAA
19
2
1
Converts Binary Add. of BCD
Decrement
DEC
2
70
•
•
M-M
COMB
7
•
•
•
A-B
COMA
60
•
00 - M
CLRA
6
3
Characters into BCD Format
6A
7
2
7A
6
DECA
DECB
Exclusive OR
EORA
88
2
2
98
3
2
EORB
C8
2
2
D8
3
2
Increment
INC
Load Acmitr
Or, Inclusive
Push Data
Pull Data
A8
5
2
B8
4
M -1 - M
3
4A
2
1
A-I - A
5A
2
1
B-1 - B
3
A
+
M-A
+
M-B
E8
5
2
F8
4
3
B
6C
7
2
7C
6
3
M + 1- M
INCA
4C
2
1
A + 1- A
INCB
5C
2
1
B + 1- B
LDAA
86
2
2
96
3
2
A6
5
2
B6
4
3
M-A
LDAB
C6
2
2
D6
3
2
E6
5
2
F6
4
3
M-B
ORAA
8A
2
2
9A
3
2 AA
5
2
BA
4
3
A+M-A
ORAB
CA
2
2 DA
3
2 EA
5
2 FA
4
3
B + M -.B
PSHA
36
4
1
A - Msp, SP - 1 - SP
PSHB
37
4
1
B - Msp, SP - 1 - SP
PULA
32
4
1
SP + 1 - SP, Msp - A
PULB
33
4
1
SP + 1 - SP, Msp - B
5·22
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
• •
•
•
•
•
•
•
• •
• •
• •
• •
• •
•
• •
• •
•
•
•
•
R
I
I
I
I
I
I
R
S
I
I
R
5
I
I
R
S
I
I
1
2
I
I
1
2
I
I
1
2
I
I
I
3
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
.. •• ••
• •
• •
•
•
4
•
R
•
R
•
5 •
5 •
5 •
R •
R
•
R •
R
•
• •
• •
• •
• •
4
4
F6800/F68AOO/F68BOO
Table 4
Accumulator and Memory Operations (Cont.)
Addressing Mode.
Operations
Mnemonic
Immad
Direct
-
-
OP
Rotate Left
Rotate Right
= OP
Index
= OP '-
ROL
69
7
Boolean/Arithmetic Operation
Extnd
Implied
= OP
-
= OP
2
6
3
79
-
=
(All register labels
ralar to contents
M
ROLA
49
2
1
A
ROLB
59
2
1
B
ROR
66
7
2
76
6
}L{]-II I I II I IIJ
C
I I I I I IJ
}CD-II
C
b7
bO
46
2
1
A
RORB
56
2
1
:}
ASL
Arithmetic
ASLA
48
2
1
ASLB
58
2
1
7
2
2
78
6
3
Shift Left,
67
7
6
B
M
3
0-111
b7
C
}DI -III
Shift Right,
ASR
Arithmetic
ASRA
47
2
1
A
ASRB
57
2
1
B
A }O-i I
b7
B
77
LSR
Logic
LSRA
44
2
1
LSRB
54
2
1
Store Acmltr
Subtract
7
2
74
6
11
b7
M
Shilt Right,
64
3
STAA
97
4
2
A7
6
2
B7
5
3
A-M
STAB
07
4
2
E7
6
2
F7
5
3
B-M
90
SUBA
60
2
2
3
2
AO
5
2
80
4
3
A- M - A
SUBB
CO
2
2 DO 3
2
EO
5
2
FO
4
3
B- M - B
A- B - A
SBA
Subtr, with Carry
SBCA
82
2
2 92
3
2
A2
5
2
B2
4
3
A-M-C-A
SBCB
C2
2
2 02 3
2
E2
5
2
F2
4
3
B-M-C-B
10
TAB
TBA
1
16
2
1
A-B
17
2
1
B-A
M - 00
Test, Zero
TST
or Minus
TSTA
40
2
1
A - 00
TSTB
50
2
1
B - 00
60
7
2
70
2
6
-
II
Subtract Acmltrs
Transler Acmltrs
3
Note
Accumulator addressing mode instructions are included in the column for IMPLIED addressing
·See condition code register notes page 26
Legend:
OP
Operation Code (Hexadecimal);
Number 01 MPU Cycles;
#
Number of Program Bytes;
+
Arithmetic Plus;
Arithmetic Minus;
Boolean AND;
Msp
Contents of memory locatiol1
pointed to be Stack Pointer;
+
Boolean Inolusive OR;
Boolean Exclusive OR;
M
Complement of M;
~
Transfer Into;
O B i t = Zero;
00
By1e = Zero;
e
Condition Code Symbols:
H
Half·carry from bit 3;
I
Interrupt mask
N
Negative (sign bit)
Z
Zero (by1e)
V
Overflow. 2's complement
C
Carry from bit 7
R
Reset Always
S
Set Always
Test and set if true. cleared otherwise
Not Affected
5-23
bO
M
3
RORA
68
-
b7
-
IIII
11-0
bO
Condo Code Reg ••
5
4
3
2
1
0
H
I
N
Z
V
C
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
I
I
6
I
I
I
6
I
I
I
6
I
I
I
6
I
I
I
6
I
I
I
6
I
I
I
6
I
I
I
6
I
I
I
6
I
I
I
6
I
I
I
6
I
I
I
6
I
R
I
6
I
R
I
6
I
R
I
6
I
I
I
R
I
I
R
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
R
I
I
R
•
I
I
R
R
I
I
R
R
I
I
R
R
N
Z
V
C
• •
11-0
bO
C
1 1 1 11-0
bO
C
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
H
I
•
•
•
•
•
F6800/F68AOO/F68BOO
Program Control Operations
register. This causes'the next byte to 'be pulled from the'
stack to come from the location indicated by the index
register. The utility of these two instructions can be, clarified
by describing the stack concept relative to the
F6800 system.
Program Control operation can be subdivided into two
categories: (1) index register / stack pointer instructions; (2)
jump and branch operations.
The stack can be thought of as a sequential list of data
stored in the MPU's read/write memory. The stack pointer
contains a 16-bit memory address that is used to access the
list from one end on a last-in-first-out (LIFO) basis in contrast
to the random access mode used by the MPU's other
addressing modes.
Index Register/Stack POinter Operations
The instructions for direct operation on the MPU's index
register and stack pointer are summarized in Table 5.
Decrement (OEX, DES), increment (lNX, INS), load (LOX,
LOS), and store (STX, STS) instructions are provided for
both. The compare instruction, CPX, can be used to compare
the index register to a 16-bit value and update the, condition
code register accordingly.
The F6800 instruction set and interrupt structure allow
extensive ~se of the stack concept for efficient handling of
data movement, subroutines and interrupts. The instructions
can be used to establish one or more stacks anywhere in
read/write memory. Stack length is limited only by the
amount of memory that is made available.
The TSX instruction causes the index register to be loaded
with the address of the last data byte put onto the stack.
The TXS instruction loads the stack pointer with a value
equal to one less than the current contents of the index
Table 5
Index Register and Stack Pointer Instructions
Immed
Pointer
Operations
Mnemonic
Direct
Index
Extend
OP
-
# OP
-
# OP
-
# OP
8C
3
3 9C
4
2
AC
6
2
-
Condo Code Reg.·
Implied
# OP
-
#
Boolean/Arithmetic
Operation
Compare
.Index Reg
CPX
Decrement
Index Reg
DEX
09
4
1
X-1-X
DES
34
4
1
SP - 1 - SP
Increment
Index Reg
iNX
08
4
1
X+1-X
Increment
Stack Pntr
iNS
31
4
1
SP + 1 - SP
Load
Index Reg
LOX
CE
3
3
DE
4
2
EE
6
2
FE
5
3
M - XH, (M + 1) - XL
Load
Stack Pntr
LOS
8E
3
3
9E
4
2
AE
6
2
BE
5
3
M - SPH, (M + 1) - SPL
Store
Index Reg
STX
OF
5
2
EF
7
2
FF
6
3
XH - M, XL - (M + 1)
Store
Stack Pntr
STS
9F
5
2
AF
7
2 BF 6
3
SPH - M, SPL - (M + 1)
Indx Reg Stack Pntr
TXS
35
4
1
X - 1 - SP
Stack Pmr Indx Reg
TSX
30
4
1
SP + 1 - X
Decrement
Stack Pntr
BC 5
3
XH - M, XL - (M + 1)
;
·See condition code register notes page 26
5-24
5
4
3
2
1
H
I
N
Z
V
.
0
C
• • (j) ® •
• • • • •
• • • • • •
• • • • •
• • • • • •
I
I
I
• •®
• •®
•
.®
I
R
I
R
I
R
•
•
•
• •® I R •
• • • • • •
• • • • • •
F6800/F68AOO/F68BOO
Operation of the stack pointer with the push and pull
instructions is illustrated in Figures 8 and 9. The push
instruction (PSHA) causes the contents of the indicated
accumulator (A in this example) to be stored in memory at
the location indicated by the stack pointer. The stack pOinter
is automatically decremented by one following the siorage
operation and is "pointing" to the next empty stack location.
The pull instruction (PULA or PU.LB) causes the last byte
stacked to be loaded into the appropriate accumulator. The
stack pointer is automatically incremented by one just prior
to the data transfer so that it will point to the last byte
stacked rather than the next empty location. Note that the
pull instruction does not remove the data from memory; in the
example, 1A is still in location (m + 1) following execution of
PULA. A subsequent push instruction would overwrite that
location with the new pushed data.
is pushed onto the stack. For both of these instructions, the
return address is the memory location following the bytes of
code that correspond to the BSR and JSR instruction. The
code required for BSR or JSR may be either two or three
bytes, depending on whether the JSR is in the indexed (two
bytes) or the extended (three bytes) addressing mode.
Before it is stacked, the program counter is automatically
incremented the correct number of times to be pointing at the
location of the next instruction. The return from subroutine
instruction, RTS, causes the return address to be retrieved
and loaded into the program counter as shown in Figure 14.
There are several operations that cause the status of the
MPU to be saved on the stack. The software interrupt (SWI)
and wait for injerrupt (WAI) instructions as well as the
maskable (IRQ) and non-maskable (NMI) hardware interrupts
all cause the MPU's internal registers (except for the stack
, pointer itself) to be stacked as shown in Figure 16. MPU
status is restored by the return from interrupt, RTI, as shown
in Figure 15.
Execution of the branch to subroutine (BSR) and jump to
subroutine (JSR) instructions cause a return address to be
saved on the stack as shown in Figures 11 through 13. The
stack is decremented after each byte of the return address
Fig. 8
Stack Operation, Push Instruction
MPU
ACCA
m
~m- 2
m - 2
.,'"'"
m-1
SP~m
PREVIOUSLY
STACKED
DATA
NEW DATA m
l-
1m ++ 1
7F
m
m
e
e
c
SP----.m -1
2
63
+3
FD
-
PREVIOUSLY
STACKED
F3
r+
7F
1
m+2
DATA m + 3
63
FD
3C
3C'
PC _ _
P$HA
NEXT INSTR
(b) AHER PSHA
(a) BEFORE PSHA
5-25
5
F6800/F68AOO/F68BOO
Fig. 9
Stack Operation, Pull Instruction
MPU
EEl
ACCA
-
r-m -2
m-l
I
MPU
m -2
m-l
SP--+-m
PREVIOUSLY m + 1
STACKED m+ 2
DATA
+3
m
m
lA
-
1A
m+2
3C
PREVIOUSLY
3C
STAg~~~
D5
I
S p - m+1
m+
EC
3::::.~D~5:::~
EC
PC
PULA
PC_
(a) BEFORE PULA
NEXT INSTR
- -
Fig. 10 Program Flow for Jump and Branch Instructions
I
~
n+ 1
INDXD
X+K
~
MAIN PROGRAM
.....---....,
n+l
~--T"'--"
'---_......
..-.....J~~
K
(n+2) ±K
INEXT INSTRUCTION I
Program Flow for BSR
,
m_2~
~
SP~m-2
m-1
7E
7A
pc·....... n
-
+1
±K
n
n+2
-
m -1
(n +2)H
m
(n +2)L
sP ......... m
m +1
~
_ _ _ _ _...
·K = SIGNED NIIT VALUE
(b) BRANCH
(a) JUMP
Fig. 11
. . . --r--...
m+l
-
- -7E
r-
BSR
BSR
=OFFSET·
n
-
NEXT MAIN INSTR
+1
±K
=OFFSET
n+2 NEXT MAIN INST
-
· K = SIGNED 7-BIT
VALUE
PC"'(n +2) ±K
lSTSUBRINSTR
(a) BEFORE EXECUTION
(b) AFTER EXECUTION
5·26
F6800/F68AOO/F68BOO
Fig. 12
Program Flow for JSR (Extended)
-
~
m- 2
m -1
m- 3
SP ...... m - 2
SP ....... m
m -1
m +1
7E
m +2
7A
m +1
7D_
m +2
-
PC_n
(n+3)H
(n + 3)L
-
7E
JSR~BD
n+1
!Itt = SUBR ADDR
n+2
SL = SUBRADDR
n+3
NEXT MAIN INSTR
JSR
n+1
SH = SUBR ADDR
n+2
SL = SUBR ADDR
n+3
NEXT MAIN INSTR
(a) BEFDRE EXECUTION
(S FORMED FROM
SHANDSL)
1--::::=::1
(b) AFTER EXECUTION
Fig. 13
Program Flow for JSR (Indexed)
sP ....... m -
m- 2
2
m-1
m -1
(n +2)H
SP--.m
m
(n +2)L
m+1
m+1
7E
7A
.JSR
PC--+-n
n+1
n+2
n+1
NEXT MAIN INSTR
*K
n+2
K
~
~
AD
OFFSET
NEXT MAIN INSTR
= a-BIT
UNSIGNED VALUE
PC- X· +K
1ST SUBR INSTR
(a) BEFORE EXECUTION
·CONTENTS OF
INDEX REGISTER
(b) AFTER EXECUTION
5·27
II
F6800/F68AOO/F68BOO
Fig. 14 Prollrlm Flow for RTS
- -
Sp-..m-2
m -1
,m
'm
+1
-
m-·2
("+3)H
m -1
("+3)l
SP:""""'m
7E
m+l
7~
-
JSR =10
JSR -BD
SH
SH = SUIR ADDR
"+'2
= SUBRADDR
IlL = SOBRADDR
SL - SUBR ADDR
" +3
NEXT MAIN INSTR
NEXT MAIN INSTR
lAST SUBR INSTR
lAST SUBR INSTR
" +1
--
RTS
RTS
Sn
(b) AFTER EXECUTION
(a) BEFORE EXECUTION
Flg.15
ProClrlm Flow for RTI
--...
SP--...m -7
m -8
m -5
m -4
m -3
m -2
m -6
CCR
ACCB
ACCB
X- (INDEX REG)
m -5
m -4
m- 3
XL (INDEX REG)
m-2
XL
+ l)H
PC(" + l)L
m -1
PCH
SP---.m
PCl
ACCA
m-l
PC("
m
" +1
Sn
PC_
m -7
CCR
7E_
NEXT MAIN INSTR
PC_" + 1
X-
-
7E_
NEXT MAIN INSTR
-
LAST INTER INSTR
LAST IIiTER INSTR
-
Sn
RTI
-....-
ACCA
RTI
-
(a) BEFORE EXECUTION
-
(b) AFTER EXECUTION
5·28
F6800/F68AOO/F68BOO
Fig. 16
Program Flow for Interrupts
n+1 1..-_ _ _...11
c>
SP
•
---+-m - 7
m -6
CONDITION CODE
m- 5
ACMLTR B
m -4
ACMLTR A
m- 3
INDEX REGISTER (X.)
m -2
INDEX REGISTER (Xu
m-1
PC(n + l)H
PC(n + l)L
SWI
HDWR
INT
WAI
NO
FFFA
FFFB
HDWR
INT
REO
NMI
NMI
WAIT LOOP
FFFC
FFFD
FFF8
FFF9
INTERRUPT MEMORY
ASSIGNMENT1
FFF8
CONSTANT, HDWARE
MS
FFF9
CONSTANT, HDWARE
LS
FFFA
SOFTWARE
MS
FFFB
SOFTWARE
LS
FFFC
NON-MASKABLE INT
MS
FFFD
NON·MASKABLE INT
LS
c:=>
FIRST INSTR
ADDR FORMED
BY FETCHING
2 BYTES FROM
PER MEM
ASSIGN
INTERRUPT PROGRAM
I 1ST INTERRUPT INSTR
FFFE
RESTART
MS
FFFF
RESTART
LS
Note
MS = Most Significant Address Byte
LS = Least Significant Addres. Byte
5·29
FFFE
FFFF
F6800/F68AOO/F68BOO
JU,mp and Branch Operation
The jump and branch instructions are summarized in Table 6.
These instructions are used to control the transfer of
operation from one point to another in the control program.
Execution of the jump instruction, JMP, and branch always,
BRA, affects program flow as shown in Figure 10. When the
MPU encounters the jump (indexed) instruction, it adds the
offset to the value in the index register and uses the result
as the address of the next instruction to be executed. In the
extended addressing mode, the address of the next
instruction to be executed is fetched from the two locations
immediately following the JMP instruction. The branch always
(BRA) instruction is similar to the JMP (extended) instruction
except that the relative addressing mode applies and the
branch is limited to the range within -125 or +127 bytes of
the branch instruction itself. The opcode for the BRA
instruction requires one less byte than JMP (extended) but
takes,one more, cycle to execute.
The no operation instruction, NOP, while included here, is a
jump operation in a very limited,sense. Its only effect ill to
increment the program counter by one. It is useful during
program development as a stand-in for some other
instruction that is to be determined during debug. It is also
used for equalizing the executidn time through alternate
paths in a control program.
Table 6
Jump and Branch Instructions
Relative
Operations
Mnemonic
OP
Branch Always
Branch if Carry Clear
Branch if Carry Set
Branch if = Zero
Branch if ;,: Zero
Branch if > Zero
Branch if Higher
Branch if :5 Zero
Branch if lower or Same
Branch if < Zero
Branch if Minus
Branch if not Equal Zero
Branch if Overflow Clear
Branch if Overllow Set
Branch if Plus
Branch to Subroutine
Jump
Jump to Subroutine
No Operation
Return from Interrupt
Aeturn from Subroutine
Software Interrupt
Wait for Interrupt'
BRA
BCC
BCS
BEQ
BGE
B,GT
BHI
BlE
BlS
BlT
BMI
BNE
BVC
BVS
BPl
BSR
JMP
JSR
NOP
ATI
RTS
SWI
WAI
20
24
25
27
2C
2E
22
2F
23
20
2B
26
28
29
2A
80
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
8
Index
# OP
-
Extend
# OP
-
Condo Code Reg. t
Implied
# OP
-
Branch Test
#
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
None
C=O
C = 1
Z = 1
N + V =
Z + (N +
C+Z=O
Z + (N +
C +'Z = 1
N + V=
N = 1
Z = 0
V = 0
V = 1
N = 0
6E 4
AD 8
2 7E 3
2 BO 9
3
3
'WAI puts address bus, R/W, and data, bus in the 3'state mode while VMA is held LOW.
tSee condition code register notes page 26.
5-30
V) =1
1
} See SpeCial Operations
01 2 1
3B 10 1
39 5 1
3F 12 1
3E 9 1
-
0
V) = 0
Advances Prog, Cntr. Only
5
4
3
2
1
H
I
N
Z
V C
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
• • •
0
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
--@-} See Special 'Operations
• • • •
·I(• ·•)1·1·1·1·
• @ ••••
F6800/F68AOO/F68BOO
The effect on program flow for the jump to subroutine (JSR)
and branch to subroutine (BSR) is shown in Figures 11
through 13. Note that the program counter is properly
incremented to be pointing at the correct return address
before it is stacked. Operation of the branch to subroutine
and jump to subroutine (extended) instruction is similar
except for the range. The BSR instruction requires less
opcode than JSR (2 bytes versus 3 bytes) and also executes
one cycle faster than JSR. The return from subroutine, RTS,
is used at the end of a subroutine to return to the main
program as indicated in Figure 14.
was negative or positive, respectively.
2. Branch on equal (BEQ) and branch on not equal
(BNE) are used to test the zero status bit, Z, to
determine whether or not the result of the previous
operation was equal to zero. These two instructions are
useful following a compare (CMP) instruction to test for
equality between an accumulator and the operand.
They are also used following the bit test (BIT) to
determine whether or not the same bit positions are set
in an accumulator and the operand.
3. Branch on overflow clear (BVC) and branch on
overflow set (BVS) tests the state of the V bit to
determine if the previous operation caused an
arithmetic overflow.
4. Branch on carry clear (BCC) and branch on carry
set (BCS) tests the state of the C bit to determine if
the previous operation caused a carry to occur. BCC
and BCS are useful for testing relative magnitude when
the values being tested are regarded as unsigned
binary numbers, that is, the values are in the range 00
(lowest) to FF (highest). BCC following a comparison
(CMP) will cause a branch if the (unsigned) value in the
accumulator is higher than or the same as the value of
the operand. Conversely, BCS will cause a branch if
the accumulator value is lower than the operand.
The effect of executing the software interrupt, SWI, and the
wait for interrupt, WAI, and their relationship to the hardware
interrupts is shown in Figure 15. SWI causes the MPU
contents to be stacked and then fetches the starting address
of the interrupt routine from the memory locations that
respond to the addresses FFFA and FFFB. Note that as in
the case of the subroutine instructions, the program counter
is incremented to point at the correct return address before
being stacked. The return from interrupt instruction, RT!,
(Figure 15) is used at the end of an interrupt routine to
restore control to the main program. The SWI instruction is
useful for inserting break points in the control program, that
is, it can be used to stop operation and put the MPU
registers in memory where they can be examined. The WAI
instruction is used to decrease the time required to service a
hardware interrupt; it stacks the MPU contents and then
waits for the interrupt to occur, effectively removing the
stacking time from a hardware interrupt sequence.
Fig. 17
The fifth complementary pair, branch on higher (BHI) and
branch on lower or same (BLS) are in a sense complements
to BCC and BCS. BHI tests for both C and Z = 0; if used
following a CMP, it will cause a branch if the value in the
accumulator is higher than the operand. Conversely, BLS will
cause a branch if the unsigned binary value in the
accumulator is lower than or the same as the operand.
Conditional Branch Instructions
BMI:
BPL:
N= 1 ;
N = "';
BEQ:
BNE:
Z = "';
Z= 1 ;
BVC:
BVS:
V = "';
V= 1 ;
BCC:
BCS:
C = "';
C=1
The remaining two pairs are useful in testing results of
operations in which the values are regarded as signed two's
complement numbers. This differs from the unsigned binary
case in the following sense: In unsigned, the orientation is
higher or lower; in signed two's complement, the comparison
is between larger or smaller where the range of values is
between -128 and +127.
BHI: C + Z = '" ;
BL T: N 0 V = 1 ;
BLS: C + Z = 1 ;
BGE: N 0 V = '" ;
BLE: Z + (N 0 V) = 1 ;
BGT: Z + (N 0 V) = '" ;
Branch on less than zero (BL T) and branch on greater than
or equal zero (BGE) test the status bits for N G1 V = "1"
and N G1 V = "0", respectively. BL T will always cause a
branch following an operation in which two negative numbers
were added. In addition, it will cause a branch following a
CMP in which the value in the accumulator was negative and
the operand was positive. BL T will never cause a branch
following a CMP in which the accumulator value was positive
and the operand negative. BGE, the complement to BL T, will
cause a branch following operations in which two positive
values were added or in which the result was zero.
The conditional branch instructions, Figure 17, consist of
seven pairs of complementary instructions. They are used to
test the results of the preceding operation and either
continue with the next instruction in sequence (test fails), or
cause a branch to another point in the program
(test succeeds).
Four of the pairs are used for simple tests of status bits N, Z,
V, and C:
1. Branch on minus (BMI) and branch on plus (BPL)
tests the sign bit, N, to determine if the previous result
The last pair, branch on less than or equal zero (BLE) and
5-31
•
I!
F6800/F68AOO/F68BOO
branch on greater than zero (BGT) test the -status bits for Z
ED (N + V) = "1" and zED (N + V) = "0", respectively.
The action of BlE is identical to that for Bl T except that a
branch will also occur if the result of the previous result was
zero. Conversely, BGT is similar to BGE except that no
branch will occur following a zero result.
the MPU that is useful in controlling program flow during
system operation. The bits-are defined in Figure 18.
The instructions shown in Table 7 are available to the user
for direct manipulation of the CCA. In addition, the MPU
automatically sets or clears the appropriate status bits as
many of the other instructions on the condition code register
were indicated as they were introduced.
Condition Code Register Operations
The condition code register (CCR) is a 6-bit register within
Table 7
Condition Code Register Instructions
Operations
Clear Carry
Clear Interrupt Mask
Clear Overflow
Set Carry
Set Interrupt Mask
Set Overflow
Acmltr A - CCR
CCR - Acmltr A
ClC
CLI
ClV
SEG
SEI
SEV
TAP
TPA
Condo Code Reg.·
Implied
Mnemonic
Boolean Operation
OP
-
#
OC
OE
OA
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
00
OF
OB
06
07
O-C
0-1
O-V
1 - C
1 - I
1 -V
A - CCR
CCR - A
R = Reset
S= Set
• = Not affected
t (ALL) Set according to tl1e contents of Accumulator A_
'See Condition Code Register notes below
5
.4
3
2
1
0
H
I
N
Z
V
C
•• .R• • •
• •
• • • •
• •
•• S• •• ••
@
..
..
• I • I • I • I
• R
•R ••
•• •S
S
•
•I•
Condition Code Register Notes: (Bit set if test is true and
cleared otherwise)
1 -(Bit V) Test: Result = 10000000?
8 (Bit V) Test: 2s complement overflow from subtraction of
MS bytes?
2 (Bit C) Test: Result = OOOOOOOO?
9 (Bit N) Test: Result less than "O"? (Bit 15
= 1)
3 (Bit C) Test: Decimal value of most significant BCD
character greater than nine? (Not c.leared if
previously set.)
10 (All)
load condition code register from stack.
(See Spacial Operations)
4 (Bit V) Test: Operand = 10000000 prior to execution?
11 (Bit I)
Set when interrupt occurs. If previously set,
a non-maskable interrupt is required to exit
the wait state.
12 (All)
Set according to the contents of
accumUlator A.
5 (Bit V) Test: Operand
=- 01111111
prior to execution?
6 (Bit V) Test: Set equal to result of N <:E> C after shift
has occurred.
7 (Bit N) Test: Sign bit of most significant (MS) byte = 1?
5·32
F6800/F68AOO/F68BOO
Fig.·18
Condition Code Register Bit Definition
Selection of the desired addressing mode is made by the
user as the source statements are written. Translation into
appropriate opcode then depends on the method used. If
manual translation is used, the addressing mode is inherent
in the opcode. For example, the immediate, direct, indexed,
and extended modes may all be used with the ADD
instruction. The proper mode is determined by selecting
(hexadecimal notation) 8B, 9B, AB, or BB, respectively.
bo
H
N
Z
v
C
H = Half-carry; set whenever a carry from b 3 to b 4 of the
result is generated by ADD, ABA, ADC; cleared if no b3
to b4 carry; not affected by other instructions.
The source statement format includes adequate information
for the selection if an assembler program is used to generate the opcode. For instance, the immediate mode is
selected by the assembler whenever it encounters the" #"
symbol in the operand field. Similarly, an "X" in the operand
field causes the indexed mode to be selected. Only the
relative mode applies to the branch instructions; therefore,
the mnemonic instruction itself is. enough for the assembler
to determine addressing mode.
Interrupt Mask; set by hardware or software interrupt or
SEI instruction; cleared by CLI instruction. (Normally not
used in arithmetic operations.) Restored to a zero as a
result of an RTI instruction if 1m stored on the stack is
LOW.
N
Negative; set if high order bit (b 7 ) of result is set;
cleared otherwise
Z
Zero; set if result = 0; cleared otherwise.
v
Overlow; set if there were arithmetic overflow as a
result of the operation; cleared otherwise.
C
Carry; set if there were a carry from the most
significant bit (b 7 ) of the result; cleared otherwise.
For the instructions that use both direct and extended
modes, the assembler selects the direct mode if the operand
value is in the range 0-255 and extended otherwise. There
are a number of instructions for which the extended mode is
valid but the direct is not. For these instructions, the
assembler automatically selects the extended mode even if
the operand is in the 0-255 range. The addressing modes are
summarized in Figure 19.
A CLI-WAI instruction sequence operated properly with early
F6800 processors only if the preceding instruction were odd.
(Least Significant Bit = "1".) Similarly it was advisable to
precede any SEI instruction with an odd opcode-such as
NOP. These precautions are not necessary for F6800
processors indicating manufacture in November, 1977
or later.
Inherent (Includes "Accumulator Addressing") Mode
The successive fields in a statement are normally separated
by one or more spaces. An exception to this rule occurs for
instructions that use dual addressing in the operand field and
for instructions that must distinguish between the two
accumulators. In these cases, A and B are "operands" but
the space between them and the operator may be omitted.
This is commonly done, resulting in apparent four character
mnemonics for those instructions.
Systems which require an interrupt window to be opened
under program control should use a CLI-NOP-SEI sequence
rather than CLI-SEI.
The addition instruction, ADD, provides an example of dual
addressing in the operand field:
Addressing Modes
The MPU operates on 8-bit binary numbers presented to it
via the data bus. A given number (byte) may represent either
data or an instruction to be executed, depending on where it
is encountered in the control program. The F6800 has 72
unique instructions; however, it recognizes and takes action
on 197 of the 256 possibilities that can occur using an 8-bit
word length. This larger number of instructions results from
the fact that many of the executive instructions have more
than one addressing mode.
or
Operator
ADD A
Operand
MEM12
AD DB
MEM12
Comment
ADD CONTENTS OF MEM12
TO ACCA
ADD CONTENTS OF MEM 12
TO ACCB
The example used earlier for the test instruction, TST, also
applies to the accumulators and uses the "accumulator
addressing mode" to designate which of the two
accumulators is being tested:
These addressing modes refer to the manner in which the
program causes the MPU to obtain its instructions and data.
The programmer must have a method for addressing the
MPU's internal registers and all of the external
memory locations.
or
5·33
Operator
TSTB
TSTA
Comment
TEST CONTENTS OF ACCB
TEST CONTENTS OF ACCA
F6800/F68AOO/F68BOO
Direct and Extended Addressing Modes
In the direct and extended modes of addressing, the operand
field of the source statement is the address of the value that
is to be operated on. The direct and extended modes differ
only in the range of memory locations to which they can
direct the MPU. Direct addressing generates a single a-bit
operand and, hence, can address only memory locations 0
through 255; a two byte operand is generated for extended
addressing, enabling the MPU to reach the remaining
memory locations, 256 through 65535. An example of direct
addressing and its effect on program flow is illustrated
in Figure 23.
A number of the instructions either alone or together with an
accumulator operand contain all of the address information
that is required, that is, "inherent" in the instruction itself.
For instance, the instruction ABA causes the MPU to add the
contents of accumulators A and B together and place the
result in accumulator A. The instruction INCB, another
example of "accumulator addressing", causes the contents
of accumulator B to be increased by one. Similarly, INX,
incrementing the index register, causes the contents of the
index register to be increased by one.
Program flow for instructions of this type is illustrated in
Figures 20 and 21. In these figures, the general case is
shown on the left and a specific example is shown on the
right. Numerical examples are in decimal notation.
Instructions of this type require only one byte of opcode.
Cycle-by-cycle operation of the inherent mode is shown
in Table 8.
Flg_ 19
The MPU, after encountering the opcode for the instruction
LDAA (direct) at memory location 5004 (program counter =
5004), looks in.the next location, 5005, for the address of
the operand. It then sets the program counter equal to the
Addressing Mode Summary
DIRECT:
DO INSTRUCTION
EXAMPLE: SUBS Z
ADOR. RANGE
= 0-255
&.
n+ 1
Z = OPRND ADDRESS
n+ 2
NEXT INSTR
IMMEDIATE:
INSTRUCTION
EXAMPLE: LDAA #K
(K = ONE-BVTE OPRND)
0+ 1
K = OPERAND
0+2
NEXT INSTR
OR
(K = TWD-BYTE DPRND)
(CPX, LOX, AND LOS)
I
INSTRUCTION
0+1
KH = OPERAND
K = OPERAND
n +,2
KL = OPERAND
OR
0+3
NEXTINSTR
0+ 1
± K = BANeI! OFFSET
(K = ONE-BYTE OPRND)
z
(I( = TWO-BYTE OPERAND)
Z I-_KH.;;.=...;.O_PE_R_A_N_D_-I
Z + 1 L.._K..;L;.=_O_PE_R_A_N_D_.1
INSTRUCTION
RELATIVE:
EXAMPLE: BNE K
(K =SlGNED 7-BIT VALUE) 0+2
NEXT INSTR
.&
NEXTINSTR
:&:1
ADDR. RANGE:
-125TO+129
RELATIVE TO o.
EXTENDED:
EXAMPLE: CMPA Z
ADDR. RANGE:
256-85535
&.
FO INSTRUCTION
,
o + 1 ZH = OPRND ADDRESS
o + 2 ZL = OPRND ADDRESS
o+3
("+2) ±K
&IF BRNCHT8t FALSE,
.&
I
IF BRNCHTst TRUE.
NEXT INSTR
INDEXED:
(K =ONE-BYTE OPRND)
Z
I
K = OPERAND
INSTRUCTION
EXAMPLE: ADDA Z, X
0+1
Z = OFFSET
ADDR. RANGE:
0-255 RELATIVE TD
INDEX REGISTER, X
0+2
NEXT INSTR
(Z = a-BIT UNSIGNED
VALUE)
X+Z
DR
(K = TWo-BVTE OPERAND)
Z
KH = OPERAND
Z+1
KL = OPERAND
5-34
I
K
=OPERAND
F6800/F68AOO/F68BOO
Table 8
Inherent Mode Cycle·by·Cycle Operation
Address Mode
and Instructions
Address Bus
Data Bus
Inherent
ABA
ASl
ASR
CBA
ClC
CLI
ClR
ClV
COM
DES
DEX
INS
INX
DAA
DEC
INC
lSR
NEG
NOP
ROl
ROR
SBA
SEC
SEI
SEV
TAB
TAP
TBA
TPA
TST
1
2
1
1
Op Code Address
Op Code Address + 1
1
1
Op Code
Op Code of Next Instruction
1
2
3
4
1
1
0
0
Op Code Address
Op Code Address + 1
Previous Register Contents
New Register Contents
1
1
1
1
Op Code
Op Code of Next Instruction
Irrelevant Data (Note 1)
Irrelevant Data (Note 1)
4
1
2
3
4
1
1
1
0
Op Code Address
Op Code Address + 1
Stack Poi nter
Stack Pointer -1
1
1
0
1
Op Code
Op Code of Next Instruction
Accumulator Data
Accumulator Data
4
1
2
3
4
1
1
0
1
Op Code Address
Op Code Address + 1
Stack Poi nter
Stack Poi nter + 1
1
1
1
1
Op Code
Op Code of Next Instruction
Irrelevant Data (Note 1)
Operand Data from Stack
1
2
1
1
0
0
Op Code Address
Op Code Address + 1
Stack Poi nter
New Index Register
1
1
1
1
Op Code
Op Code of Next Instruction
Irrelevant Data (Note 1)
Irrelevant Data (Note 1)
3
4
1
1
0
0
Op Code Address
Op Code Address + 1
Index Register
New Stack Pointer
1
1
1
1
Op Code
Op Code of Next Instruction
Irrelevant Data
Irrelevant Data
1
2
3
4
1
1
0
1
Op Code Address
Op Code Address + 1
Stack Pointer
Stack Poi nter + 1
1
1
1
1
5
1
Stack Poi nter + 2
1
Op Code
Irrelevant Data (Note 2)
Irrelevanl Data (Note 1)
Address of Next Instruction
(High Order Byte)
Address of Next Instruction
(low Order Byte)
2
4
PSH
PUl
TSX
4
TXS
4
RTS
5
3
4
1
2
5·35
--~~-
- - - - - - ---------
------
F6800/F68AOO/F68BOO
Table 8
Inherent Mode Cycl.by·Cycle Operation (Cont.)
Address Mode
and Instructions
Address Bus
Data Bus
Inherent (Cont'd)
WAI
9
RTI
10
SWI
12
1
2
3
4
5
6
7
8
9
1
1
1
1
1
1
1
1
1
Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer - 1
Stack POinter - 2
Stack Pointer - 3
Stack Pointer - 4
Stack Pointer - 5
Stack Pointer - 6 (Note 3)
1
1
0
0
0
0
0
0
1
Op Code
Op Code of Next Instruction
Return Address (Low Order Byte)
Return Address (High Order Byte)
Index Register (Low Order Byte
Index Register (High Order Byte)
Contents of Accumulator A
Contents of Accumulator B
Contents of Condo Code Register
1
2
3
4
1
1
0
1
Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer + 1
1
1
1
1
5
6
7
1
1
1
Stack Pointer + 2
Stack Pointer + 3
Stack Pointer + 4
1
1
1
8
1
Stack Pointer + 5
1
9
1
Stack POinter + 6
1
10
1
Stack Pointer + 7
1
Op Code
Irrelevant Data (Note 2)
Irrelevant Data (Note 1)
Contents of Condo Code Register from
Stack
Contents of Accumulator B from Stack
Contents of Accumulator A from Stack
Index Register from Stack
(High Order Byte)
Index Register from Stack
(Low Order Byte)
Next Instruction Address from Stack
(High Order Byte)
Next Instruction Address from Stack
(LOw Order Byte)
1
2
3
4
5
6
7
8
9
10
11
12
1
1
1
1
1
1
1
1
1
0
1
1
Op Code Address
Op Code Address + 1
Stack Poi nter
Stack Pointer - 1
Stack POinter - 2
Stack Pointer - 3
Stack POinter - 4
Stack POinter - 5
Stack Pointer - 6
Stack Pointer - 7
Vector Address FFFA (Hex)
Vector Address FFFB (Hex)
1
1
0
0
0
0
0
0
0
1
1
1
Op Code
Irrelevant Data (Note 1)
Return Address (Low Order Byte)
Return Address (High Order Byte)
Index Register (Low Order Byte)
Index Register (High Order Byte)
Contents of Accumulator A
Contents of Accumulator B
Contents of Condo Code Register
Irrelevant Data (Note 1)
Address of Subroutine (High Order Byte)
Address of Subroutine (Low Order Byte)
Notes
1. If device which is addressed during this cycle uses VMA. then the data bus will go to the high impedance 3-state condition. Depending on bus
capacitance, data from the previous cycle may be retained on the data bus.
2. Data is ignored by the MPU.
3. While the MPU is waiting for the interrupt, Bus Available will go HIGH indicating the following states of the control lines: VMA is LOW; address bus,
R/W, and data bus are all in the high impedance state.
5-36
F6800/F68AOO/F68BOO
Fig. 20
Fig. 22
Inherent Addressing
Immediate Addressing Mode
MPU
MPU
PC
PC
~
5002
EXAMPLE
GENERAL FLOW
PC
~ 5000
t--;';';"--I,
Fig. 23
EXAMPLE
GENERAL FLOW
Fig. 21
Direct Addressing Mode
Accumulator Addressing
AOOR
t-....;=--f'
PC
PC
+ 1 I-";:'~~-II
ADOR
=
100
t-----I\.
PC == 5004
5005
AOOR - 0 $: 255
GENERAL FLOW
PC
PC
GENERAL FLOW
~
5001
EXAMPLE
5·37
EXAMPLE
•
F6800/F68AOO/F68BOO
Table 9
Immediate Mode Cycle·by·Cycle Operation
Address Mode
and Instructions
Data Bus
Address Bus
Immediate
ADC
ADD
AND
BIT
CMP
EOR
LOA
ORA
SBC
SUB
CPX
LOS
LOX
1
2
1
1
Op Code Address
Op Code Address + 1
1
1
Op Code
Operand Data
1
2
1
1
1
Op Code Address
Op Code Address + 1
Op Code address + 2
1
1
1
Op Code
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
2
3
3
Table 10
Direct Mode Cycle·by·Cycle Operation
Address Mode
and Instructions
Data Bus
Address Bus
Direct
ADC
ADD
AND
BIT
CMP
CPX
LOS
LOX
EOR
LOA
ORA
SBC
SUB
Op Code Address
Op Code Address + 1
Address of Operand
1
1
1
Op Code
Address of Operand
Operand Data
3
3
1
1
1
4
1
2
3
4
1
1
1
1
Op Code Address
Op Code Address + 1
Address of Operand
Operand Address + 1
1
1
1
1
Op Code
Address of Operand
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
4
1
2
3
4
1
1
0
1
Op Code Address
Op Code Address + 1
Destination Address
Destination Address
1
1
1
0
Op Code
Destination Address
Irrelevant Data (Note)
Data from Accumulator
5
1
2
3
4
5
1
1
0
1
1
Op Code Address
Op Code Address + 1
Address of Operand
Address of Operand
Address of Operand + 1
1
1
1
0
0
Op Code
Address of Operand
Irrelevant Data (Note)
Register Data (High Order Byte)
Register Data (Low Order Byte)
1
2
STA
STS
STX
Nole
If device which is addressed during this cycle uses VMA, then the data bus will go to the high impedance 3-state condition. Depending on bus
capacitance, data from the previous cycle may be retained on the data bus.
5·38
F6800/F68AOO/F68BOO
with the "#" symbol. Program flow for this addressing mode
is illustrated in Figure 22.
value found there (100 in the example) and fetches the
operand, in this case a value to be loaded into accumulator
A, from that location. For instructions requiring a 2-byte
operand such as LOX (load the index register), the operand
bytes would be retrieved from locations 100 and 101. Table
10 shows the cycle-by-cycle operations for the direct mode
of addressing.
The operand format allows either properly defined symbols
or numerical values. Except for the instructions CPX, LOX,
and LOS, the operand may be any value in the range 0 to
255. Since compare index register (CPX), load index register
(LOX), and load stack pointer (LOS), require 16-bit values,
the immediate mode for these three instructions requires
two-byte operands. In the immediate addressing mode, the
"address" of the operand is effectively the memory location
immediately following the instruction itself. Table 9 shows the
cycle-by-cycle operation for the immediate addressing mode.
Extended addressing, Figure 24, is similar except that a twobyte address is obtained from locations 5007 and 5008 after
the LOAB (extended) opcode shows up in location 5006.
Extended addressing can be thought of as the standard
addressing mode, that is, it is a method of reaching any
place in memory. Direct addressing, since only one address
byte is required, provides a faster method of processing data
and generates fewer bytes of control code. In most
applications, the direct addressing range, memory locations
0-255, are reserved for RAM. They are used for data
buffering and temporary storage of system variables, the
area in which faster addressing is of most value. Cycle-bycycle operation is shown in Table 11 for extended
addressing.
Relative Addressing Mode
In both the direct and extended modes, the address obtained
by the MPU is an absolute numerical address. The relative
addressing mode, implemented for the MPU's branch
instructions, specifies a memory location relative to the
program counter's current location. Branch instructions
generate two bytes of machine code, one for the instruction
opcode and one for the "relative" address. (See Figure 25.)
Since it is desirable to be able to branch in either direction,
the 8-bit address byte is interpreted as a signed 7 -bit value;
the 8th bit of the operand is treated as a sign bit, "0" = plus
and "1" = minus. The remaining seven bits represent the
numerical value. This results in a relative addressing range of
± 127 with respect to the location of the branch instruction
itself. However, the branch range is computed with respect
to the next instruction that would be executed if the branch
conditions are not .satisfied. Since two bytes are generated,
the next instruction is located at PC + 2. If 0 is defined as
the address of the branch designation, the range is then:
Fig_ 24. Extended Addressing Mode
ADDR=300 ~__~__~
ADDR
or
5006
1-______-1
5009
ADOR 256
----_.
GENERAL FLOW
EXAMPLE
pc
pc
=
I-~=--II\
Operand
#25
+ 2) +
127
that is, the destination of the branch instruction must be
within -125 to + 129 memory locations of the branch
instructions itself. For transferrring control beyond this range,
the unconditional jump (JMP), jump to subroutine (JSR), and
return from subroutine CRTS) are used.
In Figure 25, when the MPU encounters the opcode for BEQ
(branch if result of last instruction was zero), it tests the zero
bit in the condition code register. If that bit is "0", indicating
a non-zero result, the MPU continues execution with the next
instruction (in location 5010 in Figure 25). If the previous
result were zero, the branch condition is satisfied and the
MPU adds the offset, 15 in this case, to PC + 2 and
branches to location 5025 for the next instruction.
Immediate Addressing Mode
In the immediate addressing mode, the operand is the value
that is to be operated on. For instance, the instruction
Operator
LOAA
(PC + 2) - 127.$ 0 .$ (PC
PC - 125 .$ 0 .$ PC + 129
Comment
LOAD 25 INTO ACCA
causes the MPU to "immediately load accumulator A with the
value 25"; no further address reference is required. The
immediate mode is selected by preceding the operand value
5-39
•
F6800/F68AOO/F68BOO
Table 11
Extended Mode Cycle·by·Cycle Operation
Address Mode
and Instructions
bata Bus
Address Bus
Extended
6
1
2
3
4
5
6
1
1
1
0
1
1
Op Code Address
Op Code Address + 1
Op Code Address + 2
Address of Operand
Address of Operand
Address of Operand +1
1
1
1
1
0
0
Op Code
Address of Operand (High Order Byte)
Address of Operand (Low Order Byte)
Irrelavant Data (Note 1)
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
9
1
2
3
4
5
6
'1
8
9
1
1
1
1
1
1
0
0
1
Op Code Address
Op Code Address + 1
Op Code Address + 2
Subroutine Starting Address
Stack Pointer
Stack Pointer -1
Stack Pointer - 2
Op Code Address + 2
Op Code Address + 2
1
1
1
1
0
0
1
1
1
Op Code
Address of Subroutine (High Order Byte)
Addres.s of Subroutine (Low Order Byte)
Op Code of Next Instruction
Return Address (Low Order Byte)
Return Address (High Order Byte)
Irrelevant Data (Note 1)
Irrelevant Data (Note 1)
Address of Subroutine (Low Order Byte)
3
1
2
3
1
1
1
Op Code Address
Op Code Address + 1
Op Code Address + 2
1
1
1
Op Code
Jump Address (High Order Byte)
Jump Address (Low Order Byte)
1
2
3
4
1
1
1
1
Op Code .Address
Op Code Address + 1
Op Code Address + 2
Address of Operand
1
1
1
1
Op Code
Address of Operand (High Order Byte)
Address of Operand (Low Order Byte)
Operand Data
1
2
3
4
5
1
1
1
1
1
Op Code Address
Op Code Address + 1
Op Code Address + 2
Address of Operand
Address of Operand + 1
1
1
1
1
1
Op Code
Address of Operand (High Order Byte)
Address of Operand (Low Order Byte)
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
2
3
4
5
1
1
1
0
1
Op Code Address
Op Code Address + 1
Op Code Address + 2
Operand Destination Address
Operand Destination Address
1
1
1
1
0
Op Code
Destination Address (High Order Byte)
Destination Address (Low Order Byte)
Irrelevant Data (Note 1)
Data from Accumulator
Op Code Address
Op Code Address + 1
Op Code Address + 2
Address of Operand
Address of Operand
Address of Operand
1
1
1
1
1
0
Op Code
Address of Operand (High Order Byte)
Address of Operand (Low Order Byte)
Curent Operand Data
Irrelevant Data (Note 1)
New Operand Data (Note 2)
STS
STX
JSR
JMP
ADC
ADD
AND
BIT
CMP
EOR
LOA
ORA
SBC
SUB
CPX
LOS
LOX
STA
STA
4
5
A
B
5
ASL
ASR
CLR
COM
DEC
INC
LSR
NEG
ROL
ROR
TST
6
1
2
3
4
5
6
1
1
1
1
0
1/0
(Note
2)
Nota.
1. If device which is addressed during this cycle: uses VMA, then the data bus will go to the high impedance 3-state condition. Depending on bus
capacitance, data from the previous cycle may be retained on the data bus.
2. For TST, VMA = "0" and operand data does not change.
5-40
F6800/F68AOO/F68BOO
The branch instructions allow the programmer to efficiently
direct the MPU to one point or another in the control program
depending on the outcome of test results. Since the control
program is normally in read-only memory and cannot be
chang!!d, the relative address used in execution of branch
instructions is a constant numerical value. Cycle-by-cycle
operation is shown in Table 12 for relative addressing.
The operand field can also contain a numerical value that will
be automatically added to X during execution. This format is
illustrated in Figure 26.
When the MPU encounters the LOAB (Indexed) opcode in
location 5006, it looks in the next memory location for the
value to be added to X (5 in the example) and calculates the
required address by adding 5 to the present index register'
value of 400. In the operand format, the offset may be
represented by a label or a numerical value in the range 0255 as in the example. In the earlier example, STAA X, the
operand is equivalent to 0, X, that is, the 0 may be omitted
when the desired address is equal to X. Table 13 shows the
cycle-by-cycle operation for the indexed mode of addressing.
Indexed Addressing Mode
With indexed addressing, the n\lmerical address is variable
and depends on the current contents of the index register. A
source statement such as
Operator
STAA
Comment
Put A in Indexed
Location
Operand
X
Fig. 26
Indexed Addressing Mode
causes the MPU to store the contents of accumulator A in
the memory location specified by the contents of the index
register (recall that the label "X" is reserved to designate
the index register). Since there are instructions for
manipulating X during program execution (LOX, INX, OEX,
etc.), the indexed addressing mode provides a dynamic onthe-fly way to modify program activity.
MPU
MPU
ADDA=INDX
OFFSET ....
Fig. 25
...;;=:....-1\
Relative Addressing Mode
= __-11
PC
PC = 5006 ....__
OFFSET $ 255
GENERAL FLOW
PC
(PC
(PC
+ 2)
I-~~_I\
+ 2) .....
~=~~~
______..
+ (OFFSET)
PC
5008 ....__~_-I,
pc
5010 ~=..;;,;;;.;,,;,;...
PC
5025 ....
.....______..
= ____"'"
5-41
-;;;;..---1\
ADDA = 405 ....
EXAMPLE
F6800/F68AOO/F88BOO
Table 12
Relative Mode Cycle·by·Cycle Operation
Addres$ Mode
and Instructions
Address Bus
Deita BU8
Rel8tive
BCC
BCS
BEQ
BGE
BGT
BNE
BPL
BRA
BVC
BVS
BHI
BLE
BLS
BLT
BMI
4
1
2
3
4
1
2
BSR
8
3
4
5
6
7
8
1
1
0
0
Op Code Address
Op Code Address
Op Code Address
Branch Address
1
1
0
1
1
0
0
0
Op'Code Address
Op Code Address + 1
Return Address of Main Program
Stack Pointer
Stack Pointer - 1
Stack Pointer - 2
Return Address of Main Program
Subroutine Address
+1
+2
1
1
1
1
Op Code
Branch Offset
Irrelevant Data (Note)
Irrelevant Data (Note)
1
1
1
0
0
1
1
1
Op COde
Branch Offset
Irrelevant Data (Note)
Return Address (Low Order Byte)
Return Address (High Order Byte)
Irrelevant Data (Note)
Irrelevant Data (Note)
Irrelevant Data (Note)
Note
I! device which is addressed during this cycle uses VMA, then the data bus will go to the high impedance 3-state condition. Depending on bus
capacitance, data from the previous cycle may be retained on the data bus.
'
Table ~3
Indexed Mode Cycle.by.Cycle Operation
Address Mode
and Instructions
VMA
Addres8 Bus
Data BU8
Indexed
JMP
1
2
4
ADC
ADD
AND
BIT
CMP
EOR
LOA
ORA
SBC
SUB
1
1
0
0
Op Code Address
Op Code Address + 1
Index Register
Index Register Plus Offset
(w/o Carry)
1
1
1
1
Op Code
Offset
Irrelevant Data (Note 1)
Irrelevant Data (Note 1)
3
4
1
1
0
0
1
1
1
1
Op Code
Offset
Irrelevant Data (Note 1)
Irrelevant Data (Note 1)
5
1
Op COde Address
Op Code Address + 1
Index Register
Index Register Plus Offset
(w/o Carry)
Index Register Plus Offset
1
Operand Data
1
2
3
4
1
1
0
0
1
1
1
1
Op Code
Offset
Irrelevant Data (Note 1)
Irrelevant Data (Note 1)
5
6
1
1
Op Code Address
Op Code Address + 1
Index Register
Index Register Plus Offset
(w/O Carry)
Index Register Plus Offset
Index Register Plus Offset
1
1
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
1
2
3
4
1
1
0
0
1
1
1
1
Op Code
Offset
Irrelevant Data (Note 1)
Irrelevant Data (Note 1)
5
6
0
1
1
0
Irrelevant Data (Note 1)
Operand Data
3
4
1
2
5
CPX
LOS
LOX
6
STA
6
Op Code Address
Op Code Address + 1
Index Register
Index Register Plus Offset
(w/o Carry)
Index Register Plus Offset
Index Register Plus Offset
5·42
+1
F6800/F68AOO/F68BOO
Table 13
Indexed Mode Cycle·by·Cycle Operation (Cont.)
Address Mode
and Instructions
Address Bus
Data Bus
Indexed (Cont.)
ASL
ASR
CLR
COM
DEC
INC
LSR
NEG
ROL
ROR
TST
7
STS
STX
7
JSR
8
1
2
3
4
1
1
0
0
5
6
7
1
0
110
(Note
2)
1
2
3
4
1
1
0
0
5
6
7
0
1
1
1
2
3
4
5
6
7
8
1
1
0
1
1
0
0
0
Op Code Address
Op Code Address +1
Index Register
Index Register Plus Offset
(w/o Carry)
Index Register Plus Offset
Index Register Plus Offset
Index Register Plus Offset
Op Code Address
Op Code Address +1
Index Register
Index Register Plus Offset
(w/oCarry)
Index Register Plus Offset
Index Register Plus Offset
Index Register Plus Offset + 1
Op Code Address
Op Code Address + 1
Index Register
Stack Pointer
Stack Pointer - 1
Stack Pointer - 2
Index Register
Index Register Plus Offset
(w/o Carry)
1
1
1
1
Op Code
Offset
Irrelevant Data (Note 1)
Irrelevant Data (Note 1)
1
1
0
Current Operand Data
Irrelevant Data (Note 1)
New Operand Data (Note 2)
1
1
1
1
Op Code
Offset
Irrelevant Data (Note 1)
Irrelevant Data (Note 1)
1
0
0
Irrelevant Data (Note 1)
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
1
1
1
0
0
1
1
1
Op Code
Offset
Irrelevant Data (Note 1)
Return Address (Low Order Byte)
Return Address (High Order Byte)
Irrelevant Data (Note 1)
Irrelevant Data (Note 1)
Irrelevant Data (Note 1)
Note
1. If device which is addressed during this cycle uses VMA, then the data bus will go to the high impedance 3-8tate condition. Depending on bus
capacitance, data from the previous cycle may be retained on the data bus.
2. For TST, VMA
= "0"
and operand data does not change.
5-43
,.
F6800/F68AOO/F68BOO
Absolute Maximum Ratings
Supply Voltage
Input Voltage
Operating Temperature Range-TL to TH
F6800, F66AOO,F66BOO
F6600C, F68AOOC, F68BOOC
F6800DM, F66AOODM, F68BOODM
Storage Temperature Range
Thermal Resistance
Plastic Package
Ceramic Package
DC Characteristics
Symbol
Vcc
= 5.0. V
COC,+7COC
-4C o C, +85°C
-55°C, +125°C
-55°C, +15C o C
± 5%, Vss
= 0., TA = h
Characteristic
VIH
VIHC
Input HIGH Voltage
VIL
VILC
Input LOW Voltage
liN
Input Leakage CLirrent
This device contains circuit,ry to protect the inputs against damage due:to
high static voltages or electric fields; however. it is advised that normal
precautions be taken to avoid ·application 01 any voltage higher than
maximum rated veiltages: to this high-impedance circuit.
-0..3 V. +7.0. V
-0..3 V, +7.0. V
Min
Logic
.p1, .p2
Logic
.p1, .p2
to TH, unless otherwise noted
Typ
.Max
Unit
Vss + 2.0.
Vcc - 0..6
Vcc"
Vcc + 0..3
V
Vss - 0..3
Vss - 0..3
Vss+ 0..8
Vss + 0..4
V
1.0.
2.5
10.0.
p.A
2.0.
10.
10.0.
p.A
Logic'
.p1, .p2
ITSI
3-State (OFF State)
00- 0 7
Input Current
Ao-A IS , R/IN
VOH
Output HIGH Voltage
00- 0 7
Ao-A IS , R/IN, VMA
BA
VOL
Output LOW Voltage
Po
Power Dissipation
CIN
Input Capacitance
.p1
.p2
0 0-0 7
Logic Inputs
COUT
V
Vss + 2.4
Vss + 2.4
Vss + 2.4
Vss + 0.:4
V
0..5
1.0.
W
25
45
10.
6.5
35
70.
12.5
10.
pF
12
pF
Output Capacitance
Ao-A IS , R/IN, VMA
5-44
Conditions
= 0. to 5.25 V, Vcc = Max
= 0. to 5.25 V, Vcc = 0..0. V
VIN = 0..4 to 2.4 V, Vcc = Max
VIN
VIN
= -20.5 p.A, Vcc = Min
= -145 p.A, Vcc = Min
= -10.0. p.A, Vcc = Min
ILoad = 1.6 mA, Vcc = Min
ILoad
ILoad
ILoad
VIN
= 0., TA = 2.5°C, f = 1.0. MHz
F6800/F68AOO/F68BOO
Clock Timing
Symbol
Vcc
= 5.0 V
± 5%. Vss
= O. TA = h
to TH• unless otherwise noted
Min
Characteristic
Typ
Max
Unit
Conditions
Frequency of Operation
f
F6800
F68AOO
F68BOO
0.1
0.1
0.1
1.0
1.5
2.0
MHz
F6800
F68AOO
F68BOO
1.000
0.666
0.500
10
10
10
j.LS
1>1.1>2 - F6800
1>1.1>2 - F68AOO
1>1.1>2 - F68BOO
400
230
180
9500
9500
9500
ns
F6800
F68AOO
F68BOO
900
600
440
teye
Cycle Time (Figure 27)
PW.pH
Clock Pulse Width
tut
Total 1>1 and 1>2
Up Time
t.pr.t.pf
Rise and Fall Times
td
Delay Time or Clock
Separation (Figure 27)
Read/Write Timing
tAD
•
ns
0
0
100
ns
Measured Between
Vss + 0.4 V and Vcc - 0.6 V
9100
9100
ns
Vov
Vov
= Vss + 0.6 V @ tr = tf S
= Vss + 1.0 V @ tr = tf S
100 ns
35 ns
(Reference Figures 28 through 32)
F6800
Symbol
Vcc - 0.6 V
CharacteristiC
Min
Typ
F68AOO
Max
Min
Typ
F68BOO
Max
Min
Typ
Max
Address Delay
Unit
ns
C
C
= 90 pF
= 30 pF
270
250
180
165
150
135
530
360
250
taee
Peripheral Read Access Time
taee = tut - (tAD + tOSA)
tOSA
Data Set-up Time (Read)
100
60
40
tH
Input Data Hold Time
10
10
10
tH
Output Data Hold Time
10
25
10
25
10
25
ns
tAH
Address Hold Time
(Address. R/Iii. VMA)
30
50
30
50
30
50
ns
tEH
Enable HIGH Time for DBE Input
toow
Data Delay Time (Write)
tpcs
tPCr. tpCf
tBA
tTSE
tTSO
tOBE
tOBEr. tOBEf
Processor Controls
Processor Control Set-up Time
Processor Control Rise and
Fall Time
Bus Available Delay
3-State Enable
3-State Delay
Data Bus Enable Down Time
During 1>1 Up Time
Data Bus Enable Rise and
Fall Times
450
280
225
140
200
150
5-45
ns
110
120
25
ns
160
100
165
40
270
100
250
40
270
ns
220
200
ns
ns
100
135
40
220
75
25
ns
ns
ns
ns
ns
ns
25
ns
F6800/F68AOO/F68BOO
Fig. 27
Clock Timing Waveform
I----------I,y,----------I
I.f
Fig. 28
Read Data From Memory or Peripherals
\~------"lV-O.SV
R/W
ADDRESS
FROM MPU
VMA
DATA
FROM MEMORY
OR PERIPHERALS
~
0.8 V
DATA NOT VALID
5-46
----"",..====""""-
F6800/F68AOO/F68BOO
Fig. 29
Write In Memory or Peripherals
•
R/W
ADDRESS
FROM MPU
VMA
tH
tDBEr
2.4 V---::.,+ofl!!!""-------.,
~~~~UD"-------------------------.,r---..~~~
0.4 V
~
DATA VALID
--"',..---------f
DATA NOT VALID
5·47
F6800/F68AOO/F68BOO
Fig. 30
Typical Data Bus Output Delay
vs Capacitive Loading (tDDW)
Fig. 31
500
500
IOH = -206 ,..A MAX @l2.4V
-10l =.1.8mAMAX@0.4V
_'Icc = 5.0 V
400
TA = 25"<:
16.. =
-leL = 1.8mAIII!AX@0.4V
Vcc = 5.0V
400 -TA = 25"<:
~
..
.
:l..
Typical ReAD/WRITE, VMA,and Address
Output Delay VB Capacitive Loading (tAD)
~
I 300
I 300
;--'
--'
..
..
",
200
--'
1:1
100
200
400
300
'CL - LOAD CAPACITANCE
Bus Timing
Tes~
~
",
--'
~
"...
--' f'ADDRESS
R/W-I--
....... --'
CL INCLUDES STRAY CAPACITANCE
CL INCLUDES'STRAY CAPACITANCE
100
VMj-
...... 1-"""
lE
;:
...c
"....
L
200
1:1
100
..
i--""
lE
;:
Fig. 32
145~M~x@~AV
.100
500
pF
200
300
400
500
CL - LOAD·CAPACITANCE - pF
loads
Test Conditions
Vee
The dynamic test load for the d4ta bus is 130 pF and One
standard TTL load, as shown. The Address, R/W, and VMA
outputs are tested under two conditions to allow optimum
operalion in both' buffered and unbuffered systems. The resistor
(R) is chosen to insure specified load currents during
VOH measurement.
RL=2.2k
TEST POINT - . -......--1(\--..
Notice that the data bus lines, the address lines, the interrupt
'request line, and the DBE line are all specified and tested to
guarantee 0.4 V of dynamic nOise immunity at both" 1" and "0"
logic levels.
IN914
OR EQUIV
C
=
130 pF,Ior 0 0 -07 , E
= 90 pF for Ao-A,., R/W, and VMA
(except t AD2)
=
30 pF for Ao7A,., R/W, .• nd VMA
(t A02 only)
= 30 pF for BA.
R = 11.7 kll for 0 0 -0 7
= 16.5 kll for Ao-A,., R/W, and VMA
= 24 kll for BA
'
"548
F6800/F68AOO/F68BOO
Ordering Information
Speed
Order Code
1.0 MHz
F6800P,S
1.5 MHz
2.0 MHz
Temperature Range
o to +70°C
F6800CP,CS
-40 to +85°C
F6800DM
-55 to +125°C
F68AOOP,S
o to +70°C
F68AOOC,CS
-40 to +85°C
F86AOODM
-55 to +125°C
F68BOOP,S
o to +70°C
F68BOOC,CS
-40 to +85°C
F68BOODM
-55 to +125°C
II
·P=plastlc package, S=CER-DIP package.
5-49
F6800/F68AOO/F68BOO
5·50
F6801/F6803
Single-Chip Microcomputer
Advance Product Information
Microprocessor Product
Description
Connection Diagram
The Fairchild F6801/F6803 is an 8-bit single-chip microcomputer unit (MCU) which significantly enhances the
capabilities of the F6800 family. It includes an upgraded
F6800 microprocessor unit (MPU) with upward-source and
object-code compatibility. The F6801/F6803 MCU can function as a monolithic microcomputer or can be expanded to
a 64K byte address space. Features of the F6801/F6803
MCU include:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Vss
Enhanced F6800 Instruction Set (see table 1)
8 x 8 Multiply Instruction
Serial Communications Interface (SCI)
16-bit Three-Function Programmable Timer
Bus Compatibility with the F6800 Family
2048 Bytes of ROM (F6801 Only)
128 Bytes of RAM
64 Bytes of RAM, Retainable During Powerdown
29 Parallel I/O and Two Handshake Control Lines
Internal Clock Generator With Divide-by-Four Output
Interrupt Capability
TTL compatible
40-Pin Ceramic or Plastic Package
+ SV Power Supply
The F6801/F6803 MCU can be configured to function in a
wide variety of applications. This flexibility is provided by
its ability to be hardware-programmed into eight different
operating modes (see table 2). The operating mode controls
the configuration of 18 of the 40 MCU pins, available onchip resources, memory map, location of interrupt vectors,
and type of external bus. Configuration of the remaining 22
pins is not dependent on the operating mode.
XTAL1
SC ,
EXTAL2
sc,
NM
PJO
fROi
P"
RESET
P"
Vee
P 33
P,o
P 34
P"
P 35
P"
P"
P"
P 37
P'4
P 40
P '0
P 4l
P ll
P 4,
P12
P 43
P 13
P44
P '4
P 45
P 15
P4•
P,.
P 47
PH
Vee
STANDBY
The F6803 can be considered an F6801 that operates in
Modes 2 and 3 only (either internal RAM with no ROM, or
no internal RAM or ROM, respectively).
5-51
•
F6801/F6803
Figure 1 Block Diagram
MODE
IF
I
IW~·M~.",'~~
EXPANDED NON-MULTIPLEXED
p.,
Poe
P36
p..
P33
p..
Po,
P30
SC.
SC,
A,/D,
110/0,
0,
110
D.
As/D.
A"D.
Ao/Do
Os
110
110
110_
110
110
110
~/Da
A,ID,
Ao/~
R/W
AS
Do
Do
D.
D,
~
R/W
IDS
SINGLE CHIP
Pzo
P2,
PORT
2
PORT
3
p..
P23
p..
110
OS.
iSs
TIMER
SCI
p..
P46
p..
p..
po.
p..
Po,
p..
A,.
A,.
A,.
A,.
A"
A,.
110
110
A,
110
110 110
110 110
As 110
A.
A.
A,
110
Ao
110
PORT
1
110
110
5-52
p,.
P"
p,.
p,.
P,o
p,.
p,.
P17
F6801/F6803
Figure 2 Programming Model
I___ ~ __ ~U~_. _~ __ ~18'BITACCUMULATORSAANDB
15
D O O R 16·BIT DOUBLE ACCUMULATOR D
01
115
X
115
SP
01 STACK POINTER (SP)
115
PC
01 PROGRAM COUNTER (PC)
INDEX REGISTER (X)
•
L-_ _ _ _ _ _ _ HALF CARRY (From Bit 3)
5·53
F6801/F6803
Table 1 New Instructions
Instructio
ABX
ADDD
ASLD or
LSLD
BHS
BLO
BRN
JSR
LDD
LSL
LSRD
MUL
PSHX
PULX
STD
SUBD
CPX
Description
Unsigned addition of Accumulator B to Index Register
Adds (without carry) the double accumulator to memory and leaves the sum in the double accumulator
Shifts the double accumulator left (towards MSB) one bit, the LSB is cleared and the MSB Is shifted into the C-bit
Branch if Higher or Same, unsigned conditional branch (same as BCC)
Branch if Lower. Unsigned conditional branch (same as BCS)
Branch Never
Additional addressing mode direct
Loads double accumulator from memory
Shifts memory or accumulator left(towards MSB) one bit, the LSB is cleared and the MSB la shifted into the C·blt
(same as ASL)
Shifts the double accumulator right (towards LiSB) one bit, the MSB is cleared and the LSB is shifted into the C-bit
Unsigned multiply, multiplies the two accumulators and leaves the product in the double accumulator
Pushes the Index Register to stack
Pulls the Index Register from stack
Stores the double accumulator to memory
Subtracts memory from the double accumulator and leaves the difference in the double accumulator
Internal processing modified to permit Its use with any conditional branch instruction
5·54
F6801/F6803
Table 2 Summary of F680lIF6803 Operating Modes
Common to all Modes:
Reserved Register Area
Port 1
Port 2
Programmable Timer
Serial Communications Interface
Single Chip Mode 7
128 bytes 0 RAMk, 2048 bytes of ROM
Port 3 is a parallel I/O port with two control lines
Port 4 is a parallel I/O port
SC1 is Input Strobe 3 (IS3)
SC2 is Output Strobe 3 (OS3)
Expanded Non-Multiplexed Mode 5
128 bytes of RAM, 2048 bytes of ROM
256 bytes of external memory space
Port 3 is an 8-bit data bus
Port 4 is an input port/address bus
SC1 is Input/Output Select (lOS)
SC2 is Read/Write (RIW)
Expanded Multiplexed Modes 1, 2, 3 6
Sour memory space options (64K address space)
(1) No internal RAM or ROM (Mode 3)
(2) Internal RAM, no ROM (Mode 2)
(3) Internal RAM and ROM (Mode 1)
(4) Internal RAM, ROM with partial address bus (Mode 6)
Port 3 is a multiplexed address/data bus
Port 4 is an address bus (inputs/address in Mode 6)
SC1 is Address Strobe (AS)
SC2 is Read/Write (RIW)
Test Modes 0 and 4
Expanded Multiplexed Test Mode 0
May be used to test RAM and ROM
Single Chip and Non-Multiplexed Test Mode 4
(1) May be changed to Mode 5 without going through
reset
(2) May be used to test Ports 3 and 4 as I/O ports
5-55
II
F6801/F6803
Table 3 . Instruction Execution Times in E·Cycles
Addressing Mode
.!
'"0
'"0
'"0
.S!
CII
e
.5
ABA
ABX
ADC
ADD
ADDD
AND
ASL
ASLD
ASR
BCC
BCS
BEQ
BGE
BGT
BHI
BHS
BIT
BLE
BLO
BLS
BLT
BMI
BNE
BPL
BRA
BRN
BSR
BVC
BVS
CBA
CLC
CLI
CLR
CLV
CMP
COM
CPX
DAA
DEC
DES
DEX
EOR
INC
INS
CII
U
!!
c
11
1.1
0
w
~
.E
•
•2
•
••
4
••4
2
4
3
5
3
4
6
4
6
4
6
4
6
•6
•6
2
•
••
•
•••
•
•
•2
•
••
•
•
•
•
••
••
•
•
••
••
2
•4
••
••
2
••
•3
•
•
•
••
•
••
••
3
•
•
••
••
•
••
••
••
••
•
•3
•5
••
•
•3
•
•
•
•
•
••
••
4
•
••
•
•
•
•••
•
•
••
••
6
•4
6
6
•6
••
4
6
•
'"0
•
Addressing Mode
c!!
"ii
••
••
••
.E
2
3
•
•2
3
2
•
•
•
••4
•
••
•
•
•
•
•
•
••
•
•
•
•• ••
•••
•
•
••
••
6
•4
6
6
•6
•
•4
6
•
•••
•
•
•2
2
2
2
2
•
2
•2
2
3
3
•
•3
CII
e
1ii
.!
•
•
•
.!
:6
.~
a:
INX
JMP
JSR
LOA
LDD
LOS
LOX
LSL
LSLD
LSR
LSRD
MUL
NEG
NOP
ORA
PSH
PSHX
PUL
PULX
ROL
ROR
RTI
RTS
SBA
•
••
••
3
3
3
3
3
3
3
•3
3
3
3
3
3
3
3
3
6
3
sec
SEC
SEI
SEV
STA
STD
STS
STX
SUB
SUBD
SI
TAB
TAP
TBA
TPA
TST
TSX
TXS
WAI
3
•
••
•
••
•
•
•
•
••
•
••
5·56
11
~
'"0
C
~
11
)(
CII
'"0
c!!
CII
.&:
.5
0
w
.E
.E
••
••
5
•3
•3
3
6
4
5
5
5
6
4
5
5
5
•2
3
3
3
••
•••
••
2
•
•
•
••
•
•
•
•2
••
•
••
•
•2
4
•
••
••
••
••
3
4
4
4
••
•
••
•
•
3
•
6
•6
•
•6
•
4
•
6
•6
•
•
•
••
•
•
2
3
2
3
10
2
2
•
•
••
•
•
•
•3
•
•
•
••
•6
•
4
••
•
6
6
•
•
••
•4
10
5
2
•
2
3
4
4
4
3
5
4
5
5
5
4
6
•
••
•
•
••
•
•
•6
•4
•
•
•
•
••
•
•6
•
••
•6
•
•
4
5
5
5
4
6
•
••
•
•6
•
••
•3
4
4
5
2
2
•2
2
•
•
•
•
•
•
12
2
2
2
2
2
3
3
9
CII
.~
SIII
a:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
••
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
••
••
•
•
•
F6802lF68821F6808
Microprocessor with Clock
and RAM
Microprocessor Product
Description
Connection Diagram
The F6802/F6882 is a monolithic 8-bit microprocessor
that contains all the registers and accumulators of the
F6800, plus an internal clock oscillator and driver on the
same chip. The F6802/F6882 also has 128 bytes of RAM
on board, located at hex addresses $0000 to $007F, Vce
standby can be utilized on the F6802/F6882 to facilitate
memory retention during a power-down situation; the
first 8 bytes of RAM at hex addresses $0000 to $0007 can
be retained on the F6882, and the first 32 bytes of RAM
at hex addresses $0000 to $001 F can be retained on the
F6802. The F6808 is identical to the F6802 without onboard RAM.
40-Pln DIP
vss
REseT
HALT
EXTAL
MR
XTAL
IRQ
E
RE
Vee
STANDBY
VMA
NMI
Rm
BA
Vee
Do
0,
As
0,
0,
The F6802/F6882 is completely software-compatible with
the F6800 microprocessor and the entire F6800 family of
parts. (Figure 1 illustrates a typical application using an
F6800 family device.)
II
D.
Os
D.
0,
•
•
•
•
•
•
•
•
•
•
On-Chip Clock Circuit
128 x 8-blt On-Chip RAM (Not Included on F6808)
8 Bytes of RAM are Retalnable on the F6882
32 Bytes of RAM are Retainable on the F6802
Software-Compatible with the F6800
Standard TTL-Compatible Inputs and Outputs
8-blt Bidirectional Data Bus
16-blt Memory Addressing
Interrupt Capability
Three Speed Grades:
1.0 MHz F6802/F68821F6808
1.5 MHz F68A02/F68A821F68A08
2.0 MHz F68B02/F68B82/F68B08
A7
A15
As
A14
A9
A13
A10
Au
A11
Vss
F6802/F6882/F6808 Signal Functions
RAM
CONTROL
INPUTS
RE
Ao
A,
A,
A,
CLOCK
CONTROL
1
EXTAL
A.
XTAL
As
MR
A,
A,
As
RESET
CPU
CONTROL
INPUTS
j
'" I
CONTROL
OUTPUTS
-"1
5-57
ADDRESS
BUS
A,
NMI
AlO
iRQ
A"
HALT
A12
A13
A,.
BA
A15
VMA
R/iN
Do
0,
0,
Vee
0,
Vee
STBY
Vss
D.
Os
0,
0,
DATA
BUS
F6802/F6882/F6808
Fig. 1
Typical Microcomputer Block Diagram
Vee
COUNTER
TIMER 1/0
RESET
{
=
Vee
Vee
Vee
Vee
"'' 'J
RESET
F6846
ROM, 1/0, TIMER
IRQ
RES
MR
CSo
VMA
HALT
VMA
CLOCK
2K BYTES ROM
10110 LINES
3 LINES TIMER
00·0,
R/W
R/W
W
-I
RE 4--"="
F68021
NMI
F6882
BA
-
00·0,
XTAL
D
EXTAL
Registers
A general block diagram of the F6802/F6882 is shown in
Figure 2. The number and configuration of the registers
are identical to the F6800, as shown, with a 128 x 8·bit
RAM- added to the basic microprocessor. The first 8
bytes in the F6882 and the first 32 bytes in the F6802
may be operated in a low·power mode via a Vee standby
and can be retained during power·up and power·down
conditions via the RE signal. The F6808 is identical to
the F6802 except for on· board RAM. Since the F6808
does not have on·board RAM, pin 36 must be tied to
ground, allowing the processor to utilize up to 64K bytes
of external memory.
Program Counter
The program counter is a 2·byte (16·bit) register that
points to the current program address.
Stack Pointer
The stack pOinter is a 2·byte register that contains the
address of the next available location in an external
push·down/pop·up stack. This stack is normally a random
access read/write memory that may have any location
(address) that is convenient. In those applications that
require storage of information in the stack when power is
lost, the stack must be non·volatile.
The microprocessing unit (MPU) has three 16·bit registers
and three 8·bit registers available for use by the
programmer, as shown in Figure 3.
Index Register
The index register is a 2·byte register that is used to
store data or a 16·bit memory address for the indexed
mode of memory addressing.
'If programs are not executed from on·board RAM, TAV1 applies. If programs are to be stored and executed from on·board RAM, TAV2 applies.
For normal data storage in the on·board RAM, this extended delay does
not apply. Programs ean be exeeuted from on·board RAM when using
1.5 and 2.0 MHz parts. On·board RAM ean be used for data storage with
all parts.
Accumulators
The two 8·bit accumulators are used to hold operands
and results from an arithmetic logic unit (ALU).
5·58
F6802lF68821F6808
Fig. 2
F6802/F6882 Block Diagram
A15A14A13A12A11A1() As
Aa
25 24 23 22 20 19 18 17
MEMORY READY
3
ENABLE
37
RESET
40
NON·MASKABLE INTERRUPT
6
HALT
2
INTERRUPT REQUEST
4
EXTAL
39
XTAL
38
A, A, A5 A, A3 A, A,
Ao
18 15 14 13 12 11 10 9
II
BUS AVAILABLE
VALID MEMORY ADDRESS
READ/WRITE
34
t
26 27 28 29 30 31 32 33
07 06 05 D4 03 02 01 Do
Condition Code Register (Status Word Register)
The condition code register indicates the results of an
arithmetic logic unit operation: negative (N), zero (Z),
overflow (V), carry from bit 7 (C), and half-carry from bit 3
(H). These bits of the condition code register are used as
testable conditions for the conditional branch
instructions. Bit 4 is the interrupt mask bit (I). The
unused bits of the condition code register (bit 6 and bit
7) are binary ones (1).
Figure 4 shows the order of saving the microprocessor
status within the stack.
5·59
F6802lF68821F6808
Fig. 3
Programming Model of the Microprocessing Unit
-I\
L.._ _A_CC_A_ _
F6802lF6882 Signal Descriptions
The control and timing signals for the F68021F6882 are
identical to those of the F6800, with the following
exceptions:
ACCUMULATOR A
°
"'10 "'2 input, and two unused pins have been
...._ _
A_CC_B_ _.,...\ ACCUMULATOR B
i. .
i. .
1. TSC, DBE
eliminated.
5_ _ _ _ _ _
'X_ _ _ _ _--'0\INOEX REGISTER
--'1
PC_ _ _ _ _
5_ _ _ _ _ _
2. The following signal and timing lines have been
added:
RAM Enable (RE)
Crystal Connections EXtal and Xtal
Memory Ready (MR)
Vcc Standby
Enable
Output (E)
PROGRAM COUNTER
1...
'5_ _ _ _ _ _
SP_ _ _ _ _- - " STACK POINTER
"'2
CONDITION CODE
L...L.........'T'-T.I-rI-~
REGISTER
The following summarizes the F6802/F6882 MPU signals.
CARRY -(FROM BIT 7)
Data Bus
OVERFLOW
ZERO
0 0-0 7 (Data Bus Lines),· Pins 26-33
Bidirectional bus used to transfer data to and from the
memory and peripheral devices. Also has 3-state output
buffers capable of driving one standard TTL load and
130 pF.
NEGATIVE
' - - - - - INTERRUPT
' - - - - - - H A L F CARRY (FROM BIT 3)
Fig. 4
Saving the Status of the Microprocessor in
the Stack
Data bus lines are in the output mode when the
internal RAM is accessed. This prohibits external data
from entering the MPU. The internal RAM is fully
decoded from addresses $0000 to $007F. External RAM
at $0000 to $007F must be disabled when internal RAM
is accessed.
m-9
m - 8
_ _ SP
m - 7
m
m
m
m
-
6
5
4
3
m - 2
m - 2
m -,
m
_ _ SP
+1
m +2
--~T
m
m -,
m
m
m
CC
ACCB
ACCA
IXH
IXl
PCH
PCl
Address Bus
Ao-A15 (Address Bus Lines), Pins 9-20, 22-25
Sixteen output lines form the address bus. The outputs
are capable of driving one standard TTL load and 90 pF.
These lines do not have 3·state capability.
'~"
0
II>
+1
+2
CPU Control Inputs
til
I
BEFORE
RESET (Reset), Pin 40
Input used to reset and start the MPU from a power-down
condition resulting from a power failure or an initial start·
up of the processor. When this line is low,the MPU is
inactive and the information in the registers is lost. If a
high level is detected on the input, this Signals the MPU
to begin the restart sequence. This starts execution of a
routine to initialize the processor from its reset
condition. All the higher order address lines are forced
high. For the restart, the last two locations in memory
AFTER
Notes
SP = Stack Pointer
CC = Condition Code (also called the Processor St"tus Byte)
ACCB = Accumulator B
ACCA = Accumulator A
IXH = Index Register, higher order 8 bits
IXl= Index Register, lower order 8 bits
PCH = Program Counter, higher order 8 bits
PCl = Program Counter, lower order 8 bits
5-60
F6802lF68821F6808
($FFFE, $FFFF) are used to load the program that is
addressed by the program counter. During the restart
routine, the interrupt mask bit is set and must be reset
before the MPU can be interrupted by iRQ. Power·up and
reset timing sequences are shown in Figures 5 and 6.
Fig. 6
Power·Down Sequence
Vee
When brought low, RESET must be held low at least
three clock cycles. This is Independent of the power·up
delay required for oscillator start·up (T Rd.
E
When RESET is released, it must go through the low-tohigh threshold without bouncing, oscillating, or
otherwise causing an erroneous reset (less than three
clock cycles) that may cause improper MPU operation
until the next valid reset.
V'H
-----------------.
Fig. 5
RE
Power-Up and Rese. Timing
~------------------------~.~,--------------------------------
Vee
E-+-------<~
V'H
V~'L~
-~
_ _ _
------'JII_-
REsa ____-4______
__--------1:-,_____
V'L
RESET - - - - - - - - - - -
~
t
--------OPTION 1
(SEE NOTE BELOW)
~-
OPTION 2
SEE· FIGURE 4 FOR
POWER DOWN CONDITION
V'ft
RE _______________~V~'L
--.
-~--:lI.r-'--t
-:.'--,
·....--tPcA
Nota
I! option 1 is chosen. RESET and RE pins ean be tied together.
5-61
- ._ _
Pe
~
F6802lF68821F6808
Fig. 7
NMI (Non.Maskable Interrupt), Pin 6
A low-going edge on this input requests that a non·
maskable interrupt sequence be generated within the
processor. As with the interrupt request (IRQ) signal, the
processor completes the current instruction being
executed before it recognizes the NMI signal. The
interrupt mask bit in the condition code register has no
effect on NMI.
MPU Flow Chart
The index register, program counter, accumulators, and
condition code register are stored on the stack, as
shown in Figure 4. At the end of the cycle, a 16·bit
address will be loaded from memory locations $FFFC
and $FFFD that points to a vectoring address. An
address loaded from these locations causes the MPU to
branch to a non·maskable interrupt routine in memory.
A nominal 3 kO external resistor to Vee should be used
for wire-OR and optimum control of interrupts. The NMI
signal may be tied directly to Vee if not used.
The IRQ and NMI inputs are hardware interrupt lines
that are sampled when E is high and start the interrupt
routine on a low E following the completion of
an instruction.
Figure 7 is a flow chart describing the major decision
paths and interrupt vectors of the microprocessor. Table
1 gives the memory map for interrupt vectors.
Table 1
Memory Map for Interrupt Vectors
Vector
MS
LS
$FFFE
$FFFF
$FFFC
$FFFD
Non·Maskable Interrupt
$FFFA
$FFFB
Software Interru pt
$FFF8
$FFF9
Interrupt Request
Description
Restart
so that no further interrupts may occur. At the end of the
cycle, a 16-bit address is loaded from memory locations
$FFF8 and $FFF9 that point to a vectoring address. An
address loaded from these locations causes the MPU to
branch to an interrupt routine in memory.
IRQ (Interrupt Request), Pin 4
This level·sensitive input requests that an interrupt
sequence be generated within the machine. The
processor waits until it completes the current instruction
that is being executed before it recognizes the request.
At that time, if the interrupt mask bit in the condition
code register is not set, the machine begins an interrupt
sequence. The index register, program counter,
accumulators, and condition code register are stored on
the stack as shown in Figure 4. The MPU responds to the
interrupt request by setting the interrupt mask bit high
The HALT line must be in the high state for interrupts to
be serviced. Interrupts are latched internally while HALT
is low.
The iRa has a high-impedance pull-up device internal
to the chip; however, a 3kO external resistor to Vee
should be used for the wire-un and optimum control
of interrupts.
5-62
F6802/F68821F6808
HALT (Halt), Pin 2
When this input is in the low state, all activity in the
machine is halted. This input is level-sensitive. In the halt
mode, the machine stops at the end of an instruction.
Bus Available is in a high state, and Valid Memory
Address is in a low state. The address bus displays the
address of the next instruction.
R/W (Read, Write), Pin 34
This TTL·compatible output signals the periphals and
memory devices whether the MPU is in a read (high) or
write (low) state. The normal standby state of this signal
is read (high). When the processor is halted, it is in the
read state. This output is capable of driving one standard
TTL load and 90 pF.
To ensure single·instruction operation, transition of the
HALT line must occur t pcs before the falling edge of E
and the HALT line must go high for one clock cycle.
Power
Vcc (Power Supply), Pin 8
Vcc tolerance is ± 5%.
HALT should be tied high if not used.
V cc STBY (Power Supply Standby), Pin 35
This pin supplies the dc voltage to the first 8 or 32 bytes
of RAM as well as the RAM enable (RE) control logic.
Thus, retention of data in this portion of the RAM on a
power-up, power-down, or standby condition is
guaranteed. Maximum current drain at maximum VS B
is ISBB '
RAM Control Port
RE (RAM Enable), Pin 36
A TTL-compatible RAM enable input that controls the onchip RAM. When placed in the high state, the on·chip
memory is enabled to respond to the MPU controls. In
the low state, the RAM is disabled. This pin may also be
utilized to disable reading from and writing to the on-chip
RAM during a power-down situation. The RE signal must
be low three cycles before Vcc goes below 4.75 V during
power-down as shown in Figure 6.
Vss (Ground), Pins 1, 21
System ground; 0 V reference.
Clock Control
The RE signal should be tied low on the F6808; it should
be tied to the correct high or low state if not used.
E (Enable), Pin 37
This pin supplies the clock for the MPU and the rest of
the system. This Is a single-phase, TTL·compatible clock
and may be conditioned by a memory ready (MR) signal.
The E signal Is equivalent to 4>2 on the F6800, and is
capable of driving one TTL load and 130 pF.
CPU Control Outputs
BA (Bus Available), Pin 7
Is normally in the low state; when activated, it goes to
the high state, indicating that the microprocessor has
stopped and that the address bus is available (but not in
a 3·state condition). This occurs if the HALT line is in the
low state or the processor is in the wait state as a result
of execution of a WAIT instruction. At such time, all
3·state output drivers go to their off state and other
outputs to their normally Inactive levels. The processor is
removed from the wait state by the occurrence of a
maskable (mask bit 1 0) or nonmaskable interrupt. This
output is capable of driving one standard TTL load and
30 pF.
EXTAL (External Crystal Connector), Pin 39
XTAL (Crystal Connector), Pin 38
The F6802JF6882 has an internal oscillator that may be
crystal controlled. These connections are for a parallelresonant, AT cut, fundamental crystal. (Figure 8
illustrates the crystal specifications.) A divide-by-four
circuit has been added so that a 4 MHz crystal may be
used in place of a 1 MHz crystal for a more cost-effective
system. An example of the crystal circuit layout on a
printed circuit board is shown in Figure 9.
=
Pin 39 may be driven externally by a TTL-input signal four
times the required clock frequency. Pin 38 is to be
grounded in this mode.
VMA (Valid Memory Address), Pin 5
This output indicates to peripheral devices that there is a
valid address on the address bus. In normal operation,
this signal should be utilized for enabling peripheral
interfaces, such as the PIA and ACIA. This signal is not
3-state. One standard TTL load and 90 pF may be directly
driven by this active-high signal.
An RC .network is not directly usable as a frequency
source on pins 38 and 39. An RC network-type TTL or
CMOS oscillator works well as long as the TTL or CMOS
output drives the on-chip oscillator.
5-63
5
F6802/F6882/F6808
Fig. 8
Crystal Specification
Q
38rD~3~
COUl
T
T
Fig. 9
VI
3.58 MHz
C'N
27pF
CaUl
27pF
4MHz
27 pF
27pF
6MHz
20pF
20pF
8MHz
18 pF
18 pF
CIN
Suggested PC Board Layout
EXAMPLE OF BOARD DESIGN
USING THE CRYSTAL OSCILLATOR
OTHER SIGNALS ARE NOT
WIRED IN THIS AREA.
Crystal Loading
YI
--~IDI-I--
E SIGNAL IS WIRED APART
FROM 38 PIN AND 39 PIN.
39
Co
3.58 MHz
4.0 MHz
6.0 MHz
8.0 MHz
Rs
60n
son
30-50n
20~40n
Co
3.5 pF
6.5 pF
4-6 pF
4-6 pF
0.010.02 pF
>20K
C,
0.015 pF
0.025 pF
0.010.02 pF
Q
>40K
>30K
>20K
'-----------¢~:~----~,;
E
Nominal Crystal Parameters·
*These are representative AT-cut parallel-response crystal parameters only.
Crystals of other types of cuts may also be used.
LC networks in place of the crystal are not recommended.
Flg.10
If an external clock is used, it may be halted'for more
than $PWOL. The F6802/F6882/F6808 is a dynamic part
except for the internal RAM, and requires the external
clock to retain information.
Memory Ready Synchronization
4xfo
OSCILLATOR
EXTAL 39
MR (Memory Ready), Pin 3
A TTL·compatible input control Signal that allows
stretching of the enable (E) signal. Use of MR requires
synchronization with the 4xfo signal, as shown in
Figure 10. When MR is high, E will be in normal
operation. When MR is low, E may be stretched integral
multiples of half periods, allowing interface to slow
memories or peripherals. A maximum stretch is tCYC; The
MR signal should be tied high if not used. Refer to
Figure 11 for MR timing information.
"<.7
F6802
XTAL
MR
5·64
~
A
A
COMB
5321B~B
R
NEG
60
7
2
70 6
3
00 - M
M
~
NEGA
402100-A·A
NEGB
5021
OO-B~B
19 2
Converts 8,nary Add. of BCD Characters
DAA
II
A - B
1
,
CD0
CD0
tCD0
tCD
Into BCD Format
Decrement
D'C
OECA
6A 7
2
7A 6
3
A8 5
2
B8 4
3
E8 5
2
F8 4
3
CD M a CD M
6C 7
2
7C 6
3
M t 1 --> M
OEca
Increment
EORA
88
2
2
98
3
2
EORB
C8 2
2
08 3
2
INC
INCA
INCB
Load Acmltr
Or,lnciusive
Push Data
Pull Data
2
E6 5
2
F6 4
9A32AA5
BA 4
A+M~A
DA 3
FA 4
a+M~ a
2
fA 5
Legend
PSHA
36 4
I
PSHa
37 4
1
--> M Sp , SP - 1 --> SP
a - MSp. SP - 1 --> SP
32 4
1
SP + 1 --+SP. MSp-A
33 4
I
SP+l~SP.Msp~a
49 2
I
59
2
1
~lL{] -
46 2
1
56 2
1
PULA
AOL
69727963
66727663
ROA
68 7
A'L
ASlA
2
78 6
3
7 2
77 6
3
48 2
58 2
67
A'R
ASRA
STAA
47
57
64
7
2
74 6
3
B7 5
3
lSRB
97 4
A7 6
07 4
STAB
E7 6
80229032
A052
804
SUBB
CO 2
EO 5
FO 4
2
00 3
2
1
1
2
I
2 1
44
2
54
2
1
1
2
SBCA
8222923
A252a24
SBCB
C222023
E2 5
2
1
a
--
1 I 1 1 1 1 II
;J
t
bO
b7
1
0 --
1 1 I 1 1 1 1 1 1- 0
C
b7
bO
;1~C?IIIIIIII
b7
:1~B
1
b7
®
0
bO
1
1
1
1
I
-->
a
a ----- A
A
TSTA
402
I
A-OO
R
R
TSTB
50 2
1
a
-00
A
A
z v
C
Note
Accumulator addressing mode instructions are included In the column for implied addressing.
5-67
Operation code (hexadecimal)
Number of MPU cycles
Number of program bytes
Arithmetic plus
Arithmetic minus
Boolean AND
Contents of memory location
point to be stack pOinter
Boolean Inclusive-OR
Boolean exclusive-OR
Complement of M
Transfer into
Bit = zero
Byte = zero
I
®I
M -00
3
o
00
®
®
A-8--A
A
+
M
t®
I®
1
C
0--:1 1 I ! I I I 1 I -
Msp
1
1
t®
I®
-0
bO
®
®
®
®
®
t
8-M-c---a
16 2
70 6
~l
jJ
bO
t
A-M-C---A
F2 4
17 2
2
~lLO
a C
II
b7
®
®
A-M-A
TBA
60 7
"""
C
1
8-M-a
TAB
TST
B
+
t
B-M
3
102
SBA
Sub!r. with Carry
OP
A
A--M
F7 S
SUBA
Subtract Acmltrs
or Minus
® •
B+l~8
SA 2
Logic
Te5t, Zero
®
CA 2
Store Acmll'
Tran$fer Acmltrs
I
A
®.
A
ORAa
L'A
lSRA
Subtract
5C 2
~
A t I
R
A
8
DRAA
ASRB
Shih Right.
1
3
ASlB
Arithmetic
4C 2
M- 8
06 3
B
-->
M~A
2
RORa
Arithmetic
~
8 - 1
A
CG 2
RORA
Shift Right,
I
86229632AG528643
ROlB
StHh left,
1
SA 2
lOAB
ROlA
Rotate Right
4A 2
lDAA
PUla
Rotate left
M - l-M
Condition Code Symbols
H
Half-carry from bit 3
I
Interrupt mask
N
Negative (sign bit)
Z
Zero (byte)
V
Overflow, 2's complement
C
Carry from bit 7
R
Reset always
S
Set always
Test and set If true, cleared
otherwise
Not affected
F6802lF68821F6808
Table 4
Index Register and Stack Manipulation Instructions
COND CODE REG
IMMED
POINTER OPERATIONS
DIRECT
INDEX
EXTND
IMP~IED
MNEMONIC
OP
-
•
OP
-
•
OP
-
•
OP
-
•
CPX
8C
3
3
9C
4
2
AC
6
2
BC
5
3
OP
-
#
5 4 3 2 1 0
BOOLEAN/ARITHMETIC OPERATION
Compare Index Reg
Decrement Index Reg
OEX
1
X-I - X
DES
09
34
4
Decrement Stack Pnlr
4
1
SP - 1 - SP
Increment Index Reg
INX
08
4
1
Increment Stack Pntr
INS
31
4
1
Load Index Reg
3
4
2
EE
FE
4
2
AE
6
6
2
9E
2
BE
5
2
EF
7
2
FF
5
2
AF
7
2
BF
STX
Store Stack Pntr
STS
9F
Indx Reg - Stack Pntr
TXS
TSX
3
3
3
OF
LOX
LOS
Stack Pntr - Indx Reg
CE
8E
DE
Load Stack Pntr
Store Index Reg
5
5
3
3
6
6
3
XH - M. XL - 1M +1.
X+1-X
+ 1 - SP
M - XH. 1M + 1 ' - XL
XH - M. XL - 1M + 1
SPH - M, SPl- 1M
4
1
X-I - SP
30
4
1
SP
I
I
I
SP
35
I N Z V C
·· · · ®.
·· ·· ·· · ··· ···
·· ·• ®· · · ··
··· • ® ···
·· ·· ·· ·· ·· ··
• (f)
M - SPH. ,M+ 1 - SPL
3
H
+ 11
+1- X
• @
I
.@
I
I
R
R
R
I
R
Table 5 Jump and Branch Instructions
CONDo CODE REG.
RELATIVE
OPERATIONS
MNEMONIC OP
Branch Always
Branch II Carry Clear
Branch If Carry Set
Branch If = Zero
Branch If c' Zero
Branch If -- Zero
Branch If Higher
Branch If oS Zero
Branch If Lower Or Same
Branch If < Zero
Branch If Minus
Branch If Not Equal Zero
Branch If Overflow Clear
Branch If Overflow Set
Branch If Plus
Branch To Subroutme
Jump
Jump To Subroutine
No Operation
Return From Interrupt
Return From Subroutine
Software Interrupt
Wait for Interrupt·
·WAI puts address bus,
BRA
BCC
BCS
BEQ
BGE
BGT
BHI
BLE
BLS
BLT
BMI
BNE
BVC
BVS
BPL
BSR
JMP
JSR
NOP
RTI
RTS
SWI
WAI
20
24
25
27
2C
2E
22
2F
23
20
2B
26
28
29
2A
80
#
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
8
INDEX
OP -
#
EXTND
OP
#
IMPLIED
OP
BRANCH TEST
#
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
None
C=O
C= 1
Z=1
N(j)V = 0
Z+IN(t>V,=O
C+Z=O
Z+ IN(t>V, = 1
C+Z=1
N(t>V= 1
N= 1
Z=O
V=O
V=1
N =0
6E 4
AD 8
2 7E 3
2 BO 9
}
3
3
01
3B
39
3F
3E
2
10
5
12
9
1
1
1
1
1
ANi, and data bus in the 3·state mode while VMA is held low.
5-68
5
4
3
2
1
H
I
N
Z
V C
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
•
0
..·
·
· . ··•
· .
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Advances Prog. Cntr. Only
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
See Special Operations
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-@-
}
See SpeCial Operations
· . .I.: . .
0
0
: •1• •
1
•: rODI
@ •
F6802/F68821F6808
Table 6
Condition Code Register Manipulation Instructions
CONDo CODE REG.
IMPLIED
OPERATIONS
Clear Carry
Clear Interrupt Mask
Clear Overflow
Set Carry
Set Interrupt Mask
Set Overflow
Acmltr A - CCR
CCR - Acmltr A
MNEMONIC
OP
CLC
CLI
CLV
SEC
SEI
SEV
TAP
TPA
OC
OE
OA
00
OF
OB
06
07
-
#
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
Condition Code Register Notes (Bit set if test is true and cleared otherwise)
1 (Bit V) Test: Result = 100oo0oo?
2 (Bit C) Test: Result = 00000000?
(Bit C) Test: Decimal value of most significant BCD character
greater than nine? (Not cleared if previously set.)
4 (Bit V) Test: Operand = 10000000 prior to execution?
5 (Bit V) Test: Operand=01111111 prior to execution?
6 (Bit V) Test: Set equal to result of N .. C after shift has occurred.
7 (Bit N) Test: Sign bit of most significant (MS) byte = I?
Table 7
5
4
3
2
1
0
BOOLEAN OPERATION H
I
N
Z
V
C
R
0- C
0-1
0
0
0
0
0
0
R
0
0
0
0
O-V
1-C
1 -I
1- V
A - CCR
CCR - A
0
0
0
0
R
0
0
0
0
0
0
S
0
S
0
0
0
0
0
0
0
0
S
0
--@--01
0
1
0
1
0
\0\0
(Bit V) Test: 2's complement overflow from subtraction of MS
9
10
11
12
bytes?
(Bit N) Test: Result less than zero? (Bit 15= 1)
(All)
Load condition code register from stack (see Figure 10)
(Bit I) Set when interrupt occurs. If previously set, a non·maskable
interrupt is required to exit the wait state.
(All)
Set according to the contents of accumulator A.
Instruction Addressing Modes and Associated Execution Times (Times in Machine Cycles)
(Dual Operand) ACCX
Immediate
(Dual Operand) ACCX
Direct Extended Indexed Implied Relative
ABA
INC
ADC
ADD
INS
INX
AND
JMP
ASL
ASA
JSR
LDA
BCC
LOS
BCS
BEA
BGE
LDX
Immediate
Direct Extended Indexed Implied
LSR
NEG
BGT
NOP
BHI
BIT
ORA
PSH
PUL
BLE
ROL
ROR
BLS
BLT
BMI
RTI
RTS
BNE
BPL
SBA
BAA
BSA
BVC
BVS
SBC
SEC
SEI
CBA
STA,
STS
10
5
2
SEV
CLC
CLI
CLR
CLV
CMP
STX
COM
TAP
cpx
DAA
TBA
TPA
DEC
TST
DES
DEX
EOR
TSX
TSX
SUB
SWI
TAB
WAI
Note
Interrupt time is 12 cycles from the end of the instruction being executed" except foltowing a WAI instruction, when it is four cycles.
5·69
12
2
II
F6802lF68821F6808
FIg,12
Special Operations
JSR. JUMP TO SUBROUTINE:
PC
INDXD
{
SP
Main Program
AD
Stack
nT 1
K- Offset"
n- 2
!\Iext Main In5tr.
Q
SP -1
SP
n
~
EXTND
{
Stack
-
JSR
- SP - 2
nT1
SH
~
Subr. Addr.
n-2
SL
~
Subr. Addr.
nT3
Next Main Instr.
Subroutine
tst Subr. Instr.
2 L
SP
Main -Program
BD
T
INX T K
nT2Hand n ,2,L Form n ,2
. K - 8-Blt Unsigned Value
PC
PC
~
- SP - 2
JSR
~
Q
SP - 1
~
S
n.,. 3 L
SP
-
~
Subroutine
PC
~
1st Subr. Instr.
Formed From SH and SL
Stack POinter After Execution.
BSR. BRANCH TO SUBROUTINE:
SP
Main Program
PC
8D
~
nT1
:: K
nT2
Next Main In5tr.
'K
~
~
Q
Offset'
SP - 1
Subroutine.
PC
Stack
SP - 2
BSR
~
nT2::K
nT2 L
SP
n T 2 Formed From n ,2 Hand n -r2.L
7·Blt Signed Value
JMP. JUMP:
PC
IND)(o
{
6E
nT1
XTK
PC
Main Program
K
~
~
Main Program
~
7E
JMP
Offset
m"D" {
INext Instruction
JMP
nT1
K"
~
Next Address
nT2
KL
~
Next Address
K
.
I
Next InstruellOn
RTS. RETURN FROM SUBROUTINE:
PC
S
SP
Subroutme
139~RTS
I
Q
SP
SP T 1
- SP T 2
Stack
PC
§
Main Program
Next Main Instr.
NL
RTI. RETURN FROM INTERRUPT:
PC
S
SP
Interrupt Program
13B~RTI
0] Q
Stack
PC
n
SP
SP
T
1
CondillOn Code
SP
T
2
Acmltr B
SP
T
3
Acmltr A
SP
T
4
Index Register XH
SP
T
5
Index Register XL
SP
T
6
NH
- SP
T
7
NL
5·70
Main Program
Next Main Instr.
F6802/F6882/F6808
Extended Addressing
in extended addressing, the address contained in the
second byte of the instruction is used as the higher 8
bits of the address of the operand. The third byte of the
instruction is used as the lower 8 bits of the address for
the operand. This is an absolute address in memory.
These are 3·byte instructions.
Output Delay
Figures 13 and 14 illustrate typical output delays versus
capacitance loading.
Fig. 13
Indexed Addressing
In indexed addressing, the address contained in the
second byte of the instruction is added to the index
register's lowest 8 bits in the MPU. The carry is then
added to the higher order 8 bits of the index register.
This result is then used to address memory. The
modified address is held in a temporary address register
so there is no change to the index register. These are
2·byte instructions.
Typical Data Bus Output Delay vs, Capacitive
Loading
600
IOH = -205 pA max @ 2.4 V
IOL = 1.6 mA max @ 0.4 V
Vee = 5.0 V
TA = 25°C
500
iii' 400
S
w
~
300
>
~
~ 200
Implied Addressing
In the implied addressing mode, the instructions give the
address (I.e., stack pointer, index register, etc.). These
are 1·byte instructions.
..,/
.,/
V
....
/
100
CL includes stray capacitance
100
Relative Addressing
In relative addressing, the address contained in the
second byte of the instruction is added to the program
counter's lowest 8 bits plus two. The carry or borrow is
then added to the higher 8 bits. This allows the user to
address data within a range of -125 to + 129 bytes of
the present instruction. These are 2·byte instructions.
200
300
400
500
600
Cl. LOAD CAPACITANCE (pF)
Fig. 14
Typical Read/Write, VMA and Address Output
Delay vs, Capacitive Loading
60 0
Summary of Cycle·by·Cycle Operation
Tab/e 8 provides a detailed description of the information
present on the address bus, data bus, valid memory
address (VMA) line, and the read/write (RlW) line during
each cycle for each instruction.
IOH - -145 Ji.A max @2.4 V
10l = 1.6 rnA max @ 0.4 V
Vee = 5.0 V
TA = 2S"C
500
I
A:::::1MA
400
300
This information is useful in comparing actual with
expected results during debug of both software and
hardware as the control program is executed. The
information is categorized according to addressing mode
and number of cycles per instruction. (In general,
instructions with the same addressing mode and number
of cycles execute in the same manner. Exceptions are
indicated in the table.)
.,/
20 0
V
~
100
.,/
----
Hw
CL includes stray capacitance
0
o
100
200
300
400
500
Cl. LOAD CAPACITANCE (pF)
5·71
600
•
F6802lF68821F6808
Table 8
Operation Summary
Address Bus
Immediate
ADC
ADD
AND
BIT
CMP
EOR
LOA
ORA
SBC
SUB
CPX
LOS
LOX
, ,,
3
EOR
LOA
ORA
SBC
SUB
CPX
LOS
LOX
3
4
STA
4 .
STS
STX
5
Indexed
JMP
4
ADC
ADD
AND
BIT
CMP
CPX
LOS
LOX
EOR
LOA
ORA
SBC
SUB
+f
2
3
Op Code Address
Op Code Address
Op Code Address
+,
+2
2
3
Op Code Address
Op Code Address +
Address of Operand
2
3
4
Op Code Address
Op Code Address + ,
Address of Operand
Operand Address + ,
2
3
4
Op Code Address'
Op Code Address +
Desti nation Add ress
Destination Address
,,
. Data Bu.
Op Code
Operand Data
2
Direct
ADC
APD
AND
BIT
CMP
Op Code Address
Op Code Address
2
R/W
Line
, ,,
,
, ,,
,
, ,,
,,
, ,,
,
, ,,
,,
, ,,
2
3
4
5
0
0
2
3
4
0
0
, ,,
2
5
6
3
4
5
0
0
2
1
0
0
,
, ,
3
4.
5
6
,,
Op Code Address
OP. Code Address +
. Address of Operand
Address of Operand
Address of Operand
,
,
,,
,
.,,
,
,,,
,
,,
,
,,,
0
,
+,
Op Code Address
Op Code Address + ,
Index Register
Index Register Plus Offset (w/o Carry I
Op Code Address
Op Code Address + ,
Index Register
Index Register Plus Offset (w/o Carryl
Index Register Plus Offset
Op Code Address
Op Code Address + ,
Index Register
Index Register Plus Offset I WID Carry)
Index Register Plus Offset
Index Register Plus Offset + ,
5·72
Op Code
Operand Data (High Order Byte)
Operand Data (Low Order. Byte)
Op Code
Address of Operand
Operand Data
,
Op Code
Address of Operand
Operand Data (High Order .Byte)
Operand Data (Low Order Byte)
Op Code
Destination Address
Irrelevant Data INote.',
Data from Accumulator
. Op Code
AQdress of Operand
Irrelevant Data INote "
0 Register Data (High Order Byte)
0 Register Data (Low Order Byte)
,,
,,
,,
,
,,
,,
,,
,
I
Op Code
Offset
Irrelevant Data (Note "
Irrelevant Data I Note. "
Op Code
Offset
Irrelevant Data INote "
Irrelevant Datil INote "
Operand Data
Op Code
Offset
Irrelevant Data INote "
Irrelevant Data INote ,)
OperanQ Data (High Order Byt~)
Operand Data (Low Order Byte)
F6802lF68821F6808
Tabl. 8
Op.... tlon Summary (Cont.)
AIW
Addre•• Mode
Addr... Bu.
and Instruction.
LSR
NEG
ROL
ROR
TST
Da.. Bu.
6
1
2
3
4
5
6
1
1
0
0
0
1
Op Code Address
Op Code Address + 1
Index Register
Index Register Plus Offset (w/o tarry I
Index Register Plus Offset
Index Register Plus Offset
1
1
1
1
1
0
Op Code
Offset
Irrelevant Data (Note 11
Irrelevant Data (Note 11
Irrelevant Data (Note 11
Operand Data
7
1
2
3
4
5
6
7
1
1
0
0
1
0
1/0
(Note
31
Op Code Address
Op Code Address + 1
Index Reg ister
Index Register Plus Offset (w/o Carry I
Index Register Plus Offset
Index Register Plus Offset
Index Register Plus Offset
1
1
1
1
1
1
0
Op Code
Offset
Irrelevant Data (Note 11
Irrelevant Data (Note 11
Current Operand Data
Irrelevant Data (Note 11
New Operand Data INote 31
7
1
2
3
4
5
6
7
1
1
0
0
0
1
1
Op Code Address
Op Code Address + 1
t"ndex Reg ister
Index Register Plus Offset I wlo Carry I
Index Register Plus Offset
Index Register Plus Offset
Index Register Plus Offset + 1
1
1
1
1
1
0
0
Op Code
Offset
Irrelevant Data (Note 11
Irrelevant Data (Note 1'1
Irrelevant Data (Note 11
Operand Data (High Order By1e)
Operand Data (Low Order By1e)
8
1
2
3
4
5
6
7
8
1
1
0
1
1
0
0
0
Op Code Address
Op Code Address + 1
Index Register
Stack Pointer
Stack Pointer - 1
Stack Poi nter - 2
Index Register
Index Register Plus Offset (w/o Carry
1
1
1
0
0
1
1
1
Op Code
Offset
Irrelevant Data (Note 11
Return 'Address (High Order Byte)
Return Address (Low Order By1e)
Irrelevant Data INote 11
Irrelevant Data (Note 11
Irrelevant Data INote 11
3
1
2
3
1
1
1
Op Code Address
Op Code Address + 1
Op Code Address + 2
1
1
1
Op Code
Jump Address (High Order Byte)
Jump Address (LLow Order By1e)
1
2
3
4
1
1
1
1
Op Code Address
Op Code Address + 1
Op Code Address + 2
Address of Operand
1
1
1
1
Op Code
Address of Operand (High Order By1e)
Address of Operand (Low Order By1e)
Operand Data
5
1
2
3
4
5
1
1
1
1
1
Op Code Address
Op Code Address + 1
Op Code Address + 2
Address of Operand
Address of Operand + 1
1
1
1
1
1
Op Code
Address of Operand
Address of Operand
Operand Data (High
Operand Data (High
5
1
2
3
4
5
1
1
1
0
1
Op Code Address
Op Code Address +
Op Code Address +
Operand Destination
Operand Destination
1
1
1
1
0
Op Code
Destination Address (High Order By1e)
Destination Address (Low Order Byte)
Irrelevant Data (Note 11
Data from Accumulator
1
1
1
1
1
0
Op Code
Address of Operand (High Order By1e)
Address of Operand (Low Order By1e)
Current Operand Data
Irrelevant Data (Note 11
New Operand Data (Note 31
STA
ASL
ASR
CLR
COM
DEC
INC
LIne
STS
STX
JSR
Extended
JMP
ADC
ADD
AND
BIT
CMP
EOR
LOA
ORA
SBC
SUB
CPX
LOS
LOX
4
STA A
STA B
ASL
ASR
CLR
COM
DEC
INC
LSR
NEG
ROL
ROR
TST
6
1
2
'3
4
5
6
1
1
1
1
0
1/0
(Note
31
1'
2
Address
Address
Op Code Address
Op Code Add ress + 1
Op Code Add ress + 2
Address of Operand
Address of Operand
Address of Operand
5-73
(High Order By1e)
(Low Order By1e)
Order By1e)
Order By1e)
F6802lF68821F6808
Table 8
Operation Summary (Cont.)
RIW
Address Mode
and Instructions
Address Bus
Line
Data Bus
6
1
2
3
4
5
6
1
1
1
0
1
1
Op Code Address
Op Code Add ress + 1
Op Code Address + 2
Address of Operand
Address of Operand
Address of Operand + 1
9
1
2
3
4
5
6
7
8
9
1
1
1
1
1
1
0
0
1
Op Code Address
Op Code Address + 1
Op Code Address + 2
Subroutine Starting Address
Stack Pointer
Stack Pointer - 1
Stack POinter - 2
Op Code Address + 2
Op Code Address + 2
1
1
1
1
0
0
1
1
1
Op Code
Address of Subroutine (High Order Byte)
Address of Subroutine (Low Order Byte)
Op Code of Next Instruction
Return Address (Low Order Byte)
Return Adc:fress (High Order Byte)
Irrelevant Data 1Note 11
Irrelevant Data INote '11
Address of Subroutine (Low Order Byte)
1
2
1
1
Op Code Address
Op Code Address
1
1
Op Code
Op Code of Next Instruction
4
1
2
3
4
1
1
0
0
Op Code Address
Op Code Address + 1
Previous Register Contents
New Register Contents
1
1
1
1
Op Code
Op Code of Next Instruction
Irrelevant Data I Note 11
Irrelevant Data INote 11
1
2
3
4
1
4
1
0
Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer - 1
1
1
0
1
Op Code
Op Code of Next Instruction
Accumulator Data
Accumulator Data
4
1
2
3
4
1
1
0
1
Op Code Address
Op Code Address
Stack Pointer
Stack Pointer + 1
1
1
1
1
Op Code
Op Code of Next Instruction
Irrelevant Data (Note 11
Operand Data from Stack
2
3
4
1
1
0
0
Op Code Address
Op Code Addiess + 1
Stack Pointer
New I ndex Register
1
,1
1
1
Op Code
Op Code of Next Instruction
Irrelevant Data (Note 11
Irrelevant Data (Note 11
0
Op Code Address
Op Code Address + 1
Index Register
New Stack Pointer
1
1
1
1
Op Code
Op Code of Next Instruction
Irrelevant Data
Irrelevant Data
3
4
1
1
0
1
Op Code Address
Op Code Address
Stack Pointer
Stack Pointer + 1
1
1
1
1
5
1
Stack Pointer
Op Code
Irrelevant Data (Note 21
Irrelevant Data (Note 1}
Address of Next Instruction (High
Order Byte)
Address of Next Instruction (Low
Order Byte)
STS
STX
JSR
1
1
1
'1
0
0
Op Code
Address of Operand (High Order Byte)
Address of Operand (Low Order Byte)
Irrelevant Data I Note 11
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Inherent
ABA
ASL
ASR
CBA
CLC
CLI
CLR
CLV
COM
DAA
DEC
INC
LSR
NEG
NOP
ROL
ROR
SBA
SEC
SEI
SEV
TAB
TAP
TBA
TPA
TST
DES
DEX
INS
INX
2
+1
"
PSH
..
PUL
,
TSX
4
TXS
4
1
2
3
4
1
RTS
2
5
1
,
1
0
+
+
1
1
+2
1
5·74
F6802lF6882/F6808
Table 8
Operation Summary (Cont.)
Address Mode
and Instructions
Address Bus
WAI
9
RTI
10
SWI
12
R/W
LIne
Data Bus
8
9
1
1
1
1
1
1
1
1
1
Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer - 1
Stack Pointer - 2
Stack Pointer - 3
Stack Pointer - 4
Stack Pointer - 5
Stack Pointer - 6 INote 4,
1
1
0
0
0
0
0
0
1
Op Code
Op Code of Next Instruction
Return Address (Low Order Byte)
Return Address (High Order Byte)
Index Register (Low Order Byte)
Index Register (High Order Byte)
Contents of Accumulator A
Contents of Accumulator B
Contents of Condo Code Register
1
2
3
4
1
1
0
1
Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer + 1
1
1
1
1
5
6
7
1
1
1
Stack Pointer + 2
Stack Pointer + 3
Stack Pointer·+ 4
1
1
1
8
1
Stack Pointer + 5
1
Op Code
Irrelevant Data INote 21
Irrelevant Data I Note 11
Contents of Condo Code Register from
Stack
Contents of Accumulator B from Stack
Contents of Accumulator A from Stack
Index Register from Stack (High Order
Byte)
Index Register from Stack ('Low Order
Byte)
Next Instruction Address from Stack
(High Order Byte)
Next Instruction Address from Stack
(Low Order Byte)
1
2
3
4
5
6
7
9
1
Stack Pointer + 6
1
10
1
Stack Pointer + 7
1
1
2
3
4
5
6
7
10
11
1
1
1
1
1
1
1
1
1
0
1
Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer - 1
Stack Pointer - 2
Stack Pointer - 3
Stack Pointer - 4
Stack Pointer - 5
Stack Pointer - 6
Stack Pointer - 7
Vector Address FFFA I Hex I
1
1
0
0
0
0
0
0
0
1
1
12
1
Vector Address FFFB I Hex I
1
Op c'ode
Irrelevant Data I Note 11
Return Address (Low Order Byte)
Return Address (Aigh Order Byte)
Index Register (Low Order Byte)
Index Register (High Order Byte)
Contents of Accumulator A
Contents of Accumulator B
Contents of Condo Code Register
Irrelevant Data INote 11
Address of Subroutine (High Order
Bytel
Address of Subroutine (Low Order Byte)
1
2
1
1
0
0
Op Code Address
Op Code Address + 1
Op Code Address + 2
Branch Address
1
1
1
1
Op Code
Branch Offset
Irrelevant Data I Note 11
Irrelevant Data I Note 11
1
1
0
1
1
0
0
0
Op Code Address
Op Code Address + 1
Return Address of Main Program
Stack Pointer
Stack Pointer - 1
Stack Pointer - 2
Return Address of· Main Program
Subroutine Address
1
1
1
0
0
1
1
1
Op Code
Branch Offset
Irrelevant Data INote 11
Return Address (Low Order Byte)
Return Address (High Order Byte)
Irrelevant Data INote 11
Irrelevant Data INote 11
Irrelevant Data (Note 11
8
9
Relative
BCC
BCS
BEQ
BGE
BGT
BHI
BLE
BLS
BLT
BMI
BNE
BPL
BRA
BVC
BVS
4
3
4
1
2
BSR
I
3
8
4
5
6
7
8
Not,.:
1. If devIce that is addressed during this cycle uses VMA, the data bus goes to the high·impedance 3·state condition. Depending on bus
capacitance, data from the previous cycie may be retained on the data bus.
2. Data is ignored by the MPU.
3. For TST, VMA 0 and operand data does not change.
4. Most significant byte of address bus = most significant byte of address of BSR Instruction, and least Significant byte of address bus = least
significant byte of subroutine address.
=
5·75
•
F6802lF6882/F6808
DC Characteristics
Absolute Maximum Ratings
Table 9 contains the dc characteristics of the
F6802/F6882.
These are stress ratings only, and functional operation at
these ratings, or under any conditions above those
indicated In this data sheet, is not Implied. Exposure to
the absolute maximum rating conditions for extended
periods of time may affect device reliability, and
exposure to stresses greater than those listed may cause
permanent damage to the device.
Voltage of any Pin Relative to GND - 0.3 V, + 7.0 V
Storage Temperature
- 55·C, + 150·C
1.5W
Power Dissipation
Thermal Resistance, IJJA
(Plastic Package)
1W
(CER-DIP Package)
55·CIW
Table 9
DC Characterlstlc$
Symbol
VIH
VIL
liN
VOH
Vee= 5.0 V ± 5%, Vss= 0, TA = 0 to 70·C unless otherwise noted)
Min
Typ
Max
Unit
Characteristic
Input High Voltage
Logic EXtal
Logic Reset
Vss + 2.0
Vss + 4.0
-
Vee
Vee
Input Low Voltage
Logic Extal, Reset
Vss - 0.3
-
Vss+0.8
Input Leakage Current
Logic
0 0-0 7
VOL
PD"
VSBB
VSB
ISBB
Output Low Voltage
Power Dissipation
Vee Standby
Power Down
Power Up
Standby Current
F6802
F6882
Capacitance
CIN
COUl
Vdc
-
Output High Voltage
Ao-A 15, RiiN, VMA, E
BA
0 0-0 7
Logic Inputs EXtal
Ao-A 15, RiiN, VMA
Condition
Vdc
~dc
1.0
2.5
-
-
V ss +O.4
Vdc
0.600
1.2
W
4.0
4.75
-
5.25
5.25
-
-
8.0
3.0
-
-
12.5
10
12
Vss +2.4
Vss +2.4
Vss + 2.4
-
VIN=O to 5.25 V, Vee= Max
Vdc
I LOAD = -206 ~dc, Vee = Min
ILOAD= -145 "Adc, Vee = Min
I LOAD = -100 "Adc, Vee= Min
-.
I LOAD = 1.0 mAdc, Vee= Min
Vdc
mA
pF
6
-
'In power-down mode, maximum power dissipation Is less than 42 mW.
Capacitances are periodically sampled. rather than 100% tested.
5-76
VIN=O, TA= 25·C, f= 1.0 MHz
F6802lF68821F6808
Timing Characteristics
Tables 10 and 11 contain timing characteristics
Information.
Table 10
Frequency Characteristics
F880A02
F8B02
Characteristic
Symbol
F88B02
Min
Max
Min
Max
Min
Max
Unit
0.1
1.0
0.1
1.5
0.1
2.0
MHz
fo
Frequency of Operation
fXTAL
4xfo
Crystal Frequency .
1.0
4.0
1.0
6.0
1.0
8.0
MHz
External Oscillator Frequency
0.4
4.0
0.4
6.0
0.4
8.0
MHz
tCYC
Cycle Time
1.0
10
0.666
10
0.5
10
P.s
450
450
9500
5000
280
280
9700
5000
220
210
9700
5000
ns
tPWEH
E High
Clock Pulse Width
E Low
tPWEL
tA, tF
Fall Time
-
25
-
25
-
20
ns
trc
Crystal Oscillator Startup Time
100
-
100
-
100
-
ms
Table 11
ReadlWrlte Timing
F8802
Symbol
tAO
t AV1
tAV2
Characteristic
Address Delay
F880A02
F88B02
Min
Max
Min
Max
Min
Max
Unit
-
270
-
220
ns
240
310
-
180
200
235
ns
-
70
-
60
10
~
10
tOSA
Address Delay (Internal RAM)
Read Access Time Useable by Peripheral @ 1 MHz
tAce= tCYC- tAO + tosA+ tF
Data Setup Time (Read)
100
tOHA
Input Data Hold Time
10
-
270
605
tOHW
Output Data Hold time
30
20
20
-
20
Address Hold Time (Address, R/W, VMA)
-
20
tAH
20.
-
toow
Data Delay Time (Write)
-
225
-
170
-
160
tpcs
tpCA, tPCF
Processor Controls
Processor Control Setup Time
Processor Control Rise and Fall Time
(Does Not Apply to RESEn
(Measured between 0.8 V and 2.0 V)
200
-
140
-
110
-
-
100
-
100
-
100
ns
ns
ns
ns
ns
ns
Note
If programs are not executed from on·board AAM, TAVl applies. If programs are to be stored and executed from on·board RAM, TAV2 applies. For normal data
storage In the on·board RAM, this extended delay does not apply. Programs cannot be exeucted from on·board RAM when using A and B parts (F68A02, F68AOB,
F68BOB). One·board RAM can be used for data storage with all parts.
5·77
•
F6802/F6882/F6808
Bus Timing Characteristics
F68D2NS
F68D2
F68D8
Symbol
Parameter
Min
G) Cycle Time
Max
Min
Max
F68BD2
F68BD8
Min
Max
Unit
1.0
10
0.667
10
0.5
10
I's
PWEL
o
Pulse Width, E Low
450
5000
280
5000
210
5000
ns
PWEH
CD Pulse Width, E High
450
9500
280
9700
220
9700
ns
t r, tf
8) Clock Rise and Fall Time
-
25
-
25
-
20
ns
tAH
® Address Hold Time
20
20
-
20
ns
10
-
tCYC
IAV1
@ Non·Muxed Address Valid Time to E (See Note 5)
160
-
100
-
50
-
270
-
-
@ Read Data Setup Time
@ Read Data Hold Time
@ Write Data Delay Time
@ Write Data Hold Time
@ Usable Access Time (See Note 4)
100
-
70
10
-
10
-
-
225
-
170
-
160
ns
30
-
20
-
20
-
ns
tAV2
tOSR
tOHR
toow
tOHw
tACC
605
E
RIW ADDRESS
(NON·MUXED)
--t...,...
READ DATA
NON·MUXED _ _+_~
NOTE
WRITE DATA
NON·MUXED
----..3:
Notes
1.
2.
3.
4.
F68AD2
F68AD8
Voltage levels shown are VL oS 0.4 V, VH '" 2.4 V, unless otherwise specified.
Measurement pOints shown are O.B V and 2.0 V, unless otherwise noted.
All electricals shown for the F6802 apply to the F6802NS and F680B, unless otherwise noted.
Usable access time is computed by 12+ 3+ 4-17.
5·78
310
60
235
ns
ns
ns
ns
F6802/F6882/F6808
FIg.15
Read Data from Memory or Peripherals
PW~H
t,
R/W
-----~~I
.... tDSA .....
DATAFROM ___~__________________________~~~~~~~~~~~
MEMORY OR
PERIPHERALS
0.8 V
~ DATA NOT VALID
Note
Timing measurements are referenced to and from a low voltage of 0.8 volts and a high voltage of 2.0 volts. unless otherwise noted.
Fig. 16
Write Data In Memory or Peripherals
~---- PW~H---"'"
E
R/W
~4----PW~L-----{f--------------------~
---""'-~~~r
DATA ______~____________________~----~~~~~~~~1il
FROM MPU
~
DATA NOT VALID
Note
Timing measurements are referenced to and from a low voltage of 0.8 volts and a high voltage of 2.0 volts. unless otherwise noted.
Fig. 17
Bus Timing Test Load
4.75 V
C
=
Rl = 2.2 kO
130 pF FOR 0 0-0,. E
90 pF FOR Ao-A, •• R/W. AND VMA
= 30 pF FOR BA
R = 11.7 kG FOR 0 0-0,. E
16.5 kG FOR Ao-A, •• R/W. AND VMA
24 kll FOR BA
=
TEST POINT
0-...-.....
---1(
c
MMD6150
OR EQUIV.
R
MMD7000
OR EQUIV.
5-79
•
F6802lF68821F6808
Ordering Information
Speed
Temperature Range
F6802P, S
1.0 MHz
F6882P,S
1.0 MHz
F6802CP, CS
1;0 MHz
Order Code
F68A02P,S
1.5 MHz
+ 70·C
+ 70·C
- 40·C to + 85·C
O·C to + 70·C
F68A02CP, CS
1.5 MHz
-40·Cto -t:85·C
F68B02P,S
2.0 MHz
O·C to
O·C to
O·C, to
+ 70·C
P = Plastic package
S = Ceramic package
5-80
F6809
Central Processing Unit
Advance Product Information
Microprocessor Product
Description
Connection Diagram
The Fairchild F68098-bit Microprocessor is an advanced,
high-performance member of the F6800 family. It offers
greater throughput, improved byte efficiency, and
increased adaptability to various software disciplines,
Including position-independent code, re-entrancy,
recursion, block structuring, and high-level language
generation. The F6809 is compatible with all F6800
peripheral devices and Is upward source code
compatible with F6800-serles microprocessors.
vss
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
XTAL
IRQ
EXTAL
FIRQ
RES
BS
Architectural improvements, such as additional 16-bit
registers and dual 8-bit data paths, allow for powerful
enhancements to the instruction set and addressing
capabilities.
•
NMI
MRDY
BA
Q
vee
E
IlMAiBREQ
R/W
Compatible with Entire F6800 Family
-Hardware Interfaces with all F6800 Peripherals
-Software Has Upward-Compatible Instruction Set
and Addressing Modes
Two 16-Bit Index Registers
Two Indexable 16-Blt Stack Pointers
Two 8-Blt Accumulators Can Be Concatenated to
Form One 16-Blt Accumulator
Direct Page Register Allows Direct Addressing
Throughout Memory Map
Single + 5 V Supply
On-Chip Oscillator
MRDY Input Extends Data Access Time for Use with
Slow Memory
DMA/BREQ Allows Access to Bus for DMA and
Memory Refresh
Fast Interrupt Request (FIRQ) Stacks Only Program
Counter and Condition Code Register
Interrupt Acknowledge Output Allows Vectoring by
Device
Sync Acknowledge Output Allows for Synchronization
to External Event
16-Blt Arithmetic (ADD, SUBTRACT, COMPARE,
LOAD, STORE)
8 x 8 Unsigned Multiply
Transfer/Exchange all Registers
Push/Pull all Registers
Ten Addressing Modes
Expanded Indexed AddreSSing, Accumulator or up to
16-Blt Offset, Auto-Increment/Decrement by One
or Two
True Indirect Addressing
Load-Effective Address
(Top View)
5-81
F6809
Block Diagram
...--vee
+-Vss
DMAIBREQ
RIW
HALt
BA
BS
XTAL
EXTAL
MRDY
L-_ _. .
5·82
E
Q
F681 O/F68A1O/F68B1 0
128 x 8-Bit Static Random
Access Memory
Microprocessor Product
Logic Symbol
Description
The F6810 128 x 8-bit static RAM is a byte-organized
memory designed for use in bus-organized systems.
Fabricated with n-channel, silicon-gate technology, the
device is available in three frequency ranges: 1.0 MHz
(F6810), 1.5 MHz (F68A10), 2.0 MHz (F68B10). The device,
which operates from a single power supply, is
compatible with TTL and DTl; it needs no clocks or
refreshing because of its static operation.
10
The memory is compatible with the F6800 microcomputer
family, providing random storage in byte increments.
Memory expansion is provided through multiple chip
select inputs.
Organized as 128 Bytes of 8 Bits
Static Operation
Bidirectional 3-State Data Input/Output
Six Chip Select Inputs
(Four Active LOW, Two Active HIGH)
• Single + 5 V Power Supply
• TTL-Compatible
• Maximum Access Time:
450 ns for F6810
360 ns for F68A10
250 ns for F68B10
23
Ao
22
A,
21
A,
20
Ao
19
A4
18
As
17
A,
•
•
•
•
11
12
13
3
4
R/W
16
6
7
8
9
Vee = Pin 24
Vss = Pin 1
Connection Diagram
24-Pin DIP
Vee
Vss
CSO-CS5
15
F6810
2
Pin Names
Do-D7
Ao-A6
14
Bidirectional Data Bus
Address Inputs
Chip Select Inputs
Read/Write Input
Do
Ao
D,
A,
D,
A,
Do
Ao
D.
A4
Ds
As
A,
D,
. D7
R/Vi
eso
Clis
CS4
CS:1
es,
(Top View)
5-83
F681 O/F68A1O/F688 10
Block Diagram
As
Do
..
..
..
•
..
0,
.
A,
•
..
..
MEMORY
MATRIX
(121 x I)
ADDRESS
DECODE
3-STATE
BUFFER
o.
05
A.o
0,
As
A.o
..
07
~
.........
I
CSo
U-
MEMORY
CONTROL
t
h.
RIW
.....
Signal Function Descriptions
Mnemonic
Pin
No.
Bus Handshake
17-23
Ao-As
00-07
Chip Control
CSO-CS5
R/W
2-9
Name
Absolute Maximum Ratings
Supply Voltage
Input Voltage
Operating Temperature - TL, TH
F6810, F68A10, F68B10
F6810C, F68A10C
F6810DM
Storage Temperature Range
Thermal Resistance - OJA
Description
Address Input signal lines con·
taining address to
Bus
which data is to be
written or from which
data is to be read
Data
Bus
Chip
Select
Input signal lines that
prepare the device for a
read or write operation
16
Readl
Write
Input signal lines that
selects a chip read or
write operation; a HIGH
selects memory read.
and a LOW selects
memory write
Supply
O·C,
- 40·C,
-55·C,
-65·C,
+ 70·C
+ 85·C
+125·C
+ 150·C
82.5·CiW
These are stress ratings only, and functional operation at these ratings, or
under any conditions above those indicated in this data sheet, is not
implied. Exposure to the absolute maximum rating conditions for extendec
periods of time may affect device reliability, and exposure to stresses
greater than those listed may cause permanent damage to the device.
Recommended Operating Conditions
Symbol
Ground Ground for supply and
signals
24
-0.3 V, +7.0V
-0.3 V, + 7.0 V
This device contains circuitry to protect the inputs against damage due
to high static voltages or electric fields; however, it is advised that
normal precautions be taken to avoid application of any voltage higher
than maximum rated voltages.
Bidirectional inputl
output signal lines over
which data is read from
or written to the device
10-15
Supply
Vss
Vee
03
+ 5 V supply voltage
5-84
Characteristic
Min
Typ
4.75
5.0
Max
Unit
5.25
V
Vee
Supply Voltage
VIH
Input HIGH Voltage
2.0
5.25
V
VIL
Input LOW Voltage
-0.3
0.8
V
F6810/F68A10/F68B10
DC Characteristics Vee
Symbol
= 5.0 V ±5%, Vss =
0, TA
= TL to TH, unless otherwise noted.
Min
Characteristic
liN
Input Current (An, RIW, CSn, CSn)
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
ILO
Output Leakage Current, 3-State
lee
Supply Current
CIN
Input Capacitance
COUT
Output Capacitance
Bus Timing Characteristics Vee
Typ
Unit
2.5
p.A
2.4
V ±50f0, Vss
= 0,
TA
Conditions
= 0 to 5.25 V
= -205 p.A
IOL = 1.6 mA
CS = 0.8 V or CS = 2.0 V,
Vo = 0.4 V to 2.4 V
VIN
V
F6810
F68A10, F68B10
= 5.0
Max
= TL to
IOH
0.4
V
10
p.A
80
100
mA
Vee = 5.25 V, all other pins
grounded, TA
O°C
7.5
pF
12.5
pF
= 1.0 MHz,
TA = 25°C
=
f
TH, unless otherwise noted.
-------,------------------------,-----------,------------,-----------,-----Symbol
Unit
Characteristic
Read (Figure 1)
tcyc(R)
Read Cycle Time
tacc
Access Time
tAS
Address Set-up Time
tAH
Address Hold Time
tOOR
450
250
360
450
20
20
20
0
0
0
Data Delay Time (Read)
230
ns
250
360
ns
ns
180
220
ns
ns
tRes
Read-to-Select Delay Time
0
0
0
ns
tOHA
Data Hold from Address
10
10
10
ns
tH
Output Hold Time
10
10
10
ns
tOHR
Data Hold from Read
10
tRH
Read Hold from Chip Select
80
10
60
10
50
ns
0
0
0
ns
450
360
250
ns
20
20
20
ns
0
0
0
ns
300
250
210
ns
0
0
0
ns
190
80
60
ns
10
10
10
ns
0
0
0
ns
Write (Figure 2)
tcyC(W)
Write Cycle Time
tAS
Address Set-up Time
tAH
Address Hold Time
tes
Chip Select Pulse Width
twes
Write-to-Chip Select Delay Time
tosw
Data Set-up Time (Write)
tH
Input Hold Time
tWH
Write Hold from Chip Select
5-85
•
F681 O/F68A 1O/F68B 10
Fig. 1
Read Cycle Timing
I~_ _ - - - - - t a c c
tcyc{R)
.
2.0V
ADDRESS
0.8 V
\_-IAH_
2.0 V
CS
cs
..
0.8 V
2.0 V
- IAH I_
0.8 V
2.0V
R/W
2.4 V
DATAOUT-------------------------(
0.4 V
Don't Care
Note
CS and Cs can be enabled for consecutive read cycles, provided
remains at VIH.
ANV'
5·86
F681 O/F68Al O/F68Bl 0
Fig. 2
Write Cycle Timing
~
I - - - - - - - - - - - - - I , y , CW)
11 . . .
I
ADDRE~-:-:-:------------------------------------------------,~~------------
1_
lAS
-I
I..
-1- -I
les
0.av~20V
\]
~'--_ _ _ _ _ _ _ __
CS _ _ _ _ _:::::.;:.;_;t;;I.J.'.J..I.."'"'""'"'"1J
~--------~~~~~~~
2.ov1I1
~81",",,"---o.av
_
-_[twes - -
BL.av
R/W
IAH
_-..J!Il
1
I. . .
f-----
DATAtN~:·.::
losw
..
DATAtNSTABLE
I
I
IWH
r~,..,..,..,..,..,..,..,..,..,..,..,..,..
!IIIIII/A
tH
[.-
"'"'1"1">"'1"1""""""""""'"' ' '"
W_=
Don't Care
Nole
es and CS can be enabled for consecutive write cycles, provided ANi is
strobed to VIH before or coincident with the address change, and remains
HIGH for time tAS.
Timing Conditions
The conditions under which the timing characteristics
have been determined are as follows:
Fig. 3 Output Load
--<.-..--1< If-CB'j
B
CB,
CONTROLS
PIA ReadlWrite (RNi), Pin 21 - T.his signal is generated
by the MPU to control the direction of data transfers on
the data bus. A LOW on the PIA read/write line enables
the input buffers, and data is transferred from the MPU
to the PIA on the E signal if the device has been
selected. A HIGH on the read/write line sets up the PIA
for a transfer of data to the bus. The PIA output buffers
are enabled when the proper address and the E pulse
are present.
PIA Interface Signals for MPU
The PIA interfaces to the F6800 MPU with an 8·bit
bidirectional data bus, three chip select lines, two
register select lines, two interrupt request lines, a
read/write line, an enable line, and a reset line. These
signals, in conjunction with the F6800 VMA output,
permit the MPU to have complete control over the PIA.
The VMA signal should be utilized in conjunction with an
MPU address line into a chip select of the PIA.
RESET, Pin 34 - The active·LOW RESET line is used to
reset all register bits in the PIA to a logic 0 (LOW). This
line can be used as a power·on reset and as a master
reset during system operation.
PIA Bidirectional Data (00.07), Pins 26·33 - The
bidirectional data lines (00.07) allow the transfer of data
between the MPU and the PIA. The data bus output
drivers are 3·state devices that remain in the high·
impedance (OFF) state except when the MPU performs a
PIA read operation. The read/write line is in the read
(HIGH) state when the PIA is selected for a
read operation.
PIA Chip Select (CSo, CSl, and CS2), Pins 22·24 - These
three input signals are used to select the PIA. eso and
eS1 must be HIGH and eS2 must be LOW for selection
of the device. Data transfers are then performed under
the control of the enable and read/write signals. The chip
select lines must be stable for the duration of the E
pulse. The device is "deselected" when any of the chip
selects are in the inactive state.
PIA Enable (E), Pin 25 - The enable (E) pulse is the only
timing signal that is supplied to the PIA. Timing of all
other signals is referenced to the leading and trailing
edges of the E pulse. This signal is normally a derivative
of the F6800 and R/W Valid to Enable Positive Transition
160
ns
tOOR
Data Delay Time
tH
Data Hold Time
10
tAH
Address Hold Time
10
tEr, tEl
Rise and Fall Time for Enable Input
320
ns
ns
ns
25
ns
Figures 11 and 12
Write
1.0
tcycE
Enable Cycle Time
PWEH
Enable Pulse Width, HIGH
0.45
ILS
25
ILS
PWEL
Enable Pulse Width, LOW
0.43
ILs
tAS
Set-up Time, Address and R/W Valid to Enable Positive Transition
160
ns
tosw
Data Set-up Time
195
ns
tH
Data Hold Time
10
ns
tAH
Address Hold Time
10
tEr, tEl
Rise and Fall Time for Enable Input
Fig. 1
Fig. 2
Peripheral Data Set·up Time
(Read Mode)
X
______J.
P~~.~PB~l
~
.• ~O.8~V~
__
~
___________________
1E_---J/~2.4V
-I
IPDSU
CA2 Delay Time
(Read Mode; CRA·S
E~O.4V
,. ."j \
2.0V
pAo·PAl
ns
25
-'L
/
1-
= CRA·3 =
1, CRA·4
ns
= 0)
\
J'+--m-4Vp
_-IRS"
~~.o~A~V______________-J;f
• Assumes part was deselected during any previous E pulse.
5-98
F6820
Fig. 3
CA2 Delay Time
(Read Mode; CRA·5
1, CRA·3
CRA·4
0.4
0)
V
--' 1
... - - - - - - - -
--'-1
C_A_'- - - 1 - - - - - - - (
I~
tr, tl
-----,Xc..:::.::...::~__
t-:
~-~'\I ~
0.4~
CA,
--~--------------.
=
=
Fig. 4
Peripheral CMOS Data Delay Times
CRA·3
1, CRA·4
(Write Mode; CRA·5
Fig.5
0)
Peripheral Data.and CB2 Delay Times
(Write Mode; CRB·5 = CRB·3 = 1, CRB·4
\
O.4V
1-
-------------~
PAO·PAl
0)
/
Ipow
~2~.47.V~--------------
PBo·PB7
0.4 V
H'~
2.4 V
0.4 V
Fig. 6
CB2 Delay Time
(Write Mode; CRB·5
;12.4 V \
CRB·3
= 1, CRB·4
0)
Note
;1
C~B=,= = = =_I- - ~I'I-~';';'4.;. v.;. le_. ~~~~~~~~_~_,____
CB2 goes LOW as a result of the positive transition of the E pulse.
Fig. 7
CB2 Delay Time
(Write Mode; CRB·5
1, CRB·3
CRB·4
0)
__I--,r"
-11- 1,,11
CB-,---+-----~i:-~:~:V~VX~-----
,. Assumes part was deselected during the previous E pulse.
__ le·'\1
IRs,._1 2.4~
~~
• Assumes part was deselected during the previous E pulse.
5-99
F6820
Fig. 8
Fig. 9
Interrupt Release Time
RESET LOW Time
I _ - - - - - . R l - - - - -__ I
_~2'4V
1-.~~~_"R~~~~~.~.2'4~V--
_ ____1__
IROA (lROB)
/
·The RESET line must be at VIH for a minimum of 1.0 .s before
addressing the PIA.
'
Fig. 11
Fig. 10
Bus Read Timing Characteristics
(Read Information from PIA)
Bus Write Timing Characteristics
(Write Information into PIA)
1 _ - - - - - t c y c E - - - - - - - <...1
"'--PWEH~
1_--,------tcycE-----__ 1
E
~
tEr ....-
l...-tAS----'
tDSW
-----..
~
.....- tEl
-.-
2.0 V
RS, CS, RIW
-
0.8 V
RS. CS, RIW
DATA BUS
0.8 V
DATA BUS
Fig. 12
Bus Timing Test Loads
LOAD B
LOAD A
(iRO ONLY)
00·07, PAo·PA7, PBo·PB7, CA2, CB2)
TEST POINT
-<..-..--K H"-JV\('v-C
5.0 V
IN914
OR EOUIV.
3k
TEST POINT ~ 5.0 V
1100 pF
C
R
130 pF for 00·07
30 pF for PAo·PA7. PBo·PB7, CA2, and CB2
11,7 kO for 00·07
24 kO for PAo·PA7, PBo-PB7, CA2 and CB2
5·100
I-'AH
I-'H
X X
2.0 V
LOAD C
(CMOS LOAD)
TESTPOINT~
I
30PF
F6820
Ordering Information
P
Speed
Order Code
1.0 MHz
F6820P,S
=
Plastic DIP
Temperature Range
ooe to
+ 70
0
e
S = Ceramic DIP
•
5·101
5·102
F6821/F68A21/F68821
Peripheral Interface Adapter
(PIA)
Microprocessor Product
Description
The F6821 Peripheral Interface Adapter (PIA) provides a
universal means of interfacing peripheral equipment to the
F6800 microprocessing unit (MPU). This device is capable
of interfacing the MPU to peripherals through two 8-bit
bidirectional data buses and four control lines, in three
speed ranges: 1.0 MHz (F6821), 1.5 MHz (F68A21), and 2.0
MHz (F68B21). No external logic is required for interfacing
to most peripheral devices.
Logic Symbol
23
CS,
The functional configuration of the PIA is programmed by
the MPU during system initialization. Each of the peripheral
data lines can be programmed to act as an input or output,
and each of the four control/interrupt lines may be
programmed for one of several control modes. This allows
a high degree of flexibility in the overall operation of
the interface.
25
E
21
RNi
40
CA,
39
CA,
18
CB,
2
36
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17
-~-----~~~-----~
RSo
35
RS,
22
CSo
24
(VMA)CS,
F6821
19
34
• 8-Bit Bidirectional Data Bus for Communication with
the MPU
• Two Bidirectional 8-Bit Buses for Interface to Peripherals
• Two Programmable Control Registers
• Two Programmable Data Direction Registers
• Four Individually Controlled Interrupt Input Lines, Two
Usable as Peripheral Control Outputs
• Handshake Control Logic for Input and Output Peripheral
Operation
• High-Impedance 3-State and Direct Transistor Drive
Peripheral Lines
• Program-ContrOlled Interrupt and Interrupt Disable
Capability
• CMOS Drive Capability on Section A Peripheral Lines
• Two-TTL Drive Capability on All A- and B-Section Buffers
• TTL-Compatible
• Static Operation
33 32 31
30 29 28 27 26
= Pin 20
Vss = Pin 1
Vee
Connection Diagram
40-Pin DIP
Vss
PA.
PA,
PA,
PA,
PA,
PAs
PAs
PA,
PB.
PB,
PB,
PB,
PB,
PBs
PBs
PB,
17
CB,
18
CB,
19
Vee
(Top-View)
5-103
IROA
38
IROB
37
•
F6821 IF68A21 IF68B21
Block Diagram
IROA
-.I---------------;::::=====~i~IN~T~E~R~R~Uf'PT;-·.-,ll-.cA,
STATUS
....
CONTROL A
. . - - . CA 2
L..-_ _ _.,.J
DO_
01~
D._
OAT A DIRECTION
REGISTER A
(DORA)
02_
0,0,_
0._
0,_
DATA BUS
BUFFERS
(DBB)
.......-. PAO
......... PAl
~PA2
BUS INPUT
PERIPHERAL
INTERFACE
........ PA 3
A
........ PA 4
REGistER
~PA5
(BIR)
......... PA6
~PA7
........... PS o
.......... PB l
PERIPHERAL
INTERFACE
B
CSo---'
CS 1 - - - - - .
CS 2 - - - .
RSO- - - '
RS1----"
Riw~
.......... PB 2
......... PB 3
.......... PB 4
......... PBs
CHIP
SELECT
AND
RiW'
. . - . PB 6
~PB7
CONTROL
ENABLE ------.
RESET----'
DATA DIRECTION
REGISTER B
(DORB)
I---------------------·-LI__:_J_!_~~_~_~_:_~I:::::::
,ROB ...
PIA/MPU Interface Signals
Data Bus (Do - 0 7), Pins 26-33
The bidirectional data lines allow the transfer of data
between the MPU and the PIA. The data bus output drivers
are 3-state devices that remain in the high-impedance
(OFF) state, except when the MPU performs a PIA read
operation. The read/write (R/W) line is in the read (HIGH)
state when the PIA is selected for a read operation.
The PIA interfaces to the F6800 MPU with an 8-bit
bidirectional data bus, three chip select lines, two register
select lines, two interrupt request lines, a read/write line,
an enable line, and a reset line (see Figure 1). These
signals, in conjunction with the F6800 VMA output, permit
the MPU to have complete control over the PIA. The
VMA output should be utilized in conjunction with an MPU
address line into a chip select of the PIA.
5-104
F6821/F68A21/F68B21
Fig. 1 PIA Bus Interface
CA,
~ CA:2
r------.. . . . . ..,
I
SECTION A
CONTROLS
ADATA
DATA DIRECTION REG A
SECTIONA
~
DATA
INTERFACE
CONTROL REG A
BDATA
OATA DIRECTION REG B
W
ECTIONB
DATA
INTERFACE
CONTROL REG B
~
~
DATA ADDRESS
BUS
BUS
BUS
CONTROL
•
Enable (E), Pin 25
The enable input pulse is the only timing signal that is
supplied to the PIA. Timing of all other signals is
referenced to the leading and trailing edges of the E pulse.
This signal is normally a derivative of the <1>2 F6800 clock.
CB'I SECTION B
CB, CONTROLS
Register Select (RS o, RS 1), Pins 35, 36
The two register select inputs are used to select the various
registers within the PIA. These two lines are used in
conjunction with internal control registers to select a
particular register that is to be written to or read from.
The register select lines should be stable for the duration of
the E pulse while in the read or write cycle.
Read/Write (R/W), Pin 21
This input signal is generated by the MPU to control the
direction of data transfer on the data bus. A LOW on the
R/IN line enables the input buffers and allows data transfer
from the MPU to the PIA on the E signal if the device has
been selected. A HIGH on the R/IN line sets up the PIA for
a transfer of data to the bus; the PIA output buffers are
enabled when the proper address and the E pulse
are present.
Interrupt Request (IROA, IROB), Pins 37, 38
The active-LOW interrupt request inputs act to interrupt the
MPU either directly or through interrupt priority circuitry.
These lines are open drain (no load device on the chip).
This permits all interrupt request lines to be tied together
in a wired-OR configuration.
Each interrupt request line has two internal interrupt flag
bits that can cause either line to go LOW. Each flag bit is
associated with a particular peripheral interrupt line. Four
interrupt enable bits are also provided in the PIA; these may
be used to inhibit a particular interrupt from a
peripheral device.
Reset (RESET), Pin 34
The active -LOW RESET input is used to reset all register bits
in the PIA to a logic 0 I LOW) state. This line can be used
as a power-on reset and as a master reset during
system operation.
Servicing an interrupt by the MPU is accomplished by
a software routine that. on a priority basis. sequentially
reads and tests the two control registers in each PIA for
interrupt flag bits that are set.
Chip Select (CSo - CS2), Pins 22-24
These three input signals are used to select the PIA. The
CSc and CS1 lines must be HIGH and CS2 must be
LOW for selection of the device. Data transfers are
then performed under control of the enable and read/write
signals. The device is "deselected" when any of the chip
select lines is in the inactive state.
The interrupt flags are cleared Iset to 0) as a result of an
MPU read peripheral data operation of the corresponding
data register. After being cleared. the interrupt flag bit
cannot be enabled until the PIA is "deselected" during
an E pulse. The E pulse is used to condition the
interrupt control lines ICA 1• CA 2• CB 1. CB 2 ). When these
The chip select lines should be stable for the duration of
the E pulse.
5·105
•
F6821 IF68A21 IF68B21
lines are used as interrupt inputs, at least one E pulse must
occur from the inactive edge to the active edge of the
interrupt input signal to condition the edge sense network.
If the interrupt flag has been enabled and the edge sense
circuit has been conditioned properly, the interrupt flag is
set on the next active transition of the interrupt input pin.
transition for these signals is also programmed by the two
control registers.
Peripheral Control (CA 2, CB 2), Pins.39, 19
Peripheral control line CA2 can be programmed to act as an
interrupt input or as a peripheral control output. As an
output, this line is compatible with standard TTL; as an
input, the internal pull-up resistor on this line represents
one standard TTL load. The function of this signal line is
programmed by control register A (CRA).
PIA/Peripheral Interface Signals
The PIA provides two 8-bit bidirectional data buses and four
interrupt/control lines for interfacing to peripheral devices.
Peripheral control line CB2 may also be programmed to
act as in interrupt input or peripheral control output. As an
input, this line has high input impedance and is compatible
with .standard TTL. As an output, it is compatible with
standard TTL and may also be used as a source of up to
1 .mA at 1.5 V to drive the base of a transistor switch directly.
This line is programmed by control register B (CRB).
Section A Peripheral Data (PA o - PA 7 ), Pins 2-9
Each of the peripheral data lines is programmed to act
as an input or output. This is accomplished by setting a 1
in the corresponding data direction register (DDR) bit for
those lines that are to be outputs. A 0 in a bit of the DDR
causes the corresponding peripheral data line to act as an
input. During an MPU read peripheral data operation, the
data on peripheral lines programmed to act as inputs
appears directly on the corresponding MPU data bus lines.
In the input mode, the internal pull-up resistor on these
lines represents a maximum of one standard TTL load.
It is recommended that the control lines (CAt, CBt, CA2,
CB2) be held in a logic 1 state when the RESET line is
active to prevent setting of corresponding interrupt flags in
the control register when RESET goes to an inactive state.
Subsequent to RESET going inactive, a read of the data
registers may be used to clear any undesired
interrupt flags.
The data in output register A (ORA) appears on the data lines
that are programmed to be outputs. A logic 1 written into the
register causes a HIGH on the corresponding data line, while
a 0 results in a LOW. Data in ORA may be read by an MPU
read peripheral data A operation when the corresponding
lines are programmed as outputs. This data is read properly if
the voltage on the peripheral data lines is greater than 2.0 V
for a logic 1 output and less than 0.8 V for a logic 0 output.
Loading the output lines in such a way that the voltage on
these lines does not reach full voltage causes the data
transferred into the MPU during a read operation to differ
from that contained in the respective bit of output register A.
Internal Controls
There are six locations within the PIA that are accessible to
the MPU data bus: two peripheral registers, two data
direction registers, and two control registers. Selection of
these locations is controlled by the register select inputs,
together with bit 2 in the control register, as shown in Table 1.
Table 1 Internal Addressing
Control
Register Bit
Section B Peripheral Data (pB, - PB 7), Pins 10-17
The peripheral data lines in the B section of the PIA can
be programmed to act as either inputs or outputs in a
manner similar to the A section lines. However, the output
buffers driving these lines differ from those driving. the A
section lines, having a 3-state capability that allows them to
enter a high-impedance state when the peripheral data line is
used as an input. In addition, data on peripheral data lines
PB o through PB T is read properly from those lines
programmed as outputs even if the voltages are below 2.0 V
for a HIGH. As outputs, these lines are compatible with
standard TTL and may also be used as a source of up to
1 mA at 1.5 V to drive the base of a transistor switch directly.
CRA-2 CRB-2
RS,
RSo
0
0
1
X
Peripheral Register A
Location Selected
0
0
0
X
Data DirectIOn Register A
0
t
X
X
Control Register A
1
0
X
1
Peripheral Register B
1
0
X
0
Data Direction Register B
t
1
X
X
Control Register B
x = Don't Care
Interrupt Input (CA" CB,), Pins 18 and 40
The interrupt input lines are input-only lines that set the
interrupt flags of the control registers. The active
Initialization
A LOW on the RESET line has the effect of zeroing all PIA
registers. This sets PAo - PA 7, PB o - PB 7 , CA 2, and CB 2
5·106
F6821/F68A21/F68B21
as inputs and disables all interrupts. The PIA must be
configured during the restart program that follows the reset.
CA2. and CB2i. In addition. they allow the MPU to enable
the interrupt lines and monitor the status of the interrupt
flags. Bits 0 through 5 of the two registers may be written to
or read from by the MPU when the proper chip select
and register select signals are applied. Bits 6 and? of the
two registers are read-only and are modified by external
interrupts occurring on the peripheral control lines. The
format of the control words is shown in Table 2.
Register Operation
Possible configurations of the data direction and control
registers are as follows:
Data Direction Registers (DORA, DDRB)
The two data direction registers allow the MPU to control
the direction of data through each corresponding peripheral
data line. A DDR bit set to 0 configures the corresponding
peripheral data line as an input; a 1 results in an output.
Table 2
Control Registers (CRA, CRB)
The two control registers allow the MPU to control the
operation of the four peripheral control lines (CA,. CB1.
Table 3
7
6
CRA
IROA,
IROA2
7
6
CRB
IROB,
IROB2
5
I
4
I
3
CA2 Control
5
4
3
CB2 Control
1 ~
2
DDRA
Access
1
2
DDRB
Access
0
CA, Control
0
CB, Control
Interrupt Input Line Control Bits
CRA-1
(CRB-1)
CRA-O
(CRB-O)
Table 4
Control Word Format
MPU Interrupt
Request
IRQA (IRQB)
Interrupt Flag
CRA-7 (CRB-7)
Interrupt Input
CAl (CB,)
0
0
I Active
Set HIGH on I of CAl I CB,i.
Disabled; IRQ remains HIGH.
0
1
I Active
Set HIGH on I of CAl ICB,I.
Goes LOW when interrupt
flag bit CRA-? ICRB-?) goes
HIGH.
1
0
t Active
Set HIGH on t of CAl ICB,I.
Disabled; IRQ remains HIGH.
1
1
t Active
Set HIGH on t of CAl ICB,).
Goes LOW when interrupt
flag bit CRA-? ICRB-?) goes
HIGH.
Peripheral Control Line Control Bits (CRA-5/CRB-5 LOW)
MPU Interrupt
Request
IRQA (lRQB)
CRA-5
(CRB-5)
CRA-4
(CRB-4)
CRA-3
(CRB-3)
Interrupt Input
CA 2 (CB 2)
0
0
0
I Active
Set HIGH on I CA2
ICB21.
Disabled; IRQ remains
HIGH.
0
0
1
I Active
Set HIGH on I of CA2
(CB2i.
Goes LOW when inteJrupt
flag bit CRA-6 (CRB-61
goes HIGH.
0
1
0
t Active
Set HIGH on t of CA2
(CB21.
Disabled; IRQ remains
HIGH.
0
1
1
t Active
Set HIGH on t CA2
(CB2i.
Goes LOW when interrupt
flag bit CRA-6 (CRB-61
goes HIGH.
Interrupt Flag
CRA-6 (CRB-6)
Notes
1. I indicates negative transition I HIGH-ta-LOWI.
2. 1 indicates positive transition I LOW-ta-HIGHI.
3. The interrupt flag bit.CRA-7. is cleared by an MPU read of the A data register. and CRB-7 is cleared by an MPU read of the B data register.
4. If CRA-O ,CRB-O' is LOW when an interrupt occurs linterrupt disabled' and is later brought HIGH. 1RQil.
occurs after CRA-O ,CRB-ol is written to a ,.
,TFiQli,
5-107
•
F6821/F68A21/F68B21
Data Direction Access Control Bit (CRA-2, CRB"2)
Bit 2 in each control register allows selection of either a
peripheral interface register (PIR) or the DDR when
the proper register select signals are applied to RSo
and RS1.
and CRB-O are used to enable MPU interrupt signals IROA
and IROB, respectively. Bits CRA-1 and CRB-1 determine
the active transition of the interrupt input signals
(see Table 31.
Peripheral control Line Control Bits
(CRA-3, CRA-4, CRA-5, CRB-3, CRB-4, CRB-5)
Bits 3, 4, and 5 of the two control registers are used to control
the CA 2 and CB 2 peripheral contro'l lines. These bits
determine if the control lines act as interrupt inputs or as
control outputs. If bit CRA-5 (CRB-51 is LOW, CA 2 (CB 21is
an interrupt input line similar to CA 1 (CB 11 (see Table 41.
When CRA-5 (CRB-51 is HIGH, CA 2 (CB21 becomes an
output that may be used to control peripheral data transfers.
When in the output mode, CA 2 and CB 2 have slightly
different characteristics (see Table 5 and Table 6).
Interrupt Flag Control Bits (CRA-6, CRA-7, CRB-6, CRB-7)
The four interrupt flag bits are set by active transitions of
signals on the four interrupt and peripheral control lines
when those lines are programmed to be input lines. These
bits cannot be set directly from the MPU data bus and are
reset indirectly by a read peripheral data operation on the
appropriate section.
Interrupnnput Line Control Bits (CRA-O, CRA-1, CRB-O,
CRB-1)
The two lowest-order bits of the control registers are used
to control interrupt input lines CA1 and CB1. Bits CRA-O
Table 5
Control of CA 2 as an Output
CA2
CRA-5
CRA-4
CRA-3
1
0
0
LOW on the negative transition of E after an
MPU read data register A operation.
HIGH when interrupt flag bit CRA-? is set by an
active transition of the CA1 signal.
1
0
1
LOW on the negative transition of E after an
MPU read data register A operation.
HIGH on the negative edge of the first E pulse that
occurs while the device is deselected.
1
1
0
LOW when CRA"3 goes LOW a~ a result of
an MPU write control register A operation.
Always LOW as long as CRA-3 is LOW. Goes
HIGH on an MPU write control register A
operation that changes CRA-3 to 1.
1
1
1
Always HIGH as long as CRA-3 is HIGH.
Cleared on an MPU write control register A
operation that clears CRA-3 to O.
HIGH when CRA-3 goes HIGH as a result of an
MPU write control register Aoperation.
Table 6
Cleared
Set
Control of CB 2 as an Output
CB 2
CRB-5
CflB-4
CRB~
1
0
0
LOW on the positive transition of the first E
pulse following an MPU wri.te data register
B operation.
'.
HIGH when interrupt flag bit CRB-7 is set by an
active transition of the CB1 signal.
1
0
1
LOW on the positive transition of the first E
pulse after an MPU write data register B
operation.
HIGH on the positive edge of the first E pulse
following an E pulse that occurred while the
device was deselected.
1
1
0
LOW when CRB-3 goes LOW as a result of an
. ~PU write control registerS operation.
1
1
1
Always HIGH as long as CRB-3 is HIGH.
Cleared when an MPU write control register B operation results in clearing CRB-3 to O.
Cleared
Set
'.
5-108
Always LOW as long as CRB-3 is LOW. Goes
HIGH on an MPU write control register B
operation that changes CR B-3 to 1.
HIGH when CRB-3 goes HIGH as a result of an
MPU write control register B operation.
F6821/F68A21/F68B21
Absolute Maximum Ratings
Supply Voltage
Input Voltage
Operating Temperature - TL to TH
F6821. F68A21. F68B21
F6821 C. F68A21 C
F6821OM
Storage Temperature Range
Thermal Resistance
DC Characteristics Vee
Symbol
I
These are stress ratings only, and functional operation at these ratings, or
under any conditions above those indicated in this data sheet, is not implied.
Exposure to the absolute maximum rating conditions for extended periods of
time may affect device reliability, and exposure to stresses greater than those
listed may cause permanent damage to the device.
-0.3 V. +7.0 V
-0.3 V. +7.0 V
O°C. +70°C
-40° C. +85° C
-55°C. +125°C
-55°C. +150°C
82.5°C/W
= 5.0 V ±5%. Vss = O. TA = TL to TH. unless otherwise noted.
Characteristic
.
Min
I
Typ
Max
Unit
V
Condition
Bus Control Inputs (R/W. RESET. RSo RS1. CSo. CS 1 • ~2)
VIH
Input HIGH Voltage
Vss + 2.0
Vee
VIL
Input LOW Voltage
Vss - 0.3
Vss + 0.8
V
2.5
p.A
VIN
7.5
pF
VIN
Vss + 0.4
V
10
p.A
5.0
pF
= 3.2 mA
VOH = 2.4 V
VIN = 0, T A = 25° C, f = 1.0 MHz
liN
Input Leakage Current
CIN
Capacitance
1.0
= 0 to 5.25 V
= O. TA = 25° C. f = 1.0 MHz
Interrupt Outputs (IROA. IROB)
VOL
Output LOW Voltage
ILOH
Output Leakage Current I o FF-State I
COUT
Capacitance
1.0
ILoad
Data Bus (00-07)
VIH
Input HIGH Voltage
Vss + 2.0
Vee
V
VIL
Input LOW Voltage
Vss - 0.3
Vss + 0.8
V
ITSI
3-State (OFF-State) Input Current
10
p.A
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
CIN
Capacitance
2.0
Vss + 2.4
V
Vss + 0.4
V
12.5
pF
= 0.4 to 2.4 V
ILOAD = -205 p.A
ILOAD = 1.6 mA
VIN = O. TA = 25°C. f = 1.0 MHz
VIN
Peripheral Bus (PAo-PA7. PB o-PB7. CAl. CA2. CB 1• CB 2)
liN
Input Leakage Current CA1, CB1
1.0
2.5
p.A
VIN
ITSI
3-State (OFF-State) Input Current
PBo-PB7, CB2
2.0
10
p.A
VIN
p.A
VIH
-10
mA
Vo
-2.4
mA
IIH
Input HIGH Current PAo-PA7. CA2
-200
IOH
Darlington Dr. Curro PBo-PB7. CB2
-1.0
IlL
Input LOW Current PAo-PA7, CA2
VOH
Output HIGH Voltage
PAo-PA7, PBo-PB7, CA2, CB2
PAo-PAl, CA2
VOL
Output LOW Voltage
CIN
Capacitance
-400
-1.3
V
= 2.4 V
= 1.5 V
VIL = 0.4 V
= -200 p.A
= -10 p.A
ILoad = 3.2 mA
VIN = 0, TA = 25°C, f = 1.0 MHz
ILoad
ILoad
Vss +2.4
Vee-1.0
Vss + 0.4
V
10
pF
550
mW
Power ReqUirements
PD
= 0 to 5.25 V
= 0.4 to 2.4 V
Power Dissipation
5·109
•
F6821/F68A21/F68B21
Enable Signal Timing Characteristics Vee
= 5.0 V ±5%, Vss = 0, TA = TL to TH,
F6821
Symbol
Characteristic
Min
teyeE
Enable Cycle Time
PWEH
Enable Pulse Width, HIGH
450
PWEL
Enable Pulse Width, LOW
430
tEr, tEt
Enable Pulse Rise and Fall Times
Fig. 2
unless otherwise noted.
F68A21
Max
1000
F68B21
Unit
Figure
500
ns
2
280
220
ns
2
280
210
ns
2
ns
2
Unit
Figures
'Min
Max
666
25
Min
Max
25
25
Enable Signal Timing Characteristics
'E,
0.8 V
= 5.0 V ±5%, Vss = 0,
Bus Timing Characteristics Vee
TA
= TL to TH,
unless otherwise noted.
F6821
Symbol
Characteristic
Min
F68A21
Max
Min
F68B21
Max
Min
Max
tAS
Set-Up Time. Address and R/W
Valid to Enable Positive Transition
160
140
70
ns
3, 4
tAH
Address Hold Time
10
10
10
ns
3, 4
tOOR
Data Delay Time, Read
tOHR
Data Hold Time, Read
10
tosw
Data Set-Up Time, Write
tOHW
Data Hold Time, Write
320
ns
3, 5
10
10
ns
3, 5
19q
80
60
ns
4, 5
10
10
10
ns
4, 5
Fig. 3 Bus Timing Characteristics (Read from PIA)
II
220
180
Fig. 4 Bus Timing Characteristics (Write to PIA)
2.0V
A.2'0.V
fO:8V
0.8 V
_ _ _ _--J
••
DATA BUS
s~
2.0 V
0.8 V
DATA BUS
2.4 V
0.4 V
5·110
F6821/F68A21/F68B21
Peripheral Timing Characteristics Vcc
= 5.0 V ±5%, Vss = 0,
TA
= TL to TH,
F6821
Symbol
Characteristic
Min
unless otherwise noted.
F68A21
Max
Min
Max
Max
Figures
ns
9
ns
9
!,s
6,10,11
tPDH
Peripheral Data Hold Time
tCA2
Delay Time, Enable Negative Transition to CA2 Negative Transition
1.0
0.670
0.500
tRS,
Delay Time, Enable Negative Transition to CA2 Positive Transition
1.0
0.670
0.500
!,s
6, 10
tr, tf
Rise and Fall for CAl and CA2
Input Signals
1.0
1.0
1.0
!,s
6,11
tRS2
Delay Time from CAl Active Transition to CA2 Positive Transition
2.0
1.35
1.0
!,s
6,11
tPDW
Delay Time, Enable Negative Transition to Peripheral Data Valid
1.0
0.670
0.5
!,s
6,12,13
tCMOS
Delay Time, Enable Negative Transition to Peripheral CMOS Data
Valid PAo-PAl, CA2
2.0
1.35
1.0
!,s
7, 12
1.0
0.670
0.5
!,s
6, 14, 15
ns
6, 13
!,s
6,14
ns
6, 10, 14
tDC
Delay Time, Peripheral Data Valid
to CB2 Negative Transition
tRS,
Delay Time, Enable Positive Transition to CB2 Positive Transition
0
100
Unit
Peripheral Data Set, Up Time
Delay Time, Enable Positive Transition to CB2 Negative Transition
135
Min
tpDSU
tCB2
200
F68821
0
20
0
20
20
0.670
1.0
550
0.5
550
PWCT
Peripheral Control Output Pulse
Width, CA2/CB2
tr, tf
Rise and Fall Time for CB, and
CB2 Input Signals
1.0
1.0
1.0
!,s
15
tRS2
Delay Time, CB, Active Transition
to CB2 Positive Transition
2.0
1.35
1.0
!,s
6,15
Interrupt Release Time,
IROA and IROB
1.60
1.10
0.85
!,s
8,17
1.0
tlR
550
tRS3
Interrupt Response Time
!,s
8, 16
PW,
Interrupt Input Pulse Width
500
500
500
ns
16
tRL
Reset LOW Time'
1.0
0.66
0.5
!,s
18
~The
1.0
RESET line must be HIGH a minimum of 1.0 J.1.$ before addressing the PIA.
5·111
1.0
&I
F6821/F68A21/F68B21
Fig. 5 Bus Timing Test Load
Fig. 9 Peripheral Data Set-Up and Hold Times (Read
Mode)
(00-07)
5.0 V
2.0 V
0.8 V
TEST POINT -
.....-~-KII-..
j
IpDSU
C
130 pF
IN914
OR EQUIVALENT
1-
31:'
IpDH
i:-12.• V - -
_ _ _ _ _ _ _ _ _-J.
0.8V
Fig. 10 CA 2 Delay Time (Read Mode;
CRA-5 = CRA-3 = 1; CRA-4.= 0)
Fig. 6 TTL Equivalent Test Load
Vcc
~CA'
'~""~-.,/ ~~IR'"
...
: ,..-"..,.,._--P-W-C-T----,_:",'
TEST POINT -..---.~(}-......
2.' V
0.4 V
C
. Assumes Rart was deselected dunng the prevIous E pulse.
IN91.
OR EQUIVALENT
Fig. 11 CA 2 Delay Time (Read Mode;
CRA-5 = 1; CRA-3 = CRA-4 = 0)
c ~ 40 pF. R~ 12 k
Adjust RL so that I, ~ 3.2 mA
wilh V, ~ 0,4 V and Vee ~ 5.25 V
-1
[_1"1,
----f-----~ ~:-----:lix~:"'-·.:-:-_-
Fig. 7 CMOS Equivalent Test Load
C_A_'
(PAo·PA7. CA.)
CA,
130
-'~=\1
O.~
TESTPOINT~
'"~
1--1_ _ _ _ _ _- '
PF
Fig. 12 Peripheral CMOS Data Delay Times (Write
Mode; CRA-5 = CRA-3 = 1; CRA-4 = 0)
Fig. 8 NMOS Equivalent Test !-oad
(iiiQ ONLY)
!:.:V
TESTPOINT~
100 PF
J
r
F6821 IF68A21 IF68B21
Fig. 13 Peripheral Data and CB 2 Delay Times (Write Mode;
CRB-5 = CRB-3 = 1; CRB-4 = 0)
\
O.BV
/
I_i----------------Ipow
------------~
Fig. 16 Interrupt Pulse Width and IRQ Response
Note:
CB2 goes
LOW as a
result of
the positive
transition
of the E pulse.
~..:O..:.B..:V___________.....;~
IRQA/B
-'~~
CB,
IIV--
~20V
0.4 V
~
\
. . - tCB2
PWCT
CB,
II
Fig. 17 IRQ Release Time
Fig. 14 CB 2 Delay Time (Write Mode; CRB-5 = CRB-3 = 1;
CRB-4 = 0)
~ ...
Assumes interrupt enable bits are set.
-~-:
.. '''--j
-V----
~
_______________-J;I'~,2-..
• Assumes part was deselected during
the prevIOUs E pulse
Fig. 18 RESET LOW Time
I~.------IRL------<..
·I
Fig. 15 CB2 Delay Time (Write Mode; CRB-5 = 1; CRB-3 =
CRB-4 = 0)
y
RESET
'iO.BV
*The RESET line must be at VIH for a minimum of
1.0 JiS before addressing the PIA.
-I I-I,. If
--+-----tl-:~:'.::X~_
,
-CB
_ICB',I
CB,
IRo, __
1
Ordering Information
fr.v
~~2"V
0.' V
• Assumes part was deselected during
any previous E pulse.
Order Code
1.0 MHz
F6821P, S
F6821CP, CS
F6821DM
O°C t6 +70°C
_40° C to +85° C
-55°C to +125°C
1.5 MHz
F68A21P, S
F68A21 CP, CS
O°C to +70°C
-40° C to +85° C
2.0 MHz
P
5·113
Temperature Range
Speed
= Plastic
F68B21P, S
package, S
:=
Ceramic package
F6821 IF68A21 IF68821
5-114
F6840/F68A40/F68840
Programmable Timer (PTM)
Microprocessor Product
Description
The F68AO is a programmable subsystem component of
the F6800 family designed to provide variable system
time intervals.
Logic Symbol
25 24 23 22 21 20 19 18 17 28
4
7
15
The F6840 has three 16-bit binary counters, three
corresponding control registers and a status register.
These counters are under software control and may be
used to cause system interrupts and/or generate output
signals. The F6840 may be utilized for such tasks as
frequency measurements, event counting, interval
measuring and similar tasks. The device may be used
for square wave generation, gated delay signals, single
pulses of controlled duration, and pulse width modulation, as well as system interrupts.
16
10
11
0,
13
0,
27
0,
26
Vee
•
•
•
•
Operates From a Single +5V Power Supply
Fully TTL-Compatible
Single System Clock Required (Enable)
Selectable Prescaler on Timer 3 Capable of 4 MHz for the
F6840. 6 MHz for the F68A40. and 8 MHz for the F68B40
• Programmable Interrupt (IRQ) Output to MPU
• Readable Down Counter Indicates Counts to Go to
Time-Out
• Selectable Gating for Frequency or Pulse-Width
Comparison
vss
~
~
•
Pin 14
Pin 1
Connection Diagram
28-Pin DIP
.~Input
• Three Asynchronous External Clock and Gate/Trigger
Inputs Internally Synchronized
• Three Maskable Outputs
Pin Names
00-07
CSO-CS1
R/W
E
IRQ
RESET
RSo-RS2
C1-C3
131-<33
01-03
IRQ
12
V,,
<:,
G,
0,
0,
G,
<:,
Do
G,
0,
0,
0,
C,
0,
~
Bidirectional Data Lines
Chip Select Input
Read/Write Input
Enable (Systems Clock 2) until one of several predetermined
conditions causes it to halt or recycle. The timers are
thus programmable, cyclic in nature, controllable by
external inputs or the MPU program, and accessible by
the MPU at any time.
Bus Interface
The programmable timer module I PTM) interfaces to the
F6800 bus with an 8-bit bidirectional data bus, two Chip
Select lines, a Read/Write line, an Enable (System <1>2)
5·116
F6840/F68A40/F68B40
line, an Interrupt Request line, an external RESET line,
and three Register Select lines. These signals, in
conjunction with the F6800 VMA output, permit the MPU
to control the PTM. VMA should be utilized in
conjunction with the MPU address line into a Chip
Select of the PTM.
Interrupt Request (IRQ)
The active LOW Interrupt Request signal is normally
tied directly (or through priority interrupt circuitry) to
the IRQ input of the MPU. This is an open drain output
(no load device on the chip) which permits other
similar Interrupt Request lines to be tied together in a
wired-OR configuration.
Bidirectional Data (00-07)
The bidirectional Data Lines (00-07) allow the transfer of
data between the MPU and the PTM. The data bus output
drivers are 3-state devices which remain in the highimpedance (OFF) state except when the MPU performs a
PTM read operation (Read/Write and Enable lines HIGH
and PTM Chip Selects activated).
The IRQ line is activated if, and only if, the composite
interrupt flag (bit 7 of the internal status register) is
asserted. The conditions under which the IRQ line is
activated are discussed in conjunction with the
status register.
External RESET
A LOW level at this input is clocked into the PTM by the
Enable (System <1>2) input. Two Enable pulses are required
to synchronize and process the signal. The PTM then
recognizes the activE! LOW or inactive HIGH on the third
Enable pulse. If the RESET signal is asynchronous, an
additional Enable period is required if set-up times are not
met. The RESET input must be stable HIGH/LOW for the
minimum time stated in the AC Characteristics table.
Chip Select (CSo, CS1)
These two signals are used to activate the data bus
interface and allow transfer of data from the PTM. With
CSo = "0" and CS1 = "1 ", the device is selected and
data transfer will occur.
Read/Write (R/W)
This signal is generated by the MPU to control the
direction of data transfer on the data bus. With the
PTM selected, a LOW state on the PTM RiiN line
enables the input buffers and data is transferred from
the MPU to the PTM on the trailing edge of the
Enable (System <1>2) signal. Alternately (under the same
conditions), R/iN = "1" and Enable HIGH allows data in the
PTM to be read by the MPU.
Recognition of a LOW level at this input by the PTM
causes the following action to occur:
a. All counter latches are preset to their maximal
count values.
b. All control reg ister bits are cleared with the exception
of CR10 (internal reset bit), which is set.
c. All counters are preset to the contents of the latches.
d. All counter outputs are reset and all counter clocks
are disabled.
e. All status register bits (interrupt flags) are cleared.
Enable (E, System <1>2)
This signal synchronizes data transfer between the MPU and
the PTM. It also performs an equivalent synchronization
function on the external Clock, RESET, and Gate inputs of
the PTM.
Table 1
Register Selection
Operations
Register Select Inputs
RS2
RS1
RSo
R/W = "0"
0
0
0
CR20 = "0"
Write Control Register 3
R/W = "1"
CR20 = "1"
Write Control Register 1
0
0
1
Write Control Register 2
No Operation
Read Status Register
0
1
0
Write MSB Buffer Register
Read Timer 1 Counter
0
1
1
Write Timer 1 Latches
Read LSB Buffer Register
1
0
0
Write MSB Buffer Register
Read Timer 2 Counter
Read LSB Buffer Register
1
0
1
Write Timer 2 Latches
1
1
0
Write MSB Buffer Register
Read Timer 3 Counter
1
1
1
Write Timer 3 Latches
Read LSB Buffer Register
5·117
•
F6840/F68A40/F68B40
control register bits (except CR1o) are cleared.
Therefore, one may write in the sequence
CR3, CR2, CR,.
Register Select Lines (RSo, RS" RS2)
These inputs are used in conjunction with the R/Vii line
to select the internal registers, ·counters and latches as
shown in Table 1.
The least significant bit of control register 1 is used as
an internal reset bit. When this bit is a logic "0", all
timers are allowed to operate in the modes prescribed
by the remaining bits of the control registers. Writing a
"1" into CR10 causes all counters to be preset with the
contents of the corresponding counter latches, all
counter clocks to be disabled, and the timer outputs
and interrupt flags (status register) to be reset. Counter
latches and control registers are undisturbed by an
internal reset and may be written into regardless of· the
state of CR10.
It has been stated previously that the PTM is accessed
via MPU load and store operations in much the same
manner as a memory device. The instructions available
with the F6800 family of MPUs which perform
operations directly on memory should not be used
when the PTM is accessed. These instructions actually
fetch a byte from memory, perform an operation, then
restore it to the same address location. Since the PTM
uses the R/Vii line as an additional register select input,
the modified data may not be restored to the same
register if these instructions are used.
The least significant bit of control register 3 is used
as a selector for a +8 prescaler, which is available with
timer 3 only. The prescaler, if selected, is effectively
placed between the clock input circuitry and the input
to counter 3. It therefore can be used with either the
internal clock (Enable) or an external clock source.
Control Register
Three write-only registers in the F6840 are used to
modify timer operation to suit a variety of applications.
Control register 2 has a unique address space
(RSo="1", RS, ="0", RS2="0") and therefore may be
written into any time. The remaining control registers
(1 and 3) share the address space selected by a
logic "0" on all register select inputs. The least
significant bit of control register 2 (CR2o) is used as an
additional addressing bit for control registers 1 and 3.
Thus, with all Register Selects and R/Vii inputs at
logic "0", control register 1 will be written into if CR20
is a logic "0". Control register 3 can also be written into
after a reset LOW condition has occurred, since all
The functions depicted in the foregoing discussions
are tabulated on the first row in Table 2 for ease
of reference.
Control register bits CR10, CR20 and CR30 are unique in
that each selects a different function. The remaining bits
(1 through 7) of each control register select common
functions, with a particular control register affecting only
Table 2 Control Register Bits
CR10 Internal Reset Bit
CR20 Control Register Address Bit
o
All timers allowed to operate
1 All ti mers held in preset state
o
CRX,'
Timer X Clock Source
TX uses external clock source on CX input
TX uses Enable clock
CRX2
Timer X Counting Mode Control
TX configured for normal (16-bit) counting mode
TX configured for dual 8-bit counting mode
o
o
1
CRX3
CRX4
CRXs
CRX6
o
1
CRX7
o
1
1
CR3 may be written
CR1 may be written
CR30 Timer 3 Clock Control
o
T3 Clock is not prescaled
1 T3 Clock is prescaled by +8
Timer X Counter Mode and Interrupt Control (See Table 3)
Timer X Interrupt Enable· .
Interrupt Flag masked on iRQ
Interrupt Flag enabled to IRQ
Timer X counter Output Enable
TX Output masked on output OX
TX Output enabled on output OX
* Control Register for timer 1. 2 ·_or 3, Bit 1.
5·118
F6840/F68A40/F68B40
its corresponding timer. For example, bit 1 of control
register 1 (CR1,) selects whether an internal or external
clock source is to be used with timer 1. Similarly, CR2,
selects the clock source for timer 2, and CR3, performs
this function for timer 3. The function of each bit of
control register "X" can therefore be defined as shown
in the remaining section of Table 2.
An individual interrupt flag is also cleared by a write
timer latches (WI command or a counter initialization
(CII seq uence, provided that W or CI affects the timer
corresponding to the individual interrupt flag.
Counter Latch Initiali~ation
Each of the three independent timers consists of a
16-bit addressable counter and 16 bits of addressable
latches. The counters are preset to the binary numbers
stored in the latches. Counter initialization results in the
transfer of the latch contents to the counter. See the
notes in Table 5 regarding the binary number N, L or M
placed into the latches and their relationship to the
output waveforms and counter time outs.
Control register bit 2 selects whether the binary
information contained in the counter latches land
subsequently loaded into the counter) is to be treated
as a single 16-bit word or two 8-bit bytes. In the single
16-bit counter mode (CR2 = "0"), the counter will
decrement to zero after N + 1 enabled I G = "0") clock
periods, where N is defined as the 16-bit number in the
counter latches. With CRX2 = "1 ", a similar time-out will
occur after I L + 1 ) . 1M + 11 enabled clock periods, where
Land M, respectively, refer to the LSB and MSB bytes
in the counter latches.
Control register bits 3, 4, and 5 are explained in detail in
the Timer Operating Modes section. Bit 6 is an interrupt
mask bit which will be explained more fully in
conjunction with the status register, and bit 7 is used to
enable the corresponding timer output. A summary of
control register programming modes is shown in
Table 3.
Since the PTM data bus is 8 bits wide and the counters
are 16 bits wide, a temporary register I MSB buffer
register) is provided. This write-only register is for .the
most significant byte of the desired latch data. Three
addresses are provided for the MSB buffer register las
indicated in Table 11, but they all lead to the same
buffer. Data from the MSB buffer will be transferred
automatically into the most significant byte of timer X
when a write timer X latches command is performed. So
it can be seen that the F6840 has been designed to
allow transfer of two bytes of data into the counter
latches provided that the MSB is transferred first.
Status Register/Interrupt Flags
The F6840 has an internal read-only status register which
contains four interrupt flags. (The remaining four bits of the
register are not used, and default to "Os" when being read).
Bits 0, 1, and 2 are assigned to timers 1, 2, and 3,
respectively, as individual flag bits, while bit 7 is a
compOSite interrupt flag. This flag bit will be asserted if any
of the individual flag bits is set while bit 6 of the
corresponding control register is at a logic "1 ". The
conditions for asserting the compOSite interrupt flag bit can
therefore be .expressed as:
In the many applications, the source of the data will be
an F6800 MPU. It should be noted that the 16-bit store
operations of F6800 family microprocessors ISTS
and STXI transfer data in the order required by the
PTM. A store index register instruction, for example,
results in the MSB of the X register being transferred to
the selected address, then the LSB of the X register
being written into the next higher location. Thus, either
the index register or stack pointer may be transferred
directly into a selected counter latch with a single
instruction.
INT = I, . CR16
where INT
h
12
13
+
i2 • CR26
+
13 • CR36
A logic "0" at the RESET input also initializes the counter
latches. In this case, all latches will assume a maximum
count of 65,53610. It is important to note that an internal
reset (bit zero of control register 1 set) has no effect on
the counter latches.
= CompOSite Interrupt Flag I Bit 71
= Timer 1 Interrupt Flag I Bit 01
= Timer 2 Interrupt Flag (Bit 11
= Timer 3 Interrupt Flag IBit 21
An interrupt flag is cleared by a timer reset condition;
i.e., external RESET = "0" or internal reset bit ICR101 = "1 ".
It will also be cleared by a read timer counter command,
provided that the status register has previously been
read while the interrupt flag was set. This condition on
the read status register-read timer counter IRS-RTI
sequence is designed to prevent missing interrupts
which might occur after the status register is read, but
prior to reading the timer counter.
Counter Initialization
Counter initialization is defined as the transfer of data
from the latches to the counter with subsequent clearing
of the individual interrupt flag associated with the
counter. Counter initialization always occurs when a
reset condition (RESET) = "0" or CR10 = "1" is recognized.
It can also occur - depending on timer mode - with a
write timer latches command or recognition of a
negative transition of the gate input.
5·119
•
F6840/F68A40/F68840
Table 3
Control Register Programming
Register 2
Register 3
All timers operate
Reg #3 may be written
T3 Clk + 1
All ti mers preset
Reg #1 may be written
T3 Clk+ a
Register 1
o
o
External Clock
(CX In'put)
Internal Clock (Enable)
o
Normal (16-Bit) Count Mode
Dual a-Bit Count Mode
Continuous Operating Mode: Gate
j
or Write to latches or Reset Causes Counter Initialization
Frequency Comparison Mode: Interrupt if Gate U + i S < Counter Time-Out
Continuous Operating Mode: Gate
j
or Reset Causes Counter Initialization
Pulse Width Comparison Mode: Interrupt if Gate ~is < Counter Time-Out
Single Shot Mode: Gate
j
or Write to latches or Reset Causes Counter Initialization
Frequency Comparison Mode: Interrupt if Gate L n i s > Counter Time-Out
Single Shot Mode: Gate
j
or Reset Causes Counter Initialization
Pulse Width Comparison Mode: Interrupt if Gate
o
Interrupt Flag Masked (iRQ)
Interrupt Flag Enabled (IRQ)
o
Timer Output Masked
Timer Output Enabled
Note
Reset is Hardware or Software Reset (RESET)::::; 0 or CR1O::::; 11.
5-120
L---1 is > Counter Time-Out
F6840/F68A40/F68B40
Counter recycling or re-initialization occurs when a
negative transition of the clock input is recognized after
the counter has reached an all-"O" state. In this case,
data is transferred from the latches. to the counter.
cycle, and not recognized the next cycle, or vice versa.
E
INPUT
Ca-~-....,=:.::..::II---"" ~~r---
Asynchronous Input/Output Lines
PTM
RECOGNIZES
THIS EOGE
Each of the three timers within the PTM has external
clock and gate inputs as well as a counter output line.
The inputs are high impedance, TTL-compatible lines
and outputs are capable of driving two standard
TTL loads.
(e"
I
10
PTM
The Gate inputs of all timers dire.,£tly affect the internal
16-bit counter. The operation of G3 is therefore
independent of the +8 prescaler selection.
Timer Outputs (0" 02, 03)
Time~ outputs 0" 02 and 03 are capable of driving up
to two TTL loads and produce a defined output
waveform for either continuous or single-shot timer
modes. Output waveform definition is accomplished by
selecting either single 16-bit or dual 8-bit operating
modes. The single 16-bit mode will produce a squarewave output in the continuous timer mode and will
produce a single pulse in the single-shot timer mode.
The dual 8-bit mode will produce a variable duty cycle
pulse in both the continuous and single shot timer
modes. One bit of each control register (CRX7) is used
to enable the corresponding output. If this bit is cleared,
the output will remain LOW (VoLl regardless of the
operating mode.
E
INPUT
' - - OR HERE
OR
Gate Inputs (G1, G2, (3)
Input lines G" G2 and G3 accept asynchronous
TTL-compatible signals which are used as triggers or
clock gating functions to timers 1, 2 and 3, respectively.
The gating inputs are clocked into the PTM by the
Enable (System 2) signal in the same manner as the
previously discussed Clock inputs. That is, a Gate
transition is recognized by the PTM on the fourth
Enable pulse (provided set-up and hold time requirements are met), and the HIGH or LOW levels of the
Gate input must be stable for at least one system clock
period plus' the sum of the set-up and hold times. All
references to G transition in this document relate to
internal recognition of the input transition.
The external clock inputs are clocked in by Enable
(System 2) pulses. Three enable periods are used to
synchronize and process the external clock. The fourth
Enable pulse decrements the internal counter. This does
not affect the input frequency', it merely creates a delay
between a clock input transition and internal recognition
of that transition by the PTM. All references to C inputs
in this document relate to internal recognition of the
input transition. Note that a clock HIGH or LOW level
which does not meet set-up and hold time specifications
may require an additional Enable pulse for recognition.
When observing recurring events, a lack of synchronization will result in jitter being observed on the output
of the PTM when using asynchronous clocks and gate
input signals. There are two types of jitter. System
jitter is the result of the input signals being out of
synchronization with the Enable input (System 2),
permitting signals with marginal set-up and hold time to be
recognized by either the bit time nearest the 'input
transition or the subsequent bit time.
EITHER - - - '
HERE
PTM
External clock input 153 represents a special case when
timer 3 is programmed to utilize its optional +8 prescaler
mode. The maximum input frequency and allowable duty
cycles for this case are specified in the AC Characteristics
table. The output of the +8 prescaler is treated in the same
manner as the previously discussed clock inputs. That is, it
is clocked into the counter by Enable pulses, is .recognized
on the fourth Enable pulse (provided set-up and hold time
requirements are rnet), and must produce an output pulse
at least as wide as the sum of an enable period, set-up and
hold times.
C2 and C3)
Clock Inputs
Input pins C" C2 and C3 will accept asynchronous TTL
voltage level signals to decrement timers 1, 2 and 3,
respectively. The HIGH and .LOW levels of the external
clocks must e,ach be stable for at least one system
clock period plus the sum of the set-up and hold times
for the inputs. Theasynch.ronous clock rate can vary,
from dc to the limit imposed by Enable (System cf>2)
set-up and hold time.
:.:-u~G~r-
I
..
SYSTEM
t--BIT TIME
JITTER
I
OUTPUT----------~sr-L-J
Input jitter can be as great as the time between input
signal negative going transitions plus the system jitter, if
the first transition is recognized during one system
5-121
F6840/F68A40/F68B40
The continuous and single-shot timer modes are the
only ones for which output response is defined. Signals
appear at the outputs (unless CRX7 = "0") during
frequency and pulse width comparison modes, but the
actual waveform is not predictable in typical applications.
timers. These modes are outlined in Table 4.
Timer Operating Modes
Continuous Operating Mode (Table 5)
Any of the timers in the PTM may be programmed to
operate in a continuous mode by writinQ "Os" into
bits 3 and 5 of the corresponding control register.
Assuming that the timer output is enabled (CRX7 = "1"),
either a square wave or a variable duty cycle waveform
will be generated at the timer output, OX. The type of
output is selected via control register bit 2.
In addition to the four timer modes in Table 4, the
remaining control register bit is used to modify counter
initialization and enabling or interrupt conditions.
The F6840 has been designed to operate effectively in a
wide variety of applications. This is accomplished by
using three bits of each control register (CRX3, CRX4
and CRX5) to define different operating modes of the
Table 4 Operating Modes
Either a timer reset (C·RX10 = "1" or External
RESET = "0") condition or internai recognition of a
negative transition of the Gate input results in counter
initialization. A write timer latches command can be
selected as a counter initialization signal by
clearing CRX4.
Control Register
CRX3
CRX4
CRX5
Timer Operating Mode
0
Continuous
0
.
1
Single-Shot
1
0
Frequency C()mparison
1
1
.
0
~Defines
.
.
In the dual 8-bit mode (CRX2 = "1") Irefer to the
example in Figure 11 the MSB decrements once for
every full countdown of the LSB + 1. When the
Pulse Width Comparison
additional timer functions
Table 5 Continuous Operating Modes, (CRX3 = "0", CRX5 = "0")
Control Register
Initialization/Output Waveforms
CRX2
CRX4
Counter Initialization
0
0
GI
+ W + R
"Timer Output (OX) (CRX7 = "1")
r(N + I ) ( T ) TN + I ) ( T TN + I)(T1
I
0
1
GI + R
1
0
131 + W + R
1
1
131 +R
I
to
I
I
TO
TO
,-VOH
-VOL
. TOI
r ( L + I)(M + I ) ( T ) T ( L + I)(M + I)(T)....1
~-VOH
-VOL
I
131
W
R
N
L
'Io
-..l I.- .-..1 I.(L)(T)
10
TO
= Negative tranSition of Gate input
= Write Timer Latches Command
= Timer Reset (CR10 = "1" or External RESET = "0")
= 16-Bit Number in Counter Latch
=.8-Bit Number in LSB Counter Latch
M=
T =
to =
TO ,=
AII time'i~tervals shown above assume the Gate (GI and Clock ,CI
signals are synchronized to Enable {System q,21 with the specified
set~up and hold time requirements.
5-122
(L)(T)
TO'
8-Bit Number in MSB Counter Latch
Clock Input Negative Transitions to Counter
Counter Initialization Cycle
Counter Time-Out (All "0" Condition)
F6840/F68A40/F68B40
Fig. 1
Timer Output Waveforms Example
'TIME
EXAMPLE: CONTENTS OF MS8
CONTENTS OF lSB
03
04
+
L
I""..
r--------MIL
---,
+
t) •
1 - - - - - - - -..........1-0__-
ALGEBRAIC EXPRESSION
03(04 + 1) + 1 = 16 E
COUNTERI'
(M + 1)(L + 1) =0 Period
MIL + 1) + 1 = LOW portion of period
L = Pulse width
*Preset LSB and MSB to Respective
Latches on the negative transition
OUT
M
I
OODm ,
L_
I"
1l1 _ _ _ _-+____ 2.4
:
I
of the Enable
V "Preset LSB to LSB Latches and
0.4 V
~--------~--------~--------~~ I
Decrement MSB by one on the negative
transition of the Enable
I
E
I
I
ISYSTEM .2)
I
I
L _ t . - - , + L-........~Ii"".._ - 1
1 +
SE
PULSES
I
I
I
I
I
I
SE
PULSES
1-,
I
I •• I
I
I
I
I
I
I
+
L-.....i
I
I
I
SE
PULSES
I~
I
I
I
(M+,I(L+~.,)
I_I
I
I
I
\+EL
PULSES
I
I
I I
I_I
I • I
I_I
I •• I
I .. I
.
I
I
ALGEBRAIC EXPRESSION
(04 + 1)(03 + 1) ~ 20 E OR
EXTERNAL CLOCK PULSES
output, if enabled, goes LOW during the counter
initialization cycle and reverses state at each time-out.
The counter remains cyclical (is re-initialized at each
time·outl and the individual interrupt flag is set when
time·out occurs. If M = L = "0", the internal counters do
not change, but the output toggles at a rate of 112 the
clock frequency.
LSB = "0", the MSB is unchanged; on the next clock
pulse the LSB is reset to the count in the LSB latches
and the MSB is decremented by 1 (one I. The output, if
enabled, remains LOW during and after initialization and
will remain LOW until the counter MSB is all "Os". The
output will go HIGH at the beginning of the next clock
pulse. The output remains HIGH until both the LSB and
MSB of the counter are all "Os". At the beginning of· the
next clock pulse the defined time-out (TOI will occur and
the output will go LOW. In the normal 16-bit mode
the period of the output of the example in Figure 1
would span 1546 clock pulses as opposed to the
20 clock pulses using the dual 8-bit mode.
The discussion of the continous mode has assumed that
the application requires an output signal. It should be
noted that the timer operates in the same manner with
the output disabled I CRX7 = "0"1. A read timer counter
command is valid regardless of the state of CRX7.
The counter is enabled by an absence of a timer reset
condition and a logic "0" at the Gate input. The counter
will then decrement on the first clock signal recognized
during or after the counter initialization cycle. It
continues to decrement on each clock signal so long as
G remains LOW and no reset condition exists. A
counter time·out (the first clock after all counter
bits = "0" I results in the individual interrupt flag being
set and re·initialization of the counter.
Single-Shot Timer Mode
This mode is identical to the continuous mode with three
exceptions. The first of these is obvious from the
name - the output returns to a LOW level after the
initial time-out and remains LOW until another counter
initialization cycle occurs. The waveforms available are
shown in Table 6.
As indicated in Table 6, the internal counting mechanism
remains cyclical in the Single-shot mode. Each time-out
of the counter results in the setting of an individual
interrupt flag and re-initialization of the.counter.
A special condition exists for the dual 8-bit mode
I CRX2 = "1" I if L = "0". In this case, the counter will
revert to a mode similar to the single 16-bit mode,
except time-out occurs after M + 1 clock pulses. The
5·123
•
F6840/F68A40/F68B40
Table 6
Single-Shot Operating Modes, (CRX3
Control Register
= "0",
CRX7
= "1",
CRXs
= "1")
Initialization/Output Waveforms
CRX2
CRX4
Counter Initialization
0
0
G! +
W
+R
Timer Output .(OX)
rt" "~=t" ",ml
r(N)(T)
0
1
G! +
R
1
0
G! +
W
~
I
r'·". ""'1=" '",.·""'l
TO
to
+R
TO
i(L)(T)
1
1
G! +
R
to
! lTO
TO
Symbols are as defined in Table 5
Time Interval Modes
The time interval modes are provided for those
applications which require more flexibility of interrupt
generation and counter initialization. Individual interrupt
flags are set in these modes as a function of both
counter time-out and transitions of the Gate input.
Counter initialization is also affected by interrupt
flag status.
The second major difference between the single-shot
and continuous modes is that the internal counter
enable is not dependent on the Gate input level
remaining in the LOW state for the single-shot mode.
Another special condition is introduced in the singleshot mode. If L = M = "0" (Dual B-bit) or N = "0" (Single
16-biti, the output goes LOW on the first clock received
during or after counter initialization. The output remains
LOW until the operating mode is changed or non-"O"
data is written into the counter latches. Time-outs
continue to occur at the end of each clock period.
The output signal is not defined in any of these modes,
but the counter does operate in either single 16-bit or
dual B-bit modes as programmed by CRX2. Other
features of the time interval modes are outlined
in Table 7.
The three differences between single-shot and
continuous timer modes can be summarized as
attributes of the single-shot mode:
If CRXs = "0", as shown in Table 7 and Table 8, an
interrupt is generated if the Gate input returns LOW prior to
a time-out. If counter time-out occurs first, the counter
is recycled and continues to decrement. A bit is set
within the timer on the initial time-out which precludes
further individual interrupt generation until a new
counter initiafization cycle has been completed. When
this internal bit is set, a negative transition of the Gate
input starts a new counter initialization cycle. (The
condition of GJ· T· TO is satisfied, since a time-out has
occurred and no individual interrupt has
been generated.)
1. Output is enabled for only one pulse until it is reinitialized.
2. Counter Enable is independent of Gate.
3. L = M = "0" or N = "0" disables output.
Aside from these differences, the two modes
are identical.
Frequency Comparison or Period Measurement Mode
(CRX3 = "1", CRX4 = "0")
The frequency comparison mode with CRXs = "1" is
straightforward. If time-out occurs prior to the first
negative transition of the Gate input after a counter
initialization cycle, an individual interrupt flag is set.
The counter is disabled, and a counter initialization
cycle cannot begin until the interrupt flag is cleared
and a negative transition on G is detected.
Any of the timers within the PTM may be programmed
to compare the period of a pulse (giving the frequency
after calculations) at the Gate input with the time period
required for counter time-out. A negative transition of
the Gate input enables the counter and starts.a counter
5·124
F6840/F68A40/F68B40
Table 7 Timer Interval Modes, CRX3 = "1"
CRX4
CRXs
Application
Condition for Se"lng Individual Interrupt Flag
0
0
Frequency Comparison
Interrupt Generated if Gate Input Period (1/F) is less than
Counter Time-Out (TO)
0
1
Frequency Comparison
Interrupt Generated if Gate Input Period (1/F) is greater than
Counter Time-Out (TO)
1
0
Pulse Width Comparison
Interrupt Generated if Gate Input "Down Time" is less than
Counter Time-Out (TO)
1
1
Pulse Width Comparison
Interrupt Generated if Gate Input "Down Time" is greater thEm
Counter Time-Out (TO)
Table 8
Frequency Comparison Mode, CRX3 = "1", CRX4
Control Register
Bit 5 (CRXs)
= "0"
Counter
Initialization
Counter Enable
Flip-Flop Set (CE)
Counter Enable
Flip-Flop Reset (CE)
Interrupt Flag
Set (1)
0
GI • T· (CE + TO • CE) + R
GI· W· R· I
W+R+I
GI Before TO
1
GI· 1+ R
GI· W· R· I
W+R+I
TO Before GI
-I represents the interrupt for a given timer.
Table 9
Pulse Width Comparison Mode, CRX3 = "1", CRX4 = "1"
Control Register
Bit 5 (CRXs)
Counter
Initialization
Counter Enable
Flip-Flop Set (CE)
Counter Enable
Flip-Flop Reset (CE)
Interrupt Flag
Set (I)
0
GI· I + R
GI· W· R·I
W+R+I+G
Gt
1
GI· 1+ R
GI· W·'R·I
W+R+I+G
TO Before
Before TO
Gt
G = Level sensitive recognition of Gate Input
initialization cycle - provided that other conditions as
noted in Table 8 are satisfied. The counter decrements
on each clock signal recognized during or after counter
initialization until an interrupt is generated, a write timer
latches command is issued,. or a Timer Reset condition
occurs. It can be seen from Table 8 that an interrupt
condition will be generated if CRXs = "0" and the period
of the pulse (single pulse or separately measured
repetitive pulses) at the Gate input is less than the
counter time-out period. If CRXs = "1", an interrupt is
generated if the reverse is true.
Pulse Width Comparison Mode
(CRX3 = "1", CRX4 = "1")
This mode is similar to the frequency comparison mode
except that a positive, rather than negative, transition of
the Gate input terminates the counf With CRXs = "0", an
individual interru~ flag will be generated if the "0" level
pulse applied to the Gate input is less than the time
period required for counter time-out. With CRXs = "1",
the interrupt is generated when the reverse condition
is true.
As can be seen in Table 9, a positive transition of the
Gate input disables the counter. With CRXs = "0", -it is
therefore possible to obtain directly the width of any
pulse causing an interrupt. Similar data for other time
interval modes and conditions can be obtained, if two
sections of the PTM are dedicated to the purpose.
Assume now with CRXs = "1" that a counter initialization
has occurred and that the Gate input has returned LOW
prior to counter time out. Since there is no individual
interrupt flag generated, this automatically starts a new
counter initialization cycle. The process will continue
with frequency comparison being performed on each
Gate input cycle until the mode is changed, or a cycle
is determined to be above the predetermined limit.
5·125
•
F6840/F68A40/F68B40
Absolute Maximum Ratings
Supply Voltage
Input Voltage
Operating Temperature Range - TL to TH
F6840P,S/F68A40P,S/F68B40P,S
Fa840CP,CS/F68A40CP,CS
F68400L
F68400M
Storage Temperature Range
Thermal Resistance
Plastic Package
Ceramic Package
-0.3 V, +7.0 V
-0.3 V, +7.0 V
. 0° C, +70° C
-40° C, +85° C
-55° C, +85° C
-55° C, +125° C
-55° C, +150° C
115° C/W
60°C/W
Stresses greater than those listed under "Absolute Maximum Ratings"
may cause permanent damage to the device. This is a stress rating only and
functiona:l operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
DC Characteristics Vee = 5.0 V ±S%, Vss = 0, TA = TL to TH, unless otherwise noted.
Symbol
Signal
Characteristic
Min
VIH
Input HIGH Voltage
2.0
VIL
Input LOW Voltage
-0.4
liN
I nput Leakage Current
ITsl
3-State (OFF State)
Input Current
00-07
VOH
Output HIGH Voltage
DO-07
Other Outputs
VOL
Output LOW Voltage
Typ
Output Leakage Current
(OFF State)
Po
Power Dissipation
CIN
Input Capacitance
COUT
Output Capacitance
V
1.0
2.5
p.A
VIN = 0 to 5.25 V
2.0
10
p.A
VIN = 0.4 to 2.4 V
V
ILoad = -205 p.A,
ILoad = 200 p.A
0.4
0.4
V
ILoad = 1.6 rnA,
ILoad = 3.2 rnA
1.0
10
p.A
VOH = 2.4 V
470
700
mW
DO-07
00-D7
All Other Inputs
12.5
7.5
01,02,03
10
IRQ
5.0
5·126
Test Condition
0.8
2.4
2.4
IIRQI
Unit
V
01-03, IRQ
ILOH
Max
VIN = 0, TA = 25°C,
f = 1.0 MHz
pF
VIN = 0, TA = 25°C,
f = 1.0 MHz
pF
F6840/F68A40/F68B40
Bus Timing Characteristics
Read (Figure 2)
Characteristic
F68B40
F68A40
F6840
Symbol
Min
Max
Min
Max
Min
Max
Unit
0.5
10
Jls
0.22
4.5
Jls
tcycE
Enable Cycle Time
1.0
10
0.666
10
PWEH
Enable Pulse Width, HIGH
0.45
4.5
0.280
4.5
PWEL
Enable Pulse Width, LOW
0.43
0.280
0.21
Jls
tAS
Set-up Time, Address and R/W
valid to enable positive transition
160
140
70
ns
ns
tOOR
Data Delay Time
tH
Data Hold Time
10
10
10
ns
tAH
Address Hold Time
10
10
10
ns
tEr, tEl
Rise and Fall Time for Enable input
180
220
320
25
25
ns
0.50
10
Jls
0.22
4.5
Jls
25
Write (Figure 3)
tcycE
Enable Cycle Time
1.0
10
0.666
10
PWEH
Enable Pulse Width, HIGH
0.45
4.5
0.280
4.5
PWEL
Enable Pulse Width, LOW
0.43
0.280
0.21
Jls
tAS
Set-up Time, Address and R/W
valid to enable positive transition
160
140
70
ns
tosw
Data Set-up Time
195
80
60
ns
tH
Data Hold Time
10
10
10
ns
tAH
Address Hold Time
10
10
10
ns
tEr, tEl
Rise and Fall Time for Enable input
Fig.2
25
25
Fig.3
Bus Read Timing Characteristics
(Read Information from PTM)
25
ns
Bus Write Timing Characteristics
(Write Information into PTM)
1+----Ic"'E---~
RS,C:S.RiW
DATA BUS
5·127
II
F6840/F68A40/F68B40
AC Characteristics (Figures 4- 8)
F68A40
F6840
Characteristic
Symbol
Min
Max
Min
Max
F68B40
Min
Max
Unit
tr, Ii
Input Rise and Fall Times
C,G and RESET
PWL
Input Pulse Width LOW
C,G and RESET
tcycE
+tsu
+thd
tcycE
+tsu
+thd
tcycE
+tsu
+thd
ns
PWH
Input Pulse Width HIGH
C,G
tcycE
+tsu
+thd
tcycE
+tsu
+thd
tcycE
+tsu
+thd
ns
tsu
Input Set-up Time
(Synchronous Model
C,G and RESET
C3 (+8 Prescaler Mode onlYI
200
120
75
ns
thd
Input Hold Time
(Synchronous Model
C,G and RESET
C3 (+8 Pres caler Mode only I
50
50
50
ns
Output Delay, 01-03
(VOH = 2.4 V, Load BI
(VOH = 2.4 V, Load D)
(VOH = 0.7 Vee, Load D)
TTL
MOS
CMOS
tco
tcm
tcmos
Interrupt Release Time
tlR
" tr
and tf :5 1
Fig. 4
x Pulse Width or
Fig. 7
340
340
1.0
ns
ns
IJs
1.2
0.9
0.7
IJS
Output Delay
\
teo, fcm, tcmos
0,-0.
Input Pulse Width High
Ci.e;
Fig. 8 fiiiQ Release Time
0,-0,
PWH
Fig. 6
460
450
1.35
'--1'"
PWL
a.-a.
mET
Flg.S
700
450
2.0
1.0 P.s, whichever is smaller.
Input Pulse Width Low
c,--e;
0.500" IJs
0.666"
1.0"
'1:-")
Input Set-up and Hold Times
. , 2 . 4Y
fRO
5-128
F6840/F68A40/F68B40
Fig.9
Ordering Information
Bus Timing Test Loads
Load A
(00.0 ,)
5.0 V
Speed
Order Code
Temperature Range
1.0 MHz
F6840P,S
F6840CP,CS
F6840DL
F6840DM
O°C
-40° C
-55° C
-55°C
1.5 MHz
F68A40P,S
F68A40CP,CS
O°C to +70°C
-40° C to +85° C
2.0 MHz
F68B40P,S
Rl = 2.5 k
TEST POINT
----Ip-......-K~-..
130 pF
P
vcc OF DEVICE UNOER TEST
AL=1.25k
IN914
OR EOUIV.
-4_.....-~
40 pF
11.7 k
Load C
(iRQ Only)
5.0 V
t
3k
TESTPOINT~
100pF
I
Load 0
(CMOS Load)
TEST POINT
Plaslic package. S
~
O°C to +70°C
Ceramic package
•
Load B
(0,,0,,03)
TEST POINT
~
to +70°C
to +85° C
to +85°C
to +125°C
1
1
30PF
·5·129
F6840/F68A40/~68B40
5-130
F6844
Direct Memory Access
Controller
Microprocessor Product
Description
Connection Diagram
40·Pin DIP
The F6844 Direct Memory Access Controller (DMAC)
transfers data directly between memory and peripheral
device controllers. In bus·organized systems, such as
those based on the F6800 microprocessor, the DMAC,
rather than the MPU, controls the address and
data buses.
Vss
liE!
CSIT.AKB
RIW
DORNT
!maT
InIml
T.AKA
The DMAC bus interface includes select, read/write,
interrupt, transfer request/grant, and bus interface logic
to permit data transfer over an 8·bit bidirectional data
bus. The F6844 functional configuration is programmed
through the data bus. The internal structure provides for
control and handling of four individual channels, each of
which is separately configured. Programmable control
registers provide control for the transfer location and
length, individual channel control and transfer mode
configuration, priority of servicing, data chaining, and
interrupt control. Status and control lines serve the
peripheral controllers.
TiSTIi
1IR!/1!EIill!
TxROO
TxR01
T.RO.
TxRC3
Do
0,
D.
03
D.
Os
The mode of transfer for each channel can be
programmed as cycle·stealing or burst transfer.
0,
0,
(Top View)
Typical applications include use with the F6856
Synchronous Protocol Communications Controller, the
F6854 Advanced Data Link Controller, and the F68488
IEEE·488 Bus Controller.
•
•
•
•
•
•
•
F6844 Signal Functions
-
Four DMA Channels, Each Having a 16·Bit Address
Register and a 16·Bit Byte Count Register
2M Byte/Sec Maximum Data Transfer Rate
Selection of Fixed or Rotating Priority Service Control
Separate Control Bits for Each Channel
Data Chain Function
Address Increment or Decrement Update
Programmable Interrupts and DMA End to Peripheral
Controllers
Ao
A,
CSIT.AKB
DORNT
DROH
A.
ADDRESS
A,
DROT
A.
IRO/DEND
A.
A.
A,
RES
A.
TxAKA
A.
T'ROo
TxRO,
E
RtW
A10
All
A,.
A13
TxRQ2
F6844
TxRQ3
T.mi
A,.
A,.
DO
VDO
0,
v.s
D.
DATA
03
D.
Os
D.
D,
5·131
•
F6844
Functional Description
(DEN D) signal is directed to the peripheral controller and
an interrupt request (IRQ) goes to the MPU. The interrupt
control register enables these interrupts; the IRQ/DEND
flag bit is read from this register.
The DMAC has 15 addressable. registers, of which eight
are 16 bits in length (see Figure 1). Each channel has a
separate address register and a byte count register, each
of which is 16 bits. There are four channel control
registers with three common general control registers
(priority, Interrupt, and data chain).
Chaining of data transfers is controlled by the data chain
register. Whenenabled,the contents of the address and
byte count registers for channel 3 are put into the
registers of the channel selected for chaining as its byte
count register becomes zero. This allows for repetitively
reading or writing a block of memory.
To prepare a channel for direct memory access (DMA),
the address registers must be loaded with the starting
memory address and the byte count register loaded with
the number of bytes to be transferred. The bits in the
channel control register establish the direction of the
transfer, the mode, and the address Increment or
decrement after each cycle. Each channel can be set for
one of three transfer modes: three-state control (TSC)
steal, halt steal, or halt burst. Two read-only status bits
in the channel control register indicate when the channel
is busy transferring data and when the DMA transfer
is complete.
During the DMA mode, the DMAC controls the address
bus and data bus for the system as well as provides the
R/W line and a signal to be used as valid memory
address (VMA). When a peripheral device controller
desires a DMA transfer, it issues a transfer request.
Assuming this request is enabled and meets the test of
highest priority, the DMAC issues a DMA request. When
the DMACreceives the DMA grant (DGRNn input, it
gives a transfer acknowledge (TxAKA or TxAKB) to the
peripheral device controller, at which time the data is
transferred. When the channel byte count register equals
zero, the transfer is complete, a DEND is given to the
peripheral device controller, and an IRQ is given
to the MPU.
The priority control register enables the transfer requests
from the peripheral controllers and establishes either a
fixed priority or rotating priority scheme of servicing
these requests. When the DMA transfer for a channel is
complete (the byte count register is'zero), a DMA end
5·132
F6844
Fig. 1 Block Diagram
RIW
3
csrr. AK8 2
Ao
4
A,
5
A.
8
A2
7
Ao
Ao
lie
8
9
10
A7
11
lie
lie A,. Au A12 A13 A,. A,.
12
13
14
15
18
17
18
19
iIillIl5!Im
33
_---+-........
0.28
0,27
0.28
0.25
0.24
D.23
CHANNEL CONTROL
REGISTERS
flO
0.22
0721
32T.RQo
31 T.RQ,
DiiliH 38
mmT37
DGRNT38
RES 39
E40
PRIORITY CONTROL
REGISTER
REQUEST,
GRANT,
TIMING
CONTROL
TRANSFER
REQUESTI
ACKNOW·
~-----------~ LEDGE
29 T.RQ.
35 TxAKA
Vss=PIN 1
VDD=PIN 20
5·133
F6844
Signal Descriptions
The F6844 input and output signals are described
in Table 1.
Table 1
F6844 Signal Functions
Mnemonic
Pin No.
Name
Description
Address
Ao-A4
4-8
Address
In the MPU mode, the signals are high-impedance inputs used
to address the DMAC registers. In the DMA mode, these
outputs are set to the contents of the address register for the
channel being processed.
A5-A 15
9:-19
Address
These output lines are in the high-impedance state during the
MPU mode. In the DMA mode, these lines are outputs that are
set to the contents of the address register for the channel
being processed.
28-21
Bidirectional Data
the eight bidirectional lines provide data transfer between the
. DMACand the MPU. The data bus output drivers are three-state
devices that remain in the high-impedance state except when
the MPU performs DMAC read operations.
I
Data
00-0 7
Control
CS/TxAKB
2
Chip Selectl
Transfer
Acknowledge B
This !lignal is an output in the four-channel mode during the
DMA transfer. At all oth.er times, it is a high-impedance, TTLcompatible input used to address the DMAC. The DMAC is
selected when CS/TxAKB is low. Valid memory address (VMA)
must be used·in generating this input to prevent false selects.
Transfers of data to and from the DMAC are then confrolled by
the E, read/write, and Ao-A4 address lines. In the four-channel
mode, when TxAKB is needed, the CS gate must have an opencollector output (a pull-up resistor should not be used). In the
two-channel mode, CS/TxAKS is always an input.
DGRNT
38
DMA Grant
A high-impedance input signal to the DMAC, providing control
of the system buses. In the three-state control (TSC) steal
mode, the signal comes from the system clock drive circuit
(DMA grant), indicating that the clock is being stretched. For
the halt steal or halt burst mode, this signal is the bus available
(SA) from the MPU, indicating that the MPU has halted and
transferred control of its buses to the DMAC. For a design
involving TSC steal and halt mode transfers, this input must be
the logical OR of the clock-driven DMA grant and the MPU BA.
DRQH
36
DMA Request
Halt Steal
This active-lOW output requests a DMA transfer for a channel
programmed for the halt steal or halt burst transfer mode. The
signal is connected directly to the MPU HALT input and
remains low until the last byte transfer has begun.
5-134
F6844
Table 1
F6844 Signal Functions (Cont.)
Mnemonic
E
R/W
Pin No.
Name
Description
37
DMA Request
Three-State
Control Steal
This active-low output requests a DMA transfer for a channel
configured for the TSC steal transfer mode. The signal is
connected to the system clock driver, requesting a <1>1 clock
stretch. It remains in the low state until the transfer has begun.
40
Direct Memory
Access
The DMAC register I/O transfers, channel request line sampling,
and gating of other control signals to the system are done
internally in conjunction with the E high-impedance input.
This input must be the system memory clock (a nonstretched
E clock).
33
Interrupt Request/
DMA End
A TIL-compatible, active-low output used to interrupt the MPU
and to signal the peripheral controller that the data block
transfer has ended. If the interrupt has been enabled, the
IRQ/DEND line goes low after the last DMA cycle of a transfer.
An open-collector gate must be connected to DGRNT and
IRQ/DEND to prevent false interrupts from the DEND signal
when interrupts are not enabled.
39
Reset
The ~ input resets the DMAC from an external source. In the
low state, the RES input causes all registers, except address
and byte count, to be reset to the logic 0 state. This disables all
transfer requests, masks all interrupts, disables the data chain
function, and puts each channel control register into the
condition of memory write, halt steal transfer mode, and
address increment.
3
Read/Write
A TIL-compatible signal that is a high-impedance input in the
MPU mode and an output in the DMA mode.
In the MPU mode, it controls the direction of data flow through
the DMAC input/output data bus interface. When read/write is
high (MPU read cycle) and the chip is selected, DMAC data
output buffers are turned on and a selected register is read.
When it is low, the DMAC output drivers are turned off and the
MPU writes into a selected register.
In the DMA mode, read/write is an output to drive the memory
and peripheral controllers. Its state is determined by bit 0 of the
channel control register for the channel being serviced. When
read/write is high, the memory Is written into the peripheral
controller. When it is low, the peripheral controller is read and
its data stored in the memory.
In the DMA mode, the DMAC data buffers are off, so data is not
available on the data bus (Do-D7)'
5-135
•
F6844
Table 1
F6844 Signal Functions (Cont )
Mnemonic
TxAKA
TxRQo-TxRQ3
Pin No.
35
32-29
Description
Name
Transfer
Acknowledge A
This signal is a TIL·compatible output used in conjunction with
the CS/TxAKB line to select the channel to be strobed for
transfer, and to give the DMA end signal. In the two·channel
mode, only TxAKA Is used to select channel 0 or 1, and
CSlTxAKB is always an input.
Transfer Request
Each of the four channels has its own hlgh·impedance input
request for transfer line. The peripheral controller requests a
transfer by setting its TxRQ line high (a logic 1). The lines are
sampled according to the priority and enabling established in
the priority control register.
In the. halt staal mode, and the first byte of the halt burst mode,
the TxRQ signals are tested on the positive edge of E and the
highest priority channel is strobed. Once strobed, the TxRQs are
not tested again until that channel's data transfer is finished.
In the succeeding bytes of the halt burst mode transfer, the
TxRQ Is tested on the negative edge of E, and data is
transferred on the next E cycle if the TxRQ signal is high.
TxSTB
34
Transfer Strobe
This output signal is an acknowledgement to the peripheral
controller, and controls transfer of data to or from memory. The
tran.sfer strobe is also used as the VMA signal in the
DMA mode.
In a one-channel system, TxSTB can be inverted and run to the
peripheral controller acknowledge input. In a two· or four·
channel system, TxSTB enables the depode of TxAKA and
CSlTxAKB to select the device controller to be acknowledged.
Power
Voo
20
Vss
1
Power Supply
Nominal +5 Vdc
Ground
Common power and signal return
5·136
F6844
Bit 3, Address UplDown- Bit 3 controls the change in
the address register for each DMA cycle. If this bit is
low, the address register is incremented each time the
byte count register decrements. If the bit Is high, the
address register is decremented.
DMAC Register Descriptions
The 15 registers in the DMAC are read/write registers,
although some of the bits are read-only status bits.
Address Registers
Each channel has its own individual 16-bit address
register. Before a DMA transfer Is begun, the starting
address for the transfer must be loaded into the address
register. Depending on the state of bit 3 of the channel
control register, the address register Is decremented or
incremented after each byte transfer.
Bit 8, Busy/Ready Flag-The busy/ready flag is a readonly status bit that indicates a DMA transfer Is in
process on that channel. This bit goes high at the
beginning of the transfer and remains high until the
IRQ/DEND has been low for one cycle (DMA end). The bit
is then reset and the channel can again be configured for
transfer.
Byte Count Registers
Each channel also has its own byte count register.
Before the DMA transfer, this register must be loaded
with the number of bytes to be transferred. Since it is 16
bits in length, the transfer can be up to 65,536 bytes of
data. The byte count register is decremented at the
beginning of each DMA cycle.
Bit 7 DMA End (DEND) Flag- The DEND bit indicates
that a DMA block transfer has ended. This bit Is set at
the same time the busy/ready flag is reset. The DEND bit
is reset by the MPU reading the channel control.register.
This bit causes an interrupt if enabled In the Interrupt
control register.
Channel Control Registers
The control of each channel's DMA transfer is
programmed into its channel control register. Bits 4 and
5 are unused.
Priority Control Register
The priority control register establishes priority and
enables the transfer requests. Bits 4, 5, and 6
are unused.
Bit 0, ReadlWrlte (RIW)- The direction of the DMA
transfer is controlled by this bit. When It Is high, the
peripheral controller reads the memory. When it is low,
the transfer is in the opposite direction, thus writing into
the memory. The system RlW line is in the same state as
this RIW bit in the DMA mode. The device controller
must change the sense of its RiW input during the
DMA mode.
Bits 0-3, Request Enable (REo_3) - The four channels are
individually enabled by setting the respective RE bit high.
A low on any of these bits disables recognition of the
transfer request for that channel. The bit number
represents the channel number; e.g., bit 2 is channel 2.
Bit 7, Rotate Control- The DMAC priority service routine
is selected by this rotate control bit. When it is low, the
fixed mode Is selected. Channel 0 has the highest
priority, channel 1 the next highest, etc. When this bit is
high, a rotating routine is used: initially, It Is the same as
in the fixed mode, but once a channel has been serviced,
it moves to the lowest priority and those that were below
It advance to the next higher priority.
Bit 1, BurstiSteal- This bit, along with bit 2, selects the
mode of the DMA transfer. With bit 1 high, the burst
mode is selected. A low selects the steal mode.
B2, TSC/Halt- This bit helps select the mode of DMA
transfer. When the bit is high, the TSC mode Is selected.
When low, the halt mode is selected. A TSC burst mode
is Illegal for F6800-family processors due to restrictions
on 1 clock stretching for these products.
Interrupt Control Register
An Interrupt Is caused by a channel completing its DMA
block transfer. The DEND (channel control register bit 7)
flags this condition for each channel. Bits 4, 5, and 6
are unused.
The mode selection for bits 1 and 2 is as follows:
Blt2
Bit 1
DMA Transfer Mode
o
o
o
Halt Steal
Halt Burst
TSC Steal
(Illegal)
1
1
1
o
1
Bits 0-3, iRO/DEND Enable (DIEo_3)-Each channel is
separately enabled to cause the interrupt. A high enables
an interrupt from the channel; a low masks the interrupt.
The bit number corresponds to the channel number; e.g.,
bit 2 is channel 2.
0
5-137
F6844
Bit 7, iRO/DEND Flag-This read-only bit Indicates an
IRQ is requested of the MPU when the signal is high_ If
the Interrupt Is enabled (DIE Is a 1) when a channel's
DEND flag (channel control register bit 7) goes high, the
IRQ/DEND flag bit also goes high_ It is reset by the MPU
reading the channel control register that caused
the interrupt.
CS/TxAKB becomes a chip select in the MPU mode and a
transfer acknowledge B in the DMA mode. With bit 3 low,
the two-channel mode is selected, and the CS/TxAKB
line is always a chip select, both for the MPU and the
DMA mode.
Initialization
During a power-on sequence, the DMAC'is reset through
the RES input. All registers, except the address and byte
count, are set to a logic 0 state. This disables all
requests and the data chain function, while masking all
interrupts. The address, byte count, and channel control
registers must be programmed before the respective
transfer request bit is enabled in the priority
control register.
Data Chain Register
Repetitive reading or writing of a block of memory can
be done in the data chain function. A DMA transfer
cannot be active on channel 3 during the data chain. Bits
4 through 7 are unused.
Bit 0, Data Chain Enable (DCE)- The data chain function
Is enabled when this bit is high.
Transfer Modes
Three methods are used for a DMA transfer, determined
by the data transfer rate required, the number of
channels attached, and the hardware complexity
allowable. Refer to Figure 2 (TSC Steal Mode), Figure 3
(Halt Steal Mode), and Figure 4 (Halt Burst Mode) for an
illustration of the three DMA transfer methods.
Bits 1 and 2, Data Chain Channel Select A, B (DCA,
DCB)- The channel updated by data chaining Is selected
by bits 1 and 2 as follows:
DCB Bit2
DCABit1
Channel #I
0
0
1
1
0
1
0
1
0
1
2
(Illegal)
Two of the modes, TSC steal and halt steal, are
accomplished by cycle stealing from the MPU. Cycle
stealing, in the TSC steal mode, is initiated by the DMAC
bringing the DRQT line low. This line goes to the system
clock driver, which returns a high on DGRNT on the
rising edge of the system 1 clock. The DGRNT signal
must cause the address control and data lines ·to go to
the high-impedance state, at wtiich time the DMAC
supplies the address from the address register of the
requesting channel. It also supplies the RIW signal as
determined from the channel control register. After one
byte is transferred, control is restored to the MPU. This
method stretches the 1 and 2 clocks while the DMAC
uses the memory (see Figure 5).
The data chain function is performed by transferring the
contents of channel 3 address and byte count registers
into the respective registers of the. channel selected by
bits 1 and 2. The transfer occurs during the cycle of E
following the byte count register having decremented
to zero.
Bit 3, Two/Four Channel Select (2/4)- Bit 3 configures
the DMAC to handle two or four channels. When high,
this bit selects the four-channel mode, in which the
5-138
F6844
Fig. 2
TSC Steal Mode Timing
E MPU
TxRQ
_ _miil.'il.iJii.tmV
•
DGANT _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- J
TxAKA
TxAKB
Ao·A1S.
RJ\jj-----------------\..~------~>---------------------
Ao.A4.RftN_~~_ _ _ __l~______~--_t------r_-~'----~~------L~----~~
5·139
F6844
Fig. 3
Halt Steal Mode Timing
E DMA
~~~
TxAQ
DGANT
/
TxAKA
\
TxAKB
,.
X
X
X
X
X
X
/
\
\
/
\
5·140
... _-- ~/
X
X
X
X
\ ... _-----------
F6844
Fig. 4
Halt Burst Mode Timing
TxRQ
DGRNT
TxAKA
------'---+----+---+----+---"---
TxAKB
A
Ao- 15,RtW
Ao·A•• RJW
-------------------1c===lx===t===j::>--------===============}---1~-'---+----t-----1-----~C===
The second mode employing cycle stealing is the halt
steal mode. This method actually halts the MPU instead
of stretching the rJ>1 clock for the transfer period. This
mode Is initiated by the DMAC bringing the DRQH line
low. This line connects to the MPU HAIT input. The MPU
bus available (BA) line is the DGRNT input to the DMAC.
While the MPU is halted, its address bus, data bus, and
RlW lines are In the high-Impedance state. The DMAC
supplies the address and Rm line. After one byte is
transferred, the HALT line Is returned high and the MPU
regains control. In this mode, the MPU stops internal
activity and is removed from the system while the DMAC
uses the memory.
The third mode of transfer Is the halt burst. This mode is
similar to the halt steal mode, except that the transfer
does not stop with one byte. The MPU is halted while an
entire block of data is transferred. When the channel
byte count register equals zero, the transfer IS complete
and control Is returned to the MPU. This mode gives the
highest data transfer rate, at the expense of the MPU
being Inactive during the transfer period.
5-141
_.
_.- . -
----~.
•
F6844
Fig. 5
Flowchart of DMAC Operation
WAIT FOR
TxRQ INPUT
CHECKEDES
WAIT FOR r-~----I
TxRQ
INPUT
BURST
MODE
5·142
F6844
DMAC Programming Model
The following programming model outlines channel
preparation for DMA transfer, request enabling, data
chain register programming, and register descriptions
(see Table 2).
Table 2
DMAC Programming Model
Register
Address
(Hex)
Register Content
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Channel
Control
1x·
DMA End
(DEND)
Flag
Busy/Ready
Flag
Not
Used
Not
Used
Address
Up/Down
TSCI
Halt
Burstl
Steal
Read/Write
(R/W)
Priority
Control
14
Rotate
Control
Not
Used
Not
Used
Not
Used
Request
Enable #3
(RE 3)
Request
Enable #2
(RE2l
Request
Enable #1
(RE 1)
Request
Enable #0
(REo)
Interrupt
Control
15
IRQIDEND
Flag
Not
Used
Not
Used
Not
Used
IRQ/DEND
Enable #3
(DIE 3l
IRQ/DEND
Enable #2
(DIE2l
IRQ/DEND
Enable #1
(DIE 1)
IRQ/DEND
Enable #0
(OlEo)
Data Chain
16
Not
Used
Not
Used
Not
Used
Not
Used
Two/Four
Channel
Select (214)
Data Chain
Channel
Select B
Data Chain
Channel
Select A
Data Chain
Enable
'The x represents the binary equivalent of the channel desired.
RE o_3
Channel Control Register
Bit 7 - Is set at end of DMA block transfer;
reset by MPU reading the channel
control register.
Bits 0-3-High=enable transfer request for
the channel; low = request disabled.
Interrupt Control Register
Busy/Ready Bit 6- Status bit set when in transfer;
Flag
cleared after DMA end.
IRQIDEND
Flag
Bit 7- This flag is set by DEND in channel
control registers when enabled;
reset by reading the register that
caused it to be set.
Bits 0-3- High = enable IRQ by DEND for
the channel; low= IRQ masked.
Address
UplDown
Bit 3- High = decrement address register
for each byte; low = increment.
DIE O_3
TSC/Halt
Bit 2- High = select TSC mode; low = halt
modes.
Data Chain Register
Bit 1- High = select burst mode;
low = steal modes.
Two/Four
Channel
Bit 3- High = 4-channel mode; low = 2channel.
Bit 0- High = device controller reads
memory; low = write into memory.
Data Chain
Channel
Select
Bits 2, 1- Binary equivalent of channel to
be updated by chaining.
Data Chain
Enable
Bit 0- High = enable data chain function;
low = disabled.
Burst/Steal
Priority Control Register
Rotate
Control
Bit 7 - High = use rotate routine;
low = fixed: 0, 1, 2. 3 priority.
5-143
•
F6844
Preparation of a channel for a DMA transfer requires:
The two B·bit bytes that form the registers in Table.3
are placed in consecutive memory locations, making it
very easy to use the MPU index register in programming
.
them.
1. Load the starting address into the address register.
2. Load the number of bytes into the byte count register.
3. Program the channel control register for the transfer
characteristics: direction (bit 0), mode (bits 1 and 2),
and the address update (bit 3).
Table 3
Address and Byte Count Registers
Register
Channel
Address (Hex)
The channel is now configured. To enable the transfer
request, set the appropriate enable bit (bits 0-3) of the
priority control register, as well as the rotate control bit.
Address High
Address Low
Byte Count High
Byte Count Low
0
0
0
0
1
2
3
If an Interrupt on DEND is desired, the enable bit (bits
0-3) of the Interrupt control register must be set.
Address High
Address Low
Byte Count High
Byte Count Low
1
1
1
1
5
6
7
Address High
Address Low
Byte Count High
Byte Count Low
2
2
2
2
A
B
Address High
Address Low
Byte Count High
Byte Count Low
3
3
3
3
C
D
E
F
If data chaining for the channel Is necessary, It Is
programmed into the data chain register and the
appropriate data must be written into the address and
byte count registers for channel 3.
A comparison of the response times and maximum
transfer rates Is shown below. The values shown are for
a system clock rate of 1 MHz.
Mode
Response Time
(,is)
Maximum
Transfer Rate
(,is/byte)
Halt Burst
Halt Steal
TSC Steal
3.5-15.5'
3.5-15.5'
2.5-3.5
1
5-15'
4
'These values depend upon the cycle In process.
5·144
o.
4
B
9
F6844
System Description
Fig. 6
One-channel Operation
IRQ (OPEN COLLECTOR)
The DMAC hardware configuration is designed for a one-,
two-, or four-channel system.
IRQ, DEND, TxAK Generation
Derivation of the IRQ, DEND, and TxAK signals for one-,
two-, and four-channel DMA is shown in Figures 6, 7, and
8. The IRQ signal, if enabled, is asserted by the DMA to
interrupt the MPU whenever a DMA block transfer is
completed. The TxAK signal is asserted during each
DMA cycle and is used to handshake with a peripheral
controller each time a DMA byte transfer occurs. The
DEND signal is used to handshake with a peripheral
controller each time a DMA block transfer is complete.
DGRNT ~>-I>o-...J
DEND,
T,5TB I--~I>o---+--==-_ T,AKa
TxAKA
Each circuit uses DMA GRANT to demultiplex the
IRQIDEND DMAC output to ensure that the system IRQ
is asserted at the proper time, only during M PU
operation. Whenever DMA GRANT is high, IRQ
is negated.
Fig. 7
NC
ii\Q (OPEN COLLECTOR)
The circuits also generate DEND and TxAK for the proper
channel, gated by TxSTB.
DEND,
DGRNT
IRQIDEND
The one-channel DMA mode requires no channel
decoding, so for this mode TxAK is derived from TxSTB
directly, and TxSTB is used to demultiplex thl? IRQIDEND
output for DEND generation.
DEND,
TxSTB
TxAKo
TxAK1
T,AKA
The two-channel mode circuit is similar to the onechannel circuit but uses TxAKA to identify the active
channel and generate the appropriate channel signal.
Fig. 8
CSrrxAKB
cs
Four-channel System
IRQ (OPEN COLLECTOR)
DGRNT
T,AKA\----4-J
csrhAKB\-_--~
IO--t:)o-......- - - i - - f - - + - T , A K ,
IO--t::)o------
B
ffi
">
!..
~
A
~ ~
DISPLAY PERIOD
::>
L
L
VERTICAL RETRACE PERIOD
TOTAL SCAN LINE ADJUST (Nadj)
5-159
"TI
G
c
Cil
CD
o
a
:J:
o
::l.
~
HORIZONTAL TOTAL (RO)
1 4 t : - - - - - - - - - - - - - -....: ( N h I + l ) X l , - - - - - - - - - - - - - - - - - - - I : 1
Fie -,
ClK
HORIZONTAL DISPLAY (Rl)N.. x t,
HORIZONTAL RETRACE
Ii
:!
3
:r
ra
,
I
I
MAO-MAW
~~~~~~--~--~--~
,
CHARACTER
iI
,
!
0
,,
., Nhd- 1 ,
,
,
~"""'I-N-hd---l .....;--.;---i-~
;-!-N..
,
~
Nh.p
I
-1,
~
Nh,p
~
Nh.
14 HS PULSE WIDTH (R3)-.j
I
I
HORIZONTAl SYNC POSITION (R2)
HS'
,
FRONT PORCH (SYNC DELAy)
I
Nhsw x Ie
I
BACK PORCH (SCAN DELAy)
g
,DISI'ENI
"TI
.,
~~~------,
Nota
Timing is shown for first displayed scan row only. The initial MA is
determined by the contents of start address register R1ZR13. Timing is
shown for R1ZR 13 = O.
"~----~
E
en
F6845
Figure 9 CRTC Vertical Timing
IF
=(Nyt ~~~~ 'fI~:.dl )( t~1
j . - - - - - - - - - - - - - - - - - - V E R T I c A L TOTAL (R4) + VERTICAL TOTAL ADJUST ( R S ) - - - - - - - - - - - - - - - - - . j
VERTICAL R E T R A C E - - - - - - - - - - - - - + i
"I"
RAO·RA4
SINTERL~CJ~--~r-~~~~~~-u----~~-,r---~~r-u----u----~~-,r---~~r-u---~~~~--~~---u~r-'r----u
SVNC AND
vlg~~ ~,~~~ ~1-=-~~~-';I....--~~~~=~-'Ir_~,....~~~..1~,....--'\'_."...,...II-''r_.I\..--..J'-~~....",,,_~.4,,_...III....--+_,...J'-......J\----~
I
MAO·MA13*·
I
I
I
I
(N"'d-1r)(Nhd+~ht
VERTICAL SCAN DELA V
vs I
(Even Field)
I
I
I
DISPL~~
ENABLE
•
I
•i
\
I
I
I
I
I
I
I
I
I
Vs l
(Odd Flold)
I
I
I
i
I
I
,
r-
I
,
i
I
I
.4
i
r- "~1
I
•i
•i
I
~
h.r~~1
•,
•i
*
'">
• Nht must be an odd number for both interlace modes.
··Inltlal MA is determined by Rl21R13 (start address register), which Is zero
in this timing example.
•• oN sl must be an odd number for Interlace sync and
video mode.
Not••:
1. Refer to Figure 2 • The odd field Is offset V. horizontal scan time.
2. Timing values are described In Table 9.
3. Vertical sync pulse width can be programmed from 1 to 16 scan line
times for the MC6645 1.
*
5-161
,
,
F6845
Horizontal Total Register (RO)· This 8·bit write·only register
determines the horizontal sync (HSYNC) frequency by defin·
ing the period in character times. It is the total of the
displayed characters plus the nondisplayed character times
(retrace) minus one.
Horizontal Timing Summary· The difference between RO and
R1 is the horizontal blanking interval (refer to figure 8). This
interval in the horizontal scan period allows the beam to
return (retrace) to the left side of the screen. The retrace
time is determined by the monitor's horizontal scan components. Retrace time is less than the horizontal blanking
interval.
Horizontal Displayed Register (R1)· This 8·bit write-only
register determines the number of displayed characters per
line. Any 8-bit number can be programmed so long as the
contents of RO are greater than the contents of R1.
Horizontal Sync Position Register (R2) ·.This 8-bit write·only
register controls the horizontal sync position, which defines
the horizontal sync delay (Front Porch) and the horizontal
scan delay (Back Porch). When the. programmed value of
this register is increased, the display on the CRT screen is
shifted to the left. When the programmed value is decreased, the display is shifted to the right. Any 8·bit number can
be programmed if the sum of the contents of R1, R2, and
R3 is less than the contents of RO.
Sync Width Register (R3)· This 8-bit write-only register determines the width of the vertical sync pulse and the horizontal sync pulse for the F6845A CRTC. The vertical sync pulse
width is fixed at 16 scan line times for the F6845, and the
upper four bits of this register are treated as "don't cares".
A good rule of thumb is to make the horizontal blanking
about 20% of the total horizontal scanning period for a
CRT. In inexpensive TV receivers, the beam overscans the
display screen so that aging of parts does not result in
underscannlng. Because of this, the retrace time should be
about one-third the horizontal scanning period. The horizontal sync delay, HS pulse width, and horizontal scan delay
are typically programmed with a 1:2:2 ratio.
Vertical Total Register (R4) and Vertical Total Adjust
Register (RS) - The frequency of the VS pulse is determined
by both the R4 and R5 registers. The calculated number of
character line times is usually an integer plus a fraction to
get exactly a 50 or 60 Hz vertical refresh rate. The integer
number of character line times minus one is programmed
in the 7-bit write-only vertical total register (R4). The fraction
of character line times is programmed in the 5·bit write-only
vertical total adjust register (R5) as a number of scan
line times.
The F6845A allows control of the VS pulse width for one to
sixteen scan line times. Programming the upper four bits
for one to fifteen selects pulse widths from one to fifteen
scan line times. Programming the upper four bits as zeros
selects a VS pulse width of 16 scan line times, allowing
compatibility with the F6845.
Vertical Displayed Register (R6) - This 7-~it write-only register
specifies the number of displayed character rows on the
CRT screen and is programmed in character row times. Any
number smaller than the contents of the R4 register can be
programmed into the R6 register.
This horizontal width must be programmed because, were it
fixed as an integral of character times, it would vary with
the character rate and be out of tolerance for certain
monitors.
Vertical Sync Position Register (Rn· This 7-bit write-only
register controls the position of vertical sync with respect
to the reference. It is programmed in character row times.
The value programmed in the register is one less than the
number of computed character line times. When the programmed value of this register is increased, the display
position of the CRT screen is shifted up. When the programmed value is decreased, the display position is shifted
down. Any number equal to or less than the vertical total
(register R4) can be used.
Table 3 Cursor and DE Skew Control
Table 4 Interlace Mode Register
For both the F6845 and the F6845A, the HS pulse width can
be programmed from one to fifteen character clock periods,
thus allowing compatibility with the HS pulse width
specifications of many different monitors. If zero is written
into this register, then no horizontal sync is provided.
Value
00
01
10
11
Skew
No Character Skew
One Character Skew
Two Character Skew
Not Available
5-162
Bit 1
0
1
0
Bit 0
0
0
1
1
1
Mode
Normal Sync Mode (Non-Interlace)
Normal Sync Mode (Non-Interlace)
Interlace Sync Mode
Interlace Sync and Video Mode
F6845
Figure 10 Interlace Control
SCAN LINE ADDRESS
SCAN LINE ADDRESS
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SCAN LINE ADDRESS
0----------------------0
1
0
0
2
-~----3"-
0
--&-----&- 3
4
0<>000
- -& ~ --o---G- -& - 4
5
0
-&
--&-----&- 5
6
0
0
7-~----~-6
--&-----&-7
EVEN
FIELD
(a) NORMAL SYNC
ODD
FIELD
(b) INTERLACE SYNC
Interlace Mode and Skew Register (R8) . The F6845 only
allows control of the interlace modes as programmed by
the low order two bits of this write·only register. The
F6845A controls the interlace modes and allows a program·
mabie delay of zero to two character clock times for the
display enable (DE) and cursor outputs. Table 3 describes
operation of the cursor and DE skew bits. Cursor skew is
controlled by bits 6 and 7 of Register RB, while DE skew is
controlled by bits 4 and 5. Table 4 shows the available in·
terlace modes; these modes are selected using the two low
order bits of this 6·bit write·only register. In the normal sync
mode (non·interlace), only one field is available, as shown in
figures 1 and 10 (a). Each scan line is refreshed at the
VSYNC frequency (e.g., 50 or 60 Hz).
Two interlace modes are available, as shown in figures 2, 10
(b) and 10 (c). The frame time is divided between even and
odd alternating fields. The· horizontal and vertical timing
relationship VSYNC delay.ed by one·half scan line time)
results in the displacement of scan lines in the odd field
with respect to the even field.
In the interlace sync mode, the same information is painted
in both fields, as shown in figure 10 (b). This is a useful
mode for filling in a character to enhance readability.
2
1
--&-----&-2
o
0_-& _ _ _ _ -&_1
4
0
0
--&-----&-3
_~~-O-~~-
o
5
0
--&-----&- 7
--------1
--------3
--------5
--------7
EVEN
ODD
FIELD
FIELD
(e) INTERFACE SYNC AND VIDEO
In addition, the programming of the CRTC registers for
interlace operation has the following restrictions.
F6845 Programming Restrictions
1. The horizontal total register value, RO, must be odd
(i.e., an even number of character times).
2.
For interlace sync and video mode only, the maximumscan line address, R9, must be odd (i.e., an
even number of scan lines).
3.
For interlace sync and video mode only, the vertical
displayed register, R6, must be even. The program·
med number, Nvd, must be one-half the actual
number required. The even-numbered scan lines are
displayed in the even field and the odd-numbered
scan lines are displayed in the odd field.
4.
For interlace sync and video mode only, the cursor
start register, R10, and cursor end register, R11, must
both be even or odd, depending in which field the
cursor is to be displayed.
F6845A Programming Restrictions
1. The horizontal total register value, RO, must be odd
(i.e., an even number of character times).
In the interlace sync and video mode, shown in figure 10 (c),
alternating lines of the character are displayed in the even
field and the odd field. This effectively doubles the given
bandwidth of the CRT monitor.
To avoid an apparent flicker effect, care must be taken
when using either interlace mode. This flicker effect is due
to the doubling of the refresh time for all scan lines, since
each field is displayed alaernately and can be minimized
with proper monitor design (e.g., longer perSistence
phosphors).
2.
For the interlace sync and video mode only, the vertical displayed register, R6, must be even. The pro·
grammed number, Nvd, must be one-half the actual
number required.
Maximum Scan Line Address Register (R9) . This 5-bit write·
only register determines the number of scan lines per
character row, including the spacing, thus control·
ling operation of the row address counter. The programmed
value is a maximum address and is one less than the
number of scan lines.
5·163
•
F6845
Figure 11 Cursor Control
ION
I OFF
I
I
-...:
I
Table 5 Cursor Start Register
I
ON
I
!!t. t.
11
CURSOR START ADR. =9
CURSOR END ADR. = 9
Bit 5
Bit 6
Cursor Display Mode
Non-blink
0
0
1
Cursor Non-clisplay
0
1
Blink, 1116 Field Rate
0
1
1
Blink, 1/32 Field Rate
Example of Cursor DIsplay Mode
:'-BLINK PERIOD=
I
16 OR 32 TIMES
FIELD PERIOD
11
CURSOR START ADR.=9
CURSOR END ADR. = 10
CURSOR START ADR.=1
CURSOR END ADR. = 5
Start Address and Light Pen Registers
Cursor Control Registers-Cursor movement is controlled by
the following four registers.
The following 14·bit registers control the start address and
light pen.
Cursor Start Register (R10) and Cursor End Register
(R11) - These registers allow a cursor of up to 32 scan lines
in height to be placed on any scan line of the character
block, as shown in figure 11. Register R10 Is a 7-bit writeonly register used to define the start scan line and the cursor blink rate. Bits 5 and 6 of the cursor start address
register control the cursor operation, as shown in table 5.
Non-clisplay, display, and two blink modes (16 times or 32
times the field period) are available. Register R11 is a 5·bit
write-only reglsterthat defines the last scan line of the
cursor.
Start Address Register (R12·H. R13-L) - This 14·bit writeonly register pair controls the first address by the CRTC
after vertical blanking. It consists of an 8-blt low order
(MAO - MA7) register and a 6·bit high order (MAs - MA13)
register. The start address register determines which portion of the refresh RAM is displayed on the' CRT screen.
Because the CRTC linear address generator counts from
this beginning count, the displayed portion of the screen
may be a window on any continuous string of characters
within a 16 block of refresh memory. Hardware scrOlling by
characters, line, or page can be accomplished by centering
the R121R13 pointer in the middle of the available
memory space.
Bit 5 is the blink timing control; when it is low, the blink
frequency Is 1/16 of the vertical field rate, and when It is
high, the blink frequency is 1132 of the vertical field rate. Bit
6 is used to enable a blink The cursor start scan line Is set
by the lower five bits.
Light Pen Register (R16-H, R17·L)· This 14-bit read-only
register pair captures the refresh address output by the
CRTC on the positive edge of a pulse input to the LPSTB
pin. It consists of an 8-blt low order (MAo-M~) register and
a 6·blt high order (MAo-MA1:Y register. Since the light pen
pulse is aynchronous with respect to refresh· address tim·
ing, an internal synchronizer is designed into the CRTC.
Due to delays in this circuit, the value of R16 and R17 need
to be corrected in software. (See the bus timing diagram in
the Timing Characteristics section). Figure 12 shows an
interrupt-driven approach, although a polling routine could
be'used.
When an external blink feature on characters is required, it
may be necessary to perform cursor blink externally so that
both blink rates are synchronized. Note that an Invertinonlnvert cursor is easily implemented by programming
the CRTC for a blinking cursor and externally Inverting the
video signal with an excluslve-OR gate.
Cursor Register (R14-H, R15-L) - This 14-blt readlwrite
register pair is programmed to position the cursor anywhere
in the refresh RAM area, thus allowing hardware paging and
scrolling through memory without loss of the original cursor position. It consists of an 8-bit low order (MAo - MA7)
register and a 6-blt high order (MAs - MA1:Y register.
5-164
F6845
Figure 12 Light Pen Interface
MPU
CRTC
LIGHT PEN
CRTC Initialization
The bus timing test load is shown in figure 16; figure 17 illustrates the CRTC timing, and figure 18 illustrates the
CRTC clock, memory addressing, and light pen timing. All
signal timing characteristics are given in the "Timing
Characteristics" section of this data sheet.
Registers RO-R15 must be initialized after the system power
is turned on. The processor normally loads the CRTC
register file sequentially from a firmware table, after which,
in most systems, RO-R11 are not changed. The worksheet
of table 6 is useful in computing proper register values for
the CRTC. Table 6 shows the worksheet completed for an
80 x 24 configuration using a 7 x 9 character generator,
and figure 13 shows an F6800 program that could be used
to program the CRT controller. The programmed values
allow use of either an F6845 or an F6845A CRTC.
Additional CRTC Applications
The foremost system function that can be performed by the
CRTC is the refreshing of dynamic RAM. This is quite
simple, as the refresh addresses run continually.
Note that the LPSTB input signal can be used to support
additional system function other than a light pen. A digitalto-analog converter (DAC) and comparator could be configured to use the refresh addresses as a reference to a
DAC composed of a resistive adder network connected to a
comparator. The output of the comparator generates the
LPSTB input signal, signifying a match between the refresh
address analog level and the unknown voltage.
The CRTC registers have an initial value at power up. When
using a direct drive monitor (without horizontal oscillator),
these initial values can result in out-of-tolerance operation.
The CTRC programming should be done immediately after
power up, especially in this type of system.
CRT Interface Signal Timing
Timing charts of CRT interface signals are illustrated with
the aid of a programmed example of the CRTC. When
values listed in table 7 are programmed into the CRTC control registers, the device provides the outputs as shown in
the timing diagrams (figure 8, 9, 14, and 15). The screen format of this example is shown in figure 7, which illustrates
the relation between refresh memory address (MAQ-MA13),
row address (RAQ-RA4), and the position on the screen. In
this example, the start address is assumed to be zero.
The light pen strobe input could also be used asa
character strobe to allow the. CRTC refresh addresses to
decode a keyboard matrix. Debouncing would need to be
done in software.
Both the VS and HS signal outputs can be used as a realtime clock. Once programmed, the CRTC provides a stable
reference frequency.
5-165
II
F6845
Table 6 Worksheet for 80 x 24 Formal
Display Formal Worksheet
I. Displayed Characters per Row
2. Displayed Character Rows per Screen
3. Character Matrix a. Columns
b.Rows
4. Character Block a. Columns
b.Rows
5. Frame Refresh Rate
6. Horizontal Oscillator Frequency
7. Active Scan Lines (Line 2 x Line 4b)
8. Total Scan Lines (Line 6 + Line 5)
9. Total Rows Per Screen (Line 8 + Line 4b)
10. Vertical Sync Delay (Character Rows)
11. Vertical Sync Width (Scan Lines, 16)
12. Horizontal Sync Delay (Character Times)
13. Horizontal Sync Width (Character Times)
14. Horizontal Scan Delay (Character Times)
15. Totai Character Times (Lines 1 + 12 + 13 + 14)
16. Character Rate (Line 6 times 15)
17. Dot Clock Rate (Line 4a times 16)
80
24
7
9
9
11
60
16,600
264
310
28
16
6
9
7
102
1.8972 M
17.075 M
Char.
Rows
Columns
Rows
Columns
Rows
Hz
Hz
Lines
Lines
Rows and 2 Lines
Rows
Lines
Character Times
Character Times
Character Times
Character Times
MHz
MHz
CRTC Registers
RO
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12, R13
Horizontal Total (Line 15 minus 1)
Horizontal Displayed (Line 1)
HOrizontal Sync Position (Line 1 + Line 12)
Horizontal Sync Width (Line 13)
Vertical Total (Line 9 minus 1)
Vertical Adjust (Line 9 Lines)
Vertical Displayed (Line 2)
Vertical Sync Position (Line 2 + Line 10)
Interlace (00 Normal, 01 Interlace
03 Interlace, and Vidio)
Max. Scan Line Add (Line 4b minus 1)
Cursor Start
CurSor End
Start Address (H and L)
R14, R15
Cursor (H and L)
<
Oeclmat
101
80
86
9
Hex
65
50
56
9
24
10
24
24
18
OA
18
18
11
B
o
11
128
128
o
o
B
00
80
00
80
5·166
F6845
Figure 13 F6800 Program for CRTC Initialization
Page 001 CRTC INIT. SA:O F6845/F6845·1 CTRC Initialization program
00001
00002
00003
00004
00005
00006
00007
00008
00009
00010
00011
oo012A 0000
00013A 0000 5F
00014A 0001 CE 1020 A
oo015A 0004 F7 9000 A
00016A 0007 A6 00 A
ooo17A 0009 B7 9001 A
oo018A OOOC 08
ooo19A 0000 5C
00020A oooE C1 10 A
ooo21A 0010 26 F2 0004
oo022A 0012 3F
00023
00024
00025
00026A 1020
00027A 1020
A
65
A 1021
A
50
00028A 1022
A
56
A 1023
09
A
00029A 1024
18 A
A 1025
OA A
00030A 1026
18 A
A 1027
18 A
00031A 1028
A
00
A 1029
OB A
00 A
00032A 102A
A 102B
OB A
0080 A
oo033A 102C
00034A 102E
0080 A
00035
Total Errors 00000-00000
NAM
TIL
OPT
F6845
F6845·1
CRTC initialization program
G,S,llE=85 print FCB's, FOB's & XREF table
******************************************
CRTC addresses
"Assign
CRTCAO EQU
CRTCRG EQU
$9000
Address Register
CRTCAO + 1 Data Register
******************************************
" Initialization program
CRTC1
ORG
ClRB
lOX
STAB
lOAA
STAA
INX
INCB
CMPB
BNE
SWI
0
#CRTIAB
CRTCAO
O,X
CRTCRG
$10
CRTC1
a place to start
clear counter
table pOinter
load address register
get register value from table
program register
increment counters
finished?
no: take branch
yes: call monitor
******************************************
" CRTC register initialization table
CRTIAB
ORG
FCB
$1020
$65,$50
start of table
RO, R1 . total & H displayed
FCB
$56,$09
R2, R3 • pos. & HS width
FCB
$18,$OA
R4, R5 . V total & V total adj.
FCB
$18,$18
R6, R7 . V displayed & VS pos.
FCB
$OO,$OB
R8, R9· Interlace & Max scan line
FCB
$OO,$OB
R10,R11 . Cursor start & end
FOB
FOB
$0080
$0080
R12,R13 • Start Address
R14,R15· Cursor Address
END
CRTCl 0004 CRTCAO 9000 CRTCRG 9001 CRTIAB 1020
5·167
II
F6845
Table 7 Values Programmed Into CRTC Registers
Reg,,,
Ra
R1
R2
R3
R4
R5
R6
R7
RS
R9
R1a
R11
R12
R13
R14
R15
R16
R17
Register Name
Value
Horizontal Total
Horizontal Displayed
Horizontal Sync Position
Horizontal Sync Width
Vertical Total
Vertical Scan Line Adjust
Vertical Displayed
Vertical Sync Position
Interlace Mode
Max. Scan Line Address
Cursor Start
Cursor End
Start Address (H)
Start Address (L)
Cursor (H)
Cursor (L)
Light Pen (H)
Light Pen (L)
Nht
Programmed
Value
+1
Nht
N hd
N hd
N hsp
N hsP
N hsw
N hsw
N vt
+1
N vt
Nsdj
Nvd
Nadj
N vd
Nvsp
Nvsp
Nsl
Nsl
1
3
a
a
a
2
Figure 14 Cursor Timing Diagram
RAO·RA4'
~,-_ _ _~_ _ _ _~~_ _ _ _-:--_ _ _ _I~I_ _ _ _~_----',
1
1
1
1
1
1
I Nhd+1 I
CHARACTER ROW.
CURSOR
I
1
1
I
1
1
~I--+---1I--+--+-+--+-~I--+--+--+--+:--t-:_-+:__I-~
1
CHARACTER.
Nhd+2
1
--j-J.":
I......:---I--:---!-I~2-f-J":r-'-~Nht--'--:--'""""":--+-~2-!-'1":
1
1
1
I
--_....
~
I
1
i ":ri--';"'-"'--;.i---i-'i~
-,...----;-.1
r-i
I
1
______~r-l
"Timing Is shown for non·lnterlace and interlace sync modes.
Example shown has cursor programmed as
Cursor Register
N hd + 2
Cursor Start = 1
Cursor End
3
"The initial MA is determined by the contents of start address register,
RI2JRI3. Timi·ng is shown for R12/13
0
=
=
=
5·168
Nht
1 2 1
1
I
1
1
~
r-l~
____
F6845
Figure 15 Refresh Memory Addressing (MAo - MA1:V Timing Diagram
a:
~
w
"hxo
~I~
§r_----------------~H~O~R='Z=O~NT~A=L~O~IS=P~~~y~----------------_.r_--------HO~R~I~ZO~N~T~A~L_R~ET~R~A~CE~IN_o_n._.;~sp_'a~YI~______,
u
ua:
01
~
'1
...c
2\
>-
!!l
"~
r0
1
o
Nh.
Nhd + 1
N. I
Nhd
Nhd+ 1
N. I
o
2X1hd
Ns I
2XNhd
1
+1
2XNhd
2XNj,d
>
-1) )(
Nhd
(Nvd
1»( Nhd+ 1
1) x Nhd
(Nyd
1»( Nhd
N,.-11
Ns I
>
~
'"c
o
N,.{
Ns I
(Nvd
Nvd)( Nhd
~
+1
Nyd x Nhd + 1
Nhd
Nyt)( Nhd
+1
N y !)( Nhd
Nvt)( Nhd
+1
Nyd
.
.•
·
:;i:
0
g.
Nhd -1
Nfd
Nhd -1
Nhd
2XNhd
2XN~d 1
2XNhd
1
3Xrhd
3XNhd - 1
3XNhd
3XNhd
Nvd)( Nhd
1
xNhd
(Nvd
Nvd
+ 1) .x Nhd 1
(Nvd + l)x Nhd-1
~
...
"
u
ffi
>
I
NV! + 1
Ny! ~ Nhd
0
Nadj
-1
(Ny!
+ It
)( Nhd
(Nyt + 1) )( Nhd
(NYl
+ 1)
(Nyt + 1)
Nvd +~»)( Nhd
(Nvt
+ 1°) )(
+ 1»(
Nhd - 1
(NYI
+?)( Nhd
Nhd
(NYl + 1) ~ Nhd - 1
(NYl +
+1
(N yt +2»( N hd -1
(Nyt + 2) )( Nhd
Nhd + 1
(Nyt+ 2»( Nhd-1
(Nyt
r
Nhd
~
(NIII
Note 1: The initial MA is determined by the contents of start register, R12/R13. Timing is shown for
sync modes are shown.
1) x
.
.·
·
R
1N914
OR EQUIVALENT
5-169
+ Nht
(Nvd - 1) )( Nhd
I
+ Nht
1) )( "Nhd
+ Nht
(Nvd
Nyd x Nhd + Nht
Nyd )(
Nhd + Nht
+ Nhl
+ Nht
Only non-interlace and interlace
TEST POINTo------1"--""""1r-lKI--t
R=
2Nhd
(Ny 1)Nhd
=2.4kll
C=
+ Nhl
2Nhd + Nht
(Ny 1)Nh:d + Nht
+ 2) )( Nhd
5.0V
C
+ Nht
Nhd
Nyt )( Nj,d + Nht
Nhd
R12/R13~0.
Nhd
Ny! x Nhd
Figure 16 CRTC Bus Timing Test Load
RL
Nhl
.
I I
Nvd + Nhd
Nf'
.•
.·
Nyd x Nhd+ 1
w
~
.
1
2XN~d
..
+1
I I
ffi
(Nvd
.
·•
....
130 pF for 00-07
30 pF for MAO-MA 13, RAO-RA4,
DE, HS, VS, and CURSOR
11 kQ for 00-07
24 for All Other Outputs
•
F6845
Figure 17 CRTC Timing Dlagrem
ClK
RAO-RA4
DE
HS
VS
CURSOR
Nole: Timing measurements are referenced to and from a low Yoltage of 0.8 yolts and a high Yoltage of 2.0 Yolts unless otherwise noted.
Figure 18 CRTC Clock, Memory Addressing, and Light Pen Timing Diagrem
1·........- - - 1 / 1 c - - - -...·~1
ClK
MAO-MA13
M
lPSTB _ _ _---------+-"""'~
M
l
+
2
~~
When the CRTC detects the rising edge of LDSTB in
this period; the CATC sets the refresh memory
address 'M + 2' into the LIGHT PEN REGISTER.
tlPD1,tlPD2: Period of uncertainty for the refresh memory address.
Nole: Timing measurements are referenced
to and from a low Yoltage of 0.8 volts, and a high voltage of 2.0 volts, unless otherwise noted.
5·170
F6845
Timing Characteristics
The signal timing for the CRTC bus is shown in figure 19;
ac characteristics for the bus timing are given in table 8,
and for the CRTC timing in table 9.
Figura 19 CRTC Bus Timing Diagram
•
Read Data
Writ. Data
::jj=~:---___.......!~.!!!df;:=:===3t=====ti=~
:~~:)~_ _ _ _ _ _ _-!MP~U~W~ri~t.~D~.t~._ _ _ _ _ _ _~::::::;t::~
Notes:
1. Voltage levels shown are VL"'0.4 V, VH ;'2.4 V. unless otherwise specified.
2. Measurement points shown are 0.8 V and 2.0 V. unless otherwise specified.
Table 8 CRTC Bus Timing Characteristics
Ident.
Number Characteristic
Symbol
F68451
F8845A
Max
Min
F68A45I
F68A45A
Min
Max
Unit
F68B451
F68B45A
Min
Max
1
Cycle Time
t eve
1.0
10
0.67
10
0.5
2
Pulse Width, E Low
PWEL
430
9500
260
9500
210
3
Pulse Width, E High
PW"t-
450
9500
260
9500
20
500
ns
4
Clock Rise and Fall Time
trotl
-
25
-
25
-
20
ns
9
Address Hold Time (RS)
tAH
10
10
t AS
60
14
R/W and CS Setup Time Before E
R/W and CS Hold Time
tcs
60
15
tcH
10
10
-
ns
RS Setup Time Before E
18
Read Data Hold Time
tnHR
20
50-
20
20
SO-
ns
21
Write Data Hold Time
tnHw
10
-
10
so-
10
13
-
10
-
ns
30
Peripheral Output Data Delay Time
-
290
-
160
0
150
ns
31
Peripheral Input Data Setup Time
tDDR
tDSIIII
165
-
60
-
60
-
ns
60
60
10
10
40
40
- The data bus output buffers are no longer sourcing or sinking current by tOHR max (high impedance).
5·171
'"'s
9500 ns
ns
ns
ns
F6845
Table 9 CRTC Timing Characteristics
Characteristic
Symbol
Min
Max.
Unit
PWCL
160
PwCH
-
ns
200
Ie
MHz
tcoo
-
2.5
PWLPH
100
-
ns
tlPOl
-
120
ns
tLP02
-
0
ns
Minimum Clock Pulse Width, Low
Minimum Clock Pulse Width, High
Clock Frequency
Rise and Fall lor Clock Input
tor,tof
Memory Address Delay Time
tMAO
Raster Address Delay Time
tRAO
Display Timing Delay Time
tOTO
Horizontal Sync Delay Time
tHSO
Vertical Sync Delay Time
tvso
Cursor Display Timing Delay Time
Light Pen Strobe Minimum Pulse Width
Light Pen Strobe Disable Time
20
ns
160
ns
160
ns
300
300
300
300
ns
NoIe: The light pen strobe must fall to low level before the VSYNC.pulse rises.
DC Characteristics
The DC characteristics lor the F6845 CRTC are presented in table 10.
Table 10 CRTC DC Characteristics (Vcc
=
Symbol
Characteristic
Min
VIH
Input High Voltage
Vil
Input Low Voltage
liN
Input Leakage Current
ITSI
5.0 V :!:: 5%, Vss
Typ
=
O·C to 70·C, unless otherwise noted.)
Max
Unit
Vce
V
-0.3
-
0.8
-
1.0
2.5
jAA
Three-State (Vce
5;25 V)
/Vi"
0.4 to 2.4 V)
Output High Voltage
(iload
205 jAA)
(iload
-100 jAA)
-10
2.0
.19
jAA
-
Output Low Voltage
(iload
1.6 rnA)
-
-
0.4
V
Po
Power Dissipation
-
600
-
mW
CIN
Input Capacitance
-
-
12.5
10
-
10
VOH
VOL
CoUT
=
==
=
=
Output Capacitance
2.0
2.4
2.4
-
Condition
V
V
00·07
Other. Outputs
-
pF
5·172
00·07
Ali others
pF
All Outputs
ns
ns
ns
ns
F6845
Absolute Maximum Ratings
Stresses greater than those indicated may cause perma·
nent damage to the device. These stress ratings only, and
functional operation of the F6845 under these or any other
conditions above those indicated in this data sheet is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
Supply Voltage
Input Voltage
Operating Temperature
Storage Temperature
- 0.3 V, + 7.0 V
- 0.3 V, + 7.0 V
O·C, +70·C
- 55·C, + 150·C
•
Ordering Information
Speed
1.0 MHz
1.5 MHz
2.0 MHz
Order Code
F6845P,S
F6845AP,S
Temperature Range
O·C to + 70·C
F6845CP,CS
F6845ACP,CS
-40·C to +85·C
F68A45P,S
F68A45AP,S
O·C to +70·C
F68A45CP,CS
F68A45ACP,CS
-40·Cto +85·C
F68B45P,S
F68B45AP,S
O·C to + 70·C
5·173
F6845
5-174
F6846
ROM-I/O-Timer
Microprocessor Product
Description
The F6846 combination chip provides the means, in
conjunction with the F6802, to develop a basic 2-chip
microcomputer system. The F6846 consists of 2048
bytes of mask-programmable Read Only Memory (ROM),
an 8-bit bidirectional data port with control lines, and a
16-bit programmable timer-counter.
logic Symbol
C50
CS,
RiW
eTO
- 0 CTG
This device is capable of interfacing with the F6802
(basic F6800, clock and 128 bytes of RAM) as well as the
F6800 if desired. No external logic is required to
interface with most peripheral devices.
CTC
- 0 RESET
IRQ
E
cp,
• 2048 8-Bit Bytes of Mask-Programmable ROM
• 8-Bit Bidirectional Data Port for Parallel Interface Plus
Two Control Lines
• Programmable Interval Timer·Counter Functions
• Programmable 1/0 Peripheral Data, Control, and
Direction Registers
• Compatible with the Complete F6800 Microcomputer
Product Family
• TTL-Compatible Data and Peripheral Lines
• Single 5 V Power Supply
Pin Names
E
Ao-A10
CSo, CS1
RIW
CTG
CTC
RESET
CP1
CP2
00-07
PO-P7
CTO
IRQ
F6846
vcc= Pin 29
_V_SS_=_p_in_1_____________________________________
Connection Diagram
40-Pin DIP
Vss
Enable (Clock System <1>2) Input
Address Inputs
Chip Select Inputs
ReadIWrite Input
Counter Gate Input
External Clock Input
Reset Input
Peripheral Interrupt Input
Bidirectional Peripheral Control
Bidirectional Data Lines
Bidirectional Peripheral Data Lines
Counter Timer Output
Interrupt Request Output
A.
A7
A.
A6
AlO
As
RESET
A4
IRQ
C50
CP2
RiW
cp,
Do
Ao
0,
A,
02
A2
D,
A,
11
D.
Vee
D,
PI
D.
P.
D1
p,
CS,
Po
CTG
p,
CTC
P2
CTO
p,
21
(Top View)
5-175
Po
J;IIII
F6846
Typical Microcomputer
Vee
Vee
Vee
Vee
IRQ
F6846
ROM·I/O TIMER
MR
CSO I-4-'V;.;;M;;;.A'-_ _ _-1 VMA
CLOCK
E
2K BYTES ROM
RIW
10110 LINES
3 TIMER LINES
F6802
MPU
00-07
XTAL
D
Ao-A1S
Ao-A15
XTAL
-=
Block Diagram
RIW
E
RESET
R/W
AND
TIMING
CONTROL
iRa
Do
0,
0,
0,
D.
DATA
BUS
BUFFERS
Os
0,
0,
COMPOSITE
STATUS
REGISTER
'CSo
'CS,
Ao
A,
A,
A,
A.
CHIP
SELECT,
MODE &
ADDRESS
INPUTS
AND
LOGIC
Cp,
Cp,
p,
p,
P,
VSS~
VCC~
P.
2048
BYTE
ROM
Ps
P,
p,
• Mask Programmable
5·176
F6846
Peripheral Control (CP2) may be programmed to act
as an interrupt input (setCSR2) or as a Peripheral
Control output.
Functional Description
The F6846 combination chip may be partitioned into
three functional operating sections: programmed storage,
timer-counter functions, and a parallel 110 port.
Pin Functions
Programmed Storage
The mask-programmable ROM section is similar to other
ROM products of the F6800 family. The ROM is
organized in a 2048 by 8-bit array to provide read-only
storage for a minimum microcomputer system. Two
mask-programmable chip selects are available for user
definition.
Bus Interface,
The F6846 interfaces to the F6800, bus via an 8-bit
bidirectional data bus, two chip select lines, a readlwrite
line, and 11 address lines. These Signals, in conjunction
with the F6800 VMA Output, permit the MPU to control.
the F6846.
Bidirec,tional Data Bus (00-07)
The bidirectional data lines (00-07) allow the transfer CIt
data between the MPU and the F6846., The data bus
output drivers are 3-state devices that remain in the highimpedance (OFF) state except when the MPU performs
an F6846 register or ROM read (RMi HIGH and 110
registers or ROM selected).
"
Address inputs Ao-A10 allow any of the 2048 bytes of
ROM to be uniquely addressed. Bidirectional data lines
(00-07) allow the transfer of data between the MPU al")d
the F6846.
Timer-Counter Functions
Under software control, this 16-bit binary counter may be
programmed to count events, measure frequencies and
time intervals, or similar tasks. It may also be used for
square wave generation, single pulses of control
duration and gated delayed Signals. Interrupts may be
generated)rom a number of conditions selectable by
software programming.
Chip Select (CSo. CS1)
The CSo and CSl inputs are used to select the ROM or
110 timer of the F6846. They are mask programmed to be
active HIGH or active l-OWas specified by th,e user.
Address ,(Ao-Al0)
The Address inputs allow any Of th~,2048 bytes' of ROM
to be uniquely selected when the circuit is operating i,n
the ROM mode. In the liD-Timer mode, Address inputs
Ao, Al and A2 select the proper 110 register, while A3
through Al0 (together with CSo and CS1) can be, used, as
additional qualifiers in the ItO select circuitry. (See the
section on liD-Timer SEllect Circuitry for additional
details.)
,
,
The TimerlCounter Control Register allows control of the
interrupt enable, output enable and selection of an
internal or external clock source, a divide-by-eight
prescaler, and operating mode. The Counter-Timer Clock
(CTC) will accept an asynchronous pulse to decrement
the internal register for the counter-timer. If the divideby-eight prescaler is used, the maximum clock rate can
be four times the master clock frequency with an
absolute maximum of 4 HMz. Counter Gate input (CTG)
accepts an asynchronous TTL-compatible signal that
may be used as a trigger or gating function to the
counter-timer. The Counter Timer Output (CTO) is also
available and is under software control, being dependent
on the timer control register, the gate input, and the
clock source.
Reset (RESET) ,
"
The active LOWstate of the RESET input is used to
initialize all register,bits in the 1/0;section of the device
to their proper values. (See the section on Initialization
for timer and peripheral register reset cO,nditi,ons.)
Enable (E)
This signal synchroniies data transfer between the, MPU
and the F6846. It also performs an equivalent '
synchronization function on the External Clock. RESET '
and ,Counter Gate inputs of the F6846 timer section.
Parallel 1/0 Port
The parallel bidirectional 110 port has functional
characteristics similar to the B port on the F6821 PIA.
This includes eight bidirectional data lines and two
handshake control signals. The control and operation of
these lines are completely software programmable.
Internal registers associated with the 110 functions may
be selected with Ao, Al and A2.
Read/Write (RIW)
This signal is generated by the MPU and is used to
control the direction of data transfer on the bidirectional
data Ijnes. A LOW level on the R/W input enables the,
F684EHnput bUffers and data is transferred to the circuit
during the <1>2 pulse when the, part has bee,n selected. A
The Peripheral Interrupt input (CP1) will set the interrupt
flag (CSR1) of the Composite Status Register. The
5-177
F6846
Control Register, the Counter Gate input, and the clock
source. The output is TTL compatible.
HIGH level on the RIW input enables the output buffers
and data is transferred to the MPU during 2 when the
part is selected.
External Clock (CTC)
CTC will accept asynchronous TTL voltage level signals
to be used as a clock to decrement the timer. The HIGH
and LOW levels of the external clock must be stable for
at least one system clock period plus the sum of the setup and hold times for the inputs. The asynchronous
clock rate can vary from dc to the limit imposed by
system 2, set·up and hold times.
Interrupt Request (IRQ)
The active LOW IRQ output acts to interrupt the MPU
through logic included on the F6846. This output utilizes
an open drain configuration and permits Interrupt
request outputs from other circuits to be connected in a
wire-OR configuration.
Peripheral Data (PO·P7)
The Peripheral Data lines can be individually
programmed as either inputs or outputs via the
Peripheral Data Direction Register. When programmed as
outputs, these lines will drive two standard TIL loads
(3.2 mAl. They are also capable of sourcing up to 1.0 mA
at 1.5 V (logic HIGH output).
The External Clock input is clocked In by enable (system
2) pulses. Three enable periods are used to synchronize
and process the external clock. The fourth enable pulse
decrements the internal counter. This does not affect the
input frequency; it merely creates a delay between a
clock input transition and Internal recognition of that
transition by the F6846. All references to CTC inputs in
this document relate to internal recognition of the input
transition. Note that a clock transition that does not
meet set·up and hold·time specifications may require an
additional enable pulse for recognition.
When programmed as inputs, the output drivers
associated with these lines enter a 3·state (highimpedanoe) mode. Since there is no internal pull-up for
these lines, they represent a maximum 10 p.A load to the
circuitry driving them, regardless of logic state.
When observing recurring events, a lack of synchroni·
zation will result in either system jitter or input jitter
being observed on the output of the F6846 when using
an asynchronous clock and gate input signal. System
jitter is the result of input signals out of synchronization
with the system 2 clock (Enable), permitting signals
with marginal set-up and hold time to be recognized
within either the bit·time nearest the input transition or
subsequent bit-time.
A logic LOW at the RESET Input forces the Peripheral
Data lines to the input configuration by clearing the
Peripheral Data Direction Register. This allows the
system designer to preclude the possibility of having a
peripheral data output connected to an external driver
output during power-up sequence.
Peripheral Interrupt (CP1)
Peripheral Interrupt input CP1 sets the interrupt flags of
the Composite Status Register. The active transition for
thiS signal is programmed by the Peripheral Control
Register for the parallel port. CP1 may also act as a
strobe for the Peripheral Data Register when it is used
as an input latch. Details for programming CP1 are in the
section on the parallel peripheral port.
Input jitter can be as great as the time between input
signal negative·going transitions plus the system jitter if
the first transition is recognized during one system
cycle, and not recognized the next cycle or vice·versa.
INPUT
Peripheral Control (CP2)
Peripheral Conltol CP2 may be programmed to act as an
interrupt input or Peripheral Control output. As an Input,
this line has high impedance and is compatible with
standard TTL voltage levels. As an output, it is TIL·
compatible and may be used asa source of 1 mA at
1.5 V to directly drive the base of a Darlington transistor
switch. CP2 is programmed by the Peripheral Control
Register.
eTC INPUT
~L-_ _""
~~~~;
I---~
EITHERJ
HERE
\ . . OR
HERE
OUTPUT
~
Counter Timer (CTO)
The Counter Timer output is softWare programmed by
salected bits in the CounterlTimer Control Register. The
mode of operation is dependent on the CounterlTimer
eTe INPUT
REeOG~
INPUT
5-178
f-~ BIT TIME
SYSTEM
JITTER
---1 ___ ...i
,
l
I
F6846
Counter Gate (CTG)
CTG accepts an asynchronous TTL-compatible signal
which is used as a trigger or a clock-gating function to
the timer. The gating input is clocked into the F6846 by
the Enable (system q,2) signal in the same manner as the
previously discussed clock inputs. A CTG transition is
recognized on the fourth enable pulse, provided set-up
and hold time requirements are met. The HIGH or LOW
levels of the CTG input must be stable for at least one
system clock period plus the sum of set-up and hold
times. All references to CTG transition in this document
relate to internal recognition of the input transition.
Memory mapping the I/O can be accomplished by using
one of the CS inputs to select between ROM and I/O,
applying the F6802 VMA output to the other CS
(programmed active HIGH) and using the Address lines
to decode Address fields.
o
110(0100)
F8820
I/O (0200)
F6a50
CSo
CSo
F6802
VMAI---_+--l-----.....
The CTG input of the timer directly affects the internal
16-bit counter. The operation of CTG is therefore
independent of the divide-by-eight prescaler selection.
RAM
(000Q.0075)
CSo Active HIGH
I/O ROM
CS1
L
H
F8820
I/O (OXBO)
ROM (8000)
CO)
I/OF:!e
AI Active HIGH
As Active HIGH
Functional Select Circuitry
I/O-Timer Select Circuitry
CSo and CSt are user programmable. Any of the four
binary combinations of CSo and CSt can be used to
select the ROM. Likewise, any other combination can be
used to select the I/O-Timer. In addition, several Address
lines are used as qualifiers for the I/O-Timer.
Specifically, A3
A4
A5 logic L. A6 can be
programmed to anH, L, or don't care (X). A7
As = Ag
= Ato = don't care or one line only may be programmed
to a logic H. The available chip select options are
diagramed below.
=
=
=
Internal Addrel!sing
Seven I/O register locations within the F6846 are
accessible to the MPU data bus. Selection of these
registers is controlled by Ao, At, and A2 as shown in
Tab/e 1, provided the I/O timer is selected. CSo and CSt
must be in the I/O state and the proper register address
must be applied to access a particular register. The
Composite Status Register is read only, where all other
registers are read/write.
=
Table 1
CS1-r~~----~~o-
__________~~
I/O
SELECT
CSo
_-1:>0-------0-
A.--o
A,---O
Aa
r
r
A2
A1
Ao
Composite Status Register
Peripheral Control Register
Peripheral Data Direction Register
Peripheral Data Register
CompOSite Status Register
CounterlTimer Control Register
CounterlTimer MSB Register
CounterlTimer LSB Register
ROM Address
L
L
L
L
H
H
H
H
X
L
L
H
H
L
L
H
H
X
L
H
L
H
L
H
L
H
X
L
H
X
As
A.
A3
5-179
Internal Register Addresses
Register Selected
=
LOW Voltage Level
HIGH Voltage Level
Don't Care
F6846
conditions causes it to halt or recycle. Thus the timer is
programmable, cyclic in nature, controllable by external
inputs or MPU program, and accessib.le to the MPU at
any time.
Initialization
When the RESET input has accepted a LOW signal, all
registers are i'nitialized to the reset state. The Peripheral
Data Direction and Peripheral Data Registers are
cleared. The Peripheral Control Register is cleared
except for bit 7 (the reset bit). This forces the parallel
port to the input mode with interrupts disabled. To
remove the reset condition from the parallel port, an L
must be written into the Peripheral Control Register
bit 7 (PCR7).
Counter Latch Initialization
The timer consists of a 16-bit addressable counter and
two 8-bit addressable latches. The latches store a binary
equivalent of the desired count value minus one. Counter
initialization results in the transfer of the latch contents
to the counter. It should be noted that data transfer to
the counters is always accomplished via the latches.
Thus, the counter latches may be accurately described
as a 16-bit counter initialization data storage register.
During initialization the counter latches are preset to
their maximal count, the CounterlTimer Control Register
bits are reset to L except for bit 0 (TCRo is set), the
counter output is cleared, and the counter clock
disabled. This state forces the timer counter to remain in
an inactive state. The Composite Status Register is
cleared of all interrupt flags. During timer initialization
the reset bit (TCRo) must be cleared.
In some modes of operation, the initialization of the
latches will cause simultaneous counter initialization
(i.e., immediate transfer of the new latch data into the
counters). It is, therefore, necessary to insure that all 16
bits of the latches are updated simultaneously. Since the
F6846 data bus is eight bits wide, a temporary register
(MSB buffer register) is provided for the most significant
byte of the desired latch data. This is a write-only
register selected via Address lines Ao, A1 and A2. Data is
transferred directly from the data bus to the MSB buffer
when the chip is selected, RNV is LOW, and the timer
MSB register is selected (Ao "" L; A1 "" A2 "" H).
ROM Select Circuitry
The mask-programmable ROM section is similar in
operation to other ROM products of the F6800 microprocessor family. The ROM is organized as 2048 words
of 8-bits to provide read-only storage for a minimum
microcomputer system. The ROM is active when
selected by the unique combination of the chip
select inputs.
The lower eight bits of the counter latch can also be
referred to as a write-only register. Data bus information
will be transferred directly to the LSB of a counter latch
when the chip is selected, R/IN is LOW and the Counterl
Timer LSB Register is selected (Ao = A1 = A2 "" H).
Data from the MSB buffer will be transferred
automatically into the most significant byte of the
counter latches simultaneously with the transfer of the
data bus information to the least significant byte of the
counter latch. For brevity, the conditions of this
operation will be referred to henceforth as a write-timerlatches command.
The active levels of CSo and CSdor ROM and 1/0 select
are a user programmable option. Either CSo and CS1 may
be programmed active HIGH or active LOW, but different
codes must be used for ROM or 1/0 select. CSo and CS1
are mask programmed simultaneously with the ROM
pattern. The ROM select circuitry is shown below.
The F6846 has been designed to allow transfer of two
bytes of data into the counter latches from any source,
provided that the MSB is transferred first. In many
applications, the source of the data will be an F6800
M PU. It shou Id therefore be noted that the 16-bit store
operations of the F6800 family microprocessbrs (STS
and STX) transfer data in the order required by the
F6846. A store index register instruction, for example,
results in the MSB of the X register being transferred to
the selected address, then the LSB of the X register
being written into the next higher location. Thus, either
the index register or stack pOinter contents may be
transferred directly into either 8-bit latch with a single
instruction.
Timer Operation
The timer may be programmed to operate in modes
which fit a wide variety of applications. The device is
fully bus compatible with the F6800 system, and is
accessed by load and store operations from the MPU.
In a typical application, the timer will be loaded by
storing two bytes of data into the counter latch. This
data is then transferred into the counter during a counter
initialization cycle. The counter decrements on each
subsequent clock cycle (which may be system 1>2 or an
external clock) until one of several predetermined
5-180
F6846
A logic L at the RESET input also initializes the counter
latches. All latches will assume maximum count (65,536)
values. It is important to note that an internal reset (bit
zero of the CounterlTimer Control Register set) has no
effect on the counter latches.
TCR3, TCR4, and TCR5 select the timer operating mode,
and are discussed in the next section.
CounterlTimer Control Register bit 6 (TCRs) is used to
mask or enable the timer interrupt request. When
TCRs = L, the interrupt flag is masked from the timer.
When TCRs = H, the interrupt flag is enabled into bit 7
of the Composite Status Register (composite IRQ bit),
which appears on the IRQ output.
Counter Initialization
Counter initialization is defined as the transfer of data
from the latches to the counter with attendant clearing
of the individual interrupt flag associated with the
counter. Counter initialization always occurs when a
reset condition (external RESET = L or TCRo = H) is
recognized. It can also occur depending on the timer
mode with a write·timer-Iatches command or recognition
of a negative transition of the CTG input.
CounterlTimer Control Register bit 7 (TCR7) has a speCial
function when the timer is in the cascaded single-shot
mode. (This function is explained in detail in the section
describing the mode.) In all other modes, TCR7 merely
acts as an output enable bit. If TCR7 = L, the Counter
Timer Output (CTO) is forced LOW. Writing a logic L into
TCR7 enables CTO.
Counter recycling or reinitialization occurs when a clock
input is recognized after the counter has reached an all
L state. In this case, data is transferred from the latches
to the counter, but the interrupt flag is unaffected.
Table 2
CounterlTimer Control Register
The CounterlTimer Control Register (see Table 2) in the
F6846 is used to modify timer operation to suit a variety
of applications. The CounterlTimer Control 'Register has
a unique address space (Ao = H, A1 = L, A2 =. H) and
therefore may be written into at any time. The least
significant bit of this control register is used as an
internal reset bit. When this bit is a logic L, all timers are
allowed to operate in the modes prescribed by the
remaining bits of the control registers.
Writing H into CounterlTimer Control Register bit 0
(TCRo) causes the counter to be preset with the contents
of the counter latches, all counter clocks to be disabled,
and the timer output and interrupt flag (status register)
to be reset. The counter latch and CounterlTimer Control
Register are undisturbed by an internal reset and may be
written into regar.dless of the state of TCRo.
CounterlTimer Control Register Format
.Control
Register
State
Bit
Bit
Definition
TCRo
L
H
Internal Reset
Timer Enabled
Timer in Preset State
TCR1
L
Clock Source
Timer uses External
Clock (CTC)
Timer uses <1>2 System
Clock
+ 8 Prescaler
Enabler
Clock is not
Prescaled
Clock is Pre.scaled by
+8 Counter
H
TCR2
L
H
TCR3 .
TCR4
TCR5
X
X
X
Operating Mode
Selection
See Table 3
TCRs
L
Timer Interrupt
Enable
IRQ Masked from
Timer
IRQ Enabled·from
Timer
Timer Output
Enable
Counter Output
(CTO) Set LOW
Counter Output
Enabled
H
CounterlTimer Control Register bit 1 (TCR1) is used to
select the clock source. When TCR1 = L, the external
clock input CTC is selected, and when TCR1 = H, the
timer uses system <1>2.
TCR7
L
H
CounterlTimer Control Register bit 2 (TCR2) enables the
divide·by-eight prescaler (TCR2= H). In this mode, the
clock frequency is divided by eight before being applied
to the counter. When TCR2 = L the clock is applied
directly to the counter.
5-181
State
Definition
F6846
Table 3
CounterlTimer Control Register
I
CSR,
I
CSRe
I
I
I
CSR.
I
CSR.
CSR.
I
I
I
Interrupt Enable
= IRQ Masked
= IRQ Enabled
L
H
L
L
I
----------------For Cascaded Single-shot
L = Output Goes Low at Time·out
= Output Go•• High at Tima-out
l
H
TCR4
TCR.
L
L
L
L
L
H
L
H
L .
Timer Operating Mode
L
L
H
H
L
H
H
L
*
H
*
+ 8 Preseale Enable
L = Clock Not Prasealed
= Clock Pr.s•• led ( + 8)
H
Int.rrupt Flag Sot
H
Ca ••aded Singi. Shot
CTGI+R
T.O.
L
Continuous
CTG I + R
T.O.
H
H
Norm.1 Singi •.Shot
CTGI +R
T.O.
L
L
CTG I • I • (W + T.O.) + R
CTa I S.'ore T.O.
H
L
H
H
H
L
H
H
H
TCRs
L
Clock Source
L = ,External Clock (CTC)
= Int.rn.1 Clock (¢2)
T.O.
Frequen.cy Comparlsoll
Puis. Width Comparison
L
Continuous
L
Cas.caded Single-shot
Normal Single-shot
G
w
R
N
Frequency Comparison
T
Pulse Width Comparison
to
T.O.
'Defines Additional Timer Functions
=
T.O. B.fore CTa t
=
Control
Register
Timer Operating Mode
I
I
CTG I Belore T.O.
.Table 5 Continuous Operating Modes
(TCR3 = L, TCR7
H, TCRs = L)
TCR2 TCR4
Single·
shot
T.O. Before CTG I
CTGI·' .... A
CiiiI'I+R
timer output is enabled (TCR7 = H), a square wave will
be generated at the Counter Timer Output CTO (see
Table 5).
Control Register
.
= Timer Enabled
CTGI+W+R
Operating Modes
TCR4
J
H
Counter Initialization
I
The F6846 has been designed to operate effectively in a
wide variety of applications. This is accomplished by
using three bits of the CounterlTimer Control Register
(TCR3, TCR4 and TCRs) to define different operating
modes of the timer, outlined in Table 4.
TCR3
CSRo
Continuous
Timer Operating Modes
Table 4
I
H = Reset Stale
= Output Ol•• bl.d (LOW)
= Output Enabled
TCR.
CSR,
Ilnt.rnal R.s.t
Timer Output Enable
H
I
CSR2
L
H
Initialization/Output Waveforms
Counter
Initialization
G+ W + R
G + R
Timer Output (2X)
(n
1·
+ 11m In +
-1-
llm(n
-1-
+ 11{T)
-I
~-VOII
.
I
I
1.0.
Negative transition of CTG input
Write·tlmer-Iatches command
Timer Reset (TCRO' = H or External
16-bit number in Counter Latch
PeriOd of Clock input to Counter
Counter initialization cycle
Counter Time·out (all L condition)
.
I
T.O-
RESEi' =
I
-VOL
1.0.
L)
Note
All time intervals shown above assume that the
and eTC signals are
synchronized to system <1>2 with the specified set-up and hold time
requirements.
=
em
Continuous Operating Mode (TCR3
L, TCRs
L)
The timer may be programmed to operate in a
continuous counting mode by writing L into bits 3 and 5
of the CounterlTimer Control Register. Assuming that the
5-182
F6846
=
=
The second difference is the method used to change the
output level. Counter/Timer Control Register bit 7 (TCR7)
has a special function in this mode. The Counter Timer
Output (CTO) is equal to TCR7 clocked by time-out. At
every time-out the content of TCR7 is clocked to and
held at the CTO. Thus, output pulses of length greater
than one timer cycle can be generated by cascading
timer cycles and counting time-outs with a software
program.
Either a Timer Reset (TCRo
H or External Reset
L)
condition or internal recognition of a negative transition
of the CTG input results in counter initialization. A writetimer-latches command can be selected as a counter
initialization signal by clearing TCR4.
The discussion of the continuous mode has assumed
that the application requires an output signal. It should
be noted that the timer operates in the same manner
with the output disabled (TCR7 = L). A read· timercounter command is valid regardless of the state
of TCR7.
An interrupt is generated at each time-out. To cascade
timer cycles, the MPU would need an interrupt routine to:
1) count each time-out and determine when to change
TCR7; 2) write into TCR7 the state corresponding to the
next desired state of the output waveform (only
necessary during the last timer cycle before the output
is to change state); and 3) clear the Interrupt flag by
reading the CompOSite Status Register followed by the
read timer MSB. It is also possible, if desired, to change
the length of the timer cycle by reinitializing the timer
latches. This allows more flexibility for obtaining
desired times.
Single-shot Timer Mode
(TCR3 = L, TCR4 = H, TCRs H)
This mode is identical to the continuous mode with two
exce'ptions. The first of these is obvious from the
name-the output returns to a LOW level after the initial
time-out and remains LOW until another counter
initialization cycle occurs. The internal counting
mechanism remains cyclical in the single-shot mode.
Each time-out of the counter results in the setting of an
individual interrupt flag and reinitialization of the
counter.
=
Cascaded Single-shot Mode Output Waveform
j.--(n
The second major difference between the single-shot
and continuous modes is that the internal counter
enable is not dependent on the CTG input level
remaining in the LOW state for the single-shot mode.
r
~1
I...
.1.
1...
+
1)-+-(n
T,O,
+
T'F-
tl
H = Write an "H" into TCR7
L = Write an "L" into TCR7
n~!-_--;.-_-:
( n + 1 ) - - - -....0-(n
T,O,
t I t0
Normal Single-Shot Mode Output Waveform
to
J
+ 1 ) - + - ( n + 1)--+-(n + 1 ) - + - ( n + 1)-.\
Note
All time intervals shown above assume the CTG and CTC signals are
synchronized to system 2 with the specified set·up and hold time
requirements.
1)-.\
H = Write an "H" into TCR7
L = Write an "L" into TCR7
Time Interval Modes (TCR3
Note
All time intervals shown above assume the CrG and CTC signals are
synchronized to system 2 with the specified set·up and hold time
requirements.
= H)
The time interval modes are provided for applications
requiring more flexibility of interrupt generation and
counter initialization. The interrupt flag is set in these
modes as a function of both counter time-out and CTG
input transition. Counter initialization is also affected by
interrupt flag status. The output signal is not defined in
any of these modes. Other features of the time interval
modes are outlined in Tab/e 6.
Cascaded Single-shot Mode
(TCR3 = L, TCR4 = L, TCRs L)
This mode is identical to the single-shot mode with two
exceptions. First, the output waveform does not return to
LOW level and remain LOW after time-out. Instead, the
output level remains at its initialized level until it is
reprogrammed and changed by time-out. The output level
may be changed at any time-out or may have any number
of time-outs between changes.
=
5-183
F6846
Table 6
Timer Interval Modes (TCR3
TCR4 TCRs
Application
= H)
condition will be generated if TCRs = L and the period
of the pulse (single pulse or measured separately
repetitive pulses) at the CTG input is less than the
counter time-out period. If TCR5 = H, an interrupt is
generated if the pulse period is greater than the
time-out period.
Conditi.on for Setting
Individual Interrupt Flag
L
L
Frequency Interrupt generated if CTG
Comparison input period (1/F) is less
than counter time-out (T.O.)
L
H
Frequency Interrupt generated if CTG
Comparison input period (1/F) is greater
than counter time-out (T.O.)
H
L
Pulse Width Interrupt generated if CTG
Comparison input down time is less
than counter time-out (T.O.)
H
H
Pulse Width Interrupt generated if CTG
Comparison input down time is greater
than counter time-out (T.O.)
=
Assume now with TCRs = H that a counter initialization
has occurred and that the CTG input has returned LOW
prior to counter time-out. Since there is no iildividual
interrupt flag generated, this automatically starts a new
counter initialization cycle. The process will continue
with frequency comparison being performed on each
CTG input cycle until the mode is changed, or a cycle is
determined to be above the predetermined limit.
=
=
Frequency Comparison Mode (TCR3
H, TCR4
L)
The timer within the F6846 may be programmed to
compare the period of a pulse (giving the frequency after
calculations) at the CTG input with the time period
required for counter time·out. A negative transition of the
CTG input enables the counter and starts a counter
initialization cycle-provided that other conditions as
noted in Table 7 are satisfied. The counter decrements
on each clock signal recognized during or after counter
initialization until an interrupt is generated, a write-timerlatches command is issued, or a timer reset condition
occurs. It can be seen from Table 7 that an interrupt
Table 7
TCR3
= H, TCR4 = L
Counter Initialization
Counter Enable
Flip-Flop Set
(CE)
Counter Enable
Flip-Flop Reset
(CE)
Interrupt Flag
Set (I)
L
G I • I • (CE + TO • CE) + R
GIW·R.I
W + R +1
G I before TO
H
G I •I + R
GIW·R.I
W + R + I
TO before G I
i repref;ients
the interrupt for a given timer.
Table 8
Pulse Width Comparison Mode
TCR3
As can be seen in Table 8, a positive transition of the
CTG input disables the counter. With TCRs = L, it is
therefore possible to directly obtain the width of any
pulse causing an interrupt.
Frequency Comparison Mode
Control Reg
Bit 5 (TCRs)
= H, TCR4
=
Pulse Width Comparison Mode (TCR3
H, TCR4
H)
This mode is similar to the frequency comparison mode
except for the limiting factor being a positive, rather
than a negative, transition of the CTG input. With
TCRs = L, an individual interrupt flag will be generated
if the L level pulse applied to the CTG input is less than
the time period required for counter time-out. With
TCRs = H, the interrupt is generated when the reverse
condition is true.
= H
Control Reg
Bit 5 (TCRs)
Counter Initialization
Counter Enable
Flip-Flop Set (CE)
Counter Enable
Flip-Flop Reset (CE)
Interrupt .Flag
Set (I)
L
GI.I+R
GI.w.R.T
W+ R + 1+ G
G I before TO
H
GI.T+R
GIIW.R.I
W+R+I+G
TO before G I
5-184
F6846
1. Timer Reset-Internal Reset bit (TCRo = H) or
External Reset
L
Differences Between the F6840 and the F6846 Timers
1. Control Registers 1 and 3 are buried (access through
Control Register 2 only) in the F6840 timer. In the
F6846 all registers are directly accessible.
=
2. Any Counter Initialization condition
3. A write-timer-Iatches command if time interval modes
(TCR3
H) are being used.
2. The F6840 has a dual 8-bit continuous mode for
generating non-symmetrical waveforms. The F6846
has a cascaded one-shot mode which can accomplish
the same function, but also allows the user to
generate waveforms longer than one time-out.
=
4. A read-timer-counter command, provided this is
preceded by a read Composite Status Register while
CSRo is set. This latter condition prevents missing an
interrupt request generated after reading the status
register and prior to reading the counter.
3. Because of the different modes, there is a difference
in the control registers between the F6840 and the
F6846. (See Table 9).
The remaining bits of the Composite Status Register
(CSR3-CSRe) are unused. They default to a logic L
when read.
Composite Status Register
The Composite Status Register (CSR) is a read-only
register which is shared by the timer and the peripheral
data port of the F6846. Three individual Interrupt flags in
the register are set directly via the appropriate
conditions in the timer or peripheral port. The composite
interrupt flag, and the IRQ output, respond to these
individual interrupts only if corresponding enable bits are
set in the appropriate control registers. The sequence of
assertion is not detected. Setting TCRe while CSRo is
HIGH will cause CSR7 to be set, for example.
Composite Status Register and Associated Logic
")-.....-Do-~ IRQ
The composite interrupt flag (CSR7) is clear only if all
enabled individual interrupt flags are clear. The
conditions for clearing CSR1 and CSR2 are detailed in a
later section. The timer interrupt flag (CSRo) is cleared
under the following conditions:
Table 9
F6840 and F6846 Control Register Comparison
Control Register Bit
Table 10
F6840
F6846
2
7
16-bit or dual 8-bit mode control
Output enable (all modes)
+ 8 prescale enable
Output next state (cascaded one-shot
mode only), output enable all other modes
o
R1 internal reset
R2 control register select
R3 timer 3 clock control
Internal reset
Composite Status Register Format
I
CSR,
I
CSR,-CSR. Not Used Delault to L When Read
l
1
COlI'\pollte Interrupt, Flag
L == No Enabled Interrupt Fl." Set
H =- One or More Enabled Interrupt Flaga Set*
I
CSR.
I
CP2 Interrupt Flag
L
No Int Req
H = Int Requoated
=
1
CSR.
J
I
CSR.
Timor Interrupt Flag
No Int Req
L
H
Int Requested
=
=
J
I
Inverse 01 This Bit Appears at IRQ Output
·Status of This Bit can be Expressed
CSR, • CSRo - TCR.
+
I
II:
CSR •• PCR.
+
CSR.
+
PCR.
5-185
CP1 Interrupt
L
Nolnt Req
H = Int Requested
=
1
F6846
Peripheral Data Regi.ster
This 8-bit register is used for transferring data between
the peripheral data port and the MPU. Any bit
corresponding to an output line will be used to drive the
output buffer associated with that line. Data in these
output bits are normally provided by an MPU write
function. (Input bits, those associated with input lines,
are unchanged by a write command.) Any input bit will
reflect the state of the associated input line if the input
latch function is deselected. If the Peripheral Control
Register is programmed to provide input latching, the
input bit will retain the state at the time. CP1 was
activated until the Peripheral Data Register is read by
the MPU.
I/O Operation
Parallel Peripheral Port
The peripheral port of the F6846 contains eight
Peripheral Data lines (PO-P7), two peripheral control lines
(CP1 and CP2), a Peripheral Data Direction Register, a
Peripheral Data Register, and a Peripheral Control
Register. The port also directly affects two bits (CSR1
and CSR2) of the Composite Status Register.
The peripheral port is similar to the "B" side of a PIA
(F6821) with the following exceptions:
1. All registers are directly accessible in the F6846. Data
direction and peripheral data in the F6821 are located
at the same address, with bit 2 of the control register
used for register selection.
Peripheral Control Register
This 8-bit register is used to control the reset function· as
well as for selection of optional functions of the two
peripheral control lines (CP1 and CP2). The Peripheral
Control Register functions are outlined in Tab/e 11.
2. Peripheral Control Register bit 2 (PCR2) of the F6846
is used to select an optional input latch function. This
option is not available with F6821 PIAs.
Peripheral Port Reset (PCR7)
Bit 7 of the Peripheral Control Register (PCR7) may be
used to initialize the peripheral section of the F6846.
When this bit is set HIGH, the Peripheral Data Register,
the Peripheral Data Direction Register, and the interrupt
flags associated with the periphe(al port (CSR1 and
CSR2) are all cleared. Other bits in the Peripheral Control
Register are not affected by PCR7.
3. Interrupt flags are located in the F6846 Composite
Status Register rather than bits 6 and 7 of the control
register as used in the F6821.
4. Interrupt flags are cleared in the F6821 by reading
data from the Peripheral Data Register. F6846
interrupt flags are cleared by either reading or writing
to the Peripheral Data Registerprovided that this
sequence is followed: a. flag set, b. read Composite
Status Register, c. read/write Peripheral Data
Register.
PCR7 is set by either a logic L at the external RESET
input or under program control by writing an H into the
location. In any case, PCR7 may be cleared only by
writing an L into the location while RESET is HIGH. The
bit must be cleared. to activate the port.
5. Bit 6 of the F6846 Peripheral Control Register is not
used. Bit 7 (PCR7) is an internal reset bit not available
on the F6821.
Control of Peripheral Interrupt Line (CP1)
CP1 may be used as an interrupt request to the F6846,
as a strobe to allow latching of input data, or both. In
any case, the .input can be programmed to be activated
by either a positive or negative transition of the signal.
These options are selected via Peripheral Control
Register bits PCRo, PCR1 and PCR2.
6. The Peripheral Data lines (and CP2) of the F6846
feature internal current limiting which allows them to
directly drive the base of Darlington npn transistors.
Peripheral Data Direction Register
The M PU can write directly to this 8-bit register to
configure the Peripheral Data lines as either inputs or
outputs. A particular bit within the register (DDRn) is
used to control the corresponding Peripheral Data line
(Pn). With DDRn = L, Pn becomes an input; if DDRn = H,
Pn is an output. For example, writing Hex $OF into the
Peripheral Data Direction Registeuesults in Po through
P3 becoming outputs and P4 through P7 inputs. Hex $55
in the Peripheral Data Direction Register results in
alternate output and inputs at the parallel port.
Peripheral Control Register bit 0 (PCRo) is used to enable
the interrupt transfer circuitry of the F6846. Regardless
of the state of PCRo, an active transition of CP1 causes
the Composite Status Register bit 1 (CSR1) to be set. If
PCRo
H, this interrupt will be reflected in the
composite interrupt flag (CSR7), and thus at the IRQ
output. CSR1 is c:leared by a peripheral port reset
condition or by either reading or writing to the Peripheral
Data Register after the Composite Status Register is
=
5-186
F6846
Table 11
Peripheral Control Register Format (Expanded)
I
PCR,
I
PCR.
I
PCR.
I
I
PCR4
PCR.
I
I
I
I
PCRo
I
CP2 Direction Control
L = CP2 Is Input
H = CP2 Is Output
I
Writing L to This Location)
~---------------L = Normal Operation
I
H = Reset Condition (Clears Perlph
Data and Data Direction Reg ± CSR1 I: CSR2)
I
I
CPo Actl.o Edge Select
L = Negative (I) Edge
H
= Pooiti.o (I) Edge
I
II
I
PCR.
I
CP, Actl.e Edge Select
L = Negatl.o (I) Edge
H = Pooltl.e (I) Edge
CP1 Input Latch Control
L = Input Data Not Latched
H = Input Data Latched on Active CP1
I
I
ICPo I. Input (PCR. = "0'11
PCR.
I
Cp, Int. Enable
L = CPt Int. Masked
H = CP, Int. Enabled
Reset (Set by Ext. Resat = L or Writing
H Into Location; Cleared by
PCR,
PCR,
I
CPo Int. Enable
L = CP2 Int. Masked
H = CPolnt. Enabled
CPo Is Output (PCR.
=H
PCR.
PCR.
L
L
Interrupt Acknowledge
L
H
Input/Output Acknowledge
H
LorH
Programmable Output
(CP2 Reflects Data
Written into PCR3)
Control of Peripheral Control Line (CP2)
CP2 may be used as an input by writing an L into PCR5.
In this configuration, CP2 becomes a dual of CP1 in
regard to generation of interrupts. An active transition
(as selected by PCR4) causes bit 2 of the Composite
Status Register to be set. PCR3 is then used to select
whether the CP2 transition is to cause CSR? to be set
and, thereby, cause IRQ to go LOW. CP2 has no effect on
the input latch function of the F6846.
read. The latter alternative is conditional; CSR1 must
have a logic H when the Composite Status Register was
last read. This preculudes inadvertent clearing of
interrupt flags generated between the time the
Composite Status Register is read and the manipulation
of peripheral data.
Peripheral Control Register bit 1 (PCR1) is used to select
the edge which activates CP1. When PCR1 = H, CP1 is
active on negative transitions (HIGH-to·LOW). LOW-toHIGH transitions are sensed by CP1 when PCR1 = H.
Writing an H into PCR5 causes CP2 to function as an
output. PCR4 then determines whether CP2 is to be used
in a handshake or programmable output mode. With
PCR4 = H, CP2 will merely reflect the data written into
PCR3. Since this can readily be changed under program
control, this mode allows CP2 to be a programmable
output line in much the same manner as those lines
selected as outputs by the Peripheral Data Direction
Register.
In addition to its use as an interrupt input, CP1 can be
used as a strobe to capture input data in an internal
latch. This option is selected by writing a HIGH into
Peripheral Control Register bit 2 (PCR2). In operation, the
data at the pins deSignated by the Peripheral Data
Direction Register as inputs will be captured by an
active transition of CP1. An MPU read of the Peripheral
Data Register will result in the captured data being
transferred to the MPU; it also releases the latch to
allow capture of new data. Note that successive active
transitions with no read·peripheral-data command
between does not update the input latch. Also, it should
be noted that use of the input latch function (which can
be deselected by writing an L into PCR2) has no effect
on output data. It also does not affect interrupt function
of CP1.
The handshaking mode (PCR5 = H, PCR4 = L) allows
CP2 to perform one of two functions as selected by
PCR3. With PCR3 = H, CP2 will go LOW on the first
Enable (system q,2) positive transition after a read or
write to the Peripheral Data Register. This input/output
acknowledge signal is released (returns HIGH) on the
next positive transition of the enable signal.
5-187
F6846
=
In the interrupt acknowledge mode (PCR5
H,
PCR4 = PCR3 = L), CP2 is set when CSR2 is set by an
active transition of CPl. It is relea.sed (goes LOW) on the
first positive transition of Enable after CSRI has been
cleared via an MPU read or write to the Peripheral Data
Register. (Note that the previously described conditions
for clearing CSRI still apply.)
Restart Sequence
A typical restart sequence for the F6846 will include
initialization of both the Peripheral Control and
Peripheral Data Direction Registers of the parallel port. It
Is necessary to set up the Peripheral Control Register
first, since PCR7
L is a condition for writing data into
the Peripheral Data Direction Register. (A logic L at the
external RESET input automatically sets PCR7).
=
Absolute Maximum Ratings
Supply Voltage, Vee
Input Voltage, VIN
Operating Temperature, TA
Storage Temperature, Tstg
Thermal Resistance, e second 2 .pulse •
0.4 V
Fig. 5
IRQ Release Time
Fig. 6
Peripheral Port Set·up Time
Bus Write Timing (Write Information from MPU)
:?J
PO-P7
.
2.0V
0.8 V
~ ~
..
Fig. 3
Peripheral Port Latch Set·up and Hold Time
Po-P,
)
2.0 V 2.0 V
0.8 V 0.8 V
Fig. 7
X
tpsu
CP2 Delay Time
(PCRs = H, PCR4
tPDH
E
cp,
Fr-,.iO""","V- - - - . , ' - - _
~
[2.0 V
~I
cp,
I
2.0 V
0.8 V
''-----I F------I! L
Ip',lpl
1--------
~
CPo
5-191
= L)
L, PCR3
{ ...
k,f-!___
Fh-::
i4
..I.
-:;-V- -
F6846
Fig. 8
Custom .ROM Programming Information
The customer's unique program code pattern may be
submitted to Fairchild in several methods. The most convenient and readily verifiable is in·the form of 2708, 2716
or 2732 EPROMs. Program code patterns may also be
submitted on Fairchild Formulator MKIII floppy disks or
on HP cassette tape in Formulator or MIKBUG* format.
Input Pulse Widths·
tPWL
CTC OR
CTll
O.BY
i'---....tt
Customer Company Name ____________
Fig. 9
I
Input Set·up and Hold Times'
~~
eTC
ffi
::'-
Customer Contact Name
Customer Part No.
Address
Phone No.
Fairchild Part No. _ _ _ _ _ _ _ _ _ _ _ _ _ __
~)C:0 v
O.B
Fairchild Use Only
SLNo.
Bid Control No.
Field Sales Engineer
Date Sent
v
Note
This mode is valid only for sYr)chronous ·operation.
Fig. 10
Output Delay
Customer Input Media
o 2708 EPROM
o 2716 EPROM
o 2732 EPROM
o H P Cassette
o Formulator Format
E
Request for Return Media
o Listing
.
D EPROM (include blank EPROMs)
CTO
Fig. 11
Bus Timing Test Loads
Load A
Rom Select"
CSo
CS1
Load B
(Do-D" CTO, CPo, ""-P,)
(IRQ Only)
1/0 Select"
CSo
CS1
A6 _______~__________________ (maybeunused
5.0 V
RL =2.5k
TEST POINT - . - -......-i(II---+
C
R
T·
TESTPOINT~
EQUIV
100 P F·r
C
= 130 pF for 00-07
R
= 11.7 k[Jfor Oo-D7
= 24 k[J for CTO, CP2, PO-P7
Location Select (Select 1 only)
o A7 HIGH
o As HIGH
o Ag HIGH
o A10 HIGH
o Not used
1N914 OR
.
'ROM and 1/0 Selects must be different.
H = HIGH to Select
L = LOW to Select
= 30 pF for CTO, CP2, Po-P7
5·192
F6846
Formulator Format
__0~1__
'~1__2~1_3~1_4~1~5~_6~1__7_1~8~_9~1_'_0~1_"~~{~(~I_M_-6~I_M_-5~I_M-_4~I_M_-3~I_M_-2~I_M-_'~I_M__
SOA
L,
SOR
La
A3
A2
A,
Ao
T,
To
001
Start of record defined to be a colon(:)
Length field defined to be the number
of packed data bytes per record. Each
record is (2 • L) + 11 characters in
length inclusive of start of record
Length 0 implies end of relocatable
module.
L1 Lo
000
0"
Dno
Dnl
0(n-l)10(n_l)0
CK,
eKe
Type field.
Data field.
Checksum field defined to be negaCK, CKo
tive modulo 256 summation of all
bytes since start of record. A
summation of all characters in a
record, including the checksum,
will result in zero.
All characters other than SOR are ASCII hexadecimal
(0-9, A-F).
T1 To
001 Doo ... D(n)1 D(n)O
Address Field
MIKBUG Format
I
Lead., (Null,)
(CA)
(LF)
(NULL)
Frame
. rof-l
F .. me, ot Tape
Checksum
10
CC 30
Header
Record
Frame
1. Start-ol-Record
53
2. Type of Record
30
3.
31
Byte Count
32
4.
7.
S
~
31
Address/Size
8.
30
30
End-ol-file
Record
53
53
12
16
0000
1100
Byte Count ·2
39
9
30
33
G3
30
30
30
0000
30
30
9.
10.
39
CC
Data
30
5.
6.
CC
Record
48-11
98
44~O
32
46
43
Fe (Checksum)
Data
n (Checksum)
S
CC
Byte Count
Start of record
Type of record
5-193
Two frames equal one byte. Frames 3
through n are hexadecimal digits (in
7-bit ASCII) which are converted to BCD.
Two BCD digits are combined to make
one 8-bit byte. The checksum is the ones
complement of the summation of 8-bit
bytes.
II
F6846
Ordering Information
Speed
Order Code
Temperature Range
1.0 MHz
F6846P, S
O·G to
P
+ 70 G
D
= Plastic Package; S = Ceramic Package
5·194
F6847
Video Display Generator
Microprocessor Product
Description
Logic Symbol
The Fairchild F6847 Video Display Generator (VDG) provides a
means of interfacing the Fairchild F6800 microprocessor family
(or similar products) to a commercially available color or
black-and-white television receiver. Applications of the VDG
include video games, bioengineering displays, education,
communications, and any instance in which graphics
are required.
The VDG reads data from memory and produces a composite
video signal that allows the generation of alphanumeric or
graphic displays. The generated composite video may be
up-modulated to either channel 3 or 4 by using a suitable rf
modulator. The up-modulated signal is suitable for application
to the antenna of a color TV. Figure 1 illustrates a typical TV
game application.
• Generates Four Different Alphanumeric Display Modes
and Eight Graphic Display Modes
• Compatible With the F6800 Family
• The Alphanumeric Modes Display 32 Characters per
Line by 16 Lines.
• An Internal Multiplexer Allows the Use of Either the
Internal ROM or an External Character Generator.
• An External Character Generator Can Be Used to Extend
the Internal Character Set for "Limited Graphic" Shapes.
• One Display Mode Offers 8-Color 64 x 32 Density
Graphics in an Alphanumeric Display Mode.
• One Display Mode Offers 4-Color 64 x 48 Density
Graphics in an Alphanumeric Display Mode.
• All Alphanumeric Modes Have a Selectable Video
Inverse.
• Generates Full Video Signal
• Generates R-Y and B-Y Signals for External Color
Modulator
• Full Graphic Modes Offer 64 x 64, 128 x 64,
128 x 96,128 x 192, or 256 x 192 Densities.
• Full Graphic Modes Allow 2-Color or 4-Color Data
Structures.
• Full Graphic Modes Use One of Two 4-Color Sets or One
of Two 2-Color Sets.
12
27
29
30
31
32
MS GM 2 GM 1 GM o INT/EXT lNV
21
DA12
20
OA ll
19
DAlo
18
DAg
16
DA,
15
DA7
14
DA,
13
DAs
26
DA4
25
DA3
24
DA,
23
DA,
22
DAo
33
34
elK
AfS
35
39
NG ess
DO,
DO,
DDs
004
F6847
003
DO,
DO,
00 0
VSS ~ Pin 1
Vee ~ Pin 17
10
11
y
RP
FS
HS
28
36
37
38
Connection Diagram
40-Pin DIP
vss
40
DO,
DO,
39
css
000
38
HS
DO,
37
FS
DO,
36
Ai'
003
35
AlG
DO,
34
AlS
33
CLK
32
INV
DDs
CHB
$B
10
31
iN'f/EXT
$A
11
30
GMo
MS
12
29
GM,
DAs
13
28
Y
CA6 .
14
27
GM,
DA,
15
26
DA4
DA,
16
25
DA3
Vee
17
24
DA,
DAg
18
23
DA,
DA10
19
22
DAo
DAl1
20
21
OA12
(Top View)
5·195
40
•
F6847
Fig. 1. Block Diagram of Use of the VDG in a TV Game .
MS elK ¢B ¢A
3.58 MHz
D
RF
Modulator
Pin Functions
Vee
+5 V
Vss
ClK
DAo - DA12
000 - 005
006, DO?
cbA,cbB,Y
CHB
RP
INV
INT/EXT
Ground
Color burst clock 3.58 MHz (input)
Address lines to display memory, high
impedance during memory select (MS)
Data from display memory RAM or ROM
Data from display memory in graphic mode;
data also in alpha external mode; color data in
alpha semigraphic-4 or -6 mode
Chrominance and luminance analog (R-Y, B-Y,
Y) output to rf modulator
Chroma Bias; reference A and B levels
Row Preset; output to provide timing for external
character generator
Horizontal Sync; output to provide timing for
external character generator
A/S
A/G
FS
CSS
5-196
Y
RFto TV
Inverts video in all alpha modes
Switches to external ROM in alpha mode and
between alpha semigraphic-4 and alpha
semigraphic-6 in semigraphics mode
Alpha/Semigraphics; selects between alpha and
semigraphics in alpha mode
Memory Select; forces VDG address buffers to
high-impedance state
Switches between alpha and graphic modes
Field Synchronization; goes low at bottom of
active display area
Color Set Select; selects between two alpha
display colors or between two color sets in
semigraphics-6 and full graphics mode
Graphic Mode Select; selects one of eight
graphic modes
F6847
VDG Signal Descriptions
Address Outputs (DAO - DA12)
Thirteen address lines are used by the VDG to scan the display
memory. The starting address of the display memory is located
at the upper left corner of the display screen. As the television
sweeps from left to right and top to bottom, the VDG
increments the RAM display address. These lines are
TTL-compatible and may be forced into a high-impedance state
whenever the MS pin goes LOW.
Data Inputs (000 - 007)
Eight TTL-compatible data lines are used to input data from the
RAM to be processed by the VDG. The data is interpreted and
transformed into luminance Y (pin 28) and color outputs q,A
and q,B (pin 11 and pin 10).
Synchronizing Outputs (FS. HS. RP)
Three TTL-compatible outputs provide circuits exterior to the
VDG with timing references to the following internal VDG
states:
Field Sync (FS) - The HIGH-to-LOW transition of the FS
output coincides with the end of active display area. During
this time interval, an MPU may have total access to the
display RAM without causing undesired flicker on the
screen. The LOW-to-HIGH transition of FS coincides with
the trailing edge of the vertical synchronization pulse.
Horizontal Sync (HS) - The HIGH-to-LOW transition of the
HS output coincides with the leading edge of the horizontal
snyc pulse portion of the VDG luminance (Y) output.
Power Inputs
Vee requires +5 volts. VSS requires zero volts and is normally
ground. (The tolerance and current requirements of the VDG
are specified in the DC Characteristics table.)
Row Preset (RP) - I! desired, an external character
generator ROM may be used with the VDG. In this
configuration, an external 4-bit counter, used to supply row
selection, is clocked by HS and cleared by the RP signal.
Mode Control Inputs (A/G. A/s. INT/EXT. GMo• GM1• GM2 •
CSS.INV)
Eight TTL-compatible inputs are used to control the operating
mode of the VDG. Ais, INT/EXT, CSS and INV may be
changed on a character-by-character basis. The CSS pin is
used to select between two possible alphanumeric colors when
the VDG is in the alphanumeric mode and between two color
sets when the VDG is in the semigraphics-6 and full graphic
mode. Table 1 illustrates the various modes that can be
obtained using the mode contollines.
Video Outputs (q,A. B. Y. CHB)
These four analog outputs are used to transfer luminance and
color information to a standard NTSC color television receiver,
either via the rf modulator or directly into Y, q,A, and q,B
television video inputs.
luminance (y) - This six-level analog output contains
composite sync, blanking, and four levels of video
luminance.
A - This three-level analog output is used in combination
with the q,B and Y outputs to specify one of eight colors.
Display Modes
The VDG is capable of generating 12 distinct display modes.
The color set selection (CSS) and invert (INV) pins allow
variations on certain modes. The VDG displays two
alphanumeric modes with two compatible semigraphic modes
or one of eight full graphic modes. A detailed description of the
various modes of operation follows. A summary of major
modes can be found in Table 2, and a detailed description of
VDG modes can be found in Table 3.
B - This four-level analog output is used in combination
with the q,A and Y outputs to specify one of eight colors.
Additionally, one analog level is used to specify the time of
the color burst reference signal.
Chroma Bias (CHB) - This pin is an analog output and
provides a dc reference corresponding to the quiescent
value of q,A and B. CHB is used to guarantee good
thermal tracking and minimize the variation between the
parts.
Alphanumeric Display Modes
All alphanumeric modes occupy an 8 x 12 dot character matrix
box; there are 32 x 16 character boxes per TV frame. Each
horizontal dot (dot-clock) corresponds to one-hal! the period
duration of the 3.58 MHz clock, and each vertical dot is one
scan line. One of two colors for the lighted dots may be
selected by the color set select pin.
Synchronizing Inputs (MS. ClK)
Three-State Control (MS) - This is a TTL-compatible input
that, when LOW, forces the VDG address lines into a
high-impedance state. This may be done to allow other
devices (such as an MPU) to address the display memory
RAM.
Internal Alphanumeric Mode - In the internal
alphanumeric mode, an internal ROM will generate 64 ASCII
display characters in a standard 5 x 7 box. Six bits of the
8-bit data word are used for the ASCII character generator;
the two bits not used can be used to implement inverse video
or color switching on a character-by-character basis. A
512-word display memory is required for this class of display.
Clock (ClK) - The VDG clock input (CLK) requires a
3.579545 MHz (standard) TV crystal frequency square
wave. The duty cycle of this clock must be between 45 and
55 percent since it controls the width of alternate dots on the
television screen.
5-197
•
F6847
selected by using the color set select pin. A 1K x 8 display
memory is required. Each pictel equals two dot-clocks by
three scan lines.
External Alphanumeric Mode - In the external
alphanumeric mode, an. external character generator may be
used to generate custom character sets of up to 256
separate 8 x 12 dot characters, each defined by an 8-bit data
word. If fewer than eight bits are used for character
definition, the remaining bits may be used for inverse video
selection or color switching on a character-by-character
basis. This display mode also requires a 512-word display
memory.
The 128 x 64 Color Graphics Mode (Graphics Two C) The 128 x 64 color graphics mode generates a display matrix
128 elements wide by 64 elements high. Each element may
be one of four colors. A 2K x 8 display memory is required.
Each pictel equals two dot-clocks by three scan lines.
The 128 x 96 Graphics Mode (Graphics Two R) - The 128
x 96 graphics mode generates a display matrix 128 elements
wide by 96 elements high. Each element may be either On or
Off. However, the entire display may be one of two colors,
selected by using the color set select pin. A 2K x 8 display
memory is required. Each pictel equals two dot-clocks by two
scan lines.
Alpha Semigraphic-4 Mode - The alpha semigraphic-4
mode translates bits 0 through 3 into a 4 x 6 dot element in
the standard 8 x 12 dot box. Three data bits may be used to
select one of eight colors for the entire character box. The
extra bit is available to implement mode switching on-the-fly.
A 512-word display memory is required. A density of 64 x 32
elements is available in the display area. The element area is
four dot-clocks wide by six lines high.
The 128 x 96 Color Graphics Mode (Graphics Three C) The 128 x 96 color graphics mode generates a display 128
elements wide by 96 elements high. Each element may be
one of four colors. A 3K x 8 display memory is required.
Each pictel equals two dot-clocks by two scan lines.
Alpha Semigraphic-6 Mode - The alpha semigraphic-6
mode maps six 4 x 4 dot elements into the standard 8 x 12
dot alphanumeric box, pro'!iding a screen density of 64 x 48
elements. Six bits are used to generate this map and two
data bits may be used to select one of four colors in the
display box. The element area is four dot-clocks wide by four
lines high.
The 128x 192 Graphics Mode (Graphics Three R) - The
128 x 192 graphics mode generates a display matrix 128
elements wide by 192 elements high. Each element may be
either On or Off, but the On elements may be one of two·
colors, selected with the color set select pin. A 3K x 8 display
memory is required. Each pictel equals two dot-clocks by
one scan line.
Full QraphicMode
There are eight full graphic modes available from the VDG.
These modes require 1K to 6K bytes of memory. The eight full
graphic modes include an outside color border in one of two
colors, depending upon the color set select (CSS) pin. The
CSS pin selects one of two sets of four colors in the four color
graphic modes.
128 x 192 Color Graphics Mode (Graphics Six C) - The
128 x 192 color graphics mode generaies a display 128
elements wide by 192 element high. Each element may be
one of four colors. A 6K x 8 display memory is required.
Each pictel equals two dot-clocks by one scan line.
The 64 x 64 Color Graphics Mode (Graphics One C) The 64 x 64 color graphics mode generates a display matrix
64 elements wide by 64 elements high. Each element may
be one of four colors. A 1K x 8 display memory is required.
Each pictel equals four dot-clocks by three scan lines.
The 256 x 192 Graphics Mode (Graphics Six R) - The
256 x 192 graphics mode generates a display 256 elements
wide by 192 elements high. Each element may be either On
or Off, but the On elements may be one of two colors,
selected with the color set select pin. A 6K x 8 display
memory is required. Each pictel equals on·e dot-clock by one
scan line.
The 128 x 64 Graphics Mode (Graphics One R) - The 128
x 64 graphics mode generates a matrix 128 elements wide
by 64 elements high. Each element may be either On or Off.
However, the entire display may be one of two colors,
5·198
F6847
Table 1
Table 2
Mode Control Inputs
A/G
A/S
INT/EXT
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
X
X
X
X
X
X
X
X
0
0
1
1
0
1
X
X
X
X
X
X
X
X
INV GM2 GM1 GMo
0
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
1
1
1
1
X
X
X
X
X
X
0
0
1
1
0
0
1
1
Alpha/Graphic Mode Selected
X
X
X
X
X
X
0
Internal Alphanumeric
Internal Alphanumeric Inverted
External Alphanumeric
External Alphanumeric Inverted
Alpha Semigraphic-4
Alpha Semigraphic-6
64 x 64 Color Graphic
128 x 64 Graphic
128 x 64 Color Graphic
128 x 96 Graphic
128 x 96 Color Graphic
128 x 192 Graphic
128 x 192 Color Graphic
256 x 192 Graphic
1
0
1
0
1
0
1
Summary of Major Modes
Memory
Colors
Alphanumeric (Internal)
Title
512 x 8
2
Alphanumeric '(External)
512 x 8
2
Alpha Semigraphic-4
512 x 8
8
Box----m---Element
Alpha Semigraphic-6
512 x 8
4
Box ---§}--Element
64 x 64 Color Graphic
1K x 8
4
128 x 64 Graphic'
1K x 8
2
128 x 64 Color Graphic
2K x 8
4
128 x 96 Graphic'
1.5K x 8
2
128 x 96 Color Graphic
3K x 8
4
128 x 192 Graphic'
3K x 8
2
128 x 192 Color Graphic
6K x 8
4
256 x 192 Graphic'
6K x 8
2
-Graphic mode turns
each element on or off.
The color may be one
of two.
5·199
Display Elements
Matrix 64 x 64
Elements
Matrix 128
Elements Wide by
64 Elements High
Matrix 128
Elements Wide by
96 Elements High
Matrix 128
Elements Wide by
192 Elements High
Matrix 256
Elements Wide by
192 Elements High
•
Table 3
Detailed Description of VDG Modes
Color
VDG Pins
MS
AlG
AlS
INT/&XT
GM2
GMt
GMO
ess
INV
0
0
t
1
0
0
0
X
X
Character Color
!
Green
Black
I Black
I Green
Background
Border
Black
------t----- , - - - -
X
0
t
t
Orange
Black
I Black
I Orange
Green
Black
I Black
I Green
Black
I
0
0
t
1
0
0
t
X
X
---
X
0
t
t
t
0
t
0
X
X
X
X
X
C2
1
1
t
1
1
L,
0
1
1
1
0
t
1
X
X
X
X
1
0
t
t
t
t
t
0
Ct
Co
X
X
X
0
0
0
0
t
t
0
t
0
1
0
0
t
t
0
0
t
t
1
0
t
0
t
C,
Co
1
X
X
0
0
0
X
X
0
X
X
0
0
t
t
0
t
0
Ct
0
0
Co
0
t
0
t
0
0
t
t
X
t
L,
0
0
t
1
X
X
0
0
X
t
0
1
t
X
X
0
t
X
0
1
0
1
1
X
X
0
t
t
X
t
0
1
t
X
X
t
0
0
X
t
0
t
t
X
X
t
0
t
X
t
0
1
t
t
t
X
X
X
X
t
t
t
1
0
1
X
Black
Color
Black
Green
Yellow
Blue
Red
Cyan
Magenta
Orange
Color
Black
Green
1
Yellow
0
t
Blue
Red
Black
Buff
Cyan
Magenta
Orange
1
1
Black
Buff
Color
Green
Black
Green
Yellow
Blue
Red
0
t
0
Buff
Cyan
1
Orange
Magenta
Color
Black
Green
1----Buff
Green
1------------ 1----0
t
1
1
0
0
t
t
1
t
Black
I Orange
I
L,
0
1
t
I
Orange
Black
t
t
0
Black
--L ____ 1 - - - - -
Same Color as
Graphics One C
Same Color as
Graphics One A
Black
Buff
Buff
Green
r----Bulf
Green
----Buff
Green
Same Color as
Graphics One C
-----
Same Color as
Graphics One R
-----
Same Color as
Graphics One C
Buff
Green
Buff
Green
-----
t
Bulf
0
Green
t
X
t
5-200
Same Color as
Graphics One R
f----Buff
Table 3
Detailed Description of VDG Modes (Cont.)
TV Screen
VOG Data Bus
Comments
Detail
Display Mode
The mternal alphanumeric mode uses an Internal
32 Characters
in Columns
8 Dots
--1
I-
'-[g-~
120015
16 Characters
In Rows
32 Characters
in Columns
16 Characters
In Rows
character generator that contains the followmg
five dot by seven dol characters: @ ABCDEF
~",
GHIJKLMNOPQRSTUVWXYZ [
_
Extra
>--s
ASCII Code
.
...
The external alphanumeric mode uses an external character generator as well as a row counter.
One Row of
Custom Characters
One
Element
Ls L,
48 Dtsplay Elements
In Rows
Ll
L3 L2
Thus, custom character fonts are graphic symbol
sets with up to 256 dtfferent 8 dot X 12 dot
"characters" that may be displayed,
The semigraphic-4 mode uses an internal
"coarse graphics" generator in which a rectangle
(8 dots by 12 dots) is divided into four equal parts.
The luminance of each part is determined by a
corresponding bit on the VOG data bus. The color
of illuminated parts is determined by three bits
64 Display Elements
Columns
In
64 Display Elements
m Columns
1 - SP
externally connected to the mode pins (AtG, AlS,
INT/EXT, GM2. GM1. GMO. CSS or lNV),
.•..
32 Display Elements
in Rows
I
!"#$%&'0·+,-.I0123456789:;<=>? The 6·bit
ASCII code leaves two bits free; these may be
I c, I col Lsi L,I L31 L21 Ll I Lol
Lo
64 Display Elements
in Columns
The semigraphic-6 mode is similar to the
semigraphic-4 mode with the following differences. The 8 dot by 12 dot rectangle tS dtvtded
into StX equal parts. Color tS determined by the
two remaining bits.
Tne graphics one C mode uses a maximum of
1024 bytes of display RAM i~ whicn one pair of
bits speCifies one picture element
64 Display Elements
in Rows
128 Display Elements
in Columns
The graphics one R mode uses a maximum of
1024 bytes at display RAM in which one bit
specifies one picture element.
64 Oisplay Elements
in Rows
128 Display Elements
in Columns
64 Display Elements
in Rows
The graphics two C mode uses a maximum of
2048 bytes of display RAM in which one pair of btt
speCifies one picture element.
128 Display Elements
in Columns
96 Display Elements
in Rows
The graphics two R mode uses a maximum of
1536 bytes of display RAM in which one bit
specifies one picture element
128 Display Elements
in Columns
96 Display Elements
in Rows
The graphics three C mode uses a maximum of
3072 bytes of display RAM In which one pair of
bytes specifies one picture element.
I E31 E21 E, I Eo I
128 Display Elements
in Columns
192 Display Elements
In Rows
The graphics three R mode uses a maximum of
3072 bytes of display RAM in which one bit
specifies on picture element
128 Display Elements
in Columns
192 Display Elements
in Rows
The graphiCS six C mode uses a maximum of 6144
bytes of display RAM in which one pair of bit
specifies one picture element
256 Display Elements
in Columns
192 Display Elements
in Rows
The graphics six R mode uses a maximum 016144
bytes of display RAM In which one bit specifies
one picture element.
5·201
•
F6847
Absolute Maximum Ratings
Supply Voltage, Vee
Input Voltage, any Pin, VIN
Operating Temperature Range, TA
Storage Temperature Range, TSTG
Power Dissipation, PD
DC Characteristics
Symbol
Stresses greater than those listed may cause permanent damage
to the device. This is a stress rating only, and functional operation of tae device
under these or any other conditions above those indicated in the operational
sections of this data sheet is not implied. Exposure to absolute maximum
-0.3 V, + 7.0 V
-0.3 V, + 7.0 V
O°C, +70°C
-65°C, +150°C
945 mW
rating conditions for extended periods may affect device reliability.
Vee = 5.0 V ±5%, VSS = 0.0 V, TA = O°C to + 70°C, unless otherwise noted
Characteristic
Min
Typ
Max
Unit
VIH
Input HIGH Voltage
CLK
Other Inputs
VSS + 2.4
VSS + 2.0
Vee
Vee
Vdc
VIL
Input LOW Voltage
CLK
Other Inputs
VSS - 0.3
VSS - 0.3
VSS + 0.4
VSS + 0.8
Vdc
lin
Input Leakage Current
CLK, GMO-GM2, INV, INT/EXT, MS,
VSS, DDO-DD7, AlS, A/G
2.5
!L Adc
ILO
Three-State (OFF State) Input
Current DAo-DA12
10
!L Adc
VOH
Outp~HIGH
Voltage
RP, HS, FS
Conditions
2.4
Vdc
CLoad = 30 pF
ILoad = -100 !LA
2.4
Vdc
CLoad = 55 pF
ILoad = -100 !LA
VOH
Output HIGH Voltage
DAo-DA12
VOL
Output LOW Voltage
RP, HS, FS,
VSS + 0.4
Vdc
CLoad = 30 pF
ILoad = 1.6 mA
VOL
Output LOW Voltage
DAO-DA12
VSS + 0.4
Vdc
CLoad = 55 pF
ILoad = 1.6 mA
IOH
Output HIGH Current (Sourcing)
All Outputs (Except cPA, cPB, Y,
and CHB)
IOL
Output LOW Current (Sinking)
All Outputs (Except cPA, cPB, Y,
and CHB
CIN
Input Capacitance
All Inputs
VR
Chroma Bias Voltage
0.3 Vee
Icc
Supply Current
90
-100
!LAdc
VOH= 2.4V
1.6
mAdc
VOL = 0.4 Vdc
7.5
5-202
pF
Vdc
114
mAdc
VIN = 0
TA = 25°C
f = 1.0 MHz
CLoad = 20 pF
RLoad = 200 k!1
Vec = 4.75 - 5.25 V
F6847
DC Characteristics (Cont.)
Symbol
VCepA
VCepB
Vy
VWL
VWM
VWH
Typ
Max
Unit
Conditions
VR + 0.1 VCC
VR
VR - 0.1 VCC
Vdc
CLoad = 20 pF
RLoad = 200 kn
See Figure 2
Chroma 1>B Voltage
Vo
VBurst
VLO
VR + 0.1 Vce
VR
VR - 0.05 Vee
VR - 0.1 Vee
Vdc
CLoad = 20 pF
RLoad = 200 kn
See Figure 2
luminance Y Voltage
Vs
VBLANK
VBLAeK
0.2 Vee
0.75 Vs
0.7 Vs
Vdc
CLoad = 20 pF
RLoad = 200 kn
See Figure 2
Vdc
See Figure 2
..
~
0.62
0.5 Vs
0.38 Vs
Voltage White low
Voltage White Medium
Voltage White High
AC Characteristics
Symbol
Min
Characteristic
Chroma 1>A Voltage
VHI
Vo
VLO
Vee
=
5.0 V ±5%, TA
= O°C to
70°C
Characteristic
f
ClKdc
ClK Frequency
ClK Duty Cycle
tVA
tYB
Chroma Phase Delay
(Measured with Respect to Y Output)
1>A
1>B
Min
Typ
Max
Unit
3.579535
45%
3.579545
50%
3.579555
55%
MHz
200
200
ns
ns
Conditions
See Figure 3C
tty
Luminance Rise Time
luminance Fall Time
60
50
ns
ns
t rC1>A
ttC1>A
t rC1>B
ttC1>B
Chroma Rise and Fall Times
1>A Rise Time
1>A Fall Time
1>B Rise Time
1>B Fall Time
60
60
60
60
ns
ns
ns
ns
tWFS
Field Sync (FS) Pulse Width
14.6
ms
See Figure 3A
tWRP
tHSRP
Row Preset (RP)
Pulse Width
Delay from HS
0.98
0.98
iJ-s
iJ-S
See Figure 38
tWHS
Horizontal Sync (HS)
4.9
iJ-s
See Figure 38
try
5·203
See Figure 3D
See Figure 3D
II
F6847
Fig. 2 Video and Chrominance Relationships Output Waveform
Lett Border
~
Sync
Blank
Black
_______________________
A~~;:!~eo
______________________
Right Border
~
AIG
v
Sync
AIG
+ A/G -
II
CSS
o ~_;s·
L(Bur.'i.
L--I
.......II
....L...I_ _
"B
Removed
for AJG • CSS • GMO)
Fig. 3 Timing Diagrams
b. Row Preset
a. Field Sync
FS---,
Leading Edge of
Vert. Blanking
t WHS
HS----..
~----------'WFS----------~
d. Video and Fall Times
c. Chroma Phase Delay
Level #2
v - -_ _ _ _ _ _....J
v
Level #2
"A _________-+_J
"B
"B --------'
5·204
F6847
Ordering Information
Order Code
Temperature Range
F6847P, S
P = Plastic Package
S = Ceramic Package
II
5·205
F6847
5-206
F6850/F68A50/F68B50
Asynchronous
Communications Interface
Adapter (ACIA)
Microprocessor Product
Description
The F6850 Asynchronous Communications Interface Adapter
(ACIA) provides the data formatting and control to interface
serial asynchronous data communications information to
bus-organized systems, such as the F6800 microprocessing
unit (MPU).
Logic Symbol
22
10
11
Riw
RTS
Tx DATA
IRQ
DCD
18
17
16
15
CS,
F6850
CS.
7
RS
23
14
13
II
Vee = Pin 12
Vss = Pin 1
Connection Diagram
24-Pin DIP
CTS
Vss
Rx DATA
Pin Functions
Rx DATA
Rx CLK
Tx CLK
CSo, CS1, CS2
RS
CTS
E
19
24
8- and 9-Bit Transmission
Optional Even and Odd Parity
Parity, Overrun, and Framing Error Checking
Programmable Control Register
Optional +1, +16, and +64 Clock Modes
Up to 1.0 Mbps Transmission
False Start Bit Deletion
Peripheral/Modem Control Functions
Double Buffered
One or Two Stop Bit Operation
00- 0 7
20
CSo
The bus interface of the F6850 includes select, enable read/write,
interrupt, and bus interface logic to allow data transfer over an
8-bit bidirectional data bus. The parallel data of the bus system is
serially transmitted and received by the asynchronous data
interface, with proper formatting and error checking. The
functional configuration of the ACIA is programmed via the data
bus during system initialization. A programmable control register
provides variable word lengths, clock division ratios, transmit
control, receive control, and interrupt control. For peripheral or
modem operation, three control lines are provided. These lines
allow the ACIA to interface directly with a 0-600 bps modem.
•
•
•
•
•
•
•
•
•
•
21
Bidirectional Data Lines
Receive Data Input
Receive Clock Input
Transmit Clock Input
Chip Select Inputs
Register Select Input
Clear-to-Send Input
Enable Input
Read/Write Input
Request-to-Send Output
Transmit Data Output
Interrupt Request Output
Data Carrier Detect Output
DCD
Rx ClK
Do
Tx ClK
D,
RTS
D.
Tx DATA
D3
iiffi
D4
CSo
D.
CS.
D6
CS,
D7
RS
RiW
Vee
(Top View)
5·207
F6850/F68A50/F68B50
Block Diagram
TRANSMIT CLOCK (Tx CLK) - - - - - - - - - ,
""'.,+'----.Il________
ENABLE (E) - - ..-----READIWRITE
(RIW) _
CHIP SELECT 0 (CSO) -
CHIP
SELECT
CHIP SELECT 1 ( CS 1) -
REA~~~RITE
CHIP SELECT 2 (Cs2) REGISTER SELECT (RS) _
CONTROL
1.J~~!!!'j-----" TRANSMIT DATA (Tx DATA)
r----
'-___J'•••
CLEAR-TO-SENO (ffi)
Do-
D.o.0._
01-
1--_ _ _
>
DATA
BUS
BUFFERS
' - - - - -.....- - - - - _ DATA CARRIER DETECT (OCO)
0506-
INTERRUPT REQUEST (IRQ)
+--±-_____. . .
r-..J...-"1-__
REQUEST-TO-SENO (RTS)
0-, -
RECEIVE CLOCK (Rx CLK) - - - - - - - - - - - - - _
Functional Description
Transmit
A typical transmitting sequence consists of reading the ACIA
status register either as a result of an interrupt or in turn in a
polling sequence. A character may be written into the transmit
data register if the status read operation has indicated that the
transmit data register is empty. This character is transferred to
a shift register, where it is serialized and transmitted from the
transmit data (Tx DATA) output preceded by a start bit and
followed by one or two stop bits. Internal parity (odd or even)
can be optionally added to the character, and occurs between
the last data bit and the first stop bit. After the first character is
written in the data register, the status register can be read
again to check for a transmit data register empty condition and
current peripheral status. If the register is empty, another
character can be loaded for transmission even though the first
character is in the process of being transmitted (because of
double buffering). The second character is transferred
automatically into the shift register when the first character
transmission is completed. This seq'uence continues until all
the characters have been transmitted.
At the bus interface, the ACIA appears as two addressable
memory locations. Internally, there are four registers: two
read-only and two write-only. The read-only registers are status
and receive data; the write-only registers are control and
transmit data. The serial interface consists of serial input and
output lines with independent clocks, and three
peripheral/modem control lines.
Power On/Master Reset
The master reset (CRo, CR1) should be set during system
initialization to ensure the reset condition and prepare for
programming the ACIA functional configuration when the
communications channel is required. Control bits CRs and CR6
should also be programmed to define the state of the
request-to-send (RTS) output whenever master reset is
utilized. The ACIA also contains internal power-on reset logic to
detect the power line turn-on transition and hold the chip in a
reset state to prevent erroneous output transitions prior to
initialization. This circuitry depends on clean power turn-on
transitions. The power-on reset is released by means of the
bus-programmed master reset, which must be applied prior to
operating the ACIA. After master resetting the ACIA, the
programmable control register can be set for a number of
options, such as variable clock divider ratios, variable word
length, one or two stop bits, and parity (even, odd, or none).
Receive
Data is received from a peripheral by means of the receive data
(Rx DATA) input. A divide-by-one clock ratio is provided for an
externally synchronized clock (to its data) while the divide-by-16
and -64 ratios are provided for internal synchronization. Bit
5-208
F6850/F68A50/F68B50
synchronization in the divide-by-16 and -64 modes is initiated by
the detection of 8 or 32 LOW samples, respectively, on the
receive data line. False start bit deletion capability ensures that a
full half bit of a start bit has been received before the internal clock
is synchronized to the bit time. As a character is being received,
parity (odd or even) is checked and the error indication made
available in the status register along with framing error, overrun
error, and receive data register full. In a typical receiving
sequence, the status register is read to determine if a character
has been received from a peripheral.lflhe receive data is full, the
character is placed on the 8-bit ACIA bus when a read data
command is received from the MPU. When parity has been
selected for an 8-bit word (seven bits plus parity), the receiver
strips the parity bit (07 = 0) so that data alone is transferred to the
MPU. This feature reduces MPU programming. The status
register can be read again to determine when another character
is available in the receive data register. The receiver is also
double buffered so that a character can be read from the data
register as another character is being received in the shift
register. The above sequence continues until all characters have
been received.
Chip Select (CSO. CS1. CS2)
These three high-impedance, TTL-compatible input lines are
used to address the ACIA. The ACIA is selected when CSo and
CS1 are HIGH and CS2 is LOW. Transfers 01 data to and from
the ACIA are then performed under the control of the E, R/W,
and RS signals.
Register Select (RS)
The register select line is a high-impedance input that is
TTL-compatible. A HIGH level is used to select the
transmit/receive data registers and a LOW level the
control/status registers. The R/W signal line is used in
conjunction with RS to select the read-only or write-only
register in each register pair.
Interrupt Request (IRQ)
Interrupt request is a TTL-compatible, open-drain (no internal
pull-up), active-LOW output that is used to interrupt the MPU.
The iRQ output remains LOW as long as the cause of the
interrupt is present and the appropriate interrupt enable within
the ACIA is set. The IRQ status bit, when HIGH, indicates that
the IRQ output is in the active state.
Input/Output Functions
The ACIA interfaces to the F6800 MPU through an 8-bit
bidirectional data bus, three chip select lines, a register select
line, an interrupt request line, read/write line, and enable line.
These signals, in conjunction with F6800 VMA output, permit
the MPU to have complete control over the ACIA.
Interrupts result from conditions in both the transmitter and
receiver sections of the ACIA. The transmitter section causes
an interrupt when the transmitter interrupt enabled condition is
selected (CRs • CRS), and the transmit data register empty
(TORE) status bit is HIGH. The TORE status bit indicates the
current status of the transmitter data register except when
inhibited by the CTS line being HIGH or the ACIA being
maintained in the reset condition. The interrupt is cleared by
writing data into the transmit data register. The interrupt is
masked by disabling the transmitter interrupt via CRs or CRs,
or by the loss of CTS, which inhibits the TORE status bit. The
receiver section causes an interrupt when the receiver interrupt
enable is set and the receive data register full (RORF) status
bit is HIGH, an overrun has occurred, or the data carrier detect
(OCO) line has gone HIGH. An interrupt resulting from the
RORF status bit can be cleared by reading data or resetting the
ACIA: Interrupts caused by overrun or loss of oeo are cleared
by reading the status register after the error condition has
occurred and then reading the receive data register or resetting
the ACIA. The receiver interrupt is masked by resetting the
receiver interrupt enable.
ACIA Bidirectional Data (Do - 07)
The bidirectional data lines (00-07) allow for data transfer
between the ACIA and the MPU. The data bus output drivers
are 3-state devices that remain in the high-impedance (OFF)
state except when the MPU performs an ACIA read operation.
ACIA Enable (E)
The enable signal (E) is a high-impedance, TTL-compatible
input that enables the bus input/output data buffers and clocks
data to and from the ACIA. This signal normally is a derivative
of the F6800 <1>2 clock.
Read/Write (R/W)
The read/write line is a high-impedance input that is
TTL-compatible and is used to control the direction of data flow
through the ACIA input/output data bus interface. When R/W is
HIGH (MPU read cycle), ACIA output drivers are turned on and
a selected register is read. When it is LOW, the ACIA output
drivers are turned off and the MPU writes into a selected
register. Therefore, the
signal is used to select read-only
or write-only registers within the ACIA.
Clock Inputs
Separate high-impedance, TTL-compatible inputs are provided
for clocking of transmitted and received data. Clock
frequencies of 1, 16, or 64 times the data rate may be selected.
Riw
Transmit Clock (Tx ClK)
The transmit clock input is used for the clocking of transmitted
data. The transmitter initiates data on the negative transition of
the clock.
5-209
5
F6850/F68A50/F68B50
Receive Clock (Rx ClK)
The receive clock input is used for synchronization of received
data. (In the + 1 mode, the clock and data must be
synchronized externally.) The receiver samples the data on the
positive transition of the clock.
Transmit Data Register (TOR)
Data is written into the transmit data register during the
negative transition of the E (Enable) pulse when the ACIA has
been addressed with RS HIGH and .R/W LOW. Writing data
into the register causes the TDRE bit in the status register to
go LOW. Data can then be transmitted. If the transmitter is
idling and no character is being transmitted, the transfer takes
place within one bit time of the trailing edge of the write
command. If a character is being transmitted, the new data
character commences as soon as the previous character is
complete. The transfer of data causes the TDRE bit to indicate
empty.
Serial Input/Output lines
Receive Data (Rx DATA)
The receive data line is a high-impedance, TTL-compatible input
through which data is received in a serial format. Synchronization
with a clock for detection of data is accomplished internally when
clock rates of 16 or 64 times the bit rate are used.
Receive Data Register (RDR)
Data is automatically transferred to the empty receive data
register (RDR) from the receiver deserializer (a shift register)
upon receiving a complete character. This event causes the
receive data register full (RDRF) bit in the status buffer to go
HIGH (full). Data may then be read through the bus by
addressing the ACIA and selecting the RDR with RS and R/W
HIGH when the ACIA is enabled. The non-destructive read
cycle causes the RDRF bit to be cleared to empty although the
data is retained in the RDR. The status is maintained by the
RDRF bit to indicate whether or not the data is current. When
the receive data register is full, the automatic transfer of data
from the receiver shift register to the data register is inhibited
and the RDR contents remain valid, with its current status
stored in the status register.
Transmit Data (Tx DATA)
The transmit data output line transfers serial data to a modem or
other peripheral.
Peripheral/Modem Control
The ACIA includes several functions that permit limited control of
a peripheral or modem. The functions included are clear-to-send,
request-to-send and data carrier detect.
Clear-te-Send (ill)
This high~impedance, TTL-compatible input provides automatic
control of the transmitting end of a communications link via the
modem clear-to-send active-LOW output by inhibiting the
transmit data register empty (TDRE) status bit.
Request-to-Send (RTS)
The request-to-send output enables the MPU to control a
peripheral or modem via the data bus. The RTS output
corresponds to the state of control register bits CR5 and CRa.
When CRa == 0 or both CR5 and CRa = 1, the RTS output is LOW
(the active state.) This output can also be used for data terminal
ready (DTR).
.
Control Register
The ACIA control register consists of eight bits of write-only
buffer that are selected when RS and R/Ware LOW. This
register controls the function of the receiver, transmitter,
interrupt enables, and the request-to-send peripheral/modem
control output.
Data Carrier Detect (DCD)
This high-impedance, TTL-compatible input provides automatic
control, such as in the receiving end of a communications link, by
means of a modem Data Carrier Detect output. The DCD input
inhibits and initializes the receiver section of the ACIA when
HIGH. A LOW-to-HIGH transition of DCD initiates an interruptto
the MPU to indicate the occurrence of a loss of carrier when the
receive interrupt enable bit is set. The RxCLK must be running for
proper DCD operation.
Counter Divide Select Bits (CRo and CR1)
,
The counter divide select bits (CRo and CRt) determine the
divide ratios utilized in both the transmitter and receiver
sections of the ACIA. Additionally, these bits are used to
provide a master reset for the ACIA that clears the status
register (except for external conditions'on CTS and DCD) and
initializes both the receiver and transmitter. Master reset does
not affect other control register bits. Note that after power-on or
a power fail/start, these bits must be set HIGH to reset the
ACIA. After resetting, the clock divide ratio may be selected,
ACIA Registers
The block diagram for the ACIA indicates the internal registers on
the chip that are used for the status, control, receiving, and
transmitting of data. The content of each of the registers is
summarized in Table 1.
5-210
F6850/F68A50/F68B50
Table 1 Definition of ACIA Register Contents
Buffer Address
Data
Bus Line
Number
RS· R/W
Transmit Data
Register
RS·R/W
Receive Data
Register
RS· R/W
Control Register
RS·R/W
Status Register
(Write Only)
(Read Only)
(Write Only)
(Read Only)
--
0
Data Bit 0'
Data Bit 0
Counter Divide Select 1 (CRa)
Receive Data Register Full (RDRF)
1
Data Bit 1
Data Bit 1
Counter Divide Select 2 (CR,)
Transmit Data Register Empty (TORE)
2
Data Bit 2
Data Bit 2
Word Select 1 (CR2)
Data Carrier Detect (DCD)
3
Data Bit 3
Data Bit 3
Word Select 2 (CR3)
Clear-to-Send (CTS)
4
Data Bit 4
Data Bit 4
Word Select 3 (CR4)
Framing Error (FE)
5
Data Bit 5
Data Bit 5
Transmit Control 1 (CR s)
Receiver Overrun (OVRN)
6
Data Bit 6
Data Bit 6
Transmit Control 2 (CRe)
Parity Error (PE)
7
Data Bit
Data Bit 7"
Receive Interrupt Enable (CR 7 )
Interrupt Request (IRQ)
~
'Leading bit
LSB
~
Bit
a
r"
"Data bit is zero in 7-bit plus parity modes.
"-Data bit is "don't care" in 7-bit plus parity modes.
request-to-send (RTS) output, and the transmission of a break
level (space). The following encoding format is used:
These counter select bits provide for the following clock divide
ratios:
CR1
CRo
Function
CR6
CRS
Function
0
-i-1
-i-16
-i-64
Master Reset
o
o
0
RTS = LOW, Transmitting Interrupt Disabled
RTS = LOW, Transmitting Interrupt Enabled
RTS = HIGH, Transmitting Interrupt Disabled
RTS = LOW, Transmits a Break Level on the
Transmit Data Output. Transmitting
Interrupt Disabled.
0
0
0
Word Select Bits (CR2. CR3 and CR4)
The word select bits are used to select word length, parity, and
the number of stop bits. The encoding format is as follows:
CR4
CR3
CR2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Receive Interrupt Enable Bit (CR7)
The following interrupts are enabled by a HIGH level in bit
position 7 of the control register (CRl): receive data register
full, overrun, or a LOW-to-HIGH transition on the data carrier
detect (DCD) signal line.
Function
7
7
7
7
8
8
8
8
Bits
Bits
Bits
Bits
Bits
Bits
Bits
Bits
1
o
+ Even Parity + 2 Stop Bits
+ Odd Parity + 2 Stop Bits
+ Even Parity + 1 Stop Bit
+ Odd Parity + 1 Stop Bit
+ 2 Stop Bits
+ 1 Stop Bit
+ Even Parity + 1 Stop Bit
+ Odd Parity + 1 Stop Bit
Status Register
Information on the status of the ACIA is available to the MPU
by reading the ACIA status register. This read-only register is
selected when RS is LOW and Riw is HIGH. Information
stored in this register indicates the status of the transmit data
register, the receive data register and error logic, and the
peripheral/modem status inputs of the ACIA.
Receive Data Register Full (RDRF). Bit 0
Receive data register full indicates that received data has been
transferred to the receive data register. The RDRF bit is
cleared after an MPU read of the receive data register or by a
master reset. The cleared or empty state indicates that the
Word length, parity select, and stop bit changes are not
buffered and therefore become effective immediately.
Transmitter Control Bits (CRs and CR6)
Two transmitter control bits provide for the control of the
interrupt from the transmit data register empty condition, the
5·211
II
F6850/F68A50/F68B50
Parity Error (PE). Bit 6
The parity error flag indicates that the number of HIGHs (l's) in
the character does not agree with the preselected odd or even
parity. Odd parity is defined to be when the total nu mber of
ones is odd. The parity error indication is present as long as
the data character is in the RDA. If no parity is selected, both
the transmitter parity generator output and the receiver parity
check results are inhibited.
contents of the receive data register are not current. Data
carrier detect being HIGH also causes RDRF to indicate empty.
Transmit Data Register Empty (TORE). Bit 1
The transmit data register empty bit being set HIGH indicates
that the transmit dataregister contents have been transferred
and that new data may be entered. The LOW state indicates
that the register is full and that transmission of a new character
has not begun since the last write data command.
Interrupt Request (IRQ). Bit 7
The IRQ bit indicates the state of the I RQ output. Any interrupt
condition with its applicable enable is indicated in this status
bit. Any time the IRQ output is LOW, the IRQ bit is HIGH to
indicate the interrupt or service request status. The IRQ bit is
cleared by a read operation to the receive data register or a
write operation to the transmit data register.
Data Carrier Detect (DCD). Bit 2
The data carrier detect bit is HIGH when the DCD input from a
modem has gone HIGH to indicate that a carrier is not present.
This bit going HIGH causes an interrupt request to be
generated when the receive interrupt enable is set. It remains
HIGH after the DCD input is returned LOW until cleared by
reading first the status register and then the data register, or
until a master reset occurs. If the DCD input remains HIGH
after read status and read data or master reset has occurred,
the interrupt is cleared, and the DCD status bit remains HIGH
and will follow the DCD input.
Clear-to-Send (CTS). Bit 3
The clear-to-send bit indicates the state of the clear-to-send
input from a modem. A LOW CTS indicates that there is a
clear-to-send from the modem. In the HIGH state, the transmit
data register empty bit is inhibited and the clear-to-send status
bit is HIGH. Master reset does not affect the clear-to-send
status bit.
Framing Error (FE). Bit 4
Framing error indicates that the received character is
improperly framed by a start and a stop bit and is detected by
the absence of the first stop bit. This error indicates a
synchronization error, faulty transmission, or a break condition.
The framing error flag is set or reset during the receive data
transfer titne. Therefore, this error indicator is present
throughout the time that the associated character is available.
Receiver Overrun (OVRN). Bit 5
Overrun is an error flag that indicates that one or more
characters in the data stream were lost. That is, a character or
a number of characters were received but not read from the
receive data register (RDR) prior to subsequent characters
being received; The overrun condition begins at the midpoint of
the last bit of the second character received in su,;cession
without a read of the RDR having occurred. The overrun does
not occur in the status register until the valid character prior to
overrun has been read. The RDRF bit remains set until the
overrun is reset. Character synchronization is maintained
during the overrun condition. The overrun indication is reset
after the reading of data from the receive data register or by a
master reset.
5-212
F6850/F68A50/F68B50
Absolute Maximum Ratings
This device contains circuitry to protect the inputs against damage due to high static
Supply Voltage
Input Voltage
Operating Temperature - TL, TH
F6850, F68A50, F68B50
F6850C, F68A50C
F6850Dl
F6850DM
Storage Temperature Range
Thermal Resistance
Ceramic
Plastic
DC Characteristics
Symbol
Vee
=
-0.3 V,
-0.3 V,
+7.0 V
+7.0 V
O"C,
-40"C,
-5SC,
-55'C,
-55'C,
+70'C
+85'C
+85'C
+125'C
+150'C
voltages or electrical fields; however it is advised that normal precautions be taken
I
to avoid application of any voltage higher than maximum rated voltages to this highimpedance circuit.
60"C/W
120"C/W
5.0 V ±5%, VSS
Characteristic
= 0,
TA
= TL to TH,
unless otherwise noted
Signal
Min
Typ
Max
Unit
Vee
V
Condition
VIH
Input HIGH Voltage
VIL
Input lOW Voltage
0.8
V
liN
Input leakage Current
R/W, CSo, CS1, CS2, RS,
Rx DATA, Rx ClK, CTS, DCD
1.0
2.5
p.,A
VIN
= 0 to
ITSI
3-State Input Current
(OFF State)
00- 0 7
2.0
10
p.,A
VIN
= 0.4 to
VOH
Output HIGH Voltage
00- 0 7
2.4
Tx DATA, RTS
2.4
VOL
Output lOW Voltage
ILOH
Output leakage Current
Po
Power Dissipation
CIN
Input Capacitance
2.0
-0.3
IRQ
00- 0 7
E, Tx ClK, Rx ClK, R/W,
RS, Rx DATA, CSo, CS1,
CS2, CTS, DCD
COUT
Output Capacitance
RTS, Tx DATA
IRQ
5-213
V
5.25 V
2.4 V
ILoad = -205 p.,A,
Enable Pulse Width
< 25 p.,s
ILoad = -100 p.,A,
Enable Pulse Width
< 25 p.,s
ILoad = 1.6 mA,
Enable Pulse Width
< 25 p.,s
0.4
V
1.0
10
p.,A
300
525
mW
10
7.0
12.5
7.5
pF
VIN = 0, TA = 25°C,
f = 1.0 MHz
10
5.0
pF
VIN = 0, TA = 25'C,
f = 1.0 MHz
VOH
= 2.4 V
F6850/F68A50/F68B50
AC Characteristics
Vcc
= 5.0 V
±5%, Vss
= 0,
TA
= TL to TH,
unless otherwise noted
F68S0
Characteristic
Symbol
Min
F68ASO
Max
Min
PWCL
Minimum Clock Pulse Width, LOW
+16, +64 Modes
600
450
PWCH
Minimum Clock Pulse Width, HIGH
+16, +64 Modes
600
450
fc
Clock Frequency
+1 Mode
+16, +64 Modes
Clock-to-Data Delay for Transmitter
tROS
Receive Data Set-up Time
+1 Mode
250
IROH
Receive Data Hold Time
+1 Mode
250
tlR
Interrupt Request Release Time
tRTS
Request-to-Send Delay Time
tr, tl
Input Transition Times (Except Enable)
Min
Unit
Condition
280
ns
Figure 1
280
ns
Figure 2
600
460
540
100
Max
1000
1500
750
1000
500
800
tTDO
F68BSO
Max
30
100
30
kHz
ns
Figure 3
ns
Figure 4
ns
Figure 5
1.2
0.9
0.7
IJ-S
Figure 6
560
480
400
ns
Figure 6
1.0
0.5
0.25
IJ-s
Note
Note
1.0 p.8 or 10% of the pulse wid1h, whichever is smailer
Bus Timing Characteristics
Read (Figures 7 and 9)
F68S0
Symbol
Characteristic
lcycE
Enable Cycle Time
Min
F68ASO
Max
1.0
Min
F68BSO
Max
Min
Max
0.500
0.666
Unit
IJ-S
PWEH
Enable Pulse Width, HIGH
0.45
PWEL
Enable Pulse Width, LOW
0.43
0.28
0.21
IJ-S
tAS
Set-up Time, Address, and R/W Valid to
Enable· Positive Transition
160
140
70
ns
tOOR
Data Delay Time
IH
Data Hold Time
10
tAH
Address Hold Time
10
tEr, tEl
Rise and Fall Time for Enable Input
25
0.28
25
0.22
220
320
10
180
10
10
25
25
ns
ns
10
25
IJ-S
ns
25
ns
Write (Figures 8 and 9)
lcycE
Enable Cycle Time
1.0
PWEH
Enable Pulse Width, HIGH
0.45
PWEL
Enable Pulse Width, LOW
0.43
0.28
0.21
IJ-s
tAS
Set-up Time, Address, and R/W Valid to
Enable Positive Transition
160
140
70
ns
tosw
Data Set-up Time
195
80
60
ns
IH
Data Hold Time
10
10
10
ns
tAH
Address Hold Time
.10
tEr, tEl
Rise and Fall Time for Enable Input
0.500
0.666
25
0.28
25
10
25
5-214
0.22
IJ-s
25
10
25
IJ-S
ns
25
ns
F6850/F68A50/F68B50
Fig. 1
Clock Pulse Width, LOW State
Fig. 5
Receive Data Hold Time (+1 Mode)
~-------'
TX elK
OR
t
2.0
RXCl~1
v
RX eLK
~
.,..,.,...;OVX,---l-tRDH
- - - : - 2.
Fig.2
RX OATA
Clock Pulse Width, HIGH State
0.8 V
Fig. 6
TX elK
OR
RX elK
Request-to-Send Delay and Interrupt Request
Release Times
PWCH
Fig. 3
E\~08V
Transmit Data Output Delay
X
_
2.4 V
---'"--r-
____~~J
_____________
~O~4~V
2.4 V
TX DATA
Fig. 7
Fig.4
Bus Read Timing Characteristics
(Read Information from ACIA)
Receive Data Set-up Time (+1 Mode)
~2.0V
RXDATA~~o~.•~v______________________
--I t----
E
tRDSU
RS,ES,RiW
RX ClK
0 •• V
DATA BUS
5·215
•
F6850/F68A50/F68B50
Fig. 8
Bus Write Timing Characteristics
(Write Information into ACIA)
1 - - - - - 'cyce -----+I
Fig. 9
Bus Timing Test Loads
Load A (00-07. RTS. Tx DATA)
5.0
TEST POINT
=
C 130 pF FOR~-o.,
C ,= 30 pF FOR RTS AND Tx DATA
R = 11,7 kIl FOR~-o.,
R = 24 kIl FOR RTS AND Tx DATA
I!
C
R
-::-
Load B (IRQ Only)
5.0 V
TEST POINT
d''·'1"
v
F6850/F68A50/F68B50
Ordering Information
Speed
Order Code
Temperature Range
1.0 MHz
F6850P,S
F6850CP,CS
F6850DL
F6850DM
O°C
-40°C
-55°C
-55°C
1.5 MHz
F68A50P,S
F68A50CP,CS
O°C to +70°C
-40°C to +85°C
2.0 MHz
F68B50P,S
P :::: Plastic package, S
=
to
to
to
to
+70°C
+85°C
+85°C
+125°C
O°C to +70°C
Ceramic package
5·217
F6850/F68A50/F68B50
5-218
F68521F68A52/F68B52
Synchronous Serial
Data Adapter
Microprocessor Product
Logic Symbol
Description
The F6852 Synchronous Serial Data Adapter (SSDA)
provides a bidirectional serial interface for synchronous
data information interchange. It contains interface
logic for simultaneously transmitting and receiving
standard synchronous communications characters
in bus-organized systems, such as the F6800 microprocessor systems.
10
11
14
13
Ax DATA
Tx DATA
Rx elK
The bus interface of the F6852 includes Select, Enable,
Read/Write, Interrupt, and bus interface logic to allow
data transfer over an 8-bit bidirectional data bus. The
parallel data of the bus system is transmitted serially
and received by the synchronous data interface with
synchronization, fill character insertion/deletion, and
error checking. The functional configuration of the
SSDA is programmed via the data bus during system
initialization. Programmable control registers provide
control for variable word lengths, transmit control,
receive control, synchronization control, and interrupt
control. Status, timing, and control lines provide
peripheral or modem control.
Tx elK
IRQ
RESET
TUF
24
eTS
23
oeD
SM/D'ffi
22 21 20 19 18 17 16 15
Vss=Pin'
•
_V_c_C_=_p_i_n_'_2_______________________________________
Connection Diagram
24-Pln DIP
Vss
Typical applications include floppy disk controllers,
cassette or cartridge tape controllers, data communications terminals, and numerical control systems.
Rx DATA
Rx elK
Tx elK
SM/OTR
• Programmable Interrupts from Transmitter,
Receiver, and Error Detection Logic
• Character Synchronization on 1 or 2 SYNC Codes
• External Synchronization Available for Parallel-Serial
Operation
• Available Speeds: 1.0 MHz for the F6852, 1.5 MHz for
the F68A52, and 2.0 MHz for the F68B52
• Programmable SYNC Code Register
• Up to 600K BPS Transmission
• Peripheral/Modem Control Functions
• 3 Bytes of FIFO Buffering on Both Transmit and
Receive
• 7-, 8-, or 9-Bit Transmission
• Optional Even and Odd Parity
• Parity, Overrun, and Underflow Status
Tx DATA
TUF
05
iiESET
06
RS
My
Vee
(Top View)
5·219
F6852/F68A52/F68B52
Pin Names
Rx DATA
Rx ClK
Tx ClK
SM/DTR
Tx DATA
IRQ
TUF
RESET
CS
RS
CTS
DCD
00-07
E
R/W
Vss
Vee
Receive Data Input
Receive Clock Input
Transmit Clock Input
Sync Match/Data Terminal Ready Output
Transmit Data Output
Interrupt Request Output
Transmitter Underflow Output
Reset Input
Chip Select Input
Register Select Input
Clear-to-Send Input
Data Carrier Detect Input
Bidirectional Data Lines
Enable (System <1>2 Clock) Input
Read/Write Input
Ground Input
+5 V Power Supply Input
Block Diagram
ENABLE
READ/Wii'ifE:
1----------- 6~~~SMIT
CHIP SELECT
r~J:1~:;~-------~---o~
REGISTER
SELECT
TRANSMITTER
UNDERFLOW
~;---------- CLEAR-TO-SEND
~=~3~~E==~===::r;:;;;;;;;;:;;;;, 5'ETECT
Do
0,
INTERRUPT
LOGIC
..
DATA CARRIER
INTERRUPT
REQUEST
r.~~;;;-' '+~~~~---l--- RECEIVE
I'~~~~~::::::::::~~::::~
1........-+--+-+_______
~~-r--~
DATA
RECEIVE
CLOCK
SYNC
1-----..... MATCHI
DATA TERMINAL
READY
5·220
F6852/F68A52/F68852
Device Operation
At the bus interface, the SSDA appears as two
addressable memory locations. Internally, ther·e are
seven registers: two read-only and five write-only
registers. The read-only registers are status and receive
data; the write-only registers are control 1, control 2,
control 3, sync code, and transmit data. The serial
interface consists of serial input and output lines with
independent clocks, and four peripheral/modem
control lines.
ITUF). The transmitter and receiver each have individual
clock inputs, allowing simultaneous operation under
separate clock control. Signals to the microprocessor
are the data bus and Interrupt Request (IRQ).
Initialization
During a power-on sequence, the SSDA is reset via the
RESET input and internally latched in a' reset condition to
prevent erroneous output transitions. The sync code
register, control register 2, and control register 3 should
be programmed prior to the programmed release of the
transmitter and/or receiver reset bits; these bits in
control register 1 should be cleared after the RESET line
has gone HIGH.
Data to be transmitted is transferred directly into the
3-byte transmit data first-in, first-out (FIFO) register from
the data bus. Availability of the input to the FIFO is
indicated by a bit in the status register; once data is
entered, it moves through the FIFO to the last empty
location. Data at the output of the FIFO is automatically
transferred from the FIFO to the transmitter shift register
as the shift register becomes available to transmit the
next character. If data is not available from the FIFO
(underflow condition), the transmitter shift register is
automatically loaded with either a sync code or an all"1s" character. The transmit section may be programmed to append even, odd, or no parity to the
transmitted word. An external Clear-to-Send (CTS) control
line is provided to inhibit the transmitter without
clearing the FIFO.
Transmitter Operation
•
Data is transferred to the transmitter section in parallel
form by means of the data bus and transmit data FIFO.
The transmit data FIFO is a 3-byte register whose status
is indicated by the transmitter data register available
(TDRA) status bit and its associated interrupt enable bit.
Data is transferred through the FIFO on negative edges
of Enable IE) pulses. Two data transfer modes are
provided in the SSDA. The 1-byte transfer mode
provides for writing data to the transmitter section I and
reading from the receiver section) one byte at a time.
The 2-byte transfer mode provides for writing two data
characters in succession.
Serial data is accumulated in the receiver based on the
synchronization mode selected. In the external sync
mode, used for parallel-serial operation, the receiver is
synchronized by the Data Carrier Detect I DCD) input
and transfers successive bytes of data to the input of
the receiver FIFO. The single-sync-character mode
requires that a match occur between the sync code
register and one incoming character before data transfer
to the FIFO begins. The two-sync-character mode
requires that two sync codes be received in sequence to
establish synchronization. Subsequent to synchronization
in any mode, data is accumulated in the shift register
and parity is optionally checked. An indication of parity
error is carried through the receiver FIFO with each
character to the last empty location. Availability of a
word at the FIFO output is indicated by a bit in the
status register, as is a parity error.
Data will automaiically transfer from the last register
location in the transmit data FIFO Iwhen it contains
data) to the transmitter shift register during the last half
of the last bit of t,he previous character. A character is
transferred into the shift register by the Transmit Clock.
Data is transmitted LS8 first, and odd or even parity
can be optionally appended. The unused bit positions in
short word length characters from the data bus are
"don't cares". I Note: The data bus inputs may be
reversed for applications requiring the MSB to be
transferred first, e.g., IBM format for floppy disks;
however, care must be taken to program th.e control
registers properly - Table 1 will have its bit
positions reversed.).
When the shift register becomes empty, and data is not
available for transfer from the transmit data FIFO, an
underflow occurs, and a character is inserted into the
transmitter data stream to maintain character synchronization. The character transmitted on underflow will be
either a mark (all "1s") or the contents of the sync
code register, depending upon the state of the transmit
sync code on underf.low control bit. The underflow
condition is indicated by a pulse (= Tx ClK HIGH period)
on the Transmitter Underflow output (when in Tx Sync
on underflow mode). The Transmitter Underflow output
The SS DA and its internal registers are selected by the
address bus, Read/Write (R/Vil), and Enable control lines.
To configure the SSDA, control registers are selected
and the appropriate bits set. The status register is
addressable for reading status.
Other I/O lines, in addition to Clear-to-Send ICTS) and
Data Carrier Detect IDCD), include Sync Match/Data
Terminal Ready I SM/DTR) and Transmitter Underflow
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F6852/F68A52/F68B52
occurs coincident with the transfer of the last half of the
last bit preceding the underflow character. The underflow
status bit is set until cleared by means of the clear
underflow control bit. This output may be used in floppy
disk systems to synchronize write operations and for
appending CRCC.
code detection techniques require custom logic external
to the SSDA for character synchronization and use of
the parallel-to-serial I external sync I mode. I Note: The
receiver shift register is set to "1 s" when resel.i
Synchronization
The SSDA provides three operating modes with respect
to character synchronization: one-sync-character mode,
two-sync-character mode, and external sync mode. The
external sync mode requires synchronization and control
of the receiving section through the Data Carrier Detect
IDCD) input Isee Figure 7). This external synchronization could consist of direct line control from the
transmitting end of the serial data link or from external
logic designed to detect the start of the message block.
The one-sync-character mode searches on a bit-by-bit
basis until a match is achieved between the data in the
shift register and the sync code register. The match
indicates character synchronization is complete and will
be retained for message block. In the two-synccharacter mode, the receiver searches for the first sync
code match on abit-by-bit basis and then looks for a
second successive sync code character prior to
establishing character synchronization. If the second
sync code character is not received, the bit-by-bit
search for the first sync code is resumed.
Transmission is initiated by clearing the transmitter reset
bit in control register 1. When the transmitter reset bit is
cleared, the first full positive half-cycle of the Transmit
Clock will initiate the transmit cycle, with the
transmission of data or underflow characters beginning
on the negative edge of the Transmit Clock pulse that
started the cycle. If the transmit data FI FO was not
loaded, an underflow character will be transmitted
(see Figure 41.
The Clear-to-Send (CTS) input provides for automatic
control of the transmitter by means of external system
hardware; e.g., the modem CTS output provides the
control in a data communications system. The CTS
input resets and inhibits the transmitter section when
HIGH, but does not reset the transmit data FIFO. The
TDRA status bit is inhibited by CTS being HIGH in
either the one-sync-character or two-sync-character
mode of operation. In the external sync mode, TDRA is
unaffected by CTS in order to provide transmit data
FIFO status for preloading and operating the transmitter
under the control of the CTS input. When the
transmitter reset bit (Tx Rs) is set, the transmit data
FIFO is cleared and the TDRA status bit is cleared.
After one E clock has occurred, the transmit data FIFO
becomes available for new data with TDRA inhibited.
Sync codes received prior to the completion of
synchronization (one or two characters) are not
transferred to the receive data FIFO. Redundant sync
codes during the preamble or sync codes that occur
as "fill characters" can be automatically stripped from
the data, when the strip sync control bit is set, to
minimize system loading. The character synchronization
will be retained until cleared by means of the clear sync
bit, which also inhibits synchronization search when set.
Receiver Operation
Data and a presynchronized clock are provided to the
SSDA receiver section by means of the Receive Data
(Rx DATA, and Receive Clock IRx ClKI inputs. The data
is a continuous stream of binary data bits without
means for identifying character boundaries within the
stream. It is, therefore, necessary to achieve character
synchronization for the data at the beginning of the data
block. Once synchronization is achieved, it is assumed
to be retained for all successive characters within
the block.
Receiving Data
Once synchronization has been achieved, subsequent
characters are automatically transferred into the receive
data FIFO and clocked through the FIFO to the last
empty location by E pulses (MPU system q,2).The
receiver data available (RDA) status bit indicates when
data is available to be read from the last FI FO location
I No. 31 when in the I-byte transfer mode. The 2-byte
transfer mode causes the RDA status bit to indicate data
is available when the last two FI FO register locations
are full. Data being available in the receive data FIFO
causes an interrupt request if the receiver interrupt
enable (RIEl bit is set. The MPU will then read the
SSDA status register, which will indicate that data is
available for the MPU read from the receive data FIFO
register. The IRQ and RDA status bits are reset by a
read from the FIFO. If more than one character has
been received and is resident in the receive data FIFO,
Data communication systems utilize the detection of
sync codes during the initial portion of the preamble to
establish character synchronization. This requires the
detection of a single code or two successive sync
codes. Floppy disk and cartridge tape units require
16 bits of defined preamble and cassettes require eight
bits of preamble to establish the reference for the start
of record. All three are functionally equivalent to the
detection of sync codes. Systems that do not utilize
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F68521F68A52/F68B52
subsequent E clocks will cause the FIFO to update, and
the ROA and IRQ status bits will be set again. The read
data operation for the 2-byte transfer mode requires an
intervening E clock between reads to allow the FIFO
data to shift. Optional parity is automatically checked as
data is received, and the parity status condition is
maintained with each character until the data is read
from the receive data FIFO. Parity errors will cause an
interrupt request if the error interrupt enable (EIE) has
been set. The parity bit is not transferred to the data
bus but must be checked in the status register. Note: In
the 2-byte transfer mode, parity should be checked prior
to reading the second byte, since a FIFO read clears the
error bit.
Enable (E)
The Enable (E) signal is a high-impedance, TTLcompatible input that enables the bus input/output data
buffers, clocks data to and from the SSDA, and moves
data through the FIFO registers. This Signal is normally
the continuous F6800 system <1>2 clock, so that incoming
data characters are shifted throLigh the FIFO.
Read/Write (RiW)
The Read/Write line is a high-impedance input that is
TTL-compatible and is used to control the direction of
data flow through the SSDAs input/output data bus
interface. When Read/Write is HIGH (MPU read cycle),
SSOA output drivers are turned on if the device is
selected and a selected register is read. When it is
LOW, the SSOA output drivers are turned off and the
MPU writes into a selected register. The Read/Write
signal is also used to select read-only or write-only
registers within the SSOA.
Other status bits that pertain to the receiver section
are receiver overrun and data carrier detect (DCD). The
overrun status bit is automatically set when a transfer of
a character to the receive data FIFO occurs and the first
register of the receive data FIFO is full. Overrun causes
an interrupt if error interrupt enable (EIE) has been set.
The transfer of the overrunning character into the FIFO
causes the previous character in the FI FO input register
location to be lost. The overrun status bit is cleared by
reading the status register 1when the overrun condition
is present), followed by a receive data FIFO register
read. Overrun cannot occur and be cleared without
providing an opportunity to detect the occurrence via
the status register.
Chip Select (CS)
This high-impedance, TTL-compatible input line is used
to address the SSOA. The SSOA is selected when CS is
LOW. VMA should be used in generating the CS input
to insure that false selects will not occur. Transfers of
data to and from the SSOA are then performed under
the control of the Enable signal, Read/Write, and
Register Select.
Register Select (RS)
The Register Select line is a high-impedance input that
is TTL-compatible. A HIGH level is used to select
control registers C2 and C3, the sync code register, and
the transmit/receive data registers. A LOW level selects
the control 1 and status registers (see Table 1).
A positive transition on the OCO input causes an
interrupt if the EIE control bit has been set. The
interrupt caused by OCO is cleared by reading the
status register when the OCD status bit is HIGH,
followed by a receive data FIFO read. The OCO status
bit will subsequently follow the state of the OCO input
when it goes LOW.
Interrupt Request (IRQ)
Interupt Request is a TTL-compatible, open-drain (no
internal pull-up), active-LOW output that is used to
interrupt the MPU. The Interrupt Request remains LOW
until cleared by the MPU.
SSOA Interface Signals for MPU
The SSOA interfaces to the F6800 MPU with an 8-bit
bidirectional data bus. a Chip Select line. a Register
Select line, an Interrupt Request line, a Read/Write line,
an Enable line, and a Reset line. These Signals, in
conjunction with the F6800 VMA output, permit the MPU
to have complete control over the SSOA.
Reset Input (RESET)
The Reset input provides a means of resetting the SSOA
from an external source .. In the LOW state, the Reset
input causes the following:
1. Receiver reset IRx Rs) and transmitter reset ITx Rs)
bits are set, causing both the receiver and transmitter
sections to be held in a reset condition.
2. Peripheral control bits PC1 and PC2 are reset to "0",
causing the SM/OTR output to be HIGH.
3. The error interrupt enable (EIE) bit is reset.
4. An internal synchronization mode is selected.
5. The transmitter data register available (TORA) status
bit is cleared and inhibited.
Bidirectional Oata Bus (00-07)
The bidirectional data lines 100-07) allow for data
transfer between the SSOA and the MPU. The data bus
output drivers are 3-state devices that remain in the
high-impedance (OFF) state except when the MPU
performs an SSOA read operation.
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5
F6852/F68A52/F68B52
When RESET returns HIGH (the inactive state), the
transmitter and receiver sections will remain in the reset
state until the receiver reset and transmitter reset bits
are cleared via the bus under software control. The
control register bit affected by RESET (Rx Rs, Tx Rs,
PC1, PC2, EIE, and E/l Synci cannot be changed when
RESET is lOW.
the system. The stored CTS information and its
associated IRQ (if enabled) are cleared by writing a "1"
in the CTS bit in control register 3 or in the transmitter
reset bit. The CTS status bit subsequently follows the
CTS input when it goes lOW.
The CTS input provides character timing for transmitter
data when in the external sync mode. Transmission is
initiated on the negative transition of the first full
positive clock pulse of the Transmit Clock (Tx ClK) after
the release of CTS. See Figure 6.
Clock Inputs
Separate high-impedance, TTL-compatible inputs are
provided for clocking of transmitted and received data.
Data Carrier Detect (DCD)
The DCD input provides a real-time inhibit to the
receiver section (the Rx FI FO is not disturbed). A
positive DCD transition resets and inhibits the receiver
section except for the receive FIFO and the RDRA
status bit and its associated IRQ.
Transmit Clock (Tx ClK)
The Transmit Clock input is used for the clocking of
transmitted data. The transmitter shifts data on the
negative transition of the clock.
Receive Clock (Rx ClK)
The Receive Clock input is used for clocking in received
data. The clock and data must be synchronized
externally. The receiver samples the data on the positive
transition of the clock.
The positive transition of DCD is stored within the
SSDA to insure that its occurrence will be acknowledged by the system. The stored DCD information and
its associated IRQ (if enabled) are cleared by reading
the status register and then the receive FIFO, or by
writing a "1" into the receiver reset bit. The DCD status
bit subsequently follows the DCD input when it goes
lOW. The DCD input provides character synchronization
timing for the receiver during the external sync mode of
operation. The receiver will be initialized and data will
be sampled on the positive transition of the first full
Receive Clock cycle after release of DCD. See Figure 7.
Serial Input/Output lines
Receive Data (Rx DATA)
The Receive Data line is a high-impedance, TTlcompatible input through which data is received in a
serial format. Data rates are from 0 to 600K bps.
Transmit Data (Tx DATA)
The Transmit Data output line transfers serial data to a
modem or other peripheral. Data rates are from
o to 600K bps.
Sync Match/Data Terminal Ready (SM/i5TR)
The SM/DTR output provides four functions depending
on the state of the PC1 and PC2 control bits. When the
Sync Match mode is selected (PC1 = "1", PC2 = "0"),
the output provides a one-bit-wide pulse when a sync
code is detected. This pulse occurs for each sync code
match even if the receiver has already attained
synchronization. The SM output is inhibited when
PC2 = "1". The DTR mode (PC1 = "0") provides an
output level corresponding to the complement of PC2
(DTR = "0" when PC2 = "1"). See Table 1.
Peripheral/Modem Control
The SSDA includes several functions that permit limited
control of a peripheral or modem. The functions
included are Clear-to-Send, Sync Match/Data Terminal
Ready, Data Carrier Detect, and Transmitter Underflow.
Clear-to-Send (CTS)
The CTS input provides a real-time inhibit to the
transmitter section (the transmit data FIFO is not
disturbed ).A positive CTS transition resets the
transmitter shift register and inhibits the TDRA status bit
and its a~sociated interrupt in both the one-synccharacter and two-sync-character modes of operation.
TDRA is not affected by the CTS input in the external
sync mode.
Transmitter Underflow (TUF)
The Transmitter Underflow output indicates the occurrence
of a transfer of a "fill character" to the transmitter shift
register when the last location (No.3) in the transmit
data FIFO is empty. The Transmitter Underflow output
pulse is approximately a Tx ClK HIGH period wide and
occurs during the last half of the last bit of the character
preceding the underflow. See Figure 4. The Transmitter
Underflow output pulse does not occur when the Tx Sync
bit is in the reset state.
The positive transition of CTS is stored within the SSDA
to insure that its occurrence will be acknowledged by
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F6852/F68A521F68B52
inhibiting resynchronization. The clear sync bit is set to
clear and inhibit receiver synchronization in a/l modes
and is reset to "0" to enable resynchronization.
SSDA Registers
Seven registers in the SSDA can be accessed by means
of the bus. The registers are defined as a read-only or
write-only according to the direction of information flow
The Register Select input (RS) selects two registers in
each state, one being read-only and the other writeonly. The Read/Write input (R/W) defines which of the
two selected registers will actually be accessed. Four
registers (two read-only and two write-only) can be
addressed via the bus at any particular time. These
registers and the required addressing are defined
in Table 1.
Transmitter Interrupt Enable (TIE). Cl Bit 4
TIE enables both the Interrupt Request output (IRQ) and
interrupt request status bit to indicate a transmitter
service request. When TIE is set and the TDRA status
bit is HIGH, the IRQ output will go lOW (the active
state) and the IRQ status bit will go HIGH.
Receiver Interrupt Enable (RIE). Cl Bit 5
RIE enables both the Interrupt Request output
and the interrupt request status bit to indicate
service request. When RII; is set and the RDA
HIGH, the IRQ output will go lOW (the active
and the IRQ status bit will go HIGH.
Control Register 1 (Cl)
Control register 1 is an a-bit, write-only register that can
be addressed directly from the data bus. Control
register 1 is addressed when RS = "0" and R/W = "0".
(IRQ)
a receiver
status is
state)
•
Address Control 1 (AC1) and Address Control 2 (AC2).
Cl Bits 6 and 7
ACl and AC2 select one of the write-only registerscontrol 2, .control 3, sync code, or transmit data
FIFO-as shown in Table 1, when RS="l" and
R/W= "0".
Receiver Reset (Rx Rs). Cl. Bit 0
The receiver reset control bit provides both a reset and
inhibit function to the receiver section. When Rx Rs is
set, it clears the receiver control logic, sync logic, error
logic, Rx Data FIFO control, parity error status bit, and
DCD interrupt. The receiver shift register is set to "1 s".
The Rx Rs bit must be cleared after the occurrence of.a
lOW level on RESET in order to enable the receiver
section of the SSDA.
Control Register 2 (C2)
Control register 2 is an a-bit, write-only register that
can be programmed from the bus when the address
control bits in control register 1 (ACl and AC2) are
reset, RS = "1" and R/iN = "0".
Transmitter Reset (Tx Rs). Cl Bit 1
The transmitter reset control bit provides both a reset
and inhibit to the transmitter section. When Tx Rs is set,
it clears the transmitter control section, transmitter shift
register, Tx Data FIFO (which can be reloaded after one
E clock pulse), the transmitter underflow status bit, and
the CTS interrupt, and inhibits the TDRA status bit (in
the one-sync-character and two-sync-character modes).
The Tx Rs bit must be cleared after the occurrence of a
lOW level on RESET in order to enable the transmitter
section of the SSDA. If the Tx FIFO is not preloaded, it
must be loaded immediately after the Tx Rs release to
prevent a transmitter underflow condition.
Peripheral Control 1 (PC1) and Peripheral Control 2 (PC2).
C2 Bits 0 and 1
Two control bits, PCl and PC2, determine the operating
characteristics of the Sync Match/DTR output. PC1,
when HIGH, selects the Sync Match mode. PC2
provides the inhibit/enable control for the SM/DTR
output in the sync match mode. A one-bitcwide pulse is
generated at the output when PC2 is "0", and a match
occurs between the contents of the sync code register
and th.e incoming data even if sync is inhibited (Clear
Sync bit = "1".) The sync match pulse is referenced to
the negative edge of Rx ClK pulse causing the match.
See Figure 3.
Strip Synchronization Characters (Strip Sync). Cl Bit 2
If the strip sync bit is set, the SSDA will automatically
strip all received characters that match the contents of
the sync code register. The characters used for
synchronization (one or two characters of sync) are
always stripped from the received data stream.
The Data Terminal Ready (DTR) mode is selected when
PCl is lOW. When PC2 = "1", the SM/DTR output = "0",
and vice versa. The operation of PC2 and PCl is
summarized in Table 1.
Clear Synchronization (Clear Sync). Cl Bit 3
The clear sync control bit provides the capability of
dropping receiver character synchronization and
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F6852/F68A521F68852
External/Internal Sync Mode Control (E/I Sync), C3 Bit 0
When the E/I sync mode bit is HIGH, the SSDA is in
the external sync mode and the receiver synchronization
logic is disabled. Synchronization can be achieved by
means of the DCD input or by starting Rx ClK at the
midpoint of data bit 0 of a character with DCD lOW.
Both the transmitter and receiver sections operate as
parallel- serial converters in the external sync mode.
The clear sync bit in control register 1 acts as a receiver
sync inhibit when HIGH to provide a bus-controllable
inhibit. The sync code register can serve as a
transmitter fill character register and a receiver match
register in this mode. A lOW on the RESET input resets
the E/I sync mode bit, placing the SSDA in the internal
sync mode.
1-Byte/2-Byte Transfer (1-Byte/2-Byte), C2 Bit 2
When 1-Byte/2-Byte is set, the TDRAand RDA status
bits will indicate the availability of their respective data
FIFO register for a single -byte data transfer. Alternately,
if ,-Byte/2-Byte is reset, the TDRA and RDA status bits
indicate when two bytes of data can be moved without
a second status read. An intervening Enable pulse must
occur between data transfers.
Word Length Selects (WS1, WS2, WS3), C2 Bits 3, 4, 5
Word length select bits WS1, WS2, and WS3 select word
length of seven, eight, or nine bits, including parity, as
shown in Table 1.
Transmit Sync Code on Underflow (Tx Sync), C2 Bit 6
When Tx Sync is set, the transmitter will automatically
send a sync character when data is not available for
transmission. If Tx Sync is reset, the transmitter will
transmit a mark char/icter (including the parity bit
position) on underflow. When the underflow is detected,
a pulse approximately a Tx ClK HIGH period wide will
occur on the underflow output if the Tx Sync bit is set.
Internal parity generation is inhibited during underflow
except for sync code fill character transmission in 8-bit
pi us parity word lengths.
One-Sync-Character/Two-Sync-Character Mode Control
(1-Sync/2-Sync), C3 Bit 1
When the 1-Sync/2-Sync bit is set, the SSDA will
synchronize on a single match between the received
data and the contents of the sync code register. When
the 1-Sync/2-Sync bit is reset, two successive sync
characters must be received prior to receiver synchronization. If the second sync character is not detected, the
bit-by-bit search resumes from the first bit in the second
character. See the description of the sync code register
for more details.
Error Interrupt Enable (EIE), C2 Bit 7
When EIE is set, the IRQ status bit will go HIGH and
the IRQ output will go lOW if:
·1. A receiver overrun occurs. The interrupt is cleared
by reading the status register and reading the
Rx Data FIFO.
2. i5CiS input has gone to a "1". The interrupt is
cleared by reading the status register and reading the
Rx Data FIFO.
3. A parity error exists for the character in the last location
(No.3) of the Rx Data FIFO. The interrupt is cleared by
reading the Rx Data FIFO.
4. The CTS input has gone to a "1 ". The interrupt is cleared
by writing a "1" in the Clear CTS bit, C3 bit 2, or by
Tx Reset.
5. The transmitter has underflowed (in the Tx Sync on
underflow mode). The interrupt is cleared by writing a
"1" into the clear underflow, C3 bit 3, or Tx Reset.
Clear CTS Status (Clear CTS), C3 Bit 2
When a "1" is written into the CTS bit, the stored status
and interrupt are cleared. Subsequently, the CTS status
bit reflects the state of the CT~ut. The Clear CTS
control bit does not affect the CTS input nor its inhibit
of the transmitter section. The Clear CTS command bit
is self-clearing, and writing "0" into this bit is a
nonfunctional operation.
Clear Transmit Underflow Status (CTUF), C3 Bit 3
When a "1" is written into the CTUF status bit, the
CTUF bit and its associated interrupt are reset. The
CTUF command bit is self-clearing and writing a "0"
into this bit is a nonfunctional operation.
Sync Code Register
The sync code register is an 8-bit register for storing
the programmable sync code required for received data
character synchronization in the one-sync-character and
two-sync-character modes. The sync code register also
provides for stripping the sync/fill characters from the
received data (a programmable option I as well as
automatic insertion of fill characters in the transmitted
data stream. The sync code register is not utilized for
receiver character synchronization in the external sync
mode; however, it provides storage of receiver match
and transmit fill characters.
When EIE is a "0", the IRQ status bit and the IRQ
output are disabled for the above error conditions. A
lOW level on the RESET input resets EIE to "0".
Control Register 3 (C3)
Control Register 3 is a 4-bit, write-only register that can be
programmmed from the bus when RS = "1" and R/W = "0",
and address control bit AC1 = "1" and AC2 = "0".
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F6852/F68A52/F68852
The sync code register can be loaded when AC2 and
AC1 are a "1" and "0", respectively, and RiiN = "0" and
RS = "1".
Strip Sync
(C1 Bit 2)
The sync code register may be changed after the
detection of a match with the received data (the first
sync code having been detected) to synchronize with a
double-word sync pattern. (This sync code change must
occur prior to the completion of the second character.)
The sync match (SM) output can be used to interrupt
the MPU system to indicate that the first eight bits have
matched. The service routine would then change the
sync match register to the second half of the pattern.
Alternately, the one-sync-character mode can be used
for sync codes for 16 or more bits by using software to
check the second and subsequent bytes after reading
them from the FIFO.
No transfer of sync code. No
parity check of sync code.
0
With
Parity
'Transfer data and sync
codes. Parity check.
0
Without
Parity
'Transfer data and sync
codes. No parity check.
1. Data format is (6 + parity), (7 + parity).
2. Strip sync is not selected (LOW).
3. After synchronization when sync code is used as
a fill character.
The transmitter sends the sync character without parity, but
the receiver checks the parity as if it is normal data.
Therefore, the sync character should be chosen to
match the parity check selected for the receiver in this
special case.
Transmitter
The transmitter does not generate parity for the sync
character except in the 9-bit mode.
parity)
parity)
parity)
X
It is necessary to pay attention to the selected sync
character in the following cases:
Parity lor Sync Character
+
+
+
1
* Subsequent to synchronization.
The detection of the sync code can be programmed to
appear on the Sync Match/DTR output by writing a "1"
in PC1 (C2 bit 0) and a "0" in PC2 (C2 bit 1). The Sync
Match output will go HIGH for one bit time beginning at
the character interface between the- sync code and the
next character (see Figure 3).
9-bit (8-bit
8-bit (7-bit
7-bit (6-bit
WSO-WS2
(Data Format)
(C2 Bit 3-5)
Receive Data First-In First-Out Register (Rx Data FIFO)
The receiVe data FIFO register consists of three 8-bit
registers that are used for buffer storage of received
data. Each 8-bit register has an internal status bit that
monitors its full or empty condition. Data is always
transferred from a full register to an adjacent empty
register. The transfer from register to register occurs on
E pulses. The RDA status bit will be HIGH when data is
available in the last location of the Rx Data FIFO.
8-bit sync character + parity
. 8-bit sync character (no parity)
. 8-bit sync character (no parity)
Receiver
At Synchronization
The receiver automatically strips the sync character(s). (two
sync characters if 2-sync mode is selected) that is used
to establish synchronization. Parity is not checked for
these sync characters.
In an overrun condition, the overrunning character will
be transferred into the full first stage of the FIFO
register and will cause the loss of that data character.
Successive overruns continue to overwrite the first
register of the FIFO. This destruction of data is
indicated by means of the overrun status bit. The
overrun bit will be set when the overrun occurs and
remains set until the status register is read, followed by
a read of the Rx Data FI FO.
Alter Synchronization is Established
When strip-sync bit is selected, the sync characters (fill
characters) are stripped and parity is not checked for
the stripped sync (Iill) characters. When strip-sync bit is
not selected (LOW), the sync character is assumed to
be normal data and it is transferred into FIFO after
parity checking. (When non-parity format is selected,
parity is not checked.)
Unused data bits for short word lengths (including the
parity bit) will appear as "Os" on the data bus when
Rx Data FIFO is read.
5-227
•
F68521F68A52/F68B52
Transmit Oats First-In First-Out Register(Tx Data FIFO)
The transmit data FIFO register consists of three 'S-bit
registers that are used for buffer storage of data to be
transmitted. Each S-bit register has an internal status bit
that monitors its full or empty condition. Data is always
transferred from a full register to an adjacent empty
register. The transfer is clocked by E pulses.
The TDRA status bit will be HIGH if'the Tx Data FIFO is
available for data.
I
Unused data bits for short word lengths will be handled
as "don't cares'~. The parity bit is not transferred
over the data bus, since the SSDA generates parity at
transmission.
'
I
I
When an underflow occurs, the underflOW character will
be either the contents of the sync code register or an
all-"15" character. The underflow will be stored in the
status register until cleared and will appear'on the underflow output as a pulse approximately a Tx ClK HIGH
period wide.
Status Register
mode. The Tx ,Data FIFO can be loaded with two bytes
without an intervening status read; however, one E pulse
must occur between loads. TDRA is inhibited by the
Tx Reset or RESET. When Tx Reset is set. the Tx Data
FIFO is cleared and then released on the next E clock
pulse. The Tx Data FIFO can then be loaded with up to
three characters of data, even though TDRA is inhibited.
This feature allows preloading data prior ,to the release
of Tx Aeset. A HIGH level on the CTS input inhibits the
TDRA status bit in either sync mode of operation (onesync-character or two-sync-character). CTS does not
affect TDRA in the external sync mode. This enables the
SSDA to operate under the control of the CTS input,
with TDRA indicating the status of the Tx Data FIFO.
The CTS input does not clear the Tx Data FIFO in any
operating mode.
Data Carrier Detect (DCD), S Bit 2
A positive transition on the DCD input is stored in the
SSDA until cleared by reading both status and Rx Data
, FIFO. A "1" written into Rx Rs also clears the stored
i5C5 status. The 5Ci5 status bit. when set, indicates
that the 5CD input has gone HIGH. The reading of bot~
status and receive data FIFO allows bit 2 of subsequent
status reads to indicate the state of the DCD input until
the next positive transition.
The status register is an S-bit, read-only register that
provides the real-time status of the SSDA and the
associated serial data chan nel. Reading' ttie status
register is a non-destructive process. The method of
clearing status bits depends upon the function each bit
represents and is discussed for each bit in the register.
Clear-to-Send (CTS), S Bit 3
A positive transition on the CTS input is stored in the
SSDA until cleared by writing a "1" into the Clear CTS
control bit or the Tx Rs bit. The CTS status bit, when
set, indicates that the ffi input has gone HIGH. The
Clear ffi command (a "1" into C3 bit 2) allows bit 3 of
$ubsequent status reads to indicate the state of the CTS
input until the next positive transition.
Receiver Data Available (RDA), S Bit 0
The receiver data available status bilindicates when
receiver d'ata can be read from the Rx Data FIFO. The
receiver data being prese!)t in the last register (No.3) of
the FIFO causes RDA to be HIGH for the 1-byte transfer
mode. The RDA bit being HIGH indicates that the last
two registers (No.2 and No.3) are full when in the
2-byte transfer mode. The second character can be read
without a second status read (to determine that the
character is"available). An E pulse m'ust occur between
reads of the Rx Data FIFO to allow the FIFO to shift.
Status must be read on a word-by-word basis if receiver
data error checking is important. The ADA status bit is
reset automatically when data is not avail,able.
Transmitter Underflow (TUF), S Bit 4
When data is not available for the transmitter, an
underflow occurs and is so indicated in the status
register (in the Tx Sync on underflow mode), The
underflow status bit is cleared by writing a "1" into the
clear underflow (CTUF) control bit or the Tx Rs bit.
TUF indicates that a sync character will be transmitted
as the next character. A TUF is indicated on the output
only when the contents of the sync code register are to
be transferred (,transmit sync code on underflow = "1").
Receiver Overrun (Rx Ovrn), S Bit 5
Overq.m indicates data has been received when the
Rx Data FIFO is full. resulting in data 1055. The Rx Ovrn
status' bit is set when overrun occurs. The RI< Ovrn
status bit is cleared by reading status foll()wed by
reading the Rx Data FIFO or by setting the Rx Rs
control bit.
Transmitter Data Register Available (TDRA), S Bit 1
The TDRAstatus bit indicates that data can be'loaded
into the Tx Data FIFO register. The first register (No.1)
of the Tx Data FIFO being empty will be indicated by a
HIGH level of the TDRA status bit in the 1-byte transfer
mode. The first two registers (No.1 and No.2) must be
empty for TDRA to be HIGH when in the 2-byte transfer
5-22S
F6852/F68A521F68B52
Receiver Parity Error (PE), S Bit 6
The parity error status bit indicates that parity for the
character in the last register of the Rx Data FIFO did
not agree with selected parity. The parity error is
cleared when the character to which it pertains is read
from the Rx Data FIFO or when Rx Rs occurs. The
OeD input does not clear the parity error or Rx Data
FIFO status bits.
Interrupt Request (IRQ), S Bit 7
The interrupt request status bit indicates when the IRQ
output is in the active state (IRQ output = "0"). The IRQ
status bit is subject to the same interrupt enables (RIE,
TIE, and EIE) as the IRQ output. The IRQ status bit
simplifies status inquiries for polling systems by
providing single-bit indication of service requests.
Table 1 SSDA Programming Model
Register
Control
Inputl
Address
Control
Regllter Content
RS
R/W AC2 AC1
Bit 7
Bit 6
Bit 5
Bit 4
0
1
X
X
Interrupt
Request
IIRQ)
Receiver
Parity
Error
(PE)
Receiver
Overrun
(Rx Ovrn)
Transmitter Clear-toUnderflow Send
(TUF)
(CTS)
Data Carrier Transmitter, Receiver
Data
Detect
Data
(DCD)
Register
Available
(RDA)
Available
(TDRA)
Control 1 0
C1
0
X
X
Address
Control 2
IAC2)
Address
Control 1
IAC1)
Receiver
Interrupt
Enable
(RIE)
Transmitter Clear
Interrupt
Sync
Enable
ITIE)
Strip Sync
Characters
(Strip Sync)
Transmitter
Reset
(Tx Rs)
Receiver
Reset
(Rx Rs)
1
Receive
Data FIFO
1
X
X
D7
Os
Os
04
D3
D2
0,
Do
Control 2
(C2)
1
0
0
0
Error
Interrupt
Enable
(EIE)
Transmit
Sync
Code on
Underflow
(Tx Sync)
Word
Length
Select 3
IWS3)
Word
Length
Select 2
(WS2)
Word
Length
Select 1
IWS1)
1-Bytel
2-Byte
Transfer
11-Bytel
2-Byte)
Peripheral
Control 2
(PC2)
Peripheral
Control 1
(PC1)
Control 3
(C3)
1
0
0
1
Not Used
Not Used
Not Used
Not Used
Clear
Clear CTS
Transmitter Status
Underflow (Clear CTS)
Status
ICTUF)
One-SyncCharacterl
Two-SyncCharacter
Mode
Control
(1-Syncl
2-Sync)
External!
Internal
Sync Mode
Control
(Ell Sync
Sync
Code
1
0
1
0
D7
Os
Os
04
D3
D2
0,
Do
Transmit 1
Data FIFO
0
1
1
D7
Os
05
04
D3
02
0,
Do
Status
IS)
x=
Don't Care
5-229
Bit 3
Bit 2
Bit 1
Bit 0
•
F6852/F68A52/F68B52
Status Register
IRQ
RDA
The IRQ flag is cleared when the source of the IRQ is cleared. The
source is determined by the enables in the control registers: TIE, RIE, EIE.
Indicate the SSDA status at a point in time, and can be
reset as follows:
Bit 6
Read Rx Data FIFO, or a "1" into Rx Rs (C1 bit 0).
Bit 5
Read status and then Rx Data FIFO, or a "1" into Rx Rs
(C1 bit 0).
Bit 4
A "1" into CTUF (C3 bit 3) or into Tx Rs (C1 bit 1)
Bit 3
A "1" into CTS (C3 bit 2) or a "1" into Tx Rs (C1 bit 1).
Bit 2
Read status and then Rx Data FIFO or a "1" into Rx Rs
(C1 bit 0).
Bit 1
Write into Tx Data FIFO.
Bit 0
Read Rx Data FIFO.
AC2, AC1
RIE
TIE
Clear Sync
Strip Sync
Bits 7, 6
Bit 5
Bit 4
Bit 3
Bit 2
Tx Rs
Rx Rs
Bit 1
Bit 0
EIE
Bit 7
Tx Sync
Bit 6
WS3, 2, 1
Bits 5-3
Bit 7
Bits 6-0
PE
Rx Ovrn
TUF
CTS
DCD
TDRA
Control Register 1
Used to access other registers, as shown above.
When "1", enables interrupt on RDA (S bit 0).
When "1", enables interrupt on TDRA (S bit 1).
When "1", clears receiver character synchronization
When "1", strips all sync codes from the received
data stream.
When "1", resets and inhibits the transmitter section.
When "1", resets and inhibits the receiver section.
Con.trol Register 2
When "1", enables the PE, Rx Ovrn, TUF, CTS, and
interrupt flags (S bits 6 through 21.
When "1", allows sync code content to be transferred
on underflow, and enables the TUF status bit and output.
When "0", an all-mark character is transmitted
on underflow.
Word Length Select
5C5
5·230
Bit 5
WS3
Bit 4
WS2
Bit 3
WS1
0
0
0
0
0
0
0
1
1
0
1
1
1
1
0
0
0
1
1
1
1
1
0
1
Word Length
6
6
7
8
7
7
8
8
Bits
Bits
Bits
Bits
Bits
Bits
Bits
Bits
+
+
Even parity
Odd Parity
+
+
+
+
Even
Odd
Even
Odd
Parity
Parity
Parity
Parity
·F6852/F68A52/F68B52
1-Byte/2-Byte
Bit 2
PC2, PC1
Bits 1-0
When "1", enables the TDRA and RDA bi.ts to
indicate when a 1-byte transfer can occur; when "0",
the TDRA and RDA bits indicate when a 2-byte transfer
can occur.
SM/DTR Output Control
Bit 1
PC2
Bit 0
PC1
SM/i)'i'R Output at Pin 5
0
0
0
1
1
Pulse
1
1
0
1
0
SM Inhibited, 0
.J""L , 1-Bit
Wide, on SM
Control Register 3
CTUF
Clear CTS
1-Sync/2-Sync
Bit 3
Bit 2
Bit 1
Ell Sync
Bit 0
When "1", clears TUF (5 bit 4)and IRQ, if enabled.
When "1", clears CTs (S bit 3) and IRQ, if enabled.
When "1", selects the one-sync-character mode;
when "0", selects the two-sync-character mode.
When "1", selects the external sync mode;
when "0", selects the internal sync mode.
Notes
When the SSDA is used in applications requiring the MSB of data to be
received and transmitted first, the data bus inputs to the SSDA may be
reversed (DO to 07. etc.l. Caution must be used when this is done, since
the bit positions in this table will be reversed, and the parity should
not be selected.
Absolute Maximum Ratings
Supply Voltage
Input Voltage
Operating Temperature Range
F6852P,S, F68A52P, S, F68B52P, S
F6852CP, CS, F68A52CP, CS
F6852DLQB
F6852DMQB
Storage Temperature Range
Thermal Resistance
Plastic Package
Ceramic Package
Stresses greater than those listed under "Absolute Maximum Ratings"
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for
-0.3 V, +7.0 V
-0.3 V, +7.0 V
O·C,
-40°C,
-55° C,
-55°C,
-55°C,
+70°C
+85°C
+85° C
+125·C
+150·C
extended periods may affect device reliability.
5·231
•
F68521F68A521F68B52
DC Characteristics Vee = 5.0 V ± 5%, Vss = 0, TA = 0 to 70·C unless otherwise noted
Symbol. Characteristic
VIH
Input HIGH Voltage
VIL
Input lOW Voltage
liN
Input leakage Current
Signal
Min
Typ
Max
2.0
Tx ClK,Rx ClK,
. Rx DATA, Enable,
RESET, RS, R/W, CS,
Unit
Test Conditions
V
0.8
V
1.0
2.5
p.A
VIN
2.0
10
p.A
VIN = 0.4 to 2.4 V,
Vee = 5.25 V
V
ILoad = -205 p.A,
Enable Pulse Width <25 p's
ILoad = -100 p.A,
Enable Pulse Width <25 P.s
0.4
V
ILo~d = 1.6 rnA,
Enable Pulse Width <25 P.s
1.0
10
p.A
VOH
300
525
mW
= 0 to 5.25 V
DCD,~
Irsl
3-State (OFF State)
Input Current
Do-D7
VOH
Output HIGH Voltage
Do-D7
2.4
Tx DATA, DTR, TUF
2.4
VOL
Output lOW Voltage
ILOH
Output leakage Current
(OFF State)
Po
Power Dissipation
CIN
Input Capacitance
COUT
Output Capacitance
(lRO)
pF
Do-D7
All Other Inputs.
12.5
7.5
Tx DATA, SM/D'fR,
TUF
IRO
10
VIN
5-232
= 0, TA = 25·C,
f = 1.0 MHz
pF
= 0, TA = 25°C,
= 1.0 MHz
VIN
f
5.0
= 2.4 V
F68521F68A521F68B52
AC Characteristics
Vcc = 5.0 V
± 5%, Vss
= 0, TA = O°C to +70°C unless otherwise noted.
F6852
F68A52
Max
Min
F68B52
Symbol
Characteristic
Min
PWCL
Minimum Clock Pulse Width,
LOW (Figure 1)
700
400
280
ns
PWCH
Minimum Clock Pulse Width,
HIGH (Figure 2)
700
400
280
ns
600
Max
Min
Max
Unit
fc
Clock Frequency
tAOSU
Receive Data Set-up Time
(Figures 3, 7)
350
200
160
ns
tAOH
Receive Data Hold Time
(Figure 3)
350
200
160
ns
tSM
Sync Match Delay Time
(Figure 3)
1.0
0.666
0.500
",s
tTOO
Clock-to-Data Delay for
Transmitter (Figure 4)
1.0
0.666
0.500
",s
trUF
Transmitter Underflow
(Figure 4, 6)
1.0
0.666
0.500
",s
1000
1500
kHz
tOTA
DTR Delay Time (Figure 5)
1.0
0.666
0.500
",s
tlA
Interrupt Request Release Time
(Figure 5)
1.2
0.800
0.600
",s
tAes
RESET Minimum Pulse Width
1.0
0.666
0.500
",s
tCTS
CTS Set-up Time (Figure 6)
200
150
120
ns
toco
DCD Set-up Time (Figure 7)
500
350
250
ns
tr, tf
Input Rise and Fall Times
(except Enable)
·1.0 ~s
1.0·
1.0·
or 10% of the pulse width. whichever is smalier.
5·233
--~
------
1.0·
Test Condition
",s
0.8 V to 2.0 V
F68521F68A52/F68B52
Bus Timing Characteristics
Read (Figures 8 and 10)
F6852
Symbol
Characteristic
Min
tcycE
Enable Cycle Time
1.0
PWEH
Enable Pulse Width. HIGH
0.45
F68A52
Max
Min
F68B52
Max
0.666
25
0.28
Min
Max
0.5
25
0.22
Unit
p,s
25
p,s
PWEL
Enable Pulse Width. LOW
0.43
0.28
0.21
p,s
tAS
Set-up Time. Address and R/W valid to
Enable positive transition
160
140
70
ns
tOOR
Data Delay Time
tH
Data Hold Time
220
320
10
10
tAH
Address Hold Time
tEr. tEl
Rise and Fall Time for Enable input
180
ns
10
10
ns
10
10
ns
25
25
25
ns
. Write (Figures 9 and. 10)
0.5
Enable Cycle Time
1.0
PWEH
Enable Pulse Width. HIGH
0.45
PWEL
Enable Pulse Width. LOW
0.43
0.28
0.21
p,s
tAs
Set-up Time. Address and R/W valid to
Enable positive transition
160
140
70
ns
tosw
Data Set-up Time
195
80
60
ns
tH
Data Hold Time
10
10
10
ns
tAH
Address Hold Time
10
10
10
tEr. tEl
Rise and Fall Time for Enable input
Fig. 2
-:£:Y-
0.28
-
25
0.22
25
...-PWCH
5-234
p,s
ns
25
-=
y t=}-.o
Rx elK
0.8 Y
25
Clock Pulse Width, High-State
Tx elK
OR
WCL
Rx elK
25
25
Fig. 1 Clock Pulse Width, Low-State
Tx eLK
OR
0.666
p,s
tcycE
ns
F6852/F68A52/F68B52
Fig. 3
Receive Data Set-up and Hold Times
and Sync Match Delay Time
0,
Dn~ 1
DO
Rx elK
Rx DATA
SYNC MATCH
-------------------------------C,. . ~. ,~.O.- _ _ _I~
0.4 V
n = Number of bits in character
~ = Don't care
Fig. 4 Transmit Data Output Delay and
Transmitter Underflow Delay Time
Fig. 5
Data Terminal Ready and
Interrupt Request Release Times
2.0,'("\ O.BV
Tx
ClK
_ _ _ _- J
tTDD~
Tx
DATA
----
0,
DTR
~~
--
________-r__ )(
~tDTR
2.4 V
Jl~0.~4~V
-"R
IrUF
_______ _
______________
I
)"2:-:.4:-:V:O--------
TUF _ _ _ _ _ _ _ _ _ _ _ _..1
n
= Number
IRQ _ _ _ _ _ _ _ _ _ _..J
of bits in character
5-235
•
F68521F68A52/F68852
Fig. 6
Fig. 9
Clear-to-Send Set-up Time
Bus Write Timing. Characteristics
(Write Information Into SSDA)
CTi~
Tx ClK
]f---\::""-j
---~Jc.:
_____...Jr
RS,
r-rroo
DATA BUS
Tx DATA _ _ _ _ _ _ _ _ _ _ _. . . . I ¥ D O
Fig. 7
ca, R/W
Fig. 10
Bus Timing Test Loads
Load A
(00-07,
D'fR,
Deta Carrier Detect Set-up Time
Tx DATA, TUF)
5.0 V
TEST POINT - _.......-Kl-...
Rx ClK
C
lN914
OR
EQUIVALENT
CIROSU
)f2.0V
Rx DATA
-------J'"to.!1l
Do
c
Fig. 8
= 130 pF for 00-07
= 30 pF for OTR, Tx OATA, and TUF
R = 11.7 kll for 00-07
= 24 kll for OTR, Tx OATA, and TUF
Bus Read Timing Characteristics
(Read Information from SSDA)
Load B
(IRQ Only)
5.0 V
Rx,
~
ea, RtW
TEST POINT
DATA BUS
5-236
--:l..J,100 pF
3k
F6852/F68A52/F68B52
Ordering Information
Speed
Order Code
Temperature Range
1.0 MHz
F6852 P,S
F6852 CP,CS
F6852DLQB
F6852DMQB
O°C to 70°C
-40° C to +85° C
-55° C to +85° C
-55°C to +125°C
1.5 MHz
F68A52 P,S
F68A52 CP,CS
O°C to 70°C
-40° C to +85° C
2.0 MHz
F68B52 P,S
O°C to 70°C
P
= Plastic package; S
= Ceramic
package
•
5-237
F68521F68A52/F68B52
5-238
F6854/F68A54/F68B54
Advanced Data Link
Controller (ADLC)
Microprocessor Product
Description
The F6854/F68A54/F68B54 Advanced Data Link Controllers
(ADLC) perform the complex MPU/data communication
link function for the Advanced Data Communication
Control Procedure (ADCCP), High-level Data Link Control
(HDLC) and Synchronous Data Link Control (SDLC)
standards. The ADLC provides key interface requirements
with improved software efficiency. The ADLC is designed to
provide the data communications interface for both primary
and secondary stations in stand-alone, polling and loop
configurations.
Logic Symbol
FLAG DET
Rx Data
F6854
RESET
LOC/OTR
ROSR
TOSR
Vcc=Pin 14
Vss=Pin1
• F6800 Compatible
• Protocol Features
• Automatic Flag Detection and Synchronization
• Zero Insertion and Deletion
• Automatic Address Field Extension (Optional)
• Extended Control Field (Optional)
• Auto Extendable Logic Control Field (Optional)
• Variable Word Length Information Field
5-, 6-, 7-, or 8-Bit
• Automatic Frame Check Sequence
Generation and Check
• Abort Detection and Transmission
• Idle Detection and Transmission
• Modem/Data Channel Control Lines
• Loop Mode
• Single 5 V Power Supply
• Enhanced Speed Options
F6854-1.0 MHz
F68A54-1.5 MHz
F68B54-2.0 MHz
Connection Diagram
28-Pin DIP
CTS
OCO
RTS
RxData
LOC/OTR
RxC
FLAG OET
TxC
TOSR
TxData
ROSR
IRQ
00
RESET
0,
02
03
0,
RS,
05
06
Pin Names
RxData
RxC
TxC
RESET
CS
RSo, RS,
Riw
E
DCD
CTS
Do - 07
RTS
TxData
IRQ
RDSR
TDSR
FLAG DET
LOC!DTR
Vss
Vee
07
Receiver Serial Data Input
Receiver Data Timing Clock Input
Transmitter Data Timing Clock Input
Chip Master Reset Input
Chip Select Input
Register Addressing Select Inputs
Read/Write Input
System Control Clock Input
Data Carrier Detect Input
Clear-to-Send Input
Bidirectional Data I/O Lines
Request-to-Send Output
Transmitter Serial Data Output
Interrupt Request Output
Receiver Data Service Request Output
Transmitter Data Service Request Output
Flag Detect Output
Loop On-line Control/Data Terminal
Ready Output
Ground
+5 V Power Supply
(Top View)
5-239
•
F6854/F68A54/F68B54
Block Diagram
cs
RM
CONTROL
REGISTER 2
CONTROL
CONTROL
REGISTER 3
REGISTER 4
-
RSl
i i i i
I
;>.
RSo
I-
CHIP SELECT
RECEIVER
(
lt
DATA
ZERO
DELETION
RECEIVER
AFO
REGISTER 1
(3 BYTES)
DCD
RxC
t
I
I
RxDala
2
3
I
~
-f-fDATA
A
DATA
BUS
BUS
00-07
INTERFACE
<=
-
Fes CHECK
STATUS
REGISTER 2
l-
I
'FLAG/ABORTliOLE
DETECT
I
c..
STATUS
REGISTER 1
-
lTRANSMIT
DATA
=)
r-
FIFO
REGISTER 1
(3 BYTES)
2
3
CONTROL
REGISTER 1
I
~
rr
I
Fes GENERATOR
FLAG/ABORT
GENERATOR
t
ZERO
INSERTION
TRANSMlnER
t
I
L
I
TxOala
4
TxC
ill
LOC/OTR
I
CONTROL
"
.1] I
+
iffii
(
iiil:i
TDSR
ROSR
Operation
Transmitter Operation
The Transmitter Data FIFO Register (Tx FIFO) cannot be
pre-loaded when the transmitter section is in a reset state.
After the reset release, the Flag/Mark Idle Select control bit
(F/M Idle) selects either the mark idle state (inactive idle)
or the flag time fill (active idle) state. Thi.s active or inactive
mark idle state will continue until data is loaded into the
Tx FIFO.
Initialization
During a power-on sequence, the ADLC is reset via the
Reset (RESET) input and internally latched in a reset
condition to prevent erroneous output transitions. The four
Control Registers must be programmed prior to the release
of the reset condition. The release of the reset condition is
performed via software by writing a LOW into the Receiver
Reset (RxRS) control bit and/or Transmitter Reset (TxRS)
control bit. The release of the reset condition will be done
after FiESET has gone HIGH.
The availability of the Tx FIFO is indicated by the
Transmitter Data Available/Frame Complete (TDRAlFC)
status bit under the control of the 2-Byte/1-Byte Transfer
(2/1-Byte) control bit. TDRA status is inhibited by the
TxRS control bit or Clear-to-Send (CTS) input being
HIGH. When the 1-byte mode is selected, one byte of the
Tx FIFO is available for data transfer when TDRA/FC goes
At any time during operation, writing a HIGH into the
RxRS control bit or TxRS control bit causes the reset
condition of the receiver or transmitter section.
5·240
F6854/F68A54/F68B54
HIGH. When the 2-byte mode is selected, two successive
bytes can be transferred when TDRA/FC goes HIGH.
The frame is terminated by one of two methods. The most
efficient way to terminate the frame from a software
standpoint is to write the last data character into the
Tx FIFO frame-terminate address (RS1, RSo = HH) rather
than the Tx FIFO frame-continue address (RS1, RSo = HL).
An alternate method is to follow the last write of data in the
Tx FI FO frame-continue address with the setting of the
Transmit Last Data (Tx Last) control bit. Either method
causes the last character to be transmitted and the Frame
Check Sequence (FCS) field to be appended automatically
along with a closing flag. Data for a new frame can be
loaded into the Tx FIFO immediately after the old frame
data if TDRA/FC is HIGH. The closing flag can serve as
the opening flag of the next frame, or separate opening and
closing flags may be transmitted. If a new frame is not
ready to be transmitted, the ADLC will automatically trans- •
mit the active (flag) or inactive (mark) idle condition.
The first byte (address field) should be written into the
Tx FIFO at the frame-continue address. Then the transmission of a frame automatically starts. If the Transmitter is
in a mark idle state, the transfer of an address causes an
opening flag within two or three transmitter clock cycles. If
the Transmitter has been in a time fill state, the current time
fill flag being transmitted is assumed as an opening flag
and the address field will follow it.
A frame continues as long as data is written into the
Tx FIFO at the frame-continue address. The ADLC
internally keeps track of the field sequence in the frame.
The frame format is described in the Frame Format section.
ADLC Transmitter State Diagram
(Cibi refers to Control Register bit)
Data Being Transmitted·
F = flag
A = address
C = (link) control
LC
I
FCS
ABT
=
=
=
=
logical control (optional)
information
frame check sequence
abort
5-241
F6854/F68A54/F68B54
If the Tx FIFO'becomes empty at any time during frame
transmission (the Tx FIFO has no data to transfer into the.
transmitter shift register during transmission of the last half
of the next-to-Iast bit of a word), an underrun will occur
and the Transmitter automatically terminates the frame by
transmitting an abort. The underrun state is indicated by
the Transmitter Underrun (TxUJ status bit.
register (Register 3) for the 1-byte transfer mode. The
2-byte transfer mode causes the RDA status bit to indicate
data is available when the last two Rx FIFO register
locations (Registers 2.and ;3) lire full. If the data character
present in the Rx FIFO is an address octet, Status Register
1 will exhibit an address present status. condition. Data
being available in the Rx FIFO causes an interrupt to be
initiated (assuming the Receiver Interrupt Enable (RIE)
control bit is enabled, RIE="1"). The MPU will read the
ADLC status rE!gisters as a result of the interrupt or in its
turn in a polling sequence. The Receiver Data Available
(RDA) or Address Present (AP) status bits will indicate that
receiver data is available and the MPU should subsequently
read the Rx FIFO. The Interrupt Request (IRQ) and RDA
status bits will then be reset automatically. If more than one
character is received and is resident in the Rx FIFO,
subsequent E clocks will cause the Rx FIFO to update
and the RDA and IRQ status bits will again be set. In the
2-byte transfer mode both data bytes may be read on
consecutive E cycles. The AP status bit provides for 1-byte
transfers only.
Any time the Transmit Abort (ABT) control bit is set, the
Transmitter immediately aborts the frame (transmits at least
eight consecutive 1s) and clears the Tx FIFO. If the Abort
Extend (ABTEX) control bit is set at the time, an idle (at
least 16 consecutive 1s) is transmitted. An abort or idle in
an out-of-frame condition can be useful to gain eight or 16
bits of delay. (For an example see Programming Considerations.)
The CTS input and Request-to-Send (RTS) output
are provided for a modem or other hardware interface.
The TDRA/FC status bit (when selected to be frame-complete status) can cause an interrupt upon frame completion
(I.e., a flag or abort completion).
The sequence of each field in the received frame is
automatically handled by the ADLC. The frame format is
described in the Frame Format section.
Details regarding the pin functions, Tx FIFO operation, and
control and status registers are described in their respective
sections.
When a flag is detected, the Receiver establishes frame
synchronization to the flag timing. If a .series of flags is
received, the Receiver resynchrooizes to each flag.
When a closing flag is received, the frame is terminated.
The 16 bits preceding the closing flag are regarded as
the FCS and are not transferred to the MPU. Whatever
data is present in the most significant byte portion of the
receiver buffer register is right justified and transferred to
the Rx FIFO. The frame boundary pointer, explained in the
Rx FIFO Register section, is set Simultaneously in
the Rx FIFO. The frame boundary pOinter sets the Frame
Valid (FV) status bit (when the frame was completed with
no error) or the Frame Check Sequence/Invalid Frame
Error (ERR) status bit (when the frame was completed with
error) when the last byte of the frame appears at the last
location of the Rx FIFO. As long as the FV or ERR status
bit is set, the data transfer from the second location of the
Rx FIFO to the last location of the Rx FIFO is inhibited.
If the frame is terminated before the internal buffer time
expires (the frame data is less than 25 bits after an
opening flag), the frame is simply ignored. Noise on
RxData during time fill can cause this kind of
invalid frame.
Any time the Rx Frame Discontinue (DISCONTINUE)
control bit is set, the ADLC discards the current frame data
in the ADLC without dropping flag synchronization. This
feature can be used to ignore a frame which is addressed
to another station.
Once synchronization has been achieved and the internal
buffer time (24 bit-times) expires, data will automatically
transfer to the Receiver Data FIFO Register (RxFIFO). The
Rx FIFO is clocked by System Control Clock (E) input to
cause received data to move through the Rx FIFO to the
last empty register .Iocation. The Receiver Data Available
(RDA) status bit indicates when data is present in the last
The reception of an abort or idle is explained in the Frame
Format section. The details regarding the pin functions,
Rx FI FO· operation, and control and status registers are
described in their respective sections.
Receiver Operation
Data and a pre-synchronized clock are provided to the
ADLC re6eiver section by means of the Receiver Serial Data
(RxData) and Receiver Data Timing Clock (RxC) inputs.
The data is a continuous strl'lam of binary bits with the
characteristic that a maximum of five 1s can occur in
succession unless abort, flag, or idling conditions occu(
The Receiver continuously (on a bit-by-bit basis) searches
for flags and aborts.
5·242
F6854/F68A54/F68B54
ADLC Receiver State Diagram
•
'Out-of-frame Abort (No IRQ)
Fig. 1 Typical Loop Configuration
Loop Mode Operation
In the loop mode the ADLC not only transmits and
receives data frames in the manner previously described,
but also has additional features for gaining and relinquishing loop control. In Figure 1, a configuration is shown
which depicts loop mode operation. The system configuration shows a primary station and several secondary
stations. The loop is always under control of the primary
station. When the primary wants to receive data, it transmits
a poll sequence and allows frame transmission to
secondary stations on the loop. Each secondary is in series
and adds one bit of delay to the loop. Secondary A in the
figure receives data from the primary via the RxData input,
delays the data one bit, and transmits it to secondary B via
the Transmitter Serial Data (TxData) output. Secondaries B,
C, and D operate in a similar manner. Therefore, data
passes through each secondary and is received back by the
primary controller.
SECONDARY STATIONS (A,B,C,D)
OPERATE IN lOOP MODE
5-243
F6854/F68A54/F68B54
on RxData. The ADlC can recognize the necessary
sequences in the data stream to automatically go on/off the
loop and to insert its own station data. This procedure is
summarized in Table 1.
Certain protocol rules must be followed that establish the
manner by which the secondary station places itself
on-loop (connects TxData to the loop), goes active on the
loop (starts transmitting data on the loop), and goes off
the loop (disconnects TxData). Otherwise, loop data to
other stations down-loop would be interrupted. The data
stream always flows the same way; the order in which
secondary terminals are serviced is determined by the
hardware configuration. The primary controller times the
delay through the loop. Should it exceed n + 1 bit-times,
where n is the number of secondary terminals on the loop,
it will indicate a loop failure. Control is transferred to a
secondary by transmitting a go-ahead signal following the
closing flag of a polling frame (request for a response from
the secondary) from the primary station. The go-ahead
from the primary is a 0 and seven 1s followed by mark
idling. The primary can abort its response request by
interrupting its idle with flags. The secondary should
immediately stop transmission and return control to the
primary. When the secondary completes its frame, a closing
flag is transmitted followed by all 1s. The primary detects
the final 01111111 (go-ahead to the primary) and resumes
control. Note that if a down-loop secondary (e.g., station D)
needs to insert information following an up-loop station
(e.g., station A), the go-ahead to station 0 is the last 0 of
the closing flag from station A followed by 1s.
1. Go On-loop - When the ADlC powers up, the
terminal station will be off line. The first task is to
become an active terminal on the loop. The ADlC must
be connected to a loop link via an external switch as
shown in Figure 2. After a hardware reset, the ADlC
loop On-line Control/Data Terminal Ready (lOC/DTR)
output will be in the HIGH state and the up-loop receive
data repeated through gate A to the down-loop stations.
Any up-loop transmission will be received by the ADlC.
The loop/Non-loop Mode (lOOP) control bit must be
set to place the ADlC in the loop mode. The ADlC now
monitors its RxData input for a string of seven consecutive 1s which will allow a station to go on line. The
loop operation may be monitored by use of the loop
Status (lOOP) status bit. After power-up and reset, this
bit is a lOW. When seven consecutive 1s are received
by the ADlC, the lOC/DTR output will go to a lOW
level, disabling gate A (refer to Figure 2), enabling
gate B and connecting the ADlC TxData output to the
down-loop stations. The up-loop data is now repeated
to the down-loop stations via the ADlC. A 1-bit delay is
inserted in the data (in NRZI mode, there will be a 2-bit
delay) as it circulates through the ADlC. The ADlC is
now oncline and the lOOP status bit will be at a HIGH.
The ADlC in the primary station should operate in a
non-loop, full-duplex mode. The ADlC in the secondaries
should operate in a loop mode, monitoring up-loop data
Table 1
Summary of Loop Mode Operation
Receiver
(Rx) Section
Transm itter
(Tx) Section
lOOP
Status Bit
Off-loop
Rx section receives data from loop and· searches
for seven 1s (when the LOC/DTR control bit
set) to goon-loop.
Inactive
1. NRZ Mode TxData output is maintained
HIGH (mark).
2. NRZI Mode TxData output reflects the
RxData input state delayed by
one bit-time. (Not normally
connected to loop.) The NRZI
data is internally decoded to
provide error-free transitions to
on-loop mode.
L
On-loop
1. When GAP/TST control bit is set, Rx section
searches for 01111111 pattern (the EOP
or go-ahead) to become the active terminal
on the loop.
2. When the LOC/DTR control bit is reset, Rx
section searches for eight 1s to go off-loop.
Inactive
1. NRZ Mode TxData output reflects RxData
input state delayed one bit-time.
2. NRZI Mode TxData output reflects RxData
input state delayed two bit-times.
H
Active
Rx section searches for flag (an interrupt from
the loop controller) at RxData input.
Received flag causes FLAG DET output to go
LOW. IRQ is generated if the RIE and FDSE
control bits are set.
TxData originates within ADLC until GAP/TST
control bit is reset and a flag or abort is
completed, then returns to on-loop Slate.
L
State
5·244
F6854/F68A54/F68B54
Fig. 2
4. Go Off-loop - The ADLC can drop off the loop (go
off-line) similar to the way it went on-line. When the
Loop On-line Control/DTR Control (LOC/DTR) control
bit is reset, the ADLC receiver section looks for eight
successive "1s" before allowing the LOC/DTR output to
return HIGH (the inactive state). Gate A in Figure 2 will
be enabled and gate B disabled allowing the loop to
maintain continuity without disturbance. The LOOP
status bit will show an off-line condition (logic HIGH).
External Loop Logic
ADLC
,-------1
I
,....-::-:-:::::-0"--1-----«
RxOata
~~~==~~}--±-r~
TxOela
I--''-I---.-jr-,
UP·LOOP Da'.
DOWN-lOOP Data
I
I
I
L _______ J
Pin Functions
All inputs of the ADLC are high-impedance and
TTL-level compatible. All outputs of the ADLC are compatible with standard TTL. Interrupt Request (IRQ),
however, is an open-drain output (no internal pull-up).
2. Go Active after Poll - The receiver section will
monitor the up-link data for a general or addressed
poll command; the Tx FIFO should be loaded with
data so that when the go-ahead sequence of a 0
followed by seven 1s (01111111--) is detected,
transmission can be initiated immediately. When the
polling frame is detected, the Go Active On PolllTest
(GAP/TST) control bit must be set. A minimum of seven
bit-times are available to set this control bit after the
closing flag of the poll. When the go-ahead is detected
by the Receiver, the ADLC will automatically change the
seventh 1 to a 0 so that the repeated sequence out
gate B in Figure 2 is now an opening flag sequence
(01111110). Transmission now continues from the Tx FIFO
with data (address, control, etc.) as previously described.
When the ADLC has gone active-on-poll, the LOOP
status bit will go to a Law. The Receiver searches for a
flag, which indicates that the primary station is interrupting the current operation.
Interface for MPU
Bidirectional Data 110 Lines (00-07)
These data bus I/O ports allow the data transfer between
ADLC and system bus. The data bus drivers are 3-state
devices that remain in the high-impedance (OFF) state
except when the MPU performs an ADLC Read operation.
System Control Clock (E)
E activates the address inputs (CS, RSo and RS,) and
Read/Write input (RIW) and enables the data transfer on
the data bus. E also moves data through the Tx FIFO and
Rx FIFO. E should be a free-running clock, such as the
F6800 MPU system clock.
Chip Select (CS)
An ADLC Read or Write operation is enabled only when the
CS input is LOW and the E input is HIGH (E·CS).
3. Go Inactive when On-loop - The GAPITST control
bit may be reset at any time during transmission. When
the frame is complete (the closing flag or abort is
transmitted), the loop is automatically released and the
station reverts back to being just a 1-bit delay in the
loop, repeating up-link data. If the GAPITST control bit
is not reset by software and the final frame is transmitted
(F/M Idle control bit = LOW), then the Transmitter will
mark idle and will not release the loop to up-loop data.
A transmitter abort command would have to be used in
this case in order to go inactive when on the loop. Also,
if the Tx FIFO was not preloaded with data (address,
control, etc.) prior to changing the go-ahead character
to a flag, the ADLC will either transmit flags (active idle
character) until data is loaded (when the F/M Idle
control bit is HIGH) or will go into an underrun
condition and transmit an abort (when the F/M Idle
control bit is LOW). When an abort is transmitted, the
GAP/TST control bit is reset automatically and the
ADLC reverts to its repeating mode (TxData = delayed
RxData). When the ADLC Transmitter lets go of the
loop, the LOOP status bit will return to a HIGH, indicating normal on-loop retransmission of up-loop data.
Register Addressing Select (RSo. RS,)
When the RSo, RS, inputs are enabled by (E'CS), they
select internal registers in conjunction with the Riw input
and Address Control (AC) control bit. Register addressing
is defined in Table 2.
Read/Write (R/W)
The R/W input controls the direction of data flow on the
data bus when it is enabled by (E·CS). The bidirectional
Data Bus Interface acts as an output driver when R/W is
HIGH, and as an input buffer when LOW. It also selects the
read-only and write-only registers within the ADLC.
Chip Master Reset (RESET)
The RESET input provides a means of resetting the ADLC
from a hardware source. In the LOW state, the RESET input
causes the following:
1. RxRS and TxRS are set, causing both the receiver and
transmitter sections to be held in a reset condition.
5·245
•
F6854/F68A54/F68B54
2. Resets the following control bits: ABT. Request-to-Send
Control (RTS). LOOP. and LOC/DTR.
3. Clears all stored status condition of the status registers.
4. The RTS and LOC/DTR ouputs go HIGH; TxData goes to
the mark state (1s are transmitted).
frame and there is no further data in the Tx FIFO for a new
frame. The positive transition of RTS occurs after the
completion of a flag. an abort. or when the RTS control bit
is reset during a mark idling state. When the RESET input
is LOW. the RTS output goes HIGH.
When RESET returns HIGH (the inactive state). the transmitter
and receiver sections wlll remain in the reset state until
TxRS and RxRS are cleared via the data bus under software
control. The control register bits affected by FiESET
cannot be changed when RESET is LOW.
Clear-to-Send (CTS)
The CTS input provides a real-time inhibit to the TDRA/FC
status bit and its associated interrupt. The positive transition of CTS is stored within the ADLC to insure its occurrence will be acknowledged by the system. Th~ stored CTS
information and its associated IRQ status bit (if enabled)
are cleared by writing a HIGH in the Clear Tr
RECEIVER
LOGIC AND
CONTROL
TRANSMITTER
LOGIC AND
CONTROL
I
IRQ
TBMT
5·267
If
I
RTS
TCLK
TSQ
RCLK
RSI
5
F3846/F6856
Fig. 2
Receiver Data Path
TEST
LOOP
RIB (16)
CCR (16)
ROA
RSOF
RCYR
CONTROL
IRO
Ci
(TEST LOOP)
RCLK
FROM
RCR
TCLK
TO DATA
BUS (08·015)
TO DATA
BUS (00·07)
Fig. 3 Transmitter Data Path
FROM DATA
BUS (00·01)
TCLK CTS
Ci
FROM
TCR
TO DATA
BUS (00·0,)
FROM RCYR
LOOP REPEATER
IRSI
SYNC
FLAG
OLE
TSO
CGR(16)
5·268
F3846/F6856
Fig. 4
BOP Receive Flow Chart
Character assembly and CRC accumulation are stopped
when a closing FLAG, ABORT or GA is detected. REOM,
ABGA (If the closing character was an ABORT or GA),
RDLo-RDL2 (indicating length of last character) and
RERR (if the accumulated CRC is incorrect) status bits
are set. The last character is transferred to RDB, the
RDA output is set HIGH and the IRQ output Is set LOW.
FOREOM =
ABORT OR GO·AHEAD
RSOF
=
The CRC accumulation includes al.1 characters following
the opening FLAG through the frame check sequence
(FCS). The contents of the CRC check register (CCR) are
checked at the close of a frame if CRC 15 selected. If an
error is detected, RERR status bit Is set. Neither the FCS
nor the closing FLAG are assembled and passed on to
the CPU.
FOREOM =
FLAG
1
The receiver may be turned off after the status and last •
characters are read by the CPU by resetting the RE bit of
RCR, or it can be left active to receive additional frames.
RDA
·EOM
The closing FLAG of one frame may be used as the
opening FLAG of the next frame. Character assembly of
the next frame starts with the first non·FLAG character.
If the frame was closed with an ABORT or GA, an
opening FLAG must be detected before character
assembly of the next frame 15 started.
= 1
=
All receiver status bits except RDA are reset after the
receiver status register (RSR) is read by the CPU, The
RDA output and status bit are reset when RDB is read by
the CPU.
FLAG. ABORT
OR GO·AHEAD
If secondary address is selected, the first non·FLAG
character of a frame is compared to the contents of the
SYNC/Address Register (SAR). Data for the frame Is not
passed on to the CPU If no address l"(Iatch occurs. When
GLOBAL address is selected,
all '15' address also
results In address match.
iiili = 0
,In
Loop Repeater Operation - Loop repeater mode is a
special case of BOP. Receiver operation is the same as
for BOP, except that the NRZI decode logic 15 disabled,
frames may be terminated by a GO·AHEAD or FLAG, and
received data and GA are routed to the transmitter. The
RCLK and TCLK lines should be tied together in this
mode.
Fig. 5
BISYNC Operation - A flow chart of BISYNC receiver
operation is shown in Figure 6, and the BISYNC
message format Is illustrated in Figure 7. Characters In
BISYNC mode may be either EBCDiC or ASCII, as
programmed in the MCR. Character length defaults to
eight bits. The eighth bit, when ASCII 15 programmed,
may be used for odd parity by the CPU. It is ignored in
the recognition of the ASCII characters.
BOP Message Format
INFORMATION FIELD
(IF ANY)
010 m BITS
INCLUDED IN CRC ACCUM.
5·269
F3846/F6856
Character assembly starts after receipt of two
continuous SYNC characters and continues until the
receiver is turned off by resetting the RE bit of RCR.
Assembled characters are shifted through the RIB to the
RSPR and transferred to the ROB. The ROA output and
status bits are set HIGH each time a character is
transferred to the ROB. All characters that match the
SYNC character in non-transparent mode and OLE SYNC
pairs (if not immediately preceded by an odd number of
OLEs) in transparent mode are excluded from the ROB.
However,the RSOF output goes HIGH for one RCLK
clock period each time a SYNC character is detected.
Fig.6a
Oata must be read by the CPU each time the ROA output
goes HIGH before the next character is assembled to
prevent an overrun, resulting in loss of data. The IRQ
output goes LOW and the ROVR status bit is set if an
overrun occurs.
The receiver always starts operation in the nontransparent mode. It switches to transparent mode if a
OLE STXcharacter pair is received. The receiver will then
remain in transparent mode until a OLE ITB, DLE ETB or
OLE ETX (if not immediately preceded by an odd number
of OLEs) character pair is received.
CRC accumulation begins after the first non-SYNC
character if the first character is an SOH or STX. It
begins after the second non-SYNC character and enters
transparent mode if the first two non-SYNC characters
are OLE STX. SYNC characters in non-transparent mode
or OLE SYNC pairs in transparent mode are excluded
from the CRC accumulation. The first OLE of a OLE OLE
sequence and the OLE of OLE ITB, OLE ETB or OLE ETX
sequences are not included in the accumulation. The
CRC is checked for 0000 remainder after receipt of an
ITB, .ETB or ETX in non-transparent mode or OLE ITB,
OLE ETB or OLE ETX in transparent mode. The REaM
and RERR (a non-zero remainder is detected) status bits
are set when the closing character is transferred to the
ROB, ROA is set HIGH and IRQ is set LOW. The block
check character (BCC) following the closing character is
passed to the CPU as the next two characters. If the
closing character was an ETB or ETX, the receiver
should be reset by dropping the RE bit of RCA. If the
closing character was an ITB, CRC accumulation and
character assembly will start again on the first character
following the BeC.
All receiver status bits except ROA are reset each time
RSR is read by the CPU. The ROA output and status bit
are reset each time ROB is read by the CPU.
5-270
BISYNC Receive
F3846/F6856
Fig. 6b
Fig. 6c
BISYNC Receive
BISYNC Receive
iiiQ = 0
RDA
=
1
RDA
=
1
•
5·271
F3846/F6856
Fig. 6d
BISYNC Receive
TRANSPARENT MODE
RDA
=1
ENTER
TRANSPARENT
MODE
EXCLUDE FROM
CRC
EXCLUDE FROM
CRC
NO
RSOF= 1
RIR -ROB
5·272
RDA
=
1
F3846/F6856
Fig. 7
BISYNC Message Format
NO
CRC
SHADED AREA INCLUDED
IN CRC ACCUMULATION
Shaded area included In CRC accumulation.
BCP Operation - The flow diagram forBCP mode other
than BISYNC is shown in Figure 8, and the BCP
message format is illustrated in Figure 9. The SYNC
character is programmed in the SAR. All characters,
including the SYNC character are the length specified in
the receiver control register (RCR).
Character assembly starts after receipt of two
contiguous SYNC characters and continues until the
receiver is turned off by resetting the RE bit of RCR.
Assembled characters are shifted through the RIB to the
RSPR and transferred to the ROB. The RDA output and
status bit are set HIGH each time an assembled
character is transferred to the ROB. All characters that
match the SYNC character are excluded from the ROB, if
SYNC strip has been programmed. Only leading SYNC
characters are excluded from the ROB if SYNC stripping
has not been programmed. However, the RSOF output
goes HIGH for one RCLK clock period each time a SYNC
character is detected.
Data must be read by the CPU each time the RDA output
goes HIGH before the next character is assembled. If
not, an overrun will occur resulting in loss of data. The
IRQ output goes LOW and the ROVR status bit is set if
an overrun occurs.
. 5·273
CRC accumulation begins with the first non·SYNC
character and includes all subsequent characters if
SYNC strip is not programmed. The CRC accumulation
will include only non·SYNC characters if SYNC strip Is
programmed. The CRC accumulation is checked each
character time and the RERR status bit is set if the
remainder does not equal "0" or reset if the remainder
equals "0". Since there is no defined end·of·message
(EOM) character, the REOM status bit is not set. The
CPU must determine when the end of message occurs
and check the RERR status at that time. If an error·free
message has been received, RERR will be "0" for one
character time. RE may be dropped, thereby resetting the
receiver, after the last character has been read. If RE Is
not reset, CRC accumulation and character assembly
will begin again on the first character following the BCC.
The two characters of the BCC are output as normal
data characters.
•
F3846/F6856
Fig. 8a
BCP Receive
Fig. 8b
BCP Receive
RDA
Fig. 9
BCP Message Format
2X CHARACTER LENGTH IF
CRC SELECTED
5-274
=
1
F3846/F6856
Transmitter
The mode control SYNC/address (MCSA) register must
be programmed prior to starting transmitter operation.
The CRC bit of the receiver control register must be set
if ORC error checking is desired. The RTS bit of the
transmitter control register (TCR) must be set to turn on
the transmitter. The SOM bit of TCR may also be set at
this time and the transmitter data buffer (TOB) loaded
with the first character of the message. When RTS has
been loaded into TCR, the RTS output goes LOW. The
TSO output is held HIGH (marks) until the CTS input
goes LOW. Two SYNC or FLAG characters are then
output on TSO, if SOM has been set. Otherwise, TSO will
continue to output marks until SOM is set and the first
character is loaded into TOB. Transmitter operation after
the two SYNC or FLAG characters have been output
depends on the mode of operation. Note that TRS and
transmitter character length must be reloaded each time
TCR is updated until after the EOM bit has been set.
(programmed in MCR) are the control field. The character
. length switches to the programmed length in TCR after
the last character of the control field, unless that
character was the end of message.
The CPU must set the EOM bit of TCR when loading the
last character of the message. Character length may be
changed at this time to allow transmission of a residUal
last character. The character in TOB is followed by the
FCS (if CRC is selected) and a closing FLAG when EOM
is set. The transmitter may be turned off by resetting
FiTs after TBMT goes HIGH or it may remain active, The·
closing FLAG of one frame may be used as the opening
FLAG of the next frame by setting SOM and loading TOB
after TBMT goes HIGH. If the transmitter is left active
and SOM has not been set, FLAG charac,ters are
transmitted between frames if the GATO bit of TCR
equals "0" or marks if GATO equals "1".
Fig.10a
BOP Transmit
BOP Operati'On - Character length in BOP mode always
starts at eight bits per character each frame. It remains
eight bits until the address and control fields have been
transmitted. It then switches to the programmed length
at the start of the information field, if any, until the last
character has been transmitted. Character length
switches back to eight bits for the transmission of the
frame check sequence (FCS) and the closing FLAG.
TURN ON
TRANSMITTER
RTS = 1
A flow diagram for BOP transmitter operation is shown
in Figure 10. The secondary address is transmitted after
the initial two FLAGs. The secondary address comes
from the SYNC/address register (SAR) if the device is
programmed as a secondary station or from the TOB if
the device is programmed as a primary. If the secondary
address came from SAR, it is followed in the
transmission by the character from TOB. Characters are
transferred in parallel from SAR or TOB to the
transmitter shift register (TXR) and serially shifted, LSB
first, out the TSO output. The TBMT output and status
bit are set HIGH each time data is transferred from TOB.
The CPU must update TCR, If required, and load TOB
with the next character. An underrun occurs if this is not
done within one character time. If an underrun occurs,
the TUR status bit is set and an ABORT (11111111) is
transmitted. The output is held at a mark until SOM is
set for a new message. A transmitter overrun occurs if
TOB is updated before TBMT goes HIGH. An overrun can
result in the misinterpretation or loss of the character in
TOB. The TOR status bit is set when an overrun occurs.
80M =1
The least significant bit (LSB) of each character, starting
with the secondary address is examined. The first
character with an LSB = "1" denotes the last character
of the address field. The next one or two characters
5-275
F3846/F6856
TUR and TOR status bits are reset whenever the
transmitter status register (TSR) is read. The TBMT
output and status bit are reset when TDB is loaded.
A message may be terminated at any time with an
ABORT by setting the TACG bit of TCA. This causes the
TSO output to go immediately to mark condition until
SOM is set.
CRC accumulation begins with the first non·FLAG
character and includes all subsequent characters up to
and including the last data character. The accumulated
CRC is then transmitted as the FCS following the last
data character, if CRC is selected.
Data transmitted on the TSO output is monitored
continuously for five consecutive "1 s." A "0" is inserted
in the data stream each time this condition occurs. This
insures that a data character will not be interpreted as a
FLAG, ABORT or GA at the received end.
Fig. 10c
Fig. 10b
BOP Transmit
TACG = 1
TO ABORT
iiiQ
=0
5·276
BOP Transmit
F3846/F6856
Loop Repeater Operation - Loop repeater mode is a
special case of BOP. The primary station in the loop
should be programmed for normal BOP primary
operation. The GATO bit of TCR is used to initiate a
polling sequence. When this bit is set, marks are
transmitted after the closing FLAG of a frame. The last
"0" of the closing FLAG and the next seven "1s" are
interpreted down·loop as a GO-AHEAD. The end of the
polling sequence is detected when the ABGA (received
GA) bit of the RSR is set.
as a OLE STX command and the transmitter begins
transparent mode operation. The transmitter wi II remai n
in transparent mode until the end of the message.
The TBMT output and status bit are set HIGH each time
data is transferred from TOB. The CPU should update
TCR, if required, and load TOB with the next character.
An underrun occurs if this is not done within one
character time, and the TUR status bit is set and SYNC
characters (or OLE SYNC pairs in transparent mode) are
transmitted until TOB is updated. A transmitter overrun
occurs if TOB is updated before TBMT goes HIGH. An
overrun can result in the misinterpretation or loss of the
character in TOB. The TOR status bit is set when an
overrun occurs.
Down-loop stations should be programmed as. BOP
secondary, loop repeater (LRSS
"1" in MCR). In this
mode, data received at the RSI input is delayed one bit
time and output on TSO. When data is to be transmitted
in this mode, the CPU should set RTSand SOM and load
the first character into TOB. The CrS input is ignored in
this mode. The transmitter waits for a received GA.
When a received GA is detected, the seventh ''1'" is
changed to a "0," creating a FLAG. This prevents
the down-loop station from receiving a GA, reserving the
line for the transmitting station. The TBMT output and
. status bit are set and transmitter operation proceeds in
normal BOP operation, except that the NRZI encode
logic is disabled.
=
The EOM bit of TCR, GATO (if in transparent mode) and •
TACG (if the accumulated CRC is to be transmitted as
the block check character) should be set when the last
character is loaded into TOB. The last character must be
an ITB, ETB or ETX if CRC is used. A 16-bit BCC, if
selected, is transmitted following the last character. The
last character is followed by marks for a minimum of
one character time if no BCC is transmitted.
A second block of data may be transmitted immediately
following the BCC by setting SOMand loading TOB after
TBMT goes HIGH. The transmitter may be turned off at
this time by resetting RTS. The transmitter transmits
marks following the BCC for a minimum of one character
time if SOM is not set.
When the last character and FCS have been transmitted,
the message is terminated with a GA. The TSO output
switches back to RSI delayed one bit time. pown-Ioop
stations may then capture the line by detecting the GA.
The RCLK and TCLK lines should be tied together in
this mode.
CRC accumulation begins after the first non-SYNC
character for non-transparent mode, or after the second
non-SYNC character if the message starts in transparent
mode. The CRC continues up to and including the last
character. SYNC characters or OLE SYNC pairs caused
by a transmitter underrun are not included. Forced OLE
characters in transparent mode are not included. The
forced OLE of a OLE STX pair which occurs after the
start of the message is included. (See Figure 7.)
BISYNC Operation - A flow diagram for BISYNC
transmitter operation is shown in Figure 11. Character
length for BISYNC mode defaults to eight bits per
character. The transmitter always assumes non·
transparent mode unless forced to transparent mode by
the CPU.
The message format following the initial SYNC pair
depends on the action of the CPU. If the transmitter data
buffer (TOB) has not been loaded with the first character
of the message, SYNC characters are output on TSO
until a TOBload. This can occur only with an 8-bit data
bus, since TCR and TOB are loaded simultaneously for a
16·bit data bus. The character from TOB, when available,
is transferred to the transmitter shift register, (TSR) and
serially shifted out the TSO output. The character in TOB
is preceded by a contiguous OLE when GATO (transmit
OLE) is set. The GATO bit is cancelled after it has been
internally processed. The first occurrence is interpreted
TUR and TOR status bits are reset whenever the
transmitter status register (TSR) is read. The TBMT
output and status bit are reset when TOB is loaded.
5-277
F3846/F6856
Flg.11a
BISYNC Transmit
Fig.11b
BISYNC Transmit
CD
5·278
Not included in CRC accumulation
F3846/F6856
Fig.11c
BISYNC Transmit
TRANSPARENT
•
CD
Not included in GRG accumulation
5-279
F3846/F6856
Fig. 11d
BISYNC Transmit
TURN OFF
XMTR
5·280
F3846/F6856
BCP Operation - The flow diagram for BCP mode other
than BISYNC is shown in Figure 12. The SYNC character
is programmed in the SYNC/address register (SAR). All
characters are the length specified in the transmitter
control register (TCR).
Fig. 12a
BCP Transmit
TURN ON
TRANSMITTER
RTS = 1
The message format following the initial SYNC pair
depends on the action of the CPU. If the transmitter data
buffer has not been loaded with the first character of the
message, SYNC characters are transmitted until a TOB
load. This can occur only with an 8-bit data bus, since
TCR and TOB are loaded simultaneously for a 16-bit data
bus. The character from TOB, when available, is
transferred to the Transmitter Shift Register (TXR) and
serially shifted out the TSO output. The TBMT output
and status bit are set HIGH each time data is transferred
from TOB. The CPU should update TCR, if required, and
load TOB with the next character. An underrun occurs if
this is not done within one character time, and the TUR
status bit is set and SYNC characters (marks, if SYNC
stripping is not programmed) are transmitted until TOB
is updated. A transmitter overrun occurs if TOB is
updated before TBMT goes HIGH. An overrun can result
in the misinterpretation or loss of the character in TOB.
The TOR status bit is set when .an overrun occurs.
RTS
=0
SOM = 1
The EOM bit of TCR and TACG (if the accumulated CRC
is to be transmitted as the block check characte'r) should
be set when the last character is loaded into TOB. The
last character is followed by a BCC and a pad character
if CRC is selected, or the pad character only if CRC is
not selected. The transmitter may be turned off by
resetting RTS after TBMT goes HIGH.
CRC accumulation (see ErrorContro/ table) includes all
non-SYNC characters. The CRC generation register
(CGR) in BCP mode is defined as twice the character
length.
TUR and TOR status bits are reset whenever the
transmitter status register (TSR) is read. The TBMT
output and status bit are reset when TOB is loaded.
5-281
•
F3846/F6856
Fig. 12b
Fig. 12c
BCP Transmit
iiiQ =
0
(2) Not included in CRC accumulation
5-282
BCP Transmit.
F3846/F6856
Data Bus Control (F6856)
The CPU uses the register address (Ao-A2), byte select
(BYTE), chip enable (CE), read/write (RIW), and enable (E)
inputs to control information transfer on the data bus.
The byte select input specifies a 16-bit data bus when
BYTE = "0" or an 8-bit data bus when BYTE = "1." For
an 8-bit data bus, Do through D7 may be wired-OR with
the corresponding pins, D8 through D15.
=
A read operation (Riw
"1") is initiated on the leading
edge of E. The other control inputs (Ao-A2, BYTE, CE,
and RIW) must be stable before the leading edge of E
(see Bus Timing Characteristics). Any unused bits in the
addressed register are "0." D8-D15 contain receiver
status when TSR is read using a 16-bit bus. Status bits
are reset on the trailing edge of E when the appropriate
register is read.
Data is loaded into the addressed register on the trailing
edge of E for a write (RiW = "0") operation. The other
control inputs must be stable prior to the leading edge
of E. TBMT is reset on the trailing edge of E when TCDR
(16-bit bus) or TDB (8-bit bus) is addressed.
Data Bus Control (F3846)
Bus Control for the F3846 has the same characteristics
as the F6856 with only RD required for read rather than
both E and Riw being "1 "s, and only WR required for
write rather than E being a "1" and R/W being a "0."
Register Addresses
R/W
BYTE = "0"
16-Bit
Data Bus
0
0
1
0
BYTE = 1
8-Bit Data
Bus Do-D7
Wired-OR
to D8-D15
X
X
X
X
X
0
1
1
0
0
0
0
0
1
0
0
Register
Ao
o
1
o
o
o
1
1
0
o
o
1
o
o
o
o
o
o
RSDR
TCDR
MCSA
RCTSl (TSR)
RCTSu (RCR)
RSDRl (RDB)
RSDRu (RSR)
TCDRl (TOB)
TCDRu (TCR)
MCSAl (SAR)
MCSAu (MCR)
RCTSl (TSR)
RCTSu (RCR)
5-283
RD
WR
o
1
o
o
o
1
o
o
o
1
o
1
o
o
o
o
1
o
F3846/F6856
Programming
The mode control SYNC/address (MCSA) register is a
directly addressable write-only register used to configure
the SPCC for the user's specific data communications
environment. MCSA should be programmed after
initialization and prior to initiating data transmission or
reception. It may be changed at any time that both the
receiver and transmitter are disabled. The default mode
(after initialization) is BOP primary with one byte control
field, NRZI encoding, a-bit character length, and error
control using CRC-CCITT preset to "1s." The lower byte,
SYNC/address, is not used in BOP primary mode.
The transmitter control and data register (TCDR) is a
directly addressable write-only register that controls the
format of the transmitted data. The lower byte (TDB)
contains the data characters to be transmitted. The
upper byte (TCR) contains control information relating
specifically to the data being transmitted. TCDR may be
updated whenever the TBMT output is HIGH. The default
mode for this register is all "Os" corresponding to
transmitter disabled.
The upper byte (RCR) of the receiver control and
transmitter status register (RCTS) is a directly
addressable write-only register that contains control
information specifically related to the receipt of data and
the i5'i'R and MISC general-purpose outputs. Those bits
that control the received character length should not be
changed while the receiver is enabled. The default value
of RCR is all "Os", corresponding to receiver disabled
and general-purpose outputs at a HIGH level.
Specific definition of the format of the addressable
registers is given in the following section. Address
information is given in the Data Bus Control section.
5-284
F3846/F6856
Addressable Register Format
Mode Control SYNC/Address (MCSA) Register - Write-Only
15
14
13
6
7
PROTOCOL
SELECT
Bit
0-7
8
5
4
3
Name
Mode
SAR
Function
BOP
BISYNC
BCP
SYNC/address register
Secondary address for secondary station mode
Not used
SYNC character
BOP
o = CCITT preset to all
EC
Error control
BCP
"O"s
1 = CCITT preset to all "1 "s
o = CRC-16 preset to all "O"s
1 = CCITT preset to all "O"s
Same as BISYNC for 8-bit character length only
9
LOOP
All
Self-test loop mode, TSO loop to RSI internally
10
NRZI
All
o=
1
12
CC
=
NRZ data
NRZI, zero complementing
BOP
BISYNC
BCP
o = 1 control
BOP
o=
LRSS
BISYNC
BCP
13-15
o
SYNC/SECONDARY ADDRESS
BISYNC
11
2
All
byte, 1
= 2 control bytes
Not used
Not used
Loop repeater/SYNC strip
Normal mode
1 = Loop repeater mode
Not used
o = Tx mark for FILL character (strip leading SYNCs only)
1 = Tx SYNC for FILL character (strip all SYNCs)
Protocol select
5-285
15 14 13
o 0 0 BOP, Primary
o 1 0 BOP, Secondary
o 1 1 BOP, Secondary, Global
1 0 0 BCP
1
0 BISYNC - ASCII
1 1
BISYNC - EBCDIC
o 0
Reserved
o
Reserved
•
F3846/F6856
Addressable Register Format (Cont'd)
Transmitter Control and Data Register (TCOR) - Write-Only
15
14
13
12
10
11
8
9
7
6
5
Bit
Name
TOB
8-10
TCLo-TCL2
Mode
All
BOP/BCP
BISYNC
3
2
Function
Transmitter data buffer
Transmitter character length
10
8
9
0
0
0
8 bits
1
0
0
1
1
2
0
0
1
1
0
3
0
1
4
0
1
1
0
5
.1
0
1
6
7
1
1
Character length automatically 8 bits
=
11
RTS
All
Request to Se~'O"
"1" on RTS output;
"1"
"0" on RTS output.
12
EOM
All
End of message_ "1" defines character in TBD as last data
character of message. This bit is self-cancelling.
13
GATO
BCP
BOP
BISYNC/
BCP
Transmit abort/CRC generate
"1"
Transmit abort
"0" = No CRC on transmitted message
"1" = Transmit block check character after last data character
BISYNC
15
TACG
SOM
=
Go-aheadltransmit OLE
"0"
FLAGs transmitted between frames
"1" = Marks transmitted between frames
"1"
Transmit OLE character ahead of character in TDB. Enter
transparent mode.
Not used
BOP
14
o
TRANSMITTER DATA BUFFER
TCL2 - TCLo
0-7
4
All
=
=
=
Start of message. Initiates start of message, causing SYNCs or
FLAGs to be transmitted. This bit is self-cancelling.
5-286
F3846/F6856
Addressable Register Format (Cont'd)
Receiver Control and Transmitter Status Register (RCTS) - Read/Write
15
14
13
Bit
12
Name
0
DSR
1
2
11
10
9
8
7
6
5
Mode
4
3
2
o
Function
All
Data set ready; equals "1" when DSR input is LOW.
CD
All
Carrier detect; equals "1" when CD input is LOW.
CTS
All
Clear to send; equals "1" when CTS input is LOW.
5
TOR
All
Transmitter overrun; "1"
was ready.
6
TBMT
All
Transmitter buffer empty; "1"
control information in TCDR.
7
TUR
All
Transmitter underrun; "1" = CPU failed to load TDB in time. Abort
is transmitted in BOP mode. When TUR occurs, FILL characters
are transmitted in BISYNC or BCP. TUR occurs along with a LOW
level of IRQ output.
RCLo-RCL1
All
Receiver character length
8
9
8-bitS
0
0
1
0
5
0
6
7
10
RE
All
Receiver enable; "1" enables receiver
11
CRC
All
"0" = No CRC (Transmit/Receive)
"1" = CRC selected
14
MISC
All
Miscellaneous; "0" = "1" on MISC output;
"1" = "0" on MISC output.
15
DTR
All
Data terminal ready; "0" = "1" on DTR output;
"1" = "0" on DTR output.
Not used
3·4
8·9
12-13
= CPU updated TCDR before the SPCC
= CPU may load new data and/or
Not used
5-287
•
F3846/F6856
Addressable Register Format (Cont'd)
Receiver Status and Data Register (RSDR) - Read Only
14
13
12
11
10
9
8
7
6
5
4
3
2
o
RDL2 - RDLo
Bit
0-7
Name
Mode
Function
ROB
All
Receiver data buffer
RERR
All
Received error; "1" = CRC error occurred on received message.
Asserted when last character isin ROB.
RDLo-RDL2
BOP only
Received last character length; corresponds to the number of pits
in last character. 000 = 8 bits, 100 = 1 bit, 010 = 2 bits, etc.
12
ABGA
BOP only
Abort/go-ahead; corresponds to received abort if RERR
go-ahead if RERR = "0".
13
REaM
8
9-11
= "1" or
BOP
BISYNC
Received end-of-message
"1" = received FLAG, abort or go-ahead
"1" = received ITB, ETB, or ETX (preceded by OLE in transparent
mode).
14
RDA
All
Received data available. "1" indicates valid data available in ROB.
15
ROVR
All
Receiver overrun. "1" indicates CPU failed to read data in ROB
before next character was assembled. Accompanied by a LOW on
IRQ output.
5-288
F3846/F6856
Absolute Maximum Ratings
Operating Temperature
Ceramic
Cermet
Plastic
Storage Temperature
Supply Voltage
Input/Output Voltage
Input Voltage
Output Voltage
-55°C,
- 55°C,
O°C,
-65°C,
-0.3 V,
-0.3 V,
-0.3 V,
-0.3 V,
+125°C
+ 125°C
+ 70°C
+150°C
+7.0 V
+ 10 V
+15V
+ 10 V
This device contains circuitry to protect the inputs against damage due
to high static vollages or eleclric fields; however, it is advised Ihal
normal precautions be taken to avoid application of any voltage higher
than maximum rated voltages.
DC Characteristics
Symbol
Over the Operating Temperature Range
Parameter
Voo
Supply Voltage
VIL
VILC
VIH
VIHC
Input Voltage
Input LOW
Clock LOW
Input HIGH
Clock HIGH
VOL
VOH
Output Voltage
Output LOW
Output HIGH
III
ILO
Leakage Current
Input Leakage
Output Leakage
100
Supply Current
CI
Co
CIO
Capacitance
Input
Output
Bus In
Typ
Max
4.75
5.0
5.25
V
0.8
0.8
Voo
Voo
V
V
V
V
0.4
V
V
2.5
±10
p.A
p.A
120
10
15
20
-0.3
-0.3
2.0
2.4
2.4
Serial Port Timing Characteristics (Refer to Figure 13)
Symbol
Parameter
Min
tRS
RSI Set-up Time
100
ns
tRH
RSI Hold Time
50
ns
tTSO
Transmit Serial Data
tcpw
Clock Pulse Width
Max
200
400
Unit
ns
ns
5-289
Condition
Unit
Min
10L
10H
= 1.6 mA
= -300 p.A
mA
Voo
= 5.25 V
pF
pF
pF
Measured at + 27"C
and 1 MHz
II
F3846/F6856
Bus Timing Characteristics (Refer to Figure 14)
Symbol
Parameter
Min
Max
Unit
Read
tcycE
Enable Cycle Time
1.0
".$
PWEH
Enable Pulse Width, HIGH
450
ns
PWEL
Enable Pulse Width, LOW
430
ns
tAS
Set·up Time, Address and R/W
Valid to Enable Positive Transition
160
260
ns
ns
F6856
F3846
tOOR
Data Delay Time
tH
Data Hold Time
10
tAH
Address Hold Time
10
tEr, tEt
Rise and Fall Time for Enable Input
PWRL
RD, CI Pulse Width, LOW
320
ns
ns
ns
25
430
ns
ns
Write
tcycE
Enable Cycle Time
PWEH
Enable Pulse Width, HIGH
PWEL
Enable Pulse Width, LOW
tAS
Set·up Time, Address and R/W
Valid to Enable Positive Transition
F6856
F3846
1.0
".s
450
ns
430
ns
160
260
ns
ns
tosw
Data Set·up Time
195
ns
tH
Data Hold Time
10
ns
tAH
Address Hold Time
10
tEr, tEt
Rise and Fall Time for Enable Input
PWWL
WR, CI Pulse Width, LOW
Fig. 13
430
Clock and Serial Data
RCLK
RSI
TCLK
~tcpw~
TSO
~I~~~----------
I· ·1
ns
25
trsD
5·290
ns
ns
F3846/F6856
Fig.14
Read/Write Timing Diagram
READ
'E_---fV-~·- ~.w"
.
v--
V,H
VIL
V,H
A.·A" BYTE. ' RiW
VIL
VOH
DATA BUS
VOL
V,H
WRITE
'E
VIL
VIH
AO·A2, BYTE, • R/W
VIL
V,H
DATA BUS
VIL
V,H
Ci, tRo. tWii
VIL
'6856
t3840
Ordering Information
Speed
Order Code
Temperature Range
1,0 MHz
F6856P, S
F6856GP, GS
F6856DL
F6856DM
OOG
-40'G
-55°G
- 55 °G
to
to
to
to
+ 700G
+85°G
+85°G
+ 125 °G
1.0 MHz
F3846P, S
F3846GP, GS
F3846DL
F3846DM
OOG to
-40oG to
-55°G to
-55°Gto
+ 700G
+85'G
+85°G
+125°G
P = Plastic Package
S
= CER·DIP
Package
5-291
,.
F3846/F6856
5·292
F38456/F68456
Multiple Protocol
Communications Controller
Advance Product Information
Microprocessor Product
Description
•
The Fairchild F38456/F68456 Multiple Protocol
Communications Controller (MPCC) is a programmable
microprocessor peripheral that interfaces a computer
system to a serial data communications channel with
minimum system overhead. It is designed to satisfy the
major interface requirements for asynchronous,
synchronous bit-oriented protocols (BOP), or
synchronous byte control protocols (BCP). The MPCC is
well-suited for application in computer-to-computer
communication, or control of network trunk lines.
•
The MPCC is organized to interface with either an 8- or
16-bit bidirectional data bus, is fully TIL compatible, and
operates from a single + 5 V supply.
•
•
•
•
•
F6800, Z80, and 8080 Bus Compatible
Data Rate from DC to 2M BPS
Asynchronous Protocols:
• 5- to 8·Blt Character Length
• Parity - Even, Odd or None
• Stops Bits - 1, 1_5 or 2
• Clock Rates - 1X, 8X, 16X or 32X Baud Rate
• Interrupt on Received Parity or Framing Error
Blt·Oriented Line·Control Protocols - SDLC, ADCCP,
HDLC
• Automatic Detection and Generation of Special
Control Sequences (e.g., Flag, Abort, Go·Ahead)
• Zero Insertion and Deletion
• Primary or Secondary Station Select
• Secondary Station Address Recognition
• Global Address Recognition
• Automatic Extended Address
• One or Two Control Bytes
• Data Character Length from 5· to 8·Bits with 1- to
8·Bit Residual Last Character
• CCITT·CRC Error Detection
• Interrupt on End of Message
• IBM Retail Store Loop Mode
Byte Control Protocol: IBM BISYNC
• Special Character Generation: OLE, SYNC
• Special Character Detection: OLE, SYNC, SOH,
STX, ITB, ETB, ETX, ENQ
• ASCII or EBCDIC
• Normal and Transparent Text Mode
• 8·Bit Character Length
• Automatic OLE Stuff·Stripping in Transparent
Mode
• Automatic Fill Character Insertion with Selectable
Stripping
• Selectable Leading Pad Transmission (Hex 55, 55)
• CCITT, CRC-16 or VRC/LRC Error Detection
• Interrupt on End of Message
5-293
Byte Control Protocols: DDCMP and Other Custom
BCP
• Programmable SYNC Character
• 5· to 8·Blt Character Length
• Selectable Leading Pad Transmission (Hex 55, 55)
• Selectable CRC Error Detection
• Automatic Fill Character Insertion with Selectable
Stripping
• CCITT, CRC·16, CRC·12, or (Odd/Even) VRC/LRC
Directly Addressable Parameter Control Registers:
Mode, SYNC/Address, Transmitter Control, and
Receiver Control
• Separate Addressable Status and Data Registers
for Receiver and Transmitter
• Modem Handshake Signals: RTS, CTS, DTR, DSR,
and CD
• NRZ or NRZI (Complement on Zero) Serial Data
• Full or Half·Duplex Operation
• Self· Test Loop·Back Mode
• 8· or 16·Bit Bidirectional 3 State Data Bus
• 40 Pin Ceramic or Plastic Package
Connection Diagram
Vee
TSO
TCLK
RCLK
RTS
RSI
e;
RSOF
·R/iN
DSR
'(WR)
Do
D8
D,
D,
D10
D2
D11
D3
D,
Ds
D,
D7
Co
CTS
A2
A,
TBMT
Ao
IRQ
BYTE
DTR
·E
Mise
, (AD)
CE
Vss
"F68456 Designation
tF38456 Designation
•
F38456/F68456
Signal Functions
D.
D,
TSO
TRANSMIT/
RECEIVE
RSI
0,
03
0,
0,
0,
07
0,
TCLK
RCLK
CD
m
MODEM STATUS
AND CONTROL
eTS
DTIi
DSIi
MJsr:
D.
0,.
0 11
D"
0'3
0,.
015
CPU INTERFACE
AND CONTROL
RDA
TRANSMITTER/RECEIVER
STATUS AND CONTROL
Ao
TBMT
A,
RSOF
A,
E (AD)
R/W (WR)
CE
BYTE
iiiQ
tI
Vee
Vss
Block Diagram
00-015
¢=)
I/O
BUFFERS
-168IT5_
--168IT5----
MODE CONTROL
SYNC/ADRESS
REGISTER
RECEIVER CONTROL
TRANSMITTER STATUS
REGISTER
~
I
if
Ao-A2
BYTE
R/W (WA)
E(AD)
CE
DATA
BUS
CONTROL
~
r-----v
-
Vss
RDA
RCTS
RSDR
TCDR
RECEIVER
ST ATUS/DAT A
REGISTER
Vee
RSOF
MCSA
I
~~
It
{~
TRANSMITTER
CONTROUDATA
REGISTER
lr
~>
RECEIVER
LOGIC AND
CONTROL
TRANSMITTER
LOGIC AND
CONTROL
It
I
IRQ
TBMT
5·294
I
RTS
TCLK
TSO
RCLK
RSI
F38456/F68456
The F38456/F68456 signal functions are described in the
following table.
Mnemonic
Pin No.
Name
Description
TSO
1
Transmitter
Serial Output
This output signal is the transmitted serial data. Data
changes on the positive going edge of TCLK.
RSI
38
Received Serial
Input
This Input signal is the received serial data. Data changes
on the negative going edge of RCLK.
TCLK
2
Transmitter Clock
Timing of the transmitter logic is provided by this input signa I.
Frequency is the same as the transmitted baud rate.
RCLK
39
Receiver Clock
Timing for the receiver logic is provided by this input.
Frequency is the same as the received baud rate.
CD
27
Carrier Detect
This input is general·purpose in nature. It can be tested by
reading the transmitter status register.
RTS
3
Request to Send
This output is used with clear to send to enable the
transmitter. It may be set low by programming the appropriat e
bit of the transmitter control register.
CTS
26
Clear to Send
This input signal is used with request to send to enable the
transmitter. It can be tested by reading the transmitter status
register.
DTR
23
Data Terminal
Ready
This is a general·purpose output. It can be set low by
programming the appropriate bit of the receiver control
register.
DSR
36
Data Set Ready
This is a general-purpose input. It can be tested by the CPU by
reading the transmitter status register.
22
Miscellaneous
This is a general·purpose input/output. It can be set low by
programming the appropriate bit of the register; it can be
tested by the CPU by reading the receiver control register.
RDA
14
Receiver Data
Available
A high level on this output signal indicates an assembled
character is in the receiver buffer. RDA is reset on the trailing
edge of enable when the receiver buffer is read by the CPU.
TBMT
25
Transmitter
Buffer Empty
A high level indicates the device is ready to receive new data
and/or control information from the CPU. This output signal is
reset on the leading edge of the first transmitter clock; it
follows the trailing edge of enable when the transmitter buffe
is loaded.
Transmit/Receive
Modem
Status/Control
-
--
MISC
Transmitter/
Receiver
Status/Control
5-295
&I
F38456/F68456
Mnemonic
Pin No.
Name
Description
37
Received Sync
or Flag
RSOF is high for one receiver clock period when a received
sync or flag character Is detected on this output signal.
0 0 .015
6·13
28·35
Data Bus
These are 16 bidirectional input/output data lines which
control information to and from the CPU. Do . 0 7 can be wired
to 0 8 • 0 15 for use as an 8·bit data bus.
Ao· A2
15·17
Register Address
These input signals select internal data, status, and control
registers. They may be selected as 8· or 16,bit registers.
E
19
Enable
(F6456)
A strobe on this input causes information transfer between
the data bus and the addressed register when the chip enable
input is low.
RD
19
Read Pulse
(F38456)
A negative pulse on this input with address causes chip
enable to transfer the data bus information to the addressed
register.
R/W
5
Read/Write
(F68456)
A high level on this input allows data from the addressed
register to be output to the data bus. A low level allows data
from the bus to be loaded into the addressed register.
WR
5
Write Pulse
(F38456)
A negative pulse on this input with address causes chip
enable to transfer the data bus information to the addressed
register.
CE
21
Chip Enable
A low level on this input signal enables a data bus transfer
with enable.
BYTE
18
Byte
A high level on this input signal indicates an 8·bit data bus. A
low level indicates a 16·bit bus.
IRQ
24
Interrupt Request
This output goes low to indicate a change in the internal
.;ldtUS of the device. The status bits linked to this output are
receiver overrun (ROVR), received end·of·message (REOM) and
transmitter underrun (TUR). IRQ is reset on the trailing edge 0
enable when the associated status register is read.
Ci
4
Chip Initialize
A low level initializes the internal control registers and timing
on this input signal.
Voo
40
Power Supply
Power supply input:
Vss
20
Ground
Ground: 0 V reference
Transmitter/
Receiver
Status/Control
RSOF
CPU Interface
and Control
Power
5·296
+5 V
± 5%
F68488
General-Purpose
Interface Adapter
Microprocessor Product
Description
The F68488 General-Purpose Interface Adapter (GPIA)
provides the means to interface between an IEEE-488
standard instrument bus and the F6800. The 488 instrument
bus provides a means for controlling and moving data from
complex systems of multiple instruments.
Logic Symbol
EOI RFD DAV DAC IBo IB, IB2 IBa IB,
IBs 166 IB7
CS
R/W
The F68488 will automatically handle all handshake protocol
needed on the instrument bus.
•
•
•
•
•
•
•
•
•
•
•
Single or Dual Primary Address Recognition
Secondary Address Capability
Complete Source and Acceptor Handshakes
Programmable Interrupts
RFD HOld-Off to Prevent Data Overrun
Operates with DMA Controller
Serial and Parallel Polling Capability
Talk-Only or Listen-Only Capability
Selectable Automatic Features to Minimize Software
Synchronization Trigger Output
F6800 Bus Compatible
Pin Names
DBO-DB?
CS
R/W
RS(j,' RS1, RS2
IRQ
RESET
DMA GRANT
DMA REQUEST
ASE
IBO-IB?
DAC
RFD
DAV
ATN
IFC
SRQ
REN
EOI
TRIG
TiR1, TiR2
E
Vss
Vee
37
RSo
IRQ
38
AS,
ASE
39
RS2
'9
RESET
DMA REQUEST
F68488
DMA GRANT
23
TRIG
2'
ATN
T/R1
28
2'
IFC
T/R2
27
22
REN
8'
Vee
Vss
9
10
11
12
13
14
= Pin 20
= Pin 1
Connection Diagram
40-Pin DIP
IRQ
Vss
DMA GRANT
RS 2
cs
RS,
ASE
RSo
R/W
IBo
E
IB,
DBo
IB2
DB,
IB3
DB2
IB,
DBa
IBs
DB,
lB.
DBs
IB7
DB.
T/R,
DB7
T/R2
DMA REQUEST
ATN
DAV
EOI
DAC
TRIG
AFD
SRQ
RESET
REN
iFC
Vee
(Top View)
5·297
'5
SRQ
26
E
Bidirectional Data Lines
Chip Select Input
Read/Write Input
Register Select Inputs
Interrupt Request Output
Chip Reset Input
DMATransfer in Progress Input
DMA Transfer Ready Output
Address Switch Enable Output
Bidirectional ASCII Bus
Bidirectional Data Accepted Line
Bidirectional Ready for Data Line
Bidirectional Data Valid Line
Attention Input
Interface Clear Input
Service Request Output
Remote Enable Input
Bidirectional End or Identify Line
Group Execute Trigger Output
Transmit/Receive Control Outputs
Enable Clock Input
Ground
+5 V Power Supply
'0
•
F68488
Functional Description
in the sequence can be initiated until the previous step is
completed. Information transfer can proceed as fast as the
devices can respond, but no faster than the slowest device
presently addressed as active. This permits several devices of
different speeds to receive the same data concurrently.
The IEEE-488 instrument bus standard is a bit-parallel,
byte-serial bus structure designed for communication to and
from intelligent instruments. Using this standard, many' .
instruments may be interconnected and remotely and
automatically controlled or programmed. Data may be taken
from, sent to or transferred between instruments. A bus
controller dictates the role of each device by making the
attention (ATN) line true and sending talk or listen addresses
on the instrument bus data lines; those devices that have
matching addresses are activated. Device addresses are set
into each GPIA from switches or jumpers on a pc board by a
microprocessor as a part of the initialization sequence.
The GPIA is designed to work with standard 488-bus driver les
to meet the complete electrical specifications of the IEEE-488
bus. Additionally, a powered-off instrument may be powered-on
without disturbing the 488 bus. With some additional logic, the
GPIA could be used with other microprocessors.
The F68488 GPIA has been designed to interface the F6800
microprocessor with the complex protocol of the IEEE-488
instrument bus. Many instrument bus protocol functions are
handled automatically by the GPIA and require no additional
MPU action. Other functions require minimum MPU response
due to a large number of internal registers conveying
information on the state of the GPIA and the instrument bus.
When the controller makes the ATN line true, instrument bus
commands may also be sent to single or multiple GPIAs.
Information is transmitted on the instrument bus data lines
under sequential control of the three handshake lines. No step
Fig. 1. Functional Diagram
(8 LINES)
-----
INTERFACE
MANAGEMENT
I
+
·CONtAOL LlNES--"
tion register to supply additional control bits during certain
instructions. In addition, the control unit has a machine instruction pre-fetch mechanism which overlaps the fetching
of the next instruction from memory during execution of
short-cycle instructions, such as arithmetic-and-Iogic (ALU)
instructions. This pre-fetch capability and the microprogram pipeline give the F9445 very fast and efficient instruction execution.
.
Archltectllre
The F9445 microprocessor comprises three main blocks:
the data path, the control unit, and the timing generator.
Data Path
The data path is 16 bits wide and is responsi ble for all the
processing of data and address in the system. In many
cases, data and address may be proceSsed simultaneously.
Timing Generator
The timing .generator produces the system timings for the
F9445 internal registers, memory, I/O, and console.
The data path includes the following blocks (see Figure 1):
Register File (ACO,.AC1, AC2, AC3, SP, FP)
Program Counter (PC)
Program Status Word or Status Register (pSW containing: Carry, Overflow, 32KW, ETRP flags)
Interrupt-On Flip-Flop (INTON)
Destination Mux
Source Mux
16-Bit ALU
17-Bit Shifter
5-Bit Counter (formulticycle instructions)
Bus Register Mux
Bus Register
Bus Mux and Buffer
Incrementer
The clock is divided on-chip using a 3-bit twisted ring counter. The divide ratio is 6:1 or 4:1, depending on whether a
short or long cycle is required. The long cycle can be
extended indefinitely by lowering the inputs BU5GNT,
RDYA, or RDYD. These signals hold the processor in state.
51 (using BUSGNT or ROYAl or S3 (using ROYOI until the
inputs are raised.
The twisted ring counter is also used to generate all the
strobes by a combinational decode of its outputs and certain bits of the microprogram register.
Signal Descriptions
Control Unit
The operations cif the data path components are governed
by the pipelined, microprogrammed control unit. This unit
comprises three main elements (see Figure 1): the PLA
(control store) to contain the microprogram, the pipeline
register (microprogram register) to latch the micro- •
instruction executed in the current cycle, and the instruc-
All F9445 inputs and outputs are TTL.
Information Bus
through IB1S' Pins 11 through 26 -16-bit Bus - Active
LOW bidirectional; iSo is most significant bit; address valid
rno
6·18
F9445
with STRBA strobe; data valid with STRBD strobe; 3-state
during data-channel and non-bus cycles.
write or output operation; 3-state during data-channel cycles and short cycles (BUSREO is HIGH).
Timing and Status
SYN, Pin 7 - Synchronize Output - Active every cycle;
may be used for external synchronization of memory and
I/O control.
RDYD, Pin 8 - Data Ready - Active HIGH input; used to
synchronize external devices with the F9445 during data
transfer; a LOW level halts the processor.
RDYA, Pin 4 - Address Ready - Active HIGH input; maintains address on bus when LOW.
STRBD, Pin 6 - Data Strobe - Active LOW output; active
only during memory, I/O, console, or data-channel cycles;
used as strobe for data.
RUN, Pin 37 - Run Status - Active HIGH output; LOW
when in halt state.
STRBA, Pin 5 - Strobe Memory Address Register - Active
LOW output; active only during normal memory cycles; not
active during write portion of read-modify-write cycles
(DSl, ISl, STB instructions and auto-increment/decrement
addressing modes); used as strobe for external address
register; active on I/O cycles when I/O instruction is output
onto bus.
M, Pin 36 - Memory or I/O Function - Active LOW output.
0" Pin 35 - Memory or I/O Function - Active HIGH output.
00, Pin 34 - Memory or I/O Function - Active HIGH output;
these pins indicate the type of bus transfer as shown in the
following table.
Memory
I/O
Instruction Fetch
Operand
Indirect Address
Address Save on interrupt, abort,
and trap
1 0 0
1 0 1
1 1 0
1 1 1
Input or Output
Data Channel Acknowledge
Read Console Code
Console Data
0
0
0 1
Single-phase clock;
BUSGNT, Pin 3 - Bus Grant - Active HIGH input; used for
multi-m'icroprocessor operation; a LOW level inhibits add ress output and halts the processor.
Service Request
The order of priority of requests and interrupts, from highest to lowest, is as follows: MR, ABORT, DCHREQ, Stack
Overflow Interrupt, INTREQ, and CONREQ,
MR, Pin 33- Master Reset-Active LOW input; a LOW
level causes the processor to enter a wait state after completing the next full cycle; if that cycle is a write, it is inhibited (changed to read); sets the F9445 to 32K mode with
trap enabled.
M 0, 00 State Indicated
o
CLK, Pin 40 - Clock Input positive-edge triggered.
BUSLOCK, Pin 2 - Bus Lock - Active LOW open collector
output; set during read portion of read-modify-write cycles
(on DSl, ISl, STB, and auto-increment/decrement), reset
during write portion of those cycles; used in multimicroprocessor system.
If a skip is taken on an arithmetic-and-Iogic (ALU) instruction, the next instruction is fetched but not executed. In
such fetches, t.he M and 0 lines will indicate the following
states.
o
INTON, Pin 27 -Interrupt-On Status - Active HIGH output; copy of Interrupt-On flag; HIGH when interrupts enabled.
Arbitration
BUSREQ, Pin 38 - Bus Request - Active LOW output; indicates that a bus cycle is required; usefulin multimicroprocessor system.
M 0,00 Function
0 0 0
0 0 1
0 1 0
0 1 1
CARRY, Pin 39 - Carry Status - Active HIGH output; copy
of carry bit.
SO through S4
S5
During machine cycles that do not use the bus, the riA and
active in these cycles.
DCHREO, Pin 29 - Data Channel Request - Active LOW
input; initiates data-channel cycles while LOW after current
instruction. Must occur before TDRH (c).
Vii, Pin 1 - Write Output -Indicates direction of data flow;
HIGH indicates a read or input operation; LOW indicates a
CONREQ, Pin 28 - Console Request - Active LOW input;
initiates a console operation after current instruction.
o lines will be "111". BUSREQ and the bus strobes are in-
6·19
~
~
F9445
Fig. 2 F9445 Register Model
INTREQ, Pin 30 - Interrupt Request - Active LOW input;
initiates entry to interrupt procedure, if interrupts are enabled, after the current instruction.
15
PROGRAM COUNTER (PC)
ABORT, Pin 32 - Abort - Active LOW input; initiates abort
sequence in the current microcycle.
PROGRAM STATUS WORD (PSW)
ACCUMULATOR 0 (ACO)
Power
Vee, Pin 31 -
Power Supply -
GND, Pin 9 -
Ground.
ACCUMULATOR 1 (AC1)
Requires +5 V.
ACCUMULATOR 2 (AC2)
ACCUMULATOR 3 (AC3)
STACK POINTER (SP)
ilNJ, Pin 10 - Injection Current Input - Operates in
200-400 mA range at approximately 1 V; requires> 350 mA
for maximum speed.
FRAME POINTER (FP)
Register Set
liNTON
The F9445 has eight user-accessible registers (see Figure 2),
including seven 16-bit registers and a program status word
(PSW) containing the following four flags: carry (bit 0), 32KW
(bit 1), trap enable (bit 2), and overflow (bit 15). The carry
flag (C) indicates the state of the carry bit during arithmetic
and logiC operations. The 32KW flag indicates whether the
processor is operating in the 32K-word ("1 ") or 64K-word
("0") mode. The trap enable/disable flag (ETRP) indicates
whether the trap instruction is enabled ("1 ") or disabled ("0").
The overflow flag (V) indicates twos-complement overflow in
arithmetic operations.
I
INTERRUPT MON FLAG
Fig. 3 Data Organization in a Stack (LIFO)
INCREASING MEMORY ADDRESSES
INCREASING MEMORY ADDRnSES
In addition, there is an interrupt-on (INTON) flag. The CPU
responds to interrupt requests from external I/O devices
when the flag is set ("1 "). When it is clear ("0"), all interrupt requests are ignored by the CPU. The state of the flag
can be altered by the Interrupt-Enable or Interrupt-Disable
instruction.
The seven 16-bit registers comprise a program counter
(PC) that sequences the execution of instructions, four
general-purpose accumulators (ACO through AC3), the
stack pointer (SP) and the frame pointer (FP). The, program
counter sequences the ,execution of instructions. It holds
the address of the next instruction to be executed and is
automatically incremented to fetch instructions from consecutive memory locations. A Skip, Jump, Jump-toSubroutine, or Trap instruction, an interrupt generated by
an I/O device or an Abort can alter the sequential execution
of instructions.
SP
-
FP
--f--cl
'---
C
r--
t--
I
FP-
AC3
-
OLDFP
TOP OF STACK
..
AC3
OLDFP
AC2
AC2
ACI
ACI
ACO
ACO
'---
AC3
OLDFP
AC2
ACO
I
I
32K WORD MODE
6-20
SP_
TOP OF STACK
ACI
The four accumulators serve as source and destination registers for 16-bit arguments in arithmetic-and-Iogic instructions which process the contents of the source accumulators and a base value for the carry flag and store the
16-bit result in the destination accumulator. The associated
carry and overflow flags are set or cleared depending on
t
t
PREVIOUS
RETURN
BLOCK
I
AC3
,..-- f--
OLD'FP
AC2
ACI
ACO
I
I
64KWORDMODE
F9445
the result of the ALU operation as the base value of carry.
Accumulators AC2 and AC3 also serve as index registers
during memory addressing operations. In addition, AC3
functions as a subroutine linkage register, and the pair ACO
and AC1 are used as a 32-bit register in the multiply/divide
and the normalize and parametric double-shift instructions.
The other two 16-bit registers serve as temporary storage
and as the stack pOinter (SP) and frame pointer (FP) in the
stack manipulation instructions. The stack pointer contains
the address of the top of the stack, i.e. the last word
"pushed" onto the stack which is also the first word that
may be "popped." The frame pointer contains the address
of the highest location in a block of five words on the
stack, a "frame," containing program status information
used to return from a subroutine (see Figure 3).
The frame pointer is updated by the Save and Return instructions which are intended to be the first and last instructions, respectively, executed by a subroutine. When a
Jump-to-Subroutine instruction is executed, the value
PC+ 1 (and the value of the carry bit in 32K-word mode
only) is stored in AC3. The Save instruction then pushes
five key words onto the stack in the following order: first,
the contents of ACO; second, the contents of AC1; third,
the contents of AC2; fourth, the value of FP before the
Save; and fifth, the contents of AC3. At this point, SP
points to the top of the frame (which is the current top of
the stack), and that address becomes the new value of FP.
This new value of FP is also placed in AC3. When a Return
instruction is executed, the five words stored in the frame
referenced by FP are used to restore accumulators ACO
through AC2 to their values at the time preceding the Save.
FPis restored to its previous value (pointing to the last
previously saved five-word frame) and PC is loaded with
the return address which had been placed in AC3 by the
previous Jump-to-Subroutine and pushed onto the stack by
the previous Save. The restored value of FP is also placed
in AC3 by the Return instruction.
Information may also be moved between SP or FP and any
of the four accumulators by the instructions MTFP, MFFP,
MTSP, and MFSP without affecting the source register of
the move or any of the registers not specified with the instruction. This allows setting up multiple stacks whose
pointers are saved in main memory when not in use.
Addressing Ranges and Modes
The F9445 memory reference instructions support two address ranges and a variety of addressing modes. These
modes include direct/indirect addressing which may be absolute, PC-relative, or indexed by AC2 or AC3. Additional
addressing modes include auto-increment, autodecrement, and address via stack and frame pOinters. The
6·21
two address ranges in which the F9445 can operate are
128K-byte (64K-word) or 64K-byte (32K-word) logical address space. The F9445 master resets to the 64K-byte
(32K-word) address range. The 128K-byte (64K word)
address range can be enabled or disabled under program
control.
64K-Byte (32K-Word) Address Range
After the master reset is activated or the 064K instruction is
executed, the F9445 operates in the 64K-byte (32K-word)
address range. In this mode of operation, it uses 15-bit addresses to fetch up to 32K words from the memory and
uses either the least-significant sixteenth bit to select high
or low byte of the word in the byte instructions or the
most-significant sixteenth bit to specify the remaining 15
bits of the word as an indirect address in multi-level indirect addreSSing instructions.
In the Load-Byte (LOB) and Store-Byte (STB) instructions, a
16-bit accumulator is specified as the byte pOinter. The
most significant 15 bits of the byte pointer are treated as
the logical address of the word containing the byte which
the least significant bit specifies, selecting the high (if "0")
or low (if "1") byte of the word.
The remaining memory reference instructions specify effective addresses of 16-bit words via various (11) addressing modes described below.
Page Zero
In this mode the instruction provides
an 8-bit absolute address to access
the first 256 words (page zero) of
memory.
PC Relative
In this mode the instruction provides
an 8-bit twos-complement signed
number which is added to the program counter to access 128 locations below and 127 locations above
the address specified in the program
counter.
Indexed by AC2
(or AC3)
In these two modes the instruction
provides an 8-bit twos-complement
signed number which is added to
AC2 (or AC3) to access 128 locations
below and 127 locations above the
address specified in the accumulator.
The memory reference instruction may specify any of the
above four memory addressing modes to be either direct or
indirect. For direct addressing, the effective address computed using the eight addre.ss bits of the instruction is the
final address of the target word to be stored or retrieved.
F9445
For indirect addressing, the effective address computed
from the eight address bits of the instruction is used to
fetch a 16-bit word that supplies the address of the target
word. If the most significant bit of this word is "0", the 15
least significant bits provide the address of the target word.
However, if the most significant bit of this word is" 1", this
specifies a further level of indirect address. In that case,
the 15 least significant bits refer to the address of another
word which could provide the final address of the target,
depending on whether its most significant bit is "0" or "1".
Thus, multiple levels of indirect addressing continue until a
word is fetched with a most significant bit of "0". Such
multiple levels of indirect addressing are only allowed in
the 32K-word address range operations.
provide the displacements for the calculation of effective
addresses of memory locations.
The whole instruction set can be divided into five broad
groups:
Memory Reference Instructions
Arithmetic-and-Logic Instructions
Stack Manipulation Instructions
I/O Instructions
Control Instructions
The Memory Reference instructions modify the contents of
memory locations, alter program execution sequence, and
move operands between the accumulators and memory locations. The contents of accumu lators and the carry and
overflow flags are processed by the Arithmetic-and-Logic
instructions. The Stack instructions manipulate the registers and the memory in stack-associated operations. The
I/O instructions effect data transfers between the accumulators and I/O devices. The Control instructions modify
or interrogate the state of the CPU and operator console,
performing such actions as controlling the status of the
interrupt-on flag and reading the status of the console
switch register.
The next two types of addressing modes are the autoincrement and auto-decrement modes. When locations 20
through 27 (octal) are indirectly addressed, the autoincrement mode is activated: the contents of the specified
location are first incremented and stored back and this
new value is treated as the effective address (which can, in
turn, be either direct or indirect). Locations 30 through 37
(octal) are used as auto-decrement locations in a similar
manner.
The last type of addressing is stack addressing in which
the address of the memory reference is derived from the
stack pointer.
128K-Byte (64K-Word) Addressing Range
After the E64K instruction is executed, the F9445 starts
operating with the 128K-byte (64K-word) addressing range.
In this range, the F9445 uses 16-bit addresses to fetch up
to 64K words from the memory and supports all the 11 addressing modes described previously. However, only one
level of indirect addressing is allowed - the one specified
in the instruction - since with 16-bit addresses there are
no bits available in the words fetched to indicate further
indirect addressing.
The byte pointer is also different in the 128K-byte
(64K-word) case compared to the 64K-byte (32K-word)
case. The 64K-word range byte pOinter is 17 bits wide and
is composed of the carry flag and the 16-bit accumulator
specified in the LDB or STB instruction. The value of the
least-significant bit of the 17-bit word selects the high (if
"0") or low (if" 1") byte of the word to be loaded or stored.
Instruction Set
The F9445 has fixed-length instructions, each of which is
16 bits long and divided into several fields. The fields are
used to specify the operation code and other related actions, to define conditions and specify the CPU registers
containing arguments, to define I/O device codes, and to
6-22
F9445
Input/Output Operations
The F9445 can transfer the contents of any accumulator to
an I/O device by executing a Data-Out instruction. It can
load data from an I/O device into any accumulator by
executing a Data-In instruction. To test the status of an I/O
device, the F9445 can execute a Skip-an-Status instruction.The I/O cycle has the same timing as the memory cycle
(see Figures 13 and 14). Features of the I/O cycle are:
Input/output devices can transfer data to the F9445-based
microcomputer via:
Programmed I/O using the I/O instructions of the F9445,
Memory-mapped I/O using the load/store instructions of
the F9445, 0 r
• 250 ns (at 24 MHz system clock) minimum cycle time
• Cycle time can be extended using RDYA, RDYD
• I/O instruction is output at address time
• STRBA is used to latch the I/O instruction
• STRBD is used to strobe the data
• a lines indicate the type of cycle as follows:
Direct memory access or data-channel transfers.
For programmed I/O, the device consists of up to three
(minimum one) bidirectional 16-bit device registers, denoted as A, B, and C, and three 1-bit flags: Busy, Done and
Interrupt Disable (see Figure 4). The 2-bit status word comprised of Busy and Done represents one of up to four possible states of the device, viz. idle, busy, partially done and
completely done (refer to Device Status Flags subsection).
The F9445 I/O instructions allow data transfers between
any of the accumulators (ACO through AC3) and any of the
device registers (A through C), and can test and set the
Busy, Done and Interrupt-Disable flags.
M 0, 0 0 Iii
I/O Input Execute
Instruction Fetch
I/O Output Execute
Interrupt Save
•
DONE
INPUT
OUTPUT
DEVICE REGISTER A
DEVICE REGISTER A
DEVICE REGISTER B
DEVICE REGISTER B
DEVICE REGISTER C
DEVICE REGISTER C
Fig. 5 Input/Output Instruction Fields
1()
Op Code
AC
Address
Type of
Transfer
Control
11
0
0
1
0
1
0
0
0
0
0
1
0
0
The I/O devices can interrupt the normal flow of the
program by using the common interrupt request line
Instruction Decode
An I/O instruction in the F9445 system comprises several
fields as shown in Figure 5. This format accommodates
data transfers between a CPU accumulator and anyone of
up to three bidirectional registers in anyone of 621/0 devices. Bits 10 through 15 are coded to represent device
codes 00 through 76 (octal). The all "1s" device code, 77
octal, is reserved for CPU control instructions and should
not be assigned to any unique I/O device; for similar reasons, device code 1 is also reserved; by convention, device
code 0 is not used.
Fig. 4 I/O Device Model
BUSY
1
12
13
14
Device Code
6·23
15
F9445
Bits 3 and 4 specify the address of any accumulator involved in an I/O instruction. When no accumulator is involved; both bits are ignored. The function bits 5,6, and 7
define the I/O operation to be performed. Bits 8 and 9 control or test the status of the device busy and done flags.
Device Status Flags
Interrupts from a device are disabled when the interruptdisable flag of the device is set to ".1". Interrupts are
enabled when the flag is clear. Interrupt requests are generated whenever the device sets the done flag.
The eight standard I/O instructions were listed
previously in the instruction set description of the
introduction to this section. The No-Input/Output (NIO)
instruction is a "no data transfer" instruction that can
be used to set the busy and done flags as required, by
attaching the appropriate flag-setting mnemonic. The
F9445 executes a "dummy" data out transfer. The status
of a device's busy and done flags Is tested by executing
a Skip (SKP) instruction that causes a specific I/O device
to put its busy and done flag states on lines IBo and IB1
of the common information bus. If the flag state
satisfies the condition specified by the busy/done flagtesting mnemonic appended to SKP, the CPU skips the
next instruction. The remaining six standard I/O
instructions first move data between an accumulator and
anyone of the device registers A, B, or C. After the
transfer is completed, the busy/done flags are set as
specified in the I/O instruction.
During programmed I/O, the interrupt-disable flag is normally set to disable interrupts, and the busy and done flags
define the status of the device for the CPU. The busy and
done flag states are coded to represent the ind icated device conditions, as follows.
There are three I/O instructions that are common to all I/O
devices: Interrupt-Acknowledge, Mask-Out, and Clear-I/ODevices. Tile device code for these three instructions is
77 (octal).
When the F9445 executes the I/O instruction, the M and d
lines will indicate an I/O operation ("100"). The 0 lines are
valid on the rising edge of SYN. The device address
(bits 10-15) must be decoded by each device on the I/O
bus. Transfers of in'formation to and from.the F9445 are
timed with STRBD in the same way as the memory cycle.
At the address time, the F9445 outputs the I/O instruction
on the information bus. This can be used to generate I/O
signals on systems without an I/O controller. STRBA is
generated and can be used to latch the I/O instruction externally. The interrupt-disable, busy and done flags organize interrupt-driven program-controlled I/O operations.
The CPU controls the interrupt-disable flag. Both the CPU
and the device can control the busy and done flags.
Busy
Done
Device State
0
1
0
0
0
1
Device idle
Device busy
Device completely done
Device partially done
The sequence Of I/O transactions is normally dictated by
the speed at which the device can communicate with the
CPU. If the CPU operates at a higher speed than a device, it
enters a wait loop between each I/O transaction with the
device. During execution of the loop, the CPU repeatedly
monitors the busy or done flag to determine when the device is ready for the next I/O operation.
During an output operation, one instruction stores data in
the desired device register and places the device in the
busy state. The CPU then enters a wait loop which terminates when the device has cleared busy and set done to
signal readiness for the next output operation.
To initiate an input transaction, the device sets the done
flag. One instruction reads data from the appropriate device register and places the device in the busy state. The
CPU then enters a wait loop which terminates when the
device has cleared busy and set done to indicate that it has
the next data ready.
6·24
F9445
(INTON), but the flag has no effect until the next instruction
begins. Thus, after the instruction that turns the interrupt
back on, the processor always executes one more instruction (assumed to be the return to the interrupted program)
before another interrupt service can start. If the service
routine allows interrupts by higher priority devices, the
routine should turn off the interrupt, before dismissing as
indicated above, to prevent further interrupts during dismissal. In dismissing, the routine should re-enable lower
priority devices.
Interrupts
The interrupt request, INTREQ, line is common to all 1/0
devices. When the device completes an 1/0 operation, it
should set the done flag. Concurrently, if the device is
enabled to interrupt, it should assert the active LOW on
the INTREQ line. The processor responds to the interrupt
request after completing execution of the current
instruction. It then clears the interrupt-on flag so no
further interrupts can be started, saves PC (which points
to the next instruction) in location 0, and executes a
"jump-indirect-to-location-1" instruction to jump to the
interrupt service routine. Location 1 should contain the
address of the interrupt routine or an indirect address to
the routine. The F9445, when interrupted, can check for
the source of the interrupt in two ways:
The interrupt request input INTREQ is negative-level
sensitive and is synchronized in the processor. Externally,
interrupt requests may be latched with the leading edge of
SYN. The interrupt request may be reset by the external I/O
controller from a decode of the I/O instruction INTA.
It can test the state of the done flags in the various devices, one by one, by executing Skip-on-Done instructions; or
The F9445 recognizes two other types of interrupts:
Abort Interrupt - This is activated by the active LOW of the
ABORT input. The processor responds by:
It can test the state of the I/O devices by executing the
Interrupt-Acknowledge instruction, causing the device
that had sent an interrupt request to respond by placing
its device code on bits 10 through 15 of the information
bus.
Aborting the instruction being executed,
Storing the address of the aborted instruction in location 46 (octal), and
Jumping indirect to location 47 (octal).
As several devices can request interrupt simultaneously,
device priority may be established in a daisy-chain fashion
by a physical connection of a serially propagated signal,
Interrupt Priority. The first device requesting an interrupt
and having its Interrupt-Priority-In line HIGH has priority,
and it answers the Interrupt-Acknowledge instruction, at
the same time blocking the propagation of the interruptpriority signal by putting its Interrupt-Priority-Out line in a
LOW state.
Stack Overflow interrupt-This is an internal interrupt
caused when the stack overflows; i.e., when a stack
operation (PSHA, PSHF, PSHR, SAVE, TOPW) writes over
a page boundary (mod 256). This interrupt is of higher
priority than the external interrupt (I NTREQ); the
processor responds, at completion of the current
instruction by:
Clearing the interrupt-on flag (to "0"),
Storing the updated program counter in location 0, and
Jumping indirect to location 3 (octal).
The interrupt-priority signal is generated in the device having the highest priority. The F9445 can disable the interrupt
system in each I/O device by placing a mask on the information bus while executing the Mask-Out instruction.
The interrupt-save cycle follows the interrupt. It can be externally detected by the code "011" on the 0 lines and
used, for example, to switch an external mapper to nonmapped mode.
Each bit in the mask is assigned to a specific device. When
that bit is "1", the interrupt system is disabled. A "0" in
that bit enables the device.
The order of priority of requests and interrupts, from highest to lowest, is as follows: MR, Ai35RT, DCHREQ, Stack
Overflow Interrupt, INTREQ, and CONREQ.
After servicing a device, the routine should restore the preinterrupt states of the accumulators and carry, turn on the
interrupt, and jump to the interrupted program. The
instruction that enables the interrupt sets interrupt on
6-25
F9445
3. The processor sets the
code in).
Data Channel
The data channel has three methods of operation with the
F9445:
M and 0
lines to "110" (console
4. In response to the M and 0 lines being set to "110", the
console logic supplies a code on the information bus
corresponding to the desired operation, which is
selected onto the bus with STRBD.
Data-channel cycle with F9445 controlling the memory,
Data-channel cycle with external memory control, and
Autonomous-bus cycle using bus arbitration scheme.
5. The console logic resets CONREQ.
The sequence of events during a data-channel cycle is as
follows:
6. The processor executes the console operation.
1. DCHREQ is set.
7. The processor may read or write data from the console
switches or console lamps. In this case, the M and 0
lines are set to "111" (console data). In most cases, the
processor halts after the console operation by entering
a Wait state. The exceptions are Continue and APL.
2. F9445 responds by setting M, 0" and O. to "101" and
BUSREQ to "1". This is recognized externally as DataChannel Acknowledge and can be used to reset
DCHREQ if it is the last data-channel cycle required.
Console logic can be implemented in three levels of
simplicity:
3. F9445 3-states the bus and sends STRBA.
4. The external logic must supply an address at this time.
The address time can be extended with RDYA.
No Console Code - If a CONREQ is generated and no
console code supplied, the default bus value ("0") will
cause the processor to execute APL. This sets the PC to
-1, then starts normal execution. This is the minimal console operation requ ired.
5. F9445 outputs STRBD.
6. The controller transmits or receives the data-channel
data and responds with RDYD, concluding the cycle.
Limited Console Operation - A subset of operations can
be arranged with a 2-bit console code. These operations
are APL, Test, Continue, and Halt.
Console Operation
Console operation allows examination and modification of
the F9445 internal registers without executing programs in
main memory. This is very useful for system diagnostics
even when the memory or I/O part of the microcomputer
system is not fully functional.
Full Console Operation - A 9-bit code (see Figure 6) defines the full set of console operations. Single-Step is not
implemented directly, but can be arranged using Continue:
first, the Continue operation is specified; after the first instruction is fetched, a new CONREQ is generated and the
operation is changed to Halt.
Upon request for console operation, the processor will
execute one of a number of console operations depending
on a console code on the information bus (see Figure 6).
This facilitates the connection of an external console for
monitoring and test purposes. The following sequence is
used to execute a console operation:
1. CONREQ is set LOW.
2. The processor finishes the current instruction.
6-26
F9445
Fig. 6 Console Codes
o
o
I
2
I
:0 :
3
4
5
O§:]
I
I
12 3 4 ,
,
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
7
6
I
I
I
15
ACO
ACI
AC2
AC3
SP
FP
o
o
6
0
1
o
1
8
9
Dffi:J
QD
I
I
I
I
I
I
PROGRAM LOAD
EXAMINE/DEPOSITITEST
CONTINUE
STOP
is carrying address or data, respectively. The M signal
(M = LOW) indicates that a memory cycle is taking place
on the bus, while the W signal indicates whether the operation is a read or write. The timing of the STRBO is shorter
for a write operation, to allow positive hold time for the
memories. The signal ROVO may be held LOW to stretch
..
the memory cycles for slow memories.
~
Bus Arbitration
The F9445 contains three signals that allow more than one
processor to share a common bus:
BUSREQ-This is LOW at the beginning of every cycle In
which the F9445 requires use of the bus.
BUSGNT-When LOW, it is used to halt the processor indicating the bus is unavailable.
A typical scheme is shown in Figure 7. This diagram shows a
4K x 16 static RAM configuration (2114-type 1K x 4). The
bus is buffered by a 74240 inverting 3-state buffer. Buffering
is optional and depends on fan-out requirements of the
memories. The buffer is normally connected for output, but
is connected for input when necessary by a simple decode
of the M, Wand STRBD lines.
BUSLOCK-This indicates that the current bus cycle and
the following bus cycle from the processor must not be interrupted by a cycle from another processor.
The BUSLOCK signal has two purposes. One purpose is to
prevent the external memory address register from being
overwritten during those instructions that rely on the address remaining in this register. The other purpose is to
provide a method of synchronizing separate software tasks
uSing a standard semaphore system. An external arbiter is
required to determine which processor has access to
the bus.
An address latch (74533) is cloCked with STRBA. The
memory address is decoded from these outputs and forms
the chip-select (CS) inputs to the RAM.
A shift register (74164) provides a time delay for ROVO for
slow memories. An alternative for this would be a one-shot
(9602). Fast memories do not require ROVD delayed.
Applications
Static Memory Interface
The F9445 bus structure allows easy connection of static
memory. Both address and data are multiplexed onto the
16-bit information bus iB'D-,sl' The mutually exclusive signals STRBA and STRBO indicate that the information bus
6-27
Fig. 7 Stalic Memory Connection Scheme
MAR15
18
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BUFFER/DRIVER
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R: CONNECT FOA £1 A RS232 INTERFACE
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4
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oeuux
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FLAG LOGIC
8,
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74lS08
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F9445
Fig. 8 F9445 Input/Output Connection Scheme (2 of 2)
iii
101
74LS240
r---=--"""
-
10,
2,3
iB9
4,5
ii 10
6,7
I
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1BI9
14,13
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»--I>~~ INTRa (9445)
BUFFER/DRIVER
IB"
8,'
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111~
STRB~
4,5
so,
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74LS74
11
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15
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6·31
IT
BUFFERI
DRIVER
F9445
Fig. 9 F9445 Dynamic Memory Connection Scheme
Dynamic Memory Timing
+ 5 V - -_ _.......
CLOCK
------1
ADDRESS DECODER
STAID
IB
D~~2~~R/O
M
MEMORY
74508
74LS138
im'
lIASo
0,
lIAS,
ADDRESS
SYN
REGISTER
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0
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00
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748533
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MUX REF
CP AE AS
~::::::+:;~i13
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CAS
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ADDRESS MUX
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STRBA
+5V
'5V
o
1
0
0
1
0
REF
MEMORY ARRAY
14K. 1.
MEMORY ARRAY
'5V
748164
SHI" REGISTER
CLOCK
REF
4 BANKS
DATA
BUS
,.
1:7.~~=::;t.-:!:::!:1 DIN' DOUT
CP
M
STA8D
Notes
I.
2.
3.
4.
6·32
D'N connected to DOUT connected to Data Bus. _ _
All FI6K devices have the same address lines and CAS. WE line.
Each bank of 16 FI6K has a separate RAS line (4 banks).
Each slice of 4 FI6K is connected to a separate data bus line (16slices).
F9445
The memory requires "refreshing" every 2 ms. The 9642
contains a 7-bit refresh counter. Every 15.63 ms (2/128), the
memory controller enters "refresh" mode. This is synchronized with SYN to avoid any conflict. Another 74164
shift register controls the refresh timing which requires
only an RAS strobe. After the refresh cycle, the refresh
counter is incremented and the normal memory timing is
resumed.
The Console Request is set whenever any operation switch
is pressed and is reset when the console code is read from
the FPLA. The circuit provides for control of two processors sharing the same bus.
All the switches are momentary-action type except the data
switches and the select-processor switch.
A full listing of the FPLA is shown in Table 2.
The refresh cycle takes place when needed and may take
place during non-memory processor cycles. In these cases,
the processor is not halted, and the refresh cycle is overlapped.
The console provides all F9445 console functions, including Self-Test, plus the additional function of Single-Step,
and is compact enough to be implemented with all
switches, lamps, logic and connectors on a double-sided
17V2-by-5V2-inch printed-circuit board.
Different memory types have different speed requirements.
These requirements can be met by changing the "taps" on
the 74164 shift registers.
Console Control
On an application board, a minimal console is usually required. The APL (automatic program load) function can be
easily implemented by pulsing the Console Request line
LOW. There are no critical timing requirements since this
signal is latched internally. The F9445 will continue to execute APL commands until the Console Request is raised.
Since the bus must be HIGH for the APL to execute correctly, bits 5 and 6 of the bus may be tied to + 5 V through
3 kD resistors as pullups.
For debugging and evaluation purposes, a console is a
very useful tool. It gives complete control of the processor
independent of software and memory operation.
Since the console commands are microprogrammed into
the F9445, a full console design is fairly simple, the
simplest full console uses the F9470 console-controller circuit, which drives an RS232 terminal and contains two serial I/O ports and a timer. The F9447 I/O controller can also
be used to provide some console functions.
Interfacing to standard switches and lamps requires switch
debouncing and encoding operations. The circuit shown in
Figure 10 uses R-S latches for switch debouncing and an
FPLA (93409) for switch encoding.
Table 2
Console PLA Listing
*P
*P
*P
*P
*P
*P
*P
*P
*P
*P
*P
*P
*P
*P
*P
*P
*P
*P
*P
-H-HHHHHHHHHL---H-HHHHHHHHL----H-HHHHHHHL-----H-HHHHHHL---H--H-HHHHHHL---L--H-HHHHHL-------H-HHHHL-----H-HL-H---L-----H-HL-H---L-----L-HL-H-----L---L-HL-H-----L---H--H-HHHHL-----L--H-HHHL---------H-HHL----------H-HL-------------L-----------HL-H-----------LL-H-----H------H-HHHHHHHHHH---
00
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
18
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
Key for Table 2:
*A
Active level of outputs
*P
Product term number
*1
Inputs
*F
Outputs
Don't care
H
High level
L
Low level
A
Active
An address latch is strobed on every STRBA, and a data
latch is strobed on every STRBD except "console code
read." This results in the correct display on the lamps. The
data switches are enabled with "console data read."
A Single-Step function is included. This function requires
two additional latches, plus some decode logic, and implements a Continue followed by a Halt.
6-33
*A
*F
*F
*F
*F
*F
*F
*F
*F
*F
*F
*F
*F
*F
*F
*F
*F
*F
*F
*F
LLLLLLLL
-----A---A--A---AA-A-----AA-----AA-A
--A-AA----AAA----AAA----AAA-A
----AA-A
----AA----AAA-A
--AAAA---------
------A-,----AA------A-----AA-----AA-
•
Fig. 10 F9445 Console Connection Scheme (1 of 3)
1
1
'5.
3'
ci
1
i
1
i
1
£
1
i
•
A
I
"
51.52
'5.
'.3
a
~
•
.,A
5
10
10
DEPACO
5
•
7
11
9
,.
I,
lS279
QUAD
LATCH
DEPAC1
10
I
Ao
I,
•
11,12
DEPAC.
,.
I
15
13
"
9318
ENCODEA
DEPAC,
1
"
5,,52
',3
7
A, C > - - -
"
a
•
I,
A, .:.-
DEPSP
SAME AS PLA PIN 1
5
I
7
•
I
!15
S
aE
1
-10.
8
I,
'--
11,12
lOb
1.
I
13
"
I"
I
"
5,,52
',3
I
•
a
*
•
1.5
I"
10
10
1
1
1
1
i
i
i
i
I
11
9
,.
1.
13
r--
I"
I,
LS279
QUAD
10
1
7
LATCH
IEXAC1
t
Zb
!-
~c
2!...
LS257
MULTIPLEXER
DEPDC
5
I
.!.-
ope
15
tEXACO
1
Za
DEPFLAGS
1
1
1.
b
XI
LATCH
10
i
i
GS
LS279
QUAD
IDEPFD
I
I,
r - - I"
9
Ao D0-
I,
11,12
EXAC,
1.
I
"
15
A'~
9318
ENCODER
EXAC.
1
I
"
5,.51
',3
a
•
1
7
•
9
3
A,
I,
GS 1>-X8
EX SO
5
•
I,
,.
LS279
QUAD
EXFD
I
EX FLAGS
10
LATCH
I,
11,12
,.
13
EXPC
15
EX-;C
SWITCH
DEBOUNCE
DPC
..
"
l -r--
SWITCH
DECODE
7'~05
.....
XPC
PIN 7 OF PLA
Fig. 10 F9445 Console Connection Scheme (2 of 3)
+5v------~-+~------~----------~----------~------~------------------------1
1k
7405
1k
10 k
10 k
10 k
RESET
0, 18
iio
02 17
ii5
lOGIC
DUAL-PROCESSOR
LOGIC
10 k
STRBA~ STRBA
~
Sfi!iiO~ STRBO
22
(RUN) A--+-~."
J
L ______-::c==::::2::n::d~FE~T;.::C::.H:.....-----2"i0 A1S
SWITCH OEBOUNCE
CONSOLE CODE PLA
6-35
F9445
Fig. 10 F9445 Console Connection Scheme (3 oj 3)
DATA LAMPS
+5 •
'\
iBo
Do
D,
ADDRESS LAMPS
-5'
'\
+5'
27.
iBo
00
LOo
1elS373
ii,
27.
'\
0,
ii,
D,
iiz
D2
OCTAL
LATCH
(RUN)B
ii2
D2
02
(ION)B
ii3
D,
0,
(RUN)"
11. "
D.
O.
Ds
Os
D,
0,
'\
(CARRY) B
..
(CARRY)A
I
I.
ii~
I'
iii,
17
ii3
12
15
(ION)"
I
t"
16
.
•
ii,
I.
iis
I'
iis
17
D,
D.
'\
Ds
'\
D,
'\
18,
iir
II D,
LE
11
00
"::"
0,-=....-......
ii
Vi
11
iBs
00
0,
ii
Vi
•
LE
Do
"::"
STRBA
+5 •
270
00
27.
iis
7CLS373
-~r"")>--t:~.J
II,
D,
0,
OCTAL
iii.
LATCH
11"
D2
li'0
01~Ol
ii"
D,
ii11
OO~Oo
ii,2
74LS04
I.
I.
D,
O.
ii12
Ds
Os
ii,)
1.
D,
0,
ii14
17
D,
0,
ii,s
74LSD4
ii'3
iiu
ii,5
DATA SWITCHES
6-36
1.
17
II
+5'
F9445
completely shared resources, does not give as high performance as the Local and Common Memory scheme.
However, for certain applications and for two processors
only, this scheme can give a considerable performance increase over a Single-processor system with very little
hardware overhead. This scheme is described in the following paragraphs.
A Multiprocessor Scheme
There are many ways to envision two or more processors
working concurrently. The method of interconnecting the
processors depends on the application and the performance objectives. Listed here are a few of the options.
Independent Operation
For those processors which can be made to run independent tasks, this provides the most efficient scheme. Each
processor has independent memory and resources.
A general scheme for two tightly coupled F9445
processors is shown in Figure 11. The processors share
a common bus and an arbiter selects which processor
uses the bus and multiplexes the control lines
accordingly. The 1/0 arbitration scheme is very simple:
each processor assigns the bus to the other processor
when it commences any cycle that does not use the bus,
as long as BUS LOCK is not set.
Shared I/O
Each processor has its own memory but shares an I/O bus.
This allows high-speed operation while minimizing system
resource requirements.
Local and Common Memory
This gives a good compromise between performance and
resource requirements. Each processor normally runs from
its own memory at high speed. Accesses to a common
memory are rarer and, because of the arbitration problems,
slower.
The scheme is most efficient when the instruction mix includes many "long" instructions, such as Multiply, Divide,
Parametric Shift and Normalize. Since only one processor
is using the bus at any time, the synchronization signals
RDYA and RDYD can be the same for both processors.
However, the interrupt request (INTREQ) and data-channel
request (DCHREQ) lines should be separate to avoid any
conflicts in I/O handling.
Tightly Coupled
Two or more processors share the same memory and I/O.
This scheme is easiest to implement but, because of the
Fig. 11 A Possible General Multiprocessor Scheme
ROYO
---11---+---1
RDYA -----<1------1
INFORMATION BUS
CONTROL BUS [MOO. 0"
SYN
mmA
!!TIfIm
6-37
'Ii]
II
•
F9445
F9445 Instruction Execution Times
Execution Times
Instruction
Clock
Cycles
16 MHz
20 MHz
24 MHz
COM
NEG
MOV
INC
ADC
SUB
ADD
AND
OR
MUL
MULS
DIV (Normal I
DIV (Overflow')
DIVS (Normal) .
DIVS (Overfiowl
NORM
6
6
6
6
6
6
6
6
6
70
70
86
14
114
26
10 + 4n
0.375
0.375
0.375
0.375
0.375
0.375
0.375
0.375
0.375
4.375
4.375
5.375
0.875
7.125
1.625
0.625 + 0.25n
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
3.5
3.5
4.3
0.7
5.7
1.3
0.5 + 0.2n
0.25
0.25
0.25
0.25
0.25
0.25
0.25
0.2.5
0.25
2.9
2.9
3.6
0.58
4.7
1.1
0.42 + 0.17n
SLLD
SALD
SARD
SLRD
SKNV
.JMP
JSR
ISZ
DSZ
LOA
STA
LOB
STB
PSHA
POPA
PSHF
POPF
POPJ
PSHR
TOPR
TOPW
MTSP
MTFP
MFSP
MFFP
SAV
RET
DSP
NIO
SKP
DIA/B/C
DOA/B/C
ETRP
DTRP
E64K
D64K
10 +4n
10 + 4n
10 + 4n
10+4n
14
6
6
22
22
12
12
24
26
16
16
16
16
16
16
16
16
6
6
6
6
60
80
6
12
16
12
12
10
10
10
10
0.625 +
0.625 +
0.625 +
0.625 +
0.875
0.375
0.375
1.375
1.375
0.75
0.75
1.5
1.625
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
0.375
0.375
0.375
0.375
3.75
5.0
0.375
0.625
1.0
1.0
1.0
0.625
0.625
0.625
0.625
0.5 +
0.5 +
0.5 +
0.5 +
0.7
0.3
0.3
1.1
1.1
0.6
0.6
1.2
1.3
0.8
0.8
0.8
0.8
0.8
0.8
0.8
0.8
0.3
0.3
0.3
0.3
3.0
4.0
0.3
0.6
0.8
0.6
0.6
0.5
0.5
0.5
0.5
0.42 +
0.42 +
0.42 +
0.42 +
0.58
0.25
0.25
0.92
0.92
0.5
0.5
1.0
1.1
0.67
0.67
0.67
0.67
0.67
0.67
0.67
0.67
0.25
0.25
0.25
0.25
2.5
3.3
0.25
0.5
0.67
0.5
0.5
0.42
0.42
0.42
0.42
0.25n
0.25n
0.25n
0.25n
0.2n
0.2n
0.2n
0.2n
0.17n
0.17n
0.17n
0.17n
Notes
Times for no-skip or unfulfilled .skip;
for fulfilled skip; add 0.3 {O.25 at
24 MHzl
n - number of steps needed for
normalization. Time is 0.7 {O.591 if n=O.
n - number of shifts;
time is 0.710.591 if n=O.
Times for page-zero addressing; add
0.310.251 for indirect; add 0.3 10.251.
for auto-increment/decrement; add
0.210.181 for indexed.
Note: Execution times are given for 20 MHz and 24 MHz clock. The clock may be operated from> 0 to 24 MHz within the specified temperature and voltage range.
6-38
F9445
Fig. 12 ALU Cycle Timing"
SYMBOL AND
(PIN It)
so
51
SlA
55
so
51
elK (40)
SYN (7)
00 (34), 0, (35)
M (36)
W(1)
RUN (37)
--1----+----+-""1
TA(C)
ABORT (32)
Fig. 13 Minimum Memory Cycle Timing"
SYMBOL AND
(PIN II)
eLK (40)
00
(34),
0, (35)
M(36),W(l),
BUSREQ (38)
SYN (7)
STRBA (5)
'iB (11-3) READ
Ii (11-26) WRITE
STRBD (6)
'See Timing Parameter Symbol Conventions at end of data sheet.
6·39
SlA
F9445
Fig. 14 Extended Memory Cycle Timing·
WAIT
SYMBOL AND
(PIN #)
FOR
ROYA
I
ROYA
RECOGNIZED
GENER-
..AIL
STRBO
I
WAIT
FOR
ROYO
ROYO
RECOGNIZED
I
CLK (40)
SYN (7)
STRBA(S)
ROYA(4)
iii (11-26) READ
iii (11-26) WRITE
STRBO(6)
ROYO (8)
"See Timing Parameter Symbol Conventions at end of data sheet.
6-40
F9445
Figure 15. Bus and Status Control Timing'
SVMBOLAND
(PIN#)
ClK (40)
so
S1G
S1
S4
S3
52
55
SO
nJILfl-nSLJL.JLJLJ
I::
- 1-
TC(S)
TC(S)
SYN (7)
TC(SO)-
1-
~
wi
STRBD (6)
TC(SA)
STiiBi(S)
-
~
I
INT REO (3D)
i
I
TREj(C)-I_
i-TC(BG)'
CoNiiEa (28)
Mii (33)
i'L
DCH REO (29)
l
:j -
-TDRh(C)~
•• 5C'ii'REQ (29)
l
- 1I
-
ABORT (32)
TA(C)
-
TA(C)
_Tc(BR)]
BUS REO (38)
CARRY(39).
INTON(27)
-
TC(CY)
.1:
-TC(R)j
RUN 137)
)
TC(Bl)l-
iiUSiOCK (2)
WAIT FOR
BUS GNT
i-TC( SO)
IR
w"~'
TBG(C)---j
BUSGNT(3)
Tc(SD)E
t:
BUS GNT
RECOGNIZED
·See Timing Parameter Symbol Conventions at end of data sheet.
""If this DCH REQ set·up time is missed, it is not recognized for another complete cycle.
6·41
r
- I - T C ( REQ)x
•
F9445
Guaranteed Operating Ranges
Part Number Supply Voltage (Vecl
Typ
Min
Max
F9445DC
F9445DM
4.75 V
4.5V
5.0V
5.0V
Ambient
Temperature
5.25 V
Oto + 75°C
5.5V - 55 to + 125°C
DC Characteristics
(Over guaranteed operating ranges unless other wise noted.)
I,NJ(min) = 300 mA; I'NJ(max) = 400 mA
Symbol
Characteristic
Min
V'H
Input HIGH Voltage
2.0
V,"
Input lOW Voltage
VeD
Input Clamp Diode Voltage
VOH
Output HIGH Voltage; RUN, CARRY,
INTON, SYN, STRBD, BUSREQ, STRBA,
Oo,O"M
2.4
2.4
Typ
-0.9
Max
Unit
Test Cqnditions
V
Guaranteed Input HIGH Voltage
0.8
V
Guaranteed Input lOW Voltage
-1.5
V
Vee = Min, I'N = -18 mA, I'NJ = 300 mA
V
Vee = Min, 10H = -400 }LA, I'NJ = 300 mA
3.4
V
Vee = Min, 10H = -1.0 mA, I'NJ = 300 mA
0.25
0.5
V
Vee = Min, 10l = 8.0 mA, I'NJ = 300 mA
Input HIGH Current; DCHREQ, INTREQ,
ClK, MR, RDYA, RDYD, ABORT,
CONREQ,BUSGNT
2.0
40
}LA
Vee = Max, V'N = 2.7 V, I'NJ = 300 mA
I'H
Input HIGH Current; IB(()"5' (3-state)
5.0
100
}LA
Vee = Max, V'N = 2.7 V, I'NJ - 300 mA
I'H
Input HIGH Current; All inputs
1.0
mA
Vee = Max, V'N = 5.5 V, I'NJ = 300 mA
I,"
Input lOW Current; All Inputs
-0.4
mA
Vee = Max, V'N = 0.4 V, I'NJ = 300 mA
10zH
Output O.£F State (High Impedance)
Current I B,0.,5., W
100
}LA
Vee = Max, VOUT = 2.4 V, I'NJ = 300 mA
-400
}LA
Vee = Max, VOUT
-100
}LA
Vee = Max, VOUT = 0.5 V, I'NJ = 300 mA
-100
mA
Vee = Max, VOUT = 0.0 V, I'NJ = 300 mA'
1.0
VOH
Output HIGH Voltage; IB(()"5" W
Val
Output lOW Voltage
I'H
IOZL
-0.21
Output O.£F State (High Impedance)
Current IB,0"5
lozl
Output O£.F State (High Impedance)
Current; W
lasH
Output Short Circuit Current; All
Outputs Except BUS lOCK
3.4
-210
-15
=
0.4 V, I'NJ = 300 mA
ILDH
Output leakage; BUSlOCK
mA
Vee = Min, VOH = 5.25 V, I'NJ = 300 mA
Icc
Supply Current
160
mA
Vee = Max, I'NJ = 300 mA
V'NJ
Injector Voltage
1.3
V
*Not more than one output to be shorted at a time,
6·42
I'NJ = 400 mA
F9445
AC Characteristics
T. = 0 to 75°C; Vee = 4.75 to 5.25 V; I'NJ = 300 mA; CL = 15 pF.
Input conditioning: Rise Time = 6 ns; Fall time = 6 ns; Amplitude
= Oto 3 V
Refer to Symbol Conventions at the end of this data sheet for explanation of the timing parameter symbols.
Symbol
Characteristic
TC(O)
Propagation delay, ClK to 0 0, 0 " M
Min
Typ
60
Max
Unit
ns
TC(S)
Propagation delay, ClK to SYN
30
ns
TC(W)
Propagation delay, ClK to IN
70
ns
TC(W)z
Propagation delay, ClK to.IN going 3-state
70
ns
TC(IBA)
Propagation delay, ClK to IB(0"5)' address
60
ns
TC(IBA)z
Propagation delay, ClK to IB(0"5)' address, going 3-state (read
cycle)
35
ns
TC(SA)
Propagation delay, ClK to STRBA
30
ns
TC(IBD)
Propagation delay, ClK to IB(1l-15)' data out
75
ns
TC(IBD)z
Propagation delay, ClK to I BIO• ,5), data out, going three-state
35
ns
TC(SD)
Propagation delay, ClK to STRBD
25
ns
TRA(C)
TC(RA)x
Setup time, RDYA to ClK
Hold time, ClK to RDYA
3
10
ns
ns
TRD(C)
TC(RD)x
Setup time, RDYD to ClK
Hold time, ClK to RDYD
2
10
ns
ns
TIBD(C)
Setup time, IB(0"5)' data in, to ClK (read or fetch cycle)
75
ns
TC(IBD)x
Hold time, IB(0"5)' data in, after ClK (read or fetch cycle)
25
ns
TREQ(C)
Setup time, INTREQ, DCHREQ, CONREQ, MR to ClK, all
are the same timing relative to S5
15
ns
TC(REQ)x
Hold time, INTREQ, DCHREQ, CONREQ, MR after ClK, all are
the same timing
20
ns
TDRh(C)
Data channel (DCHREQ) off setup time from ClK (to finish
data-channel cycle)
100
ns
TA(C)
Setup time, ABORT to ClK
30
ns
TC(Bl)1
Propagation delay, ClK to BUSlOCK going lOW
35
ns
TBG(C)
TC(BG)x
Setup time, BUSGNT to ClK
Hold time, ClK after BUSGNT
10
10
ns
ns
TC(R)
Propagation delay, ClK to RUN
80
ns
TC(CY)
Propagation delay, ClK to CARRY
50
ns
TC(INT)
Propagation delay, ClK to INTON
50
ns
TC(BR)
Propagation delay, ClK to BUSREQ
40
ns
6-43
II
F9445
TIming Parameter Symbol Conventions
The abbreviated symbols used for ac characteristic timing parameters in this data sheet are defined as follows:
The timing symbol convention is: TAb(C)d
The timing symbols all begin with the letter "T".
The second position, represented by "A", indicates the signal node beginning the interval.
The position "b" defines the direction of signal transition at the beginning node "A", if such definition is necessary; the new
state of the signal may. be: I = Low; h = High; z := 3-state; x = Oon't care; v = Valid
The position "C", which always appears within parentheses, indicates the signal node ending the interval.
The position "d" is the same as "b" but refers to the state of the signal at the node indicated by the mnemonic in position "C".
Ordering Information
ORDER CODE
SPEED
TEMPERATURE
For other temperature ranges; contact Fairchild Sales Office.
F9445·24 DC
F9445·24 OM
F9445·24 DMOS
24 MHz
24 MHz
24 MHz
O°C to +75°C
-55°C to +125°C
-55°C to +125°C
All packages are Ceramic DIPs
F9445-20 DC
F9445-20 OM
F9445-20 DMOS
20 MHz
20 MHz
20 MHz
O°C to +75°C
-55°C to +125°C
-55°C to +125°C
F9445-16DC
F9445-16 OM
F9445-16DMOS
16 MHz
16 MHz
16 MHz
O°C to +75°C
-55°C to +125°C
-55°C to +125°C
6<44
F9446
Dynamic Memory Controller
Advance Product Information
Microprocessor Product
Description
Connection Diagram
The Fairchild F9446 Dynamic Memory Controller (DMC) is
designed to support a variety of memory configurations and
provide an interface between 16K and 64K memory chips
and the .F9445 central processing unit (CPU). It provides a
16-bit memory address register (MAR), an address ..
multiplexer for the row, column, and refresh addresses, a
timing generator for the row and column strobe signals and
the write enable signal (RAS-CAS-WE), mod.e arbitration,
and page mode logic. It is Implemented in 13 L"' bipolar
technology with low-power Schottky-compatible inputs
and outputs.
Vee
liAS.
W,
W.
I!n',
m
w£
es
M!lmIEll
!mmmT
RDYD
PAll'E
I5LYlIAI
16-blt Memory Address Register
Ability to Accommodate a Variety of Memory Speeds
16K or 64K DRAMs
Automatic Page Mode
Internal Refresh Address Counter
Row/Column/Refresh Multiplexer
Complete Memory Timing Signals
Thre.state Outputs for Multlport Memories
Internal Refresh Rate Timer
Low-power Schottky-compatlble I/O
13L Bipolar Technology
64-Pln DIP
Opereting Temperature Range of from
- 55°C to + 125°C
~
GND
DlVEND
GND
RFSH
RDYM
DJ:YClj[
WI!I'rr
elK
~
mID
SPEED 1/256K
SPEEDO/RMW
MEX
TlMODE
BANKS
REFMODE
TYPE
A15
6·45
II
F9446
The F9446 Incorporates an address multiplexer and memory
timing generator for use with both static and dynamic
memories. The multiplexer selects between row and column segments of the Internal 16-bit memory address
register (MAR) or an Internal refresh address counter (RAC).
The upper two address bits provide bank Information, while
the lower 'seven, eight, or nine address bits are multiplexed to provide row, column, and refresh address. Assertion
of the static line supresses row/column multiplexing of
the memory address register outputs, which then provides
the full16-bIt address.
Signal Descriptions
CLOCK
RY HANDSHAKE
MEMORY BUS {
CONTROL
MEMORY ADDRESS
The memory timing sequence is initiated by the memory execute signal; It may be Inhibited or aborted by removal of
the chip select signal. Once started, the memory timing sequence is automatic. A choice of four speed grades accom·
modates a variety of memory access times,and external
controls may be used to further modify the timing.
ORMATION BUS
STRAPS FOR MEMORY TYPE
SPEED SELECTION
OPTIONAL {
DECODED
INPUTS
The four individual RAS lines accommodate· from one to
four banks of memory chips, with automatic satisfaction of
precharge requirements for memory access and refresh, in
page mode or not, with distributed refresh or bulk refresh.
Refreshes are initiated to satisfy a rate of 128 per 2 ms per
RAS bank. For short intervals, they may automatically be
deferred until non memory CPU cycles; this makes them
semi-transparent.
A memory bus request and memory bus grant are provided
to govern 3-state control of memory interface signals for
multi port or DMA purposes.
6-46
F9447
110 Bus Controller
Advance Product Information
Microprocessor Product
Description
•
•
Interfaces Directly to the F9445
Controls Standard and Hlgh·Speed NOVA·Compatible ~
Data Channels
• NOVA·Compatible or F9445 1/0 and Data Channel
Timing
• Complete NOVA·Compatible 110 Bus Interface
• Automatic Program Load
• Power·Up Reset Delay
• Console Interface
• Local Busy/Done/Interrupt Logic
• Low-Power Schottky·Compatible 110
• 64·Pin DIP or Optional Chip Carrier Package
• 13L Technology
• Operating Temperature Range of from - 55°C to
+ 125°C
The F9447 1/0 Bus Controller (IOC) is used with the
F9445 13 L'" 16-Bit Bipolar Microprocessor to demultiplex
the 1/0 instruction and data of the information bus (IB)_ It
provides all the timing and decode signals required for
programmed or data channel (DCH) inputloutput to
peripheral device controllers. In the NOVA'" -compatible
mode, the F9447 provides all the timing and signals
required by that 1/0 bus. For DCH transfers, address
generation and handshake can be handled by the F9449
Multiple Data Channel Controller.
Signal Functions
CLOCK
CPU
HANDSHAKE
1-
Connection Diagram
CLK
1_
10PRI
ClK
DIA
[jf1!
1m:
iNTA
SKP
DOC
~
CLEAR
(INTPOUT) .(Ji[EIiI
START
(BUSY)~
~
}INPUT
DOA
DOij
}OUTPUT
PROGRAMMED
I/O
STROBES
(DONE) CONCD
DOA
RQENB
DOij
10RST
MSKO
START
CLEAR
PULSE
GLOBAL
I
liS"
M
CONTROL
Vi
(STRBDN)
CONm
11/0 HANDSHAKE
DCHI
DCHO
DeHMO
RQENB
DIEN
DOEN
(INTPIN)
I
IlII
AI'l:SW
(STRBSY)~
DATA CHANNEL
HANDSHAKE
I/O SYNCHRONIZATION
} DATA BUFFER CONTROL
=
1-
GLOBAL
L
110 PORT
STATUS INPUT -
-------Vee
11NJ
~iRK:~~
GND
MSKO
DCHO
DiA
DIB
t
Vee
10CS
i
IINJ
GND
• )'L is a registered trademark of Fairchild Camera and Instrument
Corp.
• NOVA is a trademark of Data General Corporation.
6-47
SKP
DCHA
DCHMO
I/O PORT
STATUS OUTPUT
STRBDN
INTPIN
f1!7
186
iSs
fOim'
MRCAP
DIEN
OND
ills
INTA
DCHREQ
CONSOLE
CONTROL
OUTPUT
DOC
ill.
GND
DCHI
!
Vee
CONEN (MSKBiT)
lilC
10EX
STRBD
SYN
DOEN
STRBA
DSEN
RDYD
10BSY
RYDA
RDYM
O.
DCHEX
0,
10ENA
w.
ME
W,
INJ
W2
II
F9447
The F9447 110 controller Is a decoder and timing
generator for programmed 110 instructions and data
channel transfers. The timing sequence is selected via a
three-bit control code, WO-W2 • Additional logic is
.
included to Implement either the basic console interface
or a busy/donelinterrupt function. A hysteresis circuit for
deriving a power-on-reset, from an external capacitor to
ground, is also included. Figure 1 is a typical block
diagram of the F9447 I/O controller. Figure 2 shows how
the F9447 can be used with the F9445 system.
Signal Description
Table 1 describes the F9447 signals.
Figure 1
F9447 Block Diagram
PERIPHERAL
CONTROL BUS
F9445
CONTROL
BUS
----y
BUSY/DONE/
INTERRUPT
OR CONSOLE
INPUT
BUSY/DONE/
INTERRUPT
OR CONSOLE
OUTPUT
GLOBAL------------'
6-48
F9447
Figure 2
System Configuration
Vee
USER OPTION
1
DEY.
CODE
II
RISETEOoo-
OTHER
CONSOLE
SWITCHES
{
STEP
APL
10000-0-0--
~~------------I
'OPEN COLLECTOR
OUTPUTS, REQUIRE
PULL·UP RESISTORS.
6·49
F9447
Table 1
F9447 Signal Descriptions
pIn No.
Name
Description
2
Clock
A synchronizing input signal primarily for timing non-F9445
mode intervals through a state counter clock on alternate
positive edges.
SYN
41
Synchronize
An input signal from the CPU that maintains system timing.
STRBA
40
Strobe Address
An active low input signal that indicates an address portion of
the CPU cycle (and instruction during I/O execute).
RDYA
38
Ready Address
An active high open-collector output signal that allows the
CPU to continue beyond the address portion of the cycle.
S'i'RBfj
42
Strobe Data
An active low input signal that indicates the data portion of
the CPU cycle.
RDYD
39
Ready Data
An active high open-collector output signal that allows the
CPU to continue beyond the data portion of the cycle.
RDYM
28
Ready Memory
A bidirectional, open collector signal; an active high input
during a data channel output cycle indicates that the memory
has fetched the data. An active high output during a data
channel input cycle indicates to memory that the input data is
valid and a write may proceed.
ME
31
Memory Enable
An active low output that modifies the memory controller to
respond 'for CPU memory accesses or for data channel cycles
(ME=M+0
Mnemonic
Clock
ClK
CPU Handshake
Memory
Handshake
1.°0),
CPU Cycle Type
M
10
°0°1
36
37
W
11
Memory
° Lines
Write
An active low input from the CPU that indicates a memory
type of cycle.
A pair of input signals from the CPU to indicate the type of
cycle.
An active low input signal from the F9445 that indicates a
cycle during which data is to be written to a memory or I/O
device.
6-50
F9447
Mnemonic
Pin No.
Name
Description
10PRI
1
1/0 Priority
An active high input that enables the F9447 to begin an I/O or
data channel cycle.
10CS
24
1/0 Chip Select
An active high input enables strobes for busy and done, as
well as 1/0 control decodes.
D'S77
9
Device Select 77
An active low input signal that indicates a decode of iB 1O -iB '5
all active, a device code 77 (CPU class) 1/0 instruction.
10ENA
30
1/0 Enable
An active high input that, when low, inhibits response by the
F9447 to any F9445-programmed 1/0 cycle. Used with multiple
F9447s to allow disables.
DCHREQ
22
Data Channel
Request
An active low input that indicates there is a data channel
request.
33
34
35
Timing Options
A three-bit input code; the decodes provide a selection of
timing for 1/0 and data channel cycles.
52-56
Information Bus
Active low input signals from the F9445 containing 1/0
instruction bits 5 through 9 during address phase of 110
execute cycles.
MR
13
Master System
Reset
An open-collector bidirectional pin that, when pulled low,
initializes the F9447 and activates i5RSf. Also an output
generated by a low level on MRCAP.
MRCAP
17
Capacitive Reset
An active low input with an internal resistive pullup of 10K
ohms to Vee .
Cycle Enable
Peripheral Timing
Mode Select
W2
W,
Wo
1/0 Instruction
Field
iB5-iB9
Reset
• The F9447 does not modify the F9445 timing for the following control instructions: READS, ION, APL, HAI-T.
6-51
•
F9447
Table 1
F9447 Signal Descriptions (Cont'd.)
Mnemonic
Console 1/0 Select
Pin No.
Name
Description
GLOBAL
8
Global (Local)
An input that selects one of two uses of the global and local
modes.
DIB
DIC.
SKP
50
Data-In-A
Data-In-B
Data-In-C
Interrupt
Acknowledge
Skip
Active low timing strobe outputs that indicate execution of
data input instructions.
iN'i'A
46
45
44
49
DOA
DOB
DOC
59
58
57
Data-Out-A
Data-Out-B
Data-Out-C
Timing strobe outputs (all active low except active high
MSKO) that indicate execution of data output instructions.
10RST
51
110 Reset
An active low output that indicates either a decode of the
execution.£f..!!!!LlORST instruction or a system reset caused
by MR or MRCAP active.
MSKO
47
Mask Out
S'fARi'
61
62
60
Start
Clear
Pulse
Active-low control outputs that indicate decode and time of
start, clear, and pulse control functions during programmed
1/0 execution.
DSEN
26
Device Select
Enable
An active low output that enables device select.
10EX
43
1/0 Execute
An active low output indicating that the F9447 is involved in
the execution of a programmed 1/0 cycle.
10BSY
27
1/0 Busy
An active low input indicating that another source is using the
1/0 bus. An active low output is provided when the F9447 is
about to or is executing an 110 cycle.
i5CHEX
29
Data Channel
Execute
An active low output indicating that a data channel transfer
is in progress.
DCHA
18
Data Channel
Address
An active low timing strobe output that defines address
transfer time of a data channel cycle.
DCHI
20
Data Channel In
An active low timing strobe output that defines data transfer
in (write to memory) of a data channel cycle.
Programmed 1/0
Strobes
i5iA
CLEAR
PULSE
110 Handshake
Data·Channel
Handshake
6-52
F9447
Mnemonic
Pin No.
Name
Description
DCHO
19
Data Channel Out
An active low timing strobe that is output during data transfer
out (write to peripheral) of a data channel.
DCHMO
23
Data Channel
Mode Out
An active high input results in data channel output cycles.
7
Request Enable
A timing output that synchronizes interrupt and data-channel
priorities.
-OlEN
21
Data In Enable
An active low output that enables peripheral data onto the
F9445 information bus during programmed 1/0 or data-channel
input cycles.
DOEN
25
Data Out Enable
An active low output that enables information bus data onto
the peripheral data bus during programmed 1/0 or datachannel output cycles.
CONSW
---
15
Console Switch
An active low input with internal 2.4K-ohm pullup resistor to
Vcc and digital delay of approximately 3 ms to eliminate
contact bounce.
CONSTP
12
Console Step
An active low input with characteristics of CONSW that
initiates a console request lasting for two console code cycles
of the F9445.
APLSW
14
Auto Program
Load Switch
An active low input with characteristics ofCONSW and
CONSTP that initiates a console request cycle with APL
enable active.
--CONEN
63
Console Enable
An active low output to enable a console to provide
information to the IB of the F9445 during a read or write
operation.
CONREQ
5
Console Request
An active low output to theF9445 to request console service.
C5NCi5
6
Console Code
An active low output to enable the console code onto the IB
of the F9445 in response to a console code cycle of the F9445.
APLEN
4
Auto Program
Load Enable
An active low output initiated by an APLSW input or the
execution of (DOA ac, CPU) instruction and terminated by the
execution of a (DOAP ac, CPU) instruction or system reset.
--CONLD
3
Console Load
1/0
Synchronization
RQENB
Data Buffer
Control
Console Control
Input
Console Control
Output
---
An active low output to enable the console to latch data from
the IB of the F9445.
6-53
F9447
Table 1
F9447 Signal Descriptions, Cont'd.
Mnemonic
Pin No.
Name
Description
MsKeii'
63
Mask Bit
The local logic contains an Interrupt disable flag loaded from
a select bit of the F9445 Information bus during the execution
of a mask out instruction. The MSKBIT signal is driven by that
selected bit of the IB; a low level at the beginning of MSKO
execution sets the Interrupt disable flag.
STRBSY
15
Strobe Busy
A negative·going input edge that strobes the BUSY flag to the
clear state.
STRBDN
12
Strobe Done
A negative·going input edge that strobes the DONE flag to the
true state.
INTPIN
14
Interrupt Priority In
An active high input that determines which peripheral device
may interrupt.
BUSY
5
Busy Flag
An active high output of a flip·flop is set by the execution of
an 1I0·Start cycle with 110 Chip Select (IOCS) high; and
cleared by a similar 1/0·Clear cycle, by a negative transition
on STRBSY, by execution of an 10RST instruction, or by a low
level on MR.
DONE
6
Done Flag
An active high output of a flip·flop Is set by a negative
transition on STRBDN; cleared by the execution of an 1I0-8tart
or 1I0·Clear while 110 Chip Select (IOCS) Is high, by the_
execution of an 10RST instruction, or by a low level on MR.
INTPOUT
4
Interrupt
Priority Out
An active high output that determines which peripheral device
may Interrupt.
CONLD
3
Console Load
An active low output that enables the console to latch data
from the F9445 information bus.
Vee
64
Power Supply
Nominal + 5 V DC.
III~J
32
Injection Current
Constant current (80 mAl obtained by using a dropping
resistor from Vee (nominal V1NJ = 1.3 V). Use of bypass
capacitor to GND is desirable.
GND
16,48
Ground
Common power and signal return.
itO Port Status
Input
ItO Port Status
Output
Power
6·54
F9448
Programmable Multiport
Interface
Advance Product Information
Microprocessor Product
Description
•
•
The F9448 Programmable Multiport Interface (PMI) is 64
pin bipolar 13L device that facilitates the interface
between an F9445 16·bit bipolar microprocessor and
many industry·standard inputloutput (110) devices. It
decodes 110 instructions and memory addresses from
the central processing unit (CPU) to communicate with
devices tied to its four external ports. When used with
the F9449 Multiple Data Channel Controller, it handles
peripheral selection and timing during data channel
cycles. Some of the features of the F9448 are:
•
•
•
Four Independent 1/0 Ports
Memory·Mapped and Programmed 110
Interface with Serial, Parallel, DMA, and Other
Speclal·Purpose Devices
• Programmable Peripheral Timing
•
•
•
•
•
Compatibility with Many Industry·Standard Interfaces
Ability to Implement F9445·Programmed 1/0
Flags
Interrupt Arbitration and Response Handling
Fabricated in 13 L® Bipolar VLSI Technology
Operating Temperature Range - 55· to + 125·C
64-Pin Package
Low-Power Schottky Compatible I/O
The F9448 PMI ties the F9445 CPU to many industry·
standard microprocessor interfaces. It easily links 1/0
devices designed for the F6800 or 8080 buses and those
directly suitable for the F9445 110 bus. The system
configuration in figure 1 shows how the F9448 can be
used to interface F6800, 8086 family 110 devices or the
F3870 to the F9445 system.
~
I'L Is a registered trademark of Fairchild Camera and Instrument
Corp.
•
}
DATA
BUFFER/LATCHES
CONTROL
}
READY PERIPHERAL
PERIPHERAL
PORT
CONTROL
F9448
Figure 1 System Configuration
r;:=::=:::::::;::===:========~rrw~
I
1
~_ii,-ii"
Y c c - All?'"'
LI
FI44IPMI
_ClC,
---.. C~
USER OPTION
Ne
110 - ii15 iiCHiiEQ
~
Vi
I
~
--
I
0.1--0, I---
.....
!i
OUTI~-----.......J
I--;-
OUTDI-------·
"DVPI--
AOYD
vcc-
IE
~
Pi,1---------I~
INTPIN
il-
I
0.0,
DECODER
=:
INTPOUT
i
~
Cs, cs,
-
Fl...
DATA
CHANNEL
CONTROLLER
~
_iii
_Vi
c..J\,.
~
MEMOOV
:::=
I--
~
ADDRESS
A
..."AM"
~
~r-
_
BV.
I
DIACONnl--------
-mii
.,.!.. ROYA
iii.
1+-------.
D:;~
:~e
f--=-
l--iToiii
I--I---ilii
IOENI'--t--+-'
::t:::=U~SE;'.;:;O~PT:!.!IO"'H'-___ =::~A:~~
-0,
CLK
ii
_
_
DlRINT
f.--
HC
USER OPTION
1--...;'":;,,...-;;'0,;::'------1
III
W
viToiii
6-56
xx
110
A
0
S'Iii
-0.
:-1-
"0
DEVICE
1--;:-, Ci
1--:-'''
~I'--t--+----l
DCHACK,. t---
_iI
A
D
MARENI+-+--+---'
OUTsciiDI
DcHiiEQ
CB
I
DCHiCK, f.--
I .,. I
-
~~~l:= ~
r----
mm.f-
8
! 1i!
Ci
b .
::::I-~_____,-__ b~l::Y:B D~~E
!.
.~
f
~
I~
~I l2' D:r~E
mmm.1-~.f-
Pi,
S
.
i!
IL-
sm::f-
=~
CLK
Vee
a
OUT,I--------~
~ ilii
lK
~
a
1------......-I
OUT2
ifIiiiD
I-'-
i!
OUT3~-----.......J
STR88Zs
r
.J
OUT.~-----......
OUT.~-----.......J
~ mii
~
I-f'fiR f -
CLK
CciNiiEQ iiifRiQ
RDVM
I---
CLK
ROYD
~
~
0,
miD I--
I
"'.HI-------'
BVH
ROYA I - -
~
BUFENAI-----'
csc,
1---0.
I-fiiiii I--
MICROPAOCESSOA BYN
01"
_
I-- Vi
I--- M
iiI--
~
ENA
·OPEN COLLECTOR OUTPUTS
AlaUIRE PULL·UP REIIITOR
D~~?CE
F9448
Registers
11-bit memory-base address register used in conjuction
with memory-mapped 1/0. Figure 2 shows the F9448
program-accessible registers.
Each port has a 16-blt configuration register and busy,
done, and interrupt-disable flags. Port 4 also has an
Figure 2
F9448 Software Model
I
PORT4
CR(4)
1
FORMAT
• 0
I
1
I 2
1
TIMING
• 3
1 4
I
1
5
MASK BIT
6 1 7
I
8
I II"
10
I
a
4K
32
512
6
7
9
8
PORT3
CR(3)
1
1
FORMAT
TIMING
1
MASK BIT
1
1 10
I
I
DEVICE CODE
L·-0-+1--1~'~2-L~3~1--4-L'~5~~6~1~7~'~8-'~9-+~1~0~'~11-L'~1~2+1-1~3-L'~14~'~1~5~
PORT2
C'R(2)
'I
I
FORMAT
- 0
1 1 '
2 -
TIMING
PORT1
TIMING
3
PORn
CR(O)
I
Po
I
4
I 5'
p.
1=
P~
MASK BIT
P,
I
6
1 7'6'9
0
I
7 I 8
4K ; 7 = 321'
1
DEVICE CODE
10 I 11 ' 12
MASK BIT
I
I
13 ' 14 ' 15
I
DEVICE CODE
11
I 9
1 BLOCK SIZE IMMP 1 ~
PORT ENABLES
P,
I
3 1 4'56
'1
~
I
!
12
I 13
PULSE ENABLE
P,
p.
P,
p.
!
14
1
15
N! I
~
~0~-1~~2-L~3~~4~~5~~6~~7~-8~~9~~1~0~~11~~12~~1~3-L~14~~1~5~
6·57
•
F9448
1/0 Ports
Transactions between the F9448 and peripheral devices
are organized using several select, address, and timing
signals. Out 0- 6 signals are shared by all ports, while
each set of Peripheral Port Controls is associated with a
specific port.
The F9448 performs selecting and handshaking with
connected peripheral devices. It has five bidirectional
ports numbered 0 through 4. Port 0 is used as a
bootstrap port by the F9445 to read and write, address
and configuration registers inside the F9448; ports 1
through 4 are used to communiate with external
peripheral devices. Ports 0 through 3 respond only to
programmed 1/0 instructions; port 4 responds to either
1/0 instructions or memory cycles. This latter feature
enables a block of up to 4096 memory addresses to be
used for memory-mapped 1/0.
Table 1
Signal Descriptions
Table 1 describes the signals for the F9448.
F9448 Signal Descriptions
Pin No.
Name
Description
45
Clock
Input signal from the positive-edge-triggered master clock
from which all F9448 timing is generated.
SYN
40
Synchronize
An input signal from the F9445 for synchronizing the F9445
with external devices. Active during every CPU cycle.
STRBA
38
Strobe Address
An input Signal generated by the F9445 during external bus
cycles.
STRBD
39
Strobe Data
An input signal generated by the F9445 during data transfer
time and used by F9448 to organize transfers.
RDYD
52
Data Ready
An active high open collector output signal synchronizing
F9448 with F9445 during data transfers. A low level stalls the
F9445 until the peripheral is ready.
53
Memory Ready
Handshake between the memory controller and F9448 during
data-channel cycles. Input to F9448 during data-channel read
from memory; output from F9448 during data-channel write to
memory.
01
00
49
50
51
Memory
O-Line
O-Line
Input status lines from the F9445 indicating the type of bus
cycle.
W
37
Write
An input signal indicating the direction of data transfer on the
lB.
ABORT
46
Abort
A low input signal from the Memory Management and
Protection Unit that prevents the F9448 from starting another
cycle but allows completion of the current cycle.
Mnemonic
Clock
ClK
CPU Handshake
Ready Memory
RDYM
CPU Cycle Type
M
6·58
F9448
Table 1
F9448 Signal Descriptions (Cont'd.)
Mnemonic
Device Code
Jumpers
Pin No.
Name
Description
CSCO·CSC2
22·24
Chip Select Code
Input signals tied to Vce , GND, SYN, or SYN to define a 6·blt
device code, DS 10 through DS 15 for port 0 of F9448.
56-63, 1·8
Information Bus
A 16·bit, three·state address and data bus for transmitting
information between the F9445 and external devices.
INTPIN
43
Interrupt
Priority Input
An input for determining which peripheral device will respond
to an INTA instruction.
INTPOUT
44
Interrupt
Priority Output
A priority·signal output from the F9448 to lower·priority
devices for determining which peripheral device may interrupt.
55
Master Reset
An input signal that initializes the F9448 by clearing all F9448
user·accessible registers to 0 and clearing all busy, done, and
interrupt·disable flags.
LE
47
Latch Enable
An output signal that may be used to load the data from the
F9445 on the IB into peripheral data bus latches.
BUFENA
41
Buffer Enable
An active low output during memory, I/O, or data channel
cycles to enable IB transceivers or latches if data is to be
transferred between the IB and a device controlled by the
F9448.
DIRN
42
Direction
An output signal controlling the direction of any bus
transceivers on the IB bus between the F9445 and the F9448
or of any data latches/transceivers between the IB bus and a
peripheral data bus.
25·31
Outputs
A 7·bit peripheral output control bus that is to be shared by al
peripheral devices controlled by F9448.
54
Ready Peripheral
Open·collector handshake input signal from peripherals to the
F9448.
Information Bus
iBo·iB15
Interrupt Priority
Chain
Master Reset
MR
Data Bufferl
Latches Control
Peripheral Control
And Address Bus
OUTo·OUTs
Ready Peripheral
RDYP
6-59
•
F9448
Table 1
F9448 Signal Descriptions (Cont'd.)
Mnemonic
Pin No.
Name
Description
'l5S1,PS4
21,18,14,11
Port Select
Outputs for selecting the devices being controlled by ports 1
through 4 of the F9448.
STRBBZ1 •
STRBBZ4
20,17,13,10
Strobe Busy
A low·to·high transition on the
associated port's busy flag.
S'fRi3BZ input signal
STRBDN 1·
STRBDN 4
19, 15, 12,9
Strobe Done
A low·to·high transition on the
associated port's done flag.
STRBBiii
DCHACK1 •
DCHACK4
33·36
Data Channel
Acknowledge
Active low select inputs from the F9449 data channel
controller.
Vee
64
Power Supply
Nominal
GND
16, 48
Ground
Ground for both supply and signals.
IINJ
32
Injection Current
A constant current obtainable by use of a dropping reSistor
from Vee (V INJ ",13 V) supply. Use of a bypass capacitor to
GND is desirable.
Peripheral Port
Control
clears th e
input sets the
Power
6·60
+ 5 V DC.
F9449
Multiple Data
Channel Controller
Microprocessor Product
Connection Diagram
Description
The F9449 Multiple Data Channel Controller is a 4-port
controller that is used with the Fairchild F9445 16-Bit
Bipolar Microprocessor, and either an F9447 1/0 Bus
Controller or an F9448 Programmable Multiport Interface,
to control direct data transfer to and from memory by
peripheral devices. It contains four pairs of programcontrolled address and word count registers that are
multiplexed to control four fully independent data
channels (DCHs) through which data transfers can occur.
Data channel transfers are similar to direct memory
access (DMA) channel transfers, except that the F9445
architecture time-shares its information bus (IB).
vee
iii.
iii, 1
iB13
iii"
SYN
OCHREO
Me
STR
• Provides Control of Four Independent Channels
• Has Separate Word Count and Memory Address
Registers for Each Channel
• Supports Byte- or Word-mode Operation on Each
Channel
.
• Performs Internal Priority Arbitration
• Supports Memory-to·Memory Transfers
• Implemented in 13 L® Technology, with Low·power
Schottky TTL·compatlble Input and Output
• Available In a 64·Pln Package.
• Operating Temperature Range of from - 55°C to
+ 125°C
ClK
MAREN
M
10EN
0,
00
REO,
RE02
REQ3
REO.
ONO
OCHMO.
OCHMO.
OCHACK2
OlEN
BM,
BM2
OCHPOUT
BM.
OCHPIN
BM.
OCHMO,
TC,
TC2
OIRINT
ii14
ii10
®
13L Is a registered trademark of Fairchild Camera & Instrument Corp.
6-61
•
F9449
F9449 Signal Functions
F9449
8M.
iii" (LSB)
DCHMO.
PERIPHERAL
PORT
CONTROL
iiCHAci<2
INFORMATION
BUS
OCHM02
IB,
REQ,
iii2
8M,
DCHMO,
iiio(MSB)
DCHPIN
DCHPOUT
} REGISTER
CONTROL
SIGNALS
DCHREQ
DATA BUFFER CONTROL
OlEN
Mii
DCH DIRECTION
CONTROL
6-62
F9449
Fig. 1
F9449 Block Diagram
MSB
DCHMO,
DCHMO,
DCHMO,
MSB
BIT 0
DCHMO.
t-----TC,
DIRINT _ _ _oJ
I------TC,
t-----TC,
~~TC4
6-63
F9449
Register Operation
F$l449 I/O Cycle
The eight F9449 registers (MA1-4' WC1-4), shown in
figure 1, provide four fully independent data channels,
numbered 1 to 4, each of which is capable of transferring up to 32K 8-bit bytes or 16-bit words, depending
upon whether it is strapped for byte-mode or word-mode
operation. Figure 2 Illustrates the data formats of these
registers.
The F9449 registers are under software control. They are
loaded with starting address and word count information
through F9445 programmed output instructions, which
are decoded by the F9447 I/O controller or F9448
multiport interface. The F9445 also generates the clock
(ClK), synchronize (SYN), address strobe (STRBA), and
data strobe (STRBD) bus timing signals. (Figure 5
illustrates the I/O cycle timing; refer to the "Timing
Characteristics" section for a description of the cycle
characteristics and specifications.)
A word count (WC) register associated with each
channel contains the number of bytes or words to be
transferred by that channel. The WC registers, which are
loaded with the twos complement of the number of bytes
or words, are automatically incremented after each DCH
cycle (I.e., after every byte or word transfer), regardless
of operating mode. When a WC register increments from
all ones to zero, a terminal count (TC) signal for that port
is set by the F9449. This is normally wired to the F9447
bus controller or F9448 multiport interface to generate
an interrupt to the F9445. (Figures 3 and 4 Illustrate
system configurations using the F9447 and F9448,
respectively.) The TC signal can optionally be used to
terminate any further requests from that peripheral
channel.
Figure 2
All eight registers are cleared when master reset (MR)
goes low to allow hardware implementation of auto
load/bootstrap routines (I.e., to fill the memory beginning
at address 0).
The F9445 can read the contents of any register by
means of a programmed input instruction, which is
decoded by the F9447 or F9448 in the same manner as
the output instruction.
Register Data Formats
o
IwI
The F9447 or F9448 selects the register to be loaded by
generating the appropriate port select (PS) signal,
~ther with input/output enable (IOEN) and strobe
(STR) signals, as shown in table 1. The low-to-high
transition of the STR signal during the write time loads
the addressed port WC or MA register, selected by the
memory address enable (MAREN) signal, with data from
th.e information bus.
15
MSB
Word Count
(Twos Complement)
lSB
I
F9449 DCH Cycle
A peripheral device requests service by asserting its
request (REO n) line to the F9449, which then determines
priority and generates a data channel request (DCHREO)
signal to the F9445. After completing its current program
instruction, the F9445 responds to the DCHREO or data
channel request performing a DCH cycle, which is a long
bus cycle similar to an F9445 memory cycle, but with the
information bus and the write rN) line not driven.
Format for word- or byte-count register load
(MAREN
0). Word count range is from -2 15 to 1
(loaded with twos complement). Vii is an internal
direction bit: 0 is from peripheral to memory; 1 is from
memory to peripheral.
=
o
I MSB
15
Memory Address
lSB
The F9445 sets the bus control lines as follows: Mhigh,
01 low, and 00 high (I.e., M, 01, 00 to 101). It then
generates the ClK, SYN, STRBA and STRBD bus timing
signals. The high-to-low transition of STRBA latches the
priority resolution logic, and starts the internal DCH
sequence of the F9449. The F9449 asserts the
appropriate data channel acknowledge (DCHACK n) line
to signal the requesting peripheral and the F9447 or
F9448 that a DCH cycle for it has begun. This may cause
the peripheral to remove the REO n signal. (Figure 6
illustrates the DCH cycle timing; refer to the "Timing
Format for memory address register load (MAR EN = 1).
Address range is from 0 to 216_1.
A memory address (MA) register"associated with each
channel contains the address at which the next transfer
is to occur; each MA register provides a 16-bit address
space (0 to 65535). The MA registers are incremented
after each transfer in word mode and after every second
transfer in byte mode.
6-64
F9449
Fig. 3
F9449/F9447 Configuration
~
UIER OPTION
'11v11,1
DeMREQ
~
i1-
a
0,-
I
ri
:::OPFIOCESSOR
ii'RiA
ROVA
I
STRia
'OVD
CLK
!
-[
~::LE
100--
OWITCHEO { .
STEP
CDN'tEO
J:;::oo--,
-
':"
..J>.
DATA
EO .R
-
T
.rf-
l INJEQ
~ :)
DATA
ADISPLAV
voo---
a
-0,
DlEN
.
IOSSV
MEMORY
ADDRESS
REGISTER
----
-J\.,
PRO.
834"
RAM
...
GLOIAl
i=
CCiNii?
iTiiif 5CHi --
eONCD
~-
CONLD
CLEAR
PULSE
ROENI
DCHE)(
~~
~
L.J
tI
L
DCHO
DeRMO
10EN
CHANNEL
CONTROLLER,
DCHREQ
MAREN
....
.A
0,
SVN
DCHMOn
iii.
DCHPIN
-~l
DCHPOUT _ N C
OlEN ~ Ne
iii
DlRINT
m;
UIEA OPTION
..!...NC
:=
t
III
W
STRID
6-65
J
Te.
STRBA
ROVA
iio-~I
"'I
DIA
OD.
iiRln
CLK
--
--<
IDEX
DCHACKn
PIn
0,
f---
"'.:::5
'--G(
~
~
DCHI
APtliii
~ iii
.f
~
MSKQ
APLSW
!I-
DEY.
CODE
,
'I
DOC
10RIT
CONREQ
~
OE
DDB
iTiiii
IIouJ iii
'o.
DDA
f-
~
•
INYA
i-
f---
mIi
....
DiC-
CLK
iii
_iii
l- i-
.~
-
iiii-
MRCAP
-
iECi
I
DiA
.:_wiii!
OiA
LE
DATA
-
o.
Ne..!.
....!...
CLK
r
CONSOLE
r;:
''t
iKP
iii!
-
WNWI--
DOE.
w,
w,
w,
_0,
00--
APL
CONSOLE
CODE
0,
IVN
~
lOP",
IOENA
NC_
=
:;:
--- [fJ ::;:
L
W
4
rc==:
,......
-OPEN COLLECTOR OUTPUTS
REOUIRE PUll-UP RESiSTOR
•
F9449
Fig. 4
F9449/F9448 Configuration
r-c=:
USER OPTION.
i:E
esc,
csen
DCHREQ
Vi
DIAN
OUTe
~
I-- Vi
I--- M
I--- O.
n.r-a, r-r-STRiA r-ROYA I ifRiD r--
I
~
ROYD
CLK
CONREQ INTREQ MR
~
~
OU12
OUT,
0,
RDYP
SVN
I---
9
I-
~
CLK
~
tz
I-
RDYD
CLK
MR
PS3
S'f'RiiZ3
I
~
~
'--
=>
1--7"~
~b ~
---
1
F9449
DATA
CHANNEL
CONTROLLER
r-
93453
PROM
-----0<1
STRBA
CS~
~A
--
~ DCiiiiEQ
ME
_Vi
'---
r---
-
t--
93471
RAM
REOn
_0.
DCI:IACK n
PSn
'---
iCn
p:
SVN
aMn
DCHPIN
DOUT
~y
~
LJ
tl
~ MR
I-----
CIRINT
L
lBo-ii,s
--
":::5l
Lo(
L....--
=>
PS n
(9448)
(9449)
).-~
-
PER 4 PORTS
-'OJ
Srii
USER OPTION
~
ME
w
STABD
6·66
110
I/O
A
_0
t
...
"""I
-
DCHACK n
---:-+" Ne
sa r--=- NC
OlEN
CLK
t
~
I--
OCHPOUT - N C
STRSD
WE
I:J\CS
'~'
DCHMO n
STRBA
FlOVA
ADDRESS
0"
-
[DEN
'---+ M
0
,.....--
MAREN
I--- 0,
~xx
110
~
I-I-DCHACK2
I-PS,
SfRiiiZ,
S'i'R'i"DN,
110
DEVICE
ib ·':.'
b-~~
L:
<.>
..J
STRBB~
INTPOUT
A
~-~~
t:=
I--
S'i'RiiiN2
INTPIN
CSoCS,
~~A
f--
'"'
PS,
DCHACK,
MEMORY
ADDAESS
REGISTER
i-
I-DCHACK4
I-STRBON.
it'
1 __
~
~
Si'RiBz. I--
Sffii6
SfFii'D'N3
i5"C'HACi<3
vcc-
0.0,
~
Ps4
r
DECODER
•~
OUTo
~ STRiA
F9445
MICROPROCESSOR SYN
~
~
OUTs
OUT3
M~
~
DIR
'f
iID'fENi
OUT.
IBo -IB15
~
ENA
CSC2
NC ----. RDYM
.~~
~
t80-1B,5
F9448 PMI
-
·OPEN COLLECTOR OUTPUTS
REQUIRE PULL-UP RESISTOR
DEVICE
F9449
Table 1
F9449 I/O Control
Signal State
Operation Performed
10EN
W
MAR EN
PS1
PS2
PS3
PS4
STR
0
X
X
X
X
X
X
1
X
1
X
1
X
1
X
1
No operation
No operation
1
1
0
0
0
1
U
U
Loads IB data into selected word count register
Loads IB data into selected memory address register
1
1
1
1
0
1
··
X
X
Loads selected word count register data onto IB
Loads selected memory address register data onto IB
·· ··
··
·· ··
··
··
·One active-low Input, selected by programmed 110 instruction device code.
Note
Multiple port selects result in unpredictable results.
o
1
Low
High
Donlt care
Low-te-hlgh transition
-----------------.
Programmed I/O Timing
so
Sl
S2
S3
S3
S3
S3
S3
54
CLK (66)
SYN(59)
ClK
SYN
-+---1
M(55)
+-__-+________________________
~
)
M
0, (53)~_________________
(1",
28-3~~ : : :
I.
-f.----------------....,Y
IOENW(S)
(11) .....
MAREN (10)
PS,~(12-1S)
I
'
f
~
STRIA (41)
(
Fig. 5
~
X
U
'-________________ M,W0" 02
IOEN
JI(~~t------------------------....J
--iTEN(lBO
'--------------- Ps
MAAEN
___'::-=-=-=-=-=-=-=-='T:M:~::I~:)::======.~-::======~~~~~~~====:t)II DATA OUT OF F_
__~__________ ii READ
-+l TSTR(IB)
ii FOR WRITE
----------------------~1-j(:~+~::;,II~DA~T~A~IN~T~O~F~-~==~=~)>-:::-:_---------- ji WRITE
r- TIl (STR)
I-~~--------------~--~~JL
~
TEN(ST~
1------+1--TSTR(EN)
I
-f
~I.~::::::~T~(S~T~R)~::::~.I
6-67
- -..
-~~---
STR
F9449
four F9449 controllers by interconnecting the data
channel priority out (DCHPOUT) of a higher priority
controller to data channel priority in (DCHPIN) of the
next, thereby permitting the system to serve a total of 16
data channel peripherals.
.
Characteristics" section for a description of the cycle
characteristics and specifications.)
During the address phase of a DCH cycle, the F9449
determines which peripheral is to be served, places the
contents of the appropriate MA register onto the
information bus and drives the W line to the memory
controller so that the memory performs either a read or a
write cycle. If internal direction {DIRINn is high,
read/write selection can be programmed from the F9445
as the most significant bit of the WC register contents
load. When this bit is at a logic 0 it causes a read of
memory. If the DIRINT pin is low, the read/write
selection is controlled by the peripheral through a data
channel mode (DCHMO n) signal. A high DCHMOn signal
indicates a memory read (DCH out operation). If required,
the data in enable (OlEN) and second byte (SB) lines are
also asserted at this time.
Priority resolution occurs during every cycle, at the highto-low trarisition of the SYN signal. In a ri-tultiple·F9449
system, all pending REo n inputs are latched at that time,
and the DCHPIN/DCHPOUT signals ripple from device to
device.
Priorities are reestablished during every cycle, including
"short" F9445 cycles. Additional states are generated by
the F9449 address ready (ROY A) signal to allow priority
ripple when the F9445 responds to a DCH. request from a
"wait" cycle.
Signal Descriptions
The F9449 RDYA signal causes the microprocessor to
generate three additional F9445 address strobe (S1G)
states, allowing the address sufficient time to propagate
from the F9449 to the memory controller.
The F9449 input and output signals are described in
table 2.
Timing Characteristics
The F9449 does not actually perform the data transfer
between memory and peripheral. Instead, the end of the
STRBA Signal causes the F9449 to stop driving the
address onto the information bus and allows the F9447
or F9448 to provide data control during the data phase of
the DCH cycle. It ,enables a peripheral three-state input
buffer, or strobes data out from the IB into the
peripheral. The data phase of the DCH cycle can be
extended as required by additional data (53) states
generated from the F9445 in response to the F9447 or
F9448 data ready (RDYD) output being low.
The timing characteristics of the F9449 are illustrated in
figure 5 (Programmed I/O Timing) and figure 6 (Data
Channel Cycle Timing).
The abbreviated symbol convention used for timing
parameters in this data sheet is TAb(C)d, where:
• Timing symbols all begin with the letter "T".
• The mnemonic in the position represented by "A"
indicates the Signal node beginning the interval.
• The mnemonic in the position represented by "b"
defines the direction of Signal transition at the
beginning node, if such definition is necessary;
the new state of the signal may be low (I), high (h),
3-state (z), don't care (x), or valid (v);
• The mnemonic in the position represented by "C",
which always appears in parentheses, indicates the
signal node ending the interval.
.
• The mnemonic in the position represented by "d"
is the same as "b", but refers to the state of the
signal al the node indicated by the mnemonic in
position "C".
Because it must communicate with the peripheral during
F9445 programmed I/O cycles, the F9447 or F9448
normally accommodates the data timing peculiarities of
the peripheral.
The end of the data strobe (STRBD) causes the WC and
MA registers to increment, a TC signal to be asserted !!.!.
the WC register has reached zero), and terminates the W,
DCHACKn, RDYA, and SB Signals.
.
Priority Arbitration
The F9449 arbitrates DCH requests from multiple
peripherals on a fixed-priority basis, with channel 1
having the highest priority and channel 4 the lowest. The
priority arbitration scheme allows cascading of up to
6-68
F9449
Figure 6
Data Channel Cycle Timing
. ClK
ClK(I8)
SYN (58) _ _ _ _-'!
SiiiiA
SYN
(41)
RDYA(7)
ii(5S)~
--A
0,,(53)
ME(s?)
-1
X
=101
DATA CHANNEL CYCLE
0, (54)
b
TMOO(ME)~~+---
I-TMOO(ME)
RDYA
ii, 0" 0"
Jfr----ME
\",,_~~.,...,.. _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _.,...,.._ _
-I tT~
I-
TSTRBD(W) -+i
W~:::>~~--~~::::::::::::::::::::::::::::::::::T5TA::B:JLt:.-+i:J\:r----w
\
STRBD(8)
WRlTt
!..EAD
STRID
I;: TSTRIIA(IBA)
-+i I-TC(lBA)
(
. ADDRESS OUT
)
ii(I-4,:ze.31,33-38,IIM3)-----~-..JC:::!~~~~:~>_~~---------------------1I
-oOj
I-TC(DIEN)
TSTRID(TC) -+i
D
A
E
R
'
-
-
-
WRITE
________________
~
~
~
~
~
~
~
~
BECOND BYTE OR EACH WORD
~
__
~
I'-_ _ _ _ _
DIEN
TSTRID(SB) -+i
FIRST BYTE
~
TSTRIlA(SB)
~
it (25)
f
~
-+i
I-TC(DIEN)
-+i
\.
-+i
...a.._.....J!
TC'04C31, 38. 27, 2I) _ _ _ _ _ _ _-:-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_____
-+i..;...tTSTRIAIDCHACK)
DCHACK,-4 (8, 411, 45, 44)
DCHACKo-.
__
-+i I - TDCHPlN(DCHPOUT)
DCHPOUT(43)-------------------i*
oCHPOUT .
-~-------------fl:·::::~·~I~T~DC~H~P~IN;~;;H;PO~U~T)~----------------
DCHPlN(42)-------------~""""I*~-------------------------DCHPIN
-11+- TDCHPlN(STRBA)
\
REG, ... (52, 51, &0. 48)
..
--jTREQ(SYN)i+-
--------------------~I
.j+-TDCHMO(W)--\
j ~TREQ(DCHREQ)
DC.HMO,-4(11,11;47,4Ol
TREQ(DCHREQ) --
I+-
:::::l"
_____:-~-------------------------------I-TDIRINT(W)-'--t
~IRINT(3?) ,\-;...._ _ _ _ _ _ _ _ _ _......,;..._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
6-69
F9449
Table 2
F9449 Signal Descriptions
Mnemonic
Pin No.
Description
Name
Clock
56
Clock
An input signal from the F9445 .. The rising edge of the single·
phase system clock causes action in the F9449. This line can
also be single·stepped for debugging.
SYN
59
Synchronize
An active·highinput signal from the CPU that maintains
system timing. The start of SYN indicates the start of a CPU
cycle with valid M, 01' 00 code.
STRBA
41
Address Strobe
An active·low input signal from the F9445. In a DCH cycle, the
low-to-high transition is used by the memory controller to
strobe the memory address from the IB into the selected MA
register. (This can be delayed indefinitely by RDYA.)
RDYA
7
Address Ready
An active-high open-collector output signal to the F9445. A
low level prolongs the STRBA signal to allow time for the
F9449 to. perform priority resolution and propagate the
memory address to the memory controller over the lB.
8
Data Strobe
An active-low input signal from the F9445. The low-to-high
transition during a DCH cycle causes the selected WC and
MA registers to increment and the VIi, DCHACK n, RDYA and
SB signals to terminate.
57
Memory Enable
An active-low output signal to the memory controller. When
low, it informs the memory controller that either the F9445 M
is low or a DCH cycle is in progress.
M
55
Memory
An active-low input signal from the F9445 that serves as a
status indicator. When it is low, the F9445 is performing a
memory cycle.
°10
54
53
Memory or
I/O Function
Active-high "0" line input signals from the F9445, used with
the ¥Vi input to indicate the type of cycle the F9445 is
performing. During a DCH cycle, fYi, 01' 00 are set at 101.
VIi
5
Write
An active-low input/output signal to and from the components
in the system, normally driven by the F9445 to control the read
and write operations. Placed in a high-impedance state by the
F9445, during a DCH cycle, when it is driven by the F9449, it is
low if the system is writing to memory and high if the system
is reading from memory.
ClK
CPU Handshake
Memory
ME
CPU Cycle Type
0
6-70
F9449
Table 2
F9449 Signal Descriptions (Cont.)
Mnemonic
Pin No.
Name
Description
Information Bus
Signals
1-4
28-31
33-36
60-63
Information Bus
A set of 16 input/output signals to and from the system. This
active-low, bidirectional bus is used to load and examine the
contents of the selected WC and MA registers. These signals
are driven by the selected MA register during the STRBA state
of an F9449 DCH cycle..:...The most significant bit is iBo; the
least significant bit is IB 15 .
DCHPIN
42
Data Channel
Priority Input
An active-high input signal from a higher-priority F9449 that is
used to extend priority resolution logic throughout a multipleF9449 system. When this signal is iow, it prevents the F9449
from being in a DCH cycle. The highest priority F9449 should
have DCHPIN connected high.
DCHPOUT
43
Data Channel
Priority Output
An active-high output signal to a lower-priority F9449 that is
used to extend priority resolution logic throughout a multiple·
F9449 system. When the signal is high, none of the four
channels are requesting a DCH cycle and DCHPIN is high.
DCHREQ
58
Data Channel
Request
An active-low open-collector output used by the F9449 to
request a DCH from the F9445. Multiple simultaneous
requests will be sorted by priority resolution logic during a
DCH cycle and will result in additional consecutive DCH
cycles. A low level requests a data channel cycle.
20
Data in Enable
An active-low output signal that can be used to enable an
optional bus transceiver placed between the F9449 and the lB.
When low, the F9449 is putting out an address during a DCH
cycle or data during an I/O read operation.
17
Master Reset
An input signal that is active-low from a power-up, front-panel,
or programmed initialization signal. It is used to load the WC
and MA registers with zeros, set the internal direction control
bit to zero, set the four TC signal lines high and clear the four
DCHACK lines.
52
Port Request
A set of four active-low input signals from the
corresponding requesting peripherals. A low signal on a ~
line indicates that its associated peripheral wishes a DCH n
cycle. Priority resolution logic arbitrates multiple requests and
generates a single acknowledge, REQ 1 having the highest
priority and REQ 4 the lowest.
iBo-iB15
Data Channel
Data Buffer
Control
Reset
Peripheral Port
Control
51
50
49
6-71
F9449
Table 2
F9449 Signal Descriptions (Cont.)
Mnemonic
I
Pin No.
Description
Name
....,.
DCHACK1"
DCHACK4
6
46
45
44
Data Channel
Acknowledge
TC1·TC4
39
38
27
26
Terminal Count
A set of four active·high output signals to the associated
peripherals, indicating completion of a DCH block. When a
WC register is incremented to zero during the last phase of a
DCH cycle, the corresponding TC line goes high. When the
WC register is I.oaded with any value from the IB during an I/O
write operation to the F9449, the corresponding TC line is
cleared to low. All four TC signals are set high by a low level
on MR.
PS4
12
13
14
15
Port Select
A set of four active·low input signals from a programmed
110 device. The IB bits are decoded by an F9448, which
oiJtputs a port select signal to the F9449. When low, the
associated port is selected during an I/O read or write
operation. No more than one PS line should be low at a time.
BM 1·BM4 ·
21
22
.23
24
Byte Mode
A set of four active·low input lines that are used to
establish operating modes. When strapped low, the
corresponding channel is set for 8·bit byte·mode operation;
when strapped high, the associated channel is set for 16·bit
word· mode operation.
DCHM01•
DCHM04
18
19
47
40
Data Channel
Mode Out
A set of input signals from the requesting peripherals. When.
DIRINT Is low, a DCHMOn low indicates that the
corresponding peripheral is writing to memory during a DCH
cycle (IN). When the DCHMOn signal is high, It indicates that
the peripheral is reading from memory (OUT).
25
Second Byte
An active·low ope~tor output signal to the memory
controller. During STRBD timing, this Signal is high during the
first byte of a byte·mode DCH cycle and low during the
second byte of a byte·mode cycle and during every word in a
word·mode DCH cycle. It can be used to strobe either the left
or right half of the memory array during a STRBD operation.
11
InputlOutput
Enable
An active·high input signal from the F9447 or F9448.1t is used
to enable the F9449 when the F9445 wishes to read from or
write to a WC or MA register during an I/O cycle. When the
signal is high, a programmed 110 operation is in progress.
I
A set of four active·low output signals to the requesting
peripherals and to the F9447 or F9448. When low, it informs
the appropriate peripheral that its requested DCH cycle is in
. progress. The DCHACK signal is used.by the peripheral to
clear the REO n line. It is also used by the F9447 or F9448 and
by the peripheral to enable data buffers to and from the lB.
BYTE Status
SB
Register Control
Signals
10EN
6·72.
F9449
Table 2
F9449 Signal Descriptions (Cont.)
Mnemonic
Pin No.
Description
Name
MAREN
10
Memory Address
Register Enable
An active·hlgh Input signal from the F9447 or F9448. It Is used
to select the source/destination register for an F9445
programmed 110 operation. A high signal selects an MA
register; a low signal selects a WC register.
Si'R
9
Strobe
An input signal from the F9447 or F9448. The low-to-high
transition causes the F9449 to load the IB data into the
selected WC or MA register during an 110 write operation.
37
Internal Direction
DCH Direction
Control
DIRINT
Input line that is used to establish the control sour~ of the W
line. When OIRINT is high during a DCH cycle, the W line is
controlled internally by lBo, the most significant bit of tt!..e
data word in the WC register. When DIRINT is low, the W line
. is controlled externally by the OCHMOn input from the
corresponding requesting peripheral.
It may be driven low by selected DCHACKn outputs if some
channels need internal control and others external control:
Power
Vee
64
Power Supply
Supply voltage ( + 5 Vdc).
IINJ
32
Injection Current
A constant 250 mA current supply; may be derived by use of
an external resistor to Vee' (Nominal V1NJ = 1.2 V.)
GND
16, 48
Ground
Common power and signal return.
6-73
•
F9449
Table 3
DC Characteristics
Symbol
Characteristic
VINJ
Injector Voltage.
VIH
Input High Voltage.
Vil
Input Low Voltage.
Veo
Input Clamp Diode Voltage.
VOH
Output High Voltage.
VOL
Output Low Voltage.
IIH
Input High Current
All Inputs.
III
Input Low Current.
10ZH
Output Off (High-Impedance)
State High Current 180-1815, W.
10Zl
Output Off (High-Impedance)
State Low Current 180-1815, W.
10SH
Output Short Circuit Current.
IlOH
OHH
Output Leakage Current (Open
Collector) RDYA, S8, DCHREQ.
lee
Supply Current.
Min
Typ
Max
Unit
1.3
IINJ
V
Guaranteed Input High Voltage
0.8
V
Guaranteed Input Low Voltage
-1.5
V
= Min, liN = -18 rnA, hNJ = Min
Vee = Min, 10H = -400 p.A,
IINJ = Min
Min
Vee = Min, 10l = 8.0 mA, hNJ
Vee = Max, VIN = 5.5 V,
IINJ = 300 mA
Vee = Max, VIN = 0.4 V, IINJ = Min
Vee = Max, Your = 2.4 V,
hNJ = Min
Vee = Max, Your = 0.4 V
hNJ = Min
Vee = Max, Your = 0.0 V, IINJ = Min'
Vee = Min, VOH = 5.25 V,
IINJ = Min
Vee = Max, IINJ = Min
2.0
-0.9
2.4
3.2
0.2
-0.21
-210
-15
Test Conditions
= Max
V
V
0.5
V
1.0
mA
-0.4
mA
100
p.A
-500
p.A
-100
1.0
125
mA
mA
mA
Vee
;:
*N.ot more than one output to be shorted at a time.
Absolute Maximum Ratings
Recommended Operating Ranges
These are stress ratings only, and functional operation
at these ratings, or under any conditions above those
indicated in this data sheet, is not implied. Exposure to
the absolute maximum rating conditions for extended
periods of time may affect device reliability, and
exposure to stresses greater than those listed may
cause permanent damage to the device.
Storage Temperature
- 65°C, + 150.o C
- 55°C, + 125°C
Ambient Temperature Under 8ias
Vee Pin Potential to Ground Pin
- 0.5 V, + 6.0 V
- 0.5 V, + 5.5 V
Input Voltage (dc)
Input Current (dc)
- 20 mA, + 5 mA
Output Voltage (Output HIGH)
- 0.5 V, + 5.5 V
+ 20 mA
Output Current (dc) (Output LOW)
Injector Current (IINJ)
+ 500 mA
Injector Voltage (VINJ)
- 0.5 V, + 2.0 V
Part Number
Supply Voltage (Vcc)
F9449DC
F9449DM
Min
Typ
Max
4.75 V
4.5 V
5.0 V
5.0 V
5.25 V
5.5 V
Injector Current (hNJ)
Part Number
F9449DC
F9449DM
Min
Typ
Max
200 mA
200 mA
250 rnA
250 rnA
300 mA
300 mA
Ordering Information
6-74
Order Code
Temperature Range
F9449DC
F9449DM
O°C to
- 55°C to
+ 75°C
+ 125°C
F9450
Single-Chip Microprocessor
Advance Product Information
Microprocessor Product
Description
•
The Fairchild F9450 is a 16-bit single-chip bipolar VLSI.
microprocessor with on-chip hardware floating-point
capability. The 64-pin F9450 CPU provides 16 registers to
fully implement all standard instructions, including
interrupts, single and double precision arithmetic, and
32- and 48-bit floating pOint. The F9450 implements the
entire MIL-STD-1750A instruction set.
•
•
•
•
•
The microprocessor will directly address 64K words of
memory, and with the addition of the F9451 memory
management will handle one million words.
•
•
•
•
•
• Single 64-Pin Microprocessor Implements MIL-STD
1750A Instruction Set Architecture
• Single and. Double Precision Arithmetic (16 and 32
bits), with 16 general-purpose registers
• 32- and 46-8It Floating Point Arithmetic Implemented
On-Chip
Real-Time Processing with 16 Levels of Interrupt
Vectors, DMA, 128 1/0 Channels, and Two
Programmable Timers
Directly Addresses 64K Words; Extendable to 1 M
Words with MMU
Extensive Fault Detection and Debugging Capability
with Microcoded Console Support and Self Test
Provides for Multiprocessor Implementation
13 L@ Technology
Operating Temperature Range of from - SSOC to
+ 12SoC
64-Pin DIP or Optional Leaded Chip Carrier
Low Power Schottky 1/0
Single + S V Supply
Power Dissipation Approximately 2_S W
Radiation-Tolerant Technology
Figure 1 illustrates the CPU logic, and figure 2 shows
the configuration of the CPU with the memory
management unit (MMU) and the block protect RAM
..
~P~
~
Signal Functions
RESET
EXT REQUEST
CPU elK
TIMER elK
ADDRESS/DATA 16
ADDRESS STROBE
READY ADDRESS
.
MEMORY PROTECT ERR
DATA STROSE
~
MEMORY PARITY ERR
PIO CHNL PARITY ERR
READY DATA
DIRECTION
EXT ADDR ERR
tNST/DATA
F94S0
(1750A CPU)
PIO CHNL XMSN ERR
FAULT BIT 7
ASfPS 4
NML PWR UP
DMA REQUEST
STATUS
I BUS
MAJOR ERR
DMA ACKNOWLEDGE
DMA ENABLE
UNRECOVERABLE ERA
PWR DOWN
BUS REQUEST
USER 6
IOL 2
SYNC
BUS BUSY
SYSTEM FAULT
INTERRUPTS {
MEMORY/1Q
BUS
MEMORY 10
DMA CHNL PARITY ERR
BUS LOCK
BUS GRANT
~
• I'L is a registered trademark of Fairchild Camera and Instrument
Corp.
6-75
}
MULTI
PROCESSOR
INTERFACE
F9450
Figure 1
CPU Logic Diagram
:~~CESSOR ________________________-7~II____~________________-,~______~______________- - - - - - - - - - - -________--:ngCESSOR
~J:RNAL-----r--------1_----------~~II~------------_1~--c_--L-------_r----------------__r_------__.-~---INTERNALBUS
18
AADDR
REG. FILE
SHIVrIlREO
TEM~REO
B ADDR,.£!-.
(4)
18
18
18 18
18
18
8
8
18
18
18
18
BBUS __~2--i--~--~~~----+-----~----~~L---~--~------t--------------t__---------i-----------------------BBUS
A8US~~182-~------~~------L-----------~~--~~----------~------~~---L----------~---------------------ABUS
Figure 2
CPU Systems
RESET
EXT REQUEST
CPU CLK
TIMER CLK
ADDRESS/DATA
EXT ADDR (EXT 0 7) I EXT ADDRESS (8PO BP7) I
/18
ADDRESS STROBE
READY ADDRESS
EXTERNAL
FAULTS
MEMORY PROTECT ERR
DMASTROBE
MEMORY PARITY ERR
READY DATA
•
DMA CHNL PARITY ERR
OIRECTION
r-'-~EXT ADOR ERR
..
PIO CHNL XMSN ERR
DATA STROBE
MEf!I.ORY/l0
SYNC··
INST DATA
SYSTEM FAULT
DMAREQUEST
AS/PS
PWR
MEMORY PROTECT ERR
BUS BUSY
DMA ACKNOWLEDQE
4
UP
MAJOR ERR
UNRECOVERABLE ERR
BUS REQUEST
{PWRDOWN
BPR
DIREcnON
NML
II
MM.U
INST/DATA
BUS BUSY ,
USER
IDL
RES(RO R2)
ADDRESS/DATA
AO.DRESS STROBE'
MEM9RY/1O
FAULT BIT7
DMA { DMA ACKNOWLEDGE
CONTROL DMA ENABLE
INTERRUPTS
CPU
READY EXT ADDRESS
8
BUS LOCK
2
BUS GRANT
}
MULTI
PROCESSOR
INTERFACE
6-76
MEJORY
PROTECT
ERR
GLOBAL
MEMORY
PROTECT
ENABLE
F9451
Memory Management Unit
Microprocessor Product
Advance Product Information
Description
The Fairchild F9451 Memory Management Unit (MMU)
provides the logical-te-physical address translation for
instructions and operands in the MIL-STD 1750A
configuration. The MMU serves to expand to one million
words the direct addressing of the F9450 CPU,
and provides protection in logical space units of 4K-word
pages for access key, write, and execute instructions.
Figure 1 illustrates the addressing structure, and figure 2
shows a block diagram of the MMU.
•
•
•
•
•
•
•
•
Logical-to-Physical Address Translation for
Instructions and Operands
One Million Word Addressing Space
Protection in 4K-Word Pages for Access Key, Write,
and Execute
Instruction and Operand Maps
13 L@ Technology
Operating Temperature Range of from - SsoC to
+ 12SoC
Radiation-Tolerant Technology
64-Pin DIP or Optional Leaded Chip Carrier
Figure 1
II
Addressing Structure
ACCESS FAULT
PROTECT
LOGIC
MEMORY
PROTECT ERR
PROCESSOR
STATE (PS) 4
+-....~ "
::..IN;;:;ST'-'/.:;;DA::..T'-'A_ _
""
~} .~..
STATUS BUS
(AS/PS)
6-77
F9451
Figure 2
F9451 MMU Block Diagram
I/D
AD/DATA
MAP
512 x 16
LATCH
16
STRBA-J
,I
AD4·AD15
RDYA
STRBD_'
,
RDYD.......J
I
I
I
I
EXT O·
EXT 7
AS/PS
RDYA
6·78
F9452
Block Protect RAM
Microprocessor Product
Advance Product Information
Description
The Fairchild F9452 Block Protect RAM (BPR) unit
provides write protection in physical memory for the CPU
and DMA in blocks of 1K words. The BPR also provides
global write protection from initialization until enabled.
Figure 1 is a block diagram of the BPR.
•
•
•
•
13 L® Technology
Operating Temperature Range From - 55°C to + 125°C
Radiation·Tolerant Technology
64·Pin DIP, or Optional Leaded Chip Carrier
Figure 1
F9452 Block Diagram
r----------------~
I
EXT O·EXT
I
7~L-......
8
I
ADIDAT A-,,'"+-~r--~
16
I
STRBA--I
I
STRBD_1
I
DIRECTION_I
I
M/IO-!
I
IID-!
I
BUS BUSY-!
I
RESET-I
I
I
I
I
~----------------~
®
PL is a registered trademark of Fairchild Camera and Instrument
Corp.
6·79
DMACK
II
F9452
6-80
F9470
Communication and
Console Controller
Advance Product Information
Microprocessor Product
Description
information from the F9445, and then outputs it to the
operator's terminal.
The Fairchild F9470 Communication and Console
Controller is an LSI MOS device that provides the
Fairchild F9445 16·bit 13 L® microprocessor with virtual
console control functions via a pair of asynchronous
communication ports.
In the 1/0 service mode, the F9470 acts as a serial 1/0
controller, interfacing the serial 1/0 devices to the F9445
through device codes 10·13 and 77. The console
commands are not available while in the 1/0 service
mode: all 1/0 in this mode must be programmed through
the F9445.
The F9470 provides a variety of useful console functions,
including examine and deposit to memory and
accumulators, jump to a specified location, and trace the
F9445 instruction execution.
• Accesses Microprocessor Internal Registers
• Two Asynchronous Serial Ports
• Allows VDU to Operate as a Console for an F9445
System
• 40·Pin DIP Requiring Single + 5 V Power Supply
• NMOS Technology.
The F9470 operates in two modes: console control and
1/0 service. In the console mode, all communication with
the F9445 is controlled by the F9470, which interprets
the seven console commands, requests the appropriate
------.
Figure 1 illustrates the pin configuration of the console
controller.
Connection Diagram
Signal Functions
x,
(LSB)
CRYSTAL,I
CLOCK
l
x,
00
0,
CPU{
CYCLE
TYPES
M
INFORMATION
BUS
INTPIN
RESET
ASYNCHRONOUS{
SERIAL
PORTS 1 AND 2
RX0 2
INTREQ
CONREQ
BUSGNT
ROVO
RDYACK
EXREQ
NC
NC
NC
ROYO
NC
@
I'L is a registered trademark of Fairchild Camera and Instrument
Corp.
6·81
(MSB)
F9470
Figure 1 Pin Configuration of the Console Controller
+5
M-------------------------,
0,---------------------------,
+ 12--------.....,
~--------------------,
~~--~--~---------------------,
6
-12
RS232
3
4
INTA
ENABLE
5
~18~------_+~I.>O-~-TXD,
~19~------_+~l.>o-~-TXD2
R5232
~16~------~1~~<9~l_~RXD,
~17:..-------_+_><]-+
RXD2
14
13
10
12
11
11
12
10
13
14
9
+5
INTREQ
15
F9470
CONREQ
is
33
M
BUSGNT
0,
00
RDYD
+5
IB12
Do
IB10
1811
iB1
STRBA-l>>---+
D
Q
D
QI------I-'
Ii
I~----------~======================l:~~------if.~~~~
CLK CD Q~
LS74
0,
+5
CP,-------4------~--~
IK
6-82
F9470
The three jumpers in figure 1 perform the following functions.
Jumper
Name
Description
J1
INTA ENABLE
Jumpered low, the F9470 is the highest proirity 1/0 device, or the only 1/0 device in the
system. Removing the jumper and driving INTPIN provides a daisy-chain priority-interrupt
scheme. A high level on this pin allows interrupts from the 1/0 terminal to be disabled when
a device with a higher priority interrupts the CPU.
J2
OS77 ENABLE
With this jumper in place, the F9470 responds to device code 77 (octal) programmed 1/0
instructions. Removing the jumper allows faster interrupt response to a system device that
interrupts the CPU at a higher frequency. Notice that MSKO, INTA, and 10RST are no longer
available with the jumper removed.
J3
F94701/0
SERVICE
ENABLE
Connect the jumper to ground to use the 1/0 service mode. The F9470 decodes and executes
1/0 instructions for a processor in order to control the serial output. The F9470 responds to
device codes 10, 11, 12, 13, and 77 (teletype in and out, paper tape reader and punch, CPU),
and stalls the CPU to get time to decode and respond to the instructions using these device
codes.
II
------------~---.
Console Mode Operation
1.
Force an overflow. The F9470 buffer accepts six
octal numbers, so only the last six entries will be
used. For example, 77777777 is interpreted to be
177777. Only the least significant bit of the most
significant number is read.
2.
CTRL-H. This backs up over each mis-typed number
and echoes each entry, so the number of character
deletions is apparent.
3.
Pressing the backspace key is identical to pressing
CTRL-H.
4.
Pressing any key other than 0 through 7, or any
accepted command letter, returns to the console
mode.
5.
After executing the examine command, xxxE,
pressing any key other than 0 through 7 &~CR), or 1\
returns to the console mode.
The procedure used to communicate with the F9470 in
the console mode is as follows:
Entering Data and Commands
The console prompt is an asterisk('), which indicates the
F9470 will accept commands. The commands are
executed by typing the desired capital letter or, where
appropriate, the octal number(s) and letter. No carriage
return (CR) is necessary. Once within the examine (E)
mode, some keystroke is used to complete each
individual entry. The strokes are (CR) and 1\. Each closes
the present entry, and then respectively goes to the next
or previous address location. To write a program with the
E command, enter the octal values equivalent to the
F9445 binary instruction codes. (See the F9445 data
sheet for a description of the instruction set.)
Recovering from Keystroke Error
Return to Console Mode from 110 Service
If an error is made by typing the wrong letter command,
there is no recovery, since execution begins immediately.
There are many ways to correct data errors.
(Characteristics vary among terminals; the following text
refers to what occurs when using the Zenith terminal.)
BREAK (or CTRL-BREAK) enters the console mode from
the 1/0 service mode. The F9445 will continue execution
of any currently running code. (BREAK and CTRL-BREAK
are keystrokes. Some terminals require that the key
labeled CONTROL be held while the BREAK key is
struck.)
6·83
F9470
The seven console commands processed by the F9470 are given in table 1.
Table 1
F9470 Console Mode Commands
Command
Description
A
Displays seven fields, the present octal contents of the PC, ACO, AC1, AC2, AC3, SP, and FP registers. PC
contains the next Instruction to be executed.
n,vC
Changes any of six registers to the new octal value, v. To select which register, choose the octa.1 code
associated with that register.
Octal code (n):
Register:
o
ACO
1
AC1
2
AC2
3
AC3
4
SP
5
FP
If v is omitted, the chosen register is set to O. Comma is the only proper delimiter to use.
xE
Examines the contents of the memory cell at address x. The address and its present octal contents are
displayed on the terminal. New octal contents may then be typed. A carriage return enters the new value and
closes the cell. The next address (x + 1) and its contents are then displayed, and its new value can be typed.
Entry continues in sequential locations until the ESC key is pressed and terminates the examining session.
Pressing multiple carriage returns effectively displays the contents of consecutive cells. If A (circumflex) is
pressed instead of (CR), an open cell is closed, new data (if any) is entered, and the previous address cell is
opened.
xJ
Jumps to location x and begins executing the program located there inF9445 absolute assembly language.
Transfers from console mode to service I/O mode.
xR
Jumps to location x and begins program execution. This is. identical to the jump (J) command, except the
F9470 remains in the console mode. The console responds to keystrokes, such as A, T, or more R
commands. When the R command is used, the F9470 does not respond to I/O instructions from the F9445,
and program execution halts when .another console command (e.g., A) is entered. Back-to-back R commands
are not recommended.
S
Allows the user to reset the baud rate. Issue this command, attach the CRT cable to another device or re-set
the baud rate of the terminal In use, then press (CR). The software of the F9470 sets the board baud rate to
agree with the rate of the attached device. A second rate can then be software-programmed, in accord with
the restrictions noted in figure 2.
.
.
nT
Traces through the user program n (octal) steps, beginning at the address pointed to by. the PC counter or
where the previous trace left off, whichever was last. If n = 0 or 177777, it will trace forever; if n is omitted,
it traces one step. To start tracing at location x, set the PC counter to x with the command xE, then press
the ESC key to terminate the examine mode; finally, use the appropriate T command to begin traCing. For
every program step that is traced, the command T displays eight fields: the memory address, the instruction
in octal form, the four accumulators, the stack pointer, and the frame. pOinter.
6-84
F9470
I/O Service Mode Operation
The F9470 responds to the interrupt control instructions
listed in table 3 when in the 1/0 service mode.
When performing 1/0 functions with the F9470, the
following restrictions should be noted.
1.
The busy flag is not set with input device codes 10
and 12, therefore, SKPBZ and SKPBN should not be
used with these codes.
2.
The F9470 requires some time after clearing the
done flag to remove the associated interrupt
request. When performing interrupt-driven 1/0 to the
F9470, the operator needs to add a delay between
the clear request and the next INTEN. Alternatively,
the interrupt handler must be able to tolerate a
bogus interrupt from the F9470. In this latter case
an INTA command will return a zero (0), which the'
interrupt handler should ignore, and then re-enable
interrupts.
Table 3
F9470 Interrupt Control Commands
Instruction
Description
10RST
Clears all busy and done flags,
disables interrupts.
MSKO,ACC,CPU
Enables or disables device
interrupts by clearing or setting the
interrupt disable flag in the device.
The interrupt disable flag of each
device is associated with a
specific data line, and is set if its
mask bit is 1, cleared if 0'.
INTA,ACC,CPU
Reads device code of highest
priority device that is requesting
an interrupt. The 6-bit code is
loaded into ACC bits 10-15. All 16
bits are set to 0 of no device is
interrupting.
When in the 1/0 service mode, the F9470 responds to the
F9445 data control instructions presented in table 2.
These commands are a subset of the F9445 mnemonic
instructions described in the F9445 data sheet.
Table 2
F9470 I/O Service Instructions
'NOTE:
Instruction
Description
DIAx ACC,DEY
DOAx ACC,DEY
NIOx DEY
Data In from A
Data Out from A
No 1/0; Used to Start or
Clear a Device
Skip if Busy = 1
Skip if Busy = 0
Skip if Done = 1
Skip if Done = 0
SKPBN DEY'
SKPBZ DEY'
SKPDN DEY
SKPDZ DEY
fnterrupt Disable Bits
IB Bits
NOTES:
If x = S (start), set busy flag, clear done.
If x = C (clear), clear busy flag, set done
ACC
Accumulator 0,1,2, or 3.
DEV = Device Codes = 10,11,12,13
• Note that Busy is not defined for input devices (lT1 and PTR); hence,
SKPBN and SKPBZ should not be used with these devices.
=
6-85
13
14
15
Mnemonics
PTR
PTP
TTl
TTO
Function
CH2
In
CH2
Out
CHI
In
CHI
Out
S
9
10
11
12
•
F9470
The F9470 responds to device codes 10, 11, 12, 13, and
77, which are octal codes of the six least significant
instruction bits:
Device Code
Mnemonic
Description
Action
10
11
12
13
77
TTl
TTO
PTR
PTP
CPU
Teletype In
Teletype Out
Paper Tape Reader
Paper Tape Punch
CPU
Input on Channel 1
Output on Channel 1
Input on Channel 2
Output on Channel 2
Figure 2
Serial I/O
The F9470 has two asynchronous serial input/output
ports. Each port can select 110, 300, 1200, 1800, 2400, or
4800 baud. The initial carriage return after power·up or
after typing the S command allows the software to
define the first baud rate. The second rate is
programmed according to the mnemonic keystroke next
entered (see figure 2 for valid rates). The second baud
rate must be less than or equal to the rate of the first
one.
Serial I/O Port Baud Rate Selections
MNEMONIC
02
2
Q)
c
BAUD RATE
FOR PORT 2
0
z
300
1200
1800
2400
4800
1.
2.
6·86
Valid 2nd baud rate
Automatically
0 signifies no second line
*1
0
0
'"
*1
110
FIRST
BAUD
RATE
0
3
0
0
N
4
5
0
0
0
0
1, <1>2 Pins Only
VeL
VOH
Logical 0 Output Voltage
-O.S
0.3
V
<1>1,<1>2 Pins Only
Logical 1 Output Voltage
2.4
V
lOUT = - 400 pA
VOL
Logical 0 Output Voltage
O.4S
V
IlLS
AT/SPC Input Current (low)
1.0
mA
10L =2 mA
VIN =0.4V, AT/SPC in
Input Mode
IlL
Input Leakage Current
-1.0
1.0
p.A
VIN ;5;V OO ' All Inputs Except
<1>1,<1>2, AT/SPC
10L
Output Leakage Current
-1.0
1.0
pA
OsVINsV OO
100
Active Supply Current
300
mA
10UT=0, TA =O·C
Symbol
Parameter
Min
VIH
VIL
Logical 1 Input Voltage
Logical 0 Input Voltage
VCH
Typ
Absolute Maximum Ratings
The absolute maximum ratings for the CPU are
presented in table 3. These are stress ratings only, and
functional operation at these ratings or under any
conditions above those indicated in this data sheet is
not implied. Exposure to the absolute maximum rating
conditions for extended periods of time may affect
device reliability, and exposure to stresses greater than
those listed may cause permanent damage to the device.
Table 3
Absolute Maximum Ratings
Temperature Under Bias
Storage Temperature
All Input or Output Voltages
with Respect to GND
Power Dissipation
O·C, + 70·C
-6S·C, +1S0·C
-O.SV, +7.0V
1.SW
7·11
Test Conditions
•
F16032
7-12
F16081
Floating Point Unit
Advance Product Information
Microprocessor Product
Description
Connection Diagram
The F16081 Floating Point Unit (FPU) is a slave
processor intended to augment the instruction set of the
F16000 microprocessor family. The FPU implements a
version the IEEE standard P754 floating point
specification.
VDD
0'0
D.
D.
0,
•
•
•
•
•
•
High-Speed Operation
Single (32-Bit) and Double (64-Blt) Precision
Selectable Rounding Modes
Error Detection and Interrupt Generation
NMOS Technology
24-Pln Dual-In-Line Package (DIP)
• + 5 V Power Supply
D.
0"
0,
0"
D.
013
0,
0,.
0,.
0,
Do
GNDL
•
Signal Functions
CTIL SINGLE·
PHASE CLOCK
INPUT
AD 15
AD14
AD,.
RESET
AD12
AD11
~~:TUS
SIGNALS
I - ST,
AD 10
AD.
AD.
AD,
AD.
AD,
AD.
AD.
AD,
AD,
ADo
- - STo
SPC/AT
VDD
t
+5V
7-13
GNDL GNDB
OV
OV
MULTIPLEXED
ADDRESS/DATA BUS
SLAVE PROCESSOR
CONTROL
F16081
Instruction Summary
the instructions for the F16081 are summarized in
table 1.
Table 1
F16081 Instruction Summary
Mnemonic
Description
ABSf
ADDf
CMPf
DIVf
FLOORfi
LFSR
MOVf
MOVFL
MOVif
MOVLF
NEGf
ROUNDfi
SFSR
SUBf
TRUNCfi
Absolute Value Floating Point
Add Floating Point
Compare Floating Point
Divide Floating Point
Floor Function
Load Floating Point Status Register
Move Floating Point
Move and Convert
Move and Convert
Move and Convert
Negate Floating Point
Round Function
Store Floating Point Status Register
Subtract Floating Point
Truncate Function
7·14
F16082
Memory Management Unit
Advance Product Information
Microprocessor Product
Description
Connection Diagram
The F16082 Memory Management Unit (MMU) provides
support for virtual memory management and program
debugging when used with the F16000 microprocessor
family. It is designed to relieve the microprocessor unit
of burdensome tasks associated with memory manage·
ment and provide address translation during program
execution. The MMU converts virtual addresses issued
by the MPU to physical addresses. Support is included
to assist the operating system in implementing memory
management policies. Memory protection is
implemented by slave instructions that check the validity
of a memory reference. The F16082 also permits easy
implementation of a virtual machine in a qebugging and
in·system emulation environment. The MMU slave
processor extends the memory management capabilities
of the F16000 microprocessor family. Slave processor
concepts allow potential software compatibility with
future systems because the slave hardware is
transparent to the software.
•
•
•
•
•
•
•
•
•
•
A"
Dynamic Address Translation Using Memory Page
Tables
On·Chip Cache for the 32 Most Recently Used
Memory Page Table Entries
Virtual Memory
Memory Protection
Program Breakpointing
Program Flow Tracing
Virtual Machine Support
High·Speed NMOS Fabrication
48·Pin Dual·ln·Line Package (DIP)
Single + 5 V Power Supply
A"
A"
A"
A"
A19
TNt
A18
PAV
A17
STo
A16
ST,
AD 15
ST,
AD14
ST,
A013
PFS
AD12
DDIN
AD11
ADS
AD10
U/S
'ADg
SPC/AT
AD,
ABT/RST
AP7
m
AD,
HLDAO
ADs
HLDAI
AD,
HQ[lj
AD,
rn
AD,
RDY
AD,
"2
ADo
"1
GNDL
7-15
Voo
GNDB
II
F16082
Signal Functions
CLOCKS
I
READY
Instruction Summary
...,
A,.
A"
A"
A20
A'9
AlB
A'1
A,.
AD,s
AD,4
RDY
HOLD
HLDAI
HLDAO
RESET
BUS CYCLE
STATUS
USERISUPERVISOR
STATUS LINE
ADDRESS
STROBE
SLAVE PROCESSOR
CONTROL
PROGRAM
FLOW STATUS
I
iID
ST.
ST,
ST,
ST.
AD'3
AD12
AD11
AD,.
AD.
AD.
AD1
AD.
ADs
AD.
AD.
AD,
AD,
AD.
U/!!
AIlS
SPC/A'f
m
DDIN
Ali'f/iID
Voo
t
+SV
GNDl GNDB
OV
The instruction commands for the F16082 are sum·
marized in table 1.
}
A'23
Table 1
'''''"''"
F16082 Instruction Summary
ADDRES BITS
MULTIPLEXED
ADDRESS AND
DATA BUS
Mnemonic
Description
LMR
RDVAL
SMR
WRVAL
Load MMU Register
Read Validate
Store MMU Register
Write Validate
Absolute Maximum Ratings
DATA DIRECTION
(BUS CONTROL)
ABORT/RESET
INT
INTERRUPT
FlT
FLOAT (BUS CONTROL)
PAY
PHYSICAL ADDRESS
VALID (Memory
Control)
These are stress ratings only, and functional operation
at these ratings or under any conditions above thdse
indicated in this data sheet is not implied. Exposure to
the absolute maximum rating conditions for extended
periods of time may affect device reliability, and
exposure to stresses greater than those listed may
cause permanent damage to the device.
Temperature Under Bias
Storage Temperature
All Input or Output with Respect
to GND
Power Dissipation
OV
7·16
O·C, + 70·C
- 65·C, +150·
- 0.5 V, + 7.0 V
1.5 W
F16105
Very Intelligent
Peripheral Controller
Microprocessor Product
Advance Product Information
Description
The F16105 Very Intelligent Peripheral Controller (VIPC)
is a general-purpose device to be used either with the
F16000 microprocessor family or as a stand-alone
system element The controller is easy to program in
both assembly language and high-level language_
•
•
•
•
•
•
•
•
•
•
•
•
Upward Software Compatibility with the F16032
Microprocessor
Internal10-MHz Clock Speed with Instruction
Prefetch
4096-Byte ROM
192-Byte Two-Port RAM
64-Byte Scratchpad RAM
32 Pins Individually Programmable as 110
Asynchronous Communication Interface Port
Cascadable 16-Bit Timer and Event Counters
Eight Vectored Interrupts
Input/Output Processor (lOP) or Single-Chip
Configurations
Remote or Local Bus Configurations
External Memory Access of 56K Bytes
FI
7-17
F16105
7-18
F16201
Timing Control Unit
Advance Product Information
Microprocessor Product
Description
Connection Diagram
The Fairchild F16201 Timing Control Unit (TCU) is a
24-pin Schottky component used with the Fairchild
F16000 microprocessor family. It has four basic
functions:
1.
Provides twononoverlapping clock phases for
unbuffered use within the F16000 microprocessor
family and provides a synchronous TTL output.
2.
Provides the basic system read, write, and databuffer-enable control signals.
3.
Generates slow cycles compatible with the
requirements of the older peripherals (those for
which adding wait states is not sufficient).
4.
VDD
m
RWEN
AD
CWAIT
WR
WAITI
ODIN
WAIT2
CTTL
ROY
FCLK
XCTL2
XCTLI/ECLK
GND
Synchronizes the ready and reset inputs for the
MPU.
• Two Full-Voo Swing Clock Outputs
TTL Drive Capability on All Outputs Except Clock
• On-Chip
Generator for F16000 Systems
• Bus Control
Signals for F16000 Systems
•• Support for Slow
8080 Peripherals
Four
Wait
Inputs
(WAm
to Force up to 15 Wait
• States
Wait Input (CWAln to Generate an
• Continuous
Unlimited Number of Wait States
Signal Functions
CRYSTAL
INPUT OR
EXT SOURCE
Additional CWAIT Timing to Allow a Memory Cycle
Hold and Subsequent Regeneration for System
Arbitration or Memory Refresh
• Schmitt Trigger Reset Input, Internally Synchronized
to Generate a Reset Output for the F16000 System
Fast-Clock TTL Output with Twice the System Clock
Frequency
Frequency Range of From 0_2 MHz to 10_0 MHz
• Single + 5 V Power Supply
1-
•
XCTLI/BCLK
+1
XCTL2
+2
tWAIT
FCLK
WAITI
CTTL
WAIT2
ROY
WAff4
WAITS
RESET
•
•
CONTROL
SIGNALS
7-19
1
j-
AD
WR
IISfi
DBE
I
I
TWO·PHAse
CLOCK OUTPUT
PERIPHERAL
CLOCKS
READY
l
BUS
CONTROL
RSfO
fSO
ODIN
PER
RWEN
AD!i
VDD
GND
I
PERIPHERAL
3·STATE
CONTROL
POWER
•
F16201
wait count, CWAIT may also be taken to low, overriding
the count and forcing a continuous walt to be entered.
Functional Description
The'F16201 has five major elements (see figure 1): the
oscillator and dl'vide·by·2 circuit, the two·phase
generator, the reset synchronization circuit, the wait·
state generator, anti the timing state counter and control
signal generator (TSCCSG).
The walt·state generator counts the number of wait ,
states to begenerated~ A start pulse (generated by the
TSCCSG circuit) is used to Initiate the counting. While
the counter Is operating or the CWAIT Input is low, the
wait·state generator holds its wait output to the TSCCSG
circuit active. The wait·state generator turns Its ready
output (ROY) to low when a start pulse is received from
the TSCCSG. The ROY output returns to high when the
wait signal is released.
The oscillator and dlvlde·by·2 circuit Is connected to
either an external crystal operating at twice the desired
clock frequency or an external source by way of the
XCTL1/ECLKpin. ThIs circuit also generates the fast TTL
clock (FCLK) with the crystal or ECLK frequency. A one·
half·frequency output Is created for ,the two·phase
generator.
'
,
The timing state counter and control signal generator
circuit keeps track of the timing state (T·state) within the
MPU, 'generating the control.~ls accordingly. The
arrival of the address strobe (ADS) Identifies the first
T·state (T1) of a timing cycle. Input signals Di5iiii and
PER are latched, and fast or slow, read or write cycles
are generated. The TSCCSG circuit also extends a cycle,
as directed by the wait line. The T·state output (TSO)
signal identifies the beginning of,the second and last
T·states of a timing . cycle; 'it can be used to gate or clock
external logic for synchronization ..
The two·phase generator provides two full·V oo swing,
nonoverlapplng clock signals. Additionally, it generates a
TTL clock (CTTL) and an Intemal,clock to synchronize
the other circuits of the chip.
The reset synchronization circuit synchronizes the reset·
In Input (RSTI) to generate reset·out (RSTO) with proper
timing. The FmTI has a Schmitt trigger Input.
Wait timing allows two different modes of operation,
providing ftexibillty in the generation of the walt Inputs.
When theCWAIT or WAIT Inputs are active, 'wait states
are inserted. However, If CWAIT Is used to create the
walt, the WAIT Inputs can be applied and are
implemented following CWAIT's release. During a fixed
Figure 1
Recommended Operating Conditions
The recommended operating ranges of the TCU are
shown below,
'
Supply Voltage Vee
Temperature TA
F16201 Block Diagram
CWAlT
WAlT,'
, WAif.
WAlT.
WAlT.
WAIT
WAIT·
STATE
GENERATOR
START
TIMING
STATE
COUNTER
AND
CONTROL
SIGNAL
GENERATOR
(TSCCSG)
RDY
XCTL1'
ECLK
XCTL2
"7·20
4.75 Min., 5.25-Max V
0·C,70·C
F16202
Interrupt Control Unit
Advance Product Information
Microprocessor Product
Description
Connection Diagram
The F16202 Interrupt Control Unit (ICU) provides the
F16000 microprocessor family with hardware support for
prioritized, vectored interrupts and for a real-time clock.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
IR
IR,
16 Interrupt Sources, Cascadable to 256
8 Hardware Interrupt Sources In 16-Bit Data Bus
Mode
Up to 16 Hardware Interrupt Sources In 8-Blt Data
Bus Mode
Optional 8-Blt Input/Output (I/O) Port when the 8-Blt
Bus Mode Is Used
Five Optional Clock Outputs In the 8-Bit Bus Mode
Two 16-Bit, dc-to-10 MHz Counters that Can Be
Combined Into a Single 32-Bit Counter
Thirty-two 8-Blt Internal Registers Accessible as Pairs
in the 16-Bit Bus Mode
Software Interrupts
Automatic Handling of Return from Interrupts
Programmable Polarities and Level/Edge Selection
for Each of the Hardware Interrupts
Automatic Rotating Priority Mode
NMOS Technology
40-Pln Dual In-Line Package (DIP)
Single + 5 V Power Supply
Signal Functions
INTERRUPT
(10 MPU)
CLOCK INPUT
RESET
BUS CYCLE
STATUS LINE
(from MPU)
BUS CONTROL
SIGNALS
D15P7
DI4P.
D13PS
DI2P_
}
DllP,
Dl0P2 . . . .
D09P,
D08P.
I
07
D.
D,
D_
D,
D2
=}
CONFIGURATIONDEPENDENT SIGNALS
DATA BUS/I/O PORT/
f~p~j~NAL INTERRUPT
BIDIRECTIONAL
DATA BUS
D,
D.
COUT
EXTERNAL CLOCK
IN/OUT
GND
+5 V
VDD
t
0V
-. 7-21
ST
IR2
D15P7
IR,
D14P6
IR_
D13P5
IR,
D12P4
IR.
Dl1P3
IR7
Dl0P2
CLK
D9Pl
WR
D8PO
iii)
D7
COUT
D8
i'IR
D5
RST
D4
A_
D3
A,
D2
A2
Dl
A,
DO
Ao
GND
CS
•
F16202
7·22
F16203
Channel Controller
Advance Product Information
Microprocessor Product
Description
Connection Diagram
The F16203 Channel Controller is intended for use with
the F16000 microprocessor family. It is a four·channel
controller that can operate on a processor local
multiplexed bus (via local mode selection) to support
low-cost configurations. It can aLso operate with
separate user-defined input/output (I/O) buses (via
remote mode selection) when high performance is
required.
•
•
•
•
•
•
•
•
•
•
•
•
•
VDD
AD.
AD,
AD.
AD.
AD.
Up to Four Independent Channels
Interfaces with the F16032 Central Processing Unit
Integrated Operation with the F16202 Interrupt
Control Unit
Local/Remote (Slngle-/Multlbus) Configurations
Versatile Channel Commands
Command Chaining
Support for Memory-to-Memory and Device-to-Device
Transfers
8- and 16-Bit Devices
NMOS Technology
48-Pln Dual In-Line Package (DIP)
Single + 5 V Power Supply
Maximum Data Rate of 5M Bytes Per Second
Selectable Cycle SteallBurst/Semiburst Transfers
ADs
AD.
AD7
DSTB
AD.
1m'
AD.
jjij'f
AD,.
RDY
HlDAO
HO:iJil
HOLD
IJOIN
AIlI
.cs
iOS
11ft
A20
GND
7-23
elK
F16203
Signal Functions
CLOCK INPUT
Channel Command Summary
m
READY INPUT
HOLD
CONTROL
DMA REQUEST
FROM DEVICES
3·0
A21
A,o
A,.
A,.
Au
A,.
ROY
I
!
-
The basic channel commands for the F16203 are
DISABLE
VERIFY
SEARCH
TRANSFER AND SEARCH
Various command modifiers are append able to the basic
command and are summarized in table 1.
A"
A"
CLK
HLDAI
HLDAO
MOST SIGNIFICANT
ADDRESS BITS
AD 15
AD14
R3
112
111
AD13
Table 1
AD12
AD.
AD.
AD7
AD.
AD,
AD,
AD,
AD,
AD,
ADo
MULTIPLEXED
ADDRESS AND
DATA BUS
HBE
ADS
ODIN
MPU BUS
CONTROL
SIGNALS
DSTB
DATA STROBE TO DEVICES
(Remote Mode Only)
ACK,
ACK,
ACK 1
ACK o
CHIP SELECT
I/O SELECT
cs
lOS
F16203 Command Modifiers
AD11
AD10
Ao
V DD
t
+5V
DMA ACKNOWLEDGE TO
DEVICES 3·0
WAfT
iNT
WAIT REQUEST TO F16201
(Remote Mode Only)
INTERRUPT REQUEST
AOIli
HOLD REQUEST TO MPU
GND
t
OV
7-24
Mnemonic
Description
AS
AT
BT
D
DL
DT
DW
LP
MN
MNI
PT
RQI
SE
SL
ST
STI
SW
TC
TCI
UW
Word Assembly
Auto Transfer
Burst Type
Direct/Indirect Mode
Destination Location
Destination Type
Destination Width
Lock Priority
Match/No Match
Match/No Match Interrupt Mask
Priority Type
Request-While-Disabled Interrupt Mask
Stop Enable
Source Location
Source Type
Stop Function Interrupt Mask
Source Width
Transfer Complete
Transfer Complete Interrupt Mask
Search Type
F16204
Bus Arbiter
Microprocessor Product
Advance Product Information
Description
The F16204 Bus Arbiter manages heterogeneous
multiprocessor systems that share a common bus.
•
•
•
•
Multiprocessor Environments
Up to 32 Masters
Selection of Arbitration Algorithm
Encoded Arbitration Scheme
•
7-25
16204
7·26
F16413
CRT Controller
Advance Product Information
Microprocessor Product
Description
Signal Functions
The Fairchild F16413 CRT Controller (CRTC) operates
within the F16000 microprocessor family for computer
terminal, word processor, and monitor applications. The
64·pin, 5 V controller uses N·channel silicon gate
technology. A number of features are programmable for
easy adaptation to different display, synchronization,
and screen formats.
cs
CUR,
LPICUR,
SCAN LINE {
COUNTER
RC,
RC,
RC,
RCo
A15
A14
An
A"
A"
A,o
•
•
Programmable Display and Synchronization Formats
Memory Addressing: Row/Column, DMA with Row
Buller, or Contiguous Linear Addressing
• Three Video Modes
• Three CRT Monitor Interfaces
• Programmable Window Location
• Programmable Status Field Location That Can Be
Used to Provide a Vertical Split Screen
• Character Clock Rate to 10 MHz
• Maskable Interrupts: Line Zero, Vertical Blank,
Smooth Scroll Complete, Programmable Row
Interrupt, End of Scan Line
• Two Cursor Flags
• Double Width, Double Height Attributes
• Smooth Scrolling Forward or Reverse with Scroll
Within Window or Its Inverse (Everything but the
Window)
• Proportional Spacing
• Single + 5 V Power Supply
MEMORY
ADDRESS
LINES
POWER {
The F16413 CRTC features programmable display format
for up to 256 characters per row, 128 rows per frame,
and 16 rasters per row. It has a programmable format for
horizontal and vertical sync pulse delay (front porch),
sync pulse width, and scan delay (back porch).
Signal Descriptions
Table 1 describes the CRTC signals.
7·27
Ag
As
A,
A.
A,
A,
A,
A,
A,
Ac
GND
Voo
CCLK
LLI
LINE LOCK INPUT
1m
WIi
I!ST
iIIll
0,
D.
0,
0,
0,
0,
0,
}
DATA BUS (110)
Do
PA,
PA,
PA,
PAc
PS
PBR
}
REGISTER ADDRESS
PROP. SPACING
PROCESSOR BUS REO.
BLANK
VSYNC
HYSNC
•
F16413
Table 1
CRTC Signal Descriptions
Mnemonic
Name
Description
Voo
Power
+ 5 V power supply.
GND
Ground
Commond ground.
Ao/RAo-A5/ RA5
Address Bus and
Register Address
Lower six bidirectional address bus and register address pins.
Aa-A15
Address Bus
Higher 10 address bus output..
0 0-0 7
Data Bus
Bidirectional data bus.
CS
Chip Select
Active low input to enable read/write of the internal registers during
peripheral access.
RO
Read Strobe
Input used to read data fr{)m the internal peripheral registers.
WR
Write Strobe
Input used to write data to the int'ernal peripheral registers_
RST
Reset
An active low input to Initialize the internal control and status registers
IRQ
Interrupt Request
An active low output that indicates one of the programmable interrupt
conditions has occurred.
CCLK
Character Clock
Clock input to provide timing for synchronization and screen formatting
10 MHz maximum.
RB1
Read Row Buffer
Output, read row buffer number 1.
WB 1
Write Row Buffer
Output, write row buffer number 1.
RB2
Read Row Buffer
Output, read row buffer number 2.
WB2
Write Row Buffer
Output, write row buffer number 2.
HOLD
Hold Request
Hold request output to the MPU.
HOLOAI
Hold Acknowledge
Hold acknowledge input from the MPU when the CRTC works on the
system memory; processor bus request when the CRTC works on
dedicated video memory.
HOLOAO
Hold Acknowledge
Hold Acknowledge output to a lower priority peripheral.
CUR 1
Cursor 1
Cursor 1 output.
CUR2
Cursor 2
Cursor 2 output.
7-28
F16413
Mnemonic
Name
Description
HWS
Horizontal Window Start
Output indicating the first horizontal position of a window.
HWE
Horizontal Window End
Output indicating the last horizontal position of a window.
VWS
Vertical Window Start
Output indicating the first row of a window.
VWE
Vertical Window End
Output indicating the last row of a window.
PS
Proportional Space
Input causing an update of the RAM address counter; can also be used
as a double wide attribute input.
DH
Double Height
Input for double height character attribute.
BLANK
Blank
Active low output signal to turn off the monitor video during horizontal
and vertical retrace.
HSYNC
Horizontal Sync
Active low output signal to provide horizontal sync timing.
VSYNC
Vertical Sync
Active low output signal to provide sync timing.
-----------------.
RCo·RC3
Raster Count Address
Outputs giving the current raster count value.
--------------------
System Description
Mode Control
The F16413 CRTC can basically work in two system
configurations, i.e., on a local bus with dedicated video
memory or on the system bus with access to the main
memory. In the latter case, external row buffers must be
provided, which are being loaded during DMA operation
with the characters of the next followi ng row to be
displayed.
The mode register determines the pin assignment for
either system or remote bus operation. It is also used to
select contiguous or row/column address, non·interlaced
or interlaced video, attribute delay and external
synchronization. It contains a reset control bit so the
screen format may be reprogrammed anytime after a
software reset.
There are 33 registers implemented on the F16413 for
mode control, screen formatting, and display control.
Each of these registers is individually addressable using
the lower six address pins when chip select is active.
Information can be read out from or written into the
register via the B·bit data bus.
Windowing and Scrolling
Screen Format
The horizontally displayable dimension of the screen,
horizontal front porch, sync pulse width, and back porch
are programmable in character clocks. The vertically
displayable dimension of the screen is programmable in
number of rows. The vertical front porch, sync pulse
width, and back porch are programmable in scan lines.
The number of scan lines per row is 1 to 16.
The status field may be used to provide a vertically split
screen with the video field. The window feature of the
F16413 allows a defined window anywhere in the video
field, or splits the screen horizontally into two
independent data fields. USing the split screen feature
requires programming the number of horizontally
displayed characters in each data field into the assigned
registers.
The soft scroll control register is used to enable soft
scroll, to select the area to be scrolled (either video field,
window, or status field), and to select scroll rate and
direction.
F16413
CPU/CRTC Memory Contention
The CRTC 3·states the address bus during the horizontal
and vertical blanking intervals. An interrupt is provided
at the beginning of each blanking interval.
Remote Bus Configuration
During the blanking interval the CPU is free to access
the dedicated video memory without disturbing the
display during the active video.
System Bus Configuration
The F16413 is accessing the system memory during DMA
cycles to load external row buffers. If the user provides
one external row buffer, the DMA operation starts with
the first character of the first scan line of each row and
the data is displayed immediately. In this case the RB
and WB signals are both active during the first scan line
of a row.
If two external row buffers are used, then one of them is
being loaded with the data of the following row while the
other one is sending its data of the present row to the
CRT. Loading of the row buffers starts at the beginning
of the first scan line of the previous row.
7·30
F16425
Packet Switching Frame
Level Controller (FLC)
Advance Product Information
Microprocessor Product
Description
Status can be monitored by a series of maskable
interrupt conditions or by reading eight directly
addressable status registers.
The F16425 Packet Switching Frame Level Controller
(FLC) is a member of the F16000 microprocessor family
that controls the transmission and reception of data
(message frames) in a network conforming to the
international CCITT HDLC protocol for applications in
terminals, network access controllers, and related
equipment at level 2 (frame level). It implements X.25
LAPB and portions of X.75, SDLC, and HDLC. It can be
used with most MOS microprocessor families.
Figure 1 is a block diagram of the F16425 controller.
Figure 2 shows how the F16425 interfaces with DTE and
DCE.
Signal Descriptions
Table 1 describes the signals for the F16425 controller.
The F16425 controller can be used specifically in data
terminal equipment (DTE), data circuit terminating
equipment (DCE), and network nodes (point·to·point,
switched, or nonswitched systems). It uses all basic
commands and responses-normal response mode
(NRM) and asynchronous balanced mode (ABM) with five
options. The CPU gives simple one·byte commands to
initiate link setup, disconnect and information transfer.
Signal Functions
ODIN
0,
0,
0,
0,
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
0,
0,
0,
Do
8·Bit and 16·Bit CPU Compatibility
High·Density NMOS SI·Gate Chip
64·Pin DIP with 24 Registers at 8 Bits
DC to 2.5 Mb/s
One·Mbyte Direct Address Capability
On·Board DMA to Transfer Messages to and from
Memory
Modem Interface Control Signals
Programmable Address Field and Global Address
Automatic Sequencing, Acknowledging, and
Retransmission of Messages
Automatic Frame Check Sequence Generation and
Test
TTL·Compatible
Single + 5 V Power Supply
Separate Address and Data Bus
8· or 16·Bit Bidirectional Data Bus
Automatic Zero Insertion and Deletion for
Transparency
NRZ or NRZI Serial Data
Programmable System Parameters
-Primary Timer (TI)
-Retransmission Counter (N2)
-Window Size from 1 to 127 Frames
-Buffer length from 16 to 2K Bytes
Programmable Basic or Extended Control Field
I·Field Residual Last Character
X.25 LAPB, X.75 (Excluding Multilink), SDLC, HDLC,
ADCCP
IRQ
TSO
TCLK
RCLK
RSI
RWEN
ADDRESS BUS
CHIP CONTROL
POWER
GND
voo
7·31
F16425
Figure 1
16425 Block Diagram
READ/WRITE
ENABLE
RESET
RWEN
RST
DAT:I::;:C~~:~: -~';;;------_1
~:~ ~~~:~~ -5'=-----_1
GND
~
~~~-~~~-----1
MODEM SIGNALS
TRANSMlnER
CLOCK
TRANSMlneR
OUT
INTERRUPT REQUEST
110
REGISTERS
CENTRAL
CONTROLLER
DATA BUS
ADDRESS BUS
~=========~ A8·A15
RECEIVE
~~~~======~ A16·A19
HOLDS ANO
HOLD ACKNOWLEDGE
Figure 2
FIFO
DMA
CONTROLLER
~~~~=====::~
-...:..::==--------1.____.J
X.25 Interface
SYSTEM &
SOFTWARE
F16425
PACKET
LEVEL
PROCEDURES
FRAME
LEVEL
PROCEDURES
------------------------------I
I
I
I
I
----------I
VIRTUAL CALL PROCEDURE
PACKET
(SETUP, MAINTAIN,
LEVEL
PROCEDURES FLOW CONTROL, CLEAR)
FRAME
LINK ACCESS
LEVEL
PROCEDURES
PROCEDURES
I
I
I
PHYSICAL
LEVEL
I
SYNCHRONOUS
CIRCUIT
PHYSICAL
LEVEL
I
I
DTE (USER)
DCE (NODE)
7·32
RS 232C
RECEIVER CLOCK
F16425
Table 2 F16425
Signal Descriptions
Mnemonic
Name
Description
Chip Select
An active-low input to enable READ/WRITE of the internal registers
during a peripheral access.
Do-D 15
Register
Data
A 16-bit bidirectional data bus.
Ao-A4
Address
Address bits 0-4 are output during DMA access or input during peripheral
access; high-impedance output at all other times.
A5 -A 19
Address
Address bits 5-19 are output during DMA access; high-impedance output
at all other times.
Chip Select
CS
Data Bus
Power
GND
Ground
Voo
Data Direction
Power Supply
+5 Volts
DDIN
Data Direction In
The bidirectional DDIN signal low equals WRITE to FLC: high equals
READ from FLC for peripheral access. A DDIN signal low equals WRITE
to memory; high equals READ from memory for DMA access.
Interrupt Request
An active-low output indicating that one of the programmed interrupt
conditions has occurred.
RCLK
Receive Clock
Direct clock input; the RSI signal changes on the falling edge of the
RCLK signal.
RSI
Receive Serial In
A receive serial data input signal.
TCLK
Transmit Clock
Direct clock input, the signal TSO signal changes on the rising edge of
the TCLK signal.
TSO
Transmit Serial
Out
A transmitted serial output data signal.
Interrupt
IRQ
Transmitter/Receiver
7-33
•
F16425
Table 1
F16425 Signal Descriptions (Cont'd.)
Mnemonic
Pin No.
Name
Description
Modem Control
CD
Carrier Detect
An input signal
CTS
Clear to Send
An input signal
DSR
Data Set Ready
An input signal
DTR
Data Terminal
Ready
An output signal
RTS
Request to Send
An output signal.
DMAE
DMA Enable
A high output when FLC has control of the system buses, and a low
output at all other times; can be used to control external 3-state devices.
HBE
High Byte Enable
An active-low input/output signal that enables READ/WRITE to the highorder byte of the data bus; input during peripheral access and output
during DMA access. This signal is not used in the 8-bit mode.
HLDAI
Hold Acknowledge
In
An active-low input from the CPU or higher priority DMA granting control
of the system buses.
HLDAO
Hold Acknowledge
Out
An active-low output to a lower priority DMA.
HOLD
Hold
An active-low output requesting control of the system buses.
<0
Au
256
151)
jQ
Table 1 Signal Functions
Mnemonic
Pin No.
Name
Description
Ao·A 12
2·10,21,
23·25
Address Lines
TIL·compatible input lines that identify the memory location
to be read
CE
20
Chip Enable
Programmable Input signal that latches the address and
controls operating mode; active level is user·defined.
CS 1, CS2
26, 27
Chip Select
Programmable input signals that allow memory expansion;
active level is user·defined.
GND
14
Ground
Supply and signal ground
OE
22
Output Enable
Input signal that controls outputs and provides fast data valid
time
°0·°7
11·13,
15·19
Data Lines
TIL·compatible output lines that contain the data read from
the addressed location
Vee
28
Supply
+ 5 V power supply
8·18
F3569
64K ROM
Advance Product Information
Microprocessor Product
Description
Logic Symbol
The Fairchild F35698192 x 8-bit (64K) mask-programmable, read-only memory (ROM) is designed for use in
bus-organized systems requiring non-volatile memory
storage. Because of its high speed, it readily interfaces
with all generations of NMOS microprocessors.
10
Ao
A,
A.
A4
•
•
•
•
•
•
00
13
O.
15
0,
18
Os
17
A.
As
Ar
•
11
12
Ao
Fabricated with n-channel silicon-gate technology, the
F3569 has industry-standard pinouts and is compatible
with other available 28-pin 64K ROMs and EPROMs.
•
•
00
0,
Automatic Power-Down
Access Time (tAA) of 25.0 ns for F3569-25 and 350 ns
for F3569-35
Low Power Dissipation (440 mW, Maximum, Active;
55 mW, Maximum, Standby)
Fully TIL-Compatible
Three-State Outputs
Mask Programmable Enable Function
Single 5 V Power Supply
Completely Static Operation
Pin-Compatible with Other Standard 28-Pln 64K ROMs
and PROMs
25
A8
24
As
21
A,.
23
A11
08
18
Or
19
CE
27
28
22
20
GND: Pin 14
Vee: Pin 28
The chip enable (CE) input of the F3569 controls the
active and standby modes of operation; the output
enable (OE) input controls the chip output and provides
fast data available time for high-speed microcomputer
applications (see figure 1). Two chip select (CS) inputs
are provided for memory expansion. The active levels of
the CE and CS inputs, and the memory contents, are
user-defined.
Connection Diagram
28-Pln Dip
The F3569 requires only a single + 5 V power supply, has
TIL-compatible inputs and outputs, and, due to its static
operation, requires no clocking o(refreshing.
Signal Descriptions
The input/output signal functions of the F3569 are
described in table 1.
8·19
•
F3569
Figure 1
F3569 Block Diagram
Qo Ql Q2 Qs Q4 Qs Q6 Q7
A12
All
A10
Ag
CHIP
SELECT
INPUT
BUFFERS
Y DECODER
1·0F·32 BYTES
As
A7
A6
As
ADDRESS
INPUT
BUFFERS
A4
en
As
a:;l:
wO
oa:
A2
Oeo
256
1
2
65536·BIT
CELL MATRIX
(.)1/)
WN
OLL
Al
CS1/CS1
CS2/CS2
AL
ENABLE
INPUT
BUFFER
CE/CE
><0
256
Ao
150
PI)
Table 1 Signal Functions
Mnemonic
Pin No.
Name
Description
Ao·A 12
2·10,21,
23·25
Address Lines
TIL·compatible input lines that identify the memory location
to be read
CE
20
Chip Enable
Programmable input signal that controls operating mode;
active level is user·defined.
CS 1, CS 2
26, 27
Chip Select
Programmable input signals that allow memory expansion;
active level is user·defined.
GND
14
Ground
Supply and signal ground
OE
22
Output Enable
Input signal that controls outputs and provides fast data valid
time
°0·°7
11·13,
15·19
Data Lines
TIL·compatible output lines that contain the data read from
the addressed location
Vee
28
Supply
+ 5 V power supply
-
- - ,... _---
8·20
F3570
64K ROM
Advance Product Information
Microprocessor Product
Description
Logic Symbol
The Fairchild F3570 8192 x 8-bit (64K) mask-programmable, read-only memory (ROM) is designed for use in
bus-organized systems requiring non-volatile memory
storage. Because of its high speed, it readily interfaces
with all generations of NMOS microprocessors.
10
Ao
A,
Q.
11
Q,
12
Q.
13
Q,
15
Q.
16
QS
17
Q6
18
Q7
19
A.
A,
,..
Fabricated with n-channel Silicon-gate technology, the
F3570 has industry-standard pinouts and is compatible
with other available 28-pin 64K ROMs and EPROMs.
As
A"
A7
• Access Time (tAA) of 250 ns for F3570-25 and 350 ns
for F3570·35
• High-Speed Data Valid Time of 120 ns
• Low Power Dissipation (440'mW, Maximum, Active)
• Fully TTL·Compatible
• Three-State Outputs
• Mask-Programmable Chip Select Active Levels
• Single 5 V Power Supply
• Completely Static Operation
• Pin-Compatible with Other Standard 28-Pln 64K ROMs
and EPROMs
25
A"
24
As
21
A,.
23
A11
~
27
26
22
GND: Pin 14
Vee: Pin 28
The output enable (DE) input controls the chip output
and provides fast data valid time for high-speed
microprocessor applications (see figure 1). Two chip
select (CS) Inputs are provided for memory expansion.
The active levels of the CS inputs, and the memory
contents, are user-defined.
II
Connection Diagram
28-Pln Dip
The F3570 requires only a single + 5 V power supply, has
TIL-compatible inputs and outputs, and, due to its static
operation, requires no clocking or refreshing.
NC
Vee
A,.
CS,
Signal Descriptions
A7
CS.
The input/output signal functions of the F3570 are
described in table 1.
A"
A.
As
As
,..
A11
A.
OE
A,
A,.
A,
CE
Ao
Q7
Q.
Os
Q,
Qs
Q.
Q.
Q,
GND
(Top View)
8·21
F3570
Figure 1
F3570 Block Diagram
A12
All
Al0
A9
CHIP
SELECT
INPI,IT
BUFFERS
Y DECODER
1·0F·32 BYTES
As
A7
As
As
ADDRESS
INPUT
BUFFERS
~
I/)
As
WO
A2
Oce
(.Jon
WC'oI
C§1/CS1
CS2/CS2
256
1
2
~~
CI~
Al
ClIL.
...
••
•
65536·BIT
CELL MATRIX
><0
Ao
256
Table 1 Signal Functions
Mnemonic
Pin No.
Name
Description
Ao·A,2
2·10,21,
23·25
Address Lines
TIL·compatible input lines that Identify memory location to
be read
CS" CS2
26,27
Chip Select
Programmable Input signals that allow memory expansion;
active level is user·defined.
GND
14
Ground
Supply and signal ground
OE
22
Output Enable
Input signal that controls outputs and provides fast data valid
time
0 0-07
11·13,
15·19
Data Lines
TIL·compatible output lines that contain the data read from
the addressed location
Vee
28
Supply
+ 5 V power supply
8·22
F35316/F68316
2048 x 8 ROM
Microprocessor Products
Description
The F35316/F68316 is a mask-programmable byteorganized MOS Read Only Memory (ROM) designed for use
in bus-organized systems requiring non-volatile data storage.
It is fabricated with n-channel silicon-gate technology. For
ease of use, the F35316/F68316 operates from a single
+5 V power supply, inputs and outputs are TTL and DTL
compatible, and the device needs no clocks or refreshing
because of its static operation.
Logic Symbol
AD
A,
A3
A.
•
•
00-07
11
03
13
O.
14
05
15
A7
0,
16
23
A6
07
17
22
A9
19
AlO
VCC = Pm 24
GNO = Pin 12
Connection Diagram
24-Pin DIP
Address Inputs
Chip Select Inputs
Data Outputs
A7
Vee
A,
As
As
A9
A.
CS3*
A3
CSt·
A2
AlO
A,
CS2*
AD
07
00
0,
0,
05
02
O.
GND
03
(Top View)
Absolute Maximum Ratings
Voltage on Any Pin Relative
to GND
Operating Temperature
Storage Temperature
Power Dissipation
10
02
20 18 21
2048 x 8-BIT BUS-COMPATIBLE ORGANIZATION
FULLY STATIC OPERATION
3-STATE DATA OUTPUTS FOR WIRED-OR CAPABILITY
MASK-PROGRAMMABLE CHIP SELECTS FOR
SIMPLIFIED MEMORY EXPANSION
SINGLE +5 V ± 10% POWER SUPPLY
TTL AND DTL-COMPATIBLE INPUTS
MULTIPLE SPEED GRADES
tACC = 250 ns, 300 ns (F35316)
tACC = 350 ns, 450 ns, 500 ns (F68316)
DIRECTLY COMPATIBLE WITH 2316E
PIN COMPATIBLE WITH F2708 AND F2716 EPROMs
Pin Names
Ao-A1O
CS1-CS3
0,
CSt CS2 CS3
The F35316/F68316 provides maximum circuit density,
reliability and performance yet maintains low power
disSipation and yields significant cost advantages over an
EPROM approach.
•
•
•
F35316/F68316
As
A6
The F35316/F68316 is compatible with the F6800, F8 and
other microcomputer families providing read only storage in
byte increments. To facilitate memory expansion, the device
contains three programmable Chip Select inputs providing
any combination of active HIGH or LOW or an optional DON'T
CARE state coupled with output wired-OR capability. Chip
select code and memory content are user defined and are
fixed during the masking process.
•
•
•
•
00
A2
• Programmable Chip Selects
-0.3 V to +7 V
O°C to +70°C
-65°C to +150°C
lW
Stresses greater than those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at Ihese or any other conditions above those indicated in
the operating section of this specification IS not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
8·23
II
F35316/F68316
Block Diagram
AlO
A9
As
A7
As
As
A.
on
.
a:
w
:>
III
I-
..
:>
;!;
on
on
w
a:
A3
..
C
C
16,384-BIT
CELL MATRIX
A2
128
l(
128
Al
Ao
DC Requirements
Over operating temperature range
Characteristic
Min
Typ
Vee
Power Supply Voltage
4.75
5.0
5.25
V
VIL
Input LOW Voltage
-0.5
0.8
V
VIH
Input HIGH Voltage
2.0
5.5
V
Symbol
DC Characteristics
Max
Unit
Over operating temperature and voltage range
Min
Typ
Symbol
Characteristic
Max
Unit
lee
Vee Power Supply Current
110
rnA
1
liN
Input Leakage Current
2.5
/lA
2
lOUT
Output Leakage Current
10
/lA
3
VOL
Output LOW Voltage
0.4
V
lOUT = 1.6 rnA
VOH
Output HIGH Voltage
V
lOUT = -200 /lA
2.4
Notes on following page.
8·24
Notes
F35316/F68316
AC Characteristics (F35316)
Over operating temperature and voltage range
F35316-25
IEEE
SymbolS
Symbol
Characteristic
Min
TAVAV
tCYC
Cycle Time
250
TAVQV
F35316-30
Max
Min
Max
300
Unit
Note
ns
tACC
Address to Output Delay Time
250
300
ns
4
TSLQV
tco
Chip Select to Output Delay Time
150
150
ns
4
TSHQZ
tOF
Data Hold After Deselection
10
150
ns
4
TAXQZ
tOHA
Data Hold After Address Time
10
ns
4
CIN
Input Capacitance
7.5
7.5
pF
5
COUT
Output Capacitance
12.5
12.5
pF
5
Max
Unit
Note
AC Characteristics (F68316)
150
10
10
Over operating temperature and voltage range
F68316-35
F68316-45
Characteristic
Min
Min
Cycle Time
350
IEEE
Symbol 6
Symbol
TAVAV
tCYC
TAVQV
tACC
Address to Output Delay Time
350
450
ns
4
TSLQV
tco
Chip Select to Output Delay Time
150
150
ns
4
TSHQZ
tOF
Data Hold After Deselection
10
150
ns
4
TAXQZ
tOHA
Data Hold After Address Time
10
ns
.4
CIN
Input Capacitance
7.5
7.5
pF
5
COUT
Output Capacitance
12.5
12.5
pF
5
Max
450
150
10
ns
10
Notes
1. AlImputs 5 5 V, TA = O°C
2. VIN ~ 0 V 10 5.5 V
3 Device unselected Your = 0 V to 5.5 V
4 Measured with 1 TTL load and 130 pF. tranSition tunes = 20 ns
5 Capacitance measured with Boonlon Meter
6, Timing Parameter Abbreviations
All timing abbreviations use upper case characters with no subscripts. The mitial character is always T and is followed by four descriptors. These characters specify two
signal pomts arranged In a "from-to" sequence that define a liming Interval. The two descriptors for each signal point specify the signal name and the signal transitions.
Thus the format IS'
+____--'t
Signal name from which Interval is define_d_ _ _ _ _
TranSition directIOn for first signal - - - - - - - - - - - '
I
x
x
I
Signal name to which Interval IS defined
TranSition direction for second signal - - - - - - - - - - - - - - '
The Signal definitIOns used In thiS data sheet are.
=
A
Address
0== Data In
Q:::; Data Out
W = Write Enable
E = Chip Enable
The transitIOn
H = tranSition
L = tranSition
V = transItion
X = tranSition
Z = transItion
deflnilions used
to HIGH
In
thiS data sheet are
to LOW
to valid
to Invalid or don't care
to OFF (high Impedance)
8-25
•
F35316/F68316
Timing Diagram
ADDRESS
ADDRESS X
ADDRESS Y
PROGRAMMABLE
CHIP SELECTS
YUH __________
OUTPUT
OPEN __________- (
DATA
VOl
•
DON'T CARE INPUT CONDITION OR INDETERMINATE OUTPUT STATE
Custom ROM Programming Information
The customer's unique program code pattern may be
submitted to Fairchild in several methods. The most
convenient and readily verifiable is in the form of 2708, 2716
or 2732 EPROMs. Program code patterns may also be
submitted on Fairchild Formulator MKIII floppy disks or on HP
cassette tape in Formulator or
MIKBUG* format.
Fairchild Use Only
SLNo. __________________________________
Bid Control No. ____________________________
Field Sales Engineer _ _ _ _ _ _ _ _ _ _ _ _ __
Date Sent
Customer Company Name _ _ _ _ _ _ _ _ _ _ _ _ __
Customer Contact Name _ _ _ _ _ _ _ _ _ _ _ _ _ __
Customer Part No. _ _ _ _ _ _ _ _ _ _ _ _ _ _ ___
Address _____________________________________
Phone No.~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
Fairchild Part No. ______________________________
Customer Input Media
02708 EPROM
2716 EPROM
02732 EPROM
Floppy Disk
o HP Cassette
Formulator Format
MIKBUG Format
Request for Return Media
o Listing
o EPROM (include blank EPROMs)
o
o
o
o
'MIKBUG
IS
Chip Select Information
HIGH
0
CS 1
CS2
0
CS3
0
a Motorola trademark
8.-26
LOW
0
0
0
Don" Care
o
o
o
F35316/F68316
Formulator Format
-:::0~1~1--1.1-:-2...J1-:-3_1L-:-4-J1~5--1.-:6--1.1-:-7...J1-:-B _11-::-9-J-1-::-10--1.1,,:,1_1....L...jf/ 1 M·6 1 M·5 1 M·4 1 M·3 1 M·2 1 M·l
SOR
L,
Lo
A3
SOR
A2
A,
Ao
T,
To
001
000
011
D(n-l)loln-1)O
Ont
DnD
I
CK,
Start of record defined to be a colon (:)
Type field.
Length field defined to be the number
of packed data bytes per record. Each
record is (2' L) + 11 characters in
length inclusive of start of record.
Length a implies end of relocatable
module.
001000 ... D(n)l D(n)O Data field.
M
eKo
Checksum field defined to be negative
modulo 256 summation of all bytes
since start of record. A summation of
all characters in a record, including
the checksum, will result in zero.
Address field.
All characters other than SOR are ASCII hexadecimal
(0-9, A-F).
MIKBUG* Format
I
Leader (Nulls)
Frame
(CR)
(LF)
(NULL)
CC
Frame
CC
=
31
CC
Oat.
53
53
S
53
S
2. Type 01 Record
30
31
1
39
9
31
31
4.
32
5.
30
6.
7.
Address/Size
30
30
B.
30
9.
34
10.
38
34
34
Data
S
12
36
31
30
39
38
41
38
n (Checksum)
39
45
S
Start of record
CC
Type of record
Byte Count
Two frames equal one byte. Frames 3
through n are hexadecimal digits (in
G3
33
1100
30
30
0000
30
98
46
43
FC (Checksum)
32
44-0
--
30
30
30
48-11
"" IT]
CD• -32
16
31
0000
•
39
End-ai-File
Record
Record
1. Slart-ol-Record
3. Byte Count
10
= 30
Header
Record
-~h.CkSUm)
9E
7 -bit ASCII) which are converted to
BCD.
Two BCD digits are combined to make
one
a-bit byte. The checksum is the ones
complement of the summation of a-bit
bytes.
8-27
F35316/F68316
Ordering Information*
Part No.
Order Code
F35316·25
F35316-30
F68316·35
F68316·45
F3531625P,
F3531630P,
F3531635P,
F3531645P,
P
= Plastic
S
= Ceramic DIP
F3531625S
F3531630S
F3531635S
F3531645S
DIP
* For extended temperature or military range, call factory.
8·28
[!]
1
!INTRODUCTION
r;;i2 ! ORDERING AND PACKAGE
~ INFORMATION
1C!J!F8 MICROCOMPUTER FAMILY
1 0 1 CONTROLLER FAMILY
/~IF6800 MICROPROCESSOR FAMILY
1[1J! F16000 MICROPROCESSOR FAMILY
/ W ! ROM PRODUCTS
DEVELOPMENT SYSTEMS AND
SOFTWARE
/[!QJ
/[!!]
1APPLICATIONS
! RESOURCE AND TRAINING CENTERS!
1~lsALES OFFICES
Section 9
Development Systems
and Software
General
The following is data that describes the design aids
available for hardware and software development and
emulation in the creation of Fairchild microprocessorbased systems.
•
9-3
Development Systems
and Software
9·4
EMUTRACTM
Emulation and Tracing System
Advance Product Information
Microprocessor Product
DesCription
• The Breakpoint Comparator examines the 48·Blt
Machine-State Word During Each Bus Cycle, and Can
Detect Eight Simultaneous Breakpoint Conditions.
• A Programmable Micro-Sequencer Responds During
Each Cycle to the Detected Condition by:
- Conditional Change In Sequence, with "Jump" or
"Step" Functions;
- Conditional Update of Two Independent Delay·
Counters;
- Optional Issue of Four Independent Pulses, to Sync
External Tests;
- Conditional Recording of One Trace·Frame;
- Optional "Pause:' "Interrupt:' etc., Functions.
• Each Trace·Frame Word Captures 64 Bits, Composed of
the Address Issued During Bus·Cycle and Machlne·State
Word.
• Interactive HardwarelSoftware Debugging Is Simplified,
with Symbolic LocatlonNariable-Names, Instruction
Mnemonics, and Signal· Names.
• Simple, English-like Commands Control the Emulation
Process.
• Command Language Provides REPEAT, Flle·INCLUDE,
and MACRO Capabilities, as Well as Sesslon·Logfile and
Selective-Printout Generation.
The Fairchild EMUTRAC is a powerful, cost-effective, incircuit emulation and tracing system that supports microcomputer system development. The EMUTRAC system
allows simultaneous and interactive hardware and software
development, which permits control, interrogation, revision,
and debugging of a microcomputer system in its own realtime environment. Software may be developed and debugged with or without complete prototype hardware.
• Single Controller Fits Within the F8-1 Chassis.
• Interchangeable External Modules Individually Support
F3870, F6800, F6809, and F9445 Microprocessors.
• EMUTRAC Provides Optional Substitution for CPU and
1/0 Peripherals, as Well as Memory, in Prototype
Systems.
• Address·Steering Allows Selective Substitution for Prototype System Memory, In Blocks of 64 Words.
• 8K Words (or 16K Bytes) of Mappable Substitution· RAM
Is Provided, Using 2114 or 2148 Devices.
• 4-Bit Tags, Which Aid In Breakpoint·Marking, Can Be
Associated with Individual Substitution-Memory Loca·
tlons, 256-Locatlon Blocks of Prototype Memory, or 1/0
Device Accesses.
• A Tag, User·Asslgnable Probes, Bus Data, and Functions
of Key Microprocassor and EMUTRAC·lnternal Signals
Comprise the 48-Blt Machine·State Word, Which Is Re·
evaluated for Each Bus Cycle.
•
TMEMUTRAC is a trademark of Fairchild Camera and Instrument Corporation.
9-5
EMUTRAC
System Function
Operator Interface
The EMUTRAC control software, which runs on the FS-I, has
simple setup commands that provide explicit control of the
memory mapping, tag attachment, breakpoint definition,
and sequencer action functions. Additional commands provide the block load/dump functions for RAM definition, as
well as the interactive examine/deposit-search operations
usually provided in a debugger. Simple commands provide
start, stop, and single-cycle control for the emulation; other
commands control the operator interface providing log file
and print generation, checkpoint creation and retrieval, and
REPEAT, INCLUDE, and MACRO commands. The control
software provides an easy-ta-use, concise command structure, with HELP commands to aid on-line learning, yet aids
the accomplished user through command flies to perform
repetitious tasks.
The EMUTRAC system combines the functions of console
operations, a symbolic debugger, a logic analyzer, and a
substitution CPU and memory. The system consists of an
EMUTRAC controller card that plugs into the FS-I development system and an external module that interfaces the
controller to the target system (see figure 1).
The EMUTRAC system supports all Fairchild
microprocessor families, with processor-independent
logic on the controller card and logic unique to a
specific processor residing in the external module.
Different microprocessors can be supported using
different EMUTRAC modules with the same EMUTRAC
controller card.
Figure 1
EMUTRAC System
FSI CHASSIS
CPU/DISK
1-------I
I
I
I
CRT TERMINAL
I
I
I
------------1
I
I
EMUTRAC
SYSTEM
EMUTRAC
CONTROL
SOFTWARE
I
EMUTRAC
CONTROLLER
PC BOARD
EMUTRAC
MODULE
I
I
I
I
I
I
__ ...J
LAB
OSCILLOSCOPE
OR
LOGIC
ANALYZER
9-6
EMUTRAC
Memory Substitution and Initialization
The EMUTRAC system's RAM can selectively substitute for
sections of the prototype system's memory. Thus, tablemodifications or code-patches can be made to RAM,-and
the results verified, without time-consuming PROM·programming or ROM-masking. Similarly, the RAM can be used as
memory-expansion for the. prototype system, permitting
extra-large programs (with diagnostic or debugging aids) to
be used during development and test.
Trace-frame generation Is controlled by the programmable
sequencer. Detection of a breakpoint can trigger capture of
consecutive machine cycles, and counter controls can
"center" this capture window as desired. Additionally, the
trace log can be considerably filtered to include only those
events surrounding the trigger that satisfy additional conditions, thereby making better use of available trace memory.
Alternatively, short packets of trace information can be
recorded In response to multiple trigger conditions
encountered during testing.
Block-initialization of EMUTRAC RAM or prototype RAM (or
of any control-RAM within the EMUTRAC) can be easily
accomplished with the "load from "
command. The complementary "dump into
" provides a simple way to capture the current
contents of any memory. Together, these commands allow
"snapshots" to be taken, for later comparison and analysis
or for quick state-restoration between test runs.
Software Timing
The software timing feature, which works under the control
of the breakpoint sequencer, allows the user to acquire
statistics on the performance of the microprocessor system
software modules. The timer allows the user to measure the
execution time of a block of code, as well as the number of
times that block of code was used during the execution of a
given program. This permits the user to estimate the performance of the total system and provides direction for
optimization efforts. It can also be used to identify failing
sequences that take significantly smaller or larger amounts
of time than antiCipated.
Operator Control
The console functions of the EMUTRAC system consist of
four groups: run control, memory examine and depOSit, I/O
register examine and depOSit, and CPU register examine
and deposit. The run control comprises STOP, RESET,
START, CONTINUE, and single-Instruction STEP commands.
The memory, I/O register, and CPU register examine and
deposit controls allow the user to inspect and modify the
state of the microprocessor, I/O device, and system memory
registers. Locations examined can be displayed in symbolic
form, and modifications can be made in terms of userdefined symbols and mnemonic instruction codes.
Command·Language Features
Commands to the EMUTRAC system are issued as a sequence
of simple, English-like sentences; diagnostic messages in
response to command errors, and the HELP command
assist new users In operating the system. The accomplished user is assisted by language features such as:
IF ( ... ) ELSE ( ... )
Program Breakpoints
The breakpoint feature provides controlled Interruptions or
normal program flow when the user-selected pattern of
status conditions eXists, so that memory, registers, and
CPU status can be Interrogated and traced. To aid detection
of ranges or scattered instances of address- or I/O-access,
4-blt-per-location tags are provided in EMUTRAC memory;
thus, improper memory WRITE operations, access to nonexistent memory or I/O devices, and references to key
variables are all simple to identify. The EMUTRAC breakpointing facility is extremely powerful; up to eight independent breakpoints can be simultaneously monitored.
which allows conditional command-issue,
REPEAT ( ... )
which reissues a set of commands several times,
INCLUDE
which issues a pre-recorded sequence of commands, and
MACRO ( ... )
which constructs sequences with replaceable elements.
Real·Time Trace Control
The tracing feature of the EMUTRAC system functions like
a dedicated logic analyzer, giving the user a record of up to
255 previous events. The "audit trail" thus created can be
used to find the cause of system failure. The EMUTRAC
system, however, offers much more than a normal logic
analyzer.
During the emulation, all commands are recorded In a
session-log file as they are issued; this file could, for
instance, be printed as documentation of test results.
The run can later be duplicated, or extended, by simply
Issuing the saved log-ciata as commands with an INCLUDE
statement.
9-7
•
EMUTRAC
9-8
F8 and F387X
Formulator
Microprocessor Product
Description
The top of the line is the Formulator Mark IIiFO. This
system is identical to the Mark III, except it interfaces to
the iCOM dual-drive floppy disk.
The microprocessor system designer can create
hardware and software development systems for the F8
and F387X by selecting modular subassemblies from
Fairchild's line of F8 and F387X design aids.
Development may start with a Formulator Mark I singleboard system, then expand to more sophisticated Mark II
or Mark liFO development systems than can handle both
software and hardware development (see figure 10-1).
Future growth may lead to a complete Formulator Mark
III with intelligent control panel, power supply and
accessories, or to the top of the line Formulator Mark
IIiFO with floppy disk drives.
Three growth packages are available for Mark I, Mark II,
and Mark III expansion. Growth Package I upgrades the
Mark I system to the Mark II level. Growth Package II
converts the Mark II to the full Mark III level. Growth
Package III upgrades either the Mark II or Mark III to the
Mark liFO or the Mark IIiFO floppy disk configurations.
Other boards are available as options for all five
Formulator configurations to increase the flexibility of
the units by adding to their capabilities_ These include
4K-byte RAM, 4K-byte PROM, and 16K-byte RAM boards,
as well as an 1/0 light board, a communications board
with UART, a byte-parallel board for peripheral interface,
and a PROM programmer.
Three growth packages plus a selection of optional
modules provide a practical method for upgrading the
single-board Mark I to either the Mark II or Mark liFO, or
to the maximum system configuration Mark III or Mark
IIiFO. Using the growth packages, the designer can
begin sophisticated system application programs at very
low cost and then upgrade the development tools in
relatively inexpensive steps at a later time.
The most elementary configuration, called the
Formulator Mark I, includes a processor module that
contains an F8 CPU, program storage unit that includes
a debug program, dynamic and static memory interface
circuits, 1024 bytes of random access memory, and the
necessary buffers and other components for hardware
development. It also includes a 13-slot card cage, an 1/0
cable kit, and a power cable.
The second level, the Formulator Mark II, includes all of
the Mark I components plus a memory board with 16
kilobytes of RAM and the complete Formulator operating
system, designated FOS. The FOS provides complete
software development capability, including an
assembler, editor, and debug package, and drivers for a
teletype or the TI Silent 733 terminal.
The third level, the Formulator Mark liFO, is identical to
the Mark II with the addition of interface cards and
cables for an iCOM F03712 dual-drive floppy disk system
and Fairchild 00S4 Floppy Disk Operating System.
The fourth level, the Formulator Mark III, includes an
intelligent control panel, a serial communications
module, a quad 1/0 module, an attractive cabinet, and a
power supply. Also included are 16K bytes of RAM, the
Formulator processor module, and the Formulator
operating system.
g.g
F8 and F387X
Formulator
9-10
FS-I
Fairchild System-I
Microprocessor Product
Advance Product Inlormation
Description
Multi·User System
The Fairchild System· I (FS·I) is a versatile, multi·user
development system designed to support software
development and hardware prototyping for applications
using Fairchild microprocessors, including the F8,
F3870, F6800, F6809, F9445, F16000, and such upcoming
microprocessors as the F9450.
System features include:
Three principal versions of the FS·I are available: The
FS·I Standard System, the FS·I Multi·User System, and
the FS·I Entry·Level System. Numerous software and
hardware options are available that operate under
Fairchild's Interactive Multi·User Disk Operating System
(1M DOS). The FS·I also supports the in·circuit emulation
and tracing (EMUTRAC™) system for the F3870, the
F6800, F6809, and the F9445 microprocessors. (For a
description of the EMUTRAC system, see EMUTRAC
Advance Product /nformation.)
•
•
•
•
•
•
Standard System
•
System features include:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
CPU with 128K·Byte RAM and F9445 Instruction Set.
A Winchester and a Double·Density Floppy Drive
Provide Approximately 10M·Byte 01 Mass Storage.
1/0 Controller Board Provides Winchester/Floppy Disk
Controller Interlace.
Nine Asynchronous Serial RS·232C Ports (Up to 19.2K
Baud) Provide Support lor CRT Terminal, Optional
Letter·Quality Printer, Modem, and Other Serial
Devices.
One Synchronous Serial RS·232C Port (Up to 19.2K
Baud) and Selectable Protocols, such as BISYNC,
OOCMP, SOLC, and HOLC.
PROM Programmer Port to Interlace to the Optional
Fairchild PROM Programmer Unit.
Parallel Printer Port (Centronics·Compatible
Interlace).
Programmable Real·Time Clock.
One CRT Terminal.
Single·User Version 01 1M DOS, System Processors,
and System Utility Programs (see "System
Software").
BASIC Language Interpreter with Interlace to Custom
F9445 Assembly Language Programs.
FS·I Diagnostic Programs.
Provides Full Support lor the F9445 and lor the
PEP 45 Microcomputer System.
Hardware and Software Upgradable to Multi·User
System.
EMUTRAC Can Be Added to the Standard System.
•
•
•
•
•
•
•
•
Fully Equipped lor Four Timesharing Users
(Expandable to Eight Simultaneous Users with
Additional Terminals and Cables).
A 16·Bit CPU with 128K·Byte RAM and F9445
Instruction Set.
A Winchester and a Double·Density Floppy Drive
Provide Approximately 10M·Byte of Mass Storage.
Memory Management and Protection Unit (MMPU)
Board with 384K Bytes 01 RAM (Gives the System
512K Words 01 RAM).
I/O Controller Board Provides Winchester/Floppy Disk
Controller Interlace.
Nine Asynchronous Serial RS·232C Ports (Up to 19.2K
Baud) Provide Support lor CRT Terminals, Optional
Letter·Quality Printer, Modem, and Other Serial
Devices.
One Synchronous Serial RS·232C Port (Up to 19.2K
Baud) and Selectable Protocols, such as BISYNC,
ODCMP, SDLC, and HDLC.
PROM Programmer Port to Interlace to tlte Optional
Fairchild PROM Programmer Unit.
Parallel Printer Port (Centronics·Compatible
Interface).
Programmable Real·Time Clock.
Four CRT Terminals.
Multi·User Version of 1M ~OS, System Processors,
and System Utility Programs (see "System
Software").
BASIC Language Interpreter with Interface to Custom
F9445 Assembly Language Programs.
FS·I Diagnostic Programs.
Provides Full Support lor the F9445 and lor the PEP
45 Microcomputer System.
EMUTRAC Can Easily Be Added to the Multi·User
System.
Entry·Level System
System features include:
•
•
•
•
™ EMUTAAC is a trademark of Fairchild Camera and Instrument Corp.
9·11
A 16·Bit CPU with 128K·Byte RAM and F9445
Instruction Set.
Two Double·Density Floppy Disk Drives Provide
Approximately 1M·Byte of Mass Storage.
1/0 Controller Board Provides Floppy Disk Controller
Interface.
Nine Asynchronous Serial RS·232C Ports (Up to 19.2K
Baud) Provide Support for CRT Terminal, Optional
Letter·Quality Printer, Modem, and Other Serial
Devices.
9
FS·I
•
•
•
•
•
•
•
•
•
•
•
•
One Synchronous Serial RS·232C Port (Up to 19.2K
Baud) and Selectable Protocols, such as BISYNC,
DDCMP, SDLC, and HDLC.
PROM Programmer Port to Interface to the Optional
Fairchild PROM Programmer Unit.
Parallel Printer Port (Centronics·Compatible
Interface).
Programmable Real·Time Clock.
One CRT Terminal.
Single·User Version of IMDOS, System Processors,
and System Utility Programs (see "System
Software").
BASIC Language Interpreter with Interface to Custom
F9445 Assembly Language Programs.
FS·I Diagnostic Programs.
Full Support for the F9445 and for the PEP 45
Microcomputer System.
Hardware and Software Factory·Upgradeable to
Standard or Multi·User System.
EMUTRAC and MMPU Can Be Added to System.
•
Expansion Slots for Fairchild's Optional 1/0
Controller Boards, Optional EMUTRAC Controller
Board, Memory Expansion Boards, MMPU Board, and
Industry·Standard, Nova~ 1/0·Compatlble Interface
Boards.
Depending Upon System Configuration, the
Mainframe Contains a Single 10M·Byte Winchester
and a Single 0.5M·Byte Double·Density Floppy Disk
Drive or Two 0.5M·Byte Double·Denslty Floppy DiskDrives.
The MMPU board expands the phYSical address space of
the FS·I to 4M words by performing logical·to·physical
address translation. This board is required for multi·user
system software. With its 384K bytes of RAM, the MMPU
board extends the FS·I memory to 256K words.
Hardware Options
The FS·I systems support the following Fairchild·
supplied hardware options:
System Hardware
• Additional I/O Controller Boards that Provide
Asynchronous RS·232C Ports (Up to 19.2K Baud) in
Sets of Eight, a Synchronous RS·232C Port for each
I/O Controller Board, Data Channel Interface to Disk
Units, and a PROM Programmer Port for each I/O
Controller Board.
• Fairchild's PROM Programmer Unit.
• MMPU Board that Provides Memory Mapping and
Protection Expansion In Increments of 384K Bytes,
Optional Multi·User Software Allows the MMPU Board
to Support Eight Simultaneous Users.
• Memory Expansion Board that Provides 384K Bytes
of Additional RAM (Requires an MMPU Board In the
Chassis).
• EMUTRAC System Controller Board that Provides the
Hardware Interface Between the CPU Board in the
FS'I and Processor·Speclflc EMUTRAC Modules.
• EMUTRAC Modules and EMUTRAC Control Software
that Support the F3870, the F6800, the F6809, and the
F9445 Microprocessors.
• Additional CRT Terminals.
• Dot Matrix Printer-Texas Instruments Model 810
Basic RO Terminal (150 CPS), Centronics Parallel
Interface, and Cable.
• Daisywheel Letter·Quality Prlnter-Qume Model
Sprint 9145 with Bidirectional Forms Tractor (45 CPS),
Serial Interface, and Cable.
The hardware comprising the FS·I development system is
housed in a single enclosure that contains the
mainframe CPU, 1/0 board, optional boards, and disk
drives.
The mainframe consists of:
•
•
•
•
•
Single·Board 16·Blt CPU with 128K Bytes of RAM,
4K·Byte PEPBUG45 PROMs for Bootstrapping the
System, Real·Tlme Clock, an RS·232C·Compatible
Port, and a Centronics·Paraliel Compatible Port.
Power Supplies.
1/0 Controller Board with the Following:
• Eight Asynchronous Serial RS·232C Ports, with
Four Ports Having Full Modem Control and All
Ports Having Data Rate Selectable Up to 19.2K
Baud, that Allow Timesharing by Up to Eight
Concurrent Users on Systems Equipped with
MMPU Board and Multi·User Operating System
Software.
• One Synchronous Serial RS·232C Port (Up to
19.2K Baud) and Selectable Protocols, such as
BISYNC, DDCMP, SDLC, and HDLC.
• A Parallel Data Channel Interface Compatible with
Shugart Associates System Interface for
Communicating with Disk Units.
• 8·Blt Parallel Port to Interface with Optional
Fairchild PROM Programmer.
A Total of Nine Asynchronous Serial Ports (RS·232C·
Compatible, DB25·Pin Female Connectors).
One Parallel Printer Port (Centronlcs·Compatible
Interface, DB25·Pin Connector).
• Nova is a .registered trademark of Data General Corp.
9·12
FS·I
This powerful software package, which is included with
the standard, multi-user, and entry-level systems, offers
advanced capabilities that the user would normally
expect from a much larger system, such as:
•
•
•
•
•
•
•
•
•
•
Multi-User Timesharing
System Executive, Including File Management
System with Version Numbers for Automatic Backup
Memory Management and Protection by Memory
Mapping
Password Protection
Interactive Command Language and Command Files
Multiple Directory Devices
Device-Independent I/O
Hard Disk, Magnetic Tape, Modem, and Real-Time
Clock Support
Documentation Aids
Concurrent Processing and Spooling
PEPBUG45
The PEPBUG45 program is a virtual
console and debugging tool for F9445
absolute assembly language
programs. The PEPBUG45 program is
also available in PROM.
PEPLlNK45
Provides capability to download
programs from the FS-I to PROM or
RAM on the PEP 45 microcomputer
system.
Utility Library
Implements the utility functions listed
in the IMDOS and utility library users
guides.
PHONE
The PHONE program establishes
communication between the FS-I and
a modem or telephone line. Software
switches govern communication
protocols.
SCRIPT
TheSCRIPT program processes a text
file that contains SCRIPT commands
to produce an aesthetically pleasing
document.
TYPESET
The TYPESET program processes a
text file that contains TYPESET
commands to produce an
aesthetically pleasing document.
DEBUG
The DEBUG program is a debugger
for F9445 macro assembly language
programs.
DIAGNOSTICS
A series of programs that test the
FS-I hardware. The diagnostic
programs are available on diskette in
a version suitable for downloading to
an F9445-based system.
BASIC
Language interpreter with interface to
custom F9445 assembly language
programs.
System Software
The interactive multi-user disk operating system (IMDOS)
is the principal operating system for the FS-I. In addition
to being an operating system, the IMDOS includes the
following features that are useful for developing
F9445-based systems:
IMDOS
Single-User Supervisor-The
supervisor manages the FS-I
resources and controls the 110.
IMDOS
Multi-User Supervisor- The supervisor
manages the FS-I resources for up to
eight simultaneous users, controls
the 110, and interfaces transparently
to the MMPU board (included only
with the multi-user system).
IMDOS
Executive-The executive provides
the command language interface
between the user and the supervisor.
EDIT
The EDIT program provides the ability
to create and modify text files.
MACRO
The MACRO program is the
macroassembler for F9445 macro
assembly language.
RELOAD
The RELOAD program is used to link
relocatable macro assembly language
programs to create executable F9445
absolute assembly language
programs.
9-13
•
FS·I
Software Options
F9445
MICRO FORTRAN
F9445 PASCAL
An extended subset of FORTRAN66
that interfaces with custom F9445
.assembly language subroutines.
MICROFORTRAN produces
"ROMable" F9445 code and can be
operated under the real-time
executive (REX):
A Jensen and Wirth-compatible
PASCAL. The F9445 PASCAL
compiler generates F9445 code and
interfaces with custom F9445
assembly language subroutines.
FS-I/PEP 38
System Software
Includes F8/F3870 cross assembler
and program for downloading to the
PEP 38 system.
FS-I/PEP 68
System Software
Includes F6800 cross assembler,
F6809 cross assembler, F6800-toF6809 translator program, and
program for downloading to the PEP
68 system.
F16000 Cross
Software
F9445 REX
A real-time executive for
F9445-based systems. The REX
system allows creation of custom
REX programs, linkable using
RELOAD.
F9445 PEPBASIC
A diskette version of PEPBASIC
(supplied on PROM with the PEP 45
system). A 2K-word subset of BASIC.
which accepts abbreviations, that is
extendable with custom F9445
assembly language subroutines.
EMUTRAC Control
Software
Optional EMUTRAC control software
packages provide support for each
processor-specific- EMUTRAC
module. (Refer to EMUTRAC
Advance Product Information.)
In addition, all Fairchild software for the FS,I is
independently available without system purchase under
an ilppropriate software license agreement.'
Dimensions and Power Requirements
The FS-I standard mainframe enclosure measures only
26 inches long by 19 inches wide by 13 inches high. It
requires a 115 V, 60 Hz ac power source. A 50 Hz system
is also available.
Assembler, debugger, and
down loader allow the FS-I to
generate 16000 code that can be
downloaded to an F16000-based
system.
9-14
PEp·45
Prototyping, Evaluation and
Programming Board
Advance Product Information
Microprocessor Product
Description
Software Support
The Fairchild PEP-45 is a single-board microcomputer for
Prototyping, Evaluation, and Programming of microprocessor-based system applications using the F9445 microprocessor. When used with the Fairchild System-I (FS-I)
development system, the PEP-45 board provides capability
for executing and debugging software directly on the F9445
microprocessor.
In addition to serving as an efficient stand-alone evaluation
module, the PEP-45 is designed to operate as a key module
of the FS-I development system. A PEPLINK utility transparently couples the FS-I video terminal to the PEP-45 board.
A powerful PROM-based PEP BUG debugging monitor provides commands for trouble-shooting assembly language
programs and for developing and testing peripheral circuits
and custom interfaces. A PROM-based PEP BASIC language
allows programming in a high-level language.
• Stand-alone Prototyplng, Evaluation, and Programming
Board.
• Provides a Powerful Development Tool to Support F9445
Microprocessor-based System Development.
• Utilizes All the Advantages of the F9445 Microprocessor,
with Its Powerful Instruction Set and High Throughput.
• Memory Options for Bipolar and NMOS Memorles_
• Interfaces with IEEE 796 Standard Bus_
• Buffered F9445 bus_
• On-board EPROM programmer_
• Adapts to 16K or 32K Byte EPROMs or 64K Byte Masked
ROMs_
• Standard- and High-Speed RAM Options.
• Console Commands.
• Two Serial I/O Ports_
• 16-Blt Parallel Input/Output.
• Four Interrupt Sources_
• Five Status Llnes_
• On-board +12 V and +25 V Voltage Converter_
• Requires Single +5 V Power Supply.
Hardware Specifications
Microprocessor
CPU
F9445
Data word size
16 bits
Instruction word size
16 bits
Address capability
128K bytes
Console controller
F9470
Memory
RAM
The PEP-45 board is primarily intended for use in hardware
prototyping and software development applications. It may
also be tied to a host computer, such as the FS-I, for large
program editing, assemblinglcompiling, and general file
storage and handling. Cross-assembler software packages
are available for creating machine-executable programs in
formatted form. These programs may be down-loaded from
the host computer system into the PEP-45 board via one of
the two serial 110 channels. Since the PEP-45 board can
operate in a transparent fashion, it may be placed in-line
between the user's in-house terminal and the host computer, giving the PEP-45 the power of the host.
ROM
Eight sockets for 16K bytes of
F2716 EPROMs (8K words), or up
to 32K bytes using F2732 EPROMs
(16K words), or masked 64K byte
ROMs using F3564
Expansion
External memory in any combination of RAM or ROM up to 64K
bytes maximum (in 16-bit-wide
only)
Input/Output
Parallel 110
Also useful for incoming inspector of F9445 parts and as a
microcomputer training tool, the PEP-45 interacts with the
user at the control terminal, with prompts that assist programming. The control terminal may be a video terminal,
printer terminal, or from a microcomputer control console.
9-15
8K bytes (4K words) static RAM
(or optional high-speed RAM)
Two TTL-compatible, 16-bit 110
ports (one input, one output)
Serial 110
Two programmable, asynchronous
channels, with RS-232 interfaces.
Each channel is software-selectable to a baud rate of 110, 300,
1200,1800,2400, or 4800 baud
Real-Time Clock
Continuously selectable real-time
clock interrupts from approximately 200 !AS to 200 ms
a
PEP·45
System Buses
Dual backplane buses
PI-An 86-pin asynchronous system bus compatible with standard
Multibus 16-bit slave boards and
multi-master option
P2-A 50-pin buffered F9445 bus
that allows complete expansion of
processor capabilities and faster
operating speeds
1/0 buses
J1-A 9-pin RS-232C serial 1/0
interface for control terminal
J2-A 9-pin RS-232C second
serial 1/0 interface for a serial
printer or a host computer
+5 V ±5% at 3.5 A (typ)
Environmental
Requirements
Temperature
O·C to +50·C
Humidity
0% to 90% (noncondensing)
Physical Envelope
Dlmenslons2
Height
10.0 (254)
Length
12.0 (305)
Thickness
0.75 (19.05)
17 oz. (approximately)
Weight
P3-A 40-pin applications connector with two parallel 1/0 ports
(one input and one output), and
with status and control bits. May
be used for connection to the
microcomputer control console or
to a high-speed parallel printer
(Centronics-type)
Connectors
Power Supply
Requlrements 1
Note.
1. Power may be applied to the board either through the card..,dge backplane connector or by connection of discrete wires to the board.
2. All dimensions are in inches and millimeters (in parentheses).
Fairchild cannot assume responsibility for use of any circuitry described other than circuitry embodied In a Fairchild
product.
P1 - An 86-contact, double-sided
edge connector on 0.156" centers
Fairchild reserves the right to make changes in the circuitry
or specifications at any time without notice.
P2 - A 5O-contact, double-sided
edge connector on 0.100" centers
J1, J2-9-pln, D-type subminiature right-angle connectors
P3-A 40-pln, Ootype subminIature right-angle connector
Ordering Data
Part Number
Product Code
PEP 9445SFX
A F944516PEP
Description
PEP-45 Board with 8K byte PROM sockets populated with PEPBASIC
and PEPBUG firmware. Firmware carries copywriter notice. Minimum of
four PROM sockets will not be populated.
PEP-45 Users Guide, PEPBASIC, and PEPBUG Users Guide supplied.
PEP9445SXX
A F944516PEP
PEP-45 Board with 8K byte static MOS and eight PROM sockets not
populated.
PEP-45 Users Guide supplied. No firmware Included.
PEP 9445HXX
A F944520PEP
PEP 9445 Board with 8K byte high speed RAM and PROM sockets not
populated.
PEP-45 Users Manual supplied. No firmware or users guides included.
9-16
PEP 68 System
Single-Board Microcomputer
Development System
Advance Product Information
Microprocessor Product
Description
•
•
•
•
•
•
•
Single· Board, Stand·Alone System
Processor Options-6S02, 6S0S, or 6S09
Asynchronous Multibus· Compatible
Auxiliary Synchronous 6S0X Bus
Programming Socket for 2716 or 2732 EPROMs
SK-Byte System Monitor in ROM
9K Bytes of Static RAM-SK User, 1K System (Write·
Protectable Segments)
• Six Sockets for User·Supplied ROMIEPROM (2K, 4K,
or SK Types)
• Sixteen Possible Memory Map Configurations
(Switch-Selectable)
• Two High-Speed Audio Cassette Tape Interfaces
• Two Independent Serial 1/0 Channels-RS-232-C
• Independent Baud Rate Selection-50 Through
19.2K bps
• Connector for Parallel Printer (Centronics Type)
• Six S-Bit Parallel I/O Ports Plus Controls
• Three Programmable 16·Bit Binary Timers
• + 5 Volt-Only Operation
The PEP 68 System is a single·board microcomputer
specifically designed to aid microprocessor
hardware/software designers in designing, prototyping,
and debugging their 6802·,6808·, or 6809·based system.
A powerful, ROM·based debugging monitor provides
commands for trouble·shooting machine·language
programs. Other monitor commands provide for easy
development and testing of peripheral circuits and
custom interfaces. The monitor includes a full
complement of utility routines to make the
hardware/software/firmware design cycles as easy as
possible.
The PEP 68 System is useful as a microcomputer
training tool. Its friendly interaction with the user at the
control terminal, through its liberal use of prompting,
makes procedures easy to learn for the beginner. The
system can be operated using only a serial display
terminal and a power supply.
Since the system possesses two separate bus
connectors, expansion with external memory or
peripheral boards is simply a matter of providing a
backplane connection. Thus, the PEP 68 System can act
as a bus master in a multicard system.
II
*Multibus is a trademark of Intel Corporation.
9·17
PEP 68
Block Diagram
CRT Terminal
Connector
Secondary Channel
Connector
Multibus
Edge
Connector
Auxiliary
Synchronous
Bus Edge
Connector
General Purpose 110
Parallel Printer
Connector
(Also for General·
110 Edge
Connector
Purpuse 110)
Hardware Description
on the other hand, allows for system expansion with
peripheral boards that use the industry-standard
Multibus interface. The asynchronous aspect is
accomplished by stretching the CPU's system clock.
Both bus interfaces on the PEP 68 System can
simultaneously connect to external peripheral boards.
However, the PEP 68 System can be the only master
central processor board in the system.
The PEP 68 System is a single-board, stand-alone
microcomputer utilizing either a 6802, 6808, or 6809
microprocessor as its central processing element. The
system may be connected to a larger, host computer
system to utilize that system's file storage, editing, and
assembling capabilities. Thus, source language
programs can be created, edited, and assembled on the
host computer system using PEP-UP cross-assembler
software packages. The resulting machine-language
programs can then be downloaded into the PEP 68
System on-board RAM, executed, and debugged.
Memory
The PEP 68 System contains 8K bytes of on-card static
RAM storage for user application programs. Each
4K-byte segment can be separately write-protected by
means of either an on-card switch or by signals at the
bus edge connector. There are an additional 1K bytes of
RAM for use by the board's ROM monitor. A total of six
ROM or EPROM sockets is provided on-board. Each can
be jumpered for either 2K, 4K, or 8K-byte devices, i.e.,
many of the various 24-pin ROMs or EPROMs. Normally,
one or two of these sockets contain the FAIRBUG/68
monitor ROM, but if desired, they can be used for user
code instead.
Dual Bus Interfaces
The PEP 68 System can also serve as the central
processor in a multi board system with connections to
peripheral boards accomplished via a bus interface and
the cardcage backplane. It has two separate bus
interfaces: one synchronous and one asynchronous. The
synchronous bus interface includes the system CPU
signals and allows for expansion using synchronous
680X peripheral boards. The asynchronous bus interface,
9-18
PEP 68
All on-board memory and I/O address decoding is done
through the use of a bipolar PROM. This PROM and the
four DIP switches tied to it allow the user to select one
of 16 different memory map configurations depending on
system requirements. This feature is especially useful
during the program development phase of a project since
the user's code can be resident in either RAM or EPROM
and can be relocated with a switch change.
interfaces are driven by code contained within the
monitor, thus minimizing the required hardware circuitry.
The recording format is a self-clocking method that
allows synchronous data transfers rates of up to 2000
bits per second. Connections between the recorder and
the board are made with subminiature phone jacks.
Serial I/O Channels
The PEP 68 System provides a zero-insertion-force
socket for electrically programming 2716 and 2732 type
EPROMs; therefore, the user's application programs
residing in RAM can be preserved by "burning" the code
into an EPROM. Subsequent execution can be from
either RAM or EPROM. The programming socket is
driven by signals from three of the six on-board 1/0
ports. The monitor provides commands to perform the
following: blank check tests, copy EPROM contents to
memory, verify EPROM contents against memory,
program any portion of EPROM, and masking non-blank
EPROMs against code in memory.
EPROM Programming Socket
The board contains two serial 1/0 channels. Both
channels are general-purpose and may be used with any
serial RS-232-C device. One channel is normally used for
communication with the user's control terminal; while
the second channel would normally be used for the
interface to the host computer system. However, this
second channel could be used for any serial 1/0 use,
such as a printer or modem. The RS-232-C interfaces
generate their own + 12 and -12 volt levels. Thus no
additional supplies, other than the + 5 Vdc supply, are
required.
Software Description
Each channel has a separate baud-rate clock circuit in
which the baud-rate is hardware switch-selectable. This
allows very fast communication with a local command
terminal on channel 1 and communication with a slower
speed device such as printer, modem, or phone link on
channel 2. Allowed baud rates on each channel are 50,
110,150,300,1200,1800,2400,4800,9600, or 19,200 bps.
•
•
•
•
•
•
•
•
Parallel I/O Ports and Programmable Timers
The PEP 68 System has six 1/0 ports and associated
control signals that can be used for general-purpose
input/output. Four ports are available at the top card
edge connector, while the remaining 2 are accessible via
a special plug-in connector. The latter two ports can be
used optionally for driving a high speed parallel printer
with a special cable that attaches to the board through
the plug-in connector.
•
•
•
•
•
•
•
The signals and controls associated with the three
binary timers are accessed via the card edge connector.
Each of these three software programmable timers is 16
bits long and can be operated in several different modes,
including continuous, single-shot, frequency comparison
or pulse-width comparison modes.
•
•
Audio Cassette Tape Interfaces
•
There are provisions on the PEP 68 System for
connecting two audio cassette tape recorders for storing
and retrieving user's applications programs. The
•
•
9-19
Display or Alter any CPU Register
Display or Alter any Memory Location
Display a Range of Memory
Display the Previous (or next) Location in Memory
Rapidly Input Consecutive Data Strings to Memory
Find (search for) the Address of the Next Occurrence
of a Specified Data String
Fill a Range of Memory with a Given Data String
Move (Copy) a Block of Memory from One Address
Range to Another Address Range
Go to an Address and Begin Executing a User
Program
Load a Formatted File from Either Serial Channel
with an Optional Address Bias (Multiple Formats
Allowed)
Punch/Dump a Formatted File to Either Serial
Channel with an Optional Address Bias (Multiple
Formats)
Compare Two Memory Ranges for Differences
Calculate Checksums Over a Range of Memory
Insert a Program "Patch"
Disassemble Machine Code into Assembly
mnemonics
Set, Clear, and Display up to 8 Address Breakpoints
Remove all Breakpoints Temporarily and Then Be
Able to Restore Them Intact
Continue or Resume Execution" After a Break Occurs
or After Stopping or Tracing
Calculate Relative Branch Offsets and Perform
Double Precision Hexadecimal Arithmetic
Program 2716 or 2732 Type EPROMs
II
•
PEP 68
• Transparent Mode Operation for Conversing with a
Host Computer from the Same Command Terminal
• Echo Incoming Data from Either of the Serial
110 Channels to the Parallel Printer Port
• Echo Monitor Output to Parallel Printer Port for
Hardcopy of Monitor Output
• Enter ASCII Strings to Memory
• Print ASCII Strings from Memory
• Keyboard Test Mode
•
•
•
32 User· Definable Functions
Examine/Alter 110 Port Bits
Single·Step Program Execution Through NN
Instructions of a Program
• Step Through Instructions Conditionally Until
Specified Condition is Met
• Trace Through NN Instructions Displaying the CPU
Registers After Each Instruction
• Trace Through Instructions Displaying CPU Registers
After Each Occurence Until Specified Condition
Is Met
Applications
Low·Cost Development System
MODEMI
ACOUSTIC COUPLER
OR ANY RS-232-C
SERIAL DEVICE
F68 PEP SYSTEM
TERMINAL
More Powerful Development System
HIGH SPEEO
PARALLEL PRINTER
HOST
COMPUTER
SYSTEM
FBB PEP SYSTEM
USER'S COMMANO
TERMINAL
AUXILIARY
TO BUS SYNCHRONOUS
BACKPLANE
TO ASYNCHRONOUS
BUS BACKPLANE
I
I
I.
9·20
PEP 68
Dedicated Use
2 SERIAL I/O
CHANNELS
I___
~
~r
rL-:_-::~~--
6 PARALLEL I/O
PORTS PLUS
3TIMERS
F68 PEP SYSTEM
TO ASYNCHRONOUS
BUS BACKPLANE
(OPTIONAL)
TO SYNCHRONOUS
BUS BACKPLANE
(OPTIONAL)
I
I
Multi·Bus Card Cage Use
9·21
PEP 68
Hardware Specifications
Timers
Hardware Specifications
3 Binary Timers
Three separate 16-bit binary
counters
Microprocessor
CPU
6802, 6808, 6809
Data word size
8 bits (1 byte)
Instruction word
size
6809: 1-4 bytes 6802/6808: 1-3 bytes
Cycle time
1.0 P.s
System clock
4,000 MHz
Address
capability
65,536 bytes
Each independently software
control able and readable
Each with external clock and gate
controls for frequency and pulse·
width measurements
Each with a counter output pin
Interrupts
Hardware
Memory
One non-maskable interrupt line
available at both system bus edge
connectors (wired-OR to the Restart
pushbutton switch for initiating
manual interrupts)
RAM
9K bytes, static
2114 RAM on-board
One maskable interrupt line for fast
interrupt response (6809 only)
ROM
Six sockets for 24·pin ROMs or
EPROMs. Accepts device types:
2516, 2716, 2532, 2732, 68316, 68332,
68364, or 68764 (I.e., anywhere from
2K to 48K bytes of ROM)
One maskable 1/0 interrupt line
Expansion
Software
External memory in any combination
of RAM or ROM up to 64K bytes
maximum
Input/Output
Parallel 1/0
Six TTL-compatible, bidirectional
8-bit 1/0 ports with two port controls
each
Serial 1/0
Two programmable, asynchronous
channels with full RS-232-C
interfaces
Each channel is double·buffered and
has independent switch·selectable
baud rates of 50, 110, 150, 300, 1200,
1800,2400,4800,9600, or 19,200 bps
9·22
Software interrupts available:
1 for 6802/6808
3 for 6809
PEP 68
Power Supplies
System Busses
Dual Backplane
Busses
Requirements
P1-an 86-pin asynchronous system
bus compatible with standard
Multibus slave boards (multi-master
options not supported)
+ 25 Vde @ 30 mA (typ) (used for
EPROM programming only)
Environmental
P2-a 60-pin synchronous MPU bus
that allows complete expansion
capabilities and faster operating
speeds
1/0 Busses
+5V dc ±5% @ 2.5 A (typ)
Temperature
o to
Humidity
o to 90% (noncondensing)
+50'C
Physical
Dimensions 2
P3-a 60-pin applications bus with
four parallel 1/0 ports with controls,
plus three sets of counter controls
for the three on-board binary timers
P4-a 25-pin applications connector
with two parallel 1/0 ports with
controls; can be used for connection
with a high-speed parallel printer
(Centronics type)
Height
8.0 (203.2)
Length
12.0 (305)
Thickness
0.672 (17.1)
Weight
17 oz. (approximate)
P5-a 9-pin RS-232-C serial 1/0
interface
1.
P6-a 9-pin RS-232-C serial 1/0
interface
Power can be applied to the board either through the card·edge
backplane connector, or by connection of discrete wires to the onboard screw-down terminal strip.
2.
All dimensions in inches bold and millimeters (parentheses)
Noles
Connectors
P1-86-contact, double-sided edge
connector on 0.156" centers
II
P2-60-contact, double-sided edge
connector on 0.100" centers
P3-60-contact, double-sided edge
connector on 0.100" centers
P4-25-pin, subminiature D-type
right angle connector
P5, P6-9-pin, subminiature D-type
right angle connector
9-23
PEP 68
Ordering Information
Order Number
IT
PEP680XCSD
L...._ _ _
Relocatable Macro Cross·Assembler Software Packages
for F6800, F6801, F6802, F6803 Using
Intel MDS·800 Series Development Systems
Description
PEP 68 Single Board Development
The PEP 68 System is available with cross·assembler
software packages that allow users of Intel development
systems to do software development for F6800, F6801,
F6802, and F6803 CPUs on their own systems. The cross·
assembler software package is compatible with both the
Motorola and Fairchild language syntax. Useful features
similar to those of the 8080/8085 Assembler are included
to provide systems compatibility.
S"tom
NN = without cross·assembler
The assembler accepts the user's source program as
input and translates it into machine·executable code.
Relocatable object modules are linked together into load
modules and then into execution modules under the
ISIS-II operating system. Application programs can then
be downloaded in a formatted form through a serial port
to the PEP 68 System's on-card memory. Now the
program can be exercised and debugged using the
FAIRBUG/68 debug monitor.
specifies CPU type
8 = 6802/6808 CPU or
9=6809 CPU
for Intel MDS systems
(single density floppy disk)
for Intel MDS systems
(double density floppy disk)
•
•
•
•
•
•
•
9-24
680X Cross·Assembler Software Package
Intellec 800 and 888 Series II Compatible
Full Macro Capability
Expanded Relocation Capability
Expanded Assembler Directives
Comprehensive Conditional Assembly
Includes Logical, Comparative, and Expression
Truncation Operators
PEP F387X
Formulator
Microprocessor Product
Description
A single-board microcomputer for program development
timing, debugging, and emulating the F387X family of
single-chip microcomputers, the PEP F387X system
includes an F38E70 EPROM microcomputer programmer,
an on-board keypad, address and data displays. A 40·pin
emulation cable is also provided.
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Full In-Circuit Emulation of the F3870 and F3872
Microcomputers
On-Card Keypad for Command and Data Entry
On-Card 7-Segment Address and Data Displays
Programming Sockets for F38E70s and 2716s
2K Bytes of 2114 Static RAM Plus Space for an
Additional 2K Bytes
Space for 6K Bytes of 2716 EPROM
2K-Byte Firmware Monitor
Flexible Memory-Map Strapping Options
Crystal-Controlled System Clocks
Four General-Purpose Programmable Timers
Four General-Purpose Interrupt Controls
Current-Loop and EIA RS232C Serial 110
Spare 8-Bit 110 Port
Requires Only + 5 and + 12V Supplies
II
9-25
PEP F387X
9-26
Software Packages
Microprocessor Product
convenient and powerful programming debug facility to aid
in the development of F8 or F387X programs. The debugging program provides the user with an interactive system
via a teletype terminal or via a 4 x 6 keypad. This is the
standard debugging aid provided with the PEP 387X
development board.
Several software packages are offered by the
Microprocessor Division for the system developer. A brief
description of each one follows.
F8 Formulator Disk Operating System Version 4.0 (DOS4)
The Formulator Disk Operating System version 4.0 (DOS4)
provides the F8 or F387X system developer with a complete
set of tools for software development including source program editor, relocatable assembler, linking loader and in·
teractive debugger. Also included are many utilities for effi·
cient use of the floppy disk subsystem and support for a
number of other standard peripherals. The DOS4 is an im·
proved and streamlined version of the F8-D03 with added
capability and greater ease of use.
Minicomputer F8/F387X Cross Assembler
The Fairchild F8/F387X Cross Assembler is deSigned for
use on any 16-bit word length minicomputer with an ANSI
FORTRAN IV Compiler. The Cross Assembler is indepen·
dent of machine character representation and numerical
representation. Minor alterations may be required to satisfy
various Computer/Operating System/Peripheral
Device combinations.
FAST Software Debugger
Installation and modification of this program should be per·
formed by a programmer who is quite familiar with
FORTRAN IV and with the hardware and software con·
figuration of the target computer. Under such circumstances, installation can probably be completed in one
or two days. .
The FAST software debugger (FSD) is a fast software
debugging monitor for F8/F387X microcomputer systems
programs. Its speed and ease of use meet or exceed any
other method of debugging F8/F387X programs.
The FSD is designed for use with the Fairchild F387X programming, evaluation, and prototyping (PEP) board. It
replaces the PEPBUB monitor chip provided with the board
and allows all operations to be performed through a CRT
terminal rather than through the PEG BUG keypad. It does
not support parallel paper tape I/O.
F9445 BASIC Language Package
FAIRBUG
A special Debug ROM 3851A PSU provides the F8 user with
a convenient and powerful programming debug facility that
is used in the development of F8 programs. This debugging
program (FAIR-BUG) provides the user with an interactive
system via a teletype terminal. The following capabilities
are provided:
Display or Alter Memory locations
Display or Alter Scratch pad Registers
Display of Alter Accumulator, ISAR,
Status I.Y'I Register)
Display or Alter PCO, DCO, DC1
Load Formatted Paper Tape
Punch Formatted Paper Tape
Punch Paper Tape in PROM Format
Entry from Keyboard or by Program Instruction
I/O Subroutines available to user
F8/F3870 PEPBUG
A special F38T56 PSU with a debug monitor (PEPBUG 38)
has been developed by Fairchild to provide the user with a
9·27
The Fairchild BASIC language interpreter for F9445·based
systems is specifically tailored to high-performance
microcomputing, providing a powerful, interactive programming language that can be used to solve a wide range of
application problems. It incorporates extensions of and
modifications to the BASIC language originally developed
at Dartmouth College. The Fairchild enhanced BASIC increases the capability and flexibility of the language with a
complete set of data types, additional statements and functions, comprehensive data management facilities, file
management an I/O control and multi-dimensional array
capabilities. Interface to custom F9445 assembly language
programs is also provided. The BASIC language is fully sup·
ported by the F9445 Interactive Multi-User Disk Operating
System (1M DOS), which allows full use of the extensive
operating features of IMDOS, such as independent I/O and
the ability to dynamically create, access, and delete files.
F9445 PEP BASIC Language Package
The Fairchild PEPBASIC, deSigned to reside in a 2K PROM,
retains the essential simplicity and computational power of
BASIC. PEPBASIC provides a unique capability to extend
and customize programs, either through enhancements
written by the user in F9445 absolute assembly language.
Versatile applications like real·time process control, data
acquisition, or math packages can be created, based on the
general-purpose facilities available within PEPBASIC.
II
Software Packages
To time an instruction, a short loop containing the instruction is executed and its time lapse cOl11pared to a null (no
instruction) loop, during the transmission of one character.
The 110 terminal displays the resulting times. The user
specifies the Baud rate of the I/O device at program
execution time in reponse to a program prompt.
F9445 PEPBUG Package
The Fairchild F9445 PEPBUG package is the interactive entry and debugging software for use with the F9445 family of
microprocessor products. The PEPBUG 45 software
package creates a versatile and efficient control environment, enabling the user to enter and test F9445 absolute
assembly language programs interactively. It is unique
among the programs offered with the F9445 family in that it
gives the user control of the microprcessor through a video
terminal, provides many different capabilities in a single
stand-alone mini-executive program, and occupies a
relatively small amount (2 thousand bytes) of memory
space.
F9445 MICRO FORTRAN Language Package
The Fairchild MICROFORTRAN package is a ligh-Ievel
language compatible with the F9445 microprocessor based
family of products, providing a powerful tool for structured
program development. Subroutines and fUnctions are independently compiled, and translated into relocatable object modules that can be linked in any combination,
according to commands given at load time. Interface to
custom F9445 assembly language subroutines is provided.
F9445 PASCAL Language Package
The Fairchild F9445 PASCAL package is a high-level
language suited to the development of microcomputer software because of its strong and logical control structures
and its versatility in handling data. Fairchild PASCAL is
designed to solve complex problems using such modern
language concepts as variable data types, including
records, sets, scalars, and others. Interface to custom
F9445 assembly language subroutines is provided.
F9445 Diagnostics Package
The basic diagnostic package for the Fairchild F9445 family
of microprocessor products contains seven programs: a
memory address test, a memory test, a system exerciser, a
memory diagostic, and three F9445 instruction set tests.
These disk-based programs enable the user to identify and
isolate faults in the CPU, memory, and certain I/O subsystems of F9445-based systems. Versions of several of the
tests also test the Fairchild System-I (FS-I).
PASCAL offers highly structured techniques for organizing
and coding programs so that they are easily understood
and modified, which allows cost-effective software
development.
F9445 Interactive Multi-User Disk Operating
.
System (IMDOS)
F9445 Instruction Timer
The Fairchild F9445 Instruction Timer (fIMER45) software
operates in the F9445-based systems, reporting the time
needed to execute each class of CPU instruction. It uses
the I/O terminal device as the standard to measure the
times and report the results. The timer is most useful for
detecting the execution speeds in mircroseconds for over
60 representative instructions, to optimize the design of
F9445-based systems. It also serves as a diagnostic tool in
detecting clock drift.
The Fairchild F9445 Interactive Multi-User Disk Operating
System (IMDOS), customized for high-performance
microcomputer systems, offers extended file management,
timesharing, device-independent input/output, system processors such as MACRO assembler and a utility library.
F944T PASCAL, F9445 BASIC, and MICRO FORTRAN compilers, are also fully supported. IMDOS is also the principal
operating system for the Fairchild System-I (FS-I)
9-28
I[!]
!INTRODUCTION
~2 !ORDERING AND PACKAGE
~ INFORMATION
I[ ! ] ! Fa MICROCOMPUTER FAMILY
1 0 I CONTROLLER FAMILY
1~IF6aoo MICROPROCESSOR FAMILY
10!F16000 MICROPROCESSOR FAMILY
I~! ROM PRODUCTS
InIg I DEVELOPMENT SYSTEMS AND
L!.J SOFTWARE
I[!IJ!RESOURCE AND TRAINING CENTERS!
I@]
I SALES OFFICES
Section 10
Applications
10-3
Applications
10·4
A Matrix Printer Controller
Using The F8 and
F3870 Circuits
The multi-chip F8'" microprocessor and single-chip F3870
MicroMachine'"2 microcomputer have become popular circuits for control applications. Inexpensive and easy to use,
their instruction sets and architecture combine to give the
modern system designer NMOS LSI power and flexibility.
memory size increases.
The F8 microprocessor can address up to 64K bytes of
program and data storage. Each peripheral controller can
easily be implemented as a subroutine within the PSU and,
depending upon the desired configuration, the required PSU
can be plugged in to provide a modular, flexible system.
The architecture of the F8 microprocessor is designed to
implement I/O-intensive applications. The memory addressing registers, the 16-bit program counter, and the data counters are located in the Program Storage UnitWSU). The PSU,
as well as the other F8-system peripheral circuits, is driven by
the Central Processing Unit (CPU) with micro-instructions
communicated over the five control lines (ROMCo-ROMC4)
and is synchronized by a Write signal. The unusual partitioning of the CPU and PSU chips frees many pins normally
needed for address bussing foruse as I/O lines and provides
room for a 64-byte scratch pad memory on the CPU chip. No
matter how much memory is contained in the system, the
number of I/O lines remains fixed at 16; therefore, the number of pins available for useful functions does not diminish as
The F3870 MicoMachine2 is a complete8-bit microcomputer
on a Single MOS integrated circuit. It features 2048 bytes of
ROM, 64 bytes of scratchpad RAM, a programmable binary
timer, 32 bits of I/O, and has a Single +5 V power supply
requirement. The F3870 can execute the F8 instruction set
and can easily be interfaced with any microprocessor system
through the I/O ports by properly defining command, status,
and data lines, making it a universal controller.
MATRIX PRINTER CONTROLLER
A matrix printer controller can be constructed using either
the F8 microprocessor (Figure 1) or the F3870 microcom4.7 k
3851 lK )( 8 PSU'
"V~
HOME
DATA
BUS
ROMCoROMC4
r
¢
¢
~
:i'
-.
WRITE _ 7
TO/FROM
20
l·
2N4401
=
REV
TRIAC
CIRCUITS
FWD
"
CPU
DBDA _ 1 1
-. I,:
_10
-.
-,
l" } r-
~
2
25
7
~
INC-
INO-
r
TIP 30
~
INB-
24
--.J
4.7 k
LINE FEED
V
t~OO,.}
OUT B
9667
t--0UTC
DARLINGTON -
DRIVER
OUT 0
-
7
---;7""--
-
-
31
INE-
!-OUT E
-
36
IN F -
I-0UT F
-
37
ING-
-OUTG
.-
'Other PSUs available are the 3856 (2K x 8 with 1/0) and the 3857 (2K x 8 with address bus).
Fig. 1 Matrix Printer Controller Using the Fa Microprocessor
10-5
MATRIX
PRINTER
F3870
MICROCOMPUTER
- ['
.
4.7 k
+.~
HOME
P1,
2N4401
3'
Ph
READ STATUS
P1,
CLEAR BUFFER
,
.
"1
3.
2.
~
~
20
~
"]. l·
P1s ..
P1,
LOAD BYTE
DATA BUS
(1/0 PORT 0)
BIT
COMMAND
BUSY
READ STATU s
LOAD BYTE
TRIAC
CIRCUITS
FWD
+5V
23
1:r
j
r
. ,.
l: }
~
~
L
{""-
INB-
24
INC-
I-OUT B
rOO"}
ro""
INE-
9667
DARLINGTON
OUTD
r
DRIVER
rOUT E
3.
INF-
rOUT F
37
ING-
r
7
31
7
'"
MATRIX
PRINTER
4.7k
2 LINE FEED
22
<=>
REV
'"
P16 ..
LINE FEED
=
~
IND-
r
-
,
~
OUTG
-
-
,-
LINE FEEO
PRINT
ClEA~
BUFFER
Fig. 2 Matrix Printer Controller Using the F3870 Microcomputer
puter (Figure 2). In the F3870-based controller, the following
com mands are used to perform the control functions:
used to hold the gate current off and provide a low-impedance path to ground. This provides good noise immunity to
prevent turn-on of either triac by noise.
CLEAR BUFFER - stores zeroes in the 40-character print
buffer contained within the scratch pad RAM.
SOFTWARE DESIGN
The matrix printer controller software can easily fit within a
3851 PSU with 1K x 8 bits of ROM and 16 I/O lines.
PRINT - causes the contents of the print buffer to be
printed. Error status if the head motion is not correct.
The timing can be done by software loops without using the
timer. This is the easiest technique, but suffers from the
drawback that the whole system is tied up during the printing
of an entire line. A more sophisticated technique, employed
in many real-time control systems, is to make each timing
control event a discrete event entered into a table controlled
by the real-ti me monitor.
LINE FEED - advances the paper to the next line.
LOAD BYTE - takes a byte from the data bus and places it
next in the print buffer. Error status if the buffer is full.
READ STATUS - places the status on the data bus and
clears the status byte. The status is held on the bus until the
command is taken away, at which time the port is cleared
for reading again.
The software has three entry points:
The initialization entry point (address H'OOB1'l, which fires
the reverse triac, turns off the paper-feed solenoid, and
returns the print head to the home position.
In all command sequences, the F3870 microcomputer presents BiJSY until the command has been performed or until
status is stable on the data bus.
The line-feed entry pOint (address H'OOCFl, which energizes the paper-feed solenoid for 30 ms and then turns off
the solenoid.
The current requirements of the matrix printer solenoids are
met by a suitable driver, such as the 9667 Darlington driver
circuit with seven drivers and built-in back-emf suppression
diodes. The 9667 interfaces directly with the F8 microprocessor and F3870 microcomputer ports.
The print entry point (address H'0065'l, which fires the
forward triac, prints the line of characters, fires the reverse
triac, and then does a paper feed.
The line-feed drive solenoid is implemented as a pnp power
transistor (TIP 30), the base drive of which is supplied directly
from the I/O port. The HOME phototransistor in the matrix
printer supplies base current to a simple 2N4401 npn transistor, which saturates, providing the Home signal to the controller. The forward and reverse triac drives are provided
across 100 n resistors from +5 V (Figure 3). A TTL gate is
Access to this software is accomplished by loading the
registers with the required parameters and executing a "call
to subroutine immediate" (PI) instruction to the appropriate
entry pOint.
The subroutines to control the matrix printer head motion
10·6
'5 V
100
n
MOTOR
WINDING
75451
FWD
(FROM CONTROLLER)
----t>o-+-------
~}--28V.C
MAC 92·2
Fig. 3 Forward Triac Interface Circuit
and printing functions are listed in the appendix. These
would be used alone in a 3851 PSU with other F8 system
circuits or as part of an F3870 universal controller. The
control program for the F3870 microcomputer and its subroutines are listed in the appendix.
the status register. A test for minus then detects when Home
becomes false:
INS
BP
*-1
INPUT & SET STATUS
LOOP UNTIL "HOME" IS FALSE
However, it must be determined if the forward motion fails for
some reason. Therefore, the system does not loop indefinitely but, rather, sets up two counters and waits only 1.5
second, see program segment A.
FORWARD MOTION CONTROL
The forward triac is fired by setting bit 1 in output port 5:
LIS
OUTS
5
2
5
PRINT SOLENOID CONTROL
Once the Home indications goes false, the system fires the
print solenoids, waits 650 P.s, turns off the solenoids, and
waits 700 p'S for each of the five columns forming thecharacter, see program segment B.
All other bits in port 5 should be cleared so that it is not
necessary to OR bit 1 to the port. The Home signal is connected to port 5 bit 7 and active High <+5 = Hamel. This makes
use of the fact that the F8 system input instructions also set
Segmeni A
PRDR20
CLR
LR
LR
INS
BM
OS
BNZ
OS
BNZ
CLR
OUTS
LIS
LR
BR
O,A
1,A
!RDR30} 24 P.s x 256 }
= 5.S ms
o
1.5 s
PRDR20
1
PRDR20
5
2
ERR,A
TURN OFF FWD TRIAC
SET ERROR FLAG
EXIT
Segment B
PRDR30
LM
OUTS
II
INC
BNZ
CLR
OUTS
II
INC
BNZ
OS
BNZ
LOAD FIRING PATTERN
4
186
*-1
Sp.sx70
= 630 P.s
4
180
9
*-1
EOC
PRDR30
p'S
645 P.s "ON TIME"
}
698 "
x 76
= 684 P.s
10·7
}
"OFF TIME"
REVERSE MOTION CONTROL
The forward triac is turned off and a 10-ms delay initiated to
allow sufficient time for the triac to stop conduction (one-half
cycle is 8.3 msl. The reverse triac is then fired and the
program loops until Home becomes true. Again, there is
some error control in the event that something prevents the
print head from returning to the home position, see program
segment C.
is loaded from the table, the address is incremented by one,
pointing to the next value in the table.
The table is organized so that the first bit pattern is addressed
by pointing to the beginning of the table and adding the
ASCII character to the data counter five times:
DCI
ADC
ADC
ADC
ADC
ADC
LINE FEED CONTROL
The line-feed solenoid can be turned on for only 30 ms;
beyond that time, damage may be done to it. Setting bit 7
turns on the solenoid:
LI
OUTS
LIS
LR
OS
BNZ
DS
BNZ
CLR
OUTS
H'80'
4
10
1,A
0
'-1
1
'-4
}
TABLE ADDRESS
POINTS TO
THE Nth
ENTRY IN A
FIVE-BYTEWIDE TABLE
Since the first 32 ASCII characters are not used in this matrix
printer, the actual program subtracts 32 from the ASCII
character before adding it to the data counter five times.
TURN ON SOLENOID
}
4
BIT PAT
30 ms DELAY
CONCLUSION
The F8 instruction set has been shown to be ideal for control
applications, such as the matrix printer controller described.
Of particular note are the input/output instructions that set
status, and the table look-up instructions that allow fast
access to tables of any length and do not place any constraints on the location of tables in memory.
TURN OFF SOLENOID
CHARACTER SET TABLE
Accessing tables of data with the F8 microprocessor and
F3870 MicroMachine 2 microcomputer is easy and efficient.
The data counter is loaded using the "load dc immediate"
(DCD instruction. The "add accumulator to data counter"
(ADC) instruction allows a signed 8-bit value contained in the
accumulator to be added to the data counter. When the data
The F3870 microcomputer has been shown to be ideal for use
with any microprocessor system as a universal peripheral
controller. This is accomplished by interfacing through the
input/output ports, which gives the system designer great
flexibility in his system configuration.
Segment C
PRH010
PRH020
CLR
OUTS
LIS
LR
DS
BNZ
DS
BNZ
LIS
OUTS
CLR
LR
LR
INS
BP
DS
BNZ
DS
BNZ
LIS
LR
LIS
LR
DS
BNZ
DS
BNZ
CLR
OUTS
TURN OFF FWD TRIAC
5
3
1,A
o
'-1
1
'-4
}
10 ms DELAY
TURN ON REVERSE TRIAC
1
5
CLEAR COUNTERS FOR TIMEOUT DELAY
O,A
1,A
5
PRH020
~RD010
PRH010
1
ERR,A
3
1,A
o
'-1
I
I
1,5 sTIMEOUT
SET ERROR STATUS
10 ms DELAY
'-4
TURN OFF REVERSE TRIAC
5
10·8
APPENDIX
FORMULATOR FDOS ASSEMBLER (REV 2.0)
RS
SOURCE STATEMENT
LOC OB-JECT AIIDR LINE
0001 • MATRIX PRIhTER CONTROLLER
0002
0003 • D. R. HOLLINBECK
0004 • FAIRCHILD MOS MICROCOMPUTER
•
0005
0006
0007
000:::
000';"
0010
0005 0011
0004 0012
0003 0013
001:3 0014
0004 0015
OOFB 0016
0017
001:3
70
0019
EO
0020
Bl
2:300Bl OOBI 0021
0000
0001
0002
0003
000':", 55
0007 54
•
•
•
•
•
THE UNIVERSAL CONTROLLER CONTROL
PROGRAM IS GIVEN FIRST WITH THE
SUBROUTINES AND BIT PATTERN TABLES
FOLLOI.oJING
•STATUS-
EOU
EOU
EOU
'5
B'/TES
EOC
BUFFER
BUS..,.'
t-iBUSY
EOU
EOU
EOU
0-
•
CLR
OUTS
OUTS
PI
LR
LR
0022
002.3
0024
00,::5
0026
0027
••
4
::
100'-40 START OF BUFFER
B-- 00000100 - -- BU-S:'/-- BIT
B--- 11111011-- r-mT --BUS""'-" BIT
0
1
PRHOME
STATUS.A
BYTES.A
HE
000:3 002:=:
BZ
i':DC~1D
OOOE: '313C
0048
002':;-
B~1
0030
005C 00:31
B~1
CLF.:BUF
1
PRINT
00.32
SL
1
002A 00:33
0034
003:3 0ln5
BM
SL
Bt'1
LINEFD
1
LDB'/TE
1-'"--'
914D
1:3
911:3
1:3
911E
00:36
0037
0016
0017
001:3
0019
001B
001C
001D
001F
0021
45
BO
Al
'2204
Bl
Al
210:3
94FC
70
0022 BO
002:3 55
0024
0025
0027
002:3
Al
21FB
Bl
90DF
002A Al
002B 2204
00:3'3
00.39
0040
0041
0042
0043
0044
0045
001C 0046
0047
004:3
0049
0050
0051
0052
005:3
0054
0055
000:3 0056
0057
005:3
0059
0060
0061
SL
•
•
•
Fi:EAD STATUS
• LINE
•
•LINEFD
TEST BIT 6
TEST BIT '5
TEST BIT 4
Cm1~1AND
A,STATUS
HE
01
1
BUSY
HIS
1
1
NI
BNZ
'::LR
OUTS
LR
B'00001000' WAIT FOR COMMAND
.-:3
TO GO AWAY
CLEAR STATUS AND PORT
0
S:TATUS, A
ours
•• CLEAR
•CLRBSY
I.o.IAIT FOR '::OMMA~m
TEST BIT 7
LF.:
OUTS
GET STATUS FROM SCRATCH PAD
(I
SET 'BUSY'
BUSY STATUS
HiS
NI
OUTS
BR
1
NBUS'/
1
RDCMD
RESET 'BUSY'
I,JAIT FOR ANOTHER COMMAND
FEED COMMAND
INS
or
10·9
--~----
CLEAR ACCUMULATOR
ALLOW READING OF PORTS
(I AND 1.
INSURE HEAD IS HOME
CLEAR STATUS
AND BYTE COUNTER
READ COMMAND STROBES
•RD'::MD
000:3 Al
0009 :34FE
DODD
OOOE
0010
0011
001:3
0014
HATU-S: BYTE
NUMBER OF BYTES TO PRINT
COUNTER FOR END-OF-CHARACTE
SET 'BUSY'BUS'/
II
APPENDIX
FORMULATOR FDOS ASSEMBLER (REV 2.
R"~
.::,
SOURCE STATEMEtlT
LOC OBJECT AD DR LItlE
002D Bl
0062
002E 2:300CF OOCF 0063
0031 '30F2
0024 0064
0065
0066
0067
003:3 201:3
006>3
0035 C4
0069
0070
0036 2540
00.3:3 9407
0040 0071
0072
007:3
00'74
0075
45
0076
228S
0077
55
'30E5
0078
0024 0079
00:30
00'31
00'32
00:33
00:34
003A
00:3.B
00:3D
003E
0040
0041
0042
0043
0044
0045
0046
OB
AO
5C
44 .
IF
54
90IlD
004:3
0049
004B
004C
004E
004F
0051
0052
0053
0054
0055
0056
0057
005:3
005A
005C
005D
005F
0060
00';3
00:3'3
00'30
0091
0092
00'33
00'34
Al
2204-
Bl
2028
54
201:3
OB
70
5C
OA
IF
OB
34
'34F9
90C9
OUTS
PI
BR
• TRANSFER
•
•
LDBnE
LI
0052
0024
Al
2204
Bl
2:30065 0065
0024
90CO
1
LFOO
CLRBSY
•
•
•
•
B~IZ
•
LF.:
OI
LR
BR
POINT TO NE:':T EMPTY
BYTE HI BUFFER
CHECK: IF BUFFER FULL
A. STATU'~: I:;ET STATUS BYTE
B'"1 0001 000"
~:ET ERROR FLAI:;S
S:TATUS. A
'::LRBSY
LR
IS.A
I ~'I':::
(I
LR
LF.'
INC
LR
BF.'
.S:,A
A.BYTES
LOAD IS:AR
GET DATA
STORE ItHO 'SCRATCHPAD
INCREt1ENT COUNTER
B'/TES. A
'::LF.'BSY
':LEAR PRItH BUFFER cm1MAt'!II
•
CLRBUF
INS
or
OUTS
LI
0095
LR
0096
00'37
(1)'3:3
00'3'3
0100
0101
0102
0103
0104
0105
0106
0107
010'3
0109
0110
0111
0112
0113
LI
CLRBI0
LF.:
CLR
LR
LR
me
LR
rc
•
BUFFER
BYTES:
0"100"
LDBYI0
ERROR - SET BUFFER FULL STATUS (BIT 3)
AND ERROR FLAI3 (BIT 7) .
•LDBYI0
•
'3D DO LINE FEED
CLEAR "BUSY" AND I.,JAIT
BnE INTO PRINT BUFFER
AS
CI
00:35
00:36
0024 00:37
OO:3S
f '.
(I)
• PRINT
•PRINT
BNZ
BR
BUS..,.'
1
40
BYTES.A
BUFFER
IS-A
S,FI
A. IS:
IS.A
BnES
CLRBI0
CLRBS'l'
BUFFER COt1MAND
INS
or
OUrS:
PI
BR
10·10
BUSY
1
PRDROO
CLRB.SY
SET "BUSY'"
40 B'/TES TO CLEAR
GET nAFHING ADDRESS
At~D PUT INTO EAR
CLEAR ACCUMULATOR
STORE 'I"IA EAR
INCREMENT ISAR
APPENDIX
FORMULATOR FDoS ASSEMBLER (REV 2.0)
RS
SOURCE STATEMENT
LoC OBJECT ADDR LINE
0114
0115
0116
0117
011a
011';1
0120
0121
0122
0065 oa
006611
012.3
0124
0125
0067 72
0068 B5
0126
0127
0069
006Ft
006B
006D
006E
0071
10
012a
16
0129
24EO
0130
11
0131
2AOOEO OOEO 01.32
aE
01.33
0134
0072 aE
0135
0073 BE
01.36
0074 ;3E
0075 ;3E
01T(,
0076 70
013'::
01::;"
0140
0141
0142
014.3
0077 50
007a 51
007'3 75
(107A 5.3
(lOlB AS
007C 910F
007E 30
007F 94FB
ooa 1 31
00;::2
00:34
00:35
00:36
94Fa
70
B5
45
00.37 22;32
00:39 55
OO.3A ';"027
00;3C
OO'::D
OO'::E
0090
0091
16
B4
20BA
1F
94FE
00'33 70
0094 B4
00:l5 20B4
00';17 IF
009;:: 94FE
009A 3.3
009B:l4FO
009D 2074
009F IF
OOAO 94FE
OOA2 .34
OOA'3 94C5
OOA5 70
OOA6 B5
OOA7 7.3
ooa,:· 0144
0145
007B 0146
0147
007B 014;::
0149
0150
0151
0152
0153
00B2 0154
0155
0156
0157
015:3
0090 015·:l
0160
0161
0162
016.3
0(1":l7 0164
0165
ooac 0166
0167
016:3
OO·:lF 0169
0170
0069 0171
0172
0173
0174
EJECT
•
•
•
•
•
•
••
MATRIX PRINTER DRIVER
D. R. HoLLINBECK
FAIRCHILD MoS MICROCOMPUTER
MAIN PRINT ENTRY POINT
•PRDROO
LR
LR
i...IS
PRDR10
OUTS
LR
LM
AI
L.R
F'RDR20
DCI
ADC
-=tD'::
ADC
AD,::
ADC
CLR
LR
LR
LIS
LR
INS
B~1
H,DC
2
5
DC,H
SAVE RETURN ADDRESS
SAVE DCO
FIRE FORWARD TRIAC
RESTORE LIST POINTER
GET NEXT CHARACTER TO PRINT
·-32
H,DC
BITPAT
SA',lE D'::O
POINTER TO PRINT TABLE
DCO = DCO + '5 • (ACC)
THIS GET; ·THE PROPER ENTRY
IN A FI~E BYTE WIDE TABLE.
I),A
1, A
5
INITIALIZE DELAY COUNTER
INITIALIZE ERROR CODE
LOAD NEEDLE FIRING COUNTER
s
LOOK AT 'HOME' LED INDICATD
PRDR30
D;
0
BliZ
;:'RDR20
D~;
1
BI'iZ
PRDR20
I::LR
PRDR30
OUTS
LR
01
LR
BR
LM
OUTS
LI
S
S:TATIJS
B'10000010'
S:TATUS, Ft
PRH005
TURNOFF TRIAC'S AND EXIT
GET NEEDLE DRIVER BITS
FIRE DRI\IERS
bJAIT 650 MICROSEcmms
Ft.
HK
BNZ
CLR
.-1
RESET NEEDLE DRIVERS
LJun:
u
INC
BNZ
DS
BNZ
LI
DELAY 700 MICROSECS
.-1
EOC
PRDR30
116
TEST END-OF-CHARACTER
GET NEXT BIT PATTERN
DELAY 1350 MICROSECS
HK
BNZ
DS
BNZ
CLR
OUTS
LIS
10·11
·-1
B'lTES
PRDRI0
TEST FOR END-OF-LINE
GET NEXT BYTE TO PRINT
TURN OFF FORWARD TRIAC
5
.3
DELAY 10 MILLISECS
II
APPENDIX
FORMULATOR FDOS ASSEMBLER (REV 2.0)
RS
SOURCE STATEMENT
LoC OBJECT ADDR LINE
00A8 51
00A'3 .30
OOAA 94FE
OOAC .31
OOAD 94FB
OOAF 9002
OOA9
OOA'3
OOB2
OOBI oa
OOB2
OOB3
OOB4
OOBS
OOB6
00B7
oOB'3
OOBA
OOBB
OOBD
OOBE
oDeD
71
B5
70
50
51
A5
:::1 OB
30
94FB
.31
'34Fa
45
00C4
OOB7
ODE7
0176
0177
017a
017'3
0180
01'31
0182
01a.3
01:34
01as
01:36
01:37
018a
01:3'3
01',0
01'31
01'32
01'33
01',4
01',5
01'3'6
01'3'7
01'38
01'3'3
0200
0201
00(:1 22:31
0202
00(;3
00C4
00C5
00C6
00C7
00C9
DOCA
OOCC
OOCD
OOCE
0203
0204
OOCF
OODO
OODI
00D2
00D4
OOD5
00D6
OOD7
00D8
OODA
OODB
OODD
OODE
OODF
55
?3
51
30
'34FE
.31
'34FB
70
B5
OC
oa
LR
DS:
BNZ
DS
BNZ
BR
0175
•PRHOOS
PRH010
PRH020
1
020';:,
00C6 0207
020:3
00C6 0209
0210
0211
0213
0214
0215
0216
1
.-4
PRHo05
•
• INITIALIZATION ENTRY POINT.
•
ENTER HERE AT THE START OF THE MAIN PROGRAM
•
JUST TO ENSURE THAT THE PRINT HEAD IS HOME.
.•
PRHOME
LR
SAVE RETURN ADDRESS
•
• ENTER HERE TO RETURN PRINT HEAL HOME
020 5
0212
I,A
0
.-1
LIS
OUTS:
CLR
LR
LR
O,A
1, A
HE
:5
BF'
?RH020
IIS
0
Bi'iZ
?RH010
DS:
1
BNZ
LR
01
LR
PRH010
LE
3
LR
DS
BNZ
DS
BNZ
CLR
1, A
OUTS
•• LINE
•LFOO
FIRE REVERSE TRIAC
:5
A, S:TATUS.
B'10000001' HEAD DID NOT RETURN HOME
;:TATU;,A
0
1
.-4
:5
P~:
LR
CLR
B5
20ao
B4
7A
51
30
'34FE
31
'34FB
70
B4
oe
021:3
021'3
0220
Dun
0221
0222
LIS
10
LF.:
1. A
0225
OOD7 0226
0227
TURN OFF
REV TRIAC
RETIJRN
FEED ENTRY POINT
0217
0223
DELAY 10 MILLISECS
.-1
10
00Il7 0224
'.,IA I T FOR "HOME"
Dun
LI
DS
BNZ
D:S
BNZ
CLR
0228
ours
022'3
PK
10·12
TURN OFF TRIAC'S
5
1"1"':30'
FIRE LINE FEED
4
DELAY .30 MILLISECS
o
.-1
1
.-4
TURN OFF LINE FEED
4
RETURN FROM SUBROUTINE
APPENDIX
FORMULATOR FDOS ASSEMBLER (REV 2.0)
RS
SOURCE STATEMENT
LOC OBJECT AD DR LINE
0230
02:31
0232
02:3.3
OOEO
OOEl
00E2
OOE:3
00E4
00
00
00
00
00
0234
02:35
02:36
0237
02.3::::
02~3'3
OOE5
00E6
00E7
OOE:3
OOE':;'
00
00
7D
00
00
OOEA
OOEB
OOEC
OOED
OOEE
00
60
00
60
00
OOEF 14
7F
14
00F2 7F
OOF.3 14
oOF 0
oOF 1
12
2A
7F
2A
24
DC
DC
H'" oq···
H'" 00'"
DC
W' 00'"
0245
0246
H'" 00'"
H'" 00'"
7D"
00'"
H'" 00"
H
H'"
H'"
00'"
H' 60'"
H'" 00 , '
H' 60"
024::::
024'3
H'"
00'"
•
DC
DC
DC
DC
DC
H'14'
H' 7F'"
H'l4'
DC
DC
DC
DC
DC
W12"
H" 2A'"
H7F'
H'14 "
•
025'3
0260
0261
0262
0263
W7F'
2A"
H' 24"
H'
•
H'- t:,2'"
64
oa
0264
0265
0266
DC
DC
DC
1:3
2:3
0267
02t=.:.:::
liC
Wl3'
DC
H" 2.3'"
OOFE :36
0270
0271
DC
DC
DC
DC
DC
H" .36'"
OOFF 4"'.1
0100 35
0101 02
DC
DC
DC
DC
DC
H'" 00'"
W6:3'"
DC
DC
DC
DC
DC
H'" 00'"
H"'lC'"
W24"
W42"
H'" 00'"
DC
DC
DC
H'" 00'"
H" 42"
OOF9 62
OOFA
OOFB
OOFC
OOFD
026'3
027.3
0103 00
0104 6:3
0105 70
027:3
0106 00
01 07 00
010e
010"'.1
010A
010B
010C
00
1C
24
42
00
02::::3
0284
0285
010D 00
OlOE 42
010F 24
02:3:3
02:39
02'30
02:36
02:::7
H 4',"'H" 35'"
W02"
H'"
os'"
•
0279
02:::0
02':: 1
02;32
H 64'"
H'" 0:::: ,,'
•
0272
0274
0275
0276
0277
0102 05
••••• •
(! )
••
••
(")
•
0247
0250
0251
0252
025.3
0254
0255
0256
.: )
•
0240
0241
0242
0243
0244
0257
OOF4
OOF5
00F6
OOF7
oOF::::
E,JECT
•
• TABLE OF BIT PATTERNS FOR CHARACTER SET.
+
BITPAT
DC
H'OO'
DC
H" 00"
W70'"
H'" 00'"
••
•••••••
••
•••••••
• •
• •
•••
•••••••
•••
• •
•• •
•• •
•
• ••
• ••
•• ••
• • •
•• • •
•
••
•• •
•••
<"')
H'" 00'"
•
*
10-13
W24"
•
•••
• •
•
•
•
( ()
•
•
() )
APPENDIX
FIlRMULATDR FDIlS ASSEMBLER (REV 2.0)
RS
S:OURCE STATEMENT
LIlC OBJECT ADDR LINE
0110 lC
0111 00
0291
0292
02 ';:! 3
0294
02';:!5
0296
02 ';:! 7
0298
02';:!';:!
0300
0301
0302
0.3 0.3
0304
0.305
0.306
0.307
0.308
0.309
0.310
0.311
0.312
0.31:3
0.314
0:315
0.31E,
031"?
031 :3
031';:!
0320
0.321
0112
0113
0114
0115
0116
08
2A
lC
2A
08
0117
0118
011';:!
al1A
011B
08
0'3
7F
08
08
011C
011D
011E
011F
0120
00
OD
OE
00
00
0121
0122
0123
0124
0125
08
08
08
08
08
0126
0127
0128
012';:!
012A
00
03
03
00
00
012B
012C
012D
012E
012F
02
04
0:324
08
0326
10
20
0327
0:328
0.329
03.30
0331
03.32
0.3.3.3
0334
0.335
0336
0337
0.338
0.33';:!
0340
0341
0:342
0:343
0.344
0345
0346
0347
0348
0:349
0350
0.351
01.3 0
01.31
01:32
0133
0134
3E
45
49
51
.3E
0135
0136
01.37
0138
013'3
00
21
7F
01
00
013A
013B
01:3C
013D
013E
23
01:3F
0140
0141
0142
22
41
49
49
45
4';:!
49
31
0322
0.32.3
•
•
•
•
•
DC
DC
H'lC'
WOO"
DC
DC
DC
DC
DC
H/08'
H'2A'
W'lC'
H'2A'
W' 08'
DC
DC
DC
DC
DC
0.325
•
•
•
•
W'7F'
•
•••
•••
•••
•
(.}
•
•
•••••••
W' 08'
•
•
DC
DC
DC
DC
PC
H'OO'
H' OD'
H' OE'
H'OO'
H'" 00"
•• •
•••
DC
DC
DC
DC
DC
W08'
DC
DC
W' 00'
m;
•
W' 08'
W08"
•••
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
W08"
W08'
r!"08"
W08"
H' 08"
W51"
W3E"
H" 00'
DC
DC
DC
DC
W21"
DC
DC
DC
DC
DC
H"'2:3'-'
10·14
W7F"
W01 '
H' 00"
H'45'
W'4'3'
H'4'3"
H'31'
H"'22'"
W41'
H'49'
W"49 '
(-)
•
••
••
W04"
H'08'
III:::
DC
DC
DC
DC
•
•
H'" 02"-
W.3E'
H"'45"
H' 4'3'
(, )
•
•
W03'"
H'" 0.3'
H'" 00'"
WOO"
Wl0"
H~' 20'"
(+)
•
•
•
•
(.)
( ..... )
•
•••••
• ••
• • •
•• •
•••••
•
•
•
•
••
•••••••
• ••
• • •
• • •
•• •
• •
•
•
• • •
• • •
(0)
(1)
(2)
(.3)
APPENDIX
FORMULATOR FDDS ASSEMBLER (REV
RS
2.0)
SOURCE STATEMENT
LOC OBJECT AD DR LINE
0143 ,36
0144
0145
0146
0147
014:::
OC
14
24
7F
04
0'352
0.;:53
0.354
DC
DC
H'" OC",
(I ~:55
DC
W14'"
0:::56
DC
DC
DC
H"'24"
Y 7F'"
H' 04'"
H" 72"H 51"
H' 51'
H"' 51'
H" 4E'
0357
I)
3'5'3
•
014'3 72
0-;:60
DC
014A
014B
o14C
014D
0361
DC
DC
51
51
51
4E
o14E
1E
014F 29
0150 49
0151 4';'
0152 46
I)
;:62
DC
DC
I) 3~,;:
0364
03e.5
•
H IE'
'1 2;"
H 4;"
H 4';'
H46
O:::~,6
(1 ;:-:,(
0:::6,::
03-:,'3
0:::7 (I
0371
•
0.;:72
0153 40
0154 47
0.;:7:::
0155 4:::
0374
015':, 50
0157 6 I)
O~:75
H' 40'"
'1'47'
H" 4::: ,,'
W50"
H ':.1)'"
OJ76
0:::77
•
:::r:.
037:::
015'3 4'4
015A 49
015E: 4';'
01Se :::6
DC
DC
03::;:0
03:: 1
DC
o15D
0::,::::
03'::4
0.::::::5
015:::
015E
015F
0160
0161
30
4''''
49
4A
3C
DC
DC
0:::::2
0.;:'3 I)
03;'1
0.;:'32
(1
:::'3:::
(1166
(I
:::34
'1' ::6'
H 4:;'
H'4;'
,j ,
~,.
'1
::,:, ,
H" 30 ",
H'4;"
H ''49
:14A'
rl/ ;:C . '
II,::
H" 00"
H' 3~,
'1
::"""
H'" 00'"
H" 00'"
DC
DC
DC
DC
DC
H'" 00'"
H 6D"
0167 00
03'36
016::: 6D
0169 6E
o16A (I (I
o16B 00
03'37
oe
0402
14
22
41
00
040,::
DC
DC
O,~04
DC
H"1~2'"
0405
0406
DC
DC
W41'
DC
DC
DC
DC
W14'"
W14"
W14'
W14'
DC
'1
016C
16D
016E
016F
0170
o
03'3:::
03'3'3
0400
0401
0407
0171
0172
0173
0174
0175
14
14
14
14
14
040:::
0409
0410
0411
0412
•• ••
••
•
•
••
•••••••
•
••• • .
..
H" ""E"
H'-" 00'"
H'-' 00'"
H'" 00'"
10·15
14"
•
(5)
(e.)
(7)
.. ..
·· .. ...
(':::'
• •.. ••
...
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<'3)
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• • •
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.....
.....
.....
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•• • ••
(:
)
I., ~
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'1", 0,:: ",
•
•
....
•
W14'
•
•• •
• •••
••••
•• •
• • •
• ••
•
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••
••
..
(4.:-
'
••
•
0.;: ::t.
03·::7
0162 I) (I
016:: ::6
0164 ::~,
I) 165 00
0 (I
H"3;:,'"
+
• •
• •
•
•
•
•
•
•
•
•
•
••
•
( <>
(=)
APPENDIX
FDRMULATOR FDOS ASSEMBLER (REV 2.0)
RS
SOURCE STATEMEtiT
LOC OBJECT ADDR LItiE
0176
0177
0178
0179
0171"1
00
41
22
14
08
017B
017C
017D
017E
017F
30
40
45
48
30
0180
0181
0182
0183
0184
3E
41
5D
55
3C
0185
0186
0187
0188
0189
3F
48
48
48
3F
0181"1
018B
018C
018D
018E
7F
4'3
49
49
36
018F
0190
0191
0192
01 '3:3
3E
41
41
41
22
01'34
0195
01%
0197
01'38
41
7F
41
41
3E
019'3
0191"1
019B
01 '3C
01'3D
7F
49
49
49
41
019E
019F
011"10
011"11
011"12
7F
48
48
48
40
011"13
011"14
011"15
011"16
01A7
3E
41
41
45
47
0413
0414
0415
0416
0417
0418
0419
0420
0421
0422
0423
0424
0425
0426
0427
0428
042'3
0430
0431
0432
0433
0434
0435
0436
0437
0438
04.3'3
0440
0441
0442
0443
0444
0445
0446
0447
0448
0449
0450
0451
0452
0453
0454
0455
0456
0457
0458
0459
0460
0461
0462
0463
0464
0465
0466
0467
0468
0469
0470
0471
0472
0473
•
•
•
•
•
•
•
•
•
•
•
DC
DC
DC
DC
DC
H' 00'
H'41'
H'22'
H'14'
H'08'
DC
DC
DC
DC
DC
H'30'
H' 40"
H"45'
H'48'
H'30'
DC
DC
DC
DC
DC
H'3E'
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
W41'
H'SD"
H'55"
H" 3C'
W3F'
W48"
W48"
n'48'
W' 3F'
W7F"
W4',V
W49'
rl'A9"
W36"
DC
DC
DC
DC
DC
W3E'
WAI '
DC
DC
DC
DC
DC
W41 '
DC
DC
DC
DC
DC
W'41'
W41'
H"'22'-"
W7F"
W41"
W41"
W3E"
W7F'
W49"
W49'
H'4'3'
rl'41'
DC
DC
DC
DC
DC
H'7F'
WAS'
DC
DC
DC
DC
DC
W'3E'
H'41'
H'41'
WA5'
10·16
W48"
W48'
WAO'
W47'
•
•
• •
••
•
0)
••
•
• ••
• •
••
•••••
•
•
• ••• •
••••
••••
••••••
' Since different manufacturers have different receiver requirements, the central processing unit will differ from
manufacturer to manufacturer, or even model to model.
The F3870 low-cost one-chip microprocessor with 2K bytes of
on-board ROM, a 54-bit scratch pad RAM, and 32 bits (four 8-bit
bytes) of TTL-compatible input/output is an ideal candidate for
a central processor. The F3870 requires no peripheral devices
except a crystal and power supplies. Using this processor, the
type of control operation is programmed into the ROM at the
factory. With efficient software programming, two or three
programs could be stored in the ROM so that the receiver
manufacturer may offer the same chassis with differentfeatures
and operations.
INPUTS
~
I=-o---
DISPLAY FUNCTION
READOUTS FOR
CHANNELS/TIME, ETC.
ON/OFF
TUNING
BAND/AM/FM
VOLUME
BALANCE
BASS
TREBLE
PHONO
TAPE FUNCTIONS
PROGRAMMING/TIME FREQ
TIME
SET TIME
SET ALARM/ALARM
Television
DODD
DODD
DODD
DODD
DISPLAY FUNCTION
FREQUENCY/TIME
[[]]] •
o0
0 0
...->----+- AM/FM
TAPE FUNCTIONS
Fig. 2 Auto RadIo/HI-FI
I----------------J
Fig. 3 Receiver with Central Processor
10·19
ETC
The microprocessor may also perform additional functions
such as D/A conversion for actually controlling the circuits,
tuning; volume, brightness; color, etc. It could be used as a time
clock capable of being programmed to switch on the receiver at
a given, time and channel. The microprocessor may also act as a
receiver section of a remote control system, ultrasonic or IR, to
decode the signals for a particular function. However, specialized chips are now available that perform the dedicated functions- PLL timing, D/A conversion, etc. - more efficiently than
microprocessors, and work well under microprocessor command.
the line, may be built with almost every imaginable feature by
simply adding the appropriate modular circuit onto the bus
(Figures 5 and 6). Other circuits will be available shortly-an 8channel 6-bit D/A converter, a time clock, and an on-screen
character generator. Each modular chip will have built-in identity code, which is something like a chip select but operates on
data on the data bus. The identity code word is four bits;
therefore, there are 16 possible combinations, but only 15 are
available for use since one is reserved for when no chip is
addressed.
To address a particular chip on the data bus, the correct IDENT
code is placed on the data bus and an IDENT clock on the
control bus. The chip selected is initialized and reset, ready to
accept data from the data bus. The DATA clock on the control
bus clocks the information into the selected chip. The number
STANDARDIZED BUS SYSTEMS
Fairchild adopted a standardized bus system (Figure 4) for
mic'roprocessor-controlled AM/FM and TV receivers. Using
this system, AM/FM and TV models, from low end to the top of
MICROPROCESSOR
ACKNOWLEDGE
Flg. 4 Standardized Bus System
KEYBOARD
0000
DODD
DODD
DODO
ON SCREEN
READOUT OF
TIME AND
CHANNEL
VIDEO
TTT
FEX 2600
ON SCREEN
CHARACTER
GENERAT.OR
DATA BUS
CONTROL BUS
3870
DEDICATED
MICROCONTROLLER
Fig. 5 Microprocessor-Controlled TV with PLL Tuning
10-20
0000
0000
0000
0000
FCM 6020
TIME CLOCK CHIP
7-SEGMENT
DECODER
DRIVER
KEYBOARD
Fig_ 6
Microprocessor-Controlled AM/FM Radio with PLL Tuning
The output frequency of the veo (a varactor local oscillator) is
divided down by the divide-by-n counter and fed into the
frequency/phase detector where the frequency and phase are
compared to a reference frequency. The frequency/phase detector output circuit has three modes~open circuit, or supplying a series of pump-up or pump-down pulse charge~ to
the integrator/amplifier. The output of the integrator/amplifier
supplies dc feedback control voltage to the veo. When the
loop is locked and operating at the desired frequency, the two
frequencies fed into the frequency/phase detector are the same
and of essentially the same phase.
of words required to read a chip depends upon the particular
chip function, and a DATA clock must be generated for each
word. To disable the chip from the bus, the procedure is
reversed. The wrong IDENT code is put in the data bus with an
I DENT clock on the control bus.
PLL TUNING
It has long been realized that the ultimate tuning system is the
phase-locked loop. However, it has not successfully penetrated the consumer market, until recently, due to its stringent
requirements -large complex logic, ability to perform at high
frequencies, system partitioning, and specific system configuration. Simple PLL TV tuning systems accurately tuned to the
FCC channel assignments; however, local problems such as
antenna mismatch, IF misalignment, cable TV problems, etc:,
were often present and required fine tuning or, more accurately, detuning of the PLL system. Therefore, it was imperative to
add the fine-tuning capability, inherent in the old turret tuners,
to the PLL TV tuning system. This complicated the system and
also required some kind of non-volatile memory for storing the
fine-tuning information for each channel.
Under these conditions, the frequency/phase comparator supplies only sufficient charge to maintain loop lock. When the
loop is not locked, the two frequencies at the input to the
frequency/phase comparator differ. The frequency/phase detector supplies a charge of sufficient amplitude and direction to
the integrator/amplifier to generate a voltage for driving the
VCO to a frequency that will cause the loop to lock. Therefore,
the output frequency of the PLL can be written as follows:
Another problem in PLL TV tuning was how to control the TV
receiver, especially in the method of entry from the calculatorboard -whether one or two keys should be used, or an entry
button, and whether the channel display should indicate which
key has been depressed or indicate the channel on the screen.
fvcO = n x fREF
where n is always a whole integer.
Changing the value of the divide-by-n counter changes the
frequency. For example, a tuning system for tuning in 25 kHz
increments requires a reference frequency of 25 kHz.
Now, with the addition of the microprocessor as a central
control unit, the problems of the PLL TV tuning can be simplified and the exact application can be determined by the TV or
AM/FM manufacturer rather than by the semiconductor manufacturer.
Unfortunately, to build a programmable divide-bY-n counterfor
a PLL system that operates at the local oscillator frequencies of
FM and TV receivers is impractical. Therefore, an ECL highspeed prescaler is inserted between the veo and the programmable divide-by-n counter to reduce the counterfrequency. A simple fixed prescaler (Figure 8) places too many compromises on the PLL designer-long loop lock-up times or
BASIC PLL SYSTEMS
A better, more descriptive name for the PLL would be "frequency, phase-locked loop" (Figure 7) because, for the loop to
lock, the frequency must be adjusted first, then the phase.
10-21
0
I,
CHANNEL
SELECTION
CHANNEL
SELECTION
I,
Fig. 7 Basic PLL Clrcuil
Fig. 8 High-Frequency Loop Using Fixed Prescaler
...
, ........----LENGTH' 101 INCHES-----I..
~I
[2Q ~ __
j _,_~~O
NINE 10·INCH BRICKS
III
CJ
T
ONE 11-INCH BRICK
LENGTH: 105 INCHES
11:1
ciP CJ c::=J cj!~ CJ
FIVE 10-INCH BRICKS
FIVE 11-INCH BRICKS
Fig. 9 Brick Analogy
The operation of the system for a total divide-by-n cycle is as
follows. When the program counter reaches terminal count, it
parallel loads both itself and the swallow counter with the
desired divide ratios. The Terminal-Count output of the swallow counter, which is also the prescaler Mode-Control input,
then goes HIGH and both counters begin to count. Since the
swallow counter is smaller, it reaches terminal count first and
stops, causing the Mode-Control input to the prescaler to go
lOW, changing the prescaler modulus. The program counter
continues until reaching terminal count and the divide-by-n
sequence is repeated. Therefore the program counter performs
the coarse, or rough, tuning while the swallow counter handles
the fine tuning.
restrictions on the timing increments-that generally result in
too many loop or receiver problems. A superior approach is to
use a dual-modulus prescaler, i.e., an ECl divider with two
different divide ratios usually closely related, in a technique
called "pulse swallowing."
Pulse Swallowing
Pulse swallowing is a technique that combines the talent of a
very fast, but dumb, ECl prescaler with that of a low speed, but
very smart, counter. The best way to explain it is to divert, for the
moment, from the field of electronics and enter the world of
masonry. Suppose a universal brick were required for building
walls of any length, within one inch, without breaking the brick.
One way to do this would be to make one brick 10 inches long
and another 11 inches. Using combinations of these two sizes
01 bricks, walls ohny length (over 100") may be built(Figure9).
THE FAIRCHILD MICROPROCESSOR CONTROLLED
PLL TUNING SYSTEM
The Fairchild FEX2500 Pll circuit is made using CMOS metalgate technology and is packaged in a 28-pin DIP, either plastic
or ceramic.The primary features are:
Back to electronics-the dual-modulus prescaler (Figure 10) is
similar to the two different brick lengths. By controlling the
du.al-modulus prescaler appropriately, the incoming clock frequency pulses can be counted in two different "block lengths"
(Figure 11l. For high-frequency applications, pulse swallowing
combines the advantages ot.-both the straightforward method
(Figure 7l and the fixed modulus prescaler (Figure 8l. It allows
the highest possible reference frequency fREF and vastly reduces the speed requirement of a programmable divide-by-n
counter. The dual-modulus prescaler, when operating, appears
to swallow pulses when changing between the two divide ratios
of the prescaler.....,.thus the name, "pulse swallowing."
• Microprocessor addressable
• Data-holding registers independent of input data,
once addressed
• Operates to 4 MHz
• Operates to 1 GHz with appropriate prescaler
• Fine tuning capability-1 kHz AM band, 25 kHz FM band,
62.5 kHz TV
• Complete digital portion of Pll tuning system
• On-board oscillator circuit for reference frequency
• 4 MHz, 2 MHz and 1 MHz outputs that may be used for
clock input to microprocessor or other circuits
• Unique data-bus chip select system
• Choice of 1 kHz, 5 kHz, 7.8125 kHz or 25 kHz reference
frequency
• Phase comparator incorporates patented anti-backlash
circuit to reduce random FM modulation of the Veo
• Out-of-Iock output indicates out-of-Iock condition of loop
• Dual ratio program and swallow counters for extended loop
frequency range
To keep track of how many times the prescaler operates in one
of its two modes (usually the higher), an extra counter, called a
swallow counter, is added to the system. The swallow counter
has only a small total divide ratio compared to that of the
program counter. It differs from the program counter in that its
Terminal-Count output is connected back to a Stop input and
operates like a one-shot. This is called a dead-ended counter
because it stops after reaching terminal count.
10·22
r--------------- TOTAL OIVIDE-BV-N COUNTER -----------------1
I
I
r-----i
I
DUAL MODULUS
PRESCALER
+ U/L
1---------------
IV
I
I
I
I
I
t~7
PE
I
I
I
---- --,
I
I
I
PE
t-t-';-:-iI-t CP ~~~~~~~
TC
f-
, . CP
6~~~~:~
TC
t
1--~7__.l--:~kF. FREQ.)
I
I
STOP
I
t
I
f
I
I
MODULUS
CONTROL
(1) fosc = N x fref
PC ~ PROGRAM COUNTER RATIO
SW ~ SWALLOW COUNTER RATIO
U ~ UPPER PRESCALER DIVIDE RATIO
L = LOWER PRESCALER DIVIDE RATIO
N ~ TOTAL DIVIDE RATIO
(2) N = Sw (U-L) + LPc
(3) or N = USw + L(Pc-Sw)
LIMITS
PC >SW
Fig. 10
Frequency Dlvlde-by-N Counter Using a Dual Modulus Preacaler
j - - - REFERENCE FREQ PERIOD
r-DIVIDE-BV-N
COUNTER OUTPUT
WAVEFORM
ONE COMPLETE DIVIDE-8V-N CVCLE
I
I
-of ~
--u
I
I
PARALLEL
LOAD
-J
-J
r----~I ~
II
L
I
I
Ur---PRESCALER OPERATES IN
LOWER DIVIDE RATIO
.--I~-----_A. . ------..:_--.,
PRESCALER MODE
CONTROL WAVEFORM -of
f--I
(SWALLOW COUNTER OUTPUT)
l.; f - - -
'
-----------
L. PRESCALER OPERATES IN HIGHER DIVIDE RATIO--'
Fig. 11
Different "Block Lengths"
The FEX2500 contains all the essential digital components of
an advanced Pll tuning system, requiring only an external
tuner, integrator and a crystal to complete the entire loop.
Programs and Swallow Counters
Clock Inputs
The Clock input for the program and swallow counters can be
selected for either a differential input or a single-ended input by
using an Input Select pin (IS), For TV or FM radio applications,
the differential input mode is generally used. The Pll differential inputs are connected directly to the differential outputs of
an ECl prescaler. This considerably reduces the amount of
radiated digital-interference noise. Single-ended mode is intended for AM radio applications without the use of a prescaler.
In AM/FM radio, the local oscillator is connected to the singleended input while the differential inputs are connected to the
ECl prescaler that derives input from the FM local oscillator.
loop change from AM to FM is accomplished with the IS
control. The maximum frequency on both inputs is 4 MHz.
The Pll loop operates from 100 kHz to 4 MHz directly, andto 1
GHz with the addition of an ECl prescaler. The system has fine
tuning increments of 1 kHz for the AM band, 25 kHz for the FM
band, and 62.5 kHz for TV and can be set lower with loop
compromises. The user hasa choice of 1 kHz,5 kHz, 7.8125 kHz
or 25 kHz reference frequencies when used with a 4 MHz
reference crystal. Once addressed to the desired tuning frequency, the Pll circuit can be operated independently of the
microprocessor, since the Pll contains the necessary holding
registers for data. To accommodate the 4 MHz input operating
frequency and low propagation delays, it uses two power supplies, +12 V and 5 V. The +5 V supply is required to make the
input and output circuits compatible with other +5 V logic
circuits. Figure 12 shows the complete block diagram containing both the program counter and swallow counter as well as a
phase comparator, crystal oscillator, reference frequency divider, four 4-bit registers to store tuning information, plus
additional circuits.
Counter Configurations
The counter has a total bit length of 16 bits, is sub-divided into
two sections-a program counter and a swallow counter, and
has two selectable configurations: 13 bits program/3 bits swallow or 11 bits program/5 bits swallow. Counter-configuration
control determines which bit lengths are selected according to
10-23
II
,
ID/ENABLE
IDENT CLOCK
DATA CLOCK
DATA BUS IN 4 BITS
DIFF IN +
DIFF IN -
~
o
N
SINGLE
ENDED
INPUT
....
MC
J
!
INPUT
SELECT
MODE
CONTROL
OUTPUT
~.o""~L
COUNTER CONFIGURATION
COMPARATOR
OUTPUT DISABLE
COMPARATOR
REF SELECT 0
CO
COMPo OUTPUT
1
OSCIN
•
OL
OUT-OF-LOCK
esc
--
OUT
F1
1 MHz
F2
2 MHz
4 MHz
Fig. 12
FEX2500 PLL Block Diagram
F4
an output disable circuit. The actual frequency/phase comparator is the standard digital type that locks onto the negative
edges of the two waveforms, one from the program counter and
the other from the reference-frequency divider (Figure 141. It
can only lock onto the correct frequency with no output of the
comparator at multiples of either of the two frequencies.
different divide ratios required in various applications. The
maximum possible divide ratios are:
MODE
PROGRAM
SWALLOW
13/3
213 = 8192
23 = 8
11/5
211 =2048
25 = 32
Anti-Backlash Circuit
The anti-backlash circuit eliminates the dead-zone problems
due to propagation delays in other digital frequency/phase
comparators. A narrow pulse (~ 200 nsl is injected into the
pump-down circuit to cause a loop error. The loop responds by
making another pulse of equal and oppOSite magnitude to
cancel out the error (Figure 151. Both pulses are arranged to be
closely related in time so they can be easily filtered out by small
filter capacitors. Therefore the net charge fed to the integrator
by these pulses is zero. However, the injection of these pulses
causes a slight phase error that operates the frequency-phase
comparator outside the dead zone. The addition of this circuit
considerably enhances the spectral output of the veo, eliminating random low-frequency modulation caused by phasecomparator "hunting" in standard comparators.
Both counters are down types; therefore, the divide ratio is the
same as that of the binary load value. The load values for
frequency or channel allocation are obtained from the microprocessor. Binary counters, rather than decimal counters, simplify chip design and minimize software programming problems on the microprocessor. For low-frequency operation below 4 MHz, the swallow counter is not used and it is immaterial
what data values are loaded into it. Figure 13 shows the data
loading format.
Frequency/Phase Comparator
The frequency/phase comparator has a number of unique
features, an anti-backlash circuit, an out-of-Iock detector and
HEXADECIMAL INPUT DATA REGISTERS WXYZ
~
_ _ _ _ _ _ _ _ _ _- - J A ,_ _ _ _ _ _ _ _ _ _ _ _
~
...------... ...------... ...------... ...------...
SWALLDW + PRDGRAM
SWALLDW
CDUNTER
~
CDUNTER CONFIGURATION
3 BITS SWALLOW
13 BITS PROGRAM
I
cc
= PIN 20 "HIGH"
I
r~--
++ER:W
MSB
PRDGRAM
PRDGRAM
PRDGRAM
PROGRAM COUNTER
____________
______________
~A,-
I
I
~,
++ER>
I
LSB
LSB Msa
++++
++++
++++
+ + ++
HEXADECIMAL INPUT DATA REGISTERS WXYZ
r~'--------------~'----------~~
...------... ...------... ...------...
SWALLOW
SWALLOW + PROGRAM
SWALLOW
COUNTER
5 BITS SWALLOW
I
CC" PIN 20 "LOW"
1++R:wl
MSB
PROGRAM COUNTER
I
++R:X
I
I
LSB MSB
++++
Fig. 13
PROGRAM
~
,.-"'---., ,___----------J"---------.
COUNTER CONFIGURATION
11 BITS PROGRAM
PROGRAM
++++
I
LSB
++ ++
Bit Coordination Between Input Registers and Loop Counters
10·25
++R>
++ ++
II
ON FREQUENCY AND
IN PHASE
LOW IN FREQUENCY
HIGH IN FREQUENCY
OIVIDE-BY-N
COUNTER OUTPUT
REFERENCE
FREQUENCY
PUMP UP
PUMP DOWN
+
o +--...:..--.....---++
HIGH IMPEDANCE
(OPEN CIRCUIT)
Fig. 14
I"
Output Waveforms from Frequency/Phase Comparator
-----
REF FREQ PERIOD.
-,
LOOP RESULTANT CORRECTION PULSE
~
VARIABLE
OL
~INJECTED~
ERROR
PULSE
Fig. 15
DIGITAL
TIMING
SAMPLER
800 ns
PULSE
REFERENCE
Output of Frequency/Phase Detector
with Anti-Backlash Circuit
Fig. 16
Out-ol-Lock Circuit
Out-ol-Lock Detector (Figure 16)
This circuit is used to detect an out-of-Iock condition, due to
either a malfunction or a channel change. The indicator is also
useful during initial loop set-up and test. It can also be used to
mute the audio during channel changes, or itcan be connected
to an LED display for indication of loop malfunction.
Relerence Frequency Divider and Oscillator Circuits
The oscillator circuit consists of two high-gain CMOS inverter
circuits in series plus the external components-crystal, trimmer capacitor. resistor-connected between the input and
output of the inverters.
In operation, a window signal is decoded off the referencefrequency divider chain (Figure 171. When the loop is locked,
the negative edge of the output waveform hom the divide-by-n
counter rests in the middle of the window. If it strays outside the
window for two period reference cycles, a latch is set and an
out-of-Iock condition is indicated.
The reference frequency divider circuit is a straightforward
counter with various outputs-4 MHz, 2 MHz and 1 MHz
-which may be used for the microprocessor clock. The reference frequencies of 1 kHz, 5 kHz, 7.8125 kHz and 25 kHz are
tapped off the divider chain through a 4-input multiplexer, that
selects the reference frequency.
Output Circuit
The output circuit is designed to provide three output modes
(Figure 18) -current sourcing (pump-up), current sinking
(pump-down) or high impedance (open circuit).
Chip-Identity Circuit
When the IDENT code (PLL Chip 0110) is present on the Data
Bus input and an IDENT clock is generated, the scan counter is
initialized. Data can now be entered into the first register W via
the DATA clock. which then clocks the scan counter so the
second register X is ready to accept data. This is repeated until
the remainder of the registers are loaded. Data can be repeatedly loaded into the registers using the DATA clock, but care
must be exercised to keep track of which register is receiving
data. To disable the Data Bus input to the PLL chip, a wrong
IDENT code is put into the data bus and an IDENTclock generated. The IDENT code circuit may be disabled by leaving the ID
Enable input HIGH.
When the loop is locked, the output circuit is in the, highimpedance state, except during the positive and negative antibacklash pulse injection mentioned previously.
Output Disable
This control can be used to hold the loop on frequency while
new frequency information is being loaded into the PLL registers. When the output is disabled, the output from the frequency
phase comparator is in the high impedance state. When a
frequency change is initiated, new data is fed, relatively slowly,
into the four registers, WXYZ. During the loading of each
register, the loop responds to the new data causing erroneous
loop responses, unless the comparator output is disabled.
Data Input Terminal
Figure 13 shows the input data format for registers W X Y Z in
both configurations of the counters.
When this output is disabled, the integrator tends to remember
the last charge level, thus keeping the loop on or about
frequency.
The generation of the input data for operating a PLL at given
frequencies is worked. out from the equation in Figure 10. The
following example shows the procedure for establishing the
10-26
-OUT~OF-LOCK-r-IN-LOCK~OUT-OF-LOCKDECODED fROM
REfERENCE DIVIDER
OUT·Of·lOCK WINDOW ~~~_-:-......_ _ _ _ _"""
DIVIDE·BY·N COUNTER
Fig. 17
Out-ol-Lock Timing Diagram
+5V
fROM + N
COUNTER
OUTPUT
OISABlE
fREQI
PHASE
COM
REf fREQUENCY
DIVIDER
Fig. 18 Frequency/Phase Comparator Output
INPUT .:_ _ _~
+ 31132
:
OUTPUT
' - - - - - - _ c MODE CONTROL
11C79 200 MHo ECl PRESCAlER
INPUT
.:------IL.__
H
+_8_....
+ 31132
t - - -....
: OUTPUT
' - - - - - - -.... MODE CONTROL
Fig. 19 Prescalers
The integer part of the number is the PC load divide ratio
values and will help clarify the operation of the pulse swallowing system.
:. PC
Receiver -FM 88.1 to 107.9 MHz
IF 10.7 MHz
b. Find SW divide ratio (Fine Tuning)
Take the integer number from above and multiply
prescaler lower ratio:
PLL Setup for 4 MHz Crystal Reference
25 kHz Reference Frequency
bY",.
127 x 31 = 3939
1. LOW Frequency = Receiver + IF
= 88.1 + 10.7
= 98.8 MHz
2. Total Divide-by-n
= 127
Subtract this number from Divide-by-n:
= LOW Frequencyof- Reference
3952 - 3937 = 15
= 98.8 of- 25 kHz
= 3952
:. SW
= 15
This is the number of times the prescaler operates in the
divide-by-32 mode. It is not necessary to work out subsequent frequencies in the range, but merely increment the
values by the required amount. These numbers then have to
be translated first into binary, then into hexadecimal data
to fit the data loading format shown in Figure 13.
3. To find PLL loading data:
Program Counter = PC
Swallow Counter = SW
a. Find PC divide ratio (Coarse Tuning)
PRE SCALERS (Figure 19)
"Divide-by-n" divided by prescaler lower ratio
Two prescalers have been specially designed to operate with
the FEX2500 PLL chip: 11C79 divide-by 31/32 (200 MHz) and
3952 of- 31 = 127.48387
10·27
..
r----r---- +5 V
"NOTE: FOR TV USE A HEADER AND PLACE 11eu
PRESCALER AT THE TUNER.
J = OPTIONAL JUMPERS
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01. 01 -
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FEX2500
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FORMULATOR
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BCD TO 7 SEGMENT
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PLUMATRIllKEY80ARD/OISPLAY
Fig. 20
L________________ ~~N~~~~~~~~
Advanced AM/FM Radio Application
______________
1
I
J
11 C82 divide-by 248/2511 GHz). Other prescalers are available
with a decrease in digital noise performance: 11 C90 divide-by
10/11 1600 MHz) and 11C91 divide-by 5/61600 MHz)'
One exciting area for a PLL tuning system is a home AM/FM
radio with short-wave bands. Low-cost short-wave receivers to
date are generally difficult to tune but with the precise tuning of
a PLL tuning circuit, this would change.
The maximum operating frequency of PLL system is limited by
the 4 MHz maximum frequency of PLL FEX2500.
If the radio had memory storage for a number of short-wave
stations, people living in different lands could program in a
station from their own country. Most foreign countries radiate
the same program material on a number of frequencies. Due to
periodic sunspot activity, some frequencies are better than
others; thus it is necessary to store a number of short-wave
frequencies. Also, because of the ease of tuning, the short-wave
broadcast bands could become acceptable for normal broadcast frequencies.
Example using 11 COO divide-by 10/11:
= 4 MHz x 10 = 40 MHz
AM/FM APPLICATIONS
Figure 20 shows an advanced AM/FM radio with a single chip
F3870 microprocessor and keyboard with an LED display readout. It has manual or automatic search tuning and storage for a
number of stations. It can tune on AM to 1 kHz increments and
FM to 25 kHz.
HISTORICAL NOTE ON PULSE SWALLOWING
The pulse swallowing technique makes the whole PLL tuning
system commercially feasible and acceptable in performance.
It was the idea, or.invention, of John Nichols in about 1968-69
time period when he worked for Fairchild. The work was done
initially for 360-channel aircraft radio/transmitters. It was not
until many years later that his brilliant idea became widely
known.
With the integrator circuit, the undesirable reference frequency
modulation of the VCO frequency is:
FM = better than 50 dB at 25 kHz
AM = better than 45 dB at 1 kHz
10-29
Microprocessor-Based
Solar Controller
Microprocessor-Based Solar Controller
Controller Operation
Energy is being consumed today in greater quantities than
ever; at the same time, yesterday's seemingly unlimited
resources are now seen to be quite finlte. As a result,
energy conservation has assumed a new importance, and
the search for alternative energy sources has begun in
earnest. One of the more promising possibilities is harnessing the sun as a direct source of heat.
The microprocessor is programmed to solve a set of logicl
arithmetic equations. These equations are contained in the
EPROM program storage, with the associated constants being held in the 1K RAM. The keyboard can be used to
change a number of the equation constants, permitting
system changes to be made without hardware modification.
The solar heating systems now being installed in homes,
apartment complexes, and businesses contain heat collecting and storing devices from which resources are drawn
during non- and low-sunlight periods. Although there are
many types of such systems, the most common circulate
water or some other liquid through solar heating panels, or
collectors, during the day and store the heated fluid in
tanks. When required, this fluid is pumped through radiators
or radiant coils to provide area heating. To maintain comfort
and make the best use of the available energy, the user
must continuously monitor the temperature of every area to
be heated, as well as the temperatures of the collectors and
the storage tanks. Valves must then be opened or closed
and pumps turned on or off to maintain the desired relationship among the system components. A computerized energy management system, or solar controller, can perform all
of the monitor and control functions with optimum efficiency.
A microprocessor-based solar controller designed by Fairchild for Rho Sigma, Inc., a major manufacturer of solar
controls, is specifically intended to accept the low voltages
produced by thermistor temperature sensors, process and
display the data, and provide outputs for relay and switch
opening and closing. The solar controller contains a singleboard F8™ microprocessor, two input and two output cards,
an AID converter control card, a display control card, two
4K EPROM program storage cards, and a 1K RAM and
memory address card (figure 1).
Also included in the unit are an AID converter, a 5-digit LED
display, and a 16-key keyboard. The display automatically
sequences through all input channels, displaying the number and temperature of each channel for one second before
cycling to the next. The keyboard can be used to halt this
sequencing and either make the display continuously monitor only one channel or convert it to a clock-only display
that shows time of day.
In normal operation, the AID converter receives analog temperature information from as many as 16 thermistors and
presents the converted data to the microprocessor. Digital
data, such as that produced by switch closures and teletype
signals, can be presented directly to the microprocessor
through the 16 digital inputs of the input cards. These data
are used to solve the system functional equations and produce two types of microprocessor outputs.
In the channel-monitor modes, temperature information is
output to the display in degrees Fahrenheit or CelSius,
depending upon resident program. In the time-display
mode, a timekeeping routine program assumes control of
the display circuitry and the temperature information is not
provided.
The other microprocessor output consists of control signals
that are suitable for opening and closing relays and activating solid state switches. These signals perform such functions as turning on pumps and opening valves to let water
run into the storage tank or circulate through radiators.
Since program storage is in ROM, power failure does not
cause catastrophic loss of memory. When power is restored, a resetting sequence begins, with the controller ensuring that all valves and controls are turned off so that stored
energy is not lost. The controller then cycles through all of
the inputs, decides what the system operating conditions
should be, and generates the necessary output signals. This
analysis takes approximately five seconds. To indicate to
the user that power has been off, the display flashes until
manually reset.
Originally designed for use in solar heating applications, the
intelligent microprocessor-based controller is applicable to
any system in which the ability to deal with multiple sensor
inputs and generate control outputs is required.
10-31
II
•
Fig. 1 Solar Controller Functional Block Diagram
10-32
[!] I
1
INTRODUCTION
'2l
1ORDERING AND PACKAGE
~ INFORMATION
1 0 1 F8 MICROCOMPUTER FAMILY
101CONTROLLER FAMILY
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1C!JIF16000 MICROPROCESSOR FAMILY
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RESOURCE AND TRAINING
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Section 11
Microprocessor Resource
and Training Centers
Microprocessor Resource Center
The following Education Center course offerings are
included.
The Microprocessor Resource Center (MRC) organization
was created to serve as yet another, technically oriented,
Fairchild customer link to a world·wide support structure
that is concerned with all phases of the customer's require·
ments.
• F8 and F3870 Microprocessor Systems
Intended to introduce the student to the Fairchild F8 and
F3870 microprocessor systems, this course provides
basic knowledge of F8 and F3870 hardware, software,
applications, and development aids. Included are labora·
tory sessions in which the student applies that knowl·
edge in practical situations. Among the areas covered
are device features and architecture, use of the various
registers, machine and assembly language syntax, program writing and debugging, and hands-on use of the
PEP387X and Formulator systems.
Every MRC is available to assist the customer in microproc·
essor hardware and software development and application
engineering, product definition, and long·term product
strategies. Backed by Fairchild's expertise and extensive
resources, the MRC is a tool for solving current problems
and planning for future needs.
At each Center is a microprocessor expert who is equally
familiar with standard devices and those Fairchild state·of·
the·art products that are on the leading edge of technology.
Because they understand the microprocessor market and
development trends, these experts provide technical support
and planning assistance that can benefit the customer
through timely and cost·effective system design and
implementation.
• F6800 Microprocessor Family
This course provides the student basic knowledge of
Fairchild F6800 8·bit microprocessor family hardware,
software, applications, and development aids. Included
are laboratory sessions in which the student applies that
knowledge in practical situations. Among the areas cov·
ered are device features and architecture, register organ·
ization and use, system configurations, program writing
and debugging, and hands·on use of the various training
and development aids.
As an added convenience, all Microprocessor Division devel·
opment systems can be demonstrated at the MRCs. This
affords the customer an opportunity to assess the perform·
ance and applicability of products in an operational· type
environment.
• F9445 Family Introduction
This course is an overview of the Fairchild F9445 16·bit
microprocessor and its supporting circuits. Consisting of
both lecture and laboratory sessions, with emphasis on
hands·on experience, the course covers such areas as
F9445 CPU and system timing, software, device features
and architecture, and use of the FS·I and EMUTRAC
development aids.
Training on Fairchild's microprocessor products is available
at either the customer or MRC location. This training, which
is coordinated by the MRC manager, is performed in con·
junction with the Microprocessor Division Education Center.
Microprocessor Education Center
• F16000 Family Introduction
IntroduCing the student to the Fairchild F16000 16·bit
microprocessor family, this course is an overview that
consists of both lecture and laboratory sessions. Empha·
sizing hands·on experience in the laboratory, the course
covers such areas as device features and architecture,
CPU and system timing, principles of memory manage·
ment and virtual memory, floating point arithmetiC, and
familiarization with design aids.
Education plays a key role in the technical support of a
microprocessor user. It is essential to a full understanding
of the complexities, capabilities, and applications of
modern processor products, and is therefore treated as an
important component of the Fairchild Microprocessor
Division customer support structure.
The most recent advances in microprocessor technology
are included in the Fairchild Microprocessor Eduction
Center courses, which feature a maximum amount of
hands·on experience. Indeed, the major thrust of the
training courses is to focus on the general techniques of
microprocessor usage. This emphasis, it is felt, best pre·
pares the student to apply the available design and develop·
ment tools to specific applications in an efficient manner.
• FS·I Development System
This course introduces the student to the Fairchild
System·1 (FS·I) development system, emphasizing hands·
on experience. Included is coverage of operating system
usage, utility software usage, high·level languages and
their associated compilers and interpreters, and the
EMUTRAC emulation and tracking system.
11·3
III
Microprocessor Resource.
and Training Centers
• Microprocessor Control and Interface
This course is intended to introduce the student to the
principles and techniques of microprocessor control and
interfacing. Opportunity is provided for hands-on experimentation with a mini-development system. Included in
the course are a review of microprocessor fundamentals,
transducer types and applicability, conversion techniques, and parallel and serial formats .
• Pascal for Microprocessors
An introduction to the high-level Pascal language, this
course teaches the student the skills required to produce
software in Pascal for many practical applications, including real-time computing, scientific and engineeringtype problem solving, and data processing.
11-4
I[!]
I INTRODUCTION
~2 IORDERING AND PACKAGE
~ INFORMATION
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101F16000 MICROPROCESSOR FAMILY
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Section 12
Sales Offices
II
12·3
Sales Offices
12·4
A Schlumberger Company
Sales
Offices
United States and
Canada
Alabama
Huntsville Olfice
Indiana
Ft. Wayne Office
North Carolina
Raleigh Oflice
FAIRCHILD
500 Wynn Drive, Suite 511
2118 Inwood Drive, SUite 111
1100 Navaho Drive. SUite 112
Huntsville. Alabama 35805
Tel: 205-837-8960
Ft. Wayne. Indiana 46815
Tel: 219-483-6453 TWX 810-332-1507
Raleigh. North Carolina 27609
Tel 919-876-9643
Arizona
Phoenix Office
Indianapolis Office
Ohio
7202 N. Shadeland. Room 205
2255 West Northern Road. Suite B112
Castle POint
Dayton Office
5045 North Main Street SUite 105
Phoenix, Arizona 85021
Indianapolis, Indiana 46250
Tel: 317-849-5412 TWX: 810-260-1793
Dayton. Ohio 45414
Tel: 513-278-8278 TWX 810-459-1803
Kansas
Oklahoma
Kansas City Office
8600 West 110th Street. Suite 209
Overland Park. Kansas 66210
Tel: 913-649-3974
9810 East 42nd Street. SUite 127
Tulsa. Oklahoma 74145
Tel: 918-627-1591
Tel: 602-864-1000 TWX: 910-951-1544
California
Los Angeles Office'
Crocker Bank Bldg
15760 Ventura Blvd" Suite 1027
Encino, California 91436
Tulsa Office
Tel: 213-990-9800 TWX: 910-495-1776
San Diego Office'
7867 Convoy Court. Suite 312
San Diego. California 92111
Tel: 714-279-7961 TWX: 910-335-1512
Maryland
Columbia Office
1000 Century Plaza. SUite 225
Columbia. Maryland 21044
Tel: 301-730-1510 TWX' 710-826-9654
Oregon
Portland Office
8285 SW. Nimbus Avenue. SUite 138
Santa Ana Office"
Massachusetts
Pennsylvania
Philadelphia Office'
2500 Office Center
2500 Maryland Road
1570 Brookhollow Dnve. Suite 206
Santa Ana. California 92705
Tel: 714-557-7350 TWX: 910-595-1109
Santa Clara Office'
3333 Bowers Avenue. SUite 299
Santa Clara. California 95051
Tel: 408-987-9530 TWX: 910-338-0241
Colorado
Denver Office
7200 East Hampden Avenue. Suite 206
Denver. Colorado 80224
Tel: 303-758-7924
Framingham Office
5 Speen Street
Framingham, Massachusetts 01701
Tel: 617-872-4900 TWX 710-380-0599
Beaverton. Oregon 97005
Tel: 503-641-7871 TWX 910-467-7842
Willow Grove, Pennsylvania 19090
Tel: 215-657-2711
Michigan
Detroit Office'
21999 Farmington Road
Farmington Hills, Michigan 48024
Tel: 313-478-7400 TWX: 810-242-2973
Tennessee
Knoxville Office
Executive Square II
9051 Executive Park Drive, Suite 502
Knoxville. Tennessee 37923
Tel 615-691-4011
Minnesota
Minneapolis Office·
4570 West 77th Street. Room 356
Minneapolis, Minnesota 55435
Tel: 612-835-3322 TWX: 910-576-2944
Texas
Austin Office
Connecticut
Danbury Office
57 North Street. #206
Danbury. Ccnnectlcut 06810
Tel: 203-744-4010
New Jersey
9027 North Gate Blvd
Austin. Texas 78758
Tel: 512-837-8931
SUite 124
New Jersey Office
Vreeland Plaza
41 Vreeland Avenue
Dallas Office
1702 North CollinS Street. SUite 101
Florida
Ft. Lauderdale Office
Totowa. New Jersey 07511
Tel: 201-256-9006
Tel: 214-234-3391 TWX 910-867-4757
New Mexico
Albuquerque Office
9896 Blssonnet-2. SUite 470
Richardson, Texas 75081
Executive Plaza, Suite 112
1001 Northwest 62nd Street
Ft. Lauderdale. Florida 33309
Tel: 305-771-0320 TWX: 510-955-4098
Houston Office
North Building
Houston, Texas 77036
2900 Louisiana N.E. South G2
Tel: 713-771-3547 TWX 910-881-8278
Orlando Office'
Albuquerque, New Mexico 87110
Crane's Roost Office Park
Tel: 505-884-5601 TWX: 910-379-6435
Canada
399 Whooping Loop
Altamonte Springs. Florida 32701
Tel: 305-834-7000 TWX: 810-850-0152
New York
2375 Steeles Avenue West. Suite 203
Georgia
Atlanta Sales Office
Interchange Park. Bldg.
4183 N.E. Expressway
Atlanta. Georgia 30340
Tel: 404-939-7683
Toronto Regional Office
Fairport Office
Downsview, Ontario M3J 3AB, Canada
815 Ayrault Road
Tel: 416-665-5903 TWX 610-491-1283
Fairport. New York 14450
Tel: 716-223-7700
Melville Office
275 Broadhollow Road. Suite 219
Melville. New York 11747
Tel: 516-293-2900 TWX: 510-224-6480
Illinois
Itasca Office
500 Park Blvd" SUite 575
Itasca. Illinois 60143
Tel: 312-773-3300
Poughkeepsie Office
19 Davis Avenue
Poughkeepsie. New York 12603
Tel: 914-473-5730 TWX 510-248-0030
• Field Application Engineer
12-5
I=AIRCHILD
A Schlumberger Company
Australia
Fairchild Australia Pty Ltd.
Branch Office Third Floor
F.A.1. Insurance Building
619 Pacific Highway
SI. Leonards 2065
New South Wales, Australia
Tel, 02 ,-439-5911
Telex: AA20053
Austria and Eastern Europe
Fairchild Electronics
A-1010 Wien
Schweden platz 2
Tel: 0222635821 Telex· 75096
Benelux
Fairchild Semiconductor
Ruysdaelbaan 35
5613 Ox Eindhoven
The Netherlands
Tel 00-31-40-446909 Telex: 00-1451024
Brazil
Fairchild Semiconductores Ltda.
Caixa Postal 30407
Rua Alagoas, 663
01242 Sao Paulo. Brazil
Tel 66-9092 Telex· 011-23831
Cable FAIRLEC
France
Fairchild Camera & Instrument S_A
'21, Avenue d'italie
75013 Paris, France
Tel: 331-584-5566
Telex: 0042 200614 or 260937
Sales
Offices
International·
Hong Kong
Fairchild Semiconductor I HK Ltd,
135 Hoi Bun Road
Kwun Tong
Kowloon, Hong Kong
Tel 3-440233 and 3-890271
Telex· HKG-531
Scandinavia
Singapore
Italy
Fairchild Semiconducttori, S.P.A.
Via Flamenia Vecchia 653
00191 Roma, Italy
Tel: 06 327 4006 Telex: 63046 ,FAIR ROM
Fairchild Semiconductor Pty. Ltd.
No. 11, Lorong 3
Toa Payoh
Singapore 12
Tel: 531-066 Telex: FAIRSIN-RS 21376
Fairchild Semiconducttori S.P.A.
Viale Corsica 7
20133 Milano, Italy
Tel: 296001-5 Telex: 843-330522
Taiwan
Japan
Fairchild Japan Corporation
Pola Bldg.
1-15-21, Shibuva
Shibuya-Ku, Tokyo 150, Japan
Tel: 03 400 8351 Telex: 242173
Fairchild Japan Corporation
Yotsubashl Chuo Bldg
1-4-26, Shinmachi
Nishi-Ku, Osaka 550, Japan
Tel 06-541-6138/9
Korea
Fairchild Semikor Ltd.
K2 219-6 Gari Bong Oong
Young Dung Po-Ku
Seoul 150-06, Korea
Tel: 85-0067 Telex: FAIRKOR 22705
Germany
Fairchild Camera and Instrument GmBH
Daimlerstrasse 15
8046 Garchlng Hochbruck
Munich, Germany
Tel: ,089 320031 Telex: 524831 fair d
Fairchild Camera and Instrument GmBH
Oeltzenstrasse 15
3000 Hannover
W, Germany
Tel: 0511 17844 Telex: 09 22922
Fairchild Semiconductor AB
Svartengsgatan 6
S-11620 Stockholm
Sweden
Tel: 8-449255 Telex: 17759
mailing address
Central P.O. Box 2806
I
Mexico
Fairchild Mexicana S.A.
Blvd. Adolofo Lopez Mateos No. 163
Mexico 19, DF
Tel: 905-563-5411 Telex: 017-71-038
Fairchild Camera and Instrument GmBH
Poststrasse 37
7251 Leonberg
W. Germany
Tel 0715241026 Telex: 07 245711
12·6
Fairchild Semiconductor Ltd.
Hsietsu Bldg., Room 502
47 Chung Shan North Road
Sec. 3 Taipei, Taiwan
Tel: 573205 thru 573207
United Kingdom
Fairchild Camera and Instrument Ltd
Semiconductor Division
230 High Street
Potters Bar
Hertfordshire EN6 5BU
England
Tel: 0707 51111 Telex: 262835
Fairchild Semiconductor Ltd.
17 Victoria Street
Craigshill
Livingston
West Lothian, Scotland-EH54 5BG
Tel: Livingston 050632891 Telex: 72629
GEC-Fairchild Ltd.
Chester High Road
Neston
South Wirral L64 3U E
Cheshire, England
Tel: 051-336-3975 Telex: 629701
FAIRCHILD
Schlumberger Company
Fairchild reserves the right to make changes In the circuitry or
specifications at any time without notice. Manufactured under one of
the following U.S. ~3tents 2981877, 3015048, 3064167,3108359, 3117260;
other pat nts pending. Fairchild cannot assume responsibility for use of
any circuitrY described other than circuitry embodied in a Fairchild
pro uct. N ther circuit patent licenses are implied.
Source Exif Data:
File Type : PDF File Type Extension : pdf MIME Type : application/pdf PDF Version : 1.3 Linearized : No XMP Toolkit : Adobe XMP Core 4.2.1-c043 52.372728, 2009/01/18-15:56:37 Create Date : 2013:08:06 17:45:07-08:00 Modify Date : 2013:08:06 20:45:26-07:00 Metadata Date : 2013:08:06 20:45:26-07:00 Producer : Adobe Acrobat 9.55 Paper Capture Plug-in Format : application/pdf Document ID : uuid:812f1a07-1a2b-a14c-a165-cfc8d49e88d8 Instance ID : uuid:a24f1de3-df17-5d4d-b2ed-e3cd48a1dc83 Page Layout : SinglePage Page Mode : UseNone Page Count : 790EXIF Metadata provided by EXIF.tools