1982_Fujitsu_Memory_Data_Book 1982 Fujitsu Memory Data Book

User Manual: 1982_Fujitsu_Memory_Data_Book

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FUJITSU
MICROELECTRONICS

Fujitsu Microelectronics' manufacturing facility in San Diego, California

FUJITSU MICROELECTRONICS, INC,A U,S, ORGANIZATION
Fujitsu Microelectronics Inc, (FMI) is aU,S,
subsidiary of Fujitsu Limited of Tokyo. A
California Corporation, FMI is responsible
for the marketing and sales of all semiconductor products in North, Central and South
America.
Fujitsu Limited manufactures and markets .
advanced data processing and telecommunIcations systems, semiconductors and electronic components on a worldwide scale.
Fujitsu Limited is ranked as Japan's number
one computer manufacturer with sales in the
$2 billion range.

A LEADER IN ICs
Fujitsu is one of the world's largest electronic companies with development and
manufacturing capabilities utilizing the most
modern and innovative technical skills.
Fujitsu Microelectronics remains at the
leading edge of semiconductor technology
as exemplified by its offering of the world's
first mass-produced 64K-bit MOS RAM. Process technologies include both MOS and

bipolar; products include static and dynamic
memories, RAMs, EPROMs and PROMs; as
well as LSI logic including microprocessors
and gate arrays.

ABOUT FUJITSU MICROELECTRONICS
Fujitsu Microelectronics has completed a
new assembly and test facility in order to
better service our North American customers. The 66,000 square-foot facility is
located in Kearny Mesa Industrial Park near
downtown San Diego. The building was dedicated in June 1981 and is now fully operational.

ABOUT FUJITSU MIKROELEKTRONIK GmbH
Fujitsu Mikroelektronik GmbH was formed in
June 1980 as a wholly owned subsidiary of
Fujitsu Limited of Tokyo. From headquarters
in Frankfort, West Germany, it supervises
the sales and marketing of Fujitsu semiconductor products throughout Western Europe.
Fujitsu plans to construct a factory in
Ireland to further increase its ability to provide high quality semiconductor devices to
its European customers.

FUJITSU
MICROELECTRONICS

MEMORY DATA BOOK

APRIL 1982

Fujitsu Microelectronics, Inc. makes no warranty for the use of its products described herein.
Circuit diagrams utilizing Fujitsu products are included as a means of illustrating typical semiconductor
applications, consequently, complete information sufficient for construction purposes is not necessarily
given The information has been carefully checked and is believed to be entirely reliable. However, no
responsibility is assumed for inaccuracies. Furthermore, such information does not convey to the pur·
chaser of the semiconductor devices described herein any license under the patent rights of Fujitsu
Limited or others. Fujitsu Limited reserves the right to change device specifications.
No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of Fujitsu MicroelectrOnics, Inc.
Additional copies of this manual or other Fujitsu Microelectronics literature may be obtained from,

Literature Department

Fujitsu Microelectronics
2985 Kifer Road
Santa Clara, CA 95051

FUJITSU MICROELECTRONICS' CROSS REFERENCE GUIDE
AMD

FMI

INMOS

FMI

AM2716 ...................
AM2732 ...................
AM9016 ...................
AM9147 ...................
AM27S28 ..................
AM27S29 ..................
AM27S32 ..................
AM27S33 ..................
AM27S180 .................
AM27S181C ...............
AM27S185C ...............
AM27S191C ...............

MBM2716
MBM2732
MB8116
MBM2147
MB7123
MB7124
MB7121
MB7122
MB7131
MB7132
MB7128
MB7138

IMS1400 ...................
IMS1420 ................ : ..
IMS2600 ...................
IMS2600 ...................

MB8167
MB8168
MB8264
MB8266A

INTEL

FMI

ELECTRONIC ARRAYS

FMI

2117 ......................
2118 ......................
2147 ......................
2148 ......................
2149 ......................
2164 ......................
2167 ......................
2168 ......................
2716 ......................
2732 ......................
2732A .....................
2764 ......................
3608 ......................
3616 ......................
3628 ......................
3632 ......................
3636-1 ....................

MB8116
MB8118
MBM2147
MBM2148
MBM2149
MB8264
MB8167
MB8168
MBM2716
MBM2732
MBM2732A
MBM2764
MB7131
MB7137
MB7132
MB7142
MB7138

INTERSIL

FMI

EA2716 ................... MBM2716

FAIRCHILD

FMI

F2764 .....................
F4116 .....................
F4164 .....................
F10415 ....................
F10422 ....................
F10470 ....................
F10474 ....................
F93419 ....................
F93450 ....................
F93451 ....................
F93452 ....................
F93453 ....................
F93511 ....................
F98510 ....................
F100422 ...................
F100470 ...................

MBM2764
MB8116
MB8264
MBM10415
MBM10422
MBM10470A
MBM10474
MBM93419
MB7131
MB7132
MB7121
MB7122
MB7138
MB7137
MBM100422
MBM100470

HARRIS

FMI

HM7642 ...................
HM7643 ...................
HM7648 ...................
HM7649 ...................
HM7680 ...................
HM7681 ...................
HM7684 ...................
HM7685 ...................
HM76160 ..................
HM76161 ..................
HM76321 ..................

MB7121
MB7122
MB7123
MB7124
MB7131
MB7132
MB7127
MB7128
MB7137
MB7138
MB7142

HITACHI

FMI

HM4716A ..................
HM4816 ...................
HM4847 ...................
HM4864 ...................
HM6116L ..................
HM6147 ...................
HN25044 ..................
HN25045 ..................
HN25088 ..................
HN25089 ..................
HN25169 ..................
HN462716 .................
HN462732 .................

MB8116
MB8118
MBM2147
MB8264
MB8416
MBM2147
MB7121
MB7122
MB7131
MB7132
MB7138
MBM2716
MBM2732

IM5626 .................... MB7122

MITSUBISHI

FMI

M5L2716 ..................
M5L2732K .................
M5K4116 ..................
M5K4164NS ...............
M5K4164S .................
M58725 ...................

MBM2716
MBM2732
MB8116
MB8264
MB8265
MB8128

MONOlJTHlC
MEMORIES

FMI

6352 ......................
6353-1 ....................
6380 ......................
6381-1 ....................
63100 .....................
63101 .....................
63S1681 ...................

MB7121
MB7122
MB7131
MB7132
MB7127
MB7128
MB7138

MOSTEK

FMI

MK2147
MK2716
MK4116
MK4164
MK4167
MK4516
MK4564
MK4802

...................
...................
...................
...................
...................
...................
............. " ....
...................

MBM2147
MBM2716
MB8116
MB8265
MB8167
MB8117
MB8264
MB8128

MOTOROLA

FMI

MCM2147
MCM2167
MCM2716
MCM4016
MCM4116

MBM2147
MBM8167
MBM2716
MB8128
MB8116

.................
.................
.................
.................
.................

CROSS REFERENCE GUIDE
MOTOROLA (Cont'd)
MCM4516 .................
MCM4517 .................
MCM6664 .................
MCM6665 .................
MCM7642 .................
MCM7643 .................
MCM7681 .................
MCM7685 .................
MCM10146 ................
MCM65116 ................

NATIONAL

FMI
MBM10415
MB7124
MB7123
MB7121
MB7122
MB7132
MB7127
MB7128
MB7137
MB7138
MBM2147
MB8116
MBM2716
MBM2732
MBM27C32
MB8264
MB8118

NEe

FYI

IIPB406 ....................
IIPB426 ....................
IIPB429 ....................
IIPD416 ...................
IIPD446 ...................
IIPD447 ...................
IIPD2118 ..................
IIPD2147 ..................
IIPD2167 ..................
IIPD2716 ..................
IIPD2732 ..................
IIPD4164 ..................

MB7121
MB7122
MB7138
MB8116
MB8416
MB8417
MB8118
MBM2147
MB8167
MBM2716
MBM2732
MB8264

OXI

FYI

M5M2128
M5M2716
M5M2732
M5M2764
M5M3764
M5M5128

.................
.................
.................
.................
.................
.................

PANASONIC

RAYTHEON (Cont'd)
FMI
29651 ..................... MB7128
29653 ..................... MB7128
29681 ..................... MB7138

FMI
MB8117
MB8118
MB8265
MB8264
MB7121
MB7122
MB7132
MB7128
MBM10415
MB8416

DM10415 ..................
DM745472 .................
DM748473 .................
DM745572 .................
DM745573 .................
DM875181 .................
DM875184 .................
DM875185 .................
DM878190 .................
DM875191 .................
MM2147 .........•.........
MM5290 ...................
NMC2716 ..................
NMC2732 ..................
NMC27C32 ................
NMC4164 ..................
NMC5295 ..................

SIGNETICS

FMI

2716 ......................
10415 .....................
10422 .....................
10470 .....................
10474 .....................
100422 ....................
100470 ....................
828137 ....................
825147 ....................
825180 ....................
825181 ....................
825184 ....................
825185 ....................
828190 ....................
825191 ....................
825321 ....................

MBM2716
MBM10415
MBM10422
MBM10470
MBM10474
MBM100422
MBM100470
MB7122
MB7124
MB7131
MB7132
MB7127
MB7128
MB7138
MB7138
MB7142

SUPERTEX

FYI

5M828180 ................. MB7131
5M825181 ................. MB7132
5M828191 ................. MB7138

SYNERTEK
FYI
5Y2128 .................... MB8128
5Y2716 .................... MBM2716

MB8128
MBM2716
MBM2764
MBM2764
MB8264
MB8416

FYI

MN2716 ..............•.... MBM2716

RAYTHEON

(Continued)

FYI

29631 ..................... MB7132
29641 ..................... MB7122
29650 ..................... MB7127

TI

FYI

TBP24541 .................
TBP24581 .................
TBP28542 .................
TBP28586 .................
TBP285166 ................
TM82147H .................
TM52149 ..................
TM52716 ..................
TM54016 ..................
TM84116 ..................
TM84164 ..................

MB7122
MB7128
MB7124
MB7132
MB7138
MBM2147H
MBM2149
MBM2716
MB8128
MB8116
MB8264

TOSIDBA

FYI

TC5516 ...................
TC5517 ...................
TC5518 ...................
TMM315D .................
TMM323C .................
TMM416 ...................
TMM2016 ..................
TMM2732 ..................
TMM4164 ..................

MB8417
MB8416
MB8418
MBM2147
MBM2716
MB8116
MB8128
MBM2732
MB8264

FYI
UM2147 ................... MBM2147

ii

TABLE OF CONTENTS

Cross Reference .............................................................. .
Chapter 1
NMOS Dynamic RAMS
NMOS Dynamic RAM Product Listing ......................................... 1·1
MB8116,16K(16Kx1)NMOSDynamicRAM .................................... 1·2
MB8117, 16K(16Kx 1) NMOS Dynamic RAM ... " ....... '" .................... 1·12
MB8118, 16K(16Kx 1) NMOS Dynamic RAM ... " .............................. 1-24
MB8264,64K(64Kx 1) NMOS Dynamic RAM .................................... 1-33
MB8264A, 64K (64K x 1) NMOS Dynamic RAM .................................. 1-44
MB8265,64K(64Kx1)NMOSDynamicRAM ................................... 1·45
MB8265A,64K(64Kx 1) NMOS Dynamic RAM .................................. 1·58
MB8266A, 64K(64K x 1) NMOS Dynamic RAM ................................ 1·59

Chapter 2
NMOS Static RAMS
NMOS Static RAM Product Listing ............................................ 2·1
MBM2147, 4K (4K x 1) NMOS Static RAM ....................................... 2·2
MBM2148,4K(1Kx4)NMOSStaticRAM ....................................... 2·7
MBM2149, 4K(1 Kx4) NMOS Static RAM ...................................... 2-12
MB8128, 16K(2Kx8) NMOS Static RAM ....................................... 2-17
MB8167, 16K(16 x 1) NMOS Static RAM ....................................... 2-22
MB8167A, 16K(16Kx 1) NMOS Static RAM ..................................... 2-27
MB8168, 16K(4Kx4) NMOS Static RAM ....................................... 2-28

Chapter 3
CMOS Static RAMS
CMOS Static RAM Product Listing ............................................ 3·1
MB8416, 16K(2Kx8) CMOS Static RAM ........................................ 3·2
MB8416·X, 16K(2Kx8) CMOS Static RAM, Extended Temperature Range ............. 3-2
MBB416A, 16K(2Kx 8) CMOS Static RAM ....................................... 3·8
MB8417, 16K(2Kx8)CMOSStatic RAM ............ " .................. , ....... 3-9
MB8417-X, 16K (2K x 8) CMOS Static RAM, Extended Temperature Range ............. 3·9
MB8417A, 16K(2Kx 8) CMOS Static RAM ...................................... 3-15
MB8418, 16K(2Kx8)CMOSStaticRAM ....................................... 3·16
MBB418-X, 16K(2Kx8)CMOSStatic RAM, Extended Temperature Range ............ 3-16
MB8418A, 16K(2Kx8)CMOS Static RAM ...................................... 3-21

Chapter 4
EPROMS
EPROM Product Listing ......................................... " .......... 4·1
MBM2716, 16K(16Kx1) NMOSUV EPROM .......... " .......................... 4·2
MBM2716-X, 16K (16K x 1) NMOS UV EPROM, Extended Temperature Range .......... 4·2
M BM2732, 32K (4K x 8) NMOS UV EPROM ...................................... 4·7
MBM2732A,32K(4Kx8) NMOS UV EPROM .................................... 4·14
MBM2732A-X, 32K (4K x 8) NMOS UV EPROM, Extended Temperature Range ......... 4·14
MBM27C32, 32K(4Kx 8) CMOS UV EPROM .................................... 4·20
MBM2764, 64K (8K x 8) NMOS UV EPROM ..................................... 4·21
MBM2764-X, 64K(8K x 8) NMOS UV EPROM, Extended Temperature Range .......... 4·21
MBM27C64, 64K (8K x 8) CMOS UV EPROM .................................... 4·28

iii

TABLE OF CONTENTS

(Continued)

Chapter 5
Bipolar RAMS
Bipolar RAM Product Listing ................................................ 5·1
MB7072, 1K(256x4) EClBipolar RAM ......................................... 5·2
MBM10415AH, 1K(1Kx 1) ECl Bipolar RAM ..................................... 5·7
MBM10422, 1K(256x4) ECl Bipolar RAM ...................................... 5·12
MBM10422A, 1K (256 x 4) ECl Bipolar RAM .................................... 5·17
MBM10470A, 4K(4Kx 1) ECl Bipolar RAM ..................................... 5·18
MBM10474,4K(1Kx 4) ECl Bipolar RAM ...................................... 5·23
MBM10474A,4K(1Kx4) EClBipolar RAM ..................................... 5·28
MBM10480, 16K (16K x 1) ECl Bipolar RAM .................................... 5-29
MBM93419, 576 (64 x 9) TIL Bipolar RAM ...................................... 5-30
MBM100422, 1K(256x4) ECl BipolarRAM ..................................... 5-34
MBM100422A, 1K (256 x 4) ECl Bipolar RAM ................................... 5·39
MBM100470, 4K (4K x 1) ECl Bipolar RAM ..................................... 5-40
MBM100474, 4K (1 K x 4) ECl Bipolar RAM ..................................... 5-45
Chapter 6
Bipolar PROMS
Bipolar PROM Product Listing ............................................... 6·1
Bipolar PROM Programming Procedures ....................................... 6·2
Bipolar PROM Cross Reference Guide ......................................... 6·7
MB7121,4K(1Kx4)BipolarPROM ......................... , .................. 6-8
MB7122, 4K (1K x 4) Bipolar PROM ............................................ 6-8
MB7123, 4K(512 x8) Bipolar PROM ........................................... 6·15
MB7124, 4K(512 x8) Bipolar PROM ........................................... 6·15
MB7127,8K(2Kx4)BipolarPROM ........................................... 6·18
MB7128, 8K(2Kx4) Bipolar PROM ........................................... 6·18
MB7130, 8K(1K x8) Bipolar PROM ........................................... 6·25
MB7131, 8K(1Kx8) Bipolar PROM ........................................... 6·30
MB7132, 8K (1 K x 8) Bipolar PROM ........................................... 6·30
MB7134,16K(4Kx4)BipolarPROM .......................................... 6·37
MB7137,16K(2Kx8)BipolarPROM .......................................... 6-42
MB7138, 16K (2K x 8) Bipolar PROM .......................................... 6·42
MB7141, 32K(4Kx8) Bipolar PROM .......................................... 6·49
MB7142, 32K (4K x 8) Bipolar PROM .......................................... 6·49
Chapter 7
Generallnformation ......................................................... 7·1
Quality and Reliability Data ............................................... 7·2
Ordering Information ....................................................... 7·6
Package Information ....................................................... 7·7
Representative Listings .................................................... 7·15
Distributor Listings ....................................................... 7·15

iv

Device
MB8116E
MB8116H
MB8117-12
MB8117-10
MB8118-12
MB8118-10
MB8264-2O
MB8264-15
MB8264A-12
MB8264A-10
MB8265-2O
MB8265-15
MB8265A-12
MB8265A-10
MB8266A-12
MB8266A-10

Organization
16K x 1
16K x 1
16K x 1
16K x 1
16K x 1
16K x 1
64K x 1
64K x 1
64K x 1
64K x 1
64K x 1
64Kx 1
64K x 1
64K x 1
64K x 1
64Kx 1

Ac:ce8s
Time

P-

Power

(max)

Supply
Volts

Dissipation

2OOn5
150n5
12On5
100n5
12On5
100n5
2OOn5
150n5
12On5
100n5
2OOn5
150n5
12On5
100n5
12On5
100n5

+12, ±5
+12, ±5
+5
+5
+5
+5
+5
+5
+5
+5
+5
+5
+5
+5
+5
+5

46O/2OmW
46O/2OmW
190/20mW
190120mW
170/20mW
170/20mW
24B122mW
24B122mW
33O/22mW
3OO/22mW
24B122mW
24B122mW
33O/25mW
3OO/25mW
330123mW
33O/23mW

Package

Page

16-pin
16-pln
16-pin
16-pin
16-pin
16-pin
16-pin
16-pln
16-pin
16-pin
16-pln
16-pin
16-pin
16-pin
16-pln
16-pin

1-2
1-2
1-12
1-12
1-24
1-24
1-33
1-33
1-44
1-44
1-45
1-45
1-58
1-58
1-59
1-59.

FUJITSU

:MB8116E
:MB8116H·

MICROELECTRONICS

MOS 16,384·BIT DYNAMIC
RANDOM ACCESS MEMORY
DESCRlPTION
The Fujitsu MB8116 Is a fully
decoded dynamic NMOS random
access memory organized as
16,384 one-blt words. The design
Is optimized for high speed, high
performance applications such
as mainframe memory, buffer
memory, peripheral storage and
environments where low power
dissipation and compact layout
are required.
Multiplexed row and column address inputs permit the MB8116
to be .housed in a standard 16-pln
DIP. Pin-outs conform to the accepted industry standard.

The MB8116 is fabricated using
sillcon-gate NMOS and Fujitsu's
advanced Double-Layer PolysilIcon process. This process,
coupled with single-transistor
memory storage cells, permits
maximum circuit density and
minimal chip size. Dynamic circuitry Is employed in the design,
including the sense amplifiers.

CERDIP PACKAGE
Dlp·16C·C03

Clock timing requirements are
non-critical, and power supply tolerances are 10%. All Inputs are
TTL compatible; the output is
three-state TTL.

FEATURES
• 18,384 x 1 RAM, 18 pin
package
• Stllconlllate, double-poly
NMOS,slngle transistor cell
• Row access tlnie:
200 ns max. (MB8118E)
.150 ns max. (MB8118H)
• Cycle time:
375 n8 min.
• Low power
4$2mW active,
20 mW standby (max.)
• ~10% tolerance on + 12V,
:t 5V supplies
• All Inputs TTL compatible, low
capaCitive load

• Three-atate TTL compatible
output
• "Gated" ~
.128 refresh cycles
• Common UO capability using
"Early Write" operation
• Output unlatched at cycle end
allows extended page
boundary and twOodlmenslonal
chip select
• Read-Modlfy-Wrlte, RA5-0nly
refresh, and Page-Mode
capability
• On-chlp latches for Addresses
and Data-In
• Compatible with MK4118

MB81l6 BLOCK DIAGRAM

PLASTIC PACKAGE
Dlp·16P·M01

PIN ASSIGNYmn'
Vaa

Vss

DIN

CA§

WE

RAS

As

Ao

A3

A2

A4

Al

AS

VDD

.
A,
A,
AI

....
A.

DUMMY CELlS

:

<4

'!

U

t

Vec

D,.

---------- - ---

i.SS

DOUT

This device contains circuitry to protect the
inputs against damage due to high static
voltages or electric fields. However, it Is ad·
vised that normal precautions be taken to
avoid application of any voltage higher than
maximum rated voltages to this high 1m·
pedance circuit.

MEMORY ARRAY

SEN.SE'REFRESH AMPS

MEMORY ARRAY

OUMMYCELLS

1-2

MBSll6E/MB8ll6H
ABSOLUTE MA.XD4OM RATINGS

(see Note)
Symbol

Value

Unit

VIN, VOUT
Voo, Vcc

-0.5 to +20
-0.5 to +15
0
-55 to +150
-40 to +125

V
V
V

Rating
Voltage of any pin relative to VBB
Voltage on VOO, Vcc supplies relative to Vss
VBB·VSS (Voo-Vss

>

-

OV)
ICerdip
I Plastic

Storage Temperature

Tstg

Power Dissipation
Short circuit output current

·C

1.0
50

Po

-

W
mA

RECOMMENDED OPERATING CONDITIONS
(Referenced to VSS)
Parameter

I NOTESI

Symbol

Min

Typ

Max

Unit
V

III

Voo

10.8

12.0

IIJI2l

VCC

4.5

5.0

13.2
5.5

III
ill
III
ill

Vss
VBB

0
-4.5

0
-5.0

0
-5.5

VIHC
VIH

l1J

VIL

2.7
2.4
-1.0

Supply Voltage

Input High Voltage MS, CAS, WE
Input High Voltage except RAS, CAS, WE
Input Low Voltage, all inputs

-

V
V
V

6.5
6.5

V
V

0.8

V

Operating Temperature

O·C to +70·C

STATIC CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.)

INOTES I

Parameter

Min

Max

Units

1001
IBB1

-

35
300

mA
pA

1002
IBB2

1.5
100

mA
pA

25

mA

300

pA

27

mA

IBB4

-

300

pA

ICC

-10

10

pA

IlL

-10

10

pA

OUTPUT LEAKAGE CURRENT
(Data out is disabled, OV oS VOUT oS 5.5V)

IOL

-10

10

pA

OUTPUT LEVELS
Output high voltage (IOH = -5mA)
Output low voltage (IOL = 4.2mA)

VOH
VOL

2.4
0.4

V
V

OPERATING CURRENT
Average power supply current RAS,CAS cycling;tRC
STANDBY CURRENT
Power supply current (RAS

Symbol

= min)

= CAS = VIHC)

REFRESH CURRENT
Average power supply current
(RAS cycling,CAS = VIHC;tRC = min)

1003

PAGE MODE CURRENT
Average power supply current
(RAS VIL, CAS cycling; tpc = 225ns)

10D4

IBB3

=

Vee POWER SUPPLY CURRENT
(Data out is disabled)
INPUT LEAKAGE CURRENT
Input leakage current,any input (VBB
all other pins not under test = OV)

rID
= -5V,OVoS VIN oS 7V,

Notes: 1. All voltages are reference to Vss.
2. Output voltage will swing from Vss to Vee when activated with no current loading. For purposes of maintaining data In the
standby mode, Vee may be reduced to Vss without affecting refresh operations or data retention. However, the VOH(min)
specification Is not guaranteed in this mode.
3. When Data out is enabled, Vee power supply current depends upon output loading; Vee Is connected to the output buffer
only.

1-3

MB8ll6E/MBSll6H
CAPACITANCE
(TA = 25°C)
Parameter

Symbol

Input Capacitance Ao - As, DIN
Input Capacitance RAS, CAS, WE
Output Capacitance DOUT

CIN1
CIN2
COUT

DYNA:MIC CHARACI'ERISTICS

I

Typ

Max

Unit

-

5
10

pF
pF
pF

7

I

NOTES 4, 5, 6
(Recommended Operating Conditions unless otherwise noted.)

MB8118H

MB8118E

INOTES I

Parameter

Units

Symbol
Min

Time between Refresh

tREF

Random ReadlWrite Cycle Time

tRC

Read-Write Cycle Time

tRWC
tpc

Page Mode Cycle Time
Access Time from RAS

!1JrnJ

Access Time from CAS

[]][ID

tRAC
tCAC

Max

-

2

375
375
225

-

-

200

135
50
50

Transition Time

tOFF
tT

RAS Precharge Time

tRP

0
3
120

RAS Pulse Width

tRAS

200

32000

CAS Precharge Time

tRSH
tcp

135

-

CAS Pulse Width

tCAS

CAS Hold TIme

tCSH

Output Buffer Turn Off Delay

RAS

Hold Time

80

CAS to RAS Precharge Time

tCRP

Row Address Set Up Time

tASR

Row Address Hold Time

tRAH

Column Address Set Up Time

tASC

135
200
30
-20
0
25
-5

Column Address Hold Time

tCAH

55

tAR

twcs

120
0
10
-10

tWCH

55

tWCR
twp

120
55

RAS Lead Time

tRWL

Write Command to CAS Lead Time

tCWL

80
80

Data In Set Up Time

tos

L10J

RAS to CAS Delay Time

Column Address Hold Time Referenced to

RAS

tRCO

Read Command Set Up Time

tRCS

Read Command Hold Time

tRCH

!III

Write Command Set Up Time
Write Command Hold Time
Write Command Hold TIme Referenced to

RAS

Write Command Pulse Width
Write Command to

Data In Hold Time
Data In Hold Time Referenced to

tOH

RAS

tOHR

CAS to WE Delay

[11]

tcwo

RAS to WE Delay

!TIl

tRWO

1-4

0
55
120
95
160

-

10000

65

-

Min

-

Max

2

ms

375
375
170

-

ns

-

150
100
50
35

ns

-

ns

32000

ns

-

ns

10000

ns

-

ns

50

ns

-

ns

0
3
100
150
100
60
100
150
25
-20
0
20
-5
45
95

0
10
-10
45
95
45

60
60
0
45
95

70
120

ns
ns
ns
ns
ns

ns

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

MB81l.6E/MB81l6H
Not••: 4. Several cycles are required after power up before proper device operation Is achieved. Any 8 cycles which perform
refresh are adequate for this purpose.
5. Dynamic measurements assume tT
5ns.
6. VIHC(mln) or VIH(min) and Vldmax) are reference levels for measuring timing of Input signals. Also, transition times
are measured between VIHC or VIH and VIL.

=

7. Assumes that tRCO :s; tRCO(max). If tRCO Is greater than the maximum recommended value shown In this table, tRAC
will Increase by the amount that tRCO exceeds the value shown.
8. Assumes that tRCO .. tRCO(max).
9. Measured with a load equivalent to 2 TIL loads and 100pF.
10. Operation within the tRCD(max) limit Insures that tRCO(max) can be met. tRCO(max) Is specified as a reference point
only; If tRCO Is greater than the specified tRCO(max) limit, then access time Is controlled exclusively by tCAC.
11. twos, tcwo and tRWO are not restrictive operating parameters. They are Included In the data sheet as electrical
characteristics only. If twcs .. twos (min), the cycle Is an early write cycle and the data out pin will remain open clr·
cult (high Impedance) throughout entire cycle.
If tcwo .. tcwo(mln) and tRWo .. tRWO(mln), the cycle Is a read·wrlte cycle and data out will contain data read from
the selected cell. If neither of the above sets of conditions is satisfied the condition of the data out Is Indeterminate.

TIMING DIAGRAMS

READ CYCLE

RAS

CAS

ADDRESSES

WE

DOUT

V'L-

V'L-

V'HV'L-

V'L-

VOHVOL-

. . Don't Care

1-5

MB8l16E/MB8U6H

TIMING DIAGRAMS (Continued)
WRITE CYCLE (EARLY WRITE)

VOH-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ OPEN _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
DOUT

VOL

•

Don't Car.

READ-WRITE/READ-MODIFY·WRITE CYCLE

ADDRESSES VI

DOUT

VOH- - - - , . . . - - - - - - - - - - - D F ' E N - - - < I
VOL~--~--=~~---~

£III Don't Care

1-6

MB8ll6E/YB8U6H

TIMING DIAGRAMS (Continued)

''RAS-ONLY'' REFRESH CYCLE
NOTE:

CAS

= VIHC, WE = Don't Care

ADDRESSES

VOH- __________________________ OPEN _______________________________

VOL-

e.,.

•

Don't

•

Don't Ca,.

PAGE-MODE READ CYCLE

RAS

V'HCV'L-

CAS

V'HCV'L-

1-7

MB81l6E/MB8ll6H

TIMING DIAGRAMS

(Continued)

PAGE-MODE WRITE CYCLE

_Don't Car.

DESCRIPTION
Address Inputs:
A total of fourteen binary Input
address bits are required to
decode anyone of 16,384 storage
cell locations within the MB8116.
Seven row-address bits are established on the Input pins (Ao
through As) anq latched with the
Row Address Strobe (RAS). The
seven column-address bits are
established on the input pins and
latched with the Column Address
Strobe (CAS). All input addresses
must be stable on or before the
falling edge of RAS. CAS is internal~ inhibited (or "gated")~
RA to permit triggering of CAS
as soon as the Row Address Hold
Time (tRAH) specification has
been satisfied and the address inputs have been changed from
row-addresses to column-addresses.
Write Enable:
The read mode or write mode is
selected with the WE input. A
logic high (1) on WE dictates read
mode; logic low (0) dictates write

mode. Data Input is disabled
when read mode is selected. WE
can be driven by standard TTL circuits without a pull-up resistor.

Data Input:
Data is written into the MB8116
during a write or read-write~cle.
The last falling edge of WE or
CAS is a strobe for the Data In
(DIN) register. In a write cycle, if
WE is brought low (write mode)
before CAS, DIN is strobed by
CAS, and the set-up and hold
times are referenced to CAS. In a
read-write cycle WE will be
has made its
delayed until
negative transition. Thus DIN is
strobed by WE, and set-up and
hold times are referenced to WE.

CAS

Data Output:
The output buffer is three-state
TTL compatible with a fan-out of
two standard TTL loads. Data-out
is the same polarity as data-In.
The output is in a high impedance
state until CAS is brought low. In

1-8

a read cycle, or a read-write cycle,
the output is valid after tRAC from
transition of RAS when tRCO
(max) is satisfied, or after tCAC
from transition of CAS when the
transition occurs after tRCO
@lax). Data remains valid until
S is returned to a high level. In
a write cycle the identical sequence occurs, but data is not
valid.

Page-Mode:
Page-mode operation permits
strobing the row-address Into the
MB8116 while maintaining RAS at
a logic low (0) throughout all successive memory operations in
which the row address doesn't
change. Thus the power disSipated by the negative going
edge of RAS is saved. Futher, access and cycle times are decreased because the time normally required to strobe a new
row-address is eliminated.

MB8ll6E/MBSU6H
Refresh:
Refresh of the dynamic memory
cells Is accomplished by performing a memory cycle at each of the
128 row-address at least every
two mill i-seconds. Any operation
in which RAS transits accomplishes refresh. RAS-only refresh
avoids any output during refresh
because the output buffer is in
the high impedance state unless
CAS is brought low. Strobing
each of the 128 row-addresses
with RAS will cause all bits in
each row to be refreShed. RASonly refresh results in a substanlal reduction in power
dissipation.

sipation depends mostly on
operating frequency.

Power Conslderetlons:
The output buffer of the MB8116
can be powered via Vee from the
supply voltage (normally 5 volts)
to which the memory is interfaced. In standby operation, Vee
may be removed without affecting refresh. Thus standby power
is conserved because all the
power supplies for the peripheral
circuitry with the exception of
RAS timing and refresh address
is turned off. Most of the MB8116
circuitry, including sense
amplifiers, is dynamic, and most
of the power drain comes from an
address strobe (FiAS or CAS)
edge. Thus, dynamic power dis-

Power Up:

No particular supply sequencing
is required for the MB8116.
However, absolute maximum
ratings must be adhered to. Thus,
VeB should be turned on first and
turned off last, and Voo is turned
on. After power is applied, several
cycles are required before proper
operation is assured. About eight
refresh cycles should be suffi·
cient to accomplish this.

CUrrent Waveforms

= 13.2V, Vee = -4.5V, T.A = 25°e

NOTE: Voo

m

liAS ONLY CYCLE

LONG RASICAS CYCLE

RASICAS CYCLE

r-

M

PAGE MODE CYCLE

- '-r---T_~_lTl

rr-h'

f-I-J '

CAS f-M

-"""\

10
10

,

1\
\

11\

r

IDD
40
(mAl2O

-

o

II

1\

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20
0

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1'1\ II

\

--to,+: ""1-

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40

~+=H-

y ..

t
_-t-~

iii
\

20
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I

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10
10

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--

-h

100

Iss

Ir \

I'r'

lJ

I.J

J

J

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+

rr

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r- -

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,j

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1\

J\

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III

-,.-.+---'-- --1-

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II

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1 -+ -4+

v

(mAI-2O
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11\

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40

II_

!

I

100

--

i'-I.L

_A

1"--.....

I'

5OnalDIVISION

TYPICAL CHARACTERIS'1'ICS CURVES
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vs VOO SUPPLY VOLTAGE

1 1
1 1

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'5

I

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i

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10

NORMALIZED ACCESS TIME
vs VBB SUPPLY VOLTAGE

I

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I
4

5

V cc' SUPPLY VOLTAGE IV)

I
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I
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:MB8ll6E/MB8l16H
TYPICAL CHARACTERISTICS ctJRV!S
NORMALIZED ACCESS TIME
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T j • JUNCTION TEMPI'RATURE ('CI

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r-- ~

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Voo. SUPPLY VOLTAGE (VI

VI

I- Vea = -4.5V

i-"

10

1003 (!tQ-ONLY)
VI CYCLE RATE

zwI-

-

.... ~~

i--'

_80.4

10

C--' Vss = -4.5V

E

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w

>

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2.0 )-. V
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;: 1.6

1.2

20
o
40
80
60
T j • JUNCTION TEMPERATURE ('CI

!

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:(

II:

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I

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1.6

a

30

U

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p~ICAL i

11
12
13
14
Voo.SUPPLY VOLTAGE (VI

1002 (STANDBY)
vs Tj JUNCTION TEMPERATURE

1002 (STANDBY)
Voo SUPPLY VOLTAGE

w

w

>
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L

Voo = 13.2V
Vee =-4.5V
' RC =375n$

Z

II:
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CYCLE RATE (MHzl

....

>
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..;

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o
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20
60
80
Tj. JUNCTION TEMPERATURE ('CI

MB8U6E/MB8U6H

TYPICAL CHARACTERIS'l1CS CURVlS

<
S
I-

zw
u

vs Tj JUNCTION TEMPERATURE

--of T A

30r- - -

"250 C

--r--

t---------- --

>-

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1004 (PAGE-MODE)

vsVoo SUPPLY VOLTAGE

1---_+1-

.J

""-

1004 (PAGE-MODE)

vs CYCLE RATE

I Voo" 13.2V
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40

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20

-ir~

14

0

20

40

60

80

Tj. JUNCTION TEMPERATURE (OC)

I

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I
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3.0 f--- voo '" 10.BVfor V I LC l -I--- r--+-.J
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H
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VIHC. V ILC INPUT LEVELS

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I
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--

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1
2
3
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(Continued)

i

>

-

0

20

40

60

80

Tj. JUNCTION TEMPERATURE 1°C)

FUJITSU

MB8117·10
MB8117·12

MICROELECTRONICS

NMOS 16,384·BIT DYNAlVIIC
RANDOM ACCESS :MEMORY
DESCRIPTION
The Fujitsu MB8117 is a fully
decoded, dynamic NMOS random access memory organized
as 16,384 one-bit words. The
design is optimized for highspeed, high performance applications such as mainframe
memory, buffer memory peripheral storage and environments
where low power dissipation and
compact layout are required.
Multiplexed row and column address inputs permit the MB8117
to be housed in a standard 16-pin
DIP. Pin outs conform to the
JEDEC approved pin out.

The MB8117 Is fabricated using
silicon-gate NMOS and FUjitsu's
advanced Double-Layer Polysilicon process. This process,
coupled with single-transistor
memory storage cells, permits
maximum circuit density and
minimal chip size. Dynamic circuitry is employed In the design,
including the sense amplifiers.
Clock timing requirements are
non-critical, and power supply
tolerance Is very wide. All inputs
are TIL compatible; the output is
three-state TIL.

CERDIP PACKAGE
DIP-16C-C03

FEATURES
• 16,384 x 1 RAM, 16 pin
package
e Silicon-gate, Double Poly
NMOS single-transistor cell
• Address access time
100 ns max (MB8117-10)
120 ns max (MB8117-12)
• Cycle time,
235 ns min (MB8117-10)
270 ns min (MB8117-12)
• Low power:
182 mW max (MB8117-10)
160 mW max (MB8117-12)
19_5 mW max (Standby)
• +5V single power supply,
:t 10% tolerance
• On-chip substrate bias
generator
• All Inputs TTL compatible,
low capacitive load

• Thre.state TTL
compatible output
• Pin 1 auto refresh
capability
• Common 110 capability
using "Early Write"
operation
• Output unlatched at cycle
end allows extended
page boundary and twodimensional chip select
• Read-Modlfy-Wrlte, RA5only refresh, and PageMode capability
• On-chip latches for
Address and Data-In
• Offers two variations of
hidden refresh
• Pin compatible with
MK4516 and MCM4516

MBSH7
"'--r=l~.!:J--~
BLOCK DIAGRAM "'--t-----t--9n

PLASTIC PACKAGE
DIP-16P-M01

PIN ASSIGNMENT
RFSH

Vss

DIN

CAS

WE

3

RAS

""

~I:

....
.='"

:!2
"'III

DOUT

A6

Ao

5

A3

A2

6

A4

AI

7

As

Vee

8

N.C.

0,"

A,
DOUT

A,

A.
A,
-VSS

1-12

This device contains circuitry to protect
the inputs against damage due to high
static voltages or electric fields. However,
It is advised that normal precautions be
taken to avoid application of any voltage
high .than maximum rated voltages to this
high impedance circulI.

MBSl17-10/MBSl17-12

ABSOLUTE MAXIMUM RATINGS

(See Note)

Rating

Symbol

Value

Unit

Voltage on any pin relative to vss
Voltage on VCC pin relative to VSS
I Cerdip
Storage Temperature
I Plastic
Power dissipation
Short circuit output current

VIN, VOUT
VCC

-1 to +7
-1 to +7
-55 to +150
-40 to +125
1.0
50

V
V

Tstg
PD

-

·C
W
mA

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operational should be
restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

RECOMMENDED OPERATING CONDITIONS
(Referenced to VSS)
Parameter
Supply Voltage
Input High Voltage, all inputs
Input Low Voltage, all inputs

Symbol

Min

Typ

Max

Unit

Vcc
Vss
VIH
VIL

4.5
0
2.4
-1.0

5.0
0

5.5
0
6.5
0.8

V
V
V
V

-

Operating
Temperature

O·C to +70·C

CAPACITANCE (TA = 25·C)
Parameter

Symbol

Input CapaCitance Ao - As, DIN
Input CapaCitance RAS, CAS, WE, RFSH
Output CapaCitance DOUT

Typ

Max

Unit

-

5
8
7

pF
pF
pF

CIN1
CIN2
COUT

STATIC CHARACTERISTICS
(Recommended Operating Conditions unless otherwise noted.)

Parameter

INOTES I

OPERATING CURRENT Average Power
Supply Current (RAS, CAS cycling; tRC = Min)
STANDBY CURRENT Power
Supply Current (RAS = CAS = VIH,
DOUT = High Impedance)
REFRESH CURRENT 1 Average Power
~IY Current (RAS cycling,
CA = VIH; tRc = Min)
PAGE MODE CURRENT Average Power
~IY Current 1 (RAS = VIL,
CA cycling, tpc = Min)
REFRESH CURRENT 2 Average Power Supply
Cu~rent (RFSH cycling, RAS = CAS = VIH; tFC =
INPUT LEAKAGE CURRENT
Current, any input (OVs VINS 5.5V)
Input pins not under test = OV,
4.5Vs Vccs 5.5V, Vss = OV
OUTPUT LEAKAGE CURRENT (Data
out is disabled, OV < VOUT <5.5V
OUTPUT LEVEL Output Low Voltage
(lOL= 4.2 mAl
OUTPUT LEVEL Output High Voltage
(lOH = -5 mAl
Notes:

[I

Symbol

MB8117·10
Min
Max

ICC2

-

[I]

ICC3

[I]

[J

m
in)

MB8117·12
Min
Max

Unit

29

mA

3.5

-

3.5

mA

-

25

-

22

mA

ICC4

-

25

-

22

mA

Ices

-

28

-

25

mA

ICC1

33

IlL

-10

10

-10

10

pA

IOL

-10

10

-10

10

pA

VOL

-

0.4

-

0.4

V

VOH

2.4

-

2.4

-

V

Icc Is dependent on output loading. Specified values are obtained with the output open.

1-13

MBS1l7-10/MBS1l7-12

DYNAMIC CHARACTERISTICS 1NOTES 1, 2, 31
(Recommended operating conditions unless otherwise noted.)
Parameter

[@ill

MB 8117·12

MB 8117·10

Symbol

Min

Max

Min

-

Unit

Max

Time Between Refresh

tREF

-

Random Read/Write Cycle Time

235

-

270

-

ns

Read·Write Cycle Time

tRC
t RWC

285

320

-

ns

Page Mode Cycle Time

t pc

125

-

145

-

ns

2

2

ms

Access Time from RAS

@I[§]

t RAC

-

100

-

120

ns

Access Time from CAS

[§]I§]

t CAC

-

55

-

65

ns

Output Buffer Turn Off Delay

tOFF

0

45

0

50

ns

Transition Time

tT

3

50

3

50

ns

-

120

-

ns

RAS Pulse Width

tRP
t RAS

110
115

10000

140

RAS Hold Time

t RSH

70

-

CAS Prechange Time (all cycles except page mode)

t CPN

50

CAS Precharge Time (Page mode only)

tcp

60

-

CAS Pulse Width

tCAS

55

10000

65

CAS Hold Time

tCSH

100
25

CAS to RAS Precharge Time

tRCO
t CRP

0

-

Row Address Set Up Time

t ASR

0

Row Address Hold Time

15

Column Address Set Up Time

tRAH
t ASC

0

Column Address Hold Time

tCAH

15

Column Address Hold Time Referenced to RAS
Read Command Set Up Time

tAR
t RCS

Read Command Hold Time

RAS Precharge Time

-

10000

ns

85

--

ns

55

-

ns

70

-

ns

10000

ns

-

ns

55

ns

0

-

ns

-

0

-

ns

15

-

ns

0

-

ns

15
70

0

-

0

tRcH

0

-

0

-

ns

60

-

0

-

0

30

-

35

-

ns

Write Command Hold Time

twcs
t WCH

Write Command Hold Time Referenced to RAS

t WCR

75

-

90

ns

Write Command Pulse Width

twp

30

35

Write Command to RAS Lead Time

t RWL

60

65

-

ns

Write Command to CAS Lead Time

tcwL

45

-

-

50

-

ns

Data In Set Up Time

tos

0

-

0

-

ns

Data In Hold Time

tOH

30

-

35

-

ns

Data In Hold Time Referenced to RAS

75

-

90

-

ns

55

-

65

-

ns

-

120

-

25

-

ns
ns

RAS to CAS Delay Time

Write Command Set Up Time

iZ]1ill

~

120
25

45

ns
ns
ns
ns
ns

CAS to WE Delay

~

tOHR
t cwo

RAS to WE Delay

~

t Rwo

100
20

RFSH Set Up Time Referenced to RAS

tRRH
t FSR

110

-

120

-

ns

RAS to R FSH Delay

t RFO

110

-

120

-

RFSH Cycle Time

t FC

235

-

270

ns
ns

Read Command Hold Time Referenced to RAS

RFSH Pulse Width
RFSH Hold Time Referenced to RAS

[Q]

RFSH Precharge Time
RFSH to RAS Delay

[Q]

t FP

100

-

120

tFHR

0

-

0

-

tF I

110

-

120

-

ns

tFRO

55

-

65

-

ns

1-14

ns
ns

MBSl17-10/MBSl17-12
Notes:

ill

[]J

ill

An initial pause of 200,.s is required. Then several cycles
are required after power up before proper device operation Is achieved. Any 8 cycles which perform refresh are
adequate for this purpose.
If Internal refresh counter is to be effective, a minimum
of 64 active RFSR Initialization cycles Is required. The
Internal refresh counter must be activated a minimum of
128 times every 2 ms if the RFSH refresh function Is used.
Besides RFSH must be held high even If the RFSH
refresh function is not used.
Dynamic measurements assume tT

Assumes that tRCO

> tRCO(max).

Measured with a load equivalent to 2 TTL loads and
100pF.
Operation within the tRCO(max) limit insures that
tRAC(max) can be met. tRCO(max) is specified as a
reference pOint only; if tRCO Is greater than the specified
tRCO(max) limit, then access time is controlled exclusively by tCAC.
tRAC(mln)

= tRAH(min) + 2IT + tASC(mln).

twcs, tcwo and tRWO are not restrictive operating
parameters. They are included In the data sheet as electrical characteristics only. If twcs > twcs(min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout entire
cycle. If tcwo > tcwo(min) and tRWO > tRWO(min), the
cycle Is a read-write cycle and data out will contain data
read from the selected cell. If neither of the above sets
of conditions Is satisfied the condition of the data out Is
indeterminate.

=5ns.

VIH(min) and Vldmax) are reference levels for measurIng timing of Input signals. Also, transition times are
measured between VIH and VIL'
Assumes that tRCO < tRCO(max). If tRCO is greater than
the maximum recommended value shown In this table,
tRAC will increase by the amount that tACO exceeds the
value shown.

Test mode write cycle only.

READ CYCLE

VIH- - - - - ' " I-----'AR-----

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