1982_Harris_Linear_and_Data_Acquisition_Products_Vol_3 1982 Harris Linear And Data Acquisition Products Vol 3

User Manual: 1982_Harris_Linear_and_Data_Acquisition_Products_Vol_3

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Volume' 3

-

~

,.

,

rinear';i ta~cq\Jisition.Communications'Linear'DataAc~uisiti·O


DIE CAVITY

~~z' BONDINGPA~~
~=~~di~

EXTERNAL CONTACTS

1)1""'---_ _ TRACES

.

DIEPAD_

~

LEAD LONGEST TRACE DIP
COUNT LONGEST TRACE CC

EXTERNALCONTACTPADS:;J

.-

PROGRAMMABLE

HIGH INPUT
IMPEDANCE

HA-2725
HA-2740
HA-8023
LM346,
,LM4250 '
LM4250C

LM4250
LM4250C
LH24250C
LM346

HA.:ooail

LF347
LF351
HA-60s2
LF353
LF355
·IiA~,50!i4
~~,.5100 , LF356
LF357
iHA~160
,HA'$170,
LHOO52
HA'-5180 LHOO42
LF342;
LHOOn
'LF~7 ','
LF13741

HA:.0ua4

TL066

TL081
TL062
TL064
TL082
TL084

PM355
PM356
PM357
OP-17
OP-16

LM346

A0515
A0545

IlA776
IlA776C

IlAF355
IlAF356
J.LAF357

3522
3523
3527
3528

,1.\=353 '
'l..F':$5:,'

.}~J'
HIGH VOLTAGE

,fiA~4s
"~'

~M~

"-;,.

.

3581J
3571A
3572A
3580J

"

HIGH POWER

}J.A:;~

<.'-:."\

.:~

1-j"-t>"

~:~_

: -:~~'
'~

CA3094

3571 A
3554AI8
3580J
3583
3581

".

"

GENERAL
PURPOSE

i')

-I

·HA:4741
iHA-4156
~,.LM34a::
,HA~2656

IlA759
IlA759C

RC4156

_,f,

--

-----

OJ

•

-

rj

~

~

Operational Amplifiers Glossary
AVERAGE INPUT OFFSET CURRENT DRIFT (.lIOS/.lT)
- The ratio of the change in the offset current to the change
in temperature producing it.

input signal or load.
Input offset voltage may also be
defined for the case where two equal resistances are inserted in series with the input leads.

AVERAGE OFFSET VOLTAGE DRIFT ( tl VOS/ .:1 TI
- The ratio of the change in the offset voltage to the
change in temperature producing it.

INPUT NOISE VOLTAGE (enl - The input noise voltage
that would reproduce the noise seen at the output if all
the amplifier noise sources and source resistances were
set to zero.

BANDWIDTH (BW) - That frequency at which the gain
of the amplifier is 3dB below ,its low frequency value.
CHANNEL SEPARATION - The ratio' of the input of a
driven amplifier to the output of an adjacent undriven
amplifier.

•

COMMON MOD,E INPUT VOLTAGE (VIC) - The average
'of the two input voltages.
COMMON MODE INPUT VOLTAGE RANGE (VICR)
- The range of voltage that if exceeded at either input
terminal will cause the amplifer to cease operating
properly.
COMMON MODE REJECTION RATIO (CMRR) - The
ratio of the differential voltage gain to the common mode
voltage gain.
Note: This is measured by determining the ratio of the
change in input common-mode voltage to the resulting
change in offset voltage.
COMMON MODE RESISTANCE (ric) - The value of
resistance looking into both inputs tied together.
DIFFERENTIAL INPUT RESISTANCE (rid) - The value
of resistance between two ungrounded inputs.
FULL POWER BANDWIDTH (FPBW) - The maximum
frequency at which a full size undistorted sine wave can
be obtained at the output of the amplifier.
GAIN BANDWIDTH PRODUCT - The product of the
gain and bandwidth at some specified frequency.
INPUT BIAS CURRENT (lBIAS) - The average of the
currents flowing into the input terminals when the output is at zero voltage.
INPUT CAPACITANCE (CIN) - The capacitance of either
input with the other grounded.
INPUT NOISE CURRENT (ill) - The input noise current
that would reproduce the noise seen at the output if all
amplifier noise sources were set to zero and the source
impedances were large compared to the optimum source
impedance.
INPUT OFFSET CURRENT (lOS) - The difference in the
currents flowing into the two input terminals when the
output is at zero voltage.
INPUT OFFSET VOLTAGE (VOS) - The differential
D.C. voltage required to zero the output voltage with no

2-2

INPUT RESISTANCE IRIN) - The ratio of the change
in input voltage to the change in input current at either
terminal with the other grounded.
LARGE SIGNAL VOLTAGE GAIN (Av) - The ratio of
the peak to peak output voltage swing (over a specified
range) to the change in input voltage required to drive the
output.
OUTPUT CURRENT (lOUT) - The output current available from the amplifier at some specified output voltage.
OUTPUT RESISTANCE (RO) - The ratio of the change in
output voltage to the change in output current.
OUTPUT SHORT CIRCUIT CURRENT (lSC) - The
maximum output current available from the amplifier
with the output shorted to ground (or other specified
potential) •
OUTPUT VOLTAGE SWING (VOUTI - The peak to peak
output voltage swing, referred to ground, that can be obtained without clipping under specified loading conditions.
OVERSHOOT - Peak excursion above final value of an
output step response.
POWER SUPPLY REJECTION RATIO (PSRR) - The ratio
of the change in input offset voltage to the change in power
supply voltage producing it.
RISE TIME Itr)
- The time required for an output
voltage step to change from 10% to 90% of its final value,
when the input is subjected to a small voltage pulse.
SETTLING TIME - The time required, after application
of a step input signal, for the output voltage to settle and
remain within a specified error band around the final
value.
SLEW RATE (SR) - The rate of change of the output
ullder large signal conditions. Slew rate may be specified
separately for both positive and negative going changes.
SUPPL Y CURRENT (IS) - The current required from the
power supply to operate the amplifier with no load and the
output at zero volts.
SUPPLY VOLTAGE RANGE - The range of power supply
voltage over which the amplifier may be safely operated.
UNITY GAIN BANDWIDTH - The frequency range from
D.C. to that frequency where the amplifiers open loop
gain is unity.

m1 HA.RRIS

HA-160B
+IDV Adjustable Voltage
Reference

FEATURES

DESCRIPTION

•

MONOLITHIC CONSTRUCTION

•

INITIAL ACCURACY

•

OUTPUT VOLTAGE ERROR, TOTAL

±.1/4 LSB

•

LOW NOISE

20IlVp_p

•

WIDE INPUT RANGE

•

LOW POWER DISSIPATION

•

OUTPUTSHORT CIRCUIT PROTECTION

•

+10V ± 0.010V

12V TD 30V
30mW

These devices provide a total output voltage error of ±. 1/4 LSB for 8
bit D/A or A/D converters. Low standby power (O.3mW) makes HA1608 a natural selection for portable battery operated equipment,
comparator references, and reference stacking circuits. These devices
can also be used on -10V references.

ADJUSTABLE OUTPUT

APPLICATIONS
•

HA-1608 is a monolithic +10V adjustable voltage reference featuring
accuracy and temperature stability specifications detailed exclusively
for 8 bit data conversion systems. A stable +10V output is provided by
a reference zener and buffer amplifier coupled with laser trimmed feedback and zener bias resistors. Long term stability is ensured through
integration of all reference components into a monolithic design. Flexibility of HA-1608 is provided through an external trim control which
allows the user to adjust the output voltage for binary or BCD applications without affecting overall performance.

AN ECONOMICAL EXTERNAL REFERENCE FOR:
HI-5608; DAC 08; AD1408; AD559

•

VOLTAGE REGULATOR REFERENCE

•

PORTABLE BATTERY OPERATED EQUIPMENT

•

NEGATIVE 10V REFERENCE

PINOUT

HA-1608 is packaged in 8 pin metal cans (TO-99) and the pinout
is arranged for convenient replacement of other less accurate
regulators in applications demanding minimal change with temperature
and time. HA-1608-2 is specified for -55 0C to +125 0C operation
while the HA-1608-5 operates from OOC to +750C.

FUNCTIONAL SCHEMATIC
Section 1.1 for Packaging

TOP VIEW

NC
~---+-.rl--o TRIM

OUT
Y,N
---i

,-vVIN

.....---C::J---

13

0-

300

V

~

,,'"
zo

~

>

:~
a;o
>-~
wo
",>«0
>-w

V'

"-

~200

;:;
z

::8

vV'

5
~
5 100

... 0:
00:

0 '0

100

lK

10K

7

"s

~

R-1001C

rT~-

r-- t-

•

t--

10
9

"0

7

V

lL

10K

1M

100K

GND

11

8

~~

V

OUT

12

...>w

~

v~~

VIN

1'\

lOOK

RS -Ohms

1M

FREQUENCY - Hz

OUTPUT WIDEBAND NOISE VS. BANDWIDTH

OUTPUT VOLTAGE TRIM VS. RS
10pV

lS

OUTPUT NOISE (O.IHz TO 10Hz)

APPlICA TlONS
TYPICAL HOOK-UP WITH
OUTPUT TRIM

161

GND

31

*

OUT
R2*

+

rs--I

-4:-

I6tT
HA-I60B
+

~

GND
3

Rl'
5

-

*NOTE: Rl potentiometer value can be
10K to lOOK R2 can range from 10K
to 2M

:!:10V REFERENCE

1[+15V
1
7
VIN

If+ 15V
1
7
VIN
6

11+15V
1
7
VIN
HA-I608

NEGATIVE 10 VOLT REFERENCE

HA-I60B

-

~ lKn*
~

10Kn

GND
3

-V(-15V TYP)

5Kn

-==

+10V

10K.~

~
HA5130

'::iiiv

-1~b

*NOTE: The value of R may reduce the
output current available to less than that
specified on the data sheet.

2-5

m

HA-2400/2404/2405

H.A.RRIS

PRAM Four Channel
Programmable Amplifier

FEATURES
•

PROGRAMMABILITY

•

HIGH SLEW RATE

DESCRIPTION
3DV/IlS
4DMHz

• WIOE GAIN BANDWIDTH

•

150,000

•

HIGH GAIN

•

LOW OFFSET CURRENT

•

HIGH INPUT IMPEDANCE

•

SINGLE CAPACITOR COMPENSATION

•

DTlITTL COMPATIBLE INPUTS

5nA
3.DMn

APPlICA T/ONS
• THOUSANDS OF NEW APPLICATIONS; PROGRAM
SIGNAL SELECTION/MULTIPLEXING
OPAMP GAIN
OSCILLATOR FREQUENCY
FILTER CHARACTERISTICS
ADD-SUBTRACT FUNCTIONS
INTEGRATOR CHARACTERISTICS
COMPARATOR LEVELS

PINOUT
TOP VIEW

HA-24DO/24D4/24D5 comprise a series of four-channel
programmable amplifiers providing a level of versatility unsurpassed by any other monolithic operational amplifier. Versatility is achieved by employing four input amplifier channels,
anyone (or none) of which may be electronically selected and
connected to a single output stage through DTL/TTL compatible
address inputs. The device formed by the output and the
selected pair of inputs is an op amp which delivers excellent
slew rate, gain bandwidth and power bandwidth performance.
Other advantageous features for these dielectrically isolated
amplifiers include high voltage gain and input impedance coupled with low input offset voltage and offset current. External
compensation is not required on this device at closed loop
gains greater than 1D.
Each channel of the HA-24DD/2404/24D5 can be controlled and operated with suitable feedback networks in any of
the standard op amp configurations. This specialization makes
these amplifiers excellent components for multiplexing, signal
selection, and mathematical function designs. With 30V / Il s
slew rate, 40MHz gain bandwidth, and 30M ohms input impedance these devices are ideal building blocks for signal generators,
active filters, and data acquisition designs. Programmability
coupled with 2mV typical offset voltage and 5nA offset current
makes these amplifiers outstanding components for signal
conditioning circuits.
HA-240D/2404/2405 are available in a 16 pin dual-in-line
package. HA-24DO is specified from -55 0 C to +125 0 C. HA2404 is specified over the -25 0 C to +85 0 C range, while HA24D5 operates from OOC to +75 0 C.

SCHEMATIC
Section 11 for Packaging

Condensed circuit diagram for a programmable amplifier
(PRAM HA-24001

TRUTH TABLE

0,

SELECTED
CHANNEL

DO

EN

L

L

H

1

L

H

H

2

H

L

H

3

H

H

H

4

X

X

L

NONE

Diagram includes: ONE INPUT STAGE, DECODE CONTROL,
BIAS NETWORK AND OUTPUT STAGE

2-6

SPECIFICA TIONS
ABSOLUTE MAXIMUM RATINGS
Voltage Between V+ and V- Terminals

45.0V

Differential Input Voltage
Digital Input Voltage
Output Current

±VSupply

Internal Power Dissipation
(Note 13)
Operating Temperature Range

-0.76V to +10.0V
Short Circuit Protected
USC ~ ± 33mA)

Storage Temperature Range

ELECTRICAL CHARACTERISTICS

Offset Voltage
Bias Current (Note 12)
Offset Current (Note 12)
Input Resistance (Note 12)
Common Mode Range

-55°C ~ TA ~ +125°C (HA·2400)
-25°C ~ TA ~ +85 0C (HA·2404)
OoC ~ TA ~ +75 0C (HA·240S)
-65°C ~ TA ~ +lS00C

Test Conditions: VSuppl y = ±15.0V unless otherwise specified.

Digital inputs' VIL = +0 5V VIH =+2 4V
limits apply to each of the
fou r channels, when addressed.
PARAMETER
INPUT CHARACTERISTICS

300mW

TEMP.

HA·2400/HA·2404
LIMITS
MIN.
TYP.
MAX.

MIN.

HA·2405
LIMITS
TYP.

MAX.

UNITS

+25 0 C
Full

4

9
11

4

9
11

mV
mV

+25 OC
Full
+25 0C
Full
+25 0C

50

200
400

50

250
500

nA
nA

5

50
100

5

50
100

nA
nA
MQ

30

Full

±9.0

+2SoC
Full
Full
+25 0C
+25 0C

SOK
2SK
80

150K

20
4

Full

30

lEI

V

±9.0

TRANSFER CHARACTERISTICS
Large Signal Voltage Gain (Note 1,5)
Common Mode Rejection Ratio (Note 2)
Gain Bandwidth (Note 3)
(Note 4)
OUTPUT CHARACTERISTICS
Output Voltage Swing (Note 1)
Full Power Bandwidth (N otes 3, 5)
(Notes 4,5)

+2SoC
+25 0C
+25 0C

TRANSIENT RESPDNSE
Rise Time (Notes 4,6)

+25 0C

Output Current

Overshoot (Notes 4,6)

+25 0 C

Slew Rate (Notes 3,7)
(Notes 4,7)

+2SoC
+2SoC

Settling Time (Notes 4, 7, 8)

+2SoC

150K

100

50K
25K
74

100

V/V
V/V
dB

40
8

20
4

40
8

MHz
MHz

±10.0
10

±12.0

±10.0

±12.0

V

20

10

20

rnA

200
100

SOO
200

200
100

SOD
200

kHz
kHz

20
25
20
6

4S
40

30
8

20
6

1.S

2.5

Full

1

1.S

5

Dutput Delay (Note 9)

Full
+2SoC

Crosstalk (Note 10)

+2SoC

POWER SUPPLY CHARACTERISTICS
Supply Current

+2SoC

Power Supply Rejection Ratio (Note 11)

Full

CHANNEL SELECT CHARACTERISTICS
Digital Input Current (VIN = OV)
Digital Input Current (VIN = +5.0V)

NOTES: 1.
2.
3.
4.
5.
6.
7.

-BO

RL = 2Krl
VCM = ±5V.D.C.
Av = +10, CCOMP = 0, RL = 2Krl, CL = 50pF
Av = +1, CCOMP = 15pF, RL = 2Krl. CL = 50pF
VOUT = 20V peak·to·peak
VOUT = 200mV peak·to·peak
VOUT = 10.0V peak·to·peak

74

ns

20

SO

25

40

%

1.5

2.5

V/J.ls
V/J.ls
J.ls

1

1.5

rnA

3D
B

nA

S

100
-110

250

4.8

6.0

100
-74

90

-110
4.B

74

ns

250

dB
S.O

rnA

90

dB

8. To 0.1 % of final value
9. To 10% of final value; output then slews at normal
rate to final value.

to. Unsele.cted input to output; VIN

= ±10 V.D.C.
11. VSUPP = ±10V.D.C. to ±20V.D.C.
12. Unselected channels have approximately the same
input parameters.

13. Derate by 4.3mWf'JC above 1050 C

2-7

CHARACTERISTIC CURVES
V+

= 15VDC,

= 15VDC,

V-

TA = 25°C UNLESS OTHERWISE STATED.

INPUT BIAS CURRENT AND OFFSET
CURRENT AS A FUNCTION OF TEMPERATURE

NORMALIZED A.C. PARAMETERS
VS. TEMPERATURE

140

1.2

u

\

0

120

'"+

I~)

N

\

100

1\

~..

"",

0
0

..'"

0

>

.~

."'" -~
0

+25

+50

+15

""

0.9

0;

E
0

Z
08

+100 +125

-551-50 -25

Temperature (DC)

•

"- ~

-0

:--.....

-551-50 -25

1.0

0;

r---,

5

O~

SLEW RATE

a:

-........... ~~RRENT

0

~

1.1

E
-0

0

+25

+50

Temperature (DC)

"'" ~

+15 +100 +125

OPEN LOOP FREQUENCY AND PHASE RESPONSE

iii
~

120

..

~

'00

POWER SUPPLY CURRENT DRAIN
AS A FUNCTION OF TEMPERATURE

'.

80
60

.. ..
"

'.

r-.
r::::-

......

-

40

"OOV~

VSUPPLV'
vSUPPLY" .:!:.15 OV
I-VSUPPLV'

!100V~

c:

~

~

'"

U

>
c.

c.
o
o

20

c

-20
10

-'

~

le t;::::-

~

~

o

CcOMP - OpF
- - - CCOMP '" tSpF

'00

'20

'"'"

'n;

'00

c

'"
E

'0

-551-50 -25

0

+25

+50

>

+15 +100 +125

Co

0
0

Temperature (DC)

80

'"

0

NORMALIZED A.C. PARAMETERS
VS. SUPPLY VOLTAGE

'OK

ItlmrrlOOK

'"

I

{

po...

-

120
150

'.

'OM

2'0

100M

jj,

60
40
20

-20
'0

~~~;I·~+t~~~~~~~I,~ijillW-rH~
!

1111111 1IIIIIIiI"°"[1
'00

'OK

'K

'OaK

'M

'OM

,OOM

Frequency (Hz)

OPEN LOOP VOLTAGE GAIN
VS. TEMPERATURE

1.2

.s

1.1

-0

~

..
'"
...

.f!

a:

1.0

/"" ~

0;

>

-0

~

r

BANDWIDTH I

--

/sLEW RATE/

5~-+--~--~-+--~--~-+~

O.9

i

E
o

z

o.8
±.10

±15

Supply Voltage

2-8

!20

90 -551-50

i

-25

+25

+50

+75

Temperature (DC)

+100

~

C

'E>

c

'1..."..'c.~

o"

O. I
10K

lOOK

1M

01
100Hz

10M

Frequency (Hz)

TRANSIENT RESPONSE

~oomJ
OV
OVERSHOOT

10kHz

100kHz

SelECTED

CDMP

15pF

CHANNel

INPUT

1---f--......--o1'15DV

-S.OV
+5.0V===~-:"

>+--+1--ip--oOUT

II ERROR
I BAND

'0%

I

I :t.l0mV FROM
: FINAL VALUE

1-1So0V

-----------1I

J

!

,

II

SLEW RATE AND TRANSIENT RESPONSE

.5'0~

OUTPUT

---t
1

lMHz

Upper 3dB Frequency
Lower 3dB Frequency· 10Hz
Broadband Noise Characteristics

SLEW RATE AND SETTLING

L

INPUT

I IIII
1kHz

I

SETTLING TIME
Measured on both posItive and
negatlvetranslttons.

200D

TYPICAL APPLICATIONS
AMPLIFIER, NON-INVERTING PROGRAMMABLE GAIN

SAMPLE AND HOLD

INPUT

15pF

[}------'<"--o +15V

>---{]---_t---oOUTPUT

>--U---~--o OUTPUT

'K
11

Sample charging rate = C V/sec.
12
Hold drift rate = C V/sec.
Switch pedistal error =

2 Volts

11~150xlO-6A
12 ::::200 x 10-9 A@+250 C
::::600 x 10-9 A @ -55°C
~100 x 10-9 A@+1250 C
0::::2 x 10-12 Coul.

FOR MORE EXAMPLES, SEE HARRIS APPLICATION NOTE 514

2-9

mI H.A.RRIS

HA-2500/02/05
Precision High Slew Rate
Operational Amplifiers

FEATURES

DESCRIPTION

• HIGH SLEW RATE

30V//lS

330ns

• FAST SETTLING

500kHz

• WIDE POWER BANDWIDTH
• HIGH GAIN BANOWIDTH

12MHz

• HIGH INPUT IMPEDANCE

50M!1
10nA

• LOW OFFSET CURRENT
• INTERNALLY COMPENSATED

APPlICA TIONS
• DATA ACQUISTION SYSTEMS
• R.F. AMPLIFIERS

These dielectrically isolated amplifiers are ideally suited for
applications such as data acquisition, R.F., video, and pulse
conditioning circuits. Slew rate of ±25V / /l sand 330ns (0.1%)
settling time make these devices excellent components in fast,
accurate data acquisition and pulse amplification designs. 12
MHz bandwidth and 500kHz power bandwidth make these
devices well suited to R.F. and video applications. With 2mV
typical offset voltage plus offset trim capability and 10nA
offset current, HA-250012502/2505 are particularly useful
components in signal conditioning designs.
The gain and offset voltage figures of the HA-2500 series are
optimized by internal component value changes while the
similar design of the HA-2510 series is maximized for slew rate.

• VIDEO AMPLIFIERS
• SIGNAL GENERATORS

HA-2500/250212505 are available in metal can (TD-99) packages. HA-2500 and HA-2502 are specified over the. -55 0 C to
+125 0 C range.
HA-2505 is specified from OOC to +75 0 C.

• PULSE AMPLIFICATION

PINOUT

SCHEMATIC
Section 11 for PackBging
COMPENSATION

TOP VIEWS

vBALANCE

2-10

HA-2500/250212505 comprise a series of monolithic operational amplifiers whose designs are optimized to deliver excellent
slew rate, bandwidth, and settling time specifications. The
outstanding dynamic features of this internally compensated
device are complemented with low offset voltage and offset
current.

COMPENSATION

IN-

v+

INt

OUT

v-

BALANCE

SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
Voltage Between V+ and V- Terminals
Differential Input Voltage
Peak Output Current
Internal Power Dissipation

Operating Temperature Range - HA·2500/HA·2502
HA·2505
Storage Temperature Range

40.0V
±15.0V
50mA
300mW

-55°C ::;TA :::; +125 0 C
OOC :::; TA :::; +75 0 C
-65°C:::; TA:::; +150 oC

ELECTRICAL CHARACTERISTICS
V+

= +15V D.C., V- = -15V D.C.
HA·2500
-55°C to + 125°C
LIMITS
MIN.
TYP.
MAX.

HA·2502
-55°C to + 125°C
LIMITS
MIN.
TYP.
MAX.

HA·2505
OOC to +75°C
LIMITS
MIN.
TYP.
MAX.

+25 0 C
Full

2

4

4

Full

20

Bias Current

+25 0 C
Full

100

200
400

125

250
500

125

250
500

nA
nA

Offset Current

+25 0 C
Full

10

25
50

20

50
100

20

50
100

nA
nA

PARAMETER.

TEMP.

UNITS

INPUT
CHARACTERISTICS
Offset Voltage
Offset Voltage Average Drift

5
8

8
10

20

8
10

mV
mV

f.1V/oC

20

+25 0 C

25

Full

±10.0

+25 O C
Full

20K
15K

30K

15K
10K

25K

15K
10K

25K

V/V
V/V

Common Mode Rejection
Ratio INote 21

Full

80

90

74

90

74

90

dB

Gain Bandwidth Product
INote 31

+25 0 C

12

MHz

Input Resistance (Note 10

J

Common Mode Range

TRANSFER
CHARACTERISTICS
Large Signal Voltage Gain
INote 1,41

OUTPUT
CHARACTERISTICS
Output Voltage Swing
INote 11

50

20

50

20

±10.0

12

MQ

50

V

±10.0

12

Full

±10.0

±12.0

±10.0

±12.0

±10.0

±12.0

V

Output Current INote 41

+25 0 C

±10

±20

±10

±20

±10

±20

mA

Full Power Bandwidth
INote 41

+25 0 C

350

500

300

500

300

500

kHz

TRANSIENT RESPONSE
Rise Time INotes 1, 5, 6 & 81

+25 0 C

25

50

25

50

25

50

ns

Overshoot INotes 1,5.7 & 81 +25 0 C

25

40

25

50

25

50

%

Slew Rate INotes 1,5,8& 121 +25 0 C
Settli~g

T\me to 0.1%
INote'J ,5,8 & 121
POWER SUPPL Y
CHARACTERISTICS
Supply Current
Power Supply Relection
Ratio INote 91
NOTES:

±25

±30

+25 OC

0.33

+25 0 C

4

Full

1. RL=2K
2. VCM =± 10V
3. AV >10
4. VO=:t:l0.0V
5. CL = 50pF
6. Vo=:t:200mV

80

±20

6

4
74

90

±. 200mV

8. See transient response test
circuits and waveforms page four.
9.
V = :t:5.0V

.1

±20

0.33

90
7. Va

±30

6

±30

V/f.1s

0.33

f.1s

4
74

II

90

6

mA
dB

10. This parameter value is based on
design calculations.
11. Full power bandwidth guaranteed based
on slew rate measurement using
FPBW = S.R./21T Vpeak.
12. VOUT=±5V

2-11

PERFORMANCE CURVES
V+

= 15VDC, V- = 15VDC, T A = 250C UN LESS OTH ERWISE STATED
INPUT BIAS AND OFFSr:r CURRENT
vs TEMPERATURE

EQUIVALENT INPUT NOISE
vs BANDWIDTH

'00
D

1'--- ~~cuRRe~T

D



u

~FSETCURRENT

D

-4 D
50

2S

0

+25

V

1

r---..

D

-,

~"sj~: E::~~:~:CC.:

'\

+50

+15

'"

+100

01

100Hz

+12~

1kHz

NORMALIZED AC PARAMETERS
vs TEMPERATURE

,

•

--

SLEW

lMHl

OPEN-LOOP FREQUENCY AND PHASE RESPONSE

om

12

i'---

100kHz

10kHz

Upper 3dB Frequency
Lower 3dB Frequency - 10Hz

Temperature DC

""
"'CI

lATE

rt::::--

g. .:
.3 ~

IIIIII

100

30"

111111

eo

pJ~~E

t--

60

h.

0

BANOWIDTH

9

1\

0

K

·20
100

10

1k

100k

10k

1M

10M

60"

'"
c;,

9 0"

~

1200

~

50"6:

1

1BO"
100M

Frequency Hz
8

-50

-25

0

+25

+50

+15

+100

+125

Temperature DC

OPEN LOOP FREQUENCY RESPONSE FOR
VARIOUS VALUES OF CAPACITORS FROM
COMPENSATION PIN TO GROUND

NORMALIZED AC PARAMETERS
vs SUPPL Y VOLTAGE AT +25 0 C

"

120
BANOWIDT,

ID

/"
D9

I
f

~

-- -----

-

f-- :.--- ~

SLEwRAIe

;'

II

100

""
§".:
"'CI

80

0.,

eo

....It!:!

OpF

...:::

30pF
100pF

F-..

a; &

40

~~

i--.

20

.....:

lOOp"

>

"

111111
111m

111m

-2 0
10

1k

100

t.....:

1000pF I

10k

lOOk

1M

10M

100M

Frequency Hz
NOTE: External compensation components are not required for

DB
tiD

±2D

.tIS

stability. but may be added to reduce bandwidth if desired.

Supply Voltage

OUTPUT VOLTAGE SWING
vs FREQUENCY AT +25 0 C

OPEN LOOP VOLTAGE GAIN
vs TEMPERATURE
ViPPLy

J

.±.20OV

Y .,

t-

./'. t;::--'
""
"'CI

,

90

C

~V

VSUPPL!~.!l!OV

V

o

...,., '"C "
CT ~
t7~
...,!9

.,-

",0

a..

>

!'"

~201

",.-

V

'0;
t!:!

•

VS~PL Ls ov

-llllllllri
v SUPPLY-±15V

20

1111111111

• v ;U;~L~ ~1~oJ
0

[\

•
8D

-50

-25

0

+25

+50

Temperature DC

2-12

+15

+100

+12!i

~OK

lOOK

lMEG

10MEG

Frequency Hz

PERFORMANCE CURVES (continued)
PO WE R SUPPLY CU RRENT
vs TEMPERATURE

,

VOLTAGE FOLLOWER PULSE RESPONSE
-

/

«

E

1

c::

'1-- -

~~
p---~

VSUPPLV - j:.1QOV

~
::1

U

~

-50

tZS

-25

Temperature

SLEW RATE AND
SETTLING TIME

":J

II ERROR
t BAND
I tlOmV FROM
: FINAL VALUE
1

:

50

~~

/

I--'

15

....

V
.

100

.,

RL; 2Krl ,CL ; 50pF
Upper Trace: Input
Lower Trace: Output

25

°c

TRANSIENT RESPONSE

L

INPUT

-5.0V

SETTLING TIME

--

~~~::~:: ~~:~~~

SLEW RATE AND
TRANSIENT RESPONSE

~

I'"
Vertical; 5V/Div.
Horizontal = 200ns/Div.
TA= +25 0 C, Vs = ± 15.0V

II

SUGGESTED
VOS ADJUSTMENT

L
OVERSHOOT

1

1

OUT

1

I
I--RISE TIME
I NOTE

Mea',,"dan 00lhpc"f ...... nd
neg3I,v.lrln"uon.

2-13

mHARRIS

HA-2510/2512/2515
High Slew Rate
Operational Amplifiers
DESCRIPTION

FEATURES
60V//J.s

• HIGH SLEW RATE

250ns

• FAST SETTLING

1,000kHz

• WIDE POWER BANDWIDTH

•

•. HIGH GAIN BANDWIDTH

12MHz

• HIGH INpUT IMPEDANCE

100Mn

The HA-25l0125l212515 are a series of high performance
operational amplifiers which set the standards for maximum
slew rate, highest accuracy and widest bandwidth for internally
compensated monolithic devices. In addition to excellent
dynamic characteristics, these dielectrically isolated amplifiers
also offer low offset current and high input impedance.

10nA

• LOW OFFSET CURRENT

The ±60VI /J.s slew rate and 250ns (0.1%) settling time of these
amplifiers is ideally suited for high speed D/A, AID, and pulse
amplification designs. HA-25l0/2512/25l5's superior 12MHz
gain bandwidth and 1000kHz power bandwidth is extremely
useful in R.F. and video applications. For accurate signal conditioning these amplifiers also provide 10nA offset current, coupled with 100Mn input impedance, and offset trim capability.

• INTERNALLY COMPENSATED

APPLICA TIONS

• DATA ACQUISITION SYSTEMS

The HA-25l0/2512 are available in metal can (TO-99) and
14-pin flat packages. HA-2510 and HA-25l2 are specified from
-55 0C to +125 0C. HA-2515 is specified over the OOC to +750C
range, and is available in the TO-99 package.

• R.F. AMPLIFIERS
• VIDEO AMPLIFIERS
• SIGNAL GENERATORS
• PULSE AMPLIFICATION

PINOUT

SCHEMATIC
Section 11 for Packaging
COMPENSATION

BALANCE

2-14

COMPENSATION

IN-

v+

IN+

OUT

v-

BALANCE

SPECIFICATIOIVS
ABSOLUTE MAXIMUM RATINGS
40.0V
Voltage Between V+ a~d V- Terminals
.±15.0V
Differential Input Voltage
Operating Temperature Range
HA·2510/HA·2512
-55 0C<;. TA'$. +125 0C
HA·2515
OOC <;.TA ~+750C

Peak Output Current
Internal Power 0 issipation
Storage Temperature Range

50mA
300mW
-650C<;'TA~+1500C

ELECTRICAL CHARACTERISTICS
V+ = +15V D.C., V- = 15V D.C.

HA·2510
-55°C to +125 0 C
LIMITS
MIN.
TYP.
MAX.

HA·2512
-55°C to +125°C
LIMITS
MIN.
TYP.
MAX.

HA·2515
OOC to +75 0 C
LIMITS
MIN.
TYP.
MAX.

+25 0 C
Full

4

5

5

Full

20

Bias Curren.t

+25 0 C
Full

100

200
400

125

250
500

125

250
500

nA
nA

Offset Current

+25 0 C
Full

10

25
50

20

50
100

20

50
100

nA
nA

Input Resistance {NotelOI

+25 0 C

50

Full

±10.0

+25 0 C
Full

10K
7.5K

15K

7.5K
5K

15K

7.SK
5K

15K

V/V
V/V

Full

80

90

74

90

74

90

dB

12

MHz

±12.0

V

TEMP.

PARAMETER

UNITS

INPUT CHARACTERISTICS
Offset Voltage
Offset Voltage Average Drift

Common Mode Range

8
11

10
14

25

40

100

10
14

±10.0

Mil

100

40

II

J.lV/oC

30

100

mV
mV

V

±10.0

TRANSFER CHARACTERISTICS
Large Signal Voltage Gain (Note 1,41
Common Mode Rejection Ratio
(Note 2)
Gain BandWidth Product (Note 3)

+25 0 C

12

12

OUTPUT CHARACTERISTICS
Output Voltage Swing (Note

1)

Full

±10.0

±12.0

±10.0

±12.0

±10.0

Output Current (Note 4)

+25 0 C

±10

±20

±10

±20

±10

±20

rnA

Full Power BandWidth (Note 4, 11)

+25 0 C

750

1000

BOO

1000

BOO

1000

kHz

TRANSIENT RESPONSE
Rise Time (Notes 1,5, B& 8)

+25 0 C

Overshoot (Notes 1,5,7 & 8)

+25 0 C

Slew Rate (Notes 1,5,8 & 121

+25 0 C

Settling Time (Notes 1, 5, 8 & 121

+25 0 C

±50

25

50

25

40

±B5

±40

0.25

25

50

25

50

±BO

±40

0.25

25

50

25

50

n,
%

±60

VI Jls

0.25

Jls

POWER SUPPLY CHARACTERISTICS
Supply Current

+25 0 C

Power Supply RejectIOn RatiO (Note 9)
NOTES:

Full

4
80

1. R = 2K
2. V~M = ± 10V
3. AV >10
4. Vo = ~ 10.0V
5. C L = 50pF

6. Vo =:!; 200mV

90

4

B
74

90

7. V 0 = l: 200mV
8. See transient response test
circuits and waveforms
9. ,1 V = ~5.0V

4

B
74

6

90

rnA
dB

10. This parameter value is based
upon design calculations.
11. Full power bandwidth guaranteed

based upon slew rate measurement
FPBW = S.R./2TTVpea k.
12, VOUT

= ± 5V

2-15

PERFORMANCE CURVES
V+

= 15VDC, TA = 250C UNLESS OTHERWISE STATED.
INPUT BIAS AND DFFSET CURRENT
vs. TEMPERATURE

."a

.,a

'

........

.,a
.,a
.,a
a
-1 a

-50

-

EQUIVALENT INPUT NOISE
vs. BANDWIDTH

-BIAS CURRENT

I--.

----

-25

+25

II 1111

~O~S6URC~:::"STANCE

i-!.FFSETCURRENT

+50

+15

l---'

1

~
+100

11111

+125

Temperature DC

II

01
100Hz

1kHz

11111111
10kHz

100kH,

lMHz

lower 3dB Frequency - 10Hz

NDRMALIZED AC PARAMETERS
vs. TEMPERATURE

•

k':

1

OPEN LOOP FREQUENCY AND PHASE RESPONSE

-

~

a

t---

SLEW RATE

a0
10o

$

LlJl

0

•

,....,

1111

I-

BANDWl~

•

IIIIPHASE"

r-::

0

II

60'

0
0

09

10

_55-50

." ."

-25

+-75

-1-1(10

120 0

~

-20

08

900

r-.

lK

100

10K
lOOK
Frequency Hz

1M

10M

150'
180'

100M

+125

Temperature DC

OPEN LOOP FREQUENCY RESPONSE FOR
VARIOUS VALUES OF CAPACITORS FROM
COMPENSATION PIN TO GROUND

NDRMALIZED AC PARAMETERS
vs. SUPPLY VDLTAGE
110

1

sLJ.I--BANDWIT~

r:=
09

'll

g~

/'

a

...Jc;I

~t

BANDWIDTH

~ t;;7

1~~1I1I

100

I--

>

8

o~

30pF
IOOpF

60

r-.

40

300pF
1000pf

20 I-

~EWRATE

'"'-

100

10

....;

I'"'-

Ill"'"

-20

t'"'-

lK

10K

lOOK

1M

r-....
10M

100M

~requency Hz

NOTE: External compensation components are not required for

a,'

stability, but may be added to reduce bandwidth if desired.

±IDV

±15V

±2DV

Supply Voltage

OPEN LOOP VOLTAGE GAIN
vs. TEMPERATURE
a

,
so

OUTPUT VOLTAGESWING
vs. FREQUENCY AT +25 0 C

,

~rDvl

V ~ k.:LY'±1DV

: II 11111i"l

.,<

VSUPPLy=±15V

----

V/ V

a

,

-,,~ SUPPLY = ±15V
V SUPPLY =±lDV

II

111111

VSUPPlY='± lDV

a

\

,
"
2-16

-55 -50

-25

."

'5O

Temperature DC

."

+100

+125

a

10K

Ii
10K

lMEG

lOMEG

Frequency Hz

g.
c(

~

PERFORMANCE CURVES (continued)
POWER SUPPLY CURRENT

VOLTAGE FOLLOWER PULSE RESPONSE

vs
TEMPERATURE

,
«

h

0

E

'r- ~ ~~::~ ~: ~~~~ "VSUPPLY'!10V .......

6

.-:

.
,

-;::::.. f--"

-15

.......: ~ '7

~ ~ ::::-0

'15

."

Temperature

/
.15

.100

v

.125

°c
RL = 2K n , CL = 50pF
Upper Trace: Input
Lower Trace: Output

SLEW RATE AND
SETTLING TIME

TRANSIENT RESPONSE

L

.'~
INPUT

-50V

:I ERROR
I BANI)
!

I

dV!/JT

:

''SETTLING TIME/

"-

---

Vertical = 5V/Div.
Horizontal = 100n/Div.
TA =+25 0 C, Vs =±15.0V

•

SUGGESTED
VOS ADJUSTMENT

L
OVERSHOOT

--------

I +10mV FROM
-50V=ISLEW: FINAL VALUE
I L••n .... RATE;: I

I

SLEW RATE AND
TRANSIENT RESPONSE

'" '"

OUT
i--RISE TIME
I NOTE

::!;~~~;:~,~~.~~~.pO''''~. and

2-17

HA-2520/22/25
Uncompensated High Slew
Rate Operational Amplifiers
FEATURES

DESCRIPTION
120V!p.s

• HIGH SLEW RATE

200ns

• FAST SETTLING

2,OOOkHz

• WIDE PDWER BANDWIDTH

•

• HIGH GAIN BANDWIDTH

20MHz

• HIGH INPUT IMPEDANCE

100Mn

• LDW OFFSET CURRENT

10nA

120V! P. s slew rate and 200ns (0.1%) settling time of these
amplifiers make them ideal components for pulse amplification
and data acquisition designs. These devices are valuable components for R.F. and video circuitry requiring up to 20MHz
gain bandwidth and 2MHz power bandwidth. For accurate
signal conditioning designs the HA-2520!252212525's superior
dynamic specifications are complimented by 10nA offset current, 100 Mn
input impedance and offset trim capability.

APPlICA TIONS

• DATA ACQUISITION SYSTEMS
• R.F. AMPLIFIERS

The HA-2520!2522 are available in metal can (TO-99) and
14-pin flat packages. HA-2520 and HA-2522 are specified
over -55 0 C to +125 0 C range. HA-2525 is specified from
OOC to +75 0 C, and is available in the TO-99 package.

• VIDEO AMPLIFIERS
• SIGNAL GENERATORS
•

PULSE AMPLIFICATION

PINOUT

SCHEMATIC
COMPENSATION

TOP VIEWS

Section 11 for Packaging

vBALANCE

2-18

HA-2520/2522/2525 comprise a series of monolithic operational amplifiers delivering an unsurpassed combination of
specifications for slew rate, bandwidth and settling time. These
dielectrically isolated amplifiers are controlled at closed loop
gains greater than 3 without external compensation. In additon,
these high performance components also provide low offset
current and high input impedance.

COMPENSATION

IN-

v+

IN+

OUT

v-

BALANCE

SPECIFICA TIONS
ABSOLUTE MAXIMUM RATINGS
40.0V
Voltage Between V+and V- Terminals
±15.0V
Differential Input Voltage
Operating Temperature Range
-55 0 C:5; T A ~ + 125 0 C
HA-252012522
OOC :5;TA:5;+75 0 C
HA-2525

50mA
300mW

Peak Output Current
Internal Power Dissipation
Storage Temperature Range

ELECTRICAL CHARACTERISTICS
V+ = +15V D.C., V- = -15V D.C.
HA·2520
-55°C to +125 0 C
LIMITS
MIN.
TYP.
MAX.

HA·2522
-55°C to + 125°C
LIMITS
MIN.
TYP.
MAX.

HA·2525
OOC to +75 0 C
LIMITS
TYP.
MIN.
MAX.

+25 0 C
Full

4

5

5

Full

20

Bias Current

+25 0 C
Full

100

200
400

125

250
500

125

250
500

nA
nA

Offset Current

+25 0 C
Full

10

25
50

20

50
100

20

50
100

nA
nA

Input Resistance (Note 9)

+25 0 C

50

Full

±10.0

+25 0 C
Full

10K
7.5K

15K

7.5K
5K

15K

7.5K
5K

15K

V/V
V/V

Full

80

90

74

90

74

90

dB

+25 0 C

10

20

10

20

10

20

MHz

Full

±10.0

±12.0

±10.0

±12.Q

±10.0

±12.0

V

+25 0 C

±10

±20

±1O

±20

±1O

±20

mA

+25 0 C

1500

2000

1200

1600.

1200

1600

kHz

.'

PARAMETER

TEMP.

UNITS

•

INPUT CHARACTERISTICS
Offset Voltage
Offset Voltage Average Drift

Common Mode Range

8
11

10
14

25

40

100

/lV/oC

30

100

40

mV
mV

10
14

Mn

100

±10.0

±10.0

V

TRANSFER CHARACTERISTICS
Large Signal Voltage Gain (Note 1,41
Common Mode Rejection Ratio
(Note 2)
Gain Bandwidth Product (Note 3)
OUTPUT CHARACTERISTICS
Output Voltage Swing (Note 1)
Output Current (Note 4)
Full Power Bandwidth (Note 4,10)
TRANSIENT RESPONSE

(AV =+3)

Rise Time (Notes I, 5, 6 & 8)

+25 0 C

25

50

Overshoot (Notes I, 5, 6 & 8)

+25 0 C

25

40

Slew Rate (Notesl,5,8& 11)

+25 0 C

Settling Time (Notes I, 5, 8 & 11)

'+25 0 C

±100

±120

l

±80

25

50

25

50

ns

25

50

25

50

%

±80

±120
0.20

0.20

±120

V//ls

0.20

/ls

POWER SUPPLY CHARACTERISTICS
Supply Current

+25 0 C

Power Supply Rejection Ratio (Note 7i
NOTES:

1. RL = 2K
2,V CM =±IOV

3. AV

> 10

Full

4
~n

4. VO=±IO.OV
5. C L = 50pF
6. Va =::t200mV

90

6

4
74

L! V = ±5.0V
8. See transient response test

7.

circuits and waveforms

6

4
74

90
9.

6

90

mA
dB

This parameter value is based
upon design calculations.

10. Full power bandwidth guaranteed
based upon slew rate measurement
FPBW = S.R./27TV pea k.
II. VOUT=::t5V

2-19

PERFORMANCE CURVES
V+ = 15VDC. V-

= 15VDC. TA = 250C UNLESS OTHERWISE STATED

INPUT BIAS AND OFFSET CURRENT
vs TEMPERATU RE

."

0

'\,.

.....

.,

0

,

VSJpPlY-,j:'15V

"JeuR"t. _ I -



~~
~

111111
111111

0

.....
..

""

0

c'm

0

c.""
o c::

mU

SLEW

~>O

~ATe...,....

............-

.s ~
~ ~ +1 09I----l_-t-_+_+----1I--t_BA_~_DWI_1D-TH___1

-g

SLEWRA.lE

§~

0

c:: 0>
0>."
c. ..
o

>

0
0

100

'"

-25

-551-50

.25

.50

_15

+\00

+125

Temperature °c

OPEN LOOP FREQUENCY RESPONSE FOR VARIOUS
VALUES OF CAPACITORS FROM BANDWIDTH CONTROL
PIN TO GROUND

NO RMALIZED AC PARAMETERS
vsSUPPLY VOLTAGE AT+250C

""
c.""

~
BANDWIDTH

v.r;:::~E

" -"

,
7

,

""c::
I

~8

OPEN LOOP VOLTAGE GAIN
vs TEMPERATURE

0

...J",

c:: 0>
0>."
c. ..
O.!::
o

"u~t

-

...

-,0

-25

."

~

1-."
I
..

........

"'...........

t2'
-........
~

-55-50

0

'25

..,

r-

1IIIIIOO(lpF
0

11111

10~F

:Ii

I

''''

"

Frequency Hz

VSUp~~;t!!±20V

30

II I.I I.

vsupp

I",
00>

........

,../

to.....

30(lpF
0

36

...........

vsulLy,!,J;:,L

lO"

~

0

.. c::
~'3:

Temperature °c

2-20

DPFIIII

I--.

OUTPUT VOLTAGE SWING
vs FREQUENCY AT +25 0C

3

1

o'n;

Supply Voltage

5

4

11111111

0

o c::

>

VSUprLY-~

a:>

0
0

1

sJowlOL

10
0..>

+100

+125

II

20

•

III

II III

VSUPPLV='±10V

0

•
0

.5

""

1

'"

Frequency Hz
01

,'"

1

1111
1111

oal--t--I--+--I-----l--t--+--4

Z~

0'

G~

0

-,

0'

J II

...J",

O.!::

30'

,
,

PHA~~II

'D.

'00'

1MECl

10MEG

Frequency Hz

10M

100M

0>

c;,
c::

,.,,,,e ~"<1

TYPICAL APPlICA T/OIVS
10K

COMPENSATION CIRCUIT FOR INVERTING UNITY GAIN

.AAA

10K
INO

.AA
.vv

'>

2K

~

FT

Slew Rate

:::::

120V/\ls

Bandwidth

:::::

10MHz

Settling Time:::::

500ns

500 P

-2-21

HA-2530/2535

mHARRIS

High Slew Rate, Wideband
Inverting Amplifier
FEATURES

DESCRIPTION
±320V!J,ls

•

HIGH SLEW RATE

•

FAST SETTLING TIME

550ns

•

WIDE POWER BANOWIOTH

5MHz

•

HIGH GAIN BANDWIDTH PRODUCT

•

LOW OFFSET VOLTAGE

•

LOW POWER SUPPLY CURRENT

70MHz

APPlICA TIONS

• PULSE AMPLIFI
conditioning, signal generation, and coaxial driver applications.
The HA-2530 and HA-2535 are available in metal can (TO-99)
packages. HA-2530 is specified over the -55 0 C to +125 0 C
range while HA-2535 is specified from OOC to +75 0 C.
•

INTEGRATORS

PINOUT

SCHEMATIC
Section 11 for Packaging

TOP VIEW

,--l-'---t---t-®COMP
Case tied to V-

2-22

SPECIFICA TIONS
ABSOLUTE MAXIMUM RATINGS
Voltage Between V+ and V- Terminals

40V

Peak Output Current

±100mA

Internal Power Dissipation (Note 1)
Operating Temperature Range

550mW

Storage Temperature Range

-650C~TA~+1500C

-550C~TA~+1250C
00C~TA~+750C

(HA-2530l
(HA-2535)

ELECTRICAL CHARACTERISTICS
Test Conditions: VSuppl y = ±15.0V Unless Otherwise Specified.

HA-2530
-55°C to +125 0C
LIMITS
PARAMETER

TEMP.

MIN.

TYP.

HA-2535
OOC to +75 0C
LIMITS

MAX.

MIN.

TYP.

MAX.

UNITS

INPUT CHARACTERISTICS
+25 0C
Full

Offset Voltage

0.8

0.8
5

3

mV
mV

Full

5

5

Bias Current

+25 0C
Full

15

15

5

Input Resistance

+25 0C
Full
+25 0C

2

2

Input Capacitance

+25 0C

10

10

pF

2Xl0 6

V/V
V/V

100

dB

I

Offset Current

100

200

nA
nA

20

nA
nA

5
20

•

].lV/oC

Average Offset Voltage Drift

Mil

TRANSFER CHARACTERISTICS
Large Signal Voltage Gain (Notes 2,5)

2Xl0 6

+25 0 C
Full

10 5

Common-Mode Rejection
Ratio (Note 3)

Full

86

Gain Bandwidth Product (Note 4)

+25 0C

105
80

100
70

MHz

70

OUTPUT CHARACTERISTICS
Output Voltage SWing (Note 2)

Full

±10

±12

±10

±12

Output Current (Note 5)

+25 0C
+25 0C

±25

±SO

±25

±SO

Full Power Bandwidth (Note 5)

4

5

4

V
mA
MHz

5

TRANSIENT RESPONSE (NOTES 6& 7)
Rise Time

+25 0 C

20.

40

20

40

ns

Overshoot

+25 0C
+25 OC .±280
+25 0C

30

45

30

50

%

Slew Rate
Settl ing Time

±320

±250

500

±320

V/tJs
ns

500

POWER SUPPLY CHARACTERISTICS
Supply Current

+25 0C

Power Supply Rejection Ratio (Note 8)

Full

NOTES: 1. Derate at 5.5mW/oC for Operation at
Ambient Temperature Above 7SoC.
2. RL = 2K
3. V CM = ±S.OV
4. AV>lO

3.5
86

100

8

3.5
80

100

8

mA
dB

5. Va =±10V

6. C L = 50pF
7. See Transient Response Test Circuit
and Wave Forms

a. Av

=:!:5.0V

2-23

PERFORMANCE CURVES
V+ = 15VDC, V- = 15VDC, TA = 250C UNLESS OTHERWISE STATED

.,

INPUT BIAS AND OFFSET CURRENT
vs. TEMPERATURE

6

""

.,,
ct·,
c

I

.

r--

.........

"'"""'-

t::

-r--....

" •
.25C
,
.,
.
55ClSQIIC

,

DC

.

25C

,

SOC

Temperature DC'

E

~

.. u

.
......- •

~~

g."o

-"c.:"

w

2

I

E ..

£~D

"

~>
~S

,
looe

Upper 3dB Frequency
Lower 3dB Frequency - 10Hz
OPEN-LOOP FREQUENCY
,
",I-.
",
..........

z

_551S0C
uc_ g

.25,

. .

o
25,
50,
Temperature DC

,
.75

,
•
,
.,,

"00

,
+125

10

.

"

't;;

"">

5~
'S !.I

......
E ..

0
"

SL:~

ZTE

E

o

2

./

10.

lOOK

10M

.,

-..

3

"

2

t::

u

·

-

VSUPf'Ly"tI5V

VSU~PLp

/~

~V

~

~

-;::::::. :::;;...--

,

,2

,
tI.

.20

,

OUTPUT VOLTAGE SWING

"'.lIIIIfBI
r--

!f~

oa

,

25

50"

Temperature DC

Supply Voltage

J!~, en.~g'

,,'

VSUPPLy*:!:2DV

VSUPPly=tI5V

101~IVlsu~PPjLYi'i:!:10ivl~IIIII~~~~1

~ ~ "~mll'II~!I""~I'I
Frequency Hz

,

15

'O'

100M

~ -:;:::
~

.

,,.. .c:
,so· "-

..........

1M

c

Ii!

./

vs. FREQUENCY AT +25 0 C

2-24

10K

VSUPPLy"!20~,

E

c

"

1K

...

~

.. «

9

POWER SUPPLY CURRENT
vs TEMPERATURE

«

~

:i Bo

'"" '" "-- N\

•

BANOWIDTH

~E.o 6

"g>

PHASE

6

I

BAJWI~TH

0

3O'

,..

Frequency Hz

NORMALIZED AC PARAMETERS
vs SUPPLY VGLTAGE AT +25 0 C

~

,

CL*5Dpf

.......

..........

0

6

CC· 7pf
RL'"ZK_

..... -'' ' ::'IN

,'\..

SLEW RATE

AND PHASE RESPONSE

. . . r-..,.

,1\

SLEW RATE

E
o

...

'H,

10011,

12!iC

P

'.'~ -;:?

,

V

....

2

~

""0'"

.2: ~

CoCo

. '"

1SC

16

NORMALIZED AC PARAMETERS
vs TEMPERATURE

·

"C

i"-..

:~: ~! ~!~~~ '!'

liE

.. ;:t

OFFSET CURRENT

u

·,

1:>

BIASc!RRENT

..........

•

1:

........

EQUIVALENT INPUT NOISE
vs. BANDWIDTH

PERFORMANCE CURVES (continued)
UNITY GAIN PULSE RESPONSE

SETTLING TIME MEASUREMENT *1

\
\.

~

\.
',,I~

~

'/

\

VERTICAL
= 5mV/DIV.
HORIZONTAL = 100ns/DIV.
TA = +25 0 C, Vs = ±15V

UPPER TRACE: INPUT
VERTICAL
LOWER TRACE: OUTPUT HORIZONTAL
TA = +25 0 C, Vs = ±15V

SLEW RATE/SETTLING TIME/TRANSIENT RESPONSE TEST CI RCUIT

¥

'I vE

t

2K

2K

SI'~I
'(

31': 9
2KI' 1

.

2K
IN

50n

620 n.

+5mV __
-5mV- -

INPUT
-4.5V
OUTPUT- - -

1t

~50PF

'!V=6~t

-4.5V

I
-I
.!T

I SLEW .!V,
I RATE=:;rrI
1_

SETTLING TIME
+5V

:r

-

•
r --

_ I +TS

1-

- - - -I-\. - - - - - .

-v - - - -

1-

~--

5MHz VIDEO AMPLIFIER (AV = 10)

IN0LI
-5V
+5v
ERROR BANO
OUTPUT - - tlOmV FROM
FINAL VALUE
-5V

t.
f

TRANSIENT RESPONSE
OV:Lj

3:;
1\

-- - --

OVERSHOOT
90% I

I
I I
_ : : _ RISE TIMP

~

500n
IN().A c/'

,-~

-400mV

'MEASUREO ON BOTH POSITIVE
ANO NEGATIVE EXCURSIONS.

= 5V/DIV.
= 50ns/DIV.

"1 Settling time (TS) is measured using a high speed high
recovery oscilloscope to display the error voltage V E.
When V E is within ±5mV of final value the output Va
will be within ±10mV (0.1%).
*2 S1 closed for settling time.

~

SLEW RATE
+4.5V~

\-r-

-I-Ts

-=

rovo

250PF f

-

I

II

455 n

~~F

10%

-=

~T

::: r=: 50pF
2Kn

-=

2-25

HA-2539
Preliminary
FEATURES

•

GENERAL DESCRIPTION
600V/ps

•

VERY HIGH SLEW RATE

•

OPEN LOOP GAIN

30kV/V

•

WIDE GAIN-BANDWIDTH

600MHz

•

POWER BANDWIDTH

9.5MHz

•

LOW 0 FFSET VOLTAGE

•

INPUT VOLTAGE NOISE

•

The Harris HA-2539 represents the ultimate in high slew rate
wideband, monolithic, operational amplifiers. It has been designed and constructed with the Harris high frequency BIPDIP
(Bipolar dielectric isolation process), and features dynamic parameters never before available from a truly differential device.

3mV
15nV/jih

± 10V

OUTPUT VOLTAGE SWING

APPlICA TlONS
•

PULSE AND VIOEO AMPLIFIERS

•

WIDEBAND AMPLIFIERS

•

HIGH SPEED SAMPLE-HOLO CIRCUITS

•

RF OSCILLATORS

PINOUT

With a 600V/ fols slew rate and a 600MHz gain-bandwidthproduct, the HA-2539 is ideally suited for use in video and RF
amplifier designs. Full ± 10V output swing coupled with outstanding A.C. parameters and complemented by high open loop
gain makes these devices useful in high speed data acquisition
systems.
The HA-2539 is available in the 14 pin CEROIP. The HA2539-2 denotes -55 0 C to +125 0 C operation while the HA2539-5 operates over the OOC to +75 0 C range.

SCHEMATIC
Section 11 for Packaging

TOP VIEW
+INPUT
N.C.

2-26

Very High Slew Rate
Wideband
Operational Amplifiers

-INPUT
N.C.

-VSUPPLY

N.C.

N.C.

N.C.

N.C.

+ VSUPPLY

N.C.

N.C.

N.C.

OUTPUT

SPECIFICA TIONS
ABSOLUTE MAXIMUM RATINGS (Note

1)

Voltage between V+ and V- Terminals
Differential I nput Voltage
Output Current
Internal Power Dissipation (Note 2)
Operating Temperature Range: (HA-2539-2)
(HA-2539-5)
Storage Temperature Range

ElECTR ICAl CHARACTERISTICS

35V
6V
50mA (Peak)
870mW (Cerdip)
-55 0C-.---oOUT
90011

I

100n

AV= 10
'CL~10pF

~

LARGE SIGNAL RESPONSE

SMALL SIGNAL RESPONSE
Vertical Scale: (Volts: 50mV/Div.)
Horizontal Scale: (Time: 10ns/Div.)

Vertical Scale: (Volto: A = 1.0V/Div.• B = 2.0V/Div.)
Horizontal Scale: (Time: 20ns/Div.)
2V

50mV

20no

10no

...

SETTLING TIME TEST CIRCUIT

2oon-INPUT

"'~h
...

f---l.J""

j.t

Oo-......,....,,,NII'-.......- -

•

soon--

-=-

lr

14

h

lj.tF

...

POINT

2-28

OUTPUT

~';lJl-F-~---.......
J..'-OpROBE

-v
SETTLE

•

-

.-

I

MONITOR

Load Capacitance should be less than 10pF.

** It

is recommended that resistors be carbon composition and

that feedback and summing network ratios be matched.

•••

SETTLE POINT (Summing Node) capacitance should be less
than 10pF. For optimum settling time results, it is recommended that the test circuit be constructed directly onto the
device pins. A Tektronix 568 Sampling Oscilloscope with S-3A
sampling heads is recommended as a settle point monitor.

m~RIS

HA-2540

Preliminary
FEATURES

GENERAL DESCRIPTION
400V//ls

• VERY HIGH SLEW RATE
•

Wideband, Fast Settling
Operational Amplifiers

2500s

FAST SETTLING TIME

400MHz

• WIDE GAIN-BANDWIDTH

6MHz

• POWER BANDWIDTH
•

LOW OFFSET VOLTAGE

5mV

•

INPUT VOLTAGE NOISE

15nV/0h

•

OUTPUTVOLTAGESWING

•

MONOLITHIC BIPOLAR CONSTRUCTION

±10V

APPLICA TIONS
•

PULSE AND VIDEO AMPLIFIERS

•

WIDEBAND AMPLIFIERS

•

HIGH SPEED SAMPLE-HOLD CIRCUITS

•

FAST, PRECISE D/A CONVERTERS

PINOUT

The Harris HA-2540 is a wideband, very high slew rate, monolithic operational amplifier featuring superior speed and bandwidth characteristics. Bipolar construction coupled with dielectric
isolation allows this truly differential device to deliver outstanding performance. Additionally, the HA-2540 has a drive
capability of ±10V into a lK ohm load. Other desirable
characteristics include low input voltage noise, low offset voltage,
and fast settling time.

•

A 400V I jJS slew rate ensures high performance in video and
pulse amplification circuits, while the 400MHz gain-bandwidthproduct is ideally suited for wideband signal amplification. A
settling time of 250ns also makes the HA-2540 an excellent
selection for high speed Data Acquisition Systems.
The HA-2540-2 is specified over the -55 0 C to +125 0 C range
while the HA-2540-5 is specified from OOC to +75 0 C.

SCHEMATIC
Section 11 for Packaging

TOP VIEW

2-29

SPECIFICA TIONS
ABSOLUTE MAXIMUM RATINGS (Note 1)
Voltage between V+ and V- Terminals
Differential Input Voltage
Output Current
Internal Power Dissipation (Note 2)
Operating Temperature Range: (HA-2540-2)
(HA-2540-5)
Storage Temperature Range

ELECTRICAL CHARACTERISTICS

35V
6V
50mA (Peak)
870mW (Cerdip)
-550C< TA <+125 0C
00C-,..---0 OUT

BoOn
200n

~

LARGE SIGNAL RESPONSE

SMALL SIGNAL RESPONSE

Vertical Scale: IVolts: A = 4.0V/Div.,·B = B.OV 10iv.1
Horizontal Scale: (Time: 100nslOiv.1

Vertical Scale: (Volts: A=50mV/Oiv., B=100mV/Oiv.)
Horizontal Scale: (Time: 100nslOiv.)

II
B

A

r+

VIN~
-2.0V

A

2 •0V

"
II,

\

J
I

~+--+~r-+-~-+--~;--+~
L-..L--l..--''--..L-...:J:..---L__L-...I--l..--'

SETTLING TIME TEST CIRCUIT
+v(

.001"F

-k;"h

f lrt

400{l·*
....
INPUTQ",-1.........1'111'-...,...---/..1'"

•

-

-

OUTPUT

>--....,...-~-o

+

=

.001 .. F

i4h
I"F

-v

•

** It is recommended that resistors be carbon composition and
that feedback and summing network ratios be matched.

..l.' PROBE

I

MONITOR

Load Capacitance should be less than 10pF.

•••

SETTLE POINT (Summing Node) capacitance should be less
than 10pF. For optimum settling time results, it is recommended that the test circuit be constructed directly onto the
device pins. A Tektronix 56B Sampling Oscilloscope with S-3A
sampling heads is recommended as a settle point monitor.

SETTLE
POINT

5Kn"

2-31

m

HA-2600/2602/2605

H.ARRIS

WideBand, High Impedance
Operational Amplifiers
FEATURES

•

DESCRIPTION

• WIDE BANDWIDTH

12MHz

• HIGH INPUT IMPEDANCE

500Mn

• LOW INPUT BIAS CURRENT

InA

• LOW INPUT OFFSET CURRENT

InA

• LOWINPUTOFFSETVOLTAGE

0.5mV
1.50K VIV

• HIGH GAIN

7V/ps

• HIGH SLEW RATE
• OUTPUT SHORT CIRCUIT PROTECTION

APPLICA TlONS

HA-2600/2602/2605 are internally compensated bipolar operational amplifiers that feature very high input impedance (500
Mn, HA-2600l coupled with wideband AC performance. The
high resistance of the input stage is complemented by low offset
voltage (O.5mV, HA-2600) and low bias and offset current
(InA, HA-2600) to facilitate accurate signal processing. Input
offset can be reduced further by means of an external nulling
potentiometer. 12M Hz unity gain-bandwidth product, 7V / J.l s
slew rate and 150,OOOVIV open-loop gain enables HA-2600/
2602/2605 to perform high-gain amplification of fast, wide band
signals. These dynamic characterisitics, coupled with fast
settling times, make these amplifiers ideally suited to pulse
amplification designs as well as high frequency (e.g. video)
applications. The frequency response of the amplifier can be
tailored to exact design requirements by means of an external
bandwidth control capacitor.

• VIDEO AMPLIFIER
In addition to its application in pulse and video amplifier designs, HA-2600/2602/26il5 is particularly suited to other high
performance designs such as high-gain low distortion audio
amplifiers, high-Q and wideband active filters and high-speed
comparators.

• PULSE AMPLIFIER
• AUOIO AMPLIFIERS AND FILTERS
• HIGH-QACTIVE FILTERS
• HIGH-SPEED COMPARATORS

HA-2600 and HA-2602 are guaranteed over -55 0 C to +125 0 C.
HA-2605 is specified from OOC to +75 0 C. All devices are
available in TO-99 cans, and HA-2600/2602 are available in
10 lead flat packages.

• LOW OISTORTION OSCILLATORS

PINOUT

SCHEMATIC
COMPENSATION

Section 11 for Packaging
COMPENSATION

TOP VIEWS

Case Connected to VBALANCE
IN-

v+

IN+

OUT

v-

2-32

COMPENSATION

BALANCE

SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
Voltage Between V+ and V- Terminals
Differential Input Voltage
Peak Output Current
Internal Power Dissipation
Operating Temperature Range - HA-2600/HA-2602
HA-2605
Storage Temperature Range

45.0V
±12.0V
Full Short Circuit Protection
300mW
-55 0C ~TA~+1250C
OO~TA~+750C

-65 0C ~ TA ~ +150 oC

ELECTRICAL CHARACTERISTICS

PARAMETER

V+

= +15VDC, V- = -15VDC

HA-2600

HA-2602

HA-2605

-55°C to +125 0 C
LIMITS
MIN.
TYP.
MAX.

DoC to +75 0 C

TEMP.

-55°C to +125 0 C
LIMITS
TYP.
MAX.
MIN.

+25 0 C
Full

0.5
2

4
6

3

5
7

MIN.

LIMITS
TYP.

MAX.

UNITS

3

5
7

mV
mV

INPUT CHARACTERISTICS
Offset Voltage

5

Bias Current

1
10

10
30

15

25
60

5

25
40

nA
nA

Offset Current

+25 0 C
Full

1
5

10
30

5

25
60

5

25
40

nA
nA

Input Resistance (Note 101

+25 0 C

100

Full

±11.0

+25 0 C
Full

lOOK
70K

150K

SOK
60K

150K

SOK
70K

150K

Common Mode Rejection Ratio
(Note 21

Full

80

100

74

100

74

100

dB

Unity Gain Bandwidth (Note 31

+25 0 C

12

MHz

Common Mode Range

•

/lV/oC

Full
+25 0 C
Full

Offset Voltage Average Drift

500

40

300

40

MQ

300

V

±11.0

±11.0

TRANSFER CHARACTERISTICS
Large Signal Voltage Gain (Notes 1. 41

OUTPUT CHARACTERISTICS
Output Voltage Swing (Note 11

12

12

V/V
V/V

Full

±1O.0

±12.0

±10.0

±12.0

±1O.0

±12.0

V

Output Current (Note 41

+25 0 C

±15

±22

±10

±lS

±10

±lS

rnA

Full Power Bandwidth (Note4&11)

+25 0 C

50

75

50

75

50

75

kHz

TRANSIENT RESPONSE
Rise Time (Notes 1. 5,6 & 81

+25 0 C

30

60

25

40

Overshoot (Notes 1, 5.7 & 81

+25 0 C

Slew Rate (Notes I, 5, 8 & 12)

+25 0 C

Settling Time (Notes I, 5, 8 & 12)

+25 0 C

1.5

+25 0 C

3.0

POWER SUPPLY CHARACTERISTICS
Supply Current
PowerSupply Rejection Ratio (Note 91

Full

±4

±7

SO

90

±4

30

60

25

40

±4

±7
1.5

3.7

3.0
74

90

4.0

30

60

25

40

%

±7

V//ls

1.5

/-is

3.0
74

ns

90

4.0

mA
dB

TEST CONDITIONS
NOTES: I. RL ~ 2K
2. VCM~:':IOV

3. V o <90mV
4. Vo ~ :':IOV
5. C L ~ IOOpF
6. Vo~:':200mV

7. Vo~:':200mV
8. See Transient response test circuits
and waveforms
9.

.:lvs ~ ±5V

10, Th is parameter value guaranteed
by design calCUlations.

11. Full power bandwidth guaranteed
by slew rate measurement.
FPBW ~ S.R./2TTV pea k.
12. VOUT =

± 5V

2-33

PERFORMANCE CURVE

V+

= 15VDC, V- = 15VDC, TA = 25°C UNLESS OTHERWISE STATED.

15
0

-1

5

Vs

V

.,\~

V
50

25

0

+25

~AS(

10

~

--- -

OffSEt

5

-1 0

120

~

5
0

r::======:::-...--'r--~

lIX!

~

~

"

0

§


TEMPERATURE DC

1000

e

fA :.

~:r---t:::-:7i'7""'-l'<2'<2F&:-+--+

§

20

i:!!

o
T ~ 25°C

O.OlVI'~Ok"'H~Z---;;IOOk;;t:;;H;:-z--"IM;tH-;:Z--'I;;;;OM;';;H-;:Z--"IOO;:!MHZ

-ZOIOHZ

100Hz 1kHz
10kHz 100kHz IMHz IOMHz
fREQUENCY Hz
OPEN-LOOP FREQUENCY RES PONSE FOR VAR IOUS VALUES Of
CAPACITORS FROM COMPENSATION PIN TO GROUND

FREQUENCY Hz

INPUT IMPEDANCE VS, TEMPERATURE. 100Hz

OUTPUT VOLTAGE SWING VS. FREQUENCY

Note El(ternal Compensation Components 8fe not ReqUired
for Stablhtv, But Mav be Added to Reduce Bandwidth If DeSired
If EJilternal Compensation IS Used, Also Connect 100pF Capacitor
From Output to Ground.

20

I.

120

I,

-5SoC:S+ 12SoC
>
., 15

~

18::E 10

I

5

V

V

V

V

l20V LpPLJ

~
~

2100

I'- l"- t -

l"-

r-- l"- t--

~

l"- I -

~

•

~

e! lOV SUPPLY_

r--

~~~ l - t-'-

~

60

f-+-t-+tIlttt-t+r+ttffi--"'tt-fttHt-+-t-ttl-ttl

ti

40

f-+-t-ttlIlttt-t--Hr+ttffi-+++fttHPi--.I-ttI-ttl

;

8

BOSS

20

-35

COMMON MODE VOLTAGE RANGE
AS A FUNCTION OF SUPPLY VOLTAGE

L

85

lOS

20 f-+-t-ttlIlttt-t-tlctitffi-+++fttHt-+-t-ttl-ttl

125
COMMON MOOE AEJECTION RATIO
VSFAEOUENCY

INPU~5V
- 5V

,r------....,L

.:.J

SLEW RATE AND
TRANSIENT
RESPONSE

SUGGESTED

vas ADJUSTMENT
lOOkD

______ _
I
I

II

.V

--.hJ I
I SLEW

I +IOmVFROM
fiNAL VALUE

Ir,jT~=oR.1AJf.1 TII
1"

SETTLING TIME,
NOTE, MEASURED ON BOTH POSITIVE
AND NEGATIVE TRANS ITIONS.

25
45
65
TEMPERATURE DC

OPEN-LOOP VOLTAGE GAIN VS. TEMPERATURE

SLEW RATE AND
SETTLING TIME

TRANSIENT
RESPONSE

OVER~QflL

-IS _ 5

"f-+-t~Ilttt-"'t.qjr+ttffi-+++fttHt-+-t-ttl-ttl

ti

t--

./

10
15
SUPPLY VOLTAGE - VOlTS

2-34

~

'l5V SUPPLY

TYPICAl. APPlICA TIONS
PHOTO-CURRENT TO VOLTAGE CONVERTER

SAMPLE - AND - HOLD

S,F

R~40Kn

lNo---t-,---+'l.

5OpF'J

CIGITALCONTROL

~

DRIFT RATE

fEATURES

IFe- lQ()OpF
DRifT' 01 V msMAX

1 CONSTANT CEll VOLTAGE
2

MINIMUM BIAS CURRENT ERROR

REFERENCE VOLTAGE AMPLIFIER

).;:.--.....-0

VOLTAGE FOLLOWER

•

VO: 11 + Ml VREF

J50PFO

~'''''F'
1 000

GAIN

Z,n-_10'2
ZOUI ~ 01

0 9999

MIN
MAX

SLEW RATE "4VIIl.MIN
B W -12MH,TYP
OUTl'UTSWINO"!.IOVMIN T050kHI

FEATURES
1 MINIMUM BIAS CURRENT IN REFERENCE CELL

2 SHORT CIRCUIT PROTECTION'

*A small load capacitance is recommended in all applications where
practical to prevent possible high frequency oscillations resulting

from external wiring parasitics. Capacitance up to 100pF has
negligible effect on the bandwidth or slew rate.

2-35

HA-2620/2622/2625
Very Wide Band,
Uncompensated Operational Amplifiers

DESCRIPTION

FEATURES

•

• GAIN BANDWIDTH PRDDUCT(Av = 5)

100MHz

• HIGH INPUT IMPEDANCE

500Mn

• lOW INPUT BIAS CURRENT

lnA

• lOW INPUT OFFSET CURRENT

lnA

• lOW INPUT OFFSET VOLTAGE

O.5mV

• HIGH GAIN

150K V!V

• HIGH SLEW RATE

35V/Jls

• OUTPUT SHORT CIRCUIT PROTECTION

APPlICA TlONS
•
•
•
•
•
•

VIDEO AND R.F. AMPLIFIERS
PULSE AMPLIFIER
AUDIO AMPLIFIERS AND FILTERS
HIGH-QACTIVE FilTERS
HIGH-SPEED COMPARATORS
lOW DISTORTION OSCillATORS

In addition to its application in pulse and video amplifier designs HA-262012622/2625 is particularly suited to other high
performance designs such as high-gain low distortion audio
amplifiers, high-Q and wideband active filters and high-speed
comparators.

PINOUT
COMPENSATION

HA-2620/262212625 are bipolar operational amplifiers that
feature very high input impedance (500Mn, HA-2620l coupled
with wideband AC performance. The high resistance of the
input stage is complemented by low offset voltage (O.5mV,
HA-2620) and low bias and offset current (lnA, HA-2620) to
facilitate accurate signal processing. Input offset can be reduced
further by means of an external nulling potentiometer. 100MHz
gain-bandwidth product (HA-2620/2622/2625 are stable for
closed loop gains greater than 5), 35V/ Jl s slew rate and
150,OOOV/V open-loop gain enables HA-2620/262212625 to
perform high-gain amplification of very fast, wideband signals.
These dynamic characterisitcs, coupled with fast settling times,
make these amplifiers ideally suited to pulse amplification
designs as well as high frequency (e.. g. video) applications. The
frequency response of the amplifier can be tailored to exact
design requirements by means of an external bandwidth control
capacitor.

Section 11 for Packaging

HA-2620 and HA-2622 are guaranteed over -55 0 C to +125 0 C.
HA-2625 is specified from OOC to +75 0 C. All devices are
available in TO-99 cans, an.d 141ead D.i.P. packages.

SCHEMATIC
Case Connected to V-

v-

BALANCE

COMPENSATION

8

COMPENSATION

IN-

V+

IN+

OUT

v-

BALANCE

TOP VIEWS

NC I

14 COMPENSATION

NC 2

13 NC

BALANCE 3

12 NC

INVERTING INPUT 4-1----1'-

NONINVE~J~~* 5 -I----i'"

2-36

11 V+

10 OUTPUT

v- 6

9 BALANCE

NC 1

8

NC

SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
Voltage Between V+ and V- Terminals
Differentiall nput Voltage
Peak Output Current
Internal Power Dissipation
Storage Temperature Range

45.0V
±12.0V
Full Short Circuit Protection
300mW
-65 0 C'::;; TA'::;; +150 oC

ELECTRICAL CHARACTERISTICS
V+=+15VDC,
PARAMETER

V-=-15VDC
TEMPERATURE

HA-2620
HA·2622
HA·2625
-55 0 C to +125 0 C -55 0 C to +125 0 C OOC to +75 0 C
MIN. TYP. MAX MIN. TYP. MAX. MIN. TYP. MAX. UNITS

INPUT CHARACTERISTICS
Offset Voltage (Note I)

+25 0 C
Full

0.5

4
6

3

5
7

3

5
7

mV
mV

Bias Current

+25 0 C
Full

I
10

15
35

5

25
60

5

25
40

nA
nA

Offset Current

+25 0 C
Full

I
5

15
35

5

25
60

5

25
40

nA
nA

Input Resistance (Note.ll)

+25 0 C

65

Full

±11.0

Common Mode Range
TRANSFER CHARACTERISTICS
Large Signal Voltage Gain
(Notes 2 & 3)
Common Mode Rejection Ratio
(Note 4)
Gain Bandwidth Product
(Notes 2, 5, &6)
OUTPUT CHARACTERISTICS
Output Voltage Swing (Note 2)

+25 0 C
Full
Full
+25 0 C

100

+25 0 C

±15

Full Power Bandwidth
(Notes 2, 3, 7 &12)

+25 0 C

400 600

+25 0 C

17

Slew Rate (Notes 2, 7, 8 & 10)
POWER SUPPLY
CHARACTERISTICS
Supply Current
Power Supply Rejection Ratio
(Note 9)
NOTES:

'waveforms

cirCUits

and

74

±IO

90

±18

45

17

3.0
74

100

dB

100

MHz

V

±18

rnA

±IO

kHz

320 600

17

45

45

4.0

90

3.0
74

ns
V/jJs

±20 ±35

± 20 ±35

3.7

V/V
V/V

±IO.O +12.0

320 600

±35

3.0
80

1. Offset may be externally adjusted to zero.
2. RL=2K!1, CL=50pF
3. Va = :!:.10.0V
4. VCM = :!:.10V
5. Va <90mV
6. 40dB Gain

7. See transient response test

±.25

+25 0 C
Full

74

±IO.O ±12.0

.±22

V

80K 150K
70K

100

•

M!1

300

±11.0

100

±IO.O ±12.0

+25 0 C

40

80K 150K
60K

100

Output Current (Note 3)

TRANSIENT RESPONSE
Rise Time (Notes 2, 7 & 8)

300

±11.0

lOOK 150K
70K
80

Full

40

500

4.0

90

rnA
dB

8. AV = 5 (The HA-2620 family is not stable
at unity gain without external compensation.)

9. AVS up = ±SV
10. VOLIT = ± 5V
11. This parameter value based upon
design calculations.

12. Full power bandwidth guaranteed
based upon slew rate measurement

FPBW = S.R.!2TTV pea k.

2-37

TYPICAL PERFORMANCE CURVES

V+ = 15VDC, V· = 15VDC, TA = 25°C UNLESS OTHERWISE STATED.
15

120

100

10

!;glOO

~
~

OffSET

..........

5

/

,~S

-10

~
5
~

---

-I5 -50

10

;;

O·

+25

+50

+75

.1

+100+125

100Hz

10kHz
100kHz
IMHz
UPPER JdB fREQUENCY
LOWER )dB FREQUENCY - 10Hz
BROADBAND NOISE CHARACTERISTICS

INPUT BIAS CURRENT ANO OffSET CURRENT_
AS A FUNCTI ON Of TEMPERATURE

•

-.......

800

!g

6600

"

~+,

~

\i1

'"

~

'"

~

400

·35

15

+5

+25

+45

§

20

0'

~

r---.

PHASE

20D

1"'-

~

0

-10

HlHz

100Hz

1kHz

1Ok.Hz 100kHz IMHz

1
I

~I

l

IOMHz lOOMHz

OPEN LOOP FREQUENCY AND PHASE RESPONSE

IV r----j~ .---t--""'~t-----t

~

g a.lv t----j----t-----t--->.,""~

'"

200

 60

§

V

~

z
~ BO

+65

+85

100Hz

~

.........

+105 +125

fREQUENCY Hz

INPUT IMPEDANCE VS. TEMPERATURE. 100Hz

10kHz

100kHz

IMHz

IOMHz

FREQUENCY Hz
OPEN-LOOP FREQUENCY RESPONSE FOR VARIOUS VALUES Of
CAPACITORS FROM COMPENSATION~ PIN TO GROUNO

O.OlV1!::0'-::HZ---;:100::!'-::H"-Z- - .-;;IM~H;::z---;IO/Il=H;::Z--'I:=OOMHZ

TEMPERATURE DC

1kHz

Note External CompenS811on IS ReqUired For
Closed loop Gam < 5. If External Compensation IS Used, Also Connect 100 pF CapacItor

OUTPUT VOLTAGE SWING VS. fREQUENCY

From Output to Ground.

20

120

.5~Oc Sf 12!OC

S

0

5

./

V

V

V

V

l20V LPPLJ

/

10
15
SUPPLY VOLTAGE - VOLTS

r- t .! 15V SUPPLY
l- I - t-- t=:"gOV SUPPly
0
r- t-t-- t t-~~~
l-t20

15

COMMON MODE VOLTAGE RANGE
AS A FUNCTION Of SUPPLY VOLTAGE

25
45
65
TEMPERATURE DC

85

105

115

OPEN-LOOP VOLTAGE GAIN VS- TEMPERATURE

TRANSIENT RESPONSE

SLEW RATE ANO
TRANSIENT RESPONSE

SLEW RATE

SUGGESTED VOS ADJUSTMENT
AND COMPENSATION HOOK-UP

y

~
INPUT

OV

'INPUT IV

:~~T===1-

r---l

~v-=::..J

L
100KD

10%Ji
.
: l__
,

!

NOTE

__:>----0 OUT

R,sET,ME

MEASURED ON BOTH POSITIVE
AND NEGATIVE TRANSISTIONS

-v

2-38

TYPICAL APPLICA TlONS

HIGH IMPEDANCE COMPARATOR
'1~

ov

>-----:r-----<,---Q

VOUl

15 OV, Ov

FUNCTION GENERATOR

•

VIDEO AMPLIFIER

5"

22K.Q

VOUT

'1.,5DPF'

VIN

'A Imallload capacllance 01 al
BW· I MHl
GAIN ·4OdB

!~ast

30pf

!Hlcludmg~lraVtapacltancellsrecommended

to prevent possible high lreQuentv oscLl1al,ons

2-39

HA-2630/2635
High Performance Current Booster

DESCRIPTION

FEATURES

•

•

OUTPUT CURRENT

±400mA

•

SLEW RATE

500V//ls

•
•

BANOWIOTH

8MHz

FULL POWER BANOWIOTH

8MHz

•
•
•

POWER SUPPLY RANGE

•

PACKAGE IS ELECTRICALLY ISOLATED

2.0 x 10 6 .11

INPUT RESISTANCE
OUTPUT RESISTANCE

2.0.11
±5V to ±20V

APPlICA TIONS
•

COAXIAL CABLE DRIVERS

•

AUDIO OUTPUT AMPLIFIERS

•

SERVO MOTOR DRIVERS

•

POWER SUPPLIES (BIPOLAR)

•

PRECISION DATA RECORDING

HA-2630 and HA-2635 are monolithic, unity voltage gain
current amplifiers delivering extremely high slew rate, wide
bandwidth, and full power bandwidth even under heavy output
loading conditions. This dielectrically isolated current booster
also offers high input imp'edance and low output resistance.
These devices are intended to be used in series with an operational amplifier and inside the feedback loop whenever additional output current is required. Output current levels are
programmable by selecting two optional external resistors.
These current amplifiers offer an exceptional 500V I /l s slew
rate and 8MHz bandwidth which allows them to be used with
many high performance op amps in precision data recording
and high speed coaxial cable driver designs. 2.0M ohm input
resistance and 2 ohm output resistance coupled with ±400mA
output current make HA-2630 and HA-2635 ideal components
in high fidelity audio output amplifier designs.
HA-2630 and HA-2635 are available in an electrically isolated
TO-8 type can for ease of mounting with or without a heat
sink. HA-2630 is specified over the -55 0 C to +125 0 C range.
HA-2635 is specified from OOC to +75 0 C.

PINOUT

SCHEMATIC
Section 11 for Packaging
"

TOP VIEW

vOUT
INPUT

v+

* Optional Current
Limiting Resistor

2-40

SPECIFICA TIONS
ABSOLUTE MAXIMUM RATINGS
Voltage Between V+ and V- Terminals
Input Voltage Range
Output Current (Note 2)
Internal Power Dissipation (Note 6) Free Air:
In Heat Sink:

Operating Temperature Range:
-55°C ~ TA ~ +125°C
OOC S: TA~ +75 0 C
Storage Temperature Range:
-65°C ~ TA ~ +150 0 C

40V
± V Supply
±700mA
lW
4W

(HA-2630)
(HA-2635)

ELECTRICAL CHARACTERISTICS
VSupply = ±15 Volts

R1 = R2

RL = 50 Ohms

PARAMETER
INPUT CHARACTERISTICS
Bias Current

TEMP.

=0 Ohms

Unless otherwise specified.

HA-2630
-55°C to +125 0 C
MIN.
TYP.
MAX.

HA-2635
OOC to +75?C
TYP.
MAX.
MIN.

30

Input Resistance

+25 0 C

2.0

2.0

Mil

Input Capacitance

+25 0 C

5.0

5.0

pF

.95

V!V

Full

.85

.85

.95

Offset Voltage (VOUT - VIN)

+25 0 C
Full

70

Bandwidth (-3d B)

+25 0 C

8.0

30

70

±200
±300

150
200

±200
±300

mV
mV

8.0

MHz

OUTPUT CHARACTERISTICS
Output Voltage Swing

Full

±10

±12

±10

±12

V

Output Current (Note 1)

Full

±300

±400

±300

±400

rnA

Output Resistance

+25 0 C

2.0

2.0

il

Full Power Bandwidth (Note 1)

+25 0 C

8.0

8.0

MHz

TRANSIENT RESPONSE
Rise Time (Note 3)

+25 0 C

30

30

ns

Slew Rate (Note 4)

+25 0 C

500

V/].1s

POWER SUPPLY CHARACTERISTICS
Supply Current

Full

Supply Voltage Range

Full

Power Supply Rejection Ratio (Note 5)

Full

NOTES:

200

15
±5

1. Vo ~ ±10V
2. Heat sink is required for continuous short circuit

protection, regardless of current limit setting.
3. Vo
4. Vo

~
~

0.4V p-p.
10V p-p.

500

200

20
±20

66

15
.±5
66

•

j..lA
].1 A

+25 0 C
Full

TRANSFER CHARACTERISTICS
Voltage Gain (Note 1)

150
200

UNITS

23

rnA

±20

V
dB

5. lIVSUPPLY ~ ±5V.
6. Without heat sink, derate by 14mW/oC ambient
temperature above 1 oooe ambient, with heat

sink, derate by 67mW/oC case temperature above
115°C case.

2-41

PERFORMANCE CURVES
V+ =15VDC, V- =15VDC, TA =250C UNLESS OTHERWISE STATED
OPEN LOOP FREQUENCY AND
PHASE RESPONSE (RL = Son. CL "'lOp!)

OUTPUT SWING
(R LlMIT =on)

,
"
,

- ....

~~

0

A ~

~
~"5DQ
/.:
RL~JDO~

0

PHASE
1

0

, A~
~

1

.,

0

,.

·30

0
15
Sl,lpplyVoltageltVoltsl

lOOK

20

NORMALIZED AC PARAMETERS v•.
TEMPERATURE (RL = SOn)

10.

..
•

....V

'3d~ANOLIOTH

0

~

/""
~EWRATE

•

-JdbBANOWIO~

..
I
-50

-25

+25

+SO

+15

+100

315
100M

Frequ.ncY,Hz

~, .1

",,-

10

I

.1

.0

,
,

NORMALIZED AC PARAMETERS v•.
SUPPLY VOLTAGE (RL = SOn)

,

,

•

I'....
1""1

0

10

•
•

I'....

.- ..r~

p-

/SlEWRATE

I

7

+125

12:

10

TemiJer8111f1!.IOCI

14

16

18

20

SUPlilyVoltage,(Voltsl

OUTPUT CURRENT LIMITING vs.
LIMITING RESISTANCE

moo

OUTPUT CURRENT CHARACTERISTIC

1000

RI-Zoll
75

+llIMITIRII

t'--

-150

-I LIMIT 1RZ'

·SO

-100

I
so

I I "-IOn

j

...

250

R2"20Q
-100

____

MAXIMUM ALLOWABLE INTERNAL
POWER DISSIPATION vs. TEMPERATURE

- - r--

r-- r-

10

12

14

16

r-

18

~

3

,
1

LlffilllngR'$lstance.IQI

CASE LMPERA,]R'
.......

•

1

2-42

20'

5

1-

,

15'

Output Lllad Current, (mAl

POWER DISSIPATION vs. LIMITING RESISTANCE
WITH OUTPUT SHORTED TO GROUND; VIN = +IOV

•
3

100

·75

lmlltlll9 Rnistlnce. Inl

,

II
I/Rl"2SI1

·SO

VH2"S0Q

10'

I

"am

/

R2"25/1

0

"

/

II

I

I/R1=50n

so

-250 -zOO

10

"'lObl I

20

0
90

~ .....
........

iMB:~~~~~~~~:~[URi

100

')0

n

120
TtmperllluraoC

130

140

TYPICAL APPLICATION
20dB, 5MHz VIDEO COAXIAL LINE DRIVER
HA-2530

HA-2630

50n COAX

NOTE: R1 and R2 lead length should be minimal.

"""L.S

•

"

LINE DRIVER PULSE RESPONSE

\

1-

J

Horizontal Scale = 200ns/Div.
Upper Trace:

Input,200mV/Div.

Lower Trace:

Output,2V/Div.

SOME OTHER APPLICATIONS
• BIPOLAR POWER SUPPLY
•

FUNCTION GENERATOR OUTPUT

• DEFLECTION COIL DRIVE
• AUDIO OUTPUT AMPLIFIER

2-43

HA-2640/2645
High Voltage
Operational Amplifier

FEATURES
•

DESCRIPTION
±35V

OUTPUT VOLTAGE SWING

±10V TO±40V

• SUPPLY VOLTAGE
•

•

5nA

OFFSET CURRENT

•

BANOWIDTH

4MHz

•

SLEW RATE

5V/IlS

•

COMMON MODE INPUTVOLTAGESWING

±35V

•

OUTPUT OVERLOAD PROTECTION

INDUSTRIAL CONTROL SYSTEMS

•

POWER SUPPLIES

•

HIGH VOLTAGE REGULATORS

•

RESOLVER EXCITATION

•

SIGNAL CONDITIONING

For maximum reliability, these amplifiers offer unconditional
output overload protection through current limiting and a chip
temperature sensing circuit. This sensing device turns the
amplifier "off", when the chip reaches a certain temperature
level.
These amplifers deliver ±35V common mode input voltage
swing, ±35V output voltage swing, and up to ±40V supply range
for use in such designs as regulators, power supplies, and industrial control systems. 4MHz gain bandwidth and 5V/Ils slew
rate make these devices excellent components for high performance signal conditioning applications. Outstanding input and
output voltage swings coupled with a low 5nA offset current
make these amplifiers excellent components for resolver excitation designs.

APPlICA TIONS
•

HA-2640 and HA-2645 are monolithic operational amplifiers
which are designed to deliver unprecedented dynamic specifications for a high voltage internally compensated device. These
dielectrically isolated devices offer very low values for offset
voltage and offset current coupled with large output voltage
swing and common mode input voltage .

HA-2640 and HA-2645 are available in metal can (TO-99)
packages and can be used as high performance pin-to-pin
replacements for many general purpose op amps. HA-2640 is
specified from -55 0 C to +125 0 C and HA-2645 is specified over
the OOC to +75 0 C range.

PINOUT

SCHEMATIC
COMPENSATION

Section 11 for Packaging
COMPENSATION

v-

TOP VIEWS
BALANCE

2-44

COMPENSATION

IN-

v+

IN+

OUT

v-

BALANCE

SPECIFICA TIONS
ABSOLUTE MAXIMUM RATINGS
Operating Temperature Range
-55°C::;' TA ::;. + 125°C (HA-2640)
OOC ::;. TA::;' +75°C (HA-2645)
Storage Temperature Range
-65°C::;' TA::;' +150 0 C

Voltage Between V+ and V- Terminals
100V
Input Voltage Range
±37V
Output Current/Full Short Circuit Protection
Internal Power Dissipation
680mW'
'Derate by 4.6mW/oC above +25 0 C

ELECTRICAL CHARACTERISTICS
VSuppl y = ±40V,

RL

= 5K,

Unless Otherwise Specified.

PARAMETER
INPUT CHARACTERISTICS

HA·2640
·55 0 C to +125 0 C
TYP.
MAX.
MIN.

TEMP.

HA·2645
OOC to +75 0 C
MIN.
TYP.
MAX.

4
6

2

6
7

UNITS
mV
mV

+25 0 C
Full

2

Full

15

+25 0 C
Full

10

25
50

12

30
50

nA
nA

Offset Current

+25 0 C
Full

5

12
35

15

30
50

nA
nA

Input Resistance (Note 10)

+25 OC

50

Full

±35

+25 0 C
Full

lOOK
75K

200K

lOOK
75K

200K

V/V
V/V

Full

80

100

74

100

dB

4

MHz

Offset Voltage
Offset Voltage Average Drift

II

]..I V1°C

15

I

Bias Current

Common Mode Range

250

200

40

M.\2
V

±35

TRANSFER CHARACTERISTICS
Large Signal Voltage Gain (Note 8)
Common Mode Rejection Ratio (Note 1)
Unity Gain Bandwidth (Note 2)

+25 0 C

OUTPUT CHARACTERISTICS
Output Voltage Swing

Full

±35

Output Current (Note 9)

+25 0 C

±12

Output Resistance

+25 0 C

500

500

.\2

Full Power Bandwidth (Notes 3 &11)

+25 0 C

23

23

kHz

+25 0 C

60

100

60

100

ns

15

30

15

40

%

TRANSIENT RESPONSE
Rise Time (Notes 4, 6)

4

Overshoot (Notes 4,6)

+25 0 C
+25 0 C

POWER SUPPLY CHARACTERISTICS
Supply Current

+25 0 C

±3

Full

±10

Power Supply Rejection Ratio (Note 5)

Full

80

3. Vo = .:!:.35V

4. Va"" ±200mV

±10

rnA

±12

90

Va = ±30V
RL = 1 K

.±5
3.2

3.8
±40

5. Vs = .,!., OV to .±.40V
6. AV = 1
7. C L = 50pF

8.
9.

±2.5

±5
3.2

Supply Voltage Range

1. VCM =±20V
2. Va = 90mV

±15

(Note 7)

Slew Rate (Note 6)

NOTES:

V

±35

±10
74

V/]..Is
4.5

rnA

±40

V

90

dB

10. This parameter based upon
design calculations.
11. Full power bandwidth
guaranteed based upon

slew rate measurement.
FPBW = S.R./21TV pea k.

2-45

PERFORMANCE CURVES
v+ = V- = 40VDC, TA = +25 0 C UNLESS OTHERWISE STATED
INPUT NOISE CHARACTERISTICS

INPUT BIAS AND OFFSET CURRENT
vs TEMPERATURE

I0- 14

'00 _
9

15

.........

8

-

15

U'"

I

6

1\





--r-....

°c

C-

o

,

. . . . 1,
H

:;;

80°

115°

-. 0
'00

lK

10K

lOOK

M

10M

2700

Frequency Hz
OPEN LOOP FREQUENCY RESPONSE FOR
VARIOUS VALUES OF CAPACITORS FROM
COMPENSATION PIN TO GROUND

NORMALIZED AC PARAMETERS
vsSUPPLY VOLTAGE AT+250C
o

PHASE

G-;:;;;'"

'0

>

4

~~

.;;

8

~o

~

c-

o SLEW RATE " " " t--...,

~

120

0

I. 1

M

+1
o

. ; 1.

,

~

~

..'"

a:

~w~

n;

.

>

~

9

.!::!

n;

E
o
;;::

SLEWAAT~

,

8

/V'

·10

L

"/
-40f----f---+---+---+---t---"'~

10

30

40

Supply Voltage, Volts

,!::-O---!,"'OO,---+.'K;----;,;!;OK;----;;'O~OK;---7.'•.----;"OM

Frequency Hz
NOTE:

External Compensation Components are not Required for

Stability. But May be Added to Reduce Bandwidth if Desided.
C L = 100pF is Also Required for Stability Only if External
Compensation Capacitor is Used.

2-46

PERFORMANCE CURVES (continued)

OUTPUT VOLTAGE SWING
vs FREQUENCY AT +25 0 C

OUTPUT CURRENT CHARACTERISTIC
40

100
AV

r-- VSUPPL Y = :!,40V
- V SUPPlV":l"20V

;:

~

VSUPPLY = tlDV
100

'"
~

.,'".

"0

g
>

e0"

~

10

;----.,,0,

':::;

""" ~

0..
0

10

-550~:~
-20

I

\.,,,\

VI

-15

l

VIN = +15V

j,
-10

~
0..

10

'I 1/

5 /10
"tSOC
1+250C
-10
AV

=

lOOK

10K

'M

I

.!10
-SSoC

I, VSUPPl Y = t20V

VIN = -15V

-10

-30
AV

!'

1. VSUPPL Y = t40V

=

VIN
-40

01
,K

I
I

I II l15I /

-5

.I l \
I
-55°C I .250,/T 5O ,
l I

'I

)

!"O'I -55°'/

I I
I I I

AV= 1,VSUPPLY = t20V

,,;

~

~

I
.1125 0 ,

>

"0

0

>

1, VSUPPL V ~ !40V
VIN =+35V
30

~

""~~

'"
,S

~

= -35V

II

Output Load Current, rnA

Frequency, Hz

SWITCHING WA VEFORM AND TEST CIRCUIT
VOLTAGE FOLLOWER
PULSE RESPONSE

SLEW RATE AND TRANSIENT
RESPONSE TEST CI RCUIT

IN~

~

r-V

,

I
If

....1"

50pF

~~

-,-

~

RL = 5K, CL = 50pF
Vertical = 10V/Div,
Horizontal = 5j.ls/Oiv.

SUGGESTED

~.

<;.

\

J

~.l ~DUT

< 5KQ

vas

ADJUSTMENT

T A =+25 0 C
Vs =:!-40V

e
1

7

''':~,,~ i·
-L-

-v

2-47

mI HARRIS

HA-2650/2655

Dual High Performance
Operational Amplifier

FEATURES

DESCRIPTION

• SLEW RATE

5V Ip.s

• BANDWIDTH

8MHz
35nA

• BIAS CURRENT

•

HA-2650/2655 contains two internally compensated operational amplifiers offering high slew rate and high frequency
performance combined with exceptional DC characteristics.
5V/p. sec slew rate and 8MHz bandwidth make th,ese amplifiers
suitable for processing fast, wide band signals extending into the
video frequency spectrum. Signal processing accuracy is enhanced by front-end performance that includes 1.5mV offset
voltage, 8 p. V10C offset voltage drift and low offset and bias
current !lnA and 35nA respectively). Offset voltage can be
trimmed to zero on the devices offered in dual-in-line packages.
Signal conditioning is further enhanced by 500Mfl input impedance.

8p.V 10C

• AV.DFFSETVOLTAGEDRIFT

75mW

• POWER CONSUMPTION

±2V TO ±20V

• SUPPLY VOLTAGE RANGE

APPLICA TIONS

Applications for HA-2650/2655 include video circuit designs
such as high impedance buffers, integrators, tone generators
and filters. These amplifiers are also ideal components for
active filtering of audio and voice signals.

• VIDEO AMPLIFIERS

HA-2650/2655 are offered in 14 pin D.i.P. and metal TO-99
packages and are also available in dice form. HA-2650 is specified from -55 0 C to +125 0 C. HA-2655 operates from OOC
to +75 0 C.

• HIGH IMPEDANCE, WIDEBAND BUFFERS
• INTEGRATORS
• AUDIO AMPLIFIERS
• ACTIVE FILTERS

SCHEMATIC

PINOUT
TOP VIEW

Section 11 for Packaging

v.

rIIAS.iTWORI(

I
I
I
I
I

1·'1

;Ii::

NOTE: Case Connected to v-

I
I

I
I
I

v-

I
I

TOP VIEW

:~~
BAlANCE {

3

4
5

IN {

v-

12

-

11}

+

•

_

6
7

NOTE: Bottom of packa!lllls connected to V-

2-48

10

I

:;c

OUT

I
I
I

I
I

I

I
BALANCE

9 }
IN
8

I
I

- I_ _ _ _ _ ONE·HAlfHA_15WHA_H55

--!

_______

SPECIFICA TIONS
ABSOLUTE MAXIMUM RATINGS
Power Dissipation (Note 2)

TA = +25 0 C Unless Otherwise Stated
Voltage Between V+ and V- Terminals
Differentiall nput Voltage
Input Voltage (Note 1)
Output Short Circuit Duration

40.0V
±30.0V
Indefinite

HA-2655
DoC to +75 0 C

HA-2650
-55 0 C to +125 0 C

V+=15V V-=-15V
PARAMETER

TEMP.

300 mW

Operating Temperature Range:
HA-2650
-55°C ::;TA ::; +125 0 C
HA-2655
O~C ::; TA ::; +75 0 C
Storage Temperature Range -65 0 C::; TA ::; +150 0 C

:l:15.0V

ELECTRICAL CHARACTERISTICS

INPUT CHARACTERISTICS
Offset Voltage

300 mW

TO-99
TO-1I6

MIN.

TYP.
1.5

+25 0 C
Full

MAX.

MIN.

TYP.

MAX.

3
5

2

5
7

mV
mV

8

UNITS

Av. Offset Voltage Drift

Full

Bias Cu rrent

+25 0 C
Full

35

100
200

50

200
300

nA
nA

Offset Current

+25 0 C
Full

1

30
60

2

60
100

nA
nA

Common Mode Range

Full

Differential Input Resistance (Note 9)

+25 0 C

Common Mode Input Resistance

+25 0 C

Input Capacitance

+25 0 C

TRANSFER CHARACTERISTICS
Large Signal Voltage Gain (Note 3ab)
Common Mode Rejection Ratio (Note 4)
OUTPUT CHARACTERISTICS
*Output Voltage Swing (Note 3c)

8

:1:13
5

/-LV 1°C

:1:13
5

20
500
5

V
20

Mn

500
5

Mn
pF

+25 0 C
Full

20K
15K

+25 0 C
Full

80
80

100

74
74

100

dB
dB

+25 0 C
Full

:1:13
:1:13

±14

:1:13
:1:13

:1:14

V
V

30

80

30

80
:1:18

KHz
rnA

100

n

Full Power Bandwidth (Notes 5 &10)

+25 0 C

Output Current (Note 3a)

+25 0 C

Output Resistance

+25 0 C

TRANSIENT RESPONSE (Note 6)
Rise Time (Note 7)

+25 0 C

Overshoot (Note 7)

+25 0 C

Slew Rate

+25 0 C

POWER SUPPLY CHARACTERISTICS
Supply Current

+25 0 C

40K

15K
10K

:1:20
100
40
15
:1:2

:1:5

80
80

100

2.5

40

90

ns

30

15

40

%

NOTES: 1. For supply voltages less than :l:15V,
the absolute maximum input voltage
is equal to the supply voltage,
2. Derate at 4.7mW/oC at ambient temperatures above +11Oo C.
3. (a) Va = ±10V (b) RL = 2K
Ie) RL = 10K

4. VCM = :l:5.0V
5. AV = 1, RL = 2K, Va = 20Vpp
6. See transient response/slew rate
circuit.

:1:2

:1:5

74
74

100

4

+25 0 C
Full

7. Vin = 200mV
8. Il. V =:l:5.0V

V/V
V/V

40K

80

Power Supply Rejection Ratio (Note 8)

II

3

VIps

5

rnA
dB
dB

9.

This parameter value based upon
design calculations.
10. Full power bandwidth guaranteed
based upon slew rate measurement
FPBW = S.R.l211'V pea k.

2-49

PERFORMANCE CURVES
V+ = +15V, V-

=

-15V, TA

+25 0 C unless otherwise stated.

=

OUTPUT VOLTAGE SWING VS. FREQUENCY
OPEN LOOP FREQUENCY RESPONSE
100

;;;

I

~

w 60

"'.
«
~

40

00

,

1
PHASE

20

0

100

lk

Vo

2:

90"

'"3iz

r---

llLll

10k
lOOk
1M
FREQUENCY IHzI

10M

.-::

o

CL~50~F

-

•

I

lk

!A V
Y-LBAN~WIOTH

9

±5

~1.1

o
w
=>

ft-

.±10

±15

~
"

r--

~

«
~

±20

'" 40

~
~

z

I I
I I

~

3.0

+125

POWER SUPPLY CURRENT VS. TEMPERATURE

1'

E
v

I

~

2o onSOURCE RESISTANCE

~1 o

I

I

10

I

I

I I

'!O 0
100

.1k
FREQUENCY IHd

10k

1.0

lOOk

-55

-25

COMMON MOOE REJECTION RATIO
VS. FREQUENCY
12 0

!g 10 0

,

o

~

'"

z

0

""""

o

§
~

r-.....

0

.....

'"ow

o

'" 40
~

'"'"
13

.....

20
0
100Hz

2-50

+75

'" 2.5t

10kllSOURCE RESISTANCE

"- N

~ 30

~

o
+25
+50
TEMPERATURE lOCI

-25

o

INPUT NOISE VOLTAGE VS. FREQUENCY

O~
~6
>

O~
-75
w

.9

W

N

SUPPLY VOLTAGE

_7 0

1M

~ 1.0 ,-r--r-+--..l

I

7

lOOk

NORMALl2EO AC PARAMETERS VS. TEMPERATURE

~ 1.2

I

I

.L

I

fo-

1/

8

111111,

10k
FREQUENCY IHd

o

V V

SLEW RATE

IIIIII11

o

V

!

'-1

11111I

100
u

I

(VOLTAGE FOLLOWERI
RL ~ 2k

~o. 1 -

NORMALl2EO AC PARAMETERS VS. SUPPLY VOLTAGE
1. 1

VV±15V
:\vs ~ ±IOV
Vs - t5V
Vs ~ +2V

I

r-

>

100M

N

lL 1

fo-

III

I

":

2V

Vo

~

I

1\

8V

II

~1. 0

.0 I

0

~

o

111111

10

Vo - 18V

0

o

I 80 0

1111111

'" -20

~1

45 0

135 0

111111
111111

z

~

I

f'

>

~

"

t~,

1

;; 80

~~O ~i2d~1

or---

IIIIII

I-

1kHz

10kHl
FREQUENCY - Hz

100kHz

lMHz

+25
+50
TEMPERATURE lOCI

+75

+125

PERFORMANCE CHARACTERISTICS
TRANSIENT RESPONSE/SLEW RATE CIRCUIT

SLEWING WAVEFORM

OV

>----.......-~,......o Vo UT

--V

VOUT

Note: Numbers in parentheses refer to the second half of
TO-116 package.

7

VERTICAL 5V!D1V.

"'"

OV

HORIZONTAL lJ..1s!OIV.

TYPICAL APPLICATIONS

lEI

LOW COST HIGH FREQUENCY GENERATOR
r -____

~R~~~-----------------------------EO~ ~
1
f=4R C

I~-'1

(Eo)pp =

2VZ~~)

3 3\R2

"!VZ

ABSO LUTE-VALUE CI RCUIT
R

R

R

R

12

>-<~--O

8

Eo = lEil

10

R
HIGH IMPEOANCE
HIGH GAIN
HIGH FREQUENCY INVERTING AMP

lOOK

BW = 100KHz
AV = 100
Zin = 2 x 109 n
>--<~-o

-15V

Eo

+15V

2-51

HA-2720/25

mHARRIS

Wide Range Programmable
Operational Amplifier
FEATURES

•

DESCRIPTION

• WIDE PROGRAMMING RANGE
SLEW RATE
BANDWIDTH
BIAS CURRENT
SUPPLY CURRENT

0.06 TO 6V/p.s
5kHz TO 10MHz
0.4 TO 50nA
lp.A TO 1.5mA

• WIDE POWER SUPPLY RANGE

±1.2 TO ±18V

• CONSTANT AC PERFORMANCE OVER SUPPLY
RANGE

APPlICA TIONS
• ACTIVE FI LTERS
• CURRENT CONTROLLED OSCILLATORS
• VARIABLE ACTIVE FILTERS
• MODULATORS
• BATTERY-POWERED EQUIPMENT

HA-2720/2725 programmable amplifiers are internally compensated monolithic devices offering a wide range of performance,
that can be controlled by adjusting the circuits' "set" current
(lSET). By means of adjusting an external resistor or current
source, power dissipation, slew rate, bandwidth, output current
and input noise can be programmed to desired levels. This
versatile adjustment capability enables HA-2720/2725 to provide optimum design solutions by delivering the required level
of performance with minimum possible power dissipation.
HA-2720 and HA-2725 can, therefore, be utilized as the standard amplifier for a variety of designs simply by adjusting their
programming current.
A major advantage of HA-2720/2725 is that operating characteristics remain virtually constant over a wide supply range
(±1.2V to ±15V), allowing the amplifiers to offer maximum
performance in almost any system including battery-operated
equipment. A primary application for HA-2720/2725 is in
active filters for a wide variety of signals that differ in frequency
and amplitude. Also, by modulating the "set" current, HA272012725 can be used for designs such as current controlled
oscillators modulators, sample and hold circuits and variable
active filters.
HA- 2720 is guaranteed over -55 0 C to +125 0 C. HA-2725 is
specified from OOC to +75 0 C. Both parts are available in TO-99
cans or dice form.

PINOUT

SCHEMATIC
Section 11 for Packaging

TOP VIEWS

NOTE: Case tied to VOUT

BALANCE

INVERTING INPUT
NON-INVERTING
INPUT
v-

2-52

ISET
V+

OUTPUT
BALANCE

SPECIFICA TIONS
ABSOLUTE MAXIMUM RATINGS
Voltage Between V+ and V- Terminals
Differential Input Voltage
Input Voltage (Note 1)
ISET (Current at ISET)
VSET (Voltage to Gnd. at ISET)

45.0V
±30.0V
±15.0V
500/iA
V+ - 2.0V :S VSET :S V+

Power Dissipation (Note 2)
300mW
Operating Temperature Range:
HA-2720
-550C:S TA :S +125 0C
HA-2725
OOC :S TA :S +75 0 C
Storage Temp erature Range
-65°C ~ TA ~ +150 0 C

ELECTRICAL CHARACTERISTICS
V+ = +3.0V, V- = -3.0V

HA-2725
OOC to +75 0C

HA-2720
-55°C to +125 0C
PARAMETER
INPUT CHARACTERISTICS
Offset Voltage

TEMP.

ISET = 1.5/iA
ISET = 15/iA
ISET = 1.5/iA
ISET = 15/iA
MIN. TYP. MAX. MIN. TYP. MAX. MIN. TYP. MAX. MIN. TYP. MAX. UNITS

25°C
Full

2.0

3.0
5.0

2.0

3.0
5.0

2.0

5.0
7.0

2.0

5.0
7.0

mV
mV

Offset Current

25°C
Full

0.5

3.0
7.5

1.0

10
20

0.5

5.0
7.5

1.0

10
20

nA
nA

Bias Current

25°C
Full

2.0

5.0
10

8.0

20
40

2.0

10
10

8.0

30
40

nA
nA

Input Resistance (Note 10)

25°C

50

5

50

5

MQ

Input Capacitance

25°C

3.0

3.0

3.0

3.0

pF

25°C
Full

15K 40K
10K

15K 40K
10K

15K 40K
10K

15K 40K
10K

TRANSFER CHARACTERISTICS
Large Signal Voltage Gain (Note 91
Common Mode Rejection Ratio (Note 4)
OUTPUT CHARACTERISTICS
Output Voltage Swing (Note 3)

Full

BO

74

74

BO

V/V
V/V
dB

25°C
Full

±2.0 ±2.2
±2.0

±2.0 ±2.2
±1.9

±2.0 ±2.2
±2.0

±2.0 ±2.2
±2.0

V
V

Output Current (Note 5)

25°C

±0.2

.±2.0

±0.2

±2.0

mA

Output Resistance

25°C

2K

500

2K

500

Output Short-Circuit Current

25°C

2.B

14

2.B

14

rnA

TRANSIENT RESPONSE
Rise Time (Note 6)

25°C

2.5

0.25

2.5

0.25

/is

Overshoot (Note 6)

25°C

5

10

5

10

Slew Rate (Note 7)

25°C

0.07

0.70

0.07

0.70

25°C
Full

15

POWE R SUPPLY CHARACTERISTICS
Supply Current
Power Supply Rejection Ratio (Note 8)

Full

170

100

100

25
150

%

V/J.Ls

170

15
250

25

Q

250
150

J.LA
J.LA
/iV/V

2-53

II

SPECIFICA TlONS
ELECTRICAL CHARACTERISTICS
V+=+15.0V,

V-=-15.0V
HA-2720
-550C to +125 0C

PARAMETER

TEMP.

INPUT CHARACTERISTICS
Offset Voltage

•

ISET = 1.5/1A
MIN. TYP. MAX.

ISET = 1.5/1A
ISET - 15/1A
ISET - 15/1A
TYP. MAX. MIN. TYP. MAX. MIN. TYP. MAX. UNITS

MI~.

,

25°C
Full

2.0

3.0
5.0

2.0

3.0
5.0

2.0

5.0
7.0

2.0

5.0
7.0

mV
mV

Offset Current

25°C
Full

0.5

3.0
7.5

1.0

10
20

0.5

5.0
7.5

1.0

10
20

nA
nA

Bias Current

25°C
Full

2.0

5.0
10

8.0

20
40

2.0

10
10

8.0

30
40

nA
nA

Input Resistance (Note 10)

25°C

50

5

50

5

MQ

Input Capacitance

25°C

3.0

3.0

3.0

3.0

pF

25°C
Full

30K lOOK
20K

25K lOOK
20K

25K 120K
20K

TRANSFER CHARACTERISTICS
Large Signal Voltage Gain (Notes 3 & 9)

Common Mode Rejection Ratio (Note 4) 25°C
Full

30K 120K
20K
90

90

90

V/V

VIV
dB
dB

90
74

80

80

25°C
Full

±12 ±13.5
±10

±12 ±13.5
±10

±12 ±13.5
±10

±12 ±13.5
±10

V

Output Current (Note 5)

25°C

±0.5

±5.0

±0.5

±5.0

rnA

Output Resistance

25°C

2K

500

2K

500

Output Short-Circuit Current

25°C

3.7

19

3.7

19

rnA

TRANSIENT RESPONSE
Rise Time (Note 6)

25°C

2.0

0.2

2.0

0.2

/1s

Overshoot (Note 6)

25°C

5

15

5

15

%

Slew Rate (Note 7)

25°C

0.1

0.8

0.1

0.8

V//1s

25°C
Full

20

OUTPUT CHARACTERISTICS
Output Voltage Swing (Note 3)

POWER SUPPLY CHARACTERISTICS
Supply Current
Power Supply Rejection Ratio (Note 8)

NOTI;S:

Full

74

450

100

50
150

100

VSUPPL Y = ±3.0V

4. V CM =±1.SV
5. V 0

6.

= :t2.0V

•

VSUPPL Y = :t15.0V

ISET = 1.SI.IA

T = +2SoC

T = Ful!
V CM = ±5.0V
Vo

= ±10.0V

AV= +1, VII'I =400mV, RL = 5K,C L = 100pF

7. Vo = :t2.0V
B. f)"v = ±1.SV

Vo = :t10.0V
tlv = tS.OV

9. Vo = ±1.0V

Vo = t10.0V

10. This parameter based upon design calculations.

RL = 20K

V

Q

210

20

210
50

450
150

1. For supply voltages less than tlS.0V. the absolute maximum input voltage is equal to supply voltage.
2. Derate at 6.8mWfOC for operation ambient temperatures above 75°C.
3. T - +2SoC and Full

2-54

HA-2725
DoC to +75 0C

ISET

= 1SI.IA

/1A
/1A
/1V/V

PERFORMANCE CURVES
UNLESS OTHERWISE NOTED: T A = +25 0 C, Vs = ±15VDC

INPUT BIAS CURRENT
vs. SET CURRENT
100

==

INPUT BIAS CURRENT
vs. TEMPERATURE
10

t3V:$VSS't 1BV

16

~lV:£VS:O;: t

I'

lav
0

"I'-...

l"- t--..

ID

i'-... .......
r-

""

~50oC

_25°C

0"

!3~5"VS<~lHV

,
'SET

o

I5,UA

..... ~ ......

0

,

~

.......... r-

0

, ...........

Isn'\SJjA

0

100

ID

SI,Curranl(uA!

+250C+50°[; +150C +\oooe
T'mperil~re

CHANGE IN OFFSET VOLTAGE
vs.ISET (UNNULLEOI

.0

INPUT OFFSET CURRENT
vs. TEMPERATURE

INPUT NOISE CURRENT
vs.ISET

+12~oC

.

·lSC

-soc

·25t

ISET'IS .. A

ISET"5IJ

DC

A1

*25V -SO
Temlle.ilure

.

+l!!C

+\OOt '125 0C

II

INPUT NOISE VOLTAGE
vs.ISET

1111111 II

~M~'~VS~t3V

i.--'

,
0

"

10

100

Sdturunl-llA

Stt CII",nt (,uAI

INPUT NOISE VOLTAGE AND CURRENT
vs. FREQUENCY

SlICllrr'IIIIPA)

OPTIMUM SET CURRENT FOR MINIMUM
NOISE vs. SOURCE RESISTOR

F'lqljlrcylHd

2-55

PERFORMANCE CURVES
UNLESS OTHERWISE NOTED: TA

=+ 25 0 C, Vs =± 15VDC

MAXIMUM OUTPUT VOLTAGE SWING
vs. LOAD RESISTANCE

GAIN BANDWIDTH PRODUCT
vs.ISET

OPEN LOOP VOLTAGE GAIN
vs. TEMPERATURE

ISET= 15 UA

ISET-15LJA

Vs"t15V

24f--++~lI-:l4-Hllt!l--t-I~tIt--+ttttt1H

1/

Lilli

V

VS=:t 15V

_t::S.ETOI'5IJA

L

'00K

~ ........

,

'S~T:~~ ~

~

K

40 K

lSET~

-;?

~

-

30 K

,~!~LLUll~~~~IO~K~~~~~~'M

•

f

K

LoaclAlllstance

-so'c

S!ICu".nl-LJA

OPEN LOOP VOLTAGE GAIN
".ISET

POWER SUPPLY REJECTION
vs.ISET

_25 0 C

D'C
"'C
Temperature

vs.ISET

...

.

,'

01

S,tCurr'nll,uA)

"

10

SIlCurrenf-],JA

SeICu'rent-LJA

SUPPLY CURRENT vs.
TEMPERATURE

NORMALIZED BANDWIDTH
VS. TEMPERATURE

24Df----!----j----+-+-+--"---I-",,.---f----!
VS=t 15V

'"D~~=:::t=:t=t=t=+==t==1

J

1~:15LJA

'~
15ET=15].JA~
1

12Df----!--t---+-+-+--t----t-----!
8Of-----!----j---+--+-+--+--l----1
4Of----!-'-"-'.+'_'_"A--+_+_-If--'vs:..,·+"-,'v,-L,.,-----!
Vs-:t 3V

_sooe

2-56

-250C

DoC

25°C
500e
Temperature

150C:

loooe

125°(,

50 0 e:

75°C

STANDBY SUPPLY CURRENT

11111111 II
11111111 II

'03:,L.,;-'L....J..LLlW!~.LJ...LillL!I;;IO-.l-l.UJ.l.!!!'OO

ISET"'~ ~

°

~

,

.
SOC

- 25 'C

D'C

i'-"

-....

t'--

+25 0C +500e +15 0C+1000C+125°
TIIIIPllll1ure

\QoDe

115 'C

PERFORMANCE CURVES
PHASE MARGIN

SLEW RATE vs. 'SET

VS.

SET CURRENT

90"

so"

l/OU

, ,,_

~ 60°

~

-''-+-_-._OVOUT
OUTPUT

SKI<

V

1\

'/
VERTICAL

5V1DIV

HORIZONTAL

I.uS/DiV

DV

ISET ~ IDOPA

v-

2-57

m~RIS

HA-2730/35
Wide Range Dual Programmable
Operational Amplifier

FEATURES

DESCRIPTION

• WIDE PROGRAMMING RANGE
SET CURRENT
SLEW RATE
BANDWIDTH
BIAS CURRENT
SUPPLY CUR RENT

•

• WIDE POWER SUPPLY RANGE

0.1 TO 100J..lA
0.06 TO 6V /J..I s
5kHz TO 10MHz
0.4 TO 50nA
lJ..1A TO 1.5mA
11.2TO 118V

• CONSTANTAC PERFORMANCE OVER SUPPLY
RANGE

APPlICA TIONS

HA-2730/2735 Dual Programmable Amplifiers are internally
compensated monolithic devices offering a wide range of performance, that can be controlled by adjusting the circuits' "set"
current Usn). By means of adjusting an external resistor or
current source, power dissipation, slew rate, bandwidth, output
current and input noise can be programmed to desired levels.
Each amplifier on the chip can be adjusted independently. This
versatile adjustment capability enables HA-2730/2735 to provide optimum design solutions by· delivering the required level
of performance with minimum po~ible power dissipation.
HA-273012735 can, therefore, be utilized as the standard
amplifier for a variety of designs simply by adjusting their
programming current.
A major advantage of HA-2730/2735 is that operating characteristics remain virtually constant over a wide supply range
(±1.2V to ±15Vl, allowing the amplifiers to offer maximum
performance in almost any system including battery-operated
equipement. A primary application for HA-2730/2735 is in
active filters for a wide variety of signals that differ in frequency
and amplitude. Also, by modulating the "set" current, HA2730/2735 can be used for designs such as current controlled
oscillators, modulators, sample and hold circuits and variable
active filters.

• ACTIVE FILTERS
• CURRENT CONTROLLED OSCILLATORS
• VARIABLE ACTIVE FILTERS
• MODULATORS·

HA-2730 is guaranteed over -55 0 C to +125 0 C. HA-2735 is
specified from OOC to +75 0 C. Both parts are available in 14
lead D.I.P. package or dice form.

• BATTERY-POWERED EQUIPMENT

PINOUT

SCHEMATIC
Section 11 for Packaging

TOP VIEW
ISET
OUT

v+
ISET
OUT

VNOTE: Bottom of package Is connected to V-.

lONE HALF)
\ ONLY
HA-2730/35

2-58

SPECIFICA TlONS

ABSOLUTE MAXIMUM RATINGS
Voltage Between V+ and V- Terminals
Differential Input Voltage
Input Voltage (Note I)
ISET (Current at ISET)
VSET (Voltage to Gnd. at ISET)

ELECTRICAL CHARACTERISTICS
V+ ; +3.0V, V-; -3.0V

45.0V
±30.0V
±15.0V
500.uA
V+ - 2.0V $ VSET $ V+

Power Dissipation (Note 2)
500mW
Operating Temperature Range:
HA-2730 -55°C $ TA $ +125 0 C
HA-2735
OOC $ TA $ +75°C
Storage Temperature Range
-65°C $ TA $ +150°C

(Each Side)

HA-2730
-55°C to + 125°C
PARAMETER
INPUT CHARACTERISTICS
Offset Voltage

TEMP.

HA-2735
OOC to +75 0 C

ISET = ISf.1A
ISET = 1.5f.1A
ISET = l. S.uA
ISET - 15f.1A
MIN. TYP. MAX. MIN. TYP. MAX. MIN. TYP. MAX. MIN. TYP. MAX. UNITS

2SoC
Full

2.0

3.0
5.0

2.0

3.0
5.0

2.0

5.0
7.0

2.0

5.0
7.0

mV
mV

Offset Current

25°C
Full

0.5

3.0
7.5

1.0

10
20

O.S

5.0
7.5

1.0

10
20

nA
nA

Bias Current

25°C
Full

2.0

5.0
10

8.0

20
40

2.0

10
10

8.0

30
40

nA
nA

Input Resistance (Note 10)

25 0 C

SO

5

50

5

MQ

Input Capacitance

25 0 C

3.0

3.0

3.0

3.0

pF

25 0 C
Full

15K 40K
10K

15K 40K
10K

40K

V/V
V/V

Full

80

80

TRANSFER CHARACTERISTICS
Large Signal Voltage Gain (Notes 3 & 9)
I

Common Mode Rejection Ratio (Note 4)
OUTPUT CHARACTERISTICS
Output Voltage Swing (Note 3)

15K
10K

40K

15K
10K

74

dB

74

2S oC
Full

±Z.O ±2.2
±Z.O

±2.0 ±2.2
±1.9

±Z.O ±2.2
±Z.O

±2.0 ±2.2
±2.0

V
V

Output Current (Note 5)

25 0 C

±0.2

±2.0

±0.2

±Z.O

rnA

Output Resista~ce

2S oC

2K

500

2K

500

Output Short-Circuit Current

2S oC

2.8

14

2.8

14

rnA

TRANSIENT RESPONSE
Rise Time (Note 6)

25 0 C

2.5

0.25

2.S

0.25

f.1s

Overshoot (Note 6)

25 0 C

5

10

5

10

%

Slew Rate (Note 7)

25 0 C

0.07

0.70

0.07

0.70

V/f.1s

25 0 C
Full

15

POWER SUPPLY CHARACTERISTICS
Supply Current (Each Amp)
Power Supply Rejection Ratio (Note 8)

Full

250

100

ioo

250

25
150

Q

170

15

170
25

150

II

f.1A
f.1A
f.1 V/V

2-59

SPECIFICATIONS
ELECTRICAL CHARACTERISTICS

(Each Side)

V+=+15.0V, V-=-15.0V
HA-2730
-55°C to +125 0 C
PARAMETER

TEMP.

INPUT CHARACTERISTICS
Offset Voltage

HA-2735
OOC to +75 OC

ISET = 151lA
ISET = 1.51lA
ISET - 1.51lA
ISET = 151lA
MIN. TYP. MAX. MIN. TYP. MAX. MIN. TYP. MAX. MIN. TYP. MAX. UNITS

25°C
Full

2.0

3.0
5.0

2.0

3.0
5.0

2.0

5.0
7.0

2.0

5.0
7.0

mV
mV

Offset Current

25°C
Full

0.5

3.0
7.5

1.0

10
20

0.5

5.0
7.5

1.0

10
20

nA
nA

Bias Current

25°C
Full

2.0

5.0
10

8.0

20
40

2.0

10
10

8.0

30
40

nA
nA

Input Resistance (Note 10)

25°C

50

5

50

5

MQ

Input Capacitance

25°C

3.0

3.0

3.0

3.0

pF

25°C
Full

30K lOOK
20K

25K lOOK
20K

25K 120K
20K

TRANSFER CHARACTERISTICS
Large Signal Voltage Gain (Notes 3 & 9)

Common Mode Rejection Ratio (Note if) 25°C
Full

30K 120K
20K

80

80

74

74

dB
dB

25°C
Full

±12 ±13.5
±10

±12 ±13.5
±10

±12 ±13.5
±10

±12 ±13.5
±10

V
V

Output Current (Note 5)

25°C

±0.5

±5.0

±0.5

±5.0

rnA

Output Resistance

25°C

2K

500

2K

500

Q

Output Short-Circuit Current

25°C

3.7

19

3.7

19

rnA

TRANSIENT RESPONSE
Rise Time (Note 6)

25°C

2.0

0.2

2.0

0.2

Il s

Overshoot (Note 6)

25°C

5

15

5

15

%

Slew Rate (Note 7)

25°C

0.1

0.8

0.1

0.8

V/lls

25°C
Full

20

OUTPUT CHARACTERISTICS
Output Voltage Swing (Note 3)

POWER SUPPLY CHARACTERISTICS
Supply Current (Each Amp)
Power Supply Rejection Ratio (Note 8)
NOTES:

Full

90

90

90

20

210
450

50

210
50

150

100

100

90

450
150

1. For supply voltages less than ±15.0V. the absolute maximum input voltage is equal to supply voltage.
2. Derate at 4.7mW;OC at ambient temperatures ahove 6SoC.
VSUPPLY = :t:l.OV
3. T-+2SoCand Full

4. V CM =±.l.SV
S. Vo

= ±2.0V

VSUPPLY = ±15.0V

ISET = 1.51lA

ISET = 151lA

T=+2SoC

RL =7SKn

RL =SKn

T = Full
V CM = ±.5.0V

RL = 7SKn

RL = 7SKn

VO= ±10.0V

6. -·-----AV = +1. V 1N = 400mV, RL = SK. C L = 100pF
7. VO=±2.0V
8. t!.V =±l.SV

V O =±10.0V
t!.V = ±5.0V

9. Vo = ±1.0V

Vo = ±10.0V

10. This parameter value based upon design calculations.

2-60

V/V
V/V

RL =20K

Il A
IlA
Il V/V

PERFORMANCE CURVES

UN LESS OTHERWISE NOTED: T A = 25°C, Vs = ±15VDC

INPUT BIAS CURRENT
.. SET CURRENT

INPUT BIAS CURRENT
v,. TEMPERATURE

:::::

INPUT OFFSET CURRENT
vs. TEMPERATURE

:!:3V~VS!tlBV

"~-4---+---+--~--+---+---~-4

~r---.... IseT~15pA

1O~.....J---+---+--~--+---+---~-4

'"
'.'

0.50De

10
Sal CUHlnl

(.uAl

..

,
~

f
~.5
i

.250C

DOC

+250C+500(;

+750(;+I001l(;+,250C

Temperature

CHANGE IN OFFSET VOLTAGE
v,.ISET IUNNULLEO)

>

-

"II'i'..~i""1~1':::ET1·'~':::'·:At=t:=~-=~

'SET- 15IJ A

.~.~"o",""'::!";;;'--l;!c";;;C-;'!;;""'-':-;!'~~'V~.7:,,:;;."'-.,:7:5'O"c-.,",,,:O";;;'-"-:!125'OC
Temperature

INPUT NOISE VOLTAGE
v,.ISET

INPUT NOISE CURRENT
v,.ISET

1111111 III

...

I::W~VS2:t3V

•

"
'.1

1

100

10

SdCurrent-lJA

Sn Currenl (J,lAj

Stt Curr.nl (JlAJ

INPUT NOISE VOLTAGE AND CURRENT
v,. FREUUENCY

OPTIMUM SET CURRENT FOR MINIMUM
NOISE v,. SOURCE RESISTOR

Frequ.ncy(Hz)

SoulteRnI.lor

2-61

•

PERFORMANCE CURVES
UNLESS OTHERWISE NOTED: TA

=25°C, Vs =t15VDC

GAIN BANOWIDTH PRODUCT
vs.ISET

MAXIMUM OUTPUT VOLTAGE SWING
vs. LOAD RESISTANCE

OPEN LOOP VOLTAGE GAIN
'vs. TEMPERATURE

,
ISET=15lJ,A

'SET zI5 U"

•

J

111111

'00

vs·t1 5V

,
"
,
4D,
,
,

"

VS"tI5V

,

ISET=1 15 \.1A

./

~~

IS~T=151J~ ~

'"

1D

"
B

3D

,

•

'00

"

10K

. f.

1D
-SOC

'"

lOOK

Load RUlstilnce

OPEN LOOP VOLTAGE GAIN
vs.ISET

-25C

POWER SUPPLY REJECTION
vs.ISET

"B _ _

-.

:;.- ~

ISET=l~ r--..

ISET"0

OC

2St

.

SOC

1SC

Temperature

STANOBY SUPPLY CURRENT
vs.ISET

11111111 II
11111111 II

YS·tlIiV

l

!
i

"5~_.
I--

Vs-t3Y

'''--

,.,

'~~.,~~~~__~~~~,__~LU~
SUCurr.ntl,ttAI

10

100

SUCuITenl-IJA

SUPPLY CURRENT vs.
TEMPERATURE

NORMALIZEO BANDWIDTH
.s. TEMPERATURE

3

~151JA

'~
ISET=15UA~~
1

12'

r--+---+---t--+-+--f--f-----j

9

4Dt---f_'S_E_T'+'_5_"A-I-_+_~V~s_"r-'~'v~~-f

B

·500C

-25 DC

DOC

ZSoC
Temperit~re

2-62

,

aot---f--f--I--+-+--f--f----J
Vs"tlV
sooe

75 DC

lOooe

1250C

. "'

loDe

"-

"
. . .

........

.

-soc

25C

ac

t25C +50C
T~_--+-oVOUT
OUTPUT

5KQ

/

\.

V

OV

VNOTE

Numb~rs In

paranlhsI$ refer 10 Ihe second hall.

VERTICAL:

5V/OIV

HORIZONTAL:

IPS/DiV

ISET

=

lOO,llA

2-63

HA-2740
Quad Programmable
Operational Amplifier
FEATURES
•

DESCRIPTION

WIDE PROGRAMMING RANGE
~

SLEW RATE
~ BANDWIDTH
~BIAS CURRENT
~ SUPPLY CURRENT

•

O.BV/J.ls

lMHz
BnA
250J.lA

•

WIDE POWER SUPPLY RANGE

•

CONSTANT AC PERFORMANCE OVER
SUPPLY RANGE

APPLICATIONS
•

ACTIVE FI LTERS

•

CURRENT CONTROLLED OSCILLATORS

•

VARIABLE ACTIVE FILTERS

•

MODULATORS

•

BATTERY-POWERED EQUIPMENT

SCHEMATIC
Section 11 for Packaging

TOP VIEW
---''-t---,

15

---''-li--I.''"T

14
13

+v
+ IN B

--"-I-~...t

-IN B

~-t--l!;,

OUT B - - ' , - - - '

SET A, B, a

2-64

16

-IN A ---"-I-~.....

+ IN A

A major advantage of the HA-2740 is that operating characteristics remain
virtually constant over a wide supply range ( ± 1.2V to ± laV), allowing
the amplifier to offer maximum performance in almost any system including battery-operated equipment. A primary application for the HA-2740
is in active filters for a wide variety of signals that differ in frequency
and amplitude. Also, by modulating the "set" current, the HA-2740
can be used for designs such as current controlled oscillators, modulators,
sample and hold circuits and variable active filters.
The HA-2740-2 is guaranteed over -55 0 C to +125 0 C. The HA-2740-5
is specified fromOoC to +75 0 C. Both parts are available in a 16 pin
dual-in-Iine package.

PINOUT

OUT A

The Harris HA-2740 programmable amplifier is an internally compensated
monolithic device offering a wide range of performance, that can be controlled by adjusting the circuit "set" current USET). By means of adjusting an external resistor or current source, power dissipation, slew rate,
bandwidth, output current and input noise can be programmed to desired
levels. This versatile adjustment capability enables the HA-2740 to provide
optimum design solutions by delivering the required level.of performance
with minimum possible power dissipation. The HA-2740 can, therefore,
be utilized as the standard amplifier for a variety of designs simply by
adjusting programming current.

--=-+----'

12
11
10

aUTO
-IN 0

+ IN 0

-v
+ IN C
-IN C
OUT C
SET C

SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS (Note

1)

Voltage Between V+ and V- Terminals
45.0V
Differential Input Voltage
±30.0V
Input Voltage (Note 2)
± 15.0V
500J.,lA
ISET (Current at ISET)
VSET (Voltage to Gnd. at ISET)
V+ - 2.0~ VSET ~ V+

ELECTRICAL CHARACTERISTICS

Power Dissipation

300mW

Operating Temperature Range:
HA-2740-2
HA-2740-5

-55 0 C ~ TA ~ +125 0 C
ODC~TA~+75DC

-65 DC ~ TA ~ +150 0 C

Storage Temperature Range

V+=+15.0V, V-=-15.0V
HA-2740-2
-55 0 C to +1250 C

HA-2740-5
ooc to +750 C
~-

ISET = 1.5pA

ISET = 15pA

ISET = 1.5pA

ISET" 15pA

TEMP

MIN TYP MAX

MIN TYP MAX

MIN TYP MAX

MIN TYP MAX

UNITS

Offset Voltage

25 0 C
Full

2.0

3.0
5.0

2.0

3.0
5.0

2.0

5.0
7.0

2.0

5.0
7.0

mV
mV

Offset Current

25 0 C
Full

0.5

3.0
7.5

1.0

10
20

0.5

5.0
7.5

1.0

10
30

nA
nA

Bias Current

25 0 C
Full

2.0

5.0
10

B.O

20
40

2.0

10
10

8.0

30
40

nA
nA

Input Resistance (Note 3)

25 0 C

50

5

50

5

Mn

Input Capacitance

25 0 C

3.0

3.0

3.0

3.0

pF

PARAMETER
INPUT CHARACTERISTICS

II

TRANSFER CHARACTERISTICS
Large Signal Voltage Gain (Note 4)

25 0 C
Full

Common Mode-Rejection Ratio (Note 5)

25 0 C
Full

30K lOOK
20K

30K 120K
20K

100

100
74

VIV
VIV

100

dB
dB

±.12 .± 14
:!:.IO

V
V

100

80

80

25K 120K
20K

25K lOOK
20K

74

OUTPUT CHARACTERISTICS
Output Voltage Swing (Note 6)

± 14

25 0 C ± 12
Full ± 10

±.12 ±14
:!:.10

±.12 ±.14
:!:.10

I

Channel Separation (Note 7)

25 0 C

110

110

110

110

dB

Output Current (Note 8)

25 0 C

±0.5

:!:.5.0

±0.5

'±5.0

rnA

Output Resistance

25 0 C

2K

500

2K

500

n

Output Short Circuit Current

25 0 C

3.6

16

3.6

16

rnA

ps

TRANSIENT RESPONSE
Rise Time (Note 9)

25 0 C

2,0

0.2

2.0

0.2

Overshoot (Note 9)

25 0 C

2

10

2

10

%

Slew Rate (Note 10)

25 0 C

0.1

0.8

0.1

0.8

Vips

25 0 C
Full

25

POWER SUPPLY CHARACTERISTICS
Supply Current (each amp)
Power Supply Rejection Ratio (Note 11)

Full

250
50

100

25

100

250
50

450
150

450
150

pA
pA
pVIV

NOTES:
1. Absolute maximum ratings are limiting values,

applied individually, beyond which the serviceability of the circuit may be impaired. Functional
operability under any of these conditions is not
nece'SSarily implied.

2. Forsupply voltages less than ±15V, theabsolute
maximum input voltage is equal to the supply
voltage.

5. VCM =± 5V
6. RL = 5kn @'ISET = 15pA, RL = 75K@ ISET = 1.5/'A
7. RS= lkll, f= 100Hz.
B. VO=i 10V
9. AV = 1, VIN = 2001 V, RL = 5k, CL = 100pF.

3. This parameter based upon design calculations.

10. Vo =± 10V, RL = 5K@ISET= 15/,A,
RL = 20K @ ISET = 1.5/'A

4. Vo =± 10V, RL = 5K@ISET= 15pA
RL = 75K@ ISET = 1.5pA

.11. AV="!.5V.

2-65

TEST CIRCUITS
LARGE AND SMALL
SIGNAL RESPONSE CIRCUIT
QV+

:. ~

RSET

~

~

IN ,...

IV

~"n
~

...J.....

LARGE SIGNAL RESPONSE

OUT

SMALL SIGNAL RESPONSE

VOLTS: InputA: 5V/Oiv.,
Output B: 5V/Div.
TIME: 50j.ls/Div.

•

±,. .:
"

VOLTS: InputA: 100mV/Div.,
Output B: 100mV/Oiv.
TIME: 11J.s/Div.

--

IN
OV

IN

ov

II
1\

OUT
OV

OUT
OV

VERTICAL: 5V/Oiv.
HORIZONTAL: 50j.l$/Div.

SET CURRENT

VS.

L
J

[\

\

VERTICAL: 100mV/Oiv.
HORIZONTAL: 1ps(D,iv.

SET RESISTOR

100M

c:

10M
Vs -± 15V

-

-

VS-±3V

~

"

1M

ISET
lOOK

10K
0.1

I

10

SET CURRENT IliA)

2-66

100

Vs
±'1.5V

I.5IJA
1.2M!1

15IJA
120K!1

±.3.0V

'3.2OM!1

320K!1

.±.6.0V

7.OM!1

700Kn

±15V

19M!1

1.9Mn

HA-4156
High Performance,Quad
Operational Amplifier
FEATURES

DESCRIPTION

•

SLEW RATE

1.6 VIpS (TYP.)

•

BANDWIDTH

3.5 MHz (TYPJ

.INPUTVDLTAGENOISE(f=lKHz)

9 NV/..j;; (TYP.l

.. INPUT OFFSET VOLTAGE

0.5 mV (TYPJ

"

INPUT BIAS CURRENT

60 nA (TYPJ

The HA-4156 contains four general purpose operational
amplifiers on a monolithic chip. The performance of each
amplifier is equal to or better than the 741 type amplifier
in all respects. Its superior bandwidth, slew rate and noise
characteristics make it an excellent choice for active filter
or audio amplifier applications.

G

SUPPLY RANGE

±2V to ± 20V

The HA-4156-5 is guaranteed over OOC to +75 0 C.

•

NO CROSSOVER DISTORTION

o

STANDARD QUAD PIN-OUT

PINOUT

•

SCHEMATIC

. . . .p--o ..

r--~~---..-----...--t-

,~.-~~=-

___

-+_~m

.

OUT

.7

'-+--C014

(14) HA-4156

2-67

SPECIFICA TIONS
ABSOLUTE MAXIMUM RATINGS
TA =+25 0C Unless Otherwise Stated
Voltage Between V+ and V- Terminals
Oifferentiallnput Voltage
Input Voltage (Note 11
Output Short Circuit Ouration (Note 2)

40.0V
±30.DV
±15.0V
Indefinite

Power Oissipation (Note 3)
Operating Temperature Range
HA-4156-5
Storage Temperature Range

880mW

OOC5TA~+750C

-650C5TA~+1500C

ELECTRICAL CHARACTERISTICS
HA-4156-5
DoC to +75 0C

V+= 15V, V- =-15V
PARAMETER

•

INPUT CHARACTERISTICS
Offset Voltage
Av. Offset Voltage Drift
Bias Current

Offset Current
Cammon Made Range
Differential Input Resistance
Input Noise Voltage If = 1KHz)
If = 20Hz to 20kHz)
TRANSFER CHARACTERISTICS
Large Signal Voltage Gain (Note 4)

TEMP.

+25 0C
Full
Full
+25 0C
Full
+25 0C
Full
Full

MIN.

1.0
5.0 .
5
60
30

5
9
1.4

+25 OC
+25 0 C
25K
15K
80
74

Channel Separation (Note 5)
Small Signal Bandwidth
OUTPUT CHARACTERISTICS
Output Voltage Swing (RL = 10K)
(RL = 2K)
Full Power Bandwidth (Note 4)
Output Current (Note 6)
Output Resistance

Full
Full
+25 0 C
Full
+25 0C

il2
ilO
20
i5

TRANSIENT RESPONSE (Note 71
Rise Time
Overshoot
Slew Rate

+25 0 C
+25 0 C
+250 C

1.3

POWER SUPPLY CHARACTERISTICS
Supply Current (1+ or Ii
Power Supply Rejection Ratio (Note 8)

+25 0C
Full

80

NOTES:

1. For.supplv voltages less than

2.8

UNITS

5.0
6.5

mV
mV
/lV/OC
nA
nA
nA
nA
V
Mn
nV/.JHZ
jJVRMS

300
400
50
100

2.0

50K

-108
3.5

V/V
y/V
dB
dB
dB
MHz

i13.7
i12.5
25
il5
300

V
V
KHz
rnA
n

75
25
il.S

ns
%

V//ls

7.0

±15V, the absolute

maxImum Input voltage is equal to the supply

voltage.
2. One amplifier may be shorted to ground Indeflnltely.
3. Derate 5.8mW/oC above T A = +25 D C.

2-68

MAX.

il2

+250~

+25 OC
Full
+25 0C
Full
+25 0 C
+25 0 C

Common Mode Rejection Ratio (Note 8)

TYP.

rnA
dB

4. VOUT = ±to, RL = 2K
5. Referred to Input; f = 10KHz, RS = 1 K
6. V OUT =±10

7. See pulse response characteristics
S. Av =±5.0V

PERFORMANCE CURVES
V+

= +15V, V- = -15V, TA = +250 C
Unless Otherwise Stated.
OUTPUT VOLTAGE SWING
VS. FREQUENCY

11111

OPEN LOOP FREQUENCY RESPONSE

vo-zav

0

+11 0

+9 0

+7 0

+6 0
+5 0
+4 0

+3 0

,

IJ~I~2~t

I

+8 0

11 -.IOY

vo·,v

~~ ~:!:5V

110. 211

V

0

illllil II

111""1
11111111

+10 0

Cl"50pF

-:!'zv

i'.

0

IVOLTAGE FOLLOWERI

.If--

AL'"OPEN
Cl-SDpF

1

+1 0

11111
lK
10K
FREQUENCY - Hz

1M

lOOK

II

1111

180'

0
-1 0

100

"'"

0'

+2 0

10

11 -:!:lSV

10M

1111111

100

10'
fREQUENCY. HI

lOOK

1M

NORMALIZED AC PARAMETERS
VS. TEMPERATURE

NORMALIZED AC PARAMETERS
VS. SUPPLY VOLTAGE
2

I

BANDWID~

0

I

/~
SLEW RATE

BANDWIDTH

os

08

10

/

:--

",.

,/

I

......

Br:;-D~

StEW RATE

i'-.

I

7

"

:!:ID

:!:15V

,

I

0

0

IIIII

R~ !)!

I

,I'-.
60

1-1',

'~
,

,
BANDWIDTH

~NOISEVOlTAGE

'"

30

i'-.

4

L\'

,

I\.

,
20

2

02

I'-.

I

NOISECURRENT

o,

100

'OK
fREOUENCY-Hz

7

•
,

PHASE MARGIN

50

I'..

+125

SMALL SIGNAL BANDWIDTH AND PHASE
MARGIN VS. LOAD CAPACITANCE
I

~

.,00

+50

TEMPERATURE-oC

INPUT NOISE Vf'. FREQUENCY

o

+25

2S

:!"20

SUPPLYVOtTAGE

0

10.000

10

100,000

LOADCAPACITANCE-pF

2-69

PERFORMANCE CURVES (cont'd.)
MAXIMUM OUTPUT VOLTAGE
SWING VS. LOAD RESISTANCE

CHANNEL SEPARATION VS. FREQUENCY
·'40

I 11111111

I

I ,~,IIIIIII

I

-100

·80

""
-~
'"
.
'~-

-

."

lit·

=~

..0

_

·20

-

-"

0

II

"

'"

25

-

15

100 VOl

10 /

vjJ2

I

FREQUENCY -HI

V

20

C.S.• 20LDG(~)

,.

1111

30

-

I11t-.....1

-120

5

...

,

".

0
100

IK

10K

lOOK

LOAD RESISTANCE - OHMS

•

INPUT BIAS AND OFFSET CURRENT
VS. TEMPERATURE

POWER CONSUMPTION
VS. TEMPERATURE

'DO

'DO

80

160

_
VS·!15V

BIAS CURRENT

"

~

.........

f-I""'"

no

r-...

~

"

I'.
r--....

20

- ...

·50

.,.

0

..0
TEMPERATURE·DC

-

VS.tIOY

I--

-

vs·.tsv

-

"

~RREr

0

.

'75

.,"

+125

0

·50

-lS

0

.,.

..0
TEMPERATURE-DC

.75

"DO

+125

PULSE RESPONSE
TRANSIENT RESPONSE/SLEW
RATE CIRCUIT

v,.

t>!. ~Y'~

-=

2-70

":'"

SLEW RESPONSE
(Volts: 5v /Div. Time: 5/ols/Div)

TRANSIENT RESPONSE
(Volts: 10mv/Div • Time: 100ns/Div)
I ...
I~

/

\.

I

m1 H.ARRIS

HA-4600/02/05
High Performance
Quad Operational ARlPlifier

FEATURE.t:

DESCRIPTION

•

LOWOFFSETVOLTAGE

•

HIGH SLEW RATE

0.3mV
±4V l}ls
8MHz

• WIDE BANDWIDTH

2}lV/OC

o LOW DRIFT
•

FAST SETTLING (q.01%, 10V STEP)

•

LOW POWER CONSUMPTION

•

SUPPLY RANGE

4.2}ls
35mW/AMP
±5V TO ±20V

APPlICA TIONS
•

HIGHQ,WIDEBANDFILTERS

•

INSTRUMENTATION AMPLIFIERS

• AUDIO AMPLIFIERS
•

DATA ACQUISITION SYSTEMS

•

INTEGRATORS

•

ABSOLUTE VALUE CI RCUITS

The HA-4SOO series are high performance dielectrically isolated
monolithic quad operational amplifiers with superior specifications not previously available in a quad amplifier. These amplifiers offer excellent dynamic performance coupled with low
values for offset voltage and· drift, input noise voltage and
power consumption.

II

A wide range of applications can be achieved by using the
features made available by the HA-4SOO series. With wide
bandwidth (8M Hz), low power (35mW/amp), and internal
compensation, these devices are ideally suited for precision
active filter designs. For audio applications these amplifiers
offer low noise (8nV I JHz) and excellent fuil power bandwidth
(SOkHz). The HA-4602/4605 is particularly useful in designs
requiring low offset voltage (O.3mV) and drift (2}lV/OC), such as
instrumentation and signal conditioning circuits. The high slew
rate (4V/ps) and fast settling time (4.2ps to 0.01%, 10V step)
makes these amplifiers useful comfloinents in fast, accurate data
acquisition systems.
The HA-4600 series are available in 14 pin CERDIP packages
which are interchangeable with most other quad op amps.
HA-4SOO/4S02-2 is specified from -55 0 C to +125 0 C and
HA-4SOO/4S05-5 is specified over OOC to +75 0 C range. '

o TONE DETECTORS

PINOUT

SCHEMATIC
Section 11 for Packaging

TOP VIEW
Out

14

1

Out
4

13

Inputs
1

v+

12
11

Inputs
4

v-

10
Inputs
2

Out

Inputs
3

Out
3

ONE FOURTH ONLY (HA-4S00)

2-71

SPECIFICA 1IONS
ABSOLUTE MAXIMUM RATINGS (Note 1)
TA = +25 0 C Unless Otherwise Stated
Voltage Between V+ and V- Terminals
Oifferentiallnput Voltage
Input Voltage (Note 2)
Output Short Circuit Ouration (Note 3)

ELECTRICAL CHARACTERISTICS

PARAMETER

•

Power Dissipation (Note 4)
Operating Temperature Range
HA-4600/4602-2
HA-4600/4605-5
Storage Temperature Range

40.DV

±7V
±15.0V
Indefinite

880mW
-55 0C~TA;5+125 0 C
OOC~TA~+750C
-650C~TA~+150oC

V+=+15V, V-= -15V

TEMP

HA-4600-2
HA-4600-5
TYP
MAX
MIN

HA-4602-2
HA-4605-5
TYP
MAX
MIN

0.3

3.0

UNITS

INPUT CHARACTERISTICS
Offset Voltage
Av. Offset Voltage Drift
Bias Current
Offset Current
Common Mode Range
Input Noise Voltage (f" 1kHz)

+25 0C
Full
Full
+250C
Full
+25 0C
Full
Full
+25 0C

2
130
30

Common Mode Rejection Ratio (Note 9)
Channel Separation (Note 6)
Small Signal Bandwidth

5
200

200
325
75
125

t12

Input Resistance
TRANSFER CHARACTERISTICS
Large Signal Voltage Gain (Note 5)

2.5
3.0

70

9
10

mV
mV

400
500

IN/OC
nA
nA

150
175

±12
8

8

500

500

Full

lOOK

Full
+250C
+25 0C

86

Full
Full
+250C

t12
±10

±13
±12

Full
+25 0C

±10

60
t15

75K

250K

nA
nA
V

nV/jHz
kn

250K

-108

-108

V/V
dB
dB

8

8

MHz

±12
±10

±13
±12

V
V

60
t15

kHz

±8

200

200

n

50

80

OUTPUT CHARACTERISTICS
Output Voltage Swing (R L = 10K)
(RL = 2K)
Full Power Bandwidth (Note 5)
Output Current (Note 7)
Output Resistance

rnA

TRANSIENT RESPONSE (Note 8)
Rise Time
Overshoot
Slew Rate
Settling Time (Note 10)

2-72

+25 0C
+25 0C
+25 0C

POWER SUPPLY CHARACTERISTICS
Supply Current .

+25 0C

Power Supply Rejection Ratio (Note 9)

Full

1

50
30

ns

30
±4

±4

V/J.ls

4.2

4.2

J.lS

4.6
86

5.5

5.0
74

%

7.5

rnA
dB

NOTES:
1.

Absolute maximum ratings are limiting values, applied
individually, beyond which the serviceability of the circuit
may be impaired. Functional operability under any of
these conditions is not necessarily implied.

2.

For supply voltages less than ±15V, the absolute maximum
input voltage is equal to the supply voltage.

3.

Anyone amplifier may be shorted to ground indefinitely.

4.

Derate 5.8mW/oC above TA = +25 0 C.

5.

VOUT=±10V; RL=2Kohms.

6.

Channel separation value is referred to the input of the

amplifier. Input test conditions are: f = 10kHz; VIN =
200mV peak-to-peak; RS = 1K ohms. (Referto Channel
Separation vs. Frequency Curve for test circuits.)
7.

Output current is measured with VOUT = ±5 volts.

8.

For transient response test circuits and measurement
conditions refer to Test Circuits section of the data sheet.

9.

AV = ±5.0 volts.

10.

Settling time is measured to 0.1% of final value for a 10
volt input step, AV =-1.

TEST CIRCUITS
2<

•

2<
IN ~o-.M"-<_-l-

OUT

t~'

+
1<

LARGE SIGNAL
RESPONSE
CIRCUIT
(Volts: 5V!Div.,
Time: 5ps/Div.)

I
II

ov

SMALL SIGNAL
RESPONSE
CIRCUIT
(Volts: 10mV/Div.,
Time: 50ns/Div.)

OUTPUTh

I-'NPUT

I

II

".

\

/

1l---1/r-+---fI---'l
\.'--11--+-+--+---+

ov

\

HORIZONTAL: 50 NSECIDIV.

VERTICAl. IOmV/DIV
VERT.5V101V.
HORZ.5Il s/DlV .

SETTLING TIME CI RCUIT

......
,..
1
I...

1"l1li

+15V

(')

'N,,,,

J.
I

5Kn
.AAA

5Kn
AA.A

2Kn

~
2Kn~

"V TO
OSCILLOSCOPE

•

AV=-1.

•

Feedback and summing
resistors should be 0.1%.

• Clipping diodes are optional.
HP5082-2810 recommended.

2-73

PERFORMANCE CURVES
V+ = +15V, V- = -15V, TA = +25 0 C Unless Otherwise Stated.

OFFSET VOLTAGE INPUT BIAS AND OFFSET
CUR RENT VS. TEMPERATURE

,

,

2D
18

16

f"'-..

14 0

"O~
."0
~~

t- I--

-

0
-10

-30

1-

,

1

z

1

~

RL =2K
CL ~ 5DpF

"-

0

tG 0
.,0

I'

.,

0

"
,
4

GAI~

II'

PHASE

0

.20
0

k-~f--

135'

I'

"0
0

:-- I -

-

0

+4 0

V
Ivosl HA"'(600

111111111

0

~

(TYPICAl)

I'

0

1

r- ""-20 0

.,
.,
.,

1

........

lllllllL

.100

1

......... ' " OFFSETCURRENT

1;;1

*~

'11 0

..

,
~ ~ , I ' ~IASC~RREN~
~!

OPEN LOOP FREQUENCY RESPONSE

0
0

1BO'

10

100

lK

10K

[!I

1M

lOOK

10M

100M

fREQUENCY_HI

•

_-400
-80

."

-40

.80

"20

+160

TEMPERATURE·'C

SMALL SIGNAL BANDWIDTH AND PHASE
MARGIN VS. LOAD CAPACITANCE

,

"

,
50

,

40

II

I

I
I

PHASE MAR IN

'I.

OUTPUT VOLTAGE SWING
VS. FREQUENCY AND SUPPLY VOLTAGE
12
100

10

VS=+15V

Rl=2Kn

VS=±IDV

i

0

BANDWIDTH

v,.I± I,J

~

,

30

"-..

,

"

"

'" f'.

,

10

o,

-...... r--

100

o

111111

1

100

10,000

1000
LOAD CAPACITANCE - pF

1illl

1111

f",

10

(VOL rAGE FOllOWER)
RL=OO
CL=50pF

I

0

lK

lllliill

1M

10K
TOOK
FREQUENCY- Hl

10M

CHANNEL SEPARATION VS. FREQUENCY
-14 0

INPUT. NOISE VS. FREQUENCY

11111111 -I 11111111
JU 11111
I I lJ!!ttb...

-12 0

.~~
-.or--

r--.

-10

'V

-

lK

t---

-,OJ-r-4OJ--

j--2 OJ--

10

2-74

100

lK
FREQUENCY - Hl

10K

o
lOOK

0
10

VOl

+

-=

CS·20 LOG(...!2L)--

lOOk

~
+

'DO VOl
I

VCl2

lK

- 1111111
11111111

100

I I 1111111
I 11111111

I
I

lK
FREQUENCY -Hz

10K

lOOK

PERFORMANCE CURVES -(Continued)

NORMALIZED AC PARAMETERS
VS. SUPPLY VOLTAGE

NORMALIZED AC PARAMETERS
VS. TEMPERATURE
1.'

1.'

,

,

~
0.' f-- ~
1~

.1

.0
BANDWIDTY

•

/./

•

SLEW RATE

1.0

P

'/SLEWRATE

--+--..

IBAND~IO~

D.'

.7

D.7

±s

i'

tl2

±IS

SUPPLY VOLTAGE - VOL T8

D.'

+

."

-"

·40

+40

+80

+160

+120

Ter.tPERATURE·oC

II

PDWER SUPPLY CURRENT VS. TEMPERATURE
AND SUPPLY VOLTAGE

MAXIMUM OUTPUT VOLTAGE SWING VS. LOAD
RESISTANCE AND SUPPLY VOLTAGE

•
VS*'1t5V

........

4

i•

/"

"

•
,

-- --

/

•

~

i.

-

11111
11111
lK

o

."

lOOK

10K
LOAD RESISTANCE - OHMs

SETTLING TIME VS. OUTPUT
AMPLITUDE (Av =-1)

,
2
1

D

to.1

I JilL
i'.. 11111

"NJII
YOUT" IOV

1111

-

1111

I L

..
..

-

,
•

-l-l-W.
~III
Your· 2V

!1.0

tID

D,
.0.1

,
,

Ay .. -&

V.U T"ZV

Av··to

Your" ZV

,

+160

'<;;

,
,

'<;;

,
100Hz

AV"-5

.1.0
OUTPUT ERROR VOLTAGE. mY

+120

..,

lDO

I I
I I
I I

,"

V.~T -tOV

I I
V.~T· Iv

-

•

1111
1111

-

HA-4602 - COMMON MODE REJECTION
RATID VS. FREQUENCY

Your" lOY
Ay".10

Your"SV

,

VOUT"SV

OUTPUT ERROR VOLTAGE mV

TEMPERATURE·DC

AV·-IO

r-

".

-4.

SETTLING TIME VS. OUTPUT AMPLITUDE
AND SIGNAL GAIN (AV =-5 AND AV =-10)
.2

,
,

VS·:tlOV

~
Vs=:tsv_

i'

IV'I'ml

100

•

VS"!15V

/.

,1/
0

-

VS· 110V

1kHz

10kHz
FREQUENCY-Hz

100kHz

lMHz

,_10

2-75

APPLYING THE HA-460214605 QUAD OPERATIONAL AMPLIFIERS

1.

2.

POWER SUPPLY DECOUPLlNG: Although not absolutely
necessary, it is recommended that all power supply lines
be decoupled with .01 Jl F ceramic capacitors to ground.
Decoupling capacitors should be located as near to the
amplifier terminals as possible.
UNUSED OP AMPS: Unused op amp sections should be
connected in a non-inverting follower configuration with

the (+) input tied to ground in order to insure optimum
performance of devices being used.
3.

In high frequency applications where large value feedback resistors are used, a small capacitor (3pF) may be
needed in parallel with the feedback resistor to neutralize
the pole introduced by input capacitance.

APPLICATIONS

2ND ORDER STATE VARIABLE FILTER (1kHz,

a = 10)

R6
L-~~~-t--------------------~-{)BANDPASS

948K

r--------------,
I

I
I

I
I

II

I
I

49.9K

BAND
REJECT

I

24.9K

I
I
:

-=

IL ___________
(OPTIONAL)
,-..J:

The state variable filter is relatively insensitive to component
changes (changes can' be adjusted out with potentiometers)
and also has low sensitivity to amplifier bandwidths. (Amplifier
gain bandwidth product should be» Q x fC). The bandwidth
criteria will determine whether a general purpose op amp like
Harris HA-4741 or the wide band HA-4602/4605 should
be used.
This filter finds wide application because multiple filtering
functions are available simultaneously (H igh pass, Lo pass,
Band pass, Band reject). In this circuit the various RC products
are matched with pot adjustments allowing for non-interactive

2-76

adjustment of Q and fC. This allows capacitors (Cl, C2) with
loose tolerances to be used. To tune for fC, apply a sine wave
at fC to the input, adjust R1 for equal amplitudes at the Hi pass
and Band pass terminals (they will be phased 90 0 apart) then
adjust R2 for equal amplitudes at the Band pass and Lo pass
terminals.
The state variable filter is often used as building blocks in
multiple pole Butterworth of Chebyshev filters. Many references
contain normalized tables indicating settings for Q and fC of
each pole- pair section.

APPlICA TlONS (Continued)
SALLEN AND KEY 2ND ORDER LO PASS FILTER

NOTES:
IN

R1

R2

OUT

The advantage of using the Sallen and Key filter is simplicity,
but in any application this must be weighed against the statevariable type filter for accuracy, practicality, and cost. Amplifier bandwidth limitations are much more apparent at moderate
frequencies and a values with this filter design. (For accuracy,
amplifier gain-bandwidth product should be»fc x 0 2). The
wide bandwidth of the HA-4602/4605 is particularly advantageous in this design even at audio frequencies.

1.

Make R1 = R2

2.

fc =

3.

Q= 'h

1
21TR1JC1C2

J

C2

C1

In this filter all component values affect both a and fC. Precision, temperature stable resistors and capacitors must be used.

II

For economy, this filter could be used in the Iowa stages
of multiple-pole filter design, while the state variable type is
used in the more critical stages.

INSTRUMENTATION AMPLIFIER

,--,
I

\

~~~~+-~
... _",'
,

'

I

rI
I
I
I
I
I

I

L_J.~T.!9~A~)__ J

Instrumentation amplifiers (differential amplifiers) are specifically designed to extract and amplify small differential signals
from much larger common mode voltages.
To serve as building blocks in instrumentation amplifiers, op
amps must have very low offset voltage drift, high gain and wide
bandwidth. The HA-4602/4605 is ideally suited for this appli-

cation, delivering superior input and speed characteristics.
The optional circuitry makes use of the fourth amplifier section
as a shield driver which enhances the AC common mode rejection by nullifying the effects of capacitance-to-ground
mismatch between input conductors.

2-77

HA-4620 /22 /25
Wideband, High Performance
Quad Operational Amplifier
FEATURES

DESCRIPTION
70MHz

• Wide Gain Bandwidth Product

±20V//J.s

• High Slew Rate
•

0.3mV

low Offset Voltage

2.51ls

• Fast Settling (0.01%, 1OV Step)

•

• Total Harmonic Distortion
• low 0 rift

<.01% to 30kHz
2 J..IV laC

• low Power Consumption

35mW/Amp

• Supply Range

±5V to ±20V

APPLICATIONS
• High

Q

Wide Band Filters

• Pulse Amplifiers

The HA-4620 series are wide band quad operational amplifiers featuring high slew rate, wide bandwidth and fast settling time specifications complemented by low input offset voltage, low drift and input
noise voltage.
These dielectrically isolated devices are optimized to offer excellent
features suitable for applications where a gain of 10 or greater is to be
used. The 35mW/amp and a 70MHz gain-bandwidth-product make
these monolithic amplifiers valuable components for many active filter
circuits. HA-4620 series offers 0.3mW offset voltages and 21lV/oC
offset voltage drift for very accurate signal conditioning designs. In
high performance audio applications, these amplifiers deliver 260kHz
full power bandwidth and 8nV jTfZnoise voltage. For fast accurate
data acquisition systems HA-4620 series offer 20V J..I s slew rate and
settling time of 2.5llSecs to 0.1% 10V step.
HA-4620'series are available in 14 pin CERDIP packages and are
interchangeable with most other quad op amps. HA-4625 is also
available in chip form. HA-4620/4622-2 is specified from -55 0 C to
+125 0 C and HA-4620/4625-5 is specified over DoC to +75 0 C range.

• Audio Amplifiers
• Data Acquisition Systems
• Absolute Value Circuits
• Video and R.F. Amplifiers

SCHEMATIC

PINOUT
Section 11 for Packaging

TOP VIEW
Out
1
Inputs
1
V+

Inputs
2
Out
2

Out
4
Inputs

4

vInputs
3

Out
3

ONE FOURTH ONLY (HA-4620)

2-78

SP~CIFICATIONS
ABSOLUTE MAXIMUM RATINGS

(Note 1)

TA =+25 0C Unless otherwise stated.
Voltage between V+ and V- Terminals
Differential Input Voltage
Input Voltage (Note 2)
Output Short Circuit Duration (Note 3)

Power Dissipetion (Note 4)
Operating Temperat~re Range
HA-4620/4622-2
HA-4620/4625-5
Storage Temperature Range

40.0V
±'7V
±'15.0V
Indefinite

880mW
-550C.~ TA'::; +1250C

ooC'::;TA''::;+750C
-65 0C'::; TA '::;+150 0C

ELECTRICAL CHARACTERISTICS

PARAMETER

TEMP

HA-4620-2
HA-4620-5
MIN
TYP
MAX

HA-4622-2
HA-4625-5
TYP
MIN
MAX
3.0

UNITS

•

INPUT CHARACTERISTICS
Offset Voltage

+25 0C
Full

0.3

Av. Offset Voltage Drift
Bias Current

.Full
+25 0C
Full
+25 0C
Full

2
130

Offset Current
Common Mode Range
Input Noise Voltage (f = 1kHz)
Input Resistance

Full

30

2.5
3.0

70

75
125

±12

+250C
+250C

5
200

200
325

9
10
400
500
150
175

±12

mV
mV

INloC
nA
nA
nA
nA
V

8

8

nV/.jHz

500

500

kn

250K

TRANSFER CHARACTERISTICS
Large Signal Voltage Gain (Note 5)
Common Mode Rejection Ratio (Note 6t
Channel Separation (Note 7)
Gain Bandwidth Products (Note 81

Full

lOOK

Full
+25 0C

86

+25 0C

75K

250K
-108

-108

VN
dB
dB

70

70

MHz

±12
±10

±13
±12

±8

260
t15

V
V
kHz

80

OUTPUT CHARACTERISTICS
Output Voltage Swing (RL = lOKI
(RL = 2KI
Full Power Bandwidth (Note 91 _

Full
Full
+25 0C

±12
±10

Output Current (Note 7)

Full
+25 0C

±10

Output Resistance

±13
±12
260

t15
200

rnA

200

n

TRANSIENT RESPONSE (Note 111
Rise Time
Overshoot
Slew Rate
Settling Time (Note 10)

+25 0C
+25 0C
+25 0C

±12

38

60

38

ns

45
±20

60

45
±20

ViliS

2.5

IJ.S

t12

2.5

%

POWER SUPPLY CHARACTERISTICS
Supply Current
Power Supply Rejection Ratio (Note 91

+25 0C
Full

4.6
86

5.5

5.0
74

7.5

rnA
dB

2-79

NOTES:

fier. Input test conditions are: f = 10kHz; VIN = 200mV
peak to peak; RS = 1 kn . (Refer to Channel Separation vs.
Frequency Curve for test circuits.!

1. Absolute maximum ratings are limiting values, applied individually, beyond which the serviceability of the circuit may be
impaired. Functional operability under any of these conditions is not necessarily implied.

8. AV=10; RL=2K; CL~10pF.

2. For supply voltages < .±. ISV, the absolute maximum input
voltage is equal to the supply voltage.

9. Full power bandwidth is guaranteed by equation:
Full power bandwidth = Slew Rate
2rrV Peak

3. Anyone amplifier may be shorted to ground indefinitely.

10. Output curreilt is measured with VOUT =.± SV.

4. Derate 5.8mW/OC above TA = +25 0 C.

11. Refer to Test Circuits section of the data sheet.

5 VOUT ='±'10V, RL = 2Kn
6.

~V

12. Setting time is measured to 0.1% of final value for a 1 volt
input step, and AV = -10.

=.±S.OV.

7. Channel separation value is referred to the input of the ampli-

•

TEST CIRCUITS
LARGE AND SMALL
SIGNAL RESPONSE CIRCUIT
IN

0... - - - -...~

IT ~~---'--~--O"'OUT

IV ;.~±~200n

»

-:!:-

II'

~+--+--+--r~~+--+--~~-10V

OUTPUT B

INPUT A ~+--1-+-t-F-t-t--+-t--I

INPUT

"J

'1

A+IJ4+-+~~r-r~Lr+~

1

\1-'"

VOLTS: Input A: .5V/Div., Output B: 5V/Div.
TIME: 500ns/Div.

VOLTS: Input A: .OlV/Div., Output B: 50mV/Div.
TIM E: 50ns/D iv.

SETTLING TIME CIRCUIT
+lSV

II ,

2N4416

'r-~~--oTO
,:on +l~V ~"1! 2:i
OSCILLOSCOPE
II~"""""""__O~VOUT

VIN

ou-_"""''''".''"=
...-=-,.....,~A.U
T."';

'2';'n

-15V

J.

50

T.,

•

AV"-1

•

Feedback and summing

•

ClipPing diodes are optional
HP5082-2810 recommended

resistors should be 0.1%

2Kn

ov

TYPICAL PERFORMANCE CURVES
V+ =+15V, TA =+25 0 C Unless otherwise stated.
OFFSET VOLTAGE INPUT BIAS AND
OFFSET CURRENT VS. TEMPERATURE
~ 180
,
m ..
z 16 0
~~
CI.I
~

.......

.I'AS

I-

~

a

OPEN LOOP FREQUENCY RESPONSE

2,0

20 0

_'20
-+100

,

---

,

>

"0

1.4 ~

"

"0

o

..0

t:::~
o

..0

0.8 ~

"0

.6

,

r-

.2

1,0

............ OFFSET CURRENT

:--- .......

0

-

0

0

1-

0
_-40 0

.0

-

V

--=-

,- I -

0,6

0,'

IVosllTYPICALI

0.2
..0

..0

TEMPERATURE

••0

7
w

>

-·

i::

•

GAIN

5'C

PHASE

,
,

.20

3500

"0

.000

1f

-'010

~

,K

'00

10K

lOOK

1M

10M

100M

FREQUENCY - Hoi:

+160

111Jll

•

RL"'ZK

"lowL

1111

'0 -

5

.±'OV

IIII11
4

"\

•

OUTPUT VOLTAGE SWING VS.
FREQUENCY AND SUPPLY VOLTAGE
'00

III

'"

0 'C

oc

60

·

CL"SOpF

..0

SMALL SIGNAL BANDWIDTH AND PHASE
MARGIN VS. LOAD CAPACITANCE

·

I""RL"' 'I''''''
2Kn

'SO

o
+120

11111 111111111

"00

,S

C~RRiNT

......... r-..,

140

"20

i'3

PHASE MARGIN

\

AV"'O
RL"CX)
CL -SOpF

'.0 I-

'\
2

·

'" ""-......i',

'0

DO

'0

I1111111

1.0

,

'K

'00

10K

'M

100K

FREQUENCY - Hz

'OM

0

'00

'000

LOAD CAPACITANCE - pF

CHANNEL SEPARATlONVS. FREQUENCY

INPUT NOISE VS. FREQUENCY

~
• i~
3 g

..

-140

I 11111111
I 1111
I J LlllIll

-120

~

-

-

V02

-

1Kn·

w

il

,~
~

'0

'00

,.
FREQUENCY - Hz

'0'

lOOK

0

""

-80 I~

o

-I

'0

+

100Kn

'='

c,s. '" 20 LOG

r~

~
'Kll

-60 _

-20

-

1Kn

_

...

I1'ttt-.
'~~nl Llilli
V01

-100

z

2 ~

I 11111111

~LIILlII

I 11111111
I 11111111

'00

j

V02

)

'OOVo,

L1111111

I 11111111
I 11111111

,.

'OK

'00.

FREQUENCY - Hz

2-81

I

TYPICAL PERFORMANCE CURVES I(Continued)

NORMALIZED AC PARAMETERS
VS. SUPPLY VOLTAGE

TOTAL HARMONIC DISTORTION
VS. FREQUENCY
.=~
=+1
un-

~

1.1

~c
a: fa 1.0

! ..,

~3

j,

BANDWIDTH __

~ ~ 0.'

file
NO

.

::; IU

y 0.0

U
",

v

I,
~

e.00,.

•

'DO

l.---:/ V"
/'

0.8

/SLEWRATE

~ 0.7

o

z'"

,.

±e

±.4

±1Z

SUPPLV VOLTAGE

'.K

'K
FREQUENCY - Hz

~

:t18

;tao

VOL T8

'DOK

MAXIMUM OUTPUT VOLTAGE SWING VS.
LOAD RESISTANCE AI,\ID SUPPLY VOLTAGE

NORMALIZED AC PARAMETERS
VS. TEMPERATURE
Z8

~

g ..
./

........

-r--:::-

"-.
~

SLEW RATE

•
•

BANDWIDTH

D.7
D••

-so

....

"D
TEMPERATURE DC

...

-

..10

Iva
'K

'DK
LOAD RESISTANCE - OHMS

--t

jS-t'5V

--k

VS·±1OV

±.

II

,..-

SETTLING TIME VS.
OUTPUT AMPLITUDE (AV = -10)

~.

VS·;t5V

±4

--

~

r-..

VOUT{'V

D

.toO.1

±1,O

OUTPUT ERROR VOLTAGE - mV

•-so

....

"D
TEMPERATURE

2-82

ac

...

+120

+'60

Tr

~.~ ..I,~j

rTii

~

·'DO

POWER SUPPLY CURRENT VS.
TEMPERATURE AND SUPPLY VOLTAGE

;to

-

J

.~
.,ao

,.."

ii"11
,DOK

APPLYING THE HA-462214625
1. POWER SUPPLY OECOUPLlNG: Although not absolutely
n~cessary, it is recommended that all power supply lines be
decoupled with .OWF ceramic capacitors to ground. Oecoupling capacitors should be located as near to the amplifier terminals as possible. If several amplifier sections are connected in
series, it is recommended that every third or fourth section be
decoupled.

2. UNUSED OP AMPS: Unused op amp sections should be connected in a non-inverting AV = 10 configuration with the (+)
input tied to ground in order to optimize performance of de-

vices being used.
3. In high frequency applications where large value feedback
resistors are used, a small capacitor (3pF) may be needed in
parallel with the feedback resistor to neutralize the pole introQuced by input capacitance.
4. When driving heavy capacitive loads (> 100pF), a small value
resistor should be connected in series with the output and
inside the feedback loop.

APPlICA TIONS
SUGGESTED METHODS FOR OFFSET NULLING
NON-INVERTING AMPLIFIER
INPUT

0---

Rl

~
+%

I~

,.!

INVERTING AMPLIFIER

O~UT

-

~Rl

NON-INVERTING ANO
INVERTING AMPLIFIERS
RANGE OF AOJUSTMENT
OETERMINEO BY PROOUCT
OF VSUPPLY ANO R3/R4 RATIO

.> R2

AV = 1 +

>

R5

~50Kn

R4
200Kn

~;

~100n

']

R2

IN~T

-

R5

~
HA-462

R4200Kn

+

~50Kn

R2:~3

•

1 -

OUTPUT

R3
~100n

V-

.b

~

-

v-

SUGGESTED COMPENSATION FOR UNITY GAIN STABILITY
INVERTING

NON-INVERTING

l~r~

IN~T

'Y

INPUT

....
'"

-J4

_A

~O:PF!

1.2Kn·

~

+

30~F.*

10Kn

900n·

OUTPUT

J4

HA-46

-

.

OUTPUT

-

1">

H~

A-462

10Kn
_A .A

+

"","

•
,>10Kn

• VALUES WERE DETERMINED
EXPERIMENTALLY FOR
OPTIMUM SPEED AND
SETTLING TIME
•• OPTIONAL

-=

LARGE SIGNAL RESPONSE
~\

1\

INPUT A

OV

1\ n

OUTPUT B

INPUT A

(1

OV

OV

'"

OUTPUT B

1/
VOLTS:

Input A:

I\.

v

OV

5V/Div., Output B: 2V/Div.

TIME: 1 J.ls/Div.

2-83

m

H.ARRiS

HA-4741
Quad Operational Amplifier

FEATURES
•
•
•
•
•
•
•
•

•

DESCRIPTION

SLEW RATE
BANDWIDTH
INPUT VOLTAGE NOISE
INPUT OFFSET VOLTAGE
INPUT BIAS CURRENT
SUPPLY RANGE
NO CROSSOVER DISTORTION
STANDARD QUAD PIN-OUT

1.6V//ls (TYP.)
3.5M Hz (TYP.)
9nVVHZ (TYP.)
O.5mV (TYP.)
60nA (TYP.)
±2VTO±20V

APPlICA TlONS
• UNIVERSAL ACTIVE FILTERS
• 03 COMMUNICATIONS FILTERS

The HA-4741. which contains four amplifiers on a monolithic
chip, provides a new measure of performance for general purpose
operational amplifiers. Each amplifier in the HA-4741 has
operating specifications that equal or exceed those of the 741type amplifier in all categories of performance.
HA-4741 is well suited to applications requiring accurate signal
. processing by virtue of its low values of input offset voltage
(O.5mV), input bias current (60nA) and input voltage noise
(9nV/ {Hi at 1kHz). 3.5MHz bandwidth, coupled with high
open-loop gain, allow the HA-4741 to be used in designs requiring amplification of wide band signals, such as audio amplifiers.
Audio application is further enhanced by the HA-4741's negligible output crossover distortion. These excellent dynamic
characteristics also make the HA-4741 ideal for a wide range of
active filter designs. Performance integrity of multi-channel
designs is assured by a high level of amplifier-to-amplifier
isolation (lOadB at 1kHz).
A wide range of supply voltages (±2V to ±20V) can be used to
power the HA-4741, making it compatible with almost any
system including battery-powered equipment

• AUDIO AMPLIFIERS
• BATTERY-POWERED EQUIPMENT

The HA-4741 has guaranteed operation Qver -55 0 C to +125 0 C
and can be furnished to meet MIL-STD-883 (HA-4741-8).
The HA-4741-5 is guaranteed over OOC to +75 0 C and is available in ceramic and plastic dual-in-line packages and in dice
form.

PINOUT

SCHEMATIC
Section 11 for Packaging

TOP VIEW
Out
1

~-"""'--'Out

4

Inputs

Inputs

1

4

vInputs
3

Out
3

QUAD OPAMP
(%) HA-4741

2-84

SPECIFICA TIONS
ABSOLUTE MAXIMUM RATINGS
TA = +25 0C Unless Otherwise Stated
Voltage Between V+ and V- Terminals
Differential Input Voltage
Input Voltage (Note I)
Output Short Circuit Duration (Note 2)

40.0V
±30.0V
±15.0V
Indefinite

Power 0 issipation For
Epoxy Package. (Note 3)
Operating Temperature Range
HA·4741-2
HA-4741-5
Storage Temperature Range

880mW
-550C:STA~+1250C
OOC:STA~+750C

-650C:STA~+1500C

ELECTRICAL CHARACTERISTICS

PARAMETER
INPUT CHARACTERISTICS
Offset Voltage
Av. Offset Voltage Drift
Bias Current
Offset Current
Common Mode Range
Differential Input Resistance
Input Noise Voltage (t = 1KHz)
TRANSFER CHARACTERISTICS
Large Signal Voltage Gain (Note 4)

TEMP.

+25 0 C
Full
Full
+25 0 C
Full
+25 0 C
Full
Full
+25 0 C
+25 0 C

MIN.

MAX.

0_5

3.0
5.0

15

MIN.

TYP.

MAX.

UNITS

1.0
5.0
5
60

5.0
6.5

mV
mV
/lV/OC
nA
nA
nA
nA
V
Mn
nV/jHz

200
325
30
75

± 12

30

Channel Separation (Note 5)
Small Signal Bandwidth
OUTPUT CHARACTERISTICS
Output Voltage Swing (RL = 10K)
(RL = 2K)
Full Power Bandwidth (Notes 4 & 9)
Output Current (Note 6)
Output Resistance

Full
Full
+25 0 C
Full
+25 0 C

TRANSIENT RESPONSE (Notes 7 & 10)
Ri •• Time (Not. 11)
Overshoot (Note ttl
Slew Rate (Note 12)

+250 C
+25 0 C
+25 0 C

POWER SUPPLY CHARACTERISTICS
Supply Current
Power Supply R.je.tion Ratio (Note 8)

+25 0 C
Full

300
400
50
100

tl2

5
9

50K
25K
80
74
90
2.5

NOTES:

TYP.

4.0
5
60

+25 0 C
Full
+25 0 C
Full
+25 0 C
+25 0 C

Common Mode Rejection Ratio (Note 8)

HA-4741·5
OOC to +75 0 C

HA·4741·2
-55 0 C to +125 0 C

V+= 15V, V- =-15V

5
9

lOOK

-108
3.5

25K
15K
80
74
90
2.5

-108
3.5

tl2

t13.7

tl2

t13.7

tlO

t12.5

tlO

t12.5

14

25
±15
300

14

25

t5

tl5

t5

75
25

50K

75
25

V
V
kHz
mA
n

140
40

tt.6

t1.6

ns
%

V//ls

7.0

5.0
80

V/V
V/V
dB
dB
dB
MHz

300

140
40

80

mA
dB

1. For supply voltages less than ± 15V. the absolute
maximum Input voltage Is equal to the supply
voltage.

8. Av =±5.0V
9. Full power bandwIdth guaranteed based upon

2. One amplifier may be shorted to ground Indefinitely.
3. Derate 5.8mW/oC above T A = +250 C.

10.RL = 2K, CL = 50pf.

4. VOUT =.:!:"lo, RL = 2K
5. Referred to Input; f = 10KHz, RS = 1 K
6. V OUT =±10

•

7. See pu Ise response characteristics

slew rate measurement FPBW = S.R.l2TTVpeak
11.VOUT =±20'OmV
12. VOUT = ± 5V

2-85

PERFORMANCE CURVES
V+ =+15V, V- = -15V, TA =+250 C
Unless Otherwise Stated.

OPEN LOOP FREQUENCY RESPONSE
+11 0

IIII! II
I~~I~ 2~t

..

+100
0

Cl "'50pF

+80

GAIN

+70

'N..

+6 0

II

+50

PHASE

+4 0

•

(VOLTAGE fOLLOWERI
fl L .. OPEN
1-4-.J.+j.~I--+-I+Il+lll
Cl-SOpF

1 r-~

+30
t 35'

+20
+1 0

180'

0

·1 0
10

lK
10K
FREQUENCY - Hz

100

1M

lOOK

10M

100

,

,.

lOOK

10K

FREQUENCY - HI

BANDWlD~

1

/

•

SLEW RATE
BANDWIDTH

,

10

/

•

-

V

./

,....

r- r,;;....

B NOWI

SLEW RATE

"

I

.

7

•1

"

'!IO
SUPPLY VOLTAGE

!15V

'!20

..

·55

,

1

1

.+50

.+15

"

N01SEVOlTAGE

I~~

04 ~

f'.-..

D2

NOISEC RRENT

,

o
10K

10'
FREQUENCY-HI

+125

.10'

o·

7

11111

f-i'-

RL ~ 21(.

r

ITTilIT

0

~~~~ MARGIN

,

0'

,'f\

~

+25

SMALL SIGNAL BANDWIDTH AND PHASE
MARGIN VS. LOAD CAPACITANCE

,

,

·25

TEMPERATURE _ Ie

INPUT NOISE VS. FREQUENCY

2-86

I"""

1.2

1

10

1111

1111111

NORMALIZED AC PARAMETERS
VS. TEMPERATURE

NORMALIZED AC PARAMETERS
VS. SUPPLY VOLTAGE

,
,
,

1111

lOOK

"
"
"
"

BANDWIDTH

•
,

~

1\

2

r--..

1

,

0'
10

10'

100'
lOADCAi'AC1TANCE _pf

10,DOO

100,000

PERFORMANCE CURVES (Continued)
MAXIMUM OUTPUT VOLTAGE
SWING VS. LOAD RESISTANCE

CHANNEL SEPARATION VS. FREUUENCY
30

r---HrH+tttt-+-H1'tttttti--ft-"",J-.±++ttttt---if-+++I-tttI

25

"'::~ ~,', ,.:+ttl+ttt-I'--t-H+tttlj

20

"II'

: Ij,,1111111

CS.20l0G(~)
IDDVOI

I

•6a

r--

::~ ~'0I1
,

-.'1

I

III

15

10/

++++H-H--++++++H-I

I111

III

I

'0

/'

5

1111

100

II<

10K

lOOK

0

FREQUENCY-HI

100

lK

10K

lOOK

LOAD RESISTANCE - OHMS

INPUT BIAS AND OFFSET CURRENT
VS. TEMPERATURE

•

POWER CONSUMPTION
VS. TEMPERATURE

'00
"r-+--r~--t-~-t~--t--+~--t-~-t~--1

'"

'"

"
20

::-+---==:-!::::=:!::-j---l--l--+--~

r--+--+-ji'---.p......
_~UR"i'

,~P=!=trt:ttt~
4
-250

+25

+50

+75

+100

+125

40

---

VS·!15V

VS"!IDV

-

,
-50

TEMPERATURE·oC

-

Vs·.±sv

-25

,

.25

.5O

TEMPERATURE·at

."

+100

+125

PULSE RESPONSE
TRANSIENT RESPONSE/SLEW
RATE CIRCUIT

,? y
+

1
50 F
P

SLEW"RESPONSE

TRANSIENT RESPONSE

(Volts: 5v/Div. Time: 5/.!S/Div)

(Volts: 40rilV/Div.• Time: 100ns/Div.)

...
-5V H-t--t-+--1H-t-+--H
VOUT

2Kn

+5VH-+---17-+-+-+-I<-\.++-i

VIN IT

-=

-

":"

I
I

-5V H-f-V+-+--J-+-+-.p.....j-l

2-87

m

H.ARRIS

HA-4900/02/05
Precision Quad Comparator

FEATURES

DESCRIPTION

• FAST RESPONSE TIME

130ns

• LOW OFFSET VOLTAGE

2.0mV

• LOW OFFSET CURRENT

10nA

• SINGLE OR DUAL-VOLTAGE SUPPLY
OPERATIDN

•

• SELECTABLE OUTPUT LOGIC LEVELS
• ACTIVE PULL-UP/PULL-DDWN OUTPUT
CIRCUIT - NO EXTERNAL RESISTORS
REQUIRED

.APPlICA TIONS

• THRESHOLD DETECTOR

The HA-4900 series are monolithic, quad, precision comparators offering fast response time, low offset voltage, low
offset current, and virtually no channel-to-channel crosstalk
for applications requiring accurate, high speed, signal level
de1ection. These comparators can sense signals at ground
level while being operated from either a single +5 volt supply
(digital systems) or from dual supplies (analog networks) up
to t15 volts. The HA-4900 series contains a unique current
driven output stage which can be connected to logic system
supplies (VLogic+ and VLogid to make the output levels
directly compatible (no external components needed) with
any standard logic or special system logic levels. In combination analog/digital systems, the design employed in the
HA-4900 series input and output stages prevents troublesome ground coupling of signals between analog and digital
portions of the system.
These comparators' combination of features makes them
ideal components for signal detection and processing in data
acquisition systems, test equipment, and microprocessor/
analog signal interface networks.

• ZERO-CROSSING DETECTOR
• WINDOW DETECTOR
• ANALOG INTERFACES FOR MICROPROCESSORS

All devices are available in 16 pin dual-in-line ceramic packages. The HA-4900/4902-2 operates from -55 0 C to +125 0 C
and the HA-4905-5 operates over a DoC to +75 0 C.tempoerature range.

• HIGH STABILITY OSCILLATORS
• LOGIC SYSTEM INTERFACES

SCHEMATIC

PINOUT
Section 11 for Packaging

Top View
VLOGlC(+)

16

2

15

3

14

4

V+ 13

5

V-

12

6

11

7

10

8

VLOGIC(-) 9
ONE FOURTH ONLY (HA-4900 SERIES)

2-88

SPECIFICA TIONS
ABSOLUTE MAXIMUM RATINGS (Note 1)
Voltage Between V+ and V-

33V
18V
±15V
±50mA

Voltage Between VLogic(+) and VLogic{-)
Differential Input Voltage
Peak Output Current
Internal Power Dissipation (Note 7, 8)
Storage Temperature Range

ELECTRICAL CHARACTERISTICS

PARAMETER
, INPUT CHARACTERISTICS
Offset Voltage (Note 2)
Offset Current
Bias Current (Note 3)
Input Sensitivity (Note 4)
Common Mode Range

TEMP

V+ =+15.0V, V-=-15.0V, VLogic!+) = 5.0V, VLogicH = GND.

HA-4900-2
-550C to +125 0C
TYP
MAX
MIN

HA-4902-2
-550C to +125 0C
TYP
MIN
MAX

2

3
4

2

10

25
35

10

50

75
150

50

25 0C
Full
25 0C
Full
25 0C
Full
25 0C
Full
Full

880mW
-65 0 C ~ TA ~ 150 0 C

Vio+.3
Vio+.4
V+ -2.4

V-

V-

HA-4905-5
OOC to +750C
TYP

MAX

UNITS

5
8

4

7.5
10

mV
mV

35
35
150
200
Vio+.5
Vio+.6

25

50
70

100

150
300
Vio+.5
Vio +.7

nA
nA
nA
nA
mV
mV

V++2.4

V

V++2.4

MIN

V-

II

TRANSFER CHARACTERISTICS
Large Signal Voltage Gain
Response Time (T pdO) (Note 5)

25 0C
25 0C

Response Time (T pdll (Note 5)
OUTPUT CHARACTERISITICS
Output Voltage Level
Logic "Low State" (VoLl (Note 6)
Logic "High State" (VOH) (Note 6)

25 0C

Full
Full

3.5

Full
Full

3.0

400K

400K

400K
130
180

200

0.2
4.2

0.4

215

3.5

130
180

200
215

0.2
4.2

0.4

130
180

3.5

0.2
4.2

200
215

0.4

V/V
ns
ns

V
V

Output Current
ISink
ISource
POWER SUPPLY CHARACTERISTICS
Supply Current, Ips (+)
Supply Current, Ips (-)
Supply Current, Ips (Logic)

3.0

25 0C
25 0C
25 0C

3.0

3.0
3.0

rnA
rnA

3.0

6.5

20

6.5

20

7

20

rnA

4

8

4

5

4

2.0

8
4

rnA

2.0

8
4

+15.0

V

0

V

2.0

rnA

Supply Voltage Range
VLogic (+) (Note 71

Full

0

+15.0

0

+15.0

VLogic (-I (Note 71

Full

-15.0

0

-15.0

0

0
-15.0

2-89

NOTES:
1.

2.

•

ency ~ 100Hz; Duty Cycle
driven. See Test Circuit below.

~

Absolute maximum ratings are limiting values, applied
individually, beyond which the serviceability of the
circuit may' be impaired. Functional operability under
any of these conditions is not necessarily implied.

6.

For VOH and VOL: ISink = ISource = 3.0mA. For
other values of VLogic; VOH (min.) =VLogic' + -1.SV.

Minimum differential input voltage required to ensure
a defined ou tput state.

7.

Total Power Dissipation (T.P.D.) is the sum of individual dissipation contributions of V+, V- and VLogic
shown in curves of Power Dissipation vs. Supply Voltages (see Performance Curves). The calculated T.P.D.
is then located on the graph of Maximum Allowable
Package Dissipation vs. Ambient Temperature to determine ambient temperature operating limits imposed by
the calculated T.P.D. (See Performance Curves). For
instance, the combination of +15V, -lSV, +5V, OV
(V+, V-, VLogic+, VLogic-) gives a T.P.D. of 350mW
which allows operation to +12S oC; the combination
+lSV, -lSV, OV gives a T.P.D. of 450roW and an
operating limit of TA =+9S oC.

8.

Derate by 5.8mW/oC above TA = +75 0 C.

3.

Input bias currents are essentially constant with differential input voltages up to ±9 volts. With differential
input voltages from ±9 to ±15 volts, bias current on
the more negative input can rise to approximately
500 J.I A.

4.

RS ~ 200 ohms; VIN ~ Common Mode Range. Input
sensitivity is the worst case minimum differential input
voltage required to guarantee a given output logic state.
This parameter inludes the effects of offset voltage,
offset current, common mode rejection, and voltage
gain.

S,

For Tpd(1); 100mV input step, -SmV overdrive. For
Tpd(O); -100mV input step, 5mV overdrive. Freq-

SO%; Inverting input

RESPONSE TIME TEST CIRCUITS
+15V

>---oVOUT

OVERDRI~r-_ _ _ _ __

INPUT

- .-: - "7'" -

T

IOOmV

-

VTH = OV

f ~
-.L
IOOmV

-----:--VTH=OV

T

OVERDRIVE

OUTPUT
T=O

For input and output voltage waveforms for various input overdrives see Performance Curves.

2-90

PERFORMANCE CURVES
V+ = 15V, V- = -15V, V Logic(+) = 5.0V, VLogic(-) = OV, TA = +25 0 C, Unless Otherwise Stated.

INPUT BIAS CURRENT vs. TEMPERATURE

INPUT OFFSET CURRENT VS. TEMPERATURE

100

0

0

....

---

~I-.

0

0

5

0

5

-

~

/

~

J
0

·55

·25

50

25

75

100

125

0

·55

·25

25

TEMPERATURE,IOC}

50

75

125

100

•

TEMPERATURE, (OCI

INPUT BIAS CURRENT vs. COMMON MODE INPUT VOLTAGE
(VDIFF. = OV)
0

'-..............

0

...............

.........

0

\

0

0
15

12

oS

·3

12

15

COMMON MODE INPUT VOLTAGE

SUPPLY CURRENT-vs. TEMPERATURE

SUPPL Y CURRENT vs. TEMPERATURE
FOR SINGLE +5V OPERATION

FOR ±15V SUPPLIES AND +5V LOGIC SUPPLY

V+"'5.0'l
VLOGIC(+)- 5.OV

v- .. "LOGICr-) .. GND
2

0

V·"15.DY
VLOGICI+)" 5.0Y

VOUy" L

YlOGlCI-)" GND

~'g~T'"

""""""-

V+=15.0'l
'ps'

---.: .......

5

B

-r-

/'

'PS'

4

VOUT=H

'PS-

VOUy"L

o.r-

'PS'

,/

VOUT~l

3

'-

~
IpsL

/'
IpS"OUT" H

VOUT-L
2

IpSL
vO"T·L ......

1

'psL
,/
VOUT'" H

0
·50

·25

25
TEMPERATURE,IOC}

50

-........

'PS'

vou,· H

~

75

100

125

50

25

50
25
TEMPERATURE. lOCI

75

100

125

2-91

PERFORMANCE CURVES

(continued)
RESPONSE TIME FOR VARIOUS INPUT OVERORIVES

,~

i\'

Your
VOLTS

j...-0VERORIVE = 20~V

V

:::.~-t--t--I

VOUT
VOLTS

\ l\"

'I-+-+--+~
{11j-+-+-+-+--+--i
+ TOO
mV

VIN

\l
I--I--If-+---+-+--+-+--+-t--i

VIN

-1O'1--I--iI-+-t-+--+-t--+-j--;
10.
300
20.
40.
mV

100

llMEns

•

'00

300

40.

llMEns

MAXIMUM POWER DISSIPATION vs. SUPPLY VOLTAGE
(NO LOAD CONDITION)
MAXIMUM PACKAGE DISSIPATION
vs. TAMBIENT

~
;r

20. I--+-+-+-+-+-+--+-I-t-+-+-+--t---i>''-i

BO. F=F::j=:=+=:::r;:~~=::!===1F~IITTTI
~ ~AXIMUM ALLOWABLE PACKAGE--+----1r-~-f"....r-+--t----11-i

SOD

DISSIPATION (SEE NOTE 1)

~

~ .oor-+-+--r-+-+-+-I~I-t-+-+-~~-+--i

i 300r-+-+--r-+-+-+-I~r-r-+-+-+-~~1-~

c;
~ 200 ~+-+-+-+-+-+-I~f-r-+-+-+--t--+--i

::~

10. r-+-+--r-r-+-+-I-Ir-r-+-+-+--r-r--i
25

50
15
AMBIENT TEMPERATURE, ac

100

10
SUPPLY VOL TAGE.IVOlTS)

125

12

14

APPLYING THE HA-4900 SERIES COMPARATORS
1.

2-92

SUPPL Y CONNECTIONS: This device is exceptionally
versatile in working with most available power supplies.
The voltage applied to the V+ and V- terminals determines
the allowable input signal range; while the voltage applied
to the VL+ and VL - determines the output swing. In
systems where dual analog supplies are available, these
would be connected to V+ and V-, while the logic supply
and return would be connected to VLogic+ and VLogic-.
The analog and logic supply commons can be connected
together at one point in the system, since the comparator
is immune to noise on the logic supply ground. A negative
output swing may be obtained by connecting VL+ to
ground and VL- to a negative supply. Bipolar output
swings (15V P-P, max.) may be obtained using dual supplies. In systems where only a single logic supply is available (+5V to +15V), V+ and VLogic+ may be connected
together to the positive supply while V- and VLogicare grounded. If an input signal could swing negative with
respect the V- terminal, a resistor should be connected in
series with the input to limit input current to < 5mA
since the C-B junction of the input transistor would be
forward biased.

2.

UNUSED INPUTS: Inputs of unused comparator sections
should be tied to a differential voltage source to prevent
output "chatter".

3.

CROSSTALK: Simultaneous high frequency operation of
all other channels in the package will not affect the output
logic state of a given channel, provided that its differential
input voltage is sufficient to define a given logic state
(L1VIN ~±VOSl. Low level or high impedance input lines
should be shielded from other signal sources to reduce
crosstalk and interference.

4.

POWER SUPPLY OECOUPLlNG: Decouple all power
supply lines with .01 IJ. F ceramic capacitors to a ground
line located near the package to reduce coupling between
channneis or from external sources.

5.

RESPONSE TIME: Fast rise time « 200ns) input pulses
of several volts amplitude may result in delay times somewhat longer than those illustrated for 100mV steps. Operating speed is optimized by limiting the maximum differential input voltage applied, with resistor-diode clamping
networks.

APPLICATIONS

r-------- - - --.,

r----------,

I

I
I

I

I

DIA

I

I

I

ANALOG
INPUTS
COMPARATORS

--

IN TERFACE

,

MEMORY

i'
I

I
I
I
I

I
I

L _______ ... ___ .J

I

I

INTERFACE

MICROPROCESSOR

I
L
_________ __ J

ANALOG INPUT MODULE

PROCESSOR

DATA ACQUISITION SYSTEM

In this circuit the HA-4900 series is used in conjunction with a 0 to A converter to form a simple, versatile, multi-channel analog
input for a data acquisition system. In operation the processor first sends an address to the 0 to A, then the processor reads
the digital word generated by the comparator outputs.
To perform a simple comparison, the processor sets the 0 to A to a given reference level, then examines one or more comparator
outputs to determine if their inputs are above or below the reference. A window comparison consists of two such cycles with
2 reference levels set by the 0 to A. One way to digitize the inputs would be for the processor to increment the 0 to A in steps.
The 0 to A address, as each comparator switches, is the digitized level of the input. While stairstepping the 0 to A is slower than
successive approximation, all channels are digitized during one staircase ramp.

+5.0V

TTL TO CMOS

CMOS TO TTL

LOGIC LEVEL TRANSLATORS

The HA-4900 series comparators can be used as versatile logic interface devices as shown in the circuits
above. Negative logic devices may also be interfaced with appropriate supply connections.
If separate supplies are used for V- and VLogic-, these logic level translators will tolerate several volts of
ground line differential noise.

2-93

APPLICA TIO/J$

(continued)

INPUT

HI REF

>!-e-----O

0--++---1

HI

vcc

4.7K
3W

lK
56K

51K

LO REF o--+-I-~
'>;~---~:>LO

lK

WINDOW DETECTOR
RS-232 TO CMOS LINE RECEIVER

•

This RS-232 type line receiver to drive CMOS logic uses a
Schmitt trigger feedback network to give about 1 volt input
hysteresis for added noise immunity. A possible problem in
an interface which connects two equipments, each plugged
into a different AC receptacle, is that the power line voltage
may appear at the receiver input when the interface connection is made or broken. The two diodes and a 3 watt input
resistor will protect the inputs under these conditions.

The high switching speed, low offset current and low offset
voltage of the HA-4900 series makes this window detector
circuit extremely well suited to applications requiring fast,
accurate, decision-making. The circuit above is ideal for
industr.ial process system feedback controllers. or "outof-limit" alarm indicators.

+15V

i > - - _ - o VOH",4.2V
R2'

2K

v+

-15V

Rl

R3

lOon

13K

-15V

SCHMITT TRIGGER (ZERO CROSSING
DETECTOR WITH HYSTERESIS)
50K

OSCILLATOR/CLOCK GENERATOR

This self-starting fixed -frequency oscillator circuit gives
excellent frequency stability. Rl and Cl comprise the
frequancy determining network while R2 provides the
regenerative feedback. Diode D1 enhances the stability by
compensating for the difference between VOH and VSuppl y.
In applications where a precision clock generator up to
100kH,z is required, such as in automatic test equipment,
C1 may be replaced by a crystal.

This circuit has a 100mV hysteresis which can be used in
applications where very fast transition times are required
at the output even though the signal input is very slow.
The hysteresis loop also'reduces false 'triggering due to noise
on the input. The waveforms below show the trip points
developed by the hysteresis loop.
VOH

w--~----

______

Input to Output Waveform
Showing Hysteresis Trip Points

2-94

~L-

__________

~L-

mHA.RRIS

HA-5062 Series
low Power JFET Input
Dual Operational Amplifiers

Preliminary
FEATURES

DESCRIPTION

•
•
•
•

HIGH INPUT iMPEDANCE
LOW INPUT BIAS CURRENT
LOWINPUTOFFSETCURRENT
VERY LOW POWER CONSUMPTION
TYPICAL SUPPLY CURRENT
• INTERNAL FREQUENCY COMPENSATION
• HIGH SLEW RATE
• PIN COMPATIBLE WITH LMI458
• DIRECT REPLACEMENT FOR TL062

lol2n
200pA
IOOpA
200~A

4V!ps

APPLICATIONS
•
•
•
•

ACTIVE FILTERS
INSTRUMENTATION AMPLIFIERS
AUDIO AMPLIFIERS
BATTERY OPERATED EQUIPMENT

•

SIGNAL CONDITIONING

The HARRIS HA-5062 operational amplifiers are a series
of dual monolithic JFET-input amplifiers featuring low
input bias and offset currents, high input impedence and
very low power operation. In addition to being a direct
replacement for the TL062 series, the HA-5062 series
offers improved performance with a minimum open loop
gain 20K VIV and a slew rate of 4v/J-ls.
This improved performance is a result of the HAR RIS
FET/Bipolar technology and makes the HA-5062 series
of amplifiers ideally suited for applications in industrial
control, communication, and battery powered instrumentation equipment.
The HA-5062-2 is characterized for operation over the
full military temperature range of -55 0 C to +125 0 C.
The HA-5062A-5, HA-5062B-5 and HA-5062-5 are
all characterized over the commercial temperature range
of OOC to +75 0 C.

SIMPLIFIED SCHEMATIC

PINOUT
v+

Section 11 for Packaging

-IN

NOTE: Case Connected to v-

II

v-

OUT

TOP VIEWS

(ONE HALF ONL YI

2-95

SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS (Note 1)
Voltage Between V+ and V- Terminals
Differential Input Voltage
Input Voltage (Note 2)
Output Short Circuit Duration

Power Dissipation
BOOmW*
Operating Temperature' Range:
HA-50B2-2
-550C~TA~+1250C
HA-5062-5
OOC~T A~+ 750C
-B50C~TA~1500C
Storage Temperature Range
* To-99 Derate by 6.75mW/oC above +850C
Dip Derate by 5.57mW/oC above +650C

± 20V
±40V
±15.0V
Indefinite

ELECTRICAL CHARACTERISTICS
V+= 15V V-= 15V
Parameters are guaranteed at indicated
ambient temperature after warm-up.
PARAMETER
INPUT CHARACTERISTICS
Offset Voltage (Note 3)
Av. Offset Voltage Drift
Bias Current

11

Offset Current

HA-5062-2
-55 0 C to +125 0 C
TEMP. MIN. TYP. MAX.

+25 0 C
Full
Full
+25 0 C
Full
+25 0 C
Full
Full ±10
+25 0 C

3

HA-5062B-5
HA-5062A-5
HA-5062-5
OOC to 75 0 C
OOC to +75 0 C
OOC to 75 0 C
MIN. TYP. MAX. MIN. TYP. MAX. MIN. TYP. MAX. UNITS

3

6
9

10
30
5

10
30

200
50
100
20

5

6
7.5

2
10
30

200
7
100

5

3

3
5

3
10
30

200
7
100
3

5

±12
10 12

±10

:t12
10 12

±10

:!:12
10 12

:!:10

±12
10 12

+25 0 C 20K
Full 10K
Full
80

25K

20K
15K
80

25K

20K
15K
80

25K

10K
5K
70

25K

t12

±IO
±.10

±12

±10
±.10

±.12

±10
.±10

±.12

Unity Gain Bandwidth (Note 6)
Full Power Bandwidth (Note 7)

+25 0 C ±10
Full ±10
+25 0 C
+25 0 C

TRANSIENT RESPONSE
Rise Time (Note 8)
Overshoot (Note 8)
Slew Rate (NQte 9)
Settling Time (Note 10)

+25 0 C
+25 0 C
+25 0 C
+25 0 C

POWER SUPPLY CHARACTERISTICS
Supply Current (Nato 11)
Power Supply Rejection Ratio (Note 12)

+25 0 C
Full

Common Mode Range
Input Resistance
TRANSFER CHARACTERISTICS
Large Signal Voltage Gain (Note 4)
Common Mode Rejection Ratio (Note 5)

OUTPUT CHARACTERISTICS
Output Voltage Swing INote 6)

86

86

1
63

1
63

I
63

80
10

80
10

4

4

3.5

3.5

80
10
4
3.5

80
10
4
3.5

95

0.4
80

95

0.4
80

95

400
10
200
5

V
V
MHz
KHz
nsec
%

V/jJ.s
JJ sec
0.5

70

95

mV
mV
/J.V/oC
pA
nA
pA
nA
V
Mn

V/V
V/V
dB

76

1
63

0.4
80

86

15
20

rnA
dB

NDTES:

2-96

7.

RL =10K; Full power bandwidth guaranteed based on
.
SLEW RATE
slew rate measurement uSing FPBW = 27TVPEAK

9.

VIN = IOV, CL = 50pF, RL = 10Kn.

I.

Absolute maximum ratings are limiting values, applied
individually, beyond which the serviceability of the
circuit may be impaired. Functional operability
under any of these conditions is not necessarily implied.

2.

For supply voltages less than ±15V, the absolute maximum input voltage is equal to the supply voltage.

3.

RS = 50n.

4.

RL~10Kn, VO=±10V.

5.

~ VIN = :!:10V.

11. No load, No signal.

6.

RL = IOKfl.

12. VSUPP =±5V.D.C. to ±15 V.D.C.

10. Settling time is measured to 0.1% of final value for a
10 volt outputstep and AV = -1.

;m~RIS
Preliminary
FEATURES

HA-5064 Series
low Power, JFET Input
Quad Operational Amplifiers
DESCRIPTION

100pA

• LOW INPUT BIAS CURRENT

24mW/Pkg.

• LOW POWER OISSIPATION

4V/ps

• FAST SLEWING

10pV/OC

• LOW VIO ORIFT

The HAR RIS HA-5064 series JFET input monolithic, quad
operational amplifiers feature very low power requirements
coupled with excellent AC and DC characteristics. Maximum
power dissipation of 24 mW/package is achieved by using complementary design, process, and layout techniques.

fa

1012S?

• HIGH INPUT IMPEDANCE

120dB

• GOOD CHANNEL SEPARATION

±5V TO ±20V

• POWER SUPPLY RANGE

APPlICA TIONS
WHERE DENSITY AND POWER REQUIREMENTS
ARE DEMANDING:
• ACTIVE FILTERS
• SIGNAL CONDITIONING

A 4V/ps slew rate coupled with lMHz gain-bandwidth makes
these devices most suitable for active filter and signal conditioning
designs. The HA-5064 series is ideally suited for those applications demanding low power and high density without compromising other performance characteristics. High input impedance
and low drift also makes the HA-5064 series useful as instrumentation amplifiers.
The HA-5064 is packaged in a 14-pin DIP and is pin compatible
with most other quad operational amplifiers. The HA-5064-2
is specified for -55 0 C to +125 0 C operation while the HA-5064
A-5/HA-50B4B-5/HA-5064-5 are specified over the DoC to
+75 0 C range.

• SIGNAL GENERATION
• INSTRUMENTATION AMPLIFIERS

PINOUT

SIMPLIFIED SCHEMATIC
Section 11 for Packaging

TOP VIEW
OUT
1

2
INPUTS
3
1
4
V+
5
INPUTS
6
2
OUT
2

7

14 OUT
4
-IN

OUT

INPUTS
12
4
11

V-

10
9

INPUTS
3

8 OUT
3
ONE-FOURTH ONLY

2-97

SPECIFICA TlONS .
ABSOLUTE MAXIMUM RATINGS
40V

Voltage Between V+ and V-

:t30V

Differential Input Voltage (Note 2)

Continuous

Output Current (Note 3)

500mW

Internal Power Dissipation (Note 4)

-65 0 C to +150 oC

Storage Temperature Range

ELECTRICAL CHARACTERISTICS
V+ = 15VOC; V- = -15VOC
HA-5064-2
-55 0 C to +1250 C

•

PARAMETER

TEMP

MIN TYP

MAX

HA-5064A-5
OOC to +750 C
MIN TYP

MAX

HA-50S4-5
OOC to +75 0 C

HA-5064B-5
OOC to +75 0 C
MIN

TYP

MAX

2

3
5

MIN

TYP

MAX

UNITS

15
20

mV
mV
/JV/oC
pA
nA
pA
nA

INPUT CHARACTERISTICS
Offset Voltage
Offset Voltage Average Drift
Bias Current
Offset Current
Input Resistance

Common Mode Range

+25 0 C
2
Full
Full
10
+250 C
Full
+25 0 C
Full
+25 OC
10 12
Full
:!:10

2

6
9

6
7.5·

10
200
50
100
20

20

10
200
7
100
3

400
10
200
5

200
7
100
3

10 12

10 12

10 12

:!:10

:!:10

20K 25K
15K
80
1
120

20K
15K
SO

±10 ±12
:!:10
:!:1
63
300

±10
:!:10
:!:1

:!:10

n
V

TRANSFER CHARACTERISTICS
Large Signal Voltage Gain (Note 5)
Common Mode Reiection Ratio (Note 6)
Gain Bandwidth
Channel Separation (Note 7)

+25 0 C 20K
Full
10K
Full
80
+25 0 C
+25 0 C

25K

+25 0 C tlO
Full
:!:IO
Full
!1
+250 C
+25 0 C

±12

63
300

+25 0C
+250C
+250C

80
4
3.5

1
120

10K

25K

25K

V/V
V/V
dB
MHz
dB

5K

70
1
120

1
120

OUTPUT CHARACTERISTICS
Output Voltage Swing (Note S)
Output Current (Note 9)
Full Power Bandwidth (Note 10)
Output Resistance (Note 11)

tlO
:!:IO
:!:1

t12

63
300

;t12

V
V
rnA
kHz

63
300

I

n

TRANSIENT RESPONSE (Note 12)
Rise Time 110% TO 90%)
Slew Rate
Settling Time (Note 13)

2

eo
2

4
3.5

2

i

SO
4
3.5

2
,

nsec

80
4
3.5

VllJ.sec
/Jsec

POWER SUPPLY CHARACTERISTICS
Supply Current
P. S. R. R. (Note 14)

2-98

+25 0C
Full

.8

SO

1

.S

.8

SO

80

70

rnA
dB

NOTES
1.

2.

Absolute maximum ratings are limiting values, applied
individually, beyond which tHe serviceability of the circuit
may be impaired. Functional operability under any of
these conditions is not necessarily implied.

200m V peak-to-peak; RS = 10Kn

For supply voltages less than :t15V, the absolute maximum
input voltage is equal to the supply voltage.

8.

RL = 2K ohms.

9.

Output current is measured with VOUT = 10 volts.

10.

RL = 10K; Full power bandwidth guaranteed, based on slew
rate measurement using FPBW = SLEW RATE
2TrV PEAK

3.

Anyone amplifier may be shorted to ground indefinitely.

4.

Derate 5.8mW/oC above TA = +25 0 C.

11.

Output resistance measured under open loop conditions.

5.

VOUT=±10V;RL=10Kn

12.

Refer to Test Circuits section 01 the data sheet.

6.

,:WIN =±10V

13.

Settling Time is measured to 0.1% 01 final value lor a 10
volt output step and AV = -1.

7.

Channel separation value is relerred to the input of the
amplifier. Input test conditions are: I = 10kHz; VIN =

14.

VSUPP = +5VDC to +15VDC.

TEST CIRCUITS

II

10K

I

10K

INo----I~

-

IN~

t-'

+
5K

"::'

OUT

INPUT

LARGE SIGNAL
RESPONSE
CIRCUIT
(Volts: 5V /DiY.,
Time: 5ILs/DiY.)

OUTPurn..

OV

I

SMALL SIGNAL
RESPONSE
CIRCUIT
(Volts: 10mV/DiY.,
Time: 50ns/Diy.)

I

-::

!lUTPUI

/

\

I

-INPUT

\

-

,",v

lI--1.-I+--+-4'---+--+--I--+--I

I

II

OV

SETTLING TIME CIRCUIT
+15V

• AV· -1.
•

Feedback and summing

reslrrtors should be 0,1%,

-.o;OKII

• Clipping diodes are optional.
HP5OB2-2810 recommended,

2-99

mHA.RRIS·

HA-50B2 Series
JFET Input
Dual Operational Amplifiers

Preliminary
FEATURES
•
•
•
•

•

DESCRIPTION

HIGH INPUT IMPEDANCE
LDWINPUTBIASCURRENT
LOW INPUT OFFSET CURRENT
LOW POWER CONSUMPTION
TYPICAL SUPPLY CURRENT

• HIGH SLEW RATE
• PIN COMPATIBLE WITH LM1458
• DIRECT REPLACEMENT FOR TL082

lo 12 n
200pA
100pA
3.5mA
15V//J.S

The HARRIS HA-5082 operational amplifiers are a series
of dual monolithic JFET -input amplifiers featuring low
input bias and offset currents, high input impedance
and, high slew rate. In addition to being a direct replacement for the TL082 series, the HA-5082 series offers improved performance with an input offset voltage of 2mV,
a slew rate of 15V / J.ls, and bandwidths of 4M Hz.
This improved performance is a result of the HAR RIS
FET/Bipolar technology and makes the HA-50B2 series
of amplifiers ideally suited for applications in industrial
control, communication, and computer peripheral equipment.

APPlICA TIONS

The HA-5082-2 is characterized for operation over the
full military temperature range of -55 0 C to +125 0C.
The HA-5082A-5, HA-5082B-5 and HA-50B2-5 are all
characterized over the commercial temperature range of
OOC to +750C.

• ACTIVE FILTERS
• INSTRUMENTATION AMPLIFIERS
• AUDIO AMPLIFIERS
• SIGNAL CONDITIONING

PINOUT

SIMPLIFIED SCHEMATIC
V+

Section 11 for Packaging

-IN

OUT

NOTE: Case Connected to v-

TOP VIEWS

(ONE HALF ONLY)

2-100

SPECIFICA TIONS
ABSOLUTE MAXIMUM RATINGS (Note 1)
Voltage Between V+ and V- Terminals
Differential Input Voltage
Input Voltage (Note 2)
Output Short Circuit Duration

Power Dissipation
Operating Temperature Range:
HA-S082-2
HA-S082-S
Storage Temperature Range

±20V
±40V
±15.0V
Indefinite

600mW*
-SSOC-·......_-4~
.......1

-_~

-

:E~?

2N4416

3k

VOUT

• AV"'-1.

• Feedback and summing
resistors should be 0.1%.
• Clipping diodes are optional.
HPS082-2810 recommended.

fIJ~RIS

HA-5100/5105
Wideband, JFET Input
Operational Amplifier

FEATURES

GENERAL DESCRIPTION

•

LOWINPUTOFFSETVOLTAGE ...... 0.5mV

•

LOW OFFSET DRIFT . . . . . . . . . . . . 5p.V/oc

•

LOW INPUT BIAS CURRENT ......... 50pA

o LARGE VOLTAGE GAIN ........ 150K V/V
•

WIDE BANDWIDTH . . . . . . . . . . . . . . 18MHz

•

HIGH SLEW RATE . . . . . . . . . . . . . 8V/p.sec

•

FAST LARGE SIGNAL SETILING TIME: Up.sec

APPlICA TlONS
•

PRECISION, HIGH SPEED, DATA ACQUISITION
SYSTEMS

•

PRECISION SIGNAL GENERATION

•

PULSEAMPLlFIC.ATION

The HA-5100/5105 are monolithic wideband operational amplifiers
manufactured with FET /Bipolar technologies and dielectric isolation.
Precision laser trimming of the input stage complements the amplifier
high frequency capabilities with excellent input characteristics.
The HA-51 00/51 05 offer a number of important advantages over
similar FET input op amps from other manufacturers. In addition to
superior bandwidth and settling characteristics the Harris devices
have quite constant slew rate, bandwidth, and settling characteristics
over the operating range. This provides the user preaictable performance in applications where settling time, full power bandwidth, closed
loop bandwidth, or phase shift is critical. The slewing waveform is
symmetrical to provide reduced distortion. Note also that Harris specifies all parameters at ambient (rather than junction) temperature to
provide the designer meaningful data to predict actual operating performance.

II
I

Complementing HA-5100/5105's predictable and excellent dynamic
characteristics are very low input offset voltage, very low input bias
current, and extremely high input impedance. This ideal combination
of features make these amplifiers most suitable for precision, high
speed, data acquisition system designs and for a wide variety of signal
conditioning applications. *
* -2 denotes a range of -55 0 C to +125 0 C and -5 denotes a OOC to
+75 0 C range.

PINOUT

SCHEMA TIC DIAGRAM
Section 11 for Packaging

TOP VIEW
COMPENSATION

vCASE
CONNECTED
TO V-

2-105

SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS (Note 1)
40V

Voltage Between V+ and V-

±40V

Oifferentiallnput Voltage

Full Short Circuit Protection

Peak Output Current

510mW

Internal Power Dissipation (Note 2)

-650 C to +1500 (:

Storage Temperature Range

ELECTRICAL CHARACTERISTICS

HA-Sl00-2
-5S OC to +1250C

•

PARAMETER

TEMP

MIN

TYP

MAX

0.5
O.SO

HA-5105-5
OOC to +750C

HA-Sl00-S
OOC to +750C
MIN

TYP

MAX

UNITS

1.0
2.0

0.5
0.75

1.5
3.5

mV
mV

TYP

MAX

1.0
2.0

0.5
0.50

MIN

INPUT CHARACTERISTICS
Offset Voltage
Offset Voltage Average Orift

+25 0C
Full
Full

5

Bias Current

+25 0C
Full

20
S

50
10

20

10
50
10

50
10

100
20

/lV/OC
pA
nA

Offset Current

+25 0C
Full

2
2

10
5

2
2

10
5

5
5

50
10

pA
nA

Input Resistance

+250 C

15

1012

Q

Full

±10

±11

±10

±11

tl0

±10.5

V

+25 0 C
Full

75K
60K

150K
lOOK

75K
60K

lS0K
lOOK

50K
40K

lOOK
80K

V/V
V/V

Common Mode Rejecti~n Ratio (Note 4)

Full

80

86

80

86

dB

Full

86
18 ~

80

Gain Bandwidth Product at AV = 10

18

MHz
V
V

Common Mode Range

1012

1012

TRANSFER CHARACTERISTICS
Large Signal Voltage Gain (Note 3)

18

OUTPUT CHARACTERISTICS
Output Voltage Swing (Note 5)
Short Circuit Output Current (Note 6)

+2S oC
Full

±12
±12

±13
±13

±12
±12

±13
±13

±ll
±ll

±12
±12

Full

±10

±15

±1O

t15

±8

±15

mA

Full Power Bandwidth (Note 7)

+25 0 C

90

lS0

90

150

75

125

kHz

Output Resistance (Note 8)

+25 0 C

40

Q

30

30

TRANSIENT RESPONSE (Note 9)
Rise Time

+250 C

Slew Rate

+25 0C

Settling Time (Note 10)

+25 0 C

15
6

35

8

15
6

1.1

35

8

5

1.1

20

nsec

8

V//lsec

2.0

/lsec

POWER SUPPL Y CHARACTERISTICS

\2-106

Supply Current

Full

P.S.R.R. (Note 11)

Full

5
80

86

7

5
80

86

7

6

80

86

8

mA
dB

NOTES:
1.

2.
3.
4.

5.

Absolute maximum ratings are limiting values, applied
individually, beyond which the serviceability of the
circuit may be impaired. Functional operability under
any of these conditions is not necessarily implied.
Derate at 6.B mW!OC for operation at ambient temperatures above +75 0 C.
VOUT =±10V; RL = 2K.
VCM = ±10V D.C.
RL=10K.

6.
7.

VOUT= OV.
RL = 2K; Full power bandwidth guaranteed based on
.
SLEW RATE
slew rate. measurement uSing FPBW = 21TVPEAK'

8.

Output resistance measured under open loop conditions.
Refer to test circuits section of the data sheet.
10. Settling time is measured to 0.1% of final value for a
10 volt output step and AV = -1.
11. VSUpp = ±10V D.C. to i-20V D.C.

9.

TEST CIRCUITS
SLEW RATE AND TRANSIENT RESPONSE TEST CIRCUIT

I

r

@)OUT

LARGE SIGNAL RESPONSE

SMALL SIGNAL RESPONSE

Vertical Scale: (Volts: 5V IOiv.)
Horizonal Scale: (Time: 500ns/Oiv.)

Vertical Scale: (Volts: 100mV/Oiv.)
Horizonal Scale: (Time: 100ns/Oiv.)

OUTPUTB~+-4-~~~~~~~~~--~+-~
~~~~-+-r-r~~~-r-r~OV

lEI

50PF

OUTPUTBr-+--I--Hn~~~.~~~+-~~

1---

INPUT AI-+-t-t-+-:E'-It-+-+-t--IOV

1,..

_a.J

....,

1..oiIIII

5Kr!
AAA.
".,,,

INPUT AI-+-+-I-+-'f'-t-+-+-+--i

SETTLING TIME CIRCUIT
+15V

m~"J

-~H~---(-o:-1
~

TO
OSCILLOSCOPE

2Kn> .
~

..J-

-QVOI,IT
50

:CPF

• AV=-1.
• Feedback and summing
resistors should be 0.1%.
• Clipping diodes are optional.
HP5082-2810 recommended.

2-107

PERFORMANCE ClJRVES
V+ = +15V, V-= -15V, TA = +25OC UNLESS OTHERWISE STATED.

INPUT OFFSET VOLTAGE AND BIAS
CURRENT VS TEMPERATURE

OPEN LOOP FREQUENCY
RESPONSE
+110
+100
+90
ID +80
~ +70

2.0
3K

1.6~,

1:

1.2 ~

I-

iii 2K

OFFSET VOLTAGE

a:
a:
:::t
u

0.8
0.4

~ lK

BIAS CURRENT

iii

~

~

is

9

I-

~

>

z

o IIIII.

o

II.

o

~o

o

-40

+40
+80
TEMPERATURE DC

+120

'\.

!
~

+80
+50
w +40
~ +30
+20

!:io

>

-0.4 0

"........

"'

00
"GAIN
450

""- PHASE

~

"

...

~

0-.

-10
10

1350

"

+10

'-\

o

+160

100

1K

10K

100K

1M

•

110
100
90
ID
80
... z 70
0oc 60

VSUPPLY-±2OV
30
VSUPPLY =± 1SV

r\

it w

'"
"r
W 0

CI I-

I /I" ""

20

.. C 15
Ow

> ...

I!!
..

10

o '

5

I-

:::t

I!: 0
:::t >

o

.........

I 11111111

V~U~LY'=±SV
10K

~~

..

~

--

1/1"""

1K

.. CI

zw

\

vSUPPLY =± 10V

C ..'
I-

11111 111111111

K

11111 111111111
OpF Ildlllll

",

! c 25

1800
100M

OPEN lOOP FREQUENCY RESPONSE FOR
VARIOUS COMPENSATION CAPACITORS

35

CI ~

'"

10M

FREQUENCY - H•

OUTPUT VOLTAGE SWING
VS FREQUENCY

0

>
~

100K

"'"''

50pF

100pF

50

300pF

40

~

30
20
10
0

r-..

~

-,0,0

100

1K

10K

100K

1M

10M

100M

FREQUENCY - Hz

1MEG

FREQUENCY - Hz

INPUT VOLTAGE AND CURRENT
NOISE VS FREQUENCY

~

NORMALIZED AC PARAMETERS
VS TEMPERATURE

~
1
2.0 ,

~
w',oo
!!!

o
Zao
w

.
CI

~
o
~

80

W


CO

~ ~

_ 1mV ' -

0

g:::

POSITIVE SWING

r:::t:-..

!; [!!

t--

-S

~6
:::l>

o

400

600

800

!-

t--

r-...

I<
10--

SmV
1..-10mV

l>-

-10

1K

2.0

1.S

1.0

f-

I
I

I
O.S

ffI-

I I I

1"-1.0';';;;'

o
200

::-,0mV
i-- SmV
:-- 1mV

I:::==P L.c~
i--""

5

w 0

If

2

10

In!::i

f-

-

I

U

4

,
...w"

I I I

NEGATIVE SWING

SETTLING TIME -/JS

LOAD RESISTANCE - OHMS

•

POWER SUPPLY REJECTION
RATIO VS FREQUENCY

COMMON MODE REJECTION
RATIO VS FREQUENCY

III,
120

0120

~

~
o

~

...!!l

100

100
80

80

.........

a:

w 60

60

o

o

::ii

z

..........
40

40

~ 20

20

~

1"-

...... 1'-.

"

r-.......

r-.
NEGATIVE
SUPPLY

POSITIVE
SUPPLY

I'--~

V

t-

u

o

100

1K

o

1MEG

100K

10K
FREQUENCY-Hz

100

1K

10K
FREQUENCY - Hz

100K

1MEG

POWER SUPPLY CURRENT
VS TEMPERATURE

C 4.0

...~

I~I.-'

...... V I""'bo

w

a:
a:

I""-tV

U 3.S

~

V

r-t-

I-'"

II:

"'" i"'-

f""-

t-

t-t-

~
3.0
-80

l-

f""-

i"'-

:::l

-

I-

~

'-"

Z

_...

.....

VSUPPL Y • .:!: 20V
VSUPPLy=.:!:1SV
VSUPPLY -.:!: 10V
VSUPPLY • .:!: SV

-

1 I

1-

I

-40

o

+40
+80
TEMPERATURE oc

I

I

+120

I

I

+160

2-109

APPLYING THE HA-5100/5105 WIDE BAND OP AMP
1.

2.

POWER SUPPLY OECOUPLlNG: Although not absolutely necessary, it is recommended that all power supply lines be decoupled with .01 p.F ceramic capacitors
to ground. Decoupling capacitors should be located as
near to the amplifier terminals as possible.
STABILITY CONSIDERATIONS:
In applications
where large value feedback resistors are used, a small
capacitor (~3pF) may be needed in parallel with the
feedback resistor to neutralize the pole introduced by
the input capacitance.

3.

4.

HEAVY CAPACITIVE LOADS: When driving heavy
capacitive loads ( ~ 100pF) a small resistor (~10Dn)
should be connected in series with the output and inside
the feedback loop.
OFFSET VOLTAGE NULLING: Offset nulling, if
required, is accomplished with a 100Kn pot between
pins 1 and 5; wiper to V+. Alteration of initial offset
voltage may affect the temperature coefficient of the
offset voltage.

APPlICA TIONS
PRECISION INSTRUMENTATION AMPLIFIER (AV = 100)

•

+15V

-15V

Experimental Results
Yielded BOdB CMRR.

2K

VIO drift<20P.V/oC.

PRECISION/FAST SAMPLE/HOLD CIRCUIT
#25100
+15V
S0210

.,~ ":=====:1:K=:i=~~~~:~~___

--I

S0210 t-\N"""+---,~'V'-'

-15V

-

OUT

Experimental Results:
VIN =10 volt step
CH = 1000pF
Acquisition Time =0.4p.s (0.1%1
Charge Injection = 30pC
Drift Current = 320pA
S";itching Spikes :::::: 200mV

1kHz SALLEN AND KEY FILTER
.254I'F.:I:10%

Results:
FC = 1KHz
Q=20
-3dB ~ 1.1 KHz
-20dB ~ 3.4KHz
Experimenta~

2-110

HA-5110/5115
Wideband, JFET Input,
Uncompensated,
Operational Amplifier

FEATURES

DESCRIPTION

•

WIDE GAIN BANDWIDTH ......... 60MHz

•

HIGH SLEW RATE ............. 50V/p.s

•

SETTLING TIME ............... 850ns

•

POWER BANDWIDTH .......... 800KHz

•

OFFSET VOLTAGE ............. 0.5mV

•

BIAS CURRENT ................ 50pA

APPlICA TIONS
•

VIDEO AND RF AMPLIFIERS

•

DATA ACQUISITION

•

PULSE AMPLIFIERS

•

PRECISION SIGNAL GENERATION

HA-511 0/5115 are wideband, uncompensated, operational amplifiers manufactured with FET/Bipolar technologies and dielectric
isolation. These monolithic amplifiers feature superior high frequency capabilities further enhanced by precision laser trimming of
the input stage to provide excellent input characteristics. These
devices are controlled at closed loop gains greater than 10 without
compensation.

•

With excellent dynamic and input characteristics, HA-5110/5115
are well suited for many wideband, pulse, and video applications.
These amplifiers are ideal components for video and RF circuitry
requiring up to 60MHz gain-bandwidth-product and 800KHz power
bandwidth. 50V I p. s slew rate and 850ns settling time make these
devices useful in pulse amplification and data acquisition designs.
HA-5110/5115's 0.5mV offset voltage, 10pA offset current, and
extremely high impedance coupled with excellent AC parameters
make these amplifiers ideal selections for accurate signal conditioning designs. For applications requiring less critical input characteristics, HA-5115 is available in untrimmed form.
HA-5110/5115 are available in metal can (TO-99) packages. Suffix
-2 denotes a range to -55 0 C to +125 0 C and -5 denotes a OOC to
+75 0 C range.

SCHEMATIC

PINOUT
Section 11 for Packaging

TOP VIEW

COMPENSATION

v-

CASE CONNECTED TO V-

2-111

SPECIFICA TlONS
ABSOLUTE MAXIMUM RATINGS
Voltage Between V+ and VDifferential Input Voltage
Peak Output Current

Internal Power Dissipation (Note 2)
Storage Temperature Range

40V
±40V
Full Short Circuit Protection

510mW
-65 0C to +150 0C

ELECTRICAL CHARACTERISTICS
V+=15VDC·, V-=-15VDC
Parameters are guaranteed at indicated
ambient temperature after warm-up.
PARAMETER
INPUT CHARACTERISTICS
OffSet Voltage

•

Offset Voltage Average Drift
Bias Current
Offset Current
Input Resistance
Common Mode Range
TRANSFER CHARACTERISTICS
Large Signal Voltage Gain (Note 3)
Common Mode Rejection Ratio (Note 4)
Gain Bandwidth Product (AV = 10)
OUTPUT CHARACTERISTICS
Output Voltage Swing (Note 5)
Output Current (Note 6)
Full Power Bandwidth (Note 7)
Output Resistance (Note 8)
TRANSIENT RESPONSE (Note 9)
Rise Time (AV = 10)
Slew Rate (AV = 10)
Settling Time (Note 10)
POWER SUPPLY CHARACTERISTICS
Supply Cumint
Power Supply Rejection Ratio (Note III

TEMP

HA-5110-2
-55 0C to +125 0C
TYP MAX
MIN

HA-5110-5
OOC to +75 0C
MIN
TYP MAX

mV
mV
IN/oC
pA
nA
pA
nA

+250C
Full
Full
Full

75K
60K
ao

150K
lOOK
86
60

75K
60K
80

150K
lOOK
86
60

50K
40K
80

lOOK
aOK
86
50

V/V
V/V
dB
MHz

+25 0C
Full
+25 0C
+25 0C
+25 0C

±12
±12
±IO
550

±13
±13
±15
625
30

±12
.112
.t10
550

±13
.113
.t15
625
30

±II
±II
.18
550

±12
±12
.±15
625
40

V
V
mA
kHz

20
40
1.0

nsec
V/p.sec
p.sec

Full
+25 0C

80

50
10
10
5
±IO

20
50
.85
5
94

35

7
80

2
2
10 12
±II

1.0
2.0

1.5
3.5

0.5
0.50
5
20
5
2
2
10 12
±II

35

0.5
0.50
10
20

0.5
0.75
15
50
10
5
5
10 12
±10.5

+25 0 C
Full
Full
+25 0C
Full
+25 0C
Full
+25 0C
.110
Full

+25 0C
+25 0C
+25 0C

1.0
2.0

HA-5115-5
OOC to +750C
MIN TYP MAX UNITS

50
10
10
5
±IO

20
50
.85
5
94

35

7
80

6
94

100
20
50
10

n
V

n

8

mA
dB

NOTES:
1. Absolute maximum ratings are limiting values, applied individually, beyond which the serviceability of the circuit may be
impaired. Functional operability under any of these conditions
is not necessarily implied.
2. Derate at 6.8mW/oC for operation at ambient temperatures
above +750C.
3. VOUT = ±10V. RL = 2K
4. VCM = tlO V.D.C.
5. RL = 10K

2-112

6. VOUT = OV
7. RL = 2K; Full power bandwidth guaranteed, based on slew
rate measurement using FPBW = SLEW RATE.
21TVPEAK
8. Output resistance measured under open loop conditions.
9. Refer to Test Circuits section of the data sheet.
10. Settling Time is measured to 0.1% of final value for a 10 volt
output step and AV = -10.
tt. VSUPP =±to V.D.C. to±20 V.D.C.

NOTES:
6. VOUT= OV
7. RL = 2K;. Full power bandwidth guaranteed, based on slew
.
SLEW RATE.
rate measurement uSing FPBW = 2'TVPEAK

1. Absolute maximum ratings are limiting values, applied individ-

ually, beyond which the serviceability of the circuit may be
impaired. Functional operability under any of these conditions
is not necessarily implied.

8. Output resistance measured under open loop conditions.

2. Derate at 6.8mW/oC for operation at ambient temperatures
above +75 0 C.

9. Refer to Test Circuits section of the data sheet.

3. VOUT=±10V. RL=2K
4. VCM =tID V.D.C.

10. Settling Time is measured to 0.1% of final value for a 10 volt
output step and AV = -10.

5. RL=lOK

11. VSUpp = tlo V.D.C. to+ 20 V.D.C.

TEST CIRCUITS
LARGE AND SMALL SIGNAL RESPONSE CIRCUIT
IN

0-

•

I

LARGE SIGNAL RESPONSE

SMALL SIGNAL RESPONSE
Vertical Scale: (Volts: A=10mV/Div., B~100mV/Div.)
Horizonal Scale: (Time: 100ns/Di•• )

Vertical Scale: (Volts: A=.5V/Div,B=5V/Div.)
Horizonal Scale: (Time: 500ns/Div.)

r

A

~~I/r+-+~~4-+-~~

II

OUTPUTB~~~~~~~~~~~~~~~
INPUT A

I-..........-I-+-=I='--J--I-....- I - I

INPUT A

1-..........-1--I-4-11-.f-....-I--Iov

SETTLING TIME CIRCUIT

+15V

'i -()

,. . t-__ L...---l"l
2N 44
_ -1'..
6

soon

5Kfl

tv;":"

2KU

~CILLOSCOPE

;'r;( -_

VIN

~o--+...A'N'
'~-=H~A'U'T'
20011

I

-15V

2KU

--=r=

::r:

50

_F

Your
•

AV = -1.

•

Feedback and summing
resistors should be D.1%.

• CliPPing diodes are optional.
HP5082-2810 recommended.

2-113

PERFORMANCE CURVES
=+1SV, V- = -1SV, TA = +2SoC Unless Otherwise Stated.

V+

INPUT OFFSET VOLTAGE AND BIAS
CURRENT VS TEMPERATURE

OPEN LOOP FREQUENCY RESPONSE

•
,
,
,
, ~
, 6
• >=
tt

•

.S

..

GAIN

.6 ~

..

A

OFFSET VOLTAG!

'

.2

......E

.0

,/

,8
D.B

I

•

...

•

...

....

,,..

..,

... 0

BIAS CURRENT

•

-0.2

•

..

'00

-004
<

•

Y SUPPLY. :tIOY

•

'00.

•
•

.......

1MEO

'00

,.

.'\
10K

100K

lMEO

lOMEG

l00MEG

FREQUENCY _ Hz

10MEG

FREQUENCY - Hz

NOTE: External compensation components are not
required for closed loop gains> 10, but may
be added to reduce bandwidth If desired.

NORMALIZED AC PARAMETERS
VS TEMPERATURE

INPUT NOISE VOLTAGE AND
NOISE CURRENT VS FREQUENCY

'00

2..
2

1""1""'-

·

\.\

,.
2-114

.... _.

'

'\

•

II

.,

.•

i'
-s

,.
URCE RESISTANCE. 20Kn

...... JJ IJJ.l.lSOURCE "ESISTANCE-.n

........ "'"
».,[+'

1100PF*:r

~
I~

3~13~*

1~A.

Sf!

J

5pF**

~

\.,

OUTPUT

Vertical Scale: (Volts: 2V/Div.I
Horizonal Scale: (Time: 500ns/Div.I

40dB, 1MHz BANDWIDTH AMPLIFIER
CLOSED LOOP FREQUENCY RESPONSE (AV = 1001

SIG.INo--

~

CD

."

50

I

OUT

r-;;7'

5Kn

Z

:;:
0
0

50n
~

40

...........

CI

a.

...

,

30

Q
w 20
II)
0
10
()

...

C.
1K

10K

100K
FREQUENCY - Hz

2-116

1MEG

10MEG

;II

HA-5130/5135

HARRIS

Precision
Operational Amplifier

FEATURES
•

DESCRIPTION
25pV

LOWOFFSETVOLTAGE

•

LOW OFFSET VOLTAGE DRIFT

0.4pV/oC

•

LOW NOISE

9nV/jIh
107

• OPEN LOOP GAIN
•

2.5MHz

BANDWIDTH (UNITY GAIN)

• ALL BIPOLAR CONSTRUCTION

APPLICATIONS

HA-5130/5135 are precision operational amplifiers manufactured using a
combination of key technological advancements to provide outstanding
input characteristics.
A Super Beta input stage is combined with laser trimming, dielectric isolation, and matching techniques to produce 25pV (Max,) input offset voltage and 0.4 p V10C input offset voltage average drift. Other features enhanced by this process include 9.nV (Typ.) Input Noise Voltage, 1nA
Input Bias Current, and 140dB Open Loop Gain.

II

These features coupled with 120dB CMRR and PSRR make HA-51301
5135 an ideal device for precision DC instrumentation amplifiers. Excellent input characteristics in conjunction with 2.5MHz bandwidth and 0.8V 6Is
slew rate, makes this amplifier extremely useful for precision integrator
and biomedical amplifier designs. These amplifiers are also well suited for
precision data acquisition and for accurate threshold detector applications.

• HIGH GAIN INSTRUMENTATION
• PRECISION DATA ACQUISITION
• PRECISION INTEGRATORS
• BIOMEDICAL AMPLIFIERS

HA-5130/35 is packaged in an 8 pin (TD-99) can and an 8 lead Cerdip
and is pin compatible with many existing op amp configurations.

• PRECISION THRESHOLD DETECTORS

HA-5130/5135-2 is specified for -55 0C to +125 0 C operation while
HA-5130/5135-5 operate from OOC to +75 0C.

PINOUT

SCHEMATIC

Section 11 for Packaging
BALANCE

TOP VIEW

vBALANCE

BALANCE

IN-

v+

IN+

OUT

v-

BALANCE

* Pins 5 and 8 are internally connected

2-117

SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS

(Note II

TA = +250C Unless otherwise stated
Voltage Between V+ and V- Terminals
Differential Input Voltage

Power Dissipation (Note 21
Dperating Temperature Range
HA-513D/5135-2

40.0V
± 15.0V.

3DDmW
-55 0C .s; TA~ +125 0C
DI)C~TAS.+750C

HA-513D/51;J5~5

Indefinite

Output Short Circuit Duration

ELECTRICAL CHARACTERISTICS

PARAMETER
INPUT CHARACTERISTICS
Offset Voltage
Average Offset Voltage Drift
Bias Current
Bias Current Average Drift
Offset Current
Offset Cllrrent Average Drift
Common Mode Range
Differential Input Resistance
Input Noise Voltage
O.IHz to 10Hz (Note 3)
Input Noise Voltage Density (Note 3)
fO = 10Hz
fO= 100Hz
fO = 1000Hz
Input Noise Current (Note 3)
O.IHzto 10Hz
Input Noise Current Density (Note 3)
fO = 10Hz
fO = 100Hz
fO = 1000Hz
TRANSFER CHARACTERISTICS
Large Signal Voltage Gain (Note 4)

V+ =15V, V- =-15V

TEMP.

+250C
Full
Full
+250 C
. Full
Full
+250C
Full
Full
Full
+25 0 C
+25 0C

MIN.

HA-5130-2/-5
TYP.
MAX.

10
50
0.4
±I
0.02
0.02
:!: 12
20

0.02
0.02

75
130
1.3
±4
:!:6
0.04
4
5.5
0.04

30
0.6

+25 0C
13.0
10.0
9.0
15

+25 0C

18.0
13.0
11.0
30

13.0
10.0
9.0
15

18.0
13.0
11.0
30

+25 0C
0.4
0.17
0.14

+25 0C
Full
+25 0C
+250C
+250C

:!:.10
:!:10
8
:!: 25

± 12

TRANSIENT RESPONSE (Note 10)
Rise Time
Slew Rate
Settling Time (Note 11)

+25 0C
+25 0C
+250C

0.5

Full
Full

UNITS

/lV
/lV
/lV/OC
nA
nA
nAloC
nA
nA
nA/OC
V
Mn
/lV p_p
nV/JHz

pAp-p
pAl.jH.

Full Power Bandwidth (Note 7)
Output Current (Note 8)
Output Resistance (Note 9)

0.8
0.23
0.17

120
2.5

10
:t30
45

100

NOTES:
1. Absolute maximum ratings are limiting values, applied individually
beyond which the serviceability of the circuit may be impaired.
Functional operability under any of these conditions is not
necessarily implied.

10
50
0.4
:!:I

0.6

140

POWER SUPPLY CHARACTERISTICS
Supply Current
Power Supply Rejection Ratio (Note 12)

25
60
0.6
±2
:!:4
0.04
2
4
0.04

30

120
120
110
0.6

OUTPUT CHARACTERISTICS
Output Voltage Swing (Note 6)

HA-5135-2/-5
MIN.
TYP. MAX.

± 12
20

+250C
Full
Full
+250C

Common Mode Rejection Ratio (Note 5)
Closed Loop Bandwidth (AVCL = +1)

-65 0C:S TA ~ +150 oC

Storage Temperatura Range

340
0.8
11
1.0
130

0.4
0.17
0.14
"120
120
106
0.6

140

± 10
± 10
8
:!: 25

± 12

0.5

1.3
94

0.8
0.23
0.17
dB
dB
dB
MHz

120
2.5

10
:t30
45

V
V
kHz
rnA
n

340
0.8
II

ns
V/IlS
/ls

1.0
130

1.7

rnA
dB

7. RL = 2k; Full power bandwidth guaranteed based on slew rate
measurement using FPBW = SLEW RATE
21T VPEAK
.

8. VOUT = 10V

2. Derate at 6.8mW/oC for operation at ambient temp:s above +750C.
9. Output resistance measured under open loop conditions
3. Not tested. 90% of units meet or exceed these specifications.
(f = 100Hz)
4. VOUT =:!: lOY; RL = 2k. Gain dB = 20 1091O Average
10. Refer to test circuits section of the data sheet .
.... 120dB = 1000V/mV
11. Settling time is measured to 0.1% of final value for a 10V output
140dB = 10,OOOV/mV
step and AV = -1. .
5. VCM =:!: 10V DC
12. VSUpp=±5V DC to:!: 20V DC.
6. RL = 600n

2-118

TEST CIRCUITS
SLEW RATE AND TRANSIENT RESPONSE TEST CIRCUIT

SMALL SIGNAL RESPONSE
Vertical Scale: (Volts: 50mV/Div. Output)
(Volts: 100mV/Div. Input)
Horizontal Scale: (Time: 1JLs/Div.)

LARGE SIGNAL RESPONSE
Vertical Scale: (Volts: 5V/Div.l
Horizontal Scale: (Time: 5ps/Div.)

•

\

\

INPUT

OV

"
OUTPUT

OV

INPUT

~)

OV

V

OUTPUT

lL

1"-

......

~

OV

SETTLING TIME CIRCUIT

+15V

2N4416
5Kn

t-...----1~

TO
OSCILLOSCOPE

>-...- ...--u VOUT
•

AV = -1.

• Feedback and summing
resistors should be 0.1%.
• Clipping diodes are optional.
HP5082-2810 recommended.

2-119

PERFORMANCE CURVES

INPUT OFFSET VOLTAGE, INPUT BIAS

INPUT BIAS CURRENT VS.

AND OFFSET CURRENT VS. TEMPERATURE

DIFFERENTIAL INPUT VOLTAGE

'" .""-.

BIl

~

w

g~

i

70

50
~

'\ ~

30

:'"

20

0
0
-80

•

RRENT

......

~ 40

~

f"".- INPUT BIAS C

60

INPUT OFFSET CURRENT

...............

,>

" .......
+40

~

TV~~rL-

II:
II:

,IVOS

r-

+80

1--'""" .....

~

./

-2

-

-6

il

-4
+'60

+120

...... ~

......

-10

...a

-8

.04

-2

8

10

DIFFERENTIAL INPUT VOLTAGE-VOLTS

TEMPERATURE DC

HA-5130 OFFSET VOLTAGE
STABILITY VS. TIME

INPUT - NOISE VS. FREQUENCY

boko\TlbJs, I

I

II

VSUPPL V .. ±11iV

TC"'±1 oC
AV-1000

'0

.2

\.

NOTE: MEASUREMENT AND
ENVIRONMENTAL SYSTEMS
ALLOWED 12 HOUR STABILIo

-

__

0

fJ'

-'0
246810

o

40

20
30
TIME-DAYS

:~ECTRENT

'00

'0

.. '80

~120

~ 100

.......

"

~

:
8
~

....

40
20

~

0

z

0_20

2-120

,

~ASEANGLE

GAIN

I
I

.......

'00

1K
10K
FREQUENCY -Hz

........

,

,

360

~

,OOK

gOO

....... ~"\

J
'0

oo

I
I

....

1M

J

./

1K
10K
FREaUENCY - HZ

OPEN LOOP FREQUENCY RESPONSE

:140 ..........

--

NOISE JLTAGE

\"
\
\

ZATION PERIOD.

o

,
, ~
, 1

10M

9..",

.0

.7

~

II:

.6

§

.4

!5

"

.2

'OOK

I

PERFORMANCE CURVES (Continued)

CLOSED LOOP FREQUENCY RESPONSE

SMALL SIGNAL BANDWIDTH AND

FOR VARIOUS CLOSED LOOP GAINS

PHASE MARGIN VS. LOAD CAPACITANCE

600

80

1ft
z·

......

70
60

"-

~

20
10

PHASE MARGIN

"-

i!;4O

"'"

930
9
u

2.6

~

~60

.

.........

"'"

~

-10

10

100

1K

10K

"-

100K

1M

10M

100

FREQUENCY,Hz

00

10

2.5
BANDWIDTH

~

1000

100

2A

\'

2.35

10.000

LOAD CAPACITANCE-pF

OUTPUT VOLTAGE SWING VS.

MAXIMUM OUTPUT VOLTAGE SWING VS.

FREQUENCY AND SUPPLY VOLTAGE

LOAD RESISTANCE AND SUPPLY VOLTAGE

35
VSUPPL Y •

fov

VSUPPLYj,±16~

r

VSUPPL

VSUPP1" :±5V

100

l30
~ 25

RL'" 2K

~

~
:±10V

I

1K

~\

~w

(VSUPPLY;;O+1s1"

20

~ 15

\
_\

f

!:i

~ 10

~

!;

"

10K
FREQUENCY. Hz

•

o

"'-

tOOK

VSUPtLY - t10V

J

5

1M

/

/'

10

VSUPtLY '" ±SV

100
1K
LOAD RESISTANCE-OHMS

10K

NORMALIZED AC PARAMETERS
VS. SUPPLY VOLTAGE

.,
ffi

To1

t;
~

1.0

~

0.9

S

O.B

~

j

0.7

~

0.6 0

BA~DWlbTH
f((
II-~LEWRATE

N

±2

±4

±S

±8

±10 1'12

±14 ±18 1'18

±2D

SUPPLY VOLTAGE - VOLTS

2-121

!

PERFORMANCE CURVES (Continued)

CMRR VS. FREQUENCY

PSRR VS. FREQUENCY

14°1===~:--r--r--r-1

140

1==4=--T----,r-i-i

20

1------+-----4-----~----_+----~

120 I--_ _+_..............
~~+_--+_--+_-~

12oll---+-"""-....3oo,<+---+---4---l

l00~-~~--+~~__-+---~--~

~~~---~,,~---~~
~r--+--+---4~~~~

'"

4Or--+--+-~--~,,~
201------+-----4-----~----+--~~

°O~I----~IO----~IOO~--~I~K----~IO~K~---d,00K
FREQUENCY Hz

O~I-----I~O----~IOO~--~I~K----~I~OK~--~,00K
i=REauENCV~Hz

SETTLING TIME FOR VARIOUS

POWER SUPPLY CURRENT VS.

OUTPUT STEP VOLTAGES

TEMPERATURE AND SUPPLY VOLTAGE

<

11.4
1.
J
11.2 ~v
\ I.}s • .,sv---+----+----+----l

. . 11.0~~@!~~~~$!!i!i!!~~_.--__1

ia:

a t.8
~

11

VS·+1OV

+s
Vs" v

t.e

~ 1~~--~--~~--~--~~--~--~
1.2~--~----~--~--~~--~----I

TEMPERATURE DC

APPLYING THE HA-5130/5135 OPERATIONAL AMPLIFIERS
1.

2.

POWER SUPPLY OECOUPLlNG: Although not absolutely
necessary, it is recommended that all power supply lines
be decoupled with .01~ F ceramic capacitors to ground.
Decoupling capacitors should be located as near to the
amplifier terminals as possible.
CONSIDERATIONS FOR PROTOTYPING: The following
list of recommendations are suggested for prototyping.
• Resolving low level signals requires minimizing leakage
currents caused by external circuitry. Use of quality
insulating materials, thorough cleaning of insulating
surfaces, and implementation of moisture barriers
when required is suggested.
• Error voltages generated by theromocouples formed
between dissimilar metals in the presence of temperature gradients should be minimized. Isolation of
low level circuitry from heat generating. components
is recommended.
• Shielded cable input leads, guard rings, and shield
drivers are recommended for the most critical applications.

2-122

3.

When driving large capacitive loads (> 500pF), as small
value resistor (~50 n) should be connected in series with
the output and inside the feedback loop.

4. OFFSET VOLTAGE ADJUSTMENT: A 20 Kn balance
i_potentiometer is recommended if offset nulling is required.
--- -- ~owever, other potentiometer values such as 10Kn, 50KS1,
~nd 100KH may be used.
The minimum adjustment
range for given values is±2mV.
5.

SATURATION RECOVERY: Input and output saturation recovery time is negligible in most applications. However, care should be exercised to avoid exceeding the
absolute maximum ratings of the device.

6.

DIFFERENTIAL INPUT VDLTAGES: Inputs are shunted
with back-to-back diodes for overvoltage protection.
In applications where differential input voltages in excess
of IV are applied between the inputs, the use of limiting
resistors at the inputs is recommended.

APPLICATIONS
OFFSET NULLING CONNECTIONS

PRECISION INTEGRATOR
C

V+

---.,

I
I
I
I

OUT

I
I
I
I

OPTIONAL
CONNECTION

I
I

__ JI

The excellent input and gain characteristics of HA5130 are well suited for precision integrator applications. Accurate integration over seven decades of
frequency using HA-513o, virtuallv nullifies the need
for more expensive chopper-type amplifiers.

* Although Rp is shown equal to 2ok, other values such
as SDk, 1ook, and 1M may be used. Range of adJustment is approximatelv :!:2.5mV. Vos TC of the
amplifier is optimized at minimal Vas.

•

ZERO CROSSING DETECTOR

OUTPUT
:t 13V

200,us/DIV

INPUT

-

RIN

\
INPUT

±'5mV
200,us/DIV.

J

I
1

ii,

.I. ,\

\

I
I

o--NV'-1
II

rr

I

J

I

I

_
RF

I

t------v\IV'-----I

I

I

I

I

I

I

I

• OPTIONAL FOR
OUTPUT SWING
LIMITING

Low VOS coupled with high open loop Gain, high
CMRR, and high PSRR make HA-513o ideallv
suited for precision detector applications.

PRECISION INSTRUMENTATION AMPLIFIER (AV

= 100)

2K

2K

2K

2K

2-123

mH.ARRlS

Wideband, JFET Input,
High Slew Rate, Uncompensated,
Operational Amplifier
DESCRIPTION

FEATURES

•

HA-5160/5162

•

WIDE GAIN BANDWIDTH

100MHz

•

HIGH SLEW RATE

120V/Jl.s

•

SETTLING TIME (O.2%)

•

POWER BANDWIDTH

•

OFFSET VOLTAGE

•

BIAS CURRENT

280ns
1000kHz
1.0mV
20pA

APPL/CA TlONS
•

VIDEO AND RF AMPLIFIERS

•

DATA ACQUISITION

•

PULSE AMPLIFIERS

•

PRECISION SIGNAL GENERATION

The HA-5160/5162 is a wideband, uncompensated, operational amplifier
manufactured with FET/Bipolar technologies and dielectric isolation. This
monolithic amplifier features superior high frequency capabilities further
enhanced by precision laser trimming of the input stage to provide excelent input characteristics. This device has excellent phase margin at a closed
loop gain of 10 without external compensation.
The HA-5160/5162 offers a number of important advantages over similar
FET input op amps from other manufacturers. In addition to superior
bandwidth and settling characteristics, the HARRIS devices have nearly
constant slew rate, bandwidth, and settling characteristics over the operating
temperature range. This provides the user predictable performance in
applications where settling time, full power bandwidth, closed loop bandwidth, or phase shift is critical. Note also that HARRIS specified all parameters at ambient (rather than junction) temperature to provide the designer
meaningful data to predict actual operating performance.
Complementing the HA-5160/5162's predictable and excellent dynamic
characteristics are very low input offset voltage, very low input bias current,
and extremely high input impedance. This ideal combination of features make
these amplifiers most suitable for precision, high speed, data acquisition
system designs and for a wide variety of signal conditioning applications.*
The HA-516D provides excellent performance for applications which require
both precision and high speed perfornance. The HA-5162 meets or exceeds
the performance specifications of National's hybrid op amp, the LHDD62.

* -2 denotes a range of -55 0 C to +125 0 C and -5 denotes a DOC to +75 0 C
range.

SCHEMATIC

PINOUT
Section 11 for Packaging
COMPENSATION

TOP VIEW

B
NC

1

IN- 2

7 V+

-

~:

OB5

6 OUT

+

IP49'P5 -P48

IN+ 3

.v

5 NC

P17

D52

~

C,~Pl

054

:'8 N

D65

P24

v.<

P2Ei

:'6"

0'28

P28

r---

~.r:;.~

~ I,~ ~;OUT

~'7N5:;~l¥P6
C2.

J5

r-~"'"

~ :~ ~~ f8 tR19 ~~ n
O"~~" P7> 9 PI' k.

4

Case connected to V-

fs

P13

rOD P73~J-""*",Plm,H---t-++-t-I-l'1'18

31

"""f"

102 Rl02

~

L - P30

_IN

N44~.~~v
.70
N76

N17

.52
"53

.37

.34

.32

." .'"
"'

N"
"'

.33

P19~P80

.,i:""

~• 40

'41

~Rl

2-124

R2

.39
R3

R4

R7

-v

SPECIFICA TlONS
ABSOLUTE MAXIMUM RATINGS
40V

Voltage Between V+ and V-

±40V

Differential Input Voltage

Full Short Circuit Protection

Peak Dutput Current
Internal Power Dissipation (Nate 2)

675mW
-65 0 C to +150 oC

Storage Temperature Range

ELECTRICAL CHARACTERISTICS

V+ =+15V, V- =-15V

HA-5160-2
-55 0 C to +125 0 C
PARAMETER

TEMP

MIN

TYP

MAX

1.0
3.0

3.0
5.0

HA-5160-5
OOC to +75 0 C
MIN

HA-5162-5
OOC to 75 0 C
MAX

TYP

UNITS

3.0
5.0

3
5
20

15
20

mV
mV

35

pV/oC

65
10
10
5

pA
nA
pA
nA

TYP

MAX

1.0
3.0

MIN

INPUT CHARACTERISTICS
Offset Voltage

+25 0 C
Full
Full

10

Bias Current

Offset Voltage Average Drift

+25 0 C
Full

20
5

50
10

20

50
10

20

Offset Current

+25 0 C
Full

10
5

+25 0 C

2
2
10 12

10
5

Input Resistance

2
2
10 12

2
2
10 12

Common Mode Range

20

•

n

Full

.t 10

:tl1

.tl0

.tIl

:tl0

±.ll

V

+25 0 C
Full

75K
60K

150K
lOOK

75K
60K

150K
lOOK

25K
25K

lOOK
75K

V/V
V/V

Full

74

80

74

80

70

TRANSFER CHARACTERISTICS
Large Signal Voltage Gain (Note 3)
Common Mode Rejection Ratio (Note 4)
Gain Bandwidth Product (AV

~

10)

Full

100

100

80

dB

100

MHz

til
±.11

V
V

OUTPUT CHARACTERISTICS
Output Voltage Swing (Note 5)

+25 0 C
Full

.:!:. 10
:tl0

Output Current (Note 6)

+25 0 C

.:!:. 15

±. 20

rnA

Full Power Bandwidth (Note j)

+25 0 C

1000

1000

1000

kHz

Output Resistance (Note 81

+25 0 C

50

50

50

n

.:!:..11
:t.11

:tl0
:t. 10

±. 20

:t15

:tIl
.:!:..11

±.10
±.10

±. 20

±. 15

TRANSIENT RESPONSE (Note 91
Rise Time (AV

~

101

+25 0 C

Slew Rate (AV

~

10)

+25 0 C

Settling Time (Note 10)

20
100

+25 0 C

20

120

100

280

120

50

280

20

ns

70

Vips

400

ns

POWER SUPPLY CHARACTERISTICS
Supply Current
Power Supply Rejection Ratio (Note 11)

Full
+25 0 C

8.0
74

86

10

8.0
74

86

10

8.0
70

86

12

rnA
dB

2-125

NOTES:

6. VOUT = OV
7. RL = 2k; Full power bandwidth guaranteed, based on slew
.
SLEW RATE.
rate measurement uSing FPBW = 21TVPEAK

1. Absolute maximum ratings are limiting values, applied individually, beyond which the serviceability of the circuit may be
impaired. Functional operability under any of these conditions
is not necessarily implied.

8. Output resistance measured under open loop conditions.

2. Derate at 6.8mW/oC for operation at ambient temperatures
above +75 0 C.

9. Refer to Test Circuits section of the data sheet.

3. VOUT=±10V. RL=2k

4. VCM = ± 10V DC.

10. Settling Time is measured to 0.2% of final value for a 10 volt
output step and AV = 10.

5. RL

lL VSUPP = ±10 V.D.C. to ±20V. DC •.

=

2k

TEST CIRCUITS
LARGE AND SMALL SIGNAL RESPONSE CIRCUIT

•
LARGE SIGNAL RESPONSE
Vertical Scale: (Volts: A = O.5V/Div., B = 5V/Div.l
Horizontal Scale: (Time: 500ns/Div.)

SMALL SIGNAL RESPONSE
Vertical Scale: (Volts: A = 10mV/Div., B = 100mV/Div.)
Horizontal Scale: (Time: 100ns/Div.)

.

It.

I
OUTPUrB

OV

lJ

OUTPUTB

il
INPUT A

I

OV

J

INPUT A

SETTLING TIME CIRCUIT
+15V

TO
2N4416

••

~CILLOSCOPE
~

2k~

'I>

-=

=

• AV -10
• Feedback and summing
resistors should be 0.1%.
Clipping Diodes are optional.
HP5082-2810 recommended.

*

2k

2-126

PERFORMANCE CURVES

INPUT OFFSET VOLTAGE AND
BIAS CURRENT VS; TEMPERATURE

OPEN LOOP FREQUENCY RESPONSE
110

+2.50

iii

+2.0

4K

z
;;:

+1.5
OFFSET VOLTAGE

3K

l

+1.0

w

+D.50 ~

!

!:J

zw

II:
II:

i3
:.!

0

+D.O

... 2K

...>w

..

~.50

BIAS CURRENT

lK

iii

J

+40
+80
TEMPERATURE (OC)

0

"
w

~
g

VSUPPL V -

± 20V

30

"z
ii<
w~

25

z

~

20

S~

15

VLpPL V

10

VLPPLVo±7V

7
6
>"

5'
O~

1

lK

I

10K

0

+ 10V

"-

60

00

GAIN

.60

i"..

50

20

0

" "'"I"
"'PHASE

30

~
~

l\.
1\ \.

0
-10
10

1350

_\

10

100

lK

10K
lOOK
FREOUENCV

1M" 10M

I""

-2.0
+180

+120

1600

100M

•

OPEN LOOP FREQUENCY RESPONSE
FOR VARIOUS BANDWIDTH CONTROL
CAPACITANCES
100

'\

± 15V

"'I'
~o

"'-

-....

110

-.....

I
VSUPPL V •

70

40

9

OUTPUT VOLTAGE SWING
VS. FREQUENCY
35

80

...0

-1.50

VI

o

-80

If

-1.0

V

100

:g 90

----

lOOK
FREOUENCV (Hz)

iii
:g 90

z
;;:

'"w

1\

...0~

M

1M

>
:!;

\

9

~

zw
:!;

80

~

~~

I"'--.

"1'1"'-.-."-"-" .,

70

~

60

50
40

'V'

........

~/

."-"-

50pF

/

,~

30

100pF -

X

y

."\.V

20

~

10
-10
10

I
OpF

300pF

=

\.
'\

,,~

'\., I'\.\.

100

lK

10K
lOOK
FREOUENCY (Hz)

1M

10M

100M

10M

2-127

PERFORMANCE CURVES (Continued)

NORMALIZED AC PARAMETERS
VS. TEMPERATURE

INPUT NOISE VOLTAGE AND
NOISE CURRENT VS. FREQUENCY
1.1

160"'~----Y----'-I---'-I----,0.B

~

~

140
120 "\."\.

gli 100
gj <; BO"
i5i 50'.....

z

SOURCE RESISTANCE -100Kn

"\.~"

/

'jSOURCERESISTANCE-on

j

""

"'-....

......

0.7 ~
0.6 0:
5
00'A

(INPUT NOISE CURRENT

--...

~I:ii
a:;
5~

-

3

,............ j

1.0

O.

z~

40t=~::t:~~=t§§§~§~~0.2"
20
I
0.1 ~

s~

1~0----~I00=-----~I~K----~I~OK~--~10'0~

~

0.9 ~

!;(

O.B

0.7

~

0.6

-80

OUTPUT VOLTAGE SWING
VS. LOAD RESISTANCE

BANOWIDTH

-40

+40
+BO
TEMPERATURE (OC)

+10

10mV

NEGATIVE SWINV
L

/

~

L

.R

V

~TIVE

SWING-

V

'"
10mV

200

400

600

LOAD RESISTANCE (n)

800

lK

100

2-128

~

I"'::
+120

+160

SETTLING TIME FOR VARIOUS
OUTPUT STEP VOLTAGES

14

?--

",-

0.5

OA

•

B~NDWfoTJ

ffj

:3
~

FREQUENCY (Hz)

,

.~ ~SLEWRATE

V
~

300
400
200
SETTLING TIME (n.)

500

600

PERFORMANCE CURVES (Continued)

POWER SUPPLY REJECTION
RATIO VS. FREQUENCY

COMMON MODE REJECTION
RATIO VS. FREQUENCY
100

z
o

z

o

tw

80

~

~~ 60
w- r-eO

0;:
:1;«

za:

40

§l
:I;

8

3II0pF

o

1

~ 80
~~ 60

r-.....
't", ..

r~

20 f-

~~

-

+

10

100

lK

10K

1oo.---,---r---,---.----,---,

~~

40

~

20

=:§l
1011

,I

' ...~ ..
POSITIVE
_ SUPPLY

""~

RF

+

O,L--~,OL--,Joo--,~K--,OLK--,~oo-K-~,M

1M

lOOK

SUPPLY
300pF

FREQUENCY Hz

FREQUENCY Hz

•

POWER SUPPLY CURRENT
VS. TEMPERATURE
8.8.---,.---,.---,.---,.--c:=-'"...-----,

1
lZ

~ 8.0 I--+I-.,L--h~--r--",-"

a:

:::l

c.>

~

II:

iil 7.&1---111----1---1---1----'1----1

7.0'----'----'----'----'----'---...-1
-80

-40

o

40

80

120

160

TEMPERATURE oC

2-129

I

APPLYING THE HA-5160/5162
I. POWER SUPPLY OECOUPLlNG: Although not absolutely
necessasry, it is recommended that all power supply lines be
decoupled with 0.01 J.l. F ceramic capacitors to ground decoupling capacitors should be located as near to the amplifier
terminals as possible..
2. STABILITY: Tile phase margin of the HA-5160/5162 will be
improved by connecting a small capacitor (>1 OpF) between the

output and the inverting input of the device. This small capacitor compensates for the input capacitance of the FET.
3.

CAPACITIV~ LOAOS: When driving large capacitive loads
(>IOOpFt'it is suggested that a small resistor (~IOon)
be connecte~ in series with the output of the device and inside
the feedback loop.

APPlICA TlONS
SUGGESTED COMPENSATION FOR UNITY GAIN STABILITY *
INVERTING

•

NON INVERTING

2k
A

.....

2k

o--,/II\I'-A~_-I~

>-_--0

o-----f~

~A-5160/5162

1~160/5162

*VALUES WERE DETERMINED,EXPERIMENTALLV
FOR OPTIMUM SPEED AND SETTLING TIME

VERTICAL SCALE: (VOLTS: 2V/DIV.)
HORIZONTAL SCALE: (TIME: 500ns/DIV.)

"
OUTPUT~~-+-i--~~-+-1--~l~~

2-130

IJ~RIS

HA-5170
Precision JFET Input
Operational Amplifier

Preliminary
FEATURES
•
•

DESCRIPTION
IOOpV
3pV/oC

LOW OFFSEt VOLTAGE
LOWOFFSETVOLTAGEDRIFT

12nV/v'Hz'

• LOW NOISE
• OPEN LOOP GAIN
• BANDWIDTH (UNITY GAIN)

lOOK
SMHz

The Harris HA-S170 is a precisian, JFET input, operational amplifier
which features law noise, low offset voltage and law offset voltage drift.
Constructed using FET/Bipolar technology, the Harris Dielectric Isolation
(0 I) process, and laser trimming this amplifier offers low input bias and
offset currents. This operational amplifier design also completely eliminates the troublesome errors due to warm-up drift.
Complementing these excellent input characteristics are dynamic performance characteristics never before available from precisian operational
amplifiers. An 8V/p s slew rate and SMHz bandwidth allow the designer
to extend precision instrumentation applications in both speed and bandwidth. These characteristics make the HA-S170 well suited for precision
integrator amplifier designs.

APPlICA TIONS
• HIGH GAIN INSTRUMENTATION
• PRECISION DATA ACQUISITION
• PRECISION INTEGRATORS
• PRECISION THRESHOLD DETECTORS

The superior input characteristics also make the HA-SI70 ideally suited
for transducer signal amplifiers, precision voltage followers and precision
data acquisition systems.
Packaged in an 8-pin (TO-99) can or an 8 lead Minidip, the HA-S170
is pin compatible with most existing op amp configurations.

PINOUT

SCHEMATIC
Section 11 for Packaging

TOP VIEW
NIC

v-

BALANCE

NIC

IN-

v+

IN+

OUT

v-

BALANCE

2-131

•

SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
TA =+25 0C Unless otherwise stated
Voltage Between V+ and V-Terminals
Differential Input Voltage
Output Short Circuit Duration

ELECTRICAL CHARACTERISTICS

PARAMETER

(Note 11
Power Dissipation (Note 2)
Operating Temperature Range
HA-5170-2
HA-5170-5
Storage Temperature Range

44.0V
.i30.0V
Indefinite

675mW
-550C~TA ~+1250C

OOC~TA9750C
-650C~T A~ +150 0C

V+ = 15V, V- = -15V

TEMP.

MIN

HA-5170-2
TYP
MAX

MIN

HA-5170-5
TYP
MAX

UNITS

INPUT CHARACTERISTICS
Offset Voltage
Average Offset Voltage Drift
Bias Current

•

Bias Current Average Drjit
Offset Current
Offset Current Average Drift
Common Mode Range

Differential Input Resistance
Input Noise Voltage (f = 1kHz)
Input Noise Current (f = 1kHz)

+25 0C
Full
Full
+250 C
Full
Full
+25 0C
Full
Full
Full
+25 0C
+250C
+25 0 C

0.1

0.5
1
5
30
10

3
20
3

0.1

6x 10 10
12
0.01

mV
mV
/lV/oC
pA
nA
pAloC
pA
nA
pAloC
V
Mil
nV/VHz
pA/.jHZ

5

V/v
V/V
dB
MHz

3
20
0.04

30
5

0.5
0.75
5
60
0.1
3
60
0.1
1

±10

±10

6 x 10 10
12
0.01

TRANSFER CHARACTERISTICS
Large Signal Voltage Gain (Note 3)
Common Mode Rejection Ratio (Note 4)
Closed Loop Bandwidth (AVCL = +1)

+250C
Full
Full
+25 0C

lOOK
SOK
100

+25 0C
+250C
+250C
+250C

tID

aOK
50K
90
5

OUTPUT CHARACTERISTICS
Output Voltage Swing (Note 5)
Full Power Bandwidth (Note 6)
Output Current (Not. 7)
Output Resistance (Note a)

tl0
110

V
kHz
rnA

110

:tID

±10
45

n

45

TRANSIENT RESPONSE

Rise Time
Slew Rate
Settling Time (Note 9)

+250C
+250C
+250C

5

45
8
1

100

1.9

2.1

5

45
8
1

100

ns
V/,.s
,.s

1.9

2.1

rnA
dB

POWER SUPPLY CHARACTERISTICS
Supply CUrrent
Power Supply Rejection Ratio (Note 10)

Full
Full

NOTES:
1. Absolute maximum ratings afe limiting values, applied
individually beyond which the serviceability of the circuit
may be impaired. Functional operability under any of
these conditions is not necessarily implied.

100

90

6. RL = 2k;

Full power bandwidth guaranteed based on

sl.w rate measurement using FPBW _ SLEW RATE
2rrVPEAK
7. VOUT = 10V.

2. Derate at S.8 mW/DC for operation at ambient temperaturesabove +750 C.

8. Output resistance measured under open loop conditions
(f = 100Hz).

3. VOllT = ±10V; RL = 2k.
4. VCM = ±10V D. C.

5. RL= 2kn.

2-132

9. Settling tim. is measured to 0.1% of final value for a 10V
output st.p and AV = -1.
10. VSUpp = ±5V D. C. to ±20V D. C.

m~RIS

HA-5190/5195
Wideband, Fast Sett((I!U
Operational Amplifier

FEATURES
• FAST SETTLING TIME

GENERAL DESCRIPTION
70ns

• VERY HIGH SLEW RATE

200V/J..!s

• WIDE GAIN-BANDWIDTH

150MHz

• POWE RBAN DWIDTH

6.SMHz

• LOWOFFSETVOLTAGE

SmV

• INPUT VOLTAGE NOISE

15nV/v'HZ

• MONOLITHIC BIPOLAR CONSTRUCTION

APPlICA TlONS
• FAST, PRECISE D/A CONVERTERS
• HIGH SPEED SAMPLE-HOLD CIRCUITS
• PULSE AND VIDEO AMPLIFIERS
• WIDEBAND AMPLIFIERS
• REPLACE COSTlY HYBRIDS

SCHEMATIC

HA-5190/5195 are monolithic operational amplifiers featuring
an ultimate combination of speed, precision, and bandwidth.
Employing monolithic bipolar construction coupled with dielectric isolation, these devices are capable of delivering an unparalleled 200V I J..! s slew rate with a settling time of 70ns (0.1%,
5V output step). These truly differential amplifiers are designed
to operate at gains ~ 5 without the need for external compensation. Other outstanding HA-5190/5195 features are 150MHz
gain-bandwidth-product and 6.5MHz full power bandwidth. In
addition to these dynamic characteristics, these amplifiers also
have excellent input characteristics such as 5mV offset voltage
and 15nV input voltage noise (at 1kHz).
With 200V / J..! s slew rate and 70ns settling time, these devices
make ideal output amplifiers for accurate, high speed D/A converters or the main components in high speed sample/hold circuits. 150MHz gain-bandwidth-product, 6.5MHz power bandwidth, and 5mV offset voltage make HA-5190/5195 ideally
suited for a variety of pulse and wideband video amplifier applications.
At temperatures above +75 0 C, a heat sink is required for HA5190. (See note 2). HA-5190 is specified over the -55 0 C to
+125 0 C range while HA-5195 is specified from OOC to +75 0 C.

PINOUTS
Section 11 for Packaging

TOP VIEW

TOP VIEW

CASE TIED TO VLH0032 PINOUT

2-133

II

SPECIFICA TIONS
ABSOLUTE MAXIMUM RATINGS (Note 11
Voltage between V+ and V- Terminals
Differential Input Voltage
Output Current
Internal Power Dissipation (Note 21
Operating Temperature Range: (HA-51901"
(HA-51951
Storage Temperature Range

ELECTRICAL CHARACTERISTICS

35V
6V
50mA (Peak)
870mW (Cerdipl; lW (TO-BI Free Air
-55 0 C----t---.-o0UTPUT

+

•

lKW*

":'

.OOlu F

lJ-I

14

(
l"F
-V

*

...1.: PROBE

I

MONITOR

Load Capacitance should be less than 10pF.

** It

is recommended that resistors be carbon composition and

that feedback and summing network ratios be matched.

0.. SETTLE POINT (Summing Nodel capacitance should be less
than 1 OpF. For optimum settling time results, it is recommended that the test circuit be constructed directly onto the
device pins. A Tektronix 568 Sampling Oscilloscope with S-3A
sampling head's is recommended as a settle point monitor.

SETTLE

POINT

***
5KO**

2-135

PERFORMANCE CURVES
V+ = +15V, V- = -15V, TA = +25 0 C unless otherwise stated.

INPUT OFFSET VOLTAGE AND
BIAS CURRENT VS. TEMPERATURE
0(

"

5

~

4

lli

3

w

a

I

::::: ~

.........

r---...

~ 2

..........

'"

........

iii

..S

1

;5'!ao

OFFSET VOLTAGE

I

I

I

>

1
.8

~

100

E

,

g

~

I

+120

I
I

+180

8

~

80

'"
w

60

z
:;;

BIAS CURRENT - 1.2!:i

+BO

-40

OPEN LOOP FREQUENCY RESPONSE
2.0

~

4 ~
g
>

.....

\

~...

40

§

20

g

450

GAIN

PHASE ' /
1350

\

z

~

0

o

0
-1 1K

10K

lOOK

lMEG

I 600

10MEG l00MEG

2250

FREQUENCY - Hz

•

OUTPUT VOLTAGE SWING
VS.FREQUENCY

NORMALIZED AC PARAMETERS
VS. TEMPERATURE

18

fil
a:

18

~

1. I

!~

1.0

1.2

a:

~~

i""'---

ti!C

h

-

.9

/'

a:::l

f~

.8

~g

.7

0>

i
10K

,

lOOK
lMEG
FREQUENCY - H.

lDMEG

~ANOWIDTH~ ..........

~

+40

"

+90

+120

+160

TEMPERATURE - DC

l00MEG

NORMALIZED AC PARAMETERS
VS. LOAD CAPACITANCE

INPUT NOISE VOLTAGE AND
NOISE CURRENT VS. FREQUENCY

1.2

140
120

BANDWy

~

SLEWRA~

isz

90

...0~

60

w
w

40

::l

;5

200

~

-

I-

100
LOAO CAFACITANCE - pF

.

"<
,

,

..
.B

~

"-

~ 100

>

10

SLEWRA~E_

--'-.

20

,~

I,

40
35
30

~iiinT NOISE
II~

' J III1I1
v6LTAGJ~

!'...

.....

VOLTAGE NOISE SOURCE
25
/ . RESISTANCE' 5Kn
20
15
10

:--

SOURCE RESISTANCE = on
10
100

lK

FREQUENCY - Hz

10K

lOOK

w
!!!
0

Z
I-

zw
a:
a:
::l

u

I-

~

l::

PERFORMANCE CURVES (Continued)
OUTPUT VOLTAGE SWING
VS. LOAD RESISTANCE

g~

12

~

10

~

8

~

6

z

~

S

v-

w

g
5
~
o

SETTLING TIME FOR VARIOUS
OUTPUT STEP VOLTAGES

4

I

/

o

..

2.

2.5

to

w

"'

0

~o -2.5

"

>

~ -5

/

400

200

600

800

lK

:::::>

LOAD RESISTANCE - OHMS

10

20

30

40

'I -·t

'"

o

12K

f--

,/"

/"

w

I

0.5m~

I

5mV -

5

50

60

t--

70

'"

80

90

f--

100 110

SETTLING TIME - nl

COMMON MODE REJECTION RATIO
VS. FREQUENCY

POWER SUPPLY REJECTION
RATIO VS. FREQUENCY

..o

120

~'OO

0100

~0::

Z

o

~
;;J

a;

..........

80
60

t5

8

80

~

60

-

.......

>-

40

g;..J
0::

. NEGATIVE SUPPLY

20

s:

o

lK

100

10K
FREOUENCY - Hz

lOOK

lMEG

~

-tt-,

In

w

I

40

:::>
20

I 11111111

. / POSITIVE SUPPLY -

..... r-,

a;

::;
::;

z
o

t

1'--

0::

g

•

III 120

I1I1111
lK

10K
FREQUENCY - Hz

I

...
I'
lOOK

lMEG

POWER SUPPLY CURRENT
VS. TEMPERATURE
<

ur----,-----,-----.-----.----~----_,

E
, 20

ffi

~

r----

16

VSUPPLY'±I~,
VSUPPLY' ± IOV ......

tfP

="",,;::-i------+-----+-----;
"-

~ 12~--~----~-----4----_+----_+----~

~
ffi

In

~

4~--_1----_4----_4-----+----_+----~

~80

-40

-f4O

+80

+120

+180

TEMPERATURE - DC

2-137

I

APPLYING THE HA-5190/5195
1. POWER SUPPLY OECOUPLlNG: Although not absolutely
necessary, it is recommended that all power supply lines be
decoupled with .01J.LF ceramic capacitors to ground. Decoupling capacitors should be located as near to the amplifier
terminals as possible.

2. STABILITY CONSIDERATIONS: HA-5190/5195 is stable at
gains ~ 5. Gains < 5 are covered elsewhere in this data sheet.
Feedback resistors should be of carbon composition located as
near to the input terminals as possible.

4. OUTPUT SHORT CIRCUIT: HA-5190/5195 does not have

output short circuit protection. Short circuits to ground can
be tolerated for approximately 10 seconds. Short circuits to
either supply will result in immediate destruction of the dQvice.
In applications where short circuiting is possible, current limiting resistors in the supply lines are recommended.
5. HEAVY CAPACITIVE LOADS: When driving heavy capacitive loads (~100pF) a small resistor (~100n) should be connected in series with the output and inside the feedback loop.

3. WIRING CONSIDERATIONS: Video pulse circuits should be
built on'a ground plane. Minimum point to point connections
directly to the amplifier terminals should be used. When
ground planes cannot be used, good single poin"t grounding
techniques should be applied.

•

APPLICATIONS
SUGGESTED COMPENSATION FOR UNITY GAIN STABILITY
NONINVERTING

. ........
.~

1Kn*
.

.....

t~'~Fj~~..,
....

~

...

~

~

,:;*

*

R1 7:00-

1

200n

.DOn

'*'

:

"

".

OUTPUT

OUTPUT

lA
y'

,A . .
II"

INPUT

INPUT

J
Vertical Scale: (Volts: 2V/DiY.)
Horizontal Scale: (Time: 100ns/DiY.)

*

Values were determined experimentally for optimum speed and settling time.
R1 and C1 should be optimized for each particular application to ensure best overall frequency response.

INVERTING

'Kn..
'Kn
.....

I

.....

.

OUTPUT

HA~1

200n
~

'":'

*

INPUT

Vertical Scale: (Volts: 2VIDiY.)
Horizontal Scale: (SOns/DiY.)

2-138

\
.\.

I

J

APPLICATIONS (Continued)
VIDEO PULSE AMPLIFIERI15QCOAXIAL DRIVER
200n

1.6Kn

coon

VIDEO PULSE AMPLIFIER COAXIAL LINE DRIVER

•

'Kn

FAST DAC OUTPUT BUFFER
GAIN

. . w'"---l.
~15V

B*

C*
Vertical 5J:ale: (Volts: 2V/Div.l
Horizontal Scale: (Time: 50ns/Div.)
B = VOUT

C = DIGITAL INPUT

*

l,
~

Il,

..

\

•

Time delay between Band C represents total time delay for OV to +5V full scale coded change.

2-139

HA-B02l

mJHARRlS

Triple Low Power
Programmable
Operational Amplifier

Preliminary

DESCRIPTION

FEATURES

•

•

LOW INPUT OFFSET VOLTAGE (MAX)

3mV

•

LOW INPUT BIAS CURRENT (MAX)

30nA

•

WIDE POWER SUPPLY RANGE

•

INTERNALLY COMPENSATED

±2V TO ±18V

APPLICATIONS

•

BATTERY-POWERED EQUIPMENT

•

CURRENT CONTROLLED OSCILLATORS

•

ACTIVE FILTERS

•

VARIABLE ACTIVE FILTERS

PINOUT

The HA-8023-2 performance specifications are guaranteed
over the -55 0 C to +125 0 C temperature range and the
HA-8023-5 over the OOC to +75 0 C temperature range.

SCHEMATI'C
Section 11 for Packaging

QUIESCENT
CURRENT SET A
INVERTING
INPUTA
NON-INVERTING
INPUT A
NON-INVERTING
INPUT B
,OC
SUPPLY B& C

INVERTING
INPUT B
QUIESCENT
CURRENT SET B

QUIESCENT
CURRENT SET C
INVERTING
INPUT C
NON-INVERTING
INPUT C
TOP VIEW

2-140

The HA-8023 triple programmable amplifiers are internally
compensated, monolithic devices which offer a wide range
of performance characteristics that can be controlled by
adjusting the circuits' "SET" current. Each amplifier on
the chip can be adjusted independently, and by adjusting
an external resistor or current source, the electrical characteristics can be programmed to the desired levels. This
versatile adjustment capability enables the HA-8023 to
provide optimum design solutions by delivering the required
level of performance with minimum power dissipation.

SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS

(Note 1)

Voltage Between V+ and VDifferential Input Voltage
Input Voltage (Note 2)
Peak Output Current
Internal Power 0 issipation
Storage Temperature Range

±22V
±15V
±15V
Full Short Circuit Protection
300mW
-65 0 C to +150 0 C

ELECTRICAL CHARACTER ISTICS Vs =±6V, IQ =30,uA, unless otherwise specified IQ =Quiescent Supply Current
HA-B023-5
OOC to +75 0 C

HA-B023-2
-55 0 C to +125 0 C
PARAMETER

TEMP

MIN

TYP

MAX

3.0
4

3
±12

2
2
5
3
5
3
1
10
±13

MIN

TYP

MAX

UNITS

6
7.5

3
±12

2
2
5
3
5
3
1
10
±13

mV
mV
,uV 10C
nA
nA
nA
nA
Mn
V

•

INPUT CHARACTERISTICS
Offset Voltage (Note 3)
Offset Voltage Average Orift
Bias Current
Offset Current
Input Resistance
Input Voltage Range (Note 4)

+25 0 C
Full
Full
+25 0 C
Full
+25 0 C
Full
+25 0 C
+25 0 C

30
50
10
15

30
50
10
15

TRANSFER CHARACTERISTICS
large Signal Voltage Gain (Note 5)
Channel Separation (Note 6)
Common Mode Rejection Ratio (Note 7)
Unity Gain Bandwidth (Note 8)

Full
+25 0 C
+25 0 C
+25 0 C

5K

+25 0 C
Full
+25 0 C
+25 0 C
Full
+25 0 C
+25 0 C
+25 0 C

±11
±10
±12
±4
±4

70

10K
105
100
270

5K

±13
±13
±14
±5
±5
±4
3.5
2

±11
±10
±12
±4
±4

70

10K
105
100
270

VIV
dB
dB
kHz

±13
±13
±14
±5
±5
±4
3.5
2

V
V
V
V
V
rnA
kHz
Kn

700
.1
12

ns
V/,us

OUTPUT CHARACTERISTICS
Output Voltage Swing (Note 9)
Output Voltage Swing (Note 10)
Output Voltage Swing (Note 11)
Output Short Circuit Current
Full Power Bandwidth (Note 12)
Output Resistance
TRANSIENT RESPONSE (Note 13)
Rise Time
Slew Rate
Overshoot

+25 0 C
+25 0 C
+25 0 C

700
.1
12

+25 0 C
+25 0 C
+25 0 C

30
360
100

%

POWE R SUPPLY CHARACTERISTICS
Supply Current
Power Consumption (Note 14)
Power Supply Rejection Ratio (Note 15)

76

40
480
76

30
360
100

50
600

,uA
,uW
dB

2-141

NOTES
1.

2.
3.
4.
5.
6.

Absolute Maximum ratings are limiting values, applied
individually, beyond which the serviceability of the
circuit may be impaired. Functional operability under
any of these conditions is not necessarily implied.
For supply voltages Less than ±15V, the absolute
maximum input voltage is equal to the supply voltage.
RS:S;IDDKn
VS=±15V
RL = 101m
RS = IKn, f = 10kHz

7.
8.

RS :S;IDKn, VCM = ±5V DC
RL = 20Kn, VIN = 20m V
9: RL~IDKn, VS=±15V
10. RL~20Kn, Vs = ±15V
11. RL~IDKn, VS=±6V
12. RL =20Kn
13. RL = IDKn, CL = IDOpF
14. VOUT = DV, RSET = 2.7mn,
IS. VSUpp=±IV DCto±l1V DC

,-

TEST CIRCUITS
SLEW RATE AND TRANSIENT RESPONSE TEST CIRCUIT

•

L~l
-+

/1
VIN~ RSET}V_
LARGE SIGNAL RESPONSE
Vertical Scale: (Volts: A =2V1 Div., B =2V1Div.)
Horizontal Scale (Time: 50ps/Div.)

I

I

Your

F~

'''''T;

10K

"::"

SMALL SIGNAL RESPONSE
Yertical Scale; (Volts: A =20mY/Div., B =20mY/DivJ
Horizontal Scale: (Time: 5 ps/Div.)

\
QUIESCENT CURRENT SETIING RESISTOR
TDVI,","

"::-

QUIESCENT CURRENT ADJUSTMENT
QUIESCENT CURRENT TO YVs
~
±
±
±
±
±
±

2.DV
3.0V
6.DV
9.DV
12.DV
15.DV

_f-"""
I.,,'

IIlIIOIIII

10" 3~.IlA

IDpA
IM!2
2.7Mn
7.5Mn
18Mn
26Mn
32Mn

3DpA

IDDpA

275Kn
IMn
2.7Mn
6.3Mn
9Mn
12Mn

30KH
IOOKn
IODKn
270KH
270Kn
75DKn
1.8Mn 62DKn
2.7Mn 9DDKn
3.7Mn
1.2Mn

30DIlA

......-r

I
./

IMIl

,./

la"l tllJIIA
IQ-30f.llA

./

/
IlII,eu

2-142

,.- ,./

/

I'/
SUl'I'lYVOLTAGE!tVI

=

;II

HARRIS

Operational Amplifiersl Buffers

LF155 Series Monolithic
JFET Input Operational Amplifiers
LF155, LF155A, LF355; LF355A, LF355B low supply current

General Description
These are the first monolithic JFET input operational
amplifiers to incorporate well matched, high voltage
JFETs on the same chip with standard bipolar transistors.
These amplifiers feature low' input bias and offset currents, low offset voltage and offset voltage drift, coupled with offset adjust which does not degrade drift or
common·mode rejection. The devices are also designed
for high slew rate, wide bandwidth, e~tremely fast settling time, low voltage and current noise and a low 1If
noise corner.

Advantages
• Replace expensive hybrid and module FET op amps
• Rugged JFETs allow blow·out free handling compared
with MOSFET input devices
• Excellent for low noise applications using either high
. or low source impedance-very low llf corner
• Offset adjust does not degrade drift or common·mode
rejection as in most mQnolithic amplifiers
• New output stage allows use of large capacitive loads
(10,000 pF) without stability problems
• Internal compensation and large differential input
voltage capability

Applications
•
•
•
•
•

Precision high speed integrators
Fast D/A and AID converters
High impedance buffers
Wideband, low noise, low drift amplifiers
Logarithmic amplifiers

Simplified Schematic

• Photocell amplifiers
• Sample and Hold circuits

Common Features
(LF155A)
Low input bias current
Low Input Offset Current
High input impedance
Low input offset voltage
Low input offset voltage temperature
drift
• Low input noise current
• High common·mode rejection ratio
• Large dc voltage gain

30pA
3pA
10 12n

•
•
•
•
•

1 mV
3/NloC
0,01 pA/YHz

100dS
106dS

Uncommon Features
LF155A
• Extremely
fast settling
time to
0.01%
• Fast slew
rate
• Wide gain
bandwidth
• Low input
noise voltage

UNITS

J,ts

4

5
2.5

V/J,ts
MHz

20

nW/Hi.

(7)
r-------.---~-------4~--~----~----~--O+vcc

OUT

(4)

2-143

•

Absolute Maximum Ratings

LF155A

LF155

LF355B

LF355A
LF355

±22V

±22V

±22V

±18V

150'C

lSO'C

115"C

115'C

l00'C

Supply Voltage
Power Dissipation (Pd at 25'C)
and Thermal Resistance (BjA) (Note 1)
TjMAX
(H and J Package)
(N Package)
(H Package)
Pd
(J Package)
(N Package)

670mW

670mW

570mW

l00'C
570mW

BjA

150'CIW

150'CIW

150'CIW

150'CIW

Pd

670mW

670mW

570mW

570mW

BjA

140'CIW

140'CIW

140'CIW

140'CIW

Pd

500mW

SOOmW

BjA

155'CIW

155'CIW

Differential I nput Voltage

±40V

±40V

.40V

±30V

Input Voltage Range (Note 2)

±20V

.20V

±20V

±16V

Output Short Circuit Duration

Continuous

Storage Temperature Range

Continuous

Continuous

Continuous

..o5'C to +150'C

..oS'C to +150'C

..o5°C to +150'C

..o5'C to +150°C

300'C

300'C

300'C

300'C

Lead Temperature (Soldering, 10 seconds)

DC Electrical Characteristics

•

SYMBOL
Vas

(Note 3)

PARAMETER

RS: son, T A

Input Offset Voltage

MIN

=25'C

TVP

Average

TC of Input

RS

=50n

RS

=son,

MIN

MAX

1

TVP
1

2

Over Temperature
':'VOSJ6T

LF355A

LF155A

CONDITIONS

2
2.3

2.5

3

MAX

5

5

3

UNITS
mV
mV

/lVfC

Offset Voltage

':'TC/6 VOS

Change

In

Average TC

(Note 4)

0.5

(Notes 3, 51

3

/lVfC
permV

0.5

with Vas Adjust
lOS

Ti = 25'C,

Input Offset Current

IB

Input Bias Current

RIN

Input Resistance

TJ = 25'C

AVOL

Large Signal Voltage

VS=±15V,TA:25'C

30

T J = 25'C, (Notes 3, 51

50

nA

50

pA
nA

5

25
10 12

10'2
50

200

200

pA

1

n
V/mV

Va = ±10V. RL = 2k

Gain

Over Temperature

VCM

10

30

50

TJ '5 THIGH

Va

3

10
10

Tj '5THIGH

Output Voltage Swing

I nput Common-Mode

Voltage Range
CMRR

Common-Mode Rejection

PSRR

Supply Voltage Rejection

25

25

V/mV

Vs = ±15V. RL = 10k

±12

±13

±12

.,3

Vs = ±15V, RL = 2k

±10

±12

±10

±12

V

Vs = ±15V

±11

±11

+15.'
-12

V

+15.1
-12

V

V

B5

100

85

100

dB

85

100

85

100

dB

Ratio

(Note 61

Ratio

AC Electrical Characteristics
SYMBOL
SR

TA~ 25°C, Vs~ ±15V

PARAMETER
Slew Rate

CONDITIONS
AV= 1

LF155Ai355A
MIN

3

TVP

5

MAX

UNITS
V//ls
V/p.s

GBW

2.5

Gain Bandwidth

MHz

Product

ts

Settling Time to 0.01%

(Note 7)

en

Equivalent Input Noise

RS = lOOn
f= 100Hz

CIN

2-144

p.s

f= 1000Hz

25
25

EqUivalent Input

f=l00Hz

0.01

pAl$>

Noise Current

f= 1000Hz

0.01

pAl$>

Voltage

in

4

Input Capacitance

3

nW/Hz

nV/$>

pF

DC Electrical Characteristics
SYMBOL

r-

(Note 31

~

CONDITIONS

PARAMETER

MIN
VOS

Input Off.et Voltage

RS z

son, T A •

LF355B

LFI55
TVP
~,

25°C

MAX

MIN

l"VP

LF355
MAX

3

5

Average TC of Input

RS·

son

Rs'

son, (Note 4)

TV\>

3'

5
6.5

Over Temperature

I>VOSII>T

MIN

10

mV

13

mV

p.vfc

5

·5

5

UNITS
MAX

tR

fC::l.
CD

(n

Offset Voltage

I>TCII>VOS

Change in Average TC

0.5

,0.5

p.vfc

0.5

permV

with VOS Adjust
lOS

Input Offset Current

3

Tj = 25°C, (Note. 3,5)

20

18

TJ • 25°C, (Note. 3, 5)

Input Bias Current

30

RIN
AVOL

Large Signal Voltage

VS' ±15V, TA-= 25°C

Gain

Vo = ±10V, RL = 2k

50

Over Temperature

Input Common-Mode

CMRR

Common-Mode Reise-

' :zoO"

±12

100

30

200

pA

8

nA

50

Vs - ±ISV, RL - 2k

±10
±Il

200

'10,2
25

±12

,:tt3

±12

±10

$t2 .

±10

;;'2

til

.'6,J
,Qij'

85

;;6.1'

(Note 6)

160',

85

pA

n
V/mV
V/mV

t13
:t12.-

V

+15.1.
-12

V

V

:':'2'"

±10

85

100

80

:100

dB

85

'OIl,?'

80

'100 _

d8

"

Supply Voltage Rejec,

2PO

15

25

:t13
ott.?

tion Ratio

PSRR

.,30
,10,2

25

VS= ±15V, RL = 'Ok

VS= ±'5V

Voltage Range

50

5

'101~

TJ=25°C

VCM

3,

50

Input Resistance

Vo

20

nA

100

TJ:=:;THIGH

Output Voltage Swing

,3

20

Tj:=:;THIGH

V

Ratio

DC Electrical Characteristics

TA=25°C. VS=±15V
LFl55A1155.
LF355

PARAMETER

TVP

I

MAX

TYP

I

MAX

~

I

4

2

I

4

Supply Current

AC Electrical Characteristics

UNITS

I,.F355A1355B

rnA

TA = 25°C. Vs = ±15V
LFl55

SYMBOL

PARAMETER

CONDITIONS

355/355B

UNITS

VIp..
VIp..

SR

Slew Rate

GBW

Gain Ban~width
Product

to

Settling Time to 0.01%

(Note 7)

en

Equivalent I"put Noise

RS = lOon

Voltage

f-looHz

nW/HZ

f= 1000Hz

nV/VHZ

f= 100Hz

pAlVHZ

f· 1000 Hz

pAlVHZ

in

Equivalent

AV·'

I~put

Current Noise
CIN

Input Capacitance

MHz

p..

pF

2-145

II

Notes for Electrical Characteristics
Note 1: The maximum power disSipation for these devices must be derated at elevated temperatures and IS dictated by Tj!'i'AX. 0jA. and the
ambient temperature, T A. The maximum available power dissipation at any temperature is Pd = (T)MAX - TA)lOjA or the 25 C PdMAX:whichever is less.
Note 2: Unless otherwise specified the absolute maximum negative Input voltage is equal to the negative power supply voltage.

Note 3: Unless otherwise stated, these

"st conditions apply:
LF155A
LF155

Supply Voltage. Vs
TA
THIGH

LF355

±15V:S. VS:S. ±IBV

±15V:S. Vs ±20V

VS~±15V

-55°C:S. TA:S. +125°C
+125°C

O°C:S. TA:S. +70°C
+70°C

O°C:S.TA:S.+70'C
+70°C

O°C:S. TA:S. +7rfC
+70°C

and VOS. 18 and lOS are measured at VCM

•

LF355B

LF355A

±15V:S. VS:S. ±20V

= O.

Note 4: The Temperature Coefficient of the adjusted input offset voltage changes only a small amount.(O.5~V/oC ty~ically) for each mV of
adjustment from its original unadjusted value. Common-mode rejection and open loop voltage gain are also unaffected by offset adjustment.
Note 5: The Input bias currents are junction leakage currents which approximately double for every 10' C Increase in the junction temperature, T J.
Due to limited production test time, the input bias currents measured are correlated to junction temperature. In normal operation the junction
temperature rises above the ambient temperature as a result of internal power dissipation, Pd. Tj = T A + (~)JA Pd where (->JA is the thermal
resistance from junction to ambient. Use of a heat sink is recommended if input bias current is to be kept to a minimum.
Note 6: Supply Voltage Rejection is measured for both supply magnitudes increasing or decreasing simultaneously, in accordance with common
practice.
Note 7: Settling time is defined here, for a unity gain Inverter connectIon USln9 2 kn resistors for the, LF155 . It IS the time required for the error
volt8ge hhe voltage at the invertln9 input Pin on the amplifier) to settle to with," 0.01% of its final value from the time a 10V step ,"put is applied
to the inverter .

Typical DC Performance Characteristics
Curves are for LF155
Input Bias Current

'OOk

1...

I
I

10>
1k

i

.00

l/

;;

Input Bias Current
10

~:::~

r-"DVS-o:::::..,~

~

I5

D••

-51

-25

1

80

~

50

ii;

.
3

~

~

...:~
•~

i

~

±5VS~

.0

LF155

35

85

CD

r- r--lflU

.0

--

RL '2k
3G

.~..

e

.0

~

...

./
.... I--"

FIll
MTJlHEATSIIIII

I

0
5
COMMON.'IIIODE VOLTAGE IVI
-I

.0

•

TA-15°&

20

.J.- ~

Supply Current

Voltage Swing
CD

...
Ii

FRU~IR,

0
-.0

125

9S

RL -5Dk

30
20

CAsE TEMPERATURE reI

~

VS" !:15V
TA-Z5"C

10

~

~

~

L

c

.!

3

ii;

.

TC :,.;-55·C

~

V

3

~

2

il

I-- V
~

TC-Z5~C

::::~125·C
I

~

0

I

.0

15

•0

20

sumv VOLTAGE I,VI

lF155

5

.0

.5

20

SUPPLY VOLTAGE ltV)

"

Positive Common-Mode Input

Negative Current Limit
~
~

!w

e

-10

~

VS"f5V

~ t'-. i""--

\ i"'\

co
>

I;

5
co

...
!

-15

~~

i!:;

K55"C
,,\:5"C

-I '-- i - '25'r

~

.ii
ill

5

'0

1S

20

25

3Q

OUTPUT SINK tURRENT ImA)

2-146

20

.1
!!o.~

35

i

~~

T

\

.0

!i

....co"
co~

-55'C

~~

+26·C

......
~>

•

I

.0

~~

<125'C

\

.0 .1 20 2S 30 35

OUTPUT SOURCE CURRENT ImA)

/

15

lEW

5

0

/

_55°& :;TA S1ZSoC

vS"'15V

~

\

!:=

0

Voltage Limit

Positive Current Limit

)

CD

5

V
5·

V

V
.0

V

.5

POSITIVE SUPPLY VOLTS (V)

20

Typical DC Performance Characteristics

r-

(Continued)

3!

Negative Common·Mode Input
Voltage Limit

~
z

'"
iii...
"

~ t: -15
;i:!
o~

~~

-10

f--t-+~~-+--f--t

-S

hHlL-+-+-+--I----l

w~

~

"~
...

~~

~~

~==

24

en

16
12

"'"

4

-20

-15

...i"

........

20

~

-10

VS" !15V
TA·25'C

0

O'--'---'-_'---'-_~--'

-5

en
CD

2B

~~

lEw

~

Output Voltage Swing

-20 , . - - , - - , - - , - - , - - , . - - ,

V

o

1.0

NEGATIVE SUPPL V VOLTS (VI

10

OUTPUT LOAD RL (kiU

Typical AC Performance Characteristics
Gain Bandwidth

Normalized Slew Rate

I.B
LFI55

~

Vs

1.4

.1,10\;_ I-

'il ~VS'±I5V_
!"Iii~J_Vs·,zOV

I-

~ Ito.

12
1.0

II

v~. ,i5V

I

1.6

~

-+
r-

I-

I

t-"""

0.8
0.6

F F=

0.4
0.2

o

I

-55 -35 -15 5 25 45 55 85 105 125

-55 -35 -15 5

TEMPERATURE ('CI

25 45 65 85 105 125

TEMPERATURE ('CI

LF155 Sma" Signal Pulse Re.ponsa.

LF155 Large Signal Pul .. Response.

AV=+l

AV =+1

111

iii
pj

•

•
I

11
+

·11
TIME (D.5.,/0IVI

:1

Iiij

i

TIME (1 .slDlV)

2-147

Typical AC Performance Characteristics

(Continued)
Open Loop Fraquoncy
R_n..

Inverter Settling Tim.
II

TA~2!0~

i!:

ill

I

~
co

iI

III

VS" '11V

f

z

Iit~"

110

111

i
'"c

11",,/ 1/;lmV
J

,

~

-I

~

I

I.D

1.1

D

31

•

1\\.1

11111

-10

I!;

S

ImV

10mV\:

co

..=:
~..
,.

10

"

II

....

"

'I
0

-10

10

•

Power Supply Rejection Ratio
1011

I~~k

..

GAIN

50
25

I
I

D

-TS

1\

I-

;!

Ii

a

-21 ::
:II
-10 :I

~rtp'
1-'

-1111

III
11
FREQUENCY (11Hz)

I

Ico

TS
VS" 'IIV

-21

-31
-31

-121

IS

'111

!;i

II

'"co

II

a

i..
~
ii:
II:

;

2

110

..•

~
D

Ii

;

=:

•

10
10

""" "

RL on
TAoZi"C-

"

• r - sr

I.

\,.

Undlatortod Output Vol.... Swing

ZI

rrr-

•

I

!

..

~.

a
co

l

11

12

~

.

CD

~
I

I

'"

101

'II

1M

TA"2i"C
VSO±1iV-

H

•

1\

--"'\.

ZI

"lk

II

1..

I.

FREQUENCY (Hz)

Equ"""nt Input No... Vol....
I.

TA""C
Y

0

±lIV

121
110
10

r-

~

10

~,.
! •I

!Io

21

1.
1M
FREDUENCY 1Hz)

1_

11111

1k

i •

I
4
I

2-148

~

•

i51 •

~

VI" ±l1V
RL oa
TA""C
AV"'
 laUTIMAXI • RON is of SWl

If inequality not satisfied: TA '" VIN Ch
20mA

2: lV
• ";. Addition of SW2 improves accuracy by putting the voltage drop across SW1 inside the feedback
loop
• , LF155 developes full S, output capability fo, VIN

•

2-154

Overall accuracy of system determined by the accuracy of both amplifiers, A 1 and A2

Typical Applications

r

3!

(Continued)

g:

High Accuracy Sample and Hold

.,

en
CD

51k

....

+1SV

iir

o
~:""'''''-.()Vour

-15V

-ISV

•

By closing the loop through A2, the VaUT accuracy will be determined uniquely by AI.
No Vas adjust required for A2.
T A can be estimated by same considerations as previously but. because of the added
propagation delay in the feedback loop (A21 the overshoot i. not negligible.

•
•

Overall system slower than fast sample and hold

•
•

R 1, Cc: additional compensation
Use LF155 for
..

II

LowVas
High Q Sand Pa.. Filter

Cl

I"

O.OD1IJf

•
•

RI

By adding positive feedback (R21

a increases to 40
fBP = 100 kHz

&Zk

VaUT
V,N

~.::..-+-<> Your

":"

=

10000

•

Clean layout recommended

•

Response to a 1 Vp·p tone bu~st:
300,...

-15V

High Q Notch Filter
V·

>~~-<>Vour

•
•
•
•

2Rl = R = 10 M!1
2C =CI =300 pF
Capacitors should be matched to obtain high Q
fNOTCH = 120 Hz, notch = -55 dB, Q > 100
Use LF155 for
.. LowlS
.. Low supply current

2-155

co
II)

,..

U.
...I

m

HARRIS

Operational Amplifiersl Buffers

LF156 Monolithic JFET
Input Operational Amplifiers
LF 156, LF 156A, LF356,LF356A Wide Band
General Description

•

These are the first monolithic JFET input operational
amplifiers to incorporate well matched, high voltage
JF ETs on the same chip with standard bipolar transistors.
These amplifiers feature low input bias and offset currents, low offset voltage and offset voltage drift or
common-mode rejection. The devices are also designed
for high slew rate, wide bandwidth, extremely fast
settl ing time, low voltage and current noise and a low
llf noise corner.

Advantages
•
•
•
•
•
•

Replace expensive hybrid and module FET op amps
Rugged JFETs allow blow·out free handling compared
with MOSFET input devices
Excellent for low noise applications using either high
or low source impedance-very low llf corner
Offset adjust does not degrade drift or common·mode
rejection as in most monolithic amplifiers
New output stage allows use of large capacitive loads
(10,000 pF) without stability problems
Internal compensation and large differential input
voltage capability

• Photocell ampl ifiers
• Sample and Hold circuits

Features
LF156A
•
•
•
•
•

Low input bias current
Low Input Offset Current
High input impedance
Low input offset voltage
Low input offset voltage temperature
drift
• Low input noise current
• High common·mode rejection ratio
• Large dc voltage gain

LF156A
•

Extremely
fast settling
time to
0.01%

•

Fast slew
rate

Applications
•
•
•
•
•

Precision high speed integrators
Fast D/A and AID converters
High impedance buffers
Wideband, low noise, low drift amplifiers
Logarithmic amplifiers

1.5

1 mV

3p.vfc
0.01 pA/v'Hz
100dB
106dB

UNITS

p.s

10

V/p.s

• Wide gain
bandwidth

5

MHz

•

18

Low input
noise voltage

Simplified Schematic

16)
OUT

2-156

30pA
3pA
10 12.11

nV/v'Hz

r-n
....

Absolute Maximum Ratings
LM156/6A
Supply Voltage
Power Dissipation (Note 1)
TO-99 (H package)
Operating Temperature Range
TjlMAX)
Differential Input Voltage
Input Voltage Range (Note 2)
Output Short Circuit Duration
Storage Temperature Range
Lead Temperature (Soldering,
10 seconds)

±22V
670mW

SYMBOL
Vas

PARAMETER
RS=

OOC to +700 C
1000 C
±30V
±16V
Continuous
-65 0 C to 1500 C
3000 C

(Note 3)
CONDITIONS

Input Offset Voltage

Son, TA

Average TC of Input

tlTC/tl Vos

Change in Average TC

LF356A

LF156A
TYP

MIN

MAX

= 25°C

TYP

MIN

2
2.5

Over Temperature
/!J,vos/tl T

en

±18V
500mW

-55 0 C to +125 0 C
150 0 C
±40V
±20V
Continuous
-65 0 C to +150 0 C
3000 C

DC Electrical Characteristics

C1I

LF356/6A

MAX

2.5

UNITS

II

mV
mV

RS =

Son

3

5

JjV/OC

RS =

Son, INote 41

0.5

0.5

/.lV/OC
permV

Offset Vol tage
with Vas Adjust

los

Tj = 250C, INotes 3, 61

Input Offset Current

10
10

3

10

pA
nA

50
25

30

50
5

pA
nA

Tj$THIGH
IB

Input Bias Current

Tj = 250C, INotes 3, 51

30

Tj~THIGH

10 12

RIN

Input Resistance

Tj = 250C

AVOL

Large Signal Voltage

VS=±15V, TA = 25°C
VO=±10V,RL=2k

Gain

Over Temperature
Vo

VCM

50

10 12

200

50

25

n
V/mV

200

V/mV

25

Output Voltage Swing

Vs =±15V, RL = 10k
Vs = ±15V, RL = 2k

±12
±10

±13
±12

±12
±10

±13
±12

V
V

Input Common-Mode

VS=±15V

±11

±12

±11

±12

V

85

100

85

100

dB

85

100

85

100

dB

Voltage Range
CMRR

Common .. mode

Rejection Ratio
PSRR

Supply Voltage

INote 61

Rejection Ratio

AC Electrical Characteristics
SYMBOL

TA

= 250 C, Vs =± 15V

PARAMETER

LFI56A/356A

CONDITIONS
MIN

TYP

UNITS

MAX

SR

Slew Rate

8

10

V//1s

GBW

Galn .. Bandwidth

4

4.5

MHz

1.5

/1s

Product
ts

Settling Time to 0.01%

INote 71

en

EqUivalent Input Noise
Voltage

AS = lOOn
f= 100Hz
f=1000Hz

32
18

nV/'I/Ik.
nV/V'Hz'

EqUivalent Input

f=IOOHz
f = 1000 Hz

0.01
0.Q1

PA/'v'HZ
pA/YHZ

'n

CIN

Noise Current

Input Capacitance

pF

2-157

CD

Ln
,..

DC Electrical Characteristics

(Note 3)

U.

..J

PARAMETER

SYMBOL

MIN
Yos

Input Offset Voltage

RS

=

Son, TA

=

LF356

LF156

CONDITIONS

25 0

TYP

MAX

3

5
7

Over Temperature

MIN

UNITS

TYP

MAX

3

10
13

mY
mV

)lV/OC

RS = 50n

5

5

Change in Average TC
with Vas Adjust

RS

0.5

0.5

los

Input Offset Current

Tj = 25 0 C, (Notes 3, 51
Tj :;;THIGH

3

20
20

3

50
2

pA
nA

18

Input Bias Current

Tj = 250 C, (Notes 3, 5)

30

100
50

30

200
8

pA
nA

D.Vos/D. T

Average TC of Input

Offset Voltage

D.TCID. VAS

=

50n, (Note 41

Tj :;;THIGH

•

10 12

RIN

Input Resistance

Tj = 25 0 C

AVOL

Large Signal Voltage

VS=±15V,TA=250 C
Vo = ±lOV, RL = 2k

50

Over Temperature

25

Gain

YO
VCM

)lV/OC
permV

Output Yoltage Swing

YS = ±15V, RL = 10k
Vs =±15V, RL = 10k

Input Common-Mode

Vs =±15V

200

25

10 12

n

200

V/mV
V/mV

15

±17
±10
±11

±13
±12
±12

::t12
±10
±10

V
Y
V

±13
±12
±12

Voltage Range
CMRR

85

Common-Mode Rejection

100

80

100

dB

80

100

dB

Ratio

PSRR

SupplV Voltage

(Note 6)

Rejection Ratio

DC Electrical Characteristics

LF156A/156

Supply Current

SYMBOL

SR

GBW

100

TA=25°C, VS=±15V

PARAMETER

AC Electrical CharacteriStics

85

LF356A/LF356

TYP

MAX

TyP

MAX

5

7

5

10

UNITS

mA

TA = 25°C, Vs = ±"5V

PARAMETER

Slew Rate

CONDITIONS

LF156 Ay= 1

Gain-Bandwidth

LF156

LF156/LF356

MIN

TYP

7.5

10

5

UNITS

V/)ls

MHz

Product

ts
en

Settling Time to 0.01%

(Note 7)

1.5

Equivalent Input Noise

RS = lOOn
f=100Hz
f= 1000 Hz

32
18

nV/YHZ
nV/YHZ

0,01
0,01

pA/YHZ
pA/YHZ

Voltage

in

CIN

2-158

Equivalent Input
Current Noise
Input Capacitance

f= 100 Hz
f=1000Hz

3

J.Ls

pF

..

r-

"Tt

Notes for Electrical Characteristics
Note 1: The TO-99 package must be derated based on a thermal resistance of 1500 C/W junction to ambient or 45 0 C/W junction to case;
for the DIP package, the device must be derated based on thermal resistance of 1750 C/W junction to ambient.
Note 2: Unless otherwise specified the absolute maximum negative input voltage is equal to the negative power supply voltage.
Not. 3: These specifications apply for ±15V ~ Vs ~ ±20V, -55 0 C ~T A~+125ac and TH IGH = +125 0 C unless otherwise stated for
the LF156/6A. For the LF356/6A these specifications apply for Vs = ± 15V and OOC~T A ~+700C. VOS, 18 and lOS are measured at
VCM = O.
Note 4: The Temperature Coefficient of the adjusted input offset voltage changes only a small amount (0.5 j.N/ac typically) for each
mV of adjustment from its original unadjusted value. Common-mode rejection and open loop voltage gain are also unaffected by offset
adjustment.
Note 5: The input bias currents are junction leakage currents which approximately double for every 10D e increase in the junction
temperature. Tj temperature rises above the ambient temperature as a result of internal power dissipation, Pd. Tj = T A + QjA where
9jA is the thermal resistance from junction to ambient.
minimum.

Use of a heat sink is recommended if input bias current is to be kept to a

Note 6: Supply Voltage Rejection is measured for both supply magnitudes increasing or decreasing simultaneously, in accordance with
common practice.

Note 7: Settling time is defined here, for a unity gain inverter connection using 2 kl1resistors for the LF156. It is the time required
for the error voltage (the voltage at the inverting input pin on the amplifier) to settle to within 0.0% of its final value from the time a
10V step input is applied.

Typical DC Performance Characteristics
Input Bi. Current

Input Bias CUrrant
ll1G1<

l...

..

lk

u

100

::/
;;;

~

I
I

10k

z

::~:"-

~
...::~

~

1

~

~

.... •I

35

i! . .....- .....
~

..

••

•

-1'

12.

~

.I:!'"

-.

•

•

CO-a""ODE VOLTAGE (VI

"

Supply Current

v

::i
~

/

1
RL ·2k
TA"'Z5°C

20

i

.,.

_UMIAT.llt

I'""'

"

Voltage Swing

·30

",

",

31

II

4lI

'"

./

FRuL. ./

CASE TEMPERATURE rc)

a

V

RL--

51

iI

'"Ys -.,.,:!

0.1
-.5

vs • .t11V

l.-nOt

11

1--±10Y:~

10
1

•

V

V

)(!-5l.c

V

E
~,..
;;:

~

5

0

10

'"

5

'" VV

",""

4

.....

~

V

10

B

1

I.

3
2
0

20

SUPPLY VOLTAGE (±V)

lJzr
~".!.c
-I 1
II
c

15
10
20
5
SUPPLY VOLTAGE bY)

25

Positive Common-Mode Input

a

-10

~

.,~

Vs' j15V

~ :::--.

~

'"~

a

-16

i'"

-5

~

"

r-r- .tiST

15

i'"

.........

l'-.
\ ."'\

~

~

K,'5'C

. •1

-

20

-SS'C

l\r

~

25' C : \

15

20

25

30

OUTPUT SINK CURRENT (mAl

35

10

15

V

.,~

V

~~

10

/

2:::

I
5

!i "
~lll
~>

+125 D C

0

/

~.,

5

f

10

~~

B~

+25°C

E
5

rr

'\

10

\
20

25

5
30

35 40

OUTPUT SOURCE CURRENT (rnA)

/

-55"C S1AS125°C

Ys' ±1,'Y

~

5III
0

Voltage Limit

Positive Current Limit

Negative Current Limit

/
5

10

15

20

POSITIVE SUPPl Y VOLTS (V)

2-159

U1

0')

CD

It)
,..

Typical DC Performance Characteristics

La.

..J

(Continued)

Negative Common·Mode 1nput

Voltage Limit

Open Loop Voltage Gain
10M

-20
r-T1, _55lc

,
,,-

I-- TA'25°C

~
:"
~"

~

~~

TA,moC ~~

TA· _55°C

'"

1M

~

TA'25°C=

=
>

~

!il"

I

lDk
-10

-15

-20

Output Voltage Swing

..a

=

...~
~=

==

.
..=...
~
c

~ ~TA'125°C

~ lOOk

o
-5

RL =2k
RS=50

5

~

I

10

28
24

20

16
12

V
o

1.0
OUTPUT LOAD R( Ik!l)

SUPPLY VOLTAGE I,VI

NEGATIVE SUPPLY VOLTS IVI

/-

20

4

15

Vs' ;15V
TA = 25°C

Typical AC Performance Characteristics

•

Normalized Slew Rate

Gain Bandwidth
18
16

l\.

I\:

14

"

\.\.
\

1"- ......

10

~

~

0.8

~

f2aV

f"!II ~

:t1DV r-

~V

r-

..... ~

-55 -)5 -15 5 25 45 65 85 105 1n
TEMPERATURE lOCI

LF156 Small Signal Pulse Response,
AV-+l

2-160

v;-,,'5V

\

06
04

,

o

55 ·15 ·15

!i 2!i 45 65 85
TEMPERATURE (OC)

105125

LF156 Large Signal Pulse Response,
AV=+1

10

r-

Typical AC Performance Characteristics

"T1

(Continued)

•

(J1

0)

Open LOQP Frequency
Response

Inverter Settling Time

Bode Plot
15 ...........-,..."T"TTTTn--r.,--nTTT11 125

10 "
5

o

'

r---"'" f...lL I PHASE.

~ =~:
-20

t:I

fi'R,.+II!l'\..~~"""'+4+J..l.j.jl

~

t-

"rll-+-+-+-+---1

90 I-~I

~

~

25

70

~25 ~

I-'tp' -+-H~+IH
I- '1 i

15
50

-15

111

-100

IIII-++I-l-I-\lll -125

-4D

l0l--+-+--+-+-~"""+~
I

0.1

fREQUENCY ,MHz)

10

100r-...

~
0

Z

FREo.UENCY (H11

0

~
,.
,.z
0
0

0

~

,

60

Supply Voltage Rejecti on
Ratio

~

vs.Lsv

'-

"

Rl

0

>=

= 2k

~

TA= 25 11 C

"

20

.

100

Ik

~

20

"

16

...~

10k

~

.

GO

~

'0

~

20 -

lOOk

~

1M

0
100

10M

"4

...

8

z

TA

Vs

250C
+15V

I
Ik

10k

" .... I"

10M

1M

100k

Equivalent Input Noise
Voltage (Expanded Scale)

"4

100

0

80

>

60

~

...
...z
~

40

100

TA

0

Vs'

"I--- I-

:~~~-

~

I"

0
10M

~

GO

40

\

2

2

1M

I

~

~

0

FREOUENCY 1Hz)

NEGATIVE SUPPLY

~

1l1li

140

>

12

lOOk

"

" ",

0

~

10k

......
-....

Equivalent Input Noise Voltage

120

< 1%018T

•

,

FREOUENCY (HzI

~>

Vs= +15V
RL = 2k
TA = 25 0C
AV= 1

~

...

~

FREQUENCY IHI)

28

2

--

"

~

"""1\

TA'25 0C
VS:±15V-

""'-+--~,.- POSiTIVE SUPPlY80

t;

Undistorted Output Voltage Swing

~ 2'

I

100

Z

"-

40

120f":

0

"-

0
10

·10 l'~O-I:-:O:-O-:ILk-:1~Ok-:IJ,OO"'k-:"M':-"'IO!:M:--

SETTLING TIME ,.,1

Common-Mode Rejection
Ratio

"

ol--+--+-+--~+~~~~

-150

100

10

I

l--+--I......
,-!----1-+-I-","

5°!--+-+-~1~,+--4-+---1

--!-+l4N-+++H -50 ~

2k

-25
-3D 1-.
-35

110~

100

N.1l"!

-5 f - I - .

;;;

I

Vs· ±15V

20

'\.

20

~

0
1

10

100

1k

FREQUENCY (Hz)

10k

~

0
10

1k

lOOk

FREQUENCY (Hzl

2-161

CD

...
It)

Typical AC Performance Characteristics

(Continued)

LL

..J
Output Impedance

100~~~1J1
9

..
..5e

10

~

z

i

0.1

0.01
Ik

lOOk

10k

1M

10M

FREQUENCY 1Hz)

Detailed Schematic
~

BALANCE

III

•

....

151

r---,---t_---,--~r_-,---,--~_,~t__,--~----~_1r_1_~----1_--t_----_p--~~vcc
171

R18
30

t---+--o OUT 161
R19

30

~----~~---r~------+---------t-~~~--~~------+---~--~----~--~-VEE
141
121

131

Connection Diagrams

(Top Views) Section 11 for Packaging
Matal Can Package
NC

Order Number
LFI56AH
LFI56H
LF356AH
LF356H

Dual-In-Lina Package
Nt

BALANCE

INPUT -- -,

1,-,,,,,

INPUT ""::L-r-ry-

y-

OUTPUT

BALANCE

y-

Note 4: Pin 4 connected to case.

2-162

Orcler Number LF356N, LF356J.&

r-

...."T1

Application Hints
The LF156/6A series are op amps with JFET input
devices.
These JFETs have large reverse breakdown
voltages from gate to source and drain eliminating the
need for clamps across the inputs. Therefore large differential input voltages can easily be accomodated without
a large increase in input current. The maximum differential input voltage is independent of the supply
voltages. However, neither of the input voltages should
be allowed to exceed the negative supply as this will
cause large currents to flow which can result in a destroyed unit.
Exceeding the negative common-mode limit on either
input will cause a reversal of the phase to the output
and force the amplifier output to the corresponding
high or low state. Exceeding the negative common-mode
limit on both inputs will force the amplifier output to a
high state. In neither case does a latch occur since raising
the input back within the common-mode range
again puts the input stage and thus the amplifier in a
normal operating mode.

Exceeding the positive common-mode limit on a single
input wiil not change the phase of the output, however,
if both inputs exceed the limit, the output of the
amplifier will be forced to a high state.
These amplifiers will operate with the common-mode
input voltage equal to the positive supply. In fact, the
common-mode voltage can exceed the positive supply by
approximately 100 mV independent of supply voltage
and over the full operating temperature range. The
positive supply can therafore be used as a reference on
an input as, for example, in a supply current monitor
and/or limiter.
Precautions should be taken to ensure that the power
supply for the integrated circuit never becomes reversed

in polarity or that the unit is not inadvertently installed
backwards in a socket as an unlimited current surge
through the resulting forward diode within the IC could
cause fusing of the internal conductors and result in a
destroyed unit.

U1

0)

Because these amplifiers are JFET rather than MOSFET
input op amps they do not require special handling.

All of the bias currents in these amplifiers are set by FET
current sources. The drain currents for the amplifiers are
therefore essentially independent of supply voltage.

As with most amplifiers, care should be taken with lead
dress, component placement and supply decoupling in
order to ensure stability. For example, resistors from the
output to an input should be placed with the body close
to the input to minimize "pickup" 8Qd maximize the

frequency of the feedback pole by minimizing the
capacitance from the input to ground.

II

A feedback pole is craated when the feedback around
any amplifier is resistive. The parallel resistanca and
capacitance from the input of the device (usually the
inverting input! to ac ground set the frequency of the
pole. 'In many instances the fraquency of this pole is
much greater than the expected 3 dB frequency of the
closed loop gain and consequently there is negligible
effect on stability margin. However, if the feedback pole
is less than approximately six times the expected 3 dB
frequency a lead capacitor should be placed from the
output to the input of the op amp. The value of the
added capacitor should be such that the RC time constant
of this capacitor and the resistance it parallels if greater
than or equal to the original feedback pole time constant.

Typical Circuit Connections
Dnving Capacitive Loads

Vas Adjustment
v'

5k

y'

y-

•

VOS is adjusted with a 25k
potentiometer

•

The potentiometer wiper is

•

connected to V+
For potent'lometers with
temperature coefficient of

100 ppm/" C or less the
additional drift with adjust
is ~ 0.5 I'V/"C/mV of
adjustment

•

Due to a unique output stage design. these ampli·
fiers have the ability to drive large capacitive 'loads

and still maintain stability. CL(MAXI '" 0.01 I'F.
Overshoot 20%
Settlinq ti!~le (ts) == 5 IlS

:s

Typical overall drift: 5 I'V /

°c !(0.5 I'V/"C/mV of
adj.1

'

2-163

CD

It)
,..

Typical Applications

u.

..J

Settling Time Test Circuit
21<.0.1%
+15Y

1DVS.
o

•

YOUT

51<,0.1%
*1.Gk,O.1K

•
•

Settling time is tested with the LF156
connected as unity gain inverter
FET used to isolate the probe capacitance
Output = 10V step

Sk,O.I%
+1SV

OSCILLOSCOPE

0-

•

":"

":"

LargeSignellnverter Output, VOUT (fr';m Settling Time Circuit!
LF1S6

lj4/DIV

Low Drift Adjustable Voltage Refiren.e

2S~~""------I
V+=15V

•
•

~ VOUT/t. T =±O.002%/O C
All resistors and potentiometers should be
wire-bound

•

P1: drift adjust

•
•

-

R3

180k

2-164

P2: VOUT adjust
Use LF156 for
Low IS
Low drift

Typical Applications

r

."

....

(Continued)
High Accuracy Sample and Hold

01

Rl
51.

0)

+15V

+15V

>'-<...

-OVOUT

-15V

-tSV

•

•
•
•
•

By closing the loop through A2, the VOUT accuracy will be determined uniquely by AI.
No VOS adjust required for A2.
T A can be estimated bV same considerations as previously but, because of the added
propagation delay in the feedback loop (A2) the overshoot is not negligible.
Overall system slower than fast sample and hold
R1. Cc: additional compensation
Use LF156 for

...

Fast settling time

&

LowVOS

II

High Q Band Pas. Filter
Cl
O,II011'F

lpF

O.1~

Rl
62'

•
•

R6
62k

fBP = 100 kHz

VOUT
VIN

>.:........

-QVOUT

R2
300.

By adding positive feedback (R2)

a increases to 40

•

•

= ro,jO

Clean lavout recommended

Response to a 1

Vp~p

tone burst:

3001-"
-ISV

High Q Notch Fillar
V·

>'-1.--0 VOUT

•

2Rl = R = 10 Mn
2C = Cl = 300 pF

•

Capacitors should be matched to obtain high Q

•

fNOTCH

= 120 Hz, notch = -55 dB, Q > 100

2-165

CD

It)
,..

Typical Applications

(Continued)

LL.

Fast Logarithmic Con.artar

..J

"
r------....--.. . ."""-==-o
..... 'v
II.

.,IV

•

Dynamic range: 100 PA$.lj <1mA
15 decade.I, Va = II/ldacade -Transient response: 3 P5 for alii 0:::: 1 decade
e1. C2, R2, R3: added dynamir compensation

•
•

IVOUTI

~

[1

+~] ~
RT

q

In Vi

1__
R_r-]
VREF Ri

= -IQa Vi - -

.

Ri Ir

•

R2

= 1S.7k.

•

VOS adjust the LF156 to minimize quiescen~
error

•

RT: Tel Lab. type 081 + O.3%I O C

RT • 1k. o.3%fC (for temperature compensation)

Precision Current Monitor

•

Va = 5

~ IVlmA of

lSi

R2

Rl. R2. R+: 0.1% resistors
Use LFl56 for
Common-mode. range to supply voltage
Low 18

Low Vas

'0

Tlmp«8tur. Compensated 8-Bit Of A Conven.r
3-10 pF TUNE FOR MINIMUM

SETTLING TIME

EO

-ISV

o-t-----...-4-.....- ...-4>+++---.....- ...-4..........- .......J
15V
RA
15k

Use lF156 for
lM199

Fast settling time
Low Vas drift
Good stability
•
R 1- A4 : binary lad del
For BCQ weighting,
__

2-166

.J...

SINGlE POINT

":'"

GND

!

._______- - - J

RF=4k!1
RA=9k!!

Typical Applications

r-

"T1
.....
c.n

(Continued)

en
Isolating Lerge Capacitive Loads

Wide BW Low Noise, Low Drift Amplifier

.,

,......-----...--'11'''''-....-0

VOUT

01

'MAX3!!Z4QkHr

-:::~

0'

v-

~
2lrVp

•

Power BW: fMAX =

•

Parasitic input capacitance C1 ;;;5 (3 pF for

•

Overshoot 6%

•
•

ts 10"s
When driving large CL, the VOUT slew rate deter·
mined by CL and IOUT(MAX):

'" 240 kHz

" 0.02 V Ips = 0.04 V I"s (with CL shown}
0.5

LF156 plus any additional lavout capacitance)

II

interacts with feedback elements and creates
undesirable high frequency pole. To compensate
add C2 such that :R2C2a! R1C1.
Low Drift Peak Detector

I

Boosting the LF156 with a Current Amplifier
01

5., ..

.
,

VpEAIC

&,111

0,

V'N

u.
•
•

IOUT(MAX} '" 150 mA (will drive RL ~ lOOn)
IIVOUT
0.15
= 10-2 V/"s (with CL shown}

•

• ----aT

•

•

•

No additional phese shift added by the current amplifier

By adding 01 and Rf, VOl = 0 during hold mode. Leakage of
02 provided by feedback path through R•.
Leakage of circuit is essentially Ib (ILFI56} plus capacitor
leakage of Cpo
Diode 03 clamps VOUT (Alita VIN-V03 to improve speed and
to limit reverse bias of 02.
Maximum input frequency should be « 1/2lrRfC02 where
C02 is the shunt capacitanca of 02.

2-167

co

II)
,..

Typical Applications

(Continued)
High ImpedRn"", Low Drift I nstrumentation Amplifier

LL

+16V

...J
+

-R3

+16V

-l5V
R2
02

•

-'5Y

•

R3 [2R2
VOUT=R"
AI + 1] t.V,V-+2VS;VINcommon-modes;V+

•
•

System VOS adjusted via A2 VOS adjust
Trim R3 to boost up CMRR to 120 dB. Instrumentation amplifier
Resistor array RA201 (National Semiconductor; recoMmended

Fast Sample and Hold

VV

+15V

+1&V

I
I

L_

sm

VOUT

v,.

•
•

T
Acquisition time T A, estimated by:

1/2prOVidedthat:

VIN<2"SrRONChandTA>
If inequality not ..tisfied: T

•

2-168

-15V

Both amplifiers (Al, A2; have feedback loops individually closed with stable responses (overshoot negligible;
TA'" [ 2R ON,VIN,Ch)
. Sr
.

•
•

Ch

VINCh
,RONisofSWl
10UT(MAXI

'" VIN Ch
A
20mA
LFl56 developes full Sr output capability for VIN ~ lV
Addition of SW2 improves accuracy by putting the voltage drop across SWl inside the feedback
loop
Overall accuracy of system determined by the accuracy of both amplifiers, Aland A2

mHARRIS

i'
."

Operational Amplifiersl Buffers .....
en

.......

LF 157 Monolithic JFET
Input Operational Amplifiers
LF157,LF157A,LF357,LF357A
Wide Band Decompensated (AVMIN = 10)

General Description
These are among the first monolithic JFET input operational ampl ifiers to incorporate well matched, high
voltage JFETs on the same chip with standard bipolar
transistors. These ampl ifiers featu re low input bias and
offset currents, low offset voltage and offset voltage
drift, coupled with offset adjust which does not degrade
drift or common-mode rejection.

The devices are also

designed for high slew rate, wide bandwidth, extremely
fast settling time, low voltage and current noise and low
l/f noise corner.

Advantages
•
•
•
•
•
•

Replace expensive hybrid and module F ET op amps
Rugged JFETs allow blow-oilt free handling compared
with MOSFET input devices
Excellent for low noise applications using either high
or low source impedance-very low llf corner
Offset adjust does not degrade drift or common-mode
rejection as in most monolithic amplifiers
New output stage allows use of large capacitive loads
(10,000 pF) without stability problems
Internal compensation and large differential input
voltage capability

Applications
•
•
•
•
•

Precision high speed integrators
Fast D/A and AID converters
High impedance buffers
Wideband, low noise, low drift amplifiers
Logarithmic amplifiers

• Photocell amplifiers
• Sample and Hold circuits

Features
LF157A
• Low input bias current
• Low Input Offset Current
• High input impedance
• Low input offset voltage
• Low input offset voltage temperature
drift
• Low input noise current
• High common-mode rejection ratio
• Large dc voltage gain

LF157A

30pA
3pA

1012n
1 mV

3p.vfc
0.01 pA/YHz
100dB
106dB

UNITS

(AV = 10)
•

Extremely
fast settl i ng
time to
0.01%
• Fast slew
rate

1.5

50

V/p.s

• Wide gain
bandwidth

20

MHz

•

18

nV/YHz

Low input
noise voltage

Simplified Schematic

II'
OUT

2-169

•

......

.,..

II)

Absolute Maximum Ratings
LF157A

LL
..J
Supply Voltage
Power Dissipation (Note 1)
TO-99 )H package)
Operating Temperature Range

±22V
670mW

'DC Electrical Characteristics

•

Vas

PARAMETER

±18V
500mW
OQC to +70 o C
1000 C
±30V
±16V
Continuous
-650 C to +150 o C
3000 C

-55 0 C to +125 0 C
150 0 C
±40V
±20V
Continuous
-650 C to +150 o C
3000 C

(Note 31

CONDITIONS

MIN

RS=50n,TA =25 aC

Input Offset Voltage

L F357 AIL F357

±22V
670mW

-55 0 C to +125 0 C
150 0 C
±40V
±20V
Continuous
-65 0 C to +150 o C
3000 C

Tj(MAX)
Differential Input Voltage
Input Voltage Range (Note 2)
Output Short Circuit Duration
Storage Temperature Range
Lead Temperature (Soldering,
10 seconds)

SYMBOL

LF157

LF157A
MAX
TYP
I

MIN

.. 1

2
2.5

Over Temperature

LF357A
TYP
MAX
2
2.3

mV
mV

RS= 50n

3

3

Change in Average TC
with Vas Adjust

RS = 50n, INate 4)

0.5

0.5

los

Input Offset Current

Tj = 25aC, INates 3, 6)
Tj '5THIGH

3

10
10

3

10
1

pA
nA

IB

Input Bias Current

Tj' 25 aC, INates 3,5)

30

50
25

30

50
5

pA
nA

eNos/AT
ATC/AV as

Average TC of Input

Oflset Voltage

Input Resistance

Tj = 25aC

AVOL

large Signal Voltage
Gain

VS=±15V,TA=25aC
VO-±IOV, RL - 2k

50

200

50

VCM

Input Common-Mode

Vs -±15V, RL - 10k
Vs - ±1SV, RL - 2k

.±10

Vs - ±15V

±11

±12

Common-mode
Rejection Ratio

PSRR

Supply Voltage

±i3
±12

±12
±10

INate 6)

200

V/mV

±13
±12

V
V

.:!:12

V
V

±11
.:!:12

Voltage Range

CMRR

85

lao

85

lOa

dB

85

lOa

85

lao

dB

Rejection Ratio

AC Electrical Characteristics
SYMBOL

TA

= 250 C, Vs =±15V

PARAMETER

SR

Slew Rate

GBW

Gain-Bandwidth

CONDITIONS

LF157A!357A
MIN

TYP

MAX

UNITS

LFI57A: AV - 5 40

50

V/p.s

15

20

MHz
p.s

Product

ts

Settling Time to 0.01%

INate 7)

1.5

en

Equivalent Input Noise
Voltage

RS - lOOn
I - lOa Hz
I-1000Hz

32
18

nV/'t/JJi:.
nV/'ifH;

Equivalent Input
Noise Current

I - lOa Hz
I- 1000 Hz

0.Q1
0.Q1

PA/YHz'"
PA/¥HZ'

in
CIN

Input Capacitance

n

25

Over Temperature
Output Voltage Swing

p.VfOC

10 12

10 12

RIN

Vo

p.V/ac

permV

Tj~THIGH

2-170

UNITS

3

pF

DC Electrical Characteristics
SYMBOL

r

PARAMETER

RS = 50n, TA = 25a

Input Offset Voltage

LF357

LF157

CONDITIONS
MIN

Vas

UNITS

TYP

MAX

3

5
7

Over Temperature

MIN

TYP

MAX

3

10
13

Average.TC af Input
Offset Voltage

RS = 50n

5

5

IlTc/1l Vas

Change in Average TC
with Vas Adjust

RS = 50n, (Note 4)

0.5

0.5

Input Offset Current

Input Bias Current

mV
mV

INiaC
permV

Tj = 25 0 C, (Notes 3,5)

3

20
20

3

50
2

pA
nA

30

100
50

30

200
8

pA
nA

Tj ~THIGH
IB

CI1
....

INiac

Ilvas/ll T

los

....'TI

(Note 3)

Tj = 250 C, (Notes 3, 5)
Tj ~THIGH

10 12

RIN

Input Resistance

Tj = 25 0 C

AVOL

Large Signal Voltage

VS=±15V, TA = 250 C
Vo = ±10V, RL = 2k

50

Over Temperature

25

Gain

Vo

Output Voltage Swing

Vs =±15V, RL = 10k
VS=±15V,RL=10k

VCM

Input Common-Mode
Voltage Range

VS=±15V

CMRR

Common-Mode Rejection

±12
±10
±11

200

50

85

n

200

V/mV
V/mV

15
±13
±12

±12
±10
±IO

±12
85

10 12

V
V
V

±13
±12

V

:!:12

100

80

100

dB

100

80

100

dB

Ratio
PSRR

Supply Voltage Rejection
Ratio

(Note 6)

DC Electrical Characteristics

T A = 25°C, Vs = ±15V

PARAMETER

Supply Current

AC Electrical Characteristics
SYMBOL

SR

GBW

PARAMETER

Slew Rate

I LF157A/LF157

LF357A/LF357

TYP

MAX

TYP

MAX

5

7

5

10

UNITS

rnA

T A = 25°C, Vs = ± 15V

CONDITIONS

LF157: AV = 10

Gain-Bandwidth

UNITS

LF157

LF157/357

MIN

TYP

30

50

V/p.s

20

MHz

p.s

Product

Settling Time to 0.01%

(Note 7)

1:5

Equivalent Input Noise

Voltage'

RS = lOCH
f=looHz
f= 1000 Hz

32
18

nV/...;Hz"
nV/...;Hz"

in

Equivalent Input
Current Noise

f= 100Hz
f = 1000 Hz

0.01
0.01

pA/...;H;"
pA/y-H;"

CIN

Input Capacitance

ts
en

3

pF

2-171

•

.....
It)
..La.
..J

Notes for Electrical Characteristics
Note 1: The TD-99 package must be derated based on a thermal resistance of 1500 C/W junction to ambient or 450 C/W junction to case;
for the DIP package, the device must be derated based on thermal resistance of 175 0 C/W junction to ambient.
Note 2: Unless otherwise specified the absolute maximum negative input voltage is equal to the negative power supply voltage.
Note 3: These specifications apply for ±15V ~VS<±20V, -550 C 

OUT 161

R19

3.

R5
IK

RB
lK

RI.

9••

13)

Connection Diagrams

R12
18

R13
18

RI7
9 ••

(2)

Section 11 for Packaging
Metal Can Package
NC

Order Number
LF157AH
LF157H
LF357AH
LF357H

Dual·ln·Line Package
BALANCE

NC

INPUT

V'

INPUT

OUTPUT

BALANC~

V·

vNote 4: Pin 4 connected to cay,

TOP VIEW.

Order Number

LF357J-II, LF357N

TOPVIEW

2-173

,...
Application Hints

It)

,..
LL
...I

in polarity or that the unit is not inadvertently installed
backwards in a socket as an unlimited current surge
through the resulting forward diode within the IC could
cause fusing of the internal conductors and result in a
destroyed unit.

The LF157 series are op amps with JFET input devices.
These JFETs have large reverse breakdown voltages
from gate to source and drain eliminating the need for
clamps across the inputs. Tharefore large differential
input voltages can easily be accomodated without a.large
increase in input current. The maximum differential
input voltage is independent of the supply voltages.
However. neither of the input voltages should be allowed
to exceed the negative supply as this will cause IIrge
currents to flow which can result in a dest~oyed unit.

Because these amplifiers are JFET rather than MOSFET
input op amps they do not require spacial handling.
All of the bias currents in these amplifiers are set by FET
current sources. The drain currents for the amplifiers are
therefore essentially independent of supply voltage.

Exceeding the negative common-mode limit on either
input will cause a reversal of the phase to the output
and force the amplifier output to the corresponding
high or low state. Exceeding the negative common-mode
limit on both inputs will force the amplifier output to a
high state. In neither case does a latch occur since raising
the input back within the common-mode range
again puts the input stage and thus the amplifier in a
normal operating mode .

•

As with most amplifiers. care should be taken with lead
dress, component placement and supply decoupling in
order to ensure stability. For example. resistors from the
output to an input should be placed with the body close
to the input to minimize "pickup" and maximize the
frequency of the feedback pole by minimizing the
capacitance from the input to ground.
A feedback pole is created when the feedback around
any amplifier is resistive. The parallel resistance and
capacitance from the input of the device (usually the
inverting input) to ac ground set the frequency of the
pole. In many instances the frequency of this pole is
much greater than the expected 3 dB frequency of the
closed loop gain and consequently there is negligible
effect on stability margin. Howevar. if the feedback pole
is less than approximately six times the expected 3 dB
frequency a lead capacitor should be placed from the
output to the input of the op amp. The value of the
added capacitor should be such that the RC time
constant of this cap";itor and the resistance it parallels
is greater than or equal to the original feedback pole
time constant

Exceeding the positive common-mode limit on a Single
input will not change the phase of the output however,
if both inputs exceed the limit. the output of the
amplifier will be forced to a high state.
These amplifiers will operate with the common-mode
input voltage equal t\!, the positive supply. In fact. the
common-mode voltage can exceed the positive supply by
approximately 100 mV independent of supply voltage
and oyer the full operating temperature range. The
positive su pply can therefore be used as a reference on
an input as. for example. in a supply current monitor
and/or limiter.
Precautions should be taken. to ensure that the power
supply for the integrated circuit never becomes reversed

Typical Circuit Connections

'·
ffi

Vas Adjustment

, '
-

Driving

Capaci~iV8

1

!-+-=-r...,- - 1

LF157

r

_2y-1

•

LF157. A Largo Power BW Amplifier

Loads

CL(MAXI::O.Ol/JF
Overshoot

adjustment

Settling time (tsl

~ 20%

=: 5 J.i

S

I
I

v-

L':_J

Due to a unique output stage design, these
amplifiers have the ability to drive large
capacitive loads and still maintain stability.

is .. 0.5 I'VfC/mV of
Typical overall drift: 5 I'V /
'c ±(O.5 I'VfC/mV of
adj.1

~.~, ''I

IT
I _

For distortion < 1% and a 20 Vp-p VaUT
swing, power bandwidth is: 500 kHz

Typical Applications

(Continued)

.,

High Accuracy Sample and Hold

'"

+15V

+15V

:>::.........-OVOUT

-15V
-1SV

•
•

By closing the loop through A2, the VOUT accuracy will be determined uniquely by AI.
No VOS adjust required for A2.
T A can be estimated by same considerations as previously but. because of the added

•

propagation delay in the feedback loop (A2) the overshoot is not negligible.

•
•

Overall system slower than fast sample and hold
A1. Cc: additional compensation

High
CI
0.001 ~f

Q

Band Pass Filter
IpF

01
62k

Y,N

06
62k

YOUT
02
JDOk

•
•

By adding positive feedback (R2)

a increases to 40
fBP

= 100 kHz

VOUT =
VIN

roVO

•

Clean layout recommended

•

Response to a 1 Vp·p tone burst:
3001'5

2-175

......

,..

I.t)

Typical DC Performance Characteristics

(Continued)

LL

..J

Negative Common-Mocle Input
Voltage Limit
-20

1. _55l~ :.:-t-.",
r-_

r- T

,

TA - 2S'C
I
TA-125'C~~

If?

,

Open Loop Voltaga Gain
10M

~
"'-

~

~

..~

Output Voltage Swing

.

RL -211
RS-50

~
TA. _55°e

i....

1M

~
co

~

..
..

,.co

c

co lOOk

~

~

~

9

I'!

..

2'
24

16

12

~

4

-5

-10

-15

-20

10

15

20

V

o

SUPPL Y VOLTAGE I,V)

NEGATIVE SUPPLY VOLTS IV)

~

20

c

~

co

o

VS. :tliV
TA-ZSoC

1.0
OUTPUT LOAD RL Iklll

Typical AC Performance Characteristics

•

Normalized Slew Rate

Gain Bandwidth

1.8

i

l!

"....co

.
:;
.
"..
~

....

16

32

l\.
28 I\:

1.4

2

I.\.

1.0

24
20

N

1&

~

,20V ~

-

'OV
Ie::- Ir
~v -

0.6

25

-

O. 2

o

-55 ·35 -15

45 65 85 105 125

TEMPERATURE I"C)

LF157 Small Signal Pulse Response,
AV = +10

~

0.'

f"'= ====

I

-55 -35 -15 5

2-176

" .....

0.8

ii

'"

V~"±115V

\.

5 25 45 65 85
TEMPERATURE (DC)

LF151 Largo Signal Pulse Rasponse.
AV·+10

105 125

10

Typical AC Performance Characteristics

(Continued)

Open Loop Frequency

Invertar Settling Time

Bode Plot
35

~:j::;~mlm:=rrl+ml1'00
75
......

vS= .t15V

50
25

1\

'2i 151--+-+-H~lft---f.ld-H-HtH

0

itO

-25

~:t ~"

lor

~

a

:~:o!

-IOf-nr

.1,
10(\

-125

::!I- 'I r1111111

~::~

10
FREQUENCV (MHz J

w

0.1

90

~mv

.,

0

-

>
z

",

..
..~
z

c

10

,

10k

lOOk

~

f--

1M

8

:l:

4

100

10M

~
....
z

IUOk

1M

FREQUENCY {Hz!

10M

" "~
"

Ik

10k

lOOk

;;

VS"'+15V

.5

10M

~~:~~;~-

80

'"

~

80

60

w

15

z 4

60

....
z

40

:;

20

~

1M

~'0D

i

~

10k

POSITIVE SUPPl

NEGATIVE SUPPlY~

TA= 250 C

>

w

VS=±15V-

Equivalent Input Noise
Voltage (Expanded Scale)

~ 100

~

•

....

Equivalent Input Noise Voltage

.,

<1%DlST

10M

FREQUENCY 1Hz)

~120

g12
....
~

"

......

0

~

16

10k lOOk 1M
FREQUENCY 1Hz}

I"

0

~'40

TA=250 C
AV =10

Ik

TA=25 0 C

0
Ik

100

I

0

'\
100

VS=±15V
RL =21t

w

10

..........

"

0

I\.

28

~ 20

"""-

0

['I..

Undistorted Output Voltage Swing

~

·10

Power SupplV Rejection
Ratio

"-....

10

~ 24

I'

10

TA=250C -

20

,

c

VS=±15V
RL:: 2k

0

,

30

SETTLING TIME 1.,1

0

c
c

0

~

~

120

.........

,

~

\Imv

Common-Mode Rejection
Ratio
100

1'-.

70

II

JJ l\

100

~S= ±llsv-

~

TA' Z5"C

3D'
25
20

Response
110

0

\
1

~ 20

:;
;;

10

100

1k

FREOUENCY (Hz)

10k

~

0
10

"
1k

lOOk

FREQUENCY (Hz)

2-177

.....

,...It)

...u..

Typical Applications
Settling Time Test Circuit

Large Signellnverter Output, VOUT Ifrom Settling Time Circuitl

n.8.1%
+15V

s

LF157

'DY

o

Your

'!iO.O.'~

*1.ft.a.1'K

L-~'

••.,... _ +15Y

'''''DIV

•

Low Drift Adjustable Voltage Reference
•
•
•

Settling time is tested with the LF157
connected for AV = -10
FET used to isolate the probe capacitance
Output = 10V step

Non-Inverting Unity Gain Operation for LF157

Inverting Unity Gain for LF157
R2

R2

R1

=

R~~~
4

RI CI

AVIDC)= 1
L3dB

~5MHz

~

1

121T)'15 MHz)
R2

RI

4

AVIDC) =-1
f-3dS ~SMHz

2-178

m

Operational AmplifierSI Buffers

HARRIS

LF347 Wide Bandwidth Quad JFET
Input Operational Amplifier
General Description

Features
2mV
Internally trimmed offset voltage
50pA
Low input bias current
Low input noise voltage
16 nV/$z
Low input noise current
0.01 pA/"fifZ
4 MHz
Wide gain bandwidth
High slew rate
13 VIps
Low supply current
7.2 mA
High input impedance
10120
Low total harmonic distortion AV = 10,
<0.02%
RL = 10k, Vo =20 Vp·p, BW = 20 Hz-20 kHz
• Low l/f noise corner
50 Hz
• Fast settling time to 0.01%
2 ps
•
•
•
•
•
•
•
•
•

The Harris LF347 is a low cost, high speed quad JFET
input operational amplifier with an internally trimmed
input offset voltage. The device requires a low supply
current and yet maintains a large gain bandwidth product
and a fast slew rate. In addition, well matched high
voltage JFET input devices provide very low input bias
and offset currents. The LF347 is pin compatible with
the standard LM348. This feature allows designers to
immediately upgrade the overall performance of existing

LM348 and LM324 designs.
The LF347 may be used in applications such as high
speed integrators. fast D/A converters, sample-andhold circuits and many other circuits requiring low input

offset yo.tage, low input bias current, high input impedance, high slew rate and wide bandwidth. The device
has low noise and offset voltage drift.

Simplified Schematic

1/4 Quad

VCCo-------~------------._----_,

Vo

INTERNALLY
TRIMMED

INTERNALLY
TRIMMED

--------"-------I

-VEEo---~__----~__

Connection Diagram

Section 11 for Packaging
Dual·ln·Line Package

Order Number LF347N, LF347AN I
or LF347BN

Order Number LF347J, LF347AJ
or LF347BJ

TOP VIEW

2-179

Absolute Maximum Ratings
±18V
500mW
O°C to +70°C
115°C
±30V
±15V
Continuous
';5°Cto +150°C
300°C

Supply Voltage
Power Dissipation (Note 1 )
Operating Temperature Range
Tj(MAX)
Differential Input Voltage
Input Voltage Range (Note 2)
Output Short Circuit Duration (Note 3)
Storage Temperature Range
Lead Temperature (Soldering, 10 seconds)

DC Electrical Characteris.tics

(Note 4)
LF347A

SYMBOL
VOS

PARAMETER

Input Offset Voltage

CONDITIONS

MIN

1

RS' 10kn,TA" 25'C

•

TYP
3

4

':"VOS/IlT

Average TC of Input Offset
Voltage

RS" 10kn

10

lOS

Input Offset Curre"nt

Tj" 25'C, (Notes 4,51

25

100

25

200

50

50

4

TjS 70'C

Input Resistance

Tj" 25'C

AVOL

Large Signal Voltage Gain

VS' ±15V, TA" 25"C

50

5

TYP
5

100
4

25

200

50

25

± 12

±13.5

±12

±11

+15
-12

±12

±13.5

±11

+15
-12

UNITS
mV
mV
~V/'C

100 .

pA

4

nA

200

pA

8

nA

1012

100

50

10

10

1012

100

MAx
13

8

10 12

RIN

MIN

7

2

Tj" 25'C, (Notes 4, 5)

LF347
MAX

10

TjS70'C

Input Bias Current

MIN

2

Over Temperature

IB

LF3478
MAX

TYP

n

100

V/mV

Vo = ±10V, RL" 2 kn

Over Temperature
Vo

Output Voltage Swing

VCM

Input Common-Mode Voltage
Range

VS" ±15V

15

25

25

Vs = ±15V, RL = 10 kn

±11

V/mV
±13.5

V

+15

V
V

-12

CMRR

-Common-Mode Rejection Ratio

RSS10kn

80

100

80

100

70

100

d8

PSRR

Supply \(oltage Rejection Ratio

(Note 6)

80

100

80

100

70

100

dB

IS

Supply Current

7.2

AC Electrical Characteristics
SYMBOL

7.2

11

7.2

11

mA

(Note 4)
LF347A

PARAMETER
Amplifier to Amplifier CoupHng

11

CONDITIONS

MIN

TA = 25'C,
, = 1 Hz-20 kHz

TYP
120

LF347B
MAX

MIN

TYP

LF347
MAX

MIN

TYP
-120

120

MAX,

UNITS
dB

(Input Referred)
!

SR

Slew Rate

VS=±15V, TA=25'C

13

13

13

V/~s

GBW

Gain-Bandwidth Product

VS" ±15V, TA = 25°C

4

4

4

MHz

en

Equivalent Input Noise Voltage

TA = 2S'C, RS - lOOn,
I-1000Hz

16

16

16

nV/yHZ

In

Equivalent Input Noise Current

Tj

0.01

0.01

0.01

pA/yHZ

=25'C, , -

1000 Hz

Note 1: For operating at elevated temperature, the device must be derated based on a thermal resistance of 125°'C!W junction to ambient or
95'C/W junction to case,

Note 2: Unless otherwise specified the absolute maximum negative input voltage

is equal to the negative power supply voltage.

Note 3: Po max rating cannot be exceeded,
Note 4: These specifications apply for Vs

= ±15V and O'c S

T AS; +70'C. VOS, IS and lOS are measured at VCM"

0.

Note 5: The input bias currents Bre junction leakage currents which approximatelv double for every Hfc increase in the junction temperature. Tj.
Due to limited production test time, the input bias currents measured are correlated to junction temperature. In normal operation the junction
temperature rises above the ambient temperature as a result of internal power dissipation, PO. Tj = TA + 9jA Po where 9jA is the thermal resistance from junction to ambient. Use of a heat sink is recommended if input bias current is to be kept to a minimum.
Nota 6: Supply voltage rejection ratio is measured for both supply magnitudes increasing or decreasing simultaneously in accordance with common practice.

2-180

Typical Performance Characteristics
Input Bias Current

Input Bias Current

Supply Current

lk

..
...
=

!

":l

100 rVS' .15V
TA' 25'C

If ~TA~+7~"C

VCM'O
VS' .15V

e

..

10

.!

60

.

40

!!

20

ii

6.1

,/'

~

o

10

-10

!!
~2:

15

D"CS;TA$+70"C

~

..,.,. ..

V

....
.....
...

V

10

~

,,~

~>

i

..
~
:i
..,.,. .....
~~

/

.. !::

~i!
~

10

~

V

10

..

i...
~

~

i...

co

....~
..

25'C
70"C

~
:

O"C

~

10

20

30

...

4.5

i

r-....

~

'"cco
>-

..
~

15

..
i.....
~
...
..

a

ZO

,....

40

50

TEMPERATURE ('C)

60

40

VS' .15V
TA'25'C

25

V

20
15
10

I

15

ZO

0.1

~

10
RL - OUTPUT LOAD (kll)

Slew Rate

....

150

I'~S' ,'5V
I-

r-.

10 t-

15

100

RL '2k
CL=IOOpF

50

PHls~
GAIN

-10

70

30

a
10

c
co

....... .....

20

30

Bode Plot

ii:

30

10

I;

~

]

..

~

-50 ~

!l

~

VS= .15V
RL 'Zk
AV,'I

FALLING

14

"~ a

~
c
~
GO

13

.....

-

RisiNG

12

-100
-ISO

-3~

10

o

E

10

-20

o

a

Output Voltage Swing

>

20

O'C

OUTPUT SOURCE CURRENT (mA)

20

3G

I"'--

3.5

'\ 2r C
70'C

SUPPLY VOLTAGE ('V)

_
RL 'Ik
CL '100 pF-

r-.....

3

~

ZO

.....

0

v~. 'IJV

i

.."

10

30

Gain Bandwidth

•

,~

10

!;

RL 'Zk
-;'A =25'C

40

15

-ro-t...

>

0

a

ZO

>

a

OUTPUT SINK CURRENT (mA)

~

/

>

-5

.. -a

~

Voltage Swing

l..

...

15

NEGATIVE SUPPLY VOLTAGE (V)

~

~..

..
..e
~
.....
=:...

/

ZO

15

Positive Current Limit

40

-10

10

SUPPLY VOLTAGE (.V)

/
0

.....

a

70

2:

/

?!~

15

60

/

B~

10

50

15

Negative Current Limit
-15

40

O"C';;TA';;+70"C

POSITIVE SUPPLY VOLTAGE (V)

~

3D

10

.:c

o

10

Negative Common-Mode Input
Voltage Limit

:
a

5.8

./

TEMPERATURE l'C)

Pos~ive Common-Mode Input
Voltage Limit

..

6.4

~
ii:

V

4.8

o

10

-&

COMMON·MOOE VOLTAGE (V)

20

~
=
>-

~

.,/
7.1

0.1

10
FREQUENCV (MHz)

100

11
010203040

5060

70

TEMPERATURE ('C)

2-181
/

Typical Performance Characteristics

Undistorted Output Voltage
Swing

Distortion vs Frequency
0.2
0.175

..

O.IS

;::
~

vS" t15V

I.

I I I I

~IJ

~O.125

0.1

• 10.

:

~ 0.075

~w

Vo·zov• .,
'I
I
AV=IOO

..

I I

co

I

~

c;

0.050

"

ZO

>

100

10

..
I!:

1

0
10k

IZO

..
.~
.
..I.

!i

100

co

80

OJ

~
I

Ff;.Vj

60

~

w

40

'I'

3

I~

~

I

100.

co
;::

10

100

I.

§
OJ
'">-

80

~

i'
'"

10k lOOk

.

120

c

I I

0

1M

~

'"~
f

'!'..

60

10M

ZO
IK

100

w

10k

lOOk

E
w
"c

TA= 10'C

.

10

1M

!....

I

ffi

co

>

"5

~

z

co

~
10

IS

SUPPL YVOLTAGE (,VI

10
0
10

ffi

ZO

..~

10

III

/AV"~~

..
..~~
.
~

10mV

S

w

0

co

-S

>

....

10k

lOOk

FREQUENCY (Hzl

100.

1M

10M

/I

~

Vs= ,15V
TA=ZS'C

lmV

ImV

10~V

,

1

Ii

co -10

I.

10k

Inverter Settling Time

--If 1

100

I.

FREQUENCY (Hz)

1

r

0.1

100

~

AV= 10

0.01

10K
S

zo

~
c

>
;;
10M

40

~

~

....

f'

a

~AV' 100

10. lOOk 1M 10M

60

Output Impedance

I

I.

SO

30

~

TA' ZS"C

j...o-'"'

k:: V

100

10

.

co

VS2 t,5V

I!;

2-182

w

c

100

~

10

Equivalent I nput Noise
Voltage

FREQUENCY 1Hz)

TA =O"C.!!!.:Z5'C

~ tOOk

~

1"'-..
10

.

..;

~>

-SUPPLY'\

RL =Zk

c

~;;

I~+SUPPLY

"\

40

Open Loop Voltage Gain (VNI

.

~

t--.

0

1M

w

~
I

FREIlUENCY (Hz!

VS' ;ISV
TA' Z5'C

f'..

100

FREQUENCY 1Hz!

~z

I\.

0

;;; 140
:;!

RL =2.
TA=ZS'C

CMRR = ZO LOG VVO + OPEN LOOP
CM
VOL JAGE lAIN I

2Q

zo

1M

Power Supply Rejection
Ratio

Vs= t15V

I

I

~

co

~

FREDUENCY (Hz)

Ratio

co

"-

50
40

VS' 'ISVTA -25'C

~

80

co
~

z

Common-Mode Rejection

:;!

w
~

FREIlUENCY (Hz!

;;;

.
..
>

5

100.

10k

Ik

100

:;c

co

co

10

....

R~ ~2.'

r- ~

;;;

:;!

c

~

0

•

RL =2k
TA = 2S'C
AV=I
\<1110 1ST.

c

AV= 10-/-'ri

O.ozs

Open Loop Frequency Response
120

30

I I

vs= <15V
Tr Z5;C

(Continued)

0.1

~

1\\
I

SETIUNG TIME ("')

10

Pulse Response
Small Signal Inverting

Small Signal Non-Inverting

:>

:>
Ci
:;;

e>
e

e

c:o

.'"

c:o

.'"

!:!!.

!:!!.

is
en

is
en

w

w

'"....cr

Q

'"....cr

l-

...

I-

l-

::>

I-

::>

l-

IQ

>

>

...

::>

::>

Q

Q

TIME (0.2 ~s/DlV)

TIME (0.2 IlS/DIV)

Large Signal Inverting

Large Signal Non-I nverting

:>
is
:;;

:;;

:>

!:!!.

!:!!.

~

~
w

is

.'"

II

.'"

w

'"....cr

'"I-....cr

l-

Q

Q

>

>

I-

l-

...

...

::>

::>

l-

I-

Q

Q

::>

::>

TIME (2 ~sJDIV)

TIME (2 ~s/DIV)

Current Limit (RL = 100n)

TIME (5I'sJDIV)

Application Hints
The LF347 is an op amp with an internally trimmed
input offset voltage and JFET input devices. These
JFETs have large reverse breakdown voltages from gate
to source and drain eliminating the need for clamps
across the inputs. Therefore, large differential input
voltages can easily be accommodated without a large
increase in input current. The maximum differential
input voltage is independent of the supply Voltages.
However, neither of the input voltages should be allowed

to exceed the negative supply as this will cause large
currents to flow which can result in a destroyed unit.
Exceeding the negative common-mode limit on either
input will cause a reversal of the phase to the output
and force the amplifier output to the corresponding
high or low state_ Exceeding the negative common-mode
limit on both inputs will force the amplifier output to a

2-183

Application Hints

(Continued)

high state. In neither case does a latch occur since
raising the input back within the common-mode range
again puts the input stage and thus the amplifier in a
normal operating mode.

backwards in a socket as an unlimited current surge
through the resulting forward diode within the IC could
cause fusing of the internal conductors and result in a
destroyed unit.

Exceeding the positive common-mode limit on a single
input will not change the phase of the output; however,
if both inputs exceed the limit, the output of the amplifier will be forced to a high state.

Becau'se these amplifiers are JFET rather than MOSFET
input op amps they do not require special handling.

The amplifiers will operate with a common-mode input
voltage equal to the positive supply; however, the gain
bandwidth and slew rate may be decreased in this condition. When the negative common-mode voltage swings
to within 3V of the negative supply, an increase in input
offset voltage may occur.
Each amplifier is individually biased by a zener reference
which allows normal circuit operation <;m ±4V power
supplies. Supply voltages less than these may result in
lower gain bandwidth and slew rate_

II

The LF347 will drive a 2 kSl load resistance to ±10V
over the full temperature range of O°C to +70°C_ If the
amplifier is forced to drive heavier load currents, however, an increase in input offset voltage may occur on
the negative voltage swing and finally reach an active
current limit on both positive and negative swings.
Precautions should be taken to ensure that the power
supply for the integrated circuit never becomes reversed
in polarity or that the unit is not inadvertently installed

Detailed Schematic



32

~

~

"
::;

20

I

~

a

100

I

I

~

~

~

"z

.s

~

'"'".:)
;;
"

Ti' ~+70:C

1---

;;0

z

- -1

'"

a

Vs = :!:t5V
TA = 2SoC

~

20

10

10

3D

40

50

60

2.8

I
o

10

10

Positive Common-Mode Input
Voltage Limit

15

25

20

sum Y VOLTAGE (±iiI

TEMPERATURE 1"1:1

COMMON MODE VOL TAGE tV}

I------

I
2.4

-5

10

V

Negative Common-Mode Input
Voltage Limit

Positive Current Limit

20

~

15

.,""'"

15 , - , - . , - - , - , - . , - - , - - , - - - ,

~

15

~

'"
10

~

10

10

•

f---+--+-l\-1k-J\--

0-

"
.,"
~

>

o'---'-..L..-L......L-'---'_'--'
o

o

zo

10

~~~~

o

POSITIVE SUPPl Y VOL TAGE (V)

'"
~
..,

~

~

.,>~

-10

r----

I

~

"

~

.,"

i

>

;::

~

z

25°C

i

-5

~

O~

70~

I

-0

10

20

~

..'"

30

'"

ZO

~

0-

i

I--

R;-2k

"~

"

o

40

30

H~

Gain Bandwidth

~

.,'"

RL' 2k
CL -100pF

4.5

"

10

"z

:i

~

z

0-

~

.......

30

40

50

TEMPERATURE (~I

60

/ IIii , -1-ILL
~
'Iii I 1111
II1II

i-'

150

ZO

100

10

50

15

-50

- lao
-150
01

I

10

10

FREOUENCY (MHz)

100

VS"'.:t·15V
RL -Zk
AV" 1

14

i

FALLING

~'" 2:

""
~

13

~

12

~

-10

70

,

Slew Rate

30

-30

ZO

tt

,I

,

RL - OUTPUT LOAD (kill

-ZO

10

I

0.1

20

~

.............

3.5

,

f----f-J
"

10

.,"

~

.

V

VS'=.:!:ISV
TA'" 2SoC

15

"0-

~

;;0

'">
ii
"

ZO

Bode Plot

V~-il~V

~

15

'"
~
..,
~

I

10

25

.,>~

i
r----

~

SUPPLY VOLTAGE ("'I

OUTPUT SINK CURRENT (mAl

~

Output Voltage Swing
30

l

o

40

30

OUTPUT SOURCE CURRENT (mAl

i

lD

20

10

20

:ttFf-t

40

~>

!

i i

15

Voltage Swing

++

~

~

~J-~~~

10

NEGATIVE SUPPl V VOLTAGE (V)

Negative Current Limit
~ -15

__

~

-

!

RISING
f - - f----

--

11
o

10

ZO

30

40

50

60

10

TEMPERATURE <"CI

2-189

Typical Performance Characteristics

Undistorted Output Voltage
Swing

Distortion vs Frequency
30

0.2

..
i

co

VS' illV

0.175
0.15

~

.
i
..~...
..'"~
l!:

~VO'2DV'"
~
"I I
AV"DD

t; 0.al5
Ci

"':"

'l;"

I

0.025

AV"0-T'rJ

o
100

10

,.

•

120

10.

.

VCM

co

4D

::.

.
i:
..

~ + OPEN LOOP

iii

VCM

VOLTAGE GAIN

0
10

I.

100

10.

.100

5

I

CMRR' 20 LOG
20

z

co

':'

I

~

:!

2.

"='

lOOk

1M

10M

I

10

-.. "'.........

80

~ 100K

~

::;..--

o

......-:
TA'10'1:

'"'"
liI

-SUPPLY"\

I~
10

100

lK

10k

100.

SUPPLY VOLTAGE ('V)

..
..~

3D

~

20

~

10

~

0

!:;

c

so

>

40

5

...

~

10

1M

10M

r

...

AV'10

L

0.1

'"

:;!

10

20

1.

10k

10M

10k

lOOk

Inverter Settling Time

..f

10

l;

II III .IlvS",W
10mV

~V·'!,!! ~

lOOk

1M

10M

TA -2rc

lmV

~

~
~

FREQUENCY (Hz)

'(f

i

~

100

I.

100

co

,

10k 100. 1M

FREQUENCY (Hz)

,

~AV"00

I.

c

0.01

10K
IS

80

~

I

cco

'"==

~

2-190

I'..

EVS'±15V
TA'2s"C

5...

10

lO

~

Output Impedance

~

>
:l;

5

lao

co

lDO
TA' If:C TO +~n:_

~

i\.
10

Equivalent Input Noise
Voltage

Ii
~

~sUPPiY

20

RL '2.

~

"

'\

40

Open Loop Voltage Gain (VNI

co

I\..

20

FREQUENCY (Hz)

1M

.
:c
..
..
!i

i\.

40

I

-<:

FREQUENCY (Hz)

~

i\.

10

FREQUENCY IHI)

Vs '±15V
TA' ~I"c

120

;:

§2?Fvo

80

~

10

1M

100.

140

lii

RL·n
VS·.t1!SVTA·2s"c

o

o

'l!

~

~

>

Power Supply Rejection
Ratio

co

co
co

~

FREQUENCY (Hz)

'l!

..
E
::.
..
I..

...
.~

Common-Mode Rejection
Ratio
;: 100
c
z
1'0

co
~
co
c

co
~

FREQUENCY (Hz)

lii

.:c

lii

'l! 100

!:i

10

100.

10.

VS·.:!::t5V
RL' 2.
TA' 25'\:
AV·l
\

I

o.oso

20

Open Loop Frequency Response
120

~

• 10.

0.1

,

~

I

Tr25~cl

O.125

co

(Continued)

ImV

-6

co -10
8.1

10mV

II
II

k\
\\
11

SETTLING TIME ""I

.~

Pulse Response

UI
Small Signal Inverting

Small Sigrial Non-Inverting

>
co

c:,.)

>
co

>E

>E

c

c

!2

!2

'"z
i...
...'"'"co

'"z
i...

I--

I--

...'"'"co

I--

I--

>

>

:::>

:::>

a.

a.

I--

I--

:::>

:::>

co

co

TIME (o.2/lsiDIV)

TIME (O.2/ls/DIV)

Large Signal Inverting

Large Signal Non-I nverting

•

>
co

>
co

>
!2
'"z
iw'
...'"~

>
'"z
i...
...'"'"

!2

I--

co

co

>

>

I--

I--

a.

:::::>

:::>

:::>

I--

:::>

co

co

TIME~2 pS/DIV)

TIME (2 ,is/DIV)

TIME i5 PS/DIV)

Application Hints
These JFETs have large reverse breakdown voltages from
gate to source and drain eliminating the need for clamps
across the inputs. Therefore, large differential input
voltages can easily be accommodated without a large
increase in input cur(ent. The maximum differential
input voltage is independent of the supply voltages.
However, neither of the input voltages should be
allowed to exceed the negative supply as this will cause
large currents to flow whiCh can result in a destroyed
unit.

Exceeding the negative common-r:node limit on either
input ,will cause a reversal of the phase to, the output
and force 'the amplifier output to the corresponding
higl1 or low state. Exceeding the negative common-mode
limit on both inputs' will force the amplifier output to a

2-191

C")
LI')
C")

LL

...I

Application Hints

(Continued)

high state. In neither case does a latch occur since
raising the input back with in the common-mode range
again puts the input stage and thus the amplifier in a
normal operating mode.

backwards· in a socket as an unlimited current surge
through the resulting forward diode within the IC could
cause fusing of the internal conductors and result in a
destroyed unit.

Exceeding the positive common·mode limit on a single
input will not change the phase of the output; however.
if both inputs exceed the limit. the output of the ampli·
fier will be forced to a high state.

Because these amplifiers are JFET rather than MOSFET
input op amps they do not require special handling.
As with most amplifiers. care should be taken with lead
dress. component placement and supply decoupling in
order to ensure stability. For example. resistors from the
output to an input should be placed with the body close
to the input to minimize "pick·up" and (Tlaximize the
frequency of the feedback pole by minimizing the
capacitance from the input to ground.

The amplifiers will operate 'with a common·mode input
voltage equal to the positive supply; however. the gain
bandwidth and slew rate may be decreased in this condi·
tion. When the negative common·mode voltage swings
~o within 3V of the negative supply. an increase in input
offset voltage ma'! OCCllr

A feedback pole is created when the feedback around
any amplifier is resistive. The parallel resistance and
capacitance from the input of the device (usually the
inverti.ng input) to AC ground set the frequency of the
pole. In many instances the frequency of this pole is
much greater than the expected 3 dB frequency of the
closed loop gain and ~onsequently. there is negligible
effect on stability margin. However. if the feedback
pole is less than approximately 6 times the expected
3 dB frequency a lead capacitor should be placed from
the output to the input of the op amp. The value of the
added capacitor should be such that the RC time con·
stant of this capacitor and the resistance it parallels
is greater than or equal to the original feedback pole
time constant.

The amplifier is biased by a zener reference
which allows normal circuit operation on ±4V power
supplies. Supply voltages less than these may result in
lower gain bandwidth and slew rate.

•

The amplifiers will drive a 2 Hlload resistance to ±10V
over the full temperature range of O°C to +70°C. If the
amplifier is forced to drive heavier load currents. however. an increase in input offset voltage may occur on
the negative voltage swing and finally reach an active
current limit on both positive and negative swings.
Precautions should be taken to ensure that the power
supply for the integrated circuit never becomes reversed
in polarity or that the unit is not inadvertently installed

Detailed Schematic
+Vcco-~--------~------------------~-----------------------------------,

RIO

RS

1-_--+---'---I::'QI2

R5

-VCCo-~--------~------------------~

2-192

__

R5A
~_4----~--~--~--

________

_J

OUTPUT

Typical Applications

Three-Band Active Tone Control
BOOST

w

CUT

BASS

11k

J.6k

Uk

•

>~""-OOUl

+20

11111111

+15

(NOTE 21

+10

(NOTE 41
"\

11111 II
IIiVII

I-+fflIlItI--bfJItttIIH*~,~6TJ 1\

10

100

lk

10k

lOOk

FREQUENCY (Hzl

Not. 1: All controls flat.
Note 2: Bass and treble boost, mid flat.
Note 3: Bass and treble cut, mid flat.
Nota 4: Mid boost, bass and treble flat.

Note 5: Mid cut, bass and treble flat.

•

All potentiometers are linear taper

•

Use the LF347 Quad for stereo applications

2-193

Typical Applications (Continued)
Improved CMRR Instrumentation Amplifier
Vs

"'<>f+--H..:.t
R4

RS

Vo

RI

1-1 Ofi--+H

~v.

•

vs

vs'

1.

J

h h
I

I

-Vs

-Vs'
SEPARATE

2R2
AV= (

)
+1

R1

rh

R5

and ~

R4

are separate isolated grounds

Matching of R2's, R4's and R5's control CMRR
With AVT = 1400, resistor matching
•
•

~O,OI%:

CMRR = 136 dB

Very high input impedaDce
Super high CMRR'

fourth ,Order 'Low Pass Butterworth FIlter
c
0.01

RI

"&I,,kv-....JiNIt-. ._..:.t

VINo--,\'

VOUT

R3
11k

-15V

1M'
IDDk
Rl'
11k

2-194

j

-IiV

1M'
IGal

•

Corner frequency (fc) =

•
•
•
•
•

Pasiband gain (HO) = (1 + R4/R3) (1 + R4'/R3')
First stege Q & 1,31
Second stage Q = 0,541
Circuit shown uses neare.t 5% ~oler.nce resistor values for a filter with a corner frequency of 100 Hz and 8 passband gain of 100
Offset nulling neces.ary for accurate DC performance

1
R1R2CCl

Typical Applications (Continued)
Fourth Order High Pass Butterworth Filter

YOUT

j.

2.. = ; , 2"
J ~2

L

•

Corner frequency Ifc) =

•
•
•
•

Passband gain IHO) = 11 + R4/R3)(1 + R4'/R3'1
First ,tage'O = 1.31
Second .toga 0 = 0.641
Circuit shown use. clo.est 5% tolerance resistor values for a filter with a corner frequency of 1 kHz and a passba.nd gain of 10

1 2
R1R2C

•.

2..

•

Ohms to Volts Conllertlir
10M

RX

"1&V

Va

g

IV
RLADDER x Rx

2-195

Operational Amplifiersl Buffers

HARRIS
LM1081 LM308 Operational Amplifiers
General Description
The LM10B series are precision operational amplifiers having specifications a factor of ten better
than FET amplifiers over a -55 0 e to +125 0 e
It is possible to eliminate
offset adjustments, in most cases, and obtain
temperature range.

performance
amplifiers.

approaching

chopper

stabilized

The devices operate with supply voltages from +3
to :!:.20V and have sufficient supply rejection to ~e
unregulated supplies. They are fabricated using
the Harris dielectric isolation process which coupled with our unique design, makes external compensation unnecessary. Outstanding characteristics
include:

•

•

Maximum input bias current of 6.0 nA over

•
•
•
•

Offset current less than 5.5 nA over
temperature
Supply current of only 1.0 mA
Guaranteed drift characteristics
External compensation components not
required

The low current error of the LM10B series makes
possible many designs that are not practical with
conventional amplifiers. In fact, it operates from
10 M
source resistances, introducing less error
than devices like the 709 with 10 k,Q' sources.
Integrators with drifts less than 500 ,/V/sec and
analog time delays in excess of one hour can be
made using capacitors no larger than 1 J.1 F.

n

The LM10B is guaranteed from -55 0 e to +125 0 e
'
and the LM30B from ooe to +70 0 e.

temperature

Typical Applications
Standard Differential Amplifier

High Speed Amplifier with Low Drift
and Low Input Current

----,...--.:N.....--_- .m",
R~

AIf!

IIiPUT -""".........

1$1"

Sample and Hold

"

OUTfUT
t'r.HIIJI,I'GI.,.-c.yl"".

..-

""'... ION . . .

;If.neoMl!Intl
1ta1loM2....W_

2-196

..."

1501(.

r-

Absolute Maximum Ratings
LM108

3:
.....

LM308

0

Supply Voltage
Power Dissipation (Note 1)
Differential Input Current (Note 2)
Input Voltage (Note 3)
Output Short-Circuit Duration
Operating Temperature Range (LM108)

±20V
500mW
±10mA
±15V
Indefinite
-55°C to +125°C

±18V
500mW
±10mA
±15V
Irdefinite
oOe to +70 o e

Storage Temperature Range
Lead Temperature (Soldering. 10 seconds)

-u5°e to +150o e
300°C

-u5°e to +150o e
300°C

Electrical Characteristics
PARAMETER
Input Offset Voltage

S!!

r-

3:

~

0

CO

(Note 4)

CONDITIONS

MIN

Vs=.! 15V. TA=25 0C

LM10B.
TVP

MAX

MIN

LM308
TVP

MAX

UNITS

0.7

2.0

2.0

7.5

mV

Input Offset Current

0.05

4.0

0.2

4.0

nA

Input Bias Current

O.B

4.0

1.5

7

Input Resistance

10

30

50

300

Supply Current

1.0

Large Signal Voltage Gain

VOUT=.!10V,

Input Offset Voltage

VS=.!15V

RL~10kn

10

30

25

300

1.0

1.7

OOC~TA~700C

Input Offset Current

-550C"::TA~1250C

3.0

15

0.04

0.06

1.7

mA
V/mV

10

mV

6:0

30

jJV/oC

0.04

0.06

3.0

Average Temperature
Coefficient of Input Offset
Voltage

II

nA
Ml1

ILM30B)
ILM10B).

5.5

Average Temperature

5.5

nA
nAtC

Coefficient of"lnput Offset
Current

Input Bias Current

6.0

Supply Current

1.7

1.0

Large Signal Voltage Gain

VOUT=.!10V
RL ?:10 k $I

25

Output Voltage Swing

RL = 10kn

.!10

10

V/rnV

15
.!12

nA
rnA

+10

Input Voltage Range

.!12

Common-Mode Rejection

B5

100

BO

80

96

80

+12

V

100

dB

V

.!12

Ratio
Supply Voltage Rejection

96

dB

Ratio

Note 1: The maximum junction temperature ofthe LM108 is 1500 e and 85 0 e for the LM308. For operating at elevated
temperatures. devices in the TO-5 package must be derated based on a thermal resistance of 1500 CIW. junction to ambient
or 45 0 elW. junction to case. The thermal resistance of the dual-in-line package is lo00 elW. function to ambient.
Note 2: If a differential input voltage in excess of the operating supply is applied between the inputs. excessive current will flow
unless some limiting resistance is used.
Note 3: For supply voltages less than ± 15V. the absolute maximum input voltage is equal to the supply voltage.
Note 4: The device operating supply voltage range is ±3V:S VS:S±18V.

2-197

Typical Performance Characteristics

LM 108.

Drift Error

Offset Error

Input Currents

_ +4
<0:

E +3
0Z

w

II:
II:

'"
0-

-I

~

-2
-3

u

.'"

~

lDD

:il
ffi
t

18

.

t2
+1

~

-80 -40

t40

t80 +120

t160
1M

TEMPERATURE DC
INPUT RESISTANCE IIlI

Input Noise Voltage

Power Supply Rejection

•

103

100

z
CI
;:::

§

,/

102

).

80

E

1

60

~

I

It

;;:

IDDK

IK

FREQUENCY 1Hz)

Voltage Gain

..
...:c

liD

w

~

100

>

- ...

~125°C

o
2D

~

IIIIIH IIIIIIUI

00

'111m 1IIIIIm 450

"'~H~~
ANGL

900

!til"
100

11111111 1350
1111l1li. 11111111
I111III. IlIlIm

lK

10K lOOK

FREQUENCY 1Hz)

IIIIIII~III!

1M

1800

-

;; 12
;!:!

co

'-

~

c-

~

r--

z

>-

~ 1.0
>
~ 0.9

//

iil

I

0.8

.aD

-40

-

t=!r-

+40 +80 +120 +160
TEMPERATURE DC

Voltage Follower Pulse R_onse

,

ID

111111

II

...
..i...

TA' 250C
Vs '!15Y

c
!:;
~

10M

o
10K

...
lOOK

FREQUENCY

IHzl

•

~

r-

"

CI

IK

2-198

a::

Large Signal

~

10

10M

.V'.;,!15V

~
Vv.='{.Ov.\)

.

Frequency'Response

16

11111

1M

OUTPUT CURRENT limAI

Open Loop
Frequency Response

GAIN

10K lOOK

V':/f-2OV

1.1

o

SUPPLY VOLTAGE I'VI

...

!2w

TA ~ -ISoC

i'looM.

..

C 1.2

.s

",.,

1/

15

·11111

lK

Vs" 115V

T•• 125°C
TA ~ 2SJC

10

100

FREQUENCY (Hz)

1,\

....... ~C

,

10

10M

J

Power Supply Current VI.
Temperature and Supply Voltage

~. o2&Jc

5

CI

1M

Output Swing
15

II

160
;;: 140
co 120
w
co 100
~ 80
CI
60
>
4~
CI
2\J
:l 0
z -2r I
~

lOOK

FREOUENCY 1Hz)

12D

!

10K

",

TA=25 0 C
10UT"!1 mA
YS=!15Y

-"

10-2
IDK

'Ay=1

J

a:

ID L-L.LWIIL-.LIJ........J.J.
lD
100
IK

IDDM

Closed Loop Output Impedance

120

'"

IDM

INPUT RESISTANCE IIll

,

-

INPUT

\
-2

...
-8

OUTPUT

,

J

-,

1\

T.

0

~5°~:"

Ys,",.t1SV_

-8
-ID
1M

o

2D

eo

80 .0 IDIi 120140 110
TlME"~

Typical Performance Characteristics

1000

:;: 1000

'3

..s

+1

~I00~1111
~

'4r--t--+--i--1-~~~----~

1--+-+--+1 '2 "d---+--+---r
...

w

O"~ < ~fl ,"0

~

...'"
!l
...

u

-1

IIII

100

~

~~

"'"'"

r-

....ffi

~ 1°~!J.mll ".

:! 01-+--1-

~

Drift Error

Offsat Error

Input Currents

i

LM308

~~

10

~

1=
r-

~

~
:;
~

-2
-3

1.0 L-Ll.J..lJUllL-I..l.-UilJJL..l.-J-l,.WllJ
lOOK

1M

10M

1.0
1M

lOOK

100M

INPUT RESISTANCE UlJ

10M

100M

INPUT RESISTANCE InJ

TEMPERATURE DC

Input Noise Voltage

Closed Loop Output Impedance

Power Supply Rejection
120
Vs = !1~V

1000-,0.

~

~

SIfl

103

z

"

~

a:
~

il:

;;:

TA=2~OC

100

§

102

."

10 1

......z

AV·l
80
60
40

~

100

1=
::>

10-1

....
::>

20

~

J

10K

lK

100

lOOK

FREQUENCY (Hz)

Voltage Gain

10-2
lK

10K
lOOK 1M
FREQUENCY (Hz)

15

l'11I:::;r:::~
ii

.a
.~

TA

110

w

,.'"

-

~oc

k

1: = 10°C

.

==-==
K

-

~

f= lOU Hz

.s1.1
....

.....

!S
'"....
>

TA' =o'!e

1.0

t" 0,9

en

10

4

:!
S iii'100
45 0
1601111100
>.:e8D

900

g~ :820'

1350

-' CD

:si'll

0

WlW
-20 L.lillW1L
OlJJIIU
'01.J0 L.i.UIIIII}JJIWI-:i:
FREQUENCY (Hz)

TEMPERATURE

Large Signal
Fraquency Response
16

~ m

0.8 0 10 20 3D 40 50 60

OUTPUT CURRENT "~mAl

Opan Loop
Frequency Response

10

TA = 250C
VS=!15V

..

'"

..~~

~
::>

,.'"

"

o

-

lK

10K

lOOK

FREQUENCY (Hz)

INPUT

\
-2
-4

OUTPUT

I
~

TA'~5J-

Vo" '15V_

~1

...

-

~

w

I--

"-11--

i-

~

I--

~
....

70

ac

Voltage Follower
Pulse Response

111111 II

S 12
ZJ
z

V,":!:.5V

~+{~V
, - 1

II

90
10
15
SUPPLY VOLTAGE ltV)

I:;tr

V

::::0

5

10M

1.1

0::

~..

100

lK 10K lOOK 1M
FREQUENCY (Hz)

~, =1!20~

~

TA'=I~'C

~

TA '" 2S"C

100

1.2

Vs" t15V

TA ='O·C __

10

-"

TA" 2soJ
10UT":!:.1 mA
VS" :!:.ISV

Power Supply Current Vs.
Temperature and Supply Voltage

Output Swing

lID

~

10

10M

'Ay'

/

"

-20
100

•

/

-8
-10

1M

I I
20 40 60 80 100 lID 140 160
TIME ,.,)

2-199

Schematic Diagram
(0
w

•

I-I
2

INVERTING
INPUT

Typical Applications (Continued)
Sample end Hold

F.st t Summing Amplifier
<51

INPUT

..

10.OT-"III,.......- - - - - - - - -...--I
OUTPUT

tt.tIOR,poIylttlyllMllf
pllyclfbon....illtctrlc

........

WentClU.rih
Inttbln2.limVl..:

OUTPUT

-'n •• litiont8illCfllli.. " •
• LM1G1AI'IiSIt ..iIh .......
~pi .. i ___ OIItpIt
. . . capbility ....linainltn

:t: C5 .. ~·~rr'

tIIennIl'....... .

Connection Diagrams

Section 11 for Packaging

Metal C.n P.ck.ge

Du.I·I,.. ... I... Pack.ge

OFFSET
ADJUST
INPUT-

OffSET
ADJUST

-----'+--1"

INPUT+

y.

OUtPUT

OPTIONAL

y-

v-

Standard Differential Amplifier

OFFSET
ADJUST

TOPVIEW

TQPVIEW

Order Number LM108H

LM30BH

*Pin connections shown on
schematic diagram are for

TO-5 and Dual-In-Line Package

2-200

Order Number LM108J-B.
LM30BJ-B
Order Number LM30BN

VOUT

Ell HARRIS

Operational Amplifiersl Buffers

LM 108A/LM308A Operational Amplifiers
•

General Description
The

LM I 08A/308A series are precision opera-

tional

amplifiers

having

specifications

about

a

factor of ten better than FET amplifiers over
their operating temperature range.

In addition ro

low input currents, these devices have e)(tremely

low offset voltage, making it possible to eliminate
offset adjustments, in· most cases, and obtain
performance
approaching
chopper stabilized
ampl iliers,
The devices operate with supply voltages from
.:!:3V to .:!: 18V and have sufficient supply rejection
to use unregulated supplies. They are fabricated
using the Harris dielectric isolation process which
coupled with our unique design makes external
compensation unnecessary.
Outstanding characteristics include:

•

Offset voltage guaranteed less than 0.2fmV

•
•

Maximum input bias current of 4.0 nA over
temperature
Offset current less than 4.0 nA over temperature

Supply current of "nly 1 mA

•

Guaranteed .6 iJ.V/oe drift

•

External compensation components not re-

quired
The low current error of the LM108A series makes
possible many designs that are not practical with
comventional amplifiers, In fact, it operated from
10M 51
source resistances, introducing less error
than devices like the 709 with 10 k51 sources. Integrators with drifts less than 500 ~ VIsec and analog
time delays in excess of one hour can be made
using capacitors no larger than 1 pF.

•

The LM308A devices have slightly relaced specifications and performance guaranteed over a ooe
to 700 e temperature range.

Typical Characteristics
Standard Differential Amplifier

I--"'II\"'""-....,

-',. -'IM......

High Speed Amplifier with L._ Dri.ft
and L_ Input Current

.~.

".-'IM,....,.H

'.

"
---"I"""---r

INPUT - " "..........- - - -.....

lSOK

15011:

DD2,f

Sampl. and Hold

INPUT

.'
IIOK
OUTPUT

tyIlID •.• al,lth.,..nlO'
'DlyclrblllUl•••• lectrll:
CltllCHg,

Wonl_II'"
InI!hllnUmV11IC

2-201

LM108A
Absolute Maximum Ratings
Supply Voltage
Power Dissipation (Notl' 1)
Differential Input Current (Note 2)
Input Voltage (Note 3)
Output Short·Circuit Duration
Operating Temperature Range lM10BA
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)

Electrical Characteristics
PARAMETER
Input Offset Voltage

•

±20V
500mW'
±10mA
±15V
Indefinite
-55·C to 125·C
_65· C to 150·C
300·C

(Note 4)

CONDITIONS

MIN

Vs= .:!:15V, TA = 250 C

TVP

MAX

UNITS

.01

.025

mV
nA

Input Offset Current

0.05

2.0

Input Bias Curr~nJ

0.8

2.0

10

Input 'Resistance
Supply Current
Large Signal Voltage Gain

30
1.0

"OUT

1.7

mA

= ±10V, R L ;;:': 10 kH
120

Input Offset Voltage

Vs=.:!:15V

Average Temperature
Coefficient of Input
Offset Voltage

-550C::"TA~+1250C

dB

140
.06

.4

.6

mV

p.V/·C

Input' Offset Current

4.0

nA

Average Te'mperature
Coefficient of Input
Offset Current

.04

nAloe

Input Bias C\lrrent

4.0

nA

1.7

mA

Supply Current
Large Signal Voltage Gain

Output Voltage Swing

1.0
VOUT=.:!:10V
RL~10k:n

120

RL = 10kn

.:!:10

dB

.:!: 12

V
V

Input Voltage Range

.:!:12

Common Mode Rejection
Ratio

106

120

dB

Supply Voltage Rejection
Ratio

100

130

dB

,
Note 1: The maximum junction temperature of the LM10BA is 150o C. For operating at elevated temperatures,
devices in the TO-5 package must be derated based on a thermal resistance of 150oC/W. junction to ambient, or
45 DC/W, junction to case. The thermal resistance of the dual-in-line package is 10QoC/W. junction to ambient.
Note 2: If a differential input voltage in excess of the aerating supply is applied b~tween the inputs. excessive
current will flow unless some limiting resistance is used.

Note 3: For supply voltages less than ±.15V, the absolute maximum input voltage is equal to the supply voltage.
Nots 4: The device operating supply voltage range is .:!:.3V ~ Vs::,.:!:.18V.

2-202

nA
MH

LM308A
Absolute Maximum Ratings
Supply Voltage
Power Dissipation (Note I)
Differential Input Current (Note 2)
Input Voltage (Note 3)
Output Short-Circuit Duration
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering. 10 sec)

Electrical Characteristics
PARAMETER
Input Offset Voltage
Input

Offs~t

±18V

500mW
±IOmA
±15V

Indefinite
O°C to 70°C
_65°C to 150°C
300°C

(Note 4)
CONDITIONS

MIN

Vs = ±15V. TA = 25 0 C

Current

Input Bias Current

TYP

MAX

.01

.025

mV

0.2

2.0

nA

1.5

2.0

Input Resistance

30

Supply Current

1.0

Large Signal Voltage Gain

VOUT = ±IOV. RL

Input Offset Voltage

Vs=±15V

LM308A

~IO

k!l

120

UNITS

nA

1.7

mA

140

dB

.06

OOC~:.TA::'+700C

II

Mn

mV

Average Temperature Coefficient
of Input Offset Voltage
LM30BA

.4

Supply Current

1.0

Input Offset Current
Average Temperature Coefficient

/lV/OC

.6

1.7

mA

4.0

nA

0.04

nAloe

of Input Offset Current
4

Input Bias Current
Large Signal Voltage Gain

\lOUT=±10V

nA

120

dB

RL~IOkn

Output Voltage Swing

i

RL=10kn

V

+10

.:t 12

Input Voltage Range

+12

Common-Mode Rejection Ratio

106

120

Supply Voltage Rejection Ratio

100

130

-

V

dB

dB

Note 1::. The maximum junction termperature of the LM30BA, LM30B-l, and LM308~2 is 85 0 C. For operating at elevated temperatures, devices in
the TO-5 package must be derated based on a thermal resistance of 150 oC/W, junction to ambient, or 450 C/W. junction to case. The thermal
resistance of the dual-in-line package is lOQoe/W, junction to ambient.
Note 2: If a differential input voltage in excess of the operating supply is applied between the inputs, excessive current will flow unless some limiting resistance is used.
Note 3: For supply voltages less than ,:t15V, the absolute maximum input voltage is equal to the supply voltage.
Note 4; The device operating supply voltage range is .±3V ~ Vs -=:.:!:.18V.

2-203

Application Hints
A very low drift amplifier poses some uncommon
application and testing problems. Many sources of
error can cause the apparent circuit drift to be
much higher than would be predicted.
Thermocouple effects caused by temperature grad·
ient across dissimilar metals are perhaps the worst
offenders. Only a few degrees gradient can cause
hundreds of microvolts of error. The two places
this shows up, generally, are the package-to print·
ed circuit board interface and temperature gradients
across resistors. Keeping ,package leads short and
the two input leads close together help greatly.
Resistor choice as well as physical placement is
important for minimizing thermocouple effects,
Carbon, oxide film and some metal film resistors
can cause large thermocouple errors. Wirewound
resistors of evenohm or manganin are best since
they only generate about 2 IlV fc referenced to
copper. Of course, keeping the resistor ends at
the same temperature is important. Generally, shielding a low drift stage electrically and
thermally will yield good results.

•

Resistors can cause other errors besides gradient
generated voltages. If the gain setting resistors do
not track with temperature a gain error will result.
For example a gain of 1000 amplifier with a con-

Suggested Connections for Offset Nulling

stant 10 mV input will have a' 10V output. If the
resistors mistrack by 0.5% over the operating .temperature range, the error at the output is 50 mV.
Referred to input, this is a 50 IlV error. All of the
gain fixing resistor should be the same material.
Offset balancing the LM308A is not a problem
since there is an easy offset adjustment incorporated into the circuit, This adjustment can
be accomplished by simply using the circuit
given below.
In addition to the suggested offset nulling
method, th is adjustment can also be done at
the input by employing one of the three commonly used circuits shown.
Testing low drift amplifiers is also difficult. Standard drift testing technique such as/heating the'
device in an oven and having the leads available
through a connector, thermoprobe, or the soldering iron method - do not work. Thermal gradients
cause much greater errors than the amplifier drift.
Coupling microvolt signal through connectors is
especially bad' since the temperature difference
across the connector can be 50°C or more. The
c;levice under test along with the gain setting resistor should be isothermal. The following circuit
will yield good results if well constructed.

For Non-Inverting Amplifiers

For Inverting Amplifiers

+v

IN

> - : - - - { ) OUT

..."

-v
• Although Rp IS shown equal to 2Ok. other values such as
SOk, 1ook. and 1M may be used. Range of adjustment is
approximately +2.5mV. VOSTC of the amplifier IS not

compromised. -

Drift Measurement Circuit

Offset Adiustment for Differential Amplifiers

...

."
2-204

RI-R3+M

...., •.v(:I) (.f.!",)
GAIN.;f

Schematic Diagram *
CD
·V

•

1-1
2

INVERTING

INPUT

*·Pin connections shown on schematic diagram refer to TO-5 and Dual-In-line Package

Connection Diagrams

Section 11 for Packaging

Metal Can Package

Dual-In-Line-Package

ADJUST
INPUT-

v'

IL..II""-

INPUT+

v-

OUTPUT

Ii

v-

TOP VIEW
Drder Number LM108AH,

OPTIONAL
OFFSET
ADJUST

TOP VIEW

LM308AH
Order Number LM108AJ-6
LM308AJ-8
Order Number LM308AN

2-205

HARRIS

Operational Amplifiers/Buffers·

LM1181LM318 Operational Amplifiers
General Description
The LM118 series are precision high speed operational
amplifiers designed for applications requiring ~ide band~
width and high slew rate. They feature a factor of ten
increase in speed over general purpose devices IJI!ithout
sacrificing DC performance.
Fabricated using the Harris process which, coupled with
our unique design, affords a morEf predictable dynamic
performance.

Features
•
•
•
•
•
•

•

15 MHz small signal bandwidth
Guaranteed 50V I J1 s slew rate
Maximum bias current of 250 nA
Operates from supplies of .:!:.5V to .:!:.20V
I nternal frequency compensation
Pin compatible with general purpose op amps.

The LM118 series has internal unity gain frequency
compensation. This considerably simplifies its application
;ince no extern'al components are necessary for operation.
Howerver. unlike most internally compensated amplifiers, external frequency compensation may be added
for optimum performance. Overcompensation can be
used with the amplifier for greater stability when maximum bandwidth is not needed. Further, a single capacitor
can be added to reduce the 0.1% settling time to under
300ns if required.
The high speed and fast settling time of these op amps
make them useful in AID converters, -oscillators, active
filters, sample and hold circuits, or general purpose
amplifiers. These devices are easy to apply and offer an
order of magnitude better AC performance than industry
standards such as the LM709 .
The LM318 is identical to the LM118 except that the
LM318 has its performance specified over a Doe to
+70 0 e temperature range.

Schematic and Connection Diagrams

Section 11 for Packaging
Metal Can Pack.,.-

'Pln connections shown on schematic diagram
and typical applications are for TO:S package.
Order Number LMllSH,
or LM31SH

2-206

-'B,·.
Dual·ln·Line Package

orN/C

...".

I

'

II"

I",

I

•

itumrr

".

~

•

_

"'IMC~

Order Number LMllSJ-S,
or LM31BJ-B
Order Number LM31SN

Absolute Maximum Ratings
+20V
500mW
,:15V

Supply Voltage
Power Dissipation (Note 1)
Diffentntial Input Current (Note 2)
Output Short-Circuit Duration (Note 4)
Operating Temperature Range
LM118
LM318

Storage Temperature Range
Lead Temperature (Soldering, 10 seconds)

Electrical Characteristics
PARAMETER

Indefinite
-55 0 C to +125 0 C
DoC to +70 o C
-65 0 C to +1500 C
3000 C

(Note 5)

MIN
Input Offset Voltoge
Input Offset Current

Unless Otherwise
Specified: Vs ~ ;t15V
TA = +250 C

Input Bias Current

Input Resistance

LM318

LM118

CONDITIONS

I

Supply Current

TYP

MAX

MIN

TYP

UNITS
MAX

2

4

5

10

mV

6

50

30

200

nA

120

250

150

500

nA

3
5

0.5
B

3
6

M

HI

mA

Large Signal Voltoge Gain (Note 6)

VOUT = ;tIOV, RL~ 2kr!

12

15

10

15

V/mV

Slew Rate

AV= I

60

70

60

70

VI,""

Small Signal Bandwidth
Input Offset Voltage
I"put Offset Cu rrent

15
Unless Otherwise
Specified: Vs ~ ;t15V
-55 0 CSTAS+125 0 C (LMIIB)
OOC~TA ~+700C (LM3IB)

Input Bias Current
TA = +125 0 C

Large Signal Voltage Gain (Note 6)

VOUT= ;tIOV, RL~.2kr!

Output Voltage Swing

RL = 2kr!

4.5

6

15

mV

100

300

nA

;t10

4S

6

;t13

;t10

750

nA

6

mA
V/mV

8

8

MHz

15

500

Supply Current

II

;t13

Input Voltage Range

V
V

Common-Mode Rejection Ratio

80

100

70

100

dB

Supply Voltoge Rejection Ratio

70

80

65

80

dB

Not. 1: The maximum junction temperature of the LMI181s 1500 C and the LM318 Is 850 C. For operating at eleveted temperatures, devices
in the TO-5 package'must be derated. based on a thermal resistance of 150 o CIW. junction to ambient, or 450 cIW. junction to case.
The thermal resistance of the dual-In-line packagelsl00 0 CIW, junction to ambient.
Note 2: If a differential Input voltage In excess of the operating supplV voltage Is applied betw-een the Input, excessive current wil1 flow unless
some limiting resistance Is used.
Note 3: For supplV voltages less than.:!:. 1SV. the absolute maximum Input voltage is equal to the supply voltage.
Nota 4: LM118/LM318 can withstand continuous shorts to ground or either supply rail. However, good practice is to avoid exceeding the
maximum junction temperature rating of the device, whJth could cause the circuit to be damaged.
Not. 5: These specifications apply for .:!:.15V :!: Vs ::': .:!:.20V and -55 0 C::: TA ::: +1250 C, (LMI18), and OOC ~ TA::': +700 C (LM31B). Also,
power supplies must be bypassed with 0.1 }J. F disc capacitors.
Not. 6: In practically all applications the specified open loop voltage gain will be sufficient. In unusual applications requiring"minimized loop
gain errors, external adjustments may be necessary.

2-207

Typical Performance Characteristics
Input Current

LMl18
Power Supply Rejection

Voltage Gain

zoo

100

~ ,.!!AS

1511
100

1

i.

i110 r- ~s-Ic........ T.·ZS'C

so
0

~

OFFSET

~

~ lDO

I
o
-55 -3S -IS 5

85

25 45 IS 15 lOS IZ5

5

TEMPERATURE I C,

IAput Noise Vo'itoge

•

!z

1000

-,

100

~

~300

ID

.:;!

100

"

B ~11!a
30

40

co

10

..
I!
I!

10

Ef:jjlllllf::fl:
100

co
I!
z
co

lk

1'"

.

""'"
~

iI
co

5

III'

e
"co

10· t

5

-

AV'- 1000

-

10.2

10-3

10

100

~

iE

i

i!

'"~
!z

:iI

!!
c
to

..
.

22

II
14

l - I---

... V

Ik

10k

lOOk

1M

10M

5

IS

10

ZO

SUPPLY VOLTAGE "V,

Input Current

.
-=...

140,

_120

ill
a:

100
80

ea: 60
...

"e
"

4
.. 2

~

!!
12

10k

lOOk

I

16

1M

Vo'tage Follower Slaw Rate
130

I

.... r---::'~ J"': ttr--- ,. . . ,:::::t-.
i"'

liD

110

'5V

Vs-'IO~_

.......

r-... ::--:~

,...
r-..
r-..

t:

10

~

100

~

80

r- r-p~Sli'VE ~LJ

I-'"

10

,.....

..

~

S
,.

NEGATIVE SLEW
Vs· ilSV
Rs=Rf"'DkU

rt-+-..

TEMPERATURE I'C'

TEMPERATURE I"CI

I

1

!,omv
003

IOmV

rl

l00mV

-10

-15

-55 -35 -15 S 25 45 55 15 IDS 125

!

~

J .,

C,·SpF
-55 -35 -IS 5 IS 45 IS 85 lOS 125

'-rif,Ii,

10Z

~

80
10

....

Inverter Setthng Time

"

, 10

I

2-208

T•• 125~
4.&

FREQUENCY 1Hz!

Vs "' 'SV
II

I

~

~

I""""
'":: I""""T.-25-C-

V"""

£l

~ 6

I:::::: ~s· 'IOV

'

18

10M

V

Ik

I

10

T.'~

.! 5.8

8

Unity Gain Bandwidth
24

.
..~
.

C

2,10

'"Z

"'"

:

Rs~2kn

F"'I-+--+-ok:+---

12

1M

Supply Current

Output Current

r--

IIHIk

FREQUENCY IH.,

14

TA =25 C

10k

Ik

FREQUENCY 1Hz!

V
~ V
" VAv:y

10'

100

4.0

100

Vs= '1SV

,''

~

T.-15C_

\

FREQUENCY IH.,

Closed Loop O~tput
Impedance

'-

n.

-zo

o

lOOk

10k

SU~

5.S

50

~

10

NEGATIVE

Common Mode Rejection
128

3

Zl

T. 'f5'C '

~SITlliE SUPPLY

SUPPLY VOLTAGE I'V,

3000

!

~

zo

15

10

10

i. ..

CD

I

"'
fi

co

105 I--T.-IZSoC

:

..

80 ~

!

~

;...

10

£l
5

Vs - ,15V

1 mV

lmV

Typical Performance Characteristics

Open Loop Frequency
Response

Large Signal Frequency

Response
14
12

~

100

!z

\

'"

~
I£

C

'"
'"<
!:;
,."

1\

"

Voltage Follower Pulse
Ro.ponse
20

T!'25!C

BO

I\-

60

2M

5M

10M 20M

:! ~

135

!=

1J:

~ i-"
\

40

90
45

20
GAIN"

10

50M

100

FREQUENCY lHzl

lk

~

I

H_l

I

12

~~-M-

I

6

1\

'"

i

INPU~-

w

i !:;'"<
I ",.

II-OUTPUT

II

\

II

~

-8
-12

"'

-20

0.5M 1M

110

PHASE /

I I

16

2Z5

Vr"~V-

w

I;

o

-

120

T. ~ 2Jc1
V,· ,15V

\

10

z

LM118, (Continued)

VS"

-16
-20
-D.2

10k lOOk 1M 10M IUcr.c

t1SV

TA ,"2Sg

0.2

1.0

O.S

FREQUENCY (Hz!

C'-

1.4

1.8

TIME (••1

II
Typical Performance Characteristics

BIAS

!100

;;; 110 1--+-,1r--+--I--+-~

~

=--.11

" r::Jj~e:~~~~~::J

SO

ill

~

~ 105

~ 40
I£ 3D
i! 20

~

I--+-+--+--t--+-~

"::;

..;;J
t

80

TA °25'C

~,

..... ~~SITIVE SUPPLY

60
40

NEGATIVE

I

20

SU~

I'.

f\

iJ!

~

1
1

o

10

20

3D

40

50

60

95 L--.J._-'-_-'-_'--'-_-'
10
15
5
20

70

TEMPERATURE (OCI

1000

~ 300

~IOO~II~~I
30

"

.
""::;
;;J
..
w

""
'"
""'"

'"

8

120

-

100

\

40
20

10k

11I0I0

100

lOOk

0

0

~

~

1M

---

~I( k""

I\.

60

i.

T.,25·C_

~

80

10k

""

10M

Supply Current
5.5

Rs= 2 kSl

I--

.-

~''''<\o25t\

'\,..

o
Ik

FREQUENCY (Hzl

lk

FREQUENCY (H.I

Common Mode Rejection

Input Noise Voltage

100

-20
100

SUPPL Y VOLTAGE ('VI

3000

c;

!z
>

",. 100

OFfSET

10

o

100

115 . - - , - - . . . , - . - . . - - . . . , - ,

160

..

Power Supply Rejection

Voltage Gain

Input Current

200

l-

LM318

TA

i

10 C

4.0
lk

10k

lOOk

FREQUENCY lH.1

1M

10M

5

10

15

20

SUPPL Y VOLTAGE (,VI

2-209

Typical Performance Characteristics
Closed Loop Output Impedance
10'

....

'"
u

10'

"

i

10"

::
"

5

10- 1

~

.

10-2

Current Limiting

TA=25'C

--

Avl"OOO

~

\J

I--

~

/

12

~

V

&00

""-

..

..::..
"

10k

lOOk

1M

•

o

10

16

90

60

12

10
20

30

50

40

20

30

40

50

Large Signal Frequency

Open Loop Frequency

Response

Response
A ;

I

.
..

\

~

\

o
2M

5M

10M 20M

50M

">
5
::
""

to-

~

60

~

60

60

j

40

">

20

I

I 8D

-10

C,=IOpF
C..,'O.I.F
0.03

12

:! ~

~

:: I
"'

..ii
.."

1: "'

10k lOOk 1M 10M 100M

FREQUENCY 1Hz)

I10i~

0.1

0.3

I I
I I

16

I 36 '"

GAIN'\

1k

ImV

Rs=5kn

Voltage Follower Pulse
Response

\

100

~

TIME I."

" K' --10

I mV

R,'5kU lIJOjV

10

PHASE /

co
!:;

V,·,'5V
TA'25°C
-6

-IS

TA• 25!C
V," '15V- 225

-20
FREQUENCY IHzl

~

20

f--.

~

4

0.5M 1M

100

vs" '15V

\

co

~

120

T 2i d

~ 10

2-210

10

-

TEMPERATURE rCI

12

~

o

19

NEGATIVE SLEW

TEMPERATURE I CI

14

g

60

....

loor

~

C,"5pF

14

10

.

I

10~V

I

10

Hs'" R,·10 Kn

>

0.2 0.4 0.6 0.8

Inverter Settling TIme

r-

110

0

DIFFERENTIAL INPUT IVI

V,.I"6V

0

25

15
PQSITIVE SLEW

1---+-+--+..
~;f

"

20

Voltage Follower Slew Rate

:l

lie

15

120

~ 100

~

1

-&00
-0.8 -D.& -0.4 -0.2

OUTPUT CURRENT ImAI

" 18
iii

.."
..
.....

\

Vs= !15V

Unit Gain Bandwidth

...'"

-"
-400

./

22 r-...,--r-...,--,r-...,--r--,
20

\

-

TA'25'C

FREQUENCY IHzl

~

-

TA =10'C

...iii

Ay=·Y
V

Ik

400

S- ID

o
100

Input Current

14

Vs =Q5V

10'

LM318 (Continued)

~

6

-

4
0
-4

'1\
\

I

I I

H.I

~~-~

INPUT- II-OUTPUT

I

II

!:;
co -I

>

-12

V," '15V
TA=25C-

-16
-%0

-o.z

0.2

0.6

1.0

TIME 1.,1

1.4

I.'

~
....
....

Auxiliary Circuits

CO

.......

r-

s:w
....
CO

tSlaw In. R,ding

tim' 10 O.,,,f.,r.
10Vst.pcblllp
illDOrIJ.

Offset Balancing
Compensation for fJlinimum

Settling t Time

~.
~

"

Isolating Large Capacitive Loads

II

Overcompensation

Typical Applications

/

Fast Voltage Follower

Fast Summing Amplifier

...,-,

Differential Amplifier

'""

,...

.
"

11

I"'U~-"""-+---I->M.""-",....!j
~,

,

,,- -\

___

_ _ 61" I

INPUT

OUtpUIZINO.
"OK

"

-Tura

+ "X"nro

:t. Flillsufeadiulf.

Four Quadrant Multiplier

2-211

"

Typical Applications (Continued)

IlpF

aY"UT

I.'UT ....__.....,

OUTPUT

IAMPU

DIA Converter Using Ladder Network

Fast Sample and Hold

.'

•

". ............----+--""'.....

IN'U'.....W

-""io-aUTPUT

OUT'UT

D/A Conver••r ..,Iing Binary Weighted Network
Fast Summing Amplifier
with Low Input Current

...0'
>,'-+--OUTPUT

,"

.••

III

Wein Bridge Sine Wave Oscillator

2-212

Instrumentation Amplifier

:II HARRIS

r-

s::
Operational Ampl ifiersl Buffers .....
.....
(X)

LM 118A/LM318A Operational Amplifiers
General Description
The LM118A series are preCision high speed operational
amplifiers designed for applications requiring predictable
wide bandwidth and high slew rate. They feature sim Uar
performance criteria to the LM118 while offering lower
power requirements.

Features
•
•
•
•
•
•
•

15 MHz small signal bandwidth
Guaranteed SOVI /.15 slew rate
Maximum bias current of 250 nA
Operates from supplies of ,:t5V to .:t20V
Internal frequency compensation
Pin compatible with general purpose op amps
Need better process term

The LM118A series provides internal unity gain frequency
compensation. This coupled with the Harris 01 process
and a unique design, simplifies lM118's application since
no external compensation components are necessary.
However, compensation may be added for applications
where greater stability is required.
Further. a single
capacitor can be added to reduce the 0.1% settling time
to under 300 os if required.

»
'-..
rs::
w

.....
(X)

»

LMl18A's high speed, fast settling time, and ease of use is
ideally suited for AID cOnverters, oscillators. active filters.
sample and hold circuits. or general purpose amplifiers.
These devices offer a superior predictable AC performance
to industry standards such as LM709.
LM31BA is identical to the LMllBA except that the
LM318A has its performance specified over a DOC to
+700 C temperature range.

II

Schematic and Connection Diagrams

Section 11 for Packaging
Metal Can Package'

Dual·ln·Line Package

Comp.orN/C
1A1J1:0MP-,,

·Pin connections shown on schematic diagram
and typical applications are for TO·5 package.
Order Number LMllBH
or LM31BH

• Camp. or NIC

Order Number LMllBJ-B
Or LM31BJ-B
Order Number 31BN

2-213

~
.,..
~
..J
""«
co

Absolute Maximum Ratings
Supply Voltage
Power Dissipation (Note 1)
Differential Input Current (Note 2)
Input Voltage (Note 3)
Output Short-Circuit Duration (Note 4)
Operating Temperature Range
LM118A
LM318A
Storage Temperature Range
Lead Temperature (Soldering, 10 seconds)

.,..
.,..

:e
..J

Electrical Characteristics

+20V
500mW
-+10mA
+15V
Indefinite
-550C to +125 0 C
OOC to +70o C
-65 0 C to +150 o C
300 0 C

(Note 5)

PARAMETER

LM118A

CONDITIONS
MIN

11

Input Offset Voltage

Input Offset Current

Unless Otherwise
Specified. Vs = :':.'5V
TA = +25 0 C

Input Bias Current
50

I nput ReSistance

TVP

MIN

TVP

UNITS
MAX

1

3

5

8

mV

10

25

20

50

nA

100

200

125

250

nA

40

100
4

Supply Current

LM318A
MAX

100
4

6

Mli

6

mA

Large SIgnal Voltage Gam (Note 61

VOUT= :':.'0V, RL~2~1!

15

20

12

15

V/mV

Slew Rate

AV = 1

65

70

65

70

Vip'

12

MHz

Small Signal Bandwidth
Input Offset Voltage

12
Unless Otherwise

Specified. Vs
Input Offset Current

~

5

12

mV

50

100

nA

400

500

nA

6

rnA

:!: 15V

-550C::;:TA~+1250C

OOC~TA::::+700C

(LM1181
(LM3181

Input BIas Current
Supply Current

TA = +125 0 C

Large Signal Voltage Gain (Note 6)

VOUT= :':.10V,RL~2kl!

Output Voltage SWing

RL = 2kl!

4

"
10

+10

6

V/mV

10

+13

+10

:':.13

+10

+10

Input Voltage Range

4

V
V

Common-Mode ReJection RatiO

SO

90

74

90

dB

Supply Voltage ReJection Ratio

SO

90

74

90

dB

Note 1: The maximum junction temperature of the LM118A i, 1500 C, and the LM318A i, 85 0 C, For operating at elevated temperature"
devices in the TQ-5 package must be derated based on a thermal resistance of 150 0 C/W, junction to ambient, or 45 0 C/W, junction to case. For
the flat package, the derating is based on a thenmal resistance of 185 0 C/W when mounted on a 1/16·inch-thick epoxy glass board with ten.
0.03.inch.wide,.2-ounce copper conductors.
The thermal resistance of the dual-in-line package is 1000 C/W, iunction to ambient.
Note 2: If a differential input voltage in excess of the operating supply voltage is applied between the inputs. excessive current will flow

unless some limiting resistance is used.
Note 3: For supply voltages less than ± 15V, the absolute maximum input voltage is equal to the supply voltage.
Note 4: LM118A/LM31BA can withstand continuous shorts to the ground or either supply rail. However, good practice is to avoid exceeding

the maximum junction temperature rating of the device, which could cause the circuit to be damaged.

:s

Note 5: These specifications apply for ±5V ~ Vs
±20V and -55 0 C ~ T A:S +1250 C, (LMllSAl and OOC ~TA '5. +70 0C (LM318A). Also,
power supplies must be bypassed with 0.1 JlF dISC capacitors.
Note 6: In practically all applications the specified open loop voltage gain will be sufficient. In unusual applications requiring minimized

loop gain errors, external adjustments may be necessary.

2-214

r

Typical Performance Characteristics
Input Bias and Offset Current
vs Temperature

Open Loop Voltage Gain
vs Temperature

of'..t-..

I

100

a:

B +2 0 .......
0

--

-2 0
-50 -25

....

5

k':: k

'"
<

'l!

I--'" r-

1'/ r"-- I' VSUPPL y. :!:20V

"'B 0

1'"00

..

80 ~

r-,--,-

-a +6 0

....
0
15+4
a:

CIASICUR~ENT

VSUPPLY =:!:15V

l' VSUPPL v= :!:10V

OFFSET CUR1ENT

.

5

o

-:10 -25
-55

0 +25 +50 +75 +100 +125
TEMPERATURE DC

+25

+50

is

60

.

40

~
,.

;:

l--

T.·25"1:

NEGATIVESU~

;;:

I.

+75 +100 +125

-20
100

TEMPERATUREOC

z

,~

~

~Slf
;
§!;1.0.E!

80
60

TA=2SOC-

~

10k

1k

100k

1M

"z
"~

~

40

1

O. IL...eL.l.JJlllllL....J....L.LJlj""':....L..J...JJ~~.L..L~~.

20

4.4

r--r--r-"'-.-,--r. .---,

4.2

f--'--'-.......J.-:-::;::':-+--t--t,

~

.. 3.41-+-~+-f--t--Ir--t-....,

32L-¥_5-0~_2~5~0--+2~5-+~5-0~~~5~+I~OO~+~125
-55

100

10k

Ik

•

~ 3.6roE::::j;~~1"'9---1--r1

o

100Hz

10M

~ 3.8

~

._--t---

0

'"

~4.0

0
0

_........'.nn

~

~

r--

0

:10.II1II

1.\.1

Rs '" 2 k!!

100

»

Power Supply Current
vs Temperature

120

~

00
~

Common Mode Rejection

>

s::

....w

n.

20

II:

r

~OSITIVE SUPPLY

FREQUENCV (Hz!

Equivalent Input Noise
vs Bandwidth

....
»
........
00

Power Supply Rejection

90

+10 0
+B

s::
....

LM118A

lOOk

1M

TEMPERATURE DC

10M

FREQUENCY IHd

Closed Loop Output
Impedance

Output Current

10' r--,---,..--..,...-;-;--=~

i

10'

J---+-.-+

10'

,"",=i--.t-"'7'i-

~

10'
10 '

15 •
10k

lOOk

-

"

·f, [-~ ;

100

~

!
i

I

~

80 --t

B

60

I

t

t

:-4-+--......-T
+

1

i

1M

Normalized AC Parameters
vs Temperature

20

30
40
50
60
10
OUTPUT CURRENT (mA)

·8
-4
0
DifFERENTIAL INPUT (V)

Normalized AC Parameters
vs Temperature
u1.1

1

~!C

Sl~W

.l! "

tl'·D

f"'\

II
10

RATE

~

I
I
0'"

i=>

">

~:;;D.9
c ...

z::;

II:

-50 -25
0 +25 .50 +15 +100 +125
-55
TEMPERATURE DC

~

"'0

,,>

D.8

III

·&0
-55

25

0 +25 +50 +15 +100 +125
TEMPeRATURE DC

"

I

100~

E

........

c~

LC

12

16

Inverter Settling Time
1~

11

~;:

... +

BANDWIDTH

t""-- .....

J

I

I

FREOUENCY (H,)

9

t·- ;--. ; "

I.

10

r--- ~

1

~-+--+--+-+--+

~

~ 6
~

lie.

T-T -,-r-}"
I '

140

~ 10

~ 10° f--f---"c'I-.--t---:--"':~"1

100

Input Current

-',-,--,--

120

!

~

14

~

-~

I

10~V
ImV

lmV

IOOjVI\
-10

1'0Im~

-15
0.03

0.1

0.3
TIME (,..,!

2-215

Typical Performance Characteristics

LM318A (Continued)
Voltage Follower Puhe
Response

Output Voltage Swing
Frequencv at +25 0 C

VI

~

20
16

5roTrrmrTrm-v-SU-~-L-Y-·~i2='OV~mrTT

~ 30Htm1lk'RtIllltt--++

~~ 2D~
25·~:mI:E~~U

~

i

~

vlllll\l1.~l~~1 ~

ill...

-4

~>

-8

iil.l1JITI WY--,I-,-,III.lllW-III...L.UlJlllL-.w.

• I-.L.I

,,"

::;:

lOOk

1MEG

. -OUTPUT

I

II

-12

-16
-20
-0.2

tOMEG

FREQUENCY Hz

I

. ~-~

lNPU~-

\

w

~ 10 ~:mt:+!:m!l-U
., 5

1\

~

~ 15 VSUPPLV'" :!:1SV

H

I
I

12

~::~~~~.0.2

0.6

1.0

1.4

1.8

TIME Ips)

Open Loop Frequency and
Pha.e Response

•

iii 120

'"z 100 ~ml
~
~

~

80

0

II

3

III II

6

III

PHASE

60

9

~

~ 40
g 20

r..

~

~

0
0_20
10

1
1
1soo

r-..
100

lK

10K

lOOK

1M

10M

100M

FREQUENCY Hz

Typical Performance Characteristics

Open Loop Voltage Gain
Temperature

Input Bias and Offset Currant
VI

LM318A

Temperature

Power Supply Rejection

VI

100

90 .---,--.- -,---,--,---r--,-"

.--r--r--.---,r--,

z

60 ~--+-~~.--4r--4-

~

40

"

'"~
t

20

a
.29 '---'---''---'----''---'----''---'
-50 ·25 0 +25 +50 +75 +100 +125
TEMPERATURE DC

·25

0 +25

+50 +75 +100,125

TH1PERATUREDC

-20 L-_.1-_.1-_.1-_'--.....J
100

1k

10k

lOOk

1M

10M

FREQUENCY IHzl

Equivalent Input Noise
VI

120 ~--.--...,...--r--'r---'

~

100

"t;

so

'"

60

~
z

40

~

20 ~-+---+---+

z

;;:

1---1;;;;;;::+---+-

li

2-216

'IS

Temperature

4.4 r--r--.-,--.-.,.---r--.--,
4.2 f---'--'---'I VSUPPL Y • :t20V
VSUPPLY =:t15VVSUPPL Y = :tlOV

~4.0
,
~ 3.8

r

~ 3.6r-~~~:t:::::or91-+-+--1

Q

0.1'-""::..w..wuL...l...il
100Hz
1K Hz
10K Hz
lOOK Hz
LOWER 3dB FREUUENCY ·10Hz

Power Supply Currant

Common Mode Rejection

Bandwidth

'"' 3.4

lMHz
FREQUENCY 1Hz!

32L-~~~~~~-L~~

·50 ·25
+25 +50 +75 +100 +125
·55
TEMPERATURE DC

Typical Performance Characteristics
Closed Loop Output Impedance

LM318A (Continued)
Input Currant

Output CUrrent

10'

,---r--....---,--=,---,

•

10'

1--+--+-+-":""":--'-1

%

14

Vsa!I5V

u

~ t--.

•

'\

8

TA = 125DC

6

10'

1k

10k

tOOk

1M

'l\

1\\

10

%0

Normalized AC Parameters
vs Temperature

",N

w

+

~~

."''''
....
w'"

~ ~ 1.0
~

",>

r--.

-

50

60

10

80

90

-16

-12

.,.

Normalized AC Parameters
Tamperature
~1. 1
VI

-I..
4.
DIffERENTIAL INPUT (V)

",N

SLfW RATE

."''''
....

:if31.0

r--... .......

I"'-

~

c>
We

I' ~:;;
"w

D.9

~

O.8

ew
"''''
z ...

"'w
"''''
z ...

• 50 ·25 0 +25 +50 +15 +100 +125
·55
TEMPERATURE DC

,.

10 '-

0

. 25

0

y

lmVt-

1\'

100r~

TEMPeRATURE DC

1 mVr----

I

IlOi~ ~I

+25 +50 +75 +100 +125 .15
0 OJ

01

TEMPERATURE I C)

TEMPERATURE I C)

10~V

i

1007

·10

&0
·55

16

I'

·5

::;'"

::;'"

.1I ~.
-+

10

.......

12

I"verter Settling Tima
15

"'=

w+
w ..

BANDWIDTH

:!.. 6w 0.9
~ O.B

40

OUTPUT CURRENT (mAl

FREQUENCY 1Hz)

~ ~ 1.1

3D

~i"

• /~
.1 (
.il

\\

%

•
•
•

1.\

•

1--+--+·-,.4100

TA'"'+25 DC

•

11

O.J
TIME ("'s)

Voltage Follower Pulse
Response

Output Voltage Swing
Frequency at +25 0 C

lIS

20

I

16

H

12

r -1'V+-

t-

~

1\

'"z

INPUT--j h-OUTPUT

,

il
11

\

~

:!'"

·4

c:>

.

...\

·8
·12
-16

FREQUENCY Hz

;

I i
IJ
11

~-

:

r-'

... Vs::' 15V

I TA

co

2S"C

·20
-02

02

0.6

10

14

18

TIME",,}

Open Loop Frequency and

Phase Response
~ 120

z100

·u~

,...,LII

II ,III II

I

i

0

I

3

~

80

~

60

~

40

~

20

1

0
c -20

1

1111 II

6

PHASE

1

~

10

100

,.

....
10K

100.

1M

10M

FREQUENCY Hz

2-217

II

'-+--OU"'.IT
"

.

,"'..

-GlIB'

2DDK

A.

10.1 SK

R,::. ZOOK

Cl" C2

f .. 211

~2 Cl

Wein Bridge Sine Wave Oscillator

Instrumentation Amplifier

2-219

mHARRIS

Operational Amplifiersl Buffers

LM1431LM343 High Voltage Operational Amplifier
Features

General Description

•

The LM143 is a general purpose high voltage operational
amplifier featuring operation to ±40V, complete input
overvoltage protection up to ±40V and input currents
comparable to those of other super·p op amps. Increased
slew rate, together with higher common·mode and sup·
ply rejection, insure improved performance at high sup·
ply voltages. Operating characteristics, in particular
supply current, slew rate and gain,. are virtually inde·
pendent of supply voltage and temperature. Furthermore,
gain is unaffected by output loading' at high supply vol·
tages due to thermal symmetry on the die. The LM 143
is pin compatible with general purpose op amps and has
offset nUll. capability.
Application. areas include those of general purpose op
amps, but can be extended to higher voltages and higher
OUtput power when externally boosted. For example,
when used in audio power applications, the LM143 pro·
vides a power bandwidth that covers the entire audio
spectrum. In addition, the LM143 can be reliably
operated in environments with large overvoltage spikes
on the power supplies, where other internally·compen·
sated op amps would suffer catastrophic failure.
The LM343 is similar to the LM143 for applications in
less severe supply voltage and temperature environments.

Connection Diagrams

• Wide supply voltage range
•

±4.0V to ±40V

Large output voltage swing

±37V

• Wide input common·mode range
•

±38V

Input overvoltage protection

Full ±40V

• Supply current is virtually independent of supply
voltage and temperature

Unique Characteristics
•

Low input bias current

•

Low input offset current

10.0 nA
3.0nA

• High slew rate-essentially independent
of temperature and supply voltage
• High voltage gain-virtually independent
of resistive loading, temperatiJre, and
supply voltage

• Output short circuit protection
• Pin compatible with general purpose op amps

Metal Can Package
Dual-I n- Line-Package
OFFSET
NUll

COMP DR NC

INPUT
INVERTING
INPUT

V'

,
INPUT

v·

OUTPUT
4

OFFSET
NUll

Y'

TOP VIEW
TO' VIEW

Order Number LM143H
or LM343H

2-220

lOOk min

• ·Internally compensated for unity gain

Section 11 for Packaging

COMPENSATION
OR
NC

2.5V/p.s

Order Number LM143J

or LM343J. LM343N

Absolute Maximum Ratings

(Note 11

Supply Voltage
Power Dissipation (Note 11
Differential Input Voltage (Note 2)
Input Voltage (Note 2)
Operating Temperature Range
Storage Temperature Range
Olltput Short Circuit Duration
Lead Temperature (Soldering. 10 seconds)

LM143

LM343

±40V
680mW

±34V
680mW

BOV

S8V

±40V

±34V

oOe to +70°C
---u5°C to +150·C
5 seconds
300°C

-55·e to +125°C
--il5°C to +150°C
5 seconds
300°C

Electrical Characteristics
PARAMETER
Input Offset Voltage
Input Offset Current
Input Bias Current

CONDITIONS

LM143
MIN

Vs =:!: 28V
TA = 2S o C,
UNLESS OTHERWISE
SPECIFIED

Supply Voltage
Rejection Ratio

TYP

LM343
MAX

MIN

TYP

MAX

UNITS

2.0

5.0

2.0

B.O

mV

3.0

12.0

3.0

30.0

nA

10.0

2S.0

12.0

40

10

100

10

200

Output Voltage Swing

RL::!: S k

22

25

20

25

large Signal Voltage
Gain

VOUT= 10V,
RL2: 1OOk

lOOk

lBOk

70k

lBOk

Common·Mode
Rejection Ratio

80

90

70

90

Input Voltage Range

24

26

22

26

Supply Current

2.8

Short Circuit Current

20

4.0

2.8

V
VIV
dB
V
5.0

rnA

20

rnA

Siew Rate

AV = 1

2.5

2.5

V/p.s

Power Bandwidth

VOUT = 40 Vp p,
RL=SkTHD2:1%

20k

20k

Hz

Unity Gain Frequency

TA = 25·C

1.0M

Input Offset Voltage

TA
TA

Input Offset Current

TA
TA

Input Bias Current

TA
TA

large Signal Voltage
Gain

RL ::!: 100 kl1
RL ::!: 100 kl1

50k
50k

150k
220k

50k
50k

150k
220k

Output Voltage Swing

RL ::!: S.O k 11
,RI. 2: S.O kl1

22
22

26
25

20
20

26
25

= Max
= Min
= Max
=Min
=Max
=Min

(Note 31

1.0M
6.0
6.0

II

nA
p.VIV

Hz
10
10

mV
mV

O.B
4.0

4.5
3S.0

O.B
4.0

14
SO.O

nA
nA

5.0
16

35
SO.O

5.0
16

55
55

nA
nA
VIV
VIV
V
V

Note 1: Absolute maximum ratings are not necessarily concurrent, and care must be taken not to exceed the maximum junction temperature of

the LM143 (150·CI or the LM343 (l00·CI. For operating at elevated temperatures, devices in the TO·S package must be derated besed on a
thermal resistance of 150·CIW, junction to ambient, or 45·CIW, junction to case. The thermal resistance of the dual-in-line package is 10rfCIW,
junction to ambient.
Note 2: For supply voltage tess than ±40V for the LM143 and less than ±34V for the LM343, the absolute maximum input voltage is equal to the

supply voltaae,

Not. 3: For the LM143, -ssoe

SJ A ~ +125 0 e and for the

LM343, ooe

~T A ~ 70 o e,

2-221

Schematic Diagram

a8ANDWlDTH

r-------_,----,_----~~--_,----,_--~~_r--~r__,_r----_r----------~~~--_,----,_07V.

R"

013

6Vour

•
~--_1________+_~------------~----------_i-1~+-----~~-1--+---+--+--+-----~--~~.v.

31Nt

TRIM

llN-

Typical Performance Characteristics
Input Voltage Range

~w

.....
.
..

/

c

.

i..
"'

.....'"
..~

10

!:;

!:;

i

120

:;
.!J

/

30

c

w

100

L

3D

..
..'"
..

0;

:!!

10

ylj'C
o

10

20

10

T. -25'C R, '100kn_

20

o

o

10

20

30

4D

24

-

3

,.--

1
...

.~

TA"'+25oC

16

I'
i""-

8.0

I V,, '2~V
I
I
BIAS .

!;

!l

I

30

SUPPLY VOLTAGE {tV}

I

40

r- r-

20

3D

40

120

100

..
.

.0;

:!!

80

~
"'
c

60

.."

!:;

'.0

10

Voltage Gain

il

,I

o

SUPPLY VOLTAGE bVI

Input Current

--

20

40

SUPPL YVOLTAGE (tVI

Supply Current

'0

60

!:;
>

RL =5.n

SUPPLY VOLTAGE (.VI

2(

w

T. '25'~_

o

40

3D

80

C

20

>

o

2-222

Voltage Gain

Output Voltage Swing
4D

40

OFFSET

40

RI'

o

o
-55 -35 -15 5 25 45 65 15 105 liS
TEMPERATURE ('CI

'1 kr-

Vee. = i21V

20

-55-35-15 5 25 45 65

100

15 105 125

TEMPERATURE ('CI

Typical Performance Characteristics

Voltage Follower Slew Rate

(Continued)

SupplV Current

--r-

5_0

I

4_0

!~

.

'r- -

NIEGA~IVJ SLL

3.0

1

~

z

<

if

2.0

~

A

is
D
-55-35-15

l - I-

~

~_

----

."

5 25 45 65 85 IUS 125

-35

-15

15

·5

t- r-

I.U

i§

-

roo-

z

~

z

~

"..s....i:i

.13
.~

45

65

85

ID5

J

11
1 1

30

20

~INL

J.~

~

r:-

i"'- J"-.ll
s~u-;;r;'j

;:;

....

-r

10

ili

I I
-55 -35 -15 5

125

oc

25 45 65 85 105 125

TEMPERATURE (·C)

Input Noise Voltage

Input Noise Current

•

Ik

i

:z:

"

.'

40

:;

TEMPERATURE

Uriity Gain Bandwidth
1.5

I;

-

28

TEMPERATURE (·CI

~

-

~

"i 1

n

Vs -;t28V

- - r-

'1-- --

0
0

+ . 25·C

1.0

--r------+-

1--1-- -

""

PDSITIVE SLEW

Short Circuit Current
-,---,--

I-

-

I- -:-

o.,~~~

'0.5

--

>

!i

---==-:=j

o·°J,!"o--,,!;---+.---±----,::!.

Vs=t28V-

:0

1 1 1

fREQUENCY

1.0 L..J...J..WIIll-u.
IUD
10

-55 -35 -15 5 25 45 65 15 IDS 125
TEMPERATURE I·C)

(H~l

lOOk

18k

Ik

FREQUENCY (Hz)

Large Signal Frequency
Common-Mod~ ~ej8ction

120

!

..~'"
..
..''""

8D

T~ J

I--

r-.....

OJ
w

6D

:0;

40

'"

20

8

120

" 25 C
Vs -±28Y-

100

1.0

10

100

1"\

§

IOU

lk

lUk

.

OJ
>

~

I'\.

100.

~

80
60

1.0

10

IOU

m

80
60

w
to

..
<

4U

>

20

~

I

10

100

!

1M

180

""

PHASE

1.

135

/

90

1,\

45

1,\

"'

10k 100' 1M

FREQUENCY (Hz)

Ik

100

10k

100.

1M

FREQUENCY (Hz)

Voltage Follower Pulse

I

il

-20

lOOk

Response

1"-

TA = 25"C
-Vs =fI8V

10k

FREQUENCY (Hz)

""GAIN

'"~

Ik

~~; ~~.1tHlt-ffilttlll~:tHffIH

l"-

TA = 25"C

o

Response

-

TA " 25·C -ltll1I-f-ttMl-ftHIlIIH
Vs •• 28V tlttllI-f-tttffTtl:-ttHIlIIH

I'\.

2D

Open Loop Frequency

100

H-ttitlH+HIHlt-ttttifflt"-ti

~

1"-

NEGATIVE SUPPL~

FREQUENCY (Hz)

120

20

f"'. I""-.

40

1M

25 ,..,.-rri"",..-nTlT111r-rn"T111lrT"T

PDSITIVE SUPPLY

m

'"..
Z

I"
I'"

Response

Power Supply Rejection

~

~
~

~

~

;

20
16

~

12

INPUT

-

~
to

~

w
to

.
<

~

>

-12

~

l~UiT
.1
TA-:~

I

-4

-8

Inverter Pulse Response

20
16
12

t-

IL

r

-16
-20
10M

S

10

20
TIME (j.lsl

30

",'

28

i'-

40

.
<

~

>

1--

1\

'"z

~
:!:

I

-- -- --IINPUT

Ir-

\
I

-4

-8
-12

f::f-\:-

OUTPUT

I I
I

-16
-20
10

T-;

!i;·c-

S

28

r "I' i'-

20
30
TIME I/ois)

40

2-223

*R2 may be adjustable to trim the gain.
·*Rl may be adjusted to compensate for the resistance tolerance of R4 - R7 for best CMR .

•

±34V CommQn~Mode Instrumentation Amplifier

130 Vp.p Drive Across a Floating Load

r-----....--------1I---:C::,-1I----P-__
.
+
!OUTPUTVOLTAGE

.,

ADJU~~MENT

2Zk

G.I~F

CERAMIC ~

C3
"i"OpF
tOOv

..-o~~:EGULATED

.L

10k

"8

lOOk

+

Cl

-=

1M "'1'

sov

.3
2Zk
R4

100k

C2

+

10.lolF " "

25V..L

01

Ql

1N393.

2N4014

.,

tOOk
1%

t-__t-__

••

'2

Uk

10Uk
1%

2.OW

t-~_~:. ,V+ ~ S:ULATED
)

OUTPUT

R1l ':'"
10k

~------'-+l~----~--~----~O~
08
1N5230

tPut on common heat sink.
All resistors are 112 watt, 5%. except IS noted.

t--C-.'-------6--t--C4-o U~~~GULATED
D.1Io!F

~ CERAMIC

~1~F

-:#!

,GOV

Tracking ±66V. 1 Amp Power SupplV with Short Circuit Protection

iThe 38V supplies allow for a 5% voltage tolerance. All resistors are 1/2 watt. except as noted.

2-224

Typical Applications (Continued)

"

ZMEG

v·· .3.Vo-....

--~P--

_____....~P-__-,

.4
Uk

.5
Z.lk

....--+---+.......JY"If'V"-....--o OUTPUT

1--1~--1I---

V'N

•

.3
100k

+

'7
,7>

'17
22

a,'

2N62S4

.8

'"

tPut on common heat sink
-34 turns of no. 20 wire on a 3/8" form
**Adiust R6 to set IQ :: 100 rnA

C6
OhF

V-"

-Jav

TCERAM'C

90W Audio Power Amplifier with Sate Are. Protection

,...,%

y." tllV

.11

.....L.. C3

O.1~,F

TCERAM'C

R4
22k

,..... 0"
..... '.3666

.,

,.,i%

AID

V'N

Uk

'i-'-7

*

lM143

3V

~,. 0"

~,.

a,'

:.'...

~,. 03'

10k

A!l
A3 ,
Uk

'..,

:'...."

'8

A6

0.68

II ,••

6

4

03'
~ 2N~19

lOW
VOUT

~,I
IJ.OlliF

07

,DB

~

I~

A7
'00

A9
0.&8

' ow

jAr .. ,
..... ,.5976

I""" 0"
..... 'N4033

A'

m

tPut on common btat sink.
All Diodes Ire 1N3193.

•.I~-'CERAMJCT

v- '" -l8Y

1 Amp Power Amplifier with Short Circuit Protection

*The 38V supplies allow for a 5% voltage tolerance. All resistors are 1/2 watt. except as noted.

2-225

Application Hints
The LIVt 143 is designed for trouble free operation at any
supply voltage up to and including the guaranteed maxi·
mum of ±40V. Input overvoltage protection, both
common·mode and differential, is 100% tested and
guaranteed at the maximum supply voltage. Further·
more, all possible high voltage destructive modes during
supply voltage turn-on have been'eliminated by design,
As with most IC op amps, however, certain precautions
shoulo be observed to insure that the LM143 femains
virtually blow,o,ut proof.
Although output short circuits to ground or either
supply can be sustained indefinitely at lower supply
voltages, these, short circuits should be of limited dura·
tion when operating at higher supply voltages; Units can
be destroyed by any combination of high ambient
temperature, high supply Voltages, and high power
dissipation which results In excessive die temperature,
This is also true when driving low impedance or reactive
loads or loads that ,can revert to low impedance; for
example, the LM143 can drive most general purpose
'op amps outside of the maximum input voltage range,
causing 'heavy current to flow and possibly destroying
both devices.

•

Precautions should be taken to insure that the power
supplies never become reversed in polarity-even under
'transient conditions. With reverse voltage, the IC will
conduct excessive current, fusing the internal aluminum
interconnects. Voltage reversal between the power sup·
plies will almost always result in a destroyed unit.

In high voltage applications which are sensitive to very
low input currents, special precautions should be exer·
cised. For example, with high source resistances, care
should be taken to prevent the magnitude of the PC
board leakage currents, although' quite small, from
approaching those of the op amp input currents. These
leakage currents become larger at 125°C and are made
worse by high supply voltages. To prevent this, PC
boards should be properly cleaned and coated to prevent
contamination and to provide protection from condensed
water vapor when operating below O°C. A guard ring is
also rec;ommended to significantly reduce leakage cur·
rents from the op amp input pins to the adjacent high
voltage pins in the standard op amp pin connection as
shown in Figure 1. Figures 2, 3 and 4 show how the
guard ring is connected for the three most common op
amp configurations.

Finally. caution should be exercised in high voltage
applications as electrical shock hazards are present.

The LM143 can be used as a plug-in replacement in most
general purpose op amp applications. The circuits presented in the following section emphasize those applications which take advantage of

unique high voltage

capabilities of the LM143,

Compo or NIC

V'' .,

OUTPUT,,'

/

OFFSET NUll

I

GUARD

OFFSET NULL

O·

FIGURE 2. Guarded Voltage Follower
BOTTOM VIEW

FIGURE 1. printed Circuit Layout for Input Guarding

with TO·5 Package

.,

R2
"'UTo-J\I''''''~~--..JWv--.....,

"

R2
V·

GUARD

R3

1.,UTo------€H
R3 +

=~:

::

R1 +"2

= RsooRCE

V'

FIGURE 3. Guarded Non.lnverting Amplifier

2-226

V·

RJ~~

FIGURE 4. Guarded Inverting Amplifier

'II HARRIS

Operational Amplifiersl Buffers

LM 143A/LM343A High Voltage Operational Amplifier
General Description

Features

The LM143A is a general purpose high voltage operational
amplifier featuring operation to .:!:50V, complete input
overvoltage protection up to +50V and input currents
comparable to those of other super-fJ op amps. Increased
slew rate, together with higher common-mode and supply rejection, insure improved performance at high supply voltages.
Operating characteristics, in particular
supply current, slew rate and gain. are virtually independent of supply voltage and temperature, furthermore,
gain is unaffected by output loading at high supply voltages due to thermal symmetry on the die. The LM143A
is pin compatible with general purpose op amps and has
offset null capability.

•

Wide supply voltage range

•

Large output voltage swing

•

Wide Input common-mode range

•

Input overvoltage protection

•

Supply current is virtually independent of supply
voltage and temperature

•

Low input bias current

•

Low input offset current

•

High slew rate-essentially independent
of temperature and supply voltage

Application areas include those of general purpose op
amps, but can be extended to higher voltages and higher
output power when externally boosted. For example,
when used in audio power applications, the LM143A provides a power bandwidth that covers the entire audio

spectrum.

•

Connection Diagrams

Full.:!:50V

•

10.0 nA
3.0nA

5.0V Ips

of resistive loading, temperature, and

supply voltage

operated in environments with large overvoltage spikes

The LM343A is similar to the LM143A for applications in
less severe supply voltage and temperature environments.

.:!:4BV

High voltage gain-virtually independent

In addition, the LM143A can be reliably

on the power supplies, where other internally compensated op amps would suffer catastrophic failure.

!4.0Vto!50V

lOOk min

•

Internally compensated for unity gain

•

Pin compatible with general purpose op amps

Section 11 for Packaging

Metal Can Package

Dual-In-Llne-Package

NC OR

NC OR

OfFSE T

COMPENSATION

COMPENSATION

NUll

-=-+_-1

INPUT _ _
INVERTING

2

OUTPUT

INPUT

V'

INPUT

OUTPUT
OFFSET

NUll

v'
TOP VIEW
TQPVIEW

Order Number LM143AH
or LM343AH

Order Number LM143AJ-8
or LM343AJ-8, LM343AN

2-227



~

;!

10

=>

§!

Supply Current

L

2

I-'""

24

~
0~

i

T'T'"
" SUPPLY VOLTAGE (±V)
20

3D

'----,:l=0---2~0:c----:'30c-----'40----5.,.JO

SUPPl Y VOLTAGE (,VI

16

Voltage Gain

I
.......

I'--

•. 0

I

I

I

I

100

I

.....

ii
:!!

BIAS

..

"

r---

I '1'-,-,

,-,-,-

10

;;

r- I-4.0

120

VS=±50V

~

,I
I

TA'250C
--+---+-Rl.'" ~OOK~'

Input Current

-

3

40

SUPPl Y VOLTAGE bVI

SUPPl Y VOL TAGE (±V)

_-I

---t

~ 20

0-

"

,

120 r---.,----,----,------,-----,
1001

~ 30

30

,."
~

Voltage Gain

40~---+----+----+----~~~

~

OfFSET

.

0-

,.;;

40
Vc.c

20

o

o

I-- -

60

~

:t5DV

Rt" ,00kI'

-55 -35 -15 5 25 45 65 '5 105 125

-55-35-15 5 25 45 65 85 105 125

TEMPERATURE I"CI

TEMPERATURE I"CI

2-229

Typical Performance Characteristics

(Continued)

Supply Current

Normalized Slew Rate vs. Temperature

~ ~ 1A 1t---i,I--1,I-+-t--+-t--;

<4.D

: ';'12 It---il-+-t-+-t--t--;

~3.0

w...

E

SLEW RATE

!:! =1.0 I+--tll-~II-+-t--+-""';;l

w

g;II: 2.0

n.aI-l--+-+-+-l-4--+--;

~

QW

za:

~5

-511

>

0 +25 +50 +75 +100 +125
TEMPERATURE (DC}

...=>

il.O
Vs= :!:50V

rn

-55-35-15 -51525456585105125
TEMPERATURE DC

Normalized Gain Bandwidth vs. Temperature

•

Input Noise Voltage

Input Noise Current

~

10

';it

~

..e
I-

zw

......

r--.

BANDWIDTH

I
-SO

-25

1.0

II:
II:

=>

~

w
rn

0 +26 +50 +75 +100 +125
TEMPERATURE (DC}

~0.01.,::-,-.l.J.JJ;i~..L.
10

Large Signal Frequency
Common·Mode Rejection

-.

120

:!!

z

~

....
......
a:
~

aa

40

:::

20

f'\..

1.0

10

-

Vs'" .:t.50V-

t-- t-......

60

z

120

T~' 25!C

100

100

i

,.

I

f"

1"-

60
NEGATIVE

1"'-.

20
T... " 25°C

o

1M

1.0

10

FREQUENCY 1Hz!

:s

00

z

:;;: 120

4~o

...z
Do.

C>

2-230

80

!:;

60

goo ~
1ft

~ 40

40

1350 ~

'"
z ZQ

C>

~

.

::c

_

80

180 0

:li -40

10.

~

100.

1M

Response

iii

>

1k

Voltage Follower Pulse

Response

..

100

FREQUENCY 1Hz!

Open Loop Frequency

...'"
'"!:;

r"\.

SUPPL~

40

~

1"-

100'

I"" ,......

l"-

80

i!i

E
;;J
a:
>

10'

POSIT1VE SUPPL Y

100

:!!

I
I

f'\..

Response

Power SuppiV Rejection

2250
270 0
10 100 IK 10K lOOK 1M 10M
FREQUENCY (Hz}
+

~

Inverter Pulse Response

---------,

60
~ 40

'" 20

i

~. 0
... -20

0

f--t-\--;-. ......- .....+-i

~ -20 ~

'"~ -40

S ..aO
>

~

80

-80

0

10

40
20
TIME (/Ls}

I

~ -40 [ .... _1 .
<::-60
., • :
> -80
~~ ~_~~~~_.
10
20
30
m"E(/L.} .

o

·R2 may be adjustable to trim the pin .

.... R1 may be adjusted to compensate for tlte resistance tolerance of R4 - R7 for best eMR.

II

±34V Common·Moda Instrumentation Amplifier

130 Vp.p Drive Across a Floating Load

....- - - -....--------.--..,C.".7-.---~~--...O ~~:EGULATED
·OUTPUT VOLTAGE
ADJUSTMENT

••

Rl

12k

Cl

+
..J...

IOuF",
50V

+
T'M
CJ

O.""F
CERAMICT

1GOV

10k

.J

RlO

J,.

12k

R'

.,

lOOk

IN9,4

C2

+

.2

"::"

10",F " "

25V

..J...

IN9'4

.J

01
2N4014

.7
IN393B

INg,.

R7
lOOk
1%

.,

R.
lOOk
1%

:Uk
2.OW

C.+
I.QpF

IODV

C6 +
I.OjjF
lDaV

R16

'.k

'I

t65V
REGULATED
OUTPUT

Rl1'=
10k

"..

••

R15

..56

lN5Z30

tPut on common heat sink.
All reslston ilre 112 watt. 5%, tlCcept ilS noted.

.6
1N393•

-t--C-,0 ii~~~GULATED

t--.:C."..·-------...
O.1IlF

~CERAMIC

~lo,.,F
1IIIIY

-:JJ

Tracking ±65V, 1 Amp Power SupplV with Short Circuit Protection

:t:The 38V supplies allow for a 5% voltage tolerance. All resistors are 1/2 watt, except as noted.

2-231

Typical Applications (Continued)
RI
2MEIi

v·: +38V o-.....--"'"1~-------
co

0.1

140
120
100
80

~

60

9

40

~

20

z

co

r-I-

~

-

VS=±15V
TA = 258C

0
1.0

10

100

10

ISET",AI

100

~

l~

CI

e.

1M

III

co

e

IE

.

z
;;
c

:z:

S 101!k

0.1

•.c

...

:Ii

CI

0.01

~

10k

IE

C
CD

10
ISET "'AI

2-236

100

Phase Margin VI ISET

10M

,.t;

10
ISETlpAI

Gain Bandwidth Product vs
ISET

10

01

1

ISET"'AI

Slew Rate vs ISET

.5
!

0.1

100

10

100
ISET",AI

100

90

10
70
10
50
4G
30
20
10
0

r-..

"
VS" ±15V
TA"ZS"C
0.1

1

10
ISET",AI

100

Typical Performance Characteristics

.
w

co

~
c

>

~
c
~
~

0.9
0.8
0.7

....

0.6
0.5

Power Supply Rejection
Ratio vs ISET

Common-Mode Rejection
Ratio vs ISET

Input Offset Voltage vs ISET
S
oS

(Continued)

~
c
!;1

120

a:
z
c

80

;;:

~

60

-

;;;;:

100

r-

a:

0.4

w

0.3

co
c

40

1!i

20

40 I-H+fffllf--+++-l+f1'lf--f-H+1HlI

:11

0.2

Vs' ;15V

0.1

:I!
:I!
c
u

TA·25'C

0
0.1

10

100

20 I-H+fffllf--+++-l+f1-1+-- vs • ,15V

Vs = t15V
TA'25'C
0.1

10

o ~~~~~~~~T~A~=~2~5'~C~

100

0.1

10

100

'SET (pAl

16

•

Input Bias Current vs
Input Common-Mode
Voltage

Input Voltage Range vs
Supply Voltage

Output Voltage Swing vs
Supply Voltage

100

16

'SET-IO.A

~

14

~
w

14
12

~

10

ill
a:

co

...
w

co

~
c

=
u

.,~

~
;;;

co

12

.

10

i

co

z

..

w

>

~

>

~

=
:=
c=

~

=
!!

0

~

TA', 25'C
ISET ·IO.A

4

&

8

10

12

14

1&

ill
a:

60

l:l

50

a:

~
;;;
~

~
~

40
3D
20

r10
o

14

1&

--

'SEP10~A ~ -

-

-55 -35 -15 5

'SEPlpA

'"-F+-4

TEMPERATURE (DC)

1
....

i=

<
oS

..=

.'"

ill

10

15

ISET • IO.A

~

b!SET=I.A

u

~
c

25 45 65 85 105 125

-5

10

u

r- r-

-10

Supply Current vs
Temperature

9

....

r-..

VS . .15V
TA' 25'C

I

INPUT COMMON-MODE VOLTAGE (V)

10

IVS~±15V

90
80

12

InpL\t Offset Current VI
Temperature

100

70

10

SUPPLY VOLTAGE (.V)

Input Bias Current vs
Temperature

~

4

0

SUPPLY VOLTAGE (tV)

<
oS

0.1
-IS

0
0

ISET' O.I.A

~

~

TA·25'C
'SET·IO.A
RL'10kn

'SET' I .A

10

a:

>-

r- .....

~

l"-

~

VS=±15V

::

~~r

iil

I

o
-55 -35 -15 6

25

46 65

TEMPERATURE (DC)

85 105 125

0.1

VS'iI5V
0.01
-55 -35 -15 5

25 45 65 65 105 125

TEMPERATURE (·C)

2-237

Typical Performance Characteristics
Open Loop Voltage Gain
vs Temp,rature
140

:s

120 -

co

100

"'co

80

C>

.

60

C>

~

40

~

20

a;
z
:;:

"!:;
>

C>

ISE1' 1~A TO 10~A

!

7
10

::

106

~

105

~
~

"'co
~

C>

>

'"c;"'

...z
::0

!!

o

~,,~~!!~

~ISET·'0.A

0.1

..

!

.:

I I I
E E

I I I

0.01

~ISET·O.I.A

I I I I

TEMP~RATURE

TEMPERATURE COt)

Input Noise Current vs
Frequency

.iii
~
,..

""'"

i..

ISET"'0.A
ISET' 20.A

VS'±15V
TA" 21i"C

I I I lUI
100

lk

10k

10

FREQUENCY (Hz)

100

i

,.

18
12

~
co

i

"'
co

"

!:;
co
>

8
4

I
I
I

20

10k

10

I

I

1\ I

I

INPUT

I

-4

"

!
~
C>

50,"

-20
100

200

300

TIME",,)

~

1/

-50

l

-18

r

50

i-50
.0

lk

10k

FREQUENCY 1Hz!

IjOUTPUT

II

1--

100

Voltage Follower Transient
Response

ISET"10.A
Vs = ±15V
TA=UoC

0
-8
-12

40 r--+~+__1-~-~~

FREQUENCY 1Hz)

Voltage FolI.ower Pulse
Response
20

.....::_+----1--I---I

~ 100 t-.~

IS!T~121!~
IS!T~151!y

~

1°C)

Power Supply Rejection
Ratio vs Frequency
a; 120 r---r-,--r-----r---,----,

:s

....

~ISET=I .A

VS=±15V J
0.001
-55 -35 -1& 5 25 45 65 85 lOS 125

103
-55 -35 -15 5 25 45 65 85 105 125

5 25 45 65 85 105 125
TEMPERATURE IOC)

ISET= I.A

10

-

-

\

ISET"'U.A
Vs" ±15V
TA" 25°C
CL "UhF
Rt- 1Dkn
3

TIME",,)

Transient Responlll Test Circuit

2-238

ll!:
"'
!c

• •

Input Noise Voltage vs
Frequency
110
100
90
80
70
60
50
40
30
20
10

Slew Rata vs
Temperatu re

:;:

ys =f 151

o

Gain Bandwidth Product
vs Temperature

1
.:104Mfim~
~z

-55 -35 -15

•

=c-c--

(Continued)

.

lOOk

1M

Application Hints
Avoid reversing the power supply polarity, the device
will fail.
Common·Mode Input Voltage: The negative common·
mode voltage limit is one diode drop above the negative
supply voltage. Exceeding this limit on either input will
result in an output phase reversal. The positive common·
mode limit is typically 1V below the positive supply
voltage. No output phase reversal will occur if this limit
is exceeded by either input.
Output Voltage Swing vs ISET: For a desired output
voltage swing the value of the minimum load depends on
the positive and negative output curent capability of the
op amp. The maximum available positive output current,
(lCL+), of the device increases with ISET whereas the
negative output current (lCL) also increases with ISET '
Figure 1 illustrates the above.

Isolation Between Amplifiers: The LM 146 die is iso·
thermally layed out such that crosstalk between all 4
amplifiers is in excess of -105 dB (DC). Optimum
isolation (better than -110 dB) occurs between ampli·
fiers A and 0, Band C; that is, if amplifier A dissipates
power on its output stage, amplifier 0 is the one which
will be affected the least, and vice versa. Same argument
holds for amplifiers Band C.
LM146 Typical Performance Summary: The LM146
typical behavior is shown in Figure 3. The device is fully
predictable. As the set current, ISET, increases, the
speed, the bias current, and the supply current increase
while the noise power decreases proportionally and the
Vas remains constant. The usable GBW range of the op
amp is 10 kHz to 3.5-4 MHz.
laM

~
(lCL-)

......

-f-

t;

!

• .14

1II1II

lat

"
SU"LYCORREIIT "'AI

TA' 25 0 C

•

o.s

10

ISET (~A)

I J J II 11m 'IIIUHI
1.1
I
"
'lET""')

FIGURE 1. Output Current Limit vs ISET
Input Capacitance: The input capacitance, CIN, of the
LM146 is approximately 2 pF; any stray capacitance,
CS, (due to external circuit circuit layout) will add to
CIN. When resistive or active feedback is applied, an
additional pole is added to the bpen loop frequency
response of the device. For instance with resistive feed·
back (Figure 2), this pole occurs at 1/2rr (R11IR2)
(CIN + CS). Make sure that this pole occurs at least
2 octaves beyond the expected -3 dB frequency corner
of the closed loop gain of the amplifier; if not, place a
lead capacitor in the feedback such that the time can·
stant of this capacitor and the resistance it parallels is
equal to the RI(CS + CIN). where RI is the input resis·
tance of the c.ircuit.
Rl

Ii
I:

I

l

,. ....

1811

6

to

a

vs· +15V
4

;

tA

111

co

IE

(lCL+) ~-I-

v

."

R2

•

Tl-..2(":)

..

I II
111)2

1nJ2

(till

"

FIGURE 3. LM146 Typical Characteristics
Low Power Supply Operation: The quad op amp oper·
ates down to ±1.3V supply. Also, since the internal
circuitry is biased through programmable current sources,
no degradation of the device speed will occur.
Speed vs Power Consumption: LM146 vs LM4250
(single programmable). Through Figure 4, we observe
that the LM146's power consumption has been opti·
mized for GBW products above 200 kHz, whereas the
LM4250 will reach a GBW of no more than 300 kHz, for
GBW products below 200 kHz, the LM4250 will con·
sume less.
10M

OA

FIGURE 2
Temperature Effect on the GBW: The GBW (gain
bandwidth product), of the LM146 is directly propor·
tional to ISET and inversely proportional to the absolute temperature. When using resistors to set the
bias current, ISET, of the device, the GBW product will
decrease with increasing temperature.

~

gj
a.04

§
...

"<

;,'

,.

L-L...LO=IL..Jw..1.I.LWL...J...llWW a.l04
1a
1DO
SUPPLY CURRENT "'.,

FIGURE 4. LM146 vs LM4250

2-239

Typical Applications
Single (Positive) Supply Biasing

Dual Supply or Negative Supply Biasing

v+

SET 9 RSH

RSET 8 SET
LM346

•

ISET~

V+ - O.6V
ISET ~ -R-S-E'-T-

IV-I- O.6V
RSET

Biasing all 4 Amplifiers
with Single Current Source

Current Source Biasing

v-

v+

v+

SET

LMJ46

IT = ISET 1 + 'SET 2

2-240

Active Filters Applications
Basic (Non-Inverting "State Variable") Active Filter Building Block
lOOk
10k

•

The lMI46 quad programmable op amp is especiallv suited for active filters because of their adequate GBW product and low power
consumption.

Need to know desired:

•

fo = center frequency measured at the BP output

Clo ~ quality factor measured at the BP output

Ho = gain at the output of interest (BP or HP or lP or all of theml
~

~
~

Relation between different gains: Ho(BPI = 0.316 x Clo >< Ho(lP); Ho(lPI = lOx Ho(HP)
5.033 x 10-2
RxC=
fa
(secl
-1
(3.478 Clo _ 1)
3.478 Clo - Ho(BPI
•
Ho(BP)
)
•R _
Ho(BPI
For BP output: RQ = (
105
105 x 3.478 x Q o
• IN + 10-5
RQ

..!...

1.1 x 105

~-1

~ For HP output: RQ = 3.478 Clo 11.1 _ Ho(HPII - Ho(HP)

~

~

For lP output: RQ =

11 x 105
3.478 Clo (11 - HollP» - HollPI

RIN = Ho(HP)

; RIN =

2.+
10-5
RQ
11
HO(lP)-

Note. All resistor values are given in ohms.

-7"""'-'-_1_+ 10-5
RQ

For BR (notch I output: Use the 4th amplifier of tho lMI46 to sum the lP and HP outputs of the basic filter.

LPo-"""M........

Hpo-.J\M,...'

Determine RF eccording to the desired gains: HoIBR) If «fnotch =
•

:~

Ho(lP). HoIBR) If»

fnotch = : : Ho(HPI

Where to use amplifier C:. Examine the above gain relations and determine the dynamics of the filter. Do not allow slew rate limiting
in any output IVHP. VBP. Vlpl. thet is:
VINlpeakl

<

63.66 x 103 x ISET· x _1_ IVolts)
10"A fo x Ho

If necessary. use amplifier C. biased at higher ISET. where you gat the largast output swing.
Deviation from Theoretical Predictions: Due to the finite GBW products of the OP amps the fa.

Clo will be slightly different from the

theoretical predictions.

fa

freal == ~o

1 +__
GBW

I

Oreal

Clo
==:

1 _ 3.2 fax Clo
GBW

2-241

Active Filters Applications (Continued)
A Simple-to-Design BP, LP Filter Building Block

Uk
Uk

RQ

R

•

•

If resistive biasing is used to set the LM346 performance, the Cl., of this filter building block is nearly insensitive to the op amp's GBW
product temperature drift; it has also better noise performance than the state variable filter.

Circuit Synthllis Equations
Ho(BP) = Cl.,Ho(LP); R x C

•

0~59

=- - ;
fo

RQ· 00 x R; RIN

RQ

R

= --= - Ho(BP) Ho(LP)

For the eventual use of amplifier C, see comments on the previous page.

A 3-Amplifier Notch Filter (or Elliptic Filter Building Blockl

Uk
Uk

RQ

>~~OVOUT (IR)

Circuit Synthesis Equatlolll
0.159
R xC- - - ;RQ = Cl.,x R;RIN
fo
Ho(BR)

•

2-242

If«

0.159xf
2
0
C x f notch

=,

R
fnotch = RIN Ho(BR) If»

~

fnotch

For nothing but. notch output: RIN - R, C' = C.

C

Active Filters Applications (Continued)
Capacitorless Active Filters (Basic Circuit)

RJ

RZ
RIO

R9

8R

RS

II

Rl

•

This is a BP, LP, BR filter. The filter characteristics are created by using the tunable frequency response of the LM346.

•

Limitations: 0 0

•

Design equations: a =

< la, fo x 0 0 < 1.5 MHz, OUlput voltage should not exceed
R6 + R5

Hoi LP)

= ~ , 00 =,,;;;;t;

fo(BR)

= fo(BP)

(1

R2

R3

AS' b = Rl + R2' c = R3 + R4

-~) ~

fo(BP)

(e«

1) provided that d

d
'

=

Vpeak(out):O;

R7
R8 + R7 ' e =

= HoIBP)

x e, HoIBR)

63.66 x 103
fo

RIO

R9+R1O'

=

Advantage: fo • 00. Ho can be independently adjusted; that is, the filter is extremely easy to tune.

•

Tuning procedure (ax. BP tuning)

Pick up a convenient value for b; (b
'Adjust 00 through R5
Adjust Ho(BP) through R4
Adjust fa through RSET

= fu

fb
J a' HoIBP) =a x c,

:~.

•

1.
2.
3.
4.

folBP)

ISET II,A) (V)
x ~

< 1)

A 4th Order Butterworth Low Pass Capacitorless Filter

A'S
500

:.>1..
0 ...~:>vOUT

Ex:
•

tc = 20 kHz, Ho (gain of the filterl = 1,001 = 0.541, 002 = 1.306.

Since for this filter the GBW product of all 4 amplifiers has been designed to be the same (-1 MHz) onlv one current sourea can
be used to bias the circuit. Fine tuning can be further accomplished through Rb.

2-243

Miscellaneous Applications

A Unity· Gain Follower
with Bias Current Reduction

V,N

Circuit Shutdown

0-....- - - - - ;
VOUT

5V"'DNl

N~OV

II

2l1li

•

•

For better performance, use a matched

NPN pair.

BV pulling the SET pin(s) to V- the op amp(s) shuts down and its
output goes to a high impedance state. According to this property,
the LM346 can be used a. a very low speed analog switch.

Voice Activated Switch and Amplifier

v+
15V
0.1 ~F

MIC

IN.~ I-2 kn
OOC~TA ~+700C

RL
Output Voltage Swing

7,5

mV

75

100

nA

325

400

,..:'"

nA
VlmV

15

25
±12
±IO

:1:13

±12

t12

±10

70

:1:13
:1:12

90

70

V

96

'77

90
;

R,~IOkn

77

V
V

±12

±12
R,~10kn

Ratio

Supply Voltage Rejection

mA

'6.0

> 2kf!

RL=10kn
RL=2kH

Input Voltage Range
Common-Mode Rejection

'25

25

Output Short Circuit Current

.

'96

dB
,

dB

No_ 1, Any of tne- amplifier Outputl 'can be shorted to ground in!letinllaly; however' moruhanl)nuhould ralt b.& limu,ltineou,ly ,hortecj as the
mllXlmum junction temperatura will ba exce8ded.
Nota 2: Tha maximum power dluipatlon for these devices inust' be djlratad at aI8\lllt~,tI!mper.tur.. arid Is dictated bll riMA", 6jA,ind tha
ambient tamparature, TA. The maximum available power dissipatibn at,any, temperat!Jre IS'~d = (TjMAX - TA)/6j~ or th~ 25"C I'dMAX, which·
ever II 1l1li.
.
Nen. 3: Th ..e spacifications apply for Vs = .,5V and over the abooluta maximum operating temperature ranga (TL ~ T'Au5TH) unlass otbarwlss
noted.
'J

2-247

Typical Performance Characteristics
Supply Current

Voltage Swing

I"put Bias Current
90

50

~
'"z

80

~....

70

~
~

60

....

3D

~

20

Positive Current Limit
Vs -i15

"'"~

-10

~

.

\

~

\~
+'1A
20

25

~

'"'"
"

60

"-r'\.

40

-

BO

+25~

I

w

>

20

10

100

100

i

10

.'"

"Z

5
~

..

10

IS

20

25

100

30

Z

Vs =±.15V
TA = 25 0 C

r-

50

~

LM14B

I0

-3~

o

-35

10

100

FREQUENCY (Hz,

Ik

10k

lOOk

1M

100
90
80
10
:l
60
~
&0
40 ~
co
3D iii
20
10
0
-10

Vs"':!: 15V
TA =2 5'C

111'1'1

r¢l? ,

GAIN

;

"

~

0.1

-1 0

10M

r-...
~ ~lo;; -~m~

-5
-10
-15
-20
-25

z

30

1M

1M

I'Iot'N.I

,."'

to

~

100le

Bode Plot LM 148
20
15
10

110
90

10k

FREQUENCY (Hz)

Open Loop Frequency
Response

;;:

lOOk

lk

OUTPUT SINK CURRENT (mAl

70

10k

S
w

0.1

30

~

Ik

25

Output Impedance

:zz"

I
Vs=±lSV
TA = 25 0 C

o

20

lk

""

.125"C

15

SUPPLY VOLTAGE (.V)

~ ~ -5~"C

;::

Rejection Ratio

LM11~ r'\.

::;

10

0

Vs '" +15V

-5

120
100

V

/

0

>

QUTPUT SOURCE CURRENT {mAl

Common~Mod.

V

25 45 65 85 105 125

5

i \-55'C

15

-15

iiiw

'\: ~

10

10

Negative Currant Limit
~
'"z

/

V

TEMPERATURE ('CI

SUPPLY VOLTAGE (.VI

+lZ5°C

::
"~

,....~

-55 -35 -15 5

20

~I=::;;j,:.:r'

V

20

~

I

o
15

·'5V'-r-r-

'L V'j

3D

..~"

~t-. (-....
,....~r-

10
10

5

~r-..;.20V'

40

~

TA =2S'C

iii

50

~

JJL

40

10

10M

FREQUENCY (MHz)

FREQUENCY (Hz)

Large Signal Pulse
Response (LMl48)

Small Signal Pulse
Response (LMl48)

Undistorted Output Voltage
SWing

1 v. 1
1 1 1 ~

0

100

;;;
.5

il!

o~ -tOO
~

"com !S
iii >
;

~

:i! 100

0

~

..

Av"'1
Vs;;±15V

I

IRL ~Zk
ITA' 25'C I-

-I 0

0

1
1
1
40

TIME !..sJ

2-248

80

'"'"

28

RL

iiiw

24

"'"....

20

TA .; 25 C
Av -1
1"1gDIST

....>

16

~

12

.
"

VIN

-I 0

-100

~,...

1-1\-

~

32

vs: 15V

+

c

~~

~

120

TIME(,.~

160

200

z

"

2k

+T ,

-

....

1;;
C

"

100

Ik

10k

FREQUENCY (Hz)

lOOk

Typical Performance Characteristics
GaUl Bandwldch

V,I, ;15V

4.0

(continued)

I nvertlng Large Signal Pulse
Response (LMl481

Slew Rate

10V
-;

%

~

::. J.O

J.O

~

"
~

2

~

~

~

%
I-

2

2.0

10

w

:i

2.0

10

~

1.0

I-

0

>

1.0

LM148-

t- t-

-55 -J5 -15 5

o

25 45 65 85 105 125

..L:

'15~

c>
0 - -15

"t::

..

"w
"0<

w-

160

16

140

14

f

120

12

100

10

80

08

-10

60

0.6

w

e;

A~

-15

NEGATIVE SUPPl Y VOL T5 IV)

-20

40

04

~

20

0.2
10

65 85 105 125

20

i!;
l;

l-

i

~2

n

z
z

<

~

10

..

25 45

Positive Common-Mode Input
Voltage Limit

ii

~>

~ ~5C

'-'I-

~z

V- ~

'25

z~
,,-

~

5

TEMPERATURE lOCI

Input Noise Voltage and
Noise Current

·20
~

-55 -J5 -15

TIME (,.5)

NegatIVe Common-Mode Input
Voltage Limit
l-

I L

o
20406080100120140160180200

TEMPERATURE lOCI

=>

LM148

·10

I I

o

>0
;:>

V,I, ,15V

4.0

N

c

-55 C _ TA

+125 C

=>
;!

~

,,,"

01-

2::;

~h;::

"~"
i
,.

"<

E

Ii:

Ol-

'-'- 10

:/

wO

»

;:
v;

/

L

/

1/

II

/

100

"
FREQUENCY (Hz)

10

15

20

POSITIVE SUPPl V VOL TS IV)

Cross Talk Test Circuits

Crosstalk =

-20 log

·'OUT

(dBI

101 x.OUT
Vs = '15V

2-249

Typical Applications - LM148 (Continued)

A I kHz 4 Pole Butterwortll

11
Use general equations, and tune each section separately

0lstSECTION = 0.541, 02ndSECTION = 1.306
The response should have 0 dB peaking

A 3 Amplifier Bi-Quad Notch Filter

.J

"

"

••

.,

YouTld

••

.

v.wo-..----------------------~---------------------I

Oa

8
~
-R7

RICI
X

.J R3C2R2Cl

,

fR8
'a· ...:..
21rJ Ai

I
Necessary condition for notch: _
RS

Ex: 'NOTCH

a

3 kHz, 0·5, RI

a

I

x

.JR2R3CI C2

RS
R3R5R7CIC2

RI
c

R4R7
270k, R2 = R3 = 2Ok, R4 = 27k, R5· 20k, RS. R8 - 10k, R7 - lOOk, CI - C2· O.oolpF

Better noisl performance than the state-space approach

2-250

, fNOTCH--2"

Typical Applications -

LM148 (Continued)
Low Drift Peak Detector with Bias Current Compensation

Adjust R for minimum drift

03 low leakage dIOde

01 added to Improve speed

,

Vs·- '15V

'M

2~_'

II

Universal State-Space Filter

"

IOO~

"

11001

A4

v...

Tune Q through RO,
For predictable results: fO 0 $. 4 )( 104

Use Band Pass output to tune for Q

Nisi

01.1 = 52 + 5w a

+ wa2

Q

Olsl

·SwQHOBP
Q

f1 I, = R,C"
J -;-:;Q ,

1

'0= -

2n

'NOTCH

(

=
2n

Q

=

+ R41R3 + R4IRO)
1 + R61R5

IRG

~)

\R5

12

1 + RGIR5

RH) 112
, HOHP =
RL'112

(1

1 + R31RO + R31R4

1
, HOBP =

112

+ R41R3 + R41RO

1 + R31RO

+ R31R4

1 + R51RG

HOLP

= -----1 + R31RO + R31R4

2-251

Application Hints
The LM148 series are quad low power 741 op amps.
In the proliferation of quad op amps, these are the first
to offer the convenience of familiar, easy to use operating
characteristics of the 741 op amp. In those applications
where 741 op amps have been employed, the LM148
series op amps can be employed directly with no change
in circuit performance.
The package pin-outs are such that the inverting input
of each amplifier is adjacent to its output. In addition,
the amplifier outputs are located in the corners of the
package which simplifies PC board layout and minimizes
package related capacitive coupling between amplifiers.
For input voltages which greatly exceed the operating
supply voltages, either differentially or common-mode,
resistors should be placed in series with the inputs to
limit the current.

•

Like the LM741, these amplifiers can easily drive a
100 pF capacitive load throughout the entire dynamic
output voltage and current range. However, if very large
capacitive loads must be driven by a non-inverting
unity gain amplifier, a resistor should be placed between
the output (and feedback connection) and the capacitance to reduce the phase shift resulting from the capacitive loading.
The output current of each amplifier in the package is

Typical Applications -

.,

limited. Short circuits from an output to either ground
or the power supplies will not destroy the unit. However,
if multiple output shorts occur simultaneously, the time
duration should be short to prevent the unit from being
destroyed as a result of excessive power dissipation in
the IC chip.
As with most amplifiers, care should be taken with lead
dress, component placement and supply decoupling in
order to ensure stability. F<;>r example, resistors from the
output to an input should be placed with the body close
to the input to minimize "pickup" and maximize the
frequency of the feedback pole which capacitance from
the input to ground creates.

A feedback pole is created when the feedback around
any amplifier is resistive. The parallel resistance and capacitance from the input of the device (usually the
inverting input) to ac ground set the frequency of the
pole. In many instances the frequency of this pole is
much greater than the expected 3 dB frequency of the
closed loop gain and consequently there is negligible
effect on stability margin. However, if the feedback pole
is less than approximately six times the expected 3 dB
frequency a lead capacitor shoud be placed from the
output to the input of the op amp. The value of the
added capacitor should be such that the RC time constant of this capacitor and the resistance it parallels
is greater than or equal to the original feedback pole
time constant.

LM148

.,

One Decade Low Distortion Sinewava Generator

.s

Low Cost Instrumentation Amplifier

VOUT

.,

VOUT=2(:: +1) ,Vs
1
A4A5 ( 1
1
f = -2,,-A-l-C-l x..jK ,K = A3
ros +
+

1\

R4 As),

rOS '"

AON
Vv:S) 1/2

(1 _

fMAX = 5 kHz, THO :S 0.03%
AI = lOOk pot., Cl = 0.0047I'F, C2 = O.G1IlF, C3 = O.II'F, A2 = A6 = A7 = 1M,
A3 = 5.1k, A4 = 12.0, A5 = 240.0, a = NS51 02, 01 = lN914, 02 = 3.6V avalanche
diode (ex. LM103), VS •• 15V
A simpler version with some distortion degradation at high frequencies can be
made by using A1 as a simple inverting amplifier, and by puttin~ back to back
zeners in the feedback loop of A3.

2-252

-3V:SVINCM:SV~-3V,

Vs = ±15V
A = A2, trim A2 to boost CMAA

Typical Applications -

LM148 (Continued)
A 4th Order 1 kHz Elliptic Filter (4 Poles, 4 Zeros)
HI

lowpass Response

100~

"

-1,1

3D
-40

R"

HO

-"
·60
-70

'"
R,

..

.

,

'oo.

fREQUENCY (HI)

R1C1=R2C2=t
R'1C'1=R'2C'2=t'

.-,
lOOk

•

AD
Vo

.4
fC = 1 kHz, fS = 2 kHz, fp
1

fp =

Rp

h

JR6.

= 0.S43, fZ

1

RS x

~

1

, fZ

=

2n

= 2.14, Q = 0.841, f'p = 0.987, f'Z

~

J~

1

x

~

= 4.92, Q'

(R6

_( 1 + R41R3 + R4IRO)
Q -

1 + R6!RS

= 4.403, normalized to ripple BW

x

J As

,Q'

=

fR-6
J R-5

1 + R'41R'O
1 + R'61R'S + R'6IAp

=

Use the BP outputs to tune Q. Q', tune the 2 sections separately
Rl

= R2 = 92.6k,

R3

= R4 = RS = lOOk, R6 = 10k, RO = 107.8k, RL = lOOk, RH = lSS.1k,
= R'S = lOOk, R'6 = 10k, R'O = S.78k, R'L = lOOk, R'H = 248.l2k, R'f =

R'l = R'2 = SO.9k, R'4

lOOk. All capacitors are O.001I'F.

2-253

mHARRIS

Operational Amplifiers! Buffers

LM 148A Series Quad 741 Type Op Amps
LM148A/LM348A Quad 741 Type Op Amps

•

General Description

Features

The LM148A series is a quad 741 type operational
amplifier. It consists of four independent, high
gain, internally compensated,lowipower operational
amplifiers which have been designed to provide DC
and AC performance superior to the familiar 741
and LM148 operational amplifiers. While maintaining low supply current, these devices offer speed
and bandwidth specifications comparable to high
performance type op amps. Excellent isolation
between amplifiers has been ensured by employing
the Harris 01 process coupled with layout techniques which minimize thermal coupling.

•

The LM148A can be used in virtually all LM148
or LM149 applications. Where amplifier matching
or high packing density is required, these devices
can be used in plaCe of multiple single or dual
type op amps.

High performance operating characteristics

•

Low supply current ... POISS 140 mW/Package

•

Class AS output stage-no crossover distortion

•

Pin compatible with the LM 124

•
•

Low input offset voltage

0.3mV

Low input offset current

30nA

•
•

Low input bias current

130nA

Gain bandwidth product
LM148A (unity gain)

•

High deQree of isolation between
amplifiers

•

Overload protection on all outputs

Schematic and Connection Diagrams

8 MHz
120dS

Section 11 for Packaging
Dual-In-Line Package
TOP VIEW

oun

OUTl

IN 1

IN.

IN 4+

IN 1+
12
V+

V-

INZ'
10
IN2

IN3 -

OUT2

OUT3

Order Number LM148AJ,
LM348AJ
Ordar Number LM348AN

2-254

IN3+

Absolute Maximum Ratings

LM148A

(Note I)

LM348A

Supply Voltage

.:!:.20V

Differential Input Voltage

,!:Vs

.:!:.vs

Input Voltage

.:!:,vs

:,Vs

Output Short Circuit Duration (Note 1)

Continuous

Continuous

.:!:.20V

Power Dissipation IPd at 25 0 CI and
Thermal Resistance ( 6 JAI. (Note 21
Molded DIP (NI

Pd

500mW

6 jA
Cavity DIP (01 (JI

1500 C/W

Pd

900mW

900mW

6 jA

1000 C/W

1000 C/W

Maximum Junction Temperature (TjMAX)
Operating Temperature Range

1500 C

1000 C

-550C~TA~ +125 0 C

DoC ~TA ~ +700 C
-650 C to 1500C

Storage Temperature Range

_65 0 to +1500 C

Lead Temperature (Soldering. 60 seconds)

Electrical Characteristics

2000 C

3000 C

(Note 3)

LM148A
PARAMETER

UNITS
MIN

Input Offset Voltage
(Rs~10 klll

LM348A

CONDITIONS

Unless Otherwise
Specilled: Vs' .:!:.15V

TYP
.3

MAX

MIN

TYP

MAX

.5

4.0

nA
nA

3.0

15

25

30

50

Input Bias Current

75

100

130

300

Input Resistances

.5

Input Offset Current

TA - +25O C

Supply Current All Amplifiers

.5
7.5

Large Signal Voltage Gain

VOUT= ;tl0V. RL:!:2 kn

Amplifier to Amplifier
Coupling

1= 1 Hz to 20 kHz (Input
Referred) See Crosstalk
Test Circuit

100

mA

250

V/mV

-108

-108

dB

Small Signal Bandwidth

8

8

Phase Margin

40

40

degrees

.:!:4

V/p.s

Slew Rate

.:!:1

Output Short Circuit Current
Input Offset Voltage
(Rs~10kW

Input Offset Current

.:!:1

MHz

25

26

•

Mfl
7.5

75

250

mV

mA

Unless Otherwise
Specified: Vs = .:!:.15V

3.5

4.5

mV

-550C~TA~+1250C

75

100

nA

325

400

nA

ILM14BAI

Input Bias Current

OoC !STA ~+. 70 0 C
ILM348AI

Large Signal Voltage Gam

VOUT: .:!:10V

100

Output Voltage Swing

RL-l0k!!
RL-2kl!

;t12
.:!:IO

75

;t13
.:!:12

:!:12
:!:10

V/mV
;t13
;t12

V
V

Input Voltage Range

.:!:12

Common ... Mode Rejection
Ratio

80

90

80

90

dB

Supply Voltage Rejection

BO

90

80

90

dB

-------_.

;t12

V

Nota 1 : Any of the amplifier outputs can be shortl:d to ground indefinitely; however. more than one should not be simultaneously
shorted as the maximum junction temperature will be exceeded.
Note 2: The maximum power dissipation for these devices must be derated at elevated temperatures and is dictated by TjMAX. 8 JA.
and the ambient temperature. TA. The maximum available power dissipation at any temperature is Pd =- (TjMAX - TAU 8 jA
or the 250 C PdMAX. whichever is less.
Nota 3; These specifications applv for Vs = :!:.15V and OYer the absolute maximum operating temperature range (TL5,TA '5. THJ unless
othe~ise noted.

2-255

Typical Performance Characteristics
Powe, Supply Current VI Temperature

Offset Voltage Input Bias and Offset
Current vs T8~perature

MId Supply Voltage

Voltage Swing
50

I I I

~

il

!~
•
,=
i I :H~.j-H"'f=r
.1.

__..!-'--!,-"---!-..L-!:-'-=':--+-::!::--'-::,,;!....

20

";

10

II"

30

'/
II"
II"

V
II"

~

nMIIATUIlt! •• ~

TEMPERATURE·OC

iii
~
"
..
~

T."25"C

40

0
10

0

15

20

25

SUPPLY VOLTAGE «VI

:;; -15

Vs

•

;:;

=115

'"

~
>

\~

1

'+2rC\

15

20

-10

5
~
"

,\_55°C

10

::--...

~

'\ ~
+125°C

Output I mpadance

Negative Current limit

Positive Current Limit

w

~ ~ !'o..-5~"C
+25:~

-5

~

3D

+125",

o

E
w

..
Z

i...

~
S

10

15

20

25

IOU

30

Response

.....

+".
.,.'
~

aD

~

~

~

a:
a:

R!'~'"

......
......

!
qac ....

1I

..aciE
1351C

'10

,. ". ,...

,-

11f1ot

'M

fREDUENCY - Hz

FREQUENCY (Hz)

Large Signal Pulse

Response (LM148A)

VOLTS: &vIOl.
TIME: 20 priDI.

2-256

H+

+11

i .,.
."•
."
"

...:IE

1111111
Cl'"SOpF

10k

lOOk

1M

Small Signal Bandwidth and
Phase Margin vs Load Capacitance

Open Loop Frequency

100

lk

FREOUENCY (HzI

OUTPUT SINK CURRENT (mAl

120

10

0.1

o

OUTPUT SOURCE CURRENT ImAI

Common-Mode Rejection Ratio

IUD

u

"

>
;:
2

25

It

Vs;; t15V

'OM

i

5

•

Typical Performance Characteristics

(Continued)

Small Signal Rasponsa Circuit
CVolts: 10mVlDiv., Time: SOns/Div.)

Undistorted Output Voltage
Swing

r-- ~UTPUT r""\
INJUT

:'-

I

I
III

IL

ov

FREQUENCY - Hz

Normalized Gain Bandwith VS. Temperature

Normalized Gain Bandwidth VS. Temperature

...

u
u

-

U
1.1

;1
....

~

U

...
...
...

"0-

MIIDWlDT"

I
I
I

~;

-~

U
"w
....

... ... .......

OJ

..12D

.'1.

TEMPERATURE -DC

•

u
u
1.1

...
...
...

~ i"""

ILEWRATE

I I

..
...

I I
I

...

...
 2 k!l

15

V/mV

IS
,14
! 13

Vs': !15V, Rt. ~ lOki!
RL '2kl!

:t12

Input Vollage Range

Vs' '1SV

!,13

Common Mode
Rejection RatiO

Rs ', 10 k!l

80

100

74

100

dB

Supply Voltage
Rejection RatiO

Rs <. 10 kll

80

96

74

96

dB

Output Voltage SWing

•

V/mV

40

5.0

:t'3

!14
i13

±.13
±.12

V
V
V

;!:.13

Note 1: The maximum junction temperature of the LM1558A is 150oC. while that of the
LM1458A is tOOoC. For operating at elevated temperatures. devices in the TO-5 package

must be derated based on a thermal resistance of 150oCIW. junction to ambient or 450 CIW.
junction to case, For the DIP the devices must be derated based on a thermal resistance of
187oC/W junction to ambient.
Note 2: For supply voltages less than t 15V. the absolute maximum input voltage is equal
to the supply voltage.
Note 3: These specifications apply for Vs '" 1. 15V and -550C ~ T A~ 1250 C, unless otherwise specified. With the LM1458A. however. all specifications are limited to ODe:S:T A ~
700C and Vs '" t.1SV.

2-263

Performance Curves

v+ = +15V. V- = -15V. TA = +250 C Unless Otherwise Stated.

OutpUt Volt... Swing vs F......enc:y

t=128~L

100
1111111

~

IIIIIIUI

;(

111111111

... 60

GAIN

;80

..'"'"

00

.,

0
~

,!,

45 0

Vo = 18V

~ 10

~ 40

...>

PHASE'

~2O.

*
z

100

Ik

10k
lOOk
1M
FREQUENCY (Hz)

10M

-

'"z

I 35 0

~I 0

I 80 0

'"~

0
-201
10

~

100M

!

o

.0 I
100

•

-

,

I'

(VOLTAGE FOLLOWER)
RL = 2k
CL = 50pF

~

:-

Normalized AC ParI_ten vs Supply Volt_II

~Y~=±.I.5V
~~S'±IOV
VS' +5V
VS= +2V

I

>
...~D.
1o

"Ci

VO· 2V

....

::.

"

Vo = 8V

o

90 0

[J1111L

' . ...llJlJ.J..IL

1111111
Ik

1

illWU

"

J

10k
FREQUENCY (Hz)

lOOk

1M

Normalized AC Plrlln.tan vs Temperatura

I.I

1

"'>
w
_
o:~

t;

:IE

:"'t
0
..

"w
:; ....

A'
Y

~ ~O.9

ffie

~ffi
~ :;
a: ...

:lew

/

o.8

o. 7

o

V VV

1/ BANOWIOTH

J

ow
zo:

V

1
SLEW RATE

0:::.

1

1

±5

±Io
SUPPLY VOLTAGE

±15

!20

P_er Supply Current VI Temperature

Input Noi.. Volt... VI Frequency
3.0

O~

O~
0
0

f'0.

..
.:z

"- N

: onS,URCE

2.5

e

IOkl1S0URCE RESISTANCE

w 2.0

0:
0:

iESI~

::.
'-'

1.5

k-'

VV

-:::: :.,....i-"""
~,

r0
10

100

1k

FREQUENCY (Hz)

2-264

10k

lOOk

Vs = ±2oV j....-- I--""
I-- I-- rvs = ±ISV l - I--""
V V ~ f- t- r-VS~": j::: I~V_ t- ~
....,- V ~ l- t-

I. 0
-55

.--

~ I;;::: r- r-

VS= ±2V
1

I I

-- r- -

1

-25

o
+25
+50
TEMPERATURE (DC)

+75

+125

HARRIS

Operational Amplifiersl Buffers

LM2908;Quad Op Amps

General Description

Features

The LM2908 consists of four independent, high gain,

internally conpensated. low power operational amplifiers
which have been designed to provide functional characteristics similar to those of the familiar 741 operational
amplifier. In addition, the total supply current of all
four amplifiers is comparable to the supply current of a

single 741 type ap amp. Also, excellent isolation between
amplifiers has been achieved by independently biasing
each amplifier and using layout techniques which minimize
thermal coupling.
The LM2908 can be used anywhere multiple 741 or

1558 type amplifiers are being used and in applications
where amplifier matching or high packing density is

•

741 ap amp operating characteristics
4.0mAlPackage

•

Low supply current drain

•

Class AS outfJut stage-no crossover distortion

•

Pm compatible with the LM348

•

Low input offset voltage

lOmV

•

Low input offset current

200nA

•

Low input bias current

250nA

•

Gain bandwidth product
(unity gam I

•

High degree of isolation between
amplifiers

•

Overload protection on all outputs

required.

Schematic and Connection Diagrams

3.5

MH~

120 dB

Section 11 for Packaging
Dual-In-Line Package

Rl

3.

01'j-""'--i~":0=-'------+--f:' 03

OUT 1_1===:;-'

r-;:==~_OUT4
14

lN4

lN 1

13

IN1+-i----'

'----t-

1N4+

12

v_

IN2+-~--"""

.----t-IN3+
lN 3

lN'

OUT 27t:==:.__~===r.- OUT 3
TOP VIEW

Order Number LM2908J
Order Number LM2908N

2-265

•

ex>

o

Absolute Maximum Ratings

en

N

~

..J

1SOoC

Supply Voltage

±'18V

Maximum Junction Temperature tT,MAX)

Differential Input Voltage

!Ys

Operating Temperature Range

Input Voltage

!,v.

Storage Temperature Range

Output Short Circuit Duration (Note 11

Continuous

Lead Temperature (Soldering. 60 secondsl

Power DisSIpation (P. at 2SoCIand
Thermal Resistance IO,A I. (Note 21
Molded DIP (NI
Pd
O,A
Cavity 01 P (JI

ooe::; TA::; +700e
--{iSoC to 'ISOoC

900mW _
lOB o C/W

p.
O,A

900mW
l00°C/W

Electrical Characteristics

(Note3)
LM2908
CONDITIONS

PARAMETER
Input Offset Voltage

IRs

MIN

Unless Otherwise

~10km

Specified: Vs = .!:: 15V
TA = +25 0 C _

Input Offset Current

Input Bias Current

•

300'C

TVP

MAX

UNITS

6

10

mV

100

200

nA

250

SOD

nA

O.B

2.5

M!l

25

4
160

mA
V/mV

-120

dB

Small Signal Bandwidth

1.0

MHz

Phase Margin

60

Slew Rate

0.5

Input Resistance
SupplV Current All Amplifiers

Large Signal Voltage Gain

VOUT = 1: 1OV. R L~ 2 k n
f· 1 Hz to 20 kHz

Amplifier to Amplitrer

Input Referred

Coupling

Unless Otherwise

IRs ~IO knl

VII's
mA

25

Output Short Circuit Current
Input Offset Voltage

degrees

14

mV

250

nA

Specified: Vs· !:15V
OOC~TA!O+700C

Input Offset Current

ILM29081

600

Input Bias Current

VOUT· .!::IDV. AL >2 kSl

Lilrge Signal Voltage Gain

RL

> 2kU

15

Output Voltage Swing

AL = lDkH
AL=2kSl

.t.12
.tID

Input Voltage Range

nA
V/mV

'13
.12

V
V
V

"12

Common·Mode Rejection
Ratio

As~ID kf!

70

90

dB

SupplV Voltage Rejection

As ~10 k f!

77

96

dB

Note 1. Any of the amplifiar outputs can be shorted to ground indefinitely; however. more than one should not be simultaneouslv shortild as the
maximum junction temperature will be exceeded.
.
Not.2: The maximum power dissipation for these devices must be derated at elevated temperatures and is dictated by TiMAX. 8jA.and the
ambient temperature. T A. The maximum evailable power dissipation at any temparature is Pd = (TjMAX - TAII8jA or the 25"C PdMAX. whichever is less.

Note 3: These specifications apply for Vs
noted.
-

2-266

= ± 15V and ovar tha absolute maximum operating temparatura range (TL S; T AS; TH) unless otherwise

;II

HARRIS

Operational Amplifiersl Buffers

LM4250/LM4250C Programmable Operational Amplifier
General Description
The LM4250 and LM4250C are extremely versatile
programmable monolithic operational amplifiers.
A single external master bias current setting resistor
programs the input bias cummt, input offset cur·
rent, quiescent power consumption, slew rate,
input noise, and the gain·bandwidth product.
The device is a truly general purpose operational
amplifier.

Features
• ±lV to ±18V power supply operation
• 3 nA input offset current

•
•
•
•
•
•

Standby power consumption as low as 500 nW
No frequency compensation required
Programmable electrical characteristics
Offset Voltage nlJlling capability
Can be powered by two flashlight batteries
Short circuit protection

The LM4250C is identical to the LM4250 except
that the LM4250C has its performance guaranteed
over a O°C to 70°C temperature range instead of
the _55°C to +125°C temperature range of the
LM4250.

Schematic Diagrams

•

Typical Applications

..."

v.,

..

v.,

.

'

.....

,

Quiescent Po = 1.5 mW

-II.

X5 Difference Amplifier

v.

"

_

v.

-=

Qu~t

p... SOD nW

500 Nano·Watt X10 Amplifier

Connection Diagrams

Section 11 for Packaging
Dual·ln·Llne Pockage

Metal Can Package
aUlucltlt

"':::'8':::::-.1'11'

CURRlNrsn

IDV':I

.I....... ERTI.. I

.

"'"

IV-

+

• 'UDUT

.t.,m

V"4

lULL

ta'VlIW

Order Number LM4250H or LM4250CH

Order Number LM4260CN
Order Number LM4250J
or LM4250CJ

2-267

absolute maximum ratings
Supply Voltage
Pow'r DiSSipation (Note 1)
Differential Inpu. Vol'age
Input Voltage INa•• 2)
ISET Current

.,BV
600mW
tlOV
t15V
lSO,.A

electrical characteristics

Output Short·Circuit Duration
Operating Temperature Range

s:

Indefinite

-55'C TA s: 125'C
O'CS:TA S:70'C

lM4260

LM4250C

-65°C to 1SOoe
3OO'C

Storage Temperature Range
Lead Temperature (Soldering,10 sec)

LM4250 (_55°C ~ T A ~ 125°C unless otherwise specified)
VS-·I.SV

PARAMETERS

MIN
Vas

T A - 2S' Rs

los
I._

TA a 2SG
TA-2So

Large Signll Vol'age Glin

MAX

s: IllClkG

TA -2So RL -l00kG

lIE, ·,0/J.A

ISET-ljlA

CONDITIONS

MIN

3nA

10nA

7.SnA

SOnA

2OKV{V
2OKV{V

Va' to.6, RL • 10 kG

•

MAX
6mV

3mV

Supply Current

TA " 25°C

20jlA

Power Consumption

TA - 26'C

eojlW

Vos

RsS: 100 kG

4mV

6mV

los

TA "25'C

SnA

10nA

TA

3nA

10nA

7.5nA

SOnA

•

-SSoC

1.100

3GOjlW

to.7V

Inpu. Vol'age Ringe
Large Signal Voltage Gain

120p..A

Vo - '0.6V RL '. l00Ul

to.7V

10KV/V
10KV!V

RL ·10kn

Ou'pu. Voltage Swing

RL -100kG

to.6V
to.6V

RL"'0kG
Common Mode Rejection Rltio

RsS: 10 kG

70dB

Supply Volttge Rejection Ratio

RsS: 10 kG

76dB

Supply Current

70 dB
76 dB
200jlA

20jlA

Pow.r Conlumption

eojlW

600 jlW

V.-tI6V
PARAMETERS

IBET -lOIlA

!sET-ljlA

CONDITIONS
MIN

MAX

MIN

MAX

Vos

TA -25'C RsS: 100 kG

3mV

SmV

los

TA " 26'C

3nA

10nA

I...

TA " 2S'C

7.SnA

SOnA

Lerge Signe' Voltage Glin

TA " 26°C RL -l00kG

30KYN
30KVN

Vo - ±10V RL ·10ktl

210jlA

SUpply Current

T A ' 2S'C

25P.A

Power Consumption

T A -2S'C

300jlW

2.7mW

Vos

RsS: 100 kG

4mV

6mV

los

T A "25'C

25nA

25nA

TA " -55'C

3nA

10nA

7.5nA

SOnA

1±13.5V

Input Voltage Ringe
llrge Signel Voltage Glin

Vo - tl0V RL " 100 kG
RL -l0kG

2O"KVN

Output Voltage Swing

RL -100kG

±12V

Common Mode Rejection Retia

RsS: 10kG

70 dB

Supply Voltege Rejection Retia

RsS: 10kG

76dB

±13.5V
2OKY"N

RL -10kG

"2V
70dB
76 dB

Supply Curr.nt

25jlA

Power Consumption

160 IlW

2SO jlA
1.6 mW

NOl. 1: The maximum junclion temperature of the lM4250 is 150'C, while that of the lM4250C is 100'C. For operating
at elevated temperatures, devices in the TO·5 package must be derated based on a thermal resistance of 150'C/W junction to
ambient, or 45'CIW junction to case. The lhermal resistance, of the dual·in·line"package is 125'CIW.
Note 2: For supply yoltages less than ±15V, the absolute maximum input voltage is~equal to the supply voltage.

2-268

i
electrical characteristics

~

LM4250e (o·e ~ TA ~ 70·e unless otherwise specified)

N
U'I

Vs-,01.5V
PARAMETERS

CONDITIONS

ISIT -I ~A
MIN

ISET-10",A

MAX

MIN

MAX

Vos

TA ' 2S'C RsS: l00kO

5mV

6mV

los

TA ' 2S'C

6nA

20nA

10nA

75nA

'bll.

TA -25'C

Large Signal Voltage Gain

TA -25°C RI.-100kfl

Supply Current

T A -25'C

Power Consumption

TA ' 2S'C

601IJW

Vos

R.:S:l0kO

6.SmV

2SkV/v

Vo' ,o0.6V RL ' 10 kO

~
~

N

UI

o
n

25k v/v
20~

120 1l'A

270pW
360

SnA

los

SOnA

,o0.6V

Input Voltage Range

Vo' ,o0.6V RL ' 100 kO

mV

2SnA

10nA

'bll'
Large Signal Voltage flain

o
.....
r-

,o0.6V

2Skv/V

RL ' 10 kO

2Skv/V

Output Voltage Swing

RL ' 100 kO
RL -l0kO

,oO.6V

Common Mode Rejection Ratio

Rs

s: 10 kO

70dS

Supply Voltage Rejection Ratio

RsS: 10kO

74dB

to.6V

Supply Current

70dS

Power Consumption

II

74 dB
20pA

120uA
600 uW

60PW
VS·tI5V

PARAMETERS

ISIT -I ~A

CONDITIONS
MIN
T A • 25'C lis

Vos

s: 100 kO

ISET-l0pA
MAX

MIN

5mV

MAX
6mV

TA ·26°C

6nA

20nA

I bil•

TA ' 25'C

10nA

75 nA

Large Signal Volt. Gain

TA - 25'C RL - 100 kO

'0 •

25 KV/V

Vo' tl0V RL - 10 KO

25 KV/V

Supply Current

TA -25"C

2SpA

Power Consumption

TA - 25'C

33O~W

3mW

Vos

R.

6.5mV

7.5mV

s: 10 kO

2101IJA

loa

BnA

25nA

I,..

10nA

BOnA

Input Voltage Range

tI3.SV

Large Signil Voltage Gain

Vo - .IOY RL - 100 kO
RL • 10k{!

Output Voltage Swing

RL - 100 kO

Common Mode Reiection Ratio
Supply Voltage ReJection R.tio

R.s: 10 k{!

70dS

R.S: 10kO

74 dB

"3.5Y

20KV!V

20KV/V
.12V

RL -l0kO

.12V

Supply Current

70dB
74 dB
25uA

Power Consumption

750luW

25c>uA
7.5mW

resistor biasing
Set Current Setting Resistor to VISIT
Va

O.I~

.1.SV
!3.0V
.6.0V
.9.0V

2S.6 MO
65.6 MO
116MO
178MO
238 MO
286MO

.'2.0V
.'5.0V

O.spA
S.04MO
1I.0MO
23.0MO
35.0MO
47.0MO
68.0 MO

1.0~A

5pA

10~A

2.5MO
5.5MO
1I.5MO
17.5MO
23.5 MO
28.SMO

492 kO
I.09MO
2.28 MO
3.49 MO
4.68MO
5.68 MO

244 kO
544 kO
1.14 MO
1.74 MO
2.34 MO
2.94 MO

2-269

Typical Performance Characteristics
Input Offset Current vs
T emperatu re

Input Bias Current VI

Temperature

Input Bias Current vs 'SET
-40

.000
TA " 25"C

-3D

I I I

I I I

ISET= lDp.A

Vs "tl.5V

Vo- ".S~

.0

j

!
j

Vo-,'SV

I I I

Unnulled Input Offset Voltage
Change V5 ISET

•

~

.

I=_::PT]AIII•zIlt:s·=c::r:mm

-

&1>
...

~~
~ "
" ~

~ ~

i"!5

.

~

1I.·5V':6:---0

~Y4

=

-18V)

APPLICATIONS INFORMATION
OP·07 Senes units may be fitted directly to 725, I 08A/308A' and
OP·05 sockets with or without removal of external compEmsation or
nulling components. Additionally, OP·07 may be fined to unnulled
741-type sockets; however if conventional 741 nulling circUItry is in
use, it should be modified or removed to enable proper OP-07 operation. OP·07 offset voltage may be nulled to zero (or other desired
setting) through U!~. of a potentiometer (see diagram above).

'''J'' Package Only.

2-274

The OP-07 provides stable operation with load capacitances up ,to
500pF and! IOV swings; larger capacitances should be decoupled
with a 50n decQuphng resistor. The designer is cautioned that stray
thermoelectric voltages generated by dissimilar metals at the contacts to the input terminals can prevent realization of the drift
performance indicated. Best operation will be obtaoned when both
input contacts are maintained at the same tempe'rature. preferably
.close to the temperature of the device's package.

HA-5141/42/44

HARRIS

Ultra-Low Power
Operational Amplifier
FEATURES

DESCRIPTION
The HA-5141/42144 ultra-low power operational amplifiers provide
AC and DC performance characteristics similar to or better than
most general purpose amplifiers while only drawing 1/30 of the
supply current of most general purpose amplifiers. These amplifiers are well suited to applications which require low power
dissipation and good electrical characteristics.

60fJA
• LOW SUPPLY CURRENT
2V to 30V
• WIDE OPERATING VOLTAGE RANGE
• SINGLE SUPPLY OPERATION
1.5V 1fJs
• HIGH SLEW RATE
100K V/V
• HIGH GAIN
• AVAILABLE IN SINGLES, DUALS AND QUADS

APPlICA TlONS
•
•
o
•
•

•

The HA-5141/42144 provides accurate signal processing by virtue
of its low input offset voltage ( 0.5mV), low input bias current
(50nA), high open loop gain (100KV/V) and low noise, for low
power operational amplifiers (20nV.(jfiZl These characteristics
coupled with 1.5V / fJ s slew rate and 400KHz bandwidth make
the HA-5141/42144 ideal for use in low power'instrumentation,
audio amplifier and active filter designs. The wide range of supply
voltages (2V to 30V) also allow these amplifiers to be very useful in low voltage battery powered equipment.

PORTABLE INSTRUMENTS
METER AMPLIFIERS
TELEPHONE HEADSETS
MICROPHONE AMPLIFIERS
INSTRUMENTATION

These amplifiers are available in singles (HA-5141, can or minidip),
duals (HA-5142, can or minidip) or quads (HA-5144, 14 pin dip)
with ,industry standard pinouts which allow the HA-5141/42144's
to be interchangeable with most other operational amplifiers.

PINOUTS
TOP VIEW

TOP VIEW

NiC

TOP VIEW

v-

v-

2-275

SCHEMATIC

~~
I

-""

L.:::

\

-IN

C~

tL5

+v

JJ
[

~

r--

'>-"OUTPUT

+IN

-4

+V

~

t1

f

-V

SPECIFICA TIONS
ABSOLUTE MAXIMUM RATINGS
Voltage Between V+ and V- Terminals
Oifferentiallnput Voltage
Output Current
Internal Power Oissipation

40V
±7V
SIC Protected
500mW

ELECTRICAL CHARACTERISTICS V+

Operating Temperature Range
Storage Temperature Range

=+5V
HA-5141/42/44A

PARAMETER
INPUT CHARACTERISTICS
Offset Voltage

MIN

Common Mode Range

oto 4

TRANSFER CHARACTERISTICS
Large Signal Voltage Gain
(Note 1)
Common Mode Rejection

+25 0 C
Full
Full

50
30
80

Full

oto 4

+25 0 C

1

Offset Current

OUTPUT CHARACTERISTICS
Output Voltage Swing
(Note 1)
TRANSIENT RESPONSE
Slew Rate
(Notes 1,2,3)
POWER SUPPLY CHARACTERISTICS
Supply Current (per Amplifier)
Power Supply Rejection
Ratio
NOTES:
1. RL=SOK
2. CL = SOp!
3. VIN:: +3V Pulse

2-276

TEMP.
+25 0 C
Full
+25 0 C
Full
+25 OC
Full
Full

Bias Current

OOC~TA~+750C
-550C~T A~+1250C
-650~TA~+1500C

+25 0 C
Full
Full

MAX

0.5

6
8
75
100
10
15

45
0.3

100

MIN

TYP

MAX

UNITS

0.7

7
9
100
125
10
20

mV
mV
nA
nA
nA
nA
V

45
0.3

oto 3
20
15
77

105

KV/V
KV/V
dB

100
105

Oto 3

1.5

45
80

HA-5141/42/44

TYP

105

0.5

V

. 50

65
75

77

Vips

1

105

80
100

pA
pA
dB

HA·5180/5180A

HaARRIS

~\)V~~l~\~
FEATURES'

Low Bias Current, Low Power
JFET Input Operational Amplifier

DESCRIPTION
250fA

• ULTRA LOW BIAS CURRENT

0.8mA

• LOW POWER SUPPLY CURRENT

0.5mV (max.)

• LOW OFFSET VOLTAGE
• BANDWIDTH

2 MHz

• SLEW RATE

7V/ !J,s

APPLICA TlONS
• ELECTROMETER AMPLIFIER DESIGNS
• PHOTO CURRENT DETECTORS
• PRECISION, LONG-TERM INTEGRATORS
• LOW DRIFT SAMPLE & HOLD CIRCUITS
• VERY HIGH IMPEDANCE BUFFERS
• HIGH IMPEDANCE BIOLOGICAL MICRO PROBES

PINOUT

The HARRIS HA-5180/5180A is an ultra low input bias current, JFET
input, monolithic operational amplifier which also features low power,
low offset voltage and excellent AC characteristics. Employing
FET /Bipolar construction coupled with dielectric isolation this
operational amplifier offers the lowest input bias currents (250fA
typ.) available in any monolithic operational amplifier. The HA5180/5180A has another unique feature in which the offset bias
current may be nulled by externally adjusting the offset voltage. For
applications which require precision performance the HA-5180A offers an input offset voltage of 0.5 mV (max) while the HA-5180 offers
3 mV (max.)
The HA-5180/5180A also offers excellent AC performance not
previously available in similar hybrid or monolithic op amp designs.
The 2 MHz bandwidth and 7V/Jjs slew rate of the HA-5180/5180A
extends the bandwidth and speed for applications such as very low
drift sample and hold amplifiers and photo-current detectors. Other
applications include use in electrometer designs, pH/Ion sensitive
electrodes, low current oxygen sensors, long term precision integrators and very high impedance buffer measurement designs.
The HA-5180/5180A is packaged in an 8-pin (TO-99) can and an 8lead cerdip and is pin compatible with most existing op amp configurations. The case of the TO-99 package is internally connected to
pin 8 so that it may be connected to the same potential as the input.
This feature helps minimize stray leakage to the case, helps shield
the amplifier from external noise and reduces common mode input
capacitance.

SCHEMATIC
TOP VIEW

r-1r---r----r--,---r----r--r---;-C

+Vee

CASE

t-f--'---+-D

Your

vBALANCE

ININ.

o

v-

8alance

2-277

•

I

SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

(Note 1)

TA = + 25°C Unless otherwise stated
Voltage Between V+ and V- Terminals
Differential Input Voltage·
Output Short Circuit Duration

ELECTRICAL RATINGS

•

Power Dissipation (Note 2)
Dperating Temperature Range
HA-5180/5180A-2
HA-5180/5180A-5
Storage Temperature Range

40.0V
±40V
Indefinite

V+

-55°C9A 9-125°C
OO~TA S+ 75°C
-65°CgA:5+ 150°C

= 15V, V- = -15V
51BDA-2

PARAMETER

300mW

TEMP.

MIN

51BDA-5

TYP

MAX

+25°C
Full
Full
+25°C
Full

0.1

0.5
1

+25°C
Full

30

MIN

TYP

MAX

UNITS

0.1

0.5
1

mV
mV

INPUT CHARACTERISTICS
Offset Voltage

Average Offset Voltage Drift
Bias Current (Note 3)

Offset Current (Note 3)

Common Mode Range
Differential Input Resistance
Input Noise Voltage (f = 1kHz)
Input Noise Current (f = 1kHz)

5
250
100

6

Full
+25°C
+25°C
+ 25°C

±10

+25°C
Full
Full
+25°C

+25°C
Full
+25°C
+25°C
+25°C

5
250

1000
500
200
30

±12
10"
70
0.01

±10

200k
150k
90

1M

200k
150k
90

±10
±10

±12

J.l.V/oC
1000

6

30

fA
pA

30
1

200
5

fA
pA

±12
10"
70
0.01

V

n

nV/~
pA/~

TRANSFER CHARACTERISTICS
Large Signal Voltage Gain (Note 4)
Common Mode Rejection Ratio (Note 5)
Closed Loop Bandwidth (AVCL = + 1)

110
2

1M

V/V
VIV
dB
MHz

110
2

OUTPUT CHARACTER;STlCS
Output Voltage Swing (Note 6)
Full Power Bandwidth (Note 7)
Output Current (Note 8)
Output Resistance (Note 9)

±10
±10

±12

±10

110
±15
25

±10

110
±15
25

4

75
7
2

4

75
7
2

V
V
kHz
mA

n

TRANSIENT RESPONSE
Rise Time
Slew Rate
Settling Time (Note 10)
POWER SUPPLY CHARACTERISTICS
Supply Current
Power Supply Rejection Ratio (Note ltl

2-278

+ 25°C
+ 25°C
+ 25°C

Full
Full

85

07
105

1
85

08
105

ns

V/J.l.s
J.l.s

1

mA
dB

SPECIFICATIONS (Continued)
ELECTRICAL RATINGS

V+ = 15V, V- = -15V
5180A-5

5180A-2
PARAMETER
INPUT CHARACTERISTICS
OIlset Voltage

TEMP.

MIN

+25°C
Full

TYP

MAX

1

3
4

Full
+ 25°C
Full

5
250
100

Offset Current rNote 3)

+25°C
Full

30

Common Mode Range
Differential Input Resistance
Input Noise Voltage (f = 1kHz)
Input Noise Current (I = 1kHz)

Full
+25°C
+25°C
+25°C

±10

+25°C
Full
Full
+25°C

200k
150k
90

+25°C
Full
+25°C
+25°C
+25°C

±10
±10

Average OIfset Voltage Drift
Bias Current (Note 3)

MIN

±12
10"
70
0.01

MAX

UNITS

1

3
4

mV
mV

6

30

mV
mV
J..I.V/oC
fA
pA

30
1

200
5

fA
pA

5
250

1000
500
200
30

6

TYP

±10

1000

±12
10"
70
0.01

•

V

.\1
nV/VHZ
pAlVHZ

TRANSFER CHARACTERISTICS
Large Signal Voltage Gain (Note 4)
Common Mode Rejection Ratio (Note 5)
Closed Loop Bandwidth (AVCL = + 1)

200k

1M

1M

V/V
V/V
dB
MHz

150k
110
2

90

110
2

±12

±10
±10

±12

OUTPUT CHARACTERISTICS
Output Voltage Swing (Note 6)
Full Power Bandwidth (Note 7)
Output Current (Note 8)
Output Resistance (Note 9)

±10

110
±15
25

±'10

75
7
2

4

V
V
kHz
mA

110
±15
25

.\1

TRANSIENT RESPONSE
Rise Time
Slew Rate
Settling Time (Note 10)
POWER SUPPLY CHARACTERISTICS
Supply Current
Power Supply Rejection Ratio (Note 11)

+25°C
+25°C
+25°C

Full
Full

4

85

0.7
105

1
85

75
7
2

0.8
105

ns
VIJ..I.s
J..I.s

1

mA
dB

NOTES:
1. Absolute maximum ratings are limiting values, applied individually
beyond which the serviceability of the circuit may be impaired. Functional operability under any of these conditions is not necessarily
implied.
2.

Derate at 6.9 mW/oC for operation at ambient temperatures above
+ 75°C.

7.

RL = 2k; Full power bandwidth guaranteed based on slew rate
measurement using FPBW = SLEW RATE
21TVpEAK

8.

VOUT = ± 10V.

9.

Oulput resistance measured under open loop conditions (f = 100H2.)

10.

Settling time is measured to 0.1 % of final value lor a 10V outpul
stepandAV = -1.

11.

VSUPP = + 5V D.C. to ±20V D.C.

3. This parameter is guaranteed by design and is not 100% tested.
4. VOUT =±10V; RL =2k. Gain dB = 20 log 10Av.
5. VCM=±10VD.C.
6. RL = 2k

2-279

APPLICATION HINTS
The HA-5180/5180A offers one of the lowest input bias currents of
any monolithic operational amplifier and is ideal for use in applications for measuring signals from very high impedance or very low
current sources. To fully utilize the capabilities of the HA5180/5180A care should be taken to minimize noise pickup and current leakage paths with the use of shielding and guarding techniques
and by placing the device as close as possible to the signal source.
The small size and low quiesent current (possible battery operation)
of the HA-5180/5180A allows easy installation at the Signal source or
inside a probe. The HA-5180/5180A is internally compensated and.
is capable of driving long signal cables which have several hundred
pF capacitive loading.
Guarding is achieved by applying a low impedance bootstrap potential to a shield which surrounds the high impedance signal line. This
bootstrap potential should be held at the same potential as the Signal
source to eliminate any voltage drop (therefore, zero leakage currents) across the insulation (Ref to Fig 1 & 2). For lowest leakage at
the device either use a teflon IC socket or connect the high impedance signal line to the HA-5180/5180A inputs using teflon standoffs. If neither of these options are feasible, a guard ring, as shown
in Fig. 3, applied to both sides of the pc board and bootstrapped to
the same potential as the input signal will minimize leakage paths
across the pc board. Pin 8 of the TO-99 can, which is internally tied
to the case, should also be tied to the bootstrap potential to help
minimize noise pickup and leakage currents accross the package insulation. This technique will also reduce common mode input
capacitance.
.

•

Cleanliness of circuit boards and components is also important for
achieving low leakage currents. Printed circuit boards and components should be thoroughly cleaned by using a low residue solvent
such as TMC Freon, rinsed by deionized water and dried with
nitrogen. The circuit board should be protected from high contamination and high humidity environments.
Input protection is generally not necessary when designing with the
HA-5180/5180A. Many electrometer type devices, especially CMOS,
require elaborate zener protection schemes which may compromise
overall performance. The Harris dielectric isolation process and JFET
input design enables the HA-5180/5180A to withstand input signals
several volts beyond either supply and large differential signals equal
to the rail-to-rail supply voltage without damage or degredation of
performance.
v-

.1

INPUTS

0

o·

'0

o

~OUT

•

GUARD

,0
Figure 3 GUARD RING

EX~PLE

\
y+

.
SHIELD

>=--+--,------0 OUT

~-----------------.

1

Filll1'l2 VERY HIGH IMPEDANCE NON-INVERTING AMPLIFIER

2-280

Figure 5 SUGGESTED OFFSET ADJUSTMENT CIRCUIT

CMOS
Analog Svvitches

...................................ILI1..I1

.....

PAGE
Glossary
Selection Guide
HI-200
HI-201
HI-201HS
H 1-300 thru 307
H 1-381 /384/387/390
H 1-5040 th ru 5051
HI-5046A and HI-5047A

Dual SPST CMOS Analog Switch
Quad SPST CMOS Analog Switch
High Speed Quad SPST CMOS Analog Switch
CMOS Analog Switches
CMOS Analog Switches
CMOS Analog Switches
CMOS Analog Switches

3-2
3-3
3-4
3-10
3-16
3-19
3-24
3-29
3-29·

II
I

ABSOLUTE MAXIMUM RATINGS

As with all semiconductors, stresses listed under "Absolute Maximum Ratings" may
be applied to devices (one at a time) without resulting in permanent damage. This
is a stress rating only. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. The conditions listed under "Electrical
Characteristics" are the only conditions recommended for satisfactory operation.

3-1

Analog Svvitches Glossary

ANALOG SIGNAL RANGE (i Vsl. - The maximum safe
input voltage range.
BREAK-BEFORE-MAKE-DELAY (tOPENI - The elapsed
time between the turn-off of one switch and the corresponding turn-on of another switch for a common change
in logic state. This delay is measured between the 50%
points of the output transitions.
CHANNEL INPUT CAPACITANCE (CSOFFI The capacitance between the analog input and ground with the
channel "OFF."
This capacitance consists primarily of
the source-body capacitance.
CHANNEL OUTPUT CAPACITANCE (CDOFFI
The
capacitance between the analog output and ground with
the channel "OFF". This capacitance consists of the sum
of the drain-body capacitances.

•

CHANNEL OUTPUT CAPACITANCE (COON I - The capacitance between the analog output and ground with the
channel "ON".
CHARGE INJECTION - The amount of charge transferred
to a specified load capacitance due to the switch changing
state.
CROSSTALK - The amount of cross coupling from an
"OFF" analog input to the output of another "ON"
channel output.
DIGITAL INPUT CAPACITANCE - The capacitance
between a digital input and ground.
INPUT LOW LEAKAGE CURRENT IIALI - The current
measured at the digital input with a logic low applied.
INPUT LOW THRESHOLD (VALl - The maximum allowable voltage that can be applied to the digital inputs
and still be recognized by the device as a low input.
INPUT HIGH LEAKAGE CURRENT (lAHI - The current measured at the digital input with a logic high applied.
INPUT HIGH THRESHOLD (VAHI - The.minimum voltage that can be applied to the digital inputs and still be
recognized by the device as a high input.

3-2

INPUT TO OUTPUT CAPACITANCE (CDSOFFI - The
capacitance between the analog input and output when the
channel is "OFF".
"OFF" INPUT LEAKAGE CURRENT IISOFFI - The
current measured at the input of an "OFF" channel with a
a specified voltage applied to both input and output. This
current consists largely of the diode leakage current of the
source- body junctions.
OFF ISOLATION - The feedthrough of an applied signal
through an "OFF" switch to the output. This feedthrough
occurs through the source-body and drain-body capacitances and has a greater effect at high frequencies.
"OFF" OUTPUT LEAKAGE CURRENT (lDOFFI - The
current measured at the output of an "OFF" channel with
a specified voltage applied to both input and output. This
current is due largely to the diode leakages of the drainbody junctions.
"ON" CHANNEL LEAKAGE CURRENT IIDONI - The
current flowing through the source-body and drain body
junctions of the "ON" channel. This current is measured
with a specified voltage applied to both the input and
output.
"ON" RESISTANCE (RONI - The series "ON" channel
resistance measured between the input and output terminals under a specified range of input voltages.
SUPPLY CURRENT IIsl - The current required from the
power supply to operate the switch in a no load condition.
SWITCH TURN "OFF" TIME hOFFI - The time required
to deactivate an "ON" switch to an "OFF" state. This
time is measured from the 50% point of the logic input
change to the time the output reaches 10% of the initial value.
SWITCH TURN "ON" TIME (toNI - The time required
to activate'an "OFF" switch to an "ON" state. This time
is measured for the 50% point of the logic input to- the
time the output reaches 90% of the final value.

CMOS Switches Selection Guide
RON (n)

IO(OFF)(NA)

t(ON)(NS)

t(OFF)(NS)

Po(mW)

(TYP)

(TYP)

(TYP)

(TYP)

(TYP)

HI-5040

50

0.5

370

280

1.5

HI-200

55

1

240

180

15

HI-300

35

0.04

210

160

1

HI-304

35

0.04

210

160

0.3

HI-381

35

0.04

210

160

1

HI-5048

25

0.5

370

280

1.5

370
180 .

280

1.5 ,

30

40

FUNCTION

OEVICE

SPST
2 x SPST

4 x SPST
SPOT

HI-5041

50

0.5

HI-201
HI-201HS

55
30

1
0.3

HI-301

35

0.04

210

160

1

HI-305

35

0.04

210

160

0.3

HI-387

35

0.04

210

160

1

HI-5050

25

0.5

370

280

1.5
1.5

155

15
120

HI-5042

50

0.5

370

280

HI-303

35

0.04

210

160

1

HI-307

35

0.04

210

160

0.3

HI..,390

35

0.04

210

160

1

HI-5051

25

0.5

370

280

1.5

HI-5043

50

0.5

370

280

'1.5

OPST

HI-5044

50

0.5

370

280

1.5

2 x OPST

HI-302

35

0.04

210

160

1

HI-306

35

0.04

210

160

0.3

HI-384

35

0.04

210

160

1

HI-5049

25

0.5

370

280

1.5

HI-5045

50

0.5

370

280

1.5

HI-5046A

25

0.5

370

280

1.5

HI-5046

50

0.5

370

280

1.5

HI-5047A

25

0.5

370

280

1.5

HI-5047

50

0.5

370

280

1.5

2 x SPOT

OPOT
4PST

II

I

NOTE: All data represents typical room temperature specifications at :!: 15V supplies. For guaranteed
and tested specifications, consult the device data sheet.

3-3

m~RIS

HI-200
Dual SPST CMOS Analog Switch

FEATURES

DESCRIPTION

•

ANALOG VOLTAGE RANGE

±15V

•

ANALOG CURRENT RANGE

BOmA

•

TURN-ON TIME

240ns

•

LOW RON

•

LOW POWER DISSIPATION

•

TTL/CMOS COMPATIBLE

55n

15mW

APPlICA TlONS

•

HIGH FREQUENCY ANALOG SWITCHING

•

SAMPLE AND HOLD CIRCUITS

•

DIGITAL FILTERS

•

OPAMP GAIN SWITCHING NETWORKS

HI-200 is a monolithic device comprising two independently
selectable SPST switches which feature fast switching speeds
(290ns) combined with low power dissipation (15mW at 250C).
Each switch provides low "ON" resistance operation for input
signal voltages up to the supply rails and for signal currents
up to 80mA. Employing Dielectric Isolation and CMOS processing, H1-200 operates without any applications problems induced by latch-up or SC R mode phenomena.
All devices provide break-before-make switching and are TTL
and CMOS compatible for maximum application versatility.
H1-200 is an ideal component for use in high frequency analog
switching. Typical applications include signal path switching,
sample and hold circuit, digital filters,and op amp gain switching
networks.
HI-200 is available in DIP and metal (TO-l00) cans. HI-200-2
is specified from -55 0C to +125 0C while HI-200-5 operates
from OOC to +750C. HI-200 is functionally and pin compatible
with other available "200 series" switches.

PINOUT

FUNCTIONAL DIAGRAM
Section 11 for Packaging

.-----0 IN 1

Top View
A2

v+

'~f"

Al

:~Vl:

IN 1

NC

2

13

NC

GNO

3

12

V.

NC

4

11

NC

IN 2
OUT 2

v-

I

I

~---t-u OUT 1

SWITCH OPEN
. FOR LOGIC HIGH

OUT 1

VREF

....----+-u IN 2

L . . - - - - - ( J OUT 2

3-4

SPECIFICATIOIVS
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
VREF to Ground
~igital Input Voltage:
Analog Input Voltage (One Switch)

44V (±22)
+20V. -5V
+VSupply +4V
-VSupply -4V
+VSupply +2.0V
-VSupply -2.0V

Total Power 0 issipation*
Operating Temperature
HI-200-2
HI-200-4
HI-200-5
Storage Temperature

450mW
-55 0C to +125 0C
-200C to +S5 0C
OOC to +75 0C
-65 0C to + 150 0C

*Oerate 6mW/OC Above TA =75 0C

ELECTRICAL CHARACTERISTICS
Unless Otherwise Specified
Supplies =+15V. -15V; VREF =Open; VAH(Logic Level High) =2.4V VAL(Logic Level Low}
For Test Conditions. consult Performance Characteristics
HI-200-2

=+O.SV
HI-200-5

*.

-55°C to +125 0 C
TYP.
MAX.
MIN.

OOC to +75 0 C
MIN.
TYP.
MAX.

-15

-15

UNITS

PARAMETER
ANALOG SWITCH CHARACTERISTICS
VS. Analog Signal Range

TEMP.

+15

V

RON. On Resistance (Note 11

+25 0 C
Full

55
80

70
100

55
72

SO
100

Sl

n

IS (OFF). Off Input Leakage Current
(Note 6)

+25 0C
Full

1
100

500

1
10

500

nA
nA

IO(OFF). Off Output Leakage Current
(Note 6)

+25 0 C
Full

1
100

500

1
10

500

nA
nA

IO(ON). On Leakage Current (Note 6)

+25 0 C
Full

.02
6

500

.02
6

500

nA
nA

Full

DIGITAL INPUT CHARACTERISTICS
VAL. Input Low Threshold
VAH. Input High Threshold

Full
Full

IA.lnput Leakage Current (High or LoW) (Note 2)

Full

+15

0.8
2.4

0.8

V
V

1.0

/.lA

2.4
1.0

II

SWITCHING CHARACTERISTICS
60

ns

500

240

ns

500

500

ns

70

dB

5.5

5.5

pF

5.5

5.5

pF

+25 0 C

11

11

pF

CA. Digital Input Capacitance

+25 0 C

5

5

pF

CDS (OFF). Drain-To-Source Capacitance

+25 0 C

0.5

0.5

pF

POWER REQUIREMENTS (Note 5)
PD. Power Dissipation

+25 0 C
Full
+25 0 C
Full
+25 0 C
Full

15

15

mW
mW
mA
rnA
rnA
mA

tOPEN. Break - Before Make Delay (Note 3)

+25 0 C

ton. Switch on Time

+25 0 C

240

toff. Switch off Time

+25 0 C

330

"Off Isolation" (Note 4)

+25 0 C

70

Cs (OFF). Input Switch Capacitance

+25 0 C

CD (OFF). {

+25 0 C

CO(oN).

Output Switch Capacitance

1+. Current
1-. Current
NOTES:

1. VOUT= ±10V lOUT = 1mA
2. Digital Inputs Are MOS Gates - TYPical Leakage Is

Less Than 1 nA
3. V AH = 4.0V

60

60
0.5

2.0

60
0.5
0.5

0.5
2.0

2.0
2.0

4. V A = +5V. RL = 1KSl. c L = 10pF. Vs = 3VRMS.
f = 100kHz
5. V A = +3V or V A = OV For Both Switches
6. Refer to leakage current measurement diagram

on page (3-81

,....

Note:

HI-200-4 has same specifications as HI-200-5 over the temperature range -20oC to +850C.

3-5

SCHEMATIC DIAGRAMS
TTL/CMOS
REFERENCE CIRCUIT

SWITCH CELL

V-REF CELL

A·>---------~----------~~__,

OUTPUT

R4

GNO

A'~----------~--------~

V+

DIGITAL INPUT BUFFER
AND LEVEL SHIFTER

......--t-+--. A'

200n

'----l-+---t--t--.ii'
ALL N-CHANNEL
BODIES TO VALL P-CHANNEL
BOOtES TO V+
EXCEPT AS SHOWN.

V-

PERFORMANCE CHARACTERISTICS AND TEST CIRCUITS
(UNLESS OTHERWISE SPECIFIEO TA =25°C, VSUPPL Y =± 15V, VAH

=2.4V VAL =O.8V ANO VREF =OPEN).

ON RESISTANCE vs. ANALOG SIGNAL LEVEL,
SUPPLY VOLTAGE ANO TEMPERATURE

.-

V2
RON· j;;;A

.

V2

,....

IN

"1-

.t,vIN

1 mA

OUT
HI-200

ON RESISTANCE vs. TEMPERATURE
80
70

~

vIN·OV

60

E

.t::

..
..'"

0

50

.--~

I

u

c

t:
.;;;
co::
c

40
30

--

~

-----

~

~

•

0

20
10
0

-50

-25

+25

0

+50

+75

+100

+125

Ambient Temperature _oC

(HI-200)
ON RESISTANCE vs. ANALOG SIGNAL LEVEL
ANO POWER SUPPLY VOLTAGE
100

~

E

.t::

..
'"
..

0

"

I

u

C

.~

50

co::
c

0

0
-15

---

-10

.......

--5

I
V+ = +lDV
v- = -10V

- -..".

f--"

V+: +12.5V

""

V---12~V+=+15V

V_·-15V_ _

,..

-~

0

+5

+10

+15

Analog Signal Level - Volts

3-7

I

PERFORMANCE CHARACTERISTICS AND TEST CIRCUITS (Continued)

SWITCH LEAKAGE CURRENT vs.
TEMPERATURE (HI-20D)
100

/

/

OFF LEAKAGE CURRENT
Ys. TEMPERATURE

"

V

IsIOFF)

/
ISIOFF)/IOIOV

±14V

+10V

t~JF

I\.

300

E

.§
en

6

f+ BREAK-BEFORE-MAKE

~

i=

"§

r--

--

I-

~

.n

MAKE BEFORE - _
BREAK

lK~

VA

2_5

3_0

3_5

4_0

4_5

OUT

:::;:: 35pF

>

-

100

0

0

HI-200

,-dN- 24L_ I f"""'o. ..........

200

IN

-

5_0

TTL Logic Level (V AH) - Volts

•

SWITCHING WAVEFORMS
DIGITAL
INPUT

VA =4.0V

\

50%

1\

VA = O.OV

J

~O%
-tOFF-

-tON
SWITCH
OUTPUT

'\r

90%

ov

;0%

~

tON. tOFF(CMOS INPUT)
VREF = OPEN. VAH = +15V

tON. tOFF (TTL INPUT)
VAH =+4.0V

!f
\.

I
f

I
J

A.i

Top: TTL Input
Bottom: Output

Vertical: 2V/Oiv.
Horizontal: 200ns/Oiv.

Top: CMOS Input
Bottom: 0 utput

l

I\,
Vertical: 5V /0 iv.
Horizontal: 200ns/Oiv.

3-9

HI-201
Quad SPST CMOS
Analog Switch
FEATURES

DESCRIPTION

•

ANALOG VOLTAGE RANGE

±15V

•

ANALOG CURRENT RANGE

SOmA

• TURN-ON TIME

185ns

•

LOW RON

55n

•

LOW POWER DISSIPATION

15mW

_. TTL/CMOS COMPATIBLE

•

APPlICA TIONS

• HIGH FREQUENCY ANALOG SWITCHING
• SAMPLE AND HOLD CIRCUITS

. All devices provide break-before-make switching .and are TTL
and CMOS compatible for maximum application versatility.
HI-201 is an ideal component for use in high frequency analog
switching. Typical applications include signal path switching,
sample and hold circuit, digital filters,and op amp gain switching
networks.
HI-201 is available in a 16 lead dual-in-line package. HI-201-2
is specified from -55 0 C to +125 0 C while HI-201-5 operates
from OOC'to +75 0 C. H1-201 is functionally and pin compatible
with other available "200 series" switches.

o DIGITAL FILTERS
•

HI-201 is a monolithic device comprising four independently
selectable SPST switches which feature fast switching speeds
(1S5ns) combined with low power dissipation (15mW at 25 0 C).
Each switch provides low "ON" resistance operation for input
signal voltages up to the supply rails and for signal currents up
to SOmA. Employing Dielectric Isolation and CMOS processing,
HI-201 operates without any applications problems induced
by latch-up or SCR-mode phenomena.

OP AMP GAIN SWITCHING NETWORKS

PIN OUT

FUNCTIONAL DIAGRAM
Section 11 for Packaging

Top View

AII_~
OUT I

2--~

IN I 3-+_---1

v-

r-~_-tl
~/
I

SWITCH OPEN
FOR LOGIC HIGH

"
N

SPECIFICA TlONS
ABSOLUTE MAXIMUM RATINGS
Supply Voltage Between Pins 4 and 13
VREF to Ground
Digital Input Voltage:
Analog Input Voltage (One Switch)

44V (±22)
+20V, -5V
VSuppl y (+) +4V
VSupplyH -4V
+VSupply +2.0V
-VSupply -2.0V

Total Power Dissipation"
Operating Temperature
HI-201-2
HI-201-4
HI-201-5
Storage Temperature

750mW
-55 0 e to +125 0 e
-20 0 e to +85 0 e
ooe to +75 0 e
-65 0 e to + 150 0 e

"Derate 8mW/oe Above TA = +75 0 e

ELECTRICAL CHARACTERISTICS
Unless Othgrwise Specified
Supplies =+15V, -15V; VREF =Open; VAH (Logic Level High)
For Test Conditions, consult Performance Characteristics

=2.4V

VAL (Logic Level Low) = +O.BV
HI-201-5 .*

HI-201-2
-55°C to +125 0 C
-MIN.
TYP.
MAX.

OOC to +75 0 C
MIN.
TYP.
MAX.

-15

-15

PARAMETER
ANALOG SWITCH CHARACTERISTICS
VS, Analog Signal Range

TEMP.

RON, On Resistance (Note

+25 0 C
Full

55
80'

IS (OFF), Off Input Leakage Current
(Note 6)

+25 0 C
Full

2

10(OFF), Off Output Leakage Current
(Note 6)

+25 0 C
Full

2

10(ON), On Leakage Current (Note 6)

+25 0 C
Full

2

1)

Full

DIGITAL INPUT CHARACTERISTICS
VAL, Input Low Threshold
VAH, Input High Threshold

Full
Full

lA, Input Leakage Current (High or Low) (Note 2)

Full

+15

55
75

70
100

UNITS

+15

V

80
100

n
n

250

nA
nA

250

nA
nA

250

nA
nA

2
500
2
500
2
500
0.8

0.8

V
V

1.0

/1A

2.4

2.4
1.0

II

SWITCHING CHARACTERISTICS
tOPEN, Break - Before Make Delay (Note 3)

+25 0 C

30

30

ton, Switch ON Time

+25 0 C

185

500

185

ns

toff', Switch OFF Time

+25 0 C

220

500

220

ns

"'Off Isolation"' (Note 4)

+25 0 C

80

80

dB

Cs (OFF), Input Switch Capacitance

+25 0 C

5.5

5.5

pF

Co (OFF), {

+25 0 C

5.5

5.5

pF

COlON)

+25 0 C

11

11

pF

CA, Digital Input Capacitance

+25 0 C

5

5

pF

COS (0 FF), Orain-To-Source Capacitance

+25 0 C

0.5

0.5

pF

POWER REQUIREMENTS (Note 5)
PO, Power Dissipation

+25 0 C
Full
+25 0 C
Full
+25 0 C
Full

15

15

mW
mW
mA
mA
mA
mA

Output Switch Capacitan.ce

1+ , Current (Pin 13.)

1- Current (Pin 4)
NOTES

1. V OUT

= :!10V

lOUT

= lm.6:

2. Digital Inputs Are MOS Gates - Tvpical Leakage is

Less Than 1 nA
3. V AH : 4.0V

Note:

60

60
0.5

2.0

ns

0.5

2.0

0.5

0.5
2.0

2.0

4. V A • 5V. RL • 1 Kn. C L • 10pF. VS: 3VRMS,"
5. V A = +3V or V A = OV For all SWItches

100KHz

6. Refer to leakage current measurement diagram
on page (3-14)

H 1-201-4 has same specifications as H 1-201-5 over the temperature range -200C to +850 C.

3-11

SCHEMATIC DIAGRAMS
TTL/CMOS
REFERENCE CIRCUIT

SWITCH CELL

V-REF CELL

A'~--------~~-----------'---,

OUTPUT

R4

GND
A'

DIGITAL INPUT BUFFER

~

__________

~~

________

~

V+

AND LEVEL SHIFTER

t---+-+-~A'

L---t-+---+-+-~A'

ALL N-CHANNEL
BODIES TO VALL P-CHANNEL
BODIES TO V+
EXCEPT AS SHOWN,

3-12

V-

PERFORMANCE CHARACTERISTICS AND TEST CIRCUITS
(UNLESS OTHERWISE SPECIFIED TA = 25°C, VSUPPLY =±15V, VAH =2.4 V VAL = O.BV AND VREF = OPEN).

ON RESISTANCE vs. ANALOG SIGNAL LEVEL,
SUPPL Y VOLTAGE AND TEMPERATURE

RON

.

V2
=i;;;A

1rnA

,..,

IN

:;~
~-

;tV,N

.

v2

,..,

OUT

HI-201

ON RESISTANCE vs. TEMPERATURE
80
10

E

-

60

0
I

"'"c
.~
a:
'"
c

SO

40

.-- ~

..

V,N =OV

~

.<::

~

~

I-""'"

~

II

!

30

0

20
10
0

a

-25

-SO

')5

'25
'so
Ambient Temperature - °c

"25

"00

(HI-201)
ON RESISTANCE vs. ANALOG SIGNAL LEVEL
AND POWER SUPPLY VOLTAGE
100

V
E

.....

.<::

0

,....

V+ = +10V
V-=-10~

V+'" +12.5V

I

V-=-12.5V

2l

c

a:
c

0

--V
V

50

-=
';

L

V

V

./v+ =+15V----:
v-=;V

,/'"

,

0
-15

-10

-5

0

+5

+10

+15

Analog Signal Level- Volts

3-13

PERFORMANCE CHARACTERISTICS AND TEST CIRCU(TS (Continued)
SWITCH LEAKAGE CURRENT vs.
TEMPERATURE (HI-20l)
100

OFF LEAKAGE CURRENT
vs. TEMPERATURE

/

/

V

IsIOFF)

/

A

lolOFFI
OUT

IN

A

HI-201
-=-±14V

+14V - = -

ISIOFF)/IOIOV

~

10



11 IN 3
1-10 OUT3
1-9

A3

SWITCH OPEN
FOR LOGIC HIGH

-'I

N

PI--

~T

-

SPECIFICA T/ONS
ABSOLUTE MAXIMUM RATINGS (Note 1)
Supply Voltage Between Pins 4 and 13

+36V

Digital Input Voltage:

VSupply(+) +4V
VSupply(-) -4V
+VSupply +2.0V
-VSupply -2.0V

Analog Input Voltage (One Switch)

Total Power Dissipation*
Operating Temperature
HI-201HS-2
HI-201HS-4
HI-201HS-5
Storage Temperature

750mW
-55 0 e to +125 0 e
-20 0 e to +85 0 e
oDe to +75 0 e
-65 0 e to + 150 0 e

*Derate BmW/oe Above TA = +75 0 e

ELECTRICAL CHARACTERISTICS Unless Otherwise Specified. Supplies = +15V. -15V; VAH (Logic Level High) = 5.0V;
VAL (Logic Level Low) = +O.BV
HI-20IHS-2
HI-20IHS-5
PARAMETER

TEMP.

MIN.

FuJI

-15

TYP.

MAX.

UNITS

ANALOG SWITCH CHARACTERISTICS
+15

V

RON. On Resistance (Note 2)

+25 0C
FuJI

30

50
75

n
n

IS(OFF). Off Input Leakage Current

+25 0C
FuJI

.3

10
100

nA
nA

IO(OFF). Off Output Leakage Current

+250C
FuJI

.3

10
100

nA
nA

IO(ON). On Leakage Current

+250C
FuJI

.1

10
100

nA
nA

0.8

V

VS. Analog Signal Range

II

I

DIGITAL INPUT CHARACTERISTICS
VAL, Input Low Threshold

FuJI

VAH.lnput High Threshold

+250C
FuJI

2.0
2.4

V
V

IAL Input Leakage Current (Low)

FuJI

500

JiA

IAH.lnput Leakage Current (High)

FuJI

40

JJ.A
ns

SWITCHING CHARACTERISTICS
tON. Switch ON Time (Note 3)

+25 0 C

30

50

tOFF. Switch OFF Time (Note 3)

+250C

40

SO

"Off Isolation" (Note 4)

+2SoC

72

dB

Crosstalk (Note S)

+2S oC

86

dB

Charge Injection (Note 6)

+25 0 C

10

pC

CS(OFF), Input Switch Capacitance

+25 0 C

10

pF

CO(OFF).

+2S oC

10

pF

COlON).

+2SoC

30

pF

CA. Digital Input Capacitance

+25 0C

18

pF

COS(OFF), Orain-to-Source Capacitance

+2SoC

.S

pF

+25 0 C
Full

120

+2S oC
Full

4.S

+2SoC
Full

3.S

Output Switch Capacitance

ns

POWER REQUIREMENTS (Note 7)
PO, Power 0 issipation
1+, Current (Pin 13)
1-, Current (Pin 4)

240

mW
mW

10.0

rnA
rnA

6

rnA
rnA

NOTES:
1. Absolute maximum ratings are limiting values,
applied individually. beyond which the serviceability of the circuit may be impaired. Functional
operability under any of these conditions is not
necessarilv implied.

4. VA=5V,RL=IKn,CL=10pF,VS=3VRMS,
f = 100kHz
5. VA = 5V, RL = 1 kn, f = 100kHz, VIN = 2Vp-p
6. CL = 1000pF, VIN = OV, RIN = on

2. VOUT = ±10V, lOUT = lmA
3. RL=lkrl,CL=35pF,VIN=+10V,VA=+5V

aQ=CLx avo
1. VA"" 5Vor VA

= 0 for all switches.

3-17

TEST CIRCUIT

SWITCHING TEST CIRCUIT (tON. tOFF)

V+=+15V

r

IN
+10V

VA

OUT
I>

,.o-----t--~

LOGIC
INPUT

-"'I
I

A

£'

~

-t>d.-201HS

..L
-

GND

,.~~I1""

J -=- --

,

v-= -15V

SWITCHING WAVEFORMS
'.
DIGITAL _V~AH~......
INPUT
.~
50%

SWITCH
OUTPUT

~tON

VAL

~Ot:FF;l

________ /1'90%
.

90%

tON. tOFF (TTL INPUT)
VAH =+5.0V
5V

.... ....

11
5V

Top: TTL Input
Bottom: Output

3-18

10~ns

Vertical: 5V/Div.
Horizontal: IOOns/Div.

. . .__

miHARRIS

HI-300 thru HI-307
CMOS Analog Switches

FEATURES
•
•
•
•
•
•
•
•
•

APPlICA TIONS
± 15V

ANALOG SIGNAL RANGE (±.15V SUPPLIES)
LOW LEAKAGE (TYP.@25 0 C)
LOW LEAKAGE (TYP.@ 1250 C)
LOW ON RESISTANCE (TYP.@ 25 0 C)
BREAK-BEFORE-MAKE DELAY (TYP.)
CHARGE INJECTION
TIL, CMOS COMPATIBLE
SYMETRICAL SWITCH ELEMENTS
LOW OPERATING POWER
(TYP. FO R HI-300 - 303)

•
•
•
•
•

40pA
InA
3511
60ns
30pC
1.0mW

FUNCTIONAL DIAGRAM

DESCRIPTION

r------OOS

IN

o

TYPICAL SWITCH 300 SERIES

PINOUTS

SAMPLE AND HOLD i.e. LOW LEAKAGE SWITCHING
OP AMP GAIN SWITCHING i.e. LOW ON RESISTANCE
PORTABLE, BATIERY OPERATED CIRCUITS
LOW LEVEL SWITCHING CIRCUITS
DUAL OR SINGLE SUPPLY SYSTEMS

The HI-300 through HI-307 series of switches are monolithic devices fabricated using CMOS technology and the Harris dielectric isolation process.
These switches feature break-before-make switching, (HI-301, 303,305
& 307 only) , low and nearly constant 0 N resistance over the full analog
signal range, and low power dissipation, (a few milliwatts for the H1-300303, a few hundred microwatts for the HI-304-307J.
The HI-300-303 are TTL compatible and have a logic "0" condition with
an input less than 0.8V and a logic "1" condition with an input greater
than 4.0V. The H1-304-307 switches are CM OS compatible and have a
low state with an input less than 3.5V and a high state with an input
greater than 11 V. (See pinouts for switch conditions with a logic "1 "input.)
All the devices are available in a 14 pin epoxy or ceramic DIP. The H1-300,
301, 304 and 305 are also available in a 10 pin metal can. Each of the
switch types are available in either the -55 0 C to +125 0 C or OOC to +75 0 C
operating ranges.

(SWITCH STATES ARE FOR A LOGIC "1" INPUT)

Section 11 for Packaging

DUAL SPST HI-300 & HI-304
(TOP VIEWS)
DIP

NC 1

SPOT HI-301 & HI-3DS
(TOP VIEWS)

v+

v+

14 V+

DIP

GND

*The substrate and case are
internally tied to V-.

*The substrate and case are

(The

internally tied to V-.

case should not be used as
the V- connection, however.)

DUAL DPST HI-302 & HI-30S·
DIP

r - - - - - , (TOP VIEW)

(The

case should not be used as
the V- connection, however.)

DUAL SPOT H 1-303 & H 1-307
(TOP VIEW)
DIP
14 V+

3-19

•

SPECIFICATIONS HI-300' - HI-30l
ABSOLUTE MAXIMUM RATINGS (Note 1)
Voltage Between Supplies

44V (!22V)

Digital Input Voltage

V++4.0V
V--4.0V

Analog Input Voltage

V+ 1.5V
V-1.5V

ELECTRICAL CHARACTERISTICS

Total Power Dissipation
14 Pin Epoxy DIP
14 Pin Ceramic DIP
10 Pin Metal Can*
*Derate 6.9mW/OoC Above TA = 70 0 C
Operating Temperature H1-3XX-2
HI-3XX-5

- 55 0 C to +125 0 C
OOC to +75 0 C

Storage Temperature

- 65 0 C to +150 0 C

Unless otherwise specified; Supplies = +15V, -15V; VIN = Logic Input.
H1-300-303: VI N - for Logic "1" =4V, for Logic "0" = 0.8V
H1-304-307: VI N - for Logic "1" = 11 V, for Logic "0" = 3.5V
ODe to +750C

-55 0 C to +125 0 C
PARAMETER

526mW
588mW
435mW

TEMP

MIN

Full
+25 0 C
Full
+25 0 C
Full
+25 0 C
Full
+25 0 C
Full

-15

TYP

MAX

MIN

+15
50
15
1
100
1
100
1
100

-15

35
40
0.04
1
0.04
1
0.03
0.5

TYP

MAX

35
40
0.04
0.2
0.04
0.2
0.03
0.2

+15
50
75
5
100
5
tOO
5
100

UNITS

ANALOG SWITCH CHARACTERISTICS

Analog Signal Range
RON ON Resistance (Note 2)
ISOFF OFF Input Leakage Current (Note 3)

E

100FF OFF Output Leakage Current (Note 3)
lOON ON Leakage Current (Note 4)

V

n
n
nA
nA
nA
nA
nA
nA

DIGITAL.INPUT CHARACTERISTICS

VINllnput Low level *
VINH Input High level *

VINllnput Low Level**
VINH Input High level **
IINL Input Leakage Current (Low) INote 5)
IINH Input Leakage Current (High) INote 5)

Full
Full
Full
Full
Full
Full

O.B

O.B
4

4
3.5

11

3.5

11
1
1

1
1

V
V
V
V
IJA
IJA

SWITCHING CHARACTERISTICS

tOPEN Break-Before-Make Delay lin
tON Switch On Time*
tOFF Switch Off Time *
tON Switch On Time **
tOFF Switch Off Time **
Off Isolation (No.te 6)

Charge Injection (Note 1)
CSOFF Input Switch Capacitance
CDOFF Output Switch Capacitance
COON Output Switch Capacitance
tiN (High) Digital Input Capacitance
GIN (Low) Digital Input Capacitance

+25 0 C
+25 0 C
+25 0 C
+25 0 C
+25 0 C
+25 0 C
+25 0 C
+25 0 C
+25 0 C
+25 0 C
+250 C
+250 C

60
210
160
160
100
60
3
16
14
35
5
5

+25 0 C
Full
+25 0 C
Full
+25 0 C
Full
+25 0 C
Full
+25 0 C
Full
+25 0 C
Full
+25 0 C
Full
+25 0 C
Full

0.09

300
250
250
150

60
210
160
160
100
60
3
16
14
35
5
5

300
250
250
150

ns
ns
ns
ns
ns
dB
mV
pF
pF
pF
pF
pF

POWER REQUIREMENTS
1+ Current * (Note 81
1- Current * (Note 8)
1+ Current * (Note 91
1- Current * (Note 9)
1+ Current** (Note 101
1- Current ** (Note 101
1+ Current ** (Note 11)
1- Current ** (Note 111

0.01

om
om
0.01
0.01
0.01
0.01

0.5
1
10
100
10
100
10
100
10
100
10
100
10
100
10
tOo

• HI-300 thru HI-303 Onlv; •• HI-304 thru HI-307 Onlv; ••• HI-301, HI-303, HI-305, HI-301 Onlv

3-20

0.09
0.01

0.5
1
100

0.01

100

0.01

100

om

100

0.01

100

0.01

100

0.01

100

mA
mA
IJA
IJA
IJA
IJA
IJA
IJA
IJA
IJA
IJA
IJA
IJA
IJA
IJA
IJA

ELECTRICAL CHARACTERISTICS NOTES:
1. As with all semiconductors, stresses listed under "Absolute
Maximum Ratings" may be applied to devices (one at a time)
without resulting in permanent damage. This is a stress rating
only. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability. The conditions
listed under "Electrical Characteristics" are the only conditions
recommended for satisfactory operation.

6. Vs = lVRMS, f = 500kHz, CL = 15pF, RL = lk.
CL = CFIXTURE + CPROBE, "Off Isolation" = .201ogVSNO.
7. Vs = OV, CL = 10,OOOpF, Logic Drive = 5V pulse. (HI-300
-303) Switches are symmetrical; Sand D may be interchanged.
Logic Orive = 15V (H 1-304-3071
8. VIN = 4V (one input) (all other inputs = OV)

2. Vs = i 10V, lOUT = -10mA On resistance derived from the
voltage measured across the switch under the above conditions.

9. VIN = 0.8V (all inputs).

3. VS=i14V,VO=+14V.

10. VIN = 15V (all inputs).

4. Vs = Vo =± 14V.

11. VIN = OV (all inputs).

5. The digital inputs are diode protected MOS gates and typical
leakages of 1nA or less can be expected.

12. To drive from OTL/TTL circuits, pull-up resistors to +5V
supply are recommended.

TEST CIRCUITS
BREAK-BE FORE-MAKE TEST CIRCUIT (tBBM)

SWITCHING TEST CIRCUIT (tON. tOFF)

H1-300 th ru H1-303
H1-304 thru H1-307

HI-301, HI-303
HI-305, HI-307

4V
15V

O+l5V
5

I v+

I

.-..

I

0

Vo SWITCH
OUTPUT

f\:o-_+--::-c..-rl-O--+--J
"::'

LOGIC "1" = SWITCH ON

I
I

52

RL
CL
300133PF

I

01

51

fo°UT2

I

I
I

-I

I

I
I

J-tSBM

3-21

TYPICAL PERFORMANCE CURVES
ROS(ON) VS. VD AND
TEMPERATURE

Typical delav. rise, fell. settling limes. and switching tran&ientsin tIllseireuit.

ROSION) VS. Vo AND
POWER SUPPL Y VOLTAGE

-

~

.. ,

---

...,..

A V+-+11V. \I---1SV

• V+-+tOV, Y.··IIN'

....

~~.--~_~,,---7~---7.---7~,-~.,~.--~

C Y+·+761, V.--UN
D V+-ifV. y....-W

!,• .10

'iD_DRAINVOLTAGE IVOLTlI

T..... ace

...
0
+I
'ID_DRAINVOL1AOEtvoLTlI

RGEN -0

:J::

J

S

...........

VGEN

VLOGIC

.IN

I
I
I

RL

to... _JI

101m

y

e~

L

tND

··,
~0

"i
g

9
~

•., '--+-_"'",__"'-±,H_,....
.,\tI!-.±=-±--:!
1
10
lDO
111:
1111t IGOK
LOOlClWITCHlNGlFRlClUtNCYitbl

"*'-=

If RGEN. RL or Cl is increased, there will be proportional
increases in riH andlor fall RC times.

OFF ISOLATION
VS. FREQUENCY

13

1M

f
--r-t"1 I
111-3001II",1I1-3Cb

· -,'01'''1"7
I
I

..

··

l
I

\0

~ HI-3D4I11",HI-307

'j"ii'

.••
...
I

ICIIoDUTVCVCLE

I

ISIOFF) OR IDIOFFI
VS. TEMPERATURE *

.::

~1

.

~i
~~

~~

~

TlIII'£R4TURE-1IC

"SI!I!NDTE

"TV

!

~.~----~~~---.,.=---~

./

..,

/

•

.

VaIN-'av

VO'N'"

"'.~----~~.----,~.---~
T-~n.I~

.. The net leakage into the source or drain is the n-channel leakage minus the p-channelleakage. This difference can be positive,
negative, or zero depending on the analog voltage and temperature, and will vary greatly from unit to unit.

OUTPUT ON CAPACITANCE
VS. DRAIN VOLTAGE
~

~

~
~

DIGITAL INPUT CAPACITANCE
VS. INPUT VOLTAGE

Nr-r-r-r-r-r-~'-,

.r-~~+-+-+-+-~~

~ -r-t-t-+-+-+-+-+-1
~
~ ~r-+-+-+-+-+-+-~~
o

u

§ ·o~~'-+'-+'~'~\o~II~M07...
Yo - DMIII YDLTNK NOL1'II

04

0.8
I-T"".I~II

3-22

I'~CL
OPF

-15V

~

DEVICE POWER DISSIPATION
VS. SWITCHING FREQUENCY
SINGLE LOGIC INPUT

D

,

1.2

1.6

TYPICAL PERFORMANCE CURVES (Continued)

SWITCHING TIME VS.
TEMPERATURE
HI-300 thru HI-303
Vt~+'1V

\/ ....11V
YWH" • .ov
VINL-gy

-I-

"'"'FI"'"'
""'-I-

, ,

J
-rf
. "r..

~:~~:~IV

-~

-..-f-

I-f-

..

-"

SWITCHING TIME VS.
NEGATIVE SUPPLY VOLTAGE
HI-300 thru HI-303

Vt"tlliY
\/....1&11

_f-

f- _f-

.

SWITCHING TIME VS.
TEMPERATURE
HI-304 thru H 1-307

_35

_Ii

.

.1&1111121

T_TDII'ERATUREIOC)

-

.

y_ NEGATIVE SUI'I'f.II (VOL rq

SWITCHING TIME AND BREAK
BEFORE MAKE TIME VS.
POSITIVE SUPPL Y VOLTAGE
HI-300 thru HI-303

I
1---+- :~:~ 1---1\-- ~~::w

-

SWITCHING TIME VS.
POSITIVE SUPPLY. VOLTAGE
HI-304 thru HI-307

SWITCHING TIME VS.
NEGATIVE SUPPLY VOLTAGE
HI-304 thru HI-307

-

,f----I---~;::

,I----t--~:~:W

\

\

. "",. .
"~

\.''''''

"'''~

.

Vt "*TIIIIIU....11 M

II

o

II
10
Iii
y- NEGATIVE$UWLYVOLTAGEIVI

&
10
Iii
Vt rosrrlVESUPPLYVOLTAaElV1

I

INPUT SWITCHING THRESHOLD
VS. POSITIVE SUPPL Y VOLTAGE
HI-300 thru HI-307

3-23

mJ HARRIS

HI-381/384/
387/390
CMOS Analog Switches

FEATURES
•
•
•
•
•
•
•
•
•

•

APPLICATIONS

ANALOG SIGNAL RANGE (±15V SUPPLIES)
LOW LEAKAGE (TYP. @25 0C)
LOW LEAKAGE (TYP@ 125 0C)
LOW ON RESISTANCE (TYP. @25 0C)
BREAK-BEFORE-MAKE DELAY (TYP.)
CHARGE INJECTION
TIL COMPATIBLE
SYMMETRICAL SWITCH ELEMENTS
LOW OPERATING POWER (TYP.)

±15V
40pA
InA
35n
60ns
30pC
1.0mW

DESCRIPTION

FUNCTIONAL DIAGRAM
r-------o()S

IN

'------+-0 D

The HI-381 through HI-390 series of switches are monolithic
devices fabricated using CMOS technology and the Harris dielectric isolation process. These devices are TTL compatible and
are available in four switching configurations. (See device pinout
for particular switching function with a logic ''I': input,)
These switches feature low leakage and supply currents, low and
nearly constant ON resistance over the analog signal range, breakbefore-make switching and low power dissipation.
The HI-381 and HI-387 switches are available in a 14 pin epoxy
or ceramic DIP orl0 pin metal can. The HI-384 and HI-390
are available in a 16 pin epoxy or ceramic DIP. Each of the
individual switch types are available in the -550C to +125 0C
and DoC to +75 0C operating ranges.

TYPICAL SWITCH - 300 SERIES

PINOUTS

• SAMPLE AND HOLD i.e. LOW LEAKAGE SWITCHING
• OP AMP GAIN SWITCHING i.e. LOW ON RESISTANCE
• PORTABLE BATIERY OPERATED CIRCUITS
• LOW LEVEL SWITCHING CIRCUITS
• DUAL OR SINGLE SUPPLY SYSTEMS

(SWITCH STATES ARE FOR A LOGIC "1" INPUT)

Section 11 fDr Packaging

DUAL SPST HI-381

SPOT HI-387

(TOP VIEWS)

(TOP VIEWS)
02

DIP

DIP

Ne

Ne

*The substrate and case are
internallY tied to V-.

(The

case should not be used as
the V- connection, however.)

DIP

3-24

*The substrate and case are
Internally tied to V-.

(The

case should not be used as
the V- connection, however.)

DUAL DPST HI-384

DUAL SPOT HI-390

(TOP VIEW)

(TOP VIEW)

SPECIFICA TlONS
ABSOLUTE MAXIMUM RATINGS (Note 11
44V (±22)

Voltage Between Supplies

Total Power Dissipation
14 Pin Epoxy DIP
14 Pin Ceramic DIP
16 Pin Epoxy DIP
16 Pin Ceramic DIP
10 Pin Metal Can*
*Derate 6.SmW/oC above TA =70 0 C

Digital Input Voltage
V++4.0V
V--4.0V
Analog Input Voltage
V+ +1.5V
V- -1.5V
Storage Temperature Range

-65 0 C to

Operating Temperature
HI-3XX-2
HI-3XX-5

+150 oC

526mW
588mW
625mW
685mW
435mW

-55 0 C to +125 0 C
OOC to +75 0 C

ELECTRICAL CHARACTERISITICS Unless otherwise specified; Supplies = +15V, -15V; VIN = Logic Input,
VIN for logic "1" =4V, for logic 0 =.8V
·55 0 C to +125 0 C
PARAMETER

TEMP

MIN

FULL
+25 0 C
FULL
+25 0 C
FULL
+25 0 C
FULL
+25 0 C
FULL

-15

OOC to +75 0 C

TYP

MAX

MIN

+15
50
75
1
100
1
100
1
100

-15

35
40
.04
1
.04
1
.03
0.5

TYP

MAX

35
40
.04
0.2
.04
0.2
.03
0.2

+15
50
75
5
100
5
100
5
100

UNITS

ANALOG SWITCH CHARACTERISTICS
Analog Signal Range
RON ON Resistance INote 2)
ISOFF OFF Input Leakage Currenl (Nole 3)
IDOFF OFF Output Leakage Current
(Nole 3)
ID 0 NON Leakage Current (N ole 4)

V

n
n

II

nA
nA
nA
nA
nA
nA

OIGITAL INPUT CHARACTERISTICS
VINL Inpul Low Level
VINH Input High Level
IINH Input Leak. Current (High) (Nole 5)
IINL Input Leak. Current (Low) (Note 5)

FULL
FULL
FULL
FULL

.8

SWITCHING CHARACTERISTICS
(HI-3871
tOPEN, Break-Before Make Oelay 390 only)
tON, Switch ON Time
tOFF, Switch OFF Time
OFF Isolation (Note 6)
Charge Injection (Note])
CSOFF Input Switch Capacitance
COOFF Output Switch Capacitance

+25 0 C
+25 0C
+25 0 C
+25 0 C
+250C
+250C
+250C

60
210
160
60
3
16
14

60
3
16
14

dB
rnV
pF
pF

COON Output Switch Capacitance

+250C

35

35

pF

CIN (High) Oigitallnput Capacitance

+250C

5

5

pF

CIN (Low) Oigilallnput Capacitance

+25 0 C

5

5

pF

1+ Current (Nole 8)

+250C
FULL

.09

.5
1

.09

.5
1

rnA
rnA

1- Current (Note 8)

+25 OC
FULL

.01

10
100

.01

100

IlA
Il A

1+ Current (Note 9)

+250C
FULL

.01

10
100

.01

100

IlA
JlA

1- Current (Note 9)

+250C
FULL

.01

10

.01

100

IlA
IlA

4

.8

V
V

1
1

IlA
IlA

300
250

ns
ns
ns

4
1
1

300
250

60
210
160

POWER REQUIREMENTS

roo

3-25

ELECTRICAL CHARACTERISTICS NOTES:
1. As with- all semiconductors, stresses listed under "Absolute
Maximum Ratings" may be applied to devices (one at a time)
without resulting in permanent damage. This is a stress rating
only. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability. The conditions
listed under "Electrical Characteristics" are the only conditions
recommended for satisfactory operation.
2. Vs =:t 10V, lOUT = -10mA on resistance derived from the
voltage measured across the switch under the above conditions.

S. The digital inputs are diode protected MaS gates and typical
leakages of 1nA or less can be expected.

6. Vs = lVRMS, f = SOOkHz, CL = ISpF, RL = lk,
CL = CFIXTU RE + CPR aBE·, "off isolation" = 2010g VsIVo·
7. Vs = OV, CL = 10,OOOpF, Logic Orive = SV pulse. Switches
are symmetrical; Sand 0 may be interchanged.
8. VIN = 4V.

(one input) (all other inputs = 0)

9. VIN = 0.8V. (all inputs)

3. VS=:!.:14V,VO="+14V.

10. To drive from OTL/TTL circuits, pull-up resistors to +SV
Supply are recommended.

4. Vs = Vo =.± 14V.

TEST CIRCUITS
SWITCHING TEST CIRCUIT (tON, tOFF)

BREAK-BE FORE-MAKE TEST CIRCUIT (tBBM)

SWITCH TYPE

VINH

SWITCH TYPE

VINH

HI-381 thru HI-390

SV

HI-387 and HI-390

SV

'j'+15V

Q+15V

s

Iv+

I

___

I

I v+
D

Vo SWITCH

::~~~ ~o--t--:-
I-

~

100r- V+-+15V
TA-25DC
VINH-+4·DV

•

..
0

lOTi

-of-

I
I

l-

,

0

..

'0

>

NEGATIVE SUPPLYVOLTAaE {VOLTSI

I..

-0

VGEN --OV

INPUT SWITCHING THRESHOLD
VS. POSITIVE SUPPLY VOLTAGE
HI-381 thru HI-390

~

~~
e~

!;g

zyw

,•
•

i~

~>

,

~

I II
I I I

7

3

~o

I
I

0

·0

g

~

I I I
I I I

:l

VINL-j

v-

-,VGri,v I

~
...

200

0

~

VGEN -1OV

~

SWITCHING TIME VS.
NEGATIVE SUPPLY VOLTAGE
HI-381 thru HI-390

]

~

ILl
..LLL
·SEE NOTE

0

'OFF'

0.2

I'0P'

-15V

2

..

~

0.0

'OK~

tNO L

"0

\

O.

I

~_J

..

z
;;

'A

Ri! J-CL

I

9
g r-IIL0j'Crp'f

,.

"~

0

,

If RGEN, RL or CL is increased, there will be proportional
increases in rise and/or fall RC .times.

T - TEMPERATURE loct

~

,, ""

S

v·-·,sv

TA-2fjOC

..
0

T

..'0

2

•

VGEN- -1OV

HI-381111n,1HI-390

,

-

I

,.

0

10
5
"... POSITIVE SUPPLY VOLTAGE (VOLTSI

0.'

O~
'.2
l-TIMEIJ,laI

,.,

* NOTE: The turn-off time is primarily limited
here by the RC time constant (100ns) of the

3-28

load.

H1-5040 thru H1-5051
H1-5046A and
HI-5047A

;m~RIS

CMOS Analog Switches
FEATURES

DESCRIPTION

• WIDE ANALOG SIGNAL RANGE
• LOW "ON" RESISTANCE (TYP)
• HIGH CURRENT CAPABILITY (TYP)
• BREAK-BEFORE-MAKE SWITCHING
TU RN-O N TI ME (TYP)
TURN-OFF TIME (TYP)
• NO LATCH-UP
• INPUT MOS GATES ARE PROTECTED FROM
TROSTATIC DISCHARGE
• DTL, TTL, CMOS, PMOS COMPATIBLE

±15V
25S1
80mA
370ns
280ns
ELEC-

This family of CMOS analog switches offers low-resistance
switching performance for analog voltages up to the supply
rails and for signal currents up to 80mA. "ON" resistance is low
and stays reasonably constant over the full range of operating
signal voltage and current. RON remains exceptionally constant
for input voltages between +5V and -5V and currents up to
50mA. Switch impedance also changes very little over temperature, particularly between DoC and +75 0 C. RON is nominally 25 ohms for HI-5048 through HI-5051 and HI-5046A/
5047A and 50nfor HI-5040 through HI-5047.

II

All de.vices provide break-before-make switching and are TTL
and CMOS compatible for maximum application versatility.
Performance is further enhanced by Dielectric Isolation processing which insures latch-free operation with very low input
and output leakage currents (O.8nA at 25 0 C). This family of
switches also features very low power operation (1.5mW at
25 0 C).

APPlICA TlONS

• HIGH FREQUENCY SWITCHING

I

There are 14 devices in this switch series which are differentiated
by type of switch action and value of RON (see Functional
diagram). All devices are available in 16 pin D.I.P. packages.
The H1-5040/5050 switches can directly replace IH-5040 series
devices and are functionally compatible with the DG 180/190
family. Each switch type is available in the -55 0 C to +125 0 C
and OOC to +75 0 C performance grades.

• SAMPLE AND HOLD
o DIGITAL FILTERS
o OP AMP GAIN SWITCHING

FUNCTIONAL DESCRIPTION

FUNCTIONAL DIAGRAM

Section 11 for Packaging
PART NUMBER

TYPE

HI-S040

SPST

HI-S041
HI-S042
HI-S043
HI-S044

OUAl SPST
SPOT
OUAlSPOT
OPST

HI-S04S
HI-S046
HI-S046A
HI-S047
HI-S047A
HI-S048
HI-S049
HI-SOSO
HI-SOSI

OUAlOPST
OPOT
OPOT
4PST
4PST
OUAl SPST
OUAlOPST
SPOT
OUAl SPOT

RON
7m
7sn
7sn
7sn
7Sn
7m
7m
30n
7sn
30n
30n
30n

TYPICAL DIAGRAM
S

Ao-~

V

P~

J N
I

0
~

30n
30n

3-29

SPECIFICA TIONS
ABSOLUTE MAXIMUM RATINGS
SupplV Voltage (v+ -V-)
VR to Ground
oigital and Analog
Input Voltage

Analog Current (S to O)
Total Power Oissipation*
Operating Temperature
HI-50XX-2
HI-50XX-5
Storage Temperature

3BV
V+, VV++4V
V--4V

BOmA
450mW
-55 0 C to +125 0 C
DoC to +75 0 C
-B5 0 C to +150 0 C

*Oerate BmW/DC above TA = 75 0 C

ELECTRICAL CHARACTERISTICS
Unless Otherwise Specified
Supplies=+15V,-15V; VR = OV; VAH (Logic Level High) = 3.0V;VAL (logic level low) =+O.BV, Vl =+5V
For Test Conditions, consult Performance Characteristics

PARAMETER
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range
Ron,"ON" Resistance (Note la)
Ron,"ON"Resistance (Note lb)
Ron, Channel·to-Channel Metch (Note Ta)
Ron, Channel·to·Channel Match (Note lb)
IS(OFF) = IO(OFF), Ofllnput or Output
leakage Current
ID(ON). On leakage Current
DIGITAL INPUT CHARACTERISTICS
VAL, Input Low Threshold
VAH, Input High Threshold
lA, Input Leakage Current (High or Low)

3-30

Full
+25 0 C
Full
+25 0 C
Full
+25 0 C
+25 0 C
+25 0 C
Full
+25 0 C
Full
Full
Full
Full

SWITCHING CHARACTERISTICS
ton. Switch "ON" Time
toff' Switch "OFF" Time
Charge Injection (Note 2)
"OFF Isolation" (Note 3)
"Crosstalk" (Note 3)

+25 0 C
+2S oC
+25 0 C
+25 0 C
, +25 0 C

CS(OFF),lnput Switch Capacitance

+25 0 C

-55 0 C to +125 0 C
MIN
TYP
MAX
-15

MIN

DoC to +75 0 C
TYP
MAX

-15

+15
50
75

2

1
0.8
100
0.01
2

V

75

n
n

50
10
5

n.
n.
n.
n.

25
50
10
5

2
1
0.8
100
0.01
2

:

500
500
0.8

3.0

75
80

+15
50

25

UNITS

500
500
0.8 "

3.0
.01

1.0

.01

LO

370
280
5
80
88

1000
500
20

370
280
5
80
88

1000
500

nA
nA
nA
nA
V
V
/lA
ns
ns
mV
dB
dB

"
II

"
"

pF

+25 0 C

CD (0 r,I),
CA, Digital Input Capacitance
CDS (OFF). Drain·To·Source Capacitance

+25 0 C
+25 0 C
+250 C

22
5
0.5

22
5
0.5

pF
pF
pF

POWER REQUI REMENTS
PO, Quiescent Power Dissipation
1+, +15V Quiescent Current
1-. -15V Quiescent Current
IL' +5V Quiescent Current
'IR. Gnd Quiescent Current

+25 0 C
Full
Full
Full
Full

1.5

"":"'j

NOTES:

TEMP

Output Switch Capacitance

I. VOUT = :!:IOV, lOUT = ImA
a) For HI-5040 thru HI-5047
b) For HI-5048 thru HI-5051, HI-5046A/5047A
2. V IN = OV, C L = IO,OOOpF
3. RL = lOOn, f= 100 KHz, VIN = 2 Vpp, C L =5pF

pF

1.5
0.3
0.3
0.3
0.3

0.5
0.5
0.5
0.5

mW
mA
mA
mA
mA

SWITCH FUNCTIONS

SWITCH STATES ARE FOR LOGIC "1" INPUT

SPST
HI-S040 (7Sm
VL

8

16

DUALSPST
HI-S041 (7Sm
V+

VL

51

,
,,

SPOT
HI-S042 I7sm
VL

V+

16

01

I

,
_J

Al

_J

A2

-,

I

82

81

16

01

82

8

V+

,,

02

-"

A
02

14
VR

VR

V-

DUAL SPOT
HI-S043 (7Sn)
VL

V-

VR

DPST
HI-S044 (7Sm

DUAL DPST
HI-S04S (7Sm

v+
VL

VL

V+

V+

11
81
83
Al

01
03

81

16

01
02

,

A2
82
54

81
83
Al

01
03

-~

02

II

02
04

04

I

14
VR

VR

V-

VR

DPDT
HI-S046 (7Sm
HI-S046A (30m
VL

14

V-

4PST
HI-S047 (7Sm
HI-S047A (30m
V+

VL

V-

DUALSPST
HI-S048 (30m
VL

V+

V+

11
81
52
83
54
A

81

01
02
03
04

16

9

...!

01

01
02
03
04

16

9

...!

02
14
VR

14

V-

VR

DUAL DPST
HI-S049 (30n)
VL

81
83
Al

V+

VL

01
03

_J

81

02
04

16

01
02

!

-~

A

V-

V+

51
53
Al

01
03

A2
82

02
04

54
14

14
VR

VL

V+

82

-,

V-

DUAL SPOT
HI-SOS1 (30m

SPOT
HI-SOSO (30m

16

A2
82
84

"R

V-

VR

V-

VR

v-

3-31

PIN CONFIGURATIONS
SINGLE CONTROL

SPOT
HI-S042 (7Sm
H I-SOSO (2SUI

SPST
HI-S040 (7SUI

OPST
HI-S044 (7Sm

D'

'66

D' ,

1651

D' ,

Ne.

'6 A

Ne'

'6 A

Ne.

'6 A

Ne 3

14

v~

D.3

14 V-

D.3

14

v-

Ne 4

13 VA

6.4

13 VR

6.4

~3

VR

12 VL

Ne 5

12 VL

Ne 6

12 VL

Ne.

Ne.

11 V+

Ne 6

Ne 7

10 NC

Ne 7

Ne B

• Ne

Ne B

OPDT
HI-S046 (7S!1)
HI-S046A (2SUI

16 51

v+

Ne.

11

10 Ne

Ne 7

10 NC

9 Ne

Ne B

9 Ne

"

V+

4SPST
HI-S047 (7SD,
HI-S047A (25U1

D. ,

1652

D' ,

Ne.

,. A

Ne 2

'6 A

D13

14

D'3

14 V-

v-

16 52

6' 4

13 VR

6' 4

13 VR

S46

12 VL

646

12 VL

046

"

V+

046

"

Ne 7

10 Ne

Ne 7

10 NC

963

D. B

9 .3

DUAL CONTROL

v+

DUALSPDT
H I-S043 (7SUI
HI-SOS1 (2SUI

DUALSPST
HI-S041 (7Sm

DUAL DPST
HI-S04S (7SUI
HI-S049 (2SUI

16 51

D' ,

D'

15 At

Ne •

Ne •

15 A1

NC 3

14 V-

D. 3

D3 3

14 v-

Ne 4

13 VR

S3 4

.3 4

13 VR

Ne 6

12 VL

S4 •

S4

•

12 VL

Ne.

11 V+

D4 6

D4 •

l' V+

Ne 7

10 A2

Ne 7

Ne 7

10 A2

D. B

9

9

••

DUALSPST
HI-5048 (2SUI
Ne ,

16 Ne

Ne •

16 A1

D, 3

14

0' •

13 VR

02.

12 VL

v-

Ne 6

11 V+

D2 7

10 A2

Ne B

•

Ne

D' B

•

52

,

16 51

D' ,
Ne.

D2 •

3-32

SWITCH STATES ARE FOR LOGIC "0" INPUT

••

PERFORMANCE CHARACTERISTICS AND TEST CIRCl1.lTS
(UNLESS OTHERWISE SPECIFIED TA = 25 0 C, V+=+15V, V-=-15V, VL =+5V, VR = OV, VAH

=3.0Vand VAL = 0.8V

ON RESISTANCE vs. ANALOG SIGNAL LEVEL,
SUPPL V VO LTAGE AND TEMPERATURE
lmA

--:cID

V2
RON = lmA

.

V2

IJUT

IN

-:.::!:VIN

-¥

"ON'" RESISTANCE vs. ANALOG SIGNAL LEVEL
AND POWER SUPPLY VOLTAGE
80

E

or:

II

60

0

I

I

w
(.)

V+=+10V
V- = 10V

z

«

en 40
en
w
ex:

I-

z

P

20

-

..........

r.:::

r- "-

0
-15

-10

.JI.L V+ = t12V

t:;; ~

I"--

-

~

-5
0
+5
ANALOG SIGNAL LEVEL - VOLTS

V- = -12V

L
~
V+=+15V
V-=-15V

+10

I
+15

NORMALIZED "ON" RESISTANCE vs. TEMPERATURE
~-

w
(.)

1.2

«~c§l
en'"
N
w
ex: +

1.1

kl-

1.0

z

0

00

w
~ex:
wex:

0

z

~

0.9

NW
_
u.

-'w
«ex:
:;:ex:

---VIN = OV

0.8

'"

~

,;'

-

..........

0.7
0.6
-50 0

-25 0

00

+25 0

+50 0

+75 0

+100 0

+125 0

TEMPERATURE - DC

3-33

PERFORMANCE CHARACTERISTICS AND TEST CIRCUITS (continued)

OFF LEAKAGE CURRENT
vs. TEMPERATURE
IS(OFF)
ID(OFF)
OUT
A
A
IN

ON/OFF LEAKAGE CURRENT vs. TEMPERATURE

:!:10V-=-

~

ON LEAKAGE CURRENT
vs. TEMPERATURE
IN

lOpA ................
25 0

50 0

75 0

1250

100 0

TEMPERATURE - DC

OUT

~ID(ON)

-=- :!:10V
~

NORMALIZED "ON" RESISTANCE
vs. ANALOG CURRENT

1.4.---.---.----.-,--.-......,..-,..-,
w

(.)

2:

;:: _ 1.3t--t---t---t-r--r--t--r--1
<1><1:

U; E
w
c:o
~

2: :; 1.21-+--+--l-t--t--t-r--1
f'~
oc:
~ :f 1.11-+--+--l-t--t--t-r--1

~~

~~

-~

1.01t--+--+--I----i-'t"""=+--+--I

o

3-34

20
40
60
ANALOG CURRENT - rnA

80

"ON" RESISTANCE
vs. ANALOG CURRENT

PERFORMANCE CHARACTERISTICS AND TEST CIRCUITS (continued)
"OFF"ISOLATION vs. FREQUENCY

-20 0

~ -16 0
I

'"'">=

-12 0

:5

~

......

~

RL = lOon

-

~

-8 0
1-- ..

"OFF" ISOLATION = 2D

IOg(~)
VOUT

r-:-.
RL = 10Kn

-4 0

I i IIIIIII
11111111

10

100

IK
IDK
FREQUENCY - Hz

lOOK

1M

CROSSTALK vs. FREQUENCY

II

20 D

,

160

~,

'"
~

I

~ 12 0

«

~
o

~ 80

- -

r-

"

-

D

RL = lOon

VOUT

rKlllL J I
~
RL = IKn

i Ililll

r--r-...

I I

"CROSSTALK" = 2D IOg(~)
VOUT

~
RL IDKn
=

! 11111

I I

111111 II
100

10

IK
10K
FREQUENCY - Hz

lOOK

1M

POWER CONSUMPTION vs. FREQUENCY
200

~

+IOV 0 - + - - 0 + + - 0 - - - 1 - ,

16 D

I

I

'"

'"
~
"
:>

12 D

I

'"'-'o'"
a:

TOGGLE
ATSO%
DUTY

I

~ 8D
~

D

D~,

-IOVo-+--O

I

IK

-

_I"""

V

/

IDK
IDDK
TOGGLE FREQUENCY (SO% DUTY CYCLEI- Hz

II

+5V

+1SV -15V

1M

3-35

SWITCHING CHARACTERISTICS

VAH

ON/OFF SWITCH TIME
VS. LOGIC LEVEL

~I

I

INI

I

+10V

I
..
.-+.!

~

...

I
IN2

I

I
:

90%f:
tON

lK ~ ~ lK .. :

I

~

VA

I

I
I

--I

tON

90%

I--

-120

SWITCHING TIMES FOR POSITIVE DIGITAL TRANSISTION

660

600

E

420
360

/

600

540
460

SWITCHING TIMES FOR NEGATIVE DIGITAL TRANSISTIDN

120

660

540

\
\

300
240

""

-r -

420

........

r-..... .......
t'-......

180

-

I

360

tON

-

300

I

~

240
180

120
120
60
3.DV

2.4V

4.2V

3.6 V
DIGITAL "HIGH" (VAH)

4.8V

1/

5V~V AH~2.4V

480

T.5V~VAL~OV

tON

V

~

I

l

I

lOV

D5V

OV

SWITCHING WAVEFORMS
TOP: CMOS INPUT (5V/OIV)
VAH =IOV. VAL =OV
BOTTOM: OUTPUT (5V/DIV

TOP: TTL INPUT (lV/DIV)
VAH =3V. VAL =O.8V
BOTTOM: OUTPUT (5V/DIV)

-

~'

\

3-36

-

,

If

I
200ns!DIV

V·

60
DIGITAL "LOW" (VAL)

r

/
./

....-

tOFF

V

200ns!DIV

1,5V

SCHEMATIC DIAGRAMS
SWITCH CELL

TTL/CMOS
REFERENCE CIRCUIT·

v+
v+

R3

.---'WI~P----ov

R

Rl

200n

v-

TO P2

IN

OUT

v-

R2

9K

•

~----~--~---ov_
·Connect

v+ to

V L for

minimizing power consumption
when driving from CMOS circuits

DIGITAL INPUT BUFFER
AND LEVEL SHIFTER

v+

R4
A o-Jl/III_t-...

200n

ALL N-CHANNEL
BODIES TO V-

v-

ALL P-CHANNEL
BODIES TO V+
EXCEPT AS SHOWN

3-37

-CMOS

Analog Multiplexers
II II II
..................................
' ~ ~ ' .....

PAGE
Selection Guides
HI-506/507
H 1-506A/507A
HI-508/509
H 1-508A/509A
HI-516
HI-518
HI-524
HI-539
HI-1818A/1828A

Single 16/Differential 8 Channel CMOS Analog Multiplexers
16 Channel CMOS Analog Multiplexer with Overvoltage Protection
Single 8/Differential 4 Channel CMOS Analog Multiplexer
8 Channel CMOS Analog Multiplexers with Overvoltage Protection
16 Channel/Differential 8 Channel CMOS High Speed
Analog Multiplexers
8 Channel/Differential 4 Channel CMOS High Speed
Analog Multiplexer
4 Channel Video Multiplexer
Monolithic, Four Channel Low Level, Differential Multiplexer
Low Resistance 8 Channel CMOS Analog Multiplexers

4-2
4-3
4-9
4-15
4-22
4-28
4-31
4-34
4-39
4-48

•

ABSOLUTE MAXIMUM RATINGS

As with all semiconductors, stresses listed under "Absolute Maximum Ratings" may
be applied to devices (one at a time) without resulting in permanent damage. This
is a stress rating only. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. The conditions listed under "Electrical
Characteristics" are the only conditions recommended for satisfactory operation.

4-1

I

CMOS Multiplexers Selection Guide

FUNCTION
4-CHANNEL
DIFFERENTIAL

8-CHANNEL

•

8-CHANNEL
DIFFERENTIAL

TTL
"HIGH"
MIN(V)

RON(n!
(TYP)

ID(OFF)
(nA)
(TYP)

t(ON)
(ns)
(TYP)

t(OFF)
(ns)
(TYP)

PD(mW)
(TYP)

PAGE

DEVICE

FEATURE

HI-1828A

LOW RON
LOW LEAKAGE

4.0

250

0.05

350

250

5

48

HI-509A

ANALOG INPUT
OVERVOLTAGE
PROTECTION

4.0

1200

1.0

300

300

7.5

22

HI-1818A

LOW RON
LOW LEAKAGE

4.0

250

0.1

350

250

5

48

HI-508A

ANALOG
OVERVOLTAGE
PROTECTION

4.0

1200

1.0

300

300

7.5

22

HI-507

LOW RON

2.4

170

1.0

300

300

30

3

7.5

9

HI-507A

ANALOG
OVERVOLTAGE
PROTECTION

4.0

1200

1.0

300

300

HI-506

LOW RON

2.4

170

1.0

300

300

30

3

HI-506A

ANALOG
OVERVOLTAGE
PROTECTION

4.0

1200

1.0

300

300

7.5

34

8-CHANNELI
4 DIFFERENTIAL

HI-518

HIGH SPEED
LOW LEAKAGE

2.4

620

0.035

100

80

525

31

16-CHANNEL/
8 DIFFERENTIAL

HI-516

HIGH SPEED
LOW LEAKAGE

2.4

480

0.1

80

60

360

28

4-CHANNEL

HI-524

VIDEO
BANDWIDTH

2.4

700

0.2

180

180

540

34

4-CHANNELI
DIFFERENTIAL

HI-539

LOW
LEVEL
SIGNALS

4.0

650
e.RON:
5.5n

0.1

~ ,9 1.2

~

+10

V,N

1.8

f!+'
~ ~ 1.6

-550C

+5

+1250C~TA~-550C

" 2.0

EN~+O.8V

:::::::+10V

*

"Two measurements per channel:
+10V/-10V and -10V/+10V.
(Two measurements per device for IO(OFFI:
+10V/-10V and -10v/+10V.I

'" Islom
~!:~:::turrent -0

F~
10pA

50'

25'

75'
TemparatuI"9 0C

100'

+1Dvl

1250

~

LOGIC THRESHOLO
vs. POWER SUPPLY VOLTAGE
4

"::::
~

0

3

~
~

.3,"
~

c

""'"

-

-

2

AO

A folON)

bb

-=..±10V

+2AV

f

POWER SUPPLY CURRENT
VS. TEMPERATURE

..

Q

OUT

EN
A,

3.0

0

is is

'tiO tl2 i14 i16 ilS ±20
Power SupplV Voltage (Volts~

f-

.~

~

VEN

]:

=2.4V-

VEN - OV
1.0

,.

'Vlo

2.~

20

+1

>

~

cQ

<.>
>

~

r-"" SOrr-60
!
= 40 r-~

2.0

~

1

r-

IDOl'"

.§
c

OFF ISOLATION vs.
FREQUENCY

0
-55 -35 -15 -5

25 45 65 S5 105 125

Temperature (ac)

0
104

IlfL

-=
RL

~ ~

1'~~

!II I Ii

VIE~ ~I~Y

-=
-

1 _II

CLO~~II~,~SpF
105

=lK

~~,~? VRMS
106

107

-Frequency (Hz)

4-5

PERFORMANCE CHARACTERISTICS AND TEST CIRCUITS (continued)
TEST CIRCUIT
NO.5

ON CHANNEL CURRENT vs. VOLTAGE

ON CHANNEL CURRENT
vs, VOLTAGE

o

±2

:!6
t8
tlO
t12
VIN - Voltage Across Switch

t4

t14

t16

TEST CIRCUIT
NO.6

f:::.

SUPPLY CUR RENT

SUPPLY CURRENT vs. TOGGLE FREQUENCY

vs. TOGGLE FREQUENCY

8~--~----~-----.-----r~--~

..

E 6r-----r-----t-----t-----+---~
~
VSupp ly = t15........ /

'Ir-+-__---1

';. 4 f-----f---.-t------+---

1

•

+r

J

r------",+v,.,
rNl~±10/±5

t - - A3

ot==+===t.==~--J---J.
lK
10K
lOOK
1M
10M
Toggle Frequency.Hz

HI 506

.'

'on ~ A;

VSupprtl0V"b!'

2~=t===:j:::::::
I==1V=,r11

IN2

~--;_""'--IA

•~A

-=::-

0--

EN

: {;;!i::...

THRU

.~

:,...

:::: -----{), 10/.;, -=

GNO

I i 14.!

OUT

i ~,l,.,ls,~lPoP: Mn ~

Similar connection for HI-507

TEST CIRCUIT
NO.7

ACCESS TIME

vs. lOGIC lEVEl (HIGH)

ACCESS TIME vs. LOGIC LEVEL (HIGH)
v+

600

:§
E
,::

~

400

~~ ~,on cr-~:~

f'..

"::" "*"

~ 200

:5'

H:~~~~RU IN15l-o---:!::-~_
IN16

EN

+5V

OUT

i

-~

1I
I

IL

oMn

14"

ADDRESS

ACCESS TIME

DRIVE(VA)

~

~VAH

VAL=OV

I

+lOV

-

I

4-6

l

OUTPUT

1

\--SV

1

I

I

1

---I

1-- '- VA INPUT_+-+-+''H--I-+--i

.--- r'DlV

tA

-10V

r-+--HH--t-+- OUTPUT ++--+--1
lV/DI~

1200 NSIDIV

II
:

I

"::"
____
..II

SWITCHING WAVEFORMS
VAH=3.5V

PROBE

r-----,
I

Similar connection for HI-507

lit

~+10V-

~-=GrNO,--...:Vr-_ - '

°2L~--3L-L-~4--L-~5~4J~lL3~--,L4~~'5
VAH -logic Level (High), Volts

IN1~±10V

SWITCHING WAVEFORMS (continued)
TEST CIRCUIT
NO.8

BREAK-BEFORE-MAKE DELAY (tOPEN)

BREAK-BEfORE-MAIeE DELAYifoPENI
+15V

0"

~
SO%
SO%
I

-

VA INPUT

t-

OUTPUTA

r/OlV

8, ON

I

,

SiSON

JUT'
UT
IV/DIV

I

-.I

f4-'OPEN

V

12.5pF

I

1/

..
100 NSIDIV

Similar connection for HI-507

TEST CIRCUIT
NO.9
ENABLE DRIVE
VAH = 3.SV

ENABlEDELAYltONIENI.tOfFIENII

I
90%

I I

tl5V

Y,V~_ _ _ _ ~...._ __
I

ENABLE DELAY (tON(EN) ,tOFF(EN))

-., r-

J

VAL=OV
OUTPUT A

~
I
I
I
I
I
90%

DRIVE
2V/DIV

II
I If

S2THRUSI60FF/

~ 'ON(ENI t - I 'OFF I
I
I -IIENII-

•

ENABLE

8, ON

LT,uT
\
2V/DIV

I II
I W
100 NS/DIV

"

Similar connection for HI-507

SCHEMATIC DIAGRAMS
ADDRESS DECODER

TO p..CHANNEl
DEVICE OF
THE SWITCH

TO N-CHANNEL
DEVICE OF
THE SWITCH

Delete A3 or A31nput for HI-507

4-7

SCHEMA TIC DIAGRAM (continued)
MULTIPLEX SWITCH

ADDRESS INPUT BUFFER
LEVER SHIFTER

+V

All N-Channel Bodies to VAil P-Channel Bodies to V+ Unless Otherwise Indicated.

TTL REFERENCE CIRCUIT

v.

OND

4-8

m~RIS

HI-506A/HI-507A
16 Channel CMOS
Analog Multiplexer with
Overvoltage Protection

FEATURES

DESCRIPTION

• ANALOG/DIGITAL OVERVOLTAGE PROTECTION
• FAIL SAFE WITH POWER LOSS (NO LATCHUP)
• BREAK-BEFORE-MAKE SWITCHING
• DTL/TTL AND CMOS COMPATIBLE
• ANALOG SIGNAL RANGE

±15V

• ACCESS TIM E (TYP.)

500ns

• SUPPLY CURRENT AT lMHz
ADDRESS TOGGLE (TYP.I

4mA
7.5mW

• STANOBY POWER (TYP.)

APPLICATIONS
• DATA ACQUISITION

The HI-50SA and HI-507A are dielectrically isolated CMOS
analog multiplexers incorporating an important feature; they
withstand analog input voltages much greater than the supplies.
This is essential in any system where the analog inputs originate
outside the equipment. They can withstand a continuous input
up to 10 volts greater than either supply, which eliminates the
possibility of damage when supplies are off, but input signals
are present. Equally important, they can withstand brief input
transient spikes of several hundred volts; which otherwise
would require complex external protection networks. Necessarily, ON resistance is somewhat higher than similar unprotected devices, but very low leakage currents combine to produce low errors. Application Notes 520 and 521 further explain
these features.

II

The H1-50SA· 2 and H1-507A-2 are specified over -55 0 C to
+125 0 C while the -5 versions are specified over OOC to +75 0 C.

• INDUSTRIAL CONTROLS
• TELEMETRY

PINOUT

FUNCTIONAL DIAGRAM

HI-506A

Section 11 for Packaging

HI-506A

TOPVIEW

•

-tV SUPPLY 1

NC 1

28 OUT
21-VSUPflLY

NC 1

26 IN 8

IN 16 4

2S IN 1

IN 15 5
IN 14 6

24 IN 6
2] IN 5
22 IN 4

IN 13 1

21 IN 3

IN 12 8
IN 11 9

20 IN 2

"""'!::~

AIIDIESS

',--h~-+1-+4+-l

.,~~

19 IN 1
18 ENABLE
17 ADDRESS AO

IN 10 10
IN 9 II

GND 12
VREF I]

16 ADDRESS Al

ADORESS AJ 14

15 ADDRESS AZ

HI-507A

Section 11 for Packaging

L ___ _
... OA£SSI""UTIUfFEA
A/lDUVUSHlfTER

HI-507A

TOP VIEW
+vSUPPlY

I

OUT B 2
NC 3
IN 88
IN 18

IN 6B
IN 58

•

28
27
26
25
24
23

OUT A
-VSUPPLY
IN SA
IN 7A
IN 6A
IN SA

IN 48

8

22 IN 4A
211N3A

IN 38

9

20 IN 2A

IN 28 10

IN lB 11
GND 12
VREF 13
NC 14

19
18
17
16
15

IN lA
ENABLE
ADDRESS AO
ADDRESS AI
ADDRESS A2

DIGITAL

AOOAESS

r
...

I

"

4-9

SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS

V

Total Power Dissipation*
Operating Temperature

40V

Supply Voltage Between Pins 1 and 27

+20V

. VREF to Ground. V+ to Ground
VEN, VA, Digital Input Overvoltage:

I
I

-55 0 C to +125 0 C
OOC to +75 0 C
-65 0 C to +150 o C

H 1-50SAl507 A-2
HI-50SA/507A-5
Storage Temperature

+4V

VSuppl y (+)
A VSuppl y (_)

1200mW

-4V

Analog Overvoltage:
Vs

VSupply (+)

+20V

VSupply (-)

-20V

ELECTRICAL CHARACTERISTICS

=

*Derate 8mW/oC above TA

=+750C

(Unless otherwise specified)

=

Supplies +15V, -15V; VREF (Pin 13) Open; VAH (Logic Level High) ;,- +4.0V; VAL (Logic Level Low)
For Test Conditions, consult Performance Characteristics section.
HI-S06A/S07A-2
-55°C to +1250 C
PARAMETER

TEMP.

MIN.

Full

-15

TYP.

=+O.8V

HI-S06A/S07A-S
oDe to +150C

MAX.

MIN.

+15

-15

TYP.

MAX.

UNITS

+IS

V

I.S
2.0

Kn
Kn

±SO

nA
nA

±SOO
±250

nA
nA
nA

TRUTH TABLES

ANALOG CHANNEL CHARACTERISTICS
ilVS. Analog Signal Range

-RON. On Resistance (Note 11

+2SoC
Full

1.2
I.S

-IS (OFF). Off Input Leakage Current

+250 C
Full

0.03

+25 0 C

1.0

·'0 (OFF). Off Output Leakage Current

HI-506O
HI-507A
.

·'0 (ON). On Channel Leakage Current

HI-S06A
HI-S07A

1.5
I.S
0.03

±SO

Full

1.0
±500
±2S0

Full
+2S oC
Full

*10 (OFF) with Input Overvoltage Applied

(Note 2)

I.S
2.0

4.0

4.0

nA
/lA

2.0

+250 C
Full
Full

0.1

0.1
±SOO
±2S0

±SOO
±2S0

nA
nA
nA

HI-506A
A3

A2

AI

AO

EN

X

X

X

X

l
l
l
l
l
l
l
l
H

l
l
L
l

l
l
H
H
L
L
H
H
L
L
H

l
H
l

l
H
H
H

H

H

H

H

H
H
H
H

L
L
l
L

H

H
H

H

I

DIGITAL INPUT CHARACTERISTICS
VAL. Input low Thremold TTL Drive
VAH.lnput High Threshold (Note 7)
VALl
VAH

MOS Drive (Note 3)

*'A,lnputleakage Current (High or Low)

Full
Full

4.0

+250 C
+250 C

6.0

O.S

O.S
4.0

O.S

O.S

V
V

5.0

/lA

6.0

Full

1.0

SWITCHING CHARACTERISTICS
tA,AccessTime

+2SoC

IOPEN, Break-Before Make Delay

+250 C

tON (EN), Enable Delay (ON)

+2SoC

tOFF (EN), Enable Delay (OFF)

+250 C

300

O.S

1.0

V
V

0.5

/lS

SO

SO

ns

300

300

ns

300

ns

+250 e
+2SoC

1.3
4.4

1.3
4.4

/lS

"Off Isolation" INote 4)

+25 0 C

6S

6S

dB

Cs (OFF), Channel Input Capacitance

+25 0 C

5

S

pF

Settling Time (0.',%)

(0.025%)

/l'

e

CA, Digital Input Capacitance

+2SoC
+25 0 e

50
25
S

SO
25
S

pF
pF
pF

COS (OFF). Input to Output Capacitance

+250 e

0.1

0.1

pF

Co (OFF), Channel Output Capacitance

HI-506A
HI-S07A

+250

POWER REOUIREMENTS
PO. Power Dissipation

Full

7.S

*1+, Current Pin llNote 5)

Full

0.5

2.0

0.5

5.0

mA

*h Current Pin 27 (Note 51

Full

0.02

1.0

0.02

2.0

mA

*1+, Standby INote 61

Full

O.S

2.0

O.S

5.0

mA

*1-, Standby (Note 6)

Full

0.02

1.0

0.02

2.0

mA

NOTES:

4-10

1.
2.
3.
4.

VOUT =1: 10V,IOUT = -100 /lAo
Analog Overvoltage = ±33V.
VRE F = +10V.
VEN=O.SV,RL=IK,CL=7pF,VS=
3VRMS, f· SOOKHz.

7.5

S. VEN = +4.0V.
6. VEN = O.SV.
7. To drive from OTLrrTL circuits, lK,opullup resistOR to :t5.DV supply are recommended.

.

mW

100% Tested far Dash 8

H
H
H
H

H
H
H

L
H
l
H
l

H
l

L
L
H
H

L
H

l
H

H
H
H
H
H
H
H

"ON"
CHANNEl

NONE

I
2
3
4
5

6
1

8
9

10

"1213

H
H
H

14

H

15

H

t6

HI-507A

A2

A,

AD

EN

X
L
L
L
L

X
L
L
H

X
L

L

H

H

H

L
L
H
H

L
H
L
H

H
H
H

H
L

H
H
H
H
H
H
H
H

ON
SWITCH
PAIR
NONE
1
2
3

•5
6
I
8

PERFORMANCE CHARACTERISTICS AND TEST CIRCUITS
(UNLESS OTHERWISE SPECIFIED TA ~ 25°C, VSUPPLY ~ ±15V, VAH ~ +4V, V AL ~ O.8V AND VREF ~ OPEN.)
ON RESISTANCE ••.
INPUT SIGNAL LEVel. SUPPLY VOLTAGE

TEST
CIRCUIT
NO.1

4--IOO~A

V2_

OIl

NORMALIZED ON RESISTANCE
••. SUPPL Y VOLTAGE
-;;;

~-E

I.,..-

.-

c>
l!",

.;;+-

:~
c m
02

~>
~

1.5

1.4
1.3
1.2

~;

1.1

0==
z~

1.0

0

!!O 0.9
-10

-8

-6

-2

-4

VIN

~

10
Analog Input IVallsl

Supply Voltage

1O'''''~m
OFF OUTPUT
LEAKAGE CURRENT
10 (OFF)

lt31

TEST
CIRCUIT
NO. 2*

LEAKAGE CURRENT vs. TEMPERATURE

N

;

!10V

100A~=
]

"'OA V

V'//

cu~:I~~~

./

I

A loIOFF)

-=-

-=- +lOV

*

~

TEST
CIRCUIT
NO. 3*

/.

]

II

....V

OUT

-I-/-.,,-l-----l

~DNlEAKAGE

IVoltsl

TEST
CIRCUIT
NO. 4*

---:,"',.,---..JIOL.'.,---....-J1250

1Dp\L.,.'---o',,"""'

OUT

Temperature·OC

A JolON)

EN

-Two measurements per channel:

+10vl

+1OV/-10V and -tOV/+1OV.

(Two measurements per device for ID(OFFI:

AD

I
b

"f"

+10V/-10V and -1OV/+10V.1

b

_

.2.4V

~

±10V

ANALOG INPUT OVERVOL TAGE CHARACTERISTICS

1 18r-~~,.1~-~-t--t--+--+--+-~
~ 15 5- ~ I
j...--""
;

~

~

.3 .!.

12 4·

ANALOG INPUT
r-CURRENT !lINI

1f* -

9 3- -: -;.

"/

f62.~1

..

~
_

-I

30

/1'
I

~

V

l/"

./ _V

l'o~ r-~

....-=::~

-'
;15
;18

;21

OUTPUT OFF
LEAKAGE CURRENTIO(QFFI
;24
;21
;30
;33 ;36

ANALOG INPUT
OVERVOLTAGE CHARACTERISTICS

TEST
CIRCUIT
NO.5

k
ilN

-

~

A

;VIN

~
IOIOFFI
~v~--I---l A

f---o

f---;--o

n

I-L:_....JT

VIN - Analog Input Overvoltage (Voltsl

4-11

PERFORMANCE CHARACTERISTICS AND TEST CIRCUITS (continued)
ON CHANNEL CURRENT v•. VOLTAGE

o

..

e
i

±4

t2

±6
±II
tlO
±12
V1N - Voltage Across Switch

TEST
CIRCUIT
NO.6

ON CHANNEL CURRENT
vs. VOLTAGE

±14

Br-~SU~P~PL~Y~C~U~R~RE~N~T_~~.~T~OG~G~L~E~F~RE~QTU~EN~C~Y--,

TEST
CIRCUIT
NO.7

~'5/'1O
t"SUPPLY
SUPPLY CURRENT
VI.

I

6~--~~--~----~----~'----i

§

Vr UPPLY =

u

~15"" I

.
•~A

j4~--~~--~-----f--~'f'----i

JI

VSUPPLY = t l OV "

'",

I

... ~

10K

lK

lOOK

+V

1=

A3

A2

At

INt

HI-506A

AO

~±10/±S

T~:~I-,:-,-o--, -=
IN1S

IN16 --0.10/.:.5

-: =-9"- LE_N--=.GNrO~__...:°T-UTJ----o---O_H-~+<
A2 ....,..r:>o_H-~f-i

EN":"'---,=*,~:1:if1.~"i--j""'I~
____ J

IN 8
Section 11 for Packaging

HI-509

TOP VIEW

ADDRESS INPUT
BUFFER AND
LEVEL SHIFTER

HI-509
AO

AO

Al

ENABLE

15

GNO

-v SUPPLY

14

+V SUPPLY

IN lA

13

IN lB

IN 2A

12

IN 2B

IN 3A

11

IN 3B

IN4A

10

OUTA

IN 4B
OUT B

IN I

DIGITAL {
ADDRESS

A,

ENI~~
L ____ J
ADDRESS INPUT
BUFFER AND
LEVEL SHIFTER

OUT

•

I

SPECIFICA T/ONS
ABSOLUTE MAXIMUM RATINGS

(Note 1)
Power Dissipation *
750mW
(Derate 8mW/Oe above TA =+75 0 e)
Operating Temperature Ranges:
H1-508/509-2,-8
-55 0 C to +125 0 C
H1-508/509-5,-6
ooe to 70 0 e
-55 0 e to +200 0 e
H1-508/509-1

VSuppl y (+) to VSuppl y (-)

40V

VSuppl y (+) to GND
VSuppl y (-) to GND

20V
20V

Digital Input Overvoltage:
vsuPPI Y(+)
VEN,VA { VSuppl y (-)

+4V
-4V

Storage Temperature Range

Analog Input Overvoltage (Note 6):
vsuPPI Y(+)
VD, Vs { VSuppl y (-)

+2V
-2V

* Package limitation

-65 0 e to +150 0 e

ELECTRICAL CHARACTERISTICS Unless otherwise specified: Supplies =:!: 15V, GND = OV
HI-50BIHI-50S-2
-55 0 Cto+1250C
PARAMETER

TEMP

MIN

Full

-15

TYP

HI-50BIHI-509-5
OOC to +70 0 C

MAX

MIN

+15

-15

TYP

MAX

UNITS

TRUTH TABLES

ANALOG CHANNEL CHARACTERISTICS
VS, Analog Signal Range

•

RON. On Resistance

+25 0 C
Full

lBO
230

to RON, Any Two Channels

+25 0 C

5

IS(OFF), Off Input Leakage Current (Note 2)

+25 0 C
Full

10(OFF), Off Output Leakage Current
HI-50B
HI-50S

+25 0 C
Full
Full

10
10

200
100

IOWN). On Channel leakage Current

+25 0 C
Full
Full

10
10

+25 0 C
Full

1
5

HI-50B
HI-509
IOIFF. Differential Off Output Leakage Current

(HI-509 Only)

300
400

lBO
230

+15

V

400
500

n
n

5
10
50

10
50

nA
nA

10
10

200
100

nA
nA

200
100

10
10

200
100

nA
nA

5
50

1
5

5
50

nA
nA

DIGITAL INPUT CHARACTERISTICS
VAH, High Threshold

Full

VAL, Low Threshold

Full

O.B

O.B

V

IA. Input Leakage Currellt (High or Lowl {Note 3}

Full

1

1

J1A

1000

ns
ns

2.4

HI-50S

%

2.4

V

A2

Al

AO

EN
L
H

"ON"
CHANNEL
NONE
1

H
H

'3

X

X

X

L
L
L
L
H
H
H

L
L
H

L

H

H

H

H
L
H
L
H
L
H

L
L
H

H
H
H

H
H

2
4
5

6
7
B

SWITCHING CHARACTERISTICS

tA, Access (Transition) Time

+250C
Full

220

500
1000

220

tOPEN. Break-Before-Make Interval

+25 0 C

70

70

ns

tON(EN), Enable Turn-On

+25 0C

210

210

ns

Al

AO

EN

tOFF(EN), Enable Turn-Off

+25 0 C

lBO

lBO

ns

X

X

L

+25 0C

360
600

360
600

ns
ns

L
L

L

+250 C

H

Off Isolation (Note 4)

+25 0 C

6B

6B

dB

CS(OFF). Channel Input Capacitance

+25 0 C

5

5

pF

H
H

H

H
H
H
H

CO(OFF), Channel Output Capacitance

+25 0 C

21

21

pF

CA. Digital Input Capacitance

+25 0C

3

3

pF

COS(OF F~. Input to Output Capacitance

+25 0 C

.OB

.OB

pF

tS. Settling Tme

to 0.1%
to 0.01%

POWER REQUIREMENTS

1+, Positive Supply Current (Note 5)

Full

2

2

1-, Negative Supply Current (Note 5)

Full

1

1

mA

PO. Power Dissipation

Full

45

45

mW

NOTES: 1. Absolute maximum ratings are limiting values,

applied individually, beyond which the servjce~
ability of the circuit may be impaired. Functional
operation under any of these conditions is not
necessarily implied.
2. Ten nanoamps is the practical limit for high
speed measurement in the production test
environment. Actually, IS (off) is below 100pA
for most devices, at 25 0 C.
3. Digital input leakage is primarily due to the clamp
diodes (see Schematic). Typical leakage is less
than 1nA at 25 0 C.

4-16

HI-509

mA

4. VEN =O.BV, Rl =lK, Cl =15pF, Vs =7VRMS,
f = 500kHz. Worst case isolation occurs on channel
4 (HI-50B) and channels 4, B (HI-5091. dueto

proximity of the output pins.
5. VEN

=OV or 5V.

All VA =O.

6. If an ovelVoltage condition is anticipated (analog
input exceeds either power supply voltage). the
HARRIS HI-50BA/509A multiplexers are

recommended.

L

"ON"
CHANNEL
NONE
1
2
3
4

~

,

PERFORMANCE CHARACTERISTICS AND TEST CIRCUITS
ON RESISTANCE vs.
INPUT SIGNAL LEVEL. SUPPLY VOLTAGE

Unless Otherwise Specified; TA =25 0C, VSupply =±15V,
VAH =2.4V, VAL =o.av.

--GDV2 _ _ _

•

TEST CIRCUIT

RON;~
'rnA

--0

NO.1

'N
OUT

~~~
V,N

-=-

ON RESISTANCE
VS. ANALOG INPUT VOLTAGE, TEMPERATURE
400

NORMALIZEO ON RESISTANCE
VS. SUPPL Y VOLTAGE

2.2
+1250C~TA~-55OC

:; 2.0

------

300
TA=+1250C
TA =+250C

200
lOa

.......

~~

"

.j~
~N>-i
~ e

........

/

5~

Z

TA' -550C

0
-15

-10

+5

0

-5

"'

1.6
1.4

.........
..........

1.2

.......

ii 1.0

~

+10

V,N =OV

1.8

0.•

+15

!1!

!1!

t7

VIN Analog Input(VolUI

LEAKAGE CURRENT VS. TEMPERATURE
100nA

IOnA

:::;:::::::::::

===='

10 10ff) - "*.'oIOnl

-

"*

./ '" Off
Inpu'
Leakage Current -

EN

100°

75°

+2AV

3.0

4
;(

... 3

.§

!....

~

~

"0

"

i.--

-

1

>

0

:!6 :!8

tlO tl2 tl4 tl6 tl8

Power Supply Voltage (Volts)

no

100

'"c

80

~

60

==
"I

40

~

2.0

.3

I

:z:

""

OFF ISOLATION vs.
FREQUENCY

POWER SUPPLY CURRENT
VS. TEMPERATURE

~

i I
~

±1OV

,f

~

125°

LOGIC THRESHOLO
vs. POWER SUPPLY VOLTAGE

~

===+lDV

A IOIONI

_

Temperature DC

2

J-

OUT

+10vl
500

EN--o+O.8V

IS IOff)

F~
250

•

~j

~!

-Two measurements per channel:
+10V/-1OV and -10V/+10V.
CTwo measurements per device for IDCOFFI:
+1OV/-1OV and -1OV/+1OV.l

NO. 4*

IOpA

I--

:t15

-=1=-

/

100pA

I--

±10V-=-

~±10V

TEST CIRCUIT

~

V

'SIOFF:~

A IO(OFF)

~

/

/'

InA

NO. 3*

±lDV-=-

Current

1g-

TEST CIRCUIT

j

onLe~7

±14

NO. 2*

OUT

===Leakage Current

±lO tll
±l2 ±13
Supply Voltage (Volts)

TEST CIRCUIT

Jfll-

/'

Off OU'pu,

----

O.S

EN' OV- f-

me

2.2-

II

-

i

II~L 10M
1111

20 VEN = O~'I I
I

0
-55 -35 -IS -5 25 45 65 85 105 125
Temperature (DC)

RL = IK

Ni

0

EN =5V ~
1.0

11111111
~

0
104

I

IliluL 1

CLOAp,~,~8pF

lOS

106

107

~Frequency (Hz)

4-17

I

PERFORMANCE CHARACTERISTICS AND TEST CIRCUITS (continued)
TEST CIRCUIT
NO.5

ON CHANNEL CURRENT VS. VOLTAGE
70r-~---r---r--~--r--,---r--~

T~ -S5!C ~
SOf---+--+--+--+-:::;;;:ooI-"'~=f:=
....t--1. . . ---:::...--r TA=250C
3
...0/
~
I
601----+--+---+--+--

=

ON CHANNEL CURRENT

"l!

~s

c

40

~ 30

//

10

AV/

+i

~

/.:V"

"I 20

0"o

t2

VOLTAGE

HI-SOB

TA=+1250C--

.....

±6

±4

±S

±10

±12

±14

'16

VIN - Voltage Across SWitch

TEST CIRCUIT
NO.6
SUPPl V CURRENT
vs TOGGLE FREOUENCY

SUPPLY CURRENT vs. TOGGLE FREQUENCY
'" S

t

~'5/"0

r-----.------r---.-..."I/,-----,

+V
INt r-----o+10/f5

E 6f----+------+-----+-----f----~
VSuppl y ::

~

±15"-J

r----._.......-lA2

~ 4f----+------+-----+--~-t----~

I

vS uppr±10V ......

/..!

., 2~=+==:j:::::
17//or'l
ot::=:t==±=~----+----J.
lK
10K
lOOK
1M
10M

'~A

L

A

L

500

-

-<>--,

IN2f-,:

HI-SOB

T,~R~
IN.

A:

0-

- {VA~=3'5+:V
-=VA

Toggle FrequencY,Hz

"SUPPlY

EN

OUT""

GNO

V

<---...;;;:.;i'-----.;:.;.4-......

~~;~:YCYCLE

t;
_

f---o -10/-5 10MO

14 ,f

.

A,1:'~~,:lY' -=

-=

SimHar connection for HI-509
TEST CIRCUIT
NO.7
ACCESS TIME

VS.

ACCESS TIME
V5

LOGIC LEVEL (HIGH)
V+

600

]:
E
;=

J,

'1

~

400

$
2

IN 1 r-o±10V

L

A2

L:;

IN2THRUINl

H'..... ·i-O".'"

~ ~'".?;-" I .~

I"'-..

200

0

lOGIC lEVEL (HIGH)

4

3

5

13

14

VAH - Logic Level (Highi. Vol ..

om

fJ:+l

15

Similar connection for HI-S09

ITI
L ____ -'

SWITCHING WAVEFORMS
VAH;3.5V

ACCESS TIME

ADDRESS
DRIVE(VA)

~
VAL=OV

I

Y.VAH

I

+10V

I

-

\--av

OUTPUT
-10V

~+-+t-+--t----,I:-- OUTPUT
1VIOI~

s 8, ON
200 NS/DIV

4-18

++--+---1

SWITCHING WA VEFORMS (continued)
TEST CIRCUIT
NO.8
BREAK-BEFORE-MAKE

BREAK-BEFORE MAKE DELAY(tOPEN)
ENABLE DRIVE

DELAY (tOPEN)

t15V

VAH ° 3.5V

I i~VEIVAJ
VA~
~
50%
50%

.,v

.v

A,

AOORESS

"--

I- VA INPUT

A, HI-50B

OUTPUTA

AO

, ,

IV/DIV

s, ON
IN 8

Your

"'

EN

-+I ~
'OPEN

S 8 ON

12.5pF

'J~TPUT

1

"

lV/OlV

I
IV

100 NS/DiV

Similar connection for HI-509
TEST CIRCUIT
NO.9
ENABLE DELAY

ENABLE DELAY(tONIEN), tOFFIEN»
ENABLE DRIVE

(tON(EN) ,tOFF(EN»

+15V

I I

VAHo3.5V

~v~_ -

-

I

-t. .--I

90%

VAL °

"j

A,

ov

~
I
I
I
I

OUTPUT A
OUTH~'----'

90%

J

zoo
n

--+j 'ONIENJ J -

I

I

I 'OFF I
--+IIENJI-15V

f-

II

ENABlE

DRIVE
2V/DIV

J ,I
l 'I

SIaN

I
I II
I I

82 THRU Sa OFF

OUTPUT

iVlO'~

--' ,-- r--

100 NS/DIV

Similar connection for H1-509

SCHEMATIC DIAGRAMS
ADDRESS DECODER

ADDRESS INPUT BUFFER
LEVER SHIFTER

TO P-CHAN.

DEVICE OF
THE SWITCH

TO N-CHAN.

DEVICE OF
THE SWITCH

ENABLE

DELETE IA2 OR A2) INPUT FOR HI-509

All N-Channel Bodies to VAil P-Channel Bodies to V+ Unless Otherwise Indicated.

4-19

SCHEMA TIC DIAGRAMS (continued)
MULTIPLEX SWITCH

TTL REFERENCE CIRCUIT

APPLICATIONS
32 CHANNEL BUFFERED MULTIPLEXER

II

CHANNEL

,...

80
9

16

····
·

32

OUT

oi

A2
A1
AO
EN

9
4

···
·
o!---l!.

··
·

OUT
A2
A1
AOEN

HI-508

4

·····
-·

",4
25 V;

-

HI 508

9

,.,

17 \.r.

24

4

HI-508
OUT
A2
A1
AO
EN

HI-508
OUT
31 4

A2
A1
AO
EN

4i

1 2T 8

6

HA-2405
PRAM

7

6

DO 01

1

4028A
DECODER*

EN

~

5f

OUT

A 10
B 13
C 12

200
10

ouiPUT

COMP
--15pF

(

,AO

)
)
A1 A2

)
)
A3 A4
i

CHANNEL SELECT
*Optional; Provides Greater Isolation for AC Signals.

4-20

7

(

SYSTEM ENABLE

APPLICATIONS (continued)

ONE OF 8 DECODER

ACTIVE LOW

ACTIVE HIGH
+5V
+5V

I

I

EN

EN

1'>

HI-50a

HI-50a

.()

J".

-:r-

-

J".

.r'\

OUT

~

OUT

J".
f'o
r'\
.r'\

AO A1 A2

6 6 6 ~~>.:~:-:.~

)-

10 K

_.....

II

4-21

HI-50BA/509A

mHARRIS

8 Channel CMOS Analog
Multiplexers with Overvoltage Protection
FEATURES

DESCRIPTION

•
•
•
•
•
•
•

ANALOG/DIGITAL OVERVOLTAGE PROTECTION
FAI L SAFE WITH POWER LOSS (NO LATCH UP)
BREAK-BEFORE-MAKE SWITCHING
DTL/TTL AND CMOS COMPATIBLE
±15V
ANALOG SIGNAL RANGE
500ns
ACCESS TIME (TYPJ
SUPPLYCURRENTAT1MHz
ADDRESS TOGGLE (TYP.)
4mA
7.5mW
• STANDBY POWER (Typ;)

APPLICA TIONS

•

The H1-50BA and H1-509A are dielectrically isolated CM OS
analog multiplexers incorporating an important feature; they
withstand analog input voltages much greater than the supplies.
This is essential in any system where the analog inputs originate
outside the equipment. They can withstand a continuous input
up to 10 volts greater than either supply, which eliminates the
possibility of damage when supplies are off, but input signals
are present. Equally important, they can withstand brief input
transient spikes of several hundred volts; which otherwise
would require complex external protection networks. Necesarily, ON resistance is somewhat higher than similar unprotected devices, but very low leakage currents combine to produce low errors. Application Notes 520 and 521 further explain
these features.

• DATAACaUISITION
The H1-50BA-2 and H1-509A-2 are specified over -55 0 C to
+125 0 C while the -5 versions are specified over OOC to +75 0 C.

• INDUSTRIAL CONTROLS
• TELEMETRY

PINOUT

FUNCTIONAL DIAGRAM

HI-508A

Section 11 for Packaging

HI-508A

TOP VIEW

AO

16

AI

EN

15

A2

-V,up

14

GND

OU;ITAl

INI

13

+V,up

IN2

12

IN5

IN3

11

IN6

10

IN7

IN4
OUT

AaOllESS

INS

MULTIPLEX

AOOlIlSSIMt'U'IUFUII

SWITCHES

AJilDLlIIElSHlfTEII

HI-509A

Section 11 for Packaging

HI-509A

TOP VIEW

AO

AI

EN

15

GND

14

+Vsup

INIA

13

INIB

IN2A

12

IN2B

IN3A

11

IN3B

10

IN4B

OUTA

I

I

16

-V sup

IN4A

,.----,

OUTB

~_::r~~~~~}-~~~

DIIUTAL

ADDRESS

I
I

,
I

I
I

I ____ J
L
ADORESSIN""'UFFER
"'.0 uvu SHIFTER

4-22

DUDDUS

MUlTIPLEX

SWITCHES

SPECIFICA TlONS
ABSOLUTE MAXIMUM RATINGS
Voltage between Supply Pins

40V
20V

V+ to Ground

Total Power Dissipation*

VEN, VA, Digital Input Overvoltage:
VA

HI-508A/HI-509A-2
HI-508A/HI-509A-5
Storage Temperature

I
I

VSuppl y(+) +4V
VSuppl y (-) -4V
Analog Input Overvoltage:
Vs

725 mW

Operating Temperature:

VSuppl y (+) +20V
VSuppl y (-) -20V

-55°C to +125°C
ooe to +75 0e
-65°C to +150 0e

*Derate 8mW/De above tA = 750C

ELECTRICAL CHARACTERISTICS (Unless Otherwise Specified)
Supplies = +15V. -15V; VAH (logic level High) = +4.0V; VAL (logic level low) = +O.BV
For Test Conditions, consult Performance Characterisitcs section.
H1-50BA/509A-2

HI-50BA/509A-5
OOC to +75 0C

-55 0 C to + 125 0 C
PARAMETER

TEMP.

MIN.

TYP.

·Vs. Analog Signal Range

Full

-15

.. RON. On Resistance (Note 1)

+25 0 C
Full

1.2

+25 0 C
Full

0.03

+25 0 C
Full
Full

1.0

*IDIOFFI with Input Overvoltage Applied (Note 21 +25 0 C
Full

4.0

+25 0 C
Full

0.1

MAX.

MIN.

+15

-15

TYP

MAX.

UNITS

TRUTH TABLES

ANALOG CHANNEL CHARACTERISTICS

*IS(oFFI. Off Input Leakage Current
*1010 FFI. Off Output Leakage Current
HI-50BA
HI-509A

*IO(ON)' On Channel Leakage Current
HI-50BA
HI-509A

1.5

1.5
1.B

1.5
l.B

+15

V

l.B
2.0

HI

~50

nA

"ON"
A2 A1 AO EN CHANNEL

:':250
1.125

nA
nA
nA

x

:':250
1.125

/1 A
nA
nA
nA

nA

0.03
1.0
±250
1.125
4.0

nA

2.0
0.1
~250

I 1.125

DIGITAL INPUT CHARACTERISTICS
VAL. Input low Threshold
VAH.lnput High Threshold

I

(Note 61

*IA' Input leakage Current (High or low)

Full
Full

O.B
4.0

O.B
4.0

Full

V

V

1.0

1.0

HI-508A

Kn

X X
l
l
L L H
L H l

H

l
H

H
l

H
L

H
H

H

L

H

H

H

H

L

H

5
6
7

H

H

H

H

8

l

L
H

NONE
1

H

2
3

II

I

4

/1 A

SWITCHING CHARACTERISTICS
tA, Access Time

+25 0 C

0.5

tOPEN. Break - Before Make Delay

+25 0 C

BO

1.0

0.5
BO

/1s
ns

HI-509A

tON(ENI. Enable Delay ION)

+25 0 C

300

300

ns

tOFF (ENI. Enable Delay (OFF)

+25 0 C

300

300

ns

ON
SWITCH

Settling Time 10.1%1
(0.025%1

+25 0 C
+25 0 C

1.2
3.5

1.2
3.5

/1s
/1s

"OFF Isolation" (Note 3)

+25 0 C

65

65

dB

Cs (0 FFl. Channell nput Capacitance

+25 0 C

5

5

pF

Co (OFF). Channel Output Capacitance
HI-50BA
HI-509A

+25 0 C
+25 0 C

25
12

25
12

pF
pF

CA. Digital Input Capacitance

+25 0 C

5

5

pF

COS (OFF). Input to Output Capacitance

+25 0 C

0.1

0.1

pF

Full

7.5

Full

0.5

2.0

0.5

5.0

mA

*1-, Current
(Note 4)
*1+. Standby (Note 5)

Full
Full

0.02
0.5

1.0
2.0

0.02
0.5

2.0
5.0

mA
mA

*1-. Standby (Note 5)

Full

0.02

1.0

0.02

2.0

mA

PAIR
X

X

L

NONE

l

L

H

1

L H H
H L H

2

H H H

4

3

POWER REQUIREMENTS

po. Power Dissipation
-1+, Current

NOTES:

(Note 4)

1. VOUT ~:!: 10V. IOUT= -100J.1A
2. Analog Overvoltage :::: ~ 33V

3. VEN = O.BV, RL
Vs

'*

= 3V

RMS. f

~

lK. C L = 7pF,

= 500KHz

7.5

mW

4. VEN = +4.0V
5. VEN = O.BV

Kn

6. To drive from DTL/TTL Circuits, 1
pull·up
resistors to +5.0V supply are recommended

100% Tested for Dash 8 at +25 0 C and +125 0 C Only.

4-23

PERFORMANCE CHARACTERISTICS AND TEST CIRCUITS
UNLESS OTHERWISE SPECIFIED: TA = 25 0 C, VSUPPl Y = +15V, VAH = +4V, VAL = O.BV
+---"ooJlA

..

R _ V2
ON - 100JlA

TEST CIRCUIT
NO.1

v2

f--o

IN

-:~

-

ON RESISTANCE
ANALOG INPUT VOLTAGE

VS.

VIN

-

ON RESISTANCE vs.
INPUT SIGNAL lEVel, SUPPl Y VOLTAGE

r--o

OUT

NORMALIZED ON RESISTANCE
vs. SUPPLY VOLTAGE

1.4
1.3

TA - +12SoC

C;

1.2

I

'",

II

1,:0

TA =+25 0C

~

0.9

TA = -55°C

c5

0.8

~~
Ii ~

---

';;'+1

-8

-6

-4

-2
0
2
4
VIN -Analog InpullVolts)

6

8

.......

:: ~ 1.3

"'-

.: ~ 1.2
.>
~ S 1.1

U!
.g of!
~

-10

+1250C ?:TA ?:-S50C _
VIN =+5V

1.5

1.4

"

1.0

"-

0.9
0.8

10

~

±7

t5

t5

±8

tl0 ±ll
±12
!9
Supply Voltage· Volts

±13

±14

±IS

lEAKAGE CURRENT VS. TEMPERATURE

II

Jtn-

/"
OFF OUTPUT
LEAKAGE CURRENT
'OIOFF)

10nA

V

InA

L

!

/

50'

1'8 I-!
~ 15 d
.:J.L

"*

lgo 9 3-:
6

Z

31 .. 5.

"

0

2'~.i

!

=- 0

~

ANALOG INPUT
4.!~- r-CURRENT (IIN~

-

./

..... .."

'/

V

OUTPUT OFF
LEAKAGE CURRENT10IOFF)
t21 ±24 ±27 t30 ±33 t36
tl8
VIN - Analog Input Ova1Voltage (Voltsl

~r/
tiS

~~

./

J !+10V

TEST CIRCUIT
NO.5

!

EN~+O.8V

OUT
A IOIONI

EN

+10vl

·125'

-- ~ ~J

*Two measurements per channel:
+1OV/-1OV and -1OV/+10V .
(Two measurements per device for IO(OFF}:
+1OV/-1OV and -1OV/+1OV.}

LEAKAGE CURRENT
IS (OFF)

ANALOG INPUT OVER\fOl TAGE CHARACTERISTICS

a l2

'*

r\ OFF INPUT

75'
100'
Temperature-DC

±lOV-=-

-=-+-'ov

J-

./ ./

~IOFFI

A

±10V~

F~
10pA
25'

ISIOFF:~

OUT

TEST CIRCUIT
NO. 4*

/

V

/

100pA

V

ON LEAKAGE
CURRENT
1010N',Y

./

4-24

TEST CIRCUIT
NO. 3*

TEST CIRCUIT
NO. 2*

IDOnA

_

HV

±1OV

~

ANALOG INPUT OVERVOlTAGE CHARACTERISTICS

liN

~

W. tLJ
~

-=-

1010FFI

.A

-=-

PERFORMANCE CHARACTERISTICS AND TEST CIRCUITS (continued)

V:/"": V

~ ±12

~

en

-

±10

h

lh ~

±6

0

ON CHANNEL CURRENT
vs. VOLTAGE

~ ...-- +12S OC

,.a ~

±4
±2

55OC

+25 0C

~
= ±8
c.:o

·i"",

TEST CIRCUIT
NO.6

ON CHANNEL CURRENT vs. VOLTAGE

±14

~

~"

-:-0

I-

±12
±10
±8
VIN - Voltage Across Switch

±6

0-

.0.. ......(").

~v*

9

I

-:.=

f'"

TEST CIRCUIT
NO.7

A

SUPPLY CURRENT vLTOGGLEFREQUENCY
8

..:

E

~.

r-

I

S

~
c.:o

I

V1SUPPLY = ±15~

j4

.~

JI
---7'

I

±I 2
0

lK

10M

AO

....§

700

~

600

INS

I

400
300 3

4

5

~
~

-= -;:8

7

9

10

11

12

13

14

'y

i ~,::"::" ~

5D!!.~
,VAH

6

1
--=--=-wrP -

ACCESS TIME VS.
LOGIC LEVEL(HIGH)

.JI.

....... ~

~

lQMn

AH = 4V
VA VAL =oav
50% ~UTY CYCLE
'SIMILAR CONNECTION FOR HI-S09A

.~

~

\,

:

~'~

GND

...!l..

< 500
:!-

IN7

EN

900
800

THRU

TEST CIRCUIT
NO.8

ACCESS TIME vs. LOGIC LEVEL (HIGH)

!

IN2

HI-50BA

r

1M

10K
lOOK
Toggle Frequency. Hz

INI ~+10/+fr,

J~

son

SUPPLY CURRENTvs.
TOGGLE FREQUENCY

'v

-= ~.~

VSUPPLY = ±lOV "-

,

en

+ISUPPlY

IN 1 ~:!:.10V
~

IN 2THRUIN 7
IN a

HI-508A

~+10V-=- PROBE

OUT
GNO

I

i

15

VAH -Logic Level (Highl. Volts

'"' r----...,I
1
I
I
I

lOMnl.

tfl
-=

L __ - - - 'I

• SIMILAR CONNECTION FOR HI-50SA

SWITCHING WAVEFORMS
ACCESS TIME
V

=4.0

ADDRESS

~)

IWAH

VAL=OV

I

I--

I~PUT

1

VA
2V/DIV.

I

-.

+~UTPUTA
1

·BV

-lOV

17

J

I

I

-I

-

OUTPUT A
Sy/DIVj

I
'A

1-

i'..

I
J

200nslOov.

4-25

SWITCHING WAVEFORMS (continued)
TEST CIRCUIT
NO.9
BREAK BEFORE MAKE DELAY (tOPEN)

I~PUT

VAH = 4.0

VA
2VIOIV .

I I~VEIVAI
OV~
ADDRESS

~
50%

DUTPUT

~

• IV

IN 1
IN 2
THRU
IN J
IN 8

"

50%

,

BREAK BEFORE MAKE OELAY (tOPEN)

I

r
VOUT

OUT

t+-

IOPEN

12.SIlF

\J

OUTPUT
.SVIDIV.

\ I

,I
~

V
lOOnsiON.

'SIMILAR CONNECTION FOR HI-509A

TEST CIRCUIT
NO.10
ENABLE DELAY (tON(EN)' tOFF(EN))

ENABLE DELAY (tON(EN)' tOFF(EN))

ENABLE DRIVE
EN;BLE
DRIVE
2V/OIV.

VAH = 4 0
IN 1
v.v:f- -

-

-\

1

I

II

IN 2
THRU

~VA-L~-no~v-

1

I
90~r""--+:-'\

_"';'-_..11:

I

IN 8
OUTPUT
OUT 1-0-._--,

~

,.

---+( 10NIENI 1 -

I

I

l

I 'OFF I
-IIENII4--

• SIMILAR CONNECTION FOR HI-509A

If
'I

OUTPUT
5VIOIV.

\

lOOnslD" .

SCHEMA TIC DIAGRAMS
TIL REFERENCE CIRCUIT

r---------,
I
V+ I
1
I

1
1

I

I

I

I
I
I

ADDRESS INPUT BUFFER
AND LEVEL SHIFTER

I
I
IL.. __G!!D______ -II

-- - --

------~-

LEVEL SHIFTER
-- - - --- ---- -- --- ----,
V+
I

LEVEL
SHIFTED
ADDRESS
TO DECODE
LEVEL

+--+-::-f-.... SHIFTED
ADDRESS
TO DECODE

I
GND
L ___________________________________
.JI

4-26

r'-..

SCHEMA TIC DIAGRAMS (continued)

.y

ADDRESS DECODER
TO P·CHANNEL
DEVICE OF
THE SWITCH PAIR

TO N·CHANNEl
DEVICE Of
THE SWITCH PAIR

v-

MULTIPLEX SWITCH
OE;~~~ >.;>----------.-----------<0---.
OVEAVOLTAGE PAOTECTION

r--------

II

All

I

IN
IK

V-

L _______________

~

oe~~~~>.~----------+--------!

4-27

HI-516

~HARRIS

16 Channel/Differential
8 Channel CMOS High Speed
Analog Multiplexer

FEATURES

•

DESCRIPTION

• ACCESS TIME (TYP)

lOOns

• SETTliNG TIME (TYP TO 0.01%)

800ns

• LOW LEAKAGE IS OFF
ID OFF

10pA
35pA

•

LOW CAPACITANCE Cs OFF
CD OFF

2.5pF
18pF

•

HIGH OFF ISOLATION AT lMHz

BOdB

•

LOW CHARGE INJECTION

0.3pC

, • SINGLE ENDED TO DIFFERENTIAL
SELECTABLE (SDS)
•

LOGIC LEVEL SELECTABLE (LLS)

• DATA ACQUISITION SYSTEMS
PRECISION INSTRUMENTATION

•

INDUSTRIAL CONTROL

"

"

The HI-516 is available in a 28 lead dual-in-line package. HI-516-5 is
specified for operation over OOC to +75 0 C, and the HI-516-2 over -55 0 C
to +125 0 C. Processing to MIL-8TD-883A, Class B screening is available
by selecting the HI-SI6-8.

APPlICA TIONS
•

The HI-51 6 is a monolithic dielectrically isolated, high speed, high performance CMOS analog multiplexer. It offers unique built-in channel selection decoding plus an inhibit input for disabling all channels. The dual
function of address input A3 enables the HI-516 to be user programmed
either as a single ended 16-channel multiplexer by connecting 'out A' to
'out B' and using A3 as a digital address input, or as an B-channel differential multiplexer by connecting A3 to the V- supply. The substrate leakages and parasitic capacitances are reduced substantially using the Harris
dielectric isolation process to achieve optimum performances in both high
and low level signal applications. The low output leakage current (I DOff
< 100pA @ 25 0 C) and fast settling (tsETTlE = 800ns to 0.01%) characteristics of the device make it an ideal choice for high speed data acquisition
systems, precision instrumentation, "and industrial process controls.

PINOUT

FUNCTIONAL DIAGRAM
Section 11 for Packaging

VDD/LLS
INIA

TOP VIEW
V+

2S

DUTA

EN>+--------~~

OUTB

27

V-

NC

26

INS/SA

Ao>+--------T+-H
Al>i---------,+t+l

IN16/SB

25

IN7I7A

IN15i7B

24

IN6/6A

IN 14/6B

23

IN5/5A

IN13/5B

22

IN4/4A

IN12/4B

21

IN3/3A

IN 11/3B

20

IN2/2A

19

IN1/1A

IN10/2S

4-28

10

IN9/1S

11

18

ENABLE

GND

12

17

AO

VDD/LLS

13

16

A1

A3/SDS

14

15

A2

A2>+-------M~~

Aa
A3 Decode

I
I
I

A3 Q Q
H H L

I
I

L

L H

I

V-

L L

I

I

DECODER

I
I

IL

I
I
__________
INPUT BUFFER AND DECDDERS

~

____ I
~

MULTIPLEXER
SWITCHES

SPECIFICA TlONS
ABSOLUTE MAXIMUM RATINGS
Digital Input Overvoltage:
-6V< VAH <+6V
TTL
A2 VSUPPL V (-)
VSUPPLV(+)
CMOS
GNO
Analog Input Voltage:
{ VSUPPL V(+)
Vs
VSUPPL vI-)

Voltage Between Supply Pins
Total Power Oissipation*
Operating Temperature Ranges:
HI-516-2
HI-516-5
Storage Temperature Range
*Oerate BmW/oC above tA

-2V
+2V
-2V
+2V
-2V

33V
1200mW
-55 0 C to +1250 C
OOC to 75 0 C
-65 0 C to 150 0 C
75 0 C

ELECTRICAL CHARACTERISTICS (Unless otherwise specified) Supplies = +15V, -15V; VAH (Logic Level High) = +2.4V,
VAL (Logic Level Low) =+O.BV; VOO/LLS =Open (Note 6)
OOC to +75 0 C

-55 0 C to +125 0 C
PARAMETER
ANALOG CHANNEL CHARACTERISTICS
VS, Analog Signal Range
RON, On Resistance (Note 1)
IS (0 FF). Off Input Leakage Current
10(OFF), Off Output Leakage Current
IO(ON), On Channel Leakage Current
DIGITAL INPUT CHARACTERISTICS
VAL Input Low Threshold (TTL)
VAH Input High Threshold (TTL)
VAH Input Low Threshold (CMOS)
VAH Input High Threshold (CMOS)
IAH Input Leakage Current (High)
IAL Current (Low)
SWITCHING CHARACTERISTICS
tA, Access Time
tOPEN, Break before make delay
tON(EN), Enable Delay (IN)
tOFF(EN). Enable Delay (OFF)
Settling Time (0.1%)
(0.01%)
Charge Injection (Note 2)
Off Isolation (Note 3)
CS(OFF), Channel Input Capacitance
CO(OFF), Channel Output Capacitance
CA, Digital Input Capacitance
COS(OFF),lnput to Output Capacitance
POWER REoUUIREMENTS
PO, Power Dissipation
1+, Current (Note 4)
1-, Current (Note 4)
1+, Standby (Note 5)
1-, Standby (Note 5)
NOTES:
1.
2.

VIN =±'10V.IOUT= -100J1A
VIlli = OV. CL = 100pF. Enable input
pulse = 3V, f = 500k Hz
3. VEN = O.BV. Vs = 3VRMS. f = 500kHz,
CL = 40pF. RL = 1k. Pin 3 grounded

TEMP

MIN

Full
+25 0 C
Full
+25 0 C
Full
+25 0 C
Full
+25 0 C
Full

-15

Full
Full
Full
Full
Full
Full

TVP

620
770
0.01
0.38
0.035
0.48
0.04
0.56

MAX

MIN

+15
750
1,000

-15

TVP

620
700
0.01
0.38
0.035
0.48
0.04
0.56

50
100
100
0.8

2.4

MAX

UNITS

+15
750
1,000

n
n

50
100
100
0.8

2.4
0.3VOO

0.7V OD

0.3VOO
0.7VOO

0.05
4

1
25

0.05
4

1
25

+25 0 C
Full
+25 0 C
+25 0 C
+25 0 C
+25 0 C
+25 0 C
+25 0 C
+25 0 C
+25 0 C
+25 0 C
+25 0 C
+25 0 C

100
120
20
100
80
250
800
0.33
90
2.5
18
5
0.02

150
200

100
120
20
100
80
250
800
0.33
90
2.5
18
5
0.02

150
200

Full
Full
Full
Full
Full

525
17.5
17.5
17.0
17.0

150
125

25
25
25
25

525
17.5
17.5
17.0
17.0

30
30
30
30

V

nA
nA
nA
nA
nA
nA

II

V
V
V
V
IJ.A
IJ.A
ns
ns
ns
ns
ns
ns
ns
pC
dB
pF
pF
pF
pF
mW
rnA
rnA
rnA
rnA

4.
5.

VEN = +2.4V
VEN = O.BV

6.

VOO/LLS Pin = Open or Grounded for TTL Compatibility
VOO/LLS Pin = VOO for CMOS CompatibilitY

4-29

TRUTH TABLES
HI-51S USED AS A IS-CHANNEL MULTIPLEXER OR

HI-51S USED AS A DIFFERENTIAL
8-CHANNEL MULTIPLEXER

8 CHANNEL DIFFERENTIAL MULTIPLEXER *
USE A3 AS DIGITAL
ADDRESS INPUT

II

A3 CONNECT TO V- SUPPL Y
ON CHANNEL TO

ENABLE

A2

Al

AO

OUT A

OUT B

l

X

X

X

NONE

NONE

H

L

L

l

lA

lB

L

L

H

2A

2B

L

H

l

3A

3B

H

L

H

H

4A

4B

H

H

L

l

5A

5B

NONE

H

H

L

H

SA

6B

SA

NONE

H

H

H

L

7A

7B

l

7A

NONE

H

H

H

H

8A

8B

H

H

8A

NONE

L

L

NONE

lB

L

L

H

NONE

2B

L

H

L

NONE

3B

H

L

H

H

NONE

4B

H

H

L

L

NONE

5B

H

H

H

L

H

NONE

SB

H

H

H

H

l

NONE

7B

H

H

H

H

H

NONE

8B

ENABLE

A3

A2

Al

AO

OUTA

OUT B

L

X

X

X

X

NONE

NONE

H

l

L

L

l

lA

NONE

H

H

l

L

l

H

2A

NONE

H

H

l

L

H

l

3A

NONE

H

L

L

H

H

4A

NONE

H

l

H

L

L

5A

H

L

H

L

H

H

l

H

H

H

L

H

H

H

L

H

H

H

H

H
H

• For 16-Channel single-ended function, tie 'out A' to
'out B', for dual a-channel function use the A3 address
pin to select between MUX A and MUX B, where MUX A

is selected with A3 low.

4-30

ON CHANNEL TO

mHARRIS

HI-518
8 Channel/Differential
4 Channel CMOS High Speed
Analog Multiplexer

FEATURES

DESCRIPTION

• ACCESSTIME(TYP)
• SETTliNG TIME (0.1%)
• LOW LEAKAGE IS (OFF)
10 (OFF)
• LOW CAPACITANCE (TYP) Cs (OFF)
CD (OFF)
• HIGH OFF ISOLATION@ (IMHz)
• SINGLE ENDED TO
DIFFERENTIAL MODE SELECTABLE (SDS)
• LOGIC LEVEL SELECTABLE (LLS)
• LOW CHARGE INJECTION

80ns
250ns
50pA
100pA
2pF
10pF
75dB

0.3pC

APPLICATIONS

The H1-518 is a monolithic, high performance, high speed Analog
Multiplexer, constructed utilizing the Harris Oielectrically isolated
CM OS process.
This device has the added feature that it can be user programmed
either as a single ended 8-channel multiplexer by connecting 'out A'
to 'out B' and using A2 as a digital address input,
or as a 4channel differential multiplexer by connecting A2 to the V- supply.
TTL or CM OS compatibility is also selectable. Low leakage current,
10 off < 100pA @ 25 0 C, and fast settling, 250ns to O.I%,characteristics of this device make it an ideal choice for high speed data
acquisition systems, precision instrumentation and industrial process
controls.

II

The HI-SI8 is available in an 18 lead Oual-in-Line Package. The
HI-SI8-S is specified for operation over OOC to +75 0C, and the
HI-SI8-2 over -SSoC to +1250C. Processing to MIL-STD-883A
Class Bscreening is available by selecting the HI-518-8.

• DATA ACQUISITION SYSTEMS
• INDUSTRIAL CONTROLS
• TELEMETRY

PINOUT

FUNCTIONAL DIAGRAM
Section 11 for Packaging

TOP VIEW
+V
OUT B

r----

OUTA

Voo/LLS

IN1A

I
I

aUlA

I

-V
EN

IN8/4B

IN 4/4A

IN 7/3B

IN 3/3A

IN 6/2B

IN 212A

IN4A

Ao

A,
A2

IN1!
A2DECODE

IN 5/1B
GNO

1I

OUT.

IN 1I1A
ENABLE

Voo/LLS

AO

A2/S0S

A1

DECODER

INPUT BUFFER AND DECODERS

IN4B

MULTIPLEXER SWITCHES

4-31

SPEC/FICA TlONS
ABSOLUTE MAXIMUM RATINGS
Digital Input Dvervoltage:
TTL

{-6V < VAH < +6V
A2 VSUPPL Y (-)

Voltage Between Supply Pins
Total Power Dissipation'
Operating Temperature Ranges:
HI-518-2
H1-518-5
Storage Temperature Range
'Oerate 8mW/DC above tA

-2V
+2V
-2V

CMOS { VSUPPL Y(+)
GND
Analog Input Voltage:
{ VSUPPL Y(+)
Vs
VSUPPL Y{-)

+2V
-2V

ELECTRICAL CHARACTERISTICS

33V
725mW
-55 0 C to +125 0 C
DoC to 75 0 C
-65 0 C to 150 0 C
75 0 C

(U nless otherwise specified) Supplies = + 15V, -15V; VAH (Logic Level High) = +2.4 V,
VAL (Logic Level Low) =+O.8V; VD D/LLS =Open (Note 6).
-550C to +1250C

PARAMETER

TEMP

MIN

Full
+25 0C
Full
+25 0C
Full
+25 0C
Full
+250C
Full

-15

TYP

DoC to +750C

MAX

MIN

+15

-15

TYP

MAX

UNITS

+15
750
1000

n
n

ANALOG CHANNEL
CHARACTERISTICS
Vs Analog Signal Range
RON On Resistance (Note 1)
IS (OFF) Off Input
Leakage Current
10 (OFF) Off Output
Leakage Current
10 (ON) On Channel
Leakage Current

480
700
0.05
0.60
0.10
0.30
0.10
0.30

750
1000

480
700
0.05
0.60
0.10
0.30
0.10
0.30

50
50
50

V

50

nA
nA
nA
nA
nA
nA

0.8

V

50
50

OIGITAL INPUT
CHARACTERISTICS
VAL Input Low Threshold (TTL)
VAH Input High Threshold (TTL)
VAL Input Low Threshold (CMOS)
VAH Input High Threshold (CMOS)
IAH Input Leakage Current (High)
IAH Input Leakage Current (Low)

Full
Full
Full
Full
Full

0.8
2.4

2.4
0.3VOO

0.3VOO
O.7VOO

0.7V OO

Full

0.05
4

1
20

0.05
4

1
20

+25 0 C
Full
+25 0 C
+25 0 C
+25 0 C
+250C

80
110
20
80
60
250

125
150

80
110
20
80
60
250

125
150

V
V
V
p.A
p.A

SWITCHING CHARACTERISTICS
tA, Access Time

tOPEN, Break before make Oelay
tON (EN), Enable Delay (ON)
tOFF (EN), Enable Delay (OFF)
Settling Time (0.1%)
(0.01%)
Charge Injection (Note 2)
Off Isolation (Note 3)
Cs (OFF) Channel Input Capacitance
CD (OFF) Channel
Output Capacitance
CA, Oigitallnput Capacitance
CDS (0 FF) Input to Output
Capacitance

150
125

ns
ns
ns
ns
ns

150
125

+25 0C

800

800

+250C
+250C
+250C

0.3
86
1.9

0.3
86
1.9

pC
dB
pF

+25 0C
+25 0C

10
3

10
3

pF
pF

+25 0C

0.02

0.02

pF

Full
Full
Full
Full
Full

360
12
12
11.5
11.5

POWER REQUIREMENTS
PO, Power Dissipation

1+, Current (Note 4)
1-, Current (Note 4)
1+, Standby (Note 5)
1-, Standby (Note 5)
NOTES:
1.
2.

4-32

VIN ~ ±'10V.IOUT~ -100J1A
VIN ~ OV. CL ~ 100pF, Enable
Input pulse"" 3V, f:;: 500kHz.

3.

450
15
15
15
15

VEN ~ O.SV. Vs ~3VRMS, f ~ 500kHz,
CL = 40pF, R L = 1 k. Due to the pin

to pin capacitance between IN 8/4B

360
12
12
11.5
11.5
4.
5.
6.

540
18
18
18
18

mW
rnA
mA
mA
mA

VEN ~ +2.4V.
VEN ~ O.SV.
VDD/LLS Pin'" Open or ground-

(Pin 3) and Out B (Pin 2) channel
8/46 exhibits 60dB of Off Isolation

ed for TTL compatibility.

under the above test conditions.

compatibility.

VOO/LLS Pin ~ VDO for CMOS

TRUTH TABLES
HI-518 USED AS 8 CHANNEL MULTIPLEXER DR
4 CHANNEL DIFFERENTIAL MULTIPLEXER
USE A2 AS DIGITAL
ADDRESS INPUT

DN CHANNEL TO

HI-518 USED AS DIFFERENTIAL
4 CHANNEL MULTIPLEXER
A2 CONNECT TO
V-SUPPLY

ON CHANNEL TO

ENABLE

A2

Al

AO

OUT A

OUT B

ENABLE

Al

AO

OUT A

OUTB

L
H
H
H
H
H
H
H
H

X
L
L
L
L
H
H
H
H

X
L
L
H
H
L
L
H
H

X
L
H
L
H
L
H
L
H

NONE
lA
2A
3A
4A
NONE
NONE
NONE
NONE

NONE
NONE
NONE
NONE
NONE
lB
2B
3B
4B

L
H
H
H
H

X
L
L
H
H

X
L
H
L
H

NONE
lA
2A
3A
4A

NONE
lB
2B
3B
4B

II

I

4-33

m~RIS

HI-524
4 Channel
Video Multiplexer

FEATURES

•

DESCRIPTION

•

CROSSTALK (10MHz)

>SOdB

•

FAST ACCESS TIME

150ns

•

FAST SETTLING TIME (0.01%)

SOOns

•

TTL COMPATIBLE

Three CMOS transmission gates are used in each channel, as compared
to the single gate in more conventional CM OS multiplexers. This provides a double barrier to the unwanted coupling of signals from each
input to the output. In addition, Dielectric Isolation (DI) processing
helps to insure that Crosstalk exceed s 60dB at 10M Hz.
The HI-524 is designed to operate into a wideband buffer amplifier
such as the HARRIS HA-5190. The multiplexer chip includes two
"on" switches in series, for use as a feedback element with the amplifier.
This feedback resistance matches and tracks the channel RON resistance, to minimize the amplifier VOS and its variation with temperature.

APPlICA TIONS
WIDEBAND SWITCHING
•

The H1-524 is a four channel CMOS analog multiplexer designed to
process single-ended video signals with bandwidths up to 10MHz. The
chip includes a 1 of 4 decoder for channel selection and an Enable
input to inhibit all channels (chip select).

The HI-524 is well suited to the rapid switching of video signals in
telemetry, instrumentation, radar and video systems. It is packaged
in an 18 pin ceramic DIP and operates on± 15V supplies.

RADAR

• TV VIDEO

The performance levels available are: HII-524-2, -55 0 C to +125 0 C
operating range; HII-524-5, OOC to +75 0 C operating range and
HII-524-8, -55 0 C to+1250 C operating range plus 100% screening
per MIL-STD-883/Method 5004/Class B. Chips for hybrid applications
are designated H10-524-6.

• ECM

PINOUT

FUNCTIONAL DIAGRAM
Section 11 for Packaging
12
INt

r--------,,,

rr-,,15,+-_ _

IN'~-/'

~

SIG GND

>-'+---'

SI. GND

.,....!..~3'-g'T'-,""I~"-"-1"-+
1,,,-rl"IO:-+,:-'
~+1~ ~ ~ ~t
GND

TRUTH TABLE

2
o-+--t-
-:'+--:;---'

-15V

4-34

}

Al

AO

EN

ON
CHANNEL

X
l
l
H
H

X
l
H
l
H

l
H
H
H
H

NONE
I"
2
3
4

• CHANNEL lIS SHOWN
SELECTED IN THE DIAGRAM

SPECIFICA TID NS
ABSOLUTE MAXIMUM RATINGS
Oigitallnput Overvoltage:
-6V < VAH < +6V

Voltage Between Supply Pins
Either Supply to Ground
Total Power 0 issipation
Operating Temperature Range:
HI-524-2, -8
HI-524-5
Storage Temperature Range

Analog Input (VS) or Output (VO)
+VSUPPLY +2V
-VSUPPL Y -2V

ELECTRICAL CHARACTERISTICS

33V

16.5V
750mW
-55 0C to +1250C
OOC to 75 0C
-65 0C to 150 0C

(Unless otherwise specified) Supplies = +15V, -15V; VAH (Logic Level High) = +2.4V,
VAL = (Logic Level Low) = +O.8V; VEN = +2.4V
HI-524-2, -8
-55 0C to +1250C

PARAMETER

TEMP

MIN

Full
+25 0 C
Full
+25 0C
Full
+25 0C
Full
+25 0C
Full
Full

-10

TYP

HI-524-5
OOC to +750C

MAX

MIN

+10

-10

TYP

MAX

UNITS

+10

V
n
n
nA
nA
nA
nA
nA
nA
MHz

Analog Channel Characteristics
VS, Analog Signal Range
RON, On Resistance (Note 1)
IS (OFF), Off Input Leakage Current (Note 2)
10 (OFF), Off Output Leakage Current (Note 2)
ID (ON), On Channel Leakage Current (Note 2)
3dB Bandwidth: (N ote 3)

700

700
1.5K

1.5K
0.2

0.2
50

50

0.2

0.2
50

50
0.7

0.7
50

50

20

20

II,

Digital Input Characteristics
VAL Input Low Threshold (TTL)
VAH Input High Threshold (TTL)
IAH Input Leakage Current (High)
IAL Current (Low)

Full
Full
Full
Full

0.8
2.4

0.8
2.4

0.05
4

1
25

0.05
4

1
25

150

300

150

300

V
V
p.A
p.A

Switching Characteristics
tA, Access Time (Note 4)
tOPEN, Break before make delay (Note 4)
tON (EN), Enable Delay (ON), RL = 500n
tOFF (EN), Enable Delay (OFF), RL = 500n
Settling Time (0.1%) (Note 4)
(0.01%)
Crosstalk (Note 5)
CS (OFF!. Channel Input Capacitance
CD (OFF), Channel Output Capacitance
CA, Digital Input Capacitance

+25 0C
Full
+25 0C
+25 0C
+25 0 C
+25 0C
+25 0C
+25 0C
+25 0C
+25 0C
+25 0 C

20
180
180
200
600
-65

6
4
5

20
180
180
200
600
-65
6
4
5

25
25
25
25

540
18
18
18
18

300
250

ns
ns
ns
ns
ns
ns
ns
dB
pF
pF
pF

Power Requirements
PO, Power Dissipation
1+, Current (VEN = 2.4V) (Note 6)
1-, Current (VEN = 2.4V) (Note 6)
1+, Standby (VEN = 0.8V) (Note 6)
1-, Standby (VEN = 0.8V) (Note 6)

1.

VIN=OV;IOUT=100

A

Full
Full
Full
Full
Full

540
18
18
18
18

5.

(See Test Circuit# 1)
2.

VO=±10V;VS=+10V
(See Test Circuits :::It 2, 3, 4)

3. MUX output is buffered with HA-5190 as

shown in Applications section.

25
25
25
25

mW
rnA
rnA
rnA
rnA

VIN == 10MHz, 3Vp_p on one channel, with any
other channel selected. (Worst case is channel 3
selected with input on channel 4.)
MUX output is
buffered with HA-5190 as shown in Applications

section. Terminate all channels with 75f2 .
6,

Supply currents vary less than a.5mA for switching
rates from DC to 2MHz.

4. (See Test Circuit,#- 5)

4-35

PERFORMANCE CHARACTERISTICS AND TEST CIRCUITS
(UNLESS OTHERWISE SPECIFIED TA =250 C. VSUPPLY

=± 15V. VAH =2.4V. VAL =O.8V)

ON RESISTANCE
ON RESISTANCE VS. ANALOG
INPUT VOLTAGE
1,000-,---------------::7"1

~r_

TEST CIRCUIT NO.1

__~T~A~=~+1=2~~---------

800
----lOUT 10DpA

In)

RON

TAm+250C
700 r--...:.:...----~
600
TA = -55OC

600
OUT

4oo+-_~-r_~_r~-r_

-IOV -fN -6V -4V -2V OV

2V

4V

_ _.~
6V 6V 10V

VIN (VOLTS)
VIN ' - -_ _- '

ON RESISTANCE VS. SUPPLY VOLTAGE

,,000,..-----------------,

RON

In)
800

700 +-_ _.-r_~_r~-r__,__-r_,-_.=~
9.0 9.5 10.0 10.5 11.0 11.5 12.0 12.5 13.013.5 14.0 14.5 15.0
(VOLTS)

LEAKAGE CURRENT
TEST CIRCUIT NO. 2*

Itn
N

+D.SV

OUT

j

±10V

"Two measurements per channel:
+1OV/-1OV and -1OV/+10V.
(Two measurements per device for IO(OFF):
+1OV/-10V and -10V/+10V.)

A IO(OFF)

-=-

*

-=-i=10V

~

LEAKAGE CURRENT
VS. TEMPERATURE

./

TEST CIRCUIT NO. 3*

./'V/
10 O N /

V

1.0
0.9

+O.8V

~~~~~~i 8:87
'InA)

~:6

5/

0.4
0.3
O. 2

TEST CIRCUIT NO.4 *

0. 1

_

+2.4V

4-36

~

±1OV

i/V

V

/

ISOF~'/

}Il,or
25

50
75.
TEMPI·C)

100

125

150

PERFORMANCE CHARACTERISTICS AND TEST CIRCUITS (Continued)

TEST CIRCUIT NO.5

SETTLING TIME
ACCESS TIME
BREAK-BEFORE-MAKE DELAY
HI-524

-u-

±3V

HA-5190

...+

OU'!:UT

-F-~~
:;:3Vv-

AOAl

75n

<:..E-N+-------'

1~_-o+5V

1 I

(USE DIFFERENTIAL COMPARATOR
PLUG-IN ON SCOPE FOR SETTLING
TIME MEASUREMENT.l

_-------- - /
ADDRESS DRIVE (VA)
1.6V - ; ' -

-

VAH· 2.4V

---I- -- - - - - - - - - - --

II

VAL = OV

I

+3V

-

f----

-OV-

HA-5190
OUTPUT

t-

-

ACCESS TIME. tA
SETTLING TIME. ts

2.4V-t- A

IV

-3V

t

±O.l% OF FIS
(OR±O.Ol%)

ACCESS TIME

{10m

-'

Ir-

I--+--+--+-_·'+'tf':...-....t-_--+---+l--i--i~
50ns/em

4-37

APPLICATIONS

•

earlier, the 524 includes a feedback element for the amplifier
which matches and tracks the channel "ON" resistance.

Often it is desirable to buffer the H1-524 output, to avoid
loading errors due to the channel "0 N" resistance:
HI-524
12

CHI

•

All HI-524 package pins labeled 'SIG GNO' (pins 3, 4, 6, 13,
15) should be externally connected to signal ground for best
Crosstalk performance.

HA-5190
14

CH2

~

"\'7 7

.~

7511

~

~
7511

, proW'' ' "
18

7511-

CH4

Note that the on-chip feedback element between pins 16 and 18
includes two switches in series, to simulate a channel resistance.
These switches open for VEN =Low. This allows two or more
HI-524's to operate into one HA-5190, with their feedback
elements connected in parallel. Thus, only the selected multiplexer provides feedback, and the amplifier remains stable.

-

7511

CH3

•

5

-

--

~

OUTPUT

;=f0 -

16

-

•

"Ii 7
o APPROXIMATELY 10pF SHOULD REMOVE ANY LOW LEVEL

INSTABILITY AT THE OUTPUT.

•

II

4-38

The main requirement for the buffer amplifier is a full power
bandwidth high enough to avoid attenuation of the video
signal. The HARRIS HA-5190 is well suited for this purpose;
in fact the H1-524 was designed to be compatible with the
5190. This 524/5190 combination offers a 3dB bandwidth of
at least 20MHz for a 3V peak-to-peak input. As mentioned

•

Bypass capacitors (0.1 to 1.0JlF) are recommended from each
HI-524 supply pin to power ground (pins 1 and 17 to pin 8).
Locate the buffer amplifier near the H1-524 so the two capacitors may bypass both devices.
If an analog input 1V or greater is present when supplies are
off, a low resistance is seen from that input to a supply line.
(For example, the resistance is approximately 160n for an
input of -3V.) Current flow may be blocked by a diode in
each supply line, or limited by a resistor in series with each
channel. The best solution, of course, is to arrange that no
digital or analog inputs are present when the power supplies
are off.

HI-539
Monolithic, Four Channel,
low level, Differential Multiplexer
FEATURES
•

DESCRIPTION

DIFFERENTIAL PERFORMANCE, TYP.:
• LOW ARON, +125 0 C
• LOW AID(ON),+125 0 C
• LOW A(CHARGE INJECTION)
• LOW CROSSTALK

5.5.Q
0.6nA
O.lpC
-120dB
900ns

•

SETTLING TIME, ±.0.01%

•

WIOE SUPPLY RANGE

•

BREAK-BEFORE-MAKE SWITCHING

•

NO LATCH-UP

±5VTO±18V

The Harris H1-539 is a monolithic, four channel, differential multiplexer.
Two digital inputs are provided for channel selection, plus an Enable input
to disconnect all channels.
Performance is guaranteed for each channel over the range ± 1OV, but is optimized for low level differential signals. Leakage current, for example, which
varies slightly with input Voltage, has its distribution centered at zero for
zero input volts.
In most monolithic multiplexers, the net differential offset due to thermal
effects becomes significant for low level signals. This problem is minimized
in the H1-539 by symmetrical placement of critical circuitry with respect
to the few heat producing devices.

APPlICA TlONS

I

II

The H1-539 will be offered in both commercial and military temperature
ranges, with screening available for MIL-STD-883, Class B. Supply voltages
are ± 15V and power consumption is only 2.5mW. The package is a 16 pin
ceramic DIP.

• LOW LEVEL DATA ACQUISITION

I

• PRECISION INSTRUMENTATION
• TEST SYSTEMS

PINOUT

FUNCTIONAL DIAGRAM
8action 11 for Packaging

TOPVIEW
AO
EN

Al
2

15

GND

r------,

l

IN lA

AO

DIGITAL
ADDRESS

OUTA
ITO 3
OTHER
SWITCHES)

Al

-Vps

3

14

+Vps

INIA

4

13

INIB

OUTB
ITO 3

IN2A

5

12

IN2B

SWITCHES)

IN3A

6

11

IN3B

IN lB

10

IN4B

OTHER

IN4A
OUTA

8

9

OUT B

EN

IN4A
IN4B

)

L ____ J

ADDRESS INPUT
BUFFER AND
LEVEL SHIFTER

DECODERS

- -----

MULTIPLEX
SWITCH PAIRS

4-39

SPECIFICA TIONS
ABSOLUTE MAXIMUM RATINGS
Voltage Between Supply Pins (Vps+, Vps -)

40V

Voltage from either Supply to Ground

20V

Analog Input Voltage, Vs

Vps- ~ Vs ~ Vps+

Digital Input Voltage, VA

Vps-~VA~Vps+

Storage Temperature Range

Internal Power Dissipation (Derate
BmW/oC above +750C ambient!
Operating Temperature Range
H1-539-2,-8
HI-539-4
HI-539-5

-65 0C to +150 0C

ELECTRICAL CHARACTERISTICS

-55 0C to +125 0C
-25 0C to +85 0C
OOC to +750C

(Unless otherwise specified) Supplies =±'15V, VEN =+4.0V,
VAH (Logic Level High) = +4.0V, VAL (Logic Level Low) = +O.BV.
See the Performance Characteristics Section for test circuits and conditions.
Selected parameters are defined in the Definitions Section.
H1-539-2.-8

PARAMETER

725mW

TEMP

TYP

MAX (MIN)

HI-539-4. -5
TYP

MAX (MIN)

UNITS

ANALOGCHANNELCHARA~

(-10)/+10

(-101/+10

V

RON. On Resistance VIN = OV
VIN=±10V
VIN = OV
VIN=±10V

+25 0C
+250C
Full
Full

650
700
950
1.1k

850
. 900
1.3K
1.4k

650
700
800
900

850
900
lK
1.lk

n
n
n
n

LI. RON ISide A - Side BI
VIN = OV
VIN =± 10V
VIN = OV
VIN=±10V

+250C
+25 0C
Full
Full

4.0
4.5
4.75
5.5

24
27
28
33

4.0
4.5
4.0
4:5

24
27
24
27

n
n
n
n

30
100
0.2
0.5

200

pA
pA
nA
nA

3
10
0.02
0.05

100

30
100
0.2
0.5

200

3
10
0.02
0.05

100

50
150
0.5
0.8

200

100
0.5
0.8

pA
pA
nA
nA

0.04
1.0

/-IV
/-IV

VS. Analog Signal Range

Full

;

IS(OFF). Off Input Leakage Current
(Note 1)
Condition OV

Condition ± 10V
Condition OV

Condition ±lOV

i

+25 0C
+25 0C
Full
Full

30
100
2
5

200

+25 0C
+25 0C
Full
Full

3
10
0.2
0.5

100

+25 0C
+25 0 C
Full
Full

30
100
2
5

200

+25 0 C
+25 0 C
Full
Full

3
10
0.2
0.5

100

+250C
+25 0C
Full
Full

50
150
5
6

200

+25 0 C
+25 0C
Full
Full

10
30
0.5
0.6

100
5
6

10
30
0.05
0.08

+25 0C
Full

0.02
0.70

0.04
10

0.D2
0.08

10
25

1
2.5

Ll.IS(OFF). [Side A - Side BI
Condition OV

Condition ~ 10V
Condition OV

Condition ~ 10V

2
5

0.2
0.5

pA
pA
nA
nA

10(OFF). Off Output Leakage Current
(Not. 1)
Condition OV

Condition t 10V
Condition OV

Condition ± 10V

LI. ID(OFF). [Sid. A - Sid. BI
Condition OV
Condition ± 10V
Condition OV

Condition ± 1OV
IO(ON). On Channel Leakag. Current
(Not. 1)
Condition OV
Condition ± 10V
Condition OV
ConditIOn 1: lOV

Ll.IO(ON) [Sid.A-Sid.BI
Condition OV
Condition:!:' lOV

Condition OV
Condition ± 10V
Ll.VOS. Differ.ntial Offset Voltage

4-40

10
25

2
5

25
40

1
2.5

0.2
0.5

2.5
4.0

pA
pA
nA
nA
pA
pA
nA
nA

pA
pA
nA
nA

SPECIFICATIONS (Continued)

HI-53S-4, -5

HI-53S-2, -8
TEMP

PARAMETER

TYP

MAX (MIN)

TYP

MAX (MIN)

UNITS

DIGITAL INPUT CHARACTERISTICS
VAL, Input Low Threshold

Full

0.8

0.8

V

VAH, Input High Threshold

Full

(4.0)

(4.0)

V

IAH, Input Leakage Current (High)

Full

1

1

I1A

IAL,lnput Leakage Current (Low)

Full

1

1

I1A

SWITCHING CHARACTERISTICS

TA, Access Time

+25 0 C
Full

250
450

750
1,000

250
450

750
1,000

ns
ns

Topen, Break-Before-Make Delay

+25 0C
Full

85

(30)
(30)

85

(30)
(30)

ns
os

TON(EN), Enable Delay On

+250C
Full

250

750
1,000

250

750
1,000

os
os

TOFF(EN), Enable Delay Off

+250C
Full

160

650

160

650
SOO

ns
ns

Settling Time, to i 0.01%

+25 0C

O.S

0.9

I1 s

Charge Injection (Output)

Fuli

3

3

pC

11 Charge Injection (Output)

Full

0.1

0.1

pC

Charge Injection (Input)

Full

10

10

pC

Differential Crosstalk (Note 3)

+250C

124

124

dB

Single Ended Crostalk (Note 3)

sao

+250C

100

100

dB

CS(OFF), Channel Input Capacitance

Full

5

5

pF

CO(OFF), Channel Output Capacitance

Full

7

7

pF

CO(ON), Channel On Output Capacitance

Full

17

17

pF

COS, Input to Output Capacitance (Note 4)

Full

0.08

0.08

pF

CA, Oigitallnput Capacitance

Full

3

3

pF

+25 0 C
Full

2.5

+25 0C
Full

0.150

+25 0C
Full

0.001

Full

i 15

II

POWER REQUIREMENTS

PO. Power Dissipation
1+ Current
1- Current

i V,Supply Voltage Range

45

mW
mW

2.0

mA
mA

1.0

rnA
rnA

(t 5)/ t 18

V

2.5
45
0.150
2.0
0.001
1.0
(i5)/ i IS

i 15

NOTES
1. See Test Circuits #2, 3, 4. The condition ±'lOV means:

IS(OFF) and IO(OFF): (VS =+IOV, Vo =-10V), then
(VS = -10V, Vo = +lOV)
IO(ON):
(+10V, then -10V)
2. 11 Vas (Exclusive of thermocouple effects) =
RON 11101ON) + IO(ON) l1~ON.

See Applications section for discussion of additional
error.

Vas

3. VI N = 1kHz, 15V p_p on all butthe selected channel. See
Test Circuit .:ti9.

4. Calculated from typical Smgle-Ended Crosstalk performance.

4-41

PERFORMANCE CHARACTERISTICS AND TEST CIRCUITS
(UNLESS OTHERWISE SPECIFIED TA = 250 C, VSUPPLY=! 15V, VAH = +4V AND VAL = +O.8V)
ON RESISTANCE vs.
TEMPERATURE

ON RESISTANCE MEASUREMENT
100pA

TEST CIRCUIT
NO.1

soo

(VIN" 0 VOL Tst

OUT

HI-539

o

+2&

-tiiO

+75.100

TEMPERATURE oC

ON RESISTANCE ¥s.
ANALOG INPUT VOLTAGE

.00

NORMALIZED ON RESISTANCE
vs. SUPPLY VOLTAGE
2.0
IS

TA".,26o(:

600

-10 -8

•

-4 -2
0
2
4 6
ANALOG INPUT, VIN (VOLTS)

8

...fI

10

12
:1:7

±9
±11
t13
1:.15
SUPPLY VOLTAGE (VOLTS)

1:.17

LEAKAGE CURRENT

LEAKAGE CURRENT
vs. TEMPERATURE

TEST
CIRCUIT
NO. 2*

±10V-=-

1.

''''.

(Similar connections for side US")

'/
IOIIO~
"~A

/

~

V1O(OFF''''S(OFFI

50

7'&

100

125

TEST
CIRCUIT
NO.3*

+O.8V

TEMPERATUflE OC

(Similar connections for Side "S")

·Th.... measu ... ments = +10V/-1OV,
-10V/+10V, and OV

TEST
CIRCUIT
NO. 4*
_

..V

f

(Similar connections for side "B"l

4-42

±10V

TEST CIRCUITS (Continued)
TEST CIRCUIT
NO.5

~~ :::~'--~
2601

~,

)!.;151+10V

SUPPLY CURRENT ¥s.
TOGGLE FREQUENCY

320

~+ISUPPLY

.-------+"'v,.,

1

A,

IN1A~+10/+5V

HI-S39

,---_.---+---i AD

'~
JL

_ _ _ _ _ _ _ _ _ __

son

240

..:

... 220
-{ , :

2003~~4~~5~~6~~7~~8--~9--1~0~1~1--1~2~1~3--14--~15~
VA

VAH - LOGIC LEVEL (HIGHI. VOLTS

IN2A 1----0--,
IN3A
IN4A

~

-=

~ -101-SV

,::-LE_N_i"~i'N::.O--O-~U-.~T/-', ,.~:n

VAL=OV

Q_4PF

_

50% DUTY CYCLE

-lS/-10V

(SIMILAR CONNECTIONS FOR "B" SIDEI

TEST CIRCUIT
NO.6·
ACCESS TIME VS.
LOGIC LEVEL (HIGH)

•

14r------r------r------.------~--r__,

(FUNCTIONAL LIMIT) -

12r-----~-----+------~----~--+_~/

~~10r------r------+------+------+---hV~
/
w

VS~PPl y =

! BI----t---t-----t---+--""7od1-l/--+I
,

~

VSUPPLyl=±lo---....--...L!
4r-----_r------+-----_+------~/~-r--4
2r-----t-----~----_r

__ h

AI

INIA i+-Q±10V

AD

IN2A.
IN3A

HI-s39

~ 6~-----+------~------~------~f_~_+

~

V+

r

±15

1kHz

-=

- +~

r_~R~~,

EN

~Lt--~~

10kHz
100kHz
TOGGLE FREQUENCY, Hz

±

IN4A f-oil0V

SOl!

~

100Hz

,.,.

lMHz 3MHz 10MHz

OUTA

GND

v-

i-

b

10Mn

I

~~

I
I
I
I

-15V

14pF

L

)

I
I
I
I

I
_ : __ -'

(SIMILAR CONNECTIONS FOR "B" SIDEI

,

ACCESS TIME

VAH = 4V

~~~:EE~~AI

~ U:~: :"OV
~
-~

112VAH

+~

I
I

I

r---r- VA INPUT

Y

!

l

'DIV .

OUTPUT

I:~
I
-10V
I

----.1

tA

1
1_
SOON

J

200ns/DIV.

4-43

TEST CIRCUITS (Continued)
TEST CIRCUIT
NO.7
ENABLE DRIVE

BREAK-BEFORE-MAKE DELAY (tOPEN)

+15V

I

VAH=4V

'5V

"ADDRESS

VA~

~VEIVAI

~
60%
, , 60%

OUWUTA

A1

50H

I - r-

VA INPUT

iVID1V.

,

S,ON

HI-539

AD

VOUT

->I 10ItoPENI

840N
OUTPUT

'[IDT -

I

IV

12.5pF

~ t-

-15V

100nsIDIV.

ISIMILAR CONNECTION FOR "0" SIDE)

TEST CIRCUIT
NO.8
ENABLE DRIVE

•

ENABLE DELAY ItON(EN). tOFF(EN))

1 1

VAH"'4V

r-

1f2V

I

I

VAL"OV

I

t()N!EN) ---1>\
I

I

I

I

I

DRIVE
2V/DIV.

11
ill
OFtl

:
~
I
90%

ENABLE

OUTlIUTA

9'"

S,ON

OU~UT 1

82 THRU 54

I+- I tOFF I
I --+\ lEN) 1 -

2V/DIV.

,

I II

\

11

-15V

lOOns/DIV.

(SIMILAR CONNECTION FOR

"au SIDE)

TEST CIRCUIT
NO.9
SINGLE-ENDED CROSSTALK

DIFFERENTIAL CROSSTALK

INSTRUMENTATION

INSTRUMENTATION

AMpLIFIER·

AMPLIFIER'""

mV p _p

r
... AD606 OR 883630, FOR EXAMPLE

4-44

mVp_p

I

DEFINITIONS
CHARGE INJECTION - Charge (in pC) transferred, during a
transition between channels, through the internal gate-tochannel capacitance. The resulting voltage error varies inversely with the output (or input) capacitance.
CROSSTALK - Signal at the multiplexer output, coupling
though the CDS capacitance of an OFF channel. Amplitude
is proportional to source resistance for the ON channel. See
Test Circuit # 9 for single-ended and differential versions
of crosstal k.

DIFFERENTIAL OFFSET VOLTAGE ( .:l VOS) - Voltage
between the multiplexer output terminals with both channel
input terminals shorted to ground.
DIFFERENTIAL DN RESISTANCE (LlRON) - The absolute
difference in On Resistance for the two sides of a channel.
INPUT TO OUTPUT CAPACITANCE (CDS) - Capacitance
from one input terminal of a channel to the corresponding
output of the multiplexer. This parameter is responsible
for Crosstalk.

DIFFERENTIAL LEAKAGE CURRENT ( 6. IS(OFF),
.:lIO(DFF), .:lIO(ON)) - The absolute difference in leakage
for the two sides of a channel.

APPLICATIONS
GENERAL

The HI-539 accepts inputs in the range -15V to +15V, with
performance guaranteed over the ±10V range. At these higher
levels of analog input voltage it is comparable to the HI-509,
and is plug-in compatible with that device (as well as the
HI-509A). However, as mentioned earlier, the HI-539 was
designed to introduce minimum error when switching low level
inputs.
Special care is required in working with these low level signals.
The main concern with signals below 100mV is that noise,
offset voltage, and other aberrations can represent a large
percentage error. A shielded, differential signal path is essential, especially to maintain a noise level below 50 /J.Vrms.
LOW LEVEL SIGNAL TRANSMISSION

The transmission cable carrying the transducer signal is critical
in a low level system. It should be as short as practical and
rigidly supported. Signal conductors should be tightly twisted
for minimum enclosed area, to guard against pickUp of electromagnetic interference, and the twisted pair should be shielded

against capacitively coupled (electrostatic) interference.
A braided wire shield may be satisfactory, but a lapped foil
shield is better since it allows only one tenth as much leakage
capacitance to ground per foot. A key requirement for the
transmission cable is that it presents a balanced line to sources
of noise interference. This means an equal series impedance
in each conductor plus an equally distributed impedance from
each conductor to ground. The result should be signals equal
in magnitude but opposite in phase at any transverse plane.
Noise will be coupled in phase to both conductors, and may
be rejected as common mode voltage by a differential amplifier
connected to the multiplexer output.

•

Coaxial cable is not suitable for low-level signals because the
two conductors (center and shield) are unbalanced. Also,'
ground loops are produced if the shield is grounded at both
ends by standard BNC connectors. If coax must be used, carry
the signal on the center conductors of two equal-length cables
whose shields are terminated only at the transducer end. As
a general rule, terminate (ground) the shield at one end only,
. preferably at the end with greatest noise interference. This is
usually the transducer end for both high and low level signals.

Table 1
IMPEDANCE
PER FOOT

WIRE
GAGE

EQUIVALENT
WIDTH OF P.C.
CONDUCTOR
(2 oz. Cu.)

D.C.
RESISTANCE
PER FOOT

INDUCTANCE
PER FOOT

AT 60Hz

AT 10kHz

18
20
22
24
26
28
30
32

0.47"
0.30"
0.19"
0.12"
0.075"
0.047"
0.029"
0.018"

0.0064n
0.0102n
0.0161n
0.0257n
0.041n
0.066n
0.105n
0.168n

0.36pH
0.37pH
0.37pH
0.40pH
0.42pH
0.45pH
0.49pH
0.53pH

0.0064n
0.0102n
0.0161n
0.0257n
0.041n
0.066n
0.105n
0.168n

0.0235n
0.0254n
0.0288n
0.0345n
0.0488n
0.0718n
0.110n
0.171n

4-45

APPLICATIONS (Continued)
WATCH SMALL Av ERRORS

Printed circuit traces and short lengths of wire can add substantial error to a signal even after it has traveled hundreds of
feet and arrived on a circuit board. Here, the small voltage
drops due to current flow through connections of a few
milliohms must be considered, especially to meet an accuracy
requirement of 12 bits or more.
Table I is a useful collection of data for calculating the effect
of these short connections. (Proximity to a ground plane will
lower the values of inductance.)
As an example, suppose the HI-S39 is feeding a 12 bit converter system with an allowable error of±1/2 LSB (±1.22mV).
If the interface logic draws IOOmA from the SV supply, this
current will produce 1.28mV across 6 inches of #24 wire;
more than the error budget. Obviously, this digital current
must not be routed through any portion of the analog ground
return network.
PROVIDE PATH FOR IBIAS

The input bias current for any DC-coupled amplifier must have
an external path back to the amplifier's power supply. No
such path exists in Figure lA, and consequently the amplifer
output will remain in saturation.
A single large resistor (1M.I1 to IOM.I1) from either signal line
to power supply common will provide the required path,
but a resistor on each line is necessary to preserve accuracy.
A single pair of these bias current resistors on the HI-S39
output may be used if their loading effect can be tolerated
(each forms a voltage divider with RON). Otherwise, a resistor
pair on each input channel of the multiplexer is required.

4-46

The use of bias current resistors is acceptable only if one is
confident that the sum of signal plus common-mode voltage
will remain within the input range ofthe multiplexer/amplifier
combination.
Another solution is to simply run a third wire from the low
side of the signal source, as in Figure lB. This wire assures a
low common-mode voltage as well as providing the path for
bias currents. Making the connection near the multiplexer
will save wire, but it will also unbalance the line and reduce
the amplifier's common-mode rejection.
DIFFERENTIAL OFFSET, AVOS

There are two major sources of AVOS. That part, due to the
expression (RON .610(ON) + IO(ON) .6RON) becomes significant with increasing temperature, as shown in the Electrical
Characteristics section. The other source of offset is the
thermocouple effects due to dissimilar materials in the signal
path. These include silicon, aluminum, tin, nickel-iron and
(often) gold, just to exit the package.
For the. thermocouple effects in the package alone, the constraint on .6 VOS may be stated in terms of a limit on the
difference in temperature for package pins leading to any
channel of the H1-539. For example, a difference of O.13 0 C
produces a 511V offset. Obviously, this.6T effect can dominate the A VOS parameter at any temperature unless care is
taken in mounting the H1-539 package.
Temperature gradients across the HI-539 package should be
held to a minimum in critical applications. Locate the HI-S39
far from heat producing components, with any air currents
flowing lengthwise across the package.

APPlICA TIONS (Continued)

"FLOATING"
SOURCE

-v
Figure 1A

HI-539

+v

,,----/\

•

\
\ I ____ ...l
\I
1 TO 10M

I
<>
<>



~

I

~
V

POWER SUPPL Y
COMMON

POWER SUPPL Y
COMMON

Figure 18

The amplifier in Figure 1A is unusable because its bias currents cannot return to the power supply. Figure 1B
shows two alternative paths for these bias currents: either a pair of resistors, or (better) a third wire from the low
side of the signal source.

4-47

mHARRIS

H1-1818A/1828A

Low Resistance
8 Channel CMOS Analog Multiplexers
FEATURES

DESCRIPTION

• SIGNAL RANGE

±15V

• "ON" RESISTANCE (Typ.)

250n

•
•
•

INPUT LEAKAGEAT+125 0 C (TYP.)

20nA

ACCESS TIME (TYP.)

350ns

•
•

5mW

POWER CONSUMPTION (TYP.)
DTL/TTL COMPATIBLE ADDRESS
-55 0 C to +125 0 C OPERATION

APPlICA TIONS

•

•

DATA ACQUISITION SYSTEMS

•

PRECISION INSTRUMENTATION

•

DEMU LTIPLEXING

•

SELECTOR SWITCH

The 1818A is a single-ended 8 channel multiplexer, while the
HI-1828A is a differential 4 channel version. Either device
is ideally suited for medical instrumentation, telemetry systems,
and microprocessor based data acquisition systems.
The HI-1818A-2 and HI-1828A are specified over -55 0 C
to +125 0 C, while the -5 versions are specified over OOC to
+75 0 C.

FUNCTIONAL DIAGRAM

PINOUT
Section 11 for Packaging

HI-1818A
ADDRESSAI
+5.0V SUPPLY
ENABLE
ADDRESS A2
IN 8
·IN 7
IN 6
IN 5

The HI-1818A/1828A are monolithic high performance CMOS
analog multiplexers offering built-in channel selection decoding
plus an inhibit (enable) input for disabling all channels.
Dielectric Isolation (01) processing is used for enhanced
reliability and performance (see Application Note 521).
Substrate leakage and parasitic capacitance are much lower,
resulting in extremely low static errors and high throughput
rates. Low output leakage (typically O.lnA) and low channel
ON resistance (250 n) assure optimum performance in low level
or current mode applications.

Top View

2
3
4
5
6
7
8

DIGITAL ADDRESS

16
15
14
13
12
11
10

ADDRESS AO
-15VSUPPLY
+15V SUPPLY
INI
OUT
IN2
IN 3

9

IN 4

Section 11 for Packaging

HI-1828A

HI-1818A

AODRESS{
INPUT
BUFFERS

OUT

'N'

HI-1828A

Top View
ADDRESSAI
+5.0V SUPPLY
ENABLE
OUT5THRU8
IN 8
IN 7
IN 6
IN 5

4-48

2
4
5
6
7
8

16
15
14
13
12
11
10

ADDRESSAO
-15V SUPPLY
+15VSUPPLY
IN 1
OUT 1 THRU 4
IN 2
IN 3
9 IN 4

'"

ADDRESS {
.NPUT
BUFFERS

SPECIFICATIONS

I

ABSOLUTE MAXIMUM RATINGS (NOTE 1)
4D.DV
3D.DV

Supply Voltage Between Pins 14 and 15
Logic Supply Voltage, Pin 2
Analog Input Voltage: VSuppl y +2V

Digital Input Voltage
Total Power Oissipation (Note 2)
Storage Temperature Range

V-Supply to V+ Supply

780mW
-65 0 C to +150 oC

VSupply -2V

ELECTRICAL CHARACTERISTICS
Supplies =+15V. -15V. +5V
PARAMETER
ANALOG CHANNEL CHARACTERISTICS
··VIN. Analog Signal Range
··RON. ON Resistance (Note 3)

*IS(OFF).lnput Leakage Current
"IDWN). On Channel Leakage Current
(HI-1818A)
(RH828A)
*ID(OFF) Output Leakage Current
(HI-1818A)
(HI-1828A)
DIGITAL INPUT CHARACTERISTICS
VAL. Input Low Threshold
VAH • Input High Threshold (Note 4)
IA. ,Input Leakage Current

SWITCHING CHARACTERISTICS
TS. Access Time (Note 5)
Break-Before-Make Delay
Settling Time (0.1%)
(0.025%)
CIN. Channel Input Capacitance
COUTo Channel Output Capacitance
(HI-1818A)
(HI-1828A)
CDsIOFF). Drain-To-Source Capacitance
Co, Digital Input Capacitance

HI-1818A-211828A-2
-55 0 C to +125 0 C
TEMP.

MIN.

Full
+250 C
Full

-15

HI-1818A-5/1828A-5
oOc to +75 0 C

TYP.

MAX.

MIN.

+15
400
500

-15

250
300

Full

20

Full
Full
Full
Full

Full
Full
Full

TRUTH TABLES

TYP.

MAX.

UNITS

250
300

+15
400
500

no
no

50

20

50

nA

100
50

250
125

100
50

250
125

nA
nA

100
50

250
125

100
50

250
125

nA
nA

0.4

V
V

1

Il A

0.4
4.0

4.0
.01

1

.01

V

+250 C
+25 0 C
+250 C
+25 0 C
+250 C

350
100
1.08
2.8
4

350
100
1.08
2.8
4

ns
ns
IlS
Il S
pF

+250 C
+25 0 C
+250 C
+250 C

20
10
0.6
5

20
10
0.6
5

pF
pF
pF
pF

PDS. Standby Power (Note 6)
* 1+. Current Pin 14
* L, Current Pin 15

Full
Full
Full
Full
Full

5
5
0.1
0.3
0.3

5
5
0.1
0.3
0.3

mW
mW
mA
mA
mA

* I L. Current Pin 2
NOTES:

.

A2
L
L
L
L
H
H
H
H
X

ADDRESS
Al
AO
L
L
H
L
H
L
H
H
L
L
H
L
H
L
H
H
X
X

"ON"
CHANNEL
I
2
3
4
5
6
7
8
NONE

EN
L
L
L
L
L
L
L
L

H

HI-1828A

POWER REQUIREMENTS
Po, Power Dissipation

HI-1818A

1. Voltage ratings apply when voltages at all other pins are
within their normal operating ranges.
2. Derate 9.25 mW/oC above 750 C.
3. VOUT =± 10V lOUT =- lmA.

0.5
1
1

1
2
2

ADDRESS
EN
Al
AO
L
L
L
L
H
L
L
H
L
H
H
L
X
X
H

"ON"
CHANNELS
I and 5
2 and 6
3 and 7
.4 and 8
NONE

4. To drive from DTL/TTL circuits. 1K pull-up resistors
to + 5.0V supply are recommended.
5. Time measured to 90% of final output level;
VOUT =- 5.0V to +5.0V. Digital Inputs =OV to + 4.0V.
6. Voltage at Pin 3. ENABLE =+ 4.0V.

100% Tested for Dash 8 at +250 C and +125 0 C Only .

f

4-49

•

I

I

PERFORMANCE CHARACTERISTICS
ON CHANNEL CURRENT
vs VOLTAGE

ON RESISTANCE vs
ANALOG SIGNAL LEVEL

. --

1 rnA

.

V2

I'''~

,;y~
-=-

tVl
IN

OUT

Test Circuit
v2

-

RON = 1iiiA

+60

Test Circuit

'" 300
::;;
:I:

0
, 250
w

u

z
~

200

~

150

~

enw

~

0
100
-10

•

-55°C

..: +40

350

~I--:;:::.

::;;

,

k

k;;; i===t-+125 C
0

~ +20
w
a:
a:

:J

0

~

"z"
5 -20

----

~

-55~

~

--6

-2
+2
+4
-4
0
VI - SIGNAL LEVEL (VOLTS)

+6

+8

+12~

-60~
-8

--6

f{J1"
!10V

L

.....l-o
AD

~

I

+6

EN

INI

-5VOC

AO

A lolONI

f

OUT

IN2

Al

A2

SCOPE

EN

l!

±'OV

O.4V

+4V~
OV

_po._. .

"TwDm.... ",mlnllp.ch_l:
+tov/.tOV
and -'OVI+1OV f1>rIDIOffl
IT......... _ ..

:

":'" J.

EN
A,

bb

+10V~

-,,~

."

-,0

-=-:j:.1OV

±10V-=-

+4

ACCESS TIME

+5VOC

.t=~

A lotOFFj

-=~

+2

0

VOLTAGE ACROSS SWITCH

ON LEAKAGE

OUT

!

-2

-4

+10

LEAKAGE CURRENTS vs TEMPERATURE
OFF LEAKAGE

V

+250 C

-40

-10

-8

~

+25OC~

./

~

+tOY/·tOY _

4V

·1OV/+1OVJ

+10V

VAH =4V

-

lDOnA

'o{ONI'"'D(OFFl
lDnA

HI-1818A
HI-1828A

./

+5V

/

~

's(OFFI
(HI-1818A/1S28AI

V/ V

r-

TA

-4vl-

OUTPUT

iV/~r
-5V

100ns/DIV.
lOpA

2S

50

7'
TEMPER AT URE _0 C

4-50

J

AOINPUT_
~
2V/DIV.

/ //

\V./ ./

lnA

l00pA

/

I

I

f-VAH/2

100

.2.

7

7

+8

+10

SCHEMA TIC DIAGRAM
ADDRESS INPUT BUFFER

H-t----A
ALL N-CHANNEL
BOOIESTOVALL P-CHANNEL
BODIES TO V+
UNLESS OTHERWISE
INDICATED.

'--1---+-+--+---+ A

DECODER GATE

:----------,

i

EN

•

I

I

A2 OR A2

I

TO!
P CHANNEL
SW II

Al0RAl

P16 TO

I

N CHANNEL
N16
I

SW!

I
I

~ ~WIT~~~!:.-._ ~

A2 OR A2 NOT USED
FOR HI-1828A

MULTIPLEX SWITCH
FROM DECODE

-v

FROM DECODE

4-51

I

•

.....

Data Conversion Products
ILIIJ1
....................................

HA-2420/2425
HD-0165
HI-562A
HI-561O
HI-5618A/5618B
H 1-5712/5712A
HI-5900
HI-5901
HI-7541
HI-DAC 801

Fast Sample and Hold
Keyboard Encoder
12 Bit High Speed Monolithic Digital-to-Analog Converter
10 Bit High Speed Monolithic Digital-to-Analog Converter
8 Bit High Speed Digital-to-Analog Converters
High Performance 12 Bit Analog-to-Digital Converter
Analog Data Acquisition Signal Processor
Analog Data Acquisition Signal Processor
12 Bit Multiplying Monolithic Digital-to-Analog Converter
12 Bit High Speed Monolithic Digital-to-Analog Converter

5-2
5-9
5-12
5-17
5-23
5-30
5-39
5-44
5-50
5-57

High Speed Precision Monolithic Sample and Hold Amplifier
High Speed Monolithic Digital-to-Analog Converter with Reference
Fast, Complete 12 Bit A/D Converter with Microprocessor Interface
High Speed Monolithic Digital-to-Analog Converter
12 Bit Low Cost Monolithic D/A Converter
High Performance Monolithic 12 Bit D/A Converter
WideTemperature Range Monolithic 12 Bit D/A Converter
16 Bit D/A Converter

5-62
5-63
5-64
5-65
5-66
5-68
5-70

Advance
HA-5320
HI-565A
HI-574A
HI-5660
HI-5680
HI-5685
HI-5687
HI-DAC16B/
DAC16C

II

5-72

ABSOLUTE MAXIMUM RATINGS

As with al/ semiconductors, stresses listed under "Absolute Maximum Ratings" may
be applied to devices (one at a time) without resulting in permanent damage. This
is a stress rating only. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. The conditions listed under "Electrical
Characteristics" are the only conditions recommended for satisfactory operation.

5-1

m~RIS

HA-2420/2425
Fast Sample and Hold

FEATURES

DESCRIPTION

• LOW OROOP RATE (CH

=1000pF)

The HA-2420/2425 is a monolithic circuit consisting of a high
performance operational amplifier with its output in series with
an ultra-low leakage analog switch and a MOSFET input unity
gain amplifier.

5J.1V/ms

• LOW CHARGE TRANSFER

5pC

• FAST ACQUISITION TIME (10V STEP TO .01%)

5J.1S

With an external holding capacitor connected to the switch
output, a versatile, high performance sample-and-hold or
track-and-hold circuit is formed. When the switch is closed,
the device behaves as an operational amplifier, and any of the
standard op amp feedback networks may be connected around
the device to control gain, frequency response, etc. When the
switch is opened the output will remain at its last level.

7V//J.s

• HIGH SLEW RATE

2.5MHz

• BANDWIDTH

30ns

• LOW APERTURE TIME
• TTl COMPATIBLE CONTRULINPUT

Performance as a sample-and-hold compares very favorably
with other monolithic, hybrid, modular, and discrete circuits.
Accuracy to better than 0.01% is achievable over the temperature range. Fast acquisition is coupled with superior droop
characteristics, even at high temperatures. High slew rate,
wide bandwidth, and low acquisition time produce excellent
dynamic characteristics. The ability to operate at gains greater
than 1 frequently eliminates the need for external scaling
amplifiers.

APPlICA TlONS
• A TO 0 CONVERSION SYSTEMS
• 0 TO A DEGLITCHER
• AUTO ZERO SYSTEMS

The device may also be used as a versatile operational amplifier
with a gated output for applications such as analog switches,
peak holding circuits, etc.

• PEAK DETECTOR
• GATED OP AMP

PINOUT

FUNCTIONAL DIAGRAM
Section 11 for Packaging

TOP VIEW
SAMPLE/HOLD

CONTROL

INDEX
CORNER

'"

OFFSET
AOJ
-fIN

OFFSET _:::14
ADJUST

OFFSET
ADJ.
OFFSET

HOLD
CAP.

ADJ.

NC

~j

U
2

20
U
1
"

:::]5

CAP

:.::J7

15[:.: Ne
10

'-1

11

n

Ne OUTPUT Ne

5-2

,"'-

12

d4 ::::

:1

1"1

NC

V+

-----,

c- _ Ne

ISC. HOLD

1'1

14 PIN 011'

u

19 15

17L-- : NC

v- :':::J8 9

HOLD
CAP.

S/H
-IN Ne CONTRl GND

OFFSET ::""J6
ADJUST
Ne

SAMPLEI
HOLD
CONTROL

NC

LEAD LESS CHIP CARRIER
(LCC) PACKAGE

~----~~--~~+

I
lOUT

L-l----t--/l:---J
C
HIGH
GAIN
AMP

LOW
LEAKAGE
SWITCH

HIGH
IMPEDANCE
MOSFET
FOLLOWER

. SPECIFICA TIONS
ABSOLUTE MAXIMUM RATINGS
Voltage Between V+ and V- Terminals
40V
Differential Input Voltage
*24V
Digital Input Voltage (Pin 14)
+BV,-15V
Output Current
Short Circuit Protected
300mW (Note 7)
Internal Power Dissipation

Dperating Temperature Range
HA-2420-2/B
HA-2425-5
Storage Temperature Range

-55 0C ~ TA ~+1250C
ODC~ TA ~+750C
-650C~ TA ~+150oC

ELECTRICAL CHARACTERISTICS Test Conditions (Unless otherwise specified) VSUPPLY =±15.0V; CH = 1000pF;
Digital Input (Pin 14), VIL = +O.BV (Sample), VIH = +2.0V (Hold)

PARAMETER
INPUT CHARACTERISTICS
'Offset Voltage
"Bias Current
'Offset Current
Input Resistance
Common Mode Range
TRANSFER CHARACTERISTICS
'Large Si~nal Voltage Gain (Note 1,4)
"Common Mode Rejection (Note 2)
Hold Mode Feedthrough Attenuation (Note 9)
Gain Bandwidth Product (Note 31
OUTPUT CHARACTERISTICS
"Output Voltage Swing (Note 1)
Output Current
Full Power Bandwidth (Note 3, 4)
Output Resistance (D.C.)
TRANSIENT RESPONSE
Rise Time (Note 3, 5)
Overshoot (Note 3, 5)
Slew Rate (Nole 3, 61
DIGITAL INPUT CHARACTERISTICS
Digital Input Current (VIN = OV)
Digital Input Current (VIN = +5.0V)
Digital Input Voltage (Low)
Digital Input Voltage (High)
SAMPLE/HOLD CHARACTERISTICS
Acquisition Time to .1% 10V Step (Note 3)
Acquisition Time to .01% 10V Step (Note 3)
Aperture Time
Aperture Delay Time
Aperture Uncertainty Time
"Drift Current (Note 3, 8)
"Charge Transfer (Note 8)
POWER SUPPL Y CHARACTERISTICS
"Supply Current (+)
'Supply Current (-)
"Power Supply Rejection
NOTES:

1.
2.
3.
4.
5.

TEMP
+25 0C
Full
+25 0C
Full
+25 0C
Full
+25 0C
Full

MIN

HA-2420-2
TYP
MAX
2
3
40
10

MIN

HA-2425-5
TYP
MAX

4
6
200
400
50
100

3
4
40
10

5
±1O

10

5
±10

10

Full
Full
Full
+25 0C

25K
80

50K
90
-76
2.5

25K
74

50K
90
-76
2.5

Full
+25 0C
+25 0C
+250C

*10
±15

+25 0C
+250C
+25 0C
Full
Full
Full
Full

100
.15

100
.15

50
25
7

50
25
7

2.0
4
5
30
50
5
5
0.5
5

+25 0C
+250C
Full

3.5
2.5
90

RL=2kn
VCM = ±lOVDC
AV = +1, RL = 2kn, CL = 50pF
VOUT = 20V peak-to-peak
VOUT = 400mV peak-to-peak

n
ns
%
V/p.s
0.8
20
0.8

4
5
30
50
5
5
0.5
5

50
4.0
10
5.5
3.5
74

6. VOUT = 10.0V peak-la-peak
7. Derate Power Dissipation by
4.3mW/oC above +1050 C

3.5
2.5
90

•

V
mA
kHz

2.0

+25 0C
+250C
+250C
+250C
+250C
+25 0C
Full
+250C

mV
mV
nA
nA
nA
nA
Mn
V
V/V
dB
dB
MHz

±10
±15

0.8
20
0.8

80

6
8
200
400
50
100

UNITS

50
1.0
10
5.5
3.5

mA
p.A

V
V
p.s
p.s
ns
ns
ns
pA
nA
pC
mA
mA
dB

8. VI N = OV
9. fiN ~ 100kHz

Ambient Temperature

'100% Tested for DASH 8

5-3

PERFORMANCE CURVES
VSUPPl Y = ±15VOC, TA = +25 0 C, CH = 1,OOOpF Unless Otherwise Specified

TYPICAL SAMPLE AND HOLD PERFORMANCE
AS A FUNCTION OF HOLDING CAPACITOR

1000

~DRIFT DURING HOLD@

r

250C MILLIVOLTSISEC

"'

100

/

"

OUTPUT NOISE
"HOLD"MODE
100

SAMPLETOHQLD
OFFSET ERR OR
MILLIVOLTS

~

UNITYGAIN ~
BANDWIDTH:
MHz

e=

-""

~

~

10

"'

k::::f-"
EQUIV. INPUT NOISE
"SAMPLE" MODE 0
SOURCE RESISTANCE

"\
-A.

SLEW RATE/CHARGE
RATE: VOLTS/
MlfROSECON?

EQUIVALENT INPUT NOISE
"SAMPLE" MODE ·-100K
SOURCE RESISTANCE

f-

~

~

O. 1

/'

V

"'
r-

1000

L

UNITY GAIN PHASE
" ' MARGIN: DEGREES

10

1.0

BROADBAND NOISE CHARACTERISTICS

MINIMUM SAMPLE TIME
FOR 0.1% ACCURACY
10V SWINGS -~sec
~

1
10

100

..........

11 Hill III

lK
10K
lOOK
BANDWIDTH
(LOWER 3dB FREQUENCY = 10Hz)

1M

.0 1
10pF

100pF

l000pF
O.OI~F
CH VALUE

1.0~F

DRIFT CURRENT VS. TEMPERATURE

OPEN LOOP FREQUENCY RESPONSE

1000
100
. 90

...

L

II

L

100

80

2

70

w

50

~

V

40

>

0

30

0
0

20

2

/

w
0

i'..~

"- "-

~

,,~

-"-

'"" '"'"-""

60

"i'!....

..
....
..

/
10

ID

I
I

CH = 100pF

~:::::CH = 1000pF

.~

"' 1"-,,'\ \0..

CH =.OII1F

""- "
\."\..\
"'" "" .""

CH = 1.01lF

CH=O.II1F~

10

..........
..

0

r-~~

-10

-20

I--- ....-

v

~
~

-30

L

10

100

lK

10K

lOOK

1M

~

10M

100M

FREQUENCY, Hz

1
-50

-25

+25
+50
T(OC)

+75

+100

+125

OPEN LOOP PHASE RESPONSE
HOLD MODE FEED THROUGH ATTENUATION
CH= 1000PF
-30

-40

~ -50

V

is

~ -60

:::>

ffi
1=

-70

/

/

40

~
~..

60
80

"

100

w

120

~

hr

CH = 0~01!lF :
CH = l000pF

I

..... CH = 1.01lF

V / '"\

'< ~ ~r;; 100P

" ""

...........

........... ~/I / ,
I~
I--"""" '\
CH = 0.111~

""'~
\l

140
.. 160

-90

5-4

o
20

ffi

~

..: -80

100

:aw

§

180

ili

200

\I

I\,
\

~ 220
lK
10K
lOOK
1M
±10V SINUSOIDAL INPUT FREQUENCY (Hz)

10M

240
10

100

lK

10K
lOOK
FREQUENCY, Hz

1M

i

10M

100M

OFFSET AND GAIN ADJUSTMENT
PEDESTAL VS. INPUT VOLTAGE
PEDESTAL VOLTAGE
(MV)

10

GAIN ADJUSTMENT
6

4
D.C. INPUT
~~~~~~~~~~~VOLTAGE

(VOLTS)

....... CH = 0.1/lF,
1.0/lF

The linear variation in pedestal voltage with sample-and-hold
input voltage causes a -0.06% gain error (CH = 1000pF). In
some applications (O/A deglitcher, AID converter) the gain
error can be adjusted elsewhere in the system, while in
other applications it must be adjusted at the sample-andhold. The two circuits shown below demonstrate how to
adjust gain error at the sample-and-hold.

'CH = .01J1F

-10
-12

'CH

=1000pF

The recommended procedure for adjusting gain error is:

-14
-16
-18

1. Perform offset adjustment.

-20

'CH = 100pF

2. Apply the nominal input voltage that should produce

a +1OV output.
Figure 1

3. Adjust the trim pot for +10V output in the hold mode.

OFFSET ADJUSTMENT

4. Apply the nominal input voltage that should produce a
-10V output,

The offset voltage of the HA-242012425 may be adjusted
using a 100kn trim pot, as shown in Figure 6. The recommended adjustment procedure is:

5, Measure the output hold voltage (V-10 NOMINAL).
Adjust the trim pot for an output hold voltage of
\V-10 NOMINAL)+\-10V)

II

2
1. Apply zero volts to the sample-and-hold input, and a
square wave to the SIH control.
2. Adjust the trim pot for zero volts output in the hold
mode.
This procedure will alter the input VOS value so that it
cancels the pedestal voltage.
NONINVERTING CONFIGURATION
INVERTING CONFIGURATION
.002RF

+IN
-IN

HA-2420/2425
. S/H
CONTROL

RF
S/HCONTROL
INPUT

J1fL
GAIN

S/H CONTROL
INPUT

GAIN

Figure 2

~

1+\*

~ -=~
Figure 3

5-5

TEST CIRCUITS
CHARGE TRANSFER AND DRIFT CURRENT

-IN

INPUT

HA-2420t2425

J1J1.
8tH CONTROL
INPUT

Figure 4
CHARGE TRANSFER TEST

DRIFT CURRENT TEST

1. With a D.C. input voltage, observe the following
waveforms:

1. With a D.C. input Voltage, observe the following
waveforms:
S/H

8tH
CONTROL

CONTROL

4V----n
n - - - HOLD
OV ----J L--I ' - - SAMPLE

.,.---L.....
l-..
L-.J" L-.11--

OUTPUT~

""""J~-~-lt:N
I " l __

OUTPUT Vc

2. Compute charge transfer from:

Q

4V--1 I r---1--- HOLD
ov---l
W
L.. SAMPLE

~

=Vc CH

2. Measure the slope of the output during hold, t!.V /t!.t,
and compute drift current from: ID = CH t!.V /t!.t

HOLD MODE FEEDTHROUGH ATTENUATION
81NEWAVE
INPUT

-

-

+5
EN
IN2
IN1
IN3
IN4
HI-50BA
IN5
MUX OUT
IN6
IN7
INB
A2
A1
AO

-IN

HA-2420t2425

OUT

-

-iVINP-P

-

V
OUTPUT

-

8tH CONTROL
INPUT

Figure 5
NOTE: Compute hold mode feedthrough attenuation from the formula:
Feedthrough Attenuation = 20 Log V~~NTH~~~D
Where Vo UT HOLD = Peak-Peak value of output sinewave during the hold mode.

5-6

ACQUISITION TIMES

(CH = 1000pF)

-10VTO OV
S/H

-1V TO OV

+10V TO OV
S/H

5V

5~

5V

S/H

OV

I

\
,\
\

II
I

I

rl

2r

2V

50~mV

1lfs

+1V TO OV
S/H

~I
1

1\

OV
1)15

:,a.

OV

-100mVTO OV

5~

S/H

1)15

+100mV TO OV
S/H

5~

5V

OV
OV
OV

500rV

1~s

500ns

50mV

500ns

50rV

S/H!

CONTROL

SAMPLE

I

--4V

HOLD

L-..._ _

OV

II

SCHEMATIC
OFFSET ADJ

r-------~--~--~--~~----~_1_+~~~----------------~4r~~--~--------4r----OV,

RP

~-¥~~+_+_~--+_--+_----+_--__o~

H9

r-_+-l-+_+--Fl:::::::~'"t~-.()OUT
HID

ONOo-+---+---I-------+---------'

HI.

~-------+-----------------_r~----~----~~~--~--------~----~-----+---~-----+-~v-

I.,

IN-

5-7

APPLICA TIONS
BASIC SAMPLE-AND-HOLD
(TOP VIEW)

GUARD RING LAYOUT
(BOTTOM VIEW)

CONTROL
CONTROL

~--'-"--~INH

GN°Mo
HOLDING I
CAPACITOR"

OUT

OUT

I

~

~

°

.V-

v+_

~

Figure 6

IN+

$
$

$

____

O

Figure 7

NOTES:
This guard ring is recommended to minimize the drift
during hold mode.

1. Figure 6 shows a typical unity gain circuit, with Offset
Zeroing. All of the other normal op amp' feedback
configurations may be used with the HA-242012425.
The input amplifier may be used as a gated amplifier by
utilizing Pin 11 as the output. This amplifier has excellent drive capabilities along with exceptionally low
switch leakage.

3. The holding capacitor should have extremely high insulation resistance and low dielectric absorption. Polystyrene
(below +85 0 C), Teflon, or Parlene types are recommended.

2. The method used to reduce leakage paths on the P.C.
board and the device package is shown in Figure 7.

For more applications, consult Harris Application Note
517, or factory applications group.

GLOSSARY OF TERMS
ACQUISITION TIME:

APERTURE TIME:

The time required following a "sample" command, for the
output to reach its final value within ±0.1% or ±0.01%. This
is the minimum sample time required to obtain a given
accuracy, and includes switch delay time, slewing' time
and settling time.

The time required for the sample-and-hold switch to open,
independent of delays through the switch driver and input
amplifier circuitry. The switch opening time is that interval
between the conditions of 10% open and 90% open.
APERTURE DELAY:

CHARGE TRANSFER:

The small charge transferred to the hold capacitor from the
inter-electrode capacitance of the switch, during the transition
from Sample to Hold. Charge transfer contributes a ~ortion
(E) of the sample-to-hold offset (pedestal) error, according
to:
E(V) =Charge Transfer (pC)
Hold Capacitance (pF)

\

Other mechanisms contribute additional pedestal error during
the Sample to Hold transition.

5-8

The time interval between the sample-to-hold command
(50% level) and the instant at which the switch is 10% open.
DRIFT CURRENT:

The net leakage current from the hold capacitor during the
hold mode. Drift current can be calculated from the droop
rate using the formula:
ID(pA)

=CH (pF) x ~~ (Volts/sec)

IJ HARRIS

HO-0165
Keyboard Encoder

FEATURES

DESCRIPTION

•

STROBE OUTPUT

•

KEY ROLLOVER OUTPUT

•

EXPANOABLE: 2 PACKAGES REQUIRED FOR FULL
TELETYPEWRITER, EIGHT-BIT ENCODING

• SINGLE+5.0VSUPPLY REQUIRED
•

DTLITTL OUTPUTS

• MONOLITHIC RELIABILITY

A PPlICA TIONS

o MICROPROCESSOR OATA ENTRY (16 KEY TO
HEX COOE)
•

BCO OATA ENTRY

•

TYPEWRITER TYPE KEYBOARDS

•

CONTROL PANELS

PINOUT

The HD-OI65 Keyboard Encoder is a 16 line to four-bit parallel
encoder intended for use with manual data entry devices such as
calculator or typewriter keyboards. In addition to the encoding
function, there is a Strobe output and a Key Rollover output
which energizes whenever two or more inputs are energized
simultaneously. Any four-bit code can be implemented by
proper wiring of the input lines. Inputs are normally wired
through the key switches to the +5.0V power supply. Full
typewriter keyboard encoding up to eight bits can be accomplished with two Encoder circuits by the 'use of double pole key
switches or single pole switches with two isolation diodes per
key. Outputs will interface with all popular OTL and TTL logic
families. The circuit is packaged in a hermetic 24-pin dual-inline package and operates over the temperature range of DoC
to +75 0 C.

EI

I

EQUIVALENT CIRCUITS
Section 11 for Packaging
OUTPUT

Top View

Vee 1
PARALLEL {OUT 3 2
BINARY OUT4 3
STROBE 4
#16 INPUT 5
15
6
14
7
13
8
12
9
11
10
10
11
#9
12

..

..
.
..
..
..
.

24 KRO
23 GND
22 OUT I} PARAllEL
21 OUT 2 BINARY
20 # 1 INPUT
19
2
18
3
17
4
16
5
6'
15
14
7
13 #8

2KQ

KEYBOARO

• EQUIVALENT RESISTORS FOR OTHER
INPUTS ARE BETWEEN THESE TWO VALUES

5-9

SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
Input Voltage
Output Voltage

+7.0V
+5.5V
+5.5V

Output Current
Storage Temperature
Operating Temperature (Case)

30mA
-65° to +150°C
OoC to +75 0 C

UNITS

TEST CONDITIONS

ELECTRICAL CHARACTERISTICS
VCC =+5.0V ± 5%
TCase =OoC to +75°C
Unless otherwise specified

Test Conditions:

PARAMETER

SYM.

11,11

Input Current

MIN.

LIMITS
.. TYP.

.MAX

=+5.0V

17

rnA

+0.4
+0.4

V

ICC

52

rnA

One Input at +5.25V

Maximum ICCM

88

rnA

All Inputs at +5.25V

200

ns

TCase =25°C
VCC =VIN =+5.0V
Cl < 50pF

IIH

"0" VOL

+0.2

D.C. Output Voltage
"1" VOH

Operating

+2.4

VIN

VIH =+4.5V
IOl = lOrnA
VIH =+3.5V
IOl = 3.2mA
Vil =Open Circuit,loH =-240~A

+4.0

Power Supply Current

A.C. Skew Time (Note 1)

NOTE:

80

TSK

(1) Skew time is the maximum t~ifferential between propagation delay times of any

outputs including strobe and K RO '

TRUTH TABLE
INPUTS

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

1

2

3

L

L

L

L

L

L
L

L

L
L
L
L

L
L
L
L

L
L
L
L

L
L
L

L
L
L
L

l
l

l
l

l
l

l

L
L

l
l
l
H

H
H
H
H
H
l

l

l.
l
l

L
L
L
L
L

H
H
H

l

L
L

L
L
L

L
L
L
L

L
L
L
L
L
L
L
L
L
L
L
L

H
H

H

L
L
L
L

L

L
L

L
L
L
L
L

L

H

L
L

L

L

H
l
l

H

L
L
L

L
L

H

L
L

L
L
L

l
l
L

L
L
L

L

H

l

l

l

l

l

l

l

H

L
L
L

L
L
L
L
L

L
L
L

L
L
L
L

L
L
L
L

L
L
L

L
L
L

L
L
L
L

L
L
L

H

L

L
L

H

l
l
l
l

l
l
l

l

L

l

l
l
l
l

L

l

l
L
l
l
l
L
l
l
l
l
L
L
l
l
L
ANY TWO OR MORE HIGH
INPUTS:
OUTPUTS:

5-10

L
L
L

l
H
L
L

< +1.0V
H'"' > +2.4V

l = Open CircuIt or

L'

< +O.4V

L
L

L
L
L
L

l

H

l

L
L

L
L
L

l
l
l

l

L
L

l

H = > +4.5 V Current Source
X '" Erroneous Data

L

l
L
L
L
L
L
L
L
L

H
l
l
l

L
L
L
L

l

l

L

L
L
L
L
L
L
L
L
L

H
l
l

l
H
l

L
L

l
L
L
L

l

l
L
L
L
L
L
L
L
L
L
L

H

L

H
l
H

L

L

l
H
H

H

L

L

l

L

L

L

H

H
H
L
L

H
H
H
H

H
H

L
L

L

l

l
X

L

L

H
L

H
l
H
l
X

X

OUTPUTS
4
Sr.

H
H
H
H
H
H
H
H
H
L

l
L
L
L

L

l
l
X

H
L
L
L
L
L

l
L
L
L
L
L

l
l
l
l
l
l

KRO

H
H

H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L

APPLICATIONS
Vee +5.0V

,NPUTS , -_ _ _ _ _ _ _ _- ,

A....-

1
~2

20
19

22

18
11

PARAllEl

21

Figure 1. GENERAL CONFIGURATION FOR
ENCODING TWO TO SIXTEEN KEYS

BINARY

)

OUTPUTS

16
15
14
13

12
10

11

11
12

10

The Truth Table is used to determine
wiring from the key sWitches to Encoder
inputs to produce desired output codes.

STiffi'BE1 AUXILIARY

K1fif

24

OUTPUTS

9

13
14

15
~16

23

-=

KEYBOARD

GNO

+50V

Figure 2. SWITCH BOUNCE ELIMINATION
10K

IOOpF

HD·0165
St'

I>-t-"---o Si'
rG",,""-,,",--'

This circuit generates a delayed Strobe
pulse (ST'). Delay time is determined by
first monostable and should be about
10ms. Pulse width is determined by second monostable and should be set according to system requirements. Effect
of switch bounce or arcing on make or
break is positively eliminated and proper
encoding will take place under two
key rollover conditions

II
I

+~

ov SUPPL Y

DOUBLE POLE
KEY SWITCHES

INPUTS

OUTPUTS

HDUI6!i

."

}

OUTPUTS

10 (IOICUI1

Of FIGURE 2
HO

D16~

ALTERNATE ISOLATION METHOO
SINGLE POLE KEY SWIICHWlTH
TWa DIQIlES

Figure 3. ENCODING UP TO 256 KEYS
Use upper Encoder to produce the four most significant output bits; the lower
to produce the least significant bits. Use Truth Table and required output codes
to determine wiring from each key to the two Encoders.
SHIFT and CONTROL functions can be implemented by logic gates in series
with the output lines.

5-11

m~RlS

HI-562A
12 Bit High Speed Monolithic
Oigital-to-Analog Converter
DESCRIPTION

FEATURES
2mA, F.S.

• OUTPUT CURRENT
• MONOLITHIC CONSTRUCTION
• EXTREMELY FAST SETTLING

30005 TO 0.01% (TYP.)
±10ppm/OC (MAX.)

• LOW GAIN ORIFT
• EXCELLENT LINEARITY

±1/2 LSB (MAX.)

• OESIGNED FOR MINIMUM GLITCHES
• MONOTONIC OVER TEMPERATURE
• NOTE:

HI-562A IS RECOMMENDED FOR NEW DESIGNS

APPlICA TIONS
• CRT DISPLAY GENERATION
• HIGH SPEED AID CONVERTERS
• VIDEO SIGNAL RECOGSTRUCTION
• WAVEFORM SYNTHESIZERS
• HIGH SPEED DATA ACQUISITION

The Harris HI-562A is the first monolithic digital-to-analog converter to combine both ultra-high speed performance and 12-bit
accuracy on the same chip. The HI-562A's fast output current
settling of 300ns to 0.01% is achieved using dielectric isolation
processing to reduce internal parasitics for fast rise and fall times
during switching. Output glitches are minimized in the HI-562A
by incorporating equally weighted current sources switched into
an R-2R ladder network for symmetrical turn-ON and turn-OFF
switching times. This creates within the chip a very uniform
constant thermal distribution for excellent linearity and also
completely eliminates thermal transients during switching. High
stability thin film resistor processing together with laser trimming
provide the HI-562A with guaranteed true 12-bit linearity to
within ±1/2 LSB maximum at +25 0C for -4 and -5 parts, and to
within ±1I4 LSB maximum at +25 0C for -2 and -8 parts. The HI562A is recommended as a replacement for higher cost hybrid and
modular units for increased reliability and accuracy in applications
such as CRT displays, precision instruments and data acquisition
systems requiring throughput rates as a high as 3.3 MHz for full
range transitions. Its small size makes it an ideal choice as the
heart of high speed AID converter designs or as a building block
in high speed or high resolution industrial process control systems.
The HI-562A is also ideally suited for aircraft and space instrumentation where operation over a wide temperature range is
required.
The HI-562A-5 is specified for operation over OOC to +750C,
the HI-562A-4 over -250C to +850C and the HI-562A-2 and HI562A-8 over -55 0C to +125 0C. Processing MIL-STD-883A Class
B screening is available by selecting the H1-562A-8. All are
available in a hermetically sealed 24-lead dual-in-line package.

• HIGH-REL APPLICATIONS
• PRECISION INSTRUMENtS

FUNCTIONAL DIAGRAM

PINqUT
Section 11 for Packaging

TOP VIEW
Vps+

1

24 BIT 1 (MSB) IN

LOGfcM~{lm

2

23 BIT 21N

* VREF (LO IN)

3

22 BIT31N

N/C

4

21 BIT 41N

VREF (HIINI

5

20 BIT 51N

Vps-

6

BIPOLAR R IN

I

lB BIT liN

BIPOLAR ROUT

B

11 BITBIN

IOAC OUT

9

16 BIT giN

HI-562A

19 BIT6IN

10V SPAN R 10

15 BIT 10 IN

20V SPAN R 11

14 BIT llltl

* GNO

12

13 BIT 12 (LSBIIN

*Pin 3 connected to bottom else
for high frequency shielding.

5-12

m .....
LOGIC
GND

,

LEVEL 81Tl1N
V+ SELECT (MSBI 2

1

5

8

7

8

9

10

11

BIT 12 IN
(LSBI

SPECIFICA TlONS
ABSOLUTE MAXIMUM RATINGS
Power Supply .Inputs
Reference Inputs
Digital Inputs
Outputs

(Referred to Ground)l
Power Dissipation
Pd, Package
Operating Temperature Range
HI-562A-2
HI-562A-4
HI-562A-5
HI-562A-8
Storage Temperature Range

+2aV
Vps+
-2aV
VpsVREF (Hi)
±Vps
Bits 1-12
-IV, +12V
CM DS/TTL Logic Select -lV,+12V
Pins 7, 8, la, 11
±Vps
Pin 9
+Vps, -5V

laOOmW
-55 0 C to +125 0 C
-25 0 C to +85 0 C
OOC to +75 0 C
-55 0 C to +125 0 C
-65 0 C to +15a oC

ELECTRICAL CHARACTERISTICS (@+25 0 C, Vps +, = +5V, Vps- = -15V, VREF = +IOV, pin 2 tied to pin 12
unless otherwise noted)

PARAMETER

CONDITIONS

INPUT CHARACTERISTICS
Digital Inputs (31

Bit ON "logic I"
Bit OFF "logic 0"

r""'' '·
logic "I"
Logic "0"

TTL

2.0

Input Current (21
Logic "I"
logic "0"

O.S

20
-50

r"·"·
logic "I"
Logic "0"

CMOS

2.0

Over full
temp. range
Pin 2 tied to Pin 12

100
-100

Input Current
Logic "I"
Logic "0"

Reference Input
Input Resistance
Input Voltage

V
V

100
-100

nA
IlA

0.3Vps+

V
V

100
-100

nA
IlA

0.7Vps+

0.7Vps+
Connect pin 2 to pin 1 for

Vp .. ~ 9.5V. Otherwise
(for CMOS level. below SVI,
connect pin 2 to pin 12.

20
-50

0.8

0.3Vps+

II
I

20
-50

100
-100

20K'
+10

20
-50
20K
+10

n
V

TRANSFER CHARACTERISTICS
Resolution
Nonlinearity (31
Oifferential
Nonlinearity (31
Relative Accuracy (61
Gain Error

Bipolar Offset Error
Unipolar Offset Error
Adjustment Range
Gain
Bipolar Offset
Temperature Stability
Gain Orift (31
Offset Drift (31
Unipolar Off.. t
Bipolar Off,et
Differential Nonlinearity
Settling Time (31
to ±112 LSB

Over full temp. range

12

@+25 0 C

±1/4
:!:t

Over full temp. range

±112

@+25 0 C
Over full temp. range
With .50' n(1%1 Trim Resistors
All Bits ON
All Bits OFF

±114

±0.25
±o.25
±0.05

Bits
lSB

11

±114
±114
MONOTONICITY GUARANTEEO
±.024
±.024
±.012

12

±112

±.024
±.024
i.012

±1/2

lSB

to.25
to.25
±0.05

% FSR (41

See Operating Instructions

WithlOonTrim
Potentiometen
Drift specified with internal
span resistors for voltage output
Over lull
temp. range

to.25
±0.5

to.25

±O:S-

±6

tID

.:ttO
±2
14

All Bits OFF

% FSR

ppm of
FSR/oC

t2

Over full temp. range

±1

±2

±2

±4
±2

All Bits ON-to-OFF Dr
OFF-to-ON

300

400

300

400

ns

5-13

SPECIFICA TIONS (continued)

f

HI-S62A-2/HI-S62A-B
PARAMETER

CONDITIONS

MIN

TYP

MAX

HI-S62A-4/HI-S62A-5
MIN

TYP

MAX

UNITS

Major Carry Transient

Peak Amplitude
Settling Time to
90% Completu
Power Supply Sensitivity (31
Unipolar Offset
Vps+@+SV
Vp,-@-15V
Bipolar Offset
Vps+@5V
Vps-@-15V

From 011 ... 1 to 100... 0
or 100... 0 to 011...1

All Bits OFF

All Bits OFF, Bipolar mode

0.7

0.7

mA

35

35

n.

to.5

±0.5

to.5

to.5

t1.5
±1.5

il.5
±1.5

ppmo!
FSRI% Vp,

Gain

Vps+@+5V
Vps-@-ISV

All Bits ON

±l.5

±3.5
±7.5

:!:'I.5

OUTPUT CHARAC1:ERISTICS
Output Current
Unipolar
Bipolar

-2.0
:!:1.D

-2.0
:!:1.D

mA

Resistance

2K

2K

ohms

Capacitance

20

20

pF

010 +5
010+10
±2.5
±5
tl0

Oto+5
010+10

Output Voltage Range,
Unipolar
Bipolar

Using external op amp
and inturnal ",aling
resistors. See Figure 1
and Table 1 for connections

Compliance Limit (3)
Compliance Vollage (3)
Oulput Noise

t2.5

+10

-3

V

±5
tl0
-3

+10

V

Over !ull temp. range

itO

t1.0

V

0.1 to 10Hz (All Bits ON)
0.110 5MHz (All Bits ON)

30
100

30
100

/lV (p-p)

POWER REQUIREMENTS
Vps+ (7)
Vp,-

Over full
tump. range

Ip,+ (5)
Ips- (S)

All Bits ON or OFF in
either TTL or CMOS mode (25 0 C)

Ip,+ (5)
Ips- (5)
Power Dissipation

5-14

Same as above except
over fulltump. range
+2SoC
Vp,+ = +5V
Vps- = -15V

4.5
-13.5

5
-15

16.5
-16.5

8
16

4.75
-13.5

5
-15

16.S
-16.5

V

15
23

8
16

15
23

mA

11
20

20
30

;iu

11

.20
30

mA

280

420

mW

NOTES:
1.

Absolute maximum ratings are limiting values, applied
individually, beyond which the serviceability of the circuit
may be impaired. Functional operation under any of
these conditions is not necessarily implied.

2.

Vps+ tolerance is ±10% for HI-562A-2, -8. and ±5% for
HI-562A-4,-5.

3.

See Definitions.

4.

FSR is "full scale range" = 20V for ± 10V range, 10V
for !5V range, etc., or 2mA (!20%1 for current output.

5.

After 30 seconds warm-up.

6.

Using an external op amp with internal span resistors and
specified external trim resistors in place of potentiometers
R1 and R2. Errors are adjustable to zero using R1 and R2
potentiometers. (See Operating Instructions Figure 2.1

7.

The HI-562A.is designed for Vps+ = 5V, but +4.5V~Vps+
S +16V may be connected if convenient. (For Vps+
above +5V, there is an increase in power dissipation but
little change in performance.)

DEFINITIONS OF SPECIFICA TlONS
DIGITAL INPUTS

DRIFT

The HI-562A accepts digital input codes in binary format and
may be user connected for anyone of three binary codes.
Straight Binary, Two's Complement, or Offset Binary, (See
Operating Instructions).

GAIN DRIFT - The change in full scale analog output over the
specified temperature range expressed in parts per million of
full scale range per OC (ppm of FSR/OC). Gain error is measured with respect to +25 0 C at high (TH) and low (TLI temperatures. Gain drift is calculated for both high (TH -25 0 C) and
low ranges (+25 0 C -TL) by dividing the gain error by the respective change in temperature. The specification is the larger of
the two representing worst case drift.

ANALOG OUTPUT
DIGITAL
INPUT
MSB LSB
000 ... 000
100... 000
111...111
011...111

Straight
Binary

Offset
Binary

Two's
Complement"

Zero
-FS (Full Scale I
Zero
It,FS
Zero
-FS
+FS - 1 LSB +FS - 1 LSB
Zero -1 LSB
)f,FS - 1 LSB Zero - 1 LSB +FS - 1 LSB

'Invert MSB with external inverter to obtain Two's
Complement Coding

ACCURACY

NONLINEARITY - Nonlinearity of a D/A converter is an
important measure of its accuracy. It describes the deviation
from an ideal straight line transfer curve drawn between zero
(all bits OFFI and full scale (all bits ON).
DIFFERENTIAL NONLINEARITY - For a D/A converter, it
is the difference between the actual output voltage change and
the ideal (1 LSBI voltage change for a one bit change in code.
A Differential Nonlinearity of ±1 LSB or less guarantees monotonictiy; i.e., the output always increases and never decreases
for an increasing input.
SETTLING TIME

Settling time is the time required for the output to settle to
within the specified error band for any input code transition.
It is usually specified for a full scale or major carry transition.

OFFSET DRIFT - The change in analog output with all bits
OFF over the specified temperature range expressed in parts
per million of full scale range per oC (ppm of FSR/oCI. Offset
error is measured with respect to +25 0 C at high (THI and low
(TLI temperatures. Offset Drift is calculated for both high
(TH -25 0 CI and low (+25 0 C -TLI ranges by dividing the offset
error by the respective change in temperature. The specification
given is the larger of the two, representing worst-case drift.

II

POWER SUPPLY SENSITIVITY

Power Supply Sensitivity is a measure of the change in gain and
offset of the converter resulting from a change in the -15V
It is specified under DC conditions and
or +5V supplies.
expressed as parts per million of full scale range per percent of
change in power supply (ppm of FSR/%).
COMPLIANCE

Compliance voltage is the maximum output voltage range that
can be tolerated and still maintain its specified accuracy. Compliance limit implies functional operation only and makes no
claims to accuracy.
GLITCH

A glitch on the output of a D/A converter is a transient spike
resulting from unequal internal ON-OFF switching times. Worst
case glitches usually occur at half-scale or the major carry code'
transition from 011 ... 1 to 100... 0 or vice versa. For example, if
turn 0 N is greater than turn 0 FF for 011...1 to 100...0, an intermediate state of 000 ... 0 exists, such that, the output momentarily glitches toward zero output. Matched switching times
and fast switching will reduce glitches considerably.

5-15

OPERATING INSTRUCTIONS
DECOUPLING AND GROUNDING

Table I

For best accuracy and high frequency performance, the grounding and decoupling scheme shown in Figure 1 should be used.
Oecoupling capacitors should be connected close to the H1562A (preferably to the device pins) and should be tantalum
or electrolytic bypassed with ceramic types for best high frequency noise rejection.

r.

••• <

Unipolar
Mode

Pl
V '

Bipolar

O'O~'~F
l~F

CONNECTIONS
OUTPUT Pin 7 Pin 8 Pin 10 Pin 11 BIAS (RB)
RANGE
to
to
to
to
RESISTOR

Mode

oto +10V
oto +5V

N.C. N.C.

A

N.C.

1.43K

N.C.

N.C.

A

9

1.11K

±10V

0

9

N.C.

A

1.43K

±5V

0

9

A

N.C.

1.25K

±2.5V

0

9

A

9

1.0K

l~F

EXTERNAL GAIN AND ZERO CALIBRATION

(See Figure 2)

HI-562A

ANALOG GROUND

Figure I
UNIPOLAR AND BIPOLAR VOLTAGE OUTPUT
CONNECTIONS

CONNECTIONS - Using an external resistive load, the output
voltage should not exceed ±IV to maintain specified accuracy. For higher output voltages, accuracy can be maintained by
using an external op amp and the internal span resistors as shown
in Figure 2 and defined in Table 1 for unipolar and bipolar
modes.
+5V/.,5V,-15V

The input reference resistor (20K nominal) and bipolar offset
resistors shown in Figure 2 are both intentionally set low by
50 n to a" the user to externally trim-out initial errors to a very
high degree of precision. The adjustments are made in the voltage output mode using an external op amp as current-to-voltage converter and the HI-562A internal scaling resistors as
feedback elements for optimum accuracy and temperature
coefficient. For best accuracy over temperature, select an op
amp that has good front-end temperature coefficients such as
the HA-2600/2605 with offset voltage and offset current
tempco's of 5 Jl V/oC in lnA/OC, respectively. For high speed
voltage mode applications where fast settling is required, the
HA-2510/2515 is recommended for better than 1.5 Jl s settling
to' 0.01%. Using either one, potentiometer R3 conveniently
nulls unipolar offset plus op amp offset in one operation (for
HA-2510/2515 and HA-2600/2605 use R3 = 20K and lOOK,
respectively). For bipolar mode operation, R3 should be used to
null op amp offset to optimize its tempco (Le., short 9 to A and
adjust R3 for zero before calibrating in bipolar mode). The gain
and bipolar offset adjustment range using lOOn potentiometers
is ±12lSB and ±25 lSB respectivelv. If desired, the potentiometers can be replaced with fixed 50n(I%) resistors resulting
in an initial gain and bipolar offset accuracy,.of typically
!ll2lSB.
UNIPOLAR CALIBRATION

BIPOLAR

OFFSET

ADJUST

*

L._ _ _ _ _ _:::::.._ _--'

r::1.

~100n. 1ST

®

BIPOLAR CALIBRATION
For TTL and DTL compatibility, connect +5V to pin 1 and
tie pin 2 to pin 12. For CMOS compatibility, connect digital

power supply (+4.B5V ~ VOO ~ +12V) to pin 1 and short
pin 2 to pin 1,

**

Bias resistor, AB. should be chosen to equalize op amp offset
voltage due to, bias current. Its value is calculated from the
parallel combination of the current source outPUt resistance
(2K) and the OP amp feedback resistor. See Table 1 for
values of R B.

Figure 2

5-16

Step 1: Unipolar Offset
• Turn all bits OFF
• Adjust R3 for zero volts output
Step 2: Gain
• Turn all bits ON
• Adjust R2 for an output of FS -1 lSB
That is, adjust for:
9.9976V for OV to +1 OV range
4.9988V for OV to +5V range

Step 1: Bipolar Offset
• Turn all bits OFF
• Adjust R1 for an output of:
-10V for ±1 OV range
-5V for ±5V range
-2.5V for ±2.5V range
Step 2: Gain
• Turn bit 1 (MSB) ON; all other bits OFF
• Adjust R2 for zero volts output

mHARRIS

HI-5610
10 Bit High Speed Monolithic
Digital-to-Analog Converter

Preliminary
FEATURES

APPlICA TIONS

•

MONOLITHIC CONSTRUCTION

•
•

EXTREMELY FAST SETTLING ............... 85n8 TO Y2LSB TYP.
LOW GAIN DRIFT .......................... ±5ppm/OCTVP.

•
•
•

EXCELLENT LINEARITY OVER TEMPERATURE ....... ± Y,LSB MAX.
OESIGNEO FOR MINIMUM GLITCHES
MONOTONIC OVER TEMPERATURE

•
•
•
•
•
•
•

CRT DISPLAY GENERATION
HIGH SPEED AlO CONVERTERS
VIOEO SIGNAL RECONSTRUCTION
WAVEFORM SYNTHESIZERS
HIGH SPEEO DATA ACQUISITION
HIGH RELIABILITY APPLICATIONS
PRECISION INSTRUMENTS

DESCRIPTION
The HI-5610 is an ultra-high speed 10 bit monolithic current output digital-to-analog converter. The fast output current settling of
85ns to Y,LSB of its final value is achieved using dielectric isolation
processing to reduce internal parasitics for fast rise and fall times
during switching. Output glitches are minimized in the HI-5610 by
incorporating equally weighted current sources switched into an
R-2R ladder network for symmetrical turn-on and turn-off switching times. This creates within the chip a very uniform and constant
thermal distribution for excellent linearity and also eliminates thermal transients during switching. High stability thin film resistor
. processing, together with laser trimming provide the HI-5610 with
true 10 bit linearity to within ± Y,LSB maximum over operating
temperature range. The HI-5610's low offset and gain drift over
the operating temperature range assures that its absolute accuracy
when referred to a fixed 10V reference will not deviate more than
± 1LSB for both unipolar and bipolar operation.

PINOUT

The H1-561 0 is recommended as a replacement for high cost hybrid
and modular units for increased reliability and accuracy in applications such as CRT Displays, precision instruments and data acquisition system requiring through-put rates as high as 12mHz for full
range transitions. Its small size makes it an ideal choice as the
essential part of high speed AID converter designs or as a building
block in high speed or high resolution industrial process control
systems. The HI-5610 is also ideally suited for aircraft and space
instrumentation where operation over a wide temperature range is
required.

II
I

The HI-5610-5 is specified for operation over OOC to +75 0 C, the
HI-5610-2 and HI-5610-8 over -55 0C to +1250C. Processing to
MI L-STD-883A class B screening is available by selecting the
HI-5610-8. All are available in a hermetically sealed 24 lead dualin-line package.

FUNCTIONAL DIAGRAM
Section 11 for Packaging

TOP VIEW

LOGIC

VpsBIPOLAR R IN
BIPOLAR ROUT
IOAC OUT
SPAN R
SPAN R
• GNO

BIT 10lN

LEVEL BIT 1 IN

Vps+
CMosmL
LOGIC SELECT
• VREF (LO IN) 3
NC
VREF (HI IN)

9
10
11
12

24
23
22
21
20
19
lB
17
16
15
14
13

BIT 1 (MSB) IN
BIT 21N
BIT 31N
BIT 41N
BIT 51N
BIT 61N
BIT 71N
BIT BIN
BIT 91N
BIT 10 IN
NC
COMPo CAP"

GND

12

V+ SELECT (MSBI

24

IlSa)
10

2

23

" Pin 3 connected to bottom case for high
frequency shielding.
"" For high speed operation, connect 0.01 J..l F
between Pin 13 and GND.
leave Pin 13 open.

Otherwise,

v-

5-17

SPECIFICA TlONS
ABSOLUTE MAXIMUM RATINGS
Power Supply Inputs

(Referred to Ground) 1

Vps+
VpsVREF(Hi)
VREF(Lo)

Reference Inputs

Power Dissipation Pd, Package

±Vps
OV

Operating Temperature Range
HI-5610-2
HI-5610-5
HI-5610-8

-55 0 C to +1250 C
OOC to +75 0 C
-55 0 C to +125 0 C

Storage Temperature Range

-65 0 C to +150 oC

Digital Inputs

Bitsl-12
CMDS/TTL Logic Select

-lV,+12V
-lV,+12V

Outputs

Pins 7, 8,10,11
Pin 9

±Vps
+Vps, -5V

ELECTRICAL CHARACTERISTICS

1000mW

+20V
-20V

(@+25 0 C,V ps+,=+5V, Vps-= -15V, VREF = +10V, pin 2 ground
unless otherwise noted)
HI-5610-2
HI-5610-8

PARAMETER

TEMP

MIN

Full
Full

2.0

TYP

HI-5610-5
MAX

MIN

TYP

MAX

UNITS

O.B

V
V

100
-100

nA
/lA

0.3V p,+

V
V

100
-100

nA
/lA

INPUT CHARACTERISTICS
Digital Inputs (2)
TTL logic Input Voltage (3)
logic "1"
logic "0"
Input Current
logic "1"
logic "0"

Full
Full

CMOS logic Input Voltage (4)
logic "1"

Full
Full

Logic "0"
Input Current

logic "1"
logic "0"

Full
Full

Reference Input
Input Resistance
Input Voltage (lOUT = SmA + 20%)

2.0
O.B
20
-50

100
-100

20
-50
0.7V ps+

0.7Vps+
0.3 Vps+
20
-50

100
-100

8K
+10

20
-50

n

8K
+10

V

TRANSFER CHARACTERISTICS
Resolution

Full

10

10

Bit'

Nonlinearity (5)

25 0 C

±Y2

.t~

lSB

25 0 C

±,~

.t~

lSB

Oifferential Nonlinearitv (5)

--

Relative Accuracy (61
Gain Error

(9)

(Input Code 11.. .. 1)
Unipolar Offset Error
(Input Code 00 .... 0)
Bipolar Offset Error
(Input Code 00 .... 0)
(Adjustable to zero, see Figure 4, 5)
Adjustment Range
Gain
Bipolar Offset
Temperature Stability
Gain Drift
Unipolar Offset Drift
Bipolar Offset Drift
Oifferential Nonlinearity

Full
Full
Full
Full

iO.05

.to.05

% FSR

.to.05

·iO.05

% FSR

.to.05

'iO.05

% FSR

:to.25
iO.25

iO.25
iO.25

% FSR
% FSR

is

i5
±.3
i3
±'2

ppm/DC
ppm/DC
ppm/DC
ppm/DC

±.3
i3
±.2

MONOTONICITY - GUARANTEED OVER FUll OPERATING TEMPERATURE RANGE
Settling Time to Y,lSB (5)
From all a'' to alii',
From alii', to all a''
Major Carry Switching to 90% Complete

5-18

40

B5
85

ns
n'

40

ns

SPECIFICA TIONS (continued)

PARAMETER

TEMP

MIN

TYP

MAX

MIN

TYP

MAX

UNITS

Power Supply Sensitivity (5)
Vps+ = +5V, Vps- = -13.5V to -16.5V
Gain
(Input Code 11 .... 1)
Unipolar Offset
(I nput Code 00 .... 0)
Bipolar Offset
(I nput Code 00 .... 0)

±.2

.±2

Vps- = -15V, Vps+ = 4.5V to 5.5V
Gain
(Input Code 11 .... 1)
Unipolar Offset
(I nput Code 00 .... 0)
Bipolar Offset
(I nput Code 00 .... 0)

.±0.5

.± 0.5

.± 1.5

.± 1.5

.±I

ppm of
FSR/%Vps

.±1

±0.5

±.0.5

± 1.5

± 1.5

Output Current
Unipolar
Bipolar

-5.0
.±2.5

-5.0
.± 2.5

rnA
rnA

Output Resistance

200

200

n

Output Capacitance

20

20

pF

+5
+2.5
±2.5
± 1.25

+5
+2.5
±2.5
± 1.25

V
V
V
V

OUTPUT CHARACTERISTICS

Output Voltage Range (7J
Unipolar
Bipolar
Output Compliance Limit (5)
Output Compliance Voltage (5)

-3
Full

Output Noise Voltage (8)
0.1 Hz to 100Hz
O.IHz to IMHz

+10

-3

+10

± 1.5

± 1.5

10
100

10
100

V
V

Il Vp-p
IlVp-p

POWER REQUIREMENTS
Vps+ (4)

Full

4.5

5

16.5

4.75

5

16.5

V

Vps-

Full

-13.5

-15

-16.5

-13.5

-15

-16.5

V

Ips+ (All l's or all O's in
(10) either TTL or CMOS Mode)

25 0 C
Full

9
20

9
20

rnA
rnA

Ips- (Same as above)
(10)

25 0 C
Full

25
30

25
30

rnA
rnA

5-19

NOTES:
1.

2.

3.

4.

Absolute maximum ratings are limiting values, applied individually, beyond which the serviceability of the circuit may be
impaired. Functional operation under any of these conditions
is not necessarily implied.

5.

See definitions.

6.

The HI-5610 accepts digital input codes in binary format and
may be user connected for anyone of three binary codes.
Straight binary, offset binary, or two's complement binary.
(See operating instructions).

Using an external op amp with internal span resistors and
24.9n ±1% external trim resistors in place of potentiometers
Rl and R2. These errors are adjustable to zero using Rl and
R2. (See operating instructions.)

7.

Using an external op amp and internal span resistors. (See
operating instructions for connections'!

For TTL and OTL compatibility connect +5V to pin 1 and
ground pin 2. The Vps+ tolerance is ±10% for HI-5610-2,-S.
And ±5% for HI-5610-5.

8.

Specified for digital input in all 'l's or all 'O's.

9.

FSR is "Full Scale Range" and is 5V for ±2.5V range, 2.5V
for ±1.25V range, etc., or 5mA (±20%) for current output.

For CMOS compatibility based on Vps+ ~ +SV, (switching
thresholds'equal Vps+/2), connect pins 1 and 2. For CMOS
,levels below +SV, connect pin 2 to ground only {this provides
a threshold of approximately +1.4VI.

10.

After 30 seconds warm-up.

DEFINITIONS OF SPECIFICATIONS
ACCURACY
NONLINEARITY - Nonlinearity of a O/A converter is an important measure of its accuracy. It describes the deviation from an
ideal straight line transfer curve drawn between zero (all bits 0 FF)
and full scale (all bits ON).
DIFFERENTIAL NONLINEARITY - For a O/A converter, it is
the difference between the actual output voltage change and the
ideal (1 LSB) voltage change for a one bit change in code. 'A Differential Nonlinearity of ± 1LSB or less guarantees monotonicitiy;
i.e., the output always increases and never decreases for and increasing input.

SETTLING TIME
Settling time is the time required for the output to settle to within the specified error band for any input code transition. It is
usually specified for a full scale or major carry transition
(01 .......... 1 to 10.......... 0 or vice versa)
DRIFT
GAIN DRIFT - The change in full scale analog output over the
specified temperature range expressed in parts per million of full
scale range per DC (ppm of FSR/OC). Gain error is measured with
respect to +25 0 C at high (TH) and low (lL) temperatures. Gain
drift is calculated for both high (TH -25 0 C) and low ranges (+25 0 C
- TL) by dividing the gain error by the respective change in temperature. The specification is the larger of the two representing worst
case drift.
OFFSET DRIFT - The change in analog output with all bits OFF
over the specified temperature range expressed in parts per million

of fuJI scale range per oC (ppm of FSR/OC). Offset error is measured with respect to +25 0 C at high (TH) and low (TL) temperatures.
Offset Drift is calculated for both high (TH -25 0 C) and low (+25 0 C
-TLl ranges by dividing the offset error by the respective change
in temperature. The specification given is the larger of the two.
representing worst case drift.

POWER SUPPLY SENSITIVITY
Power Supply Sensitivity is a measure of the change in gain and offset of the D/A converter resulting from a change in -15V. +5V Dr
+15V supplies. It is specified under DC conditions and expressed as
parts per million of full scale range per percent of change in power
supply (ppm of FSRf%).

COMPLIANCE
Compliance voltage is the maximum output voltage range that can
be tolerated and still maintain its specified accuracy. Compliance
limit implies functional operation only and makes no claims to
accuracy.

GLITCH
A glitch on the output of a D/A converter is a transient spike
resulting from unequal internal ON-OFF switching times. Worst
case glitches usually occur at half-scale or the major carry code
transition from 011.. ... 1 to 100.....0 Dr vice versa. For example.
if turn ON is greater than turn OFF for 011. .... 1 to 100.....0. an
intermediate state of 000..... 0 exists, such that, the output momentarily glitches toward zero output.' Matched switching times and fast
switching will reduce glitches considerably.

OPERATING INSTRUCTIONS
DECOUPLING AND GROUNDING
For best accuracy and high speed performance. the grounding and
decoupling scheme shown in Figure 1 should be used. Decoupling
capacitors should be connected close to the HI-5610 (preferrably to
the device pin) and should be tantalum or electrolytic bypassed
with ceramic types for best high frequency noise rejection.

, .r;-

CMOSITTL
LOGIC SELECT

i-

~

SEE NOTE 3. 4

I

r.-

V p"

:k :ko.oT-

~PF

~,
~-VREF
HI-5610

£Tl-=r
T
>---4--_...,'s
lPF
l

V~_

~--t>L_-

oPF
.o1

L.-

FIGURE 1

5-20

~
'i7
&---;
~---"----i

~-

+

OPERA TING INSTRUCTIONS (continued)
HIGH PERCISION PERFORMANCE

The output accuracy of the HI-5610 depends mainly on the accuracy of the voltage applied to the VREF input of HI-5610 and it can
be described roughly as VREF/8Kn = 14 full scale output current.
This means the output of HI-5610 will change whenever VREF
varies. For high precision performance a precision +10V voltage
reference with reasonably low temperature coefficient such as HA1600 is highly recommended. For voltage output operation use an
external op amp as current-to-voltage converter and the HI-5610
internal scaling resistors as feedback elements for optimum accuracy
and temperature coefficient. The selected op amp should have a good
front-end temperature coefficient such as HA-2600/2605 with offset voltage and offset current tempco's of 5 iJ VlaC and 1nAloC,
respectively. The input reference resistor (7.975K n) and bipolar
offset resistor (3.975K n ) are both intentionally set low by 25 n
to allow the user to externally trim-out initial errors to a very high
degree of precision. For high speed voltage output applications
where fast settling is required, the HA-251 0/2515 is recommended
for better than 1 Jl s settling to %LSB.

UNIPOLAR - STRAIGHT BINARY
OV TO +2.5V OUTPUT RANGE
OIGITAL
INPUT
11
10
01
00

.....
.....
....1.
.... '.

ANALOG OUTPUT
I
0
1
0

FS -ILSB
%FS
%FS -ILSB
Zero

= 2.49756V
= 1.25000V
= 1.24756V
= O.OOOOOV

GAIN

UNIPOLAR VOLTAGE OUTPUT CONNECTIONS
AND CALIBRATION

+15V

The connections for unipolar +5V and +2.5V voltage output using
an external op amp and the internal span resistors are shown in Figure 2 and Figure 3, respectively.
CALIBRATION - UNIPOLAR

FIGURE 3

Step 1 Offset
• Turn all bits off (all O's) .
• Adjust R3 for zero volts ~utput
Step 2 Gain
• Turn all bits on (aliI's)
• Adjust RI for an output of FS-l LSB
That is, adjust for:
4.99512V for OV to +5V range
2.49756V for OV to +2.5V range

11
10
01
00

.....
.....
..•..
.....

FS -ILSB
%FS
%FS -ILSB
Zero

R3

20KIl
-15V

II

The connections for Bipolar.±. 2.5V and.±. 1.25V voltage output
using an external op amp and the internal span resistors are shown
in Figure 4 and Figure 5, respectively.
CALIBRATION - BIPOLAR
Step I Op Amp Null
• Short op amp output to op amp -input
• Adjust R3 for zero volts output
Step 2 Gain
• Turn all bits on (aliI's) record output voltage
• Turn all bits off (all O's) record output voltage
• Adjust RI till the difference between the readings
is equal to:
4.99512V for ± 2.5V range
2.49756V for ±1.25V range.
Step 3 0 ffset
• Turn bit I (MSB) on, all other bits off (10 ....0)
• Adjust R2 for zero volts output

ANALOG OUTPUT
I
0
I
0

~

BIPOLAR VOLTAGE OUTPUT CONNECTIONS
AND CALIBRATION

UNIPOLAR - STRAIGHT BINARY
OV TO +5V OUTPUT RANGE
OIGITAL
INPUT

VOUT

lOOKIl

=4.99512V
=2.50000V

=2.49512V
=O.OOOOOV

GAIN

+15V

FIGURE 2

VOUT

lOOKIl

~

R3

20KIl
-15V

5-21

OPERATING INSTRUCTIONS (continued)
BIPOLAR - OFFSET BINARY
±2.5V OUTPUT VOLTAGE RANGE

I

DIGITAL
INPUT
11
10
01
00

GAIN

ANALOG OUTPUT

0
1
0

+FS -1 LSB
ZERO
Zero - 1 LSB
-FS

=+2.49512V
= +O.OOOOOV
= -0.00488V
= -2.50000V

HI-5610

BIPOLAR TWO'S COMPLEMENT **
.±2.5V OUTPUT VOLTAGE RANGE

I

DIGITAL
INPUT
01
00
11
10

ANALOG OUTPUT

0
1
0

+FS - 1LSB
Zero
Zero -1 LSB
-FS

+15V

= +2.49512V
= +O.OOOOOV
= -0.00488V
= -2.50000V

VOUT

-15V

to obtain two's complement coding.

FIGURE 4

BIPOLAR - OFFSET BINARY
.± 1.25V OUTPUT VOLTAGE RANGE

11
10
01
00

GAIN

ANALOG OUTPUT

0
0

+FS -1 LSB
Zero
Zero -ILSB
-FS

= +1.24756V
= +O.OOOOOV
= -0.00244V
= -1.25000V

HI-5610

BIPOLAR - TWO'S COMPLEMENT **
.± 1.25V OUTPUT VOLTAGE RANGE

I

OTO

DIGITAL
INPUT
01
00
11
10

+15V

ANALOG OUTPUT

0

+FS -ILSB
Zero
Zero - lLSB
-FS

200n
= +1.24756V
= +O.OOOOOV
= -0.00244V
= -1.25000V

VOUT

100Kn
FIGURE 5

5-22

R3

20K.Il

100Kn

** Invert MSB with external inverter

DIGITAL
INPUT

~

~

R3

20Kn
-15V

m~RIS

HI-5618A/5618B
8 Bit High Speed
Oigital-to-Analog Converters

FEATURES

DESCRIPTION

• VERY FAST SETTLING CURRENT OUTPUT

65ns

• MINIMUM NONLINEARITY ERROR
±. 1/4 LSB MAX
HI-5618A
.±.1/2 LSB MAX
HI-5618B
340mWTYP

• LOW POWER OPERATION
• ON-CHIP RESISTORS FOR GAIN AND
BIPOLAR OFFSET
• GUARANTEED MONOTONIC OVER
TEMPERATURE
• CMOS, TTL, OR DTL COMPATIBLE

APPLICATIONS
• HIGH SPEED PROCESS CONTROL

The HI-5618A1B are very high speed 8 bit current output D/A converters.
These monolithic devices are fabricated with dielectrically isolated bipolar
processing, which reduces internal parasitic capacitance to allow fast rise and
fall times. This achieves a typical full scale settling time of 65ns to ±.1/2 LSB .
Output glitches are minimized by incorporation of equally weighted current
sources, switched to either an R-2R ladder network or ground for symmetrical
turn ON and turn OFF times. High stability thin film resistors provide excellent accuracy without trimming. For example, the HI-5618A has ± 1/4 LSB
maximum nonlinearity error at +25 0 C, with ±3/8 LSB guaranteed over the full
operating temperature range.
The HI-5618A1B are recommended for any application requiring high speed
and accurate conversions. They can be used in CRT displays and systems
requiring throughput rates as high as 20MHz for full scale transitions. Other
applications include high speed process control, defense systems, avionics, and
space instrumentation.

II

The HI-5618A-5 and HI-5618B-5 are specified for operation from OOC to
+75 0 C. The "-2" versions are specified from -55 0 C to +125 0 C. "Dash 8"
(-8) designates parts which have been screened per MI L-STD-883,
Method 5004/Class B.

• CRT DISPLAY GENERATION
• HIGH SPEED A/D CONVERSION
• WAVEFORM SYNTHESIS
• HIGH RELIABILITY APPLICATIONS

o VIDEO SIGNAL RECONSTRUCTION

Power requirements are +5V and -15V. Package is an 18 pin DIP, in plastic
or ceramic.

PINOUT

FUNCTIONAL DIAGRAM
Section 11 for Packaging

TOP VIEW

CMOS/TTL BIT
GND Vps+ SELECT

+VPS

BIT 1 MSB

CMOSITTl

BIT 2

VREF HIGH

BIT 3

-Vps

BIT 4

BIPOLAR RIN

BITS

lOUT

BIT 6

10 VOLT SPAN

BIT7

20 VOLT SPAN

BIT 8 lSB

GNO

9

1

fLSBI
8

2

VREF LOW

5-23

SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS

(Referred to Ground) (1)

Vps+
Vps -

+20V
-20V

Reference Inputs

VREF (Hi)
VREF (Lo)

±'Vps
OV

Digital Inputs

Bits 1-8

Power Supply Inputs

-IV, +12V

Pins 5, 7, 8
Pin 6

Dissipation Pd, Package

700mW

Dperating Temperature Range
H1-5618A/B-2
H1-5618A1B-5
HI-5618A1B-8

-lV, +12V

CMOSITTL Logic Select
Outputs

~ower

-55 0 C to + 1250 C
OOC to +75 0 C
-55 0 C to +1250 C
-65 0 C to 150 0 C

Storage Temperature Range

±Vps
+Vps, -2.5V

ELECTRICAL CHARACTERISTICS

(V ps+ =+5V; Vps-

=-15V; VREF =+10V; Pin 2 to GND,

H1-561 BAIB-2
H1-561 BAIB-8
PARAMETER

TEMP

MIN

Full
Full

2.0

unless otherwise noted)

H1-561 BAIB-5

I TYP I MAX

MIN

ITYP I MAX

UNITS

INPUT CHARACTERISTICS
Digital Inputs (2)
TTL Logic Input Current (3) Logic "I"
Logic "0"
Input Current

Logic "I"
Logic "0"

Full
Full

CMOS Logic Input Voltage (4) Logic "I"
Logic "0"

Full
Full

Logic "I"
Logic "0"

Full
Full

20
-50

+250C
+25 0C

Bk
+10

Full

8

CMOS Logic Input Current

Reference Input
Input Resistance
Input Voltage (lOUT = 5mA:!: 20%)

O.B

V
V

100
-100

nA
J.l.A

0.3V ps+

V
V

100
-100

nA
J.l.A

2.0
O.B
20
-50

100
-100

0.7Vps+

20
-50
0.7Vps+

0.3V ps+
100
-100

20
-50

n

Bk
+10

V

TRANSFER CHARACTERISTICS
Resolution

.i 114

Initial Accuracy (6)
(Relative to Ext,ernal +10V Reference)
Gain
Unipolar Zero
Bipolar Offset (Neg. Full Scale)
Temperature Stability
Gain Drift
Unipolar Zero Orift
Bipolar Zero Drift

HI-651BA
HI_5618B

Settling Time (5) to 1/2 LSB
High Impedance (11)
(from all O's to all l's)
or (from all 1's to all O's)

5-24

Bits

B

25 0 C
Full
25 0 C
Full

Nonlinearity, Integral and
Differential

-

i31B
i 1/2
±. 518

±.114
i31B
±.1/2
±518

LSB
LSB
LSB
LSB

25 0 C
25 0C
25 0 C

±2
±. liB
±.2

±.2
±. liB
±2

LSB
LSB
LSB

Full
Full
Full

±1/4
±. 1/16
±'114

±. 114
±. 1116
± 114

LSB
LSB
LSB

75

ns

+25 0 C

65

75

65

SPECIFICATIONS (Continued)
HI-5618A/B-2
HI-5618A/B-8
PARAMETER

H1-5618A/B-5

I TYP I MAX

UNITS

TEMP

MIN ! TYP! MAX

Glitch (5) - Major Carry Transition
Ouration
Amplitude (See Fig. 4)
Area

+25 0C
+25 0C
+25 0C

20
350
3500

Power Supply Sensitivity (5)
V ps+ = +5V, V ps - = -13V to
Gain
Unipolar Zero
Bipolar Offset

-16.5V
(Input Code 11 ... 1)
(Input Code 00 ... 0)
(Input Code 00 ... 0)

+25 0C
+25 0C
+25 0C

±0.5
:': 1.5

V ps - = -15V, Vps+ = 4.5V to
Gain
Unipolar Zero
Bipolar Offset

5.5V
(Input Code 11 ... 1)
(Input Code 00 ... 0)
(Input Code 00 ... 0)

+25 0C
+25 0C
+250C

:i0.5
±. 1.5

±. 0.5
±. 1.5

Unipolar
Bipolar

+25 0C
+25 0C

-5
±. 2.5

-5
±'2.5

Output Resistance

+250C

500

500

n

Output Capacitance

+25 0C

20

20

pF

+25 0C
+25 0C
+250C
+25 0C
+25 0C

+10
+5
± 10
±.5
:i 2.5

+10
+5
±.10
±.5
±'2.5

V
V
V
V
V

Output Compl.iance Voltage (5)

+25 0C

.±. 1.5

±. 1.5

V

Output Noise Voltage (8)

+25 0C
+25 0C

30
100

30
100

IlVp-p
IlV pcp

MIN

TRANSFER CHARACTERISTICS (Continued)
ns
mV
mV-ns

20
350
3500

±.5

:i5

ppm of
FSR/% Vps

±'0.5
.±. 1.5

(9)

±.5

±.!i

OUTPUT CHARACTERISTICS
Output Current

Output Voltage Range (7)

Unipolar
Bipolar

O.lHz to 100Hz
O.lHz to lMhz

rnA
rnA

II

POWER REQUIREMENTS (4)

Vps+
Vps-

1.

Full

4.5

5

Full

-13.5

-15

Ips+ (10) (All l's or all O's in either
TTL or CMOS mode) (3,4)

+25 0C
Full

9

Ips -ll0) (All 1's or all D's in either
TTL or CMOS mode) (3,4)

+25 0C
Full

19

3.

4.

For TTL and DTL compatibility connect +5V to pin 1 and
ground pin 2. The V ps+ tolerance is
10% for HI-5618A/B
-2, -B: and±.5% for HI-561BA/B-5.

±

For CMOS compatibility connect digital power supply

(+4.5V

~ VOO ~ +10V) to pin 1 and short pin 2 to pin 1.

5

-14.25 -15

V

15
-15.75

V

12

rnA
rnA

26

rnA
rnA

9
19
26

meters A,. R2. Ra. R, and R2 each provide more than ± 3
LSB's adjustment. (See Operating Instructions). The specifications listed under initial accuracy are based on use of an
external op amp, internal span and offset resistors, and 100
.:to 1% resistors, in place of R, and R2'

Absolute maximum ratings are limiting values, applied individually, beyond which the serviceability of the circuit may be
impaired. Functional operation under any of these conditions

The H 1-5618 accepts digital input codes in binary format
and may be user connected for anyone of three binary codes.
Straight binary, offset binary, or ~o's complement binary.
(See operating instructions)

-16.5

4.75

12

n

is not necessarily implied.
2.

15

7.

Using an external op amp with the internal span and offset
resistors. See Operating Instructions.

S.

Specified for all "1 's" or all "O's" digital input.

9.

FSR is "Full Scale Range", i.e., 20V for
10V range; 10V
for ± 5V range, etc. Nominal full scale output current is SmA.

10.

±

After 30 seconds warm-up.

11. See Test Circuit, Figure 3.
5.

See definitions.

6.

These errors may be adjusted to zero using external potentio-

12.

See Test Circuit. Figure 4.

5-25

DEFINITIONS OF SPECIFICATIONS
INTEGRAL NONLINEARITY - Nonlinearity of a D/A converter
is an important measure of its accuracy. It describes the deviation
from an ideal straightline transfer curve drawn between zero (all
bits 0 FF) and full scale (all bits ON).
DIFFERENTIAL NONLINEARITY - For a D/A converter, it is
the difference between the actual output voltage change and the
ideal (1 LSB) voltage change for any two adjacent codes. A Differential Nonlinearity of'± 1 LSB or less guarantees monotonicity;
i.e., the output always increases and never decreases for an increasing input.
GAIN DRIFT - The change in full scale analog output over the
specified temperature range expressed in fractional LSB's, or parts
per million of full scale range per oC (ppm of FSR/OC). Gain error is
measured with respect to +25 0 C at high (TH) and low (TL) temperatures. Gain drift is calculated for both high (TH -25 0 C) and low
ranges (+25 0 C -TL) by dividing the gain error by the respective
change in temperature. The specification is the larger of the two
representing worst case drift.
ZERO DRIFT - The change in a~alog output with all bits OFF
over the specified temperature range expressed in parts per million
of full scale range per oC (ppm of FSR/OC). Zero error is measured
with respect to +25 0 C at high (TH) and low (TL) temperatures.
Zero Drift is calculated for both high (TH - 25 0 C) and low (+25 0 C
-TL) ranges by dividing the offset error by the respective change
in temperature. The specification given is the larger of the two,
representing worst case drift.
SETTLING TIME

Settling time is the time required for the output to settle to within the specified error band for any input code transition. It is

usually specified for a full scale transition. D/A settling time may
vary depending upon the impedance level being driven. A comparator presents a high impedance, while an op amp connected for
current to voltage conversion presents a low impedance. Figure 3a
shows the test circuit used for testing the H1-5618A1B for TS (0 FF)
into a high impedance.
GLITCH

A glitch on the output of a D/A converter is a transient spike resulting from unequal internal ON-OFF switching times. Worst case
glitches usually occur at half-scale or the major carry code transition from 011 ... 1 to 100 ... 0 or vice versa. For example,
if turn ON is greater than turn OFF for 100 ... 1 to 100 ... 0,
an intermediate state of 000 ... 0 exists, such that, the output
momentarily glitches toward zero output. In general, when a
D/A is driven by a set of external logic gates, the unmatched turn
on - turn off times at the gates will add to the glitch problem.
See Figure 4.
POWER SUPPLY SENSITIVITY

Power Supply Sensitivity is a measure of the change in gain and offset of the D/A converter resulting from a change in the +5V or
-15V supplies. It is specified under DC conditions and expressed
as parts per million of full scale range per percent of change in power supply (ppm of FSR/%1.
COMPLIANCE VOLTAGE

When the D/A converter is used without an op amp, it may be
configured for various ranges of voltage at its output. However,
Compliance Voltage is the maximum full scale voltage for which the
converter will comply with its specifications.

OPERATING INSTRUCTIONS
DECOUPLING AND GROUNDING

For best accuracy and high speed performance, the grounding
and decoupling scheme shown in Figure 1 should be used. Decoupling capacitors should be connected close to the HI-5618A1B;
preferably to the device pin. A solid tantalum or electrolytic capacitor in parallel with a smaller ceramic type is recommended.

CONNECTIONS

Unipolar

OUTPUT
RANGE

PIN 5
TO

PIN 7
TO

PIN 8
TO

oto +10V

NC
NC

A
A

NC

0
0
0

NC
A
A

A
NC

Mode

oto +5V

Bipolar

± lOV

Mode

±5V
±2.5V

6

6

BIAS
RESISTOR RB

390.0
330.0
400.0
360.0
390.0

FIGURE 1

UNIPOLAR AND BIPOLAR VOLTAGE
OUTPUT CONNECTIONS

Make connections as shown in the table and Figure 2, for five
standard output ranges:

5-26

"Used in Bipolar Mode only_

The H1-5618A1B accepts an 8 bit digital word in Straight Binary
code. In the bipolar mode this code becomes Offset Binary. Also in
bipolar mode, the MSB may be complemented using an external

inverter to obtain 2's complement code.
outputs for some key input codes:

UNIPOLAR -STRAIGHT BINARY
OV TO +10V OUTPUT RANGE
OIGITAL
INPUT
11 .... .
10 .... .
01 .... .
00 .... .

BIPOLAR - OFFSET BINARY
1: 10V OUTPUT VOLTAGE RANGE
DIGITAL
INPUT

ANALOG OUTPUT
1
0
1
0

FS -1 LSB
X,FS
X,FS -1 LSB
Zero

=9.96094V
=5.00000V
=4.96094V
=O.OOOOOV

UNIPOLAR - STRAIGHT BINARY
OV TO +5V 0 UTPUT RAN GE
DIGITAL
INPUT
11 .... . 1
10 .... . 0
01 .... . 1
00 .... . 0

ANALOG OUTPUT
FS - 1 LSB
X,FS
Y,FS -1 LSB
Zero

=4.98047V
=2.50000V
=2.48047V
=O.OOOOOV

Here are the correct

11
10
01
00

.....
.....
.....
.....

ANALOG OUTPUT
1
0
1
0

+FS-l LSB
Zero
Zero -1 LSB
-FS

=+9.92188V
=+O.OOOOOV
=-0.07813V
=-10.0000V

BIPOLAR - TWO'S COMPLEMENT **
± 10V OUTPUT VOLTAGE RANGE
DIGITAL
INPUT
01 ..... 1
00 ..... 0
11 ..... 1
10 ..... 0

ANALOG OUTPUT
+FS - 1 LSB
Zero
Zero -1 LSB
-FS

=+9.92188V
=+O.OOOOOV
=-0.07813V
=-10.0000V

'.

** Invert MSB with external inverter to obtain
two's complement coding.

Output Accuracy of the HI-5618A1B is affected directly by the reference voltage, since 10(F/S)~4 (VREF/8kn). For precision performance, a stable +10V reference with low temperature coefficient
is recommended, such as HARRIS HA-1610.

5 Jl V/oC and 1nA/OC, respectively. The input reference resistor
(7.9kn) and bipolar offset resistor (3.9kU) are both intentionally
set low by 100 n to allow the user to externally trim out initial
errors to a high degree of precision.

The output current may be converted to voltage using an external
op amp with the internal span and offset resistors, as shown above
in the table. The op amp should have good front end temperature
coefficients. For example, the HA-2600/2605 is well suited to this
application, with offset voltage and offset current tempco's of

For high speed voltage output applications where fast settling is
required, the HA-2510/25 is recommended for settling times better
than 250ns to 1/2 LSB. The HA-5190/95 is recommended for applications requiring settling times less than 150ns. (See Applications).

CALIBRATION

UNIPOLAR MODE1. Apply zero (all O's) input, and adjust R3 for OV output.
2. Apply full scale (alii's) input,and adjust Rl for:
+9.96094 Volts, +10 Volt range
+4.98047 Volts,
+5 Volt range
BIPOLAR MODE1. Short the op amp output to its inverting input, then adjust
R3 for OV output. Remove the short.
2. Apply negative full scale (also called bipolar offset): All
O's for offset binary; 1000 .... for 2's complement. Adjust
R2 for output voltages as follows:
-10 Volts,
±10 Volt Range

-5 Volts,
-2.5 Volts,

± 5 Volt Range
±2.5 Volt Range

3. Apply positive full scale (all l's for offset Binary; 0111. '"
for 2's complement) Adjust R1 for output voltages as follows:
+9.92188 Volts,
± 10 Volt Range
+4.96094 Volts,
i5 Volt Range
+2.48047 Volts,
±2.5 Volt Range
4. Apply zero input (1000.... for offset Binary; 0000 ....
for 2's complement). Output should be zero volts. Any
error is due to nonlinearity in the DAC, and cannot be
nulled without disrupting the calibration in steps 2 and 3.

5-27

TEST CIRCUITS
SETTLING TIME

Turn-off settling time (TS(OFF)) is somewhat longer than TS(ON)
for the HI-5618. Typical TS(OFF) performance is shown in Figure
3C, using the circuit of Figure 3A.
Refer to Figure 3B; Settling time following turn-off equals TX
plus TO. The comparator delay TD may be measured at lmV/cm,
using a Tektronix 7A 13 differential ~omparator or equivalent.
Then, TX is easily measured in a short procedure:
•

Adjust delay on generator # 2 for TX approximately 1101 s

•

Switch the LSB to +5V (ON).

OUT

®

SYNC
PULSE
IN
GENERATOR
=#1
TRIG
_ _ _ _ _..... OUT

HI-5618

18

14

"'100kHz

13

•

DVM reads -1 LSB.
-1/2 LSB.

•

Switch the LSB to P (pulse); COMPo OUT pulse disappears.

•

Reduce generator#2 delay until COMPo OUT pulse reappears;
adjust delay for "equal brightness".

101

Measure TX from scope. (Any overshoot will be less than
1/2 LSB, so it is not necessary to examine the other side of the
envelope, i.e. final value plus 1/2 LSB.l

PULSE
GENERATOR
=#2

Adjust VLSB supply so DVM reads

OUT

©

8

16

...f"lJL

Adjust the VLSB supply for 50 percent triggering at COMPo
OUT (equal brightness).

5

17

15

•

2k

':'

3.9k

7 NC
2k
COMPARATOR
OUT

12
P
+5V--o

1

11
LSB
196

DVM

+

VLSB
SUPPLY

Figure 3A

+3V

®

~~50%

~

OV

®
(TURN OFF) -400mV
TX+3V

©

DIGITAL
INPUT

OV

OV

rI

DAC
OUTPUT

1/2 tSB
i--TD=COMPARATORDELAY

l

COMPo
STROBE
/3QUALBRIG HTNESS"

+3V

lJ

@
OV

Figure 38

5-28

COMPo
OUT

TEST CIRCUIT (Continued)
1 LSB

T(OFF) SETTLING TIME
(FULL SCALE TO ZERO TRANSITION)
+250C

1/2 LSB

1/4 LSB
118 LSB
1/16 LSB

50

75

100

125

150

175

200

225

250

NANOSECONOS

Figure 3C

OUTPUT GLITCH MEASUREMENT
+5V

~1

+5V

LSB

-=-.--.:->-.....---,.....:-.-L

T

4Vro

ov-..J

L
lOUT
(Zo=

soon)

I

I

LSB

30PF

II

* ADJUST 500nTRIMMER SO THAT INPUT SIGNALS
CROSS THEIR RESPECTIVE SWITCHING THRESHOLDS
AT THE SAME TIME.
Figure 4

APPLICATIONS
HIGH SPEED VOLTAGE OUTPUT
HI-5618

+5V~_ _ _ _ _ _...,

+15V

> + - - + -......OVO

.--ooIV'V'-I-+-_<20k

-15V
MATCHED DUAL N-FET,
MICRO POWER SYSTEMS MP-835
OR EQUIVALENT
• NOMINAL VALUE. SELECTED FOR OPTIMUM STEP RESPONSE.

5-29

HI-5712/5712A

II HA.RRIS
FEATURES

DESCRIPTION

• MICROPROCESSOR COMPATIBLE
• CONVERSION TIME
•
•
•
•
•
•
•
•

High Performance
12 Bit Analog to
Digital Converter

10~sec

MAX
OVER TEMP.
NO MISSING CODES OVER TEMPERATURE
INTERNAL +10V REFERENCE
INTERNAL CLOCK WITH EXTERNAL
OVERRIDE CAPABILITY
SERIAL OUTPUT
TTL/CMOS COMPATIBLE
TRISTATE PARALLEL OUTPUTS
40 PIN DIP
MIL-STD-883 PROCESSING AVAILABLE

APPlICA TlONS
• MULTI-CHANNEL DATA ACQUISITION
SYSTEMS
• STATUS MONITORING SYSTEMS
• PROCESS CONTROL SYSTEMS
• INSTRUMENTATION
• HIGH RELIABILITY DAS's

PINOUT

The H1-511215112A is a 12-bit successive approximation analog-to-digital
converter (ADC) intended for high-speed, high-performance data conversion
applications.
An 8 p.s conversion time for an accurate 12 bit conversion with
low gain and offset temperature coefficients are among its many features.
Numerous functions can be software controlled to meet a variety of AOC
requirements.
The highly flexible input design accepts user programmed unipolar and bipolar
inputs of: 0 to +10V, 0 to +20V, ±5V and ±10V full scale signal levels. The
internal precision +10V reference delivers up to 10mA of output current with
ultra high temperature stability. This reference is intended for biasing the
ADC reference input, although other configurations can be implemented .
A remote sense line is provided for applications requiring usage of the precision
reference elsewhere in the system.
The output code select line and the short cycle control inputs are latched internally for microprocessor compatibility and provide selection of either binary
or 2's complement output code, and resolution of 6, 8, 10 or 12 bits, respectively. A flexible interface is provided for 8,12 and 16 bit systems via the chip
select line and the word length control pins. The latter allows independent
tri-state enabling of parallel output bits 1-8 and 9-12. A serial data output line
is provided for applications requiring remote data transmission.
The HI-5712/5712A is manufactured with hermetically sealed lead less chip
carriers (LCC's) mounted to both sides of a multi-layer ceramic substrate
which results in a compact 40 pin dual-in-line package. The HI-5112A is
intended for military, industrial and instrumentation applications. MIL-STD883 class B and high reliability commercial grades are both available as standard,
products.

FUNCTIONAL DIAGRAM
Section 11
for Packaging

20V

FS

lOV

BIPOLAR

VREF

FS

OFFSET

IN

VREF VREF

OUt SENSE

Vps'
BIPOLAR

4

OFFSET
ZERO
ADJ

NC~ 2~

n--r-t~~~VPSRLS

ANALOG GND

~3.

DIGITAL GND
VLOGIC

ANALOG

PWR GND

:~A:_~~

8

ENABLE
BIT1-3
SERIAL

CON'L..

MSBlMSB
SELECT

eVB

SHORT

CLOCK

eVA

CL~~
SI112
(L5111

ENABLE

START

OUT

SHORT

ZERO ADJ.

CHIP

CHIP

ENABLE~L----L.l--LJL..L-J...L-Ll...w--L------,
STATUS

STARTCQNV.

IN

CLOCK IN

13

Bin
IMSS)

CLOCK OUT
SERIAL OUT

MSBIMsiSEl
SHORley A
SHORT CV B

5-30

;--C:Q:;+.:;t:t+';:Qr;;:t=+,;+';tQ~--_-.J

SPECIFICA TIONS
ABSOLUTE MAXIMUM RATINGS
Power Supply Inputs
Vps+
Vps-

(NOTE

11
Power Oissipation (Pel) 2 Watts
Operating Temperature Range
HI-S712-2, HI-S712A-2
HI-S712-S,HI-S712A-5
HI-S712-7,HI-S712A-7
HI-S712-8,HI-S712A-8
Storage Temperature Range

+20V
-20V
+10V
OV, Vps+
OV, Vps+
-IV, VLOGIC

VLOGIC
VREF IN (Pin 37)
VREF SENSE (Pin 39)
Oigital Inputs

SsoC to +12S oC
DoC to +75 0 C
DoC to +7S oC (Hi Rei)
-SSoC to +12S oC (Hi Rei)
65 0 C to +150 0 C

ELECTRICAL CHARACTERISTICS
(TA=+25 0 C, Vps=+ISV, Vps-=-15V, VLOGIC=+5V, VREFln=lnternaIVREF,
Full Scale = +10V, Conversion Speed = 9tJ.s TYP (Internal Clock), 12-BIT Conversion, Unless
otherwise noted)
HI-5712A-2 HI-S712-2
HI-5712A-8 HI-S712-8

I

I

PARAMETER
RESOLUTION
NONLINEARITY

HI-S712A
HI-S712

DIFFERENTIAL
NONLINEARITY

HI-S712A
HI-S712

INHERENT QUANTIZATION
ERROR
UNIPOLAR OFFSET ERROR (Note 2)
(Adjustable to Zero)
BIPOLAR OFFSET ERROR (Note 2)
(Adjustable to Zero)
GAIN ERROR (note 2)
(Adjustable to Zero)
AOJUSTMENT RANGE
UNIPOLAR OFFSET
BIPOLAR OFFSET
GAIN
TEMPERATU RE STABILITY
(With Internal VREF)
UNIPOLAR OFFSETHI-S712A
DRIFT
HI-5712
BIPOLAR OFFSET HI-5712A
DRIFT
HI-5712
GAIN DRIFT
HI-5712A
H1-5712

TEMP
Full
+25 0 C
Full
+25 0 C
Full
+2S oC
Full
+25 0 C
Full

MIN

I

TYP

I

MAX

HI-S712A-S H1-5712-S
HI-5712A-7 HI-5712-7
MIN

I

TYP

12

±1/4
. ±1/4
±1/4
±1/2
±1/4
±1/4
±1/4
!1/2

I

MAX

UNITS
BITS
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB

±1/2
±1/2

:!:1I4

12
±1/2
:!:1I2

±1/2
±1

:!:1/4

±1/2

:!:1/2

±1

±1/4
±1/4
:!:1/4
:!:1/2

:!:1/2

±1/4

±1/2
±1/2

±1/2

±1/2
±1/2
±1
±1
NO MISSING CODES GUARANTEED OVER TEMPERATURE

±1/2

Full

±.lI2

LSB

+25 0 C

.3

.6

.3

.6

%FSR

+25 0 C

.3

.6

.3

.6

%FSR

+25 0 C

.1

.3

.1

.3

%FSR

.3

%FSR
%FSR
%FSR

+25 0 C
+2S oC
+2S oC

Full
Full
Full
Full
Full
Full

±1
+1

±2
:!:2

±1
±1
.3

+2
:!:2

±2
±5
±2
ppm
±5
:t15
±4
±4
±15
ppm
±4
±4
±10
±ID ppm
±2S
±25 ppm
±8
±8
ppm
±5
.±5
±ID
±ID
±2D
.:tID
±2D ppm
±ID
NO MISSING CODES GUARANTEED OVER TEMPERATURE

I

II

FSR/oC
FSR/oC
FSR/oC
FSR/oC
FSR/oC
FSR/oC

5-31

SPECIFICATIONS (Continued)

H1-5712A-2/-B
HI-5712-2/-B
PARAMETER
CONVERSION SPEED (Internal Clock)
12BIT
10 BIT
B BIT
6 BIT
MAXIMUM CONVERSION SPEED AT
12 BITS WITH EXTERNAL CLOCK
(Note 3)
ANALOG INPUT CHARACTERISTICS
INPUT VOLTAGE RANGE
UNIPOLAR
BIPOLAR
INPUT IMPEDANCE
10V FS (PIN 6)
20V FS (PIN 5)
VREF IN (PIN 37)
ANALOG OUTPUT CHARACTERISTICS
VREF OUTPUT VOLTAGE
VREF OUTPUT CURRENT
VREF OUTPUT
HI-5712A.
HI-5712
TC
DIGITAL INPUT CHARACTERISTICS
INPUT VOLTAGE (Note B)
lOGIC 1
LOGIC 0
INPUT CURRENT (Note B)
LOGIC 1 (VCC)
LOGIC 0 (GND)

II

ETERNAL CLOCK (Note 3)
DIGITAL OUTPUT CHARACTERISTICS
OUTPUT VOLTAGE
LOGIC 1 IOH = -BOO A
LOGIC 0
IOL = +3.2mA
OUTPUT CURRENT
LOGIC 1
VO = 3.5V
VD = .4V
LOGIC 0
DIGITAL INPUT TIMING CHARACTERISTICS
CHIP ENABLE TO START CONVERT tcd
START CONVERT PULSE LOW
tscl
START CONVERT PULSE HIGH
tsch
ts
CONTROL SETUP TIME
th
CONTROL HOLD TIME
~LOCK INPUT LOW .
tpwl
CLOCK INPUT HIGH
tpwh
CLOCK INPUT PERIOD
tcl
ENABLE l-B,9-12 PULSE WIDTH
tern

5-32

TEMP

HI-5712A-5/-7
HI-5712-5/-7

TYP

MAX

"
"
"

9.0
S.8
5.6
4.4

10.0
B.5-

Full

6.5

MIN

+25 0 C

MIN

7.0
5.4

TYP

MAX

UNITS

9.0
6.B
5.6
4.4

10.0
B.5
7.0
5.4

f.lS
f.ls
f.lS
J.l.s

6.5

J.l.s

10
20
:t5
.:tl0

:t5
:tl0

V
V
V
V

Full
Full
Full
Full

10
20
:t5
:tl0

:t5
tl0

Full
Full
Full

1.S
3.2
6.4

2
4
B

2.4
4.B
9.6

1.6
3.2
6.4

2
4
B

2.4
4.B
9.6

Kn
Kn
Kr1

+25 0 C
Full
Full
Full

9.970
10

10.000

10.030

9.970
10

10.000

10.030

:tl0
:tl0

:t15
:t15

:tID
:tl0

±15
.:t15

V
rnA
ppm FSR/OC
ppm FSR/OC

Full
Full

3.3

2.7
1.2

.B

2.7
1.2

.B

V
V

Full
Full

-25

0
-200

+25
-400

0
-200

+25
-400

Full

3.3

-25

2.5

Full
Full

3.5
.2

4.0
.4

3.5

Full
Full

-BOO
3.2

-1000
4.0

-BOO
3.2

Full
Full
Full
Full
Full
Full
Full
Full
Full

50
100
50
100
100
125
150
400
100

50
100
50
100
100
125
150
400
100

4.0
.2
-1000
4.0

f.lA

2.5

f.lA
MHz

.4

V
V
f.lA
rnA
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec

SPECIFICA TIONS (Continued)

I ..

PARAMETER

I TEMP

HI-5712A-2/-8
H1-5712-2/-8
MIN
TYP
MAX

I

I

HI-5712A-5/-7
HI-5712-5/-7
TYP
MAX
MIN

UNITS

40
60
70

50
100
100

nsec
nsec
nsec

100
50

200
150
75

500
200
100

nsec
nsec
nsec

I

I

I

DIGITAL OUTPUT TIMING CHARACTERISTICS (See Figure 6)
toe
THREE STATE ENABLE DELAY
tod
THREE STATE DISABLE DELAY
START CONVERTTO STATUS DELAYtsd
START CONVERT TO CLOCK OUT DELAY
tscd
CLOCK TO SERIAL OUT DELAY
tpsd
LAST CLOCK TO STATUS DELAY
tscdt
PARALLEL DATA TO
tds
STATUS DELAY
LAST SERIAL BIT TO
STATUS DELAY
tda
CLOCK INPUT TO CLOCK
OUT DELAY
tdcl
PARALLEL DATA OUTPUT CODES
UNIPOLAR (Note 4)
BIPOLAR (Note 4)

Full
Full
Full

VLOGIC
Ips+
IpsILOGIC
POWER SUPPLY SENSITIVITY (Note 6)
Vps+ =+13.5V to +16.5V
Vps- =-15V, VLOGIC =+5V
UNIPOLAR OFFSET
BIPOLAR OFFSET
GAIN
Vps- =-13.5V to -16.5V

50
100
100
500
200
100

Full
Full

100
50

200
150
75

Full

50

75

50

75

nsec

Full

50

75

50

75

nsec

Full

25

50

50

nsec

+15
-15
+5
27
42
4.5

+16.5
-16.5
+5.25
35
50
15

V
V
V
rnA
rnA
rnA

5
4
3

ppm of
FSRI

25

Positive True Binary
Positive True Offset Binary
Positive True Two's Complement Binary
Positive True NRZ Code

SERIAL DATA OUTPUT CODE
POWER SUPPLY REQUIREMENTS (Note 5)
Vps+
Vps-

40
60
70

Full
Full
Full
Full
Full
Full

+13.5
-13.5
+4.5

+15
-15
+5
27
42
4.5

+16.5
-16.5
+5.5
35
50
15

+13.5
-13.5
+4.75

2
2
1

5
4
3

2

2
2

2

1

5
4
3

1

5
4
3

±5

±10

±5

±10

2
1

II

I

%~P.S.

Vps+ =+15V, V lOGIC =+5V
UNIPOLAR OFFSET
BIPOLAR OFFSET
GAIN
VLOGIC =+4.5V to +5.5V
Vps+ =+15V, Vps- =-15V
CONVERSION SPEED (12 Bit with
Internal Clock)

2

%

5-33

NOTES: 1.
2.
3.
4.
5.
6.
7.
B.

Absolute maximum ratings are limiting values, applied individually, beyond which the serviceability of the
circuit may be impaired. Functional operation under any of these conditions is not necessarily implied.
See Fi~ure 2 for connections. The initial errors are adjustable to zero by using external trim potentiometers
as shown in Figure 3, and 4.
The HI-5712A will operate at these speeds (for 12 bit conversion), but parametric performance is not guaranteed.
See operating instructions for details.
After 60 seconds warm-up.
See definitions.
These terminals will be used in the future for additional functions. Do not make connections to these pins in
your system.
TTL compatibility guaranteed.

PIN FUNCTIONS AND DESCRIPTIONS
DESCRIPTION

PIN

SYMBOL

1
2
3
4

VpsNC
NC
BIPOLAR
OFFSET

-15V Power Supply Terminal
No Connection See Note 7
No Connection See Note 7
Connect to VREF for Bipolar Input
Mode. See Operating Instructions
for Details.

5
6
7

20V FS
10V FS
ANALOG
GND
ENABLE
BIT9-12

20V Full Scale Analog Input
10V Full Scale Analog Input
Analog Power Supply Return

8

9

ENABLE
BIT 1-8

10

SERIAL
OUT

11

SHORT
CY B
SHORT
CY A

12

Output "Three State" Control. An
Input "0" Enables Bits 9 through
12, whereas a "I" Switches these
Bits to a High Impedance State.
Output "Three State" Control. An
Input "0" Enables Bits 1 through
8, whereas a "I" Switches these
Bits to a High Impedance State.
NRZ Serial Data Output.
To be used in Conjunction with
Clock Out for Remote Data
Transmission
See Description for Pin 12

6
8

10
12

5-34

SYMBOL

13

CLOCK
OUT

SAR Clock Output. Used for
Decoding Serial Oilt Data

14
15
16
17
18
19
20

Output Data Bit (LSB)
Output Data Bit
Output Data Bit
Output Data Bit
Output Data Bit
Output Data Bit
Digital Power Supply Return

23
24
25
26
27

BIT 12
BIT 11
BIT 10
BIT9
BIT 8
BIT 7
DIGITAL
GND
VLOGIC
BIT 6
BIT 5
BIT4
BIT 3
BIT 2
BIT 1

28
29

NC
CLOCKIN

30

MSB/MSB
SEL

No Connection. See Note 7.
An External Clock Signal Applied
to this Input Overrides the
Internal Clock.
Digital Input Pin. A "I" Applied
to this Terminal Selects a Straight
Binary or Offset Binary Output
Code. A "0" Inverts the MSB to
Yield a 2's Complement Binary
Output Code.

21

22

Digital Inputs Applied to short
cycle A and B selects a conversion
of 6, 8, 10, or 12-bits:
BITS

SHORT CY A SHORT CY B
0
0
1
1

0
1
0
1

DESCRIPTION

PIN

31

START CONV

32

STATUS

+5V Power Supply Terminal
Output Data Bit
Output Data Bit
Output Data Bit
Output Data Bit
Output Data Bit
Output Data Bit (MSB)

Digital Input Pin. A High to Low
Transition Initiates the ADC
Conversion Cycle.
Digital Output Pin. A "I"
Indicates that the ADC is Busy,
While a "0" Denotes that Conversion is Completed and Data is
Ready for Retrieval.

PIN FUNCTIONS AND DESCRIPTIONS
PIN

SYMBOL

33

CHIP
ENABLE

34
35

RLS
ZERO ADJ

DESCRIPTION
Digital Input Pin. A "1" Forces
the Output Data, Serial Out and
Status Terminals to a High Impedance State and the AD C is
Disabled. A "0" Enables these
ADC Functions.
Reference Low Sense.
External Zero Adjustment Pin,
See Operating Instructions for
Details.

PIN

SYMBOL

36
37
38

NC
VREF IN
VREF OUT

39

VREF SENSE

40

Vps+

DESCRIPTION
No Connection. See Note 7.
+10V Reference Input to ADC.
Internal +10V Reference Output,
Normally Connected to VREF IN
(Pin 37).
Internal +10V Reference Sensing
Terminal, Normally connected to
VREF Out (Pin 38). See Operating Instructions for Details.
+15V Power Supply Terminal.

APPLYING THE HI-571215712A
OPERATING INSTRUCTIONS
Conventional ADC systems provide maximum performance
when the analog and digital ground lines are tied together
at the ADC terminals. This minimizes analog interference
due to digital switching noise. For optimum performance,
this external grounding procedure should be followed in
HI-5712/5712A installations to reinforce the unit's internal
analog-to-digital ground connections. Under no circumstances should the Reference Low Sense (R LS) terminal
(Pin 34) be connected to system ground.
In practice, the Reference Low Sense (RLS) terminal (Pin
34) normally is connected to zero adjust (or error amplifier)
input terminal (Pin 35), either directly or through an appropriate resistor network. See figures 3 and 4.
On the HI-571215712A substrate, the power supply lines
to each active component are bypassed to ground
with 0.0111 F chip capacitors for high frequency noise rejec-

tion.
For best accuracy, the grounding and decoupling
schemes shown in Figures 3 and 4 are recommended. The
1011 F bypass capacitors shown should be connected as
close as possible to the HI-571215712A, preferably at the
device pin.
For applications where usage of potentiometers is highly
undesirable, the trim pots shown in Figures 3 and 4 can
either be deleted or replaced by precision fixed resistors.
(Oelete R3 and R4; replace R1 with 25 ohms). When
precision fixed resistors are used, the initial offset error
and gain error contributions are as specified in page 2.

II
I

NOTE: The HI-571215712A may latch up if the device
is enabled before applying power. Disabling the device
following power turn on will remedy this situation. Care
supplies do not excessively overshoot their final value during
turn on.

CONTROL AND INTERFACE
The HI-5712/5712A features a versatile set of controlling
functions which allows a wide variety of applications, including microprocessor bus interfacing.

end of the conversion cycle the status line will be set to low
to signify that the data is ready at the tri-state buffers. The
various timing relationships are shown in Figure 1.

When the chip enable is set to low, the internal registers
are enabled, and the output data lines can be enabled via
the output enable control lines.
The conversion cycle
is initiated at the falling edge of the start conversion pulse.
At this time, the MSB/MSB Select, Short Cycle A, and
Short Cycle B control information is latched into the internal
registers. The status line is also forced into an active high
state indicating that a conversion is taking place. At the

There are two distinct modes of operation, namely, continuous conversion and single step conversion. Continuous
conversion can be easily achieved by connecting the Status
line to the Start Convert pin. In this application, an indecision state may occur during the initial power-on conditions. Normal operation is restored by pUlsing the chip
enable pin to logic high for a period greater than 100 ns.

5-35

APPLYING THE HI-511215112A

CHIP ENABLE

START CONVERT

STATUS

CLOCK
OUTPUT ---1-"1

SERIAL OUT
ENABLE 1-8
ENABLE 9-12

DATA OUT
MSBIMSii
SHORT CY A,B

EXTERNAL
CLOCK INPUT
(IF USEDI

•

FIGURE 1. HI-671216712A TIMING DIAGRAM

+5V

REMOTE DATA TRANSMISSION

4.7k
2B

The Serial Data Out is mainly used for rem ote data transmission, where only a limited number of wires are available.

1

In order to minimize transmission error, the negative-going
edge oftheclock should be used to clock data into the remote
shift register. The parallel data will be valid once the status
line returns to low. The clocking scheme is shown in
Figure 1.

A
74LSI64

Serial Output is bit by bit (MSB first, LSB last! in a NRZ
(nonreturn-to-zero) format. It changes state only at the
positive going edges of the Clock Out, and remains valid
during the whole clock period. Parallel data can be constructed by clocking the serial data into a receiving shift
register,

_

e ~
CLEAR

6

BIT1

5

BIT2

4

BIT3

3

BIT4

Ts

2~131
B

,.... SERIALOUT
SIGNALS
TO/FROM
HI-5712/
5712A

CLOCK OUT
STATUS

I
. -f
74LSOO

STARTCONV.

1

A'
74LSI64

8
CLEAR

'--y9

BIT5

12

BIT6

11

BIT7

10

BITe

6

BIT9

5

BIT 10

4

BIT 11
BIT12

3
"

PARALLEL
DATA
OUT

(LSB)

START CON V'LJ"

FIGURE 2. DECODING SERIAL DATA OUT

5-36

(MSB)

INPUT CONNECTIONS AND CAl/BRA TION PROCEDURES
Hi-5712/5712A CALIBRATION CHART
ANALOG
MSBIMSB OFFSET ADJUST ADJUST R3 FO R
GAIN ADJUST
ADJUST Rl FOR
INPUT
R2 BIAS SELECT ANALOG INPUT DITHER BETWEEN ANALOG INPUT DITHER BETWEEN
LSB
CODES
WEIGHT
CONNECTION RESISTOR PIN 30
VOLTAGE
CODES
VOLTAGE

OPERATING
MODE

UNIPOLAR STRAIGHT
BINARY
OV to +10V

10VFS
PIN 6

ssm

HIGH

+1.22mV

0000 0000 0000
0000 0000 0001

+9.99S3V

111111111110
111111111111

2.44mV

UNIPOLAR STRAIGHT
BINARY
OV to +20V

20VFS
PIN 5

aoon

HIGH

+2.44mV

0000 0000 0000
000000000001

+19.9927V

111111111110
111111111111

4.88mV

BIPOLAR OFFSET
BINARY

10VFS
PIN S

580n

HIGH

-4.9988V

0000 0000 0000
000000000001

+4.9963V

111111111110
0111 11111111

2.44mV

BIPOLAR OFFSET
BINARY
-10V to +10V

20V FS
PIN 5

6S7H

HIGH

-9.9976V

0000 0000 0000
000000000001

+9.9927V

11111111 1110
111111111111

4.88mV

BIPOLAR 2's
COMPLEMENT
-5V to +5V

lIiv FS

580n

LOW

-4.9988V

1000 0000 0000
1000 0000 0001

+4.9963V

011111111110
0111 11111111

2.44mV

BIPOLAR 2's
COMPLEMENT
10V to +10V

20V FS
PIN S

ssm

LOW

-9.9976V

1000 0000 0000
1000 0000 0001

+9.9927V

011111111110
011111111111

4.88mV

-5V to +5V

PIN 5

CALIBRATION PROCEDU RE- Refer to Calibration Chart and to Figures3 'and 4 for appropriate analog input
connections, value of bias resistor, and MSB/MSB select.

II

STEP 1
OFFSET ADJUSTMENT
Set analog input to the appropriate value for offset adjustment.
Adjust R3 for dither between codes shown in calibration chart.

I

•
•

STEP 2
GAIN ADJUSTMENT
Set analog input to the appropriate value for gain adjustment.
Adjust R1 for dither between codes shown in calibration chart.

•
•

NOTE: This calibration procedure insures that the transfer characteristic produced by connecting the midpoints
of all quantization intervals passes through the origin.

OVTO+2DV

ANALOG
INPUTS

ovTO +1OV

*
ADJ

ADJ

.r

8 tOV
FS
4 BIPOLAR
OFFSET

GAI:~
'1".4 600
OFFSET

5 20V
FS

Rt

lOOKS!

~
BIAS

RJ

20kll

-15V

39 ~::tE
38 VREF
OUT
37 VREF
IN

HI-5712

CHIP
ENABLE 33

~:[~g~
CL~~~

30
13

SERIAL 10
OUT
STATUS 32

s~~:~

31

ENABLE

BITl-8

9

35 ZERO
AOJ
34 RLS

~

I-<"v

t---t
t---t

BITg-12

~

r---<

-5VTO+5V

6

toV

OFF!~

r;;s

4

FS

BIPOLAR
OFFSET

25<1

r- 39 ~rJfE

G:~~c:~

~~iF

1 .. '---

37

~NREF

+15V

8r---<

50S!

1

1OOk
"

~:kn

~
BIAS

EN;BH~: 33
M::~30
CLOCK

OUT 13

SERIAL 10
OUT

--+

s~~:~

--<

ENABLE
81T1-8

31

or--<
BIT 1-8

AOJ
34 RLS

r---<

!---+
!---+

STATUS 32

35 ZERO

_15V

r--<

ENABLE
BIT 9-12

.~

8f---<

+15V

'::l;)' '*

40 Vfs+

8IT9-12

-15V
10jJF

20V
FS

38

+15V
ANAL.OG
POWER
SUPPL.Y

I;

*

BIT1-B

ENABLE

·lOVTO+l0V

1

VPs-

7 ANALOG

*'l ___P~~~:

VL.OGIC 21
DIGITAL 20

'5V

*'-"1

DIGITAL
POW••
SUPPLY

G~~ ___ (1

____

FIGURE 3. UNIPOLAR INPUT CONNECTIONS
- STRAIGHT BINARY OUTPUT CODE

I

ANALOG
POWER
SUPPLY

10P~~

-15V

1011F:t;)_

40VPS+

BIT 9-12

1 VPS_

VLOGIC 21

7 ANALOG

DIGITAL 20

*'L ___~~G~:

____

.5V

T'~F

DIGITAL
POWER
SUPPLY

J

~N: ___ {~

FIGURE 4. BIPOLAR INPUT CONNECTIONS

5-37

APPLYING THE HI-5712/5712A
DEFINITIONS
Least Significant Bit (LSB) - The LSB of an Analog-to-Digital Converter (ADC) is defined to be the digital output bit carrying
the lowest numerical weight ()t,n); or the Analog input shift associated with this bit (FSR/2 n) which is the smallest possible Analog
input step that can be resolved.
Most Significant Bit (MSB) - The Digital output bit carrying the highest numerical weight (y,); or the Analog input shift associated
with this bit. In a Binary ADC the MSB indicates the Analog input reaches its )t, FSR.
Resolution - An indicati on ofthe number of possible analog input levels an ADC will resolve. Usually it is expressed as the number
of output bits. For example, a 12 bit Binary ADC can have 212 = 4096 possible output codes and it has a resolution of 12 bits.
Nonlinearity (Linearity Errorl - A measure of the deviation of each individual code from an ideal straight line transfer curve
drawn between zero and full scale. The deviation of a code from the ideal straight line is measured from the middle of each
particular code.
Code Width - A fundamental quantity for ADC specifications, it is defined as the range of Analog input values which produce a
given digital output code. The ideal value of a code width is equivalent to FSR/2 n, where n is the number of bits.
Differential Nonlinearity - A measure of the deviation between the actual code width of an ADC from the ideal code width. A
specification which guarantees no missing codes requires that every code must have a non-zero width.
Quantizing Error (or uncertainty) - The uncertainty introduced by partitioning the Analog continuum into 2n discrete ranges
for n-BIT conversion. The Analog values within a given quantum are normally assigned to the nominal midrange value, represented by the same digital code and therefore, a quantization uncertainty of .!.:.)t, LSB is inherently associated with a given
resolution.
Unipolar Offset Error - A measure of the difference between the ideal (+)t,LSB) and the actual analog input level required to
produce the first output digital code transition (00- - -0 to 00- - -01). It is usually expressed in percent of full scale range
(%FSR).
Bipolar Offset Error - A measure of the difference between the ideal ()t,FSR -)t,LSB) and the actual analog input level required
to produce the major carry output digital code transition (from 011- - -0 tol00- - -0). It is usually expressed in percent of full
scale range (%FSR).

II

Gain Error - The gain of an ADC is defined as the difference between the analog input levels required to produce the first and the
last digital output code transitions. Gain error is a measure of the deviation between the actual gain from the ideal gain of
FS-2LSB. It is usually expressed in percent of full scale range (%FSR).
Unipolar Offset Drift - A measure of the change in unipolar offset over the specified temperature range expressed in parts per
million of full scale range per oC (PPM of FSR/oC).
Gain Drift - A measure of the change in gain (with offset error removed) over the specified termperature range expressed in
parts per million of full scale range per 0C (PPM of FSR/oC ).
Bipolar Offset Drift - A measure of the change in bipolar offset 'over the specified temperature range expressed in parts per
million of full scale range per oC (PPM of FSR/OC).
Power Supply Sensitivity - A measure of the change in gain, offset, and conversion speed of the ADC resulting from a change in
supply Voltages. It is expressed in parts per million of full scale range per percent of change in power supply voltages (PPM of
FSR/%).
Conversion Speed - The measure of how long it takes an ADC to arrive at the proper output code. It is the time between the
edge of the digital command that starts conversion and the edge of the status line signal which signifies that the conversion is
completed.
Throughput Rate - For SAR-Types, ADC's throughput rate is defined as the total number of conversions in a given time period.
Usually, it is expressed in conversions per second although, the term Hertz is generally accepted.

5-38

ml~RIS

HI-5900
Analog Data Acquisition
Signal Processor

FEATURES

DESCRIPTION

•

INPUT OVERVOLTAGE PROTECTION

•

50kHz THROUGHPUT

•

12-BIT ACCURACY

•

OUTPUT TRACK/HOLD AMPLIFIER

•

ZERO OFFSET ADJUSTMENT

•

DIFFERENTIAL INPUT CHANNELS

•

SOFTWARE CONTROLLED GAIN AND
CHANNEL SELECT

•

85dB CMRR

•

COMPACT 32 PIN DIP

•

MIL-STD-883 SCREENING AVAILABLE

The H1-5900 comprises "front end" components of a data acquisition system
including an eight channel differential multiplexer, programmable gain instrumentation amplifier (PGA), and Track and Hold amplifier. Adding a timing
circuit and one A to D converter yields a complete data acquisition system. A
50kHz channel-to-channel throughput rate is achieved when the HI-5900
is used with a fast 12 bit A to D converter such as HAR RIS H1-5712.
Each output line of the input multiplexer is buffered by a high-quality noninverting amplifier. This isolates each line from source resistances external to
the 5900, preserving the high CM RR of the instrumentation amplifier block.
Also, the buffers provide a high input impedance for each channel.
The PGA, which includes an op amp, a monolithic resistor network and a four
channel differential multiplexer, offers precision gain values of 1,2,4, and 8.
The voltage gain is selected by a two bit digital word. The output of the PGA
drives the Track and Hold amplifier, and the ground side of the PGA is isolated by a buffer amplifier to maintain a high CM RR.
The output Track/Hold amplifier is a monolithic device, internally connected
for non-inverting unity gain. In the sample mode is operates as a high performance buffer amplifier. With an external holding capacitor, it may be
switched to HOLD with an aperture delay of 50ns and 10pC of charge transfer.

APPlICA TIONS
•

HIGH PERFORMANCE DATA ACQUISITION

•

MILITARY SYSTEMS

II

The packaging technique involves monolithic chips mounted in leadless chip
carriers (LCC's) and soldered to both sides of a multilayer ceramic substrate.
Each LCC may undergo reliability screening such as MIL-STD-883, Method
5004/Class B, before assembly on the substrate. The resulting package is a
compact 32 pin DIP.
The H1-5900 is offered as a high performance front-end section for military
and industrial data acquisition systems. It is designed for interface with computers and is well suited for high-rei applications.

PINOUT

FUNCTIONAL DIAGRAM
Section 11 for Packaging

TOP VIEW

CHAN
OUT
SELECT EN A

A2
NIC
GND
lB
2B

31
30
29
28

3B
48
58
6B

26
25
24

18
8B

+v

OUT A
aUTB

VREF lOW
T/H CONTROL

27

10
11
12
13

"

15
16

23

Al
AO
EN
lA
2A
3A
4A

CHAN11~lWtjgl~§
CHAN2~

5A

T/H
OUT

6A
7A
8A

22
21

-v

20
19
18
11

Go
G,
T/H OUT
CH

GAIN
SELECT

CHANa
OUT
•

0-0- - - - - '

+vo--GNDo---

-v 0 - - -

5-39

SPECIFICA TIONS
ABSOLUTE MAXIMUM RATINGS (Note 11
40V

Voltage Between V+ and V- Terminals
Digital Input Overvoltage (Multiplexers)
VSuppl y (+)
VSuppl y I-l

Output Current
Operating Temperature Range
HA-5900-5
HA-5900-2
Storage Temperature Range
Internal Power Dissipation
T/H Control Input

+4V
-4V

Analog Input Overvoltage
VSuppl y (+) +20V
VSuppl y I-l -20V

ELECTRICAL CHARACTERISTICS Unless otherwise specified: Vs =±15V; CH
PARAMETER
ANALOG INPUT CHAR.,
EACH CHANNEL
. Offset Voltage

Bias Current
Offset Current
Common Mode Range
Common Mode Rejection Ratio
(VCM =:tIOV) Any Gain
DIGITAL INPUT CHAR.
Multiple •• r Digital Input Current
(H igh or Low)
Track/Hold Digital Input Current
VIN::>'0.8V
VIN ~4.0V

E
I

TRANSFER CHARACTERISTICS
Small Signal Bandwidth (Gain =1)
Full Power Bandwidth (Gain = I,
Vo =~10V)
Crosstalk (Sample Mode, Gain =8,
1kHz 20VP -P Input on all but
Selected Channel)
"Off Isolation (Hold Mode, Gain = I,
1kHz 20V P-P Input)
Acquisition Time(Note 2). to 0.01%
Gain - Absolute Error
Gain Of 1,2,
Gain Of 4, & 8

TEMP

+250C
Full
+250C
Full
+25 0 C
Full
Full
Full

80
90
15
30
:tID
80

O.S

+25 0 C

3
80
80
20
30
:tID
74

1

-90

-80

VIL

UNITS

10
12
300
600
150
300

mV
mV
nA
nA
nA
nA
V
dB

1

jiA

0.8
20

rnA

85

0.5

2
70
-80

<:

=1000pF; VIH =4.0V;

0.8
20

+250C
+25 0 C

OOC ~ TA ~ +75 0 C
-55 0 C < TA < +125 0 C
-65 0 C <: TA +1500 C
- 650mW
+8, -15V

HI-5900-5
OOC to +700C
MIN.
TYP.
MAX.

7
9
300
600
150
300

85

Full
Full

p.A

2
70

MHz
kHz

-90

dB

+250C

-76

-76

dB

+25 0 C

9

9

jis

Full
Full

0.01
0.01

Full
+2SOC
+2S oC

DYNAMIC CHARACTERISTICS
tON. Enable (MUX)
tOFF, Enabl. (MUX)

Charg. Transfer (T /H)
Aperture Delay (T/H)
Aperture Uncertainty (T/H)

2

Full

OUTPUT CHARACTERISTICS
Output Voltag. Swing
Output Current
Output Resistance

SI.w Rate
Droop Rate (T/H)

HI-5900-2
-550C to+1250C
TYP.
MIN
MAX.

Short Circuit Protected

0.1
0.2

:tID
:!:10

0.01
0.01

0.2
0.2

%
%
V
rnA

:!:10
:tID
S

5

n

+25 0 C
+2S oC

300
300

300
300

ns
ns

+25 0 C
+2SoC
Full
2S oC
+25 0 C
+25 0 C

i4

±4
5

V/jiS
nV/l1s
I1V/l1s
pC
ns
ns

S
20

5

10
SO
5

10
SO
5

POWER SUPPLY CHARACTERISTICS
+25 0 C
Full
+250C
Full

1+

'Power Supply Rej.ction Ratio, V+
Power Supply Rejection Ratio, VNOTES:

5-40

Full
Full

8.S
6.S
76
80

90
100

13
IS
13
15

8.0
6.0
70
80

90
100

13
15
13
15

rnA
rnA
rnA
rnA
dB
dB

1. Absolute maximum ratings are lImiting values, applied Individually beyond which the serViceability of the
circuit may be impaired. Functional operabilitY under any of these conditIons IS not necessarily Implied.

2. Acquisition Time is defined for a change of channel (+10V on chan. 1 to OV on chan. 8) with simultaneous
change from HOLD to TRACK mode. Gain'" 1.

=O.8V

PIN FUNCTIONS AND DESCRIPTION
PIN

SYMBOL

4
5
6
7
8
9
10
11

lB
2B
3B
4B
5B
6B
7B
8B

29
28
26
25
24
23
22

lA
2A
4A
5A
6A
7A
SA

31
32
1

AD
Al
A2

20
19

GO
Gl

OESCRIPTION

PIN

SYMBOL

DESCRIPTION

Non-Inverting Side of the Eight
Oifferentiallnput Channels

16
2
3
12
21
18
17
15

T/H CONTROL
NC
GND
+V
-V
T/H OUT
CH
VREF LDW

13

OUT A

14

OUTB

30

EN

Track/Hold Mode Select*
No Connection
Signal and Power Ground
Positive Supply (+15V)
Negative Supply (-15V)
Output of the H1-5900
Hold Capacitor Connection
Reference for the Output on
Pin 18
"A" Dutput of the Input
Multiplexer (Inverting Side of
each Channel)
"B" Output of the Input
Multiplexer (Non-Inverting Side
of each Channel)
Enable Strobe for the Input
Multiplexer; Normally Forced
High. EN may be used in
Conjunction with 0 UT A and
OUT B, to Poll Additional
Channels through an External
Multiplexer.

Inverting Side of the Eight
Differential Input Channels

Digital Channel Select Inputs*
Digital Gain Select Inputs*

• See Programmable Functions
T/H VREF OUT OUT
CNTL LOW B
A
+V

CH

TJH
OUT

G,

Go

-v

88

SA

7B

7A

6B

6A

58

SA

4B

4A

38

3A

28

2A

18

lA

GND Nle

EN

AO

A2

•

Al

PROGRAMMABLE FUNCTIONS Input Codes are as follows:
X = DON'T CARE
0= VIN S +0.8V;
1 = VIN ~ +4.0V, where VIN is the digital input voltage.
1. T/H Control (PIN 16)

3. Channel Select
Track
Hold

0
1

I

2. Gain Select
Gl
(PIN 19)

GO
(PIN 20)

GAIN

0
0
1
1

0
1
0
1

1
2
4
8

A2
(PIN 1)

Al
(PIN 32)

AD
(PIN 31)

EN
(PIN 30)

X
0

X

X

0

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

1
1
1
1
1
"1
1
1

0
0
0
1
1
1
1

CHANNEL
None
1
2
3
4
5
6
7
8

5-41

I

PERFORMANCE CURVES
ACQUISITION TIME

VS.

OUTPUT STEP CHANGE

~

~ +10

~
~

o

~
":'i ..

S

VS.

FREQUENCY

60

40

w

o

"~

~

~o

INPUT NOISE VOLTAGE

0

20

>
w

!Il

..
0

Z

·5

10

~

-I.

10
ACQUISITION TIME

10:

100

10K

lK

lOOK

FREQUENCY-Hz

-ps

FIGURE 2

FIGURE 1

INPUT LEAKAGE, BIAS & OFFSET
CURRENT VS. TEMPERATURE
TYPICAL T/H AMPLIFIER PERFORMANCE
VS. HOLD CAPACITANCE Ch

+200nA

10.000...---....---------..,

+l00nA

1.000

100

10-r--____-=-:~~~

___

10

-10DnA

+lOnA

0.1
+1nA

0.01

+--,---,--,.--,---1
10pF

100pF 1,OOOpF O.OlJ.1.F O.lJ.1,F
CH VALUE

1.0~F

INPUT

LEAKAGE

+10DpA

FIGURE 3

+lOpA

CURRENT
(CHANNEL OFF)

---

....c

.., ... "
DO

:

+400

+8"

+2"""
TEMPERATURE

FIGURE 4

APPl YING THE HI-5900
GENERAL CONSIDERATIONS
The HI-5900 was designed to provide a versatile front-end
section for a data acquisition system. Both hardwired and
computer-controlled systems may be implemented in a
variety of configurations. The following general considerations and precautions should be observed.
1. HANDLING - Each digital input is protected by a resistor-diode network, to minimize failures due to static
discharge through the MOS gate:

5-42

+V

~~~~~
.f ~~ -

V'N_

•••

-V

+1200c

APPLYING THE HI-5900 (Continued)
For additional protection, it is wise to observe all of the
proper shipping and handling procedures customary for
CM OS devices.
2. POWER SUPPLY CONNECTIONS - Each of the four
active chips in the HI-S900 are bypassed to ground by
internal .01 f.L F capacitors. These eight non polarized
capacitors prevent high frequency variations in the supply
voltage.
To bypass lower frequencies, connect a polarized capacitor from the ground pin to each supply pin, with value
fro m 1Of.LF to SOf.LF.
3. LAYOUT
A. 0 istributed capacitance between signal paths external
to the HI-S900 is a major source of crosstalk. Within
the H1-5900, careful substrate design and packaging
have ensured that "static" crosstalk will not exceed
-aOdB. ("Static") refers to the absence of channelto-channel switching. Thus, a maximum of 2mV
p-p can feed into a selected channel, from 20V p-p
applied to one or more OFF channels.)
When a multiplexer is continuously cycled from
channel to channel, two other forms of crosstalk
arise. These are dynamic crosstalk and adjacent*
channel crosstalk, which are both minimized along
with static crosstalk by careful attention to circuit
board layout. A strip of ground plane should separate
conductors for adjacent channels on a printed circuit
board. See Fig. 5. Make these traces (and the conductors) short, and as narrow as practical for maximum separation.

* Adjacent in time - for example, channels 1 and a may
occupy adjacent time slots during time - division
multiplexing.
(BOTTOM VIEW)

32
GNO
I
I

r1-.,

I
I
I

I
I
I

CHAN. 4
CHAN.S
CHAN. 6
ETC.

: CH I
I
I
I
I
I
I

LTJ
T/H
OUT

I
I

best performance indicator for hold capacitor applications, consider these guidelines: Teflon is best (especially at high temperature) but the most expensive.
In descending order of choice, polystyrene, polypropylene, and polycarbonate are all acceptable.
Least acceptable are ceramic and mica, which can
allow several percent of change in the held voltage due
to dielectric absorption (vs •. 01% for the other types).

OFFSET ADJUSTMENT
The VREF LOW input (pin IS) is a convenient point for
nulling any DC offset voltage in an HI-5900 system. This
can be done with a simple manual trim:

+15V

A/DCONV,

t-1.....,W---S20K

FIGURE 6

With zero volts on the selected input channel, tho HI-5900
output (T/H OUT) may be adjusted to zero. If the system
includes an A to a converter, net DC offset may be nulled
by adjusting the converter's digital output to zero. In either
case, readjustment is required after a change in temperature
or a change in the HI-5900 gain. The need for readjustment
may be eliminated by using an auto-zero circuit as shown
in Fig. 7.

•

The offset at Va is driven to zero by application of a voltage
at VREF LOW, opposite in sign and with magnitude (G + 1)
Va, where G is the digitally selected gain. This voltage is
updated each time channel a is addressed. Since channel a
is chosen for the zero (ground) reference input, the SN7420
decoder output is wired to go low only when channel 8 is
addressed. The HA-2420 track/hold amplifier acquires
a new sample of the offset at Vo during this interval. This
sample is of opposite sign to Vo and approximately 100X
(G + 1) in magnitude, due to the 10K/l00D attenuator.
Storing 100X the actual correction value minimizes the
percent droop error during hold. Finally, OFFSET TRIM is
used to remove any residual offset at Va, introduced by
the HA-2420.

,.
17

16
+15V

FIGURE 5
HI-5900 GUARD RING LAYOUT

B. The holding capacitor CH is the only essential external
component required for operation of the HI-5900.
The value selected determines droop rate, offset
error and acquisition time according to curves shown
in Fig. 3. Board layout should include a guard ring
to prevent voltage-driven leakage at the capacitor
terminal. See Fig. S.
For minimum droop error in the HO La mode, choose
a capacitor with high insulation resistance and low
dielectric absorption. Since type of dielectric is the

HI-5900

TMOUT~----------~~~-r~-oVO

I
I

_ _ _ _ ..JI

CH
,*1000PF
~

CHAN.
SELECT

FIGURE 7

5-43

I

m~RIS

HI-5901
Analog Data Acquisition
Signal Processor
(

FEATURES

DESCRIPTION

• INPUT OVERVOLTAGE PROTECTION
• SOFTWARE CONTROLLEO GAIN ANO
INPUT CHANNEL SELECTION
• 16 PSEUOO-OIFFERENTIAL/SINGLE
ENDEOINPUTCHANNELS
• GAINS OF I, 2,4 ANO 8
• -90dB CROSSTALK

Being self-contained units except for the holding capacitor, they facilitate user
applications and eliminate the need for selection of high-priced precision resistors
or labor intensive adjustments to achieve the accuracy levels specified.

• 0.01% GAIN ERROR
• 9,us ACQUISITION TIME
• [)ROOP RATE: 5nV/psec
• LOW POWER DISSIPATION 250mW

•

The HI-5901 is a data acquisiton front end subsystem intended for multisensor
based high-level applications, requiring conversion of analog input data to digital
form for computer processing. It provides sixteen single-ended or pseudodifferential channels of fault-protected multiplexed inputs, programmable gains
of I, 2,4, 8 and a buffered track and hold output block compatible with any
commercially available AID converter. All these functions are digitally selectable
through appropriate coding of seven control terminals. Input channel expansion
can be easily implemented through addition of external multiplexers and proper
utilization of the enable-command pin.

• COMPACT 32 PIN OIP
• MIL-8TD-883 SCREENING AVAILABLE

APPlICA TIONS
• MULTI-CHANNEL DATA ACQUISITION
SYSTEMS
• STATUS MONITORING SYSTEMS
• PROCESS CONTROL SYSTEMS
• INSTRUMENTATION

This product provides channel to channel throughput rates of 50kHz at ±10 volt
signal range when used in connection with a fast 12 bit A/D converter such as
the HI-5712. In addition, it offers excellent input characteristics such as low
input offset voltage with offset nulling capability, low input currents, very high
input impedance, and very low crosstalk. Typical acquisition time and gain error
are 9 microseconds and ±O.OI%, respectively. The internal track and hold amplifier features aperture delay of 50ns, 10pC of charge transfer error, and a droop
rate of 5nV /psec. Total power dissipation is only 250mW.
A complete high-speed and high precision data acquisition system with 15 bits of
dynamic range can be easily implemented with only three components: the
HI-5901, the HI-5712, and an offset nulling DAC. Board space required is 3
square inches and total weight is less than 25 grams.
The manufacturing technique adopted for the H1-5901 involves monolithic
dice packaged in leadless chip carriers (LCC's) and soldered to both sides of a
multilayer ceramic substrate. The resulting product is a compact and easy-to-use
32 pin DIP.
The HI-5901 is intended for military, aerospace, industrial and instrumentation
applications. MI L-STD-883 Class B and high reliability commercial grades are
both available as standard products.

• HIGH RELIABILITY DAS's

PINOUT

FUNCTIONAL DIAGRAM
Section 11
for Packaging

TOP VIEW

CHAN

MUX

SELECT EN OUT

32

A2
A3
GND
IN,

31

30
29
28

1Nl0
INn
IN12
INn

27
26
25
24

IN'4
IN,S
IN,S

10

23

11

+v

12

MUX OUT

SENSE

13
14

"

VREF LOW
T/H CONTROL

"16

AI
AD
EN
'N,
IN2
IN3
lN4
IN,
1N6
IN,
IN8

21

-v

20
19
I.
17

TIH OUT
CH

Go

G,

CHAN 1

T/H
OUT

CHAN 16

SENSE

0-----'

+v<>-GND c>---

-v<>--

5-44

GAIN
SELECT

'--__.........-<4-;:;=,,-----<> VREF LOW

SPECIFICA TIONS
ABSOLUTE MAXIMUM RATINGS (Notel)
40V

Voltage Between V+ and V- Terminals
Digital Input Overvoltage (Multiplexers)
VSuppl y (+)
VSuppl y (-)

Output Current
Operating Temperature Range
HA-5901-5, -7
HA-5901-2, -8
Storage Temperature Range
Internal Power Dissipation

+4V
-4V

Analog Input Dvervoltage
VSuppl y (+) +20V
VSuppl y (-) -20V

TEMP

OOC ~ TA ~ +75 0 C
-55 0 C < TA < +125 0 C
+150 oC
-65 0 C <: TA
- 650mW

<:

+8,-15V

T (H Control Input

ELECTRICAL CHARACTERISTICS Unless otherwise specified: Vs ~ .:t15V; CH
PARAMETER

Short Circuit Protected

HI-5901-2, -8
-55 0 C to +115 0 C
TYP.
MAX.
MIN

~

1000pF; VIH ~ 4.0V; VIL ~ O.BV

HI-5901-5, -7
OOC to +70 0 C
MIN.
TYP.
MAX.

UNITS

ANALOG INPUT CHAR.
EACH CHANNEL

Offset Voltage

+15 0 C
Full

1

7.5
9.5

3

10.5
13

mV
mV

Bias Current

+15 0 C
Full

80
90

300
600

80
80

300
600

nA
nA

Offset Current

+15 0 C
Full

15
30

150
300

20
30

150
300

nA
nA

Common Mode Range

Common Mode

Re~ction

Ratio

Full

:':10

Full

80

V

:':10
74

85

dB

B5

(VCM = :':10VI Any Gain
DIGITAL INPUT CHAR.
Multiplexer Digital Input Current
(High or Lowl

Full

1

0.5

0.5

1

)J.A

O.B
10

mA
!J.A

Track/Hold Digital Input Current
Full
Full

VINSO.BV
VIN Z 4.0V

O.B
10

TRANSFER CHARACTERISTICS
+25 0 C

2

1

MHz

Full Power Bandwidth (Gain::: 1,
Vo = ~10VI

+25 0 C

70

70

kHz

Crosstalk (Sample Mode, Gain::: 8,
1kHz 20VP -P Input on all but

+25 0 C

-90

dB

Small Signal Bandwidth (Gain

= 1)

-BO

-BO

-90

II,

Selected Channel)
= "

+25 0 C

-76

-76

dB

AcqUIsition Time(Note 2), to 0.01%

+25 0 C

9

9

)J.s

Full

0.01
0.01

"Off Isolation (Hold Mode, Gain
1kHz 20V P-P Input!

Gain - Absolut,e Error
Gain Of 1,2,
4,8

0.1
0.2

0.01
0.01

0.2
0.2

%
%

OUTPUT CHARACTERISTICS
Full

:':10

:':10

V

Output Current

+25 0 C

~10

~10

mA

Output Resistance

+25 0 C

5

+25 0 C

Output Voltage SWing

5

n

300

300

ns

+25 0 C

300

300

ns

+25 0 C

:':4

~4

VI!J.s

+15 0 C
Full

5

,

DYNAMIC CHARACTERISTICS
tON, Enable

IMUXI
(MUXI

tOFF, Enable

Slew Rate
Droop Rate ITIHI
Charge Transfer (T IHI

Aperture Delay

ITIHI

Aperture Uncertainty (T/H)

5
5

20

nV/j..1s
!J.VI!J.s

25 0 C

10

10

pC

+25 0 C

50

50

ns

+25 0 C

5

5

ns

+25 0 C
Full

B.5

13
15

8.0

+25 0 C
Full

6.5

13
15

6.0

POWER SUPPLY CHARACTERISTICS
1+

L

13
15

mA
mA

13

mA
mA

15

Power Supply Rejection Ratio, V+

Full

76

90

70

I

90

dB

Power Supply Rejection RatiO, V-

Full

80

100

80

i

100

dB

NOTES.

1. Absolute maximum ratings arp. limiting values. applied individually beyond which the serViceability of the
CirCUit may be Impaired. Functional operability under any of these conditions IS not necessarily Implied.
2. ACQUISition Time IS defined for a change of channel (+10V on chan. 1 to OV on chan.16) With Simultaneous
change from HOLD to TRACK mode. Gain = 1.

5-45

PIN FUNCTIONS AND DESCRIPTION
PIN

SYMBOL

4
5
6
7
8
9
10
11
29
28
27
26
25
24
23
22

IN9
IN10
IN11
IN12
IN13
IN14
IN15
IN16
INI
IN2
IN3
IN4
IN5
IN6
IN7
IN8

31
32
1
2

AO
AI
A2
A3

DESCRIPTION

16 Single Ended Input
Channels. The Signals
Applied to these Input
Channels are I nverted at
the Output of HI-5901

PIN

SYMBOL

20
19

GO
Gl

16
3
12
21
18
15

T/H CONTROL
GND
+V
-V
T/H OUT
CH
VREFLOW

13
14
30

MUX OUT
SENSE
EN

17

DESCRIPTION
Digital Gain Select Inputs*

Digital Channel Select Inputs*

Track/Hold Mode Select*
Signal and Power Ground
Positive Supply (+15V)
Negative Supply (-15V)
Output of the HI-5S01
Hold Capacitor Connection
Reference for the Output on
Pin 18
Input Multiplexer Output
Analog Signal Return
Enable Strobe for the Input
Multiplexer; Normally Forced
High. EN may be used in
Conjunction with MUX OUT
and SENSE, to Poll Additional
Channels through an External
Multiplexer

*See Programmable Functions
TfH VREF

MUX

IN

IN

IN

IN

IN

IN

IN

IN'

r77T17777¥YT1777
16

15

14

13

12

11

10

E

9

8

7

6

5

4

3

2

~~

32

HI-S9D1

17

18

19

20

21

22

23

24

25

26

21

28

29

30

31

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

CH

T/H
OUT

Gl

Go

-v

IN
8

IN
7

IN
6

IN
5

IN
4

IN
3

IN
2

IN
1

EN

AO

AT

PROGRAMMABLE FUNCTIONS Input Codes are as follows:
X = DON'T CARE
0= VIN ~ +0.8V
1 = VIN ~ +4.0V, where VIN is the digital input voltage

1. T/H CONTROL (Pin 16)

3. CHANNEL SELECT
EN
AI
AO
A3
A2
(Pin 2) (Pin 1) (Pin 32) (Pin 31) (Pin 30)

0
1

I

TRACK
HOLD

I

I

2. GAIN SELECT

G,

5-46

(Pin 19)

GO
(Pin 20)

GAIN

0
0
1
1

0
1
0
1

1
2
4
8

X
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

X
0
0
0
0
1
1
1
1
0
0
0

0
1
1
1
1

X
0
0
1
1
0
0

,

1
0
0
1
1
0
0
1
1

X
0

0
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1

1
1

,

,
,
1
1
1
1
1
1
1
1
1
1
1

CHANNEL
None
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

PERFORMANCE CURVES
ACQUISITION TIME vs. OUTPUT STEP CHANGE

INPUT NOISE VOLTAGE vs. FREQUENCY
~

':?

"0

50

>
f

!ti

'5

~0

40

20
G-B

>
w

!II
0

...
Z

-5

G=4

10

G=2

G-l

K
~

-10
10

10

100

10K

lK

lOOK

FREaUENCY-Hz

ACQUISITION TIME ·J.lS

FIGURE 2

FIGURE 1

INPUT LEAKAGE, BIAS & OFFSET
CURRENT vs. TEMPERATURE
TYPICAL T/H AMPLIFIER PERFORMANCE
vs. HOLD CAPACITANCE Ch
10,000 .,.~---::=-,-,..:---,-c:-:c-,-",=--,

+200nA

+l00nA

1,000

II

-1DOnA

I

+10nA

01
+lnA

001~--.--.---r--'-~

10pF

100pF 1.000pF 00l,uF O.l,uF 10,uF
INPUT

CH VALUE

LEAKAGE

+10OpA

CURRENT
(CHANNEL OFF)

FIGURE 3
+10pA

--- .... --'"

-4ace

0°

:

+4()O

'BOO

+1200C

+2SOC
TEMPERATURE

FIGURE 4

APPLYING THE HI-5901
GENERAL CONSIDERATIONS
The HI-5901 was designed to provide a versatile front-end
section for a data acquisition system, Both hardwired and
computer-controlled systems may be implemented in a
variety of configurations, The following general considerations and precautions should be observed.

+V

n.-!~~~~
.f 4~ -

VIN_

...

1. HANDLING - Each digital input is protected by a resis-

tor-diode network, to minimize failures due to static
discharge through the MDS gate:

-V

5-47

APPLYING THE HI-590t (Continued)
For additional protection, it is wise to observe all of the
proper ~hipping and handling procedures customary for
CM OS devices.
2. POWER SUPPLY CONNECTIONS - Each of the four
active chips in the HI-5901 are bypassed to ground by
internal .01 11 F capacitors. These eight nonpolarized
capacitors prevent high frequency variations in the
supply voltage.
To bypass lower frequencies, connect a polarized capacitor from the ground pin to each supply pin, with value
from 10!1F to 50I1F.
3. LAYOUT
A. 0 istributed capacitance between signal paths external
to the HI-5901 is a major sou.rce of crosstalk. Within
the HI-S901, careful substrate design and packaging
have ensured that "static" crosstalk will not exceed
-BOdB. ("Static") refers to the absence of channelto-channel switching. Thus, a maximum of 2mV
p-p can feed into a selected channel, from 20V p-p
applied to one or more OFF channels.)
When a multiplexer is continuously cycled from
channel to channel, two other forms of crosstalk
arise. These are dynamic crosstalk and adjacent*
channel crosstalk, which are both minimized along
with static crosstalk by careful attention to circuit
board layout. A strip of ground plane should separate
conductors for adjacent channels on a printed circuit
board. See Fig. 5. Make these traces (and the conductors) short, and as narrow as practical for maximum separation.

E

*Adjacent in time - for example, channels 1 and 16
may occupy adjacent time slots during time - division
multiplexing.
(BOTTOM VIEW)

32

r
I

r-L,

r

r

I

I

CHAN. 4

II CH II

CHAN.S
CHAN. 6
ETC.

I

I

I

I

I

I

LTJ
I

TJH
OUT

best performance indicator for hold capacitor applications, consider these guidelines: Teflon is best (especially at high temperature) but the most expensive.
In descending order of choice, polystyrene, polypropylene, and polycarbonate are all acceptable.
Least acceptable are ceramic 'lind mica, which can
allow several percent of change in the held voltage due
to dielectric absorption (vs.. 01% for the other types).

OFFSET ADJUSTMENT
The VREF LOW input (pin 15) is a convenient point for
nulling any ric offset voltage in an HI-5901 system. This
can be done with a simple manual trim:

+1SV

A!DCDNV.

h--.tl'N--~20K

FIGURE 6

With zero volts on the selected input channel, the H1-5901
output (T/H OUT) may be adjusted to zero. If the system
includes an A to 0 converter, net DC offset may be nulled
by adjusting the converter's digital output to zero. In either
case. readjustment is required after a change in temperature
or a change in the H1-5901 gain. The need for readjustment
may be eliminated by using an auto-zero circuit as shown
in Fig. 7.
The offset at Vo is driven to zero by application of a voltage
at VREF LOW, opposite in sign and with magnitude (G + 1)
VO, where G is the digitally selected gain. This voltage is
updated each time channel 16 is ~ddressed. Since channel 16
is chosen for the zero (ground) reference input, the SN7420
decoder output is wired to go low only when channel 16 is
addressed. The HA-2420 track/hold amplifier acquires
a new sample of the offset at Vo during this interval. This
sample is of opposite sign to Vo and approximately 100X
(G + 1) in magnitude, due to the 10K/l00D attenuator.
Storing 100X the actual correction value minimizes the
percent droop error during hold. Finally, OFFSET TRIM is
used to remove any residual offset at VO, introduced by
the HA-2420.

I
16
+15V

FIGURE 5
HI-5901 GUARD RING LAYOUT

B. The holding capacitor CH is the only essential external
component required for operation of the HI-5901.
The value selected determines droop rate, offset
error and acquisition time according to curves shown
in Fig. 3. Board layout should include a guard ring
to prevent voltage-driven leakage at the capacitor
terminal. See Fig. 5.
For minimum droop error in the HO LD mode, choose
a capacitor with high insulation resistance and low
dielectric absorption. Since type of dielectric is the

5-48

TJH OUTI------.,.,.:;~~-+-'f-oVO

~

CHAN
SELECT

FIGURE 7

APPLYING THE HI-5901 (Continued)
TIMING AND CONTROL
The HI-5901 is intended to operate with a fast A to D converter such as HARRIS' 12 bit HI-5712. A single monostable (one-shod multivibrator such as half of the dual
SN74123 provides the necessary timing and control:
The pulse rate at Q is equal to the conversion rate of the
A to D converter, since the one-shot is driven by the converter's STATUS output. Polarity of the Q output is correct
for initiating a conversion each time the HI-5901 returns
to the HDLD mode. For maximum channel-to-channel
throughput rate, the Ii pulse duration (determined by Rand
C) may be set equal to the HI-5901 acquisition time.

FIGURE 8

II

5-49

HI-7541

m~RIS

12 Bit Multiplying
Monolithic Digital-toAnalog Converter
FEATURES

DESCRIPTION

• FULL FOUR QUAORANT MULTIPLICATION
• .01% RELATIVE ACCURACY OVER TEMPERATURE
•

100pF MAX

LOW OUTPUT CAPACITANCE

• TTl/CMOS COMPATIBLE

The Harris HI-7541 is a 12-Bit Monolithic Oigital to Analog
converter, offering full four quadrant multiplying capability.
The chip features dielectrically isolated CMOS technology
to assure fast settling time and freedom from latch-up. Included are thin film ladder and applications resistors, laser trimmed
for accuracy over the full operating temperature range.

• MONOLITHIC CONSTRUCTION
• VERY LOW OUTPUT LEAKAGE CURRENT
•

±lDOnA MAX

LOW GAIN ERROR

0.1%

The HI-7541 is recommended as a high performance direct
replacement for the A07541 device. It operates on a single
+15V supply and is available in an 18-pin ceramic package
as well as in dice form. Screening to MIL-STD-883 method
5004 class B is available.

APPLICA TIONS

II

• PROGRAMMABLE GAIN AMPLIFIERS
• PROGRAMMABLE FUNCTION GENERATION

PINOUT

FUNCTIONAL DIAGRAM
Section 11 for Packaging

TOP
IOUTl C

~ iJ RFEEOBACK

IOUT2 C 2

17

GNOC 3
(MSB) BIT lC 4
BIT 2 C 5
BIT 3 C 6
BIT4C 7
BIT 5 [
BIT 6

8

C9

iJ VOO+
iJ BIT 12ILSB)
14 iJ BIT 11
13 PBIT 10
12 PBIT9
11 iJ BIT 8
10 IJ BIT 7
16
15

HI-7541

2R

2.

2R

2R

2R

PVREF IN

(
).,

52

~~ ~?

511

~, ?

I
I

I
I

~

l

l

BIT 2

BIT 11

'-+:--.. . . -+:--u-.......
(~~.',

I
1

OS12

:?

IOUl2

I
I

+,_ _+-;-'- - . _ - o A IOU'T1

: ¢
~~t~~ ~

~RFEEDBACK
R

OlGITAllNPUTS IDTl, TTL, CMOS COMPATIBLE)
LOGIC: A SWITCH IS CLOSED TO loun FOR ITS
DIGITAL INPUT IN A HIGH (LOGIC 1) STATE.

5-50

· SPECIFICA TlONS
ABSOLUTE MAXIMUM RATINGS (Referred to Ground)l
Power Supply Inputs VDD
Reference Inputs VREF (Hi)
Digital Input Range Bits 1-12

+17V
:!:25V
VDD to GND

Output Voltage (Pins 1 and 2)

-10omV to VDD

Power Dissipation (Package) up to +750C
450mW
Derate above +750C by 6mW/oC.
Operating Temperature Range
HI-7541SD!TD/SD
-550C to +125 0C
HI-7541AD/BD
-25 0 C to +85 0C
HI-7541JN/KN/JO
DoC to +75 0C
HI-7541SD/883 AND TD/883.
-550C to +125 0C
-65 0C to +150 0C
Storage Temperature Range

ELECTRICAL CHARACTERISTICS . (@25 0C, VDD = +15V, VREF = +IOV Unless otherwise noted)

PARAMETER

CONDITIONS

INPUT CHARACTERISTICS
Digital Inputs

Bit ON = "Logic I"
Bit OFF = ,. Logic 0"

Input Voltage
Logic I, VAH
Logic 0, VAL
Input Current
Logic 1
Logic 0

0.8

0.8

V
V

1
-1

1
-1

p.A
p.A

12
+10

K!1

2.4

2.4

VIN=15V
VIN=OV

Reference Input
Input Resistance
Input Voltage

7
-10

9

12
+10

7
~10

9

II

V

TRANSFER CHARACTERISTICS
Resolution
Integral (2)
Nonlinearity
Differential (2)
Nonlinearity
Gain Error (2)
Gain Tempeo (2)(5)
Settling Time (2) (5)
to +1/2 LSB
PSRR (2)

Over Full Temp. Range
@+250C
Over Full Temp Renge
@+250C
Over Full Temp Range
@+250C
Over Full Temp. Range
Over Full Temp. Range

14.5V~VDD~15.5V;250C

Over Full Temp. Range

Bits

12

12
:t.Ol

t.02

%FSR

:t.Ol
±D.l
:to.15
:t5

:t.02
:to.2

%FSR

to.25
t5

%FSR
PPM/DC

1
:t.Ol
:!:.02

1
.±.01
:t.02

p.s
%FSR/
%~VDD

:!:50

±50

nA

±100
100
±1

±100
toO
±1

nA
pF
mVpp

OUTPUT CHARACTERISTICS
Output (2)
Leakage Current
Capacitance (2) (5)
Feed Through (2)(5)

VREF = :!:10V
@+250C
Over Full Temp. Range
VREF = 20 Vpp @10kHz

POWER REGUIREMENTS
VDD
IDD (3)

( See Fig. 6, 8, & 9 )

5-51

NOTES:
1. Absolute maximum ratings are limiting values, applied
individually, beyond which the serviceability of the circuit
may be impaired. Functional operation under any of these
conditions is not necessarily implied.

2.
3.
4.
5.

See Definitions.
After 30 seconds warm-up.
Specification's subject to change
Guaranteed by design, not tested.

without

notice.

DEFINITIONS OF SPECIFICATIONS
ACCURACY

INTEGRAL NONLINEARITY-Integral Nonlinearity of a
D/A converter is an important measure of its accuracy. It
describes the deviation from an ideal straight line drawn between zero (all bit OFF) and full scale(all bits ON).

DIFFERENTIAL NONLINEARITY-For a D/A converter,
it is the difference between the actual output change and the
ideal (1 LSB) change for a one bit change in code. A Differential Nonlinearity of +1 LSB or less guarantees monotonicity;
i.e., the output always increases and never decreases for an
increasing input.

The gain is defined only when the MDAC is used with an output operational amplifier in which case it is VOUT/VREF.
POWER SUPPLY REJECTION RATIO (PSRR)

Variation in VOUT due to variation in VDD expressed in %FSR/
% Vps.
OUTPUT CAPACITANCE

Measured capacity from loun or IOUT2 terminals to ground.
OUTPUT LEAKAGE CURRENT

SETTLING TIME

Settling time is the time required for the output to settle to
within the specified error band for any input code transition.
It is usually specified for a full scale or major carry transition.

Current leakage to ground from loun (all bits low) or IOUT2
(all bits high) with no connection to the span resistor (Pin 18).

FEEDTHROUGH ERROR

Variation in VOUT due to variation in VREF, for the condition
all bits OFF (zero output current!.

OPERA TING INSTRUCTIONS
BYPASSING AND GROUNDING

For best accuracy and high frequency performance the grounding
and bypass scheme shown in Figure 1 should be used. Bypass
capacitors should be connected close to the HI-7541 (preferably

to the device pins) and should be tantalum in parallel with a
smaller ceramic type for best high frequency noise rejection.

Voo+

18')------+-_ _--,

1
7

~
+

VREF

_

VREF'N

"-"OUT1

3::
_

HI-7541

'OUT2

'2'

3 &...GN_D_ _ _ _ _ _ _ _ _...

~I
- .... V"- ./>--+-........-oVOUT

+ /"'"

~tl--'7+----,
0.1/.IF

Vps_

SIG.GND

FIGURE 1

5-52

OPERA TING INSTRUCTIONS

(CONTINUED)

UNIPOLAR BINARY OPERATION
For most applications the H1-7541 requires an output operational amplifier, since both IOUTl and loun should remain
at ground potential to avoid linearity errors. Figure 2 shows the

VR~F

DA.
.........
R2~

17

connections for unipolar straight binary operation. A schottky
diode limits the negative excursions of voltage on lOUT.

RFEEOBACKA~

18

'Y'Y

2K

R,='K
4

BIT 1 (MSBJ
I
I
I
I
I

HI-7S41
IOUTl
1

I
I

-

I
I

IS

2

3

VOUT

V

I

BIT 12 (lSBJ ~

IOUT2
GNO

FIGURE 2
CODE TABLE- UNIPOLAR OPERATION

1
1
1
0
0
0

1
0
0
1
0
0

1
0
0
1
0
0

1
0
0
1
0
0

1
0
0
1
0
0

1
0
0
1
0
0

1
0
0
1
0
0

II

NOMINAL ANALOG OUTPUT

OIGITAL INPUT
1
0
0
1
0
0

1
0
0
1
0
0

1
0
0
1
0
0

1
0
0
1
0
0

1
1
0
1
1
0

II

-VREF (1 - 2- 12 )
-VREF (112 + 2- 12)
-VREFI2
-VREF (112 -2-12)
-VREF (2 -12)
0

CODE TABLE - BIPOLAR (OFFSET) OPERATION
NOMINAL ANALOG OUTPUT

DIGITAL INPUT
1
1
1
0
0
0

1
0
0
1
0
0

1
0
0
1
0
0

1
0
0
1
0
0

1
0
0
1
0
0

1
0
0
1
0
0

1
0
0
1
0
0

1
0
0
1
0
0

1
0
0
1
0
0

1
0
0
1
0
0

1
0
0
1
0
0

1
1
0
1
1
0

-VREF (1-2- 11 )
-VREF (2- 11 )
0
VREF (2- 11 )
VREF (1-2- 11 )
VREF

5-53

OPERATING INSTRUCTIONS'

(CONTINUEDI

BIPOLAR (4-QUADRANTI BINARY OPERATION

Figure 3 shows the configuration for bipolar offset binary
coded operation. The analog output will be the product of
2K

VREF and the values given above.

= Rl

VREF~~~,-~------------------------------------______- ;

Voo -+15V

BIT 1
MSB

18~----~~~

R2~

__- -______~

lK

lOUT!

>------VOUT
HI-7541

IOUT2

BIT 12
LSB

IOK= RF

FIGURE 3

OFFSET AND GAIN CALIBRATION

UNIPOLAR CALIBRATION
Step 1:

Unipolar Zero Offset Adjustment
• Turn all bits OFF (00 ... 00)
• Adjust offset trimpot on the output
operational amplifier to OV ± lmV at VOUT

Step 2:

Unipolar Gain Adjustment
• Turn all bits 0 N (11 ... 111
• Adjust R1 and R2 for an output of
VOUT = -VREF (1-2- 12)
BIPOLAR CALIBRATION

5-54

Step 1:

B1polar Offset Adjustment
• Set VREF = +10V
• Turn MSB ON, all other bits OFF (1000 ... 00)
• Adjust R4 so that Vo UT = OV

Step 2:

Bipolar Gain Adjustment
• Set VREF = +10V
•• Turn all bits off (00 ... 00)
• Adjust R1 and R2 so that VOUT = VREF

OPERA TING INSTRUCTIONS

(CONTINUED)

SELECTING AN OPERATIONAL AMPLIFIER

The bandwidth of the MDAC itself can be approximated by
modeling it as a voltage source (Vref) followed by a series
resistance Ro) and capacitance (Co) as in figure 3. The halfpower frequency then is;

The outputs 10UTl and 10UT2 must remain very close to
ground potential for the HI-7541 to maintain its accuracy.
Because of this constraint, most applications require selection
of a suitable output op-amp. Harris Analog Products Division
offers a wide range of high performance op-amps which are
well suited to a variety of applications.

f=

If Ro = 10Krl and Co = 50pf then f = 318KHz. However,
an output amplifier virtually eliminates Co by maintaining
zero volts across it, thus extending the DAC/amplifier bandwidth
almost to that of the amplifier alone.

COMPENSATION

In the standard configurations of Figures 1 and 2 the output
capacitance of the MOAC along with the feedback resistance
introduces a pole in the open loop response of the system.
This pole may cause undesirable phase shift leading to excessive ringing or even oscillation. The phase shift may be compensated by placing a capacitor in the feedback loop. Figure
3 shows this scheme. The compensation is exact for RoCo =
RFB CFB. This is a special case, however, since both Ro and
Co are dependent on the digital code for a CM OS MDAC.

TABLE 1 HARRIS OP AMPS
(TYPICAL AT TA = +25 0 C)
Full Power Offset
Voltage
B.W.

Op Amp
HA-

Off.et
Voltage

Bias
Current

Drift

A practical approach is to turn all bits of the MDAC ON while
applying a square wave of appropriate magnitude to the reference input.
Then select a feedback capacitor which gives
approximately 20% of overshoot, which is equal to a 45 0 Phase
Margin. This form of compensation reduces the overall bandwidth of the system, which is dependent on the op amp selected.
MDAC EQUIVALENT
CIRCUIT WITH COMPENSATION

1
21TRoCo

Settling
CFB*
Compensation Time**
lor 450 P.M.

2600

75KHz

500llV

5iIV 1oC

InA

20pl

1. 511'

2525

1.6MHz

5mV

30llV/oC

125nA

12pl

200n.

5100

150KHz

50011 V 51lV/oC

20pA

lBpl

1.71"

InA

30pl

111"

51lA

2pl

70ns

5130

600KHz

5190

6.5MHz

100llV II'V/oC
3mV

20l'V/oC

* For standard configuration such as Figure 3. Vref equals 1KHz 10V peak to peak
square wave,
H

Forthe Op Amp alone. AVCL =-1, 10V step to 0.1%.

II

OFFSET

HI-7541

The offset of the Op Amp can be adjusted to zero using either
the op amp offset terminals or the scheme of Figure 4. A
more important parameter is offset drift over temperature.
For instance a 30 V/oC offset drift spec will lead to an error
over a 75 0 C temperature span (OoC to +75 0 C) of almost 1 LSB
for a 10V Full Scale output.

FIGURE 4
OP AMP PARAMETERS

EXTERNAL OFFSET ADJUST
AND SCHOTTKY PROTECTION
HI-7541

The addition of the output amplifier has a direct effect on many
of the MDAC parameters, including bandwidth, settling time,
accuracy and tempco. Settling time is difficult to measure for
the HI-7541 since the current outputs have almost no voltage
compliance. The output settling time of the MDAC-OP AMP
system can be measured; and if the settling time of the Op Amp
itself is known, that of the MDAC can be estimated by the RootSum of Squares method;

>--.....-vo

TM DAClT2 (M DAe + AMP) - T2 AMP
FIGURE 5

5-55

OPERA TING INSTRUCTIONS

(CONTINUED)

BIAS CURRENTS

DIODE PROTECTION

Bias currents can also introduce errors but there are many Op
Amps on the market which require negligible bias current.
Examples of these are the HA-2S00 and HA-51 00.

Some high speed Op Amps present a low impedance between
the inverting input and the negative supply terminal during
power up.
In these instances a schottky diode should be
placed as in Figure 4.

PERFORMANCE CURVES
LINEARITY ERROR VS. SUPPLY VOLTAGE

FEEDTHROUGH ERROR VS. FREQUENCY

I'O~gm_
0.3

g~1

O.,O• • • •
0.2

.010 _

_
/
_

0.1

iI"

11

15

10

.OO~LOO--L-LL~~,~--~~~ll,llOK--~~LU~'O~OK--~LL~~'M
FREQUENCY Hz

SUPPLY VOLTAGE - VOLTS

FIGURE 6

FIGURE 7

GAIN ERROR VS. SUPPLY VOLTAGE

SUPPLY CURRENT VS. SUPPLY VOLTAGE
1.2
1.1

.03

1.0

..

VAH= 2.4V

•B

~ .02

.7

f

.6
.S

..

•01

VAH=VDD

.3
.2
.1
10
LINEARITY ERROR % FSR SUPPLY - VOLTS

FIGURE 8

5-56

15

1

2

3

4

5

6

7

8

9

10

"

FEEDTHROUGH - % FREQUENCY - HZ

FIGURE 9

12

13

14

16

I

IJ HARRIS

HI-OAC 801
12-8it High Speed Monolithic
Digital-to-Analog Converter

.

FEATURES

DESCRIPTION

• DAC 80 CDNFIGURATIDN
• MDNDLITHIC CDNSTRUCTION

• FAST SETTLING
GIl

..

260ns (TYP) TO 0.01%
OOC TO 75 0C

GUARANTEEO MONOTONIC
WAFER LASER TRIMMED

• APPLICATION RESISTORS ON CHIP

.

ACCEPTS 6.2V OR 10.24V REFERENCE

e DIELECTRIC ISOLATION (Oil PROCESSING

The Harris HI-DAC 801 is a 12-bit, monolithic digital to analog
converter. Available in dice form, it is suitable as a component
in hybrid or compound monolithic circuits. The HI-DAC 801 is a
current output device, and the addition of a precision voltage reference makes it the functional equivalent of the popular DAC
80CBI-1.
Two versions are available-DAC 801-A, laser trimmed
to accept a +6.2V reference; and DAC 801-B, laser trimmed to
accept a +10.24V reference. Both versions are guaranteed monotonic over the OOC to 750C temperature range. Digital input code
may be complementary binary, complementary offset binary,
or complementary two's complement binary logic.
output current settling of 260ns is achieved using Dielectric
1~~lation (0 II processing to reduce internal parasitics. The speed
of the HI-DAC 801 combined with its guaranteed monotonicity
and maximum 1/2 LSB linearity error (@+25 0 C) make it an ideal
choice for high speed successive approximation analog-to-digital
converters.
Laser trimmed application resistors are provided
on-chip for use with an external output amplifier. They allow
bipolar operation as well as +5V, +10V and +20V output ranges.
F~st

APPlICA TlONS
• HYBRID DAC 80 BY ADDING REFERENCE
.. HIGH SPEED, SUCCESSIVE APPROXIMATION
TYPEADC'S

•

• HYBRID DATA ACQUISITION SYSTEMS

PAD CONFIGURATION/CHIP
GGO 1:1

vps-

"

FUNCTIONAL DIAGRAM

"Ill 1:1
vps+/-"
,.
BIT 12 BtT11 •
(LSB!

•

10.24V REF INPUT

•

6.2V REF INPUT

.

1-'L50 END)

BIT10.
81T9.
BITS.

GROUND

BIT 7 II
SJ"
81TSIII

158

laRouND

MILS II

BIT5.

·~v~~~
LD

BIT 4"
8113

•
•

BIPOLAR'[, JUNCTION

•

10.24V BIPOLAR R

6.2V BIPOLAR R

••
•

·
I·

10VSPAN

BIT2

20VSPAN
SPAN EJUNCTION

,!PS+ • •

A~~~~T

112MIlS

* A Summing Junction (normally an inverting input) is formed at the control

BIT 1 (MSS!

1

amplifier's non inverting input, since the amplifier's feedback is inverted by
an external transistor.

5-57

SPEC/FICA T/ONS
ABSOLUTE MAXIMUM RATINGS
Power Supply Inputs
Reference Inputs
Digital Inputs

Vps+
VpsVREF (Hi)
Bits 1-12

(Referred to Ground) (Note 1).

+18V
-18V
+Vps
OVTO +10V

Operating Temperature Range

-55 0C to +125 0 C

Storage Temperature Range

-65 0 C to +150 0 C

ELECTRICAL CHARACTERISTICS (@+250C,Vps+=+15V, Vps- =-15V, VREF = 6.2V,
(Note 5)

Unless otherwise noted)

PARAMETER

CONDITION

INPUT CHARACTERISTICS
Digital Inputs
(TTL Compatible)
Input Voltage
Logic "I"
Logic "0"
Input Current
Logic "I"
Logic "0"

Bit ON = "Logic 0"
Bit 0 FF = "logic I"

2.0

Guaranteed, not tested

Reference Inputs (Note 2)
Input Voltage
HI-DAC 801-A
HI-DAC 801-B
Input Resistance
HI-DAC 801-A
HI-DAC 801-B

II

0.8

V
V

10
-100

p.A
J.lA

6.2
10.24

V
V

12.4K
20K

n
n

TRANSFER CHARACTERISTICS
Resolution

12

Bits

Linearity (Note 2)
Integral
Differential

±Yz
±Yz

LSB
LSB

0.005

0.01
0.1

% FSR
% FSR

0.05

0.1

% FSR

Monotonicity

DoC to +75 0 C GUARANTEED

Offset (Note 5)
Unipolar
Bipolar

All bits OFF

Gain Error

All bits OFF

Temperature Stability
Offsat Drift (Note 2)
Unipolar
Bipolar
Differential Nonlinearity (Note 2/
Gain Drift (Note 2)
Settling Time (Note 2) , ~ 1/2 LS B

5-58

All bits OFF

All bits ON
All bits ON to OFF or
OFFto ON

ppm
FSR/oC

0.2
2
0.5
2
260

400'

ns

SPECIFICA TlONS (Continued)
CONDITION

PARAMETER
Power Supply Sensitivity (Note 2)
Offset
Unipolar
+Vps
-Vps
Bipolar
+Vps
-Vps
Gain
+Vps
-Vps

HI-DAC 801
MIN

TYP

MAX

UNITS

-Vps = -15V
+Vps=+15V

0.05
0.05

% FSR/

-Vps=-15V
+Vps=+15V

0.05
0.05

-Vps = -15V
+Vps=+15V

10
10

%~Vps

OUTPUT CHARACTERISTICS
Output Current
Unipolar
Bipolar

1.6

2

2.4

±D.8

±1

± 1.2

1.6

2

2.4
10
+10

Not including
Feedback Resistor

Output Resistance
Output Capacitance
Compliance limit (Note 2)
Glitch (Note 2)

-3
1600

rnA
rnA

Kn
pF
V
mV-ns

POWER SUPPLY REQUIREMENTS
4.5
-16.5

Vps+
VpsIps+ (Note 4)
Ips- (Note 4)

15
-15
5
-10

16.5
-11.4

V
V
rnA
rnA

II
I

NOTES:

1. Absolute maximum ratings are limiting values, applied individually. beyond which the serviceability of the circuit
may be impaired. Functional operation under any of these conditions is not necessarily Implied.
2. See Definitions.
3. FSA is "full scale range" and is 2mA (±20%) for current output.
4. After 30 seconds warm-up,
5. Parameters may vary according to die bonding scheme used. See recommended bonding diagram.

DEFINITIONS OF SPECIFICA TlONS
DIGITAL INPUTS

ACCURACY

The HI-DAC 801 accepts digital input codes in complementary
binary, complementary offset binary, and complementary two's
complement binary.

NONLINEARITY - Nonlinearity of a D/A converter is an important measure of its accuracy. It describes the deviation from
an ideal straight line drawn between zero (all bits OFF)andfull scale
(all bits 0 N).

ANALOG OUTPUT

DIGITAL Complementary Complementary Complementary
INPUT
Binary
Offset
Two's
Binary
Complement'"
MSB lSB

+Full Scale
100.••000 MidScale-llSB
Zero
111 ... 111
011...111 +¥.! Full Scale
000...000

+Full Scale
-llSB
-Full Scale
Zero

-lSB
+Full Scale
Zero
-Full Scale

DIFFERENTIAL NONLINEARITY - For a D/A converter, it is
the difference between the actual output voltage change and the
ideal (1 lSB) voltage change for a one bit change in code. A
Differential Nonlinearity of ±1 lSB or less guarantees monotonicity; i.e., the output always increases and never decreases for
an increasing input.

"'Invert MS8 with external mverterto obtain
eTC Coding

5-59

DEFINITIONS OF SPECIFICATIONS (Continued)
SETTLING TIME

POWER SUPPLY SENSITIVITY

Settling time is the time required for the output to settle to within the specified error band for any input code transition. It is
usually specified for a full scale or major carry transition.

Power Supply Sensitivity is a measure of the change in gain and
offset of the D/A converter resulting from a change in -15V, or
+15V supplies. It is specified under DC conditions and expressed
as parts per million of fullscale range per percent of change in power
supply (ppm of FSR'/%).

DRIFT

GAIN DRIFT - T~e change in full scale analog output over the
sPQcified temperature range expressed in parts per million of full
scale range per oC (ppm of FSR/oC). Gain error is measured
with respect to +25 0 C at high (TH) and low (TLl temperatures.
Gain drift is calculated for both high (TH -25 0 C) and low ranges
(+250 C -Tl) by dividing the gain error by the respective change
in temperature. The specification is the larger of the two representing worst case drift.

COMPLIANCE

OFFSET DRIFT - The change in analog output with all bits OFF
over the specified temperature range expressed in parts per million
of full scale range per oC (ppm of FSR/OC). Offset error is measured with respect to +25 0 C at high (TH) and low (TLl temperatures. Offset Drift is calculated for both high (TH-25 0 C) and low
(+25 0 C -TLl ranges by dividing the offset error by the respective
change in temperature. The specification given is the larger of the
two, representing worst-case drift.

A glitch on the output of a D/A converter is a transient spike
resulting from unequal internal ON-OFF switching times. Worst
case glitches usually occur at half-scale or the major carry code
transition from 011 ... 1 to 100...0 or vice versa. For example,
if tum ON is greater than turn OFF for 011...1 to 100 ...0, an
intermediate state of 000 ... 0 exists, such that, the output momentarily glitches toward zero output. Matched switching times
and fast switching will reduce glitches considerably.

Compliance voltage is the maximum output voltage range that
can be tolerated and still maintain its specified accuracy. Compliance limit implies functional operation only and makes no
claims to accuracy.
GLITCH

OPERA TIN G INSTRUCTIONS
BONDING AND GROUNDING

In order to ensure proper operation of the' HI-DAC 801, care must
be taken to bond it correctly. Primary in these considerations is
the selection of a grounding scheme.. The best approach is to
distinguish between a general power ground and a reference, or
precision ground. Figure 1 shows the recommended connections
in a system uJing an operational amplifier (such as the Harris HA2600) to achieve voltage output. Notice that a ground plane extends along the chip, and all currents on the device flow through
this plane. Any errors which arise along this plane are most significant at the MSB end. It is best thlt'n to choose this end as the
reference point for tqe output. The o~posite, or lSB end of the

plane, is bonded to the general system or power ground. Varying
currents through this point will give rise to voltages above those
defined as reference; however, the only current flowing into precision ground is the constant current drawn by the. reference plus
the negligible bias current of the op-amp. Remember that the
magnitude of the reference current changes when switching from
unipolar to bipolar operation and requires readjustment of offset
and gain. The finite resistance of the bond wires themselves introduce an error at both ends of the ground plane, and this effect is
reduced by double bonding of the ground pads. For effective bypassing tie the bypass capacitors close to- the pads of the chip.

+v.=.

POWER
GROUND

-v -=.

FIGURE 1. SYSTEM GROUNDING AND SUPPLY BYPASSING

5-60

OPERATING INSTRUCTIONS (Continued)
OFFSET GAIN ADJUSTMENT

The offset and gain of the HI-DAC 801 may be externally adjusted
via potentiometers. With the device mounted in a suitable package

G

(see Packaging the HI-DAC 801/ connect the potentiometers as
indicated in Figure 2.

F

DAC aOI-A

BIPOLAR
OFFSET
ADJUST

A
"

'. E

-- -

5K

~

B
5K

6.2K

C
OTO
2mA

2K

VOUT
VREF(LO)
D RB

H
GAIN
ADJ.
R2

+15V

VREF(HI)

150K

20K
R2

Rl

BIPOLAR
MODE

OFFSET
ADJUST

-15V

OUTPUT
RANGE
UNIPOLAR
MODE

150K

OTO+l0V
OTO+5V
±10V
±5V
2.5V

CONNECTIONS

II

BIAS RESISTOR (RB)

1.43Kn
1.11Kn

BTOE;
BTOE;ATOC
FTOG;HTOI;ATOE
FTOG;HTOI;BTOE
FTOG;HTOI;BTOE
ATOC

1.31K n
1.16Kn
.94Kn

FIGURE 2. OFFSET GAIN ADJUSTMENT

UNIPOLAR CALIBRATION

Step I:

Step 2:

Unipolar Offset
Turn all bits OFF
Adjust R1 for zero volts output
Gain
Turn all Bits ON
Adjust R2 lor an output 01 F~-l LSB
That is, adjust lor:
9.9976V for OV to +IOV Range
4.99BBVfor OV to +5V Range

BIPOLAR CALIBRATION

Step I:

Step 2:

Bipolar Offset
Turn all bits OFF
Adjust R1 for an output of:
-IOV 10r±IOV Range
-5V for ±5V Range
-2.5V lor ±2.5V Range
Gain
Turn Bit 1 (MSB) ON; all other bits OFF
Adjust R2 for zero volts output

5-61

HA-5320

mHARRIS

High Speed
Precision Monolithic
Sample and Hold Amplifier
FEATURES

DESCRIPTION

TIME
1.5f.ls (0.01%)
• ACQUISITION
O.lf.lV/f.lS (25 C)
• DROOP RATE
100f.lV/f.lS (FULL TEMP)
25ns
TIME
• APERTURE
2.5 mV (ADJUSTABLE
PEDESTAL
ERROR
•
TO ZERO)
INTERNAL
HOLD
CAPACITOR
• FULLY DIFFERENTIAL INPUT
• TTL COMPATIBLE
•
0

APPl/CA TlONS

•

•
•
•
•

PRECISION DATA ACQUISITION SYSTEMS
D/A CONVERTER DEGLITCHING
AUTO-ZERO CIRCUITS
PEAK DETECTORS

PINOUT

The HA-5320 was designed for use in data acquisition systems
whose sample-and-hold acquisition time is the primary speed
limiting specification. The circuit consists of an input transconductance amplifier capable of providing large amounts of charging
current, a low leakage analog switch, and an output integrating
amplifier.
The analog switch sees virtual ground as its load; therefore, charge
injection on the hold capacitor is constant over the entire input/
output voltage range. The pedestal voltage resulting from this
charge injection can be adjusted to zero by use of the offset adjust
inputs. The device includes a hold capacitor. However, if improved droop rate is required at the expense of acquisition time,
additional hold capacitance may be added externally .
This monlithic device is manufactured using the Harris dielectric
isolation process, minimizing stray capacitance and eliminating
SCR's. This allows higher speed and latch-free operation. The
HA-5320 requires ±15V, and is available in a ceramic or plastic
14-pin DIP.

FUNCTIONAL DIAGRAM
TOP VIEW

----,..,--INPUT [

1

14

+INPUT [

2

13

OFFSET AOJ. [

r
.L

OFFSET ADJ.

OUTPUT [

P
P

S/H CONTROL
SUPPLY GND

P

3

12

4

11 PEXTERNAL

v- [ 5
REF GND [

OFFSET

6
7

N.C.

HOLD CAPACITOR

10

P

9 ]
8 ]

,

ADJUST

V+

U.

?9

t>tHA-532$50OpF

-'NPUTo~+----II
+INPUT o - ' 2 O f - - - +

1_

-

II
I

+ ""

I

...,'4+-_ _-1

S/H CONTROlQ-'-

N.C.
V+
INTEGRATOR
COMPENSATION

~3

.
SUPPLY
GND

65
v-

11 6

8

REF

INTEGRATOR

GNO

COMPENSATION

EXTERNAL
HOLD

CAPACITOR

5-62

7
r---/---{)OUTPUT

,-

HI-565A

mHARRIS

High Speed Monolithic
Digital to Analog
Converter with Reference
FEATURES

DESCRIPTION

•

DAC AND REFERENCE ON A SINGLE CHIP

•

VERY HIGH SPEED: SETTLES TO 112 LSB IN 350ns TYP
FULL SCALE SWITCHING TIME 30ns (TYP)

•

MONOTONICITY GUARANTEED OVER TEMPERATURE

•

1/2 LSB MAX NONLINEARITY GUARANTEED OVER
TEMPERATURE

•

LOW GAIN DRIFT (MAX,
DAC PLUS REFERENCE)

•

LOW POWER DISSIPATION, MAX.

15ppm/OC
345mW

The HI-565A is a fast, 12 bit digital to analog converter with a
precision voltage reference on a single chip.
Twelve high speed bipolar switches route the current from each bit
cell either to ground or to the laser trimmed thinfilm R-2R ladder
network, depending on the logic level of the bit input.
The Harris dielectric isolation process is used to fabricate the
HI-565A, providing minimal stray capacitance and latch-free
operation. The chips are laser tirmmed at the wafer level to a
maximum linearity error of 1/4 LSB at +25 0 C, making the H1-565A
an ideal choice when both high speed and high accuracy are essential.
The low noise, highly stable reference voltage is brought out to a
package pin, and may be used elsewhere in the system. Laser
trimming sets the absolute value and temperature coefficient of the
reference. The HI-565A is thus well suited for a wide temperature
range with a maximum linearity error of 1/2 LSB.

APPLICATIONS
•

CRT DISPLAYS

•

HIGH SPEED A/D CONVERTERS

II

The HI-565A is available in both commercial and military temperature grades, and is packaged in a ceramic 24 pin DIP. Power requirement is +5V, -15V.

• VIDEO SIGNAL RECONSTRUCTION
• WAVEFORM SYNTHESIS

FUNCTIONAL DIAGRAM

PINOUT

TOPVIEW
NC

C

1

24 ]

81(MS8) IN

NC ~ 2

23 ]

82 IN

v+ [

3

22 ]

83 IN

REF OUT (+10V) [

4

21 ]

841N

VREF [LO IN) [

5

20 ]

85 IN

VREF (HI IN) [

6

19 ]

861N

V- [

7

18 ]

87 IN

81POLAR R IN [

8

17 ]

881N

IOAe OUT [

9

16 ]

89 IN

10V SPAN R [

10

15 ]

810 IN

20V SPAN R [

11

14 ]

811 IN

POWER GNO [-o-_
12 _ _ _-'--'r13 ] B12 (LS8)1N

REF OUT
4

vee
3

SIP. OFF.

+

-

20
--o20VSPAN

S

HI-565A

OK

10V

~10VSPAN

IREF
O.SmA

6 19.95K

OAe 9.9SK

o--'I/'~-+--r.+~

~

J

35K
' " .>--~

o---~~~~~

3K

5K

9

--+--<>

10 ........

xIOXIREF
CODE)

-V~; ~~2 M~~-1'3

25K
.

~

~

GNO

5-63

;m H.A.RRIS

HI-574A

Fast, Complete 12-Bit
~\I·~'l ~Nl~\~ Ilnalo!, to Digital Converter
1"\. lJ
with Microprocessor Interface
FEATURES

DESCRIPTION

• AD574A SECOND SOURCE
3S0mW

• LOWPOWER

• COMPLETE 12-BIT AID CONVERTER WITH REFERENCE AND CLOCK
• FULL 8 OR IS-BIT IlP INTERFACE
• FAST SUCCESSIVE APPROXIMATION
CONVER~ON

251ls

• CDMPOUND MONOLITHIC CONSTRUCTION
• NO MISSING CODES OVER TEMPERATURE
10ppmloC

• LOW GAIN T.C.

The Harris HI-574A is a complete 12-bit analog-to-digital converter.
Successive approximation conversion is performed by two monolithic
chips housed in a 28-pin dual-in-line package. This compound monolithic circuit combines Harris' CMOS and Bipolar processes.
Designed as a direct replacement for the AD574A, the device
offers full microprocessor compatibility by both 8 and IS-bit systems
via "Three State" output buffer circuitry. Wafer level laser trimming
techniques provide close match of ladder resistors, ensuring high
accuracy plus a guarantee of no missing codes over temperature.
Included in the AID converter are a 12-bit, high performance digitalto-analog converter, a very stable voltage reference, and an accurate
comparator.
In systems where power consumption must be minimized, Harris
offers a significant improvement over other manufacturers un its.
The HI-574A dissipates typically 400mW.

• LOW COST

APPLICATIONS
• HIGH PERFORMANCE DATA ACQUISITION SYSTEMS
• PRECISION INSTRUMENTATION

The HI-574A is available in versions which have guaranteed performance over both military and commercial temperature ranges.
Screening to MIL-STD-883A, Class B is also available.

• MILITARY AND INDUSTRIAL SYSTEMS

FUNCTIONAL DIAGRAM

PINOUT

BIT OUTPUTS

TOP VIEW
+5V SUPPLY VLOGIC

2.

STATUS.STS

1m

27

DST1 MSD

CHIP SELECT, Cs

26

0810

25

OBS

DATA MODE SELECT

BYTE ADDRESS/SHORT
CYClE,AO

..v

2.

OBS

CHIPENABLE.CE

23

OB7

+15V SUPPLY, Vee

22

086

DATA

21

08,

OUTPUTS

,.
"

2.

084

READltONVERT, RIC

HI·574A

+1OV REFERENCE
REF OUT
ANALOG COMMON, AC

REFERENCE INPUT
REFIN

19

083

18

DB2

12

17

OBI

10V SPAN INPUT. 10V IN

13

16

20V SPAN INPUT. 20V IN

14

DBOlSS
DIGITAL COMMON
DC

-15VSUPf'LY, Vee
BIPOLAR OFFSET
81POFF

5-64

+15V

DIGITAL
COMMON
·t5V

"

DIGITAL

20VIN

18 STS

STATUS
BUSY/nJC

IOVIN
ANALOG
COMMON

BIPDLAA
OffSET
AHALOG CHIP
REFIN

REf OUT
(lD.DOV)

12 BITS

DIGITAl-TO-ANALOG
COHVERTER

;II

HA.RRIS

HI-5660
High Speed Monolithic
Digital-to-Analog Converter

FEATURES

DESCRIPTION

• VERY HIGH SPEED: SETTLES TO 112 LSB IN 350ns
FULL SCALE SWITCHING
TIME 30ns
• MONOTONICITY GUARANTEED OVER
TEMPERATURE

Twelve high speed bipolar switches route the current from each
bit cell either to ground or to the laser trimmed thin film R-2R
ladder network, depending on the logic level of the bit input.

1/2 LSB MAX NONLINEARITY GUARANTEED
OVER TEMPERATURE

•

10ppm/oC

• LOW GAIN DRIFT
•

LOW POWER DISSIPATION

•

LOW COST

•

LOW PSf

230mW

lppm/%PS

APPLICATIONS
• CRT DISPLAYS
•

The HI-5660 12-bit digital-to-analog converter is a similar second
source to the AD566, yet offers improved power dissipation performance.

HIGH SPEED AID CONVERTERS

The Harris dielectric isolation process is used to fabricate the HI5660, providing minimal stray capacitance and latch-free operation.
The chips are trimmed at the wafer level to a maximum linearity
error of 1/4 LSB at 25 0 C, making the HI-5660 an ideal choice when
both high speed and high accuracy are essential.
For a +10V reference, Harris recommends using the HA-1610.
This highly stable precision reference is laser trimmed to an absolute
accuracy of ± 0.05% and a temperature coefficient of ± 3ppm/oC.
For designs where an external reference is impractical, the HI565A DAC is recommended.
The H1-5660 is available in both commercial and military temperature grades, and is packaged in a ceramic 24 pin DIP. Power requirement is +5V, -15V.

• VIDEO SIGNAL RECONSTRUCTION
• WAVEFDRM SYNTHESIS

PINOUT

FUNCTIONAL DIAGRAM
TOPVIEW
24 LEAD DIP
Vp ,+

C
C
C

BIPOLAR R IN

24

2

23

3

22 :J BIT 3 IN

AMP SUMMING r 4
JUNCTION '-VREF (HI IN) C 5

21 :JBIT 41N

N. C.
ANALOG GNO

Vps- [

6

P

BIT 2 IN

C

7

18 :J BIT 7 IN

8

17:J BIT81N

9

16 :J BIT 91N

10

15 :J BIT 10 IN

11

14 :J BIT 111N

20V SPAN R [

C

j

VREF;;C5)--_"·~V:!V5K~>----t-_ _ _--,

IHnl~V

5K

1

9.95K

VREF 3
ILOlIN-

4<

~'DV

~SPANR

5<

I

r--1----!l-L..,....O'OAC

Lr.~
I:>~ rO~~;FXCODE
!

C
C

DIGITALGNO

5<

19:J BIT61N

N.C.

10V SPAN R [

~SPANR

AMP
SUMMING 4
JUNCTIONo-----.

20 :J BIT 51N

BIPOLAR R IN

IOAC OUT

<:7~2DV

P BIT 1 (MSBIIN

1

• OUT

m

~1_~_12~246_13
V ps- POWER MSB
aND
IN

LSB
IN

13 :J BIT 12 (LSB) IN
-..-------12

5-65

mJ~RIS

M)V~NlW~

HI-5680
12 Bit low Cost Monolithic
Digital-to-Analog Converter

FEATURES

DESCRIPTION

•
•

The

DAC 80 ALTERNATE SDURCE
MONOLITHIC CONSTRUCTION
(SINGLE CHIP)

HI-5680 is a monolithic direct replacement for the popular

DAC 80 12-bit digital to analog converter. Single chip construction

• FAST SETTLING
• GUARANTEED MONOTONIC
DOC TO 75 0 C
• WAFER LASER TRIMMED
• APPLICATIONS RESISTORS ON-CHIP
• ON-BOARD REFERENCE
• DIELECTRIC ISOLATION (DI) PROCESSING
• ±12V POWER SUPPLY OPERATION

APPlICA TlONS

makes the

HI-5680 the optimum choice for low cost, high re-

liability applications. Additionally, Harris' unique Dielectric Isolation (DI) processing reduces internal parasitics resulting in fast
switching time and minimum glitch. Wafer-level laser trimming of
ladder and span resistors ensures high accuracy and exceptional
tracking over temperature.

The

HI-5680

is available in both current and voltage output

models which are guaranteed over the DoC to 75 0 C temperature
•
•
•

HIGH SPEED AID CONVERTERS
PRECISION INSTRUMENTATION
CRT DISPLAY GENERATION

range.

PINOUT

HI-5680 V
HI-5680 I

TOP VIEW
(MSB) BIT I [ I
24P 6.3V REF OUT
BIT 2 [ 2
23p GAIN ADJUST
BIT3 [ 3
22P +Vs
BIT 4 [ 4
21P COMMON
BIT 5
5
l:JUNCTION
BIT6[6
19p20V
BIT7 [ 7
lap 10V
BIT 8 [ 8
17P BIPOLAR OFFSET
BIT 9 [ 9
16
REF INPUT
BITIO[IO
15PVOUT/IOUT
BIT II [ 11
14p -Vs
(LSB) BIT 12 [ ' 12
13
LOGIC SUPPLY
-_ _ _ _......J

E

Zop

P
P

5-66

INPUT
CODE

OUTPUT
MODE

Complementary Binary
Complementary Binary

Voltage
Current

MODEL

All models include a buried zener reference featuring low temperature coefficient. In addition, the voltage output models include an
on-board output amplifier.

Power requirements consist of a +5V logic supply and ±Vs which
has a range of ±(11.4V to 16.5V). The package is a 24 pin DIP.

FUNCTIONAL DIAGRAM VOLTAGE OUTPUT

HI-5680 V

FUNCTIONAL DIAGRAM CURRENT OUTPUT

HI-5680 I

5-67

m

HA.RRIS

MlV~~c,t

HI-5685
High Performance Monolithic
12 Bit Digital-to-Analog Converter

FEATURES

DESCRIPTION

•
•

The H1-5685 is a monolithic direct replacement for the popular

DAC 85 SECOND SOURCE
MONOLITHIC CONSTRUCTION
(SINGLE CHIP)

DAC 85 12-bit digital to analog converter. Single chip construction

• FAST SETTLING
• GUARANTEED MONOTONIC
-25 0 C TO +85 0 C
• WAFER LASER TRIMMED
• APPLICATIONS RESISTORS ON-CHIP
• . ON-BOARD REFERENCE
• DIELECTRIC ISOLATION (01) PROCESSING
• :!:12V POWER SUPPLY OPERATION

makes the HI-5685 the optimum choice for low cost, high reliability applications. Additionally, Harris' unique Dielectric Isolation (01) processing reduces internal parasitics resulting in fast
switching time and minimum glitch.

•
•
•

laser trimming of

tracking over temperature.
The

APPLICATIONS

Waf~r-Ievel

ladder and span resistors ensures high accuracy and exceptional

HI-5685

is available in both current and voltage output

models which are guaranteed over the specified temperature range.

HIGH SPEED AID CONVERTERS
PRECISION INSTRUMENTATION
CRT DISPLAY GENERATION

INPUT
CODE

MODEL
HI-5685 V

PINOUT

HI-5685 I
HI-5685 V
HI-5685 I

Complementary Binary
Complementary Binary
Complementary Binary
Complementary Bil\ary

OUTPUT
MODE

TEMPERATURE
RANGE

Voltage

-25 0 C to +85 0 C

Current

Voltage

-25 0 C to +85 0 C
-25 0 C to +85 0 C

Current

-25 0 C to +850 C

TOP VIEW

(MSB) BIT 1 [

1

24::::1 6.3V REF OUT

BIT 2 [

2

23 :::J GAIN AOJUST

BIT3 [: 3

22:::J +Vs

BIT 4 [ 4
BIT 5 C 5

21 ::::I COMMON
20:J EJUNCTION

BIT 6 [:: 6
BIT 7
7
BIT 8
8

19::J 20V
18:::J 10V
17:::J BIPOLAR OFFSET

BIT 9 [:: 9

16 ~ REF INPUT

C
C

BIT 10 [
BIT 11 [
(LSB) BIT 12 [

5-68

10
11

15::::1 VOUT/IOUT
14
-Vs .

::J

12
13;:J LOGIC SUPPLY
'-------'

All models include a buried zener reference featuring low temperature coefficient. In addition, the voltage output models include an
on-board outPUt amplifier.

Power require'1lents consist of a +5V logic supply and :!:Vs which
has a range of :!:(11.4V to 16.5V). The package is a 24 pin DIP.

FUNCTIONAL DIAGRAM VOLTAGE OUTPUT

HI-56S5 V

FUNCTIONAL DIAGRAM CURRENT OUTPUT

BIPOLAR

REF

II
SCALING
NE~WORK

SCALING
NETWORK

HI-56S51

5-69

~ HA.RRlS

M)V~~l~\~

HI-5687
Wide Temperature Range
Monolithic 12 Bit
Digital-to-Analog Converter

FEATURES

DESCRIPTION

•
•

The

DAC 87 SECOND SOURCE
MONOLITHIC CONSTRUCTION
(SINGLE CHIP)

HI-5687 is a monolithic direct replacement for the popuiar

DAC 87 12-bit digital to analog converter. Single chip construction

• FAST SETTLING
• GUARANTEED SPECIFICATIONS
-55 0 C to 1250 C
• WAFER LASER TRIMMED
• APPLICATIONS RESISTORS ON-CHIP
• ON-BOARD REFERENCE
• DIELECTRIC ISOLATION (01) PROCESSING
• '±'12V POWER SUPPLY OPERATION

APPLICATIONS

makes the HI-5687

the optimum choice for low cost, high re-

liability applications. Additionally, Harris' unique Dielectric Isolation (01) processing reduces internal parasitics resulting in fast
switching time and minimum glitch. Wafer-level laser trimming of
ladder and span resistors ensures high accuracy and exceptional
tracking over temperature.

The

HI-5687 is available in both current and voltage output

models which are 100% tested over the -55 0 C to +125 0 C tempera•
•
•

HIGH SPEED AID CONVERTERS
PRECISION INSTRUMENTATION
CRT DISPLAY GENERATION

ture range.

MODEL

PINOUT

HI-5687 V
HI-5687 I

TOP VIEW
1

24

BIT 2 [

2

23

BIT 3

3

22:J +Vs

I::

~
~

GAIN ADJUST

BIT 4 [

4

21

5

20:J I:JUNCTIDN

6

19

6

r::

COMMON

BIT7 [

7

18~

8

17

BIT 9

9

16

BIT 10 [

10

15

BITll [

II

14~

-Vs

12

13

LOGIC SUPPLY

(LSB) BIT 12

~

Complementary
Binary
Complementary
Binary

Voltage
Current

All models include a buried zener reference featuring low temperature coefficient. In addition, the voltage output models include an
on-board output amplifier.

~ 20V

BIT 8 [

r::

OUTPUT
MODE

6.3V REF OUT

BIT 5 [
BIT

5-70

P

(MSB) BIT 1 [

INPUT
CODE

IOV

WBIPOLAR OFFSET

Power requirements consist of a +5V logic supply and :!:Vs which

P

has a range of .±.(11.4V to 16.5V). The package is a 24 pin DIP.

P REF INPUT

P

'--------'

VOUTflOUT

FUNCTIONAL DIAGRAM VOLTAGE OUTPUT

BIPOLAR

REF

BIT liN

--------------------------

IOV

HI-5687 V

II

FUNCTIONAL DIAGRAM CURRENT OUTPUT

I

-Vs

ADJUST

HI-5687 I

5-71

HARRIS

~\)~~~c,\~

FEATURES

16-Bit D to A Converter

DESCRIPTION

"

• 16 BIT RESOLUTION
• MONOLITHIC 01 BIPOLAR CONSTRUCTION
• FAST SETTLING TIME

1J,ls TO .OOJ%FS

± 0.3ppm/oC
± lppm/oC

• LOW DIFF. NON LIN. DRIFT
• LOW GAIN DRIFT
• ON-CHIP SPAN & OFFSET RESISTORS
• TTL/5V-CMOS COMPATIBLE

~ 1I2LSB@+25 0 C

• LOW UNIPOLAR OFFSET
• LOW UNIPOLAR oFFSETT.C.

iO.2ppm/ oC

• EXCELLENT STABILITY

APPlICA TIONS
• HIGH RESOLUTION CONTROL SYSTEMS
• HIGH FIDELITY AUDIO RECONSTRUCTION
• PRECISION FUNCTION GENERATION
AND INSTRUMENTATION

The HARRIS HI-DAC16 is a 16-bit, current output D/A converter.
Single chip construction includes thin-film application resistors
for use with an external op amp. These permit standard output
voltage ranges of 0 to +5V. 0 to +10V. i"2.5V, i"5V and ±10V.
Reference and span resistors have adjacent placement on the chip
for optimum match and thermal tracking. Futhermore. this layout
feature helps minimize the superposition error caused by selfheating of the span resistor, reducing it to less than 1/10LSB.
This and other design innovations have produced exceptionally
stable operation over temperature. Typical temperature coefficients
are ± 1ppm/oC for gain error and 0.3ppm/oC for differential nonlinearity error.
The internal architecture is an extension of the earlier H1-562
with several major improvements. All code dependent ground
currents are steered to a separate non-critical path. namely, power
supply ground. This feature allows the precision ground of the
converter to be sensed with virtually zero voltage drop referred to
system ground. The result is the complete elimination of nonlinearities due to code dependent ground currents while yielding an
extremely low unipolar offset of less than 1/2LSB. Because of this
separation, the user may route the precision ground some distance
to the system ground without degrading converter accuracy.
The HARRIS HI-DAC16 delivers a stable, accurate output without sacrifice in speed. Settling time to within ±0.003% is one
microsecond. Overall performance of this monolithic device should
be attractive for applications such as high fidelity audio and highresolution control systems.

PINOUT

TOP VIEW
-VPS 1
40 t- P.S. GND
CONTROL AMP. -IN -, 2
39 r+VPS
CONTROL AMP. +IN 3
38 J- BIT 1 tMSBI
4
37 J-BIT 2
10V SPAN R BIPOLAROIS- (;
3lit-BIT3
lOUT 6
35 J-BIT 4
N.C.- 7
34,....BIT5
N.C. _
8
33 ;-- BIT 6
20V SPAN R _
9
32 ;-BIT 7
N.C. - 10
31 ,-BIT 8
VREF IN - 11
30 ,.-BIT 9
ANALOG GND - 12
29 - BIT 10
N.C.- 13
28 -BIT 11
N.C. - 14
27 -BIT 12
N.C.- 15
26 -BIT 13
25
BIT 14
N.C. - 16
GND TERM - 17
24
BIT 15
23
BIT 16 tLSBI
±5V TERM R - 18
:l:l0V TERM R - 19
22
N.C.
N.C.- 20
21
N,C.
~----~

rrrrr-

5-72

HI-DAC16B/C

Typical power requirement is 450 MW. from the +15V and -15V
supplies combined. The package is a 40 pin ceramic DIP. Two
accuracy grades are offered.

~

C")

:::!
~

i;
....
~

:t;;:
~

BIT 1 IN
+VPS (MSB)

VREF ANALOG
IN
GND

10V
SPAN R

BIT 16 IN
..
(LSB)

20V
SPAN R

GROUND
CURRENT
CANCELLATION,
CIRCUIT
1----1

, 1 .1 ,I T ?< ~~S~~ND

10K
2R ~
CONTR. AMP, +IN

3.3K

R

1¥~I'1

I

2R ~

R

I

2R ~

R

I

2R

2R

R

R

'1 '1 '1 '1 '1 '1 '1 '1 '1 '1 '1

R

10K
BIPOLAR

R

~~~_]~~'"

DIS

Z10VTERM
SPAN R

246fl
±SVTERM
SPAN R
1.42K

CONTR.AMP, -IN

GNDTERM

*R = 1.25KQ

t11

I
"-J

W

_II

~
i!5::

Communications
ILJLJ1
...................................

.....

PAGE
HC-55516
HC-5502
HC-5510/HC-5511
HC-5512/12A

All Digital Continuously Variable Slope Delta Modulator (CVSD)
SLlC-LC Subscriber Line Interface Circuit
Monolithic CODECs
PCM Monolithic Filter

6-2
6-7
6-12
6-21

Automatic Line Balance Network

6-28

Induction Motor Energy Saver

6-30

Advance
HC-5531
Preliminary
HV-1 000/1 005/
1010

II

I

ABSOLUTE MAXIMUM RATINGS

As with all semiconductors, stresses listed under "Absolute Maximum Ratings" may
be applied to devices (one at a time) without resulting in permanent damage. This
is a stress rating only. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. The conditions listed under "Electrical
Characteristics" are the only conditions recommended for satisfactory operation.

6-1

m

H.A.RRIS

HC-55516

All-Digital Continuously
Variable Slope Delta Modulator (CVSD)
FEATURES
• REQUIRES FEWER EXTERNAL PARTS
• LOW POWER DRAIN: 6mW FROM SINGLE 5V-7V
SUPPLY
• TIME CONSTANTS DETERMINED BY CLOCK
FREQUENCY; NO CALIBRATION OR DRIFT
PROBLEMS; AUTOMATIC OFFSET ADJUSTMENT

The HC-55516 is a half duplex modulator/demodulator CMOS
integrated circuit used to convert voice signals into serial NRZ
digital data, and to reconvert that data into voice. The conversion is by delta modulation, using the continuously variable
slope (CVSD) method of companding.

• HALF DUPLEX OPERATION BY DIGITAL CONTROL
• FILTER RESET BY DIGITAL CONTROL
• AUTOMATIC OVERLOAD RECOVERY
• AUTOMATIC "QUIET"PATTERN GENERATION
• AGC CONTROL SIGNAL AVAILABLE

APPLICATIONS
• VOICE TRANSMISSION OVER DATA CHANNELS
• VOICE ENCRYPTION/SCRAMBLING
• VOICE I/O FOR DIGITAL SYSTEMS
AND SPEECH SYNTHESIS

While signals are compatible with other CVSD circuits, internal
design is unique. The analog loop filters have been replaced by
digital filters, using very low power, and requiring no external
timing components. This approach allows inclusion of many
desirable features which would be difficult to implement using
other approaches.
The HC-55516 has internal time constants optimized for a 16K
bits/sec data rate and is usable from 9K bits/sec to above 64K
bits/sec. The unit is available in 14 pin DIP (HC1) packages
in two temperature ranges: -55 0 C to +125 0 C (-2 or -8), and
-40 0 C to +85 0 C (-9). It is also available in chip form.

• AUDIO MANIPULATIONS: DELAY LINES, TIME
COMPRESSION, ECHO GENERATION/
SUPPRESSION, SPECIAL EFFECTS, ETC.

PINOUT

FUNCTIONAL DIAGRAM
Section 11 for Packaging

Top View

6-2

PINOUT PIN ASSIGNMENTS

PIN#
14-LEAO
O.I.P.

SYMBOL

ACTIVE*
LEVEL

DESCRIPTION
Positive supply voltage.

VOO
2

Sig. Gnd.

Ground connection to OIA ladders and comparator;
i.e. audio ground.

3

Aud. Out

Recovered audio out. May be used as side tone at
the transmitter. Presents approximately 100 kilohm
source. Zero signal reference is Vo 0/2.

4

AGC

A logic "Low" level will appear at this output when
the recovered signal excursion reaches one-half of
full scale value.

5

Aud.ln

Audio input. Should be externallv AC coupled.
Presents approximately 100 kilohms in series with
Voo/2.

6,7

No internal connection is made to these pins.

8

Gnd.

Logic ground. Negative supply voltage.

9

Clock

Receiver clock must be phased with digital input such
that data must be present at the positive clock transition.

10

Encode
(Decode)

Low
(High)

A single CVSO can provide half-duplex operation.
The encode and decode functions are selected by
the logic level applied to this input. A low level selects the encode mode, a high level, the decode mode.

11

APT.

Low

Activating this input causes an "alternate plain text"
(quieting pattern) to be transmitted without affecting
the internal operation of the CVSO.

12

~ig.

In

13

FZ

14

Dig. Out

II

I

Input for the received digital data.
Low

Activating this input forces the transmitted output,
the internal logic, and the recovered audio output into
the "quieting" condition.
Output for transmitted digital data.

*Note: No active input should be left in a "floating condition".

6-3

SPECIFICA TlONS
ABSOLUTE MAXIMUM RATINGS
Voltage At Any Pin

-3.0V to VOO +0.3V

Operating Temperature (-9)

+7.0V

(-2)
(-8)

Maximum VDD Voltage

Storage Temperature

+5.0V to +7 .OV

Operating VDD Range

-40 0 C to +85 0 C
-55 0C to +125 0C
-55 0C to +125 0C
-65 0C to +150 0C

ELECTRICAL CHARACTERISTICS @ T A = 250 C
Test Conditions VDD

=6.0V, Bit Rate = 16Kb/s

PARAMETER

MIN.

Clock Bit Rate
Clock Duty Cycle
Supply Voltage

MAX.

UNIT

NOTE

16/32

64

Kb/s

(1)

70

%

30
+5.0

+7.0
1.0

mA

Digital "1" Input

4.5

V

(2)

Digital "0" Input

1.5

V

(2)

Digital "1" Output

5.5

V

(3)

Digital "0" Output

0.5
0.5

1.4

Audio Output Voltage

0.5

1.4

Audio Input Impedance

100

Audio Output Impedance
Transfer Gain

100
-0.5

+0.5

V

(3)

Vrms

(4)

Vrms

(5)

Kf!

(6)

Kf!

(7)

dB

(8)

Syllabic Time Constant

4.0

mS

(9)

L.P. Filter Time Constant (55516)

0.94

mS

(9)

Step Size Ratio (55516)

24

dB

(10)

Resolution (55516)

0.1

%

(11)

Min. Step Size (55516)

0.2

%

(12)

Slope Overload

(13)

Fig. 1

Signal/Noise Ratio

(14)

Tab. 1
12

mV P-P

(15)

AG C Threshold

0.5

F.S.

(16)

Clamping Threshold

0.75

F.S.

(17)

Quieting Pattern Amplitude (55516)

6-4

V

Supply Current

Audio Input Voltage

•

TYP.

NOTES
1.

2.

3.

11. Minimum quantization voltage level expressed as a percentage of supply voltage.

There is one NRZ (Non-Return Zero) data bit per
clock period. Clock must be phased with digital data
such that data must be present at the positive clock
transition.

12. The minimum step size between levels is twice the resolution.

logic inputs are CMOS compatible at supply voltage
and are diode protected. Digital data input is NRZ at
clock rate.

13. For large signal amplitudes or high frequencies, the
encoder may become slope-overloaded. Figure 1 shows
the frequency response at various signallevels,measured
with a 3kHz low-pass filter having a 130dB/octave rolloff to -50dB. See Table II.

Logic outputs are CMOS compatible at supply voltage
and withstand short-circuits to VOO orground. Digital
data output is NRZ and changes with negative clock
transitions.

4.

Recommended voice input range for best voice performance.

5.

May be used for side-tone in encode mode.

6.

Should be externally AC coupled. Presents 100 Kilohms in series with VOO/2.

7.

Presents 100 Kilohms in series with recovered audio
voltage. Zero-signal references is VOO/2.

8.

Unloaded, for linear signals.

9.

Note that filter time constants are inversely proportional to clock rate.

14. Table I shows the SN R under various conditions, using
the output filter described in 13 (above) at a bit rate
of 16Kb/s. See Table II.
15. The "quieting" pattern or idle-channel audio output
steps at one-half the bit rate, changing state on negative
clock transitions.
16. A logic "0" will appear at the AGC output pin when
the recovered signal reaches one-half of full-scale
value (positive or negative).
17. The recovered signal will be clamped, and the computation will be inhibited, when the recovered signal reaches
three-quarters of full-scale value, and will unclamp
when it falls below this value (positive or negative).

10. Step size compression ratio of the syllabic filter is
defined as the ratio of the filter output, with an equal
1-0 bit density input to the filter, to its minimum
output.

SIGNAL LEVEL
DB

I
ODa IN = lADV RMS
Vs .. +6V

TABLE I
INPUT
FREQUENCY
AMPLITUDE
Hz
mV RMS
300
300
1000
1000

1400
45
500
16

OUTPUT
SNR
dB MIN.
20
15
14
9

-OOB

-OOBIN

-ODB

-SOBIN

-12D8

-12DBIN

-1808

-18DBIN

-2408

-240B IN

·30DB

·300BIN

-3608

-36DBIN

~

~

~

~

~

""'-..l

100

200

800

300

1000

2000

3000

FREQUENCY

Figure 1 - Transfer Function for CVSD at 16KB

6-5

NOTES (Continued)
TABLE"

INPUT FILTER FREQUENCY RESPONSE

OUTPUT FILTER FREQUENCY RESPONSE

FREQUENCY

RELATIVE OUTPUT

FREQUENCY

RELATIVE OUTPUT

O±O.5dB
O±O.ldB
O±O.ldB
-3±O.5dB
-20±2.0dB

100Hz to 1500Hz
1500Hz to 3000Hz
3800Hz to 100KHz

O±1.5dB
O±2.5dB
Less Than -45dB

100Hz
200Hz
1000Hz
3000Hz
9000Hz

INPUT LOW-PASS fiLTER

IN

C3

~JK

VOICE

i>-~~_ _ _O'_'-IP~ ~~~oE~;ODER

>-----11---.N.......H

C,

0.47 pF 10%
U,
PIN4

U2
PIN4

U3
PIN4
U,. U2, U3. HARRIS HA--4741 QUAD OP AMP
CAPACITORS IN pf UNLESS OTHERWISE

+VOD

STATED

R6

3905%

c. +_
2.2 #If
,ov
GND-Vss

RESISTORS 1/20 WATT

R7

CAP. TOl. 1% UNLESS OTHERWISE

110K

U,
PIN 11

A8

U2
PIN "

cs

110K

U3
PIN 11

STATED

RES. TOL. 1% UNLESS OTHERWISE
STATED

0.1 pf 10%

OUTPUT LOW-PASS FitTER

A11
B4.5K"'

C'2
,soo

c,.
2200

A27
464K

A'8

14.3K

CVSD ENCODER
AUDIO OUT
fOR SIDETONE

Figure 2 - Suggested Input/Output Audio Filters for SNR Measurement
NOTE: An oUJPut filter similar to the input filter section above will generally suffice for good voice intelligibility.

6-6

~~RIS

HC-5502
SlIC-lC Subscriber line
Interface Circuit

Preliminary
FEATURES

DESCRIPTION

• MONOLITHIC INTEGRATEO OEVICE
The HARRIS SLlC-LC incorporates many of the BORSHT
functions on a single IC chip. This includes DC battery
feed, a ring relay driver, supervisory and hybrid functions.
Using the unique HAR'FIIS dielectric isolation process, the
SLI C-LC can operate directly with a wide range of station
battery voltagees.

• UNIQUE 01 HIGH VOLTAGE PROCESS,
o COMPATIBLE WITH WORLDWIDE PABX
PERFORMANCE REQUIREMENTS
• CONTROLLEO SUPPLY OF BATTERY FEEO
CURRENT FOR SHORT LOOPS
o INTERNAL

~ING

RELAY DRIVER

The SLlC-LC also provides selective denial of power. If the
PABX system becomes overloaded during an emergency,
the SLlC-LC will provide system protection by denying
power to selected subscriber loops.

o LOW POWER CONSUMPTION DURING STANDBY
Ii)

SWITCH HOOK, GROUND KEY AND RING TRIP
DETECTION FUNCTIONS

o SELECTIVE DENIAL OF POWER TO SUBSCRIBER
LOOPS

The HARRIS SLlC-LC is ideally suited in the design of new
digital PABX systems, by eliminating bulky, expensive
hybrid transformers.
I

APPlICA TlONS

II,

SLlC-LC is available in either a 24 pin\ual-in':line plastic
or ceramic package.

• SOLID STATE LINE INTERFACE CIRCUIT FOR
DIGITAL PBX SYSTEMS

PINOUT

FUNCTIONAL DIAGRAM
Section 11 for Packagh1g

TOP VIEW
T
R
VB+

CAP!"
CAP 3
OG
RS

TX
AG
CAP4
RX
+IN
-IN

Rii

OUT
CAP 2

TF
RF

jijj

VB-

BG

...

,

2WIRE

RC
GKO
SHO

~--~----< "~----~
POWER DENIAL

PO

L ___

-:~M.!!O~~

______ _.JI

'Optional

6-7

SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
-60 to +.5 Volts
-.5 to +15 Volts
75 Volts
DoC to +75 0C
-400C to +85 0C
TBD
TBD

Maximum Continuous Supply Voltages (VB-I
(VB+I
(VB+- VB-I
Operating Ambient Temperaure Range (TAl
Storage Temp.erature Range (RSRGI
Power Package 0 issipation @ 25 0C (PD I
Power Dissipation Derating

RECOMMENDED OPERATING CONDITIONS
Positive Supply Voltage (VB+I
Negative Supply Voltage (VB-I
Minimum High level logic Input Voltage
Maximum low level logic Input Voltage
loop Resistance (RLl
Ambient Operating Temperature Range (TA)

10.8 to 13.2 Volts
-42 to -58 Volts
2.4 Volts
0.8 Volts
200 to 1200 Ohms
DoC to +700C

ELECTRICAL CHARACTERISTICS
(VB- =-48V, VB+ =+12V, AG
PARAMETER

=BG =DG at =OV, TA = 25 0 C Unless Otherwise Stated)
CONDITIONS

MIN

On Hook Power Dissipation

II

MAX

UNITS

110

mW

Off Hook loop Current

RlOOP =1200 Ohms

21

rnA

Off Hook loop Current

RlOOP =200 Ohms

27

rnA

13.3
54
27
67

mA
mA
mA
mA

Fault Currents
TIP to VB+ Ground
RING to VB+ Ground
TIP to RING
TIP and RING to VB+Ground
Ring Relay Driver Current

0.2 Volts

62

mA

Ring Trip Detection Period

RlOOP =600 Ohms

2

Ring Cycles

7.5

10

mA

Ground Key Detection Threshold

12.5

20

mA

Dial Pulse Distortion

0.1

ms

Receive Input Impedance

90

k Ohms

Transmit Output Impedance

1

Ohm

15.5
24
31

dB
dB
dB

72
63
64

dB
dB
dB

5

Switch Hook Detection Threshold

6-8

TYP

Two Wire Return loss
SRllO
ERl
SRl HI

(Return loss Referenced
to 600Q+2.16/-lF)

longitudinal Balance
2 Wire Off Hook
2 Wire On Hook
4 Wire Off Hook

IV Peak-Peak
200Hz - 3400Hz

low Frequency longitudinal Balance

R.E.A. Method

23

dBrnC

SPECIFICATIONS (Continued)

PARAMETER

CONOITIONS

Insertion Loss
2 Wire - 4 Wire
4 Wire - 2 Wire

@ 1kHz,

Frequency Response

200 - 3400Hz Referenced
to Absolute Loss at 1kHz and
OdBm Signal Level

MIN

TYP

MAX

UNITS

±.05
±.05

±.15
±.15

dB
dB

OdBm Input Level

±.02

dB

Idie Channel Noise
2 Wire - 4 Wire
4 Wire - 2 Wire

5
5

dBrnC
dBrnC

Absolute Delay
2 Wire - 4 Wire
4 Wire - 2 Wire

30
30

J.ls
J.ls

Envelope Delay
2 Wire - 4 Wire
4 Wire - 2 Wire

90
90

J.ls
J.ls

Trans Hybrid Loss

Balance Network Set Up
for 600 Ohm Termination

Overload Level
2 Wire - 4 Wire
4 Wire - 2 Wire
Level Linearity
2 Wire - 4 Wire
4 Wire - 2 Wire

Power Supply Rejection Ratio
VB+ to 2 Wire
VB+ to Transmit
VB- to 2 Wire
VB- to Transmit
VB+ to 2 Wire
VB+ to Transmit
VB- to 2 Wire
VB- to Transmit

40

dB

+4
+4

dBm
dBm
'±.05
±.1
±.3
±.05
±.1
±.3

+3 to -40dBm
-40 to -50dBm
-50 to -55dBm
+3 to -40dBm
-40 to -50dBm
-50 to -55dBm

dB
dB
dB
dB
dB
dB

II

I,

10 - 60Hz, RLOOP = 600n

15
15
15
15

dB
dB
dB
dB

200 - 16kHz
RLOOP = GOOn

30
30
30
30

dB
dB
dB
dB

Logic Inputs
Logic '0' VI L
Logic '1' VI H
Logic Outputs
Logic '0' Vo L
Logic '1' VOH

36

2.4

0.8
5.5

Volts
Volts

0.8
6.3

Volts
Volts

Max Two TTL Loads
3.0

0.1
6.1

6-9

PIN ASSIGNMENTS
PIN
NUMBER
1

SYMBOL

2

R

3

VB+

4

CAP 1

Capacitor # 1 - Optional Capacitor used to improve +12 V supply rejection. This pin
should be left open if unused.

5

CAP3

6

OG

7

RS

8

i!ii

9

TF

10

RF

11

VB-

12

BG

13

SHO

14

GKii

15

PO

16

ifC

17

CAP2

IIi
20
21

OUT
-IN
+IN
RX

22

CAP4

23

AG

24

TX

Capacitor # 3 - An external capacitor to be connected betwaen this terminal and
analog ground. Required for proper operation of the loop current limiting function,
and for filtering -48V supply. Typical value is 0.31lF, 30V.
Digital Ground - To be connected to zero potential and serves as a ",ference for
all digital inputs and outputs on the SLiC microcircuit.
Ring Synchronization Input - A TTL-compatible clock input. The clock is arranged
such that a positive transition occurs on the negative going zero crossing of the
ring voltage source. Ensuring that the ring relay is activated and deactivated when
the instantaneous ring voltage is near zero.
Relay Driver - A low active open collector logic output. When enabled, the
external ring relay is energized.
Tip Feed - A low impedance analon output connected to the tip lead through a
300 Ohm ±1% t.eed resistance. Used with the ring feed lead to provide loop current,
feed voice signals to the telephone set, and sink longitudinal currents.
Ring Feed - A low impedance analog output connected to the ring lead through
e 300 Ohm ±1% feed resistance. Used with the tip feed lead to provide loop'
current, feed voice signals to the telephone set, and sink longitudinal currents.
Negative Voltage Source - Most negative supply. VB- is typically -48 volts with an
operational range of -42 to -58 volts. Frequently referred to as "battery",
Battery Ground - To be connected to zero potential. All loop current and some
quiescent current flows into this ground terminal.
Switch Hook Detection - A low active TTL-compatible logic output. This output
is enabled for loop currents exceeding 10mA and disabled for loop currents less
than 5mA.
Ground Key Oetection - A low active TTL-compatible logic output. This output is
enabled if the DC current into the ring lead exceeds the OC current out of the tip
lead by more than 17.5mA, and disabled if this current difference isle.. than lOrnA.
Power Denial - A low active TTL-compatible logic input. When enabled, the loop
current is limited to a maximum 2mA, the switch hook detect (SliD) and ground key
detect (fii 0.11' F
CLK

PDN

FROM SLlC---iVFXI+

---.J

VFxD - ,

11-....- - i V F x

r - - - - i vF x 1AAA..J..

~"~;'

TO SLIC

•

AAA.

{

Ox

PWRO----tPWRO+

GNDAt---;--1IHGND.A

,....--...... PWRI

GNDD~Te-~-~~GNDD

1. . .

......rIV
... "'_.... A"'N
AA\-fVFRO

~"R4" - "RS'"

VBB

O"IIF~

I
Vcc VFR',:,
~

Ox
CLKX

CLKX

~<50K

HC-SS12

-TSx

TSx

~R1

GSx

"R3"

I
PDN

I

HC-SS10/
HC-SS11

FSx
CLKR
FSR
DR

~

FSX

DR

'0
V L.V_F_R_.;;=.......;~_-'
VBB Vcc

O.lI'F~
~-------------------+--~-~T~-----+SV

L--------------__
XMT gain

= 20 x log

(R3 ;2R2) +3dB

RCV gain = 20 x log (

. R4 )
R4 + RS

----+-~._--SV

'''':;: I

~''''

The power supply decoupling capacitors should be D.1J.lF. In order to take advantage of the excellent noise performance of
the HC-551DIHC5511/HC-5512, care must be taken in board layout to prevent coupling of digital noise into the sensitive
analog lines.

6-20

m~RIS

HC-5512/5512A
PCM Monolithic Filter

FEATURES

DESCRIPTION

• EXCEEDS ALL 03/04 AND CCITT SPECIFICATIONS
• +5V, -5V POWER SUPPLIES
• LOW POWER CONSUMPTION:
45mW (soon OdBm LOAD)
30mW (POWER AMPS DISABLED)
• POWER DOWN MODE: O.5mW
• 20dB GAIN ADJUST RANGE
• NO EXTERNAL ANTI-ALIASING COMPONENTS
• SIN x/x CORRECTION IN RECEIVE FILTER
• 50/S0Hz REJECTION IN TRANSMIT FILTER
• TTL AND CMOS COMPATIBLE LOGIC
• ALL INPUT PROTECTEO AGAINST STATIC DISCHARGE
DUE TO HANDLING

The HC-55121H C-5512A filter is a monolithic circuit containing both transmit and receive filters specifically designed for
PCM CO 0 EC filtering applications in 8kHz sampled systems.
The filter is manufactured using double-poly silicon gate
CMOS technology. Switched capacitor integrators are used
to simulate classical LC ladder filters which' exhibit low
com ponent sensitivity.
TRANSMIT FILTER STAGE
The transmit filter is a fifth order elliptic low pass filter in
series with a fourth order Chebyshev high pass filter. It provides a flat response in the passband and rejection of signals
below 200Hz and above 3.4kHz.

PINOUT
DUAL-IN-L1NE PACKAGE
TOPVIEW

Section 11
for Packaging

RECEIVE FILTER STAGE
The receive filter is a fifth order elliptic low pass filter designed
to reconstructthe voice signal from the decoded/demultiplexed
signal which, as a result of the sampling process, is a stairstep signal having the inherent sin x/x frequency response.
The receive filter approximates the function required to compensate for the degraded frequency response and restore
the flat passband response.

16 VFxO
15 GNDA

VFxl-

14 CLKO
13 PDN
12 elK

11 GNDD

•

10 VFRI

PWRO-

9

Vaa

Vee

FUNCTIONAL DIAGRAM

--------------------,

I

TRANSMIT FILTER

VFXI-."'iL-'-I~
VFlIl+~1r-<>-I,,"

,.
VfxO
14
CLKO

"

PWRO,...7~_.r..

eLK

PWRO+''''°L-...l..-"'O

PWRI VFRO

Vee

VBB

GNDD

GNDA

PllN

FIGl,JRE 1

6-21

I

SPECIFICA TIONS
ABSOLUTE MAXIMUM RATINGS
Supply Voltages
Power Dissipation
Input Voltage
Output Short-Circuit Duration
Operating Temperature Range
Storage Temperature
Lead Temperature (Soldering, 10 seconds)

±7V
1W/Package
±7V
Continuqus
-25 0 C to +125 0 C
-650C to + 150 0 C

300 0 C

DC ELECTRICAL CHARACTERISTICS
Unless otherwise noted, TA = ooC to 70o e, Vce = 5.0V±5%, VBB = 5.0V±5%, clock frequency is 2.048 MHz.
Typical parameters are specified at T A = 25 0 e, Vee = 5.0V, VBB = -5.0V. Digital interfaE:e voltages measured
with respect to digital ground, GNDD. Analog voltages measured with respect to analog ground, GNDA.

Symbol

Parameter

Units

Conditions

POWER DISSIPATION
leeo

Vee Standby Current

PDN = Voo, Power Down Mode

50

100

leBO

VBB Standby Current

50

100

/LA

leel

Vee Operating Current

3.0

4.0

mA

IBBl

V BB Oper~ting Current

=Voo, Power Down Mode
PWRI =VSB, Power Amp Inactive
PWRI =VSB, Power Arri p Inactive

3.0

4.0

mA

lee2

Vee Operating Current

Note 1

4.6

6.4

mA

IBB2

VBB Operating Current

Note 1

4.6

6.4

mA

10

/LA

PDN

/LA

DIGITAL INTERFACE

•

liNe

Input Current, ClK

Vss '" VIN ", Vee

-10

IINP

Input Current, PDN

Vss '" VIN ", yee

-100

IINO

Input Current, ClKO

Vas:s VIN '" Vee - 2V

-10

-0.1

/LA

VIL

Input low Voltage, ClK, PDN

0

0.8

V

V IH

Input High Voltage, ClK, PDN

2.2

Vee

V

VILO

Input Low Voltage, ClKO

Vss

Vss+O.5

V

Vila

Input Intermediate Voltage, ClKO

0.8

V

VIHO

Input High Voltage, ClKO

Vee

V

/LA

-b.8
Vee- 0.5

TRANSMIT INPd'r OP)~MP

6-22

IBxl

Input leakage Current, VFxl

Vss '" VFx l '" Vee

-100

Rlxl

Input Resistance, VFxl

Vss '" VFx l '" Vee

10

VOSxl

Input Offset Voltage, VFxl

-2.5V'" VIN " + 2.5V

VeM

Common·Mode Range, VFxl

CMRR

Common·Mode Rejection Ratio

PSRR

Power Supply Rejection of Vee
orVss

ROL

Open loop Output Resistance,
GS x

-2.5V",V IN " 2.5V

100

nA
Mil

-20

20

-2.5

2.5

mV
V

60

dB

60

dB
kll

10

kll

RL

Minimum load Resistance, GS x

CL

Maximum load Capacitance, GS x

VOxl

Output Voltage Swing, GS x

RL",10k

±2.5

V

AVOL

Open loop Voltage Gain, GS x

RL", 10k

5,000

VIV

Fe

Open loop Unity Gain Bandwidth,
GS x

25

2

pF

MHz

SPEC/FICA TIONS
AC ELECTRICAL CHARACTERISTICS
Unless otherwise specified, T A = 25 0 C. All parameters are specified for a signal level of 0 dBmO at 1 KHz. The

o dBmO level is assumed to be 1.54 Vrms measured at the output of the transmit or receive filter.
Symbol

Parameter

Conditions

Min

Typ

TRANSMIT FILTER (Transmit filter input op amp set to the non·inverting unity gain mode, with VF.I
wise noted.)
RLx

Minimum Load Resistance, VFxO

CL x

Load Capacitance, VFxO

Max

10

kG
25

RO x

Output Resistance, VFxO

PSRRl

Vee Power Supply Rejection, VFxO 1=1 kHz, VFxl+ =0 Vrms

1

PSRR2

Vee Power Supply Rejection, VFxO Same as Above

GAx

Absolute Gain

1= 1 kHz (HC-5512A)
1= 1 kHz (HC-5512)

GR x

Gain Relative to GAx

Below 50 Hz
50 Hz
60 Hz
200 Hz(HC-5512A)
200 Hz (HC-5512)
300 Hz to 3 kHz (HC-5512A)
300 Hz to 3 kHz (HC-5512)
3.3 kHz
3.4 kHz
4.0 kHz
4.6 kHz and Above

3

30

pF
G
dB

35
2.9
2.875

Units

=1.1 Vrms unless other·

dB
3.0
3.0
-41
-35

-1.5
-1.5
-0.125
-0.15
-0.35
-0.70
-15

3.1
3.125

dB
dB

-35
-35
-30
0
0.05
0.125
0.15
0.03
-0.1
-14
-32

dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB

DAx

Absolute Delay at 1 kHz

230

I'S

DDx

Differential Envelope Delay lrom
1 kHz to 2.6 kHz

60

I's

DPxl

Single Frequency Distortion
Products

-48

dB

DPx2

Distortion at Maximum Signal
Level

-45

dB

NC xl

Total C Message Noise at VF.o

NC x2

Total C Message Noise at VFxO

GAxT

Temperature Coefficient 01
1 kHz Gain

GAxS

Supply Voltage Coefficient 01
1 kHz Gain

Vee = 5.0V ± 5%
Vss= -5.0V±5%

CTRX

Crosstalk, Receive to Transmit
VF 0
20 log _x_
VFRO
Gaintracking Relative to GAx

Receive Filter Output = 2.2 Vrms
VFxl + = 0 Vrms, 1= 0.2 kHz to 3.4 kHz
Measure VFxO

GRxL

0.16 Vrms, 1 kHz Signal Applied to
VFxl +, Gain = 20 dB, RL = 10k

Gain Setting Op Amp at 20 dB,
Non·lnverting, Note 3
TA = O'C to 70'C

Output Level = + 3 dBmO
+ 2 dBmO to - 40 dBmO
- 40 dBmO to - 55 dBmO

2

5

dBrncO

3

6

dBrncO

0.0004

dBf'C

0.01

dBIY
-70

-0.1
-0.05
-0.1

0.1
0.05
0.1

•

dB

dB
dB
dB

6-23

I

I

SPECIFICA TIONS
ELECTRICAL CHARACTERISTICS (Continued)
Unless otherwise specified, T A = 25 0 C. All parameters are specified for a signal level of 0 dBmO at 1 KHz. The

o dBmO level is assumed to be 1.54 Vrms measured at the output of the transmit or receive filter.
Symbol

Parameter

Conditions

Min

Typ

Max

Units

RECEIVE FILTER (Unless otherwise noted, the receive filter is preceded by a sin xfx IiIterwith an input signal level of 1.6 Vrms.)
IBR

Input Leakage Current, VFRI

100

10

nA
Mil

RIR

Input Resistance, VFRI
Output Resistance, VFRO

3

fl

CL R

Load Capacitance, VFRO

25

pF

RLR

Load Resistance, VFRO

PSRR3

Power Supply Rejection of Vce or
VBB , VFRO

10

kfl

VFRI Connected to GNDA
f= 1 kHz

35

dB

VFRI Connected to GNDA

-200

GAR

Absolute Gain

f = 1 kHz (HC-5512A)
f = 1 kHz (HC-5512)

GR R

Gain Relative to Gain at 1 kHz

Below 300 Hz
300 Hz to 3.0 kHz (HC-5512A)
300 Hz to 3.0 kHz (HC-55121
3.3 kHz
3.4 kHz
4.0 kHz
4.6 kHz and Above

-0.1
-0.125

0
0

-0.125
-0.15
-0.35
-0.7

200

mV

0.1
0.125

dB
dB

0.125
0.125
0.15
0.03
-0.1
-14
-32

dB
dB
dB
dB
dB
dB
dB

DAR

Absolute Delay at 1 kHz

100

'"S

DDR

Differential Envelope Delay 1 kHz
to 2.6 kHz

100

'"s

DPRl

Single Frequency Distortion
Products

f = 1 kHz

-48

dB

DPR2

Distortion at Maximum Signal
Level

2.2 Vrms Input to Sin xix Filter,
f = 1 kHz, RL = 10k

-45

dB

NCR

Total C·Message Noise at VFRO

3

GART

Temperature Coefficient of 1 kHz
Gain

0.0004

dBfoC

GARS

Supply Voltage Coefficient of
1 kHz Gain

0.01

dBIV

CTXR

Crosstalk, Transmit to Receive
VF R0
2010g-VFxO
Gaintracking Relative to GAR

GRRL

6-24

-100

ROR

VOSRO Output DC Offset, VFRO

II

- 3.2V sV IN s3.2V

Transmit Filter Output = 2.2 Vrms
VFRI = 0 Vrms, f = 0.3 kHz to 3.4 kHz
Measure VFRO
Output Level = + 3 dBmO
+ 2 dBmO to - 40 dBmO
- 40 dBmO to - 55 dBmO
Note 5

5

-70

-·0.1
-0.05
-0.1

0.1
0.05
0.1

dBrncO

dB

dB
dB
dB

SPECIFICATIONS
AC Electrical Characteristics

(Continued)
Unless otherwise specified, T A =25 0 C. All parameters are specified for a signal level of 0 dBmO at 1kHz. The
OdBmO level is assumed to be 1.54 Vrms measured at the output of the transmit or receive filter.
Parameter

Symbol

Typ

Min

Conditions

Max

Units

RECEIVE OUTPUT POWER AMPLIFIER
IBP

Input Leakage Current. PWRI

RIP

Input Resistance, PWRI

ROPl

Output Resistance, PWRO
PWRO-

CLP

Load Capacitance, PWRO +.
PWRO-

GAp+

Gam, PWRI to PWRO +

GAp-

Gain, PWRI to PWRO-

RL = 60011 Connected Between
PWRO + and PWRO - , Input
Level =0 dBmO (Note 4)

GRpL

Gaintracking Relative to 0 dBmO
Output Level

V = 2.05 Vrms, RL =600n (Notes 4, 5)
V = 1.75 Vrms, RL =30011

SlDp

SignallDistortion

V = 2.05 Vrms. RL = 6001l(N t
4 5)
V = 1.75 Vrms. RL = 3001! 0 es .

VOSP

Output DC Offset. PWRO
PWRO-

PSRR5

Power Supply Rejection of Vce
or VBB

0.1

- 3.2V s VINs3.2V

3

+,

n

Amplifiers Active
500

+.

~A

Mn

10

VIV
VIV

1
-1
0.1
0.1

dB
dB

-45
-45

dB
dB

50

mV

-0.1
-0.1

PWRI Connected to GNDA

- 50

PWRI Connected to GNDA

45

pF

dB

Note 1: Maximum power consumption will depend on the load impedance connected to the power amplifier. The specification
listed assumes 0 dBm is delivered to 60onconnected from PWRO+ to PWRO-.
Note 2: Voltage input to receive filter at OV VFRO connected to PWRI, 600n from PWRO+ to PWRO-. Output measured from
PWRO+ to PWRO-.
Note 3: The OdBmO level for the fifter is assumed to be 1.54 Vrms measured at the output of the XMT or ReV filter.
Note 4: The odBmO level for the power amplifiers is load dependent. For RL = 600 to GNDA the OdBmO level is 1.43 Vrms
measured at the amplifier output for RL = 3000 the OdBmO level is 1.22Vrms.
Note 5: VFRO connected to PWRI, input signal applied to VFRI.

I

II

I

INTERFACE CIRCUIT FOR HC-5510 CODEC
R2

J. GNoA

... _____ ~L~ ____ ,
TRANSFORMERS

I

$ - J]L::.~ i'

I

R'

I

",.oN1:'"

-,...._-,..,~1:2_ _.".1L.::3~_ _- ,

;:::= ~
~....---h6oo5~llt~RS:7
~
i It.
i
___________ J

"'." "'.'-

I

m.

ol/lF

HC-5512/HC-5512A

":' GNoA
13
PoN

9

~PCM
Ox :--OUT

He-55'0
PoN

PWRo-

I Y I--,."6,,Oo/>,r16"+1 PWRo+

VFRO

PWRI
R4

t

R3

VFRI

10

10

VFR

Note 1 Transmit voltage gain '" Rl;2 R2 x F (The filter itself introduces a 3dS gain) (Rl +R2

Note 3

~rCM
IN

14
.<

-:!- GNoA
Note 2. Receive galO '"

DR

~ 10k).

R3R+~4

(R3 +R4 ~ 10k)
In the configuration shown, the receive filter power amplifiers will drive 8 6oo!lT to R termination to a signal level of 8.Sd8m.
An alternative arrangement, using a transformer winding ratio equivalent to 1.414:1 and 300n resistor, AS. will provide a
maximum signal level 01' 10.1 dBm across a 600S 2 termination impedance.

6-25

DESCRIPTION OF PIN FUNCTIONS
Pin
No.

Name

Function

VFxl+

The non·inverting input to
the transmit filter stage.
The inverting input to the
transmit filter stage.
The output used for gain
adjustments of the transmit
filter.
The low power receive filter
output. This pin can directly
drive the receive port of an
electronic hybrid.
The input to the receive filter
differential power amplifier.
The non-inverting output of
the receive filter power
amplifier. This output can
directly interface conventional transformer hybrids.
The inverting output of the
receive filter power amplifier.
This output can be used with
PWRO + to differentially
drive a transformer hybrid.
The negative power supply
pin. Recommended input is
-5V.
The positive power supply
pin. The recommended input
is 5V.
The input pin for the receive
filter stage.

2

VFxl-

3

GS x

4

5

PWRI

6

PWRO+

7

PWRO-

8

Vee

9

Vec

10

II

Pin
No.

Name

Function

11

GNDD

Digital ground input pin. All
digital signals are referenced to this pin.

12

ClK

Master input clock. Input fre·
quency can be selected as
2.048 MHz, 1.544 MHz or
1.536 MHz.

13

PDN

The input pin used to power
down the HC-5512 during
idle periods. logic 1 (Vee)
input voltage causes a
power down condition. An in·
ternal pull·up is provided.

14

ClKO

This input pin selects internal counters in accordance with the elK input
clock frequency:
ClK

Connect ClKO to:

2048 kHz
1544 kHz
1536 kHz
An internal
provided.

Vee
GNDD
Vee
pull-up

15

GNDA

Analog ground input pin. All
analog signals are refer·
enced to this pin. Not internally connected to GNDD.

16

VFxO

The output of the transmit
filter stage.

. TYPICAL PERFORMANCE CHARACTERISTICS

Transmit Filter Stage

Receive Filter Stage
10

10

II

-10

~

-20

::>

0

-30

5

-40

w

iE
<[

1\

-10

~

I

t--

FlllJEll.lm

x:p

w

0

-30

iE

-40

<[

-60

SIN

FREQUENCY (kHzl

,f

X=

800 0

1

-70
10

0.1

~/X

-50
-60

-70

6-26

I IIII ~ -H t!rl TER

-20

::>

....
:;

-50

is

1

10

0.1

FREQUENCY (kHz)

FUNCTIONAL DESCRIPTION
The HC-5512 monolithic filter contains four main
sections; Transmit Filter, Receive Filter, Receive
Filter Power Amplifier, and Frequency Divider/
Select Logic (Figure 1). A brief description of the
operation for each section is provided below.
Transmit Filter
The input stage of the transmit filter is a CMOS operational amplifier which provides an input resistance of
greater than 10Mn ,a voltage gain of greater than
10,000, low power consumption (less than 3mW), high
power supply rejection, and is capable of driving a
10kn load in parallel with up to 25pF. The inputs and
output of the amplifier are accessible for added flexibility. Noninverting mode, inverting mode, or differential amplifier mode operation can be implemented
with external resistors. It can also be connected to
provide a gain of up to 20dB without degrading the
overall filter performance.
The input stage is followed by a prefilter which is a
two-pole RC active low pass filter designed to attenuate high frequency noise before the input signal enters
the switched-capacitor high pass and low pass filters.
A high pass filter is provided to reject 200Hz or lower
noise which may exist in the signal path. The low pass
portion of the switched-capacitor filter provides
stopband attenuation which exceeds the 03 and 04
specifications as well as the CCITT G712 recommendations.
The output stage of the transmit filter, the postfilter,
is also a two-pole RC active low pass filter which
attenuates clock frequency noise by at least 40dB.
The output of the transmit filter is capable of driving a
±3.2V peak to peak signal into a 10kn load in paralle~
with up to 25pF.
-Receive Filter
The input stage of the receive filter is a prefilter which
is similar to the transmit prefilter. The prefilter
attenuates high frequency noise that may be present on

the receive input signal. A switched capacitor low pass
filter follows the prefilter to provide the necessary
passband flatness, stopband reejction and sin x/x gain
correction. A postfilter which is similar to the transmit
postfilter follows the low pass stage. It attenuates
clock frequency noise and provides a low output
impedance capable of directly driving an electronic
subscriber-line-interface circuit.
Receive Filter Power Amplifiers
Two power amplifiers are also provided to interface to
transformer coupled line circuits. These two amplifiers
are driven by the output of the receive postfilter
through gain settling resistors, R3, R4 (Figure 2). The
power amplifiers can be deactivated, when not required, by connecting the power amplifier input (pin
5) to the negative power supply VBB. This reduces the
total filter power consumption by approximately
10mW-20mW depending on output signal amplitude.
Power Down Control
A power down mode is also provided. A logic 1 power
down command applied on the PDN pin (pin 13) will
reduce the total filter power consumption to less than
1mW and clamp the power amplifier output to VBB.
Connect PDN to GNDD for normal operation.
Frequency Divider and Select Logic Circuit
This circuit divides the external clock frequency down
to the switching frequency of the low pass and high
pass switched capacitor filters. The divider also contains a TTL-CMOS interface circuit which converts the
external TTL clock level to the CMOS logic level
required for the divider logic. This interface circuit can
also be directly driven by CMOS logic. A frequency
select circuit is provided to allow the filter to operate
with 2.048MHz, 1.544MHz or 1.536MHz clock frequencies.
By connecting the frequency select pin
CLKO (pin 14) to VCC, a 2.048MHz clock input
frequency is selected. Digital ground selects 1.544MHz
and VBB selects 1.536MHz.

II

I

APPLICATIONS INFORMATION
Gain Adjust
Figure 2 shows the signal path interconnections be-

tween the HC-5512 and HC-5510 single channel
The transmit RC coupling components
CODEC.
have been chosen both for minimum passband droop
and to present the correct impedance to the CODEC
during sampling.
Optimum noise and distortion performance will be
obtained for the HC-5512/HC-5512A filter when
operated with system peak overload voltages of +2.5V
to +3.2V at VFxO and VFRO. When interfacing to
a PCM CODEC with a peak overload voltage outside
this range, further gain or attenuation may be required.

the HC-5510/5511 series CODEC which has a 5.5V
peak overload voltage. A gain stage following the
transmit filter output and an attenuation stage following the CODEC output are required.
Board Layout
Care must be taken in PCB layout to minimize power
supply and ground noise. Analog ground (GNDA) of
each filter should be connected to digital ground
(GNDD) at a single point, which should be bypassed
to both power supplies. Further power supply decoupling adjacent to each filter and CODEC is recommended.
Ground loops should be avoided, both
between GNDA and GNDD and between the GNDA
traces of adjacent filters and CODECs.

For example, the HC-5512 filter can be used with

6-27

He-5531

HARRIS

Automatic line
Balance Network
FEATURES

DESCRIPTION

• MONOLITHIC LSI DEVICE
• NO EXTERNAL COMPONENTS REQUIRED
• AUTOMATIC SELECTION OF BALANCE NETWORK
FOR LOADED ANO NON-LOADED LOOPS
• SOFTWARE CONTROLLED LOSS IN .1dB STEPS
• SOFTWARE CONTROLLED GAIN/LOSS IN.1 dB STEPS
• LOW POWER CONSUMPTION CMOS PROCESS
• COMPATIBLE WITH EXISTING MONOLITHIC PCM
CHANNEL FILTERS
• COMPATIBLE WITH TRANSFORMER-COUPLED OR
SOLID-STATE SLiC's

The HARRIS HC-5531 Automatic Line Balance Network
(ALBN) is a monolithic LSI device for application in digital
telephone switches.

APPlICA TION
• OIGITAL TELEPHONE SWITCHES
•

The HARRIS ALBN enhances the transmission performance
of digital telephone switches by minimizing the singing margin
of a connection through automatic selection of balance networks.

2-4WIREJUNCTIONS

PIN ASSIGNMENTS

~: -i-"'-_-f'"~~+--

The device incorporates the elements required to perform
the automatic balancing of the loop using samples of the receive
and transmit signals. A signal processor selects the appropriate
balance network which provides maximum transhybrid loss
for either loaded or non-loaded subscriber loops. This type
of compensation is essential to maintain necessary singing margin
in a zero dB loss digital switch. A digitally controlled attentuator in the receive path with 1dB steps allows loss insertion
to be performed in the line card. Gain/loss control in .1dB
steps for fine adjustment is also available.

INSTAllATION DIAGRAM

_ _ _ _-t-_-RVIOUTI

AVUNI

AUTOMATIC
LINE

FILTER

BALANCE

.--_-i-_+TXUNI

NETWORK
TXloUT)

-TXUNI

A.I

TRANSFORMER..(:OUPLED SUBSCRIBER LOOP

RVUNI
AUTOMATIC
CLOCK
SELECT

SDlIO-

LINE
BALANCE
NETWORK

FILTER

TXtOUTI

STATE

sLie
+TX(lN)

-TXUNI
DOW.
""''"

BJ SOLID-STATE

CE

DATA

DATA

elK

SERIAL

FUNCTIONAL DIAGRAM SHOWING PIN ASSIGNMENTS
(HC-5531)

6-28

sLie

SPECIFICA TlONS HC-5531

TYPICAL
VALUE

UNIT

+5, -5

Volts

35
35
35

dB
dB
dB

Insertion Loss Error
0,1,2,3 or 6 dB Setting

±.01

dB

Fine Gain/Loss Error
.1 dB to .5dB in .1 dB Steps

±.OI

dB

PARAMETER
Supply Voltage
Return Loss
Cable:

1650nt /O,005p F {loaded}
soont /.05pF (Nonloaded)
900n+2.15!J F (standard)

Input Impedance
(All Analog Inputs)
Output Amplifier
Maximum Signal Capability

100

NOTE

kn

+10

dBm

Idle Channel
Noise

5

dBrnCo

Oistortion

.1

%

Power Dissipation
Operation:
Power Down:

75
1

mW
mW

1

2

NOTES:
1.
2.

Receive output driving 450n+ 450n(Balanced}
Same as Note 1 with 0 dB m signal level.

6-29

mHARRIS

HV-1000/1005/1010
Induction Motor
Energy Saver

Preliminary
FEATURES

DESCRIPTION

• OPERATES DIRECTlY OFF 110/220V AC LINE - NO
POWER SUPPLY REQUIRED
• PRODUCES POWER SAVINGS OFF FROM 10% TO 50%
FOR MOTORS WITH LIGHT OR VARIABLE LOADS
• SCR OUTPUT STAGE TRIGGERS TRIAC DIRECTlY
• LOAD ANTICIPATOR SENSES SHOCK LOADS AND
RESPONDS INSTANTLY WITH FULL POWER

The HV-l000/l005/1010 are energy saving induction motor
controller circuits specifically designed for use with 110/220
volt AC single phase induction motors to reduce power
consumption.
The controller circuit senses the load on the motor and then
controls a TRIAC to apply reduced voltage to lightly loaded
motors, full voltage to heavily loaded motors.

• WITHSTANDS LINE SURGES TO 2000V
• CAUSES MOTOR TO RUN QUIETER, COOLER
• CAN BE MOUNTED INSIDE MOTOR
• NEEDS ONLY 3 RESISTORS, 2 CAPACITORS AND A
TRIAC TO ASSEMBLE COMPLETE CONTROLLER

APPlICA TIONS

The HV-l000/1005/1010 is available in a 16 lead DIP.
Ideal for mounting inside induction motors, it can also be
mounted in a heat sunk circuit box for external, after market
application.

PINOUT
TOP VIEW

• POWER TOOLS
• WATER PUMPS

II

AC La

• HEAT PUMPS

CAP B

• PRESSES
• CONVEYORS

CAPA
POT 3
POT2

• COMPRESSORS
~ ANY APPLICATION WHERE FOR SOME OF THE
TIME THE MOTOR IS DRIVING LESS THAN ITS
RATED LOAD

ACHI

SENSE

POT 1
CONTRa L RETU RN
GATE La

GATE HI

FUNCTIONAL DIAGRAM
POT 1 POT Z POT 3 CAP A CAP B SENSE

IN 0--+-"'"
LO

6-30

...--+--U

GATE
HI

'---+--0

GATE
LO

SPECIFICA TIONS
ABSOLUTE MAXIMUM RATINGS
Input Voltage (With Input Resistor)
Input Voltage (Without Input Resistor)
Power Dissipation
Operating Temperature Range

±2000V
±600V
SOOmW
-2SoC to +8SoC
-400C to +1 OooC
3000 C
SOOmA

~torage

Temperature
Lead Temperature (Soldering, 10 seconds)
Output Current (10 microsecond pulse)

ELECTRICAL CHARACTERISTICS
These characteristics apply to the HV-l000!100S!1010 operating off 60Hz AC li~e power. HV~1000!100S!1010
respectively should be selected so that the full load power factor of the controller approximately matches that of
the motor. The motor power factor V- I ~atts
at full load, which should be measured experimentally.
at mperes
"

FULL LOAD POWER FACTOR,
HV-l000
.86

,

HV-l00S

HV-l0l0

.78

.68

I

PARAMETER

MINIMUM

Difference Between Positive and Negative
Triggering Times, Measured from Line
Voltage Zero Crossing
Output Stage Breakover Voltage

±GOO

MAXIMUM

UNITS

7S

IJsec

II

I

V

NOTES:
1. Selection of HV-l000!100S!1010 by matching the full load power factor of the motor to that of the controller
ensures that the controller will apply full voltage to the motor at' its full" rated load. At reduced loads, the
controller will then apply appropriately reduced voltage to the motor so that its power consumption is reduced.
2. No guarantee of power savings can be given since the savings achievable depend entirely on the motor and its
application. For a motor driving only a flywheel (e.g. a circular saw or a bench grinder) a power reduction of
SO% may often be observed when the too} is switched on but not in use. For typical variable load applications,
an avera!! power reduction of 10% is likely to be observed.

6-31

TYPICAL APPLICATION CIRCUIT

1/2 OPTIONAL PHASE SET
WATT
500012

110/220V
A.C.LlNE

5k

fs

'i6

POT 1
IN HI

PROTECTION

r
1

A.C. NEUTRAL

.

t5
POT 2

14
POT 3

TIME
CONSTAN~e
CAPACITOR

r;i ~:47"
CAPA

HV-l000/1005/1010

LI_N_LO_ _ _

MOTOR 3/4 HP

F

CAPB
100kn
SENSE 13 ' ..
PROTECTION
GATE HI

i91

1

~~

. . :;~ :;.:~r.1 ;: :~:. L_ _ _G_A_TE_L....I0
1

TR~

1 WATT
300n
SNUBBER
600V

1 T·

22 • F

FIGURE 1
NOTES:
1. An optional potentiometer may be attached as shown
to any of the three versions of the circuit and used to
set the full load power factor. If the potentiometer is
omitted, the full load power factor will be as defined in
the electrical characteristics. With the potentiometer
connected power factor may be adjusted from O.S to
0.9 for all three circuits.

2. A small number of motor designs exist which cannot be
controlled in a stable fashion by HV-l000/l00S/l0l0.
The symptoms of instability are irregular vibration and
jerky rotation of the shaft. This instability is seldom
observed with motors driving a pulley, flywheel or equivalent inertial load. It may be helped by increasing the
inertia in the load driven by the motor. Sometimes
the use of either larger or smaller time constant capacitors
will also help. Occasionally examination of the waveform
across the time constant capacitor with an oscilloscope
will show the presence of a low level instability which is
usually insignificant. (1) Normally this voltage shOUld be
steady when the motor and controller are in equilibrium.

II

. 3. The HV-l000/100S/1010 contains a circuit which allows

it to respond within one cycle of the power line to a
shock load. In this circumstance full power is applied
to the motor immediately.
4. The TRIAC should be chosen to have a continuous
current rating equal to the current drawn by the motor.
In most applications heat sinking will be required to
remove the heat produced by the power dissipation of
the TRIAC.
S. The snubber circuit is required to prevent the SCR
output stage being triggered inadvertently by the voltage
transient which would otherwise appear across the TRIAC
at the moment of current zero crossing.
6. In the event of a line voltage surge in excess of 600V,
a protection SCR between pins 1 and 16 breaks over and
latches down to approximately 2V, dropping the surge
voltage across the SK protection resistor. The SCR can
withstand O.4A for 1 millisecond, allowing 2000V surges
to be tolerated. The output stage is self protecting since
it consists of SCRs which break over and turn on the
TR lAC so that the surge voltage is dropped across the
motor.

THEORY OF OPERATION
Induction motors run at a speed which depends primarily
on the supply frequency, little on. voltage. They draw
almost a constant current regardless of the load - the motor
responds to load with a change in power factor. Thus, a
lightly loaded motor wastes energy by heating its windings
with inductive current. The HV-l000/100S/1010 measures
the load using the current phase angle and then saves power
by applying to the motor only sufficient voltage to drive
the load. (2) Since the voltage is adjusted by TR lAC phase
control a side benefit of the controller is power factor
correction.

the motor. This varies the RMS voltage across the motor.
The resulting voltage waveform across the motor is shown at
the top of Figure 2. A motor can be characterized by the
relation between the two parameters
c and -9-t, shown
in Figure 2 for a typical motor. At point A, the motor is
running fully loaded with full voltage applied, as it was
designed. At point B, the motor is running lightly loaded
with voltage reduced to the point of stalling. The function of
the controller is to force the motor to operate along the load
line AB, rather than AC which it does naturally. Figure 3
shows an example of the typical power savings which results
when the controller chip is incorporated in a motor.

-e

The controller chip triggers a TRIAC which is in series with
(1) For safety it is recommmended not to connect the ground clip on the scope probe when performing
this measurement.
(2) This circuit principle was first described by F. J. Nola in U.S. Pat. 4052648.

6-32

THEORY OF OPERATION (continued)

The key features of the circuit are firstly that all the analog
processing is carried out with the circuitry running entirely
on 60Hz alternating current. Direct current is not used at
all. Secondly it is integrated using dielectric isolation, with
junction breakdowns of 400V. Junctions are stacked in both
the input regulator and the SCR output stage so that the
composite breakdown voltage of these stages is ±600V.
The analog processing which achieves the control function is
explained conceptually in Figure 4. At any given load
condition the controller tries to force the motor current
phase Bc to a pre-programmed set phase. The phase to
voltage converter measures the difference between the set
phase and Bc, and increments a pedestal voltage at a rate
proportional to the difference, delaying the trigger point
Bt where a reference ramp intersects the pedestal. The
delayed triggering reduces the voltage applied to the motor,

decreasing the motor winding current so thatec is forced to
the set phase by the modulation of -B-t. The set phase is
itself a slow function of B-t, which produces the sloping
controller characteristic of Figure 2. This is achieved via
the feedback path from the output stage to the phase to
voltage converter.
An additional feature of the phase to voltage converter is
the load anticipator. If Bc is ever more than O.5msec less
than the set phase, which means the motor has received a
sudden heavy load, the full line voltage is immediately
applied to the motor. This allows the motor to respond
at once to a step function load. If the load is abruptly removed, the controller cuts back the voltage applied to the
motor over a time period of typically one second, set by the
external time constant capacitor.

MOTOR
VOLTAGE

WAVEFORM

-eC

CURRENT ZERO
CROSSING

-&t :~::~ TRIGGER

II

LlGHTl Y

I

LOADED MOTOR
WITH REDUCED
VOLTAGE

(MAX VOL lAGE)

-9-t

{MSECSJ

(MIN VOL lAGEI

FIGURE 2 - Voltage Waveform Characteristics of a TRIAC Controlled Induction Motor

POWER INPUT % RATED LOAD

..0
POWER OUTPUT % RATED LOAD

lotiO

FIGURE 3 - Power Savings as a Function of Load for a 1/3 HP Motor

6-33

THEORY OF OPERATION (continued)

~_MOTO.

i

:

1

~;:~

LINE VOLTAGE
I

SET
PHASE

f:i--'
IV

\r "v/-!

I
I

_-....

I /'"

CURRENT

"

MOTOR
BAC~EMF

I

f\1
VOLTAGE

I
I

~

. . ___ . . ,/ I
I
I

i

!:o';O~i;:SE I

I I &SETPHASE I

~_ TRIGGERPDlNT
te.l

I
PEDESTAL

'............,

~

I

ANAlOG.ROCESSING

I~!
FIGURE 4 - Relation of the Voltage and Current Waveforms to the Analog Processing Function

APPlICA TIONS INFORMATION

.-----------------------------------------I~:

+'
Improvement of the efficiency of single phase induction
motors' may be achieved in two ways. For motors which
drive a steady load equal to their rated capacity, the best
method is to use a run capacitor with an auxiliary winding.
This causes the internal ;field structure of the motor to
re~emble that of a three ph~e motor, an inherently more
efficient arrangement. How~er, if a capacitor run motor
is used to drive less than its rated load, its power consump.,.
tion will usua"y· be greater than a motor without a run
capacitor, so if this is the case for a significant fracti~n of the
time a run capacitor is not effective for improving efficiency.
By contrast an electronic ~nergy saving motor controller
produces significant improve,ments in efficiency for lightly
loaded motors and is therefore the best choice for motors
which spend a significant part of their time lightly loaded.
Electronic energy saving controllers are useful for power
tools, water pumps, heat pumps, presses, conveyors, compressors and commercial washing machines, in other words
for any application where the load on the motor is either
variable or ill defined. Run capacitors are useful for refrigerat!lrs, air conditioners, and ventilation fans - a" applcations where the load on the motor is steady al)d we"
defined. An electronic energy saving controller should not
be applied in a circumstance where a mcttor is driving a

II

6-34

constant, steady load equal to its rated load. In this circumstance the power dissipated in the TRIACs may actually
increase the total power usage. However it sometimes
happens that induction motors are relatively conservatively
designed, and the real power capability of the motor is
greater than that stated. This may come about, for instance,
because the motor may have been designed to operate with
worst case low line voltage, say, 100V for a nominal 115V
motor. In such a circu mstance an electronic energy saving
controller can produce useful savings because in realityc the
conservative design of the motor is causing it to be operating
at less than its full capability. This circumstance can be
Jested experimentally ~y connecting a power meter to the
motor and then adjusting the set power factor with a potentiometer on the controller circuit to test whether reduced
power consumption can be obtained. Once set up in this
way, the controller will continue to give the motor just
sufficient voltage to drive the load in hand, even if the line
voltage drifts high. In other words, the energy saving controller also acts as a line voltage regulator. This is especially
beneficial in areas where the line voltage fluctuates, since
-high line voltage can cause an induction motor to consume
excessive amounts of power.

Harris Hi-Rei Products
..................................
'II~II~II......

Harris takes the Total Approach to Hi-Rei
High-Reliability does not occur
by accident in microcircuit
manufacturing. It can be
achieved only as a result of
informed planning, precise
design, careful manufacturing
methods, scrupulously controlled production processes,
accurate screening, and
exhaustive testing.
In short, reliability must be
totally designed and
manufactured into the product.
It is not a characteristic that
can be added after
manufacture. It must be part
and parcel of the flow from

original design through final
assembly and test.
The major steps affecting
microcircuit reliability are:
• Initial circuit selection and
design
• Die layout and geometry
• Raw material inspection
and'QC
• Wafer/die production
process and controls
• Die/package assembly and
controls
• Burn-in techniques
• Screening and test
procedures

•

7-1

I

Harris Hi-ReI Flows
Harris recognized early that a
single grade of Hi-Rei devices
would be inadequate for such
varied customer requirements
as critical commercial equipment, manned space missions,
sensitive industrial systems, exacting avionic instruments and
demanding military applications. Realizing, further, that
custom-tailoring each product
manufacturing flow to meet individual order specfications
would result in prohibitive
costs, Harris developed and
now offers devices in four different standard Hi-Rei grades
which, together, will accommodate the requirements of virtually all users.
Not all devices are available
in all grades, of course. For
up-to-date availability information, refer to the applicable
data sheets or contact either the
factory or the local Harris
Semiconductor representative.
Produced in accordance with
different manufacturing flows,
the standard Harris Hi-Rei
grades and their indicated areas
of application are as follows:

•

7-2

as is JAN Class B. DASH-2 and
DASH-8 are tested electrically
per the criteria defined
in the applicable Harris
data sheet.
• DASH-7 is a DASH-8
equivalent for commerical applications. DASH-7 receives a
96-hour burn-in and is tested
over the O°C to + 75°C
operating range. DASH-7
screening is available on Harris
Linear Circuits only.
• JAN Class B - Most military
weapons systems and certain
other military hardware use
JAN Class B microcircuits.
JAN Class B devices receive
essentially the same environmental/mechanical screening as Harris DASH-8 products. JAN Class B circuits, in
addition, are purchased to a
MIL-M-3851O Slash Sheet,
which calls out stringent electrical screening and an extensive system of manufacturing
controls, reliability and Quality
Assurance procedures.

• DASH-2 (MIL-STD-883
Class C) is designed for general
use in a military temperature
range environment. Performance is guaranteed over a
temperature range of - 55°C to
+ 125°C.

Advantages of Standard
Flows

• DASH-8 (MIL-STD-883
Class B) provides the same basic
screening flow as DASH-2 with
the addition of a 160-hour
burn-in. The burn-in cycle
results in accelerated failure of
marginal devices or those which
may be subject to infant mortality. DASH-8 is intended to
be used in general-purpose Hi~el appli~ations .
Note the DASH-2 and DASH-8
product are not fully defined by goverment specifications

Wherever feasible, and in accordance with good value
engineering practice, the IC
user should specify Hi-Rei
device grades based on one of
the four standard Harris
manufacturing flows. These are
more than adequate for the
overwhelming majority of
applications and may be
utilized quite easily if
the user engineer bases his
designs on the standard data
book or slash sheet (as applicable) electrical limits.

Some of the more important
advantages gained by using
standard as opposed to custom
flows are as follows:
• Lower cost than the same or
an equivalent flow executed on
a custom basis. This results
from the higher efficiency
achieved with a constant product flow and the elimination
of such extra cost items as
special fixturing, test programs,
additional handling, and added
documentation.
• Faster delivery since the
manufacturer often can supply
many items from inventory
and, in any case, can establish
and maintain a better product
flow when there is no need to
restructure process and/or test
procedures.
• Increased confidence in the
Hi-Rei devices, for a continuing flow of a given Hi-Rei product permits the manufacturer
to monitor trends which may
bear on end-product performance or reliability and to effect necessary corrective action.
• Reduction of risk, since
each product is processed independent of specific customer
orders, permitting lot failures
to be absorbed within the
scheduling framework without
impacting on the customer's
needs. In the case of a custom
Hi-Rei flow, a lot failure late in
the production cycle can result
in significant delays in delivery
due to the required re-cycling
time.
Despite the advantages of using standard Hi-Rei flows,
there are cases where a special
or custom flow is mandatory to
meet design or other requirements. In such cases, the
Harris Analog and Digital
Marketing groups stand ready
to discuss individual customer
needs and, where indicated, to
develop appropriate custom
flows.

HARRIS SEMICONDUCTOR
STANDARD HI-REL PROCESSING FLOWS
IN-HOUSE
ANALYTICAL
CAPABILITY

INCOMING
MATERIAL
AND
CHEMICAL
INSPECTION

SEM
ION IMPLANT
PLASMA ETCHING

DASH-2
(MIL-STD-883
CLASS C)

DASH-8
(MIL-STD-883
CLASS BI
DASH-7 (11

JAN CLASS B

AS
APPLICABLE

AS
APPLICABLE

AS
APPLICABLE

AS
APPLICABLE

AS
APPLICABLE

REOUIRED
CONTROLS
PER
MIL-M-38510
CLASS B
AS
APPLICABLE

•

FILM THICKNESS

I

THIN FILM
TECHNOLOGY

I

SPUTTERED
ALUMINUM
PROJECTION
ALIGNMENT
CVPLOT
PHOTO RESIST
TOLERANCES
IMPLANT
PROFILES
COMPOSITIONS
IN-PROCESS
PROBES FOR HFE,
CEOi=' PNP" NPN"
OIF USEu ANu
THIN-FILM
RESISTORS
(1 ITA = -55 0 C to +125 0 C for all grades except
DASH-7 (DASH-7 T A = OOC to +750 cl

7-3

HARRIS SEMICONDUCTOR
STANDARD HI-REL.PROCESSING FLOWS
(continued)

LASER
TRIMMING
AT BOTH
PACKAGE AND
WAFER LEVELS

,...---------, r""""""'-'---, , - - - - , ,----.,
VISUAL
INSPECTION
PER
MIL-STD-BB3,
METHOD 2010.
CONDITION B,
WITHQC
MONITOR

VISUAL
INSPECTION
PER
MIL-STD-8B3.
METHOD 2010,
CONDITION B,
WITHQC
MONITOR

VISUAL
INSPECTION
PER
MIL-STD-BB3.
METHOD 2010.
CONDITION B,
WITH QC
MONITOR

YES

YES

YES

YES

YES

YES

NO

NO

NO

YES

YES

YES

4-HOUR

4-HOUR

4-HOUR

Pre-Seal Clean

AS REQUIRED

AS REQUIRED

YES

Pre-Seal Inspect

PER
MIL-STD-8B3
METHOD 2010,
CONDITIONB

PER
MIL-STD-BB3
METHOD 2010,
CONDITIONB

PER
MIL-STD-8B3
METHOD 2010,
CONDITION B

YES

YES

YES

NO

NO

YES

YES

YES

YES

YES

YES

YES

Stabilization Bake

YES

YES

YES

PROBE/DICE
PREPARATION

HIGH/LOW
TEMP
PROBE TEST

ASSEMBLY (2)(3)

DIE ATTACH
CONTROL

Lead Frame Clean

WIRE BONO
CONTROL
PRE-SEAL
WASH IN
LAMINAR
FLOW

QA Wire Bond
Control

PRE-SEAL
VISUAL
INSPECTION
IN CLASS 100
LAMINAR
FLOW
QA Seal Control

PARTICLE
IMPACT NOISE
DETECTION
(PIND)
PER
MIL-$TD-883,
METHOD 2020,
AS
REQUIRED

(2) All test methods and conditions are as prescribed
in MIL-STD-883, Method
5004 and 5005, for the

T emperatu re Cycle

YES

YES

YES

Centrifuge

YES

YES

YES

Tin-Plating

YES

YES

YES

YES

YES

YES

Fine Leak Test

YES

YES

YES

QA Tin-Plating
Inspect

G ross Leak Test

YES

YES

YES

PIND Test 100%

AS
APPLICABLE

AS
APPLICABLE

AS
APPLICABLE

Frame Removal

YES

YES

YES

Load Shipping Tubes

YES

YES

YES

QA Final Inspect

YES

YES

YES

QA Documentation
Inspect

NO

NO

YES

respective class.
(3) Example for a Cerdip
package part.

7-4

.

HARRIS SEMICONDUCTOR
STANDARD HI-REL PROCESSING FLOWS
(continued)

TEST

@ = Operation
@ = QA Monitor

lOW NAND-AMP
AC/OC SINGLE
INSERTION TEST
CAPABiliTY;
HIG H/lOW TEMP
BURN-IN
QUALITY
CONFORMANCE
BY Mll-STD-883
METHOD 5005,
GROUPS A, B, C,
AND D AS
REQUIRED
DELTAS PER
SLASH SHEET
REQUIREMENT
IN-HOUSE
PACKAGE
MOISTURE
MONITOR
CAPABILITY
COMPUTERIZED
lOT
TRACEABILITY
MONITORING
SYSTEM

Brand SEM Lot Number

NO

NO

Inspect

NO

NO

NO

Electrical Test Sorting
Operation

YES

YES

YES

Serialize

NO

NO

GROUPAAND
CSAMPLES
ONLY

NO

Inspect

NO

NO

NO

Pre Bum-In Electrical
Test

NO

YES

YES

Burn-In

NO

DASH-8:
160HR@
+125 0 C
DASH 7:
96HR@
+125 0 C

160HR@
+125OC.OR
PER
SLASH SHEET

Test Same as Pre
Burn-In

NO

YES

YES

Apply Burn-In PDA
(as applicable)

NO

NO

PER SLASH
SHEET

NO

NO

NO

Brand

YES

YES

YES

External Visual

YES

YES

YES

NO

GROUP A

GROUPA.B,
C,D

NO

PER
PURCHASE
ORDER

YES

Visual and
Mechanical Inspect

Quality
Conformance
Inspection
Final Data Review

Package & Ship
or Stock

7-5

Initial Circuit Selection
and Design
There are, of course, many different circuit configurations
capable of handling any given
task, once operational
characteristics and parameter
limits have been established.
Harris designers choose those
which are capable of meeting
the required performance
specifications with maximum
reliability.
Powerful computer aided
design (CAD) techniques are
applied in developing the
original circuits, with computer
modeled circuit simulation used
to corroborate projected product performance. Monte Carlo
methods, ISPICE programs,
and other simulation techniques
are used, as appropriate to the
specific design.
Regardless of the circuit
approach selected, high
reliability, top performance,
and maximum potential yield
are the governing criteria.
Individual active device types
and component values are
selected to provide optimum
circuit performance and to
minimize sensitivity to
parametric changes which may
occur with aging or as a result
of application environmental
conditions.

•

Die Layout and Geometry
IC die conformance with good
layout practice is a must, for

consistently reliable devices
cannot be assembled from
poorly designed dice.
Therefore, the IC die layout.
phase at Harris is controlled by
ground rules which establish
the "do's" and "don'ts" for
each manufacturing process.
These rules define dimensions
and tolerances for ensuring
product immunity to process
variations, while maximizing
product reliability under worstcase stress conditions. Computerized ground rule program
packages are used by the chip
designers to assure dimensional
adherence of diffusion windows
as well as interconnect width
and spacing. Automatic
checkout procedures confirm
that the product conforms to
the established ground rules.

Raw Material Inspection
and QC
Acknowledging that Hi-Rei,
high performance devices can
be manufactured only by using
top quality materials, Harris
subjects incoming materials,
piece parts and supplies to
rigorously documented tests
and inspections. The techniques
used are selected for optimum
evaluation of the materials
checked to ensure full compliance not only with Harris internal specifications, but with
applicable standards, including
MIL-STD-883 and MILM-38510.

POL YCRVSTALLINE SUBSTRATE

Cross-sectional view of high-frequency
PNP device formation in the 01 process.

7-6

Wafer Die Production
Process and Controls
Harris has a wide range of
state-of-the-art wafer and die
processing capabilities, permitting the chip designer to choose
the optimum production technique for each type of device.
Depending on specific design
and performance specifications,
devices may be fabricated using
either conventional or complementary bipolar, CMOS,
combined bipolar and CMOS,
NMOS or PMOS construction.
Two different complementary
vertical bipolar processes are
available, offering frequency
responses two orders of
magnitude higher than conventional designs.
Regardless of the fabrication
technique used, extensive controls and checks are incorporated within each process
technology to ensure high
yields, close adherence to target
specifications, and full conformance with all standards applicable to the specific Hi-Rel
class.
With high reliability an integral part of its manufacturing
philosophy, Harris Semiconductor does not have separate production lines for standard and
Hi-Rei devices. Rather, all Harris
devices of a given type are
manufactured on the same line.
Hi-Rel devices are selected by
the application of screening tests
and control procedures including

Dielectric isolation eliminates latch-up
by placing a silicon-dioxide isolation
barrier between devices. This separates
all active elements, eliminating interface
junctions that cause parasitic SCRs.

a comprehensive burn-in program. Compliance with overall
quality assurance goals is proven
by lot acceptance in accordance
with applicable quality
conformance test standards.

Die/Package Assembly
and Co'ntrols
Many mechanical and environmental compliance tests
are implemented during the
die/package assembly stage.
The specific controls and tests
utilized at each step are in strict
compliance with the applicable
standards for the device
reliability class designation.

Burn-In
An essential part of Harris HiReI flows, 1000/0 burn-in is a
screening procedure used to
detect devices subject to infant
mortality failure modes. Biases
are applied to simulate worst-

case operational conditions,
permitting the identification
and elimination of marginal
units.
The applied voltage levels,
operational state, temperature
and test period vary with the
type of device and reliability
class, as governed by the applicable standards. Electrical
test of the device is performed both prior .to and after the
burn-in period.

battery of internal QA and QC
tests to assure compliance with
the rigorous Harris production
standards.
Harris internal QA and QC
tests are in full compliance with
Appendix A of MIL-M-3851O
for all JAN Class B devices.
For DASH-2, DASH-7, and
DASH-8 devices, Harris
imposes a QA and QC
program derived from and
comparable to the same standard.

Screening and Test
Procedures
While many factors are critical
in the production of Hi-Rei
devices, the screening and test
procedures, considered as a
group, are critical to
establishing reliability grade
levels. In addition to
the test procedures
required by the purchase
specification, all Harris devices
must undergo an exhaustive

Reliability Assessment and Enhancement

•
I

At Harris, reliability assurance
is a dynamic program with the
primary and ultimate goal of
securing full product adherence
to all applicable standards and
specifications. Each phase of
the manufacturing operation
from original design to final
packaging is subject to continuous review, analysis, and
evaluation, with modifications
introduced when needed to
improve product performance
and reliability.

The Design Phase
The initial design is not only
the first step in producing a
new device, but can be one of
the most important in determining product reliability, for

without sound design practice,
neither extensive process controls nor intensive down line
testing can positively assure
product reliab;ility.
At Harris, a~1 new products
are developed using a proven
set of design rules. Derived
from composite inputs supplied
by the Product Design,
Manufacturing, Sustaining Product Engineering, Quality
Assurance and Reliability
Departments, the design rule
package is subject to a continuing review. These procedures
ensure that all designs conform
to state-of-the-art engineering
practice.

Process Control and
Evaluation
Harris is extremely conscious
of process-related problems
which may contribute to
degradation of reliability. All
fabrication processes are accurately documented, with
process and other program
specifications under configuration control and subject to
change only through formal
ECN. Among other measures,
critical parameters are
monitored constantly by the
Process Engineering, QC, QA,
Sustaining Product Engineering
and Reliability Departments,
which then investigate and suggest methods to enhance ,
reliability and improve yields.

7-7

The Harris Reliability Department
Charged with overall responsibility for the reliability of
Harris Semiconductor products, the Reliability Department is involved, as needed, in
all phases of the production cycle from original concept and
design through final packaging
and test. Among its major accomplishments, the Reliability
Department has implemented a
comprehensive multi-faceted
program to assure a continuing
high level of product and new
technology reliability prove-in.
The program comprises several
major activities, as follows:
• Add-On - One of the
overall activities is the
maintenance of an active
operating life test program called "Add-On." This program
provides an ongoing data base
and determines life trends.
Package integrity is verified, as
is qualification in accordance
with MIL-STD-883, including
residual moisture monitoring
inside the package cavity. In
practice, the latter is accomplished through the use of
a Harris-designed in-situ
moisture monitor cell. The
development and practical implementation of this revolutionary moisture-monitoring
technique culminated in DESC
Certification of Harris to supply moisture data.
Another facet of the Add-On
Program is the periodic release
of product and package
Reliability Bulletins. Representing the results of long-term
operating life testing, this information is routinely updated.
The current Reliability Bulletins and an applicable updated
index are available on request.

7-8

• Failure Rate Prediction Another important facet
of the comprehensive
reliability program, failure rate
prediction is used to extrapolate meaningful long-term
operating performance under
end-use conditions. Using the
Arrhenius relationship, derated
failure rates can be projected
using an activation energy for
the applicable process
technology.
• Failure Analysis An exhaustive analysis of
device failures is another
significant feature of the Harris
reliability program. Before the
Reliability Department proceeds with an analysis program,
the reported failure mode must
be confirmed by electrical tests.
After failure confirmation, the
device is processed through a
standard failure analysis
procedure.

Failure Analysis Flow

• Package Type/Vendor
Qualification
Since the integrity of packages
and associated piece-parts are
critical to the reliability of
assembled products, the
Reliability Department is charged with qualifying all vendorsupplied package types, both
initially and, on a continuing
basis, through ongoing
monitoring programs. The
qualification tests are in accordance with the rigorous MILSTD-883 procedures and ensure
full compliance with all
thermal, mechanical and environmental specifications.
• New Product/Process/
Module Qualification - In addition to the direct responsibilty
of assuring product reliability,
the Reliability Department
performs qualification of all new
products and processes. The
reliability qualification must be
completed before a new product can be transferred officially into production or offered
for sale.

Harris and the JAN
Program
Harris Semiconductor
became an active participant in
the JAN program as the first
microcircuit manufacturer to
JAN-qualify a PROM, receiving a QPL-2 qualification in
1972 and the higher level
QPL-l qualification in 1974 for
the military version of the
HPROM-0512, as defined by
MIL-M-3851O, Slash Sheet 201.
Since this initial effort, Harris

has received JAN line certification for the generic HM-76XX
PROM family. In early 1980,
Harris received JAN
certification for three additional production lines supplying Dielectrically Isolated (Dr)
operational amplifiers, analog
switches, analog multiplexers,
and Junction Isolated op amps.
Harris will continue to pursue further line certification

and part qualification efforts,
offering users an~ everexpanding line of JANqualified devices.
Full JAN-qualified products
can be supplied only in packaged form. However, Harris
stands ready to supply individual dice on special order
which have been processed
through probe/dice preparation
in accordance with indicated
JAN flows and controls.

,
MIL-M-~~J;101

QPL-2

High Performance
Amplifier

12202BGC

Now
Qualified

HA2-2620

Very Wide Band,
Uncompensated Op Amp

12203BGC

Now
Qualified

HA2-2500

Precision

12204BGC

Now
Qualified

TYPE
HA2-2600

FUNCTION
Oper",~ional

High Slew Rate Op Amp
HA2-2510

High Slew Rate Op Amp

12205BGC

Now
Qualified

HA2-2520

High Slew Rate
Uncompensated Op Amp

12206BGC

Now
Qualified

HA1-4741

Quad Operational Amp

11003BCA

Now
Qualified

•
I

Typical Harris Hi-ReI Government
Program Participation
NEARTIP (Torpedo)
CRUISE MISSILE (ALCM)
(TLCM)
(GLCM)
CAPTOR (Mine)
IUS (Shuttle Inertial
Upper Stage)
F15 (Aircraft)
F14 (Aircraft)
F16 (Aircraft)
F18 (Aircraft)

HARPOQN (Missile)
SPACE SHUTTLE
VIKiNG (Mars Lander)
GPS (Global Position Satellite
System)
ROLAND (Close in Air
Defense)
AMRAAM (Advanced Medium
Range Air-to-Air
Missile)
HELLFIRE (Anti-Tank
Missile)

757 (Commercial Aircraft)
767 (Commercial Aircraft)
SEASP ARROW (Missile
System)
WILD WEASLE (F-14)
MARK 48 TORPEDO
HARM (Hi-velocity AntiRadiation Missile)
AWACS (Airborne Warning
and Control System)
TACFIRE (Tactical Display
and Control System)

7-9

.....

Analog Application Notes
I1JLI1
...................................

PAGE
AN 509
AN 515
AN 517
AN
AN
AN
AN
AN
AN
AN
AN
AN

519
520
521
522
524
525
526
527
528

AN 529
AN 530
AN
AN
AN
AN
AN
AN

531
532
533
534
535
607

A Simple Comparator Using the HA-2620
Operation Amplifier Stability: Input Capacitance Considerations
Applications of a Monolithic Sample-and-Hold/Gated
Operational Amplifier
Operational Amplifier Noise Prediction
CMOS Analog Multiplexers and Switches
CMOS Devices for Analog Switching
Digital to Analog Converter Terminology
Digital to Analog Converter High Speed ADC Applications
HA-5190/5195 Fast Settling Operational Amplifier
Video Applications HA-5190/5195
Applying the H 1-5900 Analog Data Acquisition Signal Processor
Interfacing Microprocessors and Microcomputers with
HI-5712 High Performance 12-Bit AID Converter
Microprocessor Interface Methods for High-Speed Data
Acquisition Systems
A Data Acquisition and Conversion System With Less Than
± 1 LSB Offset Error
Analog Switch Applications in A/D Data Conversion Systems
Common Questions Concerning CMOS Analog Switches
A Monolithic Subscriber Line Interface Circuit
Additional Information on the HI-300 Series Switch
Design Consideration for a Data Acquisition System (DAS)
Delta Modulation for Voice Transmission

8-2
8-3
8-5
8-12
8-19
8-28
8-35
8-38
8-41
8-45
8-50
8-54
8-59
8-62
8-65
8-69
8-73
8-78
8-83
8-90

II

8-1

A SIMPLE
COMPARATOR USING
THE HA-2620

APPLICA TION NOTE
509
BY G. G. MILER

. The input current and impedance of a
comparator circuit frequently loads the
source and reference signals enough to
cause significant errors. This problem
is frequently eliminated by using a
high impedance operational amplifier
between the signal and the comp,arator.
Figure 1 shows a simple circuit in which
the operational amplifier is used as a
comparator which is capable of driving
approximately ten logic gates. The input impedance of the HA-2620 is typically 500 M.Q. The input current is
typically 1 nA. The minimum output
current of 15 rnA is obtainable with an
output swing of up to ±10 volts.

Figure 2 shows the waveforms for the
comparator. The stray capacitance at
the bandwidth control point can be
reduced considerably below that of the
breadboard circuit; this would improve
the switching time. The SWitching time
begins to increase more rapidly as the
overdrive is reduced below 10 mV and
is approximately 1/ls for an overdrive of
5 mV. Dependable switching can be
obtained with an overdrive as small as
1 mV. However, the switching time
increases to almost 12/ls.

VbUT~ 2~/DI~.

l

...rJl..JO

~

o

>

f-VIN

o
IN916

270Q
t

FIGURE 1 - HIGH IMPEDANG.E COMPARATOR

The bandwidth control point is a very
high impedance point having the same
voltage as the amplifier output. The
output swing can be conveniently limited by clamping the swing of the band- '
width control point. The maximum
current through the clamp diodes is
approximately 300 /lA. The switching
time is, dependent on the output voltage
swing jand the stray capacitance at the
bandwidth control point.

8-2

H

I

1\

\

= 50mV/DIV.·
I

HORIZONTAL SWEEP RATIO

=500ns/DIV.

FIGURE 2 - WAVEFORMS FOR
HA-2620 COMPARATOR (

A common mode range of ±11 volts and
a differential input range of ±12 volts
makes the HA-2620 a very versatile
comparator. The HA-2620 can sink or
supply a minimum of 15 rnA. The ability to externally clamp the output to
any desired range makes the HA-2620 a
very flexible comparator which is capable of driving unusual loads.

IJ~RIS

OPERATIONAL
AMPLIFIER STABILITY:
INPUT CAPACITANCE
CONSIDERATIONS

APPLICATION NOTE
515

BY DON JONES

This is the first in a series of notes dealing
with stabilization and optimization of A.C.
response in operational amplifiers. One of the
more common difficulties in applying operational amplifiers will be discussed.

characteristics of the amplifier between 1 and
10 MHz looks like this:

,

GAIN,dB

PHASE ANGLE

-go,

0

0

Let's consider the unity gain inverting amplifier circuit shown below:
10K

-

--.;;::: ~
G

0

0

-.

I--

r- .............

0

6

1

8

910

-

210 0

MH.

>-......-_---4>--0 0 UT
2K

The characteristics of the feedback network
alone with 5 pF capacitance to ground looks
like this:
PHASE ANGLE

GAIN,dB

o

This appears to be a straightforward application with reasonable component values.

-

0'
G

-10

•

-20

But, with the input grounded, the circuit output shows an oscillation at about 5 MHz.

- --

The culprit here is capacitance at the amplifier
inverting input. The HA-2600 in the TO-99
can has an input capacitance of about 2 or
3 pF. When soldered on a P.C. card, or inserted in a socket, wiring capacitance might
add another 3 to 6 pF. With only 5K effective
resistance at this point, 5 to 10 pF seems
pretty negligible, doesn't it? But let's find out.

-

-40

_1200

go'

7

8

I

910

MH.

Combining these two graphs by algebraically
adding the dB gains together and adding the
phase shifts together gives us the open loop
response at the summing point:
PHASE ANGLE
_900

GAIN. dB
3D

20

10

-

----;::: ~
G

--...... j-.....

~

I""" f::::

_10

The open loop amplitude and phase response

II

,O'

-3D

6

Even more surprising, if the same device is
connected as a voltage follower with the same
load, it is perfectly stable. Since the inverting
amplifier has 6 dB less feedback than the
voltage follower, shouldn't it be more stable?

3D'

-t-

4

5

,

1

::::::Ii:::.
B

910

MH.

8-3

We can see that on the composite response
curves, the phase shift crosses 1800 at 5.5 MHz,
and that there is still about +2 dB of gain at
this frequency. Therefore, closing the loop
automatically creates an oscillator.
How can we overcome this effect? If we add
a capacitor across the feedback resistor, we can
cancel the effects of the input capacitance:
5pF

,

FOLLOWER WITH FEEDBACK RESISTOR

10K
I

I
I

--'-5pF -,-..

2K

I

I

-L..

If the feedback capacitance matches the input
capacitance, the response curves of the feedback network alone will be a flat -6 dB and
0 0 across the frequency band. The composite
curves will then show a bandwidth of 7.5 MHz
and a positive phase margin of 33 0 . So the
circuit will now be quite stable. It's amazing
how much difference that small capacitance
can make.
The general scheme for compensation of various circuit types is shown below:
C2

I

I
I

,

C1::::;::::
I

I

,
I

(Include high frequency
source impedance in R1.)

INVERTING AMPLIFIER

NON-INVERTING AMPLIFIER

8-4

C1 -,-..
-'-

10K

-'-

I
I

I

It's not really necessary to know the exact
value of stray capacitance, C1 - for most layouts, about 5 to 10 pF is a good guess. Unless
you are trying to squeeze out the last Hz of
frequency response, it doesn't hurt to guess on
the high side. At higher gains, where C2
calcu lates out to less than 1 or 2 pF, it isn't
necessary to use C2 - but it won't disturb anything if you do use it.
If you are uncertain about whether compensation is necessary, check the pu Ise response or
frequency response of the closed loop stage.
Hook a pulse generator to the input, and adjust the amplitude for about a 200 millivolt
step at the output - if the output overshoot is
less than 40% of the step, the circuit will be
stable. Alternately, check the small signal
frequency response of the stage - if the high
frequency peaking is less than +6 dB, more
than the low frequency gain, the circuit is
stable. Of course, you can increase the compensation capacitor if you need even smoother
response.
The phenomena we have described are not
peculiar to anyone amplifier type. Wideband
amplifiers require a little more care in the
design of feedback networks; but the same
type oscillations will show up on 741 type
amplifiers with higher feedback resistor values.

m~RIS
APPLICATION NOTE

APPLICATIONS OF A
MONOLITHIC
SAM PLE-ANo-HO Lo/GATEo
OPERATIONAL AMPLIFIER

517
INTRODUCTION
The sample-and-hold or track-and-hold function is very widely used in linear systems_ Until recently, this function was available only
in modular or hybrid circuits; or perhaps most
frequently the circuit was constructed by the
user from an analog switch, a capacitor, and
a very low bias current operational amplifier.

BY DON JONES

must have low offset drift and sufficient slew
rate; a combination satisfied by only a few
available amplifiers.

THE HA-2420/2425
The HA-2420/2425 is the first complete monolithic sample-and-hold integrated circuit. A
functional diagram is shown in Figure 1.

A high quality sample-and-hold circuit must
meet certain requirements:
(1) The holding capacitor must charge up
and settle to its final value as quickly as possible.
(2) When holding, the leakage current at
the capacitor must be as near zero as possible
to minimize voltage drift with time.
(3) Other sources of error must be minimized.
Design of a sample-and-hold, particularly the
user built variety, involves a number of compromises in the above requirements. The amplifier or other device feeding the analog
switch must have high current capability and
be able to drive capacitive loads with stability.
The analog switch must have both low ON
resistance and extremely low OFF leakage currents. But, leakage currents of most analog
switches (except the dielectrically isolated
types) run to several hundred nanoamperes
at elevated temperatures. The analog switch
must have very low coupling between the digital input and analog output, because any
spikes generated at the instant of turn-off will
change the charge on the capacitor. The output amplifier must have extremely low bias
current over the temperature range, and also

IN IN

+

StH CONTROL
GROUND

OFFSET ADJ.

GUARD (N.C.)

OFFSET ADJ.

HOLDING CAP.

v-

GUARD (N.C.)

N.C.

v+

OUT

N.C.

II
I

Figure 1 - HA-2420/2425 Functional Diagram

The input amplifier stage isa high performance
operational amplifier with excellent slew rate,
and the ability to drive high capacitance loads
without instability. The switching element is
a highly efficient bipolar transistor stage with
extremely low leakage in the OFF condition.
The output amplifier is a MOSFET input unity gain follower to achieve extremely low
bias current.
MOSFET inputs are generally not used for
D.C. amplifiers because their offset voltage

8-5

drift is difficult to control. In this configuration, however, negative feedback is generally
applied between the output and inputs of the
ehtire device, and the effect of this Clffset
drift at the inputs is divided by the open loop
gain of the input amplifier stage.

The schematic of the HA-2420 is in Figure 2.
During sampling (S/H control LOW) the signal
path through the input amplifier stage starts
at 031-34, through 045 and 046, and then
to the holding capacitor terminal through
051-54. The output follower amplifier has
its input at MOSFET 060.

HA-2420/2425

Sample-and-Hold

NOTE: 1. Unless otherwise specified resistance values are in OHMS, capacitance values are in picofarads.
Figure 2

10,000

"'

1,000

In the "hold" mode, the S/H control is HIGH,
so 021 conducts, turning on 027 which diverts the signal away from 045 and 046, and
passes the signal to V - through 057. 057 also
forces 051-54 to ride up and down with the
output signal, so there is virtually zero potential between these transistor bases and the voltage on CH; completely eliminating leakage
from CH back into the input amplifier.

/

~ ~RIFT DURING HOLD AT ... 25 0C;

11
lDO

,"

MllLiVOLTS/SECONO

"

"'

\

to--

'.0

DEGREES

'" " "-

~

to

~ O.I:I:~~~:::v~~~Ev~I~:S~~~NGS

r

/

UNITY GAIN PHASE MARGIN;

MICROSECONDS

0.1

/

'/
_UNITY GAIN BANDWIDTH; MHz

'"

"'

""
"

,

SLEW RATE/
CHARGE RATE:
VOLTS}
MICROSECOND

"
f'\.."\.

SAMPLE TO HOLD OFFSET ERROR,
MILLIVOLTS

0.01

..

""\.

''

IDOpF

1.000pF

O.01\JF

01UF

Figure 3 - Holding capacitor, CH
TYPICAL SAMPLE-AND-HOLD PERFORMANCE
AS A FUNCTION OF HOLDING CAPACITANCE

8-6

SAMPLE-AND-HOLD APPLICATIONS

........

A number of basic applications are shown on
the following pages. The device is exceptionally versatile, since it can be wired into any of
the hundreds of feedback configurations possible with any operational amplifier. In many
applications the device will replace both an
operational amplifier and a sample-and-hold
module.

l.D\.JF

The larger the value of the timing capacitor,
the longer time it will hold the signal without
excessive drift; however, it will also reduce the

charging rate/slew rate and the amplifier bandwidth during sampling. So the capacitance
value must be optimized for each particular
application. The graph in Figure 3 shows these
tradeoffs. Drift during holding tends to double for every 10"C rise in ambient temperature.
The holding capacitor should have extremely
high insulation resistance and low dielectric
absorption-polystyrene (below +85°C), Teflon, or mica types are recommended.

Guard Ring Layout
(Bottom View)

w··· .-.--m.",.,

With the switch closed, the circuit behaves as
a conventional op amp with excellent bandwidth, slew rate, high output current capability, and is able to drive capacitive loads
with good stability. With the switch open, the
output node is an almost perfect open circuit.
The output buffer amplifier has extremely
high input impedance and exceptionally low
bias current, but is not particularly well suited
for D.C. applications outside an overall feedback loop, since its offset voltage may be
quite high.
A number of possible gated amplifier applications are suggested in the following section.

CONTROL

APPLICATION NO.1

GNO
• .l!_
HOLDING I
CAPACITOR

i'.

~ IN+

o

o
(.)\~v­

o

v+ }\\\\\'{;)

~

L ________ j

Figure 4

For least drift during holding, leakage paths
on the P.C. board and on the device package
surface must be minimized. Since the output
voltage is nearly equal to the voltage on CH,
the output line may be used as a guard line
surrounding the line to CH. Then, since the
potentials are nearly equal, very low leakage
currents will flow. The two package pins surrounding the CH pin are not internally connected, and may be used as guard pins to reduce leakage on the package surface. A suggested P.C. guard ring layout is shown in
Figure 4.

Feedback is the same as a conventional op
amp voltage follower which yields a unity
gain, non-inverting output. This hookup also
has a very high input impedance.

The only difference between a track-and-hold
and a sample-and-hold is the time period during which the switch is closed. In track-andhold operation, the switch is closed for a
relatively long period during which the output
signal may change appreciably; and the output
will hold the level present at the instant the
switch is opened. In sample-and-hold opera-

Basic Track-and-Hold/Sample-and-Hold

II

CONTROL

IN 0--+--'

GATED OPERA TlONAl
AMPLIFIER APPlICA TlONS
An operational amplifier with a highly efficient
analog switch in series with its output is a
very useful building block for linear systems.
The amplifier can be connected in any of the
conventional op amp feedback configurations.

OUT
CONTROL - ,

r-

L...---l

IN~I
:
I

I

+3V

-ov

I
I

I

OUT---LJ

8-7

tion, the switch is closed only for the period
of time necessary to fully charge the holding
capacitor.

Vin Ro
R1+R2+RO

Inverting Sample-and-Hold
APPlICA TION NO.2

Sample-and-Hold With Gain

OUT

R2
INo--+-....l

OUT

R2
GAIN = ---

Ai

GAIN

=

Rl + R2
Rl

This is the standard non-inverting amplifier
feedback circuit.
It illustrates one of the many ways in which
the HA-2420 may be used to perform both
op amp and sampling functions, eliminating
the need for a separate scaling amplifier and
sample-and-hold module.

In general, it is usually best design practice
to scale the gain such that the largest expected
signal will give an output close to + or - 10
volts. Drift current is essentially independent
of output level, and less percentage drift will
occur in a given time for a larger output signal.

APPLICATION NO.4
It is often required that a signal be filtered
prior to sampling. This can be accomplished
with only one device. Any of the inverting
and non-inverting filters which can be built
with op amps can be implemented. However,
it is necessary that the sampling switch be
closed for sufficient time for the filter to settle when active filter types are connected around the device.

Filtered Sample-and-Hold

APPLICATION NO_ 3

This illustrates another application in which
the hookup versatility of the HA-2400 often
eliminates the need for a separate operational
amplifier and sample-and-hold module. This
hookup will have somewhat higher input to
output feedthrough during "hold," than the
non-inverting connection, since output impedance is the open-loop value during "hold,"
and feedthrough will be:

8-8

IN

APPLICATION NO. 5

APPlICA TION NO. 7

Cascaded Sample-and-Hold

AID Converter
IN/'V

STROB~
OUT

S/HOU~

PARALLEL
OUT

SERIAL
OUT
CONTROL l - - u - - CONTROL2~

Short sample times require a low value holding capacitor; while long, accurate hold times
require a high value holding capacitor. So,
achieving a very long hold with a short sample
appears to be contradictory. However, it can
be accomplished by cascading two S/H circuits, the first with a low value capacitor, the
second with a high value.) Then the second
S/H can sample for as long la time as the first
circuit can accurately hold the signal.

APPLICATION NO.6
Two or more S/H circuits may share a common holding capacitor and output as shown.
The only limit to the number of devices to be

Certain analog to digital converters such as the
successive approximation type require that the
input signal be a steady D.C. level during the
conversion cycle. The HA-2420 is ideal for
holding the signal steady during conversion;
and also functions as a buffer amplifier for
the input signal, adding gain, inversion, etc.,
if required.
The system illustrated is a complete 8 bit successive approximation converter requiring only
four I.C. packages and capable of up to 40,000
conversions per second. Interconnection details are shown on the HI-0l80 data sheet.

APPlICA TION NO. 8

Multiplexed Sample-and-Hold

II

De-Glitcher

I

~CH
O/A
CONTROL
2

---u-

OUT

LEVEL 2

~
LEVEL 1

,

~_-I---41--()

OUT

I
HA-2420

L _________ J

I

Cp~

- 1L

O/A-----\
OUT

multiplexed is that the leakage currents of all
devices add together, which increases drift
during holding.

~H~

OUT

8-9

The word "glitch" has been a universal slang
expression among electronics people for an
unwanted transient condition. In D to A converters, the word has achieved semi-official
status for an output transient which momen·
tarily goes in the wrong direction when the
digital input address is changed.

This basic circuit has widespread applications
in instrumentation, AID conversion, DVM's
and DPM's to eliminate offset drift errors by
periodically rezeroing the system. Basically,
the input is periodically grounded, the output
offset is then sampled and fed back to cancel
the error.

In the illustration, the HA-2420 does double
duty, serving as a buffer amplifier as well as
a glitch remover, delaying the output by Yo
clock cycle.

The system illustrated automatically zeros a
high gain amplifier. Care in the actual design
is necessary to assure that the zeroing loop is
dynamically stable. A second sample-and-hold.
could be added in series with the output to remove the output discontinuity.

The HA·2420 may be used to remove many
other types of "glitches" in a system. If a de·
layed sample pulse is required, this can be
generated using a dual monostable multivibrator I.C.

Many variations of this scheme are possible to
suit the individual system.

APPLICATION NO.11

APPLICATION NO. 9

Integrate-Hold-Reset

This circuit reconstructs and separates analog
signals which have been time division multiplexed.
The conventional method, shown on the left,
has several restrictions, particularly when a
short dwell time and a long, accurate hold
time is required. The capacitors must charge
from a low impedance source through the resistance and current limiting characteristics of
the multiplexer. When holding, the high impedance lines are relatively long and subject

Ha~

OUT

(VIN~

\NITIAL

CONDITION
LEVEL

De -Multiplexer
aUT

~
'±'

ANALDGr

-

MULTIPLEXER.

This circuit accurately computes the functions,

-

-

I

+

Vo

I~

I

~
I:~~I •
I

•

+

CONTROL

CONTROL
OLDWAV

Vin dt

and holds the answer for further processing.

I

Lfr~

f-r~

NEWWAV

to noise pickup and leakage. When FET input
buffer amplifiers are used for low leakage, severe temperature offset errors are often introduced.
Use of the HA-2420 greatly diminishes all of
these problems.

Resetting circuits for integrators have always
been a practical design problem. The reset
circuit must produce an extremely low leakage
current across the integrating capacitor, and
must produce a very low offset voltage when
turned on. The circuit illustrated has excellent
results since the leakage at the switch node is
exceptionally low. Rc and Cc prevent oscillations during reset and their product should be
at least 0.02 times R I XCI'
For the simpler integrate and reset function
without a hold, substitute an ordinary operational amplifier for the upper device.

APPLICATION NO. 10
Automatic Offset Zeroing

APPLICATION NO. 12

.N
OUT

This accurate, low drift peak detector circuit
combines the basic sample-and-hold connection with a comparator, and will detect 20V
p-p signals up to 50kHz.

8-10

When the input signal level exceeds the voltage being stored in the S/H, the comparator
trips, and a new sample of the input is
taken. The S/H offset pot should be adjusted
for a slight positive offset, so that the comparator will trip back when the new peak is
a,cquired; otherwise the comparator would
remain "on" and the S/H would fol·low the
peak back down.
To make a negative peak detector, reverse the
comparator inputs, and adjust the S/H for a
negative offset.

This useful application illustrates how fast repetitive waveforms can be slowed down using
sampling te'1hniques. The input signal is much
too fast to be tracked directly by the X-V recorder; but sampling allows the recorder to be
driven as slow as necessary.
To operate, the waveform is first synched in
on the scope. Then the potentiometer·o.connected to the recorder X input is slowly advanced, and the waveform will be reproduced.
The HA-2420 samples for a very short interval once each horizontal sweep of the scope.
The sampling instant is determined by the potentiometer at the instant when the horizontal
, sweep waveform corresponds to the X position
of the recorder.
'
This principle can be applied to many systems
for waveform analysis, etc.

OUT

APPlICA"rION NO. 14

AOJUST FOR

Vos> +5 mV

'+5V

Gated Operational Amplifier

2K

EQUIVALENT
CIRCUIT
RESET
IL

OPEN COLLECTOR
TTL GATE
FEEDBACK

The reset function,_ which is difficult to
achieve in other peak detector circuits, forces
a new sample at th~ instantaneous input level.

•

APPlICA TION NO. 13
Plot High Speed Waveforms
With Sampling Techniques
The following are a few of the many applications where an operational amplifier followed
by a highly efficient analog switch could be
used:

SCOPE <*,H",O""OIZ",.S",WE",EP,---,

x-v PLOTTER

Analog Multiplexer Element
Gated Oscillator
Precision Timing Circuit
chopper Type Modulator/Demodulator
Crosspoint Switch Element
Reset or Initial Conditions Switch
Gated Comparator
Automatic Calibration Switch
Gated Voltage Regulator

8-11

OPERATIONAL
AMPLIFIER

miHARRIS

NOISE PREDICTION

APPLICATION NOTE
519

BY RICHARD WHITEHEAD

INTRODUCTION
4KTR,

,--)

When working with op amp circuits an engineer is frequently required to predict the
total RMS output noise in a given bandwidth
for a certain feedback configuration. While
op amp noise can be expressed in a number of
ways, "spot noise" (RMS input voltage noise
or current noise which would pass through
1Hz wide bandpass filters centered at various
discrete frequencies), affords a universal
method of predicting output noise in any op
amp configuration.

THE NOISE MODEL

Figure 1

The total RMS output noise (Eno) of an amplifier stage with gain = G in the bandwidth
between f1 and f2 is:
Eno

Figure 1 is a typical noise model depicting
the noise voltage and noise current sources
that are added together in the form of root
mean square to give the total equivalent
input voltage noise (RMS), therefore:
Eni =

Je

ni2 + Ini2Rg2 + 4KTR g

where,

Eni is the total equivalent input voltage noise
of the circuit.
eni is the equivalent input voltage noise of the
amplifier.

(270C) and Rg
8-12

=( R1R1+R3R3!\+ R2

Eni 2dfY:..)

Note that in the amplifier stage shoVlin, G
is

the

non-inverting gain

(G = 1 + ~~)

regardless of which input is normally driven.

PROCEDURE FOR COMPUTING
TOTAL OUTPUT NOISE
1.

Refer to the voltage noise curves for the
amplifier to be used. If the Rg value in
the application is close to the Rg value
in one of the curves, skip directly to step
6, using that curve for values of Eni 2 . If
not, go to step 2.

2.

Enter values of eni 2 in line (a) of the table
below from the curve labeled" Rg = 0 n".

3.

From the current noise curves for the

Ini2Rg2 is the voltage noise generated by the
current noise.
4KTR g expresses the thermal noise generated
by the external resistors in the circuit where
K = 1.23 x 10-23 joules/oK; T = 300 0 K

= G ( f{f2

amplifier, obtain the values of in i2 for
each of the frequencies in the table,
and multiply each by Rg2, entering the
products in line (b) of the table.
4. Obtain the value of 4KTR g from Figure
14, and enter it on line (c) of the table.
This is constant for all frequencies. The
4KTR g value must be adjusted for temperatures other than normal room temperature.
Figure 2

5. Total each column in the table on line
(d). This total is Eni 2 .

10Hz

100Hz

1KHz

10KHz

100KHz

The HA-2600 In a Typical G

Values are selected from Figures 5, 5a and 14
to fill in the table as shown below. An Rg
of 30KU was selected.

(e) 4KTR g

(a! eni2
Ibll n ;2Rg2

6. On linear scale graph paper enter each of
the values for Eni 2 vs .. frequency. In
most cases, sufficient accuracy can be
obtained simply by joining the points
on the graph with straight line segments.
7. For the bandwidth of interest, calculate
the area under the curve by adding the
areas of trapezoidal segments.
This
procedure assumes a perfectly square
bandpass condition; to allow for the
more normal -6db/octave bandpass skirts,
multiply the upper (-3db) frequency by
1.57 to obtain the effective bandwidth
of the circuit, before computing the area.
The total area obtained is equivalent to
the square of the. total input noise over
the given bandwidth.

=1000 Circuit

10Hz

100Hz

1KHz

10KHz

100KHz

3.6)( 10-15

1.156x 10-15

7.84)( 10-16

7.29 x 10-16

7.29 x 10-16

9.9x 10.16

1.B9 x 10-16

3.15)(10-17

7.2)(10-18

7.2 x 10-18

(cJ4KTRg

4.968 x 10. 16 4.968 x 10·16 4.968 x 10.16 4.968 x 10-16 4.968 x 10-16

(dl Eni2

5.09 x 10-15

1.86 x 10-15

1.31 x 10-15

1.23)( 10-15

1.23)( 10-15

The totals of the selected values for each
frequency is in the form of Eni 2 . This
should be plotted on linear graph paper as
shown below:

1.5xlO- 15

r---.,---,..---.------,-----,

II
os.

so,
Frequency,IHz)

8. Take the square root of the area found
above and· multiply by the gain (G) of
the Circuit to find the total Output RMS
noise.
A TYPICAL EXAMPLE
It is necessary to find the output noise of
the circuit shown below between 1 KHz and
24KHz.

HA-2600 Total Equivalent Input Noise Squared

Since a noise figure is needed for the frequency of 1 KHz to 24KHz, it is necessary to
calculate the effective bandwidth of the circuit. With AV = 60db the upper 3db point
is approximately 24KHz. The product of
1.57 (24KHz) is 37.7KHz and is the effective
bandwidth of the circuit.

8-13

The shaded area under the curve is approximately 45 x 10- 1 2 VOlts 2; the total equivalent input noise is
Eni 2 or 6.7 microvolts,
and the total output noise for the selected
bandwidth is fE;1 x (closed loop gain) or
6.7 millivolts RMS.

J

ACTUAL MEASUREMENTS FOR
COMPARISON
The circuit shown below was used to actually
measure the broadband noise of the HA2600 for the selected bandwidth:

~

ISKU

I

i

O.1pF

HA-/~!---.--I

V

i> lOOKU

T{ue

RMS
Meter

1.SKU

ISKU
lOon

Figure 3
A Typical Test Circuit for Broadband
Noise Measurements

The frequencies below the f1 point of the
bandwidth selected are filtered out by the RC
network on, the output of HA-2600. The
measurement of the broadband noise is observed on the true RMS voltmeter. The measured output noise of the circuit is 4.7
microvolts RMS as compared to the calculated
value of 6.7 microvolts RMS.

ACQUIRING THE DATA FOR
CALCUM TIONS
Spot noise values must be generated in order
to make the output noise prediction. The
effects of "Popcorn" noise have been excluded due to the type of measurement
system.
The Quan-Tech Control Unit, model no.
2283 and Filter Unit, model no. 2181 were
used to acquire spot noise voltage values
express~d in (V;-HZ). The test system performs measurements from 10Hz by orders
of magnitude to 100KHz with an effective
bandwidth of 1 Hz at each tested frequency.
Several source resistance (R g) values were
8-14

used in the measuring system to reveal the
effects of Rg on each type of Harris' op'amps
and to obtain proper voltage noise values
essential for current noise calculations.

A DISCUSSION ON "POPCORN" NOISE
"Popcorn" noise was first discovered in
early 709 type op amps. Essentially it is an
abrupt step-like shift 'in offset voltage (or
current) lasting for several milliseconds and
having amplitude from less than one microvolt to several hundred microvolts. Occur-'
ance of the "pops" is quite random - an
amplifier may exhibit several "pops" per
second during one observation period and
then remain "popless" for several minutes.
Worst case conditions are usually at low
temperatures with high values of Rg. Some
amplifier designs and some manufacturer's
products are notoriously bad in this respect.
Although theories of the popcorn mechanism
differ, it is known that devices with surface
contamination of the semiconductor chip
will be particularly bad "poppers". Adver-'
tising claims notwithstanding, the authors
have never seen any manufacturer's op amp
that was completely free of "popcorn".
Some peak detector circuits have been
developed to screen devices for low amplitude
"pops", but 100% assurance is impossible
because an infinite test time would be required. Some studies have shown that spot
noise measurements at 10Hz and 100Hz,
discarding units that are much higher than
typical, is an effective screen for potentially
high "popcorn" units.
The vast majority of Harris op amps will
exhibit less than 3 Jk V peak-to-peak "popcorn". Screening can be performed, but it
should be noted that the confidence level
of the screen could be as low as 60%.

REFERENCES
Fitchen, F.C. and Motchenbacker, C.D. Low Noise Electronic
Design. New York: John Wiley and Sons, 1973.
Instruction Manual, Model 2173C Transistor Noise Analyzer
Quan-Tech, Division of KMS Industries.
Control Unit.
Whippany, New Jersey.

Unless Otherwise Noted:
Vs = ±15V TA = +250 C

TYPICAL SPOT NOISE CURVES
Curve 1

Curve lA

HA-5130/35 INPUT NOISE VOLTAGE

HA-5130/35 INPUT NOISE CURRENT

14

~

1.4

>c 10 "'w

~
g
w
'"(5z

..

....

:::>

~1.2

12

I

NOISE VOLTAGE

"'-

!'"

..-/

1.0

1\

\

~.....7

8

zw

a:

§

6

.6

u

\

5

4

~ .4

!!: . 2

\

/

i~ECURRENT

./

.2

o
10

10K

lK

100

lOOK

o

10

lK

100

lOOK

10K

FREQUENCY - HZ

FREQUENCY - HZ

Curve 2
HA-2400 INPUT NOISE VOLTAGE

Curve 2A
HA-24oo INPUT NOISE CURRENT

~ 10~13
~.

!'IlH4
~

I

"_mm
:: 10-15

Fraquencv.Hz

Curve 3
HA-25oo/251 012520 INPUT NOISE VOLTAGE

•

Curve3A
HA-2500/2510I252o INPUT NOISE CURRENT

I

10-21
10-11

10-22

_ 10-12
~

;:;

f

>
.~

:o~.

10-13

~

ii

IT i7~:.

~

~?;; ~.~

z

~

~

~

'--?.-

~

"

10-23

'-'

.g
z

1

,-;<\

:

10- 14

"-

'0- 24

c

c

~

i

I

10-16

"

10-25

m- 15

10

100

1111
lK
frequency. Hz

10-26
10K

lOOK

10

100

lK
Frequency. Hz

10K

lOOK

8-15

TYPICAL SPOT NOISE CURVES (continued)

Curve 4

Curve 4A
HA-260012620 INPUT NOISE CURRENT

HA-2600/2620 INPUT NOISE VOLTAGE

~

__

Source Resistance = 300Kfl

~ 10-14 ~§'II~~I-III~!III~~;1
"E

>
.~
";

"

~

~

Source Resistance = 30Kn

Source Resistance =
11O-15'1~11!!1
on

10

10-27 10

10-16 '----l-LLLllll'----l-LL.LI..ll.lJ'
----l--LI-LlllllUlll---L-LLLLlilJ
10K
100
lK

100

10K

L'--'-L..LJ.llllL-...L.LJ..illllL_Ll...Ll.llLlL.--L-LJLLLlllJ

lOOK

Frequency, Hz

lK

lOOK

Frequency/Hz

Curve 5
Curve5A
HA-2640/45 INPUT NOISE CURRENT (Vs =:!:30V)

HA-2640/2645 INPUT VOLTAGE NOISE (Vs = ± 30V)

E1O-141"-...IIIIIB~I~11

?!

jg.

N'
:z:

5

7:.

Source Resistance = 100Kf2

"E

110-15 ~mll~ll~so~Jr~}~R~~J,I~t;1~!I~~3J~KJml
. 10-16
~

II

~

10

100

g

~

1lll-111.-L..L-LLLll.lJ

,----,--,-,-...u..wlL-L...LLllU.lL.-..L..LI.Ll..lL

lK
Frequency, Hz

10K

25 ,'11111111.

1~ 10- ~

Source Resistance = on

..........

\

~

>

_~

1O-24~ml~I~II~.

lOOK

26 10

10-

10

L-...LLLLUllL-,-,-.LLWJ.L-...L.Ll-LLJ.liL--lLJ....Ll.LillJ

lK

10K

lOOK

Frequency, Hz

Curve 6A
HA-2700 INPUT NOISE CURRENT

Curve 6
HA-2700 INPUT NOISE VOLTAGE

__10-13'1~llmll;IIIIII!II~II~
~
:Soure.Resistane. =1MU

l'" ~I'--II~II~Io~.I~I,!~L~Il;il;flialnce,!'I~='O~!loJliKI~
i 10-15 ~*IIf-I! !!I~II
10g

~

:E

111111111111

•Resistance,= os

16 10'---L--'--LJ.WJL--'
100 --lI..LlIllillllllL-lII-'.I..uIlll.lJlllll1L-Jlllul-UllW
10K I
lK

Frequency, Hz

8-i6

lOOK

:z:

N'

'"

ilO-25~11'111111
~

<.>

.~

z

.....

,110-26'111111~11
. ~

10-27 10

10

10K

'--L.Ll-LLJ.w.._LJ.~.illlL.-L...LJLLLilll_.LJLUWllJ

lK
Frequency, Hz

lOOK

TYPICAL SPOT NOISE CURVES (continued)

Curve 7

Curve 7A

HA-2720/2730 INPUT NOISE VOLTAGE (lSET = IJ,lA)

HA-2720/2730 INPUT NOISE CURRENT (lSET = lJ,1A)

10- 12

~

Source Resistance-l0Mfl

~

2:

~

10- 13

5

1"-

10-2
6

3

>

10-27

ill

ill
·05

z

j.

10- 14

,..
c

10-

15

==

c

"0

~

Source Resistance - 1Mn

~~

Source Resistance

j

300Kn

,..
c

Source Resistance =0 ~

III

100

10

lK

10K

10-18

lOOK

100

10

Frequency, Hz

iK

Frequency, Hz

10K

lOOK

Curve 8
HA-2720/2730 INPUT NOISE VOLTAGE (JSET = IOJ,lA)
Curve 8A

12

10-

........

X

N"
2:

~

f!
"0

HA-2720/2730 INPUT NOISE CURRENT (lSET = IO/lA)

N"

I
Source Resistance = 3m n

10-13

i5

]

>
.~
z

:;

~r-&
10- 14
c
a

Source Reisstance '"

on

c

10-27 ,LO-U..Ll-L1111,0-0--.l-L.-1..LWJ,LK:--.L.JLLLll~,O::K;--'L.J.-'-'~,OaK

I

10-110

100

5

10K

lK

"-

I,..~ 10-26~1111'1!11
~

Source Resistance = 300K n

~~

,..

10-15~11;lmlfll

c

Frequency, Hz

lOOK

Frequency, Hz

Curve 9
Curve9A

HA-2720/2730 INPUT NOISE VOLTAGE (I SET = 100/lA)
10-13

'">
j 10- 14

~
J".

~

"0

>
.~

HA-2720/2730 INPUT NOISE CURRENT (lSET = 100J,lA)

:

~~

. III

J'..

I

:

10-24'1111~1111
e

~

z

~

c

c..>

Source Resistance:: 100Kfl

-'"

Source Resistance = on

I

~ 10- 15

~;i!

I Source Resislal~~e '" 30OKn.

~j 10-25~11111111

Jl

.,!i

c

10-16

JIlll
10

100

lK

10K

,. 10-26 10L--L...LJ-..llilll_-L-.LL.llJ.ill.._.l......JL.LLl..Lu::-~~-'-'~
100
IK
10K
lOOK
Frequency. Hz

lOOK

Frequency, Hz

8-17

TYPICAL SPOT NOISE CURVES (continued)
Curve 10
HA-4602146051NPUT NOISE VOLTAGE

Curve lOA

10-12

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10-22

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10-24

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10-27

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8-18

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APPLICATION NOTE
520
INTRODUCTION

BY DON JONES

the signal lines. Signal lines can be accidentally shorted to other voltage sources.

This paper is a mixed collection of answers to questions most frequently asked about CMOS analog
multiplexers and switches. It covers selection criteria,
parameter definitions, handling and design precautions, typical applications, and special topics
such as transient considerations and R.F. switching.
Some other devices which perform analog switching
functions in particular applications are also discussed.
As a complement to this paper, the article, "Getting
the Most Out of CMOS Devices for Analog Switching
Jobs" by Ernie Thibodeaux, Electronics, December
25, 1975 is recommended reading for any analog
CMOS user (reprinted in Application Note 521).
Th is discusses the different CMOS processes used
by various manufacturers, showing the performance
trade-offs and particularly the different failure
modes which may be encountered.

CHOOSING THE RIGHT DEVICE
A. MULTIPLEXERS:
TECTED?

CMOS ANALOG
MULTIPLEXERS AND
SWITCHES;
APPLICATIONS
CONSIDERATIONS

PROTECTED OR UNPRO-

Harris overvoltage protected multiplexers, H1-506A/
507A/50BA/509A are designed for failure-proof
operation in a common class of applications: any
system in which the analog input signal lines originate external to the equipment. This includes most
data acquisition, telemetry, and process control
systems. Overvoltage protection is necessary because
the signal lines are commonly subject to a number
of potentially destructive situations.
1. Analog signals may be present while the MUX
power supplies are off.
2. The signal lines may receive induced voltage
spikes from nearby sources.
3. Static electricity may be introduced on the
signal lines by personnel or equipment.
4. Grounding problems are frequent; A.C. power
line voltages at high impedance can appear on

Harris protected type multiplexers will withstand a
continuous voltage on anyone input of i20 Volts
greater than either supply (this limitation is due only
to temperature rise considerations at maximum
ambient) and have withstood simulated static discharge conditions of greater than 1000 Volts.
It should be emphasized that only the HI-506A
through 509A (and exact equivalents from authorized alternate suppliers) will have this kind of protection necessary for inputs from the outside world.
Certain CMOS process improvements, such as
"floating body"'and "buried layer" do help minimize
one failure mode (Iatchup) but will still fail under
excess voltage or current conditions prevalerit In this
type application.
Conventional CMOS multiplexers can be protected
against overvoltage destruction by external resistordiode networks to limit input current to a safe level,
but it is difficult to prevent another phenomenon
with overvoltage; normally-off switching elements
will tend to switch on, due to parasitic bipolar transistors in the CMOS' structure, so the overvoltage
spike will appear at the multiplexer output. The
Harris internal protection circuits eliminate the
problem by automatically shutting off the parasitic
transistor during overvoltage conditions.

II

A simplified equivalent circuit of the Harris internal
protection network is shown in Figure 1.

ANALOG~-,IV~__~~~
IN

'""V'--_,",

ANALOG
OUT

Figure 1

8-19

DATA SHEET DEFINITIONS
This will help answer the question of what happens
when the supplies are turned off, but input signals
are present. If the supplies are shorted to ground,
then the inputs will have about 1 Kn impedance to
ground. If the supplies are open circuit, then the
most positive and most negative inputs will act as
supplies to the multiplexer.
In normal operating parameters, internally protected
multiplexers have one difference from the unprotected versions-ON resistance is' necessarily higher
because of the added series current limiting resistor.
However, to achieve the same degree of protection
with conventional devices, the same resistance must
be added externally, plus external diodes which
would add to the effective leakage currents.
Conventional unprotected multiplexers are suitable
for systems where the MUX inputs come from
sources within the equipment, such as from op amps
powered by the same ±15 Volt supplies. The HI-506/
507/1818A/1828A are intended for this type system.
They are entirely free of any latch-up tendency,
which have plagued some other types, even in these
more benign applications. They are also free of the
performance compromises which have accompanied
some attempts to cure the latch-up problem.
B. WHICH SWITCH TO SWITCH TO?
Harris furnishes a complete line of CMOS analog
switches, including replacements for most of the
available CMOS and JFET switches. All types feature rugged no-latch-up
construction, uniform
characteristics over the analog signal range, and
excellent high frequency characteristics.
The HI-200 and HI-201 replace the popular, low cost
OG200 and OG201 types dual and quad switches.

•

The HI-1800A is a low leakage dual OPST switch
with a versatile addressing scheme, allowing use of
a single type for many different switching functions.
The H1-5040 through H1-5051 are low resistance
types, offering one to four switches in virtually
all combinations. These replace the IH-5040 series
with sign ificantly better performance, and with both
75 ohm and 30 ohm switches available in all configurations. These are also plug-in replacements for
many of the OG180 and OG190 series of FET
hybrid switches, offering the advantage of monolithic construction, but with slightly longer switching
times.
The analog switches do not contain overvoltage
protection on the analog inputs, although they will
withstand inputs 2 or 4 Volts gr~ater than the supplies. External current limiting should be provided
if higher overvoltages are anticipated, such as a resistor in series with the analog input of value: R (ohms)
(VIN -VSUPPL Y) x 50 where VIN is the maximum expected input voltage. All digital inputs do
have overvoltage/static charge protection.

:>

8-20

A. ABSOLUTE MAXIMUM RATINGS
As with all'semiconductors, these are maximum conditions which may be applied to a device (one at a
time) without resulting in permanent damage. The
device may, or may not, operate satisfactorily under
these conditions-conditions listed under "Electrical
Characteristics" are the only ones guaranteed for
satisfactory operation.
B. VS, ANALOG SIGNAL RANGE
The input analog signal range over which reasonable
accurate switching will take place. For supply voltages lower than nominal, Vs will be equal to the
voltage span between the supplies. Note that other
parameters such as RON and leakage currents are
guaranteed over a smaller input range, and would
tend to degrade towards the Vs limits. All Harris
devices can withstand +VS applied at an input while
-VS is applied to the output (or vice-versa) without switch breakdown-this is not true for some other
manufacturers' devices.
C. RON, ON RESISTANCE
The effective series on-switch resistance measured
from input to output under specified conditions.
Note that RON changes with temperature (highest
at high temp.) and to a lesser degree with signal
voltage and current.
O. IS(OFF), IO(OFF), IO(ON): LEAKAGE
CURRENTS
Currents measured under conditions illustrated on
data sheet. Harris prefers to guarantee only worstcase high temperature leakages, because room temperature picoampere levels are virtually impossible
to measure repeatably on available automated test
equipment.
Even under laboratory conditions,
fixture and test equ ipment stray leakages may freq~
uently exceed the device leakage. Leakages tend to
double every 100C temperature rise, so it is reasonable to assume that the +25 0 C figure is about .001
times the +1250 C measurement; however, in some
cases there may be ohmic leakages, such as on the
package surface, which would make the +25 0 C
reading higher than calculated.
Each of these leakage figures is the algebraic sum of
all currents at the point being measured: to each
power supply, to ground, and through the switches;
so the current direction cannot be predicted. In
making an error analysis it should be assumed that
all leakages are in the worst-case direction.
In most systems, IO(ON) has the most effect, creating a voltage offset across the closed switch equal
toIO(ON) x RON.
E. VAL VAH; INPUTTHRESHOLOS

The lower and upper limits for the digital address
input voltage at which the switching action takes
place. All other parameters will be valid if all "0"
address inputs are less than VAL and all "1" inputs
are greater than VAH. Logic compatibility will be
discussed in detail later in this paper.
F. lA, INPUT LEAKAGE CURRENT
Current at a digital input, which may be in either
direction. Oigital inputs 'on Harris devices are similar
to CMOS logic inputs; connection to MOS gates
through resistor-diode protection networks. Unlike
some other devices, there is no OC negative resistance region which could create an oscillating condition.
G. TA, TON, TOFF; ACCESS TIME
The logic delay time plus output rise time to the
90% point of a full scale analog output swing. After
this time the output will continue to rise, approaching the 100% point on an exponential curve determined by RON x CO(OFF).
H. TOPEN,

BREAK-BEFORE-MAKE

OELAY

The time delay between one switch turning OFF
and another switch turning ON;
both switches
being commanded simultaneously.
This prevents
a momentary condition of both switches being
ON, generally a very minor problem.
I. CS(OFFl, CO(OFF, Co (ON) INPUT/OUTPUT
CAPACITANCE
Capacitance with respect to ground measured at the
analog input/output terminals. Co (ON) is generally
the sum of CS(OFF) and CO(OFF).
CO(OFF)
is usually the most important term as rise time/
settling characteristics are determined by RON x
CO(OFF), as well as the high frequency transmission characteristics.

J. COS(OFF), ORAIN TO SOURCE CAPACITANCE
The equivalent capacitance shunting an open switch.

M. PD, POWER DISSIPATION: 1+,1Quiescent power dissipation, PD = (V+ x 1+) +
(V- x 1-). This may be specified both operating
and standby ("Enable" pin ON/OFF). Note that,
as with all CMOS devices, dissipation increases with
switching frequency; but that Harris devices exhibit
much less of this effect.

CARE AIVD FEEDIIVG OF
MULTIPLEXERS AIVD SWITCHES
Dielectrically isolated CMOS I.C.'s require no more
care in handling and use than any other semiconduc tor-bipolar or otherwise. However, they are not
indestructible, and reasonable common sense care
should be taken.
In a laboratory breadboard, power should be shut off
before inserting or removing any I.C.. It is especially important that supply lines have decoupling
capacitors to ground permanently installed at the
I.C. socket pins, as intermittent supply connections
can create high voltage spikes through the inductance of a few feet of wire.
Because each of the major manufacturers of CMOS
multiplexers and switches uses a radically different
process, it is urged that units from all prospective
suppliers be equally tested in breadboards and prototypes. It will be interesting to note which types
survive best the hazards of a few weeks of breadboard testing.
Particular care of semiconductors during incoming
inspection and installation is quite important, because
the cost of reworking finished assemblies with even
a small percentage of preventable failures can seriously erode profits. All equipment should be periodically inspected for proper grounding. With these
devices, it is not usually necessary to shackle personnel to the nearest water pipe, if reasonable attention
is paid to clothing and floor coverings; but be alert
for periods of unusually high static electricity. If
special lines are already set up for handling MOS
devices, it wouldn't hurt to use them.

II

K. OFF ISOLATION
The proportion of a high frequency signal applied to
an open switch input appearing at the output: off
isolation = 20 log VIN. This feedthrough is trans-

VOUT
mitted' through CDS(OFF) to a load composed of
CD(OFF) in parallel with the external load. The
isolation generally decreases by 6dB/octave with
increasing frequency.
L. CA, DIGITAL INPUT CAPACITANCE
Capacitance to ground measured at digital input.
This chiefly affects propagation delays when driven
by CMOS logic.

There are a few good rules for P.C. card layout:
1. Each card or removable subassembly should
contain decoupling capacitors for each supply
line to ground. This not only helps keep
noise away from the analog lines, but gives
good protection from static electricity damage
when loose cards are handled.
2. When digital inputs come through a card
connector, the pull--up resistor should be at
the CMOS input. This forces current through
the connector and prevents possible dry circuit
conditions (see following discussion on digital
interface) .
3. All unused digital inputs must be tied to logic
"0" (ground) or logic "1" (logic supply or

8-21

device + supply) depending on truth table and
action desired. Open inputs tend to oscillate
between "0" and "1". It would also be best
to ground any unused analog inputs/outputs
and any uncommitted device pins.

DIGITAL INTERFACE
A. REFERENCE CONNECTION
HI-5040 through HI-5051 and HI-1800A/1818A/
1828A require a connection to the digital logic
supply (+5V to +15V) ..

'4. Reliability: it shouldn't happen with carefully processed I.C:s; but any possible long
term degradation of CMOS devices usually
involves threshold voltage shifts. The pullup resistor will help maintain operation if
input thresholds drift out of spec. On units'
without adequate input protection, the resistor
will also help protect the device when a loose
P.C. card is handled. Where the interface goes
through a P.C. connector, the resistor will
force current through the connector to break
down any insulating film which otherwise
might build up and cause erratic dry circuit
operation.
A 2K ohm resistor connected from the CMOS
input to the +5 Volt supply is adequate for any
TTL type output. If power consumption is
critical, open collector TTL/DTL should be
used, allowing a higher value resistor-the
voltage drop across the resistor is computed
from the sum of specified "1" level leakage
currents at the TTL output and CMOS input.

The HI-200/201/506A/507A have VREF pins which
are nQrmally left open' when dri'ving from +5 Volt
logic (DTL or TTL), but may be connected to higher
logic supplies (to +15V) to raise the threshold levels
when driving from CMOS or HNIL. The HI-200/201
will have significantly lower power dissipation when
VREF is connected to a high level supply.
The HI-506/507/508A/509A do not have VREF
terminals, but will operate reliably with any logic
supplied from +5 to +15 Volts.
B. DTLiTTL INTERFACE
One major difference found in comparisons of
similar devices from different manufacturers is the
worst-case digital input high threshold (VAH or
VIH). These range anywhere from +2V to +5V;
and anything greater than +2.4V is obviously not
compatible with worst-case TTL output levels.
The fact is that no CMOS input is truly TTL compatible unless an external pull-up resistor is added.'
TTL output stages were not designed, with CMOS
loads in mind.
The experienced designer will always add a pull-up
resistor from the CMOS input to the +5 Volt supply
when driving from TTL/DTL:
1. Interchangeability: allows subsititution of similar devices from several manufacturers.
2. Noise immunity: a TTL output in the "high"
condition can be quite high impedance. Even
when voltage noise immunity seems satisfactory, the line is quite susceptible to induced
noise. The pull-up resistor will reduce the
impedance while increasing voltage noise
immunity.
3. Compatibility: one manufacturer does guarantee +2.0 Volt minimum VAH. However,
this is accomplished with circuitry that is anything but TTL compatible: input current vs.
voltage shows an abrupt positive then negative resistance region which is not the kind
of load recommended for an emitter follower
stage. A pull-up resistor wi II swamp out the
negative resistance. Other CMOS inputs capacitively couple internal switching spikes to the
input which could cause double-triggering
without the pull-up resistor.

8-22

C. CMOS INTERFACE
The digital input circuitry on all Harris devices is
identical to series 4000 and 54C/74C logic inputs,
and is compatible with. CMOS logic with supplies
between +5V and +15V without external pull-up
resistors.
D. ELECTROMECHANICAL INTERFACE
When driving inputs from mechanical switches or
relays, either a pull-up or pull-down resistor must
be connected at the CMOS input to clear the dry
circuit and damp out any spikes, as illustrated in
Figure 2, (b) and (c).

la.Ja~
J
-1~

J

0

la)POOR

1M GOOD

Ie) GOOD

Figure 2

A PRACTICAL MULTIPLEXER
APPlICA TION
Figure 3 illustrates a practical data acquisition system
hookup using an analog multiplexer, a monolithic
sample-and-hold and an A/D converter. The HA2420/2425 sample-and-hold is a particularly good
choice for this type application because it eliminates
the need for a separate high impedance, high slew
rate buffer amplifier. Its acquisition time is consistent with CMOS multiplexer settling times and most
available A/D conversion times. Errors, after initial

adjustment, are consistent with up to 12 bit absolute
accuracy over a wide temperature range.
A. ACCURACY
D.C. error sources include:
1. Multiplexer:
a. input offset = R source x IS(OFF)
b. output offset = R(ON) x (iD(ON) + I bias
(S/H))
2. Sample-and-hold
a. input offset voltage
b. charge injection; sample-to-hold offset
c. gain error during "hold"
d. drift during hold
3. A/D converter:
a. linearity
b. gain drift
c. offset drift

T2 is the short interval required for the sampleto-hold transient to settle.
T3 is the AID conversion time.
The following table indicates minimum recommended
timing for ± 10 Volt input range for acquisition/
settling times to Y, L.S.B. accuracy:
.10 bit:
12 bit:

2.l

T2

6J1S
12f.1S

1f.1S
2f.1S

The multiplexer, by itself, requires about 2 f.1 sand
9 f.1s settling to 10 bit and 12 bit accuracy, respectively; but fortunately this can be concurrent with
S/H acquisition time. This is longer than would be
predicted by the RON CD time constant; probably
because of internal distributed capacitance, a rather
long period is required to traverse the last few millivolts towards the final value.

Item 1 (a) and (b), and 2(d) become significant only
at very high temperatures. 2(a) and (b) are initially
adjusted out with the offset adjustment pot on the
S/H. 2(c) is usually adjusted out by A/D gain adjustment, but could also be removed by a voltage divider
feedback on the S/H to give a slightly greater than
unity gain during "sample". After initial adjustments, typical S/H errors are less than 0.5mV over
0 0 to +75 0 C. Note that after adjustment, there may
be an appreciable offset at the S/H output when
switching from sample to hold. This is not a problem, since accuracy is required only during "hold",
and the system is adjusted for this.

It should be noted that impedance conditions at the
multiplexer inputs can affect the necessary acqUisition time. At the instant the multiplex'~r switches
from one channel to a new one, there is appreciable current pulled through the new channel input
in order to charge CD from its old level to its new
level. This can cause ringing on signal lines, or
glitches at signal conditioning amplifier outputs
which require longer periods to settle. It is best
for signal conditioning amplifiers to be wide band
types, such as HA-2600, so that their high frequency
output impedance is low and recovery from load
transients is fast; even though the signal to be measured is very low bandwidth.

The largest system errors are usually 3(b) and (c),
drifts with temperature and time. If two multiplexer channels can be dedicated for stable (+) and
(-) reference voltage inputs, then the data processor
can continuously calibrate the system, effectively
removing all errors, except 1 (a) and 3(a) which are
usually negligible.

The T1 and T2 times could be eliminated by alternating two S/H circuits, acquiring a new signal on
the second while A/D conversion is taking place.
The two S/H circuits would have inputs connected
together, and outputs alternately connected to the
A/D by an analog switch. Total time, then, would
be T3 plus the analog switch settling time.

II

If the MUX input channels are sequentially switched,
each channel will be sampled at a rate of
ANALOG
IN

FS = N(T1 +1 T2 + T3) samples per second, where N is
the number of channels. The frequency spectra of
the input signals must then be no higher than FS·
SAMPLE/HOLD

MUX ADDRESS

MUXADORESS

START

DATA
REAOY

~

--tl-CONTAOL
LJ :

SAMPLE/HOUl

T2-1 ......

A/DSTART~
AID DATA READY

~-T3~
Figure 3

B. TIMING
The timing diagram in Figure 3 indicates the necessary system delays for each multiplexer address:
T1 is the combined acquisition tim

L

0
SWITCH~~N

0

Y

'>
0

//

V

,/

II

-50

-s0

V
/'"

V

'"
bY

,/"

V

OUTPUT

I
I
I

,
I

I.I
I.1

___ -I

I,

ENABLE
DIGITAL INPUTS

V

/.

I.) FUNCTIONAL DIAGRAM

/

.~,/"

l/V
V
'N

'0-"-t--Il-'l/

'50'
10
FREQUENCY MHI

10'

Figure 10
Ibl ANALOG MULTIPLEXER WITH BUFFERED

.AL TERNATIVES TO CMOS SWITCHES

AND MULTIPLEXERS
CMOS devices are excellent in many applications.
However. there are some other devices which merit
consideration in certain analog switching circuits
where they may improve performance, reduce parts
count, or be more economical.
A.

THE PRAM, PROGRAMMABLE AMPLIFIER

The HA-2400/2405 is a unique monolithic bipolar

8-26

INPUT AND OUTPUT

Figure 11

Advantages over a comparable CMOS multiplexer
circuit are as follows:
1. High input impedance (10 12 ohms), low output
impedance « 0.1 ohm) means that ON resistance and leakage currents are no long9il" of
concern. There is negligible transient loading
of input lines.
2. Gain filtering, etc. can easily be added with
feedback networks.
3. Fast acquisition (1.5IlS).

4. Wide bandwidth (8 MHz).
5. Superior feedthrough characteristics(-110dB at
10kHz, -60dB at lMHz).
Disadvantages include:
1. Le-is accuracy for low level D.C. signals; the
offset voltages of each input stage do not
necessarily match or track each other.
2. Cannot be used in reverse as a demultiplexer.
3. Disabling the device (enable pin low) does not
open the output line, or drive the output to
zero. Adding channels may be accomplished
by tieing compensation pins together.
Figure 12 illustrates the PRAM used as a programmable gain amplifier. Any connection possible with
op amps can be wired 4 ways to make programmable
active filters, oscillators, etc., etc. Harris Application.
Note 514 shows many possibilities.

OUT

ADJUST FOR
VOS>+5mV

+5V
2K

RESET
..JL

OPEN COLLECTOR
TTL GATE

Figure 13

C. PROGRAMMABLE SUPPLY CURRENT
OPAMPS

} 0'.""

CONTROL

".'

The HA-2720/2725 and HA-2730/2735 (dual amp)
are op amps with an extra terminal which is used
to control quiescent supply current. These are most
generally used in low power systems to optimize
the power dissipation vs. bandwidth and slew rate
tradeoffs. They can also be used with variable set
currents to make linearly variable oscillators, filters,
etc. Another application is a switchable op amp as
shown in Figure 14.

AMPLIFIER. NON-INVERTING PROGRAMMABLE GAIN

Figure 14
Figure 12

B. SAMPLE-AND-HOLD
The sample-and-hold function has often been
accomplished with separate analog switches and op
amps. These designs always involve performance
tradeoffs between acquisition time, charge injection,
and droop rate.
The HA-2420/2425 monolithic sample-and-hold,
illustrated previously in Figure 3 has many times
better tradeoffs, usually at a lower total cost than
the other approaches. The switching element is a
complementary bipolar circuit with feedback which
allows high charging currents (30mAl. low charge
injection (1 OpC), and ultra low OF F leakage current
(5pA); a combination not approached in any other
electronic switch. These factors make it also superior
as an integrator reset switch, or as a precision peak
detector as shown in Figure 13. Harris Application
Note 517 illustrates many other applications.

II

The illustrated transistor could be the output of high
voltage open collector gate. The set resistor R is
chosen so that the set current is the desired value
when the transistor is ON, considering that the
voltage at ISET terminal when ON is about 2 forward
junction drops (rv 1.5V) below V+. When the transistor is turned OFF, amplifier input, output, and
supply terminals become very high impedance, so
that two or more amplifier outputs could alternately
be switched to the same point.

I

Off isolation with a 2,000 ohm load is about -80dB
at 10kHz.
D. CHOPPER STABILIZED AMPLIFIER
Analog switches are sometimes used as choppers for
amplifying low level D.C. signals with low offset
errors. The HA-2900/2905 is a monolithic chopper
stabilized amplifier in a TO-99 can. Typical offset
drifts are 0.2 MV /oC and 1pA/OC with 5 x 108
open loop gain. Harris Application Note 518 describes this device.

8-27

m~RIS

GETTING THE MOST
OUT OF C-MOS DEVICES
FOR ANALOG
SWITCHING JOBS

APPLICATION NOTE
521\

BY ERNIE THIBODEAUX

INTRODUCTION
Although most designers appreciate the benefits of
the complementary-MOS process for digital design,
few realize hqw effective the technology can be for
analog switching. C-MOS analog switches, which
consume less power than bipolar devices, exhibit no
dc offset voltage and can handle signals up to the
supply rails. The C-MOS bilateral property furnishes
input and output functions, making multiplexing and
demultiplexing possible. In addition, the on-resistance of an MOS switch is as low as 30 ohms-a third
as much as a bipolar device.
Unfortunately, C-MOS analog switches, which until
recently were built with junction isolation, have been
difficult to design into analog multiplexers and
switches. The devices latched up easily, their C-MOS
inputs were destroyed by electrostatic charges, and
they literally went up in smoke when confronted
with input overvoltage spikes and power-supply
transients. To prevent destruction, costly external
protective circuits were needed, and, even then, the
devices latched up unless the power was turned on
and off in a set sequence.
Because latch-up problems limited the use of analog
switches so severely, device designers focused a great
deal of attention on eliminating the condition.
Recently, the success has been noteworthy. Indeed,
three new technologies now offer latch-free analog
switch operation: latch-proof junction isolation (JI),
floating-body junction isolation, and dielectric
isolation (01).
Both JI techniques are conventional processes that
have been slightly modified to alleviate the old
problem of latch-up. However, both of these JI
technologies still require costly external protection
circuits to guard against burn-out in such applications
as analog-signal multiplexing that interface them with
the outside world. That is why JI devices are best
suited for internal-switching applications where the
electrical environment can be controlled. In contrast,
the improved 01 technology, by virtue of its construction, offers analog-switching devices suitable for

8-28

Reprinted from Electronics, December 25,1975.

many inside applications, as well as providing inboard analog protection for devices that interface
with the other circuits. Happily, the smaller substrate
area of the 01 device delivers a better speed-power
product than the JI technology.

THE BASIC C-MOS SWITCH
The basic C-MOS transistor (Fig. 1) has parasitic
junctions that are reverse-biased during normal
operation. However, certain overvoltage conditions
can forward-bias these junctions to cause high currents that could possibly destroy the devices.
GATE

.l

n-CHANNEL

I~"'---'l

Vs

DRAIN ~
----rOUT

SOURCE

IV+;;'VS;;'V-)

T

p-CHANNEL

GATE

Figure 1. Bad
In the basic C-MOS analog swItch, the parasitic junctions
are reversed-biased during normal operation. Large overvoltages, however,
large currents.

make them

forward-bIased and draw

The parasitic junctions are actually npn and pnp
transistors that are normally reverse-biased by the
applied body potentials. However, because many
analog switches, and especially multiplexers, are connected to their analog sources through long lines,
they are highly susceptible to externally induced
voltage spikes. For example, these spikes, which
can often exceed the p-channel body potential, V+,
can inadvertently turn on a normally off switch

Copyright 1975 by IVJcGraw-Hilllnc. 1221 Avenue of the Americas, New York, N.Y. 10020

through the parasitic pnp transistor (Fig. 1).
The n-channel device is similarly affected when the
parasitic npn transistor is turned on by a negative
overvoltage.
This action, commonly known as
channel interaction, causes momentary channel-tochannel shorting, which introduces significant errors
in the system. This intermittent condition, which
is seldom destructive, is rarely isolated because it
occurs only randomly.
One of the adverse effects of channel interaction is
illustrated in Fig. 2. Channel 1 of an analog multiplexer is selected when all other channels are off.
Channel 16 receives an input-noise spike that momentarily exceeds the positive supply. The sequence
causes channel 1 read-out to be +16V because of
interaction with channel 16 just before initiating the
hold command to the sample-and-hold device. To
prevent this annoyance requires additional protective
circuits that clamp each channel input to a voltage
below the threshold of the parasitics to ensure that
the channels remain inactive under any conditions.

and the multiplexer switch. An error during troubleshooting or an inadvertent supply glitch can trigger
this fault mode and destroy the whole system.
Therefore, there is obviously much more to system
reliability than having latch-proof C-MOS devices.
ISHORT

~-------t~--~MUXOUT

IN

ISHORT

MULTIPLEXER
CH 1 (ONI

RON

",---"TO,----"'IF~

CH 1SICFF)

t+~
16V

v+· +15V

+fOV

Figure 3. Still Worse

CH1(ON)

MUX
ADDRESS

Most serious in CMOS switches is losing substrate potential to
ground. This condition. which happens when power Is lost
and the analog signal Is present, causes very high currents.

o

SAMPLE/HOLD
CONTROL

HOLD

n. ._____
+16V

CH 16

+IOV

(NOISE SPIKE)

CONSIDERING LATCH-PROOF JI
TECHNOLOGY

PARASITIC TURNS ON _ _ _ _ _ +16V

MUX
OUTPUT

-------~~-----+16V

SAMPLE/HOLD

OUTPUT

____________

-J~

Figure 2. Worse

The standard JI process has been modified by what is
claimed to be latch-proof construction through
control of the effective betas of the parasitic transistors. A cross section in Fig. 4(a) shows the C-MOS
structure along with its parasitic transistors and the
equivalent circuit in Fig. 4(b) that gives rise to the
sil icon-controlle~-rectifier latch-up problem.

11

With CMOS devices f noise spikes can cause channel interaction.

In this multiplexer, although channel 1 is only one

selected, noise spikes cause cross talk in channel 16, which
affects reading.

A more serious condition exists when the substrates
(p- or n-) lose their respective potentials to ground
(Fig. 3) -a condition that occurs when power to the
device is turned off while the analog signals are still
present. In this situation, the analog switch, which
at that point represents a diode connected through
the low impedance of the supply, draws high current
from the analog source.
This current turns on the switch through its parasitics
and shorts all channels to the output. These shorts
can easily be catastrophic in multiplexer systems that
have different power supplies for the analog source
Reprinted from Electronics, December 25, 1975.

Under any of the fault conditions previously mentioned, the npn and/or pnp can trigger this quasidual-gate SCR into a state of high conduction. If
the transistor /3 product is 1 or greater, this configuration is sustained until either the device burns up
or all sources of power are removed. By using a
buried-layer configuration, as shown in the cross
section, the fJ product is reduced to less than 1,
eliminating the latch-up conditions.
Again, especially in multiplexer applications, the
latch-free devices do not guarantee against destruction, and the JI multiplexer still requires costly
discrete circuits around the device, as shown in Fig 5.
If an overvoltage exists, the resistor/diode circuit
at each analog input limits the input voltage to the

8-29

v-

v+

,---< INPUT A

n+

INPUT B

>----'

(e)

(b)

Figure 4. Latch-Proof.
Junction-Isolated devices are now made latch-proof with a buried-layer configuration (a), which keeps beta of
parasItic transistor under unity. That kills chanca for latch-up (b), which plagues devices built with older junction-Isolation technology.

-15

+15
+15
+15
V1
+15
+15
+15
+15
~

'"
.:

0

+15

z
.:

+15

..J

S1
S2

~

*

V2

AO

+5

S3
S4
S5
S6

A1
~

+5
A2

S7
Sa
S9

..J

;'!
Ci
15

+5
A3

S10
S"
S12

+5

+15
S13

S14

EN

S15

S16

+15
+5
+15

ANALOG IN

II

Figure 5. Protection still needed. Although new JI devices wonlt latch up, they still can be destroyed by large currents. That's why typical
JI multiplexers, like the one shown here. still need to be surrounded by external protective components, which drive up system costs.

supply-voltage range to prevent the parasitic transistor action.
The resistors limit the overvoltage currents through
the diodes. The diodes must have a low threshold
voltage-much lower than the 0.6V silicon-junction
threshold of the internal parasitic diodes-to ensure
that the parasitics do not turn on.
A germanium diode offers a low threshold voltage,
but its high leakage current makes it impractical,
Therefore, in most
especially in 0.1 % systems.
applications, more expensive low-leakage diodes
are used.
For example, Schottky diodes meet the requirements,
but they cost about 50 cents each in volume, and the
total cost per multiplexer, including parts and labor,

8-30

Reprinted from Electronics, December 25, 1975.

for the discrete protection circuit may well be double
the initial purchase price of the device. Even then,
its reliability will never approach that of an IC that
has this protection alreadY built in.

THE FLOATING-BODY JI TECHNOLOGY
Standard J I technology allows another approach to
latch-proof device construction: a portion of the
SCR continuity is broken by floating the "body" or
substrate of the n-channel switching device. A cross
section of this process is similar to that in Fig. 4(al.
excluding the buried layer and the negative supply
connection to the p- substrate, so that the dual-gate
SCR is changed to a single -gate device that can only
be triggered by the pnp parasitic. This, of course,
reduces the latch-up probability by 50%.

To completely eliminate latch-up, as before, the fJ
product of the transistors is reduced to less than 1.
This accomplishment, certainly a significant improvement over the conventional process, offers
greater reliability, but certain trade-offs must be
made when the body of a MOSFET is floated.

""-

IN ,

(a)
OFF ISOLATION' 20 LOG (OUTIIN)

Nominal source-to-drain breakdown voltages are
reduced which limit the peak-to-peak signal range.
Over-all breakdown is limited by the collectoremitter breakdown voltage, BVCEO, of the npn
parasitic transistor of the floating n-channel
MOSFET. The breakdown voltage increases with the
degree of reverse-bias potential applied to the
substrate. With a floating body, BVCEO is minimum,
so particular care is necessary when using' these
devices in configurations such as single-pole singlethrow, single-pole double-throw, dpst, and dpdt,
where each side of the switch connects to opposite
polarities. The peak-to-peak handling capability is
specified at a minimum of 22V; therefore, 30V pk-pk
cannot be switched with ± 15V supplies, as it can
with other C-MOS devices.
What's more, the leakage currents of floating-body
JI devices are higher than other types, simply because the ICEO of the floating base for the npn is
much greater than the ICBO of other devices having
fixed reversed-biased body potentials. The increased
leakage currents in spst switches may not be too
significant.
However, in multiplexers that have the outputs of as
many as 16 switches tied together in one IC, the total
summation of currents can significantly affect system
accuracy. For example, the specification for a worstcase 16-channel floating-body multiplexer is 10
microamperes, and the channel on resistance is 550
ohms. The dc-offset error would be 5.5 millivolts,
representing an accuracy to 0.055%.
Other 16-channel types specify worst-case parameters of 500 nanoamperes and channel resistance
between 550 ohms and 2 kilohms. Their dc-offset
error is between 0.28 mV and 1 mV, respectively,
allowing accuracy to 0.01% or better.
Finally, the effective off impedance of the floatingbody switch is degraded by the floating-body technique. Off-isolation characteristics of a MOSF ET are
primarily determined by its source-to-drain capacitance. But with the base floating, the effective capacitance from emitter to collector is increased by the
series combination of emitter-base and base-collector-junction capacitances (Fig. 6al. This increase
degrades the over-all off-isolation characteristics.
For example, the off isolation for a typical floatingbody channel at 1 megahertz that has R L = 100 ohms
is specified to be -54 decibels, which compares
favorable with other types.
However, at lower
frequencies such as 1 kHz, the isolation is only
-62dB, compared to more than -110dB for improved
devices. Capacitances Cl and C2 for them are shunted by the low ac impedance' of the supply voltage
(Fig.6bl.
Reprinted from Electronics. December 25, 1975.

""-

IN >---."..---~

~--~~--'---'OUT

(b)

Figure 6. Floating Bodies
Floating-body switches have degraded "off" impedance
because total capacitance (a) combines two junction capacitances.
In 01 circuit (b), capacitances are shunted out.

THE LINEAR DIELECTRIC-ISOLATION
TECHNOLOGY
The linear dielectric-isolation process requires no
modifications to guard against latch-up. Its basic
construction ensures that the SCR configuration
that causes latch-up can not exist. The functional
cross section in Fig. 7 reveals the silicon-dioxide
isolation barrier fabricated between all parasitic
transistors. This isolation allows each active element
to be self-contained and independent with no interface junctions. At most, only three-layer structures
are permitted for each tub, so that four-layer strucures, or SCRs, are impossible. Also, since the 01
technology requires no guard bands, junction capacitances, leakage currents, and size are minimized.
The resulting increase in packing density per wafer,
together with increased yields, enables these devices
to be cost-competitive with other types.
GATE

ISOLATION

GATE

Figure 7. How 01 Does It
Dielectric isolation eliminates latch-up bV a silicon-dioxide
isolation barrier between devices. This. separates all active
elements, elimin'atlng interface junctions that cause parasitic SeR's.

In working with DI devices, the IC designer is not
burdened with the fixed substrate potentials found in
JI devices. He may let the substrate float, fix it to
some potential, or jlven modulate it. Fig. 8 depicts
a typical DI analog switch circuit that minimizes the
variation of on resistance with the analog signal.
Ordinarily, in conventional circuits, the body or

8-31

substrate potentials of the nand p-channel devices
are fixed and the source-to-body bias potentials
vary with the analog input voltage. This change in
body bias causes a wide variation of on resistance
within the analog signal range. However, in the DI
circuit, the bodies of P1 and N1 are connected together through N3 during the on state. This allows
the body to follow the input voltage providing a
constant source-body bias and therefore a constant
on resistance. During the off state, the bodies of
Nl and P1 are at their respective supply potentials
through P2 and N2, thereby preserving high off
isolation and low leakage currents.

connected to V+ through P3 and diode D7 for
maximum isolation and low leakage currents in the
off state. If the input voltage suddenly exceeds
V+, the source-body junction, which would normally
conduct, is instead clamped by transistor as.
>:

FROM DECODE

OVERVOlTAGE

>i

FROM DeCODe

Figure 9. Winning Combination
Combining bipolar and MOS technologies In the same mUltiplexer gives built-in protection. This cirCUit is typical for
each channel In multiplexers HI-50BA, HI-507A, HI-SOBA,
and HI-509A.

Figure 8. 01 Does It

on

In dielectricallv isolated switches,
resistance modulation
by the analog Input Is minimized by connecting N1 and P1
bodies together through N3.

DESIGNING A FOOLPROOF C-MOS
ANALOG MULTIPLEXER
In dielectrically isolated multiplexer circuits, protection can be provided on the chip primarily to eliminate channel interaction. This protection prevents
normally off channels from being turned on by
parasitics from other channels. And because this
interaction is prevented, even worst-case powersupply faults cannot destroy the device. Moreover,
since DI structures have no SCR effect, protection
against latch:-up and power-sequencing are not
necessary. In short, DI multiplexers with built-in
protection can withstand virtually any conceivable
fault from the outside world.
The typical protected DI multiplexer (Fig. 9) benefits
from a combined bipolar/C-MOS technology. The
illustrated bipolar section is used to sense an analog
overvoltage condition and steer current away from
the parasitic MOSFET junctions. Each of the switching devices, N1 and P1, has its own protection circuits, Devices P3, OS, D7 and as protect P1 while
N3, D4, D5', and a5 protect N1. When the switch is
off, the substrate of the p-channel FET, P1, is

6-32

Reprinted from Electronics, December 26. 1975.

The base-emitter junction conducts to hold the
source-body diode off with a saturation voltage
VCE(SAT) of about 0.2V. Thus clamped, the switch
is protected from the effects of overvoltage.
Clamp as always turns on before the forwardvoltage drop of the source-body diode is exceeded
because diode DS requires an additional forwardvoltage drop for conduction through the parasitic
junction. Moreover, resistor R1 limits the current
flowing through as when high overvoltages exist.
Although R 1 adds to the total on-resistance of the
channel, its associated error is insignificant, since
most systems provide high-impedance buffering
anyway. For negative overvoltages, N1 is similarly
protected.
What's more, the protection circuit,
rated at a nominal overvoltage of ±33V, reveals
a cross-talk current of only about 5na (Fig. 10).
When the switch is normally turned on, the substrates of N1 and Pl are connected together through
N2, which, as described before, results in a constant
on resistance.
This condition represents an absolute error from
channel interaction of only S microvolts (RON x
5NA)-certainly negligible in most systems.
In
contrast, floating-body types have guarantees only
that they won't be burned up by ±25V overvoltage.
Their manufacturers do not make any claim against
channel .interaction.
In fact, channel interaction
occurs readily in these devices when the n- and
p-channel thresholds are exceeded by an overvolt-

age. For example, the n-channel device, although
floating, would be inadvertently turned on if the
analog input exceeded the negative supply by its
gate-to-source threshold, which is typically 1.5V.
21
18

<
..s
I-

r---------------------------------,
6 ~

a:
a:
=>

tJ 12
I-

w
4 C!)

::J

a.

!: 9
Cl

~

Figure 11. Digital Protection

«
«
'"
w

01 devices also protect digital Inputs. For example, the
diodes in this circuit quickly discharge any static charge
that may appear on an MeS input gate.

3 -'

g
<{

v-

'-'

::J

«
z

BUFFER

DIGITAL IN

ANALOG INPUT
CURRENT (lIN) - - . . .

tz
w

15

z

w

o-_......"'200!11V'_. . ._ _ _ _.~~DRESS
v,"'O.6V

.:;

a:
a:

Vf"O.sV

u.
u.
0

t=>
"t-

6

=>
0

OUTPUT OF F LEAKAGE
CURRENT 10 (OFF)

3

0
:1"15

:1"18

:1"21

:1"24

1:27

t30

:1"33

t36

VIN -ANALOG INPUT OVERVOLTAGE (VOLTS)

Figure 10. Blocking Cross Talk
DI switches have minimal cross-talk problems.

An over-

voltage of 33V produces a cross-talk current of only 5nA-

an absolute error from channel interaction of only 6 p. V.

ADDING BENEFITS
TOP3

RESULTS OF DIGITAL-INPUT PROTECTION TESTS
(20 DIELECTRICALLV ISOLATED UNITS)
STRESS STEPIVOLTS

FAILURES

500

0

1,000
1,500

0
0

2,000

1

2,500
3,000
3,500

0
3
0

4,000

3

Additional D) benefits are passed on to the user in
the design of the digital input-protection circuit
shown in Fig. 11. The fabrication of all components
as isolated silicon islands eliminates any possibility
of latch-up. The diodes switch fast and quickly
discharge any static charge that may appear at the
digital MOS input gates. The table gives the results
of a step-stress analysis performed on 20 units. A
total of 80% survived the 3.5 kilovolt level, and
only one failed below 2kV.
The DI technology enables a wide variety of active
elements to be integrated on the same chip to provide
maximum versatility. For example, in the transistortransistor-logic/C-MOS reference circuit shown in
Reprinted from Electronics, December 25, 1975.

Figure 12. Packing It In
01 technology increases chip density of analog switch,
allowing more circuit capability per package. For example,
01 designs make possible this Internal logic reference circuit
in HI-200 and HI-201 switches.

Fig. 12, the bipolar technology enables realization of
a simple zener reference circuit, consisting of resistor
R2 and transistors 01, 02, and 03.

8-33

The circuit develops a stable 5V reference for interfacing with TTL and eliminates the need for an additional 5V logic supply. Current for the zener (Q3) is
supplied through the normally on MOSFET, Pl,
which can be easily turned off if not needed to
minimize power consumption when interfacing
with C-MOS-Iogic circuits. Pl turns off when V+
or supply voltage VOO is applied to the reference
terminal VREF to convert the IC's power-consumption from bipolar to C-MOS level. If power is not
critical, VR EF can be left open to speed switching.
In high-speed data-acquisition systems, the designer
is concerned with both quiescent power and dynamic
power consumption. If JI devices are used, the
capacitance or leakage currents are so high they contribute a major portion of total power consumption.
That situation is caused by the large-geometry
parasitic junctions formed by the n- junction.
In contrast, the smaller substrate area of the 01
device provides much less power drain. Oynamicpower consumption as a function of frequency for
several 16-channel analog multiplexers with ±15V
supplies is shown in Fig. 13. The 01 device consumes
only 100mW at 1 MHz to yield the best speed-power
product.

400

§
.§ 320

z

0

t::0

240

::>

en

z

0

tJ

160

a:
w

;:

0

0.

JI

80
0
lk

10k

lOOk

1M

TOGGLE FREOUENCY (IN Hz) (60% DUTY)

II

Figure 13. 01 Performs
01 devices not only perform well, but do it with less power.
Dynamic-power-consumption data for commercial multiplexers shows 01 device consuming only 100mW at 1 MHz.

8'-34

DIGITAL TO ANALOG
CONVERTER
TERMINOLOGY

HARRIS
SEMICONDUCTOR
PRODUCTS DIVISION
A DIVISION OF HARRIS CORPORATION

APPllCA TION NOTE
522
INTRODUCTION
In recent years the development and rapid reduction
in cost of digital integrated circuits have resulted in
an explosion in the applications of digital processing
systems in the area of data acquisition and automatic
process control. The need for a building block,
such as the digital-to-analog converter (DACl. which
interfaces the digital system with the analog world,
is evident.
The purpose of digital-to-analog conversion is to
produce a unique but consistent analog quantity,
voltage or current, for a given digital input code.
The most commonly used input digital code to a
DAC is the natural binary number. A natural binary
number is represented as
N = An2n + An_12n-1 + . . . + A121 + A020 +
A_12-1 + ... + A_n 2\;"n
where the coefficients Ai lfor n)i )-n) assume the
values of "a" or "1" and.,bls called a "bit". The left
half portion of the binary number N
/

An2n+An_12n-1 + ... +A121 + A020
constitutes the integer part of the number N, whereas
the right portion
A_12-1 + A_22-2 + ... + A_n2-n
constitutes the fractional part of the number N. The
bit that carries the greatest weight (left most bit) is
called the most significant bit, or MSB. Similarly,
the bit with the smallest weight (right most bit) is
ealled the least significant bit, or LSB.
The analog output of a n-bit binary DAC is related
to its binary number in the following manner:

BY DICK TI TUNG

The term FS(1/2 n ) is the smallest output level that
the DAC can resolve and it is known as the 1 LSB
output level change. It is universal practice that the
input code of a DAC is written in the form of binary
integer with the fractional nature of the corresponding number understood.
As an example, the transfer function of an ideal
3-bit binary DAC is plotted as shown in Figure 1.
Since a 3-bit DAC has only 8 discrete input codes
which correspond to 8 different output levels (ranging from zero to 718 FSl. no other output levels can
exist and it is plotted as a bar graph. The line that
connects the Zero and FS is called the Ga-in Curve.

OUTPUT
, FS
(.-1

1----------------

!
7

GAIN CURVE

:

Y

/

jj

II

/

~

.,---;

3

1 L1SB/

!

~j(

I

7

ii

o
000

001

010

011

100

101

110

111

INPUT

Figure 1 - Ideal Transfer Function
Straight Binary (UnipolarJ

Eo = FS(A_12-1 + A_22-2 + ... + A_ n 2- n )
where the term FS is defined as the nominal FullScale output of the DAC and it is knowrf as the unreachable Full-Scale. It is easy to see that the actual
Full-Scale output of the DAC, EFS, with all the
input bits "1" is
EFS

= FS(2- 1

+ 2-2 + . . . + 2- n )

= FS(1-2-n).

There are two other input codings associated with
binary DACs known as Bipolar codes, which are
offset binary and two's complement binary codes.
The offset binary code is obtained by offsetting the
binary code such that the half-scale code, 10 ... 0,
becomes zero. And the two's complement code is
achieved by inverting the MSB of the offset binary

8-35

code such that it is mathematically consistent with
computer arithmetic. The transfer functions for the
3-bit DAC with offset binary input code and two's
complement input code are plotted as shown in
Figure 2 and Figure 3, respectively. (The +FS and
-FS limits are used for easy interpretation of Bipolar
operations. They are not confined by the previous
definition of FS.)
In practical DACs, the zero output level may not be
exactly zero (offset error), the range from zero to
FS may not be exactly as specified (gain error), the
differences in output levels may not be changing
uniformly (nonlinearity), and so on. In selecting a
DAC for a given application, some characteristics
may have to be weighted more than the others.
An understanding of some of the terms and characteristics involved in D/A conversion is helpful in
choosing the correct part.

TERMINOLOGY
Least Significant Bit (LSB) - The digital input bit
carrying the lowest numerical weight (1 /2n); or the
analog output level shift associated with this bit
(FSR/2 n ) which is.the smallest possible analog output
step.
Most Significant Bit (MSB) - The digital input bit
carrying the highest numerical weight (1/2); or the
analog output level shift associated with this bit. In a
binary DAC the MSB creates a 1/2 FSR output
level shift.
Resolution - An indication of the number of possible
analog output levels a DAC will produce. Usually,
it is expressed as the number of input bits. For
example, a 12-bit binary DAC will have 212 = 4096
possible output levels (including zero) and it has
a resolution of 12 bits.

OUTPUT

+FS

000

001

010

011

j-:

'---'---r--,-O~--L-~~-L--~

100

-4

-~

_______ -F:
Figura 2 - Ideal Transfer Function
Offset Binary (Bipolarl

II

OUTPUT

+FS

Absolute Accuracy - A measure of the deviation of
the analog output level from the ideal value under
any input combination. .Accuracy can be expressed
as a percentage of full scale range, a number of bits
(n bits accuracy means a magnitude of 1/2 n FSR
possible error may exist), or a fraction of the LSB
(if a DAC with n-bit resolution has 1/2 LSB accuracy
the magnitude of the possible error is 1/2(1/2 n FSR)).
Accuracy may be of the same, higher, or lower order
of magnitude as the resolution. Possible error in
individual bit weight may be cumulative with combination of bits and may change due to temperature
variations. Usually, the accuracy of a DAC is expressed in terms of nonlinearity, differential nonlinearity, and zero and gain drift due to temperature
variations.
Nonlinearity (linearity error) - A measure of the
deviation of the analog output level from an ideal
straight line transfer curve drawn between zero and
full scale (commonly referred as endpoint linearity).
Differential Nonlinearity - A measure of the deviation between the actual output level change from the
ideal (1 LSB) output level change for a one bit
change in input code. A differential nonlinearity
of ±1 LSB or less guarantees monotonicity; that is
the output always increases for an increasing input.
Gain Drift - A measure of the change in full scale
analog output, with all bits 1's, over the specified
temperature range expressed in parts per million
of full scale range per oC (PPM of FSR/oC). It is
measured with respect to +250 C at high (TH) and
low (TLl temperature, and it is specified the larger
of the two representing worst case drift.

Figura 3 - Ideal Transfer Function
Two's Complement (Bipolarl

8-36

Offset Drift (Unipolar or Bipolar) - A measure of
the change in analog output, with all bits D's, over the
specified temperature range expressed in parts per
million of full scale range per oC (PPM of FSR/OC).
It is measured with respect to +25 0 C at high (THI
and low (TLI temperature, and it is specified the
larger of the two representing worst case drift.

Settling Time - The total time measured from a
digital input change to the time the analog output
reaches its new value within a specified error band.
Usually, the settling time is specified for a DAC to
settle for a Full-Scale code change (00 . . . 0 to
11 . . . 1 or 11 . . . 1 to 00 ... 0) to within +1/2
LSB of its final value.

OUTPUT

FS

Compliance - Compliance voltage is the maximum
output voltage range that can be tolerated and still
maintain the specified accuracy.
The effects of gain error, offset error, nonlinearity,
and differential nonlinearity on the transfer functions
are plotted, respectively, as shown in Figure 4, 5,
6, & 7. A conversion chart which shows the number
of bits and its resolution is given in Table 1.

000 001

010

011

100

101

110

111

Figure 6 - linearity Error

OUTPUT

FS
7

'8

OUTPUT

6

FS

8

---------------

7

5

ii

4

8'

8

3

8'

2

8'

1

8

'8

6

5

8'

4

'8

3

8

2

8
000

001

010

all

100

101

110

111

1

ii
Figure 4 - Gain Error

01<---''---'_-'-_......._-'-_..J...._-'-_.1000

010

011

100

101

110

111

Figure 7 - Differential Linearity Error
(Non-Monotonicityl

OUTPUT

FS

001

-------------

II

7

8'
6

Table 1 - Conversion Chart

8'
5

'8

RESOLUTION

#OF

4

BITS

8'

LSB

TEMPCQ PPM/oc - 1 LSB DRIFT OVER

%

FS/64

1.5620

15,625

208.3

8

FSf128

0.7812

7.812

104.2

43.4

2

FS/256

0.3906

3,906

52.1

21.7

~

8

86.8

FS/S12

0.1953

1,953

260

10.9

1

10

FSl1024

0.0977

977

13.0

5.4

0.0488

488

6.5

2.7

o

"

FSh048

12

FSf4096

0.0244

244

3.3

1.'

13

FS/S192

0.0122

122

1.6

068

14

FS/16384

0.00610

61

0.8

0.34

15

FS/32768

0.00305

31

0.4

0.17

16

FS/65536

0.00153

15

02

0.08

8

OFFSETT~~L--L--L--L--L--L---L---~

ERROR_
000

Figure 5 - Offset Error

8-37

HARRIS
SEMICONDUCTOR
PRODUCTS 'DIVISION
A DIVISION OF HARRIS CORPORATION

APPLICATION NOTE
524
ANAlOG-TO-DIGITAl CONVERTER
(ADC)
The uses of high speed DACs in CRT display, industrial
process control, signal regeneration, etc., are well
established. Perhaps one of the most important applications is to· use the DAC in high speed ADC design.
There are two types of ADC design where high speed
and,,~igh resolution DACs are essential.
TRACKING ADC OR SERVO TYPE ADC
The tracking ADC is very efficient in monitoring one
analog signal continuously, converting it into a sequence of digital codes representing the analog signal
in real time.
Functionally, the analog input is compared with the
output of a DAC, with the digital input of the DAC
being driven by a counter. After the ADC is turned
on, the counter increments until the DAC output
crosses the analog input value. The counter will then,
running up or down, drive the DAC 1 LSB at a time
to track the input signal. The counter state represents the digital equivalent of the input signal.

•

In Figure 1, the analog input is fed into the span resistor of a DAC. The analog input voltage range is
selectable in the same way as the output voltage range
of the DAC. The net current flow through the ladder
termination resistance, Le.2k!Hor HI-562A'produces
an error voltage at the DAC output. This error voltage
is compared with 1/2 LSB by a comparator. When
the error voltage is 'within ± 1/2 LSB range, the Q
output of the comparators are both low, which stops
the counter and gives a data ready signal to indicate
that the digital output is correct. If the error exceeds
the ± 1/2 LSB range, the counter is enabled and driven
in an up or down direction depending on the polarity
of the error voltage.
Since the digital output changes state only when there
is a significant change in the analog input, the data
ready signal is then very useful in adaptive systems or
computer systems for efficient data transfer. When
monitoring a slowly varying input, it is ,necessary to

8-38

DIGITAL TO ANALOG
CONVERTER
HIGH SPEED
ADC APPLICATIONS
BY DICK TI TUNG

read the digital output only after a change has taken
place. The data ready signal could be used to trigger
a flip-flop to indicate the condition and reset it
after read-out.
The main disadvantage of the tracking ADC is that the
time required to initially acquire a signal, for a 12
bit ADC, could be up to 4096 clock periods. The
input signal usually must be filtered so that its rate
of change does nat exceed the tracking range of the
ADC (1 LSB per clock period).
SUCCESSIVE-APPROXIMA nON ADC
Perhaps the most widely used technique for a high
speed analog-to-digital converter design is the successive approximation method. Ideal for interfacing with
computers, this type is capable of both high speed
and high resolution, and the conversion time is fixed
and independent of the magnitude of the input
voltage.
Figure 2 shows a block diagram of a successiveapproximation ADC. When a negative going start
conversion pulse is applied to the ADC, the internal
registers of the successive approximation register
(SAR) 'are set to low except for the MSB, which is set
to high. This turns on the MSB of the DAC. The
FS output current of the DAC is compared with the
current fed through the span resistor by the analog
input. The net current flow through the ladder termination resistance produces an error voltage at the
DAC output. This error voltage is then compared
with a fixed reference by a comparator to determine
whether the analog input is greater or less than the
present state of the DAC. The result of the comparison is clocked into the SAR at the rising edge of the
clock. The MSB of the SAR will be set to high if the
analog input is greater; otherwise, it will be set to low.
At the same time, the second bit of the SAR is set
to high with the remaining bits at their previous states.
During the second clock period, the sum of the result
of the first choice and the weight of the second bit is
compared with the analog input. The second bit is
set to high or low in the same manner as the MSB,
and so on, until the LSB is updated.

During this conversion time, the output of a status
flip-flop is set to high, indicating that a conversion is
taking place. It will return to low at the end of conversion to signify that the output state of the SAR
represents the digital equivalent of the input analog
voltage.

This circuit is easy to implement and is especially
useful when an intelligent terminal is not available.
To expand this concept one step further, the gain
error of the system due to temperature variations
could also be eliminated if a binary multiplier is
used to correct the gain facter in real time.

It is easy to see that in any successive-approximation
ADC application, the analog input should remain
reasonably constant during the conversion to avoid
erroneous results. This is usually accomplished by
using a sample-and-hold circuit in the analog line.

ANALOG VIN >------tSPAN R
DAC

HI-562A
, - - - - - - - I I D A c OUT

DATA ACQUISITION SYSTEM
CLOCK

The functional diagram of a 16-channel data acquisition system is shown in Figure 3. Functionally, the
outputs of the binary counter are fed to the 16channel analog multiplexer to serve as the channel
select signals, and it is also fed to the 4 line to 16
line digital decoder as address inputs. At the rising
edge of the clock pulse, an analog input channel is
selected, and the sample and hold circuit (S/H) is set
to sample. The duration of the "1" state of the clock
pulse should be adjusted such that the output of the
S/H would settle to its required accuracy. At the failing edge of the clock pulse, the S/H holds the signal
level acquired during the clock "1" state, and with one
gate delay time, the ADC commences its conversion.
Once the conversion is completed, the CC signal
from the ADC will enable the decoder to send out a
decoded signal to strobe the ADC output into the
proper storage register. The duration of the "0" state
of the clock pulse should be adjusted to allow the
proper data entry to the storage register. The next
analog input channel will be acquired for the next
clock period, and so on. If a 50kHz clock pulse is
used, the data will be refreshed every 320Jls.

>-~-+----r---;>

COUNTER
+1/2 LSB

(74191)

DIGITAL
OUTPUT

r--\Hr-60ns (TYP)
-112 LSB

J

WCLOCK

Figure 1. Tracking ADC

ANALOGVIN

SPANR
DAC

This 16-channel data acquisition system is applicable
to industrial process control, and multi-channel panel
display. It can also interface with an intelligent terminal, such as a micro-computer system, to provide
multi-channel data conversion function. The offset
error and gain error of the data acquisition system
over the operating temperature range can be easily
compensated by proper programming.
By the same token, a 15-channel data acquIsition
system with offset correction could be easily incorporated as shown in Figure 4. Consider the case that
one of the analog input channels is dedicated to sense
the ground level, and its binary equivalent is stored in
latch register B in its complementary form to establish
a ground reference in real time. All the other analog
input channels will then be converted and stored in
register A, one at a time. The binary adder will perform the binary su btraction in less than 1 Jls for the
given pair of A and B. This, in fact, eliminates the
offset error of the ADC, offset error of the S/H circuit,
and excess droop of the SIH due to temperature
variation.

HI-562A
IDACOUT

+v

!
-v

II

D
SAR

>
RB

DIGITAL
OUTPUT

':'

CLOCK

L-_ _~ DATA READY

r--\Hr-60ns (TYP)

J

WCLOCK

Figure 2. Successive-Approximation ADC

8-39

16
CHANNEL
ANALOG
INPUT

•

12BIT
AOC

STORAGE
REGISTER

HI-5712

SELECT
ENABLE

/ MUX & S/H \

~ SETTLING

AOC CONVERSION
.

r
.

CLOCK
PRIORITY
SELECT

CLOCK
INPUT

Figure 3. 16 Channel Data Acquisition System

HI-50616
CHANNEL
MUX

HA-

2425
SIH

12BIT
'IDC
HI-5712

II
TIMING AND
CONTROL

Figure 4. 15 Channel Data Acquisition System
with Offset Correction

8-40

BINARY
ADDER

12BIT
OUTPUT

mHARRIS
APPLICATION NOTE
525

HA-5190/5195
FAST SETTLING
OPERATIONAL AMPLIFIER
G. COTREAU, D. JONES,
R. WHITEHEAD

INTRODUCTION
The military temperature range HA-5190 and its
commercial temperature equivalent, HA-5195, are
monolithic operational amplifiers featuring ±200V 1J1 s
slew rate, 150mHz gain-bandwidth-product, and 70ns
settling time. Similar performance has previously
been available only in more costly modular and hybrid
amplifiers, which require much higher bandwidth and
slew rate to achieve the same settling time as HA5190/5195. Since it exhibits a classical -6dB/octave
rolloff over most of its frequency range, remarkably smooth output wave forms are generated by HA5190 when reasonable care is employed.
Applications for this op amp include pulse, R F, and
video amplifiers, wave form generators, high speed
data acquisition and instrumentation circuits.

INSIDE THE HA-5190/5195

•

Figure 1. HA-5190/5195 Schematic.
Figure 1 shows the schematic of the HA-5190/5195
design. The schematic can be simplified to show the
AC signal path as shown in Figure 2.
The input stage consists of two symmetrical differential transistor pairs. The signal path for positive
going signals is 01, 02, and 03, while negative going
signals pass through 04, 05, and 06. The signal then
goes through the output stage (represented by the
voltage follower symbol) consisting of one PNP and
two NPN emitter followers.
In Figure 2, the compensation network is C1, C2, C3,
and R29. This network makes the amplifier system
appear as second-order critically damped. The scheme
produces the dominant pole plus two zeros. The zeros
are positioned to cancel the effects of undesired poles
developed by the Ft of the transistors.

Figure 2. Simplified HA-5190 Schematic.

8-41

CONSIDERA T/ONS FOR PROTO TYPING
When using the HA-5190, high frequency layout
techniques are recommended for bread-boarding.
The device should be mounted through a ground
plane. If an IC socket is to be used, Teflon types
are recommended. Feedback components should
be mOl)nted between Teflon insulated standoffs
located as close as possible to the device pins.
The input impedance characteristic of the HA-5190
is such that the closed loop performance (DC and AC)
will depend on both the feedback component ratio
and the actual impedance presented to each amplifier
input. For best high frequency performance, resistor
values for feedback networks should be limited to a
maximum of 5K ohms (preferably less than 1 K ohm).
Film type resistors are recommended. Power supply
decoupling with ceramic capacitors from the device
supply pins to ground is essential.

(a) Gain =-1

R,

(b) Stabilization using Z,N.

It is recommended that optimum circuit values for a
particular application be developed through experi··
mentation using amplifiers from several production
runs. The PC artwork in the vicinity of the HA5190 should be prototyped early to determine any
sensitivites to layout.
OPERATION AT ELEVATED TEMPERATURES
HA-5190/5195 may be used without a heat sink up
to +75 0 C ambient. Above this temperature the power
derating is 8.7mW/oC and a heat sink should be used.
THERMALLOY model 6007 heat sink is recommended. For temperatures up to +125 0 C, the thermal
resistance of the heat sink should be 30.6 0 C/W maximum.

C,1000pF

(e) Gain

= +1

~

~

(d) Stabilization using Z,N.
R4

FREQUENCY COMPENSATION
HA-5190/5195 is stable in standard DC amplifier
configurations with closed loop gains exceeding +5 or
-4. At these or higher gains, optimum AC performance
can be achieved by keeping network resistor values as
low as is practical.

II

Quite simple circuitry, as illustrated in Figure 3, gives
excellent performance for lower closed loop gains.
The compensation schemes use the ampl ifier's differential input impedance "to reduce both the input and
feedback signals thereby raising the effective noise
gain approximately 14dB to a stable point on the
frequency response curve.
Inverting and non-inverting unity gain connections for
HA-5190 are shown in Figure 3 (a) and (c). R3 and
R5 serve only to balance DC voltage offsets due to
input bias current, and may be replaced with a short
for AC applications. Cl is not neccessary for stability,
but helps reduce overshoot and smooth the frequency
response. Settling time or frequency response can be
optimized (about 30mHz small signal bandwidth is
practical) by fine tuning component values.

8-42

(e) Non-inverting gain stage.

R2

,-----NI/'---.,,
C2
:
,:
,

(f) Integrator

Figure 3. Compensation 1 + ~
recommended when
R1

< 5.

For closed loop gains between 1 and 5, reducing R 1
in Figure 3 (a) and (e) will raise the gain with minimum effect on bandwidth. However, in the inverting
configuration, R 1 determines the input impedance,
and it may be more practical to raise R2 at the expense of bandwidth. In Figure 3 (e). R4 and R5 may
be reduced as gairl is increased and removed entirely
at gains greater than +4.

.,
Vi- INPUT

·s

v+

.s

~50Kn

~5aKn

.2

.

.4
200KrI:

v-

·3

R:;l00n

2OQKrI:

(a)

·2

(b)

v-

RANGE OF ADJUSTMENT FOR BOTH NON-INVERTING (LEFT) AND INVERTING
AMPLIFIERS (RIGHT) DETERMINED BY PRODUCT OF VSUPPl V AND R3/R4 RATIO.

For applications requiring 100% feedback at high
frequencies, such as integrators and low pass filters,
HA-5190/5195's compensation scheme should be
thoroughly evaluated through experimentation. The
circuit in Figure 3 (f) is quite stable, using the two 1 K
ohm resistors.

AV=1+_R_'_
R2+ R3

Figure 4. Offset Nulling.

SUGGESTED METHODS FOR
PERFORMANCE ENHANCEMENT
To avoid compromising AC performance, the HA5190 design does not include provisions for internal
offset adjustment.

(a)

•

VALUES SHOULD BE DETERMINED
EXPERIMENTALLY FOR OPTIMIZED

PERFORMANCE.

The circuits in Figure 4 (a) and (b) show two possible
schemes for offset voltage adjustment.
Figure 5 (a) and (b) uses the inherent qualities of the
FET to reduce input bias currents by several orders of
magnitude and raise input impedance to thousands of
megohms. Both circuits are shown in the unity gain
follower mode. Circuit gain can be implemented using
normal feedback techniques. To optimize for speed,
care should be taken in layout. Experimental results
yielded slew rates of approximately 130V Il1s.

v+

(b)

R1 AND

R2~15K·

INPUT FETS ARE MATCHED PAIR 2N5564

Figure 5 (c) illustrates a composite inverting amplifier
which greatly reduces DC errors due to the HA-5190
input bias current and gain, while retaining superior
settling time. The 0 dB frequency of the integrator
section approximates the open loop low frequency
pole (",2.5kHz) of the HA-5190. This circuit might
also be connected as a current-to-voltage amplifier
for use with a high accuracy, high speed DAC.
Figure 6 shows a composite amplifier scheme for
boosting output current drive of the HA-5190/5195.
The circuit gain (shown AV = 5) can be adjusted using
normal feedback systems. HA-5190 used in conjunction with HA-2630 can drive 50 ohm coaxial cable with
10 volt peak-to-peak signals at speeds up to 200V 1 11 s.

APPlICA TIONS

RF
RIN

II

10Kn

I

(e)

Figure 5. Reducing Input Bias Currents.

IN

INTRODUCTION

HA-5190/5195 represents an ideal building block for
high speed, precision data acquisition systems and for
video pulse amplification. Although this amplifier can
be used in a wide variety of other applications, the
ones to be discussed show where it can be used most
advantageously.

'Kfl

Figure 6. Boosting Output Current.
8~43

Application 1 Fast DAC Output Buffer
The circuit at right illustrates the HA-5190's usefulness as a high speed DAC buffer.
The amplifier operates as a current-to-voltage converter/output buffer to the HI-5610 which is a precision 10 bit DAC with output current settling time
less than lOOns. The voltage divider on the noninverting input serves to null any DC errors introduced
into the system. The amplifier maximizes speed of the
system since its dynamic performance exceeds that
of the DAC.

Application
1

Application 2 High Speed Sample/Hold
Sample/Hold circuits are used in many areas of data
acquisition systems such as de-glitchers for DIA converters and input stages for successive approximation
AID converters.
The circuit at right uses the speed and drive capability of the HA-5190 coupled with two high speed
DMOS FET switches.
The input amplifier is allowed to operate at a gain of
-5 although the overall circuit gain is unity. Acquisition times of less than 1 DOns to 0.1 % of a 1 volt input
step are possible. Drift current can be appreciably
reduced by using F ET input buffers on the output
stage of the Sample/Hold.

Application
2

'KO

2000
• OPTIONAL (SWITCH DRIVE ENHANCEMENT)

Application 3 Video Pulse Amplifier/75 ohm
Coaxial Driver
HA-5190/5195 is also well suited for video pulse applications. The circuit at right could be found in various types of video broadcasting equipment where 75
ohm systems are commonly employed.
HA-5190 can drive the 75 ohm coaxial cable with
signals up to 2.5 volts peak-to-peak without the need
for current boosting. In this circuit the overall gain
of the circuit is approximately unity because of the
impedance matching network.
Application 4 Output Limiter
HA-5190 is rated for ± 5 volt output swing, and saturates at ± 7 volts. As with most op amps, recovery
from output saturation is slow compared to the amplifier's normal response time; so some form of limiting,
either of the input signal or in the feedback path, is
desirable if saturation might occur. The circuit
above illustrates a feedback limiter, where gain is reduced if the output exceeds ± (Vz + 2Vf). A 5 volt
zener with a sharp knee characteristic is recommended.

8-44

Application
4

:TIT:'J ' -

120

Application
3

n
400n

RIN

75
!1

III H.ARRIS

VIDEO APPLICATIONS
HA-5190/5195

APPLICATION NOTE
526

L. E. GARNER

INTRODUCTION

VIDEO RESPONSE TESTS

Offering superior performance in video and R F circuits, the HA-5190/5195 family can be used effectively in the design of television broadcast studio
equipment, test instruments, and monitoring or
surveillance TV systems. A very high 200V / Jls slew
rate, a full power bandwidth of 6.5MHz, and a fast
settling time of only 70ns (typ) are but three of the
unique characteristics which make these devices
ideal for critical wideband video and R F applications.
Other features include true differential operation,
excellent stability with gains ~ 5, and complete freedom from latch up, the latter a result of the exclusive
HARRIS dielectric isolation process combined with
optimized chip design and layout.

Referring to Figure 1, the test video ampli'fier comprised an HA5190/5195 op amp, BNC coaxial input
jack J 1, input level control R 1 shunted by impedance
matching resistor R2, input series stabilization
resistor R3, gain control network R4-Rgain, series
output limiting resistor Rs, and BNC coaxial output
jack J2.
Operational power was supplied by a
well regulated and filtered dual line operated
power supply.

t::))J2

The op amp family can be used, typically, as studio
tape head, test instrument, and video camera preamplifiers, as buffers, as broadcast relay link repeaters,
as coaxial line drivers, and as cable or industrial
system video repeater and bridging ampl ifiers. Extremely versatile, the devices can be operated effectively in AGC and dc gain controlled configurations
as well as in fixed gain designs, and are fully capable
of driving low impedance loads.
When used in standard video amplifier configurations,
the HA-5190/5195 devices easily meet or exceed the
performance tolerance specifications of applicable
current FCC (NTSC) composite TV signal standards
as well as the requirements of EIA Tentative
Standard RS-170A.

VIDEO

P~RFORMANCE

The overall color video performance of the HA 5190/
5195 family was confirmed by checking a number of
standard devices.
Tests were made to determine
both video response and signal/noise ratio under
typical operating conditions. The basic video amplifier circuit illustrated in Figure 1 was used fo"r the
tests, with the actual procedures abstracted from those
described in EIA Standard RS-250-B. The general
test setup is shown in Figure 2.

RS

Rgain

\;

OUTPUT

R4
lKIl

Figure 1-Test Video Amplifier

TEKTRONIX

1'6A 114BOIOR~
147AVIOEO

TEST

TEST
AMPLIFIER
{FIGURE 11

7sn

I-

TEKTRONIX
520A
VECTORSCOPE

GENERATORS

1051
PROBE

r----...,
HPI715A
200MHa AT
OSCI LLOSCOPE

Figure 2-Video Response Test Setup

8-45

Initially, standard NTSC and EIA ramp and timing
test signals were applied using the Tektronix Models
146A (1480) and 147A video test generators. Amplifier performance was observed and measured at
various levels with a Tektronix 520A Vectorscope
and HP Model 1715A 200MHz delta time Oscilloscope.
Three of the RS-250-B specified test waveforms
used are illustrated in Figure 3, including the (a)
ramp linearity, (b) 12.5T and 2Tsine-sguared pulse
and bar, and (c) multiburst signals. With the test
signal level maintained at 1.0V p-p, level control
R 1 was adjusted as needed to establish a 1.0V p-p
output signal (at J2) for each gain value. The Vectorscope was used to measure color differential
phase and gain, with the Oscilloscope used to check
for distortion of the 2T, 12.5T, multi burst and color
.bar signals. The average test results are summarized
in Table A. All measured values were well within
applicable specifications.

Table A - Summary of Test Results

NOMINAL
GAIN

Rgaln

,.

DIFF

R,

~

OIFF
GAIN

-0.6%

75n
200n
200n

-0.20
-0.15°
_0.2°
-0.40

00

,.

251H
110U

"'"'..

-0,5%

Signal/noise (SIN) ratio measurements were made
using the same basic amplifier configuration, but
with Rgain fixed at 251n. ±.1%. and Rs at 200n
.±5%. The dc power supply terminals were bypassed
with a 100 IJ F tantalum capacitor. A Tektronix
147A NTSC Test Signal Generator was used as a
signal source, with output measurements made using
a Rhode & Schwartz Video Noise Meter, as diagrammed in Figure 4.
The Tektronix 147A was
set to deliver a flat field signal at·50 IRE units, with
the R&S Video Noise Meter adjusted as follows:
(a) 10kHz High pass, (b) Video Bandpass, (c) Subcarrier Trap OFF, (d) Internal Sync, (e) Tilt &
Sag Comp OFF.
Under the specified conditions and with level control
R1 adjusted to deliver a 1.0V p-p signal at J2, the
measured p-p signal/RMS noise ratio averaged 68dB,
or well over the minimum value required by
applicable standards.

COLOR
BARS

2T

12.6T

MULTI

UNM·
UNMUNMUNM*

UNMUNM*

FLAT

FLAT

UNM*
UNM·

UNM*

FLAT
FLAT

UNM*

UNM·

SIN RATIO

UNM*

·UNM : UNMEASURABLE DISTORTION

Figure 4-S/N Ratio Test Setup
100

RAMP LINEARITY
SUBCARRIER = 40 IRE p.p

100

~

f!!

aJ

Z

:>
w

!!:

-40
0-10-16

56586264
~SEC

I

"I'i

SINE -SQUARED PULSE AND BAR (WINDOW)

'111

~'00

IU~

-4,0
0--12-20-24-----50-64
PSEC
0.5 1.5 2.0 3.0 3.68 4.2

I
100
'"
~

c)

~

MHz MHz MHz MHz MHz MHz

"'\

..

.

..

\-

100

IIWJLllBURST
NORMAL·
REDUCED--

w

!!:

o

I

-40
0-10-16-22-30-36-42-48-54-62-64

GENERAL CONSIDERATIONS
Sil1ce the HA-5190/5195 devices do notrequire special
treatment, optimum video performance can be
achieved by observing standard high frequency design
and wiring practices. However, the following suggestions, abstracted in part from HAR R IS Application
Note 525, should prove helpful when developing
practical designs.
POWER SUPPL V RE.QUIREMENTS
A well-regulated, well-filtered dual dc power source
is required for best operation, for the op amps
draw moderate. currents during normal operation.
Although not essential in all appl ications, it is recommended that the power supply lines be decoupled
using 0.01 p F ceramic capacitors to circuit ground,
with the capacitors located as near to the amplifier
terminals as possible to minimize lead inductances.
For optimum performance .and operation at specified
parameters, the dc power supply should furnish
not less than :!:.1 OV dc, with higher source voltages
(±15V, typically) preferred.

~SEC

TEMPERATURE CONSIDERATIONS
Figure 3-Video Test Signal Waveforms

The HA-5190/5195 devices can be used without heat
sinks at ambient temperatures up to 75 0 C. Under
these conditions, the internally generated heat stabilizes device operation and ensures relative immunity

8-46

to external temperature variatIOns.
At ambients
above 75 0 C, however, the devices should be derated
at 8.7mW/oC, with a suitable heat sink, such as a
THERMALLOY
Model 6007, used to provide
adequate heat dissipation. At temperatures up to
+1250 C, the thermal resistance of the heat sink
should be no greater than 30.60 CIW.
Under some conditions, the internally generated heat
can affect other components.
Therefore, avoid
mounting temperature sensitivedevices or components
near or directly adjacent to the op amps.
DESIGN HINTS
Except for their exceptional performance specifications" the HA-5190/5195 devices are essentially
standard op amps and may be treated as such by the
video equipment or system designer. Thus, conventional design techniques may be used when developing specific circuit configurations, as long as maximum ratings are observed and adequate compensation is made for device operational characteristics.
For example, the closed loop performance (dc and
ac) at gains2:5 depends on both the feedback component ratio and the actual impedance at each amplifier input. Since the devices offer a comparatively
low input impedance, feedback network resistor
values should be 5k or less (preferably, less than
1k) for optimum high frequency performance.
If the intended video application requires a high input
impedance, a FETpreamp stage may be added ahead
of the HA-5190/5195 op amp, as shown in Figure 5.
Full details and an additional FET input circuit are
provided in HARRIS Semiconductor Application
Note 525.
Where used, a FET preamp not only raises the effective input impedance from (approximately) 10k
to thousands of megohms, but also reduces the input
bias current requirement by several orders of magnitude. There is, of course, a trade-off in frequency
response, with a FET input stage reducing the effective overall slew rate from 200V/jls to 130V/j.ls
(typically).
However, the full power bandwidth
with a FET input' is more than adequate for all low
to mid level video applications.

v+

OUTPUT

• R1
15K

Some video applications may require output currents
which exceed the maximum capabilities of the HA5190/5195 devices.
In these cases, the HA-5190/
5195 op amps can be teamed with high performance
current boosters such as, for example, the HA-2630/
2635 devices. A typical cascaded op amp/booster
circuit is illustrated in Figure 6. Since the current
booster, a unity gain device, has a typical slew rate
and bandwidth (Slew rate 500V/jls, BW 8.0MHz)
far greater than that of the op amp, the overall frequency performance of the composite amplifier
is essentially that of the op amp alone.
To compensate for manufacturing tolerances and
ensure optimum performance, the fixed component
values used in specific designs should be finalized
empirically, using active devices from several production runs.

v+

v+

BNC

son

v-

v-

.001p.F

.OD1J.1.F

V Supplv~ .:t12V

Figure &-Boosting Output Current

PROTOTYPING TIPS
In accordance with standard engineering practic.e,
new circuit designs should be breadboarded to verify
overall operation.
Afterwards, a number of preproduction prototypes identical to the planned production design should be assembled and tested using
active devices from several production runs. These
prototype tests permit optimization of component
values and determination of circuit sensitivities to
layout and component positioning.
Preliminary
environmental tests, if required, also may be made
using the prototypes .

* R2
15K

vo Approximate

Values

Figure 5- FET Input Circuit

If IC sockets are used, Teflon types are preferred
to minimize distributed capacitances. For the same
reason, feedback comppnents should be mounted
between Teflon insulated standoffs located as close
as practicable to the device pins or socket terminals.
For maximum stability, film type resistors are recommended for the feedback networks.

8-47

Signal carrying leads should be kept short and direct,
of course, to minimize both lead inductances and
distributed capacitances.
The devices should be
mounted through a ground plane cr, if this is impracticable, single point grounding should be used
to avoid ground loops.

OCl

C2
O.OlPF

TYPICAL APPlICA T/ONS

R7
75n

~
RF

INPUT

OUTPUT

The test circuit given in Figure 1 may be used as a
general purpose video amplifier, although minor
changes in component values may be needed to
optimize operation for specific requirements. Additional practical circuits are illustrated in Figures
7 and 8.

R4

10KIl

-=

DCl - CLAIREX eLM 6000

+12V

RS
lKIl~I-_-'

RF AGC AMPLIFIER

RS
10KS1

Designed and checked as a buffer for the head preamp of a studio video tape recorder, the circuit
shown in Figure 7 functions as a wide band adjustable AGC amplifier.
With an effective bandwidth
of approximately 10 MHz, it is capable of handling
R F input signal frequencies from 3.2 to 10MHz at
levels ranging from 40mV up to 3V p-p.
AGC action is achieved by using opto coupler/isolator
OCI as part of the gain control feedback loop. In
operation, the positive peaks of the amplified output
signal drive the OCI LED into a conducting state.
Since the resistance of the OCI photosensitive
element is inversely proportional to light intensity,
the higher the signal level, the lower the feedback
resistance to the op amp inverting input and hence
the greater the negative feedback, thereby lowering
stage gain.
Any changes in gain occur smoothly
because the inherent memory characteristic of the
photoresistor acts to integrate the peak signal inputs.
In practice, the stage gain is adjusted automatically
to a point where the output signal positive peaks
are approximately one diode drop above ground.
GAIN SET control R5 applies a fixed dc bias to the
op amp non-inverting input, thus establishing the
steady-state zero input signal current through the
OCI LED and determining the signal level at which
In experimental tests under
AGC action begins.
large signal conditions (i.e., EIN = 3V p-p), a GAIN
SET value of -0.26V provided unity gain, while a
value of -1.55V yielded on AV of 2.7 ,with a flat
response to 5.0MHz at both levels.
Under small
signal conditions (i.e., EIN = 40mV), gains from 8
to 50 could be achieved as the GAIN SET value
was adjusted from 0.65V to -80mV.
At AV = 8,
the frequency response was flat to 5MHz, while at
AV = 80, the response was limited to that of the
HA-51 90/51 95.
The effective AGC range depends on a number of
factors, including individual device characteristics,
the nature of the R F drive signal, the initial setting
for R 5, et al.
Theoretically, however, the AGC
range can be as high as 4000: 1 for a perfect op amp,
for the OCI photoresistor can vary in value from
1 Megohm with the LED dark to 250n with the
LED full on.

8-48

GAIN SET

-12V

Figure 7-R F AGC Amplifier
+12V
R2
v-p-p

S.6Kn
R4

VIDEO
INPUT

7sn

VIDEO
OUTPUT

Rl
7511

RS

240n
-12V

01

,r-,

,
,,, RB
,
, -=

l_~~I~_J

2N3904

C3
0.1/1 F

+12V
OC1-CLAIREX elM 8500/2
Cl, C2 - TANTALUM TYPES

Figure a-DC Gain Controlled Video Amplifier (Analog Multiplierl

DC GAIN CONTROLLED VIDEO AMPLIFIER
Suitable for use in virtually any application requiring
a variable gain wideband or video amplifier, the
circuit illustrated in Figure 8 employs a cascaded
op amp integrator and transistor buffer (Q1) to drive
the amplifier gain control element.
Except for a
simple modification, the HA-5190/5195 stage is
connected as a conventional non-inverting operational amplifier, and includes input and output
impedance matching resistors R 1 and R4, respectively, series stabilization resistor R2, and power supply bypass capacitors C1 and C2. The circuit differs
from standard designs in that the gain control network includes a photoresistor, part of OCI.

Referring to the schematic diagram, opto coupler/
isolator OCI contains two matched photo resistors,
both activated by a common LED. The effective
resistances offered by these devices is inversely proportional to the light emitted by the LED. The
greater the current through the LED, then, the more
intense its light emission, and the lower the effective
One photoresistor is
values of the photoresistors.
part (with R3) of the HA-5190/5195 gain network,
while the other forms a voltage-divider with R6
to control the bias applied to the integrator noninverting terminal.
In operation, the dc voltage supplied by GAl N
control R8 is applied to the integrator inverting
input terminal through input resistor R7. Depending
on the relative magnitude of the control voltage,
the integrator output will either charge or discharge
C3. This change in output, amplified by Q1, con·
trois the current supplied to the OCI LED through
series limiting resistor R5.
This action continues
until the voltage applied to the integrator noninverting input by the R6-photoresistor voltage
divider matches the control voltage applied by
R8 to the inverting input.
At the same time, of
course, the ratio of the R3-photoresistor gain network
is changing, adjusting the op amp stage gain.
As
the control (R8) voltage is readjusted, the OCI
photo-resistances track these changes, automatically
readjusting the op amp gain in accordances with the
new control voltage setting.

ACKNOWLEDGEMENTS
A.

J. Carl Cooper of HARRIS CVS (Consolidated
Video Systems), 1255 E. Arques Ave., Sunnyvale, CA. 94086, developed the basic circuits
described herein and, in addition, devised
and executed the initial evaluation and performance tests.

B.

Richard Whitehead and Robert Junkins of
HARRIS SEMICONDUCTOR, P.O. Box 883,
Melbourne, Fla. 32901, carried out additional
confirmation tests of circuit performance
and made other significant contributions
to this publication.

REFERENCES
1.

HA-5190/5195 Wideband, Fast Settling Operational Amplifiers (Harris data brochure)

2.

Application Note 525 - HA-5190/5195 Fast
Settling Operational Amplifier.
May 1979.

3.

EIA STANDARD RS-170A - Color Television
Studio Picture Line Amplifier Output.

4.

EIA STANDARD RS5-250-B - Electrical Performance
Standards
for Television
Relay Facilities.

In experimental tests with typical devices, the amplifier gain could be varied from 12dB to 2dB as the dc
control voltage was changed from 5.0 to 10.5Volts.
Typical plots of stage gain (AV) versus control
voltage (V) are shown in Figure 9.
Since all temperature sensitive components are inside
the integrator feedback loop, the circuit is quite stable
with respect to changes in the ambient temperature.

II

I

12

"'-

0

8",

"-

1,+: 12Vl
EIN :: 200 mV
FREQ::z DC to 5MHz
PULSE @ 50% DUTY CYCLE

I"'""'-

~f:11.24K

'" "'. "
"'"
~

4

Rf:56K

"'- J'-..

r'\

"o

5

I

'"
8

9

10

11

12

GAIN AOJUST VOLTS

8-49

m

APPLYING THE HI-5900
ANALOG DATA
ACQUISITION SIGNAL
PROCESSOR

H.ARRIS

. APPLICATION NOTE
521

BY JOHN E. SULLIVAN
JUL Y 1981

INTRODUCTION

abled to the high impedance state. All analog input
lines have full overvoltage protection and can tolerate
inputs up to 20. volts in excess of the power supply
voltages for extended periods and transient spikes up
to several hundred volts.

The HI-59QQ Analog Data Acquisition Signal Processor
is a powerful building block for use in a Data Acquisition Subsystem (DAS), or in stand-alone operation.
Incorporati'ng a diffe.r.tmtial analog multiplexer, a programmable gain instrumentation amplifier and track
and hold· amplifier, ~he HI-59QQjs an ideal signal conditioning element for a wide range of commercial, industrial and military applications.

Expansion lines, MUX OUT A and MUX OUT B, can
be used either to expand the number of input channels
or as monitor outputs. The multiplexer exhibits a
nominal 2 kilohm ON resistance; therefore, when
using MUX OUT A or MUX OUT B as monitor points,
a high impedance monitor ( > 1 megohm) should be
used to minimize loading affects.

FUNCTIONAL OPERA TION
OF THE HI-5900
As illustrated in Figure 1, the HI-59QQ incorporates
three primary components. An input multiplexer controls selection of the signal to be processed, the programmable gafn instrumentation amplifier provides
common mode signal rejection and gain while the
track and hold amplifier stores the instantaneous
signal level forfinal signal processing. Signal acquisition,
including multiplexer, amplifier, and track and hold
settling times, is less than 1Q,(.Is to 0..0.1% accuracy.

"

The multiplexer selects one of eight possible differential
analog input signals to be processed, or ~t can be disINPUT
MULTIPLEXER·

Select lines AQ, A1 and A2 operate in binary mode
(0.0.0. selects channel 1 and 111 selects Channel B). The
enable line, when LOW, DISABLES the multiplexer
and forces its output to the high impedance state. Both
the select and enable lines have an operating range of
V- to +o..B volts for a logic 0. input and 4 volts to V+
for a logic 1 input. When driving these inputs with
TTL logic, a 1 K ohm pullup resistor is recommended
to ensure proper switching. All unused inputs (both
signal and control) can be hardwired to either V-or
ground for a logic 0. and +5 volts (VCC) or V+ for
a logic 1.

TRACK AND HOLD
AMPLIFIER

CHAN 1 A - L - - , /

BI4--'/
A·-L-_,/

CHAN8

~

_ _ _~

BI-t::~~~::::~J
AO Al A2
CHANNEL
. SELECT

EN

MUX
OUT
B

GO
Gl
GAIN
SELECT

V REFERENCE
T/H HOLDING
LOW
CONTROL CAPACITOR

FIGURE 1 - FUNCTIONAL BLOCK DIAGRAM

8-50

PROGRAMMABLE GAIN INSTRUMENTATION
AMPLIFIER

urations such as level shifting or- quasi-differential outputs can also be implemented as shown in Figure 5.

The programmable gain instrumentation amplifier
(PGA) operates in the true differential mode with A
input signals being inverted and B input signals being
non inverted. Some applications will have true differential input signals with an infinite impedance to ground.
These applications should incorporate a 5 megohm
resistor to ground from both the MUX OUT A and
MUX OUT B outputs to allow amplifier bias currents
to flow to ground.
The PGA has digitally selectable gains of 1, 2, 4 and 8
in binary format (00, G = 1; 11, G = 8). The digital
control levels are identical to those of the input multiplexer, and as such require 1k ohm pullup resistors
when driven from TTL logic.
The VREF LOW line can be tied to ground or used for
offset nulling as illustrated in Figure 2. Other config-

13
14
A
B
MUX
OUT

CHl
CH2

TRACK AND HOLD AMPLIFIER
The track and hold amplifier stores and holds the
instantaneous signal level applied to its input when the
T /H line goes to a logic 1. The T /H mode control is
fully TTL compatible and requires no pullup resistor,
with the track mode defined as -5 to +0.8V and the
hold mode defined as +2 to +7 volts.
An external holding capacitor (typically 1000pF to
minimize pedestal errors and droop rate) is used to
store the signal level while in the hold mode. This capacitor should be selected for minimum dielectric
absorption and leakage as found in Teflon or polystyrene types. As shown in Figure 3, the acquisition
time vs. accuracy vs. droop rate is a function of the
value of the holding capacitor, and can be chosen to
optimize anyone parameter for a given application.

10,000

1== DRIFT DURING HOLD AT +25 C;
0

18
CH3

VOUT

1,000

~

MILLIVOLTS/SECOND

/

CH4
12
CH5

+15V
10pF

3

CH6
CH7

21

-15V

~

10

........

T/HCH
1617

VCC
1.0

~1000PF

DIGITAL
CONTROL
INPUTS

-

SAMPLE TO HOLD
OFFSET ERROR:
MILLIVOLTS

GND
10pF

CH8

~

100

1

r---

L

~

1/

)

~

"-

MINIMUM SAMPLE TIME FOR
0.1% ACCURACY, 10V SWING
MICROSECONDS
0.1

II

I"-.

I

A2
Go
<>-::Gc1- - - - - - '

0.01
10pF

<>-=:'fIH.!.-------J
~~--------------_J
'THESE PULLUP RESISTORS
ARE USED WHEN INTERFACING TTL LOGIC ONLY.
VOUT = G(B-A) + VREF
G=1,2,4,8

100pF

l,OOOpF

O.OlI1F

O.lI1F

1.01lF

CH VALUE

FIGURE 3 - TYPICAL SAMPLE AND HOLD
PERFORMANCE AS A FUNCTION OF HOLDING CAPACITANCE.

FIGURE 2 - TYPICAL CONFIGURATION

8-51

APPLICA TION HINTS
1. Expanding the Channel Capacity of the HI-5900

2. The HI-5900 in a Two-Chip DAS

Figure 4 illustrates a typical HI-5900 with its
channel capacity increased from 8 to 16 channels.
Further expansion can easily be implemented by
adding more address lines (each additional address
line doubles the channel capacity) and the required control logic to enable each multiplexer.

The HI-5900, when teamed with the HI-5712
AID converter as illustrated in Figure 5, will
provide a two-package DAS with 12-bit accuracy
and a 50kHz throughput rate. The gain selection
of the H 1-5900 gives this system a dynamic range
of 15 bits.

+15V

29

CH1

GND

-15V

r---~--~~--"::":'L--.....,

---------------;

MUX

4

OUT
18

HI-5900
CH8

VOUT

22

MUX

11

OUT
AOA1 A2EN A 6

+15V GND -15V
19r.A:--~-'--""'"

CH9

.

CH16

• 11 B
• 26

I---+-+--+-+--.J

HI-507A

A
6 2
4 6 AO A1 A2 EN 1'=---+-+-+-+------'

17 16 15 18
AO------+-+--+-+----~

A1--------~T-1-----~
A2----------~-r--------~
A3------------~--_;~----.J

FIGURE 4 - EXPANDING THE HI-5900 TO 16 INPUT CHANNELS.

SELECTED
CHANNEL
1
2
3
4

5
6
7

8
9
10
11
12
13
14
15
16

8-52

A3

A2

Al

AO

0
0
0
0
0
0
0
0
1

0
0

0
0
1

0

1

1
1
1
1
1
1

0

1

0

0

1

1

1
1

0
0
1

0
1

1
1
0
0

1
0

0

1

0

1

0
1
1

1
0

0
1
0
1

1

1

1

1

0

0
1
0

0
1

+15V

12
CHl
CH2

lA

-15V

OUT

2A

3B
4A

CH6

CH7

CH8

6A
6B
7A
7B
8A

GND

-=- STYRENE
VREF

CHANNEL
ADDRESS
SELECT
GAIN
SELECT
BYTE ENABLE

I

15

13
A
MUX
14
B
T/H
Gl
A2 GO

MUX ENABLE

B2

16

B3
B4

CH
1000pF
TEFLON
OR POLY-

HI-5900

4B

5B

BIT 1 (MSBI

ZERO

CH 17

5A
CH5

10V FS
IN
100Kn

2B

CH4

18

lB

3A
CH3

40

21

HI-5712
4
j+15V

B5

REF LO SENSE

B6

BIPOLAR
OFFSET

B7

VREF SENSE

Bl0

VREF OUT

Bll

B8

50n

100Kn

PARALLEL
OUTPUT

B9
20Kn

39
38

lOOn
-15V

B12 (LSB)

son
1-8
37

19
31

SERIAL OUT

VREFIN
9-12

CLOCK OUT

1-8

MSB/MSB INPUT

STATUS (EOCI

STARTCONV.

-=-

I
* Value depends on operating mode.
See HI-5712 Data Sheet.

STARTCONV.

FIGURE 5 - DATA ACQUISITION SYSTEM (USING ONLY TWO PACKAGES).

II

8-53

m~RIS
APPLICATION NOTE
528
INTRODUCTION
The microprocessor, with its inherent ease of use
flexibility, and numerical computing capability, ha:
become a powerful tool for control and processing in a
host of commercial, industrial and military applications.
This tool, however, has had limited success in those
applications interfacing the real world of analog signals.
Until recently the Analog to Digital Converter (ADC),
which is the analog input interface to the microprocessor, has only fulfilled part of this function. Various
devices are available to easily interface the input analog
signal, but require massive support to interface with
the microprocessor. This "extra" interface support not
only increases the overall system cost and complexity,
but also reduces flexibility. The development of the
H 1-5712, 12 bit high performance analog to digital
converter solves these and other problems by providing
both an analog and microprocessor interface in a compact dual-:in-line package. An LSI circuit performs all
logic and interface functions while the balance of the
device performs analog processing. Packaged in the
unique Leadless Chip Carrier (LCC) - Hybrid form, the
H 1-5712 provides all the functions required to interface an analog signal to a microprocessor.

DIGITAL INTERFACE
The successive approximation conversion technique is
used in the HI-5712, as illustrated in Figure 1. The
Successive Approximation Register (SAR) contains all
of the digital interface and control logic for conversion
and interface control. Constructed using a modified
CMOS process (SAJI), the SAR combines the best features of CMOS and TTL logic. All input or output lines
are f.ully TTL/CMOS/NMOS compatible, with inputs
having low loading, and outputs providing 3.2mA ofsink
current in the active mode and less than 25~A loading
in the three state mode. All outputs are of a three state
design. Data output lines are enabled with a combination

8-54

INTERFACING
MICROPROCESSORS AND
MICROCOMPUTERS WITH HI-5712
HIGH PERFORMANCE 12-81T
ANALOG-TO-DIGITAL CONVERTER
BY JOHN E. SULLIVAN

of chip enable and three state enable lines, while all
other outputs are enabled using only the chip enable line.
The output is structured in byte format with the most
significant eight bits enabled by the enable bit EN 1-8
control line, and the least significant four bits enabled
by the enable bit EN 9-12 control line. For 8-bit
bus applications, the SAR 8-bit output bus can be
hardwired in parallel with the SAR 4-bit output bus,
eliminating the need for external drivers (see Figures 2
and 3). The fast enable/disable time (typically BOns)
of the output drivers, and their low loading characteristics minimize system integration problems for applications using unbuffered microprocessor buses (Figure 3).
The input architecture of the SAR, provides for realtime program control of analog signal conversion. Two
control lines, SHORT CYCLE A and SHORT CYCLE B,
control the conversion process. Conversion of B, 8; 10
or 12-bit analog signals can be configured as per
Table 1. The output format, either binary or twos
complement is controlled with the MSB/MSB select
Iine. These control lines are all internally latched into
the SAR command register on the falling edge of the
START CONVERT signal. These input lines can
be hardwired to VCC, ground or directly connected to
the microprocessor for dynamic program control as
illustrated in Figure 3.

TABLE 1
SHORT
CYCLE A

SHORT
CYCLE B

CONVERSION
RESOLUTION

0
1
0
1

0
0
1
1

B Bits
8 Bits
10 Bits
12 Bits

20V 10V BIPOLAR VREF
FS FS OFFSET IN
564

VREF VREF
OUT SENSE

2

NC~J 2~

2k

l36

2k

4k

12 BIT DAC
CHIP ENABLE ~I-r----'-"""'''''''''''''''''''''''''.J...I.-'---.
STATUS
STARTCONV.
CLOCK IN
CLOCK OUT
SERIAL OUT
MSB/MSBSEL
SHORTCYA
SHORTCYB

r-~~~~~~~=f~~rrl:k~--~

FIGURE 1 - HI-5712 FUNCTIONAL BLOCK DIAGRAM

CHIP ENABLE
START CONVERT
STATUS
CLOCK-IN
CLOCK OUT
SERIAL OUT
SHORTCYA
SHORTCYB
MSB{MSB

012

IIIIIIIII III

33
31
32

-

29
13
10

SAR

11
12
30

COMMAND
REGISTER

:
I
I
I

J

'---

HI-571 2
LSB

MSB

ENABLE~~8-~2~2:f5

2423 2219 18

1716 1514

t::~:L

--'
E9-12

DATA
OUTPUT
LINES

DO

FIGURE 2 - HI-5712.DIGITAL INTERFACE

CHIP ENABLE
START CONVERT
STATUS
CLOCK-IN
CLOCK OUT
SERIAL OUT
SHORTCY A
SHORTCY B
MSB{MSB

I I I I II I I I I I I

33
31
32
29
13

I"SAR

10

~
,!430

COMMAND
REGISTER

I
I
I

I

MSB

~

HI-571 2
LSB

- 16- 1514
-L---~i27 2625 2423 2219 18 17

8

------ --'

ENABLE
1-8

07
'--ENAB LE 9-12

MICROCOMPUTER
OR
MICROPROCESSOR
BUS
DO

FIGURE 3

8-55

Systems requiring serial data transfer can use the serial
output data port and clock output to transfer errorfree data over twisted pair lines. The SAR also contains an external clock input for those applications requiring external clock synchronization. The balance of
the H 1-5712 contains analog processing and conditioning circuits for conversion of the input signal.

Four microcomputer control lines along with the microcomputer bus satisfy all of the interface requirements.
Two of the control lines control the flow of data onto
the microcomputer bus. The remaining two control
lines start ADC conversion and interrupt the microcomputer when data is available. As discussed previously, the command register lines, the four least significant ADC data lines, and the eight most significant
ADC data lines are wired in parallel to the microcomputer bus or port. This configuration typically utilizes
less than 10% of the bus or port drive capability, allowing connection of additional peripheral support chips,
and eliminating the need for buffer or driver devices.

MICROCOMPUTER INTERFACE
Microcomputer systems using the HI-5712 ADC, unlike
other converters, usually require no additional parts for
optimum performance. Figures 4 and 5 show interfaces
with the Intel 8748 and Motorola 6801 microcomputers.
These examples are also applicable to most currently
available microcomputers.

The simplicity of the hardware interface correlates
directly with minimal software requirements. The software flowchart in Figure 6 illustrates typical operation.
The control word to the H 1-5712 need only be applied
during the falling edge of the START CONVERT line.

ANALoGINpUT-----------+r---------------l
~--------~STATUS

\

START CONVERT

HI-5712
ANALOG TO DIGITAL
CONVERTER

INTEL 8748
MICROPROCESSOR

r-~IN"'T,."E~RR",U"'P==T,...,
PORT 2

=

BUS i-=c=:::---------'''"'''---'"I TO OTH ER
t-=-=-=-------------lf DEVICES
PORTO

FIGURE 4 - INTEL 8748 MICROCOMPUTER INTERFACE WITH
HI-5712 ADC

ANALOGINPUT-------+r---------------,
HI-5712
OUTPUT
ANALOG TO DIGITAL
CONTROL
CONVERTER
START
CONVERT

MOTOROLA
6801
PORTl
XTAL

=

PORT 3

PORT3~==~------------~~TOOTHER
~=-=---------------~ DEVICES
PORT4

FIGURE 5 - MOTOROLA 6801 MICROCOMPUTER INTERFACE
WITH HI-5712 ADC

8-56

After meeting the minimum required set-up and hold
timing, the data can be removed, freeing the bus for
other functions. When the microcomputer receives the
interrupt signal, signaling data available, data is then
read in two bytes. Since reading of the data is nondestructive, the order of reading can be configured to
minimize software requirements.

rent drive capability, and can therefore be treated as any
other high impedance NMOS peripheral support device.
The software requirement is the same as a microprocessor interface. Command register data can be loaded
during a Write cycle with the converter automatically
initiating conversion of the rising edge of the Write
signal. Data is inputted to the microprocessor in the
same two byte format.

These microcomputer interfaces, although deceivingly
simple, will operate at up to 100kHz throughput rates.
At these speeds, high performance complex analog signal processing, for speech, process control and signal
analysis applications can be easily implemented.

The high speed nature of the H1-5712 ADC provides
all of the necessary capabilities for use with advanced
signal analysis techniques. It should be noted, however,
that a 12-bitconversion is completed in 8 microseconds.
To fully utilize these high speed throughput rates,
microprocessor systems will require operation with a
high speed Direct Memory Access (DMA) as most
microprocessors cannot keep pace with a 10 microsecond or faster ADC. Systems not incorporating a
D MA or other high speed transfer device will be
throughput-limited by the microprocessor and not the
ADC.

MICROPROCESSOR INTERFACE
Microprocessor systems are available in two types: the
minimum or unbuffered system, and the maximum or
fully buffered system. The minimum system is usually
found in dedicated or control process applications,
while the maximum system is more common in the
general purpose application. The H 1-5712 ADC is
equally well suited for both applications with only a
bus driver added to the minimum system configurations discussed here to support the very high drive requirements to the larger maximum system.

CONCLUSION
High performance analog processing systems using
microprocessors can now be easily designed using a
minimum of hardware and software support. By careful utilization of the versatile I/O features of the H 15712, many applications can be implemented with no
digital interface hardware and far less software than
with other conventional devices. New horizons in signal processing are now realizable. The HI-5712, with
its advanced I/O and superior analog characteristics, is
an ideal solution for microprocessor/microcomputer
systems with analog input interfaces.

As with any peripheral device, the H 1-5712 ADC requires address decoding as illustrated in Figure 7 and 8
(Intel 8085 and Motorola 6800 interfaces). The interrupt flip-flop provides stable interrupt generation to
notify the microprocessor of data availability when
conversion is completed. In a manner similar to the
microcomputer, the command register lines and output
data lines can be wired in parallel. The minimum system application requires no buffering as the HI-5712
simultaneoulsy exhibits minimum loading with high cur·

I
I

DAS
ROUTINE

CONTROL WORD
TO BUS

I

II

I
I

I

J

L------l~I

INITIATE
CONVERSION

L

r'--

FIGURE 6 - SOFTWARE FLOW CHART FOR MICROCOMPUTER
OR MICROPROCESSOR CONTROL OF ADC

8-57

.-1'-------,

ANALOG INPUT SIGNAL _ _ _

HI-S712

ANALOG TO
DIGITAL

INTEL
8085

~A~D~DtR~ES~S~B~U~S~A8~_~A~'5~~~j[~~~J(TOOTHER
~~~~:;=====II====( DEVICES
CONTROL BUS

FIGURE 7 - INTEL 8085 MICROPROCESSOR

+t

ANALO~II~~~[ _ _ _ _ _ _ _ _ _ _ _ _ _

HI-S712
ANALOG TO
DIGITAL
CONVERTER

OUTCOMMAND PUTS

STATUS

REGISTER

1-8

DECODER

II

8205

INT

XTAL

c::J

MOTOROLA

h __---.:D=A:::T::A~B:.:U.:S_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ___,j

6800

DEVICES·
ADDRESS AND CONTROL

FIGURE 8 - MOTOROLA 6800 MICROPROCESSOR
WITH HI-5712 ADC

8-58

TO OTHER

IJ~RIS
APPllCA TION NOTE
629

M ICROPROCESSO R
INTERFACE METHODS
FOR HIGH-SPEED DATA
ACQUISITION SYSTEMS
BY L. E.

EN~IQUEZ,

J. E. SULLIVAN,
D. T. TUNG

Since their introduction in the early 1970's microprocessors
have dramatically displaced random logic for system design.
This explosive growth of microprocessor applications has
greatly influenced the increased use of peripheral interface
integrated circuits (lC's). These special IC's were developed
to support CRT's, printers,floppy disks and other peripheral
devices, but virtually none were offered for analog input
signal comU~oning and conversion. Typical systews using
a single microprocessor board and multiple analog interface
boards became commonplace due to the lack of suitable
analog interface IC's. Today, new units are available which
provide microprocessor compatibility with analog input
signal conditioning and processing within compact hybrid
devices comparable in size to individual IC's. These new
products permit the assembly of a complete analog interface
and microprocessor system on a single board no larger than
those used in the past for the microprocessor alone. The
HI-5900 and the HI-5901 analog signal processors and the
HI-5712 Analog to Digital Converter (ADC) are state-ofthe-art versions of these new hybrid devices.

subsystem. The, H1-5900 includes an eight-channel differential input multiplexer, a precision gain programmable
instrumentation amplifier and a unity gain track-and-hold
stage.
Designed for 16-channel pseudo-differential or
single-ended applications, the HI-5901 features a 16-channel
multiplexer,a precision gain programmable instrumentation
amplifier and a unity gain track-and-hold amplifier. All
input control lines are microprocessor compatible and well
suited for NMOS, CMOS, and TTl logic.

A typical analog to microproces~or interface (data acquisition
subsystem) consists of five functional blocks. (See Figure 1).
Multiple input signals are accepted and selected by the input
multiplexer, with the programmable gain instrumentation
amplifier providing both common mode signal rejection and
signal amplification. Additional signal processing is required
between the output of the instrumentation amplifier and the
AD C, for the latter cannot convert a co~tinuously changing
analog signal into digital form. Th.e additional processing
is provided by the track-and-hold stage, which. samples
the instantaneous value of the analog signal on command
and holds this level as a steady input to the ADC until the
conversion cycle is completed. The AD C supplies a series of
digital output words, which correspond to the individually
sampled analog levels. Finally, digital logic circuitry is
required to interface the function control signals from the
microprocessor to the individual circuit elements.

Unlike conventional hybrid technology, thase products are
fabricated using leadless chip carrier (lC.C) techniques,
which employ IC dice packaged in lCC's mounted to both
sides of a multilayer ceramic substrate. The final product
comprises hermetically-sealed building blocks, each visually
inspected and mechanically and electricallY teated to the
htghest standards of commercial, industrial, or military
specifications prior to assembly. Subsequently, additional
visual and electrical tests are made to the completed hybrid
device at nominal and rated temperature extremes to ensure
maximum reliability and optimum performance.

As shown by the dotted lines in Figure 1, two hybrid devices,
the HI-5900 (or the HI-5901), and the HI-5712 contain all
of the necessary analog and digital building blocks needed,
for a complete two package, multi-channel data acquisition

The HI-5712 is a 12-bit, high speed ADC'Which features a
microprocessor compatible tri-state output bus and software
programmable output code and word length controls permitting its application in 8, 12, and 1S-bit systems. Accepting
either unipolar or bipolar inputs, the device incorporates
input latches on all digital control lines, assuring full compatibility with TTL, CMOS, and NMOS logic. The unit
also features an on-board, overridable, precision +10 volt
reference with sufficient output current ca~ability for
external applications.

II
.

When used in combination, the HI-5900 (or 5901) and the
H1-5712 fofiii a high performance, extremely accurate twopackage daia acquisition subsystem with a 50 kHz (600 kbs)
throughput rate: The system is compatible with all standard
microprocessor system~ although the interface peripherals
required will vary from one system to another, depending on
individual system complexity. An example of a two chip,
high performance data acquisition subsystem using a microcomputer is illustrated in Figure 2. This example, using the
Intel 8748 series microcomputer, is applicable to any of the

8-59

I

As with any peripheral, a bus driver and address decoder is
required. The octal latch provides stable control information
during signal acquisition while the one-shot generates a
start convert pulse after the required 10 )J sec delay. Two
I/O locations are used for the interface: one location is
used for both Read and Write and the other is a Read only.
A Write to the first location loads multiplexer gain and AOC
control information and 10 jJ sec after the Write initiates
a conversion cycle. At the end of conversion an interrupt is
generated informing the microprocessor that data is available. Data can then be read in the same two byte format
as previously discussed for the microcomputer. Software
control for this application is merely a driver routine to
support the two I/O locations and the interrupt routine,
with all timing functions being generated in the hardware.

currently available chip microcomputers. Both hardware and
software' requirements have been minimized to reduce costs
and provide maximum flexibility.
Four microcomputer control lines along with the microcomputer bus satisfy all of the interface requirements. Two
of the lines are used to initiate data conversion and to interrupt the microcomputer when data is available The
remaining two lines enable data onto the bus under microcomputer control. The bus is structured so that channel
selection, amplifier gain and AOC modes of operation are
controlled by simply outputting data to the bus. Input data
is in the form of two bytes: the first byte contains the most
significant eight bits with the second byte containing the
least significant four bits. Due to the high impedance nature
of the' Harris parts, other devices can be added to the bus
without exceeding bus load limitations.

Further enhancement ·of system performance can be achieved
with Direct Memory Access (OMA), FIFO's and other
circuits to alleviate the high speed data handling requirements
that a 50 kHz throughput OAS places on the microprocessor.

The complete OAS operates under software control for
maximum flexibility. A microcomputer internal software
timing loop establishes the necessary hardware timing signals.
The software flowchart in Figure 3 illustrates typical system
operation.

In conclusion, a single board microprocessor OAS can now be
easily implemented using newly available hybrid analog
interface devices. These devices not only support the requirements of microprocessor system" buses but provide
superior performance compared to discrete designs, while
using far less printed circuit (PC) board real estate. The
versatile H1-5900, H1-590 1 and H1-5712 devices offer ideal
solutions for these and other applications requiring high
performance, and cost-effective microprocessor interface
capability.

The system as depicted operates at a 50 kHz throughput
rate, while maintaining true 12-bit accuracy throughout the
temperature range. Similar high performance OAS's can be
implemented for a variety of applications Dnd offering
compatibility with most microcomputers.
Interfacing a OAS to a microprocessor system bus is similar
to interfacing any other peripheral device. Figure 4 illustrates
an interface for a typical m"icroprocessor bus and is applicable
to all popular microprocessors.

1--0--------

HI-59DD/HI-59D1

-------00•..,11--.-- HI-5712 - - -........,1
I
I
I
I
I
I
I

ANALOG
INPUT
SIGNALS

CHI =~=::j

13

CH2 =:::;::==1
CH3 ==*==1
CH4 ==*:::::j
CHS ==*=~
CHS ==*=:::::j
CH7 ==*=~

I
~::::::::J==:::;REFERENCE

I""

I

I

I
I

ANALOG

OUTPUT

HIGH

PERFORMANCE
ANALOG
TO
DIGITAL
CONVERTER

MULTIPLEXER

1

I
I
I
1

I

CH8==*=~

I
1

I
I

r

MICROPROCESSOR INTERFACE CONTROL LOGIC

I
I

T/H

MULTIPLEXER
CONTROL

AMPLIFIER
GAIN
CONTROL

TRACK
AND HOLD
CONTROL

Figure 1 Data Acquisition Subsystem

8-60

TRI-STATE

CONTROL

MODE

OUTPUT

CONTROL
(S LINES)

DATA BUS
(12 BITS)

HI~5712

CONDITIONED

HI-5900/HI-5901
ANALOG
SIGNAL
PROCESSOR

ANALOG
INPUT
SIGNAL

V'N

CONVERTER

2

BYTE

CONTROL

1

H'
LO

START CONVERT

r--

~

CONTROL
T/H PGAlMUX

~

ANALOG TO
DIGITAL

ANALOG SIGNAL

STATUS
MODE
CONTROL

aUTPUTS
1-8

OUTPUTS

9-12

~

~

I

3
INTERRUPT
PORT2

)

8 BITS

"
BUS

~

8 BITS

To OTHER
)

DE VICES

"

INTEL 8748
MICROCOMPUTER
PORT 1

8 BITS

)

"
END

Figure 2. Microcomputer with High Performance Data Acquisition Subsystem

CONDITIONED
ANALOG
INPUT
SIGNAL

H'
LO

..
..

HI-~~~~~:501 t-__A:..::..:N",Ac:L.::O..:Gc.:S"IG.::N:.:.:..:A.::L_-I V'N
SIGNAL
PROCESSOR

Figure 3 Software Flowchart

HI-5112
ANALOG TO
DIGITAL
CONVERTER

EI

I

SYSTEM
INTERRUPT
MICROPROCESSOR
SYSTEM ADDRESS
AND CONTROL

AD-

10 Lt,sec
ONESHOT

MICROPROCESSOR

BIDlREC-

SYSTEM BUS

_ _ _ _ _ _ _ _' \ TIONAL

v'

BUS
DRIVER

Figure 4.

Microprocessor DAS and Interface

8-61

~ H.AR.RIS

A DATA ACQUISITION
AND CONVERSION
SYSTEM WITH LESS THAN
±1 LSB OFFSET ERROR

APPllCA TION NOTE
530

The continuing pressure for higher resolution and
higher accuracy Data Acquisition Systems requires
smaller overall system offset errors.
Historically,
with eight-bit systems, offsets of up to 30 or 40
millivolts were acceptable, and the use of trimpots
or fixed resistors for adjustment was more than
adequate. State-of-the-art systems with 12 to 16bit resolution, however, require total system offset
over temperature to be less than 5 millivolts. Offset
voltages of this magnitude are difficult to achieve
using trimpots, and extremely difficult to stabilize
in uncontrolled thermal environments.
Ideally, a. DAS system should have less than ±1
LSB of offset error regardl~ss of the number of bits
incorporated in the system. This goal is extremely
difficult to achieve using linear design techniques.
Digital design techniques, however, can be used to
null offsets, typically to ±1/2 LSB over the complete
temperature operating 'range.
A'typical Data Acquisition System is illustrated
in Figure 1. System offset correction can be accomplished at any stage even though each stage contributes to the overall offset. The first step to offset
correction is to have the analog to digital converter

11

BY JOHN E. SULLIVAN

(A/D) calculate the digital code representing total
This
system offset when the input is grounded.
code, when converted back to analog form, inverted
and added to the input circuitry at a convenient
point, will null all offsets.
Figure 2 shows a simple digital offset correction
scheme. The additional digital to analog converter
(D/A) U3 and op amp U2 convert the calculated
digital offset code back to analog form. Op amp
U1 inverts this signal and adds it to the input differential amplifier.
The inverted signal is scaled
by resistors RA and R B such that a 1 LSB step of
the A/D is equal but opposite in sign to a 1 LSB
step of the D/A at TP1. This scaling can be calculated by Equation 1.
Equation 1

Where: VP1= Dynamic range of Linear A/D in volts
n1

= Number of Bits of A/D

VP2= Dynamic Range of Linear D/A in
volts
n2 = Number of Bits of D/A
RA = Feedback Resistor

INSTRUMENTATION

ANALOG TO DIGITAL

AMP .... F.ER

CONYERTER

RB = Input Resistor

CHA:NEl

'"

INSTRUMENTATION

SAMPLE AND HOLD

DIGITAL

AMPLIFIER

AMPLIFIER

CONVERTER

I-'Wr-4.-J>o,..

MULTIPLEXER

Figure 1 - Typical Data Acquisition Block Diagram

8-62

Figure 2 ...; Digital Error Correction Block Diagram

DATA

~~~PUT

Measu rement of the system offset is made with all
digital input bits to the D/A set at logic O. Further,
the D/A is configured for bipolar operation so that
a digital input bits to the D/A set at logic O. Further,
the D/A is configured for bipolar operation so that
a digital zero input results in a positive half full
scale output voltage at TP1. This ensures that the
AID need only measure positive offset voltages and
not negative voltages, allowing for systems operating
both in uinpolar and bipolar modes.

In operation, a spare input channel is grounded and
the input to the D/A is forced to digital zero. The
resulting compound offset, Voffset, is then equal
to the voltage at TP1 plus all component offsets.
The AID then calculates a digital code representing
Voffset which is latched into the D/A. Due to the
inversion and scaling of the Op Amp U2, this is
equivalent to subtracting Voffset from the half
full scale output of the D/A. Obviously the result
is the nulling of Voffset·

The size of the D/A converter is determined by the
maximum amount of offset that must be corrected
by the system:

The most critical parameter in this circuit is the ratio
of the resistors RA and R B. This ratio will determine the overall accuracy of the correction, and 1%
resistors are sufficiently accurate to null all offsets.
Normally for 12 and 14-bit systems, a 6-bit DAC
will correct all possible offsets.

Equation 2
D/ASize(Bits)

>

In(Maxoffset

2n1)

VP1
In(2)

CHI
CHZ

Z9

6 lOY FS

Z8

5 ZOY FS

HI-5900
OR
HI-5901

29 elK IN
13 CLK OUT
10 SERIAL OUT
33 CE

CHt5
CHt6

10

':'

HI-5712
ANALOG TO DIGITAL
CONVERTER

31 SC
32 sr

II

221918

CH

DIGITAL
CONTROL
INPUTS

DIGITAL CONTROL
INPUTS
START CONVERT

II

STATUS
AUTO

-..r

zSTR08E

81
8Z
83
84
85
88
87
88
89
810
811
81Z

I

MS8

LS8

Figure 3 - Auto-Zero Analog to Digital Converter

8-63

Various configurations can be employed to minimize
parts count. Fully automatic offset correction is
added to the HI-5900/HI-5712 DAS component
set using only four additional I.Co's as shown in
Figure 3. External digital logic or a microprocessor
selects a spare input channel which has been previously grounded.
Receipt of the Auto-Z strobe
initializes the auto-zero function by clearing the latch
to all zeroes, resulting in a D/A output of 32 LSB's of
positive offset.
The microprocessor then initiates
an analog to digital conversion sequence. The Conversion Complete status line of the AID causes the
latch to strobe and store the digital offset correction
term to the D/A converter. The analog correction
term is then injected into the zero adjust pin of
the AID converter. Care must be taken when injecting the correction term to this point on the AID
since the ratio of RA/RB is affected by the impedance of the summing junction.
Table 1 lists the accuracy of correction for various
full scale input ranges. The offset after correction
listed in the Table is the maximum observed offset
when 10 different 5900's and 5712's were tested
at all temperature ranges between -550 C, and

8-64

+1250C ambient. In no case did the offset after
correction ever exceed 1 LSB of the analog to digital
converter.
HI-57l2 INPUT
CONFIGURATION

o TO +10V
OTO+20V
-5VTO +5V
-10V TO +10V

RS

RA

OFFSET
AFTER CORRECTION

6Sm l47kn
S25n l47kn
5S0n l47kn

O.5mV
100m V
1.0mV

6Sm

2.0mV

l47kSl

Table 1 - Offset Correction Accuracy

Along with the straight forward benefit of greatly
improved offset performance, this correction technique eliminates the requirement for any offset adjustments, either initially or during the operating
life of the DAS. In practice, the auto-zero function
need only to be used after system power is applied
or after a significant change in ambient temperature.
Therefore, high performance microprocessor-based
DAS systems requiring maximum performance can
employ this technique to improve accuracy with
minimal impact on throughput rate.

mHA.RRIS
APPllCA TION NOTE
531
INTRODUCTION
A choice of three approaches is available when implementing a data conversion system: 1). "buildfrom-scratch", 2) buy sub-systems and configure
a system, or 3) purchase a pre-engineered system
Also, as a matter
which meets the requirements.
of economics, the users of sensor-based data acquisition systems make it common practice to ensure
a maximum number of elements are shared in the
system. An invaluable tool used in this process is
the analog switch or multiplexer. The purpose of
this article is to focus attention on those parts of the
system which require analog switches and to emphasize the importance of relative operating parameters.

BASIC SYSTEM CONFIGURATIONS
AID data conversion systems can be categorized into
two general groups: 1) low level signal conversion
(analog signals below 1 volt) and 2) high level signal
conversion (analog signals above 1 volt).
Within
these categories, four basic data conversion configurations are illustrated to point out the advantages
of using analog switches.

Conditioning the analog signals prior to multiplexing
(Figure 1A) is the most popular system arrangement
and is both efficient and capable of high performance
This configuration, which shares the level
signals. Figure 1 B represents a more austere approach
resulting in lower cost and decreased performance.
This type is useful in less demanding applications
To process
such as processing high level signals.
multichannel, single event information such as
wind tunnel or seismographic measurements the
arrangement shown in Figure lC is most likely to
be used. This configuration represents a more expensive, less efficient approach due to the decreased
number of shared elements.
Figure 1 D shows the
elimination of the analog multiplexer and sample

ANALOG SWITCH
APPLICATIONS IN AID
DATA CONVERSION
SYSTEMS
BY RICHARD WHITEHEAD

and hold circuits. By moving ·the multiplexing task
to the digital domain, slower and lower cost AID
converters can be used.

TYPES OF ANALOG SWITCHES
The most commonly used types of analog switches
found in today's data conversion systems are: reed
relay, JFET, and CMOS.
Reed relays offer low
ON and high OFF resistance and are capable of
handling very high voltages, but have slow speeds.
JFET switches have lower OFF leakage current and
are capable of very high speeds. CMOS switches,
which are the most popular and widely used in multiplexer applications, have low OFF leakage currents,
good speed, and stable ON resistance under varying
input signal conditions.

SELECTING THE PROPER CMOS
ANALOG SWITCH
The data conversion system error budget should be
. used to narrow the field of CMOS analog switches
suitable for the application. Primarily, the speed of
the switch must be consistent with the systems's
sample rate requirements without introducing unacceptable transfer error.
Significant dynamic
errors inherent to CMOS analog switches are OF F
channel leakage current and a settling time value
dictated by the device's ON resistance and its inherent capacitance.
Figure 2 shows the equivalent
of a CMOS analog switch giving all of the inherent
and distributed properties which may become the
source of unwanted system errors.
Other system restrictions may further narrow the
field of candidates suitable to performing the switching task. These restrictions could include, low power
budget, hostile environment, cost, alternate sourcing, and package density.
It's possible that all of

8-65

these restrictions could occur, and this situation
may influence the user to seek a compromise solution to his problem.
Fortunately, CMOS analog switches consume very
little power and only the most demanding power
budget would feel the strain of their power requirements. If the operating environment of the device
includes high voltage spikes, excessive noise pickup,
and/or power supply interruptions, the selection
should be narrowed to the internally protected analog
devices such as the HARRIS HI-506A/507A. These
multiplexers . come with guaranteed overvoltage
specifications which enhance the reliability of the
data conversion system. Usually, package density,
cost restrictions, and alternate source requirements
are simultaneously applied, and with present CMOS
analog switch availability from several vending
It
sources, these problems should be minimal.
should also be ensured that the CMOS analog switch
selected does not. exhibit any inherent latch-up tendencies.
The Harris dielectrically isolated CMOS
analog switches offer latch free operation.
To some 'users the proper CMOS analog switch
selection may become complicated leading to possible
alternate solutions. An example of such a situation
could be in high speed data conversion system where
the settling time constraint placed on the multiplexer
results in an unacceptable time penalty (Figure 3A).
Figure 3B shows an alternate and practical solution
to this problem. The two tiered multiplexing scheme
may reduce the errors caused by leakage currents
and settling time by an order of magnitude. Another
practical solution would be to select an analog signal
processor such as the HARRIS HI-5900/5901 shown
in Figures 4A and 4B. These devices facilitate user
application and reduce engineering time thereby
reducing overall cost.

HIGHLIGHTS
In A/D data conversion systems analog switches
are mainly used as multi-channel multiplexers
to increase system efficiency through shared
elements.
CMOS analog switches are the most widely used
in data conversion systems.
When selecting the proper CMOS analog switch,
look for low OFF leakage current, good settling
time, latch free operation, and stable ON resistance under varying analog signal input conditions.
If the environment is hostile, select from the
internally protected CMOS analog switches.
Where an alternate solution is required, attempt
to ensure your solution is the most practical
with respect to your error budget.

References:
Garrett, Patrick H.
Analog Systems for Microprocessors and Minicomputers.
Virginia: Reston
Publishing Company, Inc., 1978.
Kaufman, Milton and Seidman, Arthur H. Handbook
of Electronic Calculations. New York: McGrawHill Book Company, 1979.

OTHER USES FOR CMOS
ANALOG SWITCHES
Attention has been focused on the selection of CMOS
analog multiplexers used to increase efficiency of
data conversion systems through shared elements.
But the versatile CMOS switch is not limited to only
that function. Obviously they can be used in sample
and hold circuits, with important parameters being
switching speed, OFF leakage current, and charge
Analog switches such as the HAR R IS
transfer.
H 1-200/201 and H1-300 series may be used in sample
and hold circuits and also in auto-zeroing circuits
for integrating type data converters (Figure 5).
Figure 6 shows the CMOS analog switch used to
program the gain of an instrumentation amplifier.

8-66

Figure 1A - Multiplexed. Signal Conditioning
for Low Level Inputs

H.·

CDS

S06A

M
U
L
T

eQUT

RDS

•

P
L

lOUT

E
X

'A~:O)-+---.-----'
HA·
507A
ADDRESS

Figure 1B - Multiplexed. High Level Inputs

Figure 2 - Equivalent CMOS ANALOG SWITCH
DC Offset Error = RDS x 10
Setting Time Determined by RDS x CD

1

T'I

SIGNAL
CONDITIONING

508

SAMPLE

I+-

AND
HOLD

HA-5160

I

I
I
I
I

AN ALOG
'NPUTS

I

I
I

1.

f--.

i-

HA-5170

SIGNAL
CONDITIONING

I-t

I

r;;;:'

HA-2420

HA-5100

SAMPLE
AND
HOLD

~

PROGRAMMER

HI-5161518

M
U
L
T

MULTIPLE
ANALOG
INPUTS

•
P

OUT

MULTIPLEXER

L
E

x
E

R

"..
~

HI-5712

r-+

AID
CONVERTER

.~

OIGITAL
ADDRESS

---+---i

---+-+---+
ANALOG
OUTPUT

D1GI TAL

auTPUT

Figure 1C - Multiplexed. Sample I Hold Outputs

MULTIPLE
ANALOG
INPUTS

MULTIPLEXER
OUT

HI-516/518

Figure 3A - Cascaded Multiplexers: Output Leakage
Currents and Output Capacitance Increase Errors

II
HI-5161518

H.·

HA-50B4

SIGNAL
CONDITIONING

HI-5712

AID
CONVERTER

MULTIPLE
ANALOG
INPUTS

51.

0
E
M
U
L
T
L
E

X

HA-5D64

HI-5712

SIGNAL

AID

CONDITIONING

CONVERTER

E

\----+-t
EN

DIGITAL
OUTPUT

HI-5161518

R

"..

ANALOG

MSB-~-+-1~~-~---"

OIGITAL
AODRESS

P

INPUTS

MULTIPLEXER

L--'--y-"'---' OUT

•

ANALOG

HI·3oo

MULTIPLE
ANALOG
INPUTS

MULTIPLEXER

51.

Figure 10 - Multiplexed. Demultiplexer
AID Outputs

Figure 3B - Cascaded Multiplexers Two - Tiered
Method: Errors Reduced Through Shared Switch

8-67

CHAN
MUX
SELECT EN OUT

GAIN
SELECT

CHAN 1

TIH

OUT

Figure 5. This autozero integrating converter u_ six analog
switches - 8, through 86. Zero correction occurs when
83. 84 and 86 are "on". Integration occurs with 8, closed.
Integrate-reference takes place when 82 or 85 is "on".

SENse 0 - - - - - '

Figure 4A - HI-5900 Analog 8ighal Proce_r
GAIN
SELECT
CHAN
OUT
SELECT "EN A

INPUTS
TlH
OUT

OUT
•

0 -_ _- - '

Figure 4B '- HI-5901 Analog 8ignal Proce_r

•
8-68

Figure 6 - Programmable Gain
Instrumentation Amplifier

COMMON QUESTIONS
CONCERNING CMOS
ANALOG SWITCHES

mHARRIS
APPLICATION NOTE
532

BY CARL WOLFE

INTRODUCTION
The following information is a direct result of a
significant amount of time spent in response to
questions from users of HAR R IS analog switches.
Among the variety of questions are a few which
seem to be asked more frequently than others.
Over the next few pages, these questions are discussed with the hope that the answers will be helpful to the users and potential users of HARRIS
analog switches. Some questions are technical in
nature while others are simply questions on interpretation of the HARRIS Analog Data Book.

POWER SUPPl Y CONSIDERATIONS

to turn it on. A P-channel FET requires a negative
potential (gate to source voltage) to turn it on and
an N-channel F ET requires a positive potential (gate
to source). Contained in the physical structure of
the FETS are parasitic transitors which are shown in
Figure 1 as diodes from the source and drain to the
body potentials of the devices. These diodes or
parasitic junctions are normally reversed biased.
If those junctions are forward biased, a fault condition exists where the signal is passed through the
parasitic transitor. This is what occurs if the power
supplies go to ground. Depending on the polarity
of the input signal, either the N or P channel F ET
parasitics will be forward biased and the signal
passed th rough the switch.

The first two questions are similar questions and the
explanation will apply to both:
QUESTION#1:

If the power supplies are off,
will the switch be open? (present
a high impedance to the input
signal)

QUESTlON#2:

If the power supplies are off, can
an input signal be applied?

s

o

IN

•

OUT

Both of these questions refer to an overvoltage condition when the supplies are off and an input signal
is applied.
A common misunderstanding is that
the switch will be open and block the signal when
actually the opposite occurs.
What is meant by the power supplies being off? Does
it refer to the supplies being shorted to ground or
does it imply they are open circuited?
If the power supplies go to ground, the input signal
will pass through the switch and appear at the output.
The explanation for this can be seen in Figure 1,
which is a simplified CMOS switch cell. This switch
cell consists of two enhancement type field teffect
transistors, one N-channel and one P-ch1annel.
An enhancement ~ype of device is a FET which is
normally off without some potential (gate voltage)

Figure 1. Basic CMOS Transmission Gate

Having the signal pass through the switch may be acceptable in some applications, but most likely it is
not. An example would be user who was switching
various voltages (transducers) as shown in Figure 2.
If the supplies go to ground and these signals pass
through the switch, the input voltage sources could
easily be shorted.

8-69

I

+v
+V

r---I

VOUT

I R
VINo---~~~~,-,r-+---Q

----1--0 VOUT

I

I
I1..- _ _ _ _

-v
-v

Figure 2. Switching Multiple Inputs

Another situation occurs if the power supplies are
open circuited where the most positive and negative
input signals will provide power to the switch. In
this case, the signals being used for power will be
passed to the output, but the remaining switches
with inputs less than those used for supply will
operate properly.

INPUT OVERVOlTAGE PROTECTION
There is a possibilty the switch will be damaged if
exposed to excessive current levels during an overvoltage condition. A second overvoltage condition
is the case where the input signals exceed the existing
power supply levels.
Neither of these situations
are recommended and the following questions are
similar to those frequently asked.

•

QUESTION #3:

Can an input ,greater than the
supplies be applied?

QUESTION#4:

In my application, there is a
sibility that the switch will
power and the input signal
still be applied.
Is there a
to protect the switch if
situation occurs?

poslose
will
way
this

Referring to Figure 1 once again, if the input signal
exceeds the supply by an amount greater than the
breakdown voltage of the parasitic junction, the
normally reversed biased junction will come forward
biased.
These forward biased junctions will pass
the input signals to the output and possibly short
out the input voltage sources.
The most common form of protection circuit for
these types of overvoltage conditions is the resistordiode network at the input of the switch as shown in
Figure 3.
This circuit protects the device if the supplies go to
ground or if the input exceeds the supply. If either
of these situations occur the diodes will be forward
biased and current path to ground will exist. This
will protect the switch from excessive current levels.
The primary purpose of the resistor is to limit the
current through the diode.

8-70

Figure 3. Protection for Each Analog Input

Another advantage of using diode protection is that
it prevents the input signal from passing to the
output. This is a result of the input being clamped
to the breakdown voltage of the protection diodes.
If th is breakdown voltage is less tharl the threshold
voltage (turn on voltage) of the parasitic diodes,
the parasitic transistor will remain reverse biased and
the signal will not pass through the switch.
There are some disadvantages to the user with this
type of protection. One would be the econom ics
involved with using external protection for each
analog input.
This could present a cost problem
if a large number of channels were involved. Another concern would be the current limiting resistors
which adds to the on resistance of the switch contributing to the overall system error.
A further
possible source of error is current leakage in the
diodes. It is recommended that low leakage diodes,
such as schottkey diodes be used.
The protection circuit just discussed is not used to
protect the switch from latch up.
The HARRIS
switches are constructed using the dielectric isolation
process and the four layer SCR found in JI technology does not exist. This circuit is intended to
protect the device from high current levels which
result from the forward biasing of the parasitic transistors which are inherent in all F ET structures.
If for some reason the resistor-diode protection
circuit cannot be used there are other possibilities.
The following method may help to avoid the extra
cost of protecting each input. In this method,
since the supplies are open circuited, the most positive and most negative signal will power-up the chip
and any input with signals less than those being
used for power will operate properly.
However,
this method can only be used if the outputs are
not common and a user can afford to have at least
two signals pass to the output.

Trade-offs exist with single supply operation that
should be pointed out to the user. An example is
the HI-300 series of switches which has the capability of operating with a single +5 volt supply. The
performance of the switch will vary, however, as
the supply voltage varies. So, for the H 1-300 series,
as supply voltage decreases, the on resistance and the
switching times increase.
A 300 series switch with
a single +5 volt supply will have higher on resistance
and slower switching speeds than the same device
at ±15 volts or even a single +15 volt supply. This
represents a change in both DC and AC performance.
Even though the switch may now meet the users
power requirements at single supply, the question is
whether it will still meet the performance requirements.

+V

Dl

-v
Figure 4. Powering the Switch With the Input Signals

Another alternative does not involve protection circuitry, but instead takes advantage of CMOS technology. An example would be a user who has ±15V
supplies and needs to switch a +1BV signal as shown
in Figure 5. This appears to be an overvoltage condition since the input exceeds the supply. But rather
than protect the device, the user can shift the supplies
to +20V, -10V. Now the input signal is within the
supply level and the switch should work properly.
In certain applications the supply voltages can be adjusted in order to pass a larger range of input signals.

+20V

+15V

+18V

The fact that the on resistance varies with supply
voltage directly relates to the slower switching times,
since the higher on resistance will reduce the available
current needed to charge the internal capacitance of
the switch. Lower changing current relates directly
to slower switching times.

QUESTIONS ABOUT HARRIS SWITCHES
Many of the questions asked about switches could
apply to any CMOS switch manufacturer's products.
But some questions are unique to both the Harris
product line and data catalog.
The following are
examples of some of the more common questions
concerning the Harris Analog Data Catalog.

C=>+18V

-15V

The explanation for these variations can be found in
the FET devices composing the switch cell itself.
The variation in on resistance is due to the fact that
the channel impedance of F ET is dependent on the
gate - source bias. Since the gate voltage is determined by the supply voltage, it can be concluded
that the on resistance is a function of the supply
voltage.

-10V

II

QUESTION #7:
Figure 5. Varying the Supplies to Meet the VIN
V Supply Requirements

<

HI-5043

and

What is the difference between
the VL and VR pins on the
VREF pins on the HI-201 ?

power

The device pins mentioned above have their own
individual functions even though they are all associated wth the logic reference circuits of their respective designs.
For the HI-201, the VREF pin is
the terminal which establishes the logic threshold
Allevels for which the switch will change state.
though it is normally left open when driving from
+5V logic (DTL or TTL), it can be connected to a
higher supply in order to raise the switching threshold
levels when driving from CMOS Logic greater
than 5 volts.
The V REF pin enables the user to
change from TTL to CMOS Logic.

Usually engineers with critical power requirements
request single supply operation. An example would
be battery operated applications such as portable
In these cases the designer is limited
equipment.
to single supply, low supply or both.

The reference circuit of the H 1-50XX series
of switches is different from the H 1-201, which
accounts for the V R and V L pins. Even though the
VR terminal is brought out on the package, it is
recommended that this pin be grounded.
This
terminal establishes the ground for the internal ref-

SINGLE SUPPLY OPERATION
Single supply operation is a topic which is discussed
frequently and the following are examples of typical
questions.
QUESTION #5: Can the switch be operated at a
single power supply?
QUESTION #6: What is the minimum
supply possible?

I

8-71

erence circuit. The VL pin performs a similar function to the, VREF pin on the H 1-201. It is normally
connected to S volts for TTL logic but can be tied to
a higher supply for CMOS levels. This effectively
raises the switching thresholds to accomodate the
higher CMOS level.
The next question is easily the most frequently asked
'question about HARRIS HI-SOXX series of switthes.
QUESTION #8: Are the switch functions shown
on the data sheet a result of the
logic address being HIGH or LOW?
Actually, the answer to the question is printed at the
top of the data sheet page,depicting switch functions
"switch states are for a logic 1 input". Therefore,
the address is in the HIGH state for the switch
functions shown on that page.
Some other areas which are often questioned on the
data sheets are the maximum ratings and performance
between channels of the switches. The following
questions are typical:
QUESTION #9:

Will the switch operate at the
absolute maximum ratings?

The topic of absolute maximum ratings does
create some confusion.
Basically, the contents
of the Electrical characteristic table are the guaranteed parameters. The switch may operate with conditions other than those recommended, but are not
guaranteed parameters. Anything above absolute
maximum ratings may permanently damage the
device.
Problems sometime arise when a customer tests
some parts at conditions other than those which
If the parts work, the user may
are guaranteed.
go ahead and design around these conditions. But
there is a good possibility the next batch of switches
may not perform in the same manner. The user must
be aware that anything outside the guaranteed
limits is a user's risk and susceptable to variations
in manufacturing.

II

QUESTION #-10: What is the variation in "on" resistance between channels on the
switch?
There are two causes for these variation. One cause
is process variation which is due to variables in manufacturing. This can create variation between channels on the samE1 unit.
The second rea.son is lot
variation which can cause differences in performance
from unit to unit.
After all variations are taken
into account, a good "rule of thumb" is ±10% tolerance on 'typical parameter values, So if a device has
a typical on resistance of SO n , a user could expect
a ±Sn variatiqn.

8-72

A MONOLITHIC
SUBSCRIBER LINE
INTERFACE
CIRCUIT

m~RIS
APPLICATION NOTE

BY DAVID P. LAUDE

533
INTRODUCTION

The SLlC-LC provides DC loop current to the two
wire side to provide power to the end instrument
in t~e off-hook state and for loop monitoring purposes. Furthermore, this battery feed is balanced
so that the tip to ground impedance is the same as
the ring to ground impedance. To minimize power
dissipation, the SLlC-LC provides a maximum of
30mA loop current under worst case conditions
(VB- = -58 volts, RLoop = 200n). This is accomplished by a loop current limiting circuit within the
SLlC-LC device. The tip feed (TF) and the ring
feed (RF) outputs are low impedance and require
two external series 300n ±1% resistors (HC-5501)
or four external 150n±1% resistors (HC-5502) that
limit current to the secondary protection bridge
during overvoltage surges and present a 600n impe- .
dance to the loop. Both these resistors are to be
matched within 0.1% for specified longitudinal
balance.

This application note describes the HC-5501 and
HC-5502 SLiCs. These are monolithic low current
(LC) SLiCs for use in PABX or Central Office (CO)
applications which are fabricated with 80 volt Dielectric Isolation technology. The HC-5502 has
enhanced surge voltage capability, and requires
two extra external resistors as shown in the application circuit. The SLlC-LC provides battery feed
with power denial control and loop current limiting,
overvoltage protection (with some external devices),
ringing relay control, line supervision with off-hook,
ring trip and ground key detection and 2/4 wire
conversion. In addition, an uncommited op amp is
included in the SLlC-LC either for external connection of a balance network or for any other application.

FUNCTIONAL DESCRIPTION

If I Loop is less than 30mA, the RLoop = 140V .
Loop
-600n. In this case, voltage at RF = -44V for a
typical -48V operation. If RLoop is less than 733 n
and the supply voltage is -48V, then voltage at RF
will move towards ground to maintain the maximum
loop current at 30mA.

Shown in Fig. 1 is a typical line circuit configuration
using the SLlC-LC (HC-5501).
Balanced DC Battery Feed with Loop Current Limiting and Power Denial

BALANCE

RECEIVE ~----1r:-,;:::-rl

OP_AMpr{RAN~::I4::'---''--+-+'
~
HC~55Bl

HC-5502

t.::;::J

oUTPur lB

4
Cl

Cl-.5sIF

C2=.15pF

RING

t3-3"f
C4-.5pf
C5- SslF
C6=.llIf

HC-5501
HC-5502

RB2-RB4=JOlin I%MATCH

RBI =RB3=Dn .

RBI =RB2-RB3-RB4=ISBn
.1% MATCH

I

Cl=.lI1F
'''MATCHea C1

Rt-llWlc

fOR 6110n TERMINATION

R2=10DK ACROSS TIP AND
HJ-tooK
RINGTERMINAl$
21=0
ONLY
MATCH AI H2 R3

,%

Figure 1 - Typical Line Circuit Application with the Monolithic SLiC

8-73

SLlC-LC offers selective denial of power to subscriber loops. When a logic level 0 is applied to the
power denial (PD) Terminal, the following events
occur:
•

Metallic loop current is limited to a maximum
of 2mA.

•

The loop monitoring functions described later
are not necessarily valid.

•

It is not possible to apply ringing voltage to the
loop (across tip and ring).

Overvoltage Protection and Longitudinal Current
Rejection
The SLlC-LC device, in conjunction with an external
protection bridge, will withstand high voltage lightning surges and power line crosses.
High voltage surge conditions are as specified in
Table 1.
Table 1
PARAMETER
Longitudinal

Surge
Metallic Surge

T/GND,
R/GND

TEST CONOITION
10fJSRisei
1000/ls Fall

PER FOR MANCE
,MIN)

UNITS

± 1000 (Plastic)

VP"k
V Peak

± 1000 (Plastic)

V Peak
V Peak

±800 (Ceramic)

lOps Risel
1000ps Fall

± 800 (Ceramic)

101J5 Rise!
1O00!" Fall

± 800 (Ceramic)

V Peak
V Peak

11

Cycles

±1000 (Plastic)

60Hz Current

T/GND,
R/GND

700V rms

Limited to lOA rms

The SLlC-LC will withstand longitudinal currents up
to a maximum of 30mA rms without any performance degradation.

device. If tne subscriber goes off-hook during ringing, the RD output becomes inactive within 3 ring
voltage cycles after this event occurs.
Loop Monitoring (Switch Hook and Ground Key
Detection)
The SLlC-LC is able to monitor DC conditions
associated with the loop (i.e. tip and ring) in order
to determine end instrument status, transmit dial ing
pulses, and detect line fault conditions.
The SLlC-LC device provides the following low
active TTL compatible logic outputs which indicate
loop status:
• Switch Hook Detection (SHD) - This output
becomes active for loop currents exceeding 10mA
and becomes inactive for loop currents less than
5mA.
• Ground Key Detection (GKD) - This output
becomes active when the DC current flowing into
the ring lead (I RING) exceeds the current flowing
out of the tip lead HTIP) by more than l7.5mA,
and becomes inactive when this current difference
is less than 10mA. This function can be used for
monitoring calibrated ground key signals or
sustained unbalanced output shorts.
Hybrid Function
Conversion of bidirectional signals from 2 wire
telephone lines to separate receive and transmit
signals is accomplished with this SLlC-LC device.
Key features are:
• With extend resistors as specified, a balanced
DC and AC impedance of 600n appears across
tip and ring terminals.
•

Longitudinal balance (2 wire) in excess of 60dS.
A measure of degree of matching of tip to ground
and ring to ground impedance.

•

Longitudinal balance (4 wire) in excess of 50dB.
A measure of common mode rejection capability
of the device.

•

Low frequency longitudinal current suppression operational capability in presence of large common mode current at power line frequencies.

•

Low idle channel noise.

•

Level linearity over 60dB dynamic range.

Ring Injection and Ring Trip Detection with Hardware Interlock
Ring Injection is accomplished by a ring relay external to the SLlC-LC device. The SLlC-LC device has
an open collector relay d_river output (RD) capable
of sinking 62mA current for control of this ring relay.
Furthermore, the device has a low active ring command (RC) input (TTL compatible) which activates
the ring relay unless the subscriber is off hook (ILoop
> 10mA) or the SLlC-LC is in the power denial
state (PD) < O.S volts. This hardware interlock
feature, prevents inadvertent ringing of the phone in
the off-hook or power denial conditions.
In order to preserve the ring relay contacts and minimize RFI, the (RD) output is only permitted to
change state at or near the zero voltage crossings
of the ring voltage signal. A TTL compatible ring
sync (RS) input synchronized with ring voltage is
applied to implement this feature.
Ring trip detection is also performed by the SLlC-LC

8-74

• Overload level to accommodate maximum speech
power level.
• Good transhybrid loss (i.e. rejection of receive
signals leaking through to transmit side) capability
in conjunction with appropriate balancing network. As shown in Fig. 1, external passive components and internal uncommitted op amp make
up the balance network.

The impedance ZB can be made to balance any loop
impedance. Parameters of the balance impedance can
be calculated by knowing the loop termination ZL
and from the following equation: ZB = ~ ZL
2

modify the DC component of RF through summer 2
by adjustment of 11 through R. This limits the DC
transversal current to a maximum value of 30mA,
which also limits maximum power dissipation.
Longitudinal loop currents appear in voltage form at
the output of summer 4 (VLONG} which provides
input for the ring trip and ground key detection
circuit. Undesirable power line induced longitudinal
currents of up to 30mA rms are suppressed by an
external capacitor (C4} which may delay ring trip
detection by up to 3 ring cycles.

(K is a scale factor and this function allows the user
to scale the balance impedance components to
practical values. K = 100 is recommended for most
applications.}
Values of other components in balance network are:
C5 = 0.5JlF, C6 = 0.1JlF, C7 = 0.1JlF, R1 = R2 = K x
600 ohms, R3 = K x 300 ohms.

Power Denial is accomplished by setting 11 so that
the voltage at R F is -4 V. Power dissipation during
line shorts to ground is limited by the thermal Iimiting circuit, which supplies 12 to force the voltage at
RF positive. This limits die temperature by reduction
of the short circuit current.

• Minimum delay in transmitting signals through the
device.
• Capacitors C1 through C4 help provide filtering
and time delay functions.

SlIC-LC (HC-5501) PIN DESCRIPTIONS
(Refer to Fig. 3)

BLOCK DIAGRAM DESCRIPTION
In the SLlC-LC block diagram Fig. 2, the Receive
(RCV} signal and -4V are summed and buffered to
TF, they are negatively summed with VB- and
buffered to RF, providing an open circuit DC feed
of -4V and -44V for a VB- of -48V. Since the
RCV signal appears in opposite phase between
TF and RF, the 4/2 wire insertion loss is OdB if
ZL = RBF1 + RBF2.

Pin 1 - T
This is an analog input which is connected to the
TIP (more positive} side of the subscriber loop
through the ring relay. It is used in conjunction with
the ring lead to receive voice signals from the telephone and for loop monitoring purposes.

The transversal loop currents appear in voltage form
at the output of summer 3 (VTRAN} which is also
the transmit (Tx} output. The VTRAN signal is
sensed by the switch hook detection circuit which
signals the logic when transversal loop currents
exceed 7.5mA. In addition, the VTRAN signal is
monitored by the ITRAN limit circuit, which can

Pin 2 - R
This is an analog input which is connected to the
RING (more negative} side of the subscriber loop.
It is used in conjunction with the tip lead to receive
voice signals from the telephone and for loop monitoring purposes.
RCV

Cl

TFcr--------~_(

..-----------0

RBFl

TIP

o--+-.---:+{

C2

PO

LOGIC

ZL

RING o-+-f-I-f--WRBF2

R F Q - - - -....- C

C4

C3

RC

RS

RO

Figure 2 - SLIC-LC (HC·oS501) Block Diagram

8-75

Pin 10 - RF (Ring Feed)
TIP
RING
VB+

C1
C3
OG
RS
RO
TF
RF
VBBG

TX
AG

C4
RX
+IN
-IN
OUTPUT

C2

Rc
PO
.GKO
SHO

A low impedance analog output which is connected
to the ring lead through a 300 ohm ±1 % feed resistor.
It is used in conjunction with the tip feed lead to
provide loop current, feed voice signals to the telephone set, and sink longitudinal currents.
Pin 11 - VB- (Negative Voltage Source)
Most negative supply. VB- is typically -48 volts
with an operational range of -42 to -58 volts. This
supply is frequently referred to as "battery",
Pin 12 - BG (Battery Ground)

Figure 3 - Pin Configuration
Pin 3 - VB+ (Positive Voltage Source)

To be connected to zero potential. All loop current
and some quiescent current flows into this ground
terminal.

Most positive supply. VB+ is typically 12 volts
with an operational range of 10.8 to 13.2 volts.

Pin 13 - SHD (SWitCh

Pin 4 - C1 (Capacitor #1)

A low active TTL compatible logic output. This
output is enabled for loop currents exceeding 10mA
and disabled for loop current less than 5mA.

An optional external capacitor can be connected between this terminal and analog ground to further
suppress noise appearing on the +12V supply. Typical value of this capacitor is 0.5 J.I F, 5V. If this
pin is unused it should be left open.
Pin 5 - C3 (Capacitor #3)
An external capacitor is to be connected between
this terminal and analog ground. This capacitor is
required for proper operation of the loop current
limiting function, and for filtering the -48V supply.
Typical value of this capacitor is 0.3J.1F, 30V.
Pin 6 - DG (Digital Ground)
This is to be connected to zero potential and serves
as a reference for all digital inputs and outputs on
the sLle device.
Pin 7 - RS (Ring Synchronization Input)
This is a TTL compatible clock input. The clock
is arranged such that a positive transition occurs on
the negative going zero crossing of the ring voltage
source. This ensures that the ring relay is activated
and deactivated when the instantaneous ring voltage
is near zero. If this feature is not required, then
this pin may be left open or tied to +5V.
Pin 8 - lID

(ReiiiY DrlViir)

This a low active open collector logic output. When
enabled, the external ring relay is energized.

Pin 14 - GKD

HoOk Detection)

(GrOuiiii KeY Detection),

A low active TTL compatible logic output. This
output is enabled if the De current into the ring lead
exceeds the De current out of the tip lead by more
than 17.5mA, and disabled if this current difference
is less than 10mA.
Pin 15"':' PO (PoWer i5iii1i3i)
A low active TTL compatible logic input. When enabled the metallic loop current is limited to a maximum 2mA, the switch hook detect (SHD) and ground
key detect (GKD) are not necessarily valid, and the'
relay driver (RD) output is disabled.
Pin 16 - RC (Ring Command)
A low active TTL compatible logic input. When
enabled, the relay driver (RD) output goes low on
the next rising edge of the ring sync (RS) input,
as long as the sLle is not in the power denial state
(PD = 0) or the subscriber is not already off-hook
(SHD =0).
. Pin 17 - C2 (Capacitor =#2)
An external capacitor can be connected between
this terminal and digital ground. This capacitor prevents false ground key indications from occurring
during ring trip detection and may be omitted if
GKD is not used. Typical value of this capacitor
is 0.15jlF, 10V.
Pin 18 - OUTPUT

Pin 9 - TF (Tip Feed)
The analog output of the spare operational amplifier.
A low impedance analog output which is connected
to the tip lead through a 300 ohm ±1% feed resistor.
It .is used in conjunction with the ring feed lead to
provide loop current, feed volce signals to 'the telephone set, and sink longitudinal currents.

8-76

Pin 19 - -IN
The inverting analog input of the spare operational
amplifier.

Pin 20 -+IN
The non inverting analog input of the spare operational amplifier.
Pin 21 - Rx (Receive Input, Four wire side)
A high impedance (90kohm) analog input which is
internally biased. Capacitive coupling to this input is
required. AC signals appearing at this input differentially drive the tip feed and ring feed terminals,
which in turn drive tip and ring through the 300 ohm
feed resistors.
)Pin 22 - C4 (Capacitor .:#4)
An external capacitor is to be connected between
this terminal and analog ground. This capacitor
prevents false ground key indications from occurring
when large longitudinal currents are induced into the
subscriber loop form near proximity power lines and
other noise sources. Typical value of this capacitor
is 0.5j.!F, 20V).
Pin 23 - AG (Analog Ground)
To be connected to zero potential and serves as a
reference for the transmit output (Tx) and receive
input (Rx) terminals.
.
Pin 24 - Tx (Transmit Output, Four wire side)
This is a low impedance (10r! m\lx) analog output
which represents the differential voltage across tip
and ring. Transhybrid balancing must be performed
(using the spare op amp
the SLiC device) beyond
this output to completely' implement two to four
wire conversion. This output is unbalanced and
referenced to analog ground. Since the DC level of
this output varies with ,loop current, capacitive
coupling to the next stage is essential.

,w

II

8-77

ADDITIONAL
INFORMATION
ON THE HI-300
SERIES SWITCH

m~RIS
APPLICATION NOTE

BY CARL WOLFE

534
INTRODUCTION

shown in Figure 1 will help illustrate the need for
low on resistance and leakage current in high accu racy systems.

The introduction of the HI-300 series of CMOS
analog switches is the latest addition to the HARRIS
switch family and gives the designer a viable second
source to the Siliconix DG 300 series analog switch.

+15V

14
HI-301
01 2
4 81

This family of monolithic, dielectrically isolated,
CMOS analog switches consists of twelve products,
the HI-300 thru HI-307 and the HI-381 thru HI-390
are designed for TTL level compatibility (logic
"0" = .8V, logic "1" = 4.0V). The HI-304 thru
HI-307 are CMOS compatible (logic "0" = 3.5V,
logic "1" =llV).
The H1-300 series features low and nearly constant
on resistance over analog signal range, low leakage
and minimal power dissipation.

RF1 = 1K

X1

02 13 RF2 = 10K X10

RI =1K

6
VIN
VOUT

IMPROVED PERFORMANCE

II

An understanding of what a designer would consider
important in an analog switch is useful in order
to illustrate the advantage of the H1-300 series.
Although any parameter could be considered important for a particular application, there are certain
parameters considered to be most critical for the
majority of applications.
These parameters are:
"on" Resistance (Ron)
leakage current (lSOFF, IDOFF, IDON)
switching speed (ton, toff)
power supply current (1+, 1-)

Figure 1 - Inverting Programmable Gain Amplifier
Ideally, the voltage gain of this inverting amplifier
would be, AV= -(RF/RI). But when using a switch
to program the gain, its characteristics must be taken
into account and the amplifier gain equation must
be modified to AV:= - (RF +RON/RI). The higher
the on resistance of the switch, the greater the gain
error. Variations in the on resistance of the switch
will also effect the gain error.
LEAKAGE CURRENT

These parameters are important because the majority
of designs require either high accuracy, speed, or low
power dissipation.
ON RESISTANCE
rn high accuracy systems, such as data acquisition
systems, the designer would be concerned with minimizing errors caused by "on" resistance and leakage
currents. An inverting programmable gain amplifier

8-78

Another source of error occurs in the SWitch "off"
state, where leakage current causes offset voltage
errors. In Figure 1 , leakage current flowing through
the feedback resistor creates an output voltage
error equivalent to the expression, Vo= RF X IDOFF.
SWITCHING SPEED
A designer concerned with switching times would·

obviously be sensitive to the ton and toff specifications.
A low value of "on" resistance is also important, since this resistance increases the RC time
constants and can slow the circuits overall performance.

Hr-t--;-t-~

IN

GNDo--+-+--....----'

POWER SUPPLY REQUIREMENTS
Figure 2 - Partial Schematic

The last critical parameter would be power consumption.
There are certain applications where power
supply currents are the primary concern of the
designer.
Examples would be portable or battery
operated equipment.
The majority of switch applications require critical
performance in one or more of the areas just discussed. The H1-300 series offers improved performance in each of these areas. The following tables
compare the HI-300 series with existing HARRIS
switches.
Table 1 contains maximum specifications for T = 125 0C and Table 2 consists of typical
values at T = 25 0 C.

v+

o

SWITCH CELL

-v

+1250C Maximum Specifications
SWITCH
TYPE
HI-200
HI-5040
HI-300

Figure 3 - Schematic
tON tOFF
500ns
1000ns
300ns

500ns
500ns
250ns

Table 1 - Switch Comparisons at T=1250C
+25 0C Typical Specifications
SWITCH
TYPE
HI-200
HI-5040
HI-300

tON tOFF
240n.
370n.
210n.

330n.
28005
160ns

Table 2 - Switch Comparisons at T=250C
From these tables it should be clear that the HI-300
series offers improved performance to the designer.

INSIDE THE HI-300
Figure 2 shows the schematic of the digital input and
driver stages of the H1-300. The purpose of this
stage is to take the logic level signals and condition
them to drive the gates of the FET switch cells.
The H1-300 series has a digital input protection circuit consisting of a 200n series resistor and clamping
diodes, 01 and 02, to the supplies.
These diodes will quickly discharge any static charge
which might appear at the digital inputs.
The F. E. T. Devices Nl thru N5 and Pl thru P5 form
the input buffer and level shifter which establishes
the proper voltages to drive the switch cell. N6, N~
P6, and P7 form the output buffers which isolate
the level shifter from the capacitive load of the switch
cell.

The switch cell shown in Figure 3 is based on the
FET devices Nl and Pl. The remaining devices, N2
thru P5 serve various functions, such as reducing
leakage current, minimizing on resistance variations
and minimizing charge injection.

ADDITIONAL PERFORMANCE
CHARACTERISTICS
(AI SINGLE SUPPLY OPERATION
The H1-300 series has the capability of single supply
operation. These switches can operate to a minimum
supply of +5 volts, although designers must be aware
of the trade off which exists at these levels. The
trade off is the performance of the switch will vary
as the supply level varies. Examples of these performance variations are increased on resistance and
slower switching times. So, a HI-300 series switch
with a single five volt supply will have higher on
resistance and slower switching speeds then the same
device at ±15 volts or even a single +15 volt supply.
The explanation for these variations can be found in
the F .E.T. devices composing the switch cell itself.
The variation in on resistance is due to the fact that
the channel impedance of the F ET is dependent on
the gate-source bias. Since the gate voltage is determined by the supply voltage, it can be concluded that
the on resistance is a function of the supply voltage.
The fact that the on resistance varies with supply
voltage directly relates to the slower switching times.
The higher resistance reduces the available current

8-79

needed to charge the internal capacitances of the
switch.
Lower charging current directly relates
to the slower switching times.
The explanations, just given, along with the following
typical curves of the HI-300 single supply operation,
should aid the designer in applying the H 1-300
series in single supply applications.

RDSION) VS. ANALOG AND POSITIVE
SUPPLY VOLTAGE WITH V- = OV

~

300

9

INPUT SWITCHING THRESHOLD
VS. POSITIVE SUPPLY VOLTAGE
HI-300 THRU HI-307

:i

t:i
Hi

9.

v-=ov
TA

100

a:

i.-' ~

=- 250C

V+=5V

V

z

:g

~

20

a:

'I
Z

V-= OV
TA=250 C

~

oj

w

u

.-

-

v+ = 10V

-

V+r'5V

6

8

10

12

14

16

VA - ANALOG VOLTAGE (VOL lS)

HI-JOO thr" HI-JOJ

o
V+

5
10
15
POSITIVE SUPPLY VOLTAGE (VOLTS)

INPUT SWITCHING THRESHOLD
VS. POSITIVE SUPPLY VOLTAGE
HI-3S1 THRU HI-390
7r-------r-------~----__.

V-=OV
TA=25 0 C

~ ~
:t":

~~

~ §! ~
!:)9i5
~

F·

,w

4

f-------+------+------j

3

t--------t----==:l:;;;;;;;;;;_ml!i

~~

> ....

• 1------+-------'+-:-----1
V+

POSITIVE SUPPLY VOLTAGE (VOLTS)

SWITCHING TIME VS. V+ POSITIVE SUPPL Y VOLTAGE
4
V-"'DV

B) CHARGE INJECTION
The charge injection of a switch is a critical parameter
for certain applications, such as small signal switching
or sample and hold circuits.
For the case of small signal switching, unwanted
switching spikes result from this transferred charge
causing system errors.
These spikes are created
when the transitions of the gate voltage are capacitively coupled to the output through the gate to
source and gate to drain capacitances, as shown in
Figure 4. The magnitude of these switching spikes
will depend on the values of the load and source
impedances, the value of thl1 gate voltage and the
size of the internal capacitances of the switch •
For the sample and hold circuit, shown in Figure 5,
a common problem is sample to hold offset error.
It is caused by the same mechanisms discussed
for the small signal application, but in this case the
c~arge is transferred to the hold capacitor and an
offset voltage is created. The voltage is determined
by the following relationship.
V = Q/CH.

TA = 250C

~w

3

";:z
"

;:

::

2

~

...I

g
z

1

~\tON

t~ r--

\l

I~~
CGS·~~CGD

-=

~

+5V

+15V
+10V
V+ - POSITIVE SUPPLY (VOLTS)

8-80

Figure 4 - Charge Transfer

those junctions are forward biased, a fault condition
exists where the signal is passed through the parasitic
transistor. This is what occurs if the power supplies
go to ground.
Depending on the polarity of the
input signal, either the N or P channel FET parasitics
will be forward biased and the signal passed through
the switch.

Figure 5 - Sample and Hold
Charge injection can create problems in the type of
applications just described. A typical curve ot"'the
HI-300 series charge injection performance is shown
in Figure 6 as an aid to designing in these type of
circuits.

N
uS 0

"r
z
!2.0

~

~ 30

""'"

w

"~20
~

10

+15

-10

-5

0

IN

.......

+5

s

D

OUT

RIN-on
CL'" 10,OOOpf

+10

+15

VS - ANALOG INPUT VOLTAGE - V

Figure 6 - Charge Injection vs. Input Voltage

APPLICA TION HINTS

r

G2

Figure 7 - Basic CMOS Transmission Gate
A \: POWER SUPPLY CONSIDERATIONS,
The H1-300 series analog inputs do not feature overvoltage protection.
External protection circuitry
would be necessary if the switches were subjected
to possibly destructive situations.
An example could be an overvoltage condition where
the power supplies to the switch go down while an
analog input signal is still present.
A common
misunderstanding is that the switch will be open
and block the input signal, when actually the opposite occurs.
If the power supplies go to ground, the input signal
will pass through the switch and appear at the output.
The explanation for this can be seen in Figure 7,
which is a simplified CMOS switch cell. This switch
cell consists of two enhancement type field effect
transistors, one N-channel and one P-channel. An
enhancement type of device is a FET which is normally off without some potential (gate voltage) to
turn it on.
A P-channel FET requires a negative
potential (gate to source voltage) to turn it on an
N-channel FET requires a positive potential (gate to
source). Contained in the physical structure of the
FETS are parasitic transistors which are shown in
Figure 7 as diodes from the source and drain to the
body potentials of the devices.
These diodes or
parasitic junctions are normally reversed biased. If

Another situation occurs if the power supplies are
open circuited, the most positive and negative input
signals will provide power to the switch. In this
case, the signals being used for power will be passed
to the output, but the remaining switches with
input signals less than those used for supply will
operate properly.
A second overvoltage condition is the case where
the input signals exceed the existing power supply
levels. Referring to Figure 7, if the input signal exceeds the supply by an amount greater than the
breakdown voltage of the parasitic junction, the normally reversed biased junction will become forward
biased. These forward biased junctions will pass the
input signals to the output and possibly short out
the input voltage sources.

II

The most common form of protection circuit for
these types of overvoltage conditions is the resistordiode network at the input of the switch as shown in
Figure 8. This circuit protects the device if the supplies go to ground or if the input exceeds the supply.
If either of these situations occur, the diodes will
be forward biased and a current path to ground will
exist.
This protects the switch from excessive
current levels. The primary purpose of the resistor
is to limit the current through the diodes.

8-81

v+

R

.L---.4I---1

o

.I

O.0254S'1

O.02S8n
O.034sn
O.0488n

a. TWO POLE SECTION

a,07,an
D.1tOn
D.17tH

FIGURE 7. Impedance of Electrical Connections, +20'C

As an example, suppose the ADC in Fig. 1 has
12-bit'resolution, and the system accuracy is to be
± V2 LSB (± 1.2mV). The interface logic might draw
100 mA from the + 5V supply. Flowing through six in·
ches of #24 wire, this current produces a drop of
1.28mV; more than the entire error budget. Obviously,
this digital current must not be routed through any
portion of the analog ground return network.

FILTERS
The presampling or anti·aliasing filters shown in
Fig. 1 are normally required with high-level signals of
significant bandwidth, especially if the signal is to be
reconstructed by a digital-to·analog converter after
processing. If low level signals require a passive filter,
the differential configuration of Fig. 8 preserves some
degree of Impedance balance onthe line.

FIGURE 8. A Passive, Two Pole, Low Pass,
Differential Input Filter

A low-pass Butterworth response is best for the
channel bandlimiting filter in most data acquisition
systems. The Butterworth filter output decreases
monotonically with frequency, though this attenuation is very slight within the passband. Other
filter types produce ripple in the passband, whose
amplitude degrades accuracy unless expensive, high
tolerance components are used.
Butterworth is not the most linear phase
reSponse, and if Signal group delay is critical an ellip·

I

I
b. THREE POLE SECTION

FIGURE 9. Butterworth Low·Pass Filters

PROGRAMMABLE GAIN AMPLIFIER
(PGA)
Unless the ratio of highest to lowest signals an·
ticipated on any channel is s 2, some form of
programmable gain amplification is desirable between the multiplexer and A·D converter. Without this
variable gain block, the MSB's are idled one after
another as input level decre;:lses. Although the
resolution of an n-bit converter remains a constant
FS/2~ by definition, resolution referred to the input
level is decreasing (FS = Full Scale).
Considering resolution as referred to the input
level, a 12·bit converter digitizes an input of .06FS to
only 8 bits. The full 12·bit resolution applies only for
VIN"" FS/2. Therefore to fully utilize the converter, gain
should be added as necessary before each conversion, to meet the condition FS/2 == VIN::sFS. Then the
amount of gain intropuced by the PGA is noted by the
computer to keep track of the actual input value.
Three other services are performed by the PGA:
1. Buffering: Prevents a loading effect due to the
multiplexer's ON resistance.
2. Differential to Single·Ended Conversion:
Necessary.for the majority of Track (or Sample) IHolds
and A-D converters.
. 3. Common ,Mode Rejection (CMR). When connected to the output of a differential multiplexer, the
PGA's differential input rejects the common mode
voltage accumulated by a signal transmission cable.
Fig. 10 shows a subtractor or "pseudo-differential"
PGA suitable for wideband signals with low common
mode content. In this circuit, CMR is limited by
precision of the "K" ratio and variations in the channel source impedance.

II

I

8-87

K*R

DIFF MUX
R

R

* 1< VALUE MAY BE SWITCHED FOR
PROGRAMMABLE GAIN.

FIGURE 10. Subtractor or Pseudo·Differential PGA

Fig. 11 is the full differential PGA, necessary for
low-level, high common mode signals. This version offers the highest gain accuracy and for hf(jh gain, the
best CMR.
OIFF MUX

.OR

• VARY K TO CHANGE THE GAIN.

FIGURE'11. Full Differential PGA

The PGA normally precedes the Track/Hold; since
the PGA would amplify any error introduced by that
device. This order must be reversed to implement an
auto-range capability, because the Signal voltage
must be held at the PGA input for the duration of an
auto-range subroutine by the computer. Such an
algorithm cons.ists of:
• Set PGA gain
• Trigger a conversion
• Note RESULT
• Iterate until (FS/2 ::; RESULT .$ FS)

SAMPLING RATE
Throughput rate for a DAS may be defined as the
maximum number of digital samples per second that
it can produce without exceeding its specified limit
for accuracy. The system may run at a lower speed to
avoid generating redundant and u,§eless data; but if a
waveform of significant bandwiath is to be reconstructed from the digital samples, then "the higher the
better" is generally the rule for sampling rate.
The required rate is often higher than one would
suppose. For example, using the criteria of data bandwidth alone, a very low sample rate is required for
the slowly changing voltage outputs from a solar
panel. Once per minute for each channel might be
enough. With 60 channels though, the rate required is
once per second. In addition, one might require a
maximum of one second for notice of failure on any
channel, boosting the required sample rate to 60
samples per second. In this manner low bandwidth
channels may require a high speed DAS, according to
the relationship:

8-88

System Sample Rate = (Highest Channel Rate)
X (Number of Channels)
Also, a very high sample rate is required to
preserve the high frequency content of a transient
event on a single channel. The most commonly encountered requirement though, is a multichannel DAS
(see. Fig. 1) with a modest bandwidth on each channel.
For' example, each data source. might be an accelerometer with an output ranging through several
hundred Hertz.
Notice that the low and high bandwidth signals
just described cannot be handled efficiently with the
same system. A sample rate high enough for the
highest bandwidth channel will oversample the lower
bandwidth channels, generating unnecessary data.
High and low bandwidth data are best handled by
separate multiplexer/converter systems.
.
Presampling filters are essential to ensure accuracy in the sequence of digital samples representing a given channel. Since the multiplexer is a sampler (as is the Sample/Hold and A-D Converter) this
means a separate filter dedicated to each channel
vpreceding the multiplexer. A single filter fallowing the
multiplexer would do the job, but its modest response
time would form a bottleneck restricting the sample
rate. Guidelines are needed then, to relate a given
level of accuracy to data bandwidth, filter cutoff
frequency, and number of filter poles.
As mentioned earler, a filter l.imits the error due
to alias frequencies by restricting the bandwidth of
both signal and noise. Either acting alone or in concert may cause error, since alias frequencies arise in
several ways:
1. Overlap of the signal spectrum and the lower
sideband associated with the sampling frequency f s.
2. Overlap of the upper and lower sidebands
associated with any two consecutive;l:1armonics of fs.
3. Overlap of any sideband with wideband noise
from the data channel.
A band-reject filter would control case 1, but a
low-pass type is needed to handle cases 2 and 3 as
well. Again, the Butterworth response is preferred in
most applications, but it does offer increasing phase
shift and gain error for frequencies approaching the
cutoff (-3d B) frequency. This cutoff should be set no
higher than necessary for acceptable gain error in
the highest signal components. A higher cutoff will
only include unnecessary noise bandwidth.
Finally, for a given accuracy specification such
as ± Yo LSB, a tradeoff may be made between the
sample rate and number of poles. These poles usually
come from the filter, but the number may include any
pole(s) inherent in the transducer, provided they occur
at an acceptable location relative to the cutoff
frequency.
Fig. 12 shows aliasing error due to the Signal
spectrum alone vs sampling rate for different numbers of poles. The horizontal axis is normalized to
Sampling Frequency/Cutoff Frequency. Notice that a
2-pole filter requires a sampling frequency 30 times
the filter cutoff frequency, just to obtain 1 % accuracy. For ± Yo LSB error in a 12-bit system
(± .01 %), a 5-pole filter requires sampling at 11 times
the cutoff frequency. Remember, Fig. 12 applies only
to the signal spectrum. Noise will cause some additional aliasing error.
Clearly, Nyquist's Sampling Theorem is not a
practical guide for sampling rate In real applications.
Actual (as opposed to hypothetical) filters cannot
bandlimit a signal sufficiently to permit the
theoretical minimum of two samples per cycle of
highest Signal frequency.

." .........J......J...J..JL.J~,~,_"'-'-'-.u....;~:--.J.....L..J..J....O.'-';;',
NORMALIZED SAMPLING RATE
(SAMPLING FREQUENCY . FILTER CUTOFF FREaUENCYI

FIGURE 12. Effect of Filter Poles on Aliasing Error

COMPUTER INTERFACE
The typical DAS we have described (Fig. 1)
requires several control signals:
• Mulitplexer Channel Address
• PGA Gain Address
• Track/Hold Control
• A-D Converter'
- Start Convert
- MSB Invert
- Short cycle
- Unipolar/Bipolar
-. Output Byte Enable
- Conversion Interrupt etc.
This control can be provided directly by the
computer, but some portion of these signals is
usually supplied by an intermediate block of control
logic. For monitoring predictable channel data, the
DAS can repeatedly scan through its channels, trigger
the converter, and notify the computer when each
data sample is ready. This independent operation can
be accomplished by a clock and counter arrangement
to supply channel and gain addresses, plus a dual

"one shot" multivibrator (74123) to gate the Start Convert and Track/Hold functions.
To handle a sudden change in data level or other
unexpected event, the computer must be able to rand9m access any channel 9r PGA gain. Provision is
made to write this information to the DAS via the
computer's data or address bus, using appropriate
address decoders and latches.
When processing higher bClndwidth signals, one
error source to be minimized is the Track/Hold's aperture delay uncertainty, or jitter. The logic which
generates the T/H control signal needs close attention, since jitter in this waveform adds to that
specified for the device itself.
Finally, the DAS output consists of a serial
stream of parallel digital words from the converter,
synchronized with the converter's status signal indicating when the data is valid_ Techniques for
passing this data to the computer include direct
memory access (DMA), memory mapping, and mapping via a dedicated I/O port, all with or without an external interrupt of the processor.
DMA is most efficient for the high'speed transfer
of large volumes of data. This can proceed by
program request, resulting in the movement of a block
of data to a designated -sequence of memory
locations, at a speed limited only by the memory
cycle time_ As an alternative, hardware can be configured to allow transfer of a data word during every
non-memory machine cycle. This allows an almost
continuous output of data from the DAS. The transfers are asynchronous and unsolicited by the
program with only a slight increase in software
execution time.
For less demanding data rates the choice is
between an I/O or memory mapped interface. The former is best for small systems. For example, the 8085
microprocessor can control up to eight I/O devices
without external address decoding. Addition of
decoders expands the field from 8 to 256 peripherals.
There is a range of applications for which the
choice of I/O or memory mapping is not clear, but
memory mapping becomes attractive with increasing
system complexity_ The memory reference instructions available with this approach simplify programming and speed execution. A further Increase in
throtlghput is obtained by use of the processor's interrupt system, allowing the main program to proceed
while an analog-to-digital conversion is in progress.
Memory mapping plus interrupt is very effective;
however, the software overhead associated with service of an interrupt-driven I/O interface results in a
diminishing advantage as the required throughput
rate increases. Again, DMA offers the advantage for
high data rates_

BIBLIOGRAPHY
General

1. "Analog Data Book", Harris Corp., 1980
2. "Data Acquisition Handbook", Intersil. 1980
3. "Cata Conversion Systems Digest", Analogic. 1978
4. "Integrated Circuit Converters. Data Acquisition Systems and Analog Signal Conditioning Components".
Analog Devices, Inc. 1979
5. "Linear Applications Handbook," National Semiconductor, 1978
Grounds, Shielding and Power Distribution
6. "An IC Amplifier User's Guide to Decoupling, Grounding, and Making Things Go Right for a Change",
Analog Devices Application Note, 1977

7. Elimination of Noise in Low-Level Circuits", Gould Application Note.
8. "Isolation and Instrumentation Amplifiers Designer's Guide", Analog Devices, 1978
Filters
9. "Electronic Filter Design Handbook", Arthur B. Williams, McGraw-Hili, 1981
10. "Need an Active Filter? Try These Design Aids", EON, Nov. 5, 1978

8-89

~ HA.R.RIS

DELTA MODULATION
FOR VOICE
TRANSMISSION

APPLICATION NOTE
607

BY DON JONES

INTRODUCTION TO DElTAMOD
Delta modulation has evolved into a simple, efficient
method of digitizing voice for secure, reliable communications and for voice I/O in data processing.
To illustrate basic principles. a very simple delta
modulator and demodulator are illustrated in Figure
1. The modulator is a sampled data system employing a negative feedback loop. A comparator senses
whether or .not the instantaneous level of the analog
voice input is greater or less than the feedback signal.
The comparator output is clocked by a flip-flop to
form a continuous NRZ digital data stream. This
digital data is also integrated and fed back to the
comparator. The feedback system is such that the
integrator ramps up and down to produce a rough
approximation of the input waveform. An identical
integrator in the demodulator produces the same
waveform. which when filtered, reproduc~s the
voice.
We can see that the digital data O's and l's are commands to the integrators to "go up" or "go down"
respectively. Another way of looking at it is that the
digital data stream also has analog significance;
it approximates the differential of the voice, since
analog integration of the data reproduces the voice.

II

Note that the integrator output never stands still;
it always travels either up or down by a fixed amount
in any clock period. Because of its fixed integrator
output slope, the simple delta modulator is less than
ideal for encoding human voice which may have a
wide dynamic amplitude range.
The integrator cannot track large, high frequency
signals with its fixed slope. Fortunately, human
speech has statistically smaller amplitudes at higher
frequencies, and an integrator time constant of about
1 millisecond will satisfactorily reproduce voice in
a 3kHz bandwidth.
A more serious limitation is that voice amplitude
changes which are less than the heighth of the integrator ramp during one clock period cannot be
resolved. So dynamic range is proportional to clock
frequency, and satisfactory range cannot be obtai ned
at desirable low clock rates.

8-90

A means of effectively increasing dynamic range is
called "companding" (compressing-expanding); where
at the modulator, small signals are given higher
relative gain, and an inverse characteristic is produced
at the demodulator.
The CVSD: A popular effective scheme for companded delta modulation is known as CVSD (continuously variable slope deltamod) shown in Figure 2.
Additional digital logic, a second integrator, and an
analog multiplier are added to the simple modulator.
Under small input signal conditions, the second
integrator (known as the syllabic filter) has no
input. and circuit function is identical to the simple
modulator, except that the multiplier is biased to
output quite small ramp amplitudes giving good
resolution to the small signals.
A larger signal input is characterized by consecutive
strings of l's or O's in the data as the integrator
attempts to track the input. The logic input to the
syllabic filter actuates whenever 3 or more consecutive O's or l's are present in the data. When this
happens, the syllabic filter output starts to build
uP. increasing the multiplier gain, passing larger
amplitude ramps to the comparator, enabling the
system to track the larger signal. Up to a limit,
the more consecutive l's or O's generated. the larger
the ramp amplitude. Since the larger signals increase
the negative feedback of the modulator and the
forward gain of the demodulator, companding takes
place. By listening tests, the syllabic filter time
constant of 4 to 10 milliseconds is generally considered optimum.
An outstanding characteristic of CVSD is its ability,
with fairly simple circuitry, to transmit intelligible
voice at relatively low data rates. Companded PCM,
for telephone quality transmission, requires about
64K bits/sec data rate per channel. CVSD produces
equal quality at 32K bits/sec. (However, at this
rate it does not handle tone signals or phase encoded
modern transmissions as well.)
CVSD is useful at even lower data rates. At 16K
bits/sec the reconstructed voice is remarkably natural,
but has a slightly "Fuzzy Edge". At 9.6K bits/sec
intelligibility is still excellent, although the sound

is reminiscent of a damaged loudspeaker. Of course,
very sophisticated speech compression techniques
have been used to transmit speech at even lower data

II

rates; but CVSD is an excellent compromise between
circuit simplicity and bandwidth economy.

B,O'

ClOCK~

II

THE DIGITAL CVSD

"TVT
Voo

Delta modulated data is in a form which can be
digitally filtered with fairly simple circuitry. A
compatible CVSD can be made using digital integrators and multipliers driving a digital-to-analog converter. The block diagram of the Harris HC-55516/
55532 monolithic CVSD is shown in Figure 3.

R.
DIGITAL

'"

DIGITAL

OU,
VOICE

'N

VOICEI
SIOETONE

OU,

The CMOS digital circuit functions of Figure 3
closely parallel the equivalent analog function in
Figure 2. The filters are single pole recursive types
using shift registers with feedback. A digital multiplier feeds a 10 bit R-2R DAC which reconstructs
the voice waveform. The DAC output is in steps,
rather than ramps.

SIGNAL
OND.

AGe

ou,

Figure 3 - HC-55516/55532 CVSD Functional Diagram

8-91

The digital CVSD has a number of advantages over
its analog counterpart, and has desirable features
which would otherwise require additional circuitry:
1)

The all CMOS device requires only 1 mA current
from a single +4.5V to +7V supply.

2)

No bulky external precision resistors or capacitors are required for the integrators; time
constants of the digital filters are set by the
clock frequency and do not drift with time or
temperature.

3)

For best intelligibility and freedom from listener
fatigue, it is important that the recovered audio
is quiet during the pauses between spokeQ words.
During quiet periods, an alternate "1", "a"
pattern should be encoded, which when decoded
and filtered will be inaudible. Achieving this
in the analog CVSD requires that up and down
ramp slopes are precisely equal and that offsets
in the comparator and amplifiers are adjusted
to zero.
Improper adjustment or excessive
component drift can result in noisy oscillations.
In the digital design, comparator offset and
drift are adjusted by a long up-down counter
summed to the DAC to insure that over a period
of time equal numbers of 1's and a's are generated.

APPLICATIONS OF DELTA
MODULATION
1)

Telecommunications: Digitized signals are easily
routed and multiplexed with low cost digital
gates. Voice channels may be easily added to
existing multiplexed digital data transmission
systems.
The digital signals are much more
immune to crosstalk and noise when transmitted
over long distances by wire, R.F., or optical
CVSD has better intelligibility than
paths.
PCM when random bit errors are introduced
during transmission.

2)

Secure Communications: Digital data can be
quite securely encrypted using fairly simple
standard hardware (Figure 4a).
Scrambled
speech for audio channels may also be accomplished by encoding into a shift register, then
selecting different segments of the shifted data
in pseudo-random fashion and decoding it
(Figure 4b).

3)

Audio Delay Lines: Although charge-coupled
deviced (CCD) will perform this function, they
are still expensive and choice of configurations
is quite limited. Also, there is a practical limit
to the number of CCD stages, since each introduces a slight degradation to the signal.

An added feature is automatic quieting, where if
the DAC input would be less than 2 LSS's the
quieting pattern is generated instead. This has
proven to aid intelligibility.

As shown in Figure 5, the delay line consists of
a CVSD modulator, a shift register and a demodulator. Delay is proportional to the number
of register stages divided by the clock frequency.
This can be used in speech scrambling, as explained above, echo supression in PA systems;
special echo effects; music enhancement or
synthesis; and recursive or non recursive filtering.

,.

4)

To prevent momentary overload when beginning
to encode or decode, it is desirable to initialize the integrators. In the analog CVSD, external
analog switches would be required to discharge
the capacitors.
4)
In the digital CVSD, the filters are reset by
momentarily putting the "Force Zero" pin low.
At the same time, a quieting pattern is generated
without affecting internal encoding by putting
the "Alternate Plain Text" pin low.

•

5)

In some analog CVSD designs, transient noise
will be generated during recovery from a low
frequency overdriven input condi,tion.
The
digital CVSD has a clipped output with instant
recovery, when overdriven.

6)

Half-duplex operation (using the same device,
switch ing between the encode and decode
functions) requires external circuits with the
analog CVSD, while the digital type is switched
internally by a logic input.

Voice I/O: Digitized speech can be entered
into a computer for storage, voice identification,
or word recognition. Words stored in ROM's,
disc memory, etc. can be used for voice output.
CVSD, since it can operate at low data rates,
is more efficient in storage requirements than
PCM or other A to 0 conversions. Also, the
data is in a useful form for filtering or other
processing.

Figure 48 - Digital Transmission Encription

A possible drawback to the digital CVSD is that,
since its filter time constants are proportional to
the clock period, a single device will not be optimum
for all clock frequencies. For this reason, Harris has
two devices, the HC-55516 for clock rates below
24K bits/sec, and the HC-55532 for higher clock
rates.

Figure 4b - Voice Transmission Scrambling

8-92

CLOCK

6)

The AGC output (pin 4) is a digital output,
whose duty cycle is dependent on the average
audio level. This may be externally integrated
to drive an AGC preamplifier; or it could be
used (through a buffer gate) to drive im LEO
indi~ator to indicate proper speaking volume.

7)

To prevent generation lof alias frequencies, the
input filter should reduce the audio amplitude
at frequencies greater than half the clock rate
to less than 12 mill ivolts peak-to-peak.

8)

The complex output filter shown on the data
sheet is necessary only when measuring signal
to noise r4tios where an frequencies above 3kHz
must be removed. GenerMly a 2 pr 3 pole
filter is sufficient for acceptable voice quality.

9)

A suggested receiver clock circuit is a free running multivibrator, synchronized at each transition of the incoming data. Any synch errors
occurring during reception of long strings of
zeros or ones will have negligibl!l effect on the
decoded voice.

DELAYED
AUDIO

AUDIO
IN

OUT
Delay· N + FCLOCK

Figura 5 - Audio Delay Lina
aND ••v

I>----+----')OUT

6-~~=:l:~~+--O+15V

10

V-

7~_ _ _ _ _ _~

NOTES:
R1, R2: 1Kn, 1/4 or 1/2 Watt, 5%
R3: 10kn, 1/4 or 1/2 Wett, 5%
Cl, C2: 0.1/.1F
01,02: IN4002

R2~ 10kn,±5%
C1
01

:r'

-15Vo--__.-_..-'-J

IN-

11

C2 ~ 0.01/.1F (One Per Socket)
02 ~ IN4002 (One Per Board)

HA-2650/55, LM1458A/1558A,
LM4250/4250C

HA-2630/35

2

NC

V+

OUT1

NC

13

OUT2

12

BALANCE

+16V

"

02

BALANCE

BALANCE

11

-INt

BALANCE

10

+INl

-IN2

V-

+IN 2

Rl

+15V

-15V

R2

D1

NOTES:
R1, R2: 1Mn, 1/4 or 1/2 Watt, 5%
C1, C2: 0.1/.1F
01,02: IN4002

NOTE:
R1 ~2kn

HA-2650/55, LM4250/4250C

HA-2720/25

2K'.4WATT

R4

NOTES:
TA ~ +125 0 C, Supplies ~ ±15VOC
Resistors ~ 2kn, ±1 0%, 1/4 Watt
Capacitors

= 0.01

to O.1#J.F, Nonelectrolytic

NOTES:
TA~+1250C

Cl, C2 ~ 0.01 to 0.1/.1F
R1 ~ 1kn, R2 ~ 2Mn, R3 ~ 10kn, R4 ~ 5kn

10-17

HA-2740, LM146/346

HA-2730/35
14

r-__~r'~3______--,C2~

Rl

02

R4

Duro
-tNO

R4
+IND
+15V

-v,.

Cl

+INC

C2

OUTe
-1SV

t---VR"'.~-'·'-I

ISET IA.B,DI

01

NOTES:
C1. C2 = O.Ol/-1F
D1,D2=IN4002
R1. R2. R3, R4 = 2kn. 1/2 or 1/4 Watt, 5%
R5. R6 = 3Mn, 1/2 or 1/4 Watt, 5%

NOTES:
R1, + R4 = 2kn
R2,+ R3= 2Mn
C1, + C2 = .01 to .1/-1F
01, + 02 = IN4002 or Similar

HA-4156. HA-4741. HA-5064. HA-50B4.
LF37~, LM148/348, LM2908

HA-4600/02/05, HA-4620/22/25

Rl

+1SV

Dl

NOTES:
C1 = C2 = O.Ol/-1F
01 = 02 = IN4002
R 1 = R2 = R3 = R4 = 2kn, ±5%, 1/4 or 1/2 Watt

o

-15V

NOTES:
TA = +125 0 C
01,02 = IN4002

HA-5062, HA-5082, LF353

HA-4900/02/05
+15V

JlUC
_

DRIVE
SIGNAL -

QUTA

+V'"

-INA

OUTB

+INA

-IN 0

-vpo

+INB

+15V

Cl
Rl

5K

7
11
15

-1SV

D2

'--~~r-----"'-15V

NOTES:
TA = +125 0 C
C1. C2, C3 = 0.1/-1F
01,02.03 = IN4002
Drive Signal Fraq. = 2000Hz
Drive Signal Amp. = ±0.6V

10-18

NOTES:
C1, C2 = O.Ol/-1F
01,02 = IN4002
R1. R2 = 2kn, 1/2 or 1/4 Watt, 5%

R2

Dl

HA-51 00/05, HA-5110/15,
LF156 Series, LF157 Series

HA-5130/35, HA-5170, LF155 Series,
LM10B/30B, LM10BA/30BA, OP-07

R3

)----+-..--..-0"5V
01

77'\---+--....- ....0·,5V
C2

-I5V 0----<10-4-----'

NOTES:
R1 = R2 = 10kn, :t5%, 1/4 or 112 Watt
R3 = 100kn, ±5%, 1/4 or 1/2 Watt
C3 = O.01I1F
C1 = C2 = O.1I1F
01 = 02 = IN4002

NOTES:
R1 = 2kn; 5%. 1/4 or 1/2 Watt
C1, C2 = .01I1F
01,02 = IN4002

HA-5160/62

HA-5190/95
R3
+15V

01

)---+-.._-.._0+1SV

0'

D'l-_ _....._.._-o-I5V
R3

02

Rl

NOTES:
R1 = R2 = 1kn,±5%, 1/4 or 1/2 Watt
R3 = 10kn, t5%, 1/4 or 1/2 Watt
C1 = C2 = O.01IlF
C3 = O.1I1F
01 = 02 = IN4002

NOTES:
R1, R2: 1kn, 1/4 or 1/2 Watt, 5%
R3: 10kn, 1/4 or 1/2 Watt, 5%
C1, C2: O.1J.lF
01,02: IN4002

HA-B023

HC-5502

1

,

Al

~
Ne
IIA

2 -INA

.v"
OUT A

..!!..

4 DUTB

-tINB

E...

5 +V",

-INe

..!L

6 1st

,
AI

-INC

~+INC

I

A2

I.

3 +JNA

AI

R2

16

IsB 11

CI:

RING

3

'V
CEXT'

R

•
F2

CEXT3
DIGGNO
RS

iiROUT

DUTe ~

-v"

TIP

2

A'

--48V

9

C2

-

~tDI

'4V

+12V

:+~:4V

NOTES:
R1 = 2kn, 5%,1/4 or 1/2 Watt (One Each Per Socked
R2 = 150kn, 5%, 1/4 or 1/2 Watt (Ona Each Per Socket)
C1, C2 = O.01J.lF (One Each Per Socket)
01,02 = IN4002 (One Each Per Board)

10

"12

TX
ANAGNO
CEXT4

II

22

Rev
IN,

I

IN-

OUT
CEXT2

VB (TFI

~

VA(RFI
-v

PO

BATTGNO

2'
23

FI

StiD

NOTES:
R = 300n, t10%, 1/4 Watt
f1 = 15Hz, 0-5V Squara Wave
f2 = 60Hz, 0-6V Squara Wave
11 and 12 must be synchronized

10-19

HC-5551S

HC-5512/5512A

F2

VfXI+

VFXO

VFXI-

GNDA

I.I.

CLKO

14

VFRO

PoN

'3

PWRI

CLK

'2

\lSX

13
12

11

F'

I.

"

PWRO+

GNCD

PWRO-

VfRI

I.

VCC

9

V BB

-5V

Voo

--01,

-:

o.::T-L.r

+5V

NOTES:
R1 = 600n
f1 = 800kHz, TTL ±10%
f2 ~ 2.0Vp-p. 1 k Hz

NOTES:
TA = +125 0 C
VOO = +7.0V
fc= 16kHz

HI-200

HI-200

f,

.------_.--..-o+15V
C'

2

•

R'
-15V
C'

A2

A'

NC

NC

'3

GIIIo

+V

'2

NC

NC

IN2

IN'

,."

OUT 2

OUT 1

-V

VREF

f"
+15V
02

C2

R2

i j - - - 4 o - - . - o -15V

NC

01

02

NOTES:
f1 = 50kHz
R1, R2 = 1kn
C1, C2 = .01J.lF
01,02 = IN4002
(For Static Configuration Tie A1,
A2 to Ground)

NOTES:
C1 = C2 = 0.1/,!F
R1 = R2 = 1kn. ±5%, 1/4 or 1/2 Watt
01 = 02 = IN4002
f1 = 50kHz
(For Static Burn-In Tie f1 to Ground)

HI-201. HI-201HS

HI-300. HI-301. HI-302

, ----..
NC

II

AI
OUT1

IN 1
-V
Cl

GND
INC

R'

7
8

.

OUT<

A'

IN'

..

+V

13

OUT 2

VREF

IN3
OUT 3

R'

1.
I.

R2

0'

"

14

S3

54

~

03

04

...!L

c....!..

D1

02

..!L

S,

sa I.

5

7

.C

+V

13

,.!.

11

I.

2

IN'

IN2

9

GNo

-V

8

+15V

R4

c'4

fl

f

C

-

10-20

'

R3

A3

NOTES:
R1, R2, R3, R4 = 10kn, 5%, 1/4 or 1/2 Watt
C1, C2 = .01J.lF
01,02= IN4002
f = 100kHz, TTL Level. (50% Duty Cycle)

o

NOTES:
R1, R2, R3, R4 = 10kn, 5%,,1/4 or 1/2 Watt
C1, C2 = .01J.lF
01,02 = IN4002
F1 = 100kHz. TTL Level., (50% Duty Cycle 0-5V)

+-~

5V

HI-3Bl, HI-3B7

HI-303, HI-;i304, HI-305, HI-30B, HI-307

1
Rl

...''''4'-+__--1_.....<> +V

R2
13
4

12
Al

A3

11

SllNC

NC/52

14

D1/NC

NC/D2

13

NC/Dl

D2/Ne

12

Ne/S1

S2/NC

11

IN2

I.

INI
+15V

+V

-v

NC

GND

A3

f,
-15V

01

Cl

C2

NOTES:
R1 - R4 = 10k!1, :1:5%,1/4 or 1/2 Watt
C1 - C2 = .011.1F
01 - 02 = IN4002
f1 = 100kHz TTL Level., 5% Duty Cycle
(For Static Configuration Tie Input (f1) to Ground)

H 1-384. H 1-390

HI-50B/507, HI-50BA!507A

,.

15V

Al

1
2

A3

3

c....!-

,!A4

,6

7
R2

8

01

SI

NC

INI

03

-V

S3

GND

.!!..

r

14

NC

12

D4

+v

11

NC

IN2

~

D2

S2

....!..,

•
•
•

,6V

..!!.-

r
h
01 ~

02 ~

I
tC,

, *C2~

+15V

-

IN7A
IN6A

c,

IN 68/14

IN5A

IN6BJ13

IN4A

22

IN3A

21

IN3B111

IN2A

'0

10
1

IN2B/l0
IN lB/9

IN1A

12

GND

13

I•

INaB/lS
IN 78/15

IN4B/12

,.

+.v

....,-......+-<~~-o -15V

INSA

NC

f,

15

S4

-v

Dl

. ,.
EN

"

IJ!!-i+-----<>,.
17

1"--+-+------0 '1
A' 1-"'--+-+------0 I,
1-"'--+-+------0
"
16

VREF

A3iNC

A2

13

';'

NOTES:
R1 - R4 = 10k!1, :1:5%,1/4 or 1/2 Watt
C1 - C2 = .011.1F
01 - 02 = IN4002
f1 = 100kHz, TTL Level. (0-5V), 50% Duty Cycle
(For Static Configuration Tie Inputs (f1) to +5V)

NOTES:
R1, R2 = 1K!1, 5%,1/2 or 1/4 Watt
C1, C2 = O,11.1F
01,02 = IN4002
f1 = 1,OOkHz, f2 = 50kHz, f3 = 25kHz, f4 = 12.6kHz, f6 = 6.26kHz
(For Static Configuration Tla AO, A1, A2, A3 & EN to Ground)

HI-50B, HI-50BA
16

,5

f,
f2

EN

-v

-15V

+16V

01

GND

I

1.

+v

INI

II

+16V

C,

I

I

6

S3

S6

7

S4

S7

OUT

sa

, _ _---j---j-",

IN'

IN.

IN3

IN6

10

"

'OK
10K
Rl

NOTES:
R1 =10kn, 6%, 1/4 or 1/2 Watt
C1, C2 = 0.11.1F
01,02 = IN4002
fO = 100kHz, f1 = 50kHz, f2 = 25kHz, f3 = 12.5kHz,
50% Duty Cycle (0-5V)
(For Static Configuration Tie AO, A 1 & A2 to +5V.
Tie EN to Ground)

NOTES:
R1 = 10k!1, :1:5%,1/4 or 1/2 Watt
C1, C2 = .011.1F
01,02 = IN4002
fO = 100kHz, f1 = 50kHz, f2 = 25kHz, f3 = 12.6kHz, EN = 6,25kHz,
60% Duty Cycle 0-5V
(For Static Configuration Tie AO, A 1, A2 to +6V, EN to Ground)

10-21

HI-S09, HI-S09A

HI-S09, HI-S09A

100---------'_


120---------"-1

-v

-15V

-15Vo--f------<~-.----=_I

01

W

INtA

IN 18

IN2A

IN28

IN3A

IN38

01

18

+15V

C2

17
18

10K

10K
Rt

I.
I.

10K
R2

NOTES:
R1, R2 = 10kn, ±5%, 1/2 or 1/4 Watt
C1, C2 = .011lF
01,02 = IN4002
fO = 100kHz, f1 = 50kHz, f2 = 25kHz, 50% Outy Cycle (0-5V)

NOTES:
R 1, R2 = 1 Okn, ±5%, 1/2 or 1/4 Watt
C1, C2 = .011lF
01.02 = IN4002
fO = 100kHz, f1 = 50kHz, f2 = 25kHz, EN = 12.5kHz,
50% Outy Cycle (0-5V)

(For Static Configuration Tie AD, A1 to +5V. Tie EN to Ground)

(For Static Configuration Tie AO, A1, & A2 to +5V. EN to GND)

HI-518
... ,SV

W

OUT A

OUT.

-v

IN8/4B

1N4/4A

18
C2

IN313A

IN5/1S

1""-+-+------01.
1-"-+-+------0'1
1-"'-+-+------0'2
1-"'-+-+------0'3

NOTES:
R1, R2 = 10kn, ±5%, 1/4 or 1/2 Watt
01,02 = IN4002
C1, C2 = .011lF
f1 = 100kHz, f2 = 50kHz, f3 = 25kHz, f4 = 12.5kHz,
50% Outy Cycle (0-5V)
(For Static Configuration Tie AO - A2 to +5V, Tie EN to GNO)

9

AZ/SE-DIFF

IN2/2A

I'

INt/1A

13

EN

12

AO

11

AI

10

NOTES:
R1, R2 = 10kn, ±5%, 1/4 or 1/2 Watt
C1, C2 = .011lF
01, 02 = IN4002
f1 = 100kHz, f2 = 50kHz, f3 = 25kHz, 50% Outy Cycle (O-5V)
(For Static Configuration Tie AO, A1 to +5V, Tie EN to GNO)

HI-524

HI-539.

10o--------'-~

-15V

01

02

'2o-------...;~
-15Vo-~r_.....- -.....--"~

C2

D2

R2

Do--_ _ _

-+-+~

1-"'-+-+------0'1
1-"''-+-+------012

NOTES:
R1, R2 = 10kn,±5%, 1/4 or 1/2 Watt
C1, C2 = .011lF
01,02 = IN4002
f1 = 500kHz, f2 = 250kHz, f3 = 125kHz, TTL Levels,
50% Outy Cycle

10-22

NOTES:
C1, C2 = .011lF
01,02 = IN4002
R1, R2 = 10kn, 5%,1/2 or 1/4 Watt
fO = 100kHz, f1 = 50kHz, f2 = 25kHz, TTL Logic Levels

"

'I
'2

HI-562A

HI-1818A

IMSBI BIT> 1'2,,4'--_-0 "
~'---o12

5

VREF (HIINI

7

V..BIPOLAR RIN

6

I.
16
1-"'---0

7

!-"'---V

NC

A2

I.

DZ

52

9

"

II

I

12

'5V
+15V

NOTES:
Rl - R4 = 10kf2, 5%, 1/4 or 1/2 Watt
Cl, C2, C3 = .01f.JF
01,02,03 = IN4002
f1 = lOOk Hz, 50% Duty Cycle
(For Static Configuration Tie Inputs (Pins 10, 15) to +5V)

10-23

HI-561Q

'15

"

.,.

22

23

21

,.

20

-15

IB

17

16

I.
11

,.

12

13

15

NOTES:
Rl = 50kn
02,03,011 = IN4002
C2, C3, Cll = O_OlJJ.F

HI-5712/12A

26
'r1
26

as

24
23
22

10

11

NOTES:
Rl'- R12 = 4kn, 1/4 or 1/2 Watt, 5%
l'I13 = 10kn, 1/4 or 1/2 Watt, 5% (One Each Per Boerd)
R14 = lkn, 1/4 or 1/2 Watt, 5% (One Eech Per Board)
Cl, C2, C3 = .01JlF (One Each Per Socket)
C4 = lOOI.lF (One Each Pe! Board)
,
01,02,03 = IN4002 (One Each Per Board)
VIN = 1kHz Triangular Wave, :t6V
Ql = 2N2222 (One Each Per Board)
(Short Boards, PC Layout Only. Do Not Hand Wire)

Cl

"
I.
I.

02'

HI-7541

10

~+1V

I,

A.

'.V

R2
03

12

O.

-=f,

13

12

'r1

13

~

I,
I.

as
2'

C,

,0

23

11
12

22

,.,.

16

18

VREI1

+1DV

Voo

+15Y

BIT 1 (MSBl

BIT 12

BIT2

BIT11

•

BIT3

BIT 10

13

7

BIT4

BIT9

12

8

BIT5

BIT8

11

9

BIT6

BIT 7

S

01

,.

1,0

I.
18
17

,3
C2

'6

,,-

NOTES:
Cl = .01I.1F, 01 = IN4002
f1 = 100kHz, f2 = 60kHz, f3 = 26kHz, f4 = 12.5kHz, f6 = 6.26kHz,
f6 3.125kHz, f7 = 1.56kHz, f8 = .78kHz, f9 .390kHz,
flO =-.195kHz, f11 = .098kHz, f12 =,.049kHz, 50% Duty Cycle,
Square Wave, TTL Level (0-5V), (For Static Configuration Tie
fl - f12 to +5V)

=

10-24

-15V

-=-

HI-59Q1

II

12
13

=

Packaging
IL/IJI.....
................................

PAGE
Harris Analog Package Selection Guide

11-2

Package Configuration

11-4

•
11-1

I

Harris Analog Package Selection Guide
PACKAGE CONFIGURATION (See Notel

CAN

PLASTIC

CEROIP

HA-160S
HA-2400/04/05
HA-2420/25
HA-2500/02/05
HA-2510/12/15

R

G

L

H

0

R
R

G
G

L
L

HA-2520/22/25
HA-2530/35
HA-2539
HA-2540
HA-2600/02/05

R
R

G

L

H
H

0
0

R

G

L

R

G

L

G

L
L
L

PART NO.

HA-2620/22125
HA-2630/35
HA-2640/45
HA-2650/55
HA-2720/25

HA-5084
HA-51 00/05
HA-5110/15
HA-5130/35
HA-5160/62
HA-5170
HA-5190/95
HA-8023
HC-5502
I-IC-5510
HC-5511
HC-5512/5512A
HC-55516
HD-0165
HI-200
HI-201
HI-201HS
H 1-300/301/304/305

III

NOTE:

LEAD LESS
CHIP CARRIER

B

X

X

V

R
R
R

0

HA-2730/35
HA-2740
HA-4156
HA-4600/02/05
HA-4620/22/25
HA-4741
HA-4900/02/05
HA-5062
HA-5064
HA-50S2

SIDE BRAZE

R

J

E

H
H
H

0
0
0

H

D
E

G

L
0
L

H

R
R
R

R

G
H
G

G
G

X
X

0
L
L
L

X

R
R

G

L
0

J

E
M
M

V

*

X

E
A

T

H

J
J
T

H

M
D
E
E
D

X

"Package Configuration" references drawings on the following pages. Package designations to be used
in cons~ructing the part number are explained in the Ordering Information in the Part number guide.
Plastic DIP packages are not available for military temperature range.
Consult factory for information on ordering and availability of products with package configurations other
than those indicated in the chart.
Solder-dipped parts add +0.003 inches to "dimension B" in plastic DIP and "dimension G" in metal cans.
o

11-2

Contact factory for packaging.

Harris Analog Package Selection Guide (continued)
PACKAGE CONFIGURATION (See Note)
PART NO.
H 1-302/303/306/307
HI-381/384/387/390
381/387
384/390
HI-506/507

CAN

T

PLASTIC

CERDIP

H

0

J
J

E
E
N

P

H 1-506A/507 A
HI-508/509
HI-508A/509A
HI-516
HI-518

P

J
J
P
K

HI-524
HI-539
HI-562A
HI-1818A/1828A
HI-5040 thru 5051
H 1-5043/5045

K

J

LEAD LESS
CHIP CARRIER

Y

N
E
E
N
F

Y

X
X
Y

F
E
C

J
J

HI-5610
HI-5618A/18B

E
E
E

Y

X
C

K

HI-5712/12A
HI-5900
HI-5901

F
(MC) LCC's on Ceramic Substrate
(MB) LCCs on Ceramic Substrate
(MB) LCCs on Ceramic Substrate

HI-7541
HV-l 000/05/1 0
LF353
LF 155/155A/355/355A/355B
LF 156/156A/356/356A/356B
LF157 /157 A/357 /357 A/357B

R
R
R
R

LF347
LM 108/308
LM 108A/308A
LM118/318
LMl18A/318A

R
R
R
R

G

LM143/343
LM 143A/343A
LM146/346
LM148/348
LM 148A/348A

R
R

G
G

LM 1458/1558A
LM2908
LM4250/4250C
OP-07

R

NOTE:

SIDE BRAZE

Z

K

R
R

J
G
G
G
G

0
G
G
G

X

L
L
L
L
H
L
L
L
L

J

L
L
E

H
H

0
0

G

L

H

0

G
G

L
L

I

"Package Configuration" references drawings on the following pages.

a

Package designations to be used

in constructing the part number are explained in the Ordering Information in the Part number guide.

Plastic DIP packages are not available for military temperature range.
Consult factory for information on ordering and availabilitY of products with package configurations other

than those indicated in the chart.
Solder-dipped parts add +0.003 inches to "dimension B" in plastic DIP and "dimension G" in metal cans.

11-3

I

Package Configuration

o TYPE SIDE BRAZED CERAMIC
~--------D--------~

LEAD DIM. DIM. DIM. DIM. DIM. DIM. DIM. DIM. DIM. DIM. DIM.
PKG.
Q
B
C
D
F
G
H
S
TYPE COUNT A

14

A

B

16

Z

18

5

NOTE:

.200

.014
.023

:o;s Te5 '3iO

.220

.290
.320

IDa iiSC

.125
.200

.015
.060

.098

.008
.015

.840

.220
.310

.290
.320

.030
.070

.100

.200

.014
.023

.125
.200

.015
.060

.098

.014
.023

.OOB
.015

.950

.220
.310

.290
.320

.030
.070

.100

.200

.125
.200

.015
.060

.098

.008

~

.030

.100

esc
esc

OIMENSIONS IN INCHES

MAX.

o TYPE SIDE BRAZED CERAMIC

DIM.

PKG.
TYPE

S

C

.09B

NOTE:

~

DIMENSIONS IN INCHES

MAX.

I'

E---jr C

~---F----I

J TYPE CERDIP DUAL-IN-LiNE
N TYPE PLASTIC DUAL-IN-LiNE

0

PKG.

LEAD DIM. DIM. DIM. DIM. DIM. DIM. DIM. DIM. DIM. DIM. DIM. DIM.
Q
G
A
B
C
D
E
F
H
L
S

a

TYPE COUNT

III

G,L

8

D,H

14

E,J

16

F,K

18

.E!!

~ ~ ~ ~

.395

.310

.320

.070

esc

.200

~
.060

.060

00
150

~ ~
.200

.023

.015

.200

.023

.015

.790

.220
.310

.290
.320

.030
.070

.100
8SC

.125
.200

.015
.060

.098

00
150

.014
.023

.008
.015 .790

.220
.310

.290
.320

.030
.070

.100

.200

.125
.200

.015
.060

.060

00
150

.200

.014
.023

.OOB
.015

.220
.310

.290
.320

.030
.070

.125
.200

.015
.060

.060

00
150

~ .OOB

H

a

11-4

,

NOTE:

~

MAX.

.950

ssc
.100

esc

DIMENSIONS IN INCHES

Package Configuration
J TYPE CERDIP DUAL-IN-LiNE

°1

D

PKG.

IT~

LEAD

TYPE COUNT

~

H

M

24

N,P

28

NOTES:

DIM. DIM. DIM. DIM. DIM. DIM: DIM. DIM. DIM. DIM. DIM. DIM.
Q
D
E
F
G
H
L
S
A
B
C

a

.014

.OOS

.500
.015 1.290 .610

.590
.620

.030
.070

.100
SSC

.015

.120
.200

.075

.225

.023
.014

.OOS

.500

.590

.030

.:!!!!!

.120

E.!.§

.225

.023

.015 1.490 .610

.620

.070

SSC

.200

.075

II(1IN.
MAX.

.098

00
150

~
.098

150

DIMENSIONS IN INCHES

a

H TYPE METAL CAN, TO-99 (8 PIN) OR TO-100 (10 PIN)

f,*,ol
lL
A

r
J

J.
1K

PKG.

LEAO

TYPE

COUNT

R

S

T

10

NOTE:

DIM. DIM. DIM. DIM. DIM. OIM. DIM. DIM. DIM.
B
C
D
G
A
J
K
.335

.165

.010

.500

.200

.016

.027

.027

.370

.185

.040

.045

.550

SSC

.021

.045

.034

.335 .• 165
.370 .lS5

.010
.045

.500
.550

.230

.016
.021

.027

.04Q

.045

.027
.034

SSC

MIN.
MAX.

DIMENSIONS IN INCHES

H TYPE METAL CAN, TO-B
(HA-5190/95 AND HA-2630/35 ONLY)

p~~

P1
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