1982_Mitsubishi_LSI 1982 Mitsubishi LSI
User Manual: 1982_Mitsubishi_LSI
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MITSUBISHI DATA
BooK1982
LSI
,
MITSUBISHI
IIiw.. ELECTRIC
All values shown in this catalogue are subject to change for product improvement.
The information, diagrams and all other data included herein
are believed to be correct and reliable. However, no responsibility
is assumed by Mitsubishi Electric Corporation for their use, nor
for any infringements of patents or other rights belonging to
third parties which may result from their use.
MELPS and MELCS are registered trademarks of Mitsubishi
Electric Corporation.
* PARCOR System was developed by the Nippon Telegraph and
Telephone Public Corporation.
INDEXES
RANDOM-ACCESS MEMORIES
READ-ONL Y MEMORIES
MELPS 4 MICROCOMPUTERS
MELPS 41/42 MICROCOMPUTERS
MELPS 8-48 MICROCOMPUTERS
MELPS 8/85 MICROPROCESSORS
LSls FOR PERIPHERAL CIRCUITS
MELPS 86 MICROPROCESSORS
SPEECH SYNTHESIS LSls (PARCOR SYSTEM)
GENERAL-PURPOSE MOS LSls
D
D
D
ID
0
D
D
[l
D
ml
ED
MICROCOMPUTER SYSTEMS
[E
MICROCOMPUTER SUPPORT SYSTEMS
EEl
MICROCOMPUTER SOFTWARE
[I]
APPLICATIONS
EEl
MITSUBISHI LSls
PREFACE
Thank you for your continued patronage of Mitsubishi
Electric and our semiconductor products.
Semiconductor devices are a mainstay of the burgeoning electronics industry, where they are finding more and
more applications, .and meeting demands for increased
sophistication and diversification of performance and
function.
This data book has been compiled to be as complete
as possible, including data on large-scale IC memories,
single-chip microcomputers, peripheral LSls for 16-bit
parallel processing CPUs, speech synthesis LSls and microcomputer development support equipment, with the addition of a variety of originally developed MOS LSI devices.
We hope you will let us know of any mistakes or omissions that come to your attention, and any suggestions you
might have on improving the usefulness of this data book.
January, 1982
Kimio Sato, General Manager
Semiconductors Division
Mitsubishi Electric Corporation
• MITSUBISHI
"ELECTRIC
MITSUBISHI LSls
CONTENTS
D
INDEXES
Page
Index by Function .................................... .................................................................................
Index by Type Designation .......................................................................................................
Guide to Interchangeability .......................................................................................................
Guide to Selection of RAMs, PROMs, EPROMs and ROMs .......................................................
Ordering Information ................................................................................................................
Package Outlines ........................................................................................................................
Terminology ...... · .. · ......... ....... ........ ............... ............ ............ ...... ........................ ...... ..................
Letter Symbols for The Dynamic Parameters .... ·.............. · ................ · ........................ · .............. ·
Symbology ...... · .. · .... · ........... ........ ......................................................... ............ ....... ..................
Quality Assurance and Reliability Testing .................................................................................
Precautions in Handling MOS ICs ..... ....... ......................... ................. ........ ....... ................... .....
1-2
1-7
1-10
1-14
1-15
1-17
1-28
fJ M58725P,
RANDOM-ACCESS MEMORIES
P-15
16384-Bit (2048-Word by 8-Bit) Static RAM .......................................................
M58981 P-30, P-45
M5K4116P-2, P-3
M5K4164P-15, P-20
M5K4164NP-15,NP-20
M5K4164S-15, S-20
M5K4164NS-15, NS-20
M5L2114LP, P-2, P-3
M5L5101 LP-1
M5T4044P-20, P-30, P-45
B
D
D
4096-Bit (1024-Word by 4-Bit) CMOS Static RAM .................................................
16384-Bit (1 6384-Word by l-Bit) Dynamic RAM ...................................................
65536-Bit 165536-Word by l-Bit) Dynamic RAM· .................................................
65536-Bit (65536-Word by l-Bit) Dynamic RAM ...... • .... • .. • ............ • ........ • .. • .. • .... • .. •
65536-Bit (65536-Word by 1-Bit) Dynamic RAM ...................................................
65536-Bit(65536-Word by l-Bit) Dynamic RAM· .. • .................... • ............ • .. •.... • .. • ..
4096-Bit (1024-Word by 4-Bit) Static RAM ........................................................
l024-Bit (256-Word by 4-Bit) CMOS Static RAM· .. • .......................... • ................ •..
4096-Bit (4096-Word by l-Bit) Static RAM .. • ...... • .................. • .. • .. • .. • .. • .. • ............
1-33
1-36
1-39
1-44
2-3
2-9
2-13
2-25
2-41
2-55
2-71
2-85
2-89
2-93
READ-ONLY MEMORIES
Development of Mask-Programmable ROMs ..... ..........................................................................
M54700 P, S
1024-Bit (256-Word by 4-Bit) Field-Programmable ROM with Open-Collector Outputs .......
M54730P, S
256-Bit (32-Word by 8-Bit) Field-Programmable ROM with Open-Collector Outputs ..........
M54740AP, S/M54741AP, S 4096-Bit (1024-Word by 4-Bit) Field-Programmable ROM ..................................
M58653P
700-Bit (50-Word by l4-Bit) Electrically Alterable ROM ...........................................
M58735-XXXP
32768-Bit (4096-Word by 8-Bit) Mask-Programmable ROM ......................................
M5G1400P
l400-Bit (100-Word by l4-Bit) Electrically Alterable ROM ........................................
M5L2716K, K-65
l6384-Bit (2048-Word by 8-Bit) Erasable and Electrically Reprogrammable ROM ...............
M5L2732K, K-6
32768-Bit (4096-Word by 8-Bit) Erasable and Electrically Reprogrammable ROM ...............
M5L2764K, K-2, K-3
65536-Bit (8l92-Word by 8-Bit) Erasable and Electrically Reprogrammable ROM ...............
3-3
3-5
3-10
3-14
3-18
3-22
3-24
3-28
3-32
3-36
MELPS 4 MICROCOMPUTERS
M58840-XXXP, M58841-XXXSP Single-Chip 4-Bit Microoomputer with 8-Bit A/ D Converter .........................
M58842S
MELPS 4 System Evaluation Devioe .............................................................
M58843-XXXP, M58844-XXXSP Single-Chip 4-Bit Miorooomputer with 8-Bit A/D Converter· ........................
M58845-XXXSP
Single-Chip 4-Bit Microcomputer with 8-Bit A/D Conveter and Two Timer/Event Counter ..
M58846-XXXSP
Single-Chip 4-Bit Microcmputer with Two Timer IEvent Counter ...............................
M58847 -XXXSP
Single-Chip 4-Bit Microcomputer ...................................................................
4-2
4-13
4-18
4-29
4-41
4-53
MELPS 41 /42 MICROCOMPUTERS
M58494-XXXP
M58496-XXXP
M58497-XXXP
~ MELPS
5-3
5-17
Single-Chip 4-Bit CMOS Microcomputer· ...... • .... • .. • ............ • .. • ............ • ........ • .. • .. 5-32
Single-Chip 4-Bit CMOS Microcomputer ........ • ...................................... • .. • .. • .. • ..
Single-Chip 4-Bit CMOS Microcomputer .............................. • ........................ • .. •
8-48 MICROCOMPUTERS
ME LPS 8-48 Microcomputers Function of MELPS 8-48 Microcomputers ................ • ...... • .................. • .. •• .. ·
M5L8048-XXXP, M5L8035LP Single-Chip 8-Bit Microcomputer ..........................................................
M5L8049-XXXP, P-8, P-6, M5 L8039P-11, P-8, P-6 Single-Chip 8-Bit Microcomputer ............................
M5L8748S
Single-Chip 8-Bit Microcomputer with EPROM ...................................................
M5L8243P
Input/Output Expander .............................................................................
• MITSUBISHI
..... ELECTRIC
6-3
6-21
6-25
6-29
6-37
MITSUBISHI LSls
CONTENTS
o
Page
MELPS 8/85 MICROPROCESSORS
M5L8085AP, S
M5L82l2P
M5L82l6P, M5L8226P
M5L8l55P
M5L8l56P
D
7-3
7-17
4-Bit Parallel Bidirectional Bus Drivers ............................................................... 7-21
2048-Bit Static RAM with I/O Ports and Timer ..................................................... 7-25
2048-Bit Static RAM with I/O Ports and Timer ..................................................... 7-33
8-Bit Parallel Microprocessor .........................................................................
8-Bit Input/Output Port with 3- State Output .......................................................
LSls FOR PERIPHERAL CIRCUITS
M58990P
M5C6847P-l
M5L8041A-XXXP
M5L8251AP
M5L8253P-5
M5L8255AP-5
M5L8257P-5
M5L8259AP
M5L8279P-5
M5W179l-02P
m
8-Bit 8-Channel A-D Converter ........................................................................
8-3
8-7
8-17
Programmable Communication Interface .............................................................. 8-41
Programmable Interval Timer .................................... _.................................... 8-57
Programmable Peripheral Interface .................................................................... 8-65
Programmable DMA Controller· .. · .................................................................... 8-81
Programmable Interrupt Controller ..................................................................... 8-91
Programmable Keyboard/Display Interface ........................................................... 8-105
Floppy Disk Formatter/Controller .............. • .................................................... ·8-117
Video Display Generator .............. • ...... ••• .... •• ...... •• ............ • .... • ........ • ........ • ......
Universal Peripheral Interface .........................................................................
MELPS 86 MICROPROCESSORS
M5L8086S
M5L8282P, M5L8283P
M5L8284P
M5L8286P, M5L8287P
M5L8288P
[I!] SPEECH
9-3
9-35
Clock Generator and Driver for 8086, 8088, 8089 Processors ...................................... 9-39
16-Bit Parallel Microprocessor ........................................................................
Octal Latch ............................................................................................
Octal Bus Transceiver ................................................................................
Bus Controller for 8086, 8088, 8089 Processors .....................................................
9-46
9-50
SYNTHESIS LSls (PARCOR SYSTEM)
M588l7 AP
M588l8-XXXP
M588l9S
10-3
10-13
EPROM Interface ..................................................................................... 10-19
Speech Synthesizer ...................................................................................
128K-Bit Phrase ROM
..............................................................................
m
GENERAL-PURPOSE MOS LSls
M50ll0XP, M50ll5XP 30- OR 120-Function Remote-Control Transmitters' ...... •.. • .. ••• ........ • ...... • .. • ...... • ......
M50lll XP, M50ll6XP, M50ll7XP 30--120-Function Remote-Control Receiver ...................................
M50250P
Refrigerator Controller .. •• .. • ........ • .... • .................. • .......... • .... • .. • .. • ..................
M50401 P, M50402P, M50403P, M50404P, M50405P CMOS Analog Clock CirCUIts ..........................
M58412P, M584l3P
CMOS LCD Digital Alarm Clock Circuits ............................................................
M58435P, M58437-001P CMOS Analog Clock Circuits ........................................................................
M58478P, M50l21P, M50l22P 17-Stage Oscillator/Divider .............................................................
M58479P, M58482P
CMOS Counter/Timers ................ • .................... • .......... • ........ • .. • .. • ...............
M58480P, M58484P
30-Function Remote-Control Transmitters ..........................................................
M58481 P
30-Function Remote-Control Receiv·er .............................................................
M58485P
29-Function Remote-Control Receiver ... .......... .................. ..............................
M58486AP
Voltage Synthesizer ................................................................................
M58487 AP
24-Function Remote-Control Receiver .............................................................
11-3
11-9
11-15
11-19
11-23
11-31
11-35
11-39
11-43
11-47
11-51
11-55
11-65
[fl MICROCOMPUTER SYSTEMS
PCA8501 GOl , G02
PCA8506
PCA8507
PCA8520G01, G02
PGA8540G01, G02
PCA7002G01, G02
MELCS 85/2 Single-Board Computer ..............................................................
MELCS 85/2 Memory and Parallel I/O Expansion Board
......................................
12-3
12-7
12-11
12-15
M ELCS 85/2 Color TV Display Single-Board Computer .......................................... 12 -19
MELCS 70/2 Speech Synthesizer Single-Board Computer ....................................... 12-25
MELCS 85/2 Memory and Serial I/O Expansion Board· .... • .. • .......... • .... • ........ • ...... • ..
MELCS 85/3 Voice Generating Single-Board Computer ..........................................
• MITSUBISHI
"ELECTRIC
MITSUBISHI LSls
CONTENTS
[13. MICROCOMPUTER
PCA0803
PC4000
PC7000
PC8500, PCA8503
PC9000
PCA4Q(n
PCA4003
PCA4004
PCA4005
PCA4011
PCA4012
PCA4014
PCA8400
PC4100
PCA4301
PCA4303
PCA4304
PCA4305
PCA4101
PCA42011
PCA4202
PCA8402
~. MICROCOMPUTER
Page
SUPPORT SYSTEMS
13-3
13-5
Speeoh Synthesis Evaluation Unit •••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• 13-9
MELCS 85/1 Portable Miorooomputer Console ••••••••••••••••••••••••••••••••••••••••••••••••••••••• 13-11
Cross Assembler Machine ••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• 13-17
MELPS 4 Dedioated Board ••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• 13-20
MELPS 4 Dedioated Board ••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• 13-22
MELPS 4 Dedioated Board •••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••~ ••••• 13-24
MELPS 4 Dedioated Board ••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• 13-26
MELPS 41 Dedioated Board.· •••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• 13-28
MELPS 42 Dedioated Board.· •••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• 13-30
MELPS 42 Dedioated Board •••••••••••••••••••••••••••••••••••••••••••••••••••••••• , ••••••••••••••••••• 13-32
MELPS 8-48 Dedioated Board ••••••••••.•••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• 13-34
M5L8748S Programming Adaptor ••••••••.•••••••••••••••••••••••••••••••••••••••••••••••••••••••••• 13-36
MELPS 4 Evaluation Board •••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• 13-37
MELPS 4 Evaluation Board ............................................................................ 13-38
MELPS 4 Evaluation Board························ ••••••••• • •••••••••••••••••••••••••••••••••••••••••• 13-39
MELPS 4 Evaluation Board ............................................................................ 13-40
MELPS 41 Evaluation Board •••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• 13-42
MELPS 42 Evaluation Board .......................................................................... 13-44
MELPS 42 Evaluation Board .... • .............. • .. • .. • .. • .......... ••••• .. •• .... • ...................... 13-46
MELPS 8-48 Evaluation Board ....................................................................... 13-48
MELCS 8/2 Program Cheoker .........................................................................
Debugging Maohine ••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••
SOFTWARE
Software Codes .......................................................................................................................... 14-3
MELPS 4/41 Software Available Materials ....................................................................................... 14-4
MELPS 4/41 Software General Desoription ...................................................................................... 14-6
MELPS 4/41 Software Development of Applioation Programs .................................................................. 14-7
ME LPS 8/85 Software Available Materials ...... • ................................................................................ 14-8
ME LPS 8/85 Software General Desoription ...................................................................................... 14-9
MELPS 8/85 Software' Development of Applioation Programs .................................................................. 14-10
MELPS 4 Software
Cross Assembler ........................................................................................ 14-11
ME LPS 4 Software
Simulator ................................................................................................. 14-15
ME LPS 4 Software
Paper-Tape Generation Program for PROM Writers .................................................. 14-19
ME LPS 41 Software
Cross Assembler ........................................................................................ 14-21
ME LPS 41 Software
Simulator ................................................................................................. 14-25
MELPS 41 Software
Paper-Tape Generation Program for PROM Writers .................................................. 14-29
ME LPS 42 Software
Cross Assembler ........................................................................................ 14-31
MELPS 42 Software
Paper-Tape Generation Program for PROM Writers .................................................. 14-35
MELPS 8-48 Software Cross Assembler ........................................................................................ 14-37
MELPS 8-48 Software Paper-Tape Generation Program for PROM Writers ................................................... 14-41
ME LPS 8/85 Software PL/1/l Cross Compiler ................................................................................. 14-43
ME LPS 8/85 Software Cross Assembler.............................................. .......................................... 14 -47
ME LPS 8/85 Software Simulator ................................................................................................. 14-51
MELPS 8/85 Software Paper-Tape Generation Program for PROM Writers ........ • ......................................... • 14-55
MELPS 8/85 Software Self Assembler .......................................................................................... 14-57
MELPS Software
Editor .................................................................................................... 14-61
MELPS 8 BOM-PTS
Basio Operating Monitor-Paper-Tape System ....................................................... 14-63
ME LPS 8 BOM-B
Basio Operating Monitor-Basio System ............................................................... 14-65
• MITSUBISHI
.... ELECTRIC
MITSUBISHI LSls
CONTENTS
r1r=I
Page
~ APPLICATIONS
Memory Development Approaches ........................................................................................... 15-3
16K-Bit Dynamic RAM
(M5K4116P, S)···········································································15-9
64K-Bit Dynamic RAM
(M5K4164S, M5K4164NS)· .. • .... · .... •.... • .. •··• .. • .. ·• .... •·••·•••·•···· .. ··········15-21
Static RAM
(M58725P, M5L2114LP) ................................................................ 15-51
CMOS Static RAM
(M58981 p, M5L5101 LP-1 ) .............................................................. 15-56
EPROM
(M5L2716K, M5L2732K, M5L2764K)· .. •.. •·• .. ••·••··• .. •···•·• .. •·•••·•··•·•••···•• 15-67
Error Detecting and Correcting .............................................................................................. 15-79
MELPS 4 Program Library
Subroutines .. ··· ... · ........................................................................ 15-86
Application of MELPS 4 Single-Chip 4-Bit Microcomputer (M58840-xxxP) in a Microwave Oven ....... 15-98
MELPS 8/85 Program Library
Subroutines ................................................................................ 15-102
Application of MELCS 8/2 Single-Board Computer (PCA0801) in Data Transmission through a
Master-Slave Multicomputer System ........ 15-106
Contact Address for Further Information
• MITSUBISHI
.... ELECTRIC
INDEXES
D
MITSUBISHI LSls
INDEX BY FUNCTION
Electrical characteristics
Circuit function and organization
Type
Supply
Structure
voltage
(Note 1)
(V)
Typ pwr Max
diss;access
pasion
time
(mW)
(ns)
Min.
cycle
(ns)
Max.
frequency
(MHz)
tIme
Package Interchangeable
products
(Note 2)
Page
• Static RAMs
I 2114L-2
TMS4045-20
2-85
12114L-3
TMS4045-30
2-85
-
12114L
TMS4045-45
2-85
200
-
TMS4044-20
2-93
300
300
-
TMS4044-30
2-93
200
450
450
-
TMS4044-45
2-93
200
150
150
-
TMS4016-15
2-3
200
200
200
-
TMS4016
2-3
12±100/0 280
5±100/0
150
375
-
200
375
-
300
200
200
-
250
300
300
-
M5L2114LP
200
450
450
M5T4044P-20
300
200
250
M5L2114LP-2
M5L2114LP-3
M5T4044P-30
I
i
4096-Bit (1024X4) Static RAM
N,SI, ED 5 ±100/0
N,SI,ED 5±10%
4096-Blt (4096x 1) Static RAM
M5T4044P-45
r----
M58725P-15
M58725P
N, SI,ED 5±100/0
16384-Bit(2048x8)Statlc RAM
18P4
18P4
24P1
• Dynamic RAMs
M5K4116P-2
16384- Bit (16384 xl) DynamiC RAM
N. SI
M5K4116P-3
65536-Blt(65536x1)Dynamlc RAM
Pin 1 (RFE) function
N, SI
M5K4164NP-15
M5K4164NP-20
65536- Blt(65536 xl) DynamiC RAM
Pin 1 rlU connection
N, SI
M5K4164S-20
M5K4164NS-15
M5K4164NS-20
280
-5.7
M5K4164P-15
M5K4164P-20
M5K4164S-15
-4.5~
65536-Blt(65536x1)Dynamlc RAM
Pin 1 (REF) function
65536- Bit(65536 Xl) DynamiC RAM
Pin 1 no connection
N, SI
5±100/0
5±100/0
5±100/0
N, SI
5±100/0
C. SI
5±100/0
MK4116-2
2-13
MK4116-3
2-13
16P4
200
150
260
-
170
200
330
-
200
150
260
-
170
200
330
-
200
150
260
-
1f3P4
16P4
16S1
170
200
330
-
200
150
260
-
170
200
330
-
75
450
450
-
75
300
300
-
75
450
480
-
200
20/1s
-
16.8kH
14P4
14P4
16S1
-
2-25
-
2-41
2-25
2-41
MK4164
2-55
MCM6664
2-55
12164
2-71
MCM6665
2-71
15101 L-1
2-89
.CMOS Static RAMs
M5L5101LP-1
M58981 P-30
M58981 P-45
1024-Blt (256x4) CMOS Static RAM
4096- Bit (1024 X 4) CM OS Static RAM
C. SI
5±100/0
22P1
-
2-9
-
2-9
18P4
.Mask ROM
M58735-XXXP
32768-Blt (4096x8) Mask
Programmable ROM
.Field-Programmable ROMs
M58653P
M5G1400P
M5L2716K
M5L2716K-65
M5L2732K
M5L2732K-6
700-Bit(50X 14)
Electrically Alterable ROM
1400-Bit (100x 14)
Electrically Alterable ROM
P, AI
5±50/0
P, AI
5±50/0
16384-Bit (2048x8) Erasable and
Electrically Reprogrammable ROM
1'{Si,FA
5±'50/0
32768-Bit (4096x8) Erasable and
Electrically Reprogrammable ROM
N,SLFA
5±50/0
200
20/1s
-
16.8kH
300
450
-
-
300
650
-
-
400
450
-
-
400
550
-
-
200
-
-
250
!300
-
-
-
-
M5L2764K-2
M5L2764K
M5L2764K-3
65536-Bit (8192x8) Erasable and
Electrically Reprogrammable ROM
N,Si,FA
5±50/0
I
500
24K10
24K10
28K10
-
GI1400
3-18
3-24
i 2716
3--28
i 2716-6
3-28
i 2732
3-32
I 2732-6
3-32
i 2764-2
3-36
i 2764
3-36
i 2764-3
3-36
M54700P,S
1024-Blt (256x4) Fleld-Programmable ROM with Open-Collector
B
5±50/0
430
60
60
-
16P4
16S1
MM6300
3-5
M54730P,S
256-Blt (32x 8) Field-Programmable
ROM with Open-Collector
B
5±50/0
430
50
60
-
16P4
16S1
MM6330
3-10
M54740AP,S
4096-Bit(1 024X4) Field- Programmable ROM with Open-Collector
B, S
5±50/0
600
55
55
-
18P4
18S1
93452
3-14
M54741 AP, 5
4096-Blt (1024x4) Fleld-ProgrammaB, S
ble ROM with 3-State Outputs
55
55
-
18P4
18S1
93453
3-14
1-2
5±50/0
600
• MITSUBISHI
li"&ELECTRIC
MITSUBISHI LSls
INDEX BY FUNCTION
Type
Circuit function and organization
Electrical characteristics
Supply
Structure voltage 'Typ pwr Max
Max
Min
Package Interchangeable
dISSIfreaccess cycle
(Note 1)
products
(V)
pasion
quency (Note 2)
time
time
(ns)
(mW)
(ns)
(MHz)
Page
.Single-Chip Microcomputers
M68840-XXXP
Single-Chip 4-Bit Microcomputer
with 8-Bit A/D Converter
P,AI,ED -15±10%
500
M68841-XXXSP
Single-Chip 4-Bit Microcomputer
with 8-Blt A/D Converter
P,AI.ED -15±10%
M68842S
MELPS 4 System Evaluation Device
P,AI.ED -15±100/o
Sin~le-ChiP 4-Bit Microcomputer
-
10,us 0.6
42P1
-
4-2
500
-
10,us
0.6
42P4B
-
4-2
500
-
10,us
0.6
64S1
-
4-13
P.AI.ED -15±10%
400
-
10,us
0.6
29P4
-
4-18
-
4-18
M68843-XXXP
Wit
M68844-XXXSP
Single-Chip 4-Bit Microcomputer
with 8-Blt A/D Converter
P.AI.ED -15±10%
400
-
10,us
0.6
40P4B
M68846-XXXSP
Single-Chip 4-Bit Microcomputer
with 8-Blt A/D Converter
P,AI,ED -15±10%
350
-
10,us
0.6
40P4B
-
4-29
M68846-XXXSP
Single-Chip 4-Blt Microcomputer
P.AI.ED -12± 10%
280
-
10,us
0.6
40P4B
-
4-41
M68847-XXXSP
Single-Chip 4-Bit Microcomputer
P.AI,ED -12±10%
10
-
15,us
0.4
40P4B
-
4-53
MS8494-XXXP
Single-Chip 4- Bit CMOS
Microcomputer
C. AI
5± 5 %
5
-
8.8,us 0.455
72P2
-
5-3
MS8496-XXXP
Single-Chip 4-Bit CMOS
Mlcrocom puter
C. AI
5± 5%
5
-
7.7,us
72 P2
-
5-17
M S8497 -XXXP
Single-Chip 4-Blt CMOS
Microcomputer
C, AI
3-5.5%
2
-
15.4,us 0.455
72P2
-
5-32
MSL8048-XXXP
Single-Chip 8-Blt Microcomputer
N. Si.ED 5±10%
325
-
M5L8035LP
MSL8049-XXXP
M5L8049-XXXP-8
M5L8049-XXXP-6
Single-Chip 8-Blt Microcomputer
N, Si.ED
5±10%
325
-
N. SI.ED
5±10%
500
500
500
500
-
Single-Chip 8-Blt Mlcrocorr:puter
500
5()()
-
500
-
8-Blt A/D Converter
M5L8039P-"
M5L8039P-8
M5L8039P-6
Single-Chip 8-Bit Microcomputer
M5L8748S
Single-Chip 8- Bit Microcomputer
with EPROM
N.SI.ED
5±10%
N.SI.ED 5±10%
-
-
4.2
2500
6
40P1
i 8048
6-21
2500
6
40P1
6-21
1360
1875
2500
1360
11
8
6
11
i 8035L
i 8049
-
6-25
1875
8
2500
6
2500
6
40P1
i 8039
40P1
-
6-25
i 8039-6
i 8748
6-29
28P4
ADC0808
8
3
40P1
MC6847-1
8
7
17
40S10
• Microprocessors
M 5L8085AP, S
8-Blt Parallel Microprocessor
M5L80865
16-Blt Parallel Microprocessor
• LS Is for Peripheral Circuits
5+10%
M58990P
M5C6847P-1
8-Bit 8-Channel A-D Converter
C. SI
Video Display Generator
N. SI.ED 5±5%
500
M5L8041A-XXXP
Universal Peripheral Interface
N. SI. ED 5+10%
300
M5L8155P
2048- Bit Static RAlVi Wit h I/O Ports
and Timer (U="L"actlve)
N.SI.ED
5±5%
M5L8156P
2048-Blt Static RAM with I/O Ports
and Timer (CE="H"active)
N.SI.ED
3.58
6
40P1
18041A
8
500
-
-
-
40P1
I 8155
7-25
5±5%
500
-
-
-
40P1
i 8156
7-33
M5L8212P
8-Blt Input/Output Port
B. S
5+5%
450
35u
24P1
i 8212
7
M5L8216P
4-Blt Parallel Bidirectional Bus
Driver (Non Invertl ng)
B. S
5±5%
475
25u
-
-
16P4
18216
7-21
M5L8226P
4-Blt Parallel Bidirectional Bus
Driver (Inverting)
B, S
5±5%
425
25u
-
-
16P4
18226
7-21
50
-
-
-
24P1
i 8243
6
-
-
3
28P4
i 8251A
8-41
2
24Pl
I 8253-5
8
57
40P1
i 8255A-5
8
65
N.Si.ED 5+10%
M5L8243P
Input/Output Expander
M5L8251AP
Programmable Communication
Interface
N.Si.ED 5±5%
300
M5L8253P-5
Programmable Interval Timer
N.Si.ED 5+5%
300
M 5L8255AP- 5
Programmable Peripheral Interface
N.Si,ED 5+5%
250
• MITSUBISHI
"ELECTRIC
17
37
1 -- 3
II
MITSUBISHI LSls
INDEX BY FUNCTION
Electrical characteristics
Type
Circuit function and organization
Supply
Structure
voltage
(Note 1)
(V)
Typ pwr Max.
d,ss,access
pasion
time
ImW)
Ins)
Min
cycle
time
Ins)
Max.
frequency
1M Hz)
Package Interchangeable
(Note 2)
products
Page
.LSls for Peripheral Circuits (Continued)
M5L8257P-5
Programmable DMA Controller
N,Si,ED 5±50/0
300
-
-
3
40P1
i 8257- 5
8-81
M5L8259AP
Programmable I nterrupt Controller
N,Si,ED 5±100/0
275
-
-
-
28P4
i 8259A
8-91
M5L8279P-5
Programmable Keyboard/Display
Interface
N,Si,ED 5±100/0
650
-
-
3
40P1
i 8279- 5
8-105
M5L8282P
8-Bit Latch(Non Inverting)
B, S
5±100/0
500
-
-
-
20P4
i 8282
M5L8283P
8- Bit Latch (I nvertl ng)
B, S
5±100/0
500
-
-
-
20P4
18283
9-35
9-35
M5L8284P
Clock Generator and Driver for
M5L8086S CPU
B, S
5±1 (]l/o
490
-
-
-
18P4
i 8284
9-39
M5L8286P
Octal Bus Transceiver
(Non Inverting)
B, S
5±100/0
560
-
-
-
20P4
i 8286
9-46
M5L8287P
M5L8288P
Octal Bus Transceiver (I nvertlng)
B, S
5±100/0
90
-
-
-
20P4
i 8287
Bus Controller for M 5L8086S CPU
B, S
5±1 (]l/o
800
-
-
-
20P4
i 8288
9-46
9-50
M5W1791-02
Floppy Disk Formatter/Controller
I\LSi ,ED
5±50/0
300
-
-
-
40P1
FD1791-02B
8-117
300
-
-
0.66
28P4
-
10-3
80
-
-
0.17
24Pl
-
10-13
150
-
-
0.17
40S1
-
10-19
16P4
-
11-3
11-3
.Speech Synthesis (PARCOR SYSTEM)
M58817AP
M 5881 8-XXXP
Speech Synthesizer
M58819S
EPROM Interface
128K-Bit Phrase ROM
P,AI,ED -10±10%
P,AI,ED -10±10%
P,AI,ED -10±lOro
-5±50/0
.LSls for Remote-Control Receiver and Transmitter
M50110XP
30-Function Remote-Control
Transmitter
C, AI
2.2-8
-
-
-
-
M50115XP
120-F unction Remote-Control
Transmitter
C, AI
2.2-8
-
-
-
-
18P4
-
M50111XP
120-Functlon Remote-Control
Receiver
C, AI
4.5-8
-
-
-
-
16P4
-
11-9
M50116XP
120-Functlon Remote-Control
Receiver
C, AI
4.5-8
-
-
-
-
18P4
-
11-9
M50117XP
120-F unction Remote- Control
Receiver
C, AI
4.5-8
-
-
-
-
18P4
-
11-9
M58480P
30-F unct ion Remote- Control
Transmitter
C, AI
22-8
-
-
-
-
16P4
-
11-43
M58484P
30-Functlon Remote-Control
Transmitter
C, AI
2.2-8
-
-
-
-
16P4
-
11-43
M58481P
3D-Function Remote-Control
Receiver
C, AI
45-8
-
-
-
-
28P4
-
11-47
M58485P
29-Function Remote-Control
Receiver
C, AI
8-14
-
-
-
-
28P4
-
11-51
M58487AP
24-F unction Remote- Control
Receiver
C, AI
8-14
-
-
-
-
28P4
-
11-65
1.1-1.8
-
-
-
-
8P4
-
11-19
11-18
-
-
-
-
8P4
-
11-19
11-18
-
-
-
-
8P4
-
11-19
1.1-1.8
-
-
-
--
8P4
-
11-19
-
-
-
8P4
-
11-19
11-23
_.
.LSls for Clock Circuits
M50401P
CMOS Analog Clock Circuit
C. Si
M50402P
CMOS Analog Clock Circuit
C, Si
M50403P
CMOS Analog Clock Circuit
C, Si
M50404P
CMOS Analog Clock Circuit
C. Si
M50405P
CMOS Analog Clock Circuit
C, Si
1.1-1.8
-
M58412P
CMOS LCD Digital Alarm Clock
Circuit
C, AI
-1.2
--1.9
-
-
-
-
60P2
-
M58413P
CMOS LCD Digital Alarm Clock
Circuit
C, AI
-1.1
--2
-
-
-
-
60P2
-
11-23
M58435P
CMOS Analog Clock Circuit
1.2-1.9
-
-
-
-
8P4
-
M58437-001 P
CMOS Analog Clock Circuit
C. Si
C. AI
1.1-1.9
-
-
-
-
8P4
-
11-31
11-31
1-4
• MITSUBISHI
"'ELECTRIC
MITSUBISHI LSls
INDEX BY FUNCTION
Type
Circuit function and organization
Structure
(Note 1)
Electrical characteristics
Supply
Max
Min
Package Interchangeable
voltage Typ pwr Max
fredISSIaccess cycle
products
(V)
quency (Note 2)
pasion
time
time
(MHz)
(ns)
(mW)
(ns)
II
Page
.General-Purpose MOS LSls
M50121 P
17-Stage Osclilator/ Divider
C, AI
4.75-8.5
-
-
-
-
BP4
-
M50122P
17-Stage Oscillator/Divider
C, AI
4.75-8.5
-
-
--
-
BP4
-
M50250P
Refrigerator Controller
-
-
-
-
16P4
-
17-Stage Oscillator/DIvider
C. AI
C. AI
7-9
M58478P
4.75-85
-
-
-
-
BP4
-
M58479P
CMOS Counter/Timer
C, AI
7.9-9
-
-
-
-
14P4
-
M58482P
CMOS Counter/Timer
C, AI
3-9
-
-
-
-
14P4
-
M58486AP
Voltage SyntheSIZer
C. AI
11-13
-
-
-
-
42P1
-
Note 1: AI =Alumlnum gate
N=N-channel
B=Bipolar.
P =P-channe!
C=CMOS
S =Schottkey
ED=Enhancement depletion mode.
SI =SlIlcon gate
11-35
11-35
11-15
11-35
11-39
11-39
11-55
FA=FAMOS.
Package code 24 S 1
T
3:
*
Number of pins
Package structure
K=Glass-sealed ceramiC: P=Molded plastic: S=Metal-sealed ceramic
Package outline
1 =DIL Without fin
2=Flat Without fin.
4=DIL without fin (Improved)
10=DIL w/o fin. and w/quartz lid
4B=Shrink DI L without fin
I ndlcates propagation time
• MITSUBISHI
.... ELECTRIC
1-5
MITSUBISHI LSls
INDEX BY FUNCTION
I/O
port
(bits)
Ambient
operating
temp
Ta('C)
Supply
voltage
48
0-55
5
125x 145x 17
12-3
12K
48
0-55
5
125x145x17
12-7
12K
1
(serial)
0-55
12,5,-12
125x145x17
12-11
22
5-40
5, -5
125x145x20
12-19
8K or
16K
-
0-55
5, -5
125x145x25
12-25
16K
24
0-55
5, -5
125x145x20
12-15
Memory capacity
Type
Circuit function and organization
RAM
(bytes)
I
ROM
(bytes)
(V)
Dimensions
(Ixwxh)
Page
(mm)
.Micromputer Systems
PCA8501 G01
PCA8501 G02
MELCS 85/2 Single-Board
Computer
PCA8506
MELCS 85/2 Memory and Parallel
i/O Expa nsion Boa rd
PCA8507
MELCS 85/2 Memory and Serial
I/O Expansion Board
PCA8540 G01
PCA8540 G02
MELCS 82/2 Video Display
Single-Board Computer
1K
256
I
I
4K
4K
• Speech Synthesize Single- Board Computers
PCA7002 G01
PCA7002 G02
MELCS 70/2 Speech Synthesizer
Board
PCA8520 G01
PCA8520 G02
MELCS 85/3 Voice Generating
Single-Board Computer
1-----
-
256
• Microcomputer Support Systems
PCA0803
MELCS 8/2 Program Checker
-
-
-
0-55
5
170x200x27
13-3
PC4000
Debugging Machine
-
-
-
10-40
AC100
364x257x85
13-5
PC7000
Speech Synthesis Evaluation Unit
-
-
-
10-40
AC10C
390x 212x 73
13-9
PC8500
MELCS 85/1 Portable Mlcrocomputer Console
-
-
-
10-40
AC100
350x 370x 140
13-11
PC9000
Cross Assemble Machine
-
-
-
10-40
AC100
500x470x287
13-17
• Dedicated Board
PCA4001
Emulator Boad for M58840, M58841
-
-
-
10-40
13-20
PCA4003
Emulator Board for M58843
-
-
-
10-40
13-22
PCA4004
Emulator Board for M58844
-
-
-
10-40
PCA4005
Emulator Board for M58845
-
-
-
10-40
PCA4011
Emulator Board for M58494
-
-
-
10-40
13-24
Supplied
from
PC4000
210x230x20
13-26
13-28
PCA4012
Emulator Board for M58496
-
-
-
10-40
PCA4014
Emulator Board for M58497
-
-
-
10-40
13-32
PCA8400
Emulator Board for MELPS 8-48
-
-
-
10-40
13-34
PC41 00
M5L8748S Programming Adaptor
-
-
-
10-40
13-30
165x105x37
13-36
• Evaluation Board
PCA4301
Evaluation Board for M5884Q, M58841
-
-
-
0-55
-15
125x110x20
13-37
PCA4303
Evaluation Board for M58843
-
-
--
0-55
-15
125x110x20
13-38
PCA4304
Evaluation Board for M58844
-
-
-
0-55
-15
125x110x20
13-39
PCA4305
Evaluation Board for M58845
-
-
-
0-55
-15
210x230x20
13-40
PCA4101
Evaluation Board for M58494
-
-
-
0-55
5
150x 200x20
13-42
PCA4201
PCA4202
Evaluation Board for M58496
-
-
-
0-55
5
150x 200x20
13-44
Evaluation Board for M58497
-
-
-
5
Evaluation Board for MELPS 8-48
-
-
-
150x 200X 20
150x 58 X 27
13-46
PCA8402
0-55
0--55
1-6
• MITSUBISHI
.... ELECTRIC
5
13-48
MITSUBISHI LSls
INDEX BY TYPE DESIGNATION
Type
Structure
!
I
M50110XP
Function
C, AI
Remo-con
Circuit function
30-function remote-control transmitter
Page
11-3
M50111 XP
C, AI
Remo-con
120-function remote-control receiver
11-9
M50115XP
C, AI
Remo-con
120-function remote-control transmitter
11-3
M50116XP
C, AI
Remo-con
120-function remote-control receiver
11-9
M50117XP
C, AI
Remo-con
M50121 P
C, AI
Counter
M50122P
C, AI
M50250P
C, AI
M50401 P
M50402P
I
120-function remote-control receiver
11-9
17 -stage oscillator / divider
11-35
Counter
17 -stage oscillator/divider
11-35
Counter
Refrige rator counter
11-15
C, AI
Clock
CMOS analog clock circuit
11-19
C, AI
Clock
CMOS analog clock circuit
11-19
M50403P
C, AI
Clock
CMOS analog clock circuit
11-19
M50404P
C, AI
Clock
CMOS analog clock circuit
11-19
M50405P
C, AI
Clock
CMOS analog clock circuit
11-19
B
PROM
B
PROM
B, S
PROM
4096-bit (1.024-wordX4-bit) field-programmable ROM
with open-collector
3-14
B, S
PROM
4096-bit (1024-wordX4-bit) field-programmable ROM
with 3-state
3-14
M58412P
C, AI
Clock
CMOS LCD degital alarm clock circuit
11-23
M58413P
C, AI
Clock
CMOS LCD digital alarm clock circuit
11-23
M58435P
C, Si
Clock
CMOS analog clock circuit
11-31
M58437-001 P
C, AI
Clock
CMOS analog clock circuit
11-31
M58478P
C, AI
Counter
17 -stage osciliatGl / divider
11-35
M58479P
C, AI
Counter
CMOS counter/timer
11-39
M58480P
C, AI
Reme-con
30-function remote-control transmitter
11-43
M58481 P
C, AI
Remo-con
30-function remote-contr01 receiver
11-47
M58482P
C, AI
Counter
CMOS counter/timer
11-39
M58484P
C, AI
Remo-con
30-function remote-control transmitter
11-43
M58485P
C, AI
Remo-con
29-function remote-control receiver
11-51
M58486AP
C, AI
Counter
Voltage synthesizer
11-55
M58487AP
C, AI
Remo-con
22-function remote-control receiver
11-65
M58494-XXXP
C, AI
CPU
Single-chip 4-bit CMOS microcomputer
5-3
M58496-XXXP
C, AI
CPU
Single-chip 4-bit CMOS microcomputer
5-17
M58497-XXXP
C, AI
CPU
Single-chip 4-bit CMOS microcomputer
5-32
M58653P
p, AI
EEPROM
700-bit (50-word by 14-bit) electrically alterable ROM
3-18
N, Si ED
RAM
16384-bit (2048-word X 8-bit) static RAM
2-3
M54700P
M54700S
M54730P
~---------------
M54730S
M54740AP
M54740AS
M54741 AP
M54741 AS
M58725P
+
1024-bit (256-wordX4-bit) field-programmable ROM
with open- collector
3-5
256-bit (32-wo'dXB-bitJ '"Id-pm9"mm,bl, RO'
3-10
with open- collector
M58725P-15
M58735-XXXP
N, Si
ROM
32768-blt (4096-wordX8-bit) mask-programmable ROM
3-22
M58817AP
p, AI. ED
Speech
Speech synthesizer
10-3
M58818-XXXP
p, AI, ED
Speech
131072-bit phrase ROM
10--13
M58819S
p, AI, ED
Speech
EPROM interface
10-19
M58840-XXXP
p, AI, ED
CPU
Single-chip 4-bit microcomputer with 8-bit A/Dconverter
4-2
M58841-XXXSP
p, AI. ED
CPU
Single-chip 4-bit microcomputer with 8-bit A/D converter
4-2
M58842S
P, AI, ED
CPU
MELPS 4-system evaluation device
4-13
M58843-XXXP
p, AI, ED
CPU
Single-chip 4-bit microcomputer with 8-bit A/D converter
4-18
4-18
~-
M58844-XXXSP
p, AI, ED
CPU
Single-chip 4-bit microcomputer with 8-bit A/D converter
M58845-XXXSP
P, AI, ED
CPU
I Single-chip 4-bit microcomputer with 8-bit A/D converter
M58846-XXXSP
p, AI. ED
CPU
Single-chip 4-bit microcomputer
4-41
p, AI. ED
CPU
Single-chip 4-bit microcomputer
4-53
M58847-XXXSP
I
• MITSUBISHI
.... ELECTRIC
4-29
1-7
II
MITSUBISHI LSls
INDEX BY TYPE DESIGNATION
Type
M&S9S1 P-30
M&S9S1 P-4&
Structure
C. Si
Circuit function
Function
RAM
4096-bit (1024-wordX4-bit) CMOS static RAM
Page
2-9
M&S990P
C. Si
I/O
8-bit 8-channel A/D converter
8-3
M&C6S47P-1
N. Si. ED
I/O
Video display generator
8-7
M&G1400P
p. AI
EEPROM
1400-bit (1 OO-wordX 14-bit) electrically alterable ROM
3-24
N. Si
RAM
16384-bit (16384-word X 1-bit) dynamic RAM
2-13
N. Si
RAM
65536-bit (65536-word X 1-bit) dy namic RAM
Pin 1 (RFE) function
2-25
N. Si
RAM
65536-bit (65536-word X 1-bit) dynamic RAM
Pin 1 no connection
2-41
N. Si
RAM
65536-bit (65536-wordX 1-bit) dynamic RAM
Pin 1 (REF) function
2-55
N. Si
RAM
65536-bit (65536-wordX 1-bit) dynamic RAM
Pin 1 no connection
2-71
N. Si. ED
RAM
4096-bit (1024-wordX4-bit) static RAM
2-85
N. Si. FA
EPROM
16384-bit (2048-wordX8-bit) erasable and electrically
repJogrammable ROM
3-28
N. Si. FA
EPROM
32768-bit (4096-wordX8-bit) erasable and electrically
reprogram mabie ROM
3-32
N. Si. FA
EPROM
65536-bit (8192-wordX8-bit) erasable and electrically
reprogram mabie ROM
3-36
N. Si. ED
CPU
Single-chip 8-bit microcomputer
6-25
M&K4116P-2
M&K4116P-3
M6K4164P-1 &
M&K4164P-20
M&K4164NP-1 &
M&K.4164NP-20
M&K4164S-1 &
M&K4184S-20
M&K4184NS-16
M5K4184NS-20
M&L2114LP
M&L2114LP-2
M&L2114LP-3
M&L2718K
M&L2718K-8&
M&L2732K
M&L2732K-8
M&L2784K
M&L2784K-2
M&L2784'K-3
M&LS039P-8
M&LS039P-S
M&LS039·P-11
M&LS041 A-XXXP
N. Si. ED
I/O
Universal peripheral interface
8-17
M&LS04S-XXXP
N. Si. ED
CPU
Single-chip 8-bit microcomputer
6-21
N. Si. ED
CPU
Single-chip 8-bit microcomputer
6-25
N. Si. ED
CPU
8-bit parallel CPU
7-3
M&LSOS8S
N. Si. ED
CPU
16-bit parallel microprocessor
9-3
M&LS1&&P
N. Si. ED
I/O
2048-bit static RAM with I/O ports and timer (CE=low active)
7-25
M&LS1 &8P
N. Si. ED
I/O
2048-bit static RAM with I/O ports and timer (CE= high active)
7-33
M&LS212P
B. S
I/O
8-bit input/ output port
7-17
M&LS049-XXXP
M6LS049-XXXP-8
M&LS049-XXXP-S
M&LSOS&AP
M&LSOS&AS
M&LS218P
B. S
I/O
4-bit parallel bidirectional bus driver (non invert outputs)
7-21
M&LS228P
B. S
I/O
4-bit parallel bidirectional bus driver (invert outputs)
7-21
M&LS243P
N. Si. ED
I/O
Input/ output expander
6-37
M&LS2&1AP
N. Si. ED
I/O
Programmable communication interface
8-41
M&LS2&3P-5
N. Si. ED
I/O
Programmable interval timer
8-57
M&LS266AP-5
N. Si. ED
I/O
Programmable peripheral interface
8-65
M6LS267P-6
N. Si. ED
I/O
Programmable DMA controller
8-81
M6LS269AP
N. Si. ED
I/O
Programmable interrupt controller
8-91
8-105
M&LS279P-6
N. Si. ED
I/O
Programmable keyboard/ display interface
M5LS2S2P
B. S
I/O
8-bit latch (non inverting)
9-35
M6LS2S3P
B. S
I/O
8-bit latch (inverting)
9-35
M&LS2S4P
B. S
I/O
Clock generator and driver for 8086. 8088. 8089 processors
9-39
M6LS21i8P
B. S
I/O
Octal bl,Js transceiver (non inverting)
9-46
1-8
• MITSUBISHI
"ELECTRIC
MITSUBISHI LSls
INDEX BY TYPE DESIGNATION
Type
Structure
Function
Circuit function
Page
9-46
B, S
I/O
M6L8288P
B, S
I/O
Bus controller for 8086, 8088, 8089 processors
9-50
M6L8748S
N, SI, ED
I/O
Single-chip 8-bit microcomputer with EPROM
6-29
N, Si, ED
RAM
4096-bit (4096-word X 1 -bit) static RAM
2-93
N, Si, ED
I/O
Floppy disk formatter/controller
8-117
M6L8287P
Octal bus transceiver (inverting)
M6T4044P-20
M5T4044P-30
M6T4044P-45
M6W1791-02P
Note 1 . AI=Aluminum gate,
B= Bipolar,
C = CMOS,
ED = Enhancement depletion mode.
FA= FAMOS.
N=N-channel.
P=P-channel.
S=Schottkey.
Si=Silicon gate
2. CPU=Central processing unit.
I/O=input/output device.
PROM=Programmable read-only memory.
RAM = Random-access memory.
Remo-con = Remote controller.
ROM = Read-only memory. Speech=Speech Synthesizer
Type
PC4000
Function
Page
Debugging Machine
13-5
PC4100
M5L8748S programming adaptor
13-36
PC7000
Speech synthesis evaluation unit
13-9
PC8500
MELCS 85/1 portable microcomputer console
13-11
PC9000
Cross assembler machine
13-17
PCA4001
MELPS 4 dedicated board
13-20
PCA4003
MELPS 4 dedicated board
13-22
PCA4004
MELPS 4 dedicated board
13-24
PCA4005
MELPS 4 dedicated board
13-26
PCA4011
MELPS 41 dedicated board
13-28
13-30
PCA4012
MELPS 42 dedicated board
PCA4014
MELPS 42 dedicated board
13-32
PCA4101
MELPS 41 evaluation board
13-42
PCA4201
MELPS 42 evaluation board
13-44
PCA4202
MELPS 42 evaluation board
13-46
PCA4301
MELPS 4 dedicated board
13-37
PCA4303
MELPS 4 evaluation board
13-38
PCA4304
MELPS 4 evaluation board
13-39
PCA4305
MELPS 4 evaluation board
13-40
MELCS 70/2 speech synthesizer single-board computer
12-25
PCA7002G01
PCA7002G02
PCA8400
MELPS 8-48 dedicated board
13-34
PCA8402
MELPS 8-48 evaluation board
13-48
MELCS 85/2 single-board computer
12-3
PCA8501G01
PCA8501G02
PCA8506
MELCS 85/2 memory and parallel I/O expansion board
12-7
PCA8507
MELCS 85/2 memory and serial I/O expansion board
12-11
MELCS 85/3 voice generating single-board computer
12-15
MELCS 85/2 color TV display single-board computer
12-19
PCA8520G01
PCA8520G02
PCA8540G01
PCA8540G02
• MITSUBISHI
.... ELECTRIC
1-9
MITSUBISHI LSls
GUIDE TO INTERCHANGEABI!LITY
Functlon
Mitsubishi
Advanced
Micro
Electric
Devices
American
Microsystems
Fairchild
Fujitsu
Hitachi
Intel
Semiconductor
MB2114A-20L
M5L2114LP-2
HM472114A-2
P2114L-2
M5L2114LP-3
HM472114A-3
P2114L-3
~
M5L2114LP
HM472114A-4
P2114L
0:
M5T4044P-20
MB8144EL
M5T4044P-30
MB8144NL
Z
0
~
(/)
FINAL
a:
1-,
z
a:
I--
'\
UJ
<:J
h
,
6
g:
u
r
PURCHASING SPEC S
Il
Az
(/)
~
=lIN-LINE
L
EVALUATION
;lIN-LINE
EVALUATION
0
u
~
f-
r-.",
Z
Q
(/)
.I
t
f--
ARRANGE FOR )
.\
TOOLS
"
SPECS.
a:
r
II~
PRODUCT INSPECT rON
'-,0
'\,. MANUFACTURE
r
( TEST PLANNING
INCOMING MATERIALS
u
r"o
)
,
\N SUBCONTRACTING FAC"foRIES
V
PURCHASING SPE CS.
If PLANNING OF )
PJ>.
STOREROOM
SHIPPING SPECS.
\'STANDARDS
I(
(
PRODUCT SPECS
. tREGIS1~A TIO
1
,-...
MAIN
STANDARDS
I'DEVELOPMENT"\
\!,LANNING
..J
(PRE-PRODUCTION ORDER)
(
MANUFUCTURING
CONTROL
DIV,
QUALITY
ASSURANCE
DIV
QUALITY
CONTROL
DIV
PURCHASING SPEC S.
r,
l
l
WAFER AND
ASSEMBLY
DIV
ENGINEERING
PRODUCTION PLANNING
MARKET
f-
Z
0
~
a:
0
~
INSPECTION
INSTRUCTIONS
~
Z
0
f=
0
::2:
SHIPPING SPECS
go:
INSPECTION
0
]
INSTRUCTIONS
REPORT
MAIN DIVISION
1-40
o
CONCERNED DIVISION
-
FLOW OF MATERIALS, PARTS, AND PRODUCTS
• MITSUBISHI
.... ELECTRIC
-
FLOW OF INFORMATION
MITSUBISHI LSls
QUALITY ASSURANCE AND RELIABILITY TESTING
4. TYPICAL RESULTS OF RELIABILITY TESTS AND
FAILURE ANALYSES
4.1 Results of Reliability Test
~--~II
Formerly, sufficient reliability for memory MOS LSls was
obtained by using metal-sealed ceramic packages, but with
the development of high-reliability plastic molding technology, production has been shifted to plastic molded
memory MOS LSls.
The following tests are performed:
1. Operating life test: Durability is tested at high tempera-
GND
ture under operating state conditions by applying clock
pulse inputs as shown in Fig. 2.
2. DC biased test: Durability is tested at high temperature
Fig. 3 DC biased test procedure (for M5L2114 LP 4K-bit
static RAM)
biasing DC Voltage, as shown in Fig. 3.
3. High temperature storage: The durability of devices
stored at high temperatures is tested.
Typical results of memory MOS LSI life tests are shown
in Table 3. The failure rate computed from this reliability
data using an appropriate acceleration factor is 0.1 F IT or
less (1 FIT=10-9/hour) per bit, about the same as, or less
than, for core memories.
PIN CONFIGURATION (TOP VIEW)
vss DIN R/W RAS Ao A2 A, Voo
DIN =DATA IN
RAS -ROW ADDRESS STROBE
CAS'-COLUMN ADDRESS STROBE
RjW =READjWRITE
DOUT=DATA OUT
OPERATING LIFE TEST CONDITIONS
600ns
200ns
2S0ns
CAS
Ao-As
RjW
All addresses including the Ao to A6 row addresses and
column addresses are cycled through in binary sequence
such that the entire 16K bits are accessed,
Vss =-S.SV. VSS =VIL= OV. Voo=13,2V
Vee =S,SV. VIH =S.OV
Fig. 2 Operating life test procedure (for M5 K4116 P, S
16K-bit dynamic RAM)
• MITSUBISHI
"'ELECTRIC
1-41
MITSUBISHI LSls
QUALITY ASSURANCE AND RELIABIL TY TESTIN'G
Table 3 Examples of Endurance Test Results
Type No.
16- pin metal-seald
ceramic OIL
M5K41645
M5K4116P
16-pin plastic - molded
OIL
24-pin plastic- molded
DIL
M58725P
M5L2114LP
18- pin plastic - molded
DIL
18- pin plastic - molded
DIL
M58981 P
M5L 5101 LP
M5L2716K
M5L2732K
Number
of
samples
Test category
Package
22- pin plastic - molded
DIL
24-pin metal-sealed ceramic
DIL with quartz lid
24-pin metal-sealed ceramic
DIL With quartz lid
Oomponent
hours
Number
of
failures
Operating life
125'0
350
350,000
1
High-temperature storage
150'0
150
150,000
0
0
Operating life
125'0
334
334,000
DO biased
125'0
88
132,000
0
High-temperature storage
150'0
132
132,000
0
Operating life
125'0
114
114,000
0
High-temperature storage
150'0
38
38,000
0
Operating life
125'0
176
198,000
0
DO biased
125'0
22
22,000
0
High-temperature storage
150'0
88
132,000
0
Operating life
125'0
110
110,000
0
DO biased
125'0
22
22,000
0
High-temperature storage
150'0
44
66,000
0
Operating life
125'0
444
544,000
1
DO biased
125'0
94
94,000
0
High-temperature storage
150'0
94
94,000
0
Operating life
125'0
274
362,000
0
High-temperature storage
150'0
66
88,000
0
OP.erating life
125'0
264
308,000
0
High-temperature storage
150'0
44
66,000
0
Remarks
Functional failure
Functional failure
Table 4 Examples of Environmental Test Results
T est category
c
-~
<0 c
Test conditions
Soldering heat
260'C,
Type No.
lOs
Thermal shock
- 40°C-125°C, 10min/cycle, 15 cycles
M5L2114LP
'Temperature cycling
- 65°C-150°C, 1h/cycle, 100 cycles
M5L5101LP
-
Soldering heat
260'C,
~~
Thermal shock
- 55°C-125°C, 1Omin/cycle, 15 cycles
Temperature cycling
- 65°C-150°C, 1h/cycle, 100 cycles
Eg>
Temperature cycling
_c
2ffi
1-42
-
Number of
failures
M5K4116P
~.~
E2
Number of
samples
330
0
M5K41645
1,000
0
M5K4116P
M5L2114LP
M5L5101 LP
1,500
0
M5K41645
1,000
0
lOs
65°C-150°C 1h/cycle, 10 cycles
Shock
1,500G,0.5ms in Xl ,Yl,and Zl directions, 3 times
Vibration
20G, 20-2000Hz, in X, Y, and Z directions
Constant acceleration
30,000G, Y 1 direction for 1min
• MITSUBISHI
.... ELECTRIC
Remarks
MITSUBISHI LSls
QUALITY ASSURANCE AND RELIABILITY TESTING
II
5. CONCLUSION
Mitsubishi Electric's Quality Assurance System is baing
expanded to provide stronger emphasis on the following
points:
1. Establishment of quality and reliability levels that
satisfy customers' requirements.
2. Expansion of the reliability tests of wafers and assembly
processes for better evaluation, and standardization of
circuit and design rules.
3. Establishment of procedures for speeding up the introduction of new technology and improved methods that
raise reliability and to improve the accelerated life tests
for better failure analysis.
4. Establishment of a system for collecting data on failures
in the field, which will then be analyzed to develop
improved methods for increasing reliability.
We welcome and appreciate the cooperation of our
customers in developing design specifications, establ ish ing
quality levels, controlling incoming inspections, developing
assembly and adjusting processes and collecting field data.
Mitsubishi is anxious to work with its customers to develop
ICs of increased reliability that meet their requirements.
• MITSUBISHI
.... ELECTRIC
1-43
MITSUBISHI LSls
PRECAUTIONS IN HANDLING MOS ICs
A MOS transistor has a very thin oxide insulator under the
gate electrode on the silicon substrate. It is operated by
altering the conductance (gm) between source and drain to
control mobile charges in the channel formed by the
applied gate voltage.
If a high voltage were applied to a gate terminal, the
insulator-film under the gate electrode could be destroyed,
and all Mitsubishi MOS IC/lSls contain internal protection
circuits at each input terminal to prevent this. It is inherently necessary to apply reverse bias to the P-N junctions of a
MOS IC/lSI.
Under certain conditions, however, it may be impossible
to completely avoid destruction of the thin insulator-film
due to the application of unexpected Iy high voltage or
thermal destruction due to excessive current from a
forward biased P-N junction. The following recommendations should be followed in handling MOS devices.
1. KEEPING VOLTAGE AND CURRENT TO EACH
TERMINAL BELOW MAXIMUM RATINGS
1. The recommended ranges of operating conditions
provide adequate safety margins. Operating within these
limits will assure maximum equipment performance and
quality.
2. Forward bias should not be applied to any terminal since
excessive current may cause thermal destruction.
3. Output terminals should not be connected directly to
the power supply. Short-circuiting of a terminal to a
power supply having low impedance may cause burn-out
of the internal leads or thermal destruction due to
excessive current.
2. KEEPING ALL TERMINALS AT THE SAME
POTENTIAL DURING TRANSPORT AND
STORAGE
When MOS IC/lSls are not in use, both input and output
terminals can be in a very high impedance state so that they
are easily subjected to electrostatic induction from AC
fields of the surrounding space or from charged objects
in their vicinity. For this reason, MOS IC/lSls should be
protected from electrostatic charges while being transported
and stored by conductive rubber foam, aluminum foil,
shielded boxes or other protective precautions.
3. KEEPING ELECTRICAL EQUIPMENT, WORK
TABLES AND OPERATING PERSONNEL AT
THE SAME POTENTIAL
1. All electric equipment, work table surfaces and operat-
1-44
ing personnel should be grounded. Work tables should
be covered with copper or alum inum plates of good
conductivity, and grounded. One method of grounding
personnel, after making sure that there is no potential
difference with electrical equipment, is by the use of a
wristwatch metallic ring, etc. attached around the wrist
and grounded in series with a 1M
resistor. Be sure that
the grounding meets national regulations on personnel
safety.
2. Current leakage from electric equipment must be
prevented not only for personnel safety, but also to
avert the destruction of MOS IC/lSls, as described
above. Items such as testers, curve-tracers and synchroscopes must be checked for current leakage before being
grounded.
n
4. PRECAUTIONS FOR MOUNTING OF MOS
IC/LSls
1. The printed wiring lines to input and output terminals
of MOS IC/lSls should not be close to or parallel to
high-voltage or high-power signal lines. Turning power
on while the device is short-circuited, either by a solder
bridge made during assembly or by a probe during
adjusting and testing, may cause maximum ratings to be
exceeded, which may result in the destruction of the
device.
2. When inputloutput, or input andlor output, terminals
of MOS le/lSls (now open-circuits) are connected,
we must consider the possibility of current leakage and
take precautions similar to §2 above. To reduce such
undesirable trouble, it is recommended that an interface
circuit be inserted at the input or output terminal, or a
resistor with a resistance that does not exceed the
output driving capability of the MOS IC/lSI be inserted
between the power supply and the ground.
3. A filter circuit should be inserted in the AC power
supply line to absorb surges which can frequently be
strong enough to destroy aMOS IC/lSI.
4. Terminal connections should be made as described in the
catalog while being careful to meet specifications.
5. Ungrounded metal plates should not be placed near
input or output terminals of any MOS IC/lSls, since
destruction of the insulation may result if they become
electrostatically charged.
6. Equipment cases should provide shielding from electrostatic charges for more reliable operation. When a plastic
case is used, it is desirable to coat the inside of the case
with conductive paint and to ground it. This is considered
necessary even for battery-operated equipment.
• MITSUBISHI
r..ELECTRIC
RANDOM-ACCESS MEMORIES
MITSUBISHI LSls
M58725P, P-15
16 384-BIT(2048-WORD BY 8-BIT) STATIC RAM
DESCRIPTION
This is a family of 2048-word by 8-bit static RAMs, fabricated with the N-channel silicon-gate MOS process and
designed for simple interfacing. These devices operate
on a single 5V supply, as does TTL, and are directly TTL-
PIN CONFIGURATION (TOP VIEW)
As
A9
compatible.
The input and output terminals are common, and an
OE terminal is provided.
ture.
S
controls the power-down fea-
}ADDRESS
INPUTS
<--W
ADDRESS
INPUTS
~
FEATURES
1]
• Fast access time:
M58725P
M58725 P-15
II
Vee (5V)
WRITE CONTROL INPUT
<--OE
OUTPUT
ENABLE INPUT
<-- A10
ADDRESS
INPUT
<--5
CHIP SELECT
INPUT
17
200ns (max)
150ns (max)
• Low power dissipation:
Active:
Stand by:
DATA
INPUTS/
OUTPUTS
DQl
-.... DO")
DO, ....
DQ6
250mW (typ)
DATA
INPUTS/
OUTPUTS
DOs
25mW (typ)
(OV) GND
D04
• Power down by S
• Single 5V supply voltage (± 10% tolerance)
• Requires neither external clock nor refreshing
Outline 24P1
• All inputs and outputs are directly TTL compatible
During a read cycle, when a location is designated by
• All outputs are three-state, with OR-tie capability
• Easy memory expansion by chip-select (5) input
.Common data DO terminals.
.Same pin configuration as M5L2716K 16 384-bit EPROM
APPLICATION
address signals Ao"'AlO the OE signal is kept low to keep
the DO terminals in the output mode, signal W goes high,
and the data of the designated address is available at the
I/O terminals.
When signal S is high, the chip is in the non-selectable
state, disabling both reading and writing. In this case the
output is in the floating (h igh-impedance) state, useful for
• Small-capacity memory units
FUNCTION
These devices provide common data input and output
terminals. During a write cycle, when a location is designated by address signals Ao"'AlO the OE signal is kept high
to keep the DO terminals in the input mode, signal W goes
low, and the data of the DO signal at that time is written.
OR-ties with other output terminals.
Signal S controls the power down feature. When
S
goes high power dissipation is reduced to 1/10 of active
power. The access time from
access time.
5 is
equivalent to the address
BLOCK DIAGRAM
IOUTPUT
ENABLE INPUT
)
a:
w
LL
128
2048-WORDx8-BIT
(128 ROWSx
128 COLUMNS)
-'
~
«
w
Vl
~
DATA
INPUTS/OUTPUTS
ADDRESS INPUTS
16
CHIP SELECT INPUT
WRITE CONTROL
INPUT
• MITSUBISHI
.... ELECTRIC
2-3
MITSUBISHI LSls
M58725P, P-15
16 384-BIT(2048-WORD BY 8-BIT) STATIC RAM
FUNCTION TABLE
S
OE
W
DQ,-DQs
Mode
H
X
X
Hi-Z
Deselect
L
X
L
DIN
Write
L
L
H
DOUT
Read
L
H
H
Hi-Z
-
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Vee
Supply voltage
VI
Input voltage
Vo
Output voltage
Test conditions
Unit
Limits
-0.5-7
With respect to GND
Pd
Maximum power dissipation
Topr
Operating free-air ambient temperature range
Tstg
Storage temperature range
Ta=2S"C
V
-0.S-7
V
-0.5-7
V
1000
mW
0-70
"C
-6S-1S0
RECOMMENDED OPERATING CONDITIONS
"C
(Ta=0-70"C unless otherwise noted.)
Limits
Unit
Parameter
Symbol
Min
Nom
Max
S .S
5
V
Supply voltage
4.5
VIL
Low-level input voltage
-1
0.8
V
VIH
High-level input voltage
2
6
V
Vee
-~
ELECTRICAL CHARACTERISTICS
(Ta=0-70"C, Vee=5V+ 10%, unlessotherwisenoted)
Limits
Symbol
Parameter
Unit
Test conditions
Min
Typ
Max
VIH
High-level input voltage
2
6
V
VIL
Low-level input voltage
-1
0.8
V
VOH
High-level output voltage
IOH=-lmA, Vee=4.SV
VOL
Low-level output voltage
IOL=3.2mA
0.4
V
II
I nput current
VI=O-S.SV
10
J..I.A
IOZH
Off-state high-level output current
VI(S)=2V, Vo=2 .4V -Vee
10
J..I.A
IOZL
Off-state
-10
J..I.A
Icc,
Supply current from Vee
lee2
10w~level
output current
2.4
V
VI(S)=2V, VO=0.4V
VI=S.SV, VI(S)=0.8V,
Ta=2S"C
outputs open
Ta=O"C
VI=S.SV, VI(S)=2V
Ta=2S"C
outputs open
Ta=70"C
80
mA
90
mA
S
10
mA
7
15
mA
50
Stand by cu rrent
Ci
Input capacitance, all inputs
VI=GND, Vi=25mVrms, f=lMHz
3
5
pF
Co
Output capacitance
Vo=GND, Vo=25mVrms, f=lMHz
5
8
pF
Note 1: Current flowing into an I C is positive, out is negative.
2-4
• MITSUBISHI
;"'ELECTRIC
MITSUBISHI LSls
MS8725P, P-15
16384·BIT (2048.WORD BY 8·BIT) STATIC RAM
SWITCHING CHARACTERISTICS (For Read Cycle)
(Ta=0-70°C, Vcc=5V ± 10%, unless otherwise noted)
M58725P-15
Symbol
M58725P
Limits
Limits
Parameter
·Min
Typ
Max
Min
Typ
Unit
Max
tc (R)
Read cycle time
ta (A)
Address access time
150
200
ta (5)
Chip select access time
150
200
ns
ta(OE)
Output enable access time
50
60
ns
tv (A)
Data valid time after address
tpXZ(S)
Output disable time after ch'ip select
tpZX(S)
Output active time after chip select
10
20
tpu
Power up time after chip selection
0
0
tpD
Power down time after chip deselect ion
200
150
ns
ns
20
20
60
50
ns
ns
ns
80
60
TIMING REQUIREMENTS (For Write Cycle)
ns
(Ta=0-70°C, Vcc=5V±10%, unlessotherwisenoted)
M58725P-15
Symbol
ns
M58725P
Limits
Parameter
Min
Typ
Limits
Max
Min
Typ
Unit
Max
tC(W)
Write cycle time
150
200
ns
tsu(S)
Chip select setup time
100
120
ns
tsu (A)
Address setup time
20
20
ns
tw (W)
Write pulse width
80
100
ns
twr
Write recovery time
10
10
ns
tsu (OE)
Output enable setup time
40
40
ns
tsu (D)
Data setup time
60
60
ns
th (D)
Data hold time
10
10
tpXZ(OE)
Output disable time after output enable
40
40
ns
tpXZ(W)
Output disable time after write enable
40
40
ns
• MITSUBISHI
.... ELECTRIC
ns
2-5
MITSUBISHI LSls
M58725P, P-15
16 384-BIT (2048-WORD BY8-BIT) STATIC RAM
TIMING DIAGRAMS
Read Cycle 1
(Note 21
to
(R)
Ao -AlO
ta
ta
tv
DO
(DATA OUTPUTSI
(OE)
(A)
(A)
PREVIOUS DATA VALID
DATA VALID
W; high level
S ; low level
Read Cycle 2
to
(R)
\
II
r\
/
ta (S)
nl
DO
(DATA OUTPUTSI
f
ICC
\'
NOT
VALID / \
DATA VALID
tPD
leOl
\
1\
W; high level
BE ; low level
2-6
R
• MITSUBISHI
..... ELECTRIC
MITSUBISHI LSls
MS8725P, P-15
16 384-BIT (2048-WORD BY 8-BIT) STATIC RAM
Write Cycle (W Control Mode)
tc
(w)
Ao -AlO
tsu (s)
S
tw(W)
tsu (A)
w
tsu (D)
DO (NOTE 4)
(OAT A INPUTS) - - - - - - - - + - - - - - - {
DO
(OAT A OUTPUTS)
Write Cycle 2
DATA IN STABLE
»»»»»»);
(S Control Mode)
tc
(W)
AO -AlO
tsu (s)
twr
tw(w)
w
tsu (D)
DO
-r__-+-___
(NOTE__
4)_ _ _ _ _ _ _
~
(DATA INPUTS)
DATA IN STABLE
tpzx( S) ---;;*--+~-~1
DO
(NOTE~5~)_ _ _ _ _ _ _ _ _~~_+4_~~-----------------------
(DATA OUTPUTS)
OE = low level
Note 2. Testconditions
Input pulse level
Input pulse rise time
Input pulse fall time
Reference level
Load
O.4-2.4V
lOns
10ns
1 .5 V
lTTL, CL
Note 3. Either the high or low state is possible.
4. When the DO pin is in the output state, a reverse phase signal should not be
applied externally.
5 When the falling edge of W is simultaneous to or prior to the falling edge of S
the output is maintained in the high·impedance state.
= 100pF
• MITSUBISHI
;"ELECTRIC
2-7
MITSUBISHI LSls
M58725P,P-15
16384-BIT (2048-WORD BY 8-BIT) STATIC RAM
TYPICAL CHARACTERISTICS
NORMALIZED ACCESS TIME VS.
AMBIENT TEMPERATURE
NORMALIZED ACCESS TIME VS.
OUTPUT LOAD CAPACITANCE
I
I
Vcc=4.S V
VCC=4.S V
1.1
w
0
:;;;
f=
~
~ 1.0
/
(/)
~
V
u
u
0.8
~
/
/
w
u
u
<1:
~
1.0
<1:
:;;;
a::
~ 0.9
20
40
60
80
E
VCC=14.SV
...J
Ta=2S"C
~
a::
a::
::J
/
/
u
f-
::J
10
o
52
0.
10
Z
w
a::
a::
f-
::J
~
o
S
W
~
1\
i
LJ
0.6
0.8
HIGH·LEVEL OUTPUT VOLTAGE VOH (V)
VOL (V)
SUPPLY CURRENT VS.
AMBIENT TEMPERATURE
-S
-s
'"0
60
ICCI
80
0
.9
60
f-
40
~
~
a::
a::
--"-
-
ICCI
40
::J
U
::J
~
0
0..
0..
20
::J
Vl
ICC2
i7i
4.S
S .s
S.o
SUPPLY VOLTAGE VCC
2-8
Vcc=S.sv
.9
a::
a::
~
1
~
Ta=2S'C
- - t w r
R/W
tsu(es)
tSU(DAl
1/01- 1/ 0 4
DATA IN VALID
(INPUT MODE)
tPXZ(WR)
1/01- 1/ 0 4
DATA OUT INVALID
(DATA OUTPUTS)
Note 2: Hatching indicates the state is unknown
• MITSUBISHI
"'ELECTRIC
2-11
MITSUBISHI LSls
.M58981 P-30, P-45
4096-BIT (1024-WORD BY 4-BIT) CMOS STATIC RAM
POWER-DOWN OPERATION
Electrical Characteristics
(Ta=O-70·C. unless otherwise noted)
Limits
Parameter
Symbol
Test conditions
VCC(PO)
Power-down supply voltage
VI(as)
Power - down chip select input voltage
Min
VI (es)=Vee
2
2. 2V;;;; Vee(po);;;; Vee
2.2
Power-down supply current from
Vee
Vee=2V, all inputs=2V
(Ta=O-70·C.
Vee=5V ±10%. unless otherwise noted)
Limits
Symbol
Parameter
Min
tSU(PD)
Power-down setup time
t R(PD)
Power -down recovery time
Typ
Unit
Max
0
ns
tC(RD)
ns
Timing Diagram
Vee-----~
2.2V
2-12
• MITSUBISHI
"ELECTRIC
Unit
V
V
V
15
Note 3 : Current flowing Into an IC IS positive; out IS negative.
Timing Requirements
Max
Vee(po)
2 V;;;; Vee(PD);;;;2. 2V
lee(po)
Typ
/-LA
MITSUBISHI LSls
MSK4116P-2, P-3
16 384-BIT (16 384-WORD BY I-BIT) DYNAMIC RAM
DESCRIPTION
PIN CONFIGURATION (TOP VIEW)
This is a family of 16 384-word by 1-bit dynamic RAMs,
fabricated with the N-channel silicon-gate MOS process, and
is ideal for large-capacity memory systems where high
speed, low power dissipation, and low costs are essential.
The use of double-layer poly-silicon process technology and
a single-transistor dynamic storage cell provide high circuit
density at reduced costs, and the use of dynamic circuitry
including sense amplifiers assures low power dissipation.
Multiplexed address inputs permit both a reduction in pins
to the standard 16-pin package configuration and an increase in system densities.
( -5V)
VBB
Vss
(OV)
COLUMN ADDRESS
STROBE INPUT
DATA INPUT
READ/WRITE
CONTROL INPUT
II
14 -+DOUT DATA OUTPUT
ROW ADDRESS
STROBE INPUT
ADDRESS INPUTS
ADDRESS INPUTS
(12V)
VOD
Vee
(5V)
FEATURES
•
Performance ranges
Type name
Outline 16P1
Access time
(max)
(ns)
Cycle time
(min)
(ns)
Power dissipation
(typ)
(mW)
150
320
375
330
280
M5K 4116 P-2
M5K 4116P-3
200
•
Interchangeable with Mostek's MK4116 in both electrical
characteristics and pin configuration
APPLICATION
•
Standard 16-pin package
•
Voltage range on all power supplies
•
Main memory unit for computers
FUNCTION
(Voo, Vee, VBB):
±10%
•
Low standby power dissipation:
19.8mW (max)
•
Low operating power dissipation: 462mW (max)
•
Unlatched output enables two-dimensional chip selec-
The M5K4116P provide, in addition to normal read, write,
and read-modify-write operations, a number of other
functions, e.g., page mode, RAS-only refresh, and delayedwrite. The input conditions for each are shown below.
tion and extended page boundary
•
•
Inputs
Early-write operation gives common I/O capability
Operation
•
RAS
Read-modify-write, RAS-only refresh, and page-mode
capabilities
All input terminals have low input capacitance and are
directly TTL-compatible
•
Output is three-state and directly TTL-compatible
•
128 refresh cycles
--
CAS
R W
Output
Re-
Row Columr
D,N
Read
ACT
ACT
NAC
DNC
APD
APD
VLD
YE~
ACT
ACT
ACT
VLD
APD
APD
OPN
YES
Read-modifyACT
write
RAs-only refresh ACT
ACT
ACT
VLD
APD
APD
VLD
YES
NAC
DNC
DNC
APD
DNC
OPN
YES
DNC
DNC
DNC
DNC
DNC
OPN
NO
NAC
Remarks
fresh
address addres~ DouT
Write
Standby
Note
--
ACT: active; NAC : nonact,ve; DNC : don't care; VLD
Page mode
identical
except
refresh IS
NO
valid; APD : applied; OPN
open
BLOCK DIAGRAM
DATA INPUT
READ/WRITE INPUT
VOO(12V)
COLUMN ADDRESS _ _
STROBE INPUT CAS
ROW ADDRESS RA S
STROBE INPUT
4 H------~---L___,,..._--.,..------J
Vee (5V)
Vss (Ov)
Vss (-5V)
ADDRESS INPUTS
DOUT
•
DATA OUTPUT
MITSUBISHI
.... ELECTRIC
?-1~
MITSUBISHI LSls
MSK4116P-2, P-3
16 384·BIT (16 384·WORD BY I-BIT) DYNAMIC RAM
SUMMARY OF OPERATIONS
Addressing
To select one of the 16384 memory cells in the M5K 4116 P
the 14-bit address signal must be multiplexed into 7
address signals, which are then latched into the on-chip
latch by two externally-applied clock pulses. First, the
negative-going edge of the row-address-strobe pulse (RAS)
latches the 7 row-address bits; next, the negative-going edge
of the column-address-strobe pulse (CAS) latches the 7
column-address bits. Timing of the RAS and CAS clocks
can be selected by either of the following two methods:
1. The delay time from RAS to CAS td (RAS-CAS) is set
between the minimum and maximum values of the
limits. In this case, the internal CAS control signals are
inhibited almost until td (RAS-CAS) max ('gated CAS'
operation). The external CAS signal can be applied with
a margin not affecting the on-chip circuit operations,
e.g. access time, and the address inputs can be easily
changed from row address to column address.
2. The delay time td (RAS-CAS) is set larger than the
maximum value of the limits. In this case the internal
inhibition of CAS has already been released, so that
the internal CAS control signals are controlled by the
externally applied CAS, which also controls the access
time.
Data Input
Data to be written into a selected cell is strobed by the
later of the two negative transitions of R/W input and
CAS input. Thus when the R/W input makes its negative
transition prior to CAS input (early write), the data input
is strobed by CAS, and the negative transition of CAS is set
as the reference point for set-up and hold times. In the
read-write or read-modify-write cycles, however, when the
R/W input makes its negative transition after CAS, the
R/W negative transition is set as the reference point for
set-up and hold times.
Data Output Control
The output of the M5K 4116P is in the high-impedance
state when CAS is high. When the memory cycle in
progress is a read, read-modify-write, or a delayed-write
cycle, the data output will go from the high-impedance
state to the active condition, and the data in the selected
cell will be read. This data output will have the same
polarity as the input data. Once the output has entered
the active condition, this condition will be maintained
until CAS goes high, irrespective of the condition of RAS
(for a maximum of lOllS).
The output will remain in the high-impedance state
throughout the entire cycle in an early-write cycle.
These output conditions, of the M5K 4116P which can
readily be changed by controlling the timing of
the write pulse in a write cycle, and the width of the CAS
2- 14
pulse in a read cycle, offer capabilities for a number of
applications, as follows.
1. Common 1/0 Operation
If all write operations are performed in the early-write
mode, input and output can be connected directly to give
a common I/O data bus.
2. Data Output Hold
The data output can be held between read cycles, without
lengthening the cycle time, until the next cycle commences.
This enables extremely flexible clock-timing settings for
RAS and CAS.
3. Two Methods of Chip Selection
Since the output is not latched, CAS is not required to keep
the outputs of selected chips in the matrix in a highimpedance state. This means that CAS and/or RAS can
both be decoded for chip selection.
4. Extended-Page Boundary
By decoding CAS, the page boundary can be extended
beyond the 128 column locations in a single chip. In this
case, RAS must be applied to all devices.
Page-Mode Operation
This operation allows for multiple-column addressing at the
same row address, and eliminates the power dissipation
associated with the negative-going edge of RAS, because
once the row address has been strobed, RAS is maintained.
Also, the time required to strobe in the row address for
the second and subsequent cycles is eliminated, thereby
decreasing the access and cycle times.
Refresh
The refreshing of the dynamic cell matrix is accomplished
by performing a memory operation at each of the 128
row-address locations within a 2ms time interval. Any
normal memory cycle will perform the refreshing, and
RAS-only refresh offers a significant reduction in operating
power.
Power Dissipation
Most of the circuitry in the M5K 4116P is dynamic,
and most of the power is dissipated when addresses are
strobed. Both RAS and CAS are decoded and applied to
the M5K4116P as chip-select in the memory system,
but if RAS is decoded, all unselected devices go into standby independent of the CAS condition, minimizing system
power dissipation.
Power Supplies
Although the M5K 4116P require no particular powersupply sequencing so long as the devices are used
within the limits of the absolute maximum ratings, it is
recommended that the V BB supply be applied first and
removed last. VBB should never be more positive than
Vss "-,,hen power supply is applied to V DD .
Some eight dummy cycles are necessary after power is
applied to the device before memory operation is achieved.
• MITSUBISHI
"ELECTRIC
MITSUBISHI LSls
MSK4116P-2, P-3
16 384-BIT (16 384-\YORD BY 1-BIT) DYNAMIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Conditions
Limits
Unit
VOO
Supply voltage
Vee
Supply voltage
VSS
Supply voltage
VI
Input voltage
-0.5--20
V
Vo
Output voltage
--0.5-20
V
Voo
Supply voltage
-1 -15
V
Vee
Supply voltage
-1-15
V
VBS--VSS
Supply voltage
10
Output current
-With respect to
With respect to V s s
I
Pd
Power dissipation
Topr
Operating free-air temperature range
Tstg
Storage temperature range
V
-0.5 -20
V
Voo-VSS>O
0
V
50
mA
700
mW
0-70
'C
-65 -150
Limits
Parameter
Unit
Nom
Max
Voo
Supply voltage
VCC
Supply voltage (Note 2)
4.5
5
5.5
V
Vss
Supply voltage
a
0
a
V
10.8
12
13.2
-4 5
VBS
Supply voltage
VIHt
High-level input voltage. RAS,
VIH2
High-level input voltage. AO - A6,
VIL
low-level input voltage. all inputs
"C
(Ta=O-70"C. unless otherwise noted. Note 1)
Min
Note 1
V
-0.5 -20
Ta =25C
RECOMMENDED OPERATING CONDITIONS
Symbol
-0.5 -20
CAS,
-5
-5.7
V
7
V
7
V
0.8
V
2 7
RW
2 4
DIN
V
-1
All voltages with respect to Vss . Apply VSS power supply first. prior to other power supplies. and remove last.
The output voltage will swing from V SS to V CC when output loading current is zero. In standby mode V CC may be reduced to V ss
without affecting refresh operations or data retention. but the VOH min specification is not guaranteed in this mode.
ELECTRICAL CHARACTERISTICS
(Ta=0-70"C,
Voo -12V±10%,
Vcc=5V±10%,
Vss=OV, -5.7V,,;:Vss,,;:-4.5V.unlessotherwisenoted)
Parameter
Symbol
Test conditions
limits
Min
VOH
High-level output voltage (Note 2)
IOH= -5 mA
2.4
VOL
low-level output voltage (Note 2)
IOL=4.2mA
0
loz
Off -state output current
II
Input current
10Ol(AV)
Average supply current from VOO . operating
ICC1(AV)
Average supply current from
IBB1(AV)
Average supply current from Vss. operating
1002
Supply current from VOO . standby
ICC2
Supply current from V CC . standby
ISS2
Supply current from VSS . standby
1003(AV)
Average supply current from VOO . refreshing
ICC3(AV)
Average supply current from V CC . refreshing
DOUT floating
OV~Voun;;5 5V
Vss=-5V. OV~VIN~7V
All other pins =OV
-10
-10
RAS. CAS cycling
. operating (Note 4)
-10
--
tC(REF) = min
Average supply current from V SS . refreshing
Average supply current from V DO . page mode
ICC4(AV)
Average supply current from V CC . page mode (Note 4)
ISS4(AV)
Average supply current from V SS . page mode
--
--
RAS = VIL, CAS
tC(PG) = min
Ci(AO)
Input capacitance. address inputs
Ci(DA)
Input capacitance. data input
VI =Vss
Ci(R W)
Input capacitance. read/write control input
f= lMHz
Ci(RAS)
Input capacitance. R A S input
Vi=25mVrms
Ci(CAS)
Input capacitance. CAS input
Co
Output capacitance
VO=VSS. f= lMHz, VI=25mVrms
V
V
0.4
10
/-lA
10
/-lA
35
mA
1.5
RAS cycling CAS=VIH
Unit
Vcc
200
--
RAS = VIH
DOUT = floating
ISB3(AV)
Max
-
tC(RO) .~ tC(WR) = min
1004(AV)
Typ
-10
/-lA
mA--
10
/-lA
100
/-lA
27
mA
10
/-lA
200
/-lA
27
mA
200
/-lA
5
5
pF
7
pF
10
pF
-
pF
10
pF
7
pF
Note 3 Except for Iss. current flowing into an Ie is positive; out is negative
4
V CC is connected only to the output buffer. so that IcC 1 and I CC4 depend upon output loading.
• MITSUBISHI
"'ELECTRIC
?-1t;
MITSUBISHI LSls
MSK4116P-2, P-3
16 384-BIT (16 384-WORD BY I-BIT) DYNAMIC RAM
TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write, Refresh, and Page-Mode Cycles)
Voo= 12V ± 10%. VCC = 5V ± 10%. v ss = OV. -5. 7V :5:. V ss:5:. -4. 5V. unless otherwise noted. See notes 5. 6. and 7.)
(Ta ~ 0 - 70"C.
M5K4116P-2
Alternative
Symbol
Parameter
Symbol
M5K4116P-3
Limits
Limits
Max
Min
Unit
Max
Min
tC(REF)
Refresh cycle time
tREF
tW(RASH)
R A 5 high pulse width
tRP
100
tW(RASL)
R A S low pulse width
tRAS
150
10000
200
10000
tW(CASL)
CAS low pulse width (Note 8)
tCAS
100
10000
135
10000
th(RAS'CAS)
CAS hold time with respect to R A S
tCSH
150
th(CAS-RAS)
R A S hold time with respect to CAS
tRSH
100
td(RA S-CAS)
Delay time. R A S to CAS (Note 9)
tRCO
20
2
2
ms
120
I1S
I1S
I1S
200
ns
135
I1S
25
50
65
ns
td(ffi-RAS)
Delay time. CAS to RAS
tCRP
-20
-20
ns
tsu (RA-RAS)
Row address setup time with respect to R A S
tASR
0
0
I1S
tsu (CA-CAS)
Column address setup time with respect to CAS
tASC
-10
-10
I1S
th(RAS-RA)
Row address hold time with respect to R A S
tRAH
20
25
ns
th(CAS-CA)
Column address hold time with respect to CAS
tCAH
45
55
ns
th(RAS-CA)
Column address hold time with respect to R A S
tAR
95
120
11S
trHL
tTLH
Transition time
tT
3
35
50
3
--
ns
-
Note 5 After power supply is applied. some eight dummy cycles are required before memory operation is achieved. RAS/CAS refresh cycles or RAS read-only cycles are sUitable
as dummy cycles. Once power is applied. it is also recommended to keep the RAS at high-level for more than 3p.s before the dummy cycles. or to keep the RAS high
pulse width tW(RASH) more than 3p.s for a minimum of one dummy cycle
The switching characteristics are defined as t T HL = tTL H = 5n s .
7
Reference levels of input signals are V,Hl mil1.VIH2 min and VIL max· Reference levels for transition time are also betweenVIHl or VIH2 and VIL
8
Assumes that td (RAS-CA§);;': td (RAS-CAS) max.1f td (RAS-CAS) <-- td (RAS-CAS) Ina x . tW(CASL) will be increased by the amount that td (RAS-CAS)
has decreased.
The maximum value of td(RAS-CAS) does not define the limit of operation. but is specified as a reference point only; if td(RAS-CAS) is greater than the specified
td (RAS-CAS) max limit. then access time is controlled exclusively by ta (CAS).
SWITCHING CHARACTERISTICS
Read Cycle
(Ta =0-70"(;.
VOO= 12V
±
10%.
VCC=5V
±
10%.
M5K4116P-2
-_ .. -
Alternative
Symbol
Parameter
Symbol
Vss=OV. -5_ 7V -S;:Vss-s;: -4_5V. unless otherwise noted
M5K4116P-3
--
---
Min
- - --
Limits
Limits
Max
Min
Unit
Max
tC(RD)
Read cycle time
tRC
320
375
ns
tsu (RD-CAS)
Read set-up time With respect to CAS
tRCS
0
0
ns
th(CAS-RD)
Read hold time with respect to CAS
tRCH
0
th(CAS'QUT)
Data-out hold time
tOFF
0
ta(CAS)
CAS access time (Note 10)
tCAC
100
135
I1S
ta(RAS)
RA S access time (Note 11)
tRAC
150
200
ns
Note 10
11
0
40
ns
0
50
ns
ThiS IS the value when td(RAS-CAS);;': td (RAS-CAS)max. Test conditions; Load = 2TT L .CL=100pF
This is the value when td (RAS-CAS) < td (RAS-CAS)max. When td (RAS-CAS);;': td(RAS-CAS) max
ta(RAS)increases by the amount of increase of td(RAS-CAS)
Test conditions; Load
=
2TTL . CL=100pF
Write Cycle
M5K4116P-2
Symbol
Parameter
Alternative
Symbol
M5K4116P-3
Limits
Limits
Min
Max
Min
Unit
Max
tc(WR)
Write cycle time
tRC
320
375
ns
tsu(wR-ffi)
Write set -up time with respect to CAS (Note 12)
twcs
-20
-20
ns
th(CAS-WR)
Write hold time with respect to CAS
tWCH
45
55
ns
th(RAS-WR)
Write hold time with respect to R A S
tWCR
95
120
ns
th(WR-RAS)
R A S hold time with respect to write
tRwL
50
70
ns
th(WR-CAS)
CAS hold time with respect to write
tCWL
50
70
ns
tW(WR)
Write pulse width
twp
45
55
ns
tsu (DA-CAS)
Data-in setup time with respect to CAS
tos
0
0
ns
th(CAS'DA)
Data-in hold time with respect to CAS
tOH
45
55
ns
th(RAS-DA)
Data-in hold time with respect to R A S
tOHR
95
120
ns
2· 16
• MITSUBISHI
"'ELECTRIC
MITSUBISHI LSls
MSK4116P-2, P-3
16 384-BIT (16 384-WORD BY I-BIT) DYNAMIC RAM
Read-Write and Read-Modify-Write Cycles
M5K4116P-2
Parameter
Symbol
Alternative
symbol
M5K4116P-3
Limits
Limits
Min
Max
Min
tc(RMW)
Read-modify-write cycle time
tRWC
320
405
ns
tC(RW)
Reed-write cycle time
tRWC
320
375
ns
th(WR-RAS)
R A S hold time with respect to write
tRWL
50
70
ns
th(WR-CAS)
CAS hold time with respect to write
tCWL
50
70
ns
tW(WR)
Write pulse width
twp
45
55
ns
tSU(RD-CAS)
Read setup time with respect to CAS
tRCS
0
0
ns
td(RAS-WR)
Delay time. RAS to write (Note 12)
tRWO
110
145
ns
td(CAS-WR)
Delay time. CAS to write (Note 12)
tcwo
60
80
ns
tSU(DA-WR)
Data-in set-up time with respect to write
tos
0
0
ns
th(WR-DA)
Data-in hold time with respect to write
tOH
45
55
th (CAS-OUT)
Data-out hold time with respect to CAS
tOFF
ta(CAS)
CAS access time (Note 10)
tCAC
ta(RAS)
R A S access time (Note 11)
tRAC
Note 12: tSU(WR-CAS).
0
ns
50
ns
100
135
ns
150
200
ns
40
II
Unit
Max
0
td(RAS-WR). and td(CAS-WR)do not define the limits of operation. but are included as electrical characteristics only.
When tsu (WR-CAS) £ tsu (WR-CAS) mill. an early-write cycle is performed. and the data output keeps the high-impedance state.
When td(RAS-WR) ::£ td (RAS-WR)mlll and td(CAS-WR) ~ td(CAS-WR) mlrl. a read-modify-write cycle is performed. and the data
of the selected address will be read out on the data outputs.
For all conditions other than those described above the condition of data output is not defined.
Page-Mode Cycle
M5K4116P-2
Symbol
Parameter
Alternative
symbol
--
M5K4116P-3
Limits
Min
Limits
Max
Min
Unit
Max
tC(PG)
Page-mode cycle time
tpc
170
225
ns
tW(CASH)
CAS high pulse width
tcp
60
80
ns
• MITSUBISHI
"ELECTRIC
2--17
MITSUBISHI LSls
MSK4116P-2, P-3
16 384~BIT (16 384·WORD BY I.BIT) DYNAMIC RAM
TIMING DIAGRAMS
Read Cycle
~~------------------------tO(RD)------------------------------~
~------------------tW(RASL)------------------~-4
VIHl
_------1
VIL
-
I - - - - - - - - - - - - - - - - - t h (RAS-CAS)
-------------------11
~-------th(RAS-CA)----------to--l1
,__--I-+-_------I-
t h (CAS- RAS
)---------I..-{
t-------:---tW(CASL)--------~
VIH2 -
COLUMN
ADDRESS
AO- A6
VIH1-
L-ta(CAS)------~
R W
-+----I__ th (CAS-OUT)
1---------------- ta (RAS) ------------------1
VOH -
- - - - - - - - - - HIGH-IMPEDANCE STATE -------~~I
DOUT
DATA VALID
VOL -
Write and Early Write Cycles
r-~-------------------------tC(WR)----------------------------~~
I - - - - - - - - - - - - - - - - - - t W(RASL)-------------------~
f----------------th
~-----ttl(RAS-CA)
RAS
(RAS-1CAS)--------------I1
.
I - - - - ' - - - - - t h (CAS- R A S ) - - - - - : . . - I
- - - - - + - - - - ' - - - t W ( C A S L ) ----~
AO - A6
VIH1-
RW
VIL
+-___~~~~~~~~~~~~~~~~~~~~~~~~
-~~~~~~~~~~~_ _~_ _
VIH2 VIL
\A,~A,A,~AJ\)'\/',/\J'\/\
-~~~~~~~~~~~~
~-------th(RAS-DA)-----~
DOUT
2-18
VOH VOL _ - - - - - - - - - - - - - - - - H I G H - I M P E D A N C E STATE - - - - - - - - - - - - - - - - - - - -
• MITSUBISHI
.... ELECTRIC
MITSUBISHI LSls
MSK4116P-2, P-3
16 384-BIT (16 384-WORD BY I-BIT) DYNAMIC RAM
Read-Write and Read-Modify-Write Cycles
~~------------------------------tC(RMW)------------------------------------__~
~---------------------------tW(RASL)------------------------------~
1 - - - - - - - - - - - - - - - - - - - - - - - - - - th (RAS- CAS)-----------------------------l
1-~-----th(RAS-CA)----_l
~----~~---------th(CAS-RAS)------------------~
--~-+~----------------tW(CASL)--------~
Ao-A6
VIH2VIL -
td(CAS-WR)
R W
VIH1VIL -
L",c'S,
th(CAS-OUT)
VOH DOUT
I.
VOL -
HIGH-IMPEDANCE STATE
ta(RAS)
VIH2DIN
VIL -
RAS-Only Refresh Cycle
~~--------------------tc (RD) - - - - - - - - - - - - - - - - - - - - - - - - - - - l
t - - - - - t W(RASLl----------l
RAS
V IH2 -
VI L
- ........lI..l"'-lo;.~""'""~.lI...il"""""',Q""Ii..,
VOH DOUT
VOL -
- - - - - - - - - - - - - - - - - - HIGH-IMPEDANCE STATE - - - - - - - - - - - - - - - - - -
Note 13 : CAS=VIH1.
R/W=don'tcare,
• MITSUBISHI
.... ELECTRIC
2-19
MITSUBISHI LSls
MSK4116P-2, P-3
16 384-BIT (16 384-WORD BY 1-BIT) DYNAMIC RAM
Page-Mode Read Cycle
~~----------------------------tW(RASL)----------------------------------~
VIH1VIL -
AO-A6
VIH2 VIL -
DOUT
VIH1_~~~~~~----------------~~~~------------------r/FC--------------~~~~~~~~~~
R/W
VIL _~~~~'"
Page-Mode Write Cycle
~-------------------------------tW(RASL)--------------------------------~
VIH1VIL
AO-A6
VIH2VIL -
R/W
DIN
VIH1VIL
-
VIH2 VIL -,.jj.,\,Qo.,io,~~
Note 14;
Indicates the don't care input.
The center-line indicates the high-impedance state.
2-20
• MITSUBISHI
"'ELECTRIC
MITSUBISHI LSls
MSK4116P-2, P-3
16 384·BIT (16 384·WORD BY I·BIT) DYNAMIC RAM
TYPICAL CHARACTERISTICS
NORMALIZED ACCESS TIME VS.
SUPPLY VOLTAGE Voo
NORMALIZED ACCESS TIME VS.
AMBIENT TEMPERATURE
1.4
1.4
Voo= 12V
Vcc=5V
Ta=25'C
Vss=-5V
2
"~
~
1=
(/)
12
1. 0
u
~
63
N
~O.s
----
~
~
1=
~ 1.0
r--
~
«
63
~
:::2
«
a:
~
~
V
o.s
:::2
oz
a:
oz
0.6
10
11
12
13
14
25
50
75
AMBIENT TEMPERATURE Ta Cc
SUPPLY VOLTAGE VOO(V)
NORMALIZED ACCESS TIME VS.
SUPPLY VOLTAGE Vee
AVERAGE SUPPLY CURRENT FROM Voo,
OPERATING MODE VS. SUPPLY VOLTAGE
1. 4 ...---...,....-----,------..,,....------,
40r---,----.--~--__,
Ta
o
o
,(ij'
'~ 1. 2 1 - - - - - ! - - - - + - - - - - I - - - - ;
:J
100
)
~
a:
= 25"C
V ss= -4.5V
>
30~--+_---t---__!--____i
~
LL«
§~
~
1=
~ 1.0
§u-8 20f-'--=f----+-----,:::::;;;o-i-"'-------1
u
u
..JO
)-UJ
«
63
~
«
~~
(/)(9
O. Sl----l---------+----+-----I
:::2
a:
UJ
Z
~~
UJa:
101-----=4----+-----+-----1
>~
oz
. . . . . . ___
-5.5
0.6~_ _~----I..--
-4.0
-4.5
-5.0
«0
-~
0~10~-~11----,-~1~2--~13~-~14
-6.0
SUPPLY VOLTAGE Voo(V)
SUPPLY VOLTAGE V SS( V)
NORMALIZED ACCESS TIME VS.
SUPPLY VOLTAGE Vee
1. 4 ,...---...,....-----,------..,------,
AVERAGE SUPPLY CURRENT FROM Voo,
OPERATING MODE VS. AMBIENT TEMPERATURE
40
o
o
I~I~ 1. 2t----+----+--__!--____i
:J
I.
VDD= 13.2V
>
Vss= -4.5V
:::2
o
fE~
30
tc = 375ns
~ E
UJ
~
I
~
~
1=
0
a
.9
)-UJ
~ 1.0
u
tc =500ns
20
1
..JO
u
~~
«
63
tc = 750ns
(/)(9
~ O. st-----+_---t---__!I------f
«
:::2
a:
oz
UJ
Z
~~
~~
«0
O. 6.'-::-~:_'_=_--.."...".....--=".."...-......"..J
4.0
4.5
5.0
5.5
6.0
10
o
o
25
50
75
100
AMBIENT TEMPERATURE Ta('C)
SUPPLY VOLTAGE Vcc(V)
• MITSUBISHI
.... ELECTRIC
2-21
MITSUBISHI LSls
MSK4116P-2, P-3
16 384-BIT (16 384-WORD BY I-BIT) DYNAMIC RAM
AVERAGE SUPPLY CURRENT FROM Voo,
REFRESH MODE VS. SUPPLY VOLTAGE
AVERAGE SUPPLY CURRENT FROM Vo o ,
OPERATING MODE VS. FREQUENCY
40
20r-----~----~--~----~~_,
I
Ta=25°C
Voo= 13.2V
0""""
0<1:
>E
~
-00
20
~~
/
Ul<.!j
UJZ
~~
~~
«0
10
/
~
EE
/
>-UJ
Ta =25"C
..,.
/
Vss= -4.5V
30
0
cr:
u....JO
oo
151-------!..~=--___l-
1-""""
z<1:
~~g
a
10~--~--~-~~~~-~
~-
o..UJ
0..0
=>0
Ul~
~V5
51----+----+----+-----1
ffitf
~~
11
13
14
SUPPLY VOLTAGE Voo(V)
SUPPLY CURRENT FROM Voo,
STANDBY MODE VS. SUPPLY VOLTAGE
AVERAGE SUPPLY CURRENT FROM Voo,
REFRESH MODE VS. AMBIENT TEMPERATURE
1.4
25
I
Ta = 25°C
Vss= -4.5V
0,.......
0
EE
I-~
r5cr:~E
~~
ON
0
u. ..9
-
I-
ZUJ
~
1.0
!5~
u>>-al
..J O
o..Z
0..«
~~ 0.8
g
".
V
V
/
ee
=>
u
I
Voo= 13.2V
Vss= -- 5. 5V
~
g~ 1.2
ee
12
FREQUENCY f(~)(MHz)
20
1
M
0
0
= 375n5
tc (REF)
15
= 500n5
tC(REF)
~-
0.. UJ
0..0
=>0
I
Ul~
~V5
tC(REF)
10
ffi~
>UJ
= 750n5
«cr:
0.6
10
11
12
25
14
13
SUPPLY VOLTAGE Voo(V)
I
Ta = 25°C
0
Voo= 13.2V
Vss= -4.5V
>
~
0
~~
EE
cr:
I-
ON
I-
ZUJ
~
g 1.0
!5~
u>>-al
..J o
o..Z
~ ~0.8
Voo= 13.2V
0
0<1:
> E 1.2
u..9
---- -----...
Vss= -4.5V
20
r5
cr:
cr:
=>
u
>..J
o..UJ
0..0
=>0
r-
15
Ul~
UJ I
~~
cr:ee
10
UJu...
>UJ
«ee
0.6
o
25
50
75
100
50
2
3
FREQUENCY f(~) (MHz)
AMBIENT TEMPERATURE Ta (OC )
2-22
100
25r-----~----~------~----_,
1.4
0
75
AVERAGE SUPPLY CURRENT FROM V oo ,
REFRESH MODE VS. FREQUENCY
SUPPLY CURRENT FROM Vee'
STANDBY MODE VS. AMBIENT TEMPERATURE
0,.......
50
AMBIENT TEMPERATURE Ta (oC )
• MITSUBISHI
.... ELECTRIC
MITSUBISHI LSls
MSK4116P-2, P-3
16 384-BIT (16 384-WORD BY I-BIT) DYNAMIC RAM
AVERAGE SUPPLY CURRENT FRC~JI Voo.
PAGE MODE VS. SUPPLY VOLTAGE
20r------r----~------._----~
oo
Ta =25"C
>
~
tC(PG)=250ns
15~----~--~~~----+-----~
B:
RAS, CAS, R/W INPUT VOLTAGE
VIH It VIL I VS. SUPPLY VOLTAGE
;- 2.5
...J
Ta=25"C
->
! 2.0
>
I
~l(min)
-~
f--
d'i~
~ ~
3~ 10~--~~~--~~~~J-----~
>-
0:
tL
5~----~----~------~----~
W
l?
!!:
"a: 1.0
Ij
>
« «
tL
11
13
12
14
SUPPLY VOLTAGE VOO(V)
ui
l«a:
0.5
20
Voo= 13.2V, VBB= -4.5V
o
o
::2;
~
15
tC(PG; =375ns
f-
i5~
"T-
§~
tC(PG)-500ns
u ~ 10
>- 0
...J
13
14
~IH1(mint
LJ.J
l?
«
f-
LJ.J
?;
-
LJ.J
0
LJ.J
l?
~
tL
--
VIL l(max)
B
=>
I
Voo= 12V
> 1.5
(/) 0
!!:
;r:
5
> «
tL
«
1.0
Ij
o
o
50
25
75
100
AMBIENT TEMPERATURE Ta ("C)
Ta =25"C I
>
Voo=13.2V
::2;
VBB= -4.5V
15
i5~
§~
u'-;;; 10
>- 0
~.9
V
/
V
./
V
-4.5
-5.0
-5.5
-6.0
~
RAS, CAS, R/W INPUT VOLTAGE
V 1H1, VIL1 VS. AMBIENT TEMPERATURE
->
Voo= 12J
VBB= -5V
t---.
VIH1(min)
LJ.J
l?
T
«
f-
B
VIL1(max)
> 1.5
f-
~
'/
LJ.J
0.5
-4.0
...J
f-
(/)0
«
2:. 2.5
20
o
o
ui
l a:
SUPPLY VOLTAGE VBB(V)
AVERAGE SUPPLY CURRENT FROM Voo.
PAGE MODE VS. FREQUENCY
~ ~
Ta=25"C'
->
! 2.0
>
a:E
~
12
RAS, CAS, R/W INPUT VOLTAGE
VIHI, VILI VS. SUPPLY VOLTAGE
f-
~ ~
11
;- 2.5
,
tc (PG) - 250ns
>
10
SUPPLY VOLTAGE VOO(V)
AVERAGE SUPPLY CURRENT FROM Voo.
PAGE MODE VS. AMBIENT TEMPERATURE
=>
VIL1(max)
i--
0
0
iii ~
LJ.J
......-
-
~ ~
Cl:
I
VBB= -5V
?;
!!:
;r:
5
a::
LJ.J
LJ.Jl?
1.0
Ij
> «
«
tL
o
o
ui 0.5
2
«
l a:
0
25
50
75
100
AMBIENT TEMPERATURE Ta( "C)
FREOUENCY f(¢» (MHz)
• MITSUBISHI
.... ELECTRIC
2-23
MITSUBISHI LSls
MSK4116P-2, P-3
16 384-BIT (16 384-WORD BY 1-BIT) DYNAMIC RAM
INPUT VOLTAGE Ao-As. DIN VS.
SUPPLY VOLTAGE VIH2. VIL2
2
2 .5
INPUT VOLTAGE Ao - As. DIN VS.
AMBIENT TEMPERATURE VIH2. VIL2
;-2.5
I
~
Ta=25"C
->
N
.J
->
Vss= -5V
~2.0
->w
.IVIL2(max)
ir
~
VIH2(min)
~
~
~ 1.5
----
-
f-
->
w
~2(min)
-
~~ 1.5
~2.0
j
Voo= 12V
\/ss= -5V
VIL2(max)
f-
::::>
0..
~
61. 0
61.0
~
I
~0.5
iI
10
11
12
~o. 5
13
14
SUPPLY VOLTAGE VOO(V)
25
75
50
AMBIENT TEMPERATURE Ta ( °C )
SUPPLY CURRENT VS. TIME
RAS/CAS CYCLE
LONG RAS/CAS CYCLE
INPUT VOLTAGE Ao - As. DIN VS.
SUPPLY VOLTAGE VIH2. VIL2
RAS ONLY CYCLE
2.5
2:-
Ta=25"C
~
->
I
Voo= 12V
RAS
E
CAS
U;
.:; 2.0
->
VIH2(min)
w
~
g
100
(mA)
VIL2(max)
::::>
c.
~
0
0
0
rE ISS
0
(mA)-2 0
u
-4 0
f-
~
z 1. 0
0'
10 0
~ 00
(mA) ~ 0
0
0
§; I ss
~
(f)
~O. 5
-4.0
--4.5
-5.0
-5.5
-6.0
NORMALIZED ACCESS TIME VS.
LOAD CAPACITANCE
1.2
I~
51. 1
1.0
~
~
----
~
0.9
o. 8
50
100
150
SOns/DIVISION
TIME t
SUPPLY VOLTAGE VSS(V)
200
LOAD CAPACITANCE (pF)
2-24
~g
~g
§
I-
• MITSUBISHI
..... ELECTRIC
M+H-
lJplUL
o
I
1.5
en
~
II
t-tt-I't-t-t-t100
(f)
I
«
«
100
MITSUBISHI LSls
MSK4164P-1S, P-20
65 536-BIT (65 536-WORD BY 1-BIT) DYNAMIC RAM
DESCRIPTION
PIN CONFIGURATION (TOP VIEW)
This is a family of 65 536-word by 1-bit dynamic RAMs,
fabricated with the high performance N-channel silicon-gate
MOS process, and is ideal for large-capacity memory
systems where high speed, low power dissipation, and low
costs are essential. The use of double-layer polysilicon
process technology and a single-transistor dynamic storage
cell provide high circuit density at reduced costs, and the
use of dynamic circuitry including sense amplifiers assures
low power dissipation. Multiplexed address inputs permit
both a reduction in pins to the standard 16-pin package
configuration and an increase in system densities. The
M5K4164P operates· on a 5V power supply using the
on-chip substrate bias generator.
VSS
REFRESH INPUT
(QV)
15 +-CAS ~~~g~EN 1~~8~ESS
DATA INPUT
WRITE
CONTROL INPUT
14 -+ Q
DA T A OUTPUT
ROW ADDRESS
STROBE INPUT
ADDRESS INPUTS
(5vl
ADDRESS INPUTS
Vee
• If the pin 1 (REF) function is not used, pin 1 may be left open (not connect).
FEATURES
Outline 16P4
• Performance ranges
Access time
(max)
(ns)
Cycle time
(min)
(ns)
Power dissipation
(typ)
(mW)
M5K4164P-15
150
260
200
M5K4164P-20
200
330
170
Type name
•
•
•
• Standard 16-pin package
• Single 5V ±10% supply
• Low standby power dissipation:
22mW (max)
• Low operating power dissipation:
M5K4164P-15
275mW (max)
M5K4164P-20
250mW (max)
• Unlatched output enables two-dimensional chip selection and extended page boundary
• Early-write operation gives common I/O capability
• Read-modify-write, RAS-only refresh, and page-mode
capabi lities
•
•
•
•
All input terminals have low input capacitance and are
directly TTL-compatible
Output is three-state and directly TTL-compatible
128 refresh cycles every 2ms
(16K dynamic RAMs M5K4116P, S compatible)
Pin 1 controls automatic- and self-refresh mode
CAS controlled output allows hidden refresh, hidden
automatic refresh and hidden self-refresh
Output data can be held infinitely by CAS
Interchangeable with
Mostek's
MK4164
and
Motorola's MCM 6664 in pin configuration
APPLICATION
•
Main memory unit for computers
BLOCK DIAGRAM
DATA INPUT
WRITE CONTROL INPUT
COL~~R~:f?~~0f
Vee (5V)
CAS
ROW ADDRESS
STROBE INPUT
V 55 (OV)
REFRESH INPUT
MEMORY CELL
(64 ROWS X 256 COLUMNS)
SENSE REFRESH AMPLIFIER
MEMORY CELL
(64 ROWS X 256 COLUMNS)
COLUMN DECODER
MEMORY CELL
(64 ROWS X 256 COLUMNS)
ADDR ESS INPUTS
SENSE REFRESH AMPLIFIER
MEMORY
(64 ROWS
X 256 CELL
COLUMNS)
ADDRESS
MULTIPLEX
COLUMN DECODER
14
Q
DATA OUTPUT
J'
L-_______________ _________________ ________________ _
• MITSUBISHI
"'ELECTRIC
2-25
II
MITSUBISHI LSls
MSK4164P-15, P-20
65 536·BIT (65 536·WORD BY I-BIT) DYNAMIC RAM
FUNCTION
The M5K4164P provides, in addition to normal read, write,
and read-modify-write operations, a number of other
functions, e.g., page mode, RAS-only refresh, and delayedwrite. The input conditions for each are shown in Table 1.
Table 1 I nput conditions for each mode
inputs
Operation
RAS
CAS
W
0
Output
Row
address
Column
address
REF
Q
Refresh
Read
ACT
ACT
NAC
ONC
APO
APO
NAC
VLO
YES
Write
ACT
ACT
ACT
VLO
APO
APO
NAC
OPN
YES
Read-modify-write
ACT
ACT
ACT
VLO
APO
APO
NAC
VLO
YES
RAS"-only refresh
ACT
NAC
ONC
ONC
APO
ONC
NAC
OPN
YES
YES
Hidden refresh
ACT
ACT
ONC
ONC
APO
ONC
NAC
VLD
Automatic refresh
NAC
ONC
ONC
ONC
ONC
ONC
ACT
OPN
YES
Self refresh
NAC
ONC
ONC
ONC
ONC
ONC
ACT
OPN
YES
I
Hidden automatic refresh
NAC
ACT
ONC
ONC
ONC
ONC
ACT
VLO
YES
Hidden self refresh
NAC
ACT
ONC
ONC
ONC
ONC
ACT
VLO
YES
Standby
NAC
ONC
ONC
ONC
ONC
ONC
NAC
OPN
NO
I
Remarks
Page mode
identical except
refresh is NO.
Note: ACT: active, NAC : nonactive, ONC: don't care, VLO : valid, APO : applied, OPN : open.
SUMMARY OF OPERATIONS
Addressing
To select one of the 65 536 memory cells in the M5K4164P
the 16-bit address signal must be multiplexed into 8 address
signals, which are then latched into the on-chip latch by
two externally-applied clock pulses. First, the negativegoing edge of the row-address-strobe pulse (RAS) latches
the 8 row-address bits; next, the negative-going edge of the
column-address-strobe pulse (CAS) latches the 8 columnaddress bits. Timing of the RAS and CAS clocks can be
selected by either of the following two methods:
1. The delay time from RAS to CAS td (RAS-CAS) is set
between the minimum and maximum values of the
limits. In this case, the internal CAS control signals are
inhibited almost until td(RAS-CAS)max ('gated CAS'
operation), The external CAS signal can be applied with
a margin not affecting the on-chip circuit operations, e.g.
access ti me, and the address inputs can be easily changed
from row address to column address.
2. The delay time td(RAS-CAS) is set larger than the
maximum value of the limits. In this case the internal
inhibition of CAS has already been released, so that the
internal CAS control signals are controlled by the
externally applied CAS, which also controls the access
timp.,
Data Input
Date to be written into a selected cell is strobed by the later.
of the two negative transitions of W input and CAS input.
Thus when the W input makes its negative transition prior
to CAS input (early write), the data input is strobed by
CAS, and the negative transition of CAS is set as the
reference point for set-up and hold times. In the read-write
•
2 -26
or read-modify-write cycles, however, when the W input
makes its negative transition after CAS, the W negative
transition is set as the reference point for setup and hold
times.
Data Output Control
The output of the M5K4164P IS In the high-impedance
state when CAS is high. When the memory cycle in progress
is a read, read-modify-write, or a delayed-write cycle, the
data output will go from the high-impedance state to the
active condition, and the data in the selected cell will be
read. This data output will have the same polarity as the
input data. Once the output has entered the active
condition, this condition will be maintained until CAS goes
high, irrespective of the condition of RAS.
The output will remain in the high-impedance state
throughout the entire cycle in an- early-write cycle.
These output conditions, of the M5K4164P, which can
readily be changed by controlling the timing of the write
pulse in a write cycle, and the width of the CAS pulse in a
read cycle, offer capabilities for a number of applications,
as follows.
1. Common I/O Operation
If all write operations are performed in the early-write
mode, input and output can be connected directly to give a
common I/O data bus.
2. Data Output Hold
The data output can be held between read cycles, without
lengthening the cycle time. This enables extremely flexible
clock-timing settings for RAS and CAS.
MITSUBISHI
~ELECTRIC
MITSUBISHI LSls
MSK4164P-15, P-20
65 536-BIT (65 536-WORD BY I-BIT) DYNAMIC RAM
3. Two Methods of Chip Selection
4. Self-Refresh
Since the output is not latched, CAS is not required to keep
th8 outputs of selected chips in the matrix in a highimpedance state. This means that CAS and/or RAS can
both be decoded for chip selection.
The other function of pin 1 (REF) is self-refresh. Timing
for self-refresh is quite similar to that for automatic refresh.
As long as RAS remains high and REF remains low, the
M5K4164P will refresh itself. This internal sequence repeats
asynchronously every 12 to 16 /J.S. After 2 ms, the on-chip
refresh address counter has advanced through all the row
addresses and refreshed the entire memory. Self-refresh is
primarily intended for trouble free power-down operation.
For example, when battery backup is used to maintained
data integrity in the memory. REF may be used to place
the device in the self-refresh mode with no external timing
signals necessary to keep the information alive.
In summary, the pin 1 (REF) refresh function gives the
user a feature that is free, save him hardware on the board,
and in fact, will simplify his battery backup procedures,
increase his battery life, and save him overall cost while
giving him improved system performance.
There is an internal pullup resister (~ 3Mr2) on pin 1, so
if the pin 1 (REF) function is not used, pin 1 may be left
open (not connect) without affecting the normal operations.
4. Extended-Page Boundary
By decoding CAS, the page boundary can be extended
beyond the 256 column locations in a single chip. In this
case, RAS must be applied to all devices.
Page-Mode Operation
This operation allows for mUltiple-column addressing at the
same row address, and eliminates the power dissipation
associated with the negative-going edge of RAS, because
once the row address has been strobed, RAS is maintained.
Also, the time required to strobe in the row address for the
second and subsequent cycles is eliminated, thereby decreasing the access and cycle times.
Refresh
Each of the 128 rows (Ao '" A 6 ) of the M5 K4164P must be
refreshed every 2 ms to maintain data. The methods of
refreshing for the M5K4164P are as follows.
1. Normal Refresh
Read cycle and Write cycle (early write, delayed write or
read-modify-write) refresh the selected row as defined by
the low order (RAS) addresses. Any write cycle, of course,
may change the state of the selected cell. Using a read,
write, or read-modify-write cycle for refresh is not recommended for systems which utilize "wire-OR" outputs since
output bus contention will occur.
2. RAS Only Refresh
A RAS-only refresh cycle is the recommended technique
for most applications to provide for data retention. A
RAS-only refresh cycle maintains the output in the
high-impedance state with a. typical power reduction of
20% over a read or write cycle.
3. Automatic Refresh
Pin 1 (R EF) has two special functions. The M5K4164P
has a refresh address counter, refresh address multiplexer
and ,refresh timer for these operations. Automatic refresh is
initiated by bringing REF low after RAS has precharged
and is used during standard operation just like RAS-only
refresh, except that sequential row addresses from an
external counter are no longer necessary.
At the end of automatic refresh cycle, the internal
refresh address counter will be automatically incremented.
The output state of the refresh address counter is initiated
by some eight REF, RAS or RAS/CAS cycle after power is
appl ied. Therefore, a special operation is not necessary to
initiate it.
RAS must remain inactive during REF activated cycles.
Likewise, REF must remain inactive during RAS generated
cycle.
5. Hidden Refresh
A features of the M5K4164P is that refresh cycle may be
performed while maintaining valid data at the output pin
by extending the CAS active time from a previous memory
read cycle. This feature is refered to as hidden refresh.
Hidden refresh is performed by holding CAS at V 1L and
taking RAS high and after a specified precharge period,
executing a RAS-only cycling, automatic refresh and
self-refresh, but with CAS held low.
The advantage of this refresh mode is that data can be
held valid at the output data port indefinitely by leaving
the CAS asserted. In many applications this eliminates the
need for off-chip latches.
Power Dissipation
Most of the circuirty in the M5K4164P is dynamic, and
most of the power is dissipated when addresses are strobed.
Both RAS and CAS are decoded and applied to the
M5K4164P as chip-select in the memory system, but if
RAS is decoded, all unselected devices go into stand-by
independent of the CAS condition, minimizing system
power dissipation.
Power Supplies
The M5K4164P operates on a single 5V power supply.
A wait of some 500/J.s and eight or more dummy cycle is
necessary after power is applied to the device before
memory operation is ach ieved.
• MITSUBISHI
"ELECTRIC
2-27
II
MITSUBISHI LSls
MSK4164P-1S, P-20
65 536-BIT (65 536·WORD BY 1-BIT) DYNAMIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol
Paramater
Limits
Conditions
Unit
VCC
Supply voltage
VI
Input voltage
Vo
Output voltage
-1-7
V
10
Output current
50
mA
700
mW
0-70
·C
With respect to Vss
Pd
Power dissipation
Topr
Operating free-air temperature range
Tstg
Storage temperature range
Ta =25·C
VCC
Vss
Supply voltage
VIH
High·level input voltage, all inputs
VIL
Low-level input voltage, all inputs
V
·C
(Ta=0-7O"C. unless otherwise noted) (Note 1)
Limits
Parameter
Supply voltage
V
-1-7
-65-150
RECOMMENDED OPERATING CONDITIONS
Symbol
-1-7
Min
Unit
Nom
Max
4.5
5
5.5
V
0
0
0
V
2.4
6.5
V
-2
0.8
V
Note 1: All voltage values are with respect to Vss
ELECTRICAL CHARACTERISTICS
Symbol
± 10%.
(Ta =0-7O"C. Vcc=5V
Vss=OV. unless otherwise noted) (Note 2)
Test conditions
Parameter
Limits
Min
Typ
Max
Unit
VOH
High-level output voltage
10H = -5mA
2.4
VCC
VOL
Low·level output voltage
IOL=4.2mA
0
0.4
10Z
Off·state output current
Q floating
-10
10
).JA
II
Input current
I CCl(AV)
Average supply current from Vee,
operating (Note 3, 4)
OV~VOUT~5.5V
OV~VIN~6.5V • All other pins; OV
-10
V
V
10
).JA
M5K4164P- 15
RAS. CAS cycling
50
mA
M5K4164P-20
t CR =t CW = min output open
45
mA
4
mA
40
mA
ICC2
Supply current from Vee, standby
I CC3(AV)
Average supply current from Vee,
refreshing (Note 3)
M5K4164P- 15
RAS cycling
M5K4164P-20
t C (REF)= min, output open
35
mA
I CC4(AV)
Average supply current from Vee,
page mode (Note 3, 4)
M5K4164P-15
RAS = VIL. CA S cycling
40
mA
M5K4164P-20
tcpo=min. output open
35
mA
I CC5(AV)
Average supply current from Vee,
automatic refreshing (Note 3)
M5K4164P-15
RAS=VIH. REF cycling
40
mA
M5K4164P-20
tc (REF)=min. output open
35
mA
8
mA
RAS =VIH output open
ICC6(AV)
Average supply current from Vee, self refreshing
01 (A)
Input capacitance, address inputs
01
Input capacitance, data input
(0)
CAS=VIH
RAS=VIH. REF =VIL
output open
VI=VSS
01 (W)
Input capacitance, write control input
f=lMHz
01 (RAS)
I nput capacitance, RAS input
VI=25mVrms
01 (CAS)
5
pF
5
pF
7
pF
10
pF
Input capacitance, CAS input
10
pF
CI (REF)
Input capacitance, REF input
10
pF
Co
Output capacitance
7
pF
Note 2:
3:
4:
2
28
VO=VSS. f= 1MHz. VI=25mVrms
Current flowing into an IC is positive; out is negative.
I CCI (AV). I CC3(AV). I CC4(AV) and I CC5(AV) are dependent on cycle rate. Maximum current is measured at the fastest cycle rate.
I CC I (AV) and I CC4(AV) are dependent on output loading. Specified values are obtained with the output open.
• MITSUBISHI
.... ELECTRIC
MITSUBISHI LSls
MSK4164P-1S, P-20
65 536·BIT (65 536·WORD BY I-BIT) DYNAMIC RAM
TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write, Refresh, and Page-Mode Cycle)
(Ta =0-70·C, Vcc=5V
± 10%,
VSS=OV,
unless otherwise noted, See notes 5, 6and 7)
M5K4164P-15
Symbol
Alternative
Parameter
M5K4164P-20
Limits
Symbol
Min
Unit
Limits
Max
Min
Max
tcRF
Refresh cycle time
t REF
t W(RASH)
RAS high pulse width
t RP
100
t W(RASL)
RAS low pulse width
t RAS
150
t W(CASL)
CAS low pulse width
tCAS
75
t W(CASH)
CAS high pulse width
t CPN
35
40
ns
t h (RAS-CAS)
CAS hold time after RAS
tCSH
150
200
ns
t h (CAS-RAS)
RAS hold time after CAS
t RSH
75
100
ns
td (CAS-RAS)
Delay time, CAS to RAS
(Note g)
tCRP
-20
-20
t d (RAS-CAS)
Delay time, RAS to CAS
(Note 10)
t RCD
25
(Note 8)
2
2
120
ms
ns
10000
200
10000
ns
00
100
00
ns
75
ns
30
100
ns
t su (RA-RAS)
Row address setup time before RAS
t ASR
0
0
t su (CA-CAS)
Column address setup time before CAS
tAsc
-5
-5
ns
t h (RAS-RA)
Row address hold time after RAS
t RAH
20
25
ns
ns
t h (CAS-CA)
Column address hold time after CAS
t CAH
25
35
t h (RAS-CA)
Column address hold time after RAS
tAR
95
120
Transition time
h
t THL
t TLH
Note 5:
6:
7:
8:
g.
10:
3
35
ns
ns
3
50
ns
An initial pause of 500ps is required after power-up followed by a.ny eight REF, RAS or RAS/CAS cycles before proper device operation is achieved.
The switching characteristics are defined as t THL = t TLH = 5n s.
Reference levels of input signals are VI H min. and VI L max. Reference levels for transition time are aiso between VI H and VI L.
Except for page-mode.
td(CAS-RAS) requirement is only applicable for RAS/CAS cycles preceeded by a CAS only cycle (i.e., For systems where CAS has not been decoded with RAS)
Operation within the td (RAS-CAS) max limit insures that ta (RAS) max can be met. td (RAS-CAS)maX is specified reference point only;if
td (RAS-CAS) is greater than the specified td (RAS-CAS) max limit. then access time is controlled exclusively by ta(CAS)'
td (RAS-CAs)mln = th (RAS-RA)min
+ 2t THL(t TLH) + t su (CA-CAS)min.
SWITCHING CHARACTERISTICS
Read Cycle
(Ta =0-70·C, Vcc=5V
10%, VSS=OV, unless otherwise noted)
Alternative
Parameter
Symbol
±
M5K4164P-15
M5K4164P-20
Limits
Limits
Symbol
Min
Max
Unit
Max
Min
tcR
Read cycle time
t RC
260
330
tsu (R-CAS)
Read setup time before CAS
t RCS
0
0
ns
th (CAS-R)
Read hold time after CAS
t RCH
0
0
ns
th(RAS-R)
Read hold time after RAS
(Note 11)
tRRH
20
tdls (CAS)
Output disable time
(Note 12)
t OFF
0
ta (CAS)
CAS access time
(Note 13)
t CAC
75
100
ns
ta (RAS)
RAS access time
(Note 14)
t RAC
150
200
ns
Note
Note
Note
Note
11
12:
13:
14'
(Note 11)
ns
25
40
ns
0
50
ns
Either t h (RAS- R) or t h (CAS- R) must be satisfied for a read cycle.
tdls (CAS)maX defines the time at which the output achieves the open circuit condition and is not reference to VOH or VOL.
This is the value when td (RAS-CAS)~td (RAS-CAS)max. Test conditions; Load = 2T TL, C L = 100pF
This is the value when td (RAS-CAS)< td (RAS-CAS)max. When td (RAS-CAS)~td (RAS-CAS)maX, ta (RAS) will increase by the amount that
td (RAS-CAS) exceeds the value shown Test conditions; Load = 2T TL, CL = 100pF
Write Cycle
Symbol
Alternative
Parameter
M5K4164P-15
M5K4164P-20
Limits
Unit
Limits
Symbol
Min
tcw
Write cycle time
tsu (W-CAS)
Write setup time before CAS
th (CAS-W)
Max
Min
Max
260
330
twcs
-10
-10
ns
Write hold time after CAS
tWCH'
45
55
ns
th (RAS-W)
Write hold time after RAS
t WCR
95
120
ns
th (W-RAS)
RAS hold time after write
t RWL
45
55
ns
th (W-CAS)
CAS hold time after write
tcwL
45
55
ns
tW(W)
Write pulse width
twp
45
55
ns
tsu (D-CAS)
Data-in setup time before CAS
t OS
0
0
ns
th (CAS-D)
Data-in hold time after CAS
t DH
45
55
ns
th (RAS-D)
Data·in hold time after RAS
tDHR
95
120
ns
t RC
(Note 17)
• MITSUBISHI
.... ELECTRIC
ns
2-29
II
MITSUBISHI LSls
MSK4164P-1S, P-20
65 536-BIT (65 536-WORD BY I-BIT) DYNAMIC RAM
Read-Write and Read-Modify-Write Cycles
Alternative
Symbol
Parameter
M5K4164P-15
M5K4164P-20
Limits
Symbol
limits
Max
Min
Min
Unit
Max
tCRW
Read-write cycle time
(Note 15)
tRWC
280
340
ns
tCRMW
Read-modify-write cycle time
(Note 16)
tRMWC
310
390
ns
th (W-RAS)
RAS hold time after write
tRWL
45
55
ns
th (W-CAS)
CAS hold time after write
tCWL
45
55
ns
tW(W)
Write pulse width
twp
45
55
ns
tsu (R-CAS)
Read setup time before CAS
td (RAS-W)
Delay time,
t RCS
0
0
ns
tRWO
120
150
ns
tcwo
60
80
ns
0
0
ns
45
55
RAS to write
(Note 17)
td (CAS-W)
Delay time, CAS to write
(Note 17)
tSU(O-W)
Data-in setup time before write
t os
th (W-O)
Data-in hold time after write
t OH
tdis (CAS)
Output disable time
tOFF
ta (CAS)
CAS access time
(Note 13)
t CAC
ta (RAS)
RAS access time
(Note 14)
t RAC
Note 15:
= td
t CRWmin is defined as tCRW min
0
40
ns
0
50
ns
75
100
ns
150
200
ns
+ th (W-RAS) + tw (RASH) + 3t TLH(tTHL)
= ta (RAs)max + th (W-RAS) + tw (RAS H) + 3t TLH (tTHL)
(RAS-W)
16:
t CRM W min is defined as t CRM W min
17:
tsu (W-CAS). td (RAS-W). and td (CAS-W) do not define the limits of operation, but are included as electrical characteristics only.
When tsu (W-CAS);;;;;tsu (W-CAS)min. an early-write cycle is performed, and the data output keeps the high-impedance state
When td (RAS-W);;;;;td (RAS-W)min. and td (CAS-W);;;;;tsU(W-CAS)min a read-write cycle is performed, and (he data of the selected address will be read out
on the data output.
For all conditions other than those described above, the condition of data output (at access time and until CAS goes back to VI H) is not defined.
Page-Mode Cycle
Alternative
Symbol
Parameter
M5K4164P-15
M5K4164P-20
Limits
Symbol
Min
Limits
Max
Unit
Max
Min
to PGR
Page-mode read cycle ti me
t PC
145
190
ns
to PGW
Page-Mode write cycle time
tpc
145
190
ns
to PGRW
Page-Mode read-write cycle time
-
180
230
ns
to PGRMW
Page-Mode read-modify-write cycle time
-
190
245
ns
tw (CASH)
CAS high pulse width
60
80
ns
t CP
Automatic Refresh Cycle
Alternative
Symbol
Parameter
M5K4164P-15
M5K4164P-20
limits
Symbol
Unit
Limits
Max
Min
Min
Max
to(REF)
Automatic Refresh cycle time
t FC
260
330
ns
td (RAS-REF)
Delay time, RAS to REF
t RFO
100
120
ns
tw (REFL)
REF low pulse width
tFP
60
tw (REFH)
REF high pulse width
t FI
30
30
td (REF-RAS)
Delay time, REF to RAS
t FSR
30
30
ns
tsu (REF-RAS)
REF pulse setup iime before RAS
tFRO
295
360
ns
8000
8000
60
ns
ns
Self-Refresh Cycle
Symbol
Parameter
Alternative
M5K4164P-15
Min
td (RAS-REF)
Delay time, RAS to REF
t RFO
100
tw (REFL)
REF low pulse width
t FBP
8000
td ('REF-RAS)
Delay time, REF to RAS
tFBR
295
2-30
• MITSUBISHI
.... ELECTRIC
M5K4164P-20
Limits
Symbol
Limits
Max
Min
co
8000
Unit
Max
120
360
ns
00
ns
ns
MITSUBISHI LSls
MSK4164P-1S, P-20
65 536-BIT (65 536-WORD BY 1-BIT) DYNAMIC RAM
TIMING DIAGRAMS
Read Cycle
(Note 17)
(Note 18)
tOR
II
tW(RASL)
th (RAS-CAS)
-I
th (RAS-CA)
I
th (CAS-RAS)
tW(CASL)
COLUMN
ADDRESS
w
Lta(CAS)---~
--+--+---- tdiS(CAS)
I - - - - - - - - - t a (RAS) - - - - - - - - - - - 4
VOH -
Q
----------HIGH
IMPEDANCESTATE-------~~
DATA VALID
VOL -
Write Cycle (Early Write)
(Note 18)
tow
tW(RASL)
-I
th (RAS-CAS)
VIH
th(RAS-CA)
RAS
. I
VIL
th (CAS- RAS)
tW(RASH)
tW(CASL)
CAS
w
VIH
-
VIL
-
VIH
-
VIL
-~~~~~~~~~~~-----+_---~~~~~~~~~~~~~~~~~~~~~~~L
VIH
0
VIL
r - - - - - - t h (RAS-D)------I
VOH -
Q
VOL -
------------------HIGHIMPEDANCESTATE--------------------
• MITSUBISHI
"ELECTRIC
2-31
MITSUBISHI LSls
'MSK4164P-1S, P-20
65 536·BIT (65 536·WORD BY I-BIT) DYNAMIC RAM
Read-Write and Read-Modify-Write Cycles
(Note 18)
~~-----------------------------tORW/tORMW------------------------------------~
~--------------------------tW(RASL)------------------------------~
~------------------------_t h (RAS-CAS )-----------------------------1
~----_____c---------th (CAS- RAS) -----------------~
- -__~------~---------tW(CASL)----------------~
Ao-A7
w
V,H V,L
-~~~~~X~1I
Q
o
RAS-Only Refresh Cycle
(Note 19)
~---------------------tOR--------------------------~
t - - - - - - - - t W(RASL) ---------i
VOH -
Q
Note 17
VOL
_-----------------HIGH
~
IMPEDANCE
STATE------------------
Note 18, REF = V,H
Indicates the don't care input
19, CAS=REF=V,H,
~
2-32
The center-line indicates the high-impedance state
• MITSUBISHI
.... ELECTRIC
W, A7,
0 =don'tcare,
MITSUBISHI LSls
MSK4164P-1S, P-20
65 536-BIT (65 536-WORD BY I-BIT) DYNAMIC RAM
Page-Mode Read Cycle
(Note 18)
II
~-----------------------------tW(RASL)----------------------------------~
th(RAS-CAS)~
I
t h (RAS-CA)4
td (CAS-RAS)I
I
td (RAS-CAS)
Q
VOH VOL _---HIGH IMPEDANCE STATE
--t----t-.. t h (RA S- R )
~tW(RAS-R)
w
Page-Mode Write Cycle
(Note 18)
~-------------------------------tW(RASL)-------------------------------__~
th(RAS-CAS)--~
th (RAS-CA)i
td (CAS-RAS)
I
I
I.
td (RAS-CAS)
o
• MITSUBISHI
.... ELECTRIC
2-33
MITSUBISHI LSls
MSK4164P-1S, P-20
65 536-BIT (65 536-WORD BY 1-BIT) DYNAMIC RAM
Automatic Pulse Refresh Cycle (Multiple Pulse)
(Note 20)
td (REF-RAS)
Automatic Pulse Refresh Cycle (Single Pulse) (Note 20)
tsU(REF-RAS)
td ( RAS- REF)
td (REF-RAS)
tw( REFL)
REF
Self-Refresh Cycle
RAS
(Note 20)
VIH---4=
VIL -
: } -
~F-RAS)
td(RAS-REF)
REF
V,H V'L
-
~
c~----_tW_(REF_L)----~~Jf
_ __ _
__
~----------------------------------------~
Note 20. CAS, Addresses, D and Ware don't care.
Hidden Automatic Pulse Refresh Cycle
READ CYCLE
REFRESH CYCLE
REFRESH CYCLE
w
VIH
REF
-
-----t---t------~.~~~~
VIL
tdis(CAS)
ta(RAS)
Q
VOH VOL ----------~+
«
z
I--.....,..~---+---
10 I - - - - + - - - l =.....-T-=----I
O~----~----~----~----~
5.5
6.0
5.0
4.0
4.5
250
200
150
100
20
wa:w
a:o
~~
0
50
1----+----±;;"OO~----:.._~=""1
0
0..1-
a:
o
30
0
>-CJ
0.9
0.8
LOAD CAPACITANCE (pF)
SUPPLY VOLTAGE
AVERAGE SUPPLY CURRENT FROM Vee,
OPERATING MODE VS.
AMBIENT TEMPERATURE
40
fE~
~::l
fE,;::
t~=330ns
IZ
I
20
tc=500ns-
>-CJ
30
0
0
wa:w
a:o
:JO
u~
V
y~
~~
0..1-
t c= 1000ns
10
:J«
CJ)a:
WW
CJo..
«0
«0
8S
8S
>
,
10
>
«
«
25
50
75
100
o
AMBIENT TEMPERATURE Ta ('C)
2-36
~
20
>-CJ
I
a:~
0..1:J«
CJ)a:
CJo..
>
o E
30
a:w
a:o
WW
Ta=25'cJ
Vee=5.5V
u
tc=260ns
a
zw-a
u~
AVERAGE SUPPLY CURRENT FROM Vee,
OPERATING MODE VS. FREQUENCY
u·
I
I-
:JO
Vee (V)
40
VCC=5.~V
>
~::l
o E
Ta ('C)
>
IZ
8
100
Ta=25'C
u·
1.2
til
«
75
AVERAGE SUPPLY CURRENT FROM Vee,
OPERATING MODE VS. SUPPLY VOLTAGE
u
II:
u
u
50
40~----~----~----~----'
Ta=25'C
Vee=5V
1.1
25
AMBIENT TEMPERATURE
1.3
(j)
~
1=
o
Vee (V)
NORMALIZED ACCESS TIME VS.
LOAD CAPACITANCE
tf
/
a:
0.6
~
~
l/
~
Z
«
1.0
u
0
CJ)
--
1=
II:
:J
1.2
w
~
~
Vee=5V
(j)
o
FREQUENCY
• MITSUBISHI
"'ELECTRIC
f (¢) (MHz)
/
MITSUBISHI LSls
MSK4164P-1S, P-20
85 538-BIT (85 538-WORD BY I-BIT) DYNAMIC RAM
SUPPLY CURRENT FROM Vee,
STANDBY MODE VS.
AMBIENT TEMPERATURE
SUPPLY CURRENT FROM Vee,
STANDBY MODE VS. SUPPLY VOLTAGE
2.8
2.8
Vee=5.5V
Ta=25°C
u' ""
u«
>
E
I
2.4
~~
f- w
0
w 0
a: ::2'
2.0
/
a:
=>
u
~
=>
(J)
)-
co
0
z
~
::2'
0
N
0
~~
zo
~ ........
2.0
wo
~::2'
=>)-
)-0
;;:~
1.6
Cl..f~(J)
5.0
1. 2 0
6.0
5.5
Vee (V)
25
75
50
AMBIENT TEMPERATURE
40~----~----~----~-----'
Ta=25°C
100
Ta CC)
AVERAGE SUPPLY CURRENT FROM Vee,
REFRESH MODE VS.
AMBIENT TEMPERATURE
40
u'
u
Vee=5.5V
>
>
::2'""
::2'""
0«
~ ~
0«
30J------+---+----t----t
§g
w w
to (REF)= 260ns
---+- 330ns
o:w
=>0
u 0
to (REF)
20
)-::2'
--'I
Cl..(J)
Cl.. w
=>0:
(J)LL
--'I
(90:
30
0:-
201----+--::::;;;."...,."F'-
)-::2'
Cl..(J)
Cl.. w
=>0:
(J)LL
~~
§§
a:a:w
a8
t5
101-----1""""'=--+_
~
I
to (REF)=500ns
10
to (REF)=1000ns
>
40
6.0
Vee (V)
::2'
0""
0:«
LL E
30
40~----~----~----~-----'
Ta = 25°C
3 0 t - - - + - - - + - -t o (pe)=145ns
f-~
Z ..
0:-
./
o:w
20
V~
)-::2'
--'I
Cl..(J)
Cl.. w
=>0:
(J)LL
(90:
Ta (OC)
>
§§
w w
100
AVERAGE SUPPLY CURRENT FROM Vee,
PAGE MODE VS. SUPPLY VOLTAGE
u'
u
Ta =25°C
Vee=5.5V
0«
a8
75
50
25
AMBIENT TEMPERATURE
::2'""
~ ~
o
o
~
AVERAGE SUPPLY CURRENT FROM Vee,
REFRESH MODE VS. FREQUENCY
10
,;'"
w
Uo
201---~1----::::;;;;;j,.ooo"'=
)-0
;;:::2'
Cl..W
=>(9
./
(J)
;;;
;;;
o~
o~
fI<1:
I.l.
so
~.
Vee=S.SV
>
E
..
30
-
I-~
Z
w Q
fI Q
fI::>w
Uo
fI<1:
to(PG)-14Sns
r
-
20
~w
w~
(:J
«
ffi
10
to (po
>
«
r
to (PG) = SOOns
::>(:J
(fl«
o
o
so
2S
.
I- ~
Z Q
w
fI Q
fI-
30
~w
t o (PG i=190nS
>-0
0:;;;
40
E
I.l.
20
~w
::>(:J
(fl~
1000",
7S
Uo
>-0
0:;;;
w
(:J
-(fl
--,W
I
--'w
30
I- Zw
Wo
fIo
~;;;
>-(fl
-
Te (REF) = 260ns
-
20
T
I
Te (REF) = 330ns
~a:
~fI
~u..
~I.l.
>
«
Vee=S.SV
;;; E
;;;<1:
::>w
(flfI
wo
(:JI«::>
ffi«
40
u'
~:t
>~
fI
'"
I.l.
Q
--
FREQUENCY f(¢) (MHz)
AVERAGE SUPPLY CURRENT FROM Vee,
AUTO REFRESH MODE
VS. SUPPLY VOLTAGE
0-5
~
-----
AMBIENT TEMPERATURE Ta ("C)
u'
u
...----~
10~----4-----~--~__----~
::>w
(flfI
wo
(:JI«::>
ffi
-Ul
--'w
./
20
~fI
~I.l.
::>w
(flfI
wo
(:JI«::>
ffi
'"
;;; Q
0:=
::E~
as;;;
fII
fI(fl
::>w
"
u::E
>-W
o:fI
~
~
V
~u..
::>--'
(flW
(fl
o
o
4.0
4.S
5.0
S.S
SUPPLY VOLTAGE Vee (V)
FREQUENCY f(¢) (MHz)
2-38
~
1-0
• MITSUBISHI
.... ELECTRIC
6.0
MITSUBISHI LSls
MSK4164P-1S, P-20
65 536-BIT (65 536-WORD BY 1-BIT) DYNAMIC RAM
SUPPLY CURRENT FROM Vee,
SELF REFRESH MODE
VS. AMBIENT TEMPERATURE
RAS, CAS, W, REF INPUT VOLTAGE
VIH1, VIL1 VS. SUPPLY VOLTAGE
2. 5 r-----r----.,....--~--.,
w
« 2:
Vee=5.5V
<.9
~
.«
0
UE
u~
> '"
>
:J
:>
2.0 1 - - - - + - - - - t - - - V I H 1 (min)
f-
2 ()
i{
O!:?
........
CI:
w
LLO
f-O
~2
~ """'-
CI:I
CI:Cfl
~w
u~
>-w
~
- --
I~
1.51--=--+----+---
I~
~
I~
t~
~--'
Cfl~
o
I
:>
1.01----+----+----+----1
O. 5 L-._ _"'--_ _......_ _. J -_ _
4.0
4.5
5.0
5.5
6.0
~
o
25
50
100
75
AMBIENT TEMPERATURE Ta (OC)
SUPPLY VOLTAGE Vee (V)
Ao~A7' DIN INPUT VOLTAGE VIH2, VIL2
RAS, CAS, W, REF INPUT VOLTAGE
VIH1, VIL 1 VS. AMBIENT TEMPERATURE
VS. SUPPLY VOLTAGE
2:
2.5
~
Vee=5jV
w
~
0
f-
i{
Z
:J
:>
Ta=25°C
:>I
-
2.0
I
:>
I~
r----.,.---.,....--..,.....--.,
:>
<.9
« 2:
>
2.5
VIH1 (min)
w
VIL1 (max)
«
~
§;
T-
1.5
2.01---+---+---
<.9
1. 51-~~+----=......"""""'=-----+------t
f-
I~
i{
Z
I~
~
1.01---+----+----t------1
z
1.0
o
~
0.5
:tI
o
25
50
O. 5L-._ _......_ _. J -_ _...I-_ _
4.0
4.5
5.0
5.5
6.0
~
100
75
AMBIENT TEMPERATURE Ta CC)
SUPPLY VOLTAGE Vee (V)
Ao~A7,
DIN INPUT VOLTAGE VIH2, VIL2
VS. AMBIENT TEMPERATURE
2:
SUPPL Y CURRENT VS. TIME
2.5
N
Vee=5.5v
..J
:>
(fJ
(fJ
N
~
-
2.0
w
<.9
«
VIH2(min)
1VIL2(max)
f-
--'
§;
1.5
f-
~
~
~
1.0
~
~
I
:t
f-
u
Z
r5
c.3
!:?
CI:
CI:
i{
0.5
0
25
50
RAS
CAS
100
80
Icc 60
(mA) ~g
0
100
80
Iss 60
(mA) ~8
0
100
75
AMBIENT TEMPERATURE Ta (OC)
• MITSUBISHI
..... ELECTRIC
50ns/DIVISION
TIME
t
2-39
MITSUBISHI LSls
MSK4164P-1S, P-20
65 536-BIT (65 536-WORD BY I-BIT) DYNAMIC RAM
SUPPLY CURRENT VS. TIME
eVe
S.OV
100
80
Icc ~8
(mA) 20
o
100
80
Iss 60
(mA)
~g
o
SOns/DIVISION
TIME
2-40
t
• MITSUBISHI
.... ELECTRIC
MITSUBISHI LSls
MSK4164NP-1S, NP-20
65 536-BIT (65 536-WORD BY I-BIT) DYNAMIC RAM
DESCRIPTION
PIN CONFiGURATION (TOP VIEW)
This is a family of 65 536-word by 1-bit dynamic RAMs,
fabricated with the high performance N-channel silicongate
MOS process, and is ideal for large-capacity memory
NC
systems where high speed, low power dissipation, and low
VSS
DATA INPUT
costs are essential. The use of double-layer polysilicon
process technology and a single-transistor dynamic storage
15
WRITE
CONTROL INPUT
(DV)
'-CAS ~~~g~EN 1~~8fESS
14 _
Q
DATA OUTPUT
ROW ADDRESS
STROBE INPUT
cell privide high circuit density at reduced costs, and the
use of dynamic circuitry including sense amplifiers assures
low power dissipation. Multiplexed address inputs permit
ADDRESS INPUTS
ADDRESS INPUTS
both a reduction in pins to the standard 16-pin package
configuration and an increase in system densities. The
M5K4164NP operates on a 5V power supply using the
on-chip substrate bias generator.
(5V)
FEATURES
Vee
Outline 16P4
• Performance ranges
Access time
(max)
(ns)
Cycle time
(min)
(ns)
Power dissipation
(typ)
(mW)
M5K4164NP-15
150
260
200
M5K4164NP-20
200
330
170
Type name
•
Standard 16-pin package
•
•
•
Single 5V±10% supply
Low standby power dissipation:
Low operating power dissipation:
•
22mW (max)
M5K4164NP-15
275mW (max)
M5K4164NP-20
250mW (max)
All input terminals have low input capaciatance and are
directly TTL-compatible
•
Output is three-state and directly TTL-compatible
•
128 refresh cycles every 2ms
(16K dynamic RAMs M5K4116P, S compatible)
•
•
CAS controlled output allows hidden refresh
Output data can be held infinitely by CAS
•
Interchangeable with Mostek's MK4564 and
Motorola's MCM6665 in pin configuration
APPLICATION
•
Unlatched output enables two-dimensional chip selec-
•
•
tion and extended page boundary
Early-write operation gives common I/O capability
Read-modify-write, RAS-only refresh, and page-mode
•
Main memory unit for computers
capabilities
BLOCK DIAGRAM
DATA INPUT
WRITE CONTROL INPUT
COL~-j0RNo~f9~~0f
Vee (SV)
CAS
ROW ADDRESS
STROBE INPUT
Vss (OV)
MEMORY CELL
(64 ROWS X 256 COLUMNS)
SENSE REFRESH AMPLIFIER
l
MEMORY CELL
(64 ROWS X 256 COLUMNS)
AO
AI
ADDRESS INPUTS
f-a:
:;)UJ
Az
COLUMN DECODER
A3
A4
MEMORY CELL
(64 ROWS X 256 COLUMNS)
As
SENSE REFRESH AMPLIFIER
~ ~
:;)::1
A6
A)
14
Q DATA OUTPUT
ocn
MEMORY
(64 ROWS
X 256 CELL
COLUMNS)
J'
COLUMN DECODER
~---------------
-------------
'MITSUBISHI
.... ELECTRIC
-----------------
2-41
II
MITSUBISHI LSls
M5K4164NP-15, NP-20
65 536-BIT (65 536-WORD BY I-BIT) DYNAMIC RAM
FUNCTION
The M5K4164NP provides, in addition to normal read,
write, and read-modify-write operations, a number of other
functions, e.g., page mode, RASconly refresh, and delayedwrite. The input conditions for each are shown in Table 1.
Table 1 Input conditions for each mode
Output
Inputs
Operation
RAS
CAS
W
0
Row
address
Column
address
Q
Refresh
Read
ACT
ACT
NAC
ONC
APO
APO
VLO
YES
Write
ACT
ACT
ACT
VLO
APD
APO
OPN
YES
Read-modify-write
ACT
ACT
ACT
VLO
APO
APO
VLO
YES
RAS-only refresh
ACT
NAC
ONC
ONC
APO
ONC
OPN
YES
Hidden refresh
ACT
ACT
ONC
ONC
APO
ONC
VLO
YES
Standby
NAC
ONC
ONC
ONC
ONC
ONC
OPN
NO
Remarks
Page mode
identical except
refresh is NO
Note: ACT: active, NAC : nonactive, ONC : don't care, VLO : valid, APO : applied, OPN : open.
SUMMARY OF OPERATIONS
Addressing
To select one of the 65536 memory cells in the
M5K4164NP the 16-bit address signal must be multiplexed
into 8 address signals, which are then latched into the
on-chip latch by two externally-applied clock pulses. First,
the negative-going edge of the row-ad dress-strobe pulse
(RAS) latches the 8 row-address bits; next, the negativegoing edge of the column-address-strobe pulse (CAS)
latches the 8 column-address bits. Timing of the RAS and
CAS clocks can be selected by either of the following two
methods:
1. The delay time from RAS to. CAS td (RAS-CAS) is set
between the minimum and maximum values of the
limits. In this case, the internal CAS control signals are
inhibited almost until td(RAS-CAS) max ('gated CAS'
operation). The external CAS signal can be applied with
a margin not affecting the on-chip circuit operations, e.g.
access time, and the address inputs can be easily changed
from row address to column address.
2. The delay time td(RAS-CAS) is set larger than the
maximum value of the limits. In this case the internal
inhibition of CAS has already been released, so that the
internal CAS control signals are controlled by the
externally applied CAS, which also controls the access
time.
Data Input
Data to be written into a selected cell is strobed by the later
of Yle two negative transistons of W input and CAS input.
Thus when the W input makes its negative transition prior
to CAS input (early write), the data input is strobed by
CAS, and the negative transition of CAS is set as the
2-42
reference point for set-up and hold times. In the read-write
or read-modify-write cycles, however, when the IN input
makes its negative transition after CAS, the IN negative
transition is set as the reference point for setup and hold
times.
Data Output Control
The output of the M5K4164NP IS In the high-impedance
state when CAS is high. When the memory cycle in progress
is a read, read-modify-write, or a delayed-write cycle, the
data output will go from the high-impedance state to the
active condition, and the data in the selected cell will be
read. This data output wil! have the same polarity as the
input data. Once the output has entered the active
condition, this condition will be maintained until CAS goes
high, irrespective of the condition of RAS.
The output will remain in the high-impedance state
throughout the entire cycle in an early-write cycle.
These output conditions, of the M5K4164NP, which can
readily be changed by controlling the timing of the write
pulse in a write cycle, and the width of the CAS pulse in a
read cycle, offer capabilities for a number of applications,
as follows.
1. Common I/O Operation
If all write operations are performed in the early-write
mode, input and output can be connected directly to give' a
common I/O data bus.
2 Data Output Hold
The data output can be held between read cycles, without
lengthening the cycle time. This enables extremely flexible
clock-timing settings for RAS and CAS.
• MITSUBISHI
' " ELECTRIC
MITSUBISHI LSls
MSK4164NP-1S, NP-20
65 536·BIT (65 536·WORD BY I.BIT) DYNAMIC RAM
3. Two Methods of Chip Selection
Since the output is not latched, CAS is not required to keep
the outputs of selected chips in the matrix in a high·
impedance state. This means that CAS and/or RAS can
both be decoded for chip selection.
4. Extended·Page Boundary
By decoding CAS, the page boundary can be extended
beyond the 256 column locations in a single chip. In this
case, RAS must be applied to all devices.
Page- Mode Operation
This operation allows for multiple-column addressing at the
same row address, and eliminates the power dissipation
associated with the negative-going edge of RAS, because
once the row address has been strobed, RAS is maintained.
Also, the time required to strobe in the row address for the
second and subsequent cycles is eliminated, thereby decreasing the access and cycle times.
Power Dissipation
Most of the circuitry in the M5K4164NP is dynamic, and
most of the powe~issipated when addresses are strobed.
Both RAS and CAS are decoded and applied to the
M5K4164NP as chip-select in the memory system, but if
RAS is decoded, all unselected devices go into stand-by
independent of the CAS condition, minimizing system
power dissipation.
Power Supplies
The M5K4164NP operates on a single 5V power supply.
A wait of some 500J.Ls and eight or more dummy cycles
is necessary after power is applied to the device before
memory operation is achieved.
Refresh
Each of the 128 rows (Ao ,...., A 6 ) of the M5 K4164NP must
be refreshed every 2 ms to maintain data. The methods of
refreshing for the M5K4164NP are as follows.
1. Normal Refresh
Read cycle and Write cycle (early write, delayed write or
read-modify-write) refresh the selected row as defined by
the low order (RAS) addresses. Any write cycle, of course,
may change the state of the selected cell. Using a read,
write, or read-modify-write cycle for refresh is not recommended for systems which utilize "write-OR" outputs since
output bus contention will occur.
2. RAS Only Refresh
A RAS-only refresh cycle is the recommended technique
for most applications to provide for data retention. A
RAS-only refresh cycle maintains the output in the
high-impedance state with a typical power reduction of
20% over a read or write cycle.
3. Hidden Refresh
A features of the M5K4164NP is that refresh cycles may
be performed while maintaining valid data at the output pin
by extending the CAS active time from a previous memory
read cycle. This feature is refered to as hidden refresh.
Hidden refresh is performed by holding CAS at V I Land
taking RAS high and after a specified precharge period,
executing a RAS-only cycling, but with CAS held low.
The advantage of this refresh mode is that data can be
held valid at the output data port indefinitely by leaving
the CAS asserted. In many applications this eliminates the
need for off-chip latches.
. • MITSUBISHI
"ELECTRIC
2-43
B
MITSUBISHI LSls
MSK4164NP-1S, NP-20
65 536·BIT (65 536·WORD BY I·BIT) DYNAMIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol
Paramater
Conditions
Unit
Limits
-1-7
V
-1-7
V
VCC
Supply voltage
VI
Input voltage
Va
Output voltage
-1-7
V
10
Output current
50
mA
700
mW
With respect to Vss
Pd
Power dissipa,tion
Topr
Operating free-air temperalUre range
Tstg
Storage temperature range
Ta =25'C
'C
-65-150
RECOMMENDED OPERATING CONDITIONS
(Ta=0-70'C, unless otherwise noted) (Note 1)
Limits
Symbol
'C
0-70
Unit
Parameter
Min
Nom
Max
VCC
Supply voltage
4 _5
5
5.5
V
Vss
Supply voltage
0
0
0
V
VIH
High-level input voltage. all inputs
2.4
6_5
V
VIL
Low-level input voltage. all inputs
-2
0.8
V
Note 1: All voltage values are with respect to Vss
ELECTRICAL CHARACTERISTICS
± 10%,
(Ta=0-70'C, VCC=5V
VSS=OV, unless otherwise nowd) (Note 2)
Limits
Symbol
Test conditions
Parameter
Min
Typ
Max
Unit
VOH
High-level output voltage
IOH=-5mA
2.4
VCC
V
VOL
Low-level output voltage
IOL=.4·2mA
0
0.4
V
loz
Off-state output current
Q floating
OV ~VOUT ~5. 5V
-10
10
~A
II
Input current
OV~VIN~6.5V ,
All other pins = OV
-10
10
~A
ICC1(AV)
Average supply current from Vee.
operating (Note 3. 4)
M5K4164NP- 15
RAS,CAS cycling
50
mA
M5K4164NP-20
t CR =t CW = min output open
45
mA
4
mA
RAS=VIH output open
Supply current from Vee. standby
ICC2
I CC3(AV)
I CC4(AV)
cycl ing
40
mA
t C(REF)= min. output open
35
mA
M5K4164NP-15
RAS=VIL, CAS cycling
40
mA
tv15K4164NP-20
tCPG= min. output open
35
mA
5
pF
Average supply current from Vee.
M5K4164NP-15
RAS
refreshing (Note 3)
M5K4164NP- 20
Average supply current from Vee.
page mode (Note 3. 4)
CAS=VIH
CI (A)
Input capacitance. address inputs
CI (D)
Input capacitance. data input
VI=VSS
5
pF
CI (W)
Input capacitance. write control input
f=lMHz
7
pF
CI (RAS)
Input capacitance. RAS input
VI=25mVrms
10
pF
CI (CAS)
Input capacitance. CAS input
10
pF
Co
Output capacitance
7
pF
Note 2:
VO=VSS, f= 1 MHz, VI=25mVrms
Current flowing into an IC is positive; out is negative.
3
ICC 1 (AV), I CC3(AV), and I CC4 (AV) are dependent on cycle rate. Maximum current is measured at the fastest cycle rate.
4:
Icc 1 (AV) and I CC4(AV) are dependent on output loading. Specitred values are obtained with the output open.
2-44
'MITSUBISHI
"ELECTRIC
MITSUBISHI LSls
MSK4164NP-1S, NP-20
65 536-BIT (65 536-WORD BY 1-BIT) DYNAMIC RAM
TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write, Refresh, and Page-Mode Cycle)
(Ta =0-70·C, Vcc=5V
± 10%, VSS=OV, unless otherwise noted, See notes 5, 6 and 7)
M5K4164NP-15
Symbol
Alternative
Parameter
M5K4164NP-20
Limits
Symbol
Min
teRF
Refresh cycle time
tREF
t W(RASH)
RAS high pulse width
t RP
100
t W(RASL)
RAS low pulse width
t RAS
150
t W(CASL)
CAS low pulse width
tCAS
75
Unit
Limits
Max
Min
Max
2
2
120
ms
ns
10000
200
10000
ns
(Xl
100
(Xl
ns
t W(CASH)
CAS high pulse width
t CPN
35
40
t h (RAS-CAS)
CAS hold time after RAS
tCSH
150
200
ns
t h (CAS-RAS)
RAS hold time after CAS
t RSH
75
100
ns
td (CAS-RAS)
Delay time, CAS to RAS
(Note 9)
tCRP
-20
td(RAS-CAS)
Delay time, RAS to
C"AS"
(Note 10)
t RCO
25
t SU(RA-RAS)
Row address setup time before
tASR
0
0
tSU(CA-CAS)
Column address setup time before CAS
t ASC
-5
-5
ns
t h (RAS-RA)
Row address hold time after
t RAH
20
25
ns
ns
(Note 8)
RA"S
RA"S
C"AS"
Column address hold time after
t CAH
25
35
t h (RAS-CA)
Column address hold time after ~
tAR
95
120
Transition time
tT
3
35
ns
30
t h(CAS-CA)
t THL
ns
-20
75
II
100
ns
ns
ns
3
50
ns
t TLH
Note 5:
6:
7:
8:
9:
10:
An initial pause of 500J,ls is required after power-up followed by any eight RAS or RAS/CAS cycles before proper device operation is achieved.
The switching characteristics are defined as t THL =t TLH =5ns.
Reference levels of input signals are VIH min. and V 1L max. Reference levels for transition time are also between VIH and VIL.
Except for page·mode.
tdICAS-RAS) requirement is only applicable for RAS/CAS cycles preceeded by a CAS only cycle (i.e., For systems where CAS has not been decoded with RAS.)
Operation within the td (RAS-CAS) max limit insures that t a (RAS) max can be met. td (RAS-CAS)maX is specified reference point only;if
td (RAS-CAS) is greater than the specified td (RAS-CAS) max limit, then access time is controlled exclusively by ta ICAS)'
td (RAS-CAS)min = th (RAS-RA)min +2t THL(t
SWITCHING CHARACTERISTICS
Read Cycle
Symbol
TLH)
+ t SU(CA-CAS)min.
(Ta =0-70·C, Vcc=5V
± 10%,
VSS=OV, unless otherwise noted)
Alternative
Parameter
M5K4164NP-15
Min
te R
Read cycle time
t RC
tsu (R-CAS)
Read setup time before CAS
t RCS
M5K4164NP-20
Limits
Symbol
Limits
Max
Unit
Max
Min
260
330
ns
0
0
ns
ns
th (CAS-R)
Read hold time after CAS
(Note 11)
tRCH
0
0
th (RAS-R)
Read hold time after RAS
(Note 11)
tRRH
20
25
tdis (CAS)
Output disable time
(Note 12)
tOFF
0
40
ns
0
50
ns
ta (CAS)
CAS access time
(Note 13)
tCAC
75
100
ns
ta (RAS)
RAS access time
(Note 14)
tRAC
150
200
ns
Note
Note
Note
Note
11:
12:
13:
14:
Either th (RAS-R) or th (CAS-R) must be satisfied for a read cycle.
tdis (CAS)maX defines the time at which the output achieves the open circuit condition and is not reference to VOH or VOL.
This is the value when td (RAS-CAS);;:;; td (RAS-CAs)max. Test conditions; Load ~ 2T TL, CL ~ 100pF
This is the value when td (RAS-CAS)< td (RAS-CAS)max. When td (RAS-CAS);;:;;td (RAS-CAS)maX, ta (RAS) will increase by the amount that
td (RAS-CAS) .exceeds the value shown. Test conditions; Load ~ 2T TL, C L ~ 100pF
Write Cycle
Alternative
Symbol
M5K4164NP-15
Parameter
M5K4164NP-20
Limits
Min
tew
Write cycle time
tsu (W-CAS)
Write setup time before CAS
Max
Min
Max
260
330
ns
twcs
-10
-10
ns
ns
t RC
(Note 17)
Unit
Limits
Symbol
th (CAS-W)
Write h01d time after CAS
t WCH
45
55
th (RAS-W)
Write hold time after RAS
tWCR
95
120
ns
th (W-RAS)
RAS hold time after write
t RWL
45
55
ns
th (W-CAS)
CAS hold time after write
tCWL
45
55
ns
tW(W)
Write pulse width
twp
45
55
ns
tsu (O-CAS)
Data-in setup time before CAS
t OS
0
0
ns
th (CAS-D)
Data-in hold time after CAS
t OH
45
55
ns
th (RAS-O)
Data-in hold time after RAS
t OHR
95
120
ns
• MITSUBISHI
"ELECTRIC
2~45
MITSUBISHI LSls
MSK4164NP-1S, NP-20
65 536·BIT (65 536·WORD BY 1.BIT) DYNAMIC RAM
Read-Write and Read-Modify-Write Cycles
Alternative
Symbol
Parameter
M5K4164NP-15
M5K4164NP-20
Limits
Symbol
Limits
Max
Min
Min
Unit
Max
tORw
Read-write cycle time
(Note 15)
tRWC
280
340
ns
tORMW
Read-modify-write cycle time
(Note 16)
tRMWC
310
390
ns
ns
th (W-RAS)
RAS hold time after write
tRWL
45
55
th (W-CAS)
CAS hold time after write
tcwL
45
55
ns
tW(W)
Write pulse width
twp
45
55
ns
ns
tsu (R-CAS)
Read setup time before
0
0
Delay time.
CAS
liAS to write
tRCS
td (RAS-W)
(Note 17)
tRWO
120
150
ns
td (CAS-W)
Delay time.
CAS to write
(Note 17)
tcwo
60
80
ns
tsu (O-w)
Data-in setup time before write
t os
0
0
ns
th (W-O)
Data-in hold time after write
t OH
45
55
tdis (CAS)
Output disable time
tOFF
ta (CAS)
CAS access time
(Note 13)
tCAC
ta (RAS)
RAS access time
(Note 14)
t RAC
40
0
ns
50
ns
75
100
ns
150
200
ns
0
Note 15: toRwmin is defined as tORwmin=td (RAS-W)+th(W-RAS)+tw (RASH)+3tTLH(tTHL)
16: t ORMW min is defined as t ORM W min = ta (RAs)maX + th (W-RAS) + tw (RAS H) + 3t TLH(tTHL)
17: tsu (W-CAS), td (RAS-W), and td (CAS-W) do not define the limits of operation. but are included as electrical characteristics only_
When tsu (W-CAS);;;:; tsu (W-CAs)min, an early-write cycle is performed. and the data output keeps the high-impedance state.
When td (RAS-W);;;:;td (RAS-W)min. and td (CAS-W);;;:;tsu (W-CAs)min a read-write cycle is performed. and the data of the selected address will be read out
on the data output.
For all conditions other than those described above. the condition of data output (at access time and until CAS goes back to VI H) is not defined.
Page-Mode Cycle
Alternative
Symbol
Parameter
M5K4164NP-15
M5K4164NP-20
Symbol
Min
Unit
Limits
Limits
Max
Min
Max
to PGR
Page-mode read cycle time
tpc
145
190
ns
to PGW
Page-Mode write cycle time
tpc
145
190
ns
to PGRW
Page-Mode read-write cycle time
-
180
230
ns
tOPGRMW
Page-Mode read-modify-write cycle time
-
190
245
ns
tw (CASH)
CAS high pulse width
tcp
60
80
ns
2-46
• MITSUBISHI
.... ELECTRIC
MITSUBISHI LSls
MSK4164NP-1S, NP-20
65 536-BIT (65 536-WORD BY I-BIT) DYNAMIC RAM
TIMING DIAGRAMS
(Note 17)
Read Cycle
tOR
II
tW(RASL)
th(RAS-CAS)
-I
th(RAS-CA)
I
th(CAS- RAS)
tW(CASL)
COLUMN
ADDRESS
--+---t--
t - - - - - - - - - t a ( R A S ) --------~
tdiS(CAS)
VOH -
Q
VOL -
- - - - - - - - - - H I G H IMPEDA'NCE STATE-------~Ml
DATA VALID
Write Cycle (Early Write)
r.~--------------tow-----------------·~I
1 - - - - - - - - - - - t W ( R A S L ) - - - - - - - - - - -.....-..j1
_ _ _ _ _'"""\.1
I - - - - - - - - - - t h (RAS-ICASl------------l1
f----th(CAS-CA)
.
1 - - - - - - t h(CAS- RAS)---~~
tW(RASH)
---+---...!-.--tW(CASL)-----.I
VIL
- _ _ _ _",
w
VIH
0
VIL
f-----th(RAS-Dl-----.-l
VOH Q
VOL -
-----------------HIGHIMPEDANCESTATE--------------------
• MITSUBISHI
.... ELECTRIC
2-47
MITSUBISHI LSls
MSK4164NP-1S, NP-20
85 538·BIT (85 538·WORD BY 1-BIT) DYNAMIC RAM
Read-Write and Read-Modify-Write Cycles
~~-------------------------------tCRW/tCRMW------------------------------------~
~----------------------------tW(RASL)------------------------------~
1-------------------------- til( RAS- CAS ) - - - - - - - - - - - - - - - - - - - - - - - - - - - < - 4
'--------tll(RAS- CA ) - - - - - - - - i
RAS
~-----_:__---------t 11 (CAS- RAS )------------------~
-__<-+~---------------tW(CASL)--------------~~
CAS
Ao-A7
VIH VIL -
i":"",Wl
W
Q
VIH VIL -
td(CAS-W)
L,,,CA'>
tdIS(CAS)
VOH -
II
DATA VALID
o
RAS-Only Refresh Cycle
(Note 18)
~----------------tcR-----------------------~~
~----- tW(RASL ) - - - - - - - - 1
RAS
VOH Q
Note 17
VOL
_------------------------------------HIGH IMPEDANCE STATE-------------------------------------.
~
Indicates the don't care input
Note 18_
~
2-48
CAS=V,H,
The center-line indicates the high-impedance state
• MITSUBISHI
;"ELECTRIC
W,
A7, 0
= don't care.
MITSUBISHI LSls
MSK4164NP-1S, NP-20
65 536-BIT (65 536-WORD BY I-BIT) DYNAMIC RAM
Page-Mode Read Cycle
~----------------------------tW(RASL)--------------------------------~
th(RAS-CAS)~
I
th(RAS-CA)i
td (CAS-RAS)
I
I
to PGR---'------..I
td (RAS-CAS)
CAS
VOH -
Q
V OL -
--HIGH IMPEDANCE STATE
w
Page-Mode Write Cycle
~------------------------------tW(RASL)------------------------------~
t h (RAS-CAS)----,
th(RAS-CA),
td (CAS-RAS)
I-
I
I
I
--~--~
td(RAS-CAS)
CAS
w
D
• MITSUBISHI
;'ELECTRIC
2-49
MITSUBISHI LSls
MSK4164NP-1S, NP-20
6S S36-BIT (6S S36-WORD BY 1-BIT) DYNAMIC RAM
Hidden Refresh Cycle
READ CYCLE
REFRESH CYCLE
tOR
tOR
REFRESH CYCLE
tOR
tW(CASH)
th(RAS-RA)
W
VIH
VIL
tdis (CAS)
Q
VOH
DATA VALID
VOL
2-50
• MITSUBISHI
~ELECTRIC
MITSUBISHI LSls
MSK4164NP-1S, NP-20
65 536-BIT (65 536-WORD BY 1-BIT) DYNAMIC RAM
TYPICAL CHARACTERISTICS
NORMALIZED ACCESS TIME VS.
AMBIENT TEMPERATURE
NORMALIZED ACCESS TIME VS.
Vee SUPPLY VOLTAGE
Ta=25°C
4:
~
~
1.2
'"'"
j:::
1.0
4:
8N
:::;
4:
:J
"'
~
(/)
~
u
u
Vee= 5V
(j)
4:
~
0.8
:2:
a:
0
z
1.2
j:::
~
u
u
4:
:::;
4:
0.8
:2:
a:
0
z
0.6
4.0
5.0
4.5
5.5
6.0
o
25
SUPPLY VOLTAGE Vee (V)
1.3
(/)
(/)
~~
1.2
a: E
u..'";::
IZ
1.1
W
U
u
4:
8N
~
:2:
a:
1.0
0.9
0
40~----~----~----~-----,
>
~
j:::
------ ---
~
~
30~----~----~~--
0
0
wa:w
a:o
::;)0
u:2:
20~--~~----+-----
>-t:)
a:~
a. I-
~~
WW
~~
10~----+-----~~
>
4:
O~
o
50
100
150
250
200
U
40
Vee=5.~V
.I
tc = 260ns
:2:~
o E
~'::
~.9
a:w
a:o
::;)0
u:2:
20
>-t:)
~z
~~a:
WW
t:)a.
4: 0
~
____
5.0
00
IZ
.I
::;)0
tc =500ns
wa:w
a:o
u:2:
I
(/)a:
____
5.5
~
6.0
Vee (V)
Ta=25°C
Vee=5.5V
30
20
V~
>-t:)
a:~
a. I::;)4:
WW
t:)a.
4: 0
a:
~
40
u'
u
>
:2:~
o E
tic = 330ns
tc = 1000ns
10
____
AVERAGE SUPPLY CURRENT FROM Vee,
OPERATING MODE VS. FREQUENCY
3:~
30
I- 0
~
4.5
SUPPLY VOLTAGE
AVERAGE SUPPLY CURRENT FROM Vee,
OPERATING MODE VS.
AMBIENT TEMPERATURE
u
____
4.0
LOAD CAPACITANCE (pF)
>
__~~~-i
~
z
0.8
100
75
AVERAGE SUPPLY· CURRENT FROM Vee,
OPERATING MODE VS. SUPPLY VOLTAGE
u'
u
Ta=25°C
Vee= 5V
4:
~
50
AMBIENT TEMPERATURE Ta (OC)
NORMALIZED ACCESS TIME VS.
LOAD CAPACITANCE
(j)
~
---
1.0
8N
........
/
V
~
(/)
0.6
:J
II
1.4
1.4
(j)
10
/
V
/
,
a:
W
W
>
4:
>
4:
25
50
75
100
AMBIENT TEMPERATURE Ta ("C)
00
FREQUENCY
• MITSUBISHI
.... ELECTRIC
t(
<1»
(MHz)
2-51
MITSUBISHI LSls
MSK4164NP-1S, NP-20
65 536-BIT (65 536-WORD BY I-BIT) DYNAMIC RAM
SUPPLY CURRENT FROM Vee,
STANDBY MODE VS.
AMBIENT TEMPERATURE
SUPPLY CURRENT FROM Vee,
STANDBY MODE VS. SUPPLY VOLTAGE
2.8
2.8
Ta=2S0C
Vee=S.5V
u'---
u«
> E
2.4
o N
)
:2 ---
LU
0
0
:2
>-
2.0
u co
>- 0
0: ~
"- I::> C/l
C/l
,
1.6
1.2
4.0
V
4.5
t3'~
>
V
3:15
Iz
LU
~
::>
/
:2
0
~
...........
0
3:.9
I-LU
zo
LUO
~:2
::>>-
~ .........
2.0
uco
>-0
o:~
,,-I::>C/l
C/l
5.0
5.5
1.6
25
6.0
50
100
75
AMBIENT TEMPERATURE Ta CC)
AVERAGE SUPPLY CURRENT FROM Vee,
REFRESH MODE VS. SUPPLY VOLTAGE
AVERAGE SUPPLY CURRENT FROM Vee,
REFRESH MODE VS.
AMBIENT TEMPERATURE
40~----~----~----~----~
u'
u
Ta=25°C
u
0«
E
LL-....
40
u'
Vee=5.5V
>
:2--30~----+_----~----_;----~
:2--0«
LL ___
0:
E
::>0
0:
O:UJ
::>0
>-:2
>-:2
O:LU
uO
uO
20
te
(REF) =
260ns
te
(RE;)
330ns
T= 500ns
....JI
....JI
"-C/l
"-LU
::>0:
C/l
"-C/J
"-LU
::>0:
C/l
LL
LULlJ
c.:JCI:
30
~ §
I- M
Z Q
LU Q
0:-
te
(REF)
LL
101----__-+-=---_+__
LULU
c.:Ja:
10
te
<{
<{
(REF) -
1000ns
~
~
>
<{
>
<{
O~
o
____~____~~__~~__~
4.0
4.5
5.0
SUPPLY VOLTAGE
6.0
:2--o
3:~
30
(.I)
~
20
::>w
WW
c.:Ja:
40r-----~----_T----....~--__,
Ta=2S0C
Z LU
30 t----+------+--to (PG) = 14Sns
LU
....JI
(,!)
100
1----
o:w
&:
75
0:2 ___
::>0
>-::2:
50
AVERAGE SUPPLY CURRENT FROM Vee,
PAGE MODE VS. SUPPLY VOLTAGE
~
Ta=2S0d
Vee=S.SV
IZ '"
()
w ()
a:-
uO
25
AMBIENT TEMPERATURE Ta (OC)
40
tf
>
o
vee (v)
AVERAGE SUPPLY CURRENT FROM Vee,
REFRESH MODE VS. FREQUENCY
10
<{
",
0:
w
~
L
/'
L
Uo
20~-~9----~-='
>-0
0::2
,,-LU
::>c.:J
C/l~
LU
c.:J
<{
~
>
>
<{
<{
O~
o
o
2
FREQUENCY
2-52
.......
2.4
N
Sl)PPLY VOLTAGE Vee (v)
>
0:
E
3
4
f(¢) (MHz)
____
4.0
~
4.5
____
~
____
5.0
~
____
5.5
SUPPLY VOLTAGE Vee (V)
• MITSUBISHI
"ELECTRIC
~
6.0
MITSUBISHI LSls
MSK4164NP-1S, NP-20
65 536-BIT (65 536-WORD BY I-BIT) DYNAMIC RAM
AVERAGE SUPPLY CURRENT FROM Vee,
PAGE MODE VS. AMBIENT TEMPERATURE
AVERAGE SUPPLY CURRENT FROM Vee,
. PAGE MODE VS. FREQUENCY
40
U
~
~
0,....
Z ...
W 0
:::>w
Uo
>-0
u.. E
-
0: 0
0:-
20
f-'-'
te(p~190nS
W 0
0: 0
0:-
...J~
t e (pl) = SOOns
C/l«
20
~w
:::>t!l
C/l«
-
w~
10
~
tC
>
«
30
:::>w
Uo
>-0
:::>t!l
«
Z
~
~w
t!l
...
te (PG)-145ns
~~
w~
40
o:~
-
30
f- '-'
o
o
25
50
'PGF
t!l
1000",
75
«
10
0:
w
>
«
o
100
...J
3
Vee=5Jv
w
t!l
:i
;>
«
2.01----+---+---
~
f-
f2Z 5'
I
~
~
1. O l - - - - + - - - + - - - + - - - - i
'-'
:i
;>
f2
I
~
1.51---=-+---+---
;-
°>
f-
~
-
2.0
VIH1(min)
J-
;>
1.5
VILl (max)
Ii
I~
~
1.0
0.5 ......_ _ _ _ _ _...1...._ _...1...._ _...
4.0
4.5
5.0
5.5
6.0
0.5
o
25
50
100
75
SUPPLY VOLTAGE Vee (V)
AMBIENT TEMPERATURE Ta (OC)
Ao"-'A7, DIN INPUT VOLTAGE VIH2, VIL2
VS. SUPPLY VOLTAGE
Ao"-'A7, DIN INPUT VOLTAGE VIH2, VIL2
VS. AMBIENT TEMPERATURE
2:
2:
2.5
~
'"I
;>
N
~
2 .0
W
«
«
f-
~
VIH2(min)
T
VIL2(max)
...J
~
1.5
1.5
f-
f-
1t
f2
~
~
1.0
z
0"
0.5
:t
~
:t
-
2.0
t!l
t!l
z
0"
Vee=5.5V
;>
W
°>
2.5
'"...J
;>
I
-
2.5
Ta=25·C
2:
«
f-
°
I""""
RAS, CAS, W, INPUT VOLTAGE
VIH1, VIL1 VS. AMBIENT TEMPERATURE
r----.,..----r----,---....,
t!l
>
~
FREQUENCY f (¢) (M Hz)
RAS, CAS, W, INPUT VOLTAGE
VIH1, VIL1 VS. SUPPLY VOLTAGE
2.5
~
~
o
AMBIENT TEMPERATURE Ta (·C)
W
II
1
Ta'=25 ·C
Vee=5.5V
>
0,....
~~
50
u'
u
Vee=5.5V
u
>
~
I
4.0
4.5
5.0
5.5
6.0
1.0
0.5
SUPPLY VOLTAGE Vee (V)
0
25
50
75
100
AMBIENT TEMPERATURE Ta (OC)
• MITSUBISHI
"'ELECTRIC
2-53
MITSUBISHI LSls
MSK4164NP-1S, NP-20
65 536-BIT (65 536-WORD BY I-BIT) DYNAMIC RAM
SUPPLY CURRENT VS. TIME
Vcc
SV
RAS
rf)
~
CAS
0
~
100
88
ICC
(rnA) ~O
0
100
ISS ~g
(rnA) ~8
0
SOns/DIVISION
TIME
2-54
t
• MITSUBISHI
;"ELECTRIC
MITSUBISHI LSls
MSK4164S-1S, 5-20
65 536-BIT (65 536-WORD BY I-BIT) DYNAMIC RAM
DESCRIPTION
PIN CONFIGURATION (TOP VIEW)
This is a family of 65 536-word by 1-bit dynamic RAMs,
fabricated with the high performance N-channel silicon-gate
MOS process, and is ideal for large-capacity memory
systems where high speed, low power dissipation, and low
costs are essential. The use of double-layer polysilicon
process technology and a single-transistor dynamic storage
cell provide high circuit density at reduced costs, and the
use of dynamic circuitry including sense amplifiers assures
low power dissipation. Multiplexed address inputs permit
both a reduction in pins to the standard 16-pin package
configuration and an increase in system densities. The
M5K4164S operates on a 5V power supply using the
on-chip substrate bi'as generator.
REFRESH INPUT
--*
REF .....
14 -+
Q
DATA OUTPUT
4
ADDRESS INPUTS
ADDRESS INPUTS
(5V)
FEATURES
•
(QV)
15 .... CAS ~~~g~J'lI~~8~ESS
WRITE
CONTROL INPUT
~~~o:f9~~8f RAS -+
VSS
1
DATA INPUT
Outline 16S1
Performance ranges
Access time
(max)
(ns)
Cycle time
(min)
(ns)
Power dissipation
(typ)
(mW)
M5K4164S-15
150
260
200
M5K4164S-20
200
330
170
Type name
* If the pin 1 (REF) function is not used, pin 1 may be left open (not connect).
•
• Standard 16-pin package
• Single 5V ±1 0% supply
• Low standby power dissipation:
28mW (max)
• Low operating power dissipation:
M5K4164S-15
275mW (max)
250mW (max)
M5K4164S-20
• Unlatched output enables two-dimensional chip selection and extended page boundary
• Early-write operation gives common I/O capability
• Read-modify-write, RAS-only refresh, and page-mode
capabilities
All input terminals have low input capacitance and are
directly TTL-compatible
• Output is three-state and directly TTL-compatible
• 128 refresh cycles every 2ms
(16K dynamic RAMs M5K4116P, S compatible)
• Pin 1 controls automatic- and self-refresh mode.
• CAS controlled output allows hidden refresh, hidden
automatic refresh and hidden self-refresh.
• Output data can be held infinitely by CAS.
• I nterchangeable with
Mostek's MK4164
and
Motorola's MCM 6664 in pin configuration.
APPLICATION
•
Main memory unit for computers.
BLOCK DIAGRAM
DATA INPUT
WRITE CONTROL INPUT
COLL~~RNO:f~~~Jf
CAS
ROW ADDRESS
STROBE INPUT
REFRESH INPUT
MEMORY CELL
(64 ROWS X 256 COLLUMNS
SENSE REFRESH AMPLIFIER
MEMORY CELL
(64 ROWS X 256 COLUMNS)
COLUMN DECODER
ADDRESS INPUTS
MEMORY CELL
(64 ROWS X 256 COLUMNS)
SENSE REFRESH AMPLIFIER
MEMORY
(64 ROWS
X 256 CELL
COLUMNS)
COLUMN DECODER
• MITSUBISHI
.... ELECTRIC
14
Q DATA OUTPUT
J'
2-55
MITSUB.SHI LSls
MSK41645-1S, 5-20
65 536·BIT (65 536·WORD. BY 1·BIT) DYNAMIC RAM
FUNCTION
The M5K4164S provides, in addition to normal read, write,
and read-modify-write operations, a number of other
functions, e.g., page mode, RAS-only refresh, and delayedwrite. The input conditions for each are shown in Table 1.
Table 1 I nput conditions for each mode
Output
Inputs
Operation
RAS
CAS
W
D
Row
address
Column
address
REF
Q
Refresh
Read
ACT
ACT
NAC
ONC
APO
APO
NAC
VLO
YES
Write
ACT
ACT
ACT
VLO
APO
APO
NAC
OPN
YES
Read-modify-write
ACT
ACT
ACT
VLO
APO
APO
NAC
VLO
YES
l'iAS-on Iy refresh
ACT
NAC
ONC
ONC
APO
ONC
NAC
OPN
YES
Hidden refresh
ACT
ACT
ONC
ONC
APO
ONC
NAC
VLO
YES
Automatic refresh
NAC
ONC
ONC
ONC
ONC
ONC
ACT
OPN
YES
YES
Self refresh
NAC
ONC
ONC
ONC
ONC
ONC
ACT
OPN
Hidden automatic refresh
NAC
ACT
ONC
ONC
ONC
ONC
ACT
VLO
YES
Hidden self refresh
NAC
ACT
ONC
ONC
ONC
DNC
ACT
VLO
YES
Standby
NAC
ONC
ONC
ONC
ONC
ONC
NAC
OPN
NO
Remarks
Page mode
identical except
refresh is NO.
Note: ACT: active, NAC : nonactive, ONC : don't care, VLO : valid, APO : applied, OPN : open.
SUMMARY OF OPERATIONS
Addressing
To select one of the 65 536 memory cells in the M5K4164S
the 16-bit address signal must be multiplexed into 8 address
signals, which are then latched into the on-chip latch by
two externally-applied clock pulses. First, the negativegoing edge of the row-address-strobe pulse (RAS) latches
the 8 row-address bits; next, the negative-going edge of the
column-address-strobe pulse (CAS) latches the 8 columnaddress bits. Timing of the RAS and CAS clocks can be
selected by either of the following two methods:
1. The delay time from RAS to CAS td (RAS-CAS) is set
between the minimum and maximum values of the
limits. In this case, the internal CAS control signals are
inhibited almost until td(RAS-CAS)max ('gated CAS'
operation). The external CAS signal can be applied with
a margin not affecting the on-chip circuit operations, e.g.
access ti me, and the address inputs can be easily changed
from row address to column address.
2. The delay time t d ( RAS-CAS) is set larger than the
maximum value of the limits. In this case the internal
inhibition of CAS has already been released, so that the
internal CAS control signals are controlled by the
externally applied CAS, which also controls the access
time.
Data Input
Date to be written into a selected cell is strobed by the later
of the two negative transitions of W input and CAS input.
Thus when the W input makes its negative transition prior
to CAS input (early write), the data input is strobed by
CAS, and the negative transition of CAS is set as the
reference point for set-up and hold times. In the read-write
2-56
or read-modify-write cycles, however, when the W input
makes its negative transition after CAS, the W negative
transition is set as the reference point for setup and hold
times.
Data Output Control
The output of the M5K4164S IS In the high-impedance
state when CAS is high. When the memory cycle in progress
is a read, read-modify-write, or a delayed-write cycle, the
data output will go from the high-impedance state to the
active condition, and the data in the selected cell will be
read. This data output will have the same polarity as the
input data. Once the output has entered the active
condition, this condition will be maintained until CAS goes
high, irrespective of the condition of RAS.
The output will remain in the high-impedance state
throughout the entire cycle in an- early-write cycle.
These output conditions, of the M5K4164S, which can
readily be 'changed by controlling the timing of the write
pulse in a write cycle, and the width of the CAS pulse in a
read cycle, offer capabilities for a number of applications,
as follows.
1. Common I/O Operation
If all write operations are performed in the early-write
mode, input and output can be connected directly to give a
common I/O data bus.
2. Data Output Hold
The data output can be held between read cycles, without
lengthening the cycle time. This enables extremely flexible
clock-timing settings for RAS and CAS.
•. MITSUBISHI
..... ELECTRIC
MITSUBISHI LSls
MSK41645-1S, 5-20
65 536-BIT (65 536-WORD BY I-BIT) DYNAMIC RAM
3. Two Methods of Chip Selection
Since the output is not latched, CAS is not required to keep
the outputs of selected chips in the matrix in a highimpedance state. This means that CAS and/or RAS can
both be decoded for chip selection.
4. Extended-Page Boundary
By decoding CAS, the page boundary can be extended
beyond the 256 column locations in a single chip. In this
case, RAS must be applied to all devices.
Page-Mode Operation
This operation allows for multiple-column addressing at the
same row address, and eliminates the power dissipation
associated with the negative-going edge of RAS, because
once the row address has been strobed, RAS is maintained.
Also, the time required to strobe in the row address for the
second and subsequent cycles is eliminated, thereby decreasing the access and cycle times.
Refresh
Each of the 128 rows (A o. . . . A6 ) oftheM5K4164Smustbe
refreshed every 2 ms to maintain data. The methods of
refreshing for the M5K4164S are as follows.
1. Normal Refresh
Read cycle and Write cycle (early write, delayed write or
read-modify-write) refresh the selected row as defined by
the low order (RAS) addresses. Any write cycle, of course,
may change the state of the elected cell. Using a read, write,
or read-modify-write cycle for refresh is not recommended
for systems which utilize "wire-OR" outputs since output
bus contention will occur.
2. RAS Only Refresh
A RAS-only refresh cycle is the recommended technique
for most applications to provide for data retention. A
RAS-only refresh cycle maintains the output in the
high-impedance state with a typical power reduction of
20% over a read or write cycle.
3. Automatic Refresh
Pin 1 (REF) has two special functions. The M5K4164S
has a refresh address counter, refresh address multiplexer
and refresh timer for these operations. Automatic refresh is
initiated by bringing REF low after RAS has precharged
and is used during standard operation just like RAS-only
refresh, except that sequential row addresses from an
external counter are no longer necessary.
At the end of automatic refresh cycle, the internal
refresh address counter will be automatically incremented.
The output state of the refresh address counter is initiated
by'some eight REF, RAS or RAS/CAS cycles after power
is applied. Therefore, a special operation is not necessary
to initiate it.
RAS must remain inactive during REF activated cycles.
Likewise, REF must remain inactive during RAS generated
cycle.
4. Self-Refresh
The other function of pin 1 (REF) is self-refresh. Timing
for self-refresh is quite similar to that for automatic refresh.
As long as RAS remains high and REF remains low, the
M5K4164S will refresh itself. This internal sequence repeats
asynchronously every 12 to 16 J,ls. After 2 ms, the on-chip
refresh address counter has advanced through all the row
addresses and refreshed the entire memory. Self-refresh is
primarily intended for trouble free power-down operation.
For example, when battery backup is used to maintained
data integrity in the memory. REF may be used to place
the device in the self-refresh mode with no external timing
signals necessary to keep the information alive.
In summary, the pin 1 (REF) refresh function gives the
user a feature that is free, save him hardware on the board,
and in fact, will simplify his battery backup procedures,
increase his battery life, and save him overall cost while
giving him improved system performance.
There is an internal pullup resister (~ 3MSl) on pin 1, so
if the pin 1 (REF) function is not used, pin 1 may be left
open (not connect) without affecting the normal operations.
5. Hidden Refresh
A features of the M5K4164S is that refresh cycle may be
performed while maintaining valid data at the output pin
by extending the CAS active time from a previous memory
read cycle. This feature is refered to as hidden refresh.
Hidden refresh is performed by holding CAS at V I Land
taking RAS high and after a specified precharge period,
executing a RAS-only cycling, automatic refresh and
self-refresh, but with CAS held low.
The advantage of this refresh mode is that data can be
held valid at the output data port indefinitely by leaving
the CAS asserted. In many applications this eliminates the
need for off-chip latches.
Power Dissipation
Most of the circuirty in the M5K4164S is dynamic, and
most of the power is dissipated when addresses are strobed.
Both RAS and CAS are decoded and applied to the
M5K4164S as chip-select in the memory system, but if
RAS is decoded, all unselected devices go into stand-by
independent of the CAS condition, minimizing system
power dissipation.
Power Supplies
The M5K4164S operates on a single 5V power supply.
A wait of some 500J,ls and eight or more dummy cycle is
necessary after power is applied to the device before
memory operation is achieved.
• MITSUBISHI
.... ELECTRIC
2-57
II
MITSUBISHI LSls
MSK4164S-1S, 5-20·
65 536-BIT (65 536-WORD BY 1-BIT) DYNAMIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol
Para mater
Conditions
Unit
Limits
VCC
Supply voltage
VI
I nput voltage
Vo
Output voltage
-1-7
V
10
Output current
50
mA
1000
mW
0-70
'C
With respect to Vss
Pd
Power dissipation
Topr
Operating free-air temperature range
Tstg
Storage temperature range
Ta=25'C
V
-1-7
V
'C
-65-150
RECOMMENDED OPERATING CONDITIONS
Symbol
-1-7
(Ta=0-70'C. unless otherwise noted) (Note 1)
Limits
Parameter
Min
Nom
Max
Unit
VCC
Supply voltage
4.5
5
5.5
V
Vss
Supply voltage
0
0
0
V
VIH
High-level input voltage. all inputs
2.4
6.5
V
VIL
Low-level input voltage. all inputs
-2
0.8
V
Note 1: All voltage values are with respect to Vss
ELECTRICAL CHARACTERISTICS
Symbol
± 10%.
(Ta=0-70'C. Vcc=5V
Parameter
VSS=OV. unless otherwise noted) (Note 2)
Limits
Test conditions
Min
Typ
Max
Unit
VOH
High-level output voltage
IOH=-5mA
2.4
VCC
VOL
Low-level output voltage
IOL=4.2mA
0
0.4
loz
Off-state output current
Q floating OV;:;;;VoUT;:;;;5.5V
-10
10
J..lA
II
Input current
10
J..lA
ICC1(AV)
Average supply current from Vee.
operating (Note 3. 4)
50
rnA
OV;:;;;VIN;:;;;6.5V. All other pins
= OV
-10
CAS cycling
M5K4164S-15
RAS.
M5K4164S-20
t CR = t cw = min output open
V
V
45
rnA
5
mA
40
mA
ICC2
Supply current from Vee. standby
I CC3(AV)
Average supply current from Vee.
refreshing (Note 3)
M5K4164S-15
RAS cycling
M5 K4164S- 20
t C(REF)= min. output open
35
rnA
ICC4(AV)
Average supply current from Vee.
page mode (Note 3, 4)
M5K4164S-15
RAS =VIL. OAS cycling
40
mA
M5K4164S-20
tCPG= min. output open
35
rnA
I CC5(AV)
Average supply current from Vee,
automatic refreshing (Note 3)
M5K4164S-15
RAS=VIH. REF cycling
40
rnA
tc (REF)=rnin. output open
RAS=VIH output open
M5K4164S-20
I CCG (AV)
Average supply current from Vee. self refreshing
CI (A)
Input capacitance, address inputs
01 (D)
Input capacitance. data input
OAS=VIH
35
rnA
RAS=VIH. REF=VIL
output open
8
rnA
5
pF
VI=VSS
5
pF
01 (W)
Input capacitance, write control input
f=1MHz
01 (RAS)
Input capacitance. RAS input
VI=25rnVrrns
01 (CAS)
7
pF
10
pF
Input capacitance, CAS input
10
pF
01 (REF)
Input capacitance. REF input
10
pF
Co
Output capacitance
7
pF
Note 2:
3:
4:
2-58
VO=VSS. f= 1MHz. VI=25rnVrrns
Current flowing into an IC is positive; out is negative.
I CCl (AV). I CC3(AV). I CC4(AV) and I CC5(AV) are dependent on cycle rate. Maximum c~rrent is measured at the fastest cycle rate.
ICC 1(AV) and I CC4(AV) are dependent on output loading. Specified values are obtained with the output open.
• MITSUBISHI
.... ELECTRIC
MITSUBISHI LSls
M5K41645-15,5-20
65 536-BIT (65 536-WORD BY 1-BIT) DYNAMIC RAM
TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write, Refresh, and Page-Mode Cycle)
(Ta =0 -70·C. Vcc=5V ± 10%. VSS=OV. unless otherwise noted, See notes 5, 6 and 7)
M5K4164S-20
-M5K4164S-15
Symbol
Alternative
Parameter
Limits
Symbol
Min
Unit
Limits
Max
Min
Max
ms
teRF
Refresh cycle time
tREF
tW(RASH)
RAS high pulse width
tRP
100
tW(RASL)
RAS low pulse width
t RAS
150
tW(CASL)
CAS low pulse width
tCAS
75
tW(CASH)
CAS high pulse width
tCPN
35
40
t h (RAS-CAS)
CAS hold time after RAS
tCSH
150
200
ns
t h (CAS-RAS)
RAS hold time after CAS
t RSH
75
100
ns
td (CAS-RAS)
Delay time. CAS to "R'AS
(Note 9)
t CRP
-20
t d (RAS-CAS)
Delay time, RAS to
(Note 10)
tRCO
25
(Note 8)
CAS
2
2
120
ns
10000
200
10000
ns
00
100
00
ns
ns
-20
75
ns
30
100
ns
tSU(RA-RAS)
Row address setup time before RAS
tASR
0
0
t su (CA-CAS)
Column address setup time before CAS
tASC
-5
-5
ns
t h (RAS-RA)
Row address hold time after
t RAH
20
25
ns
ns
RAS
t h (CAS-CA)
Column address hold time after
t h (RAS-CA)
Column address hold time after
tTHL
CAS
RAS
Transition time
tCAH
25
35
tAR
95
120
tT
3
35
ns
ns
3
50
ns
tTLH
-_.
Note 5:
6:
7:
8:
9:
10.
An initial pause of 500~s is required after power-up followed by any eight REF. RAS or RAS"/~ cycles before proper device operation is achieved.
The switching characteristics are defined as t THL =t TLH =5ns.
Reference levels of input signals are VI H min. and VI L max. Reference levels for transition time are aiso between VI H and VI L·
Except for page-mode.
~(CAS-RASI requirement is only applicable for RAS/CAS cycles preceded by aCAS only cycle (i. e. for systems where CAS has not been decoded
with RAS).
Operation within the td (RAS-CAS) max limit insures that a (RAS) max can be met. td (RAS-CAS)maX is specified reference point only;if
td (RAS-CAS) is greater than the specifiedtd (RAS-CAS) max limit, then access time is controlled exclusively by ta(CAS)'
td (RAS-CAs)min =th (RAS-RA)min +2t THL(t TLH) +1 SU(CA-GAS)min.
SWITCHING CHARACTERISTICS
Read Cycle
(Ta=0-70·C. Vcc=5V±10%. VSs=OV. unlessotherwisenoted)
Alternative
Parameter
Symbol
M5K4164S-15
M5K4164S-20
Symbol
Min
Unit
Limits
Limits
Max
Max
Min
ns
te R
Read cycle time
t RC
260
330
tsu (R-CAS)
Read setup time before CAS
t RCS
0
0
ns
th (CAS-R)
Read hold time after CAS
tRCH
0
0
ns
(Note 11)
th(RAS-R)
Read hold time after RAS
(Note 11)
tRRH
20
tdis (CAS)
Output disable time
(Note 12)
tOFF
0
ta (CAS)
CAS access time
(Note 13,)
tCAC
ta (RAS)
RAS access time
(Note 14)
t RAC
Note
Note
Note
Note
11:
12:
13:
14:
ns
25
50
ns
75
100
ns
150
200
ns
40
0
Either th (RAS-R).or th (CAS-R) mtJst be satisfied for a read cycle.
tdis (CAS)maX defines the time at which the output achieves the open circuit condition and is not reference to VOH or Vo L·
This is the value when td (RAS-CAS);;;;;td (RAS-CAs)max. Test conditions; Load = 2TTL, CL = 100pF
This is the value when td (RAS-CAS)< td (RAS-CAS)max. When td (RAS-CAS);;;;;td (RAS-CAS)max. ta (RAS) will increase by the amount that
td (RAS-CAS) exceeds the value shown. Test conditions; Load = 2TTL, CL = 100pF
Write Cycle
Symbol
Alternative
Parameter
M5K4164S-15
M5K4164S-20
Limits
Min
teW
Write cycle time
tsu (W-CAS)
Write setup time before CAS
Max
Min
Max
260
330
ns
twcs
-10
-10
ns
t RC
(Note 17)
Unit
Limits
Symbol
th (CAS-W)
Write hold time after CAS
tWCH
45
55
ns
th (RAS-W)
Write hold time after RAS
tWCR
95
120
ns
th (W-RAS)
RAShold time after write
t RWL
45
55
ns
th (W-CAS)
CAS hold time after write
tCWL
45
55
ns
tW(W)
Write pulse width
twp
45
55
ns
tsu (O-CAS)
Data-in setup time before CAS
tos
0
0
ns
th (CAS-D)
Data-in hold time after CAS
tOH
45
55
ns
th (RAS-O)
Data-in hold time after RAS
tOHR
95
120
ns
• MITSUBISHI
;'ELECTRIC
2-59
MITSUBISHI LSls
MSK41645-1S, 5-20
65 536-BIT (65 536-WORD BY I-BIT) DYNAMIC RAM
Read-Write and Read-Modify-Write Cycles
Alternative
Parameter
Symbol
M5K4164S-15
M5K4164S-20
Limits
Symbol
limits
Max
Min
Min
Unit
Max
tORw
Read-write cycle time
(Note 15)
tRwc
280
34,0
ns
tORMW
Read-modify-write cycle time
(Note 16)
tRMWC
310
390
ns
th (W-RAS)
RAS hold time after write
t RwL
45
55
ns
th (W-CAS)
CAS hold time after write
tCWL
45
55
ns
tW(W)
Write pulse width
twp
45
55
ns
tsu (R-CAS)
Read setup time before
tRCS
0
0
ns
td (RAS-W)
Delay time,
ffAS to write
(Note 17)
t RwD
120
150
ns
td (CAS-W)
Delay time,
CAS to write
(Notela)
tCWD
60
80
ns
tsu (D-W)
Data-in set-up 'time before write
tDS
0
0
ns
th (W-D)
Data-in hold time after write
t DH
45
55
tdis (CAS)
Output disable time
tOFF
1a (CAS)
CAS access time
(Note 13)
tCAC
ta (RAS)
RAS access time
(Note 14)
t RAC
CAS
Note 15: t oRwmin is defined as. tORW min = td (RAS-W)
+
40
0
ns
50
ns
75
100
ns
150
200
ns
0
th (W-RAS) + tw (RASH) + 3t TLH(tTHL)
16: t oRMW min is defined as tORMW min =ta (RAs)maX
+ th (W-RAS) + tw (RAS H) + 3t TLH(tTHL)
17: tsu (W-CAS). td (RAS-W). and td (CAS-W) do not define the limits of operation, but are included as electrical characteristics only.
When tsu (W-CAS)~ tsu (W -CAs)min. an early-write cycle is performed, and the data output keeps the high-impedance state.
When td (RAS-W)~td (RAs-w')min. and td (CAS-W)~tsU(W-CAS)min a read-write cycle is performed, and the data of the selected address will be read out
on the data output.
For all conditions other than those described above, the condition of data output (at access time and until CAS goes back to VI H) is not defined.
Page-Mode Cycle
Alternative
Symbol
Parameter
M5K4164S-15
M5K4164S-20
Limits
Symbol
Min
Unit
Limits
Max
Max
Min
tcPGR
Page-mode read cycle time
tpc
145
190
ns
tcPGW
Page-mode writ~ cycle time
tpc
145
190
ns
tcPGRW
Page-mode read-write cycle time
-
180
230
ns
tcPGRMW
Page-mode read-modify- write cycle time
-
190
245
ns
tw (CAS!-i)
CAS high pulse width
tcp
60
80
ns
Automatic Refresh Cycle
Alternative
Symbol
Parameter
M5K4164S-15
M5K4164S-20
Limits
Symbol
Unit
Limits
Max
Min
Min
Max
to (REF)
Automatic Refresh Cycle Time
tFC
260
330
ns
tW(RASH)
RAS high pulse width
tRP
395
480
ns
td (RAS-REF)
D~lay time, RAS to REF
t RFD
100
120
1w (REFL)
REF low pulse width
tFP
80
tW(REFH)
REF high pulse width
t FI
135
150
ns
td (REF-RAS)
Delay time, REF to RAS
t FSR
30
30
ns
tsu (REF-RAS)
REF pulse setup time before RAS
tFRD
295
360
ns
8000
ns
8000
100
ns
Self-Refresh Cycle
Symbol
Parameter
Alternative
M5K4164S-15
Min
td (RAS-REF)
Delay time, RAS to REF
t RFD
100
1w (REFL)
REF low pulse width
1 FBP
8000
td (REF-RAS)
Delay time, REF to RAS
t FBR
295
2-60
• MITSUBISHI
;"ELECTRIC
M5K4164S-20
Limits
Symbol
Limits
Max
Min
Unit
Max
120
00
8000
360
ns
00
ns
ns
MITSUBISHI LSls
MSK41645-1S, 5-20
65 536-BIT (65 536-WORD BY I-BIT) DYNAMIC RAM
TIMING DIAGRAMS
Read Cycle
(Note 18)
(Note 17)
~~------------------------- teR
II
~-------------------tW(RASL)--------------------~
r----------lil(RAs-CAs)-------------------.l
------,,1
-I
1-----tI1(RAS-CA)
RAS
I
I (CAS- RAS )-------~
--------4-+__------~tI1
1----------'----tW(CASL)-----l
COLUMN
ADDRESS
Ao - A7
Lla(CAS)-------"
-+---1-...-
~---------------ta(RAS)------------------~
tdIS(CAS)
VOH -
Q
-----------HIGHIMPEDANCESTATE------------~~~
DATA VALID
VOL -
Write Cycle (Early Write) (Note 18)
~~-------------------------- lew --------------------------------~
~-----------------tW(RASL)----------------------~
1------------------- I 11 (RA s-ICA S) -------------------i_~1
f-----111(RAS-CA)
RAS
.
~--'-----ti1(CAS-RAS)-----"':"--I
tW(RASH)
--------4-4----~-----IW(CASL)-------I
CAS
VIL
- _ _ _ __
w
VIH
0
VIL
I - - - - - - - - - - t h (RAS- O ) - - - - - . - l
VOH -
Q
VOL -
----------------------HIGHIMPEDANCESTATE-----------------------------
• MITSUBISHI
"'ELECTRIC
2-61
MITSUBISHI LSls
MSK41645-1S, 5-20
85 538·BIT (85 538·WORD BY 1·BIT) DYNAMIC RAM
Read-Write and Read-Modify-Write Cycles
(Note 18)
~~-------------------------------tCRW/tCRMW--------------------------------------~
~----------------------------tW(RASL)------------------------------~
~----------------.----------th(RAS-CAS)--------------------------~~
f - - - - - - - t h (RAS- CA ) - - - - - - - - - i
RAS
f - - - - - : - - - - - - - - t 11 (CAS- RAS )-------------------1
--~_+~----~-----------tW(CASL)----------------~~
Ao-A7
w
VIH -~","/\.I""/vv
V IL
-~CJl.~~~a:i.J'..B
Q
D
RAS-Only Refresh Cycle
(Note 19)
~~---------------------tCR--------------------------~~
t - - - - - - - t W(RASL)--------i
RAS
VOH -
Q
VOL -
Note 17
------------------------------------HIGH
~
Indicates the don't care input
~
The center-line indicates the high-impedance state
IMPEDANCE
STAtE-------------------------------------.
Note 18. REF = VIH
19. CAS=REF=VIH,
2-62
• MITSUBISHI
.... ELECTRIC
W,
A7, D =don'tcare_
MITSUBISHI LSls
MSK41645-1S, 5-20
65 536-BIT (65 536-WORD BY 1-BIT) DYNAMIC RAM
Page-Mode Read Cycle
(Note 18)
II
~~-----------------------------tW(RASL)----------------------------------~-4
thCRAS-CASl~
I
-tllCRAS-CAl4
~-----;---tcPGR -----!.------I
Q
VOH VOL _ - - - HIGH IMPEDANCE STATE
I)+:~-rj~--~~ DATA
T-t"'CA'":~
~~~~~~-----------~~~r------------~/~'---------------~~~~~P
w
Page-Mode Write Cycle
(Note 18)
~---------------------------------tWCRASLl--------------------------------~~
thCRAS-CASl~
thCRAS-CAli
I
VIH
CAS
AO-A7
VIL
VIH
V IL
W
VIH
VIL
0
VIH
VIL
• MITSUBISHI
.... ELECTRIC
2-63
MITSUBISHI LSls
MSK41645-1S, 5-20
65 536-BIT (65 536-WORD BY 1-BIT) DYNAMIC RAM
Automatic Pulse Refresh Cycle (Multiple Pulse)
(Note 20)
tw(RASH)
td (RAS-REF)
fE----'-----~td (REF- RAS)
Automatic Pulse Refresh Cycle (Single Pulse)
td (RAS-REF)
(Note 20)
tw(RASH)
tsu (REF-RAS)
td (REF-RAS)
tW(REFL)
REF
Self-Refresh Cycle
(Note 20)
RAS
td(REF-RAS)
~.-----,,~
tW(REFL)
VIH
-
VIL
-
Note 20: CAS, Addresses, 0 and Ware don't care.
Hidden Automatic Pulse Refresh Cycle
READ CYCLE
REFRESH CYCLE
REFRESH CYCLE
w
REF
VIH
VIL
tdis(CAS)
ta(RAS)
VOH -
Q
2-64
DATA VALID
VOL -
• MITSUBISHI
.... ELECTRIC
L
MITSUBISHI LSls
MSK41645-1S, 5-20
65 536-BIT (65 536-WORD BY i-BIT) DYNAMIC RAM
Hidden Self-Refresh Cycle
READ CYCLE
II
IN
VIH
VIL
REF
VIH
VIL
ta(RAS)
Q
tdis (CAS)
VOH
DATA VALID
VOL
Note 21: If the pin 1 (REF) function is not used, pin 1 may be left open (not connect).
Hidden Refresh Cycle
(Note 18)
READ CYCLE
teR
REFRESH CYCLE
teR
REFRESH CYCLE
teR
t w ( RASLl
td ICAS-RASI
td (RAS-CAS)
tW(CASL)
th (RAS-RA)
th(RAS-RA)
IN
VIH
VIL
tdis (CAS)
Q
VOH
DATA VALID
VOL
• MITSUBISHI
.... ELECTRIC
2--65
MITSUBISHI LSls
MSK41645-1S, 5-20
65 536·BIT (65 536·WORD BY I.BIT) DYNAMIC RAM
TYPICAL CHARACTERISTICS
NORMALIZED ACCESS TIME VS.
AMBIENT TEMPERATURE
NORMALIZED ACCESS TIME VS.
Vee SUPPLY VOLTAGE
1.4
1.4
Ta=25°C
Vee=5V
Vi
Vi
:;;~
1.2
o E
ff:,;::
f-
-- --
1.1
U
~
u
1.0
8
~
~
~
..J
-CJ
n:'~
eLI~
~~
fi:,::
te=260ns-
T
~~
O:w
u:;;
Z
/V
0
U:;;
30
/V
,V
>-CJ
n:'~
o..f-
a:~
eLf-
tJ=500ns
~<1:
~<1:
(f)a:
Ww
20
CJeL
<1:0
«0
f5
20
IT:
t J= 1000ns
10
W
>
<1:
o
25
50
75
10
10-0
AMBIENT TEMPERATURE Ta (OC)
2-66
~
40
0
~o
30
(/)a:
>
«
Ta ~25°CJ
Vee=5.5V
wa:w
a:o
>-(.9
ww
CJo..
a: E
LL';::
f-
te=330ns
0:0
~o
~~
I
40
I- ()
Vee (V)
AVERAGE SUPPLY CURRENT FROM Vee,
OPERATING MODE VS. FREQUENCY
50
>
°E
100
u"
0:
i=
(f)
(f)
w
75
50
40r-----~----~--~,---__,
1
Ta=25 oC
Vee=5V
Vi
25
AMBIENT TEMPERATURE Ta (OC)
NORMALIZED ACCESS TIME VS.
LOAD CAPACITANCE
~
V
53
0.8
0:
~
/
<1:
8
..J
V
.
/
,..
w
:;;
~r--
u
u
1.2
o
FREQUENCY
• MITSUBISHI
.... ELECTRIC
f (¢) (M Hz)
MITSUBISHI LSls
MSK41645-1S, 5-20
65 536-BIT (65 536-WORD BY i-BIT) DYNAMIC RAM
SUPPLY CURRENT FROM Vee,
STANDBY MODE VS.
AMBIENT TEMPERATURE
SUPPLY CURRENT FROM Vee,
STANDBY MODE VS. SUPPLY VOLTAGE
3.2
3.2
Ta=25°C
Vee=5.5V
u'~
u E
:;;;----
u'~
f- w
z 0
w 0
a: :;;;
a:
=> >U CD
0
>- z
c:§;CJl~
u E
1/
2.8
V
0
8:.:!
o
2.4
2.0
/
V
:;;;
0
8:.9
f-w
zo
wo
~:;;;
&~
iii(/)
1.6
4.5
5.0
5.5
"
o
25
50
75
100
AVERAGE SUPPLY CURRENT FROM Vee,
REFRESH MODE VS. SUPPLY VOLTAGE
AVERAGE SUPPLY CURRENT FROM Vee,
REFRESH MODE VS.
AMBIENT TEMPERATURE
40
u'
u
Vee=5.5V
I
>
t e (REF) = 260ns
:;;;~
o0
=>0
uO
uO
>-:;;;
>-:;;;
...JI
...JI
Cl.
w
Ww
oa:
20
"'"'t---
te
--
te
-
t e (REF) = 500ns
t e (REF) = 1000ns
10r-----t=~~~----~--~
w
=>0:
oa:
<1:
<1:
>
>
(REF) = 330ns
I
te
(/)LL
Ww
(REF) = 260ns
---r
a:
CJl
LL
30
W 0
0:o:w
10
T
(REF) = 1000ns
ffi
ffi
<1:
O~----~----~----~----~
4.0
4.5
5.0
5.5
6.0
SUPPLY VOLTAGE
<1:
20
V
a:
ww
00:
100
40~----~----~----~-----,
>
30
...JI
(/)LL
75
:;;;
:;;;~
~ (3
W 0
a:a:w
=>0
uO
>-:;;;
50
AVERAGE SUPPLY CURRENT FROM Vee,
PAGE MODE VS. SUPPLY VOLTAGE
u'
u
Ta=25°cJ
Vee=5.5V
>
ow
Uo
&:
>-0
=>0
(/)<1:
w
<1:
..............
AMBIENT TEMPERATURE Ta (OC)
>
~
i'...
SUPPLY VOLTAGE Vee (V)
40~----~----~----~-----,
f-
~
2.0
1.6
6.0
~.
0:
2.4
=>>ucn
0
>-z
(/)
4.0
~
2.8
N
0
>
o
<1:
o
2
FREQUENCY
3
4
O~----~----~----~----~
4.0
4.5
5.0
5.5
6.0
SUPPLY VOLTAGE Vee (V)
f (¢) (MHz)
• MITSUBISHI
.... ELECTRIC
2-67
MITSUBISHI LSls
MSK41645-1S, 5-20
65 536-BIT (65 536-WORD BY I-BIT) DYNAMIC RAM
AVERAGE SUPPLY CURRENT FROM Vee,
PAGE MODE VS. FREQUENCY
AVERAGE SUPPLY CURRENT FROM Vee,
PAGE MODE VS. AMBIENT TEMPERATURE
40
50
u·
u·
u
Vee=S.SV
u
>
::2:
o~
0:«
Ll. E
f- ........
Z
W
0:
Ta=2S!C
Vee=S.SV
>
::2:
=>w
::t
te (PG)=200ns
20
---
>-0
0:::2:
a..w
=>e?
Vl«
wa..
e?
t e (PG) = 170ns
--
«
0:«
Ll. E
f- ........
Z w
40
30
>-0
...J::2:
a..
a..w
=>e?
Vl«
wa..
e?
«
0:
20
10
>
«
o
o
25
50
75
-------------
Uo
o
o
100
3
AMBIENT TEMPERATURE Ta (OC)
FREQUENCY f(¢) (MHz)
AVERAGE SUPPLY CURRENT FROM Vee,
AUTO REFRESH MODE
VS. SUPPLY VOLTAGE
AVERAGE SUPPLY CURRENT FROM Vee,
AUTO REFRESH MODE
VS. AMBIENT TEMPERATURE
40~------~------~------~------~
u·
Te(REF)=260ns
::2:«
o~
oc Q
'"
Ll.
30r-----+-----~=---~--~~
Te (REF) =330ns
I
20
&8:
=>w
10r-----+----=~--~~----_i
VlOC
wo
«=>
>
>
«
10
Tc
5«
~«
O~~~~---~~------~------~
4.0
4.5
5.0
5.5
6.0
SUPPLY VOLTAGE
o
o
25
50
' 'Fr
10000'
75
100
AMBIENT TEMPERATURE Ta (OC)
Vee (v)
SUPPLY CURRENT FROM Vee,
SELF REFRESH MODE
VS. SUPPLY VOLTAGE
AVERAGE SUPPLY CURRENT FROM Vee,
AUTO REFRESH MODE VS. FREQUENCY
40
u·
Ta=2S0cJ
Vee=S.SV
~:t
::2: E
0 ........
OC '"
Ll.
0
o
~~
U
I
20
::;t:l
a.. OC
a..Ll.
=>w
VlOC
wo
Ta=2S0C
30
f-Zw
Wo
10
/
e?f«=>
~«
V
/
V
/
.«
u E
u ........
>
w
u~
>-w
&~
=>...J
Vl~
o
o
o
4.0
FREQUENCY f(¢) (MHz)
2--68
I
Te (REI' = SOOns
~t:l
e?f«=>
>
«
1
Wo
20r---~+-----~-
e?f-
«
T
30
Zw
~~
u
I
wo
Te(REF)=260ns
f- -
>-Vl
...JW
a.. oc
a..Ll.
=>w
VlOC
::2: E
0 ........
0:
Ll. ,"
Q
I
Vee=S.SIV
~4.
Q
f-5::
Zw
Wo
~~
U
40
u·
o
Ta =2S C
u
>~
4.5
5.0
5 .5
SUPPLY VOLTAGE vee (V)
• MITSUBISHI
"'ELECTRIC
6.0
MITSUBISHI LSls
MSK41645-1S, 5-20
65 536·BIT (65 536·WORD BY 1·BIT) DYNAMIC RAM
SUPPLY CURRENT FROM Vee,
SELF REFRESH MODE
VS. AMBIENT TEMPERATURE
RAS, CAS, W, REF INPUT VOLTAGE
VIH1, VIL1 VS. SUPPLY VOLTAGE
2.5,....---..,......--...,---...,...----,
I
W
VCC=5.5 V
c:J
u~
>
2.0 r - - - + - - - - + - - - - - t - - - - I
i5: :>I
VIHl (min)
~
I~
I-
a:I
1.5 ~--+-----+----+-~--:-t
~
a:CfJ
::>w
u~
~
I~
)-W
&~
::>-.J
CfJW
CfJ
o
o
25
50
75
1.0r---+----+-----t----I
0,5~-~........-~~--~--_:_'
4.0
4.5
5.0
5.5
6.0
100
AMBIENT TEMPERATURE Ta ("C)
SUPPLY VOLTAGE Vce (V)
RAS, CAS, W, REF INPUT VOLTAGE
VIH1, VIL 1 VS. AMBIENT TEMPERATURE
2.5
W
c:J
2:
~
~
> :>
lii: I
0
Ao"'A7, DIN INPUT VOLTAGE VIH2, VIL2
VS. SUPPLY VOLTAGE
N
VIHl (min)
I
2.0
I
:>
-- -
~
ll.!
c:J
:>
JILl (max)
~
VIL2 (max)
-~
I"'"""
I-
~
Ii
~H2(mln)
Z
I~
I~
1.0
0.5
1.0
z
15
o
25
50
75
.i'
I
.l
100
0.5
.
4 0
4.5
5.0
5.5
6.0
AMBIENT TEMPERATURE Ta (OC)
SUPPLY VOLTAGE Vee (V)
Ao"'A7, DIN INPUT VOLTAGE VIH2, VIL2
VS. AMBIENT TEMPERATURE
SUPPLY CURRENT VS. TIME
2:
2.5
VCC=5,5V
..J
:>
(J)
N
:1
:!!
2.0
VIH2 (min)
W
c:J
~
o
>
"I.""
VIL2 (max)
1.5
ii:z
I-
100
80
Icc 60
::> (mA) ~8
u
0
)-
~
~
1.0
~
.i
.lI
~
a:
a:
l-
z
15
0
0.5
RAS
CAS
0
25
50
75
100
80
Iss 60
(mA) ~8
0
100
AMBIENT TEMPERATURE Ta (OC)
• MITSUBISHI
"ELECTRIC
50ns/DIVISION
TIME
t
2-69
MITSUBISHI LSls
MSK41645-1S, 5-20
6S S36-BIT (6S S36-WORD BY 1-BIT) DYNAMIC RAM
SUPPLY CURRENT VS. TIME
100
80
Icc ~8
(mA) 20
a
100
80
Iss 60
(mA) ~g
a
Sans/DIVISION
TIME
2-70
t
• MITSUBISHI
.... ELECTRIC
MITSUBISHI LSls
MSK4164NS-1S, NS-20
65 536-BIT (65 536-WORD BY I-BIT) DYNAMIC RAM
DESCRIPTION
PIN CONFIGURATION (TOP VIEW)
This is a family of 65 536-word by 1-bit dynamic RAMs,
fabricated with the high performance N-channel silicongate
MOS process, and is ideal for large-capacity memory
systems where high speed, low power dissipation, and low
costs are essential. The use of double-layer polysilicon
process technology and a single-transistor dynamic storage
cell privide high circuit density at reduced costs, and the
use of dynamic circuitry including sense amplifiers assures
low power dissipation. Multiplexed address inputs permit
both a reduction in pins to the standard 16-pin package
configuration and an increase in system densities. The
M5K4164NS operates on a 5V power supply using the
on-chip substrate bias generator.
NC
15
WRITE
CONTROL INPUT
(OV)
+--CAS ~~~g~EN 1~~8fESS
14 ~
Q
DATA OUTPUT
ROW ADDRESS
STROBE INPUT
ADDR ESS INPUTS
ADDRESS INPUTS
(5V)
FEATURES
•
VSS
DATA INPUT
Vee
Outline 16S1
Performance ranges
Access time
(max)
(ns)
Cycle time
(min)
(ns)
Power dissipation
(typ)
(mW)
M5K4164NS-15
150
260
200
M5K4164NS-20
200
330
170
Typ€ name
• Standard 16-pin package
• Single 5V±1 0% supply
28.0mW (max)
• Low standby power dissipation:
• Low operating power dissipation:
275mW (max)
M5K4164NS .15
250mW (max)
M5K4164NS -20
• Unlatched output enables two-dimensloila! chip selection and extended page boundary
• Early-write operation gives common I/O capability
• Read,modify-write, RAS-only refresh, and page-mode
capabilities
•
All input terminals have low input capaciatance and are
directly TTL-compatible
•
•
Output is three-state and directly TTL-compatible
128 refresh cycles every 2ms
(16K dynamic RAMs M5K4116P, S compatible)
CAS controlled output allows hidden refresh.
Output data can be held infinitely by CAS.
Interchangeable with Mostek's MK4564 ~nd Motorola's
MCM 6665 in pin configuration.
•
•
•
APPLICATION
•
Main memory unit for computers.
BLOCK DIAGRAM
DATA INPUT
0
2
r----------------·-----;:::=::L--,
WRITE CONTROL INPUT
COLL~_rR~:f9~~0_f
Vee (SV)
CAS
ROW ADDRESS
STROBE INPUT
VssIOV)
MEMORY CELL
(64 ROWS X 256 COLLUMNS
SENSE REFRESH AMPLIFIER
MEMORY CELL
(64 ROWS X 256 COLUMNS)
f-cr
COLUMN DECODER
::Jw
a..
tL
f- LL
14
Q DATA OUTPUT
::J::J
MEMORY CELL
(64 ROWS X 256 COLUMNS)
ADDRESS INPUTS
Oro
SENSE REFRESH AMPLIFIER
MEMORY
(64 ROWS
X 256 CELL
COLUMNS)
COLUMN DECODER
J'
~.-•
MITSUBISHI
.... ELE~TRIC
2-71
MITSUBISHI LSls
MSK4164NS-1S, NS-20
65 536·BIT (65 536·WORD BY 1.BIT) DYNAMIC RAM
FUNCTION
The M5K4164NS provides, in addition to normal read,
write, and read-modify-write operations, a number of other
functions, e.g., page mode, RAS-only refresh, and delayedwrite. The input conditions for each are shown in Table 1.
Table 1 Input conditions for each mode
Output
Inputs
Operation
RAS
CAS
W
D
Row
address
Column
address
Q
Refresh
Read
ACT
ACT
NAC
ONC
APO
APO
VLD
YES
Write
ACT
ACT
ACT
VLO
APO
APO
OPN
YES
Read-modify-write
ACT
ACT
ACT
VLO
APO
APO
VLO
YES
RAS-only refresh
ACT
NAC
ONC
ONC
APD
ONC
OPN
YES
Hidden refresh
ACT
ACT
ONC
ONC
APO
ONC
VLO
YES
Standby
NAC
ONC
ONC
ONC
ONC
ONC
OPN
NO
Remarks
Page mode
identical except
refresh is NO.
Note: ACT: active, NAC : nonactive, ONC : don't care, VLO : valid, APO : applied, OPN : open.
SUMMARY OF OPERATIONS
Addressing
To select one of the 65536 memory cells in the
M5K4164NS the 16-bit address signal must be multiplexed
into 8 address signals, which are then latched into the'
on-chip latch by two externally-applied clock pulses. First,
the negative-going edge of the row-address-strobe pulse
(RAS) latches the 8 row-address bits; next, the negativegoing edge of the column-address-strobe pulse (CAS)
latches the 8 column-address bits. Timing of the RAS and
CAS clocks can be selected by either of the following two
methods:
1. The delay time from RAS to CAS td (RAS-CAS) is set
between the minimum and maximum values of the
limits. In this case, the internal CAS control signals are
inhibited almost until td(RAS-CAS) max ('gated CAS'
operation). The external CAS signal can be applied with
a margin not affecting the on-chip circuit operations, e.g.
access time, and the address inputs can be easily changed
from row address to column address.
2. The delay time td(RAS-CAS) is set larger than the
maximum value of the limits. In this case the internal
inhibition of CAS has already been released, so that the
internal CAS control signals are controlled by the
externally applied CAS, which also controls the access
time.
Data Input
Data to be written into a selected cell is strobed by the later
of the two negative transistons of W input and CAS input.
Thus when the Winput makes its negative transition prior
to CAS input (early write), the data input is strobed by
CAS, and the negative transition of CAS is set as the
2-72
reference point for set-up and hold times. In the read-write
or read-modify-write cycles, however, when the Winput
makes its negative transition after CAS, the W negative
transition is set as the reference point for setup and hold
times.
Data Output Control
The output of the M5K4164NS is in the high-impedance
state when CAS is high. When the memory cycle in progress
is a read, read-modify-write, or a delayed-write cycle, the
data output will go from the high-impedance state to the
active condition, and the data in the selected cell will be
read. This data output will have the same polarity as the
input data. Once the output has entered the active
condition, this condition will be maintained until CAS goes
high, irrespective of the condition of RAS.
The output will remain in the high-impedance state
throughout the entire cycle in an early-write cycle.
These output conditions, of the M5K4164NS, which can
readily be changed by controlling the timing of the write
pulse in a write cycle, and the width of the CAS pulse in a
read cycle, offer capabilities for a number of applications,
as follows.
1. Common I/O Operation
If all write operations are performed in the early-write
mode, input and output can be connected directly to give a
common I/O data bus.
2. Data Output Hold
The data output can be held between read cycles, without
lengthening the cycle time. This enables extremely flexible
clock-timing settings for RAS and CAS.
• MITSUBISHI
.... EL~CTRIC
MITSUBISHI LSls
MSK4164NS-1S, NS-20
65 536·BIT (65 536·WORD BY 1·BIT) DYNAMIC RAM
3. Two Methods of Chip Selection
Since the output is not latched, CAS is not required to keep
the outputs of selected chips in the matrix in a highimpedance state. This means that CAS and/or RAS can
both be decoded for chip selection.
4. Extended-Page Boundary
By decoding CAS, the page boundary can be extended
beyond the 256 column locations in a single chip. In this
case, RAS must be applied to all devices.
Page-Mode Operation
This operation allows for multiple-column addressing at the
same row address, and eliminates the power dissipation
associated with the negative-going edge of RAS, because
once the row address has been strobed, RAS is maintained.
Also, the time required to strobe in the row address for the
second and subsequent cycles is eliminated, thereby decreasing the access and cycle times.
Power Dissipation
Most of the circuitry in the M5K4164NS is dynamic, and
most of the power~issipated when addresses are strobed.
Both RAS and CAS are decoded and applied to the
M5K4164NS as chip-select in the memory system, but if
RAS is decoded, all unselected devices go into stand-by
independent of the CAS condition, minimizing system
power dissipation.
Power Supplies
The M5K4164NS operates on a single 5V power supply.
A wait of some 500J,ls and eight or more dummy cycles
is necessary after power is applied to the device before
memory operation is achieved.
Refresh
Each of the 128 rows (Ao '" A 6 ) of the M5K4164NS must
be refreshed every 2 ms to maintain data. The methods of
refreshing for the M5K4164NS are as follows.
1. Normal Refresh
Read cycle and Write cycle (early write, delayed write or
read-modify-write) refresh the selected row as defined by
the low order (RAS) addresses. Any write cycle, of course,
may change the state of the selected cell. Using a read,
write, or read-modify-write cycle for refresh is not recommended for systems which utilize "write-OR" outputs since
output bus contention will occur.
2. RAS Only Refresh
A RAS-only refresh cycle is the recommended technique
for most applications to provide for data retention. A
RAS-only refresh cycle maintains the output in the
high-impedance state with a typical power reduction of
20% over a read or write cycle.
3. Hidden Refresh
A features of the M5K4164NS is that refresh cycles may
be performed while maintaining valid data at the output pin
by extending the CAS active time from a previous memory
read cycle. This feature is refered to as hidden refresh.
Hidden refresh is performed by holding CAS at V I Land
taking RAS high and after a specified precharge period,
executing a RAS-only cycling, but with CAS held low.
The advantage of th is refresh mode is that data can be
held valid at the output data port indefinitely by leaving
the CAS asserted. In many applications this eliminates the
need for off-chip latches.
• MITSUBISHI
.... ELECTRIC
2-73
E1
MITSUBISHI LSls
MSK4164NS-1S, NS-20
65 536·BIT (65 536·WORD BY I.BIT) DYNAMIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol
Para mater
Conditions
Unit
Limits
-1-7
V
-1-7
V
VOO
Supply voltage
VI
I nput voltage
Vo
Output voltage
-1-7
V
10
Output current
50
mA
1000
mW
With respect to Vss
Pd
Power dissipation
Topr
Operating free-air temperature range
Tstg
Storage temperature range
Ta =25·C
·C
-65-150
RECOMMENDED OPERATING CONDITIONS
Symbol
·C
0-70
(Ta =0-7O"C, unless otherwise noted) (Note 1)
Limits
Parameter
Unit
Min
Nom
Max
VOO
Supply voltage
4.5
5
5.5
V
Vss
Supply voltage
0
0
0
V
VIH
High-level input voltage, all inputs
2.4
6.5
V
VIL
Low-level input voltage, all inputs
-2
0.8
V
Note 1: All voltage values are with respect to Vss
ELECTRICAL CHARACTERISTICS
± 10%,
(Ta =0-70·C, Voo=5V
VSS=OV, unless otherwise noted) (Note 2)
Limits
Symbol
Parameter
Test conditions
Min
Typ
Max
VOH
High-level output voltage
IOH=-5mA
2.4
Voe
VOL
Low·level output voltage
10L =4.2mA
0
0.4
10Z
Off-state output current
Q floating
-10
10
II
I nput current
1001(AV)
Average supply current from Vee,
operating (Note 3, 4)
1002
Supply current from Vee, standby
1003(AV)
1004(AV)
OV;;;;VoUT;;;;5.5V
OV;;;;VIN;;;;6.5V, All other pins
M5K4164NS- 15
M5K4164NS-20
OV
-10
V
f.J.A
10
f.J.A
50
mA
tOR =t OW = min output open
45
rnA
5
rnA
cycling
Average supply current from Vee,
M5K4164NS-15
RAS
refreshing (Note 3)
M5K4164NS- 20
t O(REF)= min, output open
Average supply current from Vee,
page mode (Note 3, 4)
M5K4164NS-15
r
V
RAS,CAS cycling
=
RAS =VIH output open
M5K4164NS-20
Unit
40
rnA
35
rnA
RAS =VIL. CAS cycling
40
rnA
to PG = min, output open
35
rnA
5
pF
CAS=VIH
CI (A)
Input capacitance, address inputs
CI (D)
Input capacitance, data input
VI=VSS
5
pF
CI(W)
Input capacitance, write control input
f=1MHz
7
pF
CI (RAS)
Input capacitance, RAS input
VI=25rnVrrns
CI (OAS)
Input capacitance, CAS input
Co
Output capacitance
Note 2:
VO=VSS. f= 1MHz, VI=25rnVrrns
Current flowing into an I C is positive; out is negative.
3:
1001 (AV). I e03(AV). and 1004(AV) are dependent on cycle rate. Maximum current is measured at the fastest cycle rate.
4:
1001 (AV) and 1004(AV) are dependent on output loading. Specified values are obtained with the output open.
2-74
• MITSUBISHI
.... ELECTRIC
10
pF
10
pF
7
pF
MITSUBISHI LSls
MSK4164NS-1S, NS-20
65 536-BIT (65 536-WORD BY I-BIT) DYNAMIC RAM
TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write, Refresh, and Page-Mode Cycle)
(Ta =0-70°C, Vcc=5V ± 10%, VSS=OV, unless otherwise noted, See notes 5, 6 and 7)
M5K4164NS-15
Symbol
Alternative
Parameter
M5K4164NS-20
Limits
Min
Unit
Limits
Symbol
Max
Min
Max
toRF
Refresh cycle time
tREF
t W(RASH)
RAS high pulse width
t RP
100
t W(RASL)
RAS low pulse width
t RAS
150
10000
200
10000
ns
t W(CASL)
CAS low pulse width
tCAS
75
00
100
00
ns
t W(CASH)
CAS high pulse width
t CPN
35
40
t h (RAS-CAS)
CAS hold time after RAS
tCSH
150
200
ns
t h (CAS- RAS)
RAS hold time after CAS
t RSH
75
100
ns
(Note 9)
t CRP
-20
(NotepO)
t RCO
25
(Note 8)
td (CAS- RAS)
Delay time. CAS to RAS
t d (RAS-CAS)
Delay time, RAS to CAS
2
2
120
ns
ns
-20
75
ms
ns
100
30
ns
t SU(RA-RAS)
Row address setup time before RAS
t ASR
0
0
t SU(CA-CAS)
Column address setup time before CAS
tASC
-5
-5
ns
t h (RAS-RA)
Row address hold time after RAS
t RAH
20
25
ns
ns
t h (CAS-CA)
Column address hold time after CAS
t CAH
25
35
t h (RAS-CA)
Column address hold time after RAS
tAR
95
120
t THL
Transition time
3
tT
35
ns
ns
3
50
ns
tTLH
Note 5'
6'
7:
8:
9:
10:
An initial pause of 500).ls is required after power-up followed by any eight RAS or RAS/CAS cycles before proper device operation is achieved.
The switching characteristics are defined as t THL = t TLH = 5n s.
Reference levels of input signals are VI H min. and VI L max. Reference levels for transition time are also between VI H and VI L.
Except for page-mode.
td(CAS-RAS) requirement
IS
only applicable for RAS/CAS cycles preceded by a CAS only cycle (I. e. for systems where CAS has not been decoded with RAS).
Operation within the td (RAS-CAS) max limit insures that ta (RAS) max can be met. td (RAS-CAS)maX is specified reference point only;if
td (RAS-CAS) is greater than the specified td (RAS-CAS) max limit, then access time is controlled exciusivel'l by ta (CASI.
td (RAS-CAs)min = th (RAS-RA)min
+ 2t THL(t TLH) + t
SWITCHING CHARACTERISTICS
Read Cycle
Symbol
su (CA-CAS)min.
(Ta=0-70°C, Vcc=5V±10%, VSs=OV, unlessotherwisenoted)
M5K4164NS-15
Alternative
Parameter
M5K4164NS-20
Limits
Symbol
Min
Limits
Max
Unit
Max
Min
toR
Read cycle time
t RC
260
330
tsu (R-CAS)
Read setup time before CAS
t RCS
0
0
ns
th (CAS-R)
Read hold time after CAS
(Note 11)
t RCH
0
0
ns
the RAS-R)
Read hold time after RAS
(Note 11)
tRRH
20
tdis (CAS)
Output disable time
(Note 12)
tOFF
0
ta (CAS)
CAS access ti me
(Note 13)
tCAC
ta (RAS)
RAS access time
(Note 14)
t RAC
Note 11:
Note 12:
Note 13:
Note'14:
ns
ns
25
50
ns
75
100
ns
150
200
ns
40
0
Either th (RAS-R) or th (CAS-R) must be satisfied for a read cycle.
tdis (CAS)maX defines the time at which the output achieves the open circuit condition and is not reference to VOH or VOL.
This is the value when td (RAS-CAS)~td (RAS-CAS)max. Test conditions; Load; 2TTL, CL; 100pF
This is the value when td (RAS-CAS)< td (RAS-CAS)max. When td (RAS-CAS)~ td (RAS-CAs)m,ax, ta (RAS) will increase by the amount that
td (RAS-CAS) .exceeds the value shown. Test conditions; Load; 2TTL C L ; 100pF
Write Cycle
Symbol
Alternative
Parameter
M5K4164NS-15
r-'
M5K4164NS-20
Limits
Unit
Limits
Symbol
Min
tow
Write cycle time
tsu (W-CAS)
Write setup time before CAS
Min
Max
260
330
ns
t wcs
-10
-10
ns
t RC
(Note 17)
Max
th (CAS-W)
Write hold time after CAS
t WCH
45
55
ns
th (RAS-W)
Write hold time after RAS
tWCR
95
120
ns
th (W-RAS)
RAS hold time after write
t RWL
45
55
ns
th (W-CAS)
CAS hold time after write
tCWL
45
55
ns
tW(W)
Write pulse width
t WP
45
55
ns
tsu CD-CAS)
Data-in setup time before CAS
t OS
0
0
ns
th (CAS-D)
Data-in hold time after CAS
t OH
45
55
ns
th (RAS-O)
Data-in hold time after RAS
t OHR
95
120
ns
• MITSUBISHI
.... ELECTRIC
2-75
MITSUBISHI LSls
MSK4164NS-1S, NS-20
6S S36-BIT (6S S36-WORD BY I-BIT) DYNAMIC RAM
Read-Write and Read-Modify-Write Cycles
Alternative
Symbol
Parameter
M5K4164NS-15
M5K4164NS-20
Limits
Symbol
Limits
Max
Min
Min
Unit
Max
tCRW
Read-write cycle time
(Note 15)
tRWC
280
340
ns
tCRMW
Read-modify-write cycle time
(Nute16)
tRMWC
310
390
ns
th (W-RAS)
RAS hold time after write
t RWL
45
55
ns
th (W-CAS)
CAS hold time after write
tCWL
45
55
ns
tW(W)
Write pulse width
twp
45
55
ns
CAS
RAS to write
tsu (R-CAS)
Read setup time before
td (RAS-W)
Delay time,
t RCS
0
0
ns
(Note 17)
t RwO
120
150
ns
(Note 17)
tcwo
td (CAS-W)
Delay time, CAS to write
tsu (O-W)
Data-in set-up time before write
th (W-O)
tdis (CAS)
ta (CAS)
CAS access time
(Note 13)
t CAC
ta (RAS)
RAS access time
(Note 14)
t RAC
Note 15:
16:
60
80
ns
t OS
0
0
ns
Data-in hold time after write
t OH
45
Output disable time
tOFF
55
40
0
ns
50
ns
75
100
ns
150
200
ns
0
= tdIRAS-W) + th (W-RAS) + tw (RASH) + 3t TLH (tTHL)
is defined as t CRM W min = ta (RAs)maX + th (W-RAS) + tw (RAS H) + 3t TLH(tTHL)
t CRwmin is defined as tCRW min
t CRMW min
17: tsu (W-CAS), td (RAS-W), and td (CAS-W) do not define the limits of operation, but are included as electrical characteristics only.
When t su (W-CAS)~ tsu (W -CAs)min, an early-write cycle is performed, and the data output keeps the high-impedance state.
When td (RAS-W)~td (RAS-W)min. and td (CAS-W)~tsu (W-CAS)min a read-write cycle is performed, and the data of the selected address will be read out
on the data output.
For all conditions other than those described above, the condition of data output (at access time and until CAS goes back to VI H) is not defined.
Page-Mode Cycle
Alternative
Symbol
Parameter
M5K4164NS-15
M5K4164NS-20
Limits
Symbol
Min
Limits
Max
Min
Unit
Max
tcPGR
Page-mode read cycle time
tpc
145
190
t cPGW
Page-mode write cycle time
t PC
145
190
ns
tcPGRW
Page-mode read-write cycle time
--
180
230
ns
-
190
245
ns
60
80
ns
tCPGRMW
Page-mode read-modify-write cycle time
tw (CASH)
CAS high pulse width
2-76
tcp
• MITSUBISHI
;"ELECTRIC
ns
MITSUBISHI LSls
MSK4164NS-15, NS-20
6S S36·BIT (6S S36·WORD BY I-BIT) DYNAMIC RAM
TIMING DIAGRAMS
(Note17)
Read Cycle
~~-----------------------tCR
II
t-o---------------t w(RASL)---------------0
U2
te=260ns-
T
30
U2
~~
Ww
<.:JCl.
«0
Ww
<.:JCl.
«0
t J= 1000ns
10
a
25
50
75
Vee (V)
//
,/
:::>«
(/)0::
ffi
>
«
6.0
//
30
Cl.f-
tJ=500ns
20
~
~
r<.:J
C:~
~z
____
5.5
40
0
0
wcr:w
0::0
:::>0
r<.:J
(/)~
o E
fE,::
fZ
t e=330ns
~
Ta = 25°CJ
Vee=5.5V
2::t
o E
a
____
5.0
50
~.
Vee=5.5V
>
f-
~~
AVERAGE SUPPLY CURRENT FROM Vee,
OPERATING MODE VS. FREQUENCY
>
~'--'
__
SUPPLY VOLTAGE
AVERAGE SUPPLY CURRENT FROM Vee,
OPE RA TI NG MODE VS.
AMBIENT TEMPERATURE
~.
4.5
20
ffi
>
«
10
100
AMBIENT TEMPERATURE Ta (OC)
a
FREQUENCY
• MITSUBISHI
.... ELECTRIC
f ( E
::2'~
o
2.8
V
N
~.?
w
rz
w
a:
a::
::J
u
0
0
~
2.4
/
rco
>- 0
~
0:
I-
0..
::J
2.0
/
(1)
8:?
V
>
::2'
5
0
0
~~
t-w
zO
wo
2.4
~::2'
UCll
o:~
5.0
5.5
2.0
1.6
6.0
25
50
75
100
AVERAGE SUPPLY CURRENT FROM Vee,
REFRESH MODE VS. SUPPLY VOLTAGE
AVERAGE SUPPLY CURRENT FROM Vee,
REFRESH MODE VS.
AMBIENT TEMPERATURE
40~----~----~----~----~
~~E
a:
uo
t e (REF) = 260ns
30~----~-----+--~~-----1
0..(1)
t e (REF) = 1000ns
10
,--j=::::;:::;t.....-i'---1
o..(/)
o..w
::Ja:
O~
____
4.0
~
____
4.5
~
____
5.0
SUPPLY VOLTAGE
~
____
WW
<.'Ja::
<{
5.5
-
t e (REF) = 500n s
I
T
t e (REF) = 1000n s
o
25
50
75
100
AMBIENT TEMPERATURE Ta (OC)
Vee (V)
AVERAGE SUPPLY CURRENT FROM Vee,
PAGE MODE VS. SUPPLY VOLTAGE
40r-----~----_r----~----~
~.
Ta=25°cJ
Ta =25°C
>
::2'
::2'--...
30
V
r- ..,
0
0
20
>-:2
...JI
0..(1)
o..w
wW
<.'Ja:
<{
t e (REF) = 330n s
10
o
6.0
Vee=5.5V
~~
-~
-,-
>
<(
~
40
~.
>
uO
te(REF)=260ns
(/)ll.
AVERAGE SUPPLY CURRENT FROM Vee,
REFRESH MODE VS. FREQUENCY
a:a:w
::JO
-~
5
w
ll.~
20
...JI
...JI
o..w
::Ja:
O<{
a: E
30
r::2'
(/)u.
>
<(
ll.~
a:
a:w
::JO
uO
20r---~~~--1--
I
::2'--...
O<{
a: E
§§
>-~
WW
<.'Ja:
<{
a:
Vee=5.5V
>
§g
a:a:w
::JO
40
8
Ta= 25°C
ll.~
10
/
/
~
V
./
0--...
a::<{
ll.
E
30.....------+------+--t e
(PG)
= 170ns
r-~
zW
~
u
a:: u
a::::Jw
Uo
>-0
0:::2'
o..W
::J<.'J
~;;:
10~--~~-----+-----~----~
l~
<{
a::
5
W
o
>
<(
O~----~----~~--~~--~
4.0
4.5
5.0
5.5
6.0
o
FREQUENCY
2-82
o
AMBIENT TEMPERATURE Ta ("C)
u
u
>
<(
............ .....
SUPPLY VOLTAGE Vee (V)
>
zW
"
>-0
o..riii(/)
1.6
4.5
~
::Jr
(/)
4.0
"-
2.8
N
I(¢»
(MHz)
SUPPLY VOLTAGE Vee (V)
• MITSUBISHI
. , . ELECTRIC
MITSUBISHI LSls
MSK4164NS-1S, NS-20
65 536·BIT (65 536·WORD BY 1-BIT) DYNAMIC RAM
AVERAGE SUPPLY CURRENT FROM Vee,
PAGE MODE VS. FREQUENCY
AVERAGE SUPPLY CURRENT FROM Vee,
PAGE MODE VS. AMBIENT TEMPERATURE
40
Ta=2S!C
Vee=S. SV
u'
u
Vee=S.SV
u
>
>
~
o~
cr:<{
E
ll..
cr:c:~
"-w
W"-
= nOns
t e CPG)
W
a:
te
..
0
30
0
cr:~W
Uo
= SOOns
~o
&~
T
10
E
f-~
Z
:::t
---
~o
~l9
(/)«
ll..
t e CPG)
teCPG)=200ns
20
40
cr:<{
-10..
W 0
cr: 0
Uo
~
o~
--
30
f-~
Z ..
~w
C~ 1000ns
--
20
~l9
(/);t
W
19
19
«
ffi
>
«
10
«
cr:
W
>
«
o
o
25
50
75
o
FREQUENCY f (¢) (MHz)
RAS, CAS, W, REF INPUT VOLTAGE
VIH1, VIL1 VS. AMBIENT TEMPERATURE
RAS, CAS, W, REF INPUT VOLTAGE
VIH1, VIL1 VS. SUPPLY VOLTAGE
2.S r----"T"'""--""T"""--....,.---.....
« 2:
2.S
Vee~5. 5V
19
~
0
>
~
Z
W
« >
::i
->
f-
19
f-
2.0
t---+-----+----+---~
VIHI (min)
I
->
~
~
V------
o
100
AMBIENT TEMPERATURE Ta (OC)
W
II
50
u'
...I
0
>
f-
~
~
1. S t---+----+-----<----:--~
~
~
...I
->
2.0
VIHl (min)
I
->
I~
1.5
JILl (max)
Ii
~
~
1.0t---+---+-----+-----f
0.5~-~~--~--~--.....
4.0
4.5
5.0
5.5
6.0
I~
~
1.0
0.5
o
25
50
75
100
SUPPLY VOLTAGE Vee (V)
AMBIENT TEMPERATURE Ta (OC)
Ao"'A7, DIN INPUT VOLTAGE VIH2, VIL2
VS. SUPPLY VOLTAGE
Ao"'A7, DIN INPUT VOLTAGE VIH2, VIL2
VS. AMBIENT TEMPERATURE
2:
2:
2.S
Ta=2S0C
~
I
->
->
2.0
W
19
«
~
o
>
1.S
-.----
-'"'""
f-
VI'12 (min)
~--t'.
-
VIL2 (max)
~--
2.0
VIH2 (min)
-,-
19
«
f...I
o
>
VIL2 (max)
1.5
f-
12
z
z
6
Z
1.0
6
.t
I
.'l
JN
W
~
z
I
Vee=5.5 V
...I
->
N
2.5
N
O.S 4.0
4.5
5.0
5.5
6.0
:j
I
.'l
1.0
0.5
0
25
so
75
100
AMBIENT TEMPERATURE Ta (OC)
SUPPLY VOLTAGE Vee (V)
• MITSUBISHI
.... ELECTRIC
2-83
MITSUBISHI LSls
MSK4164NS-1S, NS-20
65 536-BIT (65 536-WORD BY I-BIT) DYNAMIC RAM
SUPPLY CURRENT VS. TIME
(/)
~
0
RAS
CAS
.9
100
ICC
(mA)
~8
~8
a
100
~8
Iss
(mA) ~8
a
Sans/DIVISION
TIME
2-84
t
• MITSUBISHI
"'ELECTRIC
MITSUBISHI LSls
MSL 2114L P, P-2, P-3
4096·BIT (1024.WORD BY 4.BIT) STATIC RAM
DESCRIPTION
This is a family of 4096-bit static RAMs organized as 1024
words of 4 bits and designed for simple interfacing. They
are fabricated using N-channel silicon-gate MOS technology. They operate with a single 5V supply, as does TTL,
PIN CONFIGURATION (TOP VIEW)
II
and the inputs and outputs are directly TIL compatible.
I/O terminals are common.
Vee (SV)
ADDRESS INPUTS
FEATURES
ADDRESS INPUTS
Parameter
MSL 2114LP-2
MSL 2114LP-3
MSL 2114LP
Access time (max)
200ns
300ns
450ns
Cycle time (min)
200ns
300ns
450ns
•
Low power dissipation: 50tLw/bit (typ)
•
•
Single 5V supply voltage (±10% tolerance)
Requires neither external clock nor refreshing
•
All inputs and outputs are directly TTL compatible
•
All outputs are three-state, with OR-tie capability
CHIP SELECT INPUT
(OV) GND
•
Easy memory expansion by chip-select (CS) input
•
Common data I/O terminals
•
Interchangeable with Intel's 2114L and TI's TMS4045 in
pin configuration and electrical characteristics
APPLICATION
•
DATA
INPUTS/OUTPUTS
Small-capacity memory units
FUNCTION
These devices operate with a single 5V power supply, and
the inputs and outputs are directly compatible with TTL.
All circuits are completely static, rendering external clock
and refresh operations unnecessary, and making the members of the series extremely easy to use. Common data
input and output terminals are provided.
Outline 18P4
During a write cycle, when a location is designated by
address signals Ao"'A9 and the R/W signal goes low, the
data at the I/O terminals is written.
During a read cycle, when the R/W signal goes high and a
location is designated by address signals Ao "'A 9, the dat.8
of the designated address is available at the I/O terminals.
When signal CS is high, the chip is in the non-selectable
state, disabling both reading and writing. !n this case the
data outputs are in the floating (high-impedance) state,
useful for OR-ties with the output terminals of other
chips.
BLOCK
DIAGRAM
1024-WORD x 4-BIT
64
12
RAM
~
\64 ROWS x
:::l
w
(/)
as
(/)
64 COLUMNS)
co
ADDRESS INPUTS
z·
16
~
:::l
c5
U
CHIP SELECT INPUT C S 8
READ/WRITE INPUT R/W 1 0 ) - - - - - - - - - - - - - - - - - - - - - - '
J
L -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
• MITSUBISHI
"ELECTRIC
2-85
MITSUBISHI LSls
MSL 2114L P, P-2, P-3
4096·BIT (1024.WORD BY 4.BIT) STATIC RAM
ABSOLUTE MAXIMUM RATINGS
Palameter
Symbol
Vee
Supply voltage
VI
Input voltage
Vo
Output voltage
Pd
Maximum power dissipation
Unit
Limits
Conditions
With respect to GND
-0.5-7
V
-0.5-7
V
-0.5-7
Topr
Operating free-air ambient temperature range
TstQ
Storage temperature range
"C
(Ta = 0 - 70°C, unless otherwise noted)
Limits
Parameter
Min
Units
Nom
Max
5
Vee
Supply voltage
5.5
V
VIL
Low-level input voltage
-0.5
0.8
V
VIH
High-level input voltage
2
Vee
V
4.5
ELECTRICAL CHARACTERISTICS
"C
0-70
-65-150
RECOMMENDED OPERATING CONDITIONS
Symbol
V
mW
700
Ta=25°C
(Ta =0-70°C.
Vce=5V ± 10%, unless otherwise noted)
Limits
Symbol
Parameter
Test conditions
Min
Typ
VIH
High-level input voltage
2
VIL
Low-level input voltage
-0.5
1---.
VOH
High-level output volta(je
10H= -200,uA.
VOH
High-level output voltage
10H=-lmA.
VOL
Low-level output voltage
IOL=2.1mA
Max
Vee
Vee=4.5V
2.4
Vee=4,75V
2.4
0.8
Unit
V
V
V
V
0.4
V
II
Input current
VI=0-5.5V
10
,uA
10ZH
Off -state high-level output current
VI(CS)=2V. Vo=2.4V-Vee
10
,uA
10ZL
Off-state low-level output current
VI(CS) =2V. VO=0.4V
-10
f-lA
lee
Supply current from Vee
VI = 5. 5V. (all inputs), output open.Ta=25°C
40
65
mA
Ci
Input capacitance, all inputs
VI =GND. V;=25mVrms. f= lMHz
3
5
pF
Co
Output capacitance
Vo=GND. Vo=25mVrms. f= lMHz
5
8
pF
Note 1 Current
flOWing
Into an IC IS positive: out IS negative
TIMING REQUIREMENTS (For Write
Cycle)(Ta=o-70°c.
Vec=5V±10%, unless otherwise noted) (Note 2)
Parameter
All.
symbol
tC(WR)
Write cycle time
tSU(AO)
Address setup time with respect to write pulse
twe
Typ
Limits
Limits
Limits
Min
M5L 2114LP
M5L 2114L P-3
M5L 2114L P-2
Symbol
Max
Min
Typ
Max
Min
Typ
Unit
Max
200
300
450
ns
0
0
0
ns
tW(WR)
Write pulse width
tw
120
150
200
ns
twr
Write recovery time
tWR
0
0
0
ns
tSU(OA)
Data setup time
tow
120
150
200
ns
th(OA)
Data hold time
tOH
0
0
0
ns
tsu(CS)
Chip select
120
150
200
tPXZ(WR)
Output disable time with respect to write pulse
~etup
time
SWITCHING CHARACTERISTICS (For Read Cycle)
Parameter
Symbol
M5L 2114L P-3
Limits
Limits
Min
Read cycle time
tRe
ta(AO)
Address access time
tA
ta(6s)
Chip select access time
teo
Typ
Max
200
ns
Vee=5V ± 10%, unless otherwise noted)(Note 2)
M5L 2114L P-2
All.
symbol
tC(RO)
(Ta =0-70°C.
ns
100
80
40
tOTW
Min
Typ
M5L2114LP
Limits
Max
300
Min
Typ
Unit
Max
450
ns
200
300
450
ns
80
100
120
ns
100
ns
tpXZ(CS)
Output disable time with respect to chip select
tOTO
tdv (AO)
Data valid time with respect to address
tOHA
50
50
50
ns
tPZX(C5)
Chip select to output active
tex
20
20
20
ns
2--86
40
• MITSUBISHI
"ELECTRIC
80
MITSUBISHI LSls
MSL 2114L P, P-2, P-3
4096-BIT (1024-WORD BY 4-BIT) STATIC RAM
TIMING DIAGRAMS
Read Cycle
tC(RD)
--+----+- ta (OS)
I/O 1-1/04
DATA OUT VALID
IDA TA. OUTPUTS)
ta(AD)
_+----+-_td v (AD)
Write Cycle
-------1"1
tC(WR)
Ao-A9
tSU(AD) __~_ _ _ _'-4-._ _ _ _ _
tW~(W~R~)_ _ _ _ _~_ _ _-+~_twr
R/W
tsu(OS)
tsu (DA)
I/O 1-1/04
DATA STABLE
IDA TA INPUTS)
- __+----+-_t PXZ (W R)
I/O 1-1/04
_+---~
__ t PXZ(OS)
DATA OUT INVALID
(DA TA OUTPUTS)
Note
Note 3
2 Test conditions
Hatching indicates the state is don't care
O.8-2V
Input pulse level
Input pulse rise time
20ns
Input pulse fall time
20ns
Reference level
Input
1,5V
Output
1,5V
Load=1TTL.
CL=100pF
• MITSUBISHI
.... ELECTRIC
2-87
MITSUBISHI LSls
MSL 2114L P, P-2, P-3
4096-BIT (1024-WORD BY 4-BIT) STATIC RAM
TYPICAL CHARACTERISTICS
NORMALIZED ACCESS TIME VS.
SUPPLY VOLTAGE
NORMALIZED ACCESS TIME VS.
OUTPUT LOAD CAPACITANCE
Ta=70"C
Ta=70"C
LOAD = 1T T L
OL= 100pF
LOAD = 1TTL
o
~
1.4
~
.3
1.3
~
1.3
~
1. 2
~
1.2
~
1.1
f=
OL= 100pF
f=
C/)
t2
u
~
1. 1
r---1.0
-
8NO.9
::J
~
O.B
~
0.7
c:
1.4
~
~
1.0
~
0.9
~
O.B
c:
~
0.6
4.0
5.0
0.7
0.6
100
6.0
SUPPLY VOLTAGE
Vee
(V)
~ 10.0
~
/
I-
c:
::J
U
5.0
~
z
Vi
I-
ir
I-
::J
0
~
~
/
I
V
0.0
0.0
V
\
\
I-
iE
c:
c:
::J
U
w
u
c:
5.0
::J
0
C/)
I-
ir
0
0.6
OUTPUT VOLTAGi='
APPLICATION EXAMPLE
O.B
OL (pF)
0.0
0.0
1.0
VOL (V)
1.0
i'..
3.0
2.0
OUTPUT VOLTAGE
4.0
V OH (V)
(for an M5L8080A P CPU)
ADDRESS BUS (A 15-AO, A 15:MSB)
OSO
OS1
OS2
OS3
MSB
4·BIT
LSB
4·BIT
MEMR
MEMW--~----------~----~--~----~---+------+-~~----~--+-
DATA BUS
M5L2114LP XB (BK BYTES)
2-88
600
1\
\
I-
0.4
500
V CO=4.5V
Ta=70·C
::J
0.2
400
\
10.0
5l
:/
iE
c:
300
OUTPUT SOURCE CURRENT VS.
OUTPUT VOLTAGE
/V
...J
5l
200
OUTPUT LOAD CAPACITANCE
OUTPUT SINK CURRENT VS.
OUTPUT VOLTAGE
VOO=4.5V
Ta=70"C
---------
• MITSUBISHI
.... ELECTRIC
5.0
MITSUBISHI LSls
MSL S101LP-l
1024-BIT (256-WORD BY 4-BIT) CMOS STATIC RAM
DESCRIPTION
This is a 256-word by 4-bit static RAM fabricated with the
silicon-gate CMOS process and designed for low power dissipation and easy application of battery back-up.
The device has two chip-select inputs CSl and CS 2 •
While maintained in the chip non-select state, the device
consumes power at the low value of only 1 Op.A (max)
standby current and accor,dingly is especially suitable as a
memory system for battery-operated applications and for
battery back-up.
The device operates on a single 5V supply, as does TTL,
and inputs and outputs are directly TTL-compatible and
are provided with common I/O terminals.
PIN CONFIGURATION (TOP VIEW)
ADDRESS INPUTS
CHIP SELECT INPUT
OUTPUT
DISABLE INPUT
CHIP SELECT INPUT
DATA OUTPUT
DATA INPUT
DATA OUTPUT
DATA INPUT
DATA INPUT
DATA OUTPUT
FEATURES
450ns (max)
• Access time:
• Low power dissipation in
10pA (max)
the standby mode:
• Single 5V power supply
• Data holding at 2V supply voltage
• No external clock or refreshing operation required
• Both inputs and outputs are directly TTL-compatible
• Outputs are three-state, with OR-tie capability
• Simple memory ~xpansion by chip-select signals
• Input and output data terminals are separate
• Interchangeable with Intel's 5101 L-1 in pin configuration and electrical characteristics
APPLICATION
• Battery-driven or battery back-up small-capacity memory units
FUNCTION
The device provides separate data input and output terminals.
,._._._._.
II
(5V)
DATA OUTPUT
DATA INPUT
Outline 22P1
During a write cycle, when a locaticn is designated by
address signals Ao"'A7 and signal R/W goes low, the data of
the 01 inputs at that time is written.
During a read cycle, when a location is designated byaddress signals Ao"'A7' and signal R/W goes high, the data of
the designated address is available at the DO terminals.
When signal CSl is high or CS 2 is low, the chip is in the
non-selectable state, disablil1g both reading and writing.
In this case, the output is in the floating (high-impedance
state) useful for OR-ties with the output terminals of other
chips.
When the signal 00 is high, the output is in the floating
state, so that 00 is used as an input/output select control
signal for common input/output operation.
The memory data can be held at a supply voltage of 2V,
enabling battery back-up operation during power failure
and power-down operation in the standby mode.
BLOCK DIAGRAM
'-'-'-'-'1
~vcc
256·WORD x 4·BIT
RAM
(32 ROWS x
32 COLUMNS)
Cf>
(5V)
GNO (OV)
ADDRESS INPUTS
I
L._._._.
R/W
READ/WRITE
INPUT
011012013014
cst
CSz
00
OUTPUT DISABLE INPUT
DATA INPUTS
CHIP SELECT INPUTS
• MITSUBISHI
"ELECTRIC
2-89
MITSUBISHI LSls
MSL S101LP-l
1024-BIT (256-WORD BY 4-BIT) CMOS STATIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol
Conditions
Parameter
Vce
Supply voltage
VI
Input voltage
Vo
Output voltage
Pd
Maximum power dissipation
Topr
Operating free-air ambient temperature range
Tstg
Storage temperature range
With respect to GND
Limits
Min
V
Supply voltage
4.5
5
5.5
V
Supply voltage
0
0
0
V
0.65
V
Vee
V
VIL
Low-level input voltage
-0.3
VIH
High-level input voltage
2.2
(Ta = 0 - 70,,(;.
Vee = 5V
Min
High-level input voltage
2.2
VIL
Low-level input voltage
-0 3
~,
YaH
High-level output voltage
10H= -lmA
VOL
Low-level output voltage
IOL=2mA
"C
"C
Typ
Max
Vee
V
V
2.4
Ii
Input current
VI =0-5.5V
Off -state high-level output current
VI(esl)=2.2V. VO=2 ,4V -Vee
10ZL
Off-state low-level output current
VI(es1)=2.2V. Vo=0.4V
CS 1;;;;0 .6SV. other inputs = Vee.
Output open
CS1~0.6SV.
other inputs=2.2V.
Output open
Unit
0.65
0.4
10ZH
Supply current from Vee
0-70
-65-150
Limits
Test conditions
VIH
lee2
mW
± 10%, unless otherwise noted)
Parameter
Supply current from Vee
V
700
Max
Vss
leet
o -Vee
Unit
Nom
Vee
Symbol
V
(Ta=0-70"C, unless otherWise noted)
Parameter
ELECTRICAL CHARACTERISTICS
Unit
-0 3-Vee+0.3
Ta =25"C
RECOMMENDED OPERATING CONDITIONS
Symbol
Limits
-0.3-7
V
V
+1
/-lA
1
/-lA
-1
/-lA
9
22
mA
13
27
mA
lee3
Supply current from Vee
CS2 ;S:;:0.2V
10
/-lA
C,
Input capacitance, all inputs
VI =GND. Vi =2SmVrms. f= 1MHz
4
8
pF
Co
Output capacitance
Vo=GND. Vo =2SmVrms. f= 1MHz
8
12
pF
Notel: Current flOWing Into an IC IS positive: out IS negative,
TIMING REQUIREMENTS (For Write Cycle)
Symbol
(Ta =0-70"(;.
Vec=SV
Alt
Parameter
Write cycle time
twe
tW(WR)
Write pu:se width
twp
tsu (AO)
Address setup time with respect to write pulse
tAW
twr
Write recovery time
tsu (00)
10%, unless otherWise noted)
Limits
Test conditions
symbol
te (WR)
±
Min
Typ
Unit
Max
450
ns
250
ns
VIH =2 .2V
130
ns
tWR
VIL=0.65V
50
ns
00 setup time with respect to data-in
tos
tr=tf=20ns
130
ns
tsu (OA)
Data setup time
tow
Reference level = 1 . 5 V
250
ns
th (OA)
Data hold time
tOH
Load
50
ns
tsu (es1)
Chip select setup time
teWt
350
ns
tsu (OS2)
Chip select setup time
tew2
350
ns
Input pulse
SWITCHING CHARACTERISTICS (For Read Cycle)
Symbol
te (RO)
~)
Parameter
tRe
tA
Chip select access time
ta (eS2)
Chip select access time
--~
te02
ta (00)
00 access time
too
tpxz
Output disable time (note 2)
tOF
tdv(CS)
Date valid time with respect to Chip select
tdv (AO)
Data valid time with respect to address
Limits
Min
Typ
Unit
Max
ns
450
Input pulse
450
VIH=2.2V
VIL =0.6SV
tr=tf=20ns
Reference level
=
1 _5 V
Load = lTTL. CL = 100pF
0
ns
400
ns
500
ns
250
ns
130
ns
0
tOHt
--
Note 2: tpxz is from CSt ,CS2 . or 00, whichever occurs first.
2-90
vee=SV±10%, unless without noted)
Test conditions
symbol
Read cycle time
CL = 100pF
(Ta=0-70"C.
Alt.
Address access time
ta (cst)
= lTTL.
• MITSUBISHI
..... ELECTRIC
0
ns
MITSUBISHI LSls
MSL S101LP-l
1024-BIT (256-WORD BY 4-BIT) CMOS STATIC RAM
TIMING DIAGRAMS
Read Cycle
to
ta
II
(RD)
(051)
ta
(00)
00
ta
tpxz
(AD)
(NOTE 4)
DATA OUT VALID
DO
Write Cycle
to
(WR)
AO-A7
OS1
tsu (052)
00
th (DA)
tsu (00)
01
tsu (OA)
DATA IN VARIABLE
DATA IN STABLE
tW(WR)
twr
R/W
tsu (AD)
Note 3 : Hatching indicates the state is unknown.
4 : Indicates that during this period the data-out is invalid for this
definition of td v (AD) and is in the floating state for this definition
of tpxz
• MITSUBISHI
"ELECTRIC
2-91
MITSUBISHI LSls
M5L 5101LP-l
1024·BIT (256·WORD BY 4.BIT) CMOS STATIC RAM
POWER-DOWN OPERATION
Electrical Characteristics
(Ta =0 -70·C unless otherwise noted)
Limits
Parameter
Symbol
Test conditions
Vee(po)
Power-down supply voltage
CS2;;:;;;0_2V
lee(po)
Power-down supply current from Vee
Vee=2 V. all inputs =2 V
Timing Requirements
Parameter
Unit
tsu(PO)
Power-down setup time
t R(PO)
Power-down recovery time
Typ
Max
0
ns
tC(RO)
ns
Timing Diagram
Vee
Max
ts u ( PO )-'-+----Io.. -'\,,---
OV
• MITSUBISHI
.... ELECTRIC
Unit
V
10
(Ta =0-70·C, Vee=5V ±10%. uniess otherwise noted)
Min
Typ
2
Limits
Symbol
2-92
Min
/-LA
MITSUBISHI LSls
MST 4044 P-20, P-30, P-4S
4096-BIT (4096-WORD BY I-BIT) STATIC RAM
DESCRIPTION
This is a family of 4096-word by l-bit static RAMs, fabricated with the N-channel silicon-gate MOS process and
designed for simple interfacing. They operate with a single
5V supply, as does TTL, and are directly TTL-compatible.
PIN CONFIGURATION (TOP VIEW)
II
(5V)
FEATURES
•
•
•
•
•
•
•
Parameter
M5T 4044P-20
M5T 4044P-30
M5T 4044 P -45
Access time (max)
200ns
300ns
450ns
Cycle time (min)
200ns
300ns
450ns
Low power dissipation: 50pw/bit (typ)
Single 5V supply (±10% tolerance)
Requires no clocks or refreshing
All inputs and outputs are directly TTL-compatible
All outputs are three-state and have OR-tie capability
Simple memory expansion by chip-select (CS) input
Interchangeable with TI's TMS4044 in pin configuration
and electrical characteristics
ADDRESS INPUTS
ADDRESS INPUTS
DATA OUTPUT DOUT- 7
READ/WRITE INPUT
RI W ..... 8
DATA INPUT
CHIP SELECT INPUT
(OV) GND
Outl ine 18P4
APPLICATION
• Small-capacity memory units
FUNCTION
These devices are very convenient to use, as they feature
static circuits which require neither external clocks nor
refreshing, and all inputs and outputs are directly compatible with TTL.
During a write cycle, when a location is deSignated by
address signals Ao"'A •• and the R/W signal goes low, the
DIN signal data at that time is written.
During a read cycle, when the R/W signal goes high
and a location is designated by address signals Ao"'A •• ,
the data of the designated address is available at the DOUT
terminals.
When signal CS is high, the chip is in the non-selectable
state, disabling both reading and writing. In this case the
output is in the floating (high-impedance) state, useful
for OR-ties with other output terminals.
BLOCK DIAGRAM
!
(5V)
4096-WORD xl-BIT
RAM
R/W
CONTROL
CIRCUIT
SENSE
AMPLIFIER
(64 ROWS x
64 COLUMNS)
ADDRESS INPUTS
OUTPUT
7
DOUT DATA OUTPUT
BUFFER
64
DATA INPUT
READ/WRITE INPUT R/W 8
CHIP SELECT INPUT
1-----------------------'
os 1 0 ' ) - - - - - - - - - - - - - - - - - - - - - - - - '
.• MITSUBISHI
.... ELECTRIC
2-93
MITSUBISHI LSI.
M5T 4044 P-20, P-30, P-45,
4098·BIT (4098·WORD BY l .. BIT) STATIC RAM
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Vee
Supply voltage
VI
Input voltage
Conditions
With respect to GND
Vo
Output voltage
Pd
Maximum power dissipation
Topr
Tstg
Unit
Limits
-0.5-7
V
-0.5-7
V
-0.5-7
V
700
mW
Operating free-air ambient temperature range
-65-150
"C
Storage temperature range
-40-125
"C
Ta=25"C
RECOMMENDED OPERATING CONDITIONS
Symbol
(Ta = 0 - 70"C. unless otherwise noted)
limits
Parameter
Units
Min
Nom
Max
Vee
Supply voltage
5.5
V
VIL
Low-level input voltage
-0.5
0.8
V
VIH
High-level input voltage
2
Vee
V
5
4.5
ELECTRICAL CHARACTERISTICS
(Ta = 0 -70"C.
Vee = 5V
±
10%. unless otherwise noted)
Limits
Symbol
Test conditions
Parameter
Typ
Min
VIH
High-level input voltage
2
VIL
Low-level input voltage
-0.5
VOH
High-level output voltage
IOH= -200,uA.
Vee =4.5V
2.4
VOH
High-level output voltage
IOH=-1.0mA.
Vec=4.75V
2.4
VOL
Low-level output voltage
IOL=2.1mA
Max
Vee
0.8
Unit
V
V
V
V
0.4
V
II
Input current
VI=0-5.5V
10
,uA
IOZH
Off-state high-level output current
VI(CS)=2V. VO=2.4V-Vee
10
,uA
IOZL
Off-state low-level output current
VI(CS) =2V. VO=0.4V
-10
,uA
lee
Supply current from Vee
V 1= 5.5 V. (all inputs). output open. Ta = 25°C
40
65
mA
Ci
Input. capacitance. all inputs
'II =GND. Vi=25mVrms. f= lMHz
3
5
pF
Co
Output capacitance
Vo=GND. Vo =25mVrms. f= lMHz
5
8
pF
Note1: Current flowing into an IC
IS
positive: out
IS
negative.
TIMING REQUIREMENTS (For Write Cycle)
(Ta=0-70"C.
M5T 4044P-20
M5T 4044P-30
Limits
Limits
Parameter
Symbol
Min
te(WR)
Write cycle time
tSU(AD)
Address setup time with respect to write pulse
tW(WR)
Write pulse width
twr
Write recovery time
tSU(DA)
Data setup time
th(DA)
Data hold time
tsu(CS)
Chip select setup time
tPXZ(WR)
Output disable time with respect to write pulse
Max
Read cycle time
Address access time
ta(eS)
tpXZ(CS)
tdV(AD)
Data valid time with respect to address
Limits
Max
Min
Typ
Unit
Max
450
ns
0
0
ns
120
150
200
ns
0
0
0
ns
120
150
200
ns
0
0
0
ns
(Ta =0 - 70"C,
Vee= 5V
M5T 4044P-30
Limits
200
Min
ns
± 10%. unless otherwise noted) (Note 2)
Limits
Max
100
80
M5T 4044P-20
Typ
ns
200
150
40
Parameter
te(RD)
Typ
300
120
ta(AD)
Min
0
Min
2-94
Typ
M5T 4044P-45
200
SWITCHING CHARACTERISTICS (For Read Cycle)
Symbol
Vec=5V± 10%. unless otherwise noted) (Note 2)
Typ
M5T 4044P-45
Unit
Limits
Max
300
Min
Typ
Max
ns
450
200
300
450
ns
Chip select access time
70
100
100
ns
Output disable time with respect to chip select
40
80
100
ns
50
• MITSUBISHI
.... ELECTRIC
50
50
ns
MITSUBISHI LSI.
M5T 4044 P-20, P-30, P-45
4096-BIT (4096-WORD BY 1-BIT) STATIC RAM
TIMING DIAGRAMS
Read Cycle
II
tC(RD)
Ao-All
--+----t--ta(cs)
DATA OUT VALID
DOUT
ta(AD)
_+---+-_tdv (AD)
Write Cycle
tC(WR)
Ao -All
tW
t SU (AD) __4-----+__- - - .:..:..:...;(W.;.:.R,;:..)---_+-_ _ _-+-_ twr
R/W
tsu(CS)
tsu(DA)
DATA STABLE
- - - f - - - - i - - t PXZ(WR)
DOUT
Note
_-+---+--t PXZ(CS)
DATA OUT INVALID
Note 3 : Hatching indicates the state is don't care.
2 Test conditions
0.8 -2V
Input pulse level
Input pulse rise time
20ns
Input pulse fall time
20ns
Reference level
Input
1.5 V
Output
1.5 V
Load =1TTL.
CL=100pF
• MITSUBISHI
.... ELECTRIC
2-95
MITSUBISHI LSls
MST 4044 P-20, P-30, P-45
4096-BIT (4096-WORD BY 1-BIT) STATIC RAM
TYPICAL CHARACTERISTICS
NORMALIZED ACCESS TIME VS.
OUTPUT LOAD CAPACITANCE
NORMALIZED ACCESS TIME VS.
SUPPLY VOLTAGE
Ta=70'C
LOAD = 1TTL
CL=100pF
'0
.5
1.4
8
1.4
:J
1.3
:J
1.3
~
1.2
lli
1.1
~
C/J
C/J
:E
1.2
UJ
1.1
~
~
0.9
~
~
a:
~
1.0
~
i=
-
-
0.8
~
1.0
~
0.9
~
0.8
~
5.0
6.0
0.7
0.6
100
Vee (V)
Vce=4.5V
Ta=70'C
10.0
/
.J
::
~
I-
z
a:
a:
:J
u
5.0
/
(ii
I-
:J
0..
I-
:J
0
/
0.0
0.0
/
200
300
:;(
I
..5
J:
::
~
10.0
\
I-
a5
a:
a:
:J
u
UJ
u
a:
5.0
:J
\
0
C/l
I-
:J
0.
I-
0.6
OUTPUT VOLTAGE
APPLICATION EXAMPLE
0.8
C L (pF)
i\
\
:J
0.4
600
Vce=4.SV
Ta=70'C
0
0.2
500
400
OUTPUT SOURCE CURRENT VS.
OUTPUT VOLTAGE
/
UJ
z
--------
~
OUTPUT LOAD CAPACITANCE
OUTPUT SINK CURRENT VS.
OUTPUT VOLTAGE
~
.-----
a:
oz
0.7
0.6
4.0
SUPPLY VOLTAGE
<
..5
Ta=70'C
LOAD = 1TTL
CL= 100pF
0.0
0.0
1.0
2.0
1.0
VOL (V)
OUTPUT VOLTAGE
~
4.0
3.0
5.0
VOH (V)
(for 8K-Byte Memory System)
This circuit is designed for a separate data bus application; and input can be tied.
if a common data bus application is required, the output
8K BYTES MEMORY SYSTEM M5T 4044P x 16
A I 5 - - - -......
Al4
Al3
ADDRESS INPUTS
---,,--
Al2
All
I
Ao
TO ALL
RAMS
ADDRESS
INPUT
MEMORY WRITE SIGNAL
(LOW ACTIVE)
MEMORY READ SIGNAL
(LOW ACTIVE)
0
l::l
0
0
~
~ ~
l-
I-
0
0
« «
.+,..MITSUBISHI
2-96
~
Al-
ADDRESS
INPUTS
+- As
3:
....
+- Ag
~
0
l>
~
~
(J)
(J)
El-
11
GND
-
01
-
0,
-
03
-
04
I
+-E2
Outline 1851
OUTPUTS
CHIP ENABLE
INPUT
(M54740AS, M54741AS)
18P4 (M54740AP,
M54741AP)
by cutting the fuses of the memory cells. The output level
is high before programming and low when written into.
The 4096 memory cells have a capacity of 1024 words
and one word is composed of 4 bits. A word is selected
from the 1024 words by address inputs A o "'A 9 , and 4-bit
parallel outputs 0 1 -04 are produced.
The input and output threshold voltage is the same as
that for a TTL system and thus direct coupling can be made
with TTL logic. The open-collector outputs (in the
M54740AP,S) or 3-state outputs (in the M54741AP,S)
enable AND-tie connection.
When both chips enable inputs Et and E; are low, the
output is enabled and the contents of the memory selected
BLOCK DIAGRAM
--------=---!
I
I
1024 WORDS X 4 BITS
ROM
(64 LINES X 64 ROWS)
I:~ ~--
~vec ADDRESS
A3 4
INPUTS
6
!
A
A~
7
1024 WORDS X 4 BITS
ROM
(64 LINES X 64 ROWS)
Ao ;
EN~~~~{~~
E2~
INPUTS
L - ___----{
01
OUTPUTS
* OPEN
COLLECTOR OUTPUTS
M54741AP,5
M54740AP,5
3
14
OUTPUTS
• MITSUBISHI
.... ELECTRIC
GND
MITSUBISHI BIPOLAR DIGITAL ICs
MS4 7 40AP ,S/MS4 7 41AP ,S
4096-BIT(1024-WORD BY 4-BIT)FIELD PROGRAMMABLE ROM
by the address input appear in the outputs. When either
chip enable input Et or E2 is high, the output is disabled,
and regardless of the address input, the output is set high
(open-collector) or put in the high-impedance mode (3state).
READ FUNCTION TABLE (Note 1)
Read function table for
Read function table for
M54740AP,S
M54741AP,S
E,
E2
L
L
H
-
-
E,
E2
0,-04
Wn
L
L
Wn
L
H
H
L
Z
L
H
H
L
H
Z
H
H
H
H
H
Z
0,-04
I
--
Note 1. Wn:
Z
Memory contents wrilten in Wn word appear in output.
High·impedance state
ABSOLUTE MAXIMUM RATINGS (Ta=25°C, unless otherwise noted)
Parameter
Symbol
Limits
Conditions
Unit
Vee
Supply voltage
~0.5-+7
V
VI
Input voltage
~0.5-
+5.5
V
Vo
Output voltage
~0.5-
+5,5
V
VOP
Appl ied output voltage
tw(P)/te(P)
Duty cycle
Topr
Operating free·air ambient temperature range
Tstg
Storage temperature range
H igh·level state
--
21
V
25
%
When writing
°C
0-- + 75
~65-
RECOMMENDED OPERATING CONDITIONS
(Ta=0~+75°C,
+ 150
°C
unless otherwise noted)
Limits
Symbol
Unit
Parameter
Vee
Supply voltage
10H
High-level output current (M54741AP/S only)
10H
10L
VOH~
2.4
Min
Nom
Max
4.75
5
5.25
V
0
~2
High·level output current (M54740AP/S or;ly) Vo=5V
0
50
fJ. A
Low-level output current
0
16
mA
VOL;;;;;O.45V
ELECTRICAL CHARACTERISTICS
mA
(Ta=-20~+75°C, unless otherwise noted)
Limits
Parameter
Symbol
VIH
High·level input voltage
VI L
Low-level input voltage
VIC
I nput clamp voltage
VOH
Test conditions
Min
Typ
*
Unit
Max
V
~
Vee=4,75V,IIC=-18mA
Vec=4.75V, VI=2V, VI=0.8V
High-level output voltage (M54741AP,S)
10H= ~2mA
2.4
0.8
V
1.2
V
3.1
V
-----------+----+---~--_r----_;
Vec=5.25V, VI=2V, VI=0.8V
High·level output current (M54740AP,S)
50
VO=5V
VCC=4.75V, VI=2V, VI=0.8V,
Low-level output voltage
0.3
I OL = 16mA
VCC=5.25V, VI=0.8V,
Off-state high-level output current (M54741 AP ,S)
VI=2V, VO=2.4V
Vce=5.25V, VI=0.8V,
10ZL
Off-state high-level output current (M54740AP ,S)
IIH
High-level input current
Vcc=5.25V, VI=2.4V
IlL
Low-level input current
Vce=5.25V, VI=0.4V
0.45
~---4---------------------~----
~
160
15
V
50
fJ. A
~50
fJ.A
VI=2V, VO=0.4V
~
fJ.A
40
fJ. A
~250
fJ. A
~100
mA
170
mA
los
Short-circuit output cummt (M54741AP,S) (Note 2)
Vee=5.25V, VO=OV
I cc
Supply current (Note 3)
VCC= 5. 25V, VI=DV
GIN
Input capacitance
VCC=5V, VI=2V, f=lMHz
pF
GOUT
Output capacitance
VCC=5V, VO=2V, f= 1MHz
pF
120
~--~-----------------------+-~------------~---+--~---+----~
* All typical values are at VcC=5V, Ta=25°C
Note 2. All measurements should be done quickly and not more than one output should be shorted at a time.
Note 3. Icc is measured with all inputs at GND .
• MITSUBISHI
.... ELECTRIC
3--15
II
MITSUBISHI BIPOLAR DIGITAL ICs
M54740AP,S/M54741AP,S
4096-BIT(1024-WORD BY 4-BIT)FIELD PROGRAMMABLE ROM
SWITCHING CHARACTERISTICS
(Vcc=5V±5°/C. Ta=O-75°C. unless otherwise noted)
Limits
ta
(A)
Unit
Test conditions
Parameter
Symbol
Min
Typ
Max
25
55
ns
15
25
ns
15
25
ns
Address access time
ta CEJ
Chip enable access time
teD (E:)
Chip disable time
Note 4. Measurement circuit
(Note 4)
INPUT
Vee
Vee
OUTPUT
(1)
The pulse generator (PG) has the following characteristics:
(2)
CL includes probe and jig capacitance.
E1
or E2
PRR~lMHz, tr~6ns, tf~6ns, tpw~500ns, Vp~3Vp.p. Zo~50n.
DUT
50Q
TIMING DIAGRAM (Referencelevel~15V)
OV
3V
Ao-Ag
OV
VOH
0,-04
OV
VOH
(NORMAL-PHASE)
_ _+---J
VOL
VOH
0,-04
(OUT -OF-PHASE)
RECOMMENDED WRITE CONDITIONS (Ta~25°C, unless otherwise noted)
-Limits
Parameter
Symbol
Unit
Min
Typ
Max
VIH(P)
High-level input voltage
2.4
5
5
V
VIL(P)
Low-level input voltage
0
0
0.4
V
VO(p)
Applied output voltage
20
21
21
V
tw(P)
Applied pulse width
0.05
0.18
50
ms
t w (p)!t e (P)
Duty cycle
tr
Pulse risetime
5
20
25
%
10
30
IJ.S
N(p)
Number of pulses applied
4
Vee(p)
Write supply voltage
5
lop
Appl ied output current
VeeL(v)
Low-level supply voltage with check after writing
3--16
-
V
100
4.4
• MITSUBISHI
;'ELECTRIC
mA
V
MITSUBISHI BIPOLAR DIGITAL les
M54740AP,S/M54741AP,S
4096-BIT(1024-WORD BY 4-BIT)FIELD PROGRAMMABLE ROM
PROGRAMMING TIMING DIAGRAM
Vee(p)
VeCL(V)
Vee
II
Ao-Ag
VO(P)
OV
OUTPUT OFF STATE
VOH
,r------
PROGRAMMING
CHECK
Note 5. The VOIP) waveform is the voltage waveform applied to the output during programming; the 0 1 -0 4 waveforms
the output level of the device itself.
Note 6. Waveform E indicates either the E; or E; waveform; the other is V1LlP).
indicate
PROGRAMMING PROCEDURE
The area into which the data are programmed is the fuses
which are composed of 4096 memory cells. When no data
are programmed into a memory cell, the output is set to
the logic high level (fuse: closed). Proceed as instructed below to set to the logic low level (fuse: open).
(1) Apply the supply voltage V CC(P) (5V typ).
(2) Select the programming word with the address inputs
Ao""'A9 (input voltage: V1H(P) 5V typ, V1L(P) OV typ).
(3) Set either chip enable input pin ~or Ez high (V1H(P)
5V typ) and set the outputs off.
(4) Apply the output pulse VO(P) (21V typ) to the output
which corresponds to the bit into which the data are to
be programmed. Apply this to one output at a time
and not to two or more outputs simultaneously.
(5) Set both ~ and E; low (V1L(P) OV typ).
(6) Reduce the supply voltage to VCCL(V) (4.4V typ) and
check whether the data has been programmed.
(7) If the check is affirmative in step (6), repeat steps (1)
through (6) to program the next word or bit.
If the check is negative in step (6), repeat steps (1)
through (6) but if the check is still negative even after four
repetitions, the device may be cOllsidered defective.
Refer to the programming timing diagram for the timing
of the programm ing operation.
• MITSUBISHI
"ELECTRIC
3-17
MITSUBISHI LSls
M58653P
700·BIT (SO·WORD BY 14·BIT) ELECTRICALLY ALTERABLE ROM
DESCRIPTION
The M58653P is a serial input/output 700 bit electrically
PIN CONFIGURATION (TOP VIEW)
erasable and reprogrammable ROM organized as 50 words
of 14 bits, and fabricated using MNOS technology. Data
(5V)
Vss
VM(NC)
(-30V)
VGG
VGND(OV)
and addresses are transferred serially via a one-bit bidirectional bus.
DATA INPUT/
OUTPUT
NC
FEATURES
• Word-by-word electrically alterable
• Non-volatile data storage:
10 years (min)
• Write/erase time:
• Typical power supply voltages:
-30V, +5V
• Number of erase-write cycles:
• Number of read access unrefreshed:
20ms/word
105 times (min)
109 times (min)
NC
NC
NC
NC
CLOCK INPUT ClK_
MODE CONTROL
INPUT
-C3
f
MODE CONTRoe
INPUTS
-C2
C1-
• 5V I/O interface
APPLICATION
Outline 14P4
• Non-volatile channel memories for electronic tuning
systems and field-reprogrammable read-only memory
systems
FUNCTION
The address is designated by two consecutive one-of-tencoded digits. Seven modes-accept address, accept data,
shift data output, erase, write, read, and standby-are
all selected by a 3-bit code applied to C1, C2 , and C3 . Data
is stored by internal negative writing pulses that selectively tunnel charges into the Si0 2 -Si 3 N4 interface of the
gate insulators of the MNOS memory transistors.
BLOCK DIAGRAM
1---
------:
1 Vss(5V)
2
MEMORY
TRANSISTOR
ARRAY
(50-WORD BY
14-BIT)
VGG( -30V)
READ
WRITE
ERASE
6 ClK CLOCK INPUT
3-18
• MITSUBISHI
"'ELECTRIC
NC
NO CONNECTION
MITSUBISHI LSls
M58653P
700-BIT (SO-WORD BY 14-BIT) ELECTRICALLY ALTERABLE ROM
PIN DESCRIPTION
Name
Pin
Functions
----------~----------------~------------------------------------------------------------------------------~
In the accept address and accept data modes. used for Input
1/0
I/O
In the shift data output mode. used for output
In the standby. read. erase and write modes. this Pin IS In a floating state
I-----------+------------------+--u--s-e-d-for
testing purposes only
Test
VM
Vss
Chip substrate voltage
Normally connected to+5V
VGG
Power supply voltage
Normally connecteci to -30V
CLK
Clock Input
14kHz timing reference
It should be left unconnected durin-g--nO-rm-a-l-o-p-er-at-,o-n-----------------------_--I
_
ReqUired for all operating modes
C1 ~C3
Mode control input
Used to select the operation mode
VGND
Ground voltage
Connected to ground (OV)
Hlgh-Ioval input is possible during standby mode
-----------------------------------------------------1
OPERATION MODES
Cl
C2
H
H
H
H
H
Functions
H
Standby mode The conte~ts of the address registers and the data register remain unchanged
in the floating state
1 he output buffer is held
Not used
H
Erase mode: The word stored at the addressed location IS erased. The data bits after erasing are all low-level
Accept address mode. Data presented at the 110 pin is shifted into the address registers one bit with each clock pulse
H
The
address IS designated by two one-of-ten-coded digits
H
H
Read mode
The addressed word is read from the memory into the data register
Shift data output mode. The output driver is enabled and the contents of the data register are shifted to the 1/0 pin one bit
H
with each clock pulse
H
Write mode
The data contained In the data register is written into the location designated by the address registers
Accept data mode:
The data register accepts serial data from the 1/0 pin one bit with each clock pulse
The address
registers remain unchanged
• MITSUBISHI
"ELECTRIC
3-19
II
MITSUBISHI LSls
M58653P
700-BIT (SO-WORD BY 14-BIT) ELECTRICALLY ALTERABLE ROM
ABSOLUTE MAXIMUM RATINGS
Symbol
VGG
VI
Input voltage
Vo
Output voltage
Limits
Conditions
Parameter
Supply voltage
Unit
0.3- -40
With respect to Vss
V
0.3- -20
V
0.3- - 20
V
Tstg
Storage temperature range
- 40- 125
'C
Topr
Operating free-air temperature range
-10-70
°C
RECOMMENDED OPERATING CONDITIONS
(Ta= -10-70°C
unless otherwise noted)
Limits
Unit
Parameter
Symbol
Min
Nom
Max
-37.8
V
6
V
VGO-VSS
Supply voltage
-32.2
-35
VSS-VOND
Supply voltage
4.75
5
VIH
High-level Input voltage
VSS-l
VSS + 0.3
V
VIL
Low-level input vOltage
Vss-6.5
V ss-4. 25
V
ELECTRICAL CHARACTERISTICS
(Ta= -10-70'C, VOo-Vss = -35V± 8
%,
VSS-VOND
=5V~2~~.
unless otherwise noted)
limits
Unit
Test conditions
Parameter
Symbol
Min
VIH
Hi9h-level Input voltage
VIL
Low-level input voltage
IlL
Low-level Input current
VI-Vss=-6.5V
IOZL
Off-state output current. low-level voltage applied
VO-VSS = - 6.5V
VOH
High-level output voltage
IOH = -200J-lA
VOL
Low-level output voltage
IOL=10J-lA
IGG
Supply current from VGG
lo=OJ-lA
Typ
Max
+ 0.3
VSS-l
VSS
V SS -6.5
V ss - 4.25
V
V
±
10
J-lA
±
10
J-lA
V
VSS-l
5.5
VGNO +0.5
V
8.8
mA
Note 1 . Typical values are at Ta=25°C and nominal supply voltage.
TIMING REQUIREMENTS
(Ta=-10-70°C. VGG-Vss=-35V± 8%,
Alternative
Parameter
Symbol
symbols
VSS-VGND=5V~2~~.
unless otherwise noted)
Limits
Test conditions
Unit
Min
Typ
Max
f(¢)
Clock frequency
f¢
11.2
14
16.8
O(¢)
Clock duty cycle
O¢
30
50
55
%
tw(W)
Write time
tw
16
20
24
ms
tW(E)
Erase time
te
16
20
24
ms
tr.
Risetime. fall time
tr.
1
J-lS
tsu(c- ¢)
Control setup time before the fall of the clock pulse
tcs
0
ns
th( ¢-c)
Control hold time after the rise of the clock pulse
tCH
0
ns
tf
SWITCHING CHARACTERISTICS
Parameter
Symbol
ta(c)
(Ta= -10-70'C.
Read access time
t!
VGG = -35V+
- 8 %. unless otherwise noted)
Alternative
symbols
tpw
Limits
Test conditions
Unit
Min
CL= 100PF VOH=Vss-2V
Typ
Max
20
VOL=VGNO+l.5V
ts
kHz
Ts
NEW= 10 4 ,
Ts
NEW= 105 •
J-lS
tw(W)= 20ms
10
Year
1
Year
tw (E) =20 ms
Unpowered nonvolatile data retention time
tw(W) =20ms
tW(E) =20 ms
NEW
Number of erase/write cycles
Nw
105
Times
NRA
Number of read access unrefreshed
NRA
10 9
Times
tdv
Data valid time
tpw
3-20
• MITSUBISHI
"ELECTRIC
20
J-lS
MITSUBISHI LSls
M58653P
700-BIT (SO-WORD BY 14-BIT) ELECTRICALLY ALTERABLE ROM
TIMING DIAGRAM
Accept Address Mode
CLK
II
C2
u---------___u_______________________________ _
I/O
ADDRESS LOCATION
LEAST SIGNIFICANT DIGIT
Note 2
The address is designated by two one-of-ten-coded digits. The figure shows
designation of the address 49.
Read Mode
CLK
Shift Data Output Mode
J1JUUU1Jl.JlJl
CLK
C2
C2
1 CLOCK CYCLE
Write Mode
I/O
CLK~MI1Il
C1
Accept Data Mode
CLK
C1
Erase Mode
CLKJUlMMM-
C21
C3
14 CLOCK CYCLES
~il---I-----,I
: l~E_t----'---':;(W)~.~
I.
ftI
tW(E)
I
I"---_ _--I;'~
c21
c31
I/O
I~
I~
----I;~:-------'il
,,---I
I
If
I'jl
.1
tdv
tate)
• MITSUBISHI
"ELECTRIC
14 CLOCK CYCLES
;0
I
3-21
MITSUBISHI LSls
MS873S-XXXP
32768-BIT( 4096-WORD BY 8- BIT) MASK-PROGRAMMABLE ROM
DESCRIPTION
The M58735-XXXP is a 32768-bit static mask-programmable read-only memory organized as 4096 words of
eight bits. It is housed in a 24-pin DI L package using
N-channel silicon gate M05 technology. The inputs and
outputs are TTL compatible.
The XXX in the type code is a three-digit decimal
number assigned by Mitsubishi to identify the customer's
specification to which the ROM has been programmed.
PIN CONFIGURATION (TOP VIEW)
Vee
ADDRESS
iNPUTS
FEATURES
•
•
•
•
•
•
•
19 +- AlO ADDRESS INPUT
Maximum access time:
350ns (max)
8-bit parallel output
By floating the output (high-impedance) using the chip
select inputs (51, 52). OR-tie connection is possible,
facilitating memory expansion.
The active logic level of the chip select inputs (51 and
52) can be programmed at the time of ROM masking
All inputs and outputs are TTL and DTL compatible
All inputs are provided with built-in protective circuits
Pin-compatibility with the M5L2732K
18
+-82/S2(~~lELECT
DATA
OUTPUTS
(OV)
GND
APPLICATION
•
(SV)
Outline 24 P4
Microcomputer memories
FUNCTION
The M58735-XXXP is a 4096 x 8-bit parall~1 output
ROM. Address inputs (Ao""'All} are decoded to select
one of the 4096 words, and the contents of that address
are made available at data outputs (00 ""'0 7 ), Chip selects
(51 and 52) are used to expand memory using two or
more M58735-XXXP ROMs. The contents of the ROM
--:-
can be read cnly when SI and S2 are at the programmed
input levels. Otherwise, data outputs (00 ""'0 7 ) are held in
the floating (high-impedance) state. The active logic level
of SI and S2 can be programmed at the time of
fabricating the ROM mask.
BLOCK DIAGRAM
- - - - - - - - - - - - - - - - - ------------~:~~ ~:~;
,
~
LL
::J
co
f-
ADDRESS
INPUTS
ir
z
II
w
(/)
o
o
~
~
II
o
o
128
o
«
X
L_--I
81/51
4096-WORD X 8-BIT
MASKPROGRAMMABLE
ROM
CHIP SELECT
INPUT BUFFER
DATA
OUTPUTS
CHIP
SELECT
PROG RAM MABLE
RDM
I'
-------j
82/82
'----v----"
CHIP SELECT INPUTS
3- 22
8x32
• MITSUBISHI
.... ELECTRIC
MITSUBISHI LSls
M58735-XXXP
32768-BIT(4096-WORD BY 8-BIT)MASK-PROGRAMMABLE ROM
ABSOLUTE MAXIMUM RATINGS
Symbol
VI
I nput voltage
V0
Output voltage
Pd
Power dissipation
Limits
Conditions
Parameter
Unit
--
-0.5 --7
.---V--=O-=-O_ _+-_S_UP_P_IY voltage
With reference to the GND
V
-0.5 -7
(with V I and Va at VOO=5V)
V
-0.5 -·7
V
1000
mW
Ta =25'C
0-70
~~~r-0_p_e_ra_t_in_g_te_m_p_e_ra_tu_r_e_ _ _ _ _ _ _ _ _ _ _ ~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _-+_____
_
Tstg
-
Storage temperature
RECOMMENDED OPERATING CONDITIONS
(Ta=O -70°C.
II
°C
65-150
T
unless otherwise noted)
Limits
Parameter
Symbol
VOO
Nom
Max
4.5
5
5.5
0
I
Hig~-Ievel
ELECTRICAL CHARACTERISTICS
Symbol
Vcot-l
V
-- 0.5
0.8
V
(Ta=O -70°C,
VOC=5V ±10%,
unless otherwise noted)
Limits
Parameter
Test conditions
Typ
Min
c----
High-level output voltage
VOL
Low-level output voltage
IOL = 2.2mA
Input current
VI=O --Voo
Unit
Max
2 .4
I OH= -400 I1A
VCH
I
V
2
input voltage
Low-Ievei input voltage
VIL
II
V
Supply voltage
GND
VIH
Unit
Min
V
0 .45
-10
- 10
V
10
I1A
10
I1A
120
mA
loz
Off-state output CLHrent
VO=0.45- V OO
100
Supply current from V 00
Output open,
Ci
I nput capacitance
Voc=5V, VI=Va= 0 V,
10
pF
Co
Output capacitance
f= lMHz, 25mVrms, Ta=25°C
15
pF
SWITCHI NG CHARACTERISTICS
80
--
VOO=5V ±10%, unless otherwise noted)
Limits
Parameter
Symbol
ta(AO)
(Ta =0 --70°C,
Ta =25°C
Unit
Test conditions (Note 2)
Access time from Address
CL=100pF,
Min
Typ
RL=2.1kQ(Notel)
Max
350
ns
------r~-------------------+_---------------------------i--·--~---~-----4
t PZX
Chip select propagation t:me
120
IlS
t pxz
Chip non-select propagation time
150
ns
TIMING DIAGRAM
Note 1 Load circuit
di~agram Vee
RL
Ao-Att
Qo -Q7
lee
1'°"
Note 2
~ The center line indicates a
~
'L
floatinq (high-impedance) state
Q 0 -- Q 7 -----i-iH]
tpzx
tpzx
ia(AO)
Input pulse level············O. 45 - 2.4 V
Input pulse risetimet r ······20ns
Input pulse falltime t f·· .. "20ns
Reference voltage for sw;tching characteriscic
measurements
Input VIH ············2V
VIL ············0.8V
VOH············2V
VOL············0.8V
OutP~t
• MITSUBISHI
"ELECTRIC
3-23
MITSUBISHI LSls
MSG1400P
1400-BIT (IOO-WORD BY 14-BIT) ELECTRICALLY ALTERABLE ROM
DESCRIPTION
The M5G 1400P is a serial input/output 1400-bit electrically erasable and reprogrammable ROM organized as 100
words of 14 bits, and fabricated using MNOS technology.
Data and addresses are transferred serially via a one-bit
bidirectional bus.
PIN CONFIGURATION (TOP VIEW)
(OV) Vss
( -35V)
FEATURES
• Word-by-word electrically alterable
• Non-volatile data storage: ••....•.......... 10 years (min)
• Write/erase time: ............................. 20ms/word
• Single 35V power supply
• Number of erase-write cycles: ........•••. 105 times (min)
• Number of read access unrefreshed:····10 6 times (min)
• Interchangeable with GI's ER1400 in pin configuration
and electrical characteristics
VM(NC)
VGG
NC
DATA INPUT/
NC
OUTPUT
NC
NC
NC
NC
CLOCK INPUT ClK-+
MODE CONTROL
INPUT
-C3
}MODE CONTROL
INPUTS
Cl-+
APPLICATION
-C2
Outline 14P4
NC: NO CONNECTION
• Non-volatile channel memories for electronic tuning
systems and field-reprogrammable read-only memory
systems
FUNCTION
The address is designated by two consecutive one-of-tencoded digits. Seven modes-accept address, accept data,
shift data output, erase, write, read, and standby-are
all selected by a 3-bit code applied to Cl , C2 , and C3 . Data
is stored by internal negative writing pulses that selectively tunnel charges into the Si0 2 -Si 3 N4 interface of the
gate insulators of the MNOS memory transistors'.
BLOCK DIAGRAM
-
------:
1 Vss(OV)
MEMORY
TRANSISTOR
ARRAY
(100-WORD BY
14-BIT)
READ
l
WRITE
ERASE
7 C
8 C2
}
MODE CONTROL INPUTS
9 C3
6 ClK CLOCK INPUT
--~
3-24
• MITSUBISHI
.... ELECTRIC
MITSUBISHI LSls
MSG1400P
1400-BIT (IOO-WORD BY 14-BIT) ELECTRICALLY ALTERABLE ROM
PIN DESCRIPTION
Name
Pin
Functions
In the accept address and accept data modes, used for input
In the shift data output mode, used for output
In the standby, read, erase and write modes, this pin is in a floating state.
I/O
I/O
~--~--------~II
VM
Test
Used for testing purposes only
Vss
Chip substrate voltage
Normally connected to ground
VGG
Power supply voltage
Normally connected to -35V
CLK
Clock Input
14kHz timing reference. Required for all operating modes
C,-C3
Mode control input
Used to select the operation mode
It should be left unconnected during normal operation
High-level input is possible during standby mode
OPERATION MODES
Cl
C2
C3
H
H
H
Standby mode The contents of the address registers and the data register remain unchanged
in the floating state
H
H
L
Not used
H
L
H
Erase mode: The word stored at the addressed location is erased. The data bits after erasing are all low-level
H
L
L
Accept address mode: Data presented at the I/O pin is shifted into the address registers one bit with each clock pulse. The
address is designated by two one-of-ten-coded digits.
L
H
H
Read mode: The addressed word is read from the memory into the data register
L
H
L
Shift data output mode: The output driver is enabled and the contents of the data register are shifted to the I/O pin one bit
with each clock pulse.
L
L
H
Write mode
L
Accept data mode: The data register accepts serial data from the I/O pin one bit with each clock pulse
registers remain unchanged.
L
L
Functions
The output buffer is held
The data contained in the data register is written into the location deSignated by the address registers.
• MITSUBISHI
..... ELECTRIC
The address
3-25
MITSUBISHI LSls
MSG 1400P
l400-BIT (lOO-WORD BY l4-BIT) ELECTRICALLY ALTERABLE ROM
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Limits
Conditions
Unit
----._----+------------------------------------+--------------------------------+-------------------~-------~
Supply voltage
0.3- -40
V
VI
Input voltage
0.3- - 20
V
VA
Output voltage
1'st9
Storage temperature range
-65-150
"C
T opr
Operati.,g free-air temperature range
-10-70
'c
VGG
With respect to Vss
-.
0.3- -- 20
RECOMMENDED OPERATING CONDITIONS
V
(Ta= -10-70'(;. unless otherwise noted)
Limits
Un,t
Parameter
Symbol
Min
Nom
Max
-32.2
-35
-37.8
V
VGG
Supply voltage
Vss
Supply voltage (GND)
VIH
High-level input voltage
VSS-l
VSS+ O. 3
V
VIL
Low-level input voltage
VSS-15
Vss-8
V
0
ELECTRICAL CHARACTERISTICS
V
(Ta= -10-70'C. VGG = -35V± 8
%.
Note 1:
The order of Vss VGG with on or off.
With on. VGG is turned on after Vss is done.
With off. Vss is turned off after VGG is done.
unless otherwise noted)
Limits
Unit
Test conditions
Paramete;-
Symbol
Min
Typ
Max
-VIH
High-level input voltage
VII_
Low-level input voltage
IlL
Low-level input current
VI=-15V
± 10
/-I A
IOZL
Off-state output current. low-level voltage applied
VO=--15V
± 10
/-I A
VOH
High-level output voltage
IOH'=-200/-lA
VOL
Low-level output voltage
10L = lO/-IA
IGG
Supply current from VGG
10 = 0/-1 A
I
VSS-l
Vss +0.3
V
Vss -15
Vss -8
V
I
Note 2:
V
Vss -1
5.5
Vss -12
V
8.8
rnA
Typical values are at Ta=25°C and nominal supply voltage
TIMING REQUIREMENTS
(Ta= -10-70'C. VGG
8
%.
unless otherwise noted)
Limits
Alternative
Parameter
Symbol
= --35V+
-
Unit
Test conditions
symbols
Min
Typ
Max
f(¢)
Clock fre-
1
~~
2
0
~L
1
0
F,
Fo
File name
2
3
0
Fl
F3
F,
...
3
F,
3110 3110311031 103 110 ···3110
:
'"O.~
~~
~-:::.
14
~
15
II III III I
II III III I
Fig. 2 RAM Address map
• MITSUBISHI
"ELECTRIC
1
0
Register X
I I
I I
MITSUBISHI MICROCOMPUTER
M58840-XXXP,M58841-XXXSP
SINGLE-CHIP 4-BIT MICROCOMPUTER
WITH 8-BIT AID CONVERTER
Registers Band E
AID Conversion Algorithms
Register B is composed of 4 bits and can be used as a 4-bit
AID conversion is controlled by the programming of the
previously described functional blocks. Thus, by modifying
the program either the successive approximation method or
the sequential comparison method may be selected. In
addition, a digital input of high or low level may be used to
select the method, eliminating software selection of the
A/D conversion technique.
(1) Successive Approximation Method
In this method, a constant conversion speed is main-
temporary storage register or for 8-bit data transfer in
conjunction with register A. Register E is composed of 8
bits and is used not only as an 8-bit temporary storage
register, but also as a
t~mporary
storage register for I/O
port S.
AID Conversion Circuit
The following AID conversion functions are controlled by
software as described below.
Fig. 3 shows the block
tained regardless of the amplitude of the analog signal.
The AID conversion process requires 0.6ms (at 600kHz
diagram.
(1) Comparators
These comparators are implemented entirely with
PMOS devices and use a chopper-type ampl ification
method. They are capable of determin ing the difference of the D/A converter output Vref and the port
K input signals VK(y) (where
(2) Register J
clock frequency). 12 program words are required.
(2) Sequential Comparison Method
In this method the conversion speed varies in accordance with the rate of change of the analog quantity.
When the rate of change is slow, the conversion rate
Y=0~13).
increases. 30 program words are required.
Register J is composed of 14 1-bit registers, each representing the comparison result from the comparators.
All register bits are set simultaneously. The value of the
register J with respect to the comparison results is as
follows.
>
[V ref [ <
1 when IVrefl
[VK(yd
Owhen
IVK(y)1
In this relationship(Y) represents the bit position in
register J which is designated by register Y. The
comparison results can be checked for each bit using
the SZJ instruction.
(3) Registers Hand L
VREF
ANALOG INPUTS
These two 4-bit registers are capable of transferring and
exchanging data to and from register A. The 8-bit
EXTERNAL REFERENCE
VOLTAGE INPUT
Fig. 3 A/D Conversion circuit block diagram
digital data for the D-A converter is transferred from
these registers, the higher order 4 bits from Hand
Interrupt Function
lower order 4 bits from L.
The flag I NTE is a 1-bit fl ip-flop used to control interrupt
(4) Register C
operation. When an interrupt request signal is applied to the
This 3-bit register is used as a counter to designate bit
pin I NT while the interrupt is enabled, the INTE flag is
positions in the Hand L registers.
reset to disable further interrupts, after which the program
(5) D/A Converter
jumps from the main program to address 0 of page 12. When
The D/A converter converts the digital values stored in
an interrupt program is used, one level of the three-level
the registers Hand L, referencing with the external
reference voltage V REF applied at the pin V REF , to
stack register is required, the remaining two levels being
used for subroutines. After the interrupt program is started,
the data pointer DP, register A, carry flag CY, and registers
used by the interrupt program must be saved and these
the analog value of the internal reference voltage Vref.
The theoretical value of the internal reference voltage
V ref is defined as follows.
V ref =
256
X
V REF
When an interrupt occurs, the microcomputer internal
states are as follows.
(1) Program Counter
where n = 1, 2, .......... 255
V ref=O
must be restored before returning to the main program. The
returning may be done by the execution of RTI instruction.
n - 0.5
where n=O
The current address in the main program is stored in a
In the above relationships n is the value weighted
stack register and the program counter is set to page
accorded to the contents of registers Hand L.
12, address O.
• MITSUBISHI
"ELECTRIC
4
5
II
MITSUBISHI MICROCOMPUTER
MS8840-XXXP,MS8841-XXXSP
SINGLE-CHIP 4-BIT MICROCOMPUTER
WITH 8-BIT AID CONVERTER
(2) Interrupt Flag INTE
The flag I NTE is reset to disable further interrupts.
This disabled state will continue even after the program
has returned from the interrupt routine to the main
program by the execution of the RTI instruction. EI is
executed and when the input level of the INT input
changes, this state is disabled. Thus, when the INTH
instruction is executed the interrupt state is enabled
when the INT input goes high. As long as it remains in
the high state, further interrupts are prohibited. If the
I NT input should change to a low level and return to
high, the next interrupt will be accepted.
(3) Skip Flags
Skip flags are provided for skip instructions and
consecutively described instructions and these skip
flags discriminate the skip and non skip conditions.
Each flag has its own stack within which the skip state
is saved.
As a mask option, the interrupt pin may be provided
with Schmitt input circuits.
Input/Output Pins
(1) Input port K
The input port K consists of 14 pins (15 pins for the
M58840-XXXP). The voltage level input at these pins is
compared with the O-A converter output voltage Vref
by a comparator and the results stored in register J. As
a mask option, it is possible to build into the input
port K load resistors. These are implemented using an
enhancement-type (M58840-XXXP) or depletion-type
(M58841-XXXSP) MOS transistors. In addition, to
enable the use of capacitive touch-type keys, it is
possible to provide these inputs with the required
discharge transistors.
(2) Input/Output Port S
The input/output port S consists of 8 bits, each bit
with an output latch. These latches are used to store
data transferred by means of a PLA from register A, or
data transferred from register A or register B directly. 4
bits at a time of the 8 input bits of port S may be
transferred to register A.
Because port S outputs are provided with a built-in
PLA, it is possible to output any arbitrarily settable
8-bit code from 4 input bits specified by register A.
These PLA output codes can be specified arbitrarily as
a masked option.
(3) Input/Output Port 0
The input/output port 0 consists of 11 bits. Each bit
can be individually designated as either input or output
and is provided with its own latch. The contents of the
data pointer register Y can be used to designate a single
bit of port 0 for output or sensing.
4
6
When port S or port 0 is used as an input port, the
output should first be cleared to the low state.
Reset Function
For the M58840-XXXP, when a power source satisfying the
conditions shown in Fig. 4 is applied, an internal power,on
reset function operates to reset the microcomputer. Cancelling of the reset state also is performed automatically, the
program being started at page 0, address O.
If the power-on reset function does not operate properly
because of the trailing edge characteristics of the power
supply, reset can be enabled by inputting a high level at the
V REF pin. Setting this V REF pin to low starts the program
at page 0, address O.
For the M58841-XXXSP, if the RESET input is kept
high for at least two machine .cycles, the reset state is
enabled. Because the M58841-XXXSP is provided with an
internal charging transistor it requires only an external
diode and capacitor as shown in Fig. 5.
For this configuration, when the supply voltage falls
below -13.5V, the circuit design should ensure that the
RESET input is above -4 V.
When the reset state is enabled, the following operations
are performed.
(1) The program counter is set to page 0, address 0
(PC) +- 0
(2) The interrupt mode is in the interrupt disabled state
(lNTE) +- 0
This is the same state as when the instruction 01 is
executed.
(3) By setting the interrupt request signal INT to high, the
interrupt enabled state is entered. This is the same state
as when the instruction INTH is executed.
(4) All outputs of port S are cleared to low (S) +- 0
(5) All outputs of port 0 are cleared to low (0) +- 0
(6) The carry and data pointer selector CPS is cleared to
low to designate OP and CY
(CPS) +- 0
Voo
~15V
ov ______-+___RE_S_ET________________ I
50rns min
~7V
10rnsMAX
Fig.4 M58840-XXXP Power on reset
OV
~POWERAPPLIED
~ 13.5V
\/00
ov
~4V
Fig.5 M58841-XXXSP Power on reset
• MITSUBISHI
"ELECTRIC
MITSUBISHI MICROCOMPUTER
M58840-XXXP ,M58841-XXXSP
SINGLE-CHIP 4-BIT MICROCOMPUTER
WITH 8-BIT AID CONVERTER
Clock Generator Circuit
A
clock
generator
circuit
has
been
built-in
to
Note 1. Since when using an RC circuit
the
M58840-XXXP and M58841-XXXSP, allowing control of
to determine frequency the fre-
450 kHz
quency will vary in accordance
the frequency by means of an externally connected RC
with the devise characteristics,
circuit or ceramic resonator. In addition, an external clock
the constants should be chosen
so that the frequency falls within
a specified limit even including
the effect of these variations
signal may be applied at the XI N pin, leaving the X OUT pin
open. Circuit examples are shown in Fig. 6 to Fig. 8.
Fig. 6 External RC circuit
Note 2. Constants should be chosen
to provide a clock duty cycle
in the range 50~60%. The
duty cyclE can be measured
at the T 4 pin. Note that the
required constants will also
vary with the frequency and
type of ceramic resonator
used
Fig. 7 Externally connected ceramic resonator
I
XIN
34t
xoJ
331
OV-,
15V
U
n n r
U U
EXTERNAL OSCILLATOR CIRCUIT
Fig. 8 External clock input circuit
• MITSUBISHI
..... ELECTRIC
4 -7
II
MITSUBISHI MICROCOMPUTER
M58840·XXXP,M58841·XXX5P
SINGLE·CHIP 4·BIT MICROCOMPUTER
WITH 8·BIT AID CONVERTER
MACHINE INSTRUCTION~ ~
r-~------~----------------~~~
fype 01 Mne.
Instruction code
"8 ~.~~~----------------------~--------~~-------------------------------------,
~
>:~~~ruc. monic De 0706050. 03D2DIDo 16 mal .~ 6
Functions
conS~~ons U
Description of operation
no t atlon
LX Y x,y
0
~ +-c-z+,-;;-----------c-,------+-~._-+LL-:-:-+_-------------,------~
1 1 x x
YYYY
0 C Y
1
1
101z
0
~
(Y )~y,
(X)~x,
where, x~0-3
where, y ~O '-15
where,
LZ z
00100
4A
1
1
(Z)~z,
INY
z
000000010002
1
1
(Y)~(Y)+1
(Y) ~O
DEY
0000000110031
(Y)~(Y)
(Y) ~ 15
+
1*
.~
B
.:.
1*
00001111001E
1
000011100 01C
1
00011101 OlD
1
0000 1 100 0 OC
000011001
19
001011001
59
1
0001101001A
1
000101100161
TAJ
00000110100D
1
1
(A)~(B)
1
1
(A)·· (Y)
(Y )~-(A)
(L)·-(A)
1
1
-1
LCPS i
0 0 1 0 0 0 0 0 i
0 4 i
t
(CPS)~"
r-~----r-------+--+-~-+TAB
TBA
TAY
TYA
TLA
THA
TEAB
TEPA
z~O.
Loads value of "x" into register X, and of "y" into Y. When LXY
is written successively, the first is executed and successive ones
are skipped
Loads value of "z" into register Z.
Written
successively
Increments contents of register Y by 1, Skips next instruction
when new contents of register Yare "0".
Decrements contents of register Y by 1 . Skips next instruction
when new contents of register Yare "15".
DP and CY are active when i= O. DP' and CY', when i= 1.
where, '-'0,1
Transfers contents of register B to register A
Transfers contents of register A to register B.
Transfers contents of register Y to register A
Transfers contents of register A to register Y.
Transfers contents of register A to register L.
(B)~(A)
(H)·-(A)
(E7-E4).-(B).
Transfers contents of register A to register H.
Transfers contents of registers A and B to register E.
Decodes contents of register A in the PLA and transfers result
(E3-Eo)~(A)
(E7-Eo)~-through PLA~(A)
to register E.
1
1
Transfers designated contents of register J to register A
when, (YIYO)~O
when, (YIYo)~1
(A)--(Jl1JloJ,Je) when, (YIYo)~2
(A)~(O JI4J13JI2) when, (YIYo)~3
(A)-(L)
(A)-(H)
(A)'-(J3J2JIJO)
(A)~(J7J.J5J.)
~
XAL
XAH
0000110000181
0010110000581
TAM j
o
01 10 01 j j
o 64
+
XAM j
0011000jj
o
XAMD j
o
o 68
1
1
1
I,
10 j j
+
o 0110
11 j j
0 62
o
AM
o 0000
101 1
AMC
where,
1~0-3
1
(A)-(M(DP», (y). (Y)--1
(X)~(X)VI.
where, 1=0-3
t
1
(A)-(M(DP». (Y)~(Y) 1-1
(X)·-(X) V 1 where, 1~0-3
j
LA n
)~0-3
1
j
XAMI j
where,
(A)-(M(DP»
(X)~(X)\f),
01 1 0
(Y)··15
(Y)=masked
skip
condition
where,
n~0-15
o Bn
1
1
(A)<-n.
0 OA
1
1
(A).-.(A)+(M(DP»
00000111000E
1
1
1010
Transfers the RAM contents addressed by the active DP to
register A Register X is then "exclusive OR-ed" with the value
j in the instruction, and the result stored in register X.
Exchanges the contents of the RAM and register A
Cnntents
of X are then "exclusive OR-ed" with the value j, and the result
stored in register X
Exchanges. the contents of the RAM and register A Contents of
X are then "exclusive OR-ed" WIth the value 1 In the instructIon,
and the result stored in regi~ter X. The contents of reqister Y
are decremented bv 1. and when the result is 15. the next instruc
tion is skipped.
Exchanges the contents of the RAM and register A. Contents of
X are then "exclusive OR -ed" with the value j in the instruction
and result stored in register X. The contents of register Yare
incremented by 1, and when the result meets with the marked
skip condition the next instruction is skipped
(A)~(M(DP»
(X)~(X)\f
6 j
Exchanges contents of register A with contents of register L.
Exchanges contents of register A with contents of register H
Wr:tten
successively
Loads the value n into register A. When LA is written conseu·
tively the first is executed, and successive ones are skipped.
Adds the contents of the RAM to register A. The result is reo
tained in register A, and thewntelll, of flag CY are unaffected.
c
o
.;::;
~
'-'
.;::;
AMCS
000001111
OOF
~
A n
01010
OAn
SC
RC
SZC
CMA
001001001 049
01001000048
0010111102F
o 1000 111 1 o BF
SB j
o 0100
~
~
(A)~(A)+(M(DP»)+(CY)
0/1
(CY ).- carry
1
(A)~(A)+(M(DP»
1
(A)'--(A)+n:where,
1
1
1
1
1
1
(CY)~1
1
1
(M) (DP»~1.
where, 1~O-3
1
1
(M,
(OP»~O,
where, ) ~O-3
1
(CY)~
SZB
j
0101
o 4C
-t
1 1 j j
o
0001000jj
o
o
RB j
11 j j
J
5~
j
2 j
0/1
,-(CY)
carry
n~O-15
A carry '~o
but n",6
(CY)~O
(A)~(A)
~d~~gth;yR~~e~~~~~n1s ;~~rr:~~I~ ~:s:~~e~c~~~e~i.t:~dAc~~~e;h~
carry in the active flag CV.
Adds the contents of the RAM and flag CY to register A. The
result is stored in register A and the carry in the CY, but the
next instruction is skipped when a carry is produced.
Adds value n in the instruction to register A. The COrotP.1I1S of
flag CY are unaffected and their next instruction is skipped if a
carry is not produced, except when n=6.
Sets active flag CY
Resets active flag CY
Skips next instruction when contents of the active flag CY are 0
Stores complement of register A in register A.
Set the jth bit of the RAM addressed by the active DP (the bit
designated by the value j in the instruction).
Resets the jth bit of the RAM addressed by the active DP (the
bit designated by the value j in the instruction)
Skips next instruction when the contents of the jth bit of the
RAM addressed by the active DP (the bit which is designated by
(M) (0 P»
~O
t--::;;-i-=-=::-:::--t-::--=-=--=--=--=-:-:--=-+-=-=-=-+-:-+-:-+_ _ _ _ _ _ _ _ _ _ _ _t-w;-:h-:-;er-=e,'::).,-;~,._o---3+_:+..,;tc:.:.he value y
i
SEAM
0
001 0
01 1 0
0 26
(M(DP)~:)
1
in the instruction) are O.
;:~p~;~X~oi~:;~~~~~~r~::; b~O~~:~~ti~! ~rter
A are equal to
SEY y
0 00 1 1 Y Y Y Y 0 3 Y 1
(Y) ~y where,
Skips next instruction when the contents of register Yare equal
t---'U'-t_ _ _r-_ _ _ _ _-+_ _+--+--+.,...-,_ _ _ _ _ _ _ _ _ _ _t--'-y~_0_-_1_5~-+_to-th-e-va_lu_e2.j in the instruction.
LC7
o 0101 0111 057
1
1 (C)~7
Loads 7 to registerC.
0000 1001
09
1 (C)~(C)-1
(C)'=7
Decr~ments Gontents of register C by 1, when result is 7, skips
DEC
SHL
0100 001 0
42
1 (H (Cl cOI)~1 when, (C2)~1
g~~st~~Jtbyn:,o~glster L or H designated by register C. The box
(L(cI col)~1 when, (G2)=0
instructiOn shows the relationship (C
7 6 5 4 3 2 1 0
c
o
betweenreglsterCand bit posItIon. I Bit IH'IH'IH, IHo IL'IL'IL' ILo
RHL
001010010052
1
1 (H(CI cOI)~O when, (C2) ~ 1
X
Resets the bit in register L or H that is des;"gnated by register C.
(LlC' COI)---O when, (C2)=0
§Reads all analog values from input port K for comparison with
00000 10000 OB
1
CPA
1 (J(il)~-1 when, iVrefl>IVK(,11
X
D·A converter output Vret. and either sets the respective bit of
$
(2) (Jlil)~O when, iVref'IV",)1
when,IVrefl-
Type of
~~~ic
instructlon
I------'I--B-X-Y-+-l-l x x x
~~~~ilon ~ ~
y y y y
Skip
conditio.ns
Functions
'0
08 07060504 03020,OG
u
.Description of operation
1 B-'--y'-+--l· +--+-(·p--C-cL)---16-X-+-y·-·-------+-----+-x+--~J-u-m-p-s-to-a-dC-Cdr-ess-xy---Cof'--th-e-c-ur-re-n-tp - a - g e - . - - - - - - - - l
(PCh)~·15. (PCL)' 16x+y
+
~to address xy on page 15 when executed, provided that
none of instructions RT, RTS, BL, BML or BMLA was executed
after execution of ',nstruction BM or BMA.
p p p p
y y y Y
0 7p
1 8y
+
x
0
0000 0001
0 01
1
1 x x x
XXXX
1 8X
+
x
BLA pxX, 0 0000 0001
0 01 1 1 P P P P
1 1 x x x XXXX
0 01
0 7p
BM xy
1 x y i 1
BL
pxy
BA
xX
0 0111
1 1 x x x
Cl.
~
2
2
Jumps to address xy of page p.
(PCH)~-p
(PCL)-16x+y
2
3
I
(PCL)··16x+(A)
Jumps to address xlAI of the current page.
(PCH)··-15. (PCL)-16x+ (A)
Jumps to the address x(AI of page 15 provided that none of
instructions. RT, RTS, BL. BML, BLA or BMLA was executed
after execution of instruction BM or BMA.
(PCH)'-P
(PCL)'16x+(A)
Jumps to the address xlA) of page·p.
a
I
~.~~~~~~----~~
o
1
!X
-
."'c"
I,,,,,,,
0
.D
BMA xX
1
x x x
y y y Y
0 011 1 P P P P
1 o x x x y y y y
0 7p
1 x y
0 0000 0001
1 o x x x XXXX
0 01
1 xX
2
(SK2)' (SK1).-(SKO).·(PC)
(PC·,)··14, (PCL)-16x + Y
Calis for the ,subroutine starting at address xX on page 14.
(PCH)' 14, (PCL)'-16x+y
Jumps to address xy of page 14 provided that none of instruc·
tions RT, RTS, BL, BML, BLA or BMLA was executed after the
execution of instructions BM or BMA.
2
(SK2)-(SK1)-(SKO)' (PC)
(PCH)-p, (PCL)·-16x+y
Calis for the su broutine starting at address xx of page P
2
(SK2)-(SKl).-(SKO)·-(PC)
~ (PCH)~-14, (PCL)-16x+ (A)
1
Calls for the subroutine starting at address xlAI of page 14.
:.n
(PCH)·-14. (PCL)·-16x + (A)
Jumps to address x (A) of page 14 provided that none of instructions RT, RTS, BL, BML, BLA or BMLA was executed after the
execution of instructions BM or BMA.
BMLA
pxX
Calls for the subroutine starting at address x(A) of page p.
RTI
E
~
j~
RT
Returns to the main routine from the subroutine, and unconditionally skips the next instruction
RTS
so
Sets the bit of port D that is designated by register Y, when the
contents of register Z are 1.
Resets the bit of port D that is designated by register Y, when the
contents of register Z are 1.
Skips the next instruction if the contents of the bit of port D that
is designated by register Yare 0 and the contents of register Z are
RO
SZO
:0
Cl.
1.
:0
o
Cl.
OSAB
OSPA
o
o
OSE
lAS i
000001011
00101 010i
0001
0001
101 1
01 1 1
0 1B
0 17
1
1
(S7-S,)-(8), (S3-So)-(A)
(S7- So),· through PLA-(A)
OOB
1
0541
1 (S)·-(E)
1,-:0:(A)'-(S7-S,)
1~1: (A)-(S3-S0)
Outputs contents of register A and B to port S.
Decodes contents of register A by PLA and the .result is output
to port.
Outputs contents of register E to port S.
Transfers from port S to register A. The high-order four bits of
port S are transferred when the value of i in the instruction is
or the low-order four bits are transferred when the value of i is 1.
Clears port D.
Clears port S
o
1
0 13
1 CD) ·-0
1
1 (S)-O
0 10
0 11
1--_~---+------------I------I---+-l-1--(-O~).--,--O-,-(-S-)---O-------------~--------+-~-C-le-ar-s~po-'--r-ts-S,--a-nd-D~.~--~~-------_---------CLO
CLS
CLOS
0
0
0
0001
0001
0001
EI
0
0
0000 0101
0000 0100
o
05
0 04
1
1
INTH
0
0000 0110
0 06
INTL
a
0000 0111
o
07
NOP
o
0000 0000
000
01
001 1
0000
0001
1
1
(INTE )~1
(INTE )'-0
Sets interrupt flag INTE to enable interrupts.
Resets interrupt flag INTE to disable interrupts.
1
1
(INTP)' 1
1
1
(INTP)' 0
Sets interrupt polarity flag INTP to enable interrupts when the
interrupt request signal is turned high.
Resets interrupt polarity flag INTP to enable interrupts when the
interrupt request signal is turned low.
1
1
(pC)~·(PC)+l
Cl.
'j
Mise
Symbol
Contents
OP
PCH
4-bit register (aacumulator)
4-bi t register
3-bit register
S-bit register
4-bit register
l5-bit register
4-bit register
2-bi t register
4-bit register
l-bit register
7-bit data pointer, combination of registers, Z, X and Y
The high-order four bits of the program counter.
PCl
PC
The low-order seven bits of the program counter.
11-bit program counter, combination of PCH and PCl.
Symbol
SKO
SKl
SK2
CY
yyyy
XXXX
No operation
Conten.ts
11-bit stack register
ll-bit stack register
ll-bit stack register
l-bit carry flag
2-bit binary variable
4-bit binary variable
l-bit binary variable
4-bit bi nary constant
l-bit binary constant
2-bit binary constant
4-bit unknown binary number
ll-bit port
l5-bit port
S-bit port
• MITSUBISHI
"ELECTRIC
Contents
Symbol
INTE
INTP
INT
Interrupt enable flag
I nterrupt polarity flag
I nterru pt request signal.
Shows direction of data flow.
I ndicates con tents of the register, memory, etc.
Exclusive
Negat',on.
xy
pxy
CPS
C
+
OR.
Indicates flag is unaffected by instruction execution.
Label used to indicate the address xxyyyy.
Label used to indicate the address xxyyyy of page pppp.
Indicates wh ich data pointer and carry are active.
Hexadecimal number C + binary number x.
4-9
MITSUBISHI MICROCOMPUTER
M58840-XXXP,M58841-XXXSP
SINGLE·CHIP 4·BIT MICROCOMPUTER
WITH 8·BIT AID CONVERTER
LIST OF INSTRUCTION CODES
~D4
00000
o 0001
1 0000 1 1000
0 001 0 0 0011
0 01 00 0 0101
00110
0 0111 0 1000
0 1001
0 1010 0 1011
0 1100 0 1101
0 1110 0 1111
\
\
1 0111 1 1111
no~~e-x-ad~e~c~im~aTI-+-----r----+-----r---~~---+-----r----~----+-----r---~-----r----~----+_----~---;----_+----1
03 ~o\tation 0 0
o
o
1
2
SZB
0000
0
NOP
3
SEY
o
4
LCPS
CLS
BA
~~:
0001
o
SZB
SEY
LCPS
1
1
1
CLDS
BMLA
o
o
5
o
6
CPAS
o
o
8
9
OA
OB
OC
00
OE
OF
BL
A
LA
LXY
LXY
LXY
LXY
BML
o
o
0,0
1,0
2,0
3,0
XAM
BL
A
LA
LXY
LXY
LXY
LXY
1
8ML
1
1
0,1
1,1
2,1
3,1
XAM
CPAE
7
10-17 18-1 F
BM
B
BM
B
-------T-;----_+-----r----+-----r_--~----_r----~----r_--~-----_T----_+-----~---~----_+----~----~----+_--~
0010
2
SZB
INY
SEY
XAM
SHL
BL
A
LA
LXY
LXY
LXY
LXY
BML
2
2
0,2
1,2
2,2
3,2
RHL
BM
B
~---~--+_--~r-----r---------_+----~-------+_----~--~----_r----~----+------~--_+----_+----~----+_----+-------
0011
3
0100
4
DEY
SZB
CLD
XAM
SEY
SEY
01
RD
RT
lAS
TAM
4
-------
~---~---+_--~-----+----_r----~-----------
0101
EI
SEY
SO
RTS
lAS
BL
A
LA
LXY
LXY
LXY
LXY
BML
3
3
0,3
1,3
2,3
3,3
BL
A
LA
LXY
LXY
LXY
LXY
BML
4
4
0,4
1,4
2,4
3,4
BM
B
BM
B
-----4-----+----+------r----;_----+-----~---1----_r----_r-----
['TAM
BL
-
-
A
LA
LXY
LXY
LXY
LXY
BM
B
BM
B
BM
B
BM
B
BM
B
BM
B
BM
B
BM
B
BM
B
~--~--+---~L-----+-----r-S-:_-Y-+-----+--~-- ;~M B~-L~----~_---~-A-5---~-:--A~--~-:-Y-+-L-1X-,:--~~-~-:-+-L-3-:-Y-+----~--~
I
0110
6
INTH
TEPA SEAM
RTI
6
0111
INTL
SEY
OSPA
-
I
-
LC7
2
CPA
SEY
XAL
8
RC
XAH
SEY
1001
9
DEC
TLA
SZJ
SC
THA
BL
3
BML
A
B
1011
1100
C
1101
0
AM
OSE
TYA
TAJ
TEAB
OSAB
SZD
TBA
TAY
6
6
0,6
1,6
2,6
3,6
A
LA
LXY
LXY
LXY
7
7
9,7
1,7
2,7
I -
A
LA
LXY
LXY
.LXY
LXY
8
8
0,8
1,8
2,8
3,8
BL
A
LA
LXY
LXY
LXY
LXY
BML
9
9
0,9
1,9
2,9
3,9
BL
o
BML
XAMDI
-~--t-I
XAMD
9
1010
BML
TAM
7
1000
I
-
LXY
I 3,7
SEY
LZ
XAMD
BL
A
LA
LXY
LXY
10
o
2
BML
10
10
0,10
1,10
LXY
LXY I
2,10
3,10
SEY
LZ
11
1
SEY
SB
12
o
SEY
SB
RB
XAMI
13
1
1
1
XA~BL
A
LA
LXY
LXY
LXY
LXY
11
11
0,11
1,11
2,11
3,11
BL
A
LA
LXY
LXY
LXY
LXY
BML
12
12
0,12
1,12
2,12
3,12
BL
A
LA
LXY
LXY
LXY I LXY
BML
13
13
0,13
1,13
2,13
BML
RB
XAMI
I
3,13
t- _
r-l-l-ll~-F-+A-M--C-S~------+-S-Z-c~--S-:-Y~--S-:--+--:-B~X-A-2M--I+-B-BM-L-L~-C-:--A I ~ +--~-4--~L-l:--;--~-~-:-+-~-~-1:~--~-~-:-+-~-'-~-:-r-B-M--~--B~
SEY
1110
E
AMe
TAB
SB
RB
XAMI
BL
\
_
A
LA
LXY
LXY
3
3
3
BML
15
Note 1. The list shows the machine codes and corresponding machine instructions. D3-DO
indicate the low-order 4 bits of the machine code and 08-D4 indicate the high-order
5 bits. The hexadecimal values are also shown that represent these codes. An instruction
may consist of 1,2, or 3 words, but only the first word is listed. Codes indicated
with bar (-) must not be used.
Note 3.
15
0,15
1,15
Second word
o
Three-Word I nstruc1ions
«
CD
--
BL
1 lxxx
YYY
BML
1 Oxxx
YYYY
BA
1 lxxx XXXX
BMA
1 Oxxx XXXX
cri
Second word
I BLA
I BMLA
Third word
0 0111
PPPP
1 1 xxx XXXX
0 0111
PPPP
1 Oxxx XXXX
• MITSUBISHI
.... ELECTRIC
3,15
Page (total of 16 pages)
Address' 0
2
3
Two-Word Instructions
2,15
B
Relationships of Branching and Paging for Branching, and SubRoutine Call Instructions
I
4--10
LXY
BM
15
Note 2.
LXY
--
125
!?6
127
MITSUBISHI MICROCOMPUTER
M58840-XXXP,M58841-XXXSP
SINGLE-CHIP 4-BIT MICROCOMPUTER
WITH 8-BIT AID CONVERTER
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
VOO
Supply voltage
VI
Input voltage, port Sand D inputs
VI
Input voltage, inputs other than port Sand 0
Limits
Conditions
0
-I
I
Vo
Output volt3ge, port Sand D outputs
Vo
Output voltage, outputs other than port Sand D
Pd
Power dis,ipation
With respect to Vss
.3-~
Unit
- 20
V
0.3- -35
V
0 .3- -20
V
0.3- -35
V
0.3- -20
V
1100
mW
Ta=25°C
Topr
Operating temperature
-10-70
°C
Tstg
Storage temperature
-40- 125
°C
RECOMMENDED OPERATING CONDITIONS
Limits
Symbol
Unit
Parameter
Min
VOO
Supply voltage
VSS
Supply voltage
VIH
High·level input voltage
VIH(¢)
High·level clock input voltage
-1.5
VIL
Low-level i~put voltage, inputs other than port D and S
VOO
VIL
Low·level input voltage, port 0 and S inputs
VIL(¢)
Low·level clock Input voltage
VI (K)
Analogrnput voltage, port Krnput
VREF
VREF
Reference voltage
-5
VOL
Low·level output vollage, port 8 and S outputs
f (¢)
Internal clock oscillation frequency
-13.5
Max
Typ
-15
V
-16
V
0
~~-
II
C
(T a=-10-70 C, unless otherwise noted)
1
.5
V
V
-4.2
V
-33
-4.2
V
VOO
Voo 12
V
o
V
-7
V
600
kHz
-33
V
f-
Note 1
300
VI L ( IV
temperature and other senslr,g devices
properly selected
In/out
Corresponding bits of register J are set when the condition,
K( Y) lis met. This port IS utilized for receiving Input signals from the touch panel or receiving analog inputs from
It can also be used as a value threshold dlg;tal signal input port when the V re f is
The I/O port S can be used as either an 8-bit output port or a pair of 4-bit Input ports Since it has open-drain circuits, It is suitable
for directly driving segments of a large fluorescent display tube, It has an 8-bit output latch and can perform to drive 8 bits
simultaneously. When the output of port S is programmed to low-level. It remains In the floating (high-Impedance) state so that
It can be used as an Input port
~-----+---------------~----~----------------------------------------------------------------------------~
Do
I
010
The I/O port 0 IS composed of 11 bits that can be used as discrete I/O units
I/O
POri D
In/out
Latches are provided on the output side to
maintain individual output signals. When port D ;)utput is programmed to low-level. to keep it in floating (high-impedance) state,
It can be used as a sense Input port. The level of the Input signal is sensed at the input terminal and IS tested to determine if it
IS high or low by executing a skip instruction
Ao
I
AlO
10
I
18
Out
The address output is composed of 11 bits that output the contents of the program counter PC to the externa, program memory
(ROM)
ROM
data Input
In
The data Input IS composed of 9 bits that are used to fetch the Instruction code for the CPU from the external program memory
(ROM)
Clock
In
ROM
address output
As the clock generator IS contained internally, clock frequency is determined by connecting an external CR circuit or an IF ceramic
Input
XOUT
Clock
output
resonator between the pins X1N and XOUT, In case an external clock source is to be used, it should be connected to the pin
XIN, leaving the pin XOUT open
Out
This pin generates the clock frequency from the Internal clock oscillation Circuit
This signal is used for requesting interrupts
Interrupt
INT
request
In
Input
Whether high or low-level Interrupt signals are In used for requests IS selected by
When the instruction INTH IS executed, Interrupt is accepted With a high-level signal. and accepted With a
low-level signal when the instruction INTL IS executed. When an interrupt IS requested and accepted, program execution is jumped
The instruction RTI IS used for the return Ir,structlon
A reference voltage Input IS applied to the D-A converter from the external terminal
Its nominal value is VREI;'
= -7V.
The
value (n-O. 5) VREF /256 IS generated by the D-A converter, and IS compared With the analog signals from the input port K; where
In
voltage
n represents the contents of the register H-L, but when n
automatic reset signal Input
Input
CNVoo
means of the program
to address 0 of page 12
External
reference
The oscillation frequency is controlled by
connecting the CR CirCUit or IF ceramic resonator between thi~ pin and the pin X 1N ,
= 0,
the output voltage IS treated as Ov.
It can also be used as an,
When a high-level is applied to the VREF input, it actuates the automatic reset circuit. and then
the VREF input is changed to low-level ready to start the. program from address 0 of page 0
Timing output
Out
CNVDO Input
In
This pin generates a part of the baSIC timing pulse
This signal is used for testing other devices incorporated in the system
ThiS input terminal should be conected With the VOD and have a low-level Input (-15V) applied
• MITSUBISHI
"'ELECTRIC
4-15
II
•
MITSUBISHI MICROCOMPUTERS
M588425
MELPS 4 SYSTEM EVALUATION DEVICE
BASIC TIMING CHART
~"h,"'''''',"
State
---------s~
Signal name
I s~~
Clock input
XIN
Clock output
XOUT
Timing output
TIt
Port D outputs
Do -010
Port D inputs
00-010
Port S outputs
So -S7
Port S inputs
So -S7
Port K Inputs
Ko -K 14
T2
T3
T4
Ts
T6
r--L-r---L- ~ ~ ~ r-c=
~~~ ~~~
L-J
(Output)
(Input)
'X)()()()\XXXXXXX
lXXXXXXXX
(Output)
(Input)
Interrupt request Input
INT
ROM address outputs
Ao-A1O
ROM data inputs
Note 1
MI
Tl
10 --Is
XXX lXXXXXXXX
XXXXXXXX [)(X)O(X)(X)< lXXXXXXX)< XXXXXXXX
XXXXXXXX
XlXXXXXXX
XXXXXXXX XXXXXXXX lXXXXXXXX
lXXXXX~'O XXXXX)\)(X XXXXXXXX lXXXXXXXX
xx XXX XXXIXXXAXX)\)less otherwise noted)
Limits
Parameter
Symbol
Test conditions
Unit
Typ
I--V~IH~~-+__
H--=-,g_h-Ievel Input voltage. port 0 and S Inputs
Max
-1,5
V
V IH
High-level Input voltage. ROM data Inputs
-1.5
V IL
Low-level Input voltage, port D and-S Inputs
-33
-4,2
V
V IL
Low-level input voltage, ROM data Inputs
VDO
-4,2
V
V OH
VOO=-15V, IOH=-15mA, Ta=25°e
High-level output voltage. port 0 outputs
- - -_.
__.._--
V
-2,5
--~--~+-~~-
V
---r-~~--r~~~r-~~~~
VOH
High-level output voltage. port S outputs
Voo=-15V, IOH=-8mA, Ta=25°e
-2,5
VOH
High-level output voltage. ROM address outputs
VOO= -15V, IOH= -2mA, Ta=25°e
-2
V
V
--
To be measured when the instruction CPAS or
Input current, port K Inputs
CPA is not being executed.
1--_11_(_1>_)~-+~CI_OCk Input current
V I = - 7V
~~__~~~+-VI (1))= -15V, Ta=25°e
-20
-7
I-/A
-40
I-/A
IOH
-15
mA
High-level output current_,_po_r_t_0_o_ut_p_u_t_s~~~~~-t-_V~0_D_=_-_-_1_5_V_,_V_O_H_=~-_2_-_5_V_,_T_a_~_-_2_5_oe-t-~~-----1I-~~-+-~~~t_~~~-I
IOH
High-level output current, port S outputs
VOO= -15 V, VOH= -2 _5V, Ta =25°C
IOL
Low-level output current ports D and S outputs
VOL =
------
-8
mA
-~~~~+-~~-+~~~4-~~~~
-
33 V, T a = 25 °e
-33
I-/A
VOL = - nv, Ta = 25°e
-17
I-/A
10
pF
10
pF
±3
LSB
I--~~~-+~~~~~~~~~~~~~~~~~~~~~--
IOL
Low-level output current, ROM address outputs
VOO=VI=VO=VSS, f=lMHz
C,
Input capacitance. port K inputs
C , (1))
Clock Input capacitance
25mVrms
VDO= XOUT=VSS, f= 1 MHz
25mVrms
-----
V REF =
A-D converSion linearity error
-- 7 V
REF = - 7 V
--~_+~~~~~~~~~~~~~~~~~~_t_~-
A-D converSion zero error
V
A-O converSion full-scale error
V REF= -7V
------~~~~~--~----~~-~-----~--~~t_~~~~~~~~~~--------
Note 2
Total
±2
Current flowing into an IC is positive; out is negative_
3: The sum of high-level output current from port 0 must be 75mA (max).
APPLICATION EXAMPLE
------------------------------------(OV)Vss
7V
( -- t5V) Voo
Vss(OV)
7V
t5V •
RESET SIGNAL/
REFERENCE
VOLTAGE
CVREFH
SV REGULATOR
10V
10 v REGULATOR
5\1
CVREF
CINTH
INTERRUPT
REOUEST
SIGNAL
INT
A,O
EMULATOR
CHIP
M58842S
VREF
CARD EDGE
CONNECTOR
PORT S CPS7H
djJ-r~mCP~OH
S7 So
a:
RESET SIGNAL/
l!J
56t~f~~CE
'"~
'CINTH
INTERRUPT
REOUEST SIGNAL
I
CCSH
MEMORY
CONTROL SIGNAL
c?
u
2
l?
~
ADDRESS BUS
l!J
I
Ag Ao
f--
a:
ADDRESS BUS
2
PORT 0 CPD 10H '
dYr~Jt cpd 0 H
PORT K CP~ 14H
INPUT CPK 0 H
P~RpU ~:~::
TOUCH PANEL
(PCA0402)
CONNECTOR
PORT D CPD2H
OUTPUT CP60H
(
( (0
15V) Voo
120V)VAA
(0
- 120V)VAA
a:
010 - Do
K14
0
9z
Ko
z
0
u
DATA. BUS INPUT
8
8
3
Is -10 r-~~~L--~~~~~~~~~-----.'-----'~
XOUl
'
X,N
c
, COB8L
DATA BUS
\
CDBOL OUTPUT
J
;r"
------------
• MITSUBISHI
.... ELECTRIC
--~~~---------
4 - 17
a
MITSUBISHI MICROCOMPUTERS
M58843-XXXP,M58844-XXXSP
SINGLE-CHIP 4-BIT MICROCOMPUTER
WITH 8-BIT AID CONVERTER
DESCRIPTION
PIN CONFIGURATIONS (TOP VIEW)
The M58843-XXXP and M58844-XXXSP are single-chip
4-bit microcomputers fabricated using p-channel aluminum
gate ED-MaS technology. They include an on-chip 8-bit
RESET INPUT RESET _
1
.... D2
A-D converter. The M58843-XXXP is housed in a 28-pin
REFERENCE
2
-Dl
plastic moulded DIL package while the M58844-XXXSP is
housed in a 40-pin shrink plastic molded DI L package.
VRE F _
vOL~;T~:elUT :
},euT/OUTeUT
PORT D
.... Do
: :
,
....S7
-S6
FEATURES
•
•
PORT D
::::..
~
D6
Basic machine instructions .................... 67
Basic instruction execution time
(for single-word instructions using
a 600kHz clock frequency) ................. 10/1s
•
Memory capacity
ROM
RAM
•
Single -15V power supply
........ 1024 words x 9 bits
.......... 64 words x 4 bits
•
Built-in 8-bit A-D converter
•
Two built-in data pointers
•
•
Subroutine nesting ...................... 3 levels
Analog/digital inputs (port K)
.... Ss
00
t;
07
INTERRUPT
REQUEST
INPUT
_S.
INPUT/OUTPUT
PORT S
I
AN~~~~( (~
P~~TU~
K2
K3
X
X
_
.....
10
~
.... S2
L1
12
(OV)CNVss"'"
13
(OV)Vss
14
CLOCK INPUT
16
-XOUT
CLOCK OUTPUT
VDD(-15V)
Outline 28P4
M58843-XXXP ....................... 4 lines
M58844-XXXSP ..................... 11 lines
•
Input/output (ports D and S)
M58843-XXXP ...................... 16 lines
M58844-XXXSP ..................... 19 lines
•
Capable of driving large fluorescent tube displays
•
Interrupt function
•
Built-in port S output decoder PLA (mask option)
•
Built-in pull-down transistors (ports D, K, and S, mask
option)
•
ANALOG/
DIGITAL
{ K.
INPUT PORT K K9
RESET INPUT
-
ANALOG/DIGITAL
INPur PORT K
1
_2
RESET ..... 3
]
REFERENCE
VOLTAGE INPUT
................ 1 factor, 1 level
D3
',"UTI
OUTPUT
PORT D
I
D.
Ds
INPUT /OUTPUT
PORT S
_7
D6
D7
Built-in clock generator circuit
INPUT /OUTPUT
PORT D
INTERRUPT
REQUEST
INPUT
APPLICATIONS
32 _DlO]
31 _
D9
iNPUT/OUTPUT
PORT D
30 _D8
Ks
KlO
•
Electronic ranges, air conditioners, heaters, washing
machines, rice cookers
•
Office equipment, copying machines
ANALOG/
DIGITAL
INPUT
PORT K
KG
Ko
Kl
K2
CLOCK INPUT
K3
CLOCK OUTPUT
VDD( -15 V)
(OV)CNVss _
PULL DOWN
VOLTAGE iNPUT
ANALOG/DIGITAL
INPUT PORT K
19
(OV)Vss
Outline 40P4B
4
18
• MITSUBISHI
.... ELECTRIC
MITSUBISHI MICROCOMPUTERS
MS8843-XXXP,MS8844-XXXSP
SINGLE-CHIP 4-BIT MICROCOMPUTER
WITH 8-BIT AID CONVERTER
BLOCK DIAGRAMS
M58843-XXXP ~NE~~:~r
RESET INPUT
rrRESET
INPUT (OV)
INT
(-15V) (OV)
CLOCK
INPUT
CLOCK
OUTPUT
X'N
CNVss
RAM
64 WORDS
X4 BITS
I
I
II
1
!
I
I
I
I
,
J
Vre!
5, S6 Ss S4 S3 S2 5, So
K3
~
INPUT/OUTPUT PORT S
COY)
INPUT
INT
COy)
CNVss
Ko
K,
VREF
~
ANALOG/DIGITAL INPUT PORT K
M58844-XXXSP ~ETg~~~;T
CNVss
K2
(-15V) COV)
Voo
Vss
CLOCK
INPUT
XIN
REFERENCE
VOLTAGE INPUT
0, 06 Ds 04 03 02 0, Do
'-v-'
INPUT/OUTPUT PORT D
CLOCK
OUTPUT
XOUT
~---------------------------------
RESETri INRUT
RESET
3
I
CONTROL
SIGNAL
~..----L-----r--~~--',-----rI-------.-----,---
I
11
I
i
3231398765398)
INPUT/OUTPUT PORT S
2
0,1 D9 08 D7 Db Os 0.01 03 02 0, Do Vp
51 56 55 54 53 52 5, So
'---v-ANALOG/DIGITAL INPUT PORT K
•
REFERENCE
VOLTAGE iNPUT
'----v-'PULL-DOWN
INPUT/OUTPUT PORT D VOLTAGE
INPUT
1
MITSUBISHI
"ELECTRIC
4 -19
MITSUBISHI MICROCOMPUTERS
M58843-XXXP,M58844-XXXSP
SINGLE·CHIP 4·BIT MICROCOMPUTER
WITH 8·BIT AID CONVERTER
PERFORMANCE SPECIFICATIONS
Parameter
PIN DESCRIPTIONS
Pin
Name
I nput or output
Function
~---.~--------------+---------+--------------------------------------------------------------------------------
Voo tpower supplies
Vss
In
Voo and Vss are applied as -15V ±1 0% and OV respectively
c----Ko-K3
(M 58843
-XXXp)
Ko-KlO
Analog/digital
In
inputportK
The input port K consists of 4 (11 for the M58844-XXXP) independent analog input pins.
They can be programmed to receive digital quantities as well
~~X5:~t4)
The I/O port S can be Llsed as either an 8-bit output port or a pair of 4-bit input ports.
I nput/output port S
In/out
Input/output port 0
In/o~t
Since it has open drain circuits, it is suitable for directly driving segments of a large fluorescent display tube.
When the outnut nort S is rrogramrned to a low level, it remains in the floating state (high-impedance) so
that it can be used as an input port.
00 - 0,
(M 58843
-XXXP)
0 0 - 010
(M 58844
Port 0 consists of 8 bits for the M58843-XXXP and 11 bits for the M58844-XXXSP, all bits operating individually
for input and
outP~'i functions.
When a port 0 output is programmed to low, the output floats (goes to high,
impedance state) and the input signal can be sensed.
-XXXSP)
A clock generator is built into the device so that t'1e clock frequency is determined by connecting an external RC
XIN
Clock input
In
circuit or ceramic resonator between pins XIN and XOUT. When an external clock source is used, it should be
connected to the XIN pin, leaving the X OUT pin open.
XOUT
Out
This pin is the output of the built·in clock generator circuit. The oscillation frequency is controlled by
connecting an RC circuit or ceramic resonator element between this pin and the XIN pin.
INT
Interrupt request input
In
This pic is used to IIlput the interrupt request Signal. The level of the IIlterrupt Sl9nal can be prograillmed as either high or low
VREF
Reference voltage input
In
This is the input for the reference voltage applied to the D-A converter.
CNVss
CNV ss input
In
This input is connected to VSS and must have a high-level input applied to it (OV)
RESET
Reset input
Ie
When this input IS kept high for at least two machine cycles, the reset state is enabled.
Pull-down
voltage input
In
This pin is used to supply the pull-down voltage for port 0 outputs and port S outputs.
Vp
(M58844
XXXSP onlyl
4
Clock output
20
• MITSUBISHI
.... ELECTRIC
MITSUBISHI MICROCOMPUTERS
MS8843·XXXP ,MS8844.XXXSP
SINGLE-CHIP 4-BIT MICROCOMPUTER
WITH 8-BIT AID CONVERTER
BASIC FUNCTION BLOCKS
Program Memory (ROM)
long as the address is not changed this is not necessary.
This 1024-word x 9-bit mask programmable ROM can be
programmed with machine ~nstruction codes in accordance
with the customer's specifications. It consists of a pages,
each containing an address range of 0 '"""' 127. Fig. 1 shows
the address map of this ROM.
Data Pointers (DP, DP')
These registers are used to designate RAM address, and bit
position for the I/O port D and register J. Each data pointer
is composed of a 6-bit register group. Register X (the
upper order 2 bits of DP) designates a RAM file; and register Y ( the lower order 4 bits of DP ) designates the digit
J'g
Program Counter (PC)
position of the RAM file. At the same time, register Y
This counter is used to specify ROM addresses and the
sequence of read-out of instructions stored in ROM. The
program counter (PC) is an 10-bit binary counter, the upper
order 3 bits of which (PC H ) indicate the ROM page, and
the lower order 7 bits of which (PC l ) are a pure binary
address designation. Each time an instruction is executed,
PCl is incremented by one step. For branching, and
subroutine call instructions, its value is set to the designated
address.
When the 127th address is reached for every page, the
address value returns to the first address of that page.
Therefore, for moving from one page to another page, the
page byte itself must be modified. This is done using the BL
and BLA instructions.
Page 14 and page 15 are special pages used for
subroutine calls. The page 14 subroutine can be called with
a one word instruction from any arbitrary page. This
instruction is either BM or BMA. When either BM or BMA
is executed, subsequent BM or BMA instructions are
equivalent to Band BA on page 14. Also, B or BA is
equivalent to B or BA on page 15. This condition is
cancelled when the RT, RTS, BL, BML, BLA or BMLA
instruction is executed. Note 3 under the instruction codes
shows corresponding states.
designates bit positions of the I/O port D and register
Stack Registers (SKo , SK 1 , SK 2 )
These registers are used to temporarily store the contents of
the PC while executing subroutines or interrupt prrgrams
until the program returns to its original routine. The SK
registers are organized in three words of 10 bits each,
enabling up to three levels of subroutine nesting. If one
word is used for an interrupt routine, the remaining two
levels can be used for subroutine calls.
Data Memory (RAM)
4-bit Arithmetic Logic Unit (ALU)
This unit executes 4-bit arithmetic and logical operations
by means of a 4-bit adder and related logic circuitry. The
arithmetic logic unit performs addition, logical comparisons,
arithmetic comparisons, and bit manipulation.
Register A and Carry flag (CY)
Register A is a 4-bit accumulator that constitutes the basis
for arithmetic operations. Data processing operations such
as arithmetic and logical operations, data transfer, exchange, conversion and data input/output are executed by
means of this register. Carry or borrow from register is
stored in the carry flag's CY and CY' after execution of
arithmetic or logical operations. The carry flags CY and CY'
can also be used as 1-bit flags. Carry flags and data pointer
DP selection is done by means of the selector CPS.
Registers Band E
Register B is composed of 4 bits and can be used as a 4-bit
temporary storage register or for a-bit data transfer in
conjunction with register A. Register E is composed of a
bits and is used not only as an a-bit temporary storage
register, but also as a temporary storage register for I/O
port S.
~~\,(i,';,.,g-
8 7 6 5 4 3 2 1
a
8 7 6 5 4 3 2 1
a
8 7
2 1
a
8 7 6 5 4 3 2 1
a
O~~~+4~~+44-~++44~~+4~~+44-~++~
~i~-r~~~LL~~LL~~~~~~~~~~~~i
~~~126~""~"~'-rrTo,,-,r,,,~r+,,'-r,,,~
127
Note
This 256-bit (64 words x 4 bits) RAM is used to store both
processing and control data. One RAM word consists of 4
bits with bit manipulation possible over the entire storage
area. The 64 words are arranged as 4 files x 16 digits x 4
bits. Fig. 2 shows the RAM address map.
Fig. 1
The RAM address specification is made by the combination of data pointer DP register X, and register Y. Thus, the
selector CPS and data pointer DP must be set. However, as
The M58843-XXXP and 1v158844-XXXSP programs are developed using
a support system having a 2048 word x 9-bit ROM memory. When
using such a system pages 8 through 15 of the 2048 words (pages 0
through 15) are used so that the program counter PCH~ 0-7 is defined
as pages 8 through 15.
ROM Address map
• MITSUBISHI
;"ELECTRIC
4-21
MITSUBISHI MICROCOMPUTERS
M58843-XXXP,M58844-XXXSP
SINGLE-CHIP 4-BIT MICROCOMPUTER
WITH 8-BIT AID CONVERTER
In the above relationships n is the value weighted
according to the contents of registers Hand L.
File name
Fo
F1
F2
F,
3210321032103210
Bit designation
Digit
desig nation
(register V)
1------=--+-.J...-.J...-.J...--I-.L-+-1-t-L-..;~L-.J---'~----1___l
1---..-:....-+--,--.;.--.---I--.--.;.-,--t-r--i--,------jc---1--;c---1___l
14
I
15
I
I
Fig.2 RAM Address map
AID Conversion Circu it
The following AID conversion functions are controlled by
software as described below. Fig. 3 shows the block
diagram.
(1) Comparators
These comparators are implemented entirely with
PMOS devices and use a chopper-type amplification
method. They are capable of determining the larger of
the D-A converter output Vref and the port K input
signals VK(V) (where(Y) = 0 '" 10).
(2) Register J
Register J is composed of 11 1-bit registers, each
representing the comparison result from the comparators. All register bits are set simultaneously. The value
of the register J with respect to the comparison results
is as follows.
1 when IVrefl > IVI< (V) I
when IVrefl < IVI< (V) I
In this relationship (Y) represents the bit position in
register J which is designated by register Y. The
comparison results can be checked for each bit using
the SZJ instruction.
(3) Registers H - L
These two 4-bit registers are capable of transferring and
exchanging data to and from register A.
The a-bit digital data for the D-A converter is
transferred from these registers, the higher order 4 bits
from H and lower order 4 bits from L.
(4) Register C
This 3-bit register is used as a counter to designate bit
positions in the Hand L registers.
(5) D-A Converter
The D-A converter converts the digital values stored in
the registers Hand L, referencing with the external
reference voltage VREF applied at the pin VREF , to
the analog value of the internal reference voltage Vref.
The theoretical value of the internal reference
voltage Vref is defined as follows.
n-0.5
.
Vref = 256 XV REF , where, n = 1,2, ......... 255
A-D Conversion Algorithms
A-D conversion is controlled by the programming of the
previously described functional blocks. Thus, by modifying
the program, either the successive approximation method
or the sequential comparison method may be selected. In
addition, a digital input of high or low level may be used to
select the method, eliminating software selection of the
A-D conversion technique.
(1) Successive Approximation
In this method, the conversion speed is maintained
constant regardless of the amplitude of the analog
signal. The A-D conversion process requires 0.6ms (at
600KHz clock frequency). 12 programs words are
required.
(2) Sequential Comparison
In this method the conversion speed varies in accordance with the rate of change of the analog quantity.
When the rate of change is slow, the conversion rate
increases. 30 program words are required.
o
Vref
4-22
=0
, where, n
K,O Kg
1(,
ANALOG INPUTS
Ko
VREF
EXTERNAL REFERENCE
VOLTAGE INPUT
Fig. 3 A-O Conversion circuit block diagram
=0
• MITSUBISHI
"'ELECTRIC
MITSUBISHI MICROCOMPUTERS
M58843-XXXP,M58844-XXXSP
SINGLE·CHIP 4·BIT MICROCOMPUTER
WITH 8·BIT AID CONVERTER
Interrupt
The flag INTE is a 1-bit flip-flop used to control interrupt
operation. When an interrupt request signal is applied to the
pin INT while the interrupt is enabled, the INTE flag is
reset to disable further interrupts, after which the program
jumps from the main program to address 0 of page 12.
When an interrupt program is used, one level of the
three-level stack register is required, the remaining two
levels being used for subroutines. After the interrupt
program is started, the data pointer DP, register A, carry
flag CY, and registers used by the interrupt program are
saved. It is necessary to restore these before returning to
the main program by using the instruction RTI.
When an interrupt occurs, the microcomputer internal
states are as follows.
(1) Program Counter
The current address in the main program is stored in a
stack register and the program counter is set to page
12, address O.
(2) Interrupt Flag INTE
The flag INTE is reset to disable further interrupts.
This disable state will continue even after the program
has returned from the interrupt routine to the main
program by the execution of the RTI instruction. EI is
executed and when the input level of the INT input
changes, this state is disabled. Thus, when the INTH
instruction is executed the interrupt state is enabled
when the I NT input goes high. As long as it remains in
the high state, further interrupts are prohibited. If the
INT input should change to a low level and return to
high, the next interrupt will be accepted.
(3) Skip Flags
Skip flags are provided to discriminate skip instructions
and consecutively described skip instructions. Each flag
has its own stack within which the skip state is saved.
As a mask option, the interrupt pins may be
provided with Schmitt input circuits.
Input/Output Pins
(1) Input port K
The input port K consists of 4 bits ·for the
M58843-XXXP and 11 bits for the M58844-XXXSP.
The voltage level input at these pins is compared with
the D-A converter voltage output Vref by a comparator
and the results stored in register J. As a mask option, it
is possible to build load resistors into the input port K.
These are implemented using depletion-type MOS
transistors. In add ition, to enable the use of capacitive
touch-type keys, it is possible to provide these inputs
with the required discharge transistors.
(2) Input/Output Port S
The input/output port S consists of 8 bits, each bit
•
with an output latch. These latches are used to store
data transferred by means of a PLA from register A, or
data transferred from register A and register B directly,
or data transferred from register E directly. 4 bits at a
time of the 8 input bits of port S may be transferred to
register A.
Because port S outputs are provided with a built-in
PLA, it is possible to output any arbitrarily settable
8-bit code from an input specified by register A. These
PL~ output codes can be specified arbitrarily as a mask
option.
In addition, as a mask option, it is possible to
build-in load resistors at the input/output port S. The
load resistors are implemented with depletion-type
MOS transistors.
(3) Input/Output Port D
The input/output port D consists of 8 bits for the
M58843-XXXP and 11 bits for the M58844-XXXSP.
Each bit can be individually designated as either input
or output and is provided with its own latch. The
contents of the data pointer register Y can be used to
designate a single bit of port D for output or sensing.
In addition, as a mask option load resistors may be
built-in at the input/output port D. These resistors are
implemented by means of depletion-type MOS transistors.
When port S or port D is used as an input port, the
output should first be cleared to the low state.
Reset Function
When the RESET input is kept high for at least two
machine cycles, the reset state is enabled. As shown in Fig.
4, it is possible to implement a power-on reset circuit using
an externally connected capacitor, resistor and diode. For
this configuration, when the supply voltage falls below
-13.5V, the circuit design should insure that the RESET
input is above -4V.
When the reset state is enabled, the following operations
are performed.
(1) The program counter is set to page 8, address 0
(PC) +- 0
Note 1· The M58843-XXXP and M58844-XXXSP programs are developed using
a support system having a 2048 word x 9-bit ROM memory. When
using such a system pages 8 through 15 of the 2048 words (pages 0
through 15) are used so that the program counter PCH= 0 -7 is defined
as pages 8 through 15.
(2) The interrupt mode is in the interrup.t disabled state
(INTEl +- 0
This is the same state as when the instruction 01 is executed.
(3) By setting the interrupt request signal INT to high, the
interrupt enabled state is entered. This is the same state
MITSUBISHI
. . . . II!'LII!'CTRIC
A_?'2
II
~
MITSUBISHI MICROCOMPUTERS
MS8843.XXXP,MS8844.XXXSP
SINGLE-CHIP 4-BIT MICROCOMPUTER
WITH 8-BIT AID CONVERTER
as when the instruction INTH is executed.
(4) All outputs of port S are cleared to low
(S) +- 0
(5) All outputs of port D are cleared to low
(D) +- 0
(6) The carry and data pointer selector CPS is cleared to
low to designate DP and CY
(CPS) +- 0
V" ov*,PUED
IM58844-xxxspl
I RESET
Vaa
~
\
I
[23
.L
RESET
OV
- 4 V
f
Clock Generator Circuit
A clock generator circuit has been built-in, to allow control
of the frequency by means of an externally connected RC
circuit or ceramic resonator. In addition, an external clock
signal may be applied at the XI N pin, leaving the X OUT pin
open. Circuit examples are shown in Fig. 5 to Fig. 7.
Note 2: Since when using an RC circuit
the frequency will vary in
accordance with the device
characteristics. the constants
should be chosen so that the
frequency falls within a specified
limit even including the
effect of these variations.
I
The following mask options are available, specifiable at the
time of initial ordering.
(1) S output PLA data
(2) Interrupt input Schmitt circuit
(3) Port Kinput pull-down resistors
(4) Port K input discharge transistors
(5) Port S input/output pull-down resistors
(6) Port D input/output pull-down resistors
DOCUMENTATION REQUIRED UPON
ORDERING
Fig. 4 Power-on reset
M58844- xxxspi
X'N
XOlJT I
25[ ••• [24
47 pF rvv~ 18 Q
MASK OPTIONS
Fig. 5 External RC circuit
Note 3: The circuit constants will depend
on the frequency and type of
ceramic resonator used.
The following information should be provided when ordering a custom mask.
(1) M58843-XXXP, M58844-XXXSP mask confirmation
sheet
(2) ROM data
3 EPROM sets
(3) S output PLA coding
On confirmation sheets
(4) Interrupt input Schmitt circuits
On confirmation sheets
(5) Port K input pull-down resistors
On confirmation sheets
(6) Port K input discharge transistors
On confirmation sheets
(7) Port S input/output pull-down resistors
On confirmation sheets
(8) Port D input/output pull-down resistors
On confirmation sheets
Fig. 6 Externally connected ceramic resonator
IM58844- xxxspi
X1N
XO UT I
I
25
t
J
241
OV
EXTERNAL OCILLATOR CIRCUIT -15
~
Fig. 7 External clock input circuit
•
4- ?4
MITSUBISHI
..... ELECTRIC
MITSUBISHI MICROCOMPUTERS
MS8843-XXXP,M58844-XXXSP
SINGLE-CHIP 4-BIT MICROCOMPUTER
WITH 8-BIT AID CONVERTER
LIST OF INSTRUCTION CODES
~-D'
Hexa03 decimal
notaI tion
Do
0000
0001
0
1
a 0000 a
0001
aa
a
NOP
CLS
SA
SMA
SLA
1
a
0010
a
0011
2
3
INY
DEY
0011 '0 0100
a
2
a
3
4
SZB
SEY
LCPS
a
a
a
SZB
SEY
LCPS
1
1
1
SZB
SEY
2
2
SZB
SEY
3
3
CLDS
SHL
~
CLD
~
SEY
0100
4
01
RO
RT
~
4
SEY
0101
5
EI
a
0101
a
5
CPAE
SO
INTH
TEPA
INTL
CPA
DEC
RTI
SEAM
OSPA
~
XAL
TLA
~
RC
~
S Z J
SC
AM
TEAB
~
~
OSE
OSAB
1101
1110
1111
C
D
E
F
TYA
TAJ
AMC
AMCS
SZD
TBA
~
XAM
BL
2
BML
~
XAM
BL
3
BML
TAM
BL
1
BML
~
TAM
BL
2
BML
~
~
TAM
BL
3
BML
LC7
~
XAMD
BL
0
BML
XAH
~
XAMD
BL
1
BML
THA
~
XAMD
BL
2
BML
~
~
XAMD
BL
3
BML
~
~
SEY
SB
RS
XAMI
BL
12
a
a
0
BML
SEY
SB
RB
XAMI
BL
13
1
1
1
BML
SEY
SB
RB
XAMI
BL
14
2
2
2
BML
SEY
SB
RB
XAMI
BL
15
3
3
3
BML
~
~
TAB
8
~
~
TAY
~
BML
1
11
1100
BL
1
lAS
SEY
B
o
~
10
1011
XAM
BL
SEY
A
1000
~
BML
9
1010
BML
0
SEY
9
BL
a
TAM
8
1001
XAM
a
SEY
8
7
lAS
7
1000
o
6
a
~
SEY
7
0111
~
6
0111
a
a
RHL
SEY
6
0110
RTS
~
5
0110
a
CPAS
BMLA
0010
a
~
~
~
CMA
SZC
a
1001
o
a
a
9
a
1010
1011
o
A
B
A
LA
a
a
A
LA
1
1
A
2
A
3
A
4
A
LA
5
5
A
6
A
7
a
1100
a
1101
oC
o0
LXY
LXY
a
1110
o
E
LXY
a
1111
o
F
a
1,
a
2,
a
3,
a
LXY
LXY
LXY
LXY
0,1
1,1
2,1
3,1
LA
LXY
LXY
LXY
LXY
2
0,2
1,2
2,2
3,2
LA
LXY
LXY
LXY
LXY
3
0,3
1,3
2,3
3,3
LA
LXY
LXY
LXY
LXY
4
0,4
1,4
2,4
3,4
~
~
~
~
LXY
LXY
LXY
LXY
0,5
1,5
2,5
3,5
LA
LXY
LXY
LXY
LXY
6
0,6
1,6
2,6
3,6
LA
LXY
LXY
LXY
LXY
7
0,7
1,7
2,7
3,7
A
LA
LXY
LXY
LXY
LXY
8
8
0,8
1,8
2,8
3,8
A
LA
LXY
LXY
LXY
LXY
9
9
0,9
1,9
2,9
3,9
~
~
~
~
~
A
LA
LXY
LXY
LXY
LXY
10
10
0, 10
1,10
2, 10
3, 10
~
A
LA
LXY
LXY
LXY
LXY
11
11
0,11
1,11
2,11
3,11
~
A
LA
LXY
LXY
LXY
LXY
12
12
0,12
1,12
2,12
3, 12
~
A
LA
LXY
LXY
LXY
LXY
13
13
0,13
1, 13
2,13
3, 13
~
A
LA
LXY
LXY
LXY
LXY
14
14
0,14
1, 14
2,14
3, 14
A
LA
LXY
LXY
LXY
LXY
15
15
0, 15
1, 15
2,15
3,15
~
~
Note 1: This list shows the machine codes and corresponding machine instructions. 03 - Do
indicate the low-order 4 bits of the machine code and 0 8 - 0 4 indicate the highorder 5 bits. Hexadecimal numbers are also shown that represent the codes.
An instruction may consist of one, two, or three words, but only the first word is
listed. Code combination indicated with a bar H must not be used.
10-17 18-1F
LXY
~
0,
1 0000 1 1000
I
I
1 0111 11111
BM
B
BM
B
BM
B
BM
B
BM
B
BM
B
BM
B
BM
B
BM
B
BM
B
BM
B
BM
B
BM
B
BM
B
BM
B
BM
B
Note 3: Page relationships for branching by means of branching
instructions and subroutine calling instructions.
Page (total of 8)
Address' 8
Note 2: Two-word instruction
BL
BML
BA
BMA
o
1
1
1
1
Second
1xxx
Oxxx
1xxx
Oxxx
1
word
yyyy
yyy y
XXXX
XXXX
Second word
0111 PPPP
0111 PPPP
2
3
Third word
1xxx XXXX
Oxxx XXXX
• MITSUBISHI
.... ELECTRIC
125
126
127
4~25
a
MITSUBISHI MICROCOMPUTERS
M58843-XXXP,M58844-XXXSP
SINGLE·CHIP 4·BIT MICROCOMPUTER
WITH 8·BIT AID CONVERTER
MACHINE INSTRUCTIONS
-l3
Type of
Mne.
monic
~~~~uc.
~ ~
Instruction code
'0
16 mal
0, 0,0,0,0. 0,0,0,0, notation ci
Z
1110
1100
1101
1100
1010
0110
0
0
0
0
0
0
1 E
1 C
10
OC
1 A
18
1
1
TEAB
TEPA
0001
0001
0001
0000
0001
0001
LXY x,y
0
1 1 x x
YYYY
0
Cy
TAY
TVA
~
a:
INV
o 0000 0010
0
X
02
DEY
o
0
03
LCPSI
001000001041
J
00110011108 4
TAM
I
.g
i
u
I
I
1
(Y)~(A)
(E,-E,)~
(X)~x,
(Y)~y,
(E,-Eo)~(A)
through
PLA~(A)
1
1
(Y)~(Y)+1
(Y)=O
1
1
(Y)~(Y)-1
(Y)=15
1
(CPS)~I,
1
(A)~(M(OP»
1
where x=0-3
where, y=0-15
(X)~(X)
V I,
1
(A)-(M(DP»
(x)~(x) Vi,
where, i=0-3
0011010110881
1
(A)-(M(DP», (Y)~(Y)-1
(X)~(X) VI, where. i=0-3
(Y)=15
1
(A)-(M(DP», (Y)~(Y)+1
(x)~(x) Vi, where, i=0-3
(Y)=O
t
0
1011
0
Bn
1
1
(A)~n,
o
0000 1010
0
OA
1
1
(A)~(A)+(M(DP»
AMC
o
0000 1110
0
OE
1
1
(A)~(A)
(Cy)~
o
o
0000 111 t
1010
0
0
OF
An
1
1
1
1
0/1
+ (M(DP» +(CY)
carry
(A)~(A)
+ (M(DP» + (CY)
(CY)=1
~
0/1
(cy)~carry
A carry is not
(A)~(A)+n,
produoed and
=0
where. n=0-15
(CY)-1
0 0100 1001
0 0100 1000
0 0010 1111
0 1000 1111
0
0
0
0
49
48
2F
8F
1
1
RC
SZC
CMA
1
1
(A)~(A)
SBI
o
0100
11
I I
o
4 C
1
1
(Mi(OP»~I,
where, i=0-3
I
o
0101
11
I I
0
5C
1
1
(Mi(DP»~O,
where. i=0-3
o
0010 001
I
0
RB
SZB
I
t
t
2 I
(Cy)~O
(CY)=O
x
x
x
(Mi(DP»
=0
where,;=0-3
CD
SEAM
000100110026
(M(DP»=
SEY Y
00011
(Y)=ywhere.
y=O-15
TLA
THA
TAJ
000011001
001011001
000001101
o
o
o
19
59
00
XAL
XAH
LC7
DEC
0
0
0
0
0001 1000
0101 1000
0101 0111
0000 1001
0
0
0
0
18
58
57
09
1
1
c:
SHL
o
0100 0010
o
42
1
i
RHL
o
0101
0010
o
52
$
CPA
o
0000 1000
o
08
~
~
03y
1
1
1
1
1
(Ll~(A)
1
(Y,y,)=Owhen.:
(Y,Y,)=1 when,:
(Y,Y,)=2when,:
(Y,Y,)=3 when.:
1
1
0
::c
CPAS
o
0101
0001
o
51
CPAE
o
0101
0000
o
50
SZJ
o 0010
1001
0
29
4-26
(A)~(J,J,J,J,)
Sets the jth bit of the RAM addressed by the active DP (the bit
designated by the value j in the instruction)
Resets the jth bit of the RAM addressed by the active DP (the
bit designated by the value j in the instruction!.
Skips next instruction when the contents of the jth bit of the
RAM addressed by the active DP (the bit which is designated by
the value j in the instruction) are O.
Skips next instruction when contents of register A are equal to
the RAM contents addressed by the active DP.
Skips next instruvtion. when the contents of register Yare equal
to the value y in the instruction.
Transfers contents of register A to register L.
Transfersconter'tts-otregister A to register H,.- -Transfers designated contents of register J to register A.
(A)~(OJ .. J.J.)
(A)~(O
0 0 0 )
(A)-(Ll
(A)-(H)
(C)~(C)-1
(C)=7
(C,)=1 when.: (H'e,-c, ~~1
(C,)=O when,: (Lle,-" ~~1
1
1
1
1
(C,)=1 when,: (H'e,-e, ,)~O
(C,)=O when, : (Lle,-e, ,)~O
IVrefl>IVK(i,lwhen.: (J(i~~1
IVreflIVK(i ,Iwhen, : (J" ~~1
IVrefl< IVK(i,1 when, : (J(i ~~O
;=0-10
Execution of the instruction CPAS is
over, and no more changes will made
in (J(y»).
• MITSUBISHI
"'ELECTRIC
Exchanges contents of register A with contents of register L.
Exchanges contents of register A with contents of register H.
Loads 7 to register C.
Decrements contents of register C by 1. when result is 7, skips
next.
Sets the bit in register L or H designated by register C. The box
7 6 5 4 3 2 1 0
instruction shows the nelatiol)ship (C)
between reqlster C and bit posltlon'l Bit IH,IH,I H,IH,I L,IL,[LJLo
Resets the bit in register L or H that is designated by register C.
Reads all analog values from input port K for comparison with
D·A converter output V ref and either sets the respective bit of
register J to the next instruction cycle wherever Vref < VK(lI
is true, or resets it wherever Vref < VK(I) is true.
Reads and stores temporarily all analog values from input port K.
which are then unaffected by changes in port K inputs. These
values are compared with the D·A converter output V ref,
calculated from contents of registers Hand L and respective bits
of negister J are set/reset. Repeated when contents of registers
H·L ane changed.
Terminates execution of instruction CPAS. Contents of register
J remain unaffected, maintaining the value immediately before
termination, and input port K is again ready to receive inputs.
Skips next instruction when the bit in register J, designated by
register Y. is O.
MITSUBISHI MICROCOMPUTERS
MS8843-XXXP,MS8844-XXXSP
SINGLE-CHIP 4-BIT MICROCOMPUTER
WITH 8-BIT AID CONVERTER
r-~r-----r----------------r~- ~~'-------------------------r--------r~---------------------------------------'
>~ype df MneInstruction code
~ [;
u
Skip
instructlon
monic
D, D,D,D,D, D,D,D,D,
Bxy
1 lxxx yyyy
16ma.1
00'
notation z
1 ey
Functions
00'
conditions
Z
Jumps to address xy of the current page.
Jumps to address xy on page 15 when executed, provirled that
none of instruction RT, RTS, Bl, BMl, BlA or BMlA was
executed after execution of instruction BM or BMA.
Jumps to address xy of page p.
+
BL pxy
0 0 1 IIp P P P
1 lxxx yyyy
0 7 P
1 ey
Description of operation
ill'
u::
1
2
(PCH)-p
(PC L )-16x+y
2
(PC L )-16x+( A)
+
'"
I
BA xX
o 0000 0001
o
1 1 x x x XXXX
1 ex
0 0000 000 1
00111pppp
1 1 x x x XXXX
o
o
01
x
+
BLA pxX
01
3
(PCH)-p
(PCL)~16x+(
7 p
1 ex
Jumps to address x(A) of the current page.
Jumps to the address x(A) of page 15 provided that none of
instructions. RT, RTS, Bl, BMl, BlA or BMlA was executed
after execution of instruction BM or BMA.
Ju mps to the address x (A) of page p.
A)
+
~~~B~M~xY--~1-0~X-X-X-y-y--y-Y~I--x-Y~'~~'(~SK~2~)~~(S~K~1~)----(S~K~O')-~(~P~C~)------~------~~X~~C~all~s~fo-r~th-e-su~b-ro-u~tin-e-st-ar~ti~ng-a-t-ad~d~re-ss-x-y-o-n-pa-ge~l4~.------'
(PC H)- 6,(PC L )-16x+y
BML pxy
~
BMA xX
0 0 1 IIp P P P
1 Oxxx yyyy
0000 0001
10xxxXXXX
o
o
7 P
x y
2
01
1 xX
2
1
o
x
(SK2)-(SK 1)-(SKO)~(PC)
(PCH)-p,(PCL)-16x+y
(SK2)-(SK 1)~(SKO)-(PC)
(PCH)-6. (PCL)~16x+(A)
Calls for the subroutine starting at address x(A) of page 14.
Jumps to address xy of page 14 provided that none of instructions. RT. RTS. Bl. BML, BlA or BMlA was executed after the
execution of instructions BM or BMA.
Calls for the subroutine starting at address xiA) of page p.
1.
~~
o 0000 0001
00111pppp
10xxxXXXX
o 01
3
(SK2)~(SK 1)-(SKO)-(PC)
(PCH)-P. (PCL)-16x+(A)
RTI
0010001100461
(PC)~(SKO)~(SK 1)-(SK2)
RT
001000100044
1
(PC)~(SKO)-(SK1)-(SK2)
SO
RO
SZO
000010101
000010100
000101011
1
1
1
where •.. O:a;(y) '" 10
(D(Y»-O. where ••. 0:a;(y):a;10
where ••. O:a;(Y):a; 10
OSAB
OSPA
000011011 0 lB 1
0000101110171
(5, -5, )~(B). (5, -So )-(A)
OSE
lAS i
000001011
00101010i
(S )-(E)
BMLA
pxx
o
1
71
Jumps to address xy of page 14 provided that none of instructions. RT, RTS, Bl, BML, BlA or BMLA was executed after the
execution of instructions BM or BMA.
Calls for the subroutine starting at address xy of page p.
x X
x
Restore internal flip-flop
X
Returns from interrupt routine to main routine. The internal flipflop is restored to the value held immediately before the inter rupt.
Roturns to the main routine from the subroutine.
1~r.R~T~s~-+~0~071~0~0-0~1~071~0~4~5~1~~7(~P~C)~~'(~S~K~0)~~7(~S~K~1)~-7(S~K~2~)------~-u-n-co-n-d-i_-1'X~~R~et~urn~s~to~th~e~m~a~in~r~0~ut~in~e~fr~0~m~t~he~su7b~ro~ut7in-e-,-an'd-u-n~ci~di---4
tiona I skip
5.
015
014
02B
tionally skips the next instruction.
(D(Y))~I.
(D(Y»= 0
(5, -So)~ through PLA-(A)
:J
o
:J
C.
C
jc:=
1
1
+
CLO
CLS
CLOS
EI
_
OOB
054
~TH
INTL
Mise NOP
000010011 013 1
o 0001 0000 0 10 1
000010001 0 11 1
000000101005
000000100 004
0000001100061
i=O : (A)~(S,-s,)
1= 1 : (A )-(5, -So)
(
)~O
(D)~O.
(S)~O
(INTE)~ 1
(INTE)-O
(INTP)~1
0000001110071
(INTP)~O
00000 0000
(PC)-(PC)+ 1
0 00
1
o
X
D)~O
(S
Sets the bit of port D that is designated by register Y.
Resets the bit of port D that is designated by register Y.
Skip the next instruction if the contents of the bit of port D
that is designated by register Yare o.
Output s contents of registers A and B to port S.
Decodes contents of register A by PlA and the result is output
to port.
Outputs contents of regisler E to port S.
Transfers from port S to register A. The high-order four bit of
port S are transferred when the value of i in the instruction is
or the low-order four bits are transferred when the value of i is 1.
Clears port D.
Clears port S.
Clears ports Sand D.
Sets interrupt flag INTE to enable intern",',ts.
Resets interrupt flag I NTE to disable interrupts.
Sets interrupt polarity flag INTP to enable interrupts when the
interrupt request signal is turned high.
Resets interrupt polarity flag INTP to enable interrupts when the
interrupt request signal is turned low.
No operation
RESET
Start from address "0" of page B.
Pin ~----+-----------4----+-4--+------------------------4---------r-+--------------------------------------~
(SK, )~(SK, )-(SKo )-(PC). (PCH)-4
INT
Calls for the subroutine starting at address "0" of page 12.
(PCL)~O
Symbol
DP
PCH
PCL
PC
SKO
Contents
4-bit register (accumulator)
4-bit register
3-bit register
8-bit register
4-bit register
l-bit register
4-bit register
2-bit register
4-bi t register
6-bit data pointer. combination of registers X and Y.
The high-order three bits of the program counter.
The low-order seven bits of the program counter.
lO-bit program counter, combination of PCH and PCL.
lO-bit stack reqlster
Contents
Symbol
SKI
SK2
CY
yyyy
II
XXXX
o
K
5
INTE
INTP
1(}bit stack register
1(}bit stack register
lobi t carry flag
2-bit binary variable
4-bit binary variable
4-bit binary constant
l-bit binary constant
2-bit binary constant
4-bit unknown binary number
11-bit port
11-bit port
8-bitport
I nterrupt enable flag
Interrupt polarity flag
Symbol
INT
(
-If
Contents
I nterrupt request signal.
Shows direction of data flow.
Indicates contents of the register. memory, etc.
Exclusive OR
Negation.
I ndicates flag is unaffected by instruction execution.
xy
pxy
CPS
C
label used to indicate the address xxxyyyy
Label used to indicate the address xxxyyyy of page pppp.
Indicates which data pointer and carry are active.
Hexadecimal number C + binary number x.
+
x
Note 1. When a skip is used with either the M 58843-XXXP or M 58843-XXXP. the next instruction becomes invalid and the program counter is not incremented
by 2. Therefore the number of cycles does not change in accordance with the existence or non-existence of a a skip.ln addition. since the M 58843-XXXP
is housed in a 28-pin package. some pins of the port K and D are not usable.
2. The M 58843-XXXP and M 58844-XXX SP programs are developed using a support system having a 2048 word x 9-bit ROM memory. When using such
a system. page 8 through 15 of the 2048 words (page 0 through 15) are used so that the program counter PCH - 0 - 7 is defined as page 8 through 15.
•
MITSUBISHI
;'ELECTRIC
4-27
a
MITSUBISHI MICROCOMPUTERS
MS8843-XXXP,MS8844-XXXSP
SINGLE-CHIP 4-BIT MICROCOMPUTER
WITH 8-BIT AID CONVERTER
ABSOLUTE MAXIMUM RATINGS
Symbol
Conditions
Parameter
Supply voltage
Input voltage, port Sand D, XIN and Vp inputs
Voo
V,
Input voltage, other than port Sand D, XIN and Vp inputs
V,
With respect to VSS
Vo
Power dissipation
Pd
Topr
Ta=25"C
Operating temperature
Storage temperature
Tstg
Min
Vss
Supply voltage
V ,H
High·level input voltage, port D
-1
0
V
V'H
High·level input voltage other than port D
High·level clock input voltage
-1.5
0
V
-1.5
0
V
Voo
V oo +2
-4.2
V
-4.2
V
-13.5
-16.5
V
0
Low·level input voltage, RESET and INT (Schmitt)
Low·level input voltage, INT (TTL compatible)
-33
V oo +2
V
Voo
0
V
Analog input voltage, port K
V REF
-5
-33
0
-7
V
0
V
V
300
600
kHz
V'(K'
VREF
Reference voltage
VOL
f( IV K (V)I
o when IV refi < IV K (V)I
In this relationship V represents the bit position in
register J which is designated by register V. The
comparison results can be checked for each bit using
the SZJ instruction.
(3) Registers Hand L
These two 4-bit registers are capable of transferring and
exchanging data to and from register A. The 8-bit
digital data for the D-A converter is transferred from
these registers, the higher order 4 bits from H and the
lower order 4 bits from L.
(4) Register C
This 3-bit register is used as a counter to designate ~it
positions in the Hand L registers.
(5) D-A Converter
The D-A converter converts the digital values stored in
the registers Hand L, referencing with the external
reference voltage VREF applied at the pin V REF , to
the analog value of the internal reference voltage V ref.
The theoretical value of the internal reference voltage
V ref if defined as follows.
MITSUBISHI
.... ELECTRIC
MITSUBISHI MICROCOMPUTERS
MS884S-XXXSP
SINGLE-CHIP 4-BIT MICROCOMPUTER
WITH a-BIT A/D CONVERTER AND TWO TIMER/EVENT COUNTER
n-0.5
Vref = 256 XVREF, where, n = 1,2, ......... 255
, where, n = 0
Vref = 0
In the above relationships n is the value weighted
according to the contents of registers Hand L.
AID Conversion Algorithms
AID conversion is controlled by the programming of the
previously described functional blocks. Thus, by modifying
the program, either the successive approximation method
or the sequential comparision method may be selected. In
addition, a digital input of high or low level may be used to
select the method, eliminating the software selection of the
AID conversion technique.
(1) Successive Approximation Method
In this method, the conversion speed is maintained at a
constant 600kHz regardless of the amplitude of the
analog signal. The A/D conversion process requires
0.6ms. 12 program words are required.
(2) Sequential Comparison Method
In this method the conversion speed varies in accordance with the rate of change of the analog quantity.
When the rate of change is slow, the conversion rate
increases. 30 program words are required.
instruction.
When an interrupt program is used, one level of the
three-level stack register is required, the remaining two
levels being used for subroutines. After the interrupt
program is started, the data pointer DP, register A, carry
flag CY, and registers used by the interrupt program are
saved. The RTI instruction is required to restore these
before returning to the main program.
When an interrupt occurs, the microcomputer internal
states are as follows.
(1) Program counter
The current address in the main program is stored in a
stack register and the vector interrupt address as shown
in Table 4 is loaded into the program counter.
(2) Interrupt flag INTE
The flag INTE is reset to disable further interrupts.
This disabled state will continue even afterreturn to the
main program by the RTI instruction until the execution of an EI instruction.
(3) Skip flags
Skip flags are provided to discriminate skip instructions
and consecutively described skip instructions. Each flag
has its own stack within which the skip state is saved.
As a mask option, the interrupt pins may be provided
with Schmitt input circuits.
TimerIEvent Counter (2 Lines)
interrupt Functions
The M58845-XXXSP provides 3-factor, 1-level vector interrupt capability, enabling unique branching addresses for
each interrupt factor.
The interrupt vector addresses are shown in Table 1.
The timer/event counter section consists of two lines
(timers). As shown in Fig. 8, this section includes timer 1
and its overflow flag (1 F) and timer 2 and its overflow flag
(2F), as well as the timer input/output port T and the timer
control registers V and W.
Table 1 Vector Interrupt Addresses
TIMER CONTROL REGISTERS
I nterrupt factor
Interrupt address
I nterrupt type
Causal cond ition
External interrupt
Rising edge at the INT
input pin
Page 1. add ress 0
Timer 1 interrupt
Timer 1 overflow
Page 1. address 2
Timer 2 interrupt
Timer 2 overflow
Page 1. address 4
An interrupt is generated whenever any of the causal
conditions listed in Table 1 are satisfied at a time when the
I NTE flag is set to 1 (when the E I instruction is executed
the INTE flag is set to 1, enabling interrupt; the D I
instruction clears this flag to 0, prohibiting interrupts). If
any of the interrupt causing conditions continues when the
INTE flag is 0, an interrupt is generated when the INTE flag
is set to 1.
The interrupts generated as a result of timer 1 and timer
2 overflow conditions can be software controlled, allowing
confirmation of the overflow condition using a skip
Fig. 4 Timer/event counter block diagram
The two timers (timer 1 and 2) are controlled by means
of the timer control registers.
(1) Timer 1
Timer 1 is implemented using an 8-bit binary counter
capable of being set and read by means of the Tl AB
and TABl instructions respectively. Starting and stopping of the counter as well as the selection of the
source (prescaler or timer 2) is accomplished by means
of the timer control register. When an overflow
condition occurs, setting the 1 F to 1 stops the
• MITSUBISHI
.... ELECTRIC
4-33
II
~
MITSUBISHI MICROCOMPUTERS
MS884S·XXX5P
SINGLE-CHIP 4-BIT MICROCOMPUTER
WITH 8-BIT A/D CONVERTER AND TWO TIMER/EVENT COUNTER
counting operation.
(2) Timer 2
Time 2 is implemented using an 8-bit binary counter
and is provided with an auto-reload register (register
R). Timer 2 data can be read using the TAB2
instruction and register R may be set as well as ready
by means of the TRAB and TABR instructions
respectively. Starting and stopping the counter as well
as the selection of the source (prescaler or external
input from port T) is controlled by the timer control
registers. In addition, when port T has been chosen as
the source, if only timer 1 is counting, gating is
possible by means of using counter enabling controlled
by the timer control registers. The overflow condition
results in the setting of the flag 2F, after which timer 2
can be set with data once more by register R
(auto-reload register) and continue counting.
(3) Prescaler
The overflow time can be selected as either 160J-Ls or
1270J-Ls (when using a 600kHz clock frequency) by
means of the counter control registers.
(4) Timer I/O port T
This port can be selected by the counter control
register as the source for timer 2. In addition, when
another source has been selected, a pulse is available at
this port every time timer 2 reaches the overflow
condition.
(5) Timer 1 and 2 overflow flags 1 F and 2F
These flags are set when. the corresponding timer has
reached the overflow condition. To test these flags,
generation of an interrupt and skip instructions (SNZ1,
SNZ2) can be used. The selection of which will be
used is made by the timer control registers. By using
either, these flags will be reset.
(6) Timer control registers V and W
The timer control registers are used to perform the
above described control functions. Instructions TVA
and TWA are used to transfer control data to these
register.
with capacity touch-type keys) may be selected as
mask options.
(2) Port D (D 11 "'Do)
This port consists of 12 bits which can be used for
both input and output functions by means of the SZD,
SO, and RO instructions. The output section provides
individual bit latching and the contents of register Y
can be used to designate a single bit of port D for
output or sensing. When using the port for input, the
output must be cleared to 0 first. The instructions CLO
and CLOS can be used to clear all bits of the port to O.
The outputs are open-drain circuits which can be
provided with pull-down transistors as a mask option.
(3) Port F (F3"'Fo)
This 4-bit port is controlled for output and input by
the OFA and IAF instructions respectively. When using
a bit for input, that bit output must first be set to O.
The outputs are open drain circuits.
(4) Port S (S7"'SO)
This port can perform 8-bit output using the OSAB,
OSPA, and OSE instructions and 4-bit input using the
lAS i instruction.
A built-in S output PLA has been provided which can
code 4 bits of register A data arbitrarily and provide
output using the OSPA instruction. The PLA output
coding is a mask option.
When the port is used for input, the outputs must first
be set to O. All the port S bits may be set to 0 by
means of the CLS or CLDS instructions.
The outputs are open-drain circuits which can be
provided with pull-down transistors as a mask option.
Vp Pin
This pin is used to supply the required voltage for the port
D and port S pull-down transistors. Built-in pull-down
transistors can be provided as a mask option for driving
Input/Output Ports
PLATE
(1) Port K (K7"'Ko)
This analog/digital input port is capable of 8-bit input
using the SZJ instruction and two groups of 4-bit
inputs using the lAS i instruction. The analog signal
may be AID converted using either successive approximation or sequential comparison, as determined by the
program. Also, an arbitrary threshold level in the range
O"'-7V with respect to the digital signal may be input,
enabling the use of the port as a high-noise immunity
input.
Pull-down transistors and discharge transistors (for use
4-34
...-4-~~~~-1'"" GRID
HEATER
Note 1. The M58845-XXXSP can be used to directly drive
fluorescent display tubes demanding up to c33V of
output level.
Note 2. To provide complete blanking. the heater should be
provided with a voltage of approximately 4 V from the
VP pin.
Fig. 5 Fluorescent display tube drive circuit
• MITSUBISHI
"'ELECTRIC
MITSUBISHI MICROCOMPUTERS
M58845-XXXSP
SINGLE·CHIP 4·BIT MICROCOMPUTER
WITH a·BIT A/D CONVERTER AND TWO TIMER/EVENT COUNTER
fluorescent display tubes, as shown in Fig. 5, eliminating
the need for the usual externally connected pull-down
resistors and resulting in a reduction in the number of
system components.
I
M58845-XXXP
xIN
XOUT
t
I
I
I
ov
- 15 V
lJl.Jl..f"
External oscillator
Reset
When the RESET pin is kept high for at least 3 machine
cycles, the reset state is enabled. After reset has been
performed, when the RESET input is driven low, program
execution will begin at page 0, address O.
When the reset state is enabled, the following operations
are performed.
(1) The program counter is set to 0, address 0, (PC) +- 0
(2) The interrupt mode is in the disabled state. INTE +- 0
(the same as for the execution of the 01 instruction)
(3) The carry and data pointer selector is set to 0,
specifying DP and CY.
(4) Registers V and Ware set to O. V=W +- 0 16
(5) The 3 interrupt flags, external interrupt flag (EXF),
timer 1 overflow flag (1 F), and timer 2 overflow flag
(2F) are reset. EXF=1 F=2F +- 0
(6) All outputs of port D are cleared to low (D) +- 0
(7) All outputs of port F are cleared to low (F) +- 0
(8) All outputs of port S are cleared to low (S) +- 0
(9) All outputs of port T are cleared to low (T) +- 0
Clock Generator Circuits
A clock generator circuit has been built in, to allow control
of the frequency by means of an externally connected RC
circuit or ceramic resonator. In addition, an external clock
signal may be applied at the XI N pin, leaving the XOUT pin
open. Circuit examples are shown in Fig. 6"'8.
with the device Icharacteristics, the constants
should be chosen so that the frequency falls
within a specified limit even including the effect
of these variations.
Fig. 6 External RC circuit
Fig. 8 External clock input circuit
Mask Options
The following mask options are available, specifiable at
time of initial ordering.
(1) S output PLA data
(2) Port K (K 7"'Ko) discharge transistors
(3) Port K (K7"'Ko) pull-down transistors
(4) Port D (D 11 "'Do) pull-down transistors
(5) Port S (S7"'SO) pull-down transistors
(6) Selection of interrupt input TTL-compatible Schmitt
circuits
(7) Selection of RESET input TTL-compatible Schmitt
circuits
(8) Selection of port T TTL-compatible Schmitt circuits
Documentation Required upon Ordering
The following information should be provided when ordering a custom mask.
(1) M58845-XXXSP mask confirmation sheet
(2) ROM data
3 EPROM sets
On confirmation sheets
(3) S output PLA coding
(4) Port K input discharge transistors
On confirmation sheets
(5) Port K pull-down transistors
(6) Port D pull-down transistors
(7) Port S pull-down transistors
(8) Selection of interrupt input TTL-compatible Schm itt
circuits
(9) Selection RESET input TTL-compatible Schmitt circuits
(10) Selection of Port T input TTL-compatible Schm itt
circuits
Note. The constants will depend on the frequency
and type of the ceramic resonator used.
Fig. 7 Externally connected ceramic resonator
• MITSUBISHI
"ELECTRIC
4-35
MITSUBISHI MICROCOMPUTERS
M58845-XXXSP
SINGLE-CHIP 4-BIT MICROCOMPUTER
WITH 8-BIT A/D CONVERTER AND TWO TIMER/EVENT COUNTER
MACHINE INSTRUCTIONS
r-~----~----------------~~~,,~ID''------------------------r------~--r-------------------------------------,
~ype o~
Mne-
~~~~uc-
~ ~
Instruction code
Functions
~
monic
Skip
conditions
i:i
Description of operation
~
r--1----~------------+-----~+=~~(-A~)~-(~B~)------------------~------~-r-T-ra-ns-fe-rs-c-o-nt-en-t-so-f-re-g-ist-er-B-t-o-re-g-is-~-rA-.-----------TAB
~
6
(B)~(A)
(A)~(Y)
(Y)~(A)
TBA
TAV
TVA
TEAB
i]
'en\-
1
(E,- E4)~(B)
(E3 - Eo)~(A)
(E, - Eo).- through
1
(x)~x
"'$
0: .~
~
TEPA
LXV x, Y 0
~
1 1 x x
Y Y Y Y
0
CV
+
~
LZ z
o
0100
1 01 z
0
4A
:2'
INV
0
0000
0010
0
02
+
-g
1
where,
Transfers contents of register
Transfers contents of register
Transfers contents of register
Transfer contents of reQisters
PLA~(A)
x=0-3
(Y)~y
where, y=0-15
(y)~z
where,
A
Y
A
A
to register B.
to register A.
to register Y.
and B to register E.
Decodes contents of register A in the PLA and transfers result
to register E.
Loads value of "x" into register X, and of "y" into Y. When LXY
is written successively the first is executed and successive ones are
skipped.
Written
successively
z~O.1
Loads value of "z" into register Z.
z
<{
a:
(Y)=15
DEV
0
0000 0011
0
03
LCPS ;
0
0100
000;
0
4 ;
1
(CPS)~I
TAM j
0
0110
01 j j
0
64
1
(A)~(M
(OP»
(X)~(X)VI where, 1=0-3
x
X
x
where, 1=0.1
Increments contents of register Y by 1. Skips next instruction
when new contents of register Yare "0".
Decrements contents of register Y by 1. Skips next instruction
when new contents of register Yare "15",
Transfers designated contents of register J to register A.
. __ __. - - - - - - - - Transfers the RAM contents addressed by the active DP to
register A. Reg ister X is then "exclusive OR-ed" with the value j
in the instruction, and the result stored in register X.
Exchanges the contents of the RAM DP and register A. Contents
of X are then "exclusive OR-ed" with the value i. and the result
stored in register X.
Exchanges the contents of the RAM and register A. Contents of
X are then "exclusive OR-ed" with the value j in the instruction,
and the result stored in register X. The contents of register Yare
decremented by 1, and when the result is 15, the next instruction
is skipped.
Exchanges the contents of the RAM and register A. Contents of
X are then "exclusive OR-ed" with the value j in the instruction
and result stored in register X. The contents of register Yare
incremented by 1, and when the result meets the next instruction
is skipped with the marked skip condition.
.
+
j
~
XAM j
0
0110
00 j j
0
6 j
1
(A)-(M (OP»
(X)~(X)VI where, 1=0-3
XAMD j
0
0110
10 j j
0
68
1
(A)-(M (OP»
~
1*
j
+
(X)~(X)"'I
XAMI j
<{
o
01 10
11 j j
0
BC
1
+
a:
where, 1=0-3
(A)-(M(OP»
(y) =0
(Y)~(Y)+1
IY)=masked
skip
condition
(X)~(X».'I
LA n
0
1011
OB
n
(Y)= 15
(Y)~(Y)-1
1
where, 1=0-3
(A)~n
where, n=0-15
AM A
0
0000
1010
0
OA
1
(A)~(A)
+ (M (OP»
0
AMC
0
0100
001 1
0
43
1
(A)~(A)
+ (M (Dp» + (CY)
~
AMCS
0
0101
001 1
0
53
1
~
A n
0
1010
SC
RC
SZC
CMA
0
0
0
0
0100
0100
0010
0000
SB j
0
0100
c
.;::;
~
x
Written
successively
o
CY~Carry
(A)~(A)+
CY~Carry
u
.;::;
0
An
1001
1000
1111
1111
0
0
0
0
49
48
2 F
OF
11 j j
0
4C
o
(M (OP» + (CY)
A carry is not
produced and
=0
nt 6
Loads the value n into register A. When LA is written consecutively the first is executed, and successive ones are skipped.
Adds the contents of the RAM to register A. The result is retained in register A, and the contents of flag CY are unaffected.
Adds the RAM contents addressed by the active DP and contents
1 of flag CY to register A. The result is stored in register A and the
carry in the active flag CY.
1 Adds the contents of the RAM and flag CY to register A. The
result is stored in register A and the carry in the CY, but the
next instruction is skipped when a carry is produced.
Adds value n in the instruction to reqister A. The contents of
flag CY are unaffected and their next instruction is skipped if
a carry is not produced, except when n=6,
Sets active flag CY,
Resets active flag CY.
Skips next instruction when contents of the active flag CY are O.
Stores complement of register A in register A.
1
(A)~(A)+n
1
(MI
(OP»~1
where, 1=0-3
Sets the jth bit of the RAM addressed by the active DP (the bit
designated by the value j in the instruction).
1
(MI
(OP»~O
where, 1=0-3
Resets the jth bit of the RAM addressed by the active DP (the
bit designated by the value j in the instruction).
.
where, n=0-15
~
(CY =0)
c
0
~
~
iii
j
RB j
0
0101
11 j j
0
5C
j
(MI (OP» =0 X
where, 1=0 - 3
SZB j
0
0010
00 j j
SEAM
0
0010
0110
0
2 B
(M(OP»
=(A)
SEV Y
0
0011
Y Y Y Y
0
3 Y
(Y) =y
TLA
THA
XAL
XAH
LC7
DEC
0
0
0
0
0
0
0001
0101
0001
0101
0101
0000
1001
1001
1000
1000
0111
1001
0
0
0
0
0
0
19
59
18
58
57
09
1
1
1
1
1
(A)-(L)
1
(C)~(C)-1
SHL
0
0100
0010
0
42
1
(C,) = 1 when : (H(C,- Co»~1
(C,) =0 when : (L(c,-Co)~1
0
2 j
~
~
~
(L)~(A)
X
X
(H)~(A)
(A)-(H)
(C)~7
(C)=7
I
~
RHL
0
0101
0010
0
52
{!!
~
8
X
x
Transfers contents of register A to register L.
Transfers contents of register A to register H.
Exchanges contents of register A with contents of register L.
Exchanges contents of register A with contents of register H.
Loads 7 to register C.
Decrements contents of register C by 1, when result is 7, skips
Sets the bit in register L or H designated by register C. The box
instruction shows the relationship between register C and bit position.
I
.g
~
Skips next instruction when contents of register A are equal to
the RAM contents addressed by the active DP.
Skips next instruction when the contents of register Yare equal
to the value y in the instruction.
where,
y=0-15
u
Skips next instruction when the contents of the jth bit of the
RAM addressed by the active DP (the bit which is designated by
the value j in the instruction) are O.
CPA
0
0000
1000
0
08
0
~
CPAS
4-36
0
0101
0001
0
51
1
(C z )=1 when :
(C,)=O when :
(H(C,-Co»~O
(c)
Bit
I 7 L6 1 5 J 4 I 3 I 2 I 1 I 0 I
I H3 I H, I H, I Ho I L3 I L, I L, I Lo I
Resets the bit in register Lor H that is designated by register C.
(L(C,-Co)~O
IVre1 1> IVK(,)I when: (J ('»~1
IVre11 < IVK("I when: (J (,»~O
1=0-7
Reads all analog values trom input port K for comparison with DO-A converter output V ref , and either sets the respective bit of
register J to the next instruction cycle, wherever Vref > VK(l)
is true, or resets it, wherever Vref VK(11 is true.
IVrel I> IVK(')I when: (J (, ))~1
IVrell-
T~pe of
instruc-
Mne-
tion
monic
i!!
~ g
8 .~
e~
«0
Skip
Fur.ctions
CPAE
001010000050
TAJ
000001101000
SZJ
00010
TlAB
010000100
TRAB
conditions
termination, and input port K is again ready to receive input.
x
x
1001029
1
01000
0101085
1
TABI
01000
1000088
1
~
TABR
010001001089
1
E
TAB2
010001010
1
TVA
TWA
SNZI
SNZ2
010000110086
010000111087
010000010082
010000011083
B xy
1
(1,-14)-(8)
(13 -lo)~(A)
(R, R4)' ·(B)
i=
1 x x x
y y y Y
08A
1
Transfers contents of register A and register B to timer 1.
Transfers contents of register A and register B to timer 2 auto
reload register R.
Transfers contents of timer 1 to register A and register B.
x
Transfers contents of timer 1 auto reload register R to register A
and register B.
Transfers contents of timer 2 to register A and register B.
0
1
0 1 lIP P P P
l x x x YYYY
(W)~(A)
(IF)=1
(2F)= 1
1
8 y
(PCL)~16xty
(PCH)~3.
0 7 P
18y
x
(V)~(A)
I
2
2
(PCL)~
Skips next instruction when the bit in register J, designated bV
register Y, is O.
X
(B)~(17
1
1
+-
BL pxy
14)
(A)-· (13.10)
(B)~(R,- R4)
(A).-(R3Ro)
(B).-(2,'2 4)
(A)+-(23 -20)
I
x
(R3-Ro)~(A)
.8
Description of operation
01
u::
Terminates execution of instruction CPAS Contents of register
J remain unaffected, maintaining the value immediatelv before
1 I Execution of the instruction CPAS is
over, and no more changes will made
in (J(Y)I
1 (Yo)=O when: (A)+-(J, J, J, co)
(Yo) =1 when : (A)~ (h h J5 J4)
084
U
x
x
x
x
x
16x + Y
Transfers
Transfers
Skips the
Skips the
contents of register A to timer control register V
contents of register A to timer control register W.
next instruction if flag 1 F is 1.
next instruction if flag 2F is 1.
II
Ju mps to address xv of the current page.
Ju mps to address xv on page 3 when executed. provided that
none of instruction RT. RTS, BL. BML, BLA or BMLA was
executed after execution of instruction BM or BMA
(PCH)~P
x
Jumps to address xv of page p.
x
SUQroutine on the current paqe. Exchanae the lower 4 bits of the con1~~t,se~J ~g~~'l(' xX With the contents aT register A and branch to
(PCL)~16x+-y
+.c
o
BA xy
c
0000
0001
XXX X
o
1
Cll
BLA pxy 0 a a 0 0
00111
1 lxxx
aa0 1
PPPP
XXX X
01
8 X
2
2
(PCL)~16x
+ (A)
x
Page 3 subroutine : After execution of a SM or SMA Instruction without execution of aRT. RTS.SL. SML. SLA. or SMLA Instruction. when a SA Instruction
IS executed branching IS done tu address 16x+ (AI on page 3
3
0 0 1
07P
18X
(PCH)~P
(PCL)~16x+
x
(A)
+
IBM
1
xy
0 x x x
1
1
x Y
(SK,J---(SK,).(SKo)+-(PC)
(PC H)·2. (PCL)~16x' y
x
Subroutine on a different page: Exchange the lower 4 bits of the contents of address xX with the contents of register A and branch to the
address 16x+ (A)
Calls for the subroutine starting at address x(A) of page 2.
Jumps to address xv of page 2 provided that none of instructions. RT, RTS, BL, BML. BLA or BMLA was executed after the
execution of instructions BM or BMA.
BML pxy 0
a
1 lIP P P P
y y y y
lOx x x
0
x Y
01
x X
1
2
7 P
1
o
(SK2)·(SK1)~(SKo)~(Pc)
(PCH)~P.
2
(PCH)~2.
I
(PCL)~16x
x
Cails for the subroutine starting at address xv of page p.
x
Calls for the subrouti~e starting at address x(A) of page 2.
+Y
(SK2)~(SK,)~(SKo)~(PC)
(PCL)~16x+
(A)
(PC )+--2 (PC )~16x-t (A)
H
.
L
I
Jumps to address x(AI of page 2 provided that none of instruc·
tions. RT, RTS, BL. BML, BLA or EMLA was executed after the
execution of instructions BM or BMA
f-------.--.--------_+----~_+~~--------------------~~------+_~~~~~.~~~~~~~--------------_1
I
BMLA
pxX
a
0000
o 0111
1
Oxxx
0001
PPPP
XXXX
0
0
1
01
7P.
xX
3
3
(SK2)~(SK1)~(SKo)~(PC)
(PCH)~P,
x
Calls for the subroutine starting at address x (A) of page p.
lPCL)+-16x+-(A)
RTI
a 0100 0110 0 4 6
x Returns from interrupt routine to main routine. The internal flipE8'~ ~~R_T____~__________~____+-~-+~~~~~~~__~____~________~~f~IO~P~iS~ffi=st=o=ffi=d~to~t~h~ev=a=lu~e~he~ld~im~m~e~d+ia=te~lv~be~f~o~re~th=e~in~re~r~ru~p~t
~
01 0
a
01 00
0
44
1
a
0100
010 1
0
45
1
CLO
CLS
CLOS
000010011013
000010000010
000010001011
1
1
(0)·-0
1
(D).·O
(S)+-O
so
RO
5.
SZO
:J
1
(PC)~(SKo)~(SK,)·'(SK2)
0
RTS
..
.t
,
O~
0001
0101
o
00010100014
0010101102B
x
x
(S)~O
1
Clears ports Sand D.
Sets the bit of port D that is designated bV register Y.
(D(Y»-Owhere,Y=O-11
x
Resets the bit of port!) that is designated bV register Y.
Skips the next instruclion if the contents of the bit of port D
that is designated bV register Y areO.
Output contents of registers A and B to port S.
(D(Y))=O
where.
Y=0-11
X
lB
1
(S7-S4)~(B)
000010111017
1
(S,-S4)· through PLA.·(A)
X
OSE
lAS i
00000
10110
OB
1
(S)~(E)
X
00101
010i
054
1
10000110110
Clears port S.
x
OSPA
OSAB
Returns to the main routine from the subroutine .
Returns to the main routine from the subroutine, and uncon,
ditionallv skips the next instruction.
Clears port D. (low level output)
=0- 11
(D (y »~ 1 where. Y
15
x
x
(PC).-(SKo)~(SK,)+-(SK2)
x
(S3-So)~(A)
I=D(A)~(S7-S4)
I =1
(A)~(S3-
X
So)
o
j
OFA
IAF
NOP
Decodes contents of register A bv PLA and the result is output
to ports.
Outputs contents of register E to port S.
Transfers from port S to register A. The high-order four bits of
port S are transferred when the value of i in the instruction is
or the low-order four bits are transferred when the value of i is 1
Sets interrupt flag I NTE to enahle interrupts.
Resets interrupt flag I NTE to disable interrupts.
0 1 0 0 0 0001
81
0100011008C
1
1
(F)-(A)
(A)-(F)
X
000000101005
1
(INTE)~1
X Outputs contents of register A to port F.
1
(INTE)~O
X
Transfers input from port F to register A.
X
No operation.
i000000100
004
[0
0
0000
0000
x
00
•
MITSUBISHI
.... ELECTRIC
4-37
MITSUBISHI MICROCOMPUTERS
MS884S-XXXSP
SINGLE-CHIP 4-BIT MICROCOMPUTER
WITH 8-BIT A/D CONVERTER AND TWO TIMER/EVENT COUNTER
Symbol
Symbol
Contents
A
B
C
4-bit register (accumulator)
4-bit register
3-bitregister
8-bit register
4-bit register
8-bit register
Symbol
Contents
Contents
Shows direction of data flow
Indicates contents of register, memory, etc.
SKo
SK I
SK,
II-bit stack register
II-bit stack register
II-bit stack register
2
Cy
INTE
Timer 2
I-bit carry flag
Interrupt enable flag
CP S
Indicates which data pointer and carry are active
W
4-bit register
8-bit timer 2 auto reload register
4-bit register
4-bitregister
2-bit register
4-bit register
I-bit register
1F
2F
EXF
I-bit timer 1 overflow flag
I-bit timer 2 overflow flag
I-bit external interrupt flag
12-bit port
4-bit port
xy
2-bit binary variable
4-bit binary variable
I-bit binary variable
4-bit binary variable
I-bit binary constant
2-bit binary constant
4-bit unknown bibary number
Exclusive-OR
Negation
Indicates flag is uneffected by instruction execution
Label used to indicate the address XXXYYYY
DP
7-bit data pointer, combination of registers X, Y, and Z
K
8-bit port
nxy
Label used to indicate the address XXXYYYY of page PPPP
PC H
PC L
PC
The high-roder 4-bits,of the program counter
The low-order 7-bits of the program.counter
S
T
II-bit program counter, combination of PCH and peL
INT
8-bit port
I-bit port
i Interrupt request signal
Note 1 ,
yyyy
Timerl
II
XX XX
V
Hexadecimal number C + binary number x
When a skip has occurred, the next instruction only is ignored and the program counter is not incremented by
2, therefore, the number of cycles does not change in accordance with the eXistence or non-existence of skip
I NSTR UCTI ON CODE TABLE
~~D'I
D3~
Do
o 0001 o 0010 o 0011 o 0100 o 0101 o 0110 o 0111 o 1000 o 1001 o 1010 o 1011 o 1100 o 1101 o 1110 o 1111
00000
Hexadecimal
number C
0 0
o
1
o2
o3
o4
SZB
SEY
LOPS
0
0
0
SZB
SEY
LOPS
1
1
1
SZB
SEY
2
2
SZB
SEY
3
3
0000
0
0001
BA
1 BMA OLDS
BLA
BMLA
0010
2
INY
0011
3
DEY
OLD
0100
4
01
RD
-
0101
5
EI
SO
-
0110
6
-
0111
7
-
1000
8
1001
NOP
OLS
-
SEY
4
SEY
5
SEY
TEPA SEAM
6
SEY
OSPA
-
OPA
XAL
-
9
DEO
TLA
1010
A
AM
TEAB
1011
B
OSE
OSAB
SZD
1100
0
TYA
TBA
-
1101
0
TAJ
TAY
-
1110
E
-
TAB
-
1111
F
8
SEY
4-38
OMA
-
-
SZO
9
OPAE
OPAS
RHL
AMO AMOS
RT
RTS
RTI
-
7
SEY
SZJ
SHL
o5
RO
SO
o6
o7
XAM
BL
0
BML
XAM
BL
1
BML
XAM
BL
2
BML
XAM
BL
3
BML
lAS
TAM
BL
0
0
BML
lAS
TAM
BL
1
1
BML
-
L07
XAH
THA
TAM
BL
2
BML
TAM
BL
3
BML
XAMD
BL
0
BML
XAMD
BL
1
BML
SEY
LZ
10
0
SEY
LZ
11
1
SEY
SB
RB
XAMI
BL
12
0
0
0
BML
SEY
SB
RB
XAMI
BL
13
1
1
1
BML
SEY
SB
RB
XAMI
BL
14
2
2
2
BML
SEY
SB
RB
XAMI
BL
15
3
3
3
BML
-
-
XAMD
BL
2
BML
XAMD
BL
3
BML
o8
-
o9
-
OFA
-
SNZl
-
SNZ2
-
T1AB
-
TRAB
-
TVA
-
TWA
-
TABl
-
TABR
TAB2
-
IAF
-
-
-
-
-
-
-
-
-
-
• MITSUBISHI
"ELECTRIC
oA
o
B
o
0
o0
o
E
o
F
A
LA
LXY
LXY
LXY
LXY
0
0
0,0
1,0
2,0
3,0
A
LA
LXY
LXY
LXY
LXY
1
1
0,1
1,1
2,1
3,1
A
LA
LXY
LXY
LXY
LXY
2
2
0,2
1,2
2,2
3,2
A
LA
LXY
LXY
LXY
LXY
3
3
0,3
1,3
2,3
3,3
A
XA
LXY
LXY
LXY
LXY
4
4
0,4
1,4
2,4
3,4
A
LA
LXY
LXY
LXY
LXY
5
5
0,5
1,5
2,5
3,5
A
LA
LXY
LXY
LXY
LXY
6
6
0,6
1,6
2,6
3,6
A
LA
LXY
LXY
LXY
LXY
7
7
0,7
1,7
2,7
3,7
A
LA
LXY
LXY
LXY
LXY
8
8
0,8
1,8
2,8
3,8
A
LA
LXY
LXY
LXY
LXY
9
9
0,9
1,9
2,9
3,9
A
LA
LXY
LXY
LXY
LXY
10
10
0,10
1,10
2,10
3,10
A
LA
LXY
LXY
LXY
LXY
11
11
0,11
1,11
2,11
3,11
A
LA
LXY
LXY
LXY
LXY
12
2
0,12
1,12
2,12
3,12
A
LA
LXY
LXY
LXY
LXY
13
13
0,13
1,13
2,13
3,13
A
LA
LXY
LXY
LXY
LXY
14
14
0,14
1,14
2,14
3,14
A
LA
LXY
LXY
LXY
LXY
15
15
0,15
1,15
2,15
3,15
1 0000
\
I 0111
1 1000
\
11111
10~
18~lF
17
BM
B
BM
B
BM
B
BM
B
BM
B
BM
B
BM
B
BM
B
BM
B
BM
B
BM
B
BM
B
BM
B
BM
B
BM
B
BM
B
MITSUBISHI MICROCOMPUTERS
MS884S-XXXSP
SINGLE-CHIP 4-BIT MICROCOMPUTER
WITH 8-BIT A/D CONVERTER AND TWO TIMER/EVENT COUNTER
Note 1: This list shows the machine codes and corresponding machine
instructions. D 3 -D o indicate the low-order 4 bits of the
machine code and D 8 -D 4 indicate the high-order 5 bits.
Hexadecimal nu mbers are also shown that represent the codes
An instruction may consist of one, two, or three words, but
only the first word is listed. Code combination indicated with
a bar (-) must not be used.
Note 3. Relationships between branching and page by means of
branching instructions and subroutine calling instructions,
Page (total of 16)
Address
Note 2: Two-word instruction
o
Second word
1
BML
lxxx YYY
1 Oxxx YYYY
BA
1
lxxx XXXX
BMA
1
Oxxx XXXX
2
1
BL
II
< XXxYYYYX XXXXXXXX ~
Port K inputs
K8-KO I
XXXXXXXX
Port F outputs
F3- F O
(Output)
J..
Port F inputs
F3- F O
(Input)
IXYXXXXXX XXXXXXX/ XXJ\./<-,-y
(PCH)~3.
c
X
x
x
(PCL)~16x+y
BL pxy
o
00111PPPP07P
1 lxxx yyyy 1 8 y
2
2
(PCH)~P
Transfers the contents of register A to register V
Skips the next instruction when the flag 1 F is 1
Skips the next instruction when the flag 2F is 1
Jumps to address xy of the current page.
Jumps to address xy on page 3 when executed, provided that
none of instructions. RT, RTS, BL, BML, BLA or BMLA was
executed after execution of instruction BM or BMA.
E
~
8
the Instruction) are 0
the RAM contents addressed by. the active DP.
Skips next instruction when the content of register Yare equal
to the value y in the instruction
y~0-15
a
.;:;
g.
111
x Skips next instruction when contents of register A are equal to
(A)
8
.~
~~~s(i:::,e~ei~i~t:~~i~7dn v~~:~a~hder~s~~~e~~ t~: ~hc~iC: 8~ ~~~h~it
(M, (OP»=O
where ,~0-3
x
Jumps to address xy of page P.
(PCL)~16x+y
+
BA xX
o
"-
U
Description of operation
8'
u:
X
Jumps to the address x/A) of page p.
X Calls for the subroutine starting at address xX on page 2
Jumps to address xy of page 2 provided that none of instructions. RT, RTS, BL, BML, BLA or BMLA was executed after
the execution of instruciions BM or BMA.
X Calls for the subroutine starting at address xy of page p.
~----~------~~~--~+-~-+--~----~--------------~-------4--~-----------------------------------
X
Calls for the subroutine starting at address x(A) of page 2.
Jumps to address x(A) of page 2 provided that none of instructions. RT, RTS, BL, BML, BLA or BMLA was executed after
the execution of instructions BM or BMA.
X
II
Calls for the subroutine starting at address x(A) of page p.
x Retwns from interrupt routine to main routine. The internal
flip-flop is restored to the value held immediately before the
interrupt.
x
Unconditional skip
Returns to the main routine from the subroutine.
x Returns to the main routine from the subroutine, and unconditionally skips the next instruction.
x Clears port D.
x Clears port S.
X Clears ports Sand D.
X Sets the bit of port 0 that is designatl!d by
(D(y»~o
wher:~O-ll
"''l'S''''
Y
x Resets the bit of port 0 that is desiglliltod ily "HI",I", Y
x Skips the next instruction if the contl!lllso1 II", IlIllIl 1",,111 11'011
x
~~t~~;n:~~~e~isr~t:~~~s~:sn1 ~~d B to port S.
x
Decords conents of register A by PLA and the result is output
to port S.
X Outputs contents of register E to port S.
x Transfers from port S to register A. The high-order four bits of
port S are transferred when the value of i in the instruction is
or the low-order four bits are transferred when the value of i is 1.
o
x
X
X
x
Transfers the port F input to register A.
Outputs contents of register A to port G.
Transfer the port K input to register A.
Skips the next instruction if the jth bit of port K input is O.
Sets port U to 1.
Resets port U to 0
X Sets interrupt flag INTE to enable interrupts.
x Resets interrupt flag INTE to disabel interrupts.
x
Contents
Symbol
B
E
4-bit register (accumulator)
4-bit register
S-bit register
S-bit
4-bit
2-bit
4-bit
l-bit
DP
PC H
PCL
PC
SKO
SK t
SK2
timer overflow register
register
register
register
register
Symbol
cy
IF
2F
yyyy
7-bit data pointer, combination of registers, X, Y and Z
II
Thehigh-order four bits of the programcounter.
The low-order seven bits of the program counter.
xxxx
l1-bit program counter combination of PC H dnd peL
ll-bit stack register
ll-bit stack register
ll-bit stack register
F
G
u
Contents
l-bit carry flag
l-bit timer 1 overflow flag
l-bit timer 2 overflow flag
2-bit binary variable
4-bit binary variable
l-bit binary variable
4-bit binary constant
l-bit binary constant
2-bit binary constant
4-bit unknown binary number
Timer 1
Timer 2
l2-bit port
4-bit port
4-bit port
l-bit port
• MITSUBISHI
..... ELECTRIC
No operation.
Symbol
INTE
INT
EXF
,'"
xy
CPS
pxy
C
+
Contents
4-bit port
S-bit port
Interrupt enable flag
Interrupt request signal
l-bit external interrupt flag
Shows the direction of data flow.
I ndicates the contents of register, memorY,etc.
Exclusive OR
Negation.
I ndicates flag is unaffected by instruction execution
Label used to indicate the address xxx yyyy
Indicate which data pointer and carry flag are actiVE
Label used to indicate the address xxx Wyyon page PPP.
Hexadecimal number C + binary number X
4-49
MITSUBISHI MICROCOMPUTER
MS8846-XXXSP
SINGLE-CHIP 4-BIT MICROCOMPUTER
WITH TWO TIMER/EVENT COUNTER
INSTRUCTION CODE LIST
~D'
o _
3
00000
Hexadecimal
notation 0 0
a 0001 a 0010 a 0011 o 0100 a 0101 a 0110 a 0111 a 1000 a 1001 a
o
Do
1
0000
0
0001
1
0010
2
INY
-
0011
3
DEY
CLO
0100
4
01
RO
NOP
CLS
BA
SMA CLOS
SLA
BMLA
o2
o3
o4
SZB
SEY
LCPS
0
0
0
SZB
SEY
LCPS
1
1
1
SZB
SEY
2
2
SZB
SEY
3
3
-
RT
4
RTS
-
5
EI
0110
6
RU
TEPA SEAM
0111
7
SU
OSPA
1000
8
-
1001
9
-
1010
A
AM
TEAB
1011
B
OSE
OSAB
SZO
1100
C
TYA
TBA
-
1101
0
-
TAY
-
1110
E
-
TAB
-
1111
F
5
SEY
6
RTI
SEY
-
-
7
SEY
-
CMA
-
RC
-
8
SEY
-
-
AMC AMCS
SEY
-
0101
-
-
o7
o6
o8
XAM
BL
0
BML
-
XAM
BL
1
BML
-
SEY
SO
o5
9
SC
XAM
BL
2
BML
XAM
BL
3
BML
lAS
TAM
BL
0
0
BML
lAS
TAM
BL
1
1
BML
2
BML
-
IAK
Tqr
TAM
BL
3
BML
XAMO
BL
0
0
BML
1
LZ
0
SEY
LZ
11
1
3
SEY
SB
RB
12
0
0
SEY
SB
RB
XAMI
BL
13
1
1
1
BML
SEY
SB
RB
XAMI
BL
14
2
2
2
BML
SEY
SB
RB
XAMI
BL
15
3
3
3
BML
SZC
SNZ2
-
OGA
-
TVA
-
10
SZK XAMO
2
-
-
-
-
-
-
BML
1
SEY
-
SNZl
-
BL
SZK XAMO
-
T2AB
oA
-
OFA
-
SZK
o9
BL
BML
2
BL
SZK XAMO
TAB2
-
-
-
BML
3
BL
(AOMI
BML
IAF
-
-
-
Note 1. This list shows the machine codes and corresponding machine instructions. 03-00
indicate the low order 4 bits of the machine code and OB-04 indicate the highorder 5 bits. Hexadecimal numbers are also shown that represent the codes.
An instruction may consist of one, two ,or three words, but only the first word is
listed Code combination indicated with a bar (-) must not be used.
10 10
-
-
--
-
a
1011
o
a
1100
a 1101 a 1110 a 1111
B
oC
o0
o
A
LA
LXY
LXY
LXY
LXY
0
0
0,0
1,0
2,0
3,0
A
LA
LXY
LXY
LXY
LXY
1
1
0,1
1-,1
2,1
1,1
A
LA
LXY
LXY
LXY
LXY
2
2
0,2
1,2
2,2
3,2
A
LA
LXY
LXY
LXY
LXY
3
3
0,3
1,3
2,3
3,3
A
XA
LXY
LXY
LXY
LXY
4
4
0,4
1,4
2,4
3,4
A
LA
LXY
LXY
LXY
LXY
5
5
0,5
1,5
2,5
3,5
A
LA
LXY
LXY
LXY
LXY
6
6
0,6
1,6
2;6
3,6
A
LA
LXY
LXY
LXY
LXY
7
7
0,7
1,7
2,7
3,7
A
LA
LXY
LXY
LXY
LXY
8
8
0,8
1,8
2,8
3,8
A
LA
LXY
LXY
LXY
LXY
9
9
0,9
1,9
2,9
3,9
E
A
LA
LXY
LXY
LXY
LXY
10
0,10
1,10
2,10
3,10
A
LA
LXY
LXY
LXY
LXY
11
11
0,11
1,11
2,11
3,11
A
LA
LXY
LXY
LXY
LXY
12
13
0,12
1,12
2,12
3,12
A
LA
LXY
LXY
LXY
LXY
13
13
0,13
1,13
2,13
3,13
A
LA
LXY
LXY
LXY
LXY
14
14
0,14
1,14
2,14
3,14
A
LA
LXY
LXY
LXY
LXY
15
15
0,75
1,15
2,15
3,15
Second word
YYY
BML
1 Oxxx
YYYY
BA
1 lxxx XXX X
BMA
1 Oxxx XXXX
Three-Word Inst ructions
Second word
Third word
r BLA
0 0111 pppp
1 lxxx XXXX
IBMLA
0 0111
1 Oxxx XXXX
PPPP
•
4-50
1 1000
\
\
1 0111
11111
10-17 18-1F
B
BM
B
BM
B
BM
B
BM
B
BM
B
BM
B
BM
B
BM
B
BM
B
BM
B
BM
B
BM
B
BM
B
BM
B
BM
B
BM
B
Note 3. Relationships for branching by means of branching instructions
and subroutine calling instructions.
PAGE (TOTAL OF 16)
1 lxxx
F
10
Note 2. Two-Word Instructions
BL
o
1 0000
126
127
MITSUBISHI
~ELECTRIC
MITSUBISHI MICROCOMPUTER
MS8846-XXXSP
SINGLE-CHIP 4-BIT MICROCOMPUTER
WITH TWO TIMER/EVENT COUNTER
ABSOLUTE MAXIMUM RATINGS
Limits
Unit
VOO
Supply voltage
0.3- -20
V
VI
Input voltage (ports D and S, and input Vp)
0.3- -33
V
0.3--20
V
V
Symbol
VI
Parameter
Conditions
Input voltage, inputs other than ports D and S, and input Vp
With respect to Vss
Vo
Output voltage, ports D and S
0.3- -33
Vo
Output voltage, other outputs than ports D and S
0.3--20
Pd
Power dissipation
Topr
Operating temperature
--10-70
°C
Tstg
Storage temperature
-40-125
°C
V
1100
Ta=25°C
mW
RECOMMENDED OPERATING CONDITIONS ("1-a=-10-70°C, unless otherwise noted)
Limits
Symbol
Parameter
Unit
Min
Nom
Max
-11
-12
-13
VOO
Supply voltage
VSS
Supply voltage
Vp
Pull-down transistor supply voltage
0
-33
V
VIH
High·level input voltage, ports Sand F
-1.5
0
V
VIH
High-level input voltage, port D
-1.0
0
V
VIH(¢)
High·level clock input voltage
-1.5
0
V
0
V
V
VIL
Low-level input voltage, inputs other than ports D and S
Voo
-4.2
'J
VIL
Low-level input voltage, ports D and S
-33
-4.2
V
VIL(¢)
Low·level clock input voltage
VOO
VOL
Low-level output voltage, ports D and S
f (¢)
Internal clock oscillation frequency
VOO+2
V
-33
0
V
300
600
kHz
Note 1. VI L( cj» is specified for the maximum Voo value
ELECTRICAL CHARACTERISTICS
(Ta=-10-70°C, Voo=-12V 10%, Vss=OV, f(< XXXXXYVY. 'XYXXXXXX xxxxxxxX
X
XXXXXXXX XXXXXXXX XXXXXXXX 'XYYX'xY'0( -
Xi\(")(') ~
X
X
XYYY\l\/\J\/' ~ ~:x YYYY\!YY'xX
The crosshatch area indicates invalid input
•
4-52
T4
T3
U
Port T outputs
Note 1.
M1
State
MITSUBISHI
.... ELECTRIC
~ VYXYYy\!\
MITSUBISHI MICROCOMPUTERS
M5884 7 -XXXSP
SINGLE-CHIP 4-BIT MICROCOMPUTER
DESCR IPTION
PIN CONFIGURATION (TOP VIEW)
The M58847-XXXSP is a single-chip 4-bit microcomputer
fabricated using p-channel aluminum gate ED-MaS tech-
06- I
nology. It is housed in a 40-pin shrink plastic molded DIL
package and provides 25 output lines, 4 input lines, 2
sensing lines and 1 interrupt input. Because of its low
OUTPUT PORT D
power consumption, it is ideal for consumer electronics
OUTPUT
PORT D
applications requiring many control signals.
00-
SUPPLY VOLTAGE
DETECTION INPUT Vz --+
FEATURES
•
•
RESET INPUT RES E T --+ 9
Basic machine instructions
52
Instruction execution time (for 1 word instructions
using a 400kHz clock frequency)
•
............
Memory capacity: ROM .......
Single -12V power supply
•
Subroutine nesting
Interrupt function ................ 1 factor, 1 level
•
Input (port K)
•
Output (ports D and P)
•
I nput/output (port S)
..................
8 ports
•
Sensing input (port T) ..................
2 ports
•
High withstanding voltage and large current output
•
•
SENSING INPUT
(~33V)
Voo
(~12V)
CLOCK INPUT
To --+ 14
27 --+ X OUT CLOCK OUTPUT
{ Tl--+15
INTERRUPT INT --+ 16
REQUEST INPUT
OUTPUT PORT P
P - 17
..................... 2 levels
........................
Vp
K3 --+ 13
128 words x 4 bits
•
{K~~: :~
2 --+ 12
2048 words x 9 bits
RAM ........
•
INPUT PORT K
15tLs
INPUT/OUTPUT
4 ports
PORT S
{SO .... 18
S1
....
(OV)Vss
................. 17 ports
OUTPUT PORT S
19
INPUT/OUTPUT
20l..-_ _ _ _---r--+-+S2
PORTS
Outline 40P4B
Built-in pull-down transistors (ports T, K, D, P, and S,
APPLICATIONS
mask option)
•
Built-in clock generator circuit
•
VTRs, TVs, cassette decks
Microwave
ovens, air conditioners, heaters, washing
machines, home sewing machines
BLOCK DIAGRAM
SENSING INPUT
RESET
,-----"-----.,
INPUT
To T1
RESET
PULL-DOWN SUPPLY
(OV)(~33V)(~12V)(OV)
CNVss
Vp
VDD
Vss
CLOCK
INPUT
XIN
CLOCK
OUTPUT
XOUT
•
Office'equipment, copying machines, medical equipment
•
Educational equipment, electronic games
INTERRUPT
REQUEST
INPUT
INT
SUPPLY VOLTAGE
DETECTION INPUT
Vz
r-------------------------.
RAM
128WORDS
X 4 BITS
ROM
2048 WORDS
X 9 BITS
OUTPUT
INPUT/OUTPUT
PORT SPORT S
• MITSUBISHI
' " ELECTRIC
4-53
II
MITSUBISHI MICROCOMPUTERS
M5884 7 -XXXSP
SINGLE-CHIP 4·BIT MICROCOMPUTER
PERFORMANCE SPECIFICATIONS
Performance
Parameter
Basic machine instructions
52
Instruction execution time
15!1s (l-word instructions using a clock frequency of 400 kHz)
Clock frequency
240 kHz - 400 kHz
2048 words x 9 bits
ROM
Memory capacity
RAM
128 words x 4 bits
Input
K
S
4 bits xl
Output
8 bits xl
Input
4 bits xl
Input/output ports
p
Output
1 bit xl
0
Output
1 bit x 16
T
Sensing input
1 bit x 2
Subroutine nesting
2 levels (including one level of interrupt)
Clock generator
Built-in (externally connected RC circuit or ceramic resonator)
I/O withstanding voltage
I/O chracteristics of ports
-33V
-
Port 0 output current
-15mA
-12V
Voo
Supply voltage
8 mA
Ports P and S output cu rrent
OV
Vss
Device structure
p-channel aluminum gate ED-MOS
Package
40-pin shrink plastic molded 01 L package
Power dissipation
10mW (typ)
PIN DESCRIPTIONS
Pin
Name
VOO
Supply voltage
VSS
Supply voltage
Vp
Pull-down voltage input
Vz
Input or
output
Function
Voo and VSS are the power supply pins_ Voo should be connected to -12V±1 0% and Vss should be grounded_
Vp is the pull-down supply voltage input for the pull-down transistors (mask options) for ports p. S. and 0_
Supply voltage
.
.
detection Input
In
RESET
Reset input
In
CNVSS
CNVss input
In
XIN
Clock input
In
This input pin is provided for use in detecting a drop in the supply voltage.
This pin is used to intialize the microcomputer. If it is held high for at least two machine cycles after Voo reaches
to within 10% of -12V. the reset condition is enabled.
This pin is not reserved for customer use but should be connected to Vss.
Tt>ese are the input and output pins for the built-in clock generator. A ceramic resonator element (240-400 kHz)
or RC circuit may be connected to these pins to provide the required oscillation stability_
XOUT
Clock output
Out
T1. To
Sensi ng input
In
Sensing input pin
K3- K O
Input port K
In
4-bit input port
S3-S0
I/O portS
In/out
S7-S4
Output port S
Out
p
Output port p
Out
015- 0 0
Output port D
Out
The individual bits of this 16-bit output port may be set and reset separately.
INT
Interrupt request input
In
This interrupt signal input pin triggers on the input signal edge,
4-54
S7-S4 and P comprise an output port
S3-S0 comprise an input/output port
• MITSUBISHI
..... ELECTRIC
MITSUBISHI MICROCOMPUTERS
M58847 -XXXSP
SINGLE-CHIP 4-BIT MICROCOMPUTER
BASIC FUNCTION BLOCKS
Program Memory (ROM)
The word addresses for the data RAM are specified by
This 2048 word x 9-bit ROM can be programmed with
machine instruction codes in accordance with the customer's specifications. It consists of 16 pages, each containing
an address range of 0""127.
The page is specified by the upper order 4 bits (PC H ) of
the program counter.
The address within a particular page is specified by the
lower order 7 bits which form a polynomial counter (PC L ).
When the last address is reached (127), the address wraps
around to the Oth address.
The BL instruction is used to branch to a different page
than the current page. While the program counter is in
reality a polynomial counter, a cross-assembly technique is
used to allow the programmer to think of this counter as a
normal pure binary counter, for ease in programming.
Page 0 and page 1 are special pages used for subroutine
calls. The single-word instruction BM can be used to call a
subroutine on page 0 from any arbitrary page. When the
BM instruction is executed, the SM flag is set and until any
of the B L, BM L, RT or RTS instructions are executed, the
Band BM instructions are used for functions differing from
their normal functions.
Until any of the above listed instructions is executed
after an BM instruction execution, the B instruction has the
effect of branching to the 1st page and the BM instruction
has the effect of branching to the Oth page. The flag SM is
reset when the BL, BML, RT, or RTS instruction is
executed.
Fig. 1 shows the ROM address map.
Program Counter (PC)
This counter is used to specify ROM addresses and the
sequence of read-out of instructions stored in ROM. The
upper 4 bits (PC H ) are used to specify the page in ROM and
the lower 7 bits (PC L ) of which are a polynomial counter
used to specify the address on the specified page.
Stack Registers (SK o , SK 1 )
means of the data pointer which consists of 1 bit of the
register Z, 2 bits of the register X and 4 bits of the register
Y. Fig. 2 shows the RAM address map. There are 8 files
(Fo""F7) consisting of 16 words of 4 bits, which are
convenient as a 16-digit register.
The specification for these file grimps is made by registers Z and X.
Data Pointer (DP)
wel~
This register is used to designate RAM addresses a.s
as
bit position for the output port D. The data pOinter IS a
7-bit register, the uppermost bit of which is register Z
which is used to specify the RAM file group, the central 2
bits of which form register X which is used to specify the
RAM file, and the lower 4 bits of which form register Y
which is used to specify the digit within the file. In
addition, when the register Z's bit is 1, register Y is used to
specify the bit position for the output port D.
4-bit Arithmetic Logic Unit (ALU)
This unit executes 4-bit arithmetic and logical operations
by means of a 4-bit adder and related logic circuitry.
Register A and Carry Flag (CY)
Register A is a 4-bit accumulator that constitutes the basis
for arithmetic operations. Data processing operations such
as arithmetic and logical operations, data transfer, exchange, conversion, and data input/output are executed by
means of this register. The carry flag CY is used to store
carry or overflow after execution of arithmetic and logical
operations by the arithmetic unit. The carry flag may also
be used as a 1-bit flag.
~ PCHr-~~~-.__~P_a_g_e_de_Si~gn_at_io_n~-,~~~~
p~ ...~
Bitdesignation 8 7 6 5 4 3 2 1 0 8 7 6 5 4 3 2 1 0 8 7
210876543210
c
°r-~++~~~~~rr~~r+++++++~~-r~-r-H
co
~r-~++~~~~~rr~~r+++++++~~~~H
W~~+'''''~~1-r""",r''TT'+",,~-rH
These registers are used to temporarily store the contents of
the PC while executing subroutines or interrupt programs
until the program returns to the main routine.
The stack registers are organized in 2 words of 11 bits,
allowing 2 levels of subroutine nesting.
~~~++~~~-H~'~~rr~++++++~~~~H
«
Fig. 1 ROM address map
Fde
.
[RegisterZ
deslgnatlonl Reg ister X
File name
Bit designation
Data Memory (RAM)
Th is 512-bit (128 words x 4 bits) RAM is used to store
both processing and control data. One RAM word consists
of 4 bits with bit manipulation possible over the entire
storage area. The 128 words are arranged in 2 file groups x
4 files x 16 digits x 4 bits.
•
F,
F,
F,
F,
I
F,
F.
32103210321032103210
3210
I
Fig. 2 RAM address map
MITSUBISHI
. . . . ~L~CTRIC
l'l--<:;<:;
II
MITSUBISHI MICROCOMPUTERS
M5884 7 -XXXSP
SINGLE-CHIP 4-BIT MICROCOMPUTER
Registers
a, E, and C
Register B is composed of 4 bits and can be used as a 4-bit
temporary storage register or for 8-bit data transfer in
conjunction with register A. Register E is an 8-bit register
which can be used for temporary data storage or as an
auxiliary register for input/output port S, and it also has
left shift capability. Register C is a 1-bit register, to which
the contents of the carry flag can be transferred.
It can
also be used to perform left shift when linked to
register E.
Interrupt Functions
An interrupt input has been provided to allow the
M58847-XXXSP to accept external interrupts. When the
input signal changes from low to high, an edge-sensing flag
is set, causing the interruption of the normally executed
program if the interrupt enable flag is set. When an interrupt
is received, the following things occur.
(1) The program counter and SM flag are saved on each
stack.
(2) The program counter is set to the Oth address on page 2.
interrupt is possible. The program counter, however, has a
two level stack, enabling subroutine nesting of one level
after an interrupt uses one of these levels.
The microcomputer can accept an interrupt request in
the following conditions.
When not executing a B, Bl, BM, BMl, lA, LXV, RT,
RTS, RTI, DI, or EI instruction or not executing a skip
operation and the interrupt enable flag is set.
Input/Output Ports
Ports T, K, S, D, and P may be provided with pull-down
transistors as a mask option. Fig. 3 shows the circuits for
the input/output ports.
In addition, the contents of the register A are decoded
to 8 bits by built-in 8 segment decoder and transferred to
register E or port S. The decoder function is fixed and not
available in special forms as a mask option. Table 1 shows
the decoder function.
::~-- ---, I~
(3) The SM flag and edge-sensing flag are reset.
(4) The interrupt enable flag is reset.
In the above state the program begins at page 2, address 0,
the first address of the interrupt program. The instruction
RTI is used to end the interrupt program and return the
processor to the main program flow.
Since the SM flag has a single-level stack, one level of
: TYP
:
IL _______
100k~2
..II
PULL-DOWN OPTION
VDD
VP
PORTS
S. D. P
PORTS T. K
Fig. 3 Input/output circuits
Table 1 Decoder function table
Register A
Port S output
Hexadecimal valut
A,
A2
A,
Ao
S,
S6
55
5,
5,
52
5,
50
0
0
0
0
0
L
L
H
H
H
H
H
H
1
0
0
0
1
L
L
L
L
L
H
H
L
I
I
2
Display
II
U
2
0
0
1
0
L
H
L
H
H
L
H
H
3
0
0
1
1
L
H
L
L
H
H
H
H
4
0
1
0
0
L
H
H
L
L
H
H
L
5
0
1
0
1
L
H
H
L
H
H
L
H
6
0
1
1
0
L
H
H
H
H
H
L
H
7
0
1
1
1
L
L
H
L
L
H
H
H
Il
8
1
0
0
0
L
H
H
H
H
H
H
H
8
9
1
0
0
1
L
H
H
L
H
H
H
H
3
Y
LI
5
I
g
A
1
0
1
0
L
H
L
H
H
H
L
L
B
1
0
1
1
H
L
L
L
L
L
L
L
C
1
1
0
0
L
H
H
H
H
L
L
H
E
D
1
1
0
1
L
L
H
H
H
L
L
H
I
L
E
1
1
1
0
L
H
L
L
L
L
L
L
-
F
1
1
1
1
L
L
L
L
L
L
L
L
Blank
456
• MITSUBISHI
.... ELECTRIC
0
-
MITSUBISHI MICROCOMPUTERS
MS884 7 -XXXSP
SINGLE-CHIP 4-BIT MICROCOMPUTER
Reset
I
The RESET input has been provided to enable initialization
of the microcomputer. If the input is kept high for at least
two machine cycles after the supply voltage V DD reaches
to within 10% of -12V, the microcomputer will be reset,
enabl ing the following states.
(1) The program counter is set to 0 (PC) +- 0
(2) Ports S, P and 0 are turned off (S) +- 0 (P) +- 0 (D)
M58847 - xxxSP
XIN
XOUT
28
27J
I
/1/1 A
vv
~-
~
+-
Fig. 5 External RC circuit
o
(3) Flag SM is reset
(SM) +- 0
(4) The edge-sensing flag is reset
(5) The interrupt enable flag is reset (INTE) +- 0
I
M58847-XXXSP
RESET
VDD
I~
a
M58847 - XXXSP
XIN
I
"9
29
1
XOUT
27
28'
~
Fig. 6 External ceramic resonator
I~
-~
I
Fig. 4 Power-on reset circuit
In addition, when the supply voltage V DD is in the range
-7V '" -13.2V and the V z input is driven high, an internal
transistor is turned on and the RESET pin is set to the level
of Vss. Even if the V z pin returns to low, the internal
transistor will remain turned on until the RESET pin is
driven high. By using this function it is possible to sense
temporary drops in the supply voltage to allow reset at
these times to return to normal operation.
M58847 - xxxSP
X'N
28[
XOUT
271
I
OPEN
.Jl.lUL
Fig.7 External clock circuit
Clock Generator Circuits
Documentation Required upon Ordering
A clock generator circuit has been built in to allow control
of the frequency by means of an externally connected RC
circuit or ceramic resonator. The choice of frequency
determining element is made at the time of purchase as a
mask option. Circuit examples are shown in Fig. 5"'7.
The following information should be provided when order-
Mask Options
•
•
•
•
Port
Port
Port
Port
T pull-down transistors
K pull-down transistors
D pull-down transistors
S pull-down transistors
•
Port P pull-down transistors
•
Oscillation conditions
ing a custom mask.
(1) M58847-XXXSP mask confirmation sheet
(2) ROM data
3 EPROM sets
(3) Port D pull-down transistors
On confirmation sheets
(4) Port S pull-down transistors
On confirmation sheets
On confirmation sheets
(5) Port P pull-down transistors
On confirmation sheets
(6) Port T pull-down transistors
On confirmation sheets
(7) Port K pull-down transistors
On confirmation sheets
(8) Oscillation conditions
• MITSUBISHI
"ELECTRIC
4-57
MITSUBISHI MICROCOMPUTERS
M5884 7 -XXXSP
SINGLE-CHIP 4-BIT MICROCOMPUTER
MACHINE INSTRUCTION~
fype of
Mnemonic
I~struc-
,-------- ~ a a
tlon
0, D,D,D,D, 0,0,0,0.
o
TAB'
TBA
TAY
o
o
TVA
o
1 01 1
1 001- 0 B 9
TEAB
0 B 5
0 B A
0 B 6
OBI
TEPA
010110000
OBO
8.!.
TXA
o
OF5
.~
TAX
l-r--;--
~
Description (,f operation
u::
(A)--(B)
x
(B)~(A)
x
(A)~(Y)
x
I
(y)~(A)
X
I
(E,-E,)~(B),\E,-E.)~(A),(C)-(CY)
(C)~(CY)
x
I
(E,-E.)~
X
I
(X)~(A,A.)
(z) ........ (A;)
1
8-segment decoder ~(A).
Transfers contents of register B to register A.
Transfers contents of register A to register B.
Transfers contents of register Y to register A..
Transfers contents of register A to register Y.
Transfers contents of registers A and B to register E, and the con~
tents of the carry flag to register C.
Decodes contents of register A In the 8·segment decoder and
transfers result to regIster E. The contents of the carry flag are
transferred to register
Transfers the first and second bits of the register A to register X,
(C)~(CY)
.~
*I
CO;d~~ons
Functions
~~~~ilon ~ ~
1 0 1 1 0 1 0 1
1 01 1 1010
101 1 01 10
010110001
~
ill
~ -i'j~..,...-------------r----,..>---"-------------------.,
Instruction code
1111
0101
all
complement of the third bit to register Z, and complerT'ent of the
(CY)~(A,)
o
1111
1001
OF9
I
1
(A,A.)~(X)
fourth bit to the cairY flag CY
Transfers the contents of register X to the first and second bits
of register A. complement of the contents of register Z to the third
bit of register A. and complement of the contents of the carry flag
X
(A,)~(Z)
a:
(A,)~(cy)
I - - - t - - - - t - - - - - - - - - - \ - - + _ _ +--+______________-+-_____+
Written
I
(X)~x. where.x= 0- 3
o 01yy yyxx 048
LXY X,Y
successively
(Y)~y. INhere.y= 0-15
t~
~,~,
__
~_!~~~~regi~~ ____._ _ _ _ _ _ ___I
Loads value of "x" into register X, and of "y" into Y. When LXY
is written successively, the first is executed and successive ones
are skipped.
Y2~
~
LZz
o
INY
o
DEY
0111010000E8
SADR j
o
0000
1 1 0 zOO C
I
X
Loads value of "z" into register Z.
(Y)~(Y)+1
(Y)=
a
X
(Y)~(Y)-1
(Y)=15
X
Increments contents of register Y by 1. Skips next instruction
when new contents of register Yare "0".
Decrements contents of register Y by 1. Skips next instruction
when new contents of register Yare "15"
1
(Z)~z.
I
1
1
I = a : specifies the Oth digi t of F4
1= 1 : specifies the Oth digit of F5
where z= 0,
1
-::
11100100
1 1 0 0
0 0 j j
OE4
0 C j
~__4-----__4-------------------~------+__~-+-I=--3--:~sp~e-ci-fie-s--th-e-O-th-d_i9_it_o_f_F7______~--------TAM j
0101000ji
oA
1
j
(A)~(M(DP»,
(X)~(X)
During the following instruction cycle only. the Oth digit of the
file soecified by the immediate field (in the range F4 to F71. The
contents of the data pointer remain unchanged.
X
I
1= 2 : specifies the Oth digit of F6
_______________________________________________________.~
II I,
X
(A)-(M(DP». (X)~(X) II I.
where.i = a - 3
X
Transfers the RAM contents addressed by the active DP to
register A. Register X is then "exclusive OR-ed" with the value
j in the instruction. and the result stored in register X.
Exchanges the contents of the RAiv·,. and register A. Contents of
X are then "exclusive OR-ed" with the value j and the result
stored in register X.
Exchanges the contents of the RAM and register A. Contents of
X are then "exclusive OR-ed" with the value j in the instruction,
and the result stored in register X. The contents of register Yare
decremented by 1, and when the result is 15 the next instruction
is skipped.
•
Exchange3 the contents of the RAM and register A. Contents of
X are then "exclusive OR-ed" with the value j in the instruction
and the result stored in register x. The contents of register Y
are incremented by 1. and when tne result meets with the marked
skip condition. the next instruction is skipped
wher8,j=O~-3
'"c
XAM j
o
1010 1 1 j j
o
1010
OAC
XAMD j
o
XAMI j
LAn
0
AM
I
1
t
S
10 j j
1
OA8
t
1010 01 j j
(Y)~(Y)-
1
OA4
t
1000
(X)~(X)II
(A)-(M(DP»,
where.i=
I,
(Y)=15
I
a-
3
(A)-(M(DP», (X)~(X)II i.
(Y)~(Y)+ 1
a- 3
(Y)=
a
where.l=
Written
successively
a -15
Loads the value n into register A. When LA is written consecutively the first is executed. and successive ones are skipped.
08n
1
(A)·-n. where. n=
1
(A)~(A)+(M(DP»
Adds the contents of the RAM to register A. The resu It is retained in register A. and the contents of flag CY are unaffected.
(A)~(A)+(M(DP»+(CY),
Adds the RAM contents addressed by tbe active DP and contents
of flag CY to register A. The result is stored in register A. and
the carry in the active flag CY.
0
1011
11 10
OBE
o
101 1
1 100
OBC
1
c
o
AMC
1
1
(CY)~Carry
'"
a
o
AMCS
o
1011
1101
OBD
1
I
(A)~(A)+(M(DP»+(CY).
(CY)~Carry
~
g.
An
o
sc
RC
SZC
CMA
(A)~(A)
a -15
1
0/
A.dds the contents of the RAM and flag CY to register A. The
result is stored in register A and the carry in the CY. but the
next instruction is skipped when a carry is produced.
X
Adds value n in the instruction to register A. The contents of
flag CY are unaffected and the next instruction is s~ipped if a
carry is not produced. except when n=6.
09n
1
000000110
0000 0101
00000 0010
010110111
006
005
002
OB7
I
1
SB j
00001
01 j
1
(MI(DP»~I.where,i=0-3
X
RB j
o
I
(Mi(DP»~O. where,I=0-3
X
SZB j
00001
1
(Mi(DP»=0?where,i=0-3
1001
o
OOj j
000101 j j
10j j
014
t
I
1
1
018
(CY)~
+n. where. n=
Carry= 1
A carry is not
produced and
=0
n~ 6
1
Sets active flag CY.
R8sets active flag CY.
Skips next instruction when contents of the active flag CY are 0 .
Stores complement of register A in register A.
(CY)~O
(CY)= a ?
(A)~(A)
(CY)= a
Sets the jth bit of the RAM addressed by the active DP (the bit
designated by the value j in the instruction).
Resets the jth bit of the RAM addressed by the active DP (the bit
designated by the value j in the instruction I.
(MI(DP» =0
X
Skips next instruction when the contents of the jth bit of the
RAM addressed by the active DP (the bit wh ich is designated by
the value j in the instruction) are O.
X
Skips next instruction when contents of register A are equal to
the RAM contents addressed by the active DP.
Skips next instructioll when the contents of register Yare equal
to the value y in the instruction.
t
SEAM
010111111
OBF
1
(M(DP»=(A)?
(M(DP))=(A)
SEY Y
00010
yyyy
02y
I
(Y)=y?, where.y=0-15
(Y)=y
B XY
1
yyyy
18y
2
(PCL)~16x+y,
lxxx
~
(PCH)~
X
(PCL)~16x+y,
BL pxy
0
1
00 I I p P P P
1 x x x y y y Y
03 p
18 Y
2
3
(PCH)~p.
Jumps to address xy on page 1 when executed, provided that
none of instructions RT, RTS, BL or BML. was executed after
execution of instruction BM.
where, (SM)= 1
(SM)~ a
X I Jumps to address xy of page p.
(PCL)~16x+y
i
t
4-58
Jumps to address xy of the current page.
where. (SM)= a
I
• MITSUBISHI
..... ELECTRIC
MITSUBISHI MICROCOMPUTERS
M5884 7 -XXXSP
SINGLE-CHIP 4-BIT MICROCOMPUTER
;~
Instruction code
fype of
instruction
Mnemonic
BM xy
0 8 0 10 6 0 5 0 4 0 3 0 2 0 10 0
1
o
x x x
y y y y
0
16mal
notation
Skip
conditions
Functions
a
Z
2
1 x Y
>-
u
g>
Description of operation
u::
(SK,)~(SKo)~(PC),
where,(SM)=O
Calls for the subroutine starting at address xy on page O.
(PCH)~O, (PC,)~16x+y, (SM)~l
~
'"
(PCH)~O
C
j
(PC,)~16x+y,
BML pxy
E
001 1
P P P P
03p
Oxxx y y y y
1 x Y
RT
RTS
0
0
0001
0001
1110
01 F
01 E
EI
01
RTI
0
0
0
0000 101 1
0000 1010
0001 1101
OOB
OOA
010
SO
0
0000 1111
OOF
1
2
3
~
i
~
1111
(SK,)~(SKo)~(PC)
(PCH)~P,
~
~ ~
8'.'3
a':
0
1
(PC)~(
SKo )~( SK,),
(SM)~O
(PC)~(SKo)~(SK,),
(SM)~O
1
(INTE)~
1
Mise
DP
pC H
PC,
PC
SKo
(SM)~(SMo)
(D(Y))
+-'-
1 , where, (Z)= 1
~
0, where, (Z)= 1
RO
0
0000 1110
OOE
1
(D(Y))
0
101 1
001 1
OB3
1
(S,-S.)~(E, -E.)~(B),
OSPA
0
101 1
0010
OB2
1
(S3-So)~(E3-Eo)~(
0
1111 0010
OF2
1
(S,-So)~(E,-Eo),
0
0000 1000
008
1
(En)~(En-1),
lAS
IAK
SZTO
SZT1
CLOS
0
0
0
0
0
1111
1000
1000
0000 0001
0000 0100
0000 0111
OF8
OB8
1
1
(A).~(S3
004
007
1
(D)~O,
NOP
0
0000 0000
000
1
(PC)~(PC)+
A)
decoder
X
X
X
Sets interrupt flag INTE to enable interrupts.
Resets interrupt flag I NTE to disable interrupts.
Returns from interrupt routine to main routine. The internal
subroutine mode flag is restored to the value held immediately
before the interrupt.
X
Sets the bit of port D, that is designated by register Y, when the
contents of register Z are 1.
Resets the bit of port D, that is designated by register Y, when
the contents of register Z are 1.
Output contents of registers A and B to port S.. and the contents
of the carry flag to port P
Decodes contents of register A by 8 segment decoder and the
X
result
(P)~(C)
X
-So)
To= 0
T,= 0
(S)~O,
Symbol
SK,
CY
yyyy
P
Returns to the main routine from the subroutine.
Returns to the main routine from the subroutine, and unconditionally skips the next instruction.
(Eo)~(C)~(CY)
To'" 0 ?
T,= 0 ?
Contents
X
X
X
(A)~(K3-Ko)
4-bit register (accumulator)
4-bit register
l-bit register
S-bit register
2-bit register
4-bit register
l-bit register
7-bit dat~ pointer,combination,of registers, X Vand Z
The high-order four bits of the proqram counter.
The low-order seven bits of the program counter.
l1-bit program counter, combination of PC H and PCl
ll-bi t stack register
Calls for the subroutine starting at address xy of page p.
(P)~(C)~(CY)
OSE
001
x
X
(P)~(C)~
(S,-So)~(E,-Eo )~8-segment
SHFT
Symbol
B
C
1
(PC)~(SKo)~(SK,),
OSAB
101 1
Unconditional
skip
(INTE)~O
~(A),
Jumps to address xy of page 0 provided that none of instructions
RT. RTS, BL or BML, was executed after the execution.of
instruction. BM
(SM)~O
2
(CY),
"""
(PC,)~16x+y,
2
1
x
where, (SM)= 1
(P)~O
I~jx
x
1
Contents
ll-bit stack register
l-bit carry flag
2-bit binary variable
4-bit binary variable
l-bi! binarY variable
4-bit binary constant
2-bit binary constant
16-bit port
4-bit port
S-bit port
l-bit port
Shows direction of data flow
• MITSUBISHI
"'ELECTRIC
IS
output to port S. and output the contents of tne carry
flag to port P
Outputs contents of regISters E and C to ports Sand P.
Links register E and register C and shifts left. The contents of
register C are shifted into the least significant bit of register E
and the contents of the flag CY are shifted into register C. The
most significant bit of register E is lost.
Transfers the 4 lower order bits of port S to register A.
Transfers the 4 bits of port K to register A.
Skips the next instruction if the sensing input To is low.
Skips the next instruction if the sensing input T 1 is low.
Clears ports D. Sand P
No operation.
Symbol
'f
xy
pxy
C
+
SM
SMo
INTE
Contents
Indicates contents of the register, memory, etc.
Exclusive OR
Negation
Indicates flag is unaffected by instruction execution
Label used to indicate the address xxxyyyy
Label usedte indicat, theaddressxxxyyyyof page pppp_
Hexadecimal number C + binary number x.
l-bit subroutine mode flag
l-bit subroutine mode flag save register
Interrupt enable flag
4-59
II
MITSUBISHI MICROCOMPUTERS
MS884 7 -XXXSP
SINGLE-CHIP 4-BIT MICROCOMPUTER
LIST OF INSTRUCTION CODES
~
-
0 0000
D.
D~ Hexadecimal
notation a a
Do \
0000
0001
0010
00.11
0100
0101
0110
0111
1000
1001
10~0
1011
1100
a
1
2
3
4
5
6
7
8
9
A
B
C
NOP
SZTO
SZC
-
SZTl
RC
SC
CLOS
SHFT
a
1
1111
F
a
3
SEY
BL
a
a
BML
SB
SEY
BL
1
1
BML
SB
SEY
BL
2
2
BML
SB
SEY
BL
3
3
BML
RB
SEY
BL
a
4
BML
RB
SEY
BL
1
5
BML
RB
SEY
BL
2
6
BML
RB
SEY
BL
3
7
BML
SZB
SEY
BL
0
8
BML
SZB
SEY
BL
1
9
BML
SZB
SEY
BL
2
10
BML
SZB
SEY
BL
3
11
BML
a
4
LXY
0,
a
LXY
2,
0
LXY
3,
a
LXY
0,
1
LXY
1,
1
LXY
2,
1
LXY
3,
1
LXY
0,
2
LXY
5
LXY
a a,
LXY
1,
a
4
LXY
1,
4
LXY
2 ,
4
LXY
3 ,
4
LXY
o,
5
LXY
1,
5
LXY
2 ,
5
LXY
3 ,
5
LXY
a,
6
LXY
a
6
LXY
0,
8
7
LXY
0,
12
LXY
LXY
1,
1,
8
LXY
2,
8
LXY
3,
8
LXY
0,
9
12
LXY
2,
12
LXY
3,
12
LXY
0,
13
LXY
LXY
1,
1,
9
LXY
2,
9
LXY
3,
9
LXY
0,
10
1,
2
LXY
1,
6
13
LXY
2,
13
LXY
3,
13
LXY
0,
14
LXY
LXY
1,
1,
LXY
10
EI
LZ
a
-
RTI
RO
SD
RTS
SEY
BL
12
BML
SEY
BL
13
BML
SEY
BL
14
BML
SEY
BL
15
BML
2,
2
LXY
3,
2
LXY
0,
3
LXY
1,
3
LXY
2,
3
LXY
2 ,
6
LXY
LXY
3 ,
6
LXY
o,
7
LXY
1,
7
LXY
2 ,
7
LXY
2,
10
LXY
3,
10
LXY
0,
11
a
8
1001
a
9
a
1010
a
A
LA
A
TAM
a
a
a
LA
A
TAM
1
1
1
LA
A
TAM
2
2
2
LA
A
TAM
3
3
3
LA
A
XAMI
4
4
LA
A
5
5
LA
A
XAMI
6
6
2
LA
A
XAMI
7
7
3
LA
A
XAMO
8
8
0
LA
A
XAMO
9
9
1
LA
A
XAMO
10
10
2
LA
A
XAMO
11
11
3
LA
A
XAM
12
12
0
a
XAMI
14
LXY
2,
14
LXY
3,
14
LXY
0,
15
LXY
LXY
LA
A
XAM
1,
13
13
1
LA
A
XAM
14
14
2
LA
A
XAM
15
15
3
11
LXY
2,
11
LXY
15
LXY
2,
15
LXY
RT
3,
3
3 ,
7
3,
11
3,
15
MITSUBISHI
.... ELECTRIC
a
1011
a
B
TEPA
a
1100
a
c
SACR
a
a
1101
a
D
a
1110
a
E
a
1 0000
1111
a
F
1 1000
I
I
1 0111
11111
10-17
18-1 F
-
-
-
BM
B
-
-
-
BM
B
-
-
BM
B
-
BM
B
-
BM
B
BM
B
SADR
TEAB
1
SADR
OSPA
OSE
2
SADR
OSAB
3
-
-
TBA
-
-
-
TYA
---
-
-
-
BM
B
CMA
-
---
-
-
BM
B
IAK
-
-
lAS
BM
B
TAB
-
-
-
TAX
BM
B
TAY
-
-
-
-
BM
B
-
-
-
--
BM
B
AMC
-
-
--
-
BM
B
AMCS
-
-
-
-
BM
B
-
-
-
BM
B
-
-
-
BM
B
-
INY
TXA
1
1,
•
4-60
a
a
01
0
E
2
SB
1
1110
a
1000
--
LZ
1101
a 0001 a 0010 a 0011 a 0100 a 0101 a 0110 a 0111 a
-
AM
SEAM
--
-
DEY
MITSUBISHI MICROCOMPUTERS
MS884 7 -XXXSP
SINGLE-CHIP 4-BIT MICROCOMPUTER
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Conditions
Limits
Unit
VOO
Supply voltage
0 3- -18
V
VI
Input vo Itage, Port Sand VP
0.3- -35
V
VI
I nput voltage, other than port S
0.3--18
V
Vo
Output voltage, ports S, P, and 0
0.3- -35
V
Vo
Output voltage, other than ports S, P and 0
0.3--18
Pd
Power dissipation
With respect to VSS (output transistors cutoff)
(Note 1)
V
mW
1000
Ta=25°C
Topr
Operating temperature
-10-70
°C
Tstg
Storage temperature
-40-125
°C
Note 1. VII¢I= 1.1--35V for use of ceramic resonater
RECOMMENDED OPERATING CONDITIONS (Ta ~-10-70°C, unless otherwise noted)
Limits
Symbol
Parameter
Unit
Min
Nom
Max
-10.8
-12
-13.2
Voo
Supply voltage
VSS
Supply voltage
VIH
High-level input voltage, ports T and K and RESET inputs
-1.5
0
V
VIH
High-level input voltage, port S, I NT and V z inputs
-0.4
0
V
VIH(q,)
High-level clock input voltage
-0.9
0
V
VIL
Low-level input voltage, ports T and K and RESET inputs
Voo
-6
V
VIL
Low-level input voltage, INT and Vz inputs
Voo
-4
V
VIL
Low-level input voltage, port S input
-33
-4
V
VIL(q,)
Low-level clock input voltage for external clock
Voo
Voo+2
V
VOL
Low-level output voltage, Ports S, P and 0
-33
0
V
f (q,)
Internal clock oscillation frequency
ELECTRICAL CHARACTERISTICS
-1.0
240
(Voo
~ -12V±10%, Vss
400
300
= OV, f( 0:
package. It has a 4096-word by 10-bit mask-programmable
ROM and a 32-word by 4-bit RAM. RAM capacity can be
0,
00
connecting generally available CMOS RAMs.
A,
(f)
Ao
A2
A3
The device is designed for application where the low
power dissipation of CMOS is essential.
A.
As
EVT
EVA
¢
FEATURES
•
Basic machine instructions .................... 92
•
Basic instruction execution time
x
x
A6
A1
As
(at 455kHz clock frequency) ................ 8.8J,ls
A9
AlO
Large memory capacity:
ROM ..................... 4096-word x 10-bit
GND
Internal RAM
0: 0: 0: 0:
02
expanded to as much as 4096 words by 4 bits by directly
•
a:
X
1)
II
A"
NC
Do
................. 32-word x 4-bit
"
0
External RAM .......... 4906-word x 4-bit (max)
•
•
Single 5V power supply
Saving of last data pointer ................. 4-level
•
Subroutine nesting ...................... l2-level
•
Internal timer:
•
•
Timer 1 ............... 14-bit
4-bit
Timer 2
I nternal event-counter ..................... 4-bit
I/O port for external RAMs (all three-state)
Address (port A) ...................... 12-bit
ooog~~ §JSJ~ :)5~:)~
- - wx
0:
Package Outline 72P2
•
Output ports (port S, port T) ............. 8-bit x 2
•
Output port
•
Event-counter input (port ECI
•
I nterrupt function
(priority interrupt type) ............ 4-factor, l-Ievel
Control signals (R/W, 00) ................ 2-bit
Data I/O (port D)
...................... 4-bit
•
General-purpose registers .................. 32-bit
•
I/O port (port Q) ......................... 8-bit
(port U, three-state output) ..... 4-bit
l-bit
APPLICATIONS
•
Electronic cash registers, electronic calculators (with
printer and/or programmable)
•
I/O port (port R) ...................... 4-bit x 2
•
Office machines, intelligent terminals, data terminals
•
I/O port (serial data port)
•
Sewing machines, knitting machines, etc.
.................. 2-bit
BLOCK
----~--~
ROM
4096 WORDS X
.---------1 ADDRESS
10 BITS
I
DATA
I
I
~~~~~-,--I
I
EC
RESET
RESET
INPUT
~
INTERRUPT
REQUEST
INPUTS
EVENT COUNTER INPUT
INPUT/OUTPUT
PORT Q
• MITSUBISHI
"ELECTRIC
INPUT/OUTPUT
PORT R
OUTPUT
PORT S
OUTPUT PORT T
5-3
MITSUBISHI LSls
M58494-XXXP
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
Outline Specifications of M58494-XXXP
Performance
Item
Number of basic instructions
92
Execution time of basic instructions
a. a,us (at Vee = 5V, f = 455kHz)
Clock frequency
100-455kHz
Memory capacity
Input/output port
for external RAM
ROM
4096 words X 10 bits
RAM (built·in)
32 words X 4 bits
RAM (external)
4095 words X 4 bits (max.)
Address (port A)
12 bits x 1 (3 states)
Control signal (port 00 and R/W)
2 bits (3 states)
Data bus (port D)
4 bits x 1 (3 states)
Input
8 bits xl
Q
Output
8 bits xl
Input
4 bits x 2
R
Input/output port
Output
8 bits xl
S
Output
8 bits xl
T
Output
8 bits xl
DATA
Serial data
1 oit (input/output port)
eLK
Synchronizing pulse
1 bit (input/output port)
U
Output
4 bits x 1 (3-state)
EC
Input
1 bit
Subroutine nesting
12 levels
Interrupt request
4 factors 1 level
Saving of data pointer
4 levels
Clock generation circuit
Ports input/output
Built-in (oscillation reference element is outside)
Absolute
maximL~m
rating voltage
Vee
characteristics
Input/output characterstics
Interchangeable with CMOS logic series
Power supply voltage
Vee
Vss
5V (nominal)
OV
Element structure
CMOS
Package
72-pin plastic molded flat package
Power dissipation
5 mW (at Vee = 5V, f = 455kHz)
5-4
• MITSUBISHI
"ELECTRIC
MITSUBISHI LSls
MS8494-XXXP
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
PIN DESCRIPTIONS
Pin
Name
Input or
output
At reset
Function
Incorporates the clock oscillat;on circuit, for setting of the oscillation frequency. The oscillation
Source oscillation
Input
X!N
clock input
t----+----------+---~--------1
reference device such as a ceramic filter for IF is connected between XIN and XOUT· When an
external clock is used, connect the clock oscillation source to the XIN pin and leave the XOUT
Source oscillation
Output
XOUT
pin open.
clock output
Resets the program counter PC and mode registers, and performs the reset initiation of the related
RESET
Reset signal
Input
input ports and output ports. For input/output ports, refer to the column for "At reset" of this
table.
INTA
Interrupt request signal A
Input
Disable
t-----t-----------+---+--------i
INTB
Interrupt request signal B
Input
EO
Event counter input
Input
Disable
Input signals for interrupt request. Request is accepted on the rising edge of the signal. Besides
these external input signals, the ;nterrupt requests. T from timer 2/event counter are also received
in the relative order RESET> INTA > INT T > INTs. Since the interrupt requests are held a:
each latch, there will be none undetected.
The input signal for the event counter, which program 2° -
:t
events of the event mode. This
value is set as an initial value and countdown starts from this value to reach F l6 , which then
generates interrupt request signal iNT T.
I----t------+---+--------+----------t
The address signal for main memory (RAM) externally connected, in the form of a 3-state output.
At MM mode where external memory is used the data of the data pointer DP is read out directly.
In SM mode where internal memory (RAM) is used, the data of the data pointer Y immediately
Ao-A"
Address output port A
Output
Floating
0 0- 0 3
Data input/output port 0
Input/
output
Floating
00
External RAM read signal
Output
Floating
R/W
External RAM write signal
Output
Floating
The output port is 3-state and the write signal generated at the data write cycle is in the externally connected main memory (RAM). During a write cycle, it is automatically set to low-level.
Output port U
Output
Floating
data content of register B, and the data of register A is output. The output setting of port U,
however, is made either by instruction SU unconditionally or by the instruction TPRA or TPRN,
before switching to MM mode is transferred to the auxiliary latch (4 bits) prior to read-out.
However, the lower S bits of the address signal (A o-A 7 ) are not affected by this mode, since data
pointers X and Z are not related to latch operation.
A 3-state input/output port to execute data transfer in 4-bit· units to/from an externally connected
main mell10ry (RAM). Switching of input-output is made automatically by instruction.
The output port is 3·state and the read signal generated at the data input cycle is in the externally connected main memory(RAM). During a read cycle, it becomes automatically'set to low-level.
The output port enables 3-state setting per 1-bit unit. The 3-state condition is modified by the
UO-U3
which transfers the data of the general-purpose register to ports Q, R, Sand T.
The input/output port for S-bit data transfer to/from register Q. Register Q enables data transfer
QO-Q7
Input/output port Q
Input/
output
between register A and register B. By instruction aPI, this port also functions to load the value
(S·bit) of the immediate field of the ROM to register Q. Port Q data can be transferred to re-
Input
gisters A and B as an input signal of S bits.
The input/output port for S-bit data transfer to/from register R. Register R enables data transfer
Ro-R7
Input/output port R
Input/
output
between register A and register B. By instruction aPI, this port also functions to load the value
Input
(S-bit) of the data field of the ROM to register R. When port R is used as the input signal of a
4-bit unit, the data, 4 bits each can be transferred to register B.
The output port that enables S-bit data transfer to/from register S. Register S enables data transfer
SO-S7
Output port S
Output
Low-level
between register A and register B. By instruction OPI, this port also functions to load the value
(S-bit) of the data field of the ROM to register S.
The output port for S-bit data transfer to register S. Register T enables data transfer between
TO-T7
Output port T
Output
Low-level
register A and register B. By instruction OPI, this also functions to load the value (S-bit) of the
immediate field of the ROMt& register T.
DATA
Serial data port
Input/
output
Floating
The input/output port normally is floating to handle the serial data of the 32-bit general-purpose
register. At output mode data of the least significant bit of the general purpose register (the least
significant bit of register T) is read out, and at the input mode, the input is to the most significant
bit of the general-purpose register (the most significant bit of register 0).
OLK
Serial data shift clock
signal
Input/
output
The input/output port is normally floating to generate a shift clock pulse synchronized with the
above serial data port. At output mode a shift clock pulse synchronized with the data transmisFloating
sion is generated and at the input mode, a shift pulse synchronized with the rate of data receiving
is applied.
• MITSUBISHI
.... ELECTRIC
5-5
II
MITSUBISHI LSls
M58494-XXXP
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
BASIC FUNCTIONAL BLOCKS AND THEIR
OPERATIONS
Program Memory ROM
The ROM stores 32-pages by 128 words of program and its
addressing is performed by a program counter. The program
counter consists of a 7-bit binary sequential counter and a
5-bit page register.
Program Counter PC
The ROM is composed of 32 pages of 128 words, and when
program execution completes instruction at address 127,
the binary counter is set to 0 and the next page is
automatically incremented in the page-designation register.
The 12-bit contents of the program counter PC can be
saved for up to 12 levels in the fixed stack area of the
external main memory (RAM)_ In the execution of instructions BM and BMA, control can be returned to a former
routine by storing the contents of the program counter
before branching, in the execution of instructions RT, RTS,
and RTI.
Register P
In the page register, the contents of register P are loaded by
instructions BL, BA, BM and BMA. Instruction BMAB
branches unconditionally to the address derived by using
the contents of register A for the low-order 4-bits of the
12-bit PC, those of register B for the middle 4-bits, and
those of the upper 4-bits of the 5-bit register P for the
upper 4-bits, and then executes the instruction OPI of the
branch, and simultaneously returns automatically.
thus incrementing the basic external
organization of 256 x 4-bit words.
minimum RAM
Data Pointer DP
This is a register of 12 bits addressing memory, being
composed of registers X, Y, and Z, having 4 bits each.
Register X address 16 files, each of which comprises 16
words. Register Y address data of 16 files (a file comprises
16 words). Register Z permits address specification such
that data memory may be extended up to maximum of 16
sets of 4096 words by 4 bits, where one unit comprises 16
files (256 words by 4 bits).
Since the address of the external main memory (4096
words by 4 bits maximum) and the internal scratch-pad
memory (32 words by 4 bits) are designated identically, the
external main memory is selected by instruction MM, and
the internal scratch-pad memory by instruction SM.
The contents of OP can be saved for up to 4 levels in the
fixed stack region of the external main memory. This
pointer is saved during the execution of instruction SOP,
and is restored by instruction LOP_
When the data pointer stack is not used, the entire
stack may be used as a program counter stack_
~:~
Register Y
File deSignation
0
1
2
3
4
5
7
6
8
A B C 0
9
E F
PCl PCM PC,
0
1
2
Stack Pointer SP
A stack of 12 levels is provided for saving of the program
counter PC in the fixed address area within the external
main memory (RAM), and the contents of the stack pointer
are used during addressing. The contents of the stack
pointer are incremented by an interruption or in the
execution of instructions BM and BMA, and are decremented in the execution of instructions RT, RTS and RTI.
c
Qj
~
Q
5
'c"
6
2'
if)
OJ
if)
3
4
I
N
-"'u
'"
7
if)
"D
if)
if)
OJ
"D
"D
«
8
U
I
I
Q.
9
A
B
I
C
Y
0
Data Memory RAM
E
The internal RAM is used to store data in the form of two
files each consisting of 16 words by 4 bits_ The external
RAM can be expanded up to 4096 words by 4 bits. These
addresses are designated by a 12-bit data pointer. The
contents of the data pointer can be saved for up to 4 levels
in the stack region (fixed region in the external RAMs) by
execution of a special instruction. The external RAM can
be easily expanded without any extra interface circuits by
connecting a 12-bit address signal, the 2-bit RAM control
signal and the 4-bit data input/output signal. These signals
can address external RAMs for up to 4096 x 4-bit words,
5
6
X
z
1
J
F
Fig. 1 External basic main memory (2
and RAM map
= 0)
Table 1 Address designation of data pointer stack
Value' of data field during execution
of Instructions SOP and LOP
Stack OP
(file deSignated
by register Y )
11
10
0
0
C
0
1
0
1
0
E
1
1
F
• MITSUBISHI
"'ELECTRIC
MITSUBISHI LSls
M58494-XXXP
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
Accumulator (Register A), Carry Flag CY
Instruction OPI loads one of the four general-purpose
registers selected by the input/outptJt address N with the
value (8 bits) of the data field. The input/output address N
is latched with the contents of the lower 2 bits of the data
field in the execution of the instructions SMAB, TNAB,
TABN, TPRN and TRPN and determines the register which
loads data in the execution of the instruction OPI.
When the general-purpose registers are used as a single
32-bit shift register, four kinds of modes as shown in Table
3 can be set by instruction SMR1.
Register A is an accumulator forming the central unit of a
4-bit-wide microcomputer. Data processing operations such
as arithmetic, data transfer, data exchange, data conversion,
input/output, etc. are executed principally with this register.
The carry flag CY stores the carry or borrow from the
most significant bit of the arithmetic unit in the execution
of specific arithmetic instructions, and is available for
multipurpose uses as a one-bit flag.
Auxiliary Register (Register B)
Mode Register
Register B is composed of four bits. It is employed for bit
operating functions, temporary memory of four-bit data
and transfer of eight-bit data when coupled with register A,
etc.
The mode register
Four-Bit Arithmetic Logic Unit (ALU)
This unit carries out four-bit arithmetic and logical functions, and is composed of a four-bit adder and a logic
circuit associated with it. It carries out addition, complement conversion, logic arithmetic comparison, arithmetic
comparison, bit processing, etc.
I nterrupt Function
This microcomputer has a hardware interrupt function for
four conditions by one-level. The interrupt requests comprise: the RESET signal; the interrupt request signals I NT A
and I NT B as external signals; and the interrupt request
signal INT T by the internal event counter.
The fixed addresses to be jumped to and the priority
order of four factors in the interrupt request are defined as
follows:
(1) In case of by reset signal RESET page 0, address 0
(2) In case of interrupt signal I NT A page 0, address 2
(3) In case of interrupt signal INT T page 0, address 8
(4) In case of interrupt signal INT B page 0, address 4
A RESET signal restores the hardware to the initial
state, independent of any current instruction.
In an interrupt enable state, the interrupt is accepted at
the rising edge of interrupt request signals INT A and INT B.
When an interruption is requested in an interrupt disable
state, the interrupt is not executed. If the interrupt disable
state is removed thereafter and a corresponding interrupt
~mable instruction is executed, the interrupt routine will be
These general-purpose registers comprise a set of four 8-bit
shift registers. When using combinations of functions such
as serial input, serial output, parallel input and parallel
output, by properly selected instructions, they are employed for data transfer between register A and register B,
data transfer between output ports or input/output ports,
data storage of the data field of the ROM value (8 bits),
transmission of internal serial data, receiving of external
serial data, etc.
Table 2 Relationship between input/output address
N and general-purpose registers
I--
Immediate data N In execution of the
instructions BMAB TNAB TPRN and TRPN
Generalpurpose
register to
be selected
N
11
10
0
0
0
Register Q
1
0
1
Register R
2
1
0
Register S
3
1
1
Register T
composed of 8 bits, and can select
5.
General-Purpose Registers 0, R, S, and T
Input!output
address
~s
operation modes and functions, etc. of the associated input
port or output port by setting or resetting the mode flag
corresponding to a bit in register A.
The mode setting by the instruction SM R is shown in
Table 4.
The mode setting by instruction SMRl is shown in Table
Table 3 Mode setting by instruction SMR 1; when the general-purpose registers are employed as a 32-bit
shift register
Mode flag
I
SDM
0
0
1
1
I
RVM
0
1
0
1
DATA pin
ClK pin
Shift data input
ISST.
I
Shift clock pulse
Transmission receiving
RST
1ST
Input
Output
Output
Output
Floating
Input (rising edge trigger)
Output (gernated by timer 2)
Output (generated by shift instruction)
Immediate field data
o input independent of
executable instruction
DA T A pin output
Immediate field data
DAT A pin output
Immediate field data
DATA pin output
Instructions SST. RST 1ST
ClK input
Instructions SST. RST, 1ST
Instructions SST, RST, 1ST
Receiving (only in instruction 1ST)
Transmission
Transmission
Transmission
• MITSUBISHI
"ELECTRIC
5-7
II
MITSUBISHI LSls
MS8494-XXXP
SINGLE·CHIP 4·BIT CMOS MICROCOMPUTER
executed immediately because the interrupt request has
of the highest priority routine. The interrupt request of
been held in the latch. The current interrupt request, held
lower priority order is held in the corresponding latch in an
in a latch during the interrupt disable state, is reset by the
interrupt disable state. When the interrupt disable state is
removed by the interrupt enable instruction (after comple-
interrupt disable instruction.
When two and more interrupt requests of four factors
occur simultaneously, the interrupt processing is by order
tion of the interrupt process of upper priority order), the
interrupt request of next lower priority is initiated.
Table 4 SMR mode setting
Bits of register A
Mode flag (contents of register
A are stored)
AO
IMQ
A,
LCD
A2
A3
Mode flag at reset
Function
Status
0
Port Q is used as an 8-bit input port
1
Port Q is used as an 8-bit output port
0
0
For output port U. only instruction cat set port U.
1
For output port U, instructions TPRN and TPRA for port Q, R, Sand T can
also set port U.
0
Port R 1 is used as a 4-bit input port
1
Port R 1 is used as a 4-bit output port
IMAl
a
Port R2 is used as a 4-bit input port
1
Port Rz is used as a 4-bit output port
IMA2
0
0
a
Table 5 SMR 1 mode setting
Bits of register A
Mode flag (contents of register
A are stored)
Ao
TMM
A,
Status
0
Event mode, event counter is used with EC input.
1
Timer mode, event counter is used in combination with timer 2.
0
All signals (A!1-Ao, 0 3 -0 0 , 00 and R/W) for external main memory,
(RAM) are put in floating.
1
All signals (All '-A o , D3 -Do. 00 and R/W) for external main memory
(RAM) are activated.
0
AVM
1
0
A3
0
SF
0
A2
Mode flag at reset
Function
SDM
When the general-purpose registers are used
8S
a 32-bit shift register,
0
functions of transmission/reoeiving, terminals DATA and ClK are employed
properly by RVM, SOM flags. For further details, refer to explanation of the
0
general-purpose register.
1
Timers and Event Counter
TIM~R 1
This block is composed of a 14-bit timer 1, a 4-bit timer 2
X OUT
and a 4-bit event counter.
-1
Timer 1 is a standard timer that continuously counts the
H
TMM(4)
t4
H
TMH(5)
f4
h
'r
1
REGISTER B (4) REGISTER A (4)
CAR RY FLAG CY
frequency XIN, divided by fourteen. The timer performs
accurate counting and the period is given by the following
TMd5)
Fig. 2 Outline of timer 1 configuration
RTM clears the contents of timer 1 and resets it to O.
formula:
(Fundamental output frequency XIN) x
s
X 24 (TM M ) x 2 (TMH) = cycle time of
timer 1
2 s (TML)
By the continuous use of instructions TATM and TBTM,
Timer 2 is composed of a 4-bit counter and a 4'-bit
latch. The contents of register A are stored as the starting
value in the latch and the counter by an STM instruction,
whereupon counting down starts in synchronization with
the contents of TMM are stored in register B, the con-
each machine cycle. When the contents of the counter
tents of the lower 4 bits of TMH in register A, and the
become F during countdown, the pre-programmed starting
high-order bit of TMH in carry flag CY, respectively.
value is restored in the counter from the latch.
The contents of timer 1 can be accessed. Instruction
5-8
• MITSUBISHI
.... ELECTRIC
MITSUBISHI LSls
M58494-XXXP
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
(1) Timer mode: When TMM = 1 is set by the
instruction SMR1
EVENT COUNTER
TIMER 2
INTERRUPT
REQUEST
SIGNAL INTT
SYSTEM CLOCK
(MACHINE CYCLE)
Reset Function
Applying a low-level input to the RESET input pin for
3
machine cycles or more cause~ the reset state. Power-on
reset is provided by such circuit as shown in Fig. 4.
M58494- XXXP
4
REGISTER A
(2) Event mode: When TMM = 0 is set by the
instruction
RESET
~f
SM R 1
EVENT COUNTER
EC INPUT
~
-I
~
EVC(4)
I
-
Vee
£;129(65)
INTERRUPT REQUEST
~SIGNALINTT
f
II
REGISTER A
Fig.3 Outline configuration of timer 2 and event
counter
Fig. 4 Power-on reset circuit
Clock Generation Circuit
The cycle period of timer 2 is given by the following
formula:
Machine cycle x [1 + (20~24)]
Where the timer mode is set by SMR1 instruction, timer
2 is connected to the event counter. Every time the contents of timer 2 become F the event counter counts down
once. For the event counter, the contents of register A
can be stored in the counter and used as a starting value by
using instruction SEC.
When the event mode is set using instruction SMR1, the
event counter is counted down by sensing the rising edge
of external event counter input EC.
In both timer mode and event mode, the event counter
is counted down from a starting value, and an interrupt
request signal is generated when the contents become F.
The time necessary for I NTT generation from the starting value is given by the following formulas:
Timer mode
Machine cycle x [1 + (2°"'2 4 )] X (2°"'2 4 )
Event mode
EC input period x (2°"'2 4 )
Clock pulses are easily generated by connecting an external
IF ceramic filter between the pins X IN and X OUT ' An
example of such as circuit is shown in Fig. 5. If the clock
signal is to be supplied from an external source, the clock
source should be connected to pin X IN , leaving the X OUT
pin open. An example of such circuit is shown in Fig. 6.
M58494-XXXP
=
Fig. 5 External oscillation element connections
M58494-XXXP
Fig. 6 Exteranl clock input circuit
Note 1
(Note 1)
Low and highjnput levels should be set such that
input level = 0-0.8V
Output level = Vee- (Vee - 0.81v
and such that the duty cycle is 40 to 60% with respect
to the XIN input.
• MITSUBISHI
"ELECTRIC
5-9
MITSUBISHI LSls
M58494-XXXP
SINGLE·CHIP 4·BIT CMOS MICROCOMPUTER
MACHINE INSTRUCTIONS
~
Classification
~
~
2
-
0<3
0>-
ci
1918 17161514 1312h lo
TAM
'~
Q)
Code
Symbol
+j
+j
+j
064
+j
068
+j
06C
+j
OE8
+j
OEC
+j
1
1
1
1
1
1
(y)<-(y)+ 1
(Y)= 0
-
(A) .......... (M(DP)).
(X)<-(X)\tj.
(Y)=15
-
(y)= 0
-
3
3
(Y)=3.7. 11. 15
-
(Y)=4.8, 12. 0
-
3
(y)<-(y) + 1
where j= 0 -
-
3
(y)<-(y)- 1
where j= 0 -
-
3
(y)<-(y)+ 1
where j= 0 -
(A) .......... (M(DP)).
(X )<-( X )V'j.
1
-
-
(y)<-(y)- 1
where j= 0 -
(A) .......... (M(DP)l.
(X )<-( X )V'j.
1
where, j= 0 -
(A)<-->(M(DP)).
(X)<-(X)Vj.
1
-
(Y)= 0
(A)<-->(M(DP))
(X )<-( X )V'j.
1
where, j= 0 -
-
(y)<-(y)+ 1
(A)·-(M(DP)).
(X)<-(X)ltj.
--
3
TMA
0001000100
044
1
1
LA n
AM
AMC
AMCS
A n
SC
RC
SZC
CMA
01 1001
nnnn
19n
060
062
063
05n
08A
088
OB8
OBA
1
1
(A)<-n.
1
1
(A)<-(A) + (M(DP))
1
1
1
1
(A)<-(A) + (M(DP)) +(CY).
(A)<-(A) + (M(DP))+ (CY).
1
1
(A)<-(A) +n.
1
1
(CY)<-l
-
1
1
1
(CY)<- 0
-
0
1
1
1
1
0001100000
0001100010
0001100011
000101
nnnn
0010001010
0010001000
0010111000
001011 1010
(M(DP) )<-(A)
where.
Consecutivelv described
n= 0 -15
where.
(CY)<- Carry
(CY)<- Carry
n=0--15
-
-
0/1
Carry = 1
Carry = 0
(CY)= 0
(A)<-(A)
• MITSUBISHI
.... ELECTRIC
-
-
--
0/1
-
-
-
MITSUBISHI LSls
M58494- XXXP
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
~
Classification
'0
0
E
o ;;:
16 ma~IZ
1918 17161514 131211 10 notation 0
I.
>-
u
Skip condition
Function
Z
OJ
u::'"
0
j
001000 11j j
08C
1
1
(B(j»+-l.
where.
j= 0 -'-- 3
-
-
RB
j
001010 11j j
OAC
1
1
(B(j»+-O.
where.
j= 0 -
-
-
000011 10j j
038
1
1
SZB
j
+j
+j
+j
i:ii
SZM
j
SEY
000000 01j j
004
+j
3
1
j=O-3
j=O-3
where.
OEO
1
1
000001 nnnn
01n
1
1
"
001001 nnnn
09"
1
1
01 Oxxx yyyy
1xy
1
1
-
(Mj(DP»= 0
1
0011100000
-
(B(j»= 0
where.
n
SEAM
OJ
OJ
.~
OU
SB
c
'"
~c
-2
Code
Symbol
-
(A)=(M(DP»
(Y)=n
'"E
where.
n=O-15
-
0
u
SEI
B
xy
(A)=n
where.
(PCL)+-Y.
(PCM)+-X
n=O-15
-
-
-
-
-
-
-
-
-
where 16x+y=O-127
BL
xy
11 Oxxx yyyy
3xy
1
1
(PCL)+-Y.
(PCM)+-(PO. x)
(PCH)+-(P4. P3.
P2. P1)
where 16x + Y= 0 - 127
BA
001101 Oi i i
i
OOi
1
1
.L
u
c
'"
CD
BMAB r
00110010 rr
OC8
+
1
1
(PCL)<--(AO. I)
where.
(PCM)<--(PO. A3.
A2.
(PCH)+-(P4. P3.
P2 . P1)
i= 0 -
7
A1)
(PCL)+-(A)
(PCM)<--(B)
r
(PCH)+-(P4.
P3.
P2. P1)
but returns unconditionally after one machine cycle.
I nput/output address r = 0 - 3 designates general-purpose register
p
01110pPPPil
1CP
1
1
(P)<--P
TPAC
0011000100
OC4
1
1
(p)<--(CY. A)
-
-
TACP
0010100100
OA4
1
1
(CY.
A)<--(P)
-
-
11 1xxx yyyy
38y
1
3
--
-
-
-
-
-
LP
BM
xy
+p
+
x
P= 0 -31
(PCL)+-Y
(PCM)+-(PO.
x).
where 16x + Y = 0 -127
(PCH)+-(P4.
P3.
P2. P1)
Consecutively described
-
(M(SP»+-(pC)
B
OJ
(SP)+-(SP)+ 1
c
:J
0
where.
BMA
i
00 11011i i i
.D
:J
U)
008
+j
1
3
(PCL)+-(AO.
i).
where . j ~ 0 - 7
(PCM)+-(PO. A3.
A2. A1)
(PCH)+-(P4. P3.
P2.
P1)
(M(SP»+-(pC)
(Sp)<--(Sp) + 1
RT
00111 f 1000
OF8
1
3
(PC)<--(M(SP»
(SP)<--(SP) - 1
RTS
001111 1010
OFA
1
4
c
(PC)+-(M(SP»
Unconditionally
-
(SP)<--(SP)- 1
:J
(PC)+-(PC) + 1
OJ
a:
RTI
001111 1001
OF9
1
3
(PC)<--(M(SP»
-
-
(SP)<--(SP)-l
. • MITSUBISHI
.... ELECTRIC
5-11
II
MITSUBISHI LSls
M58494- XXXP
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
~
Classification
~
S
Code
Symbol
-'"'
>-
(l)
.w
~~
ZU
'0
'0
0>-
Function
u
Skip conditions
OJ
1918 17 161514 13121,10
In~~a~~~
EIA
0000001001
009
1
1
Enables interruption of INT A signal.
-
-
EIB
0000001010
OOA
1
1
Enables interruption of !NT B signal.
-
-
u:'"
EIAB
0000001011
OOB
1
1
Enables interruption of INT A and INT B signals.
-
~
:;=
EIT
0000001000
008
1
1
Enables interruption of INT T signal.
---
-
OIA
0000001101
1
Disables interruption of INT A signal.
---
-
0.
OIB
0000001110
000
OOE
1
1
1
Dis8bles interruption of INT B signal.
DIAB
0000001111
OOF
1
1
Disables interruption of INT A and INT B signals.
OIT
0000001100
OOC
1
1
Disables interruption of INT T signal.
0.
0
::J
~
I
::J
0000101111
02F
1
1
(B)<-(TMM)
0010100111
OA7
1
1
(A)'- (TMH3. TMH2. TMH1.
RTM
0010110100
OB4
1
1
(TML)<- O.
STM
0011000111
OC7
1
1
(TM 2 )<-(A)
-
SEC
0011000110
OC6
1
1
(EVC)<-(A)
--
10
0000101110
02E
1
1
(B)<-(O).
(OD)<-uL"
OD
0001001100
1
1
(O)<-(B).
(R/W)<-uL"
1
1
(R( r ))<-5
1
1
(R( r))'--(A.
1
1
(A.
S
::J
0.
::J
0
::J
0.
c
(l)
.r:
(5
5-12
(TMM)<--O.
(TMH)<- 0
-
-
-
OPI s
10 ssss ssss
TNAB r
00010010rr
I~~
04~1
TABN r
00001010 rr
r
028
IQ
0010101000
r
OA8
1
1
(A.
-
-
IR1
0000101100
02C
1
1
(B)<-(P(R,))
---
-
IR2
0000101101
020
1
1
(B)<--(P(R2))
--
---
SMR
0000110100
034
1
1
(MR)<-(A)
-
SMRl
000011 0110
036
1
1
(MR1)<-(A)
SST
000011 1100
03C
1
1
(R(Qo) )<-1.
RST
000011 1101
030
1
1
(R(QO»)<- 0 . R(AII)<-l-bit shift R (All)
1ST
000011 1110
03E
1
1
(R(Qo»~(DATA).
SU
0001001110
04E
1
1
(U)<-(A.
CLP
0000000001
001
1
1
(P(AII)<- 0
--
-
TPRA
001011 0000
OBO
1
1
(P(AII) )<--( R(AII»)
-
--
TPRN r
00111100rr
OFr
1
1
(p( r))<-(R( r))
-
--
TRPN r
00011100rr
07r
1
1
(R( r))<-(P( r))
NOP
0000000000
000
1
1
0
~
TMHO)
(CY)<--(TMH4)
::J
~
._-
TBTM
0.
::J
+
-
TATM
E
~
--
+
-
-
-
B)
---
where the general-purpose register is designated with r = 0 - 3
B)<-(R( r))
--
where the general-purpose register is designated with,. = 0 - 3
B)<-(P(Q) )
R(AII)<-- l-bit shift R (All)
R(AII),
l-bit shift R iAII)
B)
No operation
• MITSUBISHI
;"ELECTRIC
--
-_.
--
.-
--
-
--
-
-
---
--
-
-
-
--
MITSUBISHI LSls
M58494 - XXXP
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
Details
Symbol
A
Details
Symbol
4-bit register (accumlator)
P(R z )
A,
Indicates the bits of register A. Where i
B
4-bit auxiliary register
B(j)
The bit of register B addressed when j
CY
1-bit carry flag
0
4-bit input/output port (3-state)
=0 -
=0 -
3
4-bit port R2
p(Q)
S-bit port 0
R(AII)
Indicates all the S·b't registers 0, R, S, T (32·bit)
3
R(r)
The register selected by r (r corresponds with registers Q, R, S, and
T where r = 0 - 3)
DATA
1-bit input/output port for serial data
R(Qo)
1st bit of register 0
OP
12-bit data pointer composed of registers X, Y and Z
R/W
l-bit output port which is used for the write signal of the external
SM(OP)
The 4-bit Internal scratch-pad memory addressed by the data pointer
maIO memory
EVC
4-bit event counter
M(OP)
4-bit data memory addressed by the data pointer DP
Mj
12-bit data from the scratch-pad memory addressed by i
Mj (OP)
4-bit data from external memory addressed by the contents data
5-bit counter
pointer DP, where j = 0 - 3
4-bit counter
1-bit flat for selection of internal scratch-pad memory (MF +- 0 at
5-bit counter
DP
4-bit stack pointer
=0 - 3
(data pointer number in the fixed area)
MF
14-bit counter composed of TM L , TMM and TMH counters
instruction SM) or external main memory (MF +- 1 at instruction
II
Indicates the bit of TMH counter, where i = 0 - 4
MM)
4-bi t counter
MM(OP)
4-bit external main memory data addressed by the data peinter DP
M(SP)
12-bit data from external memory addressed by the steck pointer
4-bit output port (3-state)
4-bit register where X = 0 -15, addressing the field of 16 words by
4 bits per file
SP (return address stored in the fi xed area)
MR
4-bit mode flag (IMO, LCD, IMR1, IMR2)
MR1
4-bit mode flag (TMM, BF '. RVM, SDM)
Y
4-bit register where Y = 0 - 15, which addresses the word un it of 16
z
4-bit register where Z = 0 - 15, which addresses 16 flies x 1G words
words by 4 bits.
Input/output address to select one 01 the general-purpose registers
Q, R, Sand T (r = 0 - 3)
x 4 bits
00
l-bit output port used for the read signal for external main memory
P
5-bit page register
III
3-bit binary variable
2-bit binary constant
P,
Indicates the bits of register P, where i = 0 - 4
nnnn
4-bit binary constant
PC
12-bit program counter composed of counters PC L , PCM and PCH
ppppp
5-oit binary constant
rr
2-bi! binary constant
SSSS SSSS
S-bit binary constant
4-bit counter
xxxx
4-bit binary variable
4-bit counter
yyyy
4-bit binary variable
Indicates all the S-bit ports. 0, R, S, T (32-bit)
zzzz
4-bit binary variable
4-bit counter
P(r)
TI
=
P(R, )
port selected by r (corresponds with ports Q, R, S, and Tat r
0 - 3)
4-bit port R 1
• MITSUBISHI
"ELECTRIC
5-13
U'1
I
INSTRUCTION CODE LIST
"""
I\'~
16
00 0001 00 0010 00 0011 00 0100 00 0101 00 0110 00 0111 00 1000 00 1001 00 1010 00 1011 00 1100 00 1101 00 1110 00 1111
mal J
~~ation
1,-1 0
0000
000000
0
00
Nap
01
SEY
02
TAY
03
-
04
TYA
1
CLP
SEY
1
0010
2
-
SEY
*
-
3
-
SEY
TAX
-
TXA
,.
rt'IaI:
r"'_
rt'I-t
0101
0110
0111
TAZ
SZM
SEY
TAM
0
4
0
SZM
SEY
TAM
1
5
1
SZM
SEY
TAM
2
6
2
SZM
SEY
TA.M
3
7
3
5
6
7
-tc
:om
(iii)
=
1000
8
EIT
-
TZA
1001
9
EIA
A
EIB
B
EIAB
1101
C
0
OIT
OIA
SMRl
*
*
0
0
1
1
2
2
E
OIB
0
1
2
F
OIAB
AMC
A
AMCS
XAM
SOP
0
a
A
XAM
SOP
5
1
1
A
XAM
SOP
6
2
2
A
XAM
SOP
7
3
3
A
XAMO
8
0
A
XAMO
9
1
A
XAMO
10
2
XAMI
12
12
a
S EY
A
XAMI
13
1
IR2
SST
RST
S EY
10
1ST
00
*
SU
S EY
15
TBTM
*
*
A
XAMI
14
2
A
XAMI
15
3
DEY
09
SEI
OA
DB
TAB TPRA TBA
SEI
*
MM
1
SEI
*
*
TASP
*
TSPA
*
*
TACM
SEI
TACP RTM TPAC
SEI
*
*
RC
*
-
-
TATM
-
10
SZC
0
*
*
SB
SEI
RB
a
12
0
SB
SEI
RB
1
13
1
SB
SEI
RB
2
14
2
SB
SEI
RB
3
15
3
9
SEI
10
*
*
1
BA
0
1
2
LOP
LOP
-
LOP
TSM TCMA
3
B
B
B
RT
B
0
RTI
B
1
RTS
B
2
3
BMA XAMII
4
B
3
BMA!3 BMA XAMDl
3
B
3
2
BMAB BMA XAMDl
2
SEI
*
-
BMAB BMA XAMDl
11
*
STM
B
1
7
*
*
BA
B
2
LOP
-
5
BMAB BMA XAMDl
CMA
*
SEC
B
0
7
*
SC
-
10-17
1
TPRN
*
SEI
*
*
*
u
TPRN
*
6
SEI
*
BA
BA
*
6
SEI
BA
3
OF
TPRN
TPRN
*
4
SEI
5
SEAM
BA
*
4
*
1
2
SEI
3
DE
BA
*
2
*
00
BA
0
8
INY
DC
0
TRPN
4
A
IRI
TRPN
A
3
SEY
1
3
XAMO
3
SM
2
A
3
14
1111
A
08
TRPN
*
11
3
13
1110
*
SEY TABN SZB TNAB
11
1100
*
SEY TABN SZB TNAB
10
1011
*
SEY TABN SZB TNAB
9
1010
SMR TMA
SEY TABN SZB TNAB
8
1
07
TRPN
0
3
4
(')(1)
AM
2
3
0100
06
A
*
2
0011
A
0
0
0001
05
01 0000
01 1100 01 1110 10 0000 11 0000 11 1000
01 1000 01 1001 01 1010 01 1011
I
I
I
I
I
I
01 0111
01 1101 01 1111 10 1111 11 0111 111111
*
TSMI
B
B
0
BMA XAMll
*
*
TMS
*
5
1
BMA XAMII
6
*
B
TMSI
B
2
BMA XAMII
*
*
7
3
*
B
18
19
lA
lB
LY
LA
LZ
LX
0
0
0
0
LY
LA
LZ
LX
1
1
1
1
LY
LA
LZ
LX
2
2
2
2
LY
LA
LZ
LX
3
3
3
3
LY
LA
LZ
LX
4
4
4
4
LY
LA
LZ
LX
5
5
5
5
LY
LA
LZ
LX
6
6
6
6
LY
LA
LZ
LX
7
7
7
7
LY
LA
LZ
LX
8
8
8
8
LY
LA
LZ
LX
9
9
9
9
LY
LA
LZ
LX
10
10
10
10
LY
LA
LZ
LX
11
11
11
11
LY
LA
LZ
LX
12
12
12
12
LY
LA
LZ
LX
13
13
13
13
LY
LA
LZ
LX
14
14
14
14
LY
LA
LZ
LX
15
15
15
15
lC-lO lE-lF 20-2F
30-37
38-3F
LP
-
OPI
BL
BM
LP
-
OPI
BL
BM
LP
-
OPI
BL
BM
OPI
BL
BM
Note: 13 -1 0 indicate the low-order 4 bits of the machine code and 19 -1 4 show the high-order 6 bits Hexadecimal expressions of the codes are also given. All instructions are one word.
• - . Do not use these codes.
-
LP
LP
-
OPI
BL
BM
LP
-
OPI
BL
BM
LP
-
OPI
BL
BM
LP
-
OPI
BL
BM
LP
-
OPI
BL
BM
LP
-
OPI
BL
BM
LP
-
OPI
BL
BM
CIt
iG)
r-
1'1"1
n•
:z:
ii
.,.•
III
=i
LP
-
LP
-
OPI
BL
BM
(')
I:
0
OPI
BL
BM
CIt
I:
LP
-
OPI
BL
BM
LP
-
OPI
BL
BM
LP
-
OPI
BL
BM
n
;a
0
n
0
I:
"G
c:
-t
1'1"1
;a
i:
en
....
QD
:.:
CD=i
I
~
III
><=
>
=~~:!~~:::'(;~~~;::;~::::~
~~~~~~~~~~:;~:;:;:;
LCg
LC,
LC7
LC,
LC,
LC.
LC,
LC,
LC,
LCo
important.
FEATURES
•
•
•
Single 5V power supply
. . . . . . . . 77
Basic machine instructions
Basic instruction execution time
(at 4.2MHz (iquid crystal frequency) . . . . . . . . . 7.7/1s
•
Memory capacity: ROM . . . . . . 2048 words x 10 bits
•
•
•
•
Internal RAM .. 128 words x 4 bits
External RAM .. 256 words x 4 bits
Internal crystal oscillation circuit
Internal 22-stage frequency divider
Low voltage detector circuit
Internal current saving circuit while idling
•
•
•
•
Subroutine nesting ... . . . . . . . . . . . . . . .. 3 levels
Internal timer: Prescaler... 7 bits Timer ... 4 bits
Output ports for liquid crystal display
segment signal (port LC). . .
. 25 bits
common signal (port COM).
. .4 bits
I/O Ports (ports K and S) ... .
Output port (port D) . . . . . . .
4 bits x 2
. . . . . . . . 1 bit x 11
BLOCK DIAGRAM
INTERNAL POWER
ON/OFF INPUT
,------A----.
PWON
COM)
Lew
FI
F,
F.
F,
F,
II
• Output port (port F)
• Output port (port P)
• Interrupt function
· . . . . . . 1 bit x 8
· . . . . . . 1 bit x 2
· 4 factors, 1 level
APPLICATIONS
•
Electronic cash registers and calculators with printer
•
•
•
Office machines, intelligent terminals and data terminals
Electronic Games
Electronic coin and changer machines
• Sewing machines
INTERRUPT
INTERNAL
POWER ON
RESET SIGNAL
PWOFF
RESET (ON)
1Y24
~~~~nT
(SV) (5V)
~~
1NTs
(OV)
(08V)
TIMING
OUTPuT
Vee Vee
I
I
L _____
I
I
-.J
CURRENT SAVING
CO~TROL CIRCUIT
RESET
CONTROL
SIG,NAL
KO K, K Z K J
S05,$253
LCo LC .. LC 4 Le 6 LeB LC'OLC'2 LC14LC'6 Le'B LC20 LCZ2 LC24 COM, cm.~J
Le,
LC 3 LC s Le 7 Leg Le 'l Le 3 Le,s Len LC'9 LCll,LCZl COMo COM"
'
'--y----' '--v----" '
I/O PORT K I/O PORT S
Po
P,
FoF,FzF3F4FsF6F,
DoD,D2D)D4D5D6D7DsD9D,o
PO~~P~~
PORT F
PORT D
OUTPUT PORT LC FOR
OUTPUT
LlOUID CRYSTAL DISPLAY LlOUIDCRYSTALDISPLAY PORT P
(COMMON SIGNAL)
(SEGMENT SIGNAL!
• MITSUBISHI
.... ELECTRIC
5-17
MITSUBISHI MICROCOMPUTERS
MS8496-XXXP
SINGLE·CHIP 4·BIT CMOS MICROCOMPUTER
FUNCTION
The M58496-XXXP consists of mask ROM and RAM, a
4-bit arithmetic logic unit, crystal oscillation circuit, 22stage frequency divider, power saving circuit, low voltage
detector circuit, 4-bit timer, interrupt circuit and a liquid
crystal display direct drive circuit. The RAM capacity can
easily be expanded by the external connection of 256-word
by 4-bit CMOS RAM.
The ROM storage is organized as 16 pages of 128 words
which is used mainly for programs. Addressing the ROM is
done through the program counter. The address register is
structured as a 7-bit address register and a 4-bit page register. The address register is counted up as nonbranching instructions are executed. When a nonbranching instruction
at address 127 on a page is executed an overflow of the address register is produced. This carry (overflow) is disregarded so the page register is not counted up and the next
instruction to be executed will come from address 0 on the
same page.
. When an interrupt request is accepted control js transferred to fixed addresses as follows: in case of an internal
power on reset signal (RESET(ON)) the program is set to
page 0 address 0, for the I NT A signal it is set to page 0
address 2, for the I NT B signal it is set to page 0 address 4
and for the output signal INTT{second signal) of the 22stage frequency divider it is set to page 0 address 8.
The internal RAM which is configured as 8 files of 16
words is used for data storage and each word can be addressed. The internal RAM is addressed by a 7-bit data
pointer. The internal RAM can be augmented by external
RAM consisting of up to 16 files of 16 words. The external
RAM is addressed by the 8-bit combined register Y (4 bits)
and register B (4 bits).
RAM addressing, register-to-register transfers, RAM-toaccumulator transfers, arithmetic operations, input/output
operations and timer operation are performed mainly
through register A (accumulator).
The current saving circuit used in conjunction with the
22-stage frequency divider and RAM can be controlled by
the PWOFF input and instruction_
The low voltage detector circuit is also active while
the power source is a battery. Low voltage is sensed by the
program and an indication can be output.
The output ports for direct drive of the liquid crystal
display are port LC (25 terminals) and port COM (4 terminals). The liquid crystal display can be driven by 1/4
duty, 1/3 bias or 1/3 duty, 1/3 bias.
Output port D consists of 11 individually latched bits
that can be used to output not only l-bit data but can also
output data such as the contents of register Y of the data
pointer and 8-bit addresses for external RAM .
Output port F consists of 8 individually latched bits
that can be used to output data. It can be set or reset by
instructions.
Output port P consists of 2 terminals through which a
synchronous signal of 1 machine cycle width can be output by instruction.
The combined 7-bit output of ports F and P can be
used to directly fetch the contents of ROM addressed by
the data field of an instruction.
The I/O ports K and S consist of 4 terminals through
which data can be transferred to and from register A.
PERFORMANCE SPECIFICATIONS
Item
Performance
Number of basic instructions
77
Execution time of basic instructions
7.7/.LS (Vee=5V, f=4.1943MHz)
Clock frequency
250-525kHz
2048 words x 10 bits
ROM
Memory Capacity
Internal RAM
128 words x 4 bits
External RAM
256 words x 4 bits
LC
COM
K
I/O Port
S
D
Liqu id crystal
display output
4 bits
25 x 1 bit
Input
4 bits
Output
4 bits (Note 1)
Input
4 bits
Output
4 bits (Note 1)
Output
11 x 1 bit (open drain)
F
Output
8 x 1 bit (Note 1)
P
Output
2 x 1 bit (Note 1 )
Frequency divider
22-stage built in
Current saving circuit
8uilt in
Low voltage detector
Built in
Subroutine nesting
3 levels (including 1 level of interrupt)
Interrupt request
4 factors, 1 level
Clock generation circuit
Built in (4.1943 MHz crystal oscillator external)
I nput/output port
Power supply valtage
Output voltage
6V (max)
Output current
-OA mA (min.)
Vee
5V (nom)
VSS
OV
(Note 2)
Note 1:
Ports K, S, F, and P are connected
ta high-impedance pull-down resistars.
Liquid crystal display driving supply voltage
O.8V (nom)
When high· driving current is required,
Element structure
CMOS
external resistars are required.
Package
72-pin plastic molded flat package
Power dissipatian
In operation
5mW (Vee=5V, 525 kHz)
(open output terminals)
In idle
1.5mW (Vee=5V, 525 kHz)
5--18
• MITSUBISHI
..... ELECTRIC
2'
External .oscillator can be selected by
mask aptian.
(1) 4.1943 MHz crystal oscillator
(2) 455 kHz ceramic oscillator
MITSUBISHI MICROCOMPUTERS
MS8496-XXXP
SINGLE·CHIP 4·BIT CMOS MICROCOMPUTER
PIN DESCRIPTION
Pin
Name
Source oscillation
clock input
Input or
output
At reset
(internal power-on)
Function
Incorporates the clock oscillation circuit. for setting the frequency. An oscillation
Input
reference device such as a crystal oscillator is connected between XIN and XOUT.
When an external clock is used, connect the clock oscillation source to the XIN pin
XOUT
Source oscillation
clock output
Output
PWON
I nternal power on input
Input
and leave the XOUT pin open.
Incorporates the power saving circuit. Its control inputs are PWON and PWOFF.
The 22·stage frequency divider and RAM are put in the idle state by a PWOFF
PWOFF
I nternal power off input
Input
RESET (DV)
Frequency divider
reset input
Input
BDIN
Low voltage
detector input
Input
I nterrupt request
A signal
Input
Low level
input.
Incorporates the 22-stage frequency divider as the crystal oscillation reference
device. This is a reset input for up to lower 17 steps of the divider.
The low voltage detector ci.-cuit is built in. A resistor should be connected to the
BDIN pin for voltage sensing.
Interrupt disable
Th is input signal is for an interrupt request. The request is accepted on the rising
edge of the signal. Besides these external input signals, an interrupt request I NT T
INTs
Interrupt request
B signal
LCO-LC24
Liquid crystal display
segment output
Input
I nterrupt disable
from the 22-stage frequency divider output signal is sensed as an interrupt.
Incorporates the liquid crystal display direct drive circuit. It is suitable for liquid
Output
crystal display at 1/4 duty and 1/3 bias.
Liquid crystal display
common output
The output ports for direct drive of the liquid crystal display are port LC (LC oOutput
LC 24 ) and port COM (COM o-COM 3 ).
This is the power supply terminal for a liquid crystal display. It inciudes the bias
Power supply for
liquid crystal display
resistor for the segment and common signals.
This output port consists of 11 bits. Each output is individually latched and can
Output port D
Output
Floating
be selected to be set or reset by the contents of register Y.
Also B bits of the
port can be used to fetCh B·bit addresses for external RAM.
Output port F
Output
Low level
The output port consists of B bits. Each output is individually latched and can be
set or reset by instructions.
This output port consists of 2 bits from which 1 synchronous signal of 1 machine
PO,P1
Output port P
Output
Low level
cycle width can be output per instruction. The immediate 7·bit field of an instruction can be output through this port in combination with 5 bits of port F.
Ko-K3
I nput/output port K
Input/output
Low level
Ports K and S are 4-bit latched input/output ports through which data can be
transferred to and from register A. When output is low-level the output will be
Input/output
SO-53
Input/output S
T2
Timing output
Output
RESET(ON)
Internal power-on
reset signal
Output
Low level
high-impedance so it can be used as an input port.
The timing output is used for testing the device.
When the internal power supply is switched on, a built in automatic reset circuit
Low level
generates a high· level reset signal that resets the I/O ports.
• MITSUBISHI
"ELECTRIC
5-19
1'1
MITSUBISHI MICROCOMPUTERS
MS8496-XXXP
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
DESCRIPTION OF OPERATION
Program Counter PC
The program counter is an ll-bit address register. The
high-order 4 bits designate the page number and as a group
are called PCH. The low-order 7 bits designate the address
on the page and as a group are called PCl. The PC designates the address of the 2048 words by 10-bit mask-programmable ROM. The ROM is organized into 16 pages of
128 words. As instructions are fetched -from ROM, PCl is
incremented so that unless there is a branch executed instructions are fetched and executed in sequence. Care must
be taken when the last instruction on a page (address 127)
is executed because when PCl is incremented it becomes
zero with a carry, but the carry is disregarded so the next
instruction to be fetched will be the start of the same page.
Therefore to move to the next page PCH must modified by
using branch instructions such as B L, BM L, B LA and
BMLA.
Pages 14 and 15 are special pages designed to accommodate subroutines. Subroutines starting on page 14 can be
called by l-word instructions BM or BMA. These instructions automatical!y load PCH to designate page 14 and in
addition the return address and control status are saved so
they can be restored when the subroutine transfers control
back to the main program. If the instructions BM or BMA
are executed on page 14, they execute a branch within page
14 without saving any information. If the instructions B
or BA are executed on page 14, they execute a branch to
page 15.
External RAM is organized as 16 files of 16 words that
can be added to the system to expand memory. Register Y
designates the word position of a file while register B designates the file.
Register A (accumulator) and Carry Flags CV, CV'
Register A is the 4-bit accumulator forming the heart of
the 4-bit microcomputer. Data processing operations such
as arithmetic, transfer, exchange, conversion, and input/
output are executed principally through this register.
The carry flags CY are to store the carry or borrow
from the most significant bit of the arithmetic unit reSUlting from executing the various instructions. It can be
tested and used for various purposes. In principle it acts
as a l·bit flag.
The carry flag CY'is selected by software to leave the
contents of CY unchanged (saves the CY).
Register B (Auxiliary Register)
Register B is a 4-bit register used for temporary storage of
4-bit data. It also is used to designate the file number of
external RAM.
Arithmetic Logic Unit (ALU)
The arithmetic logic unit performs 4-bit arithmetic and
logical operations. The heart of the ALU is a 4-bit adder
and the logic circuit associated with it. It performs operations such as additions, complement conversions, logic
arithmetic comparisons and bit processing.
Stack Registers SKo, SKl , SK2
Frequency Divider and Timer
The 3-level stack register consists of l1-bit registers for
storing the contents of the program counter when control
is transferred from the main program to a subroutine or
interrupt. When control is transferred back to the main pro·
gram, the PC can be restored. There are 3 levels, but when 1
level is saved for interrupts it leaves 2 levels for subroutine
nesting.
The frequency divider divides the basic oscillation frequency into 22 stages. It is connected to the basic oscillation device through XIN and XOUT. The frequency divider
generates the interrupt request signal I NT T to the interrupt control circuit. The frequency divider sets flag CK for
controlling the power saving circuit.
Basic oscillation for the timer is the timing signal T 2 •
The timer is composed of a 7-bit prescaler and a 4-bit counter. Timer flag TMF /F is set when a timer overflows, and is
sensed by the TTM instruction. The 4-bit timer counter is
set by the STM instruction. Prescaler and timer flag are
reset at the same time.
Data Pointers DP, DP'
The data pointer is a 7-bit register used to designate the
address of RAM or the bit position of output port D. The
data pointer is composed of the 3-bit register X and the 4bit register Y. Internal RAM is organized as 8 files of 16
words. Register X designates the file and register Y designates the word position of a file or the bit position of output port D.
The data pointer DP' is selected by software during
interrupt processing to leave the contents of DP unchanged
(saves the DP).
5 -- 20
Power Saving Circuit
The power saving circuit is controlled by the CK flag and
PW. Its output is input to the internal power supply reset
circuit and generates an interrupt request signal RESET
(ON). Control is transferred unconditionally to address 0
on page 0 and resets the I/O ports. The interrupt request
• MITSUBISHI
.... ELECTRIC
MITSUBISHI MICROCOMPUTERS
MS8496-XXXP
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
signal RESET (ON) generates on the rising edge of internal power supply on reset output. Internal power supply
is switched off by the external terminal and stop instruction, but power is maintained to the following circuits:
1. Internal data memory (RAM)
2. Clock oscillation circuit
3. 22-stage frequency divider
4. Low voltage detector circuit
5. Power saving circuit
Low Voltage Detector Circuit
The low voltage detector circuit connects the resistor for
sensing voltage to the BDIN terminal. A falling voltage level
is sensed by the program and can be displayed by using apt
output port.
Interrupt Functions
The M58496-XXXP has internal circuits to process interrupt requests from 4 single level sources. The 4 interrupt
request sources are external interrupt signals I NT A and
INTB, internal power supply reset output RESET (ON),
output I NT T from the 22-stage frequency divider. Interrupt requests INTA, INTB and INTT are enabled by the
instructions EIA, EIB and EIT respectively and disabled by
the instruction DIA, DIB and DIT respectively. Interrupt
requests from the internal power supply through reset output RESET (ON) cannot be disabled and will cause an
interrupt whenever received.
During the interrupt enable state an interrupt request
by I NT A or I NT B is accepted on the rising edge of the
signal. When an interrupt request is received during the
interrupt disable state it is latched, but is not executed.
When the disable is removed thereafter by executing the
corresponding interrupt enable instruction, the interrupt
request will be accepted immediately and control transferred to the interrupt routine because the request was
latched. A current interrupt request, held by latching during interrupt disable state is reset when the corresponding
interrupt disable instruction is executed.
One level of the 3-level stack register is required when
interrupt programs are used. This leaves 2 levels available
for subroutine processing. After an interrupt is processed
control is returned to the main program by executing a
return instruction such as RTI. Care must be taken after
starting an interrupt program to save the contents the data
pointer DP, register A, carry flag and any other registers
used, so the contents can be restored before returning to
the main program. The contents must be saved and restored by the interrupt program.
When an interrupt request is accepted the program
counter, interrupt enable flag and skip flag are affected
as follows:
(1) Program counter
The contents (the current program address) are stored
in the stack register. Control is transferred to address
a on page a by a RESET (ON) interrupt, to address 2
on page a by an I NT A interrupt, to address 4 on page
by an I NT B interrupt or to address 8 on page a by an
INTT interrupt by setting the control counter to 00,
02, 04 or 08 respectively. When control is transferred
to address a page 0, the instruction is invalid and is not
executed, so the first instruction is executed from address 1 on page O.
(2) Interrupt enable flags
When an interrupt request is accepted additional interrupts are disabled until the accepted interrupt is p r o - I I
cessed. Except that a RESET (ON) interrupt may be
accepted at any time.
(3) Skip flags
The skip flags are used to indicate an instruction skip
and the Nap state for instructions LXY and LA are
saved. A special stack is provided for saving these flags.
General-Purpose I/O ports K, S, F, P and D
These 4-bit or 1-bit general-purpose registers are used for
such things as data transfer between register A, instruction
transfers, 1-bit transfers as selected by register Y, storing
7-bit immediate field data of instructions fetched from
ROM, and data transfers between external RAM. Each output has a latch and its output circuit contains an open drain
resistor or a pulldown resistor (high-impedance).
I/O ports K, S
Ports K and S are 4-bit latched I/O ports, that can transfer
data to and from register A. Output latches are reset by
the DIKS instruction when the port is being used as an
input port.
Output port F
Port F is an 8-bit latched output port, that has independent
latches for each bit. The individual bits can be set by the
SF instruction and reset by the R F instruction.
Output port P
Port P is a 2-bit latched output port, that is usually in low"level, but can output the machine cycle high-level synchronous signal by SPo or SP 1 instructions. The 7 bits (F4""
Fo, PI, Po) can be used for direct fetching of the immediate field of the OTRO instruction.
Output port 0
Port D is an 11-bit latched output port, that has independent latches for each bit. The contents for register Y indicate the individual bit to be set by the SD instruction or
to be reset by the RD instruction. The 8-bit address of
external memory (RAM) is output through this port.
• MITSUBISHI
"ELECTRIC
5-21
MITSUBISHI MICROCOMPUTERS
MS8496-XXXP
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
Liquid Crystal Display Drive Circuit
The liquid crystal display direct drive circuit is composed
of the following units. A block diagram of the units is
shown in Fig. 1.
1 Control counter for the liquid crystal display
This is an octal counter composed of 3 bits and is
counted down by the ELC instruction. The contents
of the counter select 1 bit of register A and transfer
data in order to the segment register R LC by the TLC
instruction and determines the frame frequency for
the liquid crystal display by transferring the contents
of the counter to common register RCOM.
2 Register A
This 4-bit register is the accumulator. Its function is
to control data processing, arithmetic operations control functions and input/output of the microcomputer.
3 Segment register R LC
The 26-bit segment register stores selected l-bit data
from register A by execution of the TLC instruction.
4
5
6
It shifts 1 bit in order and stores the segment signals
for the liquid crystal display device.
Common register RCOM
The 4-bit common register storeS the common signal
for the liquid crystal display. The input for the common register is the converted contents of the control
counter for the liquid crystal display.
Port LC
The 26-bit latched port LC stores data in parallel by
the ELC or DLC instruction from the segment register R LC. A bias resistor provides for the output at 2
levels and the 25 low-order bits are output as standard
type. The high-order bit is not output to an external
terminal.
Port COM
Port COM has 4 bits of latched storage. The data is
transferred in parallel by the ELC or DLC instruction through the common register (RCOM). The outputs of this port have 3 biased levels by means of bias
resistors.
ELC INSTRUCTION
BIT DESIGNATION
VCC
~ (VCC- VLCO)
+ VLCO
V LCO
SUPPLY VOLTAGE FOR LIQUID
CRYSTAL DISPLAY
COMO COMl COM2 COM3
SEGMENT SIGNAL OUTPUT
Fig. 1 Liquid crystal display drive circuit block diagram
5--22
• MITSUBISHI
;"ELECTRIC
COMMON SIGNAL OUTPUT
V LCO
SUPPLY VOLTAGE
FOR LIQUID
CRYSTAL DISPLAY
MITSUBISHI MICROCOMPUTERS
M58496·XXXP
SINGLE·CHIP 4·BIT CMOS MICROCOMPUTER
RESET FUNCTION
Documentation Required Upon Ordering
As shown in Fig. 2, when the PWOFF input of the
The following information should be provided when order-
M58496- XXXP is driven
input/output ports are reset and the interrupt disabled state
ing a custom mask.
(1) M58496-XXXP mask confirmation sheet
low for at least 10ms, the
is entered. (Refer to the descriptions of the power-on reset
'(2) ROM data ...................... 3 EPROM sets
states in the Pin Description.) Next, if the PWON input is
(3) Oscillation frequency selection
driven high, or an interrupt is generated by the internal
. . . . . . . . . . . . . . .. On confirmation sheets
(4) Frequency divider output selection (1 Hz/2Hz)
power-on reset RESET (ON) caused by a frequency divider
output INT T, the program counter is set to address 0 page 0
as a starting location.
POWER APPLIED
SV
Vee
ov
. . . . . . . . . . . . . .. On confirmation sheets
lr~-------------
---.J-
SV
II
10ms
~I,--------
PWOFF
OV--+-....I
r----
SV
1
PWON
OV-----....I
Fig. 2 Power-on reset circuit
CLOCK GENERATOR CIRCUIT
A built-in clock generator circuit has been provided and a
quartz crystal or ceramic element (mask option) can be
externally connected. In addition, an external clock source
may be connected to pin X IN , leaving pin X OUT open.
Circuit examples are shown in Fig. 3 and Fig. 4.
M58496-XXXP
2-4.2 MHz
1) Veritication of oscillation should
GIN
15pF
T
be made at the timing output T 2.
GOUT
T15PF
In addition, the required circuit
constants will vary with the frequency and type of crystal used.
Vee (or VSS (OV))
Fig.3
External circuit connected by crystal oscillator
M58496 - xXXP
XIN
SOl
XOUT
1
51
5VLJUlr
EXTERNAL OSCILLATION CIRCUIT
OV
Fig.4 External clock input circuit
• MITSUBISHI
.... ELECTRIC
5-23
MITSUBISHI MICROCOMPUTERS
MS8496-XXXP
SINGLE·CHIP 4·BIT CMOS MICROCOMPUTER
INSTRUCTION CODE LIST
~9 o.
~~~~~.
03
0 0"'~;"'/
.,
0000
0
0001
1
2
0010
0011
3
0100
4
0101
5
0110
6
0111
7
1000
8
1001
9
1010
A
1011
B
1100
0
0
1101
1110
E
1111
Note
F
1:
5-24
(Note 1)
00 1110 01 0000 01 1000
00 0000 00 0001
00 0010 00 0011
o a
o 1
o 2
NOP
TLO
INY
seOM
EIA
OIA
EIB
OIB
OETS
OETR
EIT
DIT
STM
POF2
POFI
SDET
TTM
TCK
OIKS
SFK
SFS
lIE
OLO
lIE
ELO
spa
lIE
SPI
lIE
OTAO
lIE
ADRT
TPW
00 0100 00 0101
00 0110 00 0111
o 3
o 4
o 5
a 6
SZB
SEY
SEI
SF
0
0
a
a
SZB
SEY
SEI
SF
1
1
1
1
SZB
SEY
SEI
SF
2
2
2
2
SZB
SEY
SEI
SF
3
3
3
3
SEY
SEI
SF
4
4
4
SEY
SEI
SF
5
5
5
SEY
SEI
SF
6
6
6
SEY
SEI
SF
7
7
7
SEY
SEI
RF
8
8
a
SEY
SEI
RF
9
9
1
SEY
SEI
RF
10
10
2
SEY
SEI
RF
11
11
3
SEY
SEI
RF
12
12
4
SEY
SEI
RF
13
13
5
SEY
SEI
RF
14
14
6
SEY
SEI
RF
15
15
7
DEY
XOP
TYA
SO
RO
XO
lIE
lIE
SO
lIE
lIE
lIE
RD
lIE
lIE
RT
RTS
RTI
lIE
lIE
lIE
lIE
lIE
lIE
lIE
lIE
SZO
00 1000 00 1001
o 7
o 8
o 9
BL
BLA
BML
BMLA
-
RAR
BL
BLA
BML
BMLA
-
BL
BLA
BML
BMLA
lIE
BL
BLA
SEAM
BML
BMLA
BL
BLA
BML
BMLA
lIE
BL
BLA
BML
BMLA
TAY
BL
BLA
BML
BMLA
AND
BL
BLA
BML
BMLA
EXL
BL
BLA
BML
BMLA
lIE
BL
BLA
BML
BMLA
OMA
BL
BLA
BML
BMLA
AM
BL
BLA
BML
BMLA
lIE
BL
BLA
BML
BMLA
lIE
BL
BLA
BML
BMLA
lIE
BL
BLA
BML
BMLA
AMO
BL
BLA
AMOS
BML
BMLA
00 1010 00 1011 00 1100 00 1101
a A
o B
o 0
a 0
TAM
XAMO
A
LA
a
a
a
0
TAM
XAMO
A
LA
1
1
1
1
TAM
XAMO
A
LA
2
2
2
2
TAM
XAMO
A
LA
3
3
3
3
TAM
XAMO
A
LA
4
4
4
4
TAM
XAMO
A
LA
5
5
5
5
TAM
XAMO
A
LA
6
6
6
6
TAM
XAMO
A
LA
7
7
7
7
-
IK
IS
TBA
-
XAB
TAB
SB
XAM
XAMI
A
LA
a
a
a
8
8
SB
XAM
XAMI
A
LA
1
1
1
9
9
SB
XAM
XAMI
A
LA
2
2
2
10
10
SB
XAM
XAMI
A
LA
3
3
3
11
11
RB
XAM
XAMI
A
LA
a
4
4
12
12
RB
XAM
XAMI
A
LA
1
5
5
13
13
RB
XAM
XAMI
A
LA
2
6
6
14
14
RB
XAM
XAMI
A
LA
3
7
7
15
15
This list shows the machine codes and corresponding machine instructions
0 3 -0 0 indicate the low-order 4 bits of the machine code and 0 9 -0 4 indicate the high-order 6 bits. Hexadecimal numbers are also shown that represent the codes. An instruction may consist of one or two words, but only the
first word is listed. Code combination indicated with asterisk (*j and bar
(-I must not be used.
. • MITSUBISHI
;"ELECTRIC
10 0000
10 1000
11 0000
11 1000
\
\
\
00 1111 010111
011111
10 0111
101111
110111
111111
OE -OF 10 - 17
18 -IF
20-27
28-2F
30 - 37
38 -3F
\
\
-
OTRO
LXY
BM
BMA
B
BA
-
OTRO
LXY
BM
BMA
B
BA
-
OTRO
LXY
BM
BMA
B
BA
-
OTRO
LXY
BM
BMA
B
BA
-
OTRO
LXY
BM
BMA
B
BA
-
OTRO
LXY
BM
BMA
B
BA
-
OTRO
LXY
BM
BMA
B
BA
-
OTRO
LXY
BM
BMA
B
BA
-
OTRO
LXY
BM
BMA
B
BA
-
OTRO
LXY
BM
BMA
B
BA
-
OTRO
LXY
BM
BMA
B
BA
-
OTRO
LXY
BM
BMA
B
BA
-
OTRO
LXY
BM
BMA
B
BA
-
OTRO
LXY
BM
BMA
B
BA
-
OTRO
LXY
BM
BMA
B
BA
-
OTRO
LXY
BM
BMA
B
BA
Two·word instructions
Second word
BL
11 Oxxx
BLA
11 1xxx
YYYY
XXXX
BML
10 Oxxx
YYYY
BMLA
10 1xxx
XXXX
MITSUBISHI MICROCOMPUTERS
MS8496-XXXP
SINGLE·CHIP 4·BIT CMOS MICROCOMPUTER
MACHINE INSTRUCTIONS
~
Mnemonic
D9 D8
LXY x,Y
OJ
~
B
*
.~
a:
OJ
Y Y Y Y
Hexa-
D
decimal
z
1Sy
1
1
+
x
~
~
Cl
'"
u:::
where,
x=0-7
Consecutively
described
y=0-15
X
0000
0001
020
021
1
1
(Y)~(Y)+l
-
X
001 0
1
1
(Y)~(Y)-l
-
X
TAB
TBA
XAB
TAY
TYA
XDP
00
00
00
1 00 1
o
1
(A)~(B)
-
X
0100
1
1
(B)~(A)
,-
X
1 001
01 1 0
1
1
(A)--(B)
-
X
00
00
00
1 000
01 01
1
1
(A)~(Y)
-
X
001 0
001 1
1
1
(Y)~(A)
-
X
0010
001 0
097
094
096
085
023
022
1
1 001
1
1
(DP)--(DP' )
-
X
TAM j
00
1 0 1 0
OJ
j j
OAj
1
1
(A)~(M(DP»
-
X
XAMj
00
1 01 0
1 j j j
OAS
1
1
(A)--(M(DP»
-
X
1 1 1
(X)~(X)Vj,
+
j
XAMD j
00
1 0 1 1
OJ
j j
OBj
1
1
where,
j=0-7
(X) ~(X) V j, where,
j=0-7
XAMI j
00
1 0 1 1
1 j j j
OBS
1
1
+
j
LAn
AM
AMC
(Y)~(Y)-l
(A)--(M(DP»,
(X)~(X)Vj,
0
«
a:
(X)~x,
(Y) ~y, where,
co
~
>u
Skip conditions
ci
C
0
Functions
001 0
1
"0,
1 x x x
D3 D2D,Do
00
INY
DEY
~
01
D7 D6 D 5 D 4
~
00
«
a:
if]
Instruction code
Class
ification
i
(Note 1)
where,
(Y)~(Y)+
(A)--(M(DP»,
(X)~(X)Vj,
where,
(Y) = 15
X
(Y) =0
X
j=0-7
1
j=0-7
Consecutively
described
00
1 1 0 1
n n n n
ODn
1
1
(A)~n,
00
00
1000
1 01 0
1
1
(A)~(A)+(M(DP»
-
X
1 000
1 1 1 0
OSA
OSE
1
1
(A)~(A)+(M(DP»+(CY)
-
0/1
where, n =0 -15
X
(CY)~Carry
AMCS
00
1000
1 1 1 1
OSF
1
1
(A) ~(A) +(M(DP»+(CY)
(CY)~
u
";:;
~~
A n
00
1 1 00
n n n n
SC
RC
00
00
00
00
00
00
00
00
001 0
0100
001 0
01 01
001 0
o
001 1
1 1 1 1
1000
o
1000
01 1 1
1 000
1 001
1 001
0000
XC
SZC
AND
EXL
CMA
RAR
1 1 0
1 1 0
OCn
024
025
026
03F
OS6
OS7
OS9
090
00
1 001
1 0 i i
1
1
(A)~(A)+n,
1
(CY)~l
-
1
1
1
(CY)~O
-
0
-
(en
0
.~
en
where,
n=0-15
Carry = 0
X
1
1
(CY)--(CY' )
1
1
Skip if (CY)=O
1
1
(A)~(A)A(M(DP»
1
1
(A)~(A)
1
1
(A)~(A)
-
X
1
1
(An-1)~(An)
-
(Ao)
(CY)=O
X
-
V (M(DP»
X
X
(A3)~(CY)
1
1
(Mi(DP»~l,
where, i=0-3
-
X
1
1
(Mi(DP»~O,
where, i=0-3
-
X
1
1
Skip if (Mi(DP» =0, where, i=0-3
+
i
c
~c
E
098
0/1
1
(CY)~(Ao),
SB i
(CY)=O
Carry
RB i
00
1 00 1
1 1 i
i
09C
+
i
SZB i
00
001 1
OOi i
03i
(Mi(DP»=O
X
where, i =0-3
SEAM
SEY y
00
1000
001 1
00
0100
Y Y Y Y
OS3
04y
1
1
1
1
~
~
E
SEI n
00
01 0 1
n n n n
05n
1
.
1
Skip if (M(DP» = (A)
(M(DP»=(A)
X
Skip if (Y)=y, where, y=0-15
(Y)=y, where,
X
y =0-15
Skip if (A) =n, where,
n=0-15
(A)=n,where,
X
0
u
n =0-15
SCOM
00
0000
0001
001
1
1
Skip if (SCA=O) and (SCB=O)
SCA=O and
X
SCB=O
• MITSUBISHI
"ELECTRIC
5-25
II
MITSUBISHI MICROCOMPUTERS
MS8496-XXXP
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
IB
Instruction code
Mnemonic
Class
ification
B xy
i3
0
Hexa-
0 90 8
07 0 6 0 5 0 4
03 0 2 0 ,0 0
1 1
o
x x x
00
1 1
o
o
1 1
1 x x x
;;:
III
~
'0
'0
0
decimal
0
z
z
y y y y
3xy
1
1
1 1 1
PPPP
07p
2
2
x x x
y y y y
3xy
(Note 2)
BL pxy
~
u
c
BA xX
Functions
(PCL) ---16x +y
Skip conditions
>
u
C>
~
-
X
-
X
-
X
-
X
-
X
-
X
-
X
-
X
-
X
-
X
(PCH)---15. (PCL) ---16x +y
XXX X 38X
~
ell
(PCH) ---P
(POL) ---16x + y
1
1
(PCL) ---16x + (A)
2
2
(PCH) ---P
+
X
(Note2)
BLA pxX
(PCH) ---15. (POL)---16x+(A)
00
o
1 1 1
pppp
07p
1 1
1 x x x
XXXX
38X
(PCL) ---16x + (A)
+
x
BM xy
'1 0
o
x x x
y y y y
2xy
1
1
(SK2)---(SK 1)---(SKO )---(PC)
(PCH) ---14. (PCL) ---16x +y
(Note 2)
BML pxy
13
Q)
(POH) ---14. (POL) ---16x +y
1 0
o
o
1 0
00
c
::J
0
.0
BMA xX
1 1 1
P P P p
y y y Y
07p
2xy
2
x x x
1 x x x
XXXX
28X
1
2
(PCH)-P. (PCL)-16x+y
1
+
(Note2)
BMLA pxX
RTI
(PCH)-14. (POL)-16x+(A)
00
01 1 1
pppp
1 x x x
XXXX
07p
28X
+
x
2
1 0
00
001 1
o
036
1
1 1 0
2
1
(PC)-(SKO )---(SK 1)-(SK2)
Restore interrupt skip flags
::J
Q)
(SK2)-(SK 1)-(SKO )-(PC)
(PCH) ---P. (PCL) -16x + (A)
c
cr:
(SK2) ---(SK 1 )---(SKO) -(PC)
(PCH) ---14. (PCL) ---16x + (A)
x
~
(SK2)---(SK 1)---(SKO )-(PO)
RT
RTS
00
00
001 1
0100
1
(PC)-(SKO )-(SK 1)-(SK2)
01 01
034
035
1
001 1
1
1
(PC)-(SKO )-(SK 1)-(SK2)
DIKS
00
00
0001
0001
011
1
1
(K)-O.
-
X
1 001
001 0
092
1
1
(A)-(K)
-
X
00
1 001
001 1
1
1
(A)-(S)
-
X
00
00
0001
0001
001 0
1
1
(K)-(A)
-
X
001 1
093
012
013
1
1
(S)-(A)
-
X
00
00
001 0
1 001
029
1
1
(0(Y»-1.
0010
1 1 0 1
0001
1 1 1 0
020
OlE
1
00
1
00
0001
1 1 00
01C
1
1
IK
IS
SFK
SFS
SD
RD
ADRT
OTAD
(S) --- 0
Unconditional
X
where,
O;?; (Y);?; 10
-
X
1
(O(Y»---O. where,
O;?;(Y);?; 10
-
X
1
(0)-0
-
X
(07 -04) +-(8)
-
X
::J
(03-Do)+-(Y)
"::J
1
SF m
RF m
OTRO mn
00
01 1 0
Ommm
06m
1
1
(Fm)-1.
where,
m=0-7
-
X
00
o
lmmm
068
1
1
(Fm)---O.
where,
m=0-7
-
X
n n n n
+
m
lmn
1
1
-
X
01
1 1 0
Ommm
(Fo-F3)-n.
where,
n=0-15
(F4. PO. Pl)---m. where,
SPO
m=0-7
00
00
0001
0001
1
(PO)---1. where output 1 machine cycle
-
X
1 01 0
018
01A
1
SPl
1
1
(Pl) ---1 • where output 1 machine cycle
-
X
TLC
00
0001
0000
010
1
1
(R (LO 0» ---(Ai). where,
-
X
-
X
-
X
1000
i=0-3
(R(LCn+l»-(R(LC n»
ELC
00
0001
o
1 1 1
017
1
1
(P (LCn» -(R (LCn»
(P(COMn»-(R (COMn»
OLC
00
0001
01 01
015
1
1
(P (LCn» ---(R (LCn»
(P(COM»----i-(VCC-VLCO) +VLCO
5-26
• MITSUBISHI
"ELECTRIC
MITSUBISHI MICROCOMPUTERS
MS8496-XXXP
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
~
Instruction code
Mnemonic
0908
Class
ification
0 7 0 6 05 0 4
0 3 0 2 0 10 0
~
"E
~
~
'0
decimal ci
z
'0
ci
Hexa-
>-
Functions
Skip conditions
u
u::''""
z
EIA
00
0000
001 0
002
1
1
Enables interruption of INTA signal.
-
X
OIA
00
0000
001 1
003
1
1
Disables interruption of INTA signal.
-
X
::J
EIS
00
0000
0100
004
1
1
Enables interruption of I NTs signal.
-
X
~
DIS
00
0000
01 01
005
1
1
Disables interruption of INTs signal.
-
X
a.
EIT
00
0000
1000
008
1
1
Enables interruption of INTT signal.
-
X
OIT
00
0000
1 001
009
1
1
Disables interruption of INTT signal.
--
X
STM
00
0000
1 01 0
OOA
1
1
(TM)<--(A), (TM F/F)<--O
-
X
~
7-bit prescaler presetting
i=
~
8
>
a.
a.
::J
~
rf
Misc.
TTM
00
0000
1 1 1 0
OOE
1
TCK
00
0000
POF1
00
0000
1 1 1 1
OOF
1 1 00
OOC
POF2
00
1 0 1 1
00
0000
0001
TPW
OETS
00
OETR
00
SOET
NOP
1
Skip if (TM F/F) =1
(TM F/F)=l
X
1
1
Skip if (CK F/F)=l
(CKF/F)=l
X
1
1
(CK F/F)<--O
-
X
008
1
1
(PW F /F) <--0
-
X
1 1 1 1
01F
1
1
Skip if (PW F/F)=l
0000
01 1 0
006
1
1
(DET F/F)<--l
-
0000
01 1 1
007
1
1
( 0 E T F / F ) <--0
-
00
0000
1 1 01
000
1
1
Skip if (BOOUT) = 1
00
0000
0000
000
1
1
(PWF/F)=l
X
X
(BDoUT)= 1
-
No operation
Note 1:
When the M58496·XXXP generates a skip it is not necessary to increment the program counter so no additional cycles are required for
2'
execution.
Instructions B. BA. BM or BMA execute the second function of the functions column when executed. provided that none of instructions
X
X
X
RT. RTS. BL. BML. BLA or BMLA was executed after execution of instruction BM or BMA.
Symbol
Meaning
Meaning
Symbol
4-bit register (accumulator)
P(COMn)
Common output port for liquid crystal display
Ai
Indicates the bits of register A. Where i=1-3
P(LCn)
Segment output port for liquid crystal display
B
4-bit auxiliary register
PW F/F
1-bit power supply control flag display
BDOUT
Battery detector signal
A (COMn)
Common register for liquid crystal display (4 bits)
CK F/F
1-bit 1-second flag
R(LCn)
Segment register for liquid crystal display (25 bits)
CY
i -bit carry flag
S
4-bit I/O port
CY'
1-bit carry flag
SCA
Output of bit A of control counter for liquid crystal display
A
0
11-bit output port
SCB
Output of bit B of control counter for liquid crystal display
Oi
I ndicates the bits of port D. Where i=Cl-3
SKO
11-bit stack register
D(Y)
The bit of port D addressed by Y
SKl
11-bit stack register
DP
7-bit data pointer composed of register Y. X
SK2
11-bit stack register
TM
4-bit timer/counter
Y. Y'
4-bit register
TM F/F
1-bit timer/counter flag
X. X'
3-b it register
xx
2-bit binary variable
4-bit binary variable
DP'
7-bit data pointer
yyyy
DET F/F
1-bit battery detector flag
mmm
3-bit binary variable
F
8-bit output port
nnnn
4-bit binary variable
Fi
Indicates the bits of port F. Where i=Q-7
II
2-bit binary variable
K
4-bit I/O port
3-bit binary variable
M(DP)
4-bit data of memory addressed by data pointer DP
iii
XXX X
4-bit unknown binary variable (the value does not affect
execution)
Indicates direction of data flow
<-Mi(DP)
PC
.A bit of data of memory addressed by data pointer DP
(
where i=Q-3
V
11-bit program acounter composed of PC L • PCH
)
I ndicates contents of register memory. etc .
Exclusive OR
1\
AND
-
Negation
PCL
Low-order 7 bits of the program counter
X
Indicates flag is unaffected by instruction execution
PCH
High-order 4 bits of the program counter
xy
Label used to indicate the address xxx yyyy
Po
1-bit output port
C
Hexadecimal number C + binary number-X
p,
1-bit output port
+x
•
MITSUBISHI
~ELECTRIC
5-27
II
MITSUBISHI MICROCOMPUTERS
MS8496-XXXP
SINGLE·CHIP 4·BIT CMOS MICROCOMPUTER
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
VCC
Supply voltage
VI
Input voltage
Vo
Output voltage
Pd
Power dissipation
Topr
Operating free-air temperature range
Tstg
Storage temperature range
Limits
Conditions
With respect to Vss
Unit
-0.3-6.0
V
-0.3- V cc+ O. 3
V
0
T a=2S00
V
-Vcc
300
mW
-50
°0
-40-125
°0
0
RECOMMENDED OPERATING CONDITIONS (Ta=D-SO°C, unless otherwise noted)
Limits
Parameter
Symbol
Unit
Min
Nom
Max
VCC
Supply voltage
VSS
Supply voltage
0
V
VLCO
Liquid crystal supply voltage
0.8
V
4.5
5
5.5
V
VIH
High-level input voltage
VIL
Low·level input voltage
0
0.8
V
fXIN
Oscillator frequency
2
4.2
MHz
f¢
Internal clock oscillator frequency
250
525
kHz
Vcc- 0 .8
ELECTRICAL CHARACTERISTICS
VCC
V
(Ta=O-SO°C, Vcc=SV±10%, Vss=OV, f xIN =2-4. 2MHz, unless otherwise noted)
Limits
Symbol
Unit
Test conditions
Parameter
Min
Typ
Max
IOH
High·level output current, port 0
VOH=(VCC-O.S)V
-0.4 -0.8
IOH
High-level output current, ports F, P, K, and S
VOH=(VCC-O.S)V
-0.4 -0.6
IOL
Low-level output current, ports F, P, K, and S
VOL=O.SV
VOH
High·level output voltage, port LC
Vcc=SV. VLco=0.8V.
Ta=2S00
3.75
3.95
V
VOH
High-level output voltage, port COM
VCC=SV. VLco=0.8V.
Ta=2S00
4.8
5
V
Vox
Medium-level output voltage, port COM·(Note 1)
Vcc=SV. VLco=0.8V.
Ta=2S00
2.7
2.9
3.1
V
VOL
Low-level output voltage, port LC
Vcc=SV. VLco=0.8V.
Ta=2S00
1. 85
2.05
V
VOL
Low-level output Voltage, port COM
VCC=SV. VLco=0.8V.
Ta=2S00
0.8
1
V
Icc
Supply current, full operating condition
VCC=SV.
Ta=2S00.
Output pins open
0.7
1
mA
Ta=2S00.
Output pins open
200
300
f.1A
60
120
f.1A
2
Icc
Supply current, partial operating condition
VCC=SV.
ILCO
Liquid crystal supply current, full operating condition
Vcc -VLco=4.2V.
Ta=2S00. Output pins open
mA
mA
20
f.1A
OJ
Input capacitance
VCC=VI=VO=VSS. f=lMHz. 2SmVrms
7
10
pF
OjCXIN)
Oscillator input capacitance
Vcc =XOUT=VSS. f= 1MHz. 2SmVrms
7
10
pF
VSO
Battery voltage detection voltage range (Note 2)
5.5
V
10kQ~Rso~200kQ.
Ta=2S00
Note 1. Vox is the medium level of the 3-level output of port COM.
2. The detection resistance RBO is connected between the Vss and pin BDIN
3. Currents are taken to be positive when flowing into the IC with minimum and maximum values taken as absolute values.
5-28
• MITSUBISHI
.... ELECTRIC
4.5
MITSUBISHI MICROCOMPUTERS
MS8496-XXXP
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
TIMING REQUI REMENTS (Ta;0-50°C, Vcc;5V±10%, VSS;OV,unless otherwise noted)
Limits
Test conditions
Parameter
Symbol
Min
Typ
Unit
Max
t8u (K-X,N)
Data setup time before clock input, port K inputs
0
11 8
t8U (S-X'N)
Data setup time before clock input, port S inputs
0
118
tsu (INTA-X,N)
Data setup time before clock input, I NTA input
0
118
t8u (INTB-X ,N)
Data setup time before clock input, INT B input
0
11 8
t h(K-X ,N )
Data hold time after clock input, port K inputs
t h (S-X ,N )
f ¢=525kHz
(Note 1)
0.4
11 8
Data hold time after clock input, port S inputs
0.4
11 8
th(INTA-X,N)
Data hold time after clock input, I NTA input
0.4
118
t h (INT B-X,N)
Data hold time after clock input, I NTB input
0.4
118
Note 1. f;1/8 fXIN which corresponds to the internal clock frequency.
SWITCHING CHARACTERISTICS (Ta;0-50°C, VCC5V±10%, VSS;OV,unless otherwise noted)
r-------_,------------------------------------------~-------,--------------~~----~
Limits
Unit
Symbol
Test conditions
Parameter
Typ
Max
Min
tpLH (X,wO)
Low·to·high-Ievel propagation time from clock input to port data output. port 0
0.7
1.5
118
tPLH(X,wF)
Low-to-high·level propagation time from clock input to port data output. port F. P. K. and S
RL=20kQ
0.7
1.5
11 8
tpHL(X,wO)
High-to-Iow-Ievel propagation time from clock input to port data output. port 0
CL=100pF
2.2
3.0
118
tpHL¢<,w F )
Hlgh·to-Iow-Ievel propagation time from clock input to port data output. port F. p. K. and S
2.2
3.0
118
f ¢=525kHz
(Note 2)
Note 2. Measurement circuit
TIMING DIAGRAM
T1
X,N
T2
T3
T4
rLr'L
Ko - K3 (INPUTS)
So - S3 (INPUTS
INTA (INPUTS)
INTB (INPUTS) •
Do - 010 (OUTPUTS)
tpHL(X,wO)
tpLH(X,N-F)
Fo-F7(OUTPUTS)
tPHL(X,N-F)
• MITSUBISHI
"'ELECTRIC
5-29
II
MITSUBISHI MICROCOMPUTERS
MS8496-XXXP
SINGLE·CHIP 4·BIT CMOS MICROCOMPUTER
BASIC TIMING CHART (Note 2)
--==--
Machine cycle
s~e
Clock signal (Note 1)
M1
T1
II
¢
II
\
T2
Port D output
Do -010
Port F output
Fo-F7
X
X
Port P output
PO,P1
/
X
Port K output
KO-K3
Port K input
KO-K3
Port S output
SO-S3
Port S input
SO-S3
Note
1:
T3
T4
\
\
\
!I
Timing output
Interrupt request input
T2
INTA,INTe
XXYXXYXXXXX XXXXXXXXXX
XXXXXXXXXXX
X
XXXXXXXXXXX XXXXXXXXXX
XXXXXXXXXXX IYXXXXXXXXXXXXXXXXXXX10<
~
XXXXXXXXXXX
Internal clock signal which is l/S of basic oscillation frequency.
2: ~ indicates an invalid signal input.
INSTRUCTION FETCH TIMING
~
Instruction cycle
State
MI
T1
Mi +1
T2
T4
T3
Instruction fetch
I-----
T2
T1
---
MI +2
T4
T3
T2
T3
1-------
(Note3)
I nstruction execution
Note
TI
T4
r----
(Note 4)
3:
Instruction fetch time can differ depending on the types of the instructions.
4·
The instruction which was fetched in the preceding cycle is executed.
5:
The execution of the instruction and addressing of ROM and RAM are performed simultaneously.
I/O INSTRUCTION EXECUTION TIMING
~
Signal name
Signal SYmbol
State
010
Port D output
Do
Port F output
Fo-F7
Port P output
Po, P1
Port K output
Ko-K3
Port K input
KO-K3
Port S output
SO-S3
Port S input
SO-S3
Port LC output
LCO- LC 24
Port COM output
COMO-COM3
Note
MI
T1
T2
MI +1
T3
I
i----
T4
T1
T2
I
Mi +2
T3
T1
I
T2
I
T3
I
T4
r-----1X
i----D(
\ - - - - - - - - - - - - ----------------(Note6)
II
i----D(
r---
~
IXXXXXXX ~XX;X XXXXXXXXXXX XXXXXXXX XX XX XXX
IX
~
XXXXXX.X x.XX)< XXXAXXXXXXX YXXXXXXXXXXXXXX
IX
(Note 7)
(Note 8 )
6:
When an OTRO instruction is executed, the output is latched.
7:
Output voltage of port LC depends upon power supply VLCD for the liquid crystal display.
S·
Output voltage of port COM has 3 levels depending on the power supply VLCD for the liquid crystal display.
5-30
I
T4
• MITSUBISHI
"ELECTRIC
MITSUBISHI MICROCOMPUTERS
MS8496-XXXP
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
BRANCH AND SUBROUTINE CALL INSTRUCTION EXECUTION TIMING (Note 1)
~cle
Operation
State
M , +l
M,
Tl
I
Tz
I
T3
T4
Tz
Tl
M , +2
I
T3
T4
Tz
Tl
T4
T3
Instruction Bxy (to be operated as the branch instruction, ~hen the instruction BM or BMA was not executed before).
~.
Progra m cou n ier
---:d
~.
(POL)~XY
(POL)~(POL)+1
(POL)
~dreSS)~(J)
ROM address
I
+ 1
I
~~,,-(J,
I
I
I
Execution of the branch instruction
Execution of program
~(POL)
Execution of the instruction stored in the branched address
Instruction Bxy(to be operated as the branch instruction to page15,when the instruction BMorBMA was executed before).
~~_(Pc"l,
I
Program counter
~[II
,IROM .dd:,,,, _(pc!,
(POL) ~(POL) + 1
(POL)~XY
ROM address
I (ROM ad~resS) ~(P~)
Execution of program
Execution of the branch instruction
II
Execution of the instruction stored in the branched address on page 15
Instruction BMx y (subroutine call instruction).
0-(PC"
~rc".!
'dd["" -(PC
I I
Program counter
I
(POL)~XY
ROM address
+1,
(ROM address) ~ (PO)
IIROM
Stack register
'
(SK2) i(SK,) ~(rKo)~(PO?
Execution of program
I
Execution of the subroutine call instruction
Execution of the instruction stored in the subroutine called address
Instruction BL p,xy (branch instruction).
I
Program counter
I
I. (PO L) ~(PO L) + 1.
~
I
(ROM address)~(PO)
(TempOrary) +-f>
register
ROM address
I
Execution of program
I
~~ (TempOrarp
j
register
(POL) ~(POL) + 1
(
H)
I
I
Page number is stored temporarily
I
(POL)~~_
(ROM ad~ress) ~(P~)
r
register
H
L
~:;;:t,,-(JHPc,1
Page number is stored temporarily
~(POL)+1
L
I
(ROM address) ~(PO)
I
Execution of program
1:
~~(TempOr~~(PO )J
(POL);:::.r-,
I1R0M.drHPcr
Stack register
Note
(POL) ~(POL) + 1
~
ROM address
~(PJ)
branched address
I
I
re~~~~rar1 +-f>
>
(ROM address)
I
I
I
Execution ot the instruction stored in the
Execution of branch instruction
Instruction BML p, xy (subroutine call instruction).
Program counter
Lrj(PC" +
I
Execution of the subroutine call instruction
-
(ROM
I
address)~(PO)
E,ocJ""h,J""c)I" I
stored in the subroutine called address
The instructions BA, BMA, B LA and BM LA have the same execution timing as B, BM, BL and BM L respectively as shown. The only difference is that (PCl) <-- xy
is replaced by (PCl) <-- x(A).
INTERRUPT EXECUTION TIMING
(Note 2)
M,
Mi-l
Mi+l
T2
Interru'pt request input
Program counter
M,+z
T2
INTA
(Note 3)
(PC)
ROM address
Stack register
Execution of program
Note
2:
3:
When the instruction executed in the machine cycle Mi+l is a B L, BML, B LA or BM LA, the value of address 2 of page 0 is stored in the program counter during M i +3'
The interrupt request input I NT B has the same execution timing as I NT A. If the input is low level in the machine cycle Mi-l and high level in the machine cycle Mi,
the interrupt is executed during the interrupt enable state.
•
MITSUBISHI
;'ELECTRIC
5-31
MITSUBISHI MICROCOMPUTERS
M58497-XXXP
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
DESCRIPTION
PIN CONFIGURATION (TOP VIEW)
The M58497-XXXP is a single-chip 4-bit microcomputer
fabricated using CMOS technology. Its features are liquid
crystal display direct drive circuit, current saving circuit for
back-up of a 15-stage frequency divider and RAM.
The device is designed for applica~ions in which clock
LO ..
LO.
LO,
LO,
LO,
LOs
LO,
LO,
LO,
LO,
and liquid crystal display functions are included and where
the low-power dissipation achieved by CMOS is. especially
important.
FEATURES
•
•
o
Memory capacity: ROM: . . . . ..
s:
•
Internal oscillator circuit
•
Internal 15-stage frequency divider
•
Internal current saving cirucit
•
I nternal low-voltage detector circuit
•
Subroutine nesting ...................... 3 levels
•
Internal timer:
XO UTO
co
RESET(DV)
""......co
I
X
X
X
"0
Fs
F,
F,
Po
P,
External RAM: .. 256 words x 4 bits
Single 4.5V power supply
XO UT1
X1NG
U1
F,
2048 words x 10 bits
Internal RAM: .. 128 words x 4 bits
•
LO"
OOM,
4
Fo
F,
F,
F,
Instruction execution time (at an
57
OOMo
La.
Basic machine instructions .................... 77
oscillation frequency of 455kHz) ............ 17.6J,!s
•
o
o
Package Outline 72P2
x4
Prescaler: ................... 6 bits
•
I/O ports (ports K and S) ................ 2
Timer: .. ................... 4 bits
•
Output port (port D) ................... 11 x 1 bit
•
Output port (port F) ................... 8 x 1 bit
Segment signals (port LC) 26 bits
•
Output port (port P)
Common signals (port COM) 2 bits
•
Interrupt function
•. Output ports for liquid crystal display
2 x 1 bit
............... 4 factors, 1 level
BLOCK DIAGRAM
INTERRUPT REOUEST INPUTS (4.5 V ) (4.5 V )(2.9 V )( 1.3
POWER-ON RESET INPUT
~
RESET(PW)
INT A
11
v )(
0 V)
INT B
DIVIDER CLOCK
TIMING OUTPUT
BASIC CLOCK INPUT/OUTPUT
~ DIVIDER RESET INPUT
LOW·VOLTAGE DETECTOR
~
XOUT1 X 1N1 RESET(DV)
T2
INPUT
XINO XOuTO
24
53
49
52
50
51
I
1
l
KO K, K2 K3
So
$, 52 53 LCD· LC z
~ ~
I/O PORT K
5-32
bits
Le,
La..
Le,
LOs
Les
LOa
Le,
LO tO LO lz LO", LO l6 LOu ,LOZD LOu LOu
Le,
Lell
Le:;
LeI> LCn
Le" LCll
COMo
LCn LC" .:::::,
I/O PORT S OUTPUT PORT LC FOR LlOUID CRYSTAL DISPLAY (SEGMENT SIGNAL)
Po PI
OUTPUT PORT COM
OUTPUT
FOR LlOUID CRYSTAL PORT P
DISPLAY (COMMON SIGNAL!
• MITSUBISHI
.... ELECTRIC
Fo F, F z F J F .. Fs F6 F 1
Do
0, 02 03 0 .. Os 06 07 0 8 09 DID
'-r-' '--_ _,,--_-.J. ~
OUTPUT PORT F
OUTPUT PORT D
MITSUBISHI MICROCOMPUTERS
M58497-XXXP
SINGL::::::-CHIP 4-BIT CMOS MICROCOMPUTER
APPLICATIONS
and for the output signal I NTT (1 second signal) of the
•
Electronic tuners for radios and TVs
15-stage frequency divider, it is set to page 0, address 8.
•
Medical equipment
•
Measurement instruments
•
Vending mach ines
The internal RAM is configured as 8 files of 16 words,
addressed by the 7-bit data pointer. A 16 file x 16 digit
external expansion memory can be addressed using 8 bits of
address composed of the 4-bit register Y and 4-bit register B.
FUNCTION
RAM
addressing,
register-to-register
transfers, RAM-
The M58497-XXXP consists of a 2,048 word x 10-bit mask
accumulator transfers, arithmetic operations, input/output
ROM, 128 word x 4-bit RAM, 4-bit arithmetic logic unit,
operations, and timer operations are performed chiefly
oscillator circuit, 15-stage frequency divider, power saving
through the 4-bit register A (accumulator).
backup circuit for the RAM memory, low-voltage detector
The current saving circuit used in conjunction with the
circuit, 4-bit timer, interrupt circuit, and liquid crystal
15-stage frequency divider and RAM can be controlled by
display direct drive circuit. By connecting external 256-
the RESET (PW) input and program instructions.
word x 4-bit CMOS RAMs to this 4-bit microcomputer,
RAM
capacity can be easily expanded.
The low-voltage detector circuit is operative when using
a battery power source, and can be program controlled to
The ROM is capable of storing 16 pages of 128 words of
program, addresses being specified by the program counter.
provide an appropriate output upon sensing a low voltage
level.
The program counter consists of a 7-bit address designating
Direct drive of a liquid crystal display is possible using
counter and a 4-bit page designating counter. Wrap-around
the 26 LC pins and 2 COM pins. 1/2 duty cycle and 1/2
to address zero is automatic after exceeding the address
bias or static drive is possible.
127. The return address from subroutines and interrupts is
stored in a stack register of 11 bits x 3 levels.
The output port D consists of 11 individually latched
bits, and in addition to the ability to output a single bit, the
When an interrupt request has occurred, control is
position of which is determined by the contents of the data
transferred to a fixed address as follows. If the case of
point register Y, 8 bits of the port D can be used as the
internal power-on reset (RESET(ON)), the program is set to
external RAM address signal output.
page 0, address 0, for the I NT A signal it is set to page 0,
Output port F consists of 8 individually latched bits that
address 2, for the INT B signal it is set to page 0, address 4,
can be used to output data. It can be set or reset using
program instructions.
PERFORMANCE SPECIFICATIONS
Performance
Parameter
Number of basic instructions
Execution time of basic instructions (one-word instruction I
77
17611s (Vcc-4.5V, f-455kHzl
Clock frequency
Memory capacity
120-260kHz
ROM
Internal RAM
External RAM
LC
I/O ports
2,048 words x 10 bits
128 words x 4 bits
256 words x 4 bits
Liquid crystal display output.
COM
Liquid crystal display output
26 bits
2 bits
K
Input
Output
4 bits
4 bits
Input
4 bits
4 bits
S
D
F
P
Output
Output
Output
Output
11 x 1 bit
8 x 1 bit
2 x 1 bit
Frequency divider
15-stage built-in divider
Current saving circuit
Low-voltage detector circuit
Built-in
Built-in
3 levels (includin9 1 level of interrupti
Subroutine nesting
4 factors, 1 level
Interrupt requests
Clock generator circuit
Built-in (for use with 455kHz ceramic filter externally connected I
I.nput/output ports
Ou tpu t vol tage
Output current (loLi
Supply voltages
Vee
Vss
6V (maxi
1.8mA (mini
4.5V (noml
OV
Liquid crystal display driving voltage VLCD
1.3V (noml
Element structu re
CMOS
72-pin plastic molded flat package
Package
Power dissipation
(open output terminalsl
In full operation
Divider and RAM in the idle state
2mW (nom I (Vcc=4.5V, f=455kHzl
90llW (noml (VCc=4.5V, f=455kHzl
•. MITSUBISHI
.... ELECTRIC
5-33
II
MITSUBISHI MICROCOMPUTERS
M58497-XXXP
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
Output port P consists of 2 pins through which a
synchronous signal of one machine cycle width can be
Seven bits of output port F and P can be used to directly
fetch the immediate field of the ROM.
The I/O ports K and S consist of 4 bits through which
output by program instructions.
data can be transferred to and from register A.
PIN DESCRIPTIONS
Pin
Name
Input or
output
State at reset
(internal power-on)
Function
-
XINO
Clock oscillator input
Input
XOUTO
Clock oscillator output
Output
-
XINl
Divider clock input
Input
-
These are the clock input and output pins. A ceramic element or other frequencydeterming element is con nected between pins XINO and XO UTO . When an external
clock is used, connect the clock source to the X INO pin and leave the XO UTO pin open.
These are the divider clock input and output pins. The quartz crystal that determines
the reference oscillation frequency is connected between pins X IN1 and XO UTI
XOUTl
Divider clock output
Output
-
RESETc DVl
Divider reset input
Input
-
-
BDIN
Low-voltage detector input
Input
INTA
Interrupt request A signal
Input
Interrupt disable
This is the divider reset input for the 15-stage divider circuit used to divide the 32k
Hz crystal reference signal.
A built-in low-voltage detector circuit has been provided. A resistor should be connected to the BDIN pin for voltage sensing.
These input signals are for an interrupt request. The request is accepted on the rising
edge of the signal. In addition to these external input signals, an interrupt request
INTT from the 15-stage frequency divider output signal is also treated as an interrupt.
Interrupt request B signal
INTB
LCo -LC25
Liquid crystal display
Input
Output
Interrupt disable
-
segment outputs
COMo-COM,
Liquid crystal display
common outputs
VLCD. ~VLCD
Power supply for liquid
crystal display
Do -D,o
Output port D
These liquid crystal display outputs are suitable for driving a liquid crystal display at
1/2 duty cycle and 1/2 bias. The output ports for direct drive of such liqu id crystal
displays are port LC (LCO-LC25) for the segments and port COM (COMo-COM,)
Output
-
-
-
for the common outputs.
These are the liquid crystal display power supply pins for segment signals and common
signals.
This output port consists of 11 bits, each of which is individually latched and can be
Output
High level
selected to be set or reset according to the contents of register Y. In addition, 8 bits
of this port can be used to fetch an 8-bit address for external RAM.
Fo -F7
Output port F
Output
High level
P,
Output port P
Output
High level
This output port consists of 8 bits, each of which is individually latched and can be
set or reset using machine instructions.
This output port consists of 2 bits from which one synchronous signal of one rnapo.
ch ine cycle width can be output per instruction. The 7-bit immediate field of an
instruction can be output through this port in combination with 5 bits of port F.
Ko-K3
Input/output port K
Input/output
High level
Ports K and S are 4-bit latched input/output ports through which data can be transferred to and from register A (accumulator). When the output is programmed high,
SO-S3
Input/output port S
T2
Timing output
Output
RESET(PW)
Power-on reset input
Input
5-34
Input/output
High level
-
Low level
t he high-impedance state is enabled allowing use of the pins as input pins.
This timing output is used for testing the device.
When the internal power supply is switched on, a built-in automatic reset circuit
generates a high level reset signal that resets the I/O ports and starts the system.
• MITSUBISHI
.... ELECTRIC
MITSUBISHI MICROCOMPUTERS
M58497-XXXP
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
DESCRIPTION OF BASIC FUNCTIONAL BLOCKS
Program Counter PC
The program counter is an ll-bit address register. The 4
high-order bits are used to designate the page number and
are as a group called PC H • The 7 low-order bits are used to
designate the address on the page and as a group are called
PCL. The PC designates the address of the 2048 words by
la-bit mask-programmable ROM. The ROM is organized
into 16 pages of 128 words. As instructions are fetched
from ROM, PCL is incremented, so that, unless there is a
branch, executed instructions are fetched and executed in
sequence. Care must be taken when the last instruction on a
page (address 127) is executed, because when PCL is
incremented it becomes zero with a carry, but the carry is
disregarded so that the next instruction to be fetched will
be the instruction at the first address of the same page.
Therefore, to move to the next page, PC H must be
modified by using branch instructions such as Bl, BMl,
BlA, and BMlA.
Pages 14 and 15 are special pages set aside to accommodate subroutines. Page 14 can be used to store subroutines, which are callable from pages other than page 14
by using the instructions BM and BMA which can be used
as single-instructions to call page 14 subroutines.
When BM or BMA. instructions are executed within page
14, they are equivalent to the branch instructions Band
BA. When B or BA instructions are executed within page
14, a branch to the specified address on page 15 is
executed.
Stack Registers SK o, SK 1 , SK 2
The 3-level stack register consists of 11"bit registers for
storing the contents of the program counter when control is
transferred from the main program to a subroutine or
interrupt. Subroutines can use 3 levels, so that when 1 level
is used for an interrupt routine 2 levels are reserved for
subroutine nesting.
Data Pointers DP, DP'
The data pointer is used to designate the address of RAM or
the bit position of output port D and consists of the 3-bit
register X and the 4-bit register Y. The internal RAM is
organized as 8 files of 16 words. Register X designates the
file and register Y designates the word position of a file or
the bit position of the output port D.
The data pointer DP' is selected by software during
interrupt processing, leaving the contents of DP saved
(unchanged).
The external RAM memory is organized as 16 files of 16
words that can be added to the system to expand memory
capacity. Register Y is used to designate the word position
of a file while register B designates the file itself.
Register A (Accumulator) and Carry Flags, CV, CV'
Register A is the 4-bit accumulator which forms the heart
of the 4-bit microcomputer. Data processing operations
such as arithmetic, transfer, exchange, conversion, and
input/output operations are executed basically through this
register.
The carry flag CY are used to store the carry or borrow
from the most significant bit of the arithmetic unit
resulting from the execution of various instructions. It can
be tested and used for a variety of purposes. In principle, it
acts as a l-bit flag.
The carry flag CY' is used during interrupt processing to
save the contents of the carry flag CY.
Register B (Auxiliary Register)
This register consists of a 4-bit'register used for temporary
storage as well as designate the file number of external
RAM.
4-Bit Arithmetic Logic Unit
This unit is used to perform 4-bit arithmetic and logical
operations and consists of a 4-bit adder and the associated
logic circuitry. It is used to perform operations such as
additions, complementing, logical and arithmetic comparisons, and bit manipulation.
Frequency Divider and Timer
A 15-stage frequency divider is used to divide the basic
oscillator frequency. It is connected to the oscillator source
device through pins X 1N1 and X OUT1 • The frequency
divider generates the interrupt request signal I NT T which is
input to the interrupt control circuit. It also sets the CK
flag for controlling the power saving circuit.
The basic oscillator circuit for the timer is the timing
signal T 2. The timer consists of a 6-bit prescaler and a 4-bit
counter. The timer flags TM F/F are set when a timer
overflow occurs and sensed by the TTM instruction. The
4-bit timer counter is set by the STM instruction. Prescaler
and timer flags are reset at the same time.
Power Saving Circu it
The power saving circuit is controlled by the CK flag and
PW. Its output is sent to the built-in power supply reset
circuit and causes the generation of an interrupt request
signal R ESET(ON). Control is unconditionally transferred to
address 0 on page 0 and results in the resetting of I/O ports.
The interrupt request signal RESET(ON) is generated on
the rising edge of the built-in power supply reset output.
The built-in power supply may:be iswitched off by means of
either an external signal or stop instruction, but power is
maintained to the following circuits:
1. Internal data memory (RAM)
• MITSUBISHI
;.,. ELECTRIC
5-35
II
MITSUBISHI MICROCOMPUTERS
MS8497·XXXP
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
2. Divider Clock oscillator circuit
tion on address 0 page 0 is invalid.
(2) Interrupt Enable Flags
3. 15-stage frequency divider
If any of the four available interrupt factors are
executed, all the interrupt enable flags are reset and the
interrupt disable state is entered.
(3) Skip flags
4. Low-voltage detector circuit
5. Power saving circuit
Low-Voltage Detector Circuit
The low-voltage detector circuit is effective when using the
M58497-XXXP with a battery power supply. The resistor
which is used to determine the low sensing voltage is
connected to the BDIN pin. A voltage falling below this
level is sensed by the program and can be displayed by
using an output port.
Skip flags have been provided to indicate skip conditions for skip or continuous skip instructions. These
are provided for all stacks, the stack flags being saved
and the skip condition for an interrupt being held in
memory.
General-Purpose I/O Ports K, S, F, Pand 0
Interrupt Functions
Four factors in one level of hardware interrupt functions
have been provided. The four interrupt request sources
consist of the external interrupt requests INT A and INT B,
the internal power-on reset output RESET(ON), and the
~ 5-stage frequency divider output INT T. Interrupt is
enabled by the instructions EIA, EIB, and EIT, and
disabled by the DIA, DIB, and DIT instructions respectively. Interrupt requests generated by the internal power
supply by means of the reset output RESET(ON) cannot be
disabled and will cause an unconditional hardware initialization whenever received.
In the interrupt enable state, interrupt requests INT A
and I NT B are accepted on the rising edge of these signals.
When an interrupt request is received when interrupt is
disabled, interrupt processing does not occur but the
interrupt request is stored in a latch so that when the
interrupt disable condition is cancelled the appropriate
interrupt enabling instruction can be used to execute the
interrupt routine immediately.
One level of the 3-level stack register is required when
using an interrupt program. This leaves the remaining two
levels available for subroutine processing. After an interrupt
is processed, control is returned to the main program by
means of an instruction such as RTI.Care must be taken,
however, after starting an interrupt program to save the
content of data pointer OP, register A, carry flag CY, and
any other registers used by the interrupt program so that
the contents may be restored before returning to the main
program.
When an interrupt has been accepted, the microcomputer internal states are as follows.
(1) Program counter
The main program current address is stored in the stack
register. Control is transferred to address 0 page 0 by a
RESET(ON) interrupt, to address 2 page 0 by an INT A
interrupt to address 4 page 0 by an tNT B interrupt,
and to address 8 page 0 by an I NT T interrupt. Note,
however, that for the. RESET(ON) signal the instruc-
5-36
These 4-bit and 1-bit general-purpose registers are used for
such operations as data transfers to and from register A,
instruction transfers, 1-bit transfers as selected by register
Y, storage of the 7-bit immediate filed of instructions
fetched from ROM, and data transfers between external
RAM. Each output circuit is a latched CMOS circuit.
Input/output ports K and S are 4-bit ports, capable of
data transfer with register A. When used as input ports, the
01 KS instruction is used to reset the output latches.
The output port F consists of an 8-bit port with each bit
independently latched. Each bit is settable and resettable
by means of the SF and RF instructions respectively.
Output port P is a 2-bit port which is normally at the
high level. The instructions SP 0 and SI:' 1 can be used to
generate a low-level synchronous signal for one machine
cycle.
Seven bits of the output ports F and P can be used to
directly fetch the ROM immediate field value ( 7 bits) by
means of the OTRO instruction.
The output port 0 consists of 11 bits independently
latched. The contents of register Y indicate the individual
bit to be set by the SO instruction or to be reset by the R 0
instruction. The 8-bit address of external memory (RAM) is
output by means of this port.
Liquid Crystal Display Drive Circuit
The liquid Crystal display direct drive circuit consists of the
following units. A block diagram of these units is shown in
Fig. 1.
(1) Liquid crystal display control counter
This 2-bit quaternary counter counts down under
control of the ELC instruction. The contents of this
counter select 1 bit of register· A and transfer data
sequentially to the segment register R LC by a TLC
instruction while determining the frame frequency by
means of transferring the contents of the counter- to
the common register RCOM.
(2) Register A
This 4-bit register serves as an accumulator. Its func-
• MITSUBISHI
.... ELECTRIC
MITSUBISHI MICROCOMPUTERS
M58497-XXXP
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
tions include microcomputer processing, control, and
central processing for input and output.
(3) Segment Register R LC
This 26·bit serial register is used to store selected single
data bit from register A by means of the TLC
instruction. It shifts single bit in order and temporarily
stores the segment signals for the liquid crystal display.
(4) Common Register RCOM
(5) Port LC
This 26-bit latched port is used to store data in parallel
by means of the ELC or DLC instructions from the
segment register R LC. It provides two levels of bias,
the liquid crystal drive voltage V LCD and the supply
voltage VCC.
(6) Port COM
Port COM consists of 2 latched bits used for parallel
storage of data transferred from the common register
RCOM by the ELC and DLC instructions. It provides 3
levels of bias including liquid crystal drive voltage
This 2-bit register is used to convert the contents of the
liquid crystal display control counter to the commonsignals requ ired for the display.
(V LCD; 1/2 V LCD) and the su pply voltage VCC.
ELC INSTRUCTION
II
Vee
LOa
SUPPLY VOLTAGE FOR
LIQUID CRYSTAL DISPLAY
Fig. 1
LC24
LC25
VLCD
COMO COM1
SEGMENT SIGNAL OUTPUTS
1/2VLCD
~
'---y----'
COMMON SIGNAL OUTPUTS
SUPPLY VOLTAGE FOR
LIQUID CRYSTAL DISPLAY
Liquid crystal display drive circuit block diagram
Reset Function
Power applied
As shown in Fig. 2, when a low level of at least 10ms is
applied to the M58497-XXXP RESET(PW) input pin, all
input/output ports are reset and interrupt is disabled.
(Refer to the section on Power-on Reset States in the pin
descriptions.) Next, when the RESET(PW) input is set to
high, the internal power-on reset output RESET(ON)
causes the generation of an interrupt and the program
coutner is set to address 0 on page 0 as the starting address.
4.SV
I
~----------
Vee
OV
4.SV
oV
_ _ _+----J
Fig. 2 Power-on reset circuit
•. MITSUBISHI
.... ELECTRIC·
5-37
MITSUBISHI MICROCOMPUTERS
MS8497-XXXP
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
Clock Generator Circuit
A built-in clock generator circuit has been provided for use
with a ceramic element connected between the clock input
and output pins. In addition, an external clock source may
be input at pin X 1NO , leaving X OUTO open. Circuit
M58497-XXXP
examples are shown in Fig. 3 and Fig. 4.
G,N
1 OOpF
Documentation Required Upon Ordering
The following information should be provided when order-
Tt----
GOUT
-T'
100pF
Vee (or Vss (OVlI
ing 'a custom mask.
(1) M58497-XXXP mask confirmation sheet
(2) ROM data ...................... 3 EPROM sets
(3) Oscillation frequency selection
240-520 kHz
XouTb
1) Verification of osci Ilation should be made at the timing
output T 2. In addition, the required circuit constants
will vary with the frequency and type of ceramic
element used.
Fig.3 Externally connected ceramic filter
On confirmation sheets
(4)
Frequency divider output selection (1 Hz/2Hz)
On confirmation sheets
M58497-XXXP
X,NO
XO UTO
SOl
4.5V - ,
External oscillator circuit
Fig. 4
5-38
• MITSUBISHI
"ELECTRIC
ov
n n r
U U U
External clock input circuit
MITSUBISHI MICROCOMPUTERS
MS8497-XXXP
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
INSTRUCTION CODE LIST (Note 1)
~D'I
'.
000000
HexadeCimal
notation
U 0
0,
-Do
0000
0001
0010
0011
0
1
2
3
NOP
SCOM
EIA
DIA
001110
000001
o
000010
o2
1
TLC
DIKS
SFK
SFS
000011
o3
000100
o4
SZB
SEY
0
0
SZB
SEY
1
1
SZB
SEY
2
2
SZB
SEY
3
3
4
EIB
DIB
lIE
SC
DETS
DLC
RC
lIE
XC
DETR
C:LC
lIE
SEY
8
EIT
SPO
lIE
SEY
9
DIT
lIE
SO
1011
A
8
STM
POF2
SPI
lIE
lIE
lIE
1101
C
0
POFI
SDET
OTAD
lIE
lIE
RD
1111
F
TTM
TCK
ADRT
TPW
lIE
lIE
4
SF
SEI
4
5
SF
SEI
5
SF
6
SEI
6
7
SF
SEI
7
8
RF
SEI
0
RF
SEY
SEI
Ri'"
10
10
SEY
SEI
2
RF
lIE
11
SEY
SEI
12
12
SEY
SEI
3
RF
lIE
4
RF
lIE
13
SEI
5
RF
lIE
14
14
SEY
SEI
6
RF
SZC
15
Note 1
SEI
3
lIE
SEY
E
SF
1
13
1110
3
9
11
1100
SEI
2
lIE
9
1010
SF
2
lIE
8
1001
SEI
lIE
7
1000
1
RTI
SEY
7
SF
1
RTS
6
0111
SEI
0
RT
SEY
6
SF
TYA
5
0110
0
XDP
SEY
5
SEI
o6
DEY
4
0101
o5
000110
INY
SEY
0100
000101
15
7
000111
001000
001001
o8
09
BL
BLA
BML
BMLA
-
RAR
BL
BLA
BML
BMLA
-
BL
BLA
BML
BMLA
lIE
BL
BLA
BML
BMLA
SEAM
BL
BLA
BML
BMLA
lIE
BL
BLA
BML
8MLA
TAY
8L
BLA
8ML
8MLA
AND
8L
8LA
8ML
BMLA
EXL
BL
8LA
BML
8MLA
lIE
8L
8LA
8ML
8MLA
CMA
8L
8LA
8MI_
BMLA
AM
8L
BLA
BML
8MLA
lIE
8L
8LA
BML
8MLA
lIE
o
7
001011
001100
001101
oA
oB
OC
00
TAM
XAMD
A
LA
0
0
0
0
TAM
XAMD
A
LA
1
1
1
1
TAM
XAMD
A
LA
2
2
2
2
TAM
XAMD
A
LA
3
3
3
3
TAM
XAMD
A
LA
4
4
4
4
TAM
XAMD
A
LA
5
5
5
5
TAM
XAMD
A
LA
6
6
6
6
TAM
XAMD
A
LA
7
7
7
7
SB
XAM
XAMI
A
LA
0
0
0
8
8
S8
XAM
XAMI
A
LA
1
1
1
9
9
S8
XAM
)(AMI
A
LA
2
2
2
S8
XAM
XAMI
3
3
3
R8
XAM
XAMI
0
4
4
R8
XAM
XAMI
1
5
5
RB
XAM
XAMI
2
6
6
R8
XAM
XAMI
3
7
7
-
TAB
A
12
A
8L
8LA
8ML
8MLA
AMC
8L
BLA
8ML
8MLA
AMCS
This list shows the machine codes and corresponding machine instructions.
13
A
14
A
15
111000
I
111111
-
OTRO
LXY
BM
BMA
B
BA
-
OTRO
LXY
BM
BMA
B
BA
-
OTRO
LXY
BM
BMA
B
BA
-
OTRO
LXY
BM
BMA
B
BA
-
OTRO
LXY
BM
BMA
B
BA
-
OTRO
LXY
BM
BMA
B
BA
-
OTRO
LXY
8M
8MA
B
8A
-
OTRO
LXY
8M
BMA
8
8A
-
OTRO
LXY
BM
BMA
B
BA
-
OTRO
LXY
8M
8MA
8
8A
-
OTRO
LXY
8M
8MA
8
8A
-
OTRO
LXY
8M
BMA
8
8A
-
OTRO
LXY
8M
8MA
B
8A
-
OTRO
LXY
8M
8MA
B
8A
-
OTRO
LXY
8M
8MA
B
8A
-
OTRO
LXY
8M
8MA
8
8A
10
LA
11
LA
12
LA
lIE
8MLA
110000
I
110111
10-17 18-1F 20-27 28-2F 30-37 38-3F
XAB
11
101000
I
101111
OE-OF
-
A
100000
I
100111
I
011111
TBA
10
011000
I
010111
IS
I
010000
I
001111
IK
8L
I 8ML
BLA
001010
13
LA
14
LA
15
Two-word instructions
03-00 indicate the low-order 4 bits of the machine code and 09-04 indicate
t~e
high-order 6 bits. Hexadecimal numbers are also shown that repreSecond word
sent the codes. An instructiol' may consist of one or two words, but only the
first word is listed. Code combinatio,lS ind.icated with asterisk (*) and bar
(-) must not be used.
• MITSUBISHI
"ELECTRIC
BL
11 Oxxxx YYYY
BLA
11 1xxxx
BML
10 Oxxxx YYYY
BMLA
10
XXXX
lxxxx XXXX
5-39
II
MITSUBISHI MICROCOMPUTERS
MS8497-XXXP
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
MACHINE INSTRUCTIONS
~
iNot€
1)
Instruction code
Mnemonic
Classification
D9 D8
D,D6D5 D•
"D
0
>:
Hexa'0
D 3 D 2 D,Do
decimal ci
z
j
LXY x,Y
01
1 x x x
Y Y Y Y
18y
1
u'"
>-
r;-
Functions
'0
Skip conditions
u
OJ
"'
LL
0
z
1
+
(X)..-x,
where,
x=0-7
(Y)..-y,
where,
y=0-1!)
Consecutively
described
X
2
INY
00
0010
0000
CJ:
DEY
00
0010
0001
x
020
021
1
TA8
T8A
00
00
1 001
1 001
o1 1 1
0100
097
094
.~
XA8
TAY
1001
01 1 0
1
1
(A)-(B)
-
X
1000
0101
096
085
1
1
(A)--(Y)
-
X
TVA
XOP
00
00
00
00
0010
0010
001 1
1
1
(Y)"-(A)
-
X
0010
023
022
1
1
(DP) ..... (DP')
-
X
TAM j
00
101 0
OJ
OAj
1
1
-
X
-
X
<{
*.s
*
'g>
cr:
QJ
I
j j
1
1
(Y)"-(Y)+1
-
X
1
1
(y)..-(y) -1
-
X
1
1
(A)"-(B)
-
X
1
1
(B)"-(A)
-
X
c
"'
0
XAM j
00
101 0
1 j j j
OA8
1
1
+
j
"'
1
XAMO j
2
XAMI j
S
(A)"-(M(DP»
(X)"-(X)Yi,
00
1 0 1 1
OJ
j j
OBj
1
i=0-7
where,
j=0-7
(A)-(M(DP»
(X)"-(X)Yj,
1
where,
(A)-(M(DP», (y)..-(y) -1
(X)..-(X) yj,
00
1 01 1
1 j j j
<{
0B8
1
1
+
j
cr:
LAn
AM
AMC
00
00
00
1 1 0 1
n n n n
1000
1 010
1000
1 1 1 0
OOn
08A
08E
where,
(y)..-(y)+ 1
(A)-(M(DP»,
(X)"-(X)Vj,
where,
where,
(Y)=15
X
(Y)= 0
X
j=0-7
j=0-7
1
1
(A)..-n,
1
1
(A)"-(A)+(M(DP»
1
1
(A)"-(A) +(M(DP» +(CY)
n=0-15
Consecutively
described
X
-
X
-
0/1
(Cy)..- Carry
AMCS
00
1000
1 1 1 1
08F
1
1
(A)"-(A) +(M(DP» +(CY)
(CY)= 0
0/1
Carry = 0
X
(Cy)..- Carry
u
';:;
~
~
An
00
SC
RC
XC
SZC
AND
EXL
CMA
00
00
00
00
00
00
RAR
00
00
1 1 00
0010
n n n n
0100
0010
0010
0101
001 1
1 1 1 1
1000
1000
01 1 0
1000
1 001
1001
01 1 0
01 1 1
0000
OCn
024
025
026
1
(A)"-(A)+n,
1
(CY)"-l
-
1
1
1
(Cy)..-O
-
0
SB i
00
1001
1 0 i i
-
(en
X
(A)"'" (A);\ (M(DP»
-
X
v (M(DP»
-
X
-
X
-
(Ao )
1
(CY)-(CY')
1
1
Skip if (CY)=O
1
1
1
1
(A)"-(A)
089
090
1
1
(A)"-(A)
1
1
098
n=0-15
(CY)= 0
1
03F
086
087
(An-, )"-(An)
(Cy)..-(Ao ),
c
where,
1
1
(A 3 )..-(CY)
1
1
(Mi{DP»"-l,
where, • i=0-3
-
X
1
1
(Mi(DP»..-O,
where,
-
X
1
1
Skip if (Mi(DP»=O, where,
+
0
i
.~
~c
RB i
co
SZB i
00
1 001
1 1 i i
09C
i=0-3
+
E
i
00
001 1
OOi i
03i
i=0-3
(Mi(DP»=O
X
where, i=0-3
~E
0
u
SEAM
SEY y
00
00
1000
0100
001 1
y y y y
083
04y
1
1
Skip if (M(DP»=(A)
1
1
Skip if (Y)=y,
where,
y=0-15
(M(DP»=(A)
X
(y) =y, where,
X
y=0-15
SEI n
00
01 01
n n n n
05n
1
1
Skip if ( A )=n, where,
n=0-15
(A) =n, where,
X
n=0-15
SCOM
5-40
00
0000
0001
001
1
1
Skip if (SCA=O)
• MITSUBISHI
.... ELECTRIC
SCA= 0
X
MITSUBISHI MICROCOMPUTERS
MS8497-XXXP
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
~
Instruction code
0, Os
Class
ification
B xy
u
0
~
Mnemonic
1 1
0,0 6 05 0,
Oxxx
OJ O2 0, Do
Yy YY
Hexadecimal
3xy
-
Functions
o
1 1 1
pppp
Oxxx
YYYY
07p
3xy
2
1 1
1 1
1 x x x
XXXX
38X
1
2
u
Ol
ro
LL
(PC L )+--16x+y
(PCH)<-15,
00
Skip conditions
-
X
--
X
-
X
-
X
-
X
-
X
-
X
-
X
-
X
-
X
(PC L )<-16x +y
(PCH )<-P
(PC L )<-16x +y
1
(PC L )<-16x+( A)
+
cD
x
(PC L )<-16x+( A)
(PCH )<-15,
(Note 21
f-----
BLA pxX
00
o
1 1 1
PPPP
1 1
1 x x x
XXX X
07p
38X
2
2 I (PCH)<-p
(PC L )<-16x+( A)
+
x
BM xy
1 0
Oxxx
y y y y
2xy
1
1
(Note 21
BML pxy
1i
00
o
1 1 1
pppp
1 0
Oxxx
y y y y
07p
2xy
1 0
1 x x x
XXXX
28X
-
I
~
.£
Misc.
Skip conditions
Functions
u
Cl
'"
u.
z
1
1
Enables interruption of I NTs signal.
-
X
1
1
Disables interruption of INTs signal.
-
X
X
1
1
Enables interruption of I NT T signal.
-
009
1
1
Disables interruption of I NTT signal.
-
X
1 010
OOA
1
1
(TM)--(A),
-
X
0000
1 1 1 0
OOE
1
1
Skip if (TM F /F) = 1
(TM F/F)=l
X
00
00
00
00
00
00
00
0000
0000
0000
0001
0000
0000
0000
1 1 1 1
OOF
OOC
OOB
01F
1
1
Skip if(CK F/F)=l
(CK F /F) = 1
X
1
1
(CK F /F)<-O, with no CK flag input
-
1
1
(PW F /F)<-O, with no PW flag input
-
1
1
Skip if (PW F/F)=l
01 1 0
006
1
1
(OET F/F)--l
-
o1
1 1
1 1 0 1
007
000
1
1
(OET
F/F)--o
-
X
1
1
Skip if (BD ouT ) = 1, (Skip if normal supply voltage apply)
(BOo UT ) = 1
X
00
0000
0000
000
1
1
No operation
-
X
1000
1001
E
i=
>-
0
(TM F /F)--o
6-bit prescaler presetting
1 100
1 01 1
1 1 1 1
X
X
(PW F/F)=l
X
X
Note 1. When a skip has been generated, the next instruction only is invalid and the program counter is not incremented by 2. Therefore, the number of cycles does
not change even if a skip is not generated.
2. Instructions Bxy, BAxX, BMxy and BMAxX execute the second function of the functions column when executed, provided that none of the instructions RT
RTS, Bl, BMl, BlA, or BMlA was executed after the execution of a BM or BMA instruction.
'
Symbol
Meaning
Meaning
Symbol
A
4-bit register (accumulator)
P(COMn)
Common output port for liquid crystal display
Ai
P(LCn)
PW F/F
Segment output port for liquid crystal display
l-bit power supply control flag display
BOo UT
Indicates the bits of register A. Where i= 0-1
4-bit auxiliary register
Battery detector signal
R(COMn)
Common register for liquid crystal display (4 bits)
CK F/F
l-bit l-second flag
R(LCn)
Segment register for liquid crystal display (25 bits)
CY
l-bit carry flag
S
4-bit I/O port
CY'
l-bi t carry stac k fi ag
SCA
Output of bit A of control counter for liquid crystal display
0
ll-bit output port
Oi
Indicates the bits of port D. Where i=0-3
The bit of port D addressed by Y
SKO
ll-bit stack register
O(Y)
SKl
l1-bit stack register
OP
7-bit data pointer composed of register Y, X
B
Y
4-bit register
X
3-bit register
OP'
7-bit data pointer
l-bit battery detector flag
OET F/F
Fi
a-bit output port
Indicates the bits of port F. Where i=0-7
F
K
4-bit I/O port
4-bit data of memory addressed by data pointer DP
Mi(DP)
A bit of data of memory addressed by data pointer DP
where i=0-3
PC
ll-bit program acounter composed of PCl, PCH
PCL
low-order 7 bits of the program counter
High-order 4 bits of the program counter
Po
4-bit output port
P,
4-bit output port
5-42
l1-bit stack register
TM
4-bit timer/counter
TM F/F
l-bit timer/counter flag
xx
2-bit binary variable
yyyy
4-bit binary variable
3-bit binary variable
mmm
M(OP)
PC H
SK2
nnnn
4-bit binary variable
II
2-bit binary variable
iii
XXXX
3-bit binary variable
4-bit unknown binary variable (the value doesn't affect
-(
V1\
-
X
xy
C
+
x
• MITSUBISHI
"ELECTRIC
Indicates direction of data flow
)
execution)
Indicates contents of register memory, etc.
Exclusive OR
AND
Negation
Indicates flag is unaffected by instruction execution
label used to indicate the address
Hexadecimal number C + binary number-X
MITSUBISHI MICROCOMPUTERS
M58497-XXXP
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
ABSOLUTE MAXIMUM RATINGS
Conditions
Parameter
Symbol
VCC
Supply voltage
VI
I nput voltage
Vo
Output voltage
Pd
Power dissipation
Topr
T5tg
Limits
Unit
-0.3-6.0
With respect to Vss
V
-0.3-V ee +0.3
V
o -Vee
V
300
mW
Operating free-air temperature range
-20-70
"C
Storage temperature range
-40-125
"C
Ta=25"C
RECOMMENDED OPE RATI NG CON 01 TI ONS
(Ta=-20-70°C, unless otherwise noted)
Limits
Parameter
Symbol
Unit
Min
Nom
Max
3
4.5
5.5
VCC
Supply voltage
Vss
Supply voltage
VLCO
Liquid crystal supply voltage
VIH
High-level input voltage
0. 7V CC
Vcc
VIL
Low-level input voltage
0
0.3V cc
V
fXIN
Oscillator freqLiency
240
520
kHz
f¢
Internal clock oscillator frequency
120
260
kHz
0
ELECTRICAL CHARACTERISTICS
II
V
V
1.3
V
455
V
(Ta=-20-70°C, Vcc=4.5V, VsS=OV, f X IN=455kHz,unless otherwise noted)
Limits
Symbol
Parameter
Unit
Test conditions
Min
Typ
Max
VOH
High-level output voltage, ports 0, K, and S
IOH = -10,uA
4
V
VOH
High-level output voltage, ports F, and P
IOH = - 200,uA
2.4
V
VOL
Low-level output voltage, ports 0, K, and S
IOL =1.8mA
0.5
V
VOL
Low-level output voltage, ports F, and P
IOL=1.8mA
0.5
V
VOH
High-level output voltage, port LC
VLCO = 1.3V,
Ta=25"C
4.3
4.5
VOH
High-level output voltage, port COM
VLCo =1.3V,
Ta=25"C
4.3
4.5
Vox
Medium output voltage, port COM (Note 1)
VLCO= 1.3V,
Ta=25"C
2.7
2.9
3.1
V
VOL
Low-level output voltage, port LC
VLCO=1.3V,
Ta=25"C
1.3
1.5
V
VOL
Low-level output voltage, port COM
VLCO= 1.3V,
Ta=25"C
1.3
1.5
Icc
Supply current for full operation
Ta=25"C,
Output pins open
0.4
Icc
Supply current for partial operation
Ta=25"C,
Output pins open
20
Oi
Input capacitance
VCC=VI =VO=VSS, f= 1MHz, 25mVrms
Oi( XIN)
Oscillator input capacitance
VSO
Battery voltage detection voltage range (Note 2)
VCC= Xourr=Vss,
f=1MHz,
10kQ :5:Rso:5:200kQ,
25mVrms
Ta=25"C
4
V
V
V
mA
J-LA
7
10
pF
7
10
pF
5.5
V
Note 1. VOX is the medi'Jm level of the 3-level output of port COM.
2_ The detection resistance RBO is connected between the Vss and BDI N pin.
3. Currents are taken to be positive when flowing into the IC with minimum and maximum values taken as absolute values.
•
MITSUBISHI
.... ELECTRIC
5-43
MITSUBISHI MICROCOMPUTERS
M58497 -XXXP
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
TIMING REQUIREMENTS
(Ta=-20-70·C. Vcc=3-55V.
Vss=ov. unless otherwise noted)
Limits
Symbol
Unit
Test conditions
Parameter
Min
Typ
Max
tSU(K-XIN)
Data setup time before clock input, port K inputs
0
tSU(S-XIN)
Data setup time before clock input, port S if"lpu ts
0
f.1S
tSU(INTA-XIN)
Data setup time before clock input, I NT A input
0
f.1S
tSU(INTe-XIN)
Data setup time before clock input, [NT s input
0
f.1S
th(K-XIN)
Data hold time after clock inpu t, port K inputs
th(S-XIN)
Data hold time after ciock input, port S inputs
th(lNTA-XIN)
Data hold time after clock input, INTA input
th(INTe-XIN)
Data hold time after clock input, INTs input
f¢=230kHz
(Note 1)
f.1S
0.4
/.15
0.4
/.15
0.4
/.1S
0.4
/.15
Note 1. f1> = 1 /2.fxIN which corresponds to the internal clock frequency.
SWITCHING CHARACTERISTICS
(Ta=-20-70·C. Vcc=3-55V.
Vss =IOV, unless otherwise noted)
Limits
Symbol
Parameter
Test conditions
Unit
Min
Max
Low-to-high-Ievel propagation time from clock input to port data output. port 0
f.=230kHz
2.2
Low-to-h:gh level propagation time from clock input
to port data output, port5 F, P, K, and S
RL =20kQ
2.2
High-to-Iow-Ievel propagation time from clock input to port data output, port 0
C L =100pF
0.7
1.5
/.15
Higil-to-Iow-Ievel propagation time from clock input
to port data output, ports F, P, K and S
(Note 2)
0.7
1.5
f.1S
Note 2. Measurement circuit
TIMING DIAGRAMS
SO-S3 (inputs)
INT A (input)
INTB (input)
00-010 (outputs)
5-44
Typ
• MITSUBISHI
.... ELECTRIC
f.1S
/.1S
MITSUBISHI MICROCOMPUTERS
M58497-XXXP
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
BASIC TIMING CHART
(Note 1)
~
Signal name
SYmbOl
M,
T,
State
II
\
Clock signal (Note 2)
¢
Timing output
T2
Port D output
Do -0 '0
Port F output
Fo -F)
~
Port P output
Po. P,
I'\.
Port K outpu t
Ko -K3
~
Port K input
Ko -K 3
Port S output
So -S3
Port S input
So -S3
Interrupt request input
Note 1.
2.
zzz:
INTA.INTa
Tz
T3
T4
\
\
\
~
)<)O"0) :XXXXXXXX')()(X)()(~
X
(Note 7)
(Note 8)
Note 6 When an OTRO instruction is executed, the output is latched.
7. Output voltage of port LC depends upon power supply VLCD for the liquid crystal display.
8. Output voltage of ·port COM has 3 levels depending on the power supply VLCD for the liquid crystal display.
•
MITSUBISHI
' " ELECTRIC
5-45
II
MITSUBISHI MICROCOMPUTERS
MS8497-XXXP
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
BRANCH AND SUBROUTINE CALL INSTRUCTION EXECUTION TIMING
~CYCle
Operation
Mi
~State
Tl
I
Tz
I
(Note 1)
Mi+l
T3
T4
Tz
Tl
I
M,+z
T3
T4
Tz
Tl
T3
T4
Instruction B xy(to be operated as the branch instruction, when the instruction BM or BMA was not executed before).
Program counter
ROM address
Execution of program
Execution of the branch instruction
Execution of the instruction stored in the branched address
---------------------------~
InstructionB xy(to be operated as the branch instruction to page15,when the instruction BMor BMAwas executed before).
~~I(PCL)+l
Program counter
ROM address
rr--
(IROM addre1ss) <- (PC)
Execution of program
Execution of the branch instruction
Execution of the instruction stored in tre branched address on page 15
Instruction BM xy (subroutine call instruction).
~
'''. H", H.o)1
(PCH)~14
Program counter
(pCL)~(PCL)+l
(PCL)~XY
ROM address
I
(ROM address) <- (PC)
)~,L
Stack register
Execution of program
~~(PCLl+
,rvLlT
~
I
1
(ROM addr[less) <- (PC)
I-:E~x-e-cu-t:""io-n-o"':"'f'"':"th-e-su"":b-ro-u-t:""in-e-ca'"':"I:-"1i-ns-t-ru-ct:-io-n+~Ex-e-cu-t:-,o..,j,n-o~f-:th-e-,-ns..,j,tr-u-ct"'",o-n-s:-to..,j,re-d':"',...n...th:-e.....lSu brou tl ne
1
ca II ed address
Instruction BL P,xy (branch instruction).
I
Program counter
~f"'+'
I
I
ROM address
(ROM address) <- (PC)
Execution of the
j
Execution of program
Page number is stored temporarily
Execution of branch instruction
instruction stored in the branched address
Instruction BML p,xy (subroutine call instruction).
I
r
Program counter
I
) ~ p I(PC )~(P6 l+ 1
( Temporary
reglster~
L
L
ROM address
M'dd'T' ~ (PCI
Stack register
Execution of program
Page number is stored ter1"'porarily
--;::::i (TempOr~(PCL)
(PCL)ix/eglster I
+
1
I
"',H;',)+'
(ROM address) <- (PC)
(ROM address) <- (PC)
~K' )~(SKo ~~(PC)
U
I
I
I
Execution of the instruction
Execution of the subroutine call instruction
stored in the subroutine called address
Note 1_ The Instructions SA, SMA, BlA and SMAl have the same execution timing as B, BM, Bl and SMl respectively as shown_ The only difference IS that (PCl) <- xy
is replaced by (PCl) <- x (A I.
INTERRUPT EXECUTION TIMING
Interrupt request input
Program counter
(Note 2)
INT A (Note 3)
(PC)
ROM address
Stack register
Execution of program
Note 2 When the instruction executed in the machine cycle M i+1 is a Bl, SMl, BlA or BMlA, the value of address 2 of page
a is stored in the program counter during M i+3 -
3 The interrupt request input INTB has the same execution timing as INTA _If the input is low level in the machine cycle M i - 1 and high level in th8 machine cycle Mi,
the interrupt is executed during the interrupt enable state_
5-46
• MITSUBISHI
"ELECTRIC
MELP 58-48 MICROCOMPUTERS
MITSUBISHI MICROCOMPUTERS
MELPS 8-48 MICROCOMPUTERS
FUNCTION OF MELPS 8-48 MICROCOMPUTERS
DESCRIPTION
The ME LPS 8-48 LSI fami Iy is a low-cost high-performance
single-chip microcomputer series. The functions have been
integrated. For example the CPU, ROM, RAM, I/O ports,
timer and other circuits are ali on one chip. The MELPS 848 family has the following three configurations to meet
the requirements of different applications for various ROM
and RAM capacities.
M5L8048-XXXP
ROM
1024 bytes
RAM
64 bytes
I/O
27 pins
M5 L8049-XXXP
ROM
2048 bytes
RAM
128 bytes
I/O
27 pins
M5L8748S
EPROM 1024 bytes
RAM
64 bytes
I/O
27 pins
Timer and interrupt inputs are also built into these
chips. The program memory capacity can easily be expanded to 4K bytes. The M5L8243P input/output expander
chip can be used to extend the I/O capability. The family
of microcomputers allows designers to fabricate systems
for applications simply and quickly.
The M5L8048-XXXP contains 1 K bytes of read only
memory and the M5L8049-XXXP contains 2K bytes. The
contents of the memory is set by a mask during manufacture. This makes it practical to mass produce ROMs containing customer developed programs.
The M5L8748S contains 1 K bytes of EPROM and is pincompatible with the M5L8048-XXXP. Its memory can be
electrically written and changed by the user. This chip can
be used while a system is being developed and subject to
modifications. Once the system has been checked out and
the program debugged, the program can be masked in the
M5L8048-XXXP.
_
A cross assembler, the MELPS 8-48, is available for use
with this family of microcomputers. Designers will find the
assembler convinient and easy to use.
DOO\02D3D.Os06D7
Pll) Ph
P14 P16
P20 P22 P24
P26
Pll Ph Pls Ph
P21
P21 P25 P27
t:l
ROREGIS~RO
w R1REGISTER
~ R2 REGISTER
1
2
~ :!~~g:~~~~: ~
RSREGISTERru;;3
R6REGISTER6
R7REGISTER7
RAM 64 BYTES
----------------------To
T, if.JT RESET PROG EA
x 1 X 2 ALE PSEN
55
AD WR
Fig. 1 Block diagram of M5L8048-XXXP
• MITSUBISHI
"ELECTRIC
6-3
iii
MITSUBISHI MICROCOMPUTERS
MELPS 8-48 MICROCOMPUTERS
FUNCTION OF MELPS 8-48 MICROCOMPUTERS
BLOCK DIAGRAM
PI, Ph PI, PI.
Ph Ph PI, Ph
pz,
P2,
pz,
P2.
(5V) Vee
(OV) Vss
~ ~~=~g:~~~=~
~ R2 REGISTER 2
~ :!~~g:~~~~: ~
I
R5REGISTE~R;;3J
R6REGISTER6
R7REGISTER7
RAM 128 BYTES
------------------------TO
T, iNT RESET PROG EA x I
X 2 ALE PSEN
55 RD iNA
Fig.2 Block diagram of M5L8049-XXXP
T,
RO REGISTER
R1 REGISTER
R2 REGISTER
R3REGISTER
R4 REGISTER
RSREGISTER
.0 R6REGISTER
R7REGISTER
f5
(5V) Vee
8
(OV) Vss
~
a
1
2
0
3,"
4
~
5 co
6
7
STACK
~ ROREGISTER 0
~ P.l REGISTER 1
o
R2REGISTER
~ R3REGISTER
2
3 -
R4REGISTER 4
~
RSREG.ISTER~~
R6REGISTER 6
R7REGISTER 7
RAM 64 BYTES
------------------------TO
T, INTRESETPROG EA
x 1 X 2 ALE PSEN 55
AD
WR
Fig.3 Block diagram of M5L8748S
6-4
• MITSUBISHI
"ELECTRIC
MITSUBISHI MICROCOMPUTERS
MELPS 8-48 MICROCOMPUTERS
FUNCTION OF MELPS 8-48 MICROCOMPUTERS
BASIC FUNCTION BLOCKS
Program Memory (ROM)
The MSL8048-XXXP and M5L8748S contain 1024 bytes
of ROM, in the case of the M5L8748S, it is EPROM and its
contents can easily be changed by the user. The MSL8049XXXP contains 2048 bytes of ROM. The program for the
users application is stored in this ROM. Addresses 0,3, 7 of
the ROM are reserved for special functions. Table 1 shows
the meaning and function of these three special addresses.
Table 1 Reserved, defined addresses and their
meanings and functions
can then freely use register bank1 (addresses 24"'31) without destroying or altering data of the main program. When
the interrupt processing is complete and control is returned
to the main program by the R ETR instruction, register
bank 0 (in this example) is automatically restored as the
working register bank at the same time the main program
counter is restored.
Addresses rr-31 have special functions, but when not
all of the registers are required, the ones not needed can be
used for general storage. This includes both banks of general-purpose registers and the stack.
Meaning and function
Address
The first instruction executed after a system reset.
USER RAM
32X 8
The first instruction executed after an external interrupt is
accepted.
--------~----------------------------------~
The first instruction executed after a timer interrupt is accepted.
32
31
1
R7
I
I
I
I
GENERAL-PURPOSE REGISTERS
REGISTER BANK 1
:
The ROM can be used to store constants and other 8-bit
fixed data in addition to the program. Instructions such as
MOVP A, @A and MOVP3 A, @A can be used to access
the constants and data. The data could be in the form of
tables, and can be easily looked up.
25
24
R1
RO
]
23
8-LEVI'OL STACK
16x 8
R7
Data Memory (RAM)
I
I
The MSL8048-XXXP and MSL8748S contain 64 bytes of
RAM. The MSL8049-XXXP contains 128 bytes of RAM.
The RAM is used for data storage and manipulation and is
divided into sections for more efficient processing. Addresses rr-7 and 24"'31 form two banks of general purpose
registers that can be directly addressed. Addresses rr-7
compose bank 0 and are numbered RO"'R7. Addresses
24"'31 compose bank 1 and are also numbered RO"'R7.
Only one bank is active at a time. The instructions SEL
RBO and SEL RB1 are used to select the working bank.
Fig. 1 shows the division of the RAM and its mapping.
Addresses 8"'23 compose an 8-level program counter
stack. The details for using the stack will be found in the
"Program Counter and Stack" section. Please refer to that
section for details.
The remaining section, addresses 32 and above, must
be accessed indirectly using the general-purpose registers
RO or R1. Of course all addresses can be indirectiy addressed usi ng the general-purpose registers RO and R 1.
A good practice to simplify programming is to reserve
general-purpose register bank 0 for use of the main program
and register bank 1 for interrupt programs. For example if
register bank 0 (addressed 0"'7) is reserved for processing
data by the main program, when an interrupt is accepted
the first instruction would be to switch the working registers from bank 0 to bank 1. This would save the data of
the main program (addresses 0"'7). The interrupt program
•
GENERAL-PURPOSE REGISTERS
REGISTER BANK 0
I
R1
}
RO
Fig.4 Data memory (RAM)
PROGRAM COUNTER (PC) AND STACK (SK)
The MELPS 8-48 program counter is composed of a 12-bit
binary counter as shown in Fig. S. The low-order 10 bits
can address 1024 bytes of memory. When the high-order 2
bits are zero, the internal, on chip memory is accessed. The
high .. order 2 bits can have the values 1"'3, which allows the
user to add up to three banks of 1024 bytes. The program
counter can address up to 4096 bytes of memory.
Addresses 8"'23 of RAM are used for the stack (program
counter stack). The stack provides an easy and automatic
means of saving the program counter and other control
information when an interrupt is accepted or a subroutine
is called. For example, if control is with the main program
and an interrupt is accepted, the contents of the 12-bit PC
(program counter) is saved in the top of the stack, so it can
be restored when control is returned to the main program.
In addition to the PC, the high-order 4 bits of the PSW
(program status word) are saved in the stack and restored
along with the PC. A total of 16 bits are saved, the 12-bit
MITSUBISHI
.... ELECTRIC
6-5
MITSUBISHI MICROCOMPUTERS
MELPS 8·48 MICROCOMPUTERS
FUNCTION OF MELPS 8-48 MICROCOMPUTERS
PC and 4 bits of the PSW. A 3-bit stack pointer is associated with the stack. This pointer is a part of the PSW and
indicates the top of the stack. The stack pointer indicates
the next empty location (top of the stack), in case of an
empty stack the top of the stack is the bottom of the stack.
The data memory addresses associated with the stack
pointer along with the data storage sequence are shown in
Fig.6.
Fig. 5 Program cou nter
RAM REGISTER NUMBER
(DATA MEMORY ADDRESS)
STACK POINTER
S2
S1
Sa
1
0
R23
I
R22
:
:
,,
:
:
o
1
o
0
,
1
,I
0
1
o
:
o
0
R21
R20
R 19
R18
R17
HIGH-ORDER 4 BITS STORED
ALONG WITH THE PC IN THE STACK
R16
R15
R14
I
I
I
I I
,,
R13
I
R12
,,
,
Rll
C
R10
AC : AUXILIARY CARRY (CARRY FROM THE
LOW-ORDER 4 BITS OF ALU)
FLAG 0
Fa
PSW(4)IPC a_11 R9
1 AC 1 Fa
C
BS 1 1
S21 S1
S2 }
S1
So
So
CARRY
BS: WORKING REGISTER BANK INDICATOR
PC4- /'PCo- 3 R8
MSB
LSB
Fig. 6 Relation between the program counter
stack and the stack pointer
6- 6
PROG RAM STATUS WORD (PSW)
The PSW (program status word) is stored in 8 bits of
register storage. The configuration of the PSW is shown in
Fig. 7. The high-order 4 bits of the PSW are stored in the
stack, along with the PC, when an interrupt is accepted or
a subroutine call executed. When control is returned to
the main program by RETR both the PC and the highorder 4 bits of PSW are restored. When control is returned
by RET only the PC is restored, so care must be taken to
assure that the contents of the PSW was not unintentionally changed.
The order and meaning of the 8 bits of the PSW are
shown below.
Bit 0"'2: Stack pointer (So, SI, S2)
Bit 3:
Unused (always 1)
Bit 4: Working register bank indicator
0= Bank 0
1 = Bank 1
Flag 0 (value is set by the user and can be tested)
Bit 5:
Auxiliary carry (AC) (it is set/reset by instructions
Bit 6:
ADD and ADC and used by instruction DA A).
Bit 7: Carry bit (C) (indicates an overflow after execution)
STACK POINTER
Fig. 7 Program status word
• MITSUBISHI
.... ELECTRIC
MITSUBISHI MICROCOMPUTERS
MELPS 8-48 MICROCOMPUTERS
FUNCTION OF MELPS 8-48 MICROCOMPUTERS
I/O PORTS
The MELPS 8-48 has three 8-bit ports, which are called
data bus, port 1 and port 2.
Port 1 and Port 2
Ports 1 and 2 and both 8-bit ports with identical properties. The output data of these ports are retained and do not
change until another output is loaded into them. When
used as inputs the input data is not retained so the input
signals must be maintained until an input instruction is
executed and completed.
Ports 1 and 2 so-called quasi-bidirectional ports have
a special circuit configuration to accomplish this. The
special circuit is shown in Fig. 8. All terminals of ports
1 and 2 can be used for input or output.
CPU
IN TE RNA L--+----t
BUS
Data Bus (Port 0)
The data bus is an 8-bit bidirectional port, which is used
with I/O strobed signals. When the data bus is used for
output the output data is latched, but if it is used for input
the data is not latched. Unlike ports 1 and 2, which can
have individual terminals in the input or output mode, all
terminals of the data bus are in the input or output mode.
When the data bus is used as a static port the OUTL instruction can be used to output data and the INS instruction to input data. Strobe pulse RD is generated while the
INS instruction is being executed or WR while OUTL is
being executed.
The data bus read/write using MOVX instructions, but
then the data bus is a bidirectional port. To write into the
data bus a WR signal is generated and the data is valid when
WR goes high. When reading from the data bus, an RD signal is generated. The input levels must be maintained until
RD goes high. When the data bus is not reading/writing, it
is in the high-impedance state.
CONDITIONAL JUMPS USING TERMINALS To,
T} and INT
RESET
WRITE
PULSE
Fig. 8 I/O ports 1 and 2 circuit
Internal on chip pull-up resistors are provided for all
the ports. Through the use of pull-up resistors, TTL standard high-level or low-level signals can be supplied. Therefore
each terminal can be used for both input and output. To
shorten switching time from low-level to high-level, when 1s
are output, a device of about 5kn or lower is inserted for
a short time (about 500ns when using a 6MHz crystal oscillator).
A port used for input must output all 1s before it reads
the data from the input terminal. After resetting, a port is
set to an input port and remains in this state, therefore it
is not necessary to output all 1s if it is to be used for input.
In short a port being used for output must output 1s before
it can be used for input.
The individual terminals of quasi-bidirectional ports
can be used for input or output. Therefore some terminals
can be in the input mode while the remaining terminals
of a port are in the output mode. This capability of ports
1 and 2 is convenient for inputting or outputting 1-bit or
data with few bits. The logical instructions ANL and ORL
can easily be used to manipulate the input or output of
these ports.
Conditional jump instructions are used to alter program
depending on internal and external conditions (states).
Details of the jump instructions for the ME LPS 8-48 can
be found in the section on machine instructions.
The input signal status of To, T 1 and INT can be checked by the conditional jump. instructions. These input
terminals, through conditional jump instructions such as
JTO and JNTO, can be used to control a program. Programs and processing time can be reduced by being able
to test data in input terminal rather than reading the data
into a register and then testing it in the register.
Terminal To, Tl and INT have other functions and uses
that are not related to conditional jump instructions. The
details of these other functions and uses can be found in
the section on terminal functions.
• MITSUBISHI
..... ELECTRIC
6-7
B
IiII
MITSUBISHI MICROCOMPUTERS
MELPS 8-48 MICROCOMPUTERS
FUNCTION OF MELPS 8-48 MICROCOMPUTERS
INTERRUPT
TIMER/EVENT COUNTER
The CPU recognizes an external interrupt by a low-level
state at the INT terminal. A "Wired-OR" connection can
be used for checking multiple interrupts.
The INT terminal is tested for an interrupt request at the
ALE signal output of every machine cycle. When an interrupt is recognized and accepted, control is transferred to
the interrupt handling program. This is accomplished by an
unconditional jump to address 3 of program memory,
which is the start of the interrupt handling program, at the
same time the program counter and 4 high-order bits of
PSW are automatically moved to the top of the stack.
The interrupt level is one, so the next interrupt cannot
be accepted until the current interrupt processing has been
completed. The RETR instruction terminates the interrupt
processing. That is to say, the next interrupt can not be accepted until the RETR instruction is executed. The next
interrupt can be accepted at the start of the second cycle of
the RETR instruction (2-cycle instruction). Time/event
counter overflow which causes an interupt request also will
not be accepted.
After the processing for an interrupt is completed control is returned to the main program. This is accomplished
by executing R ETR which restores the program counter
and PSW automatical and checks INT and the time/event
counter overflow for an interrupt request. If there is an
interrupt request, the control will not be returned to the
main program but will be transferred to the interrupt handling program.
An external interrupt has a higher priority than a timer
interrupt. This means that, if an external and timer interrupt request are generated at the same time, the external
interrupt has the priority and will be accepted first.
When a second level of external interrupt is required,
the timer interrupt, if not being used, can provide this.
The procedure for this is to first disable the timer interrupt, set the timer/event counter to FF 16 and put the CPU
in the event counter mode. After this ha! been done, if T 1
input is changed to low-level from high-level, an interrupt
is generated in address 7.
Terminal INT can also be tested using a conditional
jump instruction. For more details on this procedure, check
the "Conditional Jumps Using Terminals T (l, T 1 and INT"
section.
The timer/event counter for the MELPS 8-48 is an 8-bit
counter, that is used to measure time delays or count external events. The same counter is used to measure time delays or count external events by simply changing the input
to the counter.
The counter can be initialized by executing an MOV T,
A instruction. The value of the counter can be read for
checking by executing an MOV A, T instruction. Reset will
stop the counting but the counter is not cleared, so counting can be resumed.
The largest number the counter can contain is F F 16. If
it is incremented by 1 when it contains FF 16 , the counter
will be reset to 0, the overflow flag is set and a timer interrupt request is generated.
The conditional jump instruction JTF can be used to
test the overflow flag. Care must be used in executing the
JTF instruction because the overflow flag is cleared (reset)
when executed. When a timer interrupt is accepted, the
control is transferred to address 7 of program memory.
When both a timer and external interrupt request are
generated at the same time, the external interrupt is given
priority and will be accepted first by automatically jumping to address 3 of program memory. The timer interrupt
request is kept and will be processed when the external
interrupt has been completed and a PETR is executed. A
latched timer interrupt request is cancelled when a timer
interrupt request is generated. A timer interrupt request can
be disabled by executing a DIS TCNTI instruction.
The STRT CNT instruction is used to change the counter to an event counter. Then terminal T 1 signal becomes
the input to the event counter and an event is counted each
full cycle (low-high-Iow one event). The maximum rate that
can be counted is one time in 3 machine cycles (7.5J.ls
when using 6MHz crystal). The high-level at T1 must be
maintained at least 1/5 of the cycle time (500ns when
using 6MHz crystal).
6-8
• MITSUBISHI
"ELECTRIC .
MITSUBISHI MICROCOMPUTERS
MELPS 8-48 MICROCOMPUTERS
FUNCTION OF MELPS 8-48 MICROCOMPUTERS
The STRT T instruction is used to change the counter
to a timer. The internal clock signal becomes the input to
the timer. The internal clock is 1/32 of 400kHz (when
using 6MHz crystal) or 12.5kHz. The timer is therefore
counted up every 80ps. Fig. 9 shows the timer/event
counter.
The counter can be initialized by executing an MOV T,
A instruction. The timer can be used to measure 80ps20ms in multiples of 80ps. When it is necessary to measure
over 20ms (maximum count 256x80ps) of delay time the
number of overflows,one every 20ms, can be counted by
the program. To measure times of less than 80ps; external
clock pulses can be input through T 1 while the counter is
in the event counter mode. Every third (or more) ALE signal can be used instead of an external clock.
I
I
rONDI:IONAl
JUMP
MELPS 8-48 CYCLE TIMING
The output of the state cou nter is 1/3 the input frequency
from the oscillator. When a 6MHz crystal is used for input,
the output would be 2MHz (500ns). A eLK signal is generated every 500ns (one state cycle) which is used for the
demarcation of each machine state. The instruction ENTO
eLK will output the eLK signal through terminal To. The
input of the cycle counter is eLK (state cycle) and the output is an ALE signal which is generated every 5 state
cycles.
Fig. 11 Shows the relationship between clock and generated cycles.
One machine cycle contains 5 states with a eLK signal for demarcation of each state. The MELPS 8-48 instructions are executed in one machine cycle or two machine cycles. An instruction cycle can be one or two machine cycles
as shown in Fig.12 .
..---------,11
I
I JTF
I
I
TIMER
OVERFLOW
FLAG
T1
INTERRUPT ENABLE
INTERRUPT
REQUEST
Fig. 9 Timer/event counter
Fig.10 Clocking cycle generation
.J
~
51
(~1;\PUT
TO To)
500ns(WHEN USING A 6MHz CRYSTAL)
52
53
54
55
51
52
53
54
~~~~>-lL--I"l.-I1.~~
P5EN+---~~---+--~
1----1--....
RD
WR
PROG~--+-~--~~
Flg.11 Clock and generated cycle signals
INSTRUCTION EXECUTION
2 MACHINE CYCLES
1---+-+-_ _ _5.....:.D!I_s_ _ _ _- i
Fig.12 Instruction execution timing
• MITSUBISHI
"ELECTRIC
55,
MITSUBISHI MICROCOMPUTERS
MELPS 8-48 MICROCOMPUTERS
FUNCTION OF MELPS 8-48 MICROCOMPUTERS
RESET
SING LE-STEP OPERATION
The reset terminal is for resetting the CPU. A Schmitt trig-
The terminal SS on the MELPS 8-48 is provided to facili-
ger circuit along with a pull-up register are connected to it
tate single-step operation. In single-step operation, the CPU
on the chip. A reset can easily be generated by attaching a
stops after the execution of each instruction is completed
lJ.LF as capacitor as shown in Fig. 13. An external reset
and the memory address (12 bits) of the next instruction
pulse applied at RESET must remain at low-level for at
to be fetched is output through the data bus (8 bits) plus
least 50ms after power has been turned on and reached its
the low-order 4 bits of port 2 (P 20 "'P 23 ). The user can
normal level.
use this to trace the flow of this program instruction by
The reset function causes the following initialization
within the CPU.
instruction and will find this an aid in program debugging.
Single-step operation is controlled through SS and ALE as
shown in Fig. 14.
1. Program counter is reset to O.
2. Stack pointer is reset to O.
3. Register bank is reset to O.
4. Memory bank is reset to O.
SI NG LE-STEP
MODE
SV
5. Data bus is cleared to high-impedance state.
SV
6. Ports 1 and 2 are reset to input mode.
7. External and timer interrupts are reset to disable
state.
8. Timer is stopped.
MSL
8748S
9. Timer overflow flag is cleared.
10. Flags Fo and Fl are cleared.
ALE
11. Clock output for terminal To is disabled.
BUFFER
Note 1:
On the M5L8748S the RESET terminal. in addition to being used for the
reset function. is also used when reading and writing data in the EPROM
on the chip. Details on this will be found in the section on reading and
writing data in the M5L8748S.
(a) Example of single step circuit
DATA
Do- D8BUS
~
THE LOW-ORDER : 8 BITS OF PC
(PCa- PC ?)
MSL8748S
~----------~~--------~
THE
LOW-ORDER
4 BITS OF
PORT 2
P20- P 23
SV
THE HIGH-ORDER 4 BITS OF PC
(PCs--PC,,)
> ABOUT
•
~0
1
200k.Q
EXECUTING
I NSTR UCTI ON
A
H
+l F
tL
7fT
EJECUTING
STOP-----'Oo.""1Eo.:-:-~
INSTRUCTION
(b) Single-step operation timing
10V
Fig. 13 Example of a reset circuit
I. .
Fig.14 Single-step operation circuit and timing
A type D flip-flop with preset and reset terminals, as shown
in Fig. 11, is used to generate the signal for SS. When the
preset terminal goes to low-level, SS goes to high-level,
which puts the CPU in RUN mode. When the preset terminal is grounded it goes to high-level. Then SS goes to lowlevel. When SS goes to low-level, the CPU stops. Then when
the push-button switch is pushed, a pulse is sent to the
clock terminal of the type D flip-flop which turns SS to
high-level. When SS goes to high-level the CPU fetches the
6·· 10
• MITSUBISHI
~ELECTRIC
MITSUBISHI MICROCOMPUTERS
MELPS 8-48 MICROCOMPUTERS
FUNCTION OF MELPS 8-48 MICROCOMPUTERS
next instruction and begins to execute it, but then an ALE
signal is sent to the reset terminal of the type D flip-flop
which turns 55 to low-level. The CPU again stops as soon
WHEN SS IS LOW, THE CPU RECOGNIZES THAT
IT IS TO STOP,
as execution of the current instruction is completed. When
~
the push-button switch is again pushed, the cycle is repeated and the CPU is in single-step operation as shown in Fig.
WHEN THE
NEXT
INSTRUCTION IS FETCHED,
THE CPU SETS SWITCHES SO IT WI LL STOP AFTER
12. While the CPU is stopped in single-step operation, the
THE EXECUTION OF THE INSTRUCTION IS COMPLETED,
data bus and the low-order 4 bits of port 2 are used to output the memory address of the next instruction to be fetch-
~
ed. This interferes with input and output, but essential
WHEN ALE IS HIGH, THE MEMORY ADDRESS OF
input/output can be latched by using the rising edge of
THE NEXT INSTRUCTION TO BE FETCHED IS OUT-
A LE as clock.
PUT THROUGH THE DATA BUS (8 BITS)
AI~D
THE
LOW-ORDER 4 BITS OF PORT 2.
~
Central Processing Unit (CPU)
Central Processing Unit (CPU) is composed of an 8-bit para-
WHEN
SS
IS RETURNED TO HIGH LEVE L THE
CPU RECOGNIZES THAT IT IS IN THE RUN MODE.
llel arithmetic unit, accumulator, flag flip-flop and instruc-
THEN THE ALE SIGNAL GOES TO LOW-LEVEL
tion decoder. The 8-bit parallel arithmetic unit has cir-
WHICH INDICATES THE CPU IS IN THE RUN MODE
AND THAT IT IS EXECUTING INSTRUCTIONS.
cuitry to perform the four basic arithmetic operations
~
(plus, minus, multiply and divide) as well as logical operations such as AND and OR. The flag flip-flop is used to
IF THE CPU IS IN THE SINGLE-STEP MODE (PRE-
indicate status such as carry and zero. The accumu lator
SET TERMINAL GROUNDED), AS SOON AS ALE
GOES TO LOW-LEVEL, SS GOES TO LOW-LEVE L
(STOP). IF THE CPU IS THE RUN-MODE (PRE-
contains one of the operations and the result is usually
retained in the accumulator.
SET TERMINAL NOT GROUNDED).
SS
WILL RE-
MAIN AT HIGH-LEVEL.
Fig. 15 CPU operation in single-step mode
•
MITSUBISHI
.... ELECTRIC
6-11
MITSUBISHI MICROCOMPUTERS
MELPS 8-48 MICROCOMPUTERS
FUNCTION OF MELPS 8-48 MICROCOMPUTERS
MACHINE INSTRUCTIONS
t
I nstruction code
0)
Mnemonic
D, D6 D5 D.
Type
MOV A, jj:n
MOV A, PSW
MOV A, Rr
MOV A, @Rr
0
0
1
0
"7"8"5"4
D3 D2 D, Do
0
0
1
1
"3"2"'"0
1
1
1
1
1
0
0
0
1
1
1
1
1 r 2r , r 0
1
1
1
1
0
0
oro
>
MOV Rr, A
MOV Rr. t±n
MOV ""'Rr, A
1
1
1
1
0
0
0
1
1
1
0
1
"7"6"5"4
1
0
1
0
0
1
1
1
1 r 2 r,r O
1 r2 r, r 0
"3"2"'"0
0
0
oro
O)
~
~
MOV @'Rr, #n
MOVP A, @A
MOVP3 A, @A
MOVX @Rr, A
1
0
1
1
"7"8"5"4
0
0
Oro
"3"2"'"0
al
C
2
·2
1
1
1
1
1
1
1
1
Aa
+
r
1
1
B8
+
r
n
2
2
AO
+
r
1
1
BO
+
r
n
2
2
1
2
(A)~(M(A»
1
2
(A)~(M(page
1
2
80
+
r
1
2
28
+
r
1
1
20
+
1
1
30
+
1
1
03
n
2
2
68
+
1
1
60
+
1
1
2
2
78
+
1
1
70
+
1
1
Hexadecirre I
23
n
C7
Fa
+
r
FO
+
07
1
0
1
0
0
0
1
1
A3
1
1
1
0
0
0
1
1
E3
1
0
0
1
0
0
oro
90
~
XCH A, Rr
XCH A, @R.
XCHD A. @R.
ADD A, #n
(n
R.
ADDC A, #n
ADDC A, R.
ADDC A, @R.
6
12
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
0
"7"8"5"4
0
ADD A, Rr
ADD A,
1
0
0
1
1
0
1
1
0
0
0
1
"7"6"5"4
0
0
1
1
1
1
1
1
0
0
oro
1 r 2 r,r
0
0
0
0
0
0
O
oro
oro
1
1
"3"2"'"0
1 r 2 r,r O
0
0
0
0
oro
1
1
"3"2"'"0
1 r 2 r,r O
0
0
oro
·
·
·
·
·
·
AO
Description
0
z
(A)~n
Transfers data n to register A.
(A)~(PSW)
Transfers the contents of the program status
word to register A.
(A)~(Rr)
Transfers the contents of register R, to register A.
r= 0 - 7
Transfers the contents of memory location,
of the current page, whose address is in register R r to register A.
(A)~(M(Rr»
r=O-1
~
(PSW)
(A)
(O)~(A'). (AO)~(A6)
,)
Transfers the contents of register A to the
program status word.
U
(Rr)~(A)
Transfers the contents of register A to register R r.
r=0-7
(Rr)~n
Transfers data n to register R,.
r=0-7
(M
Transfers the contents of register A to memory location. of the current page, whose address is in register R ,.
(Rr))~(A)
r=O-1
Transfers data n to memory location, of the
current page, whose address is in register R,.
r=O-1
Transfers the data of memory location, of
the current page, whose address is in register
A to register A.
Transfers the data of memory location, of
page 3. whose address is in register A to
register A
3. A»
Transfers the contents of register A to memory location, of the current page, whose
address is in register R,.
(Mx(Rr))~(A)
r=O-1
Transfers the contents of memory location.
of the current page, whose address is in register R, to register A.
(A)~(Mx(Rr»
,=0-1
(A)~~(Rr)
Exchanges the contents of register Rr with
the contents of register A.
r=0-7
Exchanges the contents of memory location.
of the current page, whose address is in register R r with the contents of register A.
(A)~(M(Rr»
r=O-1
(Ao-A3)-----(M (Rro-Rr3»
r=O-1
(A)
~-
(A) + n
(A)~(A)+(Rr)
r=0-7
(A)
1 3
n
0)
0
(M(Rr»~n
r
MOVX A, @Rr
Function
u
r
MOV PSW, A
Effected
carry
~
~
(.A)+(M(Rr»
r=O-1
(A)~(A)\-n+(O)
(A)
~
()
0
1
0
0
1
0
0
1
0
0
1
0
0
1
(A)+(Rr)+ (0)
r=0-7
(A) ~ (A)+(M (Rr»
+ (0)
r--O-l
• MITSUBISHI
"ELECTRIC
'+
1
Exchanges the contents of the low-order four
bits of register A with the low-order four
bits of memory location. of the current
page, whose address is in register R r .
Adds data n to the contents of register A
and sets the carry flags to 1 if there is an
overflow otherwise resets the carry flags
to O. The result is stored in register A.
Adds the contents of register R r to the contents of register A and sets the carry flags to 1 if
there is an overflow otherwise resets the carry
flagstoO. The result is stored in register A.
Adds the contents or register A ana tne contents of memory location, of the current page,
whose address is in register A and sets the carry
flags to 1if there is an overflow otherwise resets
thecarryflagstoO.Theresult is stored in register
A.
Adds the carry and data n to the contents of
register A and sets the carry flags to 1 if
there is an overflow otherwise resets the
carry flags to O. The result is stored in register A.
Adds the carry and the contents of register
Rr to the contents of register A and sets the
carry flags to 1 if there is an overflow
otherwise resets the carry flags to O. The
result is stored in register A.
Adcs the carry and the contents or memory
location,ofthe current page. whose address is
in register Rr to the contents of register Aand
sets the carry flags to 1 if there IS an overflow
otherwise resets the carry flags to O. 1 he resu It
is stored in register A.
MITSUBISHI MICROCOMPUTERS
MELPS 8-48 MICROCOMPUTERS
FUNCTION OF MELPS 8-48 MICROCOMPUTERS
I,\em
ITY~
Instruction code
Q)
Mnemonic
ANl A, :f:l:n
Hexadecimal
o
1
0
1
0
0
1
1
>
OJ
ANl A, @Rr
0
ORl A, :f:l:n
ORl A, Rr
ORl A, - 6
U
Description
Q)
co
0
«SP»
(SP)
2
2
~
(PO) (PSW4- PSW7)
~(SP)+l
(POo-lO)~
(POll)~
m
m
MBF
"5
Q)
c:
';
RET
1
0
0
0
0
0
1
1
83
~
1
RETR
IN A, Pp
OUTl Pp, A
ANl Pp, #n
1
0
0
1
0
0
0
0
0
0
1
0
1
0
1
1
"7"8"5"4
ORl Pp, #n
1
0
0
0
"7"8"5"4
:::J
;-
1
0
1
1
1
0
o
o
o
1
1
PI Po
PIPO
PI Po
"3"2"1"0
1
o
PI Po
"3"2"1"0
93
2
2
1
2
(A)~(BUS)
Enters the contents of data bus (port 01
to register A
1
2
(BUS)~(A)
Output latches the contents of register A
data to data bus (port 01
2
2
(BUS)
~
(BUS) 1\ n
Logical ANDs the contents of data bus
(port 01 and data n. Outputs the result to
data bus (port 01
2
2
(BUS)
~
(BUS) V n
Logical ORs the contents of data bus (port
0) and data n. Outputs the result to data
bus (port 01
p
n
0
0
0
0
1
0
02
1
0
0
1
1
0
0
0
98
MOVDA, Pp
0
0
0
0
0
1
1 PI Po
(PSW4-PSW7)~«SP»
88
+
0
0
(PC)
n
88
n
OC
+
PIPO
0
0
1
1
1
1 PI Po
(Pp)
~(A)
1
1
0
0
1
1
1 PIPO
9C
+
PIPO
Logical ANDs the contents of Pp and data
n. Outputs the result to Pp
(Pp)~(Pp)l\n
p=1-2
(Pp)~(Pp)Vn
Logical ORs the contents of Pp and data
n. Outputs the result to Pp
p=1-2
Inputs the contents of Pp
to the low-order 4 bits
of register A and inputs 0
to the high-order 4 bits
of register A.
2
1
2
1
2
PIPO
ANLD Pp, A
Output latches the contents of register A to
Pp
p=1-2
(Ao-A3)~(PPO-PP3)
3C
+
Loads the contents of Pp to register A.
p=1-2
(A4-A7)~O
MOVD Pp, A
p=4-7
(PPo- PP3)~( Ao -A3)
Outputs the low-order 4
bits of register A to Pp.
p=4-7
(PPO-PP3)~( PPO-PP3) 1\( Ao-A3)
p=4-7
ORlD Pp, A
1
0
0
0
1
1 PI Po
The SP is decremented by 1. The program
counter and the 4 high-order bits of the
PSW are restored with the saved data in the
stack indicated by the stack pointer. The
interrupt becomes enabled after the execution is completed.
2
0
0
(SP) - 1
2
OUTl BUS, A
1
~-
+P
n
08
"3"2"1"0
(SP)
(A)~(Pp)
98
0
"7"8"5"4
«SP»
2
0
"3"2"1"0
~
1
0
0
(PC)
38
+
P
1
0
(SP)-l
2
0
0
~
1
0
1
The SP is decremented by 1. The program
counter is restored to the saved setting in
the stack indicated by the stack pointer.
The PSW is not changed and interrupt disabled is maintained.
(SP)
08
+
P
0
ORl BUS, #n
Calls subroutine from address m. The program counter and the 4 high-order bits of
the PSW are stored in the address indicated
by the stack pointer (SP). The SP is incremented by 1 and m is transferred to PCoPC IO and the MBF is transferred to PC" .
2
0
"7"8"5"4
a
z
1
INS A, BUS
ANl BUS, #n
2
AO
8C
+
PIPO
(PPO-PP3)~(PpO-PP3)V
1
2
p=4-7
• MITSUBISHI
"ELECTRIC
(Ao-A 3)
Logical ANDs the 4 loworder bits of register A
and the contents of Pp.
Ppcontains the result.
Logical ORs the 4 Ioworder bits of register A
and the contents of Pp.
Pp contains the result.
Pp's
used
for multiplying 8243
ports are P4
-P 7 ·
Correspondenceto Pl.
p, is shown
below.
P4"'P1 P2 =OO
PS"'P1 P2 =OI
P6"'P1 P2 =10
P7"'P1P2= 11
6-15
MITSUBISHI MICROCOMPUTERS
MELPS 8-48 MICROCOMPUTERS
FUNCTION OF MELPS 8-48 MICROCOMPUTERS
ts
I nstruction code
0
Hexadecimal
Effected
carry
(l)
>- 0U
co
Function
(l)
C
AC
Descri pt ion
a
07 06 05 04
03 D2 0 1 Do
EN I
0
0
0
0
0
1
0
1
05
1
1
(INTF)~
DIS I
0
0
0
1
0
1
0
1
1 5
1
1
(INTF)
SEl RBo
1
1
0
0
0
1
0
1
C5
1
1
(BS)~O
SEl RBl
1
1
0
1
0
1
0
1
05
1
1
(BS)~
SEl MBo
1
1
1
0
0
1
0
1
E5
1
1
(MBF)~
SEl MBl
1
1
1
1
0
1
0
1
F 5
1
1
(MBF)~1
ENTO ClK
0
1
1
1
0
1
0
1
75
1
1
10 1 0
0
0
0
1
0
42
1
1
(A)~(T)
Transfers the contents of timer/event counter to register A.
(T)~(A)
Transfers the contents of register A to timer/
event counter.
Typ
~
ill
Mnemonic
1
z
Enables outside interrupt.
~O
Disables outside interrupt.
Selects working register bank O.
1
Selects working register bank 1.
u
MOV A, T
~
0
Selects memory bank O.
Selects memory bank 1.
Enables output of clock signal from terminal
To
MOV T, A
0
1
1
0
0
0
1
0
62
1
1
ST.RT T
0
1
0
1
0
1
0
1
55
1
1
Starts timer operation of timer/event counterm. Minimum count cycle is BOj.ls.
STRT CNT
0
1
0
0
0
1
0
1
45
1
1
Starts operation as event counter of time/
event counter. Counts up when terminated
T 1 changes to input high-level for input lowlevel. Minimum count cycle is 7.5j.1s.
STOP TCNT
0
1
1
0
0
1
0
1
65
1
1
Stops operation of timer or event counter.
EN TCNTI
0
0
1
0
0
1
0
1
25
1
1
(TCNTF)~
1
Enables interrupt of timer/event counter.
DIS TCNTI
0
0
1
1
0
1
0
1
35
1
1
(TCNTF)~
0
Disables interrupt of timer/event counter.
Resets interrupt fl ip-flop of CPU which is
set during the CPU stands-by. Timer overflow flag isn't affected.
NOP
0
0
0
0
0
0
0
0
00
1
1
8
~8
e
~
~
f.=
iii
~
No operation. Execution time is 1 cycle.
Note 1: Executing an instruction may produce a carry loverflow or underflow). The carry may be disregarded Ilost) or it may be transferred to C/AC (saved). The saving of
a carry is not shown in the function equations, but is instead shown in the carry columns C and AC. The decail affection of carries for instructions ADD AD DC and
DA is as follows:
IC) +- 1
at overflow of the accumulator is produced.
(C) +- 0
at no overflow of the accumulator is produced.
lAC) +- 1
at overflow of the bit 3 of the accumulator.
lAC) +- 0
at no overflow.
2- The contents of ST4 -ST 7 is read when the host computer reads the status of M5LB041A-XXXP.
6 -16
• MITSUBISHI
.... ELECTRIC
MITSUBISHI MICROCOMPUTERS
MELPS 8-48 MICROCOMPUTERS
FUNCTION OF MELPS 8-48 MICROCOMPUTERS
Symbol
Meaning
Symbol
A
8-bit register (accumlator)
PC
Meaning
Program counter
Ao-A3
The low-order 4 bits of the register A
PCO-PC7
The low-order 8 bits of the program counter
A4- A7
The high-order 4 bits of the register A
PCg-PCIO
The high-order 3 bits of the prcgram counter
Ao-An,An+1
The bits of the register A
PSW
Program status word
b
The value of the bits 5-7 of the first byte machine code
Rcgister designator
b7 b6 bS
The bits 5-7 of the first byte machine code
Rr
BS
Register bank select
r
Register number
BUS
Corresponds to the port 0 (bus I/O port)
rO
The value of bit 0 of the machine code
r2 rl rO
The value of bits 0-2 of the machine code
AC
Auxiliary carry flag
S 2S 1 S 0
The value of bits 0-2 of the stack pointer
C
Carry flag
SP
Stack pointer
DBB
Data bus buffer
ST4-ST7
Bits 4-7 of the status register
STS
System status
Fo
Flag 0
T
Timer / event counter
Fl
Flag 1
To
Test pin 0
Test pin 1
INTF
Interrupt flag
Tl
IBF
Input buffer full flag
TCNTF
Timer / event counter overflow interrupt flag
m
The Value of the l1-bit address
TF
Timer flag
m7mSmSm4m3m2mlmO
mlO m 9 mg
(M (A»
The second byte (low-order 8 bits) machine code of the
11 -bit add ress
The bits 5-7 of the first byte (high-order 3 bits) machine
code of at he 11 -bit address
The content of the memory location addressed by the register A
:j:j:
Symbol to indicate the immediate data
@
Symbol to indicate the cuntent of the memory location
(M (Rr»
The content of rhe memory location addressed by the register Rr
(Mx(Rr»
MBF
The content of the external memory location addressed
by the register Rr
Memory bank flag
address by the register
I
<--
Shows direction of data flow
+----+
Exchanges the contents of data
n
The value of the immediate data
(
n 7n Sn Sn 4n 3n 2n 1n 0
The immediate data of the second byte machine code
1\
Logical AND
OBF
Output buffer full flag
V
Inclusive OR
V
Exclusive OR
P
Port number
-
Negation
Pp
Port designator
0
Content of flag is set or reset after execution
PIPO
The bits of the machine code corresponding to the port number
• MITSUBISHI
"ELECTRIC
)
Contents of register. memory location or flag
6-17
MITSUBISHI MICROCOMPUTERS
MELPS 8-48 MICROCOMPUTERS
FUNCTION OF MELPS 8-48 MICROCOMPUTERS
I nstruction Code List
0000
0000
Hexadecimal
0
0
NOP
0001
0010
0011
0100
2
3
4
INC
0101
5
0110
6
0111
7
1000
1001
1010
1011
1100
1101
1110
1111
8
9
A
B
C
0
E
F
XRL
ANL
@RO
A,@RO
INC
ANL
0001
0010
2
0011
3
0100
4
0101
5
0110
6
0111
7
1000
8
1001
9
1010
A
1011
B
1100
C
1101
0
1110
E
1111
F
A
A
A
ANL
ADD
A,RO
A,RO
ANL
ADD
A,Rl
A,Rl
ANL
ADD
A,R2
A,R2
ANL
ADD
A,R3
A,R3
ANL
ADD
A,R4
A,R4
ANL
ADD
A,RS
A,RS
ANL
ADD
A,RS
A,RS
ANL
ADD
A,R7
A,R7
A
II
2-byte. 2-cycle instruction
l-byte. 2-cycle instruction
6-18
• MITSUBISHI
;"ELECTRIC
MITSUBISHI MICROCOMPUTERS
MELPS 8-48 MICROCOMPUTERS
DEVELOPMENT OF MASK-PROGRAMMABLE ROMs
GENERAL INFORMATION
This information explains how to specify the object
program for the automatic design system for mask ROMs.
This system for mask ROM production has been developed
to accept a customer's object program specifications for the
automatic design system for a mask ROM.
The main segments of the automatic design system are:
1. The plotter instructions for mask production.
2. A check list for verifing that the customer's specifications have been met.
3. A test program to assure that the production ROMs
meet specifications.
An EPROM in which a program is stored is used for a
customer's specifications. A separate (set of) EPROM (s)
should be produced for each object program.
Three sets of EPROM(s) should be supplied with the
confirmation material.
3. All the data stored in the EPROM are considered as valid
and processed to make masks.
ITEMS TO CONFIRM FOR ORDERING
1. Specify the type number M5 L8048-XXXP or M5L8049XXXP. The 3-digit number XXX will be assigned by
Mitsubishi.
2. Cleary indicate the type number of EPROM and address
designation letter symbols A and B on the supplied
EPROMs.
EPROM SPECIFICATIONS
1. The Mitsubishi M5L2708K, M5L2716K, M5L2732K or
M5L8748S are standard, but Intel 2708, 2716, 2732,
8748 or equivalent devices may be used.
2. The high-level data of both data outputs and address
inputs of the supplied EPROM will be programmed as
'1', and low-level as '0'.
MASK ROM DEVELOPMENT FLOW CHART
FROM CUSTOMER
MITSUBISHI ELECTRIC
-0
ROM TEST PROGRAM
LARGE
TESTER
• WATER
TEST
• FINAL
TEST
1 - - - - - - - 1 . QA TEST
• MITSUBISHI
.... ELECTRIC
6-19
MITSUBISHI MICROCOMPUTERS
MELPS 8-48 MICROCOMPUTERS
DEVELOPMENT OF MASK·PROGRAMMABLE ROMs
MELPS 8-48 MASK-PROGRAMMABLE ROM CONFIRMATION MATERIAL
SINGLE-CHIP 8-BIT MICROCOMPUTERS M5L8048-XXXP, M5L8049-XXXP
MITSUBISHI ELECTRIC
Signature
Customer
Company name
Prepared
Company address
Tel
Company contact
Date
1----
Approved
The single-chip microcomputer type number to order and
checking.J in the boxes. Three sets of EPROMs should be
the type of EPROMs to be supplied should be specified by
supplied.
~r
2708
2716
2732
8748
D M5L8048- XXXP
D A(OOO 16-3FF 16)
D A(OOO 16-3FF 16)
DA(00016- 3FF 16)
D A(OOO 16-3FF 16)
D M5L8049- XXXP
D A(OOO 16- 3FF 16)
8(400 16-7FF 16)
D A(00016-7FF 16)
D A(00016-7FF 16)
Single-chip
microcomputer type number
Note 1 The high-level data of both data outputs and address inputs of the supplied EPROM will be programmed as '1', and low-level as '0'.
2 Cleary indicate the type number of EPROMs and address designation letter symbols A and B on the supplied EPROMs.
3 The data of the addresses in parentheses on the EPROM are programmed onto the ROM.
4 The data from each PROM in the set is compared and if 2 of the 3 are equal, the equal value w;11 be programmed into the ROM. When the 3 values are
different programming is halted and the customer is notified of the error. The error report will show the address and data.
CUSTOMER'S IDENTIFICATION MARK
If you require a special identification mark, please specify in the following format.
I I
Mitsubishi
Note 5
6
Ie
type number
A mark field shou Id start with the box at the extreme righ:
The identification mark should be no more than 12 characters consisting of
alphanumeric characters (except J.I. and 0) or dashes
COMMENTS
6 .~- 20
• MITSUBISHI
.... ELECTRIC
-
MITSUBISHI MICROCOMPUTERS
MSL8048.. XXXP, MSL803SLP
SINGLE-CHIP a-BIT MICROCOMPUTER
DESCRIPTION
The M5L8048-XXXP and M5L8035LP are 8-bit parallel
microcomputer fabricated on a single chip using high-
PIN CONFIGURATION (TOP VIEW)
TEST PIN 0 To
speed N-channel silicon-gate ED-MOS technology.
*
Vee (5V)
1
39 ~ Tl
CLOCK INPUT 1 Xl-+ 2
TEST PIN 1
CLOCK INPUT 2 X2 -+ 3
FEATURES
RESET INPUT RESET-+ 4
•
Single 5V power supply
•
•
I nstruction cycle .....
Basic machine instructions:
l-byte instructions: 68
2-byte instructions: 28
SINGLE-STEP INPUT SS -+ 5
. 2.5ps (min)
....... 96
REQ~~H~~~0t
INT-+ 6
EXTERNAL ACCESS EA -+ 7
READ RD _
STOR~R~NGfB1~
•
Direct addressing ...... .
. up to 4096 bytes
•
Internal ROM . . . . . . . . .
(for M5L8048-XXXP only)
1024 bytes
•
•
Internal RAM . . . . . . . . .
Built-in timer/event counter
•
•
I/O Ports . . . . . . . . . . . . . . .
Easily expandable Memory and I/O
•
•
. 8 levels
Subroutine nesting . . . . . . . . . . . .
External and timer/event counter interrupt. 1 level each
PSEN WRITE WR _
LATCHA~~~~t~
8
9
'0
I/O PORT 1
ALE -
11
64 bytes
27
.. 8 bits
*
26
DATA BUS
. 27 lines
P1 0
Voo (5V)
25 -+PROG
r/~TERNAL
CONTROL
•
•
Low power standby mode
External RAM . . . . . . . . . . . . . . . . . . . . . 256 bytes
•
Interchangeable with Intel's P8048 and P8035L in pin
configuration and electrical characteristics
: ::~:t!~oU:~~: 2MI
22 "
( 0 v) Vss
----.. _ _ _ _ _- r21-
P2 1
*P20
Outline 40Pl
FUNCTION
APPLICATION
The M5L8048-XXXP and M5L8035LP are integrated 8-bit
•
Control processor or CPU for a wide variety of appli-
CPU, with memory (ROM, RAM) and tirr.er/event counter
cations
interrupt all contained on a single chip.
BLOCK DIAGRAM
Pl()
Ph P14
P16
P20 P22 P24 P26
Pl1 Ph Ph Ph
P21 P23 Pls P27
T,
RO REGISTER 0
Rl REGISTER 1
R2REGISTER 20
R3REGISTER3 ~
R4REGISTER4 ~
RSREGISTER5 ell
o R6REGISTER6
R7REGISTER7
ffi
8
:!j
STACK
~
ROREGISTERo
w 'Rl REGISTER 1
~ R2REGISTER2
~! R3REGISTER 3 R4REGISTER4 ~
RSREGISTERs
R6REGISTER6
R7REGISTER7
~u
RAM 64 BYTES
-----------------------TO
T,
iNT
RESET PROG EA
X 1
X? ALE PSEN
_
55 RD WR
• MITSUBISHI
.... ELECTRIC
6-21
MITSUBISHI MICROCOMPUTERS
MSL8048-XXXP, MSL803SLP
SINGLE-CHIP a-BIT MICROCOMPUTER
PIN DESCRIPTION
Pin
Name
Input or Output
Function
VSS
Ground
Normally connected to ground (OV).
Vee
Main power supply
Connected to 5V power supply.
VDD
Power supply
® Used for memory hold when Vee is cut.
PROG
P10-P17
Program
Port 1
Ci) Connected to 5V power supply.
Output
Input/output
Quasi-bidirectional port. When used as an input port, FFI6 must first be output to this
port. After reset, when not used as an output port nothing can be output.
Input/output
P20-P27
Strobe signal for M5l8243P I/O Expander.
Port 2
Output
CD
The same as port 1.
®
P2 o-P2 3 output the high-order 4 bits of the program counter when using external
program memory.
Input/output
@ P2o-P2 3 serve as a 4-bit I/O expander bus for the M5l8243P.
CD Provides true bidirectional
bus transfer of instructions and data between the CPU and
external memory. Synchronizing is done with signals RiS/WR. The output data is
latched.
® When
00-07
Data bus
using external progra'Tl memory the output of the low-order 8 bits of the pro·
gram counter are synchronized with ALE. After that the transfer of the instruction
Input/output
code or data from external program memory is synchronized with PSE N.
@ The output of addresses for data using external data rr:emory is synchronized with
ALE. After that the transfer of data with the external data memory is synchronized
with RDIWR.
(MOVX A, @Rr and MOVX @Rr, A)
CD Control
To
Test pin 0
(JTO m and JNTO m)
Output
Tl
Test pin 1
®
Used for outputting the internal clock signal. (ENTO ClK)
CD
Control signal from an external source for conditional jumping in a program. Jump-
®
When enabled event signals are transferred to the timer/event counter. (STRT CNT)
Input
ing is dependent on external conditions. (JT1 m and JNT1 m)
CD
INT
Interrupt
Input
Control signal from an external source for conditional jumping in a program. Jump·
ing is dependent on external conditions. (JNl m)
®
RO
signal from an external source for conditional jumping in a program. Jump·
ing is dependent on external conditions.
Input.
Used for external interrupt to CPU.
Read control signal used when the CPU requests data from external data memory or exRead control
Output
ternal devices to be transferred to the data bus.
(MOVX A,@Rrand INS A, BUS)
--
WR
Write control signal used when the CPU sends data through the data bus to external data
Write control
Output
memory or external device.
(MOVX @R, A and OUTl BUS, A)
RESET
Reset
ALE
Address latch enable
PSEN
Program store enable
Input
Output
Output
SS
Single step
Input
EA
External access
Input
Control used to initialize the CPU.
A signal used for latching the address on the data bus. An ALE signal occurs once during
each cycle.
Strobe signal to fetch external program memory,
Control signal used in conjunction with ALE to stop the CPU through each instruction,
in the single step mode.
CD Normally maintained at OV .
® When the level
is raised to 5V, external memory will be accessed even when the ad-
dress is less than 40016 (1024). The M5l8035lP is raised to 5V.
Xl. X2
6-22
Crystal inputs
Input
External crystal oscillator or RC circuit input for generating internal clock signals. An
external clock signal can be input through XI or X2 •
• MITSUBISHI
.... ELECTRIC
MITSUBISHI MICROCOMPUTERS
MSL8048-XXXP, MSL803SLP
SINGLE-CHIP 8-BIT MICROCOMPUTER
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Conditions
Unit
Limits
Vee
Supply voltage
-0.5-7
V
Voo
Supply voltage
- 0.5-7
V
-0.5-7
V
With respect to Vss
VI
Input voltage
Vo
Output voltage
Pd
Power dissipation
Topr
Operating free-air temperature range
Tstg
Storage temperature range
Ta=25"C
RECOMMENDED OPERATING CONDITIONS
-0.5-7
V
1.5
W
0-70
"C
-65-150
"C
(Ta=0-70"C. unlessotherwisenoted)
Limits
Symbol
Parameter
Unit
Min
Nom
Max
Vee
Supply voltage
4.5
5
5.5
VOO
Su pply voltage
4.5
5
5.5
VSS
Supply voltage
VIHl
High-level input vOltage, except Xl, X2 and RESET
V
V
V
0
VIH2
High-level input voltage, except Xl, X2 and RESET
VIL
Low-level input voltage
ELECTRICAL CHARACTERISTICS
2
Vee
V
3.8
Vee
V
-0.5
0.8
V
(Ta=0-70"C.
Vee=Voo=5V± 10%.
VSS=OV.
unless otherwise noted)
Limits
Symbol
Parameter
Test conditions
VOL
Low-level output voltage, BUS, RD, WR, F'St1\f, ALE
VOLl
Low-level output voltage, except the above and PROG
VOL2
Min
Typ
Max
Unit
IOL=2rnA
0.45
V
10L= 1.6rnA
0;45
V
Low-level output voltage, PROG
IOL = lrnA
0.45
VOH
High-level output voltage, BUS, RD, WR, f'S8\J, ALE
IOH= -100/1A
\/OHl
High-level output voltage, except the above
10H = -50,uA
II L
Input leak curr8nt, Tl, I NT
V ss;;;;; V IN;;;;; Vec
-10
-10
V
V
2.4
V
2.4
10
,uA
10L
Output leak current, BUS, TO high-impedance state
VSS + 0.45;;;;; VIN;;;;; Vee
I Lll
Input current during low-level input, port
VIL=0.8V
-0.2
rnA
ILl2
Input current during low-.level input, RESET, SS
VIL=0.8V
-0.05
rnA
100
Supply current from Voo
10
20
mA
100+1 ee
Supply current from VDD and Vee
65
135
rnA
TIMING REQUIREMENTS
Symbol
(Ta=0-70°C,
Parameter
Vee=Voo=5V±10%,
Vss=ov,
Min
Typ
Unit
Max
15.0
,"s
0
200
ns
0
200
ns
t RO
500
ns
Data setup time after RD
tRO
500
ns
tsu (A-D)
Data setup time after address
tAD
950
ns
tsu (PROG-D)
Data setup time after PROG
tpR
810
ns
th (PROG-D)
Data hold time before PROG
tpF
150
ns
tc
Cycle time
tey
2.5
th (PSEN-D)
Data hold time after PSEN
tOR
t h (R-D)
Data hold time after RD
tOR
tsu (PSEN-D)
Data setup time after PSEi\i
tsu (R-D)
0
/1A
unless otherwise noted)
Limits
Alternative
symbol
10
Note 1: The input voltage level of the input voltage is VIL =0.45V and VIH=2.4V.
• MITSUBISHI
..... ELECTRIC
6-23
MITSUBISHI MICROCOMPUTERS
MSL8048-XXXP, MSL803SLP
SINGLE -CHIP a-BIT MICROCOMPUTER
SWITCHI NG CHARACTERISTICS
Symbol
(Ta=0-70°C.
Parameter
Vee =Voo=5V± 10%.
Limits
Alternative
symbol
Min
tw (ALE)
ALE pulse width
t LL
400
td (A-ALE)
Delay time, address to ALE signal
tAL
120
tv (ALE-A)
Address valid time after ALE
t LA
80
tw (PSEN)
J5SEN pulse width
tee
700
tw (R)
R15 pulse width
tec
700
tw(W)
WR pulse width
tee
700
500
Delay time, data to Ii'ffi signal
tow
tv (W-Q)
Data valid time after WR
two
120
td(A-W)
Delay time, address to
tAW
230
~-
WA signal
id (AZ-R)
Delay time, address disable to Ff[J signal
tAFe
0
td (AZ-PSEN)
Delay time, address disable to PSEN signal
tAFC
0
t d (PC-PROG)
Delay time, port control to PROG signal
tcp
110
tv (PROG-PC)
Port control valid time after PROG
tpc
100
250
tp(Q-PROG)
Delay time, data to PROG signal
top
tv (PROG-Q)
Data valid time after PROG
tpo
65
tw (PROGL)
PROG low pulse width
tpp
1200
td (Q-ALE)
Delay time, data to ALE signal
t PL
350
tV(ALE-Q)
Data valid
t LP
150
Note 2:
--~ime
after ALE
Typ
Max
unless otherwise noted)
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
--
Conditions of measurement: control output CL ~80pF
CL ~150pF, tc~ 2.5~S
data bus output, port output
3:
VSS=OV.
Reference levels for the input/output voltages are low level~O.8V and high level ~2V
TIMING DIAGRAM
Read from External Data Memory
Write to External Data Memory
ALE
RD
ALE
------_r---'-~Ij,..------
WR
--------_1
tv (w-Q)
th (R-O)
BUS
BUS
Instruction Fetch from External Program Memory
Port 2
ALE
ALE
PSEN -----~--~
th(PSEN-O)
t'
PORT CONTROL INPUT DATA
d (PC-PPOC )~ t, (Ppo:-'PC)
BUS
tSU(PSEN-O)
tsu (A-D)
6-24
PROG
---....,...---------C.~W(PROGU
• MITSUBISHI
"'ELECTRIC
~!-----
MITSUBISHI MICROCOMPUTERS
MSL8049-XXXP,P-8,P-6
MSL8039P-ll,P-8,P-6
SINGLE-CHIP a-BIT MICROCOMPUTER
DESCRIPTION
The M5LS049-XXXP, P-S, P-6 and M5LS039P-11, P-S, P-6
are S-bit parallel microcomputers fabricated on a single chip
using high-speed N-channel silicon gate ED-MaS technology.
peed
S~
11 MHz Type
External ROM Type
Xz",
3
M5LB049-XXXP
M5LB039P-11
M5LB049-XXXP-B
M5LB039P-B
REQG~rf~~~0+ INT'"
6 MHz Type
M5LB049-XXXP-6
M5LB039P-6
EXTERNAL ACCESS EA'" 7
SINGLE-STEP INPUTSS ... 5
Basic machine instructions . . . . . . . . . . . . . . . .. 96
1-byte instructions: 6S
2-byte instructions: 2S
•
Direct addressing . . . . . . . . . . . . . . up to 4096 bytes
• I nternal RAM . . . . . . . . . . . . . . . . . . . . . 12S bytes
• Built-in timer/event counter . . . . . . . . . . . . . , S bits
• I/O Ports. . . . . . . . . . . . . . . . . . . . . . . .. 27 lines
• Easily expandable Memory and I/O:
• Subroutine nesting . . . . . . . . . . . . . . . . . . . S levels
• External and timer/event counter interrupt . 1 level each
• External RAM ....................... 256 bytes
M5LS049-XXXP/M5LS039P-11, P-6 are interchangeable
with Intel's PS049/PS039, PS039-6 in pin configuration
and electrical characteristics.
APPLICATION
Control processor or CPU for a wide variety of appli-
35 . . P2 4
6
+-
8
STOR~R~NG':B'i.~ PSEN+-
9
WRITE WR +-
10
ADDRESS LATCH ALE +ENABLE
11
READ RD
• Single 5V power supply
P2 7 }
37 "P2
6 I/O PORT 2
36 " P2 5
38 . .
RESET INPUT RESET'" 4
B MHz Type
•
•
Vee (5V)
CLOCK INPUT 2
Internal ROM Type
FEATURES
•
PIN CONFIGURATION (TOP VIEW)
I/O PORT 1
27 . . P1 0
Voo (5V)
DATA BUS
25
~PROG ~/~TERNAL
24 . . P2 3}
CONTROL
OUTPUT
I/O PORT 2
23 . . P2z
22 " P2 1
( 0 V) VSS
--. _ _ _ _ _....r2- 1
..
P 20
Outline 40P I
FUNCTION
The M5LS049-XXXP and M5LS039P are integrated S-bit
CPUs, with memory (ROM, RAM) and timer/event counter
interrupt all contained on a single chip.
cations
BLOCK DIAGRAM
o
ROREGISTERO
R1REGISTERl
RZREGISTER2 0
R3REGISTER3 ~
R4REGISTER4 ~
R5REGISTER5 en
R6REGISTER6
R7REGISTER7
STACK
i2
ROREGISTERo
ffi
is
(5V) Vee
~
w Rl'REGISTER 1
is RZ REGISTER
~ :! ~~g:~i~~: ~
2
,
R5REGISTEtJR~
R6REGISTER6
R7REGISTER7
RAM 128 BYTES
----------------------TO
T,
iNT RESET PROG
EA
x1
• MITSUBISHI
"ELECTRIC
6-25
MITSUBISHI MICROCOMPUTERS
MSL8049-XXXP,P-8,P-6
MSL8039P-ll,P-8,P-6
SINGLE-CHIP a-BIT MICROCOMPUTER
PIN DESCRIPTION
Pin
Name
Input or Output
Function
VSS
Ground
Normally connected to ground (OV)
Vee
Main power supply
Connected to 5V power supply
VOO
Power supply
PROG
P10-P17
Program
Port 1
CD Connected to 5V power supply
(2) Used for memory hold when Vee is cut
Output
Input/output
Quasi-bidirectional port_ When used as an input port. FF'6 must first be output to this
port. After reset. when not used as an output port nothing can be output.
Input/output
Output
P20-P27
Strobe signal for M5L8243P I/O Expander
CD
The same as port 1
(2) P2o -P2 3 output the high-order 4 bits of the program counter when using external
Port 2
program memory
Input/output
Q) P2 o -P2 3 serve as a 4-bit I/O expander bus for the M5L8243P
CD Provides true bidirectional
bus transfer of instructions and data between the CPU and
external memory. Synchronizing is done with signals REi/WR. The output data is
latched.
(2) When using external program memory the output of the low-order 8 bits of the pro00-07
Data bus
gram counter are synchronized with ALE. After that the transfer of the instruction
Input/output
code or data from external program memory is synchronized with PSEN.
Q) The output of addresses for data using external data memory is synchronized with
ALE. After that the transfer of data with the external data memory is synchronized
with RD/WR.
(MOVX A. @Rr and MOVX @Rr. A)
CD Control
To
Test pin 0
(JTO m and JNTO m)
Output
(2) Used for outputting the internal clock signal. (ENTO ClK)
CD
Tl
Test pin 1
signal from an external source for conditional jumping in a program. Jump-
ing is dependent on external conditions.
Input
Input
Control signal from an external source for conditional jumping in a program. Jumping is dependent on external conditions. (JTl m and JNTl m)
(2) When enabled event signals are transferred to the timer/event counter. (STRT CNT)
CD
TNT
Interrupt
Input
Control signal from an external source for conditional jumping in a program. Jumping is dependent on external conditions. (IN 1 m)
(2) Used for external interrupt to CPU
Read control signal used when the CPU requests data from external data memory or ex-
RO
Read control
Output
ternal devices to be transferred to the data bus.
(MOVX A. @Rrand INS A. BUS)
Write control signal used when the CPU sends data through the data bus to external data
WR
Write control
Output
memory or external device.
(MOVX @R. A and OUTL BUS. A)
RESET
Reset
Input
ALE
Address latch enable
Output
PSEN
Program store enable
Output
SS
Single step
Input
Control used to initialize the CPU.
A signal used for latching the address on the data bus. An ALE signal occurs once during
each cycle.
Strobe signal to fetch external program memory.
Control signal used in conjunction with ALE to stop the CPU through each instruction.
in the single step mode.
CD Normally maintained at OV
EA
External access
Input
(2) When the level is raised to 5V. external memory will be accessed even when the address is less than 400'6 (2048).
Xl, X2
6--26
Crystal inputs
Input
External crystal oscillator or RC circuit input for generating internal clock signals. An
external clock signal can be input through X, or X 2 •
• MITSUBISHI
..... ELECTRIC
MITSUBISHI MICROCOMPUTERS
MSL8049-XXXP,P-8,P-6
MSL8039P-ll,P-8,P-6
SINGLE-CHIP a-BIT MICROCOMPUTER
ABSOLUTE MAXIMUM RATINGS
Symbol
Conditions
Parameter
Vee
Supply voltage
Voo
Supply voltage
VI
I nput vol tage
Vo
Output voltage
Pd
Power dissipation
With respect to Vss
Ta=25,,(
Topr
Operating free·air temperature range
Tstg
Storage temperature range
R ECOMM ENDE 0 OPE RA TI NG COND I TI ONS
Symbol
Limits
V
-0.5 -7
V
-0.5-7
V
1.5
W
0-70
°C
- 65-150
"(
Limits
Min
Nom
Unit
Max
Vee
Supply voltage
4.5
5
5.5
V
Voo
Supply voltage
4.5
5
5.5
V
VSS
Supply voltage
VIHt
High-level input voltage, except for X I, X 2 , RESET
VIH2
High-level input voltage, XI, X 2 , RESET
VIL
Low-level input voltage
Symbol
V
-0.5 -7
(Ta = 0 - 70,,(, unless otherwise noted)
Parameter
0
ELECTRICAL CHARACTERISTICS
Unit
-0.5-7
V
2
Vee
V
3.8
Vee
V
-0.5
0.8
V
(Ta=0-70°C,
Vee=Voo=5V± 10%,
Parameter
III
VSS=OV, unlessotherwisenoted)
Limits
Test conditions
Min
Typ
Unit
Max
VOL
Low-level output voltage, BUS, RD, WR, PSEN, ALE
IOL=2mA
0.45
V
VOLl
Low-level output voltage, except for the above and PROG
IOL= 1.6mA
0.45
V
VOL2
Low-level output voltage PROG
IOL=lmA
0.45
V
VOH
High·level output voltage, BUS, RD, WR, PSEN, ALE
IOH= -100,uA
2.4
VOHt
High-level output voltage, except for the above
IOH= -50{JA
2.4
I IL
Input leak current, Tl, I NT
VSS~VIN~VCC
-10
-10
V
V
10
/-LA
10
,uA
IOL
Output leak current, BUS, TO, high-impedance state
VSS+ 0.45~VIN~VCC
I Lit
Input current during low-level input, port
VIL =0.8V
-0.2
mA
ILl2
Input current during low-level input, RtSIT, §
VIL=0.8V
-0.05
mA
100
Supply current from Voo
Ta=25°C
25
50
mA
100+ 1CC
Supply current from Voo and Vee
Ta=25"C
100
170
mA
TIMING REQUI REMENTS (Ta =0-70,,(.
Vcc=Voo=5V
±
10%.
VSs=OV.
unless otherwise noted)
Limits
Parameter
Symbol
Alternative
symbol
M5LS049-XXXP
M5LS039P-l1
Min
Typ
M5LS049-XXXP-8
M5LS039P-S
Typ
M5LS049-XXXP-6
M5LS039P-6
Typ
Unit
Max
Min
Max
Min
to
Cycle time
t Cy
1.36
15.0
1.875
15.0
2.5
15.0
,us
th (PSEN-D)
Data hold time after PSEf\i
tOR
0
100
0
150
0
200
ns
th (R-o)
Data hold time after RD
tOR
0
100
0
150
0
200
ns
tsu (PSEN-o)
Data setup time after PSEN
t Ro
250
350
500
ns
tsu (R-o
Data setup time after RD
tRo
250
350
500
ns
tsu (A-D)
Data setup time after address
tAD
400
650
950
ns
tsu (PROG-o)
Data setup time after PROG
t PR
810
ns
th (PROG-o)
Data hold time before PROG
t PF
150
ns
650
0
150
700
0
150
0
Max
Note 1: The input voltages are V,L=0.45V and V'H=2.4V.
• MITSUBISHI
.... ELECTRIC
6-27
MITSUBISHI MICROCOMPUTERS
MSL8049-XXXP,P-8,P-6
MSL8039P-ll,P-8,P-6
SINGLE-CHIP 8-BIT MICROCOMPUTER
SWITCHING CHARACTERISTICS
(Ta = O~70°C, Vee = Voo = 5V±10%, Vss = OV, unless otherwise noted)
Limits
Alternative
symbol
Parameter
Symbol
M5LB049-XXXP
M5LS039-11
Typ
Min
Max
M5LB049-XXXP-B
M5LB039P-B
Min
Typ
Max
M5LB049-XXXP-6
M5LS039P-6
Min
Typ
Unit
Max
tw (ALE)
ALE pulse width
t LL
150
300
400
td (A-ALE)
Delay time, address to ALE signal
tAL
70
120
150
ns
tv (ALE-A)
Address valid time after ALE
t LA
50
70
80
ns
tw (PSEN)
PSEN pulse width
tcc
300
500
700
ns
tW(R)
RD pulse width
tcc
300
500
700
ns
td (w)
WR pulse width
t CC
300
500
700
ns
tv (Q-W)
Delay time, data to WR signal
tow
250
380
500
ns
td (W-Q)
Data valid time after WR
two
40
80
120
ns
td (A-W)
Delay time, address to WR signal
tAW
200
220
230
ns
td (AZ-R)
Delay time, address disable to RD signal
tAFC
-10
-5
0
ns
td (AZ-PSEN)
Delay time, address disable to PSEN signal
tAFC
-10
-5
0
ns
td (PC-PROG)
Delay time, port control to PROG signal
t CP
100
105
110
ns
tv (PROG-PC)
Port control valid time after PROG
t PC
60
100
130
ns
tp (Q-PROG)
Delay time, data to PROG signal
top
200
210
220
ns
tv (PROG-Q)
Data valid time after PROG
tpo
20
45
65
ns
tW(PROGL)
PROG low pulse width
tpp
700
1150
1510
ns
td (Q-ALE)
Delay time, data to ALE signal
t PL
150
300
400
ns
tv (ALE-Q)
Data valid time after ALE
t LP
20
100
150
ns
ns
Note 2: Conditions of measurement: control output CL =BOpF
data bus output, port output CL =150pF tc=te (Min)
3: Reference levels for the input/output voltages are low level=O.BV and high level=2V.
TIMING DIAGRAM
Read from External Data Memory
Write to External Data Memory
ALE
ALE
tW(R)
RD --------------~I
WR
----------------~I
tv (w-Q)
td (AZ-R)
BUS
th (R-O)
BUS
DATA
Instruction Fetch from External Program Memory
Port 2
ALE
ALE
th(PSEN-O)
BUS
tsu (PSEN- D)
tsu (A-D)
6-28
PROG------------------~l~t;~~~r_-----
• MITSUBISHI
;"ELECTRIC
MITSUBISHI MICROCOMPUTERS
MSL8748S
SINGLE - CHIP 8-BIT MICROCOMPUTER WITH EPROM
DESCRIPTION
PIN CONFIGURATION (TOP VIEW)
The M5L8748S is an 8-bit parallel microcomputer frabricated on a single-chip using high-speed N-channel silicongate E'O-MOS technology. This contains ultraviolet-light
TEST PIN 0 To
erasable and electrically reprogrammable ROM (EPROM)
RESET INPUT
I nstruction cycle .....
Basic machine instructions
1-byte instructions: 68
2-byte instructions: 28
4
38
37
SS .....
5
36
*
*
35
*P24
REQ0~H~~W(;t
INT .....
6
EA .....
7
READ
RD +-
8
PSEN +WRITE WR +-
9
10
ALE +-
11
STOR~R~NG:BAL~
2.5JJs (min)
...... 96
ADDRESS
LATCH ENABLE
•
•
Direct addressing . . . . . . . . . . . . . . up to 4096 bytes
Internal EPROM. . . . . . . .
. .. 1024 bytes
•
•
Internal RAM . . . . . . . . .
Built-in timer/event counter ....... .
•
•
I/O Ports . . . . . . . . . . . . . . . . . . . . . . .
Easily expandable memory and I/O
•
Subroutine nesting .... . . . . . . . .
25
.. 8 bits
27 lines
24
23
22
(OV) VSS
External and timer/event counter interrupt . 1 level each
•
•
External RAM . . . . . . . . . . . . . . . . . . . . . 256 bytes
Interchangeable with the Intel's 08748 in pin configuration and electrical characteristics
APPLICATIONS
I/O PORT 2
*P10
.......,L_ _ _ _ _r2~1
*
*
PROG EXTERNAL
I/O
P2 3}
*P22
*
*
P2
1
CONTROL
OUTPUT
I/O PORT 2
P 20
Outline 40510
•
•
A CPU for special repetitive processing or control for
which a small number of units are to be produced.
6
P25
Voo
DATA BUS
. .. 8 levels
P2 7 }
*P2
I/O PORT 1
27
64 bytes
•
•
3
EXTERNAL ACCESS
• Single 5V power supply
•
•
Xz .....
RESET .....
SINGLE-STEP INPUT
FEATURES
Vcc(SV)
1
2
CLOCK INPUT 2
on a chip, so it is easy to change the program stored in the
EPROM.
*
CLOCK INPUT 1 Xl .....
A debugging CPU for program, application and system
design development
A CPU for prototype and preproduction systems prior
to factory-programmed mask ROM production
BLOCK DIAGRAM
T,
ffi
o
8
~
ROREGISTER
Rl REGISTER
RZ REGISTER
R3REGISTER
R4 REGISTER
R5REGISTER
R6REGISTER
R7REGISTER
0
1
2 0
3 ~
4
~
5 o:l
6
7
STACK
~ ROREGISTER 0
~ R 1 REGISTER 1
o
RzREGISTEh
2
~ R3REGISTER
3
R4 REGISTER (
~
~
R5REGISTER~~
R6REGISTER 6
R7REGISTER 7
J
RAM 64 BYTES
----------------------To
T,
iNT RESET PROG
EA x 1 X 2 ALE
P'SEN 55 AD
WR
• MITSUBISHI
.... ELECTRIC
6-29
II
•
MITSUBISHI MICROCOMPUTERS
MSL8748S
SINGLE -CHIP a-BIT MICROCOMPUTER WITH EPROM
PIN DESCRIPTION
Name
Pin
Input or Output
Function
VSS
Ground
Normally connected to ground (OV),
Vee
Main power supply
Connected to 5V power supply,
VOO
Program power supply
CD
®
Input
PROG
Port 1
Input/output
Input/output
P 2 0- P2 7
Port 2
Output
Input/output
When programming to EPROM, 25V is required.
Used to supply 25V program pulses (50 ms width) from an outside source when pro·
gramming to EPROM.
Program
Output
P10-P17
CD
Normally connected to 5V power supply.
®
Strobe signal for M5l8243P I/O Expander.
Quasi·bidirectional port. When used as an input port, FFI6 must first be output to this
port. After reset, when not used as an output port nothing can be output.
CD The same as port 1 ,
®
P2 o -P2 3 output the high-order 4 bits of the program counter when using external
program memory,
~ P2o -P2 3 serve as a 4-bit I/O expander bus for the M5l8243P.
CD Provides
true bidirectional bus transfer of instructions and data between the CPU
and external memory. Synchronizing is done with signals RD/WR. The output data
is latched.
®
When using external program memory the output of the low·order 8 bits of the program counter are synchrunized with ALE. After that the transfer of the instruction
00- 07
Data bus
Input/output
code or data from external program memory is synchronized with PSEN.
~ The output of addresses for data using external data memory is synchronized with
ALE, After that the transfer of data with the external data memory is synchronized
with RD/WR,
(MOVX A, @Rrand MOVX @Rr, A)
CD
Input
To
is dependent on external conditions. (JTO m and JNTO m)
Test pin 0
Output
Control signal from an external source for conditonal jumping in a program, Jumping
®
Used for outputting the internal clock signal. (ENTO ClK)
CD Control
Tl
Test pin 1
®
When enabled event signals are transferred to the timer/event counter. (STRT CNT)
CD Control
INT
Interrupt
®
Read control
Output
WR
Write control
Output
RESET
Reset
Input/output
signal from an external source for conditional jumping in a program. Jump-
ing is dependent
Input
RO
signal from an external source for conditional jumping in a program. Jump-
ing is dependent on external conditions. (JT1 m and JNT1 m)
Input
()~
external conditions. (JN1 m)
Used for external interrupt to CPU.
Read control signal used when the CPU requests data from external data memory or
external devices to be transferred to the data bus .. (MOVX A, @Rr and I NS A, BUS)
Write control signal used when the CPU sends data through the data bus to external data
memory or external devices. (MOVX @R, Aand OUTl BUS, A)
CD
Control used to initialize the CPU.
®
latch signal for the EPROM address when programming to EPROM and for reading
from EPROM (verify mode).
A signal used for latching the address on the data bus. An ALE signal occurs once during
ALE
Address latch enable
Output
PSEN
Program store enable
Output
SS
Single step
Input
each cycle.
Strobe signal used to fetch from external program memory.
Control signal used in conjunction with ALE to stop program execution at the finish of
each instruction, in the single step mode.
CD Normally maintained at OV.
® When the level is raised to 5V, external
EA
External access
Input
memory will be accessed even when the ad·
dress is less than 40016 (1024).
Q) When in the programming mode for the EPROM a 25V power supply must be available at this terminal.
External crystal oscillator or RC circuit input for generating internal clock signals. An ex·
Xl. X2
6-30
Crystal inputs
Input
ternal clock signal can be input through XI or X2
• MITSUBISHI
~ELECTRIC
,
MITSUBISHI MICROCOMPUTERS
MSL87485
SINGLE· CHIP 8-BIT MICROCOMPUTER WITH EPROM
ABSOLUTE MAXIMUM RATINGS
Parameter
Conditions
Limits
Unit
Vee
Supply voltage
-0.5-7
V
Voo
Supply voltage
-0.5-26.5
V
VI
I nput voltage
-0.5-7
V
Vo
Output voltage, all outputs except
Pd
Power dissipation
Topr
Operating free-air temperature range
Tstg
Storage temperature range
Symbol
With respect to Vss
rPl
and
rP2
Ta =25'C
-0.5-7
V
1.5
W
0-70
"C
-65-150
'C
RECOMMENDED OPERATING CONDITIONS
CPU Operatio n (T a = 0 - 70'C, unless otherwise noted)
Limits
Parameter
Symbol
Nom
Min
Unit
Max
Vee
Su pply voltage
4.75
5
5.25
Voo
Supply voltage, except programming EPROM
4.75
5
5.25
V
Voo
Supply voltage, programming EPROM
26
V
Vss
Supply voltage
VIHl
High-level input voltage, except X I, X2 , RESET
VIH2
High-level input voltage, XI, X2 , ~
VIL
Low-level input voltage
24
25
0
EPROM PROGRAMMING
V
2
Vee
V
3.8
Vee
V
0.8
V
-0.5
(Ta=25±5'C,
V
vee=5V±5%,
VOO=25±lV, unlessotherwisenoted)
Limits
Unit
Parameter
Symbol
Nom
Min
VOD(H)
High-level program supply voltage
VDO(L)
Low-level program supply voltage
VIH(PROG)
High-level program pulse input voltage
VIL(PROG)
Low-level program pulse input voltage
VEA(H)
High-level EA input voltage
VEA(L)
Low-level EA input voltage
24.
Max
26
4.75
5.25
21.5
21.5
V
V
24.5
V
0.2
V
24.5
5.25
V
V
ELECTRICAL CHARACTERISTICS
CPU Operation
(Ta=0-70"C,
Vee=Voo=5V± 5 %,
Vss=OV,
unless otherwise noted)
Limits
Symbol
Parameter
Test conditions
Min
Typ
Unit
Max
VOL
Low-level output voltage, BUS, RD, WR, PSEN, ALE
IOL=2mA
0.45
V
VOLl
Low-level output voltage, except the above and PROG
IOL= 1.6mA
0.45
V
VOL2
Low-level output voltage, PROG
IOL=lmA
0.45
V
VOH
High-level output voltage, BUS, RO, WR, PSEN, ALE
IOH= -100,uA
2.4
VOHl
High-level output voltage, except the above
IOH=-50!lA
2.4
I IL
I nput leak current, Tl, I NT
V ss;;;;; V IN;;;;; Vee
-10
I Lll
Low-level input current, ports
VIL=0.8V
-0.2
ILl2
Low-level input current, RESET, SS
VIL =0.8V
-0.05
100
Supply current from Voo
Ta=25'C
10
20
mA
100+ 1 ee
Supply current from Voo and Vee
Ta=25'C
65
135
mA
EPROM PROGRAMMING
(Ta=25±5'C,
vee =5V ±5%,
V
V
10
/-fA
mA
mA
VDD =25± lV, unless otherwise noted)
Limits
Symbol
Parameter
Test conditions
Min
Typ
Max
Unit
100
Supply current from Voo
30
IIH(PROG)
High-level input current, PROG
16
mA
IIH(EA)
High-level input current, EA
1
mA
• MITSUBISHI
;"ELECTRIC
mA
6-31
MITSUBISHI MICROCOMPUTERS
MSL87485
SINGLE - CHIP 8-BIT MICROCOMPUTER WITH EPROM
TIMING REQUIREMENTS
Read/Write of External Memory
Symbol
(Ta=0-70°C.
Vee =Voo =5V±5%.
Alternative
symbol
Parameter
vss = OV.
unless otherwise noted)
Limits
Min
Typ
Unit
Max
to
Cycle time
tey
2.5
15.0
th(PSEN-O)
Data hold time after PSEN
tOR
0
200
ns
t h(R-O)
Data hold time after
tOR
0
200
ns
RD
tSU(PSEN-O)
Data setup time after PSE N
tSU(R-O)
Data setup time after
tSU(A-O)
Data setup time after address
Fm
fJ.S
tRO
500
ns
tRO
500
ns
tAD
950
ns
Note 1: The input voltage level is VIL ;0,45 and VIH;2,4V.
Port 2
(Ta=0-70°C.
Vee=voo=5V±5%.
Symbol
Vss=ov. unless otherwise noted)
Parameter
Alternative
symbol
tsu (PROG-D)
Data setup time after PROG
t PR
t h (PROG-D)
Data hold time after PROG
tpF
Limits
Min
Typ
0
Max
Unit
810
ns
150
ns
Note 2: The input voltage level of the input voltage is VIL; 0,45V and V 1H ;2,4V.
EPROM PROGRAMMING
Symbol
(Ta=25±5°C.
Parameter
Vee=5V±5%.
Voo=25V±IV.
AI ternat ive
symbol
Unit
Min
tsu (A-RES)
Address setup time before RESET
tAW
4t c
th (RES-A)
Address hold time after RESET
tWA
4t c
ts U (D-PROG)
Data setup time before PROG
tow
4t c
th (PROG-D)
Data hold time after PROG
two
4t c
th (To-RES H)
RESET high hold time after To (verify mode)
tpH
4t c
tSU(Voo·PROG)
Voo setup time before PROG
tVOOW
4t c
t h (PROG.Voo)
Voo hold time after PROG
tVOOH
0
tW(PROG)
PROG pulse width
tpw
50
tSU(To'RES)
Setup time before RES
tTW
4t c
th (VDD-To)
Hold time after Voo
tWT
4t c
tw (RES)
RESET pulse width
tww
4t c
Note 3:
4:
5:
6-32
unless otherwise noted)
Limits
CPU cycle time te requires 5j.1s min.
Rise time (t r ) and fall time (tf) of Voo and PROG should be within the range of 0.5-2j.1s.
RESET setup time for the positive-going EA requires 4 te min.
• MITSUBISHI
.... ELECTRIC
Typ
Max
ns
60
ms
MITSUBISHI MICROCOMPUTERS
MSL87485
SINGLE - CHIP S-BIT MICROCOMPUTER WITH EPROM
SWITCHING CHARACTERISTICS
Read/Write of External Memory (Ta=0-70"C.
Symbol
Parameter
Vcc=Voo=5V±5%.
Vss=ov. unlessotherwisenoted)
Limits
Alternative
symbol
Min
Unit
Typ
Max
tw (ALE)
ALE pulse width
tLL
400
ns
td (A-ALE)
tv (ALE-A)
Delay time, address to ALE signal
tAL
120
ns
Address valid time after ALE
tLA
80
ns
tW(PSEN)
PSEN pulse width
tcc
700
ns
tw (R)
RD pulse width
tcc
700
ns
tcc
700
ns
tow
500
ns
tW(W)
WR pulse width
td (Q-W)
Delay time. data to
tV(W-Q)
Data valid time after WR
two
120
ns
td(A-W)
Delay time. address to WR signal
tAW
230
ns
td(AZ-R)
Delay time. address floating to RD signal
tAFC
0
ns
td (AZ-PSEN)
Delay time. address floating to
tAFC
0
ns
Note 6:
PSEN signal
Conditions of measurement: control output C L =80pF
data bus output CL =150pF. tc=2.5~s
Reference level for the input/output voltage is low level=O.8V and high level=2V.
7:
Port 2
(Ta=0-70"C.
Symbol
td (PC-PROG)
tv (PROG-PC)
tp (Q-PROG)
tv (PROG-Q)
tw (PROGL)
td (Q-ALE)
tv (ALE-Q)
Note 8:
9·
WR signal
VCC=Voo=5V ± 5%.
Vss=OV.
unless otherwise noted)
Limits
Alternative
symbol
Min
Delay time. port control to PROG signal
tcp
110
ns
Port control valid time after PROG
tpc
100
ns
Parameter
Unit
Typ
Max
Delay time. data to PROG signal
top
250
ns
Data valid time after PROG
tpo
65
ns
P'ROG low-level pulse width
tpp
1200
ns
Delay time, data to ALE signal
tpL
350
ns
Data valid time after ALE
tLP
150
ns
Condition of measurement is CL =150pF, tc=2.5~s
Reference level for the input/output voltage is low level=O.8V and high level=2V.
EPROM PROGRAMMING
Symbol
\P(To-Q)
(Ta =25±5"C. VCC=5V ±5%, Voo=25V ± lV. unless otherwise noted)
Parameter
Propagation time between To and data.
Alternative
symbol
Limits
Min
too
• MITSUBISHI
.... ELECTRIC
I
I
Typ
I
I
Max
Unit
4tc
6-33
MITSUBISHI MICROCOMPUTERS
MSL8748S
SINGLE· CHIP a·BIT MICROCOMPUTER WITH EPROM
TIMING DIAGRAM
I nstruction fetch from external program memory
c
tw(ALE)
)
ALE
I
tw(PSEN)
I
1/
~
tv (ALE-A)
r~d
td (A-ALE)
BUS
(AZ-PSEN
I
i
II.
ADDRESS
W
I
~~
II~
WI
\.\.~
tSU(PSEN-D)I
I
I
DATA
th(PSEN-D)
~\.
'71
I
l
.1
tsU(A-D)
Reading from external data memory
ALE~
\I........-_____.....J!
~.
RD
tw(R)
~H
th (R-D)
I
td (AZ-R)
BUS
tsu (A-D)
Writing to external data memory
ALE-1
\
/
tW(W)
WR
tv (W-Q)
BUS -----f[
TO --0 V
....-
RESET--OV
PRE PARAnON FOR PROG RAMM I NG
THE NEXT DATA BYTE
]
YES
NO
WHILE POWER ISSTILLON(AT*) REMOVE THE M5L8748S FROM THE SOCKET.
END
6-36
• MITSUBISHI
.... ELECTRIC
-
- { ENDS
]
MITSUBISHI LSls
MSL8243P
INPUT/OUTPUT EXPANDER
DESCRIPTION
The M5L 8243P is an input/output expander fabricated
using N-channel silicon-gate EO-MOS technology. This
device is designed specifically to provide a low-cost means
of I/O expansion for the MELPS 8-48 single-chip microcomputer and M5L 8041A-XXXP.
FEATURES
.16 Input/output pins ( IOL =5.0mA(max))
• Simple interface to MELPS 8-48 microcomputers
• Single 5V power supply
• Low power dissipation:
50mW (typ)
• Interchangeable with Intel's 8243 in pin configuration
and electrical characteristics
APPLICATION
• I/O expansion for the MELPS 8-48 single-chip microcomputers.
PIN CONFIGURATION (TOP VIEW)
INPUT/OUTPUT
PORT 5
Vee
(5V)
l'NPUT/OUTPUT
PORT 5
INPUT/OUTPUT
PORT 4
CHIP SELECT
INPUT/OUTPUT
PORT 6
PROGRAM
INPUT/OUTPUT
PORT 2
llNPUT/OUTPUT
PORT 7
(OV)
GND
Outline 24P1
_
L...-....-------'1iII
FUNCTION
The M5L8243P is designed to provide a low-cost means
of I/O expansion for the M5L 8041A-XXXP universal
peripheral interface and the M5L 8048 and M5L 8049
single-chip microcomputers. The M5L 8243P consists of
four 4-bit bidirectional static I/O ports and one 4-bit port
which serves as an interface to the M5L 8041A-XXXP and
M5L8048/9. Thus multiple M5L8243Ps can be added
to a single master.
Using the original instruction set of the master, the
M5L 8243P serves as the in resident I/O facility. Its I/O
ports are accessed by instructions MOV, ANL and ORL.
BLOCK DIAGRAM
I
+
V,,(5V)
12 GND(OV)
L
P70 P71 P 72 P73
P60 P 61 P 62 P 63
PSOPS1PS2PS3
P40P41 P 42 P 43
'---v------/
PORT 7
~
~
~
PORT 6
PORT 5
• MITSUBISHI
..... ELECTRIC
PORT 4
6-37
MITSUBISHI LSls
MSL8243P
INPUT/OUTPUT EXPANDER
PIN DESCRIPTION
Symbol
Name
Function
Input or output
PROG
Program
In
A high-to-Iow transition on PROG signifies that address (pORT 4-7) and control are available on PORT 2. and
a low-ta-high transition signifies that the designated data is available on the disignated port through PORT
2 The designation is shown in Table 1.
CS
Chip select
In
Chip select input. A high on CS causes PROG input to be regarded high inside the M5L8243P. then this
inhibits any change of output or internal status
In/out
The 4-bit bidirectional port contains the address and control bits shown in Table 1 on a high-to-Iow transition
of PROG During a low-to-high transition it contains the input (output) data on this port
In/out
The 4-bit bidirectional I/O port. May be programmed to be input. low-impedance latched output or a
three-state This port is automatically set output mode when it is written. ANLed or ORLed. then continues
its mode until next read operation. After reset on a read operation. this port is in high-impedance and input
mode
P20-P23
Input/output port 2
P40- P 43
Input/output port 4
PSO- PS3
Input/output port 5
P60- P63
Input/output port 6
P70- P73
Input/output port 7
OPERATION
The M5L 8243P is an input/output expander designed
specifically for the M5L 8014A-XXXP and MELPS 8-48
single-chip 8-bit microcomputer. The M5L8041A-XXXP
and MELPS 8-48 already have instructions and PROG pin
to communicate with the M5L 8243P.
An example of the M5L8243P and the M5L8041AXXXP is shown in Fig. 1. The following description of the
M5L8243P basic operation is made according to Fig. 1.
Upon initial application of power supply to the device,
and then about 50ms after, resident bias circuits become
stable and each device is ready to operate. And each port
of the M5L 8243P is set input mode (high-impedance) by
means of a resident power-on initialization circuit.
When the microcomputer begins to execute a transfer
instruction
MOVD
A, Pi
i = 4, 5, 6,7
which' means the value on the port Pi is transferred to the
accumulator, then the signals are sent out on the pins
PROG and P20 -P 23 as shown in Timing Diagram.
On the high-to-Iow transition of the pin PROG, the
M5L 8243P latches the instructions (ex. 0000) into itself
from pins P20 -P 23 and transfers them to the instruction
register (CD in Timing Diagram). During the low-level of
PROG, the M5L 8243P continuously outputs the contents
of the specified input (output) port (in this case port P4 ) to
pins P20 -P23 (® in Timing Diagram). The microcomputer,
at an appropriate time, latches the level of pins P20 -P23
and resumes high-level of PROG.
The next example is the case in which the microcomputer executes
i = 4, 5, 6,7
MOVD
Pi, A
the transfer (output) instruction.
In this case, as in the previous case, on the high-tolow transition of the pin PROG, the M5L8243P latches
6-38
the instructions (ex. 0110) into itself from pins P20-P 23
and transfers them to the instruction register (CD in Timing
Diagram).
After this, the microcomputer sends out high to the
pin PROG, transferring the data to pins P20-P23 which is
an output data to input/output port. Then the M5L 8243P
transfers the data of pins P20-P23 to the port latch of the
designated input/output port (in this case Pel. In a few
seconds after a low-to-high transition on the PROG, the
designated port (P e) becomes in an output mode and the
data of the port latch are transferred to the port pins
(Q) in Timing Diagram).
When instructions
ANlD
ORlD
Pi, A
Pi, A
i = 4, 5, 6,7
are executed, the microcomputer generally operates as
same function as MOVD Pi, A.
It only differs in that the data of port latch after @ in the
Til)1ing Diagram is ANDed or ORed with the data of port
latch before @ and the data of pins P20 -P 23 .
When instructions
MOVD
ANlD
ORlD
Pi, A
Pi, A
Pi, A
i = 4, 5, 6,7
are executed toward the port in an output mode, the
outputs are generated on the port as soon as low-to-high
transition on the PROG occurs.
When the mode of the output port is going to be
changed during the execution and the instruction
MOVD
A,Pi
i=4,5,6,7
is executed, it is preferable to execute one dummy
instruction. Because it takes a little time to turn the
designated port into a high-impedance state after highto-low transition on the PROG, the result may be that the
first instruction is not read correctly.
• MITSUBISHI
"'ELECTRIC
MITSUBISHI LSls
MSL8243P
INPUT/OUTPUT EXPANDER
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Vee
Supply voltage
VI
Input voltage
limits
Conditions
With respect to Vss
Unit
-0.5-7
V
-0.5-7
V
-0.5-7
Vo
Output voltage
Pd
Maximum power dissipation
Topr
Operating free-air temperature range
Tstg
Storage temperature range
Ta=25"C
V
mW
600
0-70
"C
-65- 150
RECOMMENDED OPERATING CONDITIONS
(Ta=-20-70"C,
"C
Vee=5V±10%. unless otherwise noted)
Limits
Parameter
Symbol
Vee
Supply voltage
Vss
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
Unit
Min
Nom
Max
4.5
5
5.5
0
V
2
-0.5
ELECTRICAL CHARACTERISTICS
(Ta =-20-70"C,
V
V
0.8
II
V
Vee=5V±10%. unless otherwise noted)
limits
Parameter
Symbol
Unit
Test condition
Typ
Min
VIL
Low-level input voltage
0.5
VIH
High-level input voltage
VOLI
Low-level output voltage. ports 4-7
VOL2
Low-level output voltage. port 7
IOL=20mA
VOL3
Low-level output voltage. port 2
10L = 0.6mA
VOHI
High-level output voltage. ports 4-7
10H =240,uA
VOH2
High-level output voltage. port 2
10H = 100,uA
Input leakage current. ports 4 - 7
OV~Vin~Vee
-10
OV~Vin~Vee
-10
112
Input leakage current. port 2. CS. PROG
Supply current from Vee
10L
Sum of all 10L from 16 outputs
V
1
V
0.45
V
V
2.4
IOL=5mA (VOL =0.45V) Each pin
20
,uA
10
,uA
20
mA
80
mA
Fig. 1 Basic connection
Address code
P21
Read
0
0
port 4
0
0
Write
0
1
port 5
0
1
ORLO
1
0
port 6
1
0
ANLO
1
1
port 7
1
1
P22
V
0.45
V
10
Table 1 Instruction and address codes
P23
V
Vcc+0.5
2.4
111
Instruction code
0.8
10L= 5 mA
ICC
Max
P20
M5L 8048/9 or M5L 8041 A-XXXP
PROGL-------I
P20'--------I
P21'--------I
P22'--------I
P23'--------I
.....
L...-.....,~
• MITSUBISHI
.... ELECTRIC
6-39
MITSUBISHI LSls
MSL8243P
INPUT/OUTPUT EXPANDER
TIMING REQUIREMENTS
(Ta =-20-70"C,
Vcc=5V±10%,
Vss=ov, unless otherwise noted)
Limits
Alternative
Symbol
Test conditions
Parameter
Unit
Min
symbol
Typ
Max
tSU(INST-PR)
Instruction code setup time before PROG
tA
80pF
Load
100
ns
th (PR-INST)
Instruction code hold time after PROG
t8
20pF
Load
60
ns
tsU(OQ-PR)
Data setup time before PROG
tc
80pF
Load
200
ns
th(PR-OQ)
Data hold time after PROG
to
20pF
Load
20
ns
tW(PR)
PROG pulse width
tK
700
ns
tsu(CS-PR)
Chip-select setup time before PROG
tcs
50
ns
th(PR-CS)
Chip-select hold time after PROG
tcs
50
ns
tsu (PORT-PRj
Port setup time before PROG
tiP
100
ns
th(PR-PORT)
Port hold time after PROG
tiP
100
ns
SWITCHING CHARACTERISTICS
Limits
Alternative
Symbol
Unit
Test conditions
Parameter
Min
symbol
Typ
Max
ta(PR)
Data access time after PROG
tACC
80pF Load
0
650
ns
tdv (PR)
Data valid time after PROG
tH
20pF Load
0
150
ns
tpHL(PR)
tpLH(PR)
Output valid time after PROG
tpo
100pF Load
700
ns
~:~~~:~~
Input/output switching time
800
ns
6-40
-
• MITSUBISHI
"ELECTRIC
MITSUBISHI LSls
MSL8243P
INPUT/OUTPUT EXPANDER
TIMING DIAGRAM
PROG
PORT 2
PORT 2
PORTS 4-7
PORTS 4-7
PORTS 4-7
II
PORTS 4-7
th(PR-CS)
Note 1 AC test conditions
Input pulse level
0.45 - 2. 4V
Input pulse rise time tr (lO%-90%)
20ns
Input pulse fall time tf (lO%-90%)
20ns
Reference voltage for switching characteristiC measurement
Input
VIH
2V
VIL
O. 8V
Output VOH
2V
VOL
O. 8V
Current Sinking Capability
Each of the 16 I/O lines of the M5L8243P is capable of
sinking 5mA simultaneously
(VOL =
0.45V max). However,
the drive capacity of each line depends upon whether all
125
lines are sinking current simultaneously and on the degree
of loading. This is illustrated in the curve shown.
;:t
100
93
.§.
.9
V'l
I
75
~
(1.6mA)?
I
60
50
--------~--------I
IOL =
I
I
1.6mA x 5 = 8mA (sink current for each pin)
~IOL =
I
.u;
Y9
0
r
many pins would be able to accommodate 5TTL loads
I
I
c
~
Example
Assuming that the remaining pins are not loaded, how
I
I
...J
I
I
25
I
I
I
2
9
Maximum sinked current at each pin (VOL
10
~
11
12
13
0.45V max) (mA)
60mA from curve (curve A)
(total sinking current)
Number of pins = 60mA..;. 8mA/pin = 7.5 = 7 lines
For this case, each of th 7 lines could sink 8mA for a
total of 56mA. Since 4mA reserve sinking capability exists,
9 of the I/O lines of the M5L8243P can be divided
arbitrarily.
• MITSUBISHI
"ELECTRIC
6-41
MITSUBISHI LSls
MSL8243P
INPUT/OUTPUT EXPANDER
Example
To use 20mA sinking capability at port 7, find the effects
on the skinking capabilities of the other I/O lines.
Assume the M5L8243P is driving loads as shown below.
2 lines: -20mA (VOL = 1.0V max, port 7 only)
8 lines: -4mA (VOL = 0.45V max)
6 lines: -3.2mA (VOL = O.5V max)
Is this within the allowable limit?
~IOL = (20mA x 2) + (4mA x 8) + (3.2mA x 6) = 91.2mA
From the curve we see that with respect to IOL = 4mA,
IOL is 93mA (curve B) and that the above load of 91.2mA
is within the limit of 93mA.
Note: The sinking current of ports 4 -- 7 must not exceed
30mA regardless of the value of VOL'
BUS
PORT 1
M5L8048
-xxxp
PROT 2
PROG.-----------~
Fig. 2
____________~____________~__________~
Expansion interface example
•
6-42
MITSUBISHI
..... ELECTRIC
MELPS 8/85 MICROPROCESSORS
MITSUBISHI LSls
MSL 808SAP, S
8-BIT PARALLEL MICROPROCESSOR
DESCRIPTION
PIN CONFIGURATION (TOP VIEW)
This is a family of single-chip 8-bit parallel central
processing units (CPUs) developed using the N-channel
silicon-gate ED-MOS process. It requires a single 5V
power supply and has a basic clock rate of 3M Hz. With
Vee
oUTPun~~k
:NPUn~~
an instruction set that is completely compatible with that
of the M5L8080AP,S, this device is designed to improve on
the M5L 8080A with higher system speed.
Tt~N~J~~T
FEATURES
APPLICATION
5
36 +-RESET
INFNE~J-l
Y
35 +-READY FJtBT
TRAP- 6
34
-10/ M
I
g~~~~~t~SJTEpUT
STATUS 1
OUTPUT
READ CONTROL
OUTPUT
WRITE CONTROL
I
OUTPUT
ADDRESS LATCH
ENABLE OUTPUT
STATUS 0
OUTPUT
INTERRUPT
REQUEST
INPUT
INTERRUPT
ACKNOWLEDGE
OUTPUT
Instruction cycle . . . . . . . . . . . . . . . . . 1.3 JJ.s (min.)
Clock generator (with an external crystal or RC circuit)
Built-in system controller
Four vectored interrupts (one of which is non-maskable)
• Serial I/O port:
1 each
• Decimal, binary, and double precision arithmetic operations
• Direct addressing up to 64K bytes of memory
• Interchangeable with Intel's 8085A in pin connection
and electrical characteristics
g'u~~5+ULSE
37 -eLK
SOD
SID
RESTART{RST7.0
7
INTERRUPT
RST 6 5_
REQUEST
•
INPUTS
RST5.5-
• Single 5V power supply
• Software compatibility with the M5L8080AP,S (with
two additional instructions)
•
•
•
•
(5V)
39 +-HOLD HOLD INPUT
HOLD
38 -HLDA ~E~~8rLEDGE
ADl
AD2
BIDIRECTIONAL
ADDRESS
AND
DATA BUS
AD3
ADDflESS BUS
OUTPUT
As
(OV)
Outline 40P1 (M5L 8085AP), 4051 (M5L 8085A5)
1 . -_ _- - - - - '
• Central processing unit for a microcomputer
FUNCTION
Under the multiplexed data bus concept adopted, the
high-order 8 bits of the address are used only as an
address bus and the low-order 8 bits are used as an
address/data bus. During the first clock cycle of an
instruction cycle, the address is transferred. The loworder 8 bits of the address are stored in the external latch
by the address latch enable (ALE) signal. During the second and third clock cycles, the address/data bus functions
BLOCK DIAGRAM
as the data bus, transferring the data to memory or to the
I/O. For bus control, the device provides RD, WR, and
IO/M signals and an interrupt acknowledge signal INTA.
The HOLD, READY and all interrupt signals are synchronized with the clock pulse. For simple serial data transfer
it provides both a serial input data (SID) line and a serial
output data (SOD) line. It also has three maskable restart
interrupts and one non-maskable trap interrupt.
eLK
-~~
I
TEMPORARY MULTIPLEXER
TEMPORARY REGISTER Z (81
LISI
!
~I
OISI
EISI
BISI
CISI
STACK POINTER (161
INTA
RST
RST
HLDA READY
S1
SOD
ALE
5.5
7.5
SID
HOLD
So
101M
RST
TRAP
WR AD
RESETIN
INTR
RESET OUT
6.5
• MITSUBISHI
"ELECTRIC
7-3
II
MITSUBISHI LSls
MSL 808SAP, 5
8-BIT PARALLEL MICROPROCESSOR
PIN DESCRIPTIONS
Pin
As -A,S
ADo- AD 7
ALE
Name
Address bus
Bidirectional address
and data bus
Address latch enable
Input or
Functions
output
Out
Outputs the high-order 8 bits of the memory address or the 8 bits of the I/O address
It remains in the high-Impedance state during the HOLD and HALT modes
In/out
The low-order (I/O address) appears during the first clock cycle. During the second and third clock cycles. it becomes
the data bus. It remains in the high-impedance state during the HOLD and HALT modes
Out
This signal is generated during the first clock cycle. to enable the address to be latched into the latches of peripherals The falling edge of ALE is guaranteed to latch the address information The Al-E can also be used
to strobe the status information. but it is kept in the low-level state during bus idle machine cycles
Indicates the status of the bus
S,
So. S,
Status
Out
So
a
a
HALT
WRITE
READ
FETCH
a
1
a
1
1
1
The SI signal can be used as 'an advanced R!W status.
RD
Read control
Out
WR
Write control
Out
RSTS .S
RST6.S
RST7.S
TRAP
Restart interrupt
request
Trap interrupt
In
In
RESET IN
Reset Input
In
RESET OUT
Reset output
Out
X,. X2
CLK
la/tv;
Indicates that the selected memory or I/O address is to be read and that the data bus is active for data transfer.
It remains in the high-impedance state during the HOLD and HALT modes
Indicates that the data on the data bus is to be written into the selected memory at the trailing edge of the signal
WR
It remains the high-impedance state during the HOLD and HALT modes
Input timing is the same as for INTR for these three signals. They all cause an automatic insertion of an internal
RESTART RST 7.5 has the highest priority while RST 5.5 has the lowest All three signals have a higher priority
than INTR
A non-maskable restart interrupt which is recognized at the same time as an INTR It is not affected by any mask
or another interrupt
It has the highest interrupt priority.
This signal (at least three clock cycles are necessary) sets the program counter to zero and resets the interrupt enable
and HLDA flip-flops. None of the other flags or registers (except the instruction register) are affected. The CPU
is held in the reset mode as long as the signal is applied.
This signal indicates that the CPU IS in the reset mode
It can be used as a system RESET
The signal is
synchronized to the processor clock
Clock input
In
These pins are used to connect an external crystal or CR circuit to the internal clock generator
An external clock pulse can also be input through X,.
Clock output
Data transfer
control output
Out
Out
Clock pulses are available from this pin when a crystal or CR circuit is used as an input to the CPU.
This signal indicates whether the read/write is to n:emory or to I/Os
It remains in the high-ipedance state during the HOLD and HALT modes
When it is at high-level during a read or write cycle the READY indicates that the memory or peripheral is ready
READY
Ready input
In
to send or receive data. When the signal is at low-level. the CPU will wait for the signal to turn high-level before
completing the read or write cycle.
HOLD
Hold
When the CPU receives a HOLD request. it relinqUishes the use of the buses as soon as the current machine
In
request signal
HLDA
Hold
acknowledge signal
cycle is completed
The CPU can regain the use of buses only after the HOLD state is removed
ledging the HOLD signal. the address bus. the data bus.
RE. WR
Upon acknow-
and loiliii" lines are put in the high-impedance state
By this signal the processor acknowledges the HOLD request signal and indicates that it will relinquish the buses in
Out
the next clock cycle
The signal is returned to the low-level state after the HOLD request is completed
The
processor resumes the use of the buses one half clock cycle after the signal HLDA goes low.
This signal is for a general purpose interrupt and is sampled only during the last clock cycle of the instruction
INTR
Interrupt
request signal
In
When an interrupt is acknowledged. the program counter (PC) is held and an INTA signal is generated. During this
cycle. a RESTART or CALL can be inserted to jump to an interrupt service routine
Immediately after an interrupt
is accepted it may be enabled and disabled by means of software The interrupt request is disabled by the RESET
INTA
Interrupt acknowledge
control signal
Out
SID
Serial input data
In
SOD
Serial output data
Out
This Signal is used instead of
RB
during the instruction cycle after an INTR is accepted
This is an input data line for serial data. and the data on this line is moved to the 7th bit of the accumulator
whenever a RIM instruction is executed.
This is an output data line for serial data. The output SOD may be set or reset by means of the SIM instruction
Note: HOLD, READY and all interrupt signals are synchronized with clock signal.
7-4
• MITSUBISHI
.... ELECTRIC
MITSUBISHI LSls
MSL 808SAP, 5
a-BIT PARALLEL MICROPROCESSOR
STATUS INFORMATION
RST 7.5 interrupt request.
This condition will be
maintained until the request is fulfilled or reset by a SIM
or RESET instruction.
Each of the restart interrupts may be masked independently to avoid interrupting the CPU. An interrupt requested by an RST 7.5 will be stored even when its mask is
set and the interrupt is disabled. Masks can only be
changed in the RESET mode. When two enabled interrupts are requested at the same time the interrupt with the
highest priority will be accepted. The TRAP has the
highest priority followed in order by RST 7.5, RST 6.5,
RST 5.5 and INTR. This priority system does not take
into consideration the priority of an interrupt routine that
is already started. In other words, when an RST 5.5
interrupt is reenabled before the termination of the RST
7.5 interrupt routine, it will interrupt the RST 7.5.
The TRAP interrupt is very useful in preventing
disastrous errors and bus errors resulting from power
failures. The TRAP input is recognized in the same manner
as any other interrupt, but it has the highest priority, and
is not affected by any flags or masks. The TRAP input
can be sensed by either edge or level. TRAP should be
maintained high-level until it is acknowledged. But, it will
not be acknowledged again unless it turns low and high
again. In this manner, faulty operation due to noise or
logic glitches is prevented.
The serial I/O system is also considered to be an
interrupt as it is controlled by instructions RIM and SIM.
The SID is read by instruction RIM and the SOD data is
set by instruction SIM.
Status information can be obtained directly from the
M5L 8085A. ALE is used as a ~tatus strobe. As the status
is partially encoded, it informs the user in advance what
type of bus transfer is being performed. The 10/M cycle
status signal is also obtained directly. Decoded So and
S1 signals carry:
So
o
HALT
WRITE
o
READ
FETCH
S 1 can be used in determining the R/W status of all
bus transfers.
In the M5L8085A the low-order 8 bits of the address
are multiplexed with data. When entering the low-order
of the address into memory or peripheral latch circuits,
the ALE is used as a strobe.
INTERRUPT AND SERIAL I/O
The M5L8085A has five interrupt inputs-INTR, RST 5.5,
RST 6.5, RST 7.5, and TRAP. INTR has the same function
as INT of the M5L8080A. The three RST inputs, 5.5,
6.5, 7.5, are provided with programmable masks. TRAP
has the same function as the restart interrupt, except that
it is non-maskable.
When an interrupt is enabled and the corresponding
interrupt mask is not set, the three RST interrupts will
cause the internal execution of the RST. When non maskable TRAP is applied, it causes the internal execution of an
RST regardless of the state of the interrupt enable or
masks.
The restart addresses (hexadecimal) of the
interrupts are:
Interrupt
Address
2416
TRAP
RST 5.5
2C16
RST 6.5
3416
RST 7.5
3C16
Two different types of signal are used for restart
interrupts. Both RST 5.5 and RST 6.5 are sensitive to
high-level as in INTR and INT of the M5L 8080A, and are
acknowledged in the same timing as INTR. RST 7.5 is
sensitive to rising-edge, and existence of a pulse sets the
Fig. 1 Basic cycle
II
BASIC TIMING
The M5L 8085A is provided with a multiplexed data bus.
The ALE is utilized as a strobe with which the low-order
8 bits of the address on the data bus are sampled. Fig.1
shows the basic cycle in which an out instruction is fetched, and memory is read and written to the I/O port. The
I/O port address is stored in both the address bus and the
address/data bus during the I/O write and read cycle. To
enable the M5L8085A to be used with a slow memory,
the READY line is used for extending the read and write
pulse width in the same manner as in the M5L 8080A
M1
CLK
As-A15
ADO-AD1
ALE
RD
WR
101M
STATUS
T1
-
T2
M2
T3
T1
T4
M3
T3
T2
~ Lr1---J)......J ~
- J.
X.
= X
--dC:::::}-I- - -- - ~
PCH HIGH·ORDER ADDRESS
-
.......
-
""-
Cr--\
I
\
n (PORT NO.)
n
X
DATA OUTPUT
I
\
1\
-~
-
\
X
INSTRUCTION
OUT OUT
SECOND WORD
INSTRUCTION FETCH
(OUT n)
T3
T2
u-w-w-
(PCL + 1 ) H HIGH-ORDER ADDRESS
(PC+1)L
PCL
T1
S1=1, So= 1 (FETCH)
X
LO(READ)
• MITSUBISHI
"ELECTRIC
I
X
r
0,1 (WRITE)
7-5
MITSUBISHI LSls
MSL 808SAP, 5
a·BIT PARALLEL MICROPROCESSOR
MACHINE INSTRUCTIONS
~em
Inst;~
0106
class
o
1
o 1
o 1
00
IIIVI
III, n
00
LXI
B,m
00
LXI
LXI
LXI
0>
rl,
III, r
r, III
r, n
MOV
MOV
MOV
IIIVI
'"c
'"
'"
0'"
'"
tl
Instruction code
Mnemonic
r2
D,m
H,m
SP,m
00
00
00
SPHL
STAX B
STAX D
LDAX B
LDAX D
STA
m
1 1
00
00
00
00
00
LDA
m
o 0
SHLD
m
00
LHLD
m
XCHG
XTHL
00
1 1
1 1
[ADD
ADD
ADI
r
III
n
1 0
1 0
1 1
ADC
AOC
ACI
r
III
1 0
1 0
1 1
DAD
DAD
DAD
DAD
SUB
SUB
SUI
B
D
H
SP
r
III
SBB
SBB
SBI
r
III
ANA
ANA
ANI
r
III
XRA
XRA
XRI
r
III
ORA
ORA
ORI
r
III
CIIIP
CIIIP
CPI
r
III
INR
I NR
DCR
OCR
INX
INX
INX
INX
DCX
DCX
OCX
DCX
RLC
r
III
r
III
B
D
H
SP
B
D
H
SP
DsD.D3
D D D
1 1 0
D D D
D D D
1 1 0
000
<113)
o 1 0
(B2>
(113)
1 o 0
(113)
1 1 0
<113)
1 1 1
000
o 1 0
o 0 1
o 1 1
1 1 0
I
Ms
X X
X
I
I
M2
M3
(A)
0
(A)
0
«B) (C)) I
«D) (E)) I
(A)
0
M.
M.
M.
M.
M.
X
X
X
X X
x X x
x X x
x x x
x x x
x
x
x
x
x
x
x
x
(m)~(A)
X
X
X
X
(A)~(m)
X
X
X
(m)~{L)
X
X
X
X
(B) (C)
(D) (E)
(B) (C)
(D) (E)
m
M.
M.
M.
M.
M.
X
X
m
M.
(m)
I
M.
X
X
m
m+l
M.
Ms
(L)
(H)
0
0
M.
Ms
m
m+l
M.
Ms
em)
(m+1)
I
I
M.
Ms
(SP)
(SP)+1
(m+1)~{H)
o 1 0
2 A
16
3
(L)~{m)
5
X
X X
X
X
(H)~{m+1)
,
o 1
1 1
o
4
16
1
1
1
5
8 6
C 8
4
7
7
I
I
2
1
2
2
(A)
(A)
8 E
C E
4
7
7
1
1
2
1
2
2
(A) ~(A)+(r) +(CY2)
(A) ··(A) f (M) f (CY2)
(A) ~(A)+ n ~(CY2)
10
10
10
10
4
7
7
1
1
1
1
1
1
2
3
3
3
3
1
2
2
4
1
1
2
1
2
2
(A) ~ (A) - (r) - (CY2)
(A) ~ (A)-- (M) - (CY2)
(A) '-(A)- n - (cy,)
1
2
2
(A)
00
o 0
o 0
00
1
1
1
1
S S S
1 1 0
1 1 0
o
o
o
o
S
1
1
1
1
1
1
S
0
0
9 6
D 6
S S S
1 1 0
1 1 0
9 E
DE
0
0
0
0
S
1
1
o
1
2
3
9
9
9
9
7
7
(A)~(A)+(r)
(H)
(H)
(H)
(H)
(L)
(L)
(L)
(Ll
~(A)+(M)
~(A)+
(L) I (8) (C)
(H) (L) + (D) (E)
(H) (L) + (H) (L)
~ (H) (L) r (SP)
(A)~{A)
(r)
(A) ~ (A) - (M)
(A)~(A)- n
S S S
1 1 0
1 1 0
A E
E E
4
7
7
1
1
2
1
2
2
(A)-(A)V(r)
(A) ~(A)V(M)
{A)~{A)V n
S S S
1 1 0
1 1 0
4
7
7
1
1
2
1
2
2
(A)
B 6
F 6
S S S
1 1 0
1 1 0
4
B E
F E
1
1
2
1
1
1
1
o
o
o
o
o
o
o
o
1
0 0
o 0
o 1
0 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
3 4
3 5
o 3
1 3
2 3
3 3
o B
1 B
2 B
3 B
07
4
10
4
10
6
6
6
6
6
6
6
6
1
1
1
I
1
1
I
1
3
1
3
I
1
1
1
1
1
4
1
1
1
1
1
1
1
1
1
4
I
1
1 7
4
1
1
1 1 1
1 F
4
1
1
1
1
1
1
2 F
27
37
3 F
4
4
4
4
1
1
1
1
1
1
1
1
1
1
1
1
1
(A)~(A)II
1
1
1
1
~(A)
M2
M3
M.
I
I
M.
M.
M
M.
(M)
(B2>
I
I
M.
M.
(r)
(A)
(A)-(M)
(A)- n
f
I
I
M.
M.
Where. M=(H){L)
00000
00000
00000
M
M.
(M)
(82)
I
I
M.
M.
Where. M~(H) (L)
000
000
000
0
0
0
1
1
1
M
M.
(M)
(82)
I
I
M.
M.
Where. M =(H) (L)
000
000
000
0
0
0
0
0
0
M
M.
(M)
(81)
I
I
M.
M.
Where. M =(H) (L)
000
000
000
0
0
0
0
0
0
M
M.
(M)
<82)
I
I
M.
M.
00000
00000
00000
M
M.
(M)
(82)
I
I
M.
M.
M=(H) (L)
(r)~{r)+1
Where. M={H) (L)
1
(M)~(M)-I
x o X
x o X
x o x
x 0 x
(M)
<82>
Compare: Where.
(M)~{M)+1
x
x
x
x
M.
V(r)
Y n
Where. M=(H) (L)
(8) (C) ~ (8) (C)+ I
(D) (E) ~ (D) (E)+ 1
(H) (L) ~ (H) (L) + 1
esP) ~ (SP) + I
(8) (C) ~ (8) (C) 1
(D) (E) - (D) (E)-I
(H) (L) ~ (H) {L)-1
(SP) ~(SP)-l
Left shift
I
I
(M)
(B2)
000 x 0
OOOx 0
OOOx 0
000 x 0
X X
X X
X
X
x
M
M.
(M)
I
M.
M
M.
(M)
I
M.
X X X
X
X
X
X
x
X
X
X
X
X
X
X
X
X
X
X U
X
x
x
x x X
x x x x X
x X x x X
CY2 D-----!A7AS"
-"A1A~
X
IA7AS"
!Ii
...... A1AO~
x
Right shift
CY2Q
Left shift
CY2 Q-----1A7AS ............... A1AO ~
Right shift
CY2
Q----iI A 7 AS ............ · .. Al Ao H
{A)~m
Ilesults of binary addition are adjusted to B D
Cyz - 1
(CY2) ~ CY2
x
o X
X X X o x
x x x o x
X
X
x x x x x
00000
X
x
X
X
X
X
1
o
x
x
* . State IS Tl
7-6
SP)+1
M
n
(A)~(A)
(r)-~ r)
(~ (SP) )
00000
00000
00000
(A)~(A)V(M)
I
M2
M3
M
Where. M=(H) (L)
lI(r)
(A)~(A)II(M)
00000
00000
00000
x
x
x
x
~
7
7
1
= (H) (L)
~
A 6
E 6
~
Where. M
~(H)
~(A)
ggggg
00000
1
1
2
7
7
Where. M=(H) (L)
n
S S S
1 1 0
1 1 0
4
x x x x X
x x x x x
H L -(D) (E)
(H) (L) - ( (S P)-+ 1 ) { (SP' )
E B
E 3
Accumu CiliA
compen DAA
Carry se t STC
CIIIC
1
0
0
1
(SP)~m
3
3
o 1 1
o
o
1
1
3
13
o 0
o>o>E
§§§
£'UCTJ
10
0
I
I
Where. m =(B3) (B2)
3 A
RAR
~~~
c(lC'''
(L)~
3
Q 1 0
1 1 1
~
1 0
1 0
1 1
3
A
A
2
o 1 0
E
n
1 0
1 0
1 1
10
(r)
(M)
Where. m=(B3)(B2)
SP ~ H L
«B)(C) )~(A)
({D) (E) )~(A)
(A) ~ {(B) (C))
(A) ~ ((D) (E))
o 0
$~
"''0
g>"E
0:0>
n
(E)~(B2)
3
1
2
2
2
2
4
F 9
2
2
o
1
o
1
3
RAL
c
~
n
1 0
1 0
1 1
3
M.
M.
Where. m=
X X X X X
X
x x x x X
x x x x
o 0
o 0
o 0
o 0
00
o 0
00
00
00
00
00
00
o 0
0>
'"
0
00 1
S 5 S
1 1 0
1 1 0
00
o 0
o 0
o 0
1 0
1 0
1 1
0
Address bus
Flags
Functions
~~~f~ z
0
0 0
o 0 0
o 0 0
(B2>
o 0 1
o 0 1
o 0 1
(B2>
o 0 1
o 1 1
1 o 1
1 1 1
o 1 0
o 1 0
o 1 0
o 1 1
o 1 1
o 1 1
1 o 0
1 0 0
1 0 0
(B2>
1 0 1
1 o 1
1 0 1
(B2)
1 1 0
1 1 0
1 1 0
1 1 1
1 1 1
1 1 1
(B)
D D D
1 1 0
D D 0
1 1 0
000
o 1 0
1 0 0
1 1 0
o 0 1
o 1 1
1 0 1
1 1 1
o 0 0
n
~ ()
'0 '0 '0
• MITSUBISHI
"ELECTRIC
* * . State IS T2
MITSUBISHI LSls
MSL 808SAP, 5
~tem
0
Mnemonic
~7!~s""
0706
JMP
m
1 1
DsD.D3
o
0
0
0201 Do 16mal 0
notatn z
o 1 1 C 3 10
(B2>
(B3>
PCHL
JC
m
1
1
1
1
1
o
o
8-BIT PARALLEL MICROPROCESSOR
~·i·~
Instruction code
Flags
'0 '0
Functions
s
0
z
0
z
3
3
x
(PC)· m
, ,
m
1 1
o
m
1
1
o
X
o
1 0
02 to/7 3 3/2 (CY2)= 0
1
o
1 0
CA 10/7 3 3/2
0 0
o
1 0
C 2
10/7 3
3/2 ( Z ) = 0
o
1 0
F 2
10/7
3
3/2 ( 5 )= 0
1
o
1 0
FA
10/7
3
3/2 ( 5 )=,
x x x x x
3
3/2 ( P )=,
x x x x x
x x x x x
(PC)~(H)
1 0
0
(L)
OA 10/7 3 3/2 (CY2) - ,
(
x x x x x
If condition is true
(PC)'-m
JNZ
m
1
1
o
I
I
Mz
M3
Z )= 1
X
X
X
X
(62)
(63)
I
I
M2
M3
If condition is true
x
(B2>
(B3>
!
X;I~~;
(62)
(63)
X x x x X
x x x x x
E 9
(B2>
(B3>
JZ
x x
X
0 1
1 0
6
Data bus
Address bus
Mach
P CY2CY1 Contents
cycle' Contents 1/0
o
o
1
1 1
(B2>
(B3>
JNC
z
x x x x x
(B2>
(B3>
JP
m
1
1
1
1 0
(B2>
(B3>
JM
m
1
1
1
1
x x x x x
If condition is false
(PC)' (PC) I 3
(B2>
(83)
o
JPE
m
1
1
1
JPO
m
1
1
1 0
1
o
1 0
E A
10/7
0
o
1 0
E 2
1017 3 3/2 ( P )= 0
1
1
o
CO
(B2>
(B3>
(B2>
(B3>
CALL
m
1
1
o
0
1
'8
3
5
(B2>
(83)
RST
CC
"
1
m
1
1
A A A
1
1
1
12
1
o
,
( (SP)
1) «SP)
(SP)~'
(SP)-2
x
( (SP) -1) ( (SP) --2)~(PC) + I, (PC)-nX 8,
(SP) ~ (SP) - 2 Where O';;n-o: 7
5/2 (CY2) - ,
3
1
1
o
0
DC 18/9 3
1 0
1
o
0
04 18/9 3 5/2 (CY2) = 0
1
x x x x x
2)-(PC)+3, (PC)-m
X
X
X
X
(SP)- ,
(SP)-2
(SP)- ,
(SP) - 2
x x x x x
M.
Ms
m
1
1
o
B
CZ
m
1
1
o
0
1
1
o
0
CC t8/9 3 5/2 ( Z ) =,
(B2>
(B3>
Q)
c
';0
CNZ
::J
~
m
1
1
o
«SP)-I)
If condition is true
x
«SP)-2)~(PC)+-3
X
x x
00
1
o
0
x x x x
C4 18/9 3 5/2 ( z ) = 0
(SP) - 1
M.
(62)
(63)
(PC) +3
I
I
0
M2
M3
M.
(SP) -- 2
Ms
(PC) +3
0
Ms
I
I
M.
Ms
X
(PC)~m
<82>
tA2
M3
M.
Ms
M.
Ms
I
x x x x x
If condition is true
(B2>
(B3>
I
I
0
0
0
0
~: ~~~;:;
(B2>
(B3>
CNC
(82)
(63)
(PC)+3
(PC)+3
X
(SP)·- (SP)-2
(B3>
(/J
CP
m
1
1
1
CM
m
1
1
1
CPE
m
1
1
1
CPO
m
1
1
1
x x x x x
1
o
0
F 4
18/9
3
5/2 ( 5 ) = 0
1
1
o
0
F C
18/9 3
5/2 ( 5 ) = 1
1
1
o
0
EC 18/9 3 5/2 ( P )=,
x x x x x
0
1
o
0
E 4
18/9 3
5/2 ( P ) = 0
x x x x x
,
1 0
(B2>
(B3>
1
(B2>
(B3>
x x x x x
If condition is false
I
(PC)"(PC)+ 3
o
(B2>
(B3>
o
(B2>
(B>
c
::J
Q)
e:
Input!
output
control
RET
1
1
o
RC
RNC
RZ
RNZ
RP
RM
RPE
RPO
IN
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
o
o
o
o
"
"
o
0
1
C9
10
1
0
1
0
0
1
1
0
1
o
o
o
o
o
o
o
o
o
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
08
DO
C8
CO
DB
12/6
12/6
12/6
12/6
12/6
12/6
12/6
12/6
10
1
1
1
2
3/1
3 11
311
311
3/1
3/1
3
1 0
o
1
1
03
10
2
3
1
1
F B
F 3
F 5
4
4
12
1
1
1
3
C5
12
1
3
F 0
F 8
E 8
EO
1
1
1
1
,
o
PUSH PSW
1
1
1
1
1
1
1
1
1
1 1
1 0
1 0
0
0
1
o
1
1
1
PUSH B
1
1
o
0
0
1
o
1
PUSH
(B,>
, ,
0
1
1
o
1 0
1
o
1
05
'2
,
1
1
1
o
0
1
o
1
E 5
12
1
3
pOP
PSW
1
1
1
1 0
o
0
1
F 1
10
1
3
3
62>
x x x x
X
X
X
X
X
x
«SP) 1) ~ (A), ( (SP)
(SP) ~(SP)-2
«SP)-l) -(6), «SP)-2)
(SP) -(SP)-2
~
x
1
1
(SP) ~(SP)+2
(PC) .-(PC)+'
(PC) -(PC)+'
Aii RST interrupt masks, any pending RST interrupt
requests, and the serial input data from the SID, pin
are read into the accumlator
Mask is enabled (or disabled) to the RST interrupt
corresponding to the contents (bit pattern) of the
accumulator The serial output is enabled and the
serial output bit is loaded into the SOD latch
x x x x
X
x x x x
X
x
x
x x
x
x
x
x x
x
X
X
X
x
X
,
x
x
x
X
x x x
x x x
x
x
X
X X
X
X X
X X
(SP)
(SP)-2
(SP)-1
(SP)- 2
(SP)-1
(SP)-2
(SP)-1
(SP)-2
(SP)
(SP)+ 1
(SP)
(SP)+'
(SP)
(SP)+ 1
(SP)
(spi+ 1
*
Symbol
Meaning
Symbol
Meaning
(82)
Second byte of instruction
(83)
Third byte of Instruction
AAA
Binary representation for RST Instruction n
S-blt data from the most to the least
stgnlflcant bit S. Z.~. CY1 •.!5. p.x, CY2
PC
Program counter
SP
Stack pOinter
555
Bit pattern
designating
register or
memory
or
DOD
Where
M (H) (L)
I
I
M.
Ms
(62)
Ms
(Input data)
0
I
0
0
M.
Ms
M.
Ms
0
0
0
0
I
0
(E)
0
(H)
0
(L)
0
(SP) )
I
«SP)+1) I
«SP) )
I
«SP) +1) I
«SP) )
I
( (SP)+1) I
I
Ir
I
M.
Ms
M.
Ms
M.
Ms
M.
Ms
M.
Ms
M.
Ms
Ms
rA)
M.
Ms
M.
Ms
M.
Ms
M.
Ms
M.
Ms
M.
Ms
M.
Ms
M.
Ms
(A)
(F)
(6)
(C)
(D)
M.
Ms
;~~;l{)
State IS T10
**
M.
Ms
State IS T,o
Meaning
Symbol
Register
Two-byte data
One-byte data
«SP) )
«SP) +1)
(62)
X
00000
-«SP»,(H)~«SP)+')
(L)
X
X
X
x x x x x
~(C)
«SP)-1)~(D),«SP)-2)~ (E)
(SP) ~(SP) -2
( (SP) -1) ~ (H), ( (SP) -2) ~ (L)
(SP) ~(SP)-2
~ «SP», (A).- «spH 1)
(F)
(SP) ~(SP)+2
(C)
~«SP», (6) - «SP) +1)
(SP) ~(SP)+2
(E)
~ «SP) ), (D) ~ «SP) +1)
(SP) ~(SP)+2
3
X
X
x x
2)~(F)
M.
Ms
x x x
x x x x
<92> (82)
(INTE)~1
0
I
~«SP) f
(CY,) = 1
If conditIOn is true
(CY2) =0
( Z ) = 1 (PC)~( (SP)+1) «SP»
( Z ) = 0 (SP)~(SP) +2
( 5 )= 0
If condition is false
( 5 )= 1
( P )= 1 (PC)~ (PC) +- t
( P ) 0
(A) ~ (Input buffer) ~ (Input device of number n)
(Input data)
(Output deVice of number n) ~ (A)
311
PUSH H
()
U5
(PC)
3
3/1
(B2>
1
Interrupt E I
control 01
8
1
1
1
0
0
1 1
1 1
1 o
1 o
o 1
1
OUT
~
0
Data is tra.nsferred In direction shown
Register
or
memory
555
or
DOD
6
C
0
E
H
o
o
o
0
1
L
1 0
M
A
0 0
0 1
1 0
,
Contents of register or memoy location
v
-v-
1's complement
1
,
,, ,, ,
o 0
0
InclUSive OR
ExclUSive OR
Logical AND
X
0
Content of flag IS not cnangad after execution
Content offlag IS set or reset after execution
Input mode
Output mode
7-7
a
MITSUBISHI LSls
MSL 808SAP, 5
8·BIT PARALLEL MICROPROCESSOR
INSTRUCTION CODE LIST
0100
0011
0100
0101
011 0
B
1100
C
11 01
0
11
to
1111
E
F
6
MOV
MOV
MOV
MOV
ADD
B. B
D. B
H. B
M. B
B
MOV
MOV
MOV
MOV
B. C
D. C
H. C
M.C
MOV
MOV
MOV
B.D
0.0
H.D
1011
1100
1101
1110
1111
A
B
C
o
E
F
SUB
ANA
ORA
RNZ
RNC
RPO
RP
B
B
B
ADD
SUB
ANA
ORA
POP
POP
POP
POP
C
C
C
C
B
o
H
PSW
MOV
ADD
SUB
ANA
ORA
M.D
0
0
0
0
RST
RST
RST
RST
INX
MOV
MOV
MOV
MOV
ADD
SUB
ANA
ORA
H
SP
B. E
D. E
H. E
M. E
E
E
E
E
INR
INR
INR
INR
MOV
MOV
MOV
MOV
ADD
SUB
ANA
ORA
B
o
H
M
B. H
D. H
H. H
M.H
H
H
H
H
OCR
OCR
OCR
OCR
MOV
MOV
MOV
MOV
ADD
SUB
ANA
ORA
B
o
H
M
B. L
D. L
H. L
M.L
L
L
L
L
MOV
MOV
MOV
ADD
SUB
ANA
ORA
B.M
D.M
H.M
M
M
M
M
MOV
MOV
MOV
MOV
ADD
SUB
ANA
ORA
B. A
D. A
H. A
M.A
A
A
A
A
MOV
MOV
MOV
MOV
ADC
SBB
XRA
CMP
C. B
E. B
L. B
A. B
B
B
B
B
HLT
RAL
(-)
DAA
(-)
STC
(-)
DAD
DAD
DAD
DAD
MOV
MOV
MOV
MOV
ADC
SBB
XRA
CMP
B
o
H
SP
C. C
E. C
L. C
A. C
C
C
C
C
MOV
MOV
MOV
MOV
ADC
SBB
XRA
CMP
C. 0
E. 0
L. 0
A. 0
o
o
o
o
B
o
DCX
DCX
DCX
DCX
MOV
MOV
MOV
MOV
ADC
SBB
XRA
CMP
B
o
H
SP
C. E
E. E
L. E
A. E
E
E
E
E
INR
INR
INR
INR
MOV
MOV
MOV
MOV
ADC
SBB
XRA
CMP
C
E
L
A
C. H
E. H
L. H
A. H
H
H
H
H
OCR
OCR
OCR
OCR
MOV
MOV
MOV
MOV
ADC
SBB
XRA
CMP
C
E
L
A
C. L
E. L
L. L
A. L
L
L
L
L
MOV
MOV
MOV
MOV
ADC
SBB
XRA
CMP
C.M
E.M
L.M
A.M
M
M
M
M
MOV
MOV
MOV
MOV
ADC
SBB
XRA
CMP
C. A
E. A
L. A
A. A
A
A
A
A
This list shows the machine codes and corresponding
machine instruction. 03 - Do indicate the low-order 4 bits
of the machine code and 07 - 04 indicate the high-order
4 bits. Hexadecimal numbers are also used to indicate
•
1-8
1010
INX
LDAX LDAX
1011
5
IDOl
o
1001
A
1000
INX
(-)
1010
01'1
B
RLC
1000
OliO
INX
6
0111
0101
6
RZ
RC
RPE
RM
this code. The instruction may consists of one, two, or
three bytes, but only the first byte is listed.
indicates a three-byte instruction.
_
indicates a two-byte instruction.
MITSUBISHI
.... ELECTRIC
MITSUBISHI LSls
MSL 808SAP, 5
8-BIT PARALLEL MICROPROCESSOR
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Vee
Supply voltage
VI
Input voltage
r---
Limits
Conditions
With respect to Vss
Pd
Power dissipation
Topr
Operating free-air temperature range
Tstg
Storage temperature range
Unit
-0.3-7
V
-0.3-7
V
Ta=25°C
1.5
W
0-70
°C
'C
- 65-150
RECOMMENDED OPERATING CONDITIONS
(Ta= 0 -70°C unless otherwise noted)
Limits
Parameter
Symboi
Min
Nom
4.75
5
Vee
Supply voltage
VIH
High-level input voltage
2.0
VIL
Low-level input voltage
-0.5
VIH (RESIN)
High-level reset input voltage
VIL (RESIN)
Low-level reset input voltage
ELECTRICAL CHARACTERISTICS
Unit
Max
5.25
V
Vee+O.~
V
O.B
V
O.B
-0.5
(Ta=0-70°C,
V
Vee+ O.5
2.4
V
Vee=5V±5%, Vss=ov.uniess otherwise noted)
Limits
VOL
Low-level output voltage
IOL=2rnA
VOH
High-level output voltage
IOH= -400,uA
lee
Supply current from Vcc
II
Input leak current. except RESIN (Note 1)
VI=Vee
IOZL
Output floating leak current
o .45V ~VO~V ee
VIH-VIL
Hysterisls. RESIN input
Note 1:
Unit
Test conditions
Parameter
Symbol
Typ
Min
Max
0.45
V
170
rnA
-10
10
,uA
-10
10
,uA
2.4
II
V
0.25
V
---
The input RESET IN is pulled up to Vee with the resistor 3kQ (typ) when V I=GV IH (RESIN)
TIMING REQUIREMENTS
(Ta= 0 -70"C,
Vee = 5 V ± 5 %,
Vss = 0 V. unless otherwise noted)
M5L B085AP,
S
Alternative
Symbol
Limits
Parameter
Unit
symbol
Typ
Min
2000
ns
tC(ClK)
Clock cycle time
Teye
tSU(DA-AD)
DA input setup time
-tAD
-575
ns
tsu(DA-RD)
DA Input setup time
-tRD
-300
ns
th(DA-AD)
DA Input hold time
tRDH
0
ns
tSU(RDY -AD)
READY Input setup time
-tARY
tSU(RDY -ClK)
READY input setup time
-tRYS
th(RDY-ClK)
READY Input hold time
tRYH
tSU(DA-AlE)
DA input setup time
-tLDR
tSU(HlD-ClK)
HOLD Input setup time
th(HlD-ClK)
HOLD input hold time
ns
tHDS
170
ns
tHDH
0
ns
160
ns
Interrupt setup time
tiNS
tlNH
READY input setup time
ns
-460
Interrupt hold time
2:
-110
ns
th (INT -ClK)
t SUe ROY -ALE)
ns
-220
0
tSU(INT -ClK)
Note
320
Max
-tLRY
0
ns
-110
ns
The input voltage level of the input voltage level is VIL=0.45Vand VIH=2.4V
• MITSUBISHI
..... ELECTRIC
7-9
MITSUBISHI LSls
MSL 808SAP, 5
a-BIT PARALLEL MICROPROCESSOR
SWITCHING CHARACTERISTICS (Ta=
0 -70"C,
VCC= 5 V± 5
%,
Vss=OV. unless otherwise noted)
Alternative
Limits
Unit
Parameter
Symbol
symbol
Min
Typ
Max
tw (CiJ(1
elK output low-level pulse width
t 1
80
tW(ClK)
elK output high-level pulse width
t2
120
tr(ClK)
elK output rise time
tr
30
tf(ClK)
elK output fall time
tf
30
ns
td(Xl-CLK)
Delay time. Xl to elK
tXKR
30
120
ns
td(Xl-ClK)
Delay time. Xl to elK
30
150
ns
tXKF
Delay ti me. address output to ALE signal
!d(AD-AlE)
I
ns
ns
ns
90
ADo-AD7
ns
tAL
As -A,S
115
!d(AlE-AD)
Delay ti me. ALE signal to address output
tLA
100
ns
tW(AlE)
ALE pulse width
tLL
140
ns
!d(AlE-ClK)
Delay time. ALE to elK
tLCK
100
ns
!d (ALE -CaNT)
Delay time. ALE to control signal
tLC
130
tDXZ(Ro-AD)
Address disable time from read
tAFR
tDZX(Ro-AD)
Address enable time from read
!d(CONT-AD)
ADdress valid time after control signal
!d(DA-WR)
Delay time. data output to WR signal
!d(WR-DA)
Delay time. WR signal to data output
tW(CONT)
ns
0
ns
tRAE
150
ns
tCA
120
ns
tDW
420
ns
tWD
100
ns
Control signal pulse width
tcc
400
ns
!d (CONT -ALE)
Delay time. elK to ALE signal
tCL
50
ns
!d (ClK -HlDA)
Delay time. ClK to HlDA signal
tHACK
tDXZ(HlDA-BUS
Bus disable time from HLDA
tHABF
210
ns
tDZX(HlDA-BUS
Control signal disable time
tHABE
210
ns
!d (CaNT - CaNT)
Control signal disable time
tRY
!d(AD-CONT)
I
Delay ti me. address output to control signal I
110
ns
400
ADo-AD7
ns
240
tAC
ns
As -A1S
270
td (AlE-DA)
Delay time. ALE to data output
tLDW
200
ns
t d (WAHL -DA)
Delay time. WR signal to data output
tWDL
40
ns
Note 3
4
atAs-A1S. and
101M
td(AD-CONT) after the release of the high-impedance state is lOOns
Conditions of measurement. M5L 8085AP, S
M5L 8085AP-20,S-20
tC(CLK) ~ 320ns,
CL = 150pF
tC(CLK) ~500ns,
CL= 150pF
5
Reference evel for the input/output voltage is VOL = O.BV. VOH
= 2V
6
tW(CLK). tW(CLK) are 100ns(Min). 150ns(Min) respectively when 50pF+ 1 TTL loaded
Parameters described in the timing requirements and
switching characteristics take relevant values in accord-
ance with the relational expression shown in Table 1
when the frequency is varied.
Table 1 Relational expression with the frequency T (tC(CLK)) in the M5L SOS5A
TIMMING REQUIR EMENTS
(Ta = 0-70°C, Vcc= 5V±5%, Vss =ov, unless otherwise noted)
Parameter
Symbol
Alternative symbol
Test conditions
Relational expression (Note 6)
Limit
tSU(DA-AD)
DA input setup time
-tAD
225-(S/2+ N )T
Min
tSU(DA-RiS)
DA input setup time
-tRD
180- (3/z+N)T
Min
tSU(RDY-AD)
READY input setup time
-tARY
260- (31 2)T
Min
tSU( DA-ALE)
DA input setup time
-tLDR
180-2T
Min
Note7. N indicates the total number of wait cycles.
T=tC(CLK)
7-10
• MITSUBISHI
;"ELECTRIC
MITSUBISHI LSls
MSL 808SAP, 5
8-BIT PARALLEL MICROPROCESSOR
SWITCHING CHARACTERISTICS
(Ta =O-70°C, Vcc= 5V±5%, Vss = OV, unless otherwise noted)
Parameter
Symbol
Alternative symbol
Test conditions
Relational expression (Note 6)
Limit
tW(CLK)
CLK output low-level pulse width
t 1
(1/2)T-80
Min
tW(CLK)
CLK output high-level pulse width
t2
(11 2)T -40
Min
td(AD-ALE)
Delay time, address output to ALE signal
IIADO -AD7
As -A15
(Yz)T -70
tAL
(~)T -45
Min
td(ALE-AD)
Delay time, ALE signal to address output
tLA
( 1/2)T-60
tW(ALE)
ALE pulse width
tLL
(11 2)T -20
Min
td (ALE-CLK)
Delay time, ALE to CLK
tLCK
(11 2)T -60
Min
td (ALE-CONT)
Delay time, ALE to control signal
tLC
('1 2)T -30
Min
tDzx(fill-AD)
Address enable time from read
tRAE
('/2)T-l0
Min
('1 2)T -40
Min
(3/2+ N )T-60
Min
Min
td(CONT-AD)
Address valid time after control signal
tCA
td(DA-WR)
Delay time, data output to WR signal
tow
CL
-
= 150pF
Min
td(WR-DA)
Delay time, WR signal to data output
tWD
( '/2)T-60
tW(CONT)
Control signal pulse width
tcc
(3 I 2 + N )T - 80
Min
td (CONT-ALE)
Delay time, CONT to ALE signal
tCL
('/2)T-ll0
Min
td(CLK-HLDA)
DelAY time, CLK to HLDA signal
tHACK
('1 2)T -50
Min
t DXZ(HLDA-BUS)
Bus disable time from HLDA
tHABF
( '/2)T+50
Max
t DZX(HLDA-BUS)
Bus enabl€ time from HLDA
tHABE
( '/2)T+50
Max
td ( CONT - CONT)
Control signal disable time
tRY
(3/2)T-80
Min
Delay ti me, address output to control
td (AD-CONT)
signal
IADo -AD7
I As -A'5
T-80
tAC
• MITSUBISHI
.... ELECTRIC
Min
T-50
7-11
II
I
i
MITSUBISHI LSls
MSL 808SAP, 5
8-BIT PARALLEL MICROPROCESSOR
TIMING DIAGRAM
Read Cycle
CLK
I
I
T 1
I
Tz
TWAIT
I
I
T3
\'--__'IIIr--~\'___.....JIr--""""'\\'___.....I1
--.....;\\-._--1
td(ALE-CLK)1
\~_--II
td(CONT-AD)
(I
).
AS-A15
X
ADDRESS
tsu(DA-AD)
).
ADo-AD7
f
ALE
td(ALE-AD)J
IiI//)
1//1
ADDRESS)
tw(ALE)
th(DA
tDXZ(AD
IRD )
AD)
tDZX(RD-AD)
DATA IN
"'k.
V
,IE
~
td(CONT-ALE)
tsu(DAALE)
1-
td(AD-ALE)
tsu(DA-RD)
td(ALE-CONT)
td(AD-CONT!
.1
I'it-
tw(CONT)
1
t su ( ROY - AD)
th(RDY
CLK)
tSU(RDY-CLKlj-
READY
I
"
Write Cycle
TWAIT
Tz
\I
CLK
-
T3
)
td(ALE - CLK)
N
AS-A15
)
~
ADDRESS
(r
td( CaNT - AD)
JL
ADo-AD7
)
ADDRESS
tw(ALE)
ALE
X
td(DA-WR)
td~
j
I
td(CONT-ALE)
I
th(RDY-CLK)
tsu(RDY-AD)
READY
7-12
td(WR-DA)
tw( caNT)
td( ALE - caNT)
td(AD-CONT)
K
fL
td(ALE-AD)_11
t su ( ROY
CLK1
• MITSUBISHI
"ELECTRIC
;
MITSUBISHI LSls
MSL 808SAP, 5
8-BIT PARALLEL MICROPROCESSOR
Hold Cycle
T2
T3
""\
CLK
THOLD
\
\
f
HOLD
,
THOLD
:~
\
I
tSU(HLD-CLK)1
td(CLK-HLDA)
i
th(HLD-CLK)
HLDA
--
(
1:
ttDXZ(HLDA-BUS)
ItDZX(HLDA-BUS)
r
r
BUS
T)
l
~
~
i~H
(ADDRESS, CONTROLS)
I
I
Interrupt and Hold Cycle
T4
T3
Tl
Ts
T6
I
THOLD
I
Tl
I_II
BUS FLOATING
ALE
RD ~--------------------~----~~____________________~
HOLD
----------~--~U.U
•
Ilhtt(HLD-CLK)
HLDA
-------------td(CLK-HLDA)
tDXZ(HLDA-BUS)
Clock Output Timing Waveform
XI INPUT
CLOCK INPUT
• MITSUBISHI
.... ELECTRIC
7-13
MITSUBISHI LSls
MSL 8085AP, 5
8-BIT PARALLEL MICROPROCESSOR
TRAP INTERRUPT AND RIM INSTRUCTIONS
Table 2 TRAP interrupt and RIM instructions
TRAP generates interrupts regardless of the interrupt
~er
1
2
3
4
5
6
Instruction in address a-1
EI
EI
EI
01
01
01
Instruction in address a+ 2
Condition
enable filp-flop (INTE FF). The current state of the INTE
FF is stored in flip flop A (AFF) of the CPU and then the
INTE FF is reset. The first RIM instruction after the
generation of a TRAP interrupt differs in function from
the ordinary RIM instruction. That is, the bit 3 (lNTE FF
information) in the accumulator ((A)3) after the execution
of the RIM instruction contains the contents of the A FF,
regardless of the state of the INTE FF at the time the RIM
instruction is executed. These details are shown in Fig.2,
Tables 1 and 2.
Fig. 2 TRAP interrupt processing
EI
NOP
01
EI
NOP
01
Contents of (A)3 after the execution of the RIM instruction in
address a+3
1
1
1
0
0
0
State of INTE FF after the execution
of the RIM instruction in address
a+3
1
0
0
1
0
0
Contents of (A)3 after the execution of the RIM instruction in
address a+4
1
0
0
1
0
0
State of INTE FF after the execution
of the RIM instruction in address
a+4
1
0
0-
1
0
0
Note
3-
The contents of (Ab after the excutlon of the RIM instruction IS
an information of the INTE
FF The INTE FF assumes state "1"
when it is in the EI state. and "0" when it is in the 01 state.
TRAP
INTERRUPT-
(1)
Table 3 TRAP interrupt and INTE FF processing
MEMORY
ADDRESS
a-2
~2416
(2)
a-1
a
NOP
a+1
NOP
~
RET
a+2
a+3
RIM
a+4
RIM
Below are the explanations of Fig. 2.
1. The TRAP interrupt request is issued while the instruction in address a is being executed.
2. The TRAP interrupt causes the same action as an RST
instruction and then jumps to address 2416.
3. It returns to address a+1 after executing the RET
instruction.
Table 1 shows the information in the INTE FF when
the instructions EI and/or DI are executed at addresses
a-1 and a+2.
Fig. 3 is a flow chart of the TRAP interrupt processing
routine.
Fig. 3 TRAP interrupt processing routine
yx
L:
2416 CALL
TRAP
INTERRUPT ~ a
REQUEST
AOD
0
2716
PUSH--
SAVING REGISTER
RIM
PUSH
PSW
SAVING INTE
(x)
( y)
FF
TRAP INTERRUPT
PROCESSING PROGRAM
RET
POP
PSW
ANI
0815
INTE
FF RETURN PROCESSING
JZ
(xa)
(xb)
\
\
POP - - - } RETURNING REGISTER
EI
\----
RET
\xbxa POP- --- } RETURNING REGISTER
'c.__
RET
7-14
• MITSUBISHI
.... ELECTRIC
MITSUBISHI LSls
MSL 808SAP, 5
8-BIT PARALLEL MICROPROCESSOR
PULL-UP OF THE RESET IN INPUT
Conditions for Using a Quartz Crystal Element
In order to increase the noise margin, the RESET IN input
1. Quartz Crystal Specifications
terminal is pulled up by about 3kn (typ) when the
condition VI~ V IHCRESiN) is satisfied. Fig. 4 is a connection
• Parallel resonance
• The frequency is 2 times the operation frequency (26.25MHz)
diagram of the RESET IN input, and Fig. 5 shows the
relation between input voltage and input current.
• I nternal load capacitance: Approx. 16pF
• Parallel capacitance: Below 7pF
. Fig~ 4 Connections of RESET IN input
• Equivalent resistance: Below 75[2. (for operation above
4MHz)
INSIDE CPU
• For operation in the range 2-4MHz, the resistance
should be made as small as possible.
Vee
• Drive capability: Above 5mW (the power at which the
crystal will be destoryed)
RESET
2. External Circuitry
IN
M5L8085AP
C'S: Wiring capacitance of pin X,
C2S: Wiring capacitance of pin X2
Fig. 5 RESET IN input current vs input voltage
(rnA)
C2L
0.6
I I
C2S
•
For operation above 4MHz:
•
C1 = C2 = 10pF
For operation below 4MHz:
C1 = C2 = 15pF
C, S: External capacitance at pin X,
C2L: External capacitance at pin X2
C,=C'L+C,S
C2 = C2L + C2S
(V)
VIH
INPUT VOLTAGE
DRIVING CIRCUIT' OF Xl AND X2 INPUTS
Input terminals, X 1 and X2 of the M5L SOS5A can be
driven by either a crystal, RC network, or external clock.
Since the drive clock frequency is divided to 1/2 internally,
the input frequency required is twice the actual execution
frequency (6MHz for the M5L SOS5A, which is operated
at 3MHz). Figs. 6 and 7 are typical connection diagrams
for a crystal and CR circuit respectively.
Fig. 6 Connections when
crystal is used for
X1 and X2 inputs
Fig. 7 Connections when
RC network is used
for X1 and X2 inputs
..--_ _ _--=-.2 Xz
10 PF
r
OSCILLATION FREQUENCY
A 1- 6 MHz PARALLEL RESONANT
CRYSTAL OSCILLATOR IS USED
OSCILLATION FREQUENCY
ABOUT 3MHz
• MITSUBISHI
.... ELECTRIC
7-1S
II
MITSUBISHI LSls
MSL 808SAP, 5
8-BIT PARALLEL MICROPROCESSOR
WAIT STATE GENERATOR
Fig. 8 shows a typical1-wait state generator for low speed
RAM and ROM applications.
Fig. 8 1-wait state generator
,---~--READY
M5L 8085AP
RELATION OF RIM AND SIM INSTRUCTIONS WITH
THE ACCUMULATOR (SUPPLEMENTARY DESCRIPTION).
The contents of the accumulator after the execution of
a
RIM instruction is shown in Table 4.
Table 4 Relation of the instruction RIM
with the accumulator
5
6
7
2
3
4
0
1
ISlDlr 7.slr 6.s11 s.sl'E IM7.sIM6.sIMs.sl
~
CONTENTS OF
ACCUMULATOR
~
L
STATE OF INTERRUPT MASK
("1" WHEN THE MASK IS SET)
STATE OF INTERRUPT ENABLE
FLAG ("1" WHEN ENABLE)
STATE OF UNFULFILLED
INTERRUPT REQUEST
17.5 STATE OF PENDING FLIP-FLOP
165}
15.5
STATE OF TERMINALS.
RST 6 5 AND RST 5.5
SERIAL INPUT DATA (SID)
The contents of the accumulator after the execution of
a SIM instruction is shown in Table 5.
Table 5 Relation of the SIM instruction
with the accumulator
7
6
I:SOD)1:SSE:1
5
X
4
3
2
1
0
II;
CONTENTS OF
R7.5 IMSE:11M7.S>1 M6.S>1 MS.S>1 ACCUMULATOR
~ MASK SET/RESET OF RST 5 5
1
MASK SET/RESET OF RST 6.5
MASK SET/RESET OF RST 5.5
SET = 1 INTERRUPT DISABLE
RESET = 0 INTERRUPT ENABLE
MASK SET ENABLE
ENABLES SET/RESET OF MASKS
FOR BITS 0- 2. WHEN MSE IS ''1''
RST 7.5 PENDING RESET
PENDING FLIP-FLOP OF
RST 7.5 IS RESET WHEN R7.5 IS ",".
NOT USED
SOD SET ENABLE
VALUE IN ,BIT 7 IS TRANS
FERRED TO SOD LATCH WHEN
SSE IS ","
SERIAL OUTPUT DATA
7-16
• MITSUBISHI
' " ELECTRIC
MITSUBISHI BIPOLAR DIGITAL ICs
MSL8212P
8-BIT INPUT/OUTPUT PORT WITH 3-STATE OUTPUT
DESCRIPTION
PIN CONFIGURATION (TOP VIEW)
The M5L 8212P is an input/output port consisting of an
8-bit latch with 3-state output buffers along with control
and device selection logic.
Also included is a service
request flip-flop for the generation and control
interrupts to a microprocessor.
bipolar Schottky TTL technology.
of
It is fabricated using
FEATURES
•
Service request flip-flop for interrupt generation
•
Three-state outputs
k~6~~~UPT
DATA INPUT
224-018
DATA INPUT
CONTROL
DATA OUTPUT
012-+ 5
DATA INPUT
DATA OUTPUT
DATA INPUT
DATA OUTPUT
•
Low input load current: IlL = absolute -250pA (max)
•
High output sink current: IOL
DATA INPUT
= 16mA (max)
output voltage for direct interface to a
STROBE INPUT STB-+ 11
(OV)GNO
M5L8080AP, S CPU: VOH = 3.65V (min)
•
Vee (5V)
2 -+ 1NT
DATA INPUT
Parallel 8-bit data register and buffer
High-level
24
MODE INPUT
DATA OUTPUT
•
•
DEVICE SELECT
Interchangeable with Intel's 8212 in terms of electrical
characteristics and pin configuration
a
APPLICATIONS
•
Outline 24P1
Input/output port for a M5L8080AP, S
•
Latches, gate buffers or multiplexers
request flip-flop SR is set. Also, the strobed input STB is
•
Peripheral and input/output functions for microcomputer systems
active, the data inputs
Dll~018
are latched in the data
latches, and the service request flip-flop SR is reset.
When MD is high, the data in the data latches is trans-
FUNCTION
Device select 1 (DS I) and device select 2 (DS 2 ) are used for
ferred to the data outputs. When DS l is low and DS 2 is
high, the data inputs are latched in the data latches. The
chip selection when the mode input MD is low. When
low-level clear input CLR resets the data latches and sets
DS 1 is low and DS 2 is high, the data in the latches is
the service request flip-flop SR, but the state of the output
transferred to the data outputs
DOl~D08;
and the service
buffers is not changed.
BLOCK DIAGRAM
r--.
Vee (5V)
STROBE INPUT STB \.11)-----+-----4--1
MODE INPUT M D ri't-----+~=--_tRVL~C
PG
IN OUT
RL2
50Q
CL
II
• MITSUBISHI
.... ELECTRIC
7-19
MITSUBISHI BIPOLAR DIGITAL ICs
MSL8212P
a.BIT INPUT/OUTPUT PORT WITH 3·STATE OUTPUT
TIMING DIAGRAMS
REFERENCE LEVEL =1.5V
~------------------051, 052, STB_ _ _ _ _ _ _ _ _ _ _ _--'
t-----'---'-~
~--------------------------
---------------------~
~------------------051, 052, STB
__________________ J
/-------------------------------
051, 052, MD
tPZL(MO-OO)
tPZH(MO-OO)
STB
(
tw
INT
CLR
001-00a
7-20
t
tw
1-
tHL(STS-iNT)
;r
tHL(CLR-OO)
• MITSUBISHI
..... ELECTRIC
MITSUBISHI BIPOLAR DIGITAL ICs
MSL8216P, MSL8226P
4-BIT PARALLEL BIDIRECTIONAL BUS DRIVERS
DESCRIPTION
The M5L 8216P and M5L 8226P are 4-bit bidirectional
bus drivers and suitable for the 8-bit parallel CPU
M5L8080AP, S (8080A). They are fabricated by using
bipolar Schottky TTL technology, and have high fan-out.
PIN CONFIGURATION (TOP VIEW)
FEATURES
• Parallel 8-bit data bus buffer driver
• Low input current OlEN, CS:
IlL =-500,uA(max)
01, DB:
IlL =-250,uA(max)
• High output current M5L8216P
DB:
IOL =55mA(max)
IOH =-10mA(max)
DO:
IOH =-1mA(max)
M5L8226P
DB:
IOL =50mA(max)
IOH =-10mA(max)
DO:
IOH =-1mA(max)
• Outputs can be connected with
the CPU M5L8080AP, S:
VOH =3.65V(min)
CHIP SELECT INPUT
cs-
DATA OUTPUT
000-
Vee
2
15 -
OlEN
~~~LE INPUT
DATA OUTPUT
BIDIRECTIONAL
DATA BUS
DATA INPUT
DATA OUTPUT
DATA INPUT
BIDIRECTIONAL
DATA BUS
01,-
DATA INPUT
GNO
OutUne 16P4
When the terminal CS is high-level, all outputs are in
high-impedance state, and when low-level, the direction
of the bidirectional bus can be controlled by the terminal
DIEN.
The terminal OlEN controls the data flow. The data
flow control is performed by placing one of a pair of
buffers in high-impedance state and allowing the other to
transfer the data.
• Three-state output
• The M5L8216P has interchangeability with Intel's 8216
in pin configuration and electrical characteristics, and
the M5L8226P with Intel's 8226.
APPLICATION
Bidirectional bus driver/receiver for various types of
microcomputer systems.
FUNCTION
The M5L8216P is a noninverting and the M5L8226P is
an inverting 4-bit bidirectional bus driver.
BLOCK DIAGRAM
DATA INPUT
DATA OUTPUT
DATA INPUT
010
M5L8216P
4 )----;O'----l'>--I--~
DATA INPUT
000 2
~-+---<=
1--+--
DATA OUTPUT
01,
7
}--;---+--C>---+----,
DATA INPUT
5
J---+---<: 1--+-----'
DATA OUTPUT DO,
012
9 ~-t--_l-:>-_l_~
DATA OUTPUT
002
11~-+--<'1---+
DATA OUTPUT
003 14}+--+--<
DATA INPUT
ENABLE
1~~0~
M5L8226P
'------+-+------..-l
DIEN
15~---4~----"
010
01,
DATA OUTPUT DO,
BIDIRECTIONAL
DATA BUS
DATA INPUT 012
1
4 t--------I ~:>---t-~
000 2/---+_-o<
7 t-----t----I ">o>--+--,
5 ~--t---o<
DATA OUTPUT
002 11)--+_---<><
DATA OUTPUT
003 14r--+---<><~1--+-
cs .~~~~CT INPUT
DATA
ENABLE INPUT
• MITSUBISHI
..... ELECTRIC
BIDIRECTIONAL
DATA BUS
9 ~--t-----1 '>o---+--~
~--r--~
1
cs
~~~~CT
INPUT
7-21
II
MITSUBISHI BIPOLAR DIGITAL ICs
MSL8216P, MSL8226P
4·BIT PARALLEL BIDIRECTIONAL BUS DRIVERS
ABSOLUTE MAXIMUM RATINGS
(Ta=0-75'C. unless otherwise noted)
Parameter
Symbol
Vee
Supply voltage
VI
Input voltage.
VI
Unit
Limits
Conditions
7
V
5.5
V
Input voltage. DB input
Vee
V
Vo
High-level output voltage
Vee
V
Pd
Power dissipation
700
mW
Topr
Operating free-air temperature range
0-75
'C
Tstg
Storage temperaturerange
-65-+150
'C
CS.
OlEN. 01 inputs
With respect to GND
Ta=25'C
RECOMMENDED OPERATING CONDITIONS
(Ta=0-75"C. unless otherwise noted)
Limits
Symbol
Parameter
Unit
Min
Nom
Max
4.75
5
5.25
VCC
Supply voltage
10H
High-level output current. DO output
-1
mA
V
10H
High-level output current. DB output
-10
mA
10L
Low-level output current. DO output
15
mA
10L
Low-level output current. DB output
25
mA
ELECTRICAL CHARACTERISTICS
(Ta = 0 -75 'C. unless otherwise noted)
Limits
Symbol
Parameter
Conditions
Unit
Min
VIH
High-level input voltage
VIL
Low-level input voltage
VIC
Input clamp voltage
VOH
High-level output voltage. DO output
10H=-lmA
VOH
High-level output voltage. DB output
10H= -10mA
VOL1
Low-level output voltage. DO output
VOL1
Low-level output voltage. DB output
Typ
Max
2
VCC=4.75V.
Ilc= -SmA
V
0.95
V
-1
V
3.65
V
2.4
V
VCC=4.75V
10L= 15mA
0.5
V
IOL=25mA
0.5
V
M5L 8216P
IOL=55mA
0.7
V
M5L 8226P
IOL=50mA
0.7
VIH=2V
VIL=0.95V
VOL2
Low-level output voltage. DB output
10ZH
Off-state output current. DO output
10ZH
Off-state output current. DB output
V
20
J.lA
VO=5.25V
100
J.lA
-20
J.lA
-100
J.lA
20
J.lA
10
J.lA
-500
J.lA
VCC=5.25V
10ZL
Off-state output current. DO output
10ZL
Off-state output current. DB output
hH
High-level input current. OlEN. CS inputs
VCC=5.25V.
IIH
High-level input current. 01. DB inputs
VIL=OV.
IlL
Low-level input current. OlEN CS intputs
Vcc=5.25V.
hL
Low-level input current. 01. DB input
VIL=OV.
los
Short-circuit output DO output (Note 2)
los
Short-circuit output. DB output (Note 2)
Vo=0.5V
VI=5.25V
Supply current
VIH=4.5V
VI=0.5V
Vcc=5.25V.
ICC
VIH=4.5V
M5L8216P
-65
mA
-30
-120
mA
100
mA
100
mA
M5L8216P
120
mA
M5L8226P
100
mA
Vcc=5.25V
Supply current Z
Notel: Current flowing Into an IC IS pOSItive. out IS negative.
2 : All measurements should be done quickly. and not more than one output should be shorted at a time.
7-22
J.lA
-15
Vo=OV
M5L8226P
Iccz
-250
• MITSUBISHI
..... ELECTRIC
MITSUBISHI BIPOLAR DIGITAL ICs
MSL8216P, MSL8226P
4-BIT PARALLEL BIDIRECTIONAL BUS DRIVERS
SWITCHING CHARACTERISTICS
(Vcc=5V.
Ta=25"C. unless otherwise noted)
Limits
Unit
Conditions
Parameter
Symbol
(Note 3)
tPHL(DB- DO)
tpLH(DB-DO)
t PHL( 01- DB)
tPLH(DI-DB)
tpHZ(Cs- DO)
tPLZ(Cs-DO)
High-to-Iow-and low-to-high output propagation time.
from input DB to output DO
CL =30pF, RLl =300 Q.
RL2 =600Q
High-to-Iow and low-to-high output
propagation time. from input 01 to
output DB
CL=300pF.
RL2=180Q
M5L8216P
RL 1 =90 Q.
M5L8226P
High-to-Z and low-to-Z output propagation time.
from inputs OlEN. CS. to output DO
CL=5pF.
RLl = 10kQ, RL2= lkQ
CL=5pF.
RLl =300Q, RL2 =600Q
30
ns
25
ns
35
ns
ns
ns
M5L 8216P
65
ns
54
ns
35
ns
65
ns
RL2 =600 Q
CL=5pF. RLl =10kQ. RL2= lkQ
Output disable time. from inputs OlEN. CS. to
output DB
CL=5pF. RLl =90 Q. RL2=180Q
M5L 8216P
CL =300pF.
tpZH(Cs- DB)
RLl = 10kQ. RL2= lkQ
M5L 8226P
54
ns
M5L 8216P
65
ns
54
ns
CL =300pF.
tPZL(Cs-DB)
RLl =90 Q.
RL2=180Q
M5L 8226P
TIMING DIAGRAM (Reference level
ns
65
CL =30pF. RL 1 =300 Q.
Output enable time. from inputs
OlEN. CS to output DB
25
RL2= lkQ
M5L 8226P
tpLZ(Cs-DB)
Max
54
CL =30pF. RLl =10kQ.
tPZL(Cs-DO)
tpHZ(Cs- DB)
Typ
M5L 8226P
M5L 8216P
tpZH(Cs-DO)
Output enable time.
from inputs OlEN. CS to output DO
Min
= 1 .5V)
II
Vee
Note 3 : Measurement circuit
OBo-OB3
010-013 _ _ _ _J
tpLH(DB-DO). tPLH(DI-DB)
tpHL( DB - DO)· tpHL( 01 - DB)
000 -003
DBa - OB3 _ _ _ _ _ _.J
tpHZ (05 - DB)
tPZL(05 -DO). tPZL(05 -DB)
000 -003
DBa -OB3
m----.......t'"
tpLZ(05-DB)
1>+;_----
Fig. 1 Data bus buffer
DBIN
APPLICATION EXAMPLES
Fig.1 shows a pair of M5L.8216PS or M5L8226PS which
are directly connected with the M5L 8080A CPU data bus,
and their control signal. Fig. 2 shows an example circuit
in which the M5L8216P or M5L8226P is used as an
interface for memory and I/O to a bidirectional bus.
SYSTEM DATA BUS
• MITSUBISHI
.... ELECTRIC·
7-23
MITSUBISHI BIPOLAR DIGITAL ICs
MSL8216P, MSL8226P
4·BIT PARALLEL BIDIRECTIONAL BUS DRIVERS
Fig. 2 Memory and 1/0 interface to bidirectional data bus
I/O
INTERFACE
MEMORY
is
is
8
01
01
DO
1
-~ OlEN
4 J4
4 14
4 f4
CS 0-
01
DO
r< OlEN
01
1
CSP-
DO
15
r<
CS
OlEN
M5L8216P
OR
M5L8226P
M5L8216P
OR
M5L8226P
M5L8216P
OR
M5L8226P
M5L8216P
OR
M5L8226P
DB
DB
DB
DB
BUSEN
4
4
S
BIDIRECTIONAL DATA BUS
Precautions for Use
When the M5L8216P data input or two-way data bus is set
to high to disable-output from the two-way bus or data
output, care is required as a low glitch of approximate
width 10nS will be generated.
7-24
4 t4
DO
1
15
CS P-- I/OR-[< OlEN
15
8
• MITSUBISHI
"ELECTRIC
4
4
~
MITSUBISHI LSls
MSL81SSP
2048-BIT STATIC RAM WITH I/O PORTS AND TIMER
DESCRIPTION
PIN CONFIGURATION (TOP VIEW)
The M5L8155P is a 2K-bit RAM (256-word by 8-bit)
fabricated with the N-channel silicon-gate ED-MOS tech-
PC3 ..... 1
I/O PORT C { PC4 .... .
nology. This IC has 3 I/O ports and a 14-bit counter/timer
which make it a good choice to extend the functions of an
TIMER INPUT
8-bit microcomputer. It is incased in a 40-pin plastic D I L
package and operates with a single 5V power supply.
RESET INPUT
Vee (5V)
TIMER IN-+
RESET-+ 4
I/O PORT C
TIMER OUTPUT TIMER OUT +-- 6
SELEC~E~N~Et
FEATURES
•
Compatible with ME LPS 85 devices
•
Static RAM: 256 words by 8 bits
•
Programmable 8-bit I/O port: 2
•
Programmable 6-bit I/O port: 1
•
Programmable counter/timer: 14 bits
CE-+
READ INPUT
RD -+
I/O
PORT B
WRITE INPUT
ADDRESS LATCH
ENABLE INPUT
•
Multiplexed address/data bus
•
Single 5V power supply
•
Interchangeable with Intel's P8155 in pin
•
Configuration and electrical characteristics
BIDIRECTIONAL
ADDRESS/DATA BUS
I/O
PORT A
(OV) Vss
APPLICATION
•
10 M -+ 7
CHIP ENABLE INPUT
Extension of I/O ports and timer function for MELPS
8/85 and ME LPS 8-48 devices
Outline 40P1
1 . . . - - . . -_
_- - - - - '
FUNCTION
as control terminals for the 8-bit ports, so that the 8-bit
The M5L8155P is composed of RAM, I/O ports and
counter/timer. The RAM is a 2K-bit static RAM organized
ports can be operated in a handshake mode. The counter/
as 256 words by 8 bits. The I/O ports consist of 2 program-
timer is composed of 14 bits that can be used to count
mable 8-bit ports and 1 programmable 6-bit port. The
down (events or time) and it can generate square wave
pulses that can be used for counting and timing.
terminals of the 6-bit port can be programmed to function
BLOCK DIAGRAM
,-
(5V) Vee 40
(OV) Vss 20
STATIC RAM
I/O
PORT A
(256 WORDS x 8 BITS)
DATA BUS
BUFFER
BIDIRECTIONAL
ADDRESS/DATA BUS
8-BIT INTERNAL
DATA BUS
I/O
PORT B
RESET INPUT RESE T 4
MEMORY SELECT INPUT
CHIP ENABLE INPUT
READ INPUT
WRITE INPUT
101M 7
R~AD/
WRITE
CONTROL
CIRCUIT
PC 4
PCS)
PC 3
I/O
PC 2 PORT C
ADDRESS LATCH
ENABLE INPUT
PC I
PC a
~----------0----4-----------l
TIMER IN
TIMER INPUT
TIMER OUT
TIMER OUTPUT
• MITSUBISHI
"ELECTRIC
7-25
II
MITSUBISHI LSls
MSL81SSP
2048-BIT STATIC RAM WITH I/O PORTS AND TIMER
OPERATION
Data Bus Buffer
This 3-state bidirectional 8-bit buffer is used to transfer the
data while input or output instructions are being executed
by the CPU. Command and address information is also
transferred through the data bus buffer.
Read/Write Control Logic
The read/write control logic controls the transfer of data by
interpreting I/O control bus output signals (RD, WR, 10/M
and ALE) along with CPU signal (CE). RESET signal is also
used to control the transfer of data and commands.
Bidirectional Address/Data Bus (ADo '" AD7 )
The bidirectional address/data bus is a 3-state 8-bit bus. The
8-bit address is latched in the internal latch by the falling
edge of ALE. Then if 10/M input signal is at high-level, the
address of I/O port, counter/timer, or command register is
selected. If it is at low-level, memory address is selected.
The 8-bit address data is transferred by read input (RD)
or write input (WR).
Chip Enable Input (CE)
When CE is at low-level, the address information on address/
data bus is stored in the M5L8155P
Read Input (RD)
When RD is at low-level the data bus buffer is active. If
10/M input signal is at low-level, the contents of RAM are
read through the address/data bus. If 10/M input is at highlevel, the selected contents of I/O port or counter/timer are
read through the address/data bus.
Write Input (WR)
When WR is at low-level, the data on the address/data bus
are written into RAM if 10/M is at low-level, or if 10/M is
at high-level they are written into I/O port, counter/timer
or command register.
Address Latch Enable Input (ALE)
An address on the address/data bus along with the levels
of CE and 10/M are latched in the M5L8155P on the falling
edge of ALE.
la/Memory Input (lO/M)
When 10/M is at low-level, the RAM is selected, while at
high-level the I/O port, counter/timer or command register
are selected.
I/O Port A (PA o '" PAl)
Port A is an 8-bit general-purpose I/O port. Input/output
setting is controlled by the system software.
I/O Port B (PBo "" PB 7 )
Port B is an 8-bit general-purpose I/O port. Input/output
setting is controlled by the system software.
I/O Port C (peo '" PCs )
Port C is a 6-bit I/O port that can also be used to output
control signals of port A (PA) or port B (PB). The functions
of port C are controlled by the system software. When port
7-26
C is used to output control signals of ports A or B the assigment of the signals to the pins is as shown in Table 1.
Table 1 Pin assignment of control signals of port C
Pin
Function
(port B strobe)
PCs
B STB
PC4
B BF
(port B buffer full)
PC3
B INTR
(port B interrupt)
PC2
A STB
(port A strobe)
PC,
A BF
(port A buffer full)
PCa
A INTR
(port A interrupt)
Timer Input (TIMER IN)
The signal at this input terminal is used by the counter/
timer for counting events or time. (3MHz max.)
Timer Output (TIMER OUT)
A square wave signal or pulse from the counter/timer is
output through this pin when in the operation mode.
Command Register (8 bits)
The command register is an 8-bit latched register. The loworder 4 bits (bits 0'" 3) are used for controlling and determination of the mode of the ports. Bits 4 and 5 are used as
interrupt enable flags for ports A and B when port C is used
as a control port. Bits 6 and 7 are used for controlling the
counter/timer. The contents of the command register are
rewritten by output instructions (address I/O XXXXXOOO).
Details of the functions of the individual bits of the
command register are shown in Fig. 1.
7
6
5
4
3
2
1
0
TM2 TM,I'EB IlEA I PC2 PC, I PB I PA
I
LpORT A
I/O FLAG
1: OUTPUT PORT A
0: INPUT PORT A
~PORT
B I/O FLAG
1: OUTPUT PORT B
0: INPUT PORT B
I
PORT C FLAG
00:
11:
01:
10:
ALT1
ALT2
ALT3
AL T4
PORT A INTERRUPT
ENABLE FLAG
1:ENABLE INTERRUPT
O:DISABLE INTERRUPT
PORT B INTERRUPT
ENABLE FLAG
1: ENABLE INTERRUPT
0: DISABLE INTERRUPT
COUNTER/TIMER CONTROL
00: NO INFLUENCE ON COUNTER/TIMER OPERATION
01: COUNTER/TIMER OPERATION DISCONTINUED (IF NOT
ALREADY STOPPED)
10: COUNTER/TIMER OPERATION DISCONTINUED AFTER THE
CURRENT COUNTER/TIMER OPERATION IS COMPLETED.
11: COUNTER/TIMER OPERATION STARTED
Fig. 1 Bit functions of the command register
• MITSUBISHI
.... ELECTRIC
MITSUBISHI LSls
MSL81SSP
2048-BIT STATIC RAM WITH I/O PORTS AND TIMER
Status Register (7 bits)
The status register is a 7-bit latched register. The loworder 5 bits (bits 0'"'" 4) are used as status flags for the I/O
ports. Bit 6 is as a status flag for the counter/timer. The
I)----C
DATA
II
(
Basic Output
\r
I
\
101M
\~
,(
\
ADo-A D7
}~
~K
ADDRESS
~:
-'1'\. .
ALE
K
th(RW-L)
tsu (D-W)
th (L-A)
tsu (A-L)
DATA
-J;
tw(L)
th (L-RWH)
th (W-D)
J
I
If-
l
tw (RWL)
"--
tw (RWH)
tPHL(W-P)
tPLH (W-P)
X
PORT
I
• MITSUBISHI
.... ELECTRIC
7-31
MITSUBISHI LSls
MSL81SSP
2048·BIT STATIC RAM WITH I/O PORTS AND TIMER
Strobed Input
SF
tPHL(R-BF)
INTR
tSU(P-STB)
th(STB-P)
PORT
Strobed Output
SF
INTR
PORT
Timer
(Note 8)
TIMER IN
TIMER OUT
PULSE MODE
TIMER OUT
I
SQUARE WAVE MODE - - - - - - - - - __ .J (Note 9)
Note 8: The wave form is shown counting down from 5 to 1.
9: As long as the M1 mode flag of the timer register
is at high-level, pulses are continuously output.
7-32
• MITSUBISHI
.... ELECTRIC
MITSUBISHI LSls
MSL81S6P
2048-BIT STATIC RAM WITH I/O PORTS AND TIMER
DESCRIPTION
PIN CONFIGURATION (TOP VIEW)
The M5L8156P is a 2K-bit RAM (256-word by 8-bit)
fabricated with the N-channel silicon-gate EO-MOS tech-
PC 3 +. ,
I/O PORT C
nology. This IC has 3 I/O ports and a 14-bit counter/timer
which make it a good choice to extend the functions of an
8-bit microcomputer. It is incased in a 40-pin plastic 01 L
package and operates with a single 5V power supply.
{ PC4
+.
Vee (5V)
2
TIMER INPUT
TIMER IN -+ 3
RESET INPUT
RESET-. 4
I/O PORT C
TIMER OUTPUT TIMER OUT +- 6
FEATURES
•
Compatible with MELPS 85 devices
•
Static RAM: 256 words by 8 bits
•
Programmable 8-bit I/O port: 2
•
Programmable 6-bit I/O port: 1
•
Programmable counter/timer: 14 bits
SELEC~E~~~t
10 M -+
CHIP ENABLE INPUT
CE-+
WRITE INPUT
ADDRESS LATCH
ENABLE INPUT
•
Multiplexed address/data bus
•
Single 5V power supply
•
Interchangeable with Intel's P8156 in pin
•
Configuration and electrical characteristics
BIDIRECTIONAL
ADDRESS/DATA BUS
I/O
PORT A
a
(OV)Vss
APPLICATION
•
I/O
PORT B
READ INPUT
Extension of I/O ports and timer function for MELPS
_
Outline_
40P1
8/85 and ME LPS 8-48 devices
L . . . . . - - -_
FUNCTION
The M5L8156P is composed of RAM, I/O ports and
as control terminals for the 8-bit ports, so that the 8-bit
counter/timer. The RAM is a 2K-bit static RAM organized
ports can be operated in a handshake mode. The counter/
as 256 words by 8 bits. The I/O ports consist of 2 program-
timer is composed of 14 bits that can be used to count
mable 8-bit ports and 1 programmable 6-bit port. The
down (events or time) and it can generate square wave
pulses that can be used for counting and timing.
terminals of the 6-bit port can be programmed to function
BLOCK DIAGRAM(5V) Vee
(OV) Vss
r-40
PA 7
zo
PA6
!
STATIC RAM
I/O
PORT A
(256 WORDS x 8 BITS)
DATA BUS
BUFFER
BIDIRECTIONAL
ADDRESS/DATA BUS
8-BIT INTERNAL
DATA BUS
I/O
PORT B
RESET INPUT RESET 4
MEMORY SELECT INPUT
CHIP ENABLE INPUT
READ INPUT
WRITE INPUT
101M 7
READ/
WRITE
CONTROL
CIRCUIT
:~!l
5 PC
3
PC z
ADDRESS LATCH
ENABLE INPUT
I/O
PORT C
PC,
PC o
~-------d>---4------------,
TIMER IN
TIMER INPUT
TIMER OUT
TIMER OUTPUT
• MITSUBISHI
"'ELECTRIC
7-33
MITSUBISHI LSls
M5L8156P
2048-BIT STATIC RAM WITH I/O PORTS AND TIMER
OPERATION
Data Bus Buffer
This 3-state bidirectional 8-bit buffer is used to transfer the
data while input or output instructions are being executed
by the CPU. Command and address information is also
transferred through the data bus buffer.
ReadIWrite Control Logic
The read/write control logic controls the transfer of data by
interpreting I/O control bus output signals (RD, WR, 10/M
and ALE) along with CPU signal (CE). RESET signal is also
used to control the transfer of data and commands.
Bidirectional Address/Data Bus (ADo '" AD7 )
The bidirectional address/data bus is a 3-state 8-bit bus. The
8-bit address is latched in the internal latch by the falling
edge of ALE. Then if 10/M input signal is at high-level, the
address of liD port, counter/timer, or command register is
selected. If it is at low-level, memory address is selected.
The 8-bit address data is transferred by read input (AD)
or write input (WR).
Chip Enable Input (CE)
When CE is at high-level, the address information on
address/data bus is stored in the M5L8156P.
Read Input (RD)
When RD is at low-level the data bus buffer is active. If
10/M input signal is at low-level, the contents of RAM are
read through the address/data bus. If 10/M input is at highlevel, the selected contents of I/O port or counter/timer are
read through the address/data bus.
Write Input (WR)
When WR is at low-level, the data on the address/data bus
are written into RAM if 10/M is at low-level, or if 10/M is
at high-level they are written into I/O port, counter/timer
or command register.
Address Latch Enable Input (ALE)
An address on the address/data bus along with the levels
of CE and 101M are latched in the M5L8156P on the falling
edge of ALE.
10/Memory Input (lO/M)
When 10/M is at low-level, the RAM is selected, while at
high-level the I/O port, counter/timer or command register
are selected.
I/O Port A (PAo '" PAl)
Port A is an 8-bit general-purpose I/O port. Input/output
setting is controlled by the system software.
I/O Port B (PBo '" PB 7 )
Port B is an 8-bit general-purpose I/O port. Input/output
setting is controlled by the system software.
I/O Port C (PCo '" PCs )
Port C is a 6-bit I/O port that can also be used to output
control signals of port A (PA) or port B (PB). The functions
of port C are controlled by the system software. When port
7-34
C is used to output control signals of ports A or B the assigment of the signals to the pins is as shown in Table 1.
Table 1 Pin assignment of control signals of port C
Pin
Function
(port B strobe)
PCs
B STB
PC4
B BF
(port B buffer full)
PC3
B INTR
(port B interrupt)
PC2
A STB
(port A strobe)
PCl
A BF
(port A buffer full)
PCa
A INTR
(port A interrupt)
Timer Input (TIMER IN)
The signal at this input terminal is used by the counter/
timer for counting events or time. (3MHz max.)
Timer Output (TIMER OUT)
A square wave signal or pulse from the counter/timer is
output through this pin when in the operation mode.
Command Register (8 bits)
The command register is an 8·bit latched register. The loworder 4 bits (bits 0'" 3) are used for controlling and determination of the mode of the ports. Bits 4 and 5 are used as
interrupt enable flags for ports A and B when port C is used
as a control port. Bits 6 and 7 are used for controlling the
counter/timer. The contents of the command register are
rewritten by output instructions (address I/O XXXXXOOO).
Details of the functions of the individual bits of the
command register are shown in Fig. 1.
7
6
5
3
4
2
I
1
Ir™2 TMlllEB ]IEA PC2 PCll PB
0
I PA J
LpORT A
I/O FLAG
1: OUTPUT PORT A
0: INPUT PORT A
'---PORT B I/O FLAG
1: OUTPUT PORT B
0: INPUT PORT B
PORT C FLAG
00:
11:
01:
10:
ALTl
ALT2
ALT3
AL T4
PORT A INTERRUPT
ENABLE FLAG
1: ENABLE INTERRUPT
O:DISABLE INTERRUPT
PORT B INTERRUPT
ENABLE FLAG
1: ENABLE INTERRUPT
O:DISABLE INTERRUPT
COUNTER/TIMER CONTROL
00: NO INFLUENCE ON COUNTER/TIMER OPERATION
01: COUNTER/TIMER OPERATION DISCONTINUED (IF NOT
t~~Mr~I1S~O:~Eg~ERATION
DISCONTINUED AFTER THE
CURRENT COUNTER/TIMER OPERATION IS COMPLETED.
11: COUNTER/TIMER OPERATION STARTED
10:
Fig. 1 Bit functions of the command register
• MITSUBISHI
..... ELECTRIC
MITSUBISHI LSls
MSL81S6P
2048-BIT STATIC RAM WITH I/O PORTS AND TIMER
Status Register (7 bits)
The status register is a 7-bit latched register. The loworder 5 bits (bits 0'" 4) are u5ed as status flags for the I/O
ports. Bit 6 is as a status flag for the counter/timer. The
contents of the status register are transferred into the CPU
by reading (INPUT instruction, address I/O XXXXXOOO).
Details of the functions of the individual bits of the status
register are shown in Fig. 2.
" - - - - - PORT A INTERRUPT REQUEST
L--_ _ _ _ _
PORT A BUFFER FULL FLAG
' - - - - - - - - - - PORT A INTERRUPT ENABLE
L--_ _ _ _ _ _ _ _ _ _ _
PORT B INTERRUPT REQUEST
' - - - - - - - - - - - - - - - - PORT B BUFFER FULL FLAG
' - - - - - - - - - - - - - - - - - - - PORT B INTERRUPT ENABLE
' - - - - - - - - - - - - - - - - - - - - - - COUNTER/TIMER INTERRUPT (SET TO
OF THE
AND IS
STATUS
1 WHEN THE FINAL LIMIT
COUNTER/TIMER IS REACHED
RESET TO 0 WHEN THE
IS READ)
Fig.2 Bit functions of the status register
I/O Ports
Command/status registers (8 bits/7 bits)
These registers are assigned address XXXXXOOO. When executing an OUTPUT instruction, the contents of the command register are rewritten. When executing an INPUT
instruction the contents of the status register are read.
Port A Register (8 bits)
Port A register is assigned address XXXXX001. This register
can be programmed as an input or output by setting the
appropriate bits of the command register as shown in Fig. 1.
Port A can be operated in basic or strobe made and is
assigned I/O terminal PAo '" PA 7 .
Port B Register (8 bits)
Port B register is assigned address XXXXX010. As with
Port A register, this register can be programmed as an input
or output by setting the appropriate bits of the command
register as shown in Fig. 1. Port B can be operated in basic
or strobe mode and is assigned I/O terminals PB o '" PB 7 •
Port C Register (6 bits)
Port C register is assigned address XXXXXOll. This port is
used for controlling input/output operations of ports A and
B by selectively setting bits 2 and 3 of the command
register as shown in Fig. 1. Details of the functions of the
various setting of bits 2 and 3 are shown in Table 2. Port C
is assigned I/O terminals PCo"""PC s and when used as port
control signals, the 3 low-order bits are assigned for port A
while the 3 high-order bits are assigned for port B.
Table 2 Functions of port C
State
Terminal
ALTl
AL T2
PCs
Input
Output
PC4
Input
PC3
Input
PCz
Input
PCl
Input
PCo
Input
Outrul
AL T 3
AL T 4
Output
S STS
Output
Output
S SF
Output
Output
S INTR (port B interrupt)
Output
A STS (port A strobe)
A STS
Output
A SF (port A buffer full)
A SF
A INTR (port A interrupt)
A INTR (port A interrupt)
• MITSUBISHI
..... ELECTRIC
(port B strobe)
(port B buffer full)
(port A strobe)
(port A buffer full)
7-35
II
MITSUBISHI LSls
MSL8156P
2048-BIT STATIC RAM WITH I/O PORTS AND TIMER
Configuration of Ports
A block diagram of 1 bit of ports A and B is shown in
Fig. 3. While port A or B is programmed as an output port,
if the port is addressed by an input instruction, the contents of the selected port can be read. When a port is put in
input mode, the output latch is cleared and writing into the
output latch is disabled. Therefore when a port is changed
to output mode from input mode, low-level signals are
output through the port. When a reset signal is applied, all
3 ports (PA, PB, and PC) will be input ports and their
output latches are cleared. Port C has the same configuration as ports A and B in modes AL T1 and AL T2.
The basic functions of the I/O ports are shown in Table 3.
The control signal levels to ports A and B, when port C is
programmed as a control port, are shown in Table 4.
Table 3 Basic functions of I/O ports
Address
RD
WR
0
1
AD bus .... status register
Function
Command register .... AD bus
XXXXXOOO
1
0
0
1
AD bus .... port A
1
0
Port A .... AD bus
XXXXXOOl
0
1
AD bus .... port B
1
0
Port B .... AD bus
XXXXX010
0
1
AD bus .... port C
1
0
Port C .... AD bus
XXXXXOll
Table 4 Port control signal levels at AL T3 and AL T4
Input mode
Output mode
"L"
INTR
"L"
"L"
STS
Input
Input
Control signal
SF
PA/PB
PIN
MD
"H"
Counter/Timer
RD PORT
1.
*1
*2
*3
STB
OUTPUT MODE
INPUT MODE
}
MULTIPLEX CONTROL
STROBE INPUT MODE
2. MD = 1 : OUTPUT MODE
o:
INPUT MODE
3. RD PORT=IO/M·RD·CE·
(PORT ADDRESS SELECTED)
4. WR PORT=IO/M·WR·CE·
(PORT ADDRESS SELECTED)
Fig. 3 Configuration for 1 bit of port A or B
7-36
The counter/timer is a 14-bit counting register plus 2 mode
flags. The register has two sections: address I/O XXXXX100
is assigned to the low-order 8 bits and address I/O
XXX XX 101 is assigned to the high-order 8 bits. The loworder bits 0'" 13 are used for counting or timing. The
counter is initialized by the program and then counted
down to zero. The initial setting can range from 2 16 to
3F F 16. Bits 14 and 15 are used as mode flags.
The mode flags select 1 of 4 modes with functions as
follow:
Mode 0: Outputs high-level signal during the former
half of the counter operation
Outputs low-level signal during the latter half
of the counter operation
Mode 1: Outputs square wave signals as in mode 0
Mode 2: Outputs a low-level pulse during the final
count down
Mode 3: Outputs a low-level pulse during each final
count down
Starting and stopping the counter/timer is controlled by
bits 6 and 7 of the command register (see Fig. 1 for
details). The format and timer modes of the counter/timer
register are shown in Fig. 4 and Table 5.
• MITSUBISHI
.... ELECTRIC
MITSUBISHI LSls
M5L8156P
2048-BIT STATIC RAM WITH I/O PORTS AND TIMER
I
M2
I
M1
I
T 13
I
T7
I
T6
I
T11
I
TlO
I
T9
I
Ts
I
I
To
I
THE HIGH-ORDER 6 BITS
OF THE COUNTER REGISTER
TIMER MODE
I
T12
The counter/timer is not influenced by a reset, but counting is discontinued. To resume counting, a start command
must be written into the command register as shown in
Fig. 1. While operating 2n+1 count down in mode 0, a highlevel signal is output during the n+1 counting and a lowlevel signal is output during the n counting.
I
T5
I
T4
I
T3
I
T2
I
T1
THE LOW-ORDER 8 BITS OF THE COUNTER REGISTER
Fig.4 Format of counter/timer
Table 5 Timer mode
M2
M1
Timer operation
Outputs high-level signal during the former half of the counter
operation
Outputs low-level signal during the latter half of the counter
t-_ _+-_ _+operation
(mode 0)
Outputs square wave signals as in mode 0
(mode 1)
Outputs a low-level pulse during the final count down
(mode 2)
Outputs a low-level pulse during each final count down
(mode 3)
II
ABSOLUTE MAXIMUM RATINGS
Symbol
Vee
Parameter
Conditions
Input voltage
With respect to Vss
Vo
Output voltage
Pd
Maximum power dissipation
Topr
Operating free-air temperature range
Tstg
Storage temperature range
Unit
Limits
Supply voltage
-0_5-7
V
- 0 _5-7
V
-0_5-7
V
1.5
W
0-70
"C
"C
-65-150
RECOMMENDED OPERATING CONDITIONS
(Ta=0-70"C, unlessotherwisenoted)
Limits
Symbol
Parameter
Unit
Min
Vee
Supply voltage
Vss
Power-supply voltage
4 _75
VIL
Low-level input voltage
-0.5
VIH
High-level input voltage
2
Nom
Max
5
5.25
0
ELECTRICAL CHARACTERISTICS
V
V
0.8
V
Vee +0.5
V
(Ta=0-70"C, Vee=5V+5%, unless otherwise noted)
Limits
Symbol
Test conditions
Parameter
Unit
Min
Typ
Max
VOH
High-level output voltage
VSS=OV, 10H- -400.u A
VOL
Low-level output voltage
VSS=OV, 10L = 2mA
II
Input leak current
Vss=OV, VI~O-Vee
-10
10
.u A
II (eE)
I nput leak current, CE pin
VSS=OV, VI=O-Vee
-100
100
I-J.A
loz
Output float ing leak current
VSS=OV, VI=0.45-Vee
-10
10
I-J.A
Oi
Input capacitance
VIL=OV, f= 1 MHz ,25mVrms, Ta = 25"C
10
pF
Oi/o
Input/output terminal capacitance
VI/OL=OV, f=lMHz,25mVrms, Ta=25"C
20
pF
ICC
Supply current from Vee
180
mA
Vss=OV
V
2.4
0.45
V
Note 5 Current flowing into an IC is positive, out is negative.
• MITSUBISHI
"'ELECTRIC
7-37
MITSUBISHI LSls
M5L8156P
2048-BIT STATIC RAM WITH I/O PORTS AND TIMER
TIMING REQUIREMENTS (Ta=0-70'C,
Vee=5V
unless otherwise noted)
Alternative
symbol
Parameter
Symbol
+ 5%,
Limits
Unit
Test cond it ions
Min
Typ
Max
tsu (A-L)
Address setup time before latch
tAL
50
ns
th (L-A)
Address hold time after latch
tLA
80
ns
th(L-RWH)
Read/write hold time after latch
tLe
100
ns
tW(L)
Latch pulse width
tLL
100
ns
th (RW-L)
Latch hold time after read/write
teL
20
ns
tW(RWL)
Read/write low-level pulse width
tee
250
ns
tsu (D-W)
Data setup time before write
tow
150
ns
th (W-D)
Data hold time after write
two
0
ns
tW(RWH)
Read/write high-level pulse width
tRV
300
ns
tsu (P-R)
Port setup time before read
tpR
70
ns
th (R-P)
Port hold time after read
tRP
50
ns
tW(STB)
Strobe pulse width
tss
200
ns
tsu (P-STB)
Port setup time before strobe
tpss
50
ns
th (STB-P)
Port hold time after strobe
tpHS
120
ns
tW(¢H)
Timer input high-level pulse width
t 2
120
ns
tW(¢L)
Timer input low-level pulse width
t 1
80
ns
to (¢)
Timer input cycle time
teye
tr (¢)
Timer input rise time
tr
30
ns
t1 (¢)
Timer input fall time
tf
30
ns
SWITCHING CHARACTERISTICS
Symbol
320
ns
(Ta=0-70'C, Vee=5V±5%, unlessotherwisenoted.)
AI tern at ive
symbol
Parameter
Limits
Unit
Test conditions
Min
Typ
Max
ns
tPZX(R-Q)
Propagation time from read to data output
tRD
170
tPZX(A-Q)
Propagation ti me from address to data output
tAD
400
ns
tPVZ(R-Q)
Propagation time from read to data floating (Note 7)
tRDF
100
ns
400
ns
tPHUW-P)
twp
Propagation time from write to data output
tPLH(W-P)
twp
tpLH(STB-BF)
Propagation time from strobe to BF flag
tSBF
400
ns
tpHL(R-BF)
Propagation time from read to BF flag
tRBE
400
ns
tPLH(STB-INTR)
Propagation time from strobe to interrupt
tSI
400
ns
tPHL(R-INTR)
Propagation time from read to interrupt
tRDI
400
ns
tPHL(STB-BF)
Propagation time from strobe to BF flag
tSBE
400
ns
tPLH(W-BF)
Propagation time from write to BF flag
tWBF
400
ns
tPHL(W-INTR)
Propagation time from write to interrupt
tWI
400
ns
400
ns
tPHL(¢-OUT)
tTL
Propagation time from timer input to timer output
tpLH(¢-OUT)
tTH
Note 6: Measurement conditions C = 150pF
7: Measurement conditions of note 6 are not applied.
•
7-38
MITSUBISHI
.... ELECTRIC
MITSUBISHI LSls
MSL81S6P
2048-BIT STATIC RAM WITH I/O PORTS AND TIMER
TIM I NG D I AG RAM
(reference level, high-level=2V, low-level=O.8V)
Basic Input
CE
IO/M
/r
\~
~K
/
J(
~
tPZX(A-Q)
ADo-A 07
)~
tsu (A-L)
ALE
E
lr-
ADDRESS
, .....
~
2~
th (L-A)
DATA
tPVZ(A-Q)
r-----
~f':I
-'Ittw (L)
H=
th (L-AWH)
{
tpZX(A-Q)
-'~~
Y
tw (AWL)
tsu (P-A)
J
~t\-
fth (AW-L)
tw (AWH)
th (A-P)
l"-
II
J(
):
PORT
Basic Output
;r-
-'\.
/
101M
\~
V
\
ADo-A 07
):
CE
-'K
ADDRESS
~r
-'1\-
ALE
J(
th(AW-L)
tsu (D-W)
th (L-A)
tsu (A-L)
DATA
'-'r-
-j;
tw (L)
th (L-AWH)
th (W-D)
_I
II. . .
I
tW(AWI.-)
L
tW(AWH)
tPHL(W-P)
tPLH(W-P)
X
PORT
I
• MITSUBISHI
.... ELECTRIC
7-39
MITSUBISHI LSls
MSL81S6P
2048-BIT STATIC RAM WITH I/O PORTS AND TIMER
Strobed Input
BF
INTR
tsu (P-STB)
th (STB-P)
PORT
Strobed Output
BF
INTR
PORT
Timer
(Note 81
TIMER IN
TIMER OUT
PULSE MODE
TIMER OUT
SQUARE WAVE MODE
I
__ ~ ________ .J (Note 91
Note 8: The wave form is shown counting down from 5 to 1.
9: As long as the M1 mode flag of the timer register
is at high-level, pulses are continuously output.
7-40
• MITSUBISHI
;"'ELECTRIC
LSls FOR PERIPHERAL CIRCUITS
MITSUBISHI LSls
MS8990P
8-BIT 8-CHANNEL A-D CONVERTER
DESCRIPTION
PIN CONFIGURATION (TOP VIEW)
The M58990P A-D converter is used to convert analog
signals to 8-bit digital values. The A-D converter is fabricated using silicon-gates and CMOS technology. The
M58990P can selectively multiplex 8 channels of analog
input.
FEATURES
• Single 5V power supply
• Conversion resolution of 8 bits
• Multiplex 8 channels of analog input
•
Broad range of analog input voltages: OV '"'-' Vee
Conversion time: 100J,Ls
Conversion by successive approximation
Can be used online through the data bus of a microprocessor
• The 1/0 pins can be connected directly to TTL circuits
• Interchangeable with NS's ADC0808 (in pin configuration)
•
•
•
APPLICATION
•
Used with microcomputers to control analog systems
Outline 28P 4
FUNCTION
The M58990P has eight analog input terminals that are
selected by the input signals to the 3 address terminals
(ADD A'"'-' ADD C). The address signals of these terminals
are read and latched in the internal address latches by the
ALE signal. When the OE terminal is at low-level, the output terminals 2-1 '"'-' 2-8 are in a floating state so they can
be connected directly to the data bus of a microcomputer.
BLOCK DIAGRAM
The input terminal START is used to call for the start of
an analog to digital conversion and a signal is output
through terminal EOC when the conversion is completed.
START
CONVERSION
INPUT
START
-----------IN 0
@r-~---'
IN1
IN 2
(28)------i.-l
CLOCK INPUT
CLK
----------~6
END OF
CONVERSION
OUTPUT
IN 3
IN 4
ANALOG INPUT
IN 5
IN 6
IN 7
DIGITAL OUTPUT
ADD A
ADDRESS INPUT
ADD
{
B 24
4
ADD C 2
...:=j>
ADDRESS LATCH ALE
ENABLE INPUT
~-----
---------------~12
REF(+)
REFERENCE ( +)
VOLTAGE
16
REF(-)
REFERENCE ( - )
VOLTAGE
• MITSUBISHI
.... ELECTRIC
VCC (5V)
GND (0 V)
OE
OUTPUT ENABLE INPUT
8-3
II
:
MITSUBISHI LSls
M58990P
8-BIT 8-CHANNEL A-D CONVERTER
PIN DESCRIPTIONS
Pin
Input or
Output
Name
INo
Functions
Analog signal
Input
These are analog signal input pins. Which of the 8 inputs is selected, is determined by ADD A - ADD C. An analog voltage
applied at the selected pin is converted to a digital value in the range of 2-1 - 2-8 and output.
Address signal
Input
The input is used for selecting which of the 8 terminals INo - IN, is to be converted from analog to digital. The address
input through ADD A - ADD C is read to the address latch by the riseing edge of ALE.
ALE
Address latch
enable signal
Input
REF(+)
Reference voltage (
+)
Input
This is one of the input terminals for the reference voltage that is applied to the 256R resistor ladder circuit. The other
terminal is REF (-) and the voltage levels of these two inputs must meet the condition: REF (+) > REF (-).
REF(-)
Reference voltage ( - )
Input
This is one of the input terminals for the reference voltage that is applied to the 256R resistor ladder circuit. The other
terminal is REF (+) and the voltage levels of these two inputs must meet the condition: REF (+) > REF (-).
OE
Output enable signal
Input
\
IN7
ADD A
\
ADD 0
2- 1
This is the strobe signal which causes the address signal input through ADD A - ADD C to be read and latched for use as
an internal address.
The signal at this pin controls the digital output. When the signal is low-level, pins 2-1
-
2-8 are in a floating state. When
it is high-level, the data is output.
Digital signal
Output
The analog signal, which was input through INo - IN" is converted to digital data and is output from these terminals.
When OE is low-level, these terminals are floating. When OE is high-level, the converted digital data is output. The MSB
is 2-1 and the LSB is 2-8.
EOO
End of conversion signal
Output
This terminals is used to indicate the completion of an analog to digital conversion. It is reset by a START signal (highlevel to low-level) and is set on completion of the conversion (low-level to high-level). This output is normally used to
generate an interrupt request for the CPU.
START
Start conversion signal
Input
The input signal at this terminal is used to start a conversion cycle by setting the successive approximation register. The
successive approximation register is reset by rising from low-level to high-level and conversion is started after being set by
OLK
Clock input
Input
The signal at this terminal is the basic clocking signal used to determine internal timing.
\
2- 8
falling from high-level to low-level.
8-4
• MITSUBISHI
.... ELECTRIC
MITSUBISHI LSls
MS8990P
8-BIT 8-CHANNEL A-D CONVERTER
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Vee
Supply voltage
VI
I nput voltage
Vo
Output voltage
Pd
Maximum power dissipation
Conditions
With respect to GND
Topr
Operating free-air temperature range
T stg
Storage temperature range
Limits
Unit
-0.3-7
V
-0. 3-V cc +0. 3
V
Ta=25"C
o -Vee
V
500
mW
0-70
"C
-65-150
"C
R ECOMM END EDOPE RA TI N G CON D I T IONS (Ta = 0 -70°C, unless otherwise noted)
Limits
Symbol
Parameter
Unit
Min
Nom
Vee
Supply voltage
GND
Supply voltage
VIH
High·level input voltage
2
-0.3
4.75
VIL
Low-level input voltage
Max of reference voltage (+)
VREF(-)
Min of reference voltage H
L:,.VREF
Defferential of reference voltage
VI (IN)
Analog input voltage
Vee
-0.1
5.25
V
Vee
V
0.8
V
High-level input voltage
Vee+O.l
V
V
5.12
5.25
V
VREF(+)
V
(Ta=0-70°C, Vee=5V ±5%, unless otherwise noted)
Limits
Alternative
symbol
Parameter
V
0
0
ELECTRICAL CHARACTERISTICS
VIH
5
0
VREF( +)
Symbol
Max
Test conditjons
Min
Typ
Unit
Max
2
VINI'I
V
Vee= 5 V
0.8
V
IOL = 1.6mA
0.45
V
VIL
Low-level input voltage
VINIOI
VOH
High-level output voltage
VOUTI'I
IOH=-360,uA, Ta=70"C
VOUT 101
VOL
Low-level output voltage,
r 1_ r 8output
V
Vee-0.4
VOL(EOe)
Low-level output voltage, EOC output
VOUT 101
IOL= 1.2mA
0.45
V
IIH
High·level input current
IIN(l)
VIH =5 .25V
1.0
,uA
Low-level input current
IIN(O)
VIL = 0 V
lOUT
VO= 5 V
IlL
IOZH
IOZL
Icc
Off-state (high-impedance state)
output current, 2 -, - r8 output
Off-state (Low·impedance state)
current current, r 1- r8 ou~ut
Vo= 0 V
lOUT
f (
?
APPLICATION EXAMPLE
One example of interfacing a M5C6847P-1 with a television
set for horne use is shown in Fig. 2. A M5L8085AP is used
as the CPU in the example shown. The CPU executes the
programs to control display and write the information for
one screen into display memory. The M5C6847P-1 performs the main functions of interfacing with the CRT such
as synchronizing scan, reading the display information from
the display memory while adding necessary synchronization
signals and sending to the R F modulator.
Fig. 2 Application example using the M5C6847P-1
• MITSUBISHI
..... ELECTRIC
R-ll
II
:
MITSUBISHI LSls
MSC6847p·l
VIDEO DISPLAY GENERATOR
A schematic for using the MSC6847P-1 with the
MS1342P RF modulator is shown in Fig. 3. MS1342 requires ±SV power supplies. The video signal and chroma
signal from the MSC6847P-1 can be modulated with the
sound signal to form a RF signal that appears the same as
the television antenna input signal. The video amp circuit to
enable direct connection to a MSC6847P-1 is shown in Fig.
4. This can be connected to the monochrome video monitor. In this case, the inpedance is 7SQ.
Four levels of brightness (black, low, medium and high)
can display a clear picture.
16 14 15
p
±:_ 47p
47 P
1k
CPU
CLK
0
__
M51342P
~[])>->_ I
, ,
75
~--~L~>~O~[])~~~~~~__ .~
0.0 1,u
12 3 4 2
,-10"1-1_1-------+----+-----{5} R F
0.01,u
---~
OUT
-..,--OC:A--<
1M
289 1011
33
I----------;~
CL K
YCHB¢s¢A
FS 37
M5C6847P-1
AS 38
RP 36
-----~MS
Ll
L2
L3
91.25MHz (FOR CHlI ........ ·M 10H(1661) MITSUtvil MADE
97.25MHz (FOR CH2) ........ ·M10H(1662) MITSUMI MADE
450MHz (FOR SOUND) ........ · M 10H( 1660) MITSUMI MADE
Fig. 3 Schematic for using the M51342P (RF modulator) with the M5C6847P-1
~ ~~;~~6~~~ ~-n----+----l
(28 PINS)
Fig. 4 Video amp circuit
8--12
• MITSUBISHI
.... ELECTRIC
MITSUBISHI LSls
MSC6847P-l
VIDEO DISPLAY GENERATOR
Data and Display Relation
The relation between data and 5 display modes is shown in
Table 6.
Table 6 Data and display relation
Mode
Data
07
I
Os
06
04
Display
03
02
01
5 dots
00
"';'h"'II ~po"
~&@@~
I
Character
6-bit ASCII
I
I
Width 8 dots
1------1
07
Semigraphic 4
I
05
06
I
I
04
03
07
Semigraphic 6
Os
06
I
'--y-----'
07
Color-graphic (4 colors)
02
03
02
01
00
I
04
I
03
I
02
I
01
03
~
Graphic (2 colors)
I
I
I
Os
I
04
I
03
I
02
Display element
Di~lay element
I
I
l
1
Color
Color
Color
Color
designation designation designation designation
"
I
06
02
ro; ~
00
~~'---v-----''------.
0 7
00
'---L.....:..
01
I
Display element
t-- I--
Display element
ON/OFF indication
Os
03
r-r--
~~~~~~
06
I
m--
00
Display element
ON/OFF indication
04
Color designation
I
01
~
I
Color designation
I
02
01
I
1
i
00
I I I I
~-----------~----
Display element ON/OFF indication
• MITSUBISHI
"ELECTRIC
r--------
.l.
i
I I I
l 1 1
-- -
_J
I
P
Display
~element
~
8-13
II
MITSUBISHI LSls
MSC6847p·l
VIDEO DISPLAY GENERATOR
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Vee
Supply voltage
VI
Input voltage
Vo
Output voltage
Pd
Power dissipation
Topr
Operating free-air temperature range
Tstg
Storage temperature range
Limits
Conditions
With respect to
vss
Unit
-0.3-7
V
-0.3-7
V
-0.3-7
Ta=25·C
V
1000
mW
·C
0-70
·C
- 65-150
RECOMMENDED OPERATING CONDITIONS
(Ta=0-70·C, unless otherwise noted)
Limits
Symbol
Parameter
Vee
Supply voltage
VSS
Supply voltage
Unit
Min
Nom
Max
4.75
5
5.25
0
VIH(¢)
High·level input voltage, clock
VIH
High·level input voltage
VIL(¢)
VIL
V
V
2.4
Vee
V
2
Vee
V
Low-level input voltage, clock
-0.3
0.4
V
Low·level input voltage
-0.3
O.S
V
ELECTRICAL CHARACTERISTICS
(Ta=O-7Q"C, Vee=5V ±5%, unless otherwise noted)
Limits
Symbol
Test conditions
Parameter
Unit
Min
Typ
Max
VOL
High-level output voltage, except for B chrominance burst-level output voltage
V¢B.L
¢> B chrominance low-level output voltage
VYSYNC
Luminance sync output voltage
VYBLANK
Luminance blank output voltage
VYBLACK
Luminance black output voltage
VYW(H)
White luminance high-level output voltage
VYW(M)
VCHB
VCHB
VSS=OV, OL=20pF, RL=200kQ
V
VCHB0. 16Vec
V
0.74VcC
V
VYSYNe
O.Sl
VYSYNe
0.62
VYSYNe
0.69
VYSYNe
VYW(L)
8-14
0.77
White luminance low-level output voltage
VYSYNe
• MITSUBISHI
"'ELECTRIC
V
VCHBO.OSVce
0.85
White luminance medium-level output voltage
V
V
V
V
V
V
MITSUBISHI LSls
MSC6847P-l
VIDEO DISPLAY GENERATOR
TIMING REQUIREMENTS
(Ta=0-70·C. Vcc=5V±5%. VSs=OV.
unless otherwise noted)
Limits
Symbol
Parameter
Unit
Test conditions
Min
fc (A)
¢ A chrominance output rise time
60
ns
tf (¢A)
¢ A chrominance output fall time
60
ns
tr (B)
¢B chrominance output rise time
60
ns
tf (¢B)
¢ B chrominance output fall time
60
ns
tPHL(SYNC-BURST)
¢B chrominance output propagation time after
luminance syncronization signal output
980
ns
tw (BURST)
¢ B chrominance output burst signal pulse width
2.93
I-LS
tr (BURST)
¢B chrominance output burst signal rise time
60
ns
tf (BURST)
¢B chrominance output burst signal tall time
60
ns
tpHL (Y-CH)
Chrominance propagation time after luminance
output
0
ns
tpLH (Y-CH)
II
MISCELLANEOUS
Limits
Parameter
Symbol
Unit
Test conditions
Min
Typ
Max
tw(FS)
Field syncronization pulse width
2.03
ms
tW(RP)
Row preset pulse width
980
ns
tpHL (HS-RP)
RP propagation time after HS
980
ns
tW(HS)
Horizontal syncronization pulse width
4.9
I-LS
1. 12
I-LS
140
ns
tW(CH)
Character width
tw (DOT)
Dot width
• MITSUBISHI
..... ELECTRIC
8-15
MITSUBISHI LSls
MSC6847P-l
VIDEO DISPLAY GENERATOR
TIMING DIAGRAM
Display memory access
CLK
07 -Do
CSS, A/S,
A/G,INV,
INT IEXT
INTERNAL DATA
LATCH
INTERNAL DOT
COUNT
1 WORD
~------------------~~------------------~CHARACTERMODE
DISPLAY ELEMENT (LEFT SIDEI
DISPLAY ELEMENT (RIGHT SIDE)
k-------------------~_------------------~ SEM IGRAPH IC MODE
Composite video and chroma
- - - VYBLANK
- - - - - - - - VYBLACK
y
- - - - - - - - VYWL
- - - - - - - - VYWM
- - - - - - - - VYWH
- - - - - V¢>BH
r--......- - - - - - - V ¢>BM
CPB
- - - - - V¢>BB
- - - - - V¢>BL
tw (BURST)
- - - - - V¢>AH
1\--.--------
CPA
V ¢>AM
- - - - - V¢>AL
[i,
DISPLAY
ACTIVE DISPLAY AREA
35. 76f..ls
HORIZONTAL SCAN TIME
IJ
63.57 f..lS
Miscellaneous timing
t
tweFS)
1
twCHS)
tPHL(HS-RP)
tweRP)
8 . 16
• MITSUBISHI
;"'ELECTRIC
;;.
MITSUBISHI LSls
MSL 8041A-XXXP
UNIVERSAL PERIPHERAL INTERFACE
DESCRIPTION
The M5L8041 A-XXXP is a general-purpose, programmable
interface device deisgned for use with a variety of 8-bit
microcomputer systems. This device is fabricated using
N-channel silicon-gate ED-MOS technology.
PIN CONFIGURATION (TOP VIEW)
Vee
TEST PIN 0
CLOCK 1
TEST PIN 1
CLOCK 2
RESET
INPUT/
OUTPUT
PORT 2
SINGLE STEP
FEATURES
•
•
Mask ROM: .................... 1024-word by 8-bit
Static RAM: ................... 64-word by 8-bit
•
•
18 programmable I/O pins
Asynchronous data register for interface to master
processor
• 8-bit CPU, ROM, RAM, I/O, timer, clock and low power
standby mode
• Single 5V supply
• Alternative to custom LSI
• Interchangeable with Intel's 8041A in function, electrical characteristics and pin configuration
S -+ 6
CHIP SE LECT
EXTERNAL
EA -+ 7
ACCESS (NOTE1)
READ
R-+ 8
ADDRESS
Ao-+ 9
WRITE
W-+ 10
SYNCHRONIZED
SIGNAL SYNC- 11
INPUT/
OUTPUT
PORT 1
(5V)
DATA BUS
EXTERNAL
I/O
CONTROL
INPUT/
OUTPUT
PORT 2
(OV)
APPLICATION
•
(5V)
Vss
Package Outline 40P1
Alternative to custom LSI for peripheral interface
Note 1: Connect to Vss in the
operating condition.
FUNCTION
The M5L8041 A-XXXP contains a small stand-alone microcomputer.
When it is used as a peripheral controller, it is called the
slave computer in contrast to the master processor. These
two devices can transfer the data alternatively through the
buffer register between them. The M5L8041 A-XXXP contains the buffer register to use this LSI as a slave computer,
and can be accessed the same as other standard peripheral
devices. Because M5L8041A-XXXP is a complete microcomputer, it is easy to develop a user-oriented mask-pro-a
grammed peripheral LSI only by changing control software.
:
BLOCK DIAGRAM
INPUT/OUTPUT PORT 1
RESET
1024x8
SINGLE STEP
ROM
TEST PIN 0
TEST PIN 1
READ
INSTRUCTION REGISTER
WRITE
INSTRUCTION
DECODER
CHIP SELECT
ADDRESS
' - - - - - - - ( 7 EA
EXTERNAL ACCESS
11 - 25
(NOTE 1)
SYNC PROG
EXTERNAL I/O CONTROL
SYNCHRONIZED
SIGNAL
• MITSUBISHI
.... ELECTRIC
8-17
MITSUBISHI LSls
MSL 8041A·XXXP
UNIVERSAL PERIPHERAL INTERFACE
PIN DESCRIPTION
Name
Pin
Function
Input or output
VSS
Ground
-
Connected to a OV supply (ground)
Vee
Main power supply
-
Connected to a 5V supply
VDD
Power supply
-
1 Connected to a 5V supply
2 Used as a memory hold supply when Vee is cut off
PROG
Program
Out
Serves as the strobe signal when an M5L8243P I/O expander is used
PlO- P 17
Port 1
In/out
Ouaisi-bidirectional por.t. When used as an input port, FF'6 must first be output to
this prot.
After resetting, however, when not used afterwards as an output port, this is not
necessary.
P20-P27
Port 2
In/out
1 The same as port 1
2 P20-P23 are used when an M5L8243P I/O port expander is used
DQo-DQ7
Data bus
In/out
To
Test pin 0
In
Provides external control of conditional program jumps (JTO/JNTO instructions).
T,
Test pin 1
In
1 Provides external control of conditional program jumps (JT1/JNTl instructions).
2 Can serve as the input pin for the event counter (STRT CNT instructions!.
S
Chip select input
In
Chip select input for data bus control
R
Read enable signal
In
Serves as the read signal when the master CPU is accepting data on the data bus from
the M5L8041A·XXXP.
W
Write enable signal
In
Serves as the write signal when the master CPU is outputting data from the bus to the
M5L8041 A-XXXP.
RESET
SYNC
Ao
Reset
Sync signal output
In
Out
Address input
In
SS
Single step
In
EA
External access
Serves as a sync signal for read and write operations to and from the bidirectional bus.
Data remains latched.
CPU initialization input
Output 1 time for each machine cycle
An address input used to indicate whether the signal on the data bus is data or a
command
Used to halt the execution of a command by the CPU. When usee! in combination
with the SYNC signal, the command execution of the CPU can be halted every
instruction to enable single step operation.
X,. X2
Crystal inputs
In
Normally maintained at OV
In
An internal clock circuit is provided so that by connecting an RC circuit or crystal to
these input pins the clock frequency can be determined. Pins X, and X 2 can also be
used to input an external clock signal.
8-18
• MITSUBISHI
..... ELECTRIC
MITSUBISHI LSls
MSL 8041A-XXXP
UNIVERSAL PERIPHERAL INTERFACE
BASIC FUNCTION BLOCKS
Program Memory (ROM)
The M5L8041A-XXXP contains 1024 bytes of ROM. The
program for the users application is stored in this ROM.
Addresses 0, 3, 7 of the ROM are reserved for special
functions. Table 1 shows the meaning and function of these
three special addresses.
Addresses 8"'"'23 compose an 8-level program counter
stack. The details for using the stack will be found in the
"Program Counter and Stack" section. Please refer to that
section for details.
Address 0"'"'31 have special functions, but when not all
of the registers are required, the ones not needed can be
used for general storage. This includes both banks of
general-purpose .registers and the stack.
Table 1 Reserved, defined addresses and their
meanings and functions
Address
Meaning and function
The first instruction executed after a system reset.
The first instruction executed after an external interrupt is
accepted.
The first instruction executed after a timer interrupt is accepted.
The ROM can be used to store constants and other 8-bit
fixed data in addition to the program. Instructions such as
MOVPA, @A and MOVP3A, @A can be used to access the
constants and data. The data could be in the form of tables,
and can·be easily looked up.
USER RAM
~
32
31
Data Memory (RAM)
The M5L8041A-XXXP contains 64 bytes of RAM. The
RAM is used for data storage and manipulation and is
divided into sections for more efficient processing. Addresses 0"'"'7 and 24"'"'31 form two banks of general purpose
registers that can be directly addressed. Addresses 0"'"'7
compose bank 0 and are numbered Ro"'"'R7. Addresses
24"'"'31 compose bank 1 and are also numbered Ro "'"'R7.
Only one bank is active at a time. The instructions SEL
RBO and SEL RB1 are used to select the working bank. Fig.
1 shows the division of the RAM and its mapping.
The remaining section, addresses 32 and above, must be
accessed indirectly using the general-purpose registers Ro or
R 1 • Of course all addresses can be indirectly addressed
using the general-purpose registers R 0 and R 1 •
A good practice to simplify programming is to reserve
general-purpose register bank 0 for use of the main program
and register bank 1 for interrupt programs. For example if
register bank 0 (addressed 0"'"'7) is reserved for processing
data by the main program, when an interrupt is accepted
the first instruction would be to switch the working
registers from bank 0 to bank 1. This would save the data
32X8
1
;.
R7
I
I
I
I
I
25
24
Rl
Ro
)
GENERAL-PURPOSE
REGISTERS
REGISTER BANK 1
23
8·LEVEL STACK
16x8
R7
I
I
I
Rl
}
GENERAL-PURPOSE
REGISTERS
REGISTER BANK 0
Ro
Fig. 1 Data memory (RAM)
of the main program (addresses 0"'"'7). The interrupt program
can then freely use register bank 1 (addresses 24"'"'31)
without destroying or altering data of the main program.
When the interrupt processing is complete and control is
returned to the main program by the RETR instruction,
register bank 0 (in this example) is automatically restored
as the working register bank at the same time the main
program counter is restored.
• MITSUBISHI
"ELECTRIC
8-19
MITSUBISHI LSls
MSL 8041A-XXXP
UNIVERSAL PERIPHERAL INTERFACE
Program Counter (PC) and Stack (SK)
The M5L8041 A-XXXP program counter is a lO-bit counter
configured as shown in Fig. 2.
When an interrupt or a subroutine call has occurred, the
program currently being executed is interrupted and the
execution flow must transfer to the interrupt program or
subroutine. When such a condition has been encountered,
the value currently stored in the program counter must be
saved for use when restarting execution of the original
program flow. The storage provided for this saving operation is the program counter stack. The program stack
counter is used to store not only the program counter value
but simultaneously store 4 bits of the PSW (Program Stack
Word). The program counter stack uses addressed 8"'23 of
RAM. Ten bits are required to store the program counter
value while 4 bits are required for the PSW. Therefore, each
save operation uses 2 bytes (16 bits) of RAM. Thus, using
RAM addresses 8"-'23, 8 levels of program counter value
and PSW can be stored on the program stack. This storage
scheme is shown in Fig. 3. To store which program counter
stack location has last been entered, a 3-bit stack pointer is
used. This stack pointer is also part of he PSW. However,
the staGk pointer itself is not stored in the program counter
stack. The stack pointer is automatically incremented by 1
every time the program counter value and PSW are stored
on the program stack. In the reverse operation in which
these values are read from the program stack, the program
stack pointer is decremented by 1. Note that the program
counter stack always indicates the next storage location for
the program counter value. Therefore, when return is made
from a subroutine (using RET or RETR), the stack pointer
is first decremented by1, after which the contents of the
program stack at the location indicated by the stack pointer
are transferred to the program counter.
8-20
Fig. 2 Program counter
RAM REGISTER NUMBER
(DATA MEMORY ADDRESS)
STACK POINTER
S2
S,
1
S0
:
1
R 23
i
0
R22
:
R 21
:
R20
:
R 19
1
T
0
:
;-
R IS
R17
R 16
:
1
R 15
R14
I
;-
0
1
R13
I
R 12
i
Rll
RIO
I
0
PSVI(4)1 PCS-9
R9
PC4-71 PCO-3
Rs
MSB
Fig.3
LSB
Relation between the program counter
stack and the stack pointer
• MITSUBISHI
"'ELECTRIC
MITSUBISHI LSls
MSL 8041A-XXXP
UNIVERSAL PERIPHERAL INTERFACE
PROGRAM STATUS WORD (PSW)
I/O PORTS
The PSW (program status word) is stored in 8 bits of
register storage. The configuration of the PSW is shown in
Fig. 4. The high-order 4 bits of the PSW are stored in the
stack, along with the PC, when an interrupt is accepted or a
subroutine call executed. When control is returned to the
main program by RETR both the PC and the high-order 4
The M5L8041-XXXP has two 8-bit ports, which are called
data bus, port 1 and port 2.
bits of PSW are restored. When control is returned by RET
only the PC is restored, so care must be taken to assure that
the contents of the PSW was not unintentionally changed.
The order and meaning of the 8 bits of the PSW are
shown below.
Bit 0"'2:
Stack pointer (So, Sl, S2)
Bit 3:
Unused (always 1 )
Working register bank indicator
Bit 4:
0= Bank 0 1 = Bank 1
Bit 5:
Flag 0 (Fo) (value is set by the user and can be
tested)
This value can be checked by JFO.
Auxiliary carry (AC) (it is set/reset by instrucBit 6:
tions ADD and ADC and used by instruction
DAA).
Carry bit (C)
execution)
Bit 7:
(indicates an overflow after
Port 1 and Port 2
Ports 1 and 2 are both 8-bit ports with identical properties.
The output data of these ports are retained and do not
change until another output is loaded into them. When used
as inputs the input data is not retained so the input signals
must be maintained until an input instruction is executed
and completed.
Ports 1 and 2 so-called quasi-bidirectional ports have a
special circuit configuration to accomplish this. The special
circuit is shown in Fig. 5. All Pin of ports 1 and 2 can be
used for input or output.
Internal on chip pull-up resistors are provided for all the
ports. Through the use of approximately 50kS1 pull-up
5V
CPU
INTERNAL
BUS
RESET--+---I
ABOUT 50kn
PORT 1
"'-~~_-iPORT 2
TERMINALS
WRITE ---+--_ _....._----1
PULSE
HIGH-ORDER 4 BITS STORED
ALONG WITH THE PC IN THE
I B5 I
1
: CARRY
C
AC : AUXILIARY
CARRY
(CARRY FROM THE
LOW-ORDER 4 BITS OF ALU)
Fa : FLAG 0
B5 : WORKING
52 )
5,
REGISTER
I 52 I 5, I 50
Fig. 5 I/O ports 1 and 2 circuit
Fa
ICY
IAC I
STACK
BANK
STACK POINTER
50
Fig. 4 Program status word
INDICATOR
II
I
resistors, TTL standard high-level or low-level signals can be
supplied. Therefore each Pin can be used for both
input and output. To shorten switching time from low-level
to high-level, when 1s are output, a device of about 5kS1 or
lower is inserted for a short time (about 500ns when using a
6MHz crystal oscillator).
A port used for input must output all 1s before it reads
the data from the input pin. After resetting, a port is
set to an input port and remains in this state, therefore it is
not necessary to output all 1s if it is to be used for input. In
short a port being used for output must output 1s before it
can be used for input.
The individual Pins of quasi-bidirectional ports can
be used for input or output. Therefore some Pins can be
in the input mode while the remaining pins of a port
are in the output mode. This capability of ports 1 and
2 is cOI;1Venient for inputting or outputting 1-bit or data
with few bits. The logical instructions AN L and OR L can
easily be used to manipulate the input or output of these
ports.
• MITSUBISHI
..... ELECTRIC
8-21
MITSUBISHI LSls
MSL 8041A-XXXP
UNIVERSAL PERIPHERAL INTERFACE
(2) Data Bus
The data bus (DOo-DQ7) is used for accepting data,
commands, and statuses, between the master CPU and the
M5L8041A-XXXP. The data bus is controlled by the
following 4 control signals, the relationship between the
control signals and the data bus being shown in table 2.
Ao: Address input indicating data/command, bus buffer
register and status, and register
R: Read input
W:
Write input
S:
Chip select input
STATUS
ST7
STs
S'R'Ao
rv.!Ts.A
STs
~
ST4
1
F1
S·W
Z
-1
Fo
m
IBF
:JJ
Z
~
OBF
OJ
C
(/)
DQo
8
-007-4
S'R'AQ
8
.(
OUTPUT
DATAl
BUS
BUFFER
(DBB(O»
OUT DBB, A
8
~
Table 2 Control Signals and Data Bus Relationships
S
R
W
Ao
0
0
1
0
Read
Data
0
0
1
1
Read
Status
0
1
0
0
Write
Data
Command (Fl<-l)
Data bus data
Data bus status
0
1
0
1
Write
1
X
X
X
High impedance
S·W
8
,
INPUT
DATAl
COMMAND
BUS
BUFFER
(DBB (1)
IN A, DBB
8
-
Fig. 6 shows the internal structure of the data bus. The 3
registers' (status register, output data bus buffer register,
and input data/command bus buffer register) functions are
described below.
Fig. 6 Data bus internal structure
• Status Registers
The status registers consist of 8-bit registers, the upper 4
bits of which (ST 4 -ST 7) being arbitrarily settable by
software (MOVSTS, A instruction). The lower 4 bits (OBF,
IBF, Fo, Fd being set as follows.
OBF (Output Buffer Full)
The OBF flag is automatically set to 1 when the
M5L8041 A-XXXP internally executes an output instruction (OUT DDB, A), upon which the master CPU reads the
contents of the output data bus buffer and clears this flag.
IBF (Input Buffer Full)
The IBF flag is set to 1 when the master CPU causes the
writing of data or a command into the input data/command
bus buffer, whereupon the input instruction (IN A DDB) is
executed by the M5L8041 A-XXXP and this flag is subsequently cleared.
Fo (Flag 0)
The Fo flag is set by the flag setting instructions (CPL Fo,
CLR
Fo) to inform the master CPU 'Of the
M5L8041 A-XXXP internal status.
Fl (Flag 1)
The F 1 flag is set when data or commands are input to the
input data/command bus buffer by the master CPU to
indicate the Ao status.
8-22
• MITSUBISHI
.... ELECTRIC
MITSUBISHI LSls
MSL 8041A-XXXP
UNIVERSAL PERIPHERAL INTERFACE
The
FI
flag may also be set by the flag setting
INTERRUPT
instructions (CPL F I , CLR Fd.
When an external interrupt is encountered by the CPU, the
•
Sand
Output Data Bus Buffer (DBB (0)) Register
The output data bus buffer (DBB (0)) register is loaded
Wpins
are made low. The IBF flag is used to provide
recognition of this interrupt condition.
with the contents of accumulator (A) by means of the OUT
Sampling of interrupt requests is done each machine
DBB, A instruction. Since the OBF flag is set at this time,
cycle during the output of the SYNC signal. When an
the master CPU checks the status of this OBF flag to
interrupt request is recognized, upon the completion of
ascertain whether data has been transferred to the DBB (0)
execution of the present instruction, a subroutine jump is
register.
made to address 3 of program memory. Just as would be
•
the case in a normal subroutine jump, the program counter
Input Data/Command Bus Buffer (DBB (I)) Register
When the master CPU has generated a write request (W=O),
and program status word are saved on the program stack.
the data on the data bus is transferred to the DB B (I)
The program memory address 3 is normally used to store
register. At this time, because the IBF flag is set, the status
an unconditional jump to the address at which is stored the
of the IBF flag is checked internally by the M5L8041A-
interrupt processing program.
XXXP to ascertain whether or not data or commands have
been transferred.
The interrupt level is one, so the next interrupt cannot
be accepted until the current interrupt processing has been
completed. The RETR instruction terminates the interrupt
CONDITIONAL JUMPS USING PINS To, T1
and FLAGS IBF, OBF
accepted until the RETR instruction is executed. The next
Conditional jump instructions are used to alter program
interrupt can be accepted at the start of the second cycle of
processi ng. That is to say, the next interrupt can not be
depending on internal and external conditions (states).
the
Details of the jump instructions can be found in the section
on machine instructions.
counter overflow which causes an interrupt request also will
not be accepted.
The input signal status of To, T I , and flags IBF and
OBF can be checked by the conditional jump instructions.
These input Pin s, through conditional jump instructions
control is returned to the main program. This is a c c o m - a
plished by execuiting RETR which restores the program
:
such as JTO and JNTO, can be used to control a program.
counter and PSW automatical and checks INT and the
Programs and processing time can be reduced by being
time/event counter overflow for an interrupt request. If
able to test data in input Pin rather than reading the data
there is an interrupt request, the control will not be
register and then testing it in the register.
returned to the main program but will be transferred to the
Pin T I has other functions and uses that are not related
to conditional jump instructions. The details
of these
RETR instruction (2-cycle instruction). Time/event
Afte.- the processing for an interrupt is completed
interrupt handling program.
An external interrupt has a higher priority than a timer
other functions and uses can be found in the section on
interrupt.
Pin functions.
interrupt request are generated at the same time, the
This
means that, if an external and timer
external interrupt has the priority and will be accepted
first.
When a second level of external interrupt is required, the
timer interrupt, if not being used, can provide this. The
procedure for this is to first enable the timer interrupt, set
the timer/event counter to FFl6 and put the CPU in the
event counter mode. After this has been done, if T I input is
changed to
low-level
from
high-level, an interrupt is
generated in address 7.
Flag IBF can also be tested using a conditional jump
instruction. For more details on this procedure, check the
"Conditional Jumps Using Pins To ,T I and Flags IBF, OBF"
section.
• MITSUBISHI
"ELECTRIC
8-23
MITSUBISHI LSls
MSL 8041A-XXXP
UNIVERSAL PERIPHERAL INTERFACE
TIMER/EVENT COUNTER
The timer/event counter for the MSL8041A-XXXP is an
8-bit counter, that is.used to measure time delays or count
external events but not both The same counter is used to
measure time delays or count external events by simply
changing the input to the counter.
CRYSTAL
OSCI LLATOR
1/15
OUNTER
The counter can be preset by executing an MOV T, A
instruction. The value of the counter can be read for checking by executing an MOV A, T instruction. Reset will stop
the cOl.l)1ting butthe counter is not cleared, so counting can
be resumed.
The largest number the counter can contain is FF 16 . If
it is incremented by 1 when it contains FF 16, the counter
will be reset to 0, the overflow flag is set and a timer
interrupt request is generated.
TIMER OVER FLOW FLAG
INTERRUPT ENABLE
INTERRUPT
REQUEST
Fig. 7 Timer/event counter
The conditional jump instruction JTF can be used to
test the overflow flag. Care must be used in executing the
JTF instruction because the overflow flag is cleared when
executed (reset). When a timer interrupt is accepted, the
control is transferred to address 7 of program memory.
When both a timer and external interrupt request are
generated at the same time, the external interrupt is given
priority and will be accepted first by automatically subroutine
jumping to address 3 of program memory. The timer
interrupt request is kept and will be processed when the
external interrupt has been completed and a RETR is
executed. A latched timer interrupt request is cancelled
when a timer interrupt request is generated.
The START CNT instruction is used to change the
counter to an event counter. Then Pin T 1 signal
becomes the inpu t to the event counter and an event is
counted each full cycle (low-high-Iow one event). The
maximum rate that can be counted is one time in 3
machine cycles (7.SJ,ts when using 6MHz crystal). The
high-level at T 1 must be maintained at least 1/5 of the cycle
time (SOOns when using 6MHz crystal).
The START T instruction is used to ch&nge the counter
to a timer. The internal clock signal becomes the input to
the timer. The internal clock is 1/32 of 400kHz (when
using 6MHz crystal) or 12.SkHz. The timer is therefore
counted up every 80J,ts. Fig. 7 shows the timer/event
counter.
The counter can be preset by executing an MOV T,
A instruction. The timer can be used to measure 80J,ts20ms in multiples of 80J,ts. When it is necessary to measure
over 20ms (maximum count 256x80J,ts) of delay time the
number of overflows, one every 20ms, can be counted by
the program. To measure times of less than 80J,ts; external
clock pulses can be input through T 1 while the counter is in
the event counter mode. Every third (or more) ALE signal
can be used instead of an external clock pulses.
8-24
• MITSUBISHI
"ELECTRIC
MITSUBISHI LSls
MSL 8041A·XXXP
UNIVERSAL PERIPHERAL INTERFACE
CYCLE TIMING
RESET
The output of the state counter is 1/3 the input frequency
from the oscillator. A ClK signal is generated every 500ns
(one state cycle) which is used for the demarcation of each
machine state.
Fig 9 shows the relationship between clock and generated cycles.
One machine cycle contains 5 states with a ClK signal
for demarcation of each state. The M5l8014A-XXXP
instructions are executed in one machine cycle or two
machine cycles. An instruction cycle can be one or two
machine cycles as shown in Fig. 10.
The reset Pin is for resetting the CPU. A Schmitt
trigger circuit along with a pull-up register are connected to
it on the chip. A reset can easily be generated by attaching
a lJlF as capacitor as shown in Fig. 11. An external reset
pulse applied at RESET must remain at low-level for at
least 10ms after power has been turned on and reached its
normal level.
The reset function causes the following initialization
within the CPU.
1. Program counter is reset to O.
2. Stack pointer is reset to O.
3. Memory bank is reset to O.
4. Ports 1 and 2 are reset to input mode.
5. External and timer interrupts are reset to disable
state.
6. Timer is stopped.
7. Timer overflow flag is cleared.
8. Flags F0 and Flare cleared.
Fig. 8 Clocking cycle generation
M5L8041A
-xxxp
5V
SYNC +--+--i-'
PROGt---r--t--l-L-1-~__~__~~r--t--t
-
ABOUT
200KU
ll.u F
Fig. 9 Clock and generated cycle signals
J10V
2.51ls (WHEN USING A 6MHz CRYSTAL)
Fig. 11 Example of a reset circuit
INSTRUCTION CYCLE
1
S5
Sl
II~STRU-
CTION
FETCrl
S2
I
J
S3
I
S4
I
Sl
S5
I
INSTRUCTION DECODE INSTRUCTION
PROGRAM COUNTER
EXECUTION
UPDATINjG
Fig. 10 Instruction execution timing
• MITSUBISHI
"ELECTRIC
8-25
II
MITSUB'ISHI LSls
MSL 8041A-XXXP
UNIVERSAL PERIPHERAL INTERFACE
SINGLE·STEP OPERATION
The Pin SS on the
M5L8041A-XXXP is provided
to
WHENSSIS LOW, THE CPU RECOGNIZES THAT
facilitate single-step operation. In single-step operation, the
IT IS TO STOP
CPU stops after the execution of each instruction is
J
completed and the memory address (12 bits) of the next
instruction to be fetched is output through the data bus (8
bits) plus the low-order 4 bits of port 2. The user can use
WHEN THE NEXT INSTRUCTION IS FETCHED,
THE CPU SETS SWITCHES SO IT WI LL STOP AFTER
THE EXECUTION OF THE INSTRUCTION IS COM-
this to trace the flow of this program instruction by
PLETED.
instruction and will find this an aid in program debugging.
WHEN SYNC IS HIGH, THE MEMORY ADDRESS
OF THE NEXT INSTRUCTION TO BE FETCHED
IS OUT.
PUT THROUGH THE DATA BUS (8 BITS) AND
THE LOW-ORDER 4 BITS OF PORT 2-
'"
Single-step operation is controlled through SS and SYNC as
shown in Fig. 12.
sv
~
sv
SINGLE-STEP
MODE
WHEN
55 IS
RETURNED TO HIGH LEVEL THE
CPU RECOGNIZES THAT IT IS IN THE RUN MODE.
THEN THE SYNC SIGNAL GOES TO LOW-LEVEL
WHICH INDICATES THE CPU IS IN THE RUN MODE
AND THAT IT IS EXECUTING INSTRUCTIONS
!
IF THE CPU IS IN THE SINGLE-STEP MODE (PRESET TERMINAL GROUNDED), AS SOON AS SYNC
GOES TO LOW-LEVE L, 55 GOES TO LOW-LEVE L
(STOP). I F THE CPU IS THE RUN-MODE (PRESET TERMINAL NOT GROUNDED), SSWILL RE-
BUFFER
MAIN AT HIGH-LEVEL.
(a) Example of single step circuit
SY,NC~~
EXECUTING
INSTRUCTION
I·
STOP
Fig. 13 CPU operation in single-step mode
I
EXECUTING
-+INSTRUCTION
(b) Single-step operation timing
Fig. 12. Single-step operation circuit and timing
A type 0
flip-flop with preset and reset Pins,
as
shown in Fig, 12, is used to generate the signal for SS. When
the preset Pin goes to low-level, SS goes to high-level,
which puts the CPU in RUN mode. When the preset
Pin is grounded it goes to high-level. Then SS goes to
low-level. When SS goes to low-level, the CPU stops. Then
when the push-button switch is pushed, a pulse is sent to
the clock Pin of the type 0 flip-flop which turns S5 to
high-level. When S5 goes to high-level the CPU fetches the
next instruction and begins to execute it, but then an ALE
signal is sent to the reset pin of the type 0 flip-flop
which turns S5 to low-level. The CPU again stops as soon as
execution of the current instruction is completed. The CPU
is in single-step operation as shown in Fig. 13.
8-26
• MITSUBISHI
.... ELECTRIC
MITSUBISHI LSls
MSL 8041A-XXXP
UNIVERSAL PERIPHERAL INTERFACE
Central Processing Unit (CPU)
Interrupts of the Master CPU
Central Processing Unit (CPU) is composed of an 8-bit
parallel arithmetic unit, accumulator, flag flip-flop and
instruction decoder. The 8-bit parallel arithmetic unit has
circuitry to perform the four basic arithmetic operations
(plus, minus, multiply and divide) as well as logical opera-
In addition to use as a. normal input/output port, the
M5L8041A-XXXP P24 and P25 pins may be used as the
IBF (Input Buffer Full) flag and OBF (Output Buffer Full)
flag outputs. Immediately after resetting, P24 and P25 are
usable as normal input ports.
tions such as AND and OR. The flag flip-flop is used to
indicate status such as carry and zero. The accumulator
contains one of the operations and the result is usually
retained in the accumulator. (The flag flip· frops hold the
ca'rry and borrow states for execution of ail processing
M5L8041 A-XXXP
OBF
instructions. )
)
DMA Control
In addit~on to use as a normal input/output port, the
M5L8041A-XXXP port P26 and P27 can be used to provide
control signals for handshake control of DMA operations.
Immediately after resetting, P26 and P27 can be used as a
normal port (Fig. 14).
ORO
M 5L8041 A
P27 h
ORQn
M5L82 57P
D MA
-xxxp
OACK
Fig. 15 Interrupt requests to the master CPU
When the EN F LAGS instruction is executed, P24
becomes the OBF pin and P2S thelBF pin. At this time, in
order to enable OBF flag and IBF flag status outputs for
pin 24 and pin 25, it is necessary to set pin 24 and pin 25
OMA
P26
INTERRUPT
REQUEST TO
THE MASTER
CPU
OACKn
to 1. With P24 and P2 5 set to 0, these fl ag statuses are not
output. The OBF flag output indicates that data is being
output to the M5L8041 A-XXXP output data bus buffer
register while the IBF flag output indicates that data can be
accepted by the input data/command bus buffer register.
Fig. 14 DMA Control
When the EN DMA instruction is executed, P26 becomes
the DRO (OM A request) output. Subsequently, when P26
is set to 1, ORO becomes 1 and DMA data transfer is
requested.
ORO is returned to 0 when DACK'R, DACK· W, or EN
DMA is executed.
In addition, when EN DMA is executed, P27 becomes
the DACK (DMA acknowledgment) input. This DACK
input serves as the chip select input during DMA transfer
operations. Therefore, the normal chip select S status has
no meaning during DMA transfers.
• MITSUBISHI
"ELECTRIC
8-27
8
MITSUBISHI LSls
MSL 8041A-XXXP
UNIVERSAL PERIPHERAL INTERFACE
MACHINE INSTRUCTIONS
ts
Instruction code
Mnemonic
0,0 6 Os D.
Type
MOV A, ti:n
MOV A, PSW
MOV A, Rr
MOV A, (PRr
MOV PSW, A
MOV STS, A
0
0
1
0
"7"6"5"4
0 3 D2 0 1 Do
0
1
0
0
0
1
1
1
1
1
1
1
1
1
1
$
c6
23
u
0
>
u
1
0
1
0
0
1
$
Transfers data n to register A.
0
1
1
C7
r:2 r 1 r 0
F 8
+
0
1
(A)~(PSW)
Transfers the contents of the program status
worn to register A.
oro
(A)~(Rr)
r= 0
FO
0
1
1
1
Transfers the contents of register Rr to register A.
7
~
Transfers the contents of memory location,
of the current page, whose address is in register Rr to register A.
(A)~(M(Rr»
~O
- 1
~
(PSW)
07
(A)
0
0
0
0
~
(STS)
90
0
Transfers the contents of register A to the
program status word.
0
(A)
Transfer. the contents of register A to the
system status register.
(ST.- ST')~(A.-A')
MOV Rr, A
~
t=
MOV Rr, tin
MOV (gRr, A
MOV (P Rr, j1:n
MOVP A, (gA
MOVP3 A, ",A
XCH A, Rr
XCH A, (PRr
XCHD A, (aRr
1
0
1 0
1
1
0
1
"7"6"5"4
1
1
0
0
1
1
0
1
"7"6"5"4
1
1
r 2r 1r O
r2 r 1 r 0
A8
+
0
0
0
0
oro
0
r0
"3"2"1"0
0
1
1
A3
1
1
1
0
0
0
1
1
E 3
0
0
1
0
1
r 2r 1r 0
0
0
1
1
0
0
0
oro
oro
Transfers the contents of register A to memory location, of the current page, whose address is in register R r .
(M(Rr»~(A)
(M (Rr »~n
Transfers data n to memory location, of the
current page, whose address is in register R r .
r=O- 1
0
0
Transfers data n to register R r .
r=O- 1
BO
+
0
0
(Rr)~n
AO
+
1
1
Transfers the contents of register A to register R r .
r=0-7
"3"2"1"0
0
0
(Rr)~(A)
r=0-7
B8
+
1
0
Transfers the data of memory location, of
the current page. whose address is in register
A to register A.
(A)~(M(A»
(A)~ (M (page
28
+
(A).-~
Transfers the data of memory location, o~
page 3, whose address is in register A to
register A.
3, A»
(Rr)
Exchanges the contents of register Rr with
the contents of register A.
r=O- 7
20
+
(A)
~~
Exchanges the contents of memory location,
of the current page, whose address is in register Rr with the contents of register A.
(M (Rr»
r=O-1
30
+
(Ao-A3)'~(M (Rro-Rr3»
r=O~1
-~--
ADD A, j1:n
ADD A, Rr
.,
.u
ADD A, ,aRr
0
0
0
0
"7"6"5"4
0
0
1
1
1
1
0
0
0
0
1
1
03
ADDC A, ti:n
ADDC A, Rr
ADDC A, (aRr
8-28
0
0
0
1
"7"6"5"4
0
0
1
1
1
1
1
1
(A)~
(A)+n
"3"2"1"0
1
0
r 2r 1r 0
0
oro
68
+
60
+
~
~
Description
a
(A)~n
(O)~(A'). (AO)~(A6)
1
AO
Z
r
1
Effected
carry
"3"2"1"0
1
1
0
Hexadecimal
Function
1G
0
0
1
1
(A)·-(A)+(Rr)
r=0-7
r=O-l
(A)
~
(A)+ n+ (0)
(A)
~
(A)+(Rr)+(O)
1
0 0
1
0 0
1
Adds tile contents ot register A and me contents of memory location. of the current page.
(A)~(A)+(M(Rr»
1 3
0 0
0
r 2r 1r 0
0
oro
78
+
70
+
r=0-7
(A) ~ (A)+(M (Rr»
+ (0)
r=O~l
• MITSUBISHI
.... ELECTRIC
whose address ~s in register A and sets the
carry flags to 1 If there ',S an overflow otherwise resets the carry flags to O. The result is
stored in register A.
Adds the carry and data n to the contents of
register A and sets the carry flags to 1 if there
is an overflow otherwise resets the carry flags
to O. The result is stored in register A
0 0
"3"2"1"0
1
Exchanges the contents of the low-order 4bits of register A with the low-order 4-bits
of memory location. 01 the current page,
whose address is in register Rr ·
Adds data n to the contents 01 register A and
sets the carry flags to 1 if there is an overflow
otherwise resets the carry flags toO The rebult
IS stored In register A.
Adds the contents of register Rr to the contents ot register A and sets the carry flags to 1
If there IS an overflow otherWise resets the
~arry flags to O. The result is stored In register
0 0
1
0 0
1
Adds the carry and the contents 01 register Rr
to the contents of register A and set the carry
flags to 1 if there is an overflow otherwise resets the carry flags to. O. The result is stored
in register A.
Adds the carry and the contents of memory
location. of the Current pa~e. whose address
IS In register Rr to the contents of register A
and sets the carry flags to llf there IS an over:~~~ltO~;;~i~a ~~si'J~11~~r ct,rry flags to O. the
MITSUBISHI LSls
MSL 8041A-XXXP
UNIVERSAL PERIPHERAL INTERFACE
\Item
Effected
carry
I nstruction code
\
Mnemonic
0,06 0 5 0 4
Type
CAll m
m10rn9me 1
03 D 2 0 ,Oo
0
1
0
Hexadecimal
14
0
+
me
m7 rne m S m 4
l!l
>
en
gj
Function
u
C
>
u
«SP» (SP) -
m,o
(PC) (PSW4- PSW,)
(SP)
+1
(PC o 1O)~ m
m3 m 2 rn , rn O
(PC" ) -- M8F
AC
Description
l!l
0
Z
Calls subroutine from address m. The program counter and the 4 high-order bits of the
PSW are stored In the address indicated by
the stack pointer(SP). The SP IS incremented
by 1 and m is transferred to PCo- pe1Q and
the MBF is transferred to PC".
B --
--
Q)
c
.~
RET
1
0
0
0
0
0
1
1
83
j
RETR
1
0
0
1
0
0
1
1
93
(SP) -
(SP)-1
(PC) -
«SP»
(SP) -
(SP) - 1
(PC) (PSW4 -PSW,)-«SP»
IN A, Pp
0
0
0
0
1
0 p, Po
08
(A)- (Pp)
+
p=1-2
P
OUTl Pp, A
0
0
1
1
1
0 P,Po
38
(Pp) -(A)
+
p=1-2
P
ANl Pp, lin
ORl Pp, lin
p, Po
98
n 7n 6n 5n 4 n3 n 2n,nO
P
1
0
0
1
1
o
p, Po
88
n
0
0
0
1
o
p=1-2
n
n 7n 8 n 5 n 4 n3 n 2n,nO
1
(pp )-(Pp)/\ n
+
(Pp)-(Pp)Vn
+p
IN A, DBB
0
0
1
0
0
0
1
0
22
OUT DBB, A
0
0
0
0
0
0
1
0
02
0
0
0
0
1
1 p, Po
p=1-2
The SP IS decremented by 1 The program
counter is restored to the saved setting In
the stack indicated by the stack pOinter.
The PSW is not changed and interrupt disabled is maintained.
The SP is decremented by 1. The program
counter and the 4 bigh-order bits of the PSW
are restored with the saved data in the stack
indicated by the stock pointer. The interrupt
becomes enabled after the execCJtion IS completed.
Loads the contents of Pp to register A.
Output latches the contents of register A to
Pp
Logical ANDs the contents of Pp and data
n. Outputs the result to Pp
Logical ORs the contents of Pp and data
n Outputs the result to Pp .
(A) '-(088)
Enters the contents of data bus buffer
(OBB) in register A:
(088)- (A)
Outputs the contents of register A to
bus buffer (DBB) OBF is set
::>
Cl.
i
MOVD A, Pp
OC
+
P,Po
1
(Ao-A 3 )-(PPO-PP3)
(A4- A ,)-O p=4-7
MOVD Pp, A
0
0
1
1
1
1 p, Po
3C
(PPO-PP3)-( Ao -A3)
+
p=4-7
P,Po
ANlD Pp, A
1
0
0
1
1
1 p, Po
9C
+
P,Po
(PPO-PP3)-( PpO-PP3) /\( Ao-A3)
1
p=4-7
ORlD Pp, A
1
0
0
0
1
1 p, Po
8C
+
P,Po
(PPO-PP3)-(PPO-PP3)V (Ao-A3)
1
p=4-7
• MITSUBISHI
;"ELECTRIC
Inputs the contents of Pp
of 8243 to the low - order
4 bits of register A and
inputs 0 to the high-order
4 bits of register A.
Outputs the low-order 4
bits of register A to Pp.
Logical ANOs the 4 loworder bits of register A
and the contents of Pp.
Pp contains the result
Logical ORs the 4 loworder bits of
data
Pp's used
for multiplying 8243
ports are P4
~P7.
Correspondence to P2,
P, is shown
below.
P4 -·P,P2=OO
P5 ··P,P2=01
P6 ··P,P2 = 10
P7 ··P,P2= 11
register A
and the contents of Pp
Pp contains the result
8-29
II
MITSUBISHI LSls
MSL 8041A-XXXP
UNIVERSAL PERIPHERAL INTERFACE
S
I nstruciton code
Mnemonic
Type
ANL A, it"
ANL A, Rr
ANL A, (llRr
ORL A, it"
ORL A, Rr
ORL A, (llRr
XRL A, it"
u
;:;
~
~
XRL A, Rr
XRL A, @Rr
INC A
DEC A
CLR A
CPL A
07 0 6 0 5 0 4
0
1
0
1
0 3 0 2 0,00
0
0
1
1
Hexadecimal
Q)
>-
OJ
U
53
0
1
1
0
0
1
1
1
0
r 2 r,r O
(A)~(A)
0
o ro
58
+
Effected
carry
C
>-
U
n 7 n 8 n 5 n 4 n 3 n 2 n,n O
0
Function
Q)
AC
0
The logical product of the contents of register A and data n, is stored in register A.
fin
The logical product of the contents of register A and the contents of register R r , is
stored in register A.
(A)~(A)"(Rr)
r=0-7
50
The logical product of the contents of
register A and the contents of memory location, of the current page, whose address is
in register Rr , is stored in register A
(A)~(A)"(M(Rr»
r=O-1
0
1
0
0
0
0
1
1
43
(A)~
n 7 n 6 n 5 n 4 n 3 n 2 n,n O
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
r 2 r,r O
0
0
o ro
1
1
48
1
1
1
0
0
1
1
1
0
r 2 r,r O
0
oro
0
0
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
0
1
0
0
1
1
1
0
0
1
1
0
1
1
1
0
1
0
1
0
1
1
1
0
1
0
0
0
1
1
1
1
1
1
0
0
1
1
1
08
+
DO
+
The logical sum of the contents of register A
and the contents of register Rr is stored in
register A.
The logical sum of the contents of register A
and the contents of memory location, of
the current page, whose address is in register R r , is stored in register A
(A) V (Rr)
(A)~(A)V
+
03
~
The logical sum of the contents of register
A and data n, is stored in register A.
(A)Vn
r=0-7
40
n 7 n 6 n 5 n 4 n 3 n 2 n,n O
1
(A)
+
(M(Rr»
r=O-1
2
Description
$
Z
(A)
~-
(A)\/-n
The excl usive 0 R of the contents of register
A and data n, is stored in register A.
(A)
~
(AW (Rr)
The exclusive OR of the contents of register
A and the contents of register Rr is stored
in register A.
The exclusive OR of the contents of register
A and the contents of memory location, of
the current page, whose address is in register
Rr , is stored in register A.
Increments the contents of register A by 1.
The result is stored in register A, and the carries are unchanged.
r=I-7
(A)~(A)V
(M(Rr»
r=O-1
1 7
(A)~(A)+1
07
(A)~(A)-1
27
(A)~O
37
(A)~(A)
57
(A)~(A)
47
(A4-A7)~ (Ao-A3)
Decrements the contents of register A by 1.
The result is stored in register A, and the carries are unchanged.
Clears the contents of register A, resets to
O.
Forms l's complement of register A , and
stores it in rsgister A.
The contents of register A is converted to
DA A
SWAP A
RL A
RLC A
1
1
1
1
0
1
1
1
E 7
(Ao)~(A7)
(Ao)~(C)
RRC A
u
.;:;
i
INC Rr
INC il'Rr
0
0
1
1
1
1
1
0
0
0
1
1
1
1
1
1
77
67
0
0
0
1
1
r 2 r, r 0
18
0
0
0
1
0
0
o ro
10
+
+
~
.~
a:
8-30
DEC Rr
1
1
0
0
1
r 2 r, ro
C8
+
n=0-6
0
(An)~(An+')
(A7)~
(Ao)
(An)~(An+l)
(A7)~(C)
(C)~ (Ao) n
(Rr) '-(Rr)+l
r=0-7
(M ( Rr )) ~ ( M ( Rr ) ) + 1
r=O - 1
(Rr)~(Rr)-1
r= 0 -- 7
• MITSUBISHI
.... ELECTRIC
blnarycoded de'clmal notion, and It IS stored
In reqlster A. If the contents of register A are
more than gg the carry flags are set to lather
Wise they are reset to 0
Shifts the contents of register A left one bit.
A7 the MSB is shifted to the carry flag and
the carry flag is shifted to Ao the LSB.
Shifts the contents of register A right one
bit. Ao the LSB is rotated to A7 the MSB.
n=0-6
=0 - 6
1
Shifts the contents of register A left one bit.
A7 the MSB is rotated to Ao the LSB.
n=0-6
(An+,)~(An)
F 7
0
Exchanges the contents of bits 0-3 of register A with the contents of bits 4-7 of register A.
(An+,)~(An)
(C)~(A7)
RR A
0
0
Shifts the contents of register A right one
bi t. Ao the LSB is sh i fted to the carry flag
and the carry flag is shifted to A7 the MSB.
Increments the contents of register Rr by
1. The result is stored in register Rr and the
carries are unchanged.
Increments the contents of the memory
location .. of the current page, whose address
IS In register R, by 1. Register R, uses bit
0-5 .
Decrements the contents of register Rr by
1. The result is stored in register Rr and the
carries are unchanged.
MITSUBISHI LSls
MSL 8041A-XXXP
UNIVERSAL PERIPHERAL INTERFACE
I\em
TY~
Hexadecimal
I JBb m
JNIBF m
JOBF m
JTF m
Effected
carry
I nstruction code
Mnemonic
b7 b8 bs 1
0
0
1
0
~
co>
1 2
1
0
1
0
1
1
0
C
AC
0
z
Jumps to address m of the current page when
bit b of register A is 1. Executes the next
instruction when bit b of register A is O.
Jumps to address m off the curent page
when IBF is O. otherwise the next instruction IS executed.
06
10000110
86
00010110
1 6
(TF) = 1 then (PCO-PC7)~m
04
(PCS-PClO)~mS-mlO
(OBF)
=
Jumps to address m of the current page
when OBF is O. otherwise the next instruction is exacted.
1 then (PCO-PC7)~m
Jumps to address m of the curent page
when the overflow flag of the timer IS 1
otherwise the next Instruction is executed.
Flag IS cleared after executing
(TF)=O then (PC)~(PC)+ 2
4-
JMP m
m8-10
Description
0:
u>
(Ab)=1 then (PCO-PC7)~m
(Ab)=Othen (PC)~ (PC)+2
b7b6bS= 0 - 7
+
b
1
Function
g)
u
2
Jumps to address m on page m'Om9mS in
the memory bank indicated by MBF
(PCO-PC7)~mo-m7
(PCll) ~ (MBF)
Jumps to the memory location. of the cur-
JMPP ",A
1
0
1
1
0
0
1
1
E8
+
OJNZ Rr, m
rent page. whose address is in register A.
But when the instruction executed was In
address 255. jumps to next page.
B3
(Rr) ~ (Rr )-1 r = 0 -7
(Rr) +0 then (PCo _ PC7)~ m
(Rr) = 0 then (PC)~( PC) + 2
1-_ _ _ _ _---1rm_7_m_8_m_5_m_4_m_3__m_2_m_l_m_°+_ _-+_+--+_______-._--+-+-+--i
1
JC m
1
1
1
0
1
1
0
F 6
(C)=1 then
Jumps to address m of the curent page if
the carry flag C IS 1. otherwise the next
instructio'1 isexecuted.
(PCO-PC7)~m
(C)=O then (PC)~(PC)+2
JNC m
1
1
0
0
1
1
0
E6
1
0
0
0
1
1
0
C6
1
0
0
1
0
1
1
0
96
Jumps to address m of the current page
when the contents of register A are O.
otherwise the next instruction is executed
(A) =0 then (PCO-PC7)~m
(A) ±O then
JNZ m
Jumps to address m of the current page if
the carry flag C is O. otherwise the next
Instruction is executed.
(C)=O then (PCO-PC7)~m
(C)=1 then (PC)~(PC)+2
1
JZ m
1
Decrements the contents of register Rr by 1.
Jumps to address m of the current page
when the result is not 0, otherwise the next
instruction is executed
(PC)<-(PC)+2
(A)t-O then (PCO-PC7)~m
Jumps to address m of the current page
when the contents of register A are not O.
r-______rm_7_m_6_m_s_m_4_m_3_m_2m_lm~o---1-_+-+-(A-)=-O-th_e_n__(__PC_)<_-_(_P_C_)_+_2___~~-+_-+-ot-h-er-w-is-e-th-e_n_e_xt_i_ns_tr_u_ct_io_n_i_s_ex_e_cu_te_d_.~
JTO m
JNTO m
JT1 m
JNTl m
JFO m
JFl m
CLR C
CPL C
l
Cl
ro
u:::
CLR Fo
CPL
Fo
o
0
1
1
0
1
1
0
36
0010011026
(To) = 1 then (PCO-PC7)~m
(To)=O then (PC)~(PC)+2
~h~~~lat~ T~~~rle~thr;;r~~et~~e ~~~:7~sfr~~~
(To) =0 then (PCO-PC7)~m
Jumps to address m cf the current page
(T o)=1 then
o
1
0
1
0
1
1
0
56
(Tl) =1 then
tionexccuted
when flag To is 0, otherwise the next instructIon is executed.
(PC)~·(PC)+2
Jumps to address m of the current page
when flag Tl is 1. otherWise the next instruc-
(PCO-PC7)~m
(Tl)=O then (PC)~(PC)+2
o
1
0
0
0
1
1
0
46
tion is executed
Jumps to address m of the current page
when flag T, is O. otherwise the next instruc-
(Tl)=O then (PCo -PC7)~m
(T l )=l then (PO)~(PC)+2
1
0
1
1
0
1
1
0
B6
tion is executed.
(Fo) =1 then (PCO-PC7)~m
Jumps to address m of the current page
when flag Fa is 1.
(Fo)=O then (PC)~(PC)+2
0111011076
(F,) =1 then (PCO-PC7)~m
(F,) =0 then (PC) ~ (PC)
1
0
0
1
0
1
1
1
1
0
1
0
0
1
1
1
1
000
o
1
0
1
1
0
0
1
o
1
0
1
1
0
1
0
0
1
0
1
1
0
1
1
0
1
0
1
97
(C)~
0
A 7
Jumps to address m of the current page
when flag Fl is 1.
+2
o
Clears the carry flag C. resets it to O. AC
not affected
o
Complements the carry flag C AC
affected.
85
(Fo)-O
Clears the flag F o , resets itto 0.
95
(Fo)~ (Fo)
Complements the flag Fo·
A5
B5
IS
IS
not
Clears flag F, resets itto 0.
(F,)~(F,)
• MITSUBISHI
"ELECTRIC
Complements the flag F,
8-31
II
:
MITSUBISHI LSls
MSL 8041A-XXXP
UNIVERSAL PERIPHERAL INTERFACE
~~
Effected
carry
Function
l!l
Description
Hexadecimal
CD
U
1
05
1
1
(INTF)' - 1
Enables outside interrupt.
0
1
1 5
1
1
(INTF) ~O
Disables outside interrupt.
1
0
1
C5
1
1
(BS)~O
Selects working register bank 0_
0
1
0
1
OS
1
1
(BS)~
Selects working register bank l_
0
1
0
1
E 5
1
1
0,0 6 Os 0 4
03 O2 0 1 00
EN I
0
0
0
0
0
1
0
DIS I
0
0
0
1
0
1
SEL RBo
1
1
0
0
0
SEL RB,
1
1
0
1
EN DMA
1
1
1
0
Type
~
·I~
Instruction code
Mnemonic
>
>
C
AC
0
Z
0
u
1
Enables DMA hand shake lines.
t--EN FLAGS
~8
(P24)~(OBF)
1
1
1
1
0
1
0
1
F 5
1
1
MOV A, T
0
1
0
0
0
0
1
0
42
1
1
(A)~(T)
MOV T, A
0
1
1
0
0
0
1
0
62
1
1
(T)~(A)
0
1
0
1
0
1
0
1
55
1
1
STRT T
(P2s)~(
En'lbles interrupts from master.
IBF)
Transfers the contents of ti mer/event counter to register A
I
Transfers the contents of register A to timer/
event counter.
Starts timer operation of time/event counterm. Minimum count cycle is 80lls
1
-
'c"
:0
STRT CNT
0
1
0
0
0
1
0
1
45
1
1
Starts operation as event counter of time/
event counter. Counts up when terminated
T 1 changes to input high-level for input lowlevel. Minimum count cycle is 7_5Ils.
STOP TCNT
0
1
1
0
0
1
0
1
65
1
1
Stops operation of timer or event counter
EN TeNTI
0
0
1
0
0
1
0
1
25
1
1
(TCNTF)~
DIS TCNTI
0
0
1
1
0
1
0
1
35
1
1
(TCNTF) ~- 0
NOP
0
0
0
0
0
0
0
0
00
1
1
0
u
c
~
~
~
f=
I
1
Enables interrupt of timer/event counter
Disables interrupt of timer/event counter
Resets interrupt flip-flop of CPU which is set
during the CPU stands-by Timer over flow
flag isn't affected.
u
~
No operation. Execution time is 1 cycle.
Note l' Executing an instruction may produce a carry (overflow or underflow). fhe carry may be disregarded (lost) or it ncay be transferred to C/AC (saved)
The saving of a carry is not shown in the function equation;, but is instead shown in the carry columns C and AC. The detail affection of carries for
instructions ADD ADDC and DA is as follows:
(C) <--- 1
at overflow of the accumulator is produced
(C) <--- 0
at no overflow of the accumulator is produced
(AC) <--- 1
at overflow
(AC) <--- 0
at no overflow.
Of
the bit 3 of the accumulator
2: The contents of ST. -ST 7 is read when the host computer reads the status of M5L8041 A-XXXP
8-32
• MITSUBISHI
.... ELECTRIC
MITSUBISHI LSls
MSL 8041A-XXXP
UNIVERSAL PERIPHERAL INTERFACE
Symbol
Symbol
Details
Details
A
8-bit register (accumlator)
PC
Program counter
Ao-A3
The low-order 4 bits of the register A
PCO-PC7
The low-order 8 bits of the program counter
A4-A7
The high-order 4 bits of the register A
PCS-PClO The high-order 3 bits of the program counter
Ao-An,An + 1
The bi ts of the register A
PSW
Program status word
b
rhe value of the bits 5-7 of the first byte machine code
Rr
Register designator
b7 b Sb s
The bits 5-7 of the first byte machine code
BS
Register ban k select
BUS
Corresponds to the port 0 (bus I/O port)
r
Register number
rO
The value of bit 0 of the machin8 code
r2 r 1 r O
The value of bi ts 0-2 of the machine code
l
Auxiliary carry flag
C
Carry flag
S2 S 1S 0
The value of bits 0-2 of the stack pointer
DBB
J
Data bus buffer
SP
Stack pointer
AC
Fo
Flag 0
F1
Flag 1
INTF
I nterrupl flag
IBF
Input buffer full flag
m
The value of the 11-bit address
I
(M (A»
The second byte (low-order 8 bits) machine code of the 11-bit
address
The bits 5-7 of the first byte (high-order 3 bits) machine code
of the 11 -bi t address
The content of the memory location addressed by the register A
(M (Rr»
The content of the memory location addressed by the register Rr
m7rn6mSm4m3m2m1mO
mlO mg rnS
ST4ST7
Bi ts 4-7 of the status register
STS
System status
T
Timer/event counter
To
Test pin 0
T1
Test pin 1
TCNTF
Timer/event counter overflow interrupt flag
TF
Timer flag
j:j:
Symbol to indicate the immediate data
@
Symbol to indicate the content of the memory location
addressed by the register
MBF
The content of the external memory location addressed by
the register Rr
Memory bank flag
n
The value of the immediate data
n7nSnSn4n3n2n1nO
The immediate data of the second byte machine code
---
OBF
Output buffer full flag
1\
Logical AND
V
Inclusive OR
P
Pp
Port number
Port designator
V
Exclusive OR
P1 Po
The bits of the machine code corresponding to the port number
(Mx(Rr»
• MITSUBISHI
"ELECTRIC
(
Shows direction of data flow
Exchanges the contents of data
)
Contents of register memory location or flag
-
Negation
0
Content of flag is set or reset after execution
II
8-33
MITSUBISHI LSls
MSL 8041A-XXXP
UNIVERSAL PERIPHERAL INTERFACE
Instruction Code List
0000
0000
Hexadecimal
0
0
NOP
0001
0010
0011
0100
0101
0110
0111
2
3
4
5
6
7
A
1000
1001
1010
1011
1100
1101
1110
1111
8
9
A
B
C
0
E
F
INC
ea RO
0001
0010
2
0011
3
0100
4
0101
5
0110
6
0111
7
1000
8
1001
9
1010
A
1011
B
1100
C
1101
0
1110
E
1111
F
8-34
A
A
A
A
ANL
ADD
A,RO
A,RO
ANL
ADD
A,Rl
A,Rl
ANL
ADD
A,R2
A,R2
ANL
ADD
A,RJ
A,RJ
ANL
ADD
A,R4
A,R4
ANL
ADD
A,RS
A,RS
ANL
ADD
A,R6
A,R6
ANL
ADD
A,R7
R7, A
• MITSUBISHI
.... ELECTRIC
•
2-byte, 2-cycle instruction
~
1-byte, 2-cycle instruction
MITSUBISHI LSls
MSL 8041A-XXXP
UNIVERSAL PERIPHERAL INTERFACE
ABSOLUTE MAXIMUM RATINGS
Symbol
Conditions
Parameter
Vee
Supply voltage
VI
Input voltage
Ve
Output voltage
Pd
Power dissipation
Topr
Operating temperature range
Tstg
Storage temperature range
Unit
Limits
With respect to Vss
-0.5-7
V
-0.5-7
V
-0.5-7
Ta=25'C
V
1500
mW
'C
0-70
'C
-65-150
RECOMMENDED OPERATING CONDITIONS
Limits
Symbol
Parameter
Unit
Min
Vee
Supply voltage
VSS
Supply voltage
Nom
Max
5
5.5
4.5
0
VIH
High-level input voltage
VIL
Low-level input voltage
f( ¢)
Operating frequency
V
V
2
V
0.8
1
6
V
MHz
ELECTRICAL CHARACTERISTICS (Ta = -20~70°C, Vcc=5V±1O%, unless otherwise noted)
Limits
Parameter
Symbol
Conciitions
Unit
Typ
Min
VIL
Low-level input voltage (all except X" X 2 )
VIHl
High-level input voltage (all except Xl, X2 , RESET)
VIH2
High-level input voltage (Xl, X 2 , RESET)
VOLl
Low-level output voltage (Do~D7' SYNC)
Do~D7,
SYNC, PROG)
-0.5
0.8
2
Vee
V
3.8
Vee
V
IOL= 2 mA
0.45
V
IOL=1.6mA
0.45
V
0.45
V
VOL2
Low-level output voltage (all except
VOU
Low-level output voltage (PROG)
IOL= 1 mA
VOHl
High-level output voltage (Do~D7)
IOH= -400,uA
2.4
VOH2
High-level output voltage (all other outputs)
IOH= -50,uA
2.4
RD, WR, (S,
Max
V
V
V
II
Input leakage current (To, T"
VSs~vl~Vee
±10
IOZL
Off-state output leakage current (Do~D7)
Vss+ O. 45~ VO~ Vee
±10
,uA
IILl
Low-level input current (PIO~P17' P20~P27)
VIL=0.8V
0.5
mA
IIL2
Low-level input current (RESET,
VIL=0.8V
0.2
mA
IDD
Supply current from V DD
lee+IDD
Total supply current
SS)
Ao)
• MITSUBISHI
.... ELECTRIC
,uA
15
rnA
125
mA
8-35
II
MITSUBISHI LSls
MSL 8041A-XXXP
UNIVERSAL PERIPHERAL INTERFACE
TIMING REQUIREMENTS
DBB Read
(Ta= 0-70°C, VCC=5V±10%,unlessotherwisenoted)
Parameter
Symbol
Alternative
symbol
tc( ¢)
Cycle time
tCY
tw (R)
Read pulse with
tRR
tSU(CS-R)
Chip·select setup time before read
th(R-CS)
Chip-select hold time after read
Limits
Unit
Test conditions
Min
Typ
2.5
Max
15
jJ.S
250
ns
tAR
0
ns
tRA
0
ns
tc(¢)=2.5jJ.s
DBB Write
Parameter
Symbol
Limits
AI ternative
symbol
Unit
Test conditions
Min
Typ
Max
tW(W)
Write pulse width
tww
250
ns
t~~?~;-=-:~V
t~?~=~;l
ES, Ao
setup time before write
tAW
0
ns
CS, Ao
hold tie after write
ns
tWA
0
tSU(OQ-W)
Data setup time before write
tow
150
ns
th(W-DQ)
Data hold time after write
two
0
ns
Port 2
Parameter
Symbol
Limits
Alternative
symbol
Unit
Test conditions
Min
Typ
Max
tW(PR)
PROG pulse width
tpp
1200
ns
tSU(PC-PR)
Port control setup time before PROG
tcp
110
ns
th(PR-PC)
Port control hold time after PROG
tpc
100
ns
tSU(Q-PR)
OL;tput data setup time before PROG
top
250
ns
tSU(D-PR)
Irput data hold time before PROG.
tPR
th(PR-D)
Input data hold time after PROG
0
tPF
810
ns
150
ns
DMA
Symbol
Parameter
Limits
AI ternative
symbol
Unit
Test conditions
Min
Typ
Max
tSU(DACK-R)
Data acknowledge time before read
tACC
0
ns
th(R-DAOK)
Data hold time after read
tCAC
0
ns
tsu(DAOK-W)
Data setup time before write
tACC
0
ns
th(W-DAOK)
Data hold time after write
tCAC
0
ns
SWITCHING CHARACTERISTICS (Ta = 0-70°C, Vcc=5V±1O%, unless otherwise noted)
DBB Read
Symbol
Parameter
AI terr,ative
symbol
CS
Limits
Test conditions
Unit
Min
Typ
Max
tpZX(CS-OQ)
Data enable time after
tAO
CL=150pF
225
ns
tpZX(Ao-DQ)
Data enable time after address
tAO
CL = 150pF
225
ns
tPZX(R-DQ)
Data enable time after read
tRD
CL = 150pF
225
ns
tPXZ(R-DQ)
Data disable time after read
tOF
100
ns
DMA
Symbol
Parameter
AI ternative
symbol
Limits
Unit
Test conditions
Min
Typ
Max
PZX(DAOK-DQ
Data enable time after DACK
tACO
150pF Load
225
ns
PHL(R-DRQ)
ORO disable time after read
tCRQ
150pF Load
200
ns
PHL(W-DRQ)
ORO disable time after write
tCRQ
150pF Load
200
ns
•
8-36
MITSUBISHI
.... ELECTRIC
MITSUBISHI LSls
MSL 8041A-XXXP
UNIVERSAL PERIPHERAL INTERFACE
TIMING DIAGRAMS
Read
lK
)~
CS, Ao
th (R- C3)
tSU(CS-R)
tSU(Ao-R)
j~
tW(R)
l
,~
RO
tPZX(R-DQ)
m~
00-07
~
tPXZ(R-DQ)
1
~
VALID DATA
tPZX(Ao DQ) tPZX(CS-DQ)
Write
CS, AO
SU(AO-W)
tsu(CS-W)
tW(W)
WR
00-07
Port 2
SYNC
I
,'--_ _--J/
_---I
II
''---
,'--_ _--J/
SU(D-PR
EXPANDER paR T
OUTPU T
)
P20-P23 DATA
PORT CONTROL
11
~UTPUT
EXPANDER po RT
INP UT
)
P20-P23 DATA
,
tSU(D PR)~
I
pbRT CONTROL
K
DATl
~
th(PR-D)
~11-
If
J
INPUT DATA
th(PR-PC)
t su (PC-P'1)
tW(PR)
PROG
DMA
II
1
,
~
,
,
tSU(DACK R)
tw(R)
1
I
~
th(R DACK)
-I
,
th(W-DACK)
tSU(DACK-W)
I
tw(w)
-
"
00-07
I I
tpZX( DAC~- DQ)
ORQ
ut~~DI
U
• MITSUBISHI
.... ELECTRIC
8-37
MITSUBISHI LSls
MSL 8041A-XXXP
UNIVERSAL PERIPHERAL INTERFACE
APPLICATION EXAMPLES
(1) Interface to an M5L8085AP
M5L8041 A
-xxxp
000- 007
S
PERIPHERAL
DEVICES
Ao
M5L8085AP
C/)
:::>
Control
aJ
R
~
C/)
C/)
aJ
~
W
III
';;;
"0
"0
«
0
000- 007
Ao- A7
(2) Interface to an MELPS 8-48 Microcomputer and M5L8243P
R
R
W
W
\ S
Port
000- 007
PROG
PROG
4
P20-P23
8
M5L8243P
000- 007
M5L8041 A
-XXXP
MELPS8-48
Microcomputer
P20- P23
Ao
P24- P27
4
PlO- P17
8
~
~
~
~.
.
r
To
T,
8-38
• MITSUBISHI
..... ELECTRIC
PERIPHERAL
DEVICES
MITSUBISHI LSls
MSL 8041A-XXXP
UNIVERSAL PERIPHERAL INTERFACE
GENERAL INFORMATION
EPROM SPECIFICATIONS
This information explains how to specify the object
program for the automatic design system for mask ROMs.
This system for mask ROM production has been developed
to accept a customer's object program specifications for the
automatic design system for a mask ROM.
1. The Mitsubishi M5L2708K, M5L2716K, M5L2732K or
M5L8748S are standard, but Intel 2708, 2716, 2732,
8741 or 8441 A or equivalent devices may be used.
2. The high-level data of both data outputs and address
inputs of the supplied EPROM will be programmed as
'1', and low-level as 'a'.
The main segments of he automatic design system are:
1. The plotter instructions for mask production.
2. A check list for verifyng that the customer's specifications have been met.
3. A test program to assure that the production ROMs
meet specifications.
An EPROM in which a program is stored is used for a
customer's specifications. A separate (set of) EPROM(s)
should be produced for each object program.
Three sets of EPROM(s) should be supplied with the
confi rmation material.
CONFIRMATION
SHEET
FROM CUSTOMER
3. All the data stored in the EPROM are considered as valid
and processed to make masks.
ITEMS FOR VERIF.ICATION
The type of EPROM and address designation symbol A
should be marked on the top of the EPROM. In addition,
the address indicated by the symbol A should be indicated
on the ROM verification sheet.
MITSUBISHI ELECTRIC
MASK ROM
AUTOMATIC
DESIGN PROGRAM
OBJECT
PROGRAM
GENERATION '--~_-I
LARGE
TESTER
• WATER
TEST
• FINAL
TEST
t - - - - - - - I . QA TEST
• MITSUBISHI
"ELECTRIC
8-39
MITSUBISHI MICROCOMPUTERS
MSL 8041A-XXXP
UNIVERSAL PERIPHERAL INTERFACE
MASK-PROGRAMMABLE ROM CONFIRMATION MATERIAL
M5L8041 A-XXXP
MASK VERIFICATION SHEET
MITSUBISHI ELECTRIC
Signature
Customer
Company name
*
Prepared
Company address
Tel
Company contact
Date
Approved
1. Speoify the EPROM to be supplied.
(0
Supply 3 EPROMs of eaoh pattern
EPROM Type
EPROM No.
* 2.
2708
OA(00016~3FF16)
"/"
2716
DA(00016~3FF16)
2732
DA(00016~3FF16)
Part No.
1. Marking required
2. Marking required
MITSUBISHI ELECTRIC IC TYPE NO.
Note 1. Justify the marking to the right.
2. Keep the length to within 12 oharaoters, inoluding alphamerios and
hyphens. Do not use J, I, or O.
*
*
3. Special Remarks
4. Desoription of the final produot (In as much detail as possible)
• MITSUBISHI
..... ELECTRIC
8741
8741 A
OA(00016~3FF16)
MITSUBISHI LSls
M5L8251AP
PROGRAMMABLE COMMUNICATION INTERFACE
DESCRIPTION
PIN CONFIGURATION (TOP VIEW)
The M5L 8251AP is a universal synchronous/asynchronous
receiver/transmitter (USART) IC chip designed for data
communications use. It is produced using the N-channel
02"" 1
silicon-gate ED-MaS process and is mainly used in combina-
BIDIRECTIONAL
DATA BUS
tion with 8-bit microprocessors.
RECEIVERi~~G~
RxO
(DV)
Vss
FEATURES
•
•
Single 5V power supply
Synchronous and asynchronous operation
Synchronous:
BIDIRECTIONAL
DATA BUS
1
BIDIRECTIONAL
} DATA BUS
03"" 2
(5V)
-+ 3
RECEIVERCLOCK INPUT
DATA-TERMINAL
READY OUTPUT
REOUEST- TOSEND OUTPUT
DATA-SET
READY INPUT
RESET INPUT
I
l
T~~~~t<'I;~~0\
5""'8-bit characters
CLOCK INPUT
CON'1~gLEi2~~~
I nternal or external synchronization
19 -+
CHIP-Sr~~8t
Automatic SYNC character insertion
18 -+ TxEMPTY
~g~t~g~PN'i>T6'T
cONNtfi2~~~
Asynchronous system:
READ~E601{~~T
5""'8-bit characters
TxO
17 +-
RO
-+ 13
16 ....
CTS
b~~~So~nO~~~Alt~~~~~~-T
~~~'6Ri~~UT
~6NDET/ ~A~XKD6H~t+
RxRDY +- 141...-_ _ _ _...J 15 -+ TxRDY
~~~~~~~~~~-T
Clock rate-1, 16 or 64 times the baud rate
1, 1%, or 2 stop bits
Outline 28P4
False-start-bit detection
Automatic break-state detection
The M5L8251AP receives parallel-format data from the
•
•
Baud rate: DC""'64K-baud
Full duplex, double-buffered transmitter/receiver
CPU, converts it into a serial format, and then transmits
•
Error detection: parity, overrun, and framing
via the T xD pin. It also receives data sent in via the RxD
•
Pin connection and electrical characteristics compatible
with Intel's 8251A
parallel format for sending to the CPU.
Modem control of data communications using micro-
On receipt of parallel-format data for transmission from
the CPU or serial data for the CPU from external devices,
computers
the M5L 8251AP informs the CPU using the T xRDY or
APPLICATIONS
•
•
Contro!9f CRT, TTY and other terminal equipment
RxRDY pin. In addition, the CPU can read the M5L
8251AP status at any time.
FUNCTIONT
pin from the external circuit, and converts it into a
The M5L 8251AP can detect the data received for
M5L 8251AP is used in the peripheral
errors and inform the CPU of the presence of errors as
operations in all the currently
status information. Errors include parity, overrun and
systems including IBM's 'bi-sync.'
frame errors.
TRANSMITTER-DATA OUTPUT
BIDIRECTIONAL DATA BUS
DATA
BUS
BUFFER
TRANSMITTER-READY OUTPUT
TRANSMITTER-EMPTY OUTPUT
TRANSMITTER-CLOCK INPUT
CLOCK INPUT
CONTROL/DATA -cO~~~8f
READ-DATA CONTROL INPUT
WRITE-DATA CONTROL INPUT
RxO
RECEIVER-DATA INPUT
CHIP-SELECT INPUT
DATA-SET READY INPUT
RECEIVER-READY OUTPUT
DATA-TERMINAL READY INPUT
RECEIVER-CLOCK INPUT
CLEAR-TO-SEND INPUT'
16 SYNDET/BD SYNC DETECT/BREAK DETECT
REOUEST- TO-SEND OUTPUT
•
MITSUBISHI
"'ELECTRIC
8
41
II
:
MITSUBISHI LSls
M5L8251AP
PROGRAMMABLE COMMUNICATION INTERFACE
OPERATION
Table 1 M5L8251AP Access Methods
The M5L 8251AP interfaces with the system bus as shown
0/5
RD
WR
in Fig. 1, positioned between the CPU and the modem or
L
L
L
H
H
terminal equipment, and offers all the functions required
for data communication.
Fig.1 M5L8251AP interface to 8080A standard system bus
ADDRESS BUS
16
OS
Function
H
L
Data bus +- Data in USART
L
L
USART +- Data bus
L
H
L
Data bus +- Status
H
H
L
L
Control +- Data bus
X
H
H
L
3-State +- Data bus
X
X
X
H
3 -State +- Data bus
AO
CONTROL BUS
l70R VOW RESET
4
8
Data-Bus Buffer
¢2(TTU
This is an 8-bit, 3-state bidirectional bus buffer through
which control words, command words, status information,
DATA BUS
and transfer data are transferred.
structure of the data-bus buffer.
8
.,
'1
c/o cs
00-07 RO
WR RESET
elK
Fig. 2 Data-bus-buffer structure
M5L8251AP
~'r07
Do
When using the M5L 8251AP, it is necessary to program,
Do
as the initial setting, assignments for synchronous/asynchro-
system
used.
Once
programming
I
STATUS BUFFER
I
H
nous mode selection, baud rate, character length, parity
check, and even/odd parity selection in accordance with the
communication
Fig. 2 shows the
RECEIVE-DATA BUFFER
H
Lf
is
completed, functions appropriate to the communication
system can be carried out continuously.
When initial setting of the USART is completed, data
I
TO INTER NAL DATA BUS
r
I--
CONTROL BUFFER
~
TRANSMIT-DATA
BUFFER
~
I-
communication becomes possible. Though the receiver is
always in the enable state, the transmitter is placed in the
transmitter-enable state (T xEN) by a command instruction,
and the application of a low-level signal to the CTS pin
prompts data-transfer start-up. Until this condition is
satisfied, transmission is not executed. On receiving data,
the receiver informs the CPU that reading of the receiver
data in the USART by the CPU has become possible (the
RxRDY terminal has turned toT).
Since data reception
and the entry of the CPU into the data-readable state are
output as status information, the CPU can assess USART
status without accessing the RxRDY terminal.
During receiving operation, the USART checks errors
and gives out status information. There are three types of
errors: parity, overrun, and frame. Even though an error
occurs, the USART continues its operations, and the error
state is retained until error reset (ER) is effected by a
command instruction. The M5L 8251AP access methods
are listed in Table 1.
Read/Write Control Logic
This logic consists of a control word register and command
word register. It receives signals from the CPU control bus
and generates internal-control signals for the elements.
Modem Control Circuit
This is a general-purpose control-signal circuit designed to
simplify the interface to the modem. Four types of control
signal are available: output signals DTR and RTS are
controlled by command instructions, input signal DSR is
given to the CPU as status information and input signal
CTS controls direct transmission.
Transmit Buffer
This buffer converts parallel-format data given to the databus buffer into serial data with addition of a start bit, stop
bits and a parity bit, and sends out the converted data
through the TxD pin based on the control signal.
Transmit-Control Circuit
This circuit carries out all the controls required for serialdata transmission. It controls transmitter data and outputs
the signals required by external devices in accordance with
the instructions of the read/write control logic.
8 . 42
• MITSUBISHI
'-.ELECTRIC
MITSUBISHI LSls
M5L8251AP
PROGRAMMABLE COMMUNICATION INTERFACE
Receive Buffer
Write-Data Control Input (WR)
This buffer converts serial data given via the RxD pin into a
Data and control words output from the CPU by the low-
parallel format, checks the bits and characters in accordance
level input are written in the M5l 8251AP. This terminal is
with the communication format designated by mode setting,
and transfers the assembled characters to the CPU via the
usually used in a form connected with the control bus
I/OW of the CPU.
data-bus buffer.
Read-Data Control Input (RD)
Receive Control Circuit
Receiver data and status information are output from the
This circuit offers all the controls required for normal
CPU by a low-level input for the CPU data bus.
reception of the input serial data. It controls receiver data
Control/Data Control Input (C/O)
and outputs signals for the external devices in accordance
This signal shows whether the information on the USART
with the instructions of the read/write control logic.
data bus is in the form of data characters or control words,
Clock Input (ClK)
or in the form of status information, in accordance with
This system-clock input is required for internal-timing
the RD and WR inputs while the CPU is accessing the
generation and is usually connected to the clock-output
M5L8251AP. The high level identifies control words or
status information, and the low level, data characters.
(¢2(TIL)) pin of the M5L 8224P.
Although there is no
direct relation with the data-transfer baud rate, the clock-
Request-To-Send Output (RTS)
input (ClK) frequency is more than 30 times the T xC
This is a general-purpose output signal but is used as a
or RxC input frequency in the case of the synchronous
request-to-send signal for the modem. The RTS terminal
system and more than 4.5 times in the case of the asynchro-
is controlled by the Ds bit of the command instruction.
nous system.
When Ds is equal to '1', RTS = l, and when D3 is 0, RTS
Reset Input (RESET)
= H.
Once the USART is shifted to the idle mode by a high-level
input, this state continues until a new control word is set.
Since this is a master reset, it is always necessary to load a
control word following the reset process. The reset input
Command register Ds = 1 ~ RTS = l
Command register Ds = 0 ~ RTS = H
Note: RTS controls the modem transmission carrier as
follows:
ON means carrier dispatch;
OFF means carrier stop.
requires a minimum 6-clock pulse width.
Data-Set Ready Input (DSR)
This is a general-purpose input signal, but is usually used as
Clear-To-Send Input (CTS)
a data-set ready signal to test modem status. Its status can
be known from the status reading process. The D7 bit of
When the T xEN bit (Do) of the command instruction has
the status information equals '1' when the DSR pin is in
the low state, and '0' when in the high state.
DSR = l
~
been set to T and the CTS input is low, serial data is sent
out from the T xD pin. Usually this is used as a clear-tosend signal for the modem.
D7 bit of status information = 1
Note: CTS indicates the modem status as follows:
DSR = H ~ D7 bit of status information = 0
ON means data transmission is possible;
OFF means data transmission is impossible.
Note: DSR indicates modem status as follows:
ON means the modem can transmit and receive;
OFF means it cannot.
Transmission-Data Output (TxD)
Parallel-format transmission characters loaded on the M5l
Data-Terminal Ready Output (DTR)
8251AP by the CPU are assembled into the format desig-
This is a general-purpose output signal, but is usually used
as a data-terminal ready or rate-select signal to the modem.
nated by the mode instruction and sent in serial-data form
via the T xD pin. Data is output, however, only in cases
The DTR pin is controlled by the D 1 bit of the command
where the Do bit (T xEN) of the command instruction is
instruction; if Dl
= 1, DTR = l, and
if Dl
= 0,
D 1 of the command register
= 1 ~ DTR = l
Dl of the command register
= 0 ~ DTR = H
DTR
= H.
'1' and the CTS terminal is in the low state. Once reset, this
pin is kept at the mark status (high level) until the first
character is sent.
Chip-Select Input (CS)
Transmitter-Ready (T xRDY)
This is a device-select signal that enables the USART
This signal shows that the data is ready for transmission.
by a low-level input. Usually, it is connected to the address
It is possible to confirm the status of serial-data transmis-
bus directly or via the decoder. When this signal is in the
sion by using it as an interruption signal for the CPU or
high state, the M5l 8251AP is disabled.
by allowing the CPU to read the Do bit of the status
information by polling. Since the T xRDY signal shows that
• MITSUBISHI
.... ELECTRIC
8-43
MITSUBISHI LSls
MSL8251AP
PROGRAMMABLE COMMUNICATION INTERFACE
the data buffer is empty, it is automatically reset when a
transmission character is loaded by the CPU. The T xRDY
bit of the status information means that the transmit-data
buffer shown in Fig. 2 has become empty, while the
T xRDY pin enters the high-level state only when the
transmit-data buffer is empty, T xEN equals '1', and a lowlevel input has been applied to the CTS pin.
Status (Do): Transmit-data buffer (TDB) is empty and T.
TxRDY terminal: When (TDB is empty)' (TxEN = 1)'
(CTS = 0) = 1 or resetting, it becomes
active.
Transmitter-Empty Output (TxEMPTY)
When no transmisison characters are left in the transmit
buffer, this pin enters the high state. In the asynchronous
mode, the following transmission character is shifted to
the transmit buffer when it is loaded from the CPU. Thus,
it is automatically reset. In the synchronous mode, a SYNC
character is loaded automatically on the transmit buffer
when no transfer-data characters are left. In this case,
however, the T xEMPTY does not enter the low state when
a SYNC character has been sent out, since T xEMPTY = H
denotes the state in whjch there is no transfer character
and one or two SYNC characters are being transferred or
the state in which a SYNC character is being transferred as
a filler. T xEMPTY is unrelated to the T xEN bit of the
command instruction.
Transmitter-Clock Input (TxC).
This clock controls the baud rate for character transmission
from the T xD pin. Serial data is shifted by the rising edge
of the T xC signal. In the synchronous mode, the T xC
frequency is equal to the actual baud rate. In the asynchronous mode, the frequency is specified as 1, 16, or 64 times
the baud rate by the mode setting.
Example
When the baud rate is 110 bauds:
TxC= 110Hz (lX)
TxC = 1.76kHz (16X)
T xC = 7.04kHz (64X)
Receiver-Data Input (RxD)
Serial characters sent from another device are input to this
pin and converted to a parallel-character format to serve as
data for the CPU. Unless the '1' state is detected after a
chip-master reset procedure (this resetting is carried out to
prevent spurious operation such as that due to faulty
connection of the RxD to the line in a break state), the
serial characters are not received. This applies to only the
asynchronous mode. When the RxD line enters the low
state instantaneously because of noise, etc., the mis-start
prevention function starts working. That is, the start bit is
detected by its falling edge but in order to make sure that it
8 ····44
is the correct start bit, the RxD line is strobed at the middle
of the start bit to reconfirm the low state. If it is found to
be high, a faulty-start judgment is made.
Receiver-Ready Output (RxRDV)
This signal indicates that the received characters have
entered the receiver buffer, and further, the receiver-data
buffer in the data-bUS buffer shown in Fig. 2. It is possible
to confirm the RxRDY status by using this signal as an
interruption signal for the CPU or by allowing the CPU to
read the Dl bit of the status information by polling. The
RxRDY is automatically reset when a character is read by
the CPU. Even in the break state in which the RxD line is
held at low, the RxRDY remains active. It can be masked
by making the RxE (D 2 ) of the command instruction '0'.
Receiver-Clock Input (RxC)
This clock signal controls the baud rate for the sending in
of characters via the RxD pin. The data is shifted in by
the rising edge of the RxC signal. In the synchronous mode,
the RxC frequency is equal to the actual baud rate. In the
asynchronous mode, the frequency is specified as 1, 16, or
64 times the baud rate by mode setting. This relationship is
parallel to that of T xC, and in usual communication-line
systems the transmission and reception baud rates are
equal. The T xC and RxC terminals are, therefore, used
connected to the same baud-rate generator.
Sync Detect/Break Detect Output-Input
(SVNDET /BD)
In the synchronous mode this pin is used for input and
output operations. When it is specified for the internal
synchronous mode by mode setting, this pin works as an
output terminal. It enters the high state when a SYNC
character is received through the RxD pin. If the M5L
8251AP has been programmed for double SYNC characters
(bi-sync), a high is entered in the middle of the last bit of
the second SYNC character. This signal is automatically
reset by reading the status information.
On designation of the M5L8251AP to the external
synchronous mode, this pin begins to serve for input operations. Applying a high signal to this pin prompts the M5L
8251AP to begin assembling data characters at the next
rising edge of the RxC. For the width of a high-level signal
to be input, a minimum RxC period is required.
Designation of the asynchronous mode causes this pin
to function as a BD (output) pin. When the start, data,
and parity bits and a stop bit are all in the low state, a high
is entered. The BD (break detect) signal can also be read as
the D6 bit of the status information. This signal is. reset
by resetting the chip master or by the RxD line's recovering
the high state.
• MITSUBISHI
..... ELECTRIC
MITSUBISHI LSls
M5i..8251AP
PROGRAMMABLE COMMUNICATION INTERFACE
PROGRAMMING
Fig. 4 Mode-instruction format
It is necessary for the M5L 8251AP to have the control
SINGLE CHARACTER SYNC
word loaded by the CPU prior to data transfer. This must
always be done following any resetting operation (by
external RESET pin or command instruction IR). There are
two types of control words: mode instructions specifying
EXTERNAL SYNC DETECT
general operations required for communications and comEVEN PARITY
mand instructions to control the M5L 8251AP's actual
operations.
Following the resetting operation, a mode instruction
PARITY ENABLE
must be set first. This instruction sets the synchronous or
asynchronous system to be used. In the synchronous
system, a SYNC character is loaded from the CPU. In the
case of the bi-sync system, however, a second SYNC
character must be loaded in succession.
Loading a command instruction makes data transfer
possible. This operation after resetting must be carried out
for initializing the M5L 8251AP. The USART command
instruction contains an internal-reset I R instruction (D6
bit) that makes it possible to return the M5L 8251AP to
its reset state. The initialization flowchart is shown in Fig.
3, and
the mode-instruction and command-instruction
formats are shown in Figs. 4 and 5.
PARITY
PARITY ENABLE
r-------.II
Fig. 3 Initialization flow chart
EVEN PARITY
~--------------~
Fig. 5 Command-instruction format
l
EH l l R
IRTSI ER ISBRKIRxEloTRITxENI
,~
TxENABLE
(C/O=l,
WR=O)
I
TRANSM'SS'ON ENABeE
l-ENABLE
O=DISABLE
DATA
TERMINAL
~
1
DATA-TERMINAL READY
l~DTR=O
Rx ENABLE
I
-,
SEND BREAK
1=ENABLE
O=DISABLE
J SEND BREAK CHARACTER
I
ERROR RESET
RECEIVER ENABLE
l-+TxO=LOW
II
1
I ERROR RESET
Ill-CLEAR ALL ERROR FLAG
IPE. OE. FE)
I
REQUEST TO SEND
I
'l TRANSMISSION-CARRIER
CONT~
,I
l~RTS=O
INTERNAL RESET
~NTER
HUNT MODE
• MITSUBISHI
.... ELECTRIC
-' INTERNAL RESET
I
l->TO INITIALIZATION
I
1
IENTER HUNT MODE
'I l-+ENABLE SEARCH FOR
SYNC CHARACTERS
8-45
MITSUBISHI LSls
M5L8251AP
PROGRAMMABLE COMMUNICATION INTERFACE
Asynchronous Transmission Mode
When data characters are loaded on the M5L 8251AP after
initial setting, the USART automatically adds a start bit
(low), an odd or even parity bit specified by the mode
instruction during initialization, and a specified number of
stoP bits (high). After that, the assembled data characters
are transferred as serial data via the T xD pin if transfer is
enabled (T xEN = 1·CTS = L). In this case, the transfer data
(baud rate) is shifted by the mode instruction at a rate of
1X, 1/16X, or 1/64X the TxC period.
If the data characters are not loaded on the M5L
8251AP, the TxD pin enters a mark state (high). When
SBR K is programmed by the command instruction, break
characters (low) are output continuously through the
TxD pin.
Asynchronous Reception Mode
The RxD line usually starts operations in a mark state
(high), triggered by the falling edge of a low-level pulse
when it comes to this line. This signal is again strobed at
the middle of the bit to confirm that it is a perfect start bit.
The detection of a second low indicates the validity of the
start bit (restrobing is carried out only in the case of 16X
and 64X). After that, the bit counter inside the M5L
8251AP starts operating; each bit of the serial information
on the RxD line is shifted in by the rising edge of RxC,
and the data bit, parity bit (when necessary), and stop bit
are sampled at the middle position.
The occurrence of a parity error causes the setting of a
parity-error flag. If the stop bit is in the low state, a frameerror flag is set. Attention should be paid to the fact that
the receiver requires only one stop bit even though the
program has designated 1% or 2 stop bits.
Reception up to the stop bit means reception of a
complete character. This character is then transferred to the
receiver-data buffer shown in Fig. 2, and the RxRDY
Fig. 6 Asynchronous transmission format I (transmission)
becomes active. In cases where this character is not led by
the CPU and where the next character is transferred to the
receiver-data buffer, the precedi ng character is destroyed
and an overrun-error flag is set.
These error flags can be read as the M5L 8251AP status
information. The occurrence of an error does not stop
USART operations. The error flags are cleared by the ER
(D 4 bit) of the command instruction.
The asynchronous-system transfer formats are shown in
Figs. 6 and 7.
Synchronous Transmission Mode
In this mode the TxD pin remains in the high state until
initial setting by the CPU is completed. After initialization,
the state of CTS = Land T xEN = 1 causes serial transmission of SYNC characters through the T xD pin. Then, data
characters are sent out and shifted by the falling edge of the
T xC signal. The transmission rate equals the T xC rate.
Thus, once data-character transfer starts, it must continue through the T xD pin at the same rate as that of
T xC. Unless data characters are provided from the CPU
before the transmitter buffer becomes empty, one or two
SYNC characters are automatically output from the T xD
pin. In this case, it should be noted that the TxEMPTY pin
enters the high state when there are no data characters left
in the M5L 8251AP to be transferred, and that the low
state is not entered until the USART is provided with the
next data character from the CPU. Care should also be
taken over the fact that merely setting a command instruction does not effect SYNC-character insertion, because
the SYNC character is sent out after loading of the data
characters.
In this mode, too, break characters are sent out in
succession from the T xD pin when SB R K is designated
(D 3 = 1) by a command instruction.
Fig. 7 Asynchronous transmission format II (reception)
CPU-> USART (5-8 BITS/CHARACTER)
RECEIVER INPUT (RxD)
~~RACTER
STbPI
BI~S.."
(1.15.2)
ASSEMBLED DATA FORMAT
START
BIT
DATA CHARACTER (5-8)
PARITY
BIT
STO~
BITS
(1.1 5.2)
RECEIPTION FORMAT
I
DATA~BITS
(5-8)
I
USART -> CPU (5-8 BITS/CHARACTER)
TRANSMITIER DATA OUTPUT (TxD)
ST6Pl
L....:..--L--_-'.:.-...,r-_---L-"-~
PARITY STr BIT
BIT
(1.15.2)
L-
Brf.LL-
DATA
(1 .15.2)
CHARA~TER (5-8)
Note. When the data character is 5. 6. or 7 bits/character length.
the unused bits (for USART - CPU) are set to zero.
8-46
• MITSUBISHI
..... ELECTRIC
MITSUBISHI LSls
MSL82S1AP
PROGRAMMABLE COMMUNICATION INTERFACE
Synchronous Reception Mode
is reset each time status information is read irrespective of
Character synchronization in this mode is carried out
the synchronous mode's being internal or external. This,
internally or externally by initial-setting designation.
however, does not return the M5L 8251AP to the hunt
Programming in the internal synchronous mode requires
mode. Synchronism detection is carried out even though it
that an EH instruction (0 7 = 1, enter hunt mode) is
is not the hunt mode. The synchronous transfer formats
are shown in Figs. 8 and 9.
included in the first command instruction. Data on the
RxD pin is sampled by the rising RxC signal, and the
Command Instruction
receiver-buffer contents are compared with the SYNC
This instruction defines actual operations in the communi-
character each time a bit is input. Comparison continues
cation mode designated by mode setting. Command instruc-
until an agreement is reached. When the M5L 8251AP has
tions
been programmed in the bi-sync mode, data received in
further succession is compared. The detection of two
internal-reset,
include
transmitter/receiver
modem-control,
enable
enter-hunt
error-reset,
and
break
transmission instructions.
SYNC characters in succession makes the USART end the
The mode is set following the reset operation. A SYNC
hunt mode, setting the SYNDET pin to the high state.
This reset operation is prompted by the reading of the
character is set as required, and the writing of high-level
signals on the control/data pin (C/O) that follows it is
status information. When the parity has been programmed,
regarded as a command instruction. When the mode is set
SYNDET is not set in the middle of the last data bit but in
all over again from the beginning, the M5L 8251AP can be
the middle of the parity bit.
reset by using inputting via the reset terminal or by internal
In the external synchronous mode, the M5L 8251AP
gets out of the hunt mode when a high synchronization
resetting based on the command instruction.
Note 1: The command error reset (ER), internal reset (IR)
signal is given to the SYNDET pin. The high signal requires
and enter-hunt-mode (EH) operations are only
a minimum duration of one RxC cycle. In the asynchronous
effective when the command instruction is loaded,
mode, however, the EH signal does not affect the operation
at all.
Parity and overrun errors are checked in the same way
so that these bits need not be retu rned to '0'.
2: When a break character is sent out by a command,
as in the asynchronous system. During hunt-mode opera-
the T xD enters the low state immediately irrespective of whether or not the USART has sent out
tions the parity bit is not checked, but parity checking is
data.
carried out even when the receiver is disabled.
3: Operations of the USART's receiver section which
The CPU can command the receiver to enter the hunt
is always in the enable state cannot be inhibited.
a does not mean
mode, if synchronization is lost. This prevents the SYNC
The command instruction RxE =
character from erroneously becoming equal to the received
that data reception via the RxD pin is inhibited;
data when all the data in the receiver buffer is set to '1'
it means that the RxRDY is masked and error flags
Attention should be paid to the fact that the SYN DET F IF
are inhibited.
Fig. 8 Synchronous transmission format I (transmission)
Fig. 9 Synchronous transmission format II (reception)
CPU--> USART (5-8 BITS/CHARACTER)
I
DATA
SERIAL INPUT DATA (RxDI
C~~RACTER I
USART --> CPU (5-8 BITS/CHARACTER)
ASSEMBLED TxD OUTPUT
87ARACTER
Note: When the data character is 5. 6. or 7 bits/character length.
the unused bits (for USART - CPU) are set to zero.
• MITSUBISHI
"ELECTRIC
8-47
II
:
MITSUBISHI LSls
MSL8251AP
PROGRAMMABLE COMMUNICATION INTERFACE
Status Information
The occurrence of a frame error in the receiver
FE:
section makes the status information FE "'.
The CPU can always read USART status by setting the
C/O to '1' and RD to '0'.
The status information format is shown in Fig. 10. In
OE:
The occurrence of an overrun error in the receiver
this format RxRDY, TxEMPTY and SYNDET have the
PE:
section makes the status information OE "'.
The occurrence of a parity error in the receiver
section makes this status information PE "'.
same definitions as those of the pins. This means that these
pin is in the high state. The other status information is
TxRDY: This information becomes '" when the transmitdata buffer is empty. Be careful because th is has
defined as follows:
DSR:
When the DSR pin is in the low state, status
a different meaning from the T xRDY pin that
enters the high state only when the transmitter
three pieces of status information become ,,' when each
buffer is empty, when the CTS pin is in the low
information DSR becomes "'.
state, and when T xEN is "'.
Fig. 10 Status information
l
OSR
06
Ds
ISYD~TI
FE
I
OE
I
PE
I
00
02
TxE I
R~DYITXRDYI
I
(C/D=1
T
RO=O)
1 FOR TRANSMIT DATA BUFFER IS EMPTY
SAME DEFINITION AS RxRDY PIN
SAME DEFINITION AS TxEMPTY PIN
PE IS SET WHEN A PARITY ERROR IS DETECTED IT IS RESET BY THE ER BIT OF THE
COMMAND INSTRUCTION PE DOES NOT INHIBIT OPfRATION OF THE 8251A.
OE IS SET WHEN THE CPU DOES NOT READ A CHARACTER BEFORE THE NEXT ONE
BECOMES AVAILABLE. IT IS RESET BY THE ER BIT OF THE COMMAND INSTRUCTION
OE DOES NOT INHIBIT OPERATION OF THE 8251A.
FE IS SET WHEN A VALID STOP BIT IS NOT DETECTED AT THE END OF EVERY CHAROF THE COMMAND INSTRUCTION.
~fb~E~~6~CI~~Mt d~EI~A~r8~To~\mE8~~1~T
SAME DEFINITION AS SYNDET/BD PIN
1 FOR DSR=LOW-LEVEL. 0 FOR DSR=HIGH-LEVEL
APPLICATION EXAMPLES
T xEN being equal to '1 '. For this reason the same defini-
Fig. 11 shows an application example for the M5L 8251AP
tion applies to the status and pin of T xRDY, and '1' is
in the asynchronous mode. When the port addresses of the
assigned when the transmit-data buffer is empty. Actual
M5L 8251AP are assumed to be 00# and 01# in this figure,
transfer of data is carried out in the following way:
initial setting in the asynchronous mode is carried out in
the following manner:
MVI
A,
OUT
01 #
MVI
A,
OUT
01 #
IN
The
86#
Mode setting
27#
Command instruction
01
#
Status read
I N instruction prompts the CPU to read the
USART's status. The result is: if the T xRDY equals '1'
transmitter data is sent from the CPU and written on the
M 5L 8251AP.
Transmitter data is written in the M5L
8251AP in the following manner:
In this case, the following are set by mode setting:
20 #
MVI
A,
OUT
00#
Asynchronous mode
6 bits/character
Parity enable (even)
IN
1% stop bits
~
00
#
(A) +- USART
I n the above example, the status information is read and
as a result, the transmitter data is written and read. Interruption processing by using the T xRDY and RxRDY pins
= 1 ~ RTS pin = L
RxE = 1
DTR = ,
USART+- (A)
Receiver data is read in the following manner:
Baud rate: 16X
Command instructions set the following:
RTS
2D 16 is an example of
transmitter data.
is also possible.
Fig. 12 shows the status of the TxD pin when data
DTR pin = L
TxEN = 1
When the initial setting is complete, transfer operations are
written in the USART is transferred from the CPU. When
the data shown in Fig. 12 enters the RxD pin, data sent
allowed. The RTS pin is initially set to the low-level by
from the M5L 8251AP to the CPU becomes 2D'6 and bits
D6 and D7 are treated as '0'.
setting RTS to ',', and th is serves as a CTS input with
8-48
• MITSUBISHI
.... ELECTRIC
MITSUBISHI LSls
MSL8251AP
PROGRAMMABLE COMMUNICATION INTERFACE
Fig.11 Example of circuit using the asynchronous mode
rD~
!
XTAl1
XTAl2
RESIN
BAUD RATE
GENERATOR
(DIVIDER)
RDYIN
L:;
TO TRANSMISSION LlNE{
140
to(;)-90
ns
tW«(I»
Clock low pulse width
t~
tr
Clock rise time
tR
5
20
tf
Clock fall time
tF
5
20
ns
kHz
kHz
kHz
hx
DC
64
16 X baud rate
hx
DC
310
64 X baud rate
f TX
DC
615
Transmitter input clock low
lX baud rate
tTPw
12
t e( (1))
pulse width
16X, 64X baud rate
tTPW
1
te( (1))
Transmitter Input clock high
lX baud rate
tTpo
15
pulse width
16X, 64X baud rate
tTpo
3
lX baud rate
f RX
DC
64
16X baud rate
fRX
DC
310
DC
615
frequency
tW(TPWL)
tW(TPWH)
Receiver input clock
fRX
frequency
tW(RPWL)
tW(RPWH)
ns
1 X baud rate
Transmitter Input clock
fTx
ns
90
te«(I»
te( (1))
kHz
kHz
kHz
64X baud rate
f RX
Receiver Input clock low
lX baud rate
tRPW
12
pulse width
16X, 64X baud rate
tRPW
1
Receiver input clock high
lX baud rate
tRPO
15
te( (1))
pulse width
16X, 64X baud rate
tRPO
3
te( (1))
te«(I»
te( (1))
tSU(A~R)
Address setup time before read (CS, C/D) (Note 3)
tAR
50
ns
th(R~A)
Address hold time after read (CS, C/D) (Note 3)
tRA
50
ns
tW(R)
Read pulse width
tRR
250
ns
tSU(A-W)
Address setup time before write
tAW
50
ns
thew-A)
Address hold time after write
tWA
50
ns
tw(W)
Write pulse width
tww
250
ns
tSU(DQ~W)
Data setup time before write
tow
150
ns
th(W-OQ)
Data hold time after write
two
50
ns
tSU(ESD-RxC)
E·SYNDET setup time before RxC
tES
16
te( (1))
tSU(O~R)
Control setup time before read
tOR
20
te( (1))
tRV
Write recovery time between writes (Note 4)
tRV
6
te( (1))
tSU(RxD-IS)
RxD setup time before internal sampltng pulse
tSRx
2
I1S
th(IS~RxO)
RxD hold time after internal sampling pulse
tHRx
2
I1S
Note
: The TxC and RxC frequencies have the following limitations with respect to ClK.
For lX baud rate fTx,
fRx;:;;;;1I(30tO«(I»)' For 16X, 64X baud rate fTx,
fRX;:;;;;1/(4,5tO«(I»)
: Reset pulse width=6 to( (1)) minimum; system clock must be running during reset
3 .
CS, C/D are considered as address.
4 . This recovery time is for mode initialization only. Write data is allowed only when TxRDY=l.
Recovery time between writes for asynchronous
mode is 8 to( (1)), and that for synchronous mode is 16 to( (1))
SWITCHING CHARACTERISTICS
Symbol
(Ta= 0 -70·C,
Voo= 5 V± 5
%, Vss= 0 V, unless otherwise noted)
Alternative
Parameter
Limits
Test conditions (Note 7)
symbol
PZV(R-DQ)
Output data enable time after read (Note 5)
tRO
PVZ(R-DQ)
Output data disable time afer read
tDF
PZV(TxC- TxD) TxD enable time after falling edge of TxC
Min
CL = 150pF
tOTx
Propagation time from write data to TxRDY (Note 6)
trxRDY CLEAR
PLH(CLB-RxR) Propagation time from center of last bit to RxRDY (Note 6)
PHL(R-RxR)
Propagation time from read data to RxRDY clear (Note 6)
tiS
PLH(CLB- TxE) Propagation time from center of last bit to TxEMPTY (Note 6)
PHL(W-C)
Note
tRx ROY
tRxRDY CLEAR
PLH(RxC- SYD) ~l?~6~~tTN'oi~m6) from rising edge of RxC to internal
Propagation time from rising edge of WR to control (Note 6)
tTxEMPTY
two
Max
250
10
PLH(CLB- TxR) Propagation time from center of last bit to TxRDY clear (Note 6) tTxRO Y
PHL(W-TxR)
Unit
Typ
ns
100
ns
1
I1S
8
te«(I»
6
t ey
24
te«(I»
6
t ey
24
te«(I»
20
te«(I»
8
te«(I»
5 . Assumes that· address is valid before failing edge of RD.
2V
6 . Status-up data can have a maximum delay of 28 clock periods from the event affecting the status.
0.45-2.4V
Reference level Input
420Q
Input pulse rise time
20ns
Output VIH= 2 V, VIL =0.8 V
Input pulse fall time
20ns
load·
VOH = 2 V, VOL = 0.8 V
FROM OUTPUT OF 0-.....-+----0 OUT
M5L8251AP
7 : Input pulse level
:::=X.;;;~.:,;;;8_____....;;.0_.:C
6kQ
•
MITSUBISHI
.... II!:LII!:CTRIC
II
MITSUBISHI LSls
MSL82S1AP
PROGRAMMABLE COMMUNICATION INTERFACE
TIMING DIAGRAMS
System Clock (ClK)
CLK
Transmitter Clock & Data
TxC( lX)
TxC( 16X)
TxD
Receiver Clock & Data
Rx-BIT COUNTER STARTS HERE
RxD
DATA BIT
START BIT
tW(RPWL)
tW(RPWH)
RXC(16X)
INTERNAL
SAMPLING
PULSE
tsu (RxO IS)
8-52
th(IS-Rx O)
• MITSUBISHI
.... ELECTRIC
DATA
BIT
MITSUBISHI LSls
M5L8251AP
PROGRAMMABLE COMMUNICATION INTERFACE
Write Control Cycle (CPU - USART)
X
tpHL(W~C)
tw(W)
1
~
tSU(DQ~W)
00-07
(DATA IN)
X
DONT CARE
X
DATA STABLE
t!SU(A~W)
c/B
~th(W~DQ)
th(W~A)
tSU(A~W)
~
th(W~A)_
I
\
-1-
t-
Read Control Cycle
DON'T CARE
II
(USART~PU)
X
tSU(C-R)
tW(R)
~
~
j
tpVZ(R~DQ)
tpZV(R~DQ)
r
1///
f\\\
00-07
(DATA OUT)
L
c/o
,
DATA VALID
tSU(A~R)
~tSU(A~R)
cs
t-
•
MITSUBISHI
. . . . I!:LI!:CTRIC
~~\\
1/
th(R-A~t.
th(R-A)
~
I
J
MITSUBISHI LSls
MSL82S1AP
PROGRAMMABLE COMMUNICATION INTERFACE
Write Data Cycle (CPU~ USART)
,
TxROY
tPHL~
tw(w)
,...
WR
l
tSU(DQ-W)
00-07
(DATA IN)
~-DQ)
l-
,
\:
l~h(W~A)
tSU(A-W)
~
0/0
X
DATA STABLE
DON'T CARE
~
~
f-
,
ts~
os
th(W-A)
~
~
t
1r-
Read Data Cycle (USART ~ CPU)
RxROY
tPHL~
tw(W)
~
)'
RO
l
tPZV(R-OQ)
~
00-07
(DATA OUT)
0/0
,
,
/11
\\\
tSU(A-R)
I~(R-~)
~
tSU(A-R)
~
8 -- 54
\\\
11/
jr-
t
os
DATA VALID
OZ(R-OQ)
• MITSUBISHI
.... ELECTRIC
th( R-A)
~
j
~
DON'T CARE
MITSUBISHI LSls
M5L8251AP
PROGRAMMABLE COMMUNICATION INTERFACE
Transmitter Control & Flag Timing (Async Mode)
CTS
TxEMPTY
TxROY
(STATUS)
TxROY
(PIN)
c/o
WR
TxO
DATAl
Note
8: Example format = 7 bits/character with parity & 2 stop bits.
9 : TxRDY (pin) = 1 +- (Transmit-data buffer is empty) . (TxEN = 1) . (CTS =0) =1
10 : TxRDY (status) = 1 +- (Transmit-data buffer is empty) = 1
Receiver Control & Flag Timing (Async Mode)
~
SO
(PIN)
~
OE
(STATUS)
LOST
'In
RxROY
tpLH( CLB-RxR)
I
R-D DATA 3
RID DATA 1
c/o
-1
\
/ ~
/
\
I~
\
J
W\JE
\J
~u
J
RxO
\SIaX 1X2X3X4XSX6XP{STP\s/aX1X2X3X4XSX6XP{STP\s/aX 1X2X3X4XSX6XP/STR
DATA 1
Note 11 : Example format
=7
W l
y
WRJA
WRRxE
DATA 2
DATA 3
BREAK STATE
S 1 2 3 4 5 6 P STP
bits/character with parity & 2 stop bits
• MITSUBISHI
.... ELECTRIC
8-55
MITSUBISHI LSls
M5L8251AP
PROGRAMMABLE COMMUNICATION INTERFACE
Transmitter Control &. Flat Timing (Sync Mode)
---,
~------------------~~
,....~
TxEMPTY
1\
~
TxRDY
(STATUS)
~
'~
TxRDY
(PIN)
~~~1~1r----+~________4~1~__~-+~________________-+__-*
c/o
______~\~n~~/~--~,\~/~--~I~\~/~_+~--~1
WR ~ATA 1 WR DATA 2
-~I
WR 9ATA 3
fiI--+\-----+--.1 ~
MARK STATE
WRSBRK WR DATA 5
~~--t-------'ur-uhJr-++-----+----
\011 X213141PloX1X2I3X4~ 'I01112J.3X4FIOX1X21314lPXOXlX21314xPI01112l3l41P{
DATA 1
DATA 2 SYNC CH1 SYNC CH2 DATA 3 DATA 4
TxD
\\~\~L~---r-----
L-J
WRSBRK
WR DATA 4
MARK
STATE
BREAK
STATE
MARK
STATE
0111213141PloI112l~4lPXoX
DATA 5 SYNC CHl
SYNC CH2
Note 12 : Example format = 5 bits/character with parity. bi-sync characters.
Receiver Control &. Flag Timing (Sync Mode)
SYNDET
(PIN)
INTERNAL SYNC MODE
r
I
r-r-<
V
OE
(STATUS)
r~
~L,
DATA 2
LOST
.---1
II
\
\
r,-
''-------"
J
-
'
r
1\
WR EH, RxE
'~ ~~
\...
\
r----
\
'WR EH
WR ER
UI
\J
RDSYNC
RD DATA 1 RD STATUS
1r1J
llY
RD
RD
STATUS
-1JUS
J1IlIlJUl
L EXITS
HUNT MODE
SYNDET SET
Note 13 : Example format = 5 bits/character with parity. bi-sync characters.
• MITSUBISHI
.... ELECTRIC
RD DATA 1
\,1
IxXxXxXx XXXXOX1X213X4HoI112X314) 10l1X2X3I4J 10l1X213X4) tol1X2X3X4) tOl1X2X3X4) toX1X2X3X4) IXXXXxXxXxXxXxJ
SYNC CHl SYNC CH~ ! DATA 1
DATA 2 :.1.' DATA 3 SYNC CHl i SYNC CH2.1.
CHARACTER ASSEMBLY BEGINS
:r-
8-56
~
DATA 2
LOST
RxRDY
(PIN)
RxD
--
tSU(ESD-RxC)'
tpLH (RxC-SYD)
II
SYNDET
(STATUS)
c/o
EXTERNAL
SYN C
MODE
tXXXIX!
Ol1X2X3X41 tOXl ~4»
I DATA 1
DATA 2 I
.nt fuut
EXITS HUNT MODE
SYNDET SET (STATUS)
~
SYNDET SET
(STATUS)
MITSUBISHI LSls
MSL82S3P-S
PROGRAMMABLE INTERVAL TIMER
DESCRIPTION
The M5L8253P-5 is a programmable general-purpose timer
PIN CONFIGURATION (TOP VIEW)
device developed by using the N-channel silicon-gate
ED-MOS process. It offers counter and timer functions in
systems using an 8-bit parallel-processing CPU. The use of
07++ I
the M5L 8253P frees the CPU from the execution of looped
Vee
06 ++ 2
programs, count-operation programs and other simple
processing
involving
many
repetitive operations, thus
contributing to improved system throughputs. The M5L
READ INPUT
CHIP-SELECT
INPUT
BIDIRECTIONAL
DATA BUS
) ADDRESS
INPUTS
8253P-5 works on a single power supply, and both its input
CLOCK INPUT
COUNTER
OUTPUT
GATE INPUT
and output can be connected to a TTL circuit.
FEATURES
•
•
M5L 8253P-5 is suitable for use with MELPS 85
3 independent built-in 16-bit down counters
•
•
Clock period: DC-2MHz
6 counter modes freely assignable for each counter
CLOCK INPUT
COUNTER
OUTPUT
GATE INPUT
(OV)
(5V)
WRITE INPUT
CLOCK INPUT
GATED --+ 11
GATE INPUT
COUNTER
OUTPUT
GNO
Outline 24P1
•
Binary or decimal counts
•
•
Single 5V power supply
Pin connection and electric characteristics compatible
with Intel's 8253
APPLICATIONS
Delayed-time setting, pulse counting and rate generation
in microcomputers.
II
FUNCTION
Three independent 16-bit counters allow free programming
based on mode-control instructions from the CPU. When
roughly classified, there are 6 modes (0-5). Mode 0 is
mainly used as an interruption timer and event counter,
mode 1 as a digital one-shot, modes 2 and 3 as rate gene-
rators, mode 4 for a software triggered strobe, and mode
5 for a hardware triggered strobe.
The count can be monitored and set at any time. The
counter operates with either the binary or BCD system.
BLOCK DIAGRAM
. I
(5V)
(Ov)
vee~
9 ClKO
GNO$
CLOCK INPUT
11 GATED GATE INPUT
BIDIRECTIONAL DATA BUS
DATABUS
BUFFER
10 OU TO
COUNTER OUTPUT
15 ClK1
CLOCK INPUT
14 GATE1 GATE INPUT
13 OUT1
COUNTER OUTPUT
READ INPUT
WRITE INPUT
CHIP-SELECT INPUT
16 GATE2 GATE INPUT
READ/
WRITE
LOGIC
17 OUT2
COUNTER OUTPUT
INTERNAL
DATA BUS
• MITSUBISHI
.... ELECTRIC
8-57
MITSUBISHI LSls
MSL8253p·S
PROGRAMMABLE INTERVAL TIMER
Chip-Select Input (CS)
DESCRIPTION OF FUNCTIONS
Data-Bus Buffer
A low-level on this input enables the M5L8253P-5. Changes
in the level of the CS input have no effect on the operation
This 3-state, bidirectional, 8-bit buffer is used to interface
the M5L8253P-5 to the system-side data bus. Transmission
of the counters.
and reception of all the data including control words for
mode designation and values written in, and read from, the
counters are carried out through this buffer.
Control-Word Register
This register stores information required to give instructions
a bout operational modes and to select binary or BCD
counting. Unlike the counters, it allows no reading, only
Read/Write Logic
The read/write logic accepts control signals (RD, WR) from
the system and generates control signals for each counter.
It is enabled or disabled by the chip-select signal (CS);
writing.
Counters 0, 1 and 2
These counters are identical in operation and independent
of each other. Each is a 16-bit, presettable, down counter,
and has clock-input, gate-input and output pins. The
counter can operate in either binary or BCD using the failing edge of each clock. The mode of counter operation and
the initial value from which to start counting can be desig-
if CS is at the high-level the data-bus buffer enters a floating
(high-impedance) state.
Read Input (RD)
The count of the counter designated by address inputs
Ao and Al on the low-level is output to the data bus.
nated by software. The count can be read by input instruction at any time, and there is a "read-on-the-fly" function
Write Input (WR)
Data on the data bus is written in the counter or controlword register designated by address inputs Ao and Alan
the low-level.
which enables stable reading by latching each instantaneous
count to the registers by a special counter-latch instruction.
Address Inputs (Ao, AI)
These are used for selecting one of the 3 internal counters
and either of the control-word registers.
Table 1 Basic Functions
8-58
CS
RD
WR
At
Ao
0
1
0
0
0
0
1
0
0
1
Data bus -+ Counter 1
0
1
0
1
0
Data bus -+ Counter 2
0
1
0
1
1
Data bus -+ Control-word register
0
0
1
0
0
Data bus
+-
Counter 0
0
0
1
0
1
Data bus
+-
Counter 1
0
0
1
1
0
Data bus
+-
Counter 2
0
0
1
1
1
3-state
1
X
X
X
X
3-state
0
1
1
X
X
3-state
• MITSUBISHI
.... ELECTRIC
Function
Data bus -+ Counter 0
MITSUBISHI LSls
MSL82S3P-S
PROGRAMMABLE INTERVAL TIMER
CONTROL WORD AND INITIAL-VALUE LOADING
The function of the M5L8253P-5 depends on the system
software. The operational mode of the counters can be
specified by writing control words (Ao, Al = 1, 1) into the
control-word registers.
Table 2 Control-Word Format
o7
06
05
04
03
0 2
01
Do
SCl
sca
RL 1
RLa
M2
Ml
Ma
BCD
~SC----+----R~----+-------M--------~BCO~
The programmer must write out to the M5L8253P-5 the
programmed number of count register bytes (1 or 2) prior
to actually using the selected counter.
• SC (Select Counter)
SCl
sca
4 fields. Only the counter selected by the D7 and D6 bits
0
0
Select counter 0
of the control word is set for operation. Bits Ds and D4 are
0
1
Select counter 1
used for specifying operations to read values in the counter
1
0
Select counter 2
and to initialize. Bits D3"'DI are used for mode designa-
1
1
Prohibited combination
Table 2 shows control-word format, which consists of
tion, and Do for specifying binary or BCD counting. When
Do
= 0,
binary counting is employed, and any number
from 0000 16 to FFFF 16 can be loaded into the count
register. The counter is counted down for each clock. The
• RL (Read/Load)
counting of 0000 16 causes the transmission of a time-out
PL 1
RLO
The maximum number of counts is obtained when
0
0
Operation
0000 16 is set as the initial value. When Do = 1, BCD count-
0
1
Read/load low·order 8 bits only
ing is employed, and any number from 000010 to 999910
1
0
Read/load high-order 8 bits only
can be loaded on the counter.
1
1
Read/load low-order 8 bits and then high-order 8 bits
signal from the count-output pin.
Neither system resetting nor connecting to the power
supply sets the control word to any specific value. Thus
to bring the counters into operation, the above-mentioned
control words for mode designation must be given to each
.M (Mode)
counter, and then 1"'2 byte initial counter values must be
M2
Ml
MO
set. The following is an example of this programming step.
0
a
a
Mode 0
To designate mode 0 for counter 1, with initial value
a
a
1
Mode 1
8253 16 set by binary count, the following program is used:
X
1
a
Mode 2
X
1
1
Mode 3
1
a
a
Mode 4
1
a
1
Mode 5
MVI
A, 7016
Control word 70 16
OUT
MVI
nl
n1 is control-word-register address
A, 5316
Low-order 8 bits
n 2 is counter 1 address
OUT
MVI
n2
A,8216
High-order 8 bits
OUT
n2
n 2 is counter 1 address
Thus, the program generally has the following sequence:
(1) Control-word output to counter i (j
(2)
= 0, 1, 2).
.SCD
Binary counter (16 bits)
I nitialization of low-order 8 counter bits
Binary-coded decimal counter (4 decades)
(3) I nitialization of high-order 8 counter bits
The three counters can be executed in any sequence. It is
possible, for instance, to designate the mode of each
counter and then load initial values in a different order.
Initialization of the counters designated by RL 1 and RLO
must be executed in the order of the low-order 8 bits and
then the high-order 8 bits for the counter in question.
• MITSUBISHI
..... ELECTRIC
8-59
MITSUBISHI LSls
M5L8253P-S
PROGRAMMABLE I,.TERVAL TIMER
MODE DEFINITION
Mode 0 (Interrupt on Terminal Count)
Mode set and initialization cause the counter output
to go low-level (see Fig. 1). When the counter is loaded with
an initial value, it will start counting the clock input. When
the terminal count is reached, the output will go high and
remain high until the selected count register is reloaded
with the mode, This mode can be used when the CPU is
to be interrupted after a certain period or at the time of
counting up.
Fig. 1 shows a setting of 4 as the initial value. If gate
input goes low, counting is inhibited for the duration of
the low-level period.
Reloading of the initial value during count operation will
stop counting by the loading of the first byte and start the
new count by the loading of the second byte.
Mode 1 (Programmable One-Shot)
The gate input functions as a trigger input. A gate-input
rising edge causes the generation of low-level one-shot
output with a predetermined clock length starting from the
next clock. Fig. 2 shows an initial setting of 4. While the
counter output is at the low-level (during one-shot), loading
of a new value does not change the one-shot pulse width,
which has already been output. The current count can be
read at any time without affecting the width of the
one-shot pulse being output. This mode permits retriggering.
Mode 2 (Rate Generator)
Low-level pulses during one clock operation are generated
from the counter output at a rate of one per n clock inputs
(where n is the value initially set for the counter). When a
new value is loaded during the counter operation, it is
reflected on the output after the pulses by the current
count have been output. In the example shown in Fig. 3,
n is given as 4 at the outset and is then changed to 3.
In this mode, the gate input provides a reset function.
While it is on the low-level, the output is maintained high;
the counter restarts from the initial value, triggered by a
rising gate-input edge. This gate input, therefore, makes
possible external synchronization of the counter by
hardware.
After the mode is set, the counter does not start counting until the rate n is loaded into the count register, with
the counter output remaining at the high-level.
Mode 3 (Square Rate Generator)
This is similar to Mode 2 except that it outputs a square
wave with the half count of the set rate. When the set value
n is odd, the square-wave output will be high for (n + 1 )/2
clock-input counts and low for (n - 1 )/2 counts. When a
8-60
new rate is reloaded into the count register during its operation, it is immediately reflected on the count directly
following the output transition (hig~-to-Iow or low-to-high)
of the current count. G'ate-input operations are exactly
the same as in Mqde 2. Fig. 4 shows an 'example of Mode
,
3 operation.
Mode 4 (Software Triggered Strobe)
After the mode is set, the output
~e high. By loading a
number on the counte'r, however,: clock~input counts can
be started and on ,the terminal cou'nt, th~ output will go
low for one input-clock period and' then 'will go high again.
Mode 4 differs from Mode 2 in that pulses are not output
repeatedly with the same set' c9unt. The pulse output is
delayed one clock period in Mode 2, as shown in Fig. 5.
When a new value is loaded into the: count register during
its count operation, it is reflec~ed on the next pulse output
without' affecting the current ,~ount. The' count will be
inhibited while the gate input is low-level.
Mode 5 (Hardware Triggered Strobe)
This is a variation of Mode 1. The gate input provides a
trigger function, and the count is start~d by its rising edge.
On the terminal count, the counter output goes low for on
one clock period and then goes high. As in Mode 1, retriggering by the gate input is possible. An example of timing
in Mode 5 is shown in Fig. 6.
As mentioned above, the gate input plays different roles
according to the mode. The functions are summarized in
Table 3.
will
Table 3 Gate Operations
~
Low or going low
Rising
High
Mode
0
(1) Initiates counting
(2) Resets output
after next clock
1
2
(1) Disables counting
(2) Sets output high
immediately
3
(1) Disables counting
(2) Sets output high
immediately
4
Disables counting
5
• MITSUBISHI
..... ELECTRIC
Enables
counting
Disables counting
Initiates counting
Enables
counting
Initiates counting
Enables
counting
Enables
counting
Initiates counting
MITSUBISHI LSls
MSL8253p·S
PROGRAMMABLE INTERVAL TIMER
Fig.1 Mode 0
Fig. 4 Mode 3
eLK'
WR('r1~
.
4
3
2
11
OUT(GATE="H"):
:
i
WR~
GATE----------:I
OUT ________
r-~'----------------
~'------'
~!
:3
________ ________
~,
~
Fig. 2 Mode 1
Fig. 5 Mode 4
eLK
WR(n~
G'AT E, _-------"
OUT
L..J
GATE
4
3
0
OUT--------~----~~~--~~~
Fig. 6 Mode 5
eLK
4
LJ
OUT(n=4)
__.;....~______..;........;;.......;;2~1
4
U
3
2
1
4
GATE~~_ _~
4
3
3
~
432
OUT(n-4)
COUNTER MONITORING
Read-on-the-Fly Operation
Sometimes the counter must be monitored by reading its
This method makes it possible to tead the current count
count or using it as an event counter. The M5L8253P-5
without affecting the count operation at all. A special
offers the following two methods for count reading:
counter-latch command is first written in the control-word
Read Operation
register. This causes latching of all the instantaneous counts
The count can be read by designating the address of the
counter to be monitored and executing a simple I/O read
to the register, allowing retention of stable counts. An
example of a program to execute this operation for counter
operation. I n order to ensure correct reading of the count,
2 is given below.
= D4
latching
it is necessary to cause the clock input to pause by external
logic or prevent a change in the count by gate input. An
MVI A, 1 OOOXXXX· •.. Ds
example of a program to read the counter 1 count is shown
below. If R L1, R LO = 1, 1 has been specified in the control
OUT
IN
n1 .... n1 is the control-word-register address
n3 is the counter 2 address
MOV D, A
to be read and the second I N instruction enables the highorder 8 bits.
IN
n2' ...
n2 is the counter 1 address
n3
MOV E, A
In this example, the I N instruction is executed twice. Due
MOV D, A
IN
designates counter
n3' ...
word, the first I N instruction enables the low-order 8 bits
IN
=0
to the internal logic of the M5L8253P-5 it is absolutely
essential to complete the entire reading procedure. If two
n2
MOV E, A
bytes are programmed to be read, then two bytes must be
The IN instruction should be executed once or twice by
the RL1 and RLO designations in the control-word register.
read before any OUT instruction can be executed to the
same counter.
• MITSUBISHI
.... ELECTRIC
8-61
MITSUBISHI LSI.
MSL82S3P-S
PROGRAMMABLE INTERVAL TIMER
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Vee
Power supply voltage
VI
Input voltage
Vo
Output voltage
Conditions
With respect to GND
Pd
Maximum power dissipation
Topr
Operating free-air temperature range
Tstg
Storage temperature range
Limits
Unit
-0.5-7
V
-0.5-7
V
-0.5-7
V
1000
Ta=25"C
mW
0-70
"C
-65-150
"C
RECOMMENDED OPERATING CONDITIONS
limits
Parameter
Symbol
Unit
Min
Nom
Max
4.75
5
5.25
Vee
Power supply voltage
GND
Supply voltage
VIH
High-level input voltage
2.2
Vee
V
VIL
Low-level input voltage
-0.5
0.8
V
0
ELECTRICAL CHARACTERISTICS
V
V
(Ta=0-70"C, Vee=5V±5%. unless otherwise noted.)
limits
Symbol
Parameter
Test conditions
Unit
Min
Typ
Max
VOH
High-level output voltage
GND=OV
(Note 1)
VOL
Low-level output voltage
GND= OV
(Note 2)
0.45
V
IIH
High-level input current
GND=OV, VI=5.25V
±10
/-LA
IrL
Low-level input current
GND=OV, VI=OV
±10
/-LA
IOZ
Olf-state output current
GND=OV,
±10
/-LA
lee
Power supply current
GND= OV
140
mA
Oi
Input capacitance
VIL=GND, f= 1MHz, 25mVrms, Ta=25"C
10
pF
Oilo
Input/output capacitance
VI/OL=GND, f= 1MHz,25mVrms,Ta=25"C
20
pF
8-62
VI=O-Vee
• MITSUBISHI
.... ELECTRIC
2.4
V
MITSUBISHI LSls
MSL82S3P-S
PROGRAMMABLE INTERVAL TIMER
TIMING REQUIREMENTS
Read Cycle
(Ta=0-70"C.
Vcc=SV±S%. GND=OV. unless otherwise noted.) (Note 3)
Alternative
Limits
Test condition
Parameter
Symbol
Unit
symbol
Min
Typ
Max
tW(R)
Read pulse width
tRR
300
ns
tSU(A-R)
Address setup time before read
tAR
50
ns
th(R-A)
Address hold time after read
tRA
S
ns
tree (R)
Read recovery time
tRY
1000
ns
CL=lS0pF
Write Cycle
Alternative
Parameter
Symbol
symbol
Limits
Unit
Test condition
Min
Typ
Max
tw(W)
Write pulse width
tww
300
ns
tsu(A-W)
Address setup time before write
tAW
50
ns
theW-A)
Address hold time after write
tWA
30
ns
tsu(OQ-W)
Data setup lime before write
tow
2S0
ns
th (W-DQ)
Data hold time after write
two
30
ns
tRY
1000
ns
CL=lS0pF
tree (W)
Write recovery time
Clock and Gate Timing
Limits
Alternative
Symbol
Parameter
Test condition
Unit
Min
symbol
Typ
Max
ns
tw (qlH)
Clock high pulse width
tPWH
230
tw(qlL)
Clock low pulse width
tPWL
150
tc(qI)
Clock cycle time
tCLK
380
tw(GH)
Gate high pulse width
tGW
150
ns
tw(GL)
Gate low pulse width
tGL
100
ns
tsu(G-ql)
Gate setup time before clock
tGS
100
ns
th(qI-G)
Gate hold time after clock
tGH
SO
ns
CL=1S0pF
ns
DC
ns
Note 3 : Test conditions: MSL 82S3P : CL = 1 OOpF. MSL 8253P-5 : CL = lS0pF
• MITSUBISHI
;"ELECTRIC
8-63
II
MITSUBISHI LSls
MSL82S3P-S
PROGRAMMABLE INTERVAL TIMER
SWITCHING CHARACTERISTICS'(Ta,=0-70"C. Vcc'=5V±5%. Vss=OV,
unless otherwise noted,) (Note
Alternative
Symbol
Test condition
symbol
Propagation time from
tPXZ(R-DQ)
Propagation time from read to output floating
tDF
tPZX(G-DQ)
Propagation time from gate to out~ut
PZX(~-DQ)
Propagation time from 'clock to output
Note
~ead
to output
.
J..imits
Parameter
tPZX(R-DQ)
4)
, Typ
Min
'"
"
. Max
200
tRD
25
ns
tODG
300
' ns'
tOD
400
ns
CL=150pF
(Reference yottage!; High
,
= 2.2V,
i..ow
,
= O,8V)
tsu (A-R)
D7--Do.~- ---~-~-~ -
-
-
th (R-A)
--~tPZX(R-DQ)
Write Cycle
)(
At. Ao. CS
~K
~,
~
~
tsu (A-W)
)<:
:K
th (W-DQ)
tsu(DQ-W)
;,l~
~c
tw(W)
Clock and Gate Cycle
CLK
GATE
-------------------------'
OUT
tpZX(G-DQ)
8-64
ns
100
4: Test conditions: M5L 8253P': CL=100pF. M5L 8253P-5: CL=150pF
TIMING DIAGRAMS
Read Cycle'
Unit
• MITSUBISHI
.... ELECTRIC
I
MITSUBISHI LSls
MSL 8255AP-5
PROGRAMMABLE PERIPHERAL INTERFACE
DESCRIPTION,
PIN CONFIGURATION (TOP VIEYV)
This is a family of general-purpose programmable input/
output devices designed for use with the M5L 8085A 8-bit
parallel CPU as input/output ports. These devices are .'
fabricated using N-channel silicon-gate ED-MOS technolo,-,
INPUT /OUTPUT
PORT A
gy ·for a single suppl,y voltage. They ar'esimple input and
,
output interfaces!f?r TTL "circuits, having24 input/output.
pins which crorrespo~d to three 8-bit input/output ports.'
PAl" 3
PAo .. 4
READ INPUT
RD--. 5
CHip SELECT
CS--.
6
35
-RESET
PORT ADDRESS
,INPUTS
24 prograr,nmable 1/0 pil')s
• Single 5V supply ~oltage,
• TTL-compatible tOL ~ 2.5mA (max)
• Fully compatible. with MELPS 8' microprocessor series
•
Direct bit set/reset capability.
•
Interchangeable with Intel'~ 8255A in terms of
function, electrical characteristics' and pin configuration
. B)-DIRECTIONAL
DATA BUS
INPUT /OUTPUT
PORT C
Vert, (5V)
. 25
~.PB7
.
24 .. PB·& .
, .
APPLICATION
•
RESET INPUT
(OV) GND
FEATURES
•
1:::: ~
INPUT/OUTPUT
PORT B .
Input/output ports for ME LP~ 8/85 microprocessor
FUNCTION
These PPls have 24 input/outPl.!t pins which may· be
individually programmed in two 12-bit groups A and .s
Outline 40P1
with mode control commands from a CPU. They are used
in three major modes of operation, mode 0, mode 1 and
mode 2.
co~trol
or output, and one 4-bit
port used for handshaking
and interrupt control signals. Mode 2 is used with group A
only, as one 8-bit bidirectional bu~ port and one 5-bit
control port.
Operating in mode 0, each group of 12 pins may be
programmed in sets of 4 to be inputs or outputs. In mode 1,
the 24 I/O terminals may be programmed in two 12-bit
Bit set/reset is controlled by CPU. A high-level reset
groups, group A and group B. Each group contains one 8bit data port, which may be programmed to serve as input
BLOCK
DIAGRAM
input (R ESET) clears all internal registers, and all ports
are set to the input mode (high-impedance state).
, ' - - - ' - - - - - - - - - - - - - - - - - - - ---.~
~.
37 PA 7
(5V) Vee 26
GROUP
(Ov) GND 7
GROUP
A
38 PA6
1 - - -_ _-\...39 'PA 5
40 PA4 INPUT/OUTPUT
t-------'..1 PA 3 PORT A
1 - - - - - - { 2 PA2
t - - - - - - { 3 PA I
_ _ _.--Jr-----14 PA 0
A
CONTROL
PORT A
(8-BIT)
L
DATA BUS
INPUT /OUTPUT
PORT C
8-BIT
INTERNAL
DA TABUS I---I--+-.J
READ INPUT R D 5
WRITE INPUT W R 36
GROUP
GROUP
ADDRESS ( A 1 8
INPUTS
.
Ao 9
LOGIC
PORT B
CONTROL
INPUT /OUTPUT
PORT B
(8-BIT)
RESET INPUT RES E T 35
______________________________ ..-J.
CHIP SELECT CS 6 } - - - - - - "
• MITSUBISHI
"ELECTRIC
8-65
I!II
IiII
MITSUBISHI LSI.
MSL 82SSAP-S
PROGRAMMABLE PERIPHERAL INTERFACE
FUNCTIONAL DESCRIPTION
Data Bus Buffer
This three-state, bidirectional, eight-bit buffer is used to
transfer the data when an input or output instruction is
executed by the CPU. Control words and status information are also transferred through the data bus buffer.
Read/Write Control Logic
The function of this block is to control transfers of both
data and control words. It accepts the address signals (Ao,
At, CS) from the CPU, I/O control bus outputs (RD, WR)
from the system controller, and RESET signals, and then
issues commands to both of the control groups in the PPI.
CS (Chip-Select) Input
At low-level, the communication between the PPI and the
CPU is enabled. While at high-level, the data bus is kept in
the high-impedance state, so thqt commands from the CPU
are ignored. Then the previous data is kept at the output
port.
RD (Read) Input
At low-level, the status or data at the port is transferred to
the CPU from the PPI. In essence, it allows the CPU to read
data from the PPI.
WR (Write) Input
At low-level, the data or control words are transferred from
the CPU and written in the PPI.
be divided into two 4-bit ports which can be used as ports
for control signals for port A and port B.
The basic operations are shown in Table 1.
Table 1 Basic Operations
Al
Ao
CS
RO
WR
0
0
0
0
1
0
1
0
0
1
0
0
0
0
0
0
0
1
1
0
1
Operation
Data bus
+-
Port A
1
Data bus
+-
Port B
1
Data bus
+-
Port C
1
0
Port A
+-
Data bus
0
1
0
Port B
+-
Data bus
0
1
0
Port C
+-
Data bus
1
0
1
0
Control register
X
X
1
X
X
Data bus is in high-impedance state.
1
1
0
0
1
Illegal condition
Bit Set/Reset
When port C is used as an output port, anyone bit of the
eight bits can be set (high) or reset (low) by a control word
from the CPU. This bit set/reset can be operated in the
same way as the mode set, but the control word format is
different. This operation is also used for INTE set/reset in
mode 1 and mode 2.
Fig. 1 Control word format for port C set/reset
Bit set! reset flag
I
I
Act;ve =0
Don't care
Bit selection code
Port C
Bit selected
RESET (Reset) Input
At high-level, all internal registers, including the control
register, are cleared. Then all ports are set to the input
mode (high-impedance state).
r--v
1071061051041031021011001
Port A, Port Band· Port C
The PPI contains three 8-bit ports whose modes and input/
output settings are programmed by the system software.
Port A has an output latch/buffer and an input latch.
Port B has an I/O latch/buffer and an input buffer. Port C
has an output latch/buffer and an input buffer. Port C can
8-66
Data bus.
Where, "0" indicates low level
"1" indicates high level
Ao, A1 (Port Address) Input
These input signals are used to select one of the three ports:
port A, port 8, and port C, or the control register. They
are normally connected to the least significant two bits of
the address bus.
Group A and Group B Control
Accepting commands from the read/write control logic, the
control blocks (Group A, Group B) receive 8-bit control
words from the internal data bus and issue the proper
commands for the associated ports. Control group A is
accociated with port A and the four high-order bits of port
C. Control group B is associated with port B and the four
low-order bits of port C. The control register, which stores
control words, can only be written into.
+-
• MITSUBISHI
r..ELECTRIC
03 02 01
PC7
1
1
1
PCG
1
1
0
PC5
1
0
1
PC4
1
0
0
PC3
0
1
1
PC2
0
1
0
PCl
0
0
1
PCo
0
0
0
Set/reset code
Set (high)
= 1
Reset (low) = 0
MITSUBISHI LSls
MSL 82SSAP-S
PROGRAMMABLE PERIPHERAL INTERFACE
BASIC OPERATING MODES
The PPI can operate in anyone of three selected basic modes.
Mode 0: Basic input/output
(group A, group B)
Mode 1: Strobed input/output
(group A, group B)
Mode 2: Bidirectional bus
(group A only)
The mode of both group A and group B can be selected
D7DsDsD4 D3D2D,Do
D7DsDs D4D3D2D1Do
independently. The control word format for mode set is
11101010101011101
11101010101011111
shown in Fig. 2.
Fig. 2 Control word format for mode set .
. - - - - - - - - - - - Mode set flag
I Active ~ 1
PA7-PAO
, - - - - - - - Group A mode set
Mode 0 : D s. D S = o. 0
Mode 1 : D s . D s = O. 1
Mode 2: D s. D s = 1. X
D7 DSDs D 4 D 3D2D1Do
D7DsDsD4D3D2D,Do
11101010111010101
11101010111010111
, . . . . - - - - - Port A input!output set
output - 0
_ Input = 1
I
I
. - - - - - Port C (high-order four bits) input/output set
output - 0
_ Input = 1
.
I
r-'
~
!r;
Group B mode set
I
Mode 0
Mode 1
=0
=1
D7 DSDsD4D3D2D1DO
I
D7 DSDsD4D3D2D1Do
11101010111011101
I
I
[ 1 10 10 0 11 10 11 11
Port B input! output set
~ Port C (low-order four bits) input/output set
I
II
ID 71 D siDsID41 D31D21D llDol
output - 0
input = ~
I
II
PA7-PAo
D7 DSDs D 4 D 3D2D1DO
D7 DSDs D4D3D2D1Do
11101011101010101
11101010101010111
1. Mode 0 (Basic Input/Output)
This functional configuration provides simple input and
D7DsDSD4 D3D2D1DO
output operations for each of the three ports. No "hand-
11101011101011101
D7Ds D S D 4D3D2D1Do
I
I
11 10 0 111 0 0 11 11
I
shaking" is required; data is simply written in, or read from,
the specified port. Output data from the CPU to the port
can be held, but input data from the port to the CPU
cannot be held. Anyone of the 8-bit ports and 4-bit ports
can be used as an input port or an output port. The diagrams
following show the basic input/output operating modes.
D7 DSDsD4D3D2D1Do
D7DsDsD4D3D2D1Do
11101011111010101
111010111dolol11
D7DsDs D4D3D2D,Do
D7 DSDsD4 D3D2D1Do
D7DsDsD4 D 3D2D1Do
11101010101010101
11101010101010111
11 10 10 11 1110 11 10
• MITSUBISHI
"ELECTRIC
I
D7DSDsD4D3D2D1Do
I
I
11 10 0 11 11 10 0 11
I
8-67
MIT5UBISHI LSls
MSL' 82SSAP·S
PROGRAMMAB.LE PERIPHERAL INTERFACE
2. Mode 1 (Strobed.lnput/Output)
This function can be set in both group A and· B. Both
groups are composed of one 8-bit data port and one 4-bit
control data port. The 8-bit port can be used as an input
port or an output port. The 4-bit port is used for control
and status signals affecting the 8-bit data port. The following shows operations in mode 1 for using input ports.
STB (Strobed Input)
A low-level on this input latches the output data from the
terminal units into the input register of the port. In short,
this is a lock for data latching. The data from the terminal
units can be latched by the PPI independent of the control
signal from the CPU. This data is not sent to the data bus
until the instruction IN is executed.
, Fig. 4 Timing chart
.-----------------------..,
IBF
RO
(Note 1)
INTR
PORT
INPUT
_-+-~
Do
-07------------------
IBF (Input Buffer Full Flag Output)
A high-level on this output indicates that the data from the
terminal units has been latched into the input register. IBF
is set to high·level by the falling edge of the STB input, and
is reset to low-level by the rising edge of the RD input.
INTR (Interrupt Request Output)
This can be used to interrupt the CPU when an input device
is requesting service. When INTE (interrupt enable flag) of
the PPI is high-level, INTR is set to high-level by the rising
edge of the STB input and is reset to low-level by the falling
edge of RD input.
INTEA of group A is controlled by bit setting of PC 4 •
INTE B of group B is controlled by bit setti ng of PC2 •
Mode 1 input state is shown in Fig. 3, and the timing
chart is shown in Fig. 4.
Note1: When INTE is low-level. INTR is always low-level.
The following shows operations using mode 1 for output
ports.
OBF (Output Buffer Full Flag Output)
This is reset to low-level by the rising edge of the WR signal
and is set to high-level by the falling edge of the ACK
(acknowledge input). In essence, the PPI indicates to the
. terminal units by the OBF signal that the CPU has sent data
to the port.
ACK (Acknowledge Input)
,Receiving this signal from a terminal unit .can indicate to
the .PPI that the: terminal unit has accepted data from a
port.
Fig. 3 An example of mode 1 input state
MODE 1 (PORT A)
CONTROL WORD
1/0
MODE 1 (PORT B~
CONTROL WORD
0706 05 0403 0201 Do
111xlxlxlxl1111xl
STBS
IBFs
INTRS·
INTR (Interrupt Request)
When a peripheral unit is accepting data from the CPU,
setting INTH to high-level can be used to interrupt the CPU.
When INTE (interrupt enable flag) is· high'and OBF is set to
high-level by the rising edge of an ACK signal, then INTR
will also be set to high-level by the rising edge of the ACK
signal. Also, INTR isreset to low-level by the falling edge of
the WR signal when the PPI has been receiving data from
the CPU.
lNTEA of group A is controlled by bit setting of PC 6 •
INTEB of group B is controlled by bit setting of PC 2 .
Mode 1 output state is shown in Fig: 5, and the timing
chart is shown in Fig. 6;
Combinations f~r using port A and port B as input or
output in mode 1 are shown in Fig. 7 and Fig. 8.
. • MITSUBISHI
8-68
__..J ' -_ _ _ _-+__+-___
INPUT
LATCH
I.. ELECTRIC
MITSUBISHI LSls
MSL 82S5AP-S
PROGRAMMABLE PERIPHERAL INTERFACE
Fig. 5 Mode 1 output example
Fig. 6 Timing diagram
CONTROL WORD
oB F - - t - - - - - , .
ACK --+-----+-----~
MODE 1 (PORT B)
INTR
CONTROL WORD
07 06 Os 04 0302 0 I Do
11lxlxlx{xlll0lxl
Note 2 : When INTE is low-level. then the output of INTR is always low-level.
Fig. 7 Mode 1 port A and port B 1/0 example
Fig. 8 Mode 1 port A and port B 110 example
RO
OBFA
WR
CONTROL WORD
ACKA
STBA
IBFA
CONTROL WORD
INTRA
INTRA
I
II
0
I/O
PC4. PCS
1 = INPUT
0= OUTPUT
WR
RO
PCI
PCo
INTRB
PORT A (STROBED INPUT)
PORT B (STROBED OUTPUT)
PCo
PORT A (STROBED OUTPUT)
PORT B (STROBED INPUT)
• MITSUBISHI
.... ELECTRIC
8-69
MITSUBISHI LSls
MSL 82SSAP-S
PROGRAMMABLE PERIPHERAL INTERFACE
3. Mode 2 (Strobed Bidirectional Bus Input/Output)
Fig. 9 Mode 2 timing diagram
Mode 2 can provide bidirectional operations, using one
8-bit bus for communicating with terminal units. Mode 2
is only valid with group A and uses one 8-bit bidirectional
bus port (port A) and a 5-bit control port (high-order five
bits of port C). The bus port (port A) has two internal
registers, one for input and the other for output. On the
other hand, the control port (port C) is used for communi-
INTR
cating control signals and bus-status signals. These control
signals are similar to mode 1 and can also be used to control
interruption of the CPU. When group A is programmed as
mode 2, group B can be programmed independently as
IBF ________________~
mode 0 or mode 1. When group A is in mode 2, the following five control signals can be used.
DATA FROM TERMINAL UNITS
PORT A - - - - - - - - - - - - -
(DATA FROM CPU)
-<::::::»----
OBF (Output Buffer Full Flag Output)
The OBF output wili go low-level to indicate that the CPU
has sent data to the internal register of port A. This signal
lets the terminal units know that the data is ready for
transfer from the CPU. When this occurs, port A remains in
the floating (high-impedance) state.
ACK (Acknowledge Input)
Fig. 10 An example of mode 2 operation
A low-level ACK input will cause the data of the internal
register to be transferred to port A. For a high-level ACK
input, the output buffer will be in the floating (highimpedance) state.
STB (Strobed Input)
When the STB input is low-level, the data from terminal
units will be held in the internal register; and the data will
be sent to the system data bus with an RD signal to the PPI.
IBF (Input Buffer Full Flag Output)
When data from terminal units is held on the internal
register, IBF will be high level.
INTR (Interrupt Request Output)
This output is used to interrupt the CPU and its operations
the same as in mode 1. There are two interrupt enable flags
I/O
IBF A STBA ACKA OBF A I/O INTRA
CONTROL WORD
that correspond to INTEA for mode 1 output and mode
1 input.
INTEl
is used in generating INTR signals in combination
with OBF and ACK. INTEl is controlled by bit
setting of PC 6 •
INTE2
PC2--PCO
' - - - - - - - 1 = INPUT
0= OUTPUT
is used in generating INTR signals in combination
with
TBF
and STB. I NTE2 is controlled by bit
setting of PC 4 •
PORT B
' - - - - - - - 1 = INPUT
0= OUTPUT
Fig. 9 shows the timing diagram of mode 2, and Fig. 10
is an example of mode 2 operation.
8-70
'-----------l~
• MITSUBISHI
.... ELECTRIC
GROUP B MODE
0 = MODE 0
1 = MODE 1
MITSUBISHI LSI.
MSL 82SSAP-S
PROGRAMMABLE PERIPHERAL INTERFACE
4. Control Signal Read
Table 2 Read-out control signals
In mode 1 or mode 2 when using port C as a control port,
by CPU execution of an IN instruction, each control signal
and bus status from port C can be read.
~
07
06
Mode 1, input
10
10
Mode
05
04
03
02
01
Do
IBFA INTEA INTRA INTEs IBFs INTRs
5. Control Word Tables
Mode 1, output OBFA INTEA 10
Control word formats and operation details for mode 0,
Mode 2
INTRA INTEs OBFs INTRE
10
By group B mode
OBFA INTE 1 IBFA INTE2 INTRA
mode 1, mode 2 and set/reset control of port C are given in
Tables 3, 4, 5 and 6, respectively.
Table 3 Mode 0 control words
Control words
07
06
05
04
03
02
Group A
01
Do
Hexadecimal
PortA
Group B
Port C (lOW order 4 bits)
Port C (high order 4 bits)
Port B
1
0
0
0
0
0
0
0
8 0
OUT
OUT
OUT
OUT
1
0
0
0
0
0
0
1
8
1
OUT
OUT
IN
OUT
1
0
0
0
0
0
1
0
8 2
OUT
OUT
OUT
IN
1
0
0
0
0
0
1
1
8 3
OUT
OUT
IN
IN
1
0
0
0
1
0
0
0
8 8
OUT
IN
OUT
OUT
OUT
1
0
0
0
1
0
0
1
8 9
OUT
IN
IN
1
0
0
0
1
0
1
0
8 A
OUT
IN
OUT
IN
1
0
0
0
1
0
1
1
8 B
OUT
IN
IN
IN
1
0
0
1
0
0
0
0
9 0
IN
OUT
OUT
OUT
1
0
0
1
0
0
0
1
9
1
IN
OUT
IN
OUT
1
0
0
1
0
0
1
0
9 2
IN
OUT
OUT
IN
1
0
0
1
0
0
1
1
9 3
IN
OUT
IN
IN
1
0
0
1
1
0
0
0
9 8
IN
IN
OUT
OUT
OUT
1
0
0
1
1
0
0
1
9 9
IN
IN
IN
1
0
0
1
1
0
1
0
9 A
IN
IN
OUT
IN
1
0
0
1
1
0
1
1
9 B
IN
IN
IN
IN
Note 4: OUT Indicates output port, and IN Indicates Input port.
Table 4 Mode 1 control words
07 06 05 04 03 02 01 Do
Hexadecimal
PC7
0
1
0
0
1
0
X
A4
A5
OUT
1
0
1
0
0
1
1
X
A6
A7
OUT
OUT
OUT
1
0
1
0
1
1
0
X
AC
AD
1
0
1
0
1
1
1
X
AE
AF
PC6
-OBFA
ACKA
--
-ACKA
OBFA
-ACKA
OBFA
--
--
ACKA
OBFA
0
1
1
0
1
0
X
B4
B5
IN
OUT
IBFA
1
0
1
1
0
1
1
X
B6
B7
IN
OUT
1
0
1
1
1
1
0
X
BC
BO
IN
IN
X
BE
BF
1
1
1
1
1
IN
IN
Port B
PC4
PCs
1
0
Port C
Port C
PortA
1
1
Group 9
Group A
Control words
PC3
OUT
INTRA
OUT
INTRA
IN
INTRA
IN
INTRA
--
PCz
PC,
--
--
PCo
OBFs
INTRs
OUT
IBFs
INTRs
IN
OBFs
INTRs
OUT
STBs
IBFs
INTRs
IN
--
-OBFs
INTRs
OUT
STBs
IBFs
INTRs
IN
ACKs
-STBs
ACKs
--
--
STBA
INTRA
IBFA
STBA
INTRA
IBFA
S,BA
INTRA
ACKs
OBFg
INTRs
OUT
INTRA
-STBs
IBFs
INTRs
IN
IBFA
STBA
ACKs
--
Note 5 : Mode of group A and group B can be programmed Independently.
6 : It is not necessary for both group A and group B to be in mode 1.
• MITSUBISHI
...... ELECTRIC
8-71
II
MITSUBISHI LSI.
MSL 82SSAP·S
PROGRAMMABLE PERIPHERAL INTERFACE
Table 5 Mode 2 control words
Control words
07 06 05 04 03 02 01 Do
Port B
Port A
1
1
X
X
X
0
0
1
1
X
X X
0
1
0
C2
1
1
X
X X
0
1
1
C3
1
1
X
X X
1
0
X
C4
Bidirectional
bus
Bidirectional
bus
Bidirectional
bus
Bidirectional
bus
Bidirectional
1
1
X
X X
1
1
X
C6
Bidirectional
bus
1
X
X X
0
0
0
C1
CO
Port C
Port C
1
1
Group B
Group A
Hexadecimal
(Ex.)
DUS
PC7
PC6
PCs
PC4
PC3
OBFA
ACKA
IBFA
STBA
INTRA
OUT
OUT
OUT
PC2
[
PCl
[
PCO
OBFA
ACKA
IBFA
STBA
INTRA
IN
OBFA
ACKA
IBFA
STBA
INTRA
OUT
IN
OBFA
ACKA
IBFA
STBA
INTRA
IN
IN
OBFA
ACKA
IBFA
STBA
INTRA
ACKs [ OBFs [INTRs
OUT
OBFA
ACKA
IBFA
STBA
INTRA
STBs I
IBFs
IN
IINTRS
Table 6 Port C set/reset control words
Control words
Remarks
Port C
07 06 05 04 03 02 01 DO
Hexadecimal
PC7
PC6
PCs
PC4
PC3
PC2
PCl
PCo
0
X
X
X
0
0
0
0
00
0
0
X
X
X
0
0
0
1
01
1
0
02
0
X
X
X
0
0
1
0
X
X
X
0
0
1
1
03
0
X
X
X
0
1
0
0
04
0
INTEs set/reset for mode 1 input
0
X
X
X
0
1
0
1
05
1
INTEs set/reset for mode 1 output
0
X
X
X
0
1
1
0
06
0
1
0
0
X
X
X
0
1
1
1
07
0
X
X
X
1
0
0
0
08
0
INTEA set/reset for mode 1 input
0
X
X
X
1
0
0
1
09
1
IN T E 2 set/reset for mode 2
1
0
X
X
X
1
0
1
0
OA
0
X
X
X
1
0
1
1
OB
0
X
X
X
1
1
0
0
OC
0
INTEA set/reset for mode 1 output
0
X
X
X
1
1
0
1
00
1
IN T E 1 set/ reset for mode 2
0
X
X
X
1
1
1
0
OE
0
0
X
X
X
1
1
1
1
OF
1
0
1
Note 7: The terminals of port C should be programmed for the output mode. before the bit set/reset operation is executed.
8 . Also used for controlling the interrupt enable flag (INTE)
8-72
• MITSUBISHI
..... ELECTRIC
MITSUBISHI LSls
MSL 82SSAP-S
PROGRAMMABLE PERIPHERAL INTERFACE
ABSOLUTE MAXIMUM RATINGS
Symbol
Conditions
Parameter
Vee
Supply voltage
VI
Input voltage
Vo
Output voltage
Limits
With respect to GND
Pd
Power dissipation
Topr
Operating free-air temperature range
Tstg
Storage temperature range
Ta =25·C
RECOMMENDED OPERATING CONDITIONS
Unit
-
0.5-7
-
0.5-7
V
-
0.5-7
V
V
mW
1000
0·-70
·C
-65-150
·C
(Ta=0-70·C. unless otherwise noted)
Limits
Symbol
Parameter
Unit
Min
Vee
Supply voltage
GND
Supply voltage
VIH
High-level input voltage
2
VIL
Low-Ievel'input voltage
-0.5
Nom
Max
5
5.25
4.75
0
ELECTRICAL CHARACTERISTICS
(Ta=0-70·C.
V
V
Vee
V
0.8
V
Vee=5V ±5%. GND=OV. unless otherwise noted)
Limits
Symbol
Parameter
Test conditions
Min
VOH
High-level output voltage
VOL
Low-level output voltage
Data bus
Typ
Max
Unit
IOH= -400,uA
GND=OV
2.4
Port
V
IOH= -200,uA
Data bus
IOL=2.5mA
GND=OV
0.45
Port
V
IOL=1. 7mA
IOH
High-level output current (Note 10)
GND=OV. VOH=1.5V. REXT=750Q
ICC
Supply current from Vee
GND=OV
IIH
High-level input voltage
GND=OV. VI=5.25V
IlL
Low-level input voltage
IOZ
Off-state output current
Ci
Input capacitance
VIL =GND. f=lMHz. 25mVrms Ta=2S"C
10
pF
Ci/o
Input! output terminal capacitance
Vl/oL=GND. f=lMHz. 25mVrms Ta=25"C
20
pF
-1
-4
mA
120
mA
±10
J..lA
GND=OV. VI=OV
±10
J..lA
GND=OV. VI=0-5.25V
±10
J..lA
Note 9' Current flowing into an IC is positive; out is negative.
10 : It is valid only for any 8 input/output pins of PB and PC.
TIMING REQUIREMENTS
Symbol
(Ta=O-70T. Vcc=SV±S%.
Prameter
GND=OV. unless otherwise noted)
Alternative
symbol
Limits
Test conditions
Unit
Min
Typ
Max
tW(R)
Read pulse width
tRR
tSU(PER)
Peripheral setup time before read
tlR
0
ns
th(R-PE)
Peripheral hold time after read
tHR
0
ns
300
ns
tSU(A-R)
Address setup time before read
tAR
0
ns
th(R-A)
Address hold time after read
tRA
0
ns
tW(W)
Write pulse width
tww
300
ns
tSU(OQ-W)
Data setup time before write
tow
100
ns
th(W-OQ)
Data hold time after write
two
50
ns
tSU(A-W)
Address setup time before write
tAw
0
ns
theW-A)
Address hold time after write
tWA
40
ns
tW(AeK)
Acknowledge pulse width
tAK
300
ns
tW(STB)
Strobe pulse width
tST
500
ns
tSU(PE 'STB)
Peripheral setup time before strobe
tps
0
ns
th(STB'PE)
Periphera I hold ti me after strobe
tpH
180
ns
tC(RW)
Read/write cycle time
tRY
850
ns
• MITSUBISHI
.... ELECTRIC
8-73
II
MITSUBISHI LSI.
M5L 8255AP-5
PROGRAMMABLE PERIPHERAL INTERFACE
SWITCHING CHARACTERISTICS(Ta=0-70·c.
vcc=5V±5%.
unless otherwise noted)
Limits
Alternative
Test conditions
Parameter
Symbol
symbol
Typ
Min
Max
Unit
tPZX(R-DQ)
Propagation time from read to data output
tRD
200
ns
tPXZ(R-DQ)
Propagation time from read to data floating (Note 12)
tDF
100
ns
Propagation time from write to output
tws
350
ns
tpLH( STB-IBF)
Propagation time from strobe to IBF flag
tSIS
300
ns
tPLH(STB-INTR)
Propagation time from strobe to interrupt
tSIT
300
ns
tpHL( A-INTA)
Propagation time from read to interrupt
tRIT
400
ns
tPHL(R-IBF)
Propagation time from read to IBF flag
tRIS
300
ns
tPHL(W-INTR)
Propagation time from write to interrupt
tWIT
850
ns
tPHL(W-OBF)
Propagation time from write to OBF flag
twos
650
ns
tPLH(ACK-OBF)
Propagation time from acknowledge to OBF flag
tAOS
350
ns
tPLH(ACK-INTR)
Propagation time from acknowledge to interrupt
tAIT
350
ns
tPZX(ACK-PE)
Propagation time from aCknowledge to data output
tAD
300
ns
250
ns
tPHL(W-PE)
tPLH(W-PE)
tPXZ(ACK-PE)
Propagation time from acknowledge to data output (Note 11)
20
tKD
Note 11 : Measurement conditions:
CL = 1 OOpF for M5L8255AP. $
CL = 1 50pF for M5L8255AP-5. $-5
1 2 : Measurement conditions of note 11 are not applied.
TIMING DIAGRAMS
REFERENCE LEVEL ~ "H"=2V, "L"=0.8V
Mode 0 Basic Input
tW(R)
tSU(PE-Rl
th(R-PE)
INPUT
th(R-A)
tSU(A-R)
tPZX(R-DQ)
DO-D7 -
tPXZ(R-DQ)
---- ----------
Mode 0 Basic Output
I
t W ( W)
~-
)
tSU(DQ-W)
)r
00-07
tSU(A-W)
th(W-DQ)
K
th(W-A)
I
Ao
)t
tPHL{W-PE)
I tPLH(W-PE)
)(
OUTPU T
8-74
• MITSUBISHI
"'ELECTRIC
MITSUBISHI LSls
MSL 82SSAP-S
PROGRAMMABLE PERIPHERAL INTERFACE
Mode 1 Strobed Input
tW(STB)
tPLH( STB-IBF)
IBF
INTR
tSU(PE-STB)
INPUT - - -
Mode 1 Strobed Output
tW(W)
I~--
\~
WR
¥
\
tPHL( W-OBF)
\
INTR
tPLH( ACK-OBF)
I
tw( ACK)
~
~
tPHL(W-INTR)
ACK
tPHL(W-PE)
tPLH(W-PE)
\
,/
/
~ tPLH( ACK-INTR)
~~
II
f-~
I
OUTPU T
Mode 2 Bidirectional
INTR
tPLH( STB-IBF)
IBF
INPUT- -
--- ----
Note 13: INTR=IBF·MASK·STB·RO+OBF·MASK·ACK·WR
• MITSUBISHI
.... ELECTRIC
8-75
MITSUBISHI LSls
MSL 82S5AP-S
PROGRAMMABLE PERIPHERAL INTERFACE
Circuit Examples for Applications
1. Mode 0
An example of a circuit for an application using mode 0 is
shown in Fig. 11.
Fig. 11 Circuit example for an application using mode O.
~--l
J
FAOM EXTERNAL CIRCUtT
INT
PORT A
READY
SYNC
~--~------~----------~RESET
PORT C
PPI
M5L8255AP-5
PORT C
1kQ
I----IHLDA CPU
M5L8080AP. S
D----ClWR
WR
I/OW
RD
DBIN 14----10 BIN
lOR
SYSTEM
CONTROLLER
07
\ k--+..-a
PORT B
FROM
ABo
FROM
ADDRESS
DECODER
FROM
AB,
MYI
A, 90#
OUT
03#
OB7
AB,5
DBo
\
ABo
\
16
ADDRESS BUS
DATA
BUS
L...-_ _ _ }
In this example, the PPI is in mode 0, and the control
word should be 10010000 (90 16 ),
The PPI will be initialized by executing the above two instructions.
Then, for example, to read data from port A and to
output data to port Band C, the following three instructions
can be used.
o 0 # CPU A register +- Port A
IN
o 1 # Port B +- A register
OUT
OUT
o 2 # Port C +- A register
After setting the mode each port operates as a normal port.
After setting the mode, as shown in Fig. 11, to read data
from port A, to output to port B, and to set the first bit of
port C "1", the following four instructions can be used.
8-16
HLD
TO MEMORY
CPU A register +- Port A
Port B +- A register
MYI
A, 01# Bit-setting control word for PC o
OUT
Outputting to control address
03#
(CS = "0", A1 = Ao = "1")
The other bits of port C, in this case, are unknown.
IN
OUT
• MITSUBISHI
.... ELECTRIC
00:1+
01#
MITSUBISHI LSls
MSL 82SSAP-S
PROGRAMMABLE PERIPHERAL INTERFACE
2. Mode 1
The actual program for the circuit of Fig. 12 is as follows:
An example of a circuit for an application using mode 1 is
shown in Fig. 12.
MVI
Fig. 12 A circuit for an application using mode 1
OUT
MVI
INPUT
DATA
1
DA TA STROBED
SIGNAL
STBA
IBFA
Lr
PAo
PAl
PA2
PA3
PA4
PAs
PA6
PA7
FROM
FROM
FROM
-FROM
ADDRESS A 1
ADDRESS AO
DECODER
CLOCK
GENERATOR
FROM SYSTEM CONTROLLER
IIOW
PPI
MSL82SSAP-S 0
PC4
0
PCs
01
02
03
PC3
Os
04
INTRA
FROM SYSTEM CONTROLLER
IIOR
}
TO DATA BUS
07
OUT
EI
HLT
A,
BO:j:f Control word is 10110000, port A
is the mode 1 input and the others
are output.
03:j:f
Outputting to the control address
A, 09:j:f PC 4 bit-set 00001001
03:j:f
Outputting to the control address
Interrupt enable
Halt
If the data has been set in a terminal unit, and the strobe
signal has been input; then the data will be latched in port
A and the CPU INT goes high-level. In the case of Fig. 11,
this is followed by outputting instruction RST 7 from the
system controller as an interrupt command. Then a jump to
0038 16 is executed to continue the program as follows:
PBO-PB7
CPU
TO INT
(INTERRUPT INPUT)
003816
D I
IN
0 0 :j:f CPU register A +- Port A
PC 3 interrupt signal becomes
low-level
RET
Transferring data from a terminal unit to port A and
sending a strobe signal to PC 4 will hold the data in the
internal latch of the PPI, and PC s (lBF input buffer full
flag) is set to "1". If a bit-set of PC 4 has been executed in
advance, the CPU can be interrupted by the INTR signal of
PC 3 when the input data is latched in the PPI. In this way,
port A becomes an interrupting port; and at the same time,
port B can select its mode independently.
• MITSUBISHI
.... ELECTRIC
II
8-77
MITSUBISHI LSls
M5L 8255AP·5
PROGRAMMABLE PERIPHERAL INTERFACE
3. Mode 2
An example of a circuit for an application using mode 2 is
shown in Fig. 13.
In Fig. 13, the data bus of the slave system is connected
with the corresponding PPI port A bit of the master station.
The input port consists of a three-state buffer and gate B
which allow the slave CPU to read flag outputs (lBF, OBF)
of the PPI as data.
When the following instruction is executed in this example, the action is as described:
I N 0 1 j:I: (reading in from 01 16 input port)
The data which is made up of the least significant bit
(Do), the OBF (output buffer full flag output) and the next
least significant bit (0 d of the IBF (input buffer full flag
output) will be read into the slave CPU.
When the following instruction is executed, the action is
as described:
I N 0 0 j:I: (reading in from 00 16 input port)
ACK (PC 6 ) of the PPI becomes low-level by gate C, and
the contents of the port A output latch will be read into
the slave CPU.
When the following instruction is executed, the action is
as described:
OUT 0 0:1:1: (writing out to 00 16 output port)
STB (PC 4 ) of the PPI becomes low-level by gate 0, then
the contents of the slave CPU register A will be written into
the port A input latch of the PPI.
Actual operations are as follows:
1. PPI is set in mode 2 by the master CPU (03 address).
2. The master CPU writes the data, which is transferred
to the slave CPU, into port A of the PPI (in turn, OBF
becomes low-level).
3. The slave CPU continues to read the state of flags (OBF
and ii3F) as data, while OBF is high-level (Le. no data
from the master CPU).
4. When the slave CPU senses that OBF has become lowlevel, the slave CPU starts to read the data from 00 16
(which is the input address for the preceding data) which
is in the output latch of port A ( in turn, OBF returns to
high-level) .
5. During this period, the master CPU reads the status flags
(reading in from 02 of port C) and checks the states of
both the bit 7 (OBF) and bit 5 (lBF). If OBF is low-level,
it indicates that the slave CPU has not yet received the
data; so the master does not write new data. If OBF is
high-level, the master CPU writes the next data.
6. When data is to be transferred to the master CPU, the
contents of the slave CPU A register will be transmitted
to the port input latch of the PPI. The slave CPU transfers the data to address 00 16 (in turn, the IBF becomes
high-level).
7. The master CPU transfers data to port C and then checks
the status flag. If the input latch contains data from the
slave CPU, which is indicated by IBF having a high-level
output, the data is read from port A (00 16 ) (in turn, the
IBF returns to low-level).
8. The slave CPU reads the status flag from 02 16 to determine if IBF has returned to low-level. If it has not, new
data will not be written as long as ISF is high-level.
9. In this way, data can be exchanged. Since there are two
sets of independent registers, input latch and output
latch, used by port A of the PPI, it is not necessary to
alternate input/output transfers.
A program which has operating functions as described
above, is explained as follows.
The operation, in mode 2, for group A of the PPI is
considered here.
Fig. 13 A circuit for an application using mode 2
(PPI MODE SET ADDRESS)
0316
lj'N'puf'l
[~g~ro
MASTER
CPU
SLAVE SYSTEM DATA BUS
L~ft!J
Ao
\
A1S
Ao
A1
B
O~o
SYSTEM
OB7
CONTROLLER
I/OR
I/ow
MASTER SYSTEM
Do
\
07
RO
WR
PC3
OBo
ACKA
STBA
INTR
I
\
OB7
'--------II/OR
I
PPI
TO CPU
INT TERMINAL
\
A1S
0 0 16
PC7
PC4
16 Ao
DECO-
.-----t--::.. - - -".. --IDER
PC6
00-07
8-78
_J 3 STATE
BUFFER
PCs
SLAVE
CPU
I
I
I
'---------11/0W
I
I
I
I
• MITSUBISHI
..... ELECTRIC
00-07
SYSTEM
CONTROLLER
SLAVE SYSTEM
MITSUBISHI LSls
MSL 82SSAP-S
PROGRAMMABLE PERIPHERAL INTERFACE
1. Master CPU subroutine for transmitting data to the slave
CPU.
2. Subroutine for receiving data from the slave CPU.
Program example
Program example
MOUT
PUSH
PSW
OBF
IN
02#
ANI
20#
ANI
80#
JZ
MIN
00#
MIN
IN
IN Z
OBF
IN
POP
PSW
RET
OUT
RET
00#
02#
RET
RET
3. Slave CPU subroutine for transmitting data to the master
CPU.
4. Subroutine for receiving data from the master CPU.
II
Program example
Program example
SIN
IN
02#
SOUT
PUSH
PSW
IBF
IN
02#
ANI
01#
ANI
02#
JZ
SIN
JNZ
IBF
IN
00#
POP
PSW
RET
OUT
RET
00#
RET
RET
.•. MITSUBISHI
..... ELECTRIC
8-79
MITSUBISHI LSls
MSL 82SSAP·S
PROGRAMMABLE PERIPHERAL INTERFACE
4. Address Decoding
5. PPI Initialization
Address decoding with multiple PPI units is shown in Figs.
14 and 15. These are functionally equal.
The same address data is output to both the upper and
It is advisable to reset the PPI with a system initial reset
and to select the mode at the beginning of a system program. The initial state of the PPI used as an output port is
shown in Fig. 16.
lower a-bit address bus with the execution of I N and OUT
instructions by the CPU.
Fig. 16 PPI initialization
Fig. 14 PPI address decoding (case 1)
POWER
SUPPLY Vee
CPU
M5L8080AP. S
A7~
ADDRESS
BUS
RESET
A6~
PORT
A3
TO
ADDRESS
BUS
•
A2
Al
B
A
UNSTABLE»).---------FLOATING
~
~
,-
(INPUT MODE)
C
0
M53242P
o1
2
7 8 9
rrr---r rr
'----v----'
TO PORT ADDRESS INPUT Ao AND Al TO THE CHIP SELECT INPUTCS OF
'--v---/
OF EACH PPI
EACH PPI
Fig. 15 PPI address decoding (case 2)
CPU
M5L8080AP. S
~
~
A12
TO
ADDRESS
BUS
A11
AlO
Ag
As
B
A
C
0
M53242P
o1
2
7 8 9
II r---r rr
~
TO PORT ADDRESS INPUT Ao AND A 1
OF EACH PPI
8-80
SELECTING MODE AT THE
OUTPUT PORT
OUTPUT="1"
Note 14 : Period of reset pulse must be at least 50,us during or after
power on. Subsequent reset pulse can be 500ns minimum.
Ao
A15
A14
A13
~
:
:
As
A4
ADDRESS
BUS
~ ov
'-----v----'
_
TO THE CHIP SELECT INPUT CS OF
• MITSUBISHI
.... ELECTRIC
MIT SUB ISH I LSI.
MSL82S7P-S
PROGRAMMABLE DMA CONTROLLER
DESCRIPTION
The M5L 8257P~5 is a programmable, 4-channel direct
memory access (DMA) controller. It is produced using the
N-channel silicon-gate ED-MOS process and is specifically
designed to simplify data transfer at high speeds for microcomputer systems. The LSI operates on a single 5V power
supply.
FEATURES
• 4-channel DMA controller
• Single 5V povver supply
• Single TTL clock
• Priority DMA request logic
• Channel-masking function
• Terminal count and Modulo 128 outputs
• Compatible with the MELPS 8 microprocessor series
• Pin connection and electrical characteristics compatible
with Intel's type 8257·5 programmable DMA controller
APPLICATIONS
• DMA control of peripheral equipment such as floppy
disks and CRT terminals that require high-speed data
transfer.
FUNCTION
The M5L 8257P-5 controller is used in combination with
the M5L 8212P 8-bit input/output port in 8-bit microcomputer systems.
It consists of a channel section to acknowledge DMA requests, control logic to exchange commands and data with
the CPU, read/write logic, and registers to hold transfer
addresses and count the number of bytes to be transferred.
When a DMA request is made to an unmasked channel
from the peripherals after setting of the transfer mode,
transfer-start address and the number of transferred bytes
for the registers, the M 5L 8257P-5 issues a priority request
PIN CONFIGURATION (TOP VIEW)
I/O READ
INPUT/OUTPUT
i75R-
1
INPu¥/~(ft~0f
MEMORY READ
OUTPUT
MEMORY WRITE
OUTPUT
MARK OUTPUT
ADDRESS
OUTPUTS
4-7
MEMW_ 4
TERMINAL
COUNT
OUTPUT
READY INPUT READY -+ 6
HOLDEt~~~2~JT HLOA -+ 7
ADDRESS
INPUT/
OUTPUTS
ADDRESS
STROBE OUTPUT
ADDRESS
ENABLE OUTPUT
HOLD REQUEST
OUTPUT
CHIP SELECT
INPUT
0-3
(5V)
CLOCK INPUT
DATA
INPUT/
OUTPUTS
RESET INPUT
-03
DMA{
ACKNOWLEDGE
OUTPUTS 2. 3
26 -04
DMA AC25 -+ DACK 0 KNOWLEDGE
}
24 -+ DACKI g.U TPUTS
1
REQUEST
DMAj
INPUTS 0-3
DATA
INPUTS/
OUTPUTS
1
GROUND
Outline 40P1
for the use of the bus to the CPU. On receiving an HLDA
signal from the CPU, it sends a DMA acknowledge signal to
the channel with the highest priority, starting DMA
operation.
During DMA operation, the contents of the high-order 8
bits of the transfer memory address are transmitted to the
M5L 8212P address-latch device through pins Do -D 7 • The
contents of the low-order 8 bits are transmitted through
pins Ao -A 7 • After address transmission, DMA transfer
can be started by dispatching read and write signals to the
memories and peripherals.
BLOCK DIAGRAM
19 OROo
5 OACKo
DATA BUS
BUFFER
DATA INPUTS/OUTPUTS
I/O READ INPUT/OUTPUT
I/O WRITE INPUT/OUTPUT
CLOCK INPUT
RESET INPUT
18 ORO,
~~l~~~EST
2 OACK,
g~pe~~~~r"LEDGE
1 ORO,
~~TR~~~2EST
1 [lACK,
g~pe~~~~~LEDGE
16 DRO,
~~TR~~~EST
CLK 12
RESET 13
READ/WRITE
LOGIC
B-BIT
INTERNAL
BUS
ADDRESS INPUTS/OUTPUTS
15
5ACKl g~pe~~NH~~LEDGE
TC
CONTROL
LOGIC
~~TR~~~EST
g~pe~~~~6'LEDGE
TERMINAL COUNT
OUTPUT
MARK OUTPUT
AND
MODE SET
REGISTER
• MITSUBISHI
"ELECTRIC
8-81
II
:
MITSUBISHI LSls
MSL82S7P-S
PROGRAMMABLE DMA CONTROLLER
Ready Input (READY)
OPERATION
Data-Bus Buffer
This three-state, bidirectional, 8-bit buffer interfaces the
M5L 8257P-5 to the CPU for data transfer. During a DMA
cycle the upper 8 bits of the DMA address are output to the
M5L 8212P latch device through this buffer.
I/O Read Input/Output (I/OR)
When the M5L 8257P-5 is in slave-mode operation, this
threestate, bidirectional pin serves for inputting and
reads the upper/lower bytes of the 8-bit status register
or 16-bit DMA address register and the high/low order
bytes of the terminal counter.
I n the master mode, the pin gives control output and is
used to obtain data from a peripheral equipment during the
D MA write cycle.
I/O Write Input/Output (I/OW)
This pin is also of the three-state bidirectional type. When
the M5L 8257P -5 is in slave-mode operation, it serves
for inputting and loads the contents of the data bus
on the upper/lower bytes of the 8-bit status register or
16-bit DMA address register and the upper/lower bytes of
the terminal counter.
Clock Input (ClK)
This pin generates internal timing for the M5L 8257P - 5
and is connected to the C/>2(TIL) output of the M5L 8224P
- 5 clock generator.
Reset Input (RESET)
This asynchronous input clears all registers and control lines
inside the M5L 8257P-5.
Address Inputs/Outputs (Ao-A3 )
The four bits of these input/output pins are bidirectional.
When the M5L8257P -5 is in slave-mode operation,
serve to input and address the internal registers. In the
case of master operation, they output the low-order 4 bits
of the 16-bit memory address.
This asynchronous input is used to extend the memory
read and write cycles in the M5L8257P-5 with wait
states if the selected memory requires longer cycles.
Hold Request Output (HRQ)
This output requests control of the system bus. HRQ will
normally be applied to the HOLD input on the CPU.
Hold Acknowledge Input (HlDA)
This input from the CPU indicates that the system bus is
controlled by the M5L 8257P-5 .
Memory Read Output (MEMR)
This active-low three-state output is used to read data from
the addressed memory location during DMA read cycles.
Memory Write Output (MEMW)
This active-low three-state output is used to'write data into
the addressed memory location during DMA write cycles.
Address Strobe Output (ADSTB)
This output strobes the most significant byte of the
memory address into the M5L 8212P 8-bit input/output
port through the data bus.
Address Enable Output (AEN)
This signal is used to disable the system data bus and
system control bus by means of the bus enable pin on the
M5L8228P system controller. It may also be used to inhibit non-DMA devices from responding during DMA cycles.
Terminal Count Output (TC)
This output signal notifies that the present DMA cycle is
the last cycle for this data block.
Mark Output (MARK)
This signal notifies that the DMA transfer cycle for each
channel is the 128th cycle since the previous MAR K
output.
DMA Request Inputs (DRQO-DRQ3)
These independent, asynchronous channel-request inputs
are used to secure use of the DMA cycle for the peripherals.
Chip-Select Input (CS)
DMA Acknowledge Outputs (DACKO -DACK3)
This pin is active on a low-level. It enables the lORD and
IOWA. signals output from the CPU, when the M5L8257P
-5 is in slave-mode operation.
In the master mode, it is disabled to prevent the chip
from selecting itself while performing the DMA function.
These active-low outputs indicate that the peripheral equipment connected to the channel in question can execute the
DMA cycle.
Address Inputs/Outputs (A4 -A7 )
These four address lines are three-state outputs which constitute bits 4 through 7 of the memory address generated
by the M5L 8257P- 5 during all DMA cycles.
8-82
• MITSUBISHI
.... ELECTRIC
MITSUBISHI LSls
MSL82S7P-S
PROGRAMMABLE DMA CONTROLLER
Register Initialization
Two 16-bit registers are provided for each of the 4
channels.
MODESET:
MVI A,ADDl
OUT 00#: Channel 0 lower-order. address
MVI A,ADDH
OUT 00#: Channel 0 upper-order address
• DMA Address register
15
MVI A, Tel
OUT 01#: Channel 0 terminal count lower-order
OUT 01#: Channel 0 terminal count upper-order
DMA TRANSFER STARTING ADDRESS
MVI A, XX
OUT OS#:
Mode set register
• Terminal count register
15
1413
NUMBER OF TRANSFERRED BYTES-l
The DMA transfer starting address, number of transferred bytes, and DMA mode are written for each channel
in 2 steps using the 8-bit data bus. The lower-order and
upper-order bytes are automatically indicated by the firstlast flipflop for the writing and reading in 2 continuous
steps.
The DMA mode (read, write, or verify) is indicated by
the upper 2 bits of the terminal count register. The read
mode refers to the operation of peripheral devices reading
data out of memory. The write mode refers to data from
peripheral devices being written into memory. The verify
mode sends neither the read nor the write signals and
performs a data check at the peripheral device.
In addition to the above-mentioned registers, there is a
mode set register and a status register.
• Mode set register (write only)
7
I
AL
I
TOS
I
EW
I
RP
ADDED FUNCTION SETTING BITS
I EN 3 I
EN 2
I EN 1
EN 0
CHANNEL ENABLE BITS
• Status Register (read only)
UP
TO 3
TO 2
TO 1
TO 0
I
The upper-order 4-bits of the mode set register are used to
select the added function, as described in Table 1. The
lower-order 4-bits are mask kits for each channel. When set
to 1, DMA requests are allowed. When the reset signal is
input, all bits of the mode set and status registers are reset
and DMA is inhibited for all channels. Therefore, to
execute DMA operations, registers must first be initialized.
An example of such an initialization is shown below.
As can be seen from the above example, until the contents
of the address register and terminal count register become
valid, the enable bit of the mode set register must not be
set. This prevents memory contents from being destroyed
by improper DRO signals from peripheral devices.
DMA Operation Description
When a DMA request signal is received at the DRO pin from
a peripheral device after register initialization for a channel
that is not masked, the M5l8257P-5 outputs a hold request
signal to the CPU to begin DMA operation (Sl)'
The CPU, upon receipt of the HRO signal, outputs the
HlDA signal which reserves capture of the bus after it has
executed the present instruction to place this system in the
hold state.
When the M5l8257P receives the HLDA signal, an
internal priority determining circuit selects the channel
with the highest priority for the beginning of data transfer
(So).
Upon the next Sl state, the address signal is sent. The
lower-order 8-bits and the upper-order 8-bits are sent by
means of the Ao"'A7 and Do"'D7 pins respectively, latched
into the M5L8212P and output at pins A g "'A IS • Simultaneous with this, the AEN signal is output to prohibit the
selection of a device not capable of DMA.
In the S2 state, the read, extended write, and DACK
signals are output and data transferred from memory or a
peripheral device appears on the data bus.
In the S3 state, the write signal required to write data
from the bus is output. At this time if the remaining number of bytes to be transferred from the presently selected
channel has reached 0, the terminal count (TC) signal is
output. Simultaneously with this, after each 128-byte data
transfer a mark signal is output as required. In addition, in
this state the READY pin is sampled and, if low, the wait
state (Sw) is entered. This is used to perform DMA with
slow access memory devices. In the verify mode, READY
input is ignored.
•
MITSUBISHI
.... ELECTRIC
8-83
II
MITSUBISHI LSls
MSL82S7p·S
PROGRAMMABLE DMA CONTROLLER
In the 54 state, the ORO and H LOA pins are sampled at
the end of a transferred byte as the address signal, control
signals, and OACK signal are held to determine if transfer
will continue.
As described above, transfer of 1 byte requires a minimum of 4 states for execution. For example, if a 2MHz·
clock input is used, the maximum transfer rate is SOak
byte/so
Memory Mapped I/O
When using memory mapped I/O, it is necessary to change
the connections for the control signals.
RESET
MEM RD
I/O RD
MEM WR
1/0 WR
1/0 RD
MEM RD
1/0 WR
MEM WR
SYSTEM BUS
M5L8257P-5
Fig. 2 Memory mapped I/O
Also, the read mode and write mode specifications for
setting the mode of the terminal count are reversed.
Fig. 1 DMA Operation state transistion diagram
8-84
• MITSUBISHI
"ELECTRIC
MITSUBISHI LSls
MSL82S7P-S
PROGRAMMABLE DMA CONTROLLER
Table 1 Internal Registers of the M5L8257P
Bi-directional data bus
Address input
Byte
Register
07
Os
Os
04
D3
02
01
Do
0
A7
As
As
A4
A3
A2
Al
Ao
0
1
AIS
AI4
AI3
AI2
All
AIO
Ag
As
1
0
07
Os
Os
04
03
02
01
00
0
1
1
Rd
Wr
013
012
011
010
Og
Os
0
1
0
0
A7
As
As
A4
A3
A2
Al
Ao
0
0
1
0
1
Als
AI4
AI3
AI2
All
AIO
A9
As
0
0
1
1
0
07
Os
Os
04
03
02
01
00
High-order
0
0
1
1
1
Rd
Wr
013
012
011
010
Og
Os
Channel 2
DMA address
Low-order
0
1
0
0
0
A7
As
As
A4
A3
A2
Al
Ao
High-order
0
1
0
0
1
AI5
AI4
AI3
AI2
All
AIO
Ag
A8
Channel 2
terminal count
Low-order
0
1
0
1
0
07
Os
Os
04
03
02
01
00
High-order
0
1
0
1
1
Rd
Wr
013
012
OIl
010
Og
Os
Channel 3
DMA address
Low-order
0
1
1
0
0
A7
As
As
A4
A3
A2
Al
Ao
High-order
0
1
1
0
1
AI5
AI4
AI3
AI2
All
AIO
Ag
AS
Channel 3
terminal count
Low-order
0
1
1
1
0
07
Os
Os
04
03
02
01
00
High-order
0
1
1
1
1
Rd
Wr
013
012
011
010
Og
Os
RP
EN3
EN2
ENl
ENO
TC3
TC2
TOl
TOO
Channel 0
DMA address
Channel 0
terminal count
Channell
DMA address
Channell
terminal count
EW
TOS
RP
A2
Al
AO
Low-order
0
0
0
0
High-order
0
0
0
Low-order
0
0
0
High-order
0
0
Low-order
0
High-order
Low-order
Mode setting
(for write only)
-
1
0
0
0
0
AL
TOS
EW
Status
(for read only)
-
1
0
0
0
0
0
0
0
Ao-AI5
00-013
Rd, Wr
AL
F/L
A3
UP
: Addresses of the memories for which OMA will be carried out from now on. In initialization. OMA start addresses must be written.
Terminal counts-in this IC (the number of remaining transfer bytes minus 1)
: Used for OMA-mode setting by the following convention:
Rd
Wr
0
0
Mode to be set
OMA verify
0
1
OMA read
1
0
OMAwrite
1
1
Prohibition
: Automatic load mode. When this bit has been set. contents of the channel 3 register are written. as are. on the channel 2 register when
channel 2 OMA transfer comes to an end. This mode allows quick. automatic chaining operations without intervention of the software.
: Extended write signal mode. When this bit has been set. write signals can be transmitted in advance to memories and peripheral equipment
requiring long access time.
: Terminal count stop. When a OMA transfer process is complete. with terminal-count output. the channel-enable mask of that channel is
reset. prohibiting subsequent OMA cycles.
: Rotating priority mode. The setting of this mode allows the priority order to be rotated by each byte transfer.
Channel used for the present data transfer
Priority list for the next cycle
ENO- EN3:
UP
:
TOO-TC3:
F /L
:
CH-O
OH-l
CH-2
1
CH-l
OH-2
OH-3
CH-3
OH-O
2
CH-2
OH-3
OH-O
OH-l
3
CH-3
OH-O
CH-l
OH-2
4
CH-O
OH-l
OH-2
CH-3
Channel-enable mask. ThiS mask prohibits or allows the OMA request.
Update flag. This is set when register contents are transferred in an automatic load mode from channel 3 to channel 2.
Terminal-count status flags. At the time of terminal-count output. the flag corresponding to the channel is set.
First/last flip-flop. This is toggled when program and register-read operations for each channel are finished. and specifies whether the next
program or read operation is to be for the upper bytes or the lower bytes. This means that write and read operations for each register
must be carried out for a set of lower and higher bytes.
• MITSUBISHI
.... ELECTRIC
8-85
II
MITSUBISHI LSls
MSL82S7P-S
PROGRAMMABLE DMA CONTROLLER
ABSOLUTE MAXIMUM RATINGS
Vee
Power-supply voltage
VI
Input voltage
Vo
Output voltage
Pd
Power dissipation (max.)
Topr
Operating free-air temperature range
Tstg
Storage temperature range
With respect to GND
V
-0.5-7
V
mW
0-70
"C
-65-150
"C
(Ta= 0 -75"C. unless otherwise noted.)
Limits
Min
Nom
Max
4.75
5
5.25
Vee
Power-supply voltage
Vss
Power-supply voltage (GND)
VI.H
High-level input voltage
2
VIL
Low-level input voltage
-0.5
ELECTRICAL CHARACTERISTICS
V
1000
Ta=25"C
Parameter
Unit
0
V
V
%.
(Ta= 0 -70"C, Vee= 5 V± 5
Parameter
Symbol
Unit
-0.5-7
-0.5-7
RECOMMENDED OPERATING CONDITIONS
Symbol
Limits
Conditions
Parameter
Symbol
Vee+0.5
V
0.8
V
unless otherwise noted.)
Test conditions
VOL
Low-level output voltage
IOL= 1.6mA
VOHI
High-level output voltage for AB. DB and AEN
IOH=-150.uA
VOH2
High-level output voltage for HRO
VOH3
High-level output voltage for others
ICC
Power-supply current from Vee
10H= -80.uA
Limits
Min
Typ
Max
Unit
0.45
V
2.4
Vee
V
3.3
Vee
V
2.4
Vee
V
120
rnA
II
Input current
VI=Vee- 0 V
-10
10
/.lA
loz
Off· state output current
VI=Vee- 0 V
-10
10
.uA
Oi
Input capacitance
Ta=25"C Vee=Vss=OV
Pins other than that under measurement are set
10
pF
Oi/O
Input/output terminal capacitance
to OV. fe=lMHz
20
pF
TIMING REQUIREMENTS
(Ta= 0 -70"C,
Vee= 5 V± 5
%,
VSS= 0 V,
VIH=VOH= 2 V, VIL=VOL=0.8V, unless otherwise noted.)
Limits
Alternative
Symbol
Parameter
symbol
Test conditions
Min
Typ
Max
Unit
Read pulse width
TRR
250
ns
Address or CS setup time before read
TAR
0
ns
I~~:-~)
Address or CS hold time after read
TRA
0
tSU(R-DQ)
Data setup time before read
TRD
0
200
ns
th(R-DQ)
Data hold time after read
TDF
20
100
ns
tw(W)
Write pulse width
Tww
200
ns
tSU(A-W)
Address setup time before write
TAW
20
ns
th(W-A)
Address hold time after write
TWA
0
ns
tSU(DQ-W)
Data setup time before write
TDW
200
ns
th(W-DQ)
Data hold time after write
TWD
0
ns
tW(RST)
Reset pulse width
TRSTW
300
ns
tsu( Vee - RST)
Supply voltage setup time before reset
TRSTD
500
.us
tr
Input signal rise time
Tr
20
ns
tt
Input signal fall time
Tf
20
ns
tWIRl
~~(A-R)
'(CS-R)
OL=150pF
ns
tSU(RST-W)
Reset setup time before write
TRSTS
te(¢)
Clock cycle time
Tey
tw(¢)
Clock pulse width
Te
80
tSU(DRQ-,p)
DRO setup time before clock
TQS
70
ns
th (HLDA-DRQ)
DRO hold time after HLDA
TQH
0
ns
tSU(HLDA-,p)
HLDA setup time before clock
THS
100
ns
tSU(RDY-,p)
Ready setup time before clock
TRS
30
ns
th(,p-RDY)
Ready hold time after clock
TRH
20
ns
te( tP)
2
0.32
Notel: Measurement conditions: M5L 8257P OL = 100pF,
M5L 8257P -5
CL=150pF
8-86
•. '. MITSUBISHI
.... ELECTRIC
4
0.8tc(¢)
.us
ns
MITSUBISHI LSls
MSL82S7P-S
PROGRAMMABLE DMA CONTROLLER
SWITCHING CHARACTERISTICS
(Ta= 0 -70"(:,
VCC= 5 V± 5
%,
VSS= 0 V,
VOH=2V,
VOL=0.8V, unless otherwise noted.)(Note 2)
Limits
Alternative
Symbol
tPLH(¢-HRQ)
Parameter
Test conditions
symbol
Min
Typ
Max
Unit
Propagation time from clock to HRO (Note 3)
TOQ
160
ns
Propagation time from clock to HRO (Note 5)
TOQI
250
ns
tPLH(.p-AEN)
Propagation time from clock to AEN (Note 3)
TAEL
300
ns
tPHL( .p-AEN)
Propagation time from clock to AEN (Note 3)
TAET
200
ns
tPZV(AEN - A)
Propagation time from AEN to address active (Note 6)
TAEA
tPZV(.p-A)
Propagation time from clock to address active (Note 4)
TFAAB
250
ns
tpVZ(.p-A)
Propagation time from clock to address floating (Note 4)
TAFAB
150
ns
tSU(.p-A)
Address setup time after clock (Note 4)
TASM
th(.p-A)
Address hold time after clock (Note 4)
TAH
th(R-A)
Address hold time after read (Note 6)
TAHR
60
ns
theW-A)
Address hold time after write (Note 6)
TAHW
300
ns
tpZV(.p-OQ)
Propagation time from clock to data active
TFAOB
tpVZ(.p-OQ)
Propagation time from clock to ddta floating (Note 4)
TAFOB
tPHL(A-ASTB)
Propagation time from address to address strobe (Note 4)
TASS
100
th(ASTB-A)
Propagation time from address strobe to address hold (Note 6)
TAHS
50
tPLH(.p-ASTB)
Propagation time from clock to address strobe (Note 3)
TSTL
tPHL(.p-ASTB)
Propagation time from clock to address strobe (Note 3)
TSTT
tW(ASTB)
Address strobe pulse width (Note 6)
tPHL(AS-R)
Propagation time from address strobe to read or
extended write (Note 6)
TASC
70
ns
Read or extended write hold time after data
(Note 6)
TOBC
20
ns
tPHL(¢-HRQ)
tPLH(.p-HRQ)
tPHL(.p-HRQ)
tPHL(AS-WE)
th(OQ-R)
th(OQ-WE)
tPLH( ¢- TC/MARK)
250
ns
ns
A)-50
tpHL(~ASTB)t20
300
ns
170
ns
ns
ns
200
ns
140
ns
tc( ¢)
ns
-100
TAK
Propagation time from clock to DACK or TC/MARK
(Notes 3. 7)
ns
tsu(.p-
Tsw
tPLH(.p-OACK)
tPHL( ¢- TC/MARK)
20
250
ns
tPHL(.p-R)
Propagation time from clock to read. write or extended
write (Notes 4. 8)
TOCL
200
ns
Propagation time from clock to read or write
(Notes 4. 9)
TOCT
200
ns
Propagation time from clock to read active or write
active (Note 4)
TFAC
300
ns
TAFC
150
ns
tpVZ(.p-W)
Propagation time from clock to read floating or
write floating (Note 4)
tW(R)
Read pulse width (Note 6)
TRAM
tPHL(.p-W)
tPHL(.p-WE)
tPLH(.p-R)
tPLH(.p-W)
tpZV(.p-R)
tpZV(¢-W)
tpVZ(.p-R)
2lc(¢)t
tw(W)
Write pulse width (Note 6)
TWWM
tW(WE)
Extended write pulse width
TWWME
Note 2
Reference level is VOH = 3.3 V
Note 6
tc( ¢)
ns
-50
2tc( ¢)
ns
-50
Tracking specification
3
Load = 1 TTL
7
1'-.tPLH( .p-OACK)< SOns,
4
Load = 1 TTL + 50pF
8
1'-.tPHL(¢-R)< SOns,
1'-.tPHL( .p-w)< SOns,
5
Load = 1 TTL+(RL=3.3k Q),
9
1'-.tPLH(¢-R) < SOns,
1'-.tPLH( .p-W)< SOns
VOH=3.3V
ns ns
tw(~)-50
• MITSUBISHI
.... ELECTRIC
1'-.tPHL(¢-TC/MARK)< SOns,
1'-.tPLH(.p-TC/MARK)< SOns
1'-. tPHL(¢-WE) < SOns
8-87
II
MITSUBISHI LSls
MSL82S7P-S
PROGRAMMABLE DMA CONTROLLER
TIMING DIAGRAMS
DMA Mode
I
S1
S1
I
I
S1
SO
I
S2
S3
I
I
S4
I
S1
S2
I
S3
I
S4
I
S1
I
S1
I
SO
t,"(DR~Ql~ ~1-0~ ~I\Jrvv
CLK
..,....,. t(W¢)
I
ORQo-ORQ3
1/
\
)(
\
tpLH(¢~HRQ)--;O~
-
tpHL<¢-HRQ)
HRQ
f--o
th(HLDA~DRQ)
t,"(H!A-"+ I--
- ~ ___ f
T
HLOA
tPLH(¢~AEN)--;o~
MtPHL"~ AE')
1
AEN
tpZV(¢~A)_ t-IE
AO-A7
-;0
(LOWER ADDRESS)
00-07
htpvZl(¢~DQ)
IE
~
(UPPER ADDRESS)
~I
~
tPLH(¢--ASTB)-"
AOSTB
~
OACK3
tpZV(¢~R)
MEMR/I/O R
\
J
/
H
'---
tSU(RDY
.~--------
L
I(
¢ ) r 4th(¢
I \
_________
tPHL(A-ASTB)
-,ot--J-r tpHL( ASTB- R)
!!~W)_~ t±::=tPLH(¢~W)
\,
~
tpLH(¢- DACK)
-i>~ tPLH(¢
//'
1
n
IoE+I th(ASTB~A)
.~~
\
->of--t"-
tpHL(¢~R)
READY
'\
4- tPHL(¢~IDACK)
U-
MEMW/I/O W
~h('II~A)
-.l..~
~ ~ ~tPHLI9l~ASTB)
->
OACKo-
-;0
tPHL(ASTB~WE)
R)
,
----------
Slave Mode
CS
--tW(WE)
k------...
tpVZ( ¢-R)
~"
I \
n
CS
________-J~~------_+----~I~--------______________- J
00-07----------------------~,~__~~~~--------
I/OW
RESET
tSU(Vcc-RST)
v CC
~"\.
If
Read
tSU(CS~W)
00-07
I
(Reference voltage: "H" = 2V "L" = O.8V)
Write
Ao-A7
tW(R)
\.. kd
RDY)
tPLH"- 'CiMARK) ~PHLt¢- 'CiMARK)
TC/MARK
tpVZ(¢~A)
~"
EI
N
tPZV(¢~DQ)4
8 -88
h
r--t=.tSU(¢~A)
II.;
______---I
• MITSUBISHI
"ELECTRIC
MITSUBISHI LSls
MSL82S7P-S
PROGRAMMABLE DMA CONTROLLER
I
81
I
82
I
83
I
84
I
81
I
81
I
80
I
81
I
82
I
83
I 8W I
I
8W
84
I
81
I
81
I
81
CLK
~
______________
~U-
________
~~
____
~
_________________ DRQo-DRQ3
HRO
~------~--~--------+---------~,
'-----
HLDA
AEN
~
_ _ _ AO-A7
(LOWER ADDRESSES)
~*-
____ ____________________ DO-D7
~
(UPPER ADDRESSES)
~ _ _ _ _...LL
~-f------+---
-- - - -
AD8TB
DACKoDACK3
~--------MEMR/I/OR
~_ _ _ _ _
MEMR/I/OW
READY
~----------
o
/
\
TC/MARK
Note 10:
The center line indicates a floating
(high-impedance) state.
• MITSUBISHI
"'ELECTRIC
8-89
II
MITSUBISHI LSls
M5L8257P-S
PROGRAMMABLE DMA CONTROLLER
APPLICATION EXAMPLE
As-A'5
r-________________________-+8______________~--------~~~16~Ao-A,5
.-__________~8L-----__~--~8--~J
~--~~--~
~5V
ALE ~ STB
DO,-DOs
13
T
D S2 t--'-'----1.--JV\f\r-~
M5L8212P
W
CLR
~~~~~
DS1
1'
2L.M
__
D____
DI,-Dls
ADo-ADs
~
}8
8
r-____+-____
~1------~----------------~~------~8------~DO-D7
-JVVIr- 5V
M5L8085AP. S
RD
WR
RESET
RESETIN
2
o--{
-=- A, 74LS257
~B,
4
..2.. A
2
6
-=- B2
£":
.....f - -__.-I-.;..11~A3
~ B3
0, p--:--t-t-----------...,------+--l---------------- ME M R
7
02 p.:.- - - t + - - - - - - - - - - + . , - - - + - l - - - - - - - - - - - - - - - I/OR
03p.:9~+----------++t-+~1-------------- -;:;;:=---;:-;,-:;:;12
14
10/M~13A4
B4
L...-...;..;...
HOLD
1
HOLDA _____
MEMW
04
I/OW
OE
15
SEL(B)
CLK(OUT) -
READY
RESET OUT -
MEMR
p2.
MEMW:rLI/O R
o-L-
I/O W D-.!2=---__....J
M5L8257P-5
Ao - A 7 t-__-1-8'--~
DRQo ~1,-,,9________-+-_____ DROo
'--____--+-+-1;..:0-1 H RQ
'--_____~~7~HLDA
~
12
---v~~o---f-+-+I C LK
DACKo
25
DRO,
18
DRO,
DACk,
24
DACK,
DRQ2
17
DR02
'--________-+-+-13~RESET
DACK2~p~1~4'--------4_----~~DACK2
TC __----+-+..;;.36"-1 TC
DR03
MARK _------i1-+---'5'-! MAR K
16
9
~ 8
t
13 14' 11
DS2 CLR STB
~
DI,
DO,
Dis
DOs
\
\ t--------------.J
M5L8212P
MD
DS,
1 '1
8-90
DR03
DACK3~1~5--------~--~~DACK3
AEN
L+----...
DACKo
• MITSUBISHI
"ELECTRIC
MITSUBISHI LSls
MSL82S9AP
PROGRAMMABLE INTERRUPT CONTROLLER
DESCRIPTION
The M5L8259AP is a programmable LSI for interrupt control. It is fabricated using N-channel silicon-gate ED-MOS
technology and is designed to be used easily in connection
with an M5L8080AP, M5L8085AP or M5L8086S.
PIN CONFIGURATION (TOP VIEW)
CHIP
ST~~8t
cs -
1
aNTRaL 1tf~(;t WR -
2
1~~t9 Fill -
3
aNTRaL
Vee (SV)
2 -
Ao ADDRESS INPUT
_
INTERRUPT
-INTA ACKNOWLEDGE
INPUT
FEATURES
•
•
•
Single 5V power supply
CALL instruction to the CPU is generated automatically
Priority, interrupt mask and vectored "ddress for each
interrupt request input are programmable
•
Up to 64 levels of interrupt requests can be controlled
by cascading with M5L8259AP
•
•
•
INTERRUPT
REQUEST
INPUTS
BI IRECTIONAL
DATA BUS
19 _IR,
18 _IRa
INTERRUPT
REQUEST
17 -INT OUTPUT
Polling functions
TTL compatible
I nterchangeable with I ntels P8259A in pin configuration and electrical characteristics.
16 ..... %-EN
r~tU\~lNRRBGL~AM
BUFFER OUTPUT
~_ _ _ _ _-,1~5 ..... CASz ~tNS~tDE
Outline 28P4
APPLICATIONS
• The M5L8259AP can be used as an interrupt controller for CPUs M5L8080AP, M5L8085AP and M5L8086S
FUNCTIONS
The M5L8259AP is a device specifically designed for use
in real time, interrupt driven microcomputer systems. It
manages eight levels or request and has built-in features
for expandability to other M5L8259AP's.
The priority and interrupt mask can be changed or reconfigured at any time by the main program.
When an interrupt is generated because of an interrupt
request at 1 of the pins, the M5L8259AP based on the
mask and priority will output an INT to the CPU. After
that, when an I NT A signal is received from the CPU or
the system controller, a CALL instruction and a programmed vector address is released onto the data· bus.
BLOCK DIAGRAM
INTERRUPT
ACKNOWLEDGE INPUT
INTERRUPT
REQUEST OUTPUT
BIDIRECTIONAL DATA BUS
WR ITE CONTROL INPUT
INTERRUPT
REQUEST INPUTS
READ CONTROL INPUT
ADDRESS INPUT
CHIP SELECT INPUT
CS 1 }--_ _. J
CASO 12
CASCADE LINES
t
CAS1 13
CAS215
(~t¥cEP~8rtl~IMd~WJt
SP lEN 16}E---....J
• MITSUBISHI
"ELECTRIC
8-91
8
MITSUBISHI LSls
MSL82S9AP
PROGRAMMABLE INTERRUPT CONTROLLER
PIN DESCRIPTION
Symbol
Input or
output
Pin name
Functional significance
OS
Chip select input
Input
WR
Write control input
Input
Command write control input from the CPU
RO
Read control input
Input
Data read control input for the CPU
07- 0 0
Bidirectional data bus
Input/
output
Data and commands are transmitted through this bidirectional data bus to and from the CPU.
OAS2OASo
Cascade lines
Input/
output
vidual slave. The master will enable the corresponding slave to release the device routine address during bytes 2 and 3 of
SP/EN
Slave program input/
Enable buffer output
Input/
output
SP: In normal mode, a master is designated when SP/EN=l and a slave is designated when
INT
Interrupt request output
Output
This pin goes high whenever a valid interrupt is asserted.
I nterrupt request input
Input
This input is active at low-level, but may be at high-level during interrupt request input and interrupt processing.
These pins are outputs for a master and inputs for a slave. And these pins of the master will be able to address each indi-
INTA.
SP/EN=O.
EN: In the buffered mode, whenever the M5L8259AP's data bus output is enabled, its SP/EN pin will go low.
The asynchronous interrupt inputs are active at high-level. The interrupt mask and priority of each interrupt input can
be changed at any time. When using edge triggered mode, the rising edge (low to high) of the interrupt request and the
high-level must be held until the first I NT A. For level triggered mode, the high-level must be held until the first I NTA.
I nterrupt acknowledge
input
Ao
Input
vectored address onto the data bus.
Input
Ao address input
When an interrupt acknowledge (I NT A) from the CPU is received, the M5L8259AP releases a CALL instruction or
This pin is normally connected to one of the address lines and acts in conjunction with the
CS,
WR and RD when
writing commands or reading status registers.
Table 1 M5L8259AP basic operation
OPERATION
The M5L8259AP is interfaced with a standard system bus
as shown in Fig. 1 and operates as an interrupt controller.
Ao
04
03
RO WR OS
Input operation (read)
0
0
1
0
I R R, ISR or interrupting level .... data bus
1
0
1
0
IMR.... Data bus
1
0
0
Data bus ....OCW2
Output operation (write)
16
ADDRESS BUS
CONTROL BUS
0
0
0
0
0
1
1
0
0
Data bus.... OCW3
0
1
X
1
0
0
Data bus.... ICWl
1
X
X
1
0
0
Data bus-->OCW1, ICW2, ICW3, :CW4
X
X
X
1
1
0
Data bus .... High-impedance
X
X
X
X
X
1
Data bus .... High-impedance
Disable function
DATA BUS
CS
C~CADE{
LINES
Ao
CASo
CAS,
CASz
RD
WR
INT
INTA
M5L8259AP
SP/EN
SLAVE PROGRAM INPUT/
ENABLE BU FFER OUTPUT
INTERRUPT REYQUEST INPUTS
Fig. 1 The M5L8259AP interfaces to standard system bus.
8-92
• MITSUBISHI
.... ELECTRIC
MITSUBISHI LSls
M5L8259AP
PROGRAMMABLE INTERRUPT CONTROLLER
Interrupt Sequence
1. When the CPU is an M5L8080AP or M5L8085AP:
(1) When one or more of the interrupt request inputs
are raised high, the corresponding I R R bit(s) for the
high-level inputs will be set.
(2) Mask state and priority levels are considered and, if
appropriate, the M5L8259AP sends an INT signal
to the CPU.
(3) The acknowledgement of the CPU to the I NT signal, the CPU issues an INTA pulse to the M5L8259AP.
(4) The ISR bit corresponding to the interrupt request
input is set upon receiving an INTA from the CPU,
and the corresponding I R R bit is reset. A CALL instruction is released onto the data bus.
(5) A CALL is a 3-byte instruction, so additionallNTA
pulses are issued to the M5L8259AP from the CPU.
(6) These two INTA pulses allow the M5L8259AP to
release the program address onto the data bus. The
low-order 8-bit vectored address is released at the
second I NTA pulse and the high-order 8-bit vectored address is released at the third INTA pulse.
(7) This completes the 3-byte CALL instruction and
the interrupt routine will be serviced. The ISR bit
is reset at the end of the third INTA pulse in the
AEOI mode. In the other modes the ISR bit is not
reset until an EOI command is issued.
2. When the CPU is an M5L8086S:
(1) When one or more of the interrupt request inputs
are raised high, the corresponding I R R bit(s) for
the high-level inputs will be set.
(2) Mask state and priority levels are considered and if
appropriated, the M5L8259AP sends an INT signal to the CPU.
(3) As an acknowledgement to the INT signal, the CPU
issues an INTA pulse to the M5L8259AP.
(4) The ISR bit corresponding to the interrupt request
input is set upon receiving the first INT A pulse
from the CPU, and the corresponding I R R bit is
reset. The M5L8259AP does not drive the data
bus, and the data bus goes to high-impedance state.
(5) When the second INTA pulse is issued from the
CPU an 8-bit pointer is released onto the data bus.
(6) This completes the interrupt cycle and the interrupt routine will be serviced. The ISR bit is reset at
the end of the second INTA pulse in the AEOI
mode. In the other modes the ISR bit is not reset
until an EOI command is issued from the CPU.
The interrupt request input must be held at high-level
until the first INTA pulse is issued. If it is allowed to re-
turn to low-level before the first INTA pulse is issued, an
interrupt request in I R 7 is executed. However, in this case
the ISR bit is not set.
Interrupt sequence outputs
1. When the CPU is a M5L8080AP or M5L8085AP:
A CALL instruction is released onto the data bus when
the first I NT A pu Ise is issued. The low-order 8 bits of
the vectored add ress are released when the second INT A
pulse is issued, and the high-order 8 bits are released
when the third INTA pulse is issued. The format of these
three outputs is shown in Table 2.
Table 2 Formats of interrupt CALL instruction and
vectored address
First INTA pulse (CALL instruction)
Os
05
Do
01
Second INT A- pulse (low-order 8-bit of vectored address)
IR
Interval
~
4
07
Os
05
04
03
02
01
Do
IR7
A7
f-----f-IR6
A7
As
As
1
1
1
0
0
A6
A·s
1
1
0
0
0
A6
As
1
0
1
0
0
IR4
A6
A7
f - - - -------+IR3
A6
A7
As
1
0
0
0
0
As
0
1
1
0
0
IRs
A7
IR2
A7
A6
As
0
1
0
0
0
IR1
A7
A6
As
0
0
1
0
0
IRa
A7
A6
As
0
0
0
0
0
07
06
05
04
03
02
01
Do
IR7
A7
As
1
1
1
0
0
0
IRs
A7
As
1
1
0
0
0
0
IRs
A7
As
1
0
1
0
0
0
IR4
A7
As
1
0
0
0
0
0
IR 3
A7
A6
0
1
1
0
0
0
IR2
A7
As
0
1
0
0
0
0
IR1
A7
As
0
0
1
0
0
0
IRa
A7
As
0
0
0
0
0
0
IR
-
Interval
~
8
Third INTA pulse (high-order 8 bits of vectored address)
• MITSUBISHI
..... ELECTRIC
Os
05
A13
01
Do
As
8-93
II
MITSUBISHI LSls
M5L8259AP
PROGRAMMABLE INTERRUPT CONTROLLER
2. When the CPU is a M5L8086S:
The data bus goes to a high-impedance state when the first
I NTA pulse is issued. Then the pointer T ,"'T 0 is released when the next INT A pulse is issued. The content
of the pointer T ,-To is shown in Table 3. The T 2 "'To
are a binary code corresponding to the interrupt request
level, AlO-A s are unused and ADI mode control is
ignored.
Table 3 Contents of interrupt pointer
Second I NTA pulse (8-bit pointer)
03
T3
02
01
Do
1
1
1
T4
T3
1
1
T4
T3
1
0
1
Ts
T4
T3
1
G
0
T6
Ts
T4
T3
0
1
1
T4
T3
0
1
0
T7
T6
T6
Ts
Ts
T4
T3
0
0
1
T7
T6
Ts
T4
T3
0
0
0
07
06
Os
T6
IR6
T7
T7
T6
Ts
Ts
IRs
T7
T6
Ts
IR4
T7
T6
IR3
T7
IR2
T7
IR1
IRa
IR7
04
T4
0
Interrupt Request Register (lRR), In-service Register (lSR)
As interrupt requests are received at inputs I R,"'I Ro , the
corresponding bits of I R R are set and as an interrupt request is serviced the corresponding bit of ISR is set. The
I R R is used to store all the interrupt levels which are requesting service, and the ISR is used to store all the interrupt levels which are being serviced. The status of these
two registers can be read. These two registers are connected
through the priority resolver.
An interrupt request received by I Rn is acknowledged
on the leading edge when in the edge triggered mode or
it is acknowledged on the level when in the level triggered
mode. After that an INT signal.is released and the interrupt
request signal is latched in the corresponding I R R bit if
the high-level is held until the first INTA pulse is issued. It
is important to remember that the interrupt request signal
must be held at high-level until the first INTA pulse is
issued.
The interrupt request latching in the I R R causes a signal to be sent to the priority resolver unless it is masked
out. When the priority resolver receives the signals it selects
the highest priority interrupt request latched in I R R. The
ISR is set when the first INTA pulse is issued while the
corresponding bit of IRR is reset and the other bits of IRR
are unaffected.
The bit of ISR that was set is not reset during the interrupt routine, but is reset at the end of the routine by the
EOI command (end of interrupt) or by the last INTA pulse
in AEOI mode.
8-94
Priority Resolver
The priority resolver examines all of the interrupt requests
set in I R R to determine and selects the highest priority.
The ISR bit corresponding to the selected (highest priority)
request is set by the INT A pulse.
Interrupt Mask Register (lMR)
The contents of the interrupt mask register are used to
mask out (disable) interrupt requests of selected interrupt
request pins. Each terminal is independently masked so that
masking a high priority interrupt does not influence the
lower or higher priority interrupts. Therefore the content.s
of IMR selectively enable reading.
Interrupt Request Output (lNT)
The interrupt request output connects directly to the
interrupt input of the CPU. The output level is compatible
with the input level required for the CPUs.
Interrupt Acknowledge Input (lNTA)
The CALL instruction and vectored address are released
onto the data bus by the I NT A pulse.
Data Bus Buffer
The data bus buffer is a 3-state bidirectional data bus buffer that is used to interface with the system bus. Write commands to the M5L8259AP, CALL instructions, vectored addresses, status information, etc. are transferred through
the data bus buffer.
Read/Write Control Logic
The read/write control logic is used to control functions
such as receiving commands from the CPU and supplying
status information to the data bus.
Chip Select (CS)
The M5L8259AP is selected (enabled) when CS is at lowlevel, but during interrupt request input or interrupt processing it may be high-level.
Write Control Input (WR)
When WR goes to low-level the M5L8259AP can then write.
Read Control Input (RD)
When RD goes low status information in the internal register of the M5L8259AP can be read through the data bus.
Address Input (Ao)
The address input is normally connected with one of the
address lines and is used along with WR and RD to control
write commands and reading status information.
Cascade Buffer/Comparator
The cascade buffer/comparator stores or compares identification codes. The three cascade lines are output when the
M5L8259AP is a master or input when it is a slave. The
identification code on the cascade lines select it as master
or slave.
• MITSUBISHI
.... ELECTRIC
MITSUBISHI LSls
M5L8259AP
PROGRAMMABLE INTERRUPT CONTROLLER
PROGRAMMING THE M5L8259AP
ICW3
The M5L8259AP is programmed through the Initialization Command Word (ICW) and the operational command
word (OCW). The following explains the functions of these
two commands.
When SNG L=1 it indicates that only a single M5L8259AP
is used in the system, in which case ICW3 is not valid. When
SNG L=O, ICW3 is valid and indicates cascade connections
with other M5L8259AP devices. In the master mode, a
"1" is set for each slave.
When the CPU is an M5L8080AP or M5L8085AP the
CALL instruction is released from the master at the first
INT A pulse and the vectored address is released onto the
data bus from the slave at the second and third I NT A
pulses.
When the CPU is a M5L8086S the master and slave are
in high-impedance at the same time and the pointer is released onto the data bus from the slave at the next I NT A
pulse.
The master mode is specified when SP/EM pin is highlevel or BUF=1 and M/S=1 in ICW4, and slave mode is specified when SP/EM pin is low-level or BUF=l and M/S=O in
ICW4. In the slave mode, three bits 10 2 -I Do identify the
slave. And then when the slave code released on the cascade
lines from the master, matches the assigned 10 code, the
vectored address is released by it onto the data bus at the
next I NTA pulse.
Initialization Command Words (lCWs)
The initialization command word is used for the initial setting of the M5L8259AP. There are 4 commands in this
group and the following explains the details of these four
commands.
ICWl
The meaning of the bits of ICW1 is explained in Fig. 3
along with the functions. ICW1 contains vectored address
bits A 7 -A s , a flag indicating whether interrupt input is
edge triggered or level triggered, CALL address interval,
whether a single M5L8259AP or the cascade mode is
used, and whether ICW4 is required or not.
Whenever a command is issued with Ao=O and 0 4 =1,
this is interpreted as leW1 and the following will automaticallyoccur.
(a) The interrupt mask register (IMR) is cleared.
(b) The interrupt request input I R 7 is assigned the lowest
priority.
(c) The identification code for slave mode is set to 7.
(d) The special mask mode is cleared and the status read
is set to the interrupt request register (IRR).
(e) When IC4=O all bits in ICW4 are set to zero.
ICW2
ICW2 contains vectored address bits At 5 -As or interrupt type T 7-T 3, and the format is shown in Fig. 3.
ICW4
Only when IC4=1 in ICW1 is ICW4 valid. Otherwise all bits
are set to zero. When ICW4 is valid it specifies special fully
nested mode, buffer mode master/slave, automatic EOI
and microprocessor mode. The format of ICW4 is shown in
Fig. 3.
Fig. 2 Initialization
sequence
• MITSUBISHI
"'ELECTRIC
8-95
II
:
MITSUBISHI LSls
MSL82S9AP
PROGRAMMABLE INTERRUPT CONTROLLER
ICW1
Ao
I
0
06
1
A7
I
A6
00
05
I
As
I
I
I
1
I L TIM I
AD I
I SNGL I IC4 I
I
.11: ICW4 NEEDED
0: NO ICW4 NEEDED
I
I
I
I
I
1
I
1: SINGLE
0: CASCADE MODE
1: CALL ADDRESS INTERVAL IS 4
0: CALL ADDRESS INTERVAL IS 8
1
1: LEVEL TRIGGERED MODE
0: EDGE TRIGGERED MODE
I VECTOR
I (A,-A s )
1
ADDRESS
LOW-ORDER
BITS
ADDRESS
HIGH-ORDER
BITS
ICW2
06
07
Ao
04
05
02
03
00
01
VECTOR
(A\s-A s ) OR INTERRUPT TYPE (T,-E 3 )
ICW3
Ao
(MASTER DEVICE)
07
06
05
04
03
02
01
00
57
56
Ss
54
53
S2
51
50
1: IR n INPUT HAS A SLAVE
0: IR n INPUT DOES NOT HAVE A SLAVE
ICW3
Ao
l
1
07
1
0
06
I
0
(SLAVE DEVICE)
04
05
1
0
I
0
03
I
0
01
02
I
10 2
I
101
I
00
I
100
I
SLAVE IDENTIFICATION CODE
I
ICW4
Ao
07
06
Os
04
03
02
01
0
1
2
3
4
5
6
7
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
o
0
o
0
1
1
1
1
00
1: M5L8086S MODE
0: M5L8080AP OR M5L8085AP MODE
1: AEOI MODE
0: NORMAL EOI MODE
§±B
x
NON BUFFERED MODE
1
0
BUFFERED MODE/SLAVE
1
1
BUFFERED MODE/MASTER
1: SPECIAL FULLY NESTED MODE
0: NOT SPECIAL FULLY NESTED MODE
Fig. 3 Initialization command word format
8-96
• MITSUBISHI
;"ELECTRIC
I
MITSUBISHI LSls
MSL82S9AP
PROGRAMMABLE INTERRUPT CONTROLLER
Operation Command Words (OCWs)
along with their functions. Each bit of IMR can be in-
The operation command words are used to change the con-
dependently changed (set or reset) by OeWl.
tents of 1M R, the priority of interrupt request inputs and
OCW2
the special mask. After the lew are programmed into the
The OeW2 is used for issuing EOI commands to the M5L-
M5L8259AP, the device is ready to accept interrupt re-
8259AP and for changing the priority of the interrupt
quests. There are three types of oews; explanation of
request inputs.
each follows, and the format of oews is shown in Fig. 4.
OCW3
OCW1
The OeW3 is used for specifying special mask mode, poll
The meaning of the bits of DeWl are explained in Fig. 4
mode and status register read.
OCW1
1: INTERRUPT MASK SET
0: INTERRUPT MASK RESET
OCW2
I
Ao
07
06
0
R
SL
I
I
Os
I EOI
I
04
03
02
0
0
L2
I
I
01
I
L1
00
I
La
I
10 LEVEL TO BE ACTED UPON
I
I
I
0
1
2
3
4
5
6
a
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
7
I
t
f
0
0
1
NON·SPECIFIC EOI
0
1
1
SPECIFIC EOI (RESETS ISR BITS L2 -L o l
1
0
1
ROTATE ON NON·SPECIFIC EOI
1
0
0
SETS AUTOMATIC ROTATION FLlp·FLOP
0
0
0
RESET AUTOMATIC ROTATION FLlp·FLOP
EOI
? AUTOMATIC
1
1
1
ROTATE ON SPECIFIC EOI (RESETS ISR BIT L 2 -L o l
1.
1
1
0
SETS PRIORITY COMMAND (SET LOWEST PRIORITY BIT L 2 -L o l
j
0
1
0
NO OPERATION
ROTATION
SPECIFIC ROTATION
OCW3
06
Ao
r
0
I
-
00
Os
IESMM SMM
I
0
I
1
I
P
RR
RIS
I
I
w
0
-'X
NO OPERATION
1
0
SETS STATUS READ REGISTER IN IRR
1
1
SETS STATUS READ REGISTER IN ISR
1 POLL COMMAND
0: NO POLL COMMAND
NO OPERATION
0
X
1
0
RESET SPECIAL MASK MODE
1
1
SETS SPECIAL MASK MODE
Fig. 4 Operation command word format
• MITSUBISHI
"ELECTRIC
8-97
MITSUBISHI LSls
MSL82S9AP
PROGRAMMABLE INTERRUPT CONTROLLER
FUNCTION OF COMMAND
Interrupt masks
The mask register contains a mask for each individual interrupt request. These interrupt masks can be changed by programming using OCW1.
Special mask mode
When an interrupt request is acknowledged and the ISR bit
corresponding to the interrupt request is not reset by EOI
command (which means an interrupt service routine is executing) lower priority interrupt requests are ignored.
In special mask mode interrupt requests received at
interrupt request inputs which are masked by OCW1 are
disabled, but interrupts at all levels that are not masked
are possible. This means that in the mask mode all level
of interrupts are possible or individual inputs can be selectively programmed so all interrupts at the selected inputs
are disabled. The masks are stored in IMR and special mask
is set/reset by executing OCW3.
normal fully nested mode, a serviced slave is locked out
from the master's priority, and so higher priority interrupts from the same slave are not serviced.
2. When an interrupt from a certain slave is being serviced
the software must check ISR to determine if there are
additional interrupts requests to be serviced. If the
ISR bit is 0 the EOI command may be sent to the master too. But if it is not 0 the EOI command should not
be sent to the master.
Poll mode
The poll mode is useful when the internal enable flip-flop
of the microprocessor is reset, and interrupt input is disabled. Service to the device is achieved by a programmer
initiative using a poll command. In the poll mode the M5L8259AP at the next RD pulse puts 8 bits on the data bus
which indicates whether there is an interrupt request and
reads the priority level. The format of the information on
the data bus is as shown below.
Buffered mode
The buffered mode will structure the M5L8259AP to send
an enable signal on SP/EN to enable the data bus buffer,
when the data bus requires the data bus buffer or when
cascading mode is used. I n this mode, when data bus output of the M5L8259AP is enabled, the SP/EN output becomes active. This allows the M5L8259AP to be programmed whether it is a master or a slave by software. The buffered mode is set/reset by executing ICW4.
Fully nested mode
The fully nested mode is the mode when no mode is specified and is the usual operational mode. In this mode, the
priority of interrupt request terminals is fixed from the
lowest I R7 to the highest I Ro. When an interrupt request
is acknowledged the CALL instruction and vectored address
are released onto the data bus. At the same time the ISR bit
corresponding to the accepted interrupt request is set.
This ISR bit remains set until it is reset by the input of an
EOI command or until the trailing edge of last I NTA pulse
in AEOI mode. While an interrupt service routine is being
executed, interrupt requests of same or lower priority are
disabled while the bit of ISR remains set. The priorities can
be changed by OCW2.
Special fully nested mode
The special fully nested mode will be used when cascading
is used and this mode will be programmed to the master by
ICW4. The special fully nested mode is the same as the fully
nested mode with the following two exceptions.
1. When an interrupt from a certain slave is being serviced,
this slave is not locked out from the master priority
logic. Higher priority interrupts within the slave will be
recognized by the master and the master will initiate
an interrupt req uest to the CPU. In general in the
8-98
Ds
D1
Do
Wo
Binary code of the highest priority
level requesting services.
When 1=0 (no interrupt request), W2 ""W O is 111. The
poll is valid from WR to RD and interrupt is frozen. This
mode can be used for processing common service routines
for interrupts from more than one line and does not require
any INTA sequence. Poll command is issued by setting P=l
in OCW3.
End of interrupt (EOI) and specific EOI (SEOI)
An EOI command is required by the M5L8259AP to reset
the ISR bit. So an EOI command must be issued to the
M5L8259AP before returning from an interrupt service
routine.
When AEOI is selected in ICW4, the ISR bit can be
reset at the trailing edge of the last I NT A pulse. When
AEOI is not selected the ISR bit is reset by the EOI command issued to the M5L8259AP before returning from an
interrupt service routine. When programmed in the cascade
mode the EOI command must be issued to the master once
and to corresponding slave once.
There are two forms of EOI command, specific EOI and
non-specific EO I. When the M5L8259AP is used in the fully
nested mode, the ISR bit being serviced is reset by the EOI
command. When the non-specific EOI is issued the M5L8259AP will automatically reset the highest ISR bit of
those that are set. Other ISR bits are reset by a specific EOI
and the bit to be reset is specified in the EOI by the program. The SEOI is useful in modes other than free nested
• MITSUBISHI
.... ELECTRIC
MITSUBISHI LSls
MSL82S9AP
PROGRAMMABLE INTERRUPT CONTROLLER
mode. When the M5L8259AP is in special mask mode
ISR bits masked in IMR are not reset by EOL EOI and
SEOI are selected when OCW2 is executed.
Automatic EOI (AEOI)
In th~ AEOI mode the M5L8259AP executes non-specific
EOI command automatically at the trailing edge of the last
I NT A pulse. The AEOI mode is not required within a single
M5L8259AP, but it is useful when a nested multilevel interrupt structure is expected. When AEOI==1 in ICW4, the
M5L8259AP is put in AEOI mode continuously until reprogrammed in ICW4.
Automatic rotation
The automatic rotation mode is used in applications where
many interrupt requests of the same level are expected
such as multichannel communication systems. I n this mode
when an interrupt request is serviced, that request is assigned the lowest priority so that if there are other interrupt requests they will have higher priorities. This means
that the next request on the interrupt request being serviced must wait until the other interrupt requests are serviced (worst case is waiting for all 7 of the other controllers
to be serviced). The priority and serving status are rotated
as shown in Fig. 5.
BEFORE ROTATION
IIR4 THE HIGHEST PRIORITY
REQUIRING SERVICE)
15 6
15 7
15 5
154
153
152
151
o
ISR STATUS
LOWEST PRIORITY
PRIORITY STATUS
1
*
7
1
AFTER ROTATION
157
ISR STATUS
6
1
5
0
HIGHEST PRIORITY
1
4
1
3
1
2
11 1 *
0
IIR. WAS SERVICED AND ALL OTHER
PRIORITIES ROTATED CORRESPONDINGLY)
156
155
154
153
152
151
150
1011101010101010
HIGHEST PRIORITY
PRIORITY STATUS
150
1
I
2
LOWEST PRIORITY
* *1
11 1 0 1
7
6
1
5
1
4
1
3
Specific rotation
Specific rotation gives the user versatile capabilities in interrupt controlled operations. It serves in those applications in
which a specific device's interrupt priority must be altered.
As opposed to automatic rotation which automatically
sets priorities, specific rotation is completely user controlled. That is, the user selects the interrupt level that is
to receive lowest or highest priority. Priority changes can be
executed during an EOI command.
Level triggered mode/Edge triggered mode
Selection of level or edge triggered mode of the M5L8259AP is made by ICW1. When using edge triggered mode
not only is a transition from low to high required, but the
high-level must be held until the first INTA. If the highlevel is not held until the first INTA, the interrupt request
will be treated as if it were input on I R 7 , except that the
ISR bit is not set. When level triggered mode is used the
functions are the same as edge triggered mode except that
the transition from low to high is not required to trigger the
interrupt request.
In the level triggered mode and using AEOI mode
together, if the high-level is held too long the interrupt
will occur immediately. To avoid this situation interrupts
should be kept disabled until the end of the service routine
or until the IR input returns low. In the edge triggered ~
mode this type of mistake is not possible because the i n t e r - y
rupt request is edge triggered.
Reading the M5L8259AP internal status
The contents of IRR and ISR can be read by the CPU with
status read. When an OCW3 is issued to the M5L8259AP
and an RD pulse issued the contents of IRR or ISR can be
released onto the data bus. A special command is not
required to read the contents of IMR. The contents of
IMR can be released onto the data bus by issuing an RD
pulse when Ao=1. There is no need to issue a read register
command every ti me the I R R or ISR is to be read. Once a
read register command is received by the M5L8259AP,
it remains valid until it is changed. Remember that the programmer must issue a poll command every time to check
whether there is an interrupt request and read the priority
level. Polling overrides status read when P==1, R R==1 in
OCW3.
Fig. 5 An example of priority rotation
Automatic rotation mode is selected when R==1, EOI==1,
SL==Q in OCW2. The internal priority status is changed by
EOI or AEOI commands. The rotation priority A flip-flop
is set by R=1, EOI==Q and SL=Q which is useful when the
M5L8259AP is used in the AEOI mode.
• MITSUBISHI
~ELECTRIC
8-99
MITSUBISHI LSls
MSL82S9AP
PROGRAMMABLE INTERRUPT CONTROLLER
Cascading
code of the slave through the cascade lines, so the slave will
release the vectored address on the next I NT A pulse.
The cascade lines of the master are nomally low, and will
contain the slave identification code from the trailing edge
of the first INTA pulse to the leading edge of the last
INTA pulse. The master and slave can be programmed to
work in different modes. ICWs, and EOI commands must
be issued twice: once for the master and once for the corresponding slave. Each CS of the M5L8259AP requires an
address decoder.
The M5L8259AP can be interconnected in a system of one
master with up to eight slaves to handle up to 64 priority
levels. A system of three units that can be used with the
M5L8080AP or M5L8085AP is shown in Fig. 6.
The master can select a slave by outputting its identification code through the three cascade lines. The INT
output of each slave is connected to the master interrupt
request inputs. When an interrupt request of one of the
slaves is to be serviced the master outputs the identification
16
ADDRESS BUS
CONTROL BUS
~
DATA BUS
3
8
3
3
8
8
I
os Ao
INT
M5L8259AP
SLAVE
sP!EN
oro
7 6 5
4 3
OS
CASo
CAS, ~ - CAS2 ~2 1 0
t!I!!!!!
r
Ao
M5L8259AP
SLAVE
INT
OS
CASo
CAS,
CAS2
CASo
CAS,
CAS2
5 4 3 2 1 0
SP/EN
7 6
o!o
ttl!!!!I
y
INTERRUPT REQUEST INPUTS
Fig. 6 Cascading the M5L8259AP
8-100
• MITSUBISHI
' " ELECTRIC
SP/EN
I
Vee
Ao
INT
M5L8259AP
MASTER
MJ M6 Ms M4 M3 Mz M, Mo
q! 1 ! t 1
3
MITSUBISHI LSls
MSL82S9AP
PROGRAMMABLE INTERRUPT CONTROLLER
INSTRUCTION SET
.~
Instruction code
Function
Mnemonic
Number
Ao
07
06
05
04
03
02
01
00
ICW4 required?
Interval
Single
Trigger
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
N
N
N
N
N
N
N
N
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
4
4
4
4
8
8
8
8
4
4
4
4
8
8
8
8
E
L
E
L
E
L
E
L
E
L
E
L
E
L
E
L
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
ICW1 A
ICW1 B
ICW1 C
ICW1 D
ICW1 E
ICW1 F
ICW1G
ICW1 H
ICW11
ICW1 J
ICW1 K
ICW1 L
ICW1 M
ICW1 N
ICW10
ICW1 P
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
A7
A7
A7
A7
A7
A7
A7
A7
A7
A7
A7
A7
A7
A7
A7
A7
Ae
Ae
Ae
Ae
Ae
Ae
Ae
Ae
Ae
Ae
Ae
Ae
Ae
Ae
Ae
Ae
As
As
As
As
0
0
0
0
As
As
As
As
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
17
18
19
ICW2
ICW3 M
ICW38
1
1
1
A1S
87
0
A14
8e
0
A13
8s
0
A12
84
0
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
ICW4 A
ICW4 B
ICW4 C
ICW4 D
ICW4 E
ICW4 F
ICW4 G
ICW4 H
ICW41
ICW4 J
ICW4 K
ICW4 L
ICW4 M
ICW4 N
ICW40
ICW4 P
ICW4 NA
ICW4 NB
ICW4 NC
ICW4 ND
ICW4 NE
ICW4 NF
ICW4 NG
ICW4 NH
ICW4 NI
ICW4 NJ
ICW4 NK
ICW4 NL
ICW4 NM
ICW4 NN
ICW4 NO
ICW4 NP
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
_0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
52
53
54
55
56
57
58
59
60
61
62
63
64
OCW1
OCW2 E
OCW28E
OCW2 RE
OCW2 R8E
OCW2 R
OCW2 CR
OCW2 R8
OCW3 P
OCW3 RI8
OCW3 RR
OCW38M
OCW3 R8M
1
M7
0
0
Me
0
Ms
1
0
1
0
1
0
1
0
0
0
0
0
0
1
1
0
0
1
1
1
1
0
0
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
All
83
0
Al0
82
1D2
Ag
81
IDl
Ae
80
IDo
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
1
1
1
0
0
0
1
1
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
0
1
1
1
1
0
0
0
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
1
1
1
0
0
0
1
1
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
0
1
1
1
1
0
0
0
1
1
0
M4
0
0
0
0
0
0
0
0
0
0
0
0
M3
0
0
0
0
0
0
0
M2
0
L2
0
L2
0
0
L2
1
1
1
1
1
Ml
0
Ll
0
Ll
0
0
Ll
0
Mo
0
Lo
0
Lo
0
0
Lo
0
0
0
0
0
0
1
0
1
0
1
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
1
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Y
Y
N
N
Y
Y
N
N
Y
Y
N
N
8-bit vectored address
Slave connections (master mode)
Slave identification code (slave mode)
SFNM
1
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
y
Y
Y
Y
y
Y
Y
Y
y
Y
Y
Y
y
Y
Y
Y
BUF
N
N
N
N
N
N
N
N
Y
Y
Y
Y
Y
Y
Y
Y
S
S
S
S
M
M
M
M
N
N
N
N
N
N
N
N
y
Y
Y
Y
y
Y
Y
Y
S
S
S
S
M
M
M
M
AEOI
8086
N
N
N
Y
Y
N
N
N
N
Y
Y
N
N
N
N
Y
Y
N
N
N
N
Y
Y
N
N
N
N
Y
Y
N
N
N
N
Y
Y
N
N
N
N
Y
Y
N
N
N
N
Y
Y
N
Y
Y
Y
Y
Y
y
Y
Y
Y
Y
Y
y
Y
Y
Y
Y
I nterrupt mask
EOI
SEOI
Rotate on Non-Specific EOI command (Automatic rotation)
Rotate on Specific EOI oommand (Specific rotation)
Rotate in AEOI Mode (SE:T)
Rotate in AEOI Mode (CLEAR)
Set priority without EOI
1
0
0
0
Note: Y: yes, N: no, E: edge, L: level, M: master, S: slave
• MITSUBISHI
....,ELECTRIC
8-101
II
MITSUBISHI LSls
MSL8259AP
PROGRAMMABLE INTERRUPT CONTROLLER
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Vee
Supply voltage
VI
I nput voltage
Vo
Output voltage
Pd
Power dissipation
Topr
Operating free-air temperature range
Tstg
Storage temperature range
Limits
Conditions
With respect tc Vss
Unit
-0.5-7
V
-0.5-7
V
-0.5-7
V
1000
rnW
0-70
·C
·C
-65-150
RECOMMENDED OPERATING CONDITIONS
(Ta=0--70·C, unlessotherwisenoted)
Limits
Symbol
Parameter
Min
Vee
Su pply voltage
Vss
Supply voltage
VIH
High-level input voltage
2
VIL
Low-level input voltage
-0.5
Nom
Max
5
5.5
4.5
Unit
V
V
0
ELECTRICAL CHARACTERISTICS
(Ta=0-70·C, Vee, 5V
Vee+0.5
V
0.8
V
± 10%,
Vss=OV,
unless otherwise noted.)
Limits
Symbol
Parameter
Unit
Test conditions
Typ
Min
VOH
High·level output voltage
IOH= -400,uA
2.4
VOH(INT)
High-level output voltage. interrupt request output
IOH=-100,uA
3.5
VOL
Low-level output voltage
IOL=2.2rnA
Icc
Supply current from Vee
Max
V
V
0.45
V
85
rnA
IIH
High-level input current
VI=Vee
-10
10
,uA
IlL
Low-level input current
VI=OV
-10
10
,uA
loz
Off-state output current
VSS=O,
-10
10
,uA
IIH(IR)
High-level input current. interrupt request inputs
VI=VCC
10
,uA
VI=0.45-5.5V
IIL(IR)
Low-level input current. interrupt request inputs
Ci
Output capacitance
Vce=Vss, f=1 MHz, 25rnVrrns, Ta=25·C
10
pF
Ci/O
I nput/output capacitance
Vec=Vss, f=1MHz,25rnVrrns, Ta=25·C
20
pF
TIMING REQUI REMENTS
(Ta=0-70·C, Vcc=5V
Symbol
-
VI= OV
± 10%,
300
,uA
Vss=OV, unless otherwise noted)
Aiternative
symbol
Parameter
Limits
Min
Typ
Max
Unit
tW(W)
Write pulse width
tWLWH
290
ns
tsu (A-W)
Address setup time before write
tAHWL
0
ns
th (W-A)
Address hold time after write
tWHAX
0
ns
tsu (OQ-W)
Data setup time before write
tOVWH
240
ns
th (W-DQ)
Data hold time after write
tWHDX
0
ns
tw (R)
Read pulse width
tRLRH
235
ns
tsu (A-R)
Address setup time before read
tAHRL
0
ns
th (R-A)
Address hold time after read
tRHAX
0
ns
tW(IR)
Interrupt request input width. low-level time. edge triggered mode
t JUH
100
ns
tsu (eAS-INTA)
Cascade setup time after fi\fiA (slave)
tCVIAL
55
ns
trec(W)
Write recovery time
tWHRL
190
ns
treC(R)
Read recovery time
tRHRL
160
ns
8-102
• MITSUBISHI
.... ELECTRIC
MITSUBISHI LSls
M5L8259AP
PROGRAMMABLE INTERRUPT CONTROLLER
SWITCHING CHARACTERISTICS
Symbol
(Ta=0~70°C,
VCC=5V
± 10%,
VSS=OV,
tPZV(R-DQ)
tPVZ(R-DQ)
Data output disable time after read
tpZV(A-DQ)
Limits
Alternative
symbol
Parameter
Data output enable time after read
unless otherwise noted)
Unit
Typ
Min
Max
tRLDV
200
ns
tRHDZ
100
ns
Data output enable time after address
tAHDV
200
ns
tpHL(R-EN)
Propagation time from read to enable signal output
tRLEL
125
ns
tPLH(R-EN)
Propagation time from read to disable signal output
tRHEH
150
ns
tpLH(IR-INT)
Propagation time from interrupt request input to interrupt request output
tJHIH
350
ns
tPLV(INTA-CAS)
Propagation time from Jl'J"fA to cascade output (master)
t IALCV
565
ns
t PZV (CAS-DQ)
Data output enable time after cascade output (slave)
tCVDV
300
ns
Note 1: I NT A signal is considered read signal
ES signal
is considered address signal
I nput pulse level
20ns
Input pulse fall time
20ns
Reference level input
output
Load capacitance
VIH~2V.
V-
2.4--V
0.45-2.4V
Input pulse rise time
O. 45
-A_~_.8_ _ _ _0_._:A-
V 1L ~O.8V
VOH~2V.
VOL ~O.8V
C L ~100pF. where
SP/fN
pin is 15pF
TIMING DIAGRAM
Write Mode
CS, Ao
tsU(A-W)
tW(w)
II
tSU(DQ-W)
Read Mode
CS, Ao
:~
~~
-'~
th (R-A)
tsu(A-R)
tw(R)
\r-
I
¥~
t PVZ(R-DQ)
tPZV(R-DQ)
tpZV(A-DQ)
---------------- --------~~
7F-
:'<;Ir
tpHLCR-EN)
:~-----t PLH(R-EN)
I
\
-'r-
'"
• MITSUBISHI
.... ELECTRIC
8-103
MITSUBISHI LSls
MSL82S9AP
PROGRAMMABLE INTERRUPT CONTROLLER
Interrupt Sequence
IR
INT
--- 0----0-\PLVONOA_CASl \" (CAS-'NTA'
'"
"' I
tPZV(OAS-DQ,;
\
Other Timing
Note
M5L8086S mode
M5L8080AP/M5L8085AP mode
M5 L8086S mode is in high-impedance state, pointer is released during the next I NT A.
When in single M5L8080AP/M5L8085AP mode, data is released by all INTAs. When master, CALL instruc·
tion is released during the first INTA, high impedance state during the second and third lNTA. When slave,
high impedance state during the first INTA, vectored address is released during the second and third INTA. '
8-104
• MITSUBISHI
~ELECTRIC
\
MITSUBISHI LSls
MSL8279P-S
PROGRAMMABLE KEYBOARD/DISPLAY INTERFACE
DESCRIPTION
PIN CONFIGURATION (TOP VIEW)
The M5L8279P-5 is a programmable keyboard and display
interface device that is designed to be used in combina-
Vee
tion with an 8-bit microprocessor such as the Mitsubishi
MELPS 8 CPUs. This device is fabricated with N-channel
(5V)
CLOCK INPUTCLK -+ 3
REQUE~~TSE~~0t
silicon-gate technology and is packed in a 40-pin DI L
RETURN LINE
INPUTS
package. It needs only single 5V power supply.
INT +- 4
R4 -+ 5
I
Rs
-+
1R6 -+
6
7
R7 -+ 8
FEATURES
RESET INPUT RESET
•
Output enable time after read (max)
200ns
Output enable time after address (max)
250ns
Clock cycle time (min)
320ns
-+ 9
READ S~~~5f RD -+ 10
M5L 8279P-5
Parameter
WRITE S~~~5f WR -+ 11
Do
++
12
BIDIRECTIONAL
DATA BUS
Single 5V power supply
•
Keyboard mode
•
•
•
Sensor mode
Strobed entry mode
I nternally provided key bounce protection circuit
•
Programmable debounce time
(OV)
Outline 40P1
•
2-key/N-key rollover
FUNCTION
•
8-character keyboard FIFO
The total chip, consisting of a keyboard interface and a
•
I nternally contained 16 X 8-bit display RAM
•
•
Programmable right and left entry
I nterchangeable with Intel's 8279/8279-5 in pin configuration and electrical characteristics
display interface, can be programmed by eight 8-bit
commands.
The keyboard portion is provided with a 64-bit key
debounce buffer and an 8 X 8-bit FIFO. It operates in
anyone of the scanned keyboard mode, scanned sensor
mode or strobed entry mode.
APPLICATIONS
•
Microcomputer I/O device
•
64 contact key input device for such items as electron-
The display portion is provided with a 16 X 8-bit display RAM that can be organized into a dual 16 X 4
configuration. Also, an 8-digit display configuration is
possible by means of programming.
ic cash registers
•
Dual 8- or single 16-alphanumeric display
BLOCK DIAGRAM
RESET CLOCK
INTERRl'PT
R~~~~ '~~~T ~----='----=--~"------C=-----=-D~o' REQU~~~ OUTPUT
9
3
-
12
4
CONTROL/DATA SELECT INPUT
CHIP SELECT INPUT
os
22
WRITE STROBE INPUT WR 11
READ STROBE INPUT RD 10
I
RETURN LINE INPUTS
I
31
-
,OA3 OA2 OAI OAo"OB3 OB2,OBI OBo, BLA~'NG
DbSJTLt'JT\f')
S
Db JTLt'JA(3)
___ J
23
8'3t~t
• MITSUBISHI
.... ELECTRIC
~
SCAN TIMING
OUTPUTS
8-105
MIT SUB ISH I Lsis
MSL8279P-S
PROGRAMMABLE KEYBOARD/DISPLAY INTERFACE
PIN DISCRIPTON
Pin
Name
Input or
output
Do-D7
Bidirectional data bus
In/out
CLK
Clock input
In
Clock signal from the system which is used to generate internal timing
RESET
Reset input
In
Resets the chip when this signal is high After the reset it assumes 8-digit. left-entry. encode display. and 2-key rollover
mode. and the prescale value of the clock becomes 31 The display RAM. however. is not cleared.
CS
Chip select input
In
Chip select is enabled when this signal is low
Control/data select input
In
When this signal is high. it indicates that the signals in and out are either command (in) or status (out). When low. it
indicates they are data (in/out)
AO
Functions
All data and commands between the CPU and the chip are transferred through these lines
RD
Read strobe input
In
Functions to control data transfer to the data bus
WR
Write strobe input
In
Functions to control command/data transfer from the data bus
IN T
Interrupt request output
Out
When there is any data in the FIFO during the keyboard mode or the strobed mode. this signal turns high-level so as
to request interrupt to the CPU. It turns low each time data is read. but if any data remains in the FIFO it will turn
high again and request interrupt to the CPU
So - S 3
Scan timing outputs
Out
These signals are used to scan the key switch. the sensor matrix. or the display digit. They can be either decoded or
encoded. but it requres an external decoder in the encode mode. Signals So - S 3 are all turned to low-level when
RESET is high.
R a- R 7
Return line inputs
In
These are the return lines which are connected with the scan lines through the keys or sensor switches. and are used
for 8-bit input in the strobed entry mode. They are provided with internal pullups to maintain them high until a switch
closure pulls one low. They become active at low-level
SHIFT
Shift input
In
In the keyboard mode. the shift input becomes the s'econd highest bit of the key input information and is stored in the
FIFO. ThiS input is ignored in the other modes. It is constantly kept at high-level by an internal pull resistor
C NT L
Control input
In
In the keyboard mode. the control Input becomes the most significant bit of the key input information and is stored in
the FIFO. The signal IS active at high-level. In the strobed entry mode. it becomes the strobe signal and stores the
return input data in the FIFO at the rising edge of the input It affects nothing internal in the sensor mode. It is
constantly kept at high-level by an internal pullup resistor
OAo-OA3
OBo-OB3
Display (A) and
(B) outputs
Out
These output ports can be used either as a dual 4-bit port or a single 8-bit port depending on an application. and the
contents of the display RAM are output synchronizing with the scan timing Signals. These two 4-bit ports may be
blanked independently. Blanking may be activated with either high- or low-level signal by means of clear command
BD
Blanking display output
Out
This signal is used in preventing overlapped display during digit switching It also may be brought to low-level by display
blanking command
OPERATION
ration. Also, an a-digit display configuration is possible by
Of the three operating modes, the keyboard mode is the
means of programming. Input to the register can be
most common, and allows programmed 2-key lockout and
performed by either left or right entry modes. I n the auto
N-key rollover. Encoded timing signals corresponding with
increment mode, read and write can be carried out after
key input are stored in the FIFO through the key-
designating the starting address only.
debounce logic, and the debouncing time of the key
Both the keyboard and display sections are scanned by
is also programmable. I n the sensor mode, the contents of
common scan timing signals that are derived from the basic
the a
x
a key contacts are constantly stored in the FIFO/
clock pulse. This frequency-dividing ratio is changeable by
sensor RAM, generating an interrupt signal to the CPU each
means of programming.
time there is a change in the contents. I n the strobed entry
modes for the scanning mode; timing Signals that are
mode, the CNTL input signal is used as a strobe for storing
decoded from the lower 2 bits of the scan counter are output in the decode mode, while the 4-bit binary output from
the a return line inputs to the FI Fa/sensor RAM.
The display portion is provided with a 16 X a-bit display
the scan counter is decoded externally in the encode mode.
RAM that can be organized into a dual 16 X 4-bit configu-
8-106
There are decode and encode
• MITSUBISHI
"ELECTRIC
MITSUBISHI LSls
MSL8279P-S
PROGRAMMABLE KEYBOARD/DISPLAY INTERFACE
COMMAND DESCRIPTION
There are eight commands provided for programming the
operating modes of the M5L8279P. These commands are
sent on the data bus with the signal CS in low-level and the
signal Ao in high-level and are stored in the M5L 8279P at
the rising edge of the signal WR.
1
0
1
0
1
0
1
0
LSB
1
11
0
1
1
1
AliA
LSB
1A 1A
1
A 1
This command is used to specify that the following data
readout (CS·Ao·RD) is from the display RAM. As long as
1
0
1
K
1
K
1
K
commands are necessary.
The data AAAA is the value with which the display RAM
1
read/write counter is set, and it specifies the address of the
DD (Display mode set command)
00
Code:
data is to be read from the display RAM, no additional
1 . Mode Set Command
MSB
Code:
4. Read Display RAM Command
MSB
display RAM to be read or written next.
8-8-bit character display-left entry
AI is the auto-increment flag. Turning AI to "1" makes
o1
16-8-bit character display-left entry1
10
8-8-bit character display-right entry
1 1 16-8-bit character display-right entry
the address automatically incremented after the second
read/write operation. This auto-increment bit does not
affect the auto-increment of F I Fa readout in the sensor
KKK (Keyboard mode set command)
mode.
o0 0
o0 1
Encoded display keyboard mode -
2-key lockout 1
Decoded display keyboard mode -
2-key lockout
o10
o1 1
Encoded display keyboard mode Decoded display keyboard mode -
N-key rollover
N-key rollover
1 00
Encoded display, sensor mode
With this command, following display RAM read/write
10 1
Decoded display, sensor mode
addressing is achieved without changing the data readout
110
Encoded display, strobed entry mode
source (FIFO or display RAM). Meaning of AI and AAAA
111
Decoded display, strobed entry mode
0
1
0
1
1
1
Code:
LSB
11 1 0 1 0 1 AliA 1 A 1 A
1
A 1
6. Display Write Inhibit/Blanking Command
2. Program Clock Command
MSB
1
MSB
are identical with read display RAM command.
Note1: Default after reset.
Cod e:
5. Write Display RAM Command
MSB
LSB
pip pip p
1
1
Code:
1
11
LSB
1
0 11 1 X
IIW IIW IBLIBLI
A
B
A
:
x =Don't care
B
The external clock is divided by the prescaler value PPPPP
The IW is a write inhibit bit to the display RAM that
designated by this command to obtain the basic internal
corresponds with the output A or B. I nh ibit is activated by
turning the IW "1".
frequency.
When the internal clock is set to 100kHz, it will give a
5.1 ms keyboard scan time and
8 DECODER
M5L8279P-5
8-BIT
MICROPROCESSOR
SYSTEM
--
RO
COWAOL
I
-
WR
10
11
9
RESET
3 (Note 9)
RO
4
WR
SO-S3
SCAN LINE
4
RESET
--
ADDRESS BUS
I
CS
22
Ao
21
CS
4 --> 16 DECODER
DRIVE
Ao
--
CLOCK
ClK
3
ClK
BO
23
BO
16
OBo-OB3
OAo-OA3
M5L8080AP,S
M5L8085AP,S
BLANKING
4
4
Note 8
When using an 8-bit character display of more than 9 digits for the decoder display, it is necessary to
provide a separate decoder (for example 4->10 decoder, 4->16 dEjcoder) and key scan 3->8 decoder.
Only So, SI and S2 may be used as inputs to the key scan 3->8 decoder.
9
8-116
Don't drive the keyboard decoder with the MS8 of the scan line
• MITSUBISHI
"ELECTRIC
ADDRESS
DISPLAY
DATA
DISPLAY
(8 DIGITS OR 16 DIGITS)
MITSUBISHI LSls
MSW1791-02P
FLOPPY DISK FORMATTER/CONTROLLER
DESCRIPTION
PIN CONFIGURATION (TOP VIEW)
The M5W1791-02P is a floppy disk formatter/controller
device which accommodates single and double density formats_ The device is designed for use with microprocessors
or r:nicrocomputers. The device is fabricated with the Nchannel silicon gate ED-MOS technology and is packaged in
a 40-pin D IL package.
NC
NU
WRITE CONTROL _
INPUT WR- 2
~G9~G~T
S~~~3t CR- 3
38 -
DTRQ
8et~~EOUEST
READ CO~~3t R D --+ 4
37 -
DDEN
~~~~L§Ee~~?JYpUT
CHIP
REGISTER {
SELECT
INPUT
Ao-
36 -
WPRT
A,-
35 -
TP
000,-
FEATURES
• Single 5V power supply
• Accommodate single and double density formats
IBM 3740 single density format
IBM system 34 double density format
• Selectable sector length (128,256,512 or 1024 bytes/
sector)
• Side select compare
• Single/multiple sector read or write with automatic
sector search
• Selectable track to track stepping time
• Write precompensation
• DMA or programmed data transfers
• Window extension
• Interchangeable with Western Digital's FD1791-02 in
function except for VDD power supply and pin configuration
INTERRUPT
39 -INTRQ
~~Uf PROTECT
INDEX PULSE INPUT
34 . - TROO TRACK 00 INPUT
7
__
WRITE FAUL T
INPUT/VFO
CONTROL OUTPUT
32 - READY READY INPUT
ATA
31 -WD lj'mnp
33 .-. WF /VFOE
52BIDIRECTIONAL
DATA BUS
30 --+ WG lj'm~CJTGATE
29 --+ T G 43 TG43 OUTPUT
28 -HDLD
07 ....
ouf~O~STEP
-
DIRJSJ~8~DIRC o'D'i-~bt EARLY ouf~J~ LATE 7~~Ot RESET (ov)
Vss
~M~l:JfOAD
READ
RAW READ FN't>'{h
14
27 -
15
26 -RCLK FNEp-CJ?CLOCK
16
25 --+ RG READ GATE OUTPUT
17
HEAD LOAD
TIMING INPUT
18
22 -TEST TEST INPUT
19
20
'---------'
Vee
(5 V)
NC: NO INTERNAL CONNECTION
NU NON-USABLE
Outline 40 P1
puter systems. The hardware of the M5W1791-02P consists
of a floppy disk interface, a CPU interface and a PLA control logic. The total chip can be programmed by eleven 8bit commands. The floppy disk interface portion performs
the communication with the floppy disk drive under control of the PLA control logic. The CPU interface portion
has five registers - command, dara, status, track and sector
register - and communicates with the CPU through the
data bus. These functions are also controlled by the PLA.
APPLICATIONS
• Single or double density floppy disk drive formatter/
controller
• 8-inch or mini floppy disk interface
FUNCTION
The M5W1791-02P is a floppy disk formatter/controller
that can be used with most microprocessor or microcomBIDI RECTIONAL
DATA BUS
BLOCK DIAGRAM
~
0,
DsDsD4 Dio,
0,
Do
WRITE CONTROL INPUT \VA 2
CHIP SELECT INPUT ~ 3
READ CONTROL INPUT RD
I
REGISTER SELECT{AO 5
INPUT Al
....-""""----,---136
35
WPRT WRITE PROTECT INPUT
IP
INDEX PULSE INPUT
TRACK 00 INPUT
READY READY INPUT
HDLT HEAD LOAD TIMING
INPUT
TG 43 TG43 OUTPUT
HOLD HEAD LOAD OUTPUT
DIREC DIRECTION OUTPUT
STEP OUTPUT
34 TROO
32
23
EAR L Y OUTPUT EARLY 17
LATE OUTPUT LATE 18
WRITE GATE OUTPUT WG 30
WRITE DATA OUTPUT WD 31
29
28
16
RAW
REARt~NRl~~
TEST INPUT
27
RCLK
READ CLOCK INPUT 26
CLK
CLOCK INPUT
39 INTRQ g'tVP~~UPT REQUEST
2'
DOUBLE DENSITY M~6~ 3 7 ) - - > - - - - - - - - - - - - - - - - '
SE LECT INPUT
38 DTRQ
33
DATA REQUEST OUTPUT
19r-----
RG
WFNFOE
RESET
READ GATE WRITE FAULT
RESET INPUT
OUTPUT INPUT/VFO
CONTROL OUTPUT
• MITSUBISHI
.... ELECTRIC
8-117
II
•
MITSUBISHI LSls
MSW1791-02P
FLOPPY DISK FORMATTER/CONTROLLER
PIN DESCRIPTION
Pin
Name
Input or
output
Functions
NU
Non-usable
terminal
NU (pin 1) is internally connected to the back gate bias generater, so it must remain open.
NO
No internal
connection
NC (pin 40) is not internally connected.
Reset input (Active low). The device ;s reset by this signal and automatically loads 0316 into the command register. The not-
Reset input
Input
ready-status bit is also reset by this signal. When reset input is made to be high, the device executes restore command unless
READY is active and the
d~vice
loads 0116 to the sector register.
Write control
input
Input
Write signal from a master CPU (Active low).
Chip select input
Input
Chip select (Active low).
Read control
input
Input
Read signal from a master CPU (Active low).
Register select inputs. These inputs select the register under the control of the RD and WR.
RD
WR
0
STATUS REGISTER
COMMAND REGISTER
0
TRACK REGISTER
TRACK REGISTER
SECTOR REGISTER
SECTOR REGISTER
DATA REGISTER
DATA REGISTER
A1
Ao. A1
Register select
input
Input
Bidirectional
data bus
In/Out
OLK
Clock input
Input
DTRQ
Data req uest
output
Output
Ao
Three-state, inverted bidirectional data bus_
Clock input to generate internal timin~, 2MHz for 8-inch drives, 1MHz for mini drives.
DTRO is an open drain output, so pull up to Vee by the 10k resistor. In the disk read mode, DTRO indicates that data is
assembled in the data register. In the disk write mode, it indicates that the data register is empty. DTRO is reset by the read
data or write data operation.
INTRQ is also a open drain output, so pull up to Vee by the 10k resistor_ INTRO becomes active at the completion of any
INTRQ
Interrupt request
output
Output
STEP
Step output
Outp",t
Step pulse output (Active high).
DIRO
Direction output
Output
Direction output. High level means the head is stepping in and low level means the head is stepping out.
EARLY
Early output
Output
This signal is used for write precompensation. It indicates that the write data pulse should be shifted early.
LATE
Late output
Output
This signal is also used for write precompensation_ It indicates that the write data pulse should be shifted late.
Test input
Input
This input is only used for test purposes, so user must tie it to Vee or leave it open unless using voice coil actuated motors.
HOLT
Head load timing
input
Input
When the device finds high level on this input, the device assumes that the head is engaged on the media. Active high_
RG
Read gate output
Output
8-118
command and is reset when the CPU reads the status or writes the command.
This signal shows the external data separator that the synchfield is detected.
• MITSUBISHI
i"&ELECTRIC
MITSUBISHI LSls
MSW1791-02P
FLOPPY DISK FORMATTER/CONTROLLER
Pin
Name
Input or
output
Functions
This signal is internally used for the data window. Phasing relation to raw read data is specified but polarity (RCLK high or
RCLK
Read clock input
Input
RAW
READ
Raw read input
Input
HDLD
Head load output
Output
TG43
TG 43 output
Output
WG
Write gate output
Output
This signal becomes active before disk write operations are to occur.
WD
Write data output
Output
This signal consists of data bits and clock bits. It becomes act;ve for every flux transition. Active high.
READY
Ready input
low I is not important.
This input signal from the drive shall be low for each recorded flux transition.
This output signal controls the loading of ihe head of the drive. The head must be loaded on the media by this high-level
output.
This output is valid only during disk read/write operation and it shows the position of the head. High level on this output in·
dicates that the head is positioned between track 44 to 76
This signal shows the device the drive is ready. In the disk read/write operation except for TYPE 1 command operation. lowInput
level input terminates current operation and the device generates the INTRO. In the TYPE 1 command operation. this signal
is neglected. Not ready bit in the status register is the inverted form of this input.
This is a bidirectional signal. It becomes write fault input when WG is active. In the disk write operation. low level signal on
this input terminates the write operation and makes INTRO active. This signal also appears in the status register as the
In/Out
writ~
fault bit. When WG is inactive. this signal works as VFO enable output. VFOE output is also an open drain type, so pull it
up to Vee and never input active write fault signal while WG is inactive.
TROO
Track 00 input
Input
This signal indicates that the head is located on the track 00 to the device. Active low.
IP
Index pulse input
Input
This input indicates to the device that an index hole of the diskette has been encountered.
II
t----t------+----+-------------1
WPRT
Write protect
input
Low level signal on this input informs the device that the drive is in the write protected state. Before disk write operations,
Input
this signal is sampled and an active low signal will terminate the current command and set I NTRO. The write protect status
bit in the status register is also set.
Double density
mode select input
Input
This input determines the device operation mode. When DDEN=O, double density mode is selected. When DDEN=l, single
density mode is selected.
• MITSUBISHI
.... ELECTRIC
8-119
=
MITSUBISHI LSls
MSW1791-02P
FLOPPY DISK FORMATTER/CONTROLLER
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Vee
Supply voltage
VI
Input voltage
Vo
Output voltage
Conditions
Limits
Unit
-0.5-7
vss
With respect to
Pd
Power dissipation
Topr
Operating free-air temperature range
Tstg
Storage temperature range
Ta=25·C
V
-0.5-7
V
-0.5-7
V
mW
1000
·C
0-70
·C
- 65- 150
RECOMMENDED OPERATING CONDITIONS
(Ta=0-70·C, unless otherwise noted)
Limits
Symbol
Paramter
Vee
Su'pply voltage
Vss
Su pply vol tage
VIH
High-level input voltage
VIL
Low-level input voltage
Unit
Min
Nom
Max
4.75
5
5.25
0
2
V
0.8
ELECTRICAL CHARACTERISTICS
V
V
V
(Ta=0-70·C, Vee=5V±5%, unless otherwise noted)
Limits
Symbol
Test condition
Parameter
Unit
Min
Typ
Max
VOH
High-level output voltage
IOH= -100,uA
VOL
Low-level output voltage
IOL= 1.6mA
Icc
Supply current
II
Input current, other inputs
VI=Vee- OV
-10
10
,uA
loz
Off-state output current
VI=Vee- OV
-10
10
,uA
V
2.4
0.45
100
• MITSUBISHI
..... ELECTRIC
V
mA
MITSUBISHI LSls
MSW1791-02P
FLOPPY DISK FORMATTER/CONTROLLER
TIMING REQUI REMENTS
Symbol
(Ta=0-70·C, Vcc=5V
-t 5%,
Parameter
tsu (A-R)
tsu (CS-R)
Address setup time before read and chip select
TSET
th (R-A)
th (R-CS)
Address hold time after read and chip select
THLD
tw (R)
Read pulse width
TRE
tsu (A-W)
tsu (CS-W)
Address setup time before write and chip select
TSET
th
th
(W-A)
(W-CS)
Vss=OV, unless otherwise noted)
Limits
Alternative
symbol
Unit
Test conditions
Min
CL = 50pf
Typ
Max
50
ns
10
ns
400
ns
50
ns
Address hold time after write and chip select
THLD
10
ns
tw (W)
Write pulse width
TWE
350
ns
tsu (DQ-W)
Data setup time before write
TDS
250
ns
th (W-DQ)
Data hold time after write
TDH
70
tW(RR)
Raw read pulse width
Tpw
tc (RR)
Raw read cycle time
tbc
(Note 3)
tW(RCLK)
Read clock high-level width
Ta
JNote 4, 5)
800
tw (RCLK)
Read clock low-level width
Tb
(Note 4,5)
800
tc (RCLK)
Read clock cycle time
Tc
th (RCLK-RR)
Read clock hold time before raw read
TXl
th (RR-RCLK)
Read clock hold time after raw read
TX2
tW(WD)
tc (WO)
Write data pulse width
(Note 1,2)
100
ns
ns
200
1500
1800
ns
ns
1500
1800
40
(Note 1)
ns
FM
450
500
550
MFM
150
200
250
Tbc
ns
ns
40
Twp
Write data cycle time
ns
2,3,4
ns
ns
j.tS
tw (q,)
Clock high-level pulse width
TCDl
230
250
20000
ns
tw (q,)
Clock low-level pulse width
TCD2
200
250
20000
ns
tw (RESET)
Reset pulse width
TMR
50
j.tS
tW(IP)
Index pulse width
TIP
(Note 5)
10
j.tS
tW(WF)
Write fault pulse width
TWF
(Note 5)
10
j.tS
SWITCHING CHARACTERISTICS
Parameter
Symbol
tpLH (WG-WD)
(Ta=0-70·C, VCC=5V±5%, VSS=OV,
Propagation time from write gate to write data
I
unlessotherwisenoted)
limits
Alternative
symbol
Test conditions
Unit
Min
Typ
Max
FM
2
j.tS
MFM
1
j.tS
Twg
tPLH(E-WD)
tpLH (L-WD)
Propagation time from early or late to write data
Ts
MFM
125
ns
tPHL (WD-E)
tPHL (WD-L)
Propagation time from write data to early or late
Th
MFM
125
ns
tPHL (WD-WG)
Propagation time' from write data to write gate
Twf
FM
2
j.tS
MFM
1
j.tS
t PZV (R-DQ)
Output enable time after read
TDACC
CL=50 p F
t PVZ (R-DQ)
Output disable time after read
TDOH
CL=50 pF
tPHL(R-DRQ)
Propagation time from read to ORO
TDRR(RD)
tpHL (R-INTRQ)
Propagation time from read to INTRO
TIRR(RD)
tpHL (W-DRQ)
Propagation time from write to ORO
TDRR(WR)
350
ns
150
ns
400
500
ns
500
3000
ns
400
500
ns
500
3000
ns
50
(Note 5)
tpHL (W-INTRQ)
Propagation time from write to INTRO
TIRR{NR)
(Note 5)
tw (STP)
Step pu lse width
TSTP
(Note 5)
2 or 4
j.tS
tPLH(DIR-STP)
Propagation time from direction to step
TDlR
(Note 5)
12
j.tS
Note
1: The pulse of RAW READ may be any width if pulse is entirely within RClK When the pulse occurs in the RCLK window. T'fAi}ij
than 300 ns for MFM mode and 600 ns for FM mode at CLK=2MHz. Times double for lMHz.
2: 100 ns pulse width is recommended for the RAW READ pulse in 8 MFM mode.
3: RAW READ cycle time T CIRRI and WD cycle'time TCIWDI is normally 2/1s in MFM and 4/1s in FM. Times double when CLK·l MHz.
4: The polarity of RClK during Raw READ is not important.
l'lEA5 pulse width
must be less
5: When VFOE=1, RClK must be low level,
6: Tfmes double when ClK=l MHz.
• MITSUBISHI
~ELECTRIC
8-121
II
MITSUBISHI LSls
MSW1791-02P
FLOPPY DISK FORMATTER/CONTROLLER
TIMING DIAGRAM
I nput Data
- 16 OR 32,us
Read
RAW
DTRQ
to (RR)
~---1
_
READ ~
"""'---.I
to (RCLK)
tW(RCLK)
RCLK
tW(RCLK)
INTRQ
Write Data
Write
Others
t
-~~r--IP
~
DTRQ
WF
INTRQ
~~,--~
_ _~tW(RESET)
RESET
to( "')
CLK
DIRC
50-57
STEP ~
(An)
Note 7:
8:
8-122
tpLH
-(~STP)
t
t
SERVICE (RDI maximum value; FM: 27.5/1s, MFM: 13.5J.ts
SERVICE (WRI maximum value; FM: 28/15, MFM: 14/15
• MITSUBISHI
;'ELECTRIC
t~)
'----7
~
MELPS 86 MICROPROCESSORS
MITSUBISHI LSls
MSL8086S
16-BIT PARALLEL MICROPROCESSOR
DESCRIPTION
PIN CONFIGURATION (TOP VIEW)
The M5L8086S is a 16-bit parallel microprocessor fabricated
(OV)
using high-speed N-channel silicon-gate ED-MaS
Vee
Vss
(5V)
techology. It requires a single 5V power supply and has a
maximum basic clock rate of 5MHz.
The M5L8086S is upward compatible, both in hardware
and software, with the M5L8080AP, Sand M5L8085AP, S
therefore it can replace either of these devices. It has higher
performance because of additional and more powerful
32 --.RD
operation and addressing functions and instructions.
31 _RQ/GTo (---HOLD)
30 -
RQ/GT 1 (--+ HLDA)
FEATURES
•
•
(--+WR)
(--+ MIlO)
1M byte
Direct addressing:
(--+ DT/R)
Instruction set upward compatible with that of M5L-
(--+ DEN)
8080AP, S
(--+ ALE)
•
Enlarged powerful addressing: 24 modes
•
On chip 16-bit registers:
•
(--+ INTA)
14 registers
Arithmetic operations include multiplication and divi-
•
Basic clock rate:
•
Multi-CPU functions
•
Single 5V power supply
•
Vss
(OV)
sion, signed or unsigned and 8-bit or 16-bit operands.
5MHz (max.)
) terminal name during minimum mode operation
Outline 40 S 1
Interchangeable with the Intel 8086 in pin configuration
FUNCTIONS
and electrical characteristics
The M5L8086S has a minimum and maximum mode, which
allows the composition to be selected to match the scale of
APPLICATIONS
the system in which it is used. The internal function con-
Central processing unit for 16-bit microcomputer and con-
sists of execution unit (EU) and bus interface unit (B IU).
trol units
The BIU controls the 6-byte instruction queue, while generating addresses, and decodes instructions to be executed
by the EU. Each unit operates asynchronously and can
BLOCK DIAGRAM
V;s(OV)
Vee( 5V)
------~.-@--.----- ~----
BUS HIGH INABLE
AND STATUS OUTPUT BREIS, 34
A,,(S6 35
ADDRESS AND A,a/SI36
STATUS OUTPUT lAn/54 37
A16(S,38
I
I
I
BUS INTERFACE UNIT (BIU)
:
16
J
I
I
16
z
0
FIFO 2 (S)
"IFa 3 (S)
F.'Fa 4 (S)
FI Fa 5 (S)
I:::
ADIO 6
ADDRESS AND
BIDIRECTIONAL DATA BUS
AD,
AD,
z
::::J
I-----=-",-:-'-'''-----l~~g~t~~
w
u
1---'--=P-7(-:-'16-7-)---l
:i
ffif---
AD,
AD>
AD, 15
(MIN) INTERRUPT
ADo
ACKNOWLEDGE OUTPUT(lNTA)
( IN) WRITE CONTROL OUTPUT (WR)
MIN) READ CONTROL OUTPUT (Ali)
(MIN) DATAcg~~~1r~O~UTPUT (M iO)
(MIN) DATA TRANSFER
(DT R)
CONTROL OUTPUT (DEN)
\~:~l R~b~ltsA~Hc~UTPUT
ENABLE OUTPUT
16
24
29
32
28
27
26
(ALE) 25
::::J
co
I
I
I
11 NMI
~t;~ffi:
[o~~~
i
0
c6t;
z
-
AND
0
co :
16
z
VJ
VJ
::::J
U
<
19
.J ......... (I)IS.P.-.I:t..
1
1
POP
POP
POP
POP
IN
r1
EA1
0
0
1
1
0
0
0
0
0
1
0
)
50-57
06, OE, 16, 1E
8F
REG
o
SR
0
1
. . JI)I~.P.~L.......................... J.
000
MOD
000
.. (I)~.S.p.~I:t ..
1
1
1 0 0
000
RIM
. "'RiM
)..
MOD
RIM
1 0 0 0
1
)
(DISP-L
)
(DISP-H
r1
0
1 0
1
REG
58-SF
SEG
000
SR
11
07,OF,17,1F
A-c~e,~P~o~r~t------------~~--~~~0~~~0~~1--~0~W~+---(~P~O~R~T~------------------~~~E~4~-~E~5~4
~~ r-__I~N~~A~c=e,~D~X~------------~~--~~~0~---1~~~0~W~+___~~:----------------__~~~_=EC~-~E=D~
.=: is
OUT
OUT
LEA
Port, Ace
DX, Ace
r1, EA2
LDS
r1, EA2
LES
r1, EA2
LAHF
SAHF
POPF
PUSHF
9-12
1
1 0 0
(DISP-L
1 1 0
(DISP-L
1 1 0
(DISP-L
o 0
o 0
o 0
o 0
0
0
0
0
0
0
1
0
0
0
1
0
1
1
1
1
1
1
1
0
1
1
0
0
W
W
1
)
1
)
0
)
1
0
1
0
• MITSUBISHI
.... ELECTRIC
(PORT
MOD
(DISP-H
MOD
(DISP-H
MOD
(DISP-H
REG
RIM
REG
RIM
REG
RIM
E6- E7
EE-EF
8D
)
C5
)
C4
)
9F
9E
9D
9C
MITSUBISHI LSls
MSL8086S
16-BIT PARALLEL MICROPROCESSOR
Flags
Bytes in
Clock cycles
the code
Function description
Bus cycles
2~4
0
1
(r1)~(EA2)
MOD*ll
9+EA
2~4
1
(EA 1)~(r 2)
MOD*ll
4
10+EA
4
2
I
(r
1)~
2
8+EA
0
F
0
F
F
T
F
S
F
Z
F
A
F
P
F
C
F
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
J
(r2)
3~4
0
(r
3~6
1
(EA1 )~DATA
0
(r1)~DATA
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
2~
3
1)~DATA
MOD*ll
10
3
1
(Ace )~(ADDR)
10
3
1
(ADDR )~(Acc)
X
X
X
X
X
X
X
X
X
When SR = 01 undefined
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
2
8+EA
2
9+EA
4
17+EA
3
11
2
2~4
0
1
(SEG)~(r2)
(SEG)~(EA2)
2
0
(r1)~(SEG)
2~4
1
(EA1
2
2~4
0
1
(r 1)<-----> (r 2)
(r1)<-----> (EA2)
1
1
0
1
(AL)~«BX)+(AL»
)~(SEG)
(AX)<----->(r2)
1
2
(SP)~(SP)-2,
2~4
10
10
1
1
1
1
(SP)~(SP)-2,
8
17+EA
2
1
2
(r1)~«SP)+l
2~4
1
1
1
1
1
1
0
(r1)~«SP)+l
16+EA
2
1
1
2
1
2
1
2~4
2~4
2
16+EA
2~4
2
4
4
8
10
1
1
1
1
0
0
1
1
MOD*ll
MOD*ll
11
16+EA
8
8
10
8
10
8
2+EA
MOD*11
(SP)~(SP)-2,
(SP)~(SP)-2,
: (m)
«SP)+l : (SP»~(r1)
«SP)+l : (SP»~(EA1)
MOD*11
«SP)+l : (SP»~(r1)
«SP)+l: (SP»~(SEG)WhenSR=Ol: undefined
: (SP», (SP)~(SP)+2
(EA1 )~«SP)+l : (SP», (SP)~(SP)+2
X
X
X
X--
MOD*11
: (SP», (SP)---(SP)+2
(SP», (SP)<--(SP)+2WhenSR=01 : undefined
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
(SEG)~«SP)+l:
(ACc)---(Port)
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
X
X
X
(Acc)~«DX»
(Port)<--(Acc)
«DX»~(Accl
(r 1 )~EA2
When MOD = 11: undefined
(r1)+-(EA2), (DS)~(EA2+2)
When MOD = 11: undefined
(rl)<--(EA2), (ES)~(EA2+2)
When MOD = 11: undefined
(AH)~(SF) : (ZF) : X: (AF) : X : (PF) : X : (CF)
(SF) : (ZF) : X : (AF) : X : (PF) : X : (CF)---(AH)
(FR)+-«SP)+l : (SP», (SP)~(SP)+2
(SP)+-(SP)-2, «SP)+l : (SP»~(FR)
• MITSUBISHI
.... ELECTRIC
X
X
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
X
X
X
X
X
X
9-13
MITSUBISHI LSls
MSL8086S·
16-BIT PARALLEL MICROPROCESSOR
~
tem
Instruction code
Mnemonic
Oz 0, Do
Type of
instruction
(ADD
EA1/r1, EA2/r2
o
0
0
0
..... ([)ISJ).-.L..
ADD
ADD
r1,r2
r1, EA2
ADD
EA1,r2
(ADD
EA1/r1, DATA
ADD
r1, DATA
ADD
EA1, DATA
ADD
(ADC
Acc,DATA
EA1/r1, EA2/r2
ADC
ADC
r1, r 2
r1, EA2
ADC
EA1,r2
(ADC
EA1/r1, DATA
ADC
r1, DATA
ADC
ADC
EA1, DATA
Ace, DATA
(INC
DAA
9 ·14
0
r1
d
0
0
0
0
(DISP-L
o 0 0
(DISP-L
1 0
0
(DISP-L
0
o ··0····,1
o 0 1
0
o
o
o
0
0
0
0
1
.... ([)I~.P.-L.
o 0 0 1
o 0 0 1
(DISP-L
000 1
(DISP-L
1 0
0 0
(DISP-L
.... ([).A:r~~L, ..
1 0
0
0
(DATA-L
1 0
0
0
(DISP-L
(DATA-L
o 0 0 1
(DATA-H
1
1
1
o
o
0
W
W
1
W
)
)
MOD
(DISP-H
MOD
(DISP-H
MOD
(DISP-H
1.
1
W
o 0 S W
o 0 S W
)
o 0 S W
o
o
o
o
o
1
0
0
d
)
)
W
)
W
........ J .......
0
0
d
1
W
W
)
0
0
W
)
o 0 S W
)
1.
o 0 S W
1
)
RIM
)
0
0
0
)
)
0
0
0
W
W
)
0
1
o
o
REG
1
1
1
001
0
o
1
1
1
• MITSUBISHI
"ELECTRIC
1
1
MOD
(DISP-H
RIM
)
)
04-05
REG
RIM
REG
REG
RIM
.x
RIM
10-13
)
REG
RIM
)
o
o
RIM
80-83
)
.x
0
1
0
RIM
0
1
0
RIM
000
)
)
)
14-15
.... 1. ...... ([)I.SP.-.tt ..
1
1
80-83
··0···0·0· ········R/M··
J[).A:r~~Ii ..
MOD
RIM
)
J[).I.S.P-.tt .
1
1
MOD
(DISP-H
MOD
(DISP-H
MOD
(DISP-H
1
00-03
RIM
REG
MOD
)
W
)
)
notation
·R/M·
REG
REG
(DATA-H
MOD
(DISP-H
(DATA-H
(DATA-L
W
0
1
1
0
[[)A:r~~1i
0
o 0 S W
1
RIM
)
1
1
1
(DATA-H
MOD
(DISP-H
(DATA-H
(DATA-L
)
o
REG
MOD
J ....... ([).I.S.P~tt ..
)
.... ([)~:r~~.L ..
1 0
0
0
(DATA-L
1 0
0 0
(DISP-L
(DATA-L
o 0 0 0
(DATA-H
o
0
. JDI.S.P-L.
1
1
1
1
1
1
(DISP-L
INC
INC
INC
AAA
o
Hexadecimal
FE-FF
RIM
)
000
000
. ··R/M···
RIM
)
40-47
37
27
MITSUBISHI LSls
MSL8086S
16-BIT PARALLEL MICROPROCESSOR
Flags
Clock cycles
Bytes in
the code
Function description
Bus cycles
3
9+EA
2
2-4
1
16-t-EA
2-4
2
0
(r1)--(r1)+(r2)
(r 1 )<-- (r 1)+ (EA2)
MOD*11
(EA 1) -- (EA 1 )-t- (r 2)
MOD*11
When S:W
When S:W
~
~
01 then DATA is DA TA-L and DA TA-H
11 then DATA is DATA-L and DATA-H isfilled with the
sign of DATA-L (sign extendedl
4
3-4
0
(r 1 ) -- (r 1 ) + DA T A
17+EA
3-6
2
(EA1)-- (EA1 )+DATA
4
2-3
0
(Acc)-- (Acc)+DATA
2
2-4
1
(r 1 ) -- (r 1 ) + (r 2) + 1
(rl)--(rl)+(EA2) +1
MOD*11
16+EA
2-4
2
(EA1)<--(EA1)+(r2) +1
MOD*11
When S:W - 01 then DATA is DATA-L and DATA-H
When S:W ~ 11 then DATA is DAT A-L and DATA-H is filled with the
sign of DAT A-L (sign extended I
4
3-4
0
(r 1 ) -- (r 1 ) + DA T A + 1
17+EA
3-6
2
(EA1)-- (EA1) +DATA +1
4
2-3
0
(Acc)-- (Acc)+DATA + 1
3
15+EA
2
2-4
0
2
4
1
1
0
0
4
1
0
2
(rl ) -- (n ) + 1
(EA1)--(EA1)-t-1
I
F
T
F
F
Z
F
A
F
F
C
F
0
X
X
X
0
0
0
0
0
0
X
X
X
0
0
0
0
0
0
X
X
X
0
0
0
0
0
0
X
X
X
0
0
0
0
0
0
X
X
X
0
0
0
0
0
0
X
X
X
0
0
0
0
0
X
X
X
0
0
0
0
0
X
X
X
X
X
X
0
0
X
f::,
f::,
0
0
0
f::,
f::,
0
f::,
X
X
X
0
0
0
0
0
S
P
MOD*11
(r 1 ) -- (r 1 ) + 1
When (ALI OF!. or (CFI ~ 1 (ALI +- (ALI + (ALI + 60 1•
(AH)--(AH)+1, (AF)--1,(CF)-- (AF)
(AL)--(AL) !\OFI.
When (ALI OF!. or (CFI ~ 1 (ALI +- (ALI + (ALI + 60 1•
(CF)-- (AF)V(CF), (AF)--1
When (ALI> 9F I• or (CFI ~ 1: (ALI +- (ALI + 60 1•
(CF)--1
• MITSUBISHI
"ELECTRIC
D
F
MOD*11
3
9+EA
0
0
F
9-15
MITSUBISHI LSls
MSL8086S
16-BIT PARALLEL MICROPROCESSOR
I~
Instruction code
Mnemonic
(SUB
r1, r 2
n, EA2
SUB
EA1,r2
SUB
SUB
SUB
(SBB
SBB
SBB
SBB
(SBB
c
EA1/n, EA2/r2
SUB
SUB
(SUB
u
EA1/r1, DATA
r1, DATA
EA1, DATA
Ace, DATA
EA1/r1, EA2/r2
r1, r 2
r1, EA2
EA1,r2
EA1/r1, DATA
SBB
n, DATA
SBB
EA1, DATA
0
~
c
0
u
:;J
SBB
c
u
';:;
(DEC
~
DEC
DEC
~
DEC
(NEG
NEG
NEG
(CMP
EA1/r1
r1
EA1
r1
EA1/r1
r1
EA1
EA1/r1, EA2/r2
r1, r 2
n, EA2
CMP
EA1,r2
EA1/r1, DATA
CMP
r1, DATA
CMP
EA1, DATA
CMP
AAS
CAS
16
Ace, DATA
CMP
CMP
(CMP
9
Hexadecimal
07 06 Os 04
Type of
instruction
Ace, DATA
1
0
0
" "(i)I,S,P,~L,,
1
0 0
1
0 0
(DISP-L
1
0 0
(DISP-L
1 0
0
(DISP-L
""Ji),A:r~~":,,'
1 0
0
(DATA-L
1
0
(DISP-L
(DATA-L
1
0 0
(DATA-H
0
0 0
"
03 02 0, Do
0
0
0
0
0
0
0
0
0
S
0
Os 04 03
02 0, Do
REG
RIM
MOD
""',) "" ""Ji),Il;~,-,tt,
0
0
0 7 06
d
W
d
1
W
W
)
W
1
)
REG
REG
1
MOD
)
(DISP-H
MOD
)
0
0
0
1
S
0
0
d
"" J[),I,S,P~L",
"""""""""""',J,'
0 d W
000 1
0
1
0
1 W
0 0
)
(DISP-L
1
0 0 W
0 0
0
)
(DISP-L
0 0 S W
1 ,0 0
0
)
(DISP-L
RIM
)
0
1
)
)
0
(DATA-H
MOD
0
(DISP-H
(DATA-H
(DATA-L
MOD
' "~[)~,S~,~tt,'
REG
1
REG
REG
1
MOD
1 """"""RiM"'"
)
1
RIM
)
)
)
" ""'RiM'
)
RIM
)
MOD
REG
RIM
)
(DISP-H
(DISP-H
0
80-83
RIM
)
)
' ,,ci),A:r~~I:I,,
' "RiM
1
1
0 0
1
1 0 0
0
S W
0
(DATA-L
)
)
(DATA-H
1
1 0
MOD
0 0
0 0 S W
0
RIM
)
)
(DISP-L
(DISP-H
)
(DATA-H
)
(DATA-L
)
(DATA-L
1
0 0
0
0 W
)
(DATA-H
MOD
1
1 1
0
0
1
1 W
RIM
(DISP-L -------------------------.""'",,(i)I,S,P__,tt,'
),'
--RiM
1
1
1 W
1
0
0
1 1
1
MOD
1
0
0
RIM
1 W
)
)
(DISP-L
(DISP-H
1
0
1 0 0
REG
1 1
1
0
1 1 W
MOD
1
0
RIM
)
, "([)I,S~,~L,,,
""""" (i)I,S,P~tt",
""',J
"""""'RiM-1
1
1
1
1
W
1
0
0
1
MOD
1
1
1
1 W
0
0
RIM
1
)
(DISP-H
)
(DISP-L
1
0 d W
MOD
REG
RIM
0 0
)
"" ,ci)I,S,P__,L"
""""',) """",,(i)I,~,~ __,tt,' '--R'E'a """""""RiM""
1
1
0 d W
0 0
1
0
MOD
REG
1 W
RIM
0
0
)
(DISP-H
)
(DISP-L
REG
1
0
MOD
0 W
0
0
RIM
)
)
(DISP-L
(DISP-H
1 0 0
MOD
0 0 S W
0
RIM
)
(DISP-H
)
(DISP-L
)
"",([),A:r~~":"
"""'" J[),A:r~~I:I"
"""',J
""""""RiM---1 1
1 0 0 0
0
0 S W
(DATA-L
)
)
(DATA-H
1 0
MOD
0 S W
0 0
0
RIM
)
)
(DISP-L
(DISP-H
)
)
(DATA-L
(DATA-H
(DATA-L
)
0
0
1
0 W
(DATA-H
)
0 0
",,([)A:r~~~, """"""""""""",),
2C-2D
18-1B
RIM
(DISP-H
MOD
80-83
RIM
(DISP-H
"',Ji)~:r~~I:I"
"""""""""""",J,'"
0 0 S W
1
1
0
RIM
REG
0
)
W
)
)
W
)
W
"""""""RiM"'"
(DISP-H
MOD
W
)
notation
28-2B
1C-1D
FE-FF
J.
0
0
1
0
• MITSUBISHI
.... ELECTRIC
48-4F
F6-F7
38-3B
80-83
;3C-3D
3F
2F
MITSUBISHI LSls
MSL80865
16-BIT PARALLEL MICROPROCESSOR
Flags
Clock cycles
Bytes in
the code
Function description
Bus cycles
3
9+EA
2
2-4
0
1
(n ) <- (n ) - (r 2)
(n ) <- (n ) - (EA2)
MOO*11
16+EA
2-4
2
(EA 1) <- (EA 1) - (r 2)
MOO*11
When S:W
When S:W
~
~
01 then DATA is DATA-L and DATA-H
11 then DATA is DATA-L and the signs of DATA-L are
extended to form 16-bit operand.
4
3-4
0
(n)<- (n )-DATA
17+EA
3-6
2
(EA1)<- (EA1 )-DATA
2-3
0
(Acc) <- (Acc)-OATA
4
3
9+EA
2
2-4
16+EA
2-4
~
(n)<- (n)- (r2) -1 when (CF)
~
1
2
(EA1)<- (EA1 )--(r2) -1 when (CF)
~
(r 1)<- (r 1)- (EA2) -1 when (CF)
~
~
~
3-4
0
(n)<- (n )-OATA -1 when (CF)
2
(EA1)<- (EA1 )-OATA -1 when (CF)
4
2-3
0
(Acc) <- (Acc) - OA TA when (CF)
3
15+EA
2
2-4
0
2
( n ) <- (n ) - 1
(EA1)<-(EA1)-1
2
1
0
2
2-4
0
4
(r 1 ) <- (r 1 ) - 1
When W=O (SRC)=FFH
When W=1 (SRC) =FFFFH
(n)<-(SRC)-(r 1), (n )<-0-(r1)
(EA1)<- (SRC)-(EA1), (EA 1) <- 0- (SRC)
Z
F
A
F
P
F
C
F
0
X
X
X
0 0
0
0
0
0
X
X
X
0
0
0
0
0
0
X
X
X
0
0
0
0
0
0
X
X
X
0
0
0
0
0
0
X
X
X
0
0
0
0
0
0
X
X
X
0
0
0
0
0
0
X
X
X
0
0
0
0
X
0
0
X
X
X
X
X
X
0
0
0
0
0
0
0
0
X
1
0
X
X
X
0
0
0
0
0
0
X
X
X
0
0
0
0
0
1
~
~
1
MOO*11
1
MOO*11
MOO*11
3
9+EA
2
2-4
0
1
(r 1)- (r 2)
(n )-(EA2)
MOO*11
16+EA
2-4
2
(EA1 )-(r2)
MOO*11
~
S
F
MOO*11
01 then DATA is DATA-L and DATA-H
11 then DATA is DA TA-L and the sign of DA T A-L is
extended to form a 16-bit operand.
3-6
~
T
F
MOO*11
1
4
When S:W
When SW
I
F
1
17+EA
3
16+EA
0
F
MOO*11
0
1
When S:W
When S:W
0
F
01 then DATA is DATA-L and DATA-H
11 then DATA is DA TA-L and the signs of DAT A-L are
extended to form 16-bit operand.
4
3-4
0
(n )-OATA
17+EA
3-6
2
(EA1 )-OATA
4
2-3
0
(ACC)-OATA
0
X
X
X
0
0
0
0
0
4
1
0
,6.
X
X
X
,6.
,6.
0
,6.
0
4
1
0
When ((AU V OF!6) or (AF) - 1.
When (AU V OF!6 or (AF) ~ 1: (AU +- (AL) -6
(AH)<-(AH)-1, (AF)<-1, (CF)<-(AF)
(AU +- (AU V OF!6
When ((AU V OF!6) or (AF) - 1:
When (AL) V OF!6 or (AF) ~ 1: (AU +- (AL) -6
(OF)<- (AF)V(OF), (AF)<-1
When (AU> 9F!6 or (CF) ~ 1: (AU +- (AU -60!6
(CF)<-1
,6.
X
X
X
0
0
0
0
0
MOO*11
• MITSUBISHI
"'ELECTRIC
9-17
II
MITSUBISHI LSls
MSL8086S
16-BIT PARALLEL MICROPROCESSOR
~
Instruction code
Mnemonic
07 D6 Ds D4
Type of
instruction
(MUL
MUL
EA1/r1
J
r1
1
MUL
EA1
0
IDIV
r1
J
1
J
J
---RiM-RIM
1
1
0
RIM
1
1
0
RIM
1
1
1
R!M
J
J
F6-F7
J
---RiM
1
1
1
0
0
0
1
1
1
1
1
1
1
0
1
1
AAD
CBW
1
1
1
1
1
1
1
1
1
(DISP-L
1
1
1
(DISP-L
1
1
0
1
0 0
1
1
0
1
1
0
0
0
0
98
CWO
1
1
1
0
0
1
99
IDIV
EA1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
J
1
1
1
1
MOD
(DISP-H
MOD
(DISP-H
1
0
0
0
1
0
1
0
J
1
• MITSUBISHI
~ELECTRIC
0
RIM
RIM
J
RIM
J
0
1
0
05
MITSUBISHI LSls
MSL8086S
16-BIT PARALLEL MICROPROCESSOR
Flags
Clock cycles
Bytes in
the code
Bus cycles
Function description
70~77
2
0
118~133
2
0
(EXT) +- overflow digit of operation; when (EXT) - 0: (CF) +- 0
When (EXT) 10: (OF) +- (CF), (CF) +- 1 - (CF)
When W ~ 0 (EXT) ~ (AH)
(AX)<--(AL)*(r1)
When W ~ 1: (EXT) ~ (OX)
(76~83)+EA
2~4
1
(OX: AX)<--(AX) *(r1)
When W ~ 0: (EXT) ~ (AH)
MOD*11
(124~139)+EA
2~4
1
(AX)<--(AL)*(EA1)
When W ~ 1: (EXT) ~ (OX)
MOD*11
0
F
D
I
F
F
T
F
F
Z
F
F
P
F
C
F
0
X
X
X
6
6
6
6
0
0
X
X
X
6
6
6
6
0
6
X
X
X
0
0
6
0
6
6
X
X
X
6
6
6
6
6
6
X
X
X
6
6
6
6
6
6
X
X
X
X
X
X
X
0
0
6
X
6
X
0
X
X
X
X
X
X
X
X
X
X
X
X
S
A
(OX: AX)<-- (AX) * (EA1)
80~98
2
0
2
0
(EXT) +- overflow digit of operation; when (LOW) changes to (EXT) by
extending the sign bit of (LOW) (CF) +- 0
Otherwise: (OF) +-(CF), (CF) +- 1
When W ~ 0: (EXT) ~ (AH), (LOW) ~ (AL)
(86~ 104)+EA
2--4
1
(AX)<-- (AL) * (r 1)
When W ~ 1: (EXT) ~ (OX), (LOW)
(OX: AX) <-- (AX) * (r 1)
When W ~ 0 (EXT) ~ (AH), (LOW)
(134~160)+EA
2~4
1
(AX)<-- (AL) * (EA 1)
When W ~ 1: (EXT) ~ (OX)' (LOW)
83
2
0
128~
154
~
(AX)
~
(AL)
MOD*ll
~
(AX)
MOD*ll
(OX: AX)<-- (AX) * (EA1)
(AH) +- (AL) -;.- OA I6 ,
(AL) +- remainder
80~90
2
0
(temp) +- dividend; when W - 0: MAX - FF 16;
When W ~ 1: MAX ~ FFFF ,6 ; (temp) -;.- (EA1/rl)
When results of the division are larger than MAX, an interrupt of TYPE
is generated, (SP) +- (SP) - 2, ((SP) + 1: (SP)) +- flag
(IF) +- 0, (TF) +- 0, (SP) +- (SP) -2, ((SP) + 1: (SP)) +- (CS)
(CS) +- contents of address 2, (SP) +- (SP) -2, ((SP) +1: (SP)) +- IP
(IP) +- contents of address 0, the result of the division is undefined.
(AL) <-- (AX)-.;.- (r 1), (AH) <-- Remainder
144~162
2
0
(AX)<--(DX: Ax)-.;.-(r1), (DX) <-- Remainder
2~4
1
(AL)<-- (AX)-.;.-(EA1)
2~4
1
(AX)<--(OX: AX)-.;.-(EA1), (DX) <-- Remainder
(86~96)+EA
(150~168)+EA
(AH) <-- Remainder
~
0
MOD*ll
MOD*ll
(temp) +- dividend; when W ~ 0: MAX ~ 7F '6
When W ~ 1: MAX ~ 7FFF I6 ; MIN ~ 81 16
when the result of the division is positive and over MAX or when negative
and more negative than MIN an interrupt of TYPE ~ 0 is generated and
101-112
165~ 184
1
the result of the division is undefined.
(AL) <-- (AX)-.;.- (r 1), (AH) <-- Remainder
(AX)<--(DX: AX)-.;.-(r1), (DX) <-- Remainder
(AL)--- (AX)-.;.- (EA1), (AH)<-- Remainder
MOD*ll
2~4
1
(AX)<-- (DX : AX)-.;.- (EA1), (DX)<-- Remainder
MOD*ll
2
0
0
(AL) +- (AH) * OA '6 + (AL), (AH)
(107~118)+EA
2
2
2-4
(171 ~190)+EA
60
2
1
5
1
0
0
0
When (AL)
When (AL)
When (AX)
When (AX)
+-
0
< 80 ,6 : (AH) +- 0
~
80 ,6 : (AH)
+-
FFI6 (extended sign bit)
< 8000 ,6 : (OX) +- 0
~
I
8000 16 : (OX) +- FFFFI6 (extended sign bit)
• MITSUBISHI
.... ELECTRIC
9-19
II
MITSUBISHI LSls
MSL8086S
16-BIT PARALLEL MICROPROCESSOR
~
tern
Instruction code
Mnemonic
Type of
instruct ion
02 01 Do
(NOT
NOT
NOT
(AND
EA1/r1
r1
EA1
EA 1/r1, EA2/r 2
AND
AND
AND
(AND
AND
AND
AND
EA1,r2
EA1/r1, DATA
r1, DATA
EA1, DATA
Acc, DATA
(TEST
TEST
TEST
TEST
(TEST
c
TEST
.Q
TEST
TEST
r1, r 2
r1, EA2
EA1,r2
EA1/r1, DATA
r1, DATA
EA1, DATA
Acc, DATA.
(OR
OR
OR
1 1 1
_____ (I)_I_sf)_-_L___ _
1 1 1
(DISP-L
001
0
(1)1_Sf)_-_L__ _
001
0
001
0
(DISP-L
001
D
(DISP-L
1 000
(DISP-L
__ JI)_A:r~~~ __
1 000
(DATA-L
1 000
(DISP-L
(DATA-L
001
0
(DATA-H
1 0 0 0
___ ._(I)I_Sf)."_L__ _
000
1 0 0 0
(DISP-L
1
1 1
(DISP-L
__ JD_A:r~~~ __
1
1 1
(DATA-L
1
1 1
(DISP-L
(DATA-L
1
0
1 0
(DATA-H
o 000
___ JI)Il;_P_~L__ _
o 000
o
1
o
o
1
o
0
o
o
0
0
1 o
_J ______ ~I)I_S_P_~I:t ___ _
o
1 W
1
0
1
1 W
MOD
0
1 o
)
(DISP-H
d W
MOD
REG
__ J _______ ~I)I_Sf)_~I:t_
d W
1
---,:iE-a-
0
1
o
0
d
o
0
0
o
1
0
1
o
o
o
o
o
o
0
1
W
1
)
W
)
1
1
1
(OR
OR
OR
OR
EA1/r1, DATA
r1, DATA
EA1, DATA
Acc, DATA
XOR
XOR
XOR
(XOR
XOR
XOR
XOR
9
20
EA1/r1, EA2/r2
r1,r2
r1, EA2
EA1,r2
EA1/ r 1, DATA
r1, DATA
EA1, DATA
Acc, DATA
W
)
)
o 0 W
d
d
0
1
W
)
0
0
o
0
W
(DISP-L
1 0 0
(DISP-L
0
0
0
)
W
)
0
o
0
____ .cI)A:r~~~ __
1 0 0 0
(DATA-L
1 0 0 0
(DISP-L
(DATA-L
o
0
0
o
o
)
0
0
0
0
W
)
)
o w
0
o
0
1
____ JI)IS_P_~L__ _
o 0 1
o 0 1
(DISP-L
o 0 1
(DISP-L
1 0 0 0
(DISP-L
_____ (I)A:r~~~ __
1 0 0 0
(DATA-L
1 0 0 0
(DISP-L
(DATA-L
001
(DATA-H
--W-)
o
RIM
)
RIM
(DATA-H
MOD
(DISP-H
(DATA-H
(DATA-L
RIM
)
RIM
)
RIM
80-81
)
)
----R/M--RIM
24-25
RIM
84-85
)
--------R/M--RIM
)
RIM
F6-F7
)
)
---------R/M---)
0
0
0
RIM
)
)
A8-A9
REG
08-08
RIM
)
----R-E-a-- --------R/M---
MOD
REG
(DISP-H
MOD
REG
(DISP-H
MOD
0
0
1
(DISP-H
______ (I)~:r~~ti__
1
1
0 0
1
(DATA-H
MOD
(DISP-H
(DATA-H
(DATA-L
20~23
)
--------R/M----
)
)
MOD
REG
(DISP-H
MOD
0 0 0
(DISP-H
(I)_A:r~~ti___
0 0 0
1
1
)
W
MOD
) ______ JI)Il;_P_~I:t __
W
1
1
(DATA-H
(XOR
W
o
o
0
)
-----------R/M"----
0
_J ________
1
)
o
o
___ J.
o
notation
F6~F7
)
(DATA-H
MOD
(DISP-H
(DATA-H
(DATA-L
MOD
REG
(DISP-H
OWl
1
-------R-E-a-
o
o
EA1, r2
W
)
)
lOW
)
1
o W
1
1
RIM
MOD
REG
(DISP-H
MOD
REG
(DISP-H
W
MOD
0 0
)
(DISP-H
) _______ (I)_A:r~~ti ___ _
W
1
1
0 0
)
o 0
MOD
W
)
W
)
--0--
(DISP-L
OR
W
Hexadecimal
RIM
)
RIM
)
80-81
RIM
)
)
----------R/M-)
0
0
1
RIM
)
)
OC-OD
)
o
0
d
o
0
d
o
0
1
W
MOD
__ J _________ (I)Il;f)."_I:t __
REG
1
---A-E-a--
W
MOD
(DISP-H
MOD
(DISP-H
MOD
(DISP-H
REG
RIM
RIM
REG
RIM
o
0
0
W
o
0
0
W
)
)
___ J. ______ (I)_A:r~~ti__ _
o 0
o
0
0
0
W
1
)
(DATA-H
MOD
(DISP-H
(DATA-H
(DATA-L
W
)
J
o
__J..
1
)
lOW
)
• MITSUBISHI
~ELECTRIC
1
30-33
RIM
W
)
)
o
80-81
RIM
)
0-
-------R/M )-)
o
RIM
)
)
34-35
MITSUBISHI LSls
MSL80865
16-BIT PARALLEL MICROPROCESSOR
Flags
Bytes in
Clock cycles
the code
Function description
Bus cycles
°
3
16+EA
2
2-4
0
1
When W (SRC) FF'6
When W = i: (SRC) = FFFF'6
(rn <-- (SRO) - (r n
(EAl ) <-- (SRO)-(EA1)
MOD=Fll
MOD=Fll
3
9+EA
2
2-4
0
1
16+EA
2-4
2
(EA1)<-- (EA1) 1\ (r2)
After execution of the instruction (CF)
+-
+-
0, (OF)
0, (OF)
+-
+-
4
3-4
0
(rl ) <-- (r 1) 1\ DA T A
17+EA
3-6
2
(EA1)<--(EAl) A DATA
4
2-3
0
(Acc)<-- (Acc) 1\ DATA
After execution of the instruction (CF)
After execution of the instruction (CF)
+-
0, (OF)
0, (OF)
+-
(r 1) <-- (rl) 1\
(r 1)~ (rl) 1\
(EA1)<--(EA1)
After execution of
+-
0, (OF)
+-
3
9+EA
2
2-4
0
1
3-4
0
(r 1 ) +-- (rl) A DA T A
11 +EA
3-6
2
(EA 1)~ (EAl) A DATA
4
2-3
0
(Acc) 1\ DATA.
(OF)~O.
(rl)~
(rl)
0
1
(rl
16+EA
2-4
2
(EA1)~(EAll
)~(rl)
V
4
3-4
0
(rl)~
17+EA
3-6
2
(EA1)~
4
2-3
0
(Acc)
3
9+EA
2
2-4
0
1
(rl)~
16+EA
2-4
2
(EAl )<--(EA1) ";t
~
Z
F
A
F
P
F
0
F
X
X
X
X
X
X
X
X
X
0
X
X
X
0
0
6
0
0
°
0
X
X
X
0
0
6
0
0
0
X
X
X
0
0
6
0
0
0
X
X
X
0
0
6
0
0
0
X
X
X
0
0
6
0
O.
0
X
X
X
0
0
6
0
0
0
X
X
X
0
0
6
0
0
0
X
X
X
0
0
6
0
0
(OF)~O
0
X
X
X
0
0
6
0
0
°
0
X
X
X
0
0
6
0
0
0
X
X
X
0
0
6
0
0
0
X
X
X
0
0
6
0
0
+-
°
°
MOD=Fll
+-
0, (OF)
+-
°
°
MOD=F 11
(r 2)
MOD=F 11
(Acc)
V
+-
0, (OF)
+-
V
DATA
°
DATA.
MOD=F 11
(OF)~O.
After execution of the instruction (CF)
(rl)~
S
F
DATA
V
(EA1)
(rl)
(rl)
°
(OF)~O
After execution of the instruction (CF)
(rl)
+-
(r2)
(EA2)
V
V
2
2-4
T
F
MOD=F 11
After execution of the instruction (CF)
3
9+EA
I
F
MOD=F 11
(r 2)
(EA2)
A (r2)
the instruction (CF)
5
0
F
MOD=Fll
After execution of the instruction (CF)
(r 1) <-- (r 1 ) 1\ (r 2)
(r 1 ) <-- (r 1 ) 1\ (EA2)
0
F
";t
(r 2)
";t
(EA2)
3-4
0
(r 1) <-- (r 1 )
17+EA
3-6
2
(EA1)~(EA1)
4
2-3
0
(Acc) <-- (Acc)
¥
0, (OF)
+-
MOD=Fl1
(r 2)
After execution of the instruction (CF)
4
+-
MOD=F 11
+-
0, (OF)
+-
°
DATA
¥
¥
DATA
MOD=F 11
DATA, (OF)~O. (OF)~O
• MITSUBISHI
.... ELECTRIC
9-21
II
MITSUBISHI LSls
MSL8086S
16-BIT PARALLEL MICROPROCESSOR
MACHINE INSTRUCTIONS
tem
~
Instruction code
Mnemonic
Type of
instruction
EA1/r1,1/CL
(SHL/SAL
SHL/SAL
SHL/SAL
SHL/SAL
r1, 1
r1, CL
EA1,1
SHL/SAL
EA1, CL
(SHR
)
1
1
0
(OISP-L
1
1
1
1
1
0
1
1
0
1
1
0
1
(OISP-L
1
1
0
1
(OISP-L
1
1
0
t
(OISP-L
EA1/r1, 1/CL
o
o
0
0
V
MOD
(OISP-H
1
)
W
0
D2 D1 Do
Hexadecimal
notation
RIM
00-03
0
)
---Rip';--
0
W
1
1
1
0
0
001
W
o
0
0
W
)
1
1
0
0
0
0
RIM
RIM
o
0
1
W
1
0
0
RIM
o
0
V
W
)
1
1
MOD
(OISP-H
MOD
(OISP-H
MOD
(OISP-H
1
0
0
RIM
1
1
1
1
MOD
(OISP-H
MOD
(OISP-H
1
1
1
0
0
0
1
1
1
RiM
1
0
1
RIM
1
1
1
RIM
)
)
)
00-03
)
r.
(/)
SHR
SHR
SHR
SHR
(SAR
r1,1
CL
EA1,1
n,
EA1, CL
EA1/ r 1,1/CL
SAR
SAR
SAR
r1,1
r1, CL
EA1, 1
SAR
EA1, CL
(ROL
ROL
ROL
ROL
EA1/r1,1/CL
r1,1
r1, CL
EA1,1
o
o
o
0
0
W
0
1
W
0
0
W
1
1
0
1
1
0
1
1
0
(OISP-L
1
1
0
(OISP-L
1
1
1
1
o
0
1
W
1
1
0
(OISP-L
1
o
0
V
W
)
MO~
1
1
0
0
1
1 0
(OISP-L
1
1
0
(OISP-L
1
1
0
(OISP-L
1
1
1
o
o
o
0
0
W
0
1
W
1
1
0
0
W
MO~
1
o
0
1
)
W
)
1
o
0
V
W
)
(OISP-H
MOD
(OISP-H
MOD
(OISP-H
1
1
W
1
1
1
1
0
)
)
0
0
0
RIM
RIM
)
)
1
1
1
00-03
)
(OISP-H
1
1
1
1
1
1
1
1
1
1
1
1
--RiMRIM
RIM
)
RIM
)
000
00-03
RIM
)
0
0
0
. - Rip,,,--
1
1
0
1
0
0
1 W
1
1
0
0
0
RIM
1
1
0
1
0
0
0 W
MOD
0
0
0
RIM
(OISP-L
)
(OISP-H
)
1
1
0
1
0
0
1 W
MOD
0
0
0
RI M
ROL
EA1, CL
(OISP-L
)
(OISP-H
)
~~(R~O==R--~E~A~1/~r~1~,~1~/C~L~---')---1-~1~1~~0·--~1----~0~70~V~~W~+-~M~O~0~--~0~~0~~1------~R'/~M~~--~0~0~--=073~
(OISP-L
ROR
ROR
ROR
r1,1
r1, CL
EA1,1
ROR
EA1,CL
(RCL
RCL
RCL
RCL
RCL
r1, 1
r1, CL
EA1,1
EA1, CL
J
(RCR
9-22
RCR
RCR
RCR
r1, 1
r1, CL
EA1
RCR
EA1, CL
0
0
1
1
0
(OISP-L
1
1
0
(OISP-L
1
1
0
(OISP-L
1
1
o
o
0
0
W
0
1
W
1
o
0
0
W
1
o
0
1
W
1
o
0
V
W
)
1
1
0
1
1
0
1
1
0
(OISP-L
1 1
0
(OISP-L
1
1
0
(OISP-L
1
1
1
1
1
EA1/r1,1/CL
)
1
1
1
1
0
0
1
1
1
1
0
(OISP-L
1
1
0
(OISP-L
)
)
o
o
0
0
W
0
1
W
o
0
0
W
)
W
)
1
o
0
1
1
o
0
V
W
)
(OISP-H
)
0
0
0
0
0
0
1
1
1
0
0
1
RIM
0
1
0
RIM
1
1
1
1
MOD
(OISP-H
MOD
(OISP-H
MOD
(OISP-H
0
0
0
1
1
1
0
0
0
0
1
0
RIM
0
1
1
RIM
)
- R/MRIM
RIM
)
)
00-03
)
0
0
W
1
1
0
1
0
1
W
1
1
0
1
0
0
W
0
1
o
0
1
W
MOD
(OISP-H
MOD
(OISP-H
0
• MITSUBISHI
"ELECTRIC
00-03
)
o
o
o
)
RIM
RIM
)
1
1
1
)
----RiM-
1
1
1
1
MOD
(OISP-H
MOD
(OISP-H
MOD
(OISP-H
1--------
---RiM--
1
1
1
RIM
RIM
1
1
RIM
)
)
MITSUBISHI LSls
MSL8086S
16-BIT PARALLEL MICROPROCESSOR
Flags
Clock cycles
Bytes in
the code
2
8+4/bit
lS+EA
20+EA+4/bit
Bus cycles
2
2
2-4
0
2-4
2
Function description
When V = 0: COUNT +- 1
if the high-order bit of (EA1/r1) = (CF) (OF) +- 0
if the high-order bit of (EA1/r1) l' (CF) : (OF) +-1
When V = 1: COUNT +- (CLI, (OF) is undefined
Shift one bit as indicated below and reduce COUNT by 1,
Repeat until COUNT becomes 0
0
2
El~1
',j
1
(EA1/rl )
<--
20+
EA + 4/bit
2
2
0
0
2-4
2
2-4
2
0---+1
When V
2
8+4/bit
lS+EA
2
2
2-4
0
0
2
20+EA+4/bit
2-4
2
2
2
0
8+4/bit
lS+EA
2
2-4
0
2
20+EA+4/bit
2-4
2
2
8+4/bit
lS+EA
2
2
2-4
0
0
2
20+EA+4/bit
2-4
2
2
2
2-4
0
0
2
20+EA+4 l bit
2-4
2
2
8+4/bit
lS+EA
2-4
0
2
20+EA+4/bit
2-4
2
2
2
0
Z
F
F
P
F
C
F
X
X
X
X
X
X
X
0
0
X
X
X
X
X
X
X
0
0
X
X
X
X
X
X
X
0
0
X
X
X
X
X
X
X
0
0
X
X
X
X
X
X
X
0
0
X
X
X
X
X
X
X
0
0
X
X
X
X
X
X
X
0
0
S
A
1---+ ~
(EAl /rl)
= 0: COUNT +- 1, (OF) +- 0
When V = 1: COUNT +- (CLI, (OF) is undefined
Shift one bit as indicated below and reduce COUNT by 1,
Repeat until COUNT becomes O.
ql
1---+E]
(EAl /r 1)
When V = 0 COUNT +- 1
if the high-order bit of (EA 1/r1) = (CF) (OF) +-0
if the high-order bit of (EA 1/r1) f (CF) (OF) +-1
When V = 1: COUNT +- (CLI, (OF) is undefined
rotate onebit as indicated below and reduce COUNT by 1
Repeat until COUNT becomes O.
i
~ ~
~
(EA1/rl)
When V - 0 COUNT +- 1
if the high-order bits of (EA 1/r1) are equal: (OF) +- 0
if the high-order bits of (EA 1/r 1) are not equal: (OF) +- 1
When V = 1 COUNT +- (CLI, (OF) is undefined
Rotate one bit as indicated below and reduce COUNT by 1
1Repeat until COUNT becomes O.
I ~Al/":
~EJ
When V = 0 COUNT +- 1
if the high·order bits of (EA1/r1) are eoual (OF) +- 0
if the high-order bits of (EA1/r1) are not equal (OF) +- 1
When V = 1: COUNT +- (CL), (OF) is undefined
Rotate one bit as indicated below and reduce COUNT by 1.
2
8+4/bit
lS+EA
F
F
I
0
When V = 0: COUNT +- 1
if the high-order bits of (EA 1/r1) are equal (OF) +- 0
if the high-order bits of (EA 1/r1 ) are not equal (OF) +- 1
When V = 1: COUNT +- (CLI, (OF) is undefined
Shift one bit as indicated below and reduce COUNT by 1,
Repeat until COUNT becomes O.
2
8+4/bit
lS+EA
F
T
F
D
F
0
j"""'" co,,,
COUN1 b,com~
~I
o.
(EA1/rl)
~
When V = 0 COUNT +- 1
if the high-order bits of (EA1/r1) are equal (OF) +- 0
if the high-order bits of (EA 1/r1 ) are not equal: (OF) +- 1
When V = l' COUNT +- (CL), (OF) is undefined
Rotate one bit as indicated below and reduce COUNT by 1
Repeat until COUNT becomes O.
~
(EAl /r 1)
I~~
• MITSUBISHI
.... ELECTRIC
9-23
a
MITSUBISHI LSls
MSL8086S
16-BIT PARALLEL MICROPROCESSOR
~
Instruction code
Mnemonic
Dz D, Do
Type of
instruction
><
~
~
a:
(REP
REPE/REPZ
REPNE/REPNZ
___1.. __ ~ ___1___1.. ______~ __ ~ __ ) ___ ~_____________________________________________ _
1
1
'1
F2-F3
0 0 1
001
1
0
0
W
A4-A5
1
W
A6-A7
MOVS
MEM1, MEM2
010
o
CMPS
MEM1, MEM2
010
o
c
Hexadecimal
notation
0
.~
i
t-=
1
c
0
';:
co
a.
c
0
.~
~
u
~c
E
SCAS
MEM
010
w
AE-AF
LOOS
MEM
010
o W
AC-AO
STOS
MEM
010
1
AA-AB
Cl
c
~
c
Sl
"0
co
.3
o
W
cadec;
nOtat; rnal
-Do
on
03
0000
0
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
1
2
3
4
5
6
7
8
9
A
B
C
0
E
F
0000
0
ADD
b,ear
ADC
b,ear
AND
b, ear
XOR
b,ear
INC
AX
PUSH
AX
-
JO
0001
1
ADD
w,ear
ADC
w,ear
AND
w,ear
XOR
w,ear
INC
CX
PUSH
CX
-
JNO
0010
2
ADD
b, rea
ADC
b, rea
AND
b, rea
XOR
b, rea
INC
OX
PUSH
OX
-
JB/
JNAE
0011
3
ADD
w, rea
ADC
w,rea
AND
w,rea
XOR
w,rea
INC
BX
PUSH
BX
-
JNB/
JAE
0100
4
ADD
b, ia
ADC
b, i
AND
b, i
XOR
b, i
INC
SP
PUSH
SP
-
JE/
JZ
0101
5
ADD
w,ia
ADC
w,i
AND
w,i
XOR
w,i
INC
BP
PUSH
BP
-
0110
6
SEG
ES
SEG
SS
INC
SI
PUSH
SI
-
PUSH
01
PUSH PUSH
ES
SS
NOP
MOV
MOV
AL~m
AL~i
XCHG
CX
MOV
MOV
AX~m
CL~i
XCHG
OX
MOV
MOV
AL~m
DL~i
XCHG
BX
MOV
MOV
AX~m
BL~i
XCHG MOVS
SP
b
AH~i
JNE/
JNZ
TEST XCHG MOVS
BP
w,ea
W
CH~i
JBE/
JNA
XCHG
b,ea
XCHG CMPS
SI
b
DH~i
-
JNBE/ XCHG
w,ea
JA
XCHG CMPS
01
W
CBW
TEST
b, i, a
AX~i
See
table
below
TEST
b,ea
MOV
MOV
MOV
7
POP
ES
POP
SS
DAA
AAA
INC
01
1000
8
OR
b,ear
SBB
b,ear
SUB
b, ear
CMP
b,ear
DEC
AX
POP
AX
-
JS
MOV
b, ear
1001
9
OR
w,ear
SBB
w,ear
SUB
w,ear
CMP
w,ear
DEC
CX
POP
CX
-
JWS
MOV
w,ear
CWO
TEST
w,i,a
CX~i
1010
A
OR
b, rea
SBB
b, rea
SUB
b, rea
CMP
b, rea
DEC
OX
POP
OX
-
JP/
JPE
MOV
b, rea
CALL
I, d
STOS
b
DX~i
1011
B
OR
w,rea
SBB
w,rea
SUB
w, rea
CMP
w,rea
DEC
BX
POP
BX
-
JNP/
JPO
MOV
w, rea
WAIT
1100
C
OR
b,i
SBB
b, i
SUB
b, i
CMP
b, i
DEC
SP
POP
SP
-
JLI
JNGE
MOV
easr
PUSHF LODS
b
1101
0
OR
w,i
SBB
w,i
SUB
w,i
CMP
w,i
DEC
BP
POP
BP
-
JNL/
JGE
LEA
PUSH
CS
PUSH
OS
SEG
CS
SEG
OS
DEC
SI
POP
SI
-
JLE/
JNG
MOV
srea
SAHF
AAS
DEC
01
POP
01
-
JNLE
/JG
POP
ea
LAHF
0111
111 0
1111
E
F
-
POP
OS
DAS
POPF
MOV
BH~i
MOV
MOV
MOV
STOS
MOV
W
BX~i
MOV
SP~i
LODS
MOV
W
BP~i
SCAS
b
MOV
SCAS
MOV
W
DI~i
SI~i
LOOPNZ
ILOOPNE LOCK
-
-
RET
(i+SP)
LOOPZ/
See
table
below
RET
LES
AAM
LOS
AAD
MOV
b,ea,i
MOV
w,ea,l
XLAT
LOOPE
-
LOOP
REP
z =0
JCXZ
REP
z=l
IN
b
HLT
IN
W
OUT
b
OUT
CMC
See
table
below
W
-
ESC
0
CALL
d
CLC
-
ESC
1
JMP
d
STC
RET
1.(i+SP)
ESC
2
JMP
I, d
CLI
RET
I
ESC
3
JMP
si, d
STI
INT
type 3
ESC
4
IN
b,v=l
CLD
INT
(any)
ESC
IN
w,v=l
STD
INTO
IRET
5
ESC
6
OUT
b, v=l
ESC
7
OUT
w,v=l
See
table
below
TABLE GROUP INSTRUCTION CODE LIST
modOr/m
000
o0
immed
ADD
OR
Shift
ROL
Grp 1
TEST
Grp 2
INO
o1
o1
1
1 0 0
10 1
1 1 0
111
ADC
SBB
AND
SUB
XOR
CMP
ROR
RCL
RCR
SHL/
SAL
SHR
-
NOT
NEG
MUL
IMUL
DIV
IDIV
J'4P
d
JMP
I, id
PUSH
-
1
DEC
0
CALL CALL
id
I, id
SAR
-
Note 33: Special symbols used only in the "Instruction set matrix" and the
Note 34:
"Group Instruction Code List".
EA"effective address (including register mode), REG"register
: byte operation
easr: (EA) +- (SR)
rea: processing results of REG and
w : Word operation
: immediate data
EA are transferred to REG
: this code should not be used
ia: immediate data and
: sign of 8 byte displacement is
because the result and function
accumulator
extended
are undefined
id : indirect address
srea: (SR) +- (EA)
: accumulator
is : immediate data in sign v : variable
: direct address
extended form
: z bit
ea : calculation of EA
: segment is included in
: shows direction of transfer.
ear: processing results of EA and
the jump
REG are transferred to EA
m : memory
•
9-34
The length of instructions varies from 1 byte (8 bits) to 6 bytes. The
"Instruction Set Matrix" is ordered by the hexadecimal value of the first
byte of the instruction. The instruction and its operands (an instruc·
tion may have no operand) are listed in mnemonic or symbolic form.
The group instructions (those instructions with different functions
depending on bit Os, 0 4 , 0 3 in the second word of the instruction) are
shown in the "Group Instruction Code List".
MlTSUBISHI
1'& ELECTRIC
MITSUBISHI BIPOLAR DIGITAL ICs
MSL8282P/MSL8283P
OCTAL LATCH
DESCRIPTION
The M5L8282P and M5L8283P are semiconductor integrated circu its consisting of sets of eight 3 -state latches for
use with various types of microprocessors.
PIN CONFIGURATION (TOP VIEW)
Vee
-+
(SV)
000
FEATURES
- 3 -state, high-fanout output
DATA INPUTS
........ " ......... " (lOL = 32mA, IOH = -5mA)
- Pin and electrical compatibility with the Intel 8282 and
8283
APPLICATION
DATA OUTPUTS
OUTPUT ENABLE
Data latches for various microcomputer systems
INPUT
STROBE INPUT
GNO
FUNCTION
Outline 20P4
The M5L8282P and M5L8283P are latches with noninverted and inverted outputs, respectively.
When the strobe input STB is high, the data inputs 010
'" 017 are passed through the data outputs 00 0 '" 00 7
(M5 L8282P) or to the data outputs 00 0 '" 00 7
(M5L8283P), changes in the 010 '" 017 signals being
reflected in the data outputs.
If the STB is changed from high to low, the data 010 '"
017 just before the change is latched. If the 01 data is
changed while STB is low, this change is not reflected in the
data outputs.
When OE is made high, all the data outputs go into the
high-impedance state, the data latched prior to OE going
high being held.
01 0-+ 1
Vee
-+
(SV)
000
DATA INPUTS
DATA OUTPUT
OUTPUT ENABLE
INPUT
GNO
11
+-- S T B STROBE INPUTS
Outline 20P4
BLOCK DIAGRAM-
DATA INPUTS
DATA INPUTS
DATA OUTPUTS
DATA OUTPUTS
0 16
016
STROBE INPUT
STROBE INPUT
OUTPUT ENABLE
INPUT
OUTPUT ENABLE
INPUT
•
I
I
----=---4
M5L8283P
GND
MITSUBISHI
"ELECTRIC
9-35
MITSUBISHI BIPOLAR DIGITAL ICs
MSL8282P/MSL8283P
OCTAL LATCH
ABSOLUTE MAXIMUM RATINGS
Symbol
(Ta = D-75°C, unless otherwise noted)
Conditions
Parameter
Limits
Unit
Vee
Supply voltage
-0.S-+7
V
VI
Input voltage
-O.S- +S.S
V
Vo
Output voltage
-O.S-Vee
V
Topr
Operating free-air temperature range
0- +7S
·C
Tstg
Storage temperature range
·C
-6S- + 1S0
RECOMMENDED OPERATING CONDtTIONS
(Ta =D-75"C,unlessotherwisenoted)
Limits
Parameter
Symbol
Vee
Supply voltage
IOH
High·level output current
IOL
Low·level output current
I
I
Min
Nom
Max
4 .S
S
S .S
V
VOH~2 .4V
0
-S
mA
VOL~0.4SV
0
32
mA
ELECTRICAL CHARACTER ISTICS
(Ta = D-75°C, unless otherwise noted)
Limits
Parameter
Symbol
Unit
Unit
Test conditions
Min
VIH
High·level input voltage
VIL
Low·level input voltage
Typ
Max
V
2
0.8
V
-1
V
o.4S
V
Vie
Input clamp voltage
Vee=4.SV, Ile= -SmA
VOH
High·level output voltage
Vee=4.5V, IOH= -5mA
VOL
Low·level output voltage
Vee=4.SV, IOL =32mA
IOZH
Off-state output current, high·level applied to the output
Vee=S.SV, VI=2V, VO=S.25V
IOZL
Off·state output current, low-level applied to the output
Vee=S.5V, VI=2V, VO=0.4V
IIH
High·level input current
Vee=S.SV, VI=5.2SV
SO
/-lA
IlL
Low·level input current
VCC=S.SV, VI=0.4SV
-0.2
mA
Ice
Supply current
Vce=S.5V
160
mA
GIN
I nput capacitance
F=1MHz, VBIAS=2.5V
Vee=SV, Ta =2S·C
12
pF
V
2.4
SO
/-lA
-SO
/-lA
SWITCHING CHARACTERISTICS (Vee = 5V±10%, Ta =0-75°C, unless otherwise noted)
M5L8283P
M5L8282P
Symbol
Parameter
Alternate
symbol
Test
conditions
Limits
Min
tpLH
tpHL
Propagation time from 01 input to DO
or 00 for low-to-high or high-to-Iow
change
TIVOV
tpLH
tpHL
Propagation time from STB input to
DO or DO for low-to- high and highto-low change
TSHOV
Typ
Unit
Limits
Max
Min
Typ
Max
S
30
5
22
ns
10
45
10
40
ns
(Note 2)
tPZH
tPZL
Propagation time from OE input to DO
or 50 output when -output is enabled
TELOV
10
30
10
30
ns
tpHZ
tpLZ
Propagation time from OE input to DO
or DO output when the output is disabled
T EHOV
S
18
5
18
ns
tr
Output rise time
TOLOH
From 0.8V
to 2V
20
20
ns
tf
Output fall time
TOHOL
From2V
to 0.8V
12
12
ns
•. MITSUBISHI
9-36
.... ELECTRIC
--
MITSUBISHI BIPOLAR DIGITAL ICs
MSL8282P/MSL8283P
OCTAL LATCH
TIMING REQUI REMENTS(vcc ~ 5V ±10%, Ta ~ O~75°C,unless otherwise notedl
Symbol
Limits
Alternate
symbol
Parameter
Test conditions
Unit
Min
Typ
Max
Strobe ST8 high pulse width
TSHSL
15
ns
Strobe ST8 setup time for 010 -017
TIVSL
0
ns
th
ST8 hold time for 010 - 017
TSLIx
ti-
Input rise time
TILIH
From O.BV to 2V
20
ns
tf
Input fall time
TILIH
From 2V to O.BV
12
ns
tW(STBH)
tsu
ns
25
f-"
Note 3.
Note 2.
Test Circuit
TEST ITEM
INPUT
Vee
r---"
I
DEVICE
~--<>----J LOAD
UNDER TEST
I
I
I
2.14V
I
I
I
P.G.
tPLH, tPHL
I
CIRCUIT
(Note
I
31
I
I
I
LOAD CIRCUIT
tPHZ, tPZH
1.5V
1.5V
~527Q ~33Q ~180Q
I
L ____ J
r'OOPF
TIMING DIAGRAM
tPLZ, tPZL
OUTPUT
~ 300pF
r'OOPF
(Referencevoltage~ 1.5VI
II
ST8
PRECAUTIONS FOR USE
Care shquld be taken to accommodate the glitch that is
generated when STB goes from low to high with the output
low for the M5L8283P.
•
MITSUBISHI
.... ELECTRIC
9-37
MITSUBISHI BIPOLAR DIGITAL Ie.
MSL8282P/MSL8283P
OCTAL LATCH
APPLICATION EXAMPLES
(1) Use in the maximum mode
0
Vec
M5L8Z84P
RtS
r
ClK
MN/MX
CLOCK
GENERATOR
So
ClK
So
READY
S;
S;
RESET
Sl
sz
MADC
MWTC
AMWC
III! 5LIm p i"OAC
BUS
I A
DEN CTRlR
IOWC
RDY
R
DT
M5LI08iS
CPU
AIOWC
iNTA
ALE
LCiCK
COMMAND BUS
N.C.
- AD 151/L.-___--'-......L".:..:..:....J\ I
A 16- A 19
AD~
l-MEGABYTE
ADDRESS BUS
BHE
I".-_ _ _~/ 16-BIT DATA BUS
(2) Use in the minimum mode
MN MX
M5LI284P
GE~~~~~OR ~
t--
!
f--
RES
f--- Vec
ClK
M m~--------------
READY
INTA~----------------------
RD~---------------
~ RESET
RDY
.} COMMAND BUS
WR~-------------------
f
DT R 1 - - - - - ,
DENf----,
M5UI086S
:
r-----,
, ,
CPU
1
,
I
I
,
1
I
AlE~--~-~I~~STB
II
ADo
A 16
A 19
M5 L8282P
BHE -
:
I
,
1
-
I 1
,I
r
1 L--,T
1
,
: - - - - - \ l-MEGABYTE
lA TCH
2 OR 3
v
1---1-,-"-:--~
"
I
,-- OE
'77T.
11
I
AD 15 \. .-----A9DR DATA
I
i
---,
I
I I
I I
M5 L8286P*
I IjL----~
I l"-r
I
(2 )
I I
IL ____ ...JI.J
*
TRANSCEIVER
Option
Required when the number of devices
driving the bus increases
•
9-38
ADDRESS BUS
c.-----,
L--~5E
L-----i.
I
~
MlTSWISHI
i'& ELECTItIC
(
16-BIT DATA BUS
MITSUBISHI BIPOLAR DIGITAL Ie.
MSL8284P
CLOCK GENERATOR AND DRIVER FOR 8086, 8088" 808' PROCESSORS
DESCRIPTION
The M5l8284P is a semiconductor integrated circuit
consisting of a clock generator for use with the 8086 and
8088 16-bit microprocessors.
It has a synchronous delay circuit and synchronous reset
circuit capable of controlling two Multibus (Intel trade
mark) circuits.
PIN CONFIGURATION (TOP VIEW)
CLOCK
SYNCHRONIZATION
INPUT CSYNC --+
ADDRE~~~~A:L1E
FEATURES
1
Vee (SV)
PERIPHERAL
CLOCK OUTPUT
X 1 CRYSTAL TERMINAL 1
AEN 1 --+
X 2 CRYSTAL TERMINAL 2
READY INPUT 1
• Stable, crystal controlled output frequency
• Synchronous operation of several M5l8284Ps is possible
• External clock input
• By means of an external capacitor and resistance a
power-on reset signal can be generated
• Pin and electrical compatibility with the Intel 8284
NC
READY OUTPUT
-
EF I
READY INPUT 2
_
F/
ADDRESS ENABLE
INPUT 2
CLOCK
OUTPUT
(ov)
AEN 2 --+
C
2~6ECRKN~~UT
~L~U~K SELECTION
--+ OSC OSCILLATOR
7
OUTPUT
CLK-
-
GND
--+ RESET
RES RESET INPUT
~~~~~T
APPLICATION
Clock driver and generators for the 8086 or 8088.
FUNCTION
The M5l8284P is a clock generator/driver for the 8086,
8088 or 8089 processors.
Internally the crystal oscillator signal is divided by three
to provide the clock output ClK, and by two to provide
the peripheral clock output PClK. In addition, a reset
circuit and ready circuit are provided to ensure synchronization to the ClK signal.
The reset input RES is used to generate the reset output
RESET as the CPU reset signal synced to the ClK signal. A
Schmitt trigger circuit is used at the input side.
Thus, a reset signal can be output at power on by
connecting a capacitor and resistor to the RES input.
Outline 18P4
NC : NO CONNECTION
The clock selection input F/C can be used to select the
crystal oscillator circuit output or an external clock input
as the input for the divide by three circuit.
By using these pins, the M5l8284P output can be used
to drive multiple M5l8284P devices.
The clock synchronization input CSYNC is used to
operate multiple M5l8284Ps in synchronous.
The ready inputs RDY1 and RDY2 are used to generate
the ready output READY. These ready inputs are valid
when the address enable inputs AEN1 or AEN2 respectivel y _
are low.
The PClK, RESET, and READY signals operate internally synchronized to the ClK signal.
BLOCK DIAGRAM
Vee
RESET INPUT
RES
CRYSTAL TERMINAL 1
Xl
CRYSTAL TERMINAL 2
X2
CLOCK SELECTION INPUT
FIG
EXTERNAL CLOCK INPUT
EF I
RES E T RESET OUTPUT
OSCILLATOR OUTPUT
CLOCK OUTPUT
CLOCK SYNCHRONIZATION INPUT CSYNC
2 PC L K
PERIPHERAL CLOCK OUTPUT
1
READY INPUT 1
READY OUTPUT
ADDRESS ENABLE INPUT 1
ADDRESS ENABLE INPUT 2
AEN 2 7
READY INPUT 2
• MITSUBISHI
.... ELECTRIC
9-39
iii
MITSUBISHI BIPOLAR DIGITAL ICs
MSL8284P
CLOCK GENERATOR AND DRIVER FOR 8086, 8088, 8089 PROCESSORS
PIN DESCRIPTIONS
Pin
AEN1,
Input or
output
Name
Address enable input
Input
Function
When AEN1 and AEN2 are made low, ROY1 and ROY2 are made effective respectively. By using these two
inputs separately, the CPU can be used to access two Multibusses.
AEN2
When not used as a multimaster, AEN should be set to low.
These inputs are active low.
RDY1,
Input
Bus ready input
RDY2
These inputs are connected to the signal indicating the completion of data reception from a system bus device
or a signal output indicating that data is valid.
ROY1 and ROY2 are effective when AEN1 and AEN2 are low respectively.
These inputs are active high.
READY
Ready output
Output
The state of ROY appears at this output in synchronization with the ClK output.
This is done to synchronize the READY output to the M5l8284P internal ClK because the ROY input changes
in an asynchronous fashion with respect to ClK.
This pin is normally connected to the CPU ready input and cleared after the required CPU hold time, tho
I
Xl, X2
Crystal element terminals
Input
These pins are used to make connections to the crystal.
The crystal should have a frequency such that the period is three times the CPU cycle time. The crystal should
be chosen in the range 12-25MHz and have as low as possible a series resistance. Care should be taken not to
ground these pins.
F/C
Clock selection input
Input
When this input is set to low, the ClK, and PClK outputs are driven from the crystal oscillator output and when
EFI
External clock input
Input
When FIC is high, the signal input at this pin is used to drive ClK and PClK.
it is set to high, they are driven from the EFI input.
The input is a rectangular TTL level signal of frequency such that the period is three times the CPU cycle time.
CLK
Clock output
Output
This output is connected to the CPU and the clock inputs of the surrounding ICs connected to the local bus.
The output waveform is 113 the frequency of the crystal connected to X1 and X2 or the FE I input frequency
and has a duty cycle of 1/3.
Since for Vee ~ 5V, VOH ~ 4.5V, this output can be directly connected to the CPU clock input.
PCLK
Peripheral clock output
Output
This output is used as the clock signal for peripheral devices.
The output waveform is a 50% duty cycle TTL level rectangular waveform having a frequency of 1/2 the ClK
output frequency.
OSC
Oscillator output
Output
This output is a TTL level crystal oscillator circuit output.
The frequency is the same as that of the crystal connected to Xl and X2 but care should be taken as the
frequency will be unstable if these pins are left open.
RES
Reset input
Input
This active low input is used to generate the reset output signal for the CPU.
The input uses a Schmitt trigger circuit so that by connecting a capacitor and resistance, the CPU power·up
reset can be generated.
RESET
CSYNC
Output
Reset output
Clock synchroni/ation input
Input
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Connected to the CPU RESET input.
The RES is synchronized to the ClK signal. This output is active high.
For using multiple M5l8284P devices, this input is used as a clock synchronization input.
When CSYNC is made high, the internal counter of the M5l8284P is reset and when it is made low it begins
operation.
CSYNC must be synchronized with EFI. Refer to the Section on using this device.
(Ta= Q-75°C, unless otherwise noted}
Conditions
Limits
Unit
Vee
Supply voltage
-0.5-+7
V
VI
Inputvoltage
-0.5-+5.5
V
Va
Output voltage
-0.5- +Vee
Topr
Operating free-air temperature range
Tstg
Storage temperature ra nge
9-40
0-+75
-65- + 150
• MITSUBISHI
.... ELECTRIC
V
·C
·C
MITSUBISHI BIPOLAR DIGITAL ICs
MSL8284P
CLOCK GENERATOR AND DRIVER FOR 8086,8088, 8089 PROCESSORS
RECOMMENDED OPERATING CONDITIONS
(Ta
=0-75°C, unless otherwise noted)
Limits
Symbol
Parameter
Vcc
Supply voltage
IOH
High-level output current
IOL
low-level output current
--
Unit
Min
Nom
Max
4.5
5
5.5
V
0
-1
mA
0
5
mA
VOH~4V
ClK
Other outputs VOH ~ 2 . 4 V
VOL~0.45V
ElECTR ICAl CHARACTER ISTICS (Ta = 0-75°C, unless otherwise noted)
Limits
Symbol
Parameter
Unit
Test conditions
Min
High-level input voltage
VIH
I
RES
I
Other inputs
Typ
2.6
V
V
2
low-level input voltage
VIL
VT--
VT+
Hysteresis width
RES
I
Max
0.8
V
-1
V
0.25
VCC=5V
V
VIC
I nput clamp voltage
VOH
High-level output voltage
VOL
low-level output voltage
VCC=4.5V, IOL =5mA
0.45
IIH
High-level input current
VCC=5.5V, VI=5.25V
50
fJ. A
IlL
low-level input current
VCC=5.5V, VI=0.45V
-0.5
mA
ICC
Supply current
Vcc=5.5V
140
mA
VCC=4.5V,llc=-5mA
4
I
CLK
I
Other outputs
V
VCC=4.5V, IOH= -1mA
SWITCH ING CHARACTER ISTICS
2.4
(Vee
V
V
= 5V ±10%, Ta = 0-75°C, unless otherwise noted)
Limits
Symbol
Parameter
Alternate symbol
Test conditions
Unit
Min
Typ
Max
TC
ClK repetition period
TCLCL
TW(CLKH)
ClK high pulse width
TCHCL
TW(CLKL)
ClK low pulse width
TCLCH
tTLH
TCH 1CH2
1V-3.5V
tTHL
ClK Jqw-Ieyel to high-level
transition time
ClK high-level to low-level
transition time
TCL2CL1
3.5V-1V
TW(PCLKH)
PClK high pulse width
TPHPL
TC-20
ns
TW(PCLKL)
PClK low pulse width
TPLPH
TC-20
ns
td IV
READY invalid time with
respect to ClK (Note 1)
TRYLCL
-8
ns
(2hTC)-15
ns
125
ns
(1!JTC)+2
ns
(2!JTC)-15
ns
10
J
I
10
ns
ns
(Note 5.)
tdv
READY valid time with
respect to ClK (Note 2)
TRYHCH
TOHL(CLK-RESET)
High-level to low-level delay time
From ClK to RESET
TCLIL
TOLH(CLK-PCLK)
low-level to high-level delay time
From ClK to PClK
TCLPH
22
ns
TOHL(CLK-PCLK)
High-level to low-level delay time
From ClK to PClK
TCLPL
22
ns
TOLH(OSC-CLK)
low-level to high-level delay time
From OSC to ClK
TOLCH
-5
12
ns
TOLCL
2
20
ns
High-level to low-level delay time
T OHL(OSC-CLK)
From OSC to ClK
• MITSUBISHI
"ELECTRIC
40
ns
9-41
MITSUBISHI BIPOLAR DIGITAL' ICs
MSL8284P
CLOCK GENERATOR AND DRIVER FOR 8086, 8088,8089 PROCESSORS
TIMING REQUIREMENTS
(Vee = 5V ±10%. Ta=D-75°C. unless otherwise noted)
Limits
Symbol
Parameter
Alternate symbol
Test conditions
Min
f (X'tal)
Crystal frequency
max
Typ
12
Max
25
Unit
MHz
tW(EFIH)
EFI high pulse width
TEHEL
VI (90%-90%)
t W(EFIL)
EFI low pulse width
TELEH
VI(10%-10%)
TC(FEI)
EFI repetition period (Note 3)
TELEL
t SU (ROY)
ROY1 and ROY2 setup time with
respect to C L K
TRlVCL
35
ns
t h(ROY)
ROY1 and ROY2 hold time with
respect to C l K
TCLR 1X
0
ns
t SU (AEN)
AEN1 and AEN2 setup time with
respect to ROY1 and ROY2
TA1R1V
15
ns
t h(AEN)
AENl and AEN2 hold time with
respect to C l K
TCLA1X
0
ns
t SU (CSYNC)
CSYNC setup time with respect to EF I
TYHEH
20
ns
t h(CSYNC)
CSCYNC hold time with respect to
EFI
TEHYL
20
ns
t W(CSYNC)
CSYNC pulse width
TYHYL
2TC(EFI)
ns
t SU(RES)
RES setup time with respect to ClK
(Note 4)
Tl1HCL
65
ns
TCLl1H
20
ns
'RES hold time with respect to ClK
th(RES)
(Note 4)
I
j
13
ns
13
ns
tW(EFIH)
ns
tW(EFIL)
(Note 5)
Note 1, Applies to T2 state time
2, Applies to T3 and TW state times
3, (; = EFI tR (5ns rnax) + EFI tF (5ns max)
VCC
4. tSU(RES) and thIRES) are required only to guarantee the next clock period
1kQ
Note 5. Test circuit
CLKi-=8'----------------I
AEN1
17 Xl
CL KI-'8'-------t
15MHz D
Y
OSC 12
13 RD~2
15MHzc:::J
16
READ Y 1-"5'---_ _--;
X2
12- 15pFf,
17 Xl
y
6
1
X2
F/C
7 AEN 2
TRIGGER
12-15pF
1 CSYNC
13 F/C
CSYNC
VCC
r
Vec
1kQ
1kQ
t--,.---+----'.1,4 E F I
13 F/C
8
CLKt-----------I
13 Fie
C L K1 - - - - - - - 1
~
AEN 1
1--------'=-tRDY2
1--_ _ _1_4--t E F I
7-AEN2
CSYNC
1 CSYNC
READY
•
9-42
MITSUBISHI
.... ELECTRIC
MITSUBISHI BIPOLAR DIGITAL Ie.
MSL8284P
CLOCK GENERATOR A.ND DRIVER FOR .0•• , 80•• , .0•• PROCESSORS
LOAD CI RCUIT
OUTPUT
Vee
THE DIODES ARE 1N3064 OR EQUNAlENT
Note 6. CL z 100pF
7. CL = 30pf
8. The capacitance CL includes all the coupling and floating capacitances of the probe input circuit.
TIMING DIAGRAM
(Reference level = 1.5V)
.../\J\._
.../\J\._
EFI (INPUT)
OS C (OUTPUT)
--.r----.r---
C L K (OUTPUT)
PCLK (OUTPUT)
ROY1,2 (INPUT)
AtNT;'Z
(INPUT)
READYm~~{ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~_
CSYNC (INPUT)
RES (INPUT)
RES E T (OUTPUT)
APPLICATION NOTES
(1) Connecting the cryst,al
OSC
(2) Ext.nat clock connections
SV
12
(
X'taiD
~ 16 Xz
CLKf!8~_ _ _......:14!J CLK
1kQ
-
M5L8214P
CL
13
EXTERNAL CLOCI(
(TIL LEVEL 50% DU TY CYCLE)
1~
II
Xl
X2
~ FIG
FIG
The crystal frequency should be chosen such that the
period is three times the cycle time of the 808S or 8088
and when connecting it care should be taken that it is
located as close as possible to the M5L8284P.
To ensure stable oscillations, a ceramic capacitor should
be placed in series with the crystal at pin X2 . Suitable
values of capacitance for 15MHz, 12MHz, and 22MHz, are
12"'15pF, 24pF, and 8pF respectively.
17
.J!
CLK
a
19 CLK
EFt
101.
M5LI214P
BGaa
The maximum frequency of the external clock is 25MHz
and while there is no lower limit on the frequency it should
be set at least three times the CPU minimum clock
frequency.
(3) Synchronizing using the CSYNC input
• When the EFI input is used
Vee (5V)
M74LS74AP
EXTERNAL
SYNCHRONIZATION
INPUT
(SYNC)
M5L8284P
--------1
EXTERNAL CLOCK
(EFI)
9--43
MITSUBISHI BIPOLAR DIGITAL ICs
MSL8284P
CLOCK GENERATOR AND DRIVER FOR 8086, 8088, 8089 PROCESSORS
• When the E F I input is not used
Since the 8086, 8088 and 8089 require a reset pulse over
50tls after Vee reaches 4.5V upon power up, the capacitor
M5L8284P
Vee (SV)
value should be determined by the graph shown below. Note
12
that the time for Vee to reach 4.5V has not been considered
so that it is necessary to use a value of C larger than in
the power supply used.
EXTERNAL
SYNCHRONIZ~J~~~ ~_---;
(SYNCI
Ve(t) = V (1 - e
RES VOLTAGE Vc (tl
(V)
(4)
~~)
V =4.SV
t =SO,us
Vc(t) = 1.0SV
R C:::: 1 90
x
10 - 6
Power-on reset circuit
V
R= 1k-10kQ
SO,us
CHANGE IN RES INPUT VOLTAGE
...-_ _ _
1-11 RES
r
PRECAUTIONS FOR USE
If noise is allowed to enter the XTAL 1 and XTAL2 or Vee
pins, the oscillator frequency will be pulled off the parallel
resident frequency and the stray capacita nce between
XTAL1 and XTAL2 may cause the circuit to go into
relaxatior;l oscillation. To prevent this, care should be given
to the following points.
(1) The
crystal
should
be one with a small parallel
capacitance.
(2) A capacitor of. value 0.01 to 0.1tlF with good high
frequency characteristics should be connected between
Vee and the ground. This capacitor should be mounted as close as possible to the IC.
•
9-44
MITSUBISHI
.... ELECTRIC
(t)
MITSUBISHI BIPOLAR DIGITAL ICs
MSL8284P
CLOCK GENERATOR AND DRIVER FOR 8086, 8088, 8089 PROCESSORS
APPLICATION EXAMPLES
( 1) Use in the maximum mode
CLK
MN/MX
CLOCK
GENERATOR
RES
M5L8284P
r
CLK
So I------~Sii
READY
Sj 1 - - - - - - - - - . l S j
RESET
Si I------~S;
ROY
AMWC
M5~~~88P
DEN
DTIR
M5L8086S
CPU
-IOR-C
COMMAND BUS
CTRLR
AIOWC
ALE
INTA
N.C.
LOCK
I-MEGABYTE ADDRESS BUS
,,~_ _ _~/
16-BIT DATA BUS
(2) Use in the minimum mode
15MHz
MN MX
M5L8284P
GE~~~~~OR ~
~ RES
M
READY
INTAI------------------
~ RESET
RDI---------------
f.-
-
COMMAND BUS
-
ROY
GND
f---- Vee
ml-----------------
CLK
WRI-----------------
i
DT R - - - - - ,
DEN
----I :
M5L8086S
r------,
: I
CPU
r
I I
I
I
ALEI----~I-~I~~STB
11r-11
I
BHE -
'I
r
11
I-'--I--'-:-~
:
I
I
I
I
I
M5L8282P
ADo ~ADI5 ,,~DR DATA
A 16 ~ A 19
I
5E
1m.
I
LATCH
2 OR 3
J
c.----...,
r ----, I
L-~T
--~5E
1
M5L8286P
'---------I, TRANSCEIVER
------l\
----v
I-MEGABYTE ADDRESS BUS
I I
I I
I IJL
I
'\
I\r----~v 16-BIT DATA BUS
I
(2 )
I I
IL ____ ..JU
OPTION'
REQUIRED WHEN THE NUMBER OF DEVICES DRIVING THE
BUS INCREASES
• MITSUBISHI
.... ELECTRIC
9-45
MITSUBISHI BIPOLAR DIGITAL ICs
MSL8286P/MSL8287P
OCTAL BUS TRANSCEIVER
DESCRIPTION
PIN CONFIGURATIONS (TOP VIEW)
The MSL8286P and MSL8287P are semiconductor integrated circuits consisting of a set of eight 3-state output bus
transceivers for use with a variety of microprocessor
systems.
Vee
+-+
90
4-09,
FEATURES
•
3-state, high·fanout outputs (l oL = 16mA, IOH = -1mA
for the A outputs and IOL = 32mA, IOH = -SmA for
the B outputs)
• Electrical and pin compatibility with the Intel 8286 and
8287
LOCAL BUS
DATA
SYSTEM BUS
DATA
ENABL~~~:~~
0
E- --+
GND
APPLICATION
Two-way bus transceivers for microcomputer systems
TRNSMIT INPUT
Outline 20P4
FUNCTION
The MSL8286P and M5L8287P are two-way bus transceivers with non-inverted and inverted outputs respectively.
When the output enable input OE is high, the local bus
data pins Ao '" A7 and system data pins Bo '" B7 are both
placed in the high-impedance state.
When the output enable input OE is low, the input and
output states are controlled by the transmit input T.
When T is high, Ao '" A7 are input pins and Bo '" B7 are
output pins. When T is low, Bo '" B7 are input pins and Ao
'" A7 are output pins.
BLOCK DIAGRAM
LOCAL BUS DATA
SYSTEM BUS DATA
OUTPUT ENABLE
INPUT
OUTPUT ENABLE
INPUT
M5L8286P
9 - -46
SYSTEM BUS
DATA
LOCAL BUS DATA
TRNSMIT INPUT
M5L8287P
• MITSUBISHI
"ELECTRIC
MITSUBISHIBIPOLAR DIGITAL ICs
MSL8286P/MSL8287P
OCTAL BUS TRANSCEIVER
FUNCTION TABLES
(Note 1)
M5L8286P
M5L8287P
OE
T
A
B
OE
T
A
L
L
0
I
L
L
0
I
L
H
I
0
L
H
I
0
H
X
Z
Z
H
X
Z
Z
B
Note 1. I: Input pin
0,0:
Output pin (non-inverted for the M5L8286P
and inverted for the M5L8287P)
Z: Indicated the high-impedance state (A and B
are separated)
X: Either high or low
ABSOLUTE MAXIMUM RATINGS
Symbol
(Ta = 0-75°C, unless otherwise noted I
Conditions
Parameter
Limits
Unit
Vee
Supply voltage
-0.5-+7
V
VI
I nput voltage
-0.5-+S.S
V
Vo
Output voltage
-0.5- V ee
V
Topr
Operating free-air temperature range
0- +7S
cC
Tstg
Storage temperature range
RECOMMENDED OPERATING CONDITIONS
Vee
(Ta = 0-75°C, unless otherwise noted)
Limits
Symbol
Parameter
Supply voltage
IOH
High-level output
current
IOL
Low-level output
current
cC
-65 - + 150
A output
VOH~2 .4V
B output
A output
VOL:;:;;O.4SV
'1
B output
ELECTRICAL CHARACTERISTICS
Unit
Min
Nom
Max
4.5
5
5.5
V
0
-1
mA
0
-- 5
mA
0
16
mA
0
32
mA
II
(T a = 0-7S0C, unless otherwise noted)
Limits
Symbol
Parameter
Unit
Test conditions
Min
VIH
VIL
VIC
VOH
VOL
IOZH
IOZL
Typ
Max
High-level input voltage
V
A input
0.8
V
B input
0.9
V
Low-level input voltage
Input clamp voltage
-1
Vee=4.SV,lle=-SmA
A output
VcC=4.SV,IOH--1mA
2.4
2.4
High-level output voltage
B output
Vce=4.5V, IOH= -5mA
A output
VCC=4.5V,IOL=16mA
0.45
V
B output
VCC=4.5V,IOL=32mA
0.45
V
A output
Vee=S.SV, VI=2V
VI=0.8V
B output
Vo=S.2SV
VI'=0.9V
Low-level output voltage
Off-state output current, with high-level
applied at the output
Off-state output current, with low·level
applied the output
V
V
A output
Vce=5 .5V. VI= 2V
B output
VO=0.45V
V
SO
/lA
-0.2
mA
VI=0.8V
1------
VI=0.9V
IIH
High·level input current
vee=5.sv, VI=5.25V
50
/iA
IlL
Low·level input current
Vee = 5 . 5 V , V 1= 0 . 45 V
-0.2
mA
MSL8286P
Icc
Supply current
Input capacitance
mA
130
mA
12
pF
Vce= 5.SV
M5L8287P
GIN
160
F=1MHz, VBIAS=2.SV
VCC=5V, Ta=25°C
• MITSUBISHI
.... ELECTRIC
9-47
MITSUBISHI BIPOLAR DIGITAL ICs
MSL8286P/MSL8287P
OCTAL BUS TRANSCEIVER
SWITCHING CHARACTERISTICS
(Vee
= 5V ±10%, Ta = D-75°C, unless otherwise noted)
M5l8286P
Symbol
Alternate
symbol
Parameter
Test
conditions
Typ
Min
tPLH
tpHL
low-level to high-level and
high-level and low-level
transition time from input A.
B to outputs B, A
tPZH
tPZL
Output enable time from
input to A or B output
tpHZ
tpLZ
M5l8287P
Limits
Limits
Max
Min
Typ
Unit
Max
S
30
S
22
ns
TElOV
10
30
10
30
ns
Output disable time from OE
input to A or B output
TEHOZ
S
18
5
18
ns
tr
Output nsetlme
TOlOH
From O.8V
to 2V
20
20
ns
tf
Output falltime
TOHOl
From 2V
to 0.8V
12
12
ns
TIVOV
(Note 2)
5E
TIMING REQUIREMENTS (Vee = 5V ±10%, Ta = 0-75°C, unless otherwise noted)
Limits
Alternate
symbol
Parameter
Symbol
Unit
Test conditions
Min
Typ
Max
tsu
T setup time with respect to OE
TTVFL
10
ns
th
T hold time with respect to OE
TEHTV
S
ns
tr
Input risetime
TIUH
From 0.8V to 2V
20
ns
tf
Input falltime
TIUL
From 2V to 0.8V
12
ns
Note 2. Test Circuit
INPUT
Vee
OUTPUT
r---'
I
I
I
I
DEVICE
UNDER TEST
PG
LOAD CIRCUIT II
I (Note 3)
1----4-----.1
SOQ
I
I
I
I
I
I
L ____ J
Note 3.
TEST ITEM
tPLH, tPHL
A OUTPUT
~"4Q
A OUTPUT
2.14V
A OUTPUT
~527Q
B OUTPUT
300pF
r
• MITSUBISHI
..... ELECTRIC
~33Q
r'ODPF
~900Q
T100pF
*
1.5V
B OUTPUT
9-48
~66Q
~100PF
r'ODPF
B OUTPUT LOAD CIRCUIT
l.SV
1.SV
2.28V
A OUTPUT LOAD CIRCUIT
tPHZ, tPZH
tPLZ, tPZL
1.SV
~"OQ
B OUTPUT
r'ODPF
MITSUBISHI BIPOLAR DIGITAL ICs
MSL8286P/MSL8287P
OCTAL BUS TRANSCEIVER
TIMING DIAGRAM
(Reierencevoltage=1.5V)
OE ,
A, B (INPUTS)
M5L8286P
B, A (OUTPUTS)
B, A (OUTPUT)
lV
M5L8287P
B, A (OUTPUTS)
OE
T
B, A (OUTPUTS)
VowO.1V
T
APPLICATION EXAMPLE
v cc
c;
f---...
r 01
M5 L8284P
CLOCK
GENERATOR
RES
--'-
I
1
~ '"
f-f--
MN/MX
So
READY
5,
S;
RESET
52
52
r -
.--
M5L8086S
CPU
MRDC
AMWC
M5L8288P _
BUS
IORC
DEN
CTRlR
DT/A
IOWC
AIOWC
,--- ALE
lOCK --N.C.
r--------
MWTC ~
So
ROY
I
ClK
_GND
INTA
---
COlvlMAND BUS
------
II
1
i
~ STB
ADo~ADI5
A16~A19
r. DE
11
~DDR DATA
v
M5L8282P
LATCH
(2 OR 3)
BHE t - - - -
)
I-MEGABYTE ADDRESS BUS
V
r-
r-
I
Lt;::
,T
DE
M5 L8286P
)
TRANSCEIVER
( 2 )
~
16-BIT DATA BUS
V
f\
v
•
r-
MITSUBISHI
.... ELECTRIC
9-49
MITSUBISHI BIPOLAR DIGITAL ICs
MSL8288P
BUS CONTROLLER FOR 8086, 8088, 8089 PROCESSORS
DESCRIPTION
The
MSL8288P
PIN CONFIGURATION (TOP VIEW)
is a semiconductor integrated circuit
consisting of a bus controller and bus driver for the 8086
and 8088,
16-bit microprocessors. By using the status
signals from the CPU a Multibus (Intel trademark) control
I/O BUS MODE
INPUT
lOB ---+
signal is generated.
CLDCK INPUT
ClK---+
STATUS INPUT
S;---+
~:~~:~~~~~0T;
DT/R'-
:~f:c:~~~~~
AlE'-
FEATURES
•
High-fanout outputs
Command output 10 L=32mA, 10H=-SmA
ADDRESS
Control output 10L =16mA, IOH=-1mA
•
Advanced command outputs (AIOWC and AMWC outputs)
•
Pin and electrical compatibility with the Intel 8288
- So
- 51
MRDC'ADvANcm _ _
MEMORY WRITE AMWC +-COMMAND .oUTPUT
MEMORY WRITE MWTC . COMMAND OUTPUT
(OV) GND
(5V)
1
STATUS INPUTS
MASTER CASCADE
ENABLE OUTPUT/
---+ MCE/PDEN PERIPHERAL DATA
ENABLE OUTPUT
DEN
DATA ENABLE OUTPUT
E~~~~i AEN---+
MEMOR6u~~~~
APPLICATION
Vee
CEN
f~~~AND ENABLE
--+ INTA
INTERRUPT
ACKNOWlEDGE
COMMAND OUTPUT
_
7
--+ 10RC
--+ AIOWC
--+ 10WC
Bus controller and bus driver for maximum mode operation
~~~!~g OUTPUT
~~Yr~Ng~~~ND
OUTPUT
1/.0 WRITE
COMMAND OUTPUT
of the 8086 and 8088
Outline 20P4
FUNCTION
The MSL8288P is a bus controller and driver for maximum
mode operation of the 8086 and 8088 processors.
The command signals and control signals are decoded by
means of the So ""5; outputs from the CPU and the control
signals for I/O devices and memory are output.
The device can be used in the Multimaster mode in
which several CPUs acting as masters are connected to one
data bus. An input pin for the control signal AEN from an
8289 bus arbiter is provided.
By using the MSL8288P as a bus controller, a highperformance 16-bit microcomputer system can be configured.
BLOCK DIAGRAM
~-
STATUS
DECDDER
MRDC
MEMORY READ COMMAND OUTPUT
MWTC
MEMORY WRITE COMMAND .oUTPUT
AMWC
ADVANCED MEMORY WRITE
COMMAND OUTPUT
CDMMAND
SIGNAL
GENERATDR
I/O READ COMMAND OUTPUT
COMMAND
.oUTPUTS
I/O WRITE COMMAND OUTPUT
ADVANCED I/O WRITE COMMAND OUTPUT
INTA
INTERRUPT ACKNOWLEDGE COMMAND OUTPUT
DEN
DATA ENABLE OUTPUT
DATA TRANSMiT/RECEIVE OUTPUT
CLOCK INPUT
ADDRESS ENABLE INPUT
COMMAND ENABLE INPUT
CDNTRDL
LDGIC
CEN
CONTRDL
SIGNAL
GENERATOR
17 M C E / POE N
5
I/O BUS MODE INPUT
------
--------~
ALE
GND
9-50
• MITSUBISHI
"ELECTRIC
~E~7;~~~:LS~~! i~:~ci g~~:~~/
ADDRESS LATCH ENABLE OUTPUT
CDNTRDL
.oUTPUTS
MITSUBISHI BIPOLAR DIGITAL ICs
MSL8288P
BUS CONTROLLER FOR 8086, 8088, 8089 PROCESSORS
PIN DESCRIPTIONS
Pin
Name
Status input
Input or
output
Input
Functions
These are connected to the CPU status output SO-52'
The M5l8288P uses these signals to generat~ the proper timing command signals and control signals.
All pins are provided with internal pull-up resistors.
CLK
Clock irlput
Input
Used to connect the clock generator M5l8284P clock output ClK.
All outputs of the M5l8288P change in synchronization with the clock input
ALE
Address latch enable
output
Output
Provides the strobe signal output for the address latches
This pin is connected to the STB pin of the M5l8282P or M5l8283P and used to latch the address from the CPU.
When USing any other address latch, the following conditions must be satisfied.
1. The enable input must be active high
2. Data reading is always performed while the enable input is high.
3. The latching operation is performed as the enable input goes from high to low.
~----------+-----------------~-----+-------------------------------------------------------------------------Data enable
DEN
Output
Provides the data enable signal for the local bus or a data transceiver on the system bus.
Operates in active high mode.
DTR
Data transmit/receive
control output
Output
Controls the flow of data between CPU and memory or peripheral I/O devices.
When this pin is high, the CPU can write data to the peripheral devices. When it is low, it can read data from the
peripheral devices.
I t is connected to the transmit input T of the M5 l8286P or M5 l8287P bus transceivers.
~----------+-----------------~-----+------------------------------------------------------------------------
AEN
Address enable input
Input
When the lOB input is low and the AEN input is set to high, all command outputs are put in the high-impedance
state. When the lOB input is high, there is no effect on the 10RC, 10WC, AIOWC, and INTA outputs, the
command output other than these four going into the high-impedanoe state.
None of the command outputs will go low until at least 115ns after AEN transits from high to low.
CEN
Command enable input
Input
When this pin is set to low, all command outputs and DEN are prohibited by the PDEN control output (not highimpedance statel. When set to high, the above outputs are enabled.
1------+--------+-------------------1
lOB
I nput/output bus mode
Input
Input
When this pin is set to high, the M5l8288P functions in the I/O bus mode, and when set to low it functions in
the system bus mode. (The I/O bus mode and system bus mode are described in the functional description)
Advanced I/O write
command output
Output
I/O write command
output
Output
Instructs an I/O device to read the data on the data bus. Active low.
10RC
I/O read command output
Output
Instructs an I/O device to drive its data onto the data bus. Active low
AMWC
Advanced write command
output
Output
The AMWC issues a memory write command earlier in the machine cycle to give memory devices an early
Memory write command
output
Output
Memory read command
output
Output
I nterrupt acknowledge
command output
Output
AIOWC
MWTC
MRDC
INTA
The AI OWC issues an I/O Write Command earlier in the machine cycle to give I/O devices an early indication of a
write instruction. Its timing is the same.as a read command signal. Active low
indication of a write instruction. Its timing is the same as a read command signal. Active low.
Provides a write instruction to memory for the current dat(l on the bus.
Active low.
Provides an output instruction to memory for the present data on the bus.
Active low.
This output informs an inOterrupting device that it has accepted the interrupt, outputting a vector address output
instruction to the data bus. 10RC operates in the same manner for interrupt cycles. Active low
I
• MITSUBISHI
.... ELECTRIC
9--51
EJ
•
MITSUBISHI BIPOLAR DIGITAL ICs
MSL8288P
BUS CONTROLLER FOR 8086, 8088, 8089 PROCESSORS
Pin
I nput or
output
Name
MCE IPDEN
Output
Master cascade
Enable output/
Peripheral data
Functions
This output pin has two functions.
1. When the lOB input is set to iow'
The MCE function is enabled The signal acts as the enable signal which allows a slave PiC (M5L8259AP) to
read the cascade address output to the bus by the master PIC during an interrupt sequence. Actjve high.
2. When the lOB input is set to high:
The PDEN function is enabled. This output provides the enable signal to the data bus transceiver connected to
the I/O interface bus when an instruction occurs (IORC, 10WC, AIOWC, INTA). Operates the same way as
Enable output
DEN with respect to the system bus.
FUNCTIONAL DESCRIPTION
The state of the command outputs and control outputs are
summarizes the states of the outputs SO""S2 and their corre-
determined by the CPU status outputs S~""S;. The table
sponding valid command output names.
STATUS INPUTS AND COMMAND OUTPUTS RELATIONSHIPS
S2
S1
So
8086, 8088 status
Valid command output name
L
L
L
Interrupt acknowledge
INTA
L
L
H
Data read from an I/O port
IORC
L
H
L
Data write to an I/O port
IOWC, AIOWC
L
H
H
Halt
-
H
L
L
Instruction fetch
MRDC
H
L
H
Read data from memory
MRDC
H
H
L
Write data to memory
MWTC, AMWC
H
H
H
Passive state
-
Depending upon whether the M5L8288P is in the I/O
bus mode or system bus mode, the command output
sequence will vary.
2. System bus mode operation
When lOB is set to low, the M5L8288P enters the system
bus mode. In this mode no command is issued until 115 ns
after the AEN Line is activated (LOW). This mode assumes
1. I/O bus mode operation
bus arbitration logic will inform the bus controller (on the
When lOB is high, the M5L8288P function in the I/O bus
AEN line) when the bus is free for use. Both memory and
mode.
I/O commands wait for bus arbitration. This mode is used
In the I/O Bus mode all I/O command lines (lORC, 10WC,
when only one bus exists. Here, both I/O and memory are
AIOWC, I NT A) are always enabled (i.e., not dependent on
shared by more than one processor.
AEN). When an I/O command is initiated by the processor,
the 8288 immediately activates the command lines using
3. AMWC and AIOWC outputs
PDEN and DT/R to control the I/O bus transceiver. The
With respect to the normal write control signals MWTC and
I/O command lines should not be used to control the
10WC, the advanced-write command signals AMWC and
system bus in this configuration because no arbitration is
AIOWC transit low one clock cycle earlier and remain low
present. This mode allows one 8288 Bus Controller to
for two clock cycles.
handle two external busses. No waiting is involved when the
These signals are used with peripheral devices or static,
CPU wants to gain access to the I/O bus. Normal memory
RAM devices which require a long write pulse, so that the
access requires a "Bus Ready" signal (AEN LOW) before it
CPU does not go into an unnecessarily wait cycle.
will proceed. It is advantageous to use ·the lOB mode if I/O
or
peripherals dedicated
to one processor exist in a
multi-processor system.
9 - 52
• MITSUBISHI
.... ELECTRIC
MITSUBISHI BIPOLAR DIGITAL les
MSL8288P
BUS CONTROLLER FOR 8086, 8088, 8089 PROCESSORS
ABSOLUTE MAXIMUM RATINGS
Symbol
ITa=0-75°C, unless otherwise noted)
Parameter
Conditions
Limits
Unit
Vee
Supply voltage
-0.5-+7
V
VI
Input voltage
-0.5- +5.5
V
Vo
Output voltage
- O. 5-Vee
Pd
Power dissipation
Topr
Operating free-air temperature range
Tstg
Storage temperature range
V
1.5
W
0-75
°c
°c
-65- + 150
RECOMMENDED OPERATING CONDITIONS
ITa=0-75°C, unless otherwise noted)
Limits
Symbol
Parameter
Vee
Supply voltage
IOH
High·level output
current
IOl
Low·level output
current
Min
Nom
Max
4.5
5
5.5
Command outputs
-5
Control outputs
-1
Unit
V
mA
Command outputs
32
Control outputs
16
mA
ELECTRICAL CHARACTERISTICS
ITa=0-75°C, unless otherwise noted)
Limits
Symbol
Test conditions
Parameter
VIH
High·level input voltage
Vil
Low·level input voltage
Vie
Input clamp voltage
Min
Unit
Typ
Max
2
V
I
2.4
2.4
0.8
V
-1
V
Command outputs
Vee=4.5V, VI=2V
IOH= -5mA
Control outputs
VI=0.8V
IOH = -lmA
Command outputs
Vee=4.5V, VI=2V
IOl=32mA
0.5
Control outputs
VI=0.8V
IOl=16mA
0.5
VOH
High·level output voltage
V
VOL
Low·level output voltage
IIH
High·level input voltage
Vee=5.5V, VI=5.5V
III
Low·level input voltage
Vee= 5.5V, Vi=0.45V
IOZH
Off·state output current with high·level applied to output
Vec= 5. 5V, Vo= 5. 25V
IOZl
Off-state output current with low·level applied to output
Vee= 5. 5V, Vo=0.4V
ICC
Supply current
Vee= 5.5V
V
• MITSUBISHI
.... ELECTRIC
50
f.1.A
-0.7
mA
100
f.1.A
-100
f.1.A
230
rnA
9-53
II
MITSUBISHI BIPOLAR DIGITAL ICs
MSL8288P
BUS CONTROLLER FOR 8086, 8088, 8089 PROCESSORS
SWITCHING CHARACTERISTICS (Vc C
Symbol
t PLH
t PHL
Typ
Max
TCVNV
5
45
ns
TCVNX
10
45
ns
TCLLH
20
ns
TCLMCH
20
ns
TSVLH
20
ns
TSVMCH
20
ns
From ClK input to PDEN output
Output high-level to low-level propagation time
From ClK input to PDEN output
Output low-level to high-level propagation time
From ClK input to ALE output
Output low-level to high-level propagation time
From ClK input to MCE output
Output low-level to high-level propagation time
From
inputs to ALE output
SO-s,
Output low-level to high-level propagation time
tpLH
Unit
Min
Output high-level to low-level propagation time
t PHL
tpLH
Test conditions
Output low-level to high-level propagation time
from ClK input to DEN output
Output low-level" to high-level propagation time
From ClK input to DEN output
t pLH
limits
Alternate
symbol
Parameter
t PLH
t PLH
5V ±10%, Ta;0-75°C, unless otherwise noted)
From
SO-S; inputs to MCE output
Output high-level to low-level propagation time
tpHL
t pHL
From ClK input to ALE output
Output high-level to low-level propagation time
From ClK input to MRDC, IORC, INTA,
TCHLL
4
15
ns
TCLML
10
35
ns
TCLMH
10
35
ns
50
ns
AMWC, MWTC, AIOWC, and IOWC outputs
Output low-level to high-level propagation time
t pLH
From ClK input to MRDC, IORC, INTA,
AMWC. MWTC, AIOWC, and IOWC outputs
Output high-level to low-level propagation time
tpHL
From elK input to DT/R output
TCHDTL
t PLH
Output low-level to high-level propagation time
From ClK input to DT/R output
TCHDTH
30
ns
t PZH
From AEN input to MRDC, IORC, INTA,
TAELCH
40
ns
TAEHCZ
40
ns
200
IlS
TAEVNV
20
ns
TCEVNV
25
ns
35
ns
(Note 1)
High-level output enable time
AMWC, MWTC, AIOWC, and IOWC outputs
High-level output disable time
From AEN input to MRDC, IORC, INTA,
t PHZ
AMWC, MWTC, AIOWC, and IOWC outputs
t PHL
Output high-level to lOW-level propagatIOn time
From AEN input to MRDC, IORC, INTA,
TAELCV
115
AIiilWC, MWTC. AIOWC, and TOWC outputs
t PLH
t PHL
t pLH
t PHL
Output low-level to high-level and high-level to
low-level propagation time
From AEN input to DEN output
Output low-level to hil1h-level and high-level to
low-level propagation time From CEN input to
DEN and PDEN outputs
Output low-level to high-level and high-level to
low-level propagation time _ _ _ _
From CEN input to MRDC, IQ,Bb_.lNTA,
AMWC, MWTC, AIOWC,and IOWC outputs
t pLH
t pHL
TIMING REQUIREMENTS
10
(VCC 5V ±10%, T a;0-75°C. unless otherwise noted)
Parameter
Symbol
TCELRH
Alternate
symbol
Limits
Unit
Test conditions
Min
Typ
Max
tc
Clock ClK cycle time
TCLCL
100
ns
tW(CLKU
Clock ClK low pulse width
TCLCH
50
ns
tW(CLKH)
Clock ClK high pulse width
TCHCL
30
ns
t SU(SQ-S2)
SO-S2 setup time with respect to
T for the T 1 state
TSVCH
35
ns
t h (Sa
SO-S2 hold time with respect to
T for the T 4 state
TCHSV
10
ns
t SU(So-S2)
So-~ setup time with respect to
T for the T 3 state
TSHCL
35
ns
t h (Sa - 5;,)
SO-S2 hold time with respect to
T for the T 3 state
TCLSH
10
tr
Input risetime
TILIH
20
ns
tf
Input fall time
TIHIL
12
ns
9-54
- 5;)
• MITSUBISHI
"ELECTRIC
ns
MITSUBISHI BIPOLAR DIGITAL ICs
MSL8288P
BUS CONTROLLER FOR 8086, 8088, 8089 PROCESSORS
Note 1. Test Circuit
INPUT
Vee
OUTPUT
r----'
0-+---1
U
I
I
I
I
DEVICE
~~---I;
LOAD CIRCUIT
I
I
UNDER TEST
INote 21
I
I
I
I
I
L ____ J
Note 2.
Load circuit
tp~H, tPHL
tPLZ, tPZL
1.5V
1.5V
~33Q
_J"oQ
2_ 14 V
Command output
load circuit
~527Q
r
~300PF
30 PF
0
Control output
load circuit
~'14Q
1-
tPHZ, tPZH
--
~ 300pF
--
II
80PF
•
MITSUBISHI
..... ELECTRIC
9--55
MITSUBISHI BIPOLAR DIGITAL ICs
MSL8288P
BUS CONTROLLER FOR 8086, 8088, 8089 PROCESSORS
TIMING DIAGRAM
1.
Command output timing
tc
(TCLCL)
STATE.
CLK
/
n
~)
~K~~"Lr
r-~
(TCHSV)H
\
S2,S"So
-
tPLH~
-
tS U (SO-S2)
\
-'~
ADDRESS/DATA
J1c
(TSVCH)
tsu
(TCHCL)~Wf
(TCLSH)
~
DATA
VALID
VALID
(1
J
th(SO-S2)
11
~~:::"
(TCLLH)
ALE
tW(CLK)
(So - 52)
(TSHCL)
( 3)
tpHe
(TCHLL)
~r-~
(TSVLH)
~k--
MRDC, IORC, INTA
AMWC, AIOWC
-
I
r\
-
tPHL
(TCLML)- -~
PLH
I-r-- (TCLMH)
,1{
/
tPHL
(TCLML)
-
-l
I
tPLH, tPHL
~
r--~ (TCVNV)
,~
DEN (FOR READ AND)
\-\
/
INTERRUPT
tPLH,tPHL
\
PDEN (FOR READ AND)
INTERRUPT
tPLH,tPHL
- -l
(TCVNX)
'\
,l
I
(TCVNV)
I-~
DEN (FOR WRITE)
~~
J
tPLH,tPHL
(TCVNX)
\r-.
P DEN (FOR WRITE)
, if-
/
~
tpLH
(TCHDTH)
___-:1+DT/R
}
---J-'
(FOR READAND)
INTERRUPT
t
_~--'"'~
MCE
(TCLMCH)
~c--E'::-.
(TCHDTL)
tpLH
\-
,/(4)
I
-¥~
I
tPHL
(TCHDTHJ
:-.~
tPLH
tPHL_
(TCVNX)
(TSVMCH)
Note 3. The address/data bus signals are shown only for reference.
4. The ALE and MCE leading edge occurs in synchronization 'Nith the falling edge of ClK or So-52. whichever is later.
5
9-56
Unless otherwise noted. the timing of all signals is respect to 1.5V
'. MITSUBISHI
"ELECTRIC
MITSUBISHI BIPOLAR DIGITAL ICs
MSL8288P
BUS CONTROLLER FOR 8086, 8088, 8089 PROCESSORS
2. DEN and PDEN timing
\'1
J~
CEN
*
DEN
tPLH,
tpHL
:*TAEVNVI
~'t-
j\
tPLH,
tPHL
(TCEVNV)
~~
]\
3. AEN timing
tPZH
(TAELCH)
MRDC, IORC, INTA
AMWC, MWTC,
AIOWC, IOWC
CEN
Note 6. CEN must be low or valid prior to T2 to prevent the command from being generated.
APPLICATION EXAMPLE
Vee
0
M5L8284P
CLOCK
GENERATOR
I
CLK
MN/MX
CLK
So~':':""-----~So
READY
S;~-----~Si
RESET
S21---.---~S2
ROY
DEN
M5L8086S
CPU
AMWC
M5L8288P _
DT/R
ALE
BUS
IORC
COMMAND BUS
CTRLR
AIOWC
INTA
1-MEGABYTE ADDRESS BUS
16-BIT DATA BUS
• MITSUBISHI
"ELECTRIC
9-57
SPEECH SYNTHESIS LSls (PARCOR SYSTEM)
MITSUBISHI LSls
M58817AP
SPEECH SYNTHESIZER
DESCRIPTION
The MS8817 AP is a p-channel MOS speech synthesizer
making use of the LPC (PARCOR) method.
device, approximately 100 seconds (maximum) of speech
output can be achieved.
The MS8819S EPROM is also available for use with the
-+
CONTROL SIGNAL
INPUT/OUTPUT
DATA BUS
ADDRESS BUS/
DATA BUS
INPUT/OUTPUT
DATA BUS
ADDRESS BUS
1
INPUT SYNC ISYNC CLOCK OUTPUT
(160kHz)
CLOCK OUTPUT
2¢
(320kHz)
(-10V)
VOO
(-5V/-10V)
MS8817AP.
3:
VOOl
INPUT/OUTPUT
DATA BUS
~
ADDRESS BUS
"»
TEST PIN
Single -1 OV power supply
t11
00
OSCILlATOR OUTPUT lX>UT
OSCILlATOR INPUT
FEATURES
•
To
TEST PIN
By using the device with one type MS8818-XXXP
•
PIN CONFIGURATION (TOP VIEW)
INPUT/OUTPUT
DATA BU~
BUSY SIGNAL
1J
May be used with SV microcomputers by use of a dual
CONTROL SIGNAL
-SV/-l0V supply
•
Selectable characteristic parameter compression density
Low audio quality:
............. 1.96K-bit/s (max)
High audio quality:
............. 3.92K-bit/s (max)
•
Male and female voices or sound effects mixed
•
Usable with up 16 phrase ROMs
•
Direct speaker drive is possible
•
CONTROL SIGNAL
Vss
Outline 28P4
(OV)
NC : NO CONNECTION
FUNCTION
By use of just one masked ROM up to 100 seconds of
speech output is possible
The MS8817AP is an LPC (PARCOR) speech synthesizer
consisting of a microcomputer interface, parameter storage
RAM, decoding ROM, interpolation logic, parameter register, excitation circuit, ROM interface, lattice-type digital
APPLICATIONS
Clocks, educational equipment, toys, electronic cash registers.
filter (pipeline multiplier, adder, stack and registers, etc.),
D-A converter, timing logic circuitry, and clock oscillator.
BLOCK DIAGRAM
CONTROL SIGNAL CNTR 2
INPUT SYNC ISYNC 2
INPUT/OUTPUT
DATA BUS
1~6~ ~3
D02 2
FRAME PERIOD
D03 27
SWITCHING INPUT
F R 14
BUSY SIGNAL BUSY 1~
CLOCK OUTPUT
2¢ 4
(320kHz)
MICRO
COMPUTER
PARAMETER
REGISTER
(110 BITS)
I----~ ~1~~~~tLND
1 AUD1! SPEECH
OUTPUT
DIGITAL FILTER
D-A CONVERTER
13 AUD2
ADDRESS BUS
ROM
INTERFACE
CONTROL SIGNALS
CLOCK OUTPUT
(160kHz)
PARAMETER
RAM
(48 BITS)
DECODING
ROM
(216
X 10 BITS)
CLOCK GENERATOR
L- ______
"1
I
1
I'
lOS
CIRsl'
I
I
~
I
CIR31 :
1
1
:
I
,
~
1
4Tn
,
6Td
L
1
1
I~
I
i>1~1
INSTRUCTION EXEeTiON TIME
!
1
I
I
I 3Td
Fig. 5 Data transmission instruction
ilL
I
I
I
IE
Fig. 4 Bit read instruction
I
5Td
~
,
I
~
I
1
~I1~1
I
I
1
~
10'
,I
I 3Td I
I
1
ICIR7 1
IDS
1
4Tn
5Td
~Ie
ii
1
I
r
I
I
~I
CNTR---1
,
ISYNC
ISYNC-J1-i
los
'L
I
I
I
MITSUBISHI
1"& ELECTRIC
MITSUBISHI LSls
M58817AP
SPEECH SYNTHESIZER
CNTR
~
ISYNC
I
i
l3Tn I
7Tn
1~3=T-n----::-24-:-::T=-n-----.<
r---"i
!
I
r--:~I
~ I CADO i b ~ D
IDS
:
,
lCIRl
TAO
D
@QU
CIRI
D ~ tJ
CIRI
REPEAT OF TAO TIMING
!
::
@QU
CIRI
I
:CIR4
.
TA
INSTRUCTION EXECUTION TIME
Fig. 8 Direct addressing instruction
L~
___~r-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~
CNTR
~
ISYNC
-fl.----fJ- --0~-----/l--------------------------<
~!------~~-~---------------------~
!
~
:
IDS
74Tn
~ff~H~
'\ :CIR6
)1) ;
SAME OPERAnON AS TA FOR
( DIRECT ADDRESSING
!
.
TA
J
I
!
!
I
INSTRUCTION EXECUTION TIME
Fig. 9 Indirect addressing instruction
INSTRUCTION SET
DEFINITION OF SYMBOLS
DO: Interface data bus line
DOj (i = 0""3): i-th bit of DO
a: 18-bit data used for addressing
ak (k = 0""17): k-th bit of a
A: 18-bit phrase ROM address
Ak (k = 0""17): k-th bit of A
S: 4-bit shift buffer
Sj (i = 0""3): i-th bit of S
R (A): Contents of ROM at the address specified at A
Rj (A): (j = 0""7): Value of the i-th bit of R (A)
USING THE INSTRUCTION SET
1. Direct and Indirect Addressing Instruction
(1) Direct addressing
I nstruction code:
D03
D02
DOl
a
a
1
-
a3
a2
al
ao
a
a
1
-
a7
a6
as
a4
a
a
1
-
all
alO
a9
a
a
1
DOo
--
------
as
®
-
Q)
a15
a14
a13
a
a
1
-
-
a17
1
a
a
a12
-
a16
-
E®)
As shown above data is input to the synthesizer from
top to bottom in sequence from the external controller.
• MITSUBISHI
.... ELECTRIC
10-7
MITSUBISHI LSls
M58817AP
SPEECH SYNTHESIZER
Function equations: (A). ~ a
Instruction Description
This instruction directly sets the phrase ROM address.
By using this instruction, the 1st bit, i.e. Ro (A) = Ro (a)
of the 8-bit contents of the phrase ROM at the specified
address is specified. Note that the upper order bits a 14 '" a 17
are specified by the phrase ROM chip select data.
When the contents of the address counter previous to
this instruction are known and it is not necessary to change
the upper order bits a14'" a17, the appropriate setting step
from 1 to 4 may be eliminated.
After outputting of data a16 and a17, this instruction
requires a minimum time of 24T4> during which bit read
instructions must be output as dummies. T 4> is the clock
period.
DQ3
DQ2
DQ1
0
0
1
a3
a2
a1
0
0
1
-
a7
a6
as
a4
0
0
1
-
a11
a10
ag
as
0
0
1
a1S
a14
a13
0
0
1
-
-
1
2. Bit Read Instruction
I nstruction code: 1~_~_3_D_Q_2_D_Q_1_D_Q_0---1
1. Indirect Address
Instruction
Code:
output Ro ((Ae)) '" R7 ( (Ae) ) at the specified address
(Ae) is sent to the address counter Ao"'A7, and the ROM
output Ro ( (Ae)+ 1) '" Rs ((A e )+ 1 ) at the next address
from a(Ae), (Ae) + 1 is sent to the address counter
As'" A 13 . The upper-order 4-bits A 14 '" A17 of (Ae) do not
change, however. The value of the set address data a must
not be the individual phrase ROM last address.
If the contents of the address counter prior to this
instruction are known and there is no necessity to change
higher order address bits, the appropriate step 1 through 4
may be eliminated.
After outputting the data 4 16 and a17, this instruction
requires a minimum of 74Tl/>.
1
a17
0
DQo
Function equations:
ao
-
®
a12
First (50 +- (51 )
(51) +- (52)
(52) +- (53)
(53) +- Rj ((A)) where j = 0"'7 and j
after the instruction.
Next, j +- j + 1 where j +- 0 if j = 8
(A) +- (A)
+1
-
a16
Instruction Description
-
This instruction shifts into the 4-bit shift buffer 5 the
contents of the phrase ROM. In addition, it acts to initialize
the ROM after direct addressing.
By using this instruction, the 1st bit of the 8-bit
contents of ROM specified by the address counter A is sent
to the 4-bit shift buffer 5. Immediately after execution, Ro
( (A)) is sent, and when this instruction is executed
continuously, the address counter is automatically incremented in the sequence Ro ( (A) ), Rl ( (A) ) ... R7 ( (A) ),
Ro ((A) + 1 ), thereby performing a serial conversion on
the ROM data automatically. In addition, the address
counter A is incremented by bits allowing all 16 chips to be
addressed.
As shown above data is input to the synthesizer starting
from the top sequentially.
Function equations:
First, (A) +- a, where (Ae) = a
Next, (Aj) +- Ri (a) == Ri ((AE)) where j = 0"'7
(As + j) +- Ri (a + 1) == Ri ((Ae) + 1) where
j =0"'5
(Ai) = ai where j = 14"'17
Note that the above excludes the case for which
aO"'a13 of (Ae) are all ones.
Instruction Description
This instruction indirectly specifies the phrase ROM address.
By using this instruction, the first bit, i.e. Ro ( (A) ) =
Ro (a), of the 8-bit phrase ROM contents at the specified
address is specified.
First, this instruction sets the address counter A to the
address data a. This address is used as (Ae). Next, the ROM
10-8
= 0 immediately
• MITSUBISHI
.... ELECTRIC
MITSUBISHI LSls
M58817AP
SPEECH SYNTHESIZER
3. Data Transmission Instruction
I nstruction code:
5. Speech Instruction
I nstruction code:
II-DO-o3_ _D_0_2_D_O_1_D_O_0-----1
Function equations:
(DOo ) +(DO, ) +(D02 ) +(D03 ) +-
(So)
(S, )
(S2)
(S3)
Instruction Description
This instruction outputs to the interface data bus line DO
the 4-bit contents of the shift buffer S.
By using this instruction, the 4-bit data contents of the
phrase ROM can be read externally.
D03
D02
DOl
1
0
1
-
Male speaker
0
1
1
-
Female speaker
DOo
Function equations:
(1)
Speech synthesizer +- Rj ((A))
j = 0"'7 and j = 0 directly after an addressing
instruction
(2)
j +- j + 1, however j +- 0 if j = a
(A) +- (A) + 1
(1) and (2) are repeated.
Instruction Description
4. Test Instruction
I nstruction code:
D_~_2_D_~_l_D_~_o---.!1
I_D_0_3_ _
1
Function equations:
(DO o ) +- (SM)
SM=l for speech generation and 0 for non-generation
speech, with DO,"'D03 non-defined.
Instruction Description
This instruction is used to test whether speech generation is
being performed and output the result at DOo.
Use of this instruction allows the speech mode (SM)
status to be output as a DC level at the busy pin as well. SM
and BUSY are of the same polarity, 1 for periods of speech
generation and 0 for non-generation periods.
These instructions are used to begin and execute speech
generation by the speech generating equipment.
Using these instructions, speech characteristic parameters stored in the phrase ROM are sent to the synthesizer
continuously at a rate of one frame every 25ms, the
synthesizer processing them with a cycle time of 125J,Ls.
The results of this process are D/A converted every 125J,Ls
to create the AUDl and AUD2 speech outputs. At each of
AUDl and AUD2 pins, an analog speech signal is output
corresponding to the appropriate sign codes, one being
positive and the other negative.
Use of these instructions automatically increments the
la-bit phrase ROM address counter A, and performs a
serialization of ROM data.
As the last voice parameter frame in the phrase ROM, an
end code is used so that the synthesizer, sending this end
code is reset, ending the speech synthesis process cycle and
setting the speech mode SM to O.
~
Thus, with the exception of phrase ROM memory
capacity, speech of any arbitrary length may be generated.
• MITSUBISHI
.... ELECTRIC
:f9!III
10-9
MITSUBISHI LSls
M58817AP
SPEECH SYNTHESIZER
6. Stop I ... struction
I nstruction code:
DQ3
DQ2
DQl
Data Transfer Using the Bit Read Instruction and
Indirect Addressing Instruction
DQo
o
PROGRAM COUNTER
INSTRUCTION FUNCTION
This instruction stops the speech output of the synthesizer.
Instruction Description
This instruction stops the speech generated by the synthesizer.
By using this instruction, speech generation is halted,
and the speech mode 8M is reset to O.
The phrase ROM program counter is not modified.
Upon power up, it is always required to generate a stop
instruction.
SHIFT REGISTER
Note
----
Bit read instruction
} Indirect addressing instruction
Example
This example generates female speech by sending the ROM
program counter to the first address 0013F 16 •
If a bit read instruction is output by the synthesizer, the
upper order bit of the address specified by the program
counter is transferred to the upper order bit (DQ3) of the
synthesizer register. By repetitively sending this instruction,
the previously sent bits are shifted towards the lower order
bits in the register. Thus, to observe data stored in ROM
using the bit read instruction, the data must be stored after
doing bit conversion in groups of 4 bits.
DQo
DQ3
DQ2
0
0
1
0
1
1
1
1
0
0
1
0
0
0
1
1
0
0
1
0
0
0
0
1
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
Bit read instruction
0
Female speaker instruction
0
1
DQl
1
(1) Using the bit read instruction
Addressing instruction
F
Addressing instruction
Addressing instruction
(2) Using the indirect addressing instruction
As can be seen in the Figure, the upper order and lower
order bits for the contents of ROM and those of the
program counter are reversed, requiring care when performing ROM storage operations.
Addressing instruction
Addressing instruction
Data is transferred to the synthesizer (M58817 AP) from
the controller as shown above. Refer to the Timing Diagram
for input timing.
10-10
• MITSUBISHI
.... ELECTRIC
MITSUBISHI LSls
M58817AP
SPEECH SYNTHESIZER
ABSOLUTE MAXIMUM RATINGS
Symbol
Supply voltage
VI
I nput voltage
Pd
Power dissipation
Topr
Tstg
Limits
Unit
0.3- -15
V
Conditions
Parameter
VOO
With respect to Vss
0.3--15
V
700
mW
Operating temperature
-10-70
"C
Storage temperature
-40-125
"C
RECOMMENDED OPERATING CONDITIONS
(Ta = -10-70°C, unless otherwise noted)
Limits
Symbol
Parameter
Unit
Min
Nom
-10
Max
VOO
Supply voltage
-11
VOOI
Supply voltage (Note 1)
-11
VSS
Supply voltage
VIH
High-level input voltage
-1
0
V
VIH(q,)
High·level clock input voltage
-1
0
V
VIL
Low-level input voltage
Voo
-4
VIL(q,)
Low·level clock input voltage
VOO
Voo+2
f( q,)
Oscillation frequency
620
660
-9
V
-4,75
V
0
V
V
V
kHz
Note 1. V 0 0 1 is the controller and interface power supply. For single power supply operation V 001 = VOO.
ELECTRICAL CHARACTERISTICS
(Ta = -10-70°C, Voo
= -10±1V,f(},
busy signal, input/output data bus (VOOI·related outputs)
VOH2
VOLl
VOL2
High-level output voltage for clock output (),
IOH=-50,uA
VOOI = -5±O.25V,
IOH=-50,uA
I OH= -50,uA
control signals, address bus (Voo·related outputs)
V
-1
V
-0.8
V
-4.5
V
VOOl+0.6
V
-5
V
-30
mA
-1
mA
30
mA
10
pF
VI=O- VOO
±1
,uA
VI=O-VOO
-50
,uA
VOO=VOOI,
VOOI= -5±0.25V,1 OL= 50,uA
I OL= 50,uA
control signals, address bus (Voo·related outputs)
Max
-1
I OL= 50,uA
Low·level output voltage for clock output (2),
busy signal, input/output data bus (V o o 1·related outputs)
Low·level output voltage for clock output (),
Typ
un·loaded output
100
Supply current
VOo= VOOI,
I DOl
Supply current
Un·loaded output
IDA
Maximum O/A output current
RL= 100Q
VOO=VOOI=VSS,
Ci
Input capacitance
7
f= 1MHz,
Input current, with the exception of the frame period
250mVrms
switching input
II
Input current for the frame period switching input
(built·in pull down resistor)
• MITSUBISHI
.... ELECTRIC
10-11
MITSUBISHI LSls
M58817AP
SPEECH SYNTHESIZER
APPLICATION
EXAMPLES
(1) Use with M58818-XXXP
Vss
VOD
,1
~+
VOO
AUDI
12
Dull~
Ceramic oscillation
element
15
Vss
XOUT
13
AUD2
~~ VOOI
f---'
6 8 10
2 3 4 5
6 810
2
3 4 5
C
3
¢ 16
C0
18
Cl
Q)
e.....
CNTA
0
25
23
20
27
000
001
DQ2
Do
01
02
03
H~
0.1.u F
>
III
FA
BUSY .c
u
8III
ISYNC ~
C
#1 M58818-XXXP
#16 M58818-XXXP
---phrase ROM
phrase ROM
CIN
Q)
.....
2¢
28
2
0
At
XIN
12
HI-:-
O.l.uF
tTl00PF
390Q
100pF
8
,~
.c
4
14
19
...
.!!
...
Q)
7~~
,I
12
VSS 11
1
VOO
co
co
Ln
003
24
Ao 22
A121
A2
26
A3/0
(2) Use with an EPROM
VOOI
Vss
Voo
I
15.6
151
....---
I
~ FA
Co c1§---+J1
Cl e1L~
Ao ~....A
Al ~
A2 ~
~ ISYNC
~
e..... ~
~
.!!
C
0
~
0
000
DOl
002
003
f--~ BUSY
~ 2¢
lO~a
XOUT
~
100pF
8
Ao
Al
A2
Q)
N
«,!
a; .....~
co ...
"
Ln.c
390Q
Co
Cl
A~O ~ A3/0
0..';;;
L...--
f---l~
.I
71
17 3
¢ L r---lQ¢
~ CNTA
...
100kQ
~~
8.
XIN
III
AUDI AUD2
12
13
t±
---
C!J
VOO~
SL
~
't:
~
2
ADo 1
40
ADI
39
I
I
I
I
I
31
AD9
30
ADlO
ADll ~~~
AD12 ~
,- AD13 ~
-~~
ex:
•
....
Hl~ Poe ~
O.l.uF
...J
~
0..
W
CI)
m
"'"
co
co
Ln
~
----
CS7
1M5~2~16K f--YOee
Do 18
01 19
02 20
21
03
22
04
23
05
24
06
07 26
100kQ
T.
.• MITSUBISHI
.... ELECTRIC
M5L2716K
#7
I
Q
10-12
-----
(J)
1
F
Vss
MITSUBISHI LSls
MS8818-XXXP
128K-BIT PHRASE ROM
DESCRIPTION
The M58818-XXXP is a p-channel MOS phrase ROM having
a capacity of 16K bytes (131072 bits), intended for use in
storage of speech parameters and other data. The device
includes also an 18-bit address counter/register, an 8-bit
output sense amplifier/buffer, address control circuitry, and
read control circu itry.
Used in conjunction with the M58817 AP speech synthesizer, up to 100 seconds of speech output can be obtained.
PIN CONFIGURATION (TOP VIEW)
Voo
NC
ADDRESS BUS
{~~:
ADDR~;iAB~~~
A3/Q"'"
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
(-lOV)
A2_
CLOCK INPUT
-
NC
CONTROL SIGNAL
Co -
NC_
FEATURES
• Single -1 OV power supply
• Stores parameters for up to 100 seconds of speech
output
• Large memory capacity (128K bits)
• Built-in 18-bit address counter/register
CONTROL SIGNAL
POWER-ON CLEAR
(DV)
NC
12
Outline 24P1
NC : NO CONNECTION
APPLICATIONS
Clocks, educational equipment, toys, electronic cash registers.
FUNCTION
The M58818-XXXP is a 16K x 8-bit masked ROM
consisting of a 14-bit address counter, address latch, chip
select latch, data register, and control logic circuitry.
Addressing is done by means of pins Ao through A3 in
five steps.
BLOCK DIAGRAM
ADDRESS BUS
Ao
2-
A1
3
l
Ao
@-
I
I
14-BIT
ADDRESS
COUNTER
A3/Q
ADDRESS LATCH
I
I
A2 4
ADDR~!~AB~G~
-
-
r----
DECODER
~
ROM
16KX 8BITS
A13
5
R+---1 RO
DATA LATCH
r---i
I
I
BUFFER
I
DATA REGISTER
I
I CHIP SELECT LATCH
I
~
DECODER
I
CONTROL LOGIC
I
(OV)(-lOV POWER-ON CLEAR
• MITSUBISHI
"ELECTRIC
J
CONTROL SIGNALS
CG
CLOCK INPUT
10-13
MITSUBISHI LSls
M58818-XXXP
128K·BIT PHRASE ROM
BASIC FUNCTIONAL BLOCKS
Function
Operational description
Address counter
For continuous addressing of ROM data for output, this 14-bit pure binary address counter is automatically incremented by1
Data register
This a-bit register is used for temporary storage of ROM data
Control logic
Provides internal control by means of the control signals Co and C,
Data memory
16K x a bit masked ROM
PIN DESCRIPTION
Pin
Ao-A2
Name
Address bus
Input or
output
Input
Function
Input pins for the external input of address into the address counter and chip select latch. This data must be input in five
steps.
In the address and chip select data input mode this pin acts as an input pin to accept address and data. This data must be
A3/Q
Address bus/data bus
Clock input
Input
Control signals
Input
Co
C1
Poe
10-14
Input/
output
Power-on clear
Input
input in five steps. In the data output mode this pin acts as an output pin, outputting ROM data 1 bit at a time in serial
fashion. However, for address overflow and when the chip is not selected, this output pin is floating.
Clock input pin
Determine internal operation status.
Input pins for control signals.
Upon power-on, an internal power-on clear circuit automatically clears the internal status. When this pin is set to high,
A3/Q output is prohibited and the internal states are cleared.
• MITSUBISHI
.... ELECTRIC
MITSUBISHI LSls
M58818-XXXP
128K-BIT PHRASE ROM
FUNCTIONAL DESCRIPTION
The M58818-XXXP is controlled by the following four instructions.
Instruction code
Effect
Instruction
Co
C1
Address instruction
Data is loaded into the internal address counter and chip select latch of the M58818-XXXP
0
1
Read instruction
Serially converted data from the ROM is output 1 bit at a time. This may also be used as an addressing instruction
capable of directly addressing ROM.
1
0
Indirect addressing instruction
c----------
Nap instruction
Indirectly sets the address of ROM
1
1
No operation
0
0
These instructions are described below.
1. Direct addressing
The read instruction acts as a direct addressing instruction, and 24 clock cycles after the input of the read
instruction ROM data is available at the A3/Q pin. In
addition, by inputting a read instruction ROM data can be
serially output 1 bit at a time.
The address counter is automatically incremented by 1
every 8 read instructions.
The timing is shown in Fig. 1. First, by using the addressing
instruction, Ao, A l , A 2 , and A3/Q inputs are used to
read-in in 4-bit parallel format the starting address and chip
select data. Then, five addressing instructions are used to
completely set the contents of the address counter and chip
select latch.
Next, if a read instruction is input, ROM data is read
from the address specified by the sequence above.
-Qdl-fUlJl
T1 : MINIMUM T",
T¢=6.25,us
I
Ao
A2
~ ROM DATA OUTPUT
,
I
I
I
I
I
,.
~
24T¢
I
Co
-~~--~~--~~~
I
:~~-----(J~----~
I
I
: T1
I
I
I
I
I
!
T1
I
I
~---<.~
ADDRESSING INSTRUCTION
READ INSTRUCTION
READ INSTRUCTION
START ADDRESSING PERIOD
Fig. 1
Direct addressing timing
• MITSUBISHI
"ELECTRIC
10-15
MITSUBISHI LSI.
M58818·XXXP
128K·BIT PHRASE ROM
2. Indirect addressing
The timing is shown in Fig. 2. As with direct addressing, an
indirect addressing instruction is input after setting of the
address.
By using an indirect addressing instruction, ROM data at
the address in the address counter is output and shifted into
the address counter.
In addition, when two words of ROM data are shifted
into the address counter, 74 clock cycles after the input of
an indirect addressing instruction the ROM data at the set
address is available as an output at the A3 /0 pin.
By inputting a read instruction, ROM data can be read 1
bit at a time in serial fashion.
The relationship between the two words of ROM data
and the address shifted into the address counter is as
follows.
If the address counter address is set to{0000016)when" an
indirect addressing instruction is input, the ROM data at
that address (Do 0 1 O2 0 3 0 4 05 0 6 0 7 h and the ROM
data at the address incremented 1 (00001 16 ) {D'o 0'1 0'2
0' 3 0'4 0'5 0'6 0'7 h are output and shifted into the
address counter, the overall address being set to {D's 0'4
0'30'20'10'00706050403 O2 0 1 Doh·
T, : MINIMUM T.p
Ao
A2
I----- ROM DATA OUTPUT
A3/Q
DO~
74T¢
i--_--J~---III'-----J
'----:
I
I
I
I
I
I
I
I
I
I
I
Co
c,
I
I
I
:
I
I
, I
I
{uuilln£t:1
START ADDRESSING PERIOD
Fig.2
I
I
INDIRECT ADDRESSING INSTRUCTION
Indirect addressing timing
3. Relationship of phrase ROM contents and
address setting
Up to a maximum of 16 M58818-XXXP phrase ROMs may
be connected to a single M58817 AP synthesizer. Therefore,
since the capacity of a single MS8818-XXXP is 16K bytes
(131072 bits), it is necessary to be able to address 256K
bytes. That is, an 18-bit address ai (i=O-17) is required the
relationship between ai and the ROM chip being as follows.
a17 a'6 a,s a'4 a13 a'2 a" a10 ag as a7 a6 as a4 a3 a2 a, ao
IE
"1<
:>!
Chip select
10-16
101----:-_-------~-RE-AD-INS-T-RU-C-TIO-N--
Addressing bits for 1 chip
". MITSUBISHI
.... ELECTRIC
MITSUBISHI LSls
MS8818-XXXP
128K-BIT PHRASE ROM
ABSOLUTE MAXIMUM RATINGS
Symbol
Conditions
Parameter
Limits
Unit
0.3--15
V
VOO
Supply voltage
VI
Input voltage
Pd
Power dissipation
Topr
Operating temperature
-10--70
·C
Tstg
Storage temperature
-40- 125
·C
With respect to Vss
Ta = 25·C
RECOMMENDED OPERATI NG CONDITIONS
0.3--15
V
130
mW
(Ta=-10-70°C, unless otherwise noted)
Limits
Parameter
Symbol
Min
Nom
Max
-11
-10
-9
VOD
Supply voltage
VSS
Supply voltage
VIH
High·level input voltage
-1.5
VIL
Low-level input voltage
VOO
fC¢)
External clock frequency
155
Cp
Capacitance connected to Po c pin
0
ELECTRICAL CHARACTE RISTICS
Unit
V
V
0
-4.5
160
165
0.1
V
V
kHz
,uF
(J a =-10-70°C, Voo=-10V±lV, Vss=ov, f(lj»= 160±5kHz, unless otherwise noted)
Limits
Symbol
Parameter
Test conditions
Unit
Min
Typ
Max
VOH
High-level output voltage
IOH=-0.5rnA
VOL
Low-level output voltage
IOL=0.5rnA
100
Supply current
Un-loaded output
-10
rnA
II
Input current for all pins except power-on clear
VI =O-VOO
±1
,uA
II
Input current for power-on clear input
VI =O-Voo
-50
,uA
Ci
I nput capacitance
10
pF
-0.8
V
-4.5
V
VOO=Vss,
7
f= 1MHz,
250rnVrrns
• MITSUBISHI
"ELECTRIC
10-17
MITSUBISHI LSI.
M58818-XXXP
128K-BIT PHRASE ROM
SWI TCH I NG CHARACTE R 1ST ICS
(Ta =-10-70°C, VDD =-10±1 v, "(II) = 160±5kHz, unless otherwise noted)
limits
Parameter
Symbol
Test conditions
Min
td(¢-Q)
Data output delay time
CL= 100pF
TIMING DIAGRAM
A3/Q
•
10-18
MITSUBISHI
JihtA ELECTRIC
I
I
Typ
Unit
I
I
Max
3
115
MITSUBISHI LSls
M588195
EPROM INTERFACE
DESCRIPTION
The M58819S is a p-channel MOS EPROM interface LSI
device capable of addressing 16K bytes
of
EPROM devices.
The device is housed in a 40-pin ceramic DI L package.
Speech output is possible by using the M58819S in con-·
PIN CONFIGURATION (TOP VIEW)
PROM
ADDRESS B'US
( - 5 v) V001
PROM.
ADDRESS BUS
(-lOV) VOO
junction with the M58817AP and EPROMs.
ADDRESS BUS
NC
FEATURES
•
NC
Single -1 OV power supply
•
Extendable to control up to 16K bytes of EPROM
•
Built-in 14-bit address counter
PROM
ADDRESS BUS
APPLICATION
Small-scale speech output devices.
FUNCTION
PROM
DATA BUS
The M58819S is an interface LSI which includes a 14-bit
NC
address counter, chip select latch, control logic circuitry,
(OV) Vss
and a data register.
NC
It is usable in conjunction with
PROM
DATA BUS
PROM DATA BUS
EPROMs and the M58817 AP speech synthesizer.
NC . NO CONNECTION
Outline 40S1
BLOCK DIAGRAM
~----~r---~~1 :00
AD
ADDRESS BUS
A1
{
14-BIT
ADDRESS
COUNTER
A2
ADDRESS BUS/
DATA BUS A3/Q
ADDRESS
BUFFER
I
~_ _ _ _---i_ _ _~-.{
I
I
~
PROM ADDRESS BUS
.
J
27 AD
13
V001( -5V)
Voo( -lOV)
DATA REGISTER
Vss(OV)
PROM
EXPANSION INPUT
Poc
POWER-ON CLEAR
Co
~
CONTROL INPUTS
0,7 - - -
-~o
PROM DATA BUS
• MITSUBISHI
"ELECTRIC
CLOCK INPUT
10-19
MITSUBISHI LSls
M588195
EPROM INTERFACE
BASIC FUNCTIONAL BLOCKS
Operational description
Function
Address counter
This counter is uS,ed to specify the address for external EPROMs. When this ,14-bit binary counter is used to output continuous
addresses for data output; 'it is automatically incremented by one.
Data register
This B-bit register is used for temporary storage of EPROM data
Control logic
Provides internal control by means of the control signals Co and C I
--
PIN DESCRIPTION
Pin
Name
ADO-AD13 PROM address bus
Input or
output
Function
Output pin which sends the 14-bit address to the EPROM devices
Output
Ao-A2
Address bus
Input
A3/Q
Address bUS!
data bus
Input!
output
Input pins for the external input of address into the address counter and data into the chip select latch. This data must
be input in five steps.
In the address and chip select data input mode this pin acts as an input pin to accept address and data. This data must be
input in five steps. In the data output mode this pin acts as an output pin. outputting EPROM data 1 bit at a time in serial
fashion. However. for address overflow and when the chip is not selected. this output pin is floating.
,--
- -
Clock input
Input
Clock input pin
Control signals
Input
Input pins for the control signals which determine the internal operating states
Poe
Power·on clear
Input
00-07
PROM data bus
Input
B-bit parallel input for EPROM data
Input
Normally the SL pin is set to low. enabling addressing of 16K bytes of EPROM. For addressing of 32K bytes of EPROM
with two M5B819S devices. one of the SL pins is set to high. The chip select data is used to switch between the two
devices.
¢
Co
C1
SL
10-20
PROM expansion
input
Upon power-on. an internal power-on clear circuit automatically clears the internal status. When this pin is set to high.
A3!Q output is prohibi.ted and the internal states are cleared.
• MITSUBISHI
"'ELECTRIC
_.
-------,------------~
MITSUBISHI LSls
M588195
EPROM INTERFACE
FUNCTIONAL DESCRIPTION
The M58819S is controlled by the following four instructions.
Instruction code
Effect
Instruction
Data is loaded into the internal address counter and chip select latch of the M58819S.
Addressing instruction
Serially converted data from the EPROM is output 1 bit at a time. This may also be used as an addressing instruction
Read instruction
NOP instruction
C1
0
1
1
0
Indirectly sets the address of EPROM
1
1
No operation
0
0
capable of directly addressing EPROM'
Indirect addressing instruction
Co
These instructions are described below.
1. Direct addressing
The timing is shown in Fig. 1. First, by using the addressing
instruction, Ao, AI, and A3/Q inputs are used to read-in in
from the address specified by the sequence above.
4-bit parallel format the starting address and chip select
tion, and 24 clock cycles after the input of the read
The read instruction acts as a direct addressing instruc-
data. Then, five addressing instructions are used to com-
instruction EPROM data is available at the A3/Q pin. In
pletely set the contents of the address counter and chip
addition, by inputting a read instruction EPROM data can
select latch.
be serially output 1 bit at a time. The address counter is
Next, if a read instruction is input, EPROM data is read
automatically incremented by 1 every 8 read instructions.
T¢= 6.251'S
¢
~
T1: MINIMUM T '"
.JlIl.flMfL
Ao
A1
A2
A/Q
Co
I
I
I
~
I
I
I
I
I
~'
I
I
I
,
a2 a& a,a a'41
~'I
I
I
I
I
~ EPROM DATA OUTPUT
I
~II
a3 a7 a,l a'51 I
I
I
:
I
I
I
I
I
,
I
I
I
:
I
I
I
I
I
I
Do
I
24T¢
L...,---+------+------IEI
~
INDIRECT ADDRESSING INSTRUCTION
SL
ADoAD13
I."
START ADDRESSING PERIOD
I
I
~
I.
PROM ADDRESS OUTPUT PERIOD
T2=14T¢
Fig. 1
Direct addressing timing
•
MITSUBISHI
;"ELECTRIC
10-21
MITSUBISHI LSls
M588195
EPROM INTERFACE
2. Indirect addressing
The timing is shown in Fig. 2. As with direct addressing, an
indirect addressing instruction is input after setting of the
address.
By using an indirect addressing instruction, EPROM data
at the address in the address counter is output and shifted
into the address counter.
In addition, when two words of ROM data are shifted
into the address counter, 74 clock cycles after the input of
an indirect addressing instruction the EPROM data at the
set address is available as an output at the A3/0 pin. By
inputting a read instruction, ROM data can be read 1 bit at
a time in serial fashion.
The relationship between the two words of ROM data
and the address shifted into the address counter is as
follows.
If the address counter address is set to 00000 16 when an
indirect addressing instruction is input, the EPROM data at
that address (Do 0 1 O2 0 3 0 4 Os 0 6 0 7 h and the
EPROM data at the address incremented 1 (00001h6 (0'0
0'10'20'30'4 O's 0'6 0'7h are output and shifted into the
address counter, the overall address being set to(Os 0 40 3
0i 0i 0 0 0 7 0 6 Ds 0 4 0 3 O2 0 1 Ooh.
Tl: MINIMUM T¢
Ao
L--- EPROM
A2
I
DATA OUTPUT
~
I
I
I
;----;:AD INSTRUCTION
START ADDRESSING PERIOD INDIRECT ADDRESSING INSTRUCTION
SL
C==:~ c=j1;:=J ~f=-J
ADo
AD13
L-J~
,I
PROM ADDRESS OUTPUT PERIOD
T2=14T¢
Fig.2
Indirect addressing timing
3. Interface addressing
The M58819S is capable of addressing up to a maximum of
16K bytes of EPROM. The chip select data is (OOOOh·
Therefore, it is necessary to be able to specify an 18-bit
address ai 0=0""17), the relationship between ai and the
PROM address bus being as follows.
a17 a 16 alS a14 a13 a12 all alO a9 as a7 a6 as a4 a3 a2 a1 ao
o
I
0
I_
0
Chip select
10-22
I
I
I
I
I
I
I
I
I
I
I
I
I
0 AD13AD12AD11ADlOAD9ADsAD7AD6ADsAD4AD3AD2AD1ADo
liE
Addressing bits for the EPROM
·1
•.. MITSUBISHI
;"ELECTRIC
L
MITSUBISHI LSls
MS8819S
EPROM INTERFACE
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
VDD
Supply voltage
VI
Input voltage
Pd
Power dissipation
Topr
Operating temperature
Tstg
Storage temperature
Conditions
Limits
Unit
0.3--15
V
With respect to VSS
0.3--15
Ta =25'C
-
V
180
mW
10-70
°C
°C
-40- 125
RECOMMENDED OPERATING CONDITIONS
(T a=-10-70°C, unless otherwise noted)
Limits
Symbol
Parameter
Unit
Min
VOO
Supply voltage
-11
VDOl
Supply voltage
-5.25
VSS
Supply voltage
Max
Nom
- 9
-5
-4.75
0
V
V
V
VIH
High-level input voltage
-1
0
V
VIL
Low-level input voltage for 0 0 -0 7 inputs
VOOl
-4.3
V
VIL
Low-level input voltage forA o-A 3 ,I/>, SL,C o, and C, inputs
VDD
-4.5
V
165
kHz
f (q,)
External clock frequency
155
ElECTR ICAl CHARACTE R ISTICS
160
(Ta=-10-70°C, V DO =-10±1V, V D0 1=-5±0.25V, Vss=OV, f(t/l)=160±5kHz, unless otherwise noted)
Limits
Symbol
Parameter
Test conditions
Unit
Min
VOHl
High-level output voltage for Q output
VOH2
High-level output voltage for ADo-AD,
VOH3
High-level output voltage for AD, ,-AD, 3 outputs
VOLl
Low-level output voltage for Q output
VOL2
Low-level output voltage for ADo-AD,
VOL3
Low-level output voltage for ADll -AD'3 outputs
I OH= 0.5mA
0
output
Typ
Max
-0.8
V
-1
V
IOL= 0.5mA
0
V
-1
outputs
IOL=0.5mA
-4.5
V
IOL=0.1mA
V00 1 + 0.6
V
IOL= 0.4mA
Voo1 +O.6
V
-10
mA
-
mA
I DO
Supply current
IODl
Supply current
II
Input current for all inputs other than Poe
II
Input current for Poe input
C,
Input capacitance
VOO=V001= VSS. f = 1MHz. 250mVrms
Un-loaded output
•
1
VI =O-VOO
± 1
pA
VI=O-VOD
-
50
pA
10
pF
MITSUBISHI
. . . . ~L~~TRI~
7
MITSUBISHI LSls
M588195
EPROM INTERFACE
SWITCHING CHARACTER ISTICS
(T a ;-10-70°C, Vo o ;-10±1V, VLD ;-5±0.25V, f;160±5kHz, unless otherwise noted)
Limits
Symbol
Parameter
Unit
Test conditions
Min
Typ
Max
td(ccessive current detector signal input
Compressor 6-minute stop function
(1)
THE
THE~
DEF
DEF ___________________________
LOCK
0- S W
RL 1
When LOCK input goes low within 5 to 10 seconds frorn startup
6 MINUTES
-----,1--____ 1 -""'""'-r---I
I...
'-~--·~r_,
---1
-4
RL2
:
,---...
LOCK
--......J
k-~ WITHIN 15s
D-SW
5-10s
f.c-0.5s
~
I
:'
--.J
I
RL 1
RL2
RL3 _ _ _ _ _ _ _ _ _ _ _ ___
RL3 - - - - - - - - - - - - - - - - -
SINGLE-PHASE OPERATION
OPERATION STOP
SINGLE-PHASE OPERATION
--~'I-~
I
TWO-PHASE OPERATION
OPERATION STOPPED
:-1-;
SINGLE-PHASE OPERATION OPERATION STOPPED
,.1"
-_1-0:---
TWO PHASE OPERATION
Compressor startup
(RESTART AFTER 6 MINUTESI
(2) When LOCK input goes low after marc th~n 10 seconds after startup
0-1s 0-05s
rt'"i
,
'
I
THE~
--~i~~--------------I
DEF
L-.J
LOCK
I
D-SW
RL 1
~
THE
I
DEF
LOCK
:'
D-SW - - --- WITHIN
- - 5s.,.j
----I< - lOs-MIN
- +
-f-ii-:. .,------_-.,.,.;. ,--""'I-c--'
-S-IN-GL-E-PHASE OPERATION
--.Jr--------------------------
RL1
RL2~
RL2
RL 3 _ _ _ _ _ _ _ _ _ ___
OPERATION STOP
RL3
SINGLE-PHASE OPERATION
: :I
,I
I SINGLE-PHASE OPERATION
TWO-PHASE OPERATION
OPERATION STOPPED
TWO-PHASE OPERATION
.k
*
SINGLE-PHASE OPERATION
Door alarm control
SINGLE-PHASE OPERATION
,1
TWO-PHASE OPERATION
>Ie
)1
(3) When LOCK input is low for marc than 5 seconds afWr startup (or
when lock input goes low 10 seconds after startup)
OF(orDR)
--.JI
DR (orDF)
I
THE ~
0.15s
~
BZ ___....!___
15_S_ _
-'~
DEF
LOCK
D-SW
------,
~~-
RL1
RL2
OF (or DR)
--.J
DR (or OF)
----i===~--~4~~~_*_ L--
I
5s
-~---4
----.J
RL3
BZ __________1_5_s____~L____~
OPERATION STOP
1
TWO PHASE OPERATION
I
OPERATION STOP
APPLICATION EXAMPLE
DOOR SWITCHES
r-----~
r__---
POWER SUPPLY (+)
()---'\M--r----.-~
TEMPERATURE CONTROL SIGNAL
DEFROST BIMETAL
EXCE:SSIVE CURRENT SIGNAL
16
RLl
8,
L_ COMPRESSOR MAIN WINDING CONTROL
I
50/60 Hz
~
1.------0>,
11 -18
lie
TWO-PHASE OPERATION nyO-PHASE OPERATION
COMPRESSOR AUXILIARY WINDING CONTROL
DEFROST HEATER CONTROL
• MITSUBISHI
"ELECTRIC
MITSUBISHI LSls
MS0401P, MS0402P
MS0403P, MS0404P, MS040SP
CMOS ANALOG CLOCK CIRCUITS
DESCRIPTION
The
M50401 P,
PIN CONFIGURATION (TOP VIEW)
M50402P,
M50403P,
M50404P
and
M50405P comprise a family of CMOS circuits designed for
use with quartz crystal oscillator elements in clock applications.
TYPE
M50401P
M50402P
M50403P
M50404P
M50405P
PROCESS
OUARTZ CRYSTAL
MOTOR
SILICON GATE
CMOS
4. 1943MHz
31 ms
SILICON GATE
CMOS
32.768kHz
31 ms
SILICON GATE
CMOS
32.768kHz
16ms
(1. 5V)
ALARM INPUT
ALARM SOUND
2048 x 2 x 1Hz
(OV)
ALARM OUTPUT
2048 X 8 x 1Hz
6
MOTOR OUTPUT
2048x2x 1Hz
2048X8X 1Hz
Xo UT CRYSTAL OSCILLATOR
OUTPUT
CRYSTAL OSCILLATOR
INPUT
MOTOR OUTPUT
2048 x16X 1Hz
FEATURES
•
Low power consumption
M50401 P, M50402P
M50403P, M50404P, M50405P . . . ..
•
Low operating voltage
APPLICATIONS
25J1A (typ)
Outline 8P4
2J1A (typ)
1.1V(min)
FUNCTION
•
Alarm clocks
•
Precision clocks for electronic equipment
•
Frequency dividers for electronic equipment
The
M50401 P,
M50402P,
M50403P,
M50404P
and
M50405P are CMOS ICs designed for use in crystalcontrolled clocks. They consist of a crystal controlled
oscillator, dividers, alarm bell drive output buffer circuit,
and motor drive output buffer circuits. They are designed
for use with standard 4,1943MHz or 32.768kHz clock
reference crystals, and perform the required divisions to
drive a stepping motor.
BLOCK DIAGRAM
Ell
OUTPUT BUFFER CIRCUIT
CRYSTAL OSCILLATOR INPUT
MOTOR DRIVE OUTPUTS
CRYSTAL OSCILLATOR OUTPUT XOUT
L-------+(4
6 )----------'
02
ALARM OUTPUT
2 ALO ALARM OUTPUT
BUFFFR CIRCUIT
I
~VDD
(1.5V)
I
j
• MITSUBISHI
.... ELECTRIC
11-19
MITSUBISHI LSls
MS0401P, MS0402P
MS0403P, MS0404P, MS040SP
CMOS ANALOG CLOCK CIRCUITS
ALARM OUTPUT BUFFER CIRCUIT
FUNCTIONAL DESCRIPTION
OSCILLATOR CIRCUIT
The alarm output buffer circuit generates a drive signal for
A crystal oscillator element is connected between X 1N
a piezoelectric element or magnetic speaker. The alarm
(oscillator input) and X OUT (oscillator output) pins and
output signals are 50% duty cycle 2048Hz, 2Hz, and 1Hz
signals for the M50401 P and M50403P, and 50% duty cycle
capacitors are connected to ground from each of these pins.
2048Hz, 8Hz, and 1Hz signals for the M50402P and
OUTPUT BUFFER CIRCUIT
The output buffer circuit is an amplifier capable of
M50404P. And 50% duty cycle 2048Hz, 16Hz and 1 Hz
signals for the M50405P.
producing a drive current from the output of the last
divider stage. The a 1 output is 1-second sh ifted from the
O 2 output. By connecting these to a stepping motor, the
1-second hand steps can be generated.
ALARM INPUT (ALI)
By setting the ALI pin to the value: of V ss , an alarm
waveform is output from ALa. In addition, by setting the
ALI pin to an intermediate value, a test state is achieved,
and a 2048Hz signal is continuously output from ALa. If
an intermediate level is appiied to ALI while X 1N and
X OUT are set to V ss , the last 12 stages of dividers can be
fed from the ALa signal.
Table 1 0 1 ,0 2 , and ALARM OUT Pin Output Waveforms
Oland 0 2 output waveform
Type
Pulse width T(msi
ALARM OUT pin output waveform
18
I
VDD
Vss
M50401P
M50403P
l"""1II
I----{-
I
2048Hz
"""" II
r--
250ms
I
50% duty cycle at 2048Hz, 2Hz and 1Hz
31
01
I EO
M50402P
M50404P
02
11
IE
ls
I
n
,I
31
T
EO
VDD
fl
--t+I
2s
IE
18
~:: llllnmnlllnlill
VSS
~
VDD
'Illif
125ms
Vss
2048Hz
.. I
50% duty cycle at 2048Hz, 8Hz and 1Hz
IE
M50405P
16
1s
~::llmmnlnlnmmll
~ ~ ~625m'
2048Hz
50% duty cycle at 2048Hz, 16Hz and 1 Hz
11-20
• MITSUBISHI
"ELECTRIC
)\
Ilmf
MITSUBISHI LSls
MS0401P, MS0402P
MS0403P, MS0404P, MS040SP
CMOS ANALOG CLOCK CIRCUITS
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Voo
Conditions
Supply voltage
With respect to Vss
Power dissipation
Ta=25°C
Limits
Unit
-0.3-4
V
300
mW
T opr
Operating temperature
-20-70
°C
T stg
Storage temperature
- 65-150
°C
RECOMMENDED OPERATING CONDITIONS
(Ta ~ 25°C,unless otherwise noted)
Limits
Symbol
Parameter
Unit
Min
Voa
Supply voltage
Vss
Supply voltage IGNO)
fose
V
0
M50402P
cryst~1
Max
1.5
M50401P
Quar\!
Nom
V
--
4 1943
MHz
32.768
kHz
frequency
M50403P
M50404P
M50405P
M50401P
30
M50402P
Q
60
Quart! crystal impeciance
RO
M50403P
20
kQ
External input capacitor
15
pF
External output capacitor
15
pF
M50404P
--c-CIN
----_._-
M50405P
--
.
COUT
ELECTRICAL CHARACTERISTICS
I Ta ~ 25°C, Vss
=
av, unless otherwise
noted)
Limits
Symbol
Test conditions
Parameter
I M50401P
Supply voltJge
Voo
~0402P
M50403P
M50404P
M50405P
Unit
Min
Typ
Max
GIN =GOUT = 15pF,
Ro =30 Q
1.1
1.5
1.8
V
GIN =GOUT = 15pF,
Ro =20kQ
1.1
1.5
1.8
V
Voo=1.5V, CIN=COUT=15pF,
Ro=30n
25
35
/1A
Voo=1.5V, CIN=COUT=15pF,
2
5
/1A
-M50401P
M50402P
100
__
__
RONIP+N)
Supply current
I
1_
f--
M50403P
M50404P
Ro=20k n
I M50405P
Motor drive output saturation resistance Ip channel
saturation resistance + n·channel saturation resistance)
Alarm output saturation resistance In-channel)
RONIAU
RL=180Q
55
75
Q
VOO = 1.2V,
lOUT = 1mA
200
300
Q
1
4
kQ
Voo
V
f-------
~DD=1.2V.
Alarm output saturation resistance Ip-channel)
VINH
VaD =1.2V,
Inp~t
lOuT =O.lmA
ALI pin
voltage
I
t--
VINL
RAH
6. fifo
I
-
Input voltage
ALI pin
Input pullup resistance
-
Oscillator frequency supply voltage
dependence
Vao
-0.15
I
M50401P
M50402P
M50403P
M50404P
M50405P
0.15
Vss
15
5
ALI pin
±
I
.!l2- f ,.7
1,5
V
kQ
1
ppm
ALO pin
• MITSUBISHI
.... ELECTRIC
±2
ppm
11-21
MITSUBISHI LSls
MS0401P, MS0402P
MS0403P, MS0404P, MS040SP
CMOS ANALOG CLOCK CIRCUITS
APPLICATION EXAMPLE
ALARM SETIING SWITCH
GIN 15pF
XIN
ACT
ALO
C=:J
XOUT
M50401P
0,
COUT
20pF (MAX)TRIMMER
VSS
02
VOO
1.5V
QUARTZ CRYSTAL
4.1943MHz
(32, 768kHz)
11--22
• MITSUBISHI
.... ELECTRIC
MITSUBISHI LSls
M58412P, M58413P
CMOS LCD DIGITAL ALARM CLOCK CIRCUITS
DESCRIPTION
PIN
CONFI~URATION
The M58412P and M58413P CMOS aluminum-gated LSls
(TOP VIEW)
>~
~;;
serve 4-digit liquid-crystal display (LCD) digital alarm
I
I
clocks employing quartz oscillators of 4.2 MHz and 32
kHz respectively.
FEATURES
•
Low current consumption. Under ordinary conditions,
M58412P consumes 30pA at an oscillator frequency of
4.2 MHz and VSS(l) level of -1.5V, while M58413P
consumes 2pA at 32 kHz and Vss
•
(1)
of -1.5V.
M58412P
OR
The 12-hour clock-display function shows AM or PM
M58413P
hours and minutes; the 24-hour system shows hours
and minutes alone.
•
Separate switches enable independent setting of hours
and mi nutes.
•
Five alarm output signals are provided: a continuous
F, KOR Bo _
AM OR
AoDoEoGo -
14
NC ~15~~-rr~Ir'-T;~~~~~~~~~
alarm-bell signal, intermittent alarm-bell signal, external
bell-oscillator-circuit-drive
signal, external
electronic-
apparatus switching signal, and 12 min or 120 min DC
Outline 60P2
signal.
•
The alarm bell output can continue for up to 12 min.
APPLICA TIONS
•
A 10 min 'snooze' function is incorporated.
•
Alarm clocks with a 'snooze' function
•
The LSI causes the whole display to flash on and off
•
Sleep timers
when battery voltage drops below the specified level.
•
•
Travel watches
Switching timers for electronic apparatus
The display offers immediate indication of the function
•
Auto-recording timers for audio equipment
in current operation.
FUNCTION
•
•
Two LCD mark outputs are provided: alarm and sleep.
The LSI s enable sleep and auto-recording timers to be
Normal clock, alarm clock, 'snooze' timer, sleep timer,
set at any time during a 59-minute period. A 120-minute
electronic-apparatus switching timer, and aUdio-equipment
output mode is also available with auto-recording timers.
auto-recording timer functions are provided by the oscillator and frequency divider (4.2 MHz for M58412P and
32 kHz for M58413P).
BLOCK DIAGRAM
VOLTAGE DOUBLER
TERMINALS
~
BATTERY
DETECTOR
CF CT
QUARTZ CRYSTAL
TERMINALS
~
XTAL2
56
XTAL 1
55
Ell
LCD
OUTPUTS
~
Z
=:l
o
U
CONTROL
INPUTS
TEST
INPUTS
• MITSUBISHI
..... ELECTRIC
11
~23
MITSUBISHI LSls
MS8412P, MS8413P
CMOS LCD DIGITAL ALARM CLOCK CIRCUITS
arrays on the LCD panel, the segment codes, and the display modes.
OPERATION
The following figures and tables show the LCD-electrode
An LCD-electrode arrangement and names of segments and marks (12-hour clock display)
AM
K
K
COL
Fll
I
Gl
Ell
Gl
E1
•
•
IBl
I
Cl
01
82
A2
01
PM
A2
F2
Al
AM
PM
81
Al
F 1
F21
E21
COL
(COLON)
G2
Cl
F31
I
E31
C2
02
C2
G3
SL.MARK
1
fJ
83
G3
I
(SLEEP MARK)
(ALARM MARK)
C3
4
AL.MARK
E3
03
C3
Table 1 12-Hour Clock Display
Mode
Normal clock
ordinary display
PM
AM
Alarm
I
Display
I
I
J1
C-:+:- -
-I e I-I I-I
I e I_I I_I
-
~ -
\
~~:\
Sleep-time
-I I-I
I_I
=1
-~/_/
,
11
'
-
Note 1. The symbol .,:~ Indicates a 2sec on-off flash
11
~
24
Meaning of mark display
I
,1/1l -e/, ' _ I I
CI
• MITSUBISHI
"'ELECTRIC
~
-
-
COM
SL.MARK
03
02
E2
83
A3
I
B2
G2
A3
F3
Sleep timer IS In operation
Alarm timer IS being set
Alarm time IS displayed; adjustment possible
Sleep time is displayed; adjustment possible
Alarm timer IS being set
AL.MARK
MITSUBISHI LSls
M58412P, M58413P
CMOS LCD DIGITAL ALARM CLOCK CIRCUITS
An LCD-electrode arrangement and names of segments and marks (24-hour clock display)
AD
DO
EO
GO
BO
AD
EO
GO
I
F1
A1
I I
BO
I
CO
F1
G1
A1
I
D1
A2
F2
•
•
C1
F21
G2
I
B2
G2
I
C2
E21
F3
B3
A3
F31
G3
E31
SL.MARK
COM
n
SL.MARK
A3
D2
COL
(COLON)
C1
B2
A2
B1
D1
E1
COL
I
G1
Ell
DO
CO
B1
I
B3
I
(SLEEP MARK)
(ALARM
C3
MARK)
4
D3
AL. MARK
E2
D2
C2
E3
03
D3
C3
AL. MARK
.Table 2 24-Hour Clock Display
Normal display
Meaning of mark display
Display
Mode
? ::
Alarm display
••
,,\
~
_
/
\
/
-
"
-r--
Sleep timer
-r--
Alarm timer IS being set
-~
Alarm time
",
-JJ
/ ,,I,,- -~
IS
IS
In operation
displayed: adjustment possible
/
Sleep-time display
30
..
-~
Sleep time is displayed: adjustment possible
Alarm timer
IS
being set
Note 1 The symbol ;:" Indicates a 2sec on-off flash
• MITSUBISHI
..... ELECTRIC
11
~25
MITSUBISHI LSls
MS8412P, MS8413P
CMOS LCD DIGITAL ALARM CLOCK CIRCUITS
FUNCTIONS OF INPUT AND OUTPUT PINS
Input Pins
5sPin
This pin is used to provide alarm-timer set input. Main-
The potential drop to the level of VSS(t) (-1.5V) or VSS(2)
(-3V) achieved inside the LSI ensures that all the input
taining this input pin at the V DD level causes the alarm
pins are used in the floating-state condition. The input pins
AI, A 2 , A 3 , SI, and S6 have the potential of V SS (!), while
all the other input pins have V SS (2). Signal input requires
the use of the V DD (GND) level for all input pins.
5, Pin
Every push of the SI push-button switch advances 1 minute
in normal clock-time adjustment, alarm-time setting and
sleep-time setting. Raising to the hour digit is prohibited in
this operation. In the normal-clock ordinary-display mode,
the SI pin also serves as a start/stop input pin for the sleep
timer. A sleep mark flashing on and off displays the sleep
mark to stay on. When the normal clock time coincides
with the alarm time, two types of alarm output, AL. OUT1
and AL. OUT2, generate alarm signals. (The alarm signal
with a pulse width of 250ms is generated only once after
the coincidence takes place.) When cancellation of the
alarm signal is desired, disconnecting the S5 pin from the
V DD level causes both the alarm mark and alarm signal to
disappear. No alarm signals will be generated when the
normal clock time coincides with the alarm time, unless
the S5 pin is at the V DD level.
56 Pin
This pin has three functions: 'snooze' timer-setting input,
timer's operation. It will disappear when the sleep timer
stops operation, or as soon as the time initially set on the
sleep timer is reached.
sleep-timer resetting input, and LCD lamp switching at
52 Pin
Every push of the S2 push-button switch advances 1 hour
momentarily to V DD stops the alarm signal for a moment
and generates it again after 9 ~ 10 minutes. (The 1-pulse
in normal clock-time adjustment and alarm-time setting. In
the normal-clock ordinary-display mode, the S2 pin also
alarm signal with a 250ms pulse width cannot be generated
again.) The 'snooze' function can be repeated at every sig-
serves as an input pin to bring the sleep output to the
nal input made to theS6 pin. However, it does not operate
after an alarm signal has continued for 12 minutes. This
function is useful for 'snooze' clocks and other appli-
VSS (!) level. This function makes it possible to switch off
a radio or other electronic apparatus before the time initially set on the sleep timer is reached.
53 Pin
When the A3 pin is held at the V DD level, a momentary
switch should be used to enable the input with the S3 -pin
potential to change momentarily to the V DD level. Pushing
the S3 switch changes the mode cyclically in the sequence:
normal-clock ordinary display; alarm-time display (alarmtime setting is possible); and sleep-time display (sleep-time
setting is possible). However, when the A3 pin is in the
floating state (the inside-LSI potential is -1.5V), it is recommended to use a lock switch to retain the V DD level at
the S3 pin. While S3 -pin potential is kept at V DD, the
alarm-time display mode is effective (alarm-time setting is
possible). Disconnecting the S3 pin restores the normalclock ordinary-display mode. The sleep-timer mode cannot
be used when the A3 pin is in the floating state. In this
case, however, there are convenient applications (for travel
watches, etc.) free from the problem of alarm-time lags
behind the set time which sometimes arise from the use of
momentary switches due to their accidental operation.
night. When an alarm signal is generated in the normalclock ordinary-display mode, bringing the S6 potential
cations.
When no alarm signals are generated in the normal-clock
ordinary-display mode, or when the 'snooze' function is
not in operation, bringing the S6 potential momentarily to
V DD makes it possible to reset the sleep time to 59 minutes and to make the sleep output level V DD' This means
that when a stereo or other apparatus connected is to be
switched off after 59~60 minutes, it is unnecessary to use
the 59 minute setting in the sleep-time display mode: It is
only necessary to push the S6 push-button switch and then
push the SI-pin start button, giving great ease of operation.
The S6 pin, at a potential level of -1 .5V, also serves as an
LCD lamp power terminal at night (See Fig. 1). Care should
be taken, however, over the fact that every ti me the LCD
lamp is turned on a 'snooze' timer set input or sleep-timer/
reset input is entered.
Fig. 1 All LCD lamp circuit
VDD
54 Pin
When the normal-clock normal-display mode of the basic
clock is effective, maintaining this pin at the V DD level
causes entry to the normal-clock time-adjustment mode.
After time adjustment with the 5, and 52 pins, clock
operation starts with the '00' second of the adjusted time as
soon as S4 is disconnected from the V DD level.
11-26
• MITSUBISHI
.... ELECTRIC
VSS( 1) ( -1. 5V)
MITSUBISHI LSls
MS8412P, MS8413P
CMOS LCD DIGITAL ALARM CLOCK CIRCUITS
A1 and A2 Pins
T1, T2 and T3 Pins
AL. OUT1 pin alarm output in different modes is generated
The T 3 pin is a clock-input pin for high-speed test use.
in accord with a combination of the Ai - and A2 -pin potentials. Table 3 shows four modes and their applications.
Combinations of T t and T 2 pin potentials control the test
mode and options, as shown in Table 4.
Table 3 AL. OUT1 Pin Alarm Output
Table 4 Test Mode
Al
Az
Output waveform of
AL. OUTl
~---T----~----------------------------------~
Operation of bells.
__ 1024Hz
N.C.
N.C.
VDD
VSS(1)JIIIIIIII~IIIIIIIL
I.-----~
ls
ls
Mode
Main applications
N.C.
N.C.
Normal operation
VDD
N.C.
Normal-clock ordinary display with the colon kept ON
(without colon on-off flash)
N.C.
VDD
The counter IS reset and 12: 00 AM (0: 00 for 24-hour cycle)
is displayed in the normal-clock ordinary-display mode. Here.
the alarm time is 12: 00 AM (0: 00 for 24-hour cycle) and the
sleep time is 59 minutes
VDD
VDD
Carryover from the minute to the hour digits is prohibited. The
common output is held at the V SS (2) level. and the segment
and mark output for display is at the VDD level. High-speed
testing is possible.
buzzers and other
sound sources without
oscillator circuits
(intermittent sound)
Operation of sound
VDD
sources with oscillator
N.C.
circuits (intermittent
sound)
Operation of sound
V
N.C.
VDD
DD
VSS(1)
__ 1024Hz
J 11111111111111-------
sources without
oscillation circuits
(continuous sound)
OUTPUT PINS
Output Pins for Segments, COM, COM AL MARK,
and SL. MARK
The COM output pin common signal has a frequency of
32Hz. Segments and mark output pins which are not displayed give common signals, while segments and mark
output pins displayed give inverse-phase signals of common
VDD
VDD
Jl
VDD
V SS( 1) -LLi---2-50-m-s-----
Switching of
electronic apparatus
signals. The COM output is used for permanently-displayed
segments or marks.
AL. OUT1 (Alarm output 1) Pin
When the normal-c!ock ordinary-display time coincides
with the alarm time, alarm signals with the waveforms
A3 Pin
shown in Table 3 are generated at the AL. OUT1 pin for
This pin controls mode shifts between normal-clock ordina-
12 minutes. The 250 ms pulse-width alarm output, how-
ry-display mode, alarm-time display mode, and sleep-time
ever, is given only once after"the coincidence.
display mode by the S3 pin. When the A3 pin is not con-
Coincidence in the alarm-time display mode causes the
nected (N.C.), it operates in ~he alarm-time display mode
AL. OUT1 to be given for one minute. When they coincide
so long as the S3 pin is at the V DD . level. When the S3 pin
in the normal-clock time-adjustment mode, continuous
alarm signals are generated until the time is advanced.
'
is disconnected from the V DD contact, the S3 pin enters
the normal-clock ordinary-display mode, but not the sleep-
AL. OUT2 (Alarm Output 2) Pin
time display mode. When the A3 pin is at the V DD level,
mode shifts occur cyclically in the sequence: normal-clock
the AL. OUT1 is the 250 ms pulse-width alarm output),
ordinary display; alarm-time display; sleep-time display;
the AL. OUT2 pin gives a DC output for 110,.....120 min. In
and normal-clock ordinary display, each time the S3 pin is
cases of the alarm-time minute digit set to integral multiples
When both the At and A2 pins are at the V DD level (when
momentarily at the V DD level.
of 10 minutes from 10 to 50 min., a DC output is sent out
12/24 Pin
for 120 min. This signal is useful for controlling electronic
Bringing the 12/24-hour pin to the V DD level turns the
apparatus for 2-hour auto-recording. When both
12-hour cycle display into the 24-hour cycle display.
At and A2 pins are at other than the V DD level, a DC out-
the
put is given for 11,.....12 min by the AL. OUT2 pin.
Fig. 2 Alarm output waveforms
Al. A2=
Voo level
~.
Voo
tl----------:1:-:-1-;O-O----:l-:::-20:;:---m-in-ut-es------lL VSS(1)
I Coincident with alarm time
A,. A2=
otherthanVoolevel
• MITSUBISHI
.... ELECTRIC
~
L
11-12minutes
Voo
VSS(1)
11-27
'Ell
MITSUBISHI LSls
MS8412P, MS8413P
CMOS LCD DIGITAL ALARM CLOCK CIRCUITS
SL. OUT (Sleep Output) Pin
This pin can be used not only for sleep timers but also for
turning on and off radios, TVs, cassette decks, and VTRs. In
the normal-clock ordinary-display mode, the 5L. OUT pin
can be brought to the V DD level, i.e., the switch-on stage,
by starting the sleep timer with the 51 pin, or by bringing
the S6 pin potential momentarily to Voo after 12 minutes'
issuance of the alarm signal or when the 'snooze' function
is not in operation. As soon as the sleep time becomes
59 minutes in the normal-clock ordinary-display mode
(the sleep timer does not display the time elapsed), or by
voltage drops to any specified lEivel in the detectable voltage
range of VDD=-1.2--1.5V. This flashing can be stopped
by making the 56 potential momentarily V DD. However, it
will start again at the next sampling time (max. one minute
later) until the battery is replaced.
OPERATIONAL METHODS
Minute
adjustment
(51)
Fig. 3 SL. OUT output waveforms
to:
Start ( 51)
L
~--------------------~
(52)
~I--'_----'-"--to-~L
Start ( 5 1)
(2)
Stop ( 5 1 )
(3)
J
r----,'
I
Alarm time dlsplay/
adjustment mode
PM
Note 2
The symbol
':f shows a 2sec-peflod on-off flash
3 Lock SWitches are used In the S 3, S 4 and S 5 pins
j
Fig. 5 Operation when the A3, pin is at the V DD level
A
M
_I • -I 1I . :1 CI
-
Reset to '00' sec
Sleep timer
startlstop( S 1 ) Sleep output
cancel (S 2)
Sleep-out cancelling (52 )
---ltr-=-"-to~'i
t
Minute
adjustment
(S ,)
VDD , VSS (1), VSS (2), CF, and CT Pins
The electrical power supply is a 1.5V battery (=V DDVSS(l)). Use of 0.1JlF condensers between the CF and CT
pins and between the VSS (2) and VDD(GND) pins gives voltage about double the power voltage, making possible direct
Hour
adjustment
(S2 )
--
BD (Battery Detector) Pin
(S ,)
By connecting a resistor between the BD and VSS(t) pins
which has a proper temperature characteristic and a resistance between 15kn. and 750n., the segments and marks displayed flash on and off in a 2sec period, a visual reminder
of the necessity to replace the battery, when the battery
--
--
Minute
adjustment
operation of the LCD.
AM
Start from '00' sec
:1
-I
L -'e'~ EI
','
,',
-,~~
I
PM
Normal-clock ordlnarydisplay mode
(S3)
r • nn
:1 LI LI ,\
•
~
Alarm time display/
adjustment mode
(S3 )
:In ~'.?::
--
~
LI
I
The symbol ?:~ shows a 2sec-period on-off flash.
5 : Lock switches are used in the S 4 and S 5 pins
• MITSUBISHI
..... ELECTRIC
/
-~/1'
(S3)
Note 4
Normal-clock
adjustment mode
I
(S4)
Voo
VSS(l)
I
-
'----------------1
(S2)
VSS(l)
POWER CIRCUITS
11-28
Normal-clock ordlnarydisplay mode
Start (5 1 )
VSS(l)
Start from '00' sec
~------------------~
Voo
~+r.--~tl---+~---------Tt-.~t~o~t-l~~ Voo
Start ( S 1)
I
(5,)
AM
Hour
adjustment
(1)
t
Reset to '00' sec
Minute
adJ.ustment
(St)
Sleep time set
Normal-clock
adjustment mode
_
AM_I
Hour
adjustment
bringing the S2 -pin potential momentarily to V DD in the
normal-clock ordinary-display mode, the switch-off state,
i.e., the V SS (!) level, holds. Fig. 3 shows 5L. OUT-pin output waveforms: (1) when the switched-off state is entered
at the sleep time set; (2) when the timer is stopped after
the start of the sleep timer and started again; and (3) when
the switched-off state is entered before the sleep time set.
Input pins to be used are shown in parentheses. When the
sleep output is turned to the V DD level by using the 56 pin,
this level is maintained unless the sleep timer is started
with the 51 pin. Use of the 5L. OUT pin as a maximum
60-minute auto-recording pin requires that both the Al and
A2 pin potentials are set to V DD and the AL. OUT1 pin is
connected with the 51 pin as shown in Fig. 7. In this case,
sleep output assumes the V DD level when the alarm time
coincides with the normal time.
j
Fig. 4 Operation when the A3 Pin is N.C.
Sleep-time display/
adjust ment mode
MITSUBISHI LSls
M58412P, M58413P
CMOS LCD DIGITAL ALARM CLOCK CIRCUITS
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Conditions
Limits
Unit
VSS(l)
Supply voltage
VSS(2)
Supply voltage
V,(l)
Input voltage for V SS ( 1) supply
V, (2)
Input voltage fOrVSS(2) supply
VSS(2) -Voo
Topr
Operating Iree-alr ambient temperature range
-20 -65
·C
Tstg
Storage temperature range
-30 -80
·C
Voo =GNO
Ta =25·C
0.1- -3
V
0.1- -7
V
VSS(l) -Voo
V
V
RECOMMENDED OPERATING CONDITIONS(Ta =25·C, unless otherwise noted)
Symbol
Parameter
VSS(l)
Supply voltage
VSS(2)
Supply voltage
Conditions
Limits
(Note 6)
Min
Nom
Max
-1 .2
- 1. 5
-1.9
Unit
M58412P
C'N=15pF, COUT - 10pF
Ro
M58413P
C,N = 15pF, COUT =30pF
Ro=30k Q
- 1. 1
-1.5
-2
V
M 58412P
C,N = 15pF, COUT
Ro=20 Q
-2.4
-3
-3.8
V
M 58413P
C'N=15pF, COUT =30pF
Ro=30kQ
-2.2
-3
-4
V
=
10pF
~20
Q
V
ELECTRICAL CHARACTERISTICS
(T a =25·C , Voo =GNO, M58412P: f =4. 1943MHz, M58413P: I =32. 768kHz, unless otherwise noted)
Symbol
Limits
Test conditions (Note 6)
Parameter
M58412 P
Min
VSS(l) =-1 5V,C'N = 15pF, COUT= 10pF
C I =C2 =0. l/LF, Ro=20 Q
100
Supply current from Voo
M 58413P
M58412 P
V'(OSC)
VSS( I) = -1. 5V,C'N=15pF,COUT=30pF
C,=C2 =O.I/lF, Ro=30k Q
C'N=15pF, CouT=10pF, Ro=20Q
within 1sec of oscillation
U.nit
Typ
Max
30
80
ILA
2
5
J1.A
-1.2
V
-1.2
V
Oscillator input voltage
M58413 P
C'N=15pF, COUT=30pF, RO=30k Q
within 5sec 01 oscillation
IOL(COM)
Low-level output current (common)
VSS(2)=-3V,
VOL=-2. 9V
30
J1.A
IOH(COM)
High-level output current (common)
VSS(2) = -3 V,
VOH= -0. 1V
-30
J1.A
IOL(SEG)
Low-level output current (segment)
VSS(2) = -3 V,
VOL=-2. 9V
5
J1.A
I OH( SEG)
High-level output current (segment)
VSS(2)=-3V,
VOH=-O. lV
5
J1.A
I oL( AL)
Low-level output current (alarm. sleep)
VSS(l) =-1.5V, VOL = -lV
100
J1.A
IOH(AL)
High-level output current (alarm, sleep)
VSS(I) =-1.5V, VOH=-0.5V
IlL
Low-level input current
I'H
High-level input current
VO(2)
Doubler output voltage
V,(BO)
Battery detector voltage range
-
-100
VSS(1)=-3V, V'L=-3V
except lor test input terminals
VSS(2) = -3V, V'H=OV
except for test input terminals
VSS(1)=-1.5V, Cl=C2=0. l/lF
J1.A
-0.2
ILA
0.2
J1.A
-2,8
V
lo=2/lA
15k Q
~RBO ~750k Q
-1.2
-1.5
V
Note 6 : RO refers to a crystal impedance.
• MITSUBISHI
..... ELECTRIC
11-29
MITSUBISHI LSls
MS8412P, MS8413P
CMOS LCD DIGITAL ALARM CLOCK CIRCUITS
APPLICATION EXAMPLES
Fig. 6 An alarm clock with 'snooze' and sleep functions
SEGMENT OUTPUT
Jr
51 A L . 0 UTI
!---'\I\I'\r-_ _-1
30
Al
27
Tl
x TAL 1
26
T2
M58412P
3 -23pF
25
T3
SI
Cl
} NC
28
A3
----+--+-----:-;:--;::----':-:"1 S L. 0 U T
5
1---=...:...---:-;-=-:--:-----=5-"-1
29
A2
.----+_+----.JV\f\,,-_----"-5-=-j0 B 0
TO SWITCHING CIRCUITS
53
FOR ELECTRICAL EQUIPMENT
54 V[)[)
S2
S3
}NC
MOMENTARY
SWITCH
24
---L--
22
---L-
21
---L--
0--
LOCK SWITCH
20
S4
~
---0
~o-
19
S5
18
S6
SEGMENT OUTPUT
Fig. 7 An alarm clock with 'snooze' and auto-recording
functions
SEGMENT OUTPUT
D~
TO SWITCHING
{
CIRCUIT FOR
UNATTENDED
TAPE RECORDING
51
AAA
vv
~
HI
15PF
~ XTAL
IV"
3
-f1
57
Cl=r°.l/IF
58
C~I 0.
l/IF
59
II
l.l.5V
I
1\1\/\
v
v
I
60
50
T J
cll-}
T2 -
26
S2
CT
S3
2
S4
1
S5
BD
S6
~o
~o-
NC
~
MOMENTARY
SWITCH
M58412P
SI
VSS
'-0-----.
29
28
A2
A3
CF
VSS
30
AJ
T3
XTAL2
:-0-
I
AL OUTI
52 ALOUT2
54
SL.OUT
53
V[)1l
55
XTALI
¥4.19MHz 56
23pF
TWO-WAY
TWO·POLE
SWITCH
-=rL
24
22
21
20
~o-----.
j\
~
--0
0-
10----.
~0-----.
r;
-0-----.
19
,...
-0-----.
18
j\
10---
LOCK SWITCH
----0--0-
SEGMENT OU1 PUT
Note 7
The circuit of Fig. 6 gives intermittent alarm-bell tones
8
The circuit of Fig. 7 gives continuous alarm-bell tones
output and of the SL OUT pin for maximum 60' minute non-fixed-time
9
Use of Type M58413P in Fig. 6 and Fig. 7 requires the employment
auto-recording output
Note 10 : Use is made of AL OUT2 for 11 0 - 120 minute fixed-time auto-recording
of a 32kHz quartz oscillator and a 5 - 35p F variable condenser.
11-30
• MITSUBISHI
"ELECTRIC
MITSUBISHI LSls
M58435P
MS8437-001P
CMOS ANALOG CLOCK CIRCUITS
DESCRIPTION
PIN CONFIGURATION (TOP VIEW)
This family of CMOS circuits is particularly suited for crystal-controlled clocks where induction motors or stepping
motors are used.
Type
Process
Crystal oscillator
Motor
4.1943MHz
Stepping
32.768KHz
StepPing
motor
Alarm sound
QUARTZ
OSCILLATION
INPUT
(1.5V)
M58435P
M58437
Silicon-gate
CMOS
motor
1024Hz
(OV)
7
-OO1P
CMOS
4096X8X 1Hz
MOTOR DRIVING OUTPUT
6
FEATURES
•
•
Low power dissipation:
M58435P: ...................................... 30llA
(typ)
M58437-001P: ................................ 21lA
(typ)
Low voltage operation:
M58435P: ...................................... 1.2V
(min)
M58437-001P: ........ ·························1.1V
(min)
Direct drive of ceramic resonator (M58437-001 P only)
-+ ALARM
OUT
RESE(1bNfEU1j RESET -+ 4
•
-+ XTAL2
g~~I~liTION
OUTPUT
Aluminum-gate
~'R1'~I~GBELL
OUTPUT
MOTOR DRIVING OUTPUT
'----_.....
Note1: ThiS pin is non-connected for
M58434P
Outline 8Pl (M58435P)
(M58437-001P)
FUNCTION
Circuitry consists of an oscillator, frequency divider, bridge-
APPLICATIONS
type driver circuit for an induction motor ora stepping motor
•
Crystal-controlled alarm clock
(M58435P, M58437-001 P),and an alarm bell driver circuit.
•
Precision timepiece for electronic apparatus
•
Frequency divider for electronic apparatus
The oscillator frequency is 32.768kHzfor the M58437-001 P
and 4.1943 MHz for the other types.
BLOCK DIAGRAM
OSCILLATION
CIRCUIT
QUARTZ OSCILLATION INPUT
FREQUENCY
DIVIDING CIRCUIT
OUTPUT
BUFFER
CIRCUIT
MOTOR
DRIVING OUTPUT
QUARTZ OSCILLATION OUTPUT
RESET INPUT
(NOTE 2)
RESET 4 ) - - - - - - - - - - - - - - '
(OV)
ALARM
OUTPUT
BUFFER
CIRCUIT
ALARM ALARM BELL
DRIVING OUTPUT
6 OUT
~VOO(1.5V)
vssL' _
________________________ ---.J
Note 2
• MITSUBISHI
"ELECTRIC
M58434P has no reset input pin
11- 31
MITSUBISHI LSls
M58435P
M58437-001P
CMOS ANALOG CLOCK CIRCUITS
FUNCTIONAL DESCRIPTION
Oscillation Circuit
that time, and invert 0.97-1.0sec after the reset terminal
This circuit is completed by connecting a crystal between
is released from the Vss level. In the M58436-001 P and
XTAL 1 (oscillation input) and XTAL 2 (oscillation output)
M58437-001P, OUT 1
and capacitances between both terminals and GND.
0.97-1.0sec after the reset terminal is released from Vss
level, a 31ms pulse is generated from the output opposite
Motor Driver Circuit
and OUT 2 go to the Vss level, and
This circuit amplifies motor driving current at the output
to the one that emitted a 31ms pulse immediately before
frequency of the last divider. In M58435P,Outputs OUT 1
the reset. If the RESET terminal is connected with the Vss
during the 31ms pulse, the reset will be started completely
and OUT 2 are always in a mutually reversed phase, while in
the M58437-001P, OUT, has a wave-form delayed lsec
from OUT2 •
It is realized by continuous movement or
stepped movement when the M58434P is connected to an
induction motor (M58434), to a stepping
series-connected
motor with
after the pulse ends. This prevents inadvertent interruption
of complete action of the motor owing to the reset function. The M59434P has no reset function.
Alarm Output Buffer Circuit
capacitance (M58435P) or a stepping
This circuit consists of an N-channel open-drain MaS tran-
motor (M58437-001 Pl. The size of the capacitance for
M58435P is determined by the·total current consumption
and the required motor torque, and with a 47J.lF capacitor,
sistor and generates a signal to drive a ceramic resonator or
magnetic speaker (see p. 10-14). The alarm output is a
1024 Hz signal, with a duty cycle of 50% for M5843P and
SUM-2 manganese dry cells will last for about one year.
M58435P, and burst signals of 4096Hz, 8Hz, and 1Hz,
Reset Input (RESET)
each of 50% duty, for M58437-001P. Direct drive of the
When the RESET terminal of the M58435P is held at Vss
ceramic resonator by M58437-001P is possible because
level, outputs OUTland OUT2 hold their current states of
of the high alarm output breakdown voltage.
Table 1 Output Waveforms on the OUT1, OUT2, and ALARM OUT terminals
Type
OUT,l
M58435P
OUT2
-
L
I
--VOO
M58437-001 P
OU T 2
11I.
r1024HZ 50% duty cycle
VSS
-VOO
VSS
VSS
2s 50% duty cycle
ls
"I
2s
JIIIIIIIIIIIIIIIIIIIIIIIIII-------
T
n
OUT,
ALARM OUT waveform
VOO
I
"I IE
11-32
Pulse Width (ms!
OUT, and OUT2 waveform
IE
VOO
T
Vss
=Jr.:::
31
ls
~:: llllnmnlllnllli
~LJ
125ms
4096Hz
50% duty cycle for 4096Hz, 8Hz, and 1Hz
• MITSUBISHI
.... ELECTRIC
)01
IIIW
MITSUBISHI LSls
MS843SP
MS8437-001P
CMOS ANALOG CLOCK CIRCUITS
ABSOLUTE MAXIMUM RATINGS
Symbol
Conditions
Parameter
VOO
Supply voltage
With respect to Vss
Pd
Maximum power dissipation
Ta=25"C
Topr
Tstg
limits
Unit
-0.3-5
V
300
mW
Operating free-air ambient temperature range
-20-70
"C
Storage temperature range
-40-125
"C
RECOMMENDED OPERATING CONDITIONS
(Ta=25"C. unless otherwise noted)
Limits
Symbol
Parameter
Unit
Min
VDO
Supply voltage
Vss
Supply voltage IGNO)
fosc
Ro
Max
Nom
1.5
V
0
V
M58435P
4.1943
M58437-001P
32.768
-MHz
Crystal oscllatlon frequency
kHz
Crystal impedance of crystal
M58435P
30
60
Q
oscillator
M 58437 -001 P
20
30
kQ
GIN
External input capacity
20
pF
GOUT
External output capacity
20
pF
ELECTRICAL CHARACTERISTICS
(Ta = 25"C,
Vss = 0 V . unless otherwise noted)
Limits
Symbol
Test conditions
Parameter
Unit
Min
Voo
100
RON(P+N)
RON(AL)
Isw
Typ
Max
M58435P
GIN=GOUT=20pF, RO=30Q
1 :2
1.5
1.9
M58437-001P
GIN = GOUT = 20pF, RO= 20k Q
1.1
1.5
1.9
V
,v158435P
Voo= 1.SV, CIN=COUT=20pF, Ro=30Q
30
50
fJ- A
M 58437 -001 P
Voo= 1.SV, CIN=COUT=20pF"RO=20kQ
2
5
fJ-A
Motor driving output saturation resistance
IP-channel + N-channel)
M58435P
VOO= 1.5V, IOUT=
±
3 mA
150
300
Q
M 58437 -001 P
Voo= 1.5V, IOUT=
±
3 mA
100
200
Q
Alarm bell driving output saturation
IN-channel)
resistance
M58435P
VOO=1.5V,IOUT= 3mA
0.5
1
M 58437-001 P
VOO=1.5V,IOUT= 3mA
100
200
V
Supply voltage
Supply current
Reset Input current
M58435P
• MITSUBISHI
.... ELECTRIC
Q
1
fJ-A
1
J.iA
VDO=1.5V
M 58437 -00 1 P
kQ
11-33
MITSUBISHI LSls
M58435P
M58437-001P
CMOS ANALOG CLOCK CIRCUITS
APPLICATION EXAMPLES
(2.) Ceramic buzzer with M58437-001P
(1) Magnetic speaker with M58435P
MAGNETIC SPEAKER
CRYSTAL. GIN 20pF
OSCILLATOR
RESET SWTICH
CERAMIC
RESONATOR
CRYSTAL GIN
OSCILLATOR
4.1943MHz
32.768kHz
GOUT
GOUT
SpF3SpF
MOTOR
ALARM
ACTIVATING
CONTACT
Vss
VOO
MJl
ALARM ACTIVATING
CONTACT
~----~Ir-4-------~
1.SV
(3) Magnetic speaker with M58437-001P
RESET SWITCH
CRYSTAL GIN
OSCILLATOR
32.768kHz
) ) ) MAGNETIC
SPEAKER
GOUT
ALARM ACTIVATING
CONTACT
11
~34
• MITSUBISHI
"ELECTRIC
ALARM ON SWITCH
MITSUBISHI LSls
M58478P,MS0121P,MS0122P
17 -STAGE OSCILLATOR/DIVIDER
DESCRIPTION
The M58478P, M50121P, and M50122P are semiconductor
PIN CONFIGURATION (TOP VIEW)
integrated circuits which use aluminum-gate CMOS technology. The M58478P produces a frequency of 1/59719 or
1/88672, the M50121 P produces a frequency of 1/58239
or 1/61425, and the M50122P produces a frequency of
1/86118 or 1/92077 of the input frequency.
DIVIDED
FREOUENCY 0 U T OUTPUT
FEATURES
•
Usable as a crystal oscillator circuit
•
Capable of handling small-amplitude input signals as low
as 0.3V pp
•
Frequency-dividing ratio selected through pin N
•
•
Reset function
Produces a shaped-waveform output of the same frequency as the input signal or oscillation output
•
Derives a vertical scanning frequency from TV color
subcarrier
IOV)
1
VDD
Vss
1475~8.5V)
~~~~E~-~~~~
7 _
TUN E R
6 _
OSC OUT g~~~~TION
5 _
OSC IN
OSCILLATION
INPUT
(M58478 p)
(M50121 P)
(M50122P)
Outline 8P4
APPLICATION
Frequency divider for VTR equipment.
Table 1 Input versus output frequencies
FEATURES
The M58478P, M50121P, and M50122P have a program-
Type
divider which provides one of two frequency-dividing ratios
as selected by the state of the N input.
Input frequency
State of the N input
Output frequency
(Hz)
(MHz)
mable counter consisting of a 17-stage binary frequency
M58478P
3.579545
4.433618
M50121P
3.579545
M50122P
4.433618
H(open)
59.94
L
50.00
H(open)
61.46
L
58.28
H(open)
51.48
L
48.15
BLOCK DIAGRAM
III
OSCILLATION INPUT
as C
IN 5
17-STAGE BINARY FREQUENCY DIVIDER
OSCILLATION OSC OUT 6
OUTPUT
SHAPED-WAV~~T~~~
RESETINPUT
TUN E R 7
RESET PULSE GENERATOR
1
OUT g~~g~~ FREQUENCY
9
VDD 1'75-85"
~V"IDVI
RESET 4 ) . - - - - - - - - - - - - '
• MITSUBISHI
"ELECTRIC
11-35
MITSUBISHI LSls
MS8478P,MS0121P,MS0122P
17 ·STAGE OSCILLATOR/DIVIDER
FUNCTIONAL DESCRIPTION
Crystal Oscillator
Special Frequency Dividing Ratios
A crystal oscillator is configured by connecting a quartz
resonator element between pins OSC IN and OSC OUT,
and capacitances C L1 and C LO between the two pins and
Vss (the feedback resistor included, on the chip).
A built-in amplifier at the OSC IN pin enables even
small amplitude signals to be input through a coupling
capacitor.
It is possible to modify the frequency dividing ratios on
special order. By changing one of the manufacturing
processes, the data inRut of the programmable counter
consisting of a 17-stage binary divider can be changed to
enable any frequency-dividing ratio from 5 to 131071 (=
217__ 1 ).
Table 2
Type
Output Frequency
The frequency dividing ratio depends on the state of the N
input. Table 2 summarizes the frequency dividing ratios and
duty cycles as they are related to this N input. An example
of a divided 1requency output waveform is shown in Fig. 1.
M58478P
M50121P
M50122P
When input N is open (or high):
I
OUT - - - - ,
NO OF INPUT I
I
CLOCK PULSES 1-26953 COUNTS-+--
32766 COUNTS
When input N is low:
OUT
---,L..-_____---!,
NO. OF INPUT
CLOCK PULSES
L
55906 COUNTS
I
~
32766 COUNTS
j
L
Note 1. The frequency-dividing ration in the following cycle is deterrnined
by the state of N input in just before the output OUT changes
frorn high to low.
Fig. 1 Waveforms of divided-frequency output
(for the M58478P)
A shaped-waveform output of the same frequency as the
input signal or oscillation frequency is available at the
TUNER output.
Reset Function
When the RESET input is changed from high to low (edge
triggered, active low input), the output OUT changes to
low.
Pull-up Resistance
There are resistors at the Nand RESET inputs, eliminating
the need for external resistors. The standard resistance of
the pull-up resistor is 20kn.
Frequency Dividing Ratio
The frequency-dividing ratio is determined by the data
input of the programmable counter consisting of a 17-stage
binary divider.
11-36
• MITSUBISHI
.... ELECTRIC
Frequency-Dividing Ratios
State of the
N input
Frequencydividing ratio
Divided frequency
Divided frequency
output lOW-level period output high·level period
H
59719
26953
32766
L
88672
55906
32766
H
58239
25473
32766
L
61425
28659
32766
H
86118
53352
32766
L
92077
59311
32766
MITSUBISHI LSls
MS8478P,MS0121P,MS0122P
17-STAGE OSCILLATOR/DIVIDER
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
VOO
Conditions
Supply voltage
With respect to Vss
Input voltage
Pd
Operating free-air temperature range
Ts tg
Storage temperature range
RECOMMENDED OPERATING CONDITIONS
Unit
V
VSS~VI~VOO
V
250
mW
Power dissipation
Topr
Limits
-0.3-9
--30 -70
°C
- 40-125
°C
(Ta~-30-70°C, unless otherwise noted)
Limits
Min
VOO
Supply voltage
VSS
Supply voltage
VIH
High·level input voltage
VIL
Low·level input voltage
VI
Oscillation input amplitude voltage
f
Unit
Pararneter
Symbol
Nom
4.75
Max
8.5
0
V
V
VOO 0 .5
V
0.5
0.3
V
Vpp
Input frequency with input N open
3.58
5.5
MHz
Input frequency with input N low
4.43
5.5
MHz
ELECTRICAL CHARACTERISTICS
(Ta~25°C, VDD~6.5V, Vss~ov, fIN=4.5MHL, unless otherwise noted)
Limits
Pararneter
Symbol
Test conditions
Min
VOO
Supply voltage
Ta=-30-70°C
100
Supply current
N and RESET inputs and outputs open
VIH
High·level input voltage
VIL
Low·level input voltage
VOH
High·level output voltage
VOL
Low·level output voltage
IOH
High·level output current
VO=VSS
VO=VOO
Typ
4.75
Unit
Max
8.5
V
mA
V
Voo-O .5
0.5
V
V
Voo··0.5
0.5
V
mA
mA
-2
IOL
Low-level output current
RI
PulhJp resistance, N and RESET inputs
VI
Oscillation input arnplitude voltage
VOO=4.75V
0.3
Vpp
f MAX
Maximum operating frequency
VOO=4.75V
5.5
MHz
20
kQ
III
• MITSUBISHI
..... ELECTRIC
11-37
MITSUBISHI LSls
MS8478P,MS0121P,MS0122P
17-STAGE OSCILLATOR/DIVIDER
APPLICATION EXAMPLES
(t) Crystal Oscillator (with built-in feedback resistance)
4.75-S.5V
S
Voo
,-----.:5"-10SC IN
X'TAL
M58478P
OUT 1-1_ _
Vss
, GND
(2) External I nput Signal Connections
4.75-S.5V
INPUT SIGNAL
0---i
OSC IN
M58478P
OUT
APPROX. 1000pF
Vss
11-38
• MITSUBISHI
"ELECTRIC
MITSUBISHI LSls
MS8479P, MS8482P
CMOS COUNTER/TIMERS
DESCRIPTION
The M58479P and M58482P are electronic timer ICs
PIN CONFIGURATION (TOP VIEW)
developed by aluminum-gate CMOS technology. Use of
these ICs makes possible timer devices without mechanical
elements, which have reduced power dissipation, superior
reliability, and higher noise immunity. The M58479P is
specifically designed for high noise immunity while the
M58482P particularly features low power dissipation.
DO
(7.4-9V:M 58479P)
3-9V:M58482P
0FSR~~~l~~~
AD J
_
ZD
2
ZENOR DIODE
::C~L::~{:::: :
FEATURES
•
V
(ov) Vss
PRECISE
OUTPUTS
Low power dissipation
M58479P: 2mW (typ), 7.5mW (max)
053- 5
M58482P: 200pW (typ), 750pW (max)
RESET INPUT
•
•
Superior noise immunity
Single power supply with a zenor diode
•
•
Internal RC oscillator
Precise oscillation frequency regulating capability
•
•
Extremely broad time-delay range (50ms~4800h)
Time-delaysettableto 1 0, 60,or 600timesfundamental
RESET -
l~n~l(j+
6
7
.....___
TNH __
}
..1
DIVIDING RATIO
SELECTIVE INPUT
FOR COUNTER
Outline 14P4
time (1024 times oscillation period)
•
•
•
M58479P has automatic-reset function during power
FUNCTION
engagement
These devices make possible extremely long clock perform-
Built-in reset and inhibit functions
Residual time display possible by adding Mitsubishi's
M53290P and M53242P IC
ance, by counting pulse signals from the RC oscillator. It
has precise oscillation frequency adjustment, automaticreset, reset, and inhibit functions.
There are three outputs.
When the time duration is up,
APPLICATIONS
OUT1 turns from low to high and OUT2 from high to low.
•
OUT3 can be connected to M53290P and M53242P TTLs
for residual time display.
Electronic timer or counter with broad time-delay range
(50ms'. . .A800h)
BLOCK DIAGRAM
DIVIDING RATIO SELECTIVE INPUT
FOR COUNTER
~
Ell
D1 D2
OS 1 3
OSCILLATION
INPUT/OUTPUTS
OUTPUT
CIRCUIT
OS 2
{
OS3
PRECISE
OSCILLATION
FREQUENCY
ADJUSTMENT
14
----~----~1
'-------{13
INH
RESET
INHIBIT
INPUT
RESET
INPUT
• MITSUBISHI
"ELECTRIC
Voo (7.4- 9 V:M58479P)
3 - 9 V : M 58482P
Vss (Ov)
ZD
ZENOR DIODE
11-39
MITSUBISHI LSls
MS8479P, MS8482P
CMOS COUNTER/TIMERS
Counter
FUNCTIONAL DESCRIPTION
Voltage Regulator
This counter consists of an ll-stage 112 frequency divider,
A zenor diode is on-chip, making it easy to obtain a
a 2-stage 1/10 frequency divider and a l-stage 1/6 frequency
constant voltage regulator circuit. Since the zenor diode
terminal (ZD) is independent of the power terminal (V DD ),
divider. As shown in the .table below, timer duration can be
changed by varying the number of pulses counted according
it can be used as a constant voltage power supply for the
to the combination of the input levels on terminals Dl and
total system.
D2.
Oscillator
D2
Number of pulses
counted
Time delay
Typical time
delay applied
Oscillation is obtained by connecting an external resistor
D1
(feedback resistor RFcl between terminals OSl and OS3
and an external capacitor (oscillation capacitor CFC )
H
H
1024
T,
L
H
1024 X 10
T, X 10
between terminals OSl and OS2. The values of the external
H
L
1024X10x6
T,X10X6
1h
L
L
1024X10X6X10
T,XlOx6x10
10h
resistor and capacitor can then be changed to vary the
oscillation period and thus change the time delay. Oscilla-
1 min
10min
Where, T,=ToX1024
To is the value obtained from equation (1)
tion period To is obtained by the following equation:
J
I
V TR
To = - R FC· C FC t n V DO + V BE
+
In
I
VOO-VTR
1
V DO
V BE J ... ( )
+
Where,
R Fc : Resistance of external resistor
CFC : Capacitance of external capacitor
V TR : Transition voltage of the first inverter in the
Output Circuits
The chips have three outputs: OUTl changes from low to
high and OUT2 from high to low as soon as the time
duration is up. Either can be used to drive a transistor by
connecting it to the transistor base. OUTl can drive a
thyristor when connected to the thyristor gate.
OUT3 is an open-drain output with period 1/8 of the
oscillation circuit
V DD: Supply voltage
V BE : Forward rising voltage of the diode in terminal
OSl (O.3-0.7V)
time delay, and can be used to drive a TTL in a separate
(5V) power supply line. Thus, if a M53290P counter and a
M53242P binary-to-decimal decoder are connected to
Automatic-Reset Function
OUT3, with their output connected to a light-emit!i~g
The M 58479 Phas a power-supply voltage-detection ci rcuit
on-chip, so that the counter is automatically reset by the
diode, residual time will be displayed on the LED. When
rising edge of the supply voltage when power is turned on.
Fine Adjustment 'of Oscillation Period
not in use, OUT3 should be connected to Vss.
The reset is then released, making the oscillator ready to
A variable resistor can be connected between terminals
function and the counter ready to start counting.
ADJ and V ss , enabling pJecise adjustment of the period of
The M58482P can also be provided with the same
automatic-reset function by connecting capacitor between
the oscillator. However, when not used for fine adjustment,
ADJ should be connected to Vss.
terminals RESET and Vss.
Reset Function
When the RESET input turns low (Vss), oscillation of the
oscillator can be stopped and the counter reset.
Inhibit Function
When terminal INH turns low (Vss ) while the timer is in
action, the oscillation halts. When input IN H is turned high
or returned to OPEN afterwards, it starts to count residual
time.
11-40
• MITSUBISHI
.... ELECTRIC
MITSUBISHI LSls
MS8479P, MS8482P
CMOS COUNTER/TIMERS
ABSOLUTE MAXIMUM RATINGS
Symbol
Conditions
Parameter
VOO
Supply voltage
V,
Input voltage
Pd
Maximum power dissipation
Topr
Operating free-air temperature range
Tstg
Storage temperature range
With respect to V SS
limits
Min
VOO
Supply voltage
Izo
Zenor current
I
I
Nom
Max
M58479P
7.4
9
M58482P
3
9
V
10
mA
Feedback resistance
0.005
10
Oscillation capacitance
0.001
1
.uF
RFC
Resistance for fine-adjustment of oscillation frequency
V ,H
High·level input voltage, RESET, INH, 0 1 , O2
V,L
Low-level input voltage, RESET, INH, 0 1 , O2
0
0. 7XV OD
Zenor voltage
100
Supply current
-30-75
°C
-40-125
°C
MQ
100
kQ
VOO
VOO
V
0
0. 3XV OD
V
0
(Ta=25°C, unless otherwise noted)
Parameter
VZO
mW
V
RFC
Symbol
V
250
Unit
CFC
ELECTRICAL CHARACTERISTICS
V
(Ta = -30 -75°C. unless otherwise noted.)
Parameter
Symbol
Unit
VSS~VI~VOO
Ta=25°C
RECOMMENDED OPERATING CONDITIONS
limits
-0.3-9.5
limits
Test conditions
M58479P
Typ
IzO=2mA
7.4
8.2
9
V
Izo=10mA
7.5
8.2
9
V
0.25
1
mA
100
.uA
Voo=7.5V, CFc=O.Ol.uF, RFC= 1 MQ
RAOJ=OQ, Input/output open
M58482P
VOO=7.5V, CFC=O,Ol.uF, RFC= lMQ
25
Max
RAOJ = OQ , Input/output open
VRE
Supply voltage at the time of
automatic-reset release
VTR
Transition voltage of first Inverter in the oscillator
RI
Pull-up resistance. RESET. INH. Dl. 02
Inputs
IOH
High-level output current. OUTl and OUT2 outputs
VOO=7 .5V, VO=OV
IOL
Low·level output current. OUT1. OUT2. and OUT3 outputs
VOO=7 .5V, VO=7 .5V
IOZH
Off-state output current. OUT3 output
VOo=7 .5V. Vo=7 .5V
IOL
Low-level output current; OUT1.0UT2. and OUT3 outputs
VOO=7 .5V, VO=O .4V
1.6
IOL
Low·level output current. OUT1. OUT2. and
OUT3 outputs
VOO=4 .5V. VO=O .4V
1.6
VOL
Low-level output voltage: OUT1. OUT2. and OUT3 outputs
---
M58479P
VOO=7 .5V, RAOJ=OQ
M58479P
M58482P
M58482P
Unit
Min
VOO=7.5V
• MITSUBISHI
"ELECTRIC
3.1
5.4
2.9
4.8
10
20
30
25
50
75
5
10
10
20
V
V
kQ
kQ
mA
mA
1
.uA
mA
mA
0.1
V
11-41
MITSUBISHI LSls
M58479P, MS8482P
CMOS COUNTER/TIMERS
APPLICATION EXAMPLE
12V
5V
~;r
-{~-
z:~+
11
113
14
7.»
VSS
ZO
VOO
.~
OSl
~
RO(9)1
j~RFC
OUT1
M58479P
~»
-10
RESET
INH
01
GNO
M53290P
j..t+
'2
~
6
RO(O)1
Tso
B
9
1---1
11
C
0
8
11
13
C
14
B
16
1
2
2
3
3
4
4
1/ II
II
• MITSUBISHI
.... ELECTRIC
5
~
.. ~
~
~
.. ~
GNO
~
II
~
7
6
6
5
~~
'-:77
15
A
M53242P
Vee
~~
12
0
/'
11-42
P;-
:>
~
;
~
7,77
A~
RO(O)2
02
.t t r
rs-
T---'
5 Vee
t1
1
0S3
2 AOJ
RAOJ/~
RO(9)2
14
4 OS2
5
TA
OUT3 12
~
II
.4 ~
7
;;
9
io-
.. 1/
II
~~
~
n
MITSUBISHI LSls
M58480P,M58484P
30-FUNCTION REMOTE-CONTROL TRANSMITTERS
DESCRIPTION
PIN CONFIGURATION (TOP VIEW)
The M58480P and M58484P are 30-function remotecontrol transmitter circuits manufactured by aluminumgate CMOS technology for use with in television receivers,
(OV)
Vss
OSCILLATOR
IOSCIN
l
audio equipment and the like, using infrared for transmission. They convey 30 different commands on the basis of
a 6-bit PCM code. In the M58480P, entry priority is given
Voo
-+
2
OSCOUT +-
3
(2.2-8V)
OUTPUT
to the first key pushed, while in the M58484P each key has
an assigned priority. These transmitters are intended to be
used in conjunction with an M58481, M58485P or
KEY INPUT
M58487P receiver.
SCANNER
OUTPUT
FEATURES
•
•
Single power supply
Wide supply voltage range: .......................... 2.2V-8V
•
Low power dissipation:
Non-operating condition (V DO = 3V) : ..... ·3nW (typ)
Outline 16P4
:····.·3J.1W (max)
•
•
On-chip oscillator
Low-cost LC/L or ceramic oscillator used in determining
reference frequency (480 kHz or 455 kHz)
The M58480P and M58484P transmitter circuits for infra-
Low external component count
Low transmitter duty cycle (3.6%) for minimal power
generator, a scanner, a key-in encoder, an instruction
consumption
decoder, a code modulator, and an output buffer. With
APPLICATIONS
by 6-bit PCM code. Oscillation is stopped when none of
•
the keys are depressed, to minimize power consumption.
•
•
FUNCTION
red remote-control systems consist of an oscillator, a timing
a 6 x 5 keyboard matrix, 30 commands can be transmitted
Remote-control transmitters for TV and other applications
BLOCK DIAGRAM
I
~voo
r
,v)
V% (OV)
INSTRUCTION DECODER
KEY-IN
ENCODER
KEY INPUT
(2.2-
TIMING
GENERATOR
CODE
MODULATOR
OSCILLATOR
OUTPUT
BUFFER
SCANNER
l
lhN INPUT/OUTPUT OUTPUT
•
MITSUBISHI
J-..II!'LII!'CTRIC
~
~HANNEL
CONT OL OUTPUTS
MITSUBISHI LSls
MS8481P
30-FUNCTION REMOTE-CONTROL RECEIVER
FUNCTIONAL DESCRIPTION
Instruction Decoder
Oscillator
The instruction decoder starts to function after receiving
the same instruction code three or more times in succession
from the demodulation circuit.
Table 1 shows the relations between the reception code
and instruction function. To prevent spurious operation,
there is no code 000000.
As the oscillator is on-chip, oscillation frequency is easily
obtained by connecting an external LC network or ceramic
resonator between the OSC IN and OSC OUT terminals.
Figs. 1 and 2 show typical oscillators.
Fig.1 An example of -an oscillator (using ceramic resonator)
CERAMIC RESONATOR· SFB455R OR
CSB455A
(MADE BY MURATA
SEISAKUSHOI
M58481P
'--_..,......_ _ _O_S_C~O_U_T~ CLI.
C lO
: 50-150pF
Fig. 2 An example of an oscillator (using LC network)
L
M58481P
CLI.
: 2.5mH
ClO: 90pF
C
: 0.1,uF
Reception Signal Input Circuit and Demodulation
Circuit
The reception signal caught by the photo detector is amplified in the amplifier and added to the SI, where it is
converted into a pulse signal in the input circuit to be sent
to the demodulation circuit. In the demodulation circuit,
the pulse interval of the pulse signal is judged and then
converted into the digital code to be sent to the instruction
decoder.
SI is applied as amplified, either through a capacitor
coupling (Fig. 3) or directly as a pulse signal (Figs. 4 and 5).
A Schmitt trigger circuit is provided in the SI input circuit
for preventing spurious operation due to noise.
Fig. 3 SI input waveform (when applied through a capacitor coupling)
Above15U~~~~~J~ _
Above
15~~~~
~~~~---]~_
_
~~~ijijt __ ]U
Fig. 4 SI input waveform (when applied directly)
voo
~~~------~~
Vss~U~L--..JUI
I------L
.
Fig. 5 SI input waveform (when applied directly)
:::~~[::@
11-48
Imnr
Table 1 Relations between reception codes and instructions
Reception code
Remarks
Function
0, 02 03 04 0 5 06
1
0
0
0
0
0
CH UP
Channel up
0
1
0
0
0
0
CH DOWN
Channel down
1
1
0
0
0
0
VO UP
0
0
1
0
0
0
va
1
0
1
0
0
0
BR UP
0
1
1
0
0
0
BR DOWN
DOWN
1
1
1
0
0
0
CS UP
0
0
0
1
0
0
CS DOWN
1
0
0
1
0
0
MUTE
0
1
0
1
0
0
VO( (13)
Analog control
Sound mute on/off
I
No=,Ii,""" of ,",fog CO"""
1
1
0
1
0
0
BR( (12)
0
0
1
1
0
0
CS( '/2)
1
0
1
1
0
0
CALL
0
1
1
1
0
0
POWER ON/OFF Power on/off
0
0
0
0
1
0
CH 1
1
0
0
0
1
0
CH 2
0
1
0
0
1
0
CH 3
1
1
0
0
1
0
CH 4
0
0
1
0
1
0
CH 5
1
0
1
0
1
0
CH 6
0
1
1
0
1
0
CH 7
1
1
1
0
1
0
CH 8
0
0
0
1
1
0
CH 9
1
0
0
1
1
0
CH 10
0
1
0
1
1
0
CH 11
1
1
0
1
1
0
CH 12
0
0
1
1
1
0
CH 13
1
0
1
1
1
0
CH 14
0
1
1
1
1
0
CH 15
1
1
1
1
1
0
CH 16
Output CALL on/off
Channels selected directly
Key Inputs
16 different instructions can be input by a 4 x 4 keyboard
matrix consisting of inputs h -16 and scanner outputs
(jJA-(jJE. Protection is also available against chattering within 10ms.
Entry priority is given to the first key depressed, and
subsequent key entry is not allowed unless all keys are
released. When two or more keys are depressed at the same
time, scanner outputs may short-circuit, disabling all functions.
While one of the keys is depressed, instructions from the
transmitter are ignored.
• MITSUBISHI
.... ELECTRIC
MITSUBISHI LSls
M58481P
30-FUNCTION REMOTE-CONTROL RECEIVER
Table 2 Relations between keyboard matrix and instructions
~ Scanner output
A,,-,1>O. Protection is also available against chattering within 10ms.
~~[---]~_
~~~ij~[ ____] r
higher priority effective. For the scanner output, priority
nnr----n n
vss---.J~~l---..JUI
_
:::~_-_]
is given in the order .of 1>A, 1>8, 1>C, and 1>0, and in the
order of
n~w-----lliL
I~~l
It, 12 , and 13 if scanner output is the same. Wh~n
two or more keys are depressed at the same time, scanner
outputs may short·circuit, disabling all functions.
While one of the keys is depressed, instructions from the
Fig. 5 SI input waveform (when applied directly)
11-52
} Normalization of analog control
more than two keys at the same time makes the key with
Fig. 4 SI input waveform (when applied directly)
Voo
Sound mute on/off
As entry priority is given to each key, depression of
tor coupling)
Above
Analog control
0
0
The reception signal caught by the photo detector is am-
Remarks
Function
I_Jr
transmitter are ignored.
Table 2 shows the relations between the keyboard
matrix and the commands.
• MITSUBISHI
.... ELECTRIC
MITSUBISHI LSls
M5848SP
29-FUNCTION REMOTE-CONTROL RECEIVER
Table 2 Relations between keyboard matrix and instruc-
Table 3 Relations between channel number and address
output
tions
~t
Key Input
11
12
13
4-
+- 10
---+ 11
+-
12
---+
13
---+ 14
tiC
---+
15
EACRlOO~KC~~~~3iCLOCK
4--
16
1~~~~/~u~~0~
•
Automatic bandswitching
Band skip function
•
Digital AFT (Automatic Fine Tuning) function
DATA I/O .... 17
EAROM MODE [
CONTROL
OUTPUTS
•
Frequency fine adjustment function
•
AFT on/off data is memorized in EAROM for each
C 1 4-- 18
C2 +- 19
C 3 +- 20
CHANNEL
POSITION
DISPLAY
OUTPUTS
(11-13V) VDD
channel position
•
SCANNER
OUTPUTS
9
channel number display
•
ACTUAL
CHANNEL
POSITION
NUMBER
DISPLAY
OUTPUTS
BAND CONTROL{ Bl .-.
INPUT/OUTPUTS
B2"
Used in conjunction with the M51251P linear sensor and
M5G1400P EAROM, it is possible to configure a fully
OSCll
42 •• OSC OUT} lATION
CIRCUIT
41 4--+ OSC IN
INPUT/
OUTPUT
(OV) Vss
Outline 42 P 1
Direct connection with a remote controller LSI such as
the M58485P or M58487 AP
•
Direct 16 (or 12) channel selection
•
Last channel memory function
APPLICATIONS
Electronic tuning
systems for TVs, VTRs, and other
electronic equipment.
BLOCK DIAGRAM
Ctx'i:~~~~~~~~Ji
CEX
2}----n;~===.='+----------__;:::::::::::I::=;==~~;;;;:~~:;:::=~17 DATA I/O F~p~~~oB~l~T
POWER-ONI~~BH AC 15
16 CLOCK EAROM CONTROL
18 C'}
CLOCK OUTPUT
19 C2
EAROM MODE
20) C
CONTROL OUTPUTS
3
,j:;
CHANNEl{
CH UP 6
CONTROL
CH DOWN 7
INPUTS CH RESET 8
1
I
10
D-A OUT
6~~~~~ VOLTAGE
3 Bl} BAND CONTROL
4 B2
INPUT/OUTPUTS
5 B3
9 MUTE MUTING CONTROL
OUTPUT
400,}
3902
3803
37 04
ACTUAL CHANNEL AND
CHANNEL POSITION
NUMBER DISPLAY
OUTPUTS
14
13
-~OSC IN OSC OUT UP DOWN TIME BASE Voo
VSS
~
CIRCUIT
INPUT/OUTPUT
~
(11-13V)(OV)
CONTROL
INPUTS
• MITSUBISHI
.... ELECTRIC
11-55
MITSUBISHI LSls
M58486AP
VOLTAGE SYNTHESIZER
FUNCTION
The M58486AP voltage synthesizer, when used in conjunction with the M51251P linear sensor and M5G1400P
EAROM, enables the configuration of a completely electronic tuning system without the use of any mechanical
parts.
The main functions include fully automatic search,
sequentially automatic search, direct selection of either 12
or 16 channels, automatic bandswitching, a band skip
function, digital AFT (Automatic Fine Tuning), fine
tuni ng, last channel memory, channel position tab display,
channel position number display, and actual channel
number display functions.
In addition, direct and sequential channel selection from
a remote controller as possible.
no commands will be input. However, it is possible to input
FAM or CH LOCK in combination with another key.
Table 1 shows the relationships between these matrices
and the command functions.
Table 1 Matrix and Command Functions
~
A '" 1>0,
key inputs 11 '" 14 and K1 '" K3 . 16-channel position
selection can be achieved by using the 4x4 matrix formed
by 1>A '" 1>0 and 11 '" 14 . In addition, the 4x3 matrix
formed by 1>A '" 1>0 and K1 '" K3 enables the input of 12
commands.
If two or more of the keys are depressed simultaneously,
11-56
VH
~----I
--- I ---------
VL ____ ~----L - - - - - - I
I
I
I
UP
II
I
: I
I
I
I
II
I:
I
I
I
I
I
I
-
H-~---I
L
DOWN :
-----------!l!--i--I
I
Fig. 3 Relationship of AFC signal to UP and DOWN inputs
• MITSUBISHI
"ELECTRIC
MITSUBISHI LSls
M58486AP
VOL TAGE SYNTHESIZER
Band Input/Outputs (B1 ,....., B3)
The M58486AP system is provided with three bands. An
electronic tuner is controlled by these three band inputs/
outputs and D-A OUT.
As shown in Table 2, these bands correspond to the TV
broadcast frequency bands.
Note, however, that for automatic writing of data into
EAROM in the search mode, AFT deta is on.
14 bits
14-bit up/down counter data
8 bits
2-digit BCD data of channel number counter
Ba'nd control binary data
2 bits
1 bit
AFT on/off control data
UP
Band
61
VHF low band
62
VHF high band
63
~
Broadcast frequency band
I
DOWN
UHF
TIME
Search Modes
The search is the function searching automatically the video
signal and writing of the required data into the EAR OM.
The search function is controlled by the UP, DOWN, and
TIME BASE tuning control inputs. Search functions will be
described using Fig. 3,4, and 5.
When search is begun, as up signal is applied to the
14-bit up/down counter, and the analog output of the D-A
converter increases (sweeps).
As shown in Fig. 3 and 4, when the signal reaches a
certain point, the UP input changes to high. Next, if the
DOWN input goes high within 50ms after the UP input goes
low, the sweep is ended and the digital AFT is enabled. If
DOWN doesn't go high within 50ms, this is taken as an
indication that the signal was not a video signal, and the
sweep is continued.
Digital AFT is controlled by both the UP and DOWN
inputs. When UP is high, the up signal is applied to the
up/down counter and the analog output of the D-A
converter increases. When DOWN is high, the down signal is
applied to the up/down couner and the analog output of
the D-A converter decreases. The up/down speed of digital
AFT is 1/16 of the up sweep speed.
Digital AFT is ended after 200ms, after which the TIME
BASE input is examined. If TIME BASE is low, it is taken
as an indication that the signal is not a video signal and the
sweep operation is restarted. If TIME BASE is high, the
signal is taken as a video signal and the required data is
written into the EAROM at the specified address. For this
operation, the EAROM address is determined by the
channel position and the data written is as follows.
r ____________
L__
6ASE~ --1'
-;.; i-1----------- +----1
Three band inputs (B 1 ,....., B3) are provided on the
M58486AP, the output corresponding to the currently
selected band being high, with all other band outputs low.
Thus, by connecting transistor and LED with currents to
these outputs a display of the selected band can be
implemented.
If a particular band pin is shorted to Vss that band will
be skipped during the search (band skip function).
__________________ _
SWEEP
E
200 ms
5 fmsWITHIN
'I'
!
1
";"WRITE THE
t ~~l~l~1~
MONITOR TIME
BASE INPUT
Fig. 4 UP, DOWN, TIME BASE inputs in the search mode
Fig. 5 A flowchart of the search method
• MITSUBISHI
..... ELECTRIC
11-57
MITSUBISHI LSls
MS8486AP
VOLTAGE SYNTHESIZER
TUNING VOLTAGE = OV
BAND = B1
CHANNEL POSITION
NUMBER M = 1
ACTUAL CHANNEL
NUMBER N = 1
Fig.6 A flowchart of fully automatic search (SEARCH or V-SEARCH)
Fully Automatic Search
Fig. 6 shows the flowchart of the fully automatic search.
When SEARCH or V-SEARH key is input, the D-A
converter analog output is set to the lower end of B1 and
the channel position number and actual channel number are
both initialized to 1.
After initialization, search begins and when a video
signal is captured, the required data is automatically written
into the EAROM, the channel position number and actual
channel number being incremented by 1, after which the
search is restarted.
In this manner, when tuning voltage goes to the upper
end of band 83 or when all 16 (or 12) channel positions are
written, the EAROM data corresponding to channel position number 1 (channel position 1 is selected) is read, and
the fully automatic search operation is completed. If the
upper end of band B3 is reached before all 16 (or 12) channels have been searched, the data at the EAROM addresses
corresponding to reset channel position is erased. If these
erased channel positions are selected, the D-A converter
analog output is set to the lower end of band B1, the actual
channel number is set to 0, and the AFT function is turned
off.
11-58
When U-SEARCH key is input, the operation is exactly
the same as the above described SEARCH or V-SEARCH
except that initialization to the lower end of band B3 is
performed and the search ends at the upper edge band B2.
Also, during fully automatic search, no key command
can be input.
Sequentially Automatic Search
For sequentially automatic search, the channel position and
actual channel number are the currently selected channel
position.
When V-SEARCH key is input, search begins from the
current position if the current band is B1 or B2, and from
the lower end of band B1 if the current band is B3.
The search begins and when a video signal has been
captured, the required data is automatically written into
the EAROM, the search mode is cancelled, and the search is
completed. When the upper end of the B2 band is reached,
the tuning voltage output returns to the lower end of the
B1 band and search continues.
When U-SEARCH key is input, search begins at the
present location if the current band is B3. If it is B1 or B2,
it begins at the lower end of band B3. The search method is
exactly the same as for the above described V-SEARCH
• MITSUBISHI
"ELECTRIC
MITSUBISHI LSls
M58486AP
VOLTAGE SYNTHESIZER
except that when the upper end of band B3 is reached, the
tuning voltage returns to the lower end of band B3.
When SEARCH key is input, search begins from the
current location. For SEARCH, when the upper end of
band B3 is reached, the tuning voltage returns to the lower
end of band B1.
During sequentially automatic search, pressing channel
selector keys cancels the search mode, ending the search
and resulting in input of the channel selection command.
Search Speed
The tuning voltage rate of change varies between bands and
within bands such that the search speed with respect to
frequency is virtually constant over the entire range.
Because of the time constant associated with the
integration circuit connected to the Of A OUT output, time
delays occurs during the sweep. However, to compensate
for this when UP and TIME BASE inputs are both high, the
search speed is dropped to 1/16 of the sweep speed.
Table 3 shows the search speed for all bands without this
reduced speed mode.
Table 3 Search Speed for Each Band
~
81
Tuning voltage
82
83,84
1.16s
2.31 s
'/4-'/2
0.58
1. 16
'/2-1
0.58
1. 16
4.61
Total
2.32
4.63
13.83
0-1/4
9.22s
Note 1. The reference oscillator frequency is 455kHz.
2. The tuning voltage is given normalized to a value of 1.
SWitching between fully automatic search and sequentially automatic search is accomplished by the FAM
command as shown in Table 1. By using a switch,
connecting the ¢c pin, with the K3 pin results in fully
automatic search while opening this connection results in
switching to sequencially automatic search.
If the F AM command is attempted during a search, the
command will not immediately be executed. After the
search mode has been cancelled it will be input and the
appropriate search mode, either fully automatic or automatic sequencial search, will be selected.
• MITSUBISHI
.... ELECTRIC
11-59
MITSUBISHI LSls
MS8486AP
VOLTAGE SYNTHESIZER
(a) FOR V-SEARCH
(b) FOR U-SEARCH
(e) FOR SEARCH
Fig.7 Shows the flowchart of sequentially of search.
Channel Selection Mode
When either a channel selection key is depressed or a
channel selection command is input from a remote control
receiver (described below), the data at the EAROM address
corresponding to the selected channel position is read.
After the read data is set in the up/down counter, if the
AFT control data read is on, 16 down pulses are applied,
causing the up/down counter to count down and cause a
corresponding output from the D-A converter. This is to
enable pull-in at the optimum positic;>n of the video signal,
using the digital AFT and linear AFT to be descfibed next.
If the AFT control data read is on, after 100 ms digital
AFT is enabled. In addition, when 100ms has elapsed, the
AFT output goes high and linear AFT is enabled. When the
AFT control data is off, both digital and linear AFT
functions are disabled.
11-60
Tuning Voltage Fine Adjustment (D-A UP, D-A DOWN)
By pressing the D-A UP and D-A DOWN key, it is possible
to adjust the D-A converter analog output (that is the
tuning voltage).
After channel selection, pressing the D-A UP or D-A
DOWN keys turns AFT off and disables both digital and
linear AFT functions. After this, the up or down signals are
applied to the up/down counter and the D-A converter
analog output changes. The rate of this change is 1/128 of
the sweep speed, allowing sufficient fine adjustment.
When the key is released writing into the EAROM
begins. At this time, the AFT on/off data is written as off.
• MITSUBISHI
"ELECTRIC
MITSUBISHI LSls
M58486AP
VOLTAGE SYNTHESIZER
EAROM Input/Output (CLOCK, C1, C2, C3, DATA I/O)
This system makes use of an M5G1400P as an EAROM.
To control the M5G1400P, the M58486AP is provided
with a reference clock ( "'14kHz) output clock, outputs C 1 ,
C2 , and C3 used to specify the mode, and a data
input/output DATA I/O.
These inputs and outputs are controlled by the EAROM
control circuit. The clock output is fixed at the Voo level
at all times except during memory read and write operations.
AFT Output
The AFT pin is connected to the AFT on/off pin (pin 15)
of the M51251P, and is used to on/off control linear AFT.
When the AFT output is high" linear AFT is enabled. When
it is low or high impedance (open) linear AFT is disabled.
Table 4 summarizes the AFT output for the various states.
display the actual channel number using a two-digit
seven-segment display. Fig. 9 shows an example of timing
for the outputs 0 1 '"'" 0 4 used to display the actual channel
number.
Table 4 AFT Outputs for the Various Modes
Fig. 8 Timing example for outputs P1"'P4 and ¢A"'¢O
(channel position = 7)
Mode
AFT output level
Search mode (during sweep)
L
Search mode (during the 200ms that digital AFT
is enabled)
Z
Channel selection mode (with linear AFT on)
H
Channel selection mode (with linear AFT off)
Z
Note 1. 'Z' indicates high-impedance (open)
Last Channel Memory
In this system when the power supply is applied, a last
channel memory function selects the last channel position
that was selected before the power supply was last
removed.
This function is controlled by the last channel memory
circuit such that when a channel is selected the data for the
selected channel position is written into a specified address
in the EAROM. Each time a channel is selected the data
contents are updated so that the last channel selected
before power is removed is always stored. When the power
is applied, this data is read from the EAROM and used as
the initial channel position selected.
Channel Position Display (P 1 '" P4 )
By connecting transistors and LEDs to the 4x4 matrix
formed by the PI '" P4 and ¢A '" ¢o outputs, a 16-channel
position display can be configured.
The display repetition frequency is 45Hz and the duty
cycle is 23.5%. Fig. 8 gives an example of output timings.
Note that when not used pins should be connected to Voo.
Channel Number Display (01 '" 02)
The output 0 1 '" 0 4 provide a two-digit (0 '" 99) BCD
output of the actual channel number. The upper and lower
digits are output under the control of the ¢o and ¢B scan
signals. Thus, by using a BCD seven-segment decoder (for
example, the M53247P or equivalent), it is possible to
¢A
¢s
¢c _ _;--....
¢D __~__~~rI~~r-~~r-l~~~~~rI~~~_
P1
--~+-----~~-----~~------r-+-
Pz ___
P3
P4
~~
____
~~
____
~+-
____
~-+_
I
::~____~
---~+:----~~I-----r:-+-----~~I--
~-2.25ms ,:~
I,
~
- 530,1.1 S
~
~
~
~
TIME DISPLAY
IS OUTPUT
When the 0 1 '" 0 4 outputs are used to display the
channel position number in binary form the ¢A and ¢c
scan signals are used for timing of the otuputs. For the
channel positions 1 '" 16, the 0 1 '" 0 4 outputs are 0 '"
15. Therefore, the channel position number can be
displayed using seven-segment display elements. Fig. 9
shows a timing example of the outputs 0 1 '" 0 4 used to
display the channel position number. The outputs 0 1
through 0 4 use N-channel transistors in open drain configuration. When not used they should be connected to the Vss
pin.
¢s
¢ c -+--;;.-....
¢o
01
02
Fig. 9 Timing example for outputs 01"'04 and ¢A "'¢o
(Actual channel number setting line 79
Channel position number 7)
• MITSUBISHI
"'£l£CTRIC
11-fl1
MITSUBISHI LSls
MS8486AP
VOLTAGE SYNTHESIZER
Actual Channel Number Control Inputs (CHN 10, CHN 1)
When CHN 10 key is input, the upper digit of the actual
channel number is incremented by 1, cycling back to 0
after reaching 9. In the same manner, when CHN 1 key is
input, the lower digit is incremented by 1. Therefore, by
using these inputs, the actual channel number can be
changed with respect to the channel position, and by using
the STORE command described below, the proper corresponding channel numbers can be selected.
Channel Lock Input (CH LOCK)
By using the input combination of the key input K3 and
the scan signal ¢s, the CH LOCK command is input. This
command prohibits the CHP1 '" CHP16, CHP-UP, AND
CHP-DOWN keys commands as well as the remote control
CH-UP, CH-DOWN, and CH-RESET. This command is
independent of any other key commands and can be input
simultaneously input with any command except the channel selection commands CHP1"'CHP16.
Channel Position Gontrollnputs (CHP-UP, CHP-DOWN)
When either CHP-UP or CHP-DOWN key is input, the
contents of the address counter are incremented or decremented by 1, the channel position display changing accordingly. But data is not read from the EA ROM, so the D-A
converted analog output, band, AFT output and actual
channel do not change.
Number of Channels Selection Input (CEX)
The CEX input is provided with a built-in pull-up resistance
and when at the high level (or open), the M58486AP for 16
channels. When it is at the low level the M58486AP
accommodates 12 channels.
When these commands are input, the channel position is
changed, and the STORE command described below is
input, data is written into the EAROM at the address
corresponding to the displayed channel position. This
enables, for example, such copying operations as writing
the same data in position 3 as stored in position 1.
EAROM Write Command (STORE)
When the STO R E command is input, data is written into
the EAROM at the address corresponding to the currently
displayed channel position. This STORE command is used
to change the actual channel number and to perform
memory copying operations.
Audio Control Output (MUTE)
In the search mode or channel selection mode, the MUTE
output changes to a high level, enabling the muting
function which lowers the sound level to the minimum
level. This output is normally low.
Power-on reset (AC)
By connecting a capacitor between the AC pin and the Vss
pin, the power-on reset function is enabled upon applying
power to the M58486AP.
When the power-on reset operates, the last channel
memory function is enable the channel position selected
before the power was removed, is selected.
Remote Control Inputs (CH UP, CH DOWN, CH RESET)
If the CH UP, CH DOWN, and CH RESET inputs are
connected to the corresponding pins on, for example, a
remote control receiver device such as the M58485P or
M58487 AP, direct remote control of channel selection,
channel up, and channel down functions is possible.
11- 62
• MITSUBISHI
.... ELECTRIC
MITSUBISHI LSls
M58486AP
VOL TAGE SYNTHESIZER
ABSOLUTE MAXIMUM RATINGS
Symbol
Conditions
Parameter
Limits
Unit
VOO
Supply voltage
VI
Input voltage
Va
Output voltage
Pd
Power dissipation
Topr
Operating temperature
-30-70
"C
Tstg
Storage temperature
-40-125
"C
-0.3-15
V
VSS;;;;;W~;VOO
With respect to VSS
V
Vss;;;;; Va;;;;; Voo
V
300
mW
Ta=25"C
RECOMMENDED OPERATING CONDITIONS
Limits
Parameter
Symbol
Unit
Min
Typ
Max
VOO
Supply voltage
11
12
13
V
VIH
High-level input voltage
VOO-3
VOO
VOO
V
Vil
Low-level input voltage
0
0
3
fosc
Oscillation frequency
ELECTRICAL CHARACTERISTICS
V
455
kHz
480
kHz
(Ta=25"C, Voo=12V, Vss=ov, unlessotherwise'noted)
Limits
Symbol
Parameter
Test conditions
Min
Voo
Operational supply voltage
Ta = - 30-70"C, fOSC=455kHz
100
Supply current
fOSC=455kHz
RI
Pull-up resistance
CH UP, CH DOWN, CH
RESET, UP, DOWN, TIME 8ASE, CEX
RI
Pull-up resistance, AC
RI
Pull-down resistance, 1,-14, K,-K3
11
Unit
Typ
Max
12
13
V
0.5
6
mA
kQ
50
100
kQ
50
kQ
IOH
High-level output current, A - ¢>O
Vo=12V
5
10L
Low-level output currents. CH RESET. CH UP. CH DOWN
VO=12V
20
10ZH
Off-state output currents. CH RESET. CH UP. CH DOWN
VO=12V
10H
High-level output current.
10L
Low-level output current.
10H
8
Typ
Max
12
14
2
5
V
mA
kQ
20
va
va
Unit
mA
rnA
1
f.J.A
Vo= 0 V
-7
Vo=12V
7
rnA
High-level output currents. POWER ON/OFF. CALL. MUTE
VO= 0 V
-20
rnA
10L
Low-level output currents. POWER ON/OFF. CALL. MUTE
VO=12V
5
rnA
10H
High-level output current. IR
VO= 0 V
-15
mA
10L
Low-level output current. IR
VO=12V
5
rnA
(+) POWER SOURCE
APPLICATION EXAMPLE
12
VOD
11-68
• MITSUBISHI
;'ELECTRIC
rnA
MICROCOMPUTER SYSTEMS
MITSUBISHI MICROCOMPUTERS
PCA8S01G01,G02
MELCS 85/2 SINGLE-BOARD COMPUTER
DESCRIPTION
•
The PCA8501 is a general-purpose single-board computer
that is composed of a memory and an I/O interface around
the M5L 8085AP 8-bit microprocessor and fabricated on
a single 125 x 145mm printed circuit board. As it has been
designed so compactly in its dimensions, it may be easily
attached to the board currently used. There are two types
available: the PCA8501G01, which is implemented with
the M5L2114LP NMOS RAMs, and the PCA8501G02, is
implemented with the M58981S CMOS RAMs.
FEATURES
Type
Contents
PCA850lGOI
Consists of the single-board computer only
Two M5L2114LP NMOS RAMs are mounted for its RAM.
excluding both a battery backup circuit and a wait signal
generation circuit. and one M5L2716K EPROM is attached
separately.
PCA850lG02
Consists of the single-board computer only
Two M58981S CMOS RAMs are mounted for its RAM. including a battery backup cirCUit and a wait signal generation
circuit. and one M5L 2716K EPROM is attached separately
Internally contained 12 L timer: One of the following 8
timer outputs can be selected (1.6,us, and 0.1, 0.2, 0.4,
0.8, 1.6, 3.3 and 6.6ms).
•
•
Single 5V power supply
Compact dimensions (L xW x H): 125 x 145 x 17mm
APPLICATIONS
•
Personal computers
•
•
•
Small automatic testing or control equipment
Data-communication terminal equipment
Data loggers and data-collection equipment
•
Process-control equipment
•
Instrument monitoring controllers
FUNCTION
The PCA8501 is a highly reliable single-board computer
designed around Mitsubishi's M5L8085AP CPU (equivalent
to Intel's 8085A) and its LSI family. The 8-bit parallel
CPU is fabricated by the N-channel silicon-gate ED-MOS
process. The PCA8501 comes with 4K bytes of electrically
programmable read-only memory (EPROM) in the form of
•
A single-board computer comprised of the CPU, memory, I/O interface and a timer.
two M5L 2716Ks and 1K bytes of random-access memory
in the form of two M5L 2114LPs or two M58981Ss.
For its I/O ports, the PCA8501 contains two M5L 8255AP
programmable peripheral interfaces (PPI) providing 8
bits X 6 = 48 bits programmable ports.
•
•
Capacity of EPROM:
Capacity of RAM:
4K bytes (max)
1 K bytes
A timer circuit and a battery backup circuit (which is
available only for the PCA850G02) are mounted on the
•
Programmable I/O port:
48 bits (8-bit x 6)
board, allowing timer interrupt and memory backup.
• MITSUBISHI
.... ELECTRIC
12-3
MITSUBISHI MICROCOMPUTERS
PCA8S01G01,G02
MELCS 85/2 SINGLE-BOARD COMPUTER
OPERATIONS
As the timer IC is provided on the board, it enables
As soon as the power is applied, the M5L8085A CPU is
timer interrupt by means of the RST 7.5 or timer output to
reset by the power-on reset circuit and starts to execute
the external circuit.
the program from the address OOOO,a.
BLOCK DIAGRAM NOTATION
The low-order 8 bits of the address are multiplexed with
They are
Name of block
Function
latched in the address latch circuit so as to compose an
CPU power-on
reset
Execution is carried out in accordance with the contents of a
program System reset signal is generated when the power IS
turned on.
Address latch
circuit
Latches the low-order 8-bit address signal on the multiplexed
data bus.
Address
decoder
Decodes the high-order bits of the address. and generates the
memory and I/O chip select signals.
EPROM
Both erasable M5L 2716K and M5L 2708K can be used.
data and sent out through the CPU terminals.
address bus with the high-order 8 bits of the address.
If an external extension signal is used, it makes easy the
external expansion of memory capacity for both ROMs and
RAMs.
Use of CMOS RAMs enables memory backup by means
of the battery backup circuit and batteries so that the
RAM
Allows the use of the M58981S CMOS RAMs other than the
M5L 2114LPs. which enables battery backup.
RAM battery
backup
circuit
Enable maintaining the contents of the memory by the backup
circuit with batteries in use. when the CMOS RAMs are used.
I/O port
(PPI)
It is a programmable I/O interface consisting of 48-bit I/O
signal terminals. corresponding to six 8-bit I/O ports.
Timer
This generates 7 different signals after dividing the clock signal
from the CPU. allowing RST 7.5 interrupt by using a jumper wire.
Wait signal
generation circuit
~~~no~hee ~~c~\i~eMs (f~i~n f~~i~r~aii~ s~~ala~ai?ae~~r~~edt~~
contents of the RAM are maintained even after the power
is turned off.
Either of the
ROMs,
M5L 2708K
(1K
bytes)
or
M5L2716K (2K bytes) can be used by using a jumper
socket, but the standard version is arranged for the use of
the M5L2716K.
Parallel data can be read/written through the PPls, and
serial data through the SID and SOD of the M5L 8085AP
CPU.
PCA8501G01)
BLOCK DIAGRAM
-
--r:~=================:J
MEMSL OUTPUT
ROMSL RAM
ROM EXPANSION
EXPANSION
,-----~-HI----------~--------'+-__IABFH OUTPUT
AB8H
rt--t-t----,-----::r------h---;;-.-;:-;-:::-::;;:-;;-:-"+---l AB,7H ADDRESS BUS
ABOH
RESET INPUT
RSIL
HOLD INPUT
TRAP INTERRUPT
HLDL~--~~-~
IN~UT
TRPL
INTL 1-+-+--<1:>-.-/
INTE~W~t
REQUEST
READY INPUT RDYH~-W+==r~=:l
RESTART { R75L
INTERRUPT INPUT ~g~[~=I+::::j:==:t
D~7H } DATA BUS
~~rnJ[J~~~~~§~~I~~~~~~~~~~~~~~i~DBO~t~~ ~~RCcE"Mt~8~
SERIALI~~¥l s~gt !;==~++====.J
SERIAL
DATA
OUTPUT
~~tL ~~f.R tA~NS
::~g~ o.J~~EDJE"~?G
RESET OUTPUT
~ir=i=~t=~~====~~~~~-----BA~rRY
BACKUP
CIRCUIT
VSAT (MEMORY BACKUP
VCc(SV)
GND(OV)
]
VDD( 12V)
VSS( -SV)
ITAL
1~0~~ACKNOWLEDGE
OUTPUT
CLKH
TIMH
J&?,fGT
ST1H
J0¥~~T ST~TUS
PB17H PC17H
STOH
STAJUS
OUTPUT OUTPUT
\
PA 1OH
\
--;;=~P:;tBZ""7H-:--*PC""Z""7H:--
\
PC 1OH PC 1OH
PORT
PORT
PORT
ABC
\
PAZOH
\
PBZOH PC20H
PORT
PORT
PORT
ABC
6~~~(fT 6~~~(fT 6~~~(fT 6~~~(fT 6~~~(fT 6~~(fT
Notel: The wait signal generation circuit and the RAM battery backup circuit are not mounted on the PCA8501G01.
2: The M5L21114LPs are mounted on the PCA8501G01. instead of M58981Ss.
12-4
• MITSUBISHI
.... ELECTRIC
MITSUBISHI MICROCOMPUTERS
PCA8S01G01,G02
MELCS 85/2 SINGLE-BOARD COMPUTER
SPECIFICATIONS
Connectors
For bus extension (connector J1):
Straight pin header, T-type, 50 pins
For I/O port connection (connector J2):
Angle pin header, L-type, 60 pins
Processing Method
Method: 8-bit parallel operation
CPU: M5L8085AP
Word length:
PIN CONFIGURATIONS
Connector J1
Instruction: 8,16,24 bits
Data: 8 bits
Cycle time:
12V
Basic cycle time: 1.6fJs
CPU clock frequency:
5V
2.4576 MHz ±1% (Ta=0",55°C, Vcc=5V ±5%)
(Quartz oscillation frequency: 4.9152 MHz ±1%)
DATA Busj
Memory Address and Memory Capacity
(MSB)
EPROM (M5L2716K)
#1:
0800 16 ",OFFF 16
Memory capacity:
#1:
2K bytes (An EPROM is fitted to the standard
product)
#2: 2K bytes (Only a socket is provided on the
standard product)
RAM (M5L2114LP x 2 or M58981S x 2)
Memory address:
4000 16 ",43FF 16
1 K bytes
Externally expandable up to a maximum of
64K bytes
I/O Address and I/O Capacity
HOLD INPUT
RESTART INTER·
RUPT INPUT
ADDRESS BUS
(MSB)
Signal description
Address
PA
PAI0H-PA17H
600016
PPI
#1
PB
PBI0H-PB17H
600116
PC
C.W.
PPI
#2
PC 10H - PC 17H
600216
Control word
600316
PA
PA20H-PA27H
700016
PB
PB20H - PB27H
7001,6
PC
PC20H - PC27H
700 2 16
Control word
700316
C.W.
(5V)
Interrupt
5 Interrupts:
Five interrupts such as TRAP, RST 7.5, RST 6.5, RST 5.5,
and INTR are provided. The TRAP has the highest priority,
GNO
Vee
9 .... OBOH
11 .... OB2H
OB5H- 14
OB7H .... 16
13 ..... OB4H
15 ..... OB6H
17 -+STOH
5V
7
](LSB)
JOATA BUS
}STATUS OUTPUT
19 -+ST1H
21 -+IOMH
DATA TRANSFER
fFSt~A~8hOUTPUT
23 -INTL
REQUEST INPUT
RESET INPUT
ALEH- 28
25 +- RSIL
27 -+ RSOH
HLAH- 30
HLOL-+ 32
29 -+ CLKH
31 -+MEMSL
R75L-+ 34
33 -TRPL
AB1H- 36
35 -+ABOH
AB3H- 38
37 -+ AB2H
AB5H- 40
39 -+AB6H
AB7H- 42
41
-+
AB6H
AB9H- 44
43
-+
AB8H
ABBH- 46
45 -+ABAH
ABOH- 48
ABFH +- 50
47 -+ ABCH
RESET OUTPUT
CLOCK OUTPUT
RAM EXPANSION
~~l~YJTERRUPT
INPUT
(LSB)
ADDRESS BUS
49 -+ ABEH
Vee
2
1
GNO
4
3
SOOL- 6
R55L-+ 8
10
NC
PA11H ..... 12
PA13H ++ 14
PPI #1 r
I/O PORT AI PA15H ++ 16
PA17H ..... 18
PB11H ..... 20
PPI #1
I/O PORT B
PB13H .... 22
PB15H ..... 24
1 PB17H .... 26
PC11H .... 28
PPI #1
PC13H"" 30
I/O PORT C PC15H .... 32
I
!
PC17H .... 34
PA21H .... 36
PPI #2
I/O PORT A
PA23H ++ 38
PA25H .... 40
PA27H .... 42
PB21H .... 44
46
As two PPls (Programmable Peripheral Interfaces) are
provided on the board, the PCA8501 has I/O ports of 48
bits (8-bit x 6) in total.
5
5V
Connector J2
PPI (M5L8255AP)
I/O port
6
8
Vee
OB1H ++ 10
OB3H ..... 12
ROYH-+ 26
SERIAL DATA
OUTPUT
RESTART INTERRUPT INPUT
I/O address:
GNO
ITAL- 22
HO~~~f dtHtDt.r
Memory capacity:
Vee
GNO
ROMSL- 24
ROM EXPANSION
OUTPUT
READY INPUT
ADDRESS LATCH
ENABLE 2UTPUT
#2:
1
3
WRCL- 20
Ad~T&5~~0+
000016",07FF 16
2
4
ROCL- 18
READ C§NTROL
UTPUT
WRITE C NTROL
OUTPUT
Memory address:
Voo
GNO
I/O
:6~f~ ::~~: :
48
1 PB27H .... 50
PC21H ++ 52
PC23H .... 54
PPI #21
I/O PORT C PC25H .... 56
while the INTR has the lowest priority. The RST 7.5 will
enable timer interrupt by means of a jumper wire.
• MITSUBISHI
.... ELECTRIC
PC27H .... 58
GNO
60
Vee
GNO
5 +- SIOL
7 -R65L
(5V)
rJ~0~L DATA
RESTART INTERRUPT INPUT
9 -+ TIMH
TIMER OUTPUT
11
.....PA10H)
13 .... PA12H PPI #1
15 .... PA14H
17 .....PA16H
I/O PORT A
19
..... PB10H)
21 ..... PB12H PPI #1
23 .... PB14H I/O PORT B
25 .... PB16H
27
..... PC10H I
29 ..... PC12H PPI #1
31 ..... PC14H I/O PORT C
33 .....
35
....
37 ....
39 ....
PC16H
PA20H I
PA22H PPI #2
PA24H I/O PORT A
41 .... PA26H
43
.... PB20HI
45 .... PB22H PPI #2
47 .... PB24H I/O PORT B
49 ....
51
....
53 ....
55 ....
57 ....
PC20HI
PC22H PPI #2
PC24H I/O PORT C
59
GNO
PB26H
PC26H
Note 3 : NC indicates no connection.
12-5
MITSUBISHI MICROCOMPUTERS
PCA8501G01,G02
MELCS 85/2 SINGLE-BOARD COMPUTER
Memory and I/O Addresses
Memory Address Map
As memory and I/O addresses are fixed in this singleboard computer, it is necessary to designate extra
addresses besides those already assigned, if any addi-
000016
tional external memory or I/O devices are to be employed.
~ ~ ~ ~ ~: 1 - - - - - - . ;
]
~~OB~ftSM AREA.
EPROM :\1=2
I/O Address
1\
EPROM :jj; 1
OFF F 16 1 - - - - - - - 1
PPI
Port
Port
Port
A
B
C
I
PPI :\1=2
:\1=1
I
Port
Port
Port
A
B
C
0016
C.w
C.w
I
NOT USED
4 0
4 3
i
m~/8ed 600016 600116 600216 600316 700016 700116 700216 700316
PPI
externally, because there is no perfect redundancy in the
6 a a 0 16
7 a 0 0 16
-
]
PPI :\1=1
~ ~ ~ ~~: 1 - - - - - - - 1
The following addresses are inhibited from expanding
DATA AREA.
lK BITES
NOT USED
600016
decode of the PPls:
l=r
RAM
1
F F 16 1--------1.
Memory
address
:
MEMORY MAPPED 1(0
:\1=2
7 F F F 16 I - - - - - - - - t
6 F F F 16
7 F F F 16
. NOT USED
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Vee
Supply voltage
Conditions
Limils
Unit
V
0-7
VBB
Supply voltage
0.3- -15
VDO
Supply voltage
VI
Input voltage
Vo
Output voltage
0-5.5
V
Topr
Operating free-air ambient temperature range
0-55
"C
Tstg
Storage temperature range
-30-70
"C
With respect to GND
V
-0.3-20
V
V
5.5
RECOMMENDED OPERATING CONDITIONS
(Ta=0-55"C. unless otherwise noted)
Limits
Symbol
Parameter
Unit
Min
Nom
Max
Vee
Supply voltage
4.75
5
5.25
V
VBB
Supply voltage
-4.75
-5
-5.25
V
VDD
Supply voltage
11.6
12
12.6
VIH
High-level input voltage
VIL
Low-level input voltage
2
0.8
ELECTRICAL CHARACTERISTICS
(Ta=0-55°C,
V
V
V
Vee=5V±5%. unless otherwise noted)
Limits
Test conditions
Parameter
Symbol
Unit
Min
Typ
Max
VOH
High-level output voltage. PAllH-PC27H outputs
IOH= -50,uA
2.4
V
VOH
High-level output voltage. ABOH-AB7H outputs
IOH= -900,uA
3.65
V
VOH
High-level output voltage, AB8H-ABFH outputs
IOH= -300,uA
2.4
V
VOH
High-level output voltage, RSOH, HLAH, CLKH and ALE L
output
IOH= -300,uA
2.4
V
VOH
High-level output voltage, other outputs
IOH= -400,uA
2.4
V
VOL
Low-level output voltage, PAllH-PC27H outputs
IOL=1.8mA
VOL
Low-level output voltage, ABOH-AB7H outputs
IOL=16mA
VOL
Low-level output voltage, AB8H-ABFH outputs
IOL=1.9mA
VOL
Low-level output voltage, CLKH and HLAH output
IOL=4mA
VOL
Low-level output voltage, ALEL output
VOL
Low-level output voltage, other outputs
ICC
Vee supply current
feKL
CPU clock frequency
12-6
0
V
0.5
V
0.45
V
0.4
V
IOL=0.8mA
0.4
V
IOL=1.9mA
0.45
V
0.9
4.866
• MITSUBISHI
.... ELECTRIC
4.9152
4.965
A
MHz
MITSUBISHI MICROCOMPUTERS
PCA8S06
MELCS 85/2 MEMORY AND PARALLEL I/O EXPANSION BOARD
DESCRIPTION
FUNCTION
The PCA8506 memory and parallel I/O expansion board is
designed to be used with the PCA8501 or PCA8540 singleboard computer. Memory, parallel I/O ports, and a timer
are assembled on a 145 x 125 mm printed circuit board.
The PCA8506 can easily be attached to the PCA8501 or
PCA8540 single-board computer by using a bus-extension
connector.
The PCA8506 expansion board consists of up to 12K bytes
memory, six 8-bit parallel I/O ports, along with 3 16-bit
counters for timer application. The memory can easily be
expanded in units of 2K bytes up to 12K bytes using any
combination of M5L2716K EPROMs or M58725P static
RAMs. The parallel I/O ports consist of 2 (programmable
peripheral interfaces) (PPls) each composed of 3 8-bit I/O
ports. The timer consists of a programmable interval timer
(PIT) which has 3 16-bit timer counters.
FEATURES
•
Expansion board consisting of memory, parallel I/O
ports, and a timer
•
Memory capacity: 12K bytes
(expandable in units of 2K bytes RAM or 2K bytes
ROM)
•
Programmable ports: 48 bits (8 bits x 6 ports)
•
•
•
Programmable timer: 16 bits x 3
Power supplied from the PCA8501 or PCA8540
Compact dimensions (LxWxH): 125x145x17 mm
APPLICATIONS
•
Personal computer expansion module
•
Control equipment module
• MITSUBISHI
.... ELECTRIC
12-7
MITSUBISHi MICROCOMPUTERS
PCA8S06
MELCS 85/2 MEMORY AND PARALLEL I/O :EXPANSION BOARD
DIMENSIONS
OPERATION
(LxWxH) 125x145x17 mm
The address bus of the CPU is connected to other boards
through the address bus buffer. The data bus is connected
to the data input/output pins of memory, I/O, and a timer
through the bidirectional data bus buffer. The data bus
buffer is in an active state only when an IC device on the
board is selected. The buffer is ready for output to external units only when the read signal RDCL from the CPU
goes low.
Six 24-pin sockets are provided for memory, which are
designed for M5L2716K EPRQMs. Since the M5L2716K is
compatible with the M58725P except for VpplWR (pin
21), if pin 21 is switched on the connector corresponding
to a socket, a M58725P static RAM can be used in place of
a M5L2716K EPROM in that socket. It is therefore possible to mix ROMs and RAMs in any order desired by the
user.
Since addresses have been allocated on the memory map
for the 2 parallel I/O ports 'and a timer the contents can be
read and written in the same way memory is accessed.
All ports of PPls are initiated to the input mode after
the power is turned on, and remain in this mode until a
control word is written. As soon as the counter is set by
the control word, following the operation mode, the
timer will begin to count.
MEMORY AND I/O ADDRESSING
Both memory and I/O addresses can select two areas. When
this board is added, different address areas from those of
the main board should be selected~
MEMORY MAP
000016
} PCA 8501 ROM
EPROM.
OFFF16
1000 16
PCA 8506,' ROM/RAM
ROM/RAM
}
12K BYTES TOTAL
3FFF 16
40 00 16
4 FFF16
,
HAM
PEN
I/O, TIMER
500016
6000 16
PPI :11= 1
7000 16
PPI
:11=
PCA8501 RAM
PCA8506,' I/O" TIMER
PCA 8501, PPI
2
J
, PCA 8501, PPI
8000 16
I
9000 16
r-----------i }
I
OPEN
I
#1
lI: 2
PCA 8506 ROM/RAM
12K BYTES TqTAL
ROM/RAM
,
,
B FFF 16 ~_ _ _ _ _~
COO 016
I/O, Timer
} PCA8506, I/O, TIME R
C FFF 16 !-_ _ _ _ _--'!I
D00016i
OPEN
I
I
I
BLOCK DIAGRAM
,-----
ADDRESS BUS AB;H
INPUT/OUTPUT ABOH
~
~
Cl:
Cl::Ju..
ocou..
o :J
~
co
UJ V)UJ
~
1-11
~
ABOH
\
ABAH
tSAB9H ABFH
~
111
~
}S
).11
'\-11
}s
2
AO,Al
Ao ..... AI.(l 00-07
Ao--AIO 00-07
AO --A 1000-01
M5L2716K
EPROM
M5L2716K
EPROM
M5L2716K
EPROM
OR
OR
OR
OR
M58725P
stat,c RAM
M58725P
stat,c RAM
M58725P
stat'c RAM
M53725P
stat,c RAM
CS
CS OE Y"
CS
OEY"
WF
WA
DEY"
M5L2716K
EPROM
CS
WA
OE Y"
WR
f I
~ ~ r-;=:~
,~ti,=-=s-±~f-+-I-+-i
_------,I f
~
~ 8:;------J
~~ ~
Ell
~G
DATA BUSDB;H;-!- ~~~
INPUT/OUTPUT DBOH
~co~
I-
4>- -I>
-1'.:1
123
ROM/RAM 6
SELECTOR
SWITCH
Vp
+5V
S
~ 00-0,
I
:2
t
,8
CSWRROAo-A,Do-O,
P~o
P~o
RESET
P~o
Ct----I1»_-_,-_~-_-_-_-_-_-._-~_-~--'_''__=_:P~A-:___;;:~PiB\; -;~1 pc~
PA IOH
\
PB10H
\
V-2
PC 10H
I
Pi:
PA20H
\
P~o
P'~o
~i:
PB:
PB20H
\
PA I7H
PB I7H
PC 17H
PA27H
PB27H
PORTlIlA PORTIlIB PORT PORTU2A PORT
INPUT/
INPUT/
II lC
INPUT/
1I2B
OUTPUT OUTPUT d~~~J~ OUTPUT d~~~0Y
12-8
8
M5L8255AP PPI
P?o
• MITSUBISHI
, ;"'ELECTRIC
PIT
L
IT~
3
C
-i-,
0
~b~~~ ~1T
:;g ~ ~~::~To-2
\ COUNT CLOCK
IITC 2 INPUT
G-L IT~ 0
lb~N~&2SIGNAL
ITG 2 INPUT
CsWRROAo-A, 00-:-0,
M5L8255AP PPI
~ RESET
0
~ Ao~l,L8253P
p
'----t---t:---+-+-------+-----++-.tCS
RO
CONTROL~~~0~ WRCLt-;----Iv> - - - - - - - - '
RESET INPUT RSOH
~~L,~~~rr====;:~=~=S~~;;;;~~t-=--=--=--=--=--=--=--=--=-"~
t----,8'---L-l-+-r_-"--_-_-_-+-t--+-t_-+-t-_-_-_-_-......
-:_-_-_-_-_-_-++_--1I~!====jl-+-tWR
~
CONI1~8f RDCL
RD
¥
'-t-_-+_..:;WR
~
READ
t
PC20H
\
PC27H
PORTtl2C
INPUT/
OUTPUT"
MITSUBISHI MICROCOMPUTERS
PCA8506
MELCS 85/2 MEMORY AND PARALLEL I/O EXPANSION BOARD
SPECIFICATIONS
Memory Address and Memory Capacity
Connectors
1. P1 (for bus) : Straight dip-type, 50 pins.
2. J1 (for bus) : Straight pin header, T-type, 50 pins.
3. J2 (for I/O) : Angle pin header, L-type, 60 pins.
Memory Address (Note 1)
;I: 1 : 1000 16 -17FF 16
;I: 2 : 1800 16 -1 FFF 16
Power
;I: 3 : 2000 16 -27FF 16
5V, 1A maximum (when six M5L2716Ks are loaded).
PIN CONFIGURATION
;I: 4 : 2800 16 -2FFF 16
Connectors P1 and Jl
;I: 5 : 3000 16 -37FF 16
;I: 6 : 3800 16 - 3FFF 16
Memory Capacity
#1: 2K bytes (only
#2: 2K bytes (only
#3: 2K bytes (only
#4: 2K bytes (only
#5: 2K bytes (only
#6: 2K bytes (only
Either the M5L2716K
used in the sockets.
the socket is supplied)
the socket is supplied)
the socket is supplied)
the socket is supplied)
the socket is supplied)
the socket is supplied)
EPROM or M58725P RAM can be
I/O and Timer Addresses,and I/O Capacity
I/O and timer addresses (Note 1)
Name
,
Port #1
PA
PB
PC
CW
Port #2
PA
PB
PC
CW
COUNTER 0
COUNTER 1
COUNTER 2
CW
Timer
Signal designation
Address
PA 10H-PA17H
PB10H-PB17H
PC10C-PC17H
5000 16
50 01 16
Control Word
PA20H-PA27H
PB20H-PB27H
PC20H - PC27H
Control Word
I nterval timer
0
Interval timer
5200 16
5201 16
Control Word
520216
520316
1
Interval timer 2
Note 1: The address area can be altered by using an inline connector as follows:
Memory 9000'6-BFfF'6
1/0 and timer CXXX 16
I/O Capacity
Port #1
Port #2:
ADDRESS BUS
,
5002 16
500316
,51 00 16
510116
5102 16
5103 16
8 bits x 3 ports = 24 ,bits
8 bits x 3 ports = 24 bits
Interface
Bus : All signals are TTL compatible (fanout LS TTL 1
gate).
I/O and Timer: All signals are TTL compatible.
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
ABBH_ 46
ABDH_ 48
ABFH- 50
GND
GND
5V
Vee
DB1HDB3HDATA BUS
DB5H{
DB7HREAD CO~~~8f RDCLWRITE CONTROL WRCLINPUT
NC
NC
NC
NC
NC
NC
NC
1
3
5
7
9
11
13
15
17
19
21
11 23
- 25
-;,. 27
- 29
31
33
35
37
39
41
43
45
47
49
GND
GND
Vee
5V
_DBOH}
-DB2H
_ DB4H
DATA BUS
-DB6H
NC
NC
NC
NC
NC
_ RSOH
NC
NC
NC
RESET INPUT
[~~i~~ ~ m~ )
-AB8H
-ABAH
-ABCH
-ABEH
ADDRESS BUS
NC : NO CONNECTION
Connector J2
PA 16H- 2
#IA { PA12HPA 10HPBI6H# 18 PBI4H{ PB12HPB 10HPC16H# lC PC 14H{ PC 12HPC 10HPA26H1/0 PORTS PA24H#2A { PA22APA20HPB26HPA24H#28 PB22H{
PB20HPC26H#2C PC24H{ PC22HPC20H-
{~~~~:
ITC 1 -
:
TIMERS
• MITSUBISHI
.... ELECTRIC
ITO 1 ITG 2 ITC 0 -
::~: ~~ ~ll/O
1
3
PORTS
6
5 - PA 13H # lA
8
7 ++PAll H
10
9 ..... PB 17 H
12
11 ++PB 15H
14
13 ++PB 13H #18
16
15 ++PB llH
18
17 ++ PC 17
20
19 ++PC 15H #1C
22
21 ++PC 13H
24
23 ++PC llH
26
25 ++PA 27H}
28
27 ++PA 25H 1/0 PORTS
30 L 29 -PA23H #2A
32 Po.) 31 -PA21H
34
33 ++PB27 H}
36
35 -PB 25H
38
37 ++PB23H #28
40
39 - PB 21 H
42
41 ++ PC 27H}
44
43 ++PC 25H #2C
46
45 ++ PC 23H
48
47 ++ PC 21 H
50
49 - CS 3L
NC
52
51
54
53 -ITO 0 }
56
55 -ITG 1
TIMERS
58
57 -ITC 2
60
59 -ITO 2
1/0 PORTS , PA14H .... 4
H}
12-9
MITSUBISHI MICROCOMPUTERS
PCA8506
MELes 85/2 MEMORY AND PARALLEL I/O EXPANSION BOARD
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Vee
Supply voltage
VI
Input voltage
Vo
Output voltage
Topr
Operating free-air ambient temperature range
Tstg
Storage temperature range
r--..--....
Conditions
Limits
Unit
0-6.5
With respect to GND
RECOMMENDED OPERATING CONDITIONS
V
5.5
V
5.5
V
0-55
·C
-30-70
·C
(Ta=0-55·C. unlessotherwisenoted)
Limits
Symbol
Unit
Parameter
Vee
Supply voltage
VIH
High-level input voltage
VIL
Low·level input voltage
Min
Nom
Max
4 75
5
5.25
V
0.8
V
V
2
ELECTRICAL CHARACTERISTICS
(Ta=O -55·C. Vee=5V ±5%.
unless otherwise noted)
Limits
Symbol
Parameter
Unit
Test conditions
Min
Typ
Max
VOH
High-level output voltage PA 11 H-PC27H output
IOH=-50,uA
2.4
VOH
High-level output voltage. ITOD-IT02 output
IOH= -150,uA
2.4
VOL
Low-level output voltage. PA 11 H-PC27H output
IOL=1_6mA
0.4
V
VOL
Low-level output voltage. ITOD-IT02 output
IOL =1_6mA
0.4
V
12-10
• MITSUBISHI
.... ELECTRIC
V
V
MITSUBISHI MICROCOMPUTERS
PCA8507
MELCS 85/2 MEMORY AND SERIAL I/O EXPANSION BOARD
DESCRIPTION
APPLICATIONS
The PCA8507 memory and serial I/O expansion board is
designed to be used with the PCA8501 or PCA8540 singleboard computer. Memory, a serial I/O port and a timer are
assembled on a 145 x 125 mm printed circuit board. The
PCA8507 can easily be attached to the PCA8501 or PCA8540 single·board computer by using a bus-extension connector.
•
•
•
FEATURES
•
•
•
•
•
•
Expansion board consists of memory, a serial I/O and
a timer
Memory capacity: 12K bytes
(expandable in units of 2K bytes RAM or 2K bytes
ROM)
Serial I/O port and TTL, RS-232-C interface
Programmable timer, 16 bits x 3
Power supply from the PCA8501 or PCA8540
Compact, dimensions (LxWxH): 125x145x17mm
Personal computer expansion module
Control equipment module
Data terminal module
FUNCTION
The PCA8507 expansion board consists of up to 12K
bytes of memory, serial I/O port, interface for TTL level
and RS-232-C output, along with 3 16-bit counters for
timer application.
The memory can easily be expanded in units of 2K
bytes up to 12K bytes using any combination of M5L2716K EPROMs and M5825P static RAMs. The serial
I/O port consists of a universal synchronous asynchronous
receiver transmitter (USART) for changing parallel/serial
and formatting the string in the specified format. Interfaces
are provided between the USART and the TTL level or RS232-C output. The interface is selected by a jumper connection. The timer consists of a programmable interval
timer (PIT) which has 3 16-bit timer counters. One of the
timers is used by the USART for controlling the baud rate
of serial data transfer.
• MITSUBISHI
.... ELECTRIC
12-11
MITSUBISHI MICROCOMPUTERS
PCA8507
MELCS 85/2 MEMORY AND SERIAL 1/ 0 EXPANSION BOARD
OPERATION
The address bus of the CPU is connected to other boards
through the address bus buffer. The data bus is connected
to the data input/output pins of memory, I/O, and a timer
through the bidirectional data bus buffer. The data bus buffer is in an active state only when an IC device on the board
is selected. The buffer is ready for output to external units
only when the read signal RDCL from the CPU goes low.
Six 24-pin sockets are provided for memory, which are
designed for M5L2716K EPROMs. Since the M5L2716K is
compatible with the M58725P except for Vpp/WR (pin 21),
if pin 21 is switched on the connector corresponding to a
socket, an M58725P static RAM can be used in place of an
M5L2716K EPROM in that socket. It is therefore possible
to mix ROMs and RAMs in any order desired by the user.
Since addresses have been allocated on the memory map
for the USART as a serial I/O port and a timer the contents
can be read and written in the same way memory is accessed. TTL and standard RS-232-C interfaces are built
on the board to interface between the serial I/O port and
peripheral devices. Selection of one or the other interface
is done by a jumper in the jumper socket. The timer con-
sists of 3 16-bit counters. One of the counters is used as
a clock by the USART in setting the baud rate.
MEMORY MAP
000016
EPROM (PCA 8501 )
OFFF16
100016
,
~_'!'CJL_
EPROM
OR
I
IC14
r-'C1S--
RAM
3 FFF 16
400016
4 FFF16
! 500016
.5FFFI6
6 00016
r--1.91L_
'L __ LCJL_
f---H:H6--
RAM (PCA 8501 )
I/O, TIMER
I/O (PCA 8501 )
7FFF16
800016 I .
I
:
OPEN
.:.
BF FF 16 LI_ _-..,;._ _ _--11
•
COO 0
rjWhen this area IS selected by
CFFF::
I/O, TIMER
~~en~:~~~~.oftheDIC
0100016
L __ lg.L_
.
EPROM ,- __ I__ ~_When thiS area IS selected by
OR
~ __ I.9'!!__
the sWitch of the DIC
RAM
r- J9H.__
connector.
r-~§t~--·
F F F F 16 '--_ _--..1._.:.::::.:..::.......1
BLOCK DIAGRAM
2
.
ABFH
ADDRESS BUS
\
INPUT ABOH
Ao
A,
~+h::;=S==~~~=====~==~JRxROY
,----------+1TxRDY
h-==----D<>---+lTTL TxD
~-------1TTL RxD
PAPER TAPE READER
START
DATA BUS DB7 H
INPUT/OUTPUT
\
DBOH
L-.-Y">o--'
WRITE CONI1~S.f WRCL!-,- - ; . ) > - - - - - - - - '
RESET INPUT RSCL r------1I>--------'
CLOCK INPUT CLKH
12-12
RECEIVER READY OUTPUT
TRANSMITTER READY
OUTPUT
TRANSMIT DATA
RECEIVE DATA
• MITSUBISHI
.... ELECTRIC
MITSUBISHI MICROCOMPUTERS
PCA8507
·MELCS 85/2 MEMORY AND SERIAL I/O EXPANSION BOARD
SPECIFICATIONS
.PIN CONFIGURATIONS
Connectors Pl and Jl
Memory Address and Memory Capacity
Memory Address (Note 1)
#
1· :. 1000 16 -17FF 16
# 2 :
# 3· :
# 4 :
# 5 ,:
1.800 16 -1 F,FF 16
(5V)
2000 16 -27FF 16
2800 16 -2FFF 16
,
·D~TA BUS
300;D16-37FF 16
# 6 : 3800 16 - 3FFF 16
Memory Capacity
#1:, ,2·K bytes '(only the soc,ketis supplied)
#2: '. 2K bytes (only the socket is.supplied)
#3: 2K b'ytes(only the sock,Elt is supplied)
#4: 2K byte:s (only the sock~t is supplied)
#5: 2K bytes (only the socket is supplied)
#6: '2K: bytes '(only.the socket 'is supp'lied)
Either the M5L2716K EPROM ~~\ M58725P RAM can be
used in' th~ ·sockets.
{
.
,READ CONI1~8t
WRITE CONTROL
INPUT
1
3
5
7
9
11
13
15
17
19
21
24
26
28
30
32
34
36
38
40
42
44
46
48
50
" 32
::- 25
c... 27
- 29
31
33
35
37
39
41
43
45
47
49
AB1HAB3HAH5HAB7HAB9H-
.
, '.
. ADDRESS BUS
..
2
4
6
8
10
12
14
OB7H ...... 16
ROCL- 18
WRCL- 20
22
GNO
GNO
Vee
OB1H ......
OB3H ......
OB5H ......
ABBH(
ABOHABFH-
.
GNO
GNO
Vee
(5V)
...... OBOH}
...... OB2H
...... OB4H
DATA BUS
...... OB6H
-
RSOH
RESET INPUT
-AB2H
_ABOH)
-AB4H
- AB6H
-AB8H
-ABAH
-ABCH
-ABEH
ADDRESS BUS
I/O and Ti,mer Addresses a;nd I/O Capacity
In the above diagram when a name is not shown for a pin, then that pin
is not used, only connected to the same pin number of P1 and J1 .
I/O and timer addresses (Note 1)
. Signal designation
Name
Serial port
TO
CW
Timer
COUNTER
CW
0
1/
1
1/
2
Address
Parallel data
5000 16
Control word
500116
. Interval timer 0
I nterval timer' 1
Interval timer
2
Control word
510216
5103 16
INTERFACE
Timer
Serial I/O:
All signals are TTL compatible (fanout LS
TTL 1 gate).
All signals are TTL compatible (fanout TTL
1 gate).
TTL level or RS-232-C standard interface.
CONNECTORS
1. P1 (for bus):
2. J 1 (for bus):
3. J2 (for I/O):
Vee
GNO
(-12V)
VBB
NC
NC
NC
GNO
GNO
TTL LEVEL
INPUT/OUTPUT
GNO
GNO
ITC 1_
INTERVAL TIMER ITO 1 _
INPUT /OUTPUT {
ITG 2 NC
OB6BPCA 8507 DB 4BDATA BUS ( DB 2B(12V)
Note 1 The address area can be altered by using an inline con·
nectar as follows:
Memory DOOO'6-FFFF'6
I/O and Timer CXXX'6
Bus
Connector J2
5100 16
5101 16
Straight dip-type, 50 pins
Straight pin header, T-type, 50 pins
Angle pin header, L-type, 50 pins
POWER
I
OBOBUSER OPEN {CS 3L +CHIP SELECT CS 5L-
ADbRCts~53#
A B OB NC
NC
NC
TRANS~1116~ TxROY-
5V, 1A maximum (when six M5L2716Ks are loaded)
±12V (when used as an RS-232-C interface)
• MITSUBISHI
;"ELECTRIC
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
SERIAL I/O
(RS·232-C)
1 - TxO RH
TRANSMIT DATA
3 -+ OTR RH DATA TERMINAL
5 -+ RTS RH READY
REQUEST TO SEND
7 -OSR RH
DATA SET READY
9 -RxO RH
RECEIVE DATA
11 -CTS RH CLEAR TO SEND
13 -+TTL TxO
15 - TTL RxO
SERIAL I/O
TTL LEVEL
17 -+ ROR TTL
19 -BUSY FLG
21 -ITCO
INTERVAL
23 -ITG1
TIMER
25 -ITC2
INPUT/OUTPUT
27 -+ ITO 2
29 -OB7B
31 -OB5B
PCA 8507
DATA BUS
33 -OB3B
I
c..
N
35
37
39
41
43
45
47
49
++ DB 1B
-+CS 2L
-+ CS4L
-+CS 6L
-+AB1B
NC
NC
-+RxROY
USER OPEN
} CHIP SELECT
PCA B507
ADDRESS 1#
RECEIVER
READY
t'o4C: NO CONNECTION
12-13
MITSUBISHI MICROCOMPUTERS
PCA8507
MELCS 85/2 MEMORY AND SERIAL I/O EXPANSION BOARD
ABSOLUTE MAXIMUM RATI NGS
Symbol
Parameter
Vee
Supply voltage
VDD
Supply voltage (plus supply for RS-232·C)
Conditions
Limits
Unit
0-6.5
V
15
V
Vaa
Supply voltage (minus supply for RS·232·C)
-15
V
VI
Input voltage
5.5
V
Va
Output voltage
5.5
Topr
Operating free-air ambient temperature range
Tstg
Storage temperature range
With respect to GND
RECOMMENDED OPERATING CONDITIONS
V
0-55
V
-30-70
·C
(Ta=0-55·C, unlessotherwisenoted)
Limits
Unit
Parameter
Symbol
Min
Nom
Max
Vee
Supply voltage
VIH
High-level input voltage
3
Vee
V
VIL
Low-level input voltage
0
0.65
V
4.75
VDD
Supply voltage (plus supply for RS-232·C)
Vaa
Supply voltage (minus supply for RS-232·C)
ELECTRICAL CHARACTERISTICS
5.25
5
V
10.8
12
13.2
V
-13.2
-12
-10.8
V
(Ta=0-55·C, Vee=5V ±5%, unless otherwise noted)
Limits
Symbol
Test conditions
Parameter
Unit
Min
VOH
VOL
12-14
Typ
Max
High·level output voltage
DBOB-DB7B
IOH=- 3 rnA
2.4
V
High·level output voltage
ABOB, AB1B
IOH= -
2.4
V
High·level output voltage
IT01, IT02
IOH=-150,uA
2.4
V
High·level output voltage
CS2L-CS6L
IOH= -400,uA
2.7
V
High·level output voltage
TxDRH,DTRRH,RTSRH
3 rnA
Vee + = 10.8V, Vee- = -13.2V
5
V
VIL=0.8V, RL=3-7kQ
Low· level output voltage
DBOB-DB7B
IOL=12rnA
0.4
V
Low·level output voltage
ABOB, AB1B
IOL= 12rnA
0.4
V
Low-level output voltage
IT01,IT02
IOL=1.6rnA
0.45
V
Low-level output voltage
CS2L-CS6L
IOL= 4 rnA
0.4
V
Low-level output voltage
TxDRH,DTRRH,RTSRH
-5
V
Vee+=10.8V, Vee-=-10.8V
VIH= 2 V, RL=3-7kQ
• MITSUBISHI
"ELECTRIC
MITSUBISHI MICROCOMPUTERS
PCA8520G01,G02
MELCS 8S/3 VOICE GENERATING SINGLE-BOARD COMPUTER
DESCRIPTION
The PCA8520 is a voice generating single-board computer.
It consists of an 8-bit M5L8085AP microprocessor, memory, I/O interface, voice reproducing IC, and is fabricated
on a single 125 x 145 mm printed circuit board. Voice
data is first recorded in EPROMs and is changed into voice
data through delta modulation system.
•
•
Storage capacity of the RAM: 256 bytes
I/O interface: 24 bits (8 bits x 3)
•
Voice recording time:
using M5L2716K: 9 seconds (max)
using M5L2732K: 18 seconds (max)
•
Voice maximum output power (at VCC2 = 9V):
1W (typ)
•
Compact dimensions (LWH) 125x145x20 mm
FEATURES
Type
APPLICATIONS
Contents
PCA 8520 G01
Single-board computer only
PCA 8520G02
PCA8520G01 single-board computer. .
. ...... 1 pc.
M5L2716K (007) EPROM for control
program storage . . . . . . . . . . . . 1 pc.
(008-014) EPROMs for voice data storage. . . . . . . 7 pcs.
Speaker
I nstruction manual ...
•
•
•
•
•
•
•
An alarm device to be used in factories, offices, etc.
A recorded sales message device
An audio output information device
A device to give voice operation instructions
Numerical value response for measurement instruments
and calculators
1 pc.
1 vol
A single-board computer complete with CPU, memory,
I/O interface and voice reproducing IC.
Storage capacity of the EPROM:
using M5L2716K: 16K bytes (max)
using M5L2732K: 32K bytes (max)
FUNCTION
The PCA8520 is a single-board computer with a voice
generating function, and is designed around Mitsubishi's
M5L8085AP CPU, its LSI family, and voice reproducing
IC. It comes with 16K bytes (M5L2716K x 8) or 32K
bytes (M5L2732K x 8) of read-only memory and 256
bytes (M5L2112AP) of random-access memory. The
• MITSUBISHI
.... ELECTRIC
12-15
MITSUBISHI MICROCOMPUTERS
PCA8520G01,G02
MELCS 85/3 VOICE GENERATING SINGLE-BOARD COMPUTER
BLOCK DIAGRAM NOTATION
PCA8520 has 1 M5L8255AP programmable peripheral
interface (PPI) which offers 24 bits (8 bits x 3) of .pro-
Function·
Name
grammable I/O port.
Voice reproducing is performed through an IC for delta
demodulation, a low-pass filter, and a power amplifier.
Voice data in the ROM can be sent to the voice reproducing
circuit by program control, and then output with 1Wof
Reset circu it
Oscillator circuit
power.
A nine-second message can be output when using 8
M5L2716KS. An eighteen-second message is possible when
using 8 M5L2732Ks. Voice data can be output at both
syllable- and word-levels, and can be edited under program
A system
turned on.
reset signal is generated when
The clock is supplied to the CPU and the frequency
divider circuit.
Frequency divider
circuit
The frequency of the oscillator clock is devided by
CPU
Executes the program
Address latch
from ADo-AD, terminals·of the CPU using timesharing technique, only the address signal is latched
256 and is supplied to the voice reproducing circuit.
As the data and
control.
Idw-~rder addre~s
s!gnals are sent
into the address latch circuit by the ALE timing signal.
OPERATION
The M5L8085AP CPU ,executes programs stored in the
ROM synchronizing with a quartz ocillator clock. The
frequency of this clock is divided by 256 and is supplied
to the SID terminal of the CPU and the input of the IC for
delta demodulation. The voice can be generated using voice
data. This voice data, which is, stored in the ROM, is ~on
verted parallel to serial and is sent to the SOD terminal in
sequence from the most-significant bit.
The M5L2112AP RAM can be used as a data stack, etc.
The M5L8255AP PPI can be use~ for external data
inputs or outputs.
M5L2716Ks or M5L2732Ks
can
be selected by
Jumper socket
simply changing t~e jump~r wire)n the jumper .socket:
Address decoder
Generates the selection sign~1 of a ROM,. RAM, and
PPI decoding the high-order bits of the address signal
a~d
ROM
Memory to store program
RAM
Memory to store data stack, ,temporaly ?ata, etc.
PPI
Is used for external data inputs and outputs
voice data
Voice reproducing
Reproduces voice waveform fram the digital signal
circuit
which is sent from ~he SOD t~rminal of the CPU'
Low-pass filter
This filter only passes I~W-f(~q~ency voice signals.
Amplifier
Voice signal passed ttUough the low-pa~s filter is,
amplified to lW.
(5V)VCCl
(5V) VCC2
M74L5138P
GND
Xl
(-5V) Vss
SID
CPU
M5L8085AP
M54816P
RDD--------I--~~~~
I-
RESll
RESET INPUT
Z
S
AD7
1-------...... c;> ~ t------ir-----<1RE S IN Abo
ffiu
RESOUT
~~
ALE
~
12
READY
M5L8212P
8
SOD
WRP----------+--~~
ClK
RST7.5
M5155L
VOUT
VOICE
OUTPUT
12-16
po~er is
MIXO
Do-D7
M51802L
MIXI
FZH
PREAMP MIXER OUTPUT
OUTPUT INPUT INHIBIT
INPUT
RESOH READYH
ClKH
RESET
OUTPUT
CLOCK INTERRUPT
OUTPUT
INPUT
READY
INPUT
DATA BUS
8
• MITSUBISHI
"'ELECTRIC
MITSUBISHI MICROCOMPUTERS
PCA8520G01,G02
MELCS 85/3 VOICE GENERATING SINGLE-BOARD COMPUTER
SPECIFICATIONS
PIN CONFIGURATIONS
Connector J1
Contents
Item
Method
CVSD Method
CPU device
Mitsubishi·M5L8085AP
Cycle time
Basic instruction time 2,2,us (at 3.6MHz crystal
oscillator frequency)
(SV) VSSl {
GND {
NC
NC
PA 1H++
16K bytes (max) using M5L2716Ks
address 000016-3FFF16
Memory
PA3H~
ROM
I/O PORT A
32K bytes (max) using M5L2732Ks
.address 000016-7FFF16
RA M
256 bytes
{
PA7H++
.
lPB1H++
PB3H++
I/O PORT B PB5H'++
address COOO I6 -COFF I6
Programmable I/O ports:
PB7H-
8 bits x 3 ports
I/O interface
:
(PPI M5L8255AP)
I/O PORT C
{:~~~:
PC5H++
PC7H++
address 8000 16 -8003 16
RESET OUTPUT RESOHREADY INPUT READYH.
NC
Voice recording time
9 seconds usi~g M5L2716Ks (max)
18,seconds usi~g M5L2732Ks (max)
Voice maximum
output power
1W
Interrupt
1 in(errupt, .1 level
Auxiliary units
ME LCS 85/1 microcomputer console
voice data unit.
Power supply
5V (Two power sources: VCC1, VCC2). -5V
Angle pi!1, header type
50 pins (for the I/O ports)
Connectors
Angle pin, header type
6 pins (for voice output)
Angle pin, header type
4 pins (for power)
Physical dimensions
(Ve~2=5V,
PA5H++
THD= 10%
(-:-SV)
VBB
(5 v) Vee2
f=lkHz)
GND {
1
} Veel
3
5
} GND
7
9 _ F ZH
11
13
15
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
t-
19
21
.23
25
27
29
31
33
.35
'37
39
41
43
45
47
49
YN°~f§hOUTPUT
3m~51~1~:~::U:T
17
-
(5V)
++PA6H
++PBOH
- PB2H I/O PORT B
.... PB4H
.... PB6H' '
.... PCOH}
.... PC2H I/O PORT C
.... PC4H
-PC6H
++RESIL RESET INPUT
++CLKH CLOCK OUTPUT
NC
VBB (-- 5V)
V'Cez'( 5 v )'
}GND
NC: NO CONNECTION
Connector J2
VOICE OUl'PUT ,PIN
VOUT
(LxWxH): 125x !45x20 mm
GND
MIXING I,NPUTPIN
MIXI
CONNECTORS
VOICE
OUTPUT
I/O Ports: (Connector J1)
GND
angle pin header L-type 50 pins
angle pin header L-type
PREAMP OUTPUT PIN
MIXO
Power: (Connector J2)
4 pins
GND
Voice Output: (Connector J3)
angle pin header L-type
6 pins
Connector J3
Veel
5V
Vee2
SV
POWER SUPPLY
GND
-5V
VBB
I/O ADDRESS
PPI
Port A
I/O Address
• MITSUBISHI
.... ELECTRIC
8016
I
J
Port B
8116
I
I
Port C
8216
I
I
c,
W
83 16
12-17
MITSUBISHI MICROCOMPUTERS
PCA8520G01,G02
MELCS 85/3 VOICE GENERATING SINGLE-BOARD COMPUTER
MEMORY
ADDRESS MAP
000016
ROMl
3F FF 16
400 CJ 16
ROM2
(Note 2)
000016
2·
3:
ROM2 is additional storage area when 8 M5l2732Ks are used.
ROM is fully decoded, but RAM and PPI are not.
RAM
00FF16
FFFF16
Note
lL ___ ______________ :
.J
ABSOLUTE MAXIMUM RATINGS
Conditions
Parameter
Symbol
limits
Unit
0-7
V
0-15
V
Veel
Supply voltage
VCC2
Supply voltage
VSS
Supply voltage
VI
Input voltage
5.5
Vo
Output voltage
0-5.5
V
Topr
Operational free-air ambient temperature range
0-55
°C
Tstg
Storage temperature range
-30-70
°C
With respec to GND
RECOMMENDED OPERATING CONDITIONS
-15-0
V
V
(Ta =0-55°C, unless otherwise noted.)
Limits
Symbol
Unit
Parameter
Min
Nom
Max
Veel
Supply vol tage
4.75
5
5.25
V
VCC2
Supply voltage
4
5
12
V
Vss
Supply voltage
-18
-4
V
VIH
High-level input voltage
2
VIL
low-level input voltage
0.8
V
ELECTRICAL CHARACTERISTICS
-5
V
(Ta=0-55°C, unlessotherwisenoted.)
Limits
Symbol
Test conditions
Parameter
Unit
Min
VOH
High-level output voltage, RESOH, ClK H
IOH= -400,uA
VOL
low-level output voltage, RESOH, C lKH
IOL=2mA
VOH
High-level output voltage, PAOH-PC7H
IOH= - 200,uA
VOL
low-level output voltage, PAOH-PC7H
IOL= 1. 7mA
VIH
High-level input voltage, RESI l
2.4
VIL
Low-level input voltage, RESI L
-0.3
VIH
High-level input voltage, READY, RST75H
VIL
low-level input voltage, READY, REST75H
Po
Voice maximum output power
Typ
2.4
V
V
0.45
V
Vce
+0.5
V
V
0.8
Vec
+0.5
-0.3
RL=8Q, Ta=25"C
0.45
2.4
2_2
THD= 10%, f= 1kHz, Vee2=9V
Max
0_ 7
0_8
1
V
V
V
W
ICCI
Supply current from VCCI
900
mA
ICC2
Supply current from VCC2
400
mA
Iss
Supply current from VBB
100
mA
12-18
When 8 M5l2716K EPROMs are used.
• MITSUBISHI
.... ELECTRIC
450
MITSUBISHI MICROCOMPUTERS
PCA8540G01,G02
MELCS 85/2 COLOR TV DISPLAY SINGLE-BOARD COMPUTER
DESCRIPTION
The PCA8540 is a single-board computer of the ME LPS 85
LSI family. The TV interface is fabricated on a single 125
x 145 mm printed circuit board. It provides for screen displaying with a resolution of 256 x 192 elements maximum
in 2 colors, up to 8 colors in semigraphic 4, or up to 64
ASCII coded characters. A simple connection to the antenna terminal allows it to be used with a home color TV receiver. The PCA8540 also produces composite video signals that can be connected directly to the video monitor.
FEATURES
Type
PCA8540GOI
Function
•
•
•
with monochrome video monitor signals
Contains no EPROMs
Contains only one M58725P for screen memory
A single-board computer complete with CPU, memory,
I/O and TV interface
Enables up to 256(H) x 192(V) elements graphic display
on a home color TV receiver (or monochrome video
monitor)
Up to 64 characters can be displayed
The 64 ASCII characters are stored on an internal character generator ROM and can be displayed together
with semigraphics 4 mode
•
Provide 9 colors on screen: green, yellow, blue, red, light
gray, cyan, magenta, orange and black
•
ROM 4K bytes (max) + RAM 256 bytes or ROM 2K
bytes + RAM 2.25K bytes
•
•
•
Programmable I/O port with timer: 22 bits
Compact: dimensions (LxWxH): 125x145x20 mm
Expandable memory and I/O (using memory I/O expansion board PCA8506 or PCA8507)
APPLICATIONS
For home-use TV
with output of NTSC system signals for Japan
Channel 1 or 2
Contains no EPROMs
Contains only one M58725P for screen memory
For video monitor TV
PCA8540G02
•
• TV games
• Personal computer
• Data terminal with graphic capability
• Display terminal for microcomputer systems
• Commercial advertising display
• Slave computer for a MELCS 85/2 system
FUNCTION
The PCA8540 is a single-board computer, with color TV
display capabilities designed to be compatible with the
Mitsubishi M5L8085AP CPU and its LSI family as well as
the VDG (video display generator) LSI M5C6847P-1.
The PCA8540 comes with 4K bytes of ROM + 256 bytes
• MITSUBISHI
.... ELECTRIC
12-19
MITSUBISHI MICROCOMPUTERS
PCA8540G01, .GOa
MELCS85/2 COLOR TV DISPLAY SINGLE-BOARD COMPUTER
of RAM or 2K bytes of ROM + 2,304 bytes of RAM along
with 3 I/O ports (22 bits). ROM, RAM and I/O are provided by the MSL2716K x 2 + MSL81SSA or MSL2716K
+ MS872SP + MSL81SSA.
The TV interface of the GOl system consists of a VDG
LSI MSC6847P-l (TV interface), an MS1342P RF modulator IC and 3 MS872SP 16K static RAMs which are used
for screen display memory. The G02 system has a video
amp circuit instead of an MS1342P.
As the various display modes can be' programmed using
an MSC6847P-l, the following can.be displayed.
• Character display, pattern stored on internal ROM
• Reverse character display (one character)
• Semigraphics 4 (up to 8 colors)
• Semigraphics 6:(up':to 4 colors)
• 64 x 64 4 colors • 128 x 64. 2· d),lors
• 128 x 64" 4 coJors • 128 x 96 2 colors
• 128 x 96 4 colors .. 128 x 1922 colors
• 128 x 1924 colors • 2S6 x 1922 colors
The PCA8S06 and PCA8S07 are used, for mem6rY.I/0
expansion boards, to expand to a maximum of 16K bytes
of ROM or RAM, an RS-232-C serial·interface can be used.
OPERATIONS
The program for the MSL808SAP CPU is normally stored
on 2 MSL2716K EPROMs (2 x 2K bytes) and an MSL81SSP RAM (2S6 bytes) but 1 MSL2716K EPROM can be
replaced by an MS872SP RAM (2K bytes). Data transmission to and from external sources is done through the
ports of the MSL81SSP.
There is a data buffer between the MSC6847P-l and the
CPU on the address and data bus. This allows the MSC6847P-l to operate independently of the CPU when reading
information from the MS872SP RAM for screen data. It
adds synchronous signal before it is output serially to the
MS1342P TV game modulator. The signal includes the
intensity and color signals which are modulated by the
,MS1342P into NTSCsystem TV signals for channell or 2.
The MSC6847P-l's. composite video signal can be used for
input to the monochrome video monitor.
When the CPU accesses the RAM, addresses 6000 16 77FF 16 for screen data; MSof the MSC6847P-l will be at
low-level and the address output will be in high~impedance
state. During this period the CPU can change the contents
of'the RAM for screen' data. The CPU can also change the
display mode of the M SC684 7P-l through the. data bus by
.accessing mode set address 4800 16 ,
BLOCK DIAGRAM (PCA8540G01)
-~~-----:=~=====~=;=::::=::;::::::;;;::;;';;:;:::;::;:jTA 15 H}
16,
>
ADDRESS BUS
.
Vee
GND
Vss
,TAOH
.
(5 V)
(OV)
(- 5 V)
RESET INPUT RSIL
TRAP I NTE ~~~EhRPL f----..:[>---t
.
INTERRU~.PI1~5+
t,R75L
R65Lf-----f>---t
. R55 L f-----f>---l
,
INTERRUPT R~ftH.JE2L,INTLf-----..c[>---t
INTERRUPT INTA~------I
A K NOW LER~'i~$ ~~~~::: HDYH 1----'---"'1
SERIAL DATA INPU:r SIDL
fnn=-*~:!9~~d~§~~9~
FIELD
SYNCHRONOUS
FSL OUTPUT
HS.L HORIZONTAL
RPL SYNCH RONOUS
OUTPUT
ROW PRESET OUTPUT
8 TD7H}
~-~4-+I
1
DATA BUS
. TDOH
SERIAL DATA SODL!..'- - - ' - - - - - - '
OUTPUT
READ CONTROL,
c3~1~g[ ~ggtt:=====~:±t=+~~==:::;-ti:s--r=:tti
ADDRESSo~r~~~· ALEL~-~4----,----~\:-..L--~-Irtrr~~~ts:J
WRITE
E~t~~~ g~i~~i CLKHI--".:......------'--~O-o--,---___...j
~ _ _ _ _ _ _ ____L__~____,l__=,
TI
TIMER
.INPUT
12-20
--J
'-------_-_-_-_-_
' _
.,----------
TO
TIMER
OUTPUT
• MITSUBISHI
.... ELECTRIC
,
MITSUBISHI MICROCOMPUTERS
PCA8540G01,G02
MELCS 85/2 COLOR TV DISPLAY SINGLE-BOARD COMPUTER
PIN CONFIGURATIONS'
SPECI F ICATIONS
Connector Jl
Item
Description
Method
8-bit parallel operation
CPU Component
Mitsubishi's M5L8085AP (equivalent to the intel 8085A)
Cycle time
Basic instruction time 2.23ps (at clock frequency 1.79 MHz)
Memory
EPROM
4K bytes (M5L2716K x 2)
Address '0000 16 ~OF F F 16
or 2K bytes (M5L2716K xl) (Note 1)
2
1
VBB
(-SV)
3
4
GND
5
6
GND
(SV)
Vee
7
8
Vee
(SV)
9 -DBOH }(LSB)
DB1H- 10
11
12
-DB2H
DATA BUS' DB3H.DATA BUS
DB5H ..... 14
13 -DB4H
{
(MSB) DB7H- 16
15 -DB6H
RE~D CONTROL OUTPUT RDOL- 18
17 -STOH
19 -ST1H J..STATUS OUTPUT
WrIJffR~~~~ROL OUTPUTWROL_ 20
21 -IOMH g~~~RRA~GWtH N
ACKNOWLEDGE OUTPUT ITAL- 22
24 L 23 -INTL ~~1JuRERs~PTNPUT
ROM EXP6'uN(~8~ ROMSEL 1 25 -RSIL RESET INPUT
READY INPUT RDYH- 26
27 -RSOH RESET OUTPUT
28
fflR~LEESSob~~8~ ALE L 29 -OLKH CLOCK OUTPUT
HOLD RECEIVE INPUT H LAH- 30
HOLD INPUT HLDL_ 32
31 -ROMSEL 2 ROM 5~~~~~ION
34
33
35
36
)T1tr11)NTE RRUPT
38
37
39 -AB4H
40
42
41 -AB6H
ADDRESS BUS
44
43 -AB8H
ABBH- 46
45 -ABAH
ABDH- 48
47 -ABOH
(MSB) ABFH- 50
49 -ABEH
1.
Address 0000 16 ~07FF16
RAM
256 bytes (M5L8155P)
-
I
Address 4000 16 ~40FF16
or 2304 bytes (M5L8155P + M58725P)
Address 0800016~OFFF16 (Note 1)
: ~i~~
r------------------~ ~Oc:
,OlH
OZH
03H
RSIL
ISYNC ......~I____t
Cot__----__t
c. t--------\
~ ~ot-----,,~--I
UJ
ffi
AJ
I-
1E-------------4
~
~
o
,
B:i
iE----------+i
a:
INT L
Pl0H
I
P17H
PZOH
PZ6H
DB4H
ONE-CHIP MICROCOMPUTER
DB7H
TOH
TIH
Ao
I
AlO
SPEECH DATA MEMORY
M5,L2716K X 4 or M 5L 2732K X 4
~---~----------------
12-26
'-------------------------------~ AUOZ
------------------
• MITSUBISHI
.... ELECTRIC
----------------
-----~
MITSUBISHI MICROCOMPUTERS
PCA7002G01,G02
MELCS 70/2 SPEECH SYNTHESIZER SINGLE·BOARD COMPUTER
PIN CONFIGURATIONS
Connector J 1
SPECIFICATIONS
Parameter
Control method
Specification
B-bit parallel processing
Vee
2
4
6
8
ISCH
BSYH 4-- 10
SCTH --. 12
CLKH 4-- 14
N.U.
16
INTL --. 18
SRST --. 20
(Note 1) N_U.
22
P11H ++ 24
P13H ++ 26
P15H ++ 28
P 17H ++ 30
32
P21H
P23H ++ 34
P25H ++ 36
DB4H ++ 38
DB6H ++ 40
42
(Note 2) N.C.
T1H ++ 44
46
Vss
GND
48
Vee
50
1
3
5
7
9
11
13
15
GND
M5LB04B-XXXP, M5LB049-XXXP, and M5LB74BK
Control LSI
Vss
(the PCA7002G02 includes an M5LB049-005P
containing the standard program)
Cycle time
Basic cycle 4. 19/.1s (3.579545MHz crystal)
Speech synthesis method
PARCOR
Speech synthesis LSI
M58817AP
16K-byte, maximum (M5L2732Kx4)
Speech data memory
Data rate
Speech synthesis output
time
Addressable 00000, 6-03F F F, 6
BK-byte, maximum (M5L2716Kx4)
Addressable 00000-01 FFF,6
....
1.96K bitls (maximum)
3.92K bitls (maximum)
(Selectable by means of on-board jumpers)
60 seconds (minimum) using 1.96K bills transfer rate
(Memory capacity/1960)
30 seconds (minimum) using 3.92K bitls transfer rate
(Memory capacity/3920)
Speech output power
5.5W (4n speaker)
2.75W (Bn speaker)
Interrupt
1 factor, 1 level
--.
Note 1. NU:
2. NC:
Vee
GND
Vss
++ DOH
++ D1H
++ D2H
......
4--
17
Co.
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
4--
++
......
......
++
++
++
++
++
D3H
RSIL
N.U.
N.U.
IRST
P10H
P12H
P14H
P16H
P20H
P22H
P24H
P26H
DB5H
DB7H
++
++
++ TOH
Vss
GND
Vee
Non-usable
No connection
Pin numbers conform to silk·secreened numbers on the printed
circuit board
Connector J2
Power supplV
+5V ±5%, -5V ±5%
When using an M5L8049-005P controller and four
M5L2732K data memories
1
Vee
2
GND
3
Vss
-
800mA (maximum) @+5V
270mA (maximum) @-5V
Connectors
50-pin angled-pin header (1/0 port)
4-pin angled-pin header (power supply)
4-pin angled-pin header (speech output)
Dimensions
125(W) x 145(L) x 30(H)mm
f---4
----
NC
Connector J3
r---
1
AUD1
r--2
SIG
f----
3
AUD2
f----
4
SIG
'--
• MITSUBISHI
"'ELECTRIC
12-27
MITSUBISHI MICROCOMPUTERS
PCA7002G01,G02
MELCS 70/2 SPEECH
SYNTHESIZER SINGLE-BOARD COMPUTER
SPEECH DATA MEMORY MAP
Using M5L2732K
Using M5L2716K
o0
0 0'6
IC5(ROM # 1)
IC5(ROM # 1)
IC6(ROM#2)
IC7(ROM #3)
IC6(ROM#2)
IC8(ROM #4)
1 F F F'6
L..-_ _ _ _...J
(Maximum BK bytes)
IC7(ROM #3)
300 0'6 I------~
IC8(ROM #4)
3 F F F'6
L..-_ _ _ _.....
(Maxi mum 16K bytes)
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Vee
Supply voltage
VBB
Supply voltage
VI
Input voltage
Topr
Operating temperature
Tstg
Storage temperature
Conditions
Limits
With respect to the GND
-40-125
(Ta=25±5°C, Vcc:=5V±5%, VBB =-5V±5%, unless otherwise noted)
Limits
Unit
Min
Nom
Max
Vee
Supply voltage
4.75
5
5.25
V
VBS
Supply voltage
-4.75
-5
-5.25
V
ELECTRICAL CHARACTE RISTICS
(Ta=0-55°C, Vcc=5V±5%, unless otherwise noted)
Limits
Unit
Parameter
Symbol
Min
Typ
Max
VIH
RSIL
3.8
Vee
VIH
INTL,PIOH -P26H, DB4H-DB7H, TOH, TIH
2
Vee
v
VIH
DOH -D3H, ISCH, SCTH
4.0
Vee
V
V
VIL
Inputs other than DOH -D3H, ISCH, and SCTH
-0.3
0.8
V
VIL
DOf-l-D3H, ISCH, SCTH
-0.3
1
V
VOH
DB4H-DB7H (low-l00J,lA)
2.4
V
VOH
PIOH-P26H, TOH, TIH (low-50J,lA)
2.4
V
VOH
DOH-D3H, BSYH, CLKH (low-O.lmA)
4.0
VOL
DB4H-DB7H (IOL =2mA)
0.45
VOL
PIOH-P26H, TOH, TIH (loL=1.6mA)
0.45
V
VOL
DOH -D3H, BSYH, CLKH (lOL =50J,lA)
0.6
V
500
800
rnA
200
270
rnA
ICC
ISB
12-28
V
V
0-70
Parameter
Symbol
-0.3-7
VCC+0.3-VCC-15
-0.3-7
RECOMMENDED OPERATING CONDITIONS
With one M5LB049·005P and four M5L2732K devices
mounted
V
• MITSUBISHI
.... ELECTRIC
V
Unit
V
·c
·c
MICROCOMPUTER SUPPORT SYSTEM
MITSUBISHI MICROCOMPUTERS
PCA0803
MELCS 8/2 PROGRAM CHECKER
DESCRIPTION
FUNCTION
The PCA0803 program checker is simple to use, and is suit-
Software and hardware debugging can be readily achieved
able for testing the functioning of equipment that employs
the PCA0801 single-board computer and the PCA0802
memory and I/O expansion board without requiring any
extra software monitor program.
by simply connecting the PCA0803 program checker to
the equipment tested. Because the PCA0803 is a hardware
device, it does not require any extra software monitor
The PCA0803 program checker is useful both in design
performing single-step program execution, breakpoint operation, CPU resetting, and memory read/write operations.
evaluation and system troubleshooting in field mainte-
programs. The PCA0803 program checker is capable of
nance.
FEATURES
•
Single-step function: After halting the CPU at any designated address, allows step-by-step execution of the
APPEARANCE
program instructions in successive single machine cycles.
•
this address.
•
Memory read/write function: Enables data to be read or
written from/to any desired memory location.
•
•
Reset function: Can reset the M5L8080AP CPU.
Complete with bus cable: A special bus cable, approx.
800 mm long, is provided for connection.
•
•
•
Supply voltage: 5V ±5%
Supply current: 0.6A (typ)
Compact di mensions (L x W x H): 170 x 200 x 27mm
ADDRESS BUS
° ° ° 010 000 ° ° 0°1° ° ° °
° ° 0°1° 000 ° ° 0°1° ° ° °
00001
15 14
r
For design and evaluation of MELCS 8/2 and MELCS
85/2 Board Computer application systems.
13 12 11
8
76543210
76543210
76543210
EXT
E
~
10
9
DATA BUS
DATA
ill ill i iTTrT'I'j I
7
6
5
4
ill ffi ffi ill ill ill
SINGLE
MANU BREAKPOINT
APPLICATIONS
•
MELCS S/2/PCAOS03 PROGRAM CHECKER
Breakpoint function: Halts the CPU at any designated
address. Program execution can then be started from
3
2
1
0
ADDRESS SET
DEBT
J..MITSUmSHI ELECTRIC
i.4I.---------200mm-------~.1
Mitsubishi PCA0803 program checker
• MITSUBISHI
.... ELECTRIC
13-3
MITSUBISHI MICROCOMPUTERS
PCA0803
MELCS 8/2 PROGRAM CHECKER
FUNCTION
1. Display Panel
The display panel indicates the operating status of the
address bus, data bus and control signals.
2. Address/Data Switches
The ADD R ESS/DAT A switches are used in setting the
address and data for the designated RAM area.
3. H/L Address Set Switch
The H/L ADDRESS SET switch is used in latching the
address to the address/data latch circuit. The address is
latched to the address/data latch circuit in two operations,
the most significant 8 bits and then the least significant
8 bits.
4. Data Set Key
This key is used for data setting.
5. MEM Read/MEM Write Keys
These keys are used in reading or writing data from/to the
designated memory location.
BLOCK
DIAGRAM!
INPUT IOUTPUT
6. - Manu/Auto Selection Switch
In the AUTO position, the system executes sequential program instructions. In single-step or breakpoint operation,
this switch should be set to the MANU position.
7. Single Step/Breakpoint Selection Switch
In the SINGLE STEP position, depression of the STEP key
causes step-by-step execution of the program instructions
during successive single machine cycles. When the switch is
set to the BREAKPOINT position, the program execution
halts at the designated address.
8. Step Key
Each time this key is depressed, it executes one program
step.
9. Reset Key
This key resets the M5L 8080A P CPU. The program
counter is cleared to '0', and both the data bus and the
address bus are kept in the floating state.
10. Mode! Selection Circuit
This circuit receives various signals from each of the operational switches and sends out selected signals corresponding
to the mode assigned.
I~m~
CAB.H
"".~ !l1~
'~?o~~~6
~1~~~
MEMORY REAO
CME.AL
~::T~:::: {C~f~l~
DATA BUS
ADDRESS BUS
CONTROL BUS
OATA BUS
COB3H
COB2H
COB1H
COBOH
RESET SIGNAL
STATUS STROBE
~----------------~0
1--------------------I~3
RESET IN
1--------------------+1 ~
HOlO ACKNOWLEDGE
SIGNAL
o
C;~_~"n\ :]~FJsCIAL
Pl
EXT.
DATA
~----------------~ ~ t:::
HOlD REQUEST SIGNAL
a
.-----------~~~
} 5V
}GND
CABLE
TO CONNECTORS
PMA/PMD OF THE
PCA0801/PCA0802
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Conditions
Limits
Vee
Supply voltage
7
VI
Input voltage
5.5
Topr
Operating free-air ambient temperature range
Tstg
Storage temperature range
RECOMMENDED OPERATING CONDITIONS
(Ta=0-55"C.unless otherwise noted)
Limits
Parameter
Symbol
Unit
Min
Nom
Max
Vee
Supply voltage
4.75
5
5.25
V
VIH
High-level input voltage
3
Vee
V
VIL
Low-level input voltage
0
0.65
V
13-4
• MITSUBISHI
"ELECTRIC
Unit
V
V
0-55
"C
-30-70
"C
MITSUBISHI MICROCOMPUTERS
PC4000
DEBUGGING MACHINE
DESCRIPTION
CONFIGURATION
The PC4000 is a debugging machine for use with single-chip
microcomputers. It is intended for use as a general purpose
debugging machine for support of single-chip microcomputer hardware and software.
The PC4000, as shown in the block diagram, consists of the
following hardware elements.
(1) M5L8085AP monitor CPU
(2) Serial data input/output interface circuit
(3) EPROM writer circuit
(4) Program RAM (10 bits x 4K)
(5) Keyboard and LED display circuits
(6) Power supply
FEATURES
•
•
•
•
•
•
•
Usable for RAM-based program debugging
Connectable to the user system via a D I L socket or
connector
Built-in EPROM (2716,2732) writer function
Uses serial data transfer for two-way data transfer with
the host machine (e.g. PC9000 cross assembler machine)
Usable with a variety of single-chip microcomputers by
simply replacing a single board
Print out of internal memory contents is possible by
means of an external printer
Easy-to-carry-about in its compact case, provided with
an angle stand
The PC4000 is used in conjunction with a dedicated
board which allows interface of the PC4000 with the object
microcomputer under development. The dedicated board
insertion access window is located on the right side of the
PC4000. In addition, each dedicated board stores the
control program for the monitor CPU. Therefore, when the
microcomputer type is changed, the PC4000 can be
modified to suit the new type by merely changing the single
dedicated board.
APPLICATIONS
Hardware and software development and program debugging for single-chip microcomputer systems.
• MITSUBISHI
"'ELECTRIC
13-5
MITSUBISHI MICROCOMPUTERS
PC4000
DEBUGGING MACHINE
FUNCTIONAL DESCRIPTION
Object programs developed on such devices as the PC9000
cross assembler machine are sent to the PC4000 via the
serial input/output interface. The serial data transmission
rate can be selected from 1200bps to 9600bps and the
interface is a 20mA current loop type. The transmission
format is Intel-compatible hexadecimal.
The data in the program memory is executed by the
evaluation CPU on the dedicated board. In addition, this
memory contents can be written into 2716 or 2732
EPROM devices or data can be read out of such devices via
a 24-pin 0 IL socket.
The keyboard consists of 12 function keys and 16
numerical keys as well as a single entry key. The LED
display is an 8-digit display of 7-segment LED elements
used to display data for reference while processing is
performed.
BLOCK DIAGRAM
EPROM
2716
2732
PROM WRITER
INTERFACE
KEYBOARD
DISPLAY
M5L8041A-006P
M5L8279P-S
PROGRAM
MEMORY
SERIAL I/O
INTERFACE
M5T4044PX 10
M5L8251 AP-5
,-----
---,
I
I
I
I
I
:
I
DEDICATED BOARD
I
I
IL ____________ I ____________
I
I
USER SYSTEM
•
13-6
:
I
I
MITSUBISHI
.... ELECTRIC
I
~
MITSUBISHI MICROCOMPUTERS
PC4000
DEBUGGING MACHINE
KEY FUNCTIONS (BASIC FUNCTIONS ONLY)
Symbol
SEND
Name
Data transmit key
Converts program memory data to serial
PROG
EPROM inserted in the socket
LOAD
(EPROM)
Load key
Sends data from the EPROM inserted
in the socket to program memory
PRT
Print key
Data transmit to the optional printer
Examine program
memory key
Verification/correction of program
memory contents
Examine register key
Verification/correction of register
contents
Examine memory key
Verification/correction of RAM contents
R
EXM
M
RES
Reset key
RUN
Run (execute) key
Writes program memory data into the
The system is used with a dedicated board which
includes the evaluation chip to perform in-circuit
emulation
MS8840-XXXP
Receives serial data and writes this data
into program memory
(EPROM)
Program key
EXM
Method
data and transmits to an external device
Data receive key
P
Specification
Item
Function
RCV
EXM
SPECIFICATIONS
MS8494- XXXP
Applicable
MS8496- XXXP
microcomputers
MSL8048-XXXP
MSL8049-XXXP
and all other Mitsubishi single-chip microcomputers
Program RAM
Built-in, 4K x 10 bits (250ns access time)
Control CPU
MSL808SAP
Built-in EPROM
writer circuit
Usable with 2716 or 2732 devices
Display
7-segment LED, 8 digits
Input
Key switches: Commands: 12 keys
Numerical: 16 keys
Entry: 1 key
CD
20mA current loop serial input/output interface
4800bps, full deplex, one line
(Selectable from 1200 to 9600bps)
®
Centronix-compatible parallel interface, one line
Interface
Reset of program counter
Re-start of program execution at the
specified address (real time)
Monitor programs for the appropriate object
microcomputers are written into the two M5L2732K
devices mounted on the dedicated board.
BRK
Break point set key
Sets the break point address
STEP
Single step key
Excutes the program one step at a time
O-F
Numerical keys
Used for input of address and data
ENT
Entry key
Effectively enters input numerical data
Basic Functions
Monitor function
User system
connection
···
··
·
Transfer of RAM data with an external system
Read and write of EPROM data
Verification/correction of the built-in program
memory (RAM) contents
Execution and halt at any arbitrary program address
Single-step execution of programs
Verification/correction of internal registers, memory,
flags
'Input/output connections to the dedicated board by
means of a cable
Dimensions
364 X 2S7 X 8Smm (excluding handle and key switch tops
Power supply
AC 100V
"U"peratlng
temperature
·Storage
temperature
• MITSUBISHI
.... ELECTRIC
100VA
S-40°C
-20-60°C
13--7
MITSUBISHI MICROCOMPUTERS
PC4000
DEBUGGING MACHINE
PC4000 CONFIGURATION
TO EXTERNAL PRINTER
DEDICATED BOARD
(4-8IT SINGLE-CHIP)
20mA
CURRENT
LOOP
TO PC9000 4800 bps
CROSS
ASSEMBLER
USER
SYSTEM
POWER SUPPLY
DEDICATED BOARD
(FOR USE WITH ME LPS8-48)
PCA 8400
PC 4000
13-8
• MITSUBISHI
~ELECTRIC
MITSUBISHI MICROCOMPUTERS
PC7000
SPEECH SYNTHESIS EVALUATION UNIT
DESCRIPTION
FUNCTION
The PC7000 is a device intended for use in evaluating
The PC7000 includes a 16-key panel which allows pro-
speech synthesized from voice data by the PARCOR
grammed voice sequences to be called up from EPROM
method under uniform conditions and enables complete
memory. In response to a single key up to eight voice
evaluation of Mitsubishi speech synthesis products.
instruction steps may be specified, enabling the generation
of up to seven words continuously, four words continuous-
FEATURES
ly at the specified interval and the generation of repetitions
•
Enables speech synthesis in response to keyed-in infor-
of the entire sequence. The EPROM may be removed by
mation
means of a window provided on the PC7000.
•
Allows free selection of the number of repetitions of
•
•
•
Because the PC7000 is provided with a built-in power
speech
supply, audio amplifier, and speaker, it can be powered
Enables up to a maximum of seven speeches to be
from the commercial power source and used for test
continuously generated in response to one keyed input
listening immediately. In addition, a line output is provided
Spacing between words is freely settable
for use with other amplifiers and speakers making connec-
Up to four words may be generated continuously with
tions with other audio equipment simple.
the programmed spacing
•
EPROM data modification may be used to easily change
the above programmed sequences
•
Built-in power supply and speaker allow immediate use
•
A line output is provided for test listening by means of
•
•
SPECIFICATIONS
Specification
Item
external filters, amplifiers and speakers
Speech generation
section
An external switch may be used to easily switch between
Keyboard section
male and female speakers
Volume control
An external switch may be used to select low or high bit
rate
Speech output
power
Low passfilter, highpass filter, main amplifier
16 input keys (O-FI
Controls output volume
1W (Maxi
Line output
Output before and after filtering
Speaker
12cm single cone,
EPROM
M5L2716K or M5L2732K (the EPROM may be removed from
the PC7000 by means of an access windowl
an
(11 Male/female speaker switch
External switches (21 Low-h igh bit rate switch
(312716/2732 EPROM switch
• MITSUBISHI
.... ELECTRIC
13-9
MITSUBISHI MICROCOMPUTERS
PC7000
SPEECH SYNTHESIS EVALUATION UNIT
SOFTWARE
The PC7000 has a configuration similar to the PCA7002
single-board computer, and uses the same M5L8049-005P
CPU as does the PCA7002. On the PCA7002, corresponding to the speech input to the 18 ports, speech is generated
in accordance with speech sequences and speech addresses
previously recorded in EPROM, whereas in the PC7000, of
the 18 ports 1 through 16 correspond to the keyboard
inputs 0 through F. Therefore, it is necessary to store in the
PC7000 EPROM addresses 0000 16 through 007F 16 voice
sequences which correspond to t.fle keyboard 0 through F.
For details of the method of writing voice sequence data
and starting addresses, refer to the manual for the
PCA7002.
BLOCK DIAGRAM
KEYBOARD
MALE/FEMALE SPEAKER SWITCH
C
0
E
F
8
9
A
B
BIT RATE SWITCH
4
5
6
7
2716/2732 EPROM SWITCH
2
3
o
LOWPASS
FILTER
HIGHPASS
FILTER
MAIN
AMPLIFIER
SPEAKER
LINE OUTPUT 2
LINE OUTPUT 1
POWER SUPPLY
1-------1
# 1 #2 #3 #4
EPROM SOKETS
13-10
•. MITSUBISHI
;'ELECTRIC
MITSUBISHI MICROCOMPUTERS
PC8S00,PCA8S03
MELCS 85/1 PORTABLE MICROCOMPUTER CONSOLE
DESCRIPTION
MELCS 85/1 SYSTEM CONFIGURATION
The PC8500 portable microcomputer console is a microcomputer system embodying the PCA8502 board computer. Not only it does operate as a general-purpose
BUFFER MODULE
PCA8503
PC8500
OPTIONAL
BOARD
(INDEPENDENTLY
DESIGNED BY
USER)
microcomputer, but it also can be used as a debugging
system, in which the M5L 8085AP MELPS 85 8-bit microprocessor (identical with Intel's 8085A) is used. The
PCA8503 is a buffer module that interfaces the debugged
AC100V
system with the PC8500 through an IC socket of the
M5L8085AP, S, when the PC8500 is used as a debugging
system.
FEATURES
APPLICATIONS
•
•
•
Can be used as a debugging system in which a micro-
Hardware and software development of a system in which
Interfacing of the PC8500 with the debugged system
through an IC socket of the microprocessor on the
an 8-bit microprocessor identical with the M5L8085A
is used.
Testing for board computer.
debugging system.
•
•
Debugging unit
processor identical with the M5L 8085AP is used.
The PCA8503 is provided for the interface.
Feasible to use the PC8500 as a customized unit by
adding an optional board to the general-purpose micro-
•
computer PC8500.
The 24-key keyboard and the eight 7-segment LED display are furnished as input/output devices.
•
•
Contains a circuit for a system typewriter on the board.
The PC8500 is housed in a portable carrying case.
Maintenance and inspection systems that use a board
computer.
•
General-purpose microcomputer
Application system that is customized by the user (e.g.
PROM writer, data logger, board checking system, etc).
• MITSUBISHI
.... ELECTRIC
13-11
MITSUBISHI MICROCOMPUTERS
PC8S00,PCA8S03
MELCS 85/1 PORTABLE MICROCOMPUTER CONSOLE
FUNCTION
The PC8500 is composed of the board computer PCA8502
and the power supply unit, as shown in the block diagram.
The functions of the PCA8502 comprise the following
hardware functional blocks:
(1) CPU
(2) Program memory
(3) RAM
(4) Keyboard display interface
(5) Parallel I/O interface
(6) Serial liD interface
(7) Special logical circuit designed for the debugging
system
The PCA8502 offers 1K bytes of EPROM and 4K bytes
of RAM and also releases the M5L 8255AP PPI (8-bit X
3 programmable I/O ports) for a parallel I/O interface.
Program monitoring is provided by a monitor that
controls the keyboard and the LED display of the PCA8502
and a monitor that controls the system typewriter
The PCA8503 is a buffer module employed in interfacing
the PC8500 (PCA8502) with a user system (debugged
board), as shown in the block diagram, and supplied as an
optional board.
BLOCK DIAGRAMS
PC8500
1[=-'----..1
.
I
I
PCAB502
BOARD COMPUTER
I
POWER SU_P_PL_Y_U_N_IT_lrov
PCA8503
"~
CONNECTOR J 1
TO THE
c~~N~g~~cli
.~
CPU DRIVER/RECEIVER}FOR DEBUGGED
SYSTEM
~
CONNECTOR J2
TO IC SOCKET OF
~~§T~~~~SED
OSCILLATION CIRCUIT
OF CRYSTAL
.
OSCILLATOR
_~
PCA8502 BLOCK DIAGRAM
I
CONNECTOR
J1
12V--
CPU
5 V - } CONNEcTOR J,
(POWER SUPPLY)
5V-
INTERFACE OF
THE SYSTEM
BEING DEBUGGED
MONITOR
CONTROL
LOGIC
EPROMs FOR
MONITOR
PROGRAM
PANEL KEYBOARD
AND DISPLAY
INTERFACE
RAMs
FOR
WORKING
SYSTEM
TYPEWRITER
INTERFACE
~
CONSOLE
PANEL
) CONNECTOR J,
.
L
13-12
I
RAMs FOR
PSEUDO
PROGRAM
MEMORY
USER RELEASED
PARALLEL I/O
INTERFACE
(EXPANSION BUS)
CONNECTOR
J2
• MITSUBISHI
~ELECTRIC
-
I
MITSUBISHI MICROCOMPUTERS
PC8500,PCA8503
MELCS 85/1 PORTABLE MICROCOMPUTER CONSOLE
HOW TO OPERATE THE PANEL
iJ)
®
LED WHICH SHOWS THE
OPERATING STATUS
~
7 -SEGMENT
8 PIECES
+
1-DOT LED
r~--------------~A~--------------~,
®
CD
'-------------------~v~------------------@
HARDWARE
SWITCHES
RES (RESET)
SOFTWARE CONTROLLED SWITCHES
5 Software control keyboard
Resets the I/O controllers of the system, including the
This keyboard consists of 24 2-key rollover scanning
CPU, and the CPU enters the WAIT state.
keys, and is used for entering commands for the monitor
2 MON CALL (MONITOR CALL)
program.
With this switch, the control of the CPU is removed to
the monitor area. As this switch was depressed following
the depression of the "RES" switch, the CPU enters
the monitor command request state after executing the
monitor program.
3 RST 0 (RESTART 0)
As this switch was depressed after depressing the "RES"
switch, it makes the CPU perform from the address 0 16 .
4 MEN EN (MEMORY ENABLE)
Depression of this switch enables the pseudo program
memory, and the RAM address provided in the system
is changed to the area of 000016-0FFF16 superseding
the ROM area. While it is disabled, it can be used as
an ordinary RAM that will have addresses designated
by the mini-switches provided in the system.
It can also serve as a user-specified input
device, when a user's program is prepared for it.
6 7-segment LED display
It is composed of 8 pieces of 7-segment LEOs and used
as an output device for the monitor. It can also serve
as a user-specified output device when a user's program
is ~repared for it.
7 Status indicating LEOs
The MEN EN indicator LED displays the state of the
pseudo program memory; it indicates that the pseudo
program is enabled when the LED is on.
The HOLD indicator LED shows that the CPU is in
the HOLD state.
The TRAPMK indicator LED lights to show that the
TRAP interrupt signal is being masked. It remains lit as
long as the monitor program is in execution or the
command designating TRAP interrupt is valid.
• MITSUBISHI
.... ELECTRIC
13-13
II!!IIIIII
IIIiIIIII
MITSUBISHI MICROCOMPUTERS
PC8500,PCA8503
MELCS 85/1 PORTABLE MICROCOMPUTER CONSOLE
SPECIFICATIONS OF THE PCA8502
Descri ption
Item
Method
CPU
Cycle time
M5L8085AP
1.3ps basic cycle at crystal oscillator 6.144MHz
ROM: F80016-FFFF16
System
use area
= 2K
bytes for a monitor
program
ROM: F40016-F7FF16 = 1 K bytes for user released
area
RAM: F30016-F3FF16 = 256 bytes for monitor used
area
C!-
~
g>
'0>
g>
'0
Inhibited area: F00016- F2FF 16
As a system monitor, there are two types of monitors; the
keyboard monitor, which uses the keyboard and the LED
display as I/O device, and a TIY monitor, which uses the
system typewriter as I/O device.
~
-al
o
E
~
co
System
monitor
CI)
co
c
0
User
released
area
Description
Item
8-bit parallel processing unit
j
RAM: *00016- *FFF16, max 4K bytes,
Where * indicates any number from 016-E16
Can be used as a pseudo program memory
Functions of the monitor are:
(1) Verifying the contents of the memory
(2) Verifying registers of the CPU
(3) Execution of user's program
(4) Executing a program after setting breakpoint address
(5) Step-by-step execution of program
(6) Verifying I/O registers
(7) Block transferring of data
(8) Setting and resetting interrupt mask
(9) Data dump and load to the memory (hexadecimal
notation is available in the case of the TIY monitor)
Keyboard display interface:
FD16, F116; interface for panel switch
data command indication
USART:
F416,F516; system typewriter interface
data command
I/O
interface
Optional board
Parallel port:
F816-FB16; system control interface
Available for expansion of the CPU bus
A single optional board (approx. 140 x 310mm) can be
added.
J 1 (50 pins): for the interface with the user's system
I/O address of the area,F016 - FFI6; other than the above
are inhibited from use.
Connectors
J3 (50 pins): for CPU bus
Programmable I/O port released for user's purpose:
* 016, *116, * 216, * 316
Where"* indicates any number from 0 16 -E 16.
Keyboard
display
Keyboard: 24 keys. with 2-key rollover scanning method
Display: 7-segment LED x 8 pcs
System
typwriter
interface
20mA current loop (with
source power supply)
TIL level (I/O under negative
logic)
Signal lines:
Serial data input. serial data
output. and reader start signal
lines
Applicable transfer speed' 110, 1200, 2400, and 4800
baud
Capable of connection with ASR-33, Casio Typuter, etc.
J2 (50 pins): for the parallel I/O port and the system
typewriter interface
J4 (10 pins): for power supply connection
Power supply
5V, 2.5A (typ)
1 2V, 1 50mA (typ)
-5V, 90mA (typ)
Driver/receiver:
User released
I/O port
Dimensions
SPECIFICATIONS OF THE PCA8503
Item
Description
Function
Interfaces the board computer PCA8502 with a user's
system which has a CPU identical to the M5L8085A.
Furnished with the driver/receiver and an extension cable.
Connectors
8-bit x 3 I/O programmable ports
Power supply
Applicable CPU
CPU clock
§
Interface with
user system
M5L8085AP (identical with Intel's 8085A)
Cable
Can be operated with clock from the user's system (3.125MHz max )
To be connected with the IC socket of the CPU of user's
system through the buffer module (PCA8503)
(W x L x H): 310 x 300 x 22mm
Dimensions
Operating free-air
temperature
50 pins and 40 pins
Supplied from the PCA8502, 5V/350mA (typ)
Approx. 1m long
(Wx L x H): 120 x 100 x 25mm
0-50't
SPECIFICATIONS OF THE PC8500
~
C>
c
I
'0
co
User's
address
area
All the address areas except those below, which must be
used by the debugging unit. are released to users.
Address area:
FOO016-FFFFI6
I/O address area: FOI6-FF16
Interrupt
All interrupt signals to the CPU are released for users
As for TRAP interrupt. it is possible to mask it by the monitor
command
CI)
Item
Description
Function
In compliance with function of the PCA8502 implemented
Supply power input
AC100V±1O%, 50Hz/60Hz
co
CI)
c
0
j
Pseudo
program memory
13-14
It is possible to substitute the address area 000016OFFF16 of the user's system with the RAM in the
debugging system.
Internal
supply power
Operating free-air
temperature
Dimensions
(carrying case)
Weight
• MITSUBISHI
.... ELECTRIC
5V/5A, 12V/300mA, -5V/300mA
Those used in the board are 5V/2.5A, 12V/150mA.
-5V/90mA (typ).
10-40't
(Wx Lx H): 370 x 350 x 140mm
7kg
MITSUBISHI MICROCOMPUTERS
PC8500,PCA8503
MELCS 85/1 PORTABLE MICROCOMPUTER CONSOLE
SYSTEM ADDRESS AREAS
PSEUDO PROGRAM MEMORY
Among the address areas used by the system, the memory
Among the address areas in the user's system, it is possible
addresses 000016",EFFF 16 and the I/O device addresses
00 16 ", EF 16 are all released for the user, and the rest of
the areas are used by the system. So the user should stay
within the prescribed areas.
Furthermore, the RAM area released for the user may be
to substitute the area 000016",OFFF 16 with the RAM
within the system.
.
h MEMI key,
· . .IS enabled by d epressmg
SU bstltutlon
teEN
switched over of its address in the unit of 4K bytes using
I
which allows the RAM to access the area 0000 16 ",
OFFF I6 , enabling the execution of a user's progr.am, and
altering the contents of the RAM.
the mini-switches.
OPTIONAL BOARD
It allows expansion of the system as the bus lines of the
CPU are extended to the connector J 3 .
MEMORY ADDRESS AREA
--1
0000
USER'S AREA
* 000
--
.
USER RELEASED
RAM AREA
* FFF --
-
FOO~.
F300 ':-~
F400 --
~
-
USER'S AREA
RAM
]
-
140 X 310mm as an optional board with which a userspecified device may be obtained by preparing it with the
user's own design.
4K BYTES
RELEASED FOR USER
n
1 - 256 BYTES
1WORK AREA RAM
USER RELEASED ROM
lK BYTES
ROM# 1
F800 --
It allows addition of one extra board whose size is about
1
1-
SYSTEM-USED
ADDRESS AREA
FOOO-FFFF 16
ROM#2
FOOD --
-
FFFF -.
-
SYSTEM MONITOR ROM
2K BYTES
ROM#3
1/0 ADDRESS AREA
-
USER'S AREA
*<1>
USER RELEASED
AREA
00- EF 16
*3
FO. Fl
F4. F5
SYSTEM USE
AREA
F8
FO-FF16
\
FB
NOT USED
•
MITSUBISHI
..... ELECTRIC
1':t-1t;
MITSUBISHI MICROCOMPUTERS
PC8S00,PCA8S03
MELCS 85/1 PORTABLE MICROCOMPUTER CONSOLE
PCA8502
•
11--1 h
MITSUBISHI
.... ELECTRIC
MITSUBISHI MICROCOMPUTERS
PC9000
CROSS ASSEMBLER MACHINE
DESCRIPTION
FUNCTION
The PC9000 is a cross assembler machine. It is capable of
converting programs for the Mitsubishi single-chip microcomputers written in assembler language to machine language. In addition, it can perform such debugging functions
as disassembly and act as an EPROM writer.
The PC9000 as shown in the configuration diagram consists
of the following hardware
(1) Control CPU and bootstrap ROM
(2) 48K byte RAM
(3) 2K byte display screen RAM
(4) 9-inch CRT display circuit
(5) EPROM writer circuit
(6) ASCII keyboard
(7) Hardcopy output by means of an internal mini-printer
circuit or an external printer interface circuit
(8) Floppy disk controller (two mini floppy disk drives)
(9) Parallel input/output interface circuit (two lines)
(10) Power supply
An M5L8085AP is used as the control CPU. The
keyboard, CRT, mini-floppy disk drives, and printer interfaces are connected by means of a bus line. The keyboard is
used for input of commands to the monitor and source
program data verification. The 9-inch green CRT display
screen is capable of displaying 24 lines of 80 characters. As
a printer a 20 column mini-printer is built-in to the PC9000
in addition to the ability to use an 80 column printer
having Centronix compatibility via an interface which is
available. The built-in mini-printer may be used to output
FEATURES
•
•
•
•
•
•
•
•
Input of the source program from the keyboard
An efficient screen editor allows editing of source
programs
Program dump and load to the mini-floppy disk
Object data write/read for 2708, 2716 and 2732
EPROM devices
Listing using a Centronix-compatible printer is possible
Data transmission is possible to the PC4000 debugging
machine
Usable with all types of Mitsubishi single-chip microcomputers
Compact, desk-top design
APPLICATION
Software development support for Mitsubishi single-chip
microcomputers.
• MITSUBISHI
.... ELECTRIC
13-17
MITSUBISHI MICROCOMPUTERS
PC9000
CROSS ASSEMBLER MACHINE
the disassembly results while the external printer may be
used to output the assembly listing as well as disassembly
listing.
Function
FUNCTIONAL DESCRIPTION
The PC9000 contains the assembler, disassembler, source
editor, and EPROM writer functions required for software
support of microcomputers. These functions are summarized in the Table.
Assemble
Disassembly of the specified file
Output: 20 column printer, external printer
Disassemble
Appl icable devices
Effect
Source input: keyboard
output: printer, EPROM, data transfer (with debugging
unit)
All 4-bit single-chip PMOS, and CMOS microcomputers
M5lB04B, M5lB049 and M5lB041A B-bit single-chip
microcomputers
Same as above
Source editor
Deletion, insertion, modification, character search, and
screen editing
Same as above
PROM writer
EPROM erase check, write, verification, read
M5L2708K, M5L2716K, M5L2732K
PC9000 CONFIGURATION
CRT
CONTROllER
AC
100V
CENTRON I X-COMPATI BlE
13-18
• MITSUBISHI
"ELECTRIC
MITSUBISHI MICROCOMPUTERS
PC9000
CROSS ASSEMBLER MACHINE
SPECIFICATIONS
Item
Specification
Structure
Desktop-type, single cabinet
CPU
Mitsubishi M5L8085AP (2.45 MHz clockl
IC memory
2K byte ROM (bootstrap areal. 48K-byte DRAM, 2K-byte VRAM
Memory device
Mini floppy disk x 2 drives, double-sided, double-density
Display
9-inch green CRT display, 80 lines x 25 characters
Keyboard
Modified ASCII specifications, 2-key lockout
Ded i cated pri nter
5 x 7 dot Matrix thermal printer, 20 columns. 2 lines/s. Paper width: 60mm.
Printer interface
Centronix, parallel interface
Interface connector: 36-pin DDK Amphenol
Serial input/output interface
20mA current loop (2 linesl
Data transfer format
MELPS 85
Applicable microcomputers
MELPS
MELPS
MELPS
MELPS
Outer dimensions and weight
Desk top-type 470(WI x 290(HI x 490(DI, 17kg
Power supply
AC 100V±10%
Hexadecimal (equivalent to Intel Hexadecimall
8-48
4
41
42
(M5L8048- XXXP, M5 L8049- XX XP and others)
(M58840-XXXP and others)
(M58494- XXXP)
(M58496-XXXP and others)
50/60Hz
KEYBOARD ARRANGEMENT
,--------------,POWER
IFl IF21 F'I F'I Fsi F61'~ I 11 I-I
j
°0
iDi m;~
=
-=
2708L~
ON
tj
(SPACE)
• MITSUBISHI
"ELECTRIC
13-19
MITSUBISHI MICROCOMPUTERS
PCA4001
MELPS 4 DEDICATED BOARD
DESCRIPTION
CONFIGURATION
The dedicated MELPS 4 PCA4001 board is for use with
As can be seen in the block diagram, the PCA4001 consists
the PC4000 debugging machine for the M58840·XXXP
of the following hardware:
(1) Evaluation chip (M58842S) and peripheral circuitry
and M58841·XXXSP single'chip 4·bit microcomputers and
is used by inserting the board in the PC4000 cabinet.
(2) EPROM with the PC4000 monitor program
(3) Single·step and breakpoint control circuit
FEATURES
(4) Program memory interface circuit
•
Connection to user's systems by a flat cable
•
Single·step operation and breakpoint operation capabil·
ity from the PC4000 debugging machine keyboard.
(5) I nput/output buffer/latch circuit
The- board and the user's systems can be connected by
means of an accessory cable.
Debugging functions such as confirmation of internal
•
register contents
FUNCTION
Can be used with external and internal clocks
The debugging machine PC4000 operates as a debugging
machine for MELPS 4 microcomputers using the monitor
APPLICATIONS
The development of hardware, and software for systems
program contents of a ROM mounted on the dedicated
board. The evaluation chip (M58842S) loaded on the board
using the MELPS 4 (M58840·XXXP, M58841·XXXSP)
executes program stored in the program memory in the
single·chip microcomputers.
PC4000 debugging machine.
The internal status of the evaluation chip is read out
under monitor CPU control when single'step operation and
breakpoint operation are halted.
1-
BLOCK DIAGRAM
r---------------~ D PORT
SPORT
15
DATAOUTPUT~------------------~
11
COMPARISON ADDRESS t-------f----~
ADDRESS IDENTITY
DETECTOR
INSTRUCTION ~--------------.,.-------.'-~ lo-Is
12
ADDRESS 1 - - - 1 - - - - .
INSTRUCTION
(MONITOR)
13-20
1
• MITSUBISHI
;"ELECTRIC
MITSUBISHI MICROCOMPUTERS
PCA4001
MELPS 4 DEDICATED BOARD
SPECI FICATIONS
Specification
Item
Applicable microcomputers
Clock
frequency
II
M58840-XXXP, M58841-XXXSP
Package
600kHz
Variable
range
300-600kHz
Applicable debugging
machine
Power supply
PC4000 (connected by a cartridge connector)
Supplied by the PC4000
Connection to user's
systems
By an accessory cable
Debugging functions
•
•
•
•
•
•
(contents of monitor
EPROM)
•
•
•
•
•
Program execution from any address and halt
Single-step operation
Data writing to EPROM and reading
Confirmation and change of the contents of
program RAM
Serial data transfer to an external device
Confirmation and change of the RAM in the
evaluation chip and the contents of the following
registers and flags
Program counter
Data pointer
Accumulator
B register
H/L registers
• MITSUBISHI
.... ELECTRIC
13-21
MITSUBISHI MICROCOMPUTERS
PCA4003
MELPS 4 DEDICATED BOARD
DESCRIPTION
CONFIGURATION
The PCA4003 is a dedicated ME LPS 4 board for use with
the PC4000 debugging machine for the M58843-XXXP
4-bit single-chip microcomputers and is used by inserting
the board in the PC4000 cabinet.
As can be seen in the block diagram, the PCA4003 consists
of the following hardware.
(1) Evaluation chip (M58842S) and peripheral circuitry
(2) EPROM with the PC4000 monitor program
(3) Single-step and breakpoint control circuit
(4) Program memory interf.ace circuit
FEATURES
• Connection to user's system by a flat cable
• Single-step operation and breakpoint operation capability from the PC4000 debugging machine keyboard.
Debugging functions such as confirmation of internal
register contents.
• Can be used with external and internal clocks
APPLICATIONS
The development of hardware and software for systems
using the MELPS 4 (M58843-XXXP) single-chip microcomputers.
(5) Input/output buffer/latch circuit
The board and user system can be connected by means
of an accessory cable.
FUNCTION
The debugging machine PC4000 operates as a debugging
machine for MELPS 4 microcomputers using the monitor
program contents of a ROM mounted on the dedicated
board. The evaluation chip (M58842S) loaded on the board
executes the program stored in the program memory in the
PC4000 debugging machine.
The internal status of the evaluation chip is read out
under monitor CPU control when single-step operation and
breakpoint operation are halted.
1-
BLOCK DIAGRAM
15
......---r---r--I S 0 - S 7 Ko - K 14 k------.L----l PO RT K INPUT
11
'----r---+-+--t Do- D 10
DATA OUTPUT IE-------------------~
M58842S
11
COMPARISON ADDRESS
INSTRUCTION
t-------+------:.t
ADDRESS
IDENTITY DETECTOR
INSTRUCTION
(MONITOR)
13-22
iE----7''-----t Ao-A 10
1----------------"7"'""""-----r------;;.j 10-18
12
ADDRESS
11
1-----+----,
I
• MITSUBISHI
"ELECTRIC
MITSUBISHI MICROCOMPUTERS
PCA4003
MELPS 4 DEDICATED BOARD
SPECIFICATIONS
Specification
Item
Applicablemicrocomputers
I
Clock
Package
frequency I Variable
range
M58843-XXXP
455kHz
300-600kHz
Applicable
debugging machine
PC4000 (con nected by a card edge con nector)
Power supply
Supplied by the PC4000
Connection to user's
system
By an accessory cable
Debugging functions
• Program execution from any address and halt
(contents of monitor)
EPROM
• Single-step operation
• Data writing to EPROM and reading
• Confirmation and change of the contents of
program RAM
• Serial data transfer to an external device
• Confirmation and modification of the RAM data
in the evaluation chip and verification and
modification of the following registers and flags:
• Program counter
•
•
•
•
Data pointer
Accumulator
B register
H/L registers
• MITSUBISHI
;'ELECTRIC
13-23
MITSUBISHI MICROCOMPUTERS
PCA4004
MELPS 4 DEDICATED BOARD
DESCRIPTION
CONFIGURATION
The PCA4004 is a dedicated ME LPS 4 board for use with
the PC4000 debugging machine for the M58844-XXXSP
4-bit single-chip microcomputers and is used by inserting
the board in the PC4000 cabinet.
As can be seen in the block diagram, the PCA4004 consists
of the following hardware.
(1) Evaluation chip (M58842S) and peripheral circuitry
(2) EPROM with the PC4000 monitor program
(3) Single-step and breakpoint control circuit
(4) Program memory interface circuit
(5) Input/output buffer/latch circuit
The board and user system can be connected by means of
an accessory cable.
FEATURES
• Connection to user's system by a flat cable
• Single-step operation and breakpoint operation capability from the PC4000 debugging machine keyboard.
Debugging functions such as confirmation of internal
register contents.
• Can be used with external and internal clocks
APPLICATIONS
The development of hardware and software for system
using the MELPS 4{M58844-XXXSP) single-chip microcomputers.
1-
FUNCTION
The debugging machine PC4000 operates as a debugging
machine for MELPS 4 microcomputers using the monitor
program contents of a ROM mounted on the dedicated
board. The evaluation chip (M58842S) loaded on the board
executes the program stored in the program memory in the
PC4000 debugging machine.
The internal status of the evaluation chip is read out
under monitor CPU control when single-step operation and
breakpoint operation are halted.
BLOCK DIAGRAM
.-----------------------------~~ PORTD
PORT S
15
iE--.....---.t--ISO-S1
Ko-K14~---."------lPORT K INPUT
11
L...---+-----+---I--IDo - 0 10
DAT A OUTPUT ~---------------------------------------.J
M58842S
11
COMPAR ISON ADDRESS t-------------I-------~
11
ADDRESS
IDENTITY DETECTOR
1oE-~-_I
Ao-A 10
I NSTRUCTION I-----------------------------~--------~--;~ 10 -Is
12
ADD RESS f - - - - - - - f - - - - -.....
INSTRUCTION I
(MONITOR)
•
13-24
MITSUBISHI
~ELECTRIC
MITSUBISHI MICROCOMPUTERS
PCA4004
MELPS 4 DEDICATED BOARD
SPECIFICATIONS
Item
Specification
Applicable microcomputer
M58844-XXXSP
l
Package
Clock
frequency Ivariable
range
455kHz
300 -600kHz
Applicable debugging
machine
Power supply
PC4000 (connected by a card edge connector)
Supplied by the PC4000
Connection to user's
system
Debugging functions
(contents of monitor
EPROM)
By an accessory cable
•
•
••
Program execution from any address and halt
Single-step operation
Data writing to EPROM and reading
Confirmation and change of the contents of'program
RAM
Serial data transfer to an external device
Confirmation and modification of the RAM data in
the evaluation chip and v.erification and modification
of the following registers and flags:
• Program counter
Data pointer
Accumulator
B register
•
•
•
•
•
•
H/L registers
• MITSUBISHI
"ELECTRIC
13-25
MITSUBISHI MICROCOMPUTERS
PCA400S
MELPS 4 DEDICATED BOARD
DESCRIPTION
CONFIGURATION
The PCA4005 is a dedicated MELPS 4 board for use with
the PC4000 debugging machine for the MS884S-XXXSP
4-bit single-chip microcomputers and is used by inserting
the board in the PC4000 cabinet.
As can be seen in the block diagram, the PCA400S consists
of the following hardware.
(1) Evaluation chip (MS884S-000SP) and peripheral circuitry
(2) EPROM with the PC4000 monitor program
(3) Single-step and breakpoint control circuit
(4) Program memory interface circuit
(S) Input/output buffer/latch circuit
The PC4000 is connected to this board using a card
edge connector and this board is connected to the user
system by means of an accessory cable.
FEATURES
• Connection to user's system by a flat cable
• Single-step operation and breakpoint operation capability from the PC4000 debugging machine keyboard.
Debugging functions such as confirmation of internal
register contents.
• Can be used with external and internal clocks
APPLICATIONS
FUNCTION
The development of hardware and software for systems
using the MELPS 4 (MS884S-XXXSP) single-chip microcomputers.
The debugging machine PC4000 operates as a debugging
machine for the MS884S-XXXSP using the contents of the
monitor ROM mounted on the dedicated board. The
evaluation chip (MS884S-000SP) loaded on the board
executes the program stored in the program memory in the
PC4000 debugging machine.
BLOCK DIAGRAM
II
!cCLaCK
GENERATOR
I
XIN
S7-S0
PORT S
K7- KO
PORT K
4
PORT F
F3-Fo
INSTRUCTION
EVALUATION
CHIP
M58845-000S P
COMPARISON
ADDRESS
TIMER
BREAK ADDRESS
CONTROL CIRCUIT
INPUT/OUTPUT
LATCH BUFFER
ADDRESS
8
INSTRUCTION
(MONITOR)
13-26
MONITOR
EPROM
• MITSUBISHI
.... ELECTRIC
12
PORT D
MITSUBISHI MICROCOMPUTERS
PCA400S
MELPS 4 DEDICATED BOARD
SPECIFICATIONS
Specification
Item
Applicable microcomputers
Clock
I
Package
frequency !Variable
range
M58845-
xxxsp
455kHz
300 -600kHz
Applicable debugging
machine
PC4000 (connect8d by a card edge connector)
Power supply
$upplied by the PC4000 when inserted into debuggIng machine
Connection to
user's system
By an accessory cable
Debugging functions
•
Program execution from any ~ddress and halt
(contents of monitor
EPROM)
•
Data writing to EPROM and reading
•
Confirmation and change of the contents of program RAM
Seria! data transfer to an external device
•
•
Confirmation and modification of the evaluation
chip RAM daia and register sontenls
• MITSUBISHI
.... ELECTRIC
13-27
MITSUBISHI MICROCOMPUTERS
PCA4011
MELPS 41 DEDICATED BOARD
DESCRIPTION
CONFIGURATION
The PCA4011 is a dedicated ME LPS 41 board for use with
the PC4000 debugging machine for the M58494-XXXP
4-bit single-chip microcomputers and is used by inserting
the board in the PC4000 cabinet.
As can be seen in the block diagram, the PCA4011 consists
of the following hardware:
(1) Evaluation chip (M58494-000P) and peripheral circuitry
(2) ROM with the PC4000 monitor program
(3) Single-step and breakpoint control circuit
(4) Program memory interface circuit
(5) Input/output buffer/latch circuit
The PC4000 is connected to this board using a card edge
connector and this board is connected to the user system
by means of an accessory cable.
FEATURES
• Connection to user's system by a flat cable
• Single-step operation and breakpoint operation capability from the PC4000 debugging machine keyboard.
Debugging functions such as confirmation of internal
register contents.
• Can be used with external and internal clocks
FUNCTION
APPLICATIONS
The development of hardware and software for systems
using the MELPS 41- (M58494-XXXP) single-chip micro·
computers.
The debugging machine PC4000 operates as a debugging
machine for the ME LPS 41 using the contents of the
monitor ROM mounted on the dedicated board. The
evaluation chip (M58494-000P) loaded on the board
executes the program stored in the program memory in the
PC4000 debugging machine.
The internal status of the evaluation chip is read out
under monitor CPU control when single-step operation and
breakpoint operation are halted.
BLOCK DIAGRAM
PORT Q
DIRECTION
CONTROL
~----+-----~PORTQ
12
PORT A 1 o E - - - - - - - - , ' - - - - - - - I
INSTRUCTION
(FOR 494)
RIoIE-----+-----~
DP LATCH
PORT R
R7
So
DATA BUS BUFFER ~-------:t'-1-0.--~_+~Q,oUo
\ ~-------+_-------~PORTS
S7
Q7 U1
To
'-------+--+--1 1>
I ~------+_--------~ PORT T
EVALUATIONT7
CHIP
M58494-000P
R/Wb-------+---~~
OMPARISON
12
INTERNAL
REGISTER
CONTENTS
ROM
ADDRESSI--------+----~
SI NG LE-STEP
CONTROL CIRCUIT
OD~-------------~OD
I NSTRUCTION (MONITOR)
13-28
• MITSUBISHI
.... ELECTRIC
MITSUBISHI MICROCOMPUTERS
PCA4011
MELPS 41 DEDICATED BOARD
SPECIFICATIONS
Item
Applicable microcomputers
Clock
frequency
IPackage
IVariablerange
Speci fi cation
M58494- X X X P
250kHz
100-350kHz (externally connected)
Applicable
debugging machine
PC4000 (connected by a card edge connector)
Power supply
Supplied by the PC4000
Connection to user's
system
By an accessory cable
Debugging functions
(contents of monitor
EPROM)
•
•
·
··
Program execution from any address and halt
Data writ'lng to EPROM and reading
Confirmation and change of the contents of
program RAM
Serial data transfer to an external device
Confirmation and modification of the RAM data
in the evaluation
chip (M58494-000P) and the
contents of the following registers and flags:
•
•
···•
•
Program counter
Data poi nter
Stack pointer
Accumulator
•
•
•
S register
T register
CY flag
B register
Q register
R register
• MITSUBISHI
.... ELECTRIC
13-29
MITSUBISHI MICROCOMPUTERS
PCA4012
MELPS 42
DESCR I PTION
DEDICATED BOARD
CONFIGURATION
The PCA4012 is a dedicated MELPS 42 board for use with
As can be seen in the block diagram, the PCA4012 consists
the PC4000 debugging machine for the M58496-XXXP
of the following hardware:
. (1) Evaluation chip (M58496-000P) and peripheral circuitry
(2) ROM with the PC4000 monitor program
4-bit single-chip microcomputers and is used by inserting
the board in the PC4000 cabinet.
FEATURES
(3) Single-step and breakpoint control circuit
•
Connection to user's system by flat cables
(4) Program memory interface circuit
•
Single-step operation and breakpoint operation capability from the PC4000 debugging machine keyboard.
(5) Input/output buffer/latch circuit
The PC4000 is connected to this board using a card edge
Debugging functions such as confirmation of internal
connector and this board is connected to the user system
register contents.
by means of an accessory cable.
•
Can be used with external and internal clocks
FUNCTION
APPLICATIONS
The development of hardware and software for systems
using the MELPS 42 (M58496-XXXP) single-chip microcomputers.
The debugging machine PC4000 operates as a debugging
machine for the MELPS 42 using the contents of the
monitor ROM mounted on the dedicated board. The
evaluation chip (M58496-000P) loaded on the board
executes the program stored in the program memory in the
PC4000 debugging machine.
The internal status of the evaluation chip is read out
under monitor CPU control when single-step operation and
breakpoint operation are halted.
BLOCK DIAGRAM-----
I
EIT INSTRUCTION
GENERATOR
OUTPUT PORT
LATCH
INSTRUCTION j'-----~~-~
1--_+f-'_8--';!~ PO RT P
2
I PORT F
INSTRUCTION
DATA BUFFER
~----
25+ 4
__~-------~~g=~
LC
COM
4+4
M58496
~---------+_----__--?~PORT K
PORT S
-ooop
OUTPUT PORT
LATCH
11
~---r'--~I PORT D
,
COMPARISON
ADDRESS r - - - - + - - - - - - l - - - - - - - - l
I
I
I
12
ADDRESS t - - - - - . , L -_ _~
PCA4000 MONITOR
CLOCK
GENERATOR
INSTRUCTION i'E-_ _---;.8c........._ _--I ROM 2732x2
(MONITOR)
13-30
• MITSUBISHI
"'ELECTRIC
I
J
MITSUBISHI MICROCOMPUTERS
PCA4012
MELPS 42 DEDICATED
BOARD
SPECI FICATIONS
Item
Applicablemicrocomputers
Clock
frequency
I Package
I Vanable
range
Specification
M58496-XXXP
4.194304MHz
2
~4.2MHz
Applicable debugging
machine
PC4000
(connected by a card edge connector)
Power supply
Supplied from the PC4000 when inserted into the
debugging machine
Connection to user's
system
By an accessory cable
Debugging functions
•
•
•
•
(contents of monitor)
EPROM
··
·•
··
Program execution from any address and halt
Single-step operation
Data writing to EPROM and reading
Confirmation and change of the contents of
program RAM
Serial data transfer to an external device
Confirmation and change of the RAM in the
evaluation chip (M58496-000P) and the contents
of the following registers and flags
Data pointer
Accumulator
B register
CY flag
• MITSUBISHI
lhi..ELECTRIC
13-31
MITSUBISHI MICROCOMPUTERS
PCA4014
MELPS 42 DEDICATED BOARD
DESCRIPTION
CONFIGURATION
The PCA4014 is a dedicated ME LPS 42 board for use with
As can be seen in the block diagram, the PCA-4014 consists
the PC4000 debugging machine for the M58497-XXXP
of the following hardware:
4-bit single-chip microcomputers and is used by inserting
the board in the PC4000 cabinet.
(1) Evaluation chip (M59497-000P) and peripheral circuitry
FEATURES
(3) Single-step and breakpoint control circuit
•
•
Connection to user's system by flat cables.
Single-step operation and breakpoint operation capability from the PC4000 debugging machine keyboard.
(4) Program memory interface circuit
Debugging frunctions such as confirmation of internal
connector and this board is connected to the user system
by means of an accessory cable.
(2) EPROM with the PC4000 minotor program
register contents.
•
(5) Input/output buffer/latch circuit
The PC4000 is connected to this board using a card edge
Can be used with external and internal clocks.
FUNCTION
APPLICATIONS
The debugging machine PC4000 operates as a debugging
The development of hardware and software for systems
machine for the MELPS 42 using the contents of the
using the MELPS 42 (M58497-XXXP) single-chip micro-
monitor ROM mounted on the dedicated board. The
computers.
evaluation chip
(M58497-000P)
loaded on
the board
executes the program stored in the program memory in the
PC4000 debugging machine.
The internal status of the evaluation chip is read out
under monitor CPU control when single-step operation and
breakpoint operation are halted.
BLOCK DIAGRAM-
I,
EIT INSTRUCTION
GENERATOR
OUTPUT PORT
LATCH
INSTRUCTION
;1-_ _ _ _---.;--_~
2+ 8
PORT P
I PORT F
INSTRUCTION
DATA BUFFER
26+ 2
PORT I_C
PORT
COM
I
4+4
PORT K
PORT S
M58497
-ooop
OUTPUT PORT
LATCH
11
1
PORT D
COMPARISON
ADDRESS I - - - - - f - - - - - - + - - - - - - - '
12
ADDRESS 1----------,'---_-..-1
8
PCA4000 MONITOR
INSTRUCTION
(MONITOR)
IE---~'----~
ROM 2732x2
•
13-32
CLOCK
GENERATOR
MITSUBISHI
~ELECTRIC
I
J
MITSUBISHI MICROCOMPUTERS
PCA4014
MELPS 42 DEDICATED BOARD
SPECI FICATIONS
Item
Applicable microcomputer
Specification
M58497-XXXP
I
Clock
Package
480KHz
frequencyrC7a:-:Cr C::-,aCo
bl-:-e-+--2---4-.-2M-H-Z-3-2-K-H-L- - - - - - - - - - 1
range
Iv
Applicable debugging
machine
Power supply
Connector to user's
system
Debugging functions
(contents of monitor
EPROM)
PC4000
(connected by a card edge connector)
Supplied from the PC4000 when insweted into the
debugging machine
Bv an accessory cable
•
Program execution from any address and halt
•
Single-step operation
•
Data writing to EPRmA and reading
•
Confirmation and change of the contents of
program RAM
•
Serial data transfer to an external device
•
Confirmation and change of the RAM in the
evaluation chip (M58497-000P) and the coments
of the following registers and flags
•
Data pointer
•
Accumulator
•
B register
•
CY flag
• MITSUBISHI
"ELECTRIC
13-33
MITSUBISHI MICROCOMPUTERS
PCA8400
MELPS 8·48 DEDICATED BOARD
DESCRIPTION
CONFIGURATION
The PCA8400 is a dedicated MELPS 8-48 board for use
with the PC4000 debugging machine for the 8-bit single-
As can be seen in the block diagram, the PCA8400 consists
of the following hardware:
chip microcomputers and is used by inserting the board in
the PC4000 cabinet.
(1) Evaluation chip (M5L8039P-6) and peripheral circuitry
(2) ROM with the PC4000 monitor program
FEATURES
(4) Program memory interface circuit
•
Connection to user's system by means of a 40-pin D I L
plug
(5) Input/output buffer/latch circuit
•
Control circuits and connectors for the M5L8748S
writing adaptor (PC4100)
(3) Single-step and breakpoint control circuit
The PC4000 is connected to this board using a card
edge connector and this board is connected to the user
system by means of an accessory cable.
FUNCTION
APPLICATIONS
The debugging machine PC4000 operates as a debugging
The development of hardware and software for systems
using the MELPS 8-48 8-bit single-chip microcomputers.
machine for the MELPS 8-48 using the contents of the
monitor ROM mounted on the dedicated board. The
evaluation chip (M5L8039P-6) loaded on the board executes the program stored in the program memory in the
PC4000 debugging machine.
The internal status of the evaluation chip is read out
under monitor CPU control when single-step operation and
breakpoint operation are halted.
An interface and connector to enable connection to the
M5L8748S writing adaptor PC4100 has been provided,
allowing programs to
be written and read from the
M5L8748S.
BLOCK DIAGRAM
PORT DIRECTION
~--->,"---~ PORT D
SWITCHI~JG CIRCUIT
COMPARISON
_ ADDRESS
~~PORTP1
ADDRESS LATCH
SINGLE-STEP
CONTROL CI RCUIT
PORT SWITCHING
CIRCUIT
CLOCK
GENERATOR
I
ADDRESS
~
PC4000
MONITOR ROM
M5L2732KX 2
I
INSTRUCTION
DATA
8
M5L8155P
I
J
M5L8748S INTERFACE PORT
-
13-34
-
-
• MITSUBISHI
.... ELECTRIC
-
-
--
TO PC4100
M51_8748S
WRITER
MITSUBISHI MICROCOMPUTERS
PCA8400
MELPS 8-48 DEDICATED BOARD
SPECI FICATIONS
Item
Applicable
microcomputers
Package
Clock
I
frequency I Variable
range
Specification
M5L8048-XXXP
M5L8049-XXXP
M5L8748S (PC4100)
M5L8039P-6
6.144MHz
1-6.144MHz (By changing the oscillator crystal)
--
Applicable debugging
machine
PC4000 (connected by a card edge connector)
Power supply
Supplied from the PC4000 when inserted into the
debugging machine
Connection to user's
system
By an accessory cable
Debugging functions
(contents of monitor
EPROM)
•
•
•
·
·•
·••
Other
Program execution from any address and halt
Data writing to EPROM and reading
Confirmation and change of the contents of program
RAM
Serial data transfer to an external device
Confirmation and modification of the RAM date1 in
the evaluation chip
(M5L8039P-6) and the contents of the following
registers and flags:
Program counter
Accumulator
PSW
By connecting the PC41 00, read and write operations
to the M5L8748S can be performed.
• MITSUBISHI
.... ELECTRIC
13-35
MITSUBISHI MICROCOMPUTERS
PC4100
MSL8748S PROGRAMMING ADAPTOR
DESCRIPTION
SPECIFICATIONS
The PC4100 is a programming adaptor for use in writing a
Item
program developed on a MELPS 8-48 'dedicated PCA8400
board in a PC4000 debugging machine into the internal
EPROM of the M5L8748S single-chip microcomputer.
Specification
Applicable microcomputer
M5L8748S
PCA8400 (ME LPS 8-48 dedicated board)
Match i ng boards
(Connected by a flat cable)
Supplied from the PC4000 debugging machine when
Power supply
FEATURES
•
Interfaced to the PC4000 debugging machine and MEL-
•
A protective circuit prevents misinsertion of the device
PS 8-48 board by means of a connector.
Textool zero insertion force 40-pin socket
Connector
Power supply is switched on and off by means of a
Misinsertion protection
read relay
Outer dimension
to be writtin into
•
connected to the PCA8400
200 (L) x 130 (W) x 38 (H)mm
No external power supplv is required
APPLICATIONS
Data writing into the M5L8748S
BLOCK DIAGRAM
-
~
------
-
-
40-PI N SOCKET
LEVEL INTERFACE
M5L87485
-
=J
I
CONNECTED
TO PCA8400
I
CONTROL CIRCUIT
I
(5V) Vee
DC-DC CONVERTER
-
13-36
-
• MITSUBISHI
"ELECTRIC
-
MITSUBISHI MICROCOMPUTERS
PCA4301
MELPS 4 EVALUATION BOARD
CONFIGURATION
DESCRIPTION
The PCA4301 evaluation board is used as an evaluation
As can be seen in the block diagram, the PCA4301 cQnsists
board for MELPS 4 4-bit single-chip microcomputers.
of the following hardware.
When used in the external ROM mode, this board
(1) Evaluation chip and peripheral circuitry
consists of the evaluation chip (M58842S) and the program
(2) Program EPROM socket
EPROM (M5L2716K), possessing equivalent functions to
(3) EPROM power supply circuit
the masked ROM M58840-XXXP and M58841-XXXSP.
When creating the mask for a developed program, this
The board and user system can be connected by means
of an accessory cable.
board is suitable for program verification and running tests.
SPECIFICATIONS
FEATURES
Item
Specification
•
Board computer equivalent to the M58840-XXXP and
M58841-XXXSP
Type
CPU
Mitsubishi Electric M58842S
•
•
Simple program modification using an EPROM
Connection to user's system by means of a cable
Cycle time
lOllS (when using a CF600kHz)
•
Built-in clock generator
Memory
4-bit parallel processor
i EPROM(H)
I ERROM(L)
Built-in clock
APPLICATIONS
Program and applications equipment development for
MELPS 4 4·bit single-chip microcomputers.
FUNCTIONS
2K byte Lower order 8 bits (M5L2716K)
CR
300-600kHz
CF
600kHz
Interrupts
1 level, 1 factor
Connector used
50-pin straight header
Supporting devices
PC 4000 (single-chip microcomputer debugging
machine) with PCA4001 (M 58840-XXXP board)
mounted
The evaluation chip (M58842S) outputs the value of the
program counter, and reads and executes the instruction
stored in the appropriate EPROM address.
2K byte Upper order 1 bit (M5L2716K)
•
-1 5V± 10% (single supply)
Power supply current: 250mA (max) (during
• execution
a NOP instruction)
Power supply
Outer dimensions
106.7 (L) x 125 (W) x 15 (H)mm
It is possible to have this board emulate the operation of
a single-chip microcomputer.
BLOCK DIAGRAM
I
CNVoo
VDD~I~~--------------------------~~-------i--~~-iVDD
INT ~-------------i I NT INPUT
T4 ....------~I
1'4 OUTPUT
Vss
GNDI~--------------------~::::::J:::::~--l---JL~vss
11
Do - D10 ~-----'<---------3;..j DIN PUT /
I OUTPUT
~-----------------:;~-----------------1Ao -
11
ro--'
I
A10
M58842S
XOUT
r-f
=
W21
~
:0
I
L __ .J
XIN
15
Ko-K14toE-~-------i AK INPUT
"------------~~-----___;;~----__110-18
RES/VREF
RE SH/VREF f--------------------------------------~t--__q
• MITSUBISHI
"ELECTRIC
·---lw1
L._?
t:
J
I
AK 14/RESH
RES/VREF MIXER
13-37
II
MITSUBISHI MICROCOMPUTERS
PCA4303
MELPS 4 EVALUATION BOARD
DESCRIPTION
CONFIGURATION
The PCA4303 evaluation board is used as an evaluation
As can be seen in the block diagram, the PCA4303 consists
board for MELPS 4 4-bit single-chip microcomputers.
of the following hardware.
When used in the external ROM mode, this board
consists of the evaluation chip (M58842S) and the program
(1) Evaluation chip and peripheral circuitry
(2) Program EPROM socket
EPROM (M5L2716K)
(3) EPROM power supply circuit
possessing equivalent functions to
The board and user system can be connected by means
the masked ROM M58843-XXXP. When creating the mask
of an accessory cable.
for a developed program, this board is suitable for program
verification and running tests.
SPECI F ICATIONS
FEATURES
Specification
Item
•
Board computer equivalent to the M58843-XXXP
•
Simple program modification using an EPROM
•
•
Connection to user's system by means of a cable
Built-in clock generator
1---
Type
CPU
Mitsubishi Electric rl158842S
Cycle time
10,us (when using a CF600kHz)
Memory
APPLICATIONS
4-bit parallel processor
1_
EPROM(H)
2K byte Upper order 1 bit (M5L2616K)
I
ERROM(L)
2K byte Lower order 8 bits (M5L2716K)
Built-in clock
Program and applications equipment development for
CR
300 - 600 kHz
CF
600kHz
Interrupts
1 level, 1 factor
Connector used
50-pi n straight header
MELPS 4 4-bit single-chip microcomputers.
FUNCTION
PC 4000 (single-chip microcomputer debugging
machine) With PCA4003 (M 58843-XXXP board)
mounted
Supporting devices
The evaluation chip (M58842S) outputs the value of the
program counter, and reads and executes the instruction
•
•
Power supply
stored in the appropriate EPROM address.
It is possible to have this board emulate the operation of
Outer dimensions
- 15V ±; 0% (single supply)
Power supply current: 250mA (max) (during execution an NOP instruction)
106.7 (L) x 125 (W) >: 15 (H)mm
a single-chip microcomputer.
BLOCK DIAGRAM
1-
r
I
I
Voo
-
-
-H·
INSTRUCTION ROM
POWER SUPPLY
GND
I
r-
CNVoo
INT
Voo
T4'
~
INT INPUT
I
8
SO-S71"""'"
C
I
VSS
VSS
1'4
11
Do -010
OUTPUT
S INPUT/
OUTPUT
D INPUT/
I OUTPUT
I
I
INSTRUCTION ROM
(UPPER ORDER)
I
/1.0-1110
(1
f1
INSTRUCTION ROM
(LOWER ORDER)
l,
~8
ro--'
I
OJ
r
f
I
= W21
I
M58842S
XOUT
~I
:0 ot-
I
XIN
L __ .J
Ko-K14
9
10-18
RES/VREF
t=_____
I
"ESHIVRCC
13-38
• MITSUBISHI
..... ELECTRIC
15
4;,~i~lwl ,
AK INPUT
L._
.J
~
J
-I
RES/VREF MIXER
I
I
--~
MITSUBISHI MICROCOMPUTERS
PCA4304
MELPS 4 EVALUATION BOARD
DESCRIPTION
CONFIGURATION
The PCA4304 evaluation board is used as an evaluation
As can be seen in the block diagram, the PCA4304 consists
board for MELPS 4 4-bit single-chip microcomputers.
When used in the external ROM mode, this board
consists of the evaluation chip (M58842S) and the program
of the following hardware.
(1) Evaluation chip and peripheral circuitry
(2) Program EPROM socket
EPROM (M5L2716K), possessing equivalent functions to
the masked ROM M58844-XXXSP. When creating the mask
(3) EPROM power supply circuit
The board and user system can be connected by means
for a developed program, this board is suitable for program
verification and running tests.
of an accessory cable.
SPECI FICATIONS
FEATURES
Specification
Item
•
•
Board computer equivalent to the M58844-XXXSP
Simple program modification using an EPROM
•
•
Connection to user's system by means of a cable
Built-in clock generator
Type
CPU
Mitsubishi Electric M58842S
Cycle time
lOps (when using a CF600kHz)
1--
Memory
APPLICATIONS
4-bit parallel processor
I EPROM(H)
I ERROM(L)
Built-in clock
Program and applications equipment development for
MELPS 4 4-bit single-chip microcomputers.
Interrupts
2-K byte Upper order 1 bit (M5L2616K)
2K byte Lower order 8 bits (M5L2716K)
CR
300-600kHz
CF
600kHz
1 level, 1 factor
1----
FUNCTION
Connector used
50-pin straight header
Supporting devices
PC 4000 (single-chip mlcroconputer debugging
machine) with PCA 4004 (M 58844-XXX SP dedicated board) mounted
The evaluation chip (M58842S) outputs the value of the
program counter. and reads and executes the instruction
Power supply
stored in the appropriate EPROM address.
It is possible to have this board emulate the operation of
a single-chip microcomputer.
Outer dimensions
.•
- 15V ±1 0% (single supply)
Power supply current: 250mA (max)
(during execution an NOP instruction)
106J (L) x 125 (W) x 15 (H)mm
BLOCK DIAGRAM
I
' ~--------------------~:::::j~::::~~--~~-I
Voor
CNVoo
INT
Voo
T4
INT INPUT
I
SO-S7
S INPUT/
OUTPUT
VSS
GND~I~--------------------------~~------~--~~~ VSS
T4 OUTPUT
11
Do -DlD
D INPUT/
I OUTPUT
AO-AID
10--'
I
M58842S
XOUT
r--f
= W21
L-Jo
I
XIN
1
10
L __ .J
15
Ko-K14
9
--7
AK INPUT
10-18
RES/vREF
RESH/VRFE r---------------------------------------------------~~_a
• MITSUBISHI
;"'ELECTRIC
II
RES/VREF MIXER
13-39
MITSUBISHI MICROCOMPUTERS
PCA430S
MELPS 4 EVALUATION BOARD
DESCRIPTION
CON·FIGURATION
The PCA4305 evaluation board is used as an evaluation
As can be seen in the block diagram, the PCA4305 consists
of the following hardware.
board for MELPS 4 4-bit single-chip microcomputers.
consists of the evaluation chip (M58845-000SP) and the
(1) Eva!uation chip and peripheral circuitry
(2) Program EPROM socket
program EPROM (M5L2716K), possessing equivalent func-
(3) EPROM power supply circuit
tions to the masked ROM M58845-XXXSP. When creating
The board and user system can be connected by means
of an accessory cable.
When used in the external ROM mode, this board
the mask for a developed program, this board is suitable for
program verification and running tests.
FUNCTION
FEATURES
The evaluation chip (M58845-000SP) outputs the value of
•
Board computer equivalent to the M58845-XXXSP
the program counter, and reads and executes the instruc-
•
Simple program modification using an EPROM
tion stored in the appropriate EPROM address.
•
Connection to user's system by means of a cable
•
Built-in clock generator
It is possible to have this board emulate the operation of
a single-chip microcomputer.
APPLICATIONS
Program and applications equipment development for
MELPS 4 4-bit single-chip microcomputers.
BLOCK DIAGRAM
11
(Ov) VSS r - - - - - - - - - - - - - - - - - - - - - - - - - ,
(-15V)VODr------_ _ _~-----_--------
RE06~i~~~CVREFH
.......-...l.......,
INTERRUPT CINTH ~--'\rw-,~
REQUEST SIGNAL
I
PORT S {CPS7H
INPUT/OUTPUT
CP~OH
11
CPK7H
I
CPKOH
PORT F rCPpH
CPFOH
INPUT/OUTPUT
TIMER
CPTIO
INPUT/OUTPUT
12
PORT K INPUT {
~10 EPROM
Ao M5L2716K
1
RESET INPUT
~7
Ao M5L2716K Do
A 10 EPROM
I
CPRSH
12
I
T~~~~ATOR
PORT D
INPUT/OUTPUT
13-40
r CPDllH
l CpJOH
~-_-=--=--=--=--=--=--=--=--=--=------------------...
----""""
• MITSUBISHI
"ELECTRIC
MITSUBISHI MICROCOMPUTERS
PCA430S
MELPS 4 EVALUATION BOARD
SPECIFICATIONS
Item
Specification
Type
4-bit parallel processor
CPU
M 58845- ODDS P
Cycle time
Built-in 455kHz clock
Program memory: 2048 words x 9 bits
(M5L2716K x2)
Memory
Data memory: 128 words x 4 bits
(Built-in M58845-XXXSP)
K
S
I/O
Analog input
1 bit x 8
Output
8 bits x 1
Input
4 bits x 2
Output
1 bit x 12
0
Sense input
1 bit x 12
Output
4 bits x 1
Input
4 bits x 1
F
A-D converter
Built-in, ±3 LSB ± accuracy
Touchkey interface
Built-in
Subroutine nesting
3 levels (including 1 level of interrupt)
Clock generator
Built-in (ceramic filter or RC circuit)
Timers
2
Interrupts
INT pin
Power supply
- 15V ±5%, 500mA (max)
Connector used
68 conductor (34 each side) card-edge connector
Outer dimensions
190 (L) x 180 (W) x 20 (H)mm
• MITSUBISHI
.... ELECTRIC
13-41
MITSUBISHI MICROCOMPUTERS
PCA4101
MELPS 41 EVALUATION BOARD
DESCRIPTION
CONFIGURATION
The PCA4101 evaluation board is used as an evaluation
As can be seen in the block diagram, the PCA4101 consists
board for MELPS 41 4-bit single-chip microcomputers.
of the following hardware.
When used in the external ROM mode, this board
consists of the evaluation chip (M58494-000P) and the
(1) Evaluation chip and peripheral circuitry
program EPROM (M5L2716K), possessing equivalent func-
(3) Timing generator
(2) Address data latch circuit
tions to the masked ROM M58494-XXXP. When creating
(4) Program EPROM socket
the mask for a developed program, this board is suitable for
(5) Port input/output latch buffers
program verification and running tests.
The board and user system can be connected by means
of an accessory cable.
FEATURES
•
Board computer equivalent to the M58494-XXXP
FUNCTION
•
Simple program modification using an EPROM
The evaluation chip (M58494-000P) performs time division
•
Connection to user's system by means of a cable
•
Built-in clock generator
of part of the port contents, outputs the value of the
program counter, and reads in instryctions from the
EPROM and executes them. Port output buffer and latch
APPLICATIONS
control timing is derived from either an internal or an
Program and applications equipment development for
external clock generator. This board is usable to emulate
MELPS 41 4-bit single-chip microcomputers.
the operation of the single-chip microcomputer.
BLOCK DIAGRAM
----(SV) Vee
(OV)GND
1~~~~~~nCPI NT A
SIGNALS \..CPI NT B
~
INTB
SERIES DATA
I
INPUT/{· CPCLK
OUTPUT
PORTS CPDATA
-
ClK
~
I
DATA
ABo
J
ADDRESS
DATA BUFFER
INTA
ABI,
-
------
~
1
S-.h
I>
}11
8
Q7-QO
PORT D J CPD3H I
INPUT/ \
\
OUTPUT l CPDOH
PORT R
J CPR7H
PORT S { CPS7H I
11
'\
CPXIN
12
T7-To
I
f----3.
XOUT
10
CLOCK
GENERATOR
~
PORT Q r CPQ7H
INPUT/]
\
OUTPUT l CPQOH
PORT U {CPU3H
OUTPUT
\
8
OUTPUT
13
42
l CdAOH
~
A1O- A O
EPROM
M5L2716K
EPROM
M5L2716K
~~
+2
1
~
4
'"I
r-==l
rl
I
~ GENERATOR
TIMING
I
PORT Q
OUTPUT
LATCH CIRCUIT
10
07-00
18
~
I
CPUOH
PORT A {CPAllH
PORT Q
INPUT BUFFER
C?
I
{2
07 - Do
t
CPXOUT
07-00
I8
A1O- A O
4
¢
XIN
EPROM
M5L2716K
~~
~
S7- S0
8
l CPTOH
11
A1O- A O
07 -Do
U2
U3
CdSOH
PORT T J CP\T7H
OUTPUT
8
2
EPROM
M5L2716K
2
Uo
U,
8
OIU~~UT+ l CdROH
OUTPUT
M58494 - 000 P
R7- RO
1
CHIP SELECT
CI RCUIT
A1O- AO
4
03- D O
-
PORT U OUTPUT
LATCH CIRCUIT
PORT A OUTPUT
LATCH CIRCUIT
I
12
-
• MITSUBISHI
..... ELECTRIC
-----
-
J
MITSUBISHI MICROCOMPUTERS
PCA4101
MELPS 41 EVALUATION BOARD
SPECIFICATIONS
Item
Type
Specification
4-bit parallel processor
Evaluation chip
Clock
frequency
I Internal
I Range
Memory
M58494-000P
250kHz
lOO-350kHz
Program memory: 4K words x 10 bits
(M5L2716K x 4)
Data memory:
Internal:
External:
32 x 4 bits
1024 words x 4 bits
Input/output ports: for a total of 20 lines
I/O
Ro-R7, 00-07, 00-03
Output ports: for a total of 32 lines
Ao-A",
UO-U3, SO-S7, To-T7
INTA
Interrupts
INTB
Timer
Power supply
5 V± 5%
Connector used
Two 50-pin angled headers
•
MITSUBISHI
~ELECTRIC
13-43
MITSUBISHI MICROCOMPUTERS
PCA4201
MELPS 42 EVALUATION BOARD
DESCRIPTION
FUNCTION
The PCA4201 evaluation board is used as an evaluation
The evaluation chip (M58496-000P) performs time division
board for MELPS 42 4-bit single-chip microcomputers.
of part of the port contents, outputs the value of the
When used in the external ROM mode, this board
program counter, and reads;in instructions from the EPROM
consists of the evaluation chip (M58496-000P) and the
and executes them. Pprt output buffer and latch control
program EPROM (M5L2716K), possessing equivalent func-
timing is derived from either an internal or an external
tions to the masked ROM M58496-XXXP. When creating
clock generator. This board is
the mask for a developed program, this board is suitable for
operation of the single-chip microcomputer.
usable to emulate the
program verification and running tests.
CONFIGURATION
FEATURES
As can be seen in the block diagram, the PCA4201 consists
•
Board computer equivalent to the M58496-XXXP
of the following hardware.
•
•
Simple program modification using an EPROM
Connection to user's system by means of a cables
(1) Evaluation chip and peripheral circuitry
•
Built-in clock generator
APPLICATIONS
(2) Address data latch circuit
(3) Timing generator
(4) Program EPROM socket
(5) Port loutput latch
Program and applications equipment development for
MELPS 42 4-bit single-chip microcomputers.
The board and user system can be connected by means
of accessory cables.
BLOCK DIAGRAM
PKOH
\
PK3H
4
T2'
4
PSOH
\
PS3H
PLCOH
\
PCOM3H
VLCD
PWONH
PWOFFL
RES(PV)H
INTAH
INTBH
S
I
i4'
29
11
~--------+---------~
11
POOH
\
P OlOH
1---------------------;... VLCD
3
Pw(ON)
1--------+---------;...Pw(OFF
I
RES(PV)
INTA
1NTs
BOIN I--------------------..;~ BOIN
10
PFOH
\
PF7H
PPOH
PP1H
13-44
• MITSUBISHI
"ELECTRIC
MITSUBISHI MICROCOMPUTERS
PCA4201
MELPS 42 EVALUATION BOARD
SPECI FICATIONS
Specification
Item
Type
4-bit parallel processor
Evaluation chip
M58496 -OOOp
Clock
frequency
llnternal
4.19MHz
I Range
2-4.2MHz
Memory
--
Program memory: 2K words x 10 bits
(M5L2716K x21
Data memory: 128 words x 4 bits
Dedicated LCD
ports
Input ports
Total of
LCO- LC24
}
COMo-COM3 28 lines
KO-K3
SO-S3
I/O
Output ports
Fo-F7
00- 0 10
PO, Pl
Interrupts
of
} Total
8 lines
) Total of
21 lines
I NT A, I NT B, clock interrupt
Power supply
5 V ± 10%
Connector used
Two 50-pin angled headers
• MITSUBISHI
.... ELECTRIC
13-45
MITSUBISHI MICROCOMPUTERS
PCA4202
MELPS 42 EVALUATION BOARD
DESCRIPTION
FUNCTION
The PCA4202 evaluation board is used as an evaluation
board for MELPS 42 4-bit single-chip microcomputers.
The evaluation chio (M58497-000P) performs time division
of part of the port contents, outputs the value of the pro-
When used in the external ROM mode, this board
consists of the evaluation chip (M58497-000P) and the
program EPROM (M5L2716K), prossessing equivalent func-
gram counter, and reads in instructions from the EPROM
and executes them. Port output buffer and latch control
timing is derived from either an internal or an external
tions to the masked ROM M58497-XXXP. When creating
clock generator. This board is usable to emulate the opera-
the mask for a developed program, this board is suitable for
tion of the single-chip microcomputer.
program verification and running tests.
CONFIGURATION
FEATURES
•
Board computer equivalent to theM58497-XXXP
As can be seen in the Block Diagram, the PCA4201 consist
of the following hardware.
•
Simple program modification using an EPROM
(1) Evaluation chip and peripheral circuitry
•
Connection to user's system by means of flat cables
•
Built-in clock generator
(2) Address data latach circuit
(3) Timing generator
(4) Program EPROM socket
APPLICATIONS
Program
(5) Port input/output latch buffers
and applications equipment development for
The board and user system can be connected by means
of an accessory cable.
MELPS 42 4-bit single-chip microcomputers.
BLOCK DIAGRAM
POWER
SUPPLY
--------------------PKOL
\
PK3L
4
PSOL
\
PS3L
4
K
S
POOL
PLCOH
\
P LCM 1H
28
RES{PW}H
INTAH
INTBH
BOIN
\
I
2
VLCD
1/2 VLCD
RES(PW}L
T2
T4
I
INTA
1NTs
F&P
M5849
-xxxP
XINO
13-46
• MITSUBISHI
..... ELECTRIC
POJOL
MITSUBISHI MICROCOMPUTERS
PCA4202
MELPS 42 EVALUATION BOARD
SPECJFICATIONS
Item
Specification
4-bit parallel processor
Type
M58497 -OOOP
Evaluation chip
Clock
frequency
I
I
Memory
Package
Divider
480KHz
32KHz
Program meory
2K words x 10 bits
(M5L2716K x 21
Data memory
Dedicated LCD
ports
Input/output
I/O
ports
Output ports
128 words x 4 bits
LC O-LC 2 5
} Total of
28 lines
COM o-COM 1
K o -K3
SO-S3
Fo-F 7
Do-OlD
} Total of
81mes
} Total of
21 lines
Po, P1
Interrupts
INTA, INTS, clock interrupt
Power supply
5V ± 10%
Connector used
Two 50-pin angled headers
., MITSUBISHI
.... ELECTRIC
13-47
MITSUBISHI MICROCOMPUTERS
PCA8402
MELPS 8·48 EV ALUTION BOARD
CONFIGURATION
DESCRIPTION
The PCA8402 evaluation board is used as an evaluation
As can be seen in the block diagram, the PCA8402 consists
board for MELPS 8-48 8-bit single-chip microcomputers.
of the following hardware:
This board consists basically of the external ROM chip
(1) Evaluation chip and peripheral circuitry
(M5L8039P-6) and EPROM (M5L2716K), possessing equi-
(2) Program EPROM socket
valent functions to the masked ROM M5L8048-XXXP and
(3) EPROM power supply circuit
M5L8049-XXXP. When creating the mask for a developed
The board and user system can be connected by means
program, this board is suitable for program verification and
of an accessory cable.
running tests.
FEATURES
•
Board computer equivalent to the M5L8048-XXXP and
SPECIFICATIONS
M5L8049-XXXP
•
•
•
Item
Simple program modification using an EPROM
Connection to user's system socket by means of a 40-pin
DIL plug
Built-in clock generator
Specification
Type
80b it para lIel processor
CPU
M5L8039P-6 (equivalent to Intel 8039-6)
Cycle time
Clock supplied by user system (maximum 6MHz)
Memory
Program memory: 2K bytes (M5L2716K)
128 bytes (built-in M5L8039P-6)
Data memory:
APPLICATIONS
Program and applications equipment development for
MELPS 8-48 8-bit single-chip microcomputers.
FUNCTION
8-bit parallel port x3
Test pin x2
I/O
The evaluation chip (M5L8039P-6) outputs the value of the
Interrupts
program counter and reads in instructions from E R ROM
and executes them.
The board is equivalent in operation to a single-chip
microcomputer.
1-
INT pin
Power supply
5V ±5%, 500mA (max)
Connector used
40-pin 01 L IC socket
Outer dimensions
60 (L) x 65 (W) x 30 (H)mm
BLOCK DIAGRAM
J
M5L8039P-6
PSEN
+5V- EA
2
CLOCK
Xl, Xl
-
Pl
P2 UPPER ORDER 4 BITS
A
DB f-+-i~
ADDRESS
LATCH
Pl
TEST PIN T 1
ALE
To
PORT 2
UPPER
ORDER BITS
TEST PIN TO
~
J
t
1
ALE
4
T1
DATA BUS
PORT
INPUT
BUFFER
J
PO WR
P2 LOWER ORDER 4 BITS
m
~A
ROM
r--'"'
PORT 2
UPPER
ORDER BITS
4
I
ADDRESS
8
8
I
J
OE
J
f--
~
PORT 2
~~T2BUFFER
I
OUTPUT LATCH
I
DATA BUS
PORT
OUTPUT
LATCH
DB
I
f-I
-
RD WR
13-48
• MITSUBISHI
"ELECTRIC
-
-
I
MICROCOMPUTER SOFTWARE
MITSUBISHI LSls
SOFTWARE CODES
SOFTWARE CODES
Software products for Mitsubishi's MELPS microprocessors are designated by the following alphanumeric codes.
1. PROGRAMS
Example: G A
1 AS 0101
1---+_+--+_-+__ G: Mitsubishi MELPS microprocessor software
1-..--+----4----4-- Kind of microprocessor
1----+---4---
L------4--
A:
MELPS 8/85 8-bit parallel CPU
C:
Single-chip 8-bit microcomputer
B:
Single-chip 4-bit microcomputer
Z:
General
Operation system
1: For host computer systems
2: For target computer systems
Kind of
AP:
AS:
CR:
program
Application program
Assembler
Control program
DP:
Diagnostic program
OS:
operation system
SB: Subroutine
SM: Simulator
SP: Service program
TL:
TS:
Compiler
Test program
Identifying serial number
2. MANUALS AND SUPPORT MATERIALS
Example:
GAM
- ~
SR 00 - 01 A (6r- 2 B
0)
r- r~;..;.
r..;.,~
';"r-
G:
Mitsubishi MELPS microprocessor software
Kind of microprocessor
A: MELPS 8/85 8-bit parallel CPU
B:
Single-chip 4-bit microcomputer
C:
Z:
Single-chip 8-bit
microcomputer
General
L anguage
E: English
M: Japanese
Kind of
'HR:
PS:
SH:
SR:
SS:
Material
Hardware manual
Program manual
Consumables
Software manual or operating manual
Software support materials
I dentifying serial number
Availability
A: Unrestricted
Year of issue-last digit, starting from 1976 = 6
Month of issue
1: Ja~uary
9: September
X: October
Y: November
Z: December
Fully revised edition
A: First
B: Second
etc.
-
Partial revision (advance of full revision resets to 0)
• MITSUBISHI
.... ELECTRIC
14-3
MITSUBISHI LSls
M'ELPS4/41 SOFTWARE
AVAILABLE MATERIALS
HOST PROGRAMS
Normal
S
I
L-_ _ _ _ _ _ _.....::....._Pr_o.;;.gr_a_m_ _ _ _ _ _ _ _ _ _...I..._ _
P_ro.;;.g_ra_m_c_o_d_e_n_um_b_e_r_......L._ shipping media_....._ _ _ _o_u_rc_e_an...;g_u_ag_e_ _ _ _--'
MELPS 4 Cross Assembler-MELCOM 70
GBIASOO01
Magnetic tape
FORTRAN (part in assembler)
MELPS 4 Cross Assembler-MELCOM 7000 or COSMO 700
GBIASOO02
Magnetic tape
FORTRAN
MELPS 4 Simulator-MELCOM 70
GBISMOO01
Magnetic tape
FORTRAN (part in assembler)
MELPS 4 Paper-Tape Generation Program for PROM Writers~
MELCOM 70
GBISPOO01
Magnetic tape
FORTRAN (part In assembler)
MELPS 4 Paper-Tape Generation Program for PROM WrltersMELCOM 7000 and COSMO 700
GBISPOO02
Magnetic tape
FORTRAN (part in assembler)
MELPS 41 Cross Assefnbler-MELCOM 70
GBIASOO03
Magnetic tape
FORTRAN (part
MELPS 41 Simulator-MELCOM 70
GBISMOO02
Magnetic tape
FORTRAN (part in assembler)
MELPS 41 Paper-Tape Generation Program for PROM WritersMELCOM 70
FORTRAN (part in assembler)
In
assembler)
GBISPOO03
Magnetic tape
ME LPS 42 Cross Assembler-ME LCOM 70
GBIAS0010
Magnetic tape
FORTRAN (part in assembler)
MELPS 42 Simulator-MELCOM 70
GBISMOO06
Magnetic tape
FORTRAN (part in assembler)
ME LPS 42 Paper-tape Generation Program for
PROM Writers-ME LCOM 70
GBISPOO06
Magnetic tape
FORTRAN (part in assembler)
Manual number
Number of pages
MELPS 4 Assembler Language Manual
GBM-SROO-01A
127
MELPS 4 Cross Assembler Manual-MELCOM 70
GBM-SROO-02A
68
MELPS 4 Cross Assembler Operating Manual-MELCOM 70
GBM-SROO-03A
16
MELPS 4 Simulator Manual-MELCOM 70
GBM-SROO-04A
102
MELPS 4 Simulator Operating Manual-MELCOM 70
GBM-SROO-05A
23
Manuals
(In
Japanese)
MELPS 4 CROSS ASSEMBLER MANUALS
MELPS 4 SIMULATOR MANUALS
MELPS 4 PAPER-TAPE GENERATION PROGRAM MANUALS FOR PROM WRITERS
MELPS 4 Paper-Tape Generation Program Manual for PROM Writers-MELCOM 70
GBM-SROO-06A
MELPS 4 Paper-Tape Generation Program Operating Manual for PROM Writers-MELCOM 70
GBM-SROO-07A
17
MELPS 4 HANDBOOK
MITSUBISHI MELPS 4 Single-Chip 4-Bit Microcomputer Handbook-Support Software (Note 1)
GBM-SR10-01A
200
MELPS 41 Assembly Language Manual
GBM-SROO-08A
162
MELPS 41 Cross Assembler Manual-MELCOM 70
GBM -SROO-09A
75
MELPS 41 Cross Assembler Operating Manual-MELCOM 70
GBM-SROO-10A
8
MELPS 41 Simulator Manual
GBM-SROO-11A
93
MELPS 41 Simulator Operating Manual
GBM-SROO-12A
Note1: Includes contents of all above manLials concerning MELPS 4 software
MELPS 41 CROSS ASSEMBLER MANUALS
MELPS 41 SIMULATOR MANUALS
MELPS 41 PAPER-TAPE GENERATION PROGRAM MANUALS FOR PROM WRITERS
MEL~S 41 Paper-Tape Generation Program Manual for PROM Writers- MELCOM 70
GBM-SROO-13A
MELPS 41 Paper-Tape Generation Program Operating Manual for PROM Writers-MELCOM 70
GBM-SROO-14A
14-4
• MITSUBISHI
.... ELECTRIC
11
MITSUBISHI LSls
MELPS 4/41 SOFTWARE
AVAILABLE MATERIALS
MELPS 42 CROSS ASSEMBLER MANUALS
I MELPS 42 Cross Assembler Manual-MELCOM 70
GBM-SROO-31A
34
GBM-SROO-32A
86
MELPS 42 SIMULATOR MANUALS
MELPS 42 Simulator Manual
MELPS 42 PAPER-TAPE GENERATION PROGRAM MANUALS FOR PROM WRITERS
MELPS 42 Paper-Tape Generation Program Manual for PROM Writers-ME LCOM 70
• MITSUBISHI
"ELECTRIC
GBM-SROO-33A
21
14-5
MITSUBISHI LSI.
MELPS 4/41 SOFTWARE
GENERAL DESCRIPTION
MELPS 4/41 software is the name used to designate a
software series provided by Mitsubishi for development
application programs for equipment in which single-chip
microcomputers are used.
MELPS 4/41 software is used as a tool to develop
application programs, and comprises all the programs
-assembly, PROM programming and mask makingnecessary to the manufacture of single-chip microcomputers.
MELPS 4/41 SOFTWARE CONFIGURATION
Translates a symbolic source program written in
assembly language and produces as output an
object program in machine language.
There are many kinds of control data and
instruction codes and other functions can be
changed easily
In MELPS 41. the coding format of is free and
a number of input media can be used to Input the
source program.
Executes and checks a user's program on the pseudo
CPU of the host computer. This allows more efficient
program debugging and provides more extensive
checking than can be accomplished by hardware
binary object programs and
hexadecimal form
tape for PROM writers of
Takeda Riken
Both MELPS 4 and MELPS 41 simulators feature
.Many flexible control commands
.Trace output. halt table and deleting
.Interrupt operations capable of cyclic interruptions
.Assignment of I/O ports and data
The MELPS 41 simulator also has
.Reverse assembler
.Setting execution time count
.Assignment of memory protect region
14-6
Translates assembler
outputs paper tape in
Generates paper
Minato Electronics or
• MITSUBISHI
.... ELECTRIC
M58840-XXXP and M58494-XXXP single-chip
4-bit microcomputers can be automatically
programmed to customer's specifications.
The
plotter Instructions for automatic mask production
and the program to test the production ROMs
are automatically generated from the object program
provided by the customer
MITSUBISHI LSls
MELPS 4/41 SOFTWARE
DEVELOPMENT OF APPLICATION PROGRAMS
The user can develop his application programs using
MELPS 4/41 software as follows:
The cross assembler is used for object-program
generation, and the simulator is used for program
debugging. When the application program is finalized,
the paper-tape generation program for PROM writers is
used to generate a paper tape for the PROM writer.
1. EPROM: Newly developed application programs are
programmed in EPROMs, using the PROM writer; then
these EPROMs are ready to be installed in sockets of
an evaluation breadboard computer or other singlechio microcomouter.
2. Mask-programmable single-chip microcomputer: Mitsubishi Electric has developed a system to produce a
mask-programmable single-chip microcomputer to the
user's specifications. The object program can be in the
PROM-writer format of either Minato Electronics or
Takeda Riken.
PROGRAM DEVELOPMENT
EPROM PROGRAMMING
MASK ROM CODING FOR
SINGLE-CHIP MICROCOMPUTER
MELCOM 70 SERIES. MINATO
OR TAKEDA PROM WRiTERS
MELCOM 70 SERIES
PROGRAM GENERATION ON HOST COMPUTER
MELCOM 7000 SERIES
COSMO 700 SERIES
MELCOM 70 SERIES
9
~~~~AWb~
PROGRAM
FOR PROM
WRITER
SOURCE PROGRAM
t:=1
PAPER TAPE FOR
PROM WRITER
MASK DRAFTING DATA
TEST PROGRAM
___ -.J ( Note1)
f------If------'L2,NJ
P
PROCESS
EPROM
~ M'CROCOMPUTER
EPROM
INSTALLED
PAPER TAPE FOR
PROM WRITER
I
t- ____ _
DE~~[bM~1NT
RESULT
I
- - - - - - - - - - - _ _ _ _ _ _ _ _ _ --l
SYSTEM OR
MICROCOMPUTER
AldOI~~~~~
II
SINGLE-CHIP MICROCOMPUTER
LSI INSTALLED
Note1: With MELPS 41. paper-tape can also be used for source program input.
• MITSUBISHI
.... ELECTRIC
14-7
MITSUBISHI LSls
MELPS 8/85 SOFTWARE
AVAILABLE MATERIALS
Program
Program code number
Source language
HOST PROGRAMS
MELPS 8/85 PL/I" Cross Complier-MELCOM 7000 (B-version)
GA1TL0100
Magnetic tape
FORTRAN IV
MELPS 8/85 Cross Assembler-MELCOM 70 (A-version)
GA1AS0100
Magnetic
~ape
FORTRAN IV (part in assembler)
MELPS 8/85 Simulator-MELCOM 70 (B-version)
GA 1 SM0100
Magnetic tape
FORTRAN IV (part in assembler)
MELPS 8/85 Paper Tape Generation Program for PROM Writers- MELPS 70
GA1SP0100
Magnetic tape
FORTRAN IV (part in assembler)
Magnetic tape
FORTRAN IV (part. in assembler)
ME LPS 8-48 Cross Assembler-ME LCOM 70 (A-verison)
TARGET PROGRAMS
MELPS 8/85 Self assembler
GA2AS0100
Paper tape
MELPS 8/85·assembler
MELPS 8/85 Editor
GA2SP0103
Paper tape
MELPS 8/85 assembler
MELPS 8 BOM-PTS Basic Operating Monitor
GA20S0100
Paper tape
MELPS 8/85 assem?ler
MELPS 8 BOM-B Basic Operating Monitor
GA20S0101
Paper tape
MELPS 8/85 assembler
MELPS 8/85 Subroutine 1 : Integer Arithmetic Operations
GA2SB0100
Paper tape
MELPS 8/85 assembler
f---
Manual number
Manuals (In Japanese)
Number of pages
MELPS 8/85 PL/lp CROSS COMPILER MANUALS
MELPS 8/85 PL/I" Compiler Summary (B-version)
GAM-SROO-07A
MELPS 8/85 PL/I" Compiler Language Manual (B-version)
GAM-SROO-OSA
SO
MELPS 8/85 PL/I" Cross Compiler Operating Manual (B-version)
GAM-SROO-09A
52
MELPS 8/85 PL/I" Cross Compiler Operating Manual-MELCOM 7000
GAM-SROO-l0A
28
74
MELPS 8/85 CROSS ASSEMBLER MANUALS
MELPS 8/85 Assembly Language Manual (A-version)
GAM-SROO-01A
90
MELPS 8/85 Cross Assembler Operating Manual (A-version)
GAM-SROO-02A
40
MELPS 8/85 Cross Assembler and Simulator Operating Manual-MELCOM 7000
GAM-SROO-04A
16
GAM -SROO -03A
40·
MELPS 8/85 SIMULATOR MANUAL
MELPS 8/85 Simulator Operating Manual (B-version)
MELPS 8/85 SELF ASSEMBLER MANUALS
MELPS 8/85 Self Assembly Language Manual IB-version)
GAM-SROO-25A
84
MELPS 8/85 Self Assembler Manual-PTS
GAM-SROO-19A
22
MELPS 8/85 Self Assembler Operating Manual
GAM-SROO-24A
32
--
MELPS EDITOR MANUALS
MELPS Editor Manual-PTS
GAM-SROO-26A
20
MELPS Editor Operating Manual-PTS
GAM-SROO-27A
32
MELPS 8 BOM-PTS Basic Operating Monitor Manual
GAM-SROO-18A
18
MELPS 8 BOM-B Basic Operating Monitor Manual
GAM-SROO-23A
14
GAM-SROO-17A
18
GAM-SROO-.32A
32
MELPS 8 BASIC OPERATING MONITOR MANUALS
MELPS 8/85 SUBROUTINE MANUALS
MELPS 8/85 Subroutine 1 (Integer Arithmetic Operations) Manual
PAPER-TAPE GENERATION PROGRAM MANUAL FOR PROM WRITERS
Paper·Tape Generation Program Manual for PROM Writers-MELCOM 70
MELPS 8-48 CROSS ASSEMBLER MANUALS
MELPS 8:48 Assembly Language Manual (A-version)
GCM- SROO-O lA
148
ME LPS 8-48 Cross Assembler Manual (A-version)
GCM-SROO-02A
24
MELPS 8-48 Cross Assembler Operating Manual·MELCOM 70
GCM- SROO-03A
5
14-8
• MITSUBISHI
.... ELECTRIC
I
I
I
MITSUBISHI LSls
MELPS 8/85 SOFTWARE
GENERAL DESCRIPTION
MELPS 8/85 software is the name used to designate a soft-
the second is that used as a part of application programs
ware series provided by Mitsubishi fo~ developing application
programs or operating systems for equipment in which
for MELPS 8/85 CPUs. MELPS 8/85 software can also
be divided into two classifications: the first, host pro-
MELPS 8/85 CPUs are used.
grams, which are developed to run on a host computer;
MELPS 8/85 software is divided into two parts. The first
is that used as a tool to develop application programs, and
and the second, target programs, which are developed to
run on a MELPS 8/85 microcomputer.
SOFTWARE CONFIGURATION
Compiles a source program written in
PlIl,u language and produces as output
an object program in machine language
The complete Intel PliM language is a
subset of PL/l,u. Therefore. any program
written in PL/M can be compiled using a
PlIl,u compiler. Additional functions have
been included in PL/l,u that make it easy
Executes and checks a user's program on
the pseudo CPU In a host computer. This
allows more efficient program debugging
and provides more extensive checking
than can be accomplished by hardware
FEATURES:
• Provides traces and other debugging
Riken. Mlnato Electronics. DATA I/O and
PRO-LOG.
•
•
•
•
written in assembly language and produces
as output an object program in machine
language. Parts of a program can be translated and tested. after which they can be
combined and linked because the individual outputs are relocatable. This makes
it easy to develop modules and then combine them to form a complete program
written in machine language for execution
on the microcomputer
Paper-tape is used as the source-program
input medium
The assembled oblect program is in
MELPS 8/85 binary object format and is
punched out on paper tape
Functions and la nguage specifications of
the assembler are included in the speclfi
cations of the cross assembler
Provides simulated 1/0 operations
Provides simulated interrupt operations
Simplifies program modifications
Provides flexibility for symbolic
addresses
• Provides data for evaluation of execution time
• Batch or conversational processing can
be used
generated by a cross compiler or a cross
assembler. The tapes contain translated
absolute object programs
Many kinds of paper tapes can be generated for the PROM wrrters of Takeda
as to facilitate debugging a program. This
program has a structure that makes it
easy to expand or reduce the functions
The monitor can be used for a MELPS
8/85 CPU with any memory arrangement
or organization
FUNCTIONS
• Program execution control
• Program debugging
• In put! outp'ut control
• Program loading
• Memory readout
MEMORY CAPACITY
BOM-B
2K byte
BOM-PTS 7.5K byte
M58735-XXX P 4K-byte mask-programmabie ROMs can be automatl cally programmed to customer's specifications
The plotter Instructions for automatic
mask production and the program to test
the production ROMs are automatically
generated from the object program
provided by the customer
Increases the
development
effiCiency
of
program
FUNCTJON
Loading the text from a keyboard or a
paper-tape reader to the work area.
editing the text by means of commands
from a keyboard and controlling I/Os
10 subroutines are provided that can
perform arihmetic operations with binary
or decimal Integers and logical operations
These subroutines faCilitate handling of
information of 16 bits or 32 bits for
expressions of larger value
• MITSUBISHI
"ELECTRIC
14-9
MITSUBISHI LSls
MELPS 8/85 SOFTWARE
DEVELOPMENT OF APPLICATION PROGRAMS
The user can develop his application programs using MELPS
operations, input/output control and logical operations.
Full utilization of these subroutines can facilitate pro-
8/85 software in any of three ways.
1. On a host computer: the MELPS 8/85 cross compiler or
cross assembler is used for object-program generation,
and the simulator is used for program debugging.
gram development, debugging and implementation. The
final media of a developed program can be any of the
2. On a microcomputer: the MELPS 8/85 assembler is used
for object-program generation, and the microcomputer
is used for ~xecution and implementation of programs.
1. Paper tape:
3. On a combination of host computer and microcomputer: object programs are produced by the MELPS 8/85
following:
There are four basic forms of object pro-
grams on paper-tape: MELPS 8/85 binary, simple (lPL)
binary, hexadecimal and BNPF. Object programs on
paper tape are stored in RAMs and are loaded by the
appropriate loader.
cross compiler and/or the MELPS 8/85 cross assembler
2. PROM: The developed program is programmed in a
on a host computer. The object programs are debugged
PROM using the PROM writer; then this PROM is
and implemented on a MELPS 8/85 microcomputer
under control of the basic operating monitor.
computer.
installed in the appropriate PROM socket of the micro3. Mask ROM: Mitsubishi Electric is ready to produce a
The user can develop MELPS 8/85 programs using
mask ROM to a user's specifications. The object program
general-purpose subroutines for functions such as arithmetic
can be in MELPS 8/85 binary, hexadecimal or BNPF form.
PROGRAM DEVELOPMENT
PROGRAM GENERATION ON
HOST COMPUTER
MELCOM 7000 SERIES
COSMO 700 SERIES
MELCOM 70 SERIES
PROGRAM GENERATION
WITH MICROCOMPUTER
PROM PROGRAMMING
MASK ROM CODING
MELCS DEBUG MACHINE
MELCOM 70 SERIES
MELCOM 70 SERIES
o
o~
OBJECT PROGRAM
MELPS 8(85 BINARY
L--..j ~~~DECIMAL
PROGRAM
PAPER TAPE FOR PROM
WRITER
~:inING
~
MANUFACTURING
PROCESS
_____________
~
_________
-L~~--O-B-J-EC-T~PR_O_GR_A_M ~I___~
____
0
OBJECT PROGRAM
MEL'PS 8/85 BINARY
HEXADECIMAL
~----------
t.=.=J
BNPF
BOARD COMPUTER
MICROCOMPUTER
CONSOLE
EPROM ASSEMBLY
DEVEL~~~ANJ 6~PPORT ~M=A=S=K=RO=M=A=SS=E=M=B=LY====~
MICROCOMPUTER
APPLICATION
EQUIPMENT
14-10
• MITSUBISHI
.... ELECTRIC
MITSUBISHI MICROCOMPUTERS
MELPS 4 SOFTWARE
CROSS ASSEMBLER
DESCRIPTION
INPUT/OUTPUT MEDIA
The ME LPS 4 cross assembler has been prepared for the de-
•
•
Source input
: Punched cards and magnetic
Control data input
disk
: Punched cards and magnetic
M58847-XXXSP single-schip 4-bit microcomputer.
This cross assembler not only provides many pseudo
•
Control data command : Punched cards
•
Execution command
: System
instructions, control
commands, and control data for
•
Object output
: Magnetic disk
improving programming efficiency, but it also provides
•
Output lists
: Line printer
velopment of application programs suitable for equipment
using
the
M58840-XXXP,
M58843-XXXP,
M58841-XXXSP, M58842S,
M58844-XXXSP,
disk
M58846-XXXSP and
typewriter
keyboard
program versatility for changing instruction codes and
functions.
FUNCTION
FEATURES OF THE CROSS ASSEMBLER
This cross assembler converts source programs written in
•
21 types of control data
the ME LPS 4 assembly language to machine instruction
•
I nstruction codes and functions easi Iy changed
•
Catalogs the control data in disk storage
codes that are filed in disk storage in the form of binary
absolute object codes.
The MELPS 4 cross assembler is a 2-pass translator that
•
Constants can also be expressed in non-decimal notations
•
Expandability using pseudo instructions
provides data and control command analysis along with
•
Printouts available from the tables and cross-reference
lists
cataloging functions.
•
Execution computer: MELCOM 70 (memory capacity
setting mnemonic tables and numeric tables to constants
more than 24K words, monitor BOOS)
can easily be accomplished by means of the control data.
•
Implementation language: FORTRAN
written in assembly language)
IV (parts are
Modifying the number of bits in an instruction code and
I n this way, programming versatil ity is provided for changing functions, allowing the user free selection in defining
the mnemonics of the machine instructions, etc.
FEATURES OF THE ASSEMBLY LANGUAGE
The standard version of the MELPS 4 assembly language
•
6 pseudo instructions
•
10 simulator control commands
has 7 assembler control commands (see Table 1). In addi-
•
•
68 machine instructions
Decimal numbers can be used to define the constants
commands (Table 2) can all be used in the source language
of the machine instruction operand field.
program.
tion 6 pseudo instructions and 10 system simulator control
PROCESSING SYSTEM
SOURCE PROGRAM
CONTROL DATA
CONTROL COMMANDS
EXECUTION
COMMANDS
-----1
1--------
I
I
I
I
I
I
I
i
I
I
I
CROSS ASSEMBLER
I
I
>
I
I
I
I
I
I
I
I
L _______________________ ,
LIST
CONTROL DATA LIST
ERROR WARNING LIST
COMMAND ERRORS
~'------~D
SOURCE PROGRAM FILE
CONTROL-DATA FILE
~~~~8I m~GRAM
ASSEMBLING PHASE
PASS 1 & PASS 2
CONTROL-DATA ANALYZER
:
I
i
OBJECT FILE
:L ________________________
(PROGRAM AND CONTROL DATA)
_
PROGRAM ORDERING INFORMATION
Program name
Program and software manuals included
Ordering number
MELPS 4 Assembler Language Manual
MELPS 4 cross assembler
GBIASOOOl
MELPS 4 Cross Assembler Manual
MELPS 4 Cross Assembler Operating Manual
• MITSUBISHI
"ELECTRIC
GBM-SR10-01A(93AO>
14-11
MITSUBISHI MICROCOMPUTERS
MELPS 4 SOFTWARE
CROSS ASSEMBLER
CROSS ASSEMBLER
ASSEMBLY LANGUAGE
This cross assembler facilitates assembly by the use of the
The assembly language that the MELPS 4 cross assembler
control commands shown in Table 1.
accepts consists
instructions.
Basically, it only
requires the source program and control commands input
of machine
instructions
and
pseudo
by punched cards with control data being utilized only
1 . Machine Instructions
when necessary. All input is stored and filed in disk storage.
There are 68 basic machine instructions. These are con-
The control data is processed by the control command
verted to their corresponding machine codes and then
analyzing processor, and the symbol table is created in pass
1. This is followed by pass 2, where each instruction is con-
assembled into an object program. For the mnemonics,
the assembly list are printed out as specified by the control
instruction codes and their functional descriptions, please
refer to the data sheet provided for the M58840-XXXP
single-chip 4-bit microcomputer.
commands. On the assembly list, the control commands,
2. Pseudo Instructions
verted to machine language, while control data, labels and
sequence numbers, location numbers and addresses are
Although the pseudo instructions are written in the source
printed out, along with error and warning messages, followed by the ROM page list and the cross-reference list.
program together with machine instructions, they are not
converted to instruction codes but are used to control the
OBJECT LANGUAGE
assembler and the simulator. The instruction codes will be
written in the ROM.
The object file is composed of a name section and a text
section.
The name section is filed on sector 0 of the object file
and stores overall information such as the total number of
instructions in the text section, control data, file name,
source program file name, size of a single page and the
The system simulation control instructions are among
the pseudo instructions along with assembler-control
instructions, numeric symbols defining instructions and listcontrol instructions. The pseudo instructions are shown in
Table 2.
module name.
The text section contains the data that controlled the
conversion of the source program to instruction codes and
other related data necessary for execution by the simulator.
Table 1
Assembler control commands
Format
Command
Execution start
/ / / RUN
Execution end
/ / / END
Function
Starts execution of the cross assembler
Terminates execution of the cross assembler
/ / / ASMB4,
x,
Y ..
Z
ASSignment of assembly execution and control data and assembly listings
x=(:)
y= (~)
z=(~)
Input/output function assignment
x:
Assembly control
A : Assembly needed
p: Designation of cataloging function
y:
z:
L:
Assembly listing
Control data listing
Listing needed
N: No listing needed
File
aSSignment
control
/ / CDI SK, XXXXX
Control data
/
Source program
/ / / S DIS K, XXXXX
Oblect
/ / / B DIS
11(,
/ / / IN PUT,
Assignment of the control file name (max. 6 characters)
Assignment of the source program file name (max 6 characters)
XXXXX
Assignment of the object file name (max. 6 characters)
x, y
Assignment of input device for the control data and source program
x= (g)
y= (g)
Input/output device assignment
14 --12
• MITSUBISHI
..... ELECTRIC
x:
y
Control data Input
Source program input
C
Punched card input
D
Disk input
MITSUBISHI MICROCOMPUTERS
MELPS 4 SOFTWARE
CROSS ASSEMBLER
Table 2 Pseudo instructions
Mnemonic
Classification
Assembler control
instructions
Symbol value equlvalence instructIOn
List control Instruction
System Simulator
control instructions
Function
Instruction
TTL
PAGE
ORG
END
EQU
EJE
SIN
RIN
SOlS
ROIS
sse
RSe
wse
RWSe
SINT
RINT
Program title declaration
Declares the program title
Program counter paging
Sets the counter to the top address of the next page
Program counter setting
Sets the counter to the top address of the program
End declaration
Declares the end of the program
Symbol value setting
Sets a numeral value to the specific numeral symbol
Page elect declaration
Advances the printout form to the next page during output
Data Input
Reads the Input data
Mode cancellation
Cancels
Display content printout
Prints out the contents of the display
"* *
mode Input
SDIS presetting
Enables execution of the SDIS instruction
Step counter selection
Selects the step counters
ssc presetting
Enables execution of the SSC Instruction
Step counter content prl ntout
Prints out the contents of the step counters
WSC presetting
Enables execution of the WSC instruction
Terminal Input
Starts Input from the terminal aSSigned
SINT presetting
Validates execution of the SINT instruction
Note 1. Validation refers to the execution of one command before another to enable its function. For example. to execute the SSC instruction the RSC instruction must be
executed first.
(1) label field
3. Language Format
The following format should be used in coding programs in
The value of the program counter at that time is set to
this cross assembler.
the label. The number of characters used for a label is
The single-line statement is composed of the label, in-
limited to a maximum of 6, and any of the alpha-
struction, operand, comment, and identification fields.
The format of the source statement is fixed as indicated in
numerics and special characters specified above can be
Fig. 1. Although the constant is usually a decimal number,
first column of the label field.
it may be expressed by hexadecimal notation and other
used.
However, an asterisk (*) cannot be used in the
(2) Instruction field
nation when defined by pseudo instructions and control
data.
Mnemonic codes are written in this field, left-justified.
An asterisk (*) in the first column of a line indicates
the assembler-control instructions, numeric symbol
that the entire statement is used as a comment field.
The following are valid characters for use in statements:
For pseudo instructions,. any of the mnemonics among
definition instructions, list-control
instructions, and
system simulator control instructions may be used.
Alphabetics:
A~Z
Numerics:
O~9
Parameters of the instruction are specified in this field.
Special characters:
;=,T@$+-*/!&( ).#%<
This field contains the label, defined symbol, or numerical value. The operand is stated from the 14th column,
(3) Operand field
>
? (space)
Fig. 1 Source statement format
112131415161718191101111121131141151161
.- ..
left-justified.
\
171172173/741 -- .. 80
(4) Comment field
Whenever the operand is followed by more than one
b,J 1,",,,",,,,0 J
Label field
field
space to the end of the statement, the successive
Operand and comment field
J
Identificatlon field
columns may be used for comments.
(5) Identification field
The use of this field is optional. Many find it convenient to use this field for a sequential identification card
number.
• MITSUBISHI
"'ELECTRIC
MITSUBISHI MICROCOMPUTERS
MELPS 4 SOFTWARE
CROSS ASSEMBLER
ASSEMBLY LIST FORMAT
$$$$$$$ERROR
xxx$
A source program prepared and assembled in the format
where "x x x" indicates the type of error by a numerical
indicated in the preceding paragraph may produce source,
code.
symbol table, cross reference, and ROM page list printouts.
The format of an assembly list produced as an example is
I n the case of warnings, the following message is printed
between SEQ (sequential number) and LOC (location
shown in Fig. 2. Please note that pages, locations, and
number):
* Wx * (where "x" indicates the degree of warning)
object codes are indicated in hexadecimal notation.
In addition the total numbers of errors and warnings are
MESSAGE FORMAT
printed on the last line of the assembly list.
Error and warning messages are printed out on the assemble
reference list, however, will not be produced when any
list. In the case of errors, the message is printed out under
errors are indicated.
The cross-
the respective statement in the following format:
Fig. 2 Assembly list format
TITLE SPECIFICATION STATEMENT
r - - - - PAGE OF ROM ADDRESS (HEXADECIMAL FORMI
PAGEOFLlST~
(XX PAGE)
SEQ.
XXXX
*WX
r- t -+SEOUENTIAL
NUMBER
L 0 C.
B R P
*XX
00
I
-+--l
WARNING
LOCATION
A.
0
B
~
J.
XXXX~
00
..
-
-
-
-
. .. 8
7
----j f------j
L
L
SOURCE STATEMENT
IDENTIFICATION
FIELD
OBJECT CODE (HEXADECIMAL FORMI
BRANCH PAGE AND ADDRESS DESIGNATION
Example of an assembly list
EXAMPLE 'JROGRAM
An actual example of an assembly list, for
SEC.
P.
LOC'.B'"
14-15
MITSUBISHI MICROCOMPUTERS
MELPS 4 SOFTWARE
SIMULATOR
Table 1 Simulator control commands
~
tem
Control commands
Functions
Functional
classification
Start condition setup
Mnemonic
Action
Starts simulation
ST
Designates the control command Input device and the
simulation result output device and assigns control data output
Loads the object program
LO
Loads the absolute object program
Reassigns the control command input
CM
Changes the command Input device to another device
Stops simulation
FN
Terminates the program execution. and control is returned to
the mOnitor
Trace region assignment started
TS
Assigns trace regions where the contents of the program
counter. registers. and memory file will be printed out while
being executed
.
Trace region assignment discontinued
TO
Discontinues trace region assignment
Printout of the trace table
PT
Prints out the trace table
----
Load program
Command Input
r---~eassignment
FInish simulation
Trace
Halt
u
c
E
c
0
HS
Halt-point assignment discontinued
HO
Discontinues halt-pOint assignment
Printout of the halt-pOint table
PH
Prints out the halt-pOint table
Initialization of the program counter. registers.
memory file. etc
MM
Sets the initial data to the program counter. registers. I/O ports
memory file. etc
Resets of the program
memory file. etc
CL
Resets the program counter. registers. I/O ports. memory file.
etc
Data setup
§
i
Halt-pOint assignment started
Assigns halt POints by page number. address and times of
execution
counter.
registers.
r---------+-----------------t----------- -----Data prl ntout
Printout of the data in the program counter
register. memory file. etc
OM
-----------------------
Dumps the contents of the program counter. registers. I/O
ports. memory file. etc
1-----------+----------------------------+--------------------~
::;J
U
ROGRA"I
CD
The file stored in the BOISK whose file name is OFILE
is loaded
CONTROL DATA FllE=CFllE
SOURCE FllE=SFllE
OBJECT FILE=OFllE
(l) The program title that was declared at the time of
source program preparation IS printed out
®
IllCl
--- --- --- -- - -- - --- --- ------ ------ ---- ----- ---- - - -- - --- --- --- -- - (J)
The contents of the program counter. stack pOinter.
registers. I/O ports and memory file are cancelled and
set to Initial conditions
IIIMII PRO('=O:O
---------------------------------------------------------------@
@ The contents of address 0 of page 0 of the object
lIlTS 0:O,O:4.R,M
---------------------------------------------------------------@
program is printed out on the system typewriter by
IIIHS 0:4.1
-----------------------------------------------_._--------------@
IIITO
-- - - -- --- - ------ -- -- - - - - - -- - - - -- - - - - - - - - -- --- - - - -- - -- - - - - - - - - - - !J)
lIlTS
--------------------------------------------------------------- ®
O:O,O:~,R,M
---------------------------------------------------------------@
/I IPT
***
NO.1
TRACE DUM\=> TAblE
--- 00:00
00:05
I lID II
***
DUNI> OF
CPS = 0
ACC
PORT.
0
I fHl:.F
IN T =
B
REG.
a
=
g:g:g } -----------------------------------ggggoggggoo }___________________________
OP1 Z,X,Y
OP2 Z,X,y
0 O-A
S 0-7
@
------------------------------------------ iUl
------------------------------------------ @
0000
0
0
0
0
0
0
0
A
F
e
6
0
0
0
0
a
0
0
a
0
0
a
0
a
0
0
0
0
a
a
a
9
8
7
f)
a
a
0
0
0
0
0
0
a
0
0
a
0
a
0
0
0
0
0
0
0
a
0
0
a
0
a
0
a
a
7
C
5
0
0
a
0
(J
a
0
0
a
0
a
a
0
0
a
0
0
a
a
a
0
0
0
0
0
a
0
0
0
a
a
a
a
0
0
a
MI:MO~Y
OUMf' GF
o~
the trace has been registered correctly
In
their initial states. of
the program counter. registers. stack pOinter. I/O ports
and memory file
@ The contents of CPS. (either one of a pair of the data
6
B
4
0
0
0
0
---------------- @
CY1 and CY2 (carry). OP1 and OP2 (data pOinter). Z
are printed out
@ This indicates each bit in the contents of the ports 0
@
***
1(\15T. 00:04
pointers or the carry is selected). ACC (accumulator).
(file assignment) and Y (digit deSignation In the file)
---------------------------- -----------------------------------
00:
5 of page O. and the contents of the registers and
memory file are to be printed out
etc .. are printed out
2
/I IDM
=
In thiS example.
tracing is directed from address 0 of page 0 to address
@ The contents of the program counter. stack pointer.
A
-------------------------- ------------------------------------- @
PC
step @ IS discontinued by
@ The trace table IS printed out In order to confirm that
@
/I IRN
***
In
releasing the trace· region assignment
@ This prints out the contents.
= 11
0000
p
Fa
Fl
F2
F 3"
F4
FS
F6
F7
address 4 of page 0 and the contents of the registers
are displayed
@ A new trace region IS assigned
IN THl
= a
I-i
®
00:00 SKI = 00:·)0 SK2 = 00:00 -------- @
SKO
OOOJOO."!OOOOOOOO
0000 0000
0- E
0-7
loading of the program
In address 4 of page 0
TYA
cn =
CY2 = 0
order to allow
@ TraCing is directed from address 0 of page 0 to
!J) Tracing deSignation
MOIO.-,,'go
~--~
PAGE
control
In3tructlons
~---~-------------+----------------------------L - - - -___
_______ Ie-END
'J,llr,r:p
·j;;~~~J(tlor;
EQLJ
~-~~~~_~~~~_+-~~
__
EO J E
__
--------
a short t'm'l (effe'.'i,ve only for oass 1
~~~~_~~~~_~
___
~_~~~_~~
Declares the end of the program
End declaration
----~~.-.-
- - - - - - - - + - - - - - - - - - - - - - - - - - - - ------------Sets a predetermined IJaiue to
:'ymbol·.. "I,w.>dlng
~~~,,,-.--n=~l"~-~~~~~---
I'" -'cU"
Stons the assembly for
Assembly pausing
PAUSE
f--
Function
Instruction
TTL
::j
specifiC numeral svmbo l
----~~~~--~~--~--~--~~----~--~--~~---------------
Page elect del i,Jratlon
Advances the printout form to the
p"ge dur'n"
Co_.OPIl!
~--------~-----+----------------+------------------INTM
Internal-memory-address setting
Sets the Interndl memory address to tile soe~I(" d sy:-.-.~o:
--
--
------------+-------------Sets the external-memory address to the
External-memory-address setting
-----.----~----
setting
EXT M
However, an asterisk (*) cannot be used in the first
Table 3 Macro instructions
column of the label field.
(2) Instruction field
Function
Instruction
(11 When the R IS set by the INTM Instruction. expansion IS
LZXY R±n 1
made Into LXx and LYy instructions
(2lWhen the R IS set by the EXTM instruction. expansion IS
made Into LZz. LXx and LYy Instructions
Mnemonic codes are written in this field. In addition
to the machine instructions, use can be made of pseudo
instructions such as the assembler-control, numericsymbol definition, list-control, and memory-address
Note 1 P IS specified by the INTM or EXTM instruction: symbol n is
hexadeCimal and O;?;n;?;4095
setting instructions.
(3) Operand field
4. Language Format
Parameters of the instruction are specified in this field.
The following format should be used in coding programs in
The field contains the label, defined symbol, or numerical value. It is usually necessary to leave a blank of one
this cross assembler.
The single-line statement of the source program is composed of the label, instruction, operand, comment, and
character or more behind the instruction.
(4) Comment field
identification fields. Format of the source statement is
This field is used for writing notes for the statement
free, as indicated in Fig. 1. Although the constant is usually
and is not converted to an object in the process of
a decimal number, it may be expressed by hexadecimal
changing the source statement into its corresponding
notation when defined by pseudo instructions and control
data.
object.
Writing an asterisk(*) in the first column of the source
The following are valid characters for use in statements.
Alphabetics:
A~Z
Numerics:
O~9
Special characters:
;= ,
statement enables the whole statement to be used as a
comment.
Whenever the instruction or operand field is followed
T @
$+- * /
& ( ).
#%
< >? (blank)
by more than one space, the successive characters may be
regarded as comments.
(1) Label field
(5) Identification field
The value of the program counter at that time is set to
The use of this field is optional. Many operators find
the label. Any of the alphanumerics and special char-
it convenient to use it for the sequential identification
acters specified above can be used.
card number.
The character :
(colon) is placed at the rear end of the label field.
Fig. 1 Source statement format
)1
1
Iso
\72 73\
/
LABEL FIELD2
INSTRUCTION FIELD
OPERAND FIELD
COMMENT FIELD
IDENTIFICATION FIELD
,(
/
Note 2
A colon (:) is placed behind the label_
• MITSUBISHI
..... ELECTRIC
14-23
MITSUBISHI LSls
MELPS 41 SOFTWARE
CROSS ASSEMBLER
ASSEMBLY LIST FORMAT
MESSAGE FORMAT
A source program coded and assembled in the format
Error and warning messages are printed out on the assembly
indicated in the preceding paragraph may produce as-
list. I n the case of errors, the message is printed out under
sembly-list, symbol-table-list, cross-reference-list, and ROM-
the respective statement in the following format:
page-list printouts.
$$$$$$$ERRORuxxxu$u
(Error message)
where 'xxx' indicates the type of error by a numerical
The format of an assembly list
produced as an example is shown in Fig. 2.
Please note
that pages, addresses, locations, and object codes are
code. The total number of errors is printed on the last line
indicated in hexadecimal notation.
of the assembly list. The cross-reference list, however, will
not be produced when any error is indicated.
Fig. 2 Example of an assembly list
P.
MElPS 41 EXAMPLE PROGRAM
(
SEa.
LOC· • .BR·PlA.
OBJ • • • • •
*••••
ORG
LA
SMRI
LP
LZXY
0,10
A
IBI
BM
LlXY
INTEX
REG2
REGISTER NO.1 SAVE OUT EXTERNAL MEMORY ............ @
.................................................................. @
EXAOOI00
EXAOOI10
180
380
000
BM
NOP
EX,TIN
REGISTER NO.2 RE"STORE
IN INTERNAL MEMORY ........ @
EXA00120
EXA00130
EXA00140
EXA00150
EXA00160
EXA00110
EXA00180
EXA00190
EXA00200
EXA00210
EXA00220
EXA00230
EXA00240
EXA00250
EXA00260
5
12
13
01103
If:!
14
15
16
11
18
19
20
21
22
23
24
25
26
19
01/00
lA
*•••• 5 •••• *•••• 6 •••• *•••• 1 •••• *•••• 8
10
200
10
REG1:
REG2:
12
13
14
15
lIS
17
STATEMENT ••••
EOU
EXTM
IN.TM
*A:
4
11
*.· ••• 2 •••• SOURCE
MELPS 41
2
3
10
J
TTL
1
.6
1
R
9
10
11
00 PAGE
1 ••••
19A
036
Ie 1
lAZ
160
180
383
1
REGl
EXAMPLE PROGRAM"""""""'''''''''''''''''''''''''''''''''''''''''''''''''''CD EXAOOOOO
..................................................................® EXAOOO 1 0
SYMBOL 'A' IS EOUAL TO 10.. · ...................... · ............ ·0) EXA00020
Z:X:Y=2:0:0 ; TOP ADDRESS OF REGISTER NO.l""@ EXA00030
X : Y = l ' : O ; TOP ADDRESS OF REGISTER NO.2 .... @ EXA00040
EXA00050
EXA00055
EXA00060
RESET BUS FLOUTING MODE SET(MR1J
EXA00010
EXA00080
.......................................................... @ EXA00090
.......................................................... ®
;; = ORG 1,0 = ;; .....................................................@
PAGE
ME MORY DATA TRANSFER SUBROUTINE
"
*
NOTE. MEMORY FROM EXTERNAL TO INTERNAL
(Y)=(YJ+1 , IF «Y).EO.O) RETURN SUBROUTINE
EXTIN: TSMI
B
fXTIN
RT
NOTE. MEMORY FROM INTERNAL TO EXTERNAL
(Y)=(Y)+l • IF «Y).EQ.O) RETURN SUBROUTINE
INTEX: TMSI
B
INTEX
RT
* ;;
27
0.)
01
02
01/00
OFC
100
OF8
03
04
05
01103
OFE
103
OF8
*
28
E~D
CD The program name is declared as "MELPS 41 EXAMPLE PROGRAM"
®
An asterisk (") in the first column indicates that the entire statement is a comment
Q)
Numeric value 10 (decimal number) is assigned to the symbol A by means of the symbol·value equivalence instruction
®
®
The value Z: X : Y = 2 : 0 : 0 is assigned to the symbol REG 1 by means of the external·memory address-setting instruction
®
The following program is assigned to address 10 (hexadecimal number) of page 0 by means of the program-counter setting. instruction
The value X. Y : lOis assigned to the symbol REG 2 by means of the internal-memory address-setting instruction
(j) The numerical value 10 (decimal number) assigned to the symbol A is loaded in register A
®
®
The numerical value 1 is loaded in the page register
@
@
@
@
The labeliNTEX is assigned by means of the BM instruction during assembly process and calls the subroutine starting at page 1 address 3
The value assigned to symbol REG 1 is expanded in LZ. LX and LY instructions
14 - .. 24
The value assigned to symbol REG2 is expanded in LX and LY instructions
The label EXTIN is assigned by means of the BM instruction during assembly process and calls the subroutine starting at page 1 address 0
The program-counter page number is advanced to that of the next page
• MITSUBISHI
~ELECTRIC
MITSUBISHI MICROCOMPUTERS
MELPS 41 SOFTWARE
SIMULATOR
DESCRIPTION
The MELPS 41 simulator software has been prepared for
MELPS 41 SIMULATOR PROCESSING SYSTEM
facilitating program debugging of application programs
.CONTROL COMMAND
.INPUT DATA
.OBJECT
PROGRAM
FILE
.CONTROL
DATA FILE
suitable to equipment using the M58494-XXXP CMOS
single-chip 4-bit microcomputer or microprocessors. It
also allows a significant saving of program-development
time.
With this simulator, each instruction of the microcomputer is executed just as though the program were being
I
executed on an actual microcomputer system_ This allows
I
I
confirmation that the operations and sequences of a pro-
~
gram are correct from a software point of view before the
INTERMEDIATE
RESULTS
microcomputer system is built. Simulations using various
simulator control commands are possible, and the results
RESULTS OF SIMULATION
(THROUGH LINE PRINTER
OR SYSTEM TYPEWRITER)
of the simulations are printed out along with other helpful
information for verification and debugging of the
FUNCTION
program under development_
Various simulator control commands are provided by
FEATURES
•
•
An ample 26 control commands
Production and deletion of trace and halt tables are
I nterruption-generation setting and periodical interruption are possible
I/O port -setting function
•
Data-setting function
•
Execution-time counting function
•
Reverse assembly is possible
•
Memory-protection area-setting function
•
Execution computer:
•
words or larger)
Implementation language:
This simulator allows the production and deletion of
trace and halt tables, table printouts, and the setting and
printed indication of registers, stack pointers, carry flags,
memories, and I/O ports. The 26 control commands can
MELCOM 70 (memory:
FORTRAN
24K-
IV (parts are
Cartridge-disk storages, punched
Punched cards and system-type-
•
Intermediate results:
Simulation results:
Punched tapes
Line printers and system typeLine printers and system type-
Messages:
possible to output or input intermediate results by means
of punched tapes.
The simulator control commands are classified into (1)
writers
•
commands. The results of the simulation can be selectively
displayed on a line printer or system typewriter. It is also
writer keyboard
•
essed in this program, and a simulation is carried out
according to the conditions given by the simulator control
tapes
Control commands:
SIMULATOR
generated by the MELPS 41 cross assembler, are proc-
INPUT/OUTPUT MEDIA
•
also be used for interruption generation, timer setting and
reverse assembly.
Binary object codes stored in the disk file (BDISK),
written in assembler language)
Object input:
halt program processes, while indicating the system status,
CPU state and memory contents in a trace mode_ Interruption-generation setting is also possible.
•
•
is operating properly according to original specifications.
These control commands can set operating conditions and
possible
•
the ME LPS 41 simulator to help determine if the program
simulator control instructions for starting and ending
simulations, loading and saving programs, and changing I/O
writers
devices, and (2) execution-control instructions for control-
APPLICATIONS
ling simulation-execution status.
In conjunction with the MELPS 41 cross assembler as a
Control-Command Input Format
series of tools for developing application programs for
II/XX u (parameter)
single-chip 4-bit microcomputers_ Especially useful for
XX:
debugging programs prepared for the M58494-XXXP CMOS
Parameter: A
microcomputer.
Specified by a 2-character symbol (26 kinds).
required parameter can be selected from
PROGRAM ORDERING INFORMATION
Program name
Ordering number
Software manuals Included
MELPS 41 Simulator Manual
MELPS 41 Simulator
rItII
those which have been defined in the c o n t r o l _
GB1SMOOO2
MELPS 41 Simulator Operating Manual
• MITSUBISHI
"'ELECTRIC
14-25
MITSUBISHI MICROCOMPUTERS
MELPS 41 SOFTWARE
SIMULATOR
Table 1 Simulator control commands
~
tem
Function
classification
Simulator start-up
Execution-program setting
Control commands
Functions
Action
Mnemonic
Specification of simulation-start conditions
ST
Designates the control-command input devices and the simulation-result output
device. and sets them to start status
I::xecutlon-program loading
LO
Loads the absolute oblect program ideslgnates input-device fiie namei
'0
c~----------------+---------------------------~------t-------------------------------------------------~
Program saving
Execution-program saving
SV
Outputs intermediate results of the program content. register. port. F/F. Timer. and
memory in punched tape
~~
~~~----------------+---------------------------~------t-------------------------------------------------~
C0~
Designation of
Simulation output device
Selection of command-input and simulationresult output devices
ov
Designates the command-input deVice and simulation-result output device by uSing
the deVice symbol
r---SI-m-u-la-to-r-te-rm--in-at-io-n--1-----------------------------1---F-N--~Te-r-m-In-at-e-s-th-e-p-ro-g-ra-m--ex-e-cu-t-,o-n.-a-n-d-c-on-tr-o-I-,s~re-t-ur-n-ed-t-o-t-he--m-on-,t-o-r----~
1---+-----
HS
Trace-region ass,gnment disconrlnued
TO
Discontinues trace-region assignment by table-number deSignation
Printout of the trace table
PT
Prrnts out the trace table
Halt-pOint assignment started
HS
ASSigns halt POints by page number. address and times of execution
Halt-pOint assignment discontinued
HO
Discontinues halt-pOint assignment
Printout of the halt-point table
PH
Prints out the halt-point table
Initialization of the program counter. registers.
memory. file. etc
MM
Sets the initial data to the program counter. registers. I/O ports. memory frle. etc
Reset of the program counter.
memory frle. etc
CL
Resets the program counter. registers. I/O ports. memory file. etc
OM
Dumps the contents of the program counter. registers. I/O ports. memory. flip-flop
deVice. timer. etc
Input-port control
IN
Controls the input-port data read-In deVice and the Input port by print-mode
deSignation
Export-port control
OT
Designates an output deVice for the data obtained from the output port
Interruption-generation assignment started
IT
Sets interruption conditions such as interruption type. interruption generation. head
address. and generation cycle number
Interruption-generation assignment discontinued
10
Deletes the interruption-generation table
Printout of the interruption-generation table
PI
Prints out the interruption-generation table
Execution-timer selting and printout
TI
Sets the execution timer and prints out the ®mber of execution steps
Memory-protection-region assignment started
PS
Designates the kind of memory. starling and termination addresses of the protected
region. and Inhibits Write-In steps
Memory-protectlon-region assignment
r--------------------dlscontinued
Printout of the memory-protection region
PO
Trace
Halt
Sets starting and termination addresses to the trace region. traces. and executes
while prrntlng out the contents of the registers. ports. timer and memory as
speCified
Trace-region assignment started
Data setting
'0
c
E
Data prrntout
E
8
i
registers.
Printout of the data In the program counter.
registers. ports. flip-flop deVices. memory.
timer. etc.
Port control
c
0
'"u=>
Q)
x
UJ
Interruption
Execution step time
Memory protection
PP
Discontinues the memory-protection assignment by the memory-protection table
number
Dumps the contents of the memory-protection table
Program-execution start-up
RN
Starts simulation execution
execution-limit step number
Program execution
GO
Starts simulation execution
assignment IS invalid here
Reverse assembly control
PA
Reverse-assembles the specified region and prints out the source list
Termination by executing the halt point and the
Execution start
Reverse assembly
command. A comma (,) is used to divide one
parameter from another.
The following are parameter-configuration examples: reserved word, address indication, numerical-value setting,
numerical-value indication, and time setting.
1. Reserved word
This symbol is classified according to its function in
the simulator, and specifies a predetermined ch~racter
symbol, program counter (PC), memory, register, and
port.
///MMuREGS A = 9
2. Address indication
Address indications for the internal memory, external memory and ROM are possible.
///DMuEXTM, 0:1:E, 0:A:5
External memory address indication
14-26
Termination by halt-point execution.
///DMuINTM, 0:0,1:0
///MMuPROG,OF:23
Trace-region
Internal memory address indication
ROM address indication
3. Numerical value setting
A numerical value is set for each function parameter.
///MMuFFLG, CY = 1
4. Numerical value indication
Decimal or hexadecimal notation is used.
///MMuTIME, T1
=E
5. Time setting
The specified time is set.
• MITSUBISHI
"ELECTRIC
///TluSET, 8: 15:3
(Note: Th is parameter means 8ms, 15, 3fJ. sec.)
MITSUBISHI MICROCOMPUTERS
MELPS 41 SOFTWARE
SIMULATOR
APPLICATION EXAMPLES
can be used for setting their values. Here XXXX represents
Once the command ST (this is used for specifying simu-
the symbol or numerical figure by which the program
lation-start conditions) and its parameter are typed in
counter, registers, I/O ports or memory files are designated,
through
while nnnn represents a parameter to be assigned.
the
system-typewriter
keyboard,
successive
commands may enter through punched cards or the system-
Designating the halt command HS PP: aa nnnn will make
typewriter keyboard.
It is also possible to designate
command-input and result-printer devices by setting the
the machine halt at address aa of page PP after that instruction has been executed nnnn times.
Entry of the TS command
DV-command parameter.
Simulation is started on the object file in the disk
storage that was stored there, after assembling, by the
TSUP 1 P1 :al al, P2P2:a22, R, P, I. X 1 :Yl, X 2 :Y 2 (, E, ZI:
X 1 :Y 1 ,Z2: X 2: Y 2)
MELPS 41 cross assembler. When the MELCOM 70 is used,
the simulator program should be called by the command
out from address al al of page PI PI to address a2 a2 of page
//EXECuSIM41 to start simulating operation. The following are examples of command assignment in the case of
tracing and execution during system-application program
simulation.
P2 P2. Here R designates the output of the contents of the
registers and F/F print; P designates the ports and timer
print; and I and E respectively designate print modes for
the internal and external memories.
makes possible the assignment that a trace is to be carried
Assignment of the input and printer devices is entered
When the OM command is executed, the contents of
by the ST command in the format STuX, y, where X rep-
each register, port, flip-flop device, memory, timer, and
program counter are printed out.
resents the input device (S for the system typewriter, and
C for the card reader; no designation equals the S designation in effect), and Y represents the output device on which
I nterruption can be carried out by the IT, ID and PI
commands. The IT command designates the kind of inter-
the simulation result is printed out (L for the line printer
ruption, the head address of interruption generation, and
and S for the system typewriter; no designation equals the
L designation in effect).
the number of generation cycles. ID discontinues the inter-
The stored object program (BD ISK file) is loaded by the
ruption-generation assignment, and PI effects
generation table prinouts.
interrupt~on
simulator with the LO command in the format LOu file
the TI command can be used for execution timer setting
name. The CL command should be used for clearing the
and printouts. The PS, PO and PP commands are provided
initial values and the MM command for setting initial
values.
When the program counter, registers, I/O ports and
for memory protection. PS designates the memory-protection-region assignment, PO discontinues the memoryprotection-region assignment in accordance with the
memory file are to be cancelled, the command CL may be
memory-protection table number, and PP prints out the
contents of the memory-protection-region.
used. The MM command in the format of MMuXXXX,nnnn
Table 2 Examples of the use of simulator control commands
Application exmaples of control command
Function of the conrol command and its parameters
IIISTuS,
L
To start simulation. the command-input and simulation-result printout devices are assigned
command input S is assigned to the system typewriter. and printout L to the line printer
IIILOuD,
BFILE
The file stored in the disk (BDISK) whose file name is BFILE is loaded
I I ICLuINTM,
IIIHSu5:
0:0, O:F
The deSignated Internal memory is cleared frorn digit 0 to digit F of the 0 file
This assigns a halt point: in this example it will halt after the second execution of the instruction in address F of
page 5
F, 2
IIITSuO: 5,
In thiS example.
E:F, R, P
This command designates a trace from address 5 of page 0 to address F of page E. and orders display of the
·contents of each register. flip-flop device. port and timer after completing tracing
IIIITuINTA, O:F, 5
This effects the generation of interruption A starting at address F of page 0 and after every 5 steps after that.
IllpT
This command prints out the trace table
INTA, O:F, 5
ThiS command prints out the halt-point table
command
IllpH
I I IMMuPORT,
I I IMMuINTM,
0:0
0: 1
Assignments made by TS commands can be verified by this command
0=1
0=-
Q=A5
Assignments made by HS commands can be verified by this
This sets A5 to port Q
0:0
This command changes the value 0 in digit 0 of file 0 to 1
IIIDM
The contents of the program counter. registers. I/O ports. flip-flop devices. memory. and timer at the time this
command is executed are printed out
IIIRN 50
This starts the execution of simulation. which is stopped when the halt-point address is reached or when the
number of execution steps reaches 50.
• MITSUBISHI
"ELECTRIC
14-27
MITSUBISHI MICROCOMPUTERS
MELPS 41 SOFTWARE
SIMULATOR
Fig.1 Example of simulation results
••• 'START SIH'1.ATOR OF "ELPS 41 •••
IIILO D.BF ILf
...................................................... ······CD
,........................................................... ®
111M" INTH.O:O
.••••....••.....•.....•.•.•......•......................•... (3)
0:0
0:1,'
0:2
0-1
0=2
0=.
INH" INTH,.O:F
O:F
0-3
1.:0
0=-.
IN!'.H EXTPI.Z:l:0
2: 1':'0 O~'A
2:1 1 :1 0=·.
} ........................ @
INH,H rXTM·.Z:J:E
2: NE D=.B
2:N'F O=C
2:2:0 0='.
............................................................ @
lilTS OD:l.6.00·:l7.E,Z:0:0.2:1·:F ............................................................ @
...................................................... ..... (J)
IIIT'S 00:19 ••00:1 A.I .0: 0.J: F
lilTS 00.:19.00:J.9.R
........................................................... @
INHS 00:1 A.I
............................................................ ®
1110" RfGS
(REGS)
PC PRFG ACC TR Q R 5 T lJ
00"'0(001 0 0 00 00 00 00 00
Z X Y
0 0 0
;P
K
F 00:00
........................................................... @
II/P.T
•••• *
TRACE DU"P TAB.LE
TRACE. ADD
TRACE. HODE
00:16 00:17
E(Z:O:O.Z:J:F)
0011600:16
-00: 19 00: IA
I (0:0. I:F)
00:19 00:19
'R
Tel.NO
'1
Z
3
4
courn =
• CATALOG
Execution is started by the RN and GO commands,
and it is continued to the point specified by the HS
parameter. In the case of RN the machine is
stopped by executing the limit-step number and
the IDLE instruction. In the case of GO, termination
is effected after the execution of the IDLE instruction, and the trace-region assignment becomes
invalid.
The assignment of the trace region is discontinued with the TD command, and the halt-point
assignment with the HD command. The trace table
is printed out with the PT command, and halt-point
table with the command PH, whenever required.
The IN and aT commands can be used for
I/O-port control. The DV command is provided for
designating devices for command input and simulation-result printout .
Appl ication examples of the use of the MELPS41
simulator control commands are listed in Table 2,
and the results of a simulation example are shown
in Fig. 1.
CD The operation start-up of the MELPS 41 simulator is designated
4'
............................................................ @
INP,H
•••••
HALT POINT TABLE •••••
Ta~. NO
HALT .ADD EXEC .NUH
00: IA
• CATALOG
courn =
IIIR'N 100
00/'1·6
I.
............ : ............................................... @
............................................................ @
IIIT'I SET
J 83
8M
03
(REGS)
PC PR~ G ACC TR U R S T U
0l':03(OZ)
A 0 00 00 co 00 00
(FFLG)
CY
INTF
(A)
o
IT)
(8)
0
0
INT
IA) IT) (8)
0
0
0
Z X Y
ZOO
MF
~P
0
K
00:00
HR
MRI
HR2 lOA
(2ILQ)(SR8T)I--AI)
0000
1010 0000
IEXTr)
2:0:0
2:1:0
00/·17
1.81
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
A 0 0 0 0 0 0 0 0 0 0 0 0 0 B C
LX
I EXTH)
2:0:0
I ZOO 0 0 0 0 0 Q 0 0 0 0 0 3
Z :'1: 0
A 0 0 0 0 0 0 0 0 0 0 0 0 0 B C
OO/ol~
j
80
(FFLG)
CY
INTF
INT
CA)
(T)
(8)
o
0
0
IA)
0
Z x Y
Z I 0
MF
(T)
(8)
0
0
5P
K
0
00:00
"R
HRI
HRZ lOA
(2ILQ)(SRBT)(--AI)
0000
1010 0000
( INTH)
0:0
I ZOO 0 0 0 0 0 0 0 0 0 0 0 3
1 :0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
} ........................ @
NOP
"00
('INTH)
0:0
1 ZOO 0 0 0 0 0 0 0 0 0 0 0 3
'I: 0
A 0 0 0 0 0 0 0 0 0 0 0 0 0 B C
•••
f
I
I
I
I
I
I
I
I
SOURCE PROGRAM FI LE
CONTROL-DATA FILE
L _______________________ ,
I
~$~~gi ~7~TGRAM
LIST
CONTROL DATA LIST
ERROR WARNING LIST
I
:
ASSEMBLING PHASE
PASS 1 & PASS 2
CONTROL-DATA ANALYZER
COMMAND ERRORS
~'----~D
OBJECT FILE
\L _________________________
(PROGRAM AND CONTROL DATA)
J
PROGRAM ORDERING INFORMATION
Program name
ME LPS 42 cross assembler
Ordering number
Program and software manuals included
MELPS 42 Cross Assembler Manual
GBIASOO10
•
GBM-SR 00-31 A<03AO)
MITSUBISHI
"'EU!CTRIC
1A_'11
MITSUBISHI MICROCOMPUTERS
MELPS 42 SOFTWARE
CROSS ASSEMBLER
CROSS ASSEMBLER
ASSEMBLY LANGUAGE
This cross assembler facilitates assembly by the use of the
control commands shown in Table 1. Basically, it requires
only the source program and control commands input
by punched cards with control data being utilized only
when necessary. All input is stored and filed in disk storage.
The control data is processed by the control command
analyzing processor, and the symbol table is created in pass
1. This is followed by pass 2, where each instruction is converted to machine language, while control data, labels and
the assembly list are printed out as specified by the control
commands. On the assembly list, the control commands,
sequence numbers, location numbers and addresses are
printed out, along with error and warning messages, followed by the ROM page list and the cross-reference list.
The assembly language that the ME LPS 42 cross assembler
accepts consists of machine instructions and pseudo instructions.
OBJECT LANGUAGE
The object file is composed of a name section and a text
section.
The name section is filed on sector 0 of the object file
and stores overall information such as the total number of
instructions in the text section, control data, file name,
source program file name, size of a single page and the
module name.
The text section contains the data that controlled the
conversion of the source program to instruction codes and
other related data necessary for execution by the simulator.
1. Machine Instructions
There are 77 basic' machine instructions. These are converted to their corresponding machine codes and then
assembled into an object program. For the mnemonics,
instruction codes and their functional descriptions, please
refer to the data sheet provided for the M58496-XXXP
single-chip 4-bit microcomputer.
2. Pseudo Instructions
Although the pseudo instructions are written in the source
program together with machine instructions, they are not
converted to instruction codes but are used to control the
assembler. The instruction codes will be written in the
ROM.
The assembler-control instructions, numeric symbols
defining instructions and list control instructions are
among the pseudo instructions.
The pseudo instructions are shown in Table 2.
Table 1 Assembler control commands
Function
Format
Command
Execution start
I I IRUN
Execution end
I I lEND
I I I ASMB4,
Starts execution of the cross assembler
Termtnates execution of the cross assembler
x, y,
z
Assignment of assembly execution and control data and assembly listings
x=(:)
y=(~)
Input/output function assignment
z
=(~)
x:
Assembly control
A :
Assembly needed
P :
y:
DeSignation of catalogtng function
Assembly listtng
z : Control data listtng
L : Listing needed
N :
File
assignment
control
xxx
XX
Control data
/ I ICDISK,
Source program
IIISDISK, XXXXX
Assignment of the source program file name (max. 6 characters)
Object
I I IBDISK, XXXXX
Assignment of the object file name (max. 6 characters)
IIIINPUT,
x, y
Assignment of the control file name (max. 6 characters)
ASSignment of input device for the control data and source program
x=(~)
y= (~)
Input/output device assignment
14-32
No listing needed
• MITSUBISHI
.... ELECTRIC
yx
Control data input
Source program input
C
D
N
Punched card input
Disk input
Control data no input
MITSUBISHI MICROCOMPUTERS
MELPS 42 SOFTWARE
CROSS ASSEMBLER
Table 2 Pseudo instructions
Classification
Assembler control
instruct ion
Symbol value equivalence instruction
List control instruction
Mnemonic
TTL
PAGE
ORG
END
EOU
EJE
Instruction
Function
Program title declaration
Declares the program title
Program counter paging
Sets the counter to the top address of the next page
Program counter setting
Sets the counter to the top address of the program
End declaration
Declares the end of the program
Symbol value setting
Sets a numeral value to the specific numeral symbol
Page eject declaration
Advances the printout form to the next page during output
3. Language Format
The following format should be used in coding programs in
this cross assembler.
The single-line statement is composed of the label, instruction, operand, comment, and identification fields.
The format of the source statement is fixed as indicated in
Fig. 1. Although the constant is usually a decimal number,
it may be expressed by hexadecimal notation when defined
by pseudo instructions.
An asterisk (*) in the first column of a line indicates
that the entire statement is used as a comment field.
The following are valid characters for use in statements:
Alphabetics: A"'Z
Numberics: 0"'9
Special characters:
, ... @ $ + - * /
& ().
# % < > ? (space)
lJ2131415161718191101111121131141151161
t
1711721731741
80
(
Label field
j
I I nstruction
field
J
Operand and comment field
r--
J
Identification field
(1) Label field
The value of the program counter at that time is set to
the label. The number of characters used for a label is
limited to a maximum of 6, and any of the alphanumerics and special characters specified above can be
used. However, an asterisk (*) cannot be used in the first
column of the label field.
(2) Instruction field
Mnemonic codes are written in this field, left-justified.
For pseudo instructions, any of the mnemonics among
the assembler-control instructions, numeric symbol
definition instructions and list-control instructions may
be used.
(3) Operand field
Parameters of the instruction are specified in this field.
This field contains the label, defined symbol, or numerical value. The operand is stated from the 14th column,
left-justified.
(4) Comment field
Whenever the operand is followed by more than one
space to the end of the statement, the successive columns may be used for comments.
(5) Identification field
The use of this field is optional. Many find it convenient to use this field for a sequential identification card
number.
Fig. 1 Source statement format
• MITSUBISHI
.... ELECTRIC
14-33
MITSUBISHI MICROCOMPUTERS
MELPS 42 SOFTWARE
CROSS ASSEMBLER
ASSEMBLY LIST FORMAT
$$$$$$$ERROR
xxx$
where "x x x" indicates the type of error by a numerical
code.
In the case of warnings, the following message is printed
between SEa (sequential number) and LOC (location
number):
* Wx * (where "x" indicates the degree of warning)
In addition the total number of errors and warnings are
printed on the last line of the assembly list. The crossreference list, however, will not be produced when any
errors are indicated.
A source program prepared and assembled in the format
indicated in the preceding paragraph may produce source,
symbol table, cross reference, and ROM page list printouts.
The format of an assembly list produced as an example is
shown in Fig. 2. Please note that pages, locations, and
object codes are indicated in hexadecimal notation.
MESSAGE FORMAT
Error and warning messages are printed out on the assembly
list. In the case of errors, the message is printed out under
the respective statement in the following format.
TITLE SPECIFICATION STATEMENT
I
I
~r----PAGE OF ROM ADDRESS (HEXADECIMAL FORM)
(XX PAGE)
SEQ.
lO C.
B R P
XXXX*WX
*XX
00
r-- ,---+SEQUENTIAL
NUMBER
I
-+--l
1
WARNING
LOCATION
A.
0
00
PAGE OF LIST!].
B
J.
XXXX-. . . . .
----1
L
00
1--1
I
*-------7.
I--
SOURCE STATEMENT
OBJECT CODE (HEXADECIMAL FORM)
8
L~
IDENTIFICATION
FIELD
BRANCH PAGE AND ADDRESS DESIGNATION
Fig. 2 Assembly list format
P.
Example of an assembly list
An actual example of an assembly list for
an assembly made with the MELPS 42
cross assembler is shown in Fig. 3.
SEQ,
LOC'.S~P/A.
OBJ.
TTL
I1RG
DIG"AX EQU
9
10
11
01 OEIOO
02 JE/Ol
OJ OEl07
o'
100
101
107
,,00
17
0:"1
la
01
02
Ol
04
2J*WO*OS
24
Ob
ZS
07
Z6
27
ZB
Oij
Z9
lO
09
OA
31
3Z'WO.08
3l
34
oc
program name is declared as "EXAMPLE PROGRAM".
It shows that the start of the program was set to page
address 0 by means of the program counter setting
instruction.
~An asterisk (0) in the first column indicates that the
entire statement is a comment_
@) Numeric value 13 (decimal number) is assigned to
the symbol DIGMAX by means of the symbol value
equivalence instruction.
®
o
14-34
~CGIl
JECT
GENERATED BY MELPS 42
CROSS ASSEMBLER
(BDSIK FILE)
~r--------------'l
PAPER-TAPE GENERATION
PROGRAM
(OBJECT CONVERSION
ROUTI NE)
MESSAGES
HEXADECIMAL PAPER TAPE FOR
TAKEDA RIKEN PROM WRITER
PROCESSED BY MELCOM 70
HEXADECIMAL PAPER TAPE
FOR MINATO ELECTRONICS
PROM WRITER
PROGRAM ORDERING INFORMATION
Program name
MELPS 42
paper-tape generation program for PROM wr iter
Program and software manuals included
Ordering number
GBISPOO06
MELPS 42 paper-tape generation program for PROM writer manual
• MITSUBISHI
.... ELECTRIC
GBM- SR 00- 33A (03AO >
14-35
MITSUBISHI MICROCOMPUTERS
MELPS 42 SOFTWARE
PAPER-TAPE GENERATION PROGRAM FOR PROM WRITERS
PROGRAM PROCESSING
Example of Object Conversion
The program has conversion routines for Takeda Riken's
and Minato Electronics' PROM writers. Select T 1 mode (for
Takeda Riken's PROM writer) or Ml mode (for Minato
Electronics' PROM writer) through the system typ.ewriter
keyboard. Then the object program is converted to paper
tape compatible with the selected PROM writer. When a
(BDISK file) file name is called, a paper tape is output for
the PROM writer. When a number of programs are to be
converted from.the same file, successive calls can be made
until all the programs are converted. Termination of the job
is directed with the E command, and control is then returned to the monitor.
The object file consists of name and text segments. The
data to be converted is contained in the text segment. Instruction codes, stored after sector 1 of the disk, that corresponds to machine instructions are converted to hexadecimal codes and output to paper tape.
The program at present can output 1 K-word units of paper
tape up to a total of 4K words. An example is shown in
Fig. 3.
Error Processing
When an error is encountered during object conversion, a
message will be printed out in the following format:
$$$$$$$ xxx$
where, XXX indicates the error code.
ABSOLUTE
BINARY OBJECT
OOOCJ~ ~~§:
000
3FF
000
Example of Hexadecimal Paper-Tape Format
3FF
This program can generate paper tapes for Takeda Riken's
PROM writer or Minato Electronics' PROM writer. Examples of both formats are shown in Figs. 1 and 2.
Fig. 3 Example of object conversion
SECOND BLOCK
HIGH-ORDER
(PAGES 0-7. BIT 8)
FOURTH BLOCK
HIGH-ORDER
(PAGES 8-:F. BIT 8)
.
SPROCKET HOLES
MORE THAN 200
SPROCKET HOLES
MORE THAN 100
Fig. 1 Example of hexadecimal paper-tape format of Takeda Riken
SECOND BLOCK
HIGH-ORDER
(PAGES 0-7. BIT 8)
FIRST BLOCK
LOW-ORDER
(PAGES 0-7. BITS 0-7)
.
,
<----I
THIRD BLOCK
LOW-ORDER
(PAGES 8-F. BITS 0-7)
FOURTH BLOCK
HIGH-ORDER
(PAGES 8-F. BIT 8)
.
'--y---J
SPROCKET HOLES
MORE THAN 100
SPROCKET HOLES
MORE THAN 100
~I
1
PAGE PRINT
*
0
Fig. 2 Example of hexadecimal paper-tape format of Minato Electronics
14-36
SPROCKET HOLES
MORE THAN 200
I~ I~ I[1 Hoi H~ 1~ H+H+Innu
'---v----''---y---'
TITLE
SPROCKET HOLES
MORE THAN 100
SPROCKET HOLES
MORE THAN 100
• MITSUBISHI
.... ELECTRIC
MITSUBISHI MICROCOMPUTERS
MELPS 8·48 SOFTWARE
CROSS ASSEMBLER
DESCRIPTION
The MELPS 8-48 cross assembler has been prepared for
aiding the development of application programs suitable for
equipment using the MSL8041-XXXP, MSL8048-XXXP
and'MSL8049-XXXP MITSUBISHI single-chip8-bit microcomputers.
This cross assembler allows conversion of source
programs written in the MELPS 8-48 assembler language by
using a host computer into objects in the MELPS 8 binary
language.
The assembler language has machine pseudo and macro
i~structions. The full equipment of pseudo instructions and
control commands ensureshigh programming and debugging
efficiency. Coding can be carried out in a free format.
FEATURES OF THE CROSS ASSEMBLER
• Flexibility in assembler-language changing
• Various input/output media available
• Free-format coding
• A symbol table is output as part of the object code.
• Executed on a MELCOM 70 minicomputer (with 24 K
words of memory capacity or more, BOOS monitor)
• FORTRAN IV programming language (with some
assembler language)
•
In addition to decimal notation as the standard format,
binary, octal and hexadecimal notations can be used
• Machine-instruction compatibility with Intel Corporation's cross assembler
INPUT/OUTPUT MEDIA
• Source input:
Punched cards, punched tapes,
magnetic tapes, magnetic disks
• Control-command input: Punched cards
• Object code output
Magnetic disk
FUNCTION
This cross assembler converts source programs written in
the MELPS 8-48 assembler language to machine-instruction
codes, which are output as absolute objects.
The MELPS 8-48 cross assembler functions in two
phases: control-command analyzing phase and assembly
phase (intermediate-language-generation and listing phases).
The assembly-control commands listed in Table 1 are
available. They cover use for execution start-up, termination assignment, I/O assignment, file assignment, link
control and relocation assignment.
This cross assembler permits the use of the machineinstruction codes applicable to Intel's Models 8041,
8048 and 8049 and of the 10 pseudo instructions listed in
FEATURES OF THE ASSEMBLER LANGUAGE
• 10 pseudo instructions
Table 3.
• 6 Macro instructions
• Numerical formula used
• Character constants and strings used
CROSS ASSEMBLER
With various control commands and pseudo instructions,
the MELPS 8-48 cross assembler ensures easy program
debugging.
Source programs can be input by means of punched
cards, punched tapes, magnetic tapes, and magnetic disks.
When the control commands are read in, parameters to
control assembly processing are generated by designating
the assembly-control command.
In the assembly-processing stage, the source program is
read in, and the intermediate language is generated in phase
1. This intermediate language and the source program are
stored i'n the disk, and the absolute object is then produced.
That can be output on punched tape, magnetic tape,
magnetic disk or other media as specified.
CROSS-ASSEMBLER PROCESSING SYSTEM
OBJECT
MODULE
LIBRARY
!
t:J
6
6
ASSEMBLY
LIST
ABSOLUTE OBJECTS
PROGRAM ORDERING INFORMATION
Program name
Ordering No_
MELPS-8-48 cross assembler
GC1AS0200
Program and software manuals included
Source
MELPS
MELPS
MELPS
program
8-48 Assembler Language Manual GCM-SROO-01A
8-48 Cross-Assembler Manual GCM-SROO-02A
8-48 Cross-Assembler Operating Manual GCM-SROO-03A
• MITSUBISHI
;"ELECTRIC
14-37
MITSUBISHI MICROCOMPUTERS
MELPS 8-48 SOFTWARE
CROSS ASSEMBLER
CROSS·ASSEMBLER OBJECT LANGUAGE
2. Pseudo Instructions
The objects produced by this cross assembler basically
Although the pseudo instructions are written in the source
consist of name, symbol and text sections. An end section
program together with machine instructions, they control
is placed at the rear end of an object. Fig. 1 shows the
the cross-assembler execution during assembly processing.
object-module configuration. Each name section is placed
That is, they are not converted into instruction codes
at the head of each object module, and serves for recording
to be written in the ROM but are used to control the
information such as the name of the object module, ROMI
assembler.
RAM information, and the number of symbols. The symbol
These instructions include those used for assembly
sections are used to record information concerning the
control, numeric-symbo'l and memory-content definition,
numeric symbols (labels) written in the source program.
area securing, and list control. Table 3 lists the pseudo
instructions.
The text sections have data on the conversion of the source
program to the instruction code. The end section specifies
3. Macro Instructions
the termination of one object program.
These instructions consist of groups of several machine
ASSEMBLY LANGUAGE
language instructions or simple instructions used to specify
Machine instructions pseudo and macro instructions can
parameters. They consist of the 6 instructions MACRO,
be used in the ME LPS 8-48 cross assembler.
LOCAL, REPT, I RP, I RPC, and ENDM.
1 . Machine Instructions
A total of 96 basic machine instructions are available. They
are converted to their corresponding machine codes and
Fig. 1 Object-module configuration
Module 1
Module 2
Module n
~
then assembled into ari object program. A classification of
~----
these instructions is given in Table 2.
For the mnemonics, instruction codes and their functions, please refer to the data sheet provided for the single-
~~
chip 8-bit microcomputers M5L 8041-XXXP, M5L8048XXXP and M5L8049-XXXP.
Table 1 Control Commands and their Functions
Command
Format
Function
Execution-start control
lllRUN
Execution-end control
IIIEND
Terminates execution of the cross assembler.
IIIASMB4Q, X, Y, Z
Specification of the processor for which assembly Js to be performed and the ROM size
MM: Mode designation
MM=48 8048 mode (including 8049)
MM=41
8041 mode
X: Maximum ROM size designation
X = 1 - 4 for 1 - 4K byte
/I/OPTIN, XX, XX
Selection of assembly listing, reference listing, and symbol listing for the object code including
number of characters per line (same as /I/OPTIN, LS, XL when abbreviated)
XX: Output option selection
Assembly listing output
XX = LS
XX= XL Reference listing output
XX=SO Symbol object file output
80 characters per line (132 maximum when no specifications made)
XX = PL
/ I/INPUT, X(Y»)
Source input device designation (sames as /1/1 NPUT, C when abbreviated)
X: Source program input device
X=C
Paper card
X=D
Magnetic disk
Paper tape
X=P
Magnetic tape
X=M
Y: Magnetic tape character code (abbreviated as ASCII code)
Y=A
ASCII code
Y=E
EBCDEC code
Mode designation
Output OPtion designation
Source input
device designation
///MDISK, XXXXX
Fi Ie designation
I//SDISK, XXXXX
1/ /BDISK, XXXXX
14-38
Starts execution of the cross assembler in accordance with the command designated
Macro source working file name (maximum of 5 characters)
Source program file name (maximum of 5 characters)
Absolute object program file name (maximum of 5 characters)
• MITSUBISHI
. . ELECTRIC
MITSUBISHI MICROCOMPUTERS
MELPS 8·48 SOFTWARE
CROSS ASSEMBLER
4. Language Format
1. Label field
The following free format should be used in coding
programs in this cross assembler.
The single-line statement of the source program is
composed of label, instruction, operand, comment, and
identification fields. The format of the source statement
is free, as shown in Fig. 2, allowing easy coding and punching without the fear of dislocated columns. The following
characters can be used in statements.
•
Alphanumeric ................. A""'Z
•
Numerics ......................... 0""'9
•
Special Characters. .......... : ;
* / ! & ( ).
>? (blank)
Mnemonic codes of the machine and pseudo instructions are written in this field.
3. Operand field
instructions are written in this field. The label, defined
symbol, formula, or numerical value is contained
within it.
4. Comment field
Table 2 A Classification of Machine Instructions
Function
classification
2. Instruction field
Arguments (formula, data, parameters, etc.) for the
=,'" @ $ + -
#% <
The value of the program counter at that time is set to
the label. The number of characters used for a label is
limited to a maximum of 6. The character: is placed
at the back of this field. However, a semicolon (;)
cannot be used in the first column of the label field.
This field is used for writing notes for the statement
Functions of the instruction
Data-transfer
Instruction
Direct data setting
Between registers
Between memories and registers
and is not converted to an object. Placing a semicolon
Adding logic
operation
Addition, AND, OR, EXOR logic operations
Accumulator increase and decrease, clear and rotation shift.
decimal correction
comment. When a semicolon (;) is placed halfway
Register increment,
increment
is regarded as a comment.
Register increase
and decrease
register
(;) in the first column makes the whole statement a
decrement
data-memory
Flag control
Carry clear, carry correction, clear-flag 0, 1 and flag 0, 1
correction
Subroutine control
Subroutine jump, return from subroutine return and status
restore
Interruption control
External interruption possible
External interruption prohibited
Register-bank and memory-bank selection
Clock-output marble
through the statement, the section after the semicolon
Table 3 Pseudo Instructions
~
Item
Classification _ _ _ _ -
Between port and accumulator
Port and immediate-data OR and AND
Between bus and accumulator
Bus and immediate-data OR and AND
Between expander port and accumulator
Expander-port and accumulator OR and AND
Input/output
control
Jump instructions
Unconditional jump
indirect jump
Register decrement skip
Jump by carry 0, 1
Jump by accumulator 0 or non-zero
Jump by TO = 0 or 1
Jump by T1 = 0 or 1
JumpbyFO= 1 orFl = 1
Jump at the time of timer flag
Jump at the time of INT = 0
Jump by accumulator bit
Timer-counter
control
Timer/counter read
Timer/counter load
Timer start. counter start
Timer/counter stop
Timer/counter interruption allowed
Timer/counter interruption prohibited
Others
Assembler-control
Instructions
Numeric-symbol and
memory-content definition
instructions
Program-name declaration instruction
ORG
Program-counter setting instruction
EOT
END
End-declaration instruction
EQU
Numeric-symbol definition instruction
SET
DB
Data-setting instruction
Address-setting instruction
instruction
OS
Region-securing instruction
List-control
instruction
EJ E
Page-feed decldration instruction
Table 4 Macro Instructions
Instruction
Macro
Fig. 2 Source-Statement Format
II
Instruction
NAM
ow
Region-securing
No operations
1
Mnemonic
72 73
80
\
Description
Macro symbol definition instruction
ENDM
End instruction for a macro definition
LOCAL
Symbol replacement instruction
REPT
Repeat instruction
IRP
Infinite repeat instruction
IRPC
Direct number infinite repeat instruction
I)
Label field
Instruction
field
Operand field and comment field
Identification
field
• MITSUBISHI
.... ELECTRIC
14-39
MITSUBISHI MICROCOMPUTERS
MELPS 8-48 SOFTWARE
CROSS ASSEMBLER
2. MELPS 8/48 Assembler-Language Program
Table 5 Expression Formats for Numeric Values,
Character Constants and Formulae
1. General format of program coding
Expression
Item
LABEL
Binary
-
Octai
nQ
Decimal
n
I
S
IDENTIFICATION
SEQUENCE
72 73[74 75 7677 78798
Numeric
values
Hexadecimal
nH
A (l-byte)
"A"
AB (2-byte)
"AB"
A' B (3-byte)
"A" B"
Character
constants
Formulae
MNEM···········
OPE .............
;COMM .........
SEQ· ............
Program counter
Instruction symbol (mnemonic)
Operand (lor more blanks must always be included)
Comment (A semicolon (;) is always placed at the head)
Sequential No. (columns 73-80)
/
2. Example of program
-
Logic formula
Others
LABEL: ......... A colon (:) is always placed behind the label name
- *.
+.
4 Arithmetic-rule operations
000
010
020
SEa
LABEL
$
STATEMENT AND COMME
1 12 13 14 15 16 7 8 19 110111112113 14115116117118119120121122123124125126127128129\30\31\32\33\
:
1
:1
* * * PRO G R A,M E X AMP L:E * * * f··········· .:...(1)
* 0 E C I tMtA LAO 0 I T 1,0 N :
J
5. Identification field
The use of this field is optional. Many operators find it
J
convenient to use it for the sequential identification
card num ber.
X
CODING FORMAT
CNT
EaU
10
Programs written in the MELPS 8-48 assembler language
MtO V R 0 ,
MtO V R 1 ,
can be coded in free formats.
General formats for using the control commands and
MtO V
program coding for this cross assembler are described
B R:
below, together with a citation of a few examples.
1 . Control Commands
1. Control-command general format
J
LABEL
STATEMENT AND
,
N AM E X AM·············· .:........... '," '," '," '," '," '," .:.. '(Il,
R O,Mt· .. ······· .... ·.. ············ .:..............................:... Q)
EaU 10
:
1
:
R2 ,
#X
#Y
# CNT
I
:
J
~
~
1
:
f ............:... @
I
I
I
I
IJI
I
I
I
:
I
I
A, @RO·······_····:···· .. ························:···@
AOOC A, @R1·········:···············,···············:···®
OA A·············· .. ···········:··· .. ······· .. ··· .. ···· .. ·····:... @
MOV @RO, A············:······························:···RJ)
INC RO
'
1
: v.O>J
INC R1
,
J
:
o J N Z R 2 , B R .........:..............................:... @
Mt0V
=
1 I 2 I 31 4 I 5 I 6 7 8\ 9\10\11\12113 141151161171181191201211221231241251261271281291301311321331
I I IXYZ
, P 1 L' P 2 , P 3~':"'1
:
I
I I I I I I I I ' I I I
J
J
!
!
1
!
I
I
I
I
I
XYZ : Assembly-control-command symbols
CD The
P1. P2, P3' .............. ; Assembly-control parameters
2. Example of assembly control
LABEL
STATEMENT AND
11213141516 7 819110111112113 141151161171181191201211221231241251261271281291301311321331
I I IAS,M 48,L,C,N
IIISOI SK,XXXXX
I I I I
I
I
I
IIIRUN
The source program is input through the card reader. and an assembly list
14-40
output.
• MITSUBISHI
.... ELECTRIC
lines having a semicolon (;) in the first column are regarded as
comments
CZ) The program name is declared as "EXAM" by the NAM pseudo
Instruction.
Q) The following lines are regarded as a ROM region.
@ The decimal numbers 10. 50. and 10 are assigned respectively to
symbols X. Y. and CNT.
@ The program start address is address 500 in hexadecimal notation
@The values #X. #Y. and #CNT are respectively put into registers RO.
Rl.andR2
(J) The carry is cleared.
@ The contents of label BR memory at .RO (at the address to be jumped
to; the colon (:) shows a label) are put into accumulator A
CID The contents of the carry and data memory at Rl are added to each
other. and put into the acc~mulat"or
@ The accumulator contents are decimal-corrected
(jJ) The accumulator contents (decimal-corrected results of the addition)
are put into the memory data at RO
@ The contents of registers RO and Rl are incremented.
@ Register R2 is decremented and if the c~ntents are not 0 (zero).
branching to BR follows. If O. execution proceeds to next step
® The contents of the accumulator are output in port 1.
® The end of program is declared
MITSUBISHI MICROCOMPUTERS
MELPS 8-48 SOFTWARE
PAPER·TAPE GENERATION PROGRAM FOR PROM WRITERS
DESCRIPTION
•
This program is used to convert absolute binary object
Conversion of other hexadecimal paper tapes to MELPS
8 hexadecimal paper tapes
formatted programs, which are produced by the MELPS
I nput:
8-48 cross assembler, into other language formats and then
(even-parity ASCII code)
Output: paper tapes in MELPS 8 hexadecimal format
produce a paper tape that can be used as input for a PROM
writer.
The functional configuration of this program offers
(even-parity ASCII code)
•
automatic conversion of object programs from one format
Comparison of MELPS 8 hexadecimal with other hexadecimal paper-tape formats and self comparison
to another format as well as comparison processing. In
addition, it provides extensions suitable to various
appl ications.
I nput:
paper tapes (even-parity ASCII code)
Output: printed on system typewriter
•
FEATURES
paper tapes in other hexadecimal J format
Control-command input
Through system-typewriter keyboard
•
It selectively produces partitioned, punched paper tapes
with simple control commands.
APPLICATIONS
•
It converts MELPS 8 binary object programs stored on
disks into various hexadecimal formats on paper tape.
word
•
It converts various hexadecimal-format paper tapes into
MELPS 8 hexadecimal format.
•
Comparison-matching control functions for MELPS 8
hexadecimal format paper tape as well as other formats.
•
Output of various block sizes as specified by the block
size (i.e., paper-tape partition) parameter.
Sorting capability to put files in address sequence.
•
Execution computer: MELCOM 70 minicomputer
(memory capacity: more than 24K-words; program:
about 5,000 steps).
Implementation language: FORTRAN IV (parts are
written in assembler language).
INPUT/OUTPUT MEDIA
•
by 8-bit), M5L 2716K
(2K-word by 8-bit),
and
other similar ROMs when prepared by a PROM writer
produced by Takeda Riken, Minato Electronics, Pro-log,
and Data I/O.
FUNCTION
This program converts absolute binary object programs
(abbreviated MELPS 8 binary), created in the disk area by
the MELPS 8-48 cross assembler, into hexadecimal object
•
•
Programs are applicable to the M5L2708K and -S (1 K-
Conversion of MELPS 8 binary to hexademimal paper
tapes
programs. These hexadecimal object programs can be used
to program PROMs on PROM writers produced by Takeda
Riken (T310), Minato Electronics (Type 1830), Pro-log
Ltd. (Series 90), and Data I/O (abbreviated hereafter as
Takeda, Minato, Pro-log, and Data I/O). This program also
converts absolute binary object programs into the MELPS
8 hexadecimal format and creates paper tapes with blocks
of suitable size. The program can also convert paper tapes
of Takeda, Minato, Pro-log and Data I/O into MELPS 8
I nput: cartridge disk units
Output: paper tapes (even-parity ASCII code)
hexadecimal format and compare the object paper tapes.
THE TAPE PROCESSING SYSTEM
HEXADECIMAL OBJECT
FOR PRO-LOG
AND DATA I/O
HEXADECIMAL
OBJECT FOR
MINATO
HEXADECIMAL
MELPS 8
OBJECT
HEXADECIMAL
FOR TAKEDA
OBJECT
- - - - CONVERSION FROM PAPER TAPE
PROGRAM ORDERING INFORMATION
Program
Paper-tape preparation program for
MELPS 8/48 PROM writers
Program and software manuals Included
Program code no.
GA1SP0110
Paper-Tape Preparation Program for
MELPS 8/48 PROM Writers Manual
• MITSUBISHI
..... ELECTRIC
GAM-SROO-50A
14-41
MITSUBISHI MICROCOMPUTERS
MELPS 8-48 SOFTWARE
PAPER-TAPE GENERATION PROGRAM FOR PROM WRITERS
PAPER-TAPE PROCESSING
of processing. Table 2 shows a summary of the comparison
The program provides for both conversion and comparison
processing indicating the various combinations of object
of various object programs. Table 1 shows a summary of
programs and media that the program is capable of proc-
the conversion processing indicating various combinations
essing.
of object programs and media that the program is capable
Table 1 are illustrated in Fig. 1.
Examples of all the object conversions listed in
Table 1 Object conversions
y's
PROM writer
Paper tape block size
Hexadecimal paper tapes for PROM writers that
can be converted from MELPS 8 binary (on disk)
Hexadecimal paper tapes for PROM writer that can be
converted into MELPS 8 hexadecimal paper tape
Data I/O. Pro-log. Takeda
Conversion from eight blocks of Data I/O. Pro-log
or Takeda to one 2048-byte block
1024 bytes
Data I/O. Pro-log. Takeda. Minato. TDA-80
Conversion from one block of Data I/O. Pro-log.
Takeda or Minato to one 1024- or 2048-byte block
2048 bytes
MELPS 8 hexadecimal (for mask ROM)
256 bytes
Table 2 Comparison processing of object paper tapes
~ed
Comparison
Object
MELPS 8 hexadecimal self comparison
MELPS 8
absolute hexadecimal
Comparison of.MELPS 8 hexadecimal
with Minato hexadecimal
MELPS 8
absolute hexadecimal
Comparison of MELPS 8 hexadecimal
with Takeda hexadecimal
MELPS 8
absolute hexadecimal
Paper tape
.1 024-byte block
.2048-byte block
Hexadecimal for Takeda
Comparison of MELPS 8 hexadecimal
with Pro-log hexadecimal
MELPS 8
absolute hexadecimal
Paper tape
.2048-byte block
Hexadecimal for Pro-log
Paper tape
.Eight 256-byte blocks
.Two 1 024-byte blocks
Comparison of MELPS 8 hexadecimal
with Data I/O hexadecimal
MELPS 8
absolute hexadecimal
Paper tape
.2048-byte block
Hexadecimal tor Data 1(0
Paper tape
.Eight 256-byte blocks
.Two 1 024-byte blocks
Comparison object
MELPS 8 hexadecimal
Object
Media
Paper tape
.1 024-byte block
.2048-byte block
Paper tape
.1 024-byte block
.2048-byte block
Media
MELPS 8
absolute hexadecimal
Hexadecimal for Minato
Paper tape
.1 024-byte block
.2048-byte block
Paper tape
.1 024-byte block
.Two 2048-byte blocks
Paper tape
.Eight 256-byte blocks
.One 1 024-byte block
.Two 1 024-byte blocks
Fig. 1 Medium conversion
CONVERSION FROM MELPS 8 BINARY (ON DISK)
.1 024-BYTE
.256-BYTE BLOCKS
HEXADECIMAL
FOR DATA I/O.
PRO-LOG AND
TAKEDA
MELPS B
BINARY
000t] - OOOg
OFF
000
OFF
,
BLOCKS
MELPS 8
BINARY
ooot]
:
000
MELPS 8
HEXADECIMAL
FOR DATA 1(0.
PRO-LOG.
TAKEDA AND
MINATO
'
OOOm
3FF
000
OOOg
OFF
000
OFF
:
000
'
OFF
14-42
EIGHT
~
0000
:
_7FF
:
I
000
'
3FF
7FF
HEXADECIMAL
FOR DATA I/O.
PRO-LOG. TAKEDA
AND MINATO
OOOQ
MELPS 8
HEXADECIMAL
TWO
0000
~
3FF
7FF
OOO~
000
.
.1 024-BYTE BLOCKS
MELPS 8
HEXADECIMAL
ooot]
MELPS 8
HEXADECIMAL
3FF
CONVERSION TO MELPS 8 HEXADECIMAL
HEXADECIMAL
FOR DATA I/O.
PRO-LOG AND
TAKEDA
MELPS 8
BINARY
-000
000
OFF
.256-BYTE BLOCKS
.2048-BYTE BLOCKS
3FF
• MITSUBISHI
.... ELECTRIC
7FF
MITSUBISHI MICROCOMPUTERS
MELPS 8/85 SOFTWARE
PL/l.u CROSS COMPILER
DESCRIPTION
This cross compiler is supplied on magnetic tape to users
of MELPS 8/85 CPUs.
•
Assignment of programs to ROM or RAM regions
•
Generates a relocatable object program
It is written in FORTRAN IV for
•
Linking function
execution of the MELCOM 7000 and can be easily run
•
Easily understood error messages
on other host computers with a FORTRAN IV compiler.
•
Flexibility in input/output media
The PL/I,ulanguage gives MELPS 8/85 microcomputer
users the same advantages that users of mini and large
•
•
Execution computer: MELCOM 7000 (UTS/VS)
Implementation computer: MELPS 8/85 microcomputer
computer systems have with the high level programming
•
Implementation language: FORTRAN IV
languages that are currently available. It has the same
Of the PL/l,u Language
language structure as PUI and has been designed to take
•
Bit operations
advantage of the system architecture of the microprocessor.
•
Three-level structure
System designers can use PUIJ1 to quickly and easily
•
One-dimensional arrays
implement new applications. In addition, programs written
•
Allocation of variables to specified absolute addresses
PUIJ1 are self-documenting; so they can be easily
•
Multi-entry function
changed and maintained. PUIJ1 is recognized as one of the
in
•
Interrupt function
best suited languages for programming microcomputer
FUNCTION
applications
PUIJ1 has a preprocessor that allows user to modify programs under development at compile time through the use
because the user retains the control and
efficiency of an assembly language.
of conditional compile, exchange, exclude and include
FEATURES
Of the PL/l,u Cross Compiler
functions. A program is divided into fixed and variable
segments, and these segments are automatically assigned to
•
Conditional compile with preprocessor
the appropriate memory (RAM or ROM) during compiling.
•
Inline assembly
The link editor can link up to 20 object programs (files).
•
Source program editing at compile time
Fig. 1 PLlI,u cross compiler processing system
( SOURCE PROGRAM)
00NTROL INSTRUCTION0
QOB CONTROL LANGUAGE)
CROSS COMPILER
• COMPILE
MELCOM
7000
• LINK
PROGRAM ORDERING INFORMATION
Program name
Program and software manuals included
Ordering number
Source Program
MELPS 8/85 PL/lp cross compiler
GAITL0110
MELPS 8/85 PL/lp Compiler Summary Manual (C-version)
GAM-SROO-07A
MELPS 8/85 PL/lp Compiler Language Manual (C-version)
GAM-SROO-08A
MELPS 8/85 PL/lp Cross Compiler Operating Manual (C-version)
GAM-SROO-09A
MELPS 8/85 MELCOM 7000 PL/lp Cross Compiler Operating Manual
GAM-SROO-1OA
MANUALS
Manual number
Manual name
MELPS 8/85 PL/lp Compiler Summary Manual (C-version)
GAM-SROO-07A
MELPS 8/85 PL/lp Compiler Language Manual (C-version)
GAM-SROO-08A
MELPS 8/85 PL/lp Cross Compiler Operating Manual (C-version)
GAM-SROO-09A
MELPS 8/85 Assembly Language Manual (A-version)
GAM-SROQ-34A
MELPS 8/85 Cross Assembler Operating Manual (A-version)
GAM-SROO-02A
MELPS 8/85 Simulator Operating Manual (B-version)
GAM-SROO-35A
MELPS 8 Hardware Manual
GAM-HROO-01A
• MITSUBISHI
.... ELECTRIC
14 -- 43
MITSUBISHI MICROCOMPUTERS
MELPS 8/85 SOFTWARE
PL/1p CROSS COMPILER
OPERATIONS
Users of PL/lp will find it flexible and easy to use because
of its many special features such as the preprocessor, the
link editor and the memory manager.
The preprocessor has 10 statements that can be used at
compile time to edit a PL/I,u source program. These can
generate, exchange or delete program text, as well as
modify definitions, references and macro instructions.
The link editor is able to link up to 20 object programs
that have been generated by MELPS 8/85 software. The
memory manager divides PL/lp programs into fixed and
variable segments and assigns the segments to the appropriate memory. A fixed segment is assigned to a non-write
area (ROM) while a variable segment is assigned to a write
area (RAM) during compiling; at the same time, the starting
address of each segment is recorded for linking (see Fig. 2).
Fig. 2 Linking of two programs
«
::;;
«
cr:
l?
0
g:
I[] weO
(j)
1
8x
---'z
~LJ.J
a:~
«LJ.J
>(j)
ADDRESS ASSIGNMENT
J
A
2
l?
z
~
z
::J
C(}
::;;
«
cr:
l?
0
g:
ffif-
I[] weD
(j)
1
8x
---'z
~LJ.J
a:«LJ.J~
....
L
u::
~
f-
z
~
A
1
S3
u::
~
A
2
l?
~
(j)
8
x
f-
z
B
1
LJ.J
---'
C(}
«
a:
«
B
2
>
B
2
>(j)
u::
PL/I f1 LANGUAGE
The PL/IM language is a subset of the popular PL/I language
with the addition of special functions to take advantage of
the microprocessor's architecture. The main features of the
PL/IM language are as follows:
procedures. The statements are categorized as follows:
Statements -
Easy to Read and Write
Declaration:
The statements are written in free format and are independent of columns and lines. The statements are formatted
in natural language. It is easy to express, read and understand the programs. Programs written in PL/IM are selfdocumenting.
Block-Structured Language
Programs written in PL/IM consist of one or more blocks
that are called procedures. A procedure (block) can be
thought of as a subroutine. The block structure of PL/lp
simplifies modular programming. Each procedure can be
conceptually simple and therefore easy to formulate and
debug.
BASIC LANGUAGE SPECIFICATIONS
1. Statements
The basic unit of the PL/lp language is called a statement.
A procedure (block) is composed of one or more statements, and a program is composed of one or more
14-44
Procedure definition:
Cond ition:
Non-condition:
PROCEDURE
statement
DECLARATIVE
statement
IF statement
Assignment statement, DO group,
and others
The last character of a statement must be a semicolon
(;). A statement may have a label (identifier) that is the
name of the statement.
Example
EXAMPLE:X=Y+Z;
2. Identifiers
PL/IM identifiers are used to name variables, procedures,
macro instructions and statements. An identifier may be up
to 31 characters in length, and the first character must be
an @, ? or alphabetic (A'-Z) character. The remaining 30
characters may be alphanumeric (A-Z, 0-9), @ or ?
Reserved words may not be used as identifiers in the
PL/lp language.
• MITSUBISHI
.... ELECTRIC
MITSUBISHI MICROCOMPUTERS
MELPS 8/85 SOFTWARE
· PL/lp. CROSS COMPILER
3. Data Elements
ways in PL/IJ./. PL/IJ./ accepts constants in binary, octal,
decimal and hexadecimal bases and character strings (ASCII
or ISO code).
The PL/IJ./ data elements represent constants or variables
(1 ~16 bits in length), arrays (1 dimension) and 3-ievel
structure. Constants can be expressed in several different
Example of a PLllp program
I 21 31 41 51 6 7 81 9110111112113 14115116117118119120!21122123124125j 26127)28129130131132133134135136137138139140!41142)431441451461471481491501511521531541551561571581591606116216316416516616716*917
I
~*
T HIS I S A S AMp L E ,F qR, ,A: ,C,A,T,A,L,O,G, , :*,/, .. ,''',''',' .. ; .. ; .. ;'';'':.';'': .. ,.. ,' .. ,''','',''., .. ,''.:'',''.,''.,".,".,''',... ,.''O:>--.L
DEC LA REI
,
BIN A R Y: ( ,7, ) " '"
:,'
, " .' , ~ , , , , , , , , , : , , , ,
FOREVER BINARY: (7)
IN,IT:IAL (1) ,.......:.....................,...,...,...:...,...,...,...,...,' ..,...,.. \2),
I !
I
III!
111111!1!,!
1!lt~-i:f-L---'--"---L--'---'----'---'--'-l
I--l--'---'-"-""--+-+-L--'---,--,",-/L-*+--L--,--,-IL.:.F-'--.L.:~A:R, I,A,B,L E~O,R:E,V,E,R, , ~ ,S, ,T,R:UE", ,T,H,E, ,S,T:A,T,E,M,E,N,Tc-S-'--'--;+:--'--.L....L-'----'--'---L-L--'---i
UP TO THE CORRE:SPOND,I,N,Q ,E:N,D, ,A,R,E, ,E,X,E~CUTED
* I
DO
1*
~H
I LE FOREVER· ..... ;............................. ;............................. :............................. :........................ Q:)
READ :INPUT ~ORT: 10 AND SAVE IN VARI~ABLE
*/
'
I
1*
,
I
I
I == I N PUT! (1 0 ); ········~·····························;t····················i········;·····························;··j·····j"j";"j";"i®
T HI,S :V A,LU,E, ,I, ,I,S: ,U,S,E D, ,TP, ,S:E,L,E,C,T, .'-'O=N~E='-+-=:OCLCF--'---l.--'--:-'----'---'---l.--'--+--'--'----'--'---L-L-'----'L...L...J
THE S:TATE,M,ENTSOF DO-CASE: TO EX,ECU,T:E"
,*/""
, """'"
1--'---'--"---L--'--+-i---'---'--L-L--'---t'D=-c..=O.L.....LC-'=-"-A.l-"~L~-'··l"j""L".Li· ..i. :i· :..L"i·· i·· i·· i·· j .. j .. : •• i·· j •• j •. i·· j .. i·· i'· i·· i··:·· j •. i·· j .•...••............. : ..•..•.. i····· i·· i·· i·· iC§:)
DO;
•
,
I
OU T PUT
HALT;
(S) =08 H;
,
,
I
I
,
I
I
I
I
··~·····························~····················i ........ :.................... j ........ ··j··i··i··j··j··j·····i®
I
I
I
I
I
I
I
!
I
I!
!!!
ttl
I
1=1
OUTPUT
(S)=80H;
1=2
.
,
·
OU T PUT : ( S ) =40 H ;
END;
•
,
•
CD. Comments are preceded by '/*' and followed by , * / '.
CZ). The initial value of a type declared variable 'FOREVER'
is 1.
Q). DO-WH ILE group.
@). The device number of an input instruction is expressed
using a number.
®. DO-CASE group.
@. 08H used in the output instruction indicates a hexa-
decimal number of value 08 16 .
• MITSUBISHI
.... ELECTRIC
14-45
MITSUBISHI MICROCOMPUTEI
MELPS 8/85 SOFTWARl
PL/l,u CROSS COMPILER
LANGUAGE SPECIFICATIONS
Item
Specification
55-character set
Character set
Alphabetic
SpeCial
unit (
Comments
1*
Identifiers
31 or less alphanumeric characters
Reserved words
Constant types
Variable declaration option
Operators
) (n
? (blank)
*I
Binary. octal. decimal. hexadec Imal character string
BINARy(n) 1~n~15, BIT(m) 1 ~m~l 6
LABEL INITIAL BASED DATA BYTE ADDRESS
EXTERNAL INTERNAL ALIGNED UNALIGNED
* / MOD + - PLUS MINUS
< <= <> = )=
AND
OR
Arrays
One-dimensional. 1 -
Structures
Three-level. array structure
ExpreSSions
$ ). Numeric 0 - 9
: ; < > % '(
I F DO GO TO OR BY ON
EOF END XOR AND NOT
MOD HALT THEN ELSE
CASE CALL GOTO DATA
BYTE PLUS MAIN LABEL
BASED MINUS WHILE
ENTRY ENABLE RETURN
BINARY DISABLE DECLARE
ADDRESS INITIAL
ALIGNED OPTIONS
INTERNAL EXTERNAL
RELOCATE GENERATE INTERRUPT
PROCEDURE LITERALLY
UNALIGNED
NOT
)
XOR
255 elements
Arithmetical expression. logical expression. structured expression
Statements
Insert state,ment, GOTO statement, IF statement, CALL statement,
GENERATE statement, RETURN statement, HALT statement,
DECLARE statement, ON statement, PROCEDURE statement,
DO group, ENTRY statement, NULL statement, RELOCATE statement,
ENABLE statement, DISABLE statement,
DO group
DO WH I LE, repeat DO, DO CASE
library functions
Preprocessor statements
14-46
A - Z . Currency
=+-*/,
TIME MEMORY SHL SHR ROL ROR INPUT OUTPUT
DEC HIGH LOW LENGTH LAST CARRY ZERO SIGN
PARITY
% insert statement, %A C T I V ATE statement, %D E ACT I V ATE statement,
%E NDstatement, %E XC L U D E statement, %GOT 0 statement, % I Fstatement,
% INC L U DE statement, %M A C R 0 statement, %N U L L statemen t
• MITSUBISHI
.... ELECTRIC
MITSUBISHI MICROCOMPUTERS
MELPS 8/85 SOFTWARE
SIMULATOR
DESCRIPTION
•
A pseudo CPU and a pseudo memory are modeled in the
Programming language: FORTRAN IV (parts are written
in assembly language)
host computer by the simulator, and programs in the
pseudo memory are executed by the pseudo CPU to debug
FUNCTION
and test programs.
The trace command function assigns a specific trace region
The simulator contains a powerful set of 26 control
so that it traces only the specified program steps. Execution
commands for efficient program debugging.
of the simulation can be halted by a breakpoint that can
FEATURES
be assigned to any location. Program debugging efficiency
•
Set of 26 powerful control commands
can be expected to increase by the use of these functions.
•
Batch and conversational processing
•
Symbolic addressing
•
Execution time calculations
and will not allow either reading or writing in a memory
•
I ntermediate results saved in specified format
protect region. Therefore, the program under simulation is
Binary, octal, decimal and hexadecimal numbers are
completely simulated, including the state of the memory in
selectable
the object computer system.
•
Memory protect and ROM regions are simulated. This
means the simulator will not allow writing in a ROM region
•
Assignment"of program segments to ROM or RAM region
•
Memory protection
Input/output media
•
Object program input:
Paper tape, magnetic tape and
•
I nterrupt function
•
Flexibility in input/output media
•
Continuous processing of input/output data
•
Control command input:
Punched card and keyboard
Execution minicomputer: MELCOM 70 (memory capac-
•
Simulation intermediate
Magnetic tape and magnetic
results output:
disk
•
Simulation result output: List
•
Input/output data:
•
magnetic disk
ity more than 24K words, monitor BDOS)
(
)
ABSOLUTE OBJECT PROGRAM
QQ
Punched
card,
keyboard,
paper tape and magnetic tape
SIMULATOR PROCESSING SYSTEM
(
(
CONTROL COMMANDS)
JOB CONTROL COMMANDS)
Cl
C]
!
+
I
SIMULATOR
(
MELCOM 70
C'-___IN_T..,...E_RM_E_D_IA_T_E_R_E_SU_L~T-S-----')
I
I
o
0
I
('--_E_X_EC;....U_T.....:;IO~N_R-=E-=-SU.::...:L=-T-=-S_A_N_D,M;...:E:.:S.::..SA_G.::...:E:.:S--'
~
L---J
I
CJ
PROGRAM ORDERING INFORMATION
Program name
Ordering number
MELPS 8/85 simulator IB-version)
GA1SMOll0
Program and software manuals included
Source Program
MELPS 8/85 Simulator Operating Manual IB-version)
GAM-SROO-35A
MELPS 8/85 Cross Assembler & Simulator Operating Manual (on MELCOM 70)G AM -SROO -04A
MANUALS
Manual name
Manual number
MELPS 8/85 Assembly Language Manual lA-version)
GAM-SROO-34A
MELPS 8/85 Cross Assembler Operating Manual lA-version)
GAM-SROO-02A
MELPS 8/85 Simulator Operating Manual IB-version)
GAM-SROO-35A
MELPS 8 Hardware Manual
GAM -HROO-Ol A
• MITSUBISHI
;"ELECTRIC
14-47
MITSUBISHI MICROCOMPUTERS
MELPS 8/85 SOFTWARE
CROSS ASSEMBLER
CROSS ASSEMBLER FUNCTIONS
SOURCE
PROGRAM
The control commands and pseudo instructions in this cross
assembler give the user flexibility and improve the efficien-
The control commands are shown in Table 1, and the
features and their limitations are shown in Table 2.
Table 1 List of control commands
B"
'I
BLK
2
I
BLK
0
II
O"ly the block deSignated with thiS
.
number IS assembled
BLK
RUN
END
ASMB8
BLOCK
SDISK
ODISK
BDISK
LINKG
LKLOC
Execution start
Assembler control
End
Input! outplJt assignment
g
8
Assembly
Block assignment
control
command
File assignment
c
~
~
Link control
command
Link assignment
Link location assignment
Table 2 Cross
as~embler
features and their limitations
Limitations
Features
~
Relocatable object programs
Maximum 20 programs on the disk
Link editor
~
Program segmented to non-write
area (ROM) and write area (RAM)
Multi-assembly
Maximum 9999 programs
Conditional assembly
Maximum 20 blocks
Flexibility in 1/0 media selection
Card. disk, paper tape, magnetic tape
!
ASMB8, L, D, S
0
BLK
[ :~~K't""-
0
B" ,
BLK
I
3
Mnemonic
Control command name
Classification
I~
BLK
cy of programming. The cross assembler allows linking,
mUlti-assembly and conditional assembly.
OBJECT
PROGRAM
CONTROL
COMMAND
0
3. Linking of ROM/RAM Regions
ROM and RAM regions are linked separately.
CONTROL
COMMANDS
SOURCE
PROGRAM
~
NAM
RAM
MOV
PRI
A,B
f-
ORG
MOV
100:::
B,C
f-f-
C,D
f-f-
D, E
f-I---
ROM
MOV
RAM
MOV
END
NAM
RAM
MVI
ROM
MVI
B,20
RAM
MVI
ADD
C,10
C
/ / ! LKLOC, 0, 1000
r-h
PRZ
0:::
MOV
MVI
1~00:::
I
A, 50 t - - - ~
I
C,D FIRST
B,20 A DDRESS OF
ROM REGION
100:::
n
r----
If
OBJECT
PROGRAM
MOV
B,C
MOV
MOV
MVI
MVI
ADD
A,S FIRST
D,E ADDRESS OF
A,50 RAM REGION
C,10
C
I
I
I
I
I
I
END
1 . Multi-Assembly
Many programs can be batch-assembled in one run.
CROSS-ASSEMBLER OBJECT PROGRAM
SOURCE PROGRAMS
NAM
END
~
I
I I I A 5MB 8,
IIIRUN,n
I
fNAMI
CONTROL COMMANDS
L, C, 5
The cross-assembler object program is composed of many
object modules, and each module is composed of a name, a
symbolic part and a text part. A final part ends each object
program.
The symbolic part contains the symbolic name corre-
n source programs
sponding to symbols. It is possible to program using
where 1 ~ n ~ 9999
symbolic names because each module contains a symbolic
part.
NAM
END
The object is composed of an 8-bit binary code, and one
$$
byte of the instruction code is expressed with one character
(8 bits).
Fig.1 Structure of object modules within an object program
2. Conditional Assembly
Only
the designated blocks of a source program are
assembled.
14-48
MODULE 1
• MITSUBISHI
"'ELECTRIC
MODULE 2
MODULE n
MITSUBISHI MICROCOMPUTERS
MELPS 8/85 SOFTWARE
CROSS ASSEMBLER
ASSEMBLY LANGUAGE FUNCTIONS
2. Pseudo Instructions
The assembly language consists of mnemonic instructions
Pseudo instructions control the execution of the cross
(each corresponding to a machine language instruction),
assembler while source programs are being assembled. They
pseudo instructions and macro instructions.
are not assembled as instructions in the object programs. As
Pseudo instructions are executed by the cross assembler
when a source program is being assembled, and they modify
the object program.
Macro instructions are converted to
small segments of machine instructions that are then inserted in the object program. These inserted segments
shown in Table 4, there are 13 pseudo instructions.
Table 4 List of pseudo instructions
Mnemonic
symbol
Classification
Assembler control
instructions
NAM
ORG
ROM
RAM
execute the functions of the macro instruction.
Algebraic expressions, alphanumeric constants, character
strings, octal numbers, decimal numbers, hexadecimal numbers and symbols may be used as an operand in instructions.
Link Symbol assignment
instructions
1. Machine Instructions
Memory contents
definition instructions
There are 78 basic machine instructions. These are converted
to their corresponding machine language instructions and
then inserted in the object program.
Storage allocation instructions
List control instructions
A summary of the machine instructions is given in Table 3.
Name
Program na me declaration
Program counter setting
ROM region declaration
RAM region declaration
BLK
Block declaration
END
ENT
EXT
EQU
DEF*
DADR*
B SS**
EJE
End declaration
Entry name declaration
External reference sym bol declaration
Value symbol setting
Data setting
Address setting
Storage allocation
Page eject declaration
* DEF and DADR pseudo instructions set the data or the address in the memory location
where the instruction is. See Fig. 2.
* *SSS pseudo instruction sets the program counter to the value of the operand
Table 3 Summary of machine instructions
Classification
Instruction functions
Direct data set
Data transfer instructions
Addition, subtraction, logical
operations and compare
instructions
Fig. 2 Example of DEF and DADR pseudo instructions
Between registers
Between memory and registers
CONTENTS
OF MEMORY
Addition, subtraction, comparing and logical operI ations using the accumulator together With registers, memory or carry flag
A:::r
'A,,1F#~
~
o0
,LAB
'Increment and decrement
instructions
Registers, register pairs and memory incremented
or decremented
Circulate and shift instructions
Circulate or shift the accumulator's contents
Accumulator adjust instructions
Complement. decimal adjust
Carry instructions
Complement. set
Jump instructions
Subroutine call instructions
Return instructions
Stack operation instructions
Others
DEF
DEF
DADR
DADR
1
o~
o0
o0
15B~ o 0
265~ o 0
0 1
,
1 1 1
0 0 1 1 0 1
0 0 0 o 0 0
0 0 1
o0
1
00000001
Unconditional jump
Conditional jump
Unconditional subroutine call
Conditional subroutine call
Unconditional return
3. Macro Instructions
Conditional return
Macro instructions are converted to object program segments
Input/output control instructions Input and output control
Interrupt control instructions
LAB
0 0 1 0 1 0
0100000 1
Enable interrupts
Disable interrupts
Saves the contents of registers
Restores the contents of registers
CPU halt
No operation
in machine language that executes the macro instruction
functions.
The following two macro instructions are
included in this cross assembler.
Table 5 Macro instructions
Instructions
GET
PUT
i
i
,
,
Corresponding statement
Name
j
j
Data input instruction
Data output 'instruction
IN
OUT
n
n
i
where
~
'\
jA7j A6j Asl A41 A31 A21 All Ao I
n=64i+j
• MITSUBISHI
"ELECTRIC
14-49
MITSUBISHI MICROCOMPUTERS
MELPS 8/85 SOFTWARE
CROSS ASSEMBLER
CODING EXAMPLES
1I213141 516 7 sl 9110111112113 1411SI1611711SI19120!2112212312412S126127j2~2ID3~31l3~33
*
* ,* * *
*
Examples of coding using control commands and the
assembler language of the cross assembler follow.
1. Control Commands
NA,~
EXT
EXT
ENT
ROM
1. Control commands are in the following general form:
11213141516 7 S19110111112/13 14/1sI1611711SI1912012112212312412§l261ni2~2~3QL3!l3gL33
[,Pa ram.eter: Lis t ]
I IIS,y", bol
M,AI N
:):
* * * ~ ......(j)
E X,AMP L E ,QF
EQU
C,QD! I N,G
J:
P RQ~""""~""""""""""""""'~"""®
TAB 1 , T A:B 2 , TAB 3
f) .. )(3)
TAB 4 , T A:B 5 , TAB 6
]
IMA IN ..... ;............................ j; ......@
......................... ~ ............................. ~ ...... @
* ..............;............................. ;......@
10~~~~~L~X~I~LL~H~,~T~A~0~1~:·~···~··_··~···~··~···~··_··~···~··~··_·.~~
.. ~
...~.~~7
IMVI
MV I
2. Two source programs are read in from the card reader,
and the assembly lists are printed.
11213141516 7 SI9110111112113 14/1SI1611711SI1912012112212312412SI2612712SI29130131132133
I I I AS~ B85,L,C ,S
IIIRUN ,2
LOA
*
program is generated and filed in RF11 on the disk.
:
;
C
B,
,
*-7 ........ ;............................. ;...... @
1000
:ERR, SHOR I !...... @
MV I
MOV
PCHL
*
;';';' LIN K~, R , N , 0 , F 1 1 , F:l 2 , F 1 3 , F 1 4:
II'/BDISK,RFll
'"":,
:
INR
OCR
JNZ
JMP
H,O
L,C
LXI
B,SENS
DAD
H
25~~LL~~D~A~D~~tB~~~-L~-L~~~~~~~
LOOP2
the disk are linked together, and a relocatable object
..... ~ ............................. ~ ...... @
I NDATA :
:
LOOPl
15 1-l-~--J........I-+-+-=J=Z:J........L..--J........I--t-=L=O=O=P..J.:2:.J,.......L-:-L....J.....J........L....J........L--'--'--'-;--'-~
INX
H
20
3. Four object programs (files) F11, F12, F13 and F14 on
C,O
B, 6B
,
RAM
,
,
"
".1:' .................... ; ............................. ; ...... (jJ)
30 ~1:N;:D-'!!.,;A-:I..!'-T;A;:FD:~E=.;.;=F:...J~_-L.~-+4..:..J..::5J.,;..j:j:~_
...L-.........'+~.~.. -...L-..................-J... _...L-..~
.................._.. "~" -("'1[I~
'+-'
.' . . . . .
*
IIIRUN
TAOl
SENS
~!~R
*
END
;~: ~P ~.~;.~
. . :::::::::::::::::::::::(:::g
2. Assembly Language
1. A statement is of the following general form:
112131415161 71 SI911011111211311411sI1611711sI1912012112212312412sI2612712s129130!31 132133
Symbol]luIMnemonu[Operand] :
:
Jl
II
where
LJ
I
1
.L....L..L.L.L~_-L-LJ .. ,
40~~~~LL~LL~LL~-L~~~~~-L~~~~~
CD An asterisk in the first column indicates that the entire
:
statement is a comment.
®
indicates a blank, and [ ] defines a field that is
The program name is declared as 'PROM'.
G) The external programs referenced by this program are
optional.
declared.
@ The external programs that reference this program are
2. This example evaluates the data in address INDATA
against the table at address TA01. It then jumps to the
declared.
@ The program segment from here to the next RAM
appropriate processing program according to the evaluation. The first address of the corresponding processing
pseudo instruction is regarded as a ROM region.
@ The symbol MAIN refers to the value in the program
program is located at address SENS.
location counter at this source program statement.
(J) Locations can be referred to by symbols.
@ Octal numbers can be used.
®
Expressions can be used in the operand field.
@ The statement following a blank after an operand field is
a comment.
(jJ) Declares the start of a RAM region.
@ Hexadecimal numbers can be used.
@ Character constants in ASCII code can be used.
G3> The address of symbol TAB 1 is set to the location of
address SENS and SENS+l.
14-50
• MITSUBISHI
.... ELECTRIC
MITSUBISHI MICROCOMPUTERS
MELPS 8/85 SOFTWARE
CROSS ASSEMBLER
DESCRIPTION
This cross assembler is used to convert source programs in
•
Implementation language: FORTRAN
(8-bit binary format) on a host computer. The assembly
language consists of mnemonic instructions (each mnemonic
instruction corresponds to a machine language instruction),
pseudo instructions and macro instructions.
It is obvious
that the assembly language makes programming and modification of programs easy. The pseudo instructions and
control commands in this cross assembler give the user flexi-
(parts are
Of the Assembly Language
•
13 pseudo instructions
•
Algebraic expressions
•
Character constants and strings
•
Octal, decimal and hexadecimal numbers
•
The mnemonic codes of the machine instructions are the
same as Intel's
bility and improve programming efficiency.
FEATURES
INPUT/OUTPUT MEDIA
Of the Cross Assembler
•
•
IV
written in assembly language)
assembly language to object programs in M ELPS 8/85 format
Punched
Source input:
Generates a relocatable object program
card,
paper
tape,
magnetic tape and magnetic
•
Linking function
•
Multi-assembly
•
Object input:
Magnetic disk
•
Conditional assembly
•
Control command input:
Punched card
•
Flexibility in input/output media
•
Object output:
Paper tape, magnetic tape and
•
Output of symbolic table of the object program
•
Execution computer: MELCOM 70 (memory capacity
disk
magnetic disk
more than 24K words, monitor BDOS)
CROSS ASSEMBLER PROCESSING SYSTEM
(
SOURCE PROGRAM)
(
CONTROL COMMANDS)
QQQg
D
(
Q
JOB CONTROL LANGUAGE)
DC]
CROSS ASSEMBLER
• ASSEMBLER
MELCOM
70
PROGRAM ORDERING INFORMATION
Program name
Ordering number
Program and software manuals included
Source Program
MELPS 8/85 Assembly Language Manual (A-version)
MELPS 8/85 cross assembler
GA1AOll0
MELPS 8/85 Cross Assembler Operating Manual (A-version)
MELPS 8/85 Cross Assembler & Simulator Operating Manual (on MELCOM 70)
MANUALS
Manual name
Manual number
MELPS 8/85 Assembly Language Manual (A-version)
GRM-SROO-34A
MELPS 8/85 Cross Assembler Operating Manual (A-version)
GAM-SROO-02A
MELPS 8/85 Simulator Operating Manual (B-version)
GAM-SROO-35A
MELPS 8 Hardware Manual
GAM-HROO-01A
• MITSUBISHI
~ELECTRIC
14-51
MITSUBISHI MICROCOMPUTERS
MELPS 8/85 SOFTWARE
SIMULATOR
METHOD OF CODING CONTROL COMMANDS
The input formats for control commands are shown in Fig. 1.
Fig. 1 Input formats for control commands
1
Column no.
72
Contents
Blank
No. of columns
lor more
columns
Command
The number of
characters in the
command
Blank
Parameter list
Blank
1 or more
columns
The number of
characters in the
parameter list
1 or more
columns
80
Sequence number
8 columns
Free
Not required if the command is
typed in from the systen: typewriter
The command. parameter list and comment
must be less than 73 columns.
Remarks
73
Comment
CONTROL COMMANDS
The simulator includes 26 control commands as shown in Table 1.
Table 1 List of control commands and their functions
~
Control commands
Comments
Functions
~
Start
E
End
~
Program loading or
~
E
8
Action
Mnemonic com mane
Start simulation
START
Starts simulation and designates the input unit for control commands.
Reinitialize
glNIT
Sets the state to the same state it was after the START command execution was
comp'leted
End simulation
~D
Returns to the monitor when executed during simulation.
Load object program
LOAD
results
Save intermediate results
MVE
The absolute object program or the saved intermediate partially executed program is
loaded
All information such as executed commands. contents of registers and flags. and so
forth. are saved in external memory
Changing control
Changes to card reader
MTCH
The command input unit is changed to the card reader
command input unit
Changes to system typewriter
TYPE
The command input unit is changed to the system typewriter.
Start
Starts execution of the object
program
Starts execution of the object
program
go
The stop point can be designated by either an address or the number of
instructions to be executed.
1!QN
Continues execution until a HL T Instruction is encountered
Assigns a breakpoint
~EAK
A breakpoint is assigned by an address or a range.
Releases an assigned breakpoint I
NOBREAK
A breakpoint assigned is released.
Steps
STEP
Breakpoints are assigned after every specified number of machine instructions.
Assign s a ROM region
ROM
It is declared that region assigned with this command is the ROM region.
Releases an assigned ROM region
Assigns a memory protection
region
NOROM
The assigned ROM region is released
~OT
A memory protect (unaccessible) region is assigned
E
Releases an assigned memory
protect reg ion
NOPROT
g
Assigns a trace region
TRACE
Printing out the contents of registers. the program counter and flip-flops along with
the executed instruction codes while executing the instructions in a trace region
Releases an assigned trace region
NOTRACE
The assigned trace region is released.
Set data
~ET
Registers. stack pointers. program counter. flag flip-flops. I/O ports and the contents
of memory are set
Interrupt
!J!T E R
If interrupt is enabled. within 3-byte instruction associated with this command is executed.
8
~
Vi
saving intermediate
Stop
Assigning memory
"0
c
regions
E
8
8
(l)
An assigned memory protect region is released.
Trace
>
<='
:::J
u
(l)
x
w
UME
Counts the total number of cycles of the machine instructions executed before this
command is encountered.
Assigns a base
~ASE
A base for printing is assigned.
Prints out
QI SPLAY
The contents of registers. stack pointers. program counter. flag flip-flops. I/O ports. and
memory are printed according to the assigned base
Counts the number of cycles
Printi n gout
Conversion of values
r-~
CONY
The current program counter or the assigned value is printed out in binary. octal.
decimal or hexadecimal.
S2 E Input/output simulation
Input simulated
il
Defines an input string for a machine instruction IN
-
Output simulated
OP
Defines an output string for a machine instruction OUT.
~
Note 1: The underlined part of the mnemonic command can be used as a short mnemonic.
2: The control command 'START is the first command. and its input unit must be the card reader.
14-52
• MITSUBISHI
.... ELECTRIC
MITSUBISHI MICROCOMPUTERS
MELPS 8/85 SOFTWARE
SIMULATOR
EXAMPLE OF SIMULATION
The program shown in Fig. 2 is simulated using the control
command in the sequence shown in Table 4. The program
in Fig. 2 is named 'CON102'. It converts a decimal integer
(O~65,535) to a binary number.
The decimal number to be converted is stored in addresses DED1~DED5 in ASCII code, and the converted
result is stored in addresses BID and BID+1 (see Table 2).
Further, if characters other than O~9 are found in addresses
DED1~DED5, the A register is set to ' l ' as an error flag;
and if the converted result is more than 65,535, the carry
flip-flop is set to' 1 ' as an error flag.
The simulation is executed in three segments as follows:
1. The test values are set in memory addresses DED1~
DED5.
2. The program is executed.
3. The simulator confirms that the contents of addresses
BID and BID+1 are the correct value for the conversion
of data in addresses DED1 (address 9113)~DED5
(address 9117). At the same time, it confirms that the
contents of register A and the carry flip-flop are
correct.
Fig. 2 Assembly listing of the objective program "CON102"
The objective program listing is shown in Fig. 2, and
explanations of the simulation control commands using this
example are shown in Table 4.
Table 2 Memory location and contents
Explanation of can tents
Contents
Address
a
DEDi
DED2
b
The 5-digit decimal integer is a X 10 4 + b X 10 3 +
DED3
c
X 10 2 +-d Xi 0+8 and a, b, c, d and e are set in
Df:.D4
d
ASCII code.
DED5
0
BID
Converted
results
BID+1
C
Low-order 8 bits are stored in BID and high-order 8 bits
in BID+1.
Table 3 Error flags for conversion
~
Number to
be converted
Error and no error display
Converted result
A register
Carry flip-flop
O~65,535
0
0
More than 65,535
0
1
Not correct
0
Not converted
Integer
Cha racter other than
decimal digits
Note 3
1
Correct
Overflow is displayed by being carry flip-flop as 1, and error is so A resister
as 1,
**CROSS ASSEMBLER OF 8-BIT MICROPROCESSOR
0001*
CON102
0002*
0003*
0004 2328
0005 2328 219923
0006 232B 0605
0007 232D 7E
0008 232E FE3B
0009 2330 DA9423
0010 2333 FE3B
0011 2335 D29423
0012 2338 23
0013 2339 05
0014 233A C22C23
0015 )33D 3A9D23
0016 2340 D630
0017 2342 2600
0018 2344 6F
0019 2345 3A9C23
0020 2348 D630
0021 234A 110AOO
0022 234D CA5523
0023 2350 19
0024 2351 3D
0025 2352 C34D23
0026 2355 3A9B23
0027 2358 D630
0028 235A 116400
0029 235D CA6523
0030 2360 19
0031 2361 3D
0032 2362 C35D23
*
*
*
CON102
C0100
D23
COOOO
COO01
C0101
COO02
C0102
ORG
LXI
MV I
MOV
CPI
JC
CPI
JNC
INX
DCR
JN2
LDA
SUI
MVI
MOV
LDA
SUI
LXI
JZ
DAD
DCR
JMP
LDA
SUI
LXI
JZ
DAD
DCR
JMP
9000
H', DE D 1
B,5
A,M
48
ER
59
ER
H
B
C0100
DED5
48
H,O
L,A
DED4
48
D, 10
COO02
D
A
C0101
DED3
48
D, 100
COO03
D
A
C0102
0033
0034
0035
0036
0037
0038
0039
0040
0041
0042
0043
0044
0045
0046
0047
0048
0049
0050
0051
0052
0053
0054
0055
0056
0057
0058
0059
0060
0061
0062
0063
2365
2368
236A
236D
2370
2371
2372
2375
2378
237A
237D
237F
2382
2385
2386
2387
238A
238D
2390
2391
2394
2396
2397
2398
2399
239A
239B
239C
239D
239E
2328
• MITSUBISHI
"ELECTRIC
3A9A23
D630
11E803
CA7523
19
3D
C36D23
3A9923
FE37
D29023
D630
111027
CABA23
19
3D
C38223
229E23
C39723
37
C39723
3E01
A7
00
76
00
00
00
00
00
0000
COO03
C0103
COO04
C0104
COO05
OV
ER
COO06
DED1
DED2
DED3
DED4
DED5
BID
LDA
SUI
LXI
JZ
DAD
DCR
JMP
LDA
CPI
JNC
SUI
LXI
JZ
DAD
DCR
JMP
SHLD
JMP
STC
JMP
MVI
ANA
NOP
HLT
DEF
DEF
DEF
DEF
DEF
DADR
END
DED2
48
D,1000
COO04
D
A
C0103
DED1
37j:j:
OV
48
D,10000
COO05
D
A
C0104
BID
COO06
COO06
A,11
A
0
0
0
0
0
14-53
MITSUBISHI MICROCOMPUTERS
MELPS 8/85 SOFTWARE
SIMULATOR
Table 4 Example of the use of simulation control commands
MELCOM 70 is used as the host computer. and the input unit for the control commands is selected to be the card reader.
STA RT M70,CARD
lOAD
START,5
The object program is input from the paper-tape reader (device number 5)
SET CPU SP=10000 PC=9000
The
SET MEMORY,DED1=31#
Data is set in memory. 31# is stored in location DED1. 32# in DED2. 33 # in DED2 + 1. 35#
SE M,DED2:DED5=32#,33#,35#,37#
in DED2 + 2. and 37# in DED5
BREAK COOO2,COOO3,COOO4,COOO5
Breakpoints are assigned.
DISPLAY CPU,SP,PC
D M, DED1 :DED5
~lac.;k
puinler is sel lu lhe value 10.000. and lhe plOIJrarn wunler is
~el
lu lhe value 9.000.
Displays the contents of the stack pointer (SP) and the program counter (PC) for confirmation.
Confirms whether or not the correct value is set in memory .. Here.
o is the abbreviated command
for DISPLAY and M for MEMORY.
The program is executed until the machine instruction HLT is encountered. printing out the
GO
*
contents of the PC and SP registers and flip-flops at each breakpoint that was assigned by
BREAK above
Confirms whether the conversion is correct or not. displaying the result of the conversion in
D M, 91 19: 91 20 (@')
binary form. It can also be confirmed by finding the change of the contents of registers Hand L
in the list that is printed out during execution
TIME
The number of cycles executed is counted.
NOBR COOO2,COOO3,COOO4,COOO5
S M,DED1=36#
S M,DED2:DED5=35#
S M,DED4=43#
S CP,PC=9000
The breakpoints assigned with BREAK are released.
GO
Executes until a HLT instruction is encountered
36# is set in address DED1. 35 # in addresses DED2 ~ DED5 and 43 # in address DED4.
9.000 is set in the program counter.
The data and the result are printed in the hexadecimal because the BASE command is not used.
D M,9113:9120
In this case. including a character other than 0 ~ 9 confirms whether or not a '1' is set in the A
register after execution
SAVE
2,SAV1
Intermediate results are saved in file SAVl of the disk.
START M70,C
MELCOM 70 is used as the host computer. and the input unit for the control commands is
selected to be the card reader.
lO CONT,2,SAV1
The intermediate results that were saved are loaded from the disk. The file name is 'SAVl'.
TYPE
The input unit for control commands is changed from the card reader to the keyboard.
S CUP,SP=10000,PC=9000
S M,DED1:DED5=37#,35#
The program counter and the stack pointer are set.
37 # is set in address DED1. 35# in DEDl +1.37# in OED 1 +2. 35# in OED 1 +3 and 37#
in DED5.
Executes until a HLT instruction is encountered. Confirms whether or not a '1' is set in the carry
GO
flip-flop because the data exceederl 65.535.
S CPU,PC=9000
The start address is set.
S M,DED1:DED5=30#
301# is set in addresses DEDl ~ DED5.
GO
Executes until an HLT instruction is encountered.
D M,9113:9120
Confirms the conversion result
S CPU,PC=9000
The start address is set.
S M,9113=36#
S M,9115=35#
36# is set in address 9113.35;# in address 9115.
GO
Execution starts. Executes until an HLT instruction is encountered.
D M,9113:9120
Confirms the conversion result.
END
Declares the end of simulation.
14-54
• MITSUBISHI
.... ELECTRIC
MITSUBISHI MICROCOMPUTERS
MELPS 8/85 SOFTWARE
PAPER-TAPE GENERATION PROGRAM FOR PROM WRITERS
DESCRIPTION
hexadecimal paper tapes.
This program is used to convert absolute binary object for-
Input:
Output:
cross-assembler, into other language formats and then produce a paper tape that can be used as input for a PROM
writer_
•
The functional configuration of this program provides
•
FEATURES
Paper tape in MELPS 8 hexadecimal format (even-parity ASCII code)
Compares MELPS 8 hexadecimal with other hexadecimal
paper-tape formats.
Input:
for automatic conversion of object programs from one format to another format. In addition, it provides extensions
suitable to various applications.
Paper tape in other hexadecimal format
(even-parity ASCII code)
matted programs, which are produced by the MELPS 8/85
Paper tape (even-parity ASCII code)
Output: Printed on system typewriter.
Inputs system commands.
Input using the keyboard of the system typewriter
APPLICATIONS
•
Producing, selectively, punched paper tapes with simple
control commands
•
Converting MELPS 8 binary object programs stored on
disks into various hexadecimal formats on paper tape
•
Converting various hexadecimal formatted paper tapes
into MELPS 8 hexadecimal format
•
Matching control functions for MELPS 8 hexadecimal
formatted paper tape as well as other formats
This program converts absolute binary object programs
Output of various block sizes as specified by the blocksize parameter
ME LPS 8/85 cross assembler, into hexadecimal object programs. These hexadecimal object programs can be used to
•
•
Programs are applicable to the M58563S (256-word by
8-bit), M5L2708K, S (1024-word by 8-bit, M5L2716K
(2048-word by 8-bit) or other similar ROMs when being
programmed by a PROM writer made by Data I/O, Prolog, Takeda or Minato Electronics.
FUNCTION
(abbreviated MELPS 8 binary), created on the disk by the
•
Sorting capability to put files in address sequence
•
Executing computer is a MELCOM 70 minicomputer
program PROMs on PROM writers such as those made by
•
Implementation language:
FORTRAN IV (parts are
written in assembler language)
Data I/O, the Series 90 made by Pro-log Ltd., the T-310
made by Takeda Riken and the 1830 made by Minato
INPUT/OUTPUT MEDIA
Electronics (abbreviated elsewhere to Data I/O, Pro-log,
•
Takeda and Minato). This program also converts absolute
Converts MELPS 8 binary to hexadecimal paper tape.
Input:
cartridge disk
Output:
•
binary object programs into MELPS 8 hexadecimal format
and creates a paper tape with blocks of suitable size. The
paper tape (even-parity ASCII code)
Converts other hexadecimal paper tapes to MELPS 8
program can also convert paper tapes of Data I/O, Pro-log,
Takeda and Minato into MELPS 8 hexadecimal format and
compare the functions of each.
Paper-Tape Processing System For PROM Writers
HEXADECIMAL
OBJECT FOR TAKEDA
r----1.
l-----J ---1
HEXADECIMAL
OBJECT FOR MINA TO
r----1. ---1
l-----J :
HEXADECIMAL
OBJECT FOR
c:J
MELPS 8
HEXADECIMAL
OBJECT
Hf.XADECIMAL OBJECT
FOR TAKEDA
i
HEXADECIMAL OBJECT
FOR MINATO
___ c __ _
PROLOG AND DATA 1/0
HEXADECIMAL OBJECT FOR
PRO-LOG AND DATA 1/0
-------- CONVERSION FROM
PAPER TAPE
HEXADECIMAL OBJECT
FOR TAKEDA
MELPS 8 HEXADECIMAL
OBJECT
HEXADECIMAL OBJECT
FOR MINATO
HEXADECIMAL OBJECT FOR
PRO-LOG AND DATA 1/0
PROGRAM ORDERING INFORMATION
Program
Paper tape preparation program
for PROM writers
Program and software manuals Included
Program code number
GA1SP0100
Paper-Tape Preparation Program
for PROM Writers Manual
• MITSUBISHI
"'ELECTRIC
GAM-SROO-32A
14-55
MITSUBISHI MICROCOMPUTERS
MELPS 8/85 SOFTWARE
PAPER·TAPE GENERATION PROGRAM FOR PROM WRITERS
PAPER-TAPE PROCESSING SYSTEMS FOR PROM
WRITERS
of processing. Table 2 shows a summary of the comparison
The program provides for both conversion and comparison
programs and media that the program is capable of process-
of various object programs. Table 1 shows a summary of
the conversion processing indicating various combinations
are illustrated in Fig. 1.
processing indicating the various combinations of object
ing. Examples of all the object conversions listed in Table 1
of object programs and media that the program is capable
Table 1 Object conversions
-:::::,~'h
company's PROM writer
Pap€r tape block size
Hexadecimal paper tapes for PROM writers that
can be converted from MELPS binary (on disk)
Hexadecimal paper tapes for PROM writers that can
be converted Into MELPS 8 hexadecimal paper tape
Data I/O. Pro-log. Takeda
Conversion from eight blocks of Data I/O. Pro-log or
Takeda to one 2048-byte block
1024 bytes
MELPS 8 hexadecimal (for mask ROM). Data I/O.
Pro-log. Takeda. Minato
Conversion from one block of Data I/O. Pro-log.
Takeda or Minato to one 1024-byte block or two
blocks to 2048-byte block
2048 bytes
MELPS 8 hexadecimal. Takeda. Minato (for mask
ROM)
Conversion from one block Takeda. Minato to
2048-byte block
256 bytes
Table 2 Comparison processing of object paper tapes
~d
Comparison
Comparison oblect
MELPS 8 hexadecimal
Object
Media
MELPS 8 hexadecimal self comparison
ME LPS 8 absolute
hexadecimal
Comparison of MELPS 8 hexadecimal
with Mlnato
MELPS 8 absolute
hexadecimal
Media
Paper tape
e1024-b'{le block
e2048-byte block
Paper tape
e1024-byte block
e2048-byte block
Comparison of MELPS 8 hexadecimal
with Takeda
MELPS 8 absolute
hexadecimal
Paper tape
e1024-byte block
e2048-byte block
HexadeCimal for Takeda
Comparison of MELPS 8 hexadecimal
with Pro-log
MELPS 8 absolute
hexadecimal
Paper tape
e1024-byte block
e2048-byte block
Hexadecimal for Pro-log
Paper tape
eeight 256-byte blocks
etwo 1024-byte blocks
e2048-byte block
Comparison of MELPS 8 hexadecimal
with Data 1/0
MELPS 8 absolute
hexadecimal
Paper tape
e1024-byte block
e2048-byte block
Hexadecimal for Data 1/0
Paper tape
eeight 256-byte blocks
etwo 1024-byte blocks
e2048-byte block
Object
Paper tape
e1024-byte block
e2048-byte block
Paper tape
e1024-byte block
e2048-byte block
Paper tape
eeight 256-byte blocks
etwo 1024-byte blocks
e2048-byte block
MELPS 8 absolute
hexadecimal
Hexadecimal for Mlnato
Fig. 1 Medium conversion
CONVERSION FROM MELPS 8 BINARY (ON DISK)
e 256-BYTE BLOCKS
MELPS 8
BINARY
e 1024-BYTE BLOCKS
HEXADECIMAL
FOR DATA 1/0
PRO-LOG AND
TAKEDA
MELPS 8
BINARY
ooot]
OO0t] - OOOg
OFF
000
OFF
000
I
HEXADECIMAL
FOR DATA 1/0.
PRO-LOG, TAKEDA
AND MINATO
OOOg
3FF
000
3FF
-000
000
:
I
'
:
e 2048-BYTE BLOCKS
MELPS 8
HEXADECIMAL
MELPS 8
BINARY
ooot]
7FF
OOO~
I
:
000
3FF
OFF
000
_7FF
7FF
CONVERSION TO MELPS 8 HEXADECIMAL
e 256-BYTE BLOCKS
HEXADECIMAL
FOR DATA 1/0. PRO-LOG
AND TAKEDA
OOOill
OFF
000
OFF
:
000
I
OFF
14-56
e 1024-BYTE BLOCKS
MELPS 8
HEXADECIMAL
0000
E~OCKS
HEXADECIMAL
FOR DATA 1/0. PRO-LOG
TAKEDA AND MINATO
MELPS 8
HEXADECIMAL
'"'8'"'8MO""Q""O
3FF
000
3FF
7FF
e 2048-BYTE BLOCKS
3FF
OR
BLOCKS
_
3FF
TAKEDA
MINATO
MELPS 8
HEXADECIMAL
oooQ 0000
O~K
7FF
OR
• MITSUBISHI
.... ELECTRIC
7 FF
7FF
"
MITSUBISHI MICROCOMPUTERS
MELPS 8/85 SOFTWARE
SELF ASSEMBLER
DESCRIPTION
The MELPS 8/85 self assembler is a target program that
has been prepared for the development of application programs suitable to microcomputers using the MELPS 8/85
CPU and devices utilizing microprocessors.
•
•
Character constants
Octal, decimal, and hexadecimal numbers
•
The mnemonic codes of the machine instructions are the
same as those for the MELPS 8/85 cross assembler and
Intel's.
The PTS-A version of the MELPS 8/85 self assembler
requires fewer control commands than the cross assem-
INPUT/OUTPUT MEDIA
bler, and is capable of assembly, even without a host mini-
•
Source input:
computer, using an inexpensive debug machine.
The coding for this self assembler is easy, since input
•
•
data in the MELPS 8/85 self assembler language (Bversion) may be handled in free format.
Control command input: Keyboard
Object output:
Paper tape or debug machine
memory
•
Program supply media:
FEATURES
Paper tape (object)
FUNCTION
Of the Self Assembler
•
May be used on either 3-pass or 2-pass system
•
•
Source input may be in free format
Source input may be prepared either with paper tape or
•
The number of symbols can be increased in accordance
with memory capacity expansion
•
The execution computer is the MELCS 8/1 and MELCS
from the keyboard
85/1 debug machine (with memory more than 8K-bytes
and using the BOM-PTS monitor)
•
Keyboard or paper tape
The MELPS 8/85 assembler language (A-version) is used
as the implementation language
This self assembler converts source programs written in the
MELPS 8/85 self assembly language (B-version) into absolute
objects in the MELPS 8 binary format utilizing the debug
machine.
This self assembler can handle 4 control commands for
input device assignment, object output device assignment,
assembly execution control, and end designation control,
and can use both machine and pseudo instructions. The
machine instructions, in one-to-one correspondence with
machine language, consist of 80 basic instructions (the same
as the MELPS 8/85 cross assembler) that are to be subject to object conversion. The pseudo instructions are
Of the Self Assembler Language
divided into assembly control, data setting and storage
•
8 pseudo instructions
allocation instructions, and consist of eight instructions.
•
Algebraic expressions
SELF ASSEMBLER PROGRAM PROCESSING SYSTEM
C--SO-UR-CE-P-RO-GRA-M---
,..--_-L._-..,
ASSEMBLE LISTING AND
ERROR LISTING
MELPS 8 BINARY FORMAT
PROGRAM ORDERING INFORMATION
Program name
MELPS 8/85 self assembler
Ordering number
GA2AS0100
Program and software manuals ;ncluded
Self Assembly Language Manual (B-verslon)
GAM-SROO-25A
Self Assembler Manual (PTS-A-version)
GAM-SROO-19A
Self Assembler OperatJng Manual (PTS-A-version)
GAM-SROO-24A
MANUALS
Manual number
Manual name
MELPS 8 Editor Manual (PTS-A-version)
GAM-SROO-26A
MELPS 8 Editor Operating Manual (PTS-A-version)
GAM-SROO-27A
MELPS 8 Basic Operating Moniter (BOM-B) Manual
GAM-SROO-23A
MELPS 8 Basic Operating Monitor (BOM-PTS) Manual
GAM-SROO-18A
MELPS 8 Hardware Manual
GAM-HROO-01A
• MITSUBISHI
"'ELECTRIC
14-57
MITSUBISHI MICROCOMPUTERS
MELPS 8/85 SOFTWARE
SELF ASSEMBLER
This self assembler facilitates assembly by the use of the
verted to their corresponding machine codes and then in-
control commands shown in Table 1. The assembly consists
of the creation of the symbol table in pass 1, where source
serted in the object program. The mnemonic and all the
programs are read from the keyboard or paper tapes, the
creation of the assembly list in pass 2, where source pro-
other instructions are the same as for the MELPS 8/85 cross
assembler; for these please refer to the Cross Assembler
Manual.
grams are read from paper tapes and each instruction is con-
2. Pseudo Instructions
verted into machine language, and the output of absolute
The pesudo instructions that this self assembler accepts
objects in pass 3.
consist of ORG, NAM, PAUS, and END as assembler-control instructions; EQU, DB, and DW as data-setting instructions; and DS as storage allocation instruction. These
SELF ASSEMBLER OBJECT LANGUAGE
The cross assembler is composed of many object modules,
and each module is composed of a name part, a symbolic
part, a text part and a final part. This self assembler outputs
only the text part and the final part in response to the
object output control command.
ASSEMBLY LANGUAGE FUNCTIONS
The assembly language that this self assembler accepts
consists of the following machine instructions and pseudo
instructions.
instructions are summarized in Table 2.
3. Language Format
The Self Assembler Language Manual (B-version) is applicable to the language formats for the MELPS 8/85 self assembler; these are equivalent to those for the MELPS 8/85 cross
assembler, with some restrictions, and may be handled in
a similar manner. In the source program, a statement
starts with CR (carriage return) and ends with CR (carriage
return), consisting of label, command, operand, comment,
and identification fields.
1 . Machine Instructions
There are 80 basic machine instructions. These are conTable 1 List of control commands for the self assembler
MnemoniC
Functional classification
Input device assignment command
/ / / S P u (:
Object output device assignment
11/ OB u
11/ OP
u
FuncllOn
Input device assignment for pass 1
5T . Paper tape reader
SK : Keyboard
~ J.
(~~J.
Object output device assignment
ST Paper tape punch
DM. Debug machine memory
l~ ~] J
Assembly execution start assignment and control of source listing
AN
None
Assembly execullOn control
[
None
CD
and of object output
(1 ) Listing control
.
®
LS
Source lisling needed
LC
Commentless condensed IISling needed
LE
None
End deSignation control command
CD
Llsling control
®
Object output control
(2) Object output control
AN Output of absolute objects without symbol parts
None : No object output
II/ED.
End of assembly execution designated
Table 2 List of pseudo instructions
~
Functional
classification
Assembly-control
instructions
Data-setting instructions
Storage allocation
Irlstructlon
Instruction
mnemonic
symbol
Table 3 Labels, characters, numerals, and expressions
Name of instruction
Item
Sort
Label expression
ORG
Program counter setting
NAM
PAUS
END
EQU
DB
OW
Program name declaration
OS
Listing of error statements only needed
Source listing unnecessary
Initial characters for labels
Label
ones. for labels
Number of label characters
Assemble stop
End declaration
Value symbol setting
Data setting
Character
constant
A
1 byte
AS
2 bytes
A""S3bytes
Address setting
Storage allocation
~~ except the initial
Numeral
Expression
• MITSUBISHI
.... ELECTRIC
~A~~B~
n 0
Decimal number
n
Hexadecimal number
n
H
Add
+
Subtract
-
Divide
14-58
~A ~
~AB ~
Octal number
Multiply
Others
Symbol
L:
A -Z, @, ?
A -Z, @, ?, 0-9
From one to five(e.g LAB L 1 :)
Program counter
Operational order
*
/
$
From left to right
MITSUBISHI MICROCOMPUTERS
MELPS 8/85 SOFTWARE
SELF ASSEMBLER
A comment is preceded by a semicolon (;). Since the
3. Operand field
format is free, any column may be used if the delimiters are
Operands 1 and 2, the first and second operands of the
properly placed. (Note that the printout for columns 35""72
instruction parameters, may be written. When both the
and 81 and over are neglected.)
operands 1 and 2 are necessary, a comma as a delimi-
Table 3 summarizes the labels, characters, numerals,
ter should be written.
and expressions, etc.
Octal, decimal, and hexadecimal numbers may be
used as numerals, formats such as ~A~, ~AB~ , ~A~ ~B~
1. Label field
One""-'five characters may be used. Only A""Z, @, and?
etc. as character constants, expressions combined with
operators (+, -, *,
may be used as the first character and A""Z, @, ?, and
0""9 may be used as the remaining characters. A colon is
to be added at the end of the character string.
Label example
L 1: M OV
/ ) as
expressions, and $ as the pro-
gram counter.
4. Comment field
A, B
A line preceded by a semicolon (;) and a character string
following a semicolon (;) placed attheendof a command
LABL5:
or at an arbitrary position along a line are regarded as
comments.
Comment examples; THIS LINE IS COMMENT
@ABCD:
A123?:
?AB01 :
;COMMENT
2. Instruction field
Instruction mnemonic codes are placed in this field.
LI: MOV
A, B;COMMENT;ABC
Machine instructions are formed with the same codes
as in the MELPS 8/85 cross assembler.
5. Identification field
The pseudo
The field is composed of the characters in columns 73""-'
instructions available are, ORG, NAM, PAUS, and END
as assembler-control instructions; EQU, DB, and DWas
data-setting instructions; and DS as storage allocation
80 or from 1 to 8 characters following!. This field is
placed at the end of one statement and may be omitted.
instruction.
Fig. 1 Source program format
Label field
Instruction field
Operand field
_ _ _.......' CD'----;' ®
Label
I: u I
Instruction
I
LAB1: u MYI
u MY I
LJ
LJ
LJ
First operand
A
A
CD
CD
u
u
l
Item
u, u ABC
u, u 1 0
Comment field
CD+CD
u
r-----.,' CD
Item
u
u+u
XYZ
u;A=10
Iu ; I
LJ
u
Identification field
\ CD I
I
Comment
lui
,
Identification
A=B
uSALOOl
SAL002
CD Spaces that may be omitted
® One. or more spaces needed
Note : Mark LJ denotes space.
Fig. 2 Assemble list format
I
i L ':"~~"M 1'" ~~~F~-al------s-o-u-rce-sta-J-m-e-nt-f-ro-m-t-he-------.51 5i=l~-01-um-n-S-7-1_-80-Of-th': :;:O
(2 to 6 characters)
first column
Memory address in hexadecimal (4 digits)
L..-_ _ _ _
Statement number in decimal (4 digits)
•
MITSUBISHI
"'£L£CTRIC
I
source statement
MITSUBISHI MICROCOMPUTERS
MELPS 8/85 SOFTWARE
SELF ASSEMBLER
FORMATS FOR SOURCE PROGRAM AND
ASSEMBLE LIST
ASSEMBLE EXAMPLES
The coding of source programs is in free format like that
Fig. 4 for paper-tape input and in Fig. 5 for keyboard input.
Examples of execution of passes 1, 2, and 3 are given in
shown in Fig. 1.
The format of assemble lists is shown in Fig. 2 and an
ERROR MESSAGE FORMAT
Error messages are divided into two types: one for control
example of the list is given in Fig. 3.
commands and the other for assemble.
OBJECT TAPE FORMAT
Errors for control commands···
The object program which is generated in pass 3 is an
Errors for assemble"'?
L.J
*Q *
*X *
x: Error code
absolute object program in MELPS 8 binary format.
Fig. 3 Example of assemble list
1L....--....I4 6L..--...J9 11
,'---_---I,16 18
51 53
1-'_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- - ' ,
0001
0002
0003
0004
0005
0006
0007
OOOS
0009
0010
0011
0012
0013
0014
0015
0016
0017
001S
0019
0020
0021
0022
0023
0024
0025
0026
0027
002S
0029
0030
0031
0032
60
~,
SUB R OU TIN E (1)
*
*
0000
0002
0005
OOOS
L@OOl: MV I
OEOS
LXI
210000
110000
LXI
57
MOV
0009
OOOA
OOOB
OOOC
0000
0010
7A
L@002: MOV
OF
RRC
57
MOV
7C
MOV
021100
JNC
SO
ADD
0011
0012
0013
0014
0015
1F
67
70
1F
6F
0016
0017
0019
001A
0010
001E
79
0601
4F
C20900
7A
C9
0000
L@003: RAR
MOV
MOV
RAR
MOV
MOV
SUI
MOV
J NZ
MOV
RET
END
Fig. 4 Paper tape input
........... MUL TAT - 02000
AT-02020
(A) ........ MULT AT-02030
(B) ........ MULT AT-02040
RESULT (H) (L) .... PROD AT-02060
AT-02070
C, S
AT-020S0
H, 0
AT-02090
0, 0
AT-02100
0, A
AT-02110
AT-02120
A, 0
AT-02130
RI G AT-02140
0, A
AT-02150
A, H
AT-02160
AT-02170
L@003
(A) AT-021S0
B ;
AT-02190
R-S AT-02200
H, A
AT-02210
A, L
(A) AT-02220
R-S AT-02230
L, A
AT-02240
AT-02250
A, C
(A) AT-02260
(A) AT-02270
1
AT-022S0
C, A
AT-02290
L@002
A, 0
AT-02300
AT-02310
AT-02320
AT-03330
DATA
Fig. 5 Keybord input
Input from a tape reader
:///sP.
: / / /OB .
:///OP LS,AN.
P1 Sf ART
P 1 END
: / / / GO .
Continue pass 2
P 2 S TAR T Assemble listing start
0001
NAM EXAMP1
ORG
1000
0002 03ES
LOOl :MOV A,C
0003 03ES 79
0004 03E9 3E02
L002:MVI A,2
0005 03EB 4S
L003:MOY C,B
NOP
0006 03EC 00
END
0007 0000
P2 END
:///GO.
P3 START
14-60
L..'_ _ _
: / / / SP
S K ..•....•..
Input from a keyboard
: / / /OB .
: / / /OP LS, AN.
P1 START
NAM EXAMPl
ORG
1000
LO 01 : MOV A, C
L002:MVI A,2
L003:MOY C,B
NOP
END
P 1 END
:///GO.
P 2 S TAR T ........... Assemble listing start
0001
NAM EXAMPl
0002 03ES
ORG
1000
0003 03ES 79
L001:MOV A,C
0004 03E9 3E02
L002:MVI A,2
0005 03EB 4S
L003:MOY C,B
0006 03EC 00
NOP
0007 0000
END
P2 END
:///GO.
P3 START
• MITSUBISHI
;"'ELECTRIC
MITSUBISHI MICROCOMPUTERS
MELPS SOFTWARE
EDI~'OOR
DESCRIPTION
The MELPS editor program was developed to make
modifications of programs at the source language level
easy.
This design feature also makes it a useful tool in
MELCS 85/1 (memory 8K-bytes, monitor BOM-PTS)
• The programming language is MELPS assembler (A
version) .
INPUTIOUTPUT MEDIA
program development for microcomputers and microprocessors.
•
Programs for editing:
FEATURES
•
Control commands input:
Keyboard
•
•
Output after editing:
Printer or paper tape
Fifteen easy-to-use control commands
Keyboard or paper tape
•
Convenient loading from the keyboard or by paper tape
FUNCTION
•
Variable work area to match the application requirements
The MELPS editor loads text from paper tape or key-
•
Versatile input control
edited.
•
Easy-to-use buffer-pointer control
through the keyboard.
•
Flexible output control
on paper tape, and at the same time the copy can be
printed.
hoard into the work area where the text is modified and
Control commands for the editor are entered
The edited text is punched out
•
Data editing made easy
•
String command is possible
•
The repetition function of commands shortens input
commands
functions as shown in Table 1. There are a total of 15
easy-to-use control commands.
One instruction can
•
•
Editor complete control
The command format is similar to that used in the
ME LCOM 70 editor
delete, insert or replace from one character to a number
•
Debugging and execution are done on a MELCS 8/1 and
MELPS Editor
Processing System
The powerful control commands are divided into five
of lines. This is facilitated by the flexible control provided
for the buffer pointer. The edited results can be punched
on paper tape and printed simultaneously.
CONTROL COMMANDS
SOURCE PROGRAM TO BE EDITED
MELPS EDITOR PROGRAM
OUTPUT LISTING AFTER EDITING
PROGRAM ORDERING INFORMATION
Program
Ordering number
Program and software manuals included
Source Program
MELPS 8 Editor
GA2SP0103
MELPS Editor Manual IPTS-A version)
GAM-SROO-26A
MELPS Editor Operating Manual IPTS-A version)
GAM-SROO-27A
MANUALS
Manual name
Manual number
MELPS 8 Self Assembler Language Manual IB-verSlon)
GAM-SROO-25A
MELPS 8
GAM-SROO-19A
Self Assembler Manual IPTS-A version)
MELPS 8 Self Assembler Operating Manual IPTS-A version)
GAM-SROO-24A
MELPS 8 BaSIC Operating Monitor IBOM-B) Manual
GAM-SROO-23A
MELPS 8
GAM-SROO-18A
Basic Operating Monitor IBOM-PTS) Manual
GAM-HROO-01A
MELPS 8 Hardware Manual
•
MITSUBISHI
.... ELECTRIC
14-1=;1
MITSUBISHI MICROCOMPUTERS
MELPS SOFTWARE
EDITOR
Fig. 1 General format of input commands
FUNCTIONAL OPERATIONS
The MELPS editor is designed to increase the effectiveness
///c=J$
of modifying, editing, and debugging programs. There
c=J$$
®
are five groups of control functions: input control, bufferpointer control, output control, data-editing control and
editor end control.
There are a total of fifteen control
CD
This IS an Input command message Editor program IS ready to accept
a command
commands listed in Table 1. An explanation of the action
®@
Editor control commands and necessary arguments
of each control command is also given in Table 1.
@
@
End of command delimiter (two ESC)
The
general format of a control command for input is shown
Delimiter (one ESC)
(ESC = Escape)
in Fig. 1.
1. String commands
The control commands can be used independent-
Fig. 2 Typical editor command
ly or they can be combined into a string as shown in
An editor command
the example that follows.
I//BP$RP1 $1 O$2CP$DL$BP$FPPOP
cv
IIIBP$STW$2CP$3DL$RPA$B$$
2. Command repetition
The format for repetition of a command is as
@
D$IN ;C$$
@
Before the above command is
executed and the modifications
are made
After the above command
IS executed and the
modifications are made
CD
follows:
n
PUSH H
will be repeated n times. Repetition command nesting of < and> is limited to eight levels.
An example of command formats and how they can be
stringed follows.
The contents of the work area before
and after execution are also shown in Fig. 2.
CD
®
Not modifYing
@
Delete one line (MOV E.A)
Replace 1 with 10
®
Not modifying
@
Search the string for the data (POP D) and set the buffer
pointer to the end location of the data
Insert the assigned string eC) in the work area starting at
the location indicated by the buffer pointer
Table 1 Editor control commands and an explanation of their actions
Control function
Input control
Control command
Print typewriter
TW
Print n lines.
line punch
PN
PP
PS
DC
FP
RP
OL
IN
EN
Punch n lines from the, first line of the work area
Buffer-pointer character setting
Buffer-pointer control
Buffer-pointer line setting
Output control
Punch work area
Punch sprocket holes
Delete character
Find and buffer-pointer setting
Replace
Delete line
Insert
Editor end control
14-62
Action
Buffer -pointer end setting
Buffer -pointer initial setting
Data-editing control
Mnemonic
LO
BP
CP
LP
EP
Source load
End
Assign the input device for text load and load text
Set the buffer pointer to the first address of the work area
Move the buffer pointer n characters.
Move the buffer pointer n lines.
Move the buffer pointer to the end of the work area.
Punch all the contents of the work area
Punch sprocket holes for n bytes
Delete n characters.
Search the string Tor the data and set the buffer pointer to the end
location of the data.
Locate data to be replaced and replace with the new data
Delete n lines
Insert the assigned string in the work area starting at the location
indicated blithe buffer pointer
End of editor processing
• MITSUBISHI
"'ELECTRIC
MITSUBISHI MICROCOMPUTERS
MELPS 8 BOM-PTS
BASIC OPERATING MONITOR-PAPER-TAPE SYSTEM
DESCRIPTION
Starting BOM-PTS Execution
The BOM-PTS basic operating monitor was developed for
When the BOM start switch on the panel of the debugging
microcomputers that use the M5L 8080A 8-bit parallel
machine MELCS 8/1 is turned on, the following message
CPU.
It controls execution and debugging of the user's
program. The BOM-PTS has a program capacity of 7.5Kbytes and drives the system typewriter (Casio Typuter,
Model 500 or 501) as its I/O unit.
is printed out. After the printout, monitor commands can
be entered.
BOM-PTS AOO 'READY'
//
Hardware Limitations
FEATURES
1. Memory Configuration
•
Has 3 macro instructions and 22 monitor commands
Memory locations in t:,e ROM are:
•
Provides trace, snapshot, and address halt commands
for effective program development and debugging
E000 16 ""FCF F 16
•
Has pseudo I/O and PROM write functions
area are required:
I n addition to the ROM, the following 78 bytes of RAM
FOOO I6 ""EDFF I6
FUNCTION
2. I nput/Output Device Addresses
The BOM-PTS 22 monitor commands and 3 macro instruc-
PTR, for keyboard input: 7B 16 (IN
tions provide the following functions:
PTP, for printout:
7B 16 (OUT 78#)
Status input:
7B 16 (IN
1. Program execution control
2. Program loading
78#)
78#)
The structure of the status bits is as follows:
3. Memory punching
6
4. Program debugging (trace, snapshot, and halt commands)
5. I/O control and pseudo I/O processing
6. Memory and register data display, and data alteration
4
OBIT
L21ZI/1ZVVI Yo I Yo I
ITrue when bit IS 1)
7. PROM writing function
L
~ INPUT BUSY
OUTPUT BUSY
FLOWCHART
OPERATOR MODE
RETURN PROCESSING
PROGRAM ORDERING INFORMATION
Program name
MELPS 8 baSIC operatlmg mOnitor
(SOM-PTS)
Ordenng number
GA20S0100
Program and software manuals Included
Source program. Object program
BaSIC Operating Monitor Manual IBOM-PTS)
GAM-SROO-18A
MANUALS
Manual name
Manual number
MELPS 8 BaSIC Operating Monitor Manual IBOM-B version)
GAM-SROO-23A
MELPS 8/85 Self-Assembler Language Manual IB version)
GAM-SROO-25A
MELPS 8/85 Self-Assembler Manual IPTS-A version;
GAM-SROO-19A
MELPS 8/85 Self-Assembler Operating Manual IPTS-A version)
GAM-SROO-24A
MELPS 8 Hardware Manual
GAM-HROO-01A
• MITSUBISHI
"'ELECTRIC
14-63
MITSUBISHI MICROCOMPUTERS
MELPS 8 BOM-PTS
BASIC OPERATING MONITOR-PAPER·TAPE SYSTEM
MONITOR COMMANDS AND MACRO INSTRUCTIONS FOR BOM-PTS
//G
Start program
G
-
R
Restart program
/ /R(;R LF
User pseudo I/O processing
/ /Uparal14PR LF
MELPS 8 binary loader
/ /LMpara1'4).para214)()R para31zpR LF
Dump memory data. MELPS 8 binary test
portion (to paper tape punch)
/ /DMpara111). para2(4). para3'4pR LF
Dump MELPS 8 binary end portion (to paper
tape punch)
/ /DMparp111) [para414iJ OR LF
OM
PR
Printout register data in hexadecimal form
/ /PROR LF
PM
Printout memory data in hexadecimal form
/ /PMparal'4). para214)OR LF
PA
Reverse assembler
/ /PApara 1,4). para214). para311iOR LF
MR
MM
Alter the register data
Alter the memory data
/ /MRcR LF
MC
Complement the memory data
/ /MCparal(4). para2(4)OR LF
MS
Set up constants in memory
/ /MSparal(4). para2(4). para3lz)CR LF
MT
Transfer memory data in blocks
/ /MTparal(4). para214), para3'4)CR LF
Enable machine interrupt
/ /1 para I(1)CR LF
Print debug table
Clear debug table
/ /PTCR LF
/ /C CR LF
Prepare halt and debug table
//Hpara1I,). para214), para3'4)CR LF
Cancel halt and debug table
/ /Hparal(I),para211)
[, ... para9 1111 CR LF
Prepare snapshot and debug table
/ /S parall1), para2(4), para316), para4(4),
paraS(4)[.para611)]CR LF
Cancel snapshot and debug table
/ /Sparall1),para211) [,
Prepare trace and debug table
/ /Tpara 1 (1), para2(4). para3(4), para4(4),
paraS'4) ~ ,para611), ,para7(1)]] OR LF
Cancel trace and debug table
/ /TparalI11,para2(1)!.,
Write PROM
/ /FP para 1(4), para2(4), para31zpR LF
Transfer writing address
Compare PROM data with main memory data
End declaration of program
Temporary stop of program execution
I/O control
/ /FTparaI(4)CRLF
/ /lliaral(4)CR LF
I
PT
C
Macro
instruction
Note 1 : paran (m): n = the nth parameter (input by the operator
or printout by the monitor) in a command. and is a
hexadecimal parameter l-m digits. If the number of
digits in the parameter exceeds m. only the first m digits
are valid
2: -'(underlining); Represents and input by the operator.
[
1 (blocking); Represents input by the operator that
3
can be omitted.
4: #;
Indicates
language.
14-64
hexadecimal
number
in the
assembler
Starting address
End address
Starting address
End address
No reverse assembly is done to
the operand when para 3111= 1
para 1(4):
parp 1(4):
para214):
paral(4):
para214) :
para3IZ):
para 114):
para2(4):
para314):
Starting address
Starting address
End address
Starting address
End address
The constant
Starting address
End address rwhich transfer is mad
Starting address of the memory to
paralll1: Enables machine interrupt when
para 1111= 1. and disables interrupt when para 1 (1) =1
-
S
FT
FC
EXIT
PAUSE
EXIO
para 1(4):
para2(4):
para 1(4):
para2(4):
para3111:
-
H
FP
para1 (4): First address of the user pseudo
I/O processing routine
paral(4): ROM start address(when relocatable)
para2(4): RAM start address(when relocatable)
para3(4): LE(Load End indicating key word)
para1111: para1(1)=T
para2(4): Start address
para3(4): End address
para111): para1(1)=E
para4 (4): Starting address
-
/ /MMl:!arall4lCR LF
T
Parameter
para 114): Starting address
para2(4): Altered starting address
paralI4}~[para 214Jl OR LF
U
LM
Command
Command designation. parameter input format.
and calling sequence
Function
Name
. para9 I1Jl OR LF
,paraS(1)] OR LF
paral'1): parall1)=S
para214): Halt address
para314): Number of passes before halt IS actl ve
parall1): para1(1)=D
para2 (1)- para9 (1) : 0 -7 (table number).
W (whole table)
paralll1: paral(1)=S
para214): Snapshot executing address
para3(6): Snapshot symbol
para4(4): Memory data display starting add res
paraSI4): Memory data display end address
para6(1): para6(1)=R
paral(1): para1(1)=D
para2(1)- para9 (1): 0 -7 (table number) .
W (whole table)
parall1;: para1(1)=S
para2(4): Trace region starting address
para3(4): Trace region end address
para4(4): Memory data display starting addres
paraS(4): Memory data display end address
para6111: para 6(1)=R specifies register
data display para 7(11=8 specifies to trace only while the debug
para7 (1) instruction is in execution
paral(1): para'I(1)=D
para2111-paraS(1): 0-3 (table number).
W (whole table)
paraI(4):
para2(4):
para3(2):
paraI(4):
para 1(4):
Starting address
End address
PROM writing address
Starting address
Starting address
CALL F015#
CALL F012#
DCB1
CALL FOOC #---- Execution of the EXIO macro Instruction
DADR DCB1 -.----- Starting address of the data control block
(DCB)
DEI:
10D- --- Designation of 1(0 operation; PTR (lOD=52#). PTP (=50#).
keyboard (=4B#). printout (=44#)
DADR DA ---- Setup of the 1(0 data-storing memory starting address
DADR DL ----- Setup of the 1(0 data-storing memory length
DA
I
1(0 datastoring
memory
• MITSUBISHI
.... ELECTRIC
I
I
DLt""
MITSUBISHI MICROCOMPUTERS
MELPS 8 BOM-B
BASIC OPERATING MONITOR-BASIC SYSTEM
DESCRIPTION
Starting 80M-8 Program Execution
The MELPS 8 BOM-B basic operating monitor was de-
When program execution is started at address 6800 16 , the
following message is printed out.
veloped
for microcomputers that use the M5L8080A
8-bit parallel CPU. It controls execution and debugging of
VMELPS 8 BOM-B A01
the user's program. It is contained in 2K-bytes of memory
//
and drives the system typewriter (Casio Typuter Model
After the printout, monitor commands can be entered.
Hardware Limitations
500) as its I/O unit.
1. Memory Configuration
Memory locations in the ROM are:
FEATURES
•
Available as a standard mask ROM (M58731-001 S)
It can also be programmed into a ROM for a microcomputer configuration that incorporates program de-
6800 16 ""6FFF I6
I n addition to the ROM, the following 78 bytes of
RAM area are required:
3F80 16 ""3FCD 16
bugging functions.
2. I nput/Output Device Addresses
•
Has 3 macro instructions and 9 monitor commands
•
Allows addition of user's monitor commands
PTR, for keyboard input: 7B I6 (In
•
Cannot be destroyed by a user's program
PTP, for printout:
7B I6 (OUT 78#)
Status input:
7B I6 (IN
78#)
78#)
The structure of the status bits is as follows:
FUNCTION
The 9 monitor commands and 3 macro instructions provide
4
2
0 BIT
0/1/1/1/121 Yo IYo I
the following functions:
1. Program execution control
(True whe'l bit
IS
1)
2. Program loading
L
~ INPUT BUSY
OUTPUT BUSY
3. Memory punching
4. Program debugging
5. I/O control
FLOWCHART
OPERATOR MODE
RETURN PROCESSING
PROGRAM ORDERING INFORMATION
Program name
MELPS 8 basic operating monitor
Ordering number
GA20S0101
(BaM-B)
Program a~d software manuals included
Source program. Object program
Basic Operating Monitor Manual (BOM-B version)
GAM-SROO-23A
MANUALS
Manual name
Manual number
MELPS 8 Basic Operating Monitor Manual (BOM-B version)
GAM-SROO-18A
MELPS 8/85 Self-Assembler Language Manual (B version)
GAM-SROO-25A
MELPS 8/85 Self-Assembler Manual (PTS-A version)
GAM-SROO-19A
MELPS 8/85 Self-Assembler Operating Manual (PTS-A version)
GAM-SROO-24A
MELPS 8 Hardware Manual
GAM-HROO-01A
• MITSUBISHI
"ELECTRIC
14-65
MITSUBISHI MICROCOMPUTERS
MELPS 8 BOM-B
BASIC OPERATING MONITOR-BASIC SYSTEM
Monitor commands and macro instructions for BOM-B.
Name
Commands
//G
Change start address
R
Restart of program
/ /RCR LF
L
MELPS 8 binary loader
/ /
H
MELPS 8 hexadecimal loader
//HCRLF
T
Punch MELPS 8 binary text block of the memory
data
/ / T para 1(4),para2(4) CR LF
E
Punch MELPS 8 binary end block
/ / E [para 1(4) J CR LF
P
Print hexadecimal test block of the memory data
/ / P para 1 (4), para2(4) CR LF
S
Substitute memory
//S
M
r~:::;;a~nd
PAUSE
EXIO
para«4) '-' ~ CR LF
modify register data
In
hexadecimal
Parameter
para 1 (4): Start address
G
EXIT
Macro
instruction
Command designation and parameter input
format or calling sequence
Function
para 2(4): Change start address
-
L CR LF
para 1 (4): First address
para 2(4): End address
para 1 (4): Start address
:para 1 (4): First address
para2(4): End address
~ara1(4)CR LF
para 1 (4): Change address
--
//MCRLF
End of program
CALL
6806
Pause program execution
CALL
6803
:1*
:1*
CALL
6 EBC
:1*---------- Execute EXIO macro instruction
DR
DCB1
I
Input/output control
Note 1 : para n (m): This designation shows the nth parameter in a
command (operator input or monitor printout). and also shows
it to be a hexadecimal parameter (0. 1. 2. 3. 4. 5. 6. 7. 8. 9. A.
B. C. D. E. F) of which the significant digits are 1-m. If the
length exceeds m. the least significant digits are valid.
2 : _(underline); Indicates input by an operator.
3 . [ 1 (blocking); Indicates input by an operator that can be
omitted.
4: #; Indicates a hexadecimal number in assembler language.
DAi
DCB1
0D
DEF
I
DADR
DA--"
DADR
D L --
It is feasible to implement new monitor commands, which
--- I/O operation designation; PTA (100=52#). PTP
(=50#). keyboard (=4B#). printout (=44#)
-<'- Set up the first address of I/O data area
'- Set up the data length for I/O data
DA
I/O datastoring
memory
HOW TO IMPLEMENT USER'S OWN MONITOR
COMMANDS
----------- First address of data control block
(DCB)
DLbyte
PROCESS FLOW OF USER'S MONITOR
COMMANDS
SYMBOL(3FC716)
are prepared by a user for his own need, by correcting four
4B16
bytes (3FC7 16 ....... 3FCA 16 ) of the record in the RAM. The
C316
user's monitor commands are then added as follows:
1. Set the data in "4B 16 " to SYMBOL.
2.
Set the data in "C3 16 " to SYMBOL
LOWER HALF ADDRESS OF THE USER'S MONITOR
COMMAND PROCESSING ROUTINE (YCR)
+ 1.
3. Set the starting address of the user's monitor command
processing routine (YCR) low-order into SYMBOL
and high-order into SYMBOL
UPPER HALF ADDRESS OF THE USER'S MONITOR
COMMAND PROCESSING ROUTINE (TCR)
+2
+ 3.
4. Then a symbol parameter analysis routine and command
processing routine are prepared as required for the user's
command.
5.
Command symbols used for the user's monitor com-
USER'S MONITOR COMMAND SYMBOL
PARAMETER ANALYSIS ROUTINE
(YCCPR)
.
mands should not be identical with any of the 9 command symbols used in BOM-B.
6. Both
command
symbol
and
parameter
errors
ADDRESS 68F916
(ERROR PROCESSING ROUTINE OF BOM-B)
are
checked in the YCR, and a jump is executed to address
68F916 , where the error processing routine of the BOMB is residing, when an error is found_
(?)
COMMAND PROCESS ROUTINE OF
USER'S OWN COMMANDS
(YCCR)
A question mark
will be printed out in case an error is found.
7. The last step of the YCR must be a jumped to address
6901 16 ,
where
the
monitor
command
termination
ADDRESS 690116
(MONITOR COMMAND TERMINATION PROCESSING
ROUTINE OF BOM-B
processing routine is stored.
14-66
• MITSUBISHI
"ELECTRIC
APPLICATIONS
MITSUBISHI LSls
MEMORY DEVELOPMENT APPROACHES
1. LARGE-SCALE SEMICONDUCTOR MEMORY
DEVELOPMENT APPROACHES
Introduction
The IC age which began in 1965 progressed into the 1970's
to see the beginning of a full-swing push towards LSI and in
1978 to the advent of VLSI, the 64K-bit RAM. Going into
the 1980's, the 64K-bit RAM is being used practically in
systems, and in February 1980 two announcements of
256K-bit RAM development in Japan were made at the
International Solid State Circuit Conference (ISSCC) held
at San Francisco. The VLSI Joint Research Laboratory has
pointed out the possibility of megabit memories, a development which may materialize in the form of a 1M-bit RAM
by the mid 80's.
The ever-increasing level of integration in MOS memory
devices has been supported by three areas of advancements.
• Circuit engineering advancements
• Process accuracy and micro-process advancements
• Increase in chip size
Using the ISSCC report material as a basis we will examine
some practical approaches to the development of megabit
memory devices and some of the problems involved in this
effort.
Approaches to Megabit Memory Development
Table 1.1 summarizes some typical approaches that have
been proposed for the development of megabit memory. As
is clear from this outline, areas for potential study include
improvements in cell structure and development of
methods to overcome the presence of failed bits in
large-scale memories as well as the obvious aim of development of smaller and smaller memory cells.
Table 1.1 Approaches to Megabit Memory Development
Prototype resu Its
Approach
Description
Capacity (bits)
Micro·process
80
2
NTT
80
2
Joint Research
Laboratory
80
2
Same as above, 3·layer polysilicon
NS
79
2
25.2mm2
Same as above, VMOS, L;;;' 4J.1m
Siemens
79
2
30mm 2
MOS 1 transistor, 1 capacitor bipolar configuration, 8K·word x 8 bits
IBM
80
2
Masked PROM using the full wafer
NTT
80
2
2
4.8x 8.6mm
Single 5V operation 1 transistor and 1 CMOS to form the cells. L = 1.5J.1m
5.8X5.8mm
Same as above Lefj=1.2J.1m, molybdenum gate with spare cell.
64k
(10X 10mm)
24mm 2
Same as above, QSA (quadruply self·aligned), L = 2J.1m
64k
64k
t-----===~:;_:....:.::=r.:..:.=:::.J
.
Vee (5V)
Vss (OV)
VBB (--5V)
8192-81T RAM
At
(64 ROWS x 128 COLUMNS)
Az
ADDRESS INPUTS
A3
128 SENSE AMPLIFIER
DOUT
DATA OUTPUT
A4
As
A6
• MITSUBISHI
"'ELECTRIC
15-9
MITSUBISHI LSls
16K·BIT DYNAMIC RAM
(MSK4116P,S)
FUNCTION
In addition to normal read, write, and read-modify-write
operations, the M5K4116P, S provide a number of other
functions, e.g., page-mode, RAS-only refresh, and delayedwrite. The input conditions for each are shown in Table 2.3
Table 2.3 I nput conditions for each mode
Output
Input
Operation
If you interchange address pins as shown in Fig. 2.3, you
can get a sequential location map for the 16,384 memory
bits.
RAS
CAS
R/W
D,N
Row
Re-
Column
address address
Remarks
°OUT fresh
Read
ACT
ACT
Write
ACT
ACT
Readmondlfywrite
ACT
ACT
NAC ONC APO APO VLO YES Page
mode
ACT VLO APO APO OPN YES IS Identical
except
refresh IS
ACT VLO APO APO VLO YES NO
ACT
NAC
ONC ONC APO ONC
OPN YES
ONC
ONC ONC ONC ONC
OPN
RAS-only
refresh
Standby
Note 2
I I
I
'SEOUENTIAL
ADD COUNTER
IOUTPUT
:u:
ROW DECODER
(
~~:~l
~
ROW
ADDRESS
64
.A 2
~r-------. A4
ROW ADDRESS
-
~r-
o
o
1
1
1
1
~f-------' A3
1
1
1
1
1
1
1
1
1
a
a
a
1 0
1
1
a
a
a
1 1
1
a
1
1
1
a
DATA
0
1 1
a
1
1
1
128 MEMORY SENSE AMPLIFIER CIRCUITS
[5]r--------~ AO -'
0001001
0001000
0001010
a a a 1 a 1 1
1 a a 1 a a 1
I5J----:=j[)--A6
COLUMN
ADDRESS
~
.A 1
~
A2
~
• A4
I5iI
· A3
~
.As
(5iJ
• Ao
0lP
64
COLUMN ADDRESS
8K
[
Fig. 2.3 Method for converting sequential address
15-10
'-'Oi="'"
a
a
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
8192-BIT MEMORY ARR,lI, Y
1
1
1
1
1
1
1
1
1
1
1
,1
1
1
a
a
a a
1 a
1
DATA
1
1
1
63
127
A6 a 1 1 a a 1 1 a a 1
aa1 1 aa 1 1 aa
A5 a a a a a a a a a 0
Ao 0 0 0 0 0 0 0 0 0 0
A4 0 0 0 0 0 0 0 0 1 1
A3 0 0 0 0 0 0 0 0 0 0
Az 0 0 0 0 1 1 1 1 0 0
A,
16256] MEMORY
16319
~~~A~~~~~~R
SENSE =-rAMP 16320
OF SEOUENTIAL,
-p
8K
ADD COUNTI:R
127.J,~_ _ _ _ _u 16383
63j,
64
16319
16256
8192,BIT MEMORY ARRAY
-.;::
1 1
~---------~, As
I5l
.,
000000164
00000000
0000010
0000011
1000001
'(7
NO
,
AzA3A4AoA5A, A6
SPEC ADDRESS PIN
I
NAC
ACT ,active NAC, non-active DNC: don't care VLD: valid APD, applied OPN, open
COLUMN
DECODER
16320
16383
1
Fig.2.4 M5K4116P, S memory map
• MITSUBISHI
~ELECTRIC
a
1 1
0
0
1
0
0
0
a
1
0
0
\\
1
\\
\\
1
a1
aa
1
aa1
aa
1
1
1
0
1
1
1
1
1
1
0
1 1
1 1 1 1
1 1 1 1
1\ 0 0 0 0
11 1 1
a1 1 1
1
1
1
1
0
1
1
1
1
0
aa1
aa
1 1
1
a
1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
0 1 1 1
1
t
1
1
1
MITSUBISHI LSls
16K-BIT DYNAMIC RAM
(MSK4116P,S)
N-CHANNEL DOUBLE-LAYER POLY SILICON GATE
MOS PROCESS
In order to fabricate the M5K4116P, S series, single tran-
memory capacitor because of the use of the double poly-
sistor memory cells and the N-channel double-layer poly-
silicon gate MOS process, so that the memory cell area is
silicon gate MOS process are used. There is no diffusion
area between switching transistor Q and the data-storage
reduced by 75% from that of the previous process.
Voo
WORD LINE
Si02~
p-SUBSTRA TE
\
\
\
\
\
WORD LINE
\
\
Voo
\
\
1ST
POLYSILICON
DATA LINE
\
\
\
\
Si0 2
Cs
p-SUBSTRATE
- - - - - - - - - - + - - - - - - + - - - - - - - - - - - - - - - W O R D LINE
L-----t
t-----O
Voo
Cs
DATA LINE
Fig. 2.5 Memory cell structure
• MITSUBISHI
..... ELECTRIC
15-11
MITSUBISHI LSls
16K-BIT DYNAMIC RAM
(MSK4116P,S)
FIELD DOPING (BORON)
PHOTO RESIST
~============================~~Si02
MASK 1
T
Deposit silicon nitride (Si 3N 4 ) on wafer and coat with
photo resist.
Define active area with MASK 1 and implant fields.
T
I
\
I
'-=t=-:1
==:.1
\..:-_-:
FIELD DOPING (p +)
Remove photo resist and grow field oxide using nitride as
mask.
1ST GATE POLYSILICON
1ST GATE OXIDE
Grow 1st gate oxide and deposit 1st polysilicon.
T
MASK 2
Define 1st polysilicon gate using MASK 2.
MASK 3
Define 2nd polysilicon gate and diffuse phosphorus W
dopant for source and drain.
r
T
Si02
(2ND GATE)
T
T
Deposit oxide and define aluminum contact with MASKs 4
MASKs 4, 5 and 5.
T
T
MASK 6
T....________p_-_ _ _ _ _ _ _....IT
Deposit aluminum and define bonding pad metal interconnect with MASK 6.
Deposit passivation oxide and define bonding pad openings
MASK 7
with MASK 7.
Fig. 2.6 Water manufacturing process
15-12
• MITSUBISHI
.... ELECTRIC
MITSUBISHI LSls
16K-BIT DYNAMIC RAM
(MSK4116P,S)
SUMMARY OF OPERATIONS
Table 2.4 Maximum multiplex time
Addressing
To select one of the 16384 memory cells in the M5K
4116P, S, the 14-bit address signal must be multiplexed illto 7 address signals, which are then latched into the on-chip
latch by two externally applied clock pulses. First, the
negative-going edge of the row-address-strobe pulse (RAS)
latches the 7 row address bits; next, the negative-going edge
of the column-address-strobe pulse (CAS) latches the 7
column-address bits. Timing of the RAS and CAS clocks
can be selected by either of the following two methods.
Type number
t Mux
td (RAS-CAS)
th(RAS-RA)
tSU(CA-CAS
M5K4116P, S-2
35 ns
50 ns
20 ns
-10 ns
M5K4116P, S-3
45 ns
65 ns
25 ns
-10 ns
M5K4116P, S-4
55 ns
85 ns
35 ns
-10ns
Note 3 : tT =5ns
2. The delay time td(RAS-CASI is set greater than the maximum value of the limits. In this case the internal inhibition of CAS has already been released, so that the
internal CAS control signals are controlled by the externally applied CAS, which also controls the access
time.
~-----~
ADDRESS
k-_____t~d~(R~A~S~-C~A2S~)__
tT~__~~tT
DELAY TIME MIN
MAX
td(RAS-CAS)
td (RAS-CAS)
Fig. 2.8 Read access time vs delay time
Fig. 2.7 Address multiplex
Data Input
1. The delay time from RAS to CAS td(RAS-CAS) is set
between the minimum and maximum values of the
limits. In this case, the internal CAS control signals are
inhibited until almost td( RAS-CAS) max ('gated CAS'
operation). The external CAS signal can be applied with
a margin not affecting the on-chip circuit operations
(e.g. access time), and the address inputs can easily be
changed from row address to column address. This interval is called the 'multiplex time'. Eq. 1 gives the multiplex time.
tMUX =td( RAS-CAS)-tT-th(RAS-RA)-tSU (CA-CAS)
.... Eq. 1
In the next conditions, the multiplex time (tMUX) is
maximized.
td( RAS-CAS)= max
th( RAS-RA)= min
tsu(CA-CAS)= min
Table 4 shows the maximum multiplex time in the case
where the access time is not greater than ta(RAS)MAX.
Data to be written ihto a selected cell is strobed by the
later of the two negative transitions R/W input and CAS
input. Thus, when the R/W input makes its negative transition prior to the CAS input (early write), the data input is
strobed by the CAS, and the negative transition of the CAS
is set as the reference point for setup and hold times. In
the read-write or read-modify-write cycles, however, when
the. R/W input makes its negative transition after the CAS,
the R/W negative transition is set as the reference point for
set-up and hold times.
Data Output Control
td(RAS-CAS)
ta (CAS)
HIGH IMPEDANCE
DOUT-----+~~~~~~~________~
ta(RAS)
Fig. 2.9 Read cycle
• MITSUBISHI
.... ELECTRIC
15--13
MITSUBISHI LSls
16K-BIT DYNAMIC RAM
(MSK4116P, S)
The output of the MSK4116P, S is in the high-impedance
state when the CAS is high. When the memory cycle in progress is a read, read-modify-write, or a delayed-write cycle,
3. Two Methods of Chip Selection
the data output will go from the high-impedance state to
the active condition, and the data in the selected cell will
high-impedance state. This means that the CAS and/or the
RAS can both be decoded for chip selection.
be read. This data output will have the same polarity as the
4. Extended-Page Boundary
Since the output is not latched, the CAS is not required to
maintain the output of selected chips in the matrix in a
input data. Once the output has entered the active condi-
By decoding CAS, the page boundary can be extended be-
tion, this condition will be maintained until the CAS goes
yond the 128 column locations on a single chip. I n this
case, the RAS must be appl ied to all devices.
high, irrespective of the condition of the RAS (to a maximum of 10~s).
The output will remain in the high-impedance state
throughout the entire cycle in an early-write cycle.
Page-Mode Operation
This operation allows for multiple-column addressing at the
same row address, and eliminates the power dissipation associated with the negative-going edge of the RAS because
once the row address has been strobed, the RAS is maintained. Also, the time required to strobe in the row address
for the second and subsequent cycles is eliminated, thereby
decreasing access and cycle times.
Refresh
Refreshing of the dynamic cell matrix is accomplished by
performing a memory operation at each of the 128 rowaddress locations within a 2ms time interval. Any normal
EARLY WRITE
READ-WRITE
- - - - I READ-MODIFYWRITE
DELA YEO WRITE
memory cycle will perform the refreshing, and the RASonly refresh offers a significant reduction in operating
power.
Power Dissipation
Fig.2.10 Write cycle
Most of the circuitry in the MSK 4116P, S is dynamic, and
most of the power is dissipated when the addresses are
Table 2.5 Output state in write cycle
Operation mode
Early write
Output state
High impedance
Read-write. read-modify-write
Data valid
Others
Unspecified
strobed. Both the RAS and the CAS are decoded and applied to the MSK 4116P, S as chip-select in the memory system, but if the RAS is decoded, all unselected devices go
into stand-by independent of the cAs condition, minimizing system power dissipation.
Stand-By Current-Refresh Only
The 100sB (stand-by current of V oo ) and the
(stand-by current of VBB) are calculated by the following
equations.
These output conditions of the MSK 4116P, S, which
can readily be changed by controlling the timing of the
write pulse in a write cycle, and the width of the CAS pulse
in a read cycle, offer capabilities for a number of applications, such as the following.
1. RAS/CAS refresh
100sB=1 001(Av) X{128 Xtc
-t} +
C(REF)
1002 x {1-(128 X
tc - )} .... Eq. 2
t C(REF)
IBBsB=IBB1(Av) X{128 Xtc
-t
C(REF)
1. Common I/O Operation
If all write operations are performed in the early-write
}+
I BB2 X{1-(128 Xtc
- t ) } .... Eq. 3
C(REF)
mode, input and output can be connected directly to give a
common I/O data bus.
Assuming that tc=37Sns, 1001lAv)=3SmA,
2. Data Output Hold
IBB1 (Av)=200~A, 1002=1.SmA,
The data output can be held between read cycles, without
lengthening the cycle time, until the next cycle commences.
IBB2=100~A, tC(REF)=2 ms,
we can obtain following results:
This enables extremely flexible clock-timing settings for
RAS and CAS.
100sB=3SmA x 0.024
15-14
IBBsB=200~A
• MITSUBISHI
.... ELECTRIC
+ 1.SmA x 0.976=2.3mA
x 0.024 + 100~A x 0.976=102~A
MITSUBISHI LSls
16K-BIT DYNAMIC RAM
(MSK4116P,S)
20
20
-
Ta=25"C
15
VOO=13.2V
VBB= -4.5V
RAS. CAS CYCLING
15
10
tC(RO)
= tc (WR)
10
r-
r--
=375ns
N =50 (5 LOTS)
23
27
25
33
AVERAGE 100
0.6
35
100sB=1 003 (Av) X { 1 2t 8
tcX C(REF)
}+
0.9
If-
,
1.5
IDO (mA)
100
Although the M5K4116P, S require no particular powersupply sequencing so long as the devices are used within the
t C(REF)
C(REF)
n
0.8
,
,
Power Supplies
1002 X{1-(128 X
tc - )} .... Eq. 4
I BBsB = I BB3 (Av) x {128 Xtc
-t
0.7
Fig.2.12 Distribution of stand-by
100
2. RAS-only refresh
~
STAND-BY
(mA)
Fig. 2.11 Distribution of average
Voo=13.2V
VBB= -4.5V
RAS =V1H
Ta=25"C
N =50(5 LOTS)
limits of the absolute maximum ratings, it is recommended
}+
that the V BB supply be applied first and removed last. V BB
should never be more positive than V ss when power is ap-
IBB2 X{1-(128 Xtc
- t )} .... Eq. 5
C(REF)
plied to V DO.
Assuming that 1003 (Av)=27mA, I BB3 (Av)=200JlA,
we obtain the following results:
100sB=27mA x 0.024 + 1.5mA x 0.0976=2.1mA
I BBSB =200JlA x 0.024 + 100JlA x 0.0976=102JlA
Stand-by current is about 2.1 mAo Therefore, by using
low-power refresh and external circuits, it is possible to use
Generally, when V DO is applied and V BB
is not applied, stand-by current is larger than that in the
normal state. Table 6 shows this effect.
Some eight dummy cycles are necessary after power is
applied to the device before memory operation is achieved.
Dummy cycles must be executed by the RAS/CAS refresh
cycles or RAS-only refresh cycles.
a battery back-up system.
Table 2.6 Change of stand-by current
~
Condition
:1*1
1001(AV)
:1*2
1002
1001(AV)
:1*3
1002
1001(AV)
:1*4
1002
1001(AV)
Unit
1002
VBB= -SV
25.3
0.71
26.0
0.73
25.9
0.69
24.9
0.72
mA
VBB=OV
28.0
0.76
28.8
0.78
28.7
0.74
27.6
0.76
mA
+10.7
+7.0
+10.8
+6.8
+10.8
+7.2
+10.8
+5.6
%
Change +%
• MITSUBISHI
;"ELECTRIC
15-15
MITSUBISHI LSls
16K-BIT DYNAMIC RAM
(MSK4116P,S)
2.2 16K-BIT DYNAMIC RAM APPLICATION
10000
APPLICATIONS FOR DYNAMIC RAM
5000
4000
3000
Dynamic RAM (Ramdom-Access Memory)s can be very effective components in the implementation of reliable, highperformance, low-cost memory systems. However, these devices have several requirements that should be considered.
Bit-Cell Structure
First, consider the dynamic memory bit cell, which is quite
unlike the cell of a static RAM. Fig. 2.13 shows a typical
single-transistor memory bit cell. The bit cell consists of
a transistor and a capacitor that constitute a "sample and
~
2000
"
'"
(/)
E
1000
~
f=
UJ
~
ex:
of-
Cf)
."
"
500
400
30 0
,,~
""'"
20 0
10 0
hold" circuit.
o
20
10
30
40
AMBIENT TEMPERATURE
"~
50
60
70
("C )
Fig.2.14 Storage time vs. ambient temperature
Refresh
Thus one can see that the refresh function is a very important requirement for a charge-storage memory, i.e., a
dynamic RAM. The dynamic memory controller must as-
WORD LINE
,- ---- ------1
I
I
I
I
I
I
iL_
e,l i
_ _________
--1
sure that every bit cell is refreshed periodically enough to
maintain data integrity. The refresh interval is specified by
the vendor, and a typical requirement is that each bit cell be
refreshed every 2ms.
I
SINGLE- TRANSISTOR
BIT CELL
Fig.2.13 Single-transistor memory bit cell
During the write operation, the selected word line is
brought to an active state (high). This causes the bit cell
transistor Q, to turn "On" and the data that is placed on
the bit line is stored in the capacitor Ct. The stored data is
retained even if transistor Qt turns "Off".
During the read operation, the selected line is brought
to an active state (high) again, and the capacitor voltage is
placed on the bit line. At this time, the read-out data is amplified and rewritten on the capacitor internally.
Because of the theory governing dynamic memory storage, capacitor charge in the cell will gradually leak off, and
the stored data will be lost.
For example, a 1nA leakage current discharging a 1pF
capacitor results in a voltage change of 1V per ms. The storage time of M5K4116P, S is shown in Fig. 2.14. If data is to
be retained for longer than the self-discharge time of the
cell storage capacitor, typically 2ms, the data must be
sensed before it is lost and then restored to its original
voltage level.
15-16
The M5K4116P, S are 16 384-bit memories constructed
with 128 rows and 128 columns. All columns in a single
row in an array are refreshed simultaneously. This means
that the user must supply 128 refresh cycles each 2ms.
In order to supply the refresh row address, a refresh
counter (7 bits) is required and is incremented after each
refresh cycle. A "two inputs to one output" multiplexer
is also used to multiplex either the system-supplied memory
address or the refresh counter-supplied adpress onto the
dynamic memory row address inputs.
Refresh Techniques
In most memory syster:ns it is difficult to guarantee that
normal memory operations will cause all the rows within a
memory to be sensed within the specified refresh interval.
For this reason, most dynamic memory systems have special
circuitry that will cause all rows of memory cells to be
sensed within the 2ms interval.
There are three commonly used techniques for refreshing
the memories. The first is "burst mode refresh" where all
memory accesses are inhibited for a fixed period of time
while all rows are continuously accessed. This mode is
shown in Fig. 2.15 (a). The second is "cycle steal mode,"
where a single memory cycle is periodically stolen from the
processor in order to refresh a single row. This mode is
shown in Fig. 2.15 (b). The third is called "invisible or trans-
• MITSUBISHI
.... ELECTRIC
MITSUBISitl LSls
16K·BIT DYNAMIC RAM
(MSK4116P, 5)
parent mode," where refresh cycles are introduced at the
times when the memory is not being accessed and thus
refresh is invisible to the processor. (The processor sees no
delay due to the refresh function.) This mode is shown in
Fig. 2.15 (c). The memory cycle of the invisible refresh
mode is generally longer than that of the first or second
method because single memory access continues after single
memory access.
2 MS MAX
"
))
W®
i NORMAL MEMORY CYCLE I
~
••
(a) Burst refresh mode
,
)
IREFRESfi CYCLE
(128 CYCLES)
2 MS MAX
I.
.I(~S~)I
NORMAL MEMORY
CYCLE
~
,1(128,T H)
1
SINGLE
REFRESH
NEXT MEMORY
CYCLE
(b) Cycle steal refresh mode
SINGLE MEMORY CYCLE
'I
) t·
SI~?LE MEMORY ACCESS, I,
SINGLE REFRESH
.1
Design Example
In designing dynamic memory systems, it is important to
decide whether the memory refresh will be synchronous
with the processor or asynchronous. In synchronous refresh, the designer uses a system clock to trigger the refresh
logic. In asynchronous refresh, however, the designer must
provide for a local timer to trigger the refresh and memory
access arbiter.
This example illustrates the asynchronous refres~
method which is more popular than the synchronous refresh in of interfacing dynamic RAMs to microprocessors.
The memory controller block diagram is shown in Fig. 2.16.
There are two controllers which access the memory. One is
the microprocessor, and the other is refresh timer which
requests a memory refresh every 15.6 fJS (MAX). The
memory access arbiter decides to which request the
memory cycle is allocated. If the two controllers generate
the request simultaneously, the arbiter allocates the memory cycle to the refresh timer.
Memory timing logic generates the memory clock timing
(i.e. RAS, CAS, R/W) in accodance with the memory
cycles. This timing is shown in Fig. 2.18. Three multiplexers
are used in the circuit of Fig. 2.17. In the normal memory
cycle, the row address (ADRO"'ADR6) or column address
(ADR7"'ADRD) is multiplexed by MPXCNT and CPU
AD R EN. In the refresh cycle, the refresh address is present
at MAO "'MA6, which is gated by REFADREN.
The refresh controller in Fig. 2.17 is also used in 64K
dynamic RAM applications by changing the refresh address
counter and microprocessor address multiplexer.
(c) Invisible refresh mode
Fig. 2.15 Refresh techniques
IREFRESH~
TIMER
CLEAR
CPURQ
ADDRESS
DECODER
CPU ADREN
MEMORY
ACCESS
ARBITOR
REF ADREN
MEMCTl
b
MAO-MA6
REFRESH
ADDRESS
COUNTER
1
tCOUNT UP
ACl-A6
MICROPROCESSOR
SYSTEM
REF cOMPl
L-..,
MEMORY
TIMING
LOGIC
=B
DYNAMIC
RAS RAM
CAS ARRAY
R/W
----,
MWRC
ADRO-ADR6
ADR7-ADRD
r
MPXCNT
MULTIPLEXER
TI
I
1:
r
7
01
DATASTB
DO
I
I
!
LATCH
.---J
I
DATO-DAT7
Fig. 2.16 Memory controller block diagram
• MITSUBISHI
' " ELECTRIC
15-17
U1
I
00
~
;.*1
TIMING CLOCK
(20 MHz)
b-----'.Nv---d R/W
CPURO
,.
(CPU RAM Request)
REFRESH ADDRESS COUNTER
LS393
r
,~CAS
M5K4116x8
OD
2
l
MAft
OC
OB
MEMORV
TIMING
LOGIC
5
LS244
,~RAS
I
I
MEMORV
OA
~CNT
I"I~
r-_
I"I-t
-tc:
(")(1)
::am
niii
=
*2
REF ADREN
REF COMP
...en
(REFRfCH COMPLETE)
MWRC
MPX CNT
(CPU MEMORY WRITE COMMAND)
vi
ADRO (LSB)-ADR6
*1~
~
;r I A
ADR7-ADRD Note (2)
MAO-6
\,
•
III
-...
;;.-1---<1
Note (2)
S=O
( S=l
V=A)
V=B
Note 1
ADDRESS MULTIPLEXER
~
LS258 x 2
RAM READ
DATa-DATl
RAM ACK
(RAM TRANSFER READV)
"3:
en
:-:
......
~
G)
.:u
Fig. 2.17 Refresh controller logic
'"
~
-<
Z~
:..3:=
_c:
n!en
:a:
:"r-
3:~
MITSUBISHI LSls
16K-BIT DYNAMIC RAM
(MSK4116P,S)
NORMAL MEMORY CYCLE
REFRESH CYCLE
TIMING
CLOCK
CPURO
REFRO __
~~
____________________- J
MEM CYCLE
OA
OB
OC
OD
-r__~__+-____~
OF(REF~C~O~M~P~)-+-+__
TIMING
LOGIC
OA
MPXCNT
R/W
'---+----~WRITE
RAM DATA LATCH
READY
~------N-O~T~R~E~A~D~Y~----~
r------------------------------~
Fig.2.18 Example of memory timing
IO/Mt--------------~
A15
I
A8
RAM AREA SELECT
----------~--~~-+~~
ALE 1 - - - - - - - - - ,
AD7
I 1-+------.--+1
ADO
14
I------I--+-------.<---_
ADRCl-ADRD
M5L8085AP
IE----+----- DA TO-DA T7
READY INPUT
FROM OTHER---~cr",
DEVICES
RAMACK
READY
RDD---+--~--r-a
WRr---t-,--~~~~-_a~r----------CPURO
~--~-------------- MWRC
Fig. 2.19 Design example of microprocessor interface
_
_ _ _- - - - 1 i i I~
I
• MITSUBISHI
;"ELECTRIC
15-19
MITSUBISHI LSls
16K-BIT DYNAMIC RAM
(MSK4116P,S)
=.=
Power Distribution and Decoupling Techniques
It should always be remembered that dynamic memories,
while appearing to be rather simple digital devices, are in
fact highly complex analog systems. They include differ-'
ential sensing amplifiers that must detect deci volt signals
buried in noise and must operate in tens of nano-
••
vcc~=
vss]C
seconds. For these reasons, the designer should respect the
complexity involved and take the steps necessary to ensure
vcc-...."...-~
a trouble-free design.
The layout of dynamic memories is of special importance. Typical I DD , IBB and Iss current waveforms for the
M5K4116P. S are shown in our data sheets. Distribution
and decoupling techniques must be used to suppress these
noises, which can cause data loss.
The layout should have an effectively gridded powersupply distribution network to supply adequate current and
to minimize inductive effects. The distribution of circuit
grounding is most important in reducing ground noise and
vcc;;;a=
v:c
inductive effects, and to provide a ground plane for the
signal lines. An example of the power grid of the M5K
4116P, S is shown in Fig. 2.20, in which the decoupling
capacitors are not shown.
In order to increase the effectiveness of the power grid,
decoupling capacitors should be used. The capacitors required fall into two categories. The first consists of capacitors of small size and low inductance such as monolithic
and other ceramic capacitors, which are adequate for
suppression of transient noise. The second type consists of
larger bulk capacitors used to prevent power supply drop.
These also should be included within the memory array for
good distribution.
The decoupling capacitors used in the memory array
should be of a type that exhibits good high-frequency
characteristics. It is recommended that a 0.1 J1F ceramic
capacitor be connected between V DD and V ss at every
other device in the memory array. It is also recommended
that a O.lJ1F ceramic capacitor be connected between VaB
and V ss at every other device in the array, preferably the
devices alternate to the V DD decoupling. Decoupling of the
V cc is fairly noncritical. The capacitors are connected at
the top and bottom of each column of memories.
In addition to the ceramic capacitor, it is recommended
that a 2,..., 5J!F tantalum or equivalent capacitor be con-
VDD
Vss
::~~~~~~~~f!:::::::VBB
VD~~V~BV~C VSSVBB
Note 7
"'5S
The dotted lines show the soldered side of the P.e. board,
Fig. 2.20 Suggested power grid for M5K41116P, S
c
c
c
c
c c
c
c
$00000000$
$DDDDDDDD~
~DDDDDDDD~
$DDDDDDDD~
A
C
B
C
A
C
B
C
A
C
B
C
A
C
A=O.l,uF from Voo
to VSS
B=O.l,uF from
VBS
to VSS
C=O.l,uF from Vee
to Vss
D=4.7,uF from Voo
to VSS
E = l,uF from
VSS
to VSS
B
C
Fig. 2.2 Effective capacitor placement
for the M5K4116P, S
Signal Lines Effects
By carefully laying out the circuit to minimize signal path
length, one can reduce effects due to the transmission-line
properties of the PC board. However, this may not be suf-
nected between V DD and V ss adjacent to the array for
each group of 16 memory devices. Use of a slightly smallervalue bulk capacitor is also recommended between V BB and
ficient. It is necessary to add a series-terminating resistor
to the output of the clock driver in order to match line im-
Vss. An example of capacitor placement is shown in Fig.
between the driver's source impedance and the characteristic impedance of the line.
2.21.
pedances and damp out reflections caused by mismatching
In order to avoid to cross talk problems, all signal lines
should be kept as short as possible. This implies that the
signal drivers and receivers should be physically close to the
memory array.
15-20
• MITSUBISHI
.... ELECTRIC
MITSUBISHI LSls
64K-BIT DYNAMIC RAM
(MSK4164S,MSK4164NS)
3. 64K-BIT DYNAMIC RAM
3.1 Technology
Since the introduction of the IK RAM in 1970, the
development of dynamic RAM devices has progressed at a
rate which has seen capacities multiplied by four in
approximately two years, the latest stage of development
being the 64K RAM.
Today's modern RAM devices take the user into consideration, and 64K dynamic RAMs which operate off a
single 5V power supply are common.
We will describe here the new technology which made
possible the development of a highly integrated, highperformance 64K RAM (Type M5K4164S) which operates
from a single 5V supply.
Fig. 3.1 shows the cross-section of the cell structure with
Table 3.1 summarizing a comparison of the basic parameters of the device with the 16K RAM.
Cell Structure and Process Technology
The M5K4164S 64K RAM makes use of the same two-level
n-channel polysilicon gate process and one-transistor cell
structure used in the triple power supply 16K RAM
(M5K4116 PIS) which has been used in large quantities.
To achieve a high-density RAM, the masks are manufactured using electron beam technology.
In addition, the geometries on several critical levels of
the M5K4164S are 2.5 to 3. OJ,.Lm , necessitating the use of
positive photo-resist (for resolution and delineation control) as well as dry-plasma processing at these critical levels.
Substrate Bias Circuit
In order to facilitate the operation from a single 5V supply,
the M5K4164S makes use of an on-chip substarate biClS
circuit. This bias circuit consists of a ring oscillator, driver
circuit, charge pump circuit, and decoupling capacitors. The
circuit supplies a bias to the substrate of approximately
-3.5V for Vee= 5V (Refer to Fig. 3.2).
The substrate bias circuit has the following functions.
1. It prevents destruction of storage data and disturbance of
bipolar transistor operation caused by input undershoot
which causes an injection of electrons from the input
terminals to the substrate.
2. A reduction in the capacitance of the pn junction
formed by the substrate and internal circuit nodes
enables an increase in circuit operation speed.
3. The transistor threshold voltage (V T H) modulation due
to a bias substrate is reduced, resulting in increased
circuit operating speed and stability.
CHARGE
PUMP CIRCUIT
!---=1
~r
L ____ J
I
SUBSTRATE
BIAS
DECOUPLING
CAPACITOR
Fig.3.2 Substrate bias circuit
POLY Si 2
AI WORD LINE
~
POLY Si 1
_________________ .L __
p+
IE
Fig.3.1
Table 3.1
Hi-C REGION
Hi-C structure memory cell cross-section
Main Parameters
Parameter
Memory cell area
Chip area
16K RAM
64K RAM
350.um2
200.u m 2
16.3mm 2
31.3mm 2
Effective channel length
4.um
2.um
Gate oxide thickness
850.6.
430.6.
Diffused layer depth
1.0.um
0.5.um
Diffused layer with
4.0.um
3.0.um
Aluminum width
4.0.um
3.0.um
As shown in Fig. 3.3, the substrate bias for high values of
Vee is lower than for the standby mode due to the effect
of increased impact ionization current. Adequate margin,
however, is maintained against a value of V 1L min of -2V.
Reduced Power Consumption and Noise
For operation from a 5V supply, it is necessary to reduce
the transistor threshold voltage, V TH • This however invites
error operation due to noise. For this reason, circuits
required to operate from low voltages only make use of
transistors with a low VTH , while those requiring noise
immunity are implemented with transistors having a high
value of VTH • This scheme insures stable operation.
To lower the peak circuit current, a significant problem
in memory system design, and provide for high speed operation, the ratioless driver circuit shown in Fig. 3.4 was used.
With this circuit, the current flowing in transistors 0 1
and O 2 for changes in the output waveform is practically
zero.
• MITSUBISHI
~ELECTRIC
15-21
MITSUBISHI LSls
64K-BIT DYNAMIC RAM
(MSK4164S,MSK4164NS)
POWER SUPPLY CURRENT VS
TIME MANUFACTURER
C
-7
>
«
-6
Vee=S.SV, Ta=2S·C
In
In
(f)
tiS
-S
UJ
I-
« -4
a:
I-
(f)
ill
;:)
(f)
-3
60
-2
40
I eCCAS phase is prevehted by the delay phase 1>1
from approaching td(RAS-CAS) max. This type of operation is referred to as gated CAS.
This gated CAS feature permits CAS to be activated at
anytime between the minimum and maximam value of
td(RAS-CAS) without affecting access time [ta(RAS)J.
For gated CAS operation, if the generation of internal
clock phase 1>CAS is delayed, the effective pulse width of
1>CAS is reduced. For this reason, the rising edge of CAS is
specified by th(RAS-CAS) which is reference to RAS rather
that tw(CAS L). This applies to the column address,W and 0
inputs hold time as well.
As shown by the dotted line in Fig. 3.14, if CAS falls to
a low level after td(RAS-CAS) max, the 1>CAS phase is
generated upon the falling edge of CAS.
The minimum and maximum values of td(RAS-CAS),
the delay time RAS to CAS, are specified for the
M5K4164S. Operation within the td(RAS-CAS) max limit
ensures that the access time for the device is guaranteed.
This value may be exceeded without causing data storage or
reading errors but the access time will be increased.
(2) CAS Rising Edge Timing (Fig. 3.15)
As shown in Fig. 3.15, the internally generated CAS circuit
precharge signal 1>CAS is generated with a timing that is
related to the relationship between RAS and the CAS rising
edge.
For a CAS rising edge occurring before the RAS rising
edge, 1>EAs is generated with the CAS rising edge as a
reference point (as shown in Fig. 3.15 as a solid line). If
however the CAS rising edge occurs after that of RAS,
1>CAS is generated with the RAS rising edge as a reference
(shown as dotted line in Fig. 3.15).
However, the data in the output buffer is cleared upon
the occurrence of the rising edge of CAS regardless of the
state of RAS. The required pulse width for clear is
tw(CASH ).
In this manner, the output data can be maintained for a
long period while the internal precharge width is made
large.
As described above, if the CAS rising edge occurs after
that of RAS, the internal CAS pulse width becomes not
tw(CASL) but th(CAS-RAS). Consideration should be given
to this point in system design.
td (RAS-CAS) Max
w
which is synchronized in turn to the REF input, 128 REF
pulses required to cycle to the original state. For self
refresh operation, the refresh counter is free-running with a
period of from 12 to 16Ms, counting up in synchronous to
the refresh request signal REFREO (described afterwards).
A complete cycle and return to the original state requiring
that the REF input be held low for 16Ms x 128 = 2 ms.
The above described counting operation is performed
approximately in synchronous with the refresh operation
completion. The output of the refresh counter, 0 0 to 0 6
(refresh address) is held until the next refresh cycle,
forming the address for the next cycle.
The refresh counter outputs are initialized by approximately 8 dummy cycles of RAS, RAS/CAS, or REF.
Therefore, no special initialization is required for this
refresh counter.
However, the contents of the counter, that is the toggle
counter flip-flop states, cannot be reset or preset externally
during power up or dummy cycles.
For this reason, using both normal RAS and pin 1
refresh will cause the specified refresh time to be exceeded,
and therefore should be avoided.
(3) Address Multiplexer
Fig. 3.28 shows the M5K4164S onchip address multiplexer.
The address multiplexer consists of two MOS transistors
at the address buffer inputs and the associated control
signals (MUX, MUX).
During a normal cycle, MUX is high and MUX is low, so
that only the external address Ao to A6 is input.
For pin 1 refresh operations, MUX is low and MUX is
high so that the refresh counter output signals 0 0 to 0 6
only are input to the address buffer.
MUX
;PAL
AO
~--..
Ao
.A"I---~AO
A1
A6
~--..
MUX
~
¢w
Qo
REFRESH ADDRESS
COUNTER
MUX------ITO
00
01
Fig. 3.28 Refresh address counter and multiplexer circuits
15-34
• MITSUBISHI
.... ELECTRIC
06
A6
MITSUBISHI LSls
64K·BIT DYNAMIC RAM
(MSK4164S,MSK4164NS)
(4) Timer Circuit
Fig. 3.29 shows the timer circuit block diagram while Fig.
3.30 illustrates its timing.
In the circuit of Fig. 3.29, the oscillator provides the
substrate bias as well. The other circuits are active when
REF is low.
When REF goes low, transistor 0 1 turns on, O 2 turns
off and the charge stored in C2 passes through the
rectifying circuit C2 and 0 1 to discharge upon the falling
edge of the oscillator output signal. The charge for one
cycle of the oscillator output is proportional to the ratio of
the capacitance of C 1 and C2 .
The ratio of C 1 to C2 is chosen such that the voltage
across C2 for an oscillator repetition period of 12 to 16Jls is
approximately equal to the threshold voltage of the next
gate. When the C2 voltage reaches V T H, the refresh request
signal REF REO goes active, causing the RAM refresh
operation similar to the autoamtic refresh external signal
REF. When C2 is charged by REFREO, REFREO goes
low, causing a repetition of the above described timer
operation.
As long as the REF signal is kept low, this operation will
automatically continue refreshing all memory cells every 2
ms.
Automatic Refresh Timing
Automatic refresh is accomplished in the same manner as
RAS only refresh but without providing the refresh address
data.
Fig. 3.31 shows the timing of the automatic refresh
operation.
Automatic refresh begins when REF is set to low
tW(RASH) after RAS goes high.
Shortly after the refresh cycle begins the internal RAS
signal begins to operate to strobe the refresh counter
(TO REF
CIRCUIT)
Fig. 3.29 Timer circuit block diagram
;;
IJ
\.....
\~--~r----~J~
TIMER
REFREQ
INTERNAL
RAS
~~~
------------~J~.Jf\-------
~~~
Fig. 3.30 Timer circuit timing
output and perform the refresh.
The REF input is internally latched. When the refresh
operation is complete an internal refresh complete signal
causes the chip to be precharged. Therefore, it is hot
necessary to use the REF input to determine the precharge
time greatly simplifying the timing design of REF.
It is also possible to perform hidden refreshing by
holding the CAS input low after a read cycle. The timing is
very similar to the RAS hidden refresh operation timing.
tW(RASH)
(1) Multiple pulse mode
td(RAS-REF)
I---~'------'---+I td (REF - RAS)
(2) Single pulse mode
tw (RASH)
tSU(REF-RAS)
td (REF-RAS)
tW(REFL)
Fig. 3.31
Automatic refresh timing
• MITSUBISHI
;"ELECTRIC
15-35
MITSUBISHI LSls
64K·BIT DYNAMIC RAM
(MSK4164S,MSK4164NS)
tW(REFL)
Fig. 3.32 Self refresh timing
For details refer to the specifications.
Self Refresh Timing
Self refresh is generally used for battery backup of memory
contents.
Fig. 3.32 shows the self refresh timing relationships from
which it can be seen that they are quite similar to those of
automatic refresh. Self refresh begins when REF is set to
low tW(RASH) after RAS is set to high.
Shortly after the beginning of the refresh cycle, the
internal RAS signal begins to operate to strobe the refresh
counter and perform the refresh operation.
As long as RAS is high and REF is low, the RAM will be
automatically refreshed. This operation is repeated with a
period of from 12 to 16J.(s. After 2ms, the refresh counter
has gone through all of the row address, refreshing all of the
memory cells. Self refresh ends when REF is set to high but
setting REF to high may not terminate the internal
operation of the circuit (refer to Fig. 3.30) so that one
cycle time of t d ( R E F-R AS) is required between setting
REF to high and RAS to low.
As with automatic refresh, hidden refreshing is possible.
For details refer to the specifications.
Notes on the Use of Pin 1
When pin 1 is not to be used to refresh the chip, it should
be handled in the following manner.
(1) Since pin 1 refresh is inhibited by setting the REF
input to high, the input should be set between VI H
min and VI H max. (The pin 1 input leakage current for
V IN = 6.5V is guaranteed to be below 10J.(A.)
(2) When the above method is not possible, pin 1 should
be left open. Since as shown in Fig. 3.33 as MOS
transistor is used to connect a pull-up resistor between
the input terminals and Vee' the terminal will be held
to a high level (Vee) when left open.
However, when the input is set low in order to perform
a refresh operation, a current flows from Vee to the
input terminal. This resistance is made a very high
value (approximately 3Mfl) in order to guarantee the
specified leakage current of 10J.(A maximum for V IN =
OV.
This high resistance results in pin 1 being susceptible to
the effects of external noise so that if pin 1 is to be left
open, such noise should be considered carefully.
Vee
Veep~
PULL-UP
MOS
11
>Vee +VTH
-
I
~
REF TERMINAL
STRAY
CAPACITANCE
~F
PROTECTIVE
1r
RESISTANCE
500n
I
-r-
Fig. 3.33 REF input equivalent circuit
15-36
• MITSUBISHI
..... ELECTRIC
STRAY
CAPACITANCE
~F
MITSUBISHI LSls
64K-BIT DYNAMIC RAM
(MSK4164S,MSK4164NS)
3.3 M5K4164S Bit Map
Introduction
To facilitate the generation of worst-case pattern checking
and the optimization of test sequences, it is necessary to
know the internal topology of a memory device. This
section will examine the internal topology of the M5K4164S.
Address Decoder
Fig. 3.35 shows the address decoder. To optimize pattern
layout, the decoder is arranged as shown in Fig. 3.35. For
this reason, with Ao (row) as the least significant bit and
A7 (column) as the most significant bit, sequential binary
addresses will not address adjacent cells in order.
Memory Array
Fig. 3.34 shows the dual in-line package as viewed from
above with pin 1 to the upper right. It illustrates the
memory cell layout.
The row decoder are located to the left of the memory
cells while the colum decoder are located parallel to the
cells.
PIN 1
o
~I
<
16K MEMORY ARRAY
8~==============~
8a~,-1__16~K~MMET.MT,O~R~Y~A~R~R~A~Y~
COLUMN DECODER
50:1.
16K MEMORY ARRAY
1<
============:1
:=,
.
16K MEMORY ARRAY
(f)
D
(f)
Fig. 3.34 Memory array location
ROW ADDRESS
-,
I
A5
A7
AO
0
0
o
0
o
o
000
o
0
0
Al
A3
A6
A2
A4
0 000
0
0
0
1
1
000
0 0 0
1
1
3
1
0
2
0
0
t
0
DATA
1
1
0
1
1
1
1
1
o
0
0
1
1
1
1
1
0
1
0
1
1
1
1
1
1
1
127
0
1
1
1
1
1
1
0
126
COLUMN
ADDRESS
1
o
0
1
0
o
0
1
0
0
o
1
0
o
0
o
0
256 SENSE
AMPL~:IER
1
CIRCUITS
\,
16384-81T MEMORY ARRAY
-DATA
A7
0
1
1
0
0
1
0
1
1
o
0
1
1
A6
0
0
1
1
o
0
0
1
1
o
0
1
1
A1
0
0
0
0
1
1
o
0
0
0
0
1
1
1
1
A2
0
0
0
o
0
0
1
1
1
1
1
1
1
1
A3
0
0
0
o
0
1
1
1
1
1
1
1
1
A4
0
0
o
o
0
0
0
1
1
1
1
1
1
1
1
A5
0
0
0
0
0 0
1
1
1
1
1
1
1
1
AO
o
0
0
0
o
1
1
1
1
1
1
1
1
0
o
o
0
0
1
0
0
1
1
0
1
0
0
I
16384-81T MEMORY ARRAY
0
I
0
,.
0
128
16384-81T
MEMORY ARRAY
DATA
I
1
1
1
1
1
1
o
0
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
255
1
1
1
1
1
1
1
0
254
256 SENSE AMPL;:IER CIRCUITS
16384-81T
MEMORY ARRAY
DATA
[
~65535
65534
~
III!!I
_ _ _ _ _ _ _ _ IM
Fig. 3.35 Address decoder location
• MITSUBISHI
.... ELECTRIC
15-37
MITSUBISHI LSls
64K·BIT DYNAMIC RAM
(MSK4164S,MSK4164NS)
For the arrangement of Fig. 3.35, Table 3.3 shows the
addresses that will be accessed for sequentially incremented
binary addresses if A6 (row) is the least significant bit and
Ao (column) is the most significant bit.
Bit Topology
For the purposes of simplified explanation, we have
assumed thus far that the memory cells are located in an
orderly fashion in a matrix. For actual devices, however,
techniques required to increase the density on the chip
dictate that an arrangement such as shown in Fig. 3.36 is
used.
For this reason, this layout must be considered carefully
when designing tests which detect interference between
adjacent cells.
Data Polarity
Because the sense amplifiers are located in the center of the
bit lines of the M5K4164S, half of the data matrix is stored
in inverted form. While this has absolutely no effect on
actual operation, it must be considered if a test is to be
devised which will test all cells in the charged state. This bit
inversion pattern is given in Table 3.4.
COLUMNS
• • • • WORD LINE
IS\SSI
o
BO
B1
B2
B3
GATE
BIT LINE
wolIlI....IIIIII~II....IIII....1
[
W1
W2
W3
VJ
s:
o
a::
W4
w5111111__........lIlIiI~II..1i1i
W6
[
W7
SENSE AMP. ~
I
J
I
J
I
I
Fig. 3.36 Simplified internal bit topology
15 - 38
I
I
I
I
The area represented here IS phYSically located
corner of the array
• MITSUBISHI
~ELECTRIC
In
I
I
the upper left hand
MITSUBISHI LSls
64K-BIT DYNAMIC RAM
(MSK4164S,MSK4164NS)
Table 3.3 Address Coding
Column
Cell No
Row
(MSB)
AO As A4 A3 A2 Al A6 A 7
(LSB)
A7AoAsA4A3A2A1AS
0
0
0
a
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
32 767
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
65535
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
Table 3.4 Data Polarity Arrangement
A7
AD
Input
Memory
(row)
(row)
data
data
Output
1
1
1
0
0
0
1
0
1
0
1
0
cell
data
0
0
1
0
1
0
1
0
1
0
1
1
1
1
0
0
0
1
~~
Write
Operation
Read
Operation
• MITSUBISHI
.... ELECTRIC
15-39
MITSUBISHI LSls
64K-BIT DYNAMIC RAM
(MSK4164S,MSK4164NS)
3.4 Memory System Design Considerations
New memory systems designs are making use of dynamic
RAM, static RAM, EPROM and other semiconductor
memory devices. All of these devices have some general
design considerations in common. This application note will
examine some of the delicate timing considerations involved in the design of a dynamic RAM board.
Power Distribution
Fig. 3.37 shows the current waveform of an M5K4164S
dynamic RAM. Note that when RAS and CAS go low, the
row or column address latch and buffer are charged, and
that when RAS and CAS go high, the row or column
address latch and buffer are precharged, resulting in a
transient current waveform. The 60 to 80mA current
pulse of approximate width 50ns and a risetime of 5""'10ns
represents the risetime which is observed at 50ns per division. With rise and fall times of this magnitude harmonic
noise components above 10MHz are generated. It is therefore necessary when designing the board power distribution
to suppress such noise and provide the device with a clean
supply voltage. Decoupling capacitors should be used which
are capable of charging a small loop. For a O.lJ.LF capacitor
value used with a 250ns cycle RAM, the spike voltage is
given by the following expression.
1
v = c
J
di
dt =
~
RAS
U
CAS
~
(f)
f-
a5a:
100
80
a: Icc 60
=>
u (mA)~8
:;
0
2::
100
=>
(f)
Iss ~8
(mA) ~8
0
50ns
.
80m A
Idt = - - - x 50ns = 40mV
O.lJ.LF
10nH x
80mA
50nS
Fig. 3.37
Supply current vs time RAS/CAS cycle
RAS only cycle
Rs
Fig. 3.38 (a)
Rl
vee
= 16mV
15-40
Ls
PC board trace equivalent circuit
Ll
R2
f'
L2
C'I
R3
L3
n
RS = Rl + R2 + R3
Ls
Rs I = 4mQ x 80mA = 0.32mV
/DIVISION
TIME
This yields an acceptable value of spike Voltage.
It is recommended that ceramic capacitors with good
high frequency characteristics are used as the decoupling
capacitors in memory arrays. The decoupling capacitor is
connected between the memory Vee and the ground with
as short a lead dressing as possible. In addition, as bulk
decoupling a solid tantalum capacitor is required. This type
of capacitor has a better transient response than other large
value capacitors and can be used with one capacitor per 16memory devices between Vee and the ground.
The power supply traces for a memory array should be
made as wide as possible and it is recommended that they
be arranged in a grid. Fig. 3.39 shows an example of such
an arrangement.
As another method, the use of multi-layer boards is
possible, and is an effective method in simplifying power
distri buti on.
Fig. 3.38 (a) shows the lumped constant equivalent circuit for a PC board. Ls and Rs represent the PC board
inductance and resistance respectively. If we let the Ls and
Rs of a 10mil wide 2-ounce copper pattern be 10nH/inch
and 4mQ/inch, then the generated spike voltage is given by
the following expression.
Ls •
Since the effect of the series resistance Rs compared to
that of the series inductance is very small, it may be
neglected. The series resistance of Ls is frequency dependent, increasing with increasing frequencies.
To reduce the level of the spike voltage, as shown in Fig.
3.38 (a), a decoupling capacitor is used to decrease the series
resistance. This is done by shortening the PC board current
loop.
=
L 1 + L2 + L3
Fig. 3.38(b) PC board trace equivalent circuit with
decoupling capacitors
• MITSUBISHI
.... ELECTRIC
MITSUBISHI LSls
64K-BIT DYNAMIC RAM
(MSK4164S,MSK4164NS)
GND Vee
GND Vee
Vee-GND-
Logical Considerations
For memory systems with critical timing, it is necessary to
consider the propergation delay to surrounding ICs. To
minimize signal delay, gate selection and the use of the
same IC package for related signals are effective in reducing
the difference in delays between signals. To reduce the
capacitive loading on drivers, it is necessary to limit the
number of drivers per memory array. For RAS and CAS, 8
memory/drivers and for address 16 memories/driver are
recommended.
Vee- GND-
Vee-GND-
Fig.3.39 Gridded power distribution and decoupling
capacitors
Signal Distribution
The next most important consideration in the design of a
memory system is the design of memory signal (address,
data, and control signals) distribution.
For the case of the M5K4164S dynamic RAM, two
types of chip enable signals exist; RAS and CAS. If these
are to be driven by TTL circuits, it is very important to
keep the driving TTL device as close as possible to the RAM
array. This minimizes the transmission line impedance
mismatch between the RAM array loaded line and the TTL
,driver. Another technique is the use of a damping resistor
located close to the driver. The value of this resistor is
selected to provide a good waveform at the RAM input, the
usual values being in the range 10 to 51ft This technique
brings the output impedance of the driver close to the line
impedance which minimizes waveform overshoot and
undershoot.
To eliminate crosstalk from RAS and CAS, the RAS
and CAS signal lines should be kept at 90° to the traces for
other signals. If this is impossible, they should be kept as
far as possible from traces of other signals. In addition the
address and data signal traces should be kept as short as
possible.
• MITSUBISHI
"'~L~CTRIC
MITSUBISHI LSls
64K-BIT BYNAMIC RAM
(MSK4164S, MSK4164NS)
3.5 M5K4164S Refresh Methods
Introduction
The refreshing of the M5K4164S cell matrix requires the
refreshing of 128 row addresses at least every 2ms. In
addition to the previously available RAS-only refresh
method, the M5K4164S provides REF (pin 1) automatic
refreshing, and self-refrestling. This section will cover the
application of REF refresh operations.
Automatic Refresh
Automatic refresh begins after RAS precharge (RAS = V I H)
upon setting RAF (pin 1) to low. This method is quite
similar to the RAS-only refresh with the refresh address
counter output present as a 7-bit word for automatic
refreshing, the refresh counter being automatically incremented at the end of the refresh cycle. Fig. 3.40 shows
the automatic refresh timing.
tw (RASH)
RAS
VIH
VIL
td (RAS- REF)
tsu (REF'RAS)
to (REF)
td (REF-RAS)
tw (REFL)
REF
VIH
VIL
Note
CAS, Address, D and Ware don't cares.
Parameter
Symbol
Alternative
M5K4164S·15
Limits
Symbol
Min
M5K4164S-20
Unit
Limits
Max
Min
Max
to (REF)
Automatic Refresh Cycle Time
tFC
260
330
ns
tw(RASH)
RAS high pulse width
tRP
395
480
ns
100
td (RAS-REF)
Delay time, RAS to REF
tRFD
tw (REFL)
REF low pulse width
tFP
80
tw(REFH)
REF high pulse width
t FI
135
150
ns
td (REF-RAS)
Delay time, REF to RAS
tFSR
30
30
ns
tsu(REF-RAS)
REF pulse setup time before RAS
tFRD
295
360
ns
Fig. 3.40 Automatic Refresh Timing
15 -42
• MITSUBISHI
~ELECTRIC
ns
120
8000
100
8000
ns
MITSUBISHI LSls
64K-BIT DYNAMIC RAM
(MSK4164S,MSK4164NS)
Automatic refresh has many advantages over the RASonly refresh method generally used previously. As shown in
Fig. 3.41, RAS-only refresh generally requires logic circu itry. This consists of the row-address, column-address and
refresh address multiplexer and refresh address counter.
With automatic refresh, the dotted area shown in Fig. 3.41
may be eliminated.
,.........-ADR 7
ROW
x
.6
5
{
AD...
::2:
4
UJCX)
UJL0
W('.J
ADR 7
COLUMN
a:
0 '"
6
5
{
BO
W
0:
0
0
-
&
-
~
(f)
&; 10- 7
o
Z
<{
I-
(f)
10- 8
2
4
SUPPLY VOLTAGE
Vee
(V)
Memory Map
Fig. 5.4 shows the M58981 P memory map.
ROW DECODER
/ A6 A7 As A9
1024-WORD MEMORY ARRAY
16
1023
~:
o
~
16
(~~~~~Ol+-________
COLUMN
DECODER
1024-WORD MEMORY ARRAY
10_2_3_____________________________I_/O
__3______________________________----------------1
~
A2
A3
A4
As
1 1
1 1
0 0
1 1
1 1
0
0 0 1 1
1 1 0 0
0 0 0 0
1 1 1 1
1 1 1 1
0 1
0 0
0 0
0 0
1 1
1 1
0 0
1 0
1 1 0
0 1 1
1 0 0
1 1 1
1 1 1
1 o 0 1 1 0
11 0 0 1 1
11 1 1 0 0
0 0 00 0
0 0 0 0 0 0
1 1 1 1 1 1 1 1
0 1
0 0
0 0
1 1
1 1
o
0
0
0
0
0
1
1 1 0
0 1 1
0 1 1
0 1 1
0 0 0
1 1 1
0 1 1
0 0 1
1 1 0
1 1 1
0 0 0
1 1 1
1 1 0
0 1 1
0 0 1 1
1 1 0 0
0 0 0 1 1
1 1 1 0 0
0
0
1 0
0
1
0 1
0 0
1
1
0
0
1 1 1
0 0 0
1024-WORD MEMORY ARRAY
16
1023
1024-WORD MEMORY ARRAY
16
I/O
1
1023
Fig. 5.4 Memory map
15 -- 60
• MITSUBISHI
~ELECTRIC
0
1
0
0
1
0
0
0
0
0
1
0
1
0
0
0
1 1
0 0
0 0
1 0
1 1
1 1
1 1
0 0
1 1
0 1
1 0
1 1
1 1
0 0
0 0
1 0
0
1 1
1 1
0 0
0
1 1
0 1
0 1
1 0
10
00
0
1
1
0
0 0
0 0
1
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0 0 1 1
1 0 0 1
1 1 1 0
1 1 1 1
0 0 0 0
0 0 0 0
0 0 1
1 0 0
0 0
0
1
0 0 0
0 0 0
MITSUBISHI LSls
CMOS STATIC RAM
(MS8981P, MSLS101LP.l)
5.2 CMOS STATIC RAM APPLICATIONS
INTRODUCTION
NON-VOLATILE MEMORY SYSTEM
Mitsubishi M5L 5101L P and M58981 P are static RAMs that
are fabricated with a CMOS technology. The M5L 5101L P
We can relatively easily design a large non-volatile memory
system with little additional interface logic by using CMOS
is organized as 256 words of 4 bits, and the M58981 P is
RAMs. The block diagram of a basic computer system that
organized as 1024 words of 4 bits.
They are fully TIL-
uses CMOS RAMs is shown in Fig. 5.5, and the power
compatible, and use only a single 5V supply voltage Vee.
supply on-off timing of the system are shown in Fig. 5.6. It
The purpose of th is application note is to describe the
is usually necessary to have advanced warning that AC
power has been lost. This warning signal produced by the
various
circuit
techniques
for
battery-supported non-
volatile memory systems. Electrical characteristics for the
power-fail-detect circuit interrupts the processor, which
two RAMs can be found on the previous pages.
stores the volatile data in the non-volatile area (CMOS
RAMs) before the system's DC source drops. And after the
RAMs have been protected, their Vee power source is
replaced by V SAT , as shown in Fig. 5.6.
BACK-UP POWER (VSAT)
VSAe
SYSTEM POWER (Vee)
AC POWER
REGULATOR
==>
POWERFAIL
INTERRUPT
POWER-FAIL
DETECT
CIRCUIT
MEMORY PROTECT SIGNAL
fig. 5.5 Non-volatile memory system
...............----1~.
AC INPUT
CD
Vee
~
@
RECTIFIED AC
@
------------
VTH
/
~
COMPo OUT
@
NMI INTERRUPT
®
----------~~
®
SYSTEM RESET or MEMORY PROTECT
---_/
(j)
Fig. 5.6 Power on-off timing
• MITSUBISHI
"'ELECTRIC
15-61
MITSUBISHI LSls
CMOS STATIC RAM
(MS8981P, MSLS101LP.l)
EXAMPLE OF CMOS NON-VOLATILE MEMORY
SYSTEM
Power-Failure Detection
The power-fail-detect circuit watches a separate power
supply point to provide an advanced warning of power
failure. As described before, this warning signal (power
fail) can interrupt the processor or merely protect the
CMOS RAMs.
Fig. 5.7 is a simplified diagram of the power-fail-detect
circuit. This shows that the power failure is detected from
the secondary transformer output, which is not regulated.
The Zener-diode voltage and RC time constant should be
well selected to prevent AC power failure from shutting
down the memory system.
SECONDARY SIDE
@
TO SYSTEM POWER
I---~-"::"--?----
Vee
U1 M51201 L (COMPARATOR)
U2 LS123
I,
Period with no AC power.
t2
Period of power fail operation (interrupt)
Fig.5.7 Power-fail-detect circuit
Power-Switching Circuit
The power-switching circuit replaces the main source
Vee by the back-up power source V BAT when Vee drops,
and replaces the V BA T by the Vee when the Vee voltage
rises enough to enable normal operation.
Two types of power-switching circuit are shown in Fig.
5.8 and Fig. 5.9. The diode-coupled circuit in Fig. 5.8 requires the main DC supply Vcc to be above the required
VSAc voltage by the amount of drop through the diode
(about O.6"'O.7V). Fig. 5.9 shows a transistor-coupled circuit, which has better performance than the circuit in Fig.
4. In this case it is recommended to use a transistor with
low collector-base saturation for Q1.
01
VBAC
02
1
-
VBAT
BACK-UP
POWER SUPPLY
Fig.5.8 Diode-coupled switching circuit
TRl
r---~~-~
VBAC
r---~---~
03
VCC
04
+
-
VBAT
1
Fig.5.9 Transistor-coupled switching circuit
15-62
• MITSUBISHI
"'ELECTRIC
MITSUBISHI LSls
CMOS STATIC RAM
(MS8981P, MSLS101LP.l)
TYPICAL APPLICATION CIRCUIT
An Example of M5L5101 LP-1 Application
An example of a 1 K-byte non-volatile M5L5101 LP-1 memory system is shown in Fig. 5.10. In this case, the memoryprotect signal is detected from the voltage of power source
Vee. But it is better to watch the unregulated voltage (see
Fig. 5.7) to produce the memory-protect signal that protects RAMs at the time when Vee is dropping or rising as
shown in Fig. 5.6. The CE2 pin is used for decoding the
RAM array. When the RAMs are not selected (i.e. CE2
= low-level), they enter a stand-by mode, and the power
supply current is extremely low.
M5L5101 LP-l x 8 1024-BYTE CMOS STATIC RAM ARRAY
Vee
SYSTEM POWER - - - - . - - ,
VSAe
!TANTALUM
LSB
4 BITS
ADDRESS BUS
Ao-A7
(AD: LSB)
ME MW
MEMORY WRITE
ME M R
MEMORY READ
RAM1
ADDRESS BUS
As-A15
(A15 : MSB)
TANTALUM
(J)a:
(J)LlJ
LlJO
a:o
Ou
OLlJ
MSB
4 BITS
«0
MEMORYPROTECT
CIRCUIT
Vee
RAM3
DATA
BUS
00-07
Fig.5.10
___
~L-
RAM4
_ _ _~~_ _ _ _ _ _ _ _ _~_ _ _ _ _ _ _L -_ _ _ _ _~~_ _ _ _ _~
Example of M5L5101 LP
• MITSUBISHI
"'ELECTRIC
15-63
MITSUBISHI LSls
CMOS STATIC RAM
(MS8981P, MSLS101LP.l)
An Example' of M58981 P
The M58981 P is a CMOS RAM which is fully pin compatible with M5L2114LP is organized as 1024 words of 4
bits. The M58981 P has two control inputs, CS and R/W.
The ts can control normal memory operation and stand-by
operation. When the RAM is in the stand-by mode (i.e. CS
SYSTEM
POWER
(VCC)
/~
'--------J-~------OV
-Vee
MEMORY
rr.OTECT
~------------~------- OV
-Vcc
~2.2V), the power supply current is extremely low.
Fig. 5.11 shows the memory signal timings at the time
when AC power turns on and off. An example of 4K-byte
non-volatile memory system using M58981 P is shown in
Fig.5.12.
Ir_---vCC
~~
'-------------'1------ VBAC
CS
------)--------------
- - - - - OV
' -' - -_ _ _ _ _ _ _ _--J'
~VCC
_ _ _ _ _ _ VBAC
VBAC
- - - - - - - - - - -- - - - -- - - -- - - - -- - -- _. OV
Fig.5.11
Power on-off timing (M58981P)
M58981P x 8 4K-8YTE CMOS RAM ARRAY
A9- A O
10
MEMW--------~~--_+~----~----------+-~~~--~_+---+----r__r--~--~--r_~
CS4
CS2
MEMR--~------~
CS
DATA
BUS
--~_+~~--------+_----~~DBDI~~--~~----~~---------L----------L---------~
DO
'-M-E-M-O-RY-.P-R-OT-E-CT--+-------~DBIN
CIRCUIT
Vee
Vee
BUS BUFFER
VBAe
--------1~'"'"
SYSTEM
POWER
M5L 8216PX2
RC
POWER·
SWITCHING
CIRCUIT
PROTECT
SIGNAL ---'\Mr-----+---'-NI,-----L
Re : CHARGING
REGISTER
NI·Cd
BATTERY
Fig.5.12
Example of M58981P
Other Recommendations
1. Nickel-cadmium batteries are available for the memory
back-up power source because of its rechargeable operation and wide variety of capacities, sizes and styles. For
details, see related articles.
tained that the propagation time of CMOS gates does
not exceed the access time of memory, and also that" the
2. In order to decrease the DC power-source impedance,
decoupling capacitors whose leak currents are small
should be used. It is also necessary to use O.Ol~O.lJlF
monolithic-type capacitors and 2-5,uF tantalum types
effectively.
15-64
3. When CMOS gates are used for decoding logic as shown
in Fig. 5.10 and Fig. 5.12, it shou Id be carefu lIy ascer-
stand-by voltage of the gates does not drop below 3V.
(It is possible to reduce the propagation time of CMOS gate
using high-speed CMOS gate version TC40HXXX series.)
• MITSUBISHI
..... ELECTRIC
Vee
Ql
SECONDARY POWER SUPPLY
.--------:--c-------:--c-----;::--:::---:::-;:,-:-.,.--+_------,
A733
< M58981P-45 > x 32
r--~~~'-~~~
14A I 15A I 16A 117A 1 18A 1 19A
P1
MROox'119
,.
AA
A9
A8
A7
A6
A5
A4
A3
A2
Al
20A
""l
I/O 2
~;
:~g ~
11
I
14B I 15B I 16B I 17B I 18B I 19B I 20B 14
I/O 1 13
I/O 212
:~g~
11
"""''''''''''''"'''''lcslcslCS-
8Y
I"'I~
r-_
I
~v,
~v~
~vv
~,4
CS5
I"'I-f
("un
8Y
CS6
81
CS7
"I
SWAP BUFFER
LS640
-fC:
::am
:5
(iii)
~g~~;:
341---------71
321---------;;1
'" I
AOR 11' 30t=========J~~!!2!!I""-+c::_--5TIT,..._T;5I
AOR10,28
'CO
I ,eo I ' " I ,eo I
,OC
1/01
1/02
1/03
1/04
AORF'441-----~,--r-T.~
AORE'
AORO'
AORC'
AORB'
AORA'
AOR9'
AOR8'
AOR7'
AOR6'
AOR5'
AOR4'
AOR3'
43r-----~
46r-----~
;~ ~~
GND 8586
140
150
160
170
180
190
200 14
1/01 r.l";-3--t~.o;-;;t
1/02 r.l*"2--+,..,..,....~
:ig~ 1-'"1.:...1-;::=~
PULL UP
R15
'-----------~------------
U1
I
Fig. 5.13 Schematic diagram of 16K byte CMOS RAM board
II
14
13
12
11
2
3
4
5
6
7
8
9
I
I
I
I
I
I
I
I
I
,
49r------~~~
52r-----~
511---------,;i
54
53
56
~g~f: ;~
U1
m
B1 Al
B2A2
B3A3
B4A4
B5 A5
B6A6
B7 A7
B8A8
45r-----~
481-----~
47r-----~
501-----~
AORO' 57r-----~
3 4
5 6
81 82
+5V 83841---4--t"-T--1-'
1 2
(])
I ""
18
17
16
15
14
13
12
l1
CS13
68
67
70
69
72
71
74
73
DATA 7'
DATA 6'
DATA 5'
DATA 4'
DATA 3'
DATAZ'
DATAl'
DATA 0'
CD
n
3:
CD
(I)
~
UI
CD
loA
0
.:v
CIt
~
UI
:'=i
r-
...
0
...r"V
...•
UI
'-'
-t~
-tClt
_c:
n!CIt
::a:
:'r3:~
MITSUBISHI LSls
CMOS STATIC RAM
(MS8981P, MSLS101LP.l)
Design example of *MUL TI-BUS board
Design example of CMOS RAM board is shown in Fig. 5.13,
and the block diagram is shown in Fig. 5.14.
This board is compatible with the proposed IEEE 796 bus
standard, called *MU LTI BUS
MEMORY PROTECT
MEMORY
PROTECT
LOGIC
MEMORY INHIBIT
,1
SEGMENT
ADDRESS
DECODER
4
ADDRESS
20
r-
2
RECEIVER
SECONDERY
POWER SUPPLY
ADDRESS
rL
~
~
2
LOW/HIGH BYTE
Voo
~
CS
---r-
CS
M58981 P-45 x 32
-
CS
'"""--
r-------,
4
CMOS RAM AR RA Y
8
~
f<:{
l:J
DECODER
I
HIGHER
BYTE
PROTECT
f2
LOWER
BYTE
ADDR ESS SE LECT
SWITCH
AO-A9 R/W
I/O
w
I/O
w
f-
f-
>-
~
en
a:
a:
w
S
w
I
l:J
I
0
-'
10
8
16
~
~
DATA
BUS
16
BUFFER
DATA
BUS
SWAP
BUFFER
MEMORY READ
MEMORY WRITE
8
MEMORY R/W CONTROL
MEMORY
TIMING
TRANSFER ACKNOWLEDGE
BUS CLOCK
LOGIC
t
l
Fig. 5.14 CMOS RAM Board Block Diagram
* MU LTI BUS is trademark of Intel corp.
15-66
• MITSUBISHI
..... ELECTRIC
8
MITSUBISHI LSls
EPROM
(MSL2716K, MSL2732K, MSL2764K)
6.
EPROM
6.1 EPROM Technology
INTRODUCTION
With their ability to be electrically programmed and erased
with ultraviolet light, EPROM (Erasable and Programmable
Read Only Memory) devices have achieved high popularity
for their ease-of-use and are retaining their position as the
target for memory development.
Although the EPROM was originally developed for use
as a microprocessor system debugging ROM, the device has
undergone significant improvements in density, reliability,
and basic process technology as well as cost per bit which
have extended its usefulness beyond microprocessors into
such equipment as cash registers, point-of-sale equipment,
household appliances, entertainment equipment, and a
variety of other fields. Since the introduction by Mitsubishi
Electric of a p-channel 2K-bit EPROM, the development of
n-channel devices has enabled remarkable improvements in
access time, and density in the form of an 8K-bit device.
The development of devices operable from a single power
supply greatly improved ease-of-use of the 16K- and
32K-bit "devices which were to follow. This section will
briefly outline the progress made in EPROM technology
including a description of circuit configuration and notes
on applications.
The Structure and Basic Operation of a Memory Transistor
As shown in Fig. 6.1, increasing EPROM capacity has been
accompanied by changes in the memory transistor structure. The 2K-bit device made use of a P-channel MOS
transistor to form an insulated single-layer polysilicon
floating gate. In contrast to this, devices of 8K-bit capacity
and greater make use of n-channel transistors and two-layer
gate structure with a control gate to which a voltage may be
applied placed over the floating gate. A capacitance
between the control gate and the floating gate form an
.acceleration field for electron injection to the floating gate.
Programming is performed in the following manner. For
programming operations a high voltage is applied to the
drain and control gate. By virtue of the control gate,
capacitance between control gate and floating gate a
channel is formed between the source and drain through
which a current flows. As a result, for high drain voltages
current induced breakdown occurs. The hot-electrons produced as a result of this breakdown phenomena exceed the
high energy barrier and are injected into the floating gate.
By imparting a voltage to these injected electrons the
control gate can have higher threshold voltage than before
injection (refer to Fig. 6.2), and the read voltage may be
applied to the control gate while maintaining an open circuit. This ends the write operation. This applies to the
memory transistors used in presently available EPROM
devices of 8K-bit capacity and over. Fig. 6.3 shows the
programming characteristics (dependency of the threshold
value on the write pulse width) for 16K- and 32K-bit
memory transistors.
The injected charge is located on the floating gate
which is surrounded by a 1,OOOA thick silicon oxide layer
of good insulating characteristics, and is therefore retained
for a long period. It is the retention of this charge which
holds the written data. A significant feature of two-layer
gate structure is the associated increase in density. As
shown in Fig. 6.1, whereas in the single-layer gate an
additional row selection transistor is required, the two-layer
memory transistor eliminates this necessity by having the
control gate serve two functions.
COLUMN
ADDRESS
---1
ADD~~~ ---.CJSELECTION ~
SELECJl~~
GATE
:
I
I
I
I
I
I
:L__ I_ ___ ...JI
I
(a) 2K-BIT
(b) 8K-BIT
(0) 16K-BIT AND ABOVE
Fig. 6.1 Memory transistor construction
f--
~
a:
a:
::J
u
z
«
a:
o
Fig. 6.2 Variation in memory transistor threshold
voltage (VGO: Read gate voltage, both
vertical and horizontal scales are arbitrary)
• MITSUBISHI
"ELECTRIC
15-67
MITSUBISHI LSls
EPROM
(MSL2716K, MSL2732K, MSL2764K)
The introduction of 8K- and 16K-bit devices and greater
was accompanied by improvements of control gate structure. As shown in Fig. 6.1, whereas for the 8K-bit device
the side of the folating gate is completely covered by the
control gate, this is not true of devices of 16K-bit capacity
and greater. It should be noted that while significant improvements in overall capacity has been made, chip size
remains essentially unchanged, the 16K-bit chip size being
merely 8.2% greater than that for the 8K-bit device.
Erasing is done by exposing the device to ultraviolet
light. The electrons on the floating gate receive the
ultraviolet energy, pass through the oxide layer and escape.
The transmittivity of ultraviolet radiation from a low
pressure mercury lamp through polysilicon is low compared
to silicon oxide. For this reason, the ultraviolet energy
reaching the floating gate of 16K-bit and greater memory
devices using transistors without polysilicon sides is larger
than the 8K-bit structure. This results in shorter erase times
for 16K-bit devices and over. Fig. 6.4 illustrates the change
in threshold value by exposure of ultraviolet energy.
I
I-
>
Vpp=25V
50
Fig. 6.3 Dependency of VTH on write pulse width (16K-bit
and 32K-bit)
MEASURED WITH GL-10 2cm AWAY
I
I-
>
20
40
60
80
100
120
TIME (MIN)
Fig. 6.4 Variation in VTH with erasure time
15-68
A
a:
w
t::
(/)
:::J
al
~
1i:
~
~
a:
o
o
X DECODER
I-
Cl.
~
A
«
Y DECODER
CHIP ENABLE
PROGRAMMING
CIRCUIT
OUTPUT ENABLE
CIRCUIT
OE
Vee
0---
GND
0---+-
DoD1D2 D3 D4DSDS D7
DATA INPLJT/OUTPUT
Vpp~
Fig. 6.5 EPROM Block diagram
EPROM Circuit Configuration and Characteristics
Circuit Configuration
Fig. 6.5 shows the block diagram of an ultraviolet light
erasable EPROM. Currently available devices are configured
in 8-bit words with the memory cells arranged in eight
blocks. Input and output is performed in parallel by means
of the signal lines Do '" D7 connected to these eight blocks.
The address signals are divided into column decoder inputs
and row decoder inputs. For a 32K-bit EPROM, the Ao '"
A3 (four lines) address signals are input to the column
decoder while the A4 '" At t (eight lines) address signals are
input to the row decoder, the memory being arranged as a
matrix of 24 (=16) columns by 2 8 (=256) rows.
After decoding, the column signals are input to the
column selection transistor gate which is connected to the
memory cell drain. Finally, the decoder row inputs are
connected to the memory control gates. Sense amplifiers
and data input/output buffers used in read and program
operations are connected to the drains (data lines) of the
memory cells controlled by the column selector transistors.
Almost all of the chip area is taken up by the memory cells,
address circuits, decoders, and data circuits, the remaining
area being allotted to the important control circuits.
These control circuits consist of the chip enable and
output enable circuits. The former controls the power
down operation or programming operations. The latter
circuit controls the enabling or disabling of the output
signal by means of the OEsignal. 16K-bit devices and over
are provided with these two select/unselect control circuits.
The two line control method is very effective for ORconnecting of multiple devices. If only one signal were
allowed to control chip select and unselect, cases could
arise where one chip is enabled for output before the
previous chip goes into the floating state.
• MITSUBISHI
;"ELECTRIC
MITSUBISHI LSls
EPROM
(MSL2716K, MSL2732K, MSL2764K)
As shown in Fig. 6.6, this results in excessive current
flowing and the generation of power supply noise. In
addition, data on the bus is unstable before and after
address changes. This condition is called lithe bus contention problem" and can be eliminated by using the CE as the
chip enable and OE as the output enable signal in a two-line
control mode.
EPROM Operation, Characteristics, and Application Notes.
The basic operations possible with an EPROM are programming, read, and erase. These operations will be discussed
with respect to 16K- and 32K-bit devices along with some
precautions for use. Table 1 summarizes a comparison of
the characteristics of EPROM devices currently available.
(1) Programming Operations
The normal state of all cells for an EPROM device when
shipped or after erasure is "1", programming operations
change the memory cell contents to O. Programming
operations are performed in groups of 8 bits (one word).
After applying the programming voltage to the programming pin and selecting the program mode, the address data
is set up. Next, a programming pulse of the required width
is input. The active state of this pulse depends on the device
(for instance, for 16K-bit devices the pulse is active high
while for 32K-bit devices it is active low), so that care
should be taken when generating this pulse. Although it is
often thought that the higher the programming voltage and
the wider the programming pulse, the more effective the
programming operation will be, the device characteristics
dictate that the best programming will be achieved by setting these values to the central specification values. In
particular, the maximum allowable voltage for programming that may be applied to the Vpp pin is 26V. Care must
be taken that the Vpp supply doesn't overshoot the 26-volt
maximum specification. Programming for both 16K· and
32K-bit devices can be performed in any arbitrary order,
further simplifying the programming operation.
------------------11
Vee
i
1
1
1
1
1
I
--.J
()j\JI
1
1
i
1
1
1
I
I
r---------------
II
Vee
I
I
I
1
I
1
OR.CONNECTED I
/1
" I
"
I
1
1
I
I
1
I
1
I
I
I
I
I
I
I
I
I
I
1
I
-----------------~
1
Table 6.1 Comparison of Available EPROM Devices
MEMORY
CAPACITY
(BITS)
2K
(2S6X 8)
3K
(1024X 8)
16K
(2048X 8)
32K
(4096X8)
TYPE
MSL 1702AS
MSL2708K
MSL2716 K
MSL2732K
CHANNEL
TYPE
p
n
CHIP AREA
14.2mm2
17.8mm 2
19.3mm 2
22.Smm 2
1000 ns
4S0ns
4S0ns
4S0ns
600mW
800mW
S2SmW
787mW
0.3mW
O.lmW
0.03mW
0.02mW
+S, -9V
+S, -S,
+ 12V
+SV
+SV
ADDRESS
ACCESS
TIME (MAX)
POWER
DISSIPATION
(MAXI
POWER
DISSIPATION
PER BIT
SUPPLY
VOLTAGES
n
n
ADDRESS
OE
DATA
OUTPUT
Fig. 6.7 Read timing diagram
(2) Read Operation
The read mode is enabled by lowering the program voltage
and using the chip enable signal to select the chip, and the
output control signal to enable the output of the memory
contents at the selected address. The chip enable signal
serves also as the power down signal, enabling an extreme
limitation on power consumption for the non-selected
periods. Access time is specified in terms of chip enable,
address, and output enable access times, the power down
feature making the chip enable access time generally the
longest. Operating conditions and output timing should be
carefully considered as high temperatures and excessive
output loads have an adverse affect on access time. Fig. 6.7
shows the read timing for 16K·bit and 32K-bit devices with
Fig. 6.8 and Fig. 6.9 giving the chip enable access time
dependency on temperature and load capacitance.
I
I
I
I
I
I
I
I
I
1
L
______________ _
Fig. 6.6 Fighting for an OR-connected bus
• MITSUBISHI
.... ELECTRIC
15-69
MITSUBISHI LSls
EPROM
(MSL2716K, MSL2732K, MSL2764K)
(3) Erasure
Erasure is performed by exposing the chip to ultraviolet
light. Fig. 6.4 shows the change in memory transistor
threshold value with relationship to ultraviolet radiation.
The erasure time should be selected to allow for variations
in the memory transistor characteristics. Fig. 6.10 shows
the relationship between the ultraviolet radiation time and
the number of bits erased. Verification of erasure by means
of a PROM should not be assumed to indicate that the
EPROM is sufficiently erased. While the required erasure
time depends upon factors such as the type and condition
of the lamp used and the distance to the device being
erased, the actual erasure procedure should be continued
for a period of five times the time required to erase all cells
as verified by a PROM programmer. Generally, for 16K·
and 32K-bit EPROMs, the erasure time for a GL·10 lamp
2.5cm away from the device is between 15 and 20 minutes.
The erasure characteristics for 8K-bit EPROMs differs
from those for 16K -bit and greater capacity for structural
reasons, with the differences extending to the degree of
influence of sunlight and fluorescent lighting on the
inadvertent erasure of data. To prevent such long term
ambient radiation from affecting electrical characteristics,
the use of a seal to cut out such radiation for normal use
is required.
500
c
w
:2
400
i=
(/)
(/)
w
u
u
300
SPB
EPA
SPA
2
27162800 16 ~80016
2732 ~ 1000 16 .~ 1000 16
A bytes commands after
address set command
should provide with AO
input low·level.
PASS = ON
When mode is set correctly.
(Mode request LED
turns off.)
2716 Mode
2732 Mode
Ao
[2J
NOTES
FAIL
PASS
Mode set
Defines the start
address (SPA) and th8
end address (EPA)
of programing
EPROM
LED DISPLAY
CODE
DESCRIPTION
PASS = ON
If EPROM is erased.
(i.e. All data are FF I6 )
FAIL = ON
if EPROM is not erased.
PASS = ON
When programming
finishes completely.
FAIL = ON
If it is not able to write
correctly in the EPROM
address.
(SPA- EPA)
0
z
Writes the data to the MSB
LSB
EPROM which are sent
1 1 10111010101 0 101
from master CPU and
rerifies the written
data if they are
correctly programmed.
«
:;:;
:;:;
0
u
=
4
EPROM write
LSB
5
Verify
Checks the programmed MSB
EPROM if it is written
11111011101010101
CD
Ao
OJ
Executes the
commands 3 , 4 , 5
au.tomatically.
6
LSB
MSB.
1/;
Write data
buffer full
-en
i:
r-
FAIL = ON
PASS = ON
I f the programed data are
When the programed data
are equal to the sourc:e data. not equal to the source data
N
...en.....
11111010101010101
I
QJ
PASS = ON
When there is no error
In 3 and 5 command.
I
~
FAIL = ON
When there are any errors
i:
In 3 and 5 command.
r-
en
N
I
LSB
Transfers the EPROM's MS6
data where are difined
11111110101010101
SCA and ECA to the
master CPU.
After providing Copy command,
it is necessary to provide following
Indicates if write
::J
After providing thiS command, PRPG compares
the programed data with the source data of
rT)aster CPU.
Ao
Ao
QJ
4 bytes of SCA and ECA.
~I
~
After providing this command, PRPG generates
EPROM programming timing pulse.
I'""OC'"
Automatic
write
7
Copy
AO
data buffer in the
PRPG are full or not.
II
MSB
-1-1 -1-1
LSB
"
LSB AD
"(SeAl HIGHER
~
2nd byte
(SCA) LOWE R
0
3rd byte
(ECA) HIGHER
0
4th byte
(ECA) LO,WER
AO
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Fig. 6.13 2716 Programming timing
Vpp=OV
Vpp/OE
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Fig. 6.14 2732 Programming timing
• MITSUBISHI
;"ELECTRIC
15-75
U"1
I
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IN
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CONVERTER
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:
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Or-
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MITSUBISHI LSls
ERROR DETECTING AND CORRECTING
7.
Table 7.2 Valid Word and Error Word Combinations
Error Detecting and Correcting
1. Introduction
The reliability of semiconductor memory devices is extremely high, so that for normal operation performance can
be guaranteed without the use of special correcting circuits.
However, for applications requiring even greater reliability,
or in which the large number of ICs used in the system
causes a reduction of the overal·1 MTBF, some form of data
error correction is requried. This section will examine errors
in memory devices and techniques for detecting and
correcting them.
2. Error Checking Concept and the. Redundancy Code
A code which can be used for error checking consists of the
following code of added bits to the normal data word.
I
I
I
I~:__________M__BI_T_S~~~-N-B-I-TS-_-_-_~~:IE:====_K_B_IT_S_--=:j
~'
__
WH ERE : N = K + M
Fig. 7.1 . Error check code format
The first M bits represent data, and will be referred to as
the data word. The remaining K bits are not directly related
to data, and are called redundancy bits or the redundancy
word. The combination of these two portions form a N bits
total word. Such a combination of a data word and a
redundancy word is known as a redundancy code.
As an example, let us take the case of M=2 and K=1. As
shown in Table 7.1, there are four possible combinations of
data word.
Table 7.1
DW
Valid word
0
0
0
0
1
0
1
0
1
0
0
1
1
0
1
0
0
0
1
1
1
1
1
0
1
1
0
0
1
1
1
0
0
1
1
1
0
1
1
1
1
0
0
0
1
0
Ro
0
0
0
0
1
1
1
0
1
1
1
0
Error words
Valid word
0
1
2
4
,3
2
1
7
5
4
7
1
6
7
4
2
A valid word
is one with
no errors.
From Table 7.2 and Table 7.3 we see the following
(1) The set of valid words contains no error words.
(2) Any valid word differs from other valid words by not
less than two bits.
Basically the above two statements are the same.
Specifically, valid words differ from each other in not less
than two bits so that single bit errors are not found in valid
data. In th is manner error check is to detect a (h-1) bit
error by making valid words differ from each other by h
bits to select proper redundancy words. (Seleting thus the
set of valid words which does not include error words
differing not less than (h-1) bits, so we can distinguish these
error words from valid words.) The value h for such an
error check code is known as the Hamming distance. When
this relationship is expressed in set theory notation we have
the representation of Fig. 7.2.
S
R
RW
Do
0
Table 7.3 Decimal Notation Valid and Error Words
Redundancy Code Example
D,
Error words
0
DW
: data word
RW
: redandancy word
o
: Total word set
: Valid word set
: Error word set
W
R
S
=
W
R
=
=
(000,001,010,011,100,101,
110,111 )
(000,011,101,110)
(001,010,100,111)
Fig.7.2 Parity codes classification
To this data word is added a redundancy word as shown in
Table 7.1, the redundancy bit Ro being given by the
following expression.
Ro = Do E9 D2 ........................ (1)
where E9 is the exclusive-OR operator
l'Jext, let us consider the case for which one of the bits is
different, that is, the case of a single bit error. Since the
word has three bits, for each word there are three possible
error words making a total of 12 possible error words. This
is summarized in Table 7.2.
Next let us examine the error word. For the error words
sbown in Table 7.3, the difference from the valid word is in
order across the row the first bit, the second bit, and finally
third bit. While the same word exists for the error words of
any particular row, it is impossible to know which row a
particular error word belongs to or phrased differently,
although the fact that the word is an error word is
determinable, which bit is in error must be known or else
the code cannot be used to correct the error. This type of
error check is known as error detection.
II!!III
_ _ _ _ _ _ _ _ YiII
• MITSUBISHI
.... ELECTRIC
15-79
MITSUBISHI LSls
ERROR DETECTING AND CORRECTING
As the next example, let us take the case where M=1 and
K=2. For this example the data words are shown in Table
7.4 and it can be seen that there are only two types of data
words with the redundancy word determined by equation
(2).
Table 7.4 Error Correcting Code Example
DW
RW
Do
KI
Ko
0
0
0
1
1
1
Ko = Kl = Do ........................... (2)
If as in the previous example, we consider a single bit error
word, we can derive Table 7.5 and Table 7.6 as shown
below.
Table 7.5 Single Bit Error Word Combinations
Valid word
Error words
000
o
0
o
0
1
1
1
1
1
1
1
Table 7.6 Decimal Notation Single Bit Error Words
Error words
Valid word
0
1
7
6
4
2
I
5
I
An actual circuit implementation of such an error correction code would involve determining whether the word
belonged to W, Rl, R2, or R3. If the word was found to
belong to the R set, the error correction procedure involves
simply inverting the bit corresponding to the error word
set.
3, Parity
As discussed in the previous section, some error check
techniques involve error words which have duplication and
can only be used to detect errors. One particular type of
error detection scheme used to detect single bit errors is
called parity. The parity error detection method uses a
redundancy word one bit long (Ro) regardless of the length
of the data word. Ro is derived in the following manner.
Ro
Do
Ell
D1
Ell
D2
Ell
.... Ell
Dm -
Ro = Do
Ell
01
Ell
O2
Ell
•••• Ell
Dm - 1 ............. (4)
(3)
The single bit derived in equation (3) represents the number
of 1's in the total word is even and is termed even parity
while equation (4) is referred to as odd parity.
Fig. 7.4 shows the example of an 8-bit data word, using
an M74LS280P (SN74LS280) as the parity generator. The
M74LS280P has ~E and ~o as parity outputs and inputs
A through I. The input to output relationship being defined
by the following expressions.
3
As can be seen from the table, this time there is no
ambiguity in the error words. Therefore, the valid word can
be obtained merely by looking at the error word. For
example, if the word were 001, 010, or 100, the valid data
would be clearly 000. However, if the error word were 110,
101, or 011, the original valid word would have been 111.
Approaching this differently, let us assume that the word is
001 or 110. Since the error word has the Ko bit different,
reversing the differing bit turns 001 into 000 and 110 into
111 which are the valid data words. The same procedure
applies to the other error words which are possible.
In this manner, a redundancy word is used to eliminate
ambiguities in the error word and enable the derivation of
the valid word by examining the error word. This procedure
is known as error correction. Expressed in terms of set
theory symbols we have the relationships shown in Fig. 7.3
: total word set
W
: valid word set
RI
: bit 1 .error word set
R2
: bit 2 error word set
R3
: bit 3 error word set
W = (000, 111)
RI = (001,110)
R2 = (010, 101)
R3 =(100,011)
Fig.7.3 Error correction code relationships
15-80
1 .............
or
• MITSUBISHI
.... ELECTRIC
MITSUBISHI LSls
ERROR DETECTING AND CORRECTING
MULTIPLEXED ADDRESS
A6
A6
~
~
RAS CAS R/W
~
~
~
~
RAS
A5
A4
A3
A2
Al
AD
RAS
CAS
CAS
R/W
R/W
o-
0
0
0
0
o-
0
0
0
0
0
a
~
Do - 0,
0
0
0
o
0
0
0
U
U
a
0
0
I~
~
~A
~B
~C
~D
~E
0
0
0
0
0
0
0
0
0-
Os
~
Note. Timing for CAS and R/W is as follows.
,
CAS
~H
I
t>------n
--
I
I
I
I
~
J
Zo
I
I
I
I
I
itOns min
I
F
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\
R/W
L...-LS280
R/W
0
0
Ro
ERROR RESET
o
0
U
0
0
_
0
a:
~
CAS
o-
U
R/W
R/W
0
0
I Dns min
,I I-
PARITY ERROR
Q
rt
Fig. 7.4 Parity circuit example
LE = A Ell B Ell C Ell DEllE Ell F Ell G Ell H Ell I
..... (5)
La = A Ell B Ell C Ell DEllE Ell F Ell G Ell H Ell I
..•.. (6)
For write operations, since G 1 makes the I input 0, the
parity bit ROR is written into memory with a value given by
the following expression.
Row
= Low = Dow
Ell D,w Ell ·········EIl D,w
..... (7)
where Dow '" D 7W is the write data
Next, for read operations, all of the read data (including
parity) is input to the M74LS280P. Therefore the output is
given by the following expression.
The JK flip-flop does not change states at the rising edge
of CAS. If, however, there is any single bit error in
DOR"'D7R or ROR , the following . expression is derived
from equation (7) .
ROR = DOR Ell D'R Ell
......... Ell D7R
..... (10)
When this is substituted for equation (8), we have the
following.
Lo R
= R0 R +
R0 R
=
1
..... (11)
Upon the rising edge of CAS, the JK flip-flop output goes
to 1 indicating the presence of an error.
..... (8)
If no errors are present in Dor"'D7 R, then they become
equal to Dow"'D7W and Row, equation (8) replacing (7) .
LOR
=
ROR + ROR
=0
..... (9)
• MITSUBISHI
.... ELECTRIC
15-81
MITSUBISHI LSls
ERRO~.
DETECTING AND CORRECTING
4. Single-Bit Error Correction
The detection and reversal (correction) of a single bit error is
referred to as single-bit error correction (SEC). For SEC to
be possible the Hamming distance for the total word "!lust
be a minimum of 3-bits and the following equation must be
satisfied. Examples of allowable values of M are given in
.
Table 7.7.
2K -:.1 ~ N
where N = M + K
Table 7.7 Allowable M values
21
20
19
18
17
015 014 013 012
011
Redandancy word
12-26
6
27-57
7
58-120
8
121-245
16
check bit weight, from which the location of the error bit
can be determined. To implement this scheme a 21-bit total
word is generated.
15
14
13
12
11
10
9
010
09
Os
07
06
05
04
R4
RO
Weight of
5
..... -(12)
Bit number
redundancy bit
~
M
4-11
4
SEC is an extension of t~e parity concept. For instance,
let us take the case of M = 16. From the Table we see that
K = 5 from which. N = 16 + 5 = 21. In single-bit error
correction, each bit of the redundancy word is given.a
Data word
~
K
X
R1
R2
X
X
X
X
X
X
R3
R4
X
X
X
X
X
7
6
5
03
D2
01
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
4
3
X
X
X
X
X
X
1
R1
Ro
X
X
X
2
Do
R2
R3
X
X
8
X
X
X
X
X
Fig.7.5 SEC Weighting
Whereas for parity the Ro has the weight for all bits,
SEC, as shown in Fig. 7.5, assigns weights (2 bits) Ro....... R4
in a binary coded fashion. Specifically the weights are given
in equations (13) through (17) below.
Ro = Do E9 Dl E9 D3 E9 D4~ D6· E9 D8 E9 DlO E9 Dl1
E9 D13 E9 D13 ffi DIs "
..... (13)
Rl = Do E9 D2 E9 D3 E9 Ds E9 D6 E9 D9 E9 DlO E9 D12
E9D13
..... (14)
R2 = D1 E9 D2 E9 D3 E9 D7 E9 D8 E9 D9 E9 DlO E9 D14
E9D 1S
..... (15)
R3 = D4 E9 Ds E9 D6
(B
D7 E9 D8 E9 D9 E9 DlO
This indicates the presence of an error at the 11th bit.
Therefore, the error can be corrected by merely reversing
this bit (to 1 if it were 0 and 0 if it were 1) to obtain
correct data. In a similar manner, if an error occurs at other
bits the position will be indicated in binary code by
~ORO""~OR4' allowing reversal of the bit after decoding of
the position. These ~ORO through ~OR4 are known as the
syndromes.
While we have examined single-bit error correction, for a
variety of reasons actual systems make use of double error
detection and single-bit error correction.
..... (16)
..... (17)
In this manner the redundancy bits Ro through R4 are
generated and written into memory along with the data bits
Do to DIs. For read operations, ~ORO"""'~OR4 are examined as was explained for parity checking. Should there
be no errors, ~ORO = ~OR1 = ~OR2 = ~OR3 = ~OR4 = O.
Let us assume that a single-bit error occurs, for instance at
the 11th bit (D w6 ). Ro, R1 , and R3 are used as check bits
for the 11th bit so that from equation (13) through (17) we
have ~ORO = ~OR1 = ~OR3 = 1 and ~OR2 = ~OR4 = O.
~ORO LOR1 ~OR2 ~OR3 ~OR4
o
15-82
o
~
decimal 11
• MITSUBISHI
.... ELECTRIC
MITSUBISHI LSls
ERROR DETECTING AND CORRECTING
5. Single· Bit Error Correction/Double-Bit Error Detection
Table 7.8 Allowable M values
The correction of 1-bit errors and detection of 2-bit errors
is known as single-bit error correction/double-bit error
detection (SEC-DED). To implement such a SEC-DED
scheme, the total word Hamming distance must be at least
4-bits and the following equation must be satisfied.
Table 7.8 gives examples of K and M values.
1~ N
2
where N = M + K
K
~
K
- 1 -
M
~
1-3
4
5
4-10
6
11- 25
7
26- 56
8
57-119
..... (18)
In SEC, weights are assigned so that the syndrome bits
Ro"'R K - 1 are expressed in binary code to indicate directly
the position of the error bit. In SEC-DEDh'owever, for a
17
16
15
14
13
12
11
10
9
8'
7
015 014 013 012 011 010
09
08
01
06
05
D4
03
02
01
DO
21
22
Bit number
Data word
number of reasons, the weighting is assigned as shown in
Fig. 7.6 For this reason, decoding of the syndrome is
required for error position determination.'
20
19
18
Redundancy word
X
Ro
X
X
X
R1
Weight of
R2
X
X
redundancy hit
R3
X
X
X
X
R4
X
X
X
X
X
X
X
X
X
X
X
X
X
Rs
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
6
.5
4
3
2
1
Ro
R1
R2
R3
R4
Rs
X
X
X
X
X
X
X
X
X
X
Fig. 7.6 SEC-OED Weighting
Ro = Do
$
O2
$
Os
$
D7
$
D9
$
010
Rl = Do
$,.
Dl
$
04
$
06
$
D8
$
D9
$
R2 = Dl Ell D2 Ell
03'~
08
R3 = D3
'$
04
$
Os
$
0 11
R4 = 0 6
$
07
$
08
$
D9
Rs
$
Dl
E9
O2
$
0 3 $ 04
=
Do
.~
010
$
$
D 12
010
D12
'$
$
D 13
Ds
$
$
$
DIS ... (19)
$
D14 ... (20)
$
D14
$
D13
0 11
$
0 11
$
$
0 12
06
$
0 15 0>.(21)
$
0 14
$
D 1S .. (?2/
$
D 13 ... (23)
D7
... (24)
From equations (19) through (24) we have the following
expression.
Co = Ro
= 00
$
$
D9
$
Rl
$
R2
$
R3
$
R4
$
Dl $ D2 $ D3 $ 0 4 $ Ds
DIO $ 0 11 E9 0 12 $ D 13
$
Rs
$
$
D6 $ D7 $ 0 8
D14 $ DIS ...... (25)
The righthand side of equation (25) is the same as the
righthand side of the parity expression. Therefore, for read
operations, examination of CDR is given by the following.
CDR =1: 0RO E91: 0R1 $1: 0R2 $1: 0R3 $1: 0R4 $1: 0R5
Examination of this value indicates whether or not a 2-bit
error is present (the parity can only indicate whether the
number of error bits is odd or even. Therefore it is
ineffective for more than 2-bits of error. I n contrast to this,
the SEC-OED scheme provides a no error/l-bit error
syndrome detection capability which detects an even
number of error bits as a 2-bit error).
• MITSUBISHI
"ELECTRIC
15-83
MITSUBISHI LSls
ERROR DETECTING AND CORRECTING
Table 7.9 Summary of error types
LOR5
L04
L03
LOR2
LORI
LORD
CDR
Remark
1
0
0
0
0
0
0
No error
0
1
0
0
0
0
1
RR5
error
0
0
0
0
0
0
1
RR4
error
0
0
1
0
0
0
1
RR3
error
0
0
0
1
0
0
1
RR2
error
0
0
0
0
1
0
1
RRI
error
0
0
0
0
0
1
1
RRO
error
1
0
0
0
1
1
1
DRO
error
1
0
0
1
1
0
1
DRI
error
1
0
0
1
0
1
1
DR2
error
1
0
1
1
0
0
1
DR3 error
1
0
1
0
1
0
1
DR4 error
1
0
1
0
0
1
1
DRS error
1
1
0
0
1
0
1
DR6 error
1
1
0
0
0
1
1
DR7 error
0
1
0
1
1
0
1
DRS error
0
1
0
0
1
1
1
DR9
0
1
0
1
0
1
1
DR 10 error
0
1
1
0
0
1
1
DRll error
0
1
1
1
0
0
1
DR12 error
0
1
1
0
1
0
1
DR 13 error
0
0
1
1
1
0
1
DR 14 error
0
0
1
1
0
1
1
DRIS error
0
2 bits error
Varies depending upon the error bit (all zeroes cannot occur)
error
Table 7.9 shows a summary of read error detection for
various types of errors.
Table 7.9 applies to errors of 2 bits or less.
Fig. 7.7 is the circuit implementation for the expressions
of equation (19) through (25). In actual systems, the
detection of an error results in data being latched and
corrected, whereupon it is rewritten into memory and the
control circuits for these operations would be required as
well.
The decoding of LORO through LOR5 by the SN74S138
and SN74S02 is shown in the following Table 7.10.
Table 7.10 1;ORO '" LOR5 Decoding
LORS
LOR4
LOR3
LOR2
LORI
LORD
L OR3-L ORS
Octal
L ORO-L OR2
Octal
1
0
0
0
1
1
4
3
Do
1
0
0
1
1
0
4
6
Dl
·1
0
0
1
0
1
4
5
D2
1
0
1
1
0
0
5
4
D3
1
0
1
0
1
0
5
2
D4
1
0
1
0
0
1
5
1
Ds
1
1
0
0
1
0
6
2
D6
1
1
0
0
0
1
6
1
D7
0
1
0
1
1
0
2
6
D8
0
1
0
0
1
1
2
3
D9
0
1
0
1
0
1
2
5
DlO
0
1
1
0
0
1
3
1
Dll
0
1
1
1
0
0
3
4
D12
0
1
1
0
1
0
3
2
D13
0
0
1
1
1
0
1
6
D14
0
0
1
1
0
1
1
5
DIS
15-84
• MITSUBISHI
~ELECTRIC
Data word
to memory
Do - D.c. Rn - R
Do - DIs to CPU
3xS280
Do
D2
Ds
D,
D9
DIO
Dl1
DIs
S86x4
D3
D.
Ds
Dl1
DI2
DI3
Do
DI
D2
D3
D.
Ds
Ro
,.
,.,
Do
DI
D4
D6
D8
D9
D13
DI4
11'11:
r-_
RI
ncn
.... e
DI
D2
D3
D8
D lo
11'1 ....
::am
niii
:5
C
D.
E
D'
D8
Dg
Dlo
Dl1
DI2
DI3
DI4
DIs
ZE
F
G
H
Zo
:::a
:::a
o
:::a
,.,-t
,.,
~
!l
-z
G)
R/W
~
Z
~
ZE
S08
1 bit error
2 bit error
Data latch
(J"I
Data read enable
I
00
(J"I
Fig. 7.7 SEC-OED circuit example
II
No error
n
:::a:::aU:
,.,c::
0:.:
n!
--t~
ZrG)~
MITSUBISHI MICROCOMPUTERS
MELPS 4 PROGRAM LIBRARY
SUBROUTINES
DESCRIPTION
stored on another page and branched to. Page 14 can be
Examples·of subroutines for the MELPS 4 single-chip 4-bit
used without any problems for programs other than subroutines.
microcomputer are described below. The subroutine calling
sequence is also explained.
Mnemonic
Subroutine
conversion by
• A-D
successive approximation.
ADC1
• A-D conversion by
sequential comparisons.
ADC2
Program
list reference
Fig. 5
CF,CFM
RSF
Fig. 11
Fig. 11
• Left-shift file.
• Transfer of file.
LSF
TF
EXF
Fig. 11
Fig. 12
• Exchange of file.
Fig.
Fig.
Fig.
Fig.
13
13
13
13
• Decrement memory.
• Skip non-zero memory.
INM
OEM
SNM
• Skip non-zero file.
BCD addition of files.
BCD subtraction of file.
SNFMASNFMI
ADF
SBF
Fig. 16
Fig. 17
Fig. 17
SCF
Fig. 17
•
•• Sign change of file.
BRANCH
INSTRUCTION
Fig. 4
file.
•• Clear
Right-shift file.
• Increment memory.
Fig. 1 Subroutine call instructions
SUBROUTINE CALL
INSTRUCTION
~BA
PAGE
O'
ON·PAGE
BRANCH
r-
PAGE
~~ci~IDE.
(
1
BL. BLA
a
(
I
i
i
PAGE
14
BM. BMA
B. BL
PAGE
15
CALLS A SUB·
BML. BMLA ROUTINE STORED
OUTSIDE THE PAGE
BRANCH
I
I
I
I
I
II
I
~r;:.:c'l
CALLS A SUB·
ROUTINE STORED
ON PAGE 14
BM. SMA
I
~
I
I
I
SUBROUTINE
BRANCHES TO, ·BML. BMLA ~~~L~N'E ~~~·RED
PAGE 15
OUTSIDE
THE PAGE
Note 1 The Band BA instruction will branch on page 15.
and the BM and BMA instruction will branch on
page 14 if executed without executing an Rl RTS.
BL. BLA. BML or BMLA instruction after the
execution of a BM or BMA Instruction.
1.2 Consecutively described skip instructions
1 . Effective Subroutine Program Procedures
If either arithmetic LA or RAM addressing LAX instruc-
These procedures are eff.ective in reducing memory size of
tions appear in sequence, only the first instruction will be
executed and the successive same instructions are skipped.
the program and increasing program execution' speed.
Convenient instructions that are used in subroutines are
I t is useful for clearing files as shown in Fig. 7.
discussed.
1.3 In-RAM file designation changing instructions
The following four instructions:
TAM
(where, j = 0-3)
XAM
(where, j = 0-3)
1.1 Subroutine call instructions
The following four instructions can be used as subroutine
call instructions:
BM, BMA, BML, BMLA
X A MD j (where, j
The BM and BMA instructions are one-word instructions
X A MI
= 0-3)
j (where, j = 0-3),
that can call all the subroutine stored in page 14. These
automatically change the contents of the X register depend-
instructions are designed to designate page 14 automatically by hardware action. If the entrance of a subroutine is
made by the immediate modifier j (j = 0-3). Its designat-
ing on the contents of the Z register. File designation is
programmed on page 14, the subroutine can be called by
ing rules are shown in Table 1. These instructions are very
these one-word instructions, which reduces programming
useful for shifting and transferring data within files.
memory requirements.
When the 8M, BMA B or BA instruction is executed on
page 14 (in other words, when any of these instructions are
Table 1 In-RAM file designation changing rules using the
TAM, SAM, SAMD and SAMI instructions.
used on page 14) the BM and BMA instructions will operate
~
as a branch on page 14 and the Band BA instructions will
operate as a branch on page 15. When any of the RT, RTS,
Z register
Vatue of
0
BL, BLA, BML and BMLA instructions is executed, this
1
special function is cancelled and BM, BMA, Band BA no
longer have a special function. That is, the BM and BMA
2
instructions operate as subroutine call instructions on page
14 and the Band BA instructions as on-page branch instructions. Details of these functions are explained in Fig. 1.
3
In case the whole subroutine cannot be stored on page
14, only the entrance to the subroutine should be stored on
'page 14. The balance of the subroutine programs should be
15 -- 86
(Z)=o
(Z)=1
J
•. MITSUBISHI
.... ELECTRIC
No change
No change
FO~F1
F4~F5
F2~F3
F6~F7
FO~F2
F4~F6
F1~F3
F5~F7
FO~F3
F4~F7
Fl~F2
F5~F6
MITSUBISHI MICROCOMPUTERS
MELPS 4 PROGRAM LIBRARY
SUBROUTINES
2. A-O Conversion Programs
A-D conversion is performed by comparing the input
Fig. 2 A-O conversion subroutine flow chart for
the successive approximation method
voltage of the analog input port K with Vref, which is
generated by the D-A converter, and checking the contents
of the H-L register until they at are the same level. Register
Y designates the port K input. For example, the input Ky is
selected when the contents of the Y register are y.
There are two methods, successive approximation and
sequential comparison, for A-D conversion.
selected by means of the program.
Either is
2.1 Successive approximation method
Program Operation
In this method, the input voltage in the analog input
port K(Yl is converted to an 8-bit digital value using the
successive approximation technique, and the result is stored
in the H-L register.
Its program flow is shown in Fig. 2. The H-L register is
IC) IS INITIALIZED TO 7
THE MOST SIGNIFICANT
BIT OF THE H-L REGISTER
IS DESIGNATED BY (C)
THE BIT OF THE H-L
REGISTER THAT IS
DESIGNATED BY IC)
IS SET TO "1"
first cleared, and then the C register is set to designate the
most significant bit (MSB) of the H-L register. When the
instruction CPA is executed after ''1'' has been set in the
MSB, the input voltage in the analog input port K(y) is
NO(IVK(Y)I
> IVrell)
compared with the D-A conversion output V ref.
When
I V ref I > I V K'r-Yl.1
is met during the execution of the next instruction (during
the execution of the NOP instruction), J(Yl is set to "1".
Otherwise it will be reset to "0"
YES (IvK(Y)!
If
> I vret!)
IVref I > IVKIY) i Le.J(y) = 1
the MSB of the H-L register is reset to "0:'.
If
IVrefl< IVKIY) I Le.J(y) =0
the MSB will remain as "1 ". Then (C) is decremented
THE BIT OF·THE H-L
REGISTER.THAT WAS
DESIGNATED BY IC)
IS RESET TO "0"
by 1, and the above procedure is repeated eight times until
reaching the least significant bit (LSB).
When using ports other than those used for analog quantity
measurements such as when using port K as a key input
port and applying a low level from DREF, program statements '21 and 22 shown in Fig. 4 must be changed as shown
below. The original program functions are retained.
CPA
NOP
CPAS
NOP
CPAE
This successive approximation method has a constant
RETURN
conversion speed-approximately 0.6ms at 600kHz-and
thus it is suitable for examining analog value with large
variations and detecting different analog values from
multiple channels.
Subroutine Call
The subroutine is called after designating the terminal of
the analog input port K and the bit position of the J
register with the Y register. A-D conversion is performed
• MITSUBISHI
..... ELECTRIC
15-87
MITSUBISHI MICROCOMPUTERS
MELPS 4 PROGRAM LIBRARY
SUBROUTINES
for the port Ko in the following example.
LXV 0,0
8M
Fig. 3 A-O conversion subroutine flow chart for
the sequential comparison method.
ADC1
2.2 Sequential comparison method
Program Operation
In this method, the input voltage in the analog input port
is converted to an 8-bit digital value using the
K(y)
sequential comparison technique, and the result is stored
in the H-L register.
Its program flow is shown in Fig. 3. First the appropriate
contents of the H-L register are D-A converted, and
the Vref is compared with the input VK(Y).
If
I Vref I > I VK(Y) I then (CY) is set to"l"
and if
IVref I < IVK(Y) I
then (CY) is reset to "0"
The H-L register is decremented when (CY) is
decreases
I Vref I
by
and
VREF/256. Otherwise, the H-L
register is incremented, when (CY) i~ 0, and increases
I Vref I by VREF/256. The comparison will come to an
end when the magnitudes of I V ref I and I V K(Y) I are exchanged.
The contents of the Hand L registers are stored in the
A register, and the contents of the A register are either
incremented or decremented. First, the low-order 4 bits
(L register) are incremented or decremented, followed by of
the high-order 4 bits (H register), and then the L register
again.
To increment the A register, 1 is added to that register.
Testing whether the (A) is 15 or not is performed by the A
instruction and by checking if the carry is 1. To decrement
the A register, 15 is added to the A register. Testing whether
(A) is 0 or not is performed by the A instruction and by
checking if the carry is O.
It will test (H) = 0, when Vref =-fssVREF is met, and
will test (H) = 15, when Vref =~VREF is met.
Subroutine Call
The subroutine call is executed after designating the
terminal of the analog input port K and the bit position of
the J register with the Y register. A-D conversion is performed for the port Ko in the following example. However,
it will reduce conversion time if the subroutine is called
after setting an expected value in the Hand L registers, in
cases where the digital value can be anticipated.
LXV
0,0
(H) ~ expected val ue
(L) ~ expected value
8M
15-88
ADC2
.• MITSUBISHI
;"ELECTRIC
MITSUBISHI MICROCOMPUTERS
MELPS 4 PROGRAM LIBRARY
SUBROUTINES
Fig. 4 ADC1 program list
2
3
4
*MAX
S
6
7
8
9
10
MIN
J
SIGN
*
12
00
01
la
02
19
03
20
04
21
05
22
06
23
07
24
08
25
09
26*WO*OA
27
013
28
EOU
EQU
EOU
ECiU
7
12
0
12
MELPS 4
(
LIBLA~Y
NO.1
)
##/111######*
*************************************************************
13
17
E,O
*U### ##11##11
11
14
15
16
GRG
*
OBO
019
059
057
04.2
008
000
029
052
009
104
044
*SUBR: ADCl 8-BIT A-D CONVERSION. BY SUCCESSIVE APPROXIMA.*
************************************************************
AD C1
LAO
CLE AR A, (A) : 0
TL A C LE AR L, (L): 0
TH A C LE AR H, (H): 0
LC7
(C)=7
ADCI0 SHL
SET H-L, BIT IS ASSIGNED BY (C)
CPA
COM PARE PORT K 8. VREF
NOP
SET J IF ABS VREF.GT.ABS VK(Y)
SlJ
SKIP IF (J(Y»:O
RHL
RES ET H-L
DEC
(C)=(C)-1,SKIP IF (C)=O
BM
ADCI0 REPEAT 8 TIMES
RT
END OF ADC1
*
Fig. 5 ADC2 program list
29
30
31
32
OC
33
00
34
OE:.
35
OF
36
10
37
11
38
12
39 *WO* 13
40
14
41
15
42
43
16
44 *WO*l7
45
11:3
46*WO*19
47
1A
48*WO*lB
49
lC
50
10
51*WO*lf
IF
52
53
20
54
21
55 *WO* 22
2.3
56
57
24
58*WO*25
59
26
27
60
61
28
29
62
6.3*WO*2A
64
65
008
048
029
049
008
018
029
llA
02F
044
OA1
126
019
110
02F
lID
044
OAF
118
019
058
OAF
124
OBO
059
110
019
051:3
OAl
OBF
124
************************************************************
*5UBR: ADC2 8-BIT A-D CONVERSION. BY SEOUENTIAL COMPARISON*
************************************************************
ADC2
CPA
GaM PARE PORT K 8. VREF
RC
(CY )=0
SZJ
SKIP IF (J(y»=O
SC
( CY ) =1
ADC2l CPA
COMPARE PORT K 8. VREF
XAL
(A) EX (L)
SZJ
SKIP IF (J(Y»=O
BM
ADC23 ACTS AS INSTRUCTION g ON PAGE 14
SZC
SKIP IF (CY)=O
RT
RETURN,CONVERSION FINISHED
*
ADcn
ADC23
ADC24
A
1
BM
TLA
BM
SlC
BM
RT
ADC26
A
15
ADC22
(L>
ADC21
ADC24
BM
TLA
XAH
ADC26
=( A)
Acrs AS INSTRUCTION ~ ON PAGE 14
SKIP IF (CY)=O
ACTS AS INSTRUCTION B ON PAGE 14
RETURN,CCNVERSION FINISHED
( A) = ( A) + 1 5, SKI P IF CARRY =0, ( A) =( A )-1
ACTS AS INSTRUCTION B ON PAGE 14
(L>
=( A)
15
ADC25
o
EX (H)
(A)=(A)+15,SKIP IF CARRY=O, (A)=(A)-l
ACTS AS INSTRUCTION ~ ON PAGE 14
(A)=O
ADCL1
ACTS AS INSTRUCTION
(A)
A
ADC25
(A)=(A)+1,SKIP IF CARRY=O
ACTS AS INSTRUCTION 8 ON PAGE 14
BM
LA
THA
8M
TLA
XAH
(H) =( A)
d
ON PAGE 14
(L> =( A)
EX (H)
(A)=(A)+I, SKIP IF CARRY=O
(A) =15
ACTS AS INSTRUCTION ~ ON PAGE 14
END OF ADC2
(A)
A
1
LA
15
ADCL5
BM
*
*
•
MITSUBISHI
..... ELECTRIC
1t;-Aq
MITSUBISHI MICROCOMPUTERS
MELPS 4 PROGRAM LIBRARY
SUBROUTINES
3. Clear File
Fig. 6 Function of clear-file subroutine
Program Operation
These are subroutines that are used in clearing files
FO-F7, which are formed in the RAM area and are
organized as up to 16 words each. The file organization
is shown in Fig. 6.
These are subroutines, selected
by the Z register, that clear the addresses O"'MAX (MAX
= 0"'15) or that clear the addresses MIN"'15 (MIN =
0"'15). After MAX and MIN have been initialized and then
an LXY instructron that des~gnates the file number is
branched, only the first LXY instruction will be executed,
(y)
(z)=o (Z)=1 ( x) 15 14 13 12 11 10 9
Fa. F4
a
Fl. F5
I
F2. F6
2
F3. F7
3
15
MIN=12
CLEAR FILE
(12-151
8
7
6
5
4
3
2
MAX= 7
CLEAR FILE
10-7)
and the successive ones are skipped.
To use CFM to make a subroutine that clears the
addresses MIN-MAX designated by the Y register of each
file, the instruction set SEY max is inserted after the XAMI
o instruction.
Subroutine Call
An example of subroutine call is shown in Fig. 7. The
constants MAX and MIN first have to be equated by a
pseudo instruction. A file group is then selected by the Z
register as shown below:
When (Z) = "0": FO, F1, F2, F3
When (Z) = "1": F4, F5, F6, F7
then the BM instruction calls a subroutine of each file
unit.
Fig. 7 How to call the clear-file subroutines
MAIN
MAX
MIN
EaU
E au
LZ
8M
BM
BM
BM
LZ
BM
BM
7
............................................... MAX is intialized to 7 during assembly
12
............................................... MIN is inillalized to 12 during assembly
0
............................................... File groups FO. Fl. F2 and F3 are selected
CFO
CF1
CF2M
CF3M
............................................... Clears FO (0-71
1
............................................... The file groups F4. F5. F6. and F7 are selected
CFO
CF2M
............................................... Clears F4 (0-71
............................................... Clears Fl (0-71
............................................... Clears F2 (12 -151
............................................... Clears F3 (12 -151
............................................... Clears F6 (12-151
SUBROUTINES (ON PAGE 141
CFO
CF 1
CF2
CF3
LXV
LXV
LXV
LXV
0, MAX
1 , MAX
2, MAX
3, MAX
SUBROUTINE COMMON PROCESSING
RT
15-90
'MITSUBISHI
"'ELECTRIC
1
a
MITSUBISHI MICROCOMPUTERS
MELPS 4 PROGRAM LIBRARY
SUBROUTINES
4. Right-Shift File
Fig. 9 Example of left-shift file execution
Program Operation
This is a subroutine that is used to right-shift the files
FD-F7, as shown in Fig. 8. The contents of address a
"'MAX (MAX = 0"'15) in a file designated by the Y register
are shifted right one digit. The most significant digit (MSD)
is filled with 0 and the contents of the least significant digit
A REGISTER
FILE
15 14 1
12 11 10 9 8
7
6
5
4
3
2
1
:::~~~~~:j': :::::::::::
15 LEFT-SHIFT
(LSD) are stored in the A register.
Subroutine Call
The constant MAX has to be equated by using a pseudo
instruction. Then the appropriate file group is selected by
the X register before calling the subroutine. An example
is shown below, in which the digit numbers 0"'7 of the file
F are shifted right 2 digits
MAX
EQU
7
8M
8M
Fig. la, in which the contents of the file Fa are transferred
to the file Fl. Each time the TAM 1 and XAMD 1 instructions are executed, the designated file changes to FO-+
F l-+FO ... and so on.
FILE
A REGISTER
0
contents of the files FO"'F7. The data (MAX + 1 words)
in the addresses D-MAX (MAX = 0"'15) of the file designated by the Y register is transferred.
TAM j and XAMD j instructions. An example is shown in
RSF1
RSF1
Fig. 8 Example of right-shift file execution
EXEC~~Tg~
Program Operation
This is a subroutine that is used for transferring the
As already discussed in section 1.3, changing file designation in the RAM is automatically performed by the
LZ
EXE~ITT?~~ 0
6. Transfer of File
:":"1 ": ": ": ":':: ~fM£f.£££~o
MAX
Data-transfer subroutines of the address MIN-15 can
be made by changing MAX to MIN and the XAMD j
A
RIGHT-SHIFT
instruction to XAMI j.
Subroutine Call
The constant MAX has to be equated by using a pseudo
5. Left-Shift File
instruction. Then the appropriate file group is selected by
Program Operation
the Z register before calling the subroutine. An example is
This is a subroutine that is used to left-shift the files
FO"'F7, as shown in Fig. 9. The contents of address MIN
"'15 (MIN = D-15) in a file designated by the Y register
shown below, in which file Fa is transferred to file Fl and
F5 to F7. Digits transferred in each file are 0"'7.
MAX
EaU
7
LZ
o
8M
T F 1 0
are shifted left one digit. The least significant digit (LSD)
is filled with a and the contents of the most significant digit
(MSD) are stored 17 the A register.
A subroutine that is to left-shift MIN -MAX can be
LZ
made by inserting
8M
SEY max
following the XAMI a instruction. When MIN
=
a is
T F 3 1
Fig. 10 File transfer example of (Fl)
<-
(FO)
equated, it performs the same digits as the right-shift file
subroutine. The instruction SEY, however, may be omitted
when the skip condition is altered by the optional XAM I
TRANSFER
instruction.
Subroutine Call
MAX
FILE TRANSFER
0
The constant MIN has to be equated by using a pseudo
instruction. Then the appropriate file group is selected by
Note 2 : The arrows show how the file is changed.
the Z register before calling the subroutine. An example
is shown below, in which the digit numbers 12"'15 of the
file F7 are shifted left one digit.
MIN
EaU
12
LZ
8M
LSF3
• MITSUBISHI
"ELECTRIC
15-91
MITSUBISHI MICROCOMPUTERS
MELPS 4 PROGRAM LIBRARY
SUBROUTINES
Fig.11 CF, CFM, RST and LSF program lists
66
67
68
69
70
71
72
73
28
2C
2D
2E
2F
14
30
75*WO*31
76
32
77
78
79
BO
B1
33
B2
34
83
35
84
36
B5
37
B6
38
B7 *WO*39
B8
3A
B9
90
91
92
93
38
94
3C
95
3D
96
3E
97
3F
9B
40
99*WO*41
100
42
101
102
103
104
105
4.3
106
44
107
45
108
46
109
47
110
48
III *WO*49
112
4A
113
OC7
007
OE7
OF7
OBO
068
12F
044
*****.***** •• ***.*************.****.***.*.************.*.***
.SUBR: CF
CLEAR FILE FX(O-MAX)=O
•
.*****.*.** •••••••• **** ••• *.**.**** •• * •• * ••• ******.** •• *****
CFO
LXY
O,MAX FO(O-MAX)=O OR F4(0-MAX)=0
CF1
LXY
l,MAX F1(0-MAX)=O OR F5(0-MAX)=O
CF2
LXY
2,MAX F2(0-MAX)=0 OR F6(0-MAX)=0
CF3
LXY
3,MAX F3( O-MAX)=O OR F7(0-MAX)=0
CF01
LA
0
(A)=O
XAMD 0
(M) EX (A), (Y)=(Y)-l,SKIP IF (Y)=O
BM
CF01
ACTS AS INSTRUCTION B ON PAGE 14
RT
END OF CF
OCC
ODC
OEC
OFC
OBO
06C
137
044
**************************************************.***.****.
*SUBR: CFM
CLEAR FILE FX(MIN-15)=0
*
*****.**** •• **********************.*.*.**.******.*.**.******
CFOM
LXY
O,MIN FO(MIN-lS)=O OR F4(MIN-15)=0
CFIM
LXY
l,MIN F1(MIN-15)=0 OR F5(MIN-15)=0
CF2M
LXY
2,MIN F2( MIN-1S)=0 OR F6(MIN-15)=0
CF3M
LXY
3,MIN F3(MIN-15)=0 OR F7(MIN-15)=0
CFOMI LA
0
(A)=O
XAMI 0
(M) EX (A), (Y)=(Y)+l,SKIP IF (Y)=15
8M
CFOK1 ACTS AS INSTRUCTION B ON PAGE 14
RT
END OF CFM
*
************.************.*************.**.******.*.**********
OC7
007
OE7
OF7
OBO
068
140
044
*SUBR: RSF
RIGHT-SHIFT FILE FX(O-MAX),FX(MAX)=O,(A)=FX(O)*
******.****.************************.****************.*******
RSFO
LXY
O,MAX FO(O-MAX) R-S, FO(MAX)=O, (A)=FO(O)
RSF1
LXY
1.MAX FHO-MAX) R-S. Fl=O
RT
RETURN IF OVERFLOW
RTS
END OF ADFOI
48
49
4A
48
4C
4D
4E
4F
OCC
ODC
OEC
OFC
OB8
OOA
060
044
*SUBR: SBF
BCD SUBTRACTION OF FILE
*
*
=FXlCMIN-1S)-FX2(MIN-15)
*
*****************************************************************
SBFIO LXY
O,MIN J=l: FI(MIN-15)=FICMIN-1S)-FO(MIN-15)
J=2: F2(MIN-IS)=F2(MIN-1S)-FO(MIN-15)
*
*
J=3: F3(MIN-15)=F3(MIN-IS)-FO(MIN-15)
SBF01 LXY
I,MIN J=l: FO(MIN-1S)=FO(MIN-lS)-FlCMIN-15)
J=2: F3(MIN-15)=F3(MIN-lS)-Fl(MIN-lS)
*
*
J=3: F2(MIN-15)=F2CMIN-lS)-FICMIN-15)
SBF32 LXY
2,MIN J=l: F3(MIN-15)=F3(MIN-1S)-F2(MIN-1S)
*
J=2: FOCMIN-15)=FOCMIN-IS)-F2CMIN-15)
J=3: F1CMIN-15)=F1CMIN-lS)-F2CMIN-15)
*
SBF23 LXY
3,MIN J=l: F2CMIN-15)=F2CMIN-IS)-F3CMIN-15)
J=2! F1CMIN-15)=F1CMIN-1S)-F3CMIN-15)
*
J=3: FOCMIN-15)=FOCMIN-IS)-F3CMIN-15)
*
SC
CCY)=1
SBFOll TAM
J
(A)=(M(DP»
CMA
COMPLEMENT CA)
AMCS
(A)=CA)+CM(DP»+CCY),(CY)=CARRY
A
10
(A)=CA)+10.SKIP IF CARRY=O,BCD ADJUST
XAMI J
(A) EX (M(DP»,(Y)=CY)+I,SKIP IF (Y)=15
BM
SBFOll ACTS AS INSTRUCTION 8 ON PAGE 14
SZC
SKIP IF CCY)=o
RTS
END OF SBFOI
RT
RETURN IF OVERFLOW
*
************************************************************
*SUBR: SCF
SIGN CHANGE OF FILE FX(SIGN) EX
*
************************************************************
SCFO
LXY
O,SIGN FO(SIGN) EX
SCFI
LXY
I,SIGN F1(SIGN) EX
SCF2
LXY
2.SIGN F2CSIGN) EX
SCF3
LXY
3,SIGN F3(SIGN) EX
LA
8
CA)=8
AM
(A)=(A)+(MCDP»
XA M 0
( A) EX (M CDP ) )
RT
END OF SCFO
*
*#######11#11
MELPS 4 LIBRARY END
#######l1li#*
END
-------------------------------------------------------------------------------------• MITSUBISHI
"ELECTRIC
15-97
II
MITSUBISHI MICROCOMPUTERS
APPLICATION OF MELPS 4
SINGLE-CHIP 4-BIT MICROCOMPUTER
(M58840-XXXP) IN A MICROWAVE OVEN
controls the magnetron, on and off, to maintain the
DESCRIPTION
A typical example of an application in which a Mitsubishi
power specified, and turns the magnetron off as soon as
MELPS 4 single-chip 4-bit microcomputer is used in the
the specific period is over. The oven is kept in this halt
condition for the duration.
(6) COOK 1
microwave oven.
The system is designed to control the magnetron, fan
and buzzer of the microwave oven by the touch-keyboard
The operating Rower, temperature and time can be
input, and to display the time and temperature, along with
selected for this process. If no specific power is desig-
the power, on the large fluorescent display tube, as well as
displaying the MODE on the LEDs (8 pieces). Its features
include controls for designating the start-up time and
operating temperature can be selected in the range of
3SoC-9SoC. The magnetron is operated, on and off,
controlling the defrosting process (time and power), the
cooking process #1 (time, temperature and power) and the
cooking process #2 (time, temperature and power). In
addition, the clock can be used as an independent timer.
The program for the microwave oven application is
stored in the MS8840-001P.
FEATURES
•
Programmed operation for DEFROST, COOK 1 and
nated, the oven automatically uses a 100% setting. The
at the power setting after the cooking has started until
the selected temperature is reached. Although the
magnetron is turned off after reaching the selected
temperature, it is turned on again when the temperature
in the oven falls 3°C below the selected temperature.
This procedure is repeated until the time is reached for
completion of the COOK 1 process.
When no temperature setting is made, the oven oper-
COOK 2 processes
ates at the power specified and completes the COOK 1
•
Time, temperature and power controls
process when the set time is reached.
•
•
Clock and timer
Display of the time, temperature and power on the large
The procedures for COOK 2 are the same as those for
COOK 1.
fluorescent display tube
•
(7) COOK 2
The simplification in circuit design facilitates cost
reduction and miniaturization of the oven.
(8) Clear
The clear switch is used to change key entries or to
advance to the next process and discontinue the process
FUNCTION
in operation.
(9) Reset
1 . Microwave Oven Function
(1) Outline of operation
When the start key is depressed after setting up the
cooking conditions (time, temperature and power)
through the touch key, the oven starts operating in the
following sequence regardless of the order the conditions
were keyed in.
Depressing the reset key term inates the entire cooking
process and shifts to clock operation.
(10) Stop
When the stop key is depressed or the door is opened,
the cooking process is interrupted. The start key has to
be depressed again if the operation is to be resumed.
(11) Display
The operating time, power and temperature are dis-
As soon as one process is completed, the next process
is started, skipping those processes that are not
qesignated, until finished. In addition, the clock can be
used as an independent till'er.
(2) Clock
The clock has a 12-hour dial and indicates hours and
minutes.
(3) Timer
The timer actuates the buzzer at the specific time
for the clock, power and temperature settings. The oven
temperature can also be displayed.
The cooking mode is indicated on the LED.
2. Inputs
22 keys are arranged in a matrix through the K ports
It designates the start time and starts the cooking when
that specific time is reached.
(S) Defrosting
Power and time can be selected for defrosting , but
when no power setting is made, the oven automatically
15-98
played on the screen by the use of the CLOCK key. It
usually indicates remaining cooking time during the
cooking operation, but memory contents can be recalled
(1) Key input: Ko""'K7
designated in minutes and seconds.
(4) Start time
uses a 50% setting.
plyed on the fluorescent display tube. The tube displays
key-entry data during the key entry. The clock is dis-
During the se! time, the system
and the D ports, using the touch keyboard for input. All
inputs are checked 8 times in a lOOms period before
being accepted as valid. This is done to prevent errors
in operating the oven. Furthermore, successive key entry
cannot be made until it is confirmed 8 times in a period
of lOOms that there were no keys depressed.
• MITSUBISHI
.... ELECTRIC
MITSUBISHI MICROCOMPUTERS
APPLICATION OF MELPS 4
SINGLE·CHIP 4·BIT MICROCOMPUTER
(M58840-XXXP) IN A MICROWAVE OVEN
The following 22 keys are provided: defrost (DEFR),
cook 1 (COOK 1), cook 2 (COOK 2), temperature
about 1/14, with an on duration of 0.9ms.
The following type of a display is taken into consid-
(TEMP), power (POWER), start (START), stop (STOP),
eration.
clear (CLEAR), reset (RESET), timer (TIMER), clock
is displayed in the least significant column, the colon
(CLOCK), start time (5. TIME) and numbers ((}-9).
(2) Time detection input: K 13
This input is used to count the time. Rectified AC
When indicating the temperature and a "C"
in the center of the display is not displayed. Also for
power display the colon is not displayed, and a "P" is
displayed in the least significant column.
waveform from the power source is applied.
OO·C/O
(3) 50/60Hz switching input: K9
LI 1-'· LI LI
This input is used to compensate for the power source,
50Hz or 60Hz.
(5) LED display: So-5 7 , DIO
(4) Temperature sensor input: Kll
Key entry number or the cooking mode is displayed on
Voltage appropriate to the temperature is applied from
the LED, and the contents of one or more of the
the thermistor located in the temperature probe.
following are displayed: [5. TIME], [DEFR], [COOK
(5) Temperature probe SW input: Ks
1], [COOK 2], [TIMER], [START], [STOP], and
This input is used in checking whether the temperature
probe is operating.
[TEMP].
The LED is activated dynamically, and its duty is about
(6) Door SW input, KIO
70%, with an on duration of about 9ms.
This input is used to check whether the door is open.
(7) Touch keyboard comparison voltage setup input: K14
This is an input with which the detection level is set
up for the touch keyboard. It very useful when the
specifications of the touch keyboard are altered.
3. Outputs
(6) Capacitive panel detection outputs, D o-D 2
Inverted D-port outputs are amplified and supplied to
the touch keyboard in order to identify the key depressed
in the matrix through the K ports.
Output D2 is used for displaying the colon on the
fluorecent display tube.
4. Key Entries
(1) Magnetron control output: 0 4
The magnetron is activated with a high-level output, and
After depressing a function key, a number key is depressed.
disabled
with a low-level output. Alternate on/off
Then the data thus entered will be stored in the RAM, after
operations are repeated with the designated power
(duty) in units of 30 seconds. For instance, the magne-
another function key has beed depressed, if no error was
detected in the data.
tron is activated for a period of 9 seconds and disabled
(1) Setting the time
for a period of 21 seconds, when the power setting is
30%. It also provides on/off action for controlling the
Setup of hours and minutes:
temperature.
within the range of 1 :00-12:59.
Used to set the CLOCK and S. TIME. Must be set
Setup of minutes and seconds:
(2) Fan output: 0 3
The fan is started as soon as the DEFROST, COOK 1 or
Used to set the TIMER, DEFR, COOK 1 and COOK 2
COOK 2 process is begun, and is turned off as soon
periods.
as the stop switch is depressed or the cooking process
Must be set within the range of 1 second-99 minutes
is completed.
and 59 seconds.
Error:
(3) Buzzer output: Ds
When key entry is made over the above upper limits or
There are three buzzer-control outputs.
O.2-second buzzer . . . This buzzer is activated each
more than 6 digits are entered, an error indication
time a validated key entry is made.
(EE:EE) is displayed.
0.5-second buzzer . . . This buzzer is activated each
An example of setting the clock operation is shown in
time one stage is completed.
the following illustration:
3-second buzzer ... This buzzer repeats 0.2-second
Example of key entry (1 )
intermittent actuation for a period of 3 seconds when
the timer completes its counting or the cooking
KEY
1 ST STEP (CLOCK)
process is completed.
2ND STEP (
3RD STEP (
2
with these outputs. (With maximum output voltage of
4TH STEP (
3
33V, and maximum of 15mA for the D ports and a
5TH STEP
4
maximum of 8mA for the 5 ports.)
(
6TH STEP (START)
The display is activated dynamically, and its duty is
• MITSUBISHI
.... ELECTRIC
01
:
(4) Fluorescent display tube: So-5 7 , D6 -D 9, D2
A large fluorescent display tube can be driven directly
DISPLAY
1
: : 21
::2 31
2:3 yl
2:3 L:I
15-99
MITSUBISHI MICROCOMPUTERS
APPLICATION OF MELPS 4
SINGLE-CHIP 4-BIT MICROCOMPUTER
(M58840·XXXP) IN A MICROWAVE OVEN
When a key entry error is detected in the fifth or sixth
In the first step the present time is displayed from the
step, an error indication "EE:EE" is displayed, after
clock.
the CLEAR key has been depressed. Then the data must
recalled from memory in the second and third steps.
be reentered. When there is no error in the key entry,
The time setting for COOK 1 is recalled in the fourth
Then the temperature setting for COOK 2 is
the clock operation will start as soon as the start key
step. Then the power setting for COOK 2 is recalled
is depressed.
from memory in, the fifth and sixth steps.
(2) After the start
(2) Setup of duty for the magnetron
The operating power must be set in the following
After the start key is depressed, the remaining cooking
sequence: [POWER] -+ [DEFR, COOK 1, or COOK
time is displayed, but the following data can be recalled
2] -+ [NUMBERS]. Power duty in the range of 0
and displayed for 3 seconds.
"'100% can be used for COOK 1 and COOK 2 operations, but for the DEFR operation the range is 0"'50%.
Even though the rate is set over 50% for DEFR, a rate
Power: Depression of the [POWER] key displays
the current power setting.
Clock: Depression of the [CLOCK]
key displays
the time.
of only 50% will be used because of the limit.
Entry of power duty settings 0 -90% is made by
Operating temperature: Depression of the [TEMP]
depressing one number key that is the desired setting
key once displays the current operating tempera-
to the closest 10%. An entry of 100% is made by
ture setting.
depressing the 1 followed by a O. Deviating from this
Measured temperature: Depression of the [TEMP]
key twice displays of the measured temperature at
will cause an error.
the present stage.
Example of key entry (2)
KEY
6. Correction of Data
DISPLAY
1ST STEP (POWER)
2ND STEP (COOK 1)
As the function keys are depressed to recall data, correction
:00,01
of the data can be made by entering the new corrected data
20,0 I
3RD STEP (
after the key operation in the usual manner.
01
4TH STEP (COOK 2)
depressed to stop the operation.
Automatically 100% of the duty is recalled from the
memory in the second step, 20% is displayed in the
third step, 20% is stored in the RAM in the fourth
7. General flowchart
A flowchart of the M 58840-00 1P is shown in the following
illustration.
step, and then the time of the COOK 2 is recalled from
the memory. (But only [0] is displayed in this case,
because the data for COOK 2 has not yet been entered.
(3) Setup of temperature
The operating temperature must be set in the sequence
of [TEMP] -+ [COOK 1 or COOK 2] -+ [NUMBERS].
The temperature must be within the range of 35°C
"'95°C. Exceeding this range wfll cause an error.
5. Data Display
(1) Before the start
Data during key entry is displayed in the manner
mentioned previously, but this data can be recalled
from memory by depressing the appropriate function
key when needed for reference.
Example of key entry (3)
KEY
1ST STEP (CLOCK)
2ND STEP ( TEMP)
3RD STEP (COOK 2)
4TH STEP (COOK 1)
5TH STEP (POWER)
6TH STEP (COOK 2)
15-100
To correct
the data while in operation, the stop key must first be
DISPLAY
: ::5.51
cl
62cl
5:301
,01
G 0,0\
• .MITSUBISHI
.... ELECTRIC
MITSUBISHI MICROCOMPUTERS
APPLICATION OF MELPS 4
SINGLE-CHIP 4-BIT MICROCOMPUTER
(M58840-XXXP) IN A MICROWAVE OVEN
8. Routines for Other Applications
used to terminate or start operations when the count
Program routines of the MS8840-001P that may be suitable for other applications are shown below.
reaches O.
(10) Buzzer control
(1) Temperature measurement
Buzzer actuation can be controlled for a duration of
0.2,0.5 or 3 seconds. The 3-second actuation is on-off
After measurement of the temperature, the data, output
as Hand L signals, is converted to BCD.
at 0.2-second intervals.
(2) Counting seconds
(11) Time monitoring
Up to 60 seconds can be counted by supplying the
power-supply waveform to the K'3 port.
Time can be monitored and used to terminate or start
operations when the time setting is reached.
9. Typical control circuit of a microwave oven
(3) Counting hours and minutes
Up to 12 hours can be counted.
A typical example of a microwave oven circuit is shown.
Details of input and output performance are as previous-
(4) Use of touch keyboards
Depression of a touch-keyboard key can be detected.
ly described. Please refer to the information provided for
(5) Key identification
the PCA0402 in regard to capacitive touch-keyboard
operation. The diode D" is provided to prevent counterflow
because D2 is also used for the colon output and display.
The temperature-detection circuit K" compensates for the
Up to 22 keys can be identified.
(6) Displaying
A fluorescent display tube and LEDs can be displayed
dynamically.
nonlinear output of the temperature probe and facilitates
easy temperature conversion.
(7) Temperature comparison
The touch-keyboard interface and the AID conversion
circuit are contained in the M58840-XXXP. The wide range
Temperature comparison can be made to detect a 2°C
fall in temperature for temperature control.
(8) O.S-second flickering
of S ports and high maximum output voltage of the Sand
D ports simplify circuit design. This results in cost reduc-
Display "C" or the LED can be flickered in units of
0.5 seconds.
(9) Count of time
tion, improved performance and improved reliability because fewer parts are required. The use of fewer parts
also helps miniaturization.
The time settings can be decremented each second, and
APPLICATIONS EXAMPLE (microwave oven
M58840-001 P)
F
M
A
A
N
G
30V
Z
Z
E
R
10kX12
AZI An A23 RZ4 RZ5 RZ6 RZ7 RZ8
D3
R56
~
Rll0~8
R,
I-- I-- r--
R3
t-- r-- r---
R,
t-- r-- r---
Rs
R,
t-- r-- r---
R.
VA
I
R'4
Rll 2SB
2.2k 528
-u-
D,_.(MC301 x 8)
-U-
K6
OJ
K,
JL
JL
AC WAVEFORM
RS6
33k
LED,_.
II
III/
A33 R34
R41
2.2k
""J
10k
R20
82k
R,.25B
22k 528
VREF
JL
D,
~
K.
D,
K.
-'"
Do
Rs,
Rss
eoOC" ,
EMP
10k
-30V
1/11 II
.-J Q,
30V
H~'"
500Q
VR
~~~PROBE5W
~~50/60HZ
-15V
Rso
330Q
.....-Rs,
'--- 8.2k Rs,
TEM~( ~
(MODE DI5PLY]
25C620
R"
KlO ~o5W3
r'~
~f33k
D,
R'3
R" R36 R37 R3B R39 R40
OOIP
D,o
10k
R18
III/
l}'"L
3.3kX8
M58840-
~~ ~~
R,s 25B
22k 528
IFLUORESCEN:
DISPLAY TUBE)
Ks
:;u-
R'3~~'6
10k
82k
R'~r12
8.2k
~
K3
~
/-, /-'·0 ,-,
C] ".,_, 0
IT K,
R6
t-- r-- r---
I
""1I"" K,
"""1.r
t-- r-- r---
r- 10k
R,o
K,
-U-
I
50
5,
5,
5,
55
56
5,
53-
Ko
t-- r-- r---
(
9 ~~
X,N
;!;
r-r-
-15V
Ds
D6
D,
D.
D9
XOUT
C, 10PF
PA~)
(TOUCH
D,
R29 AJO R31 R3Z
RS3
12k
5W
DOOR 5W
-15V
R48
R49
330Q
(HL SET CIRCUIT FOR
PROBE
D,o
TOUCH KEYBOARD)
R ~I--,
S'1.5~ (TEMPERATURE(AC REC TIF YING CIR CUIT)
DETECTION CIRCUIT)
• MITSUBISHI
"ELECTRIC
15-101
MITSUBISHI MICROCOMPUTERS
MELPS 8/85 PROGRAM LIBRARY
SUBROUTINES
1 . CODE-CONVERSION PROGRAMS
There are 4 code-conversion programs for conversions
between hexadecimal numbers and their corresponding
ASCII code in binary notation. Details of these programs
are given below.
Table 1 Correspondence of number formats
Hexadecimal
symbols
Machine language
binary number
ASCII code in binary notation for
hexadecimal symbols
0
1
0000
0001
001 0
001 1
0100
0101
01 10
01 1 1
1000
1001
1010
101 1
1 100
1 101
1 1 10
1111
00110000
00110001
00110010
001 1001 t
00110100
00110101
001 10110
001 lOt 1 1
00111000
001 1 1001
01000001
01000010
01000011
01000100
01000101
01000110
2
3
4
5
6
7
8
9
A
B
C
0
E
F
1 .2 Binary (8 Bits) to ASCII (2 Characters)
Conversion (BTA 2)
This program converts the 8 bits in the C register (a 2-digit
hexadecimal number OO-FF) to the 2 corresponding 8-bit
ASCII-coded hexadecimal symbols '0' -~'F'. The results
are retained in registers H (high order) and L (low order).
The B, D and E registers are not affected.
Register Status
Register
Contents at return
Contents at start
8-bit ASCII code for the high-order
hexadecimal svmbol
A
C
Binary number to be converted
Binary number to be converted
8-bit ASCII code for the high-order
hexadecimal svmbol
8-bit ASCII code for the low-order
hexadecimal svmbol
H
L
Contents at start
B. 0 and E
Flow Chart
1.1 Binary (4 Bits) to ASCII (1 Character)
Conversion (BTA)
This program converts the low-order 4 bits in the A
register (a hexadecimal number O-F) to the corresponding 8-bit ASCII-coded hexadecimal symbol '0' -'F'.
The result is retained in the A register. Registers B,
C, D, Hand L are not affected.
BTA
(L)+-(A)
Register Status
Register
Contents at start
A
Binary number to be converted
in the low-order 4 bits
Contents at return
B. C. D. E.
(A)+-(C)
8-bit ASCII code
CONTENTS OF THE A REGISTER
SHIFTED 4 BITS TO RIGHT
Contents at start
Hand L
Flow Chart
BTA
IN ASCII CODE
,
,
1
RETURN
Program Listing
I
1\2\3\415\6 7 8 \ 9\10\1 il12\13 14\15\16117\18\19\20\21\22\23\24\25\26\27\28\29\30\31\3213
'
'
)
Program Listing
1\2\3\4\5\6 7 8\9\10\11\12\1
*
* ***
*
BTA
5
B1
10
15-102
14\15\ 16\ I 7f11l1 19120121122123124125\26\27[28129130[3 113213
SUB,( B TAl)
ANI
CPI
JNC
ADI
RET
ADI
RET
*/BINARY
OF#
10
B1
48
55
TO ASCI I
*
* *** SUB,( BTA 2J *
* *BIN ARY TO TWO ASC:I I
:
*
A.C
BTA2
MOV
5
:
BTA
CALL
L.A
M,OV
A.C
M,OV
RRC
:
RRC
10
RRC
:
RRC
CALL
BTA
:
H.A
M,OV
RET
15
• MITSUBISHI
;""ELECTRIC
,,
:
CHARACT:ERS
:
:
:
:
:
:
MITSUBISHI MICROCOMPUTERS
MELPS 8/85 PROGRAM LIBRARY
SUBROUTINES
1.3 ASCII (1 Character) to Binary (4 Bits)
Conversion (ATB)
1.4 ASCII (2 Characters) to Binary (8 Bits)
Conversion (ATB 2)
This program converts the 8-bit ASCII code in the C
This program converts the two 8-bit ASCII codes in the
register (a hexadecimal symbol 'O'''''F') to a 4-bit binary
Hand L registers (2 hexadecimal symbols 'O'''''F', high
number 0000"'1111. The result is retained in the low-order
order in the H register and low order in the L register) to
4 bits of the A register. If the C register contains a code for
an 8-bit binary number (0"'255 10 ). The result is retained
a character other than a hexadecimal symbol O"'F, it is
in the A register. If the H or L register contains a code
recognized as an error; the carry flip-flop is set, and the
for a character other than a hexadecimal symbol 'O'''''F',
program is exited. Registers 8, D, E, Hand L are not
it is recognized as an error; the carry flip-flop is set, and the
affected.
program is exited. The D and E registers are not affected.
Register Status
Register
Register Status
Contents at start
A
D
ASCII coded hexadecimal symbol
to be converted
B.D.E.H and L
Contents at start
Register
Contents at return
Hexadecimal number in binary
form in the low order 4 bits
ASCII coded hexadecimal
symbol to be converted
A
Conten ts at start
C
B
H
Flow Chart
L
o and
Contents at return
8-bit binary number
(2'hexadecimal digits)
4-bit binary number in the high-order 4-bits
conversion of high-order hexadecimal symbol
Low-order ASCII coded hexadecimal
symbol to be converted
High-order ASCII coded hexadecimal High-order ASCII coded hexadecimal
symbol to be converted
symbol to be converted
Low-order ASCII coded hexadecimal Low-order ASCII coded hexadecima
symbol to be converted
symbol to be converted
Contents at start
E
Flow Chart
Program Listing
r-
1121314i516 7 819110111112113 14115116117! 18119120121122123124125126127128129130131132133
*
* ***
*~,TB
5
oA1
1-1
A2
5
A3
* I:ASC I I
SUB(ATB)
(
:
)
RETURN
Program Listing
TO B:INARY
11213141516 7 81 9110111112113 14115116117118119120;2112212312412512612712812913013113213
MOV---,
CPI
JC
CPI
JNC
SUI
ANA
RET
CPI
JC
CPI
JNC
SUI
lANA
RET
STC
RET
A,C
65
A1
71
A3
55
:
*
SUBJATB 2cl
* ***
*
RS
* ITWO ASCI I C H A R A C:T:E
:
*ATB2 MOV C,H :
5
IA
48
A3
58
A3
4,8,
A
:
:
:
10
15
:
•
CALL
RC
RLC
RLC
RLC
RLC
MOV
IMOV
CALL
RC
ADD
RET
ATB
TO B I NiARY
:
:
:
:
:
:
B,A
C, L
ATB
:
:
:
:
:
B
:
:
MITSUBISHI
IY.. ELECTRIC
15-103
MITSUBISHI MICROCOMPUTERS
MELPS 8/85 PROGRAM LIBRARY
SUBROUTINES
2. SORTING PROGRAM (SORT)
Flow Chart
This program sorts records (1 byte in length) in descending
order. Up to 65535 records can be sorted. The binary number 255 10 cannot be used as data because it is reserved for
the end-of-data mark. This data is stored in descending
INITIALIZE ADDRESS j TO
PRO; j IS THE RECORD TO
order according to its rank.
The program sorts by comparing a data item with all
BE RANKED
other data items, thus determining its rank. The data is
then stored in descending order according to that rank.
INITIALIZE ADDRESS i TO PRO.
This program can also recall the data associated with any
THESE ARE THE RECORDS TO
rank. If the rank k (1 ~ k ~ 65 535) is stored in memory
BE COMPARED
locations ORO and ORO+1, the 1-byte data associated with
INITIALIZE ADDRESS k TO MAX.
that rank is stored in the A register, and then control is
k IS THE ADDRESS OF THE kth
returned to the user's program. If k is specified as zero, the
RANKED RECORD'S DATA
A register is reset to zero and control is returned to the
user's program.
Register Status
Contents changed at return
Register
Use during execution
A
Calculates and recalls data of rank k
B
Storage for data being compared
yes
C
Not used
no
0
Memory address for storing data after
yes
E
ranking
yes
yes
yes
H
L
Memory address of data to be ranked
yes
Symbolic Memory Address
No. of bytes
Contents changed
at return
2
no
PRO
Storage area for records to be
sorted (PRO is the first address)
n+1
no
MAX
Storage area for sorted data
(MAX is the first address)
n+1
yes
DADO
Address in PRO of record
being sorted
2
no
RAOO
Address in MAX for storing
result
2
no
Ml
M2
COUNT
Address of record to be ranked
2
2
2
yes
Address of record being compared
Symbolic address
Use during execution
ORO
k (the rank of data to be recalled
LOWER RANK BY 1
*~
::)
k<--k+l
ttl
~
~
0
u
Counter for number of records
yes
yes
STORE DA fA OF RECORD j IN
OUTPUT FILE CORRESPONDING
TO ITS RANK k
15-104
•. MITSUBISHI
.... ELECTRIC
MITSUBISHI MICROCOMPUTERS
MELPS 8/85 PROGRAM LIBRARY
SUBROUTINES
Program Listing
11213141s16 7 819110/11112113 14115/16117118JI912oI21122123r2412SI2612712812~3~ 3113~33
11213141s16 7 81911~11112I1 1411s11611~lslI9I2~21122123/2412sI2612712812913~3113213
R5
R6
*
*
*
IN.A.M,
S,QR T,········t·····························t··LCI{
* i*··························~··L®
QRO
D,ADR
0:
.15
MAX
**
DEF
BSS
15:
65
:
F F# ···········:·····························:··i(4)
MA.X -P RO·····························:·-;<-m
*
RS
70
f-L-L.L
I
20 RADD
M,1
M2
C,OU,N.T
DADR
DADR
DADR
DADR
*
R7
;
10~~~~4D~E~F~~F5~5~~~~~~~~~~~
DE F
1 00 ........ j............................. j.. jQ.)
DEF
60
I
I
I
I
I
*
I
MAX
0
0
III, ,
LHLD,
R,A,DiD
OAD:D
R9
~~R~1~~~~S~H~L·D~~C~OIU~iN~T~~~~~~~~~
~
.J~
XCH~
35
*R2
IMOY
B ,oM
CP I
FF#:
RS
1M1
DADiD
JZ
SHLD
LH LD
40
R3
80
............. ~
H, 0
M
M,1
H :
A, Bi
D :
LHLD
XCHG
LHLD
DAD
MOY
COUiNT
JZ
25~:~*~*_*~P~R~IQ~\Q~IR~A=TIM~S~T~A~R~T~i*~*~*~*~~~~~
S,ORT
LHLD
INX
MOY
STAX
XCHG
LHLD
JNX
JM,P
DCX
XCHG
LHLD
DAD
M,OV
RET
~*~I~~~~~~~~~~~~~~~~~_:~_L
R,QM,
LHLD
XCH,Q
LX I
D :
H !
R3
LHLD
MOY
p,RA
75
0
INX
INX
JM,P
,III
I
I-L_~
COU:NT
H :
R1
:
:
RAD:D
D
M" A~
PLRD:
A, Li
H
R9
H
:
RAD~
D
A'M;
Explanation Keyed to Program Listing
CD The
program name is defined as 'SORT'.
(2) If column 1 of a statement is '*', it is considered a
comment.
Q) Defines the value of data.
@ The '#' in FF# indicates that FF is a hexadecimal
number.
IMOY
A,
SHLD
1M2.,
@ Reserves a region to store the results.
FF:t:I::
@ The above program is defined as a RAM region because
JZ
R7
C,M,P
B
PUSH
PSW
LOA
1M2
JC
P,OP
R4
lep I
its contents are variable at time of execution, and this is
a ROM region because its contents are fixed.
pSW,
• MITSUBISHI
IIf'&ELECTRIC
15-105
MITSUBISHI MICROCOMPUTERS
APPLICATION OF MELCS 8/2 SINGLE·BOARD COMPUTER
(PCA 0801) IN DATA TRANSMISSION
THROUGH A MASTER-SLAVE MULTICOMPUTER SYSTEM
DESCRIPTION
EPROM and the RAM for discrepancies.
If all the data is correct, LED 1, which acts as an indicator, is turned on. If not, LED 2 is lit, and execution
Three PCA080 1 single-board computers are connected to
form a master-slave microcomputer data-transmission
system. Such a system contributes significantly to reducing
the load on the host computer and to improving the
operational efficiency and functions of the system. This is
an example of a mode 2 application of the M5L8255AP
programmable peripheral interface (PPI).
is terminated.
The operational status of the LEDs (on or off), and
their significance, are shown in Table 1. These status indications are shown in the sequence of CPU progress, so
that the operating status of the master· computer may be
readily recognized from the combination of LED O"'LED
2 indicators.
FUNCTION
One of the three PCA080 1s serves as the master computer,
and the other two as the slave computers that complete
the system. When the No.1 PPI (C.W.=03 16 ) is set to
mode 2, data is transmitted between the master and either
of the slaves using the I/O port PA as a bidirectional data
bus.
Table 1 Status as Indicated by the LED Display
CPU LED LED LED
Sequ'
ence
Description of the status Indicated
0
1
2
0
0
0
System
0
0
1
Data is being started between the master and
slave computer No.1.
1
0
0
Data is being transmitted between the master and
slave computer No.1
I/O port PA (PA o "'PA 7 ). After receiving the data, the
s~ave computer inverts the data and stores it in its RAM
0
0
0
Data is completed between the master and slave
computer No.1.
(M5L2111AP). This inverted data is then sent back to the
0
0
1
System IS in the idle condition. with no transmission
between the master and slave computer No.2
master computer, after which it is stored in the master
computer's RAM.
1
1
1
Data is being started between the master and
slave computer No.2.
-->
0
1
0
Data transmission has been completed. having transmitted the data correctly
-->
0
0
1
Data transmission has completed. but a transmission
error has been found.
OPERATION
The master computer, storing 200 bytes of the transmission data within its No.2 EPROM (M5L 2708K), starts
to transmit that data to the No. 1 slave computer via the
IS
not transmitting data
'-
The master computer now starts to transmit 200 bytes
of the RAM data to the No.2 slave computer, where the
data is inverted and stored in the RAM to be sent back to
the master computer.
The master computer, having completed storage of the
data in its RAM, executes an inspection routine for the
stored data, and compares the 200-byte contents of the
Fig.1
Note 1
2
"ON" indicates where the LED turns on. and "OFF" where the LED turns off
The slave computers. No. 1 and No.2. must be In operation prror to the engagement of the master computer
Applcation Example
PCA0801 SINGLE-BOARD COMPUTER (NO 2 SLAVE)
~
M5L2111AP
PPI
PB(05,.)
M5L 8255AP
PC(06,.)
PB(O',,)
---- -----
M5L 8255AP
'"'
~
pCs~
PA(OO,,)
3309
... <,
3309
... !'!'
3309
'/
LED 2
~
LED 1
CP26 ACKA
LLED 0
CP24 STB
CP27
I
CP25 IBFA
...
...
OBF A
~
CP65
I
CP61
B
\ . \
PA, 24
CP60
CP15
~
M5L 2111AP
L---.J
PA(04,,)
~
CP"
PB(05,,)
M5L 8255AP
PC(06,,)
~
CP14
~
CP10
PPI
PB(O',,)
EPROM NO 1
(M5~6~08K)
INSTRUCTION
STORAGE
~
M5L 8080AP
~
'I
--------
M5L
8255AP
pp,
PC(02,,)
pc,
PC7
16
PCs-...!..!.
~
ACKA
CP24
STBA
CP27
OBF A
CP25
IBFA
-----;~-:c:
PA(OO,,)
8
CP26
\
\
PA, 24
CP07
@
STBA
CP20
ACKA CP2'
BIDIRECTIONAL
DATA BUS
PCA0801 SINGLE-BOARD COMPUTER (NO.1 SLAVE)
15-106
• MITSUBISHI
.... ELECTRIC
r-=:l
r------1
C;w PCs
36 PC,
39 PC,
EPROM NO.2
(M5~6~08K)
PC(06,,)
~PCo
~
r------1
6PBs
2 PB,
PB(OI,,)
5 PB,
PPI
--:'::~~~_~~,=_8~55AP
\
\
rJ~AO
24 PA,
-- -
CPOO
8
PA(04,.)
---------I----29 PB,
~ 28 PB I PB(05,.) M5L 2111AP
27 PBo
PPI
L---.J
~ 1-:::
___ ~5:-_8!25AP
CP64
------P~:a:
M5L8080AP
~
:~
PC, 15
PC, 13
PC(02,,) pc, 16
~
5V -{r
f-----.'-L
~
EPROM'"NOl
(M5~5~08K)
INSTRUCTION
STORAGE
PCA0801 SINGLE-BOARD COMPUTER (MASTER)
~
~
PA(04,.)
-,5
- -
PC.
,3 PC,
9 PCo
,0 PC,
PA(OO,,)
---PC(02,,)
EPROM NO.1
(M5L2708K)
FOR
INSTRUCTION
~
N
M5L 8080AP
~
MITSUBISHI MICROCOMPUTERS
APPLICATION OF MELCS 8/2 SINGLE-BOARD COMPUTER
(PCA 0801) IN DATA TRANSMISSION
THROUGH A MASTER-SLAVE MULTICOMPUTER SYSTEM
Fig. 2 Master microcomputer flow chart
NO
OUTPUT (COUNT)
TO I/O PORT 0416
Nap
• MITSUBISHI
"ELECTRIC
15-107
MITSUBISHI MICROCOMPUTERS
APPLICATION OF MELCS 8/2 SINGLE-BOARD COMPUtER
(PCA 0801) IN DATA TRANSMISSION
THROUGH A MASTER-SLAVE MULTICOMPUTER SYSTEM
Fig. 3 Slave microcomputer flow chart
NO
INITIALIZE VALUE
OF STACK POINTER
(A)<-(SCRTCH)
SET CARRY
CALL SO
(SLAVE DATA OUTPUT)
NO
NO
MOVE DATA IN
SCRATCH-PAD AREA
TO RAM DATA AREA
CLEAR WORK AREA
INCREMENT
(H)(L)
NO
INITIALIZE 20216
IN (D)(E)
INITIALIZE
RAM TOP ADDRESS
IN (H)(L)
NOP
14------(2
CALL SI
(SLAVE DATA INPUT)
INVERT INPUT DATA
AND STORE IN
SCRATCH-PAD AREA
15-108
COMPLEMENT CARRY
• MITSUBISHI
.... ELECTRIC
MITSUBISHI MICROCOMPUTERS
APPLICATION OF MELCS 8/2 SINGLE-BOARD COMPUTER
(PCA 0801) IN DATA TRANSMISSION
THROUGH A MASTER·SLAVE MULTICOMPUTER SYSTEM
MASTER MICROCOMPUTER MAIN PROGRAM LIST
* *CROSS ASSEMBLER OF 8-BIT MICROPROCESSOR
0001*** MASTER MICROC 0 MPUTE R MAIN PROGRAM ***
0002 0400
ROM2ST EaU
0400#
0003 4000
RAM5T Eau
4000#
0004 40ca
OS TN Tl Eau
40C8#
0005 40CA
DSTNT2 Eau
40CA#
0006 40CC
FLAG
fau
40CC#
0001 40CO
COUN T Eau
40CO#
0008 40CE
TEMPRY EQU
40CEII
0009*
0010*
0011 0000
ORG
0000#
0012 0000 3EC2
MASTER MV I
A tCU
0013 0002 0303
OUT
03'
0014 0004 3E01
MVI
AtOll
0015 0006 0303
(JUT
03'
0016 0008 3E03
MVI
A t03'
0017 OOOA 0303
OUT
03'
0018 OOOC 3E80
MVI
A t80#
0019 OOOE 0.301
01#
OUT
0020 0010 3EOO
MVI
AtOOw
0021 001Z 0305
OS,
OUT
0022 0014 3EFF
MV!
AtFF#
0023 0016 0.306
OUT
06'
0024 0018 3EAA
MVI
AtAM
0025 001A 0304
OUT
0411
0026 00 Ie 31FF40
LXI
SPt 40FF II
0021 001F 0602
Bt 2
MV I
0028 0021 210001
rftX
LXI
0029 0024 22C840
SHLO OSTNTI
0030 0027 21E 501
LXI
HtY
0031 002A 22CA40
SHLO OSTNT2
0032 002D AF
XRA
A
0033 002E 32CE40
STA
TEMPRY
0034 0031 32C040
STA
COUNT
0035 0034 3£59
MVI
At59#
0036 0036 32CC40
STA
FLAG
0031 0039 CD1201
CALL TIMEC
0038 003C 3E69
A ,69#
MVI
0039 003E 0300
00#
OUT
0040 0040 3E02
A,0211
MV!
0041 0042 0303
OUT
03#
0042 0044 3EOO
/'IV I
A,00'
0043 0046 D301
01#
OUT
0044 0048 3C
A
INR
0045 0049 0301
OUT
01'
0046 0048 3E03
A,03#
MV!
0041 0040 D303
OUT
03'
0048 004F C02E01
CALL TIMED
0049 0052 3E08
At0811
MVI
0050 0054 0301
OUT
0111
0051 0056 3EOO
A ,00,
MV!
0052 0058 0303
OUT
0311
0053 005A 3C
INR
A
0054 0058 0303
OUT
03'
0055 0050 3E09
MVI
A t0911
0056 005f 0307
OuT
0711
0051 0061 OBOO
I~
00'
0058 0063 0666
suI
6B.
0059 0065 C20B01
JNl
NOC O"1C
0060 0068 3E 01
MVI
"toa
0061 006A 0305
!juT
~5'
0062 006C 21000 4
H,RCM25T
UI
0063 006F 11 004 0
LXI
[)t~A~5T
0064 0012 OEca
(,2')')
RPT2
Mil
0065 0014 7E
~r;,
/.t~
RPTl
.,:
0066 0075 C05501
':J._L
Cf. __ L
0067 0018 C02E01
T 1"':: oJ
0068 0018 C06001
'"..f.,-,1"1
0069 007E 32CE40
':;.Tf.
T("'~~'(
J..
0010 0081 3ACC40
0011 0084 B7
0012 0085 C20101
0013 0088 3ACE40
0014 0088 EB
0015 008C 71
0016 0080 00
0011 008E EB
0018 008F C2FCOO
0079 0092 3EOO
0080 0094 0305
OOtH 0096 18
0082 0091 FE02
0083 0099 C2CFOO
0084 009C C01201
0085 009F 3E69
0086 OOAI 0300
0081 00A3 3E02
0088 00A5 0303
0089 00A1 3E02
0090 00A9 0301
0091 OOAB 3C
0092 OOAC 0301
0093 OOAE 3E03
0094 0080 0303
0095 00B2 CD2E01
0096 00B5 3EOA
0091 OOB1 0301
0098 0089 3EOO
0099 OOBB 0303
0100 0080 3C
0101 OOBE 0303
0102 OOCO 3EOB
0103 00C2 i)307
0104 00C4 OBOO
0105 00C6 0668
0106 00C8 C20BOl
0101 00C8 3E01
0108 OOCO 0305
0109 OOCF 210040 S2ENO
0110 0002 54
0111 0003 50
0112 0004 05
0113 00D5 C27200
0114 0008 OEca
0115 0001\ 110004
0116 OODD 1A
SCAN
0111 OOOE 8E
011a OODF C2F500
0119 OUE2 13
0120 00E3 23
0121 00E4 00
0122 OOE~ C2DDOO
0123 00E8 3E02
0124 OOEA 0305
0125 OOEC 3AC040 N02
0126 OOEF D304
0121 00F1 00
NOl
0128 00F2 C3F100
0129*
0130 OOF5 3E04
TRMERR
0131 00F7 0305
0132 00F9 C3ECOO
0133*
0134 OOFC 23
YET
0135 OOFO 1.3
0136 OOFE C.31400
0131*
0138*** NO-PASS SUM ***
0139*
MITSUBISHI
ELECTRIC
LOA
ORA
JNZ
LOA
XCHG
MOV
OCR
XCHG
FLAG
A
SUM
TEMPRY
JNl
YET
AtOO*
05#
AtS
02#
S2ENO
TIMEC
At69'
00#
A t0211
03.
A,OZ*
011
A
011
A t03.
03'
TIMED
A tOAl'
01'
AtOOIl
0311
A
0311
AtOBII
01#
0011
68#
NOCOMC
A ,01#
0511
H tRAHST
OtH
E,L
8
RPT2
Ct200
D"tROM2S T
D
M
TRMERR
D
H
C
SCAN
A ,0211
0511
COUNT
04#
MVI
OUT
MOV
CPI
JNl
CALL
MVI
OUT
MVI
OUT
MVI
OUT
INR
OUT
MVI
OUT
CALL
MVI
OUT
MVI
OUT
INR
OUT
MV!
OUT
IN
SUI
JNZ
MVI
OUT
LXI
MOV
MOV
OCR
JNZ
MVI
LXI
LDAX
CMP
JNZ
!NX
INX
OCR
JNZ
MVI
OUT
LOA
OUT
NOP
JMP
MtA
C
NOI
MVI
OUT
JMP
A t04'
OS.
N02
INX
INX
JMP
D
H
RPT 1
15-109
MITSUBISHI MICROCOMPUTERS
APPLICATION OF MELCS8/2 SINGLE-BOARD COMPUTER
(PCA 0801) IN DATA TRANSMISSION
THROUGH A MASTER-SLAVE MULTICOMPUTER SYSTEM
0140 0101 3AC040 SUM
LOA
0141 0104 3C
INR
0142 0105 32C040
5TA
0143 OlOd C37400
JMP
0144*
0145*
0146*** NOCOMMUNICATE ***
0147*
0148 010B 3E04
NOCOMC MVI
0149 0100 0305
OUT
0150 OlOF C3F100
JMP
0151*
0152*** SUBROUTINE TIMEC ***
0153*
0154 0112 1E32
TIMEC MVI
0155 0114 C02E01 T I ME C 1 CALL
0156 0117 10
OCR
0157 011B CA1E01
JZ
0158 011B C31401
JMP
0159011E C9
TIMEC2 RET
0160*
0161*
0162*
0163*** SUBROUTINE TIMEF ***
0164 011F 05
T I MEF PUSH
0165 0120 lEOA
MVI
0166 0122 C02EOl TIMEFI CALL
0167 0125 10
OCR
0168 0126 CA2C01
JZ
0169 0129 C32201
JMP
0170 0120 01
T I ME F2 POP
0171 0120 C9
RET
0172*
0173*** SUBROUTINE TIMEO ***
COUNT
A
COUNT
RPTl
A,0411
05#
NOI
E,50
TIMEO
E
TIMEC2
TIMEC1
D
E,10
TIMED
E
TIMEF 2
TIM EF 1
0
0174*
0175 012E F5
TIMED PUSH
0176 012F C5
PUSH
0177 0130 D5
PUSH
0178 0131 E5
PUSH
0179 0132 1614
MVI
0180 0134 OEl4
MVI
0181 0136 06C8
TIMED6 MV!
0182 0138 3EC8
~1V I
0183 013A C33DOl TIMEDI JMP
0184 0130 C34001 TH1ED2 JMP
0185 0140 05
T I ME 03 OCR
0186 0141 3D
DCR
0187 0142 CA4801
JZ
0188 0145 C33AOl
JMP
0189 014B 15
TIMED4 OCR
0190 014.9 00
DCR
0191 014A CA5001
JZ
0192 014D 03601
JMP
0193 0150 E1
TIME07 POP
0194 0151 01
PCP
0195 0152 Cl
POP
0196 0153 F1
POP
0197 0154 C9
RET
0198*
0199*
0200*** SUBROUTINE MO ***
0201*
0202 0155 0300
MO
OUT
0203 0157 05
PUSH
0204 0158 11 0202
LXI
0205 015B C06801
CALL
0206 015E 01
POP
0207 015F C9
RET
0208*
0209*
0210*** SUBROUTINE HI ***
15-110
PSW
8
D
H
D,20
C,20
B,200
A,200
TP1E02
TH1ED3
8
A
TIMED4
TIMED1
D
C
TIMED7
TIMED6
H
D
B
PSVI
00*
D
0,20211
OECODO
D
021h
M10212 0160 05
PUSH
0213 0161 110202
LXI
0214 0164 CDA2en
CALL
0215 0167 0800
IN
0216 0169 01
POP
0217 016A C9
RET
0218*
0219*
0220*** SUBROUTINE OECOOO ***
0221*
0222 016B E5
OECOOO PUSH
0223 016C 05
PUSH
0224 0160 2AC840
LHLO
0225 0170 01301
MIBF
IN
0226 0172 A6
ANA
0227 0173 C29BOl
JNZ
0228 0176 3£02
MVI
0229 017B 0303
OUT
0230 017A 23
INX
0231 017B 7E
MOV
0232 017C 0307
OUT
0233 017E 3C
INR
0234 017F 0307
OUT
0235 0181 3E03
MVI
0236 0183 0303
OUT
02.37 01B~ 79
MOV
0238 0186 0601
SUI
02J9 0188 CA9701
JZ
0240 0188 28
DCX
0241 018C 22C840 STORE 1 SHLO
0242 OlaF 3E24
MVI
0243 0191 32CC40
STA
0244 0194 01
NOIBF POP
0245 019~ El
POP
0246 0196 C9
RET
0247 01n 23
FINEI
INX
0248 0198 C38COl
JMP
0249 019B 15
MIBF P OCR
0250 019C C27001
JNZ
02~ 1 019F C39401
JMP
0252*
0253*
0254*** SUBROUTINE OE COD I * **
0
0,20211
DECOO I
0011
0
H
0
DSTNT1
01#
~1
t-1IBFP
A,0211
0311
Ii
A,M
0711
A
071#
A',0311
0311
A,C
01#
fINEl
H
OSTNT1
A ,2411
FLAG
0
H
H
STOREI
D
MIBF
NOIBF
02~5*
0256
0257
0258
0259
0260
0261
0262
0263
0264
0265
0266
0267
0268
0269
0270
0271
0272
0273
0274
0275
0276
0277
0278
0279
0280
0281
J.. MITSUBISHI
ELECTRIC
01 A2
01A3
01 A4
01A7
01 A9
01AA
OlAO
01 AE
OlAF
01B1
01B3
0185
01B7
01B9
01BA
01BS
01BD
01BE
01CO
01C3
01C4
01C7
01CA
01 CC
01CF
0100
E5
05
2ACA40
DBOI
A6
C20601
23
7E
0307
3EOO
0303
3E01
0303
7E
3C
0307
79
0601
CAD201
2B
22CA40
3ACC40
0624
32CC40
01
El
DECODI PUSH
PUSH
LHLO
M08F
IN
ANA
JNZ
INX
MOV
OUT
MVI
OUT
MVI
OUT
MOV
INR
OUT
MOV
SUI
JZ
DCX
STOREZ SHLD
LDA
SUI
STA
NOOBF POP
POP
H
D
OST NT 2
0111
'"
~OBFP
H
A,M
07#
A ,0011
03*
A,Olll
03*
A,M
A
07f1
A,C
OU
FINE2
H
OSTNT2
FLAG
24*
FLAG
D
Ii
MITSUBISHI MICROCOMPUTERS
APPLICATION OF MELCS 8/2 SINGLE-BOARD COMPUTER
(peA 0801) IN DATA TRANSMISSION
THROUGH A MASTER-SLAVE MULTICOMPUTER SYSTEM
RET
0282 OlDl C9
FINE2
H
0283 0102 23
INX
JMP
0284 0103 C3C401
STORE2
MOBFP DCR
0285 0106 1D
E
MOBF
02B6 0107 C2A701
JNl
JMP
0287 OIDA C.3CFOI
NOOI3F
0288*
0289*
0290*
SELECTIVE CHARACTER Cl TEI GI SURU *
DEF
OlN
0291 01 OD 01
X
00#
0292 OlOE 00
DEF
0293 010F 02
OEF
0211
02#
0294 OlEO 02
DEF
0295
0296
0291
0298
0299
'0300
0301
0302
0303
0304
0305
0306
0307
01El
01E2
01 E3
01E4
01 ES
01 E6
01E7
01E8
01E9
OlEA
01EB
01EC
0000
04
04
08
06
10
08
20
OA
40
OC
80
OE
Y
QEF
DEF
OEF
DEF
DEF
DEF
DEF
DEF
DEF
DEF
DEF
DEF
END
04#
0411
08#
0611
lOll
08#
20#
OAII
4-0#
OCII
60H
OE#
MASTER
SLAVE MICROCOMPUTER MAIN PROGRAM LIST
**CROSS ASSEMBLER OF 8-BIT MICROPROCESSOR
0001*** SLAVE MICROCOMPUTER MA I N P-ROuRAM ***
0002*
0003*
0004 4000
RAMST EOU
400011
0005 4000
SCRTCH EQU
40DO#
0006 4001
F1
EQU
4001*
0007 4002
F2
EOU
40D211
0008*
0009 0000
ORG
000011
0010 0000 .3ECO
SLAVE MV I
A,COII
0011 0002 D303
OUT
0311
0012 0004 3£ 81
MVI
A ,8'1#
0013 0006 0307
OUT
0711
0014 0008 31FF40
LXI
SP,4CFFII
0015 0008 DBOO
WAIT
IN
0011
0016 0000 0669
69#
SUI
0017 OOOF C20BOO
JNZ
WAIT
0018 0012 3E6B
MVI
A,6BII
0019 0014 D300
OUT
0011
0020 0016 AF
XRA
A
0021 0017 320140
Fl
STA
0022 O.olA 320240
F2
STA
0023 0010 110202
0,20211
LXI
0024 0020 210040
H ,RAMST
LXI
0025 0023 CD 5 50 0 BACK 1 CALL 5 I
0026 0026 2F
CMA
0027 0027 320040
STA
SCRTCH
0028 002A 3A0140
F1
LDA
0029 002D B7
ORA
A
0030 002E (A4000
JZ
NOPASI
0031 0031 3A0040
LOA
SCRTCH
00.32 0034 C07100
CALL sa
0033 0037 3AD240
F2
LDA
0034 003A B7
A
ORA
0035 003B CA ~ 1 0 0
JZ
NOPAS2:
0036 003E 3A0040
LDA
SCRTCH
0037 0041 77
M,A
MOV
0038 0042 23
INX
H
0039 0043 7D
A,L
MOV
0040 0044 FECS
C8#
CPI
0041 0046 OA2300
BACK]
JC
0042 0049 00
NO
NOP
0043 004A C34900
JMP
NO
0044*
0045*** NOPASS 1 ***
0046*
0047 0040 37
NOPASI STC
0048 004E C32300
JMP
BAC Kl
0049*
0050*** NOPASS 2 ***
0051 0051 3F
NOPA 52 CMC
0052 0052 C32300
JMP
BACKI
0053*
0054
EJE
J..
0055*
0056*** SUBRClur INE 51 ***
0057*
0058 0055 D5
PUSH
SI
0059 0056 D802
SIBF
IN
0060 0058 E620
ANI
0061 005A C26700
JNZ
0062 0050 15
OCR
0063 005E C25600
JNZ
0064 0061 AF
XRA
0065 0062 320140
STA
0066 0065 01
SIND
POP
0061 0066 C9
RET
0068 0067 3E01
SIN
MVI
0069 0069 32D 14 0
STA
0070 006C DBOO
IN
0071 006E C36500
JMP
0072*
0073*
0074*** SUBROUTINE SO ***
0075*
0076 0071 F5
SO
PUSH
0071 0072 D5
PUSH
0078 0073 DB02
SOBF
IN
0079 0075 E6S0
ANI
0080 0077 C28 50 0
JNZ
0081 007A 10
OCR
0082 0078 C27300
JNZ
0083 007E AF
XRA
0084 007F 320240
STA
0085 0082 D1
POP
0086 0083 F1
PCP
0087 0084 C9
RET
0088 0085 3E01
sour
MVI
0089 0087 32D240
STA
0090 008A Dl
POP
0091 0088 Fl
POP
0092 008C D300
OUT
0093 D08E C9
RET
0094 0000
END
MITSUBISHI
ELECTRIC
D
02#
2011
SIN
D
SIBF
A
F1
0
A,OU
Fl
00#
SIND
PSW
0
02#
80#
SOUT
E
SOBF
A
F2
0
P,SW
A,Olll
F2
D
PSW
OOW
SLAVE
15-111
CONTACT ADDRESSES FOR·FURTHER INFORMATION
JAPAN
Electronics Marketing Division
Mitsubishi Electric Corporation
2-3, Marunouchi 2-chome
Chiyoda-ku, Tokyo 100, Japan
Telex:
24532 MELCO J
Telephone: (03) 218-3473
(03) 218-3499
HONG KONG
Ryoden Electric Engineering Co., Ltd.
22nd fl., Leighton Centre
77, Leighton Road
Causeway Bay, Hong Kong
Telex:
73411 RYODEN HX
Telephone: (5) 790-
Mitsubishi Electric Corporation
Taipei Representative Office
Room 1303, 13th fl., Huei Fong Bldg.
27, Sec. 3, Chung Shan N. Road
Taipei, R.O.C.
Telex:
11211 MITSUBISHI
(597) 3111
Mitsubishi ElectrOnics America, Inc.
1230 Oakmead Parkway
Suite 206 Sunnyvale CA 94086 U.S.A.
Telex:
172296 MELA SUVL
Telephone: (408) 730-5900
Mitsubishi Electronics America, Inc.
2200 West Artesia Blvd.
Compton CA 90220, U.S.A.
Telex:
698246 MELA CMTN
Telephone
(213) 979-6055
Mitsubishi Electronics America, Inc.
200 Unicorn Park Drive
Woburn, MA 01801, U.S.A.
Telex:
951796 MELASB WOBN
Telephone: (617) 938-1220
WEST GERMANY
Mitsubishi Electric Europe GmbH
Brandenburger Str. 40
4030 Ratingen, West Germany
Telex
8585070 MED D
Telephone: (02102) 4860
U.K.
Mitsubishi Electric (U.K.) Ltd.
Polycherome House Sandown Road
Watford, Hearts, U.K.
Telex:
927908
Telephone: (923) 37334
AUSTRALIA
Melco Australia Pty. Ltd.
33rd Level, Australia Square,
Sydney, N.S.W., 2000, Australia
PO. Box H 129, Australia Square
Telex:
MESYO AA 26614
Telephone: (232) 6277
• MITSUBISHI
"ELECTRIC
1982 MITSUBISHI DATA BOOK
LSI
AMITSUBISHI ELECTR!C CORPORATION
HEAD OFF~CE: MITSUBISHI DENt<1 BLDG, MARUNOUCHI, TOKYO 100, TELEX)24532 CABLE: MELeo TOKYO
H-C4024-C 1<.1-8201 Printed in Japan (TOTI
Revised publication, effective Dec. 1981,
supersed:ng pubiicatlon H -C4024[3 of Apr 1981
Specificiltions subject to change without Ilotice
Source Exif Data:
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