1982_Mostek_Microelectronic_Data_Book 1982 Mostek Microelectronic Data Book
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1982/1983
MICROELECTRONIC
DATA BOOK
Copyright © 1982 Mostek Corporation (All rights reserved)
Trade Marks Registered ®
Mostek reserves the right to make changes in specifications at any time and without notice, The information furnished by
Mostek in this publication is believed to be accurate and reliable, However, no responsibility is assumed by Mostek for its use;
nor for any infringements of patents or other rights of third parties resulting from its use, No license is granted under any
patents or patent rights of Mostek,
The "PRELIMINARY" designation on a Mostekdata sheet indicates that the product is not characterized, The specifications
are subject to change, are based on design goals or preliminary part evaluation, and are not guaranteed, Mostek Corporation
or an authorized sales representative should be consulted for current information before using this product, No responsibility
is assumed by Mostek for its use; norfor any infringements of patents and trademarks or other rights ofthird parties resulting
from its use, No license is granted under any patents, patent rights, or trademarks of Mostek, Mostek reserves the right to
make changes in specifications at any time and without notice,
PRINTED IN USA May 1982
1982/1983 MICROELECTRONIC DATA BOOK
Table of Contents
0) General Information
1111
Read Only Memory
Dynamic Random Access Memory
Static Random Access Memory
68000 Family
~
Z80Family
@] 3870 Single Chip Family
Microcomputer Peripherals
@) Programmed Microcomputer Products
68000, Z80, and 3870 Development System Products
@) Military HI-Rei Memories
@fMicroprocessor and Support Devices
8)
Industrial Hi-Rei Products
Iii
1982/1983 MICROELECTRONIC DATA BOOK
0)
Table of Contents
TABLE OF CONTENTS
I.
Table of Contents
Functional Index ....................................................................... 1-1
II.
General Information
Mostek Profile ......................................................................... 11-1
Package Descriptions ................................................................... 11-5
Order Information ..................................................................... 11-13
U.S. and Canadian Sales Offices ........................................................ 11-15
U.S. and Canadian Representatives .................................................•.... 11-16
U.S. and Canadian Distributors .......................................................... 11-17
International Marketing Offices ......................................................... 11-19
MEMORY COMPONENTS
III.
Read-Only Memory
MK36000(P/J/N) Series .............................................................. 111-1
MK37000(P/J/N) Series .............................................................. 111-5
MK38000 (P IN)-25 ................................................................... 111-9
Guidelines for Submitting and Verifying Customer ROM Patterns ........................... 111-13
IV.
Dynamic Random Access Memory
MK4027 (J/N)-2/3 . ............................................... " .................. IV-l
MK4027 (J/N)-4 ..................................................................... IV-13
MK4116 (J/N/E)-2/3 ................................................................ IV-17
MK4116 (J/N/E)-4 . .................................................................. IV-27
MK4516(N/J)-10/12/15 ............................................................ . IV-31
MK4528 (D)-15/20/25 ............................................................... IV-41
MK4332 (D)-3 ....................................................................... IV-51
MK4564 (PI J/N)-15/20/25 .......................................................... IV-63
V.
Static Random-Access Memory
MK41 04 (J/N/E) Series ............................................................... V-l
MK4118A/4801A(P/J/N) Series ....................................................... V-7
MK4801 A (P/J/N) Series ............................................................. V-13
MICROCOMPUTER COMPONENTS
VI.
68000 Family
MK68000
MK68200
MK68230
MK68564
MK68901
MK68590
MK3891
VII.
CPU
MCU
PIIT
SIO
MFP
LANCE
SIA
Central Processing Unit ......................................... VI-l
16-Bit Microcomputing Unit .................................... VI-51
Paraliellnterface/Timer ........................................ VI-59
Seriallnput/Output Controller .................................. VI-95
Multi-Function Peripheral ..................................... VI-l 03
Local Area Network Controller for Ethernet ...................... VI-113
Serial Interface Adapter ....................................... VI-121
CPU
PIO
CTC
DMA
SIO
SI0/9
DART
STI
Central Processing Unit ........................................ VII-l
Parallel 1/0 Controller ......................................... VII-9
Counter Timer Circuit ....................................... " VII-17
Direct Memory Access Controller ............................. " VII-25
Seriallnput/Output Controller ................................. VII-43
Single Channel Seriallnput/Output Controller ................... VII-59
Dual Asynchronous Receiver Transmitter ........................ VII-63
Serial Timer Interrupt Controller ................................ VII-75
Z80 Family
MK3880
MK3881
MK3882
MK3883
MK3884/5/7
MK3884/517
MKDART
MK3801
1-1
VIII.
3870 Single Chip Family
3870 Family Selection Guide .......................................................... VIII-1
MK3870/38P70
Single Chip Microcomputer ...................................... VIII-3
MK2870
28 Pin Microcomputer ......................................... VIII-31
MK3873/38P73
Serial Port Microcomputer ...................................... VIII-49
MK3875/38P75
Standby RAM Microcomputer ................................... VIII-79
IX.
Microcomputer Peripherals
MK3805N/MK3806N
MK3807 (P)
X.
Programmed Microcomputer Products
SCU20
XI.
CMOS Microcomputer Clock/RAM ................................ IX-1
Programmable CRT Video Control Unit VCU ........................ IX-ll
Serial Control Unit ............................................... X-1
68000, Z80 and 3870 Development System Products
RADIUS
AIM-Z80BE
AIM-7XE
MATRIX
EVAL-70
PPG 8/l6C:
SO to SDE Adapter
MACRO 80
MACRO 70
FLP 80 DOS
M/OS-80
MOSGEN
Remote Development Station ..................................... XI-l
Application Interface Module for Z80 ............................... XI-5
Application Interface Module for 3870 Series ........................ XI-9
Development System ........................................... XI-13
3870EvaluationSystem ........................................ XI-23
PROM Programmer ............................................. XI-29
.............................................................. XI-33
Z80 Macro Assembler .......................................... XI-35
3870 Macro Assembler ......................................... XI-37
Disk Operating System .......................................... XI-39
(CP/M Like OS) ................................................ XI-43
Utility Software ................................................ XI-47
MILITARY PRODUCTS
XII.
Military/High Reliability Memories
Introduction ......................................................................... XII-l
Test Report ...................................... , ................................... XII-7
MKB2716 (J/E)-86/87/88/90 ....................................................... XII-15
MKB36000 (PI J)-80/83/84 . ......................................................... XII-2l
MKB37000 (PI J/E)-84/85 ........................................................... XII-25
MKB38000(P/J/E)-84/85 ........................................................... XII-3l
MKB4027 (J)-83/84 ................................................................ XII-35
MKB4l04 (PI J/E)-84/85 ............................................................ XII-39
MKB4ll6(P/J)-82/83/84, MKB4ll6 (E/F)-83/84 ..................................... XII-43
MKB4ll8A(P/J/E)-82/83/84 ....................................................... XII-47
MKB4l67 (PIJ)-870/855/80 ........................................................ XII-53
MKM4332 (0)-83/84 ................................................................ XII-59
MKB4516(P/J/E)-80/81/82 ........................................................ XII-65
MKM4528 (0)-83/84 ................................................................ XII-75
MKB4564 (PIE)-82/83/84 ........................................................... XII-77
MKB4801A(P/J/E)-870/890/8l ..................................................... XII-87
MKB4802(P/J/E)-8l/83 ............................................................ XII-93
XIII.
Microprocessor and Support Devices
MKB3880 (P)-80/84
CPU .......................................................... XIII-1
MKB3881 (P)-80/84 ................................................................. XIII-9
MKB3882 (P/J)-80/84 .............................................................. Xill-ll
MKB68000 ........................................................................ XIII-13
XIV.
Industrial Hi-Rei Products
Introduction ......................................................................... XIV-l
MKI27l6(J)-77/78 .................................................................. XIV-7
MK13880-70174
CPU ......................................................... XIV-ll
MK13881-70174
PliO Controller .............................................. XIV-19
MKI3882(P/J)-70174 CTC ........................................................ XIV-2l
MKI4ll6 (J)-72/73/74 ............................................................. XIV-23
1-2
TELECOMMUNICATIONS
Information on the following Mostek telecomunications
circuits is contained in the 1982 Telecommunications Data
Book which is available separately.
Integrated Tone Dialers
MK5087 Integrated Tone Dialer
MK5089 Integrated Tone Dialer
MK5087/89 Electronic Drive Application Brief
MK5091 Integrated Tone Dialer
MK5092 Integrated Tone Dialer
MK5094 Integrated Tone Dialer
MK5380 Integrated Tone Dialer
MK5382 Integrated Tone Dialer with Redial
Integrated Dialer Comparison - Tone II vs Tone III Application Brief
Loop Simulator Application Brief
Integrated Pulse Dialers with Redial
MK50981 Integrated Pulse Dialer with Redial
MK50982 Integrated Pulse Dialer with Redial
MK50991 Integrated Pulse Dialer with Redial
MK50992 Integrated Pulse Dialer with Redial
Current Sources Application Brief
Pulse Dialer Comparison Application Brief
Repertory Dialers
MK51 70 Repertory Dialer
MK5175 Ten-Number Repertory Dialer
Integrated Tone Decoders
MK51 02-5 Integrated Tone Receiver
MK51 02-5 DTMF Decoder Application Note
MK5102/S3525A DTMF Receiver System Application Brief
MK51 03-5 Integrated Tone Decoder
DTMF Receiver System Application Brief
Active Speech Networks
MK5242 Active Speech Network
CODECs
MK5116 w255 Law Companding CO DEC
MK5151 W255 Law Companding CO DEC
MK5156 A-Law Companding CODEC
MK5316 Companding CODEC with Filters
Integrated PCM CODEC Technology Update
Transmit/Receive Filter
MK5912-3 PCM Transmit/Receive Filter
CODEC/Filter Demo Board Application Brief
1-3
INDUSTRIAL PRODUCTS
Information on the following Mostek industrial circuits is
contained in the 1981 Industrial Products Data Book which is
available separately.
Frequency Generator
MK50240/1 12 Top-Octave Frequency Generator
Digital Alarm Clock
"MK50250 Series MOS Digital Alarm Clock
Counter/Display Decoders
MK5002/517 Four-Digit CounterIDisplay Decoder
MK5002/7 Application Note
MK50395/617 Six-Decade Counter/Display Decoder
MK50395/617 Application Note
MK5039S/9 Six-Decade CounterIDisplay Decoder
Counter /Time- Base Circuit
MK5009 Counter Time-Base Circuit
MK5009 Application Note
IJP-Compatible A/D Converters/Analog Multiplexers
MK51 6S-1 j.tP-Compatible AID Converter
MK50S0S Eight-Bit AID ConverterIS-Channel Analog Multiplexer
MK50S16 Eight-Bit AID Converter/16-Channel Analog Multiplexer
AID Converter Demo System Application Brief
"Not Recommended For New Design
1-4
1982/1983 MICROELECTRONIC DATA BOOK
0)
\
General Information
........
-~
i.............. _.vv=
•...............••.....•
Iill
~----
~-~-----
---~-~--
Mostek - Technology For Today And Tomorrow
I
tested and by how well it works in your
system.
In design, production and testing, the
Mostek goal is meeting specifications the
first time on every product. This goal requires
a collective discipline from the company as
well as individual efforts. Discipline, coupled
with very personal pride, has enabled
Mostek to build in quality at every level of
production.
TECHNOLOGY
From its beginning, Mostek has been an
innovator. From the developments of the 1K
dynamic RAM and the single-chip calculator
in 1970 to the current 64K dynamic RAM,
Mostek technological breakthroughs have
proved the benefits and cost-effectiveness of
metal oxide semiconductors. Today, Mostek
represents one of the industry's most
productive bases of MOS/LSI technology,
including Direct-Step-on-Wafer processing
and laser implemented redundant circuitry.
The addition of the Microelectronics
Research Center in Colorado Springs adds a
new dimension to Mostek circuit design
capabilities. Using the latest computer-aided
design techniques, center engineers will be
keeping ahead of the future with new
technologies and processes.
PRODUCTION CAPABILITY
The commitment to increasing production
capability has made Mostek the world's
largest manufacturer of dynamic RAMs. We
entered the telecommunications market in
1974 with a tone dialer, and have shipped
millions of telecom circuits since then.
Millions of our MK3870 single-chip
microcomputers are in use throughout the
world. Recent construction in Dallas, Ireland
and Colorado Springs has added some
50 percent to the Mostek manufacturing
capacity.
QUALITY
The worth of a product is measured by
how well it is designed, manufactured and
11-1
Memory Products
Through innovations in both circuit design,
wafer processing and production, Mostek
has become the industry's leading supplier
of dynamic RAMs.
Examples of Mostek leadership are
families of xl and x8 high performance static
RAMs and our extremely successful 64K
ROMs with more codes processed than any
other mask-ROM in the industry. Another
performance and density milestone is our
256K ROM, the MK38000. In MOS DynamiC
RAMs, Mostek led the way as the world's
leading supplier of 16K devices.
Our MK4564 64K dynamic RAM uses
advanced circuit techniques and design to
enhance manufacturabiiity to satisfy the
demands of a huge marketplace.
THE PRODUCTS
Telecommunications Products
Mostek is the leading supplier of tone
dialers, pulse dialers, and CODEC devices.
As each new generation of telecommunications systems emerges, Mostek is
ready with new generation components,
including PCM filters, tone decoders,
repertory dialers, new integrated tone
dialers, and pulse dialers.
These products, many of them using
CMOS technology, represent the most
modern advancements in telecommunications component design.
Microcomputer Components
Mostek's microcomputer components
cover the entire spectrum of microcomputer
applications.
Our MK68000 16-bit microprocessor is
designed for high-performance, memoryintensive systems.
Our Z80 is today's industry~standard 8-bit
microprocessor. The Mostek 3870 family of
single-chip microcomputers offers upgrade
options in ROM, RAM, and I/O-all in the
same socket. The MK38P70 EPROM
piggyback microcomputer emulates the
entire family and is ideal for low-volume
applications.
Industrial Products
Mostek's line of Industrial Products offers
a high degree of versatility per device. This
family of components includes various
microprocessor-compatible AID converters,
a counterItime-basecircuit for the division
of clock signals, and combined
counterI disp.lay decoders. As a result of the
low parts count involved, an economical
alternative to discrete logic systems is
provided.
11-2
rigors of MIL-M-38510 and are processed on
our QPL certified lines.
The MKB product line begins with the
complete Memory Products offering, and
extends into microprocessors and gate
arrays. Leadless Chip Carrier packaging and
prepared customer SCDs address the
particular needs of the military community.
Development systems include the
RADIUSTM remote development station that
lets you use your host minicomputer to
develop the applications software. The
program is then downloaded into the
RADIUS which then lets you perform realtime in-circuit emulation and debug. The
Mostek Matrix™ Development System is a
stand-alone hardware and software debug
and integration system.
Memory Systems
Mostek is the world's leading manufacturer of Z80-based STD BUS system
components. A new line of microsystems
utilizing the VME BUS and based on the
MK68000 will be available soon.
Computer systems include our Matrix line
which utilize STD BUS cards to let you
custom-design your own system.
Taking full advantage of our leadership in
memory components technology, Mostek
Memory Systems offers a broad line of
products, all with the performance and
reliability to match our industry-standard
circuits. Mostek Memory Systems offers addin memory boards for popular DEC, Data
General, and Perkin-Elmer minicomputers.
Mostek also offers special purpose and
custom memory boards for special applications.
Military Products
Gate Arrays
An extension of the high quality in
fabrication and design inherent in Mostek's
product line allows many of our ICs to be
made available screened to MIL-STD-883. In
addition, select parts are qualified to the
Utilizing the technology developed by
United Technologies Microelectronic
Research Center, Mostek plans to market
custom gate array circuits in the second half
of 1982.
Microcomputer Systems
11-3
11-4
MOSTEI{.
MICROELECTRONIC PRODUCTS
Package Descriptions
Plastic Dual-In-Line Package (N)
40 Pin
JWTE'ov..II .............. '010_ .... _ _ "' .......
Ceramic Dual-In-Line Package (P)
40 Pin
I
2025MAlC
I
.
l---r f
~ ~~'I
I_~N
--±::I
'L±
,.oM"
.
:
~I
-
1UQUAlSPACES ·.100
P-PROM Package (R)
40 Pin
11-5
1900
t
"f--ill--l
~
III
1
0
LJl
Leadless Hermetic Chip Carrier (E)
32 Pin (Proposed JEDEC Type E)
1. MIIlIIhickneH.fullows.
106£PftOM
f---i':.,---j
8EE NOTE 1
:!Llli~~~
Plastic Dual-In-Line Package (N)
28 Pin
Ceramic Dual-In-Line Package (P)
28 Pin
I
_1----1
'ADO, ...,
L""'''=1
H"~'I
i ~
ru='mw~~
I
.
I
-
.000MIN.
.,~ ~1---.''''.OO3 ~~:"'.
L~--J
0"·0"
c
....
C
13EOUALS"ACI8@1oo
Cerdip Hermetic Package (J)
28 Pin
.
I
I
I
;; -'1'00 ~±3
;
L II±Nt·J-lOO NOM-j
r ' 3 EOUALSPACES AT .100 EACH
11-6
.'.M'N.
~
..... ,---------L
~
."
Plastic Dual-In-Line Package (N)
24 Pin
~II
.
L.~,~,-J,
Ceramic Dual-In-Line Package (P)
24 Pin
I
_._I~
>'>00'.'00
·"·"·
nwr~--~-,.".
!
I II I
:J L~ I
;;or I
""':L 1
l
--ll-',"''''
11 EQI,JALSPACES@.lGO------J
"0
JC:] J'
Cerdip Hermetic Package (J)
24 Pin
"70MAX---
I
~61::P-l
r-:O;O-=!I ~
A
mN~
II
I~-~
i
r L i±f
200 MAX
I
~
I
II
100 t-O~1:o3
,,-eQUAL SPACES
11-7
~~
!~~6
(n'
.100
-au
I--(.
650 NOM
---+j(
.
[]O
. .OO'lT
l
lw
'O~"
Wf
R
Ceramic Dual-In-line Package (P)
20 Pin
0
--1
~
~O
050, 015
I---
.98'
r,295:!: .015
.:,_.
'
I
-.-' I
~·II
I
~
1
,.015
'.
-=-------------.020
I -tI
MIN
'OO'O'O~ .~~b.3 ~~;~ I
012
1._.
I
~ 365-1
9EQUA~SPACES@.'00 ~
!'-----
oo.
-
290
(
(
1'''''''1
Leadless Hermetic Chip Carrier (E)
20 Pin
-E[O
.=.=.."""'II:~
rn-mrrttr==-.
1-",
~===>--'
=------.l
-t!0TTOM
"I
Plastic Dual-In-line Package (N)
18 Pin
11'030~.Q10
,
C:JQ
IV,
v v
v v
;;1
r~~~1
1---.850MAX.~
Lfr·~~·I~
~~II~
~::. W~'60'01,01"'~I--9
~'EO~ALSPACES
I
~IO.'OO
-I
I'
""T"
196
f
J",L
9
-.L
-=11
R
,~.350±05oj,
I
~
I'
·. DCOf
00
': =-=
NOTE, Overalilenglh ,ncludes ,010 flash on 8Ilhar end of package
Ceramic Dual-In-line Package (P)
18 Pin
V
050~'.015
.900:!: .016
I
~II lID~~'020
t
-~nrr
..~'!:1. ~.~~.~~
11-8
MIN
I
oo.
1m"
Dual-In-Line Double Density Ceramic Package (D)
18 Pin
L~oJ~::""
~
MIN.
.120
I
1
~1-018±003 d~!~
t
---r
8 EQUAL SPACES
AT .100± .008 EQUALS .800 ±.008
O.A.IT.N.A.l
00
Cerdip Hermetic Package (J)
18 Pin
'I
~~~,~'
~"OMAX
I--""Y'--l
ir- ;:~-=11 ~
mNm~A:tAX
IL
l
II
II 12{MIN f
II
\."0 ~:h03
-
,0:5.1
Oil
008
r-350NOM-
.~
8EQ.SP " 100 TNA
Leadless Hermetic Chip Carrier (E)
18 Pin (Proposed JEDEC Type F)
Figure A
~,,,o''''==1
Leadless Hermetic Chip Carrier (E)
18 Pin (Proposed JEDEC Type F)
ElL-=J
J
rFll.===.="'=.===.'11~~.
I
Figure B
11-9
Plastic Dual-In-Line Package (N)
16 Pin
,
1--.350
NOTE
Ceramic Dual-In-Line Package (P)
16 Pin
'050~,
Ove.all (ength incltxles ,010 flash on eOthac "nd of package
[][]Of
r-~',",.,,~ ~ I
i__ ,295± .015--l
~.095
,
1".o15~
~i I
.100
±.O1O~;
L
1-
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~ 1--- --JI
.018±.003
~ i -=CT"--:-T~;Z
:~~~
II
R
ITOLL
,
012
;
,
~'-7 EQUAL SPACES @.100-------lI
.
OOB
I
I
,rI
;
Ceramic Flat Package (F)
16 Pin
±
16
...
290..--1
.365
,
-I
±-r
.400
,050x7".350
-
± .005
f
,------B
± ,010
I
050
9
I
.0lD (TYP.)
\
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MAX
--r
±
007
t~~::]
t
Cerdip Hermetic Package (J)
16 Pin
·1
12.-035 ' 0 "
I . TYp~I
_____ .314
--7BOMAX-----------
',00
f.--II-
!1·0",.003
l
11-10
A
I-- 220--1
'I
'310
II
~
I,-,-.
"5M'N.
I~_I
- ~60
'.005
_ 7 EQUAL SPACES .• 100
,004
'T
200 MAX
---~
.-
I!----350NOM-----!I
012
Plastic Dual-In-Line Package (N)
8 Pin
III
68000 Family
Ceramic Dual-In-Line Package (P)
64 Pin
[~~]J
11+-.- - -
W
--------1.1
w'
MIWMETERS
DIM MIN MAX
A SO.52 82.04
B 22.25 22.96
4.32
C 3.05
D
0.38
0.63
F 0.76
1.40
2.54BSC
G
0.20 0.33
J
K
2.64
4.19
L 22.61 23.11
10·
M
N
1.02
1.52
Case 746.01
INCHES
MIN MAX
3.170 3.240
0.900 0.920
0.120 0.170
0.Q15 0.021
0.030 0.067
O..I00BSC
0.008 0.013
0.100 0.165
0.890 0.910
10·
0.020 0.060
NOTES:
1. DimenSionmis datum.
2. Positional tolerance for leads:
leolo.25(o.oI0)@ITI A@I
3.
is .eating plane.
rn
4.
Dimension "L" to center of leads
when formed parallel.
5.
11-11
Dimensioning and tolerancing per
ANSI Y14.6, 1973.
Ceramic Dual-In-Line Package (P)
48 Pin
LIUFFIX
CERAMIC PACKAGE
CASE 74Q-OZ
~ILLIMETERS
DIM
A
B
C
D
F
G
J
K
L
M
N
MIN
60.35
14.63
3.05
0.381
0.762
2.54
0.203
2.54
14.99
MAX
61.57
15.34
4.32
0.533
1.397
sse
0.330
4.19
15.65
O·
10·
1.016 1.524
INCHES
MIN MAX
2.376 2.424
0.576 0.604
0.120 0.160
0.015 0.021
0.030 0.055
·0.1008se
0.008 0.013
0.100 0.165
0.590 0.616
O·
10·
0.040 0.060
NOTES:
1. DIMENSION~IS DATUM.
2. POSITIONAL TOLERANCE FOR LEADS:
I "0.2S (0.01011 TJAMI
3·rn1S SEATING PLANE.
4. DIMENSION "L" TO CENTER OF
LEADS WHEN FORMED PARALLEL.
S. DIMENSIONING AND TOLERANCING
PER ANSI Y14.S, 1973.
11-12
ORDERING INFORMATION
Factory orders for parts described in this book should include a four-part number as explained below:
f-t
Example: IMKII41671
~1.
Dash Number
2. Package
' - - - - - - - - 3. Device Number
' - - - - - - - - - 4. Mostek Prefix
1.
Dash Number
One or two numerical characters defining specific device performance characteristics and operating
temperature range.
2.
Package
P
J
N
K
T
E
D
F
3.
-
Device number
1XXX
2XXX
3XXX
38XX
4XXX
5XXX
7XXX
4.
Gold side-brazed ceramic DIP
CER-DIP
Epoxy DIP (Plastic)
Tin side-brazed ceramic DIP
Ceramic DIP with transparent lid
Ceramic lead less chip carrier
Dual density RAM-PAC
Flat pack
or 1XXXX - Shift Register, ROM
or 2XXXX
ROM, EPROM
or 3XXXX - ROM, EPROM
- Microcomputer Components
or 4XXXX - RAM
or 5XXXX - Counters, Telecommunication and Industrial
or 7XXXX - Microcomputer Systems
Mostek Prefix
MK - Standard Prefix
MKB - Military Hi-Rei screening to MIL-STD-883 Class B for extended temperature range operation.
MKI - Industrial Hi-Rei screening for -40°C to +85°C operation.
11-13
I
11-14
U.S. AND CANADIAN SALES OFFICES
II
CORPORATEHEAOQUARTERS
Southeast U.S.
Mostek Corporation
Mostek
13~07 N. Dale Mabry Highway
SUite 201
1215 W. Crosby Rd.
P. O. Box 169
Carrollton, Texas 75006
Michigan
Western Region
Mostek
Orchard Hill Place
Mostek
21333 Haggerty Road
SUite 321
Novi, MI 48050
Tampa, Florida 33618
813/962-8338
TWX 810-876-4611
Northern California
1762 Technology Drive
Suite 126
San Jose, Calif. 95110
313/348-8360
408/287-5080
TWX 810-242-1471
TWX 910-338-2219
Central U.S.
Mostek
4100 McEwen Road
SUite 151
Dallas, Texas 75234
214/386-9340
TWX 910-860-5437
Seattle Region
Mostek
1107 North East 45th 5t.
SUlte411
Seattle, WA 98105
208/632-0245
TWX 910-444-4030
REGIONAL OFFICES
Northeastern Area
Mostek
49 W Putnam, 3rd Floor
Greenwich, Conn. 06830
203/622-0955
TWX 710-579-2928
Northeast U.S.
Mostek
29 Cummings Park, Suite #426
Woburn, Mass, 01801
617/935-0635
TWX 710-348-0459
Southeastern Area
Mostek
4001 B Greentree Executive Campus
Route #73
Marlton, New Jersey 08053
609/596-9200
TWX 71 0-940-01 03
Upstate NY Region
Mostek
4651 Crossroads Park Dr., SUite 201
liverpool, NY 13088
315/457-2160
~x 710-945-0255
Chicago Region
Mostek
Two Crossroads of Commerce
Suite 360
Rolling Meadows, III. 60008
312/577-9870
TWX 910-291-1207
Southwest Region
Mostek
4100 McEwen Road
Suite 237
DaUas, Texas 75234
214/386-9141
TWX 910-860-5437
North Central U.S.
Mostek
6101 Green Valley Dr.
Bloomington, Mn. 55438
612/831-232.2
TWX 910-576-2802
Chevy Chase #4
7715 Chevy Chase Dr., Suite 116
Austin, TX 78752
512/458-5226
TWX 910-874-2007
11-15
Southern California
Mostek
18004 Skypark Circle
Suite 140
Irvine, Calif. 92714
714/549-0397
TWX 910-595-2513
Arizona Region
Mostek
2150 East Highland Ave.
Suite 101
Phoenix, AZ 85016
602/954-6260
TWX 910-957-4581
u.s.
AND CANADIAN REPRESENTATIVES
ALABAMA
Conley & Associates. Inc.
3322 Memorial Pkwy.• S.W.
Suite 17
GEORGIA
MASSACHUSETTS
Conley & Associates, Inc
3951 Pleasantdale Road
New England Technical Sales·
Suite 201
135 Cambridge Street
Burling,on, MA 01803
NEW YORK
ERA Inc.
354 Veterans Memorial Highway
Commack, NY 11725
Huntsville, AL 35801
Doraville, GA 30340
6171272-0434
516/543-0510
205/882-0316
414/447-6992
TWX 710-332-0435
TWX 510-226-1485
TWX 810-726-2159
TWX 810-766-0488
ARIZONA
Summit Sates
7825 E. Redfield Rd.
ILLINOIS
Carlson Electronic Sales·
Scottsdale, A2 85260
Elk Grove Village, fL 60007
600 East Higgins Road
6021998-4850
312/956-8240
TWX 910-950-1283
TWX 910-222-1819
CALIFORNIA
Harvey King, Inc.
8124 Miramar Road
San ~iego, CA 92126
714/566-5252
TWX 910-335-1231
COLORADO
Waugaman Associates"
4800 Van Gordon
Wheat Ridge, CO 80033
303/423-1020
TWX 910-938-0750
CONNECTICUT
New England Technical Sales
240 Pomeroy Ave.
Meriden, CT 06450
2031237-8827
TWX 710-461-1126
FLORIDA
Conley & Associates, Inc."
P.O. Box 309
235 S. Central
Oviedo, FL 32765
305/365-3283
TWX 810-856-3520
Conley & Associates, Inc.
4021 W. Waters
Suite 2
Tampa, FL33614
813/885-7658
TWX 810-876-9136
Conley & Associates, Inc.
P.O. Box 700
1612 N.W. 2nd Avenue
Boca Raton, FL 33432
306/395-6108
TWX 510-953- 7548
INOIANA
Rich Electronic Marketing*
599 Indus~rial Drive
Carmel. IN 46032
317/644-6462
TWX 810-260-2631
Rich Electronic Marketing
3448 West Taylor St.
Fort Wayne, IN 46804
219/432-5553
Computer Marketing
241 Crescent St.l2nd Floor
319/393-0231
KANSAS
Rush & West Associates·
107 N. Chester Street
Olathe, KN 66061
9131764-2700
Wichita 316/683-0206
TWX 910-749-6404
KENTUCKY
Rich Electronic Marketing
8819 Roman Court
P. O. Box 91147
Louisville, KY 40291
502/499-7808
TWX 810-535-3757
Precision Sales Corp.
617/894-7000
710·324-1503
5 Arbustus Ln .• MR·97
Binghamton, NY 13901
607/648-3686
MICHIGAN
Action Components
21333 Haggerty Road
Suite 201
Novi, MI 48050
607/648-8833
313/349-3940
301/461-1323
TWX 710-862-1874
Precision Sales Corp. *
1 Commerce Blvd.
Liverpool. NY 13008
315/451-3480
TWX 710-545-0250
MINNESOTA
Cahill, Schmitz & Cahill, Inc."
315 N. Pierce
St. Paul, MN 55104
612/646-7217
TWX 910-563-3737
Precision Sales Corp.
3594 Monroe Avenue
Pittsford, NY 14534
716/381-2820
Micro Resources, Inc.
2700 Chowen Avenue South
Minneapolis, MN 55416
914/635-3233
MISSOURI
Rush & West Associates
481 Melanie Meadows Lane
Ballwin, MO 63011
314/394-7271
NORTH CAROLINA
Conley & Associates, Inc.
4050 Wake Forest Road
Suite 102
Raleigh, NC 27609
919/876-9862
TWX 510-928-1829
NEW JERSEY
Tritek Sales, Inc.
21 E. Euclid Ave.
Haddonfield, NJ 08033
609/429-1551
MARYLAND
Arbotek Associates
3600 St. Johns Lane
Ellicott City, MO 21043
800/645-5500. 55011
Waltham, MA 02154
TWX 810-332-1404
IOWA
REP Associates
980 Arica Ave.
Marion, IA 52302
(New Jersey Phone #
215/627-0149 (Philadelphia Line)
TWX 710-896-0881
NEW MEXICO
Waugaman Associates
P.O. Box 14894
Albuquerque, NM 87111
or
9004 Menaul NE
Suite 7
Albuquerque, NM 87112
505/294-1437
505/294-1436 (Ans. Service)
*Home Office
11-16
Precision Sales Corp.
Drake Road
Pleasant Valley, NY 12569
OHIO
The Lyons Corp.
4812 Frederick Rd.
Dayton, Ohio 45414
5131278-0714
TWX 810-459-1754
The Lyons Corp.
4615 N. Streetsboro Rd.
Richfield, Ohio 44286
216/659-9224
TWX 810-427-9103
OREGON
Northwest Marketing Assoc.
9999 S.W. Wilshire 51.
Suite 124
Portland OR 97225
5031297-2581
TELEX 910-464-6157
TENNESSEE
Conley & Associates, Inc.
1128 Tusculum Blvd.
Suite 0
Greenville, TN 37743
615/639-3139
TWX 810-576-4597
UTAH
Waugaman Associates
10332 South 1540 W
South Jordan, UT 84065
8011254-0570
or
801-254-0572
TWX 910-925-4073
WASHINGTON
Northwest Marketing Assoc. *
12835 Bellevue-Redmond Rd.
Suite 203E
Bellevue, WA 98005
206/455-5846
TWX 910-443-2445
WISCONSIN
Carlson Electronic Sales
Northbrook Executive Ctr.
10701 West North Ave.
Suite 209
Milwaukee, WI 53226
414/476-2790
TWX 910-222-1819
CANADA
Cantec Representatives Inc."
1573 Laperriere Ave.
Ottawa, Ontario
Canada K1Z 7T3
613/725-3704
TWX 610-562-8967
Cantec Representatives Inc.
15 Charles Street East
Kitchener, Ontario
Canada N2G2P3
519/744-6341
TWX 610-492-2683 (Toronto)
Cantec Representatives Inc.
8 Strathearn Ave, Unit 18
Brampton, Ontario
Canada L6T4L8
4161791 -5922
TWX 610-492-2683
Cantee Representatives Inc.
3639 Sources Blvd.
Suite 116
Dollard Des Ormeaux, Quebec
Canada H9B2K4
514/683-6131
TWX 610-422-3985
U.S. AND CANADIAN DISTRIBUTORS
ARIZONA
Kierulff Electronics
4134 E. Wood St.
Phoenix, AZ 85040
COLORADO
Arrow Electronics
2121 South HudsonSt
Denver, CO 80222
602/243-4101
13031758-2100
TWX 910/951-1550
Kierulff Electronics
1WX 910/931-0552
Kierulff Electronics
10890 E. 47th Avenue
Denver, CO 80239
303/371-6500
TWX 910/932-0169
'806 w. Grant Ad
Suite 102
Tucson, AZ 85705
602/624-9986
TWX 910/952-1119
CALIFORNIA
Arrow Electronics
4029 Westerly Place
Bldg. 15, Unit 113
Newport Beach, CA 92660
17141851-8961
TWX 910/595-2861
Arrow Electronics
19748 Dearborn St
Chatsworth, CA 91311
(213) 701-7500
TWX 910-493-2086
Arrow Electronics
9511 Ridgehaven Court
San Diego, CA 92123
17141 565-4800
TWX 910/335-1195
Arrow Electronics
521 Weddell Dr.
Sunnyvale, CA 94086
4081745-6600
TWX 910/339-9371
Kierulff Electronics
2585 Commerce Way
Los Angeles, CA 90040
213/725-0325
TWX 910/580-3106
Kierulff Electronics
3969 E. Bayshore Rd.
Palo Alto, CA 94303
415/968-6292
Kierulff Electronics
8797 Balboa Avenue
San Diego, CA 92123
714/278-2112
TWX 910/335-1182
Kierulff Electronics
14101 Franklin Avenue
Tustin, CA 92680
714/731-5711
TWX 910/595-2599
Schweber Electronics
17811 Gillette Avenue
Irvine, CA 92714
714/556-3880
TWX 910/595-1720
Schweber Electronics
3110 Patrick Henry Dr.
Santa Clara, CA 95050
408/496-0200
ZeuslWest, Inc.
1130 Hawk Circle
Anaheim, CA 92807
CONNECTICUT
Arrow Electronics
12 Beaumont Rd.
Wallingford, CT 06492
2031265-7741
TWX 710/476-0162
Schweber Electronics
Finance Drive
Commerce Industrial Park
Danbury, CT 06BlO
203/792-3500
TWX 710/456-9405
FLORIDA
Arrow Electronics
1001 N.W. 62nd St.
Suite 108
F1. Lauderdale, FL 33309
3051776-7790
TWX 510/955-9456
Arrow Electronics
50 Woodlake Dr.
Palm Bay, FL 32905
305/725-1480
TWX 510-959-6337
Diplomat Southland
2120 Calumet
Clearwater, FL 33515
813/443-4514
TWX 810/866-0436
Kierulff Electronics
3247 Tech Drive
St. Petersburg, FL 33702
813/576-1966
TWX 81 0/863-5625
GEORGIA
Arrow Electronics
2979 Pacific Drive
Norcross, GA 30071
404/449-8252
TWX 8101766-0439
Schweber Electronics
303 Research Drive, Suite 210
Norcross, GA 30092
404/449-9170
ILLINOIS
Arrow Electronics
492 Lunt Avenue
P. O. Box 94248
Schaumburg, IL 60193
312/893-9420
TWX 91 0/291-3544
Kierulff Electronics
1536 Landmeier Rd
Elk Grove Village, IL 60007
312/640-0200
TWX 9101222-0351
5chweber Electronics
904 Cambridge Dr
Elk Grove Village, IL 60007
312/364-3750
INDIANA
Advent Electronics
8446 Moller
Indianapolis, IN 46268
317/872-4910
TWX 81 0/341-3228
Arrow Electronics
2718 Rand Road
Indianapolis, IN 46241
3171243-9353
TWX 810/341-3119
Pioneer Electronics
6408 Castleplace Drive
Indianapolis, IN 46250
317/849- 7300
TWX 81 0/260-1794
IOWA
Advent Electronics
682 58th Avenue
Court South West
Cedar Rapids, IA 52404
319/363-0221
TWX 910/525-1337
Arrow Electronics
193051. Andrews Dr., NE
Cedar Rapids, IA 52402
13191395-7230
714/632-6880
TWX 910/591-1961
11-17
MARYLAND
Arrow Electronics
4801 Benson Avenue
Baltimore, MD 21227
301/247-5200
TWX 7101236-9005
Pioneer Electronics
9100 Gaither Road
Gaithersburg, MD 20877
301/948-0710
TWX 710/828-0545
Schweber Electronics
9218 Gaither Rd.
Gaithersburg, MD 20877
301/840-5900
TWX 710/828-9749
MASSACHUSETTES
Arrow Electronics
Arrow Drive
Woburn, MA 01801
617/933-8130
TWX 710/393-6770
Kierulff Electronics
13 Fortune Drive
Billerica, MA 01865
617/935-5134
TWX 710/390-1449
Lionex Corporation
1 North Avenue
Burlington, MA 01803
617/272-1660
TWX 710/332-1387
Schweber Electronics
25 Wiggins Avenue
Bedford, MA 01730
6171275-5100
TWX 710/326-0268
Zeus/New England, Inc.
25 Adams Street
Burlington, MA 01803
617/273-0753
TWX 710/322-0716
MICHIGAN
Arrow Electronics
3810 Varsity Drive
Ann Arbor, MI 48104
313/971-8220
TWX 810/223-6020
Pioneer Electronics
13485 Stamford
Livonia, MI48150
313/525-1800
TWX 8101242-3271
Schweber Electronics
10260 Hubbard Ave.
livonia, MI 48150
313/525-8100
TWX 810/242-2983
MINNESOTA
Arrow Electronics
5230 W. 73rd Street
Edina, MN 55435
612/830-1800
TWX 910/576-3125
Kierulff Electronics
7667 Cahill Rd.
Edina, MN 55435
612/941-7500
TWX 910/576-2721
MISSOURI
Arrow Electronics
2380 Schuetz Road
St. Louis, MO 63141
314/567-6888
TWX 910/764-0882
Olive Electronics
9910 Page Blvd
St. Louis, MO 63132
314/426-4500
TWX 9101763-0720
Semiconductor Spec
3805 N. Oak Trafficway
Kansas City, MO 64116
816/452-3900
TWX 9101771-2114
NEW HAMPSHIRE
Arrow Electronics
1 Perimeter Rd.
ManChester, NH 03103
603/668-6968
TWX 710/220-1684
NEW JERSEY
Arrow Electronics
Pleasant Valley Avenue
Morrestown, NJ 08057
609/235-1900
TWX 710/897-0829
Arrow Electronics
285 Midland Avenue
Saddlebrook, NJ 07662
201/797-5800
TWX 710/988·2206
Kierulff Electronics
3 Edison Place
Fairfield, NJ 07006
201/575-6750
TWX 710/734-4372
Schweber Electronics
18 Madison Road
Fairfield, NJ 07006
2011227-7880
TWX 7101734-4305
u.s. AND CANADIAN
NEW MEXICO
Arrow Electronics
2460 Alamo Ave. S.E.
Albuquerque. NM 87106
605/243-4566
TWX 910/989-1679
NEWVORK
Add Electronic
7 Adler Drive
E. Syracuse. NY 13057
315/437-0300
Arrow Electronics
900 Broad Hollow Rd.
Farmingdale, 1.I .. NY 11735
516/694-6800
TWX 510/224-6494
Arrow Electronics
7705 Maltlage Drive
P. O. Box 370
liverpool, NY 13088
315/652-1000
TWX 710/545-0230
Arrow Electronics
3000 S. Winton Road
Rochester. NY 14623
716/275-0300
TWX 5101253-4766
DISTRIBUTORS
OHIO
Arrow Electronics
7620 McEwen Road
Centerville, OH 45459
513/435-5563
TWX 810/459-1611
Arrow Electronics
6238 Cochran Road
Solon, OH 44139
2161248-3990
TWX 810/427-9409
400 Oser Ave.
Hauppauge. NY 11787
, 5161273-1660
TWX 5101227-1042
Schwaber Electronics
3 Town Line Circle
Rochester. NY 14623
716/424-2222
Schweber Electronics
Jericho Turnpike
Westbury, NY 11590
516/334-7474
TWX 5101222-3660
Zeus/Long Island
401 Broad Hollow Rd.
Melville, NY 11746
5161752-9551
TWX 710/567-1248
Zeus Components Components, Inc.
tOO Midland Avenue
Port Chester, NY 10573
914/937-7400
TWX 710/567-1248
Kierulff Electronics
2121 South 3600 West
Salt lake City, UT 84119
214/386-7500
801/973-6913
TWX 91 0/860-5377
TWX 910/880-4439
12061 643-4800
TWX 910/444-2017
Quality Components
4257 Kellway Circle
Addison, TX 75001
Kierulff Electronics
1053 Andover Park East
Tukwila, WA 98188
713/491-4100
TWX 810/459-1622
TWX 910/860-5459
206/575-4420
TWX 910/444-2034
Schweber Electronics
23880 Commerce Park Road
Beachwood. OH 44122
216/464-2970
Quality Components
2427 Rutland Drive
Austin. TX 78758
Zeus/West
23701 150th S.E.
Monroe. WA 98279
5131236-9900
TWX 810/427-9441
OREGON
Kierulff Electronics
14273 NW Science Park
Portland, OR 97229
503/641-9150
TWX 910/467-8753
PENNSYLVANIA
Arrow Electronics
650 Seco Rd.
Monroeville, PA 15146
412/856-7000
Pioneer Electronics
560 Alpha Drive
Pittsburgh, PA 15238
214/387-4949
512/835-0220
TWX 910/874-1377
Quality Components
6126 Westline
Houston. TX 77036
713/772-7100
Schweber Electronics
10625 Richmond. Suite 100
Houston. TX 77042
713/784-3600
TWX 910/881-4836
Zeus/Dallas, Inc.
14001 Goldmark Dr.
Suite 250
Dallas, TX 75240
2141783-7010
TWX 910/867-9422
9191725-8711
TWX 510/931-3169
Arrow Electronics
3117 Poplarwood Court
Suite 123, P.O. Box 95163
Raleigh, NC 27625
WISCONSIN
Arrow Electronics
434 Rawson Avenue
Oak Creek. WI 53154
414/764-6600
TWX 91 01262-1193
Kierulff Electronics
2212 E. Moreland Blvd.
Waukesha. WI 53186
4141784-8160
TWX 9101265-3653
CANADA
Prelco Electronics
2767 Thames Gate Drive
Mississauga, Ontario
Toronto l4T 1G5
416/678-0401
TWX 610/492-8974
Prelco Electronics
480 Port Royal St. W.
Montreal 357 P.Q. H3l 2B9
514/389-8051
TWX 610/421-3616
Prelco Electronics
1770 Woodward Drive
Ottawa. Ontario K2C OPS
6131226-3491
Telex 05-34301
RAE. Industrial
3455 Gardner Court
Burnaby, B.C. V5G 4J7
6041291-8866
TWX 610/929-3065
Zentronics
141 Catherine Street
Ottawa, Ontario
K2P lC3
613/238-6411
Zentronics
8 Tilbury Court
Srampton, Ontario
l6T3T4 (Toronto)
416/451-9600
Telex 06-97678
Zentronics
505 locke St.
St. Laurent, Quebec
H4TIX7
5141735-5361
Telex 058-27535
Zentronics
590 Berry Street
St. James. Manitoba
R2H OR4
204/775-8661
Zentronlcs
480 "AU Dutton Drive
Waterloo. Ontario
412/782-2300
TWX 7101795-3122
N2L4C6
519/884-5700
Pioneer Electronics
261 Gibraltar
Horsham, PA 19044
RAE. Industrial
11680 170th St.
Edmonton, Alberta T55 1J7
215/674-4000
TWX 510/665-6778
403/451-4001
Telex 03-72653
Zentronics
550 Cambie St.
Vancouver. B.C. V6B 2N7
Schweber Electronics
101 Rock Road
Horsham, PA 19044
215/441-0600
NORTH CAROLINA
Arrow Electronics
938 Burke St.
Winston Salem, NC 27102
WASHINGTON
Arrow Electronics
14320 NE 21 st
Bellevue, WA 98005
Pioneer Electronics
4433 Interpoint Blvd.
Dayton, OH 45424
918/664-8812
TWX 510/227-6623
Lionex Corporation
18011539-1135
216/587-3600
TWX 810/422-2211
516/231-1000
.
612/835-4180
Arrow Electronics
13715 Gamma Road
Dallas, TX 75240
Arrow Electronics
10700 Corporate Drive
Suite 100
Stafford. TX 77477
Hauppauge, NY 11787
20 Oser Ave.
UTAH
Arrow Electronics
4980 Amelia Earhart Dr.
Salt Lake City. UT 84116
Pioneer Electronics
4800 East 131 st Street
Cleveland, OH 44105
OKLAHOMA
Quality Components
9934 East 21 st South
Tulsa, OK 74129
Arrow Electronics
TEXAS
Arrow Electronics
10125 Metropolitan Dr.
Austin, TX 78758
604/688-2533
Telex 04507789
Zentronics
3651 21st Street. N.E.
Calgary, Alberta T2E 6T5
SOUTH CAROLINA
Hammond Electronics
1035 Lowndes Hill Rd.
Greenville, SC 29602
4031230-1422
8031233-4121
Zentronics
9224 27th Avenue
Edmonton, Alberta T6N 182
403/463·3014
Zentronics
30 Sommonc!s Drive, Unit B
Dartmouth, N.S. B3B1R3
TWX 810/281-2233
TWX 919/876-3132
Hammond Electronics
2923 Pacific Avenue
Greensboro, NC 27406
902/463-8411
919/275-6391
TWX 510/925-1094
*Franchised for USA and canada excluding california for military products
11-18
INTERNATIONAL MARKETING OFFICES
EUROPEAN HEAD OFFICE
Mostek International
Av de Tervuren 270-272 Bte 21
8-1150 Brussels/Belgium
GERMANY
PLZ 1-5
Mostek GmbH
Friedlandstrasse 1
021762.18.80
0-2085 Quickborn
Telex: 62011
(04106)2077178
Telex: 213685
FRANCE
Mostek France s.a.r.1.
30 Rue du Morvan
JAPAN
0-80120ttobrunn
(089)95.10.71
Tetex: 5216516
1-2-7 Kita-Aoyama
Minato-Ku. Tokyo 107
103)404-7261
Telex: J23686
Mostek Japan KK
Sanyo Bldg. 3F
ITALY
F-94623 Rungis Cedex
PLZ 6-7
Mostek GmbH
Schurwaldstrasse 15
D-7303 Neuhausen/Filder
11)68734.14
Telex: 204049
Telex: 72.38.86
Slue 505
PLZ8
Mostek GmbH
Zaunkonigstr. 18
107158)66.45
Mostek ttalia SAL
Via F.O. Guerrauj 27
I 20145 Milano
(02) 318.5337/349.2696
and 34.23.89
Telex: 333601
UNITED KINGDOM
Mostek UK Ltd
Masons House,
'-3 Valley Drive
Ki ngsbury Road
London, N.W.9
01-2049322
Telex: 25940
SWEDEN
Mostek Scandinavia AS
Magnusvagen 1/8 tr
S-17531 Jarfalla
0758-343 38/343 48/183 30
Telex: 12997
INTERNATIONAL SALES REPRESENTATIVES/DISTRIBUTORS
ARGENTINA
Rayo Electronics S.R.L
Belgrano 990, Pisos 6y2
1092 Buenos Aires
138)-1779,37-9476
Telex - 122153
AUSTRAUA
Amtron Tyree Pty.Ltd.
176 Botany Street
Waterloo, N.S.W. 2017
(61)69-89.666
Telex - 25643
AUSTRIA
Transistor Vertriebsges, mbH
Auhofstrasse 41 A
A- 1130 Vienna
10222) 82 9451, 83 9404
Telex - 0133738
BRAS1L
Cosele, Ltd.
Rua da Consolacao, 867
Conj.31
01301 Sao Paulo
155)11-257.35.35/258.43.25
Telex - 1130869
BELGIUM
Sotronic
14 Rue Pere De Deken
8-1040 Brussels
02736.10.07
Telex - 25141
DENMARK
Semicap APS
Gammel Kongevej 148
OK-1850 Copenhagen
01-22.15.10
Telex - 15987
F1NLAND
Insele Oy
Kumpulantie 1SF-00520 Helsinki 52
0735774
Telex: 122217
FRANCE
Copel
Rue Fourny, Z.t
B.P. 22, F-78 530 BUC
11)9561018
Telex: 69379
Facen
1 10 Av de Flandre
F59290 Wasquehal. Nord
12)98.92.15
Branch Offices in
Chalon/$aone, Lilte,
Nancy, Rouen, $trasbourg
Mecodis
2 Rue Pasteur
F-94380 Bonneuil
(1) 339.20.20
Telex: 250303
P.E.P.
4 Rue Barthelemy
F-92120 Montrouge
(1)-7353320
Telex: 204 534
HONG KONG
Cet limited
1402 Tung Wah Mansion
199-203 Hennessy Road
Wanchai, Hong Kong
(5)-72.93.76
Telex - 85148
ISRAEL
Telsys Ltd.
12, Kehilat Venetsia St
Tel Aviv. Israel
Scaib
80 Rue d'Arcueil
SlllC 137
F-94523 Rungis Cedex
111-68723.12
Telex: 204674
48212617/8
Sorhodis
150-152, Rue A. France
F691 00 Villeurbanne
(78)850044
Telex: 380181
(02) 61.20.641/2/3/4/5
GERMANY
Dr Dohrenberg
Bayreuther Strasse 3
0-1000 Berlin 30
(030)213.80.43
Telex: 0 184860
Neye Enatechnik GmbH
SchiUerstrasse 14
0-2085 Ouickborn
(04106)612-1
Telex: 0 213.590
Branch offices in: Berlin, Hannover,
Dusseldorf, Darmstadt, Stuttgart,
Munchen
Raffel-Electronic GmbH
Lochnerstrasse 1
0-4030 Ratingen 1
12102)280.24
Telex: 8585180
Siegfried Ecker
Koenigsberger Strasse 2
0-6120 Michelstadt
16061)2233
Telex: 4191630
Matronic GmbH
Lichtenberger Weg 3
0-7400 Tuebingen
17071)24331
Telex: 7262879
THE NETHERLANDS
Nijkerk Elektronika BV
Drentestraat 7
NL - 1083 HK Amsterdam
(020) 428. 933
Telex: 1 1625
NEW ZEALAND
E.C.S. Div. of Airspares
P.O. Box 1048
Airport Palmerston North
(77)-047
Telex - 3766
Telex: 032392
ITALY
Comprel s.r.1.
V.le Romagna. 1
1-20092 CiniselJo B. (MI)
NORWAY
Hefro Teknisk AIS
Postboks 6596
Rodelokka, Oslo 5
02-38.02.86
Telex: 16205
Telex: 332484
Branch offices in
Bologna, Firenze,
lavagna, Loreto,
Padova, Roma, Torino,
Vicenza, Bari
Emesa S.P.A
Via l. da Viadana, 9
1-20122 Milano
102)869.0616
Telex: 335066
Branch offices in
Torino, Bologna, Roma
JAPAN
Systems Marketing, Inc
4th Floor, Shindo Blgd.
3-12-5 Uchikanda,
Chiyoda-Ku,
Tokyo, 100
(81) 3-254.27.51
Telex - 25761
Teijin Advanced Proclucts Corp.
,-, Uchisaiwai-Cho
2-Chome Chiyoda-Ku
Tokyo, 100
(81)3-506.46.73
Telex - 23548
KOREA
Vine Overseas Trading Corp.
Room 308 Korea Electric
Association Bldg.
11-4 Supyo-Dong Jung-Ku
Seoul
182)2-66-1663
PORTUGAL
Digicontrole LoA
Rua Tenente Ferreira Durao 33 AI I
1300 lisboa
19-688442/652613
Telex: 15084
SINGAPORE
Dynamar International, LTD.
Suite 526, Cuppage Road
SingalX>re 0922
SOUTH AFRICA
Radiokom
P.O. Box 56310
Pinegowrie
2123,
Transvaal
789-1400
Telex - 8-0838 SA
SPAIN
Comelta S.A
Emilio Munoz 41, ESC 1
Planta 1 Nave 2
Madrid-17
01-7543001/3007
Telex: 42007
Branch Office
Diputacion, 79
Entlo 1
Barcelona-15
3257062
3257575
Telex: 519 34
SWEDEN
TRACO AB, Box 32
S-12221 Enskede
08-132160
Telex: 10 689
Lagercrantz Elektronik AB
Box 48
S-19421 Upplands Vasby
0760861 20
Telex: 11275
SWITZERLAND
Memotec AG
Einschlagweg, 2
CH-4932 Lotzwil
063-28.11.22
Telex: 68636
TAIWAN
Dynamar Taiwan limited
P.O. Box 67-445
2nd Floor, No. 14, Lane 164
Sung-Chiang Road
Taipe!
5418251
Telex - 11064
UNITED KINGDOM
Celdis limited
37 -39 Loverock Road
Reading
Berks RG 31 ED
0734·58.51.71
Telex: 848370
lock Distribution ltd.
Neville Street
Chadderton
Oldham
lancashire
OL96LF
061 -652.04,31
Telex: 669971
Pronto Electronic Systems Ltd.
466-478 Cranbrook Road,
Gants HillUford
Essex 1G2 6LE
01-5546222
Telex: 895 4213
VSI Electronics (UK) ltd
Roydondury Industrial Park
Horsecroft Rd.
Harlow
Essex CM 19 5BY
(0279) 35477
Telex: 81387
Thame Components ltd.
Thame Park Road
Thame, Oxon aX9 3XD
0844213146
Telex: 837917
Dema-Electronic GmbH
Bluetenstrasse 21
0-8000 Munchen 40
1089)288018/19
Telex: 05-29345
11-19
III
1982/1983 MICROELECTRONIC DATA BOOK
MOSTEI(.
MEMORY COMPONENTS
64K-Bit Read-Only Memory
MK36000(P/J/N) Series
FEATURES
o MK36000 8K x 8 Organization"Edge Activated" * operation (CE)
o Standard 24 pin DIP
o Low Power Dissipation - 220mW Max Active
o Access Time/Cycle Time
PIN
Access
Cycle
MK36000-4
250 ns
375 ns
MK36000-5
300ns
450ns
o Low Standby Power Dissipation - 45mW Max, (CE High)
o On chip latches for addresses
o Inputs and three-state outputs - TTL compatible
o Outputs drive 2 TTL loads and 100pF
o Single +5V ± 10% Power Supply
o MKB version screened to MIL-STD-883
DESCRIPTION
enable (CE) input at a TTL high level. In this mode, power
dissipation is reduced to typically 45mW, as compared to
unclocked devices which draw full power continuously. In
system operation, a device is selected by the CE input, while
all others are in a low power mode, reducing the overall
system power. Lower power means reduced power supply
cost, less heat to dissipate and an increase in device and
system reliability.
The MK36000 is a N-channel silicon gate MOS Read Only
Memory, organized as 8192 words by 8 bits. As a state-ofthe-art device, the MK36000 incorporates advanced circuit
techniques designed to provide maximum circuit density
and reliability with the highest possible performance, while
maintaining low power dissipation and wide operating
margins.
Use of a static storage cell with clocked control periphery
allows the circuit to be put into an automatic low power
standby mode. This is accomplished by maintaining the chip
The edge activated chip enable also means greater system
flexibility and an increase in system speed.
FUNCTIONAL DIAGRAM (MK36000)
PIN CONNECTIONS
~
24
23
22
21
20
19
1
As 2
As 3
A.J 4
As
As
A12
CE
Al0
18 An
17 t?
16 Os
15 Os
14 ~
13 Oa
Aa 5
~
6
Al 7
Ac8
Do9
~11
vss 12
885311 BIT
vee
CELL MATRIX
PIN NAMES
Ao-A12
00-°7
VGC
.. Trademark of Mostek Corporation
111-1
Address
Outputs
+5V
~S
CE
GND
Chip Enable
II
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Terminal Relative to Vss ..........................................•............. -1.0 V to +7 V
Operating Temperature TA (Ambient) ............................................................ O°C to + 70°C
Storage Temperature - Ceramic (Ambient) ..................................................... -65°C to + 150°C
Storage Temperature - Plastic (Ambient) ..................................•................... -55°C to +125°C
Power Dissipation ................................................................................... 1 Watt
·Stresses greater than those listed under "Absolute Maximum Ralings" may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS6
(O°C :::::: TA :::::: + 70°C)
SYM
PARAMETER
MIN
TYP
MAX
Vcc
Power Supply Voltage
4.5
5.0
5.5
V
V IL
Input Logic 0 Voltage
-1.0
0.8
V
V IH
Input Logic 1 Voltage
2.0
Vcc
V
UNITS NOTES
6
DC ELECTRICAL CHARACTERISTICS
(Vcc = 5V ±10%) (O°C:::::: TA :::::: +70°C) 6
SYM
PARAMETER
ICC1
Vcc Power Supply Current (Active)
ICC2
Vcc Power Supply Current (Standby)
II(L)
Input Leakage Current
IO(L)
Output Leakage Current
VOL
Output Logic "0" Voltage
@ lOUT = 3.3 mA
V OH
Output Logic ··1" Voltage
@ lOUT = -220 pA
MIN
TYP
MAX
UNITS NOTES
40
mA
1
8
mA
7
-10
10
pA
2
-10
10
pA
3
0.4
V
2.4
V
AC ELECTRICAL CHARACTERISTICS
(Vcc = 5V ±10%) (O°C ::::::TA :::::: +70°C)6
-4
-5
SYM
PARAMETER
MIN
tc
Cycle Time
375
tCE
CE Pulse Width
250
tAC
CE Access Time
tOFF
Output Turn Off Delay
tAH
Address Hold Time Referenced to CE
60
75
ns
tAS
Address Setup Time Referenced to CE
0
0
ns
tp
CE Precharge Time
125
150
ns
NOTES:
1. Current is proportional to cycle rate. ICC1 is measured at the specified
minimum cycle time. Data Outputs open.
2. VIN ~ OVto5.5VIVCC = 5VI
3. Device unselected; VOUT = 0 V to 5.5 V
4. Measured with 2 TTL loads and 100 pF. transition times = 20 ns
MIN
MAX UNITS NOTES
450
ns
4
10000
ns
4
250
300
ns
4
60
75
ns
4
10000
300
5. Capacitance measured with Boonton Meter or effective capacitance
e = AQ.with 6V = 3 volts
calculated from the equation:
6.
7.
111-2
MAX
A minimum 2 ms time delay is required after the application of Vee (+5)
before proper device operation is achieved. CE must be at V1H for this time
period.
CE high.
CAPACITANCE
(O°C ::; TA ::; 70°C)
SYM
PARAMETER
q
Co
TYP
MAX
UNITS
NOTES
Input Capacitance
5
a
pF
5
Output Capacitance
7
15
pF
5
TIMING DIAGRAM
~----------tc--------------------------~
CHIP ENABLE
ADDRESS
V OH
DATA OUTPUT
~
------------OPEN------------~
VOL -
D-----OPEN-----
VALID
DESCRIPTION (Continued)
The MK36000 features onboard address latches controlled
by the CE input. Once the address hold time specification
has been met, new address data can be applied in
anticipation of the next cycle. Outputs can be wire 'OR'ed
together, and a specific device can be selected by utilizing
the CE input with no bus conflict on the outputs. The CE
input allows the fastest access times yet available in 5 volt
only ROM's and imposes no loss in system operating
flexibility over an unclocked device.
Any application requiring a high performance, high bit
density ROM can be satisfied by the MK36000 ROM. This
bit microprocessor systems
device is ideally suited for
such as those which utilize the zao. It can offer significant
cost advantages over PROM.
a
OPERATION
The MK36000 is controlled by the chip enable (CE) input. A
negative going edge at the CE input will activate the device
as well as strobe and latch the inputs into the on-chip
address registers. At access time the outputs will become
active and contain the data read from the selected location.
The outputs will remain latched and active until CE is
returned to the inactive state.
Other system oriented features include fully TTL compatible
inputs and outputs. The three state outputs, controlled by
the CE input, will drive a minimum of 2 standard TTL loads.
The MK36000 operates from a single +5 volt power supply
with a wide ±1 0% tolerance, providing the widest operating
margins available. The MK36000 is packaged in the
industry standard 24 pin DIP.
111-3
II
111-4
MOSTEI(.
64K-BIT MOS READ-ONLY MEMORY
M K37000(P / J/ N) Series
FEATURES
o Organization: 8K x 8 Bit ROM - JEDEC Pinout
o Mask ROM replacement for 2764 EPROM
o Pin compatible with Mostek's BYTEWYDETM Memory
o
No Connections allow easy upgrade to future
generation higher density ROMs
o
Low power dissipation: 220mW max active, 45mW
max standby
o
CE and OE functions facilitate Bus control
o
MKB version screened to MIL-STD-883
Family
o
Access Time/Cycle Time
PIN
CYCLE
ACCESS
300 ns
MK37000-5
. MK37000-4
450 ns
375 ns
250 ns
DESCRIPTION
The MK37000 is a N-channel silicon gate MOS Read
Only Memory, organized as 8192 words by 8 bits. As a
state-of-the-art device, the MK37000 incorporates
advanced circuit techniques designed to provide
maximum circuit density and reliability with the highest
possible performance, while maintaining low power
dissipation and wide operating margins. The MK37000
is to be used as a pin/function compatible mask
programmable alternative to the 2764 8K x 8 bit
EPROM. As a member of the Mostek BYTEWYDE
Memory Family, the MK37000 brings to the memory
market a new era of ROM, PROM and EPROM
compatibility previously unavailable.
FUNCTIONAL DIAGRAM (MK37000)
PIN CONNECTIONS
Use of clocked control periphery and a standard static
ROM cell makes the MK37000 the lowest power 64K
ROM available. Active power is a mere 220mW while
standby (CE high) is only 45mW. To provide greater
system flexibility an output enable (OE) function has
been added using one of the extra pins available on the
OE
A"
-Vee
-vss
AS
AS
A7
A6
A5
A.
A3
A2
A,
AO
NC
1
A12
2
28 vcc
27 NC
A7
3
4
25 AS
A5
5
24 A9
A4
6
23 All
22 OE
A6
26 NC
A3 7
A2 8
65536 SIT
CELL MATRIX
'"
Al
9"
'""
~
'"
TRUTH TABLE
CE
OE MODE
OUTPUTS
X
Deselect
High-Z
Standby
Inhibit
High-Z
Active
DOUT
Active
VIL
VIH
VIL
VIL Read
X = Don't Care
00 11
19 07
18 06
01 12
17 05
AO 10
CE
:0
VIH
21 A l 0
20 CE
9
POWE-R-
°2 13
vss14
PIN NAMES
AO - A 12-Address
Chip Enable
a:
00 - 07 - Outputs
111-5
16 04
15 03
NC OE VCC VSS -
No Connection
Output Enable
+5V supply
Ground
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Terminal Relative to VSS ..................................................... -1.0V to +7V
Operating Temperature TA (Ambient) ......................................................... O°C to + 70°C
Storage Temperature-Ceramic (Ambient) ................................................. -65°C to +150°C
Storage Temperature-Plastic (Ambient) ................................................... -55°C to +125°C
Power Dissipation ................................................................................ 1 Watt
·Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stresS rating only and functional
operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS6
(O°C $TA $ +70°C)
SYM
PARAMETER
MIN
TYP
MAX
UNITS
VCC
Power Supply Voltage
4.5
5.0
5.5
V
VIL
Input Logic 0 Voltage
-1.0
0.8
V
VIH
Input Logic 1 Voltage
2.0
VCC
V
MAX
UNITS
NOTES
40
mA
1
8
mA
7
DC ELECTRICAL CHARACTERISTICS
(VCC = 5V ± 10%) (O°C $TA $ +70°C)
NOTES
6
MIN
TVP
SYM
PARAMETER
ICC1
VCC Power Supply Current (Active)
ICC2
VCC Power Supply Current
(Standby)
II(L)
Input Leakage Current
-10
10
p.A
2
IO(L)
Output Leakage Current
-10
10
p.A
3
VOL
Output Logic "0" Voltage
@ lOUT = 3.3mA
0.4
V
VOH
Output Logic "1" Voltage
@ lOUT = -220p.A
V
2.4
AC ELECTRICAL CHARACTERISTICS6
(VCC = 5V ± 10%)(0°C $TA $ +70°C)
-4
-5
SYM
PARAMETER
MIN
tRC
Read Cycle Time
375
tCE
CE Pulse Width
250
tCEA
CE Access Time
tCEZ
Chip Enable Data Off Time
tAH
Address Hold Time Referenced
to CE
60
75
ns
Address Setup Time Referenced
to CE
0
0
ns
125
150
ns
tAS
MAX
MIN
MAX UNITS
450
ns
4
10,000
ns
4
250
300
ns
4
60
75
ns
0,000
300
tp
CE Precharge Time
tOEA
Output Enable Access Time
80
100
ns
tOEZ
Output Enable Data Off Time
60
75
ns
111·6
NOTES
CAPACITANCE
(O°C :::; TA :::; 70°C)
SYM
TYP
MAX
UNITS
NOTES
Input Capacitance
5
8
pF
5
Output Capacitance
7
15
pF
5
PARAMETER
TIMING DIAGRAM
Figure 1
II
CHIP ENABLE
ADDRESS
OUTPUT ENABLE
V IH VIL~
DATA OUTPUT
VOH_
OPEN
V OL -
NOTES:
1. Current is proportional to cycle rate. ICCl is measured at the specified
minimum cycle time. Data Outputs open.
2. VIN = OV to 5.5V
3. Device un selected; VOUT = OV to 5.5V
4. Measured with 2 TTL loads and 100pF, transition times::::: 20ns
5. Capacitance measured with Boonton Meter or effective capacitance
calculated from the equation:
C = 6.Q with 6.V = 3 volts
b.V
6.
7.
A minimum 2ms time delay is required after the application of Vee (+5)
before proper device operation is achieved. CE must be at VIH forthis time
period.
CEhigh
DESCRIPTION (Continued)
tolerance, providing the widest operating margins
available. The MK37000 is packaged in the industry
standard 28 pin DIP. Pin 1 and 26 are not connected to
allow easy upward compatibility with next generation
higher density ROM which will use these pins for
addresses. Pin 27 is not connected in order to maintain
compatibility with RAMs which use this pin as a write
enable (WE) control function.
28 pin DIP. This function matches that found on all of
the new BYTEWYDE family of memories available from
Mostek.
The use of clocked CE mode of operation provides an
automatic power down mode of operation. The
MK37000 features on chip address latches controlled
by the CE input. Once address hold time is met, new
address data can be provided to the device in
anticipation of a subsequent cycle. It is not necessary to
maintain the address up to access time to access valid
data. The output enable function controls only the
outputs and is not latched by CEo The
input can be
used for device selection and the OE input used to avoid
bus conflicts so that outputs can be 'OR'ed together
when using mUltiple devices.
Any application requiring a high performance, high bit
density ROM can be satisfied by the MK37000. This
device is ideally suited for 8 bit microprocessor systems
such as those which utilize the MK3880. It can offer
significant cost advantages over PROM.
a:
OPERATION
The MK37000 is controlled by the chip enable (CE) and
output enable (OE) inputs. A negative going edge at the
CE input will activate the device and latch the addresses
into the on chip address registers. The output buffers,
under the control of OE, will become active in CE access
Other system oriented features include fully TIL
compatible inputs and outputs. The three state outputs,
controlled by the OE input, will drive a minimum of 2
standard TIL loads. The MK37000 operates from a
single +5 volt power supply with a wide ± 10%
111-7
time (tCEA) if the output enable access time (tOEA)
requirement is met. The on chip address register allows
addresses to be changed after the specified hold time
(tAH) in preparation for the next cycle. The outputs will
remain valid and active until either CE or OE is returned
to the inactive state. After chip deselect time (tCEZ) the
output buffers will go to a high impedance state. The CE
input must remain inactive (high) between subsequent
cycles for time tp to allow for precharging the nodes of
the internal circuitry.
total of (4) 2K x 8 devices would be required to totally
describe the address space of the 8K x 8 MK37000.
A paper printout and verification approval letter will
accompany each verification EPROM set returned to the
customer. Approval is considered to be excepted when
the signed verification letter is returned to Mostek. The
original set of EPROMs will be retained by Mostek for
the duration of the prototyping process.
MK37000 ROM CODE DATA INPUT PROCEDURE
The preferred method of supplying code data to Mostek
is in the form of programmed EPROMs (see table). In
addition to the programmed set, Mostek requires an
additional set of blank EPROMs for supplying customer
code verification. When multiple EPROMs are required
to describe the ROM they shall be designated in
ascending address space with the numbers 1,2,3, etc.
As an example, EPROM #1 would start with address
space 0000 and go to 07FF for a 2K x 8 device. EPROM
#2 would then start at address space 0800 and so on. A
Acceptable EPROMs for Code Data
Table 1
EPROM
271612516
2732
2764
111-8
# REQUIRED
4
2
1
MOSTEI(.
256K-BIT MOS READ-ONLY MEMORY.
M K38000(P IN }-25
FEATURES
o Organized 32K x 8
o CE and OE functions facilitate bus control
o Pin compatible with Mostek's BYTEWYDpM Memory
Family
o Pin 27 no connection permits interchange with static
RAM (WE)
o Access Time
= Cycle
o High performance
Time
o Static Operation
o Automatic Power Down
Part No.
Access Time
Cycle Time
MK38000-25
250 ns
250 ns
DESCRIPTION
and reliability with the highest possible performance, while
maintaining low power dissipation and wide operating
margins.
The MK38000 is a N-channel silicon gate MOS Read Only
Memory, organized as32,768 wordsby8 bits. Asa state-ofthe-art device, the MK38000 incorporates advanced circuit
techniques designed to provide maximum circuit density
FUNCTIONAL DIAGRAM (MK38000)
PIN CONNECTIONS
Figure 1
Figure 2
A,
A"
,e
A"
Voo
'e
A"
L~J l~J l~j :' 1L3!J l~lj l~
A,
AO
"
A,
~J
A.
_~J
AJ
:!J
A~ -~J
A14
I
LJ
!}J
Ne
~'J
_~J
tDevice pinout is preiiminllry and may be
8Ld1;ecltuminorreviSion.
A14
1
28
Vee
A12
2
27
NC
A13
[2.!_ Po"
A7
3
2.
L~
A"
A6
4
25
AB
,-'" A"
A5
5
A9
A4
6
2'
23
A3
7
22
OE
A2
8
21
A10
A1
9
20
~
AO 10
19
07
00 11
18
06
01
12
17
Q5
02 13
16
04
15
03
,--
[Z!:
MK3BOOO
-~J
A,
A,
0
I
NC
1""-- _
L~ OE
[2~
A"
[2!_
I!>
[2!:
00,
[2]~ DO,
BE - - - ;
GND
iiE - - - - IL--_ _
14
~
QO •••• 07
PIN NAMES
TRUTH TABLE
CE
OE
H
MODE
OUTPUTS
POWER
X
Deselect
High-Z
Standby
L
H
Inhibit
High-Z
Active
L
L
Read
DOUT
Active
AO-A 14 Address
OE
CE
Chip Enable
Vee
NC
No Connection GND
QO-Q7
111-9
~
- - - - - - ---- - ---
-~---
..
- - - - - - - - - - - ... - - - .
Output Enable
+5V
Ground
Data Outputs
A11
•
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Terminal Relative to GND •..•..••••.....•..•.....•.....•.••..•••.....•...•...... -1.0 V to +7. V
Operating Temperature TA (Ambient) ••..•.••...•.•.............••...•.••••..•••.•...•...•....... O°C to +70°C
Storage Temperature-Ceramic (Ambient) ....•••.•.•....••.•........•....•.•.......•.........• -65°C to +150°C
Storage Temperature-Plastic (Ambient) .••..••.•••.....••.....•....••.............••....•...• -55°C to +125°C
Power Dissipation .••......•......•....•..•..•..•...•.......•..•...............•...•...•..•..•...•.. 1 Watt
·Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS\6
(O°C :5 TA:5 + 70°C)
SYM
PARAMETER
MIN
TYP
MAX
UNITS
Vcc
Power Supply Voltage
4.75
5.0
5.25
V
V il
Input Logic 0 Voltage
-1.0
0.8
V
V IH
Input Logic 1 Voltage
2.0
Vcc
V
TYP
MAX
UNITS
NOTES
NOTES
8
DC ELECTRICAL CHARACTERISTICS\6
(Vcc 5 V ± 5%) (O°C :5TA :5 +70°C)
=
SYM
PARAMETER
ICCl
V cc Power Supply Current (Active)
75
100
mA
5
ICC2
Vcc Power Supply Current
(Standby)
35
50
mA
7
II(l)
Input Leakage Current
-10
0.1
10
pA.
3
IO(l)
Output Leakage Current
-10
0.1
10
pA.
2
VOL
Output Logic "0" Voltage @
lOUT = 4 mA
0.4
V
V OH
Output Logic "1" Voltage @
lOUT =-1 mA
MIN
2.4
V
AC ELECTRICAL CHARACTERISTICS',4,6,9,lo
(Vcc =5 V ± 5%) (O°C:5 TA :5 +70°C)
-25
SYM
PARAMETER
MIN
t Rc
Read Cycle Time
250
tAA
Address Access Time
250
ns
tCEA
CE Access Time
250
ns
tCEZ
Chip Enable Data Off Time
40
ns
tCEl
Chip Enable to Data Bus Active
tOEA
Output Enable Access Time
50
ns
tOEZ
Output Enable Data Off Time
40
ns
tOH
Output Hold from Address Change
MAX UNITS
ns
ns
5
5
111-10
ns
NOTES
CAPACITANCE
(DOC ~ TA ~ 7D°C)
SYM
PARAMETER
C1
Input Capacitance
5
pF
Co
Output Capacitance
7
pF
TYP
MAX
UNITS
NOTES
5
TIMING DIAGRAM
Figure 3
------~~--------~C--------~~------tRC--------~-----tRC-------
00-Q7
OUTPUT LOAD
NOTES:
1. All voltages referenced to GND.
2. Measured with 0.4 V:;; Vo:;; 5.0 V outputs deselected and Vee = 5 V.
3. VIN = OVto 6.25 V.
Figure 4
Vee MAX
4. Input and output timing reference levels are at 1.5 Vfor inputs and .8 and 2.0
for outputs.
5. Measured with outputs open.
1.1KO
6. A minimum of 2 ms time delay is required after the application of Vee (+5)
before proper device operation is achieved.
period.
7.
CE must be at VIH for this time
D.U.T.
CE high.
8. Negative undershoots to a minimum of -1.5 V are allowed with a maximum
of 10 ns pulse width.
9. Measured with a load as shown in Figure 4.
10. A.C. measurements assume transition time = 5 ns levels GND to 3 V.
111-11
6800
;:::~
100pF
(Including Scope and Jig)
DESCRIPTION (continued)
As a member of the Mostek BYTEWYDE Memory Family,
the MK38000 allows compatibility between RAM, ROM,
and EPROM. The MK38000 can be used as a pin/function
density upgrade to the MK37000 8K x 8 bit ROM.
Any application reqUiring a high performance high bit
density ROM can be satisfied by the MK38000. This device
is ideally suited for 8 bit microprocessor systems such as
those which can utilize the MK3880. It can offer significant
cost advantages over PROM.
OPERATION
The output enable function controls only the outputs. The
CE input can be used for device selection and the OE input
used to avoid bus conflicts so that outputs can be 'OR'ed
together when using multiplexed or bi-directional busses.
Other system oriented features include fully TTL compatible
inputs and outputs. The three state outputs, controlled by
the OE input, will drive a minimum of 2 standard TTL loads.
The MK38000 operates from a single +5 volt power supply.
It is packaged in the industry standard 28 pin DIP. Pin 27 is
not connected in order to maintain compatiblity with RAMs
which use this pin as a write enable (WE) control function.
MK38000 ROM CODE DATA INPUT PROCEDURE
The preferred method of supplying code data to Mostek is in
the form of programmed EPROMs (see table). In addition to
the programmed set, Mostek requires an additional set of
blank EPROMs for supplying customer code verification.
When multiple EPROMs are required to describe the ROM,
they shall be designated in ascending address space with
the numbers 1, 2, 3, etc. As an example, EPROM #1 would
start with address space 0000 and go to 1FFFfor an 8K x 8
device. EPROM #2 would then start at address space 2000
and soon. A total of four8Kx8 devices would be required to
totally describe the address space of the 32K x 8 MK38000.
The MK38000 is controlled by the chip enable (CE) and
output enable (OE) inputs. A low level at the CE input
powers up the memory for an active cycle. The output
buffers, under the control of OE, will become active in CE
access time (t CEA ) if the output enable access time (tOEA)
requirement is met.
By maintaining valid address, the outputs will remain valid
and active until either CE or OE is returned to the high state
6r until an address is changed. After chip deselect time (t cez )
or output enable deselect time (t OEZ )' the output buffers will
go to a high impedance state.
customer. Approval is considered to be accepted when the
signed verification letter is returned to Mostek. The original
set of EPROMs will be retained by Mostek for the duration of
the prototyping process.
ACCEPTABLE EPROMs FOR CODE DATA
Table 1
A paper printout and verification approval letter will
accompany each verification EPROM. set returned to the
111-12
"
EPROM
# REQUIRED
2732
8
2764
4
MOSTEI(.
MEMORY COMPONENTS
Guidelines for Submitting and Verifying
Customer ROM Patterns
ROM PROGRAMMING GUIDE
CUSTOMER SPECIFICATIONS
It has always been Mostek's policy to service its customers
ROM needs in the most efficient way possible. In continuing
with this effort. Mostek has revised its ROM procedure to
better facilitate the market we serve. This new ROM
programming guide and information form will insure that all
pertinent information is received with the purchase order.
This will reduce the unnecessary delavs which develop
when sufficient information is not available.
If the customer desires different specifications for the ROM
selected than appears on the appropriate Mostek data
sheet; it is imperative that these specification changes be
well documented and sent to MosteK as early as possible.
This is important because any specification change must be
reviewed and accepted by Mostek before the ROM order
can be processed.
ROM DATA
DESCRIPTION OF ROM FORM
The first part of the ROM programming form is concerned
with providing all necessary customer information to
Mostek. This will simplify any correspondence which may
be necessary to complete the order in question.
The ROM generic type simply indicates the ROM series the
customer wishes to purchase. This indudes the following
Mostek series.
MK34000 Series
MK36000 Series
MK37000 Series
MK38000 Series
PACKAGE TYPE
The package type must be included on both the ROM form
and the purchase order to prevent parts being produced in
the wrong package. Currently, all prototypes and any followon quantities built in Dallas will be ceramic. Remember:
P = Ceramic, N = Plastic, J = Cerdip.
Mostek will accept a number of media and formats for the
inputting of programming data. This.flexibility will make it
easy for a customer to have his R<;'M order processed as
quickly as possible. The following ~able shows the media
that can be most easily processed Ity Mostek. When filling
out the ROM programming form, check the appropriate
block under pattern media.
PATTERN MEDIA
ROMs/PROMs: On Mostek's ROMs of 16K bit and larger
density, PROMs of the 2716, 2732, or 2764 type or pin
compatible ROMs may be submitted forthe ROM contents.
They must, however, be accompanied by the information
required for the Mostek ROM type in written form. Each
PROM or ROM submitted must also be clearly marked so
that no question arises as to its starting memory location.
(See ROM Programming Form on last page).
VERIFICATION MEDIA
For pattern verification, Mostek will supply a printout and
reprogrammed PROMs or magnetic tape.
CUSTOMER NUMBERS
To insure rapid turnaround of data verification information,
acceptable media should be used as outlined in the table. If
another method is desired, contact Mostek so that all
arrangements can be made and an accurate schedule can
be generated. Quick turnaround of verification information
cannot be guaranteed in cases where new software has to
be developed. Remember, when filling out the ROM
programming form, check the appropriate block under
verification media.
In the event the customer assigns a part number to the
Mostek ROM selected, this number should be entered on
the ROM form. This number will simplify any communication which may be necessary between the customer and
Mostek.
SPECIAL BRANDING
Special branding of Mostek ROMs is possible if the
instructions are indicated on the ROM programming form.
But due to space and printing limitations, any special
branding desired must be limited to 12 characters on one
line.
HOW THE PROGRAM WORKS
Mostek's ROM program is designed for maximum safety
with two verification steps that limit the liability of both the
111-13
II
customer and Mostek. However, it. circumstances dictate,
Mostek is. flexible enougl'\ to varyli:s procedures to better
serve its customers.
PATTERN VERIFICATION
Upon receipt of the ROM programming information form
and the ROM input data, Mostek engineering will regenerate the pattern data for customer verification. At this
point the only customer liability is a nominal data charge in
the event of a pattern change. Following customer
verification, Mostek begi ns prototype production. Customer
is now liable for mask charge and minimum order quantity
work in process.
The verification step can be waived so that prototype
production begins immediately upon receipt of the input
data. The time savings is the time for Mostek engineering to
generate verification plus the time necessary for the
customer to receive and verify the data. This savings is
usually less than two weeks. If data verification is waived,
the customer is liable for the mask charge plus the
minimum order quantity work-in-process material.
WAIVERS OF VERIFICATION
Arrangements must be worked out with Mostek prior to
committing deliveries based on verification waivers. If an
order is accepted by Mostek waiving pattern verification, the
quoted cycle time begins upon receipt of the input data and
only a small quantity of parts will be produced as prototypes.
If Mostek accepts an order waiving prototype verification,
the quoted cycle time will begin upon notification of pattern
verification and placement of order.
GENERAL INFORMATION
Production capacity cannot be reserved without written
verification in house and a purchase order. Therefore any
quotes for delivery will be subject to change until a purchase
order is obtained.
Limited quantities of parts are usually available from the
Mostek Dallas assembly facility shortly after prototype
shipments, but prior to standard follow on production.
These units will require an expedite adder in addition to the
standard price.
The appropriate Mostek price sheet contains information on
order minimums and price adders.
PROTOTYPE VERIFICATION
The second verification step in Mostek's ROM program is
that of prototype verification. The prototype quantity is
usually 25 parts which are considered part of the order
quantity for billing purposes. After the customer has verified
the prototype, in writing, as being correct, Mostek will
proceed with the production of the total remaining order.
ACCEPTABLE MEDIA
Table 1
The prototype verification step can also be waived and
Mostek will immediately begin production instead of
prototyping. The time savings gained from waiving
prototype verification is usually 5-6 weeks. If prototype
verification is waived, the customer is liable for the mask
charge plus all work-in-process material. If only prototype
verification is waived Mostek guaranties ROM data to agree
with data verified by customer.
111-14
ROM
PROM
Magnetic
Tape
MK34000P/N/J
X
X
X
MK36000P/NIJ
X
X
X
MK37000P/NIJ
X
X
X
MK38000P INI J
X
X
X
MKType
READ ONLY MEMORIES
Table 2
Device
Organization Logic
Number
Bits
Access
Supply Voltages
Vee
VSS
Power Dis
(mW) Max
Package
Type
Pins
BYTEWYDE
Pinout
MK34000
2048x8
Static
16384
350 ns
+5
0
330
P/N/J
24
Yes
MK36000
8192x8
Dynamic 65536
200 ns
+5
0
220
P/N/J
24
No
MK37000
8192x8
Dynamic 65536
200 ns
+5
0
220
P/N/J
28
Yes
MK38000
32768x8
Static
150 ns
+5
0
495
P/N/J
28
Yes
262144
ROM CROSS REFERENCE
Table 3
Mostek
MK34000
AMD
NEe
AM9218
,"PD2316E
MCM68316E 56831B
,"PD2364
MCM68364
MK36000
MK37000
Motorola
AMI
54264
GI
Svnertek
National
Signetics
Toshiba
SMC
RO-3-9316
5V2316B
MM52116
2616
TMM334P
2316E
RO-3-9364
5Y2364
MM52164
2664A
AM9265
36000
TMM2364P
MK38000
TMM 23256
111-15
all
ROM PROGRAMMING FORM
Customer Name _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ___
Address _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ___
City _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ State _ _ _ _ _ _ _ _ _ _ Zip _ _ _ _ _ _ _ ___
Phone (
Extension _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
Customer Contact ________________ Title _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
Mostek Rep or Dist _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~_ _ _ _ _ _ __
ROM Generic Type _ _ _ _ _ _ _ _ _ _ _ __
Customer Part #
Brand
(Including Pkg, Speed)
o Standard data sheet part
o
Customer Spec # _ _ _ _ _ _ _ _ _ _ _ ___
Date customer spec sent
to Mostek _-----,_ _ _ _ _ _ _ _ _ _ _ __
Spec review complete
0 Yes
Pattern Media
Verification Media
o PROM type
0 PROM type _ _ _ _ _ _ _ _ _ _ _ _ _ __
o
Pin Compatible ROMs - Note 1
o
Pin Compatible ROMs - Note 1
o
Magnetic Tape - Note 1
o
Magnetic Tape - Note 1
o
Other - Note 1
o
Other - Note 1
(Note l-Requires Factory Coordination)
Date Pattern Data Sent to Mostek _________
Does Customer Require Prototypes
yes _ _ _ _ _ __
No _ _ _ _ _ __
Pattern Verification Required by Customer
yes _ _ _ _ _ __
Waived _ _ _ _ __
Prototype Verification Required by Customer
yes _ _ _ _ _ __
Waived _ _ _ _ __
Pattern Verification To Be Sent To
Rep' _ _ _ _ _ __
Customer _ _ _ __
Customer signature approving waivers _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
Customer Order Number
_ _ _ _ _ _ _ _ _ _ _ _ _ Date _ _ _ _ _ _ _ _ _ _ __
Order Quantity and Price
Delivery Requested/Committed
Form Completed By
Prototypes _ _ _ _ _ _ _ _ _ _ Production _ _ _ _ _ _ _ _ _ __
_ _ _ _ _ _ _ _ _ _ _ _ _ _ Date _ _ _ _ _ _ _ _ _ _ _ __
111-16
1982/1983 MICROELECTRONIC DATA BOOK
Dynamic Random Access Memory
MOSTEI(.
4096x1-BIT DYNAMIC RAM
MK4027(J/N)-2/3
FEATURES
o
o
o
o
Industry standard
configu ration
120ns access time,
150ns access time,
200ns access time,
16-pin DIP (MK 4096)
o
Improved performance with "gated CAS", "RAS
only" refresh and page mode capability
320ns cycle (MK4027-1)
320ns cycle (MK4027,2)
375ns cycle (MK4027-3)
o
o
o
o
All inputs are low capacitance and TTL compatible
±10% tolerance on all supplies (+12\/, ±5V)
ECl compatible on VBB power supply (-5.7V)
o low Power: 462mW active (max)
I nput latches for addresses, chip select and data in
Three-state TTL compatible output
Output data latched and valid into next cycle
D MKB version screened to Mll-STD-883
27mW standby (max)
DESCRIPTION
The MK 4027 is a 4096 word by 1 bit MOS random
access memory circuit fabricated with MOSTEK's
N-channel silicon gate process. This process allows
the MK 4027 to be a high performance state-of-theart memory circuit that is manufacturable in high
volume. The M K 4027 employs a single transistor
storage cell utilizing a dynamic storage technique
and dynamic control circuitry to achieve optimum
performance with low power dissipation.
A unique multiplexing and latching technique for
the address inputs permits the MK 4027 to be packaged in a standard 16-pin DIP on 0.3 in. centers. This
package size provides high system-bit densities and is
compatible with widely available automated testing
and insertion equipment.
System oriented features include direct interfacing
capability with TTL, only 6 very low capacitance
address lines to drive, on-chip address and data
registers wh ich elimi nates the need for interface
registers, input logic levels selected to optimize noise
immunity, and two chip select methods to allow the
user to determine the appropriate speed/power
characteristics of his memory system. The MK 4027
also incorporates several flexible operating modes. In
addition to the usual reacj and write cycles, readmodify write, page-mode, and RAS-only refresh
cycles are available with the MK 4027. Page-mode
timing is very useful in systems requiring Direct
Memory Access (DMA) operation.
FUNCTIONAL DIAGRAM
PIN CONNECTIONS
V BB
16 Vss
4 - - V ••
DIN
WRITE 3
RAS 4
15
CAS
14
DOUT
CS
5
12
2
"
--~
., - - - - 1
"
-----I
Ao
A2
AI
6
7
A3
II A4
10 A5
Voo
8
9 Vee
PIN NAMES
"--~
., - - - - 1
13
54S£/IIS[-REFRESH
AO-AS
AMPLIFIERS
OAU, IN/OAT", OUT GoI,TlNG
OATA
~___~___-r_"~--,UT
OAU.
S:lU:cr
em;
cs
DIN
DOUT
"
~
WRITE
VBB
VCC
VDD
VSS
IV-1
ADDRESS INPUTS
COLUMN ADDRESS STROBE
CHIP SELECT
DATA IN
DATA OUT
ROW ADDRESS STROBE
READ/WRITE INPUT
POWER (-svi
POWER (+5VI
POWER (+ 12VI
GROUND
ABSOLUTE MAXIMUM RATINGS*
Voltage on any pin relative to VBB .............. -0.5V to +20V
Voltage on VDD, VCC relative to VSS ........... -1.0V to +15V
VBB-VSS (VDD-VSS > 0) ............................. OV
Operating temperature, T A (Ambient) ............ O°C to + 70°C
Storage temperature (Ambient)(Ceramic) ....... -65°C to + 150°C
Storage temperature (Ambient)(Plastic) ....... -55°C to + 125°C
Short circuit output current .......................... 50mA
Power dissipation ................................ " 1 Watt
*Stresses greater than those listed under
"Absolute Maximum Ratings" may cause
permanent damage to the device. This is
a stress rating only and functional opera-
tion of the device at these or any other
conditions above those indicated in the
operating sections of th is specification
is not implied.
Exposure to absolute
maximum rating conditions for extended
periods
may
affect
device
reliability.
RECOMMENDED DC OPERATING CONDITIONS 4
(One .;; T A';; 70°C) 1
PARAMETER
MIN
TYP
MAX
UNITS
VDD
Supply Voltage
10.8
12.0
13.2
volts
NOTES
VCC
Supply Voltage
4.5V
5.0
5.5
volts
2,3
VSS
Supply Voltage
0
0
0
volts
2
VSS
Supply Voltage
-4.5
-5.0
2
-5.7
volts
2
volts
2
VIHC
Logic 1 Voltage, RAS, CAS, WRITE
2.4
7.0
VIH
Logic ~Itage, all inputs except
RAS, CAS, WRITE
2.2
7.0
volts
2
VIL
Logic 0 Voltage, all inputs
-1.0
.8
volts
2
DC ELECTRICAL CHARACTERISTICS 4
(DoC < TA';; 70°C)1 (VDD = 12.0V ± 10%; VCC = 5.0V ± 10%; VSS = OV; -5.7V';; VBB ';;-4.5V)
PARAMETER
TYP
35
UNITS
mA
Standby VDD Power Supply Current
2
mA
IDD3
Average VDD Power Supply Current
during "RAS only" cycles
25
mA
ICC
VCC Power Supply Current
ISS
Average VSS Power Supply Current
150
Il A
II(L)
Input Leakage Current (any input)
10
Il A
7
IO(l)
Output Leakage Current
10
Il A
8,9
VOH
Output Logic 1 Voltage
-5mA
@
lOUT
~
VOL
Output Logic 0 Voltage
3.2mA
@
lOUT
~
MIN
IDDl
Average VDD Power Supply Current
IDD2
MAX
mA
NOTES
5
8
6
volts
2.4
0.4
volts
NOTES
1.
6.
T A is specified for operation at frequencies to tRC >tRC (min).
Operation at higher cycle rates with reduced ambient temperatures
and higher power dissipation is permissible provided that all AC
parameters are met. See figure 2 for derating curve.
7. All device pins at 0 volts except V BB which is at -5 volts and the
pin under test which is at +10 volts.
2. All voltages referenced to VSS'
8. Output is disabled (high-impedance) and rfAS and CAS are both
at a logic 1. Transient $tsbllization is required prior to measurement of th is parameter_
3. Output voltage will swing from VSS to Vee when enabled,with
no output load. For purposes of maintaining data in standby mode,
Vec may be reduced to VSS without affecting refresh operations or
data retention. However, the VOH (min) specification is not
guaranteed in this mode.
4. Several cycles are required after power-up before proper device
operation is achieved. Any 8 cycles which perform refresh are
adequate for this purpose.
5. Current is proportional to cycle rate. I 001 (max) is measured at
the cycle rate specified by tRC (min). See figure 1 for 1001 limits
at other cycle rates.
ICC depends on output loading. During readout of high level data
VCC is connected through a low impedance (13511 typ) to Data
Out. At all other times ICC consists of leakage currents only.
9. OV';;VOUT';;+ 10V.
10. Effective capacitance is calculated from the equation:
C
60 with 6
I'w
:=
V
:=
3 volts.
11. A.C. measurements assume tT = 5ns.
IV-2
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS(4, 11, 17)
= 12 OV+- 10%, VCC = 5 OV +- 10%, VSS = OV -5 7V.;; VBB ';;-4 5V)
(00 C.;; TA';; 70° C)1 (VDD
MK4027-2
PARAMETER
MIN
tRC
Random read or write cycle time
320
tRWC
Read write cycle time
tRMW
tpc
Read modify write cycle time
Page mode cycle time
320
320
170
MK4027-3
MAX
MIN
MAX
375
375
405
225
UNITS
NOTES
ns
12
ns
ns
ns
12
tRAC
Access time from row address strobe
150
200
ns
tCAC
tOFF
tRP
Access time from column address strobe
Output buffer turn-off delay
100
40
135
50
ns
ns
Row address strobe precharge time
100
tRAS
tRSH
Row address strobe pulse width
150
Row address strobe hold time
100
135
ns
tCAS
tCSH
tRCD
Column address strobe pulse width
Column address strobe hold time
100
150
135
200
ns
ns
Row to column strobe delay
Row address set-up time
20
tASR
tRAH
tASC
tCAH
tAR
120
10,000
50
200
25
65
ns
ns
ns
0
25
Column address set-up time
Col umn address hold time
-10
45
-10
55
ns
ns
Column address hold time referenced to RAS
Chip select set-up time
95
-10
120
ns
-10
55
ns
ns
tcsc
tCH
tCHR
tT
Chip select hold time
45
Ch ip select hold time referenced to RAS
Transition time (rise and fall)
95
tRCS
Read command set-up time
3
16
3
ns
50
ns
0
0
ns
17
tRCH
Read command hold time
0
0
tWCH
Write command hold time
45
55
ns
tWCR
twp
Write command hold time referenced to RAS
Write command pulse width
95
45
120
55
ns
tRWL
Write command to row strobe lead time
50
70
ns
tCWL
Write command to column strobe lead time
Data in set-up time
50
70
ns
0
ns
18
Data in hold time
Data in hold time referenced to RAS
45
95
0
55
120
ns
ns
18
tDS
tDH
tDHR
tCRP
tcp
Column to row strobe precharge time
Column precharge time
tRFSH Refresh period
twcs Write command set-up time
tCWD CAS to WR1TE delay
tRWD
tDOH
Data out hold time
0
ns
80
ns
2
ms
0
80
145
ns
ns
10
ps
ns
19
19
19
17. VIHC (l"'1in) or V1H (min) and VIL (max) are reference levels for
<
measuring timing of input signals. Also, transition times are
measured between VIHC or VIH and VIL'
12. The specifications for tRC: (min) and tRWC (min) are used only to
~~~~~~!er~~~e (~~ ;:'~ticJot)ej: ~~s:~:~~nS~~e;i~~;ef~I~~;~~;a_
ting curve.
ns
0
2
RAS to WRITE delay
Notes Continued
ns
60
0
60
110
10
II
ns
120
35
14, 15
ns
10,000
0
20
Row address hold time
12
12
13, 15
13. Assumes that tRCO
18. These parameters are referenced to
write cycles and to
~tRCO
14. Assumes that tACO ;?:tRCD (max).
WFfiT'E
C"AS
leading edge in random
leading edge in delayed write or read-
mOdify·write cycles.
(max).
19. twcs, tcwo, and tRWO are restrictive operating parameters in
.
~hr:~~~i:ii~ea~r :aeri~/:r~~~fc":~~j~~dVD~~aoOI~t ~i f~~~1a1~~hCesd(~~n),
>
15. Measured with a load circuit equivalent to 2 TTL loads and 100pF
written into the selected cell. If tCWD ~tCWD (min) and tRWD
tRWD (min), the cycle is a read-write cycle and Data Out will contain
data read from the selected cell. If neither of the above sets of conditions
is satisfied, the condition of Data Out (at access time) is indeterminate.
IV-3
AC ELECTRICAL CHARACTERISTICS
(DoC -'
,Q
"-
"::J
CIl
20mA
0
.9
"-
r-
r-~
.,~"'v
:P
~...
,;>V'>
.~p'"
~...~
/,1"L
",-0 ~~
~ ~"'~'- 1;>"-
'v"
..
....
~
....UJ
....2
..
"-
MK
4021.1I2~r-
60
UJ
iii
. I n this
"delayed write cycle" the data input set-up and
hold times are referenced--1Q the negative edge of
WRITE rather than to CAS.~illustrate this
feature, Data In is referenced to WRITE in the timing
diagram depicting the read-write and page mode
write cycles while the "earIY-YlU'ite" cycle diagram
shows Data In referenced to CASLNote that if the
chip is unselected (CS high at CAS time) WRITE
commands are not executed and, consequently,
data stored in the memory is unaffected.
Data is retrieved from the memory in a read cycle
by maintaining WR ITE in the inactive or high state
throughout the portion of the memory cycle in wh ich
CAS is active. Data read from the selected cell will
be available at the output within the specified access
time.
DATA OUTPUT LATCH
Any change in the condition of the Data Out Latch
is initiated by the CAS signal. The output buffer is
not affected by memory (refresh) cycles in which
only the RAS signal is applied to the MK 4027.
Whenever CAS makes a negative transition, the output will go unconditionally open-circuited, independent of the state of any other input to the chip. If
the cycle in progress is a read ,read-mod ify-write, or a
delayed write cycle and the chip is selected, then
the output latch and buffer will again go active and
at access time will contain the data read from the
selected cell. This output data is the same polarity
(not inverted) as the input data. If the cycle in
IllQ9ress is a write cycle (WR ITE active low before
CAS goes low) and the chip is selected, then at access
time the output latch and buffer will contain the
input data. Once having gone active, the output will
remain valid until the MK 4027 receives the next
CAS negative edge. Intervenin~fresh cycles in
which a RAS is received (but no CAS) will not cause
valid data to be affected. Conversely, the output
will assume the open-circuit state during any cycle
in which the MK 4027 receives a CAS but no RAS
signal (regardless of the state of any other inputs).
The output will also assume the......Q.Q.en circuit state in
normal cycles (in which both RAS and CAS signals
occur) if the chip is unselected.
The three-state data output buffer presents the data
output pin with a low impedance to VCC for a logic
1 and a low impedance to VSS for a logic O. The
output resistance to V CC (logic 1 state) is 420 n maximum and 135 n typically. The output resistance
to VSS (logic 0 state) is 125n maximum and 35 n
typicany. The separate VCC pin allows the output buffer to be powered from the supply voltage of
the logic to which the chip is interfaced. During
battery standby operation, the VCC pin may have
power removed without affecting the MK 4027 refresh~eration. This allows all system logic except
the RAS timing circuitry and the refresh address
logic to be turned off during battery standby to
conserve power.
REFRESH
Refresh of the dynamic cell matrix is accomplished
by performing a memory cycle at each of the 64 row
addresses within each 2 millisecond time interval.
Any cycle in which a RAS signal occurs, accomplishes
a refresh operation. A read cycle will refresh the
selected ..Low, regardless of the state of the Chip
Select (CS) input. A write or read-modify-write
cycle also refreshes the selected row, but the chip
should be unselected to prevent writing data into
the selected cell. If, during a refresh £{fIe, the
MK 4027 receives a RAS signal but no CAS signal,
the state of the output will not be affected.--tLowever, if "RAS-only" refresh cycles (where RAS is
the only signal applied to the chip) are continued
for extended periods, the output buffer may eventually lose proper data and go open-circuit. The
output buffer will r~gain. activi.tv with th~ first
cycle in which a CAS signal IS applied to the chip.
IV-8
POWER DISSIPATION/STANDBY MODE
Most of the circuitry used in the MK 4027 is dynamic
and most of the power drawn is the result of an
address strobe edge. Because the power is not drawn
during the whole time the strobe is active, the
dynamic power is a function of operating frequency
rather than active duty cycle. Typically, the power
is 170mW at 1 jlsec cycle rate for the MK 4027 with
a worse case power of less than 470mW at 320nsec
cycle time. To minimize the overall system power,
the Row Address Strobe (RAS) should be decoded
and supplied to only the selected chips. The CAS
must be supplied to all chips (to turn off the unselected output). Those chips that did not receive
a R~ however, will not dissipate any power on
the CAS edges, exceRt for that required to turn off
the outputs. If the RAS signal is decoded and suppllild only to the selected chips, then the Chip Select
(CS) input of alLQ}ips can be at a logic O. The chips
that receive a CAS but no RAS will be unselected
(output open-circuited) regardless of the Chip Select
input. For refresh cycles, however, eith~LJhe CS
input of all chips must be high or the CAS input
must be held high to prevent several "wire-OR'd"
outputs from turning on with opposing force. Note
that the MK 4027 will dissipate considerably less
power when the refresh operation is accomplished
with eRAS-only" cycle as opposed to a normal
RAS/CAS memory cycle.
This "page mode" of operation will not dissipate the
power associated with the negative going edge of
RAS. Also, the time required for strobing in a new
row address is eliminated, thereby decreasing the
access and cycle times. The chip select input (CS)
is operative in page mode cycles just as in normal
cycles. It is not necessary that the chip be selected
during the first operation in a sequence of page
cycles. Likewise. the CS input can be used to select
or disable any cycle(s) in a series of page cycles.
This feature allows the page boundary to be extended
beyond the 64 column locations in a single chip.
The page boundary can be extended by applying
RAS to multiple 4K memory blocks and decoding
CS to select the proper block.
POWER UP
The MK 4027 requires no particular power supply
sequencing so long as the Absolute Maximum Rating
Conditions are observed. However, in order to insure
compliance with the Absolute Maximum Ratings,
MOSTEK recommends sequencing of power supplies
such that VBB is applied first and removed last.
VBB shou Id never be more positive than VSS when
power is applied to VDD.
PAGE MODE OPERATION
The "Page Mode" feature of the MK 4027 allows
for successive memory operations at mu Itiple column
locations of the same row address with increased
speed without an increase in power. This is done by
strob.JmL the row address into the chip and keeping
the RAS signal at a logic 0 throughout all successive
memory cycles in which the row address is common.
Under system failure conditions in wh ich one or more
supplies exceed the specified limits significant additional margin against catastrophic device failure may
be achieved by forcing RAS and Data Out to the
inactive state.
After power is applied to the device, the MK 4027
requires several cycles before proper device operation
is achieved. Any 8 cycles which perform refresh are
adequate for this purpose.
IV-9
II
TYPICAL DEVICE CHARACTERISTICS
TYPICAL ADDRESS AND DATA INPUT LEVELS vs. VDD
3.0
TJ = 50°C
TJ = 50t
VBB =-5.0V
2.5
VBB=-5.0V
2.5
~
...J
a~
~
...J
a
~ 2.0
...J
W
-
~
>
W
1.5
...J
I-
:::>
-
Q.
z
-
TYPICAL CLOCK INPUT LEVELS vs. VDD
3.0
1.0
~
I-
VIHC (MIN)
...J
VIH (MIN)
W
>
~ 1.5
I-
i--
:::>
VIL (MAX)
Q.
~
0.5
VILC (MAX)
1.0
0.5
10
11
12
13
VDD SUPPLY VOL TAGE (VOLTS)
14
10
11
TYPICAL ADDRESS AND DATA INPUT LEVELS vs. VBB
2.5
13
14
TYPICAL CLOCK INPUT LEVELS vs. VBB
3.0
TJ = 50°C
TJ = 50°C
VDD =12.0\1,
2.5
VDD =12.0V
~
...J
~2.0
VIHC (MIN)
02.0
...J
~
VIH (MIN)
w
>
W
12
VDD SUPPL Y VOL TAG E (VOLTS)
3.0
en
I...J
a
I-
-
2.0
...J
W
~
1.5
...J
I-
1.5
...J
:::>
Q.
I-
VIL (MAX)
~
:::>
~ 1.0
0.5
- 4.0
-4.5
-5.0
-5.5
VBB SUPPLY VOLTAGE (VOLTS)
0.5
-6.0
-4.0
TYPICAL ADDRESS AND DATA INPUT LEVELS vs. Tj
3.0
VDD =12.0V
2.5
VILC (MAX)
Q.
1.0
TYPICAL CLOCK INPUT LEVELS vs. T J
"'DO =12.0V
VBB =-5.0\1
2.5
en
~
a
~
...J
a
~2.0
~2. 0
VIH(MIN)
w
...J
w
>
>
W
~ 1.5
...J
I-
I-
:::>
Q.
z
VIHC (MAX)
1.5
:::>
Q.
VIL(MAX)
~
- 1.0
0.5
-10
-6.0
3.0
VBB =·-5.0V
...J
-4.5
-5.0
-5.5
VBB SUPPLY VOLTAGE (VOLTS)
-
VIL (MAX)
1.0
20
50
80
T J. JUNCTION TEMPERATURE (OC)
O. 5
110
-10
IV-10
20
50
80
TJ. JUNCTION TEMPERATURE (t)
110
TYPICAL ACCESS TIME (NORMALIZED)
YS.
VDD
TYPICAL ACCESS TIME (NORMALIZED) YS. VBB
1.2 r - - - - - . , - - - - . . , - - - - - - , - - - - - - ,
1.2
~
..............
II
o
o
G
~
~
TJ = 50'C
~ 1.1
1.0
a:
TJ = 50'C
~ 1.1~------+_------~------_r------_i
~
II
III
III
-............
I-
:::: 0.9
o
o
G
G1O~------+_---+---_+------_i
~.
a:
~
1::
~ 0.9 ~------+_------~------_r------_i
G
u
~O.S
a:
~O.SI-------+--------i-------~--------i
I-
I-
0.7
10
11
12
13
VDD SUPPLY VOLTAGE (VOLTS)
TYPICAL ACCESS TIME (NORMALIZED)
0.7 '-:--=-_--:-'-::-_ _-=-~--_=_=---____=
-4.0
-4.5
-5.0
-5.5
-6.0
14
VBB SUPPLY VOLTAGE (VOLTS)
YS.
~
TYPICAL ACCESS TIME (NORMALIZED)
YS. JUNCTION TEMPERATURE
VCC
1.2
1.2
U
TJ=50't
I!:> 1.1
~ 1.1~------t-------+_------~------~
Ltl
II
u
G1.0~----~~----~-------+------_i
2u 1.0
U 0.9 1-------+-------+-------+-------,
-::;
1:: 0.9
U
«a:
~
a:
1::
1::
u
/
~
G
a:
u
~O.S~------t-------+_------~------~
V
/
/
I- O.S
I-
0.7
0.7 L:-:,...-----:''=---~"...---_:f_::----~
4.0
4.5
5.0
5.5
6.0
VCC SUPPL Y VOLTAGE (VOLTS)
TYPICAL 1001
YS.
-10
TYPICAL 1001
VDD
35~-----~-----~------~----~
-
so
110
VS.
JUNCTION TEMPERATURE
35
TJ=50'C
~30
130~------~------t_-------t_----~
~=~~
I-
50
20
TJ. JUNCTION TEMPERATURE (' C)
tRC = 320ns
I-
Z
Z
w
w
~25r-------+---~~~-------+------~
~25
tRC = ;J7tms
-
:::l
:::l
>
i201------=+-------~~~~~------__i
c..
>
tRC = 500ns
i20
c..
tRr - 600n5
fI)
fI)
u
u
:::l
:::l
C
~15
9151------=~------~------_+------__i
10
-10
10~----~~----~~------~----~
10
11
12
13
VDD SUPPLY VOLTAGE VOLTS
14
20
50
80
TJ. JUNCTION TEMPERATURE ('C)
IV-11
---------_._---------------_._----
110
II
IV·12
MOSTEI(.
4096x 1-BIT DYNAMIC RAM
MK4027(J/N)-4
FEATURES
o Industry standard 16-pin DIP (MK 4096)
o Improved performance with "gated CAS", "RAS
o
o
o
o
o
configuration
250ns access time, 380ns cycle
o ±10% tolerance on all supplies (+12\/, ±5V)
o ECl compatible on VSS power supply (-5.7V)
o low Power: 462mW active (max)
27mW standby (max)
only" refresh and page mode capability
All inputs are low capacitance and TTL compatible
Input latches for addresses, chip select and data in
Three-state TTL compatible output
Output data latched and valid into next cycle
o MKS version screened to Mll-STD-883
DESCRIPTION
The MK 4027 is a 4096 word by 1 bit MOS random
access memory circuit fabricated with MOSTEK's
N-channel silicon gate process. This process allows
the MK 4027 to be a high performance state-of-theart memory circuit that is manufacturable in high
volume. The MK 4027 employs a single transistor
storage cell utilizing a dynamic storage technique
and dynamic control circuitry to achieve optimum
performance with low power dissipation.
A unique multiplexing and latching technique for
the address inputs permits the MK 4027 to be packaged in a standard 16-pin DIP on 0.3 in. centers. This
package size provides high system-bit densities and is
compatible with widely available automated testing
and insertion equipment.
System oriented features include direct interfacing
capability with TTL, only 6 very low capacitance
address lines to drive, on-chip address and data
registers which eliminates the need for interface
registers, input logic levels selected to optimize noise
immunity, and two chip select methods to allow the
user to determine the appropriate speed/power
characteristics of his memory system. The MK 4027
also incorporates several flexible operating modes. In
addition to the usual react and write cycles, readmodify write, page-mode, and ~-only refresh
cycles are available with the MK 4027. Page-mode
timing is very useful in systems requiring Direct
Memory Access (DMA) operation.
FUNCTIONAL DIAGRAM
PIN CONNECTIONS
nFE----~======[)--------------------_1
"
----~
Vss
16 Vss
2
DIN
WRITE 3
15 CAS
14 DOUT
RAS
4
13 CS
Ao
5
A2
6
12 A3
II A4
AI
7
10 A5
Vee
8
9 Vce
"
------..j
PIN
"
----~
AO-A5
"
------..j
cs
------I
~T
c;s:s
DIN
"
"
NAMES
WRITE
VBB
VCC
VDD
VSS
IV-13
ADDRESS INPUTS
COLUMN ADDRESS STROBE
CHIP SELECT
DATA IN
DATA OUT
ROW ADDRESS STROBE
READ/WRITE INPUT
POWER (-5V)
POWER (+5V)
POWER (+ 12V)
GROUND
II
ABSOLUTE MAXIMUM RATINGS*
Voltage on any pin relative.to VBB .............. -0.5V to +20V
Voltage on VOO, VCC relative to VSS ........... -1.0V to +15V
VBB-VSS (VOO-VSS > 0) ............................. OV
Operating temperature, T A (Ambient) ............ O°C to + 70°C
Storage temperature (Ambient)(Ceramic) ....... -65°C to + 150°C
Storage temperature (Ambient)(Plastic) ....... -55°C to + 125°C
Short Circuit Output Current .......................... 50mA
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1 Watt
*Stresses greater. than those listed under
"Absolute Maximum Ratings" may cause
permanent damage to the device. This is
a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the
operating sections of this specification
is not implied.
Exposure to absolute
maximum rating conditions for extended
periods may affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS 4
(Ooc .;; T A .;; 70°C) 1
PARAMETER
MIN
TYP
MAX
UNITS
VOO
Supply Voltage
10.8
12.0
13.2
volts
2
VCC
Supply Voltage
4.5V
5.0
5.5
volts
2,3
VSS
Supply Voltage
0
0
0
volts
2
-5.0
-5.7
volts
2
NOTES
VBB
Supply Voltage
-4.5
VIHC
logic 1 Voltage, RAS, CAS, WRITE
2.4
7.0
volts
2
VIH
!:.291.c 1 Voltage, all inputs except
RAS, CAS, WRITE
2.2
7.0
volts
2
Vil
logic 0 Voltage, all inputs
-1.0
.8
volts
2
DC ELECTRICAL CHARACTERISTICS 4
(DoC .;;TA';; 70t)' (VOO = 12.0V ± 10%; VCC = 5.0V ± 10%; VSS = OV; -5.7V';; VBB ';;-4.5V)
1001
PARAMETER
Average VOO Power Supply Current
1002
MAX
35
UNITS
mA
Standby VOO Power Supply Current
2
mA
1003
Average VOO Power Supply Current
during "AAS only" cycles
25
mA
ICC
VCC Power Supply Current
IBB
Average VBB Power Supply Current
150
p.A
II(l)
Input leakage Current (any input)
10
p.A
7
p.A
8,9
,IO(l)
Output leakage Current
VOH
Output logic 1 Voltage
-5mA
@
lOUT =
VOL
Output logic 0 Voltage
3.2mA
@
lOUT =
MIN
TYP
mA
10
NOTES
5
8
6
volts
2.4
0.4
volts
NOTES
,. T A is specified for operation at frequencies to tRC ~tRC (min).
2. All voltages referenced to VSS'
3. Output voltage will swing from VSS to Vec when enabled,with
no output load. For purposes of maintaining data in standby mode,
~a1~ r~t~~:~~d~~~e!~r:~Se ~i~h~(:n~~f)e~~~nC~f~~:~~~~ f~~~~tions or
7. All device pins at 0 volts except Vee which is at -5 volts and the
pin under test which is at +10 volts.
8. Output is disabled (high-impedance) and F!fA'S and ~ are both
at a logic 1. Transient ttabTlization is required prior to measurement of th is parameter.
guaranteed in this mode.
10. Effective capacitance is calculated from the equation;
4. Several cycles are required after power-up before proper device
operation is achieved. Any 8 cycles which perform refresh are
adequate for this purpose.
5. Current is proportional to cycle rate.IOOl (max) is measured at
the cycle rate specified by tAC (min). See figure 1 for 1001 limits
at other cycle rates.
6. ICC depends on output loading. During readout of high level data
Vec is connected through a low impedance (135S! typ) to Data
Out. At all other times Ice consists of leakage currents only.
c
= 00 with 1'1 V = 3 volts.
I'1v
11. A.C. measurements assume tT = 5ns.
12. The specifications for tRC (min) and tRWC (min) are used only to indicate
cycle time at which proper operation over the full temperature range (0° ~
TA ~ 70°C) is assured.
IV-14
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS(4,11, 17)
(00 C.;;; TA';;; 70° C)1 (VDD = 12.0V± 10%, VCC = 5.0V ± 10%, VSS = OV, -5.7V';;; VBB ';;;-4.5V)
MK4027-4
MAX
UNITS
NOTES
PARAMETER
MIN
tRC
Random read or write cycle time
380
ns
12
tRWC
Read write cycle time
ns
tRMW
Read modify write cycle time
395
470
12
12
tpc
Page mode cycle time
285
tRAC
Access time from row address strobe
tCAC
Access time from column address strobe
tOFF
Output buffer turn-off delay
tRP
tRAS
ns
ns
12
250
165
ns
13.15
14,15
60
ns
Row address strobe precharge time
0
120
Row address strobe pulse width
250
10,000
tRSH
Row address strobe hold time
tCAS
Column address strobe pulse width
tCSH
Column address strobe hold time
165
165
250
tRCD
Row to column strobe delay
35
tASR
Row address set-up time
Row address hold time
0
35
ns
tRAH
tASC
Column address set-up time
ns
tCAH
Column address hold time
tAR
Column address hold time referenced to RAS
-10
75
160
tcsc
Chip select set-up time
ns
tCH
Chip select hold time
tCHR
Chip select hold time referenced to RAS
-10
75
160
IT
Transition time (rise and fall)
tRCS
Read command set-up time
3
0
ns
ns
ns
ns
ns
85
16
ns
ns
ns
ns
ns
ns
50
17
ns
ns
0
75
160
ns
Write command pulse width
75
ns
tRWL
Write command to row strobe lead time
85
ns
tCWL
Write command to column strobe lead time
85
ns
0
75
160
0
110
ns
18
ns
18
tRCH
Read command hold time
tWCH
Write command hold time
tWCR
Write command hold time referenced to RAS
twp
tDS
Data in set-up time
tDH
Data in hold time
tDHR
Data in hold time referenced to RAS
tCRP
Column to row strobe precharge time
tcp
Column precharge time
tRFSH
Refresh period
twcs
Write command set-up time
tCWD
CAS to WRITE delay
tRWD
RAS to WRITE delay
tDOH
Date out hold time
II
ns
ns
ns
ns
ns
ns
2
ms
0
ns
19
90
175
10
ns
19
19
ns
I's
17. VIHC (min) or VIH (min) and VIL (max) are reference ievels for
measuring timing of input signals. Also, transition times are
measured between VIHC or VIH and VIL-
Notes Continued
13. Assumes that tRCD ~tRCD (rna. ).
14. Assumes that tACO ~ tRCD (max).
15. Measured with a load circuit equivalent to 2 TTL loads and 100pF
16. Operation within the tReD (max) limit insures that tF\AC (max)
can be met. tACO (max) IS specified as a reference POint only; if
tRCD is greater than the specified tRCD (max) limit, then access
time is controlled exclusively by tCAC'
18. These parameters are referenced to CAS leading edge in random
write cycles and to W"R'i"T'E leading edge in delayed write or readmodify-write cycles.
.
19. twcs, tCYVD, and tRWD are restrictive operating parameters in
a read/write or read/modify/write cycle only. If twcs ~twcs (mm),
the cycle is an early write cycle and Data Out wilr cOntain the data
written into the selected cell. If tCWD ~tCWD (min) and tRWD ~
tRWD (min), the cycle is a read-write cycle and Data Out will contain
data read from the selected cell. If neither of the above sets of conditions
is satisfied, the condition of Data Out (at access time) is indeterminate.
IV-15
------------~
...
.~-~-.--->~----. "~~
~
..
AC ELECTRICAL CHARACTERISTICS
(DoC ,;;;;TA';;;; 70t) (VDD = 12.0V ± 10%; VSS = OV;-5.7V';;;;VBB,;;;;-4.5V)
PARAMETER
TYP
MAX
UNITS
C 11
Input Capacitance (AO·A5), DIN, CS
4
5
pF
10
C 12
Input Capacitance RAS, CAS, WR ITE
8
10
pF
10
Co
Output Capacitance (DOUT)
5
7
pF
MAXIMUM 1001 vs. CYCLE RATE FOR DEVICE OPERATION
AT EXTENDED FREQUENCIES
Figure 1
CYCLE TIME tCYC (ns)
380
400
500
1000
300
250
50mA
«
40mA
E.
fZ
~~
w
a:
a:
::l
v~~
30mA
fvv~
U
~
>-
:P
..J
~'?"
a.
a.
-$>»"
::l
en
C;
r-- -
E
I- -
/
lOrnA
o
,~
~
20rnA
~~
-<.-{~
~*'l
i./
~
i.-
"""
o
1.0
2.0
CYCLE RATE (MHz)
3.0
= 103 /tCYC
4.0
(ns)
SUPPLEMENT - To be used in conjunction with MK4027(J/N)-1/2/3 data sheet.
IV-16
NOTES
8,10
MOSTEI{.
16,384 X 1-BIT DYNAMIC RAM
MK4116(J/N/E)-2/3
FEATURES
o Recognized industry standard 16-pin configuration from MOSTEK
o
150ns access time, 320ns cycle (M K 4116-2)
200ns access time, 375ns cycle (MK 4116-3)
o Read-Modify-Write, R'AS-only refresh, and Pagemode capability
o All inputs TTL compatible,low capacitance, and
protected against static charge
o ± 10% tolerance on all power supplies (+12V, ±5V)
o 128 refresh cycles
o Low power: 462mW active, 20mW standby (max)
o ECl compatible on VBB power supply (-5.7V)
o Output data controlled by CAS and unlatched at
o MKB version screened to MIL-STD-883
end of cycle to allow two dimensional chip selection and extended page boundary
o JAN version available to MIL-M-3851 01240
o Common I/O capability using "early write"
operation
DESCRIPTION
The MK 4116 is a new generation MOS dynamic
random access memory circuit organized as 16,384
words by 1 bit. As a state-of-the-art MOS memory
device, the MK 4116 (16K RAM) incorporates
advanced circuit techniques designed to provide
wide operating margins, both internally and to the
system user, while achieving performance levels
in speed and power previously seen only in MOSTEK's
high performance MK 4027 (4K RAM).
The technology used to fabricate the M K 4116 is
MOSTEK's double-poly, N-channel silicon gate,
POL Y II
process. This process, coupled with the
use of a single transistor dynamic storage cell, provides the maximum possible circuit density and
reliability, while maintaining high performance
e
FUNCTIONAL DIAGRAM
capability. The use of dynamic circuitry throughout, including sense amplifiers, assures that power
dissipation is minimized without any sacrifice in
speed or operating margin. These factors combine
to make the MK 4116 a truly superior RAM product.
Multiplexed address inputs (a feature pioneered by
MOSTEK for its 4K RAMS) permits the MK 4116
to be packaged in a standard 16-pin 01 P. This
recognized industry standard packalle configuration,
while compatible with widely available automated
testing and insertion equipment, provides highest
possible system bit densities and simplifies system
upgrade from 4K to 16K RAMs for new generation
applications. Non-critical clock timing requirements
allow use of the multiplexing technique while maintaining high performance.
PIN CONNECTIONS
Vaa
DIN
WRITE
RAS
Ao
A2
AI
VOD
I
16
2
15
3
14
4
13
5
12
6
II
7
10
8
9
Vss
CAS
DOUT
A6
A3
A4
As
Vee
PIN NAMES
ADDRESS INPUTS
COLUMN ADDRESS
STROBE
DATA IN
DATA OUT
ROW ADDRESS STROBE
Available per MIL-STO-883 B. Mostek is qualified per JM38150ClassB.
IV-17
WRITE
VBB
Vee
VDD
Vss
READIWRITE INPUT
POWER (-5V)
POWER (+5V)
POWER (+12V)
GROUND
II
ABSOLUTE MAXIMUM RATINGS*
Voltage on any pin relative to VBB ................... '. -O.5V to +20V
Voltage on VOO, Vee suppliEls relative toVSS .......... -1.0V to +15.0V
VBB-VSS (VOO-VSS>OV) .................................. OV
Operating temperature, T A (Ambient) ................... ooe to + 70'C
Storage temperature (Ambient) Ceramic ............... -55°e to + 150°C
Storage temperature, (Ambient) Plastic ................... -55°C to +125°C
Short circuit output current ................................. 50mA
Power dissipation ........................................ 1 Watt
RECOMMENDED DC OPERATING CONDITIONS6
(Ooe <;T A <; 70°C)
·Stresses greater than those listed under
"Absolute Maximum Ratings" may cause
permanent damage to the device. This is a
stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum
rating conditions for extended periods may
affect reliabilitv.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIIS
Supply Voltage
VOO
VCC
VSS
VBB
10.8
4.5
0
-4.5
12.0
5.0
13.2
5.5
0
0
-5.0
-5.7
Volts
Volts
Volts
Volts
2
2,3
2
2
Input High (Logic 1) Voltage,
RAS, CAS, WRITE
VIHC
2.4
-
7.0
Volts
2
Input High (Logic 1) Voltage,
all inputs except RAS, CAS
WRITE
VIH
2.2
-
7.0
Volts
2
Input Low (Logic 0) Voltage,
all inputs
VIL
-1.0
-
.8
Volts
2
DC ELECTRICAL CHARACTERISTICS
(O°C ~TA ~70°C) (VDD = 12.0V ± 10%;VCC =5.0V ±10%; -5.7V ~ VBB ~ -4.5V; VSS
PARAMETER
SYMBOL
OPERATING CURRENT
Average power supply operating current
(RAS, CAS cycling; tRC
tRC Min
1001
ICCl
IBBl
STANOBY CURRENT
Power supply standby current (liAS = VIHC.
00UT = High Impedance)
1002
ICC2
IBB2
REFRESH CURRENT
Average power supply current, refresh mode
(i"fAS cycling, CAS = VIHC; tRC tRC Min
1003
ICC3
IBB3
PAGE MOOE CURRENT
Average power supply current, page·mode
operation (RAS =VIL.CAS cycling;
1004
ICC4
IBB4
=
=
tpc
= tpc
NOTES
= OV)
MAX
UNITS
35
mA
200
IJ.A
-10
1.5
10
100
mA
IJ.A
IJ.A
25
10
200
mA
IJ.A
IJ.A
4
-10
27
mA
4
5
200
p.A
MIN
NOTES
4
5
Min
INPUT LEAKAGE
Input leakage current, any input
(VBB = -5V, OV <; VIN <; +7.0V, all other
pins not under test = 0 volts)
II(L)
-10
10
p.A
OUTPUT LEAKAGE
Output leakage current (OOUT is disabled,
OV <; VOUT <; +5.5V)
10(L)
-10
10
P.A
OUTPUT LEVELS
Output high (Logic 1) voltage (lOUT = -5mA)
VOH
2.4
Output low (Logie 0) voltage (lOUT = 4.2 mAl
VOL
Volts
0.4
3
Volts
NOTES:
1.
T A. is specified here for operation at frequencies to tRC ~tRC
(mm). Operation at higher cycle rates with reduced ambient
temperatures and higher power dissipation is permissible, however, provided AC operating parameters are met. See figure 1
for derating curve.
2.
All voltages referenced to VSS.
3.
Output voltage will swing from VSS to Vce when activated with
no current loading. For purposes of maintaining data in standby
mode, Vec may be reduced to VSS without affecting refresh
operations or data retention. However, the VOH (min) specification is not guaranteed in this mode.
4.
~~~rli~~9r~f~~~,&g!rd~~~I~dr~t~S~Ycle
5.
~9Cfi 19~nl~~ii
0
"
>-
t
iii
2i
9
II,.
3.0
2.0
CYCLE RATE (MHz)
4.0
=103 /tRC(ns)
+ ,~q
It'
'limA
---
++
9.0 x Icycle rate MHz -2.661 for -3. T A Imaxl
x cycle rate MHz -3.125MHzl for-2 only.
°c = 70 -
7
~~ ",P
..
'limA
Fig. 1 Maximum ambitmt temperature versus cycle rate for extended
frequency operation. T A (max) for operation at cycling ra~es greater
than 2.66 MHz ItCYC<375nsl is determined by T A Imax)
pit
~;~ ... - ~~
,o~~~ ~~
-- -17
~
.
~
I~
,1 ,<-v""T
--
30mA
250
t
,~
i5
a:
a:
50
1.0
300
...
~
o
400
I
N
lL
lI-
...
320
C
-
,..
= 70-
9.0
_. --
,..
CYCLE RATE (MHz)
3.•
=103 1 tRC(ns)
...
Fig. 2 Maximum I D01 versus cycle rate for device operation at
extended frequencies. J DD1 (max) curve is defined by the equation:
1001 Imaxl mA
...
...
CYCLE TIME tRC(ns)
,
SOmA
300
,..
1001 Imaxl mA
= 10 + 9.4 x cycle rate
= 10 + B.O x cycle rate
-3
IMHz) for
[MHz) for -2
CYCLE TIME tpC(nl)
...
.......
,
SOmA
300
250
....A
<
!
...z
w
a:
a:
=>
0
>-
,,'1>' ~~
'!Ji~
P.:+L·
...
t
iii
a
9
"«,.
<
--
...
....'
--
i5
a:
a:
=>
0
,,.to ~
30mA
...>-
-:\0...iO~~P <\_'1-'
ZOmA
.....
!
,.to\'"
311mA
.
\""\'"(~-~~
t
iii
~<,.
0
9
~,s'l
ZOmA
~""p..
II,.
'limA
~
'limA
•
1.0
2.0
10
IOC \.-
".
\O~~~ ~)
1"":'"
...
CYCLE RATE (MHz) .103/tRC(nl)
••
1.0
2.0
3.0
CYCLE RATE (MHz) - 103 Itpc(ns)
Fig. 3 Maximum I 003 versus cycle rate for device operation at
Fig. 4 Maximum 1004 versus cycle rate for device operation in page
extended frequencies. 1003 (max) curve is defined by the equation:
mode.
1003(maxl mA = 10 + 6.5 x cycle rate [MHz! for -3
1003(maxl mA = 10 + 5.5 x cycle rate [MHz! for -2
1004 [max) mA
'004
(maxI
curve
is
defined
= 10 + 3.75 x cycle rate
by
(MHz) for -3
1004 Imaxl mA = 10 + 3.2 x cycle rate [MHz! for -2
IV-20
the
equation:
4.0
READ CYCLE
tRC----------------------~
~------------------------- tRAS--------~
RAS
I
!.------------------tesH
---------~~
tRCD ____....-;~----_;_I-- tRSH
-----:-:-----"""'"'\1--,. !4_-----'--
CAS
V1HC -
VIL
----------t<~
teAs ----~~
-
II
V'H_
ADDRESSES
WRITE
V 1L-
V IHCV
l--
I L -.l....I.:..L.I...l....L..I...L...L""t'................""
t
CAC
----~..,
f---
t RAC _____________~
1,-------..1
VOH - ________________________
DOUT
VALID
DATA
OPEN
VOL -
WRITE CYCLE (EARLY WRITE)
t RC
t RAS
tAR
"I
I
t RCD
t RSH
tcs~
tCAS
ADDRESSES
_------t DHR
VOH~
DOUT
-----_~
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ___
OPEN
VOL -
IV-21
tOFF
READ-WRITE/READ-MODIFY-WRITE CYCLE
_---------tRWC/tRMw--------tooj
RAS
I
t RSH _ _ _ _ _~
+I lCSH_-===========!I r . - - V - - - t
V,HC-
CAS
V,L -
ADDRESSES
V'H-
V'L-
Dour
"RAS-ONLY" REFRESH CYCLE
NOTE: CAS = VIHC, WRITE = Don't Care f * - - - - - - t R C . - - - - - - - - - I
VOH -
---------OPEN-----------
IV-22
PAGE MODE READ CYCLE
I RAS --------------~--~
~==~~+=====~------------~'J~~I-.-----I-RS-"_____': ~
"'->-----'CRP
V,HC·-_--:--;----...k
:j
V'L-
V'H
ADDRESSES viL-
DOUT
--;I_
VOH-_ _ _ _ _
0 PEN
-~
VOL-"7"T777"7"T777tRCS:::1rt.--L
~',~?///!I////!j
I
~
_ _ _:_J.--'_tRCHJ---'ll-r7-rTb
VffiW$/;Iff~
PAGE MODE WRITE CYCLE
~--------------------tRAS ------------------------~
ADDRESSES
IV-23
DESCRIPTION (continued)
prior to CAS, the DI N is strobed by C& and the
set-up and hold times are referenced to CAS. If the
input da.ta is not available at CAS time or if it is
desired that the cycle be a read-write cycle. the
WRITE signal wi!.1 be delayed until after CAS has
made its negative transition. In this "delayed write
cycle" the data input set-up and hold times are referenced to the negative edge of WR ITE rather than
&ASrFo illustrate this feature, DIN is referenced to
RI
in the timing diagrams depicting the readwrite and page-mode write cycles while the "early
write" cycle diagram shows DIN referenced to CAS).
System oriented features include ± 10% tolerance on
all power supplies, direct interfacing capability with
high performance logic families such as Schottky
TTL, maximum input noise immunity to minimize
"false triggering" of the inputs (a common cause of
soft errors), on-chip address and data registers which
eliminate the need for interface registers, and two
chip select methods to allow the user to determine
the appropriate speed/power characteristics of his
memory system. The MK 4116 also incorporates
several flexible timing/operating modes. In addition
to the usual read, write, and read-modify-write
cycles, the M K 4116 is capable -2Ldelayed write
cycles, page-mode operation and RAS-only-EJresh.
Proper control of the clock inputs( RAS, CAS and
WRITE) allows common I/O capability, two dimensional chip selection, and extended page boundaries
(when operating in page mode).
Data i3 retrieved from the memory in a read cycle
by maintaining WR ITE in the inactive or high state
throughout the portion of the memory cycle in wh ich
CAS is active (low). Data read from the selected cell
will be available at the output within the specified
access time.
ADDRESSING
DATA OUTPUT CONTROL
The 14 address bits required to decode 1 of the
16,384 cell locations within the MK 4116 are multiplexed onto the 7 address inputs and latched into the
on-chip address latches by externally applying two
negative going TTL-level clocks. The first clock, the
Row Address Strobe (RAS), latches the 7 row address
bits into the chiR. The second clock, the Column
Address Strobe (CAS), subsequently latches the 7
column address bits into the chip. Each of these
signals, RAS and CAS, triggers a sequence of events
which are controlled by different delayed internal
clocks. The two clock chains are linked together
logically in such a way that the address multiplexing
operation is done outside of the critical path timing
sequence for read data access. The later events in
the CAS clock sequence are inhibited until the
occurence of a delayed sign!l.!...Q.erived from the RAS
clock chain. This "gated CAS" feature allows the
CAS clock to be externally activated as soon as the
Row Address Hold Time specification (tRAH) has
been satisfied and the address inputs have been
changed from Row address to Column address
information.
The normal condition of the Data Output (DOUT)
of the MK 4116 is the high impedance (open-circuit)
state. That is to say, anytime CAS is at a high level,
the DOUT pin will be floating. The only time the
output will turn on and contain either a logic 0 or
logic 1 is at access time during a read cy'cle. DOUT
will remain valid from access time until CAS is taken
back to the inactive (high level) condition.
Note that CAS can be activated at any time after
tRAH and it will have no effect on the worst case
data access time (tRAC) up to the point in time when
the delayed row clock no longer inhibits the remaining sequence of column clocks. Two timing endpoints result from the internal gating of CAS which
are called tRGD (min) and tRCD (max). No data
storage or reading errors will result if CAS is applied
to the MK 4116 at a point in time beyond the tRCD
(max) limit. However, access time will then be determined exclusively by the access time from CAS
(tCAC) rather than from RAS (tRAC), and access
time from RAS will be lengthened by the amount
that tRCD exceeds the tRCD (max) limit.
DATA INPUT/OUTPUT
Data to be written into a selected cell is latched into
an on-chip r~*§ter by a combination of WRITE and
CAS while
is active. The later of the signals
(W RITE or CAS) to make its negative transition is the
strobe for the Data In (D IN) register. This permits
several options in the write cycle timing. In a write
cycle, if the WR ITE input is brought low (active)
If the memory cycle in progress is a read, read-modify
write, or a delayed write cycle, then the data output
will go from the high impedance state to the active
condition, and at access time will contain the dati
read from the selected cell. This output data is thl
same polarity (not inverted) as the input data. Oncl..
having gone active, the output will remain valid until
CAS is taken to the precharge (logic 1) state,whether
or not RAS goes into precharge.
I~cycle in progress is an "early-write" cycle
(WRITE active before CAS goes active), then the
output pin will maintain the high impedance state
throughout the entire cycle. Note that with this
type of output configuration, the user is given full
control of the~ pin simply by controlling the
placement of WRlTE command during a write cycle,
and the pulse width of the Column Address Strobe
during read operations. Note also that even though
data is not latched at the output, data can remain
valid from access time until the beginning of a subsequent cycle without paying any penalty in overall
memory cycle time (stretching the cycle).
This type of output operation results in some very
significant system implications.
Common I/O Operation - If all write operations are
handled in the "early write" mode, then DIN can be
connected directly to DOUT for a common I/O data
bus.
Data Output Control - DOUT will remain valid
during a read cycle from tCAC until CAS goes back
to a high level (precharge), allowing data to be valid
from one cycle up until a new memory cycle begins
with Q.QJ>enalty in cycle time. This also makes the
RAS/CAS clock timing relationship very flexible.
Two Methods of Chip Selection -
IV·24
Since DOUT
is not latched, CAS is not required to turn off the
outputs of unselected memory devices in a matrix.
This means that both CAS and/or RAS can be decoded for chip selection. If both RAS and CAS are
decoded, thEm a two dimensional" (X,Y) chip select
array c~n be realized.
. Extended Page Boundary - Page-mode operation
allows for successive memory cycles at multiple
column locations of the same row address. By decoding CAS as a page cycle select signal, the page
boundary can be extended beyond the 128 column
locations in a single chip. (See page-mode operation).
OUTPUT INTERFACE CHARACTERISTICS
The three state data output buffer presents the data
output pin with a low impedance to VCC for a logic
1 and a low impedance to VSS for a logic O. The
effective resistance to V CC (logic 1 state) is
420 n maximum and 135n typically. The resistance
to VSS (logic 0 state) is 95 n maximum and 35 n
typically. The separate VCC pin allows the output
buffer to be powered from the supply voltage of the
logic to which the chip is interfaced. During battery
standby operation, the VCC pin may have power
removed without affecting the MK 4116 refresh
operation. This allows all system logic except the
RAS timing circuitry and the refresh address logic to
be turned off during battery standby to conserve
power.
PAGE MODE OPERATION
The "Page Mode" feature of the MK 4116 allows for
successive memory operations at multiple column
locations of the same row address with increased
speed without an increase in power. This is done by
strobing the row address into the chip and maintaining the RAS signal at a logic 0 throughout all successive memory cycles in which the row address is common. This "page-mode" of operation will not dissipate the~wer associated with the negative going
edge of RAS. Also, the time required for strobing
in a new row address is eliminated, thereby decreasing the access and cycle times.
POWER CONSIDERATIONS
Most of the circuitry used in the MK 4116 is dynamic
and most of the power drawn is the result of an
address strobe edge. Consequently, the dynamic
power is primarily a function of operating frequency
rather than active duty cycle (refer to the MK 4116
current waveforms in figure 5). This current characteristic of the M K 4116 precludes inadvertent
burn out of the device in the event that the clock
inputs become shorted to ground due to system
malfunction.
Although no particular power supply noise r~stri~ti~n
exists other than the supply voltages remam Wlthm
the specified tolerance limits, adequate decoupling
should be provided to suppress high frequency
noise resulting from the transient current of tht;!
device. This insures optimum system perfprmance
and reliability. Bulk capacitance requirements are
minimal since the MK 4116 draws very little steady
state (DC) current.
In system applications requiring lower power dissipation . the operating frequency (cycle rate) of the
MK 4116 can be reduced and the (guaranteed maximum) average power dissipation of the device will be
lowered in accordance with the I DDl (max) spec
limit curve illustrated in figure 2 .
NOTE: The
MK 4116 family is guaranteed to have a maximum
1001 requirement of 35mA@ 375ns cycle (320nscycle
for the -2) with an ambient temperature range from 0°
to 70°C. A lower operating frequency, for example 1
microsecond cycle, results in a reduced maximum Iddl
requirement of under 20mA with an ambient
temperature range from 0° to 70°C.
It is possible the MK4116 family (-2 and 3 speed
selections for example) at frequencies higher than
specified, provided all AC operating parameters are met.
Operation at shorter cycle times «tRC min) results in
higher power dissipation and, therefore, a reduction in
ambient temperature is required. Refer to Figure 1 for
derating curve.
NOTE: Additional power supply tolerance has been included on the VBS
supply to allow direct interface capability with both -5V systems -S.2V Eel
systems.
The page boundary of a single MK 4116 is limited to
the 128 column locations determined by all combinations of the 7 column address bits. However, in
system applications which utilize more than 16,384
data words, (more than one 16K memory block), the
page boundary can be extended by using CAS rather
than liAS as the chip select signal. RAS is applied to
all devices to latch the row address into each device
and then CAS is decoded and serves as a page cycle
select signal. Only those devices which receive both
RAS and CAS signals will execute a read or write
cycle.
RAS/CAS CYCLE
r~
II
r
fI
If
m ONLY CYCLE
LONG RA'SJeAS CYCLE
1"-
L
flit
REFRESH
Refresh of the dynamic cell matrix is accomplished
by performing a memory cycle at each of the 128
row addresses within each 2 millisecond time interval.
Although any normal memory cycle will perform the
refresh operation'Jhis function is most easily accomplished with "RA -only" cycles. liAS-only refresh
results in a substantial reduction in operating power.
This. reduction in power is reflected in the IDD3
specification.
"
V
+80
(~~~ +60
V
In
1'50 NANOSECONDS I DIVISION
Fig. 5 Typical Current Waveforms
IV-25
III
IV
II
.
Although RAS and/or CAS can Oe decoded and used
as a chip select sifJnal for the MK 4116,overall system
power is minimized if the Row Address Strobe
(RAS) is used for this purpose. A1L.!:!.pselected devices (those which do not receive a RAS) will remain
in a lo~ower (standby) mode regardless of the
state of CAS.
such that VBB is applied first and removed last.
VBB should never be more positive than VSS when
power is applied to VDD.
Under system failure conditions in which one or more
supplies exceed the specified limits significant additional !l1argin agains.t catastrophic..deltice failu.re m~y
be achlevea by forcmg RAS and CAS to the mactlve
state (high level).
POWER UP
The MK 4116 requires no particular power supply
sequencing so long as the Absolute Maximum Rating
Conditions are observed. However, in order to insurE
compliance with the Absolute Maximum Ratings,
MOSTE K recommends sequencing of power supplies
After power is applied to the device, the MK 4116
requires several cycles before proper device operation
is achieved. Any B cycles which perform refresh
are adequate for this purpose.
TYPICAL CHARACTERISTICS
1.2 TYPICAL ACCESS TIME lNORMALIZEO)
~
~
TYPICAL ACCESS TIME (NORMALIZEOJ ... Vee
TYPICAL 1001.' JUNCTION TEMPERATURE
n. ,Voo
I
OO··13.2V:
TJ~50C
1.1
30-------4-
8
2:.1.!1
lffir--
~~O.9
t-
H--1
JRC~50On.
ItRt-750",
~O.8e--+--
--±,,--,!o,---7.
"'.~,,~--!,~,
I
I
'~!o,,----;,m,--7.,,--0'0,,-----;
"""---!",.--,,,,,-~'!---.
voo SUPPLY VOLTAGE (VOLTS)
VOD SUPl'LYVDlTAGE (VOLTS)
t
J
--j;;~
-
TJ.JUNCTIONTEMPERATUREI CI
Vee SUPPLY VOLTAGE (VOLTS)
TYPICAL I003 Y'. VOO
TYPICAL ACCESS TIME INORMAlIZEOI ... VCC
~ 'PMCK-II
"
~10
.,.
f
.,;11
U
~
I
:
I
>
12
~::
13
~
I
B09
11
!16
II
,
VOD SUPPLY VOL lAGE (VOL lSI
4.0
~'2
t ·
8
1
.9,0
'"
4.5
6.0
5.5
VCCSUPf'LYVOLTAGElVOLTSI
11
12
13
VOOSUPPLYVOLTACElVOLTSI
TYPIC AlI 004.' VOO
TYPICAL ID03 .. JUNCTION TEMPERATURE
00. 13.2\1
"
~ 18
~'8
~ 16
!18
~
~.
~
~'4 _
~ 14
~
~12
~12
Voo SUPPLY VOLTAGE (VOL TSI
TJ.JUNCTIONTEMPERATURE( CI
TYPICAL CLOCK INPUT LEVELS .. VOO
,., r----.---,---,---,
"'M' I
2.5
VBB'-UI~
!
t --- :- ~.--
TYPICAL CLOCK INPUT LEVELS .. TJ
TVPIC4lClOCK INPUT LEVelS ... V88
~;:ICAL
ADDRESS AND DATA INPUT LEVELS .. Voo
TJ-50C!
2.5
DD·,2.OVl- _ _ _ _ _~_ _
2.01--._~IHC(MIN
--
25
vea-- 50 V\
VIHC(MINI
~IHIMIN)
VIHC(MINI
I
--:--------,....-----VllCIMAX
_ - - - - - - - - v ; V I L C (MAX
-~
VSB SUPPLY VOL lAGE (VOL TSI
Voo SUPPlV VOLTAGE (VOLTS)
t --r---
",~,-----;i;;"-----.iJ;-----.;J;----1'
TJ.JUNCTIONTEMPERATUREI C)
TYPICAL ADORe >S AND DATA INPUT lEVelS .. Vss
3.0
TJ=soc.1
2.5.:EP--=-~2.EV.
I
3~OYP1CALADORESSANODATAINPUTLEVELS
2.5V::::::~
T
--
+--.-.
VILCIMAX
!
yO
i
~
I
~20f--~----r-----c----1
V1HIMIN)
i - _ - + - _ - f V I H (MINI
i----t
!
i - - - + - - - f V I L (MAX)
0.5 4 .0
+.-
I""·'"
20
50
80
TJ.JUNCTIONTEMPERATUREI C)
V88SUPPLYVOLTAGEIVOLTSI
IV-26
TJ
_
.k
---('lIMAX)
VOOSUPPLY VOLTAGE IVOLTSI
MOSTEI{.
16.384x1-BIT DYNAMIC RAM
MK4116(J/N/E)-4
FEATURES
Recognized industry standard 16-pin configuration from MOSTEK
o
Read-Modify-Write, RAS-only refresh, and Pagemode capability
o
250ns access time, 410ns cycle
o
o
o
o
All inputs TTL compatible,low capacitance, and
protected against static charge
± 10% tolerance on all power supplies (+12V, ±5V)
o
128 refresh cycles (2 msec refresh interval)
o
ECl compatible on VBB power supply (-5.7V)
o
o
low power: 462mW active, 20mW standby (max)
Output data controlled by CAS and unlatched at
end of cycle to allow two dimensional chip selection and extended page boundary
-
D MKB version screened to Mll-STD-883
D JAN version available to Mll-M-3851 01240
Common I/O capability using "early write"
operation
DESCRIPTION
The MK 4116 is a new generation MOS dynamic
random access memory circuit organized as 16,384
words by 1 bit. As a state-of-the-art MOS n'l'emory
device, the MK 4116 (16K RAM) incorporates
advanced circuit techniques designed to provide
wide operating margins, both internally and to the
system user, while achieving performance levels
in speed and power previously seen only in MOSTE K's
high performance MK 4027 (4K RAM).
capability. The use of dynamic circuitry throughout, including sense amplifiers, assures that power
dissipation is minimized without any sacrifice in
speed or operating margin. These factors combine
to make the MK 4116 a truly superior RAM product.
The technology used to fabricate the M K 4116 is
MOSTE K's double-poly, N-channel silicon gate,
POLY II
process. This process, coupled with the
use of a single transistor dynamic storage cell, provides the maximum possible circuit density and
reliability, while maintaining high performance
Multiplexed address inputs (a feature pioneered by
MOSTEK for its 4K RAMS) permits the MK 4116
to be packaged in a standard 16-pin DIP. This
recognized industry standard packa\!e configuration,
while compatible with widely available automated
testing and insertion equipment, provides highest
possible system bit densities and simplifies system
upgrade from 4K to 16K RAMs for new generation
applications. Non-critical clock timing requirements
allow use of the multiplexing technique while maintaining high performance.
FUNCTIONAL DIAGRAM
PIN CONNECTIONS
e
..
~.
-'
--------Vi.
DIN
WRITE
RAS
Ao
A2
AI
voo
',MEMORY
ARRAY
MEMORY
ARRAY
IS
VBB
--,~
-'''---,:========::0
15
2
3
14
4
13
5
12
S
II
7
10
8
9
vss
CAS
DOUT
A6
A3
A4
A5
vee
PIN FUNCTIONS
'.------1
I4-COLVMM
- -'SEL£CT I..INES---
Ao-As
CAS
DIN
DOUT
RAS
IV-27
Address Inputs
Column Address
Strobe
Data In
Data Out
Row Address Strob
iiiiRiTE
Vee
VCC
V DD
VSS
Read/Write Input
Power (-5V)
Power (+5V)
Power (+12V)
Ground
II
ABSOLUTE MAXIMUMRATINGS*
Voltage on any pin relative to VBB ................... '. -O.5V to +20V
Voltage on VDD, VCC suppliE!s relative to VSS .......... -1.0V to +15.0V
VBB-VSS (VDD-VSS>OV) ....... : .......................... OV
Operating temperature, T A (Ambient) ................... O°C to + 70't:
Storage temperature (Ambient) (Ceramic) .••.........•... -65°C to + 150°C
Storage temperature (Ambient) (Plastic) .................. -55°C to + 125°C
Short circuit output current ••..•..•................................ 50mA
Power dissipation .......•..•................•....••.............. 1 Watt
RECOMMENDED DC OPERATING CONDITIONS
(O°C ';;;T A';;; 70°C) 1
·Stresses greater than those listed under
"Absolute Maximum
permanent damage to
stress rating only and
of the device at these
Ratings" may cause
the device: This is a
functional operation
or any other condi-
tions above those indicated in the opera·
tional sections of this specification is not
implied.
Exposure to absolute maximum
rating conditions for extended periods may
affect reliabilitY.
MIN
TYP
MAX
UNITS
VOO
VCC
VSS
VBB
10.8
4.5
0
-4.5
12.0
5.0
0
-5.0
13.2
5.5
0
-5.7
Volts
Volts
Volts
Volts
1
1,2
1
1
VIHC
2.4
-
7.0
Volts
1
Input High (Logic 1) Voltage,
all inputs except RAS, CAS
WRITE
VIH
2.2
-
7.0
Volts
1
Input Low (Logic 0) Voltage,
all inputs
VIL
-1.0
-
.8
Volts
1
PARAMETER
SYMBOL
Supply Voltage
Input High (Logic 1) Voltage,
RAS, CAS, WRITE
NOTES
DC ELECTRICAL CHARACTERISTICS
{O°C';;; TA';;; /O°C)l (VDD = l2.0V ±10%; VCC = 5.0V ±10%; -5.7V';;; VBB';;; -4.5; VSS =OV)
PARAMETER
SYMBOL'
MAX
UNITS
OPERATING CURRENT
Average power supply operating current
(RAS, CAS cycling; tRC = 410ns)
1001
ICCl
IBBl
35
mA
200
P.A
STANOBY CURRENT
Power supply standby current.( R"AS = V I HC,
00UT = High Impedance)
1002
ICC2
IBB2
-10
1.5
10
mA
p.A
p.A
REFRESH CURRENT
Average power supply current, refresh mode
(RAS cycling, CAS = VIHC; tRC = 410ns)
1003
ICC3
IB83
27
10
mA
p.A
p.A
3
-10
PAGE MOOE CURRENT
Average power supply current, page·mode
operation (RAS =VIL,CAS cycling;
tpc = 275ns)
1004
ICC4
IBB4
27
mA
3
4
INPUT LEAKAGE
Input leakage current, any input
(VBB = -5V, OV';;; VIN';;; +7 .OV, all other
pins not under test = 0 volts)
II(L)
-10
10
p.A
OUTPUT LEAKAGE
Output leakage current (OOUT is disabled,
OV';;; VOUT .;;; +5.5V)
10(L)
-10
10
P.A
OUTPUT LEVELS
Output high (Logic 1) voltage (lOUT = -5mA)
VOH
2.4
Output low (Logic 0) voltage (lOUT = 4.2 mAl
VOL
MIN
NOTES
3
4
p.A
Volts
0.4
3
Volts
NOTES:
1.
All voltages referenced to Vss.
2.
Output voltage will swing from VSS to Vee when activated with
no current loading. For purposes of maintaining data in standby
mode, Vee may be reduced to Vss without affecting refresh
IV-2S
operations or data retention. However, the VOH (min) specifica~
tion is not guaranteed in this mode.
ELEOTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (5.6.7)
(ooe.;:;; TA';:;; 70°C) Voo = 12.0V ±10%; Vee = 5.0V ±10%; Vss= OV, -5.7V';:;; VBB';:;; -4.5V)
PARAMETER
SYMBOL
Random read or write cycle time
Read-write cycle time
tRC
Page mode cycle time
Access time from RAS
Access time from CAS
Output buffer turn-off delay
Transition time (rise and fali)
RAS precharge time
RAS pulse width
RAS hold time
CAS pulse width
CAS hold time
RAS to CAS delay time
CAS to RAS precharge time
Row Address set-up time
Row Address hold time
Column Address set-up time
Column Address hold time
Column Address hold time referenced to RAS
Read command set-up time
Read command hold time
Write command hold time
Write command hold time referenced to RAS
Write command pulse width
tpc
Write command to RAS lead time
Write command to CAS lead time
Data-in set-up time
Data-in hold time
Data-in hold time referenced to HAS
CAS precharge time (for page-mode cycle only)
Refresh period
WRITE command set-up time
CAS to WRITE delay
RAS to WRITE delay
tRWL
tCWL
tDS
tDH
tDHR
I DO 1, 1003, and I DD4 depend on cycle rate.
410
425
500
275
tRWC
tRMW
Read Modify Write
3.
MK4116-4
MIN
MAX
tRAC
tCAC
tOFF
tT
tRP
tcp
0
3
150
250
165
165
250
35
-20
0
35
-10
75
160
0
0
75
160
75
85
85
0
75
160
100
tREF
twcs
tCWD
tRWD
-20
90
175
tRAS
tRSH
tCAS
tCSH
tRCO
tCRP
tASR
tRAH
tASC
tCAH
tAR
tRCS
tRCH
tWCH
tWCR
twp
The maximum
1001 (max) [MA)~10+10.25x cycle rate [MHz)
1003 (max) [MA)~10+7 x cycle rate [MHz)
1004 (max) [MA) ~10 + 4.7 x cycle rate [MHz)
4.
'CC1 and ICC4 depend upon output loading. During readout of
high level data Vee is connected through a low impedance (135
typ) to data out.
At all other times ICC consists of leakage
currents only,
5.
Several cycles are required after power-up before proper device
operation is achieved. Any 8 cycles which perform refresh are
adequate for this purpose.
'
6.
AC measurements assume tT=5ns.
7.
8.
~~~£r(i~~n;i~i~gl
Assumes that tRCD ~tRCD (max).
10.
Measured with a load equivalent to 2 TTL loads and 100pF.
IV-29
10000
10000
85
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
8,10
9,10
11
7
12
13
13
14
14
14
tOFF (max) defines the time at which the output achieves the
open circuit condition and is not referenced to output voltage
levels.
12.
Operation within the tReD (max) limit insures that tRAC (max)
can be met. tRCO (max) is specified as a reference point only; if
tRCD is greater than the specified tRCD (max) limit, then access
time is controlled exclusively by tCAC.
13.
These parameters are referenced to ~ leading edge in early
write cycles and to WRITE leading edge in delayed write or
read·modify·write cycles.
14.
twcs, tCWD and tRWD are restrictive operating parameters in
read write and read modify write cycles only. If twcs ;;;. twcs
(min), the cycle is an early write cycle and the data Ollt pin will remain open circuit (high impedance) throughout the entire cycle; If
tCWD ;;;. tcwo (min) and tRWD ;;;. tRWD (min), the cycle is a
read-write cycle and the data out will contain data read from the
selected cell; If neither of the above sets of conditions is satisfied
the condition of the data out (at access time) is indeterminate.
15.
Effective capacitance calculated from the equation
with D. v = 3 volts and power supplies at nominal
levels.
16.
CAS ~ VIHC to disable 00UT.
{~i~~ta~?g~l; (m~~!o~r~r~e::j~~~~e tli~:~s ~~;
9.
250
165
60
50
11.
HO{f
measured between VIHC or VIH and VIL'
Assumes that tRCD~ tRCD (max). If tRCO is greater than the
maximum recommended value shown in this table, tRAC will
increase by the amount that tRCD exceeds the value shown.
NOTES
ns
ns
2
fr~~;f~~d o~~~~e~~c~:I~::e:r:ref~ret~~~7:~dO~~ at~~ ~~TI~!~~;~qltPa~
tions:
UNITS
ns
C =~v
~
AC ELECTRICAL CHARACTERISTICS
(O°C';; T A';; 70°C) (VDD = 12.0V ± 10%; VSS
PARAMETER
= OV, -5.7V';;
SYMBOL
VBB';; -4.5V)
TYP
MAX
UNITS
I
NOTES
Input Capacitance (AO-A6), DIN
Cll
4
5
pF
17
Input Capacitance RAS, CAS, WRITE
CI2
8
10
pF
17
Output Capacitance (DOUT)
Co
5
7
pF
17,18
DESCRIPTION (continued)
System oriented features include ± 10% tolerance on
all power supplies, direct interfacing capability with
high performance logic families such as Schottky
TTL, maximum input noise immunity to minimize
"false triggering" of the inputs (a common cause of
soft errors), on-chip address and data registers which
eliminate the need for interface registers, and two
chip select methods to allow the user to determine
the appropriate speed/power characteristics of his
memory system. The MK 4116 also incorporates
several flexible timing/operating modes. In addition
to the usual read, write, and read-modify-write
cycles, the M K 4116 is capable .QLdelayed write
cycles, page-mode operation and RAS-only~resh.
Proper control of the clock inputs( RAS, CAS and
WRITE) allows common I/O capability, two dimensional chip selection, and extended page boundaries
(when operating in page mode).
SUPPLEMENTAL DATA SHEET TO BE USED IN
CONJUNCTION WITH MOSTEK MK4116(J/N/E)-2/3 DATA SHEET.
IV-30
MOSTEI(.
MEMORY COMPONENTS
16,384 x 1-Bit Dynamic RAM
MK4516(NIJ)-10/12/15
FEATURES
o Recognized industry standard 16-pin configuration from
Mostek
o Read, Write, Read-Write, Read-Modify-Write and PageMode capability
o Single +5 V (± 10%) supply operation
o On chip substrate
performance
o Common 1/0 capability using "early write"
bias generator for
optimum
o Active power 193 mW maximum
Standby power 20 mW maximum (MK4516-10)
Standby power 17 mW maximum (MK4516-12/15)
o 100 ns access time, 235 ns cycle time (MK4516-10)
120 ns access time, 270 ns cycle time (MK4516-12)
150 ns access time, 320 ns cycle time (MK4516-15)
o A" inputs TTL compatible, low capacitance, and
protected against static charge
o Scaled POLY 5 technology
o Pin compatible with the MK4564 (64K RAM)
o 128 refresh cycles (2 msec)
DESCRIPTION
The MK4516 is a single +5 V power supply version of the
industry standard MK4116, 16,384 x 1 bit dynamic RAM.
The high performance features of the MK4516 are
achieved by state-of-the-art circuit design techniques as
we" as utilization of Mostek's "Scaled POLY 5" process
technology. Features include access times starting where
the current generation 16K RAMs leave off, TTL
compatability, and +5 V only operation.
The MK4516 is capable of a variety of operations including
READ, WRITE, READ-WRITE, READ-MODIFY-WRITE,
PAGE MODE, and REFRESH.
The MK4516 is designed to be compatible with the JEDEC
standards for the 16K x 1 dynamic RAM. The MK4516 is
intended to extend the life cycle of the 16K RAM, as we" as
create new applications due to its superior performance.
The compatability with the MK4564 will also permit a
common board design to service both the MK4516 and
MK4564 (64K RAM) designs. The MK4516 will therefore
permit a smoother transition to the 64K RAM as the
industry standard MK4027 did for the MK4116.
The user requiring only a sma" memory size need no longer
pay the three power supply penalty for achieving the
economics of using dynamic RAM over static RAM when
using this new geoeration device.
PIN OUT
Figure 1
DUAL-IN-LiNE PACKAGE
PIN FUNCTIONS
N/C 1
DIN 10)2
Aa·A6
CAS(CE)
Address Inputs
itiS (RE)
Col. Address Strobe
WRITE
DIN (D)
Data In
N/C
Not connected
DOUT(O)
Data Out
Vee
Power (+5V)
Vss
GND
WiiiTE(W}
RAS(RE}
Row Address Strobe
WVl Read/Write Input
Ao 5
A,6
A,7
vee 8
Available soon in MIL-STD-883 Class B (MKB4516)
IV-31
~----.----
---------
---
3
4
16 Vss
15
CAs (CEJ
14 DouT(Q)
13 Aa
12 A3
11 A4
10 Aa
9 N/C
ABSOLUTE MAXIMUM RATINGS*
Voltage on Vce Supply Relative to Vss .....•.................................................. -1.0Vto +7.0 V
Operating Temperature, TA (Ambient) ............................................................ O°C to + 70°C
Storage Temperature (Ceramic) .............................................................. -65°C to +150°C
Storage Temperature (Plastic) ............................................................... -55°C to +125°C
Power Dissipation .................................................................................. 1 Watt
Short Circuit Output Current ......................................................................... 50 mA
*Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
(O°C ::; TA::; 70°C)
SYM
PARAMETER
MIN
TYP
MAX
UNITS
NOTES
Vcc
Supply Voltage
4.5
5.0
5.5
V
2
V IH
Input High (Logic 1) Voltage,
All Inputs
2.4
-
Vcc +1
V
2
V il
Input Low (Logic 0) Voltage,
All Inputs
-2.0
-
.8
V
2,19
MAX
UNITS
NOTES
35
mA
3
3
mA
3.5
mA
21
DC ELECTRICAL CHARACTERISTICS
(O°C ::; TA ::; 70°C) (Vcc = 5.0 V ±1 0%)
SYM
PARAMETER
ICCI
OPERATING CURRENT
Average power supply operating current
(RAS, CAS cycling, t RC =t RC min.)
ICC2
STANDBY CURRENT
Power supply standby current (RAS
DOUT = High Impedance)
MIN
= CAS = V IH ,
ICC3
RAS ONLY REFRESH CURRENT
Average power supply current, refresh mode
(RAS cycling, CAS = V IH; t RC =t RC min.)
30
mA
3
ICC4
PAGE MODE CURRENT
Average power supply current, page mode
operation (RAS = V ll, tRAS = t RAS max., CAS
cycling; tpc =tpc min.)
32
mA
3,20
II(l)
INPUT LEAKAGE
Input leakage current, any input
(0 V ::; VIN ::; +5.5 V, all other
pins not under test = 0 volts)
-10
10
p.A.
100l)
OUTPUT LEAKAGE
Output leakage current (D OUT is disabled,
o V::; V OUT ::; +5.5 V)
-10
10
p.A.
0.4
V
V
V OH
VOL
OUTPUT LEVELS
Output High (Logic 1) voltage (lOUT = -5 mAl
Output Low (Logic 0) voltage (lOUT = 4.2 mA
IV-32
2.4
AC ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS (4,5,6,16)
(O°C:5 TA :5 70°C), VCC
= 5.0 V ± 10%
SYMBOL
MK4516-10
MK4516-12
MK4516-15
PARAMETER
MIN
MIN
MIN
tRELREL tRC
Random read or write cycle time
235
270
320
ns
7,8
tRELREL tRMw
(RMW)
Read-modify-write cycle time
285
320
410
ns
7,8
tRELREL tpc
(PC)
Page mode cycle time
125
145
190
ns
7,8,20
tRELOV tRAC
Access time from RAS
100
120
150
ns
8,9
tCELOV t CAC
Access time from CAS
55
65
80
ns
8,10
t CEHOZ tOFF
Output buffer
turn-off delay
0
45
0
50
0
60
ns
11
tT
Transition time (rise
and fall)
3
50
3
50
3
50
ns
6,16
tREHREL tRP
RAS precharge time
110
tRELREH t RAS
RAS pulse width
115
tCELREH t RSH
RAS hold time
70
85
105
ns
tRELCEH tCSH
CAS hold time
100
120
165
ns
tCELCEH tCAS
CAS pulse width
55
1()4
65
1()4
95
1()4
ns
tRELCEL t RCD
RAS to CAS delay time
25
45
25
55
25
70
ns
12
tREHWX tRRH
Read command hold time
referenced to RAS
0
0
0
ns
13
tAVREL t ASR
Row Address set-up time
0
0
0
ns
tRELAX tRAH
Row Address hold time
15
15
15
ns
tAvCEL tASC
Column Address set-up time
0
0
0
ns
tCELAX tCAH
Column Address hold time
15
15
20
ns
tRElA(C)~ tAR
Column Address hold time
referenced to RAS
60
70
90
ns
tWHCEL tRCS
Read command set-up time
0
0
0
ns
tCEHWX tRCH
Read command hold time
referenced to CAS
0
0
0
ns
tCELWX t WCH
Write command hold time
25
30
45
ns
tRELWX t WCR
Write command hold time
referenced to RAS
70
85
115
ns
t WLWH twp
Write command pulse width
25
30
50
ns
tWLREH t RWL
Write command to RAS lead time
60
65
110
ns
tWLCEH tCWL
Write command to CAS lead time
45
50
100
ns
STD
ALT
tT
MAX
MAX
120
1()4
IV-33
140
MAX UNITS NOTES
135
1()4
175
ns
1()4
ns
13
•
AC ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS (Continued)
SYMBOL
STD
ALT
PARAMETER
MK4516·10
MK4516·12
MK4516·15
MIN
MIN
MIN
MAX
MAX
MAX UNITS NOTES
tDVCEL t DS
Data-in set-up time
0
0
0
ns
14
tCELDX tDH
Data-in hold time
25
30
45
ns
14
tRELDX tDHR
Data-in hold time referenced to
RAS
70
85
115
ns
tCEHCEL tcp
(PC)
CAS precharge time
(for page mode cycle only)
60
70
85
ns
'RVRV
Refresh period
tREF
2
2
2
20
ms
tWLCEL twcs
WRITE command set-up time
0
0
0
ns
15
tCELWL tCWD
CAS to WRITE delay
55
65
80
ns
15
tRELWL t RwD
RAS to WRITE delay
100
120
150
ns
15
tCEHREL t CRP
CAS to RAS precharge time
0
0
0
ns
CAPACITANCE
(O°C s:: TA s:: 70°C) (Vcc = 5.0 V
SYMBOL
PARAMETER
Cl1
± 10%)
TYP
MAX
Input (Ao-A 6 ), DIN
4
5
pF
17
CI2
Input RAS, CAS, WRITE
8
10
pF
17
Co
Output (D OUT )
5
7
pF
17,18
NOTES:
1. No user connection to Pin 1 (Leadless Chip Carrier only). This pin must be left
floating.
2. All voltages referenced to VSS.
3. ICC is dependent on output loading and cycle rates. Specified values are
obtained with the output open.
4. An initial pause of 500 p.S is required after power-up followed by any 8 RAS
start-up cycles before proper device operation is achieved. RAS may be
cycled during the initial pause. If RAS inactive interval exceeds 2ms, the
device must be re-initialized by a minimum of 8 RAS start-up cycle.
5. AC characteristics assume tr = 5 ns
6. VIH min and VIL max are reference levels for measuring timing of input
signals. Transition times are measured between VIH and VIL.
7. The minimum specifications are used only to indicate cycle time at which
proper operation over the full temperature range (O°C :::; TA ::; 70°C) is
assured.
8. Load = 2 TTL loads and' 00 pF.
9. Assumes that tRCO ::; tRCO (max). If tRCO is greater than the maximum
recommended value shown in this table, tRAC will increase by the amount
that tRCO exceeds the value shown.
10. Assumes that tRCD "" tRCD (max).
11. tOFF max defines the time at which the output achieves the open circuit
condition and is not referenced to VOH or VOL.
UNITS NOTES
12. Operation within the tRCO (max) limit insures that tRAC (max) can be met.
tRCO (max) is specified as a reference point only; if tRCO is greater than the
specified tRCO (max) limit, then access time is controlled exclusively by
tCAC·
13. Either tRRH or tRCH must be satisfied for a read cycle.
14. These parameters are referenced to CASleading edge in early write cycles
and to WRITE leading edge in delayed write or read-modify-write.
15. twcs, tCWD' and tRWD are restrictive operating parameters in
READ/WRITE and READ/MODIFY/WRITE cycles only. If twcs "" twcs
(min) the cycle is an EARLY WRITE cycle and the data output will remain
open circuit throughout the entire cycle.lftCW02::tCWD (min)and tRWO;:::
tRWO (min)the cycle isa READ/WRITE and the data output will contain data
read from the selected cell. If neither of the above conditions are met the
condition of the data out (at access time and until CAs goes back to VIH) is
indeterminate.
16. The transition time specification applies for all input signals. In addition to
meeting the transition rate specification, all input signals must transit
between V IH and VIL (or between VIL and VIH) in a monotonic manner.
17. Effective capacitance calculated from the equation c:o:: I gwith ,1.V:o:: 3 volts
and power supply at nominal level.
!J.V
18. CAs = VIH to disable DOUT.
19. Includes the dc level and all instantaneous signal excursions.
20. Page Mode operation is not guaranteed on the standard MK4516. This
function is available on request.
21. Applies to MK4516-10 only.
IV-34
READ CYCLE
Figure 2
t RC
t RAS
RAS
tAR
V IH
VIL
tT
tCSH I
t RSH
CAS
tCAS
V IH
VIL
ADDRESSES
V IH
II
VIL
WRITE
V IH
VIL
~--------------tRAC--------------~
1_----.1
V OH
VALID
DATA
OPEN
DoUT
VOL
WRITE CYCLE (EARLY WRITE)
Figure 3
t Rc
t RAS
V IH
iiAS
tAR
VIL
-I
t
CfH
t RSH
tCAS
V IH
CAS
VIL
V IH
ADDRESSES
Wiii'iE
VIL
V IH
VIL
'_----+----+t RWL-----------------I~
I
I
_I
,..
~tos
f + - tOH
VALID
DATA
"-----------tOHRI--------t
VOH ____________________________________ OPEN - - - - - - - - - - - - - - - - - - - - - - - - - - - - VOL
IV-35
READ-WRITE/READ-MODIFY-WRITE CYCLE
Figure 4
1+-------iiAs
tRMW
---------.1
V'H
V'L
CAS
V'H
V'L
ADDRESSES
V'H
V'L
Wiiii'E
V'H
V'L
D'N
V OH
VOL
I
OPEN
VALID
DATA
D~ ~: 7//;//$/II/IIM$$;JMi~$///$m
"RAS-ONlY"REFRESH CYCLE
CAS = V,W WRITE = DON'T CARE
NOTE:
Figure 5
RAS
ADDRESSES
DOUT
V'H
V'L
~:: W$Iffi'A~)f'" AD':,';.';" Jill$/1 JI////II$P/l/h
V OH
---------OPEN - - - - - - - - -
VOL
IV-36
PAGE MODE READ CYCLE (20)
Figure 6
tRAS----------------------------~~~
JI------+------------------------jrf
ADDRESSES
PAGE MODE WRITE CYCLE (20)
Figure 7
RAS
V IH
V il
CAS
V IH
V il
ADDRESSES
VIH
V il
iiVRii'E
VIH
V il
DIN
V IH
V il
IV-37
1'"..
_---
tRSH----~~3'-
write cycle" the data input set-up and hold times are
referenced to the negative edge of WRITE rather than CAS.
OPERATION
The 14 address bits required to decode 1 of the 16,384 cell
locations within the MK4516 are multiplexed onto the 7
address inputs and latched into the on-chip address latches
by externally applying two negative going TTL-level clocks.
The first clock, Row Address Strobe (RAS), latches the 7 row
addresses into the chip. The high-to-Iow transition of the
second clock, Column Address Strobe (CAS), subsequently
latches the 7 column addresses into the chip. Each ofthese
signals, RAS and CAS, triggers a sequence of events which
are controlled by different delayed internal clocks. The two
clock chains are linked together logically in such a way that
the address multiplexing operation is done outside of the
critical timing path for read data access. The later events in
the CAS clock sequence are inhibited until the occurrence
of a delayed signal derived from the RAS clock chain. This
"gated CAS" feature allows the CAS clock to be externally
activated as soon as the Row Address Hold specification
(t RAH ) has been satisfied and the address inputs have been
changed from Row address to Column address information.
The "gated CAS" feature permits CAS to be activated at any
time after tRAH and it will have no effect on the worst case
data access time (t RAC ) up to the point in time when the
delayed row clock no longer inhibits the remaining
sequence of column clocks. Two timing endpoints result
from the internal gating of CAS which are called tRco (min)
an~CO (max). No data storage or reading errors will result
if CAS is applied to the MK4516 at a point in time beyond
the tRCO (max) limit. However, access time will then be
determined exclusively by the access time from CAS (tcAcl
rather than from RAS (t RAC ). and RAS access time will be
lengthened by the amount that tRCO exceeds the tRCO (max)
limit.
Data Input/Output
Data to be written into a selected cell is latched into an
on-chip register by a combination of WRITE and CAS while
RAS is active. The latter of WRITE or CAS to make its
negative transition is the strobe forthe Data In (DIN) register.
This permits several options in the write cycle timing. In a
write cycle, if the WRITE input is brought low (active) prior to
CAS being brought low (active), the DIN is strobed by CAS,
and the Input Data set-up and hold times are referenced to
CAS. Ifthe input data is not available at CAS time (late write)
or if it is desired that the cycle be a read-write or readmodify-write cycle the WRITE signal should be delayed until
after CAS has made its negative transition. In this "delayed
Data is retrieved from the memory in a read cycle by
maintaining WRITE in the inactive or high state throughout
the portion of the memory cycle in which both the RAS and
CAS are low (active). Data read from the selected cell is
available at the output port within the specified access time.
The output data is the same polarity (not inverted) as the
input data.
Data Output Control
The normal condition of the Data Output (D OUT) of the
MK4516 is the high impedance (open-circuit) state;
anytime CAS is high (inactive) the DOUT pin will be floating.
Once the output data port has gone active, it will remain
valid until CAS is taken to the precharge (inactive high)
state.
Refresh
Refresh of the dynamic cell matrix is accomplished by
performing a memory cycle at all 128 combinations of the
seven row address bits within each 2 ms interval. Although
any normal memory cycle will perform the required
refreshing, this function is most easily accomplished with
"RAS-only" cycles.
Page Mode Operation *
The Page Mode feature of the MK4516 allows for
successive memory operations at multiple column locations
within the same row address. This is done by strobing the
row address into the chip and maintaining the RAS signal
low (active) throughout all successive memory cycles in
which the row address is common. The first access within a
page mode operation will be available at tRAC or t CAC time,
whichever is the limiting parameter. However, all
successive accesses within the page mode operation will be
available at t CAC time (referenced to CAS). With the
MK4516, this results in as much as a 55% improvement in
access times! Effective memory cycle times are also
reduced when using page mode.
The page mode boundary of a single MK4516 is limited to
the 128 column locations determined by all combinations of
the seven column address bits. Operations within the page
boundary need not be sequentially addressed and any
combination of read-write and read-modify-write cycle are
permitted within the page mode operation.
'" see footnote 20
IV-38
MK4516 FUNCTIONAL BLOCK DIAGRAM
II
IV-39
IV-40
MOSTEI(.
131,072 x 1-BIT DYNAMIC RAM
MK4528(D)-15/20/25
o Read, Write, Read-Write, Read-Modify-Write and
Page-Mode capability
FEATURES
o
Utilizes two standard MK4564 devices in an 18-pin
package configuration
o
o
Single +5V (± 10%) supply operation
On chip substrate bias generator for optimum
performance
o
Active power 320mW (Single MK4564 active)
Standby power 44mW
o
150ns access time, 260ns cycle time (MK4564-15)
200ns access time, 345ns cycle time (MK4564-20)
250ns access time, 425ns cycle time (MK4564-25)
o
o
Common I/O capability using "early write"
Separate RAS,
o
All inputs TTL compatible, low capacitance, and are
protected against static charge
o
Scaled POLY 5 technology
o
Pin compatible with the MK4332 (32K RAM)
o
128 refresh cycles (2 msec) for each MK4564 device
in the dual density configuration (address A7 is not
used for refresh).
o
Extended DOUT hold using CAS control (Hidden
Refresh).
CAS Clocks
DESCRIPTION
The MK4528 sets a new milestone in the state ofthe art
of package technology to give you dual density now
before the next generation of MOS RAMs are available.
This device is made up of two 64K (MK4564) 5 volt only
RAMs and it is organized as 131 ,072 words by 1 bit. The
upper 16 pins are identical to the industry standard 64K
Dual-In Line Package, allowing either device to be
installed in the 18 pin position.
The MK4528's high performance features and wide
operating margins, both internally and to the system user,
are achieved by state-of-the-art circuit design techniques as
well as utilization of Mostek's "Scaled POLY 5" process
technology.
PIN CONNECTIONS
DEVICE PROFILE
N/C
1
18 Vss
DIN
2
17 ~
16 DoUT
15 As
14 A3
WRITE 3
RAS1
4
Aa 5
A2
6
13 A4
A,
7
Vee
8
12 As
11 ~
10 ~
J!iAfi 9
PIN FUNCTION
ArA
Address Inputs
RAS
Row Address Strobe
CAS
Column Address Strobe WRITE
DIN
Data In
Vee
Power(+5V)
Dour
Data Out
N/C
No Connections
Vss
GND
ReadlWrite Input
Also Available in MIL-STD-883 Class 8 (MK8)
IV-41
---
- - - - - - - - - - - - - - - . _ . _ - _.....
_-._----- - - -
--------------
•
ABSOLUTE MAXIMUM RATINGS*
Voltage on V cc supply relative to V 55 .......................................................... -1 .0 V to +7.0 V
Operating Temperature, TA (Ambient) ............................................................. O°C.to + 70C
Storage Temperature (Ceramic) .................•............................................ -65°C to +150°C
Power Dissipation ...................................•.............................................. 1 Watt
Short Circuit Output Current ......................................................................... 50 mA
*Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional
operation ofthe device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
(O°C ::; TA ::; 70°C)
SYM
PARAMETER
MIN
TYP
MAX
UNITS
NOTES
Vcc
Supply Voltage
4.5
5.0
5.5
V
1
V 1H
Input High (Logic 1) Voltage,
All Inputs
2.4
-
V cc +1
V
1
V 1L
Input Low (Logic 0)
Voltage, All Inputs
-2.0
-
.8
V
1.18
MIN
MAX
UNITS
NOTES
58
mA
2
8
mA
DC ELECTRICAL CHARACTERISTICS
(O°C ::; TA ::; 70°C) (V cc 5.0 V ± 10%)
=
SYM
PARAMETER
ICCl
OPERATING CURRENT
Average power supply operating current
(RAS, CAS cycling; t RC = t RC min.)
ICC2
STANDBY CURRENT
Power suply standby current (RAS
DOUT = High Ipedance)
ICC3
RAS ONLY REFRESH CURRENT
Average power supply current, refresh mode
(RAS cycling, CAS =V IH ; t RC = t RC min.)
49
mA
2
ICC4
PAGE MODE CURRENT
Averilfie power supply current, pilge mode
operiltlon
(RAS = V IL, t RA5 =t RA5 milX., CAS cycling;
tpc =tpc min.)
39
mA
2
il(L)
INPUT LEAKAGE
Input leakage current, any input
(OV ::; VIN ::; V cc), all other pins not under
test =0 volts
-20
20
p.A.
IO(L)
OUTPUT LEAKAGE
Output leakage current (DOUT is disabled,
OV ::; V OUT::; V cd
-20
20
p.A.
0.4
V
V
V OH
VOL
=V IH ,
OUTPUT LEVELS
Output High (Logic 1) voltage (lOUT = -5 mAl
Output Low (Logic 0) voltage (lOUT =4.2 mAl
IV-42
2.4
NOTES:
specified tRCD (max) limit then access time is controlled exclusively by
tCAC·
1. All voltages referenced to VSS.
2. ICC is dependent on output loading and cycle rates. Specified values are
obtained with the output open. Only one MK4564 is active.
3. An initial pause of 500 ,",5 is required after power-up followed by any 8 RAS
cycles before proper device operation is achieved. Note that RAS may be
cycled during the initial pause.
4. AC characteristics assume tT = 5 ns.
5. VIH min. and VIL max. are reference levels for measuring timing of input
signals. Transition times are measured between VIH and VIL'
6. The minimum specifications are used only to indicate cycle time at which
proper operation over the full temperature range (OOe ::; TA ::; 70°C) is
assured.
12. Either tRRH or tRCH must be satisfied for a read cycle.
13. These parameters are referenced to CAS leading edge in early write cycles
and to WRITE leading edge in delayed write or read-modify~write cycles.
14. twcs, tewD' and tRWD are restrictive operating parameters in
READ/WRITE and READ/MODIFY/WRITE cycles only. II twcs
~
twcs
(min) the cycle is an EARLY WRITE cycle and the data output will remain
open circuit throughout the entire cycle.lftCWD 2:tCWD (min) and tRWD 2:
tRWD (min) the cycle is a READ/WRITE and the data output will contain data
read from the selected cell. If neither of the above conditions are met the
condition of the data out (at access time and until CAS goes back to VIH) is
indeterminate.
15. In addition to meeting the transition rate specification, all input signals must
transmit between VIH and VIL (or between VIL and VIH) in a monotonic
manner.
16. Effective capacitance calculated from the equation C::: I Qlwith 1'::. V::: 3 volts
and power supply at nominal level.
t:::.V
7. Load = 2 TIL loads and 50 pF.
8. Assumes that tReD ::; tRCD (max). If tRCD is greater than the maximum
recommended value shown in this table, tRAC will increase by the amount
that tRCD exceeds the value shown.
9. Assumes that tRCD ~ tRCD (max).
10. tOFF max defines the time at which the output achieves the open circuit
condition and is not referenced to VOH or VOL.
11. Operation within the tRCD (max) limit insures that tRAC (max) can be met.
tRCD (max) is specified as a reference point only; if tRCD is greater than the
'7. CAS = VIH to disable DOUT·
18. Includes the DC level and all instantaneous Signal excurSions.
, 9.iiiiliii'E = don't care. Dataoutdependsonthestateol~.II~ =VIH, data
output is high impedance. If CAS::: VIL, the data output will contain data
from the last valid read cycle.
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(3,4,5,15) (O°C g A 70°C), V cc 5,OV ± 10%
:s:
SYMBOL
STD
ALT
=
PARAMETER
MK4528-15
MIN
MAX
MK4528-20
MIN
MAX
MK4528-25
MIN
MAX
UNITS
NOTES
tRELREL
t RC
Random read or write cycle time
260
345
425
ns
6,7
tRELREL
(RMW)
tRMW
Read modify write cycle time
310
405
490
ns
6,7
tRELREL
(PC)
tpc
Page mode cycle time
155
200
240
ns
6,7
tRELQV
tRAC
Access time from RAS
150
200
250
ns
7,8
tCELQV
t CAC
Access time from CAS
85
115
145
ns
7,9
tCEHQZ
tOFF
Output buffer turn-off delay
a
40
a
50
0
60
ns
10
tr
tr
Transition time (rise and fall)
3
50
3
50
3
50
ns
5,15
tREHREL
tRP
RAS precharge time
100
tRELREH
t RAS
R,/\S pulse width
150
tCELREH
t RSH
RAS hold time
85
115
145
ns
tRELCEH
tCSH
CAS hold time
15O
200
250
ns
tCELCEH
tCAS
CAS pulse width
85
10,000
115
10,000
145
10,000
ns
tRELCEL
tRCD
RAS to CAS delay time
30
65
35
85
45
105
ns
11
tREHWX
tRRH
Read command hold time
referenced to RAS
20
12
Row address set-up time
a
tAvREL
t ASR
165
135
10,000
!
200
1 10,000
250
ns
10,000
ns
25
30
ns
0
0
ns
25
30
ns
tRELAX
tRAH
Row address hold time
20
tAVCEL
t Asc
Column address set-up time
0
0
a
ns
tCELAX
tCAH
Column address hold time
30
40
50
ns
Column address hold time
referenced to RAS
100
130
160
ns
tRELA(C)X tAR
I
IV-43
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (Continued)
(3.4,5,15) (O°C ::; TA::; 70°C), V cc = 5.0V
± 10%
SYMBOL
MK4528-15
MK4528-20
MK4528-25
MIN
MIN
MIN
MAX UNITS NOTES
STD
ALT
PARAMETER
tWHcEL
t RCS
Read command set-up time
0
0
0
ns
tCEHWX
t RCH
Read command hold time
referenced to CAS
0
0
0
ns
MAX
MAX
tCELWX
tWCH
Write command hold time
45
55
70
ns
tRELWX
t WCR
Write command hold time
referenced to RAS
115
150
185
ns
12
t WLWH
twp
Write command pulse width
35
45
55
ns
tWLREH
t RWL
Write command to RAS lead time
45
55
65
ns
tWLCEH
tCWL
Write command to CAS lead time
45
55
65
ns
t OVCEL
tos
Data-in set-up time
0
0
0
ns
13
tCELDX
tOH
Data-in hold time
45
55
70
ns
13
tRELDX
tOHR
Data-in hold time
referenced to RAS
115
150
190
ns
CAS precharge time
(for page-mode cycle only)
60
75
85
ns
tCEHCEL
(PC)
tcp
t RVRV
tREF
Refresh Period
tWLCEL
twcs
WRITE command set-up time
-10
-10
-10
ns
14
tCELWL
t cwo
CAS to WRITE delay
55
80
100
ns
14
tRELWL
t RWO
RAS to WRITE delay
120
165
205
ns
14
tCEHCEL
t CPN
CAS precharge time
30
35
45
ns
2
2
ms
2
AC ELECTRICAL CHARACTERISTICS
(O°C ::; TA::; 70°C) (V cc = 5.0V
± 10%)
SYM
PARAMETER
CI1
Input Capacitance (Ao
CI2
MAX UNITS NOTES
- A 7 ), DIN
10
pF
16
Input Capacitance RAS, CAS
10
pF
16
C13
Input Capacitance WRITE
20
pF
16
Co
Output Capacitance (D OUT )
14
pF
16,17
IV-44
READ CYCLE
t RAS
RAS
CAS
V ,H _
V 1l -
V 1H _
V'l-
V1H _
ADDRESSES
V'L-
V ,H _
WRITE
V'L-
i.--t
II
CAC
t RAS
DOUT
V OH _
V OL _
tOFF
VALID
DATA
OPEN
WRITE CYCLE (EARLY WRITE)
RAS
CAS
V1H _
V 1L
-
V'HV1L -
V1H _
ADDRESSES
V IL -
V 1H -
WRITE
D'N
V1L -
V1H _
VIL -
DOUT
VOH -
OPEN
V OL-
IV-45
READ-WRITE/READ-MODIFY-WRITE CYCLE
~----------------------------_IRMW------------------------~
RAS
t ASR
V,H _
ADDRESSES V Il -
WRITE
Jc--:::=.,..-~
V ,H _
Vil -
VOH VOL _
'"'"""IF"""'""'u
------+---------------------OPE
V IH _
""'""'77:"77.'7777777777>'77:"77.777777'""'"''77:"77.'177777'"'''''"' ~...,..,.~.,.-"'- ,r?7;'177777777,"",",'7T.'177=
Vil -
a.t.~~='"a.t.~~='"a.t.=~~='"'"==~ ~""::::::":":::'-JI "'~='"a.t.=~~=
"RAS-ONLY" REFRESH CYCLE
I RC
t RAS
-
I-IRAH
t ASR
ADDRESSES
IV-46
4
I
~
I RP
I
PAGE MODE READ CYCLE
~------------------------------tRAS----------------------------~~
V'l -
CAS
II
ADDRESSES V'H
VOl
DOUT
JJ-----------------------~~~_
PAGE MODE WRITE CYCLE
~-----------------------------tRAS------------------------------~
CAS
ADDRESSES
WRITE
IV-47
OPERATION
The MK4528 consists of two 64K(MK4564) dynamic RAMs
connected by a substrate in a 131,072 x 1 configuration.The
eight address bits required to decode 1 of the 65,536 cell
locations within each MK4564 are multiplexed onto the
eight address inputs and latched into the on-chip address
latches by externally applying two negative going TTL-level
clocks. The first clock, Row Address Strobe (RAS), latches
the eight row addresses into the cip. The high-to-Iow
transition of the second clock, Column Address Strobe
(CAS), subsequently latches the eight column addresses
into the chip. Each of these signals, RAS and CAS, triggers a
sequence of events which are controlled by different
delayed internal clocks. The two clock chains are linked
together logically in such a way that the address
multiplexing operation is done outside ofthe critical timing
path for read data access. The later events in the CAS clock
sequence are inhibited until the occurrence of a delayed
signal derived from the RAS clock chain. This "gated CAS"
feature allows the CAS clock to be externally activated as
soon as the Row Address Hold specification (t RAH ) has been
satisfied and the address inputs have been changed from
Row address to Column address information.
The "gated CAS" feature permits CAS to be activated at any
time after tRAH and it will have no effect on the worst case
data access time (t RAC ) up to the point in time when the
delayed row clock no longer inhibits the remaining
sequence of column clocks. Two timing endpoints result
from the internal gating of CAS which are called tRCO (min)
an2.!aco (max). No data storage or reading errors will result
if CAS is applied to the MK4564 at a point in time beyond
the tRCO (max) limit. However, access time will then be
determined exclusively by the access time from CAS (tCAC )
rather than from RAS (t RAC ). and RAS access time will be
lengthened by the amount that tRco exceeds the tRCO (max)
limit.
DATA INPUT/OUTPUT
Data to be written into a selected cell is latched into an
on-chip register by a combination of WRITE and CAS while
RAS is active. The latter of WRITE or CAS to make its
negative transition is the strobe forthe Data In (DIN) register.
This permits several options in the write cycle timing. In a
write cycle, if the WRITE input is brought low (active) prior to
CAS being brought low (active), the DIN is strobed by CAS,
and the Input Data set-up and hold times are referenced to
CAS. If the input data is not available at CAStime (late write)
or if it is desired that the cycle be a read-write or readmodify-write cycle the WRITE signal should be delayed until
after CAS has made its negative transition. In this "delayed
write cycle" the data input set-up and hold times are
referenced to the negative edge of WRITE rather than CAS.
Data is retrieved from the memory in a read cycle by
maintaining WRITE in the inactive or high state throughout
the portion of the memory cycle in which both the RAS and
CAS are low (active). Data read from the selected cell is
available at the output port within the specified access time.
The output data is the same polarity (not inverted) as the
input data.
DATA OUTPUT CONTROL
The normal condition of the Data Output (D OUT) of the
MK4564 is the high impedance (open-circuit) state;
anytime CAS is high (inactive) the DOUT pin will be floating.
Once the output data port has gone active, it will remain
valid until CAS is taken to the precharge (inactive high)
state.
PAGE MODE OPERATION
The Page Mode feature of the MK4564 allows for
successive memory operations at multiple column locations
within the same row address. This is done by strobing the
row address into the chip and maintaining the RAS Signal
low (active) throughout all successive memory cycles in
which the row address is common. The first access within a
page mode operation will be available at tRAC or t CAC time,
whichever is the limiting parameter. However, all
successive accesses within the page mode operation will be
available at t CAC time (referenced to CAS'). With the
MK4564 this results in approximately a 57% improvement
in access times. Effective memory cycle times are also
reduced when using page mode.
The page mode boundary of a single MK4564 is limited to
the 256 column locations determined by all combinations of
the eight column address bits. Operations within the page
boundary need not be sequentially addressed and any
combination of read, write, and read-modify-write cycles is
permitted within the page mode operation.
REFRESH
Refresh of the dynamic cell matrix is accomplished by
performing a memory cycle at each of the 128 row
addresses within each 2 ms interval. Although any normal
memory cycle will perform the required refreshing, this
function is most easily accomplished with "RAS-only"
cycles.
The RAS-only refresh cycle requires that a 7 bit refresh
address (AO-A6) be valid at the device address inputs when
RAS goes low (active). The state of the output data port
during a RAS-only refresh is controlled by CAS. If CAS is
high (inactive) during the entire time that RAS is asserted,
the output will remain in the high impedance state. If CAS is
low (active) the entire time the RAS is asserted, the output
port will remain in the same state that it was prior to the
issuance of the RAS signal. If CAS makes a low-to-high
transition during the RAS-only refresh cycle, the output
data buffer will assume the high impedance state. However,
the CAS may not make a high to low transition during the
R'AS-only refresh cycle since the device interprets this as a
normal RAS/CAS(read or write) type cycle.
IV-4S
HIDDEN REFRESH
A ~-only refresh cycle may take place while maintaining
valid output data by extending the CAS active time from a
previous memory read cycle. This feature is referred to as a
hidden refresh. (See figure below.)
HIDDEN REFRESH CYCLE (SEE NOTE 19)
MEMORY C Y j = = {
\~
n
REFRESHC
____________
~r-
AODR . . . . .
~fl(J/IBT/I/(j(1///'{
WiiiiE
'llllllI
VIIVT//JI}///IIJ!ll
------« ' - - - - - - - - '
VAUD DATA
)-
IV-49
II
IV-50
32,768x1-BIT DYNAMIC RAM
M K4332(D)-3
FEATURES
D Utilizes two industry standard MK 4116 devices in
an 18-pin package configuration
o
o
200ns access time, 375ns cycle (MK 4116-3)
Separate RAS, CAS Clocks
± 10% tolerance on all power supplies (+12V,±5V)
D
Low power: 482mW active, 40mW standby (max)
D
Output data controlled by CAS and unlatched at
end of cycle to allow two dimensional chip selection and extended page boundary
DESCRIPTION
D
The MK 4332 is a new generation MOS dynamic
random access memory circuit organized as 32,768
words by 1 bit. As a state-of-the-art MOS memory
device, the MK4332
(32K RAM) incorporates
advanced circuit techniques designed to provide
wide operating margins, both internally and to the
system user
The technology used to fabricate the MK 4332 is
MOSTEK's double-poly, N-channel silicon gate,
POL Y II S process. This process, coupled with the
use of a single transistor dynamic storage cell, provides the maximum possible circuit density and
reliability, while maintaining high performance
capability. The use of dynamiC circuitry throughout, including sense amplifiers, assures that power
FUNCTIONAL DIAGRAM
D
Common I/O capability using "early write"
operation
D
Read-Modify-Write, RAS-only refresh, and Pagemode capability
All inputs TTL compatible,low capacitance, and
protected against static charge
D 128 refresh cycles for each MK 4116 device in the
dual density configuration
D
D
Pin compatible to MK 4116 and MK 4164
dissipation is minimized without any sacrifice in
speed or operating margin. These factors combine
to make the MK 4332 a truly superior RAM product.
II/Iultiplexed address inputs (a feature pioneered by
MOSTEK for its 4K RAMS) permits the MK 4332
to be packaged in a standard 18-pin DIP. This
standard package configuration, is compatible with
widely available automated rnsting and insertion
equipment, and it provides the highest possible system bit densities and simplifies system upgrade
from 16K to 64K RAMs for new generation applications. Non-critical clock timing requirements allow
use of the mUltiplexing technique while maintaining high performance.
PIN CONNECTIONS
18 Vss
VBa
RAs1
I
-
CAS 1
I
WE
I
4,16
AD-A6
I
I
-
I
I
I
17 CAS'
WRITE
3
16 00UT
RAS1
4
15
A.
AD
5
14
A3
A2
6
13
A.
A,
7
12 A5
VOO
8
11 Vee
RAS2
9
10
I
~
I
'---
4116
RAS 2
I
CAs2
I
I
2
.IDoUT
DIN
I
I
I
I
I
I
DIN
CA. 2
PIN NAMES
~6
ADDRESS INPUTS
COLUMN ADDRESS STROBE
DIN
DATA IN
DATA OUT
CAS
~T
WRTfE
VBB
Vee
L _ _ _ _ _ _ -'
VOO
Vss
IV-51
ROW ADDRESS STROBE
READJINRITE INPUT
POWER (-5V)
POWER (+5V)
POWER (+12V)
GROUND
II
ABSOLUTE MAXIMUM RATlNGS*
Voltage on any pin relative t~ Vas.: ................... -O.SV to +20V
Voltage on VDD, VCC supplies relative to VSS .......... -1.0V to +1S.0V
VSB-VSS (VDD-VSS>OV) .................................. OV
Operating temperature, T A (Ambient) ................... O°C to + 70ce
Storage temperature (Ambient) ... , .................. -6So C to + 1S0°C
Short circuit output current ................................. SOmA
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Watt
·Stresses greater than those listed under
"Absolute Maximum Ratings" may cause
permanent damage to the device. This is a
stress rating only and functional operatior
of the device at these o.r any other condi
tlonl above those indicated In the opera-
tional sections of this specification is not
implied. Exposure to absolute maximum
rating conditions for extended periods may
affect reliability.
RECOIVIMENDED DC OPERATING CONDITIONS6
(O°C';; T A';; 70°C)
NOTES
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
Supply Voltage
VOO
VCC
VSS
VBB
10.8
4.5
0
-4.5
12.0
5.0
0
-5.0
13.2
5.5
0
-5.7
Volts
Volts
Volts
Volts
2
2,3
2
2
RAil, A, WR IT E
Input~
VrHC
2.4
-
7.0
Volts
2
Input High (Logic 1) Voltage,
all inputs except RAS, CAS
WRITE
V,H
2.2
-
7.0
Volts
2
Input Low (Logic 0) Voltage,
all inputs
V,L
-1.0
-
.8
Volts
2
(LOgic l) Voltage,
DC ELECTRICAL CHARACTERISTICS
(VDD = 12.0V ± 10%; VCC == S.OV ±10%;-S.7V';; VSS ';;-4.5V; VSS
(O"C.;; TA';; 70b e)
PARAMETER
SYMBOL
OPERATING CURRENT
Average power supply operating current
(RAS, CAS cycling; tRC =tRC Min)
1001
ICCl
IBBl
STANOBY CURRENT
Power supply standby current (liAS = V, HC,
00UT = High Impedance)
1002
ICC2
'BB2
REFRESH CURRENT
Average power supply current, refresh mode
(iViS cycling, CAS = V,HC; tRC ='tRC Min)
1003
ICC3
IBB3
PAGE MOOE CURRENT
Average power supply current, page·mode
operation (i'iAS =VIL,~ cycling;
tpc =tPc Min)
1004
ICC4
IBB4
INPUT LEAKAGE
Input leakage current, any input
(VBB = -5V, OV,.;;, V,N";;' +7.0V,all other
pins not under test = 0 volts)
II(L)
OUTPUT LEAKAGE
Output leakage current (OOUT is disabled,
OV";;' VOUT";;' +5.5V)
MIN
= OV)
MAX
UNITS
36.5
rnA
300
IJ,A
-20
3.0
20
200
mA
IJ,A
IJ,A
-20
26.5
20
300
mA
IJ,A
IJ,A
28.5
mA
300
IJ,A
-20
20
IJ,A
10(L)
-20
20
IJ,A
OUTPUT LEVELS
Output high (Logic 1) voltage (lOUT = -5mA)
VOH
2.4
Output low (Logic 0) voltage (lOUT = 4.2 mAl
VOL
4,19
5
19
4,19
19
4,19
5
19
Volts
0.4
NOTES
3
Volts
NOTES:
1.
T A is specified here for operation at frequencies to tRC ~tRC
(mm). Operation at higher cycle rates with reduced ambient
temperatures and higher power dissipation Is permissible, how"
ever, provided AC operating parameters are met. See figure 1
for derating curve.
2.
All voltages referenced to VSS'
.3
Output voltage will swing from VSS to Vec when activated with
no current loading. For purposes of maintaining data in standby
mode,Ycc may be reduced to VSS without affecting refrlsh
operatIons or data retention. However, the VOH (min) specifica"
tion is not guaranteed in this mode.
4.
~q~r1 i~~9r,;,rt~~~~g~rd:~~I~dr~~s~YCle
5.
~lCfi1g~nl~VIJrca~t~e~~~di~~~~n~~ie~\~~~~i;~'a ~~ir~~:~~~~;
rate. See figures 2,3, and
(135 H tYp) to data out. At all other times ICC consists of
leakage currents on Iy.
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (6,7,8)
(OC",TA'" 70°C)1(VOO = 12.0V±10%;VCC= 5.0V ±10%, VSS = OV, -5.7V<:' VBB <:. -4.5V)
MK4332
PARAMETER
Random read or write cycle time
SYMBOL
MIN MAX
tRC
375
Read·write cycle time
tRWC
tRMW'
375
ns
9
Read modify write cycle time
Page mode cycle time
405
225
ns
ns
- 9
tpc
Access time from
RAS
tRAC
UNITS
ns
NOTES
9
9
200
ns
10,12
Access time from CAS
tCAC
135
ns
11,12
Output buffer turn-off delay
tOFF
0
50
ns
13
Transition time (rise and fall)
tT
3
50
ns
8
RAS precharge time
tRP
120
RAS pulse width
ns
tRAS
200 10,000
ns
RAS hold time
tRSH
135
ns
CAS hold time
tCSH
tCAS
200
135 10,000
ns
CAS pulse width
RAS to CAS delay time
tRCD
25
ns
CAS to RAS precharge
tCRP
-20
ns
Row Address set-up time
tASR
tRAH
0
25
ns
Row Address hold time
Column Address set-up time
tASC
-10
ns
Column Address hold time
tCAH
55
ns
Column Address hold time referenced to RAS
tAR
120
ns
Read command set-up time
tRCS
0
ns
Read command hold time
tRCH
0
ns
twCH
55
ns
ns
ns
time
Write command hold time
Write command hold time referenced to
RAS
65
ns
14
ns
twCR
120
Write command pulse width
twP
55
Write command to RAS lead time
tRWL
70
ns
Write command to CAS lead time
tCWL
70
ns
Data-in set-up time
tDS
0
ns
15
Data-in hold time
tDH
55
ns
15
Data-in hold time referenced to AAS
tDHR
120
ns
CAS precharge time (for page-mode cycle only)
tcp
80
Refresh period
tREF
ns
2
ms
twcs
-20
ns
16
CAS to W'Rl'rr delay
tCWD
80
ns
RAS to WR ITE delay
tRWD
145
ns
16
16
WRITE command set-up time
NOTES (Contlnued(
6.
Several cycles are required after power·up before proper device operation
8 cycles which perform refresh are adequate for thiS purpose,
achieved. Any
14.
7.
AC measurements assume IT
8.
VIHC (min) or VIH (min) and VI L (max) are reference levels for measuring timing of m·
put signals. Also, transition times are measured between VIHC or VIH and VIL.
The specifications for tRC (mm) tRMW {mini and tAwe (min) are use9 only to indicoate
cycle time at which proper operation over the full temperature range (0 C ~ T A ~ 70 C)
IS assured.
16.
9.
'=
IS
5ns.
10.
Assumes that tRCD ,,;:;. tRCD (maxI. If tRCD is greater than the maxImum recommended
value shown m this table, tRAC will increase by the amount that tRCD exceeds the value
shown.
11.
Assumes that tRCD )otRCO (maxI.
Measured wIth a load equivalent to 2 TTL loads and 10OpF.
tOFF (maxi defmes the tIme at whIch the output athieves the open CIrcuit condition and
is not referenced to output voltage levels.
12.
'3.
15.
17.
18.
19.
IV-53
Operation wlthm the tRCD (maxI limIt insures that tRAC (max) can be met. tRCD (max)
IS specified as a reference pomt only; if tRCD IS greater than the specified tRCD (max)
limit. then access time IS controlled exclusively by tCAC,
These parameters are referenced to CAS leading edge m early wrJte cycles and to WR ITE
leading edge in delayed write or read-modify-write cycles.
twes. tewD and tRWD are restnctlve operating parameters in read wflte and read mod·
ify write cycles only. If twcs~twcs (minI, the cycle Isan early write ~ycle ami the data
out pin will remain open cirCUit (high Impedance) throughout the entire cycle; If tCWD
~ tewD (min) and tRWD ~tRWO (min), the cycle is a read-write cycle and the data out
Will contain data read from the selected cell; If neither of the above sets of conditions IS
satIsfied the condition of the data out (at access time) is Indeterminate.
Effective capacitance calculated from the equation C = l!J.t with!J. V ~ 3 volts and power
supplies at nom mal levels.
6. V
CAs ~ VI He to disable DOUT·
One 16K RAM is 8ctive while the other Is in standby mode.
AC ELECTRICAL CHARACTERISTICS
(ODC ~TA ~ 70 DC) (VDD = 12.0V ± 10%; VSS = OV; -5.7V ~ VBB ~ -4.5V)
PARAMETER
SYMBOL
TYP
MAX
UNITS
NOTES
Cil
8
10
pF
Input Capacitance RAS, CAS,
CI2
8
10
pF
17
Output Capacitance (DOUT)
Co
10
14
pF
17, 18
Input Capacitance WRT"i't
CI3
16
20
pF
17
Input Capacitance (AO-A6), DIN
17
AC Characteristics and Timing Diagrams of MK4116-3.
CYCLE TIME tRC (ns)
1000
315
500
300
49'
59mA
- -
1
CYCLE TIME tRC (ns)
".
1000
E 70
500
40
300
250
~
~
~'¥
30mA
U
II- 60
~
~:'I
Z
UJ
iii
_
::IE
'\:
20mA
1.0
2.0
4.0
3.0
Fig. 1 Maximum ambient temperature versus cycle rate for extended
frequency operation. T A (max) for operation at cycling rates greater
than 2.66 MHz (tCYC<375ns) is determined by T A (max)o C = 709.0 x (cycle rate MHz -2.66) for -3.
500
400
300
SOmA
o
o
--
A...,q.
,
,
LO
30
20
Fig. 2 Maximum 1001 versus cycle rate for device operation at
extended frequencies. 1001 (max) curve is defined by the equation:
= 10 + 9.4 x cycle
250
rate [MHz] fa!
500
400
300
50mA
.
0::
0::
:::l
--
--
.-
i
-
I-
~\
>-'
~
>foe,.
::>
,QJ'"
20mA
:f-\~
~'>
0
~o
X
"
:Ii
lOrnA
o
40mA
Z
UJ
30mA
Q.
Q.
.,
250
40mA
U
en
-3
CYCLE TIME t PC (ns)
1000
...
..
VI
20mA
0
X
"
-
~
2.0
30
"
...
4.0
o
CYCLE RATE (MHz)- 103/t "C (ns)
Fig. 3 Maximum 1003 versus cycle rate for device operation at
extended frequencies. 1003 (max) curve is defined by the equation:
1003(max) mA = 10 + 6.5 x cycle rate [MHz] for -3
lOrnA
.
~
,QQ' ,.~-;.
oS'
o
10
20
30
40
CYCLE RATE (MHz)' 10 3/t PC (ns)
Fig. 4 Maximum 1004 versus cycle rate for device operation in page
mode.
1004
(max) curve
is defined by the equation:
1004 (max) mA = 10 + 3.75 x cycle rate [MHz] for -3
IV-54
READ CYCLE
~------------------------- t RC - - - - - - - - - - - - - - - - - - - - - - - ;
~---------- ------------- t RAS - - - - - - - - - - ;
RAS
~ CSHI------------;----------------I
14---------;---
~_ _ _ tRCD ___....
-----:--:--------.d---"'\
CAS
VIHC VIL
tRSH - - - - - - - - ; -. .
!.--------'--- t CAS -------I-t
-
VIH_
II
ADDRESSES V IL-
WRITE
V IHC-
V IL
I---
--'-'~t..L.L.I...L..I._'+''''''-'u.....,
t CAC - - - - - i..
t RAC ~------------~
V OH -
DOUT
VOL -
-------------------------
tOFF
VALID
DATA
OPEN
WRITE CYCLE (EARLY WRITE)
t Rc
t RAS
RAS
V IHC VIL
~
V IHC _
CAS
VIL
i
tAR
-
-j
t RSH
'CSH
-tCAS
-
V IH-
ADDRESSES
VIL -
I-- t
WRITE
WCH
_lwp
I
VIL -
I-- IOH
..I
V IH _
VIL-L.l..L.l..LLLL~~~~~J
VOH-~
DOUT
, ____~______~
~~~~~L.l..LLLLLL~~~~~~. . .
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ___
OPEN
VOL -
IV-55
READ-WRITE/READ-MODIFY-WRITE CYCLE
t-----------tRWC/ t RMW'----------t
RAS
===~I.==jE==~t~RSH~-==~---~
tCAS - -tCSH----t
----1
DOUT
"HAS-ONLY" REFRESH CYCLE
NOTE: CAS
= VIHC, WRITE =Don't Care
1 4 - - - - - - tRC--------t
VIHC----------.J
t---- t
RAS' - -
I~
ADORESSES
:'::W/B1~ t''':;,:''"-'$ff;/~#$;~-//m-----tI;;;/h
VOH -
---------OPEN-----------
IV-56
PAGE MODE READ CYCLE
RAS
CAS
ADDRESSES
V'HC_
V IL -
I RAS
----------------------------~·~1~
~==;==+=t;;;:::::::;:I------~r
------;{.j'-
ff--,I,..
V'HC_
V'L-
~::_
II
PAGE MODE WRITE CYCLE
14------------------- I RAS - - - - - - - - - - - - - - - - - - - e j
ADDRESSES
IV-57
-------------- ----------------
DESCRIPTION (continued)
System oriented features include ± 10% tolerance on
all power supplies, direct interfacing capability with
high performance logic f?mi!ies su~h as Sc:h(:>tt.ky
TTL maximum input nOise Immunity to minimize
"false triggering" of the inputs (a common cause of
soft errors) on-chip address and data registers which
eliminate the need for interface registers, and two
chip select methods. The MK 4332 also incorporates
several flexible timing/operating modes. In addition
to the usual read, write, and read-modify-write
cycles, the MK 4332 is capable ...QLdelayed write
cycles, page-mode operation and RAS-only-DUresh.
Pr~p.fr control of the clock inputs(RAS, CAS and
W I E) allows common I/O capability, two dimensional chip selection, and extended page boundaries
(when operating in page mode).
ADDRESSING
User access of a unique memory loca~ion is accomplished by multipleXing 14 address bits onto 7 address inputs and by proper control of the RAS and
CAS clocks in a manner identical to operation of the
II.1K 4116 in a memory array board. The 14 add.ress
bits required to decode 1 of the 16,384 cell locations
within each MK 4116 are multiplexed onto the 7
address inputs and latched into the on-chip address
latches by externally applying two negative going
TTL-level clocks. The first clock, the Row Address
Strobe (RAS), latches. the 7 row address bits into the
c!:!.lE:.. The second clock, the Column Address Strobe
(CAS), subsequently latches the 7 column address
bits into the chip. Each of these signals, RAS and
CAS, triggers a sequence of events which are controlled by different delayed internal .clocks. The two
clock chains are linked together logically in such a
way that the address multiplexing operation is done
outside of the critical path timing seq~e for read
data access. The later events in the CAS clock sequence are inhibited until the occurence of a delayed
sigSI derived from the RAS clock chain. This "gated
CA " feature allows the CAS clock to be externally
activated as soon as the Row Address Hold Time
specification (tRAH) has been satisfied and the address inputs have been changed from Row address to
Column address information.
Note that CAS can be activated at any time after
tRAH and it will have no effect on. th~ Vl!0rst case
data access time (tRAC) up to the pOint In time when
the delayed row clock no longer inhibits ~he. remaining sequence of colum~ clocks. .Two timing e':ldpoints result from the Internal gating of CAS which
are called tRCD (min) a~d tRCD !max~. No d?ta
storage or reading errors Will result If CA IS applied
to the MK 4332 at a point in time beyond the tRCD
(max) limit. However, access time will then be determined exclusively by the access time from CAS
(tCAC) rather thaI'! from RAS (tRAC), and access
time from RAS will be lengthened by the amount
that tRCD exceeds the tRCD (max) liltllt.
DATA INPUT/OUTPUT
Data to be written into a selected cell is latched into
an on-chip r~~er by a combination of WR IT~ and
CAS while
is active. The later of the signals
(WR ITE or CAS) to make its negative transition is the
strobe for the Data In (DIN) register. This permits
several options in the yvrite cycle timing. In a write
cycle, if the WR ITE Input IS brought low (active)
prior to cAs, the DIN is strobed by CAS and the
set-up and hold times are referenced to cAS. If the
input da.ta is not available at CAS t!me or if it is
desired that the cycle be a read-wnte cy~ the
WRITE signal will be delayed until after CAS has
made its negative -transition. In this "delayed write
cycle" the data input set-up and hold times are referenced to the negative edge of WR ITE rather than
&AS. (To illustrate this feature, DIN is referenced to
RITE in the timing diagrams depicting the readwrite and page-mode write cycles while the "early
write" cycle diagram shows DIN referenced to CAS).
Data is retrieved from the memory in a read cycle
by maintaining i.i'iTiif'fI: in the inactive or high state
throughout the portion of the memory cycle in which
CAS is active (low). Data read from the selected cell
will be available at the output within the specified
access time.
DATA OUTPUT CONTROL
The normal condition of the Data Output (DOUT)
of theMK 4332 is the high impedance (open-circuit)
state. That is to say, anytime CAS is at a hiQh level,
the DOUT pin will be floating: ~he only tl!,"e the
output will turn on and contain either a logiC 0 or
logic 1 is at access time during a read.cy'cle .. DOUT
will remain valid from access time until CAS IS taken
back to the inactive (high level) condition.
Since the outputs to both 16K devices are tied together, care must be taken with t~e timing relatio~
ships' of the two devices. Both deVices cannot be activated at the same time as a data output conflict can
occur.
If the memory cycle in progress is a read, read-modify
write or a delayed write cycle, then the data out~ut
will go from the high imp~dancf! state t
~C '" 500ns
.tRC = 500ns
,.u
t
20
iil
~C = 750n5
tRC = 750n5
~ 15
10
14
10
TYPICAL ACCESS TIME (NORMALIZED) vs. Vaa
II
TYPICAL 1002 vsJUNCTION TEMPERATURE
TYPICAL 1002 vs VOO
1.4
110
20
50
80
TJ. JUNCTION TEMPERATURE ("C)
Voo SUPPLY VOLTAGE (VOLTS)
1.2
~
30
a;
13
12
1
f-
l----
1. 4
VOO =13.2V
TJ""50"C
TJ "'50"C
2
11.1
ill"
~'0r-----~----~------~-----1
:'
---
~
~0.9
------
: 0.8 r-----+------j------+-----1
f-
0.7 L4~.0;;---;4';:.5--"'-5;C.0~--5~.5.--......,-6t..0
0.4
10
Vaa SUPPLY VOLTAGE (VOLTS)
0
----
8
6
t--
r--
O. 4
14
11
12
13
VOO SUPPLY VOLTAGE (VOLTS)
--
-10
20
50
80
TJ. JUNCTION TEMPERATURE ("c)
110
TYPICAL 1003 VS. VOD
1.2
~
~
TYPICAL ACCESS TIME (NORMALIZED) vs VCC
TYPICAL 1003 liS JUNCTION TEMPERATURE
18
TJ"'SO't
tl
~ 1.0 r-----+-----+------+-------j
II
~
~
u
0.81---____+ ____-+______+-____.~
0.7 ..
4."0----1
4 .""5----;5J,.0,-----,5!,.5,----"'6~.0
v-----
6
--I-'
2
10
8 10
12
11
10
14
13
Veo SUPPLY VOLTAGE (VOLTS)
TYPICAL ACCESS TIME (NORMALIZED)
liS JUNCTION TEMPERATURE
-- ----
TYPICAL 1004 vs VOO
-
r---
4
tRC = 750n5
J----
VCC SUPPLY VOLTAGE (VOLTS)
1.2
8
tRC = 500ns
---
-
'0 0.91-------+-----+------+------1
~
f-
~
J//
1.1 r-----+-----+------t------j
o ~oo =13.2V
~C = 375n5
/
0
/'
V
//
TJ.=
<{
50
80
TJ.JUNCTION TEMPERATURE 1°C)
110
-
~
11
DO =13.2V
1fC = 250n5
18
f-
a;
~161---~--+------j------+-----+
1fC = 375ns
-
V-- ----
10
.§.
/
/""
4
0
20
sot
,/
.;
2
-10
11.
20
6
C.7
tRC = 750n5
TYPICAL 1004 Vi. JUNCTION TEMPERATURE
20
8
tRC = SOOn
-r--
20
50
80
TJ,JUNCTION TEMPERATURE (OC)
:;'C = 250n5
1
tAC'" 375n5
t=-
12
.-1-
--13
IV-61
tpc ",'375n5
~14r-~_+------j--~~~~---+
tpc = 500n5
-VOD SUPPLY VOL rAGE (VOLTS)
,.a
~..,
tpc '" 500ns
~121-------+------j--~~~=----+
14
1~,~0,-----!2;;;0--~50;---,:.80;------!110
TJ.JUNCTION TEMPERATIjRE IOC)
TYPICAL CLOCK INPUT LEVELS VI. Voo
TJ =50t
VBB --5.0V
~
~
1.5
i
1.0
2.
!IHC(MIN)
-
2.0
~
w
~
2.0
- 1.0
TYPICAL
2.5
-
-4.5
5.0
5.5
Vea SUPPLY VOLTAGE (VOLTS)
ADDRE.~
-<1.0
, ., 0
0.:''-0----:2'=0---:::50:----::80,---1
TJ. JUNCTION TEMPERATURE (oC)
AND DATA INPUT lEVELS vs Vea
TYPICAL ADDRESS AND DATA INPUT lEVELS vs. TJ
3.0
11
2.5
~
oJ
13
VOO SUPPLY VOLTAGE (VOLTS)
14
Vaa =-5.0V
~2.0
VIHIMINI
VIH(MIN)
~
w
~ 1.5
1.5
....
i-'.0
0.6
-4.0
~OO·'2.0V
~
~
w
'v'LIMAXI
12
VOO ·'2.OV
~2.2.0
VIH(MIN)
O. 5
10
4.0
TJ"5O"C
--
i
1.0 t----+----1I---+----l
3.0
,..-- ~
1.5
VllCIMAX
VllC (MAX
14
TJ = sot
Vaa =-5.0V
w
VIH~INI
~
~
O.5
~
til i!.01--===t==--1f-~==i::;===--l
....
Z~_'·6
!1.0
3.0
~
>
w
TYPICAL AOORESSANO DATA INPUT LEVELS vs. VOO
oJ
VIHC (MIN)
~
11
12
13
VOO SUPPLY VOLTAGE (VOLTS)
Vaa =-5.0V
C;
~1.6
10
~
en 2.5
5 VOO = 12.0V
~
0.5
~2.
Voo =12.0V
~ 2.0
VILC (MAXI
2.5
3.0.---'--,---..,----,----,
3.0
TJ-50OC
2.5
TYPICAL CLOCK INPUT LEVELS VI. TJ
TYPICAL CLOCK INPUT lEVELS VI Vaa
3.0
Vll(MAX)
~
Vll(MAX}
-1.0
0.5
--4.5
-5.0
-5.5
Vea SUPPLY VOLTAGE (VOLTS)
IV-62
-<1.0
-10
20
50
80
TJ. JUNCTION TEMPERATURE (Gel
110
MOSTEI{.
MEMORY COMPONENTS
65,536 x 1-.Bit Dynamic RAM
MK4564{P INI J)-15/20/25
FEATURES
D Extended DOUT hold using CAS control (Hidden Refresh)
D Recognized industry standard 16-pin configuration from
D Common 1/0 capability using "early write"
Mostek
D Read, Write, Read-Write, Read-Modify-Write and Page-
D Single +5V (± 10%) supply operation
D On
chip substrate
performance
bias
Mode capability
generator for optimum
D Low power: 300 mW active, max
D All
inputs TIL compatible, low capacitance, and
protected against static charge
D Scaled POLY 5™ technology
22 mW standby, max
D
D 150 ns access time, 260 ns cycle time (MK4564-15)
200 ns access time, 345 ns cycle time (MK4564-20)
250 ns access time, 425 ns cycle time (MK4564-25)
DESCRIPTION
The MK4564 is the new generation dynamic RAM.
Organized 65,536 words by 1 bit, it is the successor to the
industry standard MK4116. The MK4564 utilizes Mostek's
Scaled POLY 5 process technology as well as advanced
circuit techniques to provide wide operating margins, both
internally and to the system user. The use of dynamic
circuitry throughout, including the 512 sense amplifiers,
assures that power dissipation is minimized without any
sacrifice in speed or internal and external operating
margins. Refresh characteristics have been chosen to
maximize yield (low cost to user) while maintaining
compatibility between dynamic RAM generations.
128 refresh cycles (2 msec)
Pin 9 is not needed for refresh
D MKB version screened to MIL-STD-883
Multiplexed address inputs (a feature dating back to the
industry standard MK4096, 1973) permit the MK4564 to
be packaged in a standard 16-pin DIP with only 15 pins
required for basic functionality. The MK4564 is designed to
be compatible with the JEDEC standards for the 64K x 1
dynamic RAM.
Theoutputofthe MK4564 can be held valid upto 10 J1.sec by
holding CAS active low: This is quite useful since refresh
cycles can be performed while holding data valid from a
previous cycle. This feature is referred to as Hidden Refresh.
The 64K RAM from Mostek is the culmination of several
years of circuit and process development, proven in
predecessor products.
PIN OUT
PIN FUNCTIONS
DUAL-IN-LiNE PACKAGE
"a-A 7
Address Inputs
RAS(RE)
CAS(CE)
Column Address
Strobe
Data In
Data Out
WRITE(W)
D'N(D)
DOUT(Q)
Vee
Vss
N!C
Row Address
Strobe
Read!
Write Input
Power (5V)
GND
Not Connected
16 vss
2
15 CAS (eel
WRil'EjW) 3
140 oUT (Qj
DINID}
RAs lIfE) 4
13 As
Ao 5
A, 6
12 A]
11
A4
A, 7
10
As
Vee
Available soon in MIL-STD-883 Class B (MKB).
IV-63
8
9 A,
1'1
ABSOLUTE MAXIMUM RATINGS*
Voltage on Vcc supply relative to VSS ., ...•...........................................••....•... -1.0 Vto +7.0 V
Operating Temperature, TA (Ambient)" ...................................•...........••.....•..••.. O°C to +70C
Storage Temperature (Ceramic)' .•..••.... , .•......•...•................••.................... -65°C to +150°C
Storage Temperature (Plastic) ..•...•.... '.•...........•................••.................... -55°C to +125°C
'Power Dillsipation .•........... ',' .•.........................•.......•..•.........•......•.....•..... 1 Watt
Short Circuit Output Current ...• ;'..•......••......•..•..............•.••.•.•.................•....... 50 mA
*Stres~es greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
(O°C ::::; TA::::; 70°C)
SYM
PARAMETER
MIN
TVP
MAX
UNITS
NOTES
VCC
Supply Voltage
4.5
5.0
5.5
V
1
V 1H
Input High (Logic 1) Voltage,
All Inputs
2.4
-
V cc +1
V
1
V 1L
Input Low (Logic 0)
Voltage, All Inputs
-2.0
-
.8
V
1,18
MAX
UNITS
NOTES
54,0
mA
2
4
mA
DC ELECTRICAL CHARACTERISTICS
(O°C ::::;TA ::::; 70°C) (Vcc = 5.0 V ± 10%)
SYM
PARAMETER
MIN
ICC1
OPERATING CURRENT
Average power supply operating current
(RAS, CAS cycling; t RC = t RC min.)
ICC2
STANDBY CURRENT
Power 'supply standby current (RAS ,= V 1H '
DOUT = High Impedance)
ICC3
RAS ONLY REFRESH CURRENT
Average power supply current, refresh mode
(RAS cycling, CAS = "IH; t RC = t RC min.)
45
mA
2
'CC4
PAGE MODE CURRENT
Average power supply current, page mode
operation (RAS = V 1L' t RAS '= t RAS max., ~
cycling; tpc = tpc min.)
35
mA
2
'I(L)
INPUT LEAKAGE
Input leakage current, any input
(0 V::::; V 1N ::::; Vcc), all other pins not under
test=OV
-10
10
p.A.
'O(L)
OUTPUT LEAKAGE
Output leakage current (DOUT is disabled,
V::::; V OUT ::::; Vce!
-10
10
p.A.
0.4
V
V
\
o
V OH
VOL
OUTPUT LEVELS
Output High (Logic 1) voltage (lOUT = -5 mAl
Output Low (Logic 0) voltage (lOUT = 4.2 mAl
IV-64
2.4
specified tRCO (max) limit, then access time is controlled exclusively by
tCAe12. Either tRRH or tRCH must be satisfied for a read cycle
13. These parameters are referenced to CAS leading edge in early write cycles
and to WRITE leading edge in delayed write or read-modify-write cycles.
NOTES:
1. All voltages referenced to Vss
2.ICC is dependent on output loading and cycle rates. Specified values are
obtained with the output open.
3. An initial pause of 500 JiS is required after power-up followed by any 8 RAS
cycles before proper device operation is achieved. Note that RAS may be
cycled during the initial pause
4. AC characteristics assume tT = 5 ns.
5. V1H min. and VIL max. are reference levels for measuring timing of input
14. twcs, tCWD' and tRWD are restrictive operating parameters in
READ/WRITE and READ/MODIFY/WRITE cycles only. If twcs :> twcs
(min) the cycle is an EARLY WRITE cycle and the data output will remain
open circuit throughout the entire cycle. If teWD:2 tewD (min) and tRWD:2
tRWD (min)the cycle is a READ/WRITE and the data output will contain data
read from the selected cell. If neither of the above conditions are met the
condition of the data out (at access time and until CAS goes back to VIH) is
indeterminate.
15. In addition to meeting the transition rate specification, all input signals must
transmit between VIH and VIL (or between VIL and VIH) in a monotonic
manner
16. Effective capacitance calculated from the equation C::: I.£.! with f::. V:: 3 volts
and power supply at nominal level
f::. V
17. CAs = VIH to disable DOUT
18. Includes the DC level and all instantaneous signal excursions.
19. WRITE::: don't care. Data out depends on the state of CAS. If CAS = VIH, data
output is high impedance. If CAS = VIL, the data output will contain data
from the last valid read cycle.
signals. Transition times are measured between VIH and VIL'
6. The minimum specifications are used only to indicate cycle time at which
proper operation over the full temperature range (DoC::; TA :::; 70°C) is
assured.
7. Load = 2 TIL loads and 50 pF.
8. Assumes that tRCD :::; tRCO (max). If tRCO is greater than the maximum
recommended value shown in this table, tRAC will increase by the amount
that tRCO exceeds the value shown.
9. Assumes that tRCO 2 tRCD (max).
10. tOFF max defines the time at which the output achieves the open circuit
condition and is not referenced to VOH or VOL.
11. Operation within the tRCO (max) limit insures that tRAC (max) can be met.
tRCO (max) is specified as a reference point only; if tRCO is greater than the
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(3A.5,15)(0°C:::; TA :::; 70°C), VCC = 5.0 V ± 10%
SYMBOL
STD
ALT
PARAMETER
MK4564-15
MIN
MAX
MK4564-20
MAX
MIN
MK4564-25
MIN
MAX
UNITS
NOTES
tRELREL
t Rc
Random read or write cycle time
260
345
425
ns
6,7
tRELREL
(RMW)
tRMW
Read-modify-write cycle time
310
405
490
ns
6,7
tRELREL
(PC)
tpc
Page mode cycle time
155
200
240
ns
6,7
tRELOV
t RAC
Access time from RAS
150
200
250
ns
7,8
tCELOV
t cAC
Access time from CAS
85
115
145
ns
7,9
t CEHOZ
tOFF
Output buffer turn-off delay
0
40
0
50
0
60
ns
10
tT
tT
Transition time (rise and fall)
3
50
3
50
3
50
ns
5,15
tREHREL
t RP
RAS precharge time
100
tRELREH
t RAS
RAS pulse width
150
tCELREH
t RSH
RAS hold time
85
115
145
ns
tRELCEH
tCSH
CAS hold time
150
200
250
ns
tCELCEH
tCAS
CAS pulse width
85
10,000
115
10,000
145
10,000
ns
tRELCEL
t RCD
RAS to CAS delay time
30
65
35
85
45
105
ns
11
tREHWX
tRRH
Read command hold time
referenced to RAS
20
25
30
ns
12
165
135
10,000
200
10,000
250
ns
10,000
ns
tAVREL
t ASR
Row address set-up time
0
0
0
ns
tRELAX
tRAH
Row address hold time
20
25
30
ns
tAVCEL
tASC
Column address set-up time
0
0
0
ns
tCELAX
tCAH
Column address hold time
30
40
50
ns
t RELA((
tAR
Column address hold time
referenced to RAS
100
130
160
ns
IV-65
II
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (Continued)
(3,4,5,15) (0° :c:; TA:C:; 70°C), V cc = 5.0 V ± 10%
SYMBOL
MK4564-15
MK4564-20
MK4564-25
MIN
MIN
MIN
STD
ALT
PARAMETER
tWHCEL
t RCS
Read command set-up time
0
0
0
ns
tCEHWX
t RCH
Read command hold time
referenced to CAS
0
0
0
ns
MAX
MAX
MAX
UNITS NOTES
tCELWX
tWCH
Write command hold time
45
55
70
ns
tRELWX
t WCR
Write command hold time
referenced to RAS
115
150
185
ns
12
t WLWH
twp
Write command pulse width
35
45
55
ns
tWLREH
t RWL
Write command to RAS lead time
45
55
65
ns
tWLCEH
tCWL
Write command to CAS lead time
45
55
65
ns
t DVCEL
t DS
Data-in set-up time
0
0
0
ns
13
tCELDX
tDH
Data-in hold time
45
55
70
ns
13
tRELDX
tDHR
Data-in hold time
referenced to RAS
115
150
190
ns
CAS precharge time
(for page-mode cycle only)
60
75
85
ns
tCEHCEL
(PC)
tcp
t RVRV
tREF
Refresh Period
tWLCEL
twcs
WRITE command set-up time
tCELWL
tCWD
tRELWL
tCEHCEL
2
2
ms
2
-10
-10
-10
ns
14
CAS to WRITE delay
55
80
100
ns
14
t RWD
RAS to WRITE delay
120
165
205
ns
14
t CPN
CAS precharge time
30
35
45
ns
AC ELECTRICAL CHARACTERISTICS
(Oo:c:; TA:C:; 70°C), VCC = 5.0V ± 10%
SYM
PARAMETER
Cil
Input Capacitance (Ao - A 7 ), DIN
5
pF
16
CI2
Input Capacitance RAS, CAS, WRITE
10
pF
16
Co
Output Capacitance (D OUl)
7
pF
16,17
MAX UNITS NOTES
IV-66
READ CYCLE
V1H _
RAS
V'L-
V'H_
CAS
V'L-
ADDRESSES
V 1H _
II
V'l-
WRITE
DOUT
V 1H _
V'ltOFF
V OH _
VOl _
OPEN
WRITE CYCLE (EARLY WRITE)
RAS
CAS
ADDRESSES
V1H _
V1L
-
V'HV1l -
V'H_
V'l-
WRITE
V1L -
D'N
V'H_
V1L tOHR
Dour
VOH VOl-
OPEN
IV-67
READ-WRITE/READ-MODIFY-WRITE CYCLE
RAS
V 1H _
ADDRESSES V IL -
VVifITE
V'H_ ~~7r.~~~7r.~r-----~--------------------~i
V IL
-
~'""'"''f''~~'"''
V OH VOl_------~---------------------O
V'H _
"'"7r.>7777>'77:7r.~7n'77:>77~'77:>77~7n7r.>7777>"7'"?;"77'."'" .r-~:-:-:-;~'lI.. "''7n7r.777'7n7r.777","7'"?;'7;
V'l-~~~~~~~~~~~~~GU,",~GU,"",",~~ ~~~~~ ~~~~~~,"",",~LL
"RAS-ONLY" REFRESH CYCLE
t Re
t RAS
_ t RAH
t ASR ~
ADDRESSES
IV-58
{
I
L
tRP
I
PAGE MODE READ CYCLE
~-----------------------------tRAs----------------------------~~~l~
~~~==:;t---~ }1----.,--.---~L,..=t_
II
ADDRESSES V ,H
VIL
PAGE MODE WRITE CYCLE
~---------------------------tRAS----------------------------~
CAS
ADDRESSES
WRITE
V ,H
VIL
V IH
VIL
DIN
V IH
VIL
IV-69
OPERATION
DATA OUTPUT CONTROL
The eight address bits required to decode 1 of the 65,536
cell locations within the MK4564 are multiplexed onto the
eight address inputs and latched into the on-chip address
latches by externally applying two negative going TIL-level
clocks. The first clock, Row Address Strobe (RAS), latches
the eight row addresses into the chip. The high-to-Iow
transition of the second clock, Column Address Strobe
(CAS), subsequently latches the eight column addresses
into the chip. Each ofthesesignals, RAS and CAS, triggers a
sequence of events which are controlled by different
delayed internal clocks. The two clock chains are linked
together logically in such a way that the address
multiplexing operation is done outside of the critical timing
path for read data access. The later events in the CAS clock
sequence are inhibited until the occurrence of a delayed
signal derived from the RAS clock chain. This "gated CAS"
feature allows the CAS clock to be externally activated as
soon as the Row Address Hold specification (t RAH ) has been
satisfied and the address inputs have been changed from
Row address to Column address information.
The normal condition of the Data Output (D OUT) of the
MK4564 is the high impedance (open-circuit) state;
anytime CAS is high (inactive) the DOUT pin will be floating.
Once the output data port has gone active, it will remain
valid until CAS is taken to the precharge (inactive high)
state.
The "gated CAS" feature permits CAS to be activated at any
time after tRAH and it will have no effect on the worst case
data access time (tRAd up to the point in time when the
delayed row clock no . longer inhibits the remaining
sequence of column clocks. Two timing endpoints result
from the internal gating of CAS which are called t RCD (min)
an~D (max). No data storage or reading errors will result
if CAS is applied to the MK4564 at a point in time beyond
the t RCD (max) limit. However, access time will then be
determined exclusively by the access time from CAS (tcAd
rather than from RAS (t RAC )' and RAS access time will be
lengthened by the amount that t RCD exceeds the t RCD (max)
limit.
PAGE MODE OPERATION
The Page Mode feature of the MK4564 allows for
successive memory operations at multiple column locations
within the same row address. This is done by strobing the
row address into the chip and maintaining the RAS signal
low (active) throughout all successive memory cycles in
which the row address is common. The first access within a
page mode operation will be available at tRAC or t CAC time,
whichever is the limiting parameter. However, all
successive accesses within the page mode operation will be
available at t CAc time (referenced to CAS). With the
MK4564 this results in approximately a 45% improvement
in access times. Effective memory cycle times are also
reduced when using page mode.
The page mode boundary of a single MK4564 is limited to
the 256 column locations determined by all combinations of
the eight column address bits. Operations within the page
boundary need not be sequentially addressed and any
combination of read, write, andread-modify-write cycles
is permitted within the page mode operation.
REFRESH
DATAINPUT/OUTPUT
Data to be written into a selected cell is latched into an
on-chip register by a combination of WRITE and CAS while
RAS is active. The latter of WRITE or CAS to make its
negative transition is the strobe for the Data In (DIN) register.
This permits several options in the write cycle timing. In a
write cycle, ifthe WRITE input is brought low (active) prior to
CAS being brought low (active), the DIN is strobed by CAS,
and the Input Data set-up and hold times are referenced to
CAS. If the input data is not available at CAS time (late write)
or if it is desired that the cycle be a read-write or readmodify-write cycle the WRITE signal should be delayed until
after CAS has made its negative transition. In this "delayed
write cycle" the data input set-up and hold times are
referenced to the negative edge of WRITE rather than CAS.
Data is retrieved from the memory in a read cycle by
maintaining WRITE in the inactive or high state throughout
the portion of the memory cycle in which both the RAS and
CAS are low (active). Data read from the selected cell is
available at the output port within the specified access time.
The output data is the same polarity (not inverted) as the
input data.
Refresh of the dynamic cell matrix is accomplished by
performing a memory cycle at each of the 128 row
addresses within each 2ms interval. Although any normal
memory cycle will perform the required refreshing, this
function is most easily accomplished with "RAS-only"
cycles.
The RAS-only .refresh cycle requires that a 7 bit refresh
address (AO-A6)be valid at the device address inputs when
RAS goes low (active). The state of the output data port
during a RAS-only refresh is controlled by CAS. If CAS is
high (inactive) during the entire time that RAS is asserted,
the.outputwill remain in the high impedance state. If CAS is
low (active) the entire time that RAS is asserted, the output
port will remain in the same state that it was prior to the
issuance of the RAS signal. If CAS makes a low-to-high
transition during the RAS-only refresh cycle, the output
data buffer will assume the high impedance state. However,
CAS may not make a high to low transition during the
RAS-only refresh cycle since the device interprets this as a
normal RAS/CAS (read or write) type cycle.
IV-70
HIDDEN REFRESH
A RAS-only refresh cycle may take place while maintaining
valid output data by extending the CAS active time from a
previous memory read cycle. This feature is referred to as a
hidden refresh. (See figure below.)
HIDDEN REFRESH CYCLE (SEE NOTE 19)
--.t~
CAS
ADDRESSES
___M_E_MO_R_YC~Yj====\~
\~------------~;
IIfJK
vm!llli!lR//lmJ
~JIlfJlBl/Tm
'UllDJ
DOUT
RE_FR_ES_H~CY;:=-=t
___
------«
VA.lIO DATA
II
>-
'------~
IV-71
1982/1983 MICROELECTRONIC DATA BOOK
MOSTEI(.
4096x1-BIT STATIC RAM
MK41 04(J/N/E) Series
FEATURES
o
Combination static storage cells and dynamic
control circuitry for truly high performance
PART NUMBER
ACCESS TIME
CYCLE TIME
MK41 04-3/-33
MK41 04-4/-34
MK41 04-5/-35
MK4104-6
200ns
250n,
300ns
350n,
310ns
385n,
460n,
535n,
o
Low Active Power Dissipation: 150mW (Max)
o
Battery backup mode (3V /1 OmW on -33, -34
and -35)
o
Standby Power Dissipation less than 28 mW
(at VCC = 5.5V)
o
Single +5V Power Supply
[]
Fully TTL Compatible
Fanout:
2 - Standard TTL
2 - Schottky TTL
12 - Low Power Schottky TTL
o
Standard 18-pin DIP
o
MKB version screened to MIL-STD-883
± 10% tolerance)
DESCRIPTION
The MOSTEK MK 4104 is a high performance static
random' access memory organized as 4096 one bit
words. The MK 4104 combines the best characteristics of static and dynamic memory techniques to
achieve a TTL compatible, 5 volt only, high performance, low power memory device. It utilizes advanced circuit design concepts and an innovative
state-of-the-art N-channel silicon gate process specially tailored to provide static data storage with the performance (speed and power) of dynamic RAMs.
Since the storage cell is static-IDe device may be
stopped indefinitely with the CE clock in the off
(Logic 1) state.
All input levels, including write enable (WE) and chip
enable (CE) are TTL compatible with a one level of
2.2 volts and a zero level of 0.8 volts. This gives the
system designer for a logic" 1" state, at least 200m V
of noise margin when driven by standard TTL and a
minimum of 500mV when used with high performance Schottky TTL. These margins are wider than
on most TTL compatible MOS memories available.
The push-pull output (no pull-up resistor required)
delivers a one level of 2.4V minimum and a zero
level of .4 volts maximum. The output has a fanout
of 2 standard TTL loads or 12 low power Schottky
loads.
The RAM employs an innovative static cell which
occupies a mere 2.75 square mils (Y:, the area of previous cells) and dissipates power levels comparable
FUNCTIONAL DIAGRAM
PIN CONNECTIONS
Ao1
A1 2
WE
18
A2 3
'"
16 A7
15 As
A3 4
'"
I
"
Vcc
17 A6
A4 5
14 Ag
A5 6
13 A10
DOUT 7
12 A"
11 DIN
10 CE
OOOT
WE 8
Vss 9
PIN NAMES
~-A11
CE
'0
"
DIN
DOUT
V-1
Address Inputs
Chip Enable
Data Input
Data Output
VSS
.'!.e.C
WE
Ground
Power (+5V)
Write Enable
II
ABSOLUTE MAXIMUM RATINGS*
Voltage on any pin relative to VSS .................. -1.0V to +7.0V
Operating Temperature T A (Ambient) ................ 0° C to + 70° C
Storage Temperature (Ambient) (Ceramic) .......... _65° C to +150° C
Storage Temperature (Ambient) (Plastic) ........... _55° C to +125° C
Power Dissipation ..... : .................... '............ 1 Watt
'Stresses greater than those listed under
"Absolute Maximum Ratings" may cause
permanent damage to the device. This is a
stress rating only and functional· operation
of the device at these or any other conditions above those indicated in the opera·
tional sections of this specification is not
implied. Exposure to absolute maximum
rating conditions for extended periods may
affect reliability.
Short Circuit Output Current .............................. 50mA
RECOMMENDED DC OPERATING CONDITIONSs
(00 C..;TA"; + 70°C)
PARAMETER
MK4104 Series
MIN
TYP MAX
UNITS NOTES
Vec
Supply Voltage
4.5
5.0
5.5
Volts
1
VSS
Supply Voltage
0
0
0
Volts
1
VIH
Logic "1" Voltage All Inputs
2.2
7.0
Volts
1
VIL
Logic "0" Voltage All Inputs
-1.0
.8
Volts
1
DC ELECTRICAL CHARACTERISTICS 1
(O°C"; TA"; + 70°C) (VCC = 5.0 volts± 10%)
.
PARAMETER
MIN
MAX
UNITS
NOTES
ICCl
Average VCC Power Supply Current
27
mA
2
ICC2
Standby VCC Power Supply Current
5
mA
3
IlL
Input Leakage Current (Any Input)
-10
10
p.A
4
IOL
Output Leakage Current
-10
10
p.A
3,5
VOH
Output Logic "1" Voltage IOUT=-500p.A
VOL
Output Logic "0" Voltage IOUT= 5mA
Volts
2.4
0.4
Volts
TYP
MAX
NOTES
AC ELECTRICAL CHARACTERISTICS1
(0" C ..;TA"; + 70°C) (VCC = + 5.0 volts ± 10%)
PARAMETER
CI
I nput Capacitance
4pF
6pF
14
Co
Output Capacitance
6pF
7pF
14
NOTES:
1. All voltages referenced to VSS.
8.
2.
ICCl is related to precharge and cycle times. Guaranteed maximum values for ICC1 may be calculated by:
ICCl [mal = (5tp + f5(tC - tpl + 47201 +tc
where tp and tc are expressed in nanoseconds. Equation is reo
ferenced to the -3 device, other devices derate to the same curve.
Data outpUlS open.
3. Output is disabied (open circuit!. ~ is at logic 1.
4.
All device pins at 0 volts except pin under test at 0"; VIN ..; 5.5
volts. (Vee = 5V)
5. OV";VOUT";+ 5.5V. (Vee = 5V)
S. During power up, el and WE must be at VIH for minimum of
2ms after VCC reaches 4.5V, before a valid memory cycle can be
accomplished.
If WE follows el by more than tws then data out may not remain
open circuited.
9. Determined by user. Total cycle time cannot exceed tCE max.
10. Data-in set·1!Q. time is referenced to the later of the two falling
clock edges CE or WE.
11. AC measurements assume tT = 5ns. Timing points are taken at
.BV and 2.0V on inputs and .8V and 2.0V on the output. Tran'
sition times are also taken between these levels.
12.
tc = tCE +tp +2tr'.
13. The true level of the output in the open circuit condition will be
determined totally by output load conditions.' The output is'
guaranteedto be open circuit within tOFF'
14. Effective capacitance calculated from the equation C = I~ with
t:; V equal to 3V and VCC nominal.
t:;V
7. Measured with load circuit equivalent to 2 TTL loads and
CL= 100pF.
15. tRMW = tAC + twPL + tp + 3q + tMOD
V-2
AC ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS6,11
(O°C"; T A"; +70°C) (VCC = + 5.0 volts ± 10%) 1
MK4104-3/33 MK4104-4/34 MK41 04-5/35 MK4104-6
SYMBOL PARAMETER
Read or Write Cycle Time
tc
Random Access
tAC
Chip Enable Pulse Width
tCE
tp
Chip Enable Precharge Time
Address Hold Time
tAH
Address Set-Up Time
tAS
Output Buffer Turn-Off Delay
!OFF
Read Command Set-Up Time
tRS
Write Enable Set-Up Time
tws
Data Input Hold Time
tDHC
Referenced to CE
Data Input Hold Time
tDHW
Referenced to WE
Write Enabled Pulse Width
tww
Modify Time
tMOD
twPL
WE to CE Precharge Lead Time
Data Input Set-Up Time
tDS
Write Enable Hold Time
1WH
Transition Time
tT
Read-Modify-Write Cycle Time
tRMW
MIN MAX
310
200
200 10,000
100
110
a
a
a
50
MIN MAX MIN MAX MIN MAX UNITS NOTES
ns
460
535
12
385
7
350
250
300
250 10,000 300 10,000 350 10,000
125
150
175
135
165
190
a
a
a
65
a
a
a
75
a
a
a
-20
-20
-20
-20
170
210
250
285
70
60
90
75
105
90
125
105
a
10,000
a
10,000
85
70
a
10,000
105
a
100
13
8
8
10,000
9
120
a
a
a
a
10
150
5
50
385
185
5
50
475
225
5
50
570
260
5
50
660
16
MK4104-33
MIN MAX
3.0
3.3
100
100
200
MK4104-34
MIN MAX
3.0
3.3
100
100
250
MK4104-35
MIN MAX UNITS
Volts
3.0
mA
3.3
100
Illsec
100
J,lsec
J,lsec
300
100
2.2
500
125
2.2
500
150
2.2
500
STANDBY CHARACTERISTICS
(TA = O°C to 70°C)
SYMBOL PARAMETER
VCC In Standby
VPD
Standby Cu rrent
IPD
Power Supply Fall Time
tF
Power Supply Rise Time
tR
Chip Enable Pulse Width
tCE
Chip Enable Precharge To
tpPD
Power Down Time
Min CE High "I" Level
VIH
Standby Recovery Time
tRC
nsec
Volts
,J,lsec
POWER DOWN WAVEFORM
_
VCC(MINI
'F
...-
STANDBY MODE
Vee
VPD_
I
-1
L
t_·PPO. . -. ' - - - _ - - - \ ( I ' r - '_ _
I-_'"C
~'CEl'
»)
V-3
II
DESCRIPTION (Cont'd)
to CMOS. The static cell eliminates the need for
refresh cycles and associated hardware thus allowing
easy system implementation.
Power supply requirements of +5V ± 10% tolerance
combined with TTL compatability on all I/O pins
permits easy integration into large memory configurations. The single supply reduces capacitor
count and permits denser packaging on printed circuit
boards. The 5V only supply requirement and TTL
compatible I/O makes this part an ideal choice for
next generation +5V only microprocessors such as
MOSTEK's MK3880 (Z80). The early write mode
(WE active prior to CEl permits common I/O oper-
ation, needed for Z80 interfacing, without external
circuitry.
The MK4104-3X series has the added capability of
retaining data in a reduced power mode. VCC maybe
lowered to 3V with a guaranteed power dissipation of
only 10mW maximum. This makes the MK4104
ideal for those applications requiring data retention
at the lowest possible power as in battery operation.
Reliability is greatly enhanced by the low power
dissipation which causes a maximum junction rise of
only at 8°C at 1.86 Megahertz operation. The MK
4104 was designed for the system designer and user
who require the highest performance available along
with MOSTEK's proven reliability.
READ CYCLE
VIH
ADDRESSES
VIL
VIH
WE
VIL
VIH
DIN
VIL
VOH
DOUT
____
VOL
WRITE CYCLE
VIH
IT
VIL
...
::~~~~~~~~~~~~_t_A_C
..
..
--~J~-------------
_ _ OPEN _ _ _..
--;(
te
,~"
>=
OPEN--
-------------~~~~1
1~-------------teE ------------~~I
VIH
ADDRESSES
VIL
\llH
'_tDHW~
DOUT
----------------------OPEN------------------
V-4
READ-MODIFY-WRITE CYCLE
VIH
1..__- - - - - - - - tRMW
------,I
~-------tCE
ADDRESSES
_t
l
---------;==~
_ _ _ _ _ _ _ _ _ _~I
VALID
-
AH
WE
_,AC
DOUT
- j....
_I__
.-_tM_OD_
.....
- - - - - - - OPEN - - {
-----,itOFF
VALID
} - OPEN - -
OPERATION
READ CYCLE
The circuit offers one bit of the possible 4096 by
decoding the 12 address bits presented at the inputs.
The address bits are strobed into the chiQ by the
negative-going edge of the Chip Enable (GE) clock.
A read c.xme is accomplished by holding the 'write
enable' (WE) jnput at a high level (VI H) while
clocking the CE input to a low level VI L). At
access time (t.AC) valid data will appear at the output.
The output IS unlatched by a positive transition of
CE and therefore will be open circuited (high impedance state) from the previous cycle to access
time and wi!L.go open again at the end of the present
cycle when CE goes high.
write operation the output will go active through the
modify and write period until CE goes to precharg.!::....
If the cycle is such that WE goes active after CE
but before valid data appears on the output (prior to
tAC) then the output may not remain open. However if data-in is valid on the leading edge of WE,
and 'WE occurs prior to the positive transition of CE
by the minimum lead time twpL. then valid data
will be written into the selected cell. The Data in
hold time parameters tDHW and tDHC must be
satisfied.
Once the address hold time has been satisfied, the READ-MODIFY-WRITE CYCLE
addresses may be changed for the next cycle.
The read-modify-write (RMW) cycle is no more
than an extension of the read and write cycles.
WRITE CYCLE
Data is read at access time, modified during a period
Data that is to be written into a selected cell is determined by the user and the same or new data
strobed into the chip on the later occurring ne- written between WE active (low) and the rising edge
gative edge of CE or WE. If the negative transi- of CE (twpL!. Data out will remain valid u.ntil the
edge Of CE. A minimum flMW cyc.le time can
tion of WE" occurs prior to the leading edge of CE as rising
be approximated by the follow!llil equation (tBMW
in an "early" write cycle then the "CE" input serves = RMW cycle time and tp = CE precharge time).
as the strobe for data-in. If CE leading edge occurs
tRMW = tAC + tMOD + tWPL + tp +3tT
prior to the leading edge of WE as in a read-modifywrite cycle then data-in is strobed by the WE input. POWER DOWN MODE
Due to the internal timing generator, two indepen- In power down data may be retained indefinitely by
dent timing parameters must be satisfied for 01 hold maintaining VCC at +3V. However, prior to VCC
time, these are, tDHW and tDHC. For a R!W or RMW going below VCC minimum «4.5V) CE must be
cycle tDHC is automatically satisfied making tDHW taken high (VI H = 2.2V) and held for a minimum
the more restrictive parameter. For a write only cycle time period tPPD and maintained at VIH for the
either parameter can be more restrictive depending entire standby period. After power is returned to
In any event VCC min or above, CE must be held high for a
on the POllition of WE relative to
both parameters must be satisfied.
minimum of tRC in order that the device may
operate properly. See power down waveforms herein.
In an early' vvrite cycle the output will remain in an Any active cycle in progress prior to power down
open or high impedance state. In a read-modify must be completed so that tCE min is not violated.
V-5
rr.
II
OPERATING POWER VS CYCLE TIME
120
24
22
....-l 'f'
20
//
8
./ /
6~r V r\
/ -~
1 4t--y
2V
-r----« V~ ID )>-____-<~r-V-~-~I-~-O-H""\y>-~------~
V-10
VALID OUT
'j---
The MK4118A features a fast CE (50";" of Address Access)
function to permit memory expansion without impacting
system access time. A fast OE (50% of access time) is
included to permit data interleaving for enhanced system
performance.
The MK4118A is pin compatible with Mostek's
BYTEWYDpM memory family of RAMs, ROMs and
EPROMs. Mostek also offers a higher performance version
of the MK4118A designated the MK4801 A.
OPERATION
Read Mode
The M~4118A is in the READ MODE whenever the Write
EnablEfControl input (WE) is in the high state.
In the READ mode of operation, the MK4118A provides a
fast address ripple-through access of data from 8 of 8192
locations in the static storage array. Thus, the unique
address specified by the 10 Address Inputs (An) define
which 1 of 1024 bytes of data is to be accessed.
A transition on any of the 10 address inputs will disable the
8 Data Output Drivers after tAl' Valid Data will be available
to the 8 Data Output Drivers within tAA after the last address
input sigllalis stable, providing that the CE and OE access
times are satisfied. If CE or OE access times are not met,
data access will be measured from the limiting parameter
V-ll
(tCEA or tOEA) rather tha n the address. The state of the 8 data
I/O signals is controlled by the Chip Enable (CE) and Output
Enable (OE) control signals.
Write Mode
The MK4118A is in the Write Mode whenever the Write
Enable (WE) and Chip Enable (CE) control inputs are in the
low state.
The WRITE cycle is initiated by the WE pulse going low
provided that CE is also low. The leading edge of the WE
pulse is used to latch the status of the address bus.
NOTE: In a write cycle the latter occurring edge of either WE
or CE will determine the start of the write cycle. Therefore,
t AS ' two and tAH are referenced to the latter occurring edge
of CE or WE. Addresses are latched at this time. All write
cycles whether initiated by CE or WE must be terminated by
the rising edge of WE. If the output bus has been enabled
(CE and OE low) then WE will cause the output to go to the
high Z state in t WEZ '
Data In must be valid tDswpriortothe low to high transition
of WE. The Data In lines must remain stable for tOHW after
WE goes inactive. The write control of the MK4118A
disables the data out buffers during the write cycle;
however, OE should be used to disable the data out buffers
to prevent bus contention between the input data and data
that would be output upon completion of the write cycle.
II
V-12
MOSlfEI{.
MEMORY COMPONENTS
1 K x 8-Bit Static RAM
MK4801A(P/J/N) Series
FEATURES
D
CE and OE functions facilitate bus control
D Static operation
D Organization: 1 K x 8 bit RAM JEDEC pinout
Access Time
R/W
Cycle Time
MK4801A-55
55 nsec
55/65 nsec
MK4801A-70
70 nsec
70/80 nsec
MK4801A-90
90 nsec
90/100 nsec
Part No.
D Pin compatible with Mostek's BYTEWYDETM memory
family
D 24128 pin ROM/PROM compatible pin configuration
D High performance
DESCRIPTION
The MK4801A uses Mostek's Scaled POLY 5™process and
advanced circuit design techniques to package 8,192 bits of
static RAM on a single chip. Static operation is achieved
with high performance and low power dissipation by
utilizing Address Activated™ circuit design techniques.
BLOCK DIAGRAM
DATA.INPUTS/DUTPUTS
OQO-OQ7
Figure 1
The MK4801 A excels in high speed memory applications
where the organization requires relatively shallow depth
with a wide word format. The MK4801 A presents the user a
high density cost effective alternative to bipolar and
previous generation N-MOS fast memory.
PIN CONNECTIONS
Figure 2
0,----+1
"'----+I
A71
A62
A53
A44
A35
A26
YSENSEAMP
&WRITEDAIVH~
A17
A08
0009
128. 8~8
MEMORY CEll.
MATRIX
0°110
0°211
VSS12
24VCC
23Aa
22
21
20
19
Ag
WE
OE
NC
18 CE
170°7
160°6
150°5
140°4
1300 3
TRUTH TABLE
CE
OE
WE
Mode
DQ
VIH
X
X
Deselect
High Z
VIL
X
VIL
Write
DIN
VIL
VIL
VIH
Read
DOUT
VIL
VIH
VIH
Read
High Z
PIN NAMES
~-A9
CE
VSS
VCC
X = Don't Care
V-13
Address Inputs
Chip Enable
Ground
Power (+5Vj
Write Enable
Output Enable
No Connection
Data In/
Data Out
II
ABSOLUTE MAXIMUM RATINGS*
Voltage on any pin relative to VSS ...................................................•......... -.5V to + 7.0V
Operating Temperature TA (Ambient) ...•........................................................ O°C to + 70°C
Storage Temperature (AmbientXCeramic) ...................................................... -65°C to +150°C
Storage Temperature (AmbientXPlastic) .....................................•.........•.....•. -55°C to +125°C
Power Dissipation .......................................................•.........•................ 1 Watt
Output Current ..............•...................................................................... 20mA
*Stressesgreaterthan those listed under "Absolute Maximum Ratings" maycause permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS7
(O°C ::; TA::; + 70°C)
SYM
PARAMETER
MIN
TVP
MAX
UNITS
NOTES
Vee
Supply Voltage
4.75
5.0
5.25
V
1
VSS
Supply Voltage
0
0
0
V
1
V IH
Logic "1" Voltage All Inputs
2.2
7.0
V
1
V IL
Logic "0" Voltage All Inputs
-2.0
.8
V
1,9
TVP
MAX
UNITS
NOTES
60
125
mA
8
DC ElECTRICAL CHARACTERISTICS',7
(O°C ::; TA::; + 70°C) (Vee
= 5.0 V ± 5%)
SYM
PARAMETER
lee1
Average Vee Power Supply Current
IlL
Input Leakage Current (Any Input)
-10
10
pA
2
IOL
Output Leakage Current
-10
10
pA
2
V OH
Output Logic "1" Voltage lOUT
= 1 mA
2.4
VOL
Output Logic "0" Voltage lOUT
=4mA
MIN
V
0.4
V
CAPACITANCE' ,7
(O°C ::; TA::; + 70°C) (Vee
= +5.0 V ± 5%)
SYM
PARAMETER
TVP
MAX
CI
All pins (except 0/0)
4 pF
6 pF
COlO
0/0 pins
10 pF
12 pF
V-14
NOTES
6
AC ELECTRICAL CHARACTERISTICS 3,4
(O°C $ TA $ 70°) (Vcc = 5.0 V ± 5%)
MK4801A-55 MK4B01A-70 MK4801A-90
SYM
PARAMETER
MIN
MAX
MIN
tRC
Read Cycle Time
tAA
Address Access Time
55
70
90
ns
5
tCEA
Chip Enable Access Time
25
35
45
ns
5
tCEz
Chip Enable Data Off Time
30
ns
tOEA
Output Enable Access
Time
45
ns
tOEZ
Output Enable Data Off
Time
5
30
ns
tAZ
Address Data Off Time
10
10
10
ns
twc
Write Cycle Time
65
80
100
ns
tAS
Address Setup Time
0
0
0
ns
see
text
tAH
Address Hold Time
15
20
30
ns
see
text
tosw
Data To Write Setup Time
5
5
5
ns
tOHW
Data From Write Hold
Time
10
10
10
ns
two
Write Pulse Duration
25
30
40
ns
tWEZ
Write Enable Data Off Time
tWPL
Write Pulse Lead Time
55
MAX
70
15
5
5
25
15
10
5
40
5
5
OUTPUT LOAD
MAX UNITS NOTES
90
20
5
35
50
NOTES:
1. All voltages referenced to Vss.
2. Measured with .4':; VI':; 5.0 V. outputs deselected and VCC = 6 V.
3. AC measurements assume Transition Time = 5 ns. levels VSS to 3.0 V.
4. Input and output timing reference levels are at 1.6 V.
6. Measured with a load as shown in Figure 3.
6. Output buller is daselected.
7. A minimum of 2 ms time delay is required after application of Vee (+6 V)
before proper device operation can be achieved.
8. ICC measured with outputs open.
9. Negative undershoots to a minimum of -1.5 V are allowed with 8 maximum
of 60 ns pulse width.
MIN
20
15
5
5
ns
25
5
see
text
ns
ns
60
6V
Figure 3
1.1Kn
D.U.T. - -.....- - -...
6800
;;:, 30"F
(Including Scope and Jigl
V-15
-
------------
II
TIMING DIAGRAM
Figure 4
READ
READ
WRITE
'RC
'RC
'wc
•
AO-A9
~V
\
/
-.Jr\.
-+
---...
/
r0-
'CEA
\
DE
f.-'AS
1\
\
CE
)~[\
[\
'AA_
•
_'OEA
r=
tAZ
r
....
f.-'AH
-
'WD
I'+---'WPL-+
\~V
-
'OEZ
Dn--DQ7 _ _ _ _ _ _ _ _ _ _-'lV\ VALID OUT I\'>------<.{,ALlD
I
r----,.
OU~
~_-J/
-U
\
VALID
IN
}-------
/
TIMING DIAGRAM
Figure 5
WRITE
WRITE
.....- - - - 'wc ----.........- - - 'wc
~>-~
___-«
READ
----f4----
'RC ---_~
'WPL .....
V~ ID )~----_<\r-V-~N-LlD-'D-H--,)>-~-------~~
V-16
VALID OUT
'j---
The MK4801 A features a fast CE (50% of Address Access)
function to permit memory expansion without impacting
system access time. A fast OE (50% of access time) is
included to permit data interleaving for enhanced system
performance.
(t CEA or tOEA) rather than the address. The state of the 8 data
1/0 signals is controlled by the Chip Enable (CE) and Output
Enable (OE) control signals.
The MK4801 A is pin compatible with Mostek's
BYTEWYDETM memory family of RAMs, ROMs and
EPROMs.
The MK4801A is in the Write Mode whenever the Write
Enable (WE) and Chip Enable (CE) control inputs are in the
low state.
Write Mode
OPERATION
The WRITE cycle is initiated by the WE pulse going low
provided that CE is also low. The leading edge of the WE
pulse is used to latch the status of the address bus.
Read Mode
The MK4801A is in the READ MODE whenever the Write
Enable Control input (WE) is in the high state.
In the READ mode of operation, the MK4801 A provides a
fast address ripple-through access of data from 8 of 8192
locations in the static storage array. Thus, the unique
address specified by the 10 Address Inputs (An) define
which 1 of 1024 bytes of data is to be accessed.
A transition on any of the 10 address inputs will disable the
8 Data Output Drivers after tAl. Valid Data will be available
to the 8 Data Output Drivers within tAA after the last address
input signal is stable, providing that the CE and OE access
times are satisfied. If CE or OE access times are not met,
data access will be measured from the limiting parameter
V-17
NOTE: In a write cycle the latter occurring edge of either WE
or CE will determine the start of the write cycle. Therefore,
t AS ' two and tAH are referenced to the latter occurring edge
of CE or WE. Addresses are latched at this time. All write
cycles whether initiated by CE orWE must be terminated by
the rising edge of WE. If the output bus has been enabled
(CE and OE low) then WE will cause the output to go to the
high Z state in t WEZ .
Da~n must be valid tosw prior to the low to high transition
of WE. The Data In lines must remain stable for tOHW after
WE goes inactive. The write control of the MK4801 A
disables the data out buffers during the write cycle;
however OE should be used to disable the data out buffers
to prevent bus contention between the input data and data
that would be output upon completion of the write cycle.
1982/1983 MICROELECTRONIC DATA BOOK
0)
68000 Family
MOSTEI{.
MICROCOMPUTER COMPONENTS
16-Bit Microprocessor
MK68000
Advances in semiconductor technology have provided the
capability to place on a single silicon chip a microprocessor
at least an order of magnitude higher in performance and
circuit complexity than has been previously available. The
MK68000 is the first of a family of such VLSI microprocessors from Mostek. It combines state-of-the-art
technology and advanced circuit design techniques with
computer sciences to achieve an architecturally advanced
16-bit microprocessor.
The resources available to the MK68000 user consist ofthe
following:
•
•
•
•
•
•
32-Bit Data and Address Registers
16 Megabyte Direct Addressing Range
56 Powerful Instruction Types
Operations on Five Main Data Types
Memory Mapped 1/0
14 Addressing Modes
PIN ASSIGNMENT
PROGRAMMING MODEL
31
1615
87
r--
I
I
I
I
I
--
31
rllll-
r-
o
D4
DO
-
D3
D1
D2
I
I
I
I
I
I
I
I
I
- D3
I
I
D7
EIGHT
DATA
D4 REGISTERS
-
-
D5
D6
o
1615
I
I
-
I
I
-
I
-
I
DS
DO
DS
AS
D10
UDS
D11
LDS
D12
R/iN
D13
DTACK
D14
iiG
D1S
V"
CLK
GND
SEVEN
A3 ADDRESS
A4 REGISTERS
-
D7
D1
iii!
- A1
- A2
I
i
A21
RESET
A1S
\ii\iiA
A1S
VPA
0
I
A22
A17
A6
PROGRAM
COUNTER
87
A23
Vee
A20
STATUS
REGISTER
fhls IS advance Information and speCifications are subject to change without notice
VI-1
A16
BERR
A1S
IPl2
A14
IPl1
A13
IPLO
A12
FC2
ISYSTEM BYTE USER BYTE
GND
HALT
A5
TWO STACK
POINTERS
15
D6
D2
BGACK
AO
DS
A11
FC1
A10
FCO
AS
A1
AS
A2
A7
A3
A6
A4
AS
Included in the register indirect addressing modes is the
capability to do postincrementing, predecrementing, offsetting and indexing. Program counter relative mode can
also be modified via indexing and offsetting.
As shown in the programming model, the MK68000 offers
seventeen 32-bit registers in addition tothe 32-bit program
counter and a 16-bit status register. The first eight registers
(00-07) are used as data registers for byte (8-bit), word
(16-bit), and long word (32-bit) data operations. The second
set of seven registers (AO-A6) and the system stack pointer
may be used as software stack pointers and base address
registers. In addition, these registers may be used for word
and long word address operations. All 17 registers may be
used as index registers.
The MK68000 instruction set is shown in Table 2. Some
additional instructions are variations, or subsets, of these
and they appear in Table 3. Special emphasis has been
given to the instruction set's support of structured highlevel languages to facilitate ease of programming. Each
instruction, with few exceptions, operates on bytes, words,
and long words and most instructions can use any ofthe 14
addressing modes. Combining instruction types, data types,
and addressing modes, over 1000 useful instructions are
provided. These instructions include signed and unsigned
multiply and divide, "quick" arithmetic operations, BCD
arithmetic and expanded operations (through traps).
A 23-bit address bus provides a memory addressing range
of greater than 16 megabytes. This large range of
addressing capability, coupled with a memory management
unit, allows large, modular programs to be developed and
operated without resorting to cumbersome and time
consuming software bookkeeping and paging techniques.
The status register contains the interrupt mask(eight levels
available) as well as the condition codes; extend (X),
negative (N), zero (Z), overflow (V), and carry (C). Additional
status bits indicate that the processor is in a trace (T) mode
and/or in a supervisor (S) state.
DATA ADDRESSING MODES
Table 1
Five basic data types are supported. These data types are:
•
•
•
•
•
Bits
BCD Digits (4-bits)
Bytes (8-bits)
Word (16-bits)
Long Words (32-bits)
In addition, operations on other data types such as memory
addresses, status word data, etc., are provided for in the
instruction set.
The 14 addressing modes, shown in Table 1, include six
basic types:
•
•
•
•
•
•
Register Direct
Register Indirect
Absolute
Immediate
Program Counter Relative
Implied
STATUS REGISTER
SYSTEM BYTE
USER BYTE
Mode
Generation
Register Direct Addressing
Data Register Direct
Address Register Direct
EA= On
EA=An
Absolute Data Addressing
Absolute Short
Absolute Long
EA = (Next Word)
EA = (Next Two Words)
Program Counter Relative
Addressing
EA = (PC) + d 16
Relative with Offset
Relative with Index and Offset EA = (PC) + (Xn) + dB
Register Indirect Addressing
Register Indirect
Postincrement Register Indirect
Predecrement Register Indirect
Register Indirect with Offset
Indexed Register Indirect with
Offset
EA
EA
An
EA
= (An)
= (An), An - An + N
- An - N, EA = (An)
= (An) + d 16
EA = (An) + (Xn) + dB
Immediate Data Addressing
Immediate
Quick Immediate
DATA = Next Word(s)
Inherent Data
Implied Addressing
Implied Register
EA = SR. USp, Sp, PC
NOTES:
SUPERVISOR
STATE
EA = Effective Address
dB = Eight-bit Offset
An = Address Register
(displacement)
On = Data Register
d16 = Sixteen-bit Offset
Xn = Address or Data Register
(displacement)
used as Index Register
N = 1 for Byte, 2 for
SR = Status Register
Words and 4 for Long
PC = Program Counter
Words
( ) = Contents of
Replaces
NEGATIVE
ZERO
OVERFLOW
CARRY
VI-2
INSTRUCTION SET
Table 2
Mnemonic Description
Mnemonic
Description
Mnemonic
Description
ABCD
ADD
AND
ASL
ASR
EOR
EXG
EXT
JMP
JSR
LEA
LINK
LSL
LSR
MOVE
MOVEM
MOVEP
MULS
MULU
NBCD
Exclusive Or
Exchange Registers
Sign Extend
Jump
Jump to Subroutine
Load Effective Address
Link Stack
Logical Shift Left
Logical Shift Right
Move
Move Multiple Registers
Move Peripheral Data
Signed Multiply
Unsigned Multiply
Negate Decimal with
Extend
Negate
No Operation
One's Complement
Logical Or
PEA
RESET
ROL
ROR
ROXL
ROXR
RTE
RTR
RTS
SBCD
See
STOP
SUB
SWAP
TAS
Push Effective Address
Reset External Devices
Rotate Left without Extend
Rotate Right without Extend
Rotate Left with Extend
Rotate Right with Extend
Return from Exception
Return and Restore
Return from Subroutine
Subtract Decimal with Extend
Set Conditional
Stop
Subtract
Swap Data Register Halves
Test and Set Operand
TRAP
TRAPV
TST
UNLK
Trap
Trap on Overflow
Test
Unlink
Bee
BCHG
BCLR
BRA
BSET
BSR
BTST·
CHK
CLR
CMP
DBee
DIVS
DIVU
Add Decimal with Extend
Add
Logical And
Arithmetic Shift Left
Arithmetic Shift Right
Branch Conditionally
Bit Test and Change
Bit Test and Clear
Branch Always
Bit Test and Set
Branch to Subroutine
BitTest
Check Register Against
Bounds
Clear Operand
Compare
NEG
Test Condition, Decrement NOP
NOT
and Branch
OR
Signed Divide
Unsigned Divide
VARIATIONS OF INSTRUCTION TYPES
Table 3
Instruction
Type
ADD
AND
CMP
EOR
Variation
Description
Instruction
Type
Variation
Description
ADD
ADDA
ADDQ
ADDI
ADDX
AND
ANDI
Add
Add Address
Add Quick
Add Immediate
Add with Extend
Logical And
And Immediate
MOVE
MOVE
MOVEA
MOVEQ
MOVE from SR
MOVE to SR
MOVE to CCR
MOVE USP
MOVE
Move Address
Move Quick
Move from Status Register
Move to Status Register
Move to Condition Codes
Move User Stack Poi nter
CMP
CMPA
CMPM
CMPI
Compare
Compare Address
Compare Memory
Compare Immediate
NEG
NEG
NEGX
OR
ORI
Negate
Negate with Extend
Logical Or
Or Immediate
EOR
EORI
Exclusive Or
Exclusive Or Immediate
SUB
SUBA
SUBI
SUBQ
SUBX
Subtract
Subtract Address
Subtract Immediate
Subtract Quick
Subtract with Extend
OR
SUB
DATA ORGANIZATION AND ADDRESSING
CAPABILITIES
The following paragraphs describe the data organization
and addressing capabilities of the MK68000.
OPERAND SIZE
Operand sizes are defined as follows: a byte equals 8 bits, a
word equals 16 bits, and a long word equals 32 bits. The
operand size for each instruction is either explicitly encoded
in the instruction or implicitly defined by the instruction
operation. All explicit instructions ~upport byte, word or long
word operands. Implicit instructions support some subset of
all three sizes.
DATA ORGANIZATION IN REGISTERS
The eight data registers support data operands of 1,8,16, or
VI-3
•
32 bits. The seven address registers together with the active
stack pointer support address operands of 32 bits.
explained in the following paragraphs.
Instructions specify an operand location in one of three
ways:
DATA REGISTERS. Each data register is 32 bits wide.
Byte operands occupy the low order 8 bits, word operands
the low order 16 bits, and long word operands the entire 32
bits. The least significant bit is addressed as bit zero; the
most significant bit is addressed as bit 31.
Register Specification - the number of the register is given
in the register field of the instruction.
Effective Address - use of the different effective address
modes.
Implicit Reference - the definition of certain instructions
implies the use of specific registers.
When a data register is used as either a source or
destination operand, only the appropriate low-order portion
is changed; the remaining high-order portion is neither
used nor changed.
INSTRUCTION FORMAT
Instructions are from one to five words in length, as shown
in Figure 3. The length of the instruction and the operation
to be performed is specified by the first word of the
instruction which is called the operation word. The
remaini ng words further specify the operands. These words
are either immediate operands or extensions to the effective
address mode specified in the operation word.
ADDRESS REGISTERS. Each address register and the
stack pointer is 32 bits wide and holds a full 32 bit address.
Address registers do not support byte sized operands.
Therefore, when an address register is used as a source
operand, either the low order word or the entire long word
operand is used depending upon the operation size. When
an address register is used as the destination operand, the
entire register is affected regardless of the operation size. If
the operation size is word, any other operands are sign
extended to 32 bits before the operation is performed.
PROGRAM/DATA REFERENCES
The MK68000 separates memory references into two
classes: program references, and data references. Program
references, as the name implies, are references to that
section of memory that contains the program being
executed. Data references refer to that section of memory
that contains data. Generally, operand reads are from the
data space. All operand writes are to the data space.
DATA ORGANIZATION IN MEMORY
Bytes are individually addressable with the high order byte
having an even address the same as the word, as shown in
Figure 1. The low order byte has an odd address that is one
count higher than the word address. Instructions and
multibyte data are accessed only on word (even byte)
boundaries. If a long word datum is located at address n (n
even), then the second word of that datum is located at
address n + 2.
REGISTER SPECIFICATION
The register field within an instruction specifies the register
to be used. Other fields within the instruction specify
whether the register selected is an address or data register
and how the register is to be used.
The data types supported by the MK68000 are: bit data,
integer data of 8, 16, or 32 bits, 32-bit addresses and binary
coded decimal data. Each of these data types is put in
memory, as shown in Figure 2.
EFFECTIVE ADDRESS
ADDRESSING
Most instructions specify the location of an operand by
using the effective address field in the operation word. For
example, Figure 4 shows the general format of the single
effective address instruction operation word. The effective
address is composed of two 3-bit fields: the mode field, and
the register field. The value in the mode field selects the
Instructions for the MK68000 contain two kinds of
information: the type of function to be performed, and the
location of the operand(s) on which to perform that function.
The methods used to locate (address) the operand(s) are
WORD ORGANIZATION IN MEMORY
Figure 1
15
14
13
12
11
10
9
7
8
6
5
4
3
2
o
WORDjOOOOO
BYTE 000000
BYTE 000001
WORDjOOO02
BYTE 000002
~
···
BYTE 000003
4
WORDtFFFFE
BYTE FFFFFE
BYTE FFFFFF
VI-4
DATA ORGANIZATION IN MEMORY
Figure 2
BIT DATA
1 BYTE = 8 BITS
7
6
o
2
3
4
5
INTEGER DATA
1 BYTE 8 BITS
=
15
14
13
12
I·"
11
10
8
9
7
BYTE 2
1 WORD
13
12
11
10
9
3
2
0
2
0
BYTE 1
BYTE 3
=16 BITS
8
I~'
7
6
5
4
3
~'I
WORD 0
WORD 1
WORD 2
1 LONG WORD
15
14
12
13
11
10
8
9
MSB
-
4
5
~'I
BYTE 0
14
15
6
=32 BITS
7
6
4
6
3
0
2
HIGH ORDER
-LONGWORDO -
------ ---------
-
LOWORDER
LSB
-
-LONG WORD 1 -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-LONG WORD 2 -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ADDRESSES
1 ADDRESS 32 BITS
=
15
14
13
12
11
10
9
MSB
-
-ADDRESSO- -
-
-
-
-
8
6
7
4
5
HIGH ORDER
- - - LOWORDER
-
-
-
-
-
o
2
3
-
-
LSB
-
-ADDRESS 1 -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-ADDRESS 2 - -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
MSB = Most Significant Bit
LSB Least Significant Bit
=
15
14
MSD
13
12
11
10
9
BCD1
BCDO
8
7
LSD
BCD5
..
-
DECIMAL DATA
2 BINARY CODED DECIMAL DIGITS = 1 BYTE
BCD4
-
-
..
MSD - Most SIgnifIcant Dogit
LSD = Least Significant Digit
VI-5
6
5
4
3
o
2
BCD2
BCD3
BCD6
BCD7
•
different address modes. The register field contains the
number of a register.
The effective address field may require additional
information to fully specify the operand. This additional
information, called the effective address extension, is
contained in the following word or words and is considered
part of the instruction, as shown in Figure 3. The effective
address modes are grouped into three categories: register
direct, memory addressing, and special.
REGISTER DIRECT MODES
These effective addressing modes specify that the operand
is in one of the 16 multifunction registers.
Data Register Direct. The operand is in the data register
specified by the effective address register field.
Address Register Direct. The operand is in the address
register specified by the effective address register field.
MEMORY ADDRESS MODES
These effective addressing modes specify that the operand
is in memory and provide the specific address of the
operand.
Address Register Indirect. The address of the operand is in
the address register specified by the register field. The
reference is classified as a data reference with the
exception of the jump and jump to subroutine instructions.
Address Register Indirect With Postincrement. The
address of the operand is in the address register specified by
the register field. After the operand address is used, 'it is
incremented by one, two, or four depending upon whether
the size of the operand is byte, word, or long word. If the
address register is the stack pointer and the operand size is
byte, the address is incremented by two rather than one to
keep the stack pointer on a word boundary. The reference is
classified as a data reference.
Address Register' Indirect With Predecrement. The
address of the operand is in the address register specified by
the register field. Before the operand address is used, it is
decremented by one, two, or four depending upon whether
the operand size is byte, word, or long word. If the address
register is the stack pointer and the operand size is byte, the
address is decremented by two rather than one to keep the
stack pointer on a word boundary. The reference is
classified as a data reference.
Address Register Indirect With Displacement. This
address mode requires one word of extension. The address
of the operand is the sum of the address in the address
register and the sign-extended 16-bit displacement integer
in the extension word. The reference is classified as a data
reference with the exception of the jump and jump to
subroutine instructions.
Address Register Indirect With Index. This address mode
requires one word ofextension. The address ofthe operand
is the sum of the address in the address register, the signextended displacement integer in the low order eight bits of
the extension word, and the contents of the index register.
The reference is classified as a data reference with the
exception of the jump and jump to subroutine instructions.
SPECIAL ADDRESS MODES
The special address modes use the effective address
INSTRUCTION FORMAT
Figure 3
15
14
13
12
11
10
9
8
7
6
5
4
3
2
o
OPERATION WORD
(FIRST WORD SPECIFIES OPERATION AND MODES)
IMMEDIATE OPERAND
(IF ANY, ONE OR TWO WORDS)
SOURCE EFFECTIVE ADDRESS EXTENSION
(IF ANY, ONE OR TWO WORDS)
DESTINATION EFFECTIVE ADDRESS EXTENSION
(IF ANY, ONE OR TWO WORDS)
SINGLE-EFFECTIVE-ADDRESS INSTRUCTION
OPERATION WORD GENERAL FORMAT
Figure 4
5
VI-6
2
3
o
4
EFFECTIVE ADDRESS
REGISTER
MODE
register field to spec;:ify the special addressing mode instead
of a register number.
one word of extension. The address is the sum of the
address in the program counter, the sign-extended
displacement integer in the lower eight bits ofthe extension
word, and the contents of the index register. The value in
the program counter is the address of the extension word.
This reference is classified as a program reference.
Absolute Short Address. This address mode requires one
word of extension. The address of the operand is the
extension word. The 16-bit address is sign extended before
it is used. The reference is classified as a data reference
with the exception of the jump and jump to subroutine
instructions.
Immediate Data. This address mode requires either one or
two words of extension depending on the size of the
operation.
Absolute Long Address. This address mode requires two
words of extension. The address ofthe operand is developed
by the concatenation of the extension words. The highorder part of the address is the first extension word; the
low-order part of the address is the second extension word.
The reference is classified as a data reference with the
exception of the jump and jump to subroutine instructions.
Byte operation - operand is low order byte of extension
word
Word operation - operand is extension word
Long word operation - operand is in the two extension
words, high-order 16 bits are in the first extension
word, low-order 16 bits are in the second extension
word.
Program Counter With Displacement. This address mode
requires one word of extension. The address ofthe operand
is the sum of the address in the program counter and the
sign-extended 16-bit displacement integer in the extension
word. The value in the program counter is the address ofthe
extension word. The reference is classified as a program
reference.
IMPLICIT INSTRUCTION REFERENCE SUMMARY
Table 5
Instruction
Program Counter With Index. This address mode requires
Branch Conditional (Bee)' Branch
Always (BRA)
EFFECTIVE ADDRESS ENCODING SUMMARY
Branch to Subroutine (BSR)
Table 4
Addressing Mode
Implied
Register(s)
PC
PC,SP
Check Register against Bounds (CHK)
SSP, SR
PC
Mode
Register
Data Register Direct
000
register number
Test Condition, Decrement and Branch
(DBee)
Address Register Direct
001
register number
Signed Divide (DIVS)
SSP, SR
Address Register Indirect
010
register number
Unsigned Divide (DIVU)
SSP, SR
Address Register Indirect
with Postincrement
011
register number
Jump (JMP)
Jump to Subroutine (JSR)
Address Register Indirect
with Predecrement
100
register number
Address Register Indirect
with Displacement
101
register number
Address Register Indirect
with Index
110
register number
Absolute Short
111
000
Absolute Long
111
001
Program Counter with
Displacement
111
010
Program Counter with
Index
111
011
Immediate or Status
Register
PC
PC,SP
Link and Allocate (LINK)
SP
Move Condition Codes (MOVE CCR)
SR
Move Status Register (MOVE SRI
SR
Move User Stack Pointer (MOVE USP)
USP
Push Effective Address (PEA)
SP
Return from Exception (RTE)
PC, SP, SR
Return and Restore Condition Codes (RTR) PC, SP, SR
111
Return from Subroutine (RTS)
Trap (TRAP)
SSP, SR
Trap on Overflow (TRAPV)
SSP, SR
Unlink (UNLK)
100
VI-7
- - - - - - .... _ - -
-
PC,SP
-----
SP
•
Condition Codes or Status Register. A selected set of
instructions may reference the status register by means of
the effective address field. These are:
ANDI toCCR
ANDI toSR
EORI toCCR
EORI to SR
ORI toCCR
ORI toSR
EFFECTIVE ADDRESS ENCODING SUMMARY
Table 4 is a summary of the effective addressing modes
discussed in the previous paragraphs.
address and data manipulation. Data move instructions
allow byte, word, and long word operands to be transferred
from memory to memory, memory to register, register to
memory, and register to register. Address move instructions
allow word and long word operand transfers and ensure
that only legal address manipulations are executed. In
addition to the general move instruction there are several
special data movement instructions: move multiple
registers (MOVEM), move peripheral data (MDVEP),
exchange registers (EXG), load effective address (lEA),
push effective address (PEA), link stack (LINK), unlink stack
(UNlK), and move quick (MOVEa). Table 6 is a summary of
the data movement operations.
DATA MOVEMENT OPERATIONS
Table 6
IMPLICIT REFERENCE
Some instructions make implicit reference to the program
counter (PC), the system stack pointer (SP), the supervisor
stack pointer (SSP), the user stack pointer (USP), or the
status register (SR). Table 5 provides a list of these
instructions and the registers implied.
SYSTEM STACK
The system stack is used implicitly by many instructions;
user stacks and queues may be created and maintained
through the addressing modes. Address register seven (A7)
is the system stack pointer (SP). The system stack pointer is
either the supervisor stack pointer (SSP) or the user stack
pointer (USP), depending on the state of the S-bit in the
status register. If the S-bit indicates supervisor state, SSP is
the active system stack pointer, and the USP cannot be
referenced as an address register. Ifthe S-bit indicates user
state, the USP is the active system stack pointer, and the
SSP cannot be referenced. Each system stack fills from high
memory to low memory.
INSTRUCTION SET SUMMARY
The following paragraphs contain an overview of the form
and structure of the MK68000 instruction set. The
instructions form a set of tools that include all the machine
functions to perform the following operations:
Data Movement
Integer Arithmetic
logical
Shift and Rotate
Bit Manipulation
Binary Coded Decimal
Program Control
System Control
Instruction
Operand Size
Operation
EXG
32
Rx- Ry
lEA
32
EA-An
LINK
-
An -SP@SP-An
SP+d -SP
MOVE
8,16,32
(EA)s- EAd
MOVEM
16,32
(EA)-An, On
An, Dn- EA
MOVEP
16,32
(EA)- On
Dn-EA
MOVEa
8
#xxx- On
PEA
32
EA-SP@-
SWAP
32
Dn[31 :16]-Dn[15:0]
UNlK
-
An-Sp
SP@+-An
NOTES:
s = source
d = destination
[ ] = bit numbers
@ - = indirect with predecrement
@ + = indirect with postincrement
INTEGER ARITHMETIC OPERATIONS
The complete range of instruction capabilities combined
with the flexible addressing modes described previously
provide a very flexible base for program development.
DATA MOVEMENT OPERATIONS
The basic method of data acquisition (transfer and storage)
is provided by the move (MOVE) instruction. The move
instruction and the effective addressing modes allow both
VI-8
The arithmetic operations include the four basic operations
of add (ADD), subtract (SUB), multiply (MUl), and divide
(DIV) as well as arithmetic compare (CMP), clear (ClR), and
negate (NEG). The add and subtract instructions are
available for both address and data operations, with data
operations accepting all operand sizes. Address operations
are limited to legal address size operands (160r 32 bits).
Data, address, and memory compare operations are also
available. The clear and negate instructions maybe used on
all sizes of data operands.
The multiply and divide operations are available for signed
and unsigned operands using word mUltiply to produce a
long word product, and a long word dividend with word
divisor to produce a word quotient with a word remainder.
LOGICAL OPERATIONS
Logical operation instructions AND, OR, EOR, and NOT are
available for all sizes of integer data operands. A similar set
of immediate instructions (ANDI. ORI, and EORI) provides
these logical operations with all sizes of immediate data.
Table 8 is a summary of the logical operations.
Multiprecision and mixed size arithmetic can be accomplished using a set of extended instructions. These
instructions are: add extended (ADDX), subtract extended
(SUBX), sign extend (EXT), and negate binary with extend
(NEGX).
LOGICAL OPERATIONS
Table 8
A test operand (TST) instruction that will set the condition
codes as a result of a compare of the operand with zero is
also available. Test and set (TAS) is a synchronization
instruction useful in multiprocessor systems. Table 7 is a
summary of the integer arithmetic operations.
INTEGER ARITHMETIC OPERATIONS
Table 7
Instruction
Operand Size
Operation
8,16,32
16,32
On + (EA)- On
(EA) + On - EA
(EA) + #xxx - EA
An + (EA)-An
ADDX
8,16,32
16,32
Dx+Dy+X-Dx
Ax@ - Ay@ - + X - Ax@
CLR
8,16,32
0- EA
ADD
8,16,32
CMP
16,32
Instruction
Operand Size
Operation
AND
8,16,32
DnA(EA)- On
(EA)ADn - EA
(EA)A#xxx - EA
OR
8,16,32
On v (EA) - On
(EA) v On - EA
(EA) v #xxx - EA
EOR
8,16,32
NOT
8,16,32
(EA) Ell Dy- EA
(EA) Ell #xxx - EA
~(EA)-
EA
NOTE: - = invert
SHIFT AND ROTATE OPERATIONS
Shift operations in both directions are provided by the
arithmetic instructions ASR and ASL and logical shift
instructions LSR and LSL. The rotate instructions (with and
without extend) available are ROXR, ROXL, ROR, and ROL.
All shift and rotate operations can be performed in either
registers or memory. Register shifts and rotates support all
operand sizes and allow a shift count specified in the
instruction of one to eight bits, or 0 to 63 specified in a data
register.
On -(EA)
(EA)- #xxx
Ax@ + -Ay@ +
An - (EA)
DIVS
32"'" 16
Dn/(EA)- On
DIVU
32"'" 16
Dn/(EA)- On
EXT
8-16
16- 32
(Dn)8 - Dn16
(On), 6 - Dn32
MULS
16* 16 - 32
Dn* (EA)- On
MULU
16* 16 - 32
Dn* (EA)- On
Table 9 is a summary of the shift and rotate operations.
NEG
8,16,32
O-(EA)- EA
BIT MANIPULATION OPERATIONS
NEGX
8,16,32
0- (EA) - X - EA
8,16,32
16,32
On - (EA) - On
(EA)- On -EA
(EA) - #xxx - EA
An - (EA) - An
SUBX
8,16,32
Dx-Dy-X-Dx
Ax@ - - Ay@ - - X - Ax@
TAS
8
(EA) - 0, 1 - EA[7]
TST
8,16,32
(EA)-O
SUB
NOTE: [
1=
Memory shifts and rotates are for word operands only and
allow only single-bit shifts or rotates.
Bit manipulation operations are accomplished using the
following instructions: bittest (BTST), bittest and set (ESET),
bit test and clear (BCLR), and bit test and change (BCHG).
Table 10 is a summary of the bit manipulation operations.
(Bit 2 of the status register is Z.)
BINARY CODED DECIMAL OPERATIONS
Multiprecision arithmetic operations on binary coded
decimal numbers are accompolished using the following
instructions: add decimal with extend (ABCD), subtract
decimal with extend (SBCD), and negate decimal with
extend (NBCD). Table 11 is a summary of the binary coded
decimal operations.
bit number
VI-9
..
The conditional instructions provide setting and branching
for the following conditions:
SHIFT AND ROTATE OPERATIONS
Table 9
Instruction ,.
Operand
Size
Operation
ASL
8.16.32
~O
ASR
8.16.32
LSL
8.16.32
LSR
8.16.32
ROL
8.16.32
ROR
8.16.32
ROXL
8.16.32
ROXR
8.16.32
CC - carry clear
CS - carry set
EQ - equal
F - never true
GE - greater or equal
GT - greater than
HI - high
LE - less or equal
~
~O
O~
PROGRAM CONTROL OPERATIONS
Table 12
~
~
[D-,I..
HXh
~X H
~II~I ci
Instruction
Operation
Conditional
Branch conditionally (14 conditions)
Bee
8- and 16-bit displacement
Test condition. decrement. and branch
DBee
16-bit displacement
Set byte conditionally (16 conditions)
See
BIT MANIPULATION OPERATIONS
Table 10
.Unconditional
BRA
Branch always
8- and 16-bit displacement
BSR
Branch to subroutine
8- and 16-bit displacement
JMP
Jump
JSR
Jump to subroutine
Instruction
Operand Size
Operation
BTST
8.32
- bit of (EA) - Z
BSET
8.32
- bit of(EA)~ Z
1 - bit of EA
BCLR
8.32
- bit of (EA)- Z
O-bitofEA
8.32
- bit of (EA) - Z
- bit of (EA) - bit of EA
BCHG
, LS - low or same
LT - less than
MI- minus
NE - not equal
PL - plus
T - always true
VC - no overflow
VS - overflow
Retums
RTR
RTS
Return and restore condition codes
Return from subroutine
SYSTEM CONTROL OPERATIONS
BINARY CODED DECIMAL OPERATIONS
System control operations are accomplished by using
privileged instructions. trap generating instructions. and
instructions that use or modify the status register. These
instructions are summarized in Table 13.
Table 11
Operand
Size
Operation
ABCD
8
DXlO+DY10+X - Dx
Ax@- 10+Ay@ - 10+X - Ax@
SBCD
8
DX10'- DylO - X - Ox
Ax@-10-Ay@-10-X-Ax@
NBCD
8
0- (EA)lO-X - EA
Instruction
SIGNAL AND BUS OPERATION DESCRIPTION
The following paragraphs contain a brief description of the
input and output signals. A discussion of bus operation
during the various machine cyCles and operations is also
given.
SIGNAL DESCRIPTION
PROGRAM CONTROL OPERATIONS
Program control operations are accomplished using a series
of conditional' and un~onditional bra'nch instructions and
return instructions. These instructions are summarized in
Table 1Z.
The input and output signals can be functionally organized
into the groups shown in Figure 5. The following
paragraphs provide a brief description of the signals and
also a reference (if applicable) to other paragraphs that
contain more detail about the function being performed.
ADDRESS BUS .(A1 THROUGH A23). This 23-bit.
unidirectional. three-state. bus is. capable of addressing 8
megawords of data. It provides the address for bus
operation during all cyCles except interrupt cycles. During
interrupt cycles. address lines A 1. A2. and. A3 provide
VI-10
information about what level interrupt is being serviced
while address lines A4 through A23 are all set to a logic
high.
Address Strobe (AS). This signal indicates that there is a
valid address on the address bus.
DATA BUS (DO THROUGH 015). This 16-bit bidirectional,
three-state bus is the general purpose data path. It can
transfer and accept data in either word or byte length.
During an interrupt acknowledge cycle, the external device
supplies the vector number on data lines DO-D7.
Read/Write (R/W). This signal defines the data bus
transfer as a read or write cycle. The R/W signal also works
in conjunction with the upper and lower data strobes as
explained in the following paragraph.
Upper And Lower Data Strobes (UDS, LOS). These
signals control the data on the data bus, as shown in Table
14. When the R/W line is high, the processor will read from
the data bus as indicated. When the R/W line is low, the
processor will write to the data bus as shown.
ASYNCHRONOUS BUS CONTROL. Asynchronous data
transfers are handled using the following control signals:
address strobe, read/write, upper and lower data strobes,
and data transfer acknowledge. These signals are explained
in the following paragraphs.
DATA STROBE CONTROL OF DATA BUS
Table 14
SYSTEM CONTROL OPERATIONS
Table 13
Instruction
Privileged
RESET
RTE
STOP
ORI to SR
MOVE USP
ANDI to SR
EORI to SR
MOVE EA to SR
Operation
Reset external devices
Return from exception
Stop program execution
Logical OR to status register
Move user stack pointer
Logical AND to status register
Logical EOR to status register
Load new status register
Trap Generating
TRAP
rap
TRAPV
rap on overflow
CHK
Check register against bounds
Status Register
ANDI to CCR
EORI to CCR
MOVE EA to CCR
ORI to CCR
MOVE SR to EA
Logical AND to condition codes
Logical EOR to condition codes
Load new condition codes
Logical OR to condition codes
Store status register
INPUT AND OUTPUT SIGNALS
Figure 5
V (21
cc
elK
R/W
High
High
Low
High
08-015
00-07
-
No valid data
No valid data
Low
High
Valid data bits
8-15
Valid data bits
0-7
Low
High
No valid data
Valid data bits
0-7
No valid data
Low
High
High
Valid data bits
8-15
Low
Low
Low
Valid data bits
8-15
Valid data bits
0-7
High
Low
Low
Valid data bits
0-7*
Valid data bits
0-7
Low
High
Low
Valid data bits
8-15
Valid data bits
8-15*
*These conditions are a result of current implementation
and may not appear on future devices.
Data Transfer Acknowledge (DTACK). This input
indicates that the data transfer is completed. When the
processor recognizes DTACK during a read cycle, data is
latched and the bus cycle terminated. When DTACK is
recognized during a write cycle, the bus cycle is terminated.
~
ADDRESS BUS
GND(2)
UDS LOS
l
A-
DATA BUS
MK68000
MICROPROCESSOR
~
V
An active transition of data transfer acknowledge, DTACK,
indicates the termination of a data transfer on the bus.
AS
Riw
FCO
UOS
Fe'
lOS
FC2
6'fACi(
,
iiR
ASYNCHRONOUS
}
PROCESSOR. {
BUS
CONTROL
STATUS
6800
{
PERIPHERAL
CONTROL
SYSTEM {
CONTROL,
...
vm
BO
BGAcK
iffi!ii
iPLO
RESET
IPl1
HALT
If the system must run at a maximum rate determined by
RAM access times, the relationship between the times at
which DTACK and DATA are sampled are important.
.ID
}
BUS ARBITRATION
CONTROL
}
INT'RRU",
CONTROL
All control and data lines are sampled during the
MK68000's clock high time. The clock is internally buffered,
which results in some slight differences in the sampling and
recognition of various signals. The DTACK signal. like other
VI-11
II
control signals, is internally synchronized to allow for valid
operation in an asynchrono!Jssystem.lfthe required setup
time (#47) is met during 54, DTACK will be recognized
during 55 and 56, and data will be captured during 56. The
data mUilt meet the required setup time (#2.7).
If an asynchronous control signal does not meet the
required setup time, it is possible that it may not be
recognized during that cycle. Because ofthis, asynchronous
systems must not allow DTACK to precede data by more
than parameter #31.
Asserting DTACK (or BERR) on the rising edge of a clock
(such as S4)afterthe assertion of address strobe wi II allow a n
MK68000 system to run at its maximum bus rate. If setup
times #27 and #47 are guaranteed, #31 may be ignored.
BUS ARBITRATION CONTROL. These three signals
form a bus arbitration circuitto determine which device will
be the bus master device.
Bus Request (BR). This input is write ORed with all other
devices that could be bus masters. This input indicates to
.the processor that some other device desires to become the
bus master.
Bus Grant (BG). This output indicates to all other potential
bus master devices that the processor will release bus
control at the end of the current bus cycle.
Bus Grant Acknowledge (BGACK). This input indicates
that some other device has become the bus master. This
signal cannot be asserted until the following four conditions
are met
1. a bus grant has been received
2. address strobe is inactive which indicates that the
microprocessor is not using the bus
3. data transfer acknowledge is inactive which indicates
that either memory or the peripherals are not using the
bus
4. bus grant acknowledge is inactive which indicates that
no other device is still claiming bus mastership
INTERRUPT CONTROL (IPLO, IPL 1, IPL2). These input
pins indicate the encoded priority level of the device
requesting an interrupt. Level seven is the highest priority
while level zero indicates that no interrupts are requested.
The least significant bit is given in IPLO and the most
significant bit is contained in IPL2.
1. nonresponding devices
2. interrupt vector number acquisition failure
3. illegal access request as determined by a memory
management unit
4. other application dependent errors.
The bus error signal interacts with the halt signal to
determine if exception processing should be performed or
the current bus cycle should be retried.
Refer to BUS ERROR AND HALT OPERATION paragraph for
additional information about the interaction ofthe bus error
and halt signals.
Reset (RESET). This bidirectional signal line acts to reset
(initiate a system initialization sequence) the processor in
response to an external reset signal. An internally
generated reset (result of RESET instruction) causes all
external devices to be reset and the internal state of the
processor is not affected. A total system reset (processor
and external devices) is the result of external halt and reset
signals applied at the same time. Refer to RESET
OPERATION paragraph for additional information about
reset operation .
Halt (HALT). When this bidirectional line is driven by an
external device, it will cause the processor to stop at the
completion of the current bus cycle. When the processor
has been halted using this input, all control signals are
inactive and all three-state lines are put in their highimpedance state. Refer to BUS ERROR AND HALT
OPERATION paragraph for additional information about the
interaction between the halt and bus error signals.
When the processor has stopped executing instructions,
such as in a double bus fault condition, the halt line is driven
by the processor to indicate to external devices that the
processor has stopped.
6800 PERIPHERAL CONTROL. These Control signals are
used to allow the interfacing of synchronous 6800
peripheral devices with the async!1ronous MK6.8000.
These signals are explained in the following paragraphs.
Enable (E). This Signal is the standard enable signal
common to all 6800 type peripheral devices. The period for
this output is ten MK68000 clock periods (six clocks low;
four clocks high).
SYSTEM CONTROL. The system control inputs are used
to either reset or halt the processor and to indicate to the
processor that bus errors have occurred. The three system
control inputs are explained in the following paragraphs.
Valid Peripheral Address (VPA). This input indicates that
the device or region addressed is a 6800 family device and
that data transfer should be synchronized with the enable
(E) signal. This input also indicates thatthe processor should
use automatic vectoring for an interrupt. Refer to
INTERFACE WITH 6800 PERIPHERALS.
Bus Error (BERR). This input informs the processor that
there is a problem with the cycle currently being executed.
Problems may be a result of:
Valid Memory Address (VMA). This output is used to
indicate to 6800 peripheral devices that there is a valid
address on the address bus and the processor is
synchronized to enable. This signal only responds to a valid
peripheral address (VPA) input which indicates that the
peripheral is a 6800 family device.
FUNCTION CODE OUTPUTS
Table 15
FC2
FC1
FCO
Cycle Type
Low
Low
Low
Low
High
High
High
High
Low
Low
High
High
Low
Low
High
High
Low
High
Low
High
Low
High
Low
High
(Undefined, Reserved)
User Data
User Program
(Undefined, Reserved)
(Undefined, Reserved)
Supervisor Data
Supervisor Program
Interrupt Acknowledge
PROCESSOR STATUS (FCO, FC1, FC2), These function
code outputs indicate the state (user or supervisor) and the
cycle type currently being executed, as shown in Table 15.
The information indicated by the function code outputs is
valid whenever address strobe (AS) is active.
CLOCK (CLK). The clock input is a TIL compatible signal
that is internally buffered for development of the internal
clocks needed by the processor. The clock input shall be a
constant frequency.
SIGNAL SUMMARY. Table 16 is a summary of all the
signals discussed in the previous paragraphs.
SIGNAL SUMMARY
Table 16
Signal Name
Mnemonic
Input/Output
Active State
Three
State
Address Bus
A1-A23
output
high
yes
Data Bus
00-015
input/output
high
yes
AS
output
low
yes
RIW
output
read-high
write-low
yes
UDS, [jj'S'
output
low
yes
DTACK
input
low
no
Bus Request
BR
input
low
no
Bus Grant
BG
output
low
no
BGACK
input
low
no
IPLO, IPL1, IPL2
input
low
no
Bus Error
BERR
input
low
no
Reset
RESET
input/output
low
no*
Halt
HALT
input/output
low
no*
E
output
high
no
Valid Memory Address
VMA
output
low
yes
Valid Peripheral Address
VPA
input
low
no
FCO,FC1,FC2
output
high
yes
Clock
CLK
input
high
no
Power Input
Vee
input
-
Ground
GND
input
-
Address Strobe
Read/Write
Upper and Lower Data Strobes
Data Transfer Acknowledge
Bus Grant Acknowledge
Interrupt Priority Level
Enable
Function Code Output
* open drain
VI-13
-
II
WORD READ CYCLE FLOW CHART
BYTE READ CYCLE FLOW CHART
Figure 6
Figure 7
BUS MASTER
SLAVE
SLAVE
BUS MASTER
Address Device
Address Device
1) Set R/W to Read
2) Place Address on A 1-A23
3) Place Function Code on FCO-FC2
4) Assert Address Strobe (n)
5) Assert Upper Data Strobe (UOS) and Lower
Data Strobe (Ci5~)
1) Set R/W to Read
2) Place Address on A 1-A23
3) Place Function Code on FCO-FC2
4) Assert Address Strobe (n)
5) Assert Upper Data Strobe (UDS) or Lower
Data Strobe (Li5S) (based on AO)
I
Input Data
Input Data
1) Decode Address
2) Place Data on 00-015
3) Assert Data Transfer
Acknowledge (OTACK)
1) Decode Address
2) Place Data on 00-07 or OB-D15
(based on ~ or IDS)
3) Assert Data Transfer Acknowledge
(OTACK)
I
Acquire Data
Acquire Data
1) Latch Ollta
2) Negate ~ and IDS
3) NegateA§
1 ) Latch Data
2) Negate ~ or
3) Negate AS
Li5S
Terminate Cycle
Terminate Cycle
1) Remove Data from 00-015
2) Negate OTACK
1) Remove Data from 00-07 or OB-015
2) Negate OtACK
Start Next Cycle
Start Next Cycle
BUS OPERATION
The following paragraphs explain control signal and bus
operation during data transfer operations, bus arbitration,
bus error and halt conditions, and reset operation.
DATA TRANSFER OPERATIONS. Transfer of data
between devices involves the following leads:
• Address Bus A 1 through A23
• Data Bus 00 through 015
• Control Signals
The address and data buses are separate parallel buses
used to transfer data using an asynchronous bus structure.
In all cycles, the bus master assumes responsibility for
deskewing all signals it issues at both the start and end of a
cycle. In addition, the bus master is responsible for
deskewing the acknowledge and data signals from the slave
device.
The following paragraphs explain the read, write, and read-
modify-write cycles. The indivisible read-modify-write cycle
is the method used by the MK68000 for interlocked
multiprocessor communications.
NOTE
The terms assertion and negation will be used extensively.
This is done to avoid confusion when dealing with a mixture
of "active-low" and "active-high" signals. The term assert
or assertion is used to indicate that a signal is active or true
independent of whether that voltage is low or high. The
term negate or negation is used to indicate that a signal is
inactive or false.
Read Cycle. During a read cycle, the processor receives
data from memory or a peripheral device. The processor
reads bytes of data in all cases. If the instruction specifies a
word (or double word) operation, the processor reads both
bytes. When the instruction specifies byte operation, the
processor uses an internal AD bit to determine which byte to
read and then issues the data strobe required for that byte.
For byte operations, when the AD bit equals zero, the upper
data strobe is issued. When the AD bit equals one, the lower
VI-14
READ AND WRITE CYCLE TIMING DIAGRAM
Figure 8
50 51 5253545556 57 50 515253 54 55 5657 50 S1 S2 S3 S4 w
w
w S5 56 S7
H
A1-A23
A5
\
/
UDS
\
\
/
/
lDS
\
\
DTACK
D8-D15
DO-D7
\
!
(
(
)
~
/
/
\
\
,
I
\
\
\
/
R/iiii'
FCO-2
w
~~-
ClK
,
I
!
)
)
)
X
X
~-------READ- -- - -- -~- - - - -WRITE - -
>--
r
\
(
>->--
c=--~--.--
>---
-.rc- ---- - -SLOW READ - - - - - - ---.,
WORD AND BYTE READ CYCLE TIMING DIAGRAM
Figure 9
50 S1 52 S3 S4 S5 S6 S7 505152 S3 S4 S5 S6 S7 SO S1 S2 S3 S4S5 S6 S7
~____~/~__~\======~__~\
r--
L -__~
~____---.J/
/
\
/
/
'--________I
\'--===:'
~==~)~------------~('----~>----
FCO-2
~==~==~)~=~~~~)======~=:x
X~______~X~_____----J>'Intemal Signal Only
~-- WORD READ ----~--ODD BYTE READ---~ --EVEN BYTE READ-~
data strobe is issued. When the data is received, the
processor correctly positions it internally.
A word read cycle flowchart isgiven in Figure 6. A byte read
cycle flow chart is given in Figure 7. Read cycle timing is
given in Figure 8 and Figure 9 details word and byte read
cycle operation.
Write Cycle. During a write cycle, the processor sends data
to memory or a peripheral device. The processor writes
bytes of data in all cases. If the instruction specifies a word
operation, the processor writes both bytes. When the
instruction specifies a byte operation, the processor uses an
internal AO bit to determine which byte to write and then
issues the data strobe required for that byte. For byte
operations, when the AO bit equals zero, the upper data
strobe is issued. When the AO bit equals one, the lower data
strobe is issued. A word write cycle flow chart is given in
Figure 10. A byte write cycle flowchart isgiven in Figure 11.
Write cycle timing is given.in Figure 8 and Figure 12 details
word and byte write cycle operation.
Read-Modify-Write Cycle. The read-modify-write cycle
performs a read, modifies the data in the arithmetic-logic
unit, and writes the data back to the same address. In the
MK68000 this cycle is indivisible in that the address strobe
is asserted throughout the entire cycle. The test and set
(TAS) instruction uses this cycle to provide meaningful
communication between processors in a multiple processor
environment. This instruction is the only instruction that
uses the read-modify-write cycles and since the test and set
instruction only operates on bytes, all read-modify-write
VI-15
•
WORD WRITE CYCLE FLOW CHART
BYTE WRITE CYCLE FLOW CHART
Figure 10
Figure 11
BUS MASTER
SLAVE
BUS MASTER
Address Device
SLAVE
Address Device
1) Place Function Code on FCO- FC2
2) Place Address on A 1-A23
3) Assart Address Strobe (A§)
4) Set R/W to Write
5) Place Data on 00-015
6) Assart Upper Data Strobe (UDS) and
Lower Data Strobe (LOS)
1) Place Function Code on FCO-FC2
2) Place Address on A 1-A23
3) Assert Address Strobe (Mi)
4) Set R/W to Write
5) Place Data on 00-07 or 08-015 (according
toAO)
6) Assert Upper Data Strobe (UOS) or Lower
Data Strobe (LOS) (based on AO)
,
I
Input Data
Input Data
1 ) Decode Address
2) Store Data on 00-015
3) Assert Data Transfer Acknowledge
(OTACK)
,
1 ) Decode Address
2) Store Data on 00-07 if LOS is asserted
Store Data on 08-015 if 0i5S is asserted
3) Assart Data Transfer Acknowledge
(OTACK)'
,
Terminate Output Transfer
Terminate Output Transfer
1) Negate 0i5S and LOS
2) NegateA§
3) Remove Data from 00-015
4) Set R/W to Read
1) Negate UOS and LOS
2) Negate AS
3) Remove Data from 00-07 or 08-015
4) Set R/W to Read
I
I
Terminate Cycle
~tart
,
Terminate Cycle
1) Negate OTACK
1) Negate OTACK
I
I
Next Cycle
Start Next Cycle
WORD AND BYTE WRITE CYCLE TIMING DIAGRAM
Figure 12
SO S1 S2 S3 S4 S5 S6 S7 SO S1 S2 S3 S4 S5 S6 S7 SO S1 S2 S3 S4S5 S6 S7
CLK
AO"
AS
~
\
\
UOS
LOs
R/W
OTACK
08-015'
00-07
FCO-2
,
===>--<
/
/
I
\
\
,
I
F\
1\
I
===>--<
)
)
)
X
X
:x
)
I
I
\
/
1\
I
,
I
r
>
>
>
"Intemal Signal Only
rc-- --
WORD WRITE - -- --~- - ,ODD 8YTE WRITE-----+----EVEN BYrE WRITE -- --~
VI-16
READ-MODIFY-WRITE CYCLE FLOW CHART
Figure 13
BUS MASTER
Address Device
SLAVE
1) Place Address on A 1-A23
2) Set R/Vii to Read
3) Assert Address Strobe (AS)
4) Assert Upper Data Strobe (lJi5!:) or Lower
Data Strobe (LOS) I
~--------------------~,
Input Data
1) Decode Address
2) Place Data on 00-07 or 08-015
3) Assert Data Transfer Acknowledge
(DTACK)
f
Acquire Data
1 ) Latch Data
2) Negate UDS or LOS
3) Start Data Modification
)
Terminate Cycle
1) Remove Data from 00-07 or 08-015
2) Negate DTACK
Start Output Transfer
1) Set R/Vii to Write
2) Place Data on 00-07 or 08-015
3) Assert Upper Data Strobe (UDS) or Lower
Data Strobe (LOS) LI_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- - ,
,
Input Data
1) Store Data on 00-07 or 08-015
2) Assert Data Transfer Acknowledge
(DTACK)
f
Terminate Output Transfer
1)
2)
3)
4)
Negate lJi5!: or LOS
Negate AS
Remove Data from 00-07 or 08-015
Set R/Vii to Read
Terminate Cycle
1) Negate DTACK
I
f
Start Next Cycle
cycles are byte operations. A read-modify-write cycle flow
chart is given in Figure 13 and a timing diagram is given in
Figure 14.
2. Receiving a grant that the bus is available at the end of
the current cycle.
3. Acknowledging that mastership has been assumed.
BUS ARBITRATION. Bus arbitration is a technique used
by master-type devices to request, be granted, and
acknowledge bus mastership. In its simplest form, it
consists of:
Figure 15 is a flow chart showing the detail involved in a
request from a single device. Figure 16 is a timing diagram
for the same operations. This technique allows processing
of bus requests during data transfer cycles.
1. Asserting a bus mastership request.
The timing diagram shows that the bus request is negated
VI-17
II
READ-MODIFY-WRITE CYCLE TIMING DIAGRAM
Figure 14
SO S1 S2 S3 S4 S5 S6
S7 S8 S9 S10S11S12S13S14S15S16S17S18S19
ClK
H
/
A1-A23
\
\
AS
UOS or lOS
\
08-015
/
\
OTACK
FCO-2
'----.J
/
R/W
=x
(
,,-
\
}--
)
>C
1-11----- -- -------INOIVISIBlE CYCLE at the time that an acknowledge is asserted. This type of
operation would be true for a system consisting of the
processor and one device capable of bus mastership. In
systems having a number of devices capable of bus
mastership, the bus request line from each device is wire
ORed to the processor. In this system, it is easy to see that
there could be more than one bus request being made. The
timing diagram shows that the bus grant signal is negated a
few clock cycles after the transition of the acknowledge
(BGACK) signal.
- - -- -- - - ---~
BUS ARBITRATION CYCLE FLOW-CHART
Figure 15
PROCESSOR
Request the Bus
1) Assert Bus Request (im)
f
Grant Bus Arbitration
1 ) Assert Bus Grant (BG)
I
However, if the bus requests are still pending, the processor
will assert another bus grant within a few clock cycles after
it was negated. This additiona I assertion of bus gra nt allows
external arbitration circuitry to select the next bus master
before the current bus master has completed its
requirements. The following paragraphs provide additional
information about the three steps in the arbitration process.
Requesting the Bus. External devices capable of becoming
bus masters request the bus by asserting the bus request
(BR) signal. This is a wire ORed signal (although it need not
be constructed from open collector devices) that indicates to
the processor that some external device requires control of
the external bus. The processor is effectively at a lower bus
priority level than the external device and will relinquish the
bus after it has completed the last bus cycle it has started.
t
Acknowledge Bus Mastership
1 ) Extemal arbitration determines next bus
master
2) Next bus master waits for current cycle to
complete
3) Next bus master asserts Bus Grant
Acknowledge (~) to become new
master
4) Bus master negates im
I
f
Terminate Arbitration
1) Negate Irn (and wait for ~ to be
• negated)
t
Operate as Bus Master
1) Perform Date Transfers (Read and Write
cycles) according to the same rules the pro-
When no acknowledge is received before the bus request
signal goes inactive, the processor will continue processing
when it detects that the bus request is inactive. This allows
ordinary processing to continue if the arbitration circuitry
responded to noise inadvertently.
Receiving the Bus Grant. The processor asserts bus grant
(BG) as soon as possible. Normally this is immediately after
internal synchronization. The only exception to this occurs
when the processor has made an internal decision to
execute the next bus cycle but has not progressed far
enough into the cycle to have asserted the address strobe
(AS) signal. In this case, bus grant will not be asserted until
one clock after address strobe is asserted to indicate to
external devices that a bus cycle is being executed.
REQUESTING DEVICE
Ralease Bus Mastership
1)Nagate~
t
Re-Arbitrate or Resume Processor
Operation
The bus grant signal may be routed through a daisy-chained
network or through a specific priority-encoded network. The
processor is not affected by the external method of
arbitration as long as the protocol is obeyed.
Acknowledgement of Mastership. Upon receiving a bus
VI-18
BUS ARBITRATION CYCLE TIMING DIAGRAM
Figure 16
CLK
A1-A23
AS
LDSIUDS
R/W
~
00-015
FCO-2
BR
\
~
~
/
\
~--------~\~----~/
/
\\--------
PROCESSOR --~--DMA DEVICE-~-- -- -PROCESSOR - -- - ~ - - DMA DEVICE - ---
grant, the requesting device waits until address strobe, data
transfer acknowledge, and bus grant acknowledge are
negated before issuing its own BGACK. The negation of the
address strobe indicates that the previous master has
completed its cycle, the negation of bus grant acknowledge
indicates that the previous master has released the bus.
(While address strobe is asserted no device is allowed to
"break into" a cycle.) The negation of data transfer
acknowledge indicates the previous slave has terminated
its connection to the previous master. Note that in some
applications data transfer acknowledge might not enter into
this function. General purpose devices would then be
connected such that they were only dependent on address
strobe. When bus grant acknowledge is issued the device is
bus master until it negates bus grant acknowledge. Bus
grant acknowledge should not be negated until after the bus
cycle(s) is (are) completed. Bus mastership is terminated at
the negation of bus grant acknowledge.
STATE DIAGRAM OF MK68000 BUS
ARBITRATION UNIT
Figure 17
RA
The bus request from the granted device should be dropped
when bus grant acknowledge is asserted. If bus request is
still asserted after bus grant acknowledge is negated, the
processor performs another arbitration sequence and
issues another bus grant. Note that the processor does not
perform any external bus cycles before it re-asserts bus
grant.
BUS ARBITRATION CONTROL. The bus arbitration
control unit in the MK68000 is implemented with a finite
state machine. A state diagram of this machine is shown in
Figure 17. All asynchronous signals to the MK68000 are
synchronized before being used internally. This synchronization is accomplished in a maximum of one cycle of the
system clock, assuming that the asynchronous input setup
time (#47) has been met. The input signal is sampled on the
falling edge of the clock and is valid internally after the next
falling edge.
As shown in Figure 17, input Signals labeled R and A are
internally synchronized on the bus request and bus grant
R = Bus Request Intamal
A = Bus Grant Acknowledge Internal
G = Bus Grant
T = Three-state Control to Bus Control logic
X = Don't Care
'State machine will not change state if bus is in SO. Refer to
BUS ARBITRATION CONTROL for additional information.
acknowledge pins respectively. The bus grant output is
labeled G and the internal three-state control signal T.lfTis
true, the address, data, and control buses are placed in a
high-impedance state when AS is negated. All signals are
shown in positive logic (active high) regardless of their true
active voltage level.
VI-19
------------
..
BUS ARBITRATION DURING PROCESSOR BUS CYCLE
Figure 18
Bus three s t a t e d - - - - - - - - I Bus released from three state and
Processor starts next bux cycle
BGasserted------~
BR valid internal
BGACK negated internal
BGACK sampled
BRsampled~
BGACK negated
BR asserted - - . •
ClK
so S1 S2 S3 S4 S5 S6 S7
BR----""'"
iiG
so S1 S2 S3 S4 S5 S6 S7 SO S1
I
=========~~~~~~~'::~==~_---,I
'--___---'1
'
...._-----'
~-~----------~~------~
~--------------,-~,~----~
(
OTACK _______
00-015
..
~
---'----'~~====~~--------------~__--------_;~~~~=====
____
(
PROCESSOR
-I ..
ALTERNATE BUS MASTER
BUS ARBITRATION WITH BUS INACTIVE
Figure 19
Bus released from three state and processor starts next bus c y c l e - - - - - - - - - - - - - ,
BGACK n e g a t e d - - - - - - - - - -_ _ _ _ _ _ _ _ _ _ _ _-,
BG asserted and bus three stated - - - - - - - - ,
BR valid internal----------..
BRassertedl--------~
CLK
SO S1 S2 S3 S4 S5 S6 S7
SO S1 S2 S3 S4
I
BR - - - - - - - - - - - - ,
' I
iiG
BGACK
\
/
'-----'
1
A1-~3 :~~~~======~~)::::::::::~======================~~(~~====
AS
~
,\-_ _-oJ
UOS-----,
/r----------,\~~----------------~~
lOS
I
,
~
J'--________________________)r---------:------------('-_____
R/W--------------'-___________
FCO-FC2
~----
OTACK
--------'----1
00-015
-----::::::1(:=~====)t~::::~------~::~~::~~::------_;,~~~;_
_I :ROCESSOR_
.. PROCESSOR _I.. BUS INACTIVE _I.. ALTERNATE BUS MASTER
VI-20
State changes (valid outputs) occur on the next rising edge
after the internal signal is valid.
A timing diagram of the bus arbitration sequence during a
processor bus cycle is shown in Figure 18. The bus
arbitration sequence while the bus is inactive (i.e.,
executing internal operations such as a multiply instruction)
is shown in Figure 19.
If a bus request is made at a time when the MPU has already
begun a bus cycle but AS has not been asserted (bus state
SO), BG will not be asserted on the next rising edge. Instead,
BG will be delayed until the second rising edge following its
internal assertion.
BUS ERROR AND HALT OPERATION. In a bus
architecture that requires a handshake from an external
device, the possibility exists that the handshake might not
occur. Since different systems will require a different
maximum response time, a bus error input is provided.
External circuitry must be used to determine the duration
between address strobe and data transfer acknowledge
before issuing a bus error signal. When a bus error signal is
received, the processor has two options: initiate a bus error
exception sequence or try running the bus cycle again.
Exception Sequence. When the bus error signal is
asserted, the current bus cycle is terminated. If BERR is
asserted before the falling edge of 54, AS will be negated in
S7 in either a read or write cycle. As long as BERR remains
asserted, the data and address buses will be in the highimpedance state. When the BERR is negated, the processor
will begin stacking for exception processing. The bus error
exception sequence is entered when the processor receives
a bus error signal and the halt pin is inactive. Figure 20 is a
timing diagram for the exception sequence. The sequence
is composed of the following elements:
1. Stacking the program counter and status register
BUS ERROR TIMING DIAGRAM
Figure 20
ClK
A1-A23
==---~::;----------------r=!.---.J
~
\
\
\
~
UOS
~
II
\
\
\
/
R/W
\
OTACK
08-015
00-07
FCO-2
BEJiR
~;;;j(~~~~~~~~~~~~;;j'
~=====
=x
(
~~~===
~===========\\--------~~
HALT
INITIATE
RESPONSE
BUS ERROR
INITIATE BUS
I-ilFiEAOJ+c - ---FAiLuRT-- --~------OEiECTION----- --~RRORSTACKING
RE-RUN BUS CYCLE TIMING INFORMATION
Figure 21
ClK
AS
~~====~~============~=====~
\
\
/
/
\~----~~--------------------~\
/
\
\
/
~
[OS
R/W
\
OTACK
)
)
08-015
00-07
FCO-2
=x
BERR
(
(
X
\
/~---
/
/
r-
)-)--
x=
HArT
fool------·
REAO ----~-_tc---------- HALT --------------~------ RERUN -------~
VI-21
HALT SIGNAL TIMING CHARACTERISTICS·
Figure 22
ClK
AS
----------------------,\\'------
/~-----
UOS
lOS
R/VV
---,
/
OTACK
_=:J
08-015
00-07
FCO-2
,---
~--~======~----------------~--~\======~I
\
/'---
(
~
r=-------=r--
=x
~
HALT
I--~-- READ - - ---¥-----~~HAlT -
2. Stacking the error information
3. Reading the bus error vector table entry
4. Executing the bus error handler routine
-------
¥- -- --
READ
-------.1
The halt and run modes are somewhat self explanatory in
that when the halt signal is constantly active the processor
"halts" (does nothing) and when the halt signal is
constantly inactive the processor "runs" (does something).
The stacking of the program counter and the status register
is the same as if an interrupt had occurred. Several
additional items are stacked when a bus erroroccurs. These
items are used to determine the nature of the error and
correct it, if possible. The bus errOr vector is vector number
two located at address $000008. The processor loads the
new program counter from this location. A software bus
error handler routine is then executed by the processor.
Refer to EXCEPTION PROCESSING for additional information.
The single-step mode is derived from correctly timed
transitions on the halt signal input. It forces the processorto
execute a single bus cycle by entering the "run" mode until
the processor starts a bus cycle then changing to the "halt"
mode. Thus, the single-step mode allows the user to
proceed through (and therefore debug) processor operations one bus cycle at a time.
Re-Running the Bus Cycle. When the processor receives a
bus error signal and the h}llt pin is being driven by an
external device, the processor enters the re-run sequence.
Figure 21 is a timing diagram for re-running the bus cycle.
Figure 22 details the timing required for correct single-step
operations. Some care must be exercised to avoid harmful
interactions between the bus error signal and the halt pin
when using the single cycle mode as a debugging tool. This
is also true of interactions between the halt and reset lines,
since these can reset the machine.
The processor completes the bus cycle, then puts the
address and data lines in the high-impedance state. The
processor remains "halted," and will notrun another bus
cycle until the halt signal is removed by external logic. Then
the processor will re-run the previous bus cycle using the
same address, the same function codes, the same data (for
a write operation), and the same controls. The bus error
signal should be removed at least one clock cycle before the
halt signal is removed.
When the processor completes a bus cycle after recognizing
thatthe halt signal is active, mostthree-state signals are put
in the high-impedance state. These include:
1. address lines
2. data lines
This is required for correct performance of the re-run bus
cycle operation.
NOTE
The processor will not re-run a read-modify-write cycle.
This restriction is made to guarantee that the entire cycle
runs correctly and that the write operation of a Test -a nd-Set
operation is performed without ever releasing AS. IfBERR
and HALT are asserted during a read-modify-write bus
cycle, a bus error operation results.
Note that when the processor honors a request to halt, the
function codes are put in the high-impedance state (their
buffer characteristics are the same as the address buffers).
While the processor is honoring the halt request, bus
arbitration performs as usual. That is, halting has no effect
on bus arbitration. It is the bus arbitration function that
removes the control signals from the bus.
Halt Operation with No Bus Error. The halt input signal to
the MK68000 performs a HaltiRun/Single-Step function.
The halt function and the hardware trace capability allow
the hardware debugger to trace single bus cycles or single
VI-22
RESET OPERATION TIMING DIAGRAM
Figure 23
ClK
JU1JU1JU1MflJUmJUU1J1JlflJU1JU1JU1IUUUU1f1f1JU1JUU1JU1MfU1JUU1J1JL
PLUS 5 VOLTS
Vee
~
REm
l~____~_
HALT
l~
t->100
,..~-~ MilLISECONDS -~"r------------
I
__________________~
,..~
1-..
BUS CYCLES
2
NOTES:
1) Internal start-up time
2) SSP High read in here
3) SSP Low read in here
4) PC High read in here
5) PC Low read. in here
6) First instruction fetched here.
3
4
5
6
Bus State Unknown:
All Control Signals Inactive
Data Bus In Read Mode:
instructions at a time. These processor capabilities, along
with a software debugging package, give total debugging
flexibility.
and loaded into the program counter. The processor
initializes the status register to an interrupt level of seven.
No other registers are affected by the reset sequence.
Double Bus Faults. When a bus error exception occurs, the
processor will attempt to stack several words containing
information about the state of the machine. If a bus error
exception occurs during the stacking operation, there have
been two bus errors in a row. This is commonly referred to
as a double bus fault. When a double bus fault occurs, the
processor will halt. Once a bus error exception has
occurred, any bus error exception occurring before the
execution of the next instruction constitutes a double bus
fault.
When a RESET sequence is executed, the processor drives
the reset pin for 124 clock pulses. In this case, the processor
is trying to reset the rest of the system. Therefore, there is
no effect on the internal state of the processor. All of the
processor's internal registers and the status register are
unaffected by the execution of a RESET instruction. All
external devices connected to the reset line should be reset
at the completion of the RESET instruction.
Note that a bus cycle which is re-run does not constitute a
bus error exception, and does not contribute to a double bus
fault. Note also that this means that as long .as the external
hardware requests it, the processor will continue to re-run
the same bus cycle.
The bus error pin also has an effect on processor operation
after the processor receives an external r~set input. The
processor reads the vector table after a reset to determine
the address to start program execution. If a bus error occurs
while reading the vector table (or at any time before the first
instruction is executed), the processor reacts as.if a double
bus fault has occurred and it halts. Only an external reset
will start a halted processor.
RESET OPERATION. The reset signal is a bidirectional
signal that allows either the processor or an external signal
to reset the system. Figure 23 is a timing diagram for reset'
operations. Both the halt and the reset lines must be applied
to ensure total reset of the processor.
Asserting th~ reset and halt pins for 10 clock cycles will
cause a processor reset, except when Vee is initially applied
to the processor. In this case, an. external reset must be
applied to the reset pin for 100 milliseconds.
THE RELATIONSHIP OF DTACK, BERR, AND HALT
In order to control termination of a bus cycle for a re-run or a
bus error condition properly, DTACK, BERA. and HALT
should be asserted and negated on the rising edge of the
MK68000 clock. This will assure that when two signals are
.asserted simultaneously, the required setup time (#47) f~r
both of them will ~ met during the same bus state.
This, or some equivalent precaution, should be designed
external to the MK68000. Parameter #48 is intended to
ensure this operation in a totally asynchronous system, and
may be ignored if the above conditions are met.
The preferred bus cycle terminations may be summarized
as follows (case num~rs refer to Table 17):
When the reset and halt lines are driven by an external
device, it is recognized as an entire system reset, including
the processor. The processor responds by reading the reset
vector table entry (vector number zero, address $000000)
and loads it into the supervisor stack pointer (SSP). Vector
table entry number one at address $000004 is read next
VI-23
Normal Termination: DTACK occurs first (case 1).
Halt Termination: HALT is asserted at same time, or
precedes DTACK ino BERR) cases 2 and 3.
Bus Error Termination: BERR is asserted in lieu of, at
same time, or preceding DTACK (case 4); BERR negated
at same time, or after DTACK.
Re-RunTermination: HALT and BERR asserted at the
II
DTACK. BERR. HALT ASSERTION RESULTS
Table 17
Asserted on Rising
Edge of State
N
N+2
Case
No,
Control
Signal
1
DTACK
BERR
HALT
2
DTACK
BERR
HALT
A
NA
A
DTACK
BERR
HALT
NA
NA
A
DTACK
BERR
HALT
X
X
A
NA
5
NA
DTACK
BERR
HALT
X
X
5
A
A
5
5
6
DTACK
BERR
HALT
NA
NA
A
A
3
4
Result
5
A
NA
NA
Normal cycle terminate and continue.
X
X
..
5
Normal cycle terminate and halt. Continue when HALT
removed.
X
5
A
NA
Normal cycle terminate and halt. Continue when HALT
removed.
5
Terminate and take bus error trap.
Terminate and re-run.
Terminate and re-run when HALT removed.
X
5
Legend:
N - the number of the current even bus state (e.g., 54, 56, etc.)
A - signal is asserted in this bus state
NA - signal is not asserted in this state
X - don't care
5 - signal was asserted in previous state and remains asserted in this state
BERR AND HALT NEGATION RESULTS
Table 18
Conditions of
Termination in
Table A
Control
Signal
Bus Error
BERR
HALT
Re-run
BERR
HALT
Re-run
BERR
HALT
Normal
Normal
Negated on Rising
Edge of State
N+2
N
•
•
•
•
•
Results -
Next Cycle
or
or
•
•
Takes bus error trap.
or
•
Illegal sequence, usually traps to vector
number O.
Re-runs the bus cycle.
•
BERR
HALT
•
•
or
BERR
HALT
•
or
May lengthen next cycle.
•
•
If next cycle is started it will be terminated
none as a bus error.
VI-24
same time, or before DTACK(cases 5 and 6); HALT must
be negated at least 1 cycle after BERR.
translate accesses, and is used to choose between the
supervisor stack pointer and the user stack pointer in
instruction references.
Table 17 details the resulting bus cycle termination under
various combinations of control signal sequences. The
negation of these same control signals under several
conditions is shown in Table 18 (DTACK is assumed to be
negated normally in all cases; for best results, both DTACK
and BERR should be negated when address strobe is
negated.)
The privilege state is a mechanism for providing security in a
computer system. Programs should access only their own
code and data areas, and ought to be restricted from
accessing information which theydo not need and must not
modify.
Example A: A system uses a watch-dog timer to terminate
accesses to un-populated address space. The timer asserts
DTACK and BERR simultaneously after time-out. (case 4)
The privilege mechanism provides security by allowing
most programs to execute in user state. In this state, the
accesses are controlled, and the effects on other parts of the
system are limited. The operating system executes in the
supervisor state, has access to all resources, and performs
the overhead tasks for the user state programs.
Example B: A system uses error detection on RAM
contents. Designer may (a) delay DTACK until data verified,
and return BERR and HALT simultaneously to re-run error
cycle (case 5), or if valid, return DTACK; (b) delay iYi'ACR
until data verified, and return BERR at same time as DTACK
if data in error (case 4); (c) return DTACK prior to data
verification, as described in previous section. If data invalid,
BERR is asserted (case 1) in next cycle. Error-handling
software must know how to recover error cycle.
PROCESSING STATES
The MK68000 is always in one of three processing states:
normal. exception, or halted. The normal processing state is
that associated with instruction execution; the memory
references are to fetch instructions and operands, and to
store results. A special case of the normal state is the
stopped state which the processor enters when a STOP
instruction is executed. In this state, no further memory
references are made.
The exception processing state is associated with
interrupts, trap instructions, traCing and other exceptional
conditions. The exception may be internally generated by an
instruction or by an unusual condition arising during the
execution of an instruction. Externally, exception processing can be forced by an interrupt, by a bus error, or by a
reset. Exception processing is designed to provide an
efficient context switch so that the processor may handle
unusual conditions.
The halted processing state is an indication of catastrophic
hardware failure. For example, if during the exception
processing of a bus error another bus error occurs, the
processor assumes that the system is unusable and halts.
Only an external reset can restart a halted processor. Note
that a processor in the stopped state is not in the halted
state, nor vice versa.
PRIVILEGE STATES
The processor operates in one of two states of privilege: the
"user" state or the "supervisor" state. The privilege state
determines which operations are legal, is used by the
external memory management device to control and,
SUPERVISOR STATE, The supervisor state is the higher
state of privilege. For instruction execution, the supervisor
state is determined by the S-bit of the status register; if the
S-bit is asserted (high), the processor is in the supervisor
state. All instructions can be executed in the supervisor
state. The bus cycles generated by instructions executed in
the supervisor state are classified as super~isor references.
While the processor is in the supervisor privilege state,
those instructions which use either the system stack
pointer implicity or address register seven explicitly access
the supervisor stack pointer.
All exception processing is done in the supervisor state,
regardless of the setting of the S-bit. The bus cycles
generated during exception processing are classified as
supervisor references. All stacking operations during
exception processing use the supervisor stack pointer.
USER STATE. The user state is the lower state of privilege.
For instruction execution, the user state is determined by
the S-bit of the status register; if the S-bit is negated (low),
the processor is executing instructions in the user state.
Most instructions execute the same in user state as in the
supervisor state. However, some instructions which have
important system effects are made privileged. User
programs are not. permitted to execute the STOP
instruction, or the RESET instruction. To ensure that a user
program cannot enter the supervisor state except in a
controlled manner, the instructions which modify the whole
status register are privileged. To aid in debugging programs
which are to be used as operating systems, the move to user
stack pointer (MOVE USP) and move from user stack pointer
(MOVE from USP) instructions are also privileged.
The bus cycles generated by an instruction executed in user
state are classified as user state references. This allows an
external memory management device to translate the
address and to control access to protected portions of the
address space. While the processor is in the user privilege
state, those instructions which use either the system stack
pointer implicity, or address register seven explicitly, access
the user stack pointer.
VI-25
PRIVILEGE STATE CHANGES. Once the processor is in
the user state and executing instructions, only exception
processing can change the privilege state. During exception
processing, the current setting of the S-bit of the status
register is saved and the S-bit is asserted, putting the
processing in the supervisor state. Therefore, when
instruction execution resumes at the address specified to
process the exception, the processor is in the supervisor
privilege state.
REFERENCE CLASSIFICATION
Table 19
Function Code Output
FC2
FC1
FCO
REFERENCE CLASSIFICATION. When the processor
makes a reference, it classifies the kind of reference being
made, using the encoding on the three function code output
lines. This allows external translation of addresses, control
of access, and differentiation of special processor states,
such as interrupt acknowledge. Table 19 lists the
classification of references.
EXCEPTION PROCESSING
Before discussing the details of interrupts, traps, and
tracing, a general description of exception processing is in
order. The processing of an exception occurs in four steps,
with variations for different exception causes. During the
first step, a temporary copy of the status register is made,
and the statustegister is set for exception processing. In the
second step the exception vector is determined, and the
third step is the saving of the current processor context. In
the fourth step a new context is obtained, and the processor
switches to instruction processing.
EXCEPTION VECTORS. Exception vectors are memory
locations from which the processor fetches the address of a
routine which will handle that exception. All exception
Reference Class
0
0
0
(Unassigned)
0
0
1
User Data
0
1
0
User Program
0
1
1
(Unassigned)
1
0
0
(Unassigned)
1
0
1
Supervisor Data
1
1
0
Supervisor Program
1
1
1
Interrupt Acknowledge
vectors are two words in length (Figure 24), except for the
reset vector, which is four words. All exception vectors lie in
the supervisor data space, except for the reset vector which
is in the supervisor program space. A vector number is an
eight-bit number which, when multiplied by four, gives the
address of an exception vector. Vector numbers are
generated internally or externally, depending on the cause
of the exception. In the case of interrupts, during the
interrupt acknowledge bus cycle, a peripheral provides an
8-bit vector number(Figure 25)to the processor on data bus
lines DO through 07. The processor translates the vector
number into a full 24-bit address, as shown in Figure 26.
The memory layout for exception vectors is given in Table
20.
EXCEPTION VECTOR FORMAT
Figure 24
WORD 0
NEW PROGRAM COUNTER (HIGH)
AO
WOR!) 1
NEW PROGRAM COUNTER (LOW)
AO = O. A1 = 1
= 0.A1 = 0
PERIPHERAL VECTOR NUMBER FORMAT
Figure 26
08 07
016
I
DO
IGNORED
Where:
v7 is the MSB of the Vector Number
vO is the LSB of the Vector Number
. ADDRESS TRANSLATEDFROM8-BIT Vj:CTOR NUMBER
Figure 26
A23
A10 A9 A8
ALL ZEROES
VI-26
A7 A6 AS A4 A3
A2 A1
AO
EXCEPTION VECTOR ASSIGNMENT
Table 20
Vector
Number(s)
Dec
Address
Hex
Space
Assignment·
0
0
000
SP
Reset Initial SSP
-
4
004
SP
Reset Initial PC
2
8
008
SO
Bus Error
OOC
SO
Address Error
3
12
4
16
010
SO
Illegal Instruction
5
20
014
SO
Zero Divide
6
24
018
SO
CHK Instruction
7
28
01C
SO
TRAPV Instruction
8
32
020
SO
Privilege Violation
9
36
024
SO
Trace
10
40
028
SO
Line 1010 Emulator
11
44
02C
SO
Line 1111 Emulator
12*
48
030
SO
(Unassigned. reserved)
13*
52
034
SO
(Unassigned. reserved)
14*
56
038
SO
(Unassigned. reserved)
15
60
03C
SO
Uninitialized Interrupt Vector
16-23*
64
04C
SO
(Unassigned. reserved)
95
05F
,.1
-
24
96
060
SO
Spurious Interrupt
25
100
064
SO
Level 1 Interrupt Autovector
26
104
068
SO
Level 2 Interrupt Autovector
27
108
06C
SO
Level 3 Interrupt Autovector
28
112
070
SO
Level 4 Interrupt Autovector
29
116
074
SO
Level 5 Interrupt Autovector
30
120
078
SO
Level 6 Interrupt Autovector
31
124
07C
SO
Level 7 Interrupt Autovector
3247
128
080
SO
TRAP Instruction Vectors
191
OBF
192
OGO
255
OFF
256
100
1023
3FF
48-63*
64-255
(Unassigned. reserved)
SO
User Interrupt Vectors
SO
"
*Vector numbers 12. 13. 14. 16 through 23 and 48 through 63 are reserved for future enhancements by Mostek. No user
peripheral devices should be assigned these numbers.
VI-27
II
As shown in Table 20, the memory layout is 512 words long
(1024 bytes). It starts at address 0 and proceeds through
address 1023. This provides 255 unique vectors; some of
these are reserved for TRAPS and other system functions.
Of the 255, these are 192 reserved for user interrupt
vectors. However, there is no protection on the first 64
entries, so user interrupt vectors may overlap at the
discretion of the systems designer.
KINDS OF EXCEPTIONS. Exceptions can be generated by
either internal or external causes. The externally generated
exceptions are the interrupts and the bus error and reset
requests. The interrupts are requests from peripheral
devices for processor action while the bus error and reset
inputs are used for access control and processor restart. The
internally generated exceptions come from instructions, or
from address errors or tracing. The trap (TRAP), trap on
overflow (TRAPV), check register against bounds (CHK) and
divide (DIV) instructions all can generate exceptions as part
of their instruction execution. In addition, illegal instructions, word fetches from odd addresses and privilege
violations cause exceptions. Tracing behaves like a very
high priority, internally generated interrupt after each
instruction execution.
EXCEPTION PROCESSING SEQUENCE. Exception
processing occurs in four identifiable steps. In the first step,
an internal copy is made of the status register. After the
copy is made, the S-bit is asserted, putting the processor
into the supervisor privilege state. Also, the T -bit is negated
which will allow the exception handler to execute
unhindered by tracing. For the reset and interrupt
exceptions, the interrupt priority mask is also updated.
In the second step, the vector number of the exception is
determined. For interrupts; the vector number is obtained by
a processor fetch, classified as an interrupt acknowledge.
For all other exceptions, internal logic provides the vector
number. This vector number is then used to generate the
address of the exception vector.
The third step is to save the current processor status, except
for the reset exception. The current program counter value
and the saved copy of the status register are stacked using
the supervisor stack pointer. The program counter value
stacked usually points to the next unexecuted instruction,
however for bus error and address error, the value stacked
for the program counter is unpredictable, and may be
incremented from the address of the instruction which
caused the error. Additional information defining the
current context is stacked for the bus error and address
error exceptions.
MULTIPLE EXCEPTIONS. These paragraphs describe the
processing which occurs when multiple exceptions arise
simultaneously. Exceptions can be grouped according to
their occurrence and priority. The Group 0 exceptions are
reset, bus error, and address error. These exceptions cause
the instruction currently being executed to be aborted, and
the exception processing to commence at the next minor
cycle of the processor. The Group 1 exceptions are trace and
interrupt, as well as the privilege violations and illegal.
instructions. These eXCeptions allow the current instruction
to execute to completion, but preempt the execution of the
next instruction by forcing exception processing to occur
(privilege violations and illegal instructions are detected
when they are the next instruction to be executed). The
Group 2 exceptions occur as part of the normal processing
of instructions. The TRAP, TRAPV, CHK, and zero divide
exceptions are in this group. For these exceptions, the
normal execution of an instruction may lead to exception
processing.
Group 0 exceptions have highest priority, while Group 2
exceptions have lowest priority. Within Group 0, reset has
highest priority, followed by bus error and then address
error. Within Group 1, trace has priority over external
interrupts, which in turn takes priority over illegal
instruction and privilege violation. Since only one
instruction can be executed at a time, there is no priority
relation within Group 2.
The priority relation between. two exceptions determines
which is taken, or taken first, if the conditions for both arise
simultaneously. Therefore, if a bus error occurs during a
TRAP instruction, the bus error takes precedence, and the
TRAP instruction processing is aborted. In another example,
if an interrupt request occurs during the execution of an
instruction while the T-bit is asserted, the trace exception
has priority, and is processed first. Before instruction
processing resumes, however, the interrupt exception is
also processed, and instruction processing commences
finally in the interrupt handler routine. A summary of
exception grouping and priority is given in Table 21.
EXCEPTION GROUPING AND PRIORITY
Table 21
Group
The last step is the same for all exceptions. The new
program counter value is fetched from the exception vector.
The processor then resumes instruction execution. The
instruction at the address given in the exception vector is
fetched, and normal instruction decoding and execution is
.-started.
VI-28
0
1
2
Exception
Processing
Reset
Bus Error
Exception processing begins
Address Error within two clock cycles
Trace
Interrupt
Illegal
Privilege
Exception processing begins
before the next instruction
TRAP, TRAPV,
Exception processing is started
CHK,
Zero Divide by normal instruction execution
EXCEPTION PROCESSING DETAILED DISCUSSION
Exceptions have a number of sources, and each exception
has processing which is peculiar to it. The following
paragraphs detail the sources of exceptions, how each
arises, and how each is processed.
RESET. The reset input provides the highest exception
level. The processing of the reset signal is designed for
system initiation, and recovery from catastrophic failure.
Any processing in progress at the time of the reset is
aborted and cannot be recovered. The processor is forced
into the supervisor state, and the trace state is forced off.
The processor interrupt priority mask is set at level seven.
The vector number is internally generated to reference the
reset exception vector at location 0 in the supervisor
program space. Because no assumptions can be made
about the validity of register contents, in particular the
supervisor stack pointer, neither the program counter nor
the status register is saved. The address contained in the
first two words of the reset exception vector is fetched as the
initial supervisor stack pointer, and the address in the last
two words of the reset exception vector is fetched as the
initial program counter. Finally, instruction execution is
started at the address in the program counter. The powerup/restart code should be pointed to by the initial program
counter.
suppressed, and. the processor priority level is set to the
level of the interrupt being acknowledged. The processor
fetches the vector number from the interrupting device,
classifying the reference as an interrupt acknowledge and
displaying the level number of the interrupt being
acknowledged on the address bus. If external logic requests
an automatic vectoring, the processor internally generates
a vector number which is determined by the interrupt level
number. If external logic indicates a bus error, the interrupt
is taken to be spurious, and the generated vector number
references the spurious interrupt vector. The processor
then proceeds with the usual exception processing, saving
the program counter and status register on the supervisor
stack. The saved value ofthe program counter is the address
of the instruction which would have been executed had the
interrupt not been present. The content of the interrupt
vector whose vector number was previously obtained is
fetched and loaded into the program counter, and normal
instruction execution commences in the interrupt handling
routine. A flow chart for the interrupt acknowledge
sequence is given in Figure 27; a timing diagram isgiven in
Figure 28.
Priority level seven is a special case. Level seven interrupts
INTERRUPT ACKNOWLEDGE SEQUENCE
FLOWCHART
Figure 27
The RESET instruction does not cause loading of the reset
vector, but does assert the reset line to reset external
devices. This allows the software to reset the system to a
known state and then continue processing with the next
instruction.
PROCESSOR
INTERRUPTING DEVICE
Request Interrupt
I
Grant Interrupt
INTERRUPTS. Seven levels of interrupt priorities are
provided. Devices may be chained externally within
interrupt priority levels, allowing an unlimited number of
peripheral devices to interrupt the processor. Interrupt
priority levels are numbered from one to seven, level seven
being the highest priorty. The status register contains a
three-bit mask which indicates the current processor
priority, and interrupts are inhibited for all priority levels less
than or equal to the current processor priority.
An interrupt request is made to the processor by encoding
the interrupt request level on the interrupt request lines; a
zero indicates no interrupt request. Interrupt requests
arriving at the processor do not force immediate exception
processing, but are made pending. Pending interrupts are
detected between instruction executions. If the priority of
the pending interrupt is lower than or equal to the current
processor priority, execution continues with the next
instruction and the interrupt exception processing is
postponed. (The recognition of level seven is slightly
different, as explained in a following paragraph.)
If the priority of the pending interrupt is greater than the
current processor priority, the exception processing
sequence is started. First a copy of the status register is
saved, and the privilege state is set to supervisor, tracing is
VI-29
1 ) Compare interrupt level in status register
and wait for current instruction to complete
2)
3)
4)
5)
6)
Place interrupt level on A 1. A2, A3
Set R/W to read
Set function code to interrupt acknowledge
Assert address strobe (AS)
Assert lower data strobe (LOS)
)
,
Provide Vector Number
1) Place vector number on 00-07
2) Assert data transfer acknowledge (OTACK)
I
Acquire Vector Number
,
1 ) Latch vector number
2) Negate LOS
3) Negate AS
)
Release
1) Negate OTACK
t
Start Interrupt Processing
)
II
INTERRUPT ACKNOWLEDGE SEQUENCE TIMING DIAGRAM
Figure 28
A1-A3
=>-<
I
\
AS
\
ODs
\
\
\
r
\
\
}.
\
I
rns
R/W
\
OTACK
\
08-015
(
00-07
(
\
(
(
FCO-2:J(
IPLO-2
\
/
)
<
X.
7
\
LAST BUS CYCLE OF INSTRUCTION STACK
(READ OR WRITE)
I PCL. I.
1...
.. .... (SSP)-I..
lACK CYCLE
(VECTOR NUMBER ACQUISITION)
STACK AND
*..._----.. .
*-..._ - - - - - - - - - - - - - ...
cannot be inhibited by the interrupt priority mask, thus
providing a "non-maskable interrupt" capability. An
interrupt is generated e,ach time the interrupt request level
changes from some lower level to level seven. Note that a
level seven interrupt may still be caused by the level
comparison if the request level is a seven and the processor
priority is set to a lower level by an instruction.
UNINITIALIZED INTERRUPT. An interrupting device
asserts VPA or provides an interrupt vector during an
interrupt acknowledge cycle to the MK68000. If the vector
register has not been initialized, the responding MK68000
Family peripheral will provide vector 15, the uninitialized
interrupt vector. This provides a uniform way to recover
from a programming error.
SPURIOUS INTERRUPT. If during the interrupt acknowledge cycle no device responds by asserti ng DTACK or VPA,
the bus error line should be asserted to terminate the vector
acquisition. The processor separates the processing of this
error from bus error by fetching the spurious interrupt
vector instead of the bus error vector. The processor then
proceeds with the usual exception processing.
INSTRUCTION TRAPS. Traps are exceptions caused by
instructions. They arise eitherfrom processor recognition of
abnormal conditions during instruction execution, or from
use of instructions whose normal behavior is trapping.
Some instructions are used specifically to generate traps.
The TRAP instruction always forces an exception, and is
useful for implementing system calls for user programs.
The TRAPV and CHK instructions force an exception if the
user program detects a runtime error, which may be an
arithmetic overflow or a subscript out of bounds.
1 VECTOR FETCH 1
--1.
The signed divide (DIVS) and unsigned divide (DIVU)
instructions will force an exception if a division operation is
attempted with a divisor of zero.
ILLEGAL AND UNIMPLEMENTED INSTRUCTIONS.
Illegal instruction is the term used to refer to anyofthe word
bit patterns which are not the bit pattern of the first word of a
legal instruction. During instruction execution, if such an
instruction is fetched, an illegal instruction exception
occurs.
Word patterns with bits 15 through 12 equaling 1010 or
1111 are distinguished as unimplemented instructions and
separate exception vectors are given to these patterns to
permit efficient emulation. This facility allows the operating
system to detect program errors, or to emulate unimplemented instructions in software.
PRIVILEGE VIOLATIONS. In order to provide system
security, various instructions are privileged. An attempt to
execute one of the privileged instructions while in the user
state will cause an exception., The privileged instructions
are:
STOP
RESET
RTE
MOVE to SR
AND (word) Immediate to SR
EOR (word) Immediate to SR
OR (word) Immediate to SR
MOVEUSP
TRACING. To aid in program development, the MK68000
includes a facility to allow instruction by instruction tracing.
In the trace state, after each instruction is executed an
exception is forced, allowing a debuggi!lg program to
monitor the execution of the program under test.
VI-30
The trace facility uses the T-bit in the supervisor portion of
the status register. If the T-bit is negated (off), tracing is
disabled, and instruction execution proceeds from instruction to instruction as normal. If the T-bit is asserted (on) at
the beginning of the execution of an instruction, a trace
exception will be generated after the execution of that
instruction is completed. If the instruction is not executed,
either because an interrupt is taken, or the instruction is
illegal or privileged, the trace exception does not occur. The
trace exception also does not occur if the instruction is
aborted by a reset, bus error, or address error exception. If
the instruction is indeed executed and an interrupt is
pending on completion, the trace exception is processed
before the interrupt exception. If, during the execution of the
instruction, an exception is forced by that instruction, the
forced exception is processed before the trace exception.
status register are of course saved. The value saved for the
program counter is advanced by some amount, two to ten
bytes beyond the address of the first word of the instruction
which made the reference causing the bus error. If the bus
error occurred during the fetch of the next instruction, the
saved program counter has a value in the vicinity of the
current instruction, even if the current instruction is a
branch, a jump, or a return instruction. Besides the usual
information, the processor saves its internal copy of the first
word of the instruction being processed and the address
which was being accessed by the aborted bus cycle.
Specific information about the access is also saved whether
it was a read or a write, whether the processor was
processing an instruction or not, and the classification
displayed on the function code outputs when the bus error
occurred. The processor is processing an instruction if it is in
the normal state or processing a Group 2 exception; the
processor is not processing an instruction if it is processing
a GroupOor a Group 1 exception. Figure 29 illustrates how
this information is organized on the supervisor stack.
Although this information is not sufficient in general to
effect full recovery from the bus error, it does allow software
diagnosis. Finally, the processor commences instruction
processing at the address contained in the vector. It is the
responsibility of the error handler routine to clean up the
stack and determine where' to continue execution.
As an extreme illustration of the above rules, consider the
arrival of an interrupt during the execution of a TRAP
instruction while tracing is enabled. First the trap exception
is processed, then the trace exception, and finally the
interrupt exception. Instruction execution resumes in the
interrupt handler routine.
BUS ERROR. Bus error exceptions occur when the
external logic requests that a bus error be processed by an
exception. The current bus cycle which the processor is
making is then aborted. Whether the processor was doing
instruction or exception processing, that processing is
terminated, and the processor immediately begins
exception processing.
If a bus error occurs during the exception processing for a
bus error, address error, or reset, the processor is halted,
and all processing ceases. This simplifies the detection of
catastrophic system failure, since the processor removes
itself from the system rather than destroy all memory
contents. Only the RESET pin can restart a halted processor.
Exception processing for bus error follows the usual
sequence of steps. The status register is copied, the
supervisor state is entered, and the trace state is turned off.
The vector number is generated to refer to the bus error
vector. Since the processor was not between instructions
when the bus error exception request was made, the
context of the processor is more detailed. To save more of
this context, additional information is saved on the
supervisor stack. The program counter and the copy of the
ADDRESS ERROR. Address error exceptions occur when
the processor attempts to access a word or a long word
operand or an instruction at an odd address. The effect is
much like an internally generated bus error, so that the bus
cycle is aborted, and the processor ceases whatever
processing it is currently doing and begins exception
processing. After exception processing commences, the
SUPERVISOR STACK ORDER
Figure 29
15
14
13
12
11
10
9
6
7
8
4
5
LOWER
ADDRESS
o
2
3
FUNCTION
CODE
IR/wIIlN I
HIGH
- ACCESS ADDRESS -
-
-
-
-
-
-
- - LOW
-
-
-
-
-
-
-
-
-
-
-
-
-
INSTRUCTION REGISTER
STATUS REGISTER
HIGH
PROGRAM COUNTER-
- - - - - - - ------------LOW
R/W (read/write): wnte = O. read = 1. I/N (instruction/not): instructIon = O. not = 1
VI-31
•
sequence is the same as that for bus error including the
information that is stacked, except that the vector number
refers to the address error vector instead. Likewise, if an
address error occurs during the exception processing for a
bus error, address error, or reset, the processor is halted.
6800 INTERFACING FLOW CHART
Figure 30
PROCESSOR
Initiate Cycle
SLAVE
1 ) The processor starts a normal Read or
Write cycle
INTERFACE WITH 6800 PERIPHERALS
•
To interface the synchronous 6800 peripherals with the
asynchronous MK68000, the processor modifies its bus
cycle to meet the 6800 cycle requirements whenever a
6800 device address is detected. This is possible since both
processors use memory mapped I/O. Figure 30 is a flow
chart of the interface operation between the processor and
6800 devices.
:Oefine 6800 cycle
1) External ~ware asserts Valid Peripheral
Address (VPA)
Synchronize With Enable
DATA TRANSFER OPERATION
1 ) The processor monitors Enable (E) until it is
low (Phase 1 )
Three signals on the processor provide the 6800 interface.
They are: enable (E), valid memory address (VMA), and valid
peripheral address (VPA). Enable corresponds to the E or 2
signal in existing 6800 systems. It is the bus clock used by
the frequency clock that is one tenth of the incoming
MK68000 clock frequency. The timing of E allows 1 MHz
peripherals to be used with an 8 MHz MK680oo. Enable
has a 60/40 duty cycle; that is, it is low for six input clocks
and high for four input clocks. This duty cycle allows the
processor to do successive VPA accesses on successive E
pulses.
2) The processor asserts Valid Memory Ad-
6800 cycle timing isgiven in Figure 31. At state zero (SO) in
the cycle, the address bus and function codes are in the
high-impedance state. One half clock later, in state 1, the
address bus and function code outputs are released from
the high-impedance state.
1) The processor waits until E goes low. (On a
dress(VMA)
I
Transfer Data
1 ) The peripheral waits until E is active and
then transfers the data
I
Terminate Cycle
,
Read cycle the data is latched as E goes
low intemally)
2) The processor negates VMA
3) The processor negates AS, UOS, and
During state 2, the address strobe (AS) is asserted to
rns
Start Next Cycle
6800 CYCLE OPERATION
Figure 31
~~~~~~~~~~~~~~~~~~~~~~~~~~~%~
CLK
f1JlJUl
A1·A23
>-<
~
UOS
~~__________________~
">-<\..____________--:::
~~----------------~
LOS
r
R/Vii
OTACK
~
08·015
00-07
(
>-<
(
---c=>~~~~~~~~~~E~~~~
>-<
X
X
X
FCO-2
)(
I
/\
E
VPA
tt-
---c=>~
\
I
\
VI-32
L
I
\
r
indicate that there is a valid address on the address bus. If
the bus cycle is a read cycle, the upper and/or lower data
strobi'ls are also asserted in state 2. If the bus cycle is a write
cycle, the read/write (R/W) signal is switched to low (write)
during state 2. One half clock later, in state 3, the write data
is placed on 1:hedata bus, and in state 4 the data strobes are
issued to indicate valid data on the data bus.
fact that while the vector numbers are fixed, the contents of
the vector table entries are assigned by the user.
Since VMA is asserted during autovectoring, the 6800
peripheral address decoding should prevent unintended
accesses.
INSTRUCTION SET
The processor now inserts wait states until it recognizes the
assertion of VPA. The VPA input signals the processor that
the address on the bus is the address of a 6800 device (or an
area reserved for 6800 devices) and that the bus should
conform to the <1>2 transfer characteristics of the 6800 bus.
Valid peripheral address is derived by decoding the address
bus, conditioned by address strobe.
'
The following paragraphs provide information about the
addressing categories and instruction set of the MK68000.
ADDRESSING CATEGORIES
Effective address modes may be categorized by the ways in
which they may be used. The following classifications will
be used in the instruction definitions.
After the recognition ofVPA, the processor assures that the
Enable (E) is low, by waiting if necessary, and subsequently
asserts VMA. Valid memory address is then used as part of
the chip select equation ofthe peripheral. This ensures that
the 6800 peripherals are selected and deselected at the
correct time. The peripheral now runs its cycle during the
high portion of the E signal.
Data
Memory
During a read cycle, the processor latches the peripheral
data in state 6. For all cycles, the processor negates the
address and data strobes one half clock cycle later in state 7
and the Enable signal goes low at this time. Another half
clock later, the address bus is put in the high-impedance
state. During a write cycle, the data bus is put in the highimpedance state and the read/write signal is switched high
at this time, The peripheral logic must remove VPA within
one clock after address strobe is negated. DTACK should.
not be asserted whileVPA is asserted.
Figure 32 shows the timing required by 6800 peripherals,
the timing specified for the 6800, and the corresponding
timing for the MK68000. Notice that the MK68000 VMA is
active low, contrasted with the active high 6800 VMA. This
allows the processor to put its buses in the high-impedance
state on DMA requests without inadvertently selecting
peripherals.
INTERRUPT INTERFACE OPERATION
During an interrupt acknowledge cycle while the processor
is fetching the vector, if VPA is asserted, the MK68000 will
assert VMA and complete a normal 6800 read cycle as
shown in Figure 33. The processor will then use an
internally generated vector that is a function ofthe interrupt
being serviced. This process is known as autovectoring. The
seven autovectors are vector numbers 25 through 31
(decimal).
Alterable
Control
If an effective address mode may be used to
refer to data operands, it is considered a data
addressing effective address mode.
If an effective address mode may be used to
refer to memory operands, it is considered a
memory addressing effective address mode.
If an effective address mode may be used to
refer to alterable (writeable) operands, it is
considered an alterable addressing effective
address mode.
If an effective address mode may be used to
refer to memory operands without an associated size, it is considered a control addressing
.
effective address mode.
Table 22 shows the various categories to wh ich each ofthe
effective address modes belong. Table 23 is the instruction
set summary.
The status register addressing mode is not permitted unless
it is explicitly mentioned as a legal addressing mode.
These categories may be combined, so that additional. more
restrictive, classifications may be defined. For example, the
instruction descriptions use such classifications as
alterable memory or data alterable. The former refers to
those addressing modes which are both alterable and
memory addresses, and the latter refers to addressing
modes which are both data and alterable.
INSTRUCTION PRE-FETCH
This operates in the same fashion (but is not restricted to)
the 6800 interrupt sequence. The basic difference is that
there are six normal interrupt vectors and one NMI type
vector. As with both the 6800 and the MK68000's normal
vectored interrupt, the interrupt service routine can be
located anywhere in the address space. This is due to the
The MK68000 uses a 2-word tightly-coupled instruction
prefetch mechanism to enhance performance. This
mechanism is described in terms of the microcode
operations involved. If the execution of an instruction is
defined to begin when the microroutine for that instruction
is entered, some features of the prefetch mechanism can be
described.
VI-33
1) When execution of an instruction begins, the operation
word and the word following have already been
•
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rPeripheral"
t+- 30 ns 6800"
14- 10 ns Peripheral"
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Type A
220 ns
320 ns
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Type A
80 ns
Std
195 ns
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c:,.,
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6800 WRITE DATA
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10 ns Peripheral
MK68000 (8 MHz)
I+- 2oons~
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WRITE DATA
MK68000 CLK
"Times are expressed for different device clock frequencies
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MK68000 ADDRESS
II
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Std
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0
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AUTOVECTOR OPERATION TIMING DIAGRAM
Figure 33
ClK
A1·A3
A4·A23
AS
UOS
iJ)5
R/VV
OTACK
~
08·015
--c:J------------------
00·07
----c=J-------------
c
FCO·2
X
7
IPW-2
~~~=======:-----~======~~-
L--
E
VPA
________
VMA
~\========~~--------~r-'l
II
____JI
\~ _ _ _ _ _ _
,..-~~~~-+-------
AUTOVECTOR OPERATION - - -
---I
EFfECTIVE ADDRESSING MODE CATEGORIES
Table 22
Effective
Address
Modes
Data
Addressing Categories
Memory
Control
Alterable
register number
register number
register number
X
X
X
X
X
X
X
011
100
101
register number
register number
register number
X
X
X
X
X
X
-
X
X
X
X
An@(d, ix)
xxx.w
xxx.L
110
111
111
register number
001
X
X
X
X
X
X
X
X
X
X
X
X
PC@(d)
PC@(d, ix)
#xxx
111
111
111
010
011
100
X
X
X
X
X
X
X
X
-
-
-
Mode
Register
Dn
An
An@
000
001
010
An@+
An@An@(d)
000
INSTRUCTION SET
Table 23
Mnemonic
Description
Operation
Condition
Codes
XN ZVC
ABCD
Add Decimal with Extend
(Destination), o+(Source), 0 - Destination
* U* U*
ADD
Add Binary
(Destination)+(Source) - Destination
* * * * *
* affected
o cleared
U defined
- unaffected
VI-35
1 set
[ I=
bit number
INSTRUCTION SET (CONTINUED)
Table 23
Mnemonic
Description
Operation
Condition
Codes
XN ZVC
ADDA
Add Address
(Destination)+(Source) - Destination
-
ADDI
Add Immediate
(Destination)+lmmediate Data - Destination
* * * * *
ADDQ
Add Quick
(Destination)+lmmediate Data - Destination
* * * * *
ADDX
Add Extended
(Destination)+(Source)+ X - Destination
* * * * *
AND
AND Logical
(Destination) A (Source) - Destination
- * * 0 0
ANDI
AND Immediate
(Destination) A Immediate Data - Destination
- * * 0 0
ASL,ASR
Arithmetic Shift
(Destination) Shifted by - Destination
* * * * *
Bee
Branch Conditionally
If ee then PC+d - PC
-
BCHG
Test a Bit and Change
~
«bit number» OF Destination - Z
«bit number» OF Destination OF Destination
- - * - -
BCLR
Test a Bit and Clear
~ «bit number» OF Destination - Z
0- - OF Destination
-
-
BRA
Branch Alwavs
PC+d-P.C
-
- - - -
-
-
* -
-
-
-
-
-
-
-
-
* -
-
* U UU
- - -
-
- - - -
~
* - -
BSET
Test a Bit and Set
«bit number» OF Destination - Z
1 - OF Destination
BSR
Branch to Subroutine
PC - SP@ -; PC+d - PC
BTST
Test a Bit
~
CHK
Check Register against Bounds
If Dn <0 or Dn> «ea» then TRAP
-
CLR
Clear an Operand
o-
- 0 1
CMP
Compare
(Destination) - (Source)
- * * * *
CMPA
Compare Address
(Destination) .:. (Source)
-
CMPI
Compare Immediate
(Destination) - Immediate Data
- * * * *
CMPM
Compare Memory
(Destination) - (Source)
- * * * *
DBee
Test Condition, Decrement and Branch If ~ ee then Dn - 1 - Dn; if Dn ¥= - 1 then
PC+d-PC
-
- -
DIVS
Signed Divide
(Destination)/(Source) - Destination
-
* * * 0
DIVU
Unsigned Divide
(Destination)/(Source) - Destination
- * * * 0
EOR
Exclusive OR Logical
(Destination) EB (Source) - Destination
- * *
EORI
Exclusive OR Immediate
(Destination) EB Immediate Data - Destination
- * *
EXG
Exchange Register
Rx -- Ry
- - - - -
EXT
Sign Extend
(Destination) Sign-extended - bestination
-
* * 0 0
JMP
Jump
Destination - PC
-
-
~
* affected
o cleared
U defined
«bit number» OF Destination - Z
Destination
- unaffected
VI-36
1 set
o0
* * * *
[ 1= bit number
-
-
o
o
-
-
0
0
-
INSTRUCTION SET (CONTINUED)
Table 23
Mnemonic
Description
Operation
Condition
Codes
XN Z V C
JSR
Jump to Subroutine
PC - SP@ -; Destination - PC
- -
-
- -
LEA
Load Effective Address
Destination - An
-
-
-
-
-
LINK
Link and Allocate
An - SP@ -; SP - An; SP + d - SP
-
-
-
-
-
LSL, LSR
Logical Shift
(Destination) Shifted by - Destination
* * * 0 *
MOVE
Move Data from Source to Destination (Source) - Destination
-
MOVE to CCR
Move to Condition Code
(Source) - CCR
* * * * *
MOVE to SR
Move to the Status Register
(Source) - SR
* * * * *
MOVE from
SR
Move from the Status Register
SR - Destination
-
-
-
-
-
MOVE USP
Move User Stack Pointer
USP - An, An - USP
-
-
-
-
-
MOVEA
Move Address
(Source) - Destination
-
-
-
-
-
MOVEM
Move Multiple Registers
Registers - Destination
(Source) - Registers
- -
-
--
-
MOVEP
Move Peripheral Data
(Source) - Destination
-
-
-
-
-
MOVEQ
Move Quick
Immediate Data - Destination
-
* *
0
MULS
Signed Multiply
(Destination)* (Source) - Destination
-
* *
MULU
Unsigned Multiply
(Destination)* (Source) - Destination
-
* *
o
o
o
NBCD
Negate Decimal with Extend
0- (Destination), 0 - X - Destination
* U * U *
NEG
Negate
0- (Destination) - Destination
* * * * *
NEGX
Negate with Extend
0- (Destination) - X - Destination
* * * * *
NOP
No Operation
-
-
-
NOT
Logical Complement
- (Destination) - Destination
-
* *
OR
Inclusive OR Logical
(Destination) v (Source) - Destination
-
* *
ORI
Inclusive OR Immediate
(Destination) v Immediate Data - Destination
-
PEA
Push Effective Address
Destination - SP@ -
-
RESET
Reset External Devices
-
ROL, ROR
Rotate (Without Extend)
ROXL, ROXR
* *
o
0
0
0
-
0
0
* *
o
o
o
-
-
-
--
-
-
-
-
-
(Destination) Rotated by - Destination
-
* * 0 *
Rotate with Extend
(Destination) Rotated by - Destination
* * * 0 *
RTE
Return from Exception
SP@ - - SR, SP@ + - PC
* * * * *
RTR
Return and Restore Condition Codes
SP@ + - CC; SP@ + - PC
* * * * *
RTS
Return from Subroutine
SP@+ - PC
-
* affected
o cleared
U defined
- unaffected
VI-37
1 set
-
-
-
[ l' bit number
-
0
-
•
INSTRUCTION SET (CONTINUED)
Table 23
Mnemonic
Description
Operation
Condition
Codes
XN Z V C
SBCD
Subtract Decimal with Extend
(Destination I, 0 - (Sourcel,o - X - Destination
* U * U *
Sec
Set According to Condition
If ee then 1's- Destination else O's- Destination
-
STOP
Load Status Register and Stop
Immediate Data - SR; STOP
* * * * *
SUB
Subtract Binary
(Destination) - (Source) - Destination
* * * * *
SUBA
Subtract Address
(Destination) - (Source) - Destination
-
SUBI
Subtract Immediate
(Destination) - Immediate Data - Destination
* * * * *
SUBQ
Subtract Quick
(Destination) - Immediate Data - Destination
* * * * *
SUBX
Subtract with Extend
(Destination) - (Source) - X - Destination
* * * * *
SWAP
Swap Register Halves
Register [31 :16]- Register [15:0]
-
TAS
Test and Set an Operand
(Destination) Tested - CC; 1 - [7] OF Destination - * * 0 0
TRAP
Trap
PC - SSP@ -; SR - SSP@ -; (Vector) - PC
-
TRAPV
Trap on Overflow
If V then TRAP
- - -
-
TST
Test an Operand
(Destination) Tested - CC
- * *
o0
UNlK
Unlink
An - SP; SP@ + - An
- - - - -
* affected
2)
3)
4)
5)
o cleared
U defined
- unaffected
fetched. The operation word is in the instruction
decoder.
In the case of multi-word instructions, as each
additional word of the instruction is used internally, a
fetch is made to the instruction stream to replace it.
The last fetch from the instruction stream is made
when the operation word is discarded and decoding is
started on the next instruction.
If the instruction is a single-word instruction causing a
branch, the second word is not used. But because this
word is fetched by the preceding instruction,it is
impossible to avoid this superfluous fetch. In the case of
an interrupt or trace exception, both words are not
used.
The program counter usually points to the last word
fetched from the instruction stream.
INSTRUCTION EXECUTION TIMES
The following paragraphs contain listings of the instruction
execution times in terms of external clock (ClK) periods. In
this timing data, it is assumed thatthe memory cycle time is
4 clock periods. Any wait states ca used by a longer memory
cycle must be added to the total instruction time. The
number of bus read and write cycles for each instruction is
also included with the timing data. This data is enclosed in
1 set
- -
- -
- - - -
* * 0 0
- - - -
[ ] = bit number
parenthesis following the execution periods and is shown
as: (r/w) where r is the number of read cycles and w is the
number of write cycles.
NOTE
The number of periods includes instruction fetch and all
applicable operand fetches and stores.
EFFECTIVE ADDRESS OPERAND CALCULATION
TIMING
Table 24 lists the number of clock periods required to
compute an instruction's effective address. It includes
fetching of any extensio.n words, the address computation,
and fetching of the memory operand. The number of bus
readand write cycles is shown in parenthesis as (r/w). Note
there are no write cycles involved in processing the effective
address.
MOVE INSTRUCTION CLOCK PERIODS
Tables 25 and 26 indicate the number of clock periods for
the move instruction. This data includes instruction fetch,
operand reads, and operand writes. The number of bus read
and write cycles is shown in parenthesis as: (r/w).
VI-3S
STANDARD INSTRUCTION CLOCK PERIODS
=address register operand, On =data register operand, ea
= an operand specified by an effective address, and M =
The number of clock periods shown in Table 27 indicates
the time required to perform the operations, store the
results, and read the next instruction. The number of bus
readand write cycles is shown in parenthesis as: (r/w). The
number of clock periods plus the number of read and write
cycles must be added to those of the effective address
calculation where indicated.
memory effective address operand.
In Table 27, the headings have the following meanings. An
IMMEDIATE INSTRUCTION CLOCK PERIODS
The number of clock periods shown in Table 28 includes the
time to fetch immediate operands, perform the operations,
store the results, and read the next operation. The number
of bus read and write cycles is shown in parenthesis as:
(r/w). The number of clock periods plus the number of read
EFFECTIVE ADDRESS CALCULATION TIMING
Table 24
Addressing Mode
.,
Byte, Word
Long
Dn
An
Register
Data Register Direct
Address Register Direct
0(0/0)
0(0/0)
0(0/0)
0(0/0)
An@
An@+
Memory
Address Register Indirect
Address Register Indirect with Postincrement
4(1/0)
4(1/0)
8(2/0)
8(2/0)
An@An@(d)
Address Register Indirect with Predecrement
Address Register Indirect with Displacement
6(1/0)
8(2/0)
10(2/0)
12(3/0)
An@(d, ix)*
xxx.w
Address Register Indirect with Index
Absolute Short
10(2/0)
8(2/0)
14(3/0)
12(3/0)
xxx.L
PC@(d)
Absolute Long
Program Counter with Displacement
12(3/0)
8(2/0)
16(4/0)
12(3/0)
PC@(d, ix)*
#xxx
Program Counter with Index
Immediate
10(2/0)
4(1/0)
14(3/0)
8(2/0)
*The size of the index register (ix) does not affect execution time.
MOVE BYTE AND WORD INSTRUCTION CLOCK PERIODS
Table 25
Destination
An@(d)
An@-
On
An
An@
An@+
Dn
An
An@
4(1/0)
4(1/0)
8(2/0)
4(1/0)
4(1/0)
8(2/0)
8(1/1)
8(1/1)
12(2/1)
8(1/1)
8(1/1)
12(2/1 )
8(1/1)
8(1/1 )
12(2/1 )
An@+
An@An@(d)
8(2/0)
10(2/0)
12(3/0)
8(2/0)
10(2/0)
12(3/0)
12(2/1 )
14(2/1)
16(3/1)
12(2/1 )
14(2/1)
16(3/1 )
An@(d, ix)*
xxx.w
xxx.L
14(3/0)
12(3/0)
16(4/0)
14(3/0)
12(3/0)
16(4/0)
18(3/1)
16(3/1)
20(4/1)
PC@(d)
PC@(d, ix)*
#xxx
12(3/0)
14(3/0)
8(2/0)
12(3/0)
14(3/0)
8(2/0)
16(3/1)
18(3/1)
12(2/1 )
Source
An@(d,ix)*
xxx.W
xxx.L
12(2/1)
12(2/1 )
16(3/1 )
14(2/1 )
14(2/1)
18(3/1 )
12(2(1 )
12(211)
16(3/1 )
16(3/1 )
16(3/1 )
20(4/1 )
12(2/1 )
14(2/1 )
16(3/1 )
16(3/1 )
18(3/1 )
20(4/1 )
18(3/1 )
20(3/1 )
22(4/1 )
16(3/1),
18(3/1 )
20(4/1 )
20(4/1 )
22(4/1)
24(5/1)
18(3/1 )
16(3/1)
20(4/1 )
18(3/1 )
16(3/1 )
20(4/1 )
22(4/1 )
20(4/1 )
24(5/1)
24(4/1 )
22(4/1 )
26(5/1)
22(4/1)
20(4/1 )
24(5/1)
26(5/1)
24(5/1)
28(6/1)
16(3/1 )
18(3/1 )
12(2/1 )
16(3/1 )
18(3/1)
12(2/1 )
20(4/1)
22(4/1)
16(3/1 )
22(4/1 )
24(4/1 )
18(3/1)
20(4/1 )
22(4/1)
16(3/1 )
24(5/1 )
26(5/1)
20(4/1)
*The size of the index register (ix) does not affect execution time.
VI-39
II
MOVE LONG INSTRUCTION CLOCK PERIODS
Table 26
Destination
An@(d)
An@-
An@(d.ix)*
xxx.W
xxx.L
16(212)
16(212)
24(412)
18(212)
18(212)
26(412)
16(212)
16(212)
24(412)
20(312)
20(312)
28(512)
20(312)
22(312)
24(412)
24(4/6)
26(412)
28(512)
26(412)
28(412)
30(512)
24(412)
26(412)
28(512)
28(512)
30(512)
32(612)
26(412)
24(412)
28(512)
26(412)
24(412)
28(5/2)
30(512)
28(512)
32(612)
32(512)
30(5)2)
34(612)
30(512)
28(512)
32(612)
34(612)
32(612)
36(712)
24(412)
26(4/2)
20(312)
24(412)
26(4/2)
20(3/2)
28(512)
30(512)
24(412)
30(512)
32(512)
26(412)
28(512)
30(512)
24(412)
32(512)
34(612)
28(512)
On
An
An@
An@+
Dn
An
An@
4(1/0)
4(110)
12(3/0)
4(1/0)
4(1/0)
12(3/0)
12(112)
12(112)
20(312)
12(112)
12(112)
20(312)
14(112)
14(112)
20(312)
An@+
An@An@(d)
12(3/0)
14(310)
16(4/0)
12(3/0)
14(3/0)
16(4/0)
20(312)
22(312)
24(412)
20(312)
22(312)
24(412)
An@(d,ix)*
XXX.W
xxx.L
18(4/0)
16(4/0)
20(510)
18(4/0)
16(4/0)
20(5/0)
26(412)
24(412)
28(512)
PC@(d)
PC@(d,ix)*
#xxx
16(4/0)
18(4/0)
12(3/0)
16(4/0)
18(4/0)
12(3/0)
24(4/2)
26(4/2)
20(312)
Source
*The size of the index register (ix) does not affect execution time.
STANDARD INSTRUCTION CLOCK PERIODS
Table 27
Instruction
Size
op. An
op. On
op Dn,
ADD
Byte, Word
Long
8(1/0) +
6(1/0) +**
4(110) +
6(1/0) +**
8(1/1) +
12(112) +
Byte, Word
Long
-
AND
-
4(1/0) +
6(1/0) +**
8(111 )+
12(112)+
CMP
Byte, Word
Long
6(110)+
6(1/0) +
4(1/0) +
6(1/0) +
-
DIVS
-
-
158(1/0) +*
-
DIVU
-
-
140(1/0) +*
-
Byte, Word
Long
-
EOR
-
4(1/0)***
8(1/0)***
8(1/1)+
12(112) +
MULS
-
-
70(1/0) +*
-
MULU
-
-
70(110) +*
-
OR
Byte, Word
Long
-
4(110) +
6(1/0) +**
8(1/1) +
12(112) +
SUB
Byte, Word
Long
8(110) +
6(1/0) +**
4(110) +
6(1/0) +**
8(1/1)+
12(112) +
+ add effective address calculation time
* indicates maximum value
** total of 8 clock periods for instruction if the, effective address is register direct
*** only available effective address mode is data register direct
and write cycles must be added to those of the effective
address calculation where indicated.
memory operand, and An '" address register operand.
SINGLE OPERAND INSTRUCTION CLOCK PERIODS
In Table 28, the headings have the following meanings: # =
immediate ope[and, Dn = data register operand, M =
Table 29 indicates the number of clock periods for the single
VI-40
IMMEDIATE INSTRUCTION CLOCK PERIODS
Table 28
Instruction
Size
op #. On
op#. M
op #. An
ADDI
Byte, Word
Long
8(2/0)
16(3/0)
12(2/1) +
20(312) +
-
AD DO
Byte, Word
Long
4(110)
8(1/0)
8(1/1) +
12(112) +
8(1/0)*
8(1/0)
ANDI
Byte, Word
Long
8(2/0)
16(3/0)
12(2/1) +
20(3/1) +
-
CMPI
Byte, Word
Long
8(2/0)
14(3/0)
8(2/0) +
12(3/0) +
8(2/0)
14(3/0)
Byte, Word
Long
8(210)
16(3/0)
12(2/1) +
20(312) +
-
EORI
Long
4(1/0)
-
-
Byte, Word
Long
8(2/0)
16(3/0)
12(2/1) +
20(312) +
-
ORI
SUBI
Byte, Word
Long
8(210)
16(3/0)
12(2/1) +
20(312) +
-
SUBO
Byte, Word
Long
4(110)
8(1/0)
8(1/1) +
12(112) +
8(1/0)*
8(1/0)
MOVEO
-
-
+ add effective address calculation time
*word only
SINGLE OPERAND INSTRUCTION CLOCK PERIODS
Table 29
Instruction
Size
Register
Memory
Byte, Word
Long
4(1/0)
6(1/0)
8(1/1) +
12(112) +
Byte
6(110)
8(1/1) +
NEG
Byte, Word
Long
4(1/0)
6(1/0)
8(1/1) +
12(112)+
NEGX
Byte, Word
Long
4(110)
6(1/0)
8(1/1) +
12(1/2) +
NOT
Byte, Word
Long
4(110)
6(1/0)
8(1/1) +
12(1/2) +
See
Byte, False
Byte, True
4(110)
6(1/0)
8(1/1) +
8(1/1) +
TAS
Byte
4(1/0)
10(1/1) +
TST
Byte, Word
Long
4(110)
4(1/0)
4(1/0)
4(1/0) +
CLR
NBCD
+ add effective address calculation time
VI-41
•
SHIFT/ROTATE INSTRUCTION CLOCK PERIODS
Table 30
Size
Register
Memory
Byte, Word
Long
6 + 2n(1/0)
8 + 2n(1/0)
8(1/1) +
ASR, ASL
Byte, Word
Long
6 + 2n(1/0)
8 + 2n(1/0)
8(111) +
LSR, LSL
Byte, Word
Long
6 + 2n(1/0)
8 + 2n(1/0)
8(111) +
ROR, ROL
Byte, Word
Long
6 + 2n(1/0)
8 + 2n(1/0)
8(111) +
ROXR, ROXL
Instruction
-
-
BIT MANIPULATION INSTRUCTION CLOCK PERIODS
Table 31
Dynamic
Static
Instruction
Size
Register
Memory
Register
Memory
Byte
Long
-
BCHG
8(110)*
8(111 )+
-
12(2/1 )+
-
12(2/0)*
-
Byte
Long
-
BCLR
10(1/0)*
8(111 )+
-
12(2/1)+
-
14(2/0)*
-
Byte
Long
-
BSET
8(110)*
8(1/1)+
-
12(2/1)+
-
12(2/0)*
-
Byte
Long
-
BTST
6(1/0)
4(110)+
-
-
10(2/0)
8(2/0)+
-
+ add effective address calculation time
* indicates maximum value
CONDITIONAL INSTRUCTION CLOCK PERIODS
Table 32
Trap or Branch
Taken
Trap or Branch
Not Taken
Byte
Word
10(2/0)
10(2/0)
8(1/0)
12(2/0)
BRA
Byte
Word
10(2/0)
10(210)
-
Byte
Word
18(212)
18(212)
-
BSR
CC true
CC false
-
DBee
10(2/0)
12(2/0)
14(3/0)
CHK
-
40(5/3)+ *
8(110)+
TRAP
-
34(4/3)
-
TRAPV
-
34(5/3)
4(110)
Instruction
Displacement
Bee
+ add effective address calculation time
* indicates maximum value
VI-42
-
JMP, JSR, LEA, PEA, MOVEM INSTRUCTION CLOCK PERIODS
Table 33
Instr
Size
An@
An@+
An@-
JMP
-
8(2/0)
-
JSR
-
16(2/2)
LEA
-
PEA
-
MOVEM
Word
M--R
Long
MOVEM
Word
R_M
Long
An@(d) An@(d,ix)*
xxx.W
xxx.L
-
10(2/0)
14(3/0)
10(2/0)
12(3/0)
10(2/0)
14(3/0)
-
-
18(2/2)
22(212)
18(2/2)
20(3/2)
18(2/2)
22(2/2)
4(1/0)
-
-
8(2/0)
12(2/0)
8(210)
12(3/0)
8(210)
·12(2/0)
12(112)
-
-
16(2/2)
20(2/2)
16(2/2)
20(3/2)
16(2/2)
20(2/2)
12 + 4n 12 + 4n
(3 + n/O) (3 + n/O)
12 + 8n 12 + 8n
(3 + 2n/0) (3 + 2n/0)
8 + 5n
(2In)
8 + 10n
(2/2n)
-
-
-
-
-
-
PC@(d) PC@(d,ix)*
16 + 4n
18 + 4n
16 + 4n 20+4n 16 +4n
18 + 4n
(4 + n/O) (4 + n/O) (4 + n/O) (5 + n/O) (4 + n/O) (4 + n/O)
16 + 8n
18 + 8n
16 + 8n 20+ 8n 16 + 8n
18 + 8n
(4 + 2n/0) (4 + 2n/0) (4 + 2n/0) (5 + 2n/0) (4 + 2n/0) (4 + 2n/0)
8 + 5n 12 + 5n
(2In)
(3/n)
8 + 10n 12 + 10n
(2/2n) (3/2n)
14 + 5n
(3/n)
14 + 10n
(3/2n)
12 + 5n 16 + 5n
(3/n)
(4/n)
12 + 10n 16 + 10n
(3/2n)
(4/2n)
-
-
-
-
-
n is the number of registers to move
* is the size of the index register (ix) does not affect the instruction's execution time
operand instructions. The number of bus read and write
cycles is shown in parenthesis as: (r/w). The number of
clock periods plus the number of read and write cycles must
be added to those of the effective address calculation where
indicated.
the jump, jump to subroutine, load effective address, push
effective address, and move multiple registers instructions.
The number of bus read and write cycles is shown in
parenthesis as: (r/w).
MULTI-PRECISION INSTRUCTION CLOCK PERIODS
SHIFTIROTATE INSTRUCTION CLOCK PERIODS
Table 30 indicates the number of clock periods for the shift
and rotate instructions. The number of bus read and write
cycles is shown in parenthesis as: (r/w). The number of
clock periods plus the number of read and write cycles must
be added to those of the effective address calculation where
indicated.
Table 34 indicates the number of clock periods for the
multi-precision instructions. The number of clock periods
includes the time to fetch both operands, perform the
operations, store the results, and read the next instructions.
The number of read and write cycles is shown in
parenthesis as: (r/w).
BIT MANIPULATION INSTRUCTION CLOCK PERIODS
In Table 34, the headings have the following meanings: Dn
= data register operand and M = memory operand.
Table 31 indicates the number of clock periods required for
the bit manipulation instructions. The number of bus read
and write cycles is shown in parenthesis as: (r/w). The
number of clock periods plus the number of read and write
cycles must be added to those of the effective address
calculation where indicated.
MULTI-PRECISION INSTRUCTION CLOCK PERIODS
Table 34
Size
opDn, Dn
opM,M
ADDX
Byte, Word
Long
4(110)
8(110)
18(3/1 )
30(5/2)
CMPM
Bvte, Word
Long
-
12(3/0)
20(510)
SUBX
Byte, Word
Long
4(110)
8(110)
18(3/1 )
30(5/2)
ABCD
Byte
6(1/0)
18(3/1 )
SBCD
Byte
6(110)
18(3/1 )
Instruction
CONDITIONAL INSTRUCTION CLOCK PERIODS
Table 32 indicates the number of clock periods required for
the conditional instructions. The number of bus read and
write cycles is indicated in parenthesis as: (r/w). The
number of clock periods plus the number of read and write
cycles must be added to those of the effective address
calculation where indicated.
JMP, JSR, LEA, PEA, MOVEM INSTRUCTION CLOCK
PERIODS
Table 33 indicates the number of clock periods required for
VI-43
MISCELLANEOUS INSTRUCTION CLOCK PERIODS
Table 35
Size
Register
Memory
-
6(1/0)
8(1/1 )+
-
-
12(2/0)
12(2/0)+
-
-
12(2/0)
12(2/0)+
-
-
Word
Long
-
-
18(2/2)
24(2/4)
16(4/0)
24(6/0)
EXG
-
6(110)
-
-
--
Word
Long
4(110)
4(1/0)
-
-
-
EXT
LINK
-
16(2/2)
-
-
-
MOVE from USP
-
4(1/0)
-
-
-
MOVE to USP
-
4(1/0)
-
-
-
NOP
-
4(1/0)
-
-
-
RESET
-
132(1/0)
-
-
-
RTE
-
20(510)
-
-
-
RTR
-
20(5/0)
-
-
-
RTS
-
16(4/0)
-
-
-
STOP
-
4(010)
-
-
-
SWAP
-
4(1/0)
-
-
-
UNLK
-
12(3/0)
-
-
-
Instruction
MOVE from SR
MOVE to CCR
MOVE to SR
MOVEP
Register Memory Memory Register
-
+ add effective address calculation time
EXCEPTION PROCESSING CLOCK PERIODS
MISCELLANEOUS INSTRUCTION CLOCK PERIODS
Table 36
Table 35 indicates the number of clock periods for the
following miscellaneous instructions. The number of bus
read and write cycles is shown in parenthesis as: (r/w). The
number of clock periods plus the number of read and write
cycles must be added to those of the effective address
calculation where indicated.
Exception
Periods
Address Error
50(417)
Bus Error
50(417)
Interrupt
44(513)*
EXCEPTION PROCESSING CLOCK PERIODS
Illegal Instruction
34(4/3)
Table 36 indicates the number of clock periods for exception
processing. The number of clock periods includes the time for
all stacking, the vector fetch, and the fetch of the first
instruction of the handler routine. The number of bus read
,md write cycles is shown in parenthesis as: (r/w).
Privileged Instruction
34(4/3)
Trace
34(4/3)
*The interrupt acknowledge bus cycle is assumed to take
four external clock periods
VI-44
AC ELECTRICAL WAVEFORMS
Figure 34
These waveforms should only be referenced in regard to the edge-to-edge measurement ofthe timing specifications. They are not intended as a
functional description of the input and output signals. Refer to other functional descriptions and their related diagrams for device operation.
\~----------~\rl---------
E
~
~-~-------------~5'r_~------------~~--_{
CLK
A23-A1
FC2-FCO
AS _ _ _
i:DS. UOS READ CYCLE
"---,,t:tt=ttCs)=t:::L~~---+--{'4)-----+-J=n-~
-----'
LOS. UOS WRITE CYCLE
R/WWRITE CYCLE
~01
DATA OUT
sS~~
______
~411~
}--
__ ____=1®~47~1'______________~__1~'__~~
=========~ ~
ASYNCHRONOUS INPUTS
(SEE NOTE 1) _ _ _ _ _ _ _ _ _ _ _ __
HALT. RESET (INPUT)- -- -
-
-- -- -
----------~~
_'1 ___ _
~~~
-----------------..
DATA IN- -
-- -
-- -
-- -
-
-
-- -
NOTE1: Setup time for the asynchronous inputs B'ERi'i. BGACK. BR.
DTACK. iP[(j-IPL2. and VPA guarantees their recognition at the next
falling edge of the clock.
NOTE 2: Waveform measurements for all inputs and outputs are
specified at: logic high ~ 2.0 volts. logic low = 0.8 volts,
VI-45
•
AC ELECTRICAL SPECIFICATIONS
(V cc = 5.0 Vdc ± 5%; V ss = 0 Vdc; TA = O°C to 70°C, Figure 31 )
No.
Characteristic
'4 MHz
8 MHz
6 MHz
10 MHz
Symbol MK68000-4 MK68000-6 MK68000-8 MK68000-10
Min Max Min Max Min Max Min Max
Unit
1
Clock Period
tcyc
250
500
167
500
125
500
100
500
ns
2
Clock Width Low
tCl
115
250
75
250
55
250
45
250
ns
3
Clock Width High
tCH
115
250
75
250
55
250
45
250
ns
4
Clock Fall Time
tCI
-
10
-
10
-
10
-
10
ns
5
Clock Rise Time
tCr
-
10
-
10
-
10
-
10
ns
6
Clock Low to Address
tCLAV
-
90
-
80
-
70
-
55
ns
6A
Clock High to FC Valid
tCHFCV
-
90
-
80
-
70
-
60
ns
7
Clock High to Address/Data
High Impedance (maximum)
tCHAZx
-
120
-
100
-
80
-
70
ns
8
Clock High to Address/FC
Invalid (minimum)
tCHAZn
0
-
0
-
0
-
0
-
ns
9'
Clock High to AS, OS Low
(maximum)
tCHS Lx
-
80
-
70
-
60
-
55
ns
10
Clock High to AS, OS Low
(minimum)
tCHSln
0
-
0
-
0
-
0
-
ns
112
Address to AS, OS
(read) Low/ AS Write
t AVSl
55
-
35
-
30
-
20
-
ns
11A2
FC valid to AS, OS
(read) Low/ AS Write
tFCVSl
80
-
70
-
60
-
50
-
p's
12'
Clock Low to AS, OS High
t ClSH
-
90
-
80
-
70
-
55
ns
132
AS, OS High to Address/FC
Invalid
tSHAZ
60
-
40
-
30
-
20
-
ns
142
AS, OS Width Low (read)/
AS Write
tSl
535
-
337
-
240
-
195
-
ns
-
285
-
170
-
115
-
95
-
ns
tSH
285
-
180
-
150
-
105
-
ns
14A2
OS Width Low (Write)
152
AS, OS Width High
16
Clock High to AS, OS High
Impedance
t CHSZ
-
120
-
100
-
80
-
70
ns
172
OS High to R/W High
tSHRH
60
-
50
-
40
-
20
-
ns
18'
Clock High to R/W High (maximum)
tCHRHx
-
90
-
80
-
70
-
60
ns
19
Clock High to R/W High (minimum)
tCHRHn
0
-
0
-
0
-
0
-
ns
20'
Clock High to R/W Low
tCHRl
-
90
-
80
-
70
-
60
ns
212
Address/Valid to R/W Low
t AVRl
45
-
25
-
20
-
0
-
ns
FC Valid to R/W Low
tFCVRl
80
-
70
-
60
-
50
-
ns
21A2
~
VI-46
AC ELECTRICAL SPECIFICATIONS (Continued)
(VCC = 5.0 Vdc ± 5%; VSS =0 Vdc; TA =O°C to 70°C, Figure 31)
No.
Characteristic
4MHz
6MHz
8 MHz
10 MHz
Symbol MK68000-4 MK68000-6 MK68000-8 MK68000-10
Min Max Min Max Min Max Min Max
Unit
222
R/W Low to OS Low (write)
t RLSL
200
-
140
-
80
-
50
-
ns
23
Clock Low to Data Out Valid
t CLOO
-
90
-
80
-
70
-
55
ns
24
Clock High to RIW, VMA High
Impedance
tCHRZ
-
120
-
100
-
80
-
70
ns
25 2
OS High to Data Out Invalid
t SHOO
60
-
40
-
30
-
20
-
ns
26 2
Data Out Valid to OS Low (write)
tOOSL
55
-
35
-
30
-
20
-
ns
27 5
Data In to Clock Low (set up time)
t OICL
30
-
25
-
15
-
15
-
ns
28 2
OS High to DTACK High
tSHOAH
0
240
0
160
0
120
0
90
ns
29
OS High to Data Invalid (hold time)
t SHOI
0
-
0
-
0
-
0
-
ns
30
AS, OS High to BERR High
tSHBEH
0
-
0
-
0
-
0
-
ns
DTACK Low to Data In (setup time)
tOALOI
-
180
-
120
-
90
-
65
ns
31 2,6
32
HALT and RESET Input Transition
Time
tRHrf
0
200
0
200
0
200
0
200
ns
33
Clock High to BG Low
t CHGL
90
-
80
-
70
-
60
ns
34
Clock High to BG High
t CHGH
-
90
-
80
-
70
-
60
ns
35
BR Low to BG Low
tBRLGL
1.5
3.0
1.5
3.0
1.5
3.0
1.5
3.0
36
BR High to BG High
tBRHGH
1.5
3.0
1.5
3.0
1.5
3.0
1.5
3.0
37
BGACK Low to BG High
tGALGH
1.5
3.0
1.5
3.0
1.5
3.0
1.5
3.0
clk.
per.
clk.
per.
clk.
per.
38
BG Low to Bus High Impedance
(with AS high)
tGlZ
-
120
-
100
-
80
-
70
ns
39
BG Width High
tGH
1.5
-
1.5
-
1.5
-
1.5
-
clk.
per.
40
Clock Low to VMA Low
tCLVML
-
90
-
80
-
70
-
70
ns
41
Clock Low to E Transition
tCLE
-
100
-
85
-
70
-
55
ns
42
E Output Rise and Fall Time
tErf
-
25
-
25
-
25
-
25
ns
43
VMA Low to E High
tVMLEH
325
-
240
-
200
-
150
-
ns
44
AS, OS High to VPA High
t SHVPH
0
240
0
160
0
120
0
90
ns
45
E Low to AddressNMAlFC
Invalid
tELAI
55
-
35
-
30
-
10
-
ns
46
BGACKWidth
t BGL
1.5
-
1.5
-
1.5
-
1.5
-
elk.
per.
47
Asynchronous Input Setup Time
tASI
30
-
25
-
20
-
20
-
ns
48
BERR Low to DTACK Low
tBELOAL
50
-
50
-
50
-
50
-
ns
49
E Low to AS, OS Invalid
t ELSI
-80
-
-80
-
-80
-
-80
-
ns
VI-47
•
AC ELECTRICAL SPECIFICATIONS (Continued)
(Vcc = 5.0 Vdc ± 5%; Vss = 0 Vdc; TA = O°C to 70°C, Figure 31)
S MHz
8MHz
4MHz
10 MHz
Symbol MKS8000-4 MKS8000-S MKS8000-8 MKS8000-10
Min Max Min Max Min Max Min Max
Characteristic
No.
Unit
50
EWidth High
tEH
900
-
600
-
450
-
350
-
ns
51
EWidth Low
tEL
1400
-
900
-
700
-
550
-
ns
52
E Extended Rise Time
tCIEHX
80
-
80
-
80
-
80
-
ns
53
Data Hold from Clock High
t CHDO
0
-
0
-
0
-
0
-
ns
54
Data Hold from E Low (Write)
tELDOZ
60
-
40
-
30
-
20
-
ns
55
R/W to Data bus Impedance change
t RLDO
55
-
35
-
30
-
20
-
ns
56
Halt/RESET Pulse Width (Note 4)
t HRPW
10
-
10
-
10
-
10
-
elk.
per.
NOTES:
1. For a loading capacitance of less than or equal to 50 picofarads, subtract 5
nanoseconds from the values given in these columns.
2. Actual value depends on actual clock period.
3. If #47 is satisfied for both 1iTACK and BER'R. #48 may be ns.
a
4. After Vee has been applied for 100 ms.
5. If the asynchronous setup time(#47) requirements are satisfied, the DTACK
low·to-data setup time (#31) requirement can be ignored. The data must
only satisfy the data-in to clock-low setup time (#27) for the following cycle.
AC ELECTRICAL WAVEFORMS - BUS ARBITRATION
Figure 35
RESET TEST LOAD
HALT TEST LOAD
TEST LOADS
Figure 36
Figure 37
Figure 38
+5Vdc
+5 Vdc
+5Vdc
TEST
POINT
9100
RESET
2.90
HALT
I130PF
"
I-
MM07000
OR EQUIVALENT
70PF
C = 130pF
(~ncludes all Parasitics)
RL = 6.0 kO for
AS. A1-A23. BG, O..Q.-015, E__ FCO-FC2, LOS, R/W. UOS, VMA
*R = 1.22 kO for A1-A23. BG.
E, FCO-FC2
VI-48
DC ELECTRICAL CHARACTERISTICS
(Vee = 5.0 Vdc ± 5%; Vss = 0 Vdc; TA = O°C to 70°C, Figures 33, 34, 35)
Characteristic
Symbol
Min
Max
Unit
Input High Voltage
V 1H
2.0
Vee
Vdc
Input Low Voltage
V 1L
Vss - 0.3
0.8
Vdc
lin
-
2.5
MAdc
-
20
ITS1
-
20
MAdc
V OH
2.4
-
Vdc
Input Leakage Current
@5.25V
BERR,BGACK,BR,VPA,
DTACK, CLOCK, IPLO-IPL2
HALT, RESET
Three-State (Off State) Input Current
@2.4V/O.4V
AS, A 1-A23, 00-D15,
FCO-FC2, LDS,
RIW, UDS, VMA
Output High Voltage (lOH = -400 MAdc) AS, A1-A23, BG,
00-D15, E, FCO-FC2,
IDS, R/W, UDS, VMA
E*
Output Low Voltage
(lOL = 1.6mA)
(lOL = 3.2mA)
(lOL = 5.0mA)
(lOL = 5.3mA)
V ce-O·75
HALT
A1-A23, BG, E, FCO-FC2
RESET
E, AS, 00-D15, LDS, RIW,
UDS,VMA
Power Dissipation (Clock Frequency =
8 MHz)
Capacitance (Package Type Dependent)
(Vin = 0 Vdc; TA = 25°C;
Frequency = 1 MHz)
*with external pull up register of 470
n
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
Supply Voltage
Vee
-0.3 to + 7.0 Vdc
Input Voltage
V in
-0.3 to + 7.0 Vdc
Operating Temperature
TA
Oto70
°C
Storage Temperature
Tstg
-55 to 150
°C
VI-49
-
0.5
0.5
0.5
0.5
PD
-
1.5W
W
Cin
-
10.0
pF
VOL
Vdc
•
MK68000 ORDERING INFORMATION
PART
NO.
PACKAGE
TYPE
MAX. CLOCK
FREQUENCY
MK6S000P-4
Ceramic
4.0 MHz
MK6S000P-6
Ceramic
6.0 MHz
MK6S000P-S
Ceramic
S.O MHz
MK6S000P-10
Ceramic
10.0 MHz
TEMPERATURE
RANGE
0° to 70°C
VI-50
MOSTEI(.
MICROCOMPUTER COMPONENTS
16-Bit Single-Chip Microcomputer
MK68200
FEATURES
MK68200 LOGICAL PIN OUT
Figure 1
o 16-bit high performance single-chip microcomputer
15
o 14 address and data registers
Eight 16-bit or sixteen 8-bit data registers
Six 16-bit address registers
o Advanced 16-bit instruction set
Bit, byte, and word operands
9 Addressing modes
Byte and word BCD arithmetic
14
13
13
12
12
11
11
10
10
9
PORT
0
o High performance (6 MHz clock)
500 ns register-to-register move or add
3.5 J.IS 16x16 multiply
4.0 J.Ls 32/16 divide
8
8
7
7
6
6
XI2
5
XI1
4
}
•
EXTERNAL
INTERRUPT
2
RCLK
SERIAL
SO
o 256 byte RAM (128 x 16)
o Three 16-bit timers
Interval modes
Event modes
One-shot modes
Pulse and period measurement modes
Two input and two output pins
o Interrupt controller
16 independent vectors
8 external interrupt sources
1 non-maskable interrupt
Individual interrupt masking
o Optional external bus
16-bit multiplexed address/data bus
Mask-programmable control bus options
1
'=}
MK68200
2
o 4K byte ROM (2K x 16)
o Parallel I/O
Up to 40 pins
Direction programmable by bit
8- or 16-bit ports with handshaking
"'ORT
4 XIO
3
o
o Serial channel
Double buffered receive and transmit
Asynchronous to 250 Kbps
Synchronous to 1 Mbps
Address wake-up recognition and generation
Internal/external Baud rate generation
1/0 15
1/0
14
1/0
1/0 0
51
Vee
I
0
15TAO
GND
I
0
14 TBO
~
I
I
13TAI
CLKOUT
0
I
12 TBI
CLK1
I
I
CLK2
I
NMi
I
0
"
MODE
I
0
8
}n.,,,
"""}
10STRL
9 RDYH
PORT
4
PORTO
HANDSHAKE
ROYL
MK68000-compatible bus
General-purpose bus
Automatic bus request/grant arbitration
o 6 MHz clock
Crystal or external TIL clock
o Single +5 volt power supply
048 pin DIP
INTRODUCTION
The MK68200 is the first of a new family of highperformance 16-bit single-chip microcomputers from
Mostek. Implemented in Scaled Poly-5 NMOS, it combines
a modern, comprehensive instruction set architecture with
extensive, flexible I/O capabilities. 4K Bytes of on-chip
ROM and 256 Bytes of on-chip RAM are provided within a
full 64K Byte Address Space, allowing for expansion in
future family members. In addition, the on-chip I/O
capabilities will change and grow to meet the needs of the
marketplace.
VI-51
The MK68200 is designed to serve the needs of
microcomputer applications requiring high performance
and low cost, such as industrial control and instrumentation. High speed mathematical ability, rapid I/O addressing
and interrupt response, and powerful bit manipulation
instructions provide the necessary tools for th~se
applications. Also, where multiple processors or distributed
intelligence is required, several MK68200 processors may
be interconnected by either a single serial channel or a
shared parallel bus as illustrated in Figure 2. The on-chip
resources such as ROM, RAM, and I/O are accessed within
each MK68200 without affecting the utilization of the
shared bus so that only external communications compete
for bus bandwidth.
DISTRIBUTED PROCESSING
Figure 2
SERIAL
PROCESSOR ARCHITECTURE
The MK68200 microcomputer contains an advanced
processor architecture, combining the best properties of
both 8- and 16-bit processors, since most instructions
operate on either byte or word operands.
REGISTERS
The MK68200 register set includes 3 system registers, 6
address registers, and 8 data registers. The three 16-bit
system registers, as shown in Figure 4, include a Program
Counter, Status Register, and Stack Pointer. The 6 address
registers may be used either for 16-bit data or for memory
addressing. The eight 16-bit data registers are used for data
and may also be referenced as sixteen 8-bit registers,
providing great flexibility in register allocation.
REGISTER SET
PARAllEL
Figure 4
I--------~I :
t--------t
SYSTEM
REGISTERS
A5
ADDRESS
REGISTERS
EXTERNAL BUS
~________________~
In addition, the MK68200 can be used as a very costeffective peripheral controller in MK68000 systems. Here,
the MK68200's instruction set similarity and direct bus
compatibility with the MK68000 make it an ideal choice to
perform many intelligent I/O functions in the system. For
instance, since the MK68200 includes both a serial channel
and an external bus capable of performing DMA transfers, it
can be programmed to act as a Serial DMA Controller, as
shown in Figure 3.
DH7
DL7
AO
07
DATA
REGISTERS
DHO
SERIAL DMA CONTROLLER
Figure 3
15
DLO
8
7
DO
o
ADDRESSING
SERIAL
CHANNEL
The MK68200 directly addresses a 64K byte memory
space, which is organized as 32K 16-bit words. The
memory is byte-addressable, but most transfers occur 16
bits at a time for increased performance over 8-bit
microcomputers. AI/Input/Output is memory-mapped, and
theon-chip I/O is situated in the top 1K bytesofthe address
space, as depicted in Figure 5.
VI-52
ADDRESS SPACE
Figura 5
INSTRUCTION EXECUTION TIMES
Table 2
FFFF
1K
1/0
PORTS
Instruction Type
Clock
Periods
Execution Time
with 6 MHz
clock (/lS)
Move Register-to-register
3
0.5
Add Register-to-register
(binary or BCD)
3
0.5
Move Memory-to-register
6
1.0
Add Register-to-memory
9
1.5
Multiply (16x16)
21
3.5
Divide (32/16)
23
3.84
Move Multiple (save or
restore all registers)
55
9.2
FCOO
266
RAM
FBOO
1000
4K
ROM
o
Nine addressing modes provide ease of access to data in the
MK68200, as depicted in Table 1. The four Register Indirect
forms utilize the address registers and the stack pointer and
support many common data'structures such as arrays,
stacks, queues, and linked lists. I/O Port addressing is a
short form address for the first 16 words of the I/O port
space and allows most instructions to access the most often
referenced I/O data in just one word. Many microcomputer
applications are I/O intensive, and short, fast addressing of
I/O has a significant impact on performance.
ADDRESSING MODES
Table 1
Register
Register Indirect
Register Indirect with Post-increment
Register Indirect with Pre-decrement
Register Indirect with Displacement
Program Counter Relative
Memory Absolute
Immediate
I/O Port
In addition to operations on bytes and words, the MK68200
has rapid bit manipulation instructions which can operate
on both registers and memory. The bit to be affected may be
an immediate operand of the instruction or may be
dynamically specified in a register. Operations available
include bit set, clear, test, change, and exchange; and all bit
operations always perform a bit test as well. Since each
instruction is indivisible, this provides the necessary testand-set function for the implementation of semaphores.
The MOVE group of instructions has the most extensive
capabilities. A wide variety of combinations of addressing
modes are supported, including memory-to-memory
transfers. A special Move Multiple is included to save and
restore a specified portion of the registers rapidly.
In total, the MK68200 instruction set provides a
programming environment similar to the MK68000 which
has been optimized for the needs of the single-chip
microcomputer marketplace. A summary of the instruction
set is provided in Table 3.
INPUT/OUTPUT ARCHITECTURE
INSTRUCTIONS
The MK68200 instruction set has been designed with
regularity and ease of programming in mind. In addition,
instructions have been encoded to minimize code space, a
feature which is especially important in single-chip
microcomputers. Small code space is related to execution
speed, and most instructions execute in either 3 or 6 clock
periods. (A clock period is equal to 167 ns with a 6 MHz
clock.) See Table 2.
The I/O capabilities of the MK68200 are extensive,
encompassing timers, a serial channel, parallel I/O, and an
interrupt controller. All ofthese devices are accessible to the
programmer as ports within the top 1K bytes of the address
space, and the most commonly accessed ports may be
accessed with the short Port Addressing mode.
In total, 40 pins out of the 48 are used for I/O, and the
functions they perform are highly programmable by the
user. In particular, many pins can perform multiple
.functions and the programmer selects which ones are to be
VI-53
•
INSTRUCTION SET SUMMARY
Table 3
INST
DESCRIPTION
INST
DESCRIPTION·
ADD
ADD.B
AD DC
ADDC.B
AND
AND.B
ASL
ASL.B
ASR
ASR.B
BCHG
BCLR
BEXG
BSET
BTST
CALLA
CALLR
CLR
CLRB
CMP
CMP.B
DADO
DADD.B
DADDC
DADDC.B
Add
Add Byte
Add with Carry
Add with Carry Byte
Logical And
Logical And Byte
Arithmetic Shift Left
Arithmetic Shift Left Byte
Arithmetic Shift Right
Arithmetic Shift Right Byte
Bit Test and Change
Bit Test and Clear
Bit Test and Exchange
Bit Test and Set
Bit Test
Call Absolute
Call Relative
Clear
Clear Byte
Compare
Compare Byte
Decimal Add
Decimal Add Byte
Decimal Add with Carry
Decimal Add with Carry Byte
Disable Interrupts
Divide Unsigned
Decrement Count and Jump if
Non-zero
Decrement Count Byte and Jump
if Non-zero
DeCimal Negate
Decimal Negate Byte
Decimal Negate with Carry
Decimal Negate with Carry Byte
Decimal Subtract
Decimal Subtract Byte
Decimal Subtract with Carry
Decimal Subtract with Carry Byte
Enable Interrupts
Exclusive Or
Exclusive Or Byte
Exchange
Exchange Byte
Extend Sign
HALT
JMPA
JMPR
LlBA
LlWA
LSR
LSRB
MOVE
MOVE.B
MOVEM
MOVEM.B
MULS
MULU
NEG
NEG.B
NEGC
NEGC.B
NOP
NOT
NOT.B
OR
ORB
POP
POPM
PUSH
PUSHM
RET
RETI
ROL
ROL.B
ROLC
ROLC.B
ROR
RORB
RORC
RORC.B
SUB
SUB.B
SUBC
SUBC.B
TEST
TEST.B
TESTN
TESTN.B
Halt
Jump Absolute
Jump Relative
Load Indexed Byte Address
Load Indexed Word Address
Logical Shift Right
Logical Shift Right Byte
Move
Move Byte
Move Multiple Registers
Move Multiple Registers Byte
Multiply Signed
Multiply Unsigned
Negate
Negate Byte
Negate with Carry
Negate with Carry Byte
No Operation
One's Complement
One's Complement Byte
Logical Or
Logical Or Byte
Pop
Pop Multiple Registers
Push
Push Multiple Registers
Return from Subroutine
Return from Interrupt
Rotate Left
Rotate Left Byte
Rotate Left through Carry
Rotate Left through Carry Byte
Rotate Right
Rotate Right Byte
Rotate Right through Carry
Rotate Right through Carry Byte
Subtract
Subtract Byte
Subtract with Carry
Subtract with Carry Byte
Test
Test Byte
TestNot
Test Not Byte
01
DIVU
DJNZ
DJNZ.B
DNEG
DNEG.B
DNEGC
DNEGC.B
DSUB
DSUB.B
DSUBC
DSUBC.B
EI
EOR
EORB
EXG
EXG.B
EXT
VI~54
used. For example, TAl may be used as an inputforTimer A,
an interrupt source, or a general input pin, and the interrupt
source may be selected simultaneously with either of the
other functions. Refer to the Logical Pin Out Figure 1.
TIMERS
In addition to the typical USART functions, the serial
channel can transmit and receive several special wake-up
modes by appending a Wake-up bit to each data word, as
illustrated in Figure 7.
SERIAL FRAME WITH WAKE-UP
Figure 7
There are 3 full 16-bit timers on-chip. The first two (A and B)
provide a variety offunctions while the third (C) may be used
either as an interval timer or a baud rate generator for the
serial channel. Most significant timer events, such as a
count match or a timer input signal transition can generate
interrupts to the processor. Timers A and B also each have
associated input and output pins.
TIMER MODES
Table 4
Timer
Modes
A
A
A
Interval
Event
Pulse Width and Period Measurement
B
B
B
Interval
Retriggerable One-shot
Non-retriggerable One-shot
C
C
Interval
Baud Rate Generation
START ILSB __D_A_TA_ _ MJL._P_A_RI_TY-II_W_A_K_E_,u_pJ.I_ST_O_p........
This Wake-up bit is used to differentiate normal data words
and special address words. The receiver can be
programmed to receive only address words or only address
words with a specific data value. In this way, the processor
can be interrupted only when it receives its particular
address and can then change mode to receive the following
data words. Wake-up capability is especially useful when
several MK68200 microcomputers are interconnected on
one serial link.
PARALLEL 1/0
Two 16-bit ports, PO and Pl, may be usedforparallell/O.lf
individual bits are desired, each of the 32 bits may be
separately defined as input or output. Bits may be grouped
to provide the exact data widths desired. Port 0 has the
additional capability of operating under the control of
external handshaking signals. 8- or 16-bit sections of PO
may be individually controlled as input, output, or
bidirectional 1/0. Two pairs of Ready and Strobe signals
provide the necessary control.
SERIAL CHANNEL
The Serial Channel on the MK68200,as shown in Figure 6,
is a full-duplex USART with double buffering on both
transmit and receive. Word length, parity, stop bits, and
modes are fully programmable. The asynchronous mode
supports bit rates up to 250 Kbps, and the byte synchronous
mode operates up to 1 Mbps. Either internal or external
clocks may be used.
SERIAL CHANNEL
Figure 6
PO
81
.,8 r--=______--,
10,1) L -_ _ _- - - '
INTERRUPT CONTROLLER
The MK68200interrupt controller provides rapid service of
up to 16 interrupt sources, each with a unique internal
vector. The lowest 16 words of the address space contain
the starting addresses of the service routines of each
potential interrupt source, as shown in Figure 8.
Interrupt sources are prioritized in the order shown, with
Reset having highest priority. A single non-maskable
interrupt (NMI) is provided. All ofthe other sources share an
interrupt enable bit in the processor status register. This bit
is automatically cleared whenever an interrupt is acknowledged. Also, each of these sources has a corresponding
individual enable bit. This feature allows selective enabling
of particular interrupts, including the ability to choose any
priority scheme desired with only minimal software
overhead. In fact, 15 levels of nested priority may be
programmed.
EXTERNAL BUS
80
When it is necessary to expand beyond the on-chip
complement of RAM, ROM, or 1/0, orwhen DMA access to
external memory space is desired, the MK68200 may be
placed in an external bus mode. The selection of single-chip
VI-55
II
INTERRUPT SOURCES
Figure 8
VECTOR LOCATION
NAME
MNEMONIC
Reset
Non-Maskable Interrupt
RESET
NMI
0000
Spare
External Interrupt 2
Strobe'L'
Timer 'A' Output Interrupt
S
XI2
STRL
TAOI
TAl
STRH
RSCI
RNI
Xll
TBOI
TBI
XIO
XMTI
TCI
0004
Timer 'A' Input
Strobe 'H'
Receive Special Condition Interrupt
Receive Normal Interrupt
External Interrupt 1
Timer 'B' Output Interrupt
Timer 'B' Input
External Interrupt 0
Transmit Interrupt
Timer C Interrupt
0006
0008
oooA
OOOC
oooE
0010
0012
0014
0016
0018
00lA
00lC
00lE
1/0 or external bus is accomplished by the Mode pin at
Reset time. Port 0 and a portion of Port 1 are reconfigured to
provide the necessary bus functions. Figure 9 illustrates the
external bus logical pin out.
EXTERNAL BUS LOGICAL PIN OUT
Figure 9
UPC
GP
14 01)§
'SLDS
AI
[jj
'3
13 R/Vi
R/W
'2
12
11
,.
15
1/0
"'0
iiGACK ~
I:rfACK ~
'O~
MULTIPLEXED
ADDRESS/
DATA
BUS
I
1m
aUSIN
8
iR
BUSOUT
CONTROL
BUS
,
PORT
I/O 7
MK68200
6
XI2
5
XI1
4
XIO
:,
o
1/0
c= ~
ec
•
elK1
I
V
CLK2
I
NMi
I
1/0
0
0
51
:
}
)
TIMERS
11 STRH}
10 STRL
0
9
RDVH
MODE L,...;..,'_ _ _ _-=:.O.J 8
RDYL
-
Port 0 becomes the 16-bit multiplexed AddresslData bus,
and half of Port 1 becomes the Control bus. Two different
,Control busses are available as a mask-option: a Universal
Peripheral Controller(UPC) bus which generates MK68000compatible control signals and a General Purpose (GP) bus
which provides control signals which can be used to
interface to a wide variety of existing busses.
The UPC Control bus is easily connected to an MK68000
system bus with the simple addition of an external address
latch, as shown in Figures 3 and 10. With the UPC Control
bus, the MK68200 always acts as a bus requester in a
system with the MK68000 typically as a bus master. Once
the UPC has gained mastership of the system bus, it may
proceed to perform DMA transfers or to communicate with
other I/O devices in the system.
GP CONTROL BUS
SO
~ :~
LEVEL 1
EXTERNAL
} INTERRUPT
:~~ }SERIAl
'5 TAO
-
UPC CONTR.OL BUS
A§
9
LEVEL 2
0002
PORT
•
PORTO
HANDSHAKE
The GP Control bus is provided to allow connection to
non-MK68000 systems and to support systems of multiple
MK68200 microcomputers better. The control signals have
been designed to be able to generate the appropriate control
signals of many available bus systems, with only a small
amount of external logic. For the multiple microcomputer
case, the GP bus provides BUSIN and BUSOUT, two signals
which are used for bus arbitration. At Reset time, these two
pins are configured so that the MK68200 may act as either
a bus requester or the bus granter. When several
microcomputers are connected together on a. shared GP
VI-56
bus, only a simple bus arbiter is required in external logic. If
exactly two processors are used, no external logic is needed.
UPC BUS INTERFACE
Figure 10
-
16
L
A
T
C
BUS OPERATION
ADDRESS
H
~E
As mentioned previously, the selection of single-chip 1/0
DATA
AID
AS
UDS
LOs
M
K
MK6BOOO
SYSTEM
BUS
R/iN
6
B
2
0
0
DTACK
iiR
BG
BGACK
pins or an external bus is made with the Mode pin. The
Mode pin is also used to determine the portion of the
address space which is placed on the external bus. In all
cases, the on-chip 1/0 Ports and on-chip RAM are retained.
However, the on-chip ROM may be either kept or removed
from the address space. Keeping the ROM allows the
designer primarily to access internal resources with
occasional external references. This mode allows the
maximum amount of concurrent processing in multiprocessor configurations. As long as references remain
on-chip, the external bus will be tri-stated and unaffected by
the processor. The bus request/grant logic within the
MK68200 monitors each memory reference in order to
detect external bus addresses. Whenever such a reference
is about to occur, the logic automatically holds the processor
in an internal wait state as it proceeds to obtain mastership
of the bus. As soon as the bus is obtained, the processor is
allowed to continue the reference. This procedure is
invisibleto the running program. 1ft he next reference is also
an external address, the bus is retained.
1/0 PORT SUMMARY
TableS
PORT
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
FUNCTION
16 External 1/0 pins
16 External 1/0 pins (including Interrupt, Serial, and Bus Control)
(reserved)
Serial Transmit (Low byte) and Receive (High byte) Buffers
8 External 1/0 pins (Timer Control and Port 0 Handshake Control)
(reserved)
(reserved)
Interrupt Latches
Interrupt Enable Register
Serial 1/0 Receive Control and Status Register
Serial 1/0 Transmit Control and Status Register
Timer B Latch
Timer A, Low Latch
Timer A, High Latch
Timer Control, Interrupt Edge Select
Port 0 Handshake Mode bits, Bus Lock, Bus Segment bits
Port 0 Direction Control (DDRO)
Port 1 Direction Control (DDR1)
Serial 1/0 Mode and Sync Registers
Timer C Latch
VI-57
•
VI-58
t!J
UNITED
MICROCOMPUTER
COMPONENTS
TECHNOLOGIES
MOSTEK
PARALLEL INTERFACEITIMER (PI/T)
MK68230P8/MK68230P10
MK68230 PARALLEL INTERFACE/TIMER
The MK68230 Parallel InterfacelTimer provides versatile
double buffered parallel interfaces and an operating system
oriented timer to MK68000 systems. The parallel interfaces
operate in unidirectional or bidirectional modes, either 8 or
16 bits wide. In the unidirectional modes. an associated
data direction register determines whether the port pins are
inputs or outputs. In the bidirectional modes the data
direction registers are ignored and the direction is
determined dynamically by the _state of four handshake
pins. These programmable handshake pins provide an
interface flexible enough for connection to a wide variety of
low, medium. or high speed peripherals or other computer
systems. The PI/T poltS allow use of vectored or
autovectored interrupts. and also provide a DMA Request
pin for connection to the MK68450 Direct Memory Access
Controller or a similar circuit. The PIIT timer contains a
24-bit wide counter and a 5-bit prescaler. The timer may be
clocked by the system clock (PI/T ClK pin) or by an external
clock (TIN pin). and a 5-bit prescaler can be used. It can
generate periodic interrupts, a square wave, or a single
interrupt after a programmed time period. Also it can be
used for elapsed time measurement or as a device
watchdog.
II
PIN ASSIGNMENT
• MK68000 Bus Compatible
06_
06
07
PAO
PA1
PA2
PA3
PA4
PA6
PA6
PA7
• Port Modes Include:
Bit I/O
Unidirectional 8-Bit and 16-Bit
Bidirectional 8-Bit and 16-Bit
• Selectable Handshaking Options
• 24-Bit Programmable Timer
• Software Programmable Timer Modes
Vee
• Contains Interrupt Vector Generation logic
H1
• Separate Port and Timer Interrupt Service Requests
H3
H4
• Registers are Read/Write and Directly Addressable
PBO
PB1
PB2
PB3
PB4
PB6
H2
• Registers are Addressed for MOVEP (Move Peripheral)
and DMAC Compatibility
PB~
PB7
VI-59
----------
-------------
44
43
42
41
40
39
38
g 37
N
36
36
34
:::E
33
32
31
30
29
28
27
26
26
J..;..-_ _-=:J
!
04
03
02
01
DO
RIW
I5'I'XCR
CS
ClK
-RE!!T
Vss
PC7/T1ACK
Pe6/PiACi(
PC6/PIRQ
PC4/DMAREQ
Pe3/TOUT
PC2/TIN
PC1
PeO
RS1
RS2
RS3
RS4
RS6
PIIT SYSTEM BLOCK DIAGRAM
Figure 1
PAO·7
PBO·7
H2
H3
MK68000
H4
1------1 PC5/PiRo.
PC41
t----tPC3ITOUT
6MAfiEO.
PC21TIN
MK68230
PI/T
PC'
pco
~------~~~
mET
GENERAL DESCRIPTION
The PI/T consists of two logically independent sections: the
ports and the timer. The port section consists of Port A
(PAO-7), Port B (PBO-7), four handshake pins (H1, H2, H3,
and H4), two general 1/0 pins, and six dual-function pins.
The dual-function pins can individually operate as a third
port (Port C) or an alternate function related to either Ports A
and B, or the timer. The four programmable handshake
pins, depending on the mode, can control data transfer to
and from the ports, or can be used as interrupt generating
inputs, or 1/0 pins.
Vss
The timer consists of a 24-bit counter, optionally clocked by
a 5-bit prescaler. Three pins provide complete timer 110:
PC2/T1N, PC3/TOUT, and PC7/TlACR. Of course, only the
ones needed for the given configuration perform the timer
function, while the others remain Port CliO.
The system bus interface provides for asynchronous
transfer of data from the PI/T to a bus master over the data
bus (00-07). Oata transfer acknowledge (OTACK), register
selects (RS1-RS5), chip select, the readlwrite line (RIW),
and Port Interrupt Acknowledge (PlACK) or Timer Interrupt
Acknowledge (TIACK) control data transfer between the
PI/T and the MK68000.
VI-60
MK68230 BLOCK DIAGRAM
Figure 2
38
Vss
39
R"E'SEf
40
ClK
41
CS
42
DTACK
43
44
R/W DO
45
01
46
02
47
03
48
04
1
05
2
06
3
07
t t t
DATA 8US INTERFACE AND
INTERRUPT VECTOR REGISTERS
r---,..___ PAO
' - - - - - - - - - - - - ' L _ _ _ _ _--"".
INTERNAL
DATA BUS
PORT
INTERRUPTI
DMA
CONTROL
lOGIC
PORT
A
4
t---PA1 6
!----PA2 6
! - -__ PA3 7
!----PA4 8
i---PAS 9
i - - - P A 6 10
L~_J--·PA7 11
---Vee 12
HANDSHAKE
CONTROllERS
AND
MODE lOGIC
H1
H2
H3
13
14
1S
16
L-==~-J~~-H4
TIMER
r-'---,..___ PBO
17
!--_PB1
18
i----PB3
!----PB4
i----PBS
i----PB6
_ _...J---PB7
20
21
22
23
24
! - -__ PB2 19
PORT
B
L
PORT C AND PIN FUNCTION MULTIPLEXER
PC7/
TIACK
37
PC6/
PlACK
36
PCS/
PIRQ
36
PC4/ pe3/TOUT PC2/TIN PC1
33
32
31
34
iSMAiiEQ
VI-61
PCO
30
+
RSS
2S
..
PI/T PIN DESCRIPTION
Throughout the data sheet, signals are presented using the
terms active and inactive or asserted and negated
independent of whether the signal is active in the highvoltage state or low-voltage state. (The active state of each
logic pin is given below.) Active low signals are denoted by a
superscript bar. R/W indicates a 'write' is active low and a
'read' active high.
lOGICAL PIN ASSIGNMENT
Figure 3
ClK - Clock Input. The clock pin is a high-impedance
TTL-compatible signal with the same specifications as the
MK68000. The PI/T contains dynamic logic throughout,
and hence this clock must not be gated off at any time. It is
not necessary that this clock maintain any particular phase
relationship with the MK68000 clock. It may be connected
to an independent frequency source (faster or slower) as
long as all bus specifications are met.
PAO-7
00-07
PBO-7
RS1-RS6
R/W
MKSB230
PIIT
CLK
Vee
GNO
RESET - Reset Input. RESET is a high-impedance input
used to initialize all PI/T functions. All control and data
direction registers are cleared and most internal operations
are disabled by the assertion of RESET (low).
~
H1
H2
H3
H4
PC7/TIACK'
PCS/PIACK'
PC6/PiiiQ'
PC4/0MAREQ'
PC3/TOUT'
PC2/TIN'
PC1
________~~PCO
'Individually Programmable Dual-Function Pin
00-07 - Bidirectional Data Bus. The data bus pins 00-07
form an 8-bit bidirectional data bus to/from the MK68000
or other bus master. These pins are active high.
RS1-RS5 - Register Selects. RS1-RS5 are active high
high-impedance inputs that determine which of the 25
possible registers is being addressed. They are provided by
the MK68000 or other bus master.
RIW - Read/Write Input. R/w is the high-impedance
Read/Write signal from the MK68000 or bus master,
indicating whether the current bus cycle is a read (high) or
write (low) cycle.
CS - Chip Select Input. CS is a high-impedance input that
selects the PI/T registers for the current bus cycle. Address
strobe and the data strobe (upper or lower) of the bus
master, along with the appropriate address bits, must be
included in the chip select equation. A low level
corresponds to an asserted chip select.
DTACK - Data Transfer Acknowledge Output. DTACK is
an active low output that signals the completion of the bus
cycle. During read or interrupt acknowledge cycles, DTACK
is asserted by the MK68230 after data has been provided on
the data bus; during write cycles it is asserted after data has
been accepted at the data bus. Data transfer acknowledge is
compatible with the MK68000 and with other Mostek bus
masters such as the MK68450 DMA controller. A holding
resistor is required to maintain DTACK high between bus
cycles.
PAO-PA7and PBO-PB7 - PortAand Port B. Ports A and B
are 8-bit ports that may be concatenated to form a l6-bit
port in certain mo.des. The ports may be controlled in
conjunction with the handshake pins Hl-H4. For
stabilization during system power-up, Ports A and B have
internal pullup resistors to Vcc. All port pins are active high.
H 1-H4 - Handshake pins (1/0 depending on the Mode and
Submode). Handshake pins Hl-H4 are multi-purpose pins
that (depending on the operational mode) may provide an
interlocked handshake, a pulsed handshake, an interrupt
input (independent of data transfers), or simple I/O pins. For
stabilization during system power-up, H2 and H4 have
internal pullup resistors to Vcc. Their sense (active high or
low) may be programmed in the Port General Control
Register bits 3-0. Independent of the mode, .the
instantaneous level of the handshake pins can be read from
the Port Status Register.
Port C - (PCO-PC7/ Alternate function). This port can be
used as eight general purpose 1/0 pins (PCO-PC7) or any
combination of six special function pins and two general
purpose 110 pins (PCO-PC1). (Each dual function pin can be
standard 1/0 or a special function independent of the other
port C pins.) The dual function pins are defined in the
following paragraphs. When used as a port C pin, these pins
are active high. They may be individually programmed as
inputs or outputs by the Port C Data Direction Register.
The alternate functions (TIN, TOUT, and TIACK) are timer
1/0 pins. TIN may be used as a rising-edge triggered
external clock input or an external runlhalt control pin (the
timer is in the run state if runlhalt is high and in the halt
state if runlhalt is low). TOUT may provide an active low
timer interrupt request output or a general-purpose squarewave output, initially high. TIACK is an active low highimpedance input used for timer interrupt acknowledge.
Port A and B functions have an independent pair of active
low interrupt request (PIRQ) and interrupt acknowledge
(PlACK) pins.
The DMAREQ (Direct Memory Access RequE!st) pin
provides an active low Direct Memory Access Controller
VI-62
REGISTER MODEL
(DMAC) request pulse of 3 clock cycles, completely
compatible with the MK68450 DMAC.
A register model that includes the corresponding Register
Selects is shown in Table 1.
REGISTER MODEL
Table 1
7
·
o
5
4
3
2
H34
Enable
H12
Enable
H4
Sense
H3
Sense
6
Port Mode
Control
SVCRO
Select
H2
Sense
H1
Port General
Sense Control Register
Port Interrupt
Priority Control
Interrupt
PFS
Port Service
Request !;legister
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
PortAData
Direction Register
Bit
7
Bit
6
Bit
Bit
5
4
Bit
3
Bit
2
Bit
1
Bit
0
Port B Data
Direction Register
Bit
7
Bit
6
Bit
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
Port C Data
Direction Register
5
·
Interrupt Vector Number
·
Port Interrupt
Vector Register
PortA
Submode
H2 Control
H2
Int
Enable
H1
SVCRO
Enable
H1
Stat
Ctrl.
PortB
Submode
H4 Control
H4
Int
Enable
H3
SVCRO
Enable
H3
Stat
Ctrl.
Register
Port A Control
Register
Port B Control
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
Port A Data
Register
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
Port B Data
Register
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
Register
Bit
4
Bit
3
Bit
2
Bit
1
Bit
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
H2
Level
H1
Level
H4S
H3S
H2S
H1S
Bit
7
Bit
6
Bit
Bit
7
Bit
6
Bit
Bit
7
Bit
6
Bit
7
Bit
6
Bit
5
Bit
5
Bit
7
Bit
6
H4
Lewl
H3
Lewl
5
5
0
0
Port A Alternate
Port B Alternate
Register
Port C Data
Register
Port Status
Register
·· ·· ·· ·· ··· ·· ·· ··
(null)
Bit
7
Bit
6
Bit
5
Bit
4
kBit
3
Bit
2
Bit
1
Bit
0
Timer Interrupt
Vector Register
Bit
23
Bit
22
Bit
21
Bit
20
Bit
19
Bit
18
Bit
17
Bit
16
Counter Preload
Register (High)
Bit
15
Bit
14
Bit
13
Bit
12
Bit
11
Bit
10
Bit
9
Bit
8
(Mid)
Bn
7
Bit
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
(Low)
6
Bit
23
Bit
22
Bit
21
Bit
20
Bit
19
Bit
18
Bit
17
Bit
16
Count Register
(High)
Bit
15
Bit
14
Bit
13
Bit
12
Bit
11
Bit
10
Bit
9
Bit
B
(Mid)
Bit
7
Bit
6
Bit
5
Bit
4
Bit
Bit
2
Bit
1
Bit
0
(Low)
TOUT/TlACK
Control
·
·
·
···
··
·
·
·
···
··
·
·
·
···
··
·
·
·
···
··
·Unused, read as zero.
VI-63
Timer Timer Control
Enable Register
Clock
Control
ZD
Ctrl.
·
·
3
·
··
··
·
·
·
·
···
··
(null)
·
·
·
··
··
·
·
·
ZDS
··
··
·
(null)
(null)
Timer Status
Register
(null)
(null)
(null)
(null)
(null)
•
H2 -
Status/interrupt generating input,
general-purpose output, or operation with
H1 in the interlocked or pulsed input
handshake protocols
Submode 01 - Double-Buffered Output
H1 - Indicates data received by peripheral
H2 - Status/interrupt generating input,
general-purpose output, or operation with·
H1 in the interlocked or pulsed input
handshake protocols
Submode 1X - Bit I/O
H1 - Status/interrupt generating input
H2 - Status/interrupt generating input or
general-purpose output
Port B, H3 and H4 - Identical to Port A. H1 and H2
PORT CONTROL STRUCTURE
The primary focus of most applications will be on Ports A
and B, the handshake pins, the portinterrupt pins, and the
DMA request pin. They are controlled in the following way:
the Port General Control Register contains a 2-bit field that
specifies a set of four operation modes. These govern the
overall operation of the ports and determine their
interrelationships. Some modes require additional information from each port's control register to further define its
operation. In each port control register, there is a 2-bit
submode field that serves this purpose. Each port
mode/submode combination specifies a set of programmable characteristics that fully defines the behavior of that
port and two of the handshake pins. This structure is
summarized in Table 2 and Figure 4.
PORT MODE LAYOUT
Figure 4
MODE 0 SUBMODE 00
MODE 0 SUBMODE 01
:-_~w II~
OUTPUT
MODE 1 PORT B SUBI!!IODE XO
H1 IH3)
H1 IH3)
H21H4)
H21H4)
MODE 1 PORT B SUBMODE X1
H1
H1
H2
AANDB
116)
H3
H3
L-.r---H4
<--r---- H4
MODE 3
MODE 2
V
BIT 1/0
AI8)
.,
MODEOSUBMODE1X
~.
'\r/
AANDB
116)
81DIRECTIONAL 16-BIT
PORT MODE CONTROL SUMMARY
Table 2
Mode 0 (Unidirectional 8-Bit Mode)
PortA
Submode 00 - Double-Buffered Input
H1 - Latches input data
Mode 1 (Unidirectional 16-Bit Mode)
Port A - Double-Buffered Data (Most significant)
Submode XX (not used)
H1 - Status/interrupt generating input
H2 - Status/interrupt generating input or
general-purpose output
Port B - Double-Buffered Data (Least significant)
Submode XO - Unidirectional 16-Bit Input
H3 - Latches input data
H4 - Status/interrupt generating input,
general-purpose output, or operation with
H3 in the interlocked or pulsed input
handshake protocols
Submode X1 - Unidirectional 16-Bit Output
H3 - Indicates data received by peripheral
H4 - Status/interrupt generating input,
general-purpose output, or operation with
H3 in the interlocked or pulsed input
handshake protocols
Mode 2 (Bidirectional 8-Bit Mode)
Port A - Bit I/O (with no handshaking pins)
Submode XX (not used)
Port B - Bidirectional 8-Bit Data (Double-Buffered)
Submode XX (not used)
H1 -Indicates output data received by peripheral
H2 - Operation with H1 in the interlocked or
pulsed output handshake protocols
H3 - Latches input data
H4 - Operation with H3 in the interlocked or
pulsed input handshake protocols
Mode 3 (Bidirectional 16-Bit Mode)
Port A - Double-Buffered Data (Most significant)
Submode XX (not used)
Port B - Double-Buffered Data (Least significant)
Submode XX'(not used)
H1 -Indicates output data received by peripheral
H2 - Operation with H1 in the interlocked or
pulsed output handshake protocols
H3 - Latches input data
H4 - Operation with H3 in the interlocked or pulsed
input handshake protocols
VI-64
PORT GENERAL INFORMATION AND
CONVENTIONS
DOUBLE-BUFFERED INPUT TRANSFERS - In all
modes, the PI/T supports double-buffered input transfers.
Data that meets the port setup and hold times is latched on
the asserted edge of H1(H3). H1(H3) is edge-sensitive, and
may assume any duty-cycle as long as both high and low
minimum times are observed. The PlfT contains a Port
Status Register whose H1 S(H3S) status bit is set anytime
any input data is present in the double-buffered latches that
have not been read by the bus master. The action of H2(H4)
is programmable; it may indicate whether there is room for
more data in the PI/T latches or it may serve other purposes.
The following options are available, depending on the mode.
The following paragraphs introduce concepts that are
generally applicable to the PI/T ports independent of the
chosen mode and submode. For this reason, no particular
port or handshake pins are mentioned; the notation H1 (H3)
indicates that, depending on the chosen mode and
submode, the statement given may be true for either the H1
or H3 handshake pin.
UNIDIRECTIONAL VS BIDIRECTIONAL - Figure 4
shows the configuration of Ports A and B and each of the
handshake pins in each port mode and submode. In Modes
o and 1, a data direction register is associated with each of
the ports. These registers contain one bit for each port pin to
determine whether that pin is an input or an output. Modes
o and 1 are, thus, called unidirectional modes because each
pin assumes a constant direction, changeable only by a
reset condition or a programming change. These modes
allow double-buffered data transfers in one direction. This
direction, determined by the mode and submode definition,
is known as the primary direction. Data transfers in the
primary direction are controlled by the handshake pins.
Data transfers not in the primary direction are generally
unrelated, and single or unbuffered data paths exist.
1. H2(H4) may be an edge-sensitive input that is
independent of H1 (H3) and the transfer of port data. On
the asserted edge of H2(H4), the H2S(H4S) status bit is
set. It is cleared by the direct method (refer to Direct
Method of Resetting Status), the RESET pin being
asserted, orwhenthe H12 Enable(H34 Enable) bit ofthe
Port General Control Register is O.
2. H2(H4) may be a general purpose output pin that is
always negated. The H2S(H4S) status bit is always O.
3. H2(H4) may be a general purpose output pin that is
always asserted. The H2S(H4S) status bit is always O.
4. H2(H4) may be an output pin in the interlocked input
handshake protocol. It is asserted when the port input
latches are ready to accept new data. It is negated
asynchronously following the asserted edge of the
H1(H3) input. As soon asthe input latches become ready,
H2(H4) is again asserted. When the input doublebuffered latches are full, H2(H4) remains negated until
data is removed. Thus, anytime the H2(H4) output is
asserted, new input data may be entered by asserting
H 1(H3). At other times transitions on H 1(H3) are ignored.
The H2S(H4S) status bit is always O. When H12 Enable
(H34 Enable) is 0, H2(H4) is held negated.
In Modes 2 and 3there is no concept of primary direction as
in Modes 0 and 1. Except for Port A in Mode 2 (Bit I/O), the
data direction registers have no effect. These modes are
bidirectional. in thatthe direction of each transfer (always 8
or 16 bits, double-buffered) is determined dynamically by
the state of the handshake pins. Thus, for example, data
may be transferred out ofthe ports, followed very shortly by
a transfer into the same port pins. Transfers to and from the
ports are independent and may occur in any sequence.
Since the instantaneous direction is always determined by
the external system, a small amount of arbitration logic may
be required.
CONTROL OF DOUBLE-BUFFERED DATA PATHS Generally speaking, the PI/T is a double-buffered device. In
the primary direction, double-buffering allows orderly
transfers by using the handshake pins in any of several
programmable protocols. (When Bit I/O is used, doublebuffering is not available and the handshake pins are used
as outputs or status/interrupt inputs.)
Use of double-buffering is most beneficial in situations
where a peripheral device and the computer system are
capable of transferring data at roughly the same speed.
Double-buffering allows the fetch operation of the data
tra nsm itter to be overlapped with the store operation of the
data receiver. Thus, throughput measured in bytes or
words-per-second may be greatly enhanced. If there is a
large mismatch in transfer capability between the computer
and the peripheral, little or no benefit is obtained. In these
cases there is no penalty in using double-buffering.
5. H2(H4) may be an output pin in the pulsed input
handshake protocol. It is asserted exactly as in the
interlocked input protocol, but never remains asserted
longer than 4 clock cycles. Typically, a four clock cycle
pulse is generated. But in the case that a subsequent
H1(H3) asserted edge occurs before termination of the
pulse, H2(H4) is negated asynchronously. Thus, anytime
after the leading edge of the H2(H4) pulse, new data may
be entered in the PlfT double-buffered input latches. The
H2S(H4S) status bit is always O. When H 12 Enable (H34
Enable) is 0, H2(H4) is held negated.
A sample timing diagram is shown in Figure 5. The H2(H4)
interlocked and pulsed input handshake protocols are
shown. The DMAREQ pin is also shown assuming it is
enabled. All handshake pin sense bits are assumed to be 0
(refer to Port General Control Register); thus, the pins are in
the low state when asserted. Due to the great similar.ity
between modes, this timing diagram is applicable to all
double-buffered input transfers.
VI-65
•
DOUBLE-BUFFERED INPUT TRANSFERS
FigureS
READ
READ
PORT DATA
H1(H31
H2(H41INTERLOCKED
H2(H41 PULSE
DOUBLE-BUFFERED OUTPUT TRANSFERS - The
PIIT supports double-buffered output transfers in all
modes. Data, written by the bus master to the PIIT, is stored
in the port's output latch. The peripheral accepts the data by
asserting H1 (H3), which causes the next data to be moved
to the port's output latch as soon as it is available. The
function of H2(H4) is programmable; it may indicate
whether new data has been moved to the output latch or it
may serve other purposes. The H1 S(H3S) status bit may be
programmed for two interpretations. Normally the status bit
is a 1 when there is at least one latch in the double-buffered
data path that can accept new data. After writing one
byte/word of data to the ports, an interrupt service routine
could check this bit to determine if it could store another
byte/word, thus, filling both latches. When the bus master
is finished, it is often useful to be able to check whether all of
the data has been transferred to the· peripheral. The
H1 S(H3S) Status Control bit of the Port A and B Control
Registers provides this flexibility. The programmable
options of the H2(H4) pin are given below, depending on the
mode.
1. H2(H4) may be an edge-sensitive input pin independent
of H1 (H3) and the transfer of port data. On the asserted
edge of H2(H4), the H2S(H4S) status bit is set. It is reset
by the direct method (refer to Direct Method of Resetting
Status), the RESET pin being asserted, or when the H12
Enable (H34 Enable) bit of the Port General Control
Register is O.
2. H2(H4) may be a generalcpurpose output pin that is
always negated. The H2S(H4S) status bit is always O.
3. H2(H4) may be a general-purpose output pin that is
always asserted. The H2S(H4S) status bit is always O.
4. H2(H4) may be an output pin in the interlocked output
handshake protocol. H2(H4) is asserted two clock cycles
after data is transferred to the double-buffered output
latches. The data remains stable and H2(H4) remains
asserted until the next asserted edge of the H1 (H3) input.
At that time, H2(H4) is asynchronously negated. As soon
as the next data is available, it is transferred to the output
latches. When H2(H4) is negated, asserted transitions on
H1 (H3) have no effect on the data paths. As is explained
later, however, in Modes 2 and 3 they do control the
three-state output buffers of the bidirectional portIs). The
H2S(H4S) status bit is always O. When H12 Enable (H34
Enable) is 0, H2(H4) is held negated.
DOUBLE-BUFFERED OUTPUT TRANSFERS
Figure 6
WRITE
WRITE
PORT DATA
H2(H41INTERLOCKED
H2(H41 PULSE
H1(H31
VI-66
5. H2(H4) may be an output pin in the pulsed output
handshake protocol. It is asserted exactly as in the
interlocked output protocol above, but never remains
asserted longer than four clock cycles. Typically, a four
clock pulse is generated. But in the case that a
subsequent H 1(H3) asserted edge occurs before
termination of the pulse, H2(H4) is negated asynchronously shortening the pulse. The H2S(H4S) status
bit is always O. When H12 Enable (H34 Enable) is 0,
H2(H4) is held negated.
A sample timing diagram is shown in Figure 6. The H2(H4)
interlocked and pulsed output handshake protocols are
shown. The DMAREQ pin is also shown assuming it is
enabled. All handshake pin sense bits are assumed to be 0;
thus, the pins are in the low state when asserted. Due to the
great similarity between modes, this timing diagram is
applicable to all double-buffered output transfer.
REQUESTING BUS MASTER SERVICE - The PI/T has
several means of indicating a need for service by a bus
master. First, the processor may poll the Port Status
Register. It contains a status bit for each handshake pin,
plus a level bit that always reflects the instantaneous state
of that handshake pin. A status bit is 1 when the PIIT needs
servicing, i.e., generally when the bus master needs to read
or write data to the ports, or when a handshake pin used as
a simple status input has been asserted. The interpretation
of these bits is dependent on the chosen mode and
submode.
Second, the PIIT may be placed in the processor's interrupt
structure. As mentioned previously, the PI/T contains Port
A and B Control Registers that configure the handshake
pins. Other bits in these registers enable an interrupt
associated with each handshake pin. This interrupt is made
available through the PC5/PIRQ pin, if the PIRQ function is
selected. Three additional conditions are required for PIRQ
to be asserted: (1 ) the handshake pin status bit is set, (2) the
corresponding interrupt (service request) enable bit is set,
and (3) DMA requests are not associated with that data
transfer (H1 and H3 only). The conditions from each of the
four handshake pins and corresponding status bits are
ORed to determine PIRQ.
The third method of requesting service is via the
PC4/DMAREQ pin. This pin can be associated with doublebuffered transfers in each mode. If it is used as a DMA
controller request, it can initiate requests to keep the PI/T's
inputloutput double-buffering emptylfull as much as
possible. It will not overrun the DMA controller. The pin is
compatible with the MK68450 Direct Memory Access
Controller (DMAC).
VECTORED, PRIORITIZED PORT INTERRUPTS - Use
of MK68000-compatible vectored interrupts with the PIIT
requires the PIRQ and PlACK pins. When PlACK is asserted,
the PIIT places an 8-bit vector on the data pins 00-07.
Under normal conditions, this vector corresponds to the
highest priority, enabled, active port interrupt source with
which the OMAREQ pin is not currently associated. The
most-significant six bits are provided by the Port Interrupt
Vector Register (PIVR), with the lower two bits supplied by
prioritization logic according to conditions present when
PlACK is asserted. It is important to note that the only affect
on the PIIT caused by interrupt acknowledge cycles is that
the vector is placed on the data bus. Specifically, no
registers, data, status, or other internal states of the PI/T are
affected by the cycle.
Several conditions may be present when the PlACK input is
asserted to the PI/T. These conditions affect the PI/T's
response and the termination of the bus cycle. If the PI/T
has no interrupt function selected, or is not asserting PIRQ,
the PI/T will make no response to PlACK (DTACK will not be
asserted). If the PIIT is asserting PIRQ when PlACK is
received, the PI/T will output the contents of the Port
Interrupt Vector Register and the prioritization bits. If the
PIVR has not been initialized, $OF will be read from this
register. These conditions are summarized in Table 3.
RESPONSE TO PORT INTERRUPT ACKNOWLEDGE
Table 3
Conditions
PIVR has not been initialized
since RESET
PIVR has been initialized
since RESET
PIRQ negated OR interrupt
request function not selected
No response from PI/T.
No DTACK.
No response from PI/T.
No DTACK.
PIRQ asserted
PI/T provides $OF, the
Uninitialized Vector.*
PI/T provides PIVR contents
with prioritization bits.
*The uninitialized vector is the value returned from an interrupt vector register before it has been initialized.
VI-67
•
The vector table entries for the PI/T appear as a contiguous
block of four vector numbers whose common upper six bits
are programmed in the PIVR. The following table pairs each
interrupt source with the 2-bit value provided by the
prioritization logic, when interrupt acknowledge is asserted.
H1
H2
H3
H4
source source source source -
00
01
10
11
AUTOVECTORED PORT INTERRUPTS -Autovectored
interrupts use only the PIRO pin. The operation of the PI/T
with vectored and autovectored interrupts is identical
except that no vectors are supplied and the PC6/PIACK pin
can be used as a Port C pin.
DIRECT METHOD OF RESETTING STATUS -In certain
modes one or more handshake pins can be used as edgesensitive inputs for the sole purpose of setting bits in the
Port Status Register. These bits consist of simple flip-flops.
They are set (to 1 ) by the occurrence of the asserted edge of
the handshake pin input. Resetting a handshake status bit
can be done by writing an 8-bit mask to the Port Status
Register. This is called the direct method of resetting. To
reset a status bit that is resettable by the direct method, the
mask must contain a 1 in the bit position of the Port Status
Register corresponding to the desired bit. Other positions
must contain O·s. For status bits that are not resettable by
the direct method in the chosen mode, the data written to
the port status register has no effect. For status bits that are
resettable by the direct method in the chosen mode, a 0 in
the mask has no effect.
HANDSHAKE PIN SENSE CONTROL - The PI/T
contains exclusive-OR gates to control the sense of each of
the handshake pins, whether used as inputs or outputs.
Four bits in the Port General Control Register may be
programmed to determine whether the pins are asserted in
the low or high voltage state. As with other control registers,
these bits are reset to 0 when the RESET pin is asserted,
defaulting the asserted level to be low.
ENABLING PORTS A AND B - Certain functions involved
with double-buffered data transfers,. the handshake pins,
and the status bits, may be disabled by the external system
or by the programmer during initialization. The Port General
Control Register contains two bits, H12 Enable and H34
Enable, which control these functions. These bits are
cleared when the RESET pin is asserted, and the functions
are disabled. The functions are the following:
1. Independent of other actions by the bus master or
peripheral (via the handshake pins), the PI/T's disabled
handshake controller is held to the" empty" state, i.e:, no
data is present in the double-buffered data path.
2. When any handshake pin is used to set a simple status
flip-flop, unrelated to double-buffered transfers, these
flip-flops are held reset to O. (See Table 2.)
3. When H2(H4) is used in an interlocked or pulsed
handshake with H1(H3), H2(H4) is held negated,
regardless of the chosen mode, submode, and primary
direction. Thus, for double-buffered input transfers, the
programmer may signal a peripheral when the PI/T is
ready to begin transfers by setting the associated
handshake enable bit to 1.
THE PORT A AND B ALTERNATE REGISTERS - In
addition to the Port A and B Data Registers, the PI/T
contains Port A and B Alternate Registers. These registers
are read-only, and simply provide the instantaneous level of
each port pin. They have no effect on the operation of the
handshake pins, double-buffered transfers, status bits, or
any other aspect of the PI/T, and they are mode/submode
independent.
PORT MODES
This section contains information that distinguishes the
various port modes and submodes. General characteristics,
common to all modes, have been defined previously.
MODE 0 -
UNIDIRECTIONAL 8-BIT MODE
In Mode 0, Ports A and B operate independently. Each may
be configured in any of its three possible submodes:
Submode 00 - Double-Buffered Input
Submode 01 - Double-Buffered Output
Submode 1X - Bit I/O
Handshake pins H 1 and H2 are associated with Port A and
configured by programming the Port A Control Register.
(The H12 Enable bit of the Port General Control Register
enables Port A transfers.) Handshake pins H3 and H4 are
associated with Port B and configured by programming the
Port B Control Register. (The H34. Enable bit of the Port
General Control Register enables Port B transfers.) The Port
A and B Data Direction Registers operate in all three
submodes. Along with the submode, they affect the data
read and written at the associated data register according to
Table 4. They also enable the output buffer associated with
each port pin. The DMAREO pin may be associated with
either (not both) PortA or Port B, but does not function ifthe
Bit I/O submode is programmed for the chosen port.
VI-68
MODE 0 PORT DATA PATHS
Table 4
Mode
OSubmode 00
o Submode 01
OSubmode 1X
Read Port AlB
Data Register
DDR=O
DDR=1
FIL, D.B.
Pin
Pin
Write Port AlB
Data Register
DDR=X
FOL Note 3 FOL,S.B.
Note 1
FOL Note 3 IOUFOL, D.B. Note 2
FOL Note 3 FOL,S.B.
Note 1
Abbreviations:
IOL - Initial Output Latch
FOL - Final Output Latch
FIL - Final Input Latch
S.B. - Single Buffered
D.B. - Double Buffered
DDR - Data Direction Register
Note 1: Data is latched in the output data registers (final output latch)
and will be single buffered at the pin if the DDR is 1. The
output buffers will be turned off if the DDR is O.
Note 2: Data is latched in the double-buffered output data registers.
The data in the final output latch will appear on the port pin if
the DDR is a 1.
Note 3: The output drivers that connect the final output latch to the
pins are turned on.
PORT A OR B SUBMODE 00
(8-BIT DOUBLE-BUFFERED INPUT) -
II
PORT A OR B SUBMODE 01
(8-BIT DOUBLE-BUFFERED OUTPUT) -
MODE 0 SUBMODE 00
MODE 0 SUBMODE 01
DOUBLE·BUFFERED
OUTPUT
Hl (H3)
H2(H4)
In Mode 0, double-buffered input transfers of up to a-bits
are available by programming Submode 00 in the desired
port's control register. The operation of H2 and H4 may be
selected by programming the Port A and Port B Control
Registers, respectively. All five double-buffered input
handshake options, previously mentioned in the Port
General Information and Conventions section, are
available.
For pins used as outputs, the data path consists of a single
latch driving the output buffer. Data written to the port's
data register does not affect the operation of any handshake
pin, status bit, or any other aspect of the PIIT. Output pins
may be used independently of the input transfer. However,
read bus cycles to the data register do remove data from the
port. Therefore, care should be taken to avoid processor
instructions that perform unwanted read cycles.
Refer to PARALLEL PORTS Double-Buffered
Transfers for a sample timing diagram (Figure 5).
Input
In Mode 0, double-buffered output transfers of up to a bits
are available by programming submode 01 in the desired
port's control register. The operation of H2 and H4 may be
selected by programming the Port A and Port B Control
Registers, respectively. All five double-buffered output
handshake options, previously mentioned in the Port
General Information and Conventions section, are
available.
For pins used as inputs, data written to the associated data
register is double-buffered and passed to the initial or final
output latch, as usual. but the output buffer is disabled.
Refer to PARALLEL PORTS Double-Buffered Output
Transfers for a sample timing diagram (Figure 6).
VI-69
Mode 1 can provide convenient, high-speed 16-bit
transfers. The Port A and B data registers are addressed for
compatibility with the MK68000 Move Peripheral (MOVEP)
instruction and with the MK68450 DMAC. To take
advantage of this, Port A should contain the mostsignificant byte of data and always be read or written by the
bus master first. The interlocked and pulsed handshake
protocols are keyed to accesses to the Port B Data Register
in Mode 1 . if it is accessed last, the 16-bit double-buffered
transfers proceed smoothly.
PORT A OR B SUBMODE 1X (BIT 1/0)MODE 0 SUBMODE 1X
¢)A~B)
BIT 1/0
H1 (H3)
H2(H4)
PORT B SUBMODE XO
(16-BIT DOUBLE-BUFFERED INPUT) In Mode 0, simple Bit 1/0 is available by programming
Submode 1X in the desired port's control register. This
submode is intended for applications in which several
independent devices must be controlled or monitored. Data
written to the associated data register is single-buffered. If
the data direction register bit for that pin is a 1 (output), the
output buffer is enabled. If it is 0 (input), data written is still
latched, but is not available at the pin. Data read from the
data register is the instantaneous value of the pin or what
was written to the data register, depending on the contents
of the data direction register. H1(H3) is an edge-sensitive
status input pin only and it controls no data-related function.
The H1 S(H3S) status bit is set following the asserted edge of
the input waveform. It is reset by the direct method, the
RESET pin being asserted, or when the H12 Enable (H34
Enable) bit is O.
H2(H4) can be progr!lmmed as a simple status input
(identical to H1(H3), or as an asserted or negated output.
The interlocked or pulsed handshake configurations are not
available.
MODE 1 -
UNIDIRECTIONAL 16-BIT MODE
In Mode 1, Ports A and B are concatenated to form a single
16-bit port. The Port B Submode field controls the
configuration of both ports. The possible submodes are:
Port B Submode XO Port B Submode X1 -
Double-Buffered Input
Double-Buffered Output
Handshake pins H3 and H4, configured by programming the
Port B Control Register, are associated with the 16-bit
double-buffered transfer. These 16-bit transfers are
enabled by the H34 Enable bit of the Port General Control
Register. Handshake pins H1 and H2 may be used as simple
status inputs not related to the 16-bit data transfer or H2
may be an output. Enabling of the H1 and H2 handshake
pins is done by the H12 Enable bit of the Port General
Control Register. The PortA and B Data Direction Registers
operate in each submode. Along with the submode, they
affect the data read and written at the data register
according to Table 5. They also enable the output buffer
associated with each port pin. The DMAREQ pin may be
associated only with H3.
MODE 1 PORT B SUBMODE XO
r----14--H1
14-__.H2
r-
<
~
IAANDB
(16)
LATCHED, DOUBLEBUFFERED INPUT
14--H3
"-=LJ.+-.... H4
In Mode 1 Port B Submode XO, double-buffered input
transfers of up to 16 bits may be obtained. The level of all16
pins is asynchronously latched with the asserted edge of
H3. The processor may check H3S status bit to determine if
new data is present. The DMAREQ pin may be used to
signal a DMA controller to empty the input buffers.
Regardless of the bus master, Port A data should be read
first. (Actually, Port A data need not be read at all.) Port B
data should be read last. The operation of the internal
handshake controller, the H3S bit, and DMAREQ are keyed
to the reading of the Port B data register. (The MK68450
DMAC can be programmed to perform the exact transfers
needed for compatibility with the PIIT.) H4 may be
programmed for all five of the handshake options
mentioned in the Port General Information and Conventions section.
For pins used as outputs, the data path consists of a single
latch driving the output buffer. Data written to the port's
data register does not affect the operation of any handshake
pin, status bit, or any other aspect of the PI IT. Thus, output
pins may be used independently of the input transfer.
However, read bus cycles to the Port B Data Register do
remove data, so care should be taken to avoid unwanted
read cycles.
Refer to PARALLEL PORTS Double-Buffered
Transfers for a sample timing diagram (Figure 5).
Input
In Mode 1 Port B Submode X1, double-buffered output
transfers of up to 16 bits may be obtained. Data is written by
the bus master (processor or DMA controller) in two bytes.
VI-70
MODE 1 PORT DATA PATHS
Table 5
Mode
Read Port AlB
Register
DDR=O
1, Port B
SubmodeXO
1, Port B
SubmodeXl
DDR
FIL. D.B.
Write Port AlB
Register
=1
FOL
Note 3
FOL
Note 3
Pin
DDR=O
DDR=1
FOL. S.B.
Note 2
10UFOL.
D.B.,
Note 1
FOL. S.B.
Note 2
10UFOL,
D.B.,
Note 1
Note 1: Data written to Port A goes to a temporary latch. When the
Port B data register is later written, Port A data is transferred
toIOUFOL.
Note 2: Data is latched in the output data registers (final output latch)
and will be single buffered at the pin if the DDR is 1. The
output buffers will be turned off if the DDR is O.
Note 3: The output drivers that connect the final output latch to the
pins are turned on.
Abbreviations:
10L - Initial Output Latch
FOL - Final Output Latch
FIL - Final Input Latch
S.B. - Single Buffered
D.B. - Double Buffered
DDR - Data Direction Register
PORT B SUBMODE X1
(16-BIT DOUBLE-BUFFERED OUTPUT) -
For pins used as inputs, data written to either data register is '
double-buffered and passed to the initial or final output
latch, as usual, but the output buffer is disabled.
Refer to PARALLEL PORTS Double-Buffered Input/Output
Transfer for a sample timing diagram (Figure 6).
MODE 1 PORT B SUBMODE X1
14---H1
(4---IH2
MODE 2 - BIDIRECTIONAL 8-BIT MODE
DOUBLE-BUFFERED
OUTPUT
i.---IH3
MODE 2
A (B)
L~-""H4
The first byte (most-significant) is written to the PortA Data
Register. It is stored in a temporary latch until the next byte
is written to the Port B Data Register. Then all 16 bits are
transferred to the final output latches of Ports A and B. Both
options for interpretation of the H3S status bit, mentioned in
Port General Information and Comments section, are
available and apply to the 16-bit port as a whole. The
DMAREQ pin may be used to signal a DMA controller to
transfer another word to the port output latches. (The
MK68450 DMAC can be programmed to perform the exact
transfers needed for compatibility with the PI/T.) H4 may be
programmed for all five of the handshake options
mentioned in the Port General Information and Comments
section.
B(8)
BIDIRECTIONAL 8-BIT
H1
OUTPUT
H2 >--TRANSFERS
H3>--INPUT
L.-r--__ H4
TRANSFERS
In Mode 2, Port A is used for simple bit I/O with no
associated handshake pins. Port B is used for bidirectional
a-bit double-buffered transfers. H 1 and H2, enabled by the
H12 Enable bit in the Port General Control Register, control
VI-71
-~-------
II
output transfers, while H3 and H4, enabled by the Port
General Control Register bit H34 Enable, control input
transfers. The instantaneous direction of the data is
determined by the Hl handshake pin. The Port B Data
Direction Register is not used. The Port A and Port B
submode fields do not affect PIIT operation in Mode 2.
DOUBLE-BUFFERED 110 (PORT BI - The only aspect of
bidirectional double-buffered transfers that differs from the
unidirectional modes lies in controlling the Port B output
buffers. They are controlled by the level of H1 . When H1 is
negated, the Port B output buffers(aIl8) are enabled and the
pins drive the bidirectional bus. Generally, Hl is negated in
response to an asserted H2, which indicates that new
output data is present in the double-buffered latches.
Following acceptance ofthe data, the peripheral asserts Hl,
disabling the Port B output buffers. Other than controlling
the output buffer, Hl is edge-sensitive as in other modes.
Input transfers proceed identically to the double-buffered
input protocol described in the Port General Information and
Conventions Section. In Mode 2, only the interlocked and
pulsed handshake pin options are available on H2 and H4.
The DMAREQ pin may be associated with either input
transfers (H3) or output transfers (H 1 ), but not both. Refer to
Table 6 for a summary ofthe Port B Data Register responses
in Mode 2.
BIT 1/0 (PORT Al - Mode 2, Port A performs simple bit
1/0 with no associated handshake pins. This configuration
is intended for applications in which several independent
devices must be controlled or monitored. Data written to the
Port A data register is single-buffered. If the Port A Data
Direction Register bit for that pin is 1 (output), the output
buffer is enabled. If it is 0, data written is still latched but not
available atthe pin. Data read from the data register is either
the instantaneous value of the pin or what was written to
the data register, depending on the contents of the Port A
Data Direction Register. This is summarized in Table 7.
MODE 3 -BIDIRECTIONAL 16-BIT DOUBLEBUFFERED 1/0
MODE 3
AANDB
(16)
BIDIRECTIONAL 16-BIT
Hl
OUTPUT
H2 )--TRANSFERS
H3)--INPUT
L--... GV - - -"'"'-------- -'
DATA TO MEMORY
---""'"
ALE
irn (DOTTED)
DAS
READY
i'iimi (READ)
i'ilITi(READ)
i'iimi (WRITE)
"1"
i'ilITi(WRITE)
'--___.....J/
"
"'-------------------------~/
,,~-----~/
VI-119
•
VI-120
MOSTEI{.
MICROCOMPUTER COMPONENTS
------------------------------------------------
Serial Interface Adapter
MK3891
FEATURES
o
TIL compatible input to 20 MH~ oscillator eliminates
need for a separate crystal for SIA(ie. share uP's crystal).
o 100% compatible with companion LANCE chip and
Ethernet specification
o
Bipolar VLSI technology
o
Manchester data encoding
o
Single 5 volt power supply
o
Manchester data decoding with a Phase Lock Loop (PLL)
o
20 MH~ crystal oscillator which generates 10 MHz
LANCE Cluck inputs
o
Receive Squelch circuitry
o
All LANCE signals TIL compatible
o
Collision Squelch circuitry
o
o
Differential TRANSMIT transceiver cable drivers
All transceiver signals compatible with Ethernet
specifications
INTRODUCTION
The MK3891-SIA (Serial Interface Adapter) is a VLSI
device designed to simplify greatly the interfacing of a
microcomputer or minicomputer to an Ethernet Local
Area Network. The SIA is a companion device to the
LANCE (Local Area Network Controller for Ethernet)
Ethernet Protocol Controller. The SIA and LANCE chips
are intended to operate in an environment that includes a
closely coupled memory and microprocessor. The SIA is
compatible with the transceiver input specifications
detailed in the September 30, 1980 (Rev. 1.0)
specification entitled "The Ethernet - A Local Area
Network - Data Link Layer and Physical Layer
Specification".
FUNCTIONAL CAPABILITIES
The Serial Interface Adapter (SIA) interfaces the LANCE
Ethernet protocol controller with a standard Ethernet
Transceiver cable as specified in the Ethernet Specification. Seven interface signals between the LANCE and
the SIA chips can be wired pin to pin, while the six
transceiver cable signals can be connected directly to the
15 pin 0 Transceiver connector. This relationship is
described in Figure 1.
Figure 2 details a block diagram of the SIA. The Crystal
Oscillator is controlled by a 20 MHz external crystal or
can accept a 20 MHz TIL signal. A 10 MHz symmetric
signal is created to drive the Manchester Encoder and to
provide a TRANSMIT CLOCK for the LANCE. The
Manchester Encoder takes the TRANSMIT DATA and
TRANSMIT ENABLE signals from the LANCE and creates
the Manchester encoded differential signals TRANSMIT
+ and TRANSMIT - to drive the Transceiver interface.
A collision on the Ethernet cable will be sensed by the
Transceiver, and it will create the differential signals
COLLISION PRESENCE + and COLLISION PRESENCE which are received and signal conditioned to produce a
TIL signal COLLISION for the LANCE. Likewise when
data is on the Ethernet coax, the Transceiver will create
the differential signals RECEIVE + and RECEIVE -. These
inputs to the SIA are decoded by the PLL phase locked
loop which synchronizes to the Ethernet Preamble and
recovers clock and data from the Manchester Encoded
cable signals. These two signals are supplied to the
LANCE as TIL signals RECEIVE DATA and RECEIVE
CLOCK. In addition, the SIA creates the signal CARRIER
PRESENT while it is receiving data from the cable to
indicate to the LANCE that receive data and clock are
valid and available.
VI-121
ETHERNET.~OCAL ARE~ NETWORK SYSTEIIII BLOCK DIAGRAM
Figure 1
MICROPROCESSOR
C
o
M
P
U
T
E
MK68200
MK68000
18086
Z8000
LSI-11
T-11
R
S
--- --..
Y
S
T
16
LOCAL AREA
NETWORK
CONTROLLER FOR
ETHERNET
(LANCE)
7
SERIAL
INTERFACE
ADAPTER
rJ.,
(SIA)
8
XCVR
TAP
TRANSCEIVER
CABLE
E
M
B
U
S
LOCAL
MEMORY
2
POWER
f-f-
NETWORK INTERFACE MODULE
VI-122
NETWORK
CABLE
SERIAL INTERFACE ADAPTER (SIA) BLOCK DIAGRAM
Figure 2
I
RECEIVE DATA (RX)
MANCHESTER DECODER
• PLL DECODER
RECEIVE CLOCK (RCLK)
C
RECEIVE +
RECEIVE -
• RECEIVE SQUELCH
-I
Jl
l>
CARRIER PRESENT (CARR) : ...: _ - - - - - - - - - '
W
~
COLLISION
SQUELCH
COLLISION (CLSN) ._
u.
rr
W
I-
I:
COLLISION
:PRESENCE +
COLLISION
PRESENCE -
m
<:m
Jl
Z
~
m
Jl
-n
l>
U
z
l
z
en
(")
-I
W
:3
l
TRANSMITD ATA(TX)
MANCHESTER ENCODER
TRANSMIT ENABL E (TEN A)
TRANSMIT CLOC K (TCLK)
e
m
TRANSMIT 10 MHz
I
j20 MHz
XTAL1
20 MHz
TRANSMIT +
(")
CRYSTAL
OSCILLATOR
XTAL2
VI-123
J
1'1
1982/1983 MICROELECTRONIC DATA BOOK
.................. ~
•••••••••••••
~
• •••••••
_ '"
.......... ~· ................ ~v .. · · " ............ ~~
•••••••••• "'
M~
............. ~v_ .................. .
MOSTEI{.
zao MICROCOMPUTER
Central Processing Unit
MK3880
FEATURES
ZSO PIN CONFIGURATION
Figure 1
o The zao is fully software compatible with the aOaOA
CPU. The 7a instructions of the aOaOA are a subset of
the zao's 15a instructions.
o
o
The extensive instruction set includes relative and
indexed addressing, block searches and block transfers,
word, byte, and bit data operations.
The architecture provides duplicate sets of general
purpose Flag and Index registers to allow backgroundl
foreground programming and easier single level
interrupt processing and to facilitate array and table
processing.
SYSTEM
CONTROL
o
o
~RO
RD
We
lR"FSH
WA"iT
CPU
CONTROL
TNT
NMI
RE'SET
CPU
BUS
o
r
r
M'R"E'O
CON'TROl
3D
27
19
20
A3
A,
21
22
A,
28
A6
A)
A8
'8
ADDRESS
BUS
A,
A10
24
All
ZIOCPU
A"
A13
MK3810
MK388().4
MK3880·&
A"
A15
{BUSRa
BUSAK
14
On chip Dynamic memory refresh counter
DO
0,
.,.
Single +5 V supply
AO
A,
A,
.,v
0,
03
DATA
GND
0,
BUS
0,
06
Single phase system clock
D)
o
Vectored interrupt handling system. This system allows
for a Daisy Chain arrangement of a priority interrupt
scheme with little if any additional hardware.
INTRODUCTION
The Mostek zao family of components is a significant
advancement in the state-of-the-art of microcomputers.
These components can be configured with any type of
standard semiconductor memory to generate computer
systems with an extremely wide range of capabilities. For
example, as few as two LSI circuits and three standard TIL
MSI packages can be combined to form a simple controller.
With additional memory and 110 devices, a computer can
be constructed with capabilities that only a minicomputer
could previously deliver. This wide range of computational
power allows standard modules to be constructed by a user
that can satisfy the requirements of an extremely wide
range of applications.
The zao Central Processing Unit is the heart of the zao
family. It provides arithmetic and bus control to operate with
the bussed peripheral controllers such as the Parallel 110,
Serial 110, CounterlTimer, and Direct Memory Access
Circuits. The zao-cpu utilizes N channel silicon gate
depletion load technology and is packaged in a 40 pin DIP.
ZSO-CPU PIN DESCRIPTION
The zao-cpu is packaged in an industry-standard 40 pin
Dual In-Line Package. The I/O pins are shown in Figure 1,
and the function of each is described below.
Ao-A15
(Address Bus)
Tri-state {)utput, active high. Ao-A15
constitute a 16-bit address bus. The
address bus provides the address for
memory (up to 64K bytes), data
exchanges, and for 110 device data
exchanges. 1/0 addressing uses the a
lower address bits to allow the user to
select up to 256 input or 256 output
ports directly. Ao is the least significant
address bit. During refresh time, the
lower 7 bits contain a valid refresh
address.
0 0 -0 7
(Data Bus)
Tri-state input/output, active high. 0 0 0 7 constitute an a-bit bidirectional data
bus. The data bus is used for data
exchanges with memory and 110 devices.
VII-1
III
Ml
(Machine Cyele
one)
Output, active'low, Ml indicates that
the current machine cycle is the Of>,
code fetch cycle of an instruction
execution. Note that during execution of
2 -byte op-codes, M 1 is generated as
each op code byte is fetched. These tWo
byte op-codes always begin with CBH,
DOH, EDH,orFDH. Ml also occurs with
10RO to indicate an interrupt acknowledge cycle.
Tri-state output, active low. The meinMREO
(Memory Request) ory request signal indicates that the
address bus holds a valid address for a
memory read or memory write operation.
10RO
(Input/Output
Request)
Output, active low. WAIT indicates to
the Z80-CPU that the addressed
memory or I/O devices are not ready for
a data transfer. The CPU continues to
enter wait states for as long as this
signal is active. This signal allows
memory or I/O devices of any speed to
be synchronized to the CPU.
INT
(Interrupt
Request)
Input, active low. The Interrupt'Request
signal is generated by I/O devices. A request will be honored at the end of the
current instruction if the internal
software controlled interrupt enable
flip-flop (IFF) is enabled and if the
BUSRQ signal is not active. When the
CPU accepts the interrupt, an acknowledge signal (IORO during Ml time) is
sent out at the beginning of the next
instruction cycle. The CPU can,respond
to an interrupt in three different modes
that are described in detail in section 8
of the Technical Manual, which is
included in section IV of this data book.
Tri-state output, active low. The 10RO
signal indicates that the lower half ~f
the address bus holds a valid I/O
address for an I/O read or write
operation. An 10RO signal is also
generated with an Ml signal when an
interrupt is being acknowledged to
indicate that an interrupt response
vector can be placed on the data bus.
Interrupt Acknowledge operations occur during M, time while I/O operations never occur during Ml time. '
RD
(Memory Read)
Tri-state output, active low. RD indicates that the CPU wants to read data
from memory or an I/O device. ,The
addressed I/O device or memory
should use this signal to gate data onto
the CPU data bus.
WR
(Memory Write)
Tri-state output, active low. WR indicates that the CPU data bus holds valid
datI:! 'to be'stored in the addressed
memory or I/O device.
RFSH
(Refresh)
Output, active low. RFSH indicates that
the, lower 7 bits of the address bus
contain a rt)fresh address for dynamic
memories and current MREO signal
should be used to do a refresh read to all
dynamic memories. A7 is a lOgic zero
and the upper 8 bits oftheAddress Bus
contain the I Register.
HALT
(Halt state)
WAIT*
(Wait)
Output, active low. HALT indicates that
the CPU has executed a HArf software'
instruction and is awaiting either a non
maskabie or a maskable interrupt (with
the mask enabled) before operatIon can
resume. While halted, the CPU executes
NOP's to maintain memory refresh activity.
Input, negative edge triggered. The non
maskable interrupt request line, has a
higher priority than INT and is always
recognized at the end of the current
instruction, independent of the status of
the interrupt enable flip-flop. iiiMi
automatically forces the Z80-CPU to
restart to location 0066H. The program
counter is automatically saved in the
external ,stack so that the user can
return to the program that was
interrupted. Note that continuous WAIT
cycles can prevent the current instruction from en~, and that a BUSRO will
override an NMI.
RESET
Input, active low. RESET forces the
program counter to zero and initializes
the CPU. The CPU initialization will:
1) Disable the interrupt enable flip-flop
2) Set Register I OOH
3) Set Register R = OOH
=
4) Set Interrupt Mode 0
During reset time, the address bus and
data bus go to a high impedance state
and all control output signals go to the
inactive state. No refresh occurs.
8USRQ
(Bus Reql,lest)
Input, active low. The bus request signal
is used to reql,lest the CPU address bus,
data bus and tri-state output control
signals to go to a high impedance state
so that other devices can control buses
to a high impedance state as soon as
the current CPU machine cycle is terminated.
Output, active low. Bus acknowledge is
used to indicate to the requesting
device that the CPU address bus, data
bus and tri-state control bus signals
have been set to their high impedance
state and the external device can now
control these signals.
Single phase system clock.
*While the Z80-CPU is in either a WAIT state or a Bus
Acknowledge condition, Dynamic Memory Refresh will not
occur.
VII-3
For further details on this device, please consult the
MK3880Z80 CPU Technical Manual, included in Section
IV.
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS*
Temperature Under. Bias ........................................................... Specified Operating Range
Storage Temperature ....................................................................... -65°C to +150°C
Voltage on Any Pin with Respect to Ground ................................. .' .................... -0.3 V to + 7V
Power Dissipation ................................................................................... 1.5 W
All ac parameters assume a load capacitance of 50 pF max.
*Stressesabove those listed under" Absolute Maximum Ratings" maycause permanent damage to thedevice. This is a stress rating only and functional operation of
the device at these Or any other condition above those indicated in'the operational sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
D.C. CHARACTERISTICS
TA = O°C to 70°C, Vee = 5 V ± 5% unless otherwise specified
SYMBOL
PARAMETER
MIN
VILe
Clock Input Low Voltage
VI He
Clock Input High Voltage
VIL
TYP
MAX
UNITS
-0.3
0.8
V
Vee-· 6
V ee +·3
V
Input Low Voltage
-0.3
0.8
V
V IH
Input High Voltage
2.0
Vee
V
VOL
Output Low Voltage
0.4
V
IOL = 1.8 mA
V OH
Output High Voltage
V
IOH = -250
Icc
Power Supply Current
150*
mA
III
Input Leakage Current
±10
JJA
VIN = Oto Vee
ILO
Tri-State Output Leakage
Current in Float
±10
JJA
VOUT
2.4
TEST CONDITIONS
JJA
=0.4 V to Vee
*200 mA for -4, -10 or -20 devices
CAPACITANCE
TA = 25°C, f = 1 MHz unmeasured pins returned to ground
MAX
UNIT
Clock Capacitance
35
pF
CIN
Input Capacitance
5
pF
COUl
Output Capacitance
10
pF
SYMBOL
PARAMETER
C
VII-4
MK3880-4. MK3880-6. MK3880-10 Z80-CPU
AC CHARACTERISTICS
TA =O°C to 70°C. Vee = +5 V
± 5%. Unless Otherwise Noted
SIGNAL SYMBOL PARAMETER
Ao-15
tc
yH)
yL)
tr,t
Clock Period
Clock Pulse Width. Clock High
Clock Pulse Width. Clock Low
Clock Rise and Fall Time
tD(AO)
t FlAO)
tacm
taci
Address Output Delay
Delay to Float
Address Stable Prior to MREO (Memory Cycle)
Address Stable Prior to lORa. RD or WR
(1/0 Cycle)
Address Stable From RD, WR, lORa or MREO
Address Stable From RD or WR During Float
tea
teat
tD(O)
tFlO)
tS4>(O)
0 0 _7
ts~O)
t dcm
t dci
tcdf
tH
tOL4iiMR)
tOH4>(MR)
MREO
tOH~MR)
lw\MRL)
tw(MRH)
tOL4>(IR)
tOL4iiIR)
lORa
tOH 4>(IR)
tOH4iiIR)
RD
WR
Data Output Delay
Delay to Float During Write Cycle
Data Setup Time to Rising Edge of Clock During
M1 Cycle
Data Setup Time to Falling Edge at Clock During
M2toM5
Data Stable Prior to WR (Memory Cycle)
Data Stable Prior to WR (1/0 Cycle)
Data Stable from WR
Input Hold Time
400
250
110
110
t OL4>(WR)
t OL4i(wR)
tOHi(wR)
twe\iiiRL)
WR Delay From Rising Edge of Clock, WR Low
WR Delay From Falling Edge of Clock. WR Low
WR Delay From Falling Edge of Clock. WR High
Pulse Width, WR Low
NOTES:
A. Data should be enabled onto the CPU data bus when RD is active. During
interrupt acknowledge data should be enabled when M1 and IORO are both
active.
VII-5
165
65
65
90
80
[24]
[25]
[3]
[4]
[15]
[16]
[26]
[27]
230
90
150
130
80
90
50
35
30
60
50
40
[5]
[6]
[17]
[18]
[19]
0
[28]
[29]
[30]
0
[7]
0
100
15
20
85
20
70
100
85
70
100
85
70
[20]
[21]
[20]
[21]
90
75
65
110
85
70
100
85
70
110
85
70
100
130
100
110
85
95,.,
85
85
70
80
70
70
15
80
15
65
80
80
90
100
[10]
[12]
(D)
2000
20
110
90
[13]
[14]
[8]
[9]
Rising Edge of Clock. RD Low
Falling Edge of Clock, RD Low
RiSing Edge of Clock. RD High
Falling Edge of Clock, RD High
[12]
(D)
20b0
30
3880-6
MIN
MAX
(ns)
(ns)
[1]
[2]
lORa Delay From Rising Edge of Clock.
lORa Low
lORa Delay From Falling Edge of Clock.
lORa Low
lORa Delay From Rising Edge of Clock.
lORa High
lORa Delay From Falling Edge of Clock
Clock. lORa High
From
From
From
From
[12]
(D)
2000
30
145
110
20
MREO Delay From Falling Edge of Clock,
MREOLow
MREO Delay From Rising Edge of Clock.
MREOHigh
MREO Delay From Falling Edge of Clock.
MREOHigh
Pulse Width, MREO Low
Pulse Width, MREO High
tOH 4>(RO)
t OH4iiBO)
tOL~RO)
3880-4
MIN
MAX
(ns)
(ns)
180
180
RD Delay
RD Delay
RD Delay
RD Delay
tOLiRO)
3880
MIN
MAX
(ns)
(ns)
[22]
60
70
70
[22]
B. The Rlm' signal must be active for a minimum of 3 clock cycles.
(Conl'd. on next page].
II
MK3880-4, MK3880-6, MK3880-10 Z80-CPU
3880
MIN
MAX
(ns)
(ns)
SIGNAL SYMBOL PARAMETER
M1
tOUM1)
tOH(Ml)
RFSH
tOURF)
3880·4
MIN
MAX
(ns) . (ns)
3880-6
MIN
MAX
(ns)
(ns)
M'j Delay From Rising Edge of Clock M1 Low
M1 Delay From Rising Edge of Clock M1 High
130
130
100
100
80
80
RFSH Delay From Rising Edge of Clock,
180
130
110
150
120
100
~SHLow
RFSH Delay From Rising Edge of Clock,
RFSH High
tOH(RF)
WAIT
tS(WT)
HALT
tD(Hn
ViiAiT Setup Time to Falling Edge of Clock
IHACf Delay Time From Falling Edge of Clock
INT
tS(1n
INT Setup Time to Rising Edge of Clock
80
80
70
NMI
t....{NMI)
Pulse Width, NMI Low
80
80
70
BUSRQ t 5(80)
BUSRQ Setup Time to Rising Edge of Clock
80
50
50
BUSAK tOUBA)
BUSAK Delay From Rising Edge of Clock,
BUSAKLow
BUSAK Delay From Falling Edge of Clock.
BUSAK High
tOH(BA)
RESET
ts(RS)
RESET Setup Time to Rising Edge of Clock
tF(C)
Delay to/from Float (MREQ, IORQ, RD and WR)
t m,
M1 Stable Prior to IORQ (Interrupt Ack.) .
+ tf-75
[1)
tACM ~ t w (4) HI
[2)
taci = tc - 80
[3)
tCA = t w (4)LI
+ t,-4O
[19) ted!
[4)
teaf = t w (4)L)
+ t, - 60
[20) tw iMRL) = tc -30
t.lcm = tC-210
tdci = t w (4)L)
+ t, - 210
[7)
tcd! = tw (4)L)
+ t, - 80
[8)
tw (MRL) = tc - 40
[9)
tw (MRH) = tw (4)H)
[12) tc
= te -
[22) tw (Wii)
[24) tACM
+ tf - 30
40
+ tw (4)H) +tf - 80
=t w (4)H) + t w (4)L) + t, + tf
= te -30
[26) tCA = tw (4)L)
+ t, -50
[27) teaf = tw (4)L)
+ t,-45
[28) tdcm
90
110
100
90
60
60
[30) tedf
+ t, -50
70
80
[31]
[23]
LOAD CIRCUIT FOR OUTPUT
Vee
TEST POINT
FROM OUTPUT _ _---+---4~
UNDER TEST
R2 =9,S3KO
=tc -140
[14) taci = tc -70
t w (4)L)
100
100
[11]
260
120
90
= tw (4)H) +tf-50
129) t.lci = tw (4)L) + t,-14O
~
300
[25) taci = tc -55
[13) tacm = ~w (
lEI
Interrupt Enable In (input, active high)
This signal is used to form a priority interrupt
daisy chain when more than one interrupt
driven device is being used. A high level on
this pin indicates that no other devices of
higher priority are being serviced by a CPU
interrupt service routine.
lEO
Interrupt Enable Out (output, active high)
The lEO signal is the other signal required to
form a daisy chain priority scheme. It is high
only if lEI is high and the CPU is not servicing
an interrupt from this PIO. Thus this signal
blocks lower priority devices from interrupting while a higher priority device is being
serviced by its CPU interrupt service routine.
INT
Interrupt Request (output, open drain, active
low)
When INT is active the l80-PIO is requesting
an interrupt from the l80-CPU.
Ao-A 7
Port A Bus (bidirectional, tri-state)
This 8 bit bus is used to transfer data andlor
status or control information between Port A
of the l80-P10 and a peripheral device. Ao is
the least significant bit ofthe Port Adata bus.
A STB
Port A Strobe Pulse from peripheral Device
(input, active low)
The meaning of this Signal depends on the
mode of operation selected for Port A as
follows:
System Clock (input)
The l80-P10 uses the standard l80 system
clock to synchronize certain signals internally.
This is a single phase clock.
Machine Cycle One Signal from CPU (input,
active low)
This signal from the CPU is used as a sync
pulse to control several internal PIO operations. When M 1 is active and the RD signal is
active, the l80-CPU is fetching an instruction
from memory. Conversely, when M1 is active
and lORa is active, the CPU is acknowledging
an interrupt. In addition, the M1 signal has
two other functions within the l80-PI0.
1. M 1 synchronizes the PIO interrupt logic.
2. When M1 occurs without an active RD or
lORa signal, the PIO logic enters a reset
state.
lORa
If RD is active a MEMORY READ or 1/0 READ
operation is in progress. The RD signal is
used with BIA Select, CID Select, CE and
lORa signals to transfer data from the l80PIO to the l80-CPU.
InputlOutput Request from l80-CPU (input,
active low)
The lORa Signal is used in conjunction with
the BIA Select, CID Select, CE, and RD
signals to transfer commands and data
between the l80-CPU and the l80-PI0.
When CE, RD and lORa are active, the port
addressed by BIA will transfer data to the
CPU (a read operation). Conversely, when CE
and lORa are active but RD is not active, then
the port addressed by BIA will be written into
from the CPU with either data or control
information as specified by the CID Select
signal. Also, if lORa and M1 are active
simultaneously, the CPU is acknowledging
an interrupt and the interrupting port will
automatically place its interrupt vector on the
CPU data bus if it is the highest device
requesting an interrupt.
Read Cycle Status from the l80-CPU (input,
active low)
VII-10
1) Output mode: The positive edge of this
strobe is issued by the peripheral to
acknowledge the receipt of data made
available by the PIO.
2) Input mode: The strobe is issued by the
peripheral to load data from the peripheral
into the Port A input register. Data is
loaded into the PIO when this signal is
active.
3) Bidirectional mode: When this signal is
active, data from the Port A output register
is gated onto Port A bidirectional data bus.
The positive edge of the strobe acknowledges the receipt of the data.
4) Control mode: The strobe is inhibited internally.
ARDY
Register A Ready (output, active high)
The meaning of this signal depends on the
mode of operation selected for Port A as follows:
status or control information between Port B
of the PIO and a peripheral device. The Port B
data bus is capable of supplying 1.5 ma@ 1.5 V
to drive Darlington transistors. Bo is the least
significant bit of the bus.
1) Output mode: This signal goes active to
indicate thatthe Port A output register has
been loaded and the peripheral data bus is
stable and ready for transfer to the
peripheral device.
Port B Strobe Pulse from Peripheral Device
(input, active low)
The meaning of this signal is similar to that of
A STB with the following exception:
2) Input mode: This signal is active when the
Port A input register is empty and is ready
to accept data from the peripheral device.
3) Bidirectional mode: This Signal is active
when data is available in Port A output
register for transfer to the peripheral
device. In this mode data is not placed on
the Port A data bus unless A STB is active.
Inthe PortAbidirectional mode this signal
strobes data from the peripheral device
into the Port A input register.
BRDY
Register B Ready (output, active high)
The meaning ofthis signal is similar to that of
A Ready with the following exception:
4) Control mode: This Signal is disabled and
forced to a low state.
In the Port A bidirectional mode this signal
is high when the Port A input register is
empty and ready to accept data from the
peripheral device.
Port B (bidirectional, tristate)
This 8 bit bus is used to transfer data and/or
OUTPUT LOAD CIRCUIT
Figure 2
TEST POINT
FROM OUTPUT o----.----~~---IIC
UNDER TEST
1 N914 OR EQUIVALENT
CR,
CL
CL
r
250 p.A
For further details on this device, please consult the PIO
MK3881 Technical Manual, included in Section IV.
VII-11
c
c
50 pF on 0 - 0 7
50 pF on
Others
A8
ELECTRICAL SPECIFICATIONS
MK3881
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ...•.•..•.•.•...•..•••••...•.•.••..•............. , .......... Specified operating range
Storage Temperature ....••.........•••..•...•..•..•.•........•......•.......•.......•...... -65°C to +150°C
Voltage On Any Pin With ....••..•..•.•..••.••.•.•....•......•..•.••••....•.....••...•••..•..• -0.3 V to +7 V
Respect To Ground
Power Dissipation .•...••.•.................•....•..•..•........•......•...............•......•...... .6 W
All ac parameters assume a load capacitance of 100 pF max. Timing references between two output signals assume a load
difference of 50 pF max.
*Stresses above those listed under "Absolute Maximum Ratings" maycause permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
D.C. CHARACTERI.STICS
TA = O°C to 70°C, Vee = 5 V ± 5% unless otherwise specified
SYMBOL
PARAMETER
MIN
MAX
UNIT
VILe
Clock Input Low Voltage
-0.3
0.80
V
V IHe
Clock Input High Voltage
Vee-· 6
Vee +.3
V
V IL
Input Low Voltage
-0.3
0.8
V
V IH
Input High Voltage
2.0
Vee
V
VOL
Output Low Voltage
0.4
V
V OH
Output High Voltage
lee
Power Supply Current
70*
rnA
lu
Input Leakage Current
±10
pA.
ILOH
Tri-State Output Leakage Current in Float
10
pA.
ILOL
Tri-State Output Leakage Current in Float
-10
pA.
=Oto Vee
V OUT = 2.4 to Vee
V OUT = 0.4 V
ILO
Data Bus Leakage Current in Input Mode
±10
pA.
0:5 VIN :5 Vee
IOHD
Darlington Drive Current
rnA
VOH = 1.5V
Port B Only
2.4
V
-1.5
TEST CONDITION
=2.0 rnA
IOH =-250 pA.
IOL
VIN
*150 rnA for -4, -10, and -20 devices.
CAPACITANCE
TA = 25°C, f 1 MHz
=
MAX
UNIT
Clock Capacitance
10
pF
Unmeasured Pins
CIN
Input Capacitance
5
pF
Returned to Ground
COUT
Output Capacitance
10
pF
SYMBOL
PARAMETER
C~
VII-12
TEST CONDITION
A.C. CHARACTERISTICS MK3881. MK3881·10. MK3881·20. Z80·PIO
TA =O°C to 70°C. V CC = +5 V ± 5%. unless otherwise noted
SIGNAL
4>
C/O SEL
CE ETC.
3881
MIN
MAX
3881·4
MIN
MAX
UNIT
400
250
105
105
[1]
2000
2000
30
nsec
nsec
nsec
nsec
SYMBOL
PARAMETER
tc
tW(H)
tW(L)
t" lj
Clock
Clock
Clock
Clock
th
Any Hold Time for Specified Set·Up Time
0
0
nsec
tS(CS)
Control Signal Set-up Time to Rising Edge of
4> During Read or Write Cycle
50
50
nsec
tOR(O)
tS(O)
Data Output Delay from Falling Edge of RD
Data Set-up Time to Rising Edge of 4> During
Write or M1 Cycle
Data Output Delay from Falling Edge of lORa
During INTA Cycle
Delay to Floating Bus (Output Buffer Disable Time)
Do - 0 7
tOI(O)
tF(O)
Period
Pulse Width. Clock High
Pulse Width. Clock Low
Rise and Fall Times
170
170
[1]
2000
2000
30
430
380
nsec
nsec
340
250
nsec
160
110
nsec
50
50
lEI
tS(IEI)
lEI Set-Up TIme to Falling Edge of lORa During
INTAcycle
lEO
tOH(lO)
tOL(lO)
tOM(IO)
lEO Delay Time from Rising Edge of lEI
lEO Delay Time from Falling Edge of lEI
210
190
160
130
nsec
nsec
lEO Delay from Falling' Edge of M1 (Interrupt
Occurring Just Prior to M1) See Note A.
300
190
nsec
lORa
tS(IR)
lORa Set-Up Time to Rising Edge of 4> During
Read or Write Cycle
250
M1
tS(M1)
~Set-Up
Time to Rising Edge of 4> During
INTA or M1 Cycle. See Note B.
210
90
nsec
RD
tS(RO)
RD Set-Up Time to Rising Edge of During
Read or M 1 Cycle
240
115
nsec
tS(PO)
Port Data Set-Up Time to Rising Edge of
STROBE (Mode 1)
Port Data Output Delay from Falling Edge of
STROBE (Mode 2)
Delay to Floating Port Data Bus from Rising
Edge of STROBE (Mode 2)
Port Data Stable from Rising Edge of lORa
During WR Cycle (Mode 0)
260
230
nsec
Pulse Width, STROBE
150
150
[4]
[4]
t05(PO)
Ao- A 7
Bo - B7
tF(PO)
tOI(PO)
ASTB
BSTB
tWIST)
INT
tD(IT)
tD(IT3)
INT Delay Time from Rising Edge of
INT Delay Time from Data Match During
Mode 3 Operation
ARDY
tOH (RY)
BRDY
tOL(RY)
Ready Response Time from Rising Edge of lORa
Ready Response Time from Rising Edge of
STROBE
Sfif<5BE
VII-13
140
140
nsec
. 115
nsec
230
210
nsec
200
180
nsec
200
180
nsec
nsec
nsec
490
420
440
tc+46O
t c+
400
tc+41 0
t c+
360
380
nsec
nsec
nsec
nsec
A. 2.5 tc > (N.2)tDL(IO)+tDM(IO)+tS(IEI)+TTL Buffer Delay, if any.
B.
(IJ
(2J
(3J
Increase 101 (0) by 1 0 nsec for each 50 pF increase in loading up to 200 pF
(4J
For Mode 2: tw (ST) > tS(PO)
[5]
Increase these values by 2 nsec for each 10 pF increase in loading up to
100 pF max.
max.
M1 must be active for a minimum of 2 clock periods to reset the PIO.
tc=tW(H)+Iw(L)+tr+tf
Increase tOR(O)by 1 0 nsectore8oh 50pF increase in loading upto 200pF
max.
TIMING DIAGRAM
Figure 3
Timing measurements are made at the following voltages, unless otherwise specified:
CLOCK
OUTPUT
INPUT
FLOAT
lEI
lEO
READY
(A ROY OR
B ROY)
STROBE
(Am OR
iISi'B)
(MODE 2)
(MODE 1)
(MODE 3)
VII-14
"'"
4,2V
2.0V
2.0V
t:.V
"0"
O.BV
O.BV
O.BV
0.5V
ORDERING INFORMATION
PART NO.
DESIGNATOR
PACKAGE TYPE
MK3881N
Z80-PIO
Plastic
2.5 MHz
MK3881P
Z80-PIO
Ceramic
2.5 MHz
MK3881N-4
Z80A-PIO
Plastic
4.0 MHz
MK3881P-4
Z80A-PIO
Ceramic
4.0 MHz
MK3881P-10
Z80-PIO
Ceramic
4.0 MHz
VII-15
MAX CLOCK FREQUENCY
TEMPERATURE
RANGE
0° to 70°C
-40° to +85°C
VII-16
MOSTEI(@
zao
MICROCOMPUTER
Counter Timer Circuit
MK3882
FEATURES
zaO-CTC PIN CONFIGURATION
Figure 1
o All inputs and outputs fully TIL compatible
,. I
o Each channel may be selected to operate in either
Counter Mode or Timer Mode
DATA BUS
o Used in either mode, a CPU-readable Down Counter
indicates number of counts-to-go until zero
ZC/TO O
ZetTD,
D,
D5
D6
D7
o A Time Constant Register can automatically reload the
Down Counter at Count Zero in Counter and Timer Mode
CHANNEL
SIGNALS
ZCfT02
MK3SS2
2S0-CTC
CSO
cs,
o Selectable positive or negative trigger initiates time
operation in Timer Mode. The same input is monitored
for event counts in Counter Mode.
CTC
CONTROL
o Three channels have Zeto CountlTimeout outputs
capable of driving Darlington transistors
+5V
o Interrupts may be programmed to occur on the zero
count condition in any channel .
GND
·r
o Daisychain priority interrupt logic included to provide for
automatic interrupt vectoring without external logic
INTERRUPT {INT
CONTROL
INT
ENA~~:
~:
ENAa~~
11
OUT
INTRODUCTION
The ZBO-Counter Timer Circuit (CTC) is a programmable
component with four independent channels that provide
counting and timing functions for microcomputer systems
based on the Z80-CPU. The CPU can configure the CTC
channels to operate under various modes and conditions as
required to interface with a wide range of devices. In most
applications, little or no external logic is required. The Z80CTC utilizes N-channel silicon gate depletion load
technology and is packaged in a 28-pin DIP. The Z80-CTC
requires only iI single 5 volt supply and a one-phase 5 volt
clock.
L-._ _ _ _--l
the Z80-CTC. There are 8 bits on this bus, of
which Do is the least significant.
CS1-CSO
CTC PIN DESCRIPTION
A diagram of the Z80-CTC pin configuration is shown in
Figure 1. This section describes the function of each pin.
Z80-CPU Data Bus (bidirectional, tristate)
This bus is used to transfer all data and
command words between the Z80-CPU and
VII-17
Channel Select (input, active high)
These pins form a 2-bit binary address code
for selecting one ofthe four independent CTC
channels for an 1/0 Write or Read (See truth
table below.)
ChO
Ch1
Ch2
Ch3
CS1
0
0
1
1
CSO
0
1
0
1
Chip Enable (input, active low)
A low level on this pin enables the CTC to
accept control words, Interrupt Vectors, or
time constant data words from the Z80 Data
Bus during an I/O Write cycle, or to transmit
the contents ofthe Down.Counter to the CPU
during an I/O Read cycle. In most applications this signal is decoded from the 8 least
significant bits of the address bus for any of
the four I/O port addresses that are mapped
to the four Counter/Timer Channels.
Clock (4))
Input/Output Request from CPU (input,
active low)
The 10RO signal is used in conjunction with
the CE and RD signals to transfer data and
Channel Control Words between. the Z80CPU and the CTC. During a CTC Write Cycle,
10RO and CE must be true and RD false. The
CTC does not receive a specific write Signal.
instead generating its own internally from the
inverse of a valid RD signal. In a CTC Read
Cycle, 10RO, CE and RD must be active to
place the contents of the Down Counter on
the zao Data Bus. If 10RO and M1 are both
true, the CPU is acknowledging an interrupt
request, and the highest-priority interrupting
channel will place its Interrupt Vector on the
Z80 Data Bus.
lEI
lEO
Interrupt Enable Out (output, active high)
The lEO signal. in conjunction with lEI, is
used to form a system-wide interrupt priority
daisy chain. lEO is high only if lEI is high and
the CPU is not servicing an interrupt from any
CTC channel. Thus this signal blocks lower
priority devices from interrupting while a
higher priority device is being serviced by the
CPU.
INT
Interrupt Request (output, open drain, active
low)
This signal goes true when any CTC channel
which has been programmed to enable
interrupts has a zero-count condition in its
Down Counter.
RESET
Reset (input, active low)
This signal stops all channels from counting
and resets channel interrupt enable bits in all
control registers, thereby disabling CTCgenerated interrupts. The ZC/TO and INT
outputs go to their inactive states, lEO reflects
lEI. and the CTC's data bus output drivers go
to the high impedance state.
System Clock (input)
This single-phase clock is used by the CTC to
synchronize certain signals internally.
Machine Cycle One Signal from CPU (input,
active low)
When M1 is active and the RD signal is
active, the CPU isfetching an instruction from
memory. When M1 is active and 10RO is
active, the CPU is acknowledging an
interrupt, alerting the CTC to place an
Interrupt Vector on the zao Data Bus if it has
daisy chain priority and one of its channels
has requested an interrupt.
RD
capability. A high level on this pin indicates
that no other interrupting devices of higher
priority are being serviced by the Z80-CPU.
Read Cycle Status from the CPU (input, active
low)
The RD signal is used in conjunction with the
10RO and CE signals to transfer data and
Channel Control Words between the Z80CPU and the CTC. During a CTC Write Cycle,
10RO and CE must be true and RD false. The
CTC does not receive a specific write signal.
instead generating its own internally from the
inverse of a valid RD signal. In a CTC Read
Cycle, 10RO, CE and RD must be active to
place the contents of the Down Counter on
the zao Data Bus.
CLK/TRG3- External ClockiTimer Trigger (input. userCLK/TRGO selectable active high or low)
There are four CLK/TRG pins, corresponding
to the four independent CTC channels. In the
Counter Mode, every active edge on this pin
decrements the Down Counter. In the Timer
Mode, an active edge on this pin initiates the
timing function. The user may select the
active edge to be either rising or falling.
ZC/T02ZC/TOO
Zero Count/Timeout (output, active high)
There are three ZC/TO pins, corresponding to
CTC channels 2 through O. (Due to package
pin limitations channel 3 has no ZC/TO pin.)
In either Counter Mode orTimer Mode, when
the Down Counter decrements to zero an
active high going pulse appears at this pin.
For further details on this device, please consult the CTC
MK3aa2 Technical Manual, included in Section IV.
Interrupt Enable In (input, active high)
This signal is used to help form a systemwide interrupt daisy chain which establishes
priorities when more than one peripheral
device in the system has interrupting
VII-18
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ................•..........•.............•........•.....•... Specified operating range
Storage Temperature .................................•.......•....••••........••....•...••• -65°C to +150°C
Voltage On Any Pin With Respect To Ground •.•••........•..•.....•.......•........•••...•...••. -0.3 V to +7 V
Power Dissipation ........................••....•..............•.......•............•••.........•.•. 0.8 W
All ac parameters assume a load capacitance of 100 pF max. Timing references between two output signals assume a load
difference of 50 pF max.
*Stressesabove those listed under "Absolute Maximum Ratings" maycause permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
D.C. CHARACTERISTICS·
TA = DoC to 70°C, Vee = 5 V ± 5% unless otherwise specified
SYMBOL
PARAMETER
MIN
MAX
UNIT
VILe
Clock Input Low Voltage
-0.3
0.80
V
VIHe
Clock Input High Voltage (1)
Vee-· 6
Vee +.3
V
VIL
Input Low Voltage
-0.3
0.8
V
VIH
Input High Voltage
2.0
Vee
V
VOL
Output Low Voltage
0.4
V
IOL=2mA
VOH
Output High Voltage
V
IOH = -250 pA
Icc
Power Supply Current
120
mA
Te = 400 nsec**
III
Input Leakage Current
±10
pA
VIN = OtoVee
ILOH
Tri-State Output Leakage Current in Float
10
pA
V OUT = 2.4 to Vee
ILOL
Tri-State Output Leakage Current in Float
-10
pA
V OUT = 0.4 V
IOHD
Darlington Drive Current
mA
V OH = 1.5 V
2.4
-1.5
TEST CONDITION
**Te = 250 nsec for MK3882-4
CAPACITANCE
TA = 25°C, f = 1 MHz
SYMBOL
PARAMETER
MAX
UNIT
CcJ>
Clock Capacitance
20
pF
Unmeasured Pins
CIN
Input Capacitance
5
pF
Returned to Ground
COUT
Output Capacitance
10
pF
VII-19
TEST CONDITION
III
A.C. CHARACTERISTICS MK3882. MK3882-10. Z80-CTC
TA =' O°C to 70°C. Vee = +5 V ± 5%. unless otherwise noted
38823882-4
MIN
MAX
SIGNAL
SYMBOL
PARAMETER
tc
tw(H)
tw(l)
t,. t f
Clock Period
Clock Pulse Width. Clock High
Clock Pulse Width. Clock low
Clock Rise and Fall Times
tH
Any Hold Time for Specified
Setup Time
CS. CEo etc. ts(CS)
to(D)
ts(D)
Do - D7
tol(D)
t~D)
lEI
Control Signal Setup Time to
Rising Edge of During Read
or Write Cycle
Data Output Delay from Rising
Edge of During Read Cycle
Data Setup Time to Rising Edge
of During Write or M1 Cycle
Data Output Delay from Falling
Edge of lORa During INTA Cycle
Delay to Floating Bus (Output
Buffer Disable Time)
ts(lEI)
lEI Setup Time to Falling Edge
of lORa During INTA Cycle
tOH(lO)
lEO Delay Time from Rising Edge
of lEI
lEO Delay Time from Falling
Edge of lEI
lEO Delay from Falling Edge of
M1 (Interrupt Occurring just
Prior to M1)
tOL(IO)
400
170
170
(1 )
2000
2000
30
MIN
MAX
250
105
105
(1 )
2000
2000
30
UNIT COMMENTS
ns
ns
ns
0
0
ns
160
145
ns
240
60
200
50
ns
ns
340
160
ns
230
110
ns
140
200
220
160
ns
(3)
190
130
ns
(3)
300
190
ns
(3)
toM(IO)
lORa
ts(IR)
lORa Setup Time to Rising Edge
of During Read or Write Cycle
250
115
ns
M1
ts(M1)
M1 Setup Time to Rising Edge
of During INTA or M1 Cycle
210
90
ns
RD
ts(RD)
RD Setup Time to Rising Edge
of During Read or M1 Cycle
240
115
ns
INT
to(IT)
INT Delay from Rising Edge of
td CK)
t,. t f
Clock Period
Clock and Trigger Rise and Fall
Times
Clock Setup Time to Rising Edge
of for Immediate Count
Trigger Setup Time to Rising
Edge of for Enabling of
Prescaler on Following Rising
Edge of
ts(TR)
ClK/
TRG O_3
tvJCTH)
tvJCTl)
tdU Rll-
lEI
I---+ISUEI)
lEO
1--+----·IC(CKl-+--------~1
(COUNTER MODEl
ClK/
TRG O_3
tS(TRI
(TIMER MODEl
ZC/TOO_2
"'"
4.2 V
2.0V
2.0V
flV
"0"
O.BV
O.BV
O.BV
0.6V
ORDERING INFORMATION
PART NO.
DESIGNATOR
PACKAGE TYPE
MAX CLOCK FREQUENCY
MK3882N
Z80-CTC
Plastic
2.5 MHz
MK3882P
Z80-CTC
Ceramic
2.5 MHz
MK3882N-4
Z80A-CTC
Plastic
4.0 MHz
MK3882P-4
Z80A-CTC
Ceramic
4.0 MHz
MK3882P-10
Z80-CTC
Ceramic
4.0 MHz
TEMPERATURE
RANGE
0° to 70°C
-40° to +85°C
•
VII-23
VII·24
MOSTEI<.
zao
MICROCOMPUTER
Direct Memory Access Controller MK3883
FEATURES
o Transfers, searches and searchltransfers in byte-ata-time, burst or continuous modes. Cycle length and
edge timing can be programmed to match the speed
of any port.
o Dual port addresses (source and destination)
generated for memory-to-I/O, memory-to-memory,
or I/O-to-I/O operations. Addresses may be fixed or
automatically i ncrementedldecremented.
o Standard Z80 Family bus-request and prioritized
interrupt-request daisy chains implemented without
external logic. Sophisticated, internally modifiable
interrupt vectoring.
o Direct interfacing to system buses without external
logic.
GENERAL DESCRIPTION
o Extensive programmability of functions. CPU can
read complete"channel status.
The MK3883 Z80 DMA (Direct Memory Access) is a
powerful and versatile device for controlling and
processing transfers of data. Its basic function of
managing CPU-independent transfers between two
ports is augmented by an array offeatures that optimize
transfer speed and control with little or no external logic
in systems using an 8- or 16-bit data bus and a 16-bit
address bus.
PIN FUNCTIONS
PIN ASSIGNMENTS
o Next-operation loading without disturbing current
operations via buffered starting-address registers.
An entire previous sequence can be repeated
automatically.
Figure 2
Figure 1
ZIODMA
~{
Ag
A1
A2
A3
DATA
BUS
~
AS
AS
A7
SYSTEM
ADDRESS
BUS
As
Ag
BUS
{
CONTROL
At;
39
-'7
A3
3
38 lEI
A2
4
37
A1
5
36 lEO
Ag
6
35 DO
7
340 1
WR
8
33 02
RO
9
3203
+6V 11
MiiEii
}
12
29 0 6
28 De
BAI14
270;
CE/WAIT 16
INTERRUPT
CONTROL
CLK
VII-25
3104
30 GNO
1iiW 13
BUSRQ 15
lEO
iiiii
CLK
10RQ 10
}DMA
CONTROL
GND
40
2
A"
A12
CONTROL
BUS
@:X____
IEO _ _ _ _ _ _ _ _ _~:,r_
VII-53
•
ABSOLUTE MAXIMUM RATINGS
Voltages on all inputs and outputs with respect to GND ........................................... -0.3V to +7.0\
Operating Ambient Temperature ............................................ As Specified in Ordering Informatior
Storage Temperature ........................................................................ -65°C to +150 0 (
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating, only; operation of the device at an
condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for extended periods rna
affect device reliability.
STANDARD TEST CONDITIONS
The characteristics below apply for the following
standard test conditions, unless otherwise noted. All
voltages are referenced to GND. Positive current flows
into the referenced pin. Standard conditions are as
follows:
vcc
2.1K
FROM OUTPUTO-_......._
UNDER TEST
• +4.75V::; VCC::; +5.25V
• GND:= OV
• TA as specified in Ordering Information
......-+lH
All AC parameters assume a load capacitance of 100 pF
max. Timing references between two output signals
assume a load difference of 50 pF max.
DC CHARACTERISTICS
SYM
PARAMETER
MIN
MAX
UNIT
TEST CONDITION
VILC
Clock Input Low Voltage
-0.3
+0.80
V
VIHC
Clock Input High Voltage
VCC -0.6
+5.5
V
VIL
Input Low Voltage
-0.3
+0.8
V
VIH
Input High Voltage
+2.0
+5.5
V
VOL
Output Low Voltage
+0.4
V
IOL:= 2.0mA
VOH
Output High Voltage
+2.4
V
IOH:= -250 iJ-A
III
Input Leakage Current
-10
±10
iJ-A
O<==
~------------------------------
OATA _______-JX. . ___IN______
OATA ------------INTERRUPT ACKNOWLEDGE CYCLE
Figure 7
RETURN FROM INTERRUPT CYCLE
Figure '8
CLOCK
CLOCK
M'
---'1
iii \ ' - -_ _ _ _ _
RO
'-----I
lORa
R O - - - - - - - - - -_ _ _ _ _ _ _ ___
lEI
...... _____ 1I
=====:=::7
IEI------
lEO
OATA--------------<~>----VII-68
r-
------~/
MK-DART READ AND WRITE REGISTERS
Figure 9
READ REGISTER 0
READ REGISTER,.
10l§710l§.10~&10[S4~0~ALLSENT
10710eI0.iO~03102Io,IOol
L R.CHARACTERAVAILABLE
L,NT PENDING ICH. A ONLY)
I
~~~
L-NOTUSED
~~~UFFER EIMPTY
PARITY ERROR
RI
CTS
USED WITH ""EXTERNAV
STATUS INTERRUPT""
FRAMING ERROR
NOT USfD
MODE
Rx OVERRUN ERROR
NOT USED
·U.ed with Speciel Receive Condition Mode
BREAK
READ REGISTER 2
INTERRUPT VECTOR
"Variable If "StatuI Affect.
Veeto," is Programmed
WRITE REGISTER 0
WRITE REGISTER 1
10710el051041031021o,IOoi
10710.10510410310210,1001
l
--C: ooo
00'
0'0
011
'00
'0'
REGISTER
REGISTER
REGISTER
REGISTER
REGISTER
REGISTER
T
1
0
1
2
3
4
6
00
001
0'0
o1 1
1 00
, 01
1 10
NULL CODE
NOT USED
RESET EXT/STATUS INTERRUPTS
CHANNEL RESET
ENABLE INT ON NEXT Rx CHARACTER
RESET lxlNT PENDING
ERROR RESET
, "
RETURN FROM INT ICH·A ONLY)
I L EXTINT ENABLE
L- TxlNT ENABLE
STATUS AFFECTS VECTOR
ICH. B ONLY}
00 Rx INT DISABLE
o 1 Rx INT ON FIRST CHARACTER
1 OINT ON ALL Rx CHARACTERS (PARITY
AFFECTS VECTOR)
1 1 INT ON ALL Rx CHARACTERS (PARITY
DOES NOT AFFECT VECTOR)
1--_____ WAIT/READY ON R/T
I
"------WAIT/RE~DYFUNCTION
'---_ _ _ _ _ _ WAIT /READV ENABLE
~------------NOTUSEO
WRITE REGISTER 3
WRITE REGISTER 2 (CHANNEL 8 ONLY)
11
10710.10.10410310210,1001
I
L
L--
R.ENABLE
NOTUSED
1--------___ AUTO ENABLES
1--------------- 00 Rx 5 BITS/CHARACTER
INTERRUPT
o 1 Rx 7 BITS/CHARACTER
VECTOR
1 0 Rx 6 BITS/CHARACTER
1 1 Rx 8 BITS/CHARACTER
WRITE REGISTER 4
ITT
WRITE REGISTER 5
107IT0610~0~410Llli310t~ :~;
10710e10&1041031021o,IOol
o
0'
L.:::::~:::~~DD·
NOT USED
LNOTUSED
1 STOP BIT ICHARACTER
Tx ENABLE
1 0 1 Y2 STOP BITS/CHARACTER
1 1 2 STOP BITS/CHARACTER
NOT USED
00
1
10
11
o
USED
SEND BREAK
00
01
10
11
Xl CLOCK MODE
X16 CLOCK MODE
X32 CLOCK MODE
X64 CLOCK MODE
Tx 6
Tx 7
Tx 6
Tx 8
BITS/CHARACTER
BITS/CHARACTER
BITS/CHARACTER
BITS/CHARACTER
OTR
VII-69
OR ON SPECIAL
RECEIVE CONDITION
II
ABSOLUTE MAXIMUM RATINGS
Voltages on all inputs and outputs with respect to GND ......................................... -0.3 V to +7.0 V
Operating Ambient Temperature ...•........................................ As Specified in Ordering Information
Storage Temperature •....•..............•.................................................. -6S0C to +1S0°C
Power Dissipation •...........•..................................................................... 1.S W
Stressesgreaterthan those listed under Absolute Maximum Ratings may ca use permanent damagetothe device. This is a stress rating only; operation oftha device at
any condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
STANDARD TEST CONDITIONS
The characteristics below apply for the following
standard test conditions. unless otherwise noted. All
voltages are referenced to GND. Positive current flows
into the referenced pin. Standard conditions are as
follows:
• +4.7SV:5 VCC:5 +S.2SV
• GND = OV
• TA as specified in Ordering Information
2.1K
FROM OUTPUT O---r--.....-iQ-I
UNDER TEST
All AC parameters assume a load capacitance of
100pF max. Timing references between two output
signals assume a load difference of SOpF max.
DC CHARACTERISTICS
SYM
PARAMETER
MIN
MAX
UNIT
VILC
Clock Input Low Voltage
-0.3
+0.80
V
V IHC
Clock Input High Voltage
Vcc-O·6
+S.S
V
V IL
Input Low Voltage
-0.3
+0.8
V
VIH
Input High Voltage
+2.0
+S.S
V
VOL
Output Low Voltage
+0.4
V
VOH
Output High Voltage
+2.4
IL
Inputl3-State Output Leakage
Current
-10
IL(Rl)
RI Pin Leakage Current
-40
Icc
Power Supply Current
TEST CONDITION
V
= 2.0 mA
IOH =-2S01-1A
+10
I-IA
0.4L
RxO _ _
W/ROY
(i)
~~~.
_ _ _ _ __
~@~~
INT
ELECTRICAL CHARACTERISTICS
III
Figure 11
elK
x'-__
iORii. AD - - - - - - - r " ......_ - i - - - - - T - _ ; - - - J
lEI
lEO
VII-73
VII-74
MOSTEl(.
zao MICROCOMPUTER PERIPHERALS
Serial Timer Interrupt Controller
MK3801
FEATURES
DEVICE PINOUT
Figure 1
o Full duplex USART with programmable DMA control
signals
TAO
TBO
TCO
o Two binary delay timers
o Two full feature timers with
• Delay to interrupt mode
• Pulse width measurement mode
• Event counter mode
TOO
TCLK
vee
RC
S'
SO
TC
M1
RESET
o Eight general purpose lines with
• Full bi-directionall/O capability
• Edge triggered interrupts on either edge
'0
'1
'2
o Full control of each interrupt channel
• Enable/disable
• Maskable
• Automatic end-of-interrupt mode
• Software end-of-interrupt mode
'3
'4
'5
,~
'7
o 2.5,4 MHz, and 6 MHz versions available
'E'
1NT
INTRODUCTION
'EO
The MK3801 Z80 STI (Serial Timer Interrupt) is a
multifunctional peripheral device for use in Z80 microprocessor based systems. It is designed to optimize current
systems by reducing chip count and system costs. By
providing a USART, four timers (two binary and two full
function), and eight bi-directionall/O lines with individually
programmable interrupts, the MK3801 can make substantial improvement to any Z80 based system.
Control and operation of the MK3801 are provided by 24
internal registers accessible by the Z80 bus. Sixteen of
these registers are directly addressable and accessible;
eight are indirectly addressable. Two of the four timers
provide full service features, while the other two provide
delaytimerfeatures only. Serial Communication is provided
iORo
vss
A1
A2
A3
WR
CE
RO
°7
°6
°5
°4
°3
°2
°1
°0
by the USART, which is capable of either asynchronous or
synchronous operation, optional sync word recognition and
stripping, and programmable DMA control handshake lines.
Eight bi-directionall/O lines provide parallel I/O capability
and individually programmable interrupt capability. The
interrupt structure of the device is fully programmable for all
interrupts, provides for interrupt vector generation,
conforms to the Z80 daisy chain interrupt priority scheme,
and supports automatic end of interrupt functions for the
Z80.
VII-75
II
SIGNAL NAME
DESCRIPTION
Vss
Ground
+5 volts (± 5 percent)
Chip Enable (Input active low)
Read Enable (Input, active low)
Write Enable (Input, active low)
Address Inputs. Used to address one of the internal registers during a read or write
operation
Data Bus (bi-directional)
Device Reset (Input, active low). When activated, all internal registers (except for Timer or
USART Data registers) will be cleared, all timers stopped, USART turned off, all
interruptsdisabled and all pending interrupts cleared, and all 110 lines placed in tri-state
input mode.
General purpose I/O and interrupt lines
Interrupt Request (Output, active low, open drain)
Input/Output Request from ZOO-CPU (input, active low). The 10RQ signal is used in
conjunction with M1 to signal the MK3801 that the CPU is acknowledging its interrupt.
Interrupt Enable In, active High
Interrupt Enable Out, active High
Serial Output
Serial Input
Receiver Clock Input
Transmit Clock Input
Timer Outputs
Timer Clock Input
Z80 Machine Cycle One (Input, active low)
~c
RD
WR
Ao- A 3
Do-Dz
RESET
~
INT
10RQ
lEI
lEO
SO
SI
RC
TC
TAO-TOO
TCLK
M1
PIN DESCRIPTION
Figure 1 illustrates the pinout of the MK3oo1. The functions
of these individual pins are described above.
INTERNAL ORGANIZATION
Figure 2 illustrates the MK3801 internal organization,
which supports the full set of timing, communications,
parallel 1/0, and interrupt processing functions available in
the device.
CPU BUS 1/0
The CPU BUS 1/0 provides the means of communications
between the system and the MK3801. Data, Status, and
Control Registers in the MK3801 are accessed by the bus in
order to establish device parameters, assert control, and
transfer status and data between the system and the
MK3801.
Each register in the MK3801 is addressed over the address
bus in conjunction with Chip Enable (CE), while data is
transferred over the eight bit Data bus under control of Read
(RD) and Write (WR) signals.
both CE and RD active; thus the read operation will begin
when the later of these two signals goes active and will end
when the first signal goes inactive. The address bus must be
stable prior to the start of the operation and must remain
stable until the end ofthe operation. Unless a read operation
or an interrupt acknowledge cycle is in progress, the data
bus (Do-Dz) will remain in the tri-state condition.
To write a register, both CE and WR must be active. The
address must be stable prior to the start of the operation and
must remain stable until the end of the operation. The data
must be stable prior to the end of the operation and must
remain stable until the end of the operation. The data
presented on the buswill be latched into the register shortly
after either \.iiiR or CE goes inactive.
INTERNAL REGISTERS
There are 24 internal registers used to control the operation
of the STI. Sixteen of these registers are directly
addressable and accessible. Eight registers are indirectly
addressable via the Pointer IVector Register and accessible
via the Indirect Data Register.
DIRECTLY ADDRESSABLE REGISTERS
REGISTER ACCESSES
All register accesses are independent of any system clock.
To read a register, both ~ and RD must be active. The
internal read control signal is essentially the combination of
The Directly Addressable Registers are accessed by placing
the address of the desired register on the address lines
(Ao-A3) during a write or read cycle. Figure 3 lists the
Directly Addressable Registers.
VII-76
INTERNAL ORGANIZATION
Figure 2
l
TCLK
INTERNAL CONTROL
LOGIC
J
I
DATA 18)
.....
-
AD DR 14)
RD
-
TIMERS
C&D
TCO
I
TDO
j
t
~ TAO
TIMERS
A&B
r-C
P
U
f----- TBO
B
U
5
51
RC
I
/
U5ART
0
50
-
TC
J
I
INTERRUPT
CONTROL
r
-
lEI
lEO
DIRECTLY ACCESSIBLE REGISTERS
Figure 3
ADDRESS
ABBREVIATION
REGISTER NAME
0
lOR
1
GPIP
General Purpose I/O-Interrupt
2
IPRB
Interrupt Pending Register B
3
IPRA
Interrupt Pending Register A
4
ISRB
Interrupt in-Service Register B
5
ISRA
Interrupt in-Service Register A
6
IMRB
Interrupt Mask Register B
7
IMRA
Interrupt Mask Register A
8
PVR
9
TABCR
Indirect Data Register
Pointer IVector Register
Timers A and B Control Register
VII-77
GENERAL
PURPOSE
I/O ·INTRPT
I
III
DIRECTLY ACCESSIBLE REGISTERS (Continued)
Figure 3
ADDRESS
ABBREVIATION
A
TBDR
Timer B Data Register
B
TADR
Timer A Data Register
C
REGISTER NAME
UCR
USART Control Register
D
RSR
Receiver Status Register
E
TSR
Transmitter Status Register
UDR
USART Data Register
,
F
,
INDIRECTLY ADDRESS~El~,~,',REGISTERS
Figure 4
INDIRECT ADDRESS
",,"
"
"
'ABBREVIATION
REGISTER NAME
'>"
a
1
2
3
4
5
6
7
SCR
TDDR
TCDR
AER
IERB
IERA
DDR
TCDCR
Sync Character Register
Timer D Data Register
Timer C Data Register
Active Edge Register
Interrupt Enable Register B
Interrupt Enable Register A
Data Direction Register
Timers C and D Control Reqister
INDIRECTLY ADDRESSABLE REGISTERS
Indirectly Addressable Regi~te;:s'are addressed by placing
the indirect address in bits IAQ-IA2 of the Pointer/Vector
Register, as defined in Fig(jr!,!S.'Dat~ may be written to or
read from the register indicat~d' by'these Indirect Register
Address bits by a write or read access of the Indirect Data
Register (selected when Ao-A3 are all zero). The indirect
address bits of the Pointer/Vector Register will remain
unchanged after an indirect access. Repeated accesses of
the Indirect Data Register will access the same indirect
register as long as the indirect address in the
Pointer/Vector Register remains unchanged. The Indirectly
Addressable Registers are listed in Figure 4.
INTERRUPT VECTOR DEFINITION
Each individual function in theMK3801 is provided with a
unique interrupt vector th -- P5-7
P1-0 --
STROBE
EXTINT
RESET
TEST
XTL1,XTL2
VCC' GND
DESCRIPTION
1/0 PortO
1/0 Port 1
110 Port 4
1/0 Port 5
Ready Strobe
External Interrupt
External Reset
Test Line
Time Base
Power Supply Lines
TYPE
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Output
Input
Input
Input
Input
Input
STROBE is a ready strobe associated with 1/0 Port 4. This
pin, which is normally high, provides a single low pulse after
valid data is present on the P4-0--P4-7 pins during an
output instruction.
EXT INT is the external interrupt input. Its active state is
software programmable. This input is also used in
conjunction with the timer for pulse width measurement
and event counting.
XTL 1 and XTL 2 are the time base inputs to which a crystal,
LC network, RC network, or an external single-phase clock
may be connected. The time base network must be
specified when ordering a mask ROM MK3870. The
MK38P70 will operate with any of the four configurations.
TEST is an input, used only in testing the MK3870. For
normal circuit function this pin may be left unconnected, but
VIII-4
it is recommended that TEST be grounded.
architecture is common to all members of the 3870 family.
All 3870 devices are instruction set compatible and differ
only in amount and type of ROM, RAM, and 1/0. The unique
features of the MK3870 are discussed in the following
sections. The user is referred to the 3870 FamilyTechnical
Manual for a thorough discussion of the architecture,
instruction set, and other features which are common to all
3870 family devices.
Vee is the power supply input (single +5v).
MK3870 ARCHITECTURE
The basic functional elements ofthe MK3870 are shown in
Figure 1. A programming model is shown in Figure 2. The
MK3870 PROGRAMMABLE REGISTERS. PORTS.
AND MEMORY MAP
Figure 2
CPU REGISTERS
I 0 PORTS
BI;'\IARV
TIMER
ACCUMULATOR
PORT 7
A
SCAATCHPAD MEMOAY
SCRATCHPAO
OEC
R
7....-8 81T5----. 0
HEX
DC'
o
O
I
INTERRUPT
CONTROL PORT
STATUS
REGISTER
(WI
POAT6
H{
I~I+I+I
I 0 PORTS
I~
I,su
PORT'
'0
A
au
"
,.
8
al
'5
Hl
KU
'2
'3
Kl
§
a
INDIRECT
SCRATCHPAD
ADDRESS REGISTER
PORT4
I
a{
•
PARAllEL
I
K{
I 0 Z C 5
N V E A I
T E A A G
A A o A N
C
Y
N l
T 0
A W
l
4...--5 81T5- . .
J
HU
6'
62
63
C
0
E
"
'2
'3
,.
'4
'6
'7
30
3E
3F
7.
76
77
7..-8 BITS'" 0
ISlj
32·
0
....-6 8IT5·-.
POATO
MAIN ""EMORY
7......-8 BITS--. 0
PROGRAM
COUNTER
PO
87
....--- 12 BITS
~
STACK
REGISTER
11
ROM
87
. . . . - 12 BITS--..
DATA
COUNTER
locu OF
11
Dell
87
0
'-''lBITS~
I
OCI U
DC'
I
RAM
MKl870/'2
MKl870/22
MKl870/32
MK3870/42
AUX DATA
COUNTER
11
OEC
HEX
0
0
1023
'02'
DF
MK3870/10
4---UK3870/12
IFE
'047
7FF
ROM TO'
MK3870/ZQ
....-- MKal7Q/21
3070
3071
....
,
I
11
Delli
87
V/II-5
~ ....
~
{ii
7....-8 11T8-" 0
,
3F1
ME
.B•
• 030
4031
faF
403.
4033
F 0
F'
....
FFE
FFF
. . .4
ROM TOP
ROM TOP
+-:~:::~:~
ROMTOP
<4-MK3170/42
ROMTOP
~MK3'70/40
MK3870 MAIN MEMORY
SIZES AND TYPES BY SLASH NUMBERS
Figure 3
\ RAM
I
Hex Dec
I
~
I
I
I
I
I
RAM
RAM
. / FFF 4095
....... FCC) 4032
I
I
GJ~
3870/10 3870/12
RAM
COO 3072
BFF 3071
I
800 2043
7FF 2047
I
I
ROM
64 bytes
executable
FBF 4031
I
ROM
>
400 1024
3FF 1023
2K
2K
3K
3K
4K
4K
ROM
ROM
ROM
ROM
ROM
ROM
3870/20 3870/22
3870/30
00000000
3870/32 3870/40 3870/42
~~"""""--"----------~v~"------"----"""------'
All devices contain 64 bytes of scratchpad RAM.
NOTE: Data derived from addressing any locations other than
those within a part's specified ROM space or RAM space
(if any) are not tested nor are the data guaranteed. Users
should refrain from entering this area of the memory
map.
S cratch pad
RAM Size
(Decimal)
Address
Register Size
(PO. P. DC. DC1)
ROM
Size
(Decimal)
Executable
RAM Size
MK3870/10
64 bytes
12 bits
1024 bytes
o bytes
MK3870/12
64 bytes
12 bits
1024 bytes
64 bytes
MK3870/20*
64 bytes
12 bits
2048 bytes
o bytes
MK3870122
64 bytes
12 bits
2048 bytes
64 bytes
MK3870/30
64 bytes
12 bits
3072 bytes
o bytes
MK3870/32
64 bytes
12 bits
3072 bytes
64 bytes
MK3870/40
64 bytes
12 bits
4096 bytes
o bytes
MK3870/42
64 bytes
12 bits
4032 bytes
64 bytes
Device
*The MK3870/20 is equivalentto the original 3870 device in memory size; however, the original 3870 had an 11-bit
Address Register. The original 3870 with 11-bit Address Register is available where required. Consult the section
describing ROM Code Ordering Information for additional information.
VIII-6
1/0 PIN CONCEPTUAL DIAGRAM WITH OUTPUT
BUFFER OPTIONS
Figure 4
OUTPUT
BUFFER
PORT
z0
1/0
PIN
i=
«
a:
:J
0
ii:
Z
0
u
a:
0
~
a:
0
0.
0
«w
a:
Q
~
a:
0
0.
0
«
0
....I
0W
a:
~
CII
:J
III
«~
«
0
11.-:
"
vcc
OUTPUT BUFFER OPTIONS
(MASK PROGRAMMABLE)
II
MOR
6KllTYP.
(1\:~ ;:~
",i:.:laO)
STANDARD
OUTPUT
OPEN DRAIN
OUTPUT
'J
DIRECT DRIVE
OUTPUT
~\('r
Ports 0 and 1 are Standard Output type only.
I'! :. \Ot
Ports 4 and 5 may both be any of the three output options (mask programmable bit by bit)
The STROBE output is always configur~l'J~t~r to a Direct Drive Output except that it is capable of driving 3 TTL loads.
REffi and EXT INT may have standard 6Kll (typical) pull-up or may have no pull-up. (mask programmable).
--
" '{u
~t:~(H'
RESET and EXT INT do not haw internal pull up on the MK38P70.
-:";,- :1;).1"\
.\l '·~ioj
VIII-7
MK3870 MAIN MEMORY
located directly on top of the package. A number of standard
EPROMs may be plugged into this socket.
There are four address registers used to access main
memory. These are the Program Counter (PO), the Stack
Register (P), the Data Counter (DC), and the Auxiliary Data
Counter (DC1). The Program Counter is used to address
instructions or immediate operands. The Stack Register is
used to save the contents ofthe Program Counter during an
interrupt or subroutine call. Thus, the Stack Register
contains the return address at which processing is to
resume upon completion of the subroutine or interrupt
routine. The Data Counter is used to address data tables.
This register is auto-incrementing. Of the two data
counters, only Data Counter (DC), can access the ROM.
However, the XDC instruction allows the Data Counter and
Auxiliary Data Counter to be exchanged.
The graph in Figure 3 shows the amounts of ROM and
executable RAM for every available slash number in the
MK3870 pin configuration.
EXECUTABLE RAM
The MK38P70 can act as an emulator for the purpose of
verification of user code prior to the ordering of mask ROM
MK3870 devices. Thus, the MK38P70 eliminates the need
foremulator board products. In addition, several MK38P70s
can be used in prototype systems in order to test design
concepts in field service before committing to high-volume
production with mask ROM MK3870s. The compact size of
the MK38P70/EPROM combination allows the packaging
of such prototype systems to be the same as that used in
production. Finally, in low-volume applications, the
MK38P70 can be used as the actual production device.
Most of the material which has been presented for the
MK3870 in this document applies to the MK38P70. This
includes the description of the pin configuration,
architecture, programming model, and 1/0 ports. Additional
information is presented in the following sections.
MK38P70 MAIN MEMORY
The upper bytes of the address space in some of the
MK3870 devices are RAM memory. As with the ROM
memory, the RAM may be addressed by the PO and the DC
address registers. The executable RAM may be addressed
by all MK3870 instructions which address Main Memory.
Additionally, the MK3870 may execute an instruction
sequence which resides in the executable RAM. Note this
cannot be done with the scratchpad RAM memory, which is
the reason the term "executable RAM" is given to this
additional memory.
1/0 PORTS
The MK3870 provides four, 8 bit bidirectionallnputlOutput
ports. These are ports 0, 1, 4, 5. In addition, the Interrupt
Control Port is addressed as Port 6 and the binary timer is
addressed as Port 7. The programming of Ports 6 and 7 and
the bidirectional 1/0 pin are covered in the 3870 Family
Technical Manual. The schematic of an 1/0 pin and
available output drive options are shown in Figure 4.
An output ready strobe is associated with Port 4. This flag
may be used to signal a peripheral device that the MK3870
has just completed an output of new data to Port 4. The
strobe provides a single low pulse shortly after the output
operation is completely finished, so either edge may be used
to signal the peripheral. STROBE may also be used as an
input strobe to Port 4 after completing the input operation.
MK38P70 GENERAL DESCRIPTION
The MK38P70 is the EPROM version of the MK3870. It
retains an identical pinout with the MK3870, which is
documented in the section of this data sheet entitled
"FUNCTIONAL PIN DESCRIPTION". The MK38P70 is
housed in two packages which incorporate a 28-pin socket
There are two basic versions of the MK38P70. These are
the 97400 series and the 97500 series. The 97400 series
parts have twelve bit address capability thus a total 4K
memory map like the MK3870 ROM devices. The 97500
series has 16 bit address capability.
As can be seen from Figure 6, both the 97400 series and the
97500 series contain on-chip RAM in the upper portion of
their memory maps and no on-chip ROM. Instead of on-chip
ROM, address and data lines are brought out to the 28 pin
socket located directly on top of the 40 pin package so that
external memory devices (principally EPROMs) are
addressed.
By using an external EPROM, the 38P70 may be used to
emulate the 3870 ROM devices. The 97400 series can
directly emulate the following devices.
MK3870/10
MK3870120
MK3870122
MK3870/30
MK3870/42
The MK3807/40 cannot be emulated exactly by the 97400
series because the 97400 devices have the 64 bytes of
RAM in the upper memory map while the 3870/40
provides ROM memory in this address space.
Besides the difference in the size of the address registers,
97500 series can also emulate many of the 3870 ROM
devices. This difference in address capability should not
cause any functional difference as long as normal
programming practice is used. That is, as long as address
roll-over or automatic truncation is not used. One such
usage would be an end around branch (branching forward
VIII-8
MK38P70 BLOCK DIAGRAM
Figure 5
XTL1
EXTINT
XTL2
EXTERNAL
PROM
Ej
MEMORY ADDRESS BUS
4xB
EXECUTABLE
RAM
MAIN
CONTROL
LOGIC
RESULT BUS
TEST
I/O (8)
1/0 (B)
1/0 (8)
1/0 (8)STROBE
RESET
II
MK38P70 MAIN MEMORY MAP
HEX
Figure 6
~ -~
__
FFBF
DEC
65535
RAM
65472 _~._ _ _-'
65471
I
I
I
I
I
I
I
..L
.L
'T'
'T'
I
I
I
I
I
RAM
I
_
-OFFF
- - --OFCO
----.
••
4 0 9 5 . EXTERNAL
4 0 3 2 . MEMORY
• - ---oFBF - - ---:w31-
•
••
EXTERNAL.•
MEMORY:
•••
'--____---':
~ __
MK97400
SERIES
0000
_
'--_ _--'
MK97500
SERIES
SCRATCHPAD
RAM SIZE
(DECIMAL)
ADDRESS
REGISTER
SIZE
EXTERNALLY
ADDRESSABLE
MEMORY
SIZE
INTERNAL
EXECUTABLE
RAM
SIZE
97400 Series
64 bytes
12 bits
4032 bytes
64 bytes
97500 Series
64 bytes
16 bits
65472 bytes
64 bytes
MK38P70
TYPE
MK38P70 devices have no internal ROM memory.
VIII-9
at upper memory to get to lower memory). Another case
would be in using automatic truncation of data loaded into
the 12 bit address registers on the ROM devices. For
example, to access some particular location (03FF hex for
example) via the data counter, one could load that address
into DC using the DCI instruction. The instruction
DCI'73FF
would cause 3FF to be loaded into the DC of the 3870 ROM
device because the upper bits of the DC (bits 12-15) do not
exist. If that instruction was followed by the LM instruction,
the data stored at location 3FF would be obtained. The
97500 series devices would not truncate the 73FF address
to 3FF. As previously stated, this type of programming is
generally not done and thus the 97500 devices can be used
to emulate the following devices directly.
MK3870/10
MK3870/20
MK3870/30
MK3870/4O
The 97500 series can also be used to emulate the
remainder of the 3870 devices as long as one accounts for
the difference in the location of the RAM memory. In the
97500 devices, RAM is located at FFCO through FFFF.
While in 3870 devices this RAM (when it exists) is located at
OFCO through OFFF. When this minor difference is
accounted for, the 97500 series will also emulate the
following devices.
like the 38P70. Thus a few variations are offered which still
give some flexibility to the designer. The available I/O
options are also shown in Figure 7.
28 PIN SOCKET SIGNALS
The 40 package pins are the identical signals that are
provided with the MK3870 ROM devices. In addition to
these 40 inputs and outputs, various other signals are
implemented on the 38P70 die which are available for
connection to the top socket. Depending upon the particular
version, some subset of these signals are connected to the
28 pin socket. These signals are described below.
AO - A" (97400 Series)
Ao - A'5 (97600 Series)
These are the address buses. They are always outputs and a
new address will appear on this bus during each machine
cycle. Normally this is the address of op-codes or operands,
but there are ~achine cycles wherein no op-code or
operand is reqUired by the CPU. During these cycles, an
address is still JSiovided but the data that may be read from
that address is l:1'ot used.
"
Do - D7 (97400 and .97600 Series)
. .'
,"
~
This is the bi-directional data bus for the external memory.
Normally these, lines:are high impedance inputs. During
op-code or op~rand .reads, they receive data from the
external memory and conduct it onto the internal 38P70
data bus. During those cycles wherein the operation is
MK3870/22
strictly internal to the 38P70, they remain hi-z inputs. Data
MK3870/42
may be presel1ted to the 38P70 by an external memory
device but it isnbt conducted onto the internal data bus. This
MK38P70 EPROM SOCKET
includes machine cycles wherein op-codes or operands are
,aad from the internal executable RAM. During the operand
A 28 pin socket is located on top of the 40 pin package.
write machine cycle that occurs in the ST (store) instruction,
When 24 pin memories are used, they are inserted so that
they become push-pull outputs to conduct data to be written
pin 1 of the memory device is plugged into pin 3 of the
out to the external memory. However, if data is written to
socket (the 24 pin memory is lower justified in the 28 pin
the internal executable RAM, tl:1is transaction is strictly
socket).
internal and thus the data bus lines remain in their hi-z
state. It, therefore, depends upon the address as to whether
A 24 pin top socket was used so that the same package
this bus becomes an active output bus or remains high
could be used for all 38P70 devices but could accommodate
impedance. If the address of the operand is not within the
both 24 pin and 28 pin. Due to pin-out differences between
internal executable RAM space when aST instruction is
various common memory devices, several different
executed, Do - 0 7 will become active outputs at the approversions of the MK38P70 are provided with differing signals
priate time, or ~Ise they will remain in the hi-z state. The
connected to particular pins on the 28 pin socket. Figure 7
97400 devices do not provide a RD (read) control signal, nor
shows the various options available.
is this signal pr(ivided on all versions of the 97500 series.
Thus if a ST is eiecuted with the operand address being that
of external memory, that memory may access data and
MK38P70 I/O PORTS
drive it onto Do - 0 7 while the 38P70 isalso driving data onto
For custom 3870 ROM codes, the user is given a bit by bit
Do -07 and a bus conflict will result. This condition should
selection of I/O options on I/O ports 4 and 6. Additionally, . be avoided; thus the user should note whether or not his
the user has the option of selecting whether or not either
external memory will drive Do - 0 7 in this event. If it will
RESET or EXT INT has an internal pull-up resistor. This
drive Do - 0 7 , an ST with that operand address should be
flexibility allows about 172 million possible variations in I/O
avoided. In general, one would not normally execute a write
port and RESET and EXT INTconfigurations. Obviously, it is
to a memory location where there is ROM or EPROM
not practical to offer this variety in an Uoffthe shelf product
memory instead of RAM. However, some 3870 users have
u
VIII-10
DEVICE
MK97400
PORT4
1/0 TYPE
PORT 5
110 TYPE
TTL
TTL
::!'!3i:
=
~
C Co)
TOP 28 PIN
SOCKET WIRING
VERSION
SUPPORTS THESE
MEMORY DEVICES
2716,2516,2532,2758
MK34000ROM
A
Cil CD
~~
~
::II
(I)
MK97410
Open
Drain
Open
Drain
2716,2516,2532,2758
MK34000ROM
A
MK97500
TTL
Open
Drain
2716,2516,2532,2758
MK34000 ROM
B
MK97501
TTL
Open
Drain
2764, 2732, MK37000 ROM
MK34000 ROM
C
MK97503
TTL
Open
Drain
Use connector from
28 pin socket to memory bus
D
o
2
(I)
~
......
Vee .1
Vss . 2
A7 .3(1)
As • 4(2)
As .5(3)
A4 .6(4)
A3 .7(5)
A2 .8(6)
A, .9(7)
Ao .10(8)
Do • 11 (9)
0, .12(10)
O2 .13(11)
Vss .14(12)
28 •
27 •
(24)26.
(23) 25 •
(22) 24.
(21) 23 •
(20) 22.
(19) 21 •
(18) 20.
(17) 19 •
(16) 18 •
(15) 17 •
(14) 16 •
(13) 15 •
VERSION A
Vee
Vee
Vee
As
A9
Vee
Vss
A,o
A11
07
Os
Os
04
03
••
••
••
•••
••
O2 •
•
NC
•
NC
.WR
A'2
A7
As
As
A4
A3
A2
A,
Ao
Do
Vss
•
VERSION
B
03
Vss
•
Vee
As
A9
•
•
•
0,
A,o
A"
0Os7
Os
04
A'2
A7
As
As
A4
A3
A2
A,
Ao
Do
0,
'0 2
•
•
~e
•
•
R
••
•
•
Vee
II
••
•
•••
••
•••
•••
••
•
~
•
•
As
A9
Vee
:~
.~
•
MREQ
•
•
•
•
VERSION
C
•
07
Os
Os
04
03
A'4
A'2
A7
As
As
A4
A3
A2
A,
Ao
Do
0,
O2
A,s
••
••
••
•
•••
••
•
•
FE'fC'H
••• FA
A'3
• AsA9
•• ~
••• ~
0
••• OsOs
0
•• 0
RD
A
7
4
3
VERSION
°
found the ST instruction useful even in devices like the
3870/20 which have no executable RAM. In this case it
causes the data counter to increment (to perhaps totalize
some event) but otherwise does nothing as one cannot
write the internal ROM. No internal conflicts will occur if
one attempts to write a 3870 ROM location. Most 97500
versions place a RD (read, active low) signal on the top
socket pin which matches the OE (output enable, active low)
input on most memories. Since RD will remain high during
an operand write, the external memory would not have its
data outputs enabled and no conflict will occur.
remain high. It will also remain high during an operand
write cycle.
WR (97500 Series Only)
This is the active low write control output. It is normally high
but will go low then return high during an operand write if
the address is not that of internal executable RAM.
FETCH (97500 Series Only)
This is the active low fetch status signal which signals that
an op-code fetch occurred during that cycle. It is generated
for use of the 97500 as a development system component.
MREQ (97500 Series Only)
This is an active low output which occurs during each
machine cycle. It goes high at the start of each cycle then
goes low for the remainder of the cycle.
It will go low during all op-code fetches whether from
internal or external memory.
RD (97500 Series Only)
38P70 EXTERNAL MEMORY TIMING
This is the active low read output which goes high at the
start of each cycle then goes low if data (op-codes or
operands) are to be read from external memory. During
cycles wherein a strictly internal operation occurs, RD will
The following Figures show the relative waveforms for the
signals used to interface with external memory. The timing
parameters are labeled. Their values are given in the A.C.
Characteristics section of the Electrical Specifications.
97400 SERIES TIMING
Read Cycle
Figure 8
PREVIOUS ADDRESS
CURRENT ADDR VALID
DATA VALID
~
Actively driven by 38P70 but not necessarily in
valid state.
-)
Not actively driven by the 38P70. May be
actively driven by external memory but does
not have to be in a valid state or may be placed
in hi-z state by external memory.
VIII-12
97500 SERIES TIMING
Figure 9
~IC-
IC____OP.CODE FETCH
~
MREQJ
I
I--T.m~
RDJ
r--
I
.
OPERAND READ
-I
I
1_-
1_ _ _ _ _ _
T••
,~
T...
OPERAND READ
A. OP·CODE A~~AL MEMORY
FROM EXTE
VIII-13
III
97500 SERIES TIMING (Continued)
Figure 9
1-1
00 - - - OP-COOE
MREQ
J
FETCH------<.~I.o------ OPERAND WRITE -------.~I
.~_--.----Jt
L---_I
B. OPERAND WRITE TO EXTERNAL
MEMORY
VIII-14
97500 SERIES TIMING (Continued)
Figure 9
CD
iffi
Do· 0'6
ru
CD
®
u
u
=-=-><=Xlf---~>a)f-------------7xy~C. EXAMPLES OF VARIOUS CYCLES
tct>
Internal ct> clock
210
210
WRITE
tw
Internal WRITE Clock period
4tct>
6tct>
4tct>
6tct>
I/O
~I/O
Output delay from internal
WRITE clock
0
tsl/O
Input setup time to internal
WRITE clock
1000
tl/O-s
Output valid to STROBE delay
3tct>
-1000
3tct>
+250
3tct>
-1200
3tct>
+300
ns
I/O load =
50pF + 1 TTL load
tsL
STROBE low time
8tct>
-250
12tct>
+250
8tct>
-300
12tct>
+300
ns
STROBE load=
50pF + 3TTL loads
tRH
RESET hold time, low
6t
+750
STROBE
RESET
tRPOC RESET hold time, low for power
clear
EXTINT
tEH
EXT INT hold time in active and
inactive state
power
supply
rise
1000
1200
0
1200
6t
+1000
4MHz-2MHz
Short Cycle
Long Cycle
ns
50pF plus
one TTL load
ns
ns
power
supply
nse
1:...
time -01
time
6t
+750
2t
6t
+1000
2t
VIII-20
UNIT NOTES
i
ms
ns
ns
To trigger
interrugt
To trigger timer
AC CHARACTERISTICS FOR MK38P70 Signals brought to top 28 pin socket.
TA' Vee within specified operating range.
I/O Power Dissipation::; 100 mW (Note 2)
97400 Series (See Note 3)
-00. -05
SYMBOL
PARAMETER
MIN
taas
External memory required
access time from Ao-A,l stable
3t
-850
MAX
-10. -15
MIN
MAX
3t
-850
UNIT CONDITION
ns
CLAo-A"
50 pF
=
97500 Series (See Note 3)
-00. -05
-10. -15
SIGNAL
SYMBOL
PARAMETER
MIN
MREO
Thm
MREO high time
2t
-100
2t
-100
ns
Load = 50 pF + 1
TIL load
RD
Thr
RD high time
2t
-100
2t
-100
ns
Load = 50 pF + 1
TIL load
WR
Tw
WR low from
MREOlow
3t
-200
3t
+100
3t
-200
3t
+100
ns
Load = 50 pF + 1
TIL load
Twl
WR low time
t
-100
t
+100
t
-100
t
+100
ns
Tit
FETCH stable prior
to rising MREO
650
650
650
650
ns
Load = 50 pF + 1
TIL Load
Tfh
FETCH hold time
after MREO high
Ta
Address stable prior
to RD or MREO falling
Tah
Address hold time after
MREO, RD, or WR high
Taas
FETCH
Ao - A 15
Do - D7
MAX
MIN
MAX UNITS CONDITION
20
20
ns
Load = 20 pF
t
-400
t
-400
ns
Load = 50 pF + 1
TIL load
15
15
ns
Load = 20 pF
External memory required
access time from
3t
-850
3t
-850
ns
Tmas
External memory required
access time from MREO
or RD low
2t
-450
2t
-450
ns
Tdhr
Required data hold time
after MREO rising
0
0
ns
Tda
Data bus active after
MREO or RD high
t
t
Tdw
Data stable prior to WR
falling
5t
-2250
5t
-2250
ns
Load = 50 pF + 1
TIL load
Tdhr
Data hold after WR high
15
15
ns
Load = 20 pF
Tdfw
Data ~Iay to float
after MR
rising
200
VIII-21
200
ns
II
CAPACITANCE
TA = 25°C
All Part Numbers
SYM
PARAMETER
CIN
Input capacitance
CXTL
Input capacitance; XTL 1, XTL2
MIN
MAX
UNIT NOTES
10
pF
23.5
29.5
pF
-00, -05
-10, -15
unmeasured
pins grounded
DC CHARACTERISTICS
TA- Vee within specified operating range
I/O power dissipation:::; 100 mW (Note 2)
SYMBOL
PARAMETER
lee
Average Power Supply
Current
MIN
VIII-22
MAX
MIN
MAX
UNIT DEVICE
85
110
. mA
MK3870/10
Outputs Open
94
125
mA
MK3870/12
Outputs Open
85
110
mA
MK3870/20
Outputs Open
94
125
mA
MK3870122
Outputs Open
100
130
mA
MK3870/30
Outputs Open
100
130
mA
MK3870/32
Outputs Open
100
130
mA
MK3870/40
Outputs Open
100
130
mA
MK3870/42
Outputs Open
125
150
mA
MK38P70/X2
No EPROM,
Outputs Open
DC CHARACTERISTICS (cont.)
-00, -05
SYMBOL
PARAMETER
Po
Power Dissipation
MIN
MAX
400
-10,-15
MIN
MAX
525
UNIT DEVICE
mW MK3870/10
Outputs Open
440
575
mW MK3870/12
Outputs Open
400
525
mW MK3870/20
Outputs Open
440
575
mW MK3870/22
Outputs Open
475
620
mW MK3870/30
Outputs Open
475
620
mW MK3870/32
Outputs Open
475
620
mW MK3870/40
Outputs Open
475
620
mW MK3870/42
Outputs Open
600
750
mW MK38P70/X2
No EPROM,
Outputs Open
VIII-23
DC CHARACTERISTICS (cont.)
TA, V CC within specified operating range, 1/0 power dissipation :s 1OOmW (Note 2)
-00,-05
-10,-15
SYM
PARAMETER
MIN
MAX
MIN
MAX
VIHEX
External Clock input high level
2.4
5.8
2.4
5.8
V
VILEX
External Clock input low level
-.3
.6
-.3
.6
V
IIHEX
External Clock input high current
100
130
JJA
IILEX
External Clock input low current
-100
-130
JJA
VILEX=VSS
VIHI/O
Input high level, 1/0 pins
VIHR
VIHEI
Input high level, RESET
Input high level. EXT INT
UNIT CONDITIONS
VIHEX=VCC
2.0
5.8
2.0
5.8
V
Standard pull-up
2.0
13.2
2.0
13.2
V
Open drain (1)
2.0
5.8
2.2
5.8
V
Standard pull-up
2.0
13.2
2.2
13.2
V
No Pull-up
2.0
5.8
2.2
5.8
V
2.0
13.2
2.2
13.2
V
Standard pull-up
No Pull-up
-.3
.8
-.3
.7
V
VIL
Input low level
IlL
Input low current, all pins with
standard pull-up resistor
-1.6
-1.9
mA
VIWO.4V
IL
Input leakage current, open drain
pins, and inputs with no pull-up resistor
+10
-5
+18
-8
JJA
JJA
VIW13.2V
VIN=O.OV
10H
Output high current pins with
standard pull-up resistor
10HDD
Output high current,
direct drive pins
-100
-89
JJA
VOW2.4V
-30
-25
JJA
VOW3.9V
-100
-1.5
-80
-1.3
JJA
mA
mA
VOW2.4V
VOW1.5V
VOWO.7V
VOH = 2.4V
-11
-8.5
10HS
STR08E Output High current
10L
10LS
(1 )
-300
-270
JJA
Output low current
1.8
1.65
mA VOL=0.4V
STROBE Output Low current
5.0
4.5
mA
VIII-24
VOL=0.4V
DC CHARACTERISTICS FOR MK38P70
Signals brought to top 25 pin socket
TA' Vee within specified range
I/O Power Dissipation :5100 mW (Note 2)
97400, 97600 Series
..,00, -06
SYMBOL
PARAMETER
V1H
V1L
-10, -16
MIN
MAX
MIN
MAX
Input high level (Do - 0,)
2.0
Vee
+.3
2.1
Vee
+.3
V
Input low level (Do - 0,)
Vss
.8
Vss
.7
V
±15
p.A
-.3
IL
Input Leakage (Do - 0,)
V OH
Output high level (a" outputs and
0 0 -0, in output mode)
VOL
Output low level (a" outputs and
0 0 -0, in output mode)
IOH
Output source current (a" outputs
,and 0 0 -0, in output mode)
IOL
Output sink current (a" outputs
and 0 0 -0, in output mode)
Ree
Package resistance from device
pin 40 to top socket Vee
pin(s)
Do - 0, in Hi-z
input mode
-.3
±10
2.4
2.4
.4
V
.4
V
-100
-90
p.A
1.8
1.65
mA VOL
n
Package resistance from device
pin 20 to top socket Vss pin(s)
Rss
UNIT CONDITION
VOH
= 2.4V
= .4V
n
n
Pin 28, 27, or 26
when Vee
Pin 1 if Vee
Pin 23 if Vee
n
n
Pin 14whenVss
Pin 2 or 22 when
Vss
Supply current available from
top socket Vee pin(s)
Icc
Supply current available from
top socket Vss pin(s)
Iss
-185
-185
mA
-20
-10
-20
-10
mA
mA
II pin 28 27, 26
whenVr.r.
Pin 1 ifVr.r.
Pin 23 if Vee
190
2
2
190
2
2
mA
mA
mA
Pin 14 if Vss
Pin 2 if V!,:!,:
Pin 22 ifVss
NOTES:
1.
iiESE'f and EXT INT have internal
Schmit triggers giving minimum .2 V
hysteresis.
2. Power dissipation for 1/0 pins is calcualted by I(VCC - VILI( IIILI ) = I(VCCVOH) (IIOH I) = I(VOH)(IOL)
3. AC timing for external memory signals on 38P70 8fe measured from either
the .8 or 2.0 volt points as applicable. High means at or above 2.0 volts. Low
means at or below.8 volts. Stable means high or low as appropriate. Rising
means signal is no longer below.8 volts. Falling means signal is no longer
above 2.0 volts. Hold times on outputs assume full rated load on reference
signal and 20 pf load on specified signal. For 97400 series, only applicable
specification is Taas as no other Signals are available to reference to other
than Ao-A".
TIMER AC CHARACTERISTICS
Definitions:
Error = Indicated time value - actual time value
tpsc
=t x Prescale Value
Interval Timer Mode:
Single interval error, free running (Note 3) _............................. _.. _. __ ....... __ .... ____ .. ____ ±6t
Cumulative interval error, free running (Note 3) ........ ___ .. _...... _.............. _' ................ _...... 0
VIII-25
II
Error between two Timer reads (Note 2) ....••••••..••••..•••••••.••••.•••.•..••••••••••...•.••..• ± (tpsc + t to - (tpsc + t to - (tpsc + 7t to -8t
Load Timer to stop Timer error (Note 1) .••.• , ..•..••.••••••••.•••••••.•••••..••.•••......•• + till to - (tpsc + 2t to -9t
Pulse Width Measurement Mode:
Measurement accuracy (Note 4) •••.••••.•.••••.••...••..••.••..••...•••.•••.•••.•....•• + till to -(tpsc + 2t
Event Counter Mode:
Minimum active time of EXT INT pin ....••..•••••.•••••.•..••••••.••••.•.••.•••...••.•.•••••.••.•..•.. 2t
Minimum inactive time of EXT INT pin ....•.••••.•....••..••••••.••.•.•••..••••••......•••.•••..•.•.... 2t
Note.:
1. All times which entail loading, starting. or stopping the Timer are referenced from the end of the last machine cycle of the OUT or OUTS instruction.
2. All times which entail reading the Timer are referenced from the end of the last machine cycle of the IN or INS instruction.
3. All times which entail the generation of an interrupt request are referenced from the stan of the machine cycle in which the appropriate interrupt request latch is
set. Additional time may elapse if the interrupt request occurs during a privileged or multicycle instruction,
4. Error may be cumulative if operation is repetitively performed.
AC TIMING DIAGRAM
Figure 16
External Clock
Internal Clock
1/0 Port Output
STROBE
RESET
EXTINT
=
ICPBIT]=OO ~H:=3(
ICPBIT2=1
.
'-----
Note: All AC measurements are referenced to V 1L max., V 1H min., VOL (.8v), or V OH (2.Ov).
VIII-26
INPUT/OUTPUT AC TIMING
Figure 17
INTERNAL
WRITE
CYCLE TIMING
~----~~--------~~I--------·----~~-----'+----'DEPENDSONINSTRUCTION
CLOCK
4MHz EXTERNAL
OPCODE
FETCHED
CLOCK
PORT PINS
A. INPUT ON PORT 4 OR 5
----.j-.------.r----- ~~~~~~~~~~NSTRUCTION
INTERNAL
WRITE
CLOCK
OUT OR
OUTS
OP CODE
FETCHED
PORT ADDR.
ON DATA
BUS
ACCUMULATOR
CONTENTS
ON DATA BUS
NEXT
OP CODE
FETCHED
PORT PINS
STAYS LOW
STROBF
(ACTIVE FOR PORT 4 ONLYI
FOR TWO WRITE
CYCLES
B. OUTPUT ON PORT 4 OR 5
tl/O-S
INTERNAL
WRITE
CLOCK
OUTS 0.1
FETCHED
ACC DATA
ON BUS
NEXT
OPCODE
FETCHED
PORT PINS
C. INPUT ON PORT 0 OR 1
D. OUTPUT ON PORT O. 1
VIII-27
II
STROBE SOURCE CAPABILITY
(TYPICAL AT Vee = 5 V, TA = 25°C)
Figure 18
-15
s
0
U
A
C
E
!
!
C
U
A
A
E
N
T
i
-10
I"'
......
i
...... r--.
-5
,
,
'" '"
M
A
,-t-
l'
I
I"'r-.,
,-..
.1
I
OUTPUT VOLT AGE
STROBE SINK CAPABILITY
(TYPICAL AT Vee = 5 V, TA = 25°C)
Figure 19
S
+100
I
n±--
++1-r- ++
~
+I
N
K
I
c
U
A
R
E
.......
I
+50
j,;'
N
!
t-r-c-,
M
A
1.1
I
,
1/
T
-
I
VI
I
I
I
1
OUTPUT VOLTAGE
STANDARD 1/0 PORT SOURCE CAPABILITY 1.5
(TYPICAL AT Vee = 5 V, TA = 25°C)
Figure 20
s
0
I~
u
A
C
E
,.....
-1.0
I'
C
u
1'-. ,....,
A
R
E
N
T
I'
-.5
r--.
M
A
,....,
I'
J"-.
!"o.
OUTPUT VOL T AGE
DIRECT DRIVE 1/0 PORT SOURCE CAPABILITY
(TYPICAL AT Vee = 5 V, TA = 25°C)
Figure 21
r-r
s
o
U
R
C
',-t-10
E
C
U
R
R
E
N
T
M
A
_._- -f--
-r-~
I"--
-5
r-;--- --
f--- -
l-
t-
'"
-- f-,'
-
i"' .... ~
rOUTPUT VOLTAGE
VIII-28
,
--t--- 1---
--
1/0 PORT SINK CAPABILITY
(TYPICAL AT Vee = 5 V. TA = 25°C)
Figure 22
t-
f-f- ""
100
I
"...
p(~
50
AStle
100
200
300
I..... to-.
400
CER4n;;c
.....
500
r-
to-.
1000
600
PDI/OMIIY
MAXIMUM OPERATING TEMPERATURE VS.
1/0 POWER DISSIPATION
Figure 23
<£0
S
I
N
+50
K
Z
+40
R
R
E
+30
N
T
M
,
+2 0
A
+1 0
I-'"
,
~
-
~
OUTPUT VOLT AGE
III
VIII-29
ORDERING INFORMATION
There are two types of part numbers for the 3870 family of
devices. The generic part number describes the. basic device
type, the amount of ROM and Executable RAM, the desired
package type, temperature range, and power supply
tolerance. For each customer specific code, additional
information defining I/O options and oscillator options will
be combined with the information described in the generic
part number to define a customer/code specific device
order number. Note: the specific device order number will
be used to differentiate between the MK3870/20 with
1 2-bit Address Registers and the original 3870 with 11 -bit
Address Register, as mentioned in an earlier section.
GENERIC PART NUMBER
An example of the generic part number is shown below.
1:-
MK 3870 12 2 .P-1 0
0= 5V± 10%
5= 5V±5%
S'POIY Tol,,,",,
Operating Temperature Range
~_.... Package
........---1~
0= O°C - +70°C
1 = -40·C - +85·C
type
P = Ceramic
N = Plastic
Executable RAM Designator
0= None
2 = 64 bytes
ROM Designator
'1 = 1K Bytes
2 = 2K bytes
3 = 3K Bytes
4 = 4K Bytes
Basic Device Type
An example of the generic part number for the EPROM
device is shown below.
MK38P70/02 R-05
DEVICE ORDER NUMBER
An example of the device order number is shown below.
MK 14007 N - 0 5
IT:
Powoc
S,,,,,,
T~".""
0=5V±10%
5 = 5V±5%
Operating Temperature Range
I - - - -__ Package
0= O·C - +70°C
1 = -40°C - +85°C
Types
P = Ceramic
N = Plastic
'-------Customer/Code Specific Number
The Customer/Code specific number defines the ROM bit
pattern, I/O configuration, oscillator type, and generic part
type to be used to satisfy the requirements of a particular
customer purchase order. For further information on the
ordering of mask ROM devices, the customer should refer to
the 3870 Family Technical Manual.
VIII-30
MOSTEl(.
MICROCOMPUTER COMPONENTS
3870 Single Chip Micro Family
MK2870
MK2870 FEATURES
o
MK2870
Figure 1
28 pin version of the industry standard MK3870 single
chip microcomputer
'0 Available with 1K or 2K bytes of mask programmable
ROM memory
o 64 bytes scratchpad RAM
o Available with additional 64 bytes executable RAM
o 20 bits TTL compatible 1/0
o Programmable binary timer
Interval timer mode
Pulse width measurement mode
Event counter mode
o External interrupt input
o Crystal, LC, RC, or external time base options
o Low power (275mW typ.)
o Single +5 volt supply
MK2870 PIN CONNECTIONS
Figure 2
GENERAL DESCRIPTION
The MK2870 is the 28 pin version of the industry standard
Mostek MK3870 single chip microcomputer. It is offered as
a low cost device which can be used in those applications
that do not require the entire 1/0 capability of the 40 pin
MK3870. The compact 28 pin package makes the MK2870
ideally suited for applications where PC board space is a
premium.
The MK2870can execute morethan 70 instructions, and is
completely software compatible with the rest of the devices'
in the 3870 family. The MK2870 features 1 K or 2K bytes of
ROM and optional additional executable RAM depending
on the specific part type designated by a slash number
suffix. The MK2870 also features 64 bytes of scratchpad
RAM, a programmable binary timer, and 20 bits of 1/0.
The programmable binary timer operates by itself in the
interval timer mode or in conjunction with the external
interrupt input in the pulse width measurement and the
event counter modes of operation. Two sources of vectored,
prioritized interrupt are provided with the binary timer and
VIII-31
28
REsET
XTL2
1
2
3
STROBE
4
25
P4-O
5
24
P4-1
6
23
P5-0
P4-2
7
22
P5-i
P4-3
8
P4-4
9
21
20
P5-3
P5-4
Vee
XTL1
P4-5
27
EXTINT
26
p;::f
P1-2
.1>1-3
P5-2
10
11
19
P4-6
18
P5-5
P4-7
12
17
P5-ii
PO-7
13
16
P5-7
GND
14
15
TEST
MK2870BLOCK DIAGRAM
Figure 3
MEMORY ADDRESS BUS
64x8
EXECUTA8L
RAM
MAIN
CONTROL
LOGIC
ROM
RESULT BUS
TEST
1/0(1)
liD (8)Si'ii'QiE
1/0(3)
the external interrupt input. The user has the option of
specifying one of four clock sources for the MK2870:
Crystal, LC, RC, or external clock. In addition, the user can
specify either a ±10% power supply tolerance or a ±5%
power supply tolerance.
PIN NAME
DESCRIPTION
TYPE
PO-7
P1-1 -- P1-3
P4-0 -- P4-7
P5-0 -- P5-7
STROBE
EXTINT
RESET
TEST
XTL 1,XTL2
Vee' GND
I/O Port 0 Bit 7
I/O Port 1 Bits 1-3
I/O Port 4
I/O Port 5
Ready Strobe
External Interrupt
External Reset
Test Line
Time Base
Power Supply
Lines
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Output
Input
Input
Input
Input
Input
liD (8)
STROBE is a ready strobe associated with I/O Port 4. This
pin, which is normally high, provides a single low pulse after
valid data is present on the P4-0--P4-7 pins during an
output instruction.
RESET may be used to externally reset the MK2870. When
pulled low the MK2870will reset. When then allowed to go
high the MK2870 will begin program execution at program
location H '000'.
EXT INT is the external interrupt input. Its active state is
software programmable. This input is also used in
conjunction with the timer for pulse width measurement
and event counting.
XTL 1 and XTL 2 are the time base inputs to which a crystal,
LC network, RC network, or an external single-phase clock
may be connected. The time base network must be
specified when ordering a mask ROM MK2870.
TEST is an input, used only in testing the MK2870. For
normal circuit functionality this pin may be left
unconnected, but it is recommended that TEST be
grounded.
FUNCTIONAL PIN DESCRIPTION
PO-7, P1-1--P1-3, P4-0--P4-7, and P5-0--P5-7 are 20 lines
which can be individually used as either TTL compatible
inputs or as latched outputs.
Vee is the power supply input (single +5 V).
VIII-32
instruction set. and other features which are common to all
2870 family devices.
MK2870 ARCHITECTURE
The basic functional elements ofthe MK2870 are shown in
Figure 3. A programming model is shown in Figure 4. The
architecture is common to all members of the 2870 family.
All 2870 devices are instruction set compatible and differ
only in amount and type of ROM and RAM. The unique
features of the MK2870 are discussed in the following
sections. The user is referred to the 3870 Family Technical
Manual for a thorough discussion of the architecture.
MK2870 MAIN MEMORY
There are four address registers used to access main
memory. These are the Program Counter (PO). the Stack
Register (P). the Data Counter (DC). and the Auxiliary Data
Counter (DC1). The Program Counter is used to address
instructions or immediate operands. The Stack Register is
MK2870 PROGRAMMABLE REGISTERS. PORTS.
AND MEMORY MAP
Figure 4
CPU REGISTfRS
I 0 PORTS
SCRATCHPAD MFMORY
BI:\IAAY
TIMER
ACCUMULATOR
A
PORT 7
7....--8 BITS·-. 0
7...-8
SCRATCHPAD
BITS~
DEC
HEX
O
°
HU
10
A
12
Hl
"
C
,.
0
15
H
0
OC1
INTERRUPT
CONTROL PORT
STATUS
REGISTER
iWI
PORT 6
7"'-8
BITS~
J
I~I+I+I
a
0
PARALLEL
I 0 PORTS
PORT 5
PORT 4
PORT 1
PORT
°
al
15
17
N l
T a
I
I
I
I
R
w
4"
5 BITS
.. 0
[,SU
'~ ISl
5
32
61
3D
75
62
3'
3'
76
77
63
INDIRECT
SCRATCHPAO
ADDRESS REGISTER
II
a
7 . 8 BITS __
I
0
~BITS-+-
MAIN
7 -+---8 BITS ...-. 0
MEMORY
PROGRAM
COUNTER
PO
I
"
87
'-128IT5_
ROM
STACK
REGISTEA
I
PU
Pl
11
87
I
~
~
0
....--128IT5'-'
NOTE: All 32 parallel 1/0
port pins are available in the
2870. However. only 20 of the
bits are connected to 110 pins.
Refer to the pin diagram for
complete definition.
16
N
OR
R
,
au
,.
Kl
l C S
N V E A I
T E R R G
R
C
12
13
KU
I
"
13
11
1022
1023
3"
3FF
2046
2047
7FE
7FF
I
DCI
I
HEX
I
I
DATA
COUNTER
DC
DEC
87
I
U
. . - 12 BITS--.
I
I
I
I
B
-{a
4032
4033
'CO
FCl
4094
4095
FFE
FFF
MK2870112
MK2870/22
AUX DATA
I
COUNTER
DCI U
11
DC1
I
Delli
87
.....-12BITS~
VIII-33
7 _ 8 8ITS----. 0
ROM TOP
. . . - - MK2870/10
MK2870/12
~
ROM TOP
MK2870/20
MK2870/22
MK2870 MAIN MEMORY
SIZES AND TYPES BY SLASH NUMBERS
Figure 5
Hex
~
~
I
Dec
./' FFF
"-
4095
FCO 4032
FBF 4031
>
64 bytes
executable
RAM
I
I
COO 3072
BFF 3071
I
I
I
BOO 2043
7FF 2047
I
~CJ
400 1024
3FF 1023
2K
2K
ROM
ROM
ROM
ROM
2870/10
2870/12
2870120
2870/22
00000000
V
,~------~,..--------~/
All devices contain 64 bytes of scratchpad RAM.
NOTE:
Data derived from addressing any locations other than
those within a part's specified ROM space or RAM space
(if any) is not tested nor is it guaranteed. Users should
refrain from entering this area of the memory map.
Device
Scratchpad
RAM Size
(Decimal)
Address
Register Size
(PO, P. DC. DC1 )
ROM
Size
(Decimal)
Executable
RAM Size
(Decimal)
MK2870/10
64 bytes
12 bits
1024 bytes
o bytes
MK2870/12
64 bytes
12 bits
1024 bytes
64 bytes
MK2870120
64 bytes
12 bits
2048 bytes
o bytes
MK2870122
64 bytes
12 bits
2048 bytes
64 bytes
NOTE:
The Address Register Size for the 2870120 is
11 bits. It will be changed to 12 bits at a later
date.
VIII-34
1/0 PIN CONCEPTUAL DIAGRAM WITH OUTPUT
BUFFER OPTIONS
Figure 6
OUTPUT
BUFFER
PORT
z0
i=
e:(
a::
::l
t!1
...:
Z
0
U
a::
0
1/0
PIN
....
....
0
0
a::
Il.
C
e:(
w
a::
a::
Il.
0
e:(
0
....
6w
a::
~
Vl
::l
co
e:(
....e:(
0
OUTPUT BUFFER OPTIONS
(MASK PROGRAMMABLE)
VCC
6K!!TYP
STANDARD
OUTPUT
OPEN DRAIN
OUTPUT
Ports 0 and 1 are Standard Output type only.
Ports 4 and 5 may both be any of the three output options (mask programmable bit by bit)
The "STRC5'8E output is always configured similar to a Direct Drive Output except that it is capable of driving 3 TIL loads.
RESET and EXT INT may have standard 6K
n (typical) pull·up or may have no pull· up (mask programmable).
When Direct Drive option is selected, it should be used as an Output only (not as an input).
VIII-35
DIRECT DRIVE
OUTPUT
used to save the contents of the Program Counter during an
interrupt or subroutine call. Thus, the Stack Register
contains the return address at which processing is to
resume upon completion of the subroutine or interrupt
routine. The Data Counter is used to address data tables.
This register is auto-incrementing. Of the two data
counters, only Data Counter (DC), can access the ROM.
However, the SOC instruction allows the Data Counter and
Auxiliary Data Counter to be exchanged.
The graph in Figure 5 shows the amounts of ROM and
executable RAM for every available slash number in the
MK2870 pin configuration.
1) Crystal
2) LC Network
. 3) RC Network
4) External Clock
The type of network which is to be used with the mask ROM
MK2870 must be specified at the time when mask ROM
devices are ordered.
The specifications for the four configurations are given in
the following text. There is an internal capacitor between
XTL 1 and GND and an internal capacitor between XTL 2
and GND. Thus, external capacitors are not necessarily
required. In all clock modes the external time base
frequency is divided by two to form the internal PHI clock.
EXECUTABLE RAM
CRYSTAL SELECTION
The upper bytes of the address space in some of the
MK2870 devices is RAM memory. As with the ROM
memory, the RAM may be addressed by the PO and the DC
address registers. The executable RAM may be addressed
by all MK2870 instructions which address Main Memory.
Additionally, the MK2870 may execute an instruction
sequence which resides in the executable RAM. Note this
cannot be done with the scratchpad RAM memory, which is
the reason the term "executable RAM" is given to this
additional memory.
1/0 PORTS
The MK2870 provides four, 8 bit bidirectionallnputlOutput
ports. These are ports 0, 1,4,5. However, only 20 ofthe bits
are connected to 1/0 pins. The remaining bits are storage
elements. In addition, the Interrupt Control Port is
addressed as Port 6 and the binary timer is addressed as
Port 7. The programming of Ports 6 and 7 and the
bidirectional 1/0 pin are covered in the 3870 Family
Technical Manual. The schematic of an 1/0 pin and
available output drive options are shown in Figure 6.
An output ready strobe is associated with Port 4. This flag
may be used to signal a peripheral device that the MK2870
has just completed an output of new data to Port 4. The
strobe provides a single low pulse shortly after the output
operation is completely fin ished, so either edge may be used
to signal the peripheral. STROBE may also be used as an
input strobe to Port 4 after completing the input operation.
To usea portpinasan input, the large transistor which pulls
the pin to Vss must be turned off. This is accomplished by
writing a '0' to that bit ofthe port. This applies to Ports 0, 1,4,
and 5 only.
2870 TIME BASE OPTIONS
The 2870 contains an on-chip oscillator circuit which
provides an internal clock. The frequency of the oscillator
circuit is set from the external time base network. The time
base for the 2870 may originate from one of four sources:
The use of a crystal as the time base is highly recommended
as the frequency stability and reproducability from system
to system is unsurpassed. The 2870 has an internal divide
by two to allow the use of inexpensive and widely available
TV Color Burst Crystals (3.58 MHz). Figure 8 lists the
required crystal parameters for use with the 2870. The
Crystal Mode time base configuration is shown in Figure 7.
Through careful buffering ofthe XTL 1 pin it may be possible
to amplify this waveform and distribute it to other devices.
However, Mostek recommends that a separate active
device (such as a 7400 series TTL gate) be used to oscillate
the crystal and the waveform from that oscillator be
buffered and supplied to all devices, including the 2870, in
the eventthat a single crystal is to provide the time base for
more than just a single 2870.
While a ceramic resonator may work with the 2870 crystal
oscillator, it was not designed specifically to support the use
ofthis component. Thus, Mostek does not support the use of
a ceramic resonator either through proper testing,
parametric specification, or applications support.
LCNETWORK
The LC time base configuration can be used to provide a less
expensive time base for the 2870 than can be provided with
a crystal. However, the LC configuration is much less
accurate than is the crystal configuration. The LCtime base
configuration is shown in Figure 9. Also shown in the figure
are the specified parameters for the LC components, along
with the formula for calculating the resulting time base
frequency. The minimum value of the inductor which is
required for proper operation of the LC time base network is
0.1 millihenries. The inductormustbea Qfactorwhich is no
less than 40. The value of C is derived from C external, the
internal capacitance of the 2870 CXTL' and the stray
capacitances, CS1 and CS2 ' CXTL is the capacitance looking
into the internal two port netWork at XTL 1 and XTL 2. CXTL
is listed under the "Capacitance" section of the Electrical
Specifications. CS1 and CS2 are stray capacitances from XTL
1 to ground and from XTL 2 to ground, respectively. C
VIII-36
CRYSTAL MODE CONNECTION
Figure 7
XTl1
XTL2
D
AT· CUT
NOTE: Lead lengths from the crystal to the 2870 pins should be kept reasonably short to
reduce stray capacitance load.
CRYSTAL PARAMETERS
Figure 8
a) Parallel resonance, fundamental mode AT-Cut
b) Shunt capacitance (Co) = 7 pf max.
c) Series resistance (Rs) = See table
d) Holder = See table below.
Frequency
Series Resistance
Holder
f
=2-2.7 MHz
Rs
= 300 ohms max
HC-6
HC-33
f
= 2.8-4 MHz
Rs
= 150 ohms max
HC-6
HC-18*
HC-25*
HC-33
*This holder may not be available at frequencies near the lower end of this range.
external should also include the stray shunt capacitance
across the inductor. This is typically in the 3 to 5 pf range
and significant error can result if it is not included in the
frequency calculation.
Variation in time base frequency with the LC network can
arise from one of four sources: 1) Variation in the value of
the inductor. 2) Variation in the value of the external
capacitor. 3) Variation in the value of the internal
capacitance ofthe 2870 at XTL 1 and XTL 2 and 4) Variation
in the amount of stray capacitance which exists in the
circuit. Therefore, the actual frequency which is generated
by the LC circuit is within a range of possible frequencies,
where the range of frequencies is determined by the worst
case variation in circuit parameters. The designer must
select component values such that the range of possible
frequencies with the LC mode does not go outside of the
specified operating frequency range for the 2870.
RC CLOCK CONFIGURATION
The time base for the 2870 may be provided from an RC
network tied to the XTl2 pin, when XTL 1 is grounded. A
schematic picturing the RC clock configuration is shown in
Figure 10. The RC time.base configuration is intended to
provide an inexpensive time base source for applications in
which timing is not critical. Some users have elected to tune
each unit using a variable resistor or external capacitor thus
reducing the variation in frequency. However, for increased
time base accuracy Mostek recommends the use of the
Crystal or LC time base configuration. Figure 11 illustrates a
curve which gives the resulting operating frequency for a
particular RC value. The x-axis represents the product of the
value of the resistor times the value of the capacitor. Note
that three curves are actually shown. The curve in the
middle represents the nominal frequency obtained for a
given value of RC. A maximum curve and a minimum curve
VIII~37
II
LC MODE CONNECTION
Figure 8
XTL2
XTL1
---
---
--
L
J I
I
fJ J
I
I
I
L _________ ~ ~---------CEXTERNAL
(OPTIONAL)
f=
2
11"
v-LC
NOTE: The LC options uses the 88me mask option as the crystal option.
RC MODE CONNECTION
Figure 10
RCMODE
XTL2
XTL1
R
I
-L
'1'
I
MINIMUM R = 4K II
.....L
C = 26.5 p'F ± 2.6pF + Cextemal
VIII-38
CEXTERNAL
(OPTIONAL)
FREQUENCY VS. RC
Figure 11
..........
4 MHz
F
R
E
3 MHz
Q
U
E
N
C
y
287X·00, ·05
2MHz
RC PRODUCT
1 x 10-7
2 x 10-7
2.5 x 10- 7
for different types of 2870 devices are also shown in the
diagram.
3 x 10- 7
Maximum RC
= (R max) (C external max + CXTL max)
Minimum RC = (R min) (C external min + CXTL min)
The designer must select the RC product such that a
frequency of less than 2 MHz is not possible taking into
account the maximum possible RC product and using the
minimum curve shown in Figure 11. Also, the RC product
must not allow a frequency of more than 4 MHz taking into
account the minimum possible Rand C and using the
Maximum curve shown below. Temperature induced
variations in the external components should be considered
in calculating the RC Product.
Frequency variation from unit to unit due to switching speed
and level at constant temperature and Vee = + or -5
percent.
Frequency variation due to Vee with all other parameters
constant with respect to +5 V =+ 7 percent to -4 percent on
all devices.
Frequency variation due to temperature with respect to 25
C (all other parameters constant) is as follows:
PART #
VARIATION
287X-OO, -05
287X-10, -15
+6 percent to - 9 percent
+9 percent to -1 2 percent
Typical RC
II
= (R typ) (C external typ +
{CXTL max + CXTL min})
2
Positive Freq. Variation
= RC typical - RC minimum
RC typical
Netative Freq. Variation = RC maximum - RC typical
RC typical
due to RC Components
Total frequency variation due to all factors:
287X-OO, -05
+ 18 percent pi us positive
frequency variation due
to RC components
287X-l0, -15
= +21 percent plus positive
frequency variation due
to RC components
=-18 percent minus nega- =-21 percent minus
tive frequency variation due negative frequency variation
due to RC components
to RC components
Total frequency variation due to Vee and temperature of a
unit tuned to frequency at +5 V Vee, 25 C
Variations in frequency due to variations in RC components
may be calculated as follows:
287X-OO, -05
= + 13 percent
VIII-39
287X-10, -15
= +16 percent
EXTERNAL MODE CONNECTION
Figure 12
XTl1
XTL2
I
NO CONNECTION
EXTERNAL
CLOCK
INPUT
EXTERNAL CLOCK CONFIGURATION
requirements.
The connection for the external clock time base
configuration is shown in Figure 12. Refer to the DC
Characteristics section for proper input levels and current
Refer to the Capacitance section of the appropriate 2870
Family device data sheet for input capacitance.
VIII-40
OPERATING VOLTAGES AND TEMPERATURES
ELECTRICAL SPECIFICATIONS
MK2870
Operating
Voltage
Vee
Dash
Number
Suffix
Operating
Temperature
TA
+5V±10%
O°C -70°C
-00
-05
+5V±5%
O°C -70°C
+5 V ± 10";"
-40°C - +85°C
-10
+5V±5%
-40°C - +85°C
-15
See Ordering Information for explanation of part numbers.
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias .....•.......•...•......•.•..•.....
Storage Temperature ...........•....••......••............
Voltage on any Pin With Respect to Ground
(Except open drain pins and TEST) ....••......••.•........••
Voltage on TEST with Respect to Ground .••...••............
Voltage on Open Drain Pins With Respect to Ground ......... .
Power Dissipation .............•......••..•.....•.....•...
Power Dissipation by anyone I/O pin ...................... .
Power Dissipation by all I/O pins ....................•......
-00, -05
-20°C to +85°C
-65°C to +150°C
-10, -15
-50°C to + 100°C
-65°C to +150°C
-1.0Vto +7 V
-1.0Vto +9 V
-1.0Vto+13.5V
1.5W
60mW
600mW
-1.0Vto + 7 C
-1.0Vto +9 V
-1 .0 V to + 13.5 V
1.5W
60mW
600mW
*Stresses above those listed under "Absolute Maximum Ratings" maycause permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
AC CHARACTERISTICS
TA, Vee within specified operating range.
I/O power dissipation::S 100 mW (Note 2)
-00, -05
MAX
MIN
-10, -15
MIN
MAX
250
500
90
400
400
250
100
110
UNIT NOTES
SIGNAL
SYM
PARAMETER
XTL 1
XTL2
to
tex(H)
tax(L)
Time Base Period, all clock modes
External clock pulse width high
External clock pulse width low
cJ>
tol>
Internal cJ> clock
21:0
21:0
WRITE
1w
Internal WRITE Clock period
4tcJ>
6tcJ>
4tcJ>
6tcJ>
I/O
t dl/O
Output delay from internal
WRITE clock
0
t51/0
Input setup time to internal
WRITE clock
1000
t1/0-5
Output valid to STROBE delay
3tcJ>
-1000
3tcJ>
+250
3tcJ>
-1200
3tcJ>
+300
ns
I/O load =
50 pF + 1 TTL load
t5L
STROBE low time
8tcJ>
-250
12tcJ>
+250
8tcJ>
-300
12tcJ>
+300
ns
STROBE load =
50 pF + 3TTL loads
tRH
FiESEfhold time, low
6tcJ>
+750
6tcJ>
+1000
tRPoe
RESET hold time, low for power
clear
power
power
supply
STROBE
RESET
EXTINT
tEH
EXT INT hold time in active and
inactive state
100
supply
1000
500
390
390
0
1200
1200
ns
ns
ns
4 MHz - 2 MHz
Short Cycle
Long Cycle
ns
50 pF plus
one TTL load
ns
ns
r;so
r;so
time +0.1
time + ,15
ms
6tcJ>
+750
6tcJ>
+1000
ns
To trigger
interrupt
2tcJ>
2tcJ>
ns
To trigger timer
VIIJ-41
II
DC CHARACTERISTICS
TA • Vee within specified operating range
1/0 power dissipation:::; 100 rnW (Note 2)
-00. -05
SYMBOL
PARAMETER
lee
Average Power Supply Current
Po
MIN
Power Dissipation
MAX
-10. -15
MIN
MAX
UNIT DEVICE
85
110
rnA
MK2870/10
Outputs Open
94
125
rnA
MK2870/12
Outputs Open
85
110
rnA
MK2870120
Outputs Open
94
125
rnA
MK2870122
Outputs Open
400
525
rnW
MK2870/10
Outputs Open
440
575
rnW
MK2870/12
Outputs Open
400
525
rnW
MK2870120
Outputs Open
440
575
rnW
MK2870/22
Outputs Open
V IHEX
External Clock input high level
2.4
5.8
2.4
5.8
V
V ILEX
External Clock input low level
-.3
.6
-.3
.6
V
IIHEX
External Clock input high current
100
130
!LA
VIHEX=Vee
IILEX
External Clock input low current
-100
-130
!LA
VILEX=VSS
VIHI/O
Input high level. 1/0 pins
V IHR
V IHEI
Input high level. RESET
Input high level. EXT INT
2.0
5.8
2.0
5.8
V
Standard pull-up
2.0
13.2
2.0
13.2
V
Open drain (1)
2.0
5.8
2.2
5.8
V
Standard pull-up
2.0
13.2
2.2
13.2
V
No Pull-up
2.0
5.8
2.2
5.8
V
Standard pull-up
2.0
13.2
2.2
13.2
V
No Pull-up
-.3
.8
-.3
.7
V
(1 )
VIL
Input low level
IlL
Input low current. all pins with
standard pull-up resistor
-1.6
-1.9
rnA
VIN = 0.4 V
IL
Input leakage current. open drain
pins. and inputs with no pull-up resistor
+10
-5
+18
-8
!LA
!LA
V OH = 13.2 V
VIN = 0.0 V
IOH
Output high current pins with standard
pull-up resistor
-100
-89
!LA
V OH = 2.4 V
-30
-25
!LA
V OH = 3.9V
VIII-42
DC CHARACTERISTICS (cont.)
TA, Vee within specified operating range, I/O power dissipation:::: 100 mW (Note 2)
-00. -05
SYM
PARAMETER
MIN
IOHDD
Output high current, direct drive
pins
-100
-1.5
MAX
-10. -15
MIN
-S.5
IOHS
STROBE Output High current
IOL
IOLS
MAX
-SO
-1.3
-11
UNIT CONDITIONS
p,A
mA
mA
V OH = 2.4 V
V oH =1.5V
V OH = 0.7V
-300
-270
p,A
V OH = 2.4 V
Output low current
1.S
1.65
mA
V...o L = 0.4 V
STROBE Output Low current
5.0
4.5
mA
VOL = 0.4 V
TIMER AC CHARACTERISTICS
Definitions:
Error = Indicated time value - actual time value
tpsc = tep x Prescale Value
Interval Timer Mode:
Single interval error, free running (Note 3) ............................................................ ±6t
Cumulative interval error, free running (Note 3) ............. , ............................................. 0
Error between two Timer reads (Note 2) .................................................... , ... ±(tpsc + t
Load Timer to stop Timer error (Note 1) ........ , ......................................... + tep to - (tpsc + 2tep)
Load Timer to read Timer error (Notes 1, 2) ............................................ -5tep ± to - (tpsc + Step)
Load Timer to interrupt request error (Notes 1, 3) ............................................... -2tep to -9t
Pulse Width Measurement Mode:
Measurement accuracy (Note 4) ........................................................ + t to - (tpsc + 2tep)
Minimum pulse width of EXT INT pin .................................................................. 2tep
Event Counter Mode:
Minimum active time of EXT INT pin .................................................................. 2t
Minimum inactive time of EXT INT pin ................................................................. 2t
NOTES:
1. All times which entail loading, starting, or stopping the Timerare referenced
from the end of the last machine cycle of the OUT or OUTS instruction.
2. All times which entail reading the Timer are referenced from the end of the
last machine cycle of the IN or INS instruction.
3. All times which entail the generation of an interrupt request are referenced
from the start of the machine cycle in which the appropriate interrupt
request latch is set. Additional time may elapse if the interrupt request
occurs during a privileged or multicycle instruction.
4. Error may be cumulative if operation is repetitively performed.
VIII-43
AC TIMING DIAGRAM
Figure 13
External Clock
Internal Clock
1/0 Port Output
STROBE
RESET
EXTINT
~'"J=
tEH
ICP BITZ =1
Note: All AC measurements are referenced to V 1L max., V 1H min., VOL (.8v), or V OH (2.Ov).
VIII-44
INPUT IOUTPUT AC TIMING
Figure 14
INTERNAL
WRITE
CLOCK
I-----.J.--------I--------J-.---.t---.- ~:;;~;~~~~NSTRUCTION
• CYCLE TIMING
SHOWN FOR
4MHz EXTERNAL
CLOCK
A. INPUT ON PORT 4 OR 5
INTERNAL
WRITE
CLOCK
OUT OR
OUTS
OP CODE
FETCHED
PORT ADDR.
ON DATA
BUS
ACCUMULATOR
CONTENTS
ON DATA BUS
NEXT
OP CODE
FETCHED
PORT PINS
STAYS LOW
STROBE
IACTIVE FOR PORT 4 ONLYI
B. OUTPUT ON PORT 4 OR 5
FOR TWO WRIT[
r.YCLES
li/O·S
INTERNAL
WRITE
CLOCK
OUTS 0,1
FETCHED
ACC DATA
ON BUS
NEXT
OP CODE
FETCHED
PORT PINS
D. OUTPUT ON PORT 0, 1
C. INPUT ON PORT 0 OR 1
VIII-45
STROBE SOURCE CAPABILITY
(TYPICAL AT Vee = 5 V, TA = 25°C)
Figure 15
.15
s
0
u
A
e
E
·10
e
u
I..........
A
A
E
N
T
.....
to...
·5
....
M
A
'"
l"'-
I"
OUTPUT VOL TAGE
STROBE SINK CAPABILITY
(TYPICAL AT Vee
= 5 V, TA = 25°C)
Figure 16
S
+100
1
N
K
l-
e
u
A
R
E
+50
I-'"
N
T
IL
M
1.1
A
1/
I
~
I
OUTPUT VOLTAGE
STANDARD I/O PORT SOURCE CAPABILITY
(TYPICAL AT Vee = 5 V, TA = 25°C)
Figure 17
-1.5
s
0
U
A
e
-1.0
l"'-
E
I""
e
u
'"
A
A
E
N
T
I'
·,5
'" "'" ,.....
M
A
"""
OUTPUT VOL T AG~
DIRECT DRIVE I/O PORT SOURCE CAPABILITY
(TYPICAL AT Vee = 5 V, TA = 25°C)
Figure 18
s
o
U
A
·10
e
E
e
u
A
A
E
r-~
·5
N
T
....
.....
I"'-
M
A
......
OUTPUT VOL TAGE
VIII·46
I/O PORT SINK CAPABILITY
(TYPICAL AT
Figure 19
vee =
5 V, TA' = 25°C )
S
I
N
K
C
U
.4 0
R
R
E
'3 0
I-
N
T
~
M
A
i-'"
0
OUTPUT VOL TAGE
MAXIMUM OPERATING TEMPERATURE VS.
I/O POWER DISSIPATION
Figure 20
100
....
-
Pl~flC
50
100
200
300
r-...
400
....
CERAM'ic
500
600
POliO MW
VIII·47
1000
ORDERING INFORMATION
There are two types of part numbers for the 2870 family of
devices. The generic part number describes the basic device
type, the amountof ROM and Executable RAM, the desired
package type, temperature range, and power supply
tolerance. For each customer specific code, additional
information defining I/O options and oscillator options will
be combined with the information described in the generic
part number to define a customer/code specific device
order number.
GENERIC PART NUMBER
An example of the generic part number is shown below.
MK 2870 / 2 2 N - 1 0
0= 5V± 10%
5 = 5V±5%
11power Supply Tolerance
Loperating Temperature Range
0= O°C - +70°C
1 = -40°C - +85°C
Package type
'-----1~Executable
N = Plastic
RAM Designator
0= None
2 = 64 bytes
'----_ROM Designator
L------_~Basic
1=1Kbytes
2 = 2K bytes
Device Type
DEVICE ORDER NUMBER
An example of the device order number is shown below.
MK 87007 N - 0 5
l~Powe'
S"POIV
Tol"'~
.0=5V±10%
5 = 5V±5%
Operating Temperature Range
0= O°C - +70°C
1 = -40°C - +85°C
'----.Package Type
N = Plastic
'------.Customer/Code Specific Number
The Customer/Code specific number defines the ROM bit
pattern, I/O configuration, oscillator type, and generic part
type to be used to satisfy the requirements of a particular
customer purchase order. For further information on the
ordering of mask ROM devices, the customer should refer to
the 3870 Family Technical Manual.
VIII-48
MOSTEI(.
3870 SINGLE CHIP MICRO FAMILY
MK3873 and MK38P73
MK3873 FEATURES
o Available with 1K or 2K byte mask programmable ROM
o
Software compatible with 3870 instruction set
o 64 byte scratchpad RAM
o
Available with 64 byte Executable RAM
o
29 bits (4 ports) TTL compatible parallel 1/0
o
Serial Input/Output port
• External or Internal Serial Port Clock
• Transmit and Receive registers double buffered
• Internal Baud rate generator
• Synchronous or Asynchronous serial 1/0
• Data rates to 9600 bits per second (ASYNC)
• I/O pins dedicated as SERIAL IN, SERIAL OUT, and
SERIAL CLOCK
• Variable duty cycle waveform generation
o
Vectored interrupts
o
Programmable binary timer
• Internal timer mode
• Pulse width measurement mode
• Event counter mode
o
External Interrupt
XTL 1 -----.
1
XTL2_ 2
PO-O_ 3
po., ....... 4
o Crystal, LC, RC or external time base options available
o
Low power (325 mW typ.)
o
Single +5V power supply
o
MK38P73 PIN CONNECTIONS
XTL1~
1
XTL2_ 2
Pinout compatible with the 3870 Family members
394-- FfEm
38~ EXTINT
PO-1 .......
4
~
5
37 ..... Pf.3
36 ....... SRClK
...........
J5if.3.....-. 6
35 .... SI
34 ...... SO
33 ......
~
32 .....
P5-'i
SfROiE _
MK3BP73 FEATURES
40 ..-....- Vee
'SO:O ........ 3
7
o
EPROM version of MK3873
154-0 ....... 8
P4.i ..... 9
Pi1: ....... 10
o
Piggyback PROM (P-PROM)TM package
P4-4 ........ 12
P4-5 --... 13
29 ....... P6-4
1i4-'6_14
27 ...... PS":a
2& ...... P5-7
~
o
P4-'7 ......
Accepts 24 pin or 28 pin EPROM memories
o
Identical pinout as MK3873
o
In-SOCket emulation of MK3873
....... 1'
VIII-49
15
31 ....... PS.2
3O ...... ~
28 ....... P!r.5
~"""'6
25 ...... Pf7
fSO-6 ....... 17
24 - - .
j5i().'5 ......... 18
'PO-'4 ........ 19
23 ......... Pr.5
22 ....... I5f..4
GND ---+- 20
21 _ _ TEST
K-I
SO - SERIAL OUT is an output line for either serial
synchronous or asynchronous data.
GENERAL DESCRIPTION
The MK3873 single chip microcomputer introduces a major
addition to the 3870 microcomputer family, a serial
input! output port. This serial port is capable of either
synchronous or asynchronous serial data transfers. The heart
of the serial port is a 16-bit Shift Register that is doublebuffered on transmit and receive. The Shift Register clock
source can be either the internal baud rate generator or an
external clock. An end-of-word vectored interrupt is
generated in either transmit or receive mode so that the CPU
overhead is only at the word rate and not at the serial bit rate.
This serial channel can be used to provide a low-cost data
channel for communicating between 3873 microcomputers
or between a 3873 and another host computer. The serial
port is also very flexible so that it could be used for other
purposes such as an interface to external serial logic or serial
memory devices.
SRCLK is the clock for the serial port operations. It can be
configured by software to be an input or output depending
upon whether an internal baud rate or external clock is
desired. It has a Schmitt trigger input and can be used to drive
up to 3 TIL loads.
STROBE is a ready strobe associated with 1/0 Port 4. This pin
which is normally high provides a single low pulse after valid
data is present on the J54-O - P4-i pins during an output
instruction. STROBE can be used to drive up to 3 TIL loads.
RESET may be used to externally reset the MK3873. When
pulled low the MK3873 will reset. When allowed to go high
the MK3873 will begin program execution at program
location H'OOO'.
The MK3873 retains commonality with the 3870 family of
single chip microcomputers. It has up to 2048 bytes of mask
ROM for program storage, and 64 bytes of scratchpad
random-access memory. Certain versions also include up to
64 bytes of Executable RAM. Also, the 3870's sophisticated
programmable binary timer is included and provides for
system flexibility by operating in 3 different modes. The
MK3873 has a large number of parallel 110 lines available
to the user. Twenty nine pins of the MK3873 are dedicated
to parallel 1/0. In addition, three pins are dedicated to the
serial 1/0 port. These pins provide input, output, and clock
for the serial port. The serial clock pin can be driven externally or programmed to provide a 50% duty cycle TIL compatible serial clock. No additional CPU instructions are
necessary for use with the serial port. Thus, the MK3873 is
instruction set compatible with the rest of the 3870 family.
The MK38P73 microcomputer is the PROM based version of
the MK3873 single-chip microcomputer. The MK38P73 is
called the Piggyback PROM (P-PROM)TM microcomputer
because of a new packaging concept. This concept allows a
24 or 28 pin EPROM to be mounted directly on top of the
microcomputer itself. The EPROM can then be removed and
reprogrammed as required with a standard PROM
programmer. The MK38P73 retains exactly the same pinout
and architectural features as other members of the
MK3873 Family. The MK38P73 is discussed in more detail
in a later section of this document.
PIN NAME
DESCRIPTION
TYPE
PO-O, PO-7
P1-3 - P1-7
P4-O - P4-7
P5-0 - P5-7
STROBE
EXTINT
RESET .
SI
SO
SRCLK
TEST
XTL 1,XTL2
VCC,GND
1/0 PortO
1/0 Port 1
1/0 Port 4
1/0 Port 5
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Output
Input
Input
Input
Output
Bidirectional
Input
Input
Input
Ready Strobe
External Interrupt
External Reset
Serial Input
Serial Output
Serial Clock
Test Line
Time Base
Power Supply
Lines
EXT INT is the external interrupt input. Its active state is
software programmable as described in the 3870 Family
Technical Manual. This input is also used in conjunction with
the timer for pulse width measurement and event counting.
XTL 1 andXTL2arethetimebase inputs (2 MHzt04MHz)to
which a crystal, LC network. RC network. or an external
single-phase clock may be connected. The time base mode
must be specified when submitting an order for a mask ROM
MK3873. The MK38P73 will operate with any of the four
configurations.
MK3873 ARCHITECTURE
FUNCTIONAL PIN DESCRIPTION
PO-O - P07, P1-3 - P1-7, P4-0 - P4-7, P5-O - P5-7 are 29
bidirectional 1/0 lines which can either be used as TIL
compatible inputs or latch outputs.
SI - SERIAL IN is a TIL compatible Schmitt Trigger input pin
for either serial synchronous or asynchronous data.
The architecture ofthe MK3873 is identical to that of the rest
of the devices in the 3870 family, with the exception of the
serial port logic. The serial port logic is shown in the block
diagram of the MK3873 {Figure 1). Addressing of the serial
port logic is accomplished through 1/0 instructions.
Operation and programming of the serial port is thoroughly
discusssed below. A programming-model of the MK3873 is
shown in Figure 2. For a more complete discussion of the
3870 family architecture, the user is referred to the 3870
Family Technical Manual..
VIII-50
MK3873 BLOCK DIAGRAM
Figure 1
EXTINT
TEST
SERIAL SERIAL
SERIAL
CLOCK INPUT 151)
OUTPUT ISO)
SRCLK
MAIN MEMORY
EXECUTABLE RAM
The main memory section on the MK3873 consists of a
combination of ROM and executable RAM.
There are four registers associated with the main memory
section. These are the Program Counter (PO). the Stack
Register (P). the Data Counter (DC). and the Auxiliary Data
Counter (DC1). The Program Counter is used to address
instructions during program execution. P is used to save the
contents of PO during an interrupt or subroutine call. Thus.
P contains the return address at which processing is to
resume upon completion of the subroutine or the interrupt
routine. The Data Counter (DC) is used to address data
tables. This register is auto-incrementing. Of the two data
counters. only DC can access memory directly. However.
the XDC instruction allows DC and DC1 to be exchanged.
The length ofthe PO. p. DC. and DC1 registers for all MK3873
devices is listed in the table shown in Figure 3. The graph and
table in Figure 3 also shows the amounts of ROM and
executable RAM for the different members of the MK3873
family.
The upper bytes of the total address space in certain
MK3873 devices is RAM memory. As with the ROM memory
the RAM may be addressed by the PO and DC address
registers. The executable RAM may be accessed by all 3870
instructions which address main memory indirectly through
the Data Counter (DC) register. Additionally. the MK3873
may execute an instruction sequence which resides in the
Executable RAM. Note that this cannot be done with the
scratchpad RAM memory. which is the reason the term
"Executable RAM" is given to this additional memory.
I/O PORTS
On the MK3873. 29 lines are provided for bidirectional.
parallel I/O. These lines are addressable as four parallel I/O
ports at locations O. 1.4. and 5. Note that Ports 0.4. and 5 are
8 bits wide. while Port 1 contains only 5 bits of I/O in bit
positions 3. 4. 5. 6. and 7. Bits 0-2 on Port 1 are not available
for use as I/O port pins or as storage elements. The
remaining three pins are used to provide the serial I/O
VIII-51
II
MK3873 PROGRAMMABLE REGISTERS. PORTS. AND MEMORY MAP
Figure 2
CPU REGISTERS
1/0 PORTS
BINARY
TIMER
ACCUMULATOR
PORT7
A
7..-8 91T8--. 0
74--8
SCRATCHPAD DEC
BITS~
H
0
I
INTERRUPT
CONTROL PORT
STATUS
REGISTER
IWI
PORT 6
I
N
T
R
BAUD RATE
CONTROL PORT
C F
PORTC
0
KL
OU
OL
7 '4-8 81T8--.. 0
I~
IISU
6
SHIFT REGISTER
BUFFER
UPPER HALF
10
A
12
11
12
13
14
8
C
13
14
16
11
0
E
15
18
17
Y
4 ~6 BITS----. 0
INDIRECT
SCRATCHPAD
ADDRESS REGISTER
PORTO
o
9
N L
T 0
R W
L
SERIAL PORT
CONTROL. STATUS REGISTER
OC1
o
I
HL
KU
0 Z C 5
V E A I
ERR G
R 0 R N
HEX
o
J
HU
I~I+I+I
7 -4-8 BITS....... 0
3~4BITS-'
SCRATCHPAO MEMORY
61
30
76
82
83
3E
3F
76
77
7~88ITS~O
ISL I
32
0
....-68IT5-...
MAIN MEMORY
PORT E
7~
PROGRAM
COUNTER
8 81T8..-.. 0
Ipou
PO
J
11
POL
§
I
0
87
~12BITS--"
SHIFT REGISTER
BUFFER
LOWER HALF
I
P
I
PU
PORTF
11
7....-88IT8 .... 0
PL
I
I
87
0
12 BITS----.
PORTO
RAM
I
7~8BITS---+-O
I
AUX DATA
COUNTER
I
7_6BITS . .3
11
DC1
4094
MK3873/22 d 4 0 9 5
I
I
DCIL
87
0
____ 12 BITS ______
74- 8 BITS-+O
ROM TOP
MK387~/10
MK3873/12
7FE
7FF
.
MK3873/12
DCIU
PORT 1
~
3FE
3FF
I
U4032
1===i~033
DC
~
I
!!li!
2048
DATA
PORT4
1
2047
COUNTER
IDCU
11
HEX
0
1
\1022
87
0
....-- 12 BITS---+-
PARALLEL
1/0 PORTS
PORT 6
I
ROM
StACK
REGISTER
DEC
0
FCO
FC1
FFE,
FFF
ROM TOP
MK3873/20
MK3873/22
MK3873 MAIN MEMORY SIZES AND TYPES
Figure 3
r-::l
r-::l---
~
1
I
1
I
~1- -
1
I
I
i
l
I
I
1:1
~
\ 3873/10
i
HEX
DEC
FFF
4095
FCO
4032
64 BYTES
EXECUTABLE
RAM
- "';F?:B~F;----'--':4;;0~3~1'--./
I
l
I
~~M I [J
3873/12
w_ _ -i~
t
Internal clock
210
210
WRITE
tw
Internal WRITE Clock period
4t
6t
4t
6t
I/O
tdl/O
Output delay from internal
WRITE clock
0
tsl/O
Input setup time to internal
WRITE clock
1000
STROBE
RESET
tl/O-s Output valid to S'fROBE delay
0
Short Cycle
Long Cycle
ns
50pF plus
one TIL load
ns
3t
+250
3t
-1200
3t
+300
ns
I/O load =
50pF + 1 TTL load
12t
+250
8t
-300
12t
+300
ns
STROBE load =
50pF+3TILloads
8t
-250
tRH
RESET hold time, low
6t<1>
+750
6t
+1000
power
supply
power
supply
rise
tEH
4MHz-2MHz
3t
-1000
STROBE low time
EXT INT hold time in active and
inactive state
1200
1200
tsL
tRPOC RESET hold time, low for power
clear
EXTINT
1000
UNIT NOTES
rise
time
time
-0.1
-0,15
6t
+750
2t
6t
+1000
2t
VIII-68
ns
ms
ns
ns
To trigger
interrupt
To trigger timer
CAPACITANCE
TA = 25°C
All Part Numbers
MIN
SYM
PARAMETER
CIN
Input capacitance; liD, RESET, EXT INT, TEST
CXTL
Input capacitance; XTL1, XTL2
MAX
UNIT
10
pF
29.5
pF
23.5
NOTES
unmeasured
pins grounded
AC CHARACTERISTICS FOR SERIAL 1/0 PINS
TA' VCC within specified operating range.
I/O Power Dissipation::::; 1OOmW (Note 2)
-00, -05
-10, -15
SIGNAL SYM
PARAMETER
MIN
MAX
MIN
SRCLK
Serial Clock Period in
3.25
00
3.25
00
IJ.S
4.0
00
4.0
00
p's
tw(SRCLKH) Serial Clock Pulse Width, High.
External Clock Mode
1.3
00
1.3
00
p's
tw(SRCLKL) Serial Clock Pulse Width, Low.
External Clock Mode
1.3
00
1.3
00
p's
tC(SRCLK)
External Clock Mode
tr(SRCLK)
Async
Sync
Serial Clock Rise Time
MAX UNIT
100 ns
60
Internal Clock Mode
tf(SRCLK)
tS(SI)
Serial Clock Fall Time
Setup Time To Rising Edge
50
30
ns
Hold Time From Rising
0
0
ns
2
2
p's
Edge of SRCLK (SYNC Mode)
SO
tD(SO)
2.4V-O.4V
CL = 100pf
of SRCLK (SYNC Mode)
tH(SI)
0.8V-2.0V
CL = 100pf
Internal Clock Mode
SI
CONDITIONS
Data Output Delay From
1190
Falling Edge of SRCLK
(SYNC Mode)
VIII-69
1190 ns
AC CHARACTERISTICS FOR MK38P73
(Signals brought out at socket)
TA, VCC within specified operating range.
I/O Power Dissipation :5 100mW (Note 2)
-10, -15
-00. -05
SYMBOL
PARAMETER
taas*
Access time from
Address A,,-Ao' stable
until data must be valid at
07- 0 0
MIN
MAX
650
MIN
MAX
UNIT CONDITION
650
ns
= 2.0MHz
*See Table in Figure 13.
DC CHARACTERISTICS
TA, Vce within specified operating range
I/O Power Dissipation :5 1OOmW (Note 2)
-00.-05
SYM
PARAMETER
lec
Average PoWer Supply
Current
Po
Power Dissipation
MIN
-10.-15
MAX
DEVICE
MAX
UNIT
93.5
121
mA
MK3873/10
Outputs Open
103
138
mA
MK3873/12
Outputs Open
93.5
121
mA
MK3873/20
Outputs Open
103
138
mA
MK3873122
Outputs Open
138
165
mA
MK38P73/02
No EPROM,
Outputs Open
440
570
mW
MK3873/10
Outputs Open
485
645
mW
MK3873/12
Outputs Open
440
570
mW
MK3873120
Outputs Open
485
645
mW
MK3873/22
Outputs Open
646
775
rriW
VIII-70
MIN
MK38P73/02
No EPROM,
Outputs Open
DC CHARACTERISTICS
TA, VCC within specified operating range
1/0 Power Dissipation :5100rnW (Note 2)
-00,-05
SYM
PARAMETER
VIHEX
-10,-15
MIN
MAX
MIN
MAX
External Clock input high level
2.4
5.8
2.4
5.8
V
V,LEX
External Clock input low level
-.3
.6
-.3
.6
V
"HEX
External Clock input high current
100
130
JJA
V'HEX=VCC
"LEX
External Clock input low current
-100
-130
JJA
V'LEX=VSS
V,H,/O
1/0 input high level
V,HR
V,HE,
Input high level. RESET
Input high level, EXT INT
UNIT CONDITIONS
2.0
5.8
2.0
5.8
V
standard pull-up (1 )
2.0
13.2
2.0
13.2
V
open drain (1)
2.0
5.8
2.2
5.8
V
standard pull-up (1)
2.0
13.2
2.2
13.2
V
No pull-up
2.0
5.8
2.2
5.8
V
standard pull-up (1)
2.0
13.2
2.2
13.2
V
-.3
.8
-.3
0.7
V
No pull-up
V,L
1/0 ports, RESET1, EXT INIl
input low level
',L
Input low current, standard
pull-up pins
-1.6
-1.9
rnA V'N=0.4V
'L
Input leakage current, open drain
pins RESET and EXT INT inputs
With no pull-up resistor
+10
-5
+18
-8
JJA
JJA
V'W 13 .2V
V'N=O.OV
10H
Output high current, standard
-100
-89
JJA
VOW2.4V
pull-up pins
-30
-25
JJA
VOW3.9V
Output high current,
-100
-80
JJA
VOW2.4V
direct drive pins
-1.5
10HDD
-1.3
-8.5
-11
(1 )
rnA VOW1.5V
rnA VOWO.7V
10L
Output low current, 1/0 ports
1.8
1.65
rnA
VOL=0.4V
'OHS
STROBE Output High current
-300
-270
JJA
VOW 2 .4V
'OLS
STROBE output low current
5.0
4.5
VIII-71
rnA VOL=0.4V
DC CHARACTERISTICS FOR MK38P73
(Signals brought out at socket)
TA, V CC within specifiec operating range, I/O Power Dissipation :5 100mW. (Note 2)
-00, -05
SYM
PARAMETER
MIN
Power Supply Current
for EPROM
MAX
-10. -15
MIN
-185
MAX
UNIT CONDITION
-185
rnA
VIL
Input Low Level Data bus in
-0.3
0.8
-0.3
0.7
V
VIH
Input High Level Data bus in
2.0
5.8
2.0
5.8
V
10H
Output High Current
-100
-30
-90
-25
pA
pA
10L
Output Low Current
1.8
1.65
rnA VOL=0.4V
IlL
Input Leakage Current
10
10
pA
VOW2.4V
VOW3.9V
Data Bus in Float
DC CHARACTERISTICS FOR SERIAL PORT I/O PINS
TA, VCC within specified operating range
I/O Power Dissipation :5 1OOmW (Note 2)
-00. -05
!.
SYM
PARAMETER
VIHS
-10. -15
MIN
MAX
MIN
MAX
Input High for SI, SRCLK
2.0
5.8
2.0
5.8
V
VILS
Input Low level for SI. SRCLK
-.3
.8
-.3
0.7
V
IlLS
Input low current for SI, SRCLK
10HSO
Output High Current SO
-100
-30
-90
-25
pA
pA
10LSO
Output Low Current SO
1.8
1.65
rnA VOL =O.4V
10HSRC Output High Current SRCLK
-300
-270
pA
10LSRC Output Low Current SRCLK
5.0
4.5
-1.6
-1.9
UNIT TEST CONDITIONS
rnA VIL =0.4V
VOH = 2.4V
VOL =3.9V
VOH = 2.4V
rnA VOL =0.4V
1. RESET and EXT INT have internal Schmit triggers giving minimum .2V hysteresis.
2. Power dissipation for I/O pins is calculated by 1: (VCC - VILi gilL! ) + 1: (Vee' VOH) Olot-lll + 1: (VoLi (loll
TIMER AC CHARACTERISTICS
Definitions:
Error = Indicated time value - actual time value
tpsc = t cI> x Prescale Value
Interval Timer Mode:
Single interval error, free running (Note 3) .....•................•.................•......•........•.... ±6tcI>
Cumulative interval error, free running (Note 3) ................•.......•.......................•........•.. 0
Error between two Timer reads (Note 2) •........•............•....•..••.•..•.................... ± (tpsc + tcI>
Start Timer to stop Timer error (Notes 1,4). . . . . . • . . . . . . . . . • • . . . . . . . . . . . . .. ......•........... +tcI> to -(tpsc +tcI»
Start Timer to read Timer error (Notes 1,2) ....•...•...••..•.............. . ........•....• -5tcI> to -(tpsc + 7tcI»
Start Timer to interrupt request error (Notes 1,3) .....•........•...•.••.•.............•...•..•.. -2tcI> to -8tcI»
Load Timer to stop Timer error (Note 1) ..•.......•..•......••......•.•.......••..•.....•.. +tcI> to -(tpsc + 2tcI»
Load Timer to read Timer error (Notes 1,2) ..•....•...•.........•..........••............ -5tcI> to -(tpsc + 8tcI»
Load Timer to interrupt request error (Notes 1,3) ..•...................••.......•............... -2tcI> to -9tcI»
VIII-72
Pulse Width Measurement Mode:
Measurement accuracy (Note 4) ...•.....•......................•.................... +t ~ to -(tpSC +2t ~)
Minimum pulse width of EXT INT pin ................................................................ 2t~
Event Counter Mode:
N_
Minimum active time of EXT INT pin ................................................................ 2t~
Minimum inactive time of EXT INT pin ............................................................... 2t~
1. All times which entail loading. starting. or stopping the Timer are referenced from the end of the last machine cycle of the OllT or, OlITS instruction.
2. All times which entail reading the Timer are referenced from the end of the lest machine cycle of the IN or INS instruction.
3. All times which entail the generation of an interrupt request are referenced from the start of the machine cycle in which the appropriate interrupt request latch is set Additional
time may elapse if the interrupt request occurs during a privileged or multicyCle instruction.
4. Error may be cumulative Woperation is repet~ively performed.
AC TIMING DIAGRAM
Figura 20
External Clock
Internal ~ Clock
I/O Port Output
STROBE
RESET
EXTINT
~~J=
-
tEH
ICPBIT2=1
Note: All AC measurements are referenced to V IL max., V IH min., VOL (.8v), or V OH (2.0v).
VIII-73
INPUT/OUTPUT AC TIMING
Figure 21
INTERNAL
WRITE
CLOCK
* CYCLE TlMI NG
SHOWN FOR
4MHz EXTER NAL
CLOCK
CYCLE TIMING
DEPENDS ON INSTRUCTION
n
2JJ$*
I
INOR
INS
OPCODE
FETCHED
3J.1S*
r
PORT ADDR.
PLACED ON
DATA BUS
PORT PINS
r
3J.1S*
PORT DATA
DRIVEN ON TO
DATA BUS
2J.1S*
r
I
1-------
J\-
NEXT
OPCODE
FETCHED
~
X
tSI {O
A. INPUT ON PORT 4 OR 5
INTERNAL
WRITE
CLOCK
CYCLE TIMING
~----'--+-------~--~'-------------+-----~~--~~DEPENDSONINSTRUCTION
3J.1S*
PORT ADDR.
ON DATA
BUS
3J.1S*
ACCUMULATOR
CONTENTS
ON DATA BUS
NEXT
OP CODE
FETCHED
PORT PINS
STAYS LOW
STROBE'
(ACTIVE FOR PORT 4 ON L Y)
FOR TWO WRITE
CYCLES
tI/O-S
B. OUTPUT ON PORT 4 OR 5
INTERNAL
WRITE
CLOCK
OUTS 0,1
FETCHED
ACC DATA
ON BUS
PORT PINS
C. INPUT ON PORT 0 OR 1
D. OUTPUT ON PORT 0, 1
VIII-74
OP CODE
FETCHED
AC TIMING DIAGRAM FOR SERIAL I/O PINS.
Figure2i2
tS(51)
tc(SRCLK)
lW(5.RCLKH)
SRCLK
I
tH(SI)
I
I
tW(SRCLKL)
51
)
[)(
to(SO)
X
so
STROBE SOURCE CAPABILITY
(TYPICAL AT VCC =5V. TA = 25°C) s
_.
-15
--
0
Figure 2.3
u
R
E
-10
C
U
R
R
E
N
T
,-1-
- - t---- -
c
r
~
!
-5
"
M
A
ft- . "_+ " t--"
- I
I
:
I'
OUTPUT VOLTAGI;
STROBE SINK CAPABILITY
(TYPICALATVCC = 5V. TA = 25°C)
Figure 24
S
I
N
K
+100
+-- .--
-I
i +- --.
C
U
R
R
E
N
T
M
A
+50
......
-
....
I
I
./I
1/
~
OUTPUT VOLTAGE
VIII-75
,
,
..1.5
STANDARD I/O PORT SOURCE CAPABILITY
(TYPICALATVCC = 5V. TA = 25°C)
Figure 25
s
0
U
r-..
R
c
-1.0
E
'"
C
U
R
R
E
N
T
r-.
~
I'
-.5
i'o
~
M
A
i'"
-
r-..
·1
OUTPUT VOLTAGE
DIRECT DRIVE 1/0 PORT SOURCE CAPABILITY
(TYPICAL AT VCC = 5V. TA = 25°C)
Figure 26
s
o
f-~
U
r-
f- ..
-10
R
-+-
1-:-- C- ..
C
E
f-,- _.
c
R
R
E
N
T
f--
.-
-
.....
...
-
,---
---
r
. f-r--.-
l-
-5
M
A
-
-. f-
r-I-~
U
-+
. f-
-
. -~
f- ... - ..
..
......
"'"
f--
.-
r-.r-;
OUTPUT VOLTAGE
I/O PORT SINK CAPABILITY
(TYPICAL AT VCC = 5V. TA = 25°C)
Figure 27
+60
S
I
N
K
C
U
R
R
E
N
T
+50
-
.
- f-c-
+40
r+30
M
A
+20
~
I-'"
+10
1 f-"
"
I"
~.. 2
OUTPUT VOL T AGE
MAXIMUM OPERATING TEMPERATURE VS. I/O POWER DISSIPATION
Figure 28
H-
~
100
~+-
···f- e _
.....
-
f-I---
C-o.
..
---~
f-
.-
~
.....
50
~
.....
-
-·F
.
._-
~(4'S'rlc
-.-
-- . -f:;: -+-1-I
.... t'-- .... ~'!.."-M"7c -I-
-
f-+
~
- 100
200
300
400
t
500
600
PDI/OMW
VIII-76
_L_
-
1000
ORDERING INFORMATION
There are two types of part numbers for the 3870 family of
devices. The generic part number describes the basic device
type, the amount of ROM and Executable RAM, the desired
package type, temperature range, and power supply
tolerance. For each customer specific code, additional
information defining I/O options and oscillator options will be
combined with the information described in the generic part
number to define a customer/code specific device order
number.
GENERIC PART NUMBER
An example of the generic part number is shown below.
MK 3873/2 0 P-1 0
l~p",,", S"'"~ T~.,,"oe
0= 5V± 10%
5=5V±5%
Operating Temperature Range
0= O°C - +70°C
1 = -40°C - +85°C
P = Ceramic
N = Plastic
Package type
L----t.
L....._ _. . .
Executable RAM Designator
0= None
2 = 64 bytes
ROM Designator
1 = 1K Bytes
2 = 2K bytes
Basic Device Type
An example of the generic part numberforthe PPROM device
is shown below.
II
MK38P73/02 R-OS
DEVICE ORDER NUMBER
An example of the device order number is shown below.
L:-, Su~Tm".~
MK 13002 N - 0 5
[1
0= 5V± 10%
S =5V±5%
0= O°C - +70°C
1 = -40°C - +85°C
P = Ceramic
N = Plastic
Loperating Temperature Range
Package Types
L....-----Customer/Code Specific Number
The Customer/Code specific number defines the ROM bit
pattern, I/O configuration, oscillator type, and generic part
type to be used to satisfy the requirements of a particular
customer purchase order. For further information on the
ordering of mask ROM devices, the customer should refer to
the 3870 Family Technical Manual.
VIII-77
VIII-78
MOSTEI(.
3870 SINGLE CHIP MICRO FAMILY
MK3875 and MK38P75
MK3875 FEATURES
MK3875
o Available with 2K or 4K bytes of mask programmable
ROM memory.
o 64 bytes scratchpad RAM
o 64 bytes of Executable RAM
o Standby feature for low power data retention of
executable RAM including:
Low standby power
Low standby supply voltage
No external components required to trickle charge
battery.
o Software compatible with 3870 family
o 30 bits (4 ports) TTL compatible 1/0
o Programmable binary Timer
Interval Timer Mode
Pulse Width Measurement Mode
Event Counter Mode
MK38P75
o External Interrupt Input
o Crystal, LC, RC, or external time base options available
D Low power under normal operation (285 mW tYP.)
II
o +5 volt main power supply
o Pinout compatible with 3870 family
MK38P75 FEATURES
o EPROM version of MK3875
o Piggyback RPOM (P-PROM)TM package
o Accepts 24 pin or 28 pin EPROM memories
o Identical pinout as MK3875
o In-socket emulation of MK3875
PIN CONNECTIONS
MK3875
Xlll_
1
xTL2_
V
_
SB
2
vsa i502-
3
•
•
P'Qj ......... 6
PIN CONNECTIONS
MK38P75
4 0 _ V"
3 9 _ A'mf
3 8 _ EXT INT
37-Pi'O.
3 6 _ Pii
35 ........
Pi2
XTL1_
1
40 -
xTL2_
2
39_~
Vea'--"
J
V SB ' - -
4
37_~
1i'Oi-
5
6
36_Pi"i
35 _
Pi2
STROBE _
7
34. _
Prj
P4Q _
8
33 -
P50
POJ_
38 -
Vee
EXTINT
SfR"B'ii"E_
7
m-
8
3' -Pi3"
33 ___ P'5"O
P41
;;r,P43'-
9
32_
Pn
P4i'-
P52
P53
~_10
m_
11
31
30 _
12
29_
13
PSi
PiJ- "
'P44_ 12
Pi"'5-
28_
'Pi'6P47_
,."
m
27 26 _
fiS6
m_14
27 _
Pi7_
15
25 _
Pi7
26_Ji5"7
P07 -
16
-
10
P 0 6 _ 17
PO'S-
18
-
P45 _
g'7
24_m
PO'6_
13
17
2J_m
21
-
32 31 -
30 ___
29 -
fiST
PSi
P53
PS4
28_~
Ps6
2S _
Pi7
24 -
PiS
2J_~
22_1Si4
G N D - 20
9
PO"4-19
TEST
22_i514
21
VIII-79
_
TEST
PIN NAME
DESCRIPTION
TYPE
PO-2-
I/O Port 0
I/O Port 1
I/O Port 4
I/O Port 5
Ready Strobe
External Interrupt
External Reset
Test Line
Time Base
Power Supply Lines
Standby Power
Substrate Decoupling
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Output
Input
Input
Input
Input
Input
Input
Input
PO-7
Pf.{) - Pl-7
P4-0 - P4-7
P5-0 - P5-7
STROBE
EXTINT
RESET
TEST
XTL 1, XTL 2
VCC,GND
VSB
VBB
valid data are present on the P4-0 - P4-7 pins during an
output instruction.
RESET - may be used to externally reset the MK3875.
When pulled low, the Mk3875 will reset. When allowed to
go high the MK3875 will begin program execution at
program location H '000'. Additionally, when RESET is
brought low all accesses of the executable RAM are
prevented and the RAM is placed in a protected state for
powering down Vee without loss of data.
EXT INT is the external interrupt input. Its active state is
software programmable. This input is also used in
conjunction with the timer for pulse width measurement
and event counting.
GENERAL DESCRIPTION
The MK3875 Single Chip Microcomputer offers a Low
Power Standby mode of operation as an addition to the
3870 Family. The Low Power Standby feature provides a
means of retaining data in the executable RAM on the
MK3875 while the main power supply line (Ved is at 0 volts
and the rest of the MK3875 microcomputer is shut down.
The executable RAM is powered from an auxiliary power
supply input (V SB ) while operating in the Lower Power
Standby mode. When VSB is maintained at or above its
minimum level, data is retained in the executable RAM
memory with a very low power dissipation.
The MK3875 retains commonality with the rest of the
industry standard 3870 family of single chip microcomputers. It has the same central processing unit,
oscillator and clock circuits, and 64 byte scratchpad memory
array. Also, the 3870's sophisticated programmable binary
timer is included which provides three different operating
modes. Two pins on the MK3875 are dedicated to the Low
Power Standby mode and are designated as VSB and V BB .
The RESET line serves to reset the MK3875 and place it in a
protected state so that the contents of the Executable RAM
will remain unchanged when Vee is being powered down to
volts. All other pins on the MK3875 are identical in
function to corresponding pins on the MK3870, so that pin
compatibility is maintained. The MK3875 executes the
entire 3870 instruction set.
o
The MK38P75 microcomputer is the PROM based version
ofthe MK3875. It is called the piggyback PROM (P-PROM),M
because of its packaging concept. This concept allows a
standard 24-pin or 28-pin EPROM to be mounted directly
on top of the microcomputer itself. The EPROM can be
removed and reprogrammed as required with a standard
PROM programmer. The MK38P75 retains the pinout and
architectural features as other members ofthe 3870family.
The MK38P75 is discussed in more detail in a later section.
FUNCTIONAL PIN DESCRIPTION
XTL 1 andXTL2arethetimebaseinputstowhichacrystai
(2 t04 MHz), LC network, RC network, or an external singlephase clock may be connected. The time base network must
be specified when ordering an MK3875.
TEST is an input used only in testing the MK3875. For
normal circuitfunction this pin may be left unconnected but
it is recommended that TEST be grounded.
Vee is the power supply input +5 V.
VSB is the RAM standby power supply input.
V BB is the substrate decoupling pin. A .01 micro-Farad
capacitor is required which is tied between V BB and GND.
MK3875 ARCHITECTURE
The basic functional elements of the mask ROM MK3875
single chip microcomputer are shown in the block diagram
in Figure 1. A programming model is shown in Figure 2.
Much of the Mk3875 architecture is identical with the rest
of the devices in the 3870 fa m iIy. The sig nifica nt featu res of
the MK3875 are discussed in the following sections. The
user is referred to the 3870 FamilyTechnical Manual for a
thorough discussion of the architecture, instruction set, and
other features which are common to the 3870 family.
MAIN MEMORY
The main memory section on the MK3875 consists of a
combination of ROM and executable RAM.
There are four registers associated with the main memory
section. These are the Program Counter (PO), the Stack
Register (P), the Data Counter (DC) and the Auxiliary Data
Counter (DC1). The Program Counter is used to address
instructions during program execution. P is used to save the
contents of PO during an interrupt or subroutine call. Thus,
P contains the return address at which processing is to
resume upon completion of the subroutine or the interrupt
routine.
PO-2 - PO-7, Pl-0 - Pl-7, P4-0 - P4-7, and P5-0- P5-7 are
30 lines which can be individually used as either TTL
compatible inputs or as latched outputs.
The Data Counter (DC) is used to address data tables. This
register is auto-incrementing. Ofthe two data counters only
DC can access the memory. However, the XDC instruction
allows DC and DCl to be exchanged.
STROBE is a ready strobe associated with I/O Port 4. This
pin, which is normally high, provides a single low pulse after
The length of the PO, P, DC, and DCl registers for all
MK3875 devices is 12 bits. Figure 3 shows the amounts of
VIII-80
MK3875 BLOCK DIAGRAM
Figure 1
XTl1
XTL2
~
MEMORY ADDRESS BUS
4xB
EXECUTABLE
RAM
MAIN
CONTROL
LOGIC
ROM
TEST
I/O (6)
$
I/O (8)
I/O (8IsTROBE
I/O (8)
RESET
ROM and Executable RAM for each device in the MK3875
family.
available for use as general purpose 1/0 pins. Ports 1,4, and
5 are all a full 8 bits wide.
EXECUTABLE RAM
The schematic of an 1/0 pin and available output drive
options are shown in Figure 4.
The upper bytes of the total address space in all MK3875
devices are RAM memory. As with the ROM memory, the
RAM may be addressed by the PO and DC address registers.
The executable RAM may be accessed by all 3870
instructions which address main memory indirectly
through the Data Counter (DC) register. Additionally, the
MK3875 may execute an instruction sequence which
resides in the executable RAM. Note that this sequence
cannot be done with the scratch pad RAM memory, which is
the reason the term "executable RAM" is given to this
additional memory. The contents of the executable RAM
memory are preserved when the Low Power Standby mode
is in operation.
1/0 PORTS
The MK3875 provides 30 bits of bidirectional parallel 1/0.
These lines are addressed as Ports 0,1,4 and 5. In addition,
the Interrupt Control Port is addressed as Port 6 and the
binary timer is addressed as Port 7. The programming of
Ports 6 and 7 and the bidirectional 110 pins are covered in
the 3870 Family Technical Manual.
Since two pins are dedicated to serve the Standby Power
mode (V S8 ), port 0 has only the upper 6 bits, PO-2 - PO-7,
An output ready strobe is associated with Port 4. This flag
may be used to signal a peripheral device that the MK3875
has just completed an output of new data to Port 4. The
strobe provides a single low pulse shortly after the output
operation is completely finished, so either edge may be used
to signal the peripheral. STROBE may be used as an input
strobe simply by doing a dummy output of H '00' to Port 4
after completing the input operation.
STANDBY POWER MODE
On the MK3875, the contents of the on-chip executable
RAM can be saved when the Standby Power mode is
operative. The Standby Power mode allows the MK3875's
mai n power supply to drop all way down to 0 volts while the
on-chip executable RAM is powered from the auxiliary low
power supply input, V SB ' Thus, key variables may be
maintained within the MK3875 executable RAM during the
time that the rest of the microcomputer is powered down.
On the MK3875, two of the pins which are used as
bidirectional port pins on the MK3870 are used for the
Standby Power feature. Port 0, Bit 0 (PO-O), remains
readable and writeable although it is not connected to a
package pin. The logic level being applied to the auxiliary
VIII-81
II
3875 PROGRAMMABLE REGISTERS. PORTS AND
MEMORY MAP
Figure 2
CPU REGISTERS
I 0 PORTS
SCRATCH PAD MFMORY
BI~ARY
TIMER
ACCUMULATOR
PORT 7
A
7.--8 8ITS-. 0
7-4-8 BITs--. 0
SCRATCHPAD
OEC
OC1
HEX
R
o
INTERRUPT
CONTROL PORT
STATUS
REGISTEA
PORT 6
J
(W)
I~I+I+I
,az
74'-8 BITS-' 0
E A
V
T E R R
R R OR
y
C
,
Hl
11
KU
12
13
au
,.
G
N
Ol
15
Kl
INDIRECT
§
SCRATCHPAO
7 ..... 8 BITs-. 0
N l
T 0
W
PARAllEL
I D.PORTS
4"
PORT 5
10
S
,
C
N
5 BITS
11
HU
.. 0
A
12
C
13
14
0
15
16
17
61
3D
75
62
3E
63
3'
76
77
ADDRESS REGISTER
'~
PORT 4
!'SU
7....--8
BITS~
PORT 0
32
1J
0
.....-6 BITS--+-
PORT 1
0
I
MAIN MEMORY
PROGRAM
COUNTER
7~6BITS""2
11
87
. . - - '2 BITS - - . . .
STACK
REGISTER
87
11
......- 17 BITS.-.
OATA
COUNTER
locu
DC
!
87
'1
. . . - - 1") BITS---..
AUX DATA
COUNTER
I
.DCI U
l'
DC1
I
DC I L
87
.......--1]8ITS~
I
~
~
·~{i
ROM
DEC
0
1
HEX
0
1
2046
7FE
7FF
2047
ROM TOP
4030
4031
FSE
FBF
4032
4033
FCO
FC1
4094
40$5
FFE
FFF
MK3875122
MK3875/42 '
7
VII1-82
-8BITS_O
_MK3875/22
_MK3875/42
ROM TOP
MK3875 MAIN MEMORY
SIZES AND TYPES BY SLASH NUMBER
Figure 3
RAM
HEX
~R-A-M--'/ FFF
l=====<'-
2K
ROM
4K
ROM
3875/22
3875/42
DEC
FCO
FBF
4095
4032
4031
800
7FF
2048
2047
>
64 BYTES
EXECUTABLE RAM
00000000
\'-_
- _ _ _ _~Vr - - - - - ' I
All devices contain 64 bytes of scratchpad RAM
Data derived from addressing any locations other than
within the specified ROM or RAM space is not tested nor is
it guaranteed. Users should refrain from entering this area
of the memory map.
Device
Scratchpad
RAM Size
(Decimal)
MK3875122
MK3875/42
64 bytes
64 bytes
Address
Register
Size
(PO.P.DC.DC1 )
ROM
Size
(Decimal)
Executable
RAM
Size
12 bits
12 bits
2048 bytes
4032 bytes
64 bytes
64 bytes
power supply input (VSB)can be read at PortO. Bit 1 (PO-1).
Writing to PO-1 has no effect.
A capacitor (.01 microfarads) must be connected between
pin 3 (VBB) and ground. VBB is bonded directly to the
substrate of the MK3875. The purpose of the capacitor is to
decouple noise on the substrate of the circuit when V CC is
switched on and off.
It is recommended that Nickel Cadmium batteries (typical
voltage of 3 series cells =3.6V) be used for standby power.
since the MK3875 can automatically trickle charge the
three NiCads. If more than three cells. in series are used. the
charging circuit must be provided outside the MK3875.
Whenever RESET is brought low. the executable RAM is
placed in a protected state. Also the RAM is switched from
VCC power to the VSB power. When powering down. it may
be desirable to interrupt the MK3875 when an impending
power down condition is detected, so that the necessary
data can be saved before VCC falls below the minimum
level. After the save is completed, RESET can fall, which
prevents any further access of the RAM. The timing for this
power down sequence is illustrated in Figure 5A.
A second power down sequence is illustrated in Figure 5B.
and may be used if a special save data routine is not needed.
The EXT INT line need not be used. Note that for both cases
shown in Figures 5A and 5B, RESET must be low before
Vee drops below the minimum specified operating voltage
for the MK3875. This is to ensure that the contents of the
executable RAM are not altered during the power down
sequence.
There may be a set of variables stored in the RAM memory
which is continually updated during the tme when the
MK3B75 is in its normal operating mode. If a particular
variable occupies more than one byte of RAM, there can be
a problem if a reset occurs in response to an impending
power down condition during the time that the multi-byte
variable was being modified. If such a reset occurs, then
only part of the variable may contain the updated value,
while the rest contains the old value. An example of this
case would be when a double precision (2 byte) binary
number is being saved in the executable RAM. Suppose
that a new value of the number has been calculated in the
program, and that this new value is to replace the old value
contained in the executable RAM; note that a reset could
occur just after the program wrote one byte of the new value
VIII-83
II
1/0 PIN CONCEPTUAL DIAGRAM WITH OUTPUT BUFFER OPTIONS
Figure 4
OUTPUT
BUFFER
PORT
1/0
PIN
z
o
~
a::
:I
~
~
oIL
"
Z
o
u
a::
o
o
w
a::
Q
C
w
a::
~
a::
oIL
Q
C
g
a::
~
en
:I
CD
i!c
Q
OUTPUT BUFFER OPTIONS
(MASK PROGRAMMABLE)
VCC
6KOTYP.
STANDARD
OUTPUT
OPEl\! DRAIN
OUTPUT
DIRECT DRIVE
OUTPUT
Ports 0 and 1 are Standard Output type only.
Ports 4 and 5 m.ay both ba any of the..th_ output options (mask progremmable bit by bit)
The
STRoBE output is always configurad similar to a Direct Driva Output . .capt that it is capable of driving 3 TTL loads..
RESET and EXT INT may have Standard 6KU (typical) pull-up or may have no pull-up (mask programmable). These two inputs have Schmitt trigger
inputs with a minimum of 0.2 volts of hysteresis.
RESET and EXT INT do not have internal pull up on the MK38P75.
into the RAM. When power is restored following the
Standby Power mode, the double precision variable would
contain an erroneous value.
"set" is a good byte of data. While this method significantly
encumbers the data storage process, it eliminates the need
for a power fail interrupt which both reduces external
circuitry and leaves the external interrupt pin completely
free for other use.
This problem can be avoided ifthe external interrupt is used
to signal the MK3875 of an impending power down
condition. The user's system should be designed so that the
MK3875 can properly save all variables between the time
that the external interrupt occurs and RESET falls. If multibyte variables must be saved during the Standby Power
mode and it is not desirable to· use the external interrupt in
the manner described above, then each byte of a multi-byte
variable may be kept with an associated flag. The method of
updating a two byte variable would be as follows:
Often it is necessary to distinguish between an initial
power-on condition wherein there is no valid data stored in
the RAM (or where V SB has dropped below the minimum
required stand-by level) and a re-application of power
wherein valid RAM data has been maintained during the
power outage. One method of distinguishing between
these two conditions is to reserve several memory locations
for key words and checksums. When Vee is applied and
processor operation begins. these locations can be checked
for proper contents. However, this method may not be
perfectly accurate as those locations holding key codes may
be maintained even though V SB drops below its minimum
required level while other RAM locations may lose data. or
they could power up with the exact data required to match
the key codes. Also a checksum may be matched on
occasion even though RAM data has been corrupted. The
accuracy of this method is improved by increasing the
number of memory locations used and the variety of key
codes and or checksums used.
- Clear Flag Word 1
- Update Byte 1
- Set Flag Word 1
- Clear Flag Word 2
- Update Byte 2
- Set Flag Word 2
Now if RESET goes low during the update of a byte of a
variable. the flag word associated with that byte of data will
be reset. Any byte of the variable where the flag word is
SAVE ROUTINE REQUIRED. VSB > 3.2 VOLTS
Figure 5a
:-:!
--.J
Vce
.!.-
I .
-------'--1---+'. . ."'-.
.
VCC
SUSTAINED~PACITOR OR
BATTERY UNTIL RESET BROUGHT LOW
\lAIN POWER SUPPLY
l'AILURE DETECTED - .
I
}
I
....1.r-----
~
;,
~I--.L-/- :_ \ - -H-J' :
EXTINT
,
1
, ~'-------!nl-----tl'~;1I
DATA SAVE
--i
1
MUST
~~E
r-
1
ACCESS TO
RAM INHIBITED
HERE
,
•
f.-
EXECUTION
BEGINS AGAIN
.1
1
NO SAVE ROUTINE REQUIRED, VSB > 3.2 VOLTS
Figure5b
Vee ----------_~
MAiN POWER
FAILURE DETECTED
1
/.
----ifj\,-----.... .
\~-----Iff~-------JI
VIII-85
A more reliable method is the external VSB flip.flop. The
flip-flop is designed to power up in a known first state and
hold thatfirst state until forced into a second state. As long
as V SB is above the minimum operating level, the flip-flop
can hold the second state, but, if VSB drops below the
minimum level, the flip-flop will flip back to the first state.
Thus when power is initially applied or if VSB drops below
the minimum level during a Vee outage, the flip-flop will be
in the first state. The flip-flop output can be read through a
port pin by the processor when processor operation begins
to determine whether the RAM data is valid (second state)
or invalid (first state). If the flip-flop is found to be in the first
state it can be forced to the second state by the processor. If
it holds the second state, V SB is above the minimum level
(batteries are charged).
MK38P75 MAIN MEMORY
MK38P75 contains executable RAM in the main memory
map. The MK38P75 contains no on-chip ROM. Instead, the
memory address lines are brought out to the 28-pin socket
located directly on top ofthe 4O-pin package, so the external
ERPOM memory is addressed as main memory.
CONCEPTUAL DIAGRAM
Figure 6
FROM
38715 RElET
The MK38P75 is offered with two types of output buffer
options on Ports 4 and 5. These are the open drain output
buffer and the standard output buffer which are pictured in
Figure 4. The open drain version of the MK38P75 is
provided so that user-selected open drain port pins on the
MK3875 can be emulated prior to ordering those mask
ROM devices. Figure 9 lists which version(s) of the
MK38P75 has open drain output buffers and which has
standard output buffers in parentheses following the
specified MK38P75 part ordering number (MK9XXXX).
As can be seen from the block diagram in Figure 7, the
A conceptual diagram is shown in Figure 6.
FROM 3876
PORT 4 OR 15
PIN
MK38P75 1/0 PORTS
TO 38715
PORT PIN
There is one memory version of the MK38P75 and it is
designated as the MK38P75/02. The MK38P75/02.
contains 64 bytes of on-chip executable RAM. The
MK38P75/02 can emulate the following devices.
MK3875/22
MK3875/42
The MK38P75/02 cannot exactly emulate the MK3875/40
because of the 64 bytes of executable RAM in the upper
ROM space of the MK3875/40.
MK38P75 GENERAL DESCRIPTION
The MK38P75is the EPROM version of the MK3875. It
retains an identical pinout with the MK3875, which is
documented in the section of this data sheet entitled
"FUNCTIONAL PIN DESCRIPTION". The MK38P75 is
housed in the "R" package which incorporates a 28-pin
socket located directly on top of the package. A number of
standard EPROMs may be plugged into this socket.
The MK38P75 can act as an emulator for the purpose of
verification of user code prior to the ordering of mask ROM
MK3875 devices. Thus, the MK38P75 eliminates the need
for emulator board products. In addition, several MK38P75s
can be used in prototype systems in order to test design
concepts in field service before commiting to high-volume
production with mask ROM MK3875s. The compact size of
the MK38P75/EPROM combination allows the packaging
of such prototype systems to be the same as that used in
production. Finally, in low-volume applications, the
MK38P75 can be used as the actual production device.
Most of the material which has been presented for the
MK3875 in this document applies to the MK38P75. This
includes the description of the pin configuration,
architecture, and programming mode. Additional information is presented in the following sections.
Addressing of main memory on the MK38P75 is
accomplished in the same way as it is for the MK3875. See
Figure 8 for main memory addresses and for address
register size in the MK38P75.
MK38P75 EPROM SOCKET
A 28-pin ERPOM socket is located on top of the MK38P75
"R" package. The socket and compatible ERPOM memories
are shown in Figure 9. When 24-pin memories are used in
the 28-pin socket, they should be inserted so that pin 1 of
the memory device is plugged into pin 3 of the socket (the
24-pin memory should be lower justified in the 28-pin
socket).
The 28-pin socket has been provided to allow use of both
24-pin and 28-pin memory devices. Minor pin-out
differences in the memory devices must be accommodated
by providing different versions of the MK38P75.
Initially, the MK38P75 that is compatible with the MK2716
is available. The MK38P75 designed to accommodate the
28-pin memory devices will be available at a later date.
VIII-86
MK38P75 BLOCK DIAGRAM
Figure 7
XTl1
XTl2
EJ
MEMORY ADDRESS BUS
64 x B
EXECUTABLE
RAM
MAIN
CONTROL
LOGIC
ROM
$
1/0(6)
TEST
1/0 (8)
1/0 (8)STROBE
1/0 (8)
MK38P75 MAIN MEMORY MAP
Figure 8
RAM
HEX
DEC
64 BYTES
FCO
4095
4032
4031
INTERNAL
EXECUTABLE
RAM
FBF
800
, - - -7FF
II
2048
2047
I
I
I
I
I
EXTERNAL I
EPROM
I
~----~I
~~~
____________~~=-
MK38P75/02
Device
MK38P73/02
97310
Scratchpad
RAM Size
(Decimal)
Address Register
Size
PO. P. DC. DC1)
ROM
Size
(Decimal)
Executable
RAM
Size
64 bytes
12 bits
o bytes
64 bytes
VIII-87
MEMORY ACCESS TIMING:
MK38P75 "R" PACKAGE SOCKET PINOUT'
Figure 9
MK97413 (Open Drain Outputs)
Compatible Memories
2758
MK2716
2516
2532
MK97403 (Standard Outputs)
Competible Memories
2758
MK2716
2516
2532
A timing diagram depicting the memory access timing of the
MK38P75 is shown in the next table. The clock signal is
derived internally in the MK38P75 by dividing the time base
frequency by two and is used to establish all timing
frequencies. The WRITE signal is another internal signal to
the MK38P75 which corresponds to a machine cycle,
during which time a memory access may be performed.
Each machine cycle is either 4 clock periods or 6 clock
periods long. These machine cycles are termed short cycles
and long cycles. respectively. The worst case memory cycle
is the short cycle, during which time an op code fetch is
performed: This is the cycle which is pictured in the timing
diagram. After a delay from the falling edge of the WRITE
clock. the address lines beCOme stable. Data must be valid at
the data out lines of the PROM for a setup time prior to the
next falling edge of the WRITE pulse. The total access time
available for the MK38P75 version is shown as taas or the
time when address is stable until data must be valid on the
data bus lines. The eq~ation for calculating available
memory access time along with some calculated access
ti mes based on the Iisted time base frequencies is shown in
the following table.
MEMORY ACCESS .SHORT CYCLE OP CODE
FETCH MK38P75
Figure 10
WRITE
:
~
\
A,,-Ao
I
I
PREVIOUS ADDRESS
I
~
: Signal is internal to the MK38P75
6
t ... =time base fraq. -850 ns
(FROM ADDRES$'STA8LE)
4 MHz 3.5 MHz. 3 MHz ,2.5 MHz 2 MHz
650~s
825 ns
1.15 ps
1.55 ps
\
NEW ADDRESS
I
I
I
I
I
I
I
I
I
ACCESS
TIME
~ '\"
2.15 ps
VIII-88
ta.
I
I
I
~I
I
i
I
I
i
DATA
VAUDI
I
I
I
3875 TIME BASE OPTIONS
CRYSTAL SELECTION
The 3875 contains an on-chip oscillator circuit which
provides an internal clock. The frequency of the oscillator
circuit is set from the external time base network. The time
base for the 3875 may originate from one of four sources:
The use of a crystal as the time base is highly recommended
as the frequency stability and reproducability from system
to system is unsurpassed. The 3875 has an internal divide
by two to allow the use of inexpensive and widely available
TV Color Burst Crystals (3.58 MHz). Figure 12 lists the
required crystal parameters for use with the 3875. The
Crystal Mode time base configuration is shown in Figure
11.
1)
2)
3)
4)
Crystal
LC Network
RC Network
External Clock
The type of network which is to be used with the mask ROM
MK3875 must be specified at the time when mask ROM
devices are ordered. However, the MK38P75 may operate
with any of the four configurations so that it may emulate
any configuration used with a mask ROM device.
The specifications for the four configurations are given in
the following text. There is an internal 26 pF capacitor
between XTL 1 and GND and an internal 26 pF capacitor
between XTL 2 and GND. Thus, external capacitors are not
necessarily required. In all external clock modes the
external time base frequently is divided by two to form the
internal PHI clock.
Through careful buffering ofthe XTL1 pin it may be possible
to amplify this waveform and distribute it to other devices.
However, Mostek recommends that a separate active
device (such as a 7400 series TIL gate) be used to oscillate
the crystal and that the waveform from that oscillator be
buffered and supplied to all devices, including the 3875, in
the eventthata single crystal is to provide the time base for
more than just a single 3875.
While a ceramic resonator may work with the 3875 crystal
oscillator, it was not designed specifically to support the use
ofthis component. Thus, Mostek does not support the use of
a ceramic resonator either through proper testing,
parametric specification, or applications support.
CRYSTAL MODE CONNECTION
Figure 11
XTL2
XTL1
D
AT-CUT
VIII-89
CRVSTALPARAMETERS
Figure 12
a)
b)
c)
d)
Parallel resonance, fundamental mode AT-Cut
Shunt capacitance (Co) = 7 pf max.
Series resistance (Rs) = See table
Holder = See table below.
Frequency
Series Resistance
Holder
f = 2-2.7 MHz
Rs = 300 ohms max
HC-6
HC-33
= 2.8-4 MHz
Rs = 150 ohms max
HC-6
HC-18*
HC-25*
HC-33
f
*This holder may not be available at frequencies near the lower end of this range.
a
LC NETWORK
The LC time base configuration can be used to provide a less
expensive time base for the 3875 than can be provided with
a crystal. However, the LC configuration is much less
accurate than is the crystal configuration. The LC time base
configuration is shown in Figure 13. Also shown in the
figure are the specified parameters for the LC components,
along with the formula for calculating the resulting time
base frequency. The minimum value of the inductor which
is ~equired for proper operation of the LC time base network
is 0.1 millihenries. The inductor must have a factor which
is no less than 40. The value of C is derived from C external,
the internal capacitance of the 3875, CXTL' and the stray
capacitances, CS1 and CS2 ' CXTL is the at XTL1 and
capacitance looking into the, internal two port network
XTL2. CXTL is listed under the "Capacitance" section of the
Electrical Specifications. CS1 and CS2 are stray capacitances from XTL 1 to· ground and from XTL2 to ground,
respectively. C external should also include the stray shunt
capacitance across the inductor. This is typically in the 3 to 5
pf range and significant error can result if it is not included in
the frequency calculation.
LC MODE CONNECTION
Figure 13
XTL1
---
XTL2
f----
L
I
'I III
I
I
I
L _________ ~ ~---------CEXTERNAL
(OPTIONAL)
f=
VIII-90
2
7r
v-rE"
Variation in time base frequency with the LC network can
arise from one of four sources: 1) Variation in the value of
the inductor. 2) Variation in the value of the external
capacitor. 3) Variation in the value of the internal
capacitance of the 3875 at XTL 1 and XTL2, and 4) Variation
in the amount of stray capacitance which exists in the
circuit. Therefore, the actual frequency which is generated
by the LC circuit is within a range of possible frequencies,
where the range of frequencies is determined by the worst
case variation in circuit parameters. The designer must
select component values such that the range of possible
frequencies with the LC mode does not go outside of the
specified operating frequency range for the 3875.
network tied to the XTL2 pin, when XTL 1 is grounded. A
schematic picturing the RC clock configuration is shown in
Figure 14. The RC time base configuration is intended to
provide an inexpensive time base source for applications in
which timing is not critical. Some users have elected totune
each unit using a variable resistor or external capacitor thus
reducing the variation in frequency. However, for increased
time base accuracy Mostek recommends the use of the
Crystal or LCtime base configuration. Figure 15 illustrates a
curve which gives the resulting operating frequency for a
particular RC value. The x-axis represents the product ofthe
value of the resistor times the value of the capacitor. Note
that three curves are actually shown. The curve in the
middle represents the nominal frequency obtained for a
given value of RC. A maximum curve and a minimum curve
for different types of 3875 devices are also shown in the
diagram.
RC CLOCK CONFIGURATION
The time base for the 3875 may be provided from an RC
RC MODE CONNECTION
RC MODE
Figure 14
XTL2
XTL1
Vee
Q
?>
?
R
I
--L.
...,...
I
MINIMUM R = 4K n
-L
-
C = 26.5 pF ± 2.6pF + Cexternal
FREQUENCY VS. RC
Figure 15
4MHz1r------t_------~~~~--------+_----------t_----__i
3MHz
2MHz4-------+-----------+-----------+-----~~r.?~~----~
RC PRODUCT
1 x 10.7
2 x 10-7
V\II-91
2.5 x 10-7
CEXTERNAL
(OPTIONAL)
The designer must select the RC product such that a
frequency of less than 2 MHz is not possible taking into
account the maximum possible RC product and using the
minimum curve shown in Figure 15. Also, the RC product
must not allow a frequency of more than 4 MHz taking into
account the minimum possible Rand C and using the
Maximum curve shown. Temperature induced variations in
the external components should be considered in
calculating the RC product.
Positive Freq. Variation
= RC typical - RC minimum
RC typical
Negative Freq. Variation
due to RC Components
= RC maximum - RC typical
RC typical
Total frequency variation due to all factors:
387X-OO, --05
= +18 percent plus positive
Frequencyvariation from unitto unitdueto switching speed
and level at constant temperature and Vee = + or - 5
percent.
frequency variation due
to RC components
387X-10, -15
= +21 percent plus positive
frequency variation due
to RC components
=-18 percent minus negative =-21 percent minus
frequency variation due to
RC components
Frequency variation due to Vee with all other parameters
constant with respect to +5V =+7 percent to -4 percent on
all devices.
Frequency variation due to temperature with respect to 25
C (all other parameters constant) is as follows:
PART #
Total frequency variation due to Vee and temperature of a
unit tuned to frequency at +5V Vee' 25 C
VARIATION
387X-OO, --05
= + 13 percent
387X-OO, --05
387X-10, -15
+6 percent to - 9 percent
+9 percent to -12 percent
=(R max) (C external max + CXTL max)
Minimum RC
= (R min) (C external min + CXTL min)
387X-10, -15
= + 16 percent
EXTERNAL CLOCK CONFIGURATION
Variations in frequency due to variations in RC components
may be calculated as follows:
Maximum RC
negative frequency
variation due to RC
components
The connection for the external clock time base
configuration is shown in Figure 16. Refer to the DC
Characteristics section for proper input levels and current
requirements.
Refer to the Capacitance section of the appropriate 3875
Family device data sheet for input capacitance.
Typical RC = (R typ) (C external typ +
{CXTL max + CXTL min))
2
EXTERNAL MODE CONNECTION
Figure 16
XTL1
XTL2
I
NO CONNECTION
EXTERNAL
CLOCK
INPUT
VIII-92
MK3875, MK38P75
ELECTRICAL SPECIFICATIONS
OPERATING VOLTAGES AND TEMPERATURES
Dash
Operating
Operating
Temperature
Number
Voltage
Suffix
TA
VCC
+5V ± 10%
O°C -70°C
-00
+5V±5%
O°C -70°C
- 05
+5V ± 10%
-40°C - +85°C
-10
- 15
+5V ± 5%
-40°C - +85°C
See order information for explanation of part numbers.
ABSOLUTE MAXIMUM RATINGS*
-00, -05
-10, -15
Temperature Under Bias ................................. .
Storage Temperature .................................... .
Voltage on any Pin With Respect to Ground
(Except open drain pins and TEST) ....................... .
Voltage on TEST with Respect to Ground ................... .
Voltage on Open Drain Pins with Respect to Ground ......... .
Power Dissipation ....................................... .
Power Dissipation by anyone 1/0 pin ...................... .
Power Dissipation by all 1/0 pins .......................... .
-20°C +85°C
-65°C +150°C
-50°C to 100°C
-65°C to +150°C
-1.0Vto +7V
-1.0V to +9V
-1.0V to +13.5V
1.5W
60mW
600mW
-1.0Vto +7V
-1.0V to +9V
-1 .OV to 13.5V
1.5W
60mW
600mW
*Stresses above those listed under"Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation aftha device at
these or any other condition above those indicated in the operational sections of this specification is not implied, Exposure to absolute maximum rating and conditions for extended
periods may affect device reliability.
AC CHARACTERISTICS
TA, VCC within specified operating range
1/0 Power Dissipation < 1OOmW (Note 4)
SIGNAL
SYM
PARAMETER
-00,-05
MIN
MAX
-10,-15
MIN
MAX
XTL1
XTL2
to
Time Base Period, all clock modes
250
500
250
500
ns
tex(H)
tex(L)
External clock pulse width high
External clock pulse width low
90
100
400
400
100
110
390
390
ns
ns
t
Internal clock
WRITE
tw
Internal WRITE Clock period
1/0
tdllO
Output delay from internal
WRITE clock
0
tsllO
Input setup time to internal
WRITE clock
1000
STROBE
tl/O-s Output valid to STROBE delay
2to
2to
4t
6 t
4t
6t
3t
-1 ()()(}
RESET
tsL
STROBE low time
8t
-250
tRH
RESET hold time, low
6t
+750
tRPOC RESET hold time, low for power
clear
EXTINT
tEH
EXT INT hold time in active and
inactive state
powe,
supply
rise
time +5.0
6t
+750
2t
VIII-93
1000
0
1200
1200
3t
+250
12t
+250
3t
-1200
8t
-300
6t
+1000
UNIT NOTES
4MHz-2MHz
Short Cycle
Long Cycle
ns
50pF plus
one TTL load
ns
3t
+300
125<1>
+300
ns
ns
1/0 load =
50fF + 1 TTL load
STROBE load =
50pF + 3TTL loads
ns
powe,
supply
rise
time +5.5
ms
6t
+1000
2t
ns
ns
To trigger
interrupt
To trigger timer
II
AC CHARACTERISTICS FOR MK38P75
(Signals brought out at socket)
TA- Vee within specified operating range.
1/0 Power Dissipation :5 100 mW. (Note 2)
-00. -05
SYMBOL
PARAMETER
MIN
taas*
Access time from Address A,,-Ao
stable until data must be valid at DTDO
650
MAX
-10. -15
MIN
MAX
650
UNIT CONDITION
ns
<1>= 2.0 MHz
*See Table in Figure 10
CAPACITANCE
TA = 25°C All Part Numbers
SYM
PARAMETER
CIN
Input capacitance; 1/0 RESET, EXT INT,
TEST
CXTL
Input capacitance; XTL 1, XTL2
MAX
MIN
UNIT NOTES
10
pF
23.5
29.5
pF
-00.-05
-10,-15
unmeasured
pins grounded
DC CHARACTERISTICS
TA, V CC within specified operating range
1/0 Power Dissipation :5 l00mW (Note 4)
SYM
PARAME:rER
ICC
Average Power Supply Current
PD
Average Power Dissipation
VIHEX
External Clock input high level
2.4
5.8
VILEX
External Clock input low level
-.3
.6
IIHEX
External Clock input high current
IILEX
External Clock input low current
VIHI/O
Input high level, 1/0 pins
VIHR
VIHEI
VIL
VILRPT
MIN
Input high level, RESET
Input high level, EXT INT.
1/0 ports, RESET, EXT INT input
low level
RESET input low level to protect,
RAM during loss at VCC
MAX
MIN
MAX
UNIT NOTES
94
125
mA
Outputs Open (5)
440
575
mW
Outputs Open (6)
2.4
5.8
V
-.3
.6
V
100
130
pA
VIHEX=VCC
-100
-130
pA
VILEX=VSS
2.0
5.8
2.0
5.8
V
Standard Pull-Up (1,2)
2.0
13.2
2.0
13.2
V
Open Drain (1,3)
2.0
5.8
2.2
5.8
V
Standard Pull-Up(l, 2)
2.0
13.2
2.2
13.2
V
No Pull-Up (1,3)
2.0
5.8
2.2
3.8
V
Standard Pull-Up(l, 2)
2.0
13.2
2.2
13.2
V
No Pull-Up (1,3)
-.3
.8
-.3
.7
V
-.3
.4
-.3
.4
V
-1.9
mA
-.-----
IlL
-1.6
Input low current, standard pull-up
pins
VIN=0.4V
(2)
VIII-94
DC CHARACTERISTICS (Continued)
TA• Vee within specified operating range
I/O Power Dissipation:5 100 rnW (Note 4)
-00. -05
MIN MAX
SYM
PARAMETER
IL
Input leakage current. open drain pins
Reset and EXT INT inputs
With no pull-up resistor
10H
Output high current. standard
-100
Pull-Up pins
10HDD
-10. -15
MIN
MAX
+10
-5
+18
-S
UNIT NOTES
p.A
p.A
VIW13.2V
VIN=O.OV
(3)
-89
p.A
VOW2.4V
-30
-~5
p.A
VOW3.9V
Output high current
-100
-130
p.A
VOW2.4V
Direct Drive pins
-1.5
rnA
rnA
VOW1.5V
VOWO.7V
-1.3
-8.5
.11
.'
10L
Output low current. I/O ports
1.8
1.65
rnA
VOL=0.4V
10HS
STROBE Output High current
-300
-270
p.A
VOL=2.4V
10LS
STROBE output low current
5.0
4.5
rnA
VOL=0.4V
>
DC CHARACTERISTICS FOR STANDBY POWER PINS
Vcc, TA within operating range I/O Power Dissipation:5 100 rnW (Note 4)
-00, -05
SYMBOL
PARAMETER
VSB
Standby VCC for RAM
ISB
Standby Current
ICHARGE
Trickle charge available on
VSBwith VCC in operating
range.
-10.-1f>
MIN
MAX
MIN
MAX
3.2
VCC
MAX
3.2
VCC
MAX
UNIT NOTES
V
6
7.5
rnA
VSB ;:VSB MAX
3.7
5.0
rnA
VSB =VSB MIN
-lS
rnA
rnA
VSB;: 3.SV
VSB = 3.2V
-.7
-.8
-1 b
II
DC CHARACTERISTICS FOR MK38P75
(Signals brought out at socket)
TA' Vec within specified operating range, I/O power dissipation :5 100 rnW (Note 2)
-00. -05
SYM
PARAMETER
ICCE
Power Supply Current for EPROM
VIL
Input Low Level Data bus in
~.3
O.S
VIH
Input High Level Data bus in
2.0
5.8
IOH
Output High Current
IOL
Output Low Current
IlL
Input Leakage Current
MIN
MAX
-10,
MIN
~15
MAX
UNIT CONDITION
~lS5
rnA
~.3
O.S
V
2.0
5.S
V
~lS5
~100
~90
p.A
VoH =2.4 V
~30
~25
p.A
VoH :=3.9 V
1.8
1.65
rnA VoL=0.4V
10
VIII-95
10
p.A
Data Bus in Float
-
1.
2,
3,
4,
5,
6,
i!ilm and ET INT have internal Schmit triggers giving minimum .2V hysteresis.
RESer and EXT INT prgrammed with standard pull· up
~ or EXT INT programmed without standard pull· up
Power dissipation for 1/0 pins is calculated by I (Vee' VIL)lIIILIl ' I (Vee' VOH)lIIOHIl' I (VOL) IIOL)
ICC exclusive of Icharge'
.
Po exclusive of battery charging power, Battery char,gin9power dissipated inside the MK3875 (Vee' VSB) IIcharge)'
TIMER AC CHARACTERISTICS
Definitions:
Error
tpsc
=Indicated time value - actual time value
=tIP x Pr.escale Value
Interval Timer Mode
Single interval error; free running (Note 3) ••••..•••.••••••••••••••.•.•••••••••••••••••••••••••••••••• ±StlP
Cumulative interval error, free running (Note 3) ••••••.•.•........•.••.•••..•.•....•.•..•.......•..•••.••• 0
Error between two Timer reads (Note 2) ••••••••••••••••••••••••••••••••••.••••••••••••.•.•••••• ±(tpsc + tIP)
Start timer to stop Timer error (Notes 1, 4) .•.••..........•••••••..••.........•••.••.•.•... +tlP to - (tpsc + tIP)
Start Timer to read Timer error (Notes 1, 2) ••••.•••.•••••••••••••••••••••.•••••••••••••• -StlP to -(tpsc + 7tlP)
Start Timer to interrupt request error (Notes 1. 3) . ~ . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . • • . .. -2tlP to -StlP
Load Timer to stop Timer error (NoteJJ •. :.............................................. +tlP to -(tpsc + 2t to -(tpsc + St to -9t
PulaeWidth Measurement Mode
Measurement accuracy (Note 4) •••••••.••••••••••••••••••••••••••••••••••••••.•••••••• +t to -(tpsc +2t
Minimum pulse Vll,idth of EXT INT pin ••.•••••••••••.••••••••••••••••••••••••••••••••••••••.•••.••.••• 2t
Event Counter Mode
Minimum active time of EXT 1NT pin •.••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• 2t
Minimum inactive time of EXT INT pin ................................................................ 2t
NqIu:,
I. Alltl""" which eo:uailloading. SU!r1ing. or stopping the Timer are referenced from the end of the last machine cycle of the OUT 0,· OUTS instruction,
2. Alf tl""" which entail reeding the Timer ere referenced from the end of the last mechine cycle of the IN or INS instruction.
3. Alltl""" which entail the generation of In in1ern~p1 request are referenced from !he start of the machine cycle in which !he a~at. interrUpt request latch is sat,
Additional time
alapea ilthe interrUpt request occurs during I privileged or multlcycle instruction.
mev
4. Error may be cumulative if operation is ~idvelV performed.
VIII-96
AC TIMING DIAGRAM
Figure 17
External Clock
Internal cP Clock
Input capacitance; I/O, RESET, EXT INT,
I/O Port Output
STROBE
RESET
EXTINT
=('-----
ICPBIT~~>
ICPBIT2:J=
L
Note: All AC measurements are referenced to V 1L max., V 1H min., VOL (.Bv), or V OH (2.0v).
VIII-97
INPUTIOUTPUT AC TIMING
Figure 18
INTERNAL
WRITE
CLOCK
* CYCLE TIMI NG
SHOWN FOR
4MHz EXTER NAL
CLOCK
CYCLE TIMING
DEPENDS ON INSTRUCTION
n IJ'NOR'I
3!1S*
2/lS*
INS
OPCODE
FETCHED
I
PORT ADDR.
PLACED ON
DATA BUS
3/1S*
I
PORT DATA
DRIVEN ON TO
DATA BUS
I
'--'IL-
NEXT
OP CODE
FETCHED
X
/<
PORT PINS
2!1S*
ro-tSI/OA. INPUT ON PORT 4 OR 5
INTERNAL
WRITE
CLOCK
CYCLE TIMING
~-----~~~--------~~r------------++--------+----~DEPENDSONINSTRUCTION
3!1S*
3J.1S*
OUTOR
OUTS
OP CODE
FETCHED
PORT ADDR.
ON DATA
BUS
ACCUMULATOR
CONTENTS
ON DATA BUS
NEXT
OP CODE
FETCHED
PORT PINS
STAYS LOW
STROBF
(ACTIVE FOR PORT 4 ONLY)
FOR TWO WRITE
CYCLES
tI/O-S
B. OUTPUT ON PORT 4 OR 5
INTERNAL
WRITE
CLOCK
INS 0,1
FETCHED
BUS
FETCHED
PORT PINS
OUTS 0,1
FETCHED
ACC DATA
ON BUS
PORT PINS
C. INPUT ON PORT 0 OR 1
D. OUTPUT ON PORT 0, 1
VIII-98
STROBE SOURCE CAPABILITY
(TYPICAL AT VCC = 5V. TA = 25°C)
-15
Figure 19
s
o
U
A
C
E
-10
c
U
A
A
E
N
,.....
t....
-5
T
M
r--.
r--.
A
,..
r'"
OUTPUT VOL TAGE
STROBE SINK CAPABILITY
(TYPICALATVCC = 5V. TA = 25°C)
Figure 20
S
+100
I
N
-
K
C
~-
u
A
R
+50
.....
E
N
T
I'"
/
M
,I
A
1/
OUTPUT VOLTAGE
STANDARD I/O PORT SOURCE CAPABILITY
(TYPICAL AT VCC = 5V. TA = 25°C)
Figure 21
-1.5
s
o
U
A
C
I"
E
-1.0
l"'-
C
U
A
A
I"
.......
E
N
T
M
A
I"
-.5
r'"
OUTPUT VOL T AGE
DIRECT DRIVE I/O PORT SOURCE CAPABILITY
(TYPICAL AT VCC = 5V. TA = 25°C)
Figure 22
s
o
U
A
-10
C
E
c
U
A
A
E
-1'-0
-5
r-...
bo
N
T
M
i'"
,.....
J".
A
OUTPUT VOLTAGE
VIII-99
1'-
I/O PORT SINK CAPABILITY
(TYPICALATVCC = 5V. TA = 25°C)
Figure 23
+60
5
I
N
K
C
U
R
R
E
+50
+40
-
+30
N
T
M
... ~
+20
,.,..
A
+10
......
i-'"
"
OUTPUT VOLTAGE
MAXIMUM OPERATING TEMPERATURE VS.
I/O POWER DISSIPATION
Figure 24
100
...
50
, 00
200
~~rIe
300
400
r--
i'
500
CEFlAM'7C
r-
600
PDI/OMW
r-
1000
ORDERING INFORMATION
supply tolerance. For each customer specific code,
additional information defining I/O options and oscillator
options will be combined with the information described
in the generic part number to define a customer/code
specific device order number.
There are two types of part numbers for the 3870 family
of devices. The generic part number describes the basic
device type, the amount of ROM and executable RAM,
the desired package type, temperature range and power
GENERIC PART NUMBER
An example of the generic part number is shown below.
MK3875/ 2 2 P - I 0
-
~
l~powe, SoWly Tol",""
0=5V±10%
5 = 5V ±5%
.Operating Temperature Range
'--___ Package type
0= O°C - +70°C
1 = -40°C - +85°C
P = Ceramic
N = Plastic
'--_--1-. Executable RAM Designator
2 = 64 Bytes
ROM Designator
2 = 2K Bytes
4 = 4K Bytes
Basic Device Type
DEVICE ORDER NUMBER
An example of the device order number is shown below.
MK 18000 N - 0 5
II :
Powe' SoWlyTol,,,",,
0= +5V ± 10%
5 = +5V±5%
Operating Temperature Range
0= O°C - +70°C
1 = AO°C - +85°C
L---~~Package
Types
P = Ceramic
N = Plastic
'-------Customer/Code Specific Number
The customer/code specific number defines the ROM bit
pattern, I/O configuration, oscillator type, and generic part
type to be used to satisfy the requirement of a particular
customer purchase order. For further information on the
ordering of mask ROM devices, the customer should refer to
the 3870 Family Technical Manual.
VIII-101
1982/1983 MICROELECTRONIC DATA BOOK
-----
~-
...
-..
----~-
...
-~--
.. ----
...
MOSTEl(.
MICROCOMPUTER COMPONENTS
CMOS MICROCOMPUTER CLOCK/RAM
MK3805N/MK3806N
FEATURES
o
o
Real-time clock counts seconds, minutes, hours, date of
the month, day of the week, month, and year. Every 4th
year, February has 29 days.
24 x 8 RAM for scratchpad data storage
o
Simple Microcomputer interface
o
High speed shift clock independent of crystal oscillator
frequency
X1/CI 2
x23
GND 4
TTL Compatible (Vee
o
Low-power CMOS
o
lee S 2mA (Vee
'=
'=
7 SClK
6 I/O
5 CE
MK3805N
X1/Cl4
X2 5
GNO 6
7
8
16
15
14 vee
13 SClK
12 1/0
11 CE
10
9
PIN DESCRIPTION
Table 1
PIN
PIN NAME DESCRIPTION
3805N 3806N
Single byte or multiple byte (Burst Mode) data transfer
capability for read or write of clock or RAM data.
o
1
2
CKO 3
'"·'8'·"
Serial I/O for minimum pin count (8 pins)
o
o
PIN OUT
Figure 1
1
2
3
4
5
6
5V)
7
5 V)
8
3
4
5
6
11
12
13
14
CKO
X1/C1
X2
GND
CE
I/O
SCLK
Vee
Buffered Sytem Clock Output
Crystal or External Clock Input
Crystal Input
Power Supply Pin
Chip Enable for Serial I/O Transfer
Data Input/Output Pin
Shift Clock for Serial I/O Transfer
Power Supply Pin
o +3V S Vee S 9.5V
GENERAL DESCRIPTION
Many microprocessor applications require a real-time clock
and/or memory that can be battery powered with very low
power drain. The MK3805N/MK3806N are specifically
designed for these applications. The device contains a realtime clock/calendar, 24 bytes of static RAM, an on-chip
oscillator, and it communicates with the microprocessor via
a simple serial interface. The MK3805N/MK3806N are
fabricated using CMOS technology, thus insuring very low
power consumption.
The real-time clock/calendar provides seconds, minutes,
hours, day, date, month, and year information to the
microprocessor. The end of the month date is automatically
adjusted for months with less than 31 days, including
correction for leap year every 4 years. The clock operates in
either the 24 hour or 12 hour format with an AM/PM
indicator.
so that a wide variety of crystal frequencies can be
accommodated. The oscillator also has an output available
that can be connected to the microprocessor clock input. A
separately programmable divider provides several different
output frequencies for any given crystal frequency. This
feature can eliminate having to use a separate crystal or
external oscillator for the microprocessor, thereby reducing
system cost.
Interfacing the CLOCK/RAM with a microprocessor is
greatly simplified using synchronous serial communication.
Only 3 lines are required to communicate with the
CLOCK/RAM: (1) CE (chip enable), (2) I/O (data line) and (3)
SCLK (shift register clock). Data can be transferred to and
from the CLOCK/RAM one byte at a time or in a burst of up
to 24 bytes.
TECHNICAL DESCRIPTION
Figure 2 is a block diagram of the CLOCK/RAM chip. Its
main elements are the oscillator and divider circuit,
oscillator and clock control, the real-time clock/calendar,
static RAM, the serial shift register, and the command and
control logic.
The on-chip oscillator provides a real-time clock source for
the clock/calendar. It incorporates a programmable divider
IX-1
BLOCK DIAGRAM
EXTERNAL CLOCK INPUT
I
Figure 2
xllclrD~
OSCILLATOR
AND
DIVIDERS
REAL TIME CLOCK
i'-
~
•
~
~
CE
1
OSCILLATOR
AND
CLOCK CONTROL
DATA BUS
~
SCLK
CKO
....
110
SHIFT
REGISTER
.~
7
COMMAND
AND
CONTROL
LOGIC
""
7
24 x8 RAM
r;;ooRESS & CONTROL BUS
1
The shift register is used to communicate with the outside
world. Data on the I/O line is either input or output on each
shift register clock pulse when the chip is enabled. If the
chip is in the input mode, the data on the I/O line is input to
the shift register on the risi ng edge of SCLK. If in the output
mode, data is shifted out onto the I/O line on the falling
edge of SCLK.
The command and control logic receives the first byte input
by the shift register after CE goes active. This byte must be
the command byte and will direct further operations within
the CLOCK/RAM. The command specifies whether subsequent transfers will be data input or data output, and
which register or RAM location will be involved.
A control register provides programmable control of the
dividerfor the internal clock signal. the external clock signal,
the crystal type and mode, and the write protect function.
The real-time clock/calendar is accessed via seven
registers. These registers control seconds, minutes, hours,
day, date, month, and year. Certain bits within these
registers also control a run/stop function, 12/24 hour
format, and indicate AM or PM (12 hour mode only). These
registers can be accessed sequentially in Burst Mode, or
randomly in a single byte transfer.
The static RAM is organized as 24 bytes of 8-bits each. They
can be accessed either sequentially in burst mode, or
randomly in a single byte transfer.
POWER UP
A clock signal is necessary for correct power up, and it
should be noted that a delay exists between power up and
the correct power up state of the clock and control registers.
nATA TRANSFER
Data Transfer is accomplished under control of the CE and
SCLK inputs by an external microcomputer. Each transfer
consists of a single byte ADDRESS/COMMAND input
followed by a single byte or mUltiple byte (if Burst Mode is
specified) data input or output, as specified by the
ADDRESS/COMMAND byte. The serial data transfer
occurs with LSB first, MSB last format.
ADDRESS/COMMAND BYTE
The ADDRESS/COMMAND Byte is shown below:
7
6
5
4
3
2
A2
A1
o
AO~
As defined, the MSB (bit 7) must be a logical 1; bit 6 specifies
a Clock/Calendar/Control register if logical 0 or a RAM
register if logical 1; bits 1-5 specify the designated
IX-2
register(s) to be input or output; and the LSB (bit 0) specifies
a WRITE operation (input) if logical 0 or READ operation
(output) if logical 1.
rising edge of SCLK. and DATA bits are output on the falling
edge of SCLK.
A data transfer terminates if CE goes high. and the transfer
must be reinitiated by the proper ADDRESS/ COMMAND
when CE again goes low. The data I/O pin is high
impedance when CE is high.
BURST MODE
Burst Mode may be specified for either the Clock/
Calendar/Control registers or for the RAM registers by
addressing location 31 Decimal (ADDRESS/COMMAND
bits 1-5 logical 1). As before. bit 6 specifies Clock or RAM
and bit 0 specifies read or write.
DATA INPUT
=
Following the 8 SCLK cycles that input the WRITE Mode
ADDRESS/COMMAND byte (bitO =logical 0). a DATA byte
is input on the rising edge of the next 8 SCLK cycles (per
byte. if Burst Mode is specified). Additional SCLK cycles are
ignored should they inadvertently occur.
There is no data storage capability at location 31 in either
the Clock/Calendar/Control registers or the RAM registers.
SCLK and CE CONTROL
DATA OUTPUT
All data transfers are initiated by CE going low. After CE
goes low. the next 8 SCLK cycles input an ADDRESS/
COMMAND byte of the proper format. A SCLK cycle is the
sequence of a positive edge followed by a negative edge. For
data inputs. the data must be valid during the SCLK cycle. If
bit 7 is not a logical 1. indicating a valid CLOCK/RAM
ADDRESS/COMMAND. the ADDRESS/COMMAND byte
is ignored as are all SCLK cycles until CE goes high and
returns low to initiate a new ADDRESS/COMMAND
transfer. See Figure 3.
Following the 8 SCLK cycles that input the READ Mode
ADDRESS/COMMAND byte (bitO =logical 1). a DATA byte
is output on the falling edge of the next 8 SCLK cycles (per
byte. if Burst Mode is specified). Additional SCLK cycles
retransmit the data byte(s) should they inadvertently occur.
so long as CE remains low. This operation permits
continuous Burst Read Mode capability.
DATA TRANSFER SUMMARY
ADDRESS/COMMAND bits and DATA bits are input on the
A data transfer summary is shown in Figure 3.
DATA TRANSFER SUMMARY
Figure 3
I. SINGLE BYTE TRANSFER
SCLK-----'
~I~
______________~r-
II
DATA INPUT/OUTPUT
II. BURST MODE TRANSFER
SCLK-----'
~~L------------------------------------~Ir'~.------~
4
6
I I I
7
)>-----
DATA lID BYTE N
BYTE
SCLK
FUNCTION
N
n
CLOCK
8
72
2.
200
NOTES
1) Data input sampled on rising edge of clock
2) Data output changes on falling edge of clock
3) Rising edge of CE terminates operation and resets address/command
IX-3.
RAM
REGISTER DEFINITION
X4
X3 Xtal Mode
Primary Frequencies
CLOCK/CALENDAR
0
0
1
1
The Clock/Calendar is contained in 7 addressable/ writeable/
readable registers, as defined below.
Address
Function
0
1
0
1
Binary
Microprocessor
Baud Rate
Color Burst
2 22 , 221 , 220 Hz
8, 5, 4, 2.5, 2, 1.25, 1·' MHz
7.3728, 3.6864, 1.8432 MHz
3.5795 MHz
Range (BCD)
CRYSTAL DIVIDER PRESCALER
0
1
2
Seconds+Clock Halt Flag
Minutes
Hours/ AM-PM/12-24 Mode
3
Date
4
5
Month
Day
Year
6
00-59
00-59
00-23 or
01-12
01-28,29,
30,31
01-12
01-07
00-99
X2, Xl, and XO specify a particular prescaler divider
selection necessary to generate a 1 Hz frequency for the
Clock/Calendar-Refer to Table 2 for complete definition.
SYSTEM CLOCK OUTPUT
Data contained in the Clock/Calendar registers is in binary
coded decimal format (BCD).
Cl and CO designate the system clock output frequency
selected. The options are X, Xl2, X/4, and -2 kHz. When in
the Binary Mode and Cl, CO = '1', the output frequency is
2048 Hz. In any other mode, the output frequency is -2048
Hz. Refer to Table 3 for complete definition.
CLOCK HALT FLAG
WRITE PROTECT
Bit 7 of the Seconds Register is defined as the Clock Halt
Flag. Bit 7 = logical 1 inhibits the 1 Hz input to the
Clock/Calendar. Bit 7 is set to logical 1 on power-up to
prevent counting, and it may be set high or low by writing to
the seconds register under normal operation ofthe device.
AM-PM/12-24 MODE
Bit 7 ofthe Hours Register is defined as the 12 or 24 hour
mode select bit. When high, the 12 hour mode is selected. In
the 12-hour mode, bit 5 is the AM/PM bit with logic high
being PM. In the 24-hour mode, bit 5 is the second 10-hour
bit (20-23 hours).
Bit 7 of the Control Register is the WRITE PROTECT Flag. Bit
7 is set to logical 1 on power-up, and it may be set high or
low by writing to the Control Register. When high, the
WRITE PROTECT Flag prevents a write operation to any
internal register, including the other bits of the Control
Register. Further, logic is included such that the WRITE
PROTECT bit may be reset to a logic 0 by a Write operation
without altering the other bits of the Control Register.
CLOCK/CALENDAR/CONTROL BURST MODE
Address 31 Decimal of the Clock/Calendar/Control
Address space specifies Burst Mode operation. In this
mode, the 7 Clock/Calendar Registers and the Control
Register may be consecutively read or written. Addresses
above address 7 (Control Register) are non-existent; only
addresses 0-7 are accessible.
TEST MODE BITS
Bit 7 of the Date Register and Bit 7 of the Day Register are
Test Mode Bits utilized in testing the MK3805N/MK3806N.
These bits should be logic 0 for normal operation.
RAM
CONTROL REGISTER
The Control Register specifies the crystal mode/frequency
to be used, the system clock output frequency, and. the
WRITE PROTECT Mode for data protection. The Control
Register is located at address 7 in the Clock/Calendar/
Control address space.
765432
0
X3
X2
Xl
XO
The static RAM is contained in 24 addressable/writeable/
readable registers, addressed consecutively in the RAM
address space beginning at location O.
RAM BURST MODE
Address 31 Decimal of the RAM address space specifies
Burst Mode operation. In this mode, the 24 RAM registers
may be consecutively read or written. Addresses above the
maximum RAM address location are non-existent and are
not accessible.
CRYSTAL DIVIDER MODE
REGISTER SUMMARY
X4 and X3 specify the Crystal frequency divider mode
selected.
IX-4
A Register, Data Format summary is shown in Figure 4.
MICROCOMPUTER CLOCK/RAM
ADDRESS/COMMAND. REGISTER. DATA
FORMAT SUMMARY
Figure 4
2
,
f¥;iA
EK
4 IA 3 I A2 I A,
1Ao
I. ADDRESS/COMMAND FORMAT
7
I,
4
5
6
3
0
~
II. REGISTER ADDRESS
REGISTER DEFINITION
A. CLOCK
4
3
2
1 0
0
0
1 0 10 10
0
7
SEC
I,
MINI,
HR
I,
DATE I ,
MONTH I '
DAyl,
YEAR I '
CONTROL
CLOCK
BURST
I,
I,
6
5
0
0
1
1
1 0
1
I
I
0
1 0 1 0
1 01
0
0
o
1
0
0
o
1 0
0
0
0
1
0
0
0
0
I,
1 0
1
0
I'
l%l
,~
0
1 0 I'
1
0
0
r%l
21 1
0'-'21'24
00-23
0
I'
Or%l
f%l
I
I'
I'
I '
o
I,
I'
I,
I'
I
I' I'
0
0,- 07
0-99
RAM23
RAM
BURST
I
0
o 1
1
0
I
0
'0 YEAR
DATE
o
I
80
I
00
00
I
MONTH
u>1
YEAR
I
0'
0'
DAY
0
X
IWpl C, 1 Co I 4 I X31 X2 1 X, I Xo
0[:%1
RAM
D~TA
••
•
0
HR
I
0'
1
I
00
AO
'l%l
I' I ' I I' ' I ,~
I, 1 ' I' I' 1 ' I' I' 1:%1
' 1
1 T21 o
I
1
I'ODATEI
0,-,21 0
0
MIN
1~~pl HR
L%1
0
I
o
0
I
o
1
0'-28/ 29 1
0'-30 T,
0'-3'
1
0
SEC
00-591 0 1 '0 MIN
B.RAM
RAMO
4 3
'OSEC
,~
I, I, l%l
I'
7
00-591 CH 1
POWER
ON
RESET
I
RAMI
D:~A
IX-5
1
•
••
1
I I I I I
XX
XX
II
CRYSTAL FREQUENCY SELECTION
Table 2
X4 X3
X2
X1
XO
fXTAL (MHz)
Crystal Frequency
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
8.388608
8.388608
4.194304
4.194304
2.097152
2.097152
1.048576
0.032768
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
8.000000
5.000000
4.000000
2.500000
2.000000
1.250000
1.000000
0.031250
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
7.372800
7.372800
3.686400
3.686400
1.843200
1.843200
0.921600
0.028800
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
7.159040
7.159040
3.579520
3.579520
1.789760
1.789760
0.894880
0.027965
Comments
Power on condition
CLOCK OUTPUT SELECTION
Table 3
C1
CO
0
0
1
1
0
1
0
1
CKO
Output Frequency
Comments
fXTAL
fXTAL -:- 2
fXTAL -:- 4
Power on condition
2048 Hz
Binary mode
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS*
Voltage on V cc relative to GND ............................................................. -0.5 V to + 12.0 V
Voltage on any pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to + VCC + .5
Temperature under bias .................................................................... " -50°C + 95°C
Storage Temperature ................. " ., .................................................. -55°C to +125°C
·Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other condition above those indicated in the operational sections of this specification is not implied. Exposure to Absolute
Maximum Rating conditions for extended periods may affect device reliability.
DC OPERATING CONDITIONS
-40°C::::: TA ::::: + 85°C
SYMBOL PARAMETER
MIN
TYP
MAX
UNIT
NOTES
Supply Voltage
3.0
5.0
9.5
V
1
MAX
UNIT
NOTES
2.0
0.1
1.0
10.0
mA
mA
pA
pA
V
V
2
3
4
4
1,5
1
V
V
V
V
l(1oH=-l00pA)
l(l oL = 1.8 rnA)
l(1oH = -400pA)
1(lOL = 4.0 mAl
Vcc
DC ELECTRICAL CHARACTERISTICS
-40°C :::::TA ::::: + 85°C, Vcc = 5V ± 10%
SYMBOL PARAMETER
ICC1
ICC2
lu
ILO
V 1H
V 1L
V1HX2
VI/OH
VI/OL
V CKH
V CKL
Power Supply Current
Power Supply Current
Input Leakage Current, SCLK and CE
Output Leakage Current, I/O Pin
Logic "1" Voltage, All Inputs except Xl
Logic "0" Voltage, All Inputs
Logic "1" Voltage, X 2 Input
Output Logic "1" Voltage, I/O pin
Output Logic "0" Voltage, I/O pin
Output Logic "1 " Voltage, CKO pin
Output Logic "0" Voltage, CKO pin
MIN
-1.0
-10.0
2.0
0.8
3.5
2.4
0.4
2.4
0.4
NOTES:
1. All voltages referenced to GND.
2. Crystal/Clock Input frequency::: 8.4 MHz, outputs open.
3.
TYP
Crystal/Clock Input frequency::: 32,768 Hz, outputs open.
4. MeasuredwithVcc = 5.0V, O:::;V,S5.0V, outputs in high impedance state.
5. When X, is driven by an external signal. a pull-up resistor is required.
IX-7
III
AC ELECTRICAL CHARACTERISTICS
-40°C ::STA::S +85°C. VCC 5 V
± 10%
SYMBOL PARAMETER
CI
CliO
Cx
fx
tcss
tsCH
toss
tSOH
tsoo
tcoz
tSWL
tSWH
fSCLK
ts R• tSF
tCR' tCF
tCWH
tlNIT
MIN
Capacitance on Input pin
Capacitance on I/O pin
Capacitance on XI/CI and X2
Crystal frequency
CE to SCLKI set up time
SCLKI to CEI hold time
Input Data to SCLKI set up time
Input Data from SCLKI hold time
Output Data from SCLKI delay time
CEI to I/O high impedance
SCLK low time
SCLK high time
SCLK frequency
SCLK Rise and Fall Time
CKO Rise and Fall Time
CE high time
Delay from power
XTAL=27 kHz
up till power up
XTAL=1 MHz
states va Iid
TYP
MAX
UNIT
NOTES
6
10
12
12
8400
pF
pF
pF
6
6
6
7
7
27
1.0
1.0
1.0
100
300
kHz
1.7
1.7.12
1.7
1.7
1.7.8.9
1.7.8.9
f.LS
f.LS
f.LS
1000
500
1.95
1.95
DC
00
ns
ns
ns
f.Ls
00
f.Ls
250
1
50
kHz
500
150
ms
ms
2.0
10
9.10
f.LS
ns
f.LS
11
11
NOTES:
6. Measured as C :=.!.ill, with !:::.V = 3V, and unmeasured pins grounded.
10. tr and tf measured from O.BV to 2.0V
11. tlNIT is measured from the time Vee =4.5VandXTALinputisvalid until the
eN
7. Measured atVIH::;: 2.0VorVIL = O.8Vand 50 ns rise and fall times on inputs.
B. Measured at VOH " 2.4V and VOL" 0.4V.
9. Load Capacitance" 100 pF
power up states of the CLOCK/RAM registers are valid.
12. tSCH must follow the last rising edge ofSCLK during a write cycle in order to
allow time to complete a write to the internal register.
I/O TIMING DIAGRAM
Figure 5
r--tscH-"~I.~_-_-_-_-_tc_W_"::::_-_~_"~1
.
~----------------I~/
SCLK
liD
\
--JA'-___~DATA _ _ _--'I
COMMAND
__
' - - - - - INPUT
INPUT
WRITE DATA TRANSFER (n BITS)
IX-8
\~___
1/0 TIMING DIAGRAM (Cont.)
Figure 5
SCLK
~tSDD
I/O
~~~~\~
__
O_____
CO~MAN~
INPUT
____8__________
~n'~ATA~n_'1
CLOCK/RAM
_________n__
~/
OUTPUT
DRIVES I/O
READ DATA TRANSFER (n BITS)
II
ORDERING INFORMATION
There are two types of part numbers for the 3870 family of
devices. The generic part number describes the basic device
type, the amount of ROM and executable RAM, the desired
package type, temperature range and power supply
tolerence. For each customer specific code, additional
information defining I/O options and oscillator options will
be combined with the information describes in the generic
part number to define a customer/code specific device
order number.
GENERIC PART NUMBER
An example of the generic part number is shown below.
MK3805/ 00 N • 1 0
1I~_s~~To~,~,
L
Openm""
0= 5V± 10"10
t.In"""" .,"'.
Package type
N = Plastic
L......---~Executable RAM Designator
L -_ _ _ _
0= None
ROM Designator
0= None
'---------I~ BasiC Device Type
DEVICE ORDER NUMBER
An example of the device order number is shown below.
Ir
MKXXXXN ·05
:
1'<...."
So"", TO~"""
0= +5 V ± 10%
5 = +5V±5%
Operating Temperature Range
L......_ _ _~ Package Types
"--------l~
0'" O°C· +70°C
1 = -40°C . +85'o C
N = Plastic
Customer/Code Specific Number
The customer/code specific number defines the ROM bit
pattern, I/O configuration, oscillator type, and geileric part
type to be used to satisfy the requirement of a particular
customer purchase order. For further information on the
orderi ng of mask ROM devices, the customer shOuld refer to
the 3870 Family Technical Manual.
IX-10
MOSTEI(.
MICRO PERIPHERAL COMPONENTS
MK3807
Programmable CRT Video Control Unit (VCU)
FEATURES
o
PIN CONFIGURATION
Fully Programmable Display Format
Characters per data row (1 -2(0)
Data rows per frame (6-64)
Raster scans per data row (1-16)
A!
AD
HO
H!
H2
H3
o Programmable Monitor Sync Format
Raster Scans/Frame (256-1023)
"Front Porch"
Sync Width
"Back Porch"
Interlace/Non-Interlace
Vertical Blanking
R!
H4
H5
H6
o Direct Outputs to CRT Monitor
Horizontal Sync
Vertical Sync
Composite Sync
Blanking
Cursor coincidence
CSYN
H7/DR5
VSYN
DR4
Dee
DR3
V DD
DR2
Vee
DR!
HSYN
ORO
eRV
DBO
Bl
DB!
DB1
DB2
DB6
DB3
DBS
o Programmed via:
Processor data bus
External PROM
o BUS Oriented: Compatible with moSt microprocessors
o Standard or Non-Standard CRT Monitor Compatible
o Second source to SMC CRT 5037
o Refresh Rate: 60 Hz
ON-Channel Silicon Gate Technology
o Scrolling
Single Line
Multi-Line
GENERAL DESCRIPTION
o Cursor Position Registers
o Programmable Character Format
o
Programmable Vertical Data Positioning
o Balanced Beam Current Interlace
o Graphics Compatible
o Split-Screen Applications
Horizontal
Vertical
o Interlace or Non-Interlace operation
o TIL Compatibility
The Programmable CRT Video Control Unit (VCU) Chip is a
user programmable 40-pin n channel MOS/LSI device containing the logic functions required to generate all the
timing signals for the presentation and formatting of
interlaced and non-interlaced video data on a standard or
non-standard CRT monitor. The MK3807 VCU is a second
source to SMC CRT 5037.
With the exception of the dot counter, which may be clocked
at a video frequency above 25 MHz and is therefore not
recommended for MOS implementation, all frame
formatting, such as horizontal. vertical, and composite sync,
characters per data row, data rows per frame, and raster
scans per data row and per frame, are totally user
programmable. The data row counter has been designed to
facilitate scrolling. Refer to Table 1 for description of pin
functions.
IX-11
Programming is accomplished by loading seven 8-bit
control registers directly off an 8-bit bidirectional data bus.
Four register address lines and a chip enable line provide
complete microprocessor compatibility for program controlled set up. The device can be "self loaded" via an
external PROM tied on the data bus as described in the
OPERATiON section.
The MK3807 (VCU) may be programmed for an odd or even
number of scan lines per data row in both interlaced and
non-interlaced modes.
In addition to the seven control registers. two additional
registers are provided to store the cursor character and data
row addresses for generation of the cursor video signal. The
contents of these two registers can also be read out onto the
bus for update by the program.
Figure 1 shows a block diagram of the internal functional
components of the VCU.
DESCRIPTION OF PIN FUNCTIONS
Table 1
Name
Inputl
Outpu1 Func1ion
Pin No.
Symbol
25-18
DBO-7
Data Bus
CE
AO-3
I
I
1/0
9
OS
Chip Enable
Register
Address
Data Strobe
12
DCC
Dot Counter Carry
I
38-32
HO-6
0
7.5.4
R1-3
H7/DR5
Character
Counter Outputs
Scan Counter
Outputs
H7/DR5
RO
Scan Counter LSB
0
26-30
DRO-4
0
17
15
11
10
BL
HSYN
VSYN
CSYN
Data Row
Counter Outputs
Blank
Horizontal Sync
Vertical Sync
Composite Sync Output
16
14
13
CRV
VCC
VDD
Cursor Video
Power Supply
Power Supply
3
39,40.1.2
31
8
I
0
0
0
0
0
0
0
PS
PS
IX-12
Data bus. Input bus for control words from microprocessor
or PROM. Bi-directional bus for cursor address.
Signals chip that it is being addressed.
Register address bits for selecting one of seven control
registers or either of the cursor address registers.
Strobes DBO-7 into the appropriate register or outputs the
cursor character address or cursor line address onto the
data bus.
Carry from off-chip dot counter establishing basic character clock rate. Character clock.
Character counter outputs.
Three most significant bits ofthe Scan Counter; row select
inputs to character generator.
Pin definition is user programmable. Output is MSB of
Character Counter if horizontal line counter (REG.O) is 2128; otherwise output is MSB Of Data Row Counter.
Least significant bit of the scan counter. In the interlaced
mode with an even number of scans per data row. RO will
toggle at the field rate; for an odd number of scans per data
row in the interlaced mode. RO will toggle at the data row
rate.
Data Row counter outputs.
Defines non-active portion of horizontal and vertical scans.
Initiates horizontal retrace.
Initiates vertical retrace.
Composite sync is provided on the MK3807. This output is
active in non-interlaced mode only. Provides a true RS170 composite sync wave form.
Defines cursor location in data field.
+5 volt Power Supply
+12 volt Power Supply
r.0~;~~~==~~;~======;~~;;;;;;:::;:;;;=========----------
I'
DATABUSDBO-? L 25-18
5"1
~
C
.;';
G)
%I
l>
3:
SELR2
12
f~
______ ••
I
DOT COUNTER
CARRY
CURSORV ADDRESS
REGISTER
38-32
J••
VSVNcl
~
....
w
t:::
I' -LOC'D :SYNC I.
BL
=I
~'
~ 1-1- 1 UF·
CO.'A.A,,"
"R
i 1;J7.5.4
'
39.40.1.2
r,-.::.:
3 'CHIP ENABLE;
9 DATA STROBr
SCROLL
RESET
START
SELF LOAD
6
II
17
OPERATION
The design philosophy employed was to allow the
MK3807 Programmable CRT Video Control Unit (VCU) to
interface effectively with either a microprocessor based or
hardwire logic system. The device is programmed by the
user in one of two ways: via the processor data bus as part of
the system initialization routine, or during power up via a
Horizontal Formatting:
Characters/Data Row
PROM tied on the data bus and addressed directly by the
Row Select outputs of the chip (See Figure 2). Seven 8-bit
words are required to program the chip fully. Bit
assignments for these words are shown in Tables 2,3 and
4.The information contained in these seven words consists
of the following:
A 3 bit code providing 8 mask programmable character lengths from 20 to 132. The
standard device will be masked for the following character lengths; 20, 32, 40, 64, 72,
80, 96, and 132.
Horizontal Sync Delay
3 bits assigned providing up to 8 character times for generation of "front porch".
Horizontal Sync Width
4 bits assigned providing up to 16 character times for generation of horizontal sync
width.
Horizontal Line Count
8 bits assigned providing up to 256 character times for total horizontal formatting.
Skew Bits
A 2 bit code providing from a 0 to 2 character skew (delay) between the horizontal
address counter and the blank and sync (horizontal. vertical, composite) signals to
allow for retiming of video data prior to generation of composite video signal. The
Cursor Video signal is also skewed as a function of this code.
Vertical Formatting:
Interlaced/Non-interlaced
This bit provides for data presentation with odd/even field formatting for interlaced
systems. It modifies the vertical timing counters as described below. A logic 1
establishes the interlace mode.
Scans/Frame
8 bits assigned, defined according to the following equations: Let X = value of 8
assigned bits.
1) in interlaced mode-scans/frame =2X + 513. Therefore for 525 scans, program X
= 6 (00000110). Vertical sync will occur precisely every 262.5 scans, thereby
producing two interlaced fields.
Range = 513 to 1023 scans/frame, odd counts only.
2) in non-interlaced mode-scans/frame = 2X + 256. Therefore for 262 scans,
program X = 3 (00000011 ).
Range = 256 to 766 scans/frame, even counts only.
In either mode, vertical sync width is fixed at three horizontal scans (=3H).
Vertical Data Start
8 bits defining the number of raster scans from the leading edge of vertical sync until
the start of display data. At this raster scan the data row counter is setto the data row
address at the top of the page.
Data Rows/Frame
6 bits assigned providing up to 64 data rows per frame.
Last Data Row
6 bits to allow up or down scrolling via a preload defining the count of the last
displayed data row.
Scans/Data Row
4 bits assigned providing up to 16 scan lines per data row.
IX-14
ADDITIONAL FEATURES
MK3807 VCU Initialization:
millisecond). The timing sequence will begin one line scan
after the 1111 address is removed. In processor based
systems, self loading is initiated by presenting the 0111
address to the device. Self loading is terminated by
presenting the start command to the device which also
initiates the timing chain.
Under microprocessor control-The device can be reset
under system or program control by presenting a 1010
address on A3-0. The device will remain reset at the top of
the even field page until a start command is executed by
presenting a 1110 address on A3-0.
Via "Self Loading"-In a non-processor environment, the
self loading sequence is effected by presenting and holding
the 1111 address on A3-0, and is initiated by the receipt of
the strobe pulse (OS). The 1111 address should be
maintained long enough to ensure that all seven registers
have been loaded (in most applications under one
Scrolling-In addition to the Register 6 storage of the last
displayed data row a "scroll" command (address 1011)
presented to the device will increment the first displayed
data row count to facilitate up scrolling in certain
appl ications.
CONTROL REGISTERS PROGRAMMING CHART
Table 2
Horizontal line Count:
Characters/Data Row:
Total Characters/Line = N
DB2
DB1
DBO
000
o
0
1
010
o
Skew Bits
1
0
o
1
o
0
0
1
Scans/Frame
Vertical Data Start:
Data Rows/Frame:
Last Data Row:
Mode:
Scans/Data Row:
= 20
= 32
to 255 (DBO
= LSB)
Active Characters/Data Row
=40
= 64
=72
0
1
= 80
1
0
= 96
1
1
1
= 132
= N, from 1 to 7 character times (DBO = LSB, N =0 Disallowed)
= N, from 1 to 15 character times (DB3 = LSB, N =0 Disallowed)
I
Sync/Blank Delay
Cursor Delay
DB7
DB8
(Character Times)
1
1
1
Horizontal Sync Delay:
Horizontal Sync Width:
1
0
+ 1, N =0
0
1
2
2
0
0
1
2
8 bits assigned, defined according to the following equations:
Let X = value of 8 assigned bits. DBO = LSB)
1) in interlaced mode- scans/frame = 2X + 513. Therefore for 525 scans, program X = 6
(0000110). Vertical sync will occur precisely every 262.5 scans, thereby producing two
interlaced fields.
Range = 513 to 1023 scans/frame, odd counts only.
2) in non-interlaced mode-scans/frame = 2X + 256. Therefore for 262 scans, program
X = 3 (00000011).
Range = 256 to 766 scans/frame, even counts only.
In either mode, vertical sync width is fixed at three horizontal scans (= 3H)
N = number of raster lines delay after leading edge of vertical sync of vertical start position.
(DBO = LSB)
Number of data rows = N + 1, N = 0 to 63 (DBO = LSB)
N = Address of last displayed data row, N = 0 to 63, ie; for 24 data rows, program N = 23.
(DBO = LSB)
Register 1, DB7 = 1 established Interlace
Interlace Mode
Scans per data Row = N + 2. N =0 to 14, odd or even counts.
Non-Interlace Mode
Scans per Data Row
= N + 1, odd or even count, N = 0 to 15.
IX-15
SELF LOADING SCHEME
Figure 2
l l l l !
DBO'"
....
~
........
1
...L.
.....'"I""
.........
....... 1""
...
.... f'I
......
." ...."
. """
v
A3 CE
A1 A2
... t...
.......
DB7
Ao
MK3807
PROGRAMMABLE
CRT VIDEO CONTROL UNIT
(VCU)
"f'I
-
....
"'1"" RO
R1
R2
R3
Ao
A1
MK2716
SLOAD
(FROM SYSTEM)
A2
A3
CE
A4
+5
"''''''-AI ~~I ~ "T<>
"v
.... .., .............. ..,.
TO CHARACTER GENERATOR
OPTIONAL START-UP SEQUENCE
When employing microprocessor controlled loading of the
MK3807 VCU's registers. the following sequence of
instruction may be used optionally:
ADDRESS
1 1 1 0
1 0 1 0
000 0
o
1 0
1
1
0
COMMAND
Start Timing Chain
Reset
Load Register 0
The sequence of START RESET LOAD START is necessary
to ensure proper initialization of the registers.
This sequence is not required if register loading is via either
of the Self Load modes.
Load Register 6
Start Timing Chain
IX-16
REGISTER SELECTS/COMMAND CODES
Tabla 3
A3
0
0
0
0
0
0
0
0
A2
Description
0
0
0
0
1
1
1
1
A1
0
0
1
1
0
0
1
1
AO
0
1
0
1
0
1
0
1
Select/Command
Load Control Register 0
Load Control Register 1
Load Control Register 2
Load Control Register 3
Load Control Register 4
Load Control Register 5
Load Control Register 6
Processor Initiated Self Load
0
0
0
0
0
1
0
1
0
Read Cursor Line Address
Read Cursor Character Address
Reset
See Table 4
Up Scroll
0
o
o
o
Load Cursor Character Address'
Load Cursor Line Address'
Start Timing Chain
1
o
1
Non-Processor Self Load
NOTE':
Command from processor instructing
MK3807 VCU to enter Self Load Mode (via
external PROM)
Resets timing chain to top left of page. Reset is
latched on chip by OS and counters are held
until released by start command.
Increments address of first displayed data row
on page, i.e.; prior to receipt of scron
command-top line =0, bottom line =23. After
receipt of Scroll Command-top line = 1,
bottom line =O.
Receipt of this command after a Reset or
Processor Self Load command will release the
timing chain approximately one scan line later.
In applications requiring synchronous operation of more than one VCU the dot countet
carry should be held low during the OS for this
command.
Device will begin self load via PROM when OS
goes low. The 1111 command should be
maintained on A3-O long enough to guarantee
self load. (Scan counter should cycle through at
least once). Self load is automatically terminated and timing chain initiated when the all
"1's" condition is removed, independent of OS.
For synchronous operation of more than one
VCU; the Oot Counter Carry should be held
low when the command is removed.
During Self-Load. the Cursor Character Address Register (REG 7) and the Cursor Row Address Register (REG 8) are enabled during statesO'"
R3-RO Scan Counter outputs respectively. Therefore. Cursor data in the PROM should be stored at these addresses.
BIT ASSIGNMENT CHART
Tabla 4
HORIZONTAL LINE COUNT
=1;:::;:::;:1=;::1::;:Il..,~I
REG 0 , 1;,: ; : ,::::;:,
i
31
ill II I i
MODE INTERLACED/ H SYNC WIDTH H SYNC DELAY
NON-INTERLACED
REG
I
=?
21 XI
!\ i
I0
x-LI_~
I REG 6\L-X...LI
2
CURSOR CHARCTER ADDRESS
0
REG
2fTI I
REG 5
~-,-I
1--1 -I.\--L-I-,-I---11--,-1--,-1........
1. I
IX-17
I
7L-17.. 1-1-,-1--,-1--,--,--1. .1-1-,-I0---,1
CHARACTERS/DATA ROW VERTICAL DATA START
13 1
1.....\...I.--li---l--L.\I--,o\
iI I i
i
I
SCAN LINES/FRAME
I
'1716\ _ 1 1 lJ! \ REG 4\ I I I _ \
3
SCANS/DATA ROW
REG
I
LAST DISPLAYED DATA ROW
SKEW BITS DATA ROWS/FRAME
REG
and '000 of the
CURSOR ROW ADDRESS
X-LI_~1.....1...I.--li---l--L.I---,~I
X...LI
REG 8 L-I
MAXIMUM GUARANTEED RATINGS*
Operating Temperature Range •.•.......•..••..........•..•...•.....•••.....••....•.........•. O°C to + 70°C
Storage Temperature Range ...•..•.•.••..•.••.•••....•..•....•.•...•.•..•••.....••.••..•. -55°C to + 150°C
Lead Temperature (soldering, 10 sec.) ..•••.•••...•..•.....•....•.•..•.....•.........•••....••..•... + 325°C
Positive Voltage on any Pin, with respect to ground ....•...•..•...•..........•••.••...••..•........... + 18.0 V
Negative Voltage on any Pin, with respect to ground ••......•.....•.......•..••••....••................. -0.3 V
*Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or at any other
condition above those indicated in the operational sections of this specification is not implied.
NOTE: When powering this device from laboratory or system power supplies, it is important that the Absolute Maximum Ratings not be exceeded or device failure can result.
Some power supplies exhibit voltage spikes or "glitches" on their outputs when the AC power is switched on and off. In addition, voltage transients on the AC power line may
appear on the DC output. For eXample, the bench power supply programmed to deliver +12 volts may have large voltage transients when the AC power is switched on and off. If
this possibility exists it is suggested that a clamp circuit be used.
DC CHARACTERISTICS
(TA == ooe to 70°C, Vec == +5V ± 5%, VOO == +12V ± 5%, unless otherwise noted)
PARAMETER
INPUT VOLTAGE LEVELS
Low Level, VIL
High Level, VIH
OUTPUT VOLTAGE LEVELS
Low Level- VOL for RO-3
Low Level - VOL, all others
High Level- VOH for RO-3, OBO-7
High Level- VOH all others
MIN
TYP
Vce- 1.5
MAX
UNIT COMMENTS
0.8
Vec
V
V
0.4
0.4
V
V
IOL==3.2 ma
IOL=1.6 ma
IOw8OJ.ta
IOw40J.ta
250
10
p.A.
p.A.
VIWO.4V
15
40
15
pF
pF
pF
10
J.tA
100
70
mA
mA
2.4
2.4
INPUT CURRENT
Low Level, IlL (Address, eE only)
Leakage, IlL (All inputs except Address, CE)
O~VIN~VCC
iNPUT CAPACiTANCE
10
25
10
Data Bus, CIN
OS, Clock, CjN
All other, elN
DATA BUS LEAKAGE in INPUT MODE
lOB
POWER SUPPLY CURRENT
80
40
ICC
100
IX-18
0.4 ~ VIN ~ 5.25 V
AC CHARACTERISTICS
ctA = 70°C)
PARAMETER
MIN
DOT COUNTER CARRY
frequency
PWH
PWL
tp tf
0.5
35
215
DATA STROBE
PWDS
TYP
4.0
10
150ns
MAX
50
UNIT COMMENTS
MHz
ns
ns
ns
Figure 3
Figure 3
Figure 3
Figure 3
Figure 4
10J.!S
ADDRESS, CHIP ENABLE
Set-up time
Hold time
125
50
ns
ns
Figure 4
Figure 4
DATA BUS - LOADING
Set-up time
Hold time
125
75
ns
ns
Figure 4
Figure 4
125
60
ns
ns
Figure 4, CL =50pF
Figure 4, CL =50pF
125
ns
Figure 3, CL =20pF
750
ns
Figure 5, CL =20pF
DATA BUS - READING
TDEL2
TDEL4
5
OUTPUTS, HO-7, HS, VS, BL, CRV
CE-TDEL1
OUTPUTS: RO-3, DRO-5
TDEL3
*
AC TIMING DIAGRAMS
VIDEO TIMING
Figure 3
HO-7
H SYNC. V SYNC, BLANK.
CURSOR VIDEO.
COMPOSITE SYNC
...
T DEL1
---+-I
RESTRICTIONS
1. Only one pin is available for strobing data into the device via the data bus. The cursor X and Y coordinates are loaded into the chip by presenting one set of addresses and
are output by presenting a different set of addresses. Therefore. the standard WRITE and READ control signals from most microprocessors must be "NORed" externally
present a single strobe (OS) signal to the device.
2. In interlaced mode, the total number of character slots assigned tathe horizontal scan must be even to ensure that vertical sync occurs precisely between horizontal sync
pulses.
IX-19
LOAD/READ TIMING
Figure 4
TSET UP 1------------J...,
ADDRESS
CHIP ENABLE
DBO-7
LOADING IN
OF DATA
DBO-7
READING OUT
OF DATA
DS-----------------------------------,
SCAN AND DATA ROW COUNTER TIMING
Figure 5
HSYNC~
RO-3
DRO-5
--------------------------f----,------J
~TDEL3·
*RO-3 and DRO-5 may change prior to the falling edge of H sync
GENERAL TIMING
Figure 6
HORIZONTAL TIMING
£
START OF LINE N
START OF LINE N+1 - .
----In
JlL-----JLV.J.--JZZr----t:Z_'_/.L..I.ZZ~!.L._7'_'_O_'_Z.L..I.ZZ____'_Z...L.Z.I_I.ZZ----,-ZJ....-,ZZ,-,-Z...L.ZL-/.ZZ-LZ..,LLA
II(
1-rV/-r-70--r-Z-r-J/
ACTIVE VIDEO =
CHARACTERS PER DATA LINE ------_+oc,~..,.~
HORIZONTAL SYNC DELAY
(FRONT PORCH)
HORIZONTAL SYNC WIDTH
HORIZONTAL LINE COUNT=H
VERTICAL TIMING
START OF FRAME M OR ODD FIELD
E-----------------
foo
.
l .
START OF FRAME M+1 OR EVEN FIELD
SCAN LINES PER FRAME --------------------l.~1
~'________"_V.LJ.ZZ_'___/_'_7L_j77'--LZ...L.OL_l./_'___Z_'___'Z7<_J.Z_'_7_'_ZL-'-7Z-'---/..L-...ZZ,-"Z--,-7.L-ZL-LZZ--L-Z-,--,/7<-Li1~n'--_-L-VZZ
~
\11(
VERTICAL DATA
START
:=jll(
ACTIVE VIDEO =
DATA ROWS PER FRAME
IX-20
.1
~
VERTICAL
SYNC" 3H
COMPOSITE SVNCTIMING
Figure 7
Jl
I
----------~I
n
~--------~I
n
VOL~
:
I
'I
I
VOH
HSYNC
VSYNC
VoHi
__ ____________
~'
I
n
~--------~
rL
~----------
~.
I
VOL:
:....-- H
VOH:
n
~--------~
,
. : it
,
H
_I
I
~________~~H/2~
---+oj
:I
COMPOSITE
SYNC
VERTICAL SYNC TIMING
Figure 8
. . .f----------- FRAME M+I - - - - - - - - - - - -
- - - - - - - - - - - - - - FRAME M ------,---------I.~I
SCAN COUNTER IS HELD
H
~
1
3
6
7
9
1
SCANS/DATA
ROW
COUNTER-RO
N=9
RESE~TDURINGVBLANK
0
2
4
6
8
DATA ROW
COUNTER-DRO"\L_ _.........._ _
N=23
22
0
6
4
7
6
9
8
0
DATA ROW COUNTER
MA:' ~TAINS LAST COUNTDU!-.G V BLANK
-.lf
BLANK
3
2
2
23
..t
23-+-
fiJ..._____--'
JUUUUUUUUUl.·UUUUUUUUlllJBiANK
VERTICAL
-------SYNC
EXAMPU' ,.?ED ON NON-INTERLACED (REG 1, BIT 7 = 0). 24 DATA ROWS, 10 SCANS/DATA ROW
IX-21
II
1982/1983 MICROELECTRONIC DATA BOOK
Programmed Microcomputer Products
MOSTEI{.
3870 MICROCOMPUTER COMPONENTS
Serial Control Unit SCU20
FEATURES
SCU20
Figure 1
o Provides programmable remote I/O functions, real time
operational capabilities, and standardized network
communications on a 40 pin chip.
o Performs preprogrammed functions on command,
including:
• Byte input and output
• Bit input and output
• Set, clear, and toggle selected pins
• Data access from real time functions
o Performs real time preprogrammed functions, including:
• Data log on external interrupt, timer, or host control, up
to 63 bytes of data
• Five Event Counters driven from external interrupt,
timer or host control
o Up to 24 programmable I/O pins
o Allows user to network up to 255 SCUs on a single
communications channel
Figure 2
o Asynchronous serial data transmission
XTL1
o Selectable Baud rate (300, 1200, 2400, or 9600 Baud)
o Secure, Error resistant data link protocol
39 RESET
PO-O
38
PO-1
37
PO-2
o Requires single +5 volt supply
o Low power (275mW typ)
40 Vee
XTL2
5
EX'F.1iiii'.
SEiiAi5iN
36SRCLK
PO-3
6
35,51
STROBE
7
34 SO
P4-0
8
33 P5-0
P4-1
9
32.P5-1
31 P5-2
30 P5-3
INTRODUCTION
29 P5-4
28
The SCU20 serial control unit is a preprogrammed MK3873
single chip microcomputer. It is a general purpose remote
control/data acquisition unit, with 38 preprogrammed
functions available to the user.
P4-614
P4-7 15
PO-7
Communications with the SCU20 take place over an
asynchronous half duplex communications channel at 300,
1200,2400, or 9600 Baud. The communications protocol is
efficient and error resistant, and yet easy to implement on
the host system.
X-1
P5=5
27 P5-6
P5-7
16
25 BO
PO-6 17
24 B1
PO-5 18
23 RTS
PO-4 19
22 CTS
GND 20
21 NC
The SCU20 can be used for both monitoring and control
systems where remote intelligence is required. It can be
configured to provide many different input/output and data
acquisition functions through its 24 I/O pins. Such
intelligent functions as Data Log and Event Counters allow
many different applications that will not burden the host
system with constant update requirements.
SI -
Serial input. Receives serial asynchronous
data from the host.
SO -
Serial output. Transmits serial asynchronous data to the host.
RTS -
Request to send (output, active low).
FUNCTIONAL PIN DESCRIPTION
CTS -
Clear to send (input, active low).
The SCU20 is housed in a plastic 40 pin dual in-line
package.
RESET -
External reset (input, active low).
EXT. INT.-
External interrupt (input, active low).
SERADIN -
Serial address input/address mode (input,
active low. See SCU20 Address section).
BO, B1 -
Ba ud rate select.
Vee -
Power supply, 5 volts.
GND -
Power supply ground.
Figure 2 shows the location of each pin on the SCU20. The
following describes the function of each pin.
SCU20 PINOUT DEFINITION
XTL 1, XTL2 - Time base inputs for 3.6864 MHz crystal.
PO-O - PO-7 - SCU20 port 0 (Bidirectional, active low).
SCU20 address input or general purpose
data port (see SCU20 Address section).
SCU2 NETWORK
Data available strobe for port 4 (output
active low).
The SCU2 Network is a serial linked network of devices in
the SCU2 family. All communications are via a common
serial link using the SCU2 family communications protocol.
In this way, a distributed control facility may be easily
implemented from standard parts, and controlled by the
host computer via the serial link.
P4-0 - P4-7 - SCU20 port 4 (Bidirectional, active low).
General purpose data port.
P5-0 - P5-7 - SCU20 port 5 (Bidirectional, active low).
General purpose data port.
SRCLK -
Figure 3 illustrates the SCU2 Network.
Clock signal generated by internal Baud rate
,.. ................... +...... ..
·l:::f'..·'· .... · U L.... I .
SCU2 NETWORK
Figure 3
HOST
~---------------------.--~~-------------
SCU2x
SCU2x
#1
#2
---------SCU2x
#n
X-2
Each SCU2x in the network has an individual address to,
which it will respond. All SCU2x devices in the network are·
slave processors to the host, and are unable to initiate·
communications except in response to the host.
the only command that does not require a specific SCU2x
address as part of the command. It uses the system reset
address which is recognized by each device.
seU20 ADDRESS
When the system is initialized, all SCU2x devices are in the·
listen mode, and are performing no functions. The host will
issue an inquiry command to each device. Once all devices
have been queried, the host will issue commands to each
device to set up the particular operational parameters
required of it. When this has been done, the host may then
use the devices to control equipment, measure values, etc.,
by issuing commands and receiving responses.
The address to which the SCU20 responds may be
established in one of two ways.
The first mode is the Direct Strapped Address mode, and is
enabled by tying the SERADIN pin directly to ground. In this
mode, the SCU20 address is strapped at port O. Because of
this, port 0 is not available as a general purpose 1/0 port.
Unless issuing a response, the SCU2x is always in the listen
mode. If a command has been sent to an SCU2x, a response
is expected within a specific time period. If none is
forthcoming, it means that the command transmitted was
not successfully received by the device. In this case, the host
must take steps either to notify the operator or to retransmit
the command.
The second mode is the Serial Address Input mode. The
SERADIN pin is used to input the address as a serial 8-bit
stream from a shift register. SRCLK is used as a shift clock
for this operation. The STROBE signal is used at
initialization time to cause the address to be loaded into the
shift register before shifting begins. In the Serial Address
mode, port 0 becomes available for use as a general
purpose data 1/0 port.
If a system error occurs in the host, it may suspend
operation ofthe entire network by transmitting the network
reset command which causes all devices to be reset. This is
Figure 4 illustrates both methods of establishing the SCU20
address.
seU20 ADDRESS ESTABLISHMENT
Figure 4
DIRECT STRAPPED ADDRESS
~
16
SCU20
SERIAL ADDRESS INPUT
SCU20
~
ADDRESS
~
SEiiADiiii ..
SHIFT REGISTEFI
LD
37
SC
I
SRCLK
iii
X-3
--------_._------- --------
36
SCU20 COMMUNICATIONS
MODEM SIGNALS
The SCU20 communicates with the host computer over a
half duplex asynchronous serial link. The communications
protocol is simple, yet error resistant.
RTS and CTS are provided to facilitate handshaking with
modems. Just prior to responding to a valid command, RTS
will goto logic 1, indicating that the SCU20 is ready to send
data back to the host. CTS is an input to the SCU20 that is
tested after RTS goes active to determine if the SCU20 may
begin transmitting data.
The general form of the communication message is as
follows:
IHDR I ADDR I CMD I DATA I PATA I- - -
HDR -
-I
LRC
1
Message header. Hex '01' indicates a command
message from the host; Hex '02' indicates a
response from the SCU20.
ADDR - SCU20 Address. Indicates which SCU20 the
message is for, or originates from.
DATA - Any data that may be required by the particular
command.
Linear Redundancy Check.
The Mask Register provides a data mask that may be applied
to the input data before transmission to the master. The
mask is established once and may be used repeatedly
before being changed by establishing a new mask value. If a
pin is to be available upon read, the corresponding bit in the
mask register is set to 1, while a pin that is to be masked out
will have its mask bit set to O.
214 Bit Times
Message Separation
Rytp. m
t
Internal clock
STROBE
t l/O _s
output valid to ~ delay
3t
-1000
3t
+250
ns
1/0 load =
50 pF + 1 TTL load
tsL
STROBE low time
8t
-250
12t
+250
ns
STROBE load =
50 pF + 3TTL loads
tRH
RESET hold time, low
6t
+750
ns
t RPoe
RESET hold time, low for power clear
power
supply'
ms
RESET
I::~,.. ........ I
~""'''''''
"'1 ........1, ..... 1.... 0. .A.irl+h I",•• ,
...... " ..
•• '''' ...... v ... , ' ,... ............. "' ........ L'
UNIT NOTES
4 MHz - 2 MHz
3.6864 required for
standard baud
freque!'1c!es
2to
rise
time
+0.1
EXTINT
tEH
EXT INT hold time in active and inactive
state
X-6
6t
+750
ns
To trigger interrupt
CAPACITANCE
TA = 25°C
All Part Numbers
SYM
PARAMETER
CIN
Input capacitance; 1/0, RESET, EXT INT
CXTL
Input capacitance; XTL 1, XTL2
MIN
MAX
UNIT NOTES
10
pF
23.5
29.5
pF
MIN
MAX
unmeasured pins
grounded
AC CHARACTERISTICS FOR SERIAL 1/0 PINS
TA< V cc within specified operating range.
1/0 Power Dissipation :5 100 mW (Note 2)
SIGNAL
SYM
PARAMETER
SRCLK
tr(SRCLK)
Serial Clock Rise Time
60
ns
0.8 V - 2.0V
CL = 100 pf
it(SRCLK)
Serial Clock Fall Time
30
ns
2.4 V -0.4 V
CL = 100 pf
UNIT CONDITIONS
DC CHARACTERISTICS
TA< V cc within specified operating range.
I/O Power Dissipation :5 100 mW (Note 2)
SYM
PARAMETER
Icc
Po
MIN
MAX
UNIT
Average Power Supply Current
103
mA
SCU20
Outputs Open
Power Dissipation
485
mW
SCU20
Outputs Open
X-7
DEVICE
DC CHARACTERISTICS
TA' Vee within specified operating range
I/O Power Dissipation :5 100 rnW (Note 2)
SYM
PARAMETER
MIN
MAX
UNIT
V IHEX
External Clock input high level
2.4
5.8
V
V ILEX
External Clock input low level
-.3
.6
V
IIHEX
External Clock input high current
100
pA
V IHEX = Vee
IILEX
External Clock input low current
-100
pA
V ILEX = Vss
VIHI/O
I/O input high level
2.0
5.8
V
standard pull-up (1)
2.0
13.2
V
open drain (1)
2.0
5.8
2.0
13.2
V
No pull-up
2.0
5.8
V
standard pull-up (1)
2.0
13.2
V
No pull-up
-.3
.8
V
(1 )
V IHR
V IHEI
Input high level, RESET
Input high level, EXT INT
.V
CONDITIONS
standard pull-up (1)
V IL
I/O ports, RESET1, EXT INT' input low level
'lL
Input low current, I/O ports and EXT IN
-1.6
rnA
VIN = 0.4 V
'L
Input leakage current, RESET input
+10
-5
pA
pA
VIN = 13.2 V
VIN = O.OV
IOH
Output high current, I/O ports
-100
pA
V OH = 2.4 V
-30
pA
V OH = 3.9V
IOL
Output low current, I/O ports
1.8
rnA
VOL = 0.4 V
'OHS
STROBE Output High current
-300
pA
VOL = 2.4 V
'OLS
STROBE output low current
5.0
rnA
VOL = 0.4 V
X-B
DC CHARACTERISTICS FOR SERIAL PORT 1/0 PINS
TA • VCC within specified operating range
1/0 Power Dissipation :s; 100 mW (Note 2)
SYM
PARAMETER
MIN
MAX
UNIT
VIHS
Input High for 51
2.0
5.8
V
V llS
Input Low level for 51
-.3
.8
V
IllS
Input low current for 51
-1.6
rnA
IOHSO
Output High Current 50
-100
-30
pA.
pA.
IOlSO
Output Low Current 50
1.8
rnA
IOHSRC
Output High Current. 5RCLK
-300
pA.
=0.4 V
V OH = 2.4 V
VOL = 3.9V
VOL =0.4 V
VOH = 2.4V
IOlSRC
Output Low Current. 5RCLK
5.0
rnA
VOL
TEST CONDITIONS
Vil
=0.4 V
NOTES
1. RESET and EXT INT have internal Schmitt triggers giving minimum .2 V hysteresis.
2. Power dissipation for 1/0 pins is calculated by :!:(VCC • VIU ( IlL 1+ :!:(VCC - VOHI ( 10H 1+ :!:(VoU (lOLl
AC TIMING DIAGRAM
Figure 6
External Clock
Intemal Clock
110 Port Output
STROBE
Note: All AC measurements are referenced to Vil max., VIH min., VOL (.8v), or V OH (2.0v).
X-9
STROBE SOURCE CAPABILITY
(TYPICALATVCC = 5V, TA = 25°C) s
0
Figure 7
u
-15
R
C
E
-10
C
.....
U
R
R
..... 1-0.
E
.....
N
T
-5
.....
M
A
....
I'
OUTPUT VOL TAGE
STROBE SINK CAPABILITY
(TYPICALATVCC = 5V, TA = 25°C)
FigureS
S
I
N
K
+100
-
c
U
R
R
E
.... i""
+50
i..o"
N
T
i/
M
A
1/
1/
OUTPUT VOL lAGE
STANDARD 110 PORT SOURCE CAPABILITY
(TYPICAL AT VCC = 5V, TA = 25°C)
Figure 9
s
o
U
R
c
.....
E
c
......
.....
U
R
R
E
N
T
-.5
......
M
A
I'
OUTPUT VOL T AGE
110 PORT SINK CAPABILITY
(TYPICALATVCC = 5V, TA = 25°C)
Figure 10
+60
S
I
N
K
C
U
R
R
E
N
T
'50
'40
'30
M
A
+20
.,0
,.
.....
,.
_f-"
OUTPUT VOL TAGE
X-10
.....
MAXIMUM OPERATING TEMPERATURE VS. 1/0 POWER DISSIPATION
Figure 11
100
,...
P~
sr,c
50
100
200
300
400
I-
CfRAM'i;o
r-. .....
500
r-
600
1000
PDI/OMVV
ORDERING INFORMATION
An example of the device order number is shown below.
.pL:L _,
MK 95010 N - 1 0
S"W"ToOrn~
Operating Temperature Range
Package Types
0= 5V±10%
5 = 5V±5%
0= O°C - +70°C
1 = -40°C - +85°C
P = Ceramic
N = Plastic
' - - - - -..... CustomerICode Specific Number
X-11
1982/1983 MICROELECTRONIC DATA BOOK
68000, Z80, and 3870 Development System Products
MOSTEI{@
DEVELOPMENT SYSTEM PRODUCTS
RADIUSTM
Remote Development Station
FEATURES
RADIUS
Figure 1
o Microcomputer development with host computer
• Software development on the host
• Download to RADIUS
• Hardware debug and software integration on RADIUS
o
Utilizes standard Mostek SDE series AIM modules
o
Host software supplied
• Preconfigured for selected hosts
• Reconfigurable for other hosts
o
Upload/download performed with error tolerant protocol
o
Emulation possible while disconnected from the host
o
Serial I/O Baud rate up to 9600
o
Supports optional line printer and PROM programmer
o
Self-diagnostic test
INTRODUCTION
Mostek RADIUS - Remote Access Development and
Integration 1Lc0mputer System - is a state-of-the-art
microcomputer development system, designed specifically
to be used in a host computer environment. RADIUS
provides software development capability via the host
computer and hardware development and software
integration using the advanced in-circuit-emulation capability of Mostek AIM modules.
In Local Mode, the user can:
• Set optional Baud rates and special RADIUS control
characters
• Perform self diagnostics on RADIUS
In Utility Mode, the user can:
RADIUS is installed between the user's CRT terminal and
the host computer via an ASCII RS-232 serial interface. See
Figure 2. It can be operated in any of three modes:
Transparent, Local or Utility.
• Run the host components of the RADIUS Utility
Packages (i.e. AIM-Z80SE, AIM-7XE, Line Printer
Utility, PROM Programmer Utility, etc.).
• Perform hardware debug and software integration.
In Transparent Mode, the user can:
RADIUS has no mass storage. Instead it uses the mass
storage capabilities of the host. Once the user's target
program is downloaded, the user has the option of
disconnecting the RADIUS from the host. This allows the
user to save connect time and long distance charges.
• Perform any function that can be performed on the
host computer. RADIUS becomes completely transparent to the user.
XI-1
RADIUS SYSTEMS CONFIGURATION
Figure 2
HOST
PROM PROGRAMMER
(OPTIONAl)
CRT
RADIUS
TARGET
. BOARD
RADIUS can be configured in a single-user environment or
in a multi-user environment, in which several RADIUS
units are connected to an appropriate host and operated
simultaneously, performing entirely separate jobs. This
configuration supports the development of multiple
microprocessor/microcomputer systems. See Figure 3.
supply compartment on the left and the processing
compartment on the right. The processing compartment
can house up to five boards: a zao CPU/Memory board, two
AIM modules boards, and two slots for future expansion.
The CPU/Memory board contains:
DEVELOPMENT SYSTEM
• Z80CPU
• 64 Kbyte internal systems memory
• Four SIO ports;
- one dedicated to user terminal, one to the host
computer, and two for optional printer and PROM
programmer
- RADIUS supports 11 standard Baud rates from 50 to
9600 Baud
RADIUS is a cost effective microcomputer development
tool. It consists of an integrated cabinet, power supply, I/O
panel, and a Z80 based processor module with four serial
I/O ports.
RADIUS is supplied with a host communications software
package configured for several popular mini/microcomputer systems. (See ordering information.) A user
rehostable version is available for other host computers.
Additional preconfigured versions of the RADIUS host
software will be provided in the future.
RADIUS HARDWARE FEATURES
zao
RADIUS consists of a structural foam cabinet,
CPU/Memory/IO board, and a power supply board. The
user can add AIM-Z80BE or AIM-7XE modules to RADIUS
to perform the full range of real time in-circuit emulation
needed for hardware development and softWare integration. Future AIM products will be completely supported
on RADIUS.
The cabil1et is divided into two compartments: the power
RADIUS SOFTWARE FEATURES
• Local mode to set options on RADIUS and to perform
local diagnostics
• Most link parameters set at host configuration time
• Full AIM command set available
• AIM packages can run command files from the host
• AIM packages can log all terminal output to the host
• Progress of download/upload indicated on CRT
• Protocol re-transmits messages upon line error
• Self-explanatory error messages
• Translators to convert TEKHEX, F8HEX, and INTELHEX
object formats to Mostek HEX
• Local PROM programming (optional)
• Local printing (optional)
• Self diagnostic test
XI-2
RADIUS local mode provides the following commands:
SPECIFICATIONS
•
•
•
•
•
•
The power supply board has single phase AC input at47 Hz
to 63 Hz for the following voltage ranges:
• 95 Vto 132 V
• 190 V to 264 V
HELP
PORT
MEMORY
OPTIONS
DIAGNOSE
QUIT
The approximate dimensions are:
• Width: 9.2"
• Height: 10.8"
• Depth: 12.6"
RADIUS INSTALLATION IN A MULTI-USER ENVIRONMENT
Figure 3
HOST
CRT
MODEM
SOFTWARE
OEVELOPMENT
STATIONS
RAOIUS
RADIUS
RADIUS
~~------~~
D
D
D
CRT
CRT
CRT
HARDWARE/SOFTWARE
DEVELOPMENT STATIONS
PROM
PROGRAMMER
(OPTIONAL)
HARDWARE/SOFTWARE
DEVelOPMENT STATION
VIA MODEM
XI-3
ORDERING INFORMATION
For detailed ordering information refer to the Development
System Products Ordering Guide.
XI-4
MOSTEI(.
DEVELOPMENT SYSTEM PRODUCTS
AIM-Z80BE
Application Interface Module
FEATURES
AIM-Z80BE PRODUCTS
Figure 1
o Direct interface to Mostek's MATRIX-80S OS, SYS-80F,
and RADIUS development systems
o
In-circuit emulation of the Z80 microprocessor
o
Real-time execution (1-6 MHz with no wait states)
o
Flexible breakpoints (one hardware, eight software, and
one timer)
o
Single-step execution
o
16 K bytes of emulation RAM
o
Memory mappable into target or AIM system memory in
256 byte blocks
o
Illegal write-to-memory detection
o
Non-existent memory mapping and access detection
o
Forty-eight-channel-by-1024-words history memory for
tracing bus events
o
T-state timer to measure execution time
o
English-oriented command structure
o
Disassembly of instructions
o
System configuration parameters can be saved for future
use
GENERAL DESCRIPTION
AlM-ZSOBE is an advanced development tool which
provides debug assistance for both software and hardware
via in-circuit-emulation of the Z80 microprocessor. Use of
the AIM-Z80BE is transparent to the user's final system
configuration (referred to as the "target"). No memory space
. or user ports are used, and all signals, including RESET INT,
and NMI are functional during emulation. No memory wait
states are required.
Single-step circuitry allows the user to execute target
instructions one at a time to see the exact effect of each
instruction. Single step is functional in both ROM and RAM.
Up to 16 K bytes of emulation RAM can be used to emulate
the target microprocessor RAM or ROM. Thus, debugging
can begin before the user system is completely configured
with memory.
Breakpoint-detect circuitry allows real-time execution to
proceed to any desired point in the user's program and then
terminate execution. All CPU status information and
register contents can be displayed for the user and saved for
later continuation of execution or single-stepping. Realtime execution may be terminated by the user at any time.
EVENT and DELAY counters associated with the hardware
breakpoint give added flexibility for viewing the exact point
of interest in the user's program.
A forty-eight channel history memory records up to 1024
bus transactions. The address bus, data bus, control signals,
and 18 external probes may be logged into the history
memory and later displayed by the user.
XI-5
AIM-Z80SE SLOCK DIAGRAM
Figure 2
TARGET
SYSTEM
CONTROL MODULE
I
BUFFER
HISTORY MODULE
II EM~':~ION I
I
r-;:::::~ir~~ir~:::::;l
J. ~ II 11. 11 .H 1r .J.1 1 I
I
BREAKPOINT
DETECT
11
EXECUTION
CONTROL
il
JL
INTERFACE
RAM
ii
I
MEMORY
CONTROL
Ii
BUFFER
LATCH
I
TIMER
~I
24-81T
COMPARE
.....----,
EVENT
COUNTER
II
BUFFER
II
II
PORT
DECODE
HISTORY
CONmOl
I
iT
41
II
JL
DELAY
COUNTER
I
ADDRESS/CONTROL BUS
SLOCK DIAGRAM DESCRIPTION
logging elapsed time and generating the timer breakpoint.
The Z80 emulation system is composed of two boards, the
Control Board and the History Board, as shown in Figure 2.
These boards are attached to a Buffer module which
contains the target CPU and piugs directiy into the target
system CPU socket. Address, data, and control signals are
buffered by the Buffer module and cabled to the Control and
History Boards installed in the development system.
USING THE AIM-Z80SE
The Control Board has the circuitry for detecting the
breakpoint condition(s) and forces program execution to
begin in a separate System Interface RAM. The System
Interface RAM is loaded with an interface program and is
shadowed into the target memory space. This control
program makes the target CPU a slave to the development
system. When the user desires to resume execution of his
program, the control program activates the execution
control circuit and execution resumes at the desired
address. The Control board contains 16 K bytes of emulation
RAM, which may be mapped into any address space
required by the target system. Alternatively, if the user's
system has memory available, he may use that as his target
memory instead of the memory on the Control board.
The History board has a 24-bit comparator circuit, an EVENT
counter, and a DELAY counter to detect a hardware
breakpoint condition. The 48-channel-by-1024-word history RAM is controlled by the History control circuit.
The Timer circuit is used to count target processor clocks for
The Control and History boards of AIM-Z80BE are installed
directiy into the deveiopment system. Tu I;umpieie ihe
emulation system the Buffer module is used as a buffer
interface between the first two boards and the target
system's Z80 CPU socket.
The program which controls the AIM-ZooBE emulator
system is AI MZoo. After execution of AIMZ80 is started, the
program takes control ofthe AIM-ZooBE em ulation system.
The user can then initialize the target system and use the
AIMZ80 commands to load, test, and debug the target
program.
AIMZ80 SOFlWARE
AIMZ80 is the software which operates the AIM-Z80BE
emulation system in the Mostek MATRIX-80SDS or SYS80F disk system or the RADIUS development tool. Target
system programs may be developed on a Mostek disk
system by use of the appropriate assembler. Programs may
be developed for RADIUS cross products supplied by
Mostek or other vendors. The AIM software is supplied on a
variety of media for use with Mostek. disk-based
development systems and with different host systems for
RADIUS. The commands available in AIMZ80 are
summarized below. Each command also has a "short form"
which allows abbreviated input with fewer keystrokes.
XI-6
BATCH
BREAK
CLEAR
COpy
DISABLE
DISASSEMBLE
DUMP
ENABLE
EXECUTE
FILL
GET
HEXADECIMAL
HELP
HISTORY
INIT
LOCATE
LOG
MAP
MEMORY
OFFSET
PORT
QUIT
RAMTEST
REGISTER
STATUS
STEP
TRACE
TRANSPARENT
VERIFY
Read AIM commands from a file
Display and set breakpoints (S software, 1 hardware, and 1 timer breakpoint)
Clear one breakpoint or all breakpoints
Copy one block of memory to another block
Disable target CPU interrupts
Display and/or update instructions
Dump a block of memory to a file
Dump the memory map to a file
Enable target CPU interrupts
Start or continue execution of the target program
Fill memory with a data byte
Load a target program into memory
Load the target memory map from a file
Perform hexadecimal arithmetic
Display a menu of commands for the user
Set history logging options
Reinitialize target handshake
Locate a pattern in a memory block
Log all console output to a file
Map the block of memory as target supplied, AIM system supplied, or nonexistent, and write protected or not write protected
Display and/or update memory
Set an offset value for relative module debugging
Display and update a port on the target CPU
Output a value to a port without reading it
Return to the resident operating system
Perform a test on the target RAM
Display and/or update the target CPU registers
Display the current status of the AIM system
Perform a single or multi-step execution
Display the contents of the history RAM
Allows the RADIUS user to temporarily access the host
Verify the contents of a block of memory with another block or with a file.
SPECIFICATIONS
clock, RESET, INT, NMI, and DATA signals.
4. The signals Ml, MREQ, RD, and WR have a maximum
of 25 nanoseconds added propagation delay.
5. The input signals RESET, INT, and NMI have a
maximum of 45 nanoseconds propagation delay.
Target operating frequency: 1 to 6 MHz (MK7S204)
Target interface: all signals meet the specifications for the
ZSO with the following exceptions:
1. The output low voltage is 0.5 V max at 1.S mA for the
ADDRESS, DATA IORQ, RFSH, HALT, and BUSAK
signals.
2. The input low current is 400 microampsmaxforthe PHI
clock, RESET, INT, NMI, and DATA signals.
3. The input high current if 20 microamps for the PHI
Target system power requirements (maximum): +5 V ±5%
@ 600 milliamps
System compatibility:
RADIUS
MATRIX-SO/SDS, SYS-SOF, or
Operating temperature range; 0 to +50 degrees C
ORDERING INFORMATION
For detailed ordering information refer to the Development
System Products Ordering Guide.
XI-7
XI-8
MQSI'E1{
DEVELOPMENT SYSTEM PRODUCTS
AIM-7XE
Application Interface Module
FEATURES
AIM-7XE
Figure 1
o Direct interface to Mostek's MATRIX-80/SDS, SYS-80F,
and RADIUSTM development systems
o
In-circuit emulation of all MK3870 and MK3873 family
microprocessors (does not include piggy-back parts)
o
Real-time execution (1-4 MHz with no wait states)
o
Flexible breakpoints (one hardware, eight software, and
one timer breakpoint) and any number of manuallyinserted breakpoints
o
Single-step execution
o
4 K bytes of emulation RAM
o
Option of on-board oscillator or user clock
o
Illegal write-to-memory detection
o
Forty-eight-channel-by-1024-words history memory for
tracing bus events
o
Event counter and delay counter for monitoring bus
events
o
T-state timer to measure execution time
o
English-oriented command structure
o
Disassembly of instructions
Breakpoint-detect circuitry allows real-time execution to
proceed to any desired point in the user's program and then
terminate execution.
All CPU status information and registers can be displayed
for the user and saved for later continuation of execution or
single-stepping. Real-time execution may be terminated by
the user at any time. EVENT and DELAY counters
associated with the hardware breakpoint give added
flexibility for viewing the exact point of interest in the user's
program.
GENERAL DESCRIPTION
AIM-7XE is an advanced development tool which provides
debug assistance for both software and hardware via incircuit-emulation of the MK3870 and MK3873 family of
microprocessors. Use of the AIM-7XE is completely
transparent to the user's final system configuration
(referred to as the "target"). No memory space or user ports
are used, and all signals, including IRESET and IEXT INT,
are functional during emulation. No memory wait states are
required.
A forty-eight channel history memory records up to 1024
bus transactions. The address bus, data bus, ports 0, 1, and
either port 4, 5, or 8 external probes may be logged into the
history memory and later displayed by the user.
BLOCK DIAGRAM DESCRIPTION
The MK3870 Family emulation system is composed of both
the AIM-7XE system and personality modules. AIM-7XE
consists of two boards, the Control board and the History
board, as shown in Figure 2. These boards are attached by
cables to the personality module which contains the target
Single-step circuitry allows the user to execute target
instructions one at a time to see the exact effect of each
instruction. 4 K bytes of emulation RAM are used to
emulate the target microprocessor ROM.
XI-9
AIM-7XE BLOCK DIAGRAM
F'Igure 2
'/
APM xx
AIM PERSONALITY MODULE
L:?I BUFFER
/
V
TARGET
SYSTEM
.u
I(
I'
l TARGET
J
CPU
V
VJ
~
AIM·7XE
ir
DETECT
~
I,EXECUTIONI
CONTROL
If
I
11
.!J
BUFFER
I INTERFACE
RAM
U
4/
IF'
1-
1'1
PORT
1
1 1 DECODE
VJ
Jl
ADDRESS/CONTROLBUS
EVENT :
COUNTER
ir
.!J
V
V
'/
HISTORY
RAM
If
BUFFER
11
FI RADIUS ATABUS
l
BUFFER
LATCH
1 1MEMORY
1 r-- 124
BIT
,I
COMPARE
CONTROL
ir
ft
'/ '/MATRIXI SYs·
l
RAM
IFr ~J.
HISTORY BOARD
..t..
~~ULATIONJ
I BUFFER
I~REAKPOINT
V
CONTROL BOARD
1
JI
TIMER
I
J
l DELAY
J l HISTORY
COUNTER
CONTROL
5t
5J
J
I l PORT
DECODE
;>-
LL
II
CPU and plugs directly into the target system CPU socket.
Address, data, and control signals are buffered by the
pp.rsonality module,
user target system is not required todo software debugging.
Only the AIM-7XE boards and a personality module are
needed.
The Control Board has the circuitry for detecting the
breakpoint condition(s) and forces program execution to
begin in the System Interface RAM, The System Interface
RAM is loaded with an interface program and is shadowed
into the target memory space. This control program makes
the target CPU a slave to the development system. When
the user desires to resume execution of his program, the
control program activates the execution control circuit and
execution resumes at the desired address.
The program which controls the AIM-7XE emulator system
is named AIM7X. After execution of AIM7X is started, the
program takes control of the AIM-7XE emulation system.
The user can then initialize the target system and use the
AIM7X commands to load, test, and debug the target
program.
The History Board has a 24-bit comparator circuit, an
EVENT counter, and a OELAY counter to detect a hardware
breakpoint condition. The 48-channel-by-1024-word history RAM is controlled by the History control circuit. The
Timer circuit is used to count target processor clocks for
logging elapsed time and generating the timer breakpoint.
USING THE AIM-7XE
The Control and History boards ofthe AIM-7XE are installed
directly into the Mostek development system. To complete
the emulation system a personality module is required. This
module is a buffer interface between the first two boards
and the target system's CPU socket. Note that a complete
AIM7X SOFTWARE
AIM7X is the software which operates the AIM-7XE
emulation system in the Mostek MATRIX-80/S0S or SYS80F disk system or the RAOIUSTM development tool. Target
system programs may be developed on a Mostek disk
system by use of the Mostek 3870/F8 Macro Cross
Assembler (MACRO-70) and the resident linker. Programs
may be developed for RAOIUSTM using cross products
supplied by Mostek or other vendors. The AIM7X software
is supplied on standard FLP-8000S diskette for Mostek
disk-based systems and on a variety of media for different
host systems for use with RADIUSTM. The commands
available in AIM7X are summarized below. Each command
also has a "short form" which allows abbreviated input with
fewer keystrokes.
XI-10
Read AIM commands from a file
Display and set breakpoints (8 software, 1 hardware, and 1 timer breakpoint)
Clear one breakpoint or all breakpoints
Copy one block of memory to another block
Disable target CPU interrupts
Display and/or update instructions
Dump a block of memory to a file
Enable target CPU interrupts
Start or continue execution of the target program
Fill memory with a data byte
Load a target program file into memory
Perform hexadecimal arithmetic
Display a menu of commands for the user
Set history logging options
Reinitialize target handshake
Locate a pattern in a memory block
Log all console output to a file
Display and/or update memory
Set an offset value for relative module debugging
Display and update a port on the target CPU
Return to the resident operating system
Perform a test on the target RAM
Display and/or update the target CPU registers
Display the current status of the AIM system
Perform a single or multi-step execution
Display the contents of the history RAM
Allows the RADIUS user to temporarily access the host
Verify the contents of a block of memory with another block or a file
BATCH
BREAK
CLEAR
COpy
DISABLE
DISASSEMBLE
DUMP
ENABLE
EXECUTE
FILL
GET
HEXADECIMAL
HELP
HISTORY
INIT
LOCATE
LOG
MEMORY
OFFSET
PORT
QUIT
RAMTEST
REGISTER
STATUS
STEP
TRACE
TRANSPARENT
VERIFY
SPECIFICATIONS
Target operating frequency: 1 to 4 MHz
Target interface: All signals meet the specifications of the
MK3870 family except that the XLT2 input will not accept a
user crystal. It requires a TIL clock input.
System compatibility: MATRIX-80/SDS, SYS-80F, or
RADIUS
Operating temperature range:
a to +50°C
ORDERING INFORMATION
II
For detailed ordering information refer to the Development
System Products Ordering Guide.
XI-11
XI-12
MOSTEI(.
DEVELOPMENT SYSTEM ,PRODUCTS
MATRIXTM
Microcomputer Development System
INTRODUCTION
The Mostek MATRIXTM is a complete state-of-the-art, floppy
disk-based computer. Not only does it provide all the
necessary tools for software development, but it provides
complete hardware/software debug through Mostek's
AIMTM series of in-circuit emulation cards for the Z80 and
the 3870 family of single-chip microcomputers. The
MATRIX has at its heart the powerful OEM-80E (Single
Board Computer), the RAM-80BE (RAM I/O add-on board),
and the FLP-80E (floppy disk controller board). Because
these boards and software are available separately to OEM
users, the MATRIX serves as an excellent test bed for
developing systems applications.
The disk-based system eliminates the need for other mass
storage media and provides ease of interface to any
peripheral normally used with computers. The file-based
structure for storage and retrieval consolidates the data
base and provides a reliable portable media to speed and
facilitate software development.
The FLP-80DOS Disk Operating System is designed for
maximum flexibility both in use and expansion to meet a
multitude of end-user or OEM needs. FLP-80DOS is
compatible with Mostek's SO and MD Series of OEM
boards, allowing software designed on the MATRIX to be
directly used in OEM board applications.
The relocatable and linking feature of the assembler
enables the use of contemporary modular design
techniques whereby major system alterations can be made
in small tractable modules. Using the Linker, the small
modules can be combined to form a run-time module
without major reassembly of the entire program.
Development System Features
Package System Features
The MATRIX is an excellent integration of both hardware
and software development tools for use throughout the
complete system design and development phase. The
software development is begun by using the combination of
Mostek's Text Editor with "roll in-roll out" virtual memory
operation and the Mostek relocating assembler. Debug can
then proceed inside the MATRIX domain using its resources
as if they were in the final system. Using combinations of
the Monitor, Designer's Debugging Tool, execution time
breakpoints, and single step/ multistep operation along
with a formatted memory dump, provides control for
attacking those tough problems. The use of the Mostek
AIMTM options provides extended debug with versatile
hardware breakpoints on memory or port locations, a
buffered in-circuit emulation cable for extending the
software debug into its own natural hardware environment,
and a history memory to capture bus transactions in real
.
time for later examination.
From a system standpoint, the MATRIX has been designed
to be the basis of an end-product, such as a small
business/industrial computer. The flexibility provided in the
FLP-80DOS operating system permits application programs
to be as diverse as a high-level language compiler or a
supervisory control system in the industrial environment.
Other hardware options are available, with even more to be
added. Expansion of the disk drive units to a total of four
single-sided or double-sided units provides up to two
megabytes of storage. This computer uses the thirdgeneration Z80 processor supported with the power of a
complete family of peripheral chips. Through the use of its
158 instructions, including 16-bit arithmetic, bit
manipulation, advanced block moves and interrupt
handling, almost any application from communication
concentrators to general purpose accounting systems is
made easy.
XI-13
OEM Features
The hardware and software basis for the MATRIX is also
a;;u;~cb!G SCp~r3te!y
to the OE!\',~ pt.!rchaser. Through 8
software licensing agreement. all Mostek software can be
utilized on these OEM series of cards.
MATRIX RESIDENT SOFTWARE (FLP-80DOS)
A totally integrated package of resident software is offered
in conjunction with the MATRIX and consists of:
Monitor
Text Editor
MACRO 80 Assembler
linker
DDT-SO with extended debug through AIMTM
modules
Peripheral Interchange Program
Floppy Disk Handler
1/0 Control System
Device Driver library
Batch Mode Operation
1/0 is done in terms of logical unit numbers. as is commonly
done in FORTRAN. A set of logical units is pre-assigned to
deflllllt I/O drivers upon power UD or reset. From the
console. the user can reassign any logical unit to any new
I/O device and can also display logical unit assignments.
Executable file creation can be done by the Save command;
printable absolute object files can be produced using the
Dump command.
MATRIX BLOCK DIAGRAM
Monitor
The FLP-SODOS Monitor is the environment from which all
activity in the system initiates. From the Monitor. any
system routine such as PIP or a user-generated program is
begun by simply entering the program name. FLP-SODOS
XI-14
Text Editor
fill
The Text Editor permits editing/creating of any source
file independent of the language being written. The
Editor is both line and string oriented to give maximum
utility and user flexibility. The Editor, through its virtual
memory "roll in-roll out" technique, can edit a file
whose length is limited only by maximum diskette
storage. Included in the repertoire of 15 commands are
macro commands to save time when encountering a
redundant editing task. The Editor is also capable of
performing in one operation all the commands which
will fit into an aD-column command buffer.
Summary of Editor Commands
Advance N
!!.ackup N
Change
N/S1/S2
- Advance line pointer N line
- backs up N lines
- change N occurrences of String I to
String 2
Delete N
- Delete current line plus next N-llines
of text
Ixchange N - Exchanges current line plus next N-1
lines with lines to be inserted while in
insert mode
- Reads another file and inserts it into
get file
the file being edited after the current
line
Insert
- Place Editor in insert mode. Text will
be inserted after present line
Line N
- Place line pointer on Line N.
Macro 1 or
Macro 2
- Defines Macro 1 or Macro 2 by the
following string of Text Editor commands.
- Outputs N lines of the file being edited
Put N file
to another disk file.
Quit
- Stores off file under editing process
and returns to Monitor environment
Search N/S1 - Searches from existing pointer
location until NTH occurrence of
string SI is located and prints it.
- Inerts records at top of file before first
Top
line.
Verify N
- Print current record to console plus
next N-I records while advancing
pointer N records ahead.
Write N
- Prints current records plus next N-I
records to source output device while
advancing pointer N records.
eXecute N
- Executes Macro I or Macro 2 as
defined by Macro command.
.!!reakpoint - sets software trap in user code for
interrupting execution in order to
examine CPU registers
- displays contents of user's registers
.Register
Offset
- enters address adder for debug of
relocatable modules
yerify
~alk
Quit
- fills specified portion of memory with
a bit byte
- compares two blocks of memory
- software single step/multistep
- returns to Monitor
Debuggers for other processors have similar or
enhanced capability and are included with the
appropriate AIM.TM
zao ASSEMBLER
The zao Resident Assembler generates relocatable or
absolute object code from source files. The assembler
recognizes all 15a zao instructions as well as 20
powerful pseudo operators. The object code generated
is absolute or relocatable format. With the relocating
feature, large programs can be easily developed in
smaller sections and linked using the Linker. Because
the assembler utilizes the I/O Control System, object
modules or list modules can be directed to disk files,
paper tape, console, or line printer. Portability of output
media eliminates the requirement for a complete set of
peripherals at every software/hardware development
~ystem. The assembler run-time options include sorted
symbol table generation, no list, no object, pass 2 only,
quit, cross reference table, and reset symbol table. The
assembler is capable of handling 14 expression
operators including logical. shift, multiplication,
division, addition and subtraction operations. These
permit complex expressions to be resolved at assembly
time by the assembler rather than manually by the
programmer. Comments can be placed anywhere but
must be integrated with the listing file but can be
directed to the console device. In addition, assembler
pseudo operators are:
GLOBAL
PSECT operator
- for global symbol definition.
- to generate relocatable or
absolute modules
IF expression
- conditional assembly IF expression is true
INCLUDE dataset - to include other datasets (files) as
in-line source code anywhere in
source file.
Linker
The Linker program provides the capability of linking
assembler-generated, absolute or relocatable object
modules together to create a binary or run-time file. This
process permits generation of programs which may
require the total memory resources of the system. The
linking process includes the library search option,
which, if elected, will link in standard library object files
from disk to resolve undefined global symbols. Another
option selects a complete global symbol cross-reference
listing.
XI-15
DDT
The Designer's Debugging Tool consists of commands for
facilitating an otherwise difficult debugging process. The
MATRIX allows rapid source changes through the editor
and assembler. This is followed by DDT operations which
close the loop on the debug cycle. The DDT commands
include:
Memory
Port
.£xecute
Hexadecimal
.£opy
Init
- display, update, or tabulate memory
-display, update or tabulate liD ports
- execute user's program
- performs 16 bit addl sub
- copy one block to another
Rename
Status
Peripheral Interchange Program
PIP provides complete file maintenance activity for
operations such as copy file from disk to disk, disk to
peripheral, or any peripheral to any other peripheral
supporting both file-structured and character-oriented
devices. Key operations such as renaming, appending,
and erasing files also exist along with status commands
for diskette 10 and vital statistics. PIP can search the
diskette directories for any file or a file of a specific
name, extension, and user number. The PIP operations
are:
Append
~opy
Date
Qirectory
Erase
Format
- appends file 1 to file 2 without
changing file 1.
- copies input files or data from an input
device to an output file or device. The
Copy command can be used for a
variety of puq.Juses such CiS :lstiiig
files, concatenating individual files, or
copying all the files on a single file
from one disk unit (e.g. DKO) to a
second disk unit (e.g. OK 1)
- allows the specifying of the date in
day, month, and year format. The date
specified will be used to date tag any
file which is created or edited.
- lists the directory of a specified disk
unit (DKO, DKI, etc.). The file name,
extension, and user number and
creation or edited date are listed for
each file in the directory. The user can
also request listing-only files of a
specified name, only files of a
specified extension, or only files of a
specified user number. The list device
can be any device supported by the
system as well as a file.
- erases a single file or files from a
diskette in a specified disk unit. The
user has the option to erase all files,
only files of a specified file name, or
only files of a specified user number.
- takes completely unformatted softsectored diskettes, formats to IBM
Quit
3740, and prepares to be a system
diskette. Operation is performed on
diskette unit 1 and a unique 11character name is assigned to that
diskette.
- initializes maps in the disk handler
when a new diskette has been
changed while in the PIP environment.
- renames a file, its extension, and user
number to a file of name X, extension
Y, and user Z.
- lists all vital statistics of a disk unit to
any device. These include the number
of allocated records, the number of
used records, and the number of bad
records
- returns to Monitor Environment.
DOSIDisk Handler
The heart of the FLP-80DOS software package is the Disk
Operating System. Capable of supporting up to 4 singledensity, single or double-sided units, the system provides a
file-structure orientation timed and optimized for rapid
storage and retrieval. Program debug is enhanced by
complete error reporting supplied with the DOS.
Additionally, extensive error recovery and bad sector
allocation ensure data and file integrity. The DOS not only
provides file reading and writing capability, but special
pointer manipulation, record deletions, record insertions,
skip records both forward and backward, as well as
directory manipulation such as file creation, renaming, and
erasure. The DOS is initiated by a ca:Hng vector '"A.:h!ch !s a
subset of the liD control system vector or by the standard
10CS calling sequence to elect buffer allocation, blocking,
and deblocking of data to a user-selectable, logical record
type.
A unique dynamic allocation algorithm makes optimal
use of disk storage space. Run time (Binary) files are
given first priority to large blocks of free space to
eliminate overhead in operating system and overlay
programs. The algorithm marks storage fragments as
low priority and uses them only when the diskette is
nearing maximum capacity. The DOS permits 7 files to
be opened for operations at anyone time, thus
permitting execution of complex application programs.
I I 0 Control System
The I/O Control System provides a central facility from
which all calls to liD can be structured. This permits a
system applications program to dissolve any device
dependence by utilizing the logical unit approach of
large, main-frame computers. For example, a
programmer may want to structure the utility to use
logical unit No.5 as the list device which normally in the
system defaults to the line printer. He may, however,
XI-16
strapped for other ROM/PROM elements.
assign at run time a different device for logical unit No.
5. The application program remains unchanged.
RAM-aOBE
Interface by a user to 10CS is done by entering a device
mnemonic in a table and by observing the calling sequence
format. 10CS supplies a physical buffer of desired length,
handles buffer allocation, blocking, and deblocking, and
provides a logical record structure as specified by the user.
Batch - Mode Operation
In Batch-Mode Operation, a command file is built on disk or
assigned to a peripheral input device such as a card reader.
The console input normally taken from the keyboard is
taken from this batch device or batch file. While operating
under direction of a batch file, the console output prompts
the user as normal. or the prompting can be directed to any
other output device. The Batch operation is especially useful
forthe execution of redundant procedures not requiring the
constant attention of the operator.
The RAM-aOBE adds additional memory with Mostek's
MK4116 16K dynamic memory along with more I/O.
These two fully programmable a-bit I/O ports with
handshake provide additional I/O expansion as system
RAM memory needs to grow. Standard system configuration is 4aK bytes for a system total of 60K bytes
user RAM (56K contiguous).
FlP-80E
Integral to the MATRIX system is the floppy controller.
The FLP-aOE is a complete IBM 3740 singledensity/double-sided controller for up to 4 drives. The
controller has 12a bytes of FIFO buffer resulting in a
completely interruptable disk system.
OPTIONAL MODULES COMPATIBLE WITH MATRIX
AIM-zaOBE (6.0 MHz max. clock rate)
MATRIX SYSTEM SPECIFICATIONS
•
•
•
•
•
•
•
•
•
•
•
The AIM-ZaOBE is an improved zao In-Circuit-Emulation
module usable at zao-cpu clock rates of up to 6MHz. The
AIM-ZaOBE is a two processor solution to In-Circuit
Emulation which utilizes a zao-cpu in the buffer box for
accurate emulation at high clock rates with minimum
restrictions on the target system. The AIM-Z80BE provides
real time emulation (no WAIT states) while providing full
access to RESET, NMI and INT control lines. Eight single
byte software breakpoints (in RAM) are provided as well as
one hardware trap (RAM or ROM). The emulation RAM on
the AIM-Z80BE is mappable into the target system in 256
byte increments. A 1024 word x 48 bit history memory is
triggerable by the hardware intercept and can be read back
to the terminal to provide a formated display of the zao-cpu
address, data, and control busses during the execution of
the program under test. Several trigger options are available
to condition the loading of the history memory.
zao CPU.
4K byte PROM bootstrap and zao debugger
60K bytes user RAM. (56K contiguous)
a x a bit I/O ports (4 x PIO) with user-definable
drivers/receivers
Serial port, RS 232 and 20 mA current loop.
4 channel counter/timer (CTC).
2 single-density, single-sided disk drives; 250K
bytes per floppy disk.
3 positions for AIM modules, A/D cards, Serial
Interface, etc.
Device drivers for paper tape readers, punches, card
readers, line printers, Silent 700's, Teletypes and
CRT's are included. Others can be added.
PROM programmer I/O port. Programmer itself is
optional.
Bus compatible with Mostek SD/E series of OEM
boards.
AIM-7XE
The AIM-7XE module provides debug and in-circuit
emulation capabilities for the 3870 series microcomputers
on the MATRIX. Multiple-breakpoint capability and singlestep operation allow the designer complete control over the
execution of the 3a70 Series microcomputer.
HARDWARE DESCRIPTION OEM-80E
CPU Module
The OEM-aOE provides the essential CPU power of the
system. While using the zao as the central processing
unit, the OEM-aOE is provided with other zao family
peripheral chip support. Two zao PIO's give 4
completely programmable a bit parallel 110 ports with
handshake from which the standard system peripherals
are interfaced. Also on the card is the ZaO-CTC counter
time circuit which has 3 free flexible channels to
perform critical counting and timing functions. Along
with 16K of RAM, the OEM-aO provides 5 ROM/PROM
sockets which can be utilized for 10120K of ROM or
5/10K PROM. Four sockets contain the firmware
portion of FLP-aODOS. The remaining socket can be
Register, Port display, and modification capability provide
information needed to find system "bugs." All I/O is in the
user's system and is connected to AIM-7X by a 40-pin
interface cable.
The debugging operation is controlled by a mnemonic
debugger which controls the interaction between the zao
host computer and the 3870 slave. It includes a history
module for the last 1024 CPU cycles and also supports all
3870 family circuits.
XI-17
Assembly and linking are done using the MACRO-70
Assembler and the standard FLP-80DOS linker.
Card Cage: Six slots DIN 41612 type connectors
Operating Temperature: +1 O°C to +35°C
MECHANICAL SPECIFICATIONS
Overall Dimensions:
CPU subsystem - 8" High x 21" wide x 22" deep
(20.3qm x 53.3 cm x 55.8cm)
Disk subsystem - 8" High x 21" wide x 22" deep
(20.3cm x 53.3 cm x 55.8cm)
Humidity: up to 90% relative, noncondensing.
ELECTRICAL SPECIFICATIONS
INPUT 100/1151230 volts AC ± 10%
50 Hz (MK78189) or 60Hz (MK78188)
OUTPUT
CPU subsystem
Material: Structural Foam (Noryl)
Weight: CPU Subsystem 25 Ibs (11.3 Kg)
Disk Subsystem 50 Ibs (22.7 Kg)
Disk subsystem
+5 VDC at 12A max.
+12 VDC at 1.7A max.
-12 VDC at 1.7A max.
+5VDC at 3.0A max.
-5 VDC at 0.5A max.
+24 VDC at 3.4A max.
Fan Capacity: 115 CFM
ORDERING INFORMATION
BASIC SYSTEM NO.
NAME
DESCRIPTION
PART NO.
MATRIXTM
Z80 floppy disk based microcomputer with
eCK bytBS of R,A,~..~ {56K bytes c0!"'!!igll(HI~ RAM). 4K bytes
PROM bootstrap, two 250K byte single density floppy
disk drives with Operations Manual. Includes the software
package of FLP-80DOS distributed on diskette. Requires
signed license agreement with purchase order.
MK78188 (60Hz)
MK78189 (50Hz)
MATRIXTM
Operations Manual Only
MK79730
FLP-80DOS
Operations Manual Only
MK78557
XI-18
IN-CIRCUIT EMULATION MODULES
NAME
DESCRIPTION
PART NO.
AIM-Z80AE
4.0 MHz RAM based Z80 in-circuit emulator with expanded
history trace, buffer box, cables and Operations Manual
16K Bytes emulation RAM
MK78181-1
MK78181-2
32K Bytes emulation RAM
AIM-Z80AE
Operations Manual only
MK79650
AIM-7XE
RAM based in-circuit emulator for the 3870
series of single-chip microcomputers (3870, 3872, 3874
and 3876) with cables and Operations Manual.
MK79077
AIM-7XE
Operations Manual only
MK79579
SOFTWARE-FULLY SUPPORTED
NAME
DESCRIPTION
PART NO.
MACRO-70
Relocatable 3870/F8 MACRO assembler which
speeds up development of 3870/F8 programs through use
of MACRO to run on MATRIX with Operations Manual.
Requires signed license agreement with purchase order.
MK79085
MACRO-70
Operations Manual Only
MK79658
MACRO-80
Operations Manual Only
MK79635
NAME
DESCRIPTION
PART NO.
ANSI
BASIC
ANSI BASIC interpreter with random disk
MK78157
access for the MATRIX microcomputer including operations
manual. Requires signed license agreement with purchase
order.
ANSI
BASIC
Operations Manual only
MK79623
XI-19
SOFTWARE-LEVEL 2 UNSUPPORTED
NAME
DESCRIPTION
PART NO.
MOSTEK
FORTRAN IV
FORTRAN IV compiler (Z80 object code) for the MATRIX
microcomputer with Operations Manual. Requires signed
license agreement with purchase order.
MK78158
MOSTEK
FORTRAN IV
Operations Manual only
MK79644
MK79643
LIBRARY
Vol. 1 of zao Software Library including FLP-aOOOs
MK78164
utilities, sort, 8080 to Z80 source translator, word processor
program, LLL BASIC (6K). 23 Programs total including
source, object, and binary.
PERIPHERALS AND CABLES
NAME
DESCRIPTION
PART NO.
MOSTEK
VT
110-9600 Baud CRT with upper and lowercase character
set. Includes cable (78152) to MATRIX. 110/115 volt
50/60 Hz 230 volt 50/60 Hz
MK78190-1 (60Hz)
MK78190-2(50Hz)
MOSTEK LP
7 x 7 dot MATRIX printer with 120 character LP per second
operation. Includes interface cable to MATRIX.
100/115 volt model 50/60 Hz 230 volt model 50/60Hz
MK78191-1 (60Hz)
MK78191-2(50Hz)
PPG-8/16
Programmer for 2708, 2758 and 2716 PROM
~nc;iude5 liitei"fac;iig cab!c$ to f'i!,A"TR!X.
MK79081-1
SO-WW
Wire wrap card compatible with MATRIX.
MK79063
SO-EXT
Extender card compatible with MATRIX.
MK79062
LP-CABLE
Interface cable from MATRIX Microcomputer to Centronics
306 or 702 printer
MK79089
PPG-CABLE
Interface cables from MATRIX to PPG-8/16 PROM
programmer (MK79081).
MK79090
XI-20
Standard license Agreement and Registration Form
All Mostek Corporation software products are sold
on condition that the purchaser agrees to
the following terms:
The Purchaser agrees not to sell, provide, give away, or otherwise make available to any unauthorized persons, all or any part
of, the Mostek software products listed below, including, but not restricted to 9bject code, source code, and program listings. This
license allows the purchaser to operate the software product only on the system referenced by serial number below. Mostek
retains title to all Mostek software products including diskettes and tapes.
2. The Purchaser may at any time demonstrate the normal operation of the Mostek software product to any person.
3. Purchaser may not copy materials furnished with Mostek software products but copies may be obtained from Mostek. No part
of the Mostek software products may be copied by Purchaser In printed or machine-readable form unless for the purpose of study,
modification or back-up. Purchaser will place Mostek's copyright notice on all copies and maintain records, available at Mostek's
request. of the location of the copies.
4. Mostek's sole obligation shall be to make available to Purchaser all published modifications or updates made by Mostek to
licensed software products which are published and made generally available within one (1) year from date of purchase, provided
Purchaser has complied with the Software License Agreement and Registration Form.
5.ln no event will Mostek be held liable for any loss, expense or damage, of any kind whatsoever, direct or indirect. including as a
result of Mostek's negligence. Mostek shall not be liable for any incidental damages, consequential damages and lost profits,
arising out of or connected In any manner with any of Mostek's software products described below.
6. MOSTEK MAKES NO WARRANTIES OF ANY KIND, WHETHER STATUTORY, WRITTEN, ORAL, EXPRESSED OR IMPLIED
(INCLUDING WARRANTIES OF FITNESS FOR A PARTICULAR PURPOSE AND MERCHANTABILITY AND WARRANTIES ARISING
FROM COURSE OR DEALING OR USAGE OF TRADE) WITH RESPECT TO THE SOFTWARE DESCRIBED BELOW.
7. Any license under this agreement may be terminated for breach by one month's prior written notice and Purchaser will
promptly return all copies of any parts of Mostek Software products.
List the following Software Products subject to this agreement
Mostek Product
Number (MK#)
Mostek Product
Number (MK#)
Product Name
Product Name
AGREED TO
PURCHASER
MOSTEK CORPORATION
Name (PRINT)
Name
Signature (PARTY)
Title
Date
Title
Date
PLEASE PRINT FOLLOWING INFORMATION
Company Name __________________________________
Date ____________________________________________
Address ________________________________________________
City _____________________________ State ___________________________ Zip Code __________
Country ___________________________________________ Telephone( ____~_________________________________
Mostek Disk System Serial #
or Mostek Disk Controller Serial #
or 0 Non Mostek Hardware
Date of Purchase
Place of Purchase ______________________________.
XI-21
If you are purchasing this product from a Distributor, print the Distributor's name below and return this form to the Distributor;
The distributor will provide a purchase order # and will then forward this form to the address below.
Distributor Name ____________________________
~
If you are purchasing this product direct from Mostek, check the Customer PO # box, provide your purchase order #, and return
this form to the address below.
Purchase Order # to Mostek
o Customer
PO #
or
o Distributor PO
PO # _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
#
RETURN THIS FORM TO
Software Librarian, MS #510
Micro System Department
Mostek Corporation
1215 W. Crosby Road
P.O Box 169
Carrollton, Texas 75006
"NOTE: Mostek will not ship this software product to customer until this signed form
librarian.
XI-22
IS
received by the Mostek software
MOSTEI(.
DEVELOPMENT SYSTEM PRODUCTS
EVAL-70
3870 Evaluation System
FEATURES
o An ideal hardware and/or software design aid for the
MK38P70 and MK3870 family of Single-Chip
Microcomputers
o
Includes a 2K byte firmware monitor
o
Keypad for command and data entry
o
7-segment address and data display
o
Programming socket for MK2716/2758's
o
Crystal controlled system clock
o
2K bytes of MK4118 static RAM (up to 4K optional)
o
Sockets for up to 4K bytes of MK2716 PROM's
o
Flexible memory map strapping options
o
Current loop or RS-232 serial loader optional (110-3001200 baud)
o
3 general purpose timer/counters
o
3 general purpose external interrupts
o
Easy to use - requires only two supplies for normal
operation (+5, +12)
o
Ideal for evaluation of MK3870 family single-chip microcomputers
USING EVAL-70
o
Full in-circuit emulation of MK3870 single-chip microcomputer family.
DESCRIPTION
EVAL-70 is a single board computer with on-board keypad,
address and data displays, and 2716 PROM programmer.
EVAL-70 is designed to be an easy-to-use introduction to the
industry standard MK3870 family of single-chip computers.
Programs can be written and debugged in RAM using the
powerful DDT-70 operating system. The 40 pin AIM cable
can be used to perform real-time emulation of the MK3870
family of devices. After debugging, programs can be loaded
into MK2716's for final circuit checkout (and emulation).
The photograph above shows how EVAL-70 is used as a
program development tool. Only an external power supply is
required for operation of EVAL-70; the built-in keyboard and
display offer all the functions needed to design, develop, and
debug programs for the MK3870 family of single-chip
microcomputers at the machine code level.
COMMAND SUMMARY
OM:
Display memory: allows memory to be displayed
and (RAM) updated.
DR:
Display registers: allows the user's register values
to be displayed and updated.
DP:
Display ports: allows the contents of ports 0 thru
F to be displayed and updated
HX:
Hex calculator: allows hexadecimal arithmetic
calculations to be performed (add and subtract)
GO:
causes execution of a user program at a specified
address
XI-23
£I
BK:
Breakpoint: a1I0ws a breakpoi ntto be set or reset
ST:
Step: causes single-step execution of a user program at a specified address
LD:
Load: initiates the serial loader (optional)
MV:
Move: allows a block of memory to be moved or
copied from one space to another
RO, R8:
Read PROM: causes the PROM programmer
socket to be read into address space 00-7FF or
800-F7F
PO, P8:
Program PROM: causes the contents of address
space 000-7FF or 800-F7F to be programmed
into the PROM programmer socket
EVAL-70 KEYBOARD DRAWING
IElulAILlllol
BLOCK DIAGRAM
EVAL-70 uses several members of the F8 multichip family. A
MK3850 Central Processing Unit (CPU) provides the ALU,
registers, system control and two 8-bit ports. A MK90071
Peripheral Input Output chip (PIO) provides two more 8-bit
ports plus a flexible timer/interrupt control block. These four
ports are connected to the AIM cable connector for in-circuit
emulation of the MK3870 family devices, and also to the
PROM programmer socket. An additional PIO (MK90073)
interfaces the LED display and keyboard. A MK3853 Static
Memory Interface chip (SMI) interfaces the operating system
ROM, uptotw02KPROMsand uptofour1 K RAMs. A switch
option allows either the 4K of PROM or the 4K of RAM to
appear at address OOOOH, with the other 4K appearing at
1000H. The operating system ROM may be up to 8K
(currently 2K) starting at 8000H. A switch option allows reset
to either OOOOH or to the 8000H ROM.
USING EVAL-70 WITH LARGER SYSTEMS
BLOCK DIAGRAM
A!thcugh the EV..~\,L-70 operet!r!g system (DDT-70) W~~
designed to make program machine code entry simple and
quick, many users will find it more efficient to assemble their
programs on a larger computer and then download to
EVAL-70.
PIO
MK90071
CPU
MK3850
The download to EVAL-70 may be accomplished in either of
two ways:
1)
SMI
MK3853
PIO
MK90073
KEYBOARD
2)
A PROM may be programmed on the Development System, and then read into RAM by the
EVAL-70 for debugging.
A direct connection may be made between a
serial port on the Development System and the
serial loader port on EVAL-70. An optional serial
loader program is provided in the EVAL-70
Operations Manual.
Owners of minicomputers may purchase XFOR-70, a 3870
cross-assembler written in ANSI standard Fortran IV. It may
be compiled and executed on any.computer system which
has at least a 16-bit word length for integer storage and 13K
(typical) of memory for program storage.
XI-24
DEVELOPMENT SYSTEM
EVAL-70
PROM
"
II"
"'"
c=)~c) ~ao~a
[II]]]]]
~
DEVELOPMENT SYSTEM
II
XI-25
EVAL-70 BOARD
XI-26
Owners of a Matrix Disk Development System may
purchase MACRO-70, an advanced 3870 cross
assembler. MACRO-70 will generate relocatable,
linkable object modules and provides MACRO assembly
capability.
SPECIFICATIONS
Operating Temperature: O°C - sooC
Power Supplies Required: +SVDC ±S% 1.0A max
+12VDC ±S% 0.1A max
+2SVDC ±S% 0.1 A max
Board Size: 8.5 in. (21.6 cm) x 12 in. (30.Scm) x 2 in. (Scm)
Connectors and Cables: 40 pin in-circuit-emulation cable
is provided.
ORDERING INFORMATION
NAME
DESCRIPTION
PART NO.
EVAL-70
3870 Evaluation System, Assembled and tested
with Operations Manual and In-circuit Emulation cable.
MK79086
EVAL-70
Manual
EVAL-70 Operations Manual only
MK79717
XFOR-SOI70
FORTRAN Cross assembler for 3870 series
MK79012
MATRIX
Disk Based !Jevelopment System
MK78189 (50Hz)
MK78188 (60Hz)
AIM-72E
In-circuit emulation module for the MATRIX
for the 3870, 3872, 3874 and 3876 Microcomputer
MK79077
MACRO-70
3870 Cross Assembler with MACRO capability
for the Matrix Disk Development System
MK7908S
£I
XI-27
XI-28
MOSTEI(.
DEVELOPMENT SYSTEM PRODUCTS
PPG 8/16C
PROM Programmer
FEATURES
PPG B/16C
o Programs, reads, and verifies 270S-, 275S-, and 2716type PROMs (275S and 2716 PROMS must be 5-Volt
only type)
o
Interfaces to MATRIX and MDX-PIO
o
Driver software included on system diskette for
FLP-SODOS
o
Zero-insertion-force socket
o
Power and programming indicators
DESCRIPTION
The PPG-S/16C PROM Programmer is a peripheral which
provides a low-cost means of programming 2708, 275S, or
2716 PROMs. It is compatible with Mostek's MATRIX
Microcomputer Development System and the MDX-PIO.
The PPG-S/16C has a generalized computer interface (two
S-bit 1/0 ports) allowing it to be controlled by other types of
host computers with user-generated driver software. A
complete set of documentation is provided with the PPGS/16C which describes the internal operation and details
user's operating procedures
The PPG-S/16C is available in a metal enclosure for use
with the MATRI)(TM and the MDX-PIO. Interface cables for
either the MATRIX or MDX-PIO must be purchased
separately.
SOFTWARE DESCRIPTION
The driver software accomplishes four basic operations.
These are (1) loading data into host computer memory, (2)
reading the contents of a PROM into host computer
memory, (3) programming a PROM from the contents of the
host computer memory, and (4) verifying the contents of a
PROM with the contents of the host computer memory.
The driver software is provided on the FLP-SODOS system
diskette. The user documentation provided with the PPGS/16C fully explains programming procedures to enable a
user to develop a software driver on a different host
computer.
XI-29
PPG 8/1 6C BLOCK DIAGRAM
J1
CONNECTOR
TO
HOST
COMPUTER
SSTS
01
Os
275S1
MK270S1
MK2716
SOCKET
MODE
SELECT
CIRCUIT
J2
+12 VDC
CONNECTOR
TO
+5, +12, -12
POWER SUPPLY
+5VDC
GND
-12VDC
PROGRAM
PULSE
CONVERTER
+27.5 VDC
":U~mR It~'1
PROGRAM
LED
STEP-UP
VOLTAGE
REGULATOR
-5VDC +5VDC
+12 VDC
INTERFACE
OPERATING TEMPERATURE
25-pin control connector (0 type)
4O-pin control connector (0.1-in. centers card edge)
for AIO-SOF, SOB-SO, SOB-50170, or MATRI)(TM
12-pin power connector (0.156-in. centers card edge)
All control signals are TTL-compatible
PROGRAMMING TIME
POWER REQUIREMENTS
270S - 2.5 minutes
275S - 0.9 minutes
2716 - 1.S minutes
+ 12 VOC at 250mA typical
+5 VOC at 1OOmA typical
-12 VOC at 50mA typical
XI-30
ORDERING INFORMATION
DESIGNATOR
DESCRIPTION
PART NO.
PPG-S/16C
PROM Programmer for 270S1275S12716 PROMs
with Operations Manual for interface with MATRIX.
MK790S1-1
MATRIX to PPG-S/16C
PPG-S/16C Interface Cable for MATRIX
MK79090
MD-PPG-C
PPG-S/16C Interface Cable for MDX-PIO
MK77957
PPG-S/16C Operations Manual
MK79603
*NOTE: The PPG-S/16C will only program the 270S. 275S. and 2716 PROMs. The 275S and 2716 are 5 Volt only type
PROMs. THE PPG-S/16C WILL NOT PROGRAM THE TI2716 MULTIPLE-VOLTAGE 2K x S PROM.
XI-31
XI-32
MOS'rEl(@
DEVELOPMENT SYSTEM PRODUCTS
SO To SOE Adapter
SD TO SDE ADAPTER
INTRODUCTION
Figure 1
The 'SD To SDE Adapter' is an inexpensive conversion aid
for the AID-SOF customers to expand their system to accept
the AIM-ZSOBE or AIM-7XE modules. The 'SD to SDE
Adapter' is a bus converter PCB allowing the installation of
the SDE seriesAIM modules into an AID-SOF Development
System.
HARDWARE
The 'SD To SDE Adapter' is a single SD form factor printed
circuit board with connectors and card guides for the SDE
form factor modules. The SDE series AIM modules are
installed onto the Adapter and then become an
insertable/removable unit configured to the AID-SOF
systems.
The 'SD To SDE Adapter' has three connectors: J1 is the
AID-SOF bus interface edge connector; SK1 and SK2 are
the SDE series AIM module interface connectors.
SPECIFICATIONS
Width: 12.0 inches
Height: S.5 inches
Power consumption: None
INSTALLATION
STRAPPING
A. Slide the AIM board into the properly strapped Adapter
The customer wi.1I need two of these Adapters to be able to
use the AIM modules on hisAID-SOF system. Hewill need
to strap J2 pins 1 and 2 on one Adapter for his AIM Logic
board, and strap J3 pins 1 and 2 on the other Adapterforthe
AIM History board. Refer to the following table for the J2
and J3 strapping instructions.
board so that the connectors gently mate. Do not force
complete mating.
B. Slide the Adapter into the AID-SOF card cage with the
components facing the same direction as the other
boards in the system.
C. Completely mate the Adapter with the 100 pin edge
connector in the AID-SOF system.
D. Completely mate the SDE board with the Adapter.
AIM Board
AIM-ZooBE
AIM-7XE
AIM History
J2
Strap J2 pins 1
and 2
Strap J2 pins 1
and 2
Leave J2 unstrapped
J3
Leave J3 UI1strapped
Leave J3 unstrapped
Strap J3 pins 1
and 2
WARNING: Make sure that the components on the AIM
boards are facing the same direction as the
other boards in the AID-SOF system. If not,
the AIM boards will be damaged upon power
up.
XI-33
I
III
ORDERING INFORMATION
DESIGNATOR
DESCRIPTION
PART NO.
SO to SOE Adapter
The conversion aid for the AIO-80F system to accept the
new AIM modules.
MK79095
XI-34
MQSfEI{.
SOFTWARE PRODUCTS
MACRO-SO
MK78165
FEATURES
o
o
Assembles standard Z80 instruction set to produce
relocatable, linkable, object modules
Provides nested conditional assembly, an extensive
expression evaluation capability, and an extended set of
assembler pseudo-ops:
- origin
- equate
EQU
- set/define macro label
DEFL
DEFM
- define message
DEFB
- defi ne byte
DEFW
- define word
DEFS
- define storage
- end of program
END
- global symbol definition
GLOBAL
NAME
- module name definition.
- program section definition
PSECT
IF/ENDIF
- conditional assembly
INCLUDE
- include another file in source module
LI ST/N LIST - list on/oft.
CLiST
- code listing only of macro expansions
ELiST
- list/no list of macro expansions
EJECT
- eject a page of listing
TITLE
- place title on listing
ORG
o
o
Provides options for obtaining a printed cross-reference
listing, terminating after pass one if errors are
encountered, redefining standard Z80 opcodes via
macros, and obtaining an unused-symbol reference
table.
Provides the most advanced macro handling capability in
the microcomputer market which includes:
- optional arguments
- default arguments
- looping capability
- global/local macro labels
- nested/recursive expansions
- integer/boolean variables
- string manipulation.
- conditional expansion based on symbol definition
- call-by-value facility
- expansion of code-producing statements only
- expansion of macro-call statement only
o Listing and object modules can be output on disk files or
any device.
o
Compatible with other Mostek Z80 assemblers and FLP80DOS Version 2.0 or higher. Requires 32K or more of
system RAM.
DESCRIPTION
MACRO-80 is an advanced upgrade from the FLP-80DOS
Assembler (ASM). In addition to its macro capabilities, it
provides for nested conditional assembly and allows symbol
lengths of any number of characters. It supports global
symbols, relocatable programs, a symbol cross-reference
listing, and an unused-symbol reference table. MACRO-80
is upward compatible with all other Mostek Z80
assemblers.
The Mostek Z80 Macro Assembler (MACRO-80) is
designed to run on the Mostek Dual-Disk Development
System with 32K or more of RAM. It requires FLP-80DOS,
Version 2.0 or higher. Macro pseudo-ops include the
following:
MACRO/MEND
MNEXT
MIF
MGOTO
MEXIT
MERROR
MLOCAL
- defi ne a macro
- step to next argument
- evaluate expression and branch to
local macro label if true
- branch to local macro label
- terminate macro expansion
- print error message in listing
- define local macro label
Predefined macro-related parameters include the following:
%NEXP
%NARC
#PRM
%NPRM
%NCHAR
- current number of this expansion
- number of arguments passed to
expansion
- expand last-used argument
- number of last-used argument
- number of characters in
argument
The operations manual describes in detail all facilites
available in MACRO-80 and provides a host of examples
and sample print-outs.
XI-35
£I
ORDERING INFORMATION
.'
D ESIGNATOR
DESCRIPTION
PART NO.
MACRO-80
Z80 Macro Assembler, binary program supplied on a standard
MK78165
FLP-80DOS diskette, with Operations Manual.
MACRO-80 Operations Manual
XI-36
MK79635
MOSTEKs
SOFnNAREPRODUCTS
MACRO·70
MK79085
o An extended instruction set for the MK3870 is defined
via a macro definition file and is shipped with the
MACRO-70 diskette.
FEATURES
o
Assembles standard 3870/F8instruction set to produce
relocatable, linkable object modules.
o
Provides nested conditional assembly, an extensive
expression evaluation capability, and an extended set of
assembler pseudo-ops:
ORG
EaU
DC
DEFL
DEFM
DEFB
DEFW
DEFS
END
GLOBAL
NAME
PSECT
IF/ENDIF
INCLUDE
UST/NUST
CUST
EUST
EJECT
mLE
- origin
- equate
- define constant
- set/define macro label
- define message
- define byte
- define word
- define storage
- end of program
- global symbol definition
- module name definition
- program section definition
- conditional assembly
- include another file in source module
- list on/off
- code listing only of macro expansions
-list/no list of macro expansions
- eject a page of listing
- place title on listing
o
Listing and object modules can be output on disk files or
any device.
o
Compatible with other Mostek 3870/F8 assemblers and
FLP-SODOS Version 2.0 or higher. Requires 32K or more
of system RAM.
DESCRIPTION
MACRO-70 is an advanced upgrade from the 3870/F8
Cross Assembler (FZCASM). In addition to its macro
capabilities, it provides for nested conditional assembly and
allows symbol lengths of any number of characters. It
supports global symbols, relocatable programs, a symbol
cross-reference listing, and an unused-symbol reference
table. MACRO-70 is upward compatible with all other
Mostek 3870/F8 Assemblers.
The Mostek 3870/F8 Macro Assembler (MACRO-70) is
designed to run on the Mostek Dual-Disk Development
System with 32K or more of RAM. It requires FLP-80DOS,
Version 2.0 or higher. Macro pseudo-ops include the
following:
o Provides options for obtaining a printed cross-reference
listing, terminating after pass one if errors are
encountered, redefining standard MK3870 opcodes via
macros, and obtaining an unused-symbol reference
table.
o Provides the most advanced macro handling capability
on the microcomputer market, which includes:
- optional arguments
- default arguments
-looping capability
- global/local macro labels
- nested/recursive expansions
- integer/boolean variables
- string manipulation
- conditional expansion based on symbol definition
- call-by-value facility
- expansion of code-producing statements only
- expansion of macro-call statements only
MACRO/MEND
MNEXT
MIF
MGOTO
MEXIT
MERROR
MLOCAL
- define a macro
- step to next argument
- evaluate expression and branch to
local macro label if true
- branch to local macro label
- terminate macro expansion
- print error message in listing
- define local macro label
Predefined macro-related parameters include the following:
%NEXP
%NARC
#PRM
%NPRM
%NCHAR
- current number of this expansion
- number of arguments passed to
expansion.
- expand last-used argument
- number of last-used argument
- number of characters in
argument
The operations manual describes in detail all facilities
available in MACRO-70 and provides a host of examples
XI-37
til
and sample print-outs. An e.xtended instruction set which is
designed to ease programming for the MK3870 is defined
in the manual. The new instructions are provided on the
MACRO-70 diskette in the form of a macro definition file
which can be included in a source program.
Downloading to other Mostek systems is facilitated by a
utility program called F8DUMP, which is supplied on the
MACRO-70 diskette.
ORDERING INFORMATION
DESGINATOR
DESCRIPTION
PART NO.
MACRO-70
3870/F8 Macro Cross Assembler, binary program supplied
on a standard FLP-80DOS diskette. Includes F8PUMP utility,
an extended instruction set, macro definition file, and the
Operations Manual.
MK79085
MACRO-70 Operations Manual
MK79635
XI-3S
MOSTEI(.
SOFnNAREPRODUCTS
FlP-80DOS
MK78142, MK77962
FLP-80DOS
INTRODUCTION
The Mostek FLP-aODOS software package is designed for
the Mostek dual floppy disk zao Development System or an
MD board system. Further information on this system can
be found in the MATRI)(TM Data Sheet. FLP-aODOS
includes:
o Monitor
o
o
o
o
o
o
o
Debugger
Text Editor
zao Macro Assembler
Relocating Linking Loader
Peripheral Interchange Program
Linker
A Generalized I/O System For Peripherals
These programs provide state-of-the-art software for
developing zao programs as well as establishing a firm
basis for OEM products.
MONITOR
The Monitor provides user interface from the console to the
rest of the software. The user can load and run system
programs, such as the Assembler, using one simple
command. Programs in object and binary format can be
loaded into and dumped from RAM. All I/O is done via
channels which are identified by Logical Unit Numbers. The
Monitor allows any software device handler to be assigned
to any Logical Unit Number. Thus, the software provides
. complete flexibility in configuring the system with different
peripherals. The Monitor also allows two-character
mnemonics to represent 16-bit address values. Using
mnemonics simplifies the command language. Certain
mnemonics are reserved for I/O device handlers such as
'DK' for the flexible disk handler. The user can create and
assign his own mnemonics at any time from the console,
thus simplifying the command language for his own use.
The Monitor also allows "batch mode operation" from any
input device or file.
The Monitor commands are:
$ASSIGN assign a Logic Unit Number to a device.
$CLEAR remove the assignment of a Logical Unit
Number to a device.
$RTABLE print a list of current Logic Unit Numberto-Device assignments.
$DTABLE -
print default Logical Unit Number-toDevice assignments.
$LOAD load object modules into RAM.
$GTABLE print a listing of global symbol table.
$GINIT initialize global symbol table.
$DUMP dump RAM to a device in object format.
load a binary file into RAM from disk.
$GET $SAVE save a binary file on disk.
$BEGIN start execution of a loaded program.
$INIT initialize disk handler.
$DDT enter DDT debug environment.
IMPLIED RUN COMMAND - get and start execution of a
binary file.
DESIGNER'S DEVELOPMENT TOOL - DDT
The DDT debugger program is supplied in ROM for
debugging relocatable and absolute zao programs.
Standard commands allow displaying and modifying
memory and CPU registers, setting breakpoints, and
executing prog~ams. Mnemonics are used to represent ZOO
registers, thus simplifying the command language.
XI-39
II
The allowed commands are:
BInsert a breakpoint in user's program.
CCopy contents of a block of memory to another
location in memory.
EExecute a program.
Fill an area of RAM with a constant.
FH16-bit hexadecimal arithmetic.
LLocate and print every occurrence of an 8-bit
pattern.
M Display, update, or tabulate the contents of
memory.
PDisplay or update the contents of a port.
RDisplay the contents of the user's register.
SHardware single step requires Mostek's AIM-80
board or AIM-Z80A board.
W Software single step.
VVerify memory (compare two blocks and print
differences).
TEXT EDITOR -EDIT
The FLP-80DOS Editor permits random-access editing of
ASCII character strings. The Editor works on blocks of
characters which are rolled in from disk. It can be used as a
line-or character-oriented editor. Individual characters may
be located by position or context. Each edited block is
automatically rolled out to disk after editing. Although the
Editor is used primarily for creating and modifying Z80
assembly language source statements, it may be applied to
any ASCII text delimited by "carriage returns".
The Editor has a pseudo-macro command processing
option. Up to two sets of commands may be stored and
processed at anytime during the editing process. The Editor
allows the following commands:
An Advance record pointer n records.
Bn Backup record pointer n records.
Cn dS1dS2d - Change string S1 to string S2 for n
occurrences.
Dn Delete the next n records.
En Exchange current records with records to be
inserted.
Fn If n = 0, reduce printout to console device (for
TIY and slow consoles).
1Insert records.
Ln Go to line number n.
Mn Enter commands into one of two alternate
command buffers (pseudo-macro).
QQuit - Return to Monitor.
Sn dS1d - Search for nth occurrence of string S1.
TInsert records at top of file before first record.
Output n records to console device.
Vn Wn Output n records to Logical Unit Number five
(LUN 5) with line numbers.
Xn Execute alternate command buffer n.
zao ASSEMBLER - ASM
The FLP-80DOS Assembler reads standard Z80 source
XI-40
mnemonics and pseudo-ops and outputs an assembly
listing and object code. The assembly listing shows address,
machine code, statement number, and source statement.
The code is in industry-standard hexadecimal format
modified for relocatable, linkable assemblies.
The Assembler supports conditional assemblies, global
symbols, relocatable programs, and a printed symbol table.
It can assemble any length program, limited only by a
symbol table size of over 400 symbols. Expressions
involving arithmetic and logical operations are allowed.
Although normally used as a two-pass assembler, the
Assembler can also be run as a single-pass assembler or as
a learning tool. The following pseudo-ops are supported:
COND
DEFB
DEFL
DEFM
DEFS
DEFW
END
ENDC
ENDIF
EQU
GLOBAL
IF
INCLUDE
NAME
ORG
PSECT
EJECT
TITLE
LIST
NLiST
-
-
same as IF.
define byte.
define label.
define message (ASCII).
define storage.
define word.
end statement.
same as ENDIF.
end of conditional assembly.
equate label.
global symbol definition.
conditional assembly.
include another file within an assembly.
program name definition.
program origin.
program section definition.
eject a page of listing.
place heac'ing at top of each page of listing.
turn listing on.
turn listing off.
RELOCATING LINKING LOADER - RLL
The Mostek FLP-80DOS Relocating Linking Loader
provides state-of-the-art capability for loading programs
into memory. Loading and linking of any number of
relocatable or nonrelocatable object modules is done in one
pass. A non-relocatable module is always loaded at its
starting address as defined by the ORG pseudo-op during
assembly. A relocatable object module can be positioned
anywhere in memory at an offset address.
The Loader automatically links and relocates global symbols
which are used to provide communication or linkage
between program modules. As object modules are loaded, a
table containing global symbol references and definitions is
built up. The symbol table can be printed to list all global
symbols and their load address. The number of object
modules which can be loaded by the Loader is limited only
by the amount of RAM available for the modules and the
symbol table.
The Loader also loads industry-standard non-relocatable,
non-linkable object modules.
LINKER - LINK
INPUTIOUTPUT CONTROL SYSTEM - IOCS
The Linker provides capability for linking object modules
together and for creating a binary (RAM image) file on disk.
A binary file can be loaded using the Monitor GET or
IMPLIED RUN command. Modules are linked together using
global symbols for communication between modules. The
linker produces a global symbol table and a global cross
reference table which may be listed on any output device.
The first package is called the I/O Control System (IOCS).
This is a generalized blockerIdeblocker which can interface
to any device handler. Input and output can be done via the
10CS in any of four modes:
1. Single-byte transfer.
2. Line at a time, where the end of a line is defined by
carriage return.
3. Multibyte transfers, where the number of bytes to be
transferred is defined as the logical record length.
4. Continuous transfer to end-of-file, which is used for
binary (RAM-image) files.
The Linker also provides a library search option for all global
symbols undefined after the specified object modules are
processed. If a symbol is undefined, the Linker searches the
disk for an object file having the file-name of the symbol. If
the file is found, it is linked with the main module in an
attempt to resolve the undefined symbol.
PERIPHERAL INTERCHANGE PROGRAM - PIP
The Peripheral Interchange Program provides complete file
maintenance facilities for the system. In addition, it can be
used to copy information from any device or file to any other
device or file. The command language is easy to use and
resembles that used on DEC minicomputers. The following
commands are supported:
COMMAND
APPEND
COPY
DIRECT
ERASE
FORMAT
INIT
RENAME
STATUS
QUIT
FUNCTION
Append files.
Copy files from any device to another
device or file.
List Directory of specified Disk Unit.
Delete a file.
Format a disk.
Initialize the disk handler.
Rename a file.
List number of used and available sectors
on specified disk unit.
Return to Monitor.
The first letter only of each command may be used.
The 10CS provides easy application of 1/0 oriented
packages to any device. There is one entry point, and all
parameters are passed via a vector defined by the calling
program. Any given handler defines the physical attributes
of its device which are, in turn, used by the 10CS to perform
blocking and deblocking.
FLOPPY DISK HANDLER - FDH
The Floppy Disk Handler (FDH) interfaces from the 10CS to a
firmware controllerfor up to fourfloppydisk units. The FDH
provides a sophisticated command structure to handle
advanced OEM products. The firmware controller interfaces to Mostek's FLP-SOE Controller Board. The disk
format is IBM 3740 soft sectored. The software can be
easily adapted to double-sided and double-density disks.
The Floppy Disk Handler commands include:
- erase file
- create file
- open file
- close file
- rename file
- rewind file
- read next n sectors
- reread current sector
- read previous sector
- skip forward n sectors
- skip backward n sectors
- replace (rewrite) current sector
- delete n sectors
DISK OPERATING SOFTWARE
The disk software, as well as being the heart of the MATRIX
development system, can be used directly in OEM
applications. The software consists of two programs which
provide a complete disk handling facility.
The FDH has advanced error recovery capability. It supports
a bad sector map and an extensive directory which allows
multiple users. The file structure is doubly-linked to
increase data integrity on the disk, and a bad file can be
recovered from either its start or end.
XI-41
II
FLP-80 DOS BLOCK DIAGRAM
FLP80DOS
MONITOR
+
~
J
J
DE8UGGER
(DDT)
LINKER
(LINK)
OEM
APPLICATION
;
PERIPHERAL
INTERCHANGE
PROGRAM
(PIP)
~
Z80
ASSEMBLER
(ASM)
RELOCATING
LINKAGE
LOADER
(RLL)
1
TEXT
EDITOR
(EDIT)
;
;
;
t
;
t
- -- -- --
-
-- -- -- -
J
-- -
t
-- --
-- -- -- -- -- --
1/0 CONTROL
SYSTEM
(lOCS)
t
~
J
CONSOLE
DEVICE
HANDLER
LINE
PRINTER
HANDLER
f
;
HARDWARE
UART
;
I
FLOPPY DISK
HANDLER
(FDH)
!
OTHER
DEVICE
HANDLERS
j
DISK
CONTROLLER
FIRMWARE
HARDWARE
PIO
1
DD
LINE
PRINTER
CONSOLE
- -
CLOPPY DISK UNITS)
AND
FLP-80 BOARD
ORDERING INFORMATION
DESIGNATOR
DESCRIPTION
PART NO.
FLP-8000S
SOE based development system software (SO PROMs)
MK78142
FLP-8000S
MO based development system software (MO PROMs)
MK77962
FLP-8000S Operations Manual Only
MK78557
XI-42
-
IJ
UNITED
TECHNOLOGIES
MOSTEK
SOFTWARE PRODUCTS
FLEXIBLE DISK OPERATING SYSTEM - M/OS-80
USER FEATURES
M/OS-SO provides a direct migration path to CP/M
compatibility without any changes to the system hardware.
o CP/MTM compatibility gives the user many available
programs to choose from.
o
o
Additional utilities and systems commands provide
increased capability and functionality to the user.
Provided on standard media for use with Mostek
standard systems and MD Series boards for short system
integration time.
INTRODUCTION
MO/S-SO is a CP/MTM compatible, floppy disk operating
system for the MD or SO series of microcomputer board
systems. It offers a comprehensive solution to a wide variety
of system design problems. The software is provided on an
S-inch single-sided, single-density floppy diskette which
can be booted on Mostek disk-development systems or
user-configured systems (see "Hardware Required"
paragraph). M/OS-SO can be altered for different
inputloutput hardware configurations by using the
MOSGEN Utility (sold separately).
Several powerful utilities are provided with M/OS-SO.
These programs give the user a broad base of support and
will improve design efficiency. These include:
Editior (Edit)
Designer's Development Tool (Debugger)
Transfer Utility (XFER)
FilelDisk Dumps (DSKDUMP)
Print Utility (PRINT)
Print Spooler (SPOOL)
Several System Utilities
M/OS-SO is a more sophisticated and powerful floppy disk
operating system than any other micro-operating system
available. It provides the user with a unique, but invisible,
library structure. By assigning one system disk as a Master
Library disk, the system can free the user to place all
application-related files on another disk while still having
the utility of the various system programs on-line.
Unlike other operating systems, M/OS-SO provides the
user with comprehensive error messages. In most cases,
methods of recovery are displayed and the operator is given
several options from which to choose.
HARDWARE REQUIRED
M/OS-SO is currently supplied in three versions. V3 is
designed to run on Mostek's MATRIX systems and on
systems built with MD Series boards. An MD Series system
must contain the following boards:
Item
Processor
Console Interface
Pri nter Interface
Floppy Interface
Memory
Hardware Required
MDX-CPU1 or MDX-CPU2
MDX-EPROM/UART or MDX-SIO
MDX-PIO or MDX-SIO
MDX-FLP1 or MDX FLP2
(2) MDX-DRAM with 64K of RAM
The V5 system is for use with a Mostek Phantom PROM
system configuration. The following boards are required:
Because of M/OS-SO's C/PM compatibility, a large
number of pre-written programs are available. M/OS-SO is
designed to run programs written for other CP/Mcompatible operating systems, such as CDOSTM, I/OSTM,
and SDOSTM, provided these programs conform to the
standards described by Digital Research in versions 1.4
through 2.2. Virtually all compilers and interpreters now
sold for use on CP1M (versions 1.4 -2.2) will work. For those
Mostek customers who are currently running FLP-80DOS,
CP/M is a Trademark of Digital Research, Inc.
COOS is a Trademark of Cromemco, Inc.
SYSTEM FEATURES
Item
Processor
Floppy Interface
Memory
Hardware Required
MDX-CPU3 or MDX-CPU4
MDX-FLP2
(2) MDX-DRAM with 64K of RAM
(required only for MDX-CPU4)
The V6 system is for use with a Mostek Phantom hard-disk
system. The following boards are required:
SDOS is a Trademark of SO Systems, Inc.
I/OS is a Trademark of Infosoft Systems, Inc.
XI-43
II
Item
Processor
Floppy Interface
Memory
Hard Disk
Interface
Hardware Required
MDX-CPU3 or MDX-CPU4
MDX-FLP2
(2) MDX-DRAM with 64K of RAM
(required only for MDX-CPU4)
Delete a line(s) or character(s)
Put a block of text into another file
Get a block of text from another file
View text on the console screen
Print text on the line printer
Create a set of commands which can be executed
as a macro
MDX-SASI1
XFER - Transfer Utility
With either the V3, V5 or V6, M/OS-80 requires 64K bytes
of RAM for operation. Four bootstrap PROMs are supplied
with V3, and one bootstrap PROM is supplied with V5 or V6.
The system initially must have at least one 8-inch, singlesided, single-density floppy disk drive in order to boot-up
M/OS-80. Up-to-four disk drives are supported. The V6
configuration can also boot-up from hard disk.
The XFER'program is a general-file transfer utility. It allows
for the moving of files from disks or devices to other (or the
same) disks or devices. The XFER features include:
Transfer an ASCII file
Compare two files without moving
Filter out i"egal ASCII characters
Conditionally transfer a file (user prompted)
Transfer a Read-Only file
Expand tabs
Verify files after moving
Print HEX address of comparison failure
Transfer only old files
Transfer only new files
Table 1 details the peripheral and CPU configurations
required for the M/OS-80 versions.
MiaS-SO CONFIGURATION SUMMARY
Table 1
DSKDUMP - Disk Dump
PERIPHERALS
CPU1
CPU2 CPU3 CPU4*
UART Console
SIO Console
STI Console
SIO Line Printer
Pia Line Printer
STI Line Printer
FLP1
FLP2
SASI
V3
V3
V3
V3
N/A
N/A
N/A
N/A
V5
V5**
V5
V5**
N/A
N/A
N/A
V3**
V3
V3**
V3
N/A
N/A
N/A
N/A
V5
V5
V3
V3***
*
V3
V3***
*
N/A
N/A
V5
V6
V5
V6
The DSKDUMP program allows reading or modifying of a
file, the disk data area, or the disk directory. Each block
requested is read into a 128-byte buffer, then displayed. The
blocks are numbered sequentially. Any block can be
selected, displayed, modified, and written back to the disk.
PRINT - Print Utility
Not Applicable.
Future Design.
SIO line printer configuration is supplied as alternate
on systems disk.
Single-density only.
NOTE:
1. MOSGEN Utility may be purchased to configure systems for different peripherals
and smaller sizes of RAM. See the MOSGEN Data Sheet for more information.
EDIT - Text Editor
The ASC" EDITor file provided with M/OS-80 provides a
text editor for users who do not have access to a screeneditor. The editor allows creation and modification of the
text files by several easy-to-use commands. EDIT features
include:
Find a text string
Change a text string
Find a line
Insert new text
The PRINT utility formats ASCII files to the CRT or printer
with automatic headings, tabbing and pagination. Userspecified options include page width and length, page
headings, date printed of the top of each page, and page
formatting.
SPOOL - Print Spooler
The SPOOL file system feature is used to output a file from
the printer to a system list device while the system
continues with otherfunctions. Any ASCII file maybe spoolprinted, and direct printer activity is prevented while a spoolprint is active.
Other System Utilities
M/OS-80 provides several other system utilities to permit a
user the highest degree of flexibility in the manipulation of
the files and programs created and used with the system.
Some of these utilities include: programs to format disks,
change disk labels, examine directories, and to diagnose
disk problems. A PROM programming utility is also included
that interfaces with Mostek's PPG 8/16.
XI-44
ORDERING INFORMATION
DESIGNATOR
DESCRIPTION
PART NO.
M/OS-SOV3
One diskette containing all MiaS-SO programs in binary, four
bootstrap PROMs, and one Operations Manual. (See Table 1 for
hardware configuration requirements.) Requires the signed
Software License Agreeement (enclosed) with purchase order.
MK71 01 OC-S1
M/OS-SOV5
One diskette containing all MiaS-SO programs in binary, one
bootstrap PROM, and one Operations Manual. (See Table 1 for
hardware configuration requirements.) Requires the signed
Software License Agreement (enclosed) with purchase order.
MK71 011 C-S1
M/OS-SOV6
One diskette containing all MiaS-SO programs in binary, one
PROM for booting from floppy or hard disk, and an Operations
Manual. (See Table 1 for hardware configuration requirements.)
Requires the signed Software License Agreement (enclosed)
with purchase order.
MK71012C-S1
MiaS-SO
Operations
Manual
Detailed description of the operation and use of the
MiaS-SO software package.
4420064
II
XI-45
XI-46
UNITED
~ TECHNOLOGIES
SOFnNAREPRODUCTS
MOSTEK
MOSGEN UTILITY
MK71001
USER FEATURES
D Adapts M/OS-SO to customized MDX and SD systems.
D Allows tailoring M/OS-SO for different
1/0 devices and
RAM sizes.
D Works on systems configured around the DDTIDCF
PROMs or Phantom PROM.
D Menu driven format to speed the configuration process.
DESCRIPTION
Mostek's MOSGEN Utility is a system generation package
used to generate unique configurations of the M/OS-SO
Operating System. MOSGEN allows the user to modify the
M/OS-SO by rewriting existing 1/0 drivers or creating new
drivers for specialized I/O operation, and configuring
different system RAM sizes.
MOSGEN allows creation of a command file which will link
a newly customized system. The MOSGEN package also
includes a set of object and source files to provide the user
with a valid set of device drivers. These drivers are provided
to help the user create new drivers based on knownworking examples. Users are permitted to modify or select
drivers for the following logical-unit devices:
•
•
•
•
•
•
•
System Console (output)
Keyboard (input)
List
Punch
Reader
Disk
Clock
MOSGEN is supplied on two single-sided, single-density
S-inch diskettes. They are the System Generation diskette
and the Device DriverslLibrary diskette.
MOSGEN OPERATION
The MOSGEN package creates a batch submit (.CMD) file
which, when executed, walks the system through the
complex re-assembly, trial linkage, and final linkage process
automatically and without operator intervention. The last
steps of the MOSGEN-created batch file test the newlycreated system for errors in linkage, size, and conformity to
system restrictions. The user-supplied drivers are linked
into the main core of the system during this linkage process.
A special linkage editor is provided for the sole purpose of
this system generation link. MOSGEN proves itself useful. if
not essential. when system restrictions limit the amount of
available RAM in the target system, or require the use of
non-standard peripherals or special-intelligent 1/0 drivers.
MOSGEN may be used to configure M/OS-SO for different
sizes of RAM in the user system down to a minimum of 24K
bytes.
MOSGEN SYSTEM REQUIREMENTS
MOSGEN and all related software require the userto have a
running 64K M/OS-SO system in place. Depending on the
requirements of the users development languages, the
system memory requirements may be in excess of the 32K
bytes of RAM required for a minimum M/OS-SO system.
II
XI-47
ORDERING INFORMATION
DESIGNATOR
DESCRIPTION
PART NO.
MOSGEN Utility
Two diskettes containing MOSGEN system generation utilities
and device drivers, both source and object files, and one
Operations Manual. A signed Software License Agreement is
required with purchase order.
MK71 001 C-80
MOSGEN
Operations Manual
Detailed description of the operation and use of the MOSGEN
Utility.
4420270
XI-48
..
1982/1983 MICROELECTRONIC DATA BOOK
Military and High Reliability Products
INTRODUCTION
devices are screened to a subset of 883B requi rements and
offer high reliability at significantly reduced cost (see the
following sections for more detail concerning MKI
products).
Overview
Mostek's Military/Hi-Rei Products Department serves the
special needs of the Defense, Aerospace and Commercial
Hi-Rei markets. The organization's principal objective is to
provide Mostek's state-of-the-art products screened to MILSTD 883 Class B, Methods 5004 and 5005.
Quality Conformance/Reliability
Mostek has been providing MKB versions of selected
memory products since 1978. Quality conformance
inspections in accordance with Method 5005 of MIL-STD883 area central part of MKB screening procedures. Group
A inspections are performed on a 100% basis to the
requirements contained in the detail specification (Mostek
data sheet). Group B, C and D inspections are performed
periodically per the requirements of MIL-STD-883.
Traditional Military IC manufacturers have met stringent
Military reliability requirements at a cost of being several
years behind the state-of-the-art in commercial products.
Mostek Military brings the leading edge in high reliability
RAM, ROM, EPROM, Gate Array and microprocessor
devices to the Military systems designer today. As MIL-M38510 slash sheets are announced, the Military Products
Department will qualify Mostek's products in the JAN
38510 program. Mostek has already received QPL listing of
its 4116 dynamic RAM. Designated JM-3851 01240, this
device is one of the most advanced MOS circuits to receive
QPL listing to date.
A data report documenting the results of Group B, C and D
testing is available.
For more information contact:
The Military Products Department is also heavily engaged in
the development of high density lead less chip carrier
packaging technology. Most circuits are cu rrently offered in
carriers or planned for the near future.
Mostek Corporation
Military Products Department
Mail Station 1100
P.O. Box 169
Carrollton, Texas 75006
Product offerings are broken into two categories. Devices
prefixed "MKB" are screened to the full requirements of
MIL-STD-883 Class B. "MKI" (Industrial grade) prefixed
Telephone - (214) 323-7926/7718
TWX - 910-860-5856
Telex - 730423
APPLICATION
Military/Aerospace
TYPE OF
SYSTEM
Ground Airborne
MOSTEK
HI-REL TYPE
MKB/
MKI
Industrial
Commerical
Medical
Automotive
InstrumenTactical
Process InstrumenTelecom Instrumen- FAA Airborne
Space
tation
Control
tation
Missile
tation
MKB/JAN
Class.
,S
Equiv,
MKI
XII-1
MKB/MKI
MKI
£I
SCD PROGRAM SIMPLIFIES DESIGN ACCEPTANCE
AND DOCUMENTATION
To speed up the documentation cycle for government
acceptance of a "non-standard part", Mostek has
developed an innovative customer-oriented program. It's
called Support-Customer-Documentation (SCD). This
ready-made source control document is a complete
procurement specification, per MIL-STD 883 Class B
(Mostek MKB), for those devices without an existing
DESC drawing or slash sheet. Patterned after DESC mini
specifications, SCD provides a reliable, detailed spec. So
detailed, in fact, that the only additional items required
are your company's name and part number.
The Mostek SCD documents are available for all new
military devices and will be written around DOL103
Guidelines for DESC Selected Item Drawings.
MOSTEK MILITARY /HI-REL SCREENING ATTRIBUTES
JAN-(MIL-M-38510 Slash Sheet)
MKI-(Industrial Grade)
• QPL listed, qualified per MIL-M-3851 0, Class B
• Cost-effective: Nominal cost-adder over commerical
hermetic devices, generally half of MKB (883B) cost
• Tested to MIL-STD 883B, MIL-M-38510, and
appropriate military specifications
• Greater reliability than commercial device
• Produced in DESC-certified domestic wafer fabrication,
assembly and test facilities
• Eliminates logistics problems caused by sending units
to outside burn-in labs
MKB-(MIL-STD-883)
• Built-in reliability -40°C to +85°C operating range
• Compliance with MIL-STD 883, Method 5004, Level B
• 44 hours minimum, 125°C MIL burn-in
• 112 to 1/3 the cost of JAN circuits
• Hermetic packaging
• Quality conformance testing per method 5005, Groups
B,C,D
• 0.4% parametric and functional outgoing AQL
• No charge for Group B, C and D generic data
• Available for most Mostek RAM, EPROM and
microprocessor components
• Group A data summary and certificate of compliance
included with all shipments
• Off-the-shelf delivery from factory and distributor stock
• 10% burn-in PDA
• Available for broad spectrum of VLSI, RAM, ROM,
EPROM and microprocessor devices
XII-2
SCREENING AND LOT CONFORMANCE COMPARISON
ACTIVITYI
SCREEN
MKI
(INDUSTRIAL)
MKB (883B
METHOD 5004)
JAN
Die Inspection
Pre-Seal Inspection
Stabilization Bake
Temperature Cycle
Centrifuge
Fine Leak
75X Mostek Spec.
30X-60X Mostek Spec.
2010 Condo
2010 Condo
1008 Condo
1010 Condo
2001 Condo
1014 Condo
B
B
C
C
E
C
2010 Cond.B
2010 Condo B
1008 Condo C
1010 Condo C
2001 Condo E
1014 Condo C
Gross Leak
Mostek Spec.
1014 Condo C
1014 Condo C
Voltage Stress
(DRAMs Only)
1015 Condo D
10 Hrs. Min., 125°C
1015 Condo D
10 Hrs. Min., 125°C
Per Slash
Sheet
Burn-In
1015 Condo D
44 Hrs. Min.
125°C dynamic
1015 Condo D
160 Hrs. Min.
125°C dynamic
1015 Condo D
160 Hrs. Min.
125°C dynamic
Electrical Tests
Method 5005 Group
A electrical subgroups,
testing conditions and
limits which guarantee
AC, DC and functional
performance over full
temp. range.
Group A tests for AC,
DC and functional performance at detail
spec. min. and
max. temp.
Tests for AC, DC and
func. performance in
conformance with
slash sheet.
External Visual
Visual tests to guarantee
marking, construction
and mechanical integrity
2009
2009
OA Lot Acceptance
Method 5005 Group A
sample testing to guarantee performance to
data sheet over full
temp. range.
5005 Group A and
C.ofC.
5005 Group A and
C.ofC.
5005 Groups B, C, D
5005 Groups B, C, D
Quality Conformance
5 Cycles, 101 0 Condo C
2001 Condo D, 20 Kg, Yl
1014 Condo B, 1 x 10-7
atm cc/sec
,
><'11-3
PART NUMBER ORDERING INFORMATION
EXAMPLE:
I
PARTTVPE
SCREENING
MKB=MIL-STO-883
Level B testing
MKI=lndustriaI/Commercial hi-rei
screening
MKB 3880 P- 83
=r- =rr
i
I
Mostek
device name
-r:=::;-------,I
PACKAGE
TEMPERATURE
SPEED
D=dual density
RAM-PACTM
E=leadless chip
carrier: JEDEC
7=lndustrial Range
(-400 to +85°C)
8=Military Range*
(device dependent)
One or two number
designator denoting
access time. Device
dependent)
ElF
F=flat package
J=cerdip
P=side-brazed DIP
MKIINDUSTRIAL PRODUCTS LISTING
Product
Organization
Device
Packages
Temp.
Range
Access Time
or Frequency
Dynamic RAMs
MKI4116-72
MK14116-73
MK14116-74
MKI4564-72
16K x 1
16K x 1
16K x 1
64Kx 1
J
J
J
J
-40°CI+85°C
-40°CI+85°C
-40°CI+85°C
-40°CI+85°C
150ns
200ns
250ns
150ns
Static RAMs
MK14118A-71
MKI4118A-72
MK14118A-73
MK14802-790
MK14S02-71
1Kx8
1Kx8
1Kx8
2Kx8
2Kx8
J
J
J
J
J
-40°CI+85°C
-40°CI +85°C
-40°CI+85°C
-40°CI+85°C
-40°CI +85°C
120 ns
150 ns
200ns
90 ns
120 ns
ROMs
MKI37000-74t
8Kx8
J
-40°CI+85°C
300ns
EPROMs
MKI2716-77
MK12716-78
2Kx8
2Kx8
J
J
-40°CI +85°C
-40°CI+85°C
390ns
450ns
Microprocessors
MK138SO-70
MK138SO-74
MK13881-70
MKI3881-74
MK13882-70
MK13882-74
Z80 CPU
ZSOACPU
ZSOPIO
ZSOPIO
ZSOCTC
Z80CTC
P
P
P
P
J
J
-40°CI +85°C
-40°CI +85°C
-40°CI +85°C
-40°CI+85°C
-40°CI +85°C
-40°CI+85°C
2.5 MHz
4.0 MHz
2.5 MHz
4.0 MHz
2.5 MHz
4.0 MHz
t1982 Introduction
JAN PRODUCTS LISTING
Product
Device
JAN
JM-385101
Dynamic
24001 BEC
RAMs(4116) JM-3851 01
24002 BEC
Organization
Pkgs.
16Kx 1
P
16Kx 1
P
Access
Times/Freq.
Active
Power
Standby
Power
-55°CI+110°C
200 ns
462mW
30mW
-55°CI+110°C
250 ns
462mW
30mW
Temp.
Range
XII-4
MKB MILITARY PRODUCTS LISTING
Access
Times/Freq.
Active
Power
Standby
Power
-55°C/+110°C
-55°C/+110°C
-55°C/+11O°C
-55°C/+110°C*
-55°C/+11O°C*
-55°C/+110°C*
-55°C/+11O°C*
-55°C/+110°C
-55°C/+11O°C
150 ns
200 ns
250 ns
120 ns
150 ns
200 ns
250 ns
200 ns
250ns
462mW
462mW
462mW
30mW
30mW
30mW
495mW
495mW
60mW
60mW
E,J
E,J
E,J
E,P
E,P
E,P
E,P
E,P
E,P
E,P
E,P
E,P
-55°C/+125°C
-55°C/+125°C
-55°C/+125°C
-55°C/+125°C*
-55°C/+125°C*
-55°C/+125°C
-55°C/+125°C
-55°C/+125°C
-55°C/+125°C
-55°C/+125°C*
-55°C/+125°C
-55°C/+125°C
250ns
300 ns
350ns
85 ns
70ns
150 ns
200 ns
90 ns
120 ns
90ns
120 ns
200 ns
150mW
150mW
150mW
53mW
53mW
53mW
500mW
500mW
8Kx8
8Kx8
8Kx8
P
P
E,P
-55°C/+125°C
-55°C/+125°C
-55°C/+125°C*
250ns
300 ns
300 ns
220mW
220mW
165mW
·55mW
55mW
45mW
MKB2716-86
MKB2716-87
MKB2716-88
2Kx8
2Kx8
2Kx8
E,J
E,J
E,J
-55°c/+125°C
-55°C/+125°C
-55°C/+125°C
350ns
390 ns
450ns
633mW
633mW
633mW
165mW
165mW
165mW
MKB38SO-SO
MKB38SO-84
MKB3881-80*
MKB3881-84*
MKB3882-80*
MKB3882-84
MKB3884/5I7t
Z80CPU
Z80ACPU
ZSOPIO
ZSOPIO
ZSOCTC
Z80CTC
zaOSIO
P
P
P
P
P
-55°C/+125°C
-55°C/+125°C
-55°C/+125°C
-55°C/+125°C
-55°C/+125°C
-55°C/+125:j:C
-55°C/+125°C
2.5 MHz
4.0 MHz
2.5 MHz
4.0 MHz
2.5 MHz
4.0 MHz
1.0W
1.0W
Organization
Pkgs.
MKB4116-82
MKB4116-83
MKB4116-84
MKB4516-81
MKB4564-82
MKB4564-83
MKB4564-84
MKM4332-83
MKM4332-84
16K x 1
16K x 1
16K x 1
16K x 1
64K x 1
64Kx 1
64K x 1
32Kx 1
32Kx 1
E,F,J
E,F,J
E,F,J
E,P
E,P
E,P
E,P
D
D
MKB41 04-84
MKB41 04-85
MKB4104-86
MKB4167 -885
MKB41 67 -870
MKB4118A-82
MKB4118A-83
MKB4S01 A-890
MKB4801A-81
MKB4S02-890*
MKB4S02-81
MKB4802-83
4Kx 1
4Kx 1
4Kx 1
16K x 1
16K x 1
1Kx8
1Kx8
1Kx8
1Kx8
2Kx8
2Kx8
2Kx8
ROMs
MKB36000-83
MKB36000-84
MKB37000-84*
EPROMs
Microprocessors
Product
Dynamic
RAMs
Static RAMs
RAMs
Device
P
P
Temp.
Range
*1982 Introduction
tPlanned
XII-5
630mW
630mW
630mW
XII-6
MOSTEI(.
MILITARYIHIGH REL PRODUCTS
Test Report
QUALITY CONFORMANCE
TEST REPORT
GROUPS B. C AND D
1978 - 1981
NOTE:
This report covers testing performed through June 1981. For a more recent report.
cOntact your local Mostek representative.
XII-7
GROUP B INSPECTION - METHOD 5005.7
Chart 1
TEST
Subgroup 1
Physical dimension
Subgroup 2
Resistance to
solvents
Subgroup 3
Solderability
METHOD
CONDITIONS
2016
2 devices
(No failures)
2015
4 devices
(No failures)
2003
Soldering temperature of 260
± 10°C
Subgroup 4
Internal visual and
mechanical
CLASS B
15 leads
(3 units min
(No failures)
2014
Failure criteria from design
and construction requirements of
applicable procurement document
1 device
(No failures)
2011
Test condition C or 0
15 Bonds
(10 units min
(No failures)
1018
1.000 PPM max @ 100°C
3 devices
(No failures)
Subgroup 7
Seal
1014
As Applicable
5
Subgroup 8
Electrical parameters
ESD sensitivity
Electrical parameters
Group A. Subgroup 1
3015 Test Condition A or B
Group A. Subgroup 1
Subgroup 5
Bond strength
Subgroup 6
Internal water vapor
content
XII-S
15
GROUP C INSPECTION - METHOD 5005.7
Chart 2
TEST
METHOD
CONDITIONS
CLASS B
LTPD
Subgroup 1
Operating Life Test
1005
Test conditions to be specified
1000 hours @ 125°C
As specified in the applicable
detail specification
5
1010
2001
1014
Test condition C
Test condition E, Yl axis
As applicable
15
End point electricals
Subgroup 2
Temperature cycling
Constant acceleration
Seal
Fine
Gross
Visual examination
End point electrical
parameters
1010
As specified in applicable device
specification
II
XII-9
GROUP D INSPECTION - METHOD 5005.7
Chart 3
TEST
METHOD
Subgroup 1
Physical dimensions
2016
Subgroup 2
Lead integrity
Seal
Fine
Gross
Lid torque
Subgroup 3
Thermal shock
Temperature cycling
Moisture resistance
Seal
Fine
Gross
Visual examination
End point electrical
parameters
Subgroup 4
Mechanical shock
Vibration, variable freq.
Constant acceleration
Seal
Fine
Gross
Visual examination
CONDITIONS
LTPD
CLASS B
LTPD
15
2004
1014
Test conditions B2 (lead fatigue)
As applicable
2024
As applicable
1011
1010
1004
1014
Test condition B, 15 cycles
Test condition C, 100 cycles
15
15
As applicable
100412009
As specified in the applicable
device specification
2002
2007
2001
1014
Test condition B
Test condition A
Test condition E, Yl Axis
As applicable
15
1010 or
1011
End point electrical
parameters
Subgroup 5
Salt atmosphere
Seal
Visual examination
Subgroup 6
Internal water vapor
content
Subgroup 7
Adhesion of lead finish
As specified in the applicable
device specification
1009
1014
1009
Test condition A
As applicable
Paragraph 3.3.1 of Method 1009
15
1018
5,000 ppm max @ 100°C
3 devices
(No failures)
2025
15
XII-10
GROUP 8 TEST RESULTS
Chart 4
Package
Subgroup
8-4
8-1
8-2
8-3
8-5
Year Sam les Rejects Samples Rejects Samples Rejects Samples Rejects Sam les Rejects
16 Pin*
P package
(side brazed)
1979
1980
1981
30
28
20
0
0
0
51
67
48
3
0
0
16 Pin
J package
(CERDIP)
1979
1980
1981
74
50
18
0
0
0
119
46
37
16 Pin
F package
(flatpack)
1979
1980
1981
154
52
85
0
0
0
18 Pad
E.package
(chip carrier)
1979
1980
1981
14
10
18 Pin
P package
(side brazed)
18 Pin
J package
(CERDIP)
1979
1980
0
0
0
17
16
13
0
0
0
80
70
302
0
0
2
1
0
0
42
39
30
114
39
29
0
0
1
42
21
9
0
0
0
281
89
225
0
0
1
324
105
248
0
0
0
195
75
154
0
0
0
84
23
45
0
0
1
700
76
1075
1
0
2
0
0
18
4
0
0
18
16
0
0
7
5
0
0
36
125
0
0
8
0
16
0
12
0
4
0
16
0
1979
1980
1981
8
28
6
0
0
0
12
47
12
0
0
0
12
24
9
0
0
0
4
12
8
0
0
2
0
0
4
24 Pin
P package
(side brazed)
1979
1980
1981
34
30
10
0
0
0
60
43
24
0
0
0
66
33
15
0
0
0
19
15
5
0
0
0
40
48
75
128
! 60
325
24 Pin
T package
(side brazed
w/window)
1979
1980
1981
15
16
0
0
24
43
0
1
18
30
0
0
9
9
0
0
162
176
0
0
24 Pin
J package
(w/window)
1980
1981
45
28
0
0
15
61
0
0
15
64
0
0
15
14
0
0
15
375
0
9
40 Pin
P package
(side brazed)
1981
4
0
4
0
7
0
2
0
50
0
0
0
2
*Includes data from M3851 0124001 BEC (JAN MKB4116P) subgroups 6 (water vapor and 7 (VZAP) passed with no failures.
II
XII-11
GROUP C TEST RESULTS
Chart 5
Subgroup
C-1
Samples Rejects
C-2'
Samples Rejects
C-3
Samples Rejects
Microcircuit Group2
Device Type
Year
46-NMOS RAM
STATIC
1979
1980
1981
440
430
213
0
0
3
108
100
50
0
2
1
152
152
76
0
0
0
DYNAMIC
1979
1980
1981
1306
755
214
5
3
3
294
230
50
1
1
0
380
338
76
0
0
0
JAN1240
1980
105
2
25
0
110
0
MASK ROM
1979
1980
1981
330
215
315
3
1
3
108
54
75
3
1
0
152
76
114
0
0
0
UVEPROM
1980
1981
210
107
2
2
50
25
0
1
76
38
0
0
47-NMOS ROM/PROM
NOTES: 1) Subgroup C-2 testing is performed following the completion
of Subgroup C-l testing,
2) See Chart 7 for Microcircuit Group Assignment.
FAILURE RATE CALCULATIONS
Chart 6
Based upon Group C testing per MIL-M-3851 0, failure rates for the following devices have been determined,
Hours
Failure Rate
at 125°C
Average
Activation
Energy
Failure Rate
at 70°C
Failure Rate
at 55°C
2716
317,000
0.63 %/Khr
0.8eV
,015%/Khr
.0044%/Khr
36000
860,000
0.814
0.68
.034
,012
4027
537,000
0,372
0.61
,022
,0085
4104
977.000
0.102
0,57
.0071
.0030
4116
1,738,000
0.288
0.76
.0083
,0026
4118
106,000
1.89
0.67
.083
.029
Device
NOTES: 1) Derating performed using the Arrhenius equation, Refer to
the Reliability Report for more information,
2) Activation energies based upon analysis of Group Cfailures,
XII-12
GROUP D TEST RESULTS
Chart 7
Subgroup
D-1
D-2
D-3
D-4
D-5
D-6
D-7
Sam. Rej. Sam. Rej. Sam. Rej. Sam. Rej. Sam. Rej. Sam. Rej. Sam. Rej.
Package
Year
16 Pin P'
1979
1980
75
50
0
0
29
50
0
0
75
75
o
o
80
50
0
50
50
0
0
1979
1980
1981
125
50
50
0
0
0
75
50
50
0
0
0
55
80
50
6
1
o
180
50
50
9
0
0
151
50
50
2
0
0
16 Pin F
1980
25
0
25
0
25
6
25
0
25
3
18 Pad E
1980
25
0
25
0
47
o
47
4
25
2
18 Pin P
1979
26
0
25
0
30
o
30
0
25
18 Pin J
1980
1981
25
75
0
0
50
75
0
0
25
75
o
1
50
75
0
0
50
75
1979
1980
1981
76
76
25
0
0
185
50
25
0
0
0
77
50
25
o
o
47
75
25
3
2
0
1980
1981
32
25
0
32
25
0
0
32
25
o
0
1
32
25
0
0
1980
24
0
58
0
53
o
97
16 Pin J
24 Pin P
24 PinJ
24 Pin T
0
o
1
6
o
30
o
0
0
15
o
45
o
27
50
25
0
0
0
3
o
15
o
106
25
0
0
5
o
15
o
25
0
NOTES: 1) Includes M3851 0/24001 BEC (JAN 4116)
2) Subgroups 6 and 7 added in Method 5005.7 dated
4 Nov. 1980
II
XIJ-13
MICROCIRCUIT GROUP ASSIGNMENTS PER MIL-M-38510E
Chart 8
Microcircuit Group 46
NMOS RAM
MKB4027
MKB4116
MKB4104
MKB4118
4KX 1
16KX 1
4KX 1
1K X 8
Dynamic RAM
Dynamic RAM
Static RAM
Static RAM
16 pin
16 pin
18 pin
24 pin
Microcircuit Group 47
NMOS ROM/PROM
MKB2716
MKB36000
2K X 8
8K X 8
UV Eraseable PROM 24 pin
ROM
24 pin
XII-14
MOSTEI(.
MILITARYIHIGH-REL PRODUCTS
Processed to MIL-STD-883, Method 5004, Class B
2048 X 8-Bit UV Erasable PROM
MKB2716(J/E)-86/87/88/90
FEATURES
o Military temperature range (-55°C :5 TA:5 +125°C)
PIN
Access Time
MKB2716-86
350 ns
MKB2716-87
390 ns
MKB2716-88
450 ns
MKB2716-90
550 ns
o
Qualified per Method 5005, MIL-STD 883. Group B, C, D
data report available
o
Available processed to DESC selected item drawing
number 78022 (part no. 7802201 JX)
o
Pin compatible with Mostek's BYTEWYDpM memory
family
o
Single +5 volt power supply during read operation
o
Single programming requirement: single
programming with one 50 msec pulse
o
Low power dissipation: 663 mW max active, 165 mW
max standby
o
Industrial MKI version available (-40°C to 85°C)
o
Three state output OR-tie capability
o
Five modes of operation for greater system flexibility (see
Table)
location
o TIL compatible in all operating modes
o
Standard 24 pin JEDEC DIP pinout
DESCRIPTION
The MKB2716 is a 2048 x 8 bit electrically programmablel
ultraviolet erasable read only memory. The circuit is
fabricated with Mostek's advanced N-channel silicon gate
technology for the highest performance and reliability. The
MKB2716 offers significant advances over hardwired logic
cost, system flexibility, turnaround time and performance.
BLOCK DIAGRAM
Figure 1
The device has many useful system oriented features
including a standby mode of operation which lowers power
from 633 mW maximum active power to 165 mW
maximum for an overall savings of 75%.
Programming is done with a single TTL level pulse, and may
E-PACKAGE
A62
24 vcc
23 AS
A53
A44
22 Ag
21 vpp
A71
DE
CE/PGM
AO
THRU
AlO
A3 5-
20 OE
A26
19 A,o
A4
7~
~9'
A17
18CE/PGM A,
Aoa
17 DQ7
DQo 9
16 DQ6
AD,,:
DQ11O'
DQ211
15 DQs
IIIC :'2;
VSS12
130Q3
14 DQ4
LEADLESS
CHIP CARRIER
A3 _8;
III
TOP VIEW
A, :'0'
DQo
~'~3:
'14:
~~: ~~~
;9:
r;~
DQ 1DQ 2 V ssNCOQ 3 DQ4 OQ5
16.384 BIT
CELL MATRIX
PIN NAMES
Ao - AlO
Addresses
~Oa
CE/PGM
Chip Enablel
Program
OE
Vss
'Inputs in Program Mode
XII-15
- DQ7
Data Outputs'
Output Enable
Ground
ABSOLUTE MAXIMUM RATINGS*
Voltage on any pin relative to Vss (Except V pp ) ................................................... -0.3 V to +6 V
Voltage on Vpp supply pin relative to Vss' ................................................•..... -0.3 V to +28 V
Operating Temperature TA (Ambient) .................................................... -55°C ~ TA ~ +125°C
Storage Temperature (Ambient) ......................................................... -65°C ~ TA ~ +125°C
Power Dissipation ...............•.................................................................. 1 Watt
Short Circuit Output Current .......................................................•................. 50 mA
*Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
READ OPERATION
RECOMMENDED DC OPERATING CONDITIONS
(-55°C ~ TA ~ 125°C)
SYM
PARAMETER
TYP
V IH
Input High Voltage
2.0
V cc +l
V
V IL
Input Low voltage
-0.1
0.8
V
MIN
MAX
UNITS NOTES
DC ELETRICAL CHARACTERISTICS'·2.4-.
(-55°C ~TA~ 125°C)(Vcc = +5 V ± 10%, Vpp= V Cd2
~
SYM
PARAMETER
ICCl
"
MIN
TYP
MAX
Vcc Standby Power Supply
Current (OE = V IL; CE = V IH )
10
30
mA
2
Icc2
V cc Active Power Supply
Current (OE = CE = V IL)
57
43
115
90
mA
2,10
IpPl
Vpp Current (Vpp = 5.5 V)
2.0
10
mA
2
V OH
Output High Voltage
(lOH = -400 j.J.A)
VOL
Output Low Voltage
(lOL = 2.1 mAl
.45
V
IlL
Input Leakage Current
VIN = 5.5 V)
10
j.J.A
IOL
Output Leakage Current
(V OUT = 5.5 V)
10
j.J.A
TA = -55°C
TA - +125°C
2.4
UNITS NOTES
V
AC ELECTRICAL CHARACTERISTICS'·2.5
(-55°C ~ TA ~ 125°C) (Vcc = +5 V ± 10%, Vpp = V Cd2
-86
-87
-88
-90
MIN
MAX UNITS NOTES
SYM
PARAMETER
t ACC
Address to Output Delay
(CE = OE = Vld
350
390
450
550
ns
tCE
CE to Output Delay
(OE = V IL)
350
390
450
550
ns
5
tOE
Output Enable to Output
Delay (CE = Vld
150
150
150
180
ns
9
tDF
Chip Deselect to Output
Float (CE = Vld
0
130
ns
8
tOH
Address to Output Hold
(CE = OE = V IL)
0
MIN
MAX
130
MIN
MAX
0
0
XII-16
130
MIN
0
0
MAX
130
0
0
ns
CAPACITANCE
(TA
= 25°C)
SYM
PARAMETER
TYP
MAX
UNITS
NOTES
CIN
Input Capacitance
4
6
pF
6
COUT
Output Capacitance
8
12
pF
6
READ OPERATION NOTES:
1. Vee must be applied at the same time or before Vppand removed atteror at
the same time as Vpp.
2. Vpp and Vee may be connected together except during programming. With
Vpp = VCC. the supply current is the sum of ICC and IpPl·
3. All voltages with respect to VSS.
4. load conditions::: 1 TTL load and 100 pf, tr =tf =
ns, reference levels are
1 V and 2 V for inputs and .8 V and 2 V for outputs.
5. tOE is referenced to EE or the addresses, whichever occurs last.
20
6. Efhictive Capacitance calculated from the equation C;: t::. Qwhere 6. V = 3V.
=
=
'IV
7. Typical numbers are for TA 25'C and VCC 5.0 V.
8. tOF is applicable to both ff and BE, which occurs first.
9. DE may follow up to tACC·tOE after the falling edge of CE without affecting
tACC'
10. Power consumption decreases with temperature from a maximum at low
temperature to a minimum at high temperature.
TIMING DIAGRAMS
READ CYCLE (eE = Vld
Figure 3
V IH ADDRESSES
OE
OPEN
OUTPUT
STANDBY POWER
DOWN MODE (OE = V IL)
Figure 4
VALID
ADDRESS
VALID
V IH STANDBY
CE
ACTIVE
STANDBY
V IL tDF
V OH OUTPUT
VOL -
VAL!D
FOR CURRENT
ADDRESS
OPEN
XII-17
VALID
FOR CURRENT
ADDRESS
III
PROGRAM OPERATION
RECOMMENDED DC OPERATING CONDITIONS8
(TA = 25°C ± 5°C)(Vee = +5 V ± 10%. Vpp = 25 V ± 1 V)
SYM
PARAMETER
MIN
MAX
UNITS
V IL
Input Low Level
-0.1
0.8
V
V IH
Input High Level
2.0
Vee + 1
V
MIN
MAX
UNITS
NOTES
3
DC ELECTRICAL CHARACTERISTICS
(TA = 25°C ± 5°C)(V ee = +5 V ± 10%. Vpp
NOTES
= 25 V ± 1 V)
SYM
PARAMETER
IlL
Input Leakage Current
10
J1.A
Icc
Vee Power Supply Current
100
mA
IpP1
Vpp Supply Current
10
mA
4
IpP2
Vpp Supply Current during
Programming Pulse
30
mA
5
RECOMMENDED AC OPERATING CONDITIONS AND ELECTRICAL CHARACTERISTICS,·2.•. 7
(TA = 25°C ± 5°C)(V ce = +5 V ± 10%. Vpp = 25 V ± 1 V)
SYM
PARAMETER
t AS
Address Setup Time
2
J1.s
toES
OE Setup Time
2
J1.S
tos
Data Setup Time
2
J1.S
tAH
Address Hold Time
2
J1.S
tOEH
OE Hold Time
2
J1.S
tOH
Data Hold Time
2
J1.S
tOF
Output Enable to Output
Float
0
tOE
Output Enable to Output
Delay
tpw
Program Pulse Width
tpRT
Program Pulse Rise Time
5
ns
tPFT
Program Pulse Fall Time
5
ns
MIN
MAX
TYP
45
50
PROGRAM OPERATION NOTES:
1. Vee must be applied at the same time or before Vpp and removed after or at
the same time as Vpp. To prevent damage to the device it must not be
inserted into a board with Vpp at 25 V.
4. CE'/PGM
5. CE/PGM
6. IT
2. Care must be taken to prevent overshoot of the Vpp supply when switching
to +25 V.
3. 0.45 V:S VIN :s 5.50 V
7.
0
0
0
UNITS
NOTES
130
ns
4
120
ns
4
55
ms
VIL'
VIH.
20 nsec.
1 V and 2 V for inputs and .8 V and 2 V for outputs are used as timing
reference levels.
8. Although speed selections are made for read operation all programming
specifications are the same for all dash numbers.
XII-18
TIMING DIAGRAM
(Program Mode)
Figure 5
14---PRDGRAM _ _~_ _ _ PRDGRAM''-_ _-+I
VERIFY
ADDRESS N
ADDRESSES
V IL -
ADDRESS N + M
_ _ _J
DATA OUT
tAH---"'7{~ VALID
DATA
ADDN_--DATA IN
STABLE
ADD N+ M
VIL- _ _ _ _""""I
DE
V IL -
_ _ _J
Ce/PGM
MODE SELECTION
Pin:
into the device by following the program procedures
outlined in this data sheet.
CE'/PGM
OE
Vpp
Mode
(18)
(20)
(21)
Output
Read
V IL
V 1L
+5
Valid Out
Standby
V IH
Don't
Care
+5
Open
Program
Pulsed
VIL to V 1H
V IH
+25
Data
Inputs
Program
Verify
VIL
V IL
+25
Valid Out
Program
Inhibit
VIL
V IH
+25
Open
The MKB2716 is specifically designed to fit those
applications where fast turnaround time and pattern
experimentation are required. Since data may be altered in
the device (erase and reprogram) it allows for early
debugging of the system program. Since single location
programming is available the MKB2716 can have its data
content increased (assuming all 2048 bytes were not
programmed) at any time for easy updating of system
capabilities in the field. Once the contents become fixed and
the system enters production, mask programmable ROMs
can offer speed, cost per bit and power per bit benefits.
Mostek offers the MKB36000 and MKB37000 8 K x 8
ROMs which allow the user to quadruple memory density in
the application. A "ROM Programming Guide" is available
to aid the user in preparing the code for submission once
prototyping with MKB2716s has verified its accuracy.
Vcc (24) = 5 V all modes
DESCRIPTION (Continued)
be done at any individual word address, sequencially or at
random. The three-state output controlled by the OE input
allows OR-tie capability for construction of large arrays. A
single power supply requirement of +5 volts makes the
MKB2716 ideally suited for use with Mostek's 5-volt only
microprocessors such as the MKB3880 (Z80). The
MKB2716 is packaged in the industry standard 24-pin dualin-line package with a transparent, hermetically sealed lid.
This allows the user to expose the chip to ultraviolet light to
erase the data pattern. A new pattern may then be written
READ OPERATION
The MKB2716 has five basic modes of operation. Under
normal operating conditions (non-programming) there are
two modes; READ and STANDBY. A READ operation is
accomplished by maintaining pin 18 (CE) at V IL and pin 21
(Vpp) at +5 volts. If OE (pin 20) is held active low after
addressing (Ao - AlO have stabilized) then valid output data
will appear on the output pins at access time t ACC (address
XII-19
III
access). In this mode, access time may be referenced to OE
(toe) depending on when nE occurs (see timing diagrams).
POWER DOWN operation is accomplished in STANDBY
mode by taking pin 18 (CE) to a TTL high level (VI H)' The
power is reduced by 75% from 633 mW maximum to 165
mW. During power down Vpp must be at +5 volts, and the
outputs will be open-circuit regardless of the condition of
OE. Access time from a high to low transition of CE (teE) is
the same as from addresses (tAcd. (See STANDBY Timing
Diagram).
PROGRAM INHIBIT is another useful mode of operation
when programming multiple, parallel addressed MKB2716's
with different data. It is necessary only to maintain DE at
V IH' Vpp at +25, allow addresses and data to stabilize, and
pulse the CE/PGM pin of the device to be programmed. The
devices with ~/PGM at V IL will not be programmed. Data
may then be changed and the next device pulsed.
PROGRAMMING INSTRUCTIONS
The MKB2716 is shipped from Mostek completely erased.
In this initial state, and after any subsequent erasure, all bits
will be at a '1 ' level (output high). Information is introduced
by selectively programming 'O's into the proper bit locations.
Once a '0' has been programmed into the chip it may be
changed only by erasing the entire chip with UV light.
The MKB2716 is put into the PROGRAM mode by
maintaining Vpp at +25 V, and OE at V IH . In this mode the
output pins serve as inputs (8 bits in parallel)for the required
program data. Word address selection is done the same as
in the READ mode, and logic levels for other inputs and the
Vcc supply voltage are the same as in the READ mode.
To program a "byte" (8 bits) of data, a TTL active high level
pulse is applied to the CE/PGM pin after address inputs and
data have stabilized. Each location to be programmed must
have a pulse applied, and only one pulse per location is
required. Any individual location, a sequence of locations or
locations at random may be programmed in this manner.
(The program pulse has a maximum width of 55 msec, and
programming must not be attempted with a high level D.C.
signal applied to the CE/PGM pin.)
XII-20
PROGRAM VERIFY allows the MKB2716 program data to
be verified without having to reduce V pp from +25 V to +5 V.
Vpp = 25 V should only be used in the PROGRAM,
PROGRAM INHIBIT and PROGRAM VERIFY modes and
must be at +5 V in all other modes.
MKB2716 ERASING PROCEDURE
The MKB2716 maybe erased by exposure to high intensity
ultraviolet light, illuminating the chip through the
transparent window. This exposure to ultraviolet light
induces the flow of a photo current from the floating gate,
thereby discharging the gate to its initial state. An ultraviolet
source of 2537 A yielding a total integrated dosage of 15
Watt-seconds/cm 2 is required. Note that all bits of the
MKB2716 will be erased. The erasure time is approximately
15 to 20 minutes utilizing a ultra-violet lamp with a 12000
p.W/CM2 power rating. The lamp should be used without
short wave filters, and the MKB2716 to be erased should be
placed about one inch away from the lamp tubes. It should
be noted that as the distance between the lamp and the chip
is doubled, the exposure time required goes up by a factor of
4. The UV content of sunlight is not sufficient to provide a
practical means of erasing the MKB2716. However, it is
recommended that the MKB2716 not be operated or stored
in direct sunlight, as the UV content of sunlight may cause
erasure of some bits in a short period of time.
MOSTEI(®
64K-BIT READ-ONLY MEMORY
Processed to MIL-STD-883, Method 5004, Class B
MKB36000{P/ J)-80/83/84
FEATURES
o Standard 24 pin DIP (EPROM Pin Out Compatible)
o MKB36000 8K x 8 Organization - "Edge Activated"
operation (CE)
o Low Standby Power Dissipation - 55 mW typical (CE
High)
o Maximum access time: 300ns (-84)
250ns (-83)
250ns (-80)
o On chip latches for addresses
o Inputs and three-state outputs-TTL compatible
o Low Power Dissipation -
220mW max active
o Outputs drive 2 TTL loads and 100 pF
o Extended operating ambient temperature range
(-55°C:::; TA:::; +125°C): -84
(-55°C:::; TA:::; + 125°C):-83
(-40°C:::; TA:::; +80°C):-80
o Ruggedized for use in severe military environments
o Single +5V
DESCRIPTION
The MKB36000 is a new generation N-channel silicon
gate MOS Read Only Memory, organized as 8192 words
by 8 bits. As a state-of-the-art device, the MKB36000
incorporates advanced circuit techniques designed to
provide maximum circuit density and reliability with the
highest possible performance, while maintaining lower
power dissipation and wide operating margins.
±
10% power supply
chip enable (CE) input at a TTL high level. In this mode,
power dissipation is reduced to typically 35mW, as
compared to unclocked deviced which draw full power
continuously. In system operation, a device is selected
by the CE input, while all other are in a low power mode,
reducing the overall system power. Lower power means
reduced power supply cost, less heat to dissipate and an
increase in device and system reliability.
The MKB36000 utilizes what is fast becoming an
industry standard method of device operation. Use of a
static storage cell with clocked control periphery allows
the circuit to be put into an automatic low power
standby mode. This is accomplished by maintaining the
The edge activated chip enable also means greater
system flexibility and an increase in system speed. The
MKB36000 features onboard address latches
controlled by the CE input. Once the address hold time
specification has been met, new address data can be
applied in anticipation of the next cycle. Outputs can be
FUNCTIONAL DIAGRAM
PIN CONNECTIONS
A7
A6 2
A5 3
A4 4
AI2
A"
_-Yo<
A,O
_ _ VIS
A.
A3 5
A2 6
Al 7
Aa
A,
AS
Ao
A,
A,
~
8
9
°1
02 10
03 11
IT
~
GND12
XII-21
24 VCC
23 A8
22 A9
21 A12
20 CE
19 AlO
18 All
17 08
16 °7
15 06
14 05
13 04
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Terminal Relative to VSS ..................................................... -0.5V to + 7V
Operating Temperature TA (Ambient) -83/84 ............................................... -55°C to +125°C
Operating Temperature TA (Ambient) -80 ..................•................................ -40°C to +85°C
Storage Temperature - Ceramic (Ambient) ................................................ -65°C to +150°C
Power Dissipation ...................................................••........................... 1 Watt
·Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS6
(-55°C::; TA::; +125°C) for -84; (-40° ::; TA::; +85°C) for -80
MIN
TYP
MAX
UNITS
NOTES
Power Supply Voltage
4.5
5.0
5.5
Volts
6
VIL
Input Logic 0 Voltage
-1.0
0.8
Volts
VIH
Input Logic 1 Voltage
2.4
VCC
Volts
SYM
PARAMETER
VCC
DC ELECTRICAL CHARACTERISTICS
(VCC = 5V ± 10%) (ELECTRICAL CHARACTERISTICS VALID OVER TEMPERATURE RANGE FOR EACH DEVICE)6
MAX
UNITS
NOTES
VCC Power Supply Current Active
40
mA
1
ICC2
VCC Power Supply
Current Standby
10
mA
7
II(L)
Input Leakage Current
-10
10
!J.A
2
IO(L)
Output Leakage Current
-10
10
!J.A
3
VOL
Output Lo~c "0" Voltage
@ IOU1 = .3mA
0.4
Volts
VOH
Output Lo~c "1" Voltage
@ IOU1 = 20!J.A
SYM
PARAMETER
ICC1
MIN
TYP
Volts
2.4
AC ELECTRICAL CHARACTERISTICS
(VCC = 5V ± 10%)6 (ELECTRICAL CHARACTERISTICS VALID OVER TEMPERATURE RANGE FOR EACH DEVICE)6
36000-80/83
36000-84
UNITS
NOTES
ns
4
7500
ns
4
250
300
ns
4
60
75
ns
4
75
ns
4
0
0
ns
125
150
ns
SYM
PARAMETER
MIN
tc
Cycle Time
375
tCE
CE Pulse Width
250
tAC
CE Access Time
tOFF
Output Turn Off Delay
tAH
Address Hold Time
Referenced to CE
60
tAS
Address Setup Time
Referenced to CE
tp
CE Precharge Time
XII-22
MAX
MIN
MAX
450
7500
300
CAPACITANCE
(-55°C :S TA :S + 125°C)
TYP
MAX
UNITS
NOTES
Input Capacitance
5
8
pF
5
Output Capacitance
7
15
pF
5
SYM
PARAMETER
C1
Co
NOTES:
1. Current is proportional to cycle rate. ICCI is measured at the specified
minimum cycle time.
2. VIN = OV to 5.5V
3. Device unselected; VOUT = OV to 5.5V
4. Measured with 2 TTL loads and l00pF, transition times = 20ns.
5. Capacitance measured with Boonton Meter or effective c.apacitance
calculated from the equation:
C = f:>. with f:>.V = 3volts
f:>.V
6. A minimum 2ms time delay is required after the application of Vee (+5)
before proper device operation is achieved. CE must be high during this
period.
7. CE high.
TIMING DIAGRAM
tc
CHIP ENABLE
ADDRESS
DATA OUTPUT
Vow
VOL------
MKB 36000 ROM PUNCHED CARD CODING FORMAT (1 & 6)
COlS
FIRST CARD
SECOND CARD
THIRD CARD
FOURTH CARD
1-30
31-50
60-72
1-30
31-50
DATA FORMAT
INFORMATION FIELD
512 data cards (16 data words/card) with the
following format:
Customer
Customer Part Number
Mostek Part Number (2)
Engineer at Customer Site
Direct Phone Number for
Engineer
Mostek Part Number {2~
Data Format (3)
Logic - ("Positive Logic"
or "Negative Logic")
35-57 Verification Code (4)
1-5
1-9
15-28
NOTES:
1. Positive or negative logic formats are accepted as noted in the fourth card.
2. ASSigned by Mostek; may be left blank.
3. Mostek punched card coding format should be used Punch "Mostek"
starting in column one.
4. Punches as(a) VERIFICATION HOLD - i.e .. customer verification of the data
as reproduced by Mostek is required prior to production of the ROM. To
accomplish this Mostek supplies a copy of its Customer Verification Data
COlS
INFORMATION FIELD
1-4
Four digit octal address of
first output word on card
5-7
Three digit octal output
word specified by address in
column 1-4
8-52
Next fifteen output words.
each word consists of three
octal digits.
Sheet (CVDS) to the customer.
(b) VERIFICATION PROCESS - i.e .. the customer will receive a CVDS but
production will begin prior to receipt of customer verification; (c)
VERIFICATION NOT NEEDED - i.e., the customer will not receive a CVDS
and production will begin immediately.
5. 512 cards for MIa with l> V = 3 volts
6. A minimum 2ms time delay is required after the application of Vee (+5)
before proper device operation is achieved CE must be at VIH for this time
period.
7. ~high
8. Power supply current decreases with increasing temperature.
l>V
XII-27
III
TIMING DIAGRAM
Figure 1
CHIP ENABLE
ADDRESS
OUTPUT ENABLE
DATA OUTPUT
DESCRIPTION (Continued)
market a new era of ROM, PROM and EPROM compatibility
previously unavailable.
Use of clocked control periphery and a standard static ROM
cell makes the MKB37000 the lowest power 64K ROM
available. Power consumption is a low 165mW maximum.
To provide greater system flexibilityan output enable (OE)
function has been added using one of the extra pins
available on the 28 pin DIP. This function matches that
found on all of the new BYTEWYDE family of memories
available from Mostek.
The use of clocked CE mode of operation provides an
automatic power down mode of operation. The MKB37000
features on chip address latches controlled by the
input.
Once address hold time is met, new address data can be
provided to the device in anticipation of a subsequent cycle.
It is not necessary to maintain the address up to access time
to access valid data. The output enable function controls
only the outputs and is not latched by the CEo The CE input
can be used for device selection and the OE input used to
avoid bus conflicts so that outputs can be 'OR'ed together
when using multiple devices.
a:
Any application reqUiring a high performance, high bit
density ROM can be satisfied by the MKB37000. This
device is ideally suited for 8 bit microprocessor systems
such as those which utilize the MKB3880. It can offer
significant cost advantages over EPROM.
OPERATION
The MK37000 is controlled by the chip enable (CE) and
output enable (OE) inputs. A negative going edge at the CE
input will activate the device and latch the addresses into
the on chip address registers. The output buffers, under the
control of OE, will become active in CE access time (t cEA) if
the output enable access time (tOEA) requirement is met.
The on-chip address register allows addresses to be changed
after the specified hold ti me (tAH ) in preparation for the next
cycle. The outputs will remain valid and active until either
CE or OE is returned to the inactive state. After chip deselect
time (tCEZ ) the output buffers will go to a high impedance
state. The CE input must remain inactive (high) between
subsequent cycles for time tp to allow for precharging the
nodes of the internal circuitry.
MK37000 ROM CODE DATA INPUT PROCEDURE
Other system oriented features include fu IIy TTL compatible
inputs and outputs. The three state outputs, controlled by
the OE input, will drive a minimum of 2 standard TTL loads.
The MKB37000 operates from a single +5 volt power
supply with a wide +10% tolerance, providing the widest
operating margins available. The MKB37000 is packaged in
the industry standard 28 pin DIP. Pin 1 and 26 are not
connected to allow easy upward compatibility with next
generation higher density ROM which will use these pins
for addresses. Pin 27 is not connected in order to maintain
compatibility with RAMs which use this pin as a write
enable (WE) control function.
The preferred method of supplying code data to Mostek is in
the form of programmed EPROMs (see table). In addition to
the programmed set of blank EPROMs for supplying
customer code verification. When multiple EPROMs are
required to describe the ROM they shall be designated in
ascending address space with the numbers 1,2,3, etc. As
an example, EPROM #1 would start with address space
0000 and go to 07FF for a 2K x 8 device. EPROM #2 would
then start at address space 0800 and so on. A total of (4) 2K
x 8 devices would be required to toally describe the address
space of the 8K x 8 MK37000.
XII-28
A paper printout and verification approval letter will accompany each verification EPROM set returned to the
customer. Approval is considered to be excepted when the
signed verification letter is returned to Mostek. The original
set of EPROMs will be retained by Mostek for the duration of
the prototyping process. Please consult with your local
Mostek representative for more information.
Acceptable EPROMs for Code Data
Table 1
EPROM
# REQUIRED
271612516
4
2732
2
2764
1
XII-29
XII-30
!t
UNITED
TECHNOLOGIES
MOSTEK
MILITARY
HIGH-REL
PRODUCTS
PROCESSED TO MIL-STD-883A METHOD 5004
256K-BIT MOS READ-uNLY MEMORY
MKB38000(P/J/E)-84/85
o Fully screened to MIL-STD-883
Method 5004, Class B
FEATURES
o
Organized 32K x 8
o
Pin compatible with Mostek's BYTEWYDpM Memory
Family
o
Upward compatible with the MKB3700
o
Access Time = Cycle Time
o
Static Operation
o
Automatic Power Down
o
Temperature range: -55°C::::: Te ::::: 125°C
DESCRIPTION
o
CE and OE functions facilitate bus control
o
Pin 27 no connection permits interchange with static
RAM (WE)
o
High performance
Part No.
Access Time
Cycle Time
MKB38000-84
250 ns
250 ns
MKB38000-85
300 ns
300 ns
The MKB38000 is a N-channel silicon gate MOS Read Only
Memory, organized as 32,768 words by8 bits. As a state-ofthe-art device, the MKB38000 incorporates advanced
circuit techniques designed to provide maximum circuit
density and reliability with the highest possible performance,
while maintaining low power dissipation and wide
operating margins.
FUNCTIONAL DIAGRAM (MKB38000)
PIN CONNECTIONS
Figure 1
Figure 2
" '" ,',., Iv,.< I I I'"I
'" I':
, , L_Jl_Jl_J
'LJ,
NC
1'1
I
L_J LJ U
A"
A7
3
26
'.,
A6
•
2•
A8
"
=~J
L2!_
A"
•
2.
A9
" =~J
L2_6_ NC
A.
6
23
A11
"
-~J
L2':_
A3
7
22
DE
:l~J
~lJ
[2~-
A",
A2
8
"
2'
A'O
[2Y: EE
A'
9
20
cr
NO
~2J
DO"
n,
O'----L-____J
MODE
OUTPUTS
POWER
H
X
Deselect
High-Z
Standby
L
H
Inhibit
High-Z
Active
L
L
Read
DOUT
Active
A'3
'.
r--
",
"
00,
L2_'_ DO
DO, DO,
OE
NC
[2~_
r-' r-, r-, r-, r-' r-,r-'
:14:,151:161117::18:
1'9 :,201
CE
Vee
27
L2L
c.----I
TRUTH TABLE
28
2
~J
'.,
OO·····Q7
,
A12
'.,
" "
AO
A"
NO
132113111301
141'31
..
"
NC
DQ, D0. OQ.
A.
AO 10
'9
07
00 11
18
06
01
12
'7
O.
02
,.
,.
O.
GND
13
'6
III
PIN NAMES
AO-A14 Address
OE
CE
Chip Enable
Vee
No Connection GND
NC
QO-Q7
XII-31
03
Output Enable
+5V
Ground
Data Outputs
ABSOI-UTE MAXIMUM RATINGS*
Voltage on Any Terminal Relative to GND ......•.••.............................•..•............ -0.5 V to +7 V
Operating Temperature Tc (Case) ...•......................................................... 55°C to +125°C
Storage Temperature-Ceramic (Ambient) ..........................•.....•.................... -65°C to +150°C
Power Dissipation .......•.....................................•....•............................... 1 Watt
·Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability,
RECOMMENDED DC OPERATING CONDITIONS1,6
(-55°C:5 Tc:5 + 125°C)
SYM
PARAMETER
MIN
TYP
MAX*
UNITS
Vcc
Power Supply Voltage
4.75
5.0
5.25
V
V 1L
Input Logic 0 Voltage
-0.3
0.8
V
V 1H
Input Logic 1 Voltage
2.0
Vcc
V
TYP
MAX*
UNITS
NOTES
NOTES
8
DC ELECTRICAL CHARACTERISTICS1,6
(V CC =5 V ± 5%)(-55°C:5 Tc:5 +125°C)
SYM
PARAMETER
ICCl
V cc Power Supply Current (Active)
75
100
rnA
5
ICC2
V cc Power Supply Current
(Standby)
35
50
rnA
7
II(L)
Input Leakage Current
-10
0.1
10
pA
3
IO(L)
Output Leakage Current
-10
0.1
10
pA
2
VOL
Output Logic "0" Voltage @
lOUT =4 rnA
0.4
V
V OH
Output Logic "1 " Voltage @
lOUT =-1 rnA
MIN
V
2.4
NOTE:
1. ·Preliminary values. Contact factory for current status
AC ELECTRICAL CHARACTERISTICS1,4.6.9.1o
(Vcc = 5 V ± 5%) (-55°C :5Tc:5 +125°C)
-85
-84
MAX
MIN
MAX UNITS NOTES
300
ns
SYM
PARAMETER
MIN
t RC
Read Cycle Time
250
tAA
Address Access Time
250
300
ns
tCEA
CE Access Time
250
300
ns
tCEZ
Chip Enable Data Off Time
40
50
ns
tCEL
Chip Enable to Data Bus Active
tOEA
5
5
ns
Output Enable Access Time
50
60
ns
tOEZ
Output Enable Data Off Time
40
50
ns
tOH
Output Hold from Address Change
5
5
ns
XII-32
CAPACITANCE
(-55°C s: Tc s: '25°C)
SYM
PARAMETER
C1
Input Capacitance
5*
pF
Co
Output Capacitance
7*
pF
TYP
MAX
UNITS
NOTES
5
*Sample tested only and guaranteed by design
TIMING DIAGRAM
Figure 3
________~.~------tRC--------
CE
OE
D
AO·A7
NOTES:
1.
2.
3.
4.
All voltages referenced to GND.
Measured with 0.4 V:::; Vo::; 5.0 V outputs deselected and Vee:;::; 5 V.
VIN = 0 V to 5.25 V.
Input and output timing reference levels are at 1.5 V for inputs and.8 and 2.0
for outputs.
5. Measured with outputs open.
6. A minimum of 2 ms time delay is required after the application of Vee (+5)
before proper device operation is achieved. CE must be at VIH for this time
period.
7. CE high.
8. Negative undershoots to a minimum of-l.5 V are allowed with a maximum
of 10 ns pulse width once per cycle.
9. Measured with a load as shown in Figure 1.
10. A.C. measurements assume transition time;::: 5 ns levels GND to 3 V.
OUTPUT LOAD
Figure 4
XII-33
5V
1.1KO
D. U. T.
-----4~----......
6800
100pF
(Including Scope and Jig)
£II
DESCRIPTION (continued)
As a member of the Mostek BYTEWYDE Memory Family,
the MKB38000 allows compatibility between RAM, ROM,
and EPROM. The MKB38000 can be used as a pin/function
density upgrade to the MKB37000 8K x 8 bit ROM.
Any application requIring a high performance high bit
density ROM can be satisfied by the MKB38000. This
device is ideally suited for 8 bit microprocessor systems
such as those which can utilize the MKB3880. It can offer
significant cost advantages over PROM.
OPERATION
The output enable function controls only the outputs. The
CE input can be used for device selection and the OE input
used to avoid bus conflicts so that outputs can be 'OWed
together when using multiplexed or bi-directional busses.
Other system oriented features include fully TIL compatible
inputs and outputs. The three state outputs, controlled by
the OE input, will drive a minimum of 2 standard TIL loads.
The MKB38000 operates from a single +5 volt power
supply. It is packaged in the industry standard 28 pin DIP.
Pin 27 is not connected in order to maintain compatiblity
with RAMs which use this pin as a write enable (WE)
control function.
The MKB38000 is controlled by the chip enable (CE) and
output enable (OE) inputs. A low level at the CE input
powers up the memory for an active cycle. The output
buffers, under the control of OE, will become active in CE
access time (t CEA ) if the output enable access time (tOEA)
requirement is met.
By maintaining valid address, the outputs will remain valid
and active until either CE or OE is returned to the high state
or until an address is changed. After chip deselecttime(tcEZ )
or output enable deselect time (tOEZ )' the output buffers will
go to a high impedance state.
MKB38000 ROM CODE DATA INPUT PROCEDURE
The preferred method of supplying code data to Mostek is in
the form of programmed EPROMs (see table). In addition to
the programmed set, Mostek requires an additional set of
blank EPROMs for supplying customer code verification.
When multiple EPROMs are required to describe the ROM,
they shall be designated in ascending address space with
the numbers 1,2,3, etc. As an example, EPROM #1 would
start with address space 0000 and go to 1FFF for an 8K x 8
device. EPROM #2 would then start at address space 2000
and soon. A total offour8Kx8 devices would be required to
totally describe the address space of the 32K x 8
MKB38000.
customer. Approval is considered to be accepted when the
signed verification letter is returned to Mostek. The original
set of EPROMswili be retained by Mostek for the duration of
the prototyping process.
ACCEPTABLE EPROMs FOR CODE DATA
Table 1
A paper printout and verification approval letter will
accompany each verification EPROM set returned to the
XII-34
EPROM
# REQUIRED
2732
8
2764
4
MOSTEI{.
4096 x 1-BIT DYNAMIC RAM
Processed to MIL-STD-883, Method 5004, Class B
MKB4027(J )-83/84
FEATURES
o Extended operating temperature range (-55°C :5 TA
o Improved performance with "gated CAS,"
only" refresh and page mode capability
:5 +85°C)
o
o
o
o
o
o
o
Industry standard 16-pin DIP (MK4096) configuration
200ns access time, 375ns cycle (-83)
250ns access time, 375ns cycle (-84)
o ± 10% tolerance on all supplies (+ 12V, ± 5V)
o Low Power: 467mW active (max)
40mW standby (max)
DESCRIPTION
"R'AS
All inputs are low capacitance and TTL compatible
Input latches for addresses, chip select and data in
Three-state TTL compatible output
Output data latched and valid into next cycle
Ruggedized for use in severe military environments
with widely available automated testing and insertion
equipment.
The MKB4027 is a 4096 word by 1 bit MOS random
access memory circuit fabricated with Mostek's Nchannel silicon gate process. This process allows the
MKB4027 to be a high performance state-of-the-art
memory circuit that is manufacturable in high volume.
The MKB4027 employs a single transistor storage cell
utilizing a dynamic storage technique and dynamic
control circuitry to achieve optimum performance with
low power dissipation.
A unique multiplexing and latching technique for the
address inputs permits the MKB4027 to be packaged in
a standard 16-pin DIP on 0.3 in. centers. This package
size provides high system-bit densities and is compatible
System oriented features include direct interfacing
capability with TTL, only 6 very low capacitance address
lines to drive, on-chip address and data registers which
eliminates the need for interface registers, input logic
levels selected to optimize noise immunity, and two chip
select methods to allow the user to determine the
appropriate speed/power characteristics of his memory
system. The MKB4027 also incorporates several
flexible operating modes. In addition to the usual read
and write cycles, read-modify write, page-mode, and
RAS only refresh cycles are available with the
MKB4027. Page-mode timing is very useful in systems
requiring Direct Memory Access (DMA) operation.
FUNCTIONAL DIAGRAM
PIN CONNECTIONS
Vee 1
16 VSS
DIN 2
WRITE 3
15 CAS
RAS 4
(D •• ,)
"
Ao 5
12 A3
A2 6
A, 7
11 A4
VDD 8
"
PIN NAMES
Ao-Ae Address Inputs
Col Address Strobe
CS
Data In
DIN
Data Out
DOUT
Row Address Strobe
RAS
"
XII-3S
14 DOUT
13 CS
10 AS
9 VCC
WRITE Read/Write Input
Power (-5VI
VSS
Power (+5V)
VCC
Power (+12VI
VDD
Ground
VSS
ABSOLUTE MAXIMUM RATINGS*
Voltage on any pi.n relative to VSS' .......................................................... -0.5V to +20V
Voltage on VOO' V CC relative to VSS ........................................................ -1 .OV to + 15V
VSS - VSS (VOO - VSS > 0) ............................................................................ OV
Operating Temperature (Ambient)(Ceramic) ................................................. -55°C to +85°C
Storage Temperature (Ambient)(Ceramic) .................................................. -65°C to +150°C
Short Circuit Output Current ........................................................................ 50mA
Power Dissipation ................................................................................ 1 Watt
*Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS4
(-55°C ~ TA ~ 85°C)
SYM
PARAMETER
MIN
TYP
MAX
UNITS
NOTES
VOO
Supply Voltage
10.8
12.0
13.2
V
2
VCC
Supply Voltage
4.5
5.0
5.5
V
2,3
VSS
Ground
0
0
0
V
2
VSS
Supply Voltage
-4.5
-5.0
-5.5
V
2
VIHC
Logic 1 Voltage, RAS, CAS, WRi'fi:
2.7
7.0
V
2
VIH
Logic 1 Voltage, all inputs except
RAS, CAS, WRITE
2.4
7.0
V
2
VIL
Logic 0 Voltage, all inputs
-1.0
.8
V
2
DC ELECTRICAL CHARACTERISTICS4
(-55°C ~ TA ~ 85°C)1 (VOO = 12.0V ± 10%; VCC
= 5.0V ± 10%; VSS = OV; VSS = -5.0V ± 10%)
MAX
UNITS
NOTES
Avg. VOO Power Supply Current
35
mA
5
1002
Standby VOO Power Supply
Current
3.0
mA
8
1003
Avg. VOO Power Supply Current
during "RAS only" cycles
27
mA
ICC
VCC Power Supply Current
ISS
Avg. VSS Power Supply Current
I(L)
SYM
PARAMETER
1001
TYP
MIN
mA
6
200
p.A
Input Leakage Current (any input)
10
p.A
7
IO(L)
Output Leakage Current
10
p.A
8,9
VOH
Output Logic 1 Voltage @
lOUT = -5mA
VOL
Output Logic 0 Voltage @
lOUT = 3.2mA
V
2.4
0.4
V
NOTES:
1.
2.
3.
TA is specified for operation at frequencies totRC~tRC (min). Operation at
higher cycle rates with reduced ambient temperatures and higher power
dissipation is permissible provided that all AC parameters are met.
All voltages referenced to VSS.
Output voltage will swing from VSS to Vee when enabled, with no output
load. For purposes of maihtaining data in standby mode, Vee may be
reduced to VSS without affecting refresh operations or data retention.
However, the VOH (min) specification is I'\ot gl,!aranteed in this mode.
XII-36
4.
5.
6.
Several cycles are required after power-up before proper device operation
is achieved. Any 8 cycles which perform refresh are adequate for this
purpose.
Current is proportional to cycle rate. 1001 (ma)() is measured at the cycle
rate specified bytRC (min). See Figure 1 for 1001 limits at other cycle rates.
ICC depends on output loading. During readout of high level data Vce is
connected through a low impedance (1350 typ) to Data Out. At all other
times ICC consists of leakage currents only.
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (4,",7)
(-55°C::; TA::; 85°C)1 (VDD = 12.0V ± 10%, VCC = OV, Vaa = -5.0V ± 10%)
MKB4027-83 MKB4027-84
SYM
PARAMETER
MIN
tRC
Random read or write cycle time
375
380
ns
12
tRWC
Read-write cycle time
375
395
ns
12
tRMW
Read Modify Write Cycle
405
470
ns
12
tpc
Page mode cycle time
225
285
ns
12
tRAC
Access time from row address strobe
200
250
ns
13,15
tCAC
Access time from column address strobe
135
165
ns
14,15
tOFF
Output buffer turn-off delay
50
60
ns
tRP
Row address strobe precharge time
120
tRAS
Row address and strobe pulse width
200
tRSH
Row address strobe hold time
135
165
ns
tCAS
Column address strobe pulse width
135
165
ns
tCSH
CAS hold time
200
250
ns
tRCD
Row to column strobe delay
tASR
Row address set-up time
tRAH
Row address hold time
tASC
25
MAX
MIN
MAX UNITS
120
5000
65
250
35
ns
5000
85
ns
ns
0
0
ns
25
35
ns
Column address set-up time
0
0
ns
tCAH
Column address hold-time
55
75
ns
tAR
Column address hold time referenced to RAS
120
160
ns
tcsc
Chip select set-up time
0
0
ns
tCH
Chip select hold time
55
75
ns
tCHR
Chip select hold time referenced to RAS
120
160
ns
tT
Transition time (rise and fall)
3
tRCS
Read command set-up time
0
0
ns
tRCH
Read command hold time
0
0
ns
tWCH
Write command hold time
55
75
ns
tWCR
Write command hold time referenced to RAS
120
160
ns
twp
Write command pulse width
55
75
ns
tRWL
Write command to row strobe lead time
70
85
ns
tCWL
Write command to column strobe lead time
70
85
ns
tDS
Data in set-up time
0
0
ns
XII-37
50
3
NOTES
50
ns
16
17
18
ELECTRICAL CHARACTERISTICS (Continued)
MKB4027-83 MKB4027-84
SYM
PARAMETER
tDH
Data in hold time
55
75
ns
tDHR
Data in hold time referenced to RAS
120
160
ns
tCRP
Column to row strobe precharge time
0
0
ns
tcp
Column precharge time
80
110
ns
tRFSH
Refresh Period
twcs
Write command set-up time
0
0
tCWD
CAS to WRITE delay
80
80
ns
19
tRWD
RAS to WRITE delay
145
175
ns
19
tDOH
Data out hold time
5
5
J.lS
MIN
MAX
MIN
2
MAX UNITS
2
NOTES
18
ms
19
NOTES (Continued)
7.
8.
9.
10.
15.
All device pins at 0 volts except VSS which is at -5 volts and the pin under
test which is at -10 volts
Output logic is disabled (high-impedance) and RAS and CAS are both at a
logic 1. Transient stabilization is required prior to measurement of this
parameter.
16.
17.
OV <: VOUT <: -10V
or VIH and VIL.
Effective capacitance is calculated from the equation'
e
Measured with a load circuit equivalent to 2 TTL loads and 100pF.
Operation within the tRAC (max) limit insures that tACO (max) is specified
tRCD (max) limit then access time is controlled exclusively by tCAC.
VIHC (min) or VIH (min) and VIL (max) are reference levels for measuring
timing of input signals. Also, transition times are measured between VIHC
18.
= "Q with "V = 3 Volts
V
19.
11.
AC measurements assume t1 :::: 5ns.
12
The specification for tRC (min) and tRWC (min) are used only to indicate
cycle time at which proper operation over the full temperature range
(-55°C::; TA::; 85°C) is assured. See Figure 2 for derating curve
13
Assumes that tRCO:::; tRCO (max)
14.
Assumes that tRCO 2: tRCD (max)
AC ELECTRICAL CHARACTERISTICS
(-55°C:::; TA:::; 85°C)' (VDD = 12.0V ± 10%, VCC
SYM
PARAMETER
CI1
= 5V ±
These parameters are referenced to CAS leading edge in random write
cycles to WRITE leading edge in delayed write or read-modify-write cycles.
twcs, tCWD' and tRWD are restrictive operating parameters in a
read/write or read/modify/write cycle only. If twcs 2: twcs (min), the,
cycle is an early write cycle and the Data Out will contain the data written
into the selected cell. If teWD? tewD (min) and tRWD? tRWD (min), the
cycle is a read-write cycle .and Data Out will contain data read from the
selected cell. If neither of the above sets of conditions is satisfied, the
condition of Data Out (at access time) is indetermined.
10%, VSS
= OV, VBB = -5.0V ±
10%)
TYP
MAX
UNITS
NOTES
Input Capacitance (AO - A5), DIN, cs
4
5
pF
10
CI2
Input Capacitance RAS, CAS, WRITE
8
10
pF
10
Co
Output Capacitance (DOUT)
5
7
pF
8,10
-SUPPLEMENTAL DATA SHEET TO BE USED IN CONJUNCTION
WITH MOSTEK MK4027(J)-1/2/3 and MK4027(J)-4 DATA SHEETS
XII-38
4096 x 1-81T STATIC RAM
Processed to MIL-STD-883, Method 5004, Class 8
MKB4104 (P/J/El-84/85
FEATURES
o Extended operating temperature range (-55°C:5 TA
:5 125°C)
o
o
Combination static storage cells and dynamic control
circuitry for truly high performance
o
Standby power dissipation less than 53mW
o
Single +5V power supply (5% tolerance)
o
Fully TTL compatible
Fanout:
2 - Standard TTL
2 - Schottky TTL
12 - Low Power Schottky TTL
Part Number Access Time
Cycle Time
4104(J)-84
250ns
385ns
o
Standard 18 pin DIP
4104(J)-85
300ns
510ns
o
Leadless chip carrier (E package) available for high
density applications
o
Ruggedized for use in severe military environments
Average power dissipation less than 150mW
The Mostek MKB4104 is a high performance static
random access memory organized as 4096 one bit
words. The MKB41 04 combines the best characteristics
of static and dynamic memory techniques to achieve a
TTL compatible, 5 volt only, high performance, low
power memory device. It utilizes advanced circuit
design concepts and an innovative state-of-the-art Nchannel silicon gate process specially tailored to provide
static data storage with the performance (speed and
power) of dynamic RAMs. Since the storage cell is static
the device may be stopped indefinitely with the CE clock
in the off (Logic 1) state.
FUNCTIONAL DESCRIPTION
PIN CONNECTIONS
DESCRIPTION
17
'-+
CLOCK
GEN
Ao'
A12
A2 3
A3 4
-Jo,
,-y
..
'
ROW
ADDRESS
BUFFERS
ROW
DECODe
~
+
CLOCK
GEN
-----.
f+
.,~
COL
ADDRESS
BUFFERS
COWMN
DECODE
15 As
14 Ag
~5
~
AS 6
13
12
11
10
DOUT7
64x64
STORAGE
ARRAY
-'"
~
DATA
INPUT
BUFFER
DATA
OUTPUT
BUFFER
...
18
1
2
18 VCC
17 As
16
16 A7
WE8
VSS 9
3
16
4
14
6
A10 13
A11
6
DIN
7
12
CE
11
10
9
8
PIN NAMES
AO-All
CE
DIN
DOUT
XII-39
Address Inputs
Chip Enable
Data Input
Data Output
VSS
~
Ground
Power (+5V)
Write Enable
£I
ABSOLUTE MAXIMUM RATINGS*
Voltage on any pin relative to VSS ........................................................... -1.0V to +7.0V
Operating Temperature TA (Ambient) ......................................................... -55°C to +125°C
Storage Temperature (Ambient)(Ceramic) .................................................. -65°C to +150°C
Power Dissipation ................................................................................ 1 Watt
Short Circuit Output Current ........................................................................ 50rnA
·Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This IS a stress rallng only and functIonal
operation of the device at these or any other conditions above those indicated In the operation sections of this specIfication IS not Imphed Exposure to absolute
maximum rallng conditIons for extended periods may affect rehablilty
RECOMMENDED DC OPERATING CONDITIONS6
(-55°C:5 TA:5 +125°C)
SYM
PARAMETER
MIN
TYP
MAX
UNITS
NOTES
VCC
Supply Voltage
4.75
5.0
5.25
V
1
VSS
Supply Voltage
0
0
0
V
1
VIH
Logic "1" Voltage All Inputs
2.4
7.0
V
1
VIL
Logic "0" Voltage All Inputs
-1.0
.65
V
1
MAX
UNITS
NOTES
DC ELECTRICAL CHARACTERISTICS
(-55°C:5 TA:5 +125°C) (VCC =5.0 volts ± 5%)
MIN
SYM
PARAMETER
ICCl
Average VCC Power Supply Current
27
rnA
2
ICC2
Standby VCC Power Supply Current
10
rnA
3
IlL
Input Leakage Current (Any Input)
-10
10
4
IOL
Output Leakage Current
-10
10
JJA
JJA
3,5
VOH
= -500JJA
Output Logic "-" Voltage lOUT = 5mA
V
11
0.4
V
11
TYP
MAX
NOTES
VOL
2.4
Output Logic "1" Voltage lOUT
AC ELECTRICAL CHARACTERISTICS
(-55°C:5 TA:5 +125°C) (VCC = +5.0 volts ± 5%)
SYM
PARAMETER
MIN
CI
Input Capacitance
4pF
6pF
14
Co
Output Capacitance
7pF
7pF
14
NOTES:
10.
1.
2.
3.
4.
5.
6.
7.
8.
9.
All voltages referenced to vss.
ICC 1 is related to precharge and cycle times. Guaranteed maximum values
for ICCl are at minimum cycle time.
Output is disabled (open circuit). CE is at logic 1 .
All devicepinsatOvoltsexceptpin under test atO:5VIN:5 5.5V(VCC 5V)
OV:5 VOUT:5 • 5.5V (VCC 5V)
During power up.
andINE must be at VIH for minimum of 2ms afterVCC
reaches 4.75V. before a valid memory cycle can be accomplished.
Measured with load circuit equivalent to 2 TTlloeds and Cl l00pF.
If WE follows after CE by more than twS. then data out may not remain
open circuited.
Determined by user. Total cycle time cannot exceed tCF max.
er
11.
12.
13.
14.
15.
16.
XII-40
Data· in set· up time is referenced to the later of the two fa iling clock edges
CEorWE.
AC measurements assume tl 5ns. Timing points are taken at .8V and
2.OV on inputs and .8V and 2.OV on the output. Transition times are also
taken between these levels.
tc tCl' tp , 2tl·
The true level of the output in the open circuit condition will bedetermined
totally by output load conditions. The output is guaranteed to be open
circuit within tOFF.
Effective capacitance calculated from the equation C 1 c.t with C.V
equal to 3V and VCC nominal.
C.V
For RMW. tCE tAC' twPL ' 5MOD
tc tAC' twPl 'tp , 3tl ·tMOD·
AC ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS6,"
(-55°C::; TA::; +125°C) (VCC = +5.0 Volts ± 5%)
MKB41 04-84 MKB41 04-85
SYM
PARAMETER
tc
MIN
MAX
MIN
Read or Write Cycle Time
410
510
tAC
Random Access
250
tCE
Chip Enable Pulse Width
250
tp
Chip Enable Precharge Time
150
200
ns
tAH
Address Hold Time
135
165
ns
tAS
Address Set-Up Time
0
tOFF
Output Buffer Turn-Off Delay
0
tws
Write Enable Set-Up Time
0
tDHC
Data Input Hold Time Referenced
to CE
tDHW
5000
300
MAX UNITS
ns
12
300
ns
7
5000
ns
15
ns
0
65
ns
13
0
ns
8
210
250
ns
Data Input Hold Time Referenced
toWE
90
105
tww
Write Enabled Pulse Width
60
90
tMOD
Modify Time
0
tWPL
WE to CE Precharge Lead Time
tDS
5000
0
NOTES
0
75
ns
5000
ns
9
10
85
105
ns
Data Input Set-Up Time
0
0
ns
tWH
Write Enable Hold Time
185
225
ns
tT
Transition Time
tRMW
Read-Modify-Write Cycle Time
tRS
Read Set-Up Time
5
50
5
50
ns
500
620
ns
0
0
ns
16
All input levels, including write enable (WE) and chip
enable (CE) are TIL with a one level of 2.4 volts and a
zero level of .65 volts. The push-pull output (no pull-up
resistor required) delivers a one level of 2.4V minimum
and a zero level of .4 volts maximum. The output has a
fanout of 2 standard TIL loads or 1210w power Schottky
loads.
Power supply requirement of +5V combined with TIL
compatibility on all 1/0 pins permits easy integration
into large memory configurations. The single supply
reduces capacitor count and permits denser packaging
on printed circuit boards. The 5V only supply
requirement and TIL compatible 1/0 makes this part an
ideal choice for next generation +5V only microprocessors such as Mostek's zao. The early write mode
(WE active prior to eE) permits common 1/0 operation,
needed for Z80 interfacing, without external circuitry.
The RAM employs an innovative static cell which
occupies a mere 2.75 square mils (y2 the area of
previous cells) and dissipates power levels comparable
to CMOS. The static cell eliminates the need for refresh
cycles and associated hardware thus allowing easy
system implementation.
Reliability is greatly enhanced by the low power
dissipation which causes a maximum junction rise of
only 6.6° at 1.6 Megahertz operation. The MKB4104
was designed for the system designer and user who
require the highest performance available along with
Mostek's proven reliability.
DESCRIPTION (Continued)
SUPPLEMENTAL DATA SHEET TO BE USED IN CONJUNCTION
WITH MOSTEK MK4104(P/N) DATA SHEET
XII-41
II
XII-42
MOSTEI(.
16,384 x 1-81T DYNAMIC RAM
Processed to MIL-STD-883, Method 5004, Class 8
MKB4116(P/ J)-82/83/84
MKB4116(E/F)-83/84
FEATURES
o Extended operating temperature range (-55°C::; T C
::; +11 O°G)
o Common I/O capability using "early write" operation
o Recognized industry standard 16-pin configuration
from Mostek
o Read-Modify-Write, RAS-only refresh, and Pagemode capability
o 150ns access time, 320ns cycle (MKB4116-82)
200ns access time, 375ns cycle (MKB4116-83)
250ns access time, 41 Ons cycle (MKB4116-84)
o All inputs TTL compatible, low capacitance, and
protected against static charge
o
± 10% tolerance on all power supplies (+12V, ± 5V)
o Low power: 462mW active, 30mW standby (max)
o Output data controlled by CAS and unlatched at end
of cycle to allow two dimensional chip selection and
extended page boundary
o 128 refresh cycles (2msec refresh interval)
o Leadless chip carrier(E) and flat pack(F) available for
high density applications, -83/84
o Ruggedized for use in severe military environments
DESCRIPTION
The MKB4116 is a new generation MOS dynamic
random access memory circuit organized as 16,384
words by 1 bit. As a state-of-the-art MOS memory
device, the MKB4116 (16K RAM) incorporates
advanced circuit techniques designed to provide wide
operating margins, both internally and to the system
user, while achieving performance levels in speed and
power previously seen only in Mostek's high
performance MK4027 (4K RAM).
The technology used to fabricate the MKB4116 is
Mostek's double-poly, N-channel silicon gate, POLY ITM
process. This process, coupled with the use of a single
transistor dynamic storage cell, provides the maximal
circuit density and reliability, while maintaining high
performance capability. The use of dynamic circuitry
throughout, including sense amplifiers, assures that
power dissipation is minimized without any sacrifice in
speed or operating margin. These factors combine to
make the MKB4116 a truly superior RAM product.
BLOCK DIAGRAM
PIN CONNECTIONS
15 16
---;::::========::[)
VBB
DIN
2
15
CAS
WRITE
3
14
DOUT
RAS 4
13
A6
5
12
A3
AO
m
A26
"---~
1
2
1
AI
7
VDD
8
11
14
3
13
4
NC
NC
A4
10
A5
12
5
11
6
9 vcc
10
9
8
7
PIN NAMES
"---~
. . -COl........
SEuel
LINU-- - -
AO - A6Address inputs
CAS
Col. Address Strobe
Data in
Data Out
Row Address Strobe
WRiTE
VBB
VCC
V DD
VSS
Read/Write input
Power (-5V)
Power (+5V)
Power (+12V)
Ground
II
ABSOLUTE MAXIMUM RATINGS*
Voltage on any pin relative to VSS' .......................................................... -0.5V to +20V
Voltage on VDD, VCC supplies relative to VSS .............................................. -1.0V to +15.0V
VSB - VSS (VDD - VSS > OV) .......................................................................... OV
Operating Temperature, TC (Case) ......................................................... -55°C to +11 O°C
Storage Temperature (Ambient) ........................................................... -65°C to +150°C
Short Circuit Output Current. ....................................................................... 50mA
Power Dissipation ................................................................................ 1 Watt
*Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS6
(-55°C:S TC :S +11 O°C)
SYM
PARAMETER
MIN
TYP
MAX
UNITS
NOTES
VDD
Supply Voltage
10.8
12.0
13.2
Volts
2
VCC
Supply Voltage
4.5
5.0
5.5
Volts
2,3
VSS
Supply Voltage
0
0
0
Volts
2
Vss
Supply Voltage
-4.5
-5.0
-5.5
Volts
2
VIHC
Input High (Logic 1) Voltage,
RAS, CAS, WRITE
2.7
-
7.0
Volts
2
Input High (Lo9.!£.]) Volta~
inputs except RAS, CAS, WRITE
2.4
-
7.0
Volts
2
Input Low (Logic 0) Voltage, all
inputs
-1.0
-
.8
Volts
2
MAX
UNITS
NOTES
35
mA
4
5
400
p.A
VIH
VIL
DC ELECTRICAL CHARACTERISITCS
(-55°C:S Tc:S +11O°C)(VDD = 5.0V ± 10%; -5.5V:S VBB:S -4.5V; VSS = OV)
SYM
PARAMETER
IDD1
ICC1
ISB1
OPERATING CURRENT
supply operating current
(RAS, CAS cycling; tRC = tRC (min)
IDD2
ICC2
IBS2
STANDBY CURRENT
Power supply standby current (RAS '" VIHC'
DOUT = High Impedance)
-10
2.25
10
200
mA
p.A
p.A
IDD3
ICC3
IBS3
REFRESH CURRENT
Average power supply current, refesh mode
(RAS cycling, CAS'" VIHC; tRC = tRC min)
27
10
400
mA
p.A
p.A
4
-10
IDD4
ICC4
ISB4
PAGE MODE CURRENT
Average po~ supply~ent page-mode
operation (RAS '" VIL' CAS cycling;
tpc '" tpc min)
27
mA
4
5
400
p.A
II(L)
INPUT LEAKAGE
Input leakage, any input (VSS '" -5V, OV :S VIN
:S +7.0V, all other pins not under test'" 0 volts)
-10
10
p.A
IO(L)
OUTPUT LEAKAGE
Output leakage current (DOUT is disabled,
OV:S VOUT:S +5.5V)
-10
10
p.A
0.4
Volts
Volts
VOH
VOL
MIN
Avera~ower
OUTPUT LEVELS
Output high (Logic 1) voltage (lOUT'" -5mA)
Output low (Logic 0) voltage (lOUT'" 4.2mA)
XII-44
2.4
3
NOTES
1.
2.
3.
4.
5.
T C is specified here for operation at frequencies to tRC ;;::: tAC (min).
Operation at higher cycle rates with reduced ambient temperatures and
higher power dissipation is permissible, however, provided AC operating
parameters are met.
All voltages referenced to VSS'
Output voltage will swing from VSS toVccwhen activated with no current
loading. For purposes of maintaing data in standby mode. Vee may be
reduced to VSS without affecting refresh operations or data retention.
However, the VOH (min) specifications is not guaranteed in this mode.
1001.1003. and 1004 depend on cycle rate. See Figures2. 3 and4for 100
limits at other cycle rates.
ICCl and ICC4 depend upon output loading. During readout of high level
data Vee is connected through a low impedance(135 fityp)todata out. At
all other times ICC consists of leakage currents only.
6.
7.
8.
9.
10.
11.
12.
Several cycles are required after power~up before proper device operation
is achieved. Any 8 cycles which perform refresh are adequate for this
purpose.
AC measurements assume t1 5ns.
VIHc(min) or VIL (max) are reference levels for measuring timing of input
signals. Also, transition times are measured between VIHC or VIH or VIL'
The specificationsfortRc(min)tRMW(min) are used only to indicate cycle
which proper operation over the full temperature range (-55 D C :$ TC :s
110°C) is assured.
Assumes that tRCO :$ tRCO (max). If tRCO is greater than the maximum
recommended value shown in this table, tRCDwi11 increase bytheamount
that tRCO exceeds the value shown.
Assumes that tRCO 2: tRCO (max)
Measured with a load equivalent to 2 TIL loads and 100pF.
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (6/.8)
.(-55°C :s TC :s 11 O°Cp (VDD = 12.0V ± 10%; VCC = 5.0V ± 10%, VSS = OV. -5.5V:S VBB :s -4.5V)
MKB4116-82 MKB4116-83 MKB4116-84
SYM PARAMETER
MAX
MIN
MAX
MIN
MAX
UNITS
NOTES
320
375
410
ns
9
tRWC Read-write cycle time
320
375
425
ns
9
~MVIi Read-modify-write cycle time
320
405
500
ns
9
Page mode cycle time
170
225
275
ns
9
tRC
tpc
Random read or write cycle time
MIN
tRAC Access time from RAS
150
200
250
ns
10.12
tCAC Access time from CAS
100
135
165
ns
11.12
tOFF Output buffer turn-off delay
tor
Transition time (rise and fall)
tRP
RAS precharge time
0
3
40
35
100
0
3
50
0
60
ns
13
50
3
50
ns
8
ns
150
120
tRAS RAS pulse width
150
tRSH RAS hold time
100
135
165
ns
tCSH CAS hold time
150
200
250
ns
tCAS CAS pulse width
100
5000
135
5000
165
5000
tRCD RAS to CAS delay time
20
50
25
65
35
85
tCRP CAS to RAS precharge time
0
tASR Row Address set-up time
0
tRAH Row Address hold time
5000
200
5000
250
5000
ns
ns
ns
0
0
ns
0
0
ns
20
25
35
ns
tASC Column Address set-up time
0
0
0
ns
tCAH Column Address hold time
45
55
75
ns
Column Addr~old time
referenced to R
95
120
160
ns
tRCS Read command set-up time
0
0
0
ns
tRCH Read command hold time
0
0
0
ns
twCH Write command hold time
45
55
75
ns
twCR Write comma~ld time
referenced to RA
95
120
160
ns
45
55
75
ns
tAR
twp
Write command pulse width
XII-45
15
II
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (6,7,8)
(-55°C ::s TC ::s +11 0°C)1 (VDD = 12.0V ± 10010; VCC = 5.0V ± 10%, VSS = OV, -5.5V::S VBB ::s -4.5V)
MKB4116-83
MKB4116-82
SYM PARAMETER
MIN
tDH
Date-in hold time
tDHR
tcP
Da~
to
MIN
MAX UNITS NOTES
85
ns
50
70
85
ns
0
0
0
ns
15
45
55
75
ns
15
95
120
160
ns
60
80
100
ns
50
tCWL Write command to CAS lead time
Data-in set-up time
MAX
70
tRWL Write command to RAS lead time
tDS
MIN
MAX
MKB4116-84
hold time referenced
CAS precharge time (for pagemode cycle only)
tREF Refresh period
2
2
2
ms
19
twcs WRITE command set-up time
0
0
0
ns
16
tCWD CAS to WRITE delay
60
80
90
ns
16
tRWD RAS to WRITE delay
110
145
175
ns
16
AC ELECTRICAL CHARACTERISTICS
(-55°C::S TC ::s +11 O°C) (VDD = 12.0V ± 10%; VSS
SYM
PARAMETER
CI1
= OV; -5.5V ::s VBB ::s -4.5V)
TYP
MAX
UNITS
NOTES
Input Capacitance (AO - A6), DIN
4
5
pF
17
CI2
Input Capacitance, RAS, CAS, WRITE
8
10
pF
17
Co
Output Capacitance (DOUT)
5
7
pF
17,18
NOTES: Continued
'3.
16.
14.
tOPI (max) defines the time at which the output achieves the open circuit
condition and is not referenced to output voltage levels.
Operation within the tRCO (max) limit insures that tRAe (max) can be met
tRCD (max) is specified as a reference point only, iftRCP is greater than the
specified tACO (max) limit. then access time is controlled exclusively by
15.
tCAC'
These parameters are referenced to CAS leading edge in early write cycles
and'to WRITE leading edge in delayed write or read-modify-write cycles.
17.
1B.
twcs, leWD, andtRWD are restrictive operating parameters in read-write
and read-modify-write cycles only. If tWCS:;; twcs (min), the cycle is an
early write cycle and the data out pin will remain open circuit (high
impedance) throughout the entire cycle. If tCWD:;; tewD (min) and tRWD
:$ tRwe (min), the cycle is a read·write cycle and the data out will contain
data read from the selected cell. If neither of the above sets of conditions is
satisfied the condition of the data out (at access time) is indeterminate.
Effective capacitance calculated from the equation C IAt with AV 3
volts and power supplies at nominal levels.
AV
CAS: VIHC to disable DOUT·
=
=
DESCRIPTION (Continued)
Multiplexed address inputs (a feature pioneered by
insertion equipment, provides highest possible system
Mostek for its 4K RAMs) permits the MKB4116 to be
bit densities and simplifies system upgrade from 4K to
16K RAMs for new generation applications. Non-critical
packaged in a standard 16-pin DIP. This recognized
industry standard package configuration, while comclock timing requirements allow use ofthe multiplexing
patible with widely available automated testing and
technique while maintaining high perfomance.
SUPPLEMENTAL DATA SHEET TO BE USED IN CONJUNCTION
WITH MOSTEK MK4116-2/3 AND MK4116-4, DATA SHEETS
XII-46
MOSTEI(.
MILITARY HIGH-REL PRODUCTS
Processed to MIL-STD-883, Method 5004, Class B
1 K X 8-Bit Static RAM
MKB4118A(P/J/E)-82/83/84
FEATURES
o
o
Part No.
Access Time
R/W
cycle Time
Tested per MIL-STD-883B method 5004 and qualified
per method 5005.
MKB4118A-82
150 nsec
150 nsec
Static operation, single +5 V power supply
MKB4118A-83
200 nsec
200 nsec
MKB4118A-84
250 nsec
250 nsec
o Military temperature range (-55°C:::; TA:::; + 125°C)
o Organization: 1K x 8 bit RAM JEDEC pinout
o Pin compatible with Mostek's BYTEWYDpM memory
family
0 CE and OE functions facilitate bus control
o 24128 pin ROM/PROM compatible pin configuration
0 Industrial
M~@>~on available (-40"C/85°C),
••••••••••••••••••• ',' ••••••••••••••••••••••••••••••••••••••••••••••••••• 1 Watt
Output Current .................., .................................................................... 20 mA
<... ............................................
*Stresses greater than those listed under ."Absolute Maximum
Ratin'gs'; may ca~$e permanent da":1age to the device. This is a stress rating only and functional
operat~o.n ..of the device at these or any other conditions above those" indicated int
he operational sections of this specification is n~~ imp.li~d. Exposure to absolute
maximum rating conditions for extended periQds may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS7
(":55°C :::; TA:::; + 125°C)
UNITS NOTES
SYM
PARAMETER
MIN
TYP
MAX
VCC
Supply Voltage
4.75
5.0
5.25
V
1
Vss
Supply Voltage
0
0
0
V
1
V IH
Logic "1" Voltage All Inputs
2.4
7.0
V
1
V IL
Logic "0" Voltage All Inputs
-0,3
.8
V
1,9
DC ELECTRICAL CHARACTERISTICS';'
(-55°C:::; TA:::; + 125°C) (Vcc
= +5.0 V ± 5%)
SYM
PARAMETER
MIN
MAX
UNITS NOTES
ICC1
Average V cc Power Supply Current
90
mA
8
ICC1
Average V cc Power Supply Current TA = 125°C
65
mA
10
IlL
Input Leakage 'Current (Any Input)
-10
10
J,JA
2
IOL
Output Leakage Current
-10
10
J,JA
2
V OH
Output Logic "1 " Voltage lOUT = 1 rnA
2.4
VOL
Output Logic "0" Voltage lOUT = 4 mA
V
0.4
V
AC ELECTRICAL CHARACTERISTICS3
(-55°C:::; TA:::; 125°C) (Vcc
= 5.0 V ± 5%)
MKB4118A-82
MAX
MKB4118A-83
MIN
MAX
MKB4118A-84
MIN
MAX
SYM
PARAMETER
MIN
t RC
Read Cycle Time
150
tAA
Address Access Time
150
200
250
tCEA
Chip Enable Access Time
·75
100
125
ns
250
200
40
UNITS NOTES
45
\
ns
4
ns
4
tCEZ
Chip Enable Data Off Time
tOEA
Output Enable Access Time
tOEZ
Output Enable Data Off Time
,5
tAZ
Address Data. Off Time
10
10
10
ns
twc
Write Cycle Time
150
200
250
ns
5
35
5
100
75
35
XII-48
5
5
40
5
ns
125
ns
45
ns
4
AC ELECTRICAL CHARACTERISTICS3
(-55°C:::; TA :::; +125°C) (Vee = 5.0 V ± 5%)
MKB4118A-82
SYM
PARAMETER
NOTES
t AS
Address Setup Time
0
0
0
ns
see text
tAH
Address Hold Time
50
65
80
ns
see text
tDSW
Data To Write Setup Time
10
15
20
ns
tDHW
Data From Write Hold Time
20
25
30
ns
tWD
Write Pulse Duration
50
60
70
ns
tWEZ
Write Enable Data Off Time
tWPL
Write Pulse Lead Time
5
MAX
MIN
35
MAX
MKB4118A-84
UNITS
CAPACITANCE'·7
(-55°C:::; TA :::; +125°C) (Vee = +5.0 V
MIN
MKB4118A-83
40
5
130
90
MIN
MAX
45
5
see text
ns
170
ns
± 5%)
NOTES
SYM
PARAMETER
TYP
C1
Capacitance on all pins (except D/O)
4 pF
5
CD/ Q
Capacitance on DIO pins
10 pF
5,6
NOTES;
1. All voltages referenced to Vss.
2. Measured with .4:::; V,5.0 V, outputs deselected and Vee = 5 V.
3. AC test conditions: input rise anc;:i fall times::; 5 ns; input levels 0 V to 3 V;
timing measurement reference level 1.5 V.
MAX
OUTPUT LOAD
Figure 3
5V
4. Measured with a load as shown in Figure 3.
5. Effective capacitance calculated from the equation C = f::.Q with 6V;;;: 3 volts
"""KV
and power supplies at nomina/levels.
6. Output buffer is deselected.
7. A minimum of 2 ms time delay is required after application of Vee (+5 V)
before proper device operation can be achieved.
8.ICCl measured with outputs open.
9. Negative undershoots to a minimum of -1.5 V are allowed with maximum of
50 ns pulse width. DC value of low level must not exceed -0.3 V.
10. Power consumption decreases with temperature from a maximum at low
temperature to a minimum at high temperature.
XII-49
1.1 k!l
D.U.T.----.-----.
680 !!
100 pF
(Including Scope and Jig)
III
TIMING DIAGRAM
Figure 4
READ
READ
WRITE
~-----tRC -----I~------ t RC - - - - - I I . j . . . o t - - - - - l w c - - - - - . !
- - - - t A A ---I~
-
WE
tAl
tOEA
<
DQo-DQ7
VALID OUT
r
Y
(
VALID OUT
H
VALID IN
TIMING DIAGRAM
Figure 5
WRITE
WRITE
twc
twc
READ
.-
t RC
tOfA
DO o-D0 7
VALID OUT } - - - - - {
~------~
,-----..1-
XII-50
..--
r-------------~
)
DESCRIPTION (Cont.)
The MKB4118A features a fast CE (50% of Address Access)
function to permit memory expansion without impacting
system access time. A fast OE (50% of access time) is
included to permit data interleaving for enhanced system
performance.
The MKB4118A is pin compatible with Mostek's
BYTEWYDpM memory family of RAMs, ROMs and
EPROMs.
OPERATION
Read Mode
The MKB4118A is in the read mode whenever the Write
Enable Control input (WE) is in the high state.
In the read mode of operation, the MKB4118A provides a
fast address ripple-through access of data from 8 of 8192
locations in the static storage array. Thus, the unique
address specified by the 10 Address Inputs (An) define
which 1 of 1024 bytes of data is to be accessed.
A transition on any of the 10 address inputs will disable the
8 data output drivers after tAZ' Valid Data will be available to
the 8 data output drivers within tAA after the last address
input signal is stable, providing that the CE and OE access
times are satisfied. If CE or OE access times are not met,
data access will be measured from the limiting parameter
(t CEA or tOEA) ratherthan the address. The state ofthe 8 data
1/0 signals is controlled by the Chip Enable (CE) and Output
Enable (OE) control signals.
Write Mode
The MKB4118A is in the write mode whenever the Write
Enable (WE) and Chip Enable (CE) control inputs are in the
low state.
The write cycle is initiated by the WE pulse going low
provided that CE is also low. The leading edge of the WE
pulse is used to latch the status of the address bus.
NOTE: In a write cycle the latter occurring edge of either WE
or CE will determine the start of the write cycle. Therefore,
t AS ' two and tAH are referenced to the latter occurring edge
of CE or WE. Addresses are latched at this time. All write
cycles whether initiated by CE or WE must be terminated by
the rising edge of WE. If the output bus has been enabled
(CE and OE low) then WE will cause the output to go to the
high Z state in t WEZ '
III
DaE!.!n must be valid tosw prior to the low to high tra nsition
of WE. The Data In lines must remain stable for tOHW after
WE goes inactive. The write control of the MKB4118A
disables the data out buffers during the write cycle;
however, OE should be used to disable the data out buffers
to prevent bus contention between the input data and data
that would be output upon completion of the write cycle.
XII-51
XII-52
I!
UNITED
TECHNOLOGIES
MOSTEK
MILITARY
HIGH-REL
PRODUCTS
PROCESSED TO MIL-STD-883, METHOD 500~J
CLASS B, 16,384 x 1-BIT(STATIC RAIVI
MKB4167 P)-870/885/80
FEATURES
o -55 to +125°C operating temperature range
Active
Max
Standby
Max
o
Industry standard 20 pin 300 mil DIP
o
Scaled POLY 5™ technology
MKB4167-870
70 ns
70 ns 660mW
220mW
o
Fully TIL compatible
MKB4167 -885
85 ns
85 ns 660mW
220mW
o
Density upgrade over the 2147
MKB4167-80
100 ns
100 ns 660mW
220mW
o
Chip select power down feature
o
Access time equal to cycle time
disabled mode and the power drops to a fraction of its active
level.
DESCRIPTION
The MKB4167 is a high performance 16K x 1 fully static
RAM suited for either high speed cache memories or for
slower main memory applications. The low standby power
allows maximum packing density with the JEDEC Type F
chip carrier or ths 300 mil wide DIP.
This static RAM offers a cycle time equal to its access time
and has fullyTIL compatible inputs and outputs resulting in
a part that fits easily into a wide range of applications.
A charge pump is employed on the MKB4167 giving the
user two notable advantages. The function of the charge
pump is to negatively bias the substrate giving sufficient
operating margin internally which allows a single 5 V power
supply to be used. Since the charge pump applies a negative
PIN CONNECTIONS
Figure 1
DEVICE OPERATION
The MKB4167 is a fully static Random Access Memory
which accesses one of its 16,384 address locations based
upon the value presented at its 14 address input pins. This
power gated part will function in either a ripple through
fashion when the Chip Select (CS) line is held active (low) or
as a clocked part with the CS selecti ng the device. When the
CS returns high the output is placed in a high impedance or
TRUTH TABLE
Ao 1
20 vee
A, 2
19 A'3
A2 3
A3 4
17 A"
18 A12
A. 5
16 A,o
A. 6
15 Ag
A. 7
14 As
DOUT 8
WE 9
vss 10
13 A7
12 D'N
11
cs
PIN NAMES
Ao - A13
CS
WE
Mode
Output
Power
H
L
L
X
Not Selected
Write
Read
HighZ
HighZ
DOUT
Standby
Active
Active
CS
DIN
L
H
Access
Time
Cycle
Time
Part
Number
Dour
Vss
Vee
WE
XII-53
Address Inputs
Chip Select
Data Input
Data Output
Ground
Power (+5 V)
Write Enable
ABSOLUTE MAXIMUM RATINGS*
Voltage on any pin relative to Vss ................................................ " ............ -2.0 V to +7 V
Operating temperature (T d .................................................................. -55°C to +125°C
Storage temperature (Ambient) .............................................................. -65°C to +150°C
DC output current ....•............................................................................. 20 mA
Power dissipation ..........................................................•........................ 1 Watt
"Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS\10
(-55°C ~ Te ~ +125°C)
SYM
PARAMETER
MIN
TYP
MAX
UNITS NOTES
Vee
Supply Voltage
4.5
5.0
5.5
V
1
Vss
Supply Voltage
0
0
0
V
1
V1H
Logic '"1'" Voltage All Inputs
2.0
-
V ee +1
V
1
V1L
Logic '"0" Voltage All Inputs
-2.5
-
0.8
V
1
DC ELECTRICAL CHARACTERISTICS1.10
(-55°C ~ Te ~ +125°C) (Vee = 5.0 V ± 10%)
MKB4167-870 MKB4167·885 MKB4167·80
MIN
MAX MIN
MAX MIN
MAX UNITS NOTES
SYM
PARAMETER
lee
Operating Current AC (tRe
lee
Operating Current (te
ISB
=t Re min)
120
120
120
mA
9
90
90
90
mA
9,11
Standby Current (CS 2: V 1H )
40
40
40
mA
IL
Input Leakage Current (Any Input)
10
10
10
p.A
3,12
IOL
Output Leakage Current
50
50
50
p.A
2
V OH
Output Logic '"1 '"
Voltage lOUT = -4 mA
VOL
Output Logic '"0'"
Voltage lOUT = 8 mA
= 125°C)
2.4
2.4
2.4
0.4
XII-54
0.4
V
0.4
V
RECOMMENDED AC OPERATING CONDITIONS AND ELECTRICAL CHARACTERISTICSlO
(-55°C -S:TC -s: +125°C)(V cc = 5.0 V ± 10%)
READ CYCLE TIMING
MKB4167-870 MKB4167-885 MKB4167-80
MAX UNITS NOTES
MAX MIN
MIN
MAX MIN
SYM
PARAMETER
t RC
Read Cycle Time
tAA
Address Access Time
70
85
100
ns
6
tCSA
Chip Select Access Time
70
85
100
ns
6
tOH
Output Hold From Address Change
5
5
5
ns
tLZ
Chip Selection to Output Low Z
10
10
10
ns
tHZ
Chip Deselection to Output High Z
0
tpu
Chip Selection to Power Up Time
0
tpD
Chip Deselection to Power Down
30
ns
100
85
70
0
35
40
0
ns
0
0
70
60
50
7
ns
ns
WRITE CYCLE TIMING
MKB4167-870 M KB4167 -885 MKB4167-80
MIN
MAX MIN
MAX MIN
MAX UNITS NOTES
SYM
PARAMETER
twc
Write Cycle Time
70
85
100
ns
tcw
Chip Select to End of Write
60
75
85
ns
tAW
Address Valid to End of Write
60
75
85
ns
tAS1
Address Setup Time WE
Controlled Cycle
10
10
10
ns
t AS2
Address Setup Time CS
Controlled Cycle
0
0
0
ns
twp
Write Pulse Width
40
55
65
ns
tWR
Write Recovery Time
0
0
0
ns
tDW
Data Valid to End of Write
30
35
40
ns
tDH
Data Hold Time
10
10
10
ns
twz
Write Enable to Output in High Z
0
tow
Output Active From End of Write
0
35
45
0
0
0
50
0
ns
7
ns
CAPACITANCE'
(-55°C -s: Tc -s: +125°C)(Vcc = +5.0 V ± 10%)
MAX
UNITS
NOTES
Input Capacitance
5
pF
8
Output Capacitance
6
pF
8,9
SYM
PARAMETER
CIN
COUT
XII-55
READ CYCLE NUMBER 1 (5,6)
Figure 2
DATA OUT
PREVIOUS DATA VALID
DATA VALID
READ CYCLE NUMBER 2 (5,7)
Figure 3
t RC
::,
...., ttCSA
•
t+- t HZ -+
tLZ
HIGH IMPEDANCE
DATA OUT
~;:;.'CV
CURRENT
VX X X
\ r - - HIGH
DATA VALID
J
"" IS8
I MPEDANCE
-----=r?,....5-0-%-------------------------~~1t '"'
~tpu
u
~tpo_
-
WRITE CYCLE NUMBER 1
(WE CONTROLLED)
Figure 4
~C
ADDRESSES
~V
---'
tcw
CS
\
-Ir
7 ttAW
t AS1
WE
DATA IN
~p
"-
f-- twR-
:+tOH~
tow
)
~
DATA INVALID
---------D-A-T-A-U-N-D-E-FI-N-ED------~
-twz
DATA OUT
I I
XII-56
t+--
tow
IIII
WRITE CYCLE NUMBER 2
ICS CONTROLLED)
Figure 5
fwe
ADDRESSES
--\I
/
-.-..J
t AS2
tew
71-
-'~
tAW
I-fwR-
fwp
\\\\\\\\\\
IIIIIIII
- tDH ..
tDW
~
DATA IN
DATA INVALID
'I
-------------------D-A-T-A-U-N-D-E-F-IN--ED------------~~--------------------r-----------
=:>I
[-tW2
DATA OUT
HIGH IMPEDANCE
A.C. TEST CONDITIONS
OUTPUT LOAD
Input Levels ........................ O V to 3.0 V
Transition Times ................... 5 ns
Input timing reference level ....... 1.5 V
Output timing reference levels .... 0.8 V - 2.0 V
Output load ........................ See figure
5V
480
n
DOUT------~~----------.
255
n
30 pf
(including scope
jig capacitance)
NOTES;
1. All voltages referenced to VSS.
8. Effective capacitance calculated from the equation
2. es = VIH, Vce = MAX, VOUT = Vss to 4.5 V.
3. Vee = MAX. Also 0:; VIN :; vee.
twz
4. tHZ and
defines the time at which the output achieves the open circuit
condition and is not referenced to output voltage levels.
5. WE is high for Read Cycles.
6. Device is continuously selected CS::; VIL.
7. Addresses valid prior to or coincident with CS transition low.
c;::: 1M with!::"V:::: 3 volts
6V
and power supplies at nominal levels. This parameter is sample te5ted only.
9. Output buffer is deselected.
10. A minimum of 2 ms is required following the application of Vee (+5 V) before
proper device operation is achieved.
11 Power consumption decreases with increasing temperature.
XII-57
bias to the substrate, it also allows large negative values to
exist on the inputs without the fear of damaging the device.
Large negative spikes have other drawbacks though, as
discussed in the application section. To allow the charge
pump sufficient start up time, 2 ms is required following the
appl ication of Vee prior to device operation.
A CS controlled write cycle is shown in Figure 5. In this
cycle, timing is referred to the rising edge of CS, and both
the addresses and WE may change following that time.
Note that the data must remain valid for t DH .
Read Cycle
All high speed NMOS devices share the trait that their
current consumption is composed of high frequency
transients. Proper device operation depends on both the use
of decoupling capacitors and low impedance printed circuit
board paths for both Vee and VSS·
A read cycle occurs whenever WE is high and the part is
selected. Access time is measured from either the falling
edge of CS or from the stable address.
The read cycle number 1 waveform shown in Figure 2
demonstrates the fully static operation of this part when CS
is held active. The output retains the previous valid data for
t OH ' after which it is indeterminate until tAA The output will
remain valid until there is a transition on the address inputs
and another read cycle occurs.
Operation as shown in read cycle 2 (Figure 3) will take
advantage of the power gating feature. If the addresses
become stable prior to or as CS falls operation is as shown
for read cycle 2. The output changes from a high impedance
mode after tLl and becomes indeterminate until teEA when
it is valid.
POWER SUPPLY GRIDDING
When a designer has the ability to take advantage of
multilayer board construction for separate Vss and Vee
power planes on optimal low inductance path for power
distribution can be had. If a two layer approach is chosen,
some care in the design to fully grid Vee and V ss on both
sides of the board will give quite satisfactory results.
Regardless of the approach taken, a high frequency
decoupling capacitor (0.1 I.d) should be placed next to each
device with larger tantalum capacitors for each row of
devices. These efforts will help reduce the ringing on Vee
and V ss due to the long inductive path between the power
supply and the device.
LINE TERMINATION
Once the cycle is ended by the rising edge of CS, the output
becomes undefined. T PD later the part is in the standby
mode.
A write cycle is initiated by the later of CS or WE going low
and is terminated by the rising edge of CS orWE. The output
remains in a high impedance mode during a write cycle.
To take advantage of high speed memories, high speed TIL
drivers are often used. Unfortunately, a printed circuit board
trace terminating into a MOS input behaves line an
unterminated transmission line. Ringing is the natural
result with the potentially destructive voltage levels and
noise induced into neighboring PC traces. While the
MKB4167 with its charge pump can withstand -2.0 V on
any input. such large negative spikes result in a noisy board.
A write enable (WE) controlled write cycle is shown in
Figure 4. The addresses must be valid for t ASI prior to the
falling edge of WE and remain valid for tWR after WE has
gone high. If these times are not met. the contents of other
cells may be altered. The data in valid is referenced to the
rising edge of WE. Once WE goes high, the output again
goes active and a read cycle may begin.
Series termination is a method to dampen these reflections
in an easy to implement fashion. By placing a 30 n to 5 n
resistor at the TIL driver's output, the effective impedance
of the driver has been raised to more closely match the
impedance of the PC trace. These printed circuit board
design ideas are explained in more detail in the Memory
Data Book And Designers Guide.
Write Cycle
XII-58
MOSTEI(.
32,768 x 1-81T DYNAMIC RAM
Processed to MIL-STD-883, Class 8
MKM4332(D}-83/84
FEATURES
o Extended operating temperature range -55°C::::: TC :::::
110°C
o Utilizes two industry standard MKB4116 devices in chip
carriers mounted on an 18-pin ceramic motherboard DIP
o Read-Modify-Write, RAS-only refresh capability
o All inputs TTL compatible, low capacitance, and
protected against static charge
o 128 refresh cycles (2 msec refresh interval)
o 200ns access time, 375ns cycle (MKM4332-83)
250ns access time, 41 Ons cycle (MKM4332-84)
o Pin compatible to MKB4116, MKB4516 and MKB4164
o Separate RAS, CAS Clocks
o
o Detailed test flows for the individual MKB4116 chip
carriers and the completed D-package motherboard
assembly are presented in the last pages of this data
sheet.
± 10% tolerance on all power supplies (+12V, ± 5V)
o Low power: 482mW active, 40mW standby (max)
DESCRIPTION
o Output data controlled by CAS and unlatched at end of
cycle to allow two dimensional chip selection and
extended page boundary
o Common 1/0 capability using "early write" operation
The MKM4332 is a new generation MOS dynamic random
access memory circuit organized as 32,768 words by 1 bit.
As a state-of-the-art MOS memory device, the MKM4332
(32K RAM) incorporates advanced circuit techniques
FUNCTIONAL DIAGRAM
PIN CONNECTIONS AND MKB4116 COMPATIBILITY
MKM4332D
v••
I
RAS 1
CAS 1
WE
I
4116
-RAS 2
-CAS 2
I
WRITE 3
RAS
4
13 A.
Ao
5
14 A3
Ao
5
12 A3
A2
6
13 A.
A2
6
11 A.
I
A,
7
12 As
A,
7
10 As
I
voo
8
11
voo
8
9
I
RAS 2 9
I
I
4116
16 Vss
15 CAS
2
15 As
100UT
'--
D'N
16 DOUT
DIN
~
v••
4
I
I
I
18 Vss
17 CAS 1
WRITE 3
AO· A6
I
2
RAs1
I
I
D'N
MKB4116J
I
vee
14 DOUT
10 CAS 2
PIN NAMES
I
I
D'N
~T
RAS
XII-59
Address Inputs
Column Address
Strobe
Data In
Data Out
Row Address Strobe
WRITE
Vss
Read/Write Input
Power (-51
Vee
Voo
V ss
Power (+5VI
Power (i 12VI
Ground
vee
II
ABSOLUTE MAXIMUM RATINGS*
Voltage on any pin relative to Vss .............................................................. -O.5V to +20V
Voltage on V DD , Vcc supplies relative to Vss ................................................... -1.0V to +15.0V
Vss - Vss (V DD - Vss > OV) .............................................................................. OV
Operating Temperature, Tc (case operating) ................................................... -55°C to +11 O°C
Storage Temperature (Ambient) .............................................................. -65°C to +130°C
Short Circuit Output Current ......................................................................... 50mA
Power Dissipation .................................................................................. 1 Watt
*Stressesgreater than those li!?ted under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS·
(O°C :::; Tc :::; 110°C)
SYM
PARAMETER
MIN
TYP
MAX
UNITS
NOTES
V DD
Supply Voltage
10.8
12.0
13.2
V
2
Vcc
Supply Voltage
4.5
5.0
5.5
V
2,3
Vss
Supply Voltage
0
0
0
V
2
Vss
Supply Voltage
-4.5
-5.0
-5.5
V
2
V IHC
Input High (Logic 1) Voltage RAS,
CAS, WRITE
2.4
-
7.0
V
2
Input High (Logic 1) Voltage all inputs
exceptRAS, CAS, WRITE
2.2
-
7.0
V
2
Input Low (Logic 0)
Voltage, all inputs
-1.0
-
.8
V
2
MAX
UNITS
NOTES
37.5
mA
4
5
400
p.A
4.5
20
200
mA
-20
27
20
400
mA
-20
29.5
mA
400
p.A
20
p.A
V IH
V IL
DC ELECTRICAL CHARACTERISTICS
(O°C:::; Tc:::; 110°C) (V DD = 12.0V ± 10%; Vcc
= 5.0V ± 10%; -5.5V:::; Vss:::; -4.5V; Vss = OV)
SYM
PARAMETER
IDD1
ICCl
ISSl
OPERATING CURRENT
Average power supply operating current
(RAS, CAS cycling; t RC = t RC Min)
IDD2
ICC2
ISS2
STANDBY CURRENT
Power supply standby current (RAS
Dour = High Impedance)
IDD3
ICC3
ISS3
REFRESH CURRENT
Average power supply current, refresh mode
IDD4
ICC4
PAGE MODE CURRENT
Average power supply current,
page-mode operation
(RAS = V IL, CAS cycling; tpc = tpc Min)
ISS4
II(L)
MIN
= V IHC
p.A
p.A
4
p.A
p.A
4
5
INPUT LEAKAGE
Input leakage current, any input (Vss = -5V, OV:::;
V IN :::; + 7.0V, all other pins not under test = 0 volts)
XII-50
-20
SYM
PARAMETER
MIN
MAX
UNITS
IO(L)
OUTPUT LEAKAGE
Output leakage current (DOUT is disabled, OV:::;
VOUT :::; +5.5V)
-20
20
}JA
0.4
V
V
V OH
VOL
OUTPUT LEVELS
Output high (Logic 1) voltage (lOUT = -5mA)
Output low (Logic 0) voltage (lOUT = 4.2mA)
2.4
NOTES
3
NOTES
1. T C is specified here for operation at frequencies to tRe
:s
or
tRC (min),
Operation at higher cycle rates with reduced ambient temperatures and
higher power dissipation is permissible, however, provided AC operating
parameters are met. See supplemental MK4332 data sheet for AC derating
curves.
2. All voltages referenced to VSS'
3. Outp,ut voltage will swing from VSS to Vee when activated with no current
loading. For purposes of maintaining data in standby mode. Vee may be
reduced to VSS without affecting refresh operations
data retention.
However, the VOH (min) specification is not guaranteed in this mode.
4.1001. 1003. and 1004 depend on cycle rate.
5.ICC1 and ICC4 depend upon output loading. During readout of high level
data VCC is connected through a low impedance (135 n typ) to data out. At
all other times ICC.consists of leakage currents only.
ElECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS(6,1,8)
(O°C:::; TC:::; 11O°C)1 (V DD = 12.0V ± 10%; VCC = 5.0V ± 10%, VSS = OV, -5.5V:::; Vaa:::; -4.5V)
MKM4332-83 MKM4332-84
SYM
PARAMETER
MIN
t RC
Random read or write cycle time
375
t Rwc
Read-write cycle time
tRMW
UNITS
NOTES
410
ns
9
375
425
ns
9
Read modify write cycle time
405
500
ns
9
tpc
Page mode cycle time
225
275
ns
9
t RAc
Access time from RAS
200
250
ns
10,12
t CAC
Access time from CAS
135
165
ns
11,12
tOFF
Output buffer turn-off delay
0
50
0
60
ns
13
tT
Transition time (rise and fall)
3
50
3.
50
ns
8
t RP
RAS precharge time
120
t RAS
RAS pulse width
200
t RSH
RAS hold time
135
165
ns
tCSH
CAS hold time
200
250
ns
tCAS
CAS pulse width
135
5000
165
5000
ns
t RCD
RAS to CAS delay time
25
65
35
85
ns
t CRP
CAS to RAS precharge time
0
0
ns
t ASR
Row Address set-up time
0
0
ns
tRAH
Row Address hold time
25
35
ns
tAS C
Column Address set-up time
0
0
ns
tCAH
Column Address hold time
55
75
ns
XII-61
MAX
MIN
MAX
ns
150
5000
250
5000
ns
14
MKM4332-8~ I MKM4332-84
SYM
PARAMETER
MIN
MAX
MIN
tAR
Column Address hold time referenced
to RAS
120
160
ns
t RCS
Read command set-up time
0
0
ns
t RCH
Read command hold time
0
0
ns
t WCH
Write command hold time
55
75
ns
t WCR
Write command hold time referenced
to RAS
120
160
ns
twp
Write command pulse width
55
75
ns
t RWL
Write command to RAS lead time
70
85
ns
tCWL
Write command to CAS lead time
70
85
ns
tos
Data-in set-up time
0
0
ns
15
tOH
Data-in hold time
55
75
ns
15
tOHR
Data-in hold time referenced to RAS
120
160
ns
tcp
CAS precharge time (for page-mode
cycle only)
80
100
ns
tREF
Refresh period
twcs
WRITE command set-up time
0
0
ns
16
t cwo
CAS to WRITE delay
80
90
ns
16
t RWD
RAS to WRITE delay
145
175
ns
16
2
MAX
UNITS
2
NOTES
!
ms
NOTES
6. Several cycles are required after power-up before proper device operation is
achieved. Any 8 cycles which perform refresh are adequate forthis purpose.
7. AC measurements assume tr = 5ns.
8. VIHC (min) or VlH (max) are reference levels for measuring timing of input
signals. Also, transition times are measured between VlHC or VIH and VIL'
9. The specifications fortRC (min)tRMW(minj andtRWC (min) are u.sed only to
indicate cycle time at which proper operation over the full temperature
range (-55°C::; Tc::; 110°C) is assured.
10. Assumes that tReD S tRCD (max). If tReD is grater than the maximum
recommended value shown in this table, tRAC will increase by the amount
that tRCD exceeds the value shown.
11. Assumes that tRCD 2' tRCD (max).
12. Measured with a load equivalent to 2 TIL loads and 100pF.
13. tOFF (max) defines the time at which the output achieves the open circuit
condition and is not referenced to output voltage levels.
14. Operation within the tRCD (max) limit insures that tRAC (max) can be met.
tRCD (max) is specified as a reference point only; if tRCD is greater than the
specified tRCD (max) limit, then access time is controlled exclusively ty
tCAC·
15 These parameters are referenced to CAS leading edge in early write cycles
and to WRITE leading edge in delayed write or read-modify-write cycles.
16. twcs, tCWD and tRWD are restrictive operating parameters in read-write
and read-modify-write cycles only. If twcs ::; twcs (min), the cycle is an
early write cycle and the data out pin will remain open circuit (high
impedance) throughout the entire cycle.lftcWD::; tCWD (min) and tRWD::;
tRWD (min), the cycle is a read-write cycle and the data out will contain data
read from the selected cell. If neither of the above sets of conditions is
satisfied the condition of the data out (at access time) is indeterminate.
17. Effective capacitance calculated from the equation C - 16.tl 6. V with 6. V - 3
volts and'power supplies at nominal levels.
18. CAS
= VHK to disable Dour.
AC ELECTRICAL CHARACTERISTICS
(-55°C:O: TC:O: 11 O°C)(V DO
='
SYM
PARAMETER
CI1
12.0V ± 10%; VSS
='
OV; -5.5V:O: VBB:O: -4.5)
TYP
MAX
UNITS
NOTES
Input Capacitance (Ao - A 6 ), DIN
8
10
pF
17
C!2
Input Capacitance RAS, CAS
8
10
pF
17
Co
Output Capacitance (D OUT )
10
14
pF
17,18
CI3
Input Capacitance WRITE
16
20
pF
17
XII-62
MKB4116 CHIP CARRIER PROCESSING
(MIL-STD-883, Class B)
PROCESS STEP
CONDITION
Method 2010 Condition B
100%
Preseal Inspect
Method 2010 Condition B
100%
24 hrs., 150°C
100%
Temp Cycle
-65/ + 150°C, 10 cycles
100%
Centrifuge
30 Kg, Y,
5 x 10-8 cc/sec
100%
Stabilization Bake
Fine Leak
Gross Leak
100%
Method 1014, Condition C
100%
Pre-Stress Electrical Test 1
Max Rated Temperature
100%
Voltage/Temp Stress
12 hr., +125°C, Dynamic
100%
Post Stress Electrical Test 2
Max Rated Temperature
100%
160 hr., +125°C, Dynamic
100%
Max. Rated Temperature
100%
100%
Burn-in
Final Electrical Tests 3, 4
Min. Rated Temperature
Q.A. Lot Acceptance
Method 5005.5, Group A, Class B
Fine Leak Sample
Gross Leak Sample
External Visual
[QJ
LIMITS
Die Inspect
5 x 10-8 cc/sec
AQL'= .4%
Method 1014, Condition C
AQL'= .4%
100%
Q.C. Final Inspect
AQL'= 2.5%
Q.C. Pre-Shipment Inspect
AQL'= 1.0%
'= Quality Control Check
MKM4332D D PACKAGE (MOTHERBOARD) PROCESSING
PROCESS STEP
CONDITION
LIMITS
Motherboard Assembly
Visual Inspection
100%
Electrical Test
Max. Rated Temp.
Visual Inspection
100%
o
Fine Leak Sample
o
Gross Leak Sample
Method 1014, Condition C
Group A Electrical
Lot Acceptance
Method 5005.5, Group A,
Subgroups 2, 5, 8 Max, 10
Q
5 x 10-8 cc/sec
QC Final Inspection
[QJ
100%
AQL'= .4%
AQL'= 2.5%
'= Quality Control Check
DESCRIPTION (Continued)
designed to provide wide operating margins, both internally
and to the system user.
The technology used to fabricate the MKM4332 is Mostek's
double-poly, N-channel silicon gate, POLY IITM process. This
process, coupled with the use of a single transistor dynamic
storage cell, provides the maximum possible circuit density
and reliability, while maintaining high performance
capability. The use of dynamic circuitry throughout,
including sense amplifiers, assures that power dissipation
is minimized without any sacrifice in speed or operating
XII-63
margin. These factors combine to make the MKM4332 a
truly superior RAM product.
Multiplexed address inputs (a feature pioneered by Mostek
for its 4K RAMs) permits the MKM4332to be packaged in a
standard 18-pin DIP. This standard package configuration,
is compatible with widely available automated testing and
insertion equipment, and it provides the highest possible
system bit densities and simplifies system upgrade from
16K to 64K RAMs for new generation applications. Noncritical clock timing requirements allow use of the multiplexing technique while maintaining high performance.
XII-64
I!I
UNITED
MILITARY
HIGH-REL
PRODUCTS
TECHNOLOGIES
MOSTEK
PROCESSED TO MIL-STD-883, METHOD 500~J
CLASS B, 16,384 x 1 BIT-DYNAMIC RAIVI
MKB4516(P/J/E) - 80/81/82
FEATURES
o
Military temperature range: -55°C:5 TC:5 +11O°C
o
Recognized industry standard 16-pin configuration from
Mostek
o
Single +5 V (± 10%) supply operation
o
On chip substrate
performance
o
bias
generator
for
o Read, Write, Read-Write, Read-Modify-Write and PageMode capability
o
All inputs TIL compatible, low capacitance, and are
protected against static charge
o
Scaled POLY 5 technology
optimum
o Pin compatible with the MKB4564 (64K RAM)
lOOns access time, 235 ns cycle time (MKB4516-80)
120 ns access time, 270 ns cycle time (MKB4516-81)
150 ns access time, 320 ns cycle time (MKB4516-82)
o
128 refresh cycles (2 msec)
o
Available to the DESC part number 8101501 EX
o
Common I/O capability using "early write"
o Indefinite DOUT hold using CAS control
o
Interchangeable with M2118
DESCRIPTION
The MKB4516 is a single +5 V power supply version ofthe
industry standard MKB4116, 16,384 x 1 bit dynamic RAM.
The high performance features of the MKB4516 are
achieved by state-of-the-art circuit device techniques as
well as utilization of Mostek's "Scaled POLY 5" process
technology. Features include access times starting where
the current generation 16K RAMs leave off, TIL compatibility, and +5 V operation.
The small memory user need no longer pay a three power
supply penalty for achieving the economics of using
dynamic RAM over static RAM with this new generation
device.
PIN OUT
Figure 1
P/J
E
PACKAGE
PACKAGE
I
16 Vss
15 CAS
The MKB4516 is capable of a variety of operations including
READ, WRITE, READ-WRITE, READ-MODIFY-WRITE,
PAGE MODE, and REFRESH. The output of the MKB4516
can be held valid indefinitely by holding CAS active low. This
is quite useful since a refresh cycle can be performed while
holding data valid from a previous cycle.
WRITE ~J 3
14 DOUT
13A.
12 A3
11 A4
10 As
N/C
I
I
1.,.1
I
I
1~
I
,
17 ,.._
16L_ DOUT
RAS ~J4
15C As
=J5
(TOPVIEW)14C N/C
Ao :J6
A2 =J78
n
9 N/C
The MKB4516 is designed to be compatible with JEDEC
standards for the 64K x 1 dynamic RAM. It is intended to
extend the life cycle ofthe 16K RAM, as well as create new
applications due to its superior performance. Compatibility
with the MKB4564 will also permit a common board design
to service both the MKB4516 and the MKB4564 (64K RAM)
designs. The MKB4516 will therefore permit a smoother
transition to the 64K RAM as the industry standard
MKB4027 did forthe MKB4116.
lot
I
I
PIN FUNCTIONS
XII-65
Ac - A6
CAS
D'N
Dour
NC
Address Inputs
Col. Address Strobe
Data In
Data Out
Not Connected
RAS
Row Address Strobe
ViiRiTE ReadlWrite Input
RFSH Refresh
vee
Power (+5 V)
vss
GND
ABSOLUTE MAXIMUM RATINGS*
Voltage on Vec Supply Relative to Vss .......................................................• -2.0 V to +7.0 V
Operating Temperature, Tc (Case) ..............................................•.•........... -55°C to +11 O°C
Storage Temperature .•.......••......................................................•..... ~65°C to +150°C
Power Dissipation ............•...•.......•..............................•......................•..• 1 Watt
Short Circuit Output Current ...•.....•..........•..........................................•......•.. 50 mA
*Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions ,above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
(-55°C:::; Tc:::; 110°C)
SYM
PARAMETER
MIN
TYP
MAX
UNITS
NOTES
Vcc
Supply Voltage
4.5
5.0
5.5
V
2
V IH
Input High (Logic 1) Voltage,
All Inputs
2.4
-
V cc +1
V
2
VIL
Input Low (Logic 0) Voltage, All Inputs
-2.0
-
.8
V
2,17
MAX
UNITS
NOTES
38
mA
3
30
mA
3,18
DC ELECTRICAL CHARACTERISTICS
(-55°C:::; Tc:::; 110°C)
SYM
PARAMETER
lec1
OPERATING CURRENT
Average power supply operating current
(RAS, CAS cycling, t Rc =t RC min.)
MIN
= 110°C)
ICC1
Operating Current (Tc
ICC2
STANDBY CURRENT
Power supply standby current (RAS = CAS = V IH
DOUT = High Impedance)
4
mA
ICC3
RAS ONLY REFRESH CURRENT
Average Power Supply current, refresh mode
(RAS cycling, CAS = V IH; t RC = min.)
32
mA
3
ICC4
PAGE MODE CURRENT
Average power supply current, page mode
operation (RAS = V IL, tRAS tRAS max., CAS
cycling; tpc '= tpc min.)
35
mA
3
=
II(L)
INPUT LEAKAGE
Input leakage current. any input
(0 V :::; VIN :::; +5.5 V, all other
pins not under test = 0 volts
-10
10
p.A
IO(L)
OUTPUT LEAKAGE
Output leakage current (DOUT is disabled,
OV :::;VOUT :::; +5.5 V)
-10
10
p.A
0.4
V
V
V OH
VOL
OUTPUT LEVELS
Output High (Logic 1) voltage (lOUT =-5 mAl
Output Low (Logic 0) voltage (lOUT = 4.2 mA
2.4
XII-66
AC ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATION CONDITIONS (4, 5, 9)
(-55°C:::; Tc:::; 110°C), Vcc = 5.0 V
±
10%
SYMBOL
STD
ALT
PARAMETER
MK4516-80
MIN
MAX
MK4516-81
MIN
MAX
MK4516-82
MIN
MAX
UNITS NOTES
tRELREL t RC
Random read or write cycle time
235
270
320
ns
6
285
320
410
ns
6
125
145
190
ns
6
tRELREL tRMW Read-modify-write cycle time
(RMW)
tRELREL tpc
(PC)
Page mode cycle time
tRELOV tRAC
Access time from RAS
100
120
150
ns
7
tCELOV t CAC
Access time from CAS
55
65
80
ns
8
t CEHOZ tOFF
Output buffer
turn-off delay
0
60
ns
Transition time (rise
and fall)
3
tREHREL tRP
RAS precharge time
110
tRELREH t RAS
RAS pulse width
115
tCELREH t RSH
RAS hold time
70
85
105
ns
tRELCEH tCSH
CAS hold time
100
120
165
ns
tCELCEH tCAS
CAS pulse width
55
10'
65
10'
95
10'
ns
tRELCEL tRCD
RAS to CAS delay time
25
45
25
55
25
70
ns
tREHWX tRRH
Read command hold time
referenced to RAS
0
tAVREL t ASR
Row Address set-up time
0
0
0
ns
tRELAX tRAH
Row Address hold time
15
15
15
ns
tAVCEL t ASC
Column Address set-up time
0
0
0
ns
tCELAX tCAH
Column Address hold time
15
15
20
ns
tRELA(C) tAR
Column Address hold time
referenced to RAS
60
70
90
ns
tWHCEL tRCS
Read command set-up time
0
0
0
ns
tCEHWX t RCH
Read command hold time
referenced to CAS
0
0
0
ns
tCELWX tWCH Write command hold time
25
30
45
ns
tRELWX t WCR
Write command hold time
referenced to RAS
70
85
115
ns
Write command pulse width
25
30
50
ns
tWLREH t RWL
Write command to RAS lead time
60
65
110
ns
tWLCEH tCWL
Write command to CAS lead time
45
50
100
ns
tT
tH
tT
twp
45
0
50
0
9
50
3
50
140
0
50
135
120
10'
3
10'
175
0
ns
5
ns
10'
ns
10
ns
11
XII-67
11
AC ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS (Continued)
SYMBOL
STD
ALT
PARAMETER
MK4516-10
MIN
MAX
MK4516-12
MIN
MAX
MK4516-15
MIN
MAX
UNITS NOTES
tOVCEL
tos
Data-in set-up time
0
0
0
ns
12
tCELOX
tOH
Data-in hold time
25
30
45
ns
12
tRELOX
tOHR
Data-in hold time referenced to
RAS
70
85
115
ns
tCEHCEL
(PC)
tcp
CAS precharge time
(for page mode cycle only)
60
70
85
ns
t RVRV
tREF
Refresh period
tWLCEL
twcs
WRITE command set-up time
0
0
0
ns
13
tCELWL
t cwo
CAS to WRITE delay
55
65
80
ns
13
tRELWL
t RWO
RAS to WRITE delay
100
120
150
ns
13
tCEHREL
t CRP
CAS to RAS precharge time
0
0
0
ns
2
2
2
ms
OUTPUT LOAD
AC TEST CONDITIONS
Input Levels .....••.............•.•......•.......0 V to 3.0 V
Transition times .....•...•.....•.......................• 5 ns
Input timing reference level •.•.••..........••....•... .1.5 V
Output timing reference levels ............... 0.8 V - 2.0 V
Output load .....................•.........•.......See figure
5V
4800
50 pf
2550
(including
:~ scope and
jig capacitance
XII-68
CAPACITANCE
(-55°C::; Tc ::; 11 O°C) (Vee = 5.0 V
± 10%)
SYMBOL
PARAMETER
MAX
C11
Input (Ao - A 5 ), DIN
4
5
pF
15
C12
Input RAS, CAS, WRITE
8
10
pF
15
Co
Output (D OUT )
5
7
pF
15,16
TYP
NOTES:
UNITS
NOTES
specified tRCD (max) limit. then access time is controlled exclusively by
1. No user connection to Pin 1 (Leadless Chip Carrier only), This pin must be left
tCAC'
11. Either tRRH or tRCH must be satisfied for a read cycle.
12. These parameters are referenced to CAS leading edge in early write cycles
and to WRITE leading edge in delayed write or read-modify-write.
13. twcs, tCWD' and tRWD are restrictive operating parameters in
READ/WRITE and READ/MODIFY/WRITE cycles only. If twcs ? twcs
(min) the cycle is an EARLY WRITE cycle and the data output will remain
open circuit throughout the entire cycle.lftcWD ~tCWD (min) and tRWD?
tRWD (min)the cycle is a READ/WRITE and the data output will contain data
read from the selected cell. If neither of the above conditions are met the
condition of the data out (at access time and until CAS goes back to VIH) is
indeterminate.
14. The transition time specification applies for all input signals. In addition to
meeting the transition rate specification, all input signals must transmit
between VIH and Vil (or between Vil and VIH) in a monotonic manner.
15. Effective capacitance calculated from the equation c= I ~with t::..V = 3 volts
b.V
and power supply at nominal level. This parameter is sample tested only.
16. CAS = VIH DOUT.
17. Includes the de level and all instantaneous signal excursions.
18. Power consumption decreases with increasing temperature.
floating.
2. All voltages referenced to VSS.
3.ICC is dependent on output loading and cycle rates. Specified values are
obtained with the output open.'
4. An initial pause of 500 f.!.s is required after power~up followed' by any 8 RAS
cycles before proper device operation is achieved. RAS may be cycled during
the initial pause.
5. VIH min. and VIL max are reference levels for measuring timing of Input
signals. Transition times are measured between V,H and V,L.
6. The minimum specifications are used only to indicate cycle time at which
proper operation over the full temperature range (-55°C::; TC::; +11 QOC) is
assigned.
7. Assumes that tRCD ::; tRCD (max). If tRCD is greater than the maximum
recommended value shown in this table, tRAC will increase by the amount
that tRCD exceeds the value shown
8. Assumes that tRCD? tRCD Imax}.
9. tOFF max defines the time at which the output achieves the open circuit
condition and is not referenced toVOH or VOL.
10. Operation within the tRCD (max) limit insures that tRAC (max) can be met.
tRCD (max) is specified as a reference point only; if tRCD is greater than the
READ CYCLE
Figure 2
I
RC
tRAS
RAS
-tAR
V ,H
V IL
IT
tRCD
..
tCSH
t RSH
tCAS
V ,H
CAS
V IL
ADDRESSES
V ,H
V IL
WRITE
V ,H
V IL
LtCAC----l~
~----------------tRAC---------------.,
V OH
OPEN
DOUT
VOL
XII-69
VALID
DATA
WRITE CYCLE
t RC
Figure 3
t RAS
V ,H
RAS
-I
tAR
V'L
tC~H
t ASH
teAs
V ,H
CAS
V'L
V ,H
ADDRESSES
V'L
WRITE
V ,H
V'L
~-----tDHR-----+t
V OH
VOL
------------------------------------OPEN -----------------------------
READ-WRITE/READ-MODIFY-WRITE CYCLE
Figure 4
~----tAR------~~
CAS
V ,H
V'L
ADDRESSES
V ,H
V'L
V OH
D'N
VOL
V ,H
DOUT
V'L
XII-70
"RAS-ONLY" REFRESH CYCLE
NOTE: CAS
= V 1H WRITE = DON'T CARE
Figure 5
ADDRESSES
DOUT
V OH - - - - - - - - - OPEN
VOl
PAGE MODE READ CYCLE
Figure 6
XII-71
- - - - - - - - -
PAGE MODE WRITE CYCLE
Figure 7
RAS
V'H
V'l
CAS
V'H
V'l
ADDRESSES
V'H
V'l
WRITE
V'H
V'l
D'N
V'H
V'l
OPERATION
lengthed by the amount that t RCD exceeds the t RCD (max)
limit.
The 14 address bits required to decode 1 of the 16,384 cell
locations within the MKB4516 are multiplexed onto the 7
address inputs and latched into the on-chip address latches
by externally applying two negative going TIL-level clocks.
The first clock, Row Address Strobe (RAS), latches the 7 row
addresses into the chip. The high-to-Iow transition of the
second clock, Column Address Strobe (CAS), subsequently
latches the 7 column addresses into the chip. Each ofthese
signals, RAS and CAS, triggers a sequence of events which
are controlled by different delayed internal clocks. The two
clock chains are linked together logically in such a way that
the address multiplexing operation is done outside of the
critical timing path for read data access. The later events in
the CAS clock sequence are inhibited until the occurence of
a delayed signal derived from the RAS clock chain. This
"gated CAS" feature allows the CAS clock to be externally
activated as soon as the Row Address Hold specification
(t RAH ) has been satisfied and the address inputs have been
changed from Row address to Column address information.
The "gated CAS" feature permits CAS to be acitvated at any
time after tRAH and it will have no effect on the worst case
data access time (tRAd up to the point in time when the
delayed row clock no longer inhibits the remaining
sequence of column clocks. Two timing endpoints result
from the internal gating of CAS which are called t RCD (min)
a~CD (max). No data storage or reading errors will result
if CAS is applied to the MKB4516 at a point in time beyond
the t RCD (max) limit. However, access time will then be
determined exclusively by the accesss time from CAS (tcAd
rather than from RAS (t RAC ). and RAS access time will be
Data Input/Output
Data to be written into a selected cell is latched into an
on-chip register by a combination of WRITE and CAS while
RAS is active. The latter of WRITE or CAS to make its
negative transition is the strobe for the Data In (DIN) register.
This permits several options in the write cycle timing. In a
write cycle, if the WRITE input is brought low (active) prior to
CAS being brought low (active), the DIN is strobed by CAS,
and the Input Data set-up and hold times are referenced to
CAS. Ifthe input data is not available at CAS time (late write),
or if it is desired that the cycle be a read-write or readmodify-write cycle the WRITE signal should be delayed until
after CAS has made its negative transition. In this "delayed
write cycle" the data input is set-up and hold times are
referenced to the negative edge of WRITE rather than CAS.
Data is retrieved from the memory in a read cycle by
maintaining WRITE in the inactive or high state throughout
the portion of the memory cycle in which both the RAS and
CAS are low (active). Data read from the selected cell is
available at the output port within the specified access time.
The output data is the same polarity (not inverted) as the
input data.
Data Output Control
The normal condition of the Data Output (D OUT ) of the
MK4516 is the high impedance (open circuit) state;
anytime CAS is high (inactive) the DOUT pin will be floating.
XII-72
Once the output data port has gone active, it wil remain
valid until CAS is taken to the precharge (inactive high)
state.
Page Mode Operation
The Page Mode feature of the MKB4516 allows for
successive memory operations at multiple column locations
within the same row address. This is done by strobing the
row address into the chip and maintaining the RAS signal
low (active) throughout all successive memory cycles in
which the row address is common. The first success within
a page mode operation will be available attRAc or t cAc time,
whichever is the limiting parameter. However, all
successive accesses within the page mode operation will be
available at t CAC time (referenced to CAS). With the
MKB4516, this results in as much as a 45% improvement in
access times! Effective memory cycle times are also
reduced when using page mode.
The page mode boundary of a single MKB4516 is limited to
the 128 column locations determined by all combinations of
the seven column address bits. Operations within the page
mode boundary need not be sequentially addressed and any
combination of read-write and read-modify-write cycle are
permitted within the page mode operation.
Refresh
Refresh of the dynamic cell matrix is accomplished by
performing a memory cycle at all 128 combinations of the
seven row address bits within each 2 ms interval. Although
any normal memory cycle will perform the required
refreshing, this function is most easily accomplished with
"RAS-only" cycles.
III
XII-73
XII-74
~ TECHNOLOGIES
UNITED
MILITARY
HIGH-REL
PRODUCTS
MOSTEK
131,072 x 1-BIT DYNAMIC RAM
MKM4528(D) - 83/84
FEATURES
o Utilizes two standard MKB4564E devices in an 18-pin
dual in-line package configuration
o
Separate RAS, CAS Clocks
o Read, Write, Read-Write, Read-Modify-Write and PageMode capability
o -55°C to +110°C case operating temperature range
o Single +5 V (± 10",6) supply operation
o MKM Module electrically tested at maximum tempperature following assembly
o Each MKB4564E Leadless Chip Carrier fully processed
and burned in to MIL-STD-883 Method 5004 Class B
o Active power 325mW (Single MKB4564E active)
Standby power 55mW
o Scaled POLY 5 technology
o 128 refresh cycles (2 msec) for each MKB4564 device in
the dual density configuration (addressA7 is not used for
refresh)
o 200ns access time, 345ns cycle time MKM4528D-83
250ns access time, 425ns cycle time MKM4528D-84
o Indefinite DOUT hold using CAS control and unlatched at
end of cycle to allow two dimensional chip selection and
extended page boundary
o Common 1/0 capability using "early write"
DESCRIPTION
The MKM4528 sets a new milestone in the state of the art
in package technology to give you dual density now before
the next generation of MOS RAMs are available. This device
is made up of two 64K (MKB4564E) 5 volt only RAMs and it
is organized as 131 ,072 by 1 bit.
The high performance features of the MKM4528 are
achieved by state-of-the-art circuit design techniques as
well as utilization of Mostek's "Scaled POLY 5" process
technology. Features include access times starting where
the current generation 16K RAMs leave off, plus
compatibility with the 128 refresh cycles of th.e previous
generation.
PIN CONNECTIONS
DEVICE PROFILE
NC 1
DIN 2
18 Vss
17 CAS 1
WRITE 3
16 DoUT
RAS 14
15 As
14 A3
13 A4
Ao 5
A2 6
A,7
vee 8
RAS29
PIN FUNCITONS
Ao- A7 Address Inputs
Column Address Strobe
CAS
Data In
DIN
Data Out
DOUT
GND
VSS
II
12 A5
11 Po,
10 CAS 2
RAS
WRITE
VCC
NC
Row Address Strobe
ReadlWrite Input
Power (+5 V)
No Connect
XII-75
The completed MKM module is composed of individually
processed and burned in devices which are then reflow
soldered onto a cofired ceramic substrate. This inherently
reliable assembly is then visually and electrically tested to
confirm its quality.
The MKM4528 is capable of a variety of operations
including READ, WRITE, READ-WRITE, READ-MODIFYWRITE, PAGE MODE, and REFRESH. The output of the
MKM4528 can be held valid indefinitely by holding CAS
active low. This is quite useful since a refresh cycle can be
performed while holding data valid from a previous cycle.
Multiplexed address inputs (a feature pioneered by Mostek
for its 4K RAMs) permits the MKM4528 to be packaged in a
standard 18-pin DIP. This standard package configuration,
is compatible with widely available automated testing and
insertion equipment, and it provides the highest possible
system bit densities. Non-critical clocktiming requirements
allow use of the multiplexing technique while maintaining
high performance. Device selection occurs through RAS
decoding in the same manner as if the devices were
independently placed in a memory matrix.
XII-76
B
UNITED
MILITARY
HIGH-REL
PRODUCTS
TECHNOLOGIES
MOSTEK
PROCESSED TO MIL-STD-883,t METHOD 5~"
CLASS 8, 65,536 x 1-811 DYNAMIC RAlvl
MK84564 (P/E) - 82/83/84
FEATURES
D
Military temperature range: -55°C ::5 TC ::5 +11 O°C
D Low power: 300 mW active, max
22 mW standby, max
D Dynamic burn in at 125°C for 160 hours
D Extended DOUT hold using CAS control (Hidden Refresh)
D Recognized industry standard 16-pin configuration from
D Common 1/0 capability using "early write"
Mostek
D Read, Write, Read-Write, Read-Modify-Write and Page
D Single +5 V (± 10%) supply operation
Mode capability
D On
chip substrate
performance
bias
generator for
optimum
D All
inputs TTL compatible, low capacitance, and
protected against static charge
D Typical ordering information
D Scaled POLY 5™ technology
MKB4564P-82 150 ns t RAC
MKB4564P-83 200 ns t RAC
MKB4564P-84 250 ns t RAC
D 128 refresh cycles (2 msec)
Pin 9 is not needed for refresh
DESCRIPTION
The MKB4564 is the new generation dynamic RAM.
Organized 65,536 words by 1 bit, it is the successor to the
industry standard MKB4116. The MKB4564 utilizes
Mostek's scaled POLY 5 process technology as well as
advanced circuit techniques to provide wide operating
margins, both internally and to the system user. The use of
dynamic circuitry throughout, including the 512 sense
amplifiers, assures that power dissipation is minimized
without any sacrifice in speed or internal and external
operating margins. Refresh characteristics have been
chosen to maximize yield (low cost to user) while
maintaining compatibility between dynamic RAM generations.
Multiplexed address inputs (a feature dating back to the
industry standard MK4096, 1973) permit the MKB4564 to
be packaged in a standard 16-pin DIP with only 15 pins
required for basic functionality. The MKB4564 is designed
to be compatible with the JEDEC standards for the 64K x 1
dynamic RAM.
The output ofthe MKB4564 can be held valid up to 10 p'sec
by holding CAS active low. This is quite useful since refresh
cycles can be performed while holding data valid from a
previous cycle. This feature is referred to as Hidden Refresh.
The 64K RAM from Mostek is the culmination of several
years. of circuit and process development, proven in
predecessor products.
PIN OUT
Figure 1
DUAL-IN-LiNE
PACKAGE
N/C 1
16 Vss
15 CAs (EEl
DIN (D) 2
WRiTE(W)
3
14 DOUTIQ)
RAsiRE)
Ao
4
13 As
5[
12 As
A, 6
A,7
LEADLESS CHIP CARRIER
RAs (RE)
N/C
~J
['=4 N/C
AO
~J
[1}
A2
?J
[~2 A4
l' A4
10 As
9 A7
Vee 8
~~j l~j t'.8j ~?l
J
~J
WRITE [W)
~
[1}
OOUT [01
[f~
A6
A3
PIN FUNCTIONS
Table 1
Address Inputs
CAS (CE)
DOUT (Q)
XII-77
RAS (RE) Row Address Strobe
(W) ReadIWrite Input
Column Address
Strobe
WRITE
Vee
Power (5 V)
Data In
Vss
GND
Data Out
N/C
Not Connected
ABSOLUTE MAXIMUM RATINGS*
Voltage on V cc supply relative to V 55 . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . • . . . . . . . . . . . . . . . . . . . . . .. 1.0 V to +7.0 V
Operating Temperature Tc (case) ...............................•. '" ..........•........•..... -55°C to +110°C
Storage Temperature ...............•....................................................... -65°C to +150°C
Power Dissipation ..........................•..........................................•............ 1 Watt
Short Circuit Output Current ................•.................•.....••............................... 50mA
*Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
(-55°C:::; Tc :::; +11O°C)
SYM
PARAMETER
MIN
TYP
MAX
UNITS
NOTES
VCC
Supply Voltage
4.5
5.0
5.5
V
1
V
1
V IH
Input High (Logic 1) Voltage,
All Inputs
2.4
-
Vcc
V IL
Input Low (Logic 0)
Voltage, All inputs
-2.0
-
.8
V
1,16
MIN
MAX
UNITS
NOTES
60.0
mA
2
45
mA
2,18
5
mA
+1
DC ELECTRICAL CHARACTERISTICS
(-55°C :::;Tc:::; +110°C) (Vcc = 5.0 V ± 10%)
SYM
PARAMETER
ICCl
OPERATING CURRENT
Average power supply operating current
(RAS, CAS cycling; t RC = t RC min.)
ICCl
OPERATING CURRENT (Tc = +110°C)
ICC2
STANDBY CURRENT
Power supply standby current (RAS = V IH,
DOUT = High Impedance)
ICC3
RAS ONLY REFRESH CURRENT
Average power supply current, refresh mode
(RAS cycling, CAS = V IH ; t RC = t RC min.)
45
mA
2
ICC4
PAGE MODE CURRENT
Average power supply current, page mode
operation (RAS = V IL ' t RA5 =tRA5 max., CAS
cycling; tpc = tpc min.)
35
mA
2
II(L)
INPUT LEAKAGE
Input leakage current, any input
(0 V :::; VIN :::; V cc), all other pins not under
test=OV
-10
10
/J.A
IO(L)
OUTPUT LEAKAGE
Output leakage current (DOUT is disabled,
OV:::;VouT:::;Vcd
-10
10
iJ.A
0.4
V
V
VOH
VOL
OUTPUT LEVELS
Output High (Logic 1) voltage (lOUT = -5 mA
Output Low (Logic 0) voltage (lOUT = 4.2 mAl
XII-78
2.4
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (3,4,5,15)
(-55°C S:Tc s: 110°C), VCC
SYMBOL
STD
ALT
= 5.0 V ± 10%
PARAMETER
MK4564-15
MIN MAX
MK4564-20
MIN MAX
MK4564-25
MIN MAX UNITS NOTES
tRELREL
t RC
Random read or write cycle time
260
345
425
ns
6,7
tRELREL
(RMW)
tRMW
Read-modify-write cycle time
310
405
490
ns
6,7
tRELREL
(PC)
tpc
Page mode cycle time
155
200
240
ns
6,7
tRELQV
t RAC
Access time from RAS
150
200
250
ns
7,8
tCELQV
t CAC
Access time from CAS
85
115
145
ns
7,9
t CEHOZ
tOFF
Output buffer turn-off delay
0
40
0
50
0
60
ns
10
tT
tT
Transition time (rise and fall)
3
50
3
50
3
50
ns
5,15
tREHREL
t RP
RAS precharge time
100
tRELREH
tRAS
RAS pulse width
150
tCELREH
t RSH
RAS hold time
85
115
145
ns
tRELCEH
tCSH
CAS hold time
150
200
250
ns
tCELCEH
tCAS
CAS pulse width
85
10,000
115
10,000
145
10,000
ns
tRELCEL
t RCD
RAS to CAS delay time
30
65
35
85
45
105
ns
11
tREHWX
tRRH
Read command hold time
referenced to RAS
20
25
30
ns
12
135
10,000
200
165
10,000
250
ns
10,000
ns
tAVREL
t ASR
Row address set-up time
0
0
0
ns
tRELAX
tRAH
Row address hold time
20
25
30
ns
tAvCEL
tASC
Column address set-up time
0
0
0
ns
tCELAX
tCAH
Column address hold time
30
40
50
ns
tRELA(C)X
tAR
Column address hold time
referenced to RAS
100
130
160
ns
tCELWX
t RCH
Read command hold time
referenced to CAS
0
0
0
ns
tCELWX
tWCH
Write command hold time
45
55
70
ns
tRELWX
tWCR
Write command hold time
referenced to RAS
115
150
185
ns
twLWH
twp
Write command pulse width
35
45
55
ns
tWLREH
t RWL
Write command to RAS lead time
45
55
65
ns
twLCEH
tcwL
Write command to CAS lead time
45
55
65
ns
XII-79
12
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (3,4,5,15,)
(-55°C::; TC::; 110°C), VCC = 5.0 V ± 10%
SYMBOL
STD
ALT
PARAMETER
MK4564-15
MIN
MAX
MK4564-20
MIN
MAX
MK4564-25
MIN
MAX UNITS NOTES
0
0
0
ns
13
Data-in hold time
45
55
70
ns
13
Data-in hold time
referenced to RAS
115
150
190
ns
CAS precharge time
(for page-mode cycle only)
60
75
85
ns
tOVCEL
tos
Data-in set-up time
tCELOX
tOH
tRELOX
tOHR
tCEHCEL
(PC)
tcp
t RVRV
tREF
Refresh period
WLCEL
twcs
WRITE command set-up time
-10
-10
-10
ns
14
tCELWL
tcwo
CAS to WRITE delay
55
80
100
ns
14
tRELWL
t RWO
RAS to WRITE delay
120
165
205
ns
14
tcEHCEL
t CPN
CAS precharge time
30
35
45
ns
2
2
2
ms
AC ELECTRICAL CHARACTERISTICS
(-55°C::; TC ::; 110°C) = 5.0 V ± 10%
MAX UNITS NOTES
SYM
PARAMETER
Cil
Input Capacitance (Ao - A 7 ), DIN
5
pF
14
CI2
Input Capacitance RAS, CAS, WRITE
10
pF
14
Co
Output Capacitance (Dour)
7
pF
14
NorEs:
1 . All voltages referenced to V ss.
2.ICC is dependent on output loading and cycle rates. Specified values are
obtained with the output open.
3. An initial pause of 500 j.l.S is required after power-up followed by any 8 Fi'AS
cycles before proper device operation is achieved. Note that i=fA§' may be
cycled during the initial pause.
4. VIH min. and VIL max. are reference levels for measuring timing of input
Signals. Transition times are measured between VIH and VIL'
5. The minimum specifications are used only to indicate cycle time at which
proper operation over the full temperature range (-55°C:5 Tc:::; 110°C) is
assured.
6. Assumes that tRCD :s; tRCD (maxi. If tRCD is greater than the maximum
recommended value shown in this table. tRAC will increase by the amount
that tRCo exceeds the value shown.
7. Assumes that tRCD 2: tRCD (maxi.
S. tOFF max. defines the time at which the output achieves the open circuit
condition and is not referenced to VOH or VOL.
9. Operation within the tRCo (max.) limit insures that tRAC (max.) can be met.
tRCo(max.) is specified as a reference point only; iftRCD is greater than the.
specified tRCo limit. then access time is controlled exclusively by tCAC'
10. Either tRRH or tRCH must be satisfied for a read cycle.
11 These parameters are referenced to CAS leading edge in early write cycles
and to WRITE leading edge in delayed or read-modify-write cycles.
12. twCS. tCWD. andtRWD are restrictive operating parameters in REAO/WRITE
and READ/MODIFY !WRITE cycles only. If twcs 2: twcs Iminl the cycle is
an EARLY WRITE cycle and the data output will remain open circuit
throughout the entire cycle.lftcWD;=: tcwO(min) and tRWo;=: tRWO (min)
the cycle is a READ/WRITE and the data output will contain data read from
the selected cell. If neither of the above conditions are met the condition of
the data out (at access time and until CAS goes back to VIH) is indeterminate.
13.ln addition to meeting the transition rate specification. all input Signals must
transmit between VIH and VIL (or between VIL and VI H) in a monotonic
manner.
14. Effective capacitance calculated from the equation C =Iill, with t::. V = 3 volts
t:N
and power supply is at nominal level. This parameter is sample tested only.
15. CAS = VIH to disable DOUT·
16. Includes the DC level and all instantaneous signals excursions.
17. WRITE = don·tcare. Data out depends on the state of eAS. If CAS = VIH. data
output is high impedance. If ~ = VIL. the data output will contain data
from the last valid read cycle.
18. Power consumption decreases with increasing temperature.
XII-80
AC TEST CONDITIONS
OUTPUT LOAD
Table 2
Figure 2
Input Levels .............................. 0 to 3.0 V
Transistion Times ............................... 5 ns
Input timing reference levels .................... 1.5 V
Output timing reference levels ............ 0.8 V - 2.0 V
Output Load .............................. See figure
5V
48011
DOUT-----1~----------_.
25511
50pF
-=
(INCLUDING
SCOPE AND
JIG CAPACITANCE)
READ CYCLE
Figure 4
~-------------------tRC------------------~
t----------------- t RAs ------~~
V ,H _ ------------,...:....------_--.... f<_---I--t._.o------t~
V
r+,..-----------------"
,l -
ADDRESSES V,H V,l -
WRITE
V ,H _
V'l -
k-t
t
CAC
RAC
DOUT
VOL V OH -
OPEN
XII-a1
VALID
DATA
WRITE CYCLE (EARLY WRITE)
Figure 5
V IH _
RAS
Vil -
V IH _
CAS
Vil -
ADDRESSES
V IH Vil -
V IH _
WRITE
Vil -
V IH _
DIN
Vil tOHR
DOUT
VOL V OH -
OPEN
PAGE MODE READ CYCLE
Figure 6
RAS
Vil -
V IH _
CAS
Vil -
V IH
ADDRESSES
Vil
DOUT
ValV OH -
WAITE
V IH ""
Vil
I
OPEN
L
XII-82
PAGE MODE WRITE CYCLE
Figure 7
~------------------------tRAS------------------------~
V IH
_----'--:-------.Ib..
VIL -
V
ADDRESSES V IH
IL
VIH -Z;~~?t;~.Ir_v:I\iii"".,
11\"'~"""".,,.~",,""q~lfJl
,--'-=:..:::...__::r"GGGGGGGGG~
VIL
READ-WRITE/READ-MODIFY-WRITE CYCLE
FigureS
~---------------------------~MW---------------------~
V IH _
---....,.,f----------..t--..
VIL -
ADDRESSES
WRITE
V IH _
V IL -
V OH _
Dour
L
V OL -
t RAC
V IH _
DIN
VIL -
XII-83
II
"RAS-ONLY" REFRESH CYCLE
Figure 9
t RC
t RAS
t
ADDRESSES
A
~
t RP
~_AS_R_A-D"""~'""~""'':'''''S-S~
- tRAH
I
I
i+-
OPERATION
The eight address bits required to decode 1 of the 65,536
cell locations within the MKB4564 are multiplexed onto the
eight address inputs and latched into the on-chip address
latches by externally applying two negative going TIL-level
clocks. The first clock, Row Address Strobe (RAS), latches
the eight row addresses into the chip. The high-to-Iow
transition of the second clock, Column Address Strobe
(CAS), subsequently latches the eight column addresses
into the chip. Each ofthese signals, RA§ and CAS, triggers a
sequence of events which are controlled by different
delayed internal clocks. The two clock chains are linked
together logically in such a way that the address
multiplexing operation is done outside of the critical timing
path for read data access. The later events in the CAS clock
sequence are inhibited until the occurrence of a delayed
signal derived from theRAS clock chain. This "gated CAS"
feature allows the CAS clock to be externally activated as
soon as the Row Address Hold specificatic;m (tRAH ) has been
satisfied and the address inputs have been changed from
Row address to Column address information.
The" gated CAS" feature permits CAS to be activated at any'
time after tRAH and it will have no effect on the worst case
data access time (tRAcl up to the point in time when the
dalayed row clock no longer inhibits the remaining
sequence of column clocks. Two timing endpoints result
from the internal gating of CAS which are called t RCD (min)
and t RCD (max). No data storage or reading errors will result
if CAS is applied to the MKB4564 at a point in time beyond
the tRCD (max) limit. However, access time will then be
determined exclusively by the access time from CAS (tcAc)
rather than from RAS (tRAC )' and RAS access time will be
lengthened by the amount that t RCD exceeds the tRCD (max)
limit.
DATAINPUT/OUTPUT
Data to be written into a selected cell is latched into an
on-chip register by a combination of WRITE and CAS while
RAS is active. The latter of WRITE or CAS to make its
negative transition is the strobe for the Data In (DIN) register.
This permits several options in the write cycle timing. In a
write cycle, ifthe WRITE input is brought low (active) prior to
CAS being brought low (active), the DIN is strobed by CAS,
and the Input Data set-up and hold times are referenced to
CAS.lfthe input data is not available at CAS time(late write)
or if it is desired that the cycle be a read-write or readmodify-write cycle the WRITE signal should be delayed until
after CAS has made its negative transition. In this "delayed
write cycle" the data input set-up and hold times are
referenced to the negative edge of WRITE rather than CAS.
Data is retrieved from the memory in a read cycle by
maintaining WRITE in the inactive or high state throughout
the portion of the memory cycle in which both the RAS and
CAS are low (active). Data read from the selected cell is
available at the output port within the specified access time.
The output data is the same polarity (not inverted) as the
input data.
DATA OUTPUT CONTROL
The normal condition of the Data Output (D OUT ) of the
MKB4564 is the high impedance (open-circuit) state;
anytime CAS is high (inactive) the DOUT pin will be floating.
Once the output data port has gone active, it will remain
valid until CAS is taken to the precharge (inactive high)
state.
PAGE MODE OPERATION
The Page Mode feature of the MKB4564 allows for the
successive memory operations at multiple column locations
within the same row address. This is done by strobing the
row address into the chip and maintaining the RAS signal
low (active) throughout all successive memory cycles in
which the row address is common. The first access within a
page mode operation will be available at tRAC or t CAC time,
whichever is the limiting parameter. However, all
successive accesses within the page mode operation will be
available at t CAC time (referenced to CAS). With the
MKB4564 this results in approximately a 45% improvement
in access times. Effective memory cycle times are also
reduced when using page mode.
XII-84
The page mode boundary of a single MKB4564 is limited to
the 256 column locations determined by all combinations of
the eight column address bits. Operations within the page
boundary need not be sequentially addressed and any
combination of read. write. and read-modify-write cycles is
permitted within the page mode operation.
REFRESH
Refresh of the dynamic cell matrix is accomplished by
performing a memory cycle at each of the 128 row
addresses within each 2ms interval. Although any normal
memory cycle will perform the required refreshing. this
function is most easily accomplished with "RAS-only"
cycles.
The RAS-only refresh cycle requires that a 7 bit refresh
address (AD-A6) be valid at the device address inputs when
RAS goes low (active). The state of the output data port
during a RAS-only refresh is controlled by CAS. If CAS is
high (inactive) during the entire time that RAS is asserted.
the output will remain in the high impedance state. If CAS is
low (active) the entire time that RAS is asserted. the output
port will remain in the same state that it was prior to the
issuance of the RAS signal. If CAS makes a low-to-high
transition during the RAS-only refresh cycle. the output
data buffer will assume the high impedance state. However.
CAS may not make a high to low transition during the
RAS-only refresh cycle since the device interprets this as a
normal RAS/CAS (read or write) type cycle.
HIDDEN REFRESH
A RAS-only refresh cycle may take place while maintaining
valid output data by extending the CAS active time from a
previous memory read cycle. This feature is referred to as a
hidden refresh. (See figure below.)
HIDDEN REFRESH CYCLE (SEE NOTE 19)
Figure 10
MEMORY
CAS
AOORESSES
R"RESH CY
\~------------~;
~/l//l!EYlIT!I(//l1ll\..
7lllDJ
Dour
en n
v!lTJIIf@J/m/Ul
------~<~----------~>-
£I
XII-85
XII-86
MOSTEI(@
MILITARYIHIGH-REL PRODUCTS
PROCESSED TO MIL-STD 883, METHOD 5004, CLASS B
1024 x 8-Bit Static RAM
MKB4801 A(P I J/E)-870/890/81
-55°C to 125°C operating temperature
FEATURES
D
D Static operation
D High performance
D Organization: 1K x 8 bit RAM JEDEC pinout
Access Time
R/W
Cycle Time
MKB4801 A-870
70 nsec
70/80 nsec
MKB4801 A-890
90 nsec
90/100 nsec
MKB4801A-81
120 nsec
120 nsec
Part No.
Pin compatible with Mostek's BYTEWYDpM memory
family
D
D 24128 pin ROM/PROM compatible pin configuration
D
EE and OE functions facilitate bus control
DESCRIPTION
The MKB4801 A uses Mostek's Scaled POLY 5™ process
and advanced circuit design techniques to package 8,192
bits of static RAM on a single chip. Static operation is
achieved with high performance and low power dissipation
by utilizing Address Activated™ circuit design techniques.
BLOCK DIAGRAM
""'"''''""''"''
Figure 1 ' , , -
The MKB4801 A excels in high speed memory applications
where the organization requires relatively shallow depth
with a wide word format. The MKB4801 A presents the user
a high density cost effective alternative to bipolar and
previous generation N-MOS fast memory.
PIN CONNECTIONS
Figure 2
,,----+I
.. - - - - + I
A7 1
24VCC
A62
A5 3
23Aa
22 A9
A44
21 WE
A35
A26
20 OE
19 NC
An
18
AO 8
17007
128.8.8
MEMORY CELL
000 9
00110
00211
TRUTH TABLE
X
~
VSS12
CE
OE
WE
Mode
DO
V'H
X
X
Deselect
High Z
V'L
X
V'L
Write
D'N
DOUT
High Z
V'L
V'L
V'H
Read
V'L
V'H
V'H
Read
Don't Care
CE
1300 3
:
As __5=
A5
A. ~ ~~
A3
~=8J
A, ~ ~~
Al_~(O~
~J2J ~_lJ ~_oJ
~2~
:
L_ ~
_-~~:
A.
J~~ A.
LEADLESS
CHIP CARRIER
(E PACKAGE)
TOP VIEW
~X NC
C2~(.,WE
[i-'~OE
~2~~ NC
Ao ~(1]
16006 NC :(2J
15005 000 -))J
1400 4
PIN NAMES
&l-A9
Address Inputs
CE
Chip Enable
Vss
Ground
Vcc
Power (+5 V)
XII-87
A7 NC NC NC vccNC NC
L4: ~ 3: L2J :';
(450 mil x 550 mil'
JEDEC type E)
r-'
r - ~ r" -.
r",
[2)~
CE
~2:
DO,
:3=(
DO.
~l!L :,~ ~o.
DQ,DQ, v ssNCDQ30Q. DQ~
:14: ~i~:
Write Enable
Output Enable
No Connection
Data In/Data Out
II
ABSOLUTE MAXIMUM RATINGS*
Voltage on any pin relative to Vss ............................................................ -0.3 V to +7.0 V
Operating Temperature TA (Ambient) ..•....................................•................. -55°C to +125°C
Storage Temperature (Ambient) (Ceramic) ..................................................... -65°C to +150°C
Power Dissipaion .......................•........•...................•....................•...•..... 1 Watt
Output Current .................•................•.......•..•.......•.....•....•........•........... 20 mA
*Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS8
(-55°C :5 TA :5 + 125°C)
SYM
PARAMETER
MIN
TYP
MAX
VCC
Supply Voltage
4.75
5.0
5.25
V
1
VSS
Supply Voltage
0
0
0
V
1
V IH
Logic "1" Voltage All Inputs
2.4
7.0
V
1
V IL
Logic "0" Voltage All Inputs
-0.3
.65
V
1,10
UNITS NOTES
DC ELECTRICAL CHARACTERISTICS1.8
(-55°C :5 TA :5 + 125°C) (Vcc
= 5.0 volts ±5%)
SYM
PARAMETER
MIN
MAX
ICC1
Average Vcc Power Supply Current
120
mA
9
ICC1
Average V cc Power Supply Current
(TA = 125°C)
90
mA
9, 11
IlL
Input Leakage Current (Any Input)
-10
10
pA
2
IOL
Output Leakage Current
-50
50
pA
2
V OH
Output Logic "1" Voltage lOUT = -1 rnA
2.4
VOL
Output Logic "0" Voltage lOUT = 4 mA
V
0.4
XII-SS
UNITS NOTES
V
AC ELECTRICAL CHARACTERISTICS3.•
(-55°C :5 TA :5 125°C) (VCC = 5.0 volts ± 5%)
MKB4801 A-870 MKB4801 A-890 MKB4801A-81
MIN
MIN
MAX
MIN
MAX
MAX
SYM
PARAMETER
t RC
Read Cycle Time
tAA
Address Access Time
70
90
120
ns
5
tCEA
Chip Enable Access Time
35
45
60
ns
5
tcEZ
Chip Enable Data Off Time
30
ns
toEA
Output Enable Access Time
60
ns
toEZ
Output Enable Data Off Time
5
30
ns
tAZ
Address Data Off Time
10
10
10
,ns
WC
Write Cycle Time
80
100
120
ns
tAS
Address Setup Time
0
0
0
ns
see text
tAH
Address Hold Time
20
30
40
ns
see text
tosw
Data To Write Setup Time
5
5
10
ns
tOHW
Data From Write Hold Time
10
10
15
ns
two
Write Pulse Duration
30
40
45
ns
WEZ
Write Enable Data Off Time
WPL
Write Pulse Lead Time
CAPACITANCE,·8
(-55°C :5 TA :5 +125°C) (Vcc
70
5
20
5
30
20
5
15
5
50
30
25
5
5
5
30
75
60
NOTES
ns
45
35
5
120
90
UNITS
5
see text
ns
ns
= +5.0 volts ± 5%)
SYM
PARAMETER
TYP
CI
All pins (except 0/0)
4pF
6
COla
0/0 pins
10pF
6,7
NOTES:
1. All voltages referenced to Vss.
2. Measured with .4:S VI:S 5.0 V. outputs deselected and Vee = 5 V.
3. AC measurements assume Transition Time = 5 ns; levels VSS to 3.0 V.
4. Input and output timing reference levels are at 1.5 V.
5. Measured with a load as shown in Figure 3.
.6.0
6. Effective capacitance calculated from the equation C =~ith l:1V = 3 yolts
and power supplies at nominal levels.
7. Output buffer is deselected.
B. A minimum of 2 ms time delay is required after application of Vee (+5 V)
before proper device operation can be achieved.
9. ICCl measured with outputs open.
10. Negative undershootsto8 minimum of-l.5 Vara allowed with a maximum
of 50 ns pulse width. DC value of low level input must not exceed -0.3 V.
11. Power supply current decreases with increasing temperature.
OUTPUT LOAD
MAX
NOTES
5V
Figure 3
1.1 KO
D.U.T. - -......- - -..
6800
/'r;
-'--
XII-89
30pF
(Including Scope and Jig)
TIMING DIAGRAM
Figure 4
READ
1-.. ---tRC
READ
WRITE
----_1------ tRC - - - -.....~---- twc ---_._·1
000-0
°7 -----------1(
' - -_ _..J
TIMING DIAGRAM
Figure 5
WRITE
WRITE
twc
twc
(-4-----
XII-90
READ
---~~_----
tRC - - - - - . - J
DESCRIPTION (Cont.)
The MKB4801 A features a fast CE (50% of Address Access)
function to permit memory expansion without impacting
system access time. A fast OE (50"10 of access time) is
included to permit data interleaving for enhanced system
performance.
The MKB4801A is pin compatible with Mostek's
BYTEWYDETM memory family of RAMs. ROMs and
EPROMs.
OPERATION
Read Mode
The MKB4801 A is in the READ MODE whenever the Write
Enable Control input (WE) is in the high state.
In the READ mode of operation. the MKB4801 A provides a
fast address ripple-through access of data from 8 of 8192
locations in the static storage array. Thus. the unique
address specified by the 10 Address Inputs (An) define
which 1 of 1024 bytes of data is to be accessed.
A transition on any ofthe 10 address inputs will disable the
8 Data Output Drivers after t AZ . Valid Data will be available
to the 8 Data Output Drivers within tAA after the last address
input signal is stable. providing that the CE and OE access
times are satisfied. If CE or OE access times are not met.
data access will be measured from the limiting parameter
(t CEA or tOEA) rather than the address. The state ofthe 8 data
1/0 signals is controlled by the Chip Enable (CE) and Output
Enable (OE) control signals.
Write Mode
The MKB4801 A is in the Write Mode whenever the Write
Enable (WE) and Chip Enable (CE) control inputs are in the
low state.
The WRITE cycle is initiated by the WE pulse going low
provided that CE is also low. The leading edge of the WE
pulse is used to latch the status of the address bus.
NOTE: In a write cycle the latter occurring edge of either WE
or CE will determine the start of the write cycle. Therefore.
tAs.:.!.wo and tAH are referenced to the latter occurring edge
of CE or WE. Addresses are latched at this time. All write
cycles whether initiated by CE orWE must beterminated by
the rising edge of WE. If the output bus has been enabled
(CE and OE low) then WE will cause the output to go to the
high Z state in t WEZ '
Da.!!.!n must be valid tosw prior to the low to high transition
of WE. The Data In lines must remain stable for tOHw after
WE goes inactive. The write control of the MKB4801A
disables the data out buffers during the write cycle;
however. OE should be used to disable the data out buffers
to prevent bus contention between the input data and data
that would be output upon completion of the write cycle.
II
XII-91
XII-92
MOSTEI{.
MILITARYIHIGH-REL PRODUCTS
PROCESSED TO MIL-STD 883, METHOD 5004, CLASS B
2048 x 8 Bit Static RAM
MKB4802(P I J/E)-81 183
FEATURES
o Static operation
o High performance
o Organization: 2K x 8 bit RAM JEDEC pinout
o Pin compatible with Mostek's BYTEWYDETM memory
family
o Double density version of the MKB4118 1K x 8 static
RAM
Part No.
Access Time
R/W
Cycle Time
MKB4802-81
120 nsec
120 nsec
MKB4802-83
200 nsec
200 nsec
o 24128 pin ROM/PROM compatible pin configuration
o CE and OE functions facilitate bus control
o -55°C to 125°C operating temperature
DESCRIPTION
with high performance and low power dissipation by
utilizing Address Activated™ circuit design techniques.
The MKB4802 uses Mostek's Scaled POLY 5™ process and
advanced circuit design techniques to package 16,384 bits
of static RAM on a single chip. Static operation is achieved
BLOCK DIAGRAM
The MKB4802 series presents to the user a high density
cost effective N-MOS memory with the performance charac-
Figure 1
Figure 2
DATA INPUTS/OUTPUTS
000 - 007
YSENSE AMP
II< WRITE DRIVER
"
"
"
'"
1-=:==:1
I-
"
"
PIN CONNECTIONS
A7 1
A62
A5 3
24 Vee
23 AS
A44
21 WE
20 OE
A35
A26
A17
A08
llBx16.a
ME'MORY CelL
"'.
"
"
000 9
OQ110
OQ211
"
VSS12
22 Ag
19 A10
18
CE
A7 NC NC NC vccNC NC
~4J ~:: L~I
A6 ~~:
As -_-1;1
;')
:i
~~ ~~j l:~
L.J
A3 ~~
=~:
A, I~
lEADlESS CHIP
CARRIER
IE PAK)
TOP VIEW
X
OE
WE
Mode
DQ
VIH
x
x
Deselect
High Z
VIL
X
VIL
Write
DIN
VIL
VIL
VIH
Read
DOUT
VIL
VIH
VIH
Read
High Z
~
PIN NAMES
Ao-AtO Address Inputs
':!.s:,s;,
CE
Chip Enable
WE
OE
Vss
Ground
DOa-DQ7Data In/Data Out
Don't Care
XII-93
C2~~
WE
[2~_
OE
~~~ A,o
170Q7 Ao
~~ CE
~fl
'450 mil x 550 mil
160Q6 NC 1~
2~-D~
JEDEC type E)
150Q5 DOo I3}
:!i DO,
140Q4
:;;l r~ F~ ~~ ;81 i,~ ~~
130Q3
OQ, DQ 2 VssNCOQ 3 DQ4 DQs
TRUTH TABLE
CE
~~~ A,
~!~ NC
A4 ~?:
A2
=z:~ As
Power (+5 V)
Write Enable
Output Enable
II
ABSOLUTE MAXIMUM RATINGS*
Voltage on any pin relative,to Vss ............................................................ -0.5 V to +7,0 V
Operating Temperature TA (Ambient) ..•..•.............•....................•.•...•.••....... -55°C to +125°C
StorageTemperature (Ambient) ....................• , .............. , ..............•.•••...... -65°C to +150°C
Power DisSipation .....••.....•................................................................•..•• 1 Watt
Output Current ....•....••.....•.•............................••...................................• 20 mA
·Stresses greater than those· listed un:der "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolut~
maximum rating conditions for extended periods may affect reliability.
RECOMMENDED D.C. OPERATING CONDITIONS8
(-55°C:::; TA:::; + 125°C)
SYM
PARAMETER
MIN
TYP
MAX
UNITS
NOTES
Vee
Supply Voltage
4.75
5.0
5.25
V
1
VSS
Supply Voltage
0
0
0
V
1
V IH
Logic "1" Voltage All Inputs
2.4
Vee +.5 V
V
1
VIL
Logic "0" Voltage All Inputs
-0.3
.65
V
1,10
MAX
UNITS
NOTES
120
mA
9
90
mA
9, 11
DC ELECTRICAL CHARACTERISTICS,·8
(-55°C:::; TA :::; + 125°C) (Vee = 5.0 volts ± 5%)
MIN
SYM
PARAMETER
lee1
Average Vee Power Supply Current
lee1
Average Vee Power Supply Current (TA
IlL
Input Leakage Current (Any Input)
-10
10
pA
2
IOL
Output Leakage Current
-10
10
pA
2
V OH
Output Logic "1" Voltage lOUT = -1 mA
2.4
VOL
Output Logic "0" Voltage lOUT = 4 mA
= 125°C)
V
0.4
V
MAX
AC ELECTRICAL CHARACTERISTICS1.8
(-55°C:::; TA :::; +125°C) (Vee +5.0 volts ± 5%)
=
SYM
PARAMETER
TYP
CI
Capacitance on all pins (except 0/0)
4pF
6
COlO
Capacitance on 0/0 pins
10 pF
6,7
XII-94
NOTES
ELECTRICAL CHARACTERISTICS3.4
(-55°C ::5 TA ::5 + 125°C) (Vcc = 5.0 volts
± 5%)
MKB4802-81
MIN
MAX
MKB4802-83
MIN
MAX UNITS
SYM
PARAMETER
t RC
Read Cycle Time
tAA
Address Access Time
120
200
ns
5
tCEA
Chip Enable Access Time
60
100
ns
5
tCEZ
Chip Enable Data Off Time
35
ns
tOEA
Output Enable Access Time
100
ns
tOEZ
Output Enable Data Off Time
5
35
ns
tAZ
Address Data Off Time
10
10
ns
twc
Write Cycle Time
120
200
ns
tAs
Address Setup Time
0
0
ns
see text
tAH
Address Hold Time
40
65
ns
see text
tosw
Data To Write Setup Time
10
20
ns
tOHW
Data From Write Hold Time
10
10
ns
two
Write Pulse Duration
45
60
ns
tWEZ
Write Enable Data Off Time
5
t WPL
Write Pulse Lead Time
65
120
5
ns
200
35
5
60
35
35
5
5
NOTes
35
130
5
see text
ns
ns
OUTPUT LOAD
NOTES:
1. All voltages referenced to Vss.
2. Measured with .4 S; VI:S; 5.0 V, ou~p_uts des.elected and Vee;:: 5 V.
3. AC measurements assume Transition Time = 5 ns; levels VSS to 3.0 V.
4. Input and output timing reference levels are at 1.5 V.
5. Measured with a load as shown in Figure 3.
6. Effective-capacitance calculated from the equation C ;:: flO with 6.V;:: 3 volts
and power supplies at nominal levels.
6.V
7. Output buffer is deselected.
8. A minimum of 2 rns time delay is required after application of Vee (+5 V)
before proper device operation can be achieved.
9.ICC1 measured with outputs open.
10. Negative undershoots to a minimum of -1.5 V are allowed with a maximum
of 50 ns pulse width. DC value of low level input must no\ exceed -0.3 V.
11. Power supply current decreases ,with increasing temperature.
Figure 3
XII-95
5V
1.1KO
D.U.T. - -......- - -..
6800
;:f'
100 pF
(Including Scope and Jig)
TIMING DIAGRAM
Figure 4
READ
I~"----'Re
READ
WRITE
-----~~------'Re--------~++--------
'we
------..~I
TIMING DIAGRAM
Figure 5
WRITE
'we
WRITE
READ
'we
'Re
AO-A10
CE
OE
-
'WPL ....
--.-'WEZ
WE
<
VALID
IN
)
~
'O"W~
V~~IO
XII-96
')
~
VALID OUT
'j--
teristics necessary for today's high performance microprocessor applications. The MKB4802 is ideal for memory
applications where the organization requires relatively
shallow depth with a wide word format.
access will be measured from the limiting parameter (t CEA
or tOEA) rather than the address. The state ofthe 8 data I/O
signals is controlled by the Chip Enable (CE) and Output
Enable (OE) control signals.
The MKB4802 features a fast CE (50"10 of Address Access)
function to permit memory expansion without impacting
system access time. A fast OE (50"10 of access time) is
included to permit data interleaving for enhanced system
performance.
WRITE MODE
The MKB4802 is in the Write Mode whenever the Write
Enable (WE) and Chip Enable (CE) control inputs are in the
low state.
The MKB4802 is pin compatible with Mostek's
BYTEWYDpM Memory Family of RAMs, ROMs and
EPROMs.
The WRITE cycle is initiated by the WE pulse going low
provided that CE is also low. The leading edge of the WE
pulse is used to latch the status of the address bus.
OPERATION
NOTE: In a write cycle the latter occurring edge of either WE
or CE will determine the start of the write cycle. Therefore,
tAs.:..!Yvo and tAH are referenced to the latter occurring edge
of CE or WE. Addresses are latched at this time. All write
cycles whether initiated by CE or WE must be terminated by
the rising edge of WE. If the output bus has been enabled
(CE and OE low) the WE will cause the output to go to the
high Z state in tWEz.
READ MODE
The MKB4802 is in the READ MODE whenever the Write
Enable Control Input (WE) is in the high state. In the READ
mode of operation, the MKB4802 provides a fast address
ripple-through access of data from 8 of 16,384 locations in
the static storage array. Thus, the unique address specified
by the 11 Address Inputs (An) define which 1 of 2048 bytes
of data is to be accessed.
A transition on any ofthe 11 address inputs will disable the
8 Data Output Drivers after t AZ . Valid Data will be available
to the 8 Data Output Drivers within tAA after the last address
input signal is stable, providing that the CE and OE access
time are satisfied. If CE or OE access times are not met, data
Data In must be va Iid tosw priorto the low to high tra nsition
of WE. The Data In lines must remain stable for tOHW after
WE goes inactive. The write control of the MKB4802
disables the data out buffers during the write cycle;
however, OE should be used to disable the data out buffers
to prevent bus contention between the input data and data
that would be output upon completion of the wrITe cycle.
XII-97
1982/1983 MICROELECTRONIC DATA BOOK
:::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::=:. . . . - . . . . . . . . -~~.::.-...- - -
@) Microprocessor and Support Devices
Ii'"
MOSTEI(.
zao
CENTRAL PROCESSING UNIT
Processed to MIL-STD 883, Method 5004, Class B
MKB3880(P)-80/84
FEATURES
o Single 5-Volt supply and single-phase clock required
o Screened per MIL-STD-883, Method 5004 Class B
o Z80 CPU and Z80 A CPU
o Software compatible with 8080A CPU
o -55°C to 125°C temperature range
o Complete development and OEM system product
support
o Two speeds
• 2.5 MHz MKB3880)P)-80
• 4.0 MHz MKB3880(P)-84
o Industrial MKI version available (-40°C to 85°C)
DESCRIPTION
The Mostek Z80 family of components is a significant
advancement in the state-of-art of microcomputers. These
components can be configured with any type of standard
semiconductor memory to generate computer systems with
an extremely wide range of capabilities. For example,.as few
as two LSI circuits and three standard TTL MSI packages
can be combined to form a simple controller. With additional
memory and 1/0 devices, a computer can be constructed
with capabilities that only a minicomputer could deliver
previously. This wide range of computational power allows
standard modules to be constructed by a user that can
satisfy the requirements of an extremely wide range of
applications.
The CPU is the heart of the system. Its function is to obtain
instructions from the memory and perform the desired
operations. The memory is used to contain instructions and,
in most cases, data that is to be processed. For example, a
typical instruction sequence may be to read data from a
specific peripheral device, store it in a location in memory,
check the parity, and write it out to another peripheral
device. Note that the Mostek component set includes the
CPU and various general purpose 1/0 device controllers, as
well as a wide range of memory devices. Thus, all required
components can be connected together in a very simple
manner with virtually no other external logic. The user's
effort then becomes primarily one of the software
development. That is, the user can concentrate on
describing his problem and translating it into a series of
instructions that can be loaded into the microcomputer
memory. Mostek is dedicated to making this step of
software generation as simple as possible. A good example
of this is our assembly language in which a simple
mnemonic is used to represent every instruction that the
CPU can perform. This language is self-documenting in
such a way that from the mnemonic the user can
understand exactly what the instruction is doing without
constantly checking back to a complex cross listing.
ZSO-CPU BLOCK DIAGRAM·
ZSO PIN CONFIGURATION
Figure 1
Figure 2
r
MREQ
SYSTEM
CONTROL
~RO
RD
WR
RFsH
ALU
INSTRUCTION
DECODE
,
r
WAIT
CPU
___ /' I &
CPU
13
CONTROL
CPU AND
CONTROL
~
NM'
SYSTEM
CONTROL
27
..
"
"
'"
22
..
Z80CPU
MKB3880(P)-80
MKB3880(P)-84
REsE'f
SIGNALS
CPU
BUS
CONTROL
A,
A,
A,
A,
A.
A,
A.
Ag
A,.
A"
A"
A"
A"
A"
ADDRESS
BUS
{BUSRO
BUSAK
D.
ri'r
0,
0,
0,
0,
0,
0,
0,
.,v
GND
+5V GND 'I'
}."
BUS
XIII~1
------_._- ._.
.. _--
--_.-
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias .•...•...................•............•.•..•............•........... -55°C to +125°C
Storage Temperature ........••..........•......••....•...........•.....•..•...........•••.. -65°C to +150°C
Voltage on Any Pin with Respect to Ground ...................................• ; ....•...••.•..•.. -O.3V to + 7V
Power Dissipation ............•..........•.....•••..••..........••.........•.....•.•...•......•.....• 1 .5W
*Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at
these or any other condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
DC CHARACTERISTICS
(TA = -55°C to 125°C, Vee = 5 V ± 5% unless otherwise specified)
MAX
UNIT
-0.3
0.8
V
Vee-· 6
Vee +·3
V
Input Low Voltage
-0.3
0.8
V
V IH
Input High Voltage
All inputs except NMI
2.4
Vee
V
VIH(NMI)
Input High Voltage (NMI)
2.7
Vee
V
VOL
Output Low Voltage
0.4
V
IOL = 1.8mA
V OH
Output High Voltage
V
IOH =-250~
Icc'
Power Supply Current
200
mA
III
Input Leakage Current
10
~
V IN = OtoVee
ILOH
Tri-State Output Leakage
Current in Float
10
~
V OUT = 2.4 to Vee
Tri-State Output Leakage
Current in Float
-10
~
VOUT=0.4V
Data Bus Leakage Current
In Input Mode
±10
~
O
MAX
UNIT
TEST CONDITIONS
Clock Capacitance
35
pF
Unmeasured Pins
CIN
Input Capacitance
5
pF
Returned to Ground
COUT
Output Capacitance
10
pF
XIII-2
AC CHARACTERISTICS
MKB3880(P)-80 Z80-CPU
(TA = -55°C to 125°C, VCC = +5V, ±5%, Unless Otherwise Noted)
SIGNAL
SYM
PARAMETER
MIN
MAX
UNIT
te
Clock
Clock
Clock
Clock
.4
180
180
[12]
(D)
2000
30
Ilsec
nsec
nsec
nsec
145
110
[1]
nsec
nsec
nsec
[2]
nsec
[3]
nsec
[4]
nsec
~(cpH)
cp
tw(cpL)
t,f
tD(AD)
tF(AD)
taem
Ao-15
taei
tea
tea!
tD(D)
tF(D)
tS(D)
DO-7
tS;j;(D)
t dem
t dei
ted!
tH
tDL;j;(MR)
MREO
tDH(MR)
tDH;P(MR)
tw(MRL)
tw(MRH)
tDLIWR)
WR Delay From Rising Edge of Clock,
WRLow
WR Delay From Falling Edge of Clock,
WRLow
WR Delay From Falling Edge of Clock,
WR High
Pulse Width, WR Low
tDLIWR)
1wIWRL)
t DLlM1 )
Ml
tDHIM1)
RFSH
t DLlRF )
tDHIRF)
MIN
MAX
UNIT
80
nsec
90
nsec
100
nsec
Ml Delay From Rising Edge of Clock
Ml Low
Ml Delay From Rising Edge of Clock,
Ml High
130
nsec
130
nsec
RFSH Delay From Rising Edge of Clock,
RFSH Low
RFSH Delay From Rising Edge of Clock
RFSH High
180
nsec
150
nsec
CL = 50pF
CL = 30pF
t slWT )
WAIT Setup Time to Falling Edge of
Clock
HALT
t DIHT)
HALT Delay Time From Falling Edge
of Clock
INT
t sllT)
INT Setup Time to Rising Edge of Clock
80
nsec
NMI
twINML)
Pulse Width, NMI Low
80
nsec
BUSRO
ts(BQ)
BUSRO Setup Time to Rising Edge of
Clock
80
nsec
BUSAK
t DLlBA )
BUSAK Delay From Rising Edge of
Clock, BUSAK Low
BUSAK Delay From Falling Edge of
Clock, BUSAK High
RESET
Delay to/from Float (MREO, IORO,
RDandWRI)
tmr
Ml Stable Prior to IORO (Interrupt Ack.)
taem = tw (H) + If -75
[2]
taci
[3]
tea = tw (L) + tr -40
teaf = tw (t) + tr -60
[5]
t dem = te -210
[6]
[7]
[8]
tde; = tw (L) + tr -210
tedf = tw (L) + tr -80
1w (MRL) = Ie -40
nsec
110
nsec
nsec
90
100
[9]
[11]
nsec
nsec
tw (MRH) = tw (H) + t f -70
[10] tw (WR) = te -40
[12] te = tw (H) + tw(L) + tr + If
LOAD CIRCUIT FOR OUTPUT
Figure 3
TEST POINT
= te -80
[4]
120
CL = 50pF
[11] tmr = 2tc + tw (H) + If -80
Add 10 nsec delay for each 50pF increase in load up to a maximum of 200pF for
the data bus and 1OOpF for address and control lines.
Although static by design, testing guarantees tw (4)H) of 200 J.1sec maximum.
[1]
nsec
CL = 50pF
t Fle )
2. The RESET signal must be active for a minimum of 3 clock cycles.
3. Output Delay vs. Load Capacitance
TA = 125°C Vee = 5 V ± 5%
4.
300
RESET Setup Time to Rising Edge of
Clock
active.
nsec
70
t slRS )
NOTES
1. Data should be enabled onto the CPU data bus when RD is active. During
interrupt acknowledge data should be enabled when Ml and lORa are both
CL = 50pF
nsec
[10]
WAIT
tDHIBA)
TEST CONDITION
XIII-4
R,.2.1K,Q
AC CHARACTERISTICS
MKB3880(P)-84 Z80A-CPU
(TA = -55°C to 125°C, Vee = +5V, ±5%, Unless Otherwise Noted)
SIGNAL
SYM
PARAMETER
MIN
MAX
UNIT
Clock
Clock
Clock
Clock
.25
110
110
[12]
(D)
2000
30
f.isec
tc
tw(H)
tw(L)
110
90
[1]
nsec
nsec
nsec
[2]
nsec
[3]
nsec
[4]
nsec
t"f
to(AO)
tF(AO)
tacm
Ao.15
tac;
tca
tcaf
tOlD)
tF(O)
t S 4>(O)
DO-7
ts¥(O)
tdcm
tdc;
tcdf
tH
tOL¥(MR)
MREO
t OH4>(MR)
tOH¢(MR)
tw(MRL)
tw(MRH)
t OL4>(lR)
tOL¥(IR)
10RO
tOH;j;(IR)
tOH4>(IR)
t OL4>(RO)
RD
tOL¥(RO)
tOH4>(RO)
tOH¢;(RO)
Period
Pulse Width, Clock High
Pulse Width, Clock Low
Rise and Fall Time
Address Output Delay
Delay to Float
Address Stable Prior to MREO
(Memory Cycle)
Address Stable Prior to 10RO, RD or
WR (I/O Cycle)
Address Stable From RD, WR, 10RO
or MREO
Address Stable From RD or WR
During Float
Data Output Delay
Delay to Float During Write Cycle
Data Setup Time to Rising Edge of
Clock During M 1 Cycle
Data Setup Time to Falling Edge at
Clock During M2 to M5
Data Stable Prior to WR (Memory
Cycle)
Data Stable Prior to WR (I/O Cycle)
Data Stable From WR
Input Hold Time
MREO Delay From Falling Edge of
Clock, MREO Low
MREO Delay From Rising Edge of
Clock, MREO High
MREO Delay From Falling Edge of
Clock, MREO High
Pulse Width, MREO Low
Pulse Width, MREO High
nsec
nsec
nsec
50
nsec
nsec
nsec
60
nsec
[5]
nsec
[6]
[7]
0
nsec
nsec
nsec
170
90
20
85
nsec
85
nsec
85
nsec
[8]
[9]
CL = 50pF
Except T3-M1
CL = 50pF
CL = 50pF
nsec
nsec
10RO Delay From Rising Edge of
Clock, 10RO Low
10RO Delay From Falling Edge of
Clock, 10RO Low
IORO Delay From Rising Edge of
Clock, 10RO High
10RO Delay From Falling Edge of
Clock, 10RO High
75
nsec
85
nsec
85
nsec
85
nsec
RD Delay From
RD Low
RD Delay From
RD Low
RD Delay From
RD High
RD Delay From
RD High
Rising Edge of Clock,
85
nsec
Falling Edge of Clock,
95
nsec
Rising Edge of Clock,
85
nsec
Falling Edge of Clock,
85
nsec
XIII-5
TEST CONDITION
CL = 50pF
CL = 50pF
II
AC CHARACTERISTICS (Cont.)
SIGNAL
SYM
tOL(WR)
WR
tOL~(WR)
tOH(WR)
tw(WRL)
tOL(Ml)
M1
t OH(Ml)
RFSH
tOL(RF)
tOH(RF)
PARAMETER
MIN
WR Delay From Rising Edge of Clock,
WRLow
WR Delay From Falling Edge of Clock,
WRLow
WR Delay From Falling Edge of Clock,
WR High
Pulse Width, WR Low
MAX
UNIT
65
nsec
80
nsec
80
nsec
[10]
M1 Delay From Rising Edge of Clock
M1 Low
M1 Delay From Rising Edge of Clock,
M1 High
100
nsec
100
nsec
RFSH Delay From Rising Edge of Clock,
RFSH Low
RFSH Delay From Rising Edge of Clock
RFSH High
130
nsec
120
nsec
CL '" 50pF
CL '" 50pF
tS(WT)
WAIT Setup Time to Falling Edge of
Clock
HALT
to(HT)
HALT Delay Time From Falling Edge
of Clock
INT
ts(lT)
INT Setup Time to Rising Edge of Clock
80
nsec
NMI
tw(NML)
Pulse Width, NMI Low
80
nsec
BUSRO
ts(BQ)
BUSRO Setup Time to Rising Edge of
Clock
50
nsec
BUSAK
tOL(BA)
BUSAK Delay From Rising Edge of
Clock, BUSAK Low
BUSAK Delay From Falling Edge of
Clock, BUSAK High
RESET
1.
300
tF(C)
Delay to/From Float (MREO, IORO,
RDandWR)
t m,
M1 Stable Prior to IORO (Interrupt Ack.)
active.
2. The RESET signal must be active for a minimum of 3 clock cycles.
3. Output Delay vs. Load Capacitance
TA = 125'e Vee = 5 V ± 5%
Add 10 nsec delay for each 50pF increase in load up to a maximum of 200pF for
the data bus and l00pF for address and control lines.
4. Although static by deSign, testing guarantees tw (¢H) of 200 f.1sec maximum.
[1]
taem '" tw (4)H) + it -65
[2]
[3]
taei '" te -70
tea '" tw (4)L) + t, -50
[4]
[5]
[6]
tea' '" tw (4)L) + t, -45
l dem '" te -1 70
tdei '" tw (4)L) + t, -170
[7]
ted' '" tw (4)L) + t, -70
[8]
tw (MRL) '" te -30
nsec
100
nsec
100
nsec
CL '" 50pF
CL '" 50pF
RESET Setup Time to Rising Edge of
Clock
Data should be enabled onto the CPU data bus when AD is active. During
interrupt acknowledge data should be enabled when M1 and IORO are both
nsec
70
ts(RS)
NOTES
CL '" 50pF
nsec
WAIT
tOH(BA)
TEST CONDITION
nsec
60
80
[9]
[11]
nsec
nsec
tw (MRH) '" tw (4)H) + t, -40
[10] tw (WR) '" te -30
[11] t m, '" 2te + tw (4)H) + t, -65
[12] te '" 6 w (4)H) + t w(4)L) + t, + t,
LOAD CIRCUIT FOR OUTPUT
Figure 4
TEST POINT
XIII-6
Vee
A.C. TIMING DIAGRAM
Timing measurements are made at the following voltages, unless otherwise specified.
CLOCK
OUTPUT
INPUT
FLOAT
"1 "
V ee-·6
2.4V
2.4V
"0"
!;V
±0.5V
.8V
.8V
.8V
A O-A15
A O- 15
IN
DO_7 {
DUT
tOllMll
"Ic} _I
(j-- -----~'
',+_rI
'D:~~rr-
"'-r-r-
"'l--r't~
,
I
I
______________________________________-+t-______________________________
ii'i:iSii'K
XIII-7
,
I
~-- ~'DH IBA)
~'U~l~IB~A}_
II
XIII-8
MOSTEl{@
MILITARYIHIGH-REL PRODUCTS
Processed to MIL-STD 883, Method 5004, Class B
Parallel 1/0 Controller
MKB3881 (P)-80/84
FEATURES
DESCRIPTION
o Two independent 8 bit bidirectional peripheral interface
ports with 'handshake' data transfer control
The Z80 Parallel I/O Circuit is a programmable, two port
device which provides a TIL compatible interface between
peripheral devices and the Z80-CPU. The CPU can
configure the Z80-P10 to interface with a wide range of
peripheral devices with no other external logic required.
Typical peripheral devices that are fully compatible with the
Z80-P10 include most keyboards, paper tape readers and
punches, printers, PROM programmers, etc. The Z80-P10
utilizes N channel silicon gate depletion load technology
and is packaged in a hermetic 40 pin DIP.
o Interrupt driven 'handshake' for fast response
o Anyone of four distinct modes of operation may be
selected for a port including:
• Byte output
• Byte input
• Byte bidirectional bus (Available on Port A only)
• Bit control mode
All with interrupt controlled handshake
o Daisy chain priority interrupt logic included to provide for
automatic interrupt vectoring without external logic
o Eight outputs are capable of driving Darlington
tra nsistors
o Typical ordering: MKB3881 P-80
MKB3881 P-84
2.5 MHz Z80-P10
4.0 MHz Z80-P10
o Single 5 volt supply and single phase clock required
o Fully processed to MIL-STD-883 Method 5004, Class B.
-55°C to 125°C temperature range
o
One of the unique features of the Z80-P10 that separates it
from other interface controllers is that all data transfer
between the peripheral device and the CPU is accomplished
under total interrupt control. The interrupt logic of the PIO
permits full usage of the efficient interrupt capabilities ofthe
Z80-CPU during I/O transfers. All logic necessary to
implement a fully nested interrupt structure is included in
the PIO so that additional circuits are not required. Another
unique feature of the PIO is that it can be programmed to
interrupt the CPU on the occurrence of specified status
conditions in the peripheral device. For example, the PIO
can be programmed to interrupt if any specified peripheral
alarm conditions should occur. This interrupt capability
reduces the amount of time that the processor must spend
in polling peripheral status.
MKI3881 available for Industrial/Hi-Rei users
PIO BLOCK DIAGRAM
PIO PIN CONFIGURATION
,
'.
c."
PERIPHERAL
INTERFACE
INTERFACE
,
.,'
DATA OR CONTROL
}
HANDSHA"'E
'.
,'.
}
HANDSHAKE
XIII-9
II
XIII-10
MOSTEI{.
MILITARYIHIGH-REL PRODUCTS
Processed to MIL-STD 883, Method 5004, Class B
Counter Timer Circuit
MKB3882 (P/J)-80/84
FEATURES
DESCRIPTION
o Each channel may be selected to operate in either
The Z80-Counter Timer Circuit (CTC) is a programmable
component with four independent channels that provide
counting and timing functions for microcomputer systems
based on the Z80-CPU. The CPU can configure the CTC
channels to operate under various modes and conditions as
required to interface with a wide range of devices. In most
applications, little or no external logic is required. The Z80CTC utilizes N-channel silicon gate depletion load
technology and is packaged in a 28-pin DIP. The Z80-CTC
requires only a single 5 volt supply and a one-phase 5 volt
clock.
Counter Mode or Timer Mode
o Used in either mode, a CPU-readable Down Counter
indicates number of counts-to-go until zero
o A Time Constant Register can automatically reload the
Down Counter at Count Zero in Counter and Timer Mode
o Selectable positive or negative trigger initiates time
operation in Timer Mode. The same input is monitored
for event counts in Counter Mode
o Three channels have Zero CountlTimeout outputs
capable of driving Darl ington transistors
o Interrupts may be programmed to occur on the zero
count condition in any channel
o Da isy cha i n priority interrupt logic i ncl uded to provide for
automatic interrupt vectoring without external logic
o Typical ordering: MKB3882P-80
MKB3882P-84
2.5 MHz Z80-CTC
4.0 MHz Z80-CTC
o Fully processed to MIL-STD-883 Method 5004 Class B.
-55°C to +125°C operating range
A block diagram of the Z80-CTC is shown in the figure. The
internal structure oftheZ80-CTC consists of a Z80-CPU bus
interface, Internal Control Logic, four sets of Counter/Timer
Channel Logic, and Interrupt Control Logic. The four
independent counter/timer channels are identified by
sequential numbers from 0 to 3. The CTC has the capability
of generating a unique interrupt vector for each separate
channel (for automatic vectoring to an interrupt service
routine). The 4 channels can be connected into four
contiguous slots in the standard Z80 priority chain with
channel number 0 having the highest priority. The CPU bus
interface logic allows the CTC device to interface directly to
the CPU with no other external logic. However, port address
decoders and/or line buffers may be required for large
systems.
o MKI3882 available for Industrial Hi-Rei users
ZSO-CTC PIN CONFIGURATION
ZSO-CTC BLOCK DIAGRAM
~~~~O~~~NT /
".
",
CLOCK/TRIGGER 0
ZERO COUNTt
TIMEOUT 1
CHI',.
CONTROL
ZERO COUNT/
TIMEOUT 2
CLOCK/TRIGGER 2
CONTROL
LINES
XIII-11
..,!4
XIII-12
I!I
UNITED
MILITARY
HIGH-REL
PRODUCTS
TECHNOLOGIES
MOSTEK
SCREENED TO MIL-STD-883
16-BIT MICROPROCESSOR
MKB68000
Advances in semiconductor technology have provided the
capability to place on a single silicon chip a microprocessor
at least an order of magnitude higher in performance and
circuit complexity than has been previously available. The
MKB68000 is the first of a family of such VLSI microprocessors from Mostek. It combines state-of-the-art
technology and advanced circuit design techniques with
computer sciences to achieve an architecturally advanced
16-bit microprocessor.
MKB68000
Figure 2
The resources available to the MKB68000 user consist of
the following:
•
•
•
•
•
•
32-Bit Data and Address Registers
16 Megabyte Direct Addressing Range
56 Powerful Instruction Types
Operations on Five Main Data Types
Memory Mapped I/O
14 Addressing Modes
PROGRAMMING MODEL
PIN ASSIGNMENT
Figure 1
Figure 3
31
1615
87
o
lllllll-
I
I
I
I
I
-
I
I
I
I
I
I
I
I
I
I
I
-
I
-
I
I
I
r----
I
USERiiTACKPOINTER -
-
-
-
DO
AO
A1
A2
SEVEN
A3 ADDRESS
A4 REGISTERS
A5
A6
lWO STACK
A7 POINTERS
I
87
R'W
0'2
013
=
5'fiCK
ii!!
BGACR
0'5
1m
A23
V"
ClK
A2'
Hii'T'
i!tEiEf
-
0"
GND
A22
Vee
A20
A,9
\7IIill[
A'B
E
A'7
VI'lI:
A'S
A'S
IPLl
A"
A,3
IPLO
A'2
FC2
A"
FC'
A'O
6~~~~::
FCO
AO
A'
A2
AB
STATUS
REGISTER
A3
A6
A'
A5
0
ISYSTEM BYTEj USER BYTE I
OS
0'0
0"
iPi2
-~
SUPERVISOR STACK POINTER
15
AS
OS
om
GND
~---------------~
~
0
I
07
0'
DO
07
ll-
I
02
06
o
-
01
02
05
1615
I
0'
03
03 EIGHT
DATA
04 REGISTERS
31
D.
DO
This is advance information and specifications are subject to change without
nOlice.
XIII-13
A7
II
1982/1983 MICROELECTRONIC DATA BOOK
Industrial Hi-Rei Products
MKI INDUSTRIAL HIGH RELIABILITY
PRODUCTS
WHY DEMAND GREATER DEVICE QUALITY
The MKI family of memories and microprocessors is
manufactured by Mostek to be cost-effective for industrial
hi-rei applications. These devices are produced by the
Military Products Department using QPL facilities to insure
high quality and built-in reliability. Compared with
commercial devices, MKI offers these principle product
enhancements:
From the user's standpoint, improved incoming inte·
grated circuit quality means a lower cost at ownership,
As devices are mounted onto boards and then assembled
into systems, it becomes increasingly difficult and
expensive to remove failed devices from the manufacturing process. The full cost of locating and replacing one
bad IC during system assembly can range between $7
and $50 at today's rates. Figure 1 depicts this.
1. Extended temperature operation. All devices receive
complete electrical testing to verify funtionality to AC
and DC parameters over the -40°C to +85°C
temperature range.
Typical costs tor detection and replacement ot Ie
tailures at various manufacturing stages.
Figure 1
2. Greater system reliability. Each device receives a
125°C dynamic burn-in of at least 44 hours to remove
potential early life failures. Hermetic packaging
exclusively is employed.
3. Improved quality. Stringent military 100% test criteria
are applied and tightened AQL levels are guaranteed.
These reliability and capability enhancements make the
MKI device family ideally suited for high-reliability
extended temperature industrial applications. And,
because improved quality and reliability mean lower cost
of ownership, virtually any application should benefit
economically. Table 1· illustrates the breadth of application of the MKI device family.
At the component level. complex VLSI devices demand
extremely expensive testers for incoming evaluation, A
costly support staff must be maintained for test software
generation, tester operation and maintenance and parts
control.
Partial MKI Applications Spectrum
Table 1
INDUSTRY
At the board level. failed components reduce board test
throughput causing production delays. And inefficient
use of expensive automatic board test systems results if
they are time-shared for troubleshooting. To keep the
production flow smooth, failed boards are usually
accumulated for later repair. This increases work-inprocess and component inventories and their carrying
costs.
SYSTEM APPLICATION
At the system level. the cost of component failure is
magnified further. Due to the increased level of
integration, problem devices at this point are more
difficult to find. And failures at this late a stage often mean
late customer deliveries.
OPTIONS FOR ACHIEVING IMPROVED DEVICE
QUALITY
The user has a choice of any of three alternatives for
achieving greater IC quality. These are:
1. In-house incoming test
2. Use of burn-in test laboratories
3. Original purchase of vendor-screened hi-rei devices.
XIV-1
Beyond these fundamental concerns about test integrity
itself. use of burn-in labs often results in various logistics
problems (Table 2), such as:
Alternative 1. as noted before. can be very expensive.
Usually. this option is reseNed for only the very large user
(consumption approaching 100 million units/year). His
volume presents the opportunity to realize economies of
scale. and the large capital equipment outlay is easily
absorbed.
1. Unpredictable losses due to burn-in and temperature
test fallout. Possible ESD handling losses.
Burn-in labs can generally be expected to effectively test
SSI and most MSI functions. But complex. highly integrated
devices require an intimate familiarity with their design
and layout plus an extensive characterization and
production test database to insure consistently effective
screening. This level of ability resides with the Ie
manufacturer alone. For example. many VLSI devices can
exhibit pattern and temperature sensitivities that may
only become apparent years after their introduction. A
particular sensitivity might even vary from manufacturer to
manufacturer for the same generic part type. Screens for
these potential failure modes are frequently considered
proprietary by the device maker. They are therefore rarely
part of the test procedure used by burn-in labs.
2. Additional receiving inspections plus shipping and
handling costs.
3. Maintenance of larger in-transit and stockroom
inventories.
The use of manufacturer screened hi-rei devices such as
Mostek's MKI series. avoids all of the problems associated
with other alternatives. Mostek is experienCed in every
phase of volume VLSI production and test. Simply, quality
and reliability are assured by letting "the experts do it".
ConSiderations In the decision to upgrade commercial
or purchase vendor produced hi-rei ICs.
Table 2
CONSIDERATION
VARIABLES OF UPGRADING
COMMERCIAL ICs
XIV-2
THE CERTAINTIES OF BUYING MKI
MKI: ACHIEVING IMPROVED QUALITY
MKI Test Flow
Table 4
Ie FAILURE MECHANISMS
In typical usage, IC failures are traceable to random
defects or errors that occurred at some stag'e in their
production. Table 3 below illustrates the types of failure
mechanisms affecting device quality in each of three
major production stages. Also noted are the MKI controls
applied to eliminate these defects during production.
QUALITY STARTS IN WAFER FAB
Quality and reliability are built into Mostek MKI products
starting in wafer fabrication. Facilities and equipment in
this critical area are among the most advanced in the
world today. Five-inch wafers are positioned and exposed
with direct-step-on-wafer CDSW) projection systems. This
assures highly accurate feature definition, enhancing
yields and minimizing defect density. In ultra-clean
darkroom areas, dust particles are controlled to within
10 ppm not exceeding Y, micron in size, further minimizing
chances of contamination that could· jeopardize
reliability. Tightly controlled processes, coupled with
Mostek's history of innovative circuit design and fabrication experience, result in MKI devices with built-in
reliability.
MKI TESTING
The·MKI program subjects each device to a battery of
100% environmental and electrical tests to weed out
defectives and assure conformance to specifications.
Table 4 depicts the rigorous screening MKI devices
undergo. Test criteria are. based upon MIL-STD-883B
methods.
·Burn-in is generally longer. The MKI program requires the
removal of infant failures to the point at which the failure
rate becomes essentially flat. AnalYSis of device complexity, production maturity and Group C life test data
help determine bum-in length required.
IC failure Mechanisms and MKI Controls
Table 3
PRODUCTION STAGE
FAILURE MECHANISMS
POTENTIALLY INTRODUCED
MKI CONTROLS
1:1
XIV-3
voltage, eliminates the two major sources of early device
failure: oxide defects and contamination. Together. these
two failure mechanisms account for between 60% and
85% of MOS LSI failures in normal system usage.
TIGHTENED AQL REQUIREMENTS VERIFY
QUALITY
The MKI Quality Level program is designed to prevent the
possibility of shipment of defective devices to the user.
Table 5 details AQL levels all MKI devices must meet prior
to shipment.
MKI BURN·IN AND INFANT FAILURES
MKI AQL Guarantee
Table 5
It has been shown that the failure rate of semiconductor
devices over time is well described by the curve in Figure 2
below. The bathtub curve, as it's commonly called, is
divided into three regions, Failures per unit time are
greatest in the first 3 months to 1 year of normal usage,
corresponding to the infant failure region of Figure 2.
Beyond this, the failure rate is small and gradually
decl ining throug hout the useful life of the device (20 years
or more). Defective devices in this phase are random and
infrequent and remain so until wearout sets in.
Semiconductor failure rate V5, time
Figure 2
The MKI guarantee of .4% electrical AQL applies to all AC
and DC parameters and functionality over the entire
-40°C to +85'C range. For extended temperature designs
requiring critical parametric performance at temperature, MKI provides an extra margin of design safety,
Temperature upgrading of standard commercial devices
at a burn-in lab is generally not practical. Without access
to a device's temperature characterization database,
extended temperature testing at a test lab may result in
extremely low yields. It may also compromise reliability
since the commercial device manufacturer's "maximum
operating temperature" warning has been exceeded.
With MKI from Mostek, extended temperature performance to spec is guaranteed,
(44 - 160 HRS, C,C 125 C)
MKI devices recieve a variable length burn-in (44 hours
minimum) sufficient to remove the vast majority of infant
failures. Data from ongoing MIL-STD 883, Method 5005,
Group C, 1000 hour life testing is periodically analyzed to
describe the shape of a device's reliability curve, The
required length of MKI burn-in is accurately determined
from this and other considerations,
MKI: ACHIEVING IMPROVED RELIABILITY
PRODUCT RELIABILITY
What is the importance of MKI burn-in to the user? Point A
in Figure 2 represents the reduced failure rate of MKI
devices at delivery, This rate is as much as 10 to 15 times
lower than that exhibited by standard commercial
devices. It would take between 3 and 12 months of normal
operation of a system using commercial devices to weed
out enough failures before the remainder were as reliable
as MKI devices are at delivery. Further, the MKI variable
length burn-in can be expected to eliminate between
40% and 60% of devices subject to fail anytime in their
useful life. With MKI, a system manufacturer need not be
subject to the expense of repairing early failures at the
customer's site. And, the cost and difficulty of stressing his
system in-house for long periods of time before delivery is
eliminated. In short, the use of MKI ICs can help minimize
system cost and maximize customer satisfaction,
Reliability cannot be tested into a device. It must be built
in through proper. worst-case circuit design and tightlycontrolled waferfab processes, The implementation of this
philosophy keeps Mostek products among the most
reliable available anywhere.
Reliability however, must be verified before a device
reaches the user through stress testing. The MKI program
incorporates a variety of 100% screens (Table 4) to
compress time and weed out early life failures,
Temperature cycling, centrifuge, hermeticity, voltage
stress, and high temperature test all effectively screen a
percentage of the infant mortality, thereby improving
system reliability, The most important MKI reliability screen
applied is the 125°C, 44 hour minimum, dynamic burn-in,
Th,is stress test, accomplished at higher than nominal
XIV-4
MKI PRODUCTS AND ORDERING
INFORMATION
MKI industrial hi-rei components are produced by the
Military Products Department at Mostek using QPL
facilities. Table 6 shows currently available and planned
future MKI products. Generally. every MKI device Is also
available screened to Method 5004. Class Bof MIL-STD-883
(prefixed "MKB").
MKI Device listing
Table 6
t 1982 Introduction
PART NUMBERING
Example: MKI4116J-73
MK
Mostek Corp.
standard
prefix
Device screening
level:
I = Industrial
Hi-Rei
4116
J
7
3
Mostek
generic
part
number
Package:
J = cerdip
p= ceramic
sidebrazed
DIP
Temperature:
-40/+85°C
for MKI Products
Access time:
device
dependent
II
XIV-5
XIV-6
MOSTEI<.
MILITARYIHIGH-REL PRODUCTS
Extended Temperature, Extended Burn-in Industrial Processing
2048
8-Bit UV Erasable PROM
MKI2716(J)-77/78
X
FEATURES
D Three state output OR-tie capability
D 44 hr. min., 125°C burn-in plus Industrial screening for
greater reliability (see Figure 3 for processing
description)
D Five modes of operation for greater system flexibility (see
Table)
D Extended operating temperature (-40°C::; TA::; 85°C)
D Single
programming requirement: single
programming with one 50 msec pulse
location
D Pin compatible with Mostek's BYTEWYDETM memory
family
D Single +5 volt power supply during read operation
D Military MKB version available (-55°C to 125°C)
D TTL compatible in all operating modes
D Fast 450ns access time in read mode
D Standard 24 pin DIP with transparent lid
D Low power dissipation: 633 mW max active
MODE SELECTION
D Power down mode: 165 mW max standby
Pin
Mode
DESCRIPTION
The MKI2716 is a 2048 x 8 bit electrically programmable/ultraviolet erasable read only memory. The circuit
is fabricated with Mostek's advanced N-channel silicon gate
technology for the highest performance and reliability. The
MKI2716 offers significant advances over hardwired logic
cost, system flexibility, turnaround time and performance.
Figure 1
X
DECODER
'.'"'"',
~_v"
OE
Vpp
(18)
(20)
(21)
Output
Read
V'L
V'L
+5
Valid Out
Standby
V ,H
Don't
Care
+5
Open
Pulsed
V ,H
+25
Input
Program
V'L to V ,H
The MKI2716 has many useful system oriented features
including a standby mode of operation which lowers the
device power from 633mW maximum active power to
165mW maximum for an overall savings of 75%.
BLOCK DIAGRAM
CE/PGM
Program
Verify
V'L
V'L
+25
Valid Out
Program
Inhibit
V'L
V ,H
+25
Open
V cc(24) = 5V all modes
PIN CONNECTIONS
Figure 2
16.3848IT
CELL MATRIX
.---.--.--
A71
24Vcc
A62
23 A •
As 3
22Ag
A.4
21
A35
200E
v"
A2 6
19A,o
A,7
18CE
AD 8
170 7
00 9
160 6
0,10
150 s
0 2 11
14 0 •
GND12
130 3
PIN NAMES
AD - A 1D
CE/PGM
NOTE: Pin 18 and 20 have been renamed for compatibility with presently
available 16K, 32K and 64K ROMs and future generation 32K and 64K
EPROMs All other specifications for this device remain unaffected by this
change
XIV-7
Addresses
Chip Enablel
Program
OE
00
,
a,
Output Enable
Outputs
ABSOLUTE MAXIMUM RATINGS*
Voltage on any pin relative to Vss (Except Vpp) ................................................... --0.3 V to +6 V
Voltage on Vpp supply pin relative to Vss ............................••......................... --0.3 V to +28 V
Operating Temperature TA (Ambient) .........................................•.......•...• -40°C:S; TA:S; 85°C
Storage Temperature (Ambient) ................ " .. , .................................... -65°C:S; TA:S; +125°C
Power Dissipation .................................................................................. 1 Watt
Short Circuit Output Current ............... , ......................................................... 50 mA
·Stresses greater than those listed under "Absolute Maximum Ratings" maycause permanent damage tathe device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
READ OPERATION
RECOMMENDED DC OPERATING CONDITIONS
HO°C :s; TA:S; 85°C)
MAX
UNITS
2.0
Vcc +1
V
--0.1
0.8
V
TYP
MAX
UNITS
NOTES
MIN
SYM
PARAMETER
V IH
Input High Voltage
V IL
Input Low Voltage
TYP
NOTES
DC ELECTRICAL CHARACTERISTICS'·2.4.8
(-40°C:S; TA:S; 85°C) (Vcc = +5 V ± 5%, Vpp = V cel2
SYM
PARAMETER
ICCl
Vcc Standby Power Supply
Current (OE = V IL; CE =VIH )
10
30
mA
2
ICC2
V cc Active Power Supply
Current (OE = CE = Vld
57
115
mA
2
IpPl
Vpp Current (Vpp
10
mA
2
VOH
Output High Voltage
(lOH = -400 p,A)
VOL
Output Low Voltage
(IOL = 2.1 mAl
.45
V
IlL
Input Leakage Current
(VIN = 5.25 V)
10
JJ.A
IOL
Output Leakage Current
(Vour = 5.25 V)
10
JJ.A
MAX
UNITS
MIN
= 5.25 V)
V
2.4
AC ELECTRICAL CHARACTERISTICS,,2,6
(-40°C :s; TA :s; 85°C) (V cc = +5 V ± 5%, V pp = V cel2
-78
-77
SYM
PARAMETER
t ACC
Address to Output Delay
(CE = OE = V IL)
390
450
ns
tCE
CE to Output Delay
(OE = V IL)
390
450
ns
5
tOE
Output Enable to Output
Delay (CE = Vld
150
150
ns
9
tOF
Chip Deselect to Output
Float (CE = Vld
0
130
ns
8
tOH
Address to Output Hold
(CE = OE = V IL)
0
MIN
XIV-8
MAX
130
MIN
0
0
ns
NOTES
RECOMMENDED AC OPERATING CONDITIONS AND ELECTRICAL CHARACTRISTICS'·2.6.7
(TA = 25°C ± 5°C)(V cc = +5V ± 5%, Vpp = 25V ± 1V)
SYM
PARAMETER
TYP
t AS
Address Setup Time
2
J.ls
tOES
OE Setup Time
2
J.lS
tos
Data Setup Time
2
J.lS
tAH
Address Hold Time
2
J.lS
tOEH
OE Hold Time
2
J.lS
tOH
Data Hold Time
2
J.lS
tOF
Output Enable to Output Float
0
tOE
Output Enable to Output Delay
tpw
Program Pulse Width
tpRT
Program Pulse Rise Time
5
ns
tPFT
Program Pulse Fall Time
5
ns
MIN
45
PROGRAM OPERATION NOTES:
1. Vee must be applied at the same time or before Vpp and removed after or atthe
same time as Vpp. To prevent damage to the device it must not be inserted into a
board with Vpp at 25V.
2. Care must be taken to prevent overshoot of the Vpp supply when switching to
-25V.
3. O.4SV <; VIN <; S.2SV
50
4.
5.
6.
7.
8.
MAX
UNITS
NOTES
130
ns
4
120
ns
4
55
ms
CE/PGM - VIL
CE/PGM - VIH
tT - 20nsec
1V or 2V for inputs and 8V or 2V for outputs are used as timing reference levels.
Although speed selections are made for read operation all programming
specifications are the same for all dash numbers.
MKI INDUSTRIAL HI-REL SCREENING
Figure 3
Package Assembly
Environmental
Electrical
Voltage Stress (DRAMs only)
Burn-in
QA Acceptance
Screen
MIL-STD 883 Method
Reqmt.
Die Inspect
Pre-Seal Inspect
Temperature Cycle
Centrifuge
Fine Leak
Gross Leak
Electrical Screens
75X Mostek Spec.
30X-60X Mostek Spec.
1010 Condo C, 5 Cycles
2001 Condo D, 20Kg Y}
1014 Condo B, 1 X 10- atm cc/sec
Mostek Spec.
5005 Grp. A electrical sub-groups, testing conditions
and limits which guarantee ac, dc and functional
performance over the full temperature range.
1015 Condo D, 10 hrs. min., 125°C
1015 Condo 0,44 hrs. min., 125°C
Fine and gross leak samples
5005 Grp. A sample testing to guarantee
performance to data sheet over full temp. range.
Visual tests to guarantee marking, construction and
mechanical integrity
100"'{'
100%
100%
100%
100%
100%
100%
Hermeticity
Electrical Tests
Visual/Mechanical
lQ()O'{'
lQ()O'{'
.25%AQL
.4%AQL
.65%AQL
LTPD 10
.65%AQL
Solderability
Pre-shipment Inspect
XIV-9
CAPACITANCE
(TA = 25°C) 8
SYM
PARAMETER
TYP
MAX
UNITS
NOTES
CIN
Input Capacitance
4
6
pF
6
COUT
Output Capacitance
8
12
pF
6
READ OPERATION NOTES:
1. Vee must be applied on or before Vpp and removed after or at the same time as
Vpp.
2. Vpp and Vee may be connected together except during programming, in which
case the supply current is the sum of ICC and IpP1.
3. All voltages with respect to VSS.
4. Load conditions :::0 ITIL load and 1COpE, tr =tF - 20n5, reference levels are 1Vand
2V for inputs and .BV and 2V for outputs
5.
tOE is referenced to CE or the addresses, whichever occurs last.
6.
Effective Capacitance calculated from the equation C : : :
~~
where!:::. V ::;: 3V.
7. Typical numbers are for TA = 25°C and VCC = 5.0V.
8. tOF is applicable to both CE and QE, whichever occurs first.
9. DE may follow up to tACC-tOE afterthefalling edge of CE without effecting tACC'
PROGRAM OPERATIONs
RECOMMENDED DC OPERATING CONDITIONS s
(TA = 25°C ± 5°C)(Vee = +5V ± 5%, Vpp = 25V ± 1V)
SYM
PARAMETER
MIN
MAX
UNITS
V IL
Input Low Level
-0.1
0.8
V
V IH
Input High Level
2.0
Vee + 1
V
MIN
MAX
UNITS
NOTES
10
JJA
3
100
mA
DC ELECTRICAL CHARACTERISTICS
(TA = 25°C ± 5°C) (Vee = +5V ± 5%, Vpp = 25V
NOTES
± 1V)
SYM
PARAMETER
IlL
Input Leakage Current
lee
Vee Power Supply Current
IpPl
Vpp Supply Current
10
mA
4
IpP2
Vpp Supply Current during
Programming Pulse
30
mA
5
XIV-10
MOSTEI(.
MILITARYIHIGH-REL PRODUCTS
Extended Temperature, Extended Burn-In Industrial Processing
Z80/Z80A Central Processing Unit
MK13880-70/74
FEATURES
o
44 hr. min., 125°C burn-in plus industrial screening for
greater reliability(see Figure 6for processing description)
o
-4Q°C to 85°C temperature range
o
Two speeds
• 2.5 MHz
• 4.0 MHz
MKI3880(P)-70 (Z80 CPU)
MKI3880(P)-74 (Z80A CPU)
DESCRIPTION
The Mostek Z80 family of components is a significant
advancement in the state-of-art of microcomputers. These
components can be configured with any type of standard
semiconductor memory to generate computer systems with
an extremely wide range of capabilities. For example, as few
as two LSI circuits and three standard TIL MSI packages
can be combined to form a simple controller. With additional
memory and I/O devices, a computer can be constructed
with capabilities that only a minicomputer could deliver
previously. This wide range of computational power allows
standard modules to be constructed by a user that can
satisfy the requirements of an extremely wide range of
applications.
o Single 5-Volt supply and single-phase clock required
o
Software compatible with 8080A CPU
o
Complete development and OEM system product
support
o
Military MKB version available (-55°C/125°C)
o
Typical power 625 mW
specific peripheral device, store it in a location in memory,
check the parity, and write it out to another peripheral
device. Note that the Mostek component set includes the
CPU and various general purpose I/O device controllers, as
well as a wide range of memory devices. Thus, all required
components can be connected together in a very simple
manner with virtually no other external logic. The user's
effort then becomes primarily one of the software
development. That is, the user can concentrate on
describing his problem and translating it into a series of
instructions that can be loaded into the microcomputer
memory. Mostek is dedicated to making this step of
software generation as simple as possible. A good example
of this is our assembly language in which a simple
mnemonic is used to represent every instruction that the
CPU can perform. This language is self-documenting in
such a way that from the mnemonic the user can
understand exactly what the instruction is doing without
constantly checking back to a complex cross listing. Please
refer to the Z80 Data Book for extensive Z80 operation
documentation.
The CPU is the heart of the system. Its function is to obtain
instructions from the memory and perform the desired
operations. The memory is used to contain instructions and,
in most cases, data that is to be processed. For example, a
typical instruction sequence may be to read data from a
ZSO-CPU BLOCK DIAGRAM
ZSO PIN CONNECTIONS
Figure 1
Figure 2
{'"
"...--------,
""'"
""
u:mtl
SYSTEM
CONTROL
RD
RFSii"
Hill
INSTRUCTION
OECODE
iYA1T"
..........
./'-""" _ _ _ / 1 CPU
"
CPU AND
SYSTEM
CONTROL
SIGNALS
CPO
CONTROL
CONTROL
~~
CONTROL
{
iiii't
NMi
.....,.
{""""
BUSAK
.,.
.,.
XIV-11
Z80 CPU
MKI3880(P)-70
MKI3880(P)-74
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ..................................................................... -40°C to +85°C
Storage Temperature .................................................................... " . -65°C to +150°C
Voltage on Any Pin with Respect to Ground ..................................................... -0.3 V to + 7 V
Power Dissipation .................................................................................. 1.5 W
*Stressesabove those listed under "Absolute Maxim'urn Ratings" maycause permanent damage tathe device. This is a stress rating only and functional operation of
the device at these or any other condition above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
(TA ~ -40°C to 85°C, Vee ~ 5 V ± 5% unless otherwise specified)
SYM
PARAMETER
MIN
MAX
UNITS
VILe
Clock Input Low Voltage
-0.3
0.8
V
VIHe
Clock Input High Voltage
V ee-·6
V ee +·3
V
VIL
Input Low Voltage
-0.3
0.8
V
VIH
Input High Voltage
All inputs except NMI
2.4
Vee
V
VIH(NMI)
Input High Voltage (NMI)
2.7
Vee
V
MAX
UNITS
0.4
V
IOL = 1.8mA
V
IOH
= -250 JJA
=o to Vee
TYP
TEST CONDITIONS
DC ELECTRICAL CHARACTERISTICS
(TA = -40°C to 85°C, Vee = 5 V ± 5% unless otherwise specified)
TEST CONDITIONS
SYM
PARAMETER
VOL
Output Low Voltage
V OH
Output High Voltage
Icc
Power Supply Current
200
mA
III
Input Leakage Current
±10
JJA
VIN
ILOH
Tri-State Output Leakage
Current in Float
10
JJA
VOUT = 2.4 to Vee
Tri-State Output Leakage
Current in Float
-10
JJA
VOUT= 0.4V
Data Bus Leakage Current
In Input Mode
±10
JJA
O
te
t.v(cI>H)
tw(cI>L)
tr,f
180
180
[12]
(D)
2000
30
!-,sec
nsec
nsec
nsec
to(AOI
tF(AO)
taem
Address Output Delay
Delay to Float
Address Stable Prior to MREO
(Memory Cycle)
Address Stable Prior to 10RO, RD or
WR (1/0 Cycle)
Address Stable From RD, WR, 10RO
or MREO
Address Stable From RD or WR
During Float
145
110
[1]
nsec
nsec
nsec
[2]
nsec
[3]
nsec
[4]
nsec
Ao-15
tae;
tea
teaf
to(OI
tF(O)
tS(O)
0 0 .7
ts'¥(O)
t dem
tde;
tcdf
tH
tOL(i;(MRI
MRro
tOH(MRI
tOH(ROI
RD
tOL¥(RO)
tOH(ROI
tOH<$(RO)
Period
Pulse Width, Clock High
Pulse Width, Clock Low
Rise and Fall Time
Data Output Delay
Delay to Float During Write Cycle
Data Setup Time to Rising Edge of
Clock During M1 Cycle
Data Setup Time to Falling Edge at
Clock During M2 to M5
Data Stable Prior to WR (Memory
Cycle)
Data Stable Prior to WR (1/0 Cycle)
Data Stable From WR
Input Hold Time
MREO Delay From Falling Edge of
Clock, MREO Low
MREO Delay From Rising Edge of
Clock, MREO High
MREO Delay From Falling Edge of
Clock, MREO High
Pulse Width, MREO Low
Pulse Width, MREO High
10RO Delay From Rising Edge of
Clock, 10RO Low
10RO Delay From Falling Edge of
Clock, 10RO Low
10RO Delay From Rising Edge of
Clock, 10RO High
10RO Delay From. Falling Edge of
Clock, 10RO High
RD Delay From
RD Low
RD Delay From
RD Low
RD Delay From
RD High
RD Delay From
RD High
50
nsec
nsec
nsec
60
nsec
[5]
nsec
[6]
[7]
0
nsec
nsec
nsec
250
90
100
nsec
100
nsec
100
nsec
[8]
[9]
CL = 50pF
Except T3-M 1
CL = 50pF
CL = 50pF
nsec
nsec
90
nsec
110
nsec
100
nsec
110
nsec
Rising Edge of Clock,
100
nsec
Falling Edge of Clock,
130
nsec
Rising Edge of Clock,
100
nsec
Falling Edge of Clock,
110
nsec
XIV-13
TEST CONDITIONS
CL = 50pF
CL = 50pF
AC ELECTRICAL CHARACTERISTICS (Cont.)
(TA = -40°C to 85°C, Vcc = +5 V, ± 5%, unless otherwise noted)
SIGNAL
WR
SYM
PARAMETER
tOL(WR)
WR Delay From Rising Edge of Clock,
WRLow
WR Delay From Falling Edge of Clock,
tOL<$(WRI
tOH(WR)
IW(WRL)
t OL(Ml)
M1
t OH(Ml)
RFSH
tOL(RF)
tOH(RF)
MIN
MAX
UNIT
80
nsec
90
nsec
100
nsec
WR Delay From Falling Edge of Clock,
WR High
Pulse Width, WR Low
[10)
nsec
M1 Delay From Rising Edge of Clock
M1 Low
M1 Delay From Rising Edge of Clock,
M1 High
130
nsec
130
nsec
RFSH Delay From Rising Edge of Clock,
RFSH Low
RFSH Delay From Rising Edge of Clock
RFSH High
180
nsec
150
nsec
CL = 50pF
CL = 30pF
tS(WT)
WAIT Setup Time to Falling Edge of
Clock
HALT
to(HT)
HALT Delay Time From Falling Edge
of Clock
INT
ts(IT)
INT Setup Time to Rising Edge of Clock
80
nsec
NMI
tw{NML)
Pulse Width, NMI Low
80
nsec
BUSRO
ts(BQ)
BUSRO Setup Time to Rising Edge of
Clock
80
nsec
BUSAK
tOL(BA)
BUSAK Delay From Rising Edge of
Clock, BUSAK Low
BUSAK Delay From Falling Edge of
Clock, BUSAK High
RESET
120
nsec
110
nsec
CL = 50pF
CL = 50pF
tF(C)
Delay to/from Float (MREO, IORO,
RD andWRI)
tmr
M 1 Stable Prior to IORO (Interrupt Ack.)
nsec
90
80
NOTES:
[11)
[11]
[12]
A. Data should be enabled onto the CPU data bus when RD is active. During
interrupt acknowledge data should be enabled when M1 and IORO are both
'w
nsec
300
RESET Setup Time to Rising Edge of
Clock
active.
B. The RESET signal must be active for a minimum of 3 clock cycles.
C. Output Delay VS. Load Capacitance
TA =85°e Vee = 5V ± 5%
Add 10 nsec delay for each 50pF increase in load up to a maximum of 200pF for
the data bus and 1OOpF for address and control lines.
D. Although static by design, testing guarantees tw (4)H) of 200 /Lsec maximum.
[1]
laern = Iw (
Ao-15
SYM
PARAMETER
MIN
MAX
UNIT
te
tw(H)
tw(L)
tr,f
Clock
Clock
Clock
Clock
.25
110
110
[12]
(D)
2000
30
,.,sec
nsec
nsec
nsec
tD(AD)
tF(AD)
taem
Address Output Delay
Delay to Float
Address Stable Prior to MREO
(Memory Cycle)
Address Stable Prior to 10RO, RD or
WR (I/O Cycle)
Address Stable From RD, WR, 10RO
or MREO
Address Stable From RD or WR
During Float
110
90
[1]
nsec
nsec
nsec
[2]
nsec
[3]
nsec
[4]
nsec
taei
tea
teaf
tD(D)
tF(D)
tS(D)
DO_7
tS~(D)
tdem
t dei
tedf
tH
tDL~(MR)
MREO
tDH(MR)
tDH~(MR)
tw(MRL)
tw(MRH)
tDL(IR)
tDLij;(IR)
10RO
tDH;j;(IR)
tDH(IR)
tDL(RD)
RD
tDLij;(RD)
tDH(RD)
tDH¥(RD)
Period
Pulse Width, Clock High
Pulse Width, Clock Low
Rise and Fall Time
Data Output Delay
Delay to Float During Write Cycle
Data Setup Time to Rising Edge of
Clock During M1 Cycle
Data Setup Time to Falling Edge at
Clock During M2 to M5
Data Stable Prior to WR (Memory
Cycle)
Data Stable Prior to WR (I/O Cycle)
Data Stable From WR
Input Hold Time
MREO Delay From Falling Edge of
Clock, MREO Low
MREO Delay From Rising Edge of
Clock, MREO High
MREO Delay From Falling Edge of
Clock, MREO High
Pulse Width, MREO Low
Pulse Width, MREO High
IORO Delay From Rising Edge of
Clock, 10RO Low
10RO Delay From Falling Edge of
Clock, 10RO Low
IORO Delay From Rising Edge of
Clock, 10RO High
10RO Delay From Falling Edge of
Clock, 10RO High
RQ.Pelay From
RD Low
RD Delay From
RD Low
RD Delay From
RD High
RD Delay From
RD High
170
90
35
nsec
nsec
nsec
50
nsec
[5]
nsec
[6]
[7]
0
nsec
nsec
nsec
20
85
nsec
85
nsec
85
nsec
CL = 50pF
Except T3-M1
CL = 50pF
CL = 50pF
nsec
nsec
[8]
[9]
75
nsec
85
nsec
85
nsec
85
nsec
Rising Edge of Clock,
85
nsec
Falling Edge of Clock,
95
nsec
Rising Edge of Clock,
85
nsec
Falling Edge of Clock,
85
nsec
XIV-15
TEST CONDITIONS
CL = 50pF
CL = 50pF
II
AC ELECTRICAL CHARACTERISTICS (Cont.)
(TA = -40°C to 85°C, V cc = +5 V, ± 5%, unless otherwise noted)
SIGNAL
WR
SYM
PARAMETER
tOL(WR)
WR Delay From Rising Edge of Clock,
WRLow
WR Delay From Falling Edge of Clock,
WRLow
WR Delay From Falling Edge of Clock,
WR High
Pulse Width, WR Low
tOL(WR)
tOH(WR)
tw(WRL)
t Ol(Ml )
Ml
t OH(Ml)
RFSH
tOl(RF)
tOH(RF)
MIN
MAX
UNIT
65
nsec
80
nsec
80
nsec
[10]
Ml Delay From Rising Edge of Clock
Ml Low
Ml Delay From Rising Edge of Clock,
Ml High
100
nsec
100
nsec
130
nsec
120
nsec
CL = 50pF
RFSH Delay From Rising Edge of Clock,
RFSH Low
RFSH Delay From Rising Edge of Clock
RFSH High
CL = 50pF
tS(WT)
WAIT Setup Time to Falling Edge of
Clock
HALT
to(HT)
HALT Delay Time From Falling Edge
of Clock
INT
ts(IT)
INT Setup Time to Rising Edge of Clock
80
nsec
NMI
tw(NML)
Pulse Width, NMI Low
80
nsec
BUSRO
ts(BQ)
BUSRO Setup Time to Rising Edge of
Clock
50
nsec
BUSAK
tOl(BA)
BUSAK Delay From Rising Edge of
Clock, BUSAK Low
BUSAK Delay From Falling Edge of
Clock, BUSAK High
RESET
nsec
70
300
nsec
100
nsec
100
nsec
CL = 50pF
CL = 50pF
ts(RS)
RESET Setup Time to Rising Edge of
Clock
tF(C)
Delay to/From Float (MREO, IORO,
RDandWR)
tmr
Ml Stable Prior to IORO (Interrupt Ack.)
nsec
60
80
NOTES.
A. Data should be enabled onto the CPU data bus when AD is active. During
interrupt acknowledge data should be enabled when M1 and IORO are both
active,
B. The RESET signal must be active for a minimum of 3 clock cycles.
C. Output Delay vs. Load Capacitance
TA = 85'e Vee = 5V ± 5%
Add 10 nsec delay for each 50pF increase in load up to a maximum of 200pF for
the data bus and 100pF for address and control lines.
D. Although static by design, testing guarantees tw (H) of 200 J.tsec maximum
[1]
laem =Iw (HI + If -65
[2]
laei =Ie -70
[3]
lea =Iw (LI + Ir -50
[4]
leaf = Iw (LI + Ir -45
[5]
Idem =Ie -170
[6]
Idei =Iw(LI + Ir -170
[7]
Icdt = Iw (LI + Ir -70
[8]
Iw (liifltLl = Ie -30
[9]
Iw (MRHI = Iw (HI + If -40
CL = 50pF
nsec
WAIT
tOH(BA)
TEST CONDITIONS
[11]
[10]
[11]
[12]
nsec
nsec
Iw (WRI = Ie -30
Imr = 21e + Iw (HI + If -65
Ie =Iw (HI + Iw (LI + Ir + If
LOAD CIRCUIT FOR OUTPUT
Figure 4
TEST POINT
FROM OUTPUT
UNDER TEST --r----t----K
XIV-16
R,-2.1Kll
CAPACITANCE
TA = 25°C, f = 1 MHz
SYM
PARAMETER
MAX
UNIT
TEST CONOITIONS
C
Clock Capacitance
35
pF
Unmeasured Pins
CIN
Input Capacitance
5
pF
Returned to Ground
COUT
Output Capacitance
10
pF
AC TIMING DIAGRAM
Figure 5
Timing measurements are made at the following voltages, unless otherwise specified.
=y..H-_-_-__
CLOCK
OUTPUT
INPUT
FLOAT
NMI
"1 "
Vee -.6
2.0V
2.4V
;:, V
2.7V
"0"
.BV
.BV
.BV
±05V
~O}
A o_1s
-_-tt----_-_-_-1_k./ ''---H------t-----j-,/}< ___ _
---- ~;.'~~-- f--~---
--
IN
°0_7
'0'0'
{
M1
-
""-
~DH'R.r")'r-'
1,,'_DL_'M_1)-tt__
1----- --
---
~---
tOLIRFJ_
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-- 'w,mF:l
RD
'DHirR'-
D.±-
_ _ _..,."
tOL (RD)
tOH4>(RDI-
;Jr--+l--t---t-+-..,
/'t--f--tt--i1
tOH'iIROI-
I
_tn;
----+---1+-----1-1----++--+---1-1---++--"'"'-
'URJ
I
IORQ----II--.-m'---+l-~" 'DHOIIR,- }Ir--++--+----++-,.+-;
_ ___
);~t ~ ~'C'
l't-;:.DO'"L~!-,'W:::"R:l'ft--
tOl$I!Rl
,
r--
_ - vt--+-tt--tt-'H-t+t.l.l 'FlO}
._DH_'M_'_'_-t1,. . /~/I-
OUT
,
-
rr ..__.r-
h,_ __
tOH4>[WR)
-
'Dii"RI- kh"._.r-
~IROltOH4>IRO'"
Ro----tt------t~~--+--++--..
II
1-:
,rh,.
.OL.,W:::R:;-,...~ft--+'Pk
~
'"
iNA
NMi
~ 5-
h ..
_.r-
tdci
:::_________F '"k--__
INT
tOH4>IWR)-
_.r-
'''"'::J
----------------'>C -Y-'---~---
_________________'_W'_NML_"'__
~~___________....·t=-~
____~
BUSRQ
tOHI8AI
tOlISA)
BUSAK
RESET
____________
~DS(RSI
tH
, -_ ___
____ I
"
,
_______ _
XIV-17
II
MKI INDUSTRIAL HI-REL SCREENING
Figure 6
Screen
MIL-STD 883 Method
Reqmt.
Die Inspect
Pre-Seal Inspect
75X Mostek Spec.
30X-60X Mostek Spec.
100%
100%
Environmental
Temperature Cycle
Centrifuge
Fine Leak
Gross Leak
1010 Condo C, 5 Cycles
2001 Condo D, 20Kg Yj
1014 Condo B, 1 X 10' atm cc/sec
Mostek Spec.
100%
100%
100%
100%
Electrical
Electrical Screens
5005 Grp. A electrical sub-groups, testing conditions and limits which guarantee ac, dc and
functional performance over the full
temperature range.
100%
Voltage Stress (DRAMs only)
1015 Condo D, 10 hrs. min., 125°C
100%
Burn-in
1015 Condo D, 44 hrs. min., 125°C
100%
Fine and gross leak samples
5005 Grp. A sample testing to guarantee
performance to data sheet over full temp. range.
Visual tests to guarantee marking, construction
and mechanical integrity
.25%AOL
.4%AOL
Package Assembly
QA Acceptance
Hermeticity
Electrical Tests
Visual/Mechanical
Solderabil ity
Pre-shipment Inspect.
.65%AOL
LTPD 10
.65%AOL
XIV-18
MOSfEI{.
MILITARYIHIGH-REL PRODUCTS
Extended Temperature, Extended Burn-in Industrial Processing
Parallel 1/0 Controller
MKI3881'-70/74
FEATURES
DESCRIPTION
o Two independent 8 bit bidirectional peripheral interface
ports with 'handshake' data transfer control
The Z80 Parallel 1/0 Circuit is a programmable, two port
device which provides a TTL compatible interface between
peripheral devices and the Z80-CPU. The CPU can
configure the Z80-P10 to interface with a wide range of
peripheral devices with no other external logic required.
Typical peripheral devices that are fully compatible with the
Z80-P10 include most keyboards, paper tape readers and
punches, printers, PROM programmers, etc. The Z80-P10
utilizes N channel silicon gate depletion load technology
and is packaged in a hermetic 40 pin DIP.
o
Interrupt driven 'handshake' for fast response
o
Anyone of four distinct modes of operation may be
selected for a port including:
• Byte output
• Byte input
• Byte bidirectional bus (Available on Port A only)
• Bit control mode
All with interrupt controlled handshake
o
Daisy chain priority interrupt logic included to provide for
automatic interrupt vectoring without external logic
o
Eight outputs are capable of driving Darlington
transistors
o
-40°C to +85°C operating range
o 44 hour Mil Spec burn in
o
MKB3881 available for military requirements per
MIL-STD-883B
o
Typical ordering: MKI3881 P-70
MKI3881 P-74
2.5 MHz Z80-P10
4.0 MHz Z80-P10
PIO BLOCK DIAGRAM
C'"
INTERFACE
One of the unique features of the Z80-P10 that separates it
from other interface controllers is that all data transfer
between the peripheral device and the CPU is accomplished
under total interrupt control. The interrupt logic of the Pia
permits full usage ofthe efficient interrupt capabilities ofthe
Z80-CPU during 1/0 transfers. All logic necessary to
implement a fully nested interrupt structure is included in
the Pia so that additional circuits are not required. Another
unique feature of the Pia is that it can be programmed to
interrupt the CPU on the occurrence of specified status
conditions in the peripheral device. For example, the Pia
can be programmed to interrupt if any specified peripheral
alarm conditions should occur. This interrupt capability
reduces the amount of time that the processor must spend
in polling peripheral status.
PIO PIN CONFIGURATION
PERIPHERAL
INTERFACE
,~,".""{,,,,..~ ::
C""TROL
INTENA,:'.'i:'22
17l9'1J
'----~
XIV-19
XIV·20
MOSTEI{.
MILITARYIHIGH-REL PRODUCTS
Extended Temperature, Extended Burn-in Industrial Processing
Counter Timer Circuit
MKI3882 (P/J)-70/74
FEATURES
DESCRIPTION
o Each channel may be selected to operate in either
Counter Mode or Timer Mode
The l80-Counter Timer Circuit (CTC) is a programmable
component with four independent channels that provide
counting and timing functions for microcomputer systems
based on the l80-CPU. The CPU can configure the CTC
channels to operate under various modes and conditions as
required to interface with a wide range of devices. In most
applications, little or no external logic is required. The l80CTC utilizes N-channel silicon gate depletion load
technology and is packaged in a 28-pin DIP. The l80-CTC
requires only a single 5 volt supply and a one-phase 5 volt
clock.
o Used in either mode, a CPU-readable Down Counter
indicates number of counts-to-go until zero
o A Time Constant Register can automatically reload the
Down Counter at Countlero in Counter and Timer Mode
o Selectable positive or negative trigger initiates time
operation in Timer Mode. The same input is monitored
for event counts in Counter Mode
o Three channels have lero Count/Timeout outputs
capable of driving Darlington transistors
o Interrupts may be programmed to occur on the zero
count condition in any channel
o
Daisy chain priority interrupt logic included to provide for
automatic interrupt vectoring without external logic
o -40°C to +85°C operating range
o 44 hour Mil Spec burn in
o MKB3882 available for military requirements per
MIL-STD-883B
o Typical ordering: MK13882P-70
MK13882P-74
A block diagram of the l80-CTC is shown in the figure. The
internal structure ofthe l80-CTC consists of a l80-CPU bus
interface, I nterna I Control Log ic, fou r sets of Counter/Timer
Channel Logic, and Interrupt Control Logic. The four
independent counter/timer channels are identified by
sequential numbersfromOto 3. The CTC hasthe capability
of generating a unique interrupt vector for each separate
channel (for automatic vectoring to an interrupt service
routine). The 4 channels can be connected into four
contiguous slots in the standard l80 priority chain with
channel number 0 having the highest priority. The CPU bus
interface logic allows the CTC device to interface directly to
the CPU with no other external logic. However, port address
decoders and/or line buffers may be required for large
systems.
2.5 MHzl80-CTC
4.0 MHz l80-CTC
ZBO-CTC BLOCK DIAGRAM
ZBO-CTC PIN CONFIGURATION
ZERO COUNTI
TIMEOUT 0
CLOCK/TRIGGER 0
ZEROCOUNTI
nMEOUT1
CLOCK/TRIGGER 1
ZEROCOUNTI
TIMEOUT 2
CLOCK/TRIGGER 2
--1
-1
".
cs,'i
.-
,~."" {,~'NTEN"'~""
COOlfAOL
.~
XIV-21
"'elK/TRIl,
XIV-22
MOSTEI{®
MILITARYIHIGH-REL PRODUCTS
Extended Temperature, Extended Burn-In Industrial Processing
16,384 X 1-Bit Dynamic RAM
MKI4116(J)-72/73/74
FEATURES
o Low power: 462 mW active, 30 mW standby (max)
o
o
Output data controlled by CAS and unlatched at end of
cycle to allow two dimensional chip selection and
extended page boundary
o
Common 1/0 capability using "early write" operation
o
Read-modify-write, RAS-only refresh, and page-mode
capability
o
All inputs TIL compatible, low capacitance, and
protected against static charge
o
128 refresh cycles (2 msec refresh interval)
o
MKB military version available (-55 to 110°C)
Extended operating temperature range (-40°C :S TA :S
+85°C)
o 44 hr. min., 125°C burn-in plus industrial screening for
greater reliability(see Figure 3 for processing description)
o
Recognized industry standard 16-pin configuration from
Mostek
o
150 ns access time, 320 ns cycle (MKI4116-72)
200 ns access time, 375 ns cycle (MKI4116-73)
250 ns access time, 410 ns cycle (MKI4116-74)
o ± 10"10 tolerance on
all power supplies (+12 V,
± 5 V)
The MKI4116 is a new generation MOS dynamic random
access memory circuit organized as 16,384 words by 1 bit.
As a state-of-the-art MOS memory device, the MKI4116
(16K RAM) incorporates advanced circuit techniques
designed to provide wide operating margins, both internally
and to the system user, while achieving performance levels
in speed and power previously seen only in Mostek's high
performance MK4027 (4K RAM).
The technology used to fabricate the MKI4116 is Mostek's
double-poly, N-channel silicon gate, POLY ITM process. This
process, coupled with the use of a single transistor dynamic
storage cell, provides the maximal circuit density and
reliability, while maintaining high performance capability.
The use of dynamic circuitry throughout, including sense
amplifiers, assures that power dissipation is minimized
without any sacrifice in speed or operating margin. These
factors combine to make the MKI4116 a truly superior RAM
product.
BLOCK DIAGRAM
PIN CONNECTIONS
Figure 1
Figure 2
DESCRIPTION
VBB 1
_VOl>
--'"
16 vss
__
vv.s
..
_
D'N
2
15 CAS
WRITE
3
Ao
5
14
13
12
A2
6
11 A4
RAS 4
'.-----1
A, 7
,,-----I
'.-----1
10
voo 8
'. - - - - - I ."
'. _ _---IA~~pRjTSS
" _ _---I BU~~~RS
,,-----I
DOUT
A6
A3
As
9 vee
PIN NAMES
AD - A6 Address Inputs
CAS
Col. Address Strobe
Data In
D'N
~T Data Out
RAS
Row Address Strobe
XIV-23
WR E
V BB
Vee
Voo
Vss
Read/Write Input
Power (-5V)
Power (+5V)
Power (+12V)
Ground
ABSOLUTE MAXIMUM RATINGS*
Voltage on any pin relative to Vss ............................................ , ................ -0.5 V to +20 V
Voltage on Voo. VCC supplies relative to V ss .........................•......•................. -1.0 V to + 15.0 V
Vss - Vss (V OD - Vss > 0 V) .................... ", ......................•...............................• OV
Operating Temperature, TA (Ambient) ....•.........................................•........... -40°C to +85°C
Storage Temperature (Ambient) .............................................................. -65°C to +150°C
Short Circuit Output Current ......................................................................... 50 mA
Power Dissipation ...............................................................•.................. 1 Watt
*Stresses greater than 'those listed under "Absolute Maximum Ratings" may cause permanent damage to the device, This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS6
(-40°C S TAS +85°C)
SYM
PARAMETER
MIN
TYP
MAX
UNITS
NOTES
VOO
Supply Voltage
10.8
12.0
13.2
V
2
Vcc
Supply Voltage
4.5
5.0
5.5
V
2,3
VSS
Supply Voltage
0
0
0
V
2
-4.5
-5.0
-5.5
V
2
Vss
Supply Voltage
V IHC
Input ~ (Logic 1) Voltage,
RAS, CAS, WRITE
2.7
-
7.0
V
2
V IH
Input High (Logic 1) Voltage, all
inputs except RAS, CAS, WRITE
2.4
-
7.0
V
2
Input Low (Logic 0) Voltage, all
inputs
-1.0
-
.8
V
2
MAX
UNITS
NOTES
35
mA
4
5
400
pA
2.25
10
200
mA
27
10
mA
V IL
DC ELECTRICAL CHARACTERISTICS
(_40DC S TA S +85°C) (Voo = 5.0 V ± 10"16; -5.5 V S VSS S -4.5 V; Vss
SYM
PARAMETER
1001
ICCl
ISSl
OPERATING CURRENT
Average power supply operating current
(RAS, CAS cycling; t RC = t RC (min)
1002
ICC2
ISS2
STANDBY CURRENT
Power supply standby current (RAS
DOUT = High Impedance)
1003
ICC3
ISS3
REFRESH CURRENT
Average power supply current, refesh mode
(RAS cycling. CAS = V IH6 t RC =t RC min)
1004
ICC4
ISS4
PAGE MODE CURRENT
Average power supply current, page-mode
operation (RAS = V IL, CAS cycling;
tpc = tpc min)
=0 V)
MIN
= V IHC'
-10
-10
pA
pA
400
pA
pA
27
mA
400
pA
IIIL)
INPUT LEAKAGE
Input leakage, any input (Vss = -5 V, 0 V S VIN
S +7.0 V. all other pins not under test = 0 volts)
-10
10
pA
IO(L)
OUTPUT LEAKAGE
Output leakage current (DOUT is disabled,
VS VOUTS +5.5 V)
-10
10
pA
0.4
V
V
4
4
5
o
V OH
VOL
OUTPUT LEVELS
Output high (Logic 1) voltage (lOUT = -5 mAl
Output low (Logic 0) voltage (lOUT = 4.2 mAl
XIV-24
2.4
3
\
RECOMMENDED AC OPERATING CONDITIONS AND ELECTRICAL CHARACTERISTICS(6?,8)
(Voo = 12.0V± 10%; VCC = 5.0V± 10%, VSS = OV, -5.5 V~VBB~-4.5 V)
(-40°C~TA~85°C)1
SYM PARAMETER
MK14116-72
MK14116-73
MK14116-74
MIN
MIN
MIN
MAX
MAX
MAX
UNITS
NOTES
320
375
410
ns
9
t AWC Read-write cycle time
320
375
425
ns
9
tAMW Read-modify-write cycle time
320
405
500
ns
9
tpc
Page mode cycle time
170
225
275
ns
9
t RAC
Access time from
RAS
150
200
250
ns
10,12
tCAC
Access time from CAS
100
135
165
ns
11,12
tOFF
Output buffer turn-off delay
0
40
0
50
0
60
ns
13
tT
Transition time (rise and fall)
3
35
3
50
3
50
ns
8
tAP
RAS precharge time
100
t AAS
RAS pulse width
150
t AsH
RAS hold time
100
tCSH
CAS hold time
150
tCAS
CAS pulse width
100
5000
135
5000
165
5000
ns
tACO
RAS to CAS delay time
20
50
25
65
35
85
ns
!cAP
CAS to RAS precharge time
0
0
0
ns
tASA
Row Address set-up time
0
0
0
ns
tRAH
Row Address hold time
20
25
35
ns
t ASC
Column Address set-up time
0
0
0
ns
tCAH
Column Address hold time
45
55
75
ns
tAA
Column Address hold time
referenced to RAS
95
120
160
ns
t ACS
Read command set-up time
0
0
0
ns
t AC
Random read or write cycle time
120
5000
200
150
5000
135
250
ns
5000
165
ns
250
200
ns
ns
0
0
0
ns
t WCH Write command hold time
45
55
75
ns
t WCA Write command hold time
referenced to RAS
95
120
160
ns
tACH
Read command hold time
15
twp
Write command pulse width
45
55
75
ns
t AWL
Write command to RAS lead time
50
70
85
ns
tCWL
Write command to
CAS lead time
50
70
85
ns
tos
Data-in set-up time
0
0
0
ns
15
tOH
Date-in hold time
45
55
75
ns
15
tOHA
Data-in hold time referenced
toRAS
95
120
160
ns
tcp
CAS precharge time (for page-mode
cycle only)
60
80
100
ns
XIV-25
1:1
RECOMMENDED ACOPERATINGCONDITIONS AND ELECTRICAL CHARACTERISTICS (Cont.)(6,1,8)
(-40°C :s TA:S +85°C)' (V DD := 12.0 V ± 10"10; Vee = 5.0 V ± 10%, V55 = 0 V, -5.5 V :s VBB :s -4.5 V)
MK14116-72
MIN
SYM PARAMETER
tREF
MK14116-73
MIN
MAX
MIN
2
2
Refresh period
MAX
MK14116-74
MAX UNITS
2
NOTES
ms
19
twe5 WRITE command set-up time
0
0
0
ns
16
tewD CAS to WRITE delay
60
80
90
ns
16
t RWD RAS to WRITE delay
110
145
175
ns
16
CAPACITANCE
(-40°C :s TA:S +85°C) (V DD = 12.0 V
± 10%; V 55 := 0 V; -5.5 V :s VBB :s -4.5 V)
SYM PARAMETER
TYP
MAX
UNITS NOTES
CI1
Input Capacitance (Ao - A 6 ), DIN
4
5
pF
17
CI2
Input Capacitance, RAS, CAS, WRITE
8
10
pF
17
Co
Output Capacitance (OOUl)
5
7
pF
17,18
NOTES:
1. TA is specified here for operation at frequencies to tRC 2: tRC (min).
Operation at higher cycle rates with reduced ambient temperatures and
higher power dissipation is permissible, however, provided AC operating
parameters are met.
2. All voltages referenced to VSS.
3. Qutputvoltage will swing from VSS toVccwhen activated with nocurrent
loading. For purposes of maintaining data in standby mode, Vee may be
reduced to VSS without affecting refresh operations or data retention.
However, the VOH (min) specifications is not guaranteed in this mode.
4. 100l' 1003. and 1004 depend on cycle rate. See Figures 2.3 and 410r 100
limits at other cycle rates.
5. ICCl and ICC4 depend upon output loading. During readout of high level
data VCC is connected through a low impedance (135 ntyp)toaata out.At
all other times ICC consists of leakage currents only.
6. Several cycles are required after power-up before proper device operation
is achieved. Any 8 cycles which perform refresh are adequate for this
purpose.
7. AC measurements assume tr = 5 ns.
8. VIHc(min) or VIL (max) are reference levels for measuring timing of input
signals. Also, transition times are measured between VIHC or VIH or VIL.
9. The specifications for tRC (min)tRMW(min) are used only to indicate cycle
which proper operation over the full temperature range (-40°C::; TA :::;
85"C) is assured.
DESCRIPTION (Continued)
Multiplexed address inputs (a feature pioneered by Mostek
for its 4K RAMs) permits the MKI4116 to be packaged in a
standard 16-pin DIP. This recognized industry standard
package configuration, while compatible with widely avail-
10.
11.
12.
13.
14.
15.
16.
17.
18.
Assumes that tRCD ::; tRCD (max). If tRCD is greater than the maximum
recommended value shown in this table, tRCD will increase by the amount
that tRCO exceeds the value shown.
Assumes that tRCD 2:" tRCD (max)
Measured with a load equivalent to 2 TTL loads and 1(;OpF.
tOPI (r'!lax) defines the time at which the output achieves the open cirCUit
condition and is not referenced to output voltage levels.
Operation within the tRCO (max) limit insures that tRAC (max) can be met
tRCO (max) is specified as a reference point only, iftRCP is greater than the
specified tRCD (max) limit, then access time is controlled exclusively by
tCAC'
These parameters are referenced to CAS leading edge in early write cycles
and to WRITE leading edge in delayed write or read-modify-write cycles.
twcs, tCWD, and tRWO are restrictive operating parameters in read-write
and read-modify-write cycles only. If twcs $twcs (min), the cycle is an
early write cycle and the data out pin will remain open circuit (high
impedance) throughout the entire cycle .. lf tCWD::; tewD (min) and tRWD
$ tRWD (min), the cycle is a read-write cycle and the data out will contain
data read from the selected cell. If neither of the above sets of conditions is
satisfied the condition of the data out (at access time) is indeterminate.
Effective capacitance calculated from the equation C =~with t.:.V = 3
volts and power supplies at nominal levels.
f::::.V
CAS = VIHC to disable 00UT
able automated testing and insertion equipment, provides
highest possible system bit densities and simplifies system
upgrade from 4K to 16K RAMs for new generation applications. Non-critical clock timing requirements allow use of
the mUltiplexing technique while maintaining high
performance.
XIV-26
I!
UNITED
TECHNOLOGIES
MOSTEK
Mostek Corporation, 1 215 West Crosby Rd .
Carrollton, Texas 75006 USA; (214) 323 -6000
In Europe, Contact Mostek Brussels
270-272 Avenue de Tervuren (BTE21)
B-1150 Brussels, Belgium; Telephone: 762 .18.80
PRINTED IN USA May 1982
Copyright 1982 by Mostek Corporation
All rights Rese rved
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