1982_Mostek_Telecommunications_Data_Book 1982 Mostek Telecommunications Data Book
User Manual: 1982_Mostek_Telecommunications_Data_Book
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REPRESENTED BY
CARLSON ELECTRONIC SALES CO.
l :)R-:-HSR OOK EXECUTIVE CTR.
10701 WEST NORTH AVENUE
MILWAU K EE, WISCONSIN 53226
414 476-2790
1982
TELECOMMUNICATION
PRODUCTS DATA BOOK
Copyright © 1981 Mostek Corporation (All rights reserved)
Trade Marks Registered ®
The "PRODUCT PROFILE" designation on a Mostek literature item indicates that the product is not available as of the print
date of this document and that the specification goals have not yet been fully established. The PRODUCT PROFILE is an initial
disclosure of a new product's features and general information. The information given in the PRODUCT PROFILE is subject
to change and is not guaranteed. Mostek Corporation or an authorized sales representative should be consulted for current
information before using this product. No responsibility is assumed by Mostek for its use; nor for any infringements of
patents and trademarks or other rights of third parties resulting from its use. No license is granted under any patents, patent
rights, or trademarks of Mostek. Mostek reserves the right to make changes in the product at any time and without notice.
".
l
The "TARGET SPECIFICATION" designation on a Mostek data sheet indicates that the product is not yet available. The
TARGET SPECIFICATION is an initial disclosure of specification goals for the product. The specifications are subject to
change, are based on design goals, and are not guaranteed. Mostek Corporation or an authorized sales representative
should be consulted for current information before using this product. No responsibility is assumed by Mostek for its use; nor
for any infringements of patents and trademarks or other rights of third parties resulting from its use. No license is granted
under any patents, patent rights, or trademarks of Mostek. Mostek reserves the right to make changes in specifications at
any time and without notice.
The "PRELIMINARY" designation on a Mostek data sheet indicates that the product is not characterized. The specifications
are subject to change, are based on design goals or preliminary part evaluation, and are not guaranteed. Mostek Corporation
or an authorized sales representative should be consulted for current information before using this product. No responsibility
is assumed by Mostek for its use; norfor any infringements of patents and trademarks or other rights ofthird parties resulting
from its use. No license is granted under any patents, patent rights, or trademarks of Mostek. Mostek reserves the right to
make changes in specifications at any time and without notice.
The "APPLICATION BRIEF" or "APPLICATION NOTE" designation on a Mostek literature item indicates that the literature
item contains information regarding Mostek product features and/or their varied applications. The information given in the
APPLICATION BRIEF or APPLICATION NOTE is believed to be accurate and reliable; however, the information is subject to
change and is not guaranteed. No responsibility is assumed by Mostek for its use; nor for any infringements of patents and
trademarks or other rights of third parties resulting from its use. No license is granted under any patents, patent rights, or
trademarks of Mostek.
Mostek reserves the right to make changes in specifications at any time and without notice. The information furnished by
Mostek in this publication is believed to be accurate and reliable. However, no responsibility is assumed by Mostek for its use;
nor for any infringements of patents or other rights of third parties resulting from its use. No license is granted under any
patents or patent rights of Mostek.
PRINTED IN USA December 1981
1982 TELECOMMUNICATION PRODUCTS DATA BOOK
1982 TELECOMMUNICATION PRODUCTS DATA BOOK
TABLE OF CONTENTS
I - Table of Contents
Functional Index ........................•.••.....••..•....•...•...•...•.....•••••...•••.•. I-i
Numerical Index ............................•.....•...••...•.................•••••..••••.• I-iii
II - Telecommunications
Introduction to Telecommunication Products ..••.••..•••••....••.•...•••..•......•.........•. II-i
Telecommunications Terms Application Brief ...•..•..•••.•..•.••.•...••...•......••.•••..••• II-iii
Definitions of Data Sheet Designations •...••....•...•.....•.........•...........••.•••..••• II-vii
Order Information .....•..•.....••.•.....•..•.•...•••...••.•..••..••...•.....•.•.•...•.•. II-ix
Package Descriptions ••••.•...•.••.•..•.....•.••...••••..•••..••..•••..•.....•••......... II-xi
III - General Information
Mostek Profile •.•........•......•.•..............•..........................•••....•••••• III-i
U.S. and Canadian Sales Offices. . • . . . . . . . • • . . . . • . . . . . . . . . • • . . . . . • . . . . . • . . . . . . . . . • . • . . . • . .. III-v
U.S. and Canadian Representatives ..•..•.••.•..•.......•..•.....•..••...•...............•. III-vi
U.S. and Canadian Distributors. . . • • . • . . . . • • . • • . • • . . • • • . • . • . . • . . • • . . • • . . • • . . . . . • . . • • . . . . .. III-vii
International Marketing Offices ••.••.•..•..•..•.••..•••.•..•.••.....••....•....••..••.....• III-ix
IV - Integrated Tone Dialers
MK5087 Integrated Tone Dialer ......•.....•.••.••...•••..•.•••.•...•••..•......••.•••..••. IV-1
MK5089 Integrated Tone Dialer .....•..•....••.••..•••••..•.••.•....••..•......••••••..••• IV-7
MK5087/89 Electronic Drive Application Brief ..••••..•••.•.••.•..••..•••.••.....•.•••....•• IV-13
MK5091 Integrated Tone Dialer .............••.•...•••••.•.....•.....•..•.....•..••..•.•• IV-15
MK5092 Integrated Tone Dialer •.•.................................•....•.......••..•.••• IV-21
MK5094 Integrated Tone Dialer •••..•....••.•..•............•......••...•......•......... IV-29
MK5380 Integrated Tone Dialer •••..•.•..••.••.••..••••••••.•..•...•••..•.....••••..••.•• IV-37
MK5382 Integrated Tone Dialer With Redial .••••..•..•••••.••.•..••..••...•.....•.••...•••• IV-45
Integrated Dialer Comparison - Tone II vs Tone III Application Brief .......•••..•.....•.••...•.•• IV-47
Loop Simulator Application Brief •••.......••.••.••..•••••.•••••.•..••••..•.....•..•...•••• IV-49
V - Integrated Pulse Dialers with Redial
MK50981 Integrated Pulse Dialer with Redial ...•....•••.••••....••••...................•... V-1
MK50982 Integrated Pulse Dialer with Redial ...•.•..•••.•....•..••......................... V-7
MK50991 Integrated Pulse Dialer with Redial ........•.•.................•................. V-13
MK50992 Integrated Pulse Dialer with Redial ...••...••..••••.•..••••...••••...•........... V-19
Current Sources Application Brief ...•••..•••••••...••••.•••..•..•••...••..•....••......... V-25
Pulse Dialer Comparison Application Brief .••••••...••••.•.••.•..•..••..••.....••.......••• V-27
VI - Repertory Dialers
MK5170 Repertory Dialer .•...••..•.•...•••••.•.. '.' .....••••..•..••••••.....••..•...•.••. VI-1
MK5175 Ten-Number Repertory Dialer •..•••••••.•.••••.••••.•..••..••...•....••......•••• VI-19
VII - Integrated Tone Decoders
MK51 02-5 Integrated Tone Receiver •......•.....•..•••......•••....•.•..•......•......... VII-1
MK51 02-5 DTMF Decoder Application Note ....•.••...........•••......•..•......•......... VII-5
MK5102/S3525A DTMF Receiver System Application Brief •...•••••...•.•..•....••••..••... VII-15
MK51 03-5 Integrated Tone Decoder .•.....•.•.......•••.....••••..•..•.......•.•........ VII-17
DTMF Receiver System Application Brief ••..••.••...•••..••••.••.••..•••..•..........••..• VII-23
I-i
VIII - Active Speech Networks
MK5242 Active Speech Network ..................................•.......•........•..... VIII-1
IX - CODECs
MK5116 1L-255 Law Companding CODEC ............•... : •.•........•.•.........•......... IX-1
MK5151 1L-255 Law Companding CODEC .••........•.............•...•........•.•....••.. IX-11
MK5156 A-Law Companding CODEC .....•.........•.........•....•..•.......•••.•...••.. IX-23
MK5316 Companding CODEC with Filters ...........•.............••...........•..•...••.. IX-33
Integrated PCM CO DEC Technology Update .........•..................•........•.......••. IX-35
X - Transmit/Receive Filter
MK5912-3 PCM Transmit/Receive Filter .................•..•......•..•.....•.............. X-1
CODEC/Filter Demo Board Application Brief ........•.....•••...........•...••.......•..... X-11
I-ii
1982 TELECOMMUNICATION PRODUCTS DATA BOOK
NUMERICAL INDEX
MK5087
Integrated Tone Dialer ...••.•.......•.........••............••......•••.• IV-1
MK5087/89
Electronic Drive Application Brief .••.......••..•..............•..•••..... IV-13
MK5089
Integrated Tone Dialer .•...•..•..••.....•.••...........••....•••.••...... IV-7
MK5091
Integrated Tone Dialer ..•..........•......••.•.............••..•..••.•.. IV-15
MK5092
Integrated Tone Dialer ..•............•......••••.....•......••......••••. IV-21
MK5094
I'ltegrated Tone Dialer ....•...•...•.......•..•...............••••.••.... IV-29
MK5102-5
Integrated Tone Receiver ••........•.......•.•.................••.••.... VII-1
MK51 02-5
DTMF Decoder Application Note .............•......•...............•.•.. VII-5
MK5102/S3525A
DTMF Receiver System Application Brief .......••••...•••......•......••• VII-15
MK51 03-5
Integrated Tone Decoder ............................................... VII-17
MK5116
MK5151
w255 Law Companding CODEC .....••......•...............•.....•..•... IX-1
w255 Law Companding CODEC .................•...•...............•• : . IX-11
MK5156
A-Law Companding CODEC ••...................•...•••....•............ IX-23
MK5170
Repertory Dialer ................•..............•••...•...............•.. VI-1
MK5175
Ten-Number Repertory Dialer .....•...............••.................... VI-19
MK5242
Active Speech Network ..........•.............••....••................. VIII-1
MK5316
Companding CODEC with Filters .••......•...........•.•................. IX-33
MK5380
Integrated Tone Dialer ..........•••....•..•...••.•........•.•........••. IV-37
MK5382
Integrated Tone Dialer with Redial .•.......••.....•.......••..•.•••...... IV-45
MK5912-3
PCM Transmit/Receive Filter' ..•...••......•..............•....•.••••..... X-1
MK50981
Integrated Pulse Dialer with Redial .......•.••.....•........•..•..•........ V-1
MK50982
Integrated Pulse Dialer with Redial .................••...•.........•....... V-7
MK50991
Integrated Pulse Dialer with Redial •.•......•.......•....•................ V-13
MK50992
Integrated Pulse Dialer with Redial ...................•..•...........•.... V-19
CODEC/Filter Demo Board Application Brief .......••........•..•......•.•• X-11
Current Sources Application Brief ...•........•..........•...........•.... V-25
DTMF Receiver System Application Brief ................•................ VII-23
Integrated Dialer Comparison-Tone II vs Tone III Application Brief .........•.•• IV-47
Integrated PCM CODEC Technology Update .•...........•................• IX-35
Loop Simulator Application Brief ........................••............... IV-49
Pulse Dialer Comparison Application Brief ...••...........•................ V-27
Telecommunications Terms Application Brief .......•........•..•.••........ II-iii .
I-iii
I-iv
1982 TELECOMMUNICATION PRODUCTS DATA BOOK
Telecommunications
Mostek offers a broad line of telecommunications circuits aimed at cost-effective
solutions for large or small systems. At Mostek, you have a choice. Tone dialers, pulse
dialers, repertory dialers, tone decoders, CODECs, and PCM filters are available in volume now.
Mostek made its commitment to telecommunications products in 1974, the year we
produced our first tone dialer. Since 1974, we have shipped over nine million tone dialers
and we have earned our reputation as a dependable source for reliable products. Our
extensive testing and quality control procedures all assure reliable systems in the field.
Some excellent examples of Mostek's technological leadership are the recently
introduced ten-number repertory dialer and the switched-capacitor PCM filter. In an
application where space and power are the most critical parameters, Mostek's CODEC and
PCM filter offer industry's lowest power.
II-i
II-ii
MOSTEI(.
TELECOMMUNICATION PRODUCTS
Telecommunications Terms
BALANCED LINE: A line or circuit utilizing two identical
conductors, each having the same electro-magnetic
characteristics with respect to other conductors and
ground. A balanced line is preferred in circumstances
where minimum noise and crosstalk are desired.
.
CORNER EFFECT: The rounding off ofthe attenuation vs.
frequency characteristic of a filter at the extremes (or
corners) of the passband.
CROSS MODULATION: A type of intermodulation due to
the modulation of the carrier of the desired signal by an
undesired signal wave.
BALANCING NETWORK: An arrangement of
impedances connected to one branch of hybrid to match the
impedance of a line connected to the opposite branch.
CROSSTALK: Crosstalk is the presence of unwanted voice
currents. It mayor may not be intelligible, but it can be
heard. There are two general forms of crosstalk, near-end
and far-end.
CVSD: Continuously Variable Slope Delta Modulation.
BASEBAND: The total frequency band occupied by the
aggregate of all the information signals used to modulate a
carrier (multiplex or radio).
CARRIER: A form of communication using waves that can
dBm: dBm is a transmission level referenced to a specified
impedance. For instance, 0 dBm/600 fl is a power of 1
milliwatt across a 600 n impedance. (0 dBm '" 1 mW)
dBmO: The power expressed in dBm measured at, or
referenced to, a point of zero transmission level.
be modulated by changing their amplitude, frequency, or
phase so that they can "carry" intelligence. Carrier
communication is used as a means of transmitting one or
more messages over a single open-wire pair, cable pair, or
radio circuit.
dBmOp: Based upon 1.0 milliwatt at the 0.0 dBm TLP,
psophometrically weighted.
CENTRAL OFFICE (CO): A place or building where
telephone calls are switched
automatically or manually.
or
connected,
either
dBrn: dBrn is used for noise measurement on telephone
lines. Reference noise is -90 dBm (0 dBrn).
C-MESSAGE: A frequency weighting which evaluates the
dBrncO: A C-Message weighted value based upon -90.0
dBmC referenced to apoint of zero transmission level ie.,
0,0 dBrncO '" -90.0 dBmCO.
effects of noise corresponding to its annoyance to the
"typical" subscriber of standard telephone service. This
weighting is also used to evaluate the effects of noise
(background and impulse) on voice-grade data services.
DELTA MODULATION: A means of encoding analog
signals in control and communication systems. The output
of the delta encoder is a single-weighted digital pulse train
which may be decoded at the receiving end to reconstruct
the original analog signal.
C-NOTCHED: A frequency weighting similar to CMessage weighting except for the addition of a narrow
stopband or notch at 1010Hz. Used in making noise-withtone measurements.
DESENSITIZATION: The tendency of a receiver to fail to
CODEC: A circuit comprised of an encoder and decoder in
the same device.
recognize valid DTMF signals in the presence of such
factors as dial tone, pilot signals, or data signals.
COMPANDOR: A compandor is an electronic circuit used
DROP CHANNEL: This refers to a type of operation where
in carrier systems to provide better signal-to-noise ratios.
The name is a contraction of two-compressor and
expandor, which describe the actions of the two types of
circuits in the equipment-a speech compressor at the
transmitting end and a speech expandor at the receiving
end.
one or more channels of a· multichannel system are
terminated (dropped) at some point intermediate between
the end terminals of the system.
DROPOUT: Short interruptions of service where the
transmitted signal experiences a sudden large drop in
power; often, the signal becomes undetectable. Present
standards define a dropout as a decrease in signal level of
12 dB with a duration greater than 10 ms.
COMPRESSOR: The part of a compandor that is used to
compress the intensity range of signals at the transmitting
end of a circuit. It amplifies weak signals and attenuates
strong signals.
DRY LINE: A telephone line without battery voltage
CONTROL OFFICE: The control office is the location
present.
designated on the circuit order card as having the
responsibility for maintaining the overall circuit. This office
is sometimes referred to as the control point. In most cases,
this is the office which coordinates all activities on a circuit
with the customer.
ECHO: The result of impedance mismatches, hybrid
unbalance, and time delay. Depending upon the location of
impedance irregularities and the propagation
characteristics of a facility, echo may interfere with the
II-ii i
talker or listener, or both. The greater out-of-phase the
currents are, the greater the interfering effect.
ECHO R ETU R N LOSS(ER L): Is a weighted average of the
return losses at all frequencies between 500 and 2500 Hz.
ECHO SUPPRESSOR: Echo Suppressors are used to
minimize the effect of echo. They work in such a way as to
block the echo return currents. They are voice-operated
gates which allow communication one way at a time.
ENVELOPE DELAY DISTORTION: Envelope delay isthe
derivative of the circuit phase shift (in radians) with respect
to frequency (radians p .r second). The deviation of this
derivative at any frequency from the derivative's value at a
prescribed frequency (usually 1800 Hz) is called envelope
delay distortion (ED D).
EQUALIZER: An electrical network in which attenuation
(or gain) varies with frequency and is used to provide
equalization of a frequency-dependent transmission line.
EXPANDOR: A part of a compandor. It is used at the
receiving end of a circuit to return the compressed signal to
its original form. It amplifies strong signals.
FOUR-WIRE CIRCUIT: A four-wire circuit is considered to
be one which terminates at the customer's premises in four
wires. Transmission is done over one pair and reception is
done over the other pair. The circuit is four-wire throughout
and may include repeaters, carrier, or both. When carrier is
used, the circuit is sometimes referred to as "equivalent
four-wire" since different transmitting frequencies may be
superimposed in the same cable pair or open-wire.
FREQUENCY RESPONSE: The frequency response of a
circuit refers to its overall transmission characteristics. The
frequencies to be measured and their limits are shown on
the circuit order card.
FREQUENCY SHIFT: A fixed offset in each received
frequency of a signal relative to the transmitted signal, due
to differences in the inserted carrier frequencies in the
receivers and transmitters of transmission systems.
FULL DUPLEX: Telegraph or signaling circuits arranged for
transmission in both directions at the same time.
GAIN TRACKING: Loss deviation (1000 Hz reference)
over the range of levels of interest.
HALF DUPLEX: Transmission in one direction at a time
over a single channel. Thus, in a half-duplex telegraph
system, information can be transmitted in only one direction
at a time.
HOOKSWITCH: The switch on the telephone set which is
activated by placing the receiver on the hook. The two
conditions are defined as off-hook and on-hook conditions,
corresponding to busy and idle circuits respectively.
HYBRID: A bridge-type circuit or connecting device that
combines the function of providing impedance matching
between certain circuits and isolation between other
circuits. A hybrid is often used to connect four-wire lines to
a two-wire line so that in both directions of transmission the
four-wire lines are isolated from each other, but are
connected to the two-wire line.
HYBRID COIL: A hybrid coil is a transformer arrangement
used to convert a two-way, two-wire circuit into two
separate two-wire circuits (four-wire operation).
IMPULSE NOISE: Characterized by large excursionsofthe
total noise waveform which are much higher than the
normal peaks of the message circuit noise.
LOOP RESISTANCE: The loop resistance of a cable pair is
the dc resistance from the telephone office to a distant
point. It may include a coil at the far end. If no coil is present,
a short must be placed across the tip and ring. Corrections
for temperature variations from 68°F must be made to the
measured dc resistance in order to determine if the loop
resistance is correct.
LOSS: End-to-end circuit attenuation usually measured at
1000 Hz.
MESSAGE CIRCUIT NOISE: Background noise
measured between two balanced lines. Also called
"Metallic Noise".
MODEM: A single unit of equipment which combines the
functions of modulator and demodulator. Connects enduser's equipment with telephone system.
MULTIPLEX: A means of transmitting two or more signals
over the same medium.
NET LOSS: The net loss of a circuit is the transmission loss
at 1000 cycles in dB between two locations. The greater the
number, the poorer the circuit. It is sometimes referred to as
the specified equivalent or the card loss.
NETWORK: Network, as generally used, refers to an
impedance matching device associated with a hybrid coil or
terminating set. It is used to balance the derived two-wire
circuit (line) for maximum return loss. Networks are of two
broad types-precision and compromise. Networks of this
type may be referred to as a balancing net, precision net,
camp. net, or net.
NOISE FIGURE: The noise figure expresses the amount of
noise introduced by a piece of equipment over the basic
thermal noise that is present. It represents the relationship
of the signal-to-noise ratio at the input of the device to the
signal-to-noise ratio at its output.
NOISE IMMUNITY: A measure of a DTMF receiver's
ability to prevent valid signals from being rejected as noise.
It is sometimes specified as the ability of the receiver to
operate under conditions of gaussian noise in dBrnC.
NOISE-TO-GROUND: A noise measurement where the
noise is measured from a balanced line to ground.
NOISE WEIGHTING: Noise weighting is used to give the
proper interfering effect when noise currents are converted
to sound. The weighting networks integrate the noise
power over the frequency range by giving each small band
of frequencies a weighting proportional to its contribution to
the total interfering effect.
NONLINEAR DISTORTION: The generation of new
signal components not present in the original transmitted
signal. This usually happens when the loss on a channel is
nonlinear with respect to input level.
Il-iv
PABX: Private Automatic Branch Exchange. Has the same
usage as a PBX except that calls within the system are
completed automatically by dialing. An attendant at an
attendant's board may be required to route and complete
incoming calls from the central office. Stations within the
system are connected to the central office by dialing directly,
or they are made to go through the attendant as company
policy dictates.
PBX: Private Branch Exchange. A telephone system located
on the premises of a business and requiring an attendant to
complete all calls. It is usually owned by the telephone
company and is equipped with trunks to a telephone
company central office.
PCM: Pulse-Code Modulation - pulse modulation in which
the signal is sampled periodically and each sample is
quantized and transmitted as a digital binary code.
PHASE JITTER: The undesired component of a received
signal which appears as phase (or frequency) modulation.
PHASE HIT: A sudden change(+ or -) in the received signal
phase (or frequency).
PRIVATE LINE CIRCUIT: A private line circuit is a
connection between two or more stations for the exclusive
use of a customer. It mayor may not have access to the
nationwide telephone network.
PSOPHOMETRIC-WEIGHTED: A frequency weighting
similar to C-Message weighting, which is used as the
standard for European telephone system testing.
QUANTIZING NOISE: Signal-correlated noise generally
associated with the quantizing error introduced by analogdigital and digital-analog conversions in digital
transmission systems.
SINGING POINT (S.P.): The singing point of a circuit isthe
threshold at which it goes into oscillation. It is a measure of
stability and is a function of return loss. It is measured in dB
and the larger the number, the greater the stability.
SINGING RETURN LOSS (SRL): Weighted average of
the return losses at all frequencies in a frequency band.
There is a low frequency test covering the 200 to 500 Hz
band (SRL-LO) and a high frequency test covering the 2500
to 3000 Hz band (SRL-HI).
SKEW: A measure (expressed in percent) of the departure
of each individually received signal frequency from its
nominal value. A function of component tolerances, aging,
environmental conditions, and certain types of transmission-multiplexing equipment, skew is measured at the
DTMF receiver.
SLEEVE (S): Sleeve is a term to describe the frame or body
portion of a telephone plug or jack. See tip and ring.
SUBSCRIBER'S SUBSET: The telephone instrument on
the subscriber's premises.
TALK-OFF: The tendency of a DTMF system to respond
falsely to other-than-valid DTMF signals. Talk-off criteria
are generally specified very subjectively - sometimes in
such broad terms as "good" or "poor".
TERMINATING CONNECTION: A measurement that
substitutes the internal resistance of the measuring
instrument for the subscriber's subset or other equipment.
If the measuring instrument does not have the desired
impedance, an external resistor must be placed across the
input terminals.
REPEATER: A repeater is an amplifier. Some repeaters
use separate amplifiers for each direction of transmission
while others use one amplifier for both directions.
TERMINATING SET: A terminating set is used at the
terminals of an equivalent four-wire circuit for converting to
two-wire operation. The transformer arrangement is similar
to a hybrid coil. The set is sometimes referred to as a
four-wire term set or term set.
REPEATING COIL: A repeating coil is a transformer. There
are numerous impedance ratios available to match a variety
of telephone cable and equipment impedances. A repeating
coil is sometimes called a repeat coil or coil.
TIP AND RING: Tip (T) and ring (R) are terms used to
identify the two conductors of a circuit. They originate from
switchboard terminology pertaining to cord circuits. A fourwire circuit is designated T 1, T2 and Rl and R2'
RETURN LOSS (R.L.): The return loss of a circuit is a
measure of the amount of transmitting current which is
transferred to the receiver at the same location due to
impedance mismatches. The higher the ratio in dB, the
better the return loss. See ERL and SRL.
TWIST: The difference (in decibels) between the DTMF
high-group and low-group signal levels, mathematically
defined as 10 log [(high-group power)/(Iow-group power)].
Measured at the DTMF receiver, it's a function of both the
level difference generated by the signal source and the
gain-frequency characteristic of the transmission facility.
RINGDOWN SIGNALING: The 90 Vat 20 Hz signal used
to operate the ringer in a subscriber's telephone set.
RINGER: The signaling bell in a telephone set.
SENSITIVITY: Generally expressed in dBm at a specified
impedance (usually 600 n), sensitivity is a measure of the
lowest DTMF signal level that a receiver can detect. It
represents an absolute threshold below which detection of
a single frequency is not generated.
SHORT: A circuit is said to be "short" when the net loss is
less than the limits allow. This may create "singing"
(oscillation).
SINGING: Singing means a circuit is oscillating because it
has too much gain. It can sing at any frequency, but the
effect is worse at those frequencies within the usable band. II-v
TWO-WIRE CIRCUIT: A two-wire circuit is one which
terminates at the customer's premises in two wires. It may,
however, contain some facilities which are four-wire, such
as a repeater or carrier.
VARLEY: A varley (varley loop test) is made with a
Wheatstone bridge and is used to detect a difference
(unbalance) in the dc resistance of the tip and ring
conductors.
WET LINE: A telephone line with battery voltage present.
WHITE NOISE: Random noise whose constant energy per
unit bandwidth is independent of the central frequency at
the band. The name is taken from the analogous definition
of white light.
ZERO TRANSMISSION LEVEL POINT (OTLP): An
arbitrary point in a transmission system to which all relative
II-vi
levels at other points in the system are referred. The OTLP is
usually the transmitting toll switchboard or testboard.
MOSTEI{
TELECOMMUNICATION PRODUCTS
Definitions of Data Sheet Designations
are not guaranteed. Mostek reserves the right to make
changes in specifications at any time and without notice.
A Product Profile is an initial disclosure of a new product's
features and general information. A "PRODUCT PROFILE"
designation on a Mostek literature item indicates that the
product is not yet available and that the specification goals
have not yet been fully established. The information given in
the Product Profile is subject to change and is not
guaranteed. Mostek reserves the right to make changes in
the Product Profile at any time and without notice.
A Target Specification is an initial disclosure of specification
goals for a product. The 'TARGET SPECIFICATION"
designation on a Mostek data sheet indicates that the
product is not yet available. The specifications in the data
sheet are subject to change, are based on design goals, and
A Preliminary data sheet indicates that the specifications in
the data sheet are based on design goals or preliminary part
evaluation. The "PRELIMINARY" designation on a Mostek
data sheet indicates that the product is not characterized.
The specifications are subject to change and are not
guaranteed. Mostek reserves the right to make changes in
specifications at any time and without notice.
A data sheet without any specific designation indicates that
the product has been characterized and that the
specifications have been verified. The information furnished by Mostek in this data sheet is believed to be
accurate and reliable.
II-vii
II-viii
ORDER INFORMATION
TELECOMMUNICATION PRODUCTS
Factory orders for parts described in this book should include a four-part number as explained below:
Example: MK
5103(N)~5
C'
Dash Number
2. Package
3. Device Number
4. Mostek Prefix
1.
Dash Number
One or two numerical characters defining specific device performance characteristic.
2.
Package
P
J
N
K
T
E
3.
Gold side-brazed ceramic DIP
- CER-DIP
Epoxy DIP (Plastic)
tin side-brazed ceramic DIP
Ceramic DIP with transparent lid
Ceramic leadless chip carrier
Device number
Shift Register, ROM
1XXX or 1XXXX
2XXX or 2XXXX
ROM, EPROM
3XXX or 3XXXX - ROM, EPROM
38XX
Microcomputer Components
4XXX or 4XXXX
RAM
Telecommunications and Industrial
5XXX or 5XXXX
7XXX or 7XXXX
Microcomputer Systems
4.
Mostek Prefix
MK-Standard Prefix
MKB-1oo% 883B screening, with final electrical test at low, room and high-rated temperatures.
II-ix
II-x
MOSTEI{®
TELECOMMUNICATION PRODUCTS
Package Descriptions
Plastic Dual-In-Line Package (N)
16-Pin
C::::]='
f
.,,--=.r-'o.,
III v
L
NOM.
U
.-- fJ ~
MIN.
E,.~o~'~l
I---.,oo .
j'''t''O ,
I
•020
'R"
v ~\Lo"
v
u
.0>0
_~.
-'I
MIN .
~:±.O~UI
I
~7 EQ~~~;;"CES---l
.OGONOt.'!.
-
~.J25~025~
.m
'I
"
'I
NOTE: Overall length includes .005 flash on either end of package
Plastic Dual-In-Line Package (N)
18-Pin
~=:r
,~.325!:'025.-..l,
NOTE: OveraUlangth includes .005 flash on either end of package
Plastic Dual-In-Line Package (N)
24-Pin
~.
,1..---....,....----1,
NOTE: Overall length includes .005 flash on either end of package
II-xi
Plastic Dual-In-Line Package (N)
28-Pin
NOTE: Overalilangth includes .005 flash on either end of package
Plastic Dual-In-Line Package (N)
40-Pin
NOTE: Overall length includes .005 flash on either end of package
Side-Braze Ceramic Package (P)
16-Pi,n
f"l
\ .•"'.oo,
~
.,. -j\P
.ur;
•
Side-Braze Ceramic Package (P)
18-Pin
II-xii
•
Side-Braze Ceramic Package (P)
24-Pin
Side-Braze Ceramic Package (P)
28-Pin
Side-Braze Ceramic Package (P)
40-Pin
Cerdip Package (J)
16-Pin
II-xiii
Cerdip Package (J)
18-Pin
Cerdip Package (J)
24-Pin
Cerdip Package (J)
28-Pin
Cerdip Package (J)
40-Pin
II-xiv
1982 TELECOMMUNICATION PRODUCTS DATA BOOK
Mostek - Technology For Today And Tomorrow
system.
In design, production and testing, the
Mostek goal is meeting specifications the
first time on every product. This goal requires
strict discipline from the company and from
its individual employees. Discipline, coupled
with very personal pride, has enabled
Mostek to build in quality at every level of
production.
TECHNOLOGY
From its beginning, Mostek has been an
innovator. From the developments of the 1 K
dynamic RAM and the single-chip calculator
in 1970 to the current 64K dynamic RAM,
Mostek technological breakthroughs have
proved the benefits and cost-effectiveness of
metal oxide semiconductors. Today, Mostek
represents one of the industry's most
productive bases of MOS/LSI technology,
including Direct-Step-on-Wafer processing
and ion-implantation techniques.
The addition of the Microelectronics
Research Center in Colorado Springs adds a
new dimension to Mostek circuit design
capabilities. Using the latest computer-aided
design techniques, center engineers will be
keeping ahead of the future with new
technologies and processes.
PRODUCTION CAPABILITY
The commitment to increasing production
capability has made Mostek the world's
largest manufacturer of dynamic RAMs. We
entered the telecommunications market in
1974 with a tone dialer, and have shipped
millions of telecom circuits since then. More
than two million of our MK3870 single-chip
microprocessors are in use throughout the
world. To meet the demand, production
capability is being constantly increased.
Recent construction in Dallas, Ireland and
Colorado Springs has added some 50
percent to the Mostek manufacturing
capacity.
QUALITY
The worth of a product is measured by
how well it is designed, manufactured and
tested and by how well it works in your
III-i
alternative to discrete logic systems is
provided.
Memory Products
Through innovations in both circuit design,
wafer processing and production, Mostek
has become the industry's leading supplier
of memory products.
An example of Mostek leadership is our
new BYTEWYDpM family of static RAMs,
ROMs, and EPRpMs. All provide high
performance, N words x 8-bit organization
and common pin configurations to allow
easysystem upgrades in density and
performance. Another important product
area is fast static RAMs. With major
advances in technology, Mostek static RAMs
now feature access times as low as 55
nanoseconds. With high density ROMs and
PROMs, static RAMs, dynamic RAMs and
pseudostatic RAMs, Mostek now offers one
of industry's broadest and most versatile
memory product lines.
THE PRODUCTS
Telecommunication Products
Mostek is the leading supplier of tone
dialers, pulse dialers, and CODEC devices.
As each new generation of telecommunications systems emerges, Mostek is
ready with new generation components,
including PCM filters, tone decoders,
repertory dialers, new integrated tone
dialers, and pulse dialers.
These products, many of them using
CMOS technology, represent the most
modern advancements in telecommunications component design.
Microcomputer Components
Industrial Products
Mostek's line of Industrial Products offers
a high degree of versatility per device. This
family of components includes various
microprocessor-compatible A/D converters,
a counter/time-base circuit for the division
of clock signals, and combined
counter/display decoders. As a result of the
low parts count involved, an economical
III-ii.
Mostek's microcomputer components are
designed for a wide range of applications.
Our Z80 family is today's industry
standard 8-bit microcomputer. The MK3870
family is one of the industry's most popular
8-bit single-chip microcomputers, offering
upgrade options in ROM, RAM and I/O, all
in the same socket. The 38P7X EPROM
versions support and prototype the entire
family.
function, reducing system cost because the
designer buys only the specific functional
modules his system requires. All MDX
boards are STD-Z80 BUS compatible.
Microcomputer Systems
Complementing the component product
line is the powerful MATRIXTM
microcomputer development system, a Z80based, dual floppy-disk system that is used to
develop and debug software and hardware
for all Mostek microcomputers.
A software operating system, FLP-80DOS,
speeds and eases the design cycle with
powerful commands. BASIC, FORTRAN, and
PASCAL are also available for use on the
MATRIX.
Mostek's MD Series™ features both
stand-alone microcomputer boards and
expandable microcomputer boards. The
expandable boards are modularized by
Memory Systems
Taking full advantage of our leadership in
memory components technology, Mostek
Memory Systems offers a broad line of
products, all with the performance and
reliability to match our industry-standard
circuits. Mostek Memory Systems offers addin memory boards for popular DEC and Data
General minicomputers.
Mostek also offers special purpose and
custom memory boards for special
applications.
III-iii
III-iv
U.S. AND CANADIAN SALES OFFICES
CORPORATE HEADQUARTERS
Mostek Corporation
1215 W. Crosby Ad
P. O. Box 169
Carrollton, Texas 75006
REGIONAL OFFICES
Atlanta Region
South Central U.S.
2 Exchange Place
2300 Peachford Rd. #2105
Atlanta. GA 30338
Mostek
3400 S. Dixie Ave.
Suite 101
Kettering, Ohio 45439
404/458-7922
TWX 810·757-4231
513/299-3405
TWX 810-459-1625
Northeastern Area
Mostek
49 W. Putnam, 3rd Floor
Greenwich. Conn. 06830
203/622-0955
TWX 710-579-2928
Upstate NY Region
Mostek
4651 Crossroads Park Dr., Suite 201
Liverpool, NY 13088
Michigan
Mostek
Orchard Hill Place
21333 Haggerty Road
Suite 321
Novi, MI 48050
313/348-8360
lWX 810-242-1471
315/457-2160
TWX 710-545-0255
Northeast U.S.
Mostek
29 Cummings Park, Suite #426
Woburn, Mass. 01801
617/935-0635
TWX 710-348-0459
Southeastern Area
Mostek
4001 B Greentree Executive Campus
Route #73
Marlton, New Jersey 08053
609/596·9200
TWX 710-940-0103
Southeast U.S.
Mostek
13907 N. Dale Mabry Highway
Suite 201
Tampa, Florida 33618
813/962-8338
TWX 810-876-4611
Florida Region
Mostek
22521 Southwest 66th Ave.
Apt.A211
Boca Raton, FL 33433
305/483-2483
Central U.S.
Mostek
4100 McEwen Road
Suite 151
Dallas, Texas 75234
214/386-9340
nNX 910-860-5437
Chicago Region
Mostek
Two Crossroads of Commerce
Suite 360
Rolling Meadows, III. BC008
312/577-9870
TWX 910-291-1207
Southwest Region
Mostek
4100 McEwen Road
Suite 237
Dallas, Texas 75234
214/386-9141
TWX 910-860-5437
North Central U.S.
Mostek
6101 Green Valley Dr.
Bloomington. Mn. 55438
612/831-2322
TWX 910-576-2802
Chevy Chase #4
7715 Chevy Chase Dr., Suite 116
Austin, 1)( 78752
5121458-5226
TWX 910-874-2007
III-v
Western Region
Northern California
Mostek
1762 Technology Drive
Suite 126
San Jose, Calif. 95110
408/287-5080
TWX 910-338-7338
Seattle Region
Mostek
1107 North East 45th 51.
Suite 41 1
Seattle, WA 98105
206/632-0245
TWX 910-444-4030
Southern California
Mostek
18004 Skypark Circle
Suite 140
Irvine, Calif. 92714
714/549-0397
TWX 910-595-2513
Arizona Region
Mostek
2150 East Highland Ave
Suite 101
Phoenix, Al85016
602/954-6260
TWX 910-957-4581
Denver Region
3333 Quebec Street, #9090
Denver, CO 80207
303/321-6545
TWX 910-931-2583
U.S. AND CANADIAN REPRESENTATIVES
ALABAMA
Beacon Elect. Assoc" Inc. 011309 S. Memorial Pkwy
Sllite G
Huntsville, AL 35803
205/881 -5031
TWX 810-726-2136
Conley & Associates. Inc.
3322 Memorial Pkwy .. S.W
Suite 17
Huntsville, AL 35801
205/882-0316
TWX 810-726-2159
ARIZONA
Summit Sales
7825 E, Redfield Rd.
Scottsdale, AZ 85260
602/998-4850
TWX 910-950-1283
ARKANSAS
Beacon Elect. Assoc., Inc
P.O. Box 5382, Brady Station
little Rock, AK 72215
5011224-5449
TWX 910-722-7310
MARYLAND
Arbotek Associates
3600 St. Johns LClne
Ellicott City, MD 21043
301/461-1323
TWX 710-862-1874
ILLINOIS
Carlson Electronic Sales~
600 East Higgins Road
Elk Grove ViJJage, IL 60007
312/956-8240
TWX 91 0-222-1819
MASSACHUSETTS
New England Technical Sales"
135 Cambridge Street
Burlington, MA01803
6171272-0434
TWX 710-332-0435
INDIANA
Rich Electronic Marketing"
599 Industrial Drive
Carmel, IN 46032
317/844-8462
TWX 81 0-260-2631
MICHIGAN
Action Components
21333 Haggerty Road
Suite 201
Novi, MI 48050
313/349-3940
Rich Electronic Marketing
3448 West Taylor St
Fort Wayne, IN 46804
219/432-5553
TWX 810-332-1404
MINNESOTA
Cahill, Schmitz & CahilL
315 N. Pierce
SI. Paul, MN 55104
612/646-7217
TWX 91 0-563-3737
IOWA
Carlson Electronic Sales
204 Collins Rd. NE
Cedar Rapids, IA 52402
319/377 -6341
TWX 910-222-1819
CALIFORNIA
Harvey King, Inc
8124 Miramar Road
San Diego. CA 92126
714/566-5252
TWX 910-335-1231
COLORADO
Waugaman Associates·
4800 Van Gordon
Wheat Ridge. CO 80033
303/423-1020
TWX 910-938-0750
CONNECTICUT
New England Technical Sales
240 Pomeroy Ave.
Meriden, CT 06450
203/237-8827
TWX 710-461-1 126
FLORIDA
Conley & Associates,
P.O. Box 309
235 S. Central
Oviedo, FL 32765
305/365-3283
TWX 81 0-856-3520
GEORGIA
Conley & Associates, Inc
3951 Pleasantdale Road
Suite 201
Doraville, GA 30340
404/447-6992
TWX 810-766-0488
Inc.~
Conley & Associates, Inc
4021 W. Waters
Suite 2
Tampa, FL 33614
813/885-7658
TWX 810-876-9136
REP Associates
980 ArecCl Ave.
Marion, IA 52302
319/393-0231
KANSAS
Rush & West Associates~
107 N. Chester Street
Olathe, KN 66061
913/764-2700
Wichita 316/683-0206
TWX 910-749-6404
KENTUCKY
Rich Electronic Marketing
5910 Bardstown Road
P. O. Box 91147
louisviJJe, KY 40291
502/239-2747
TWX 810-535-3757
~Home
Inc.~
NORTH CAROLINA
Conley & Associates, Inc.
4050 Wake Forest Road
Suite 102
Raleigh, NC 27609
919/876-9862
TWX 510-928-1 829
NEW JERSEY
Tritek Sales, Inc.
21 E. Euclid Ave
Haddonfield, NJ 08033
609/429-1551
215/627 -0149 (Philadelphia Line)
TWX 710-896-0881
NEW MEXICO
Waugaman Associates
P.O. Box 14894
Albuquerque, NM 87111
9004 Menaul NE
Suite 7
Albuquerque, NM 87112
505/294-1437
505/294-1436 (Ans. Service)
Conley & Associates, Inc.
P.O. Box 700
1612 N.W. 2nd Avenue
Boca Raton, FL 33432
305/395-6108
TWX 510-953-7548
Office
III-vi
Precision Sales Corp.
5 Arbustus Ln., MR-97
Binghamton, NY 13901
607/648-3686
607/648-8833
Precision Sales Corp. ~
1 Commerce Blvd.
Liverpool, NY 13008
315/451-3480
TWX 710-545-0250
MISSOURI
Rush & West Associates
481 Melanie Meadows Lane
Ballwin, MO 63011
314/394-7271
0'
NEW YORK
ERA Inc
354 Veterans Memorial Highway
Commack, NY 11725
516/543-0510
TWX 510-226-1485
(New Jersey Phone #
800/645-5500,5501 )
Precision Sales Corp.
3594 Monroe Avenue
Pittsford, NY 14534
71 6/381 ~2820
Precision Sales Corp.
Drake Road
Pleasant Valley, NY 12569
914/635-3233
OHIO
Rich Electronic Marketing
7221 Taylorsville Road
Dayton, Ohio 45424
5131237-9422
TWX 810-459-1767
Rich Electronic Marketing
141 E. Aurora Road
Northfield, Ohio 44067
216/468-0583
TWX 810-427-9210
OREGON
Northwest Marketing Assoc
9999 S.W. Wilshire St.
Suite 124
Portlar.d OR 97225
503/297-2581
TELEX 36-0465 (AMAPORT PTL)
TENNESSEE
Conley & Associates, Inc
1128 Tusculum Blvd.
Suite D
Greenville, TN 37743
615/639-3139
TWX 810-576-4597
TEXAS
Southern States Marketing, Inc!
P.O, Box 8000
Addison, TX 75001
214/387 -2489
TWX 910-860-5138
Southern States Marketing, Inc
7745 Chevy Chase
Suite 219
Austin, TX 78752
5121452-9459
Southern States Marketing, Inc
9730 Town Park Drive, Suite 105
Houston, Texas 77036
713/988-0991
TWX 910-881-1630
UTAH
Waugaman Associates
2520 S. State Street
Suite #159
Salt Lake City, UT 84115
801/467 -4263
TWX 910·925-4073
WASHINGTON
Northwest Marketing Assoc."
12835 Bellevue-Redmond Rd.
Suite 203E
Bellevue, WA 98005
206/455-5846
TWX 910-443-2445
WISCONSIN
Carlson Electronic Sales
Northbrook Executive Ctr.
10701 West North Ave.
Suite 209
Milwaukee, WI 53226
414/476-2790
TWX 910-222-1819
CANADA
Cantec Representatives Inc."
1573 Laperriere Ave.
Ottawa, Ontario
Canada K1Z 7T3
6131725-3704
TWX 610-562-8967
Cantec Representatives Inc.
83 Galaxy Blvd., Unit 1 A
(Rexdale)
Toronto, Canada M9W 5X6
416/675-2460
TWX 610-492-2655
Cantec Representatives Inc.
3639 Sources Blvd.
Suite 116
Dollard Des Ormeaux, Quebec
Canada H982K4
514/683-6131
TWX 610-422-3985
U.S. AND CANADIAN DISTRIBUTORS
4134 E. Wood St
COLORADO
Kierulff Electronics
10890 E. 47th Avenue
Phoenix, AZ. 85040
602/243·4101
TWX 9101951-1550
303/371 -6500
TINX 910/932-0169
Wyle Distribution Group
8155 North 24th Avenue
Phoenix, Arizona 85021
Wyle Distribution Group
451 E. 124th Ave.
Thornton. CO 80241
602/249-2232
303/457·9953
TWX 910/951·4282
TWX 910/936-0770
ARIZONA
KierulH Electronics
CALIFORNIA
Bell Industries
1161 N. Fair Oaks Avenue
Sunnyvale, CA 94086
4081734·8570
TWX 910/339·9378
Arrow Electronics
521 Weddell Or
Sunnyvale, CA 94086
4081745·6600
1WX 910/339·9371
Kierulff Electronics
2585 Commerce Way
Los Angeles, CA 90040
2131725·0325
1WX 910/580·3106
Kierulff Electronics
8797 Balboa Avenue
San Diego, CA 92123
714/278-2112
TWX 910/335-1182
Kierulff Electronics
14101 Franklin Avenue
Tustin, CA 92680
714/731·5711
TWX 910/595·2599
Schweber Electronics
17811 Gillette Avenue
Irvine, CA 92714
714/556·3880
1WX 910/595· 1720
Wyle Distribution Group
124 Maryland Street
EI Segundo, CA 90245
213/322·8100
TWX 910/348·7111
Wyle Distribution Group
9525 Chesapeake Drive
San Diego, CA 92123
714/565·9171
TWX 910/335·1590
Wyle Distribution Group
17872 Cowan Ave.
Irvine, CA 92714
714/841-1600
TWX 910/348·7111
Wyle Distribution Group
3COQ Bowers Ave.
Santa Clara, CA 95051
408/727-2500
TWX 910/338-0296
Denver, CO 80239
CONNECTICUT
Arrow Electronics
12 Beaumont Rd,
Wallingford, CT 06492
2031265·7741
ILLINOIS
Arrow Electronics
492 Lunt Avenue
P. O. Box 94248
Schaumburg, IL 60193
312/893-9420
lWX 9101291 -3544
Bell Industries
3422 W. Touhy Avenue
Chicago, IL 60645
TWX 710/456·9405
FLORIDA
Arrow Electronics
1001 N.W. 62nd S1.
Suite 108
Ft. Lauderdale, FL 33309
3051776· 7790
TWX 510/955·9456
Arrow Electronics
'15 Palm Bay Road, NW
Suite 10, Bldg. 200
Palm Bay, FL 32905
305/725-1480
TWX 510-959-6337
Diplomat Southland
2120 Calumet
Clearwater, FL 33515
813/443-4514
1WX 810/866..0436
Kierulff Electronics
3247 Tech Orive
S1. Petersburg, FL 33702
813/576-1966
404/449·8252
TWX 8101766-0439
Schweber Electronics
303 Research Drive, Suite 210
Norcross, GA 30092
404/449·9170
3011247·5200
TWX 710/236·9005
314/567·6888
TWX 910/764·0882
Pioneer Electronics
9100 Gaither Road
Gaithersburg, MD 20760
Olive Electronics
9910 Page Blvd.
S1. Louis, MO 63132
301/948-0710
314/426·4500
312/982·9210
TWX 710/828-0545
TWX 910/763·0720
Schweber Electronics
9218 Gaither Rd
Gaithersburg, MD 20760
Semiconductor Spec
3805 N. Oak Trafficway
Kansas City, MO 64116
301/840-5900
816/452·3900
312/640·0200
TWX 710/828-9749
TWX 9101771 ·2114
MICHIGAN
Arrow Electronics
3810 VarsitY Drive
Ann Arbor, M148104
NEW HAMPSHIRE
Arrow Electronics
1 Perimeter Rd
Manchester, NH 03103
TWX 9101222..0351
INDIANA
Advent Electronics
8446 Moller
Indianapolis, IN 46268
317/872-4910
TWX 810/341·3228
Arrow Electronics
2718 Rand Road
Indianapolis, IN 46241
317/243·9353
TWX 810/341·3119
Ft. Wayne Electronics
3606 E. Maumee
Ft. Wayne, IN 46803
219/423·3422
TWX 81 0/332·1562
Pioneer Electronics
6408 Castleplace Drive
Indianapolis. IN 46250
317/849·7300
TWX 810/260·1794
IOWA
Advent Electronics
682 58th Avenue
Court South West
Cedar Rapids, IA 52404
319/363-0221
TWX 910/525·1337
TWX 810/863-5625
GEORGIA
Arrow Electronics
2979 Pacific Drive
Norcross, GA 30071
MISSOURI
Arrow Electronics
2380 Schuetz Road
SI. Louis, MO 63141
TWX 910/223-4519
Kierulff Electronics
1536 Lanmeier
Elk Grove Village, IL 60007
TWX 710/476-0162
Schweber Electronics
Finance Drive
Commerce Industrial Park
Danbury, CT06810
2031792·3500
MARYLAND
Arrow Electronics
4801 Benson Avenue
Baltimore, MO 21227
MASSACHUSETTES
Kierulff Electronics
13 Fortune Drive
Billerica, MA01821
617/935-5134
TWX 710/390·1449
Lionex Corporation
1 North Avenue
Burlington, MA 01803
617/272-9400
TWX 710/332·1387
Schweber Electronics
25 Wiggins Avenue
Bedford, MA 01730
617/275-5100
TWX 710/326·0268
Arrow Electronics
Arrow Drive
Woburn, MA 01801
617/933·8130
TWX 710/393·6770
III-vii
313/971-8220
TWX 810/223·6020
Schweber Electronics
33540 Schoolcraft Road
livonia, MI 48150
313/525·8100
TWX 810/242·2983
MINNESOTA
Arrow Electronics
5251 W. 73rd Street
Edina, MN 55435
612/830-1800
TWX 910/576·3125
Kierulff Electronics
5280 W. 74th St.
Edina, MN 55435
612/835·4388
TWX 910/576·2721
Industrial Components
5229 Edina Industrial Blvd
Minneapolis, MN 55435
6121831·2666
TWX 910/576·3153
603/668·6968
TWX 7101220-1684
NEW JERSEY
Arrow Electronics
Pleasant Valley Avenue
Morrestown, NJ 08057
609/235·1900
TWX 710/897-0829
Arrow Electronics
285 Midland Avenue
Saddlebrook, NJ 07662
2011797-5800
TWX 710/988·2206
Kierulff Electronics
3 Edison Place
Fairfield, NJ 07006
201/575·6750
TWX 710/734·4372
Schweber Electronics
18 Madison Road
Fairfield, NJ 07006
2011227·7880
TWX 7101734-4305
u.s.
AND CANADIAN DISTRIBUTORS
NEW MEXICO
NORTH CAROLINA
Bell/Century
11728 linn N.E
Albuquerque, NM 87123
SOUTH CAROLINA
UTAH
CANADA
Arrow Electronics
938 Burke St
Winston Salem, NC 27102
Hammond Electronics
1035 Lowndes Hill Rd
Greenville, SC 29602
BeU/Century
3639 W. 2150 South
Salt Lake City, UT 84120
9191725-8711
TWX 510/931-3169
8031233-41 21
TWX 810/281-2233
801/972-6969
TWX 910/925·5686
Prelco Electronics
2767 Thames Gate Drive
Mississauga, Ontario
Toronto L4T 1G5
Hammond Electronics
2923 Pacific Avenue
Greensboro, NC 27406
TEXAS
505/292-2700
TWX 9101989-0625
Arrow Electron1Cs
2460 Alamo Ave. S,E
Albuquerque, NM 87106
TWX 910/989-1679
9191275-6391
TWX 510/925-1094
Arrow Electronics
13715 Gamma Road
Dallas. TX 75240
NEW YORK
OHIO
214/386-7500
TWX 910/860-5377
Arrow Electronics
7620 McEwen Road
CenterVIlle, OH 45459
Quality Components
2427 Rutland Drive
Austin, TX 78758
505/243-4566
Arrow Electronics
900 Broad Hollow Ad
Farmingdale. U., NY 11735
516/694-6800
TWX 5101224-6494
Arrow Electronics
7705 Maltlage Drive
p, O. Box 370
Liverpool. NY 13088
315/652-1000
TWX 7101545-0230
Arrow Electronics
3(}(X) S. Winton Road
Rochester, NY 14623
716/275-0300
TWX 5101253-4766
Arrow Electronics
20 Oser Ave.
HauPPauge, NY 11787
516/231·1000
TWX 5101227-6623
Lionex Corporation
400 Oser Ave
HauppaUge, NY 11787
5161273- 1660
TWX 510/227-1042
Schweber Electronics
2 Twin Una Circle
Rochester, NY 14623
716/424-2222
Schweber Electronics
,Jericho Turnpike
Westbury, NY 11590
516/334-7474
TWX 510/222-3660
"Zeus Components, Inc.
500 Executive Blvd
Elmsford. NY 10523
914/592-4120
TWX 710/567·1248
513/435-5563
lWX 810/459-161 1
Arrow Electronics
6238 Cochran Road
Solon, OH 44139
2161248-3990
TWX 810/427-9409
Schweber Electronics
23880 Commerce Park Road
Beachwood, OH 44122
216/464-2970
TWX 8101427-9441
Pioneer Electronics
4800 East 131 st Street
Cleveland, OH 44105
216/587-3600
TWX 810/422-2211
Pioneer Electronics
4433 Interpoint Blvd
Dayton, OH 45424
513/236-9900
TWX 810/459-1622
5121835-0220
TWX 910/874-1377
Quality Components
4257 Kellway Circle
Addison, TX 75001
214/387·4949
TWX 910/860-5459
Quality Components
6126 Westline
Houston, 1)( 77036
713/772-7100
Schweber Electronics
10625 Richmond, Suite 100
Houston, 1)( 77042
7131784-3600
TWX 910/881-1109
Arrow Electronics
10700 Corporate Drive
Suite 100
Stafford, TX 77477
713/491-4100
TWX 910/880-4439
OKLAHOMA
Kierulff Electronics
2121 South 3600 West
Salt Lake City, UT84104
416/678-0401
TWX 610/492-8974
801/973-6913
Prelco Electronics
480 Port Royal SI. W.
Montreal 357 P.Q H3L 2B9
WASHINGTON
514/389-8051
TWX 6101421-3616
Kierulff Electronics
1005 Andover Park East
Tukwila, WA 98188
Prelco Electronics
1770 Woodward Drive
Onawa, Ontario K2C OP8
206/575-4420
TWX 910/444·2034
Wvle Oistribution Group
1750 132nd Avenue N.E.
Bellevue, Washington 98005
206/453·8300
TWX 910/443-2526
WISCONSIN
Arrow Electronics
434 Ramon Avenue
Oak Creek, WI 53154
4141764-6600
TWX 910/262- 1193
Kierulff Electronics
2212 E. Moreland Blvd
Waukesha, WI 53186
4141784-8160
TWX 910/262-3653
613/226·3491
Telex 05·34301
RAE. Industrial
3455 Gardner Court
Burnaby, B.C. V5G 4J7
604/291-8866
TWX 610/929-3065
Zentronics
141 Catherine Street
Ottawa, Ontario
K2P 1 C3
613/238~6411
Telex 05·33636
Zentronics
1355 Meyerside Drive
Mississauga, Ontario
(Toronto) L5T lC9
416/676-9000
Telex 06·983657
Zentronics
5010 Rue Pare
Montreal, Quebec
M4P lP3
5141735·5361
Telex 05-827535
Zentronics
590 Berry Street
51. James, Manitoba
(Winnipeg) R2H OR4
Quality Components
9934 East 21st South
Tulsa, OK 74129
918/664-8812
204/775-8661
OREGON
Zentronics
480 "A" Dunon Drive
Waterloo, Ontario
N2L 4C6
Kierulff Electronics
14273 NW Science Park
Portland, OR 97229
503/641·9150
TWX 910/467·8753
519/884-5700
RAE. Industrial
11680 170th St.
Edmonton, Alberta T5S 1J7
PENNSYLVANIA
Schweber Electronics
101 Rock Road
Horsham, PA 19044
403/451-4001
Telex 03-72653
Zentronics
550 Cambie St
Vancouver. B.C. V68 2N7
215/441-0600
Arrow Electronics
650Seco Rd.
Monroeville, PA 15146
604/688-2533
Telex 04507789
Zentronics
3651 21st Street, N.E
Calgary, Alberta T2E 6T5
412/856- 7000
Pioneer Electronics
560 Alpha Drive
Pittsburgh, PA 15238
4121782-2300
493/230-1422
TWX 710/795-3122
Zentronics
9224 27th Avonue
Edmonton: Alberta T6N 182
Pioneer Electronics
261 Gibraltar
Horsham, PA 19044
403/463-3014
215/674-4(XX)
TWX 510/665-6778
-Franchised for USA and Canada excluding California for military products
III-viii
INTERNATIONAL MARKETING OFFICES
EUROPEAN HEAD OFFICE
GERMANY
Mostek International
Av de Tervuren 270-272 Bte 21
8-1150 Brussels/Belgium
PLZ 1-5
Mostek GmbH
Friedlandstrasse 1
D-2085 Quickborn
021762.18.80
Telex: 62011
(04106) 2077178
PLZ8
Mostek GmbH
Zaunkonigstf.18
0-8012 Ottobrunn
(089) 609 1017
Telex: 5216516
Telex: 213685
FRANCE
Mostek France s.a.r.1
30 Rue du Morvan
SlUG 505
F-94623 Rungis Cedex
(1) 687 34.14
Telex: 204049
PLZ 6-7
Mostek GmbH
Schurwaldstrasse 15
0-7303 Neuhausen/Filder
(07158) 66,45
Telex: 72.38.86
JAPAN
Mostek Japan KK
Sanyo Bldg. 3F
1-2-7 Kita-Aoyama
Minato-Ku, Tokyo 107
1031 404- 7261
Telex: J23686
ITALY
Mostek Italia SRL
Via F,O. Guerrazzi 27
120145 Milano
(02) 318.5337/349.2696
and 34.23.89
Telex: 333601
UNITED KINGDOM
Mostek U.K, Ltd.
Masons House,
1-3 Valley Drive
Kingsbury Road
London, N,W.9
01·2049322
Telex: 25940
SWEDEN
Mostek Scandinavia AB
Magnusvagen 118 tr
S·17531 JarfalJa
0758-343 38/343 48/183 30
Telex: 12997
INTERNATIONAL SALES REPRESENTATIVES/DISTRIBUTORS
ARGENTINA
Rayo Electronics S.R.l.
Belgrano 990, Pises 6y2
1092 Buenos Aires
(38)-1779, 37-9476
Telex - 122153
Mecodis
2 Rue Pasteur
F-94380 Bonneuil
(l) 339.20.20
Telex: 250303
AUSTRALIA
Amtron Tyree Pty.ltd
176 Botany Street
Waterloo, N.S.W. 2017
(61) 69-89.666
Telex - 25643
4 Rue Barthelemy
F-92120 Montrouge
151-72.93.76
PEP.
AUSTRIA
Transistor Vertriebsges, mbH
Auhofstrasse 41 A
A- 1130 Vienna
(0222) 82 9451, 83 9404
Telex - 0133738
BRASIL
Cosele, Ltd.
Rua da Consolacao, 867
Conj.31
01301 Sao Paulo
(55) 11-257.35.351258.43.25
Telex - 1130869
BELGIUM
Sotronic
14 Rue Pere De Deken
B- 1040 Brussels
02736.10.07
Telex - 25141
DENMARK
Semicap APS
Gammel Kongevej 148
OK-t850 Copenhagen
01-22.15.10
Telex - 15987
FINLAND
Insele Oy
Kumpulantie 1
SF-OD520 Helsinki 52
0735774
Telex: 122217
FRANCE
Copel
Rue Fourny, Z.I
B.P. 22, F-78 530 BUC
(1) 9561018
Telex: 69379
Facen
110 Av de Flandre
F59290 Wasquehal. Nord
12198.92.15
Branch Offices in
Chalon/Saone, Lille,
Nancy, Rouen, Strasbourg
HONG KONG
Cet Limited
1402 Tung Wah Mansion
199-203 Hennessy Road
Wanchai, Hong Kong
111-735.33.20
Telex: 204 534
Scaib
80 Rue d'Arcueil
SILIC 137
F-94523 Rungis Cedex
111-687.23.12
Telex: 204674
Sorhodis
150-152, Rue A France
F69100 Villeurbanne
1781850044
Telex: 380181
GERMANY
Dr Dohrenberg
Bayreuther Strasse 3
0-1000 Berlin 30
10301 213.80.43
Telex: 0 184860
Neye Enatechnik GmbH
Schillerstrasse 14
0-20850uickborn
1041061612-1
Telex: 0 213,590
Branch offices in: Berlin, Hannover,
Dusseldorf, Darmstadt, Stuttgart,
Munchen
Raffel-Electronic GmbH
Lochnerstrasse 1
0-4030 Ratingen 1
121021280.24
Telex: 8585180
Siegfried Ecker
Koenigsberger Strasse 2
0-6120 Michelstadt
1606112233
Tele;o.:: 4191630
Matronic GmbH
Lichtenberger Weg 3
0-7400 Tuebingen
(7071) 24331
Telex: 7262879
THE NETHERLANDS
Nijkerk Elektronika BV
Orentestraat 7
NL - 1083 HK Amsterdam
(02D) 428. 933
Telex: 11625
Telex - 85148
ISRAEL
Telsys ltd,
12, Kehilat Venetsia St.
Tel Aviv. Israel
482126/7/8
Telex: 032392
ITALY
Comprel S.r,1.
V.le Romagna. 1
1-20092 Cinisello B. (MI)
(02) 61.20.6411213/4/5
Telex: 332484
Branch offices in
Bologna, Firenze,
Lavagna, Loreto,
Padova, Roma, Torino,
Vicenza, Bari
Emesa S.PA
Via l. da Viadana, 9
1-20122 Milano
1021869.0616
NEW ZEALAND
E.C.S. Div. of Airspares
P.O. Box 1048
Airport Palmerston North
JAPAN
Systems Marketing, Inc.
4th Floor, Shindo Blgd.
3-12-5 Uchikanda,
Chiyoda-Ku,
Tokyo, 100
18113-254.27.51
Telex - 25761
Teijin Advanced Products Corp.
1-1 Uchisaiwai-Cho
2-Chome Chiyoda-Ku
Tokyo, 100
1811 3-506.46.73
Telex - 23548
KOREA
Vine Overseas Trading Corp
Room 308 Korea Electric
Association Bldg.
11-4 Supyo-Dong Jung-Ku
Seoul
Lagercrantz Elektronik AB
Box 48
S-19421 Upplands Vasby
0760861 20
Telex: 11275
1771-047
Telex - 3766
NORWAY
Helro Teknisk AIS
Postboks 6596
Rooelokka, Oslo 5
02-38.02,86
Telex: 16205
PORTUGAL
Digicontrole LOA
Rua Tenente Ferreira Durao 33 R/I
1300 Lisboa
19-688442/652613
Telex: 15084
SINGAPORE
Dynamar International, LTD.
Suite 526, Cuppage Road
Singapore 0922
Telex: 335066
Branch offices in
Torino, Bologna, Roma
SWEDEN
Interelko AB, Box 32
S-12221 Enskede
08-1321 60
Telex: 10689
SOUTH AFRICA
Radiokom
P.O. Box 56310
Pinegowrie
2123,
Transvaal
789-1400
Telex - 8-0838 SA
SPAIN
Comelta SA
Emilio Munoz 41, ESC 1
Planta 1 Nave 2
Madrid-17
01-7543001/3007
Telex: 42007
Branch Office
Diputacion, 79
Entlo 1
Barcelona-15
3257062
3257575
Telex: 519 34
SWITZERLAND
Memotec AG
Einschlagweg, 2
CH-4932 Lotzwil
063-28.11.22
Telex: 68636
TAIWAN
Dynamar Taiwan limited
P,O. Box 67-445
2nd Floor, No. 14, Lane 164
Sung-Chiang Road
Taipei
5418251
Telex - 11064
UNITED KINGDOM
Celdis i.Jmited
37-39 Loverock Road
Reading
Berks RG 31 ED
0734-58.51.71
Telex: 848370
Lock Distribution Ltd,
Neville Street
Chadderton
Oldham
Lancashire
Ol96LF
061-652,04.31
Telex: 669971
Pronto Electronic Systems Ltd.
466-478 Cranbrook Road,
Gants Hillilford
Essex 1G 2 6lE
01-5546222
Telex: 895 4213
VSI Electronics (UK) ltd.
Roydondury Industrial Park
Horsecroft Rd
Harlow
Essex CM19 5BY
(0279) 35477
Telex: 81387
18212-66-1663
Thame Components ltd.
Thame Park Road
Thame, Oxon OX93XD
0844213146
Telex: 837917
Dema-Electronic GmbH
Bluetenstrasse 21
0-8000 Munchen 40
(089) 288018/19
Telex: 05-29345
III-ix
III-x
1982 TELECOMMUNICATION PRODUCTS DATA BOOK
MOSTEI{.
TELECOMMUNICATION PRODUCTS
Integrated Tone Dialer
MK5087(N/P/J)
FEATURES
o
Pin-for-pin compatible with MK5085 with improved
performance
o
Direct telephone-line operation with no external power
supply
o
Auxiliary switching functions on chip
o
Low standby power
o
PIN CONNECTIONS
Figure 1
V+_1
XMTR
SWITCH- 2 .
COL1_3
o
On-chip regulation of dual-and single-tone amplitudes
o
Uses low-cost calculator-type keyboard (Form A contact)
or standard 2-of-8 keyboard
o
Multiple key entry pin-selectable to either single tone or
no tone
INHIBIT
14-ROW1
13_ROW2
COL3_5
12_Fi'0W3
V--6
11_ROW4
OSCIN_7
Uses inexpensive 3.579545 MHz television color-burst
crystal to provide high-accuracy tones
15_~TONE
COL2_4
Minimum external parts count
o
16_TONEOUT
OSCOUT_B
10-MUTEOUT
9_COL4
sine wave and requires little or no filtering for low-distortion
applications. The same operational amplifier that
accomplishes the current-to-voltage transformation
necessary for the D-to-A converter also mixes the low and
high-group signals. Frequency stability of this type of tone
generator is such that no frequency adjustment is needed to
meet standard DTMF specifications.
DESCRIPTION
The MK5087 is a monolithic integrated circuit fabricated
using the complementary-symmetry MaS (CMOS) process.
A member of the TONE 11* family of integrated tone dialers,
the MK5087 uses an inexpensive crystal reference to
provide eight different audio sinusoidal frequencies, which
are mixed to provide tones suitable for Dual-Tone-MultiFrequency (DTMF) telephone dialing.
Pin connections are shown in Figure 1 and a block diagram
is shown in Figure 2.
FUNCTIONAL DESCRIPTION
V+, Pin 1
Pin 1 is the positive supply pin. The voltage on Pin 1 should
be between 3.5 and 10.0 volts, measured relative to V-(Pin
6).
The MK5087 was designed specifically for integrated tonedialer applications that require the following: wide-supply
operation with regulated output, auxiliary switching
functions, single-contact keyboard inputs, and Single Tone
Inhibit option.
XMTR SWITCH, Pin 2
Pin 2 is connected to the emitter of an. on-chip bipolar
transistor whose collector is connected to ,v+. With no
keyboard input this transistor is turned on and pulls Pin 2 up
to within V BE of the V+ supply. When a keyboard entry is
sensed, this output goes open circuit (high impedance). The
XMTR Switch output switches regardless of the state of the
Single Tone Inhibit input.
Keyboard entries to the TONE 11* family of integrated tone
dialers cause the selection of the proper divide ratio to
obtain the required two audio frequencies from the
3.579545 MHz reference oscillator. D-to-A conversion is
accomplished on-chip by a conventional R-2R ladder
network. The tone output is a stairstep approximation to a
• Trademark of Mostek Corporation
IV-1
MK5087 BLOCK DIAGRAM
Figure 2
V+
Ai
,.
L
R2 is R4
"
'2
'3
RR
V·
RR
RR
RR
I
-
I
KEYBOARO LOGIC
VKB
.~
OSC
OUT
ROW
COUNTER
~4
B
SINE
WAVE
COUNTER
I.1-
COLUMN
COUNTER
7
OSC
IN
KEYBOARD LOGIC
I
I
SINE
WAVE
COUNTER
VI{
DIA
'0
-
t--
r ~
~:OUT
TONE
VKii
p.;
XMTR
SWITCH
'5
SINGLE TONE
INHIBIT
V-
9
C3
CONVERTER
~
-
r
RC
r-
DIA
1
6
C4
V-
KEYBOARD CONFIGURATIONS
ROW-COL INPUTS,
Pins 3, 4, 5. 9, 11, 12, 13. 14
Figure 3
1.. .
COL ....
~
ROW
CLASS A KEYBOARD
c=i;
The MK5087 features inputs compatible with the standard
2-of-8 keyboard, the inexpensive single-contact (Form A)
keyboard, and electronic input. Figure 3 shows how to
connect to the two keyboard types and Figure 4 shows
waveforms for electronic input. The inputs are static, i.e.
there is no n'oise generation as occurs with scanned or
dyr1amic inputs.
COL
ROW
2-0F-8 KEYBOARD
ELECTRONIC INPUT
Figure 4
~~ ......... 011. .___ COLUMNS
~~........... LJr---- :-::>WS
The internal structure of the MK5087 inputs is shown in
Figure 5. RR and Rc pull in oppoSite directions and hold their
associated input sensing circuit turned off. When one or
more row or column inputs are tied together, however, the
input sensing circuits sense the "y, Level" and deliver a
logic signal to the internal circuitry of the MK5087 and
cause the proper tone or tones to be generated.
When operating with a keyboard, normal operation is for
dual-tone generation when any single button is pushed,
and single-tone operation when one or more buttons in the
same row or .columnis pushed. Activation of diagonal
buttons will result in no tones being generated.
When the inputs to thEj MK5087 are electronically
activated, per Figure4, inputto a single row and column will
result in that dual-tone digit's being generated. Input toa
IV-2
single column will result in that column tone being
generated. Input to multiple columns will result in no tone
being generated.
INPUT CURRENT VS. INPUT VOLTAGE
Graph 1
800
Activation of a single row is not sensed by the internal
circuitry ofthe MK5087. If a single-row tone is desired, two
columns must be activated along with the desired row.
600
400
ROW AND COLUMN INPUTS
Figure 5
INPUT
CURRENT
V+
- JJA
200
2 3 4 5 6
RoW
INPUT
COLUMN
INPUT
7 8
9 10
INPUT - VOLTS
OUTPUT FREQUENCY DEVIATION
Table 1
tandard DTMF
(Hz)
V-, Pin 6
Tone Output
% Deviation
Frequency Using
From Standard
3.579545 MHz Crystal
f1
697
701.3
+0.62
f2
770
771.4
+0.19
ROW
Pin 6 is the power supply return pin and it is the
measurement reference for V+ (Pin 1).'
OSC IN, Pin 7; OSC OUT, Pin 8
13
852
857.2
f4
941
935.1
-0.63
15
1209
1215.9
+0.57
16
1336
1331.7
·0.32
f7
1477
1471.9
.Q.35
18
1633
1645.0
+0.73
Ol
The MK5087 contains an on-board inverter with sufficient
loop-gain to provide oscillation when working with a lowcost television color-burst crystal. The inverter's input is Osc
In (Pin 7) and output is Osc Out (Pin 8). The circuit is
designed to work with a crystal cutt03.579545 MHzto give
the frequencies in Table 1. The oscillator is disabled
whenever a keyboard input is not sensed.
LOW
GROUP
+0.61
HIGH
GROUP
of the state of the Single Tone Inhibit input.
Any crystal frequency deviation from 3.579545 MHz will be
reflected in the tone output frequency. Most crystals do not
vary more than ± .02%.
SINGLE TONE INHIBIT. Pin 15
The Single Tone Inhibit input is used to inhibit the
generation of other than dual tones. It has a pull-up to the
V+ supply and, when left floating or tied to V+, single or dual
tones may be generated as described in the paragraph
under row-column inputs. When forced to the V- supply,
any input situation that would normally result in a single
tone will now result in no tone, with all other chip functions
operating normally.
MUTE OUT. Pin 10
The Mute .output is a conventiona I CMOS gate that pu lis to
V-with no keyboard input and pulistotheV+ supply when a
keyboard entry is sensed. This output is used to control
auxiliary switching functions that are required to actuate
upon keyboard input. The Mute output switches regardless
IV-3
TONE OUT. Pin 16
The output pin is connected internally in the MK5087 to the
emitter of an npn transistor whose collector is tied to V+.
The input to this transistor is the on-chip operational
amplifier which mixes the row and column tones together.
TYPICAL DUAL-TONE WAVEFORM
(ROW 1. COL. 1)
Figure 8
The leitel of a dual-tone output is the sum of the levels of a
single-row and a single-column output. This level is
controlled by an on-chip reference which is not sensitive to
variations in the supply voltage.
ROW 2 TONE OUTPUT
Figure 6
v
o
U
T
SPECTRAL ANALYSIS OF WAVEFORM IN FIG. 8
(Vert-10 dB/div.• Horizontal-1 kHz/div.)
Figure 9
TIME~ 44.7 !lS/div.
COLUMN 4 TONE OUTPUT
Figure 7
v
o
U
T
TIME--"19 !lS/dlV.
OUTPUT WAVEFORM
The row and column output waveforms are shown in
Figures 6 and 7. These waveforms are digitally-synthesized
using on-chip D-to-A converters. Distortion measurement
of these unfiltered waveforms will show a typical distortion
of 9% or less.
The on-chip operational amplifier ofthe MK5087 mixes the
row and column tones to result in a dual-tone waveform.
Spectral analysis of this waveform will show that typically
all harmonic and intermodulation distortion components
will be -30 dB when referenced to the strongest
fundamental (column tone).
A commonly quoted method of dual-tone distortion
measurement is the comparison of total power in the
unwanted components (Le. intermodulation and harmonic
components) with the total power in the two fundamentals.
For the MK5087 dual-tone waveform. THD is -20 dB
maximum.
A simpler measurement may be made directly from the
screen of a spectrum analyzer by relating any component to
one of the fundamentals. The MK5087 dual-tone spectrum
will show all individual harmonic and IMD components are
typically at least -30 dB with respect to the column tone.
Figures 8 and 9 show a typical dual-tone waveform and its
spectral analysis.
TYPICAL APPLICATION
Figure 11 shows an application of the MK5087 in a
standard telephone set that uses the standard 2500-type
network. The tone levels and loop compensation that result
from this application meet the requirements of the U.S.
telephone systems.
IV-4
ABSOLUTE MAXIMUM RATINGS*
DC Supply Voltage V+ ............................................................................ 10.5 Volts
Any Input Relative to V+ ........................................................................ +0.30 Volts
Any Input Relative to V- ......................................................................... -0.30 Volts
Operating Temperature ...................................................................... -30°C to +60°C
Storage Temperature ........................................................................ -55°C to +85°C
Maximum Circuit Power Dissipation ................................. , 500 mW @ 25°C (see derating curve below)
·Stresses above those listed under "Absolute Maximum Ratings" maycause permanent damage to the device. This is a stress rating only and functional operation of the device at
these or any otller condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
POWER DISSIPATION DERATING CURVE
Figure 10
60't---------------'-
"C
SAFE OPERATING
RANGE
20
O,1------+----~~----+_----4-----_i
o
100
200
300
400
500
mW
ELECTRICAL CHARACTERISTICS
DC CHARACTERISTICS
(-30°C -< TA -< 60°C)
SYM
PARAMETER
MIN
TYP
MAX
UNITS
NOTES
V+
DC Operating Voltage
3.5
10.0
V
1
V 1L
Input Voltage Low - "0"
V-
30% ofV+
V
1, 11
V 1H
Input Voltage High - "1 "
70% ofV+
V+
V
1, 12
R1PSfj
Input Pull-up Resistance, STI
20
100
kD
3
..
-
AC CHARACTERISTICS
(-30°C::; TA::; 60°C; 3.0 V ::; V+ ::; 10.0 V)
SYM
PARAMETER
ISSB
Supply Current-Standby
(Pin 6, V+ = 3.5 V)
(Pin 6, V+ = 10.0 V)
Iso
10HX
10LX
10HM
10LM
MIN
Supply Current-Operating
(V+ = 3.5 V)
(V+ = 10.0V)
Output Drive, XMTR Switch-No Entry
(V+ = 3.5 V, V OHX = 2.5 V)
(V+ = 10.0 V, V OHX = 8.0 V)
-15
-40
TYP
MAX
UNITS
NOTES
0.25
0.50
100
200
~
iJ- A
2,7
2,7
1.0
5.0
2.0
15.0
mA
mA
2,6,8,9
2,6,8,9
-25
-100
mA
mA
Output Drive, XMTR Switch-Valid
Entry (V+ = 10.0 V, Output = 0.0 V)
0.1
10.0
}J.A
Output Drive, MUTE - Valid Entry
(V+ = 3.5 V, VOH = 3.0 V)
(V+ = 10.0V, V OH = 9.5 V)
0.5
1.0
2.0
4.0
mA
mA
Output Drive, MUTE - No Entry
(V+ = 3.5 V, VOL = 0.5 V)
(V+ = 10.0 V, VOL = 0.5 V)
0.5
1.0
2.0
4.0
mA
mA
Input Current Rows and Columns - SEE GRAPH 1
IV-5
AC CHARACTERISTICS (Continued)
SYM
PARAMETER
V NKD
Tone Output-No Key Down
t RISE
Tone Output Rise Time
V OUT
Tone Output Voltage
Row Tone (R L = 1K, 620 D, 330 D)
Col Tone (R L = 1K, 620 D, 330!l)
PE HB
Pre-Emphasis, High Band
DIS
Output Distortion
MAX
UNITS
-80
dBm
3.0
5.0
ms
317
396
400
500
504
630
mVRMS
mVRMS
1.0
2.0
3.0
dB
-20
dB
MIN
TYP
NOTES
5,9
1,3,6
1,3,6 .
4,10
NOTES:
1. All voltages referenced to V-.
2. All outputs unloaded.
3. TA = 25°C.
4. Any row plus any column at V+ 2':: 4 volts.
5. Time from a valid keystroke with no bounce to allow wave to go from
minimum to 90% of the final magnitude of either frequency.
6. True RMS Readings
8. Current Out Of Pin'6 One Key Depressed.
9. Crystal parameters AS:S 100 n. LM = 96 mHo CM = 0.02 pF. Ch = 5 pF. f =
3.579545 MHz. CL = 18 pF.
10. Output Distortion measured in terms of total out-of-band power relative to
the sum of Rowand Column fundamental power.
11. Column inputs require a voltage low (OJ of 10% of V+ (max).
12. R'OW inputs require a voltage high (1) of 90% of V+ (min).
7. Current Out Of Pin 6 No Key Depressed.
TYPICAL APPLICATION IN 2500-TYPE TELEPHONE
Figure 11
V'
14
13
R1iWl
ROW 2 TONE
12 ROW3 OUT 16
11 ROW4
MK5087
COL4
COL3
6
COL2
4
COL 1
12011
MUTE
OUT 10
3.579545
MHz
2500 - TYPE NElWORK
.005"F
--------~------------------,
C
G
2N6660
300K
1K
NOTE: Transient protection circuitry not shown_
IV-6
MOSTEI(.
TELECOMMUNICATIONS
Integrated Tone Dialer
MK5089(N/P I J)
FEATURES
o
Minimum external parts count
o
High-accuracy tones
o
Digital divider logic, resistive ladder network, and CMOS
operational amplifier on single chip
o
o
PIN CONNECTIONS
Figure 1
v+ ---..1
TONE DlSABLE~ 2
COL 1---" 3
Uses inexpensive 3.579545 MHz television color-burst
crystal
13....-ROW2
COL 3--" 5
12'+-ROW 3
OSC IN--" 7
OSCOUT~ 8
o Interfaces easily in electronic or ,uP dialing applications
o
COL 2--" 4
v----.. 6
Multiple key entry pin selectable to either single tone or
no tone
16~TONEOUT
15.
~TONE
' + - INHIBIT
14~ROW1
11 ' + - ROW4
10 ---..ANYKEY
DOWN
9'+-COL4
Tone Disable inhibits tone generation without defeating
the Any Key Down output
DESCRIPTION
The MK5089 is a monolithic integrated circuit fabricated
using the complementary-symmetry MOS (CMOS) process.
A member of the TONE 11* family of integrated tone dialers,
the MK5089 uses an inexpensive crystal reference to
provide eight different audio sinusoidal frequencies which
are mixed to provide tones suitable for Dual-Tone MultiFrequency (DTMF) telephone dialing.
The MK5089 was designed specifically for integrated tone
dialer applications that require the following: fixed supply
operation, a negative-true keyboard input, Tone Disable
input, stable output tone level, and an Any Key Down output
that is open circuit when no keyboard buttons are pushed
and pulls to the V- supply when a button is pushed.
Keyboard entries to the TONE 11* family of integrated tone
dialers cause the selection of the proper divide ratio to
obtain the required two audio frequencies from the
3.579545 MHz reference oscillator. D-to-A conversion is
accomplished on-chip by a conventional R-2R ladder
network. The tone output is a stairstep approximation to a
sine wave and requires little filtering for low-distortion
applications. The same operational amplifier that
accomplishes the current-to-voltage transformation
necessary for the D-to-A converter also mixes the low- and
'Trademark of Mostek Corporation
high-group signals. Frequency stability of this type of tone
generation is such that no frequency adjustment is needed
to meet standard DTMF specifications.
Pin connections are shown in Figure 1 and a block diagram
is shown in Figure 2.
FUNCTIONAL DESCRIPTION
V+, Pin 1
Pin 1 is the positive supply pin. The voltage on Pin 1 should
be between 3.0 and 10.0 volts, measured relative to V(Pin 6).
TONE DISABLE, Pin 2
The Tone Disable input is used to defeat tone generation
when the keyboard is used for other functions besides
DTMF signaling. It has a pull-upto the V+ supply and, when
tied to the V- supply, tones are inhibited. All other chip
functions operate normally.
ROW-COLUMN INPUTS,
Pins 3, 4, 5, 9,11,12,13,14
With Single Tone Inhibit at V+, connection of V- to a single
column will cause the generation of that column tone.
Connection of V- to more than one column will result in no
IV-7
BLOCK DIAGRAM
Figure 2
V+
i
R;""R;"R;~
14
13 12
11
RRI
1
V+
RRI
V-
RRI
RRI
KEYBOARD LOGIC
OSC
OUT
OSC
IN
B
~
7
I
SINE
WAVE
COUNTER
74
ROW
COUNTER
D/A
r- CONVERTER
VKB~
V+
J.%V+
COLUMN /.-COUNTER
t
KEYBOARD LOGICI
SINE
WAVE
COUNTER
~~
V+
r- CONVERTER D/A
VKB
V-
Rei
5
~C; C;
V+
b.
C4
2-0F-8 KEYBOARD
Figure 4
Each keyboard input is standard CMOS with a pull-up
resistor to the V+ supply. These inputs may be controlled by
a keyboard or electronic means. Open-collector TTL or
standard CMOS (operated off same supply as the MK5089)
may be used for electronic control. Refer to Figures 3 and 4.
The switch contacts used in the keyboards may be void of
precious metals, due to the CMOS network's ability to
recognize resistance up to 1 kfl as a valid key closure.
ELECTRONIC INPUT
Figure 3
V+
v- ____
SINGL E
i'O'NE
ifiiHiBi"T
6
tones being generated. The application of V- to only a row
pin or pins has no effect on the circuit. There must always
be at least one column connected to V- for row tones to be
generated. If a single-row tone is desired, it may be
generated bytying any two column pins and the desired row
pin to V-. Dual tones will be generated if a single-row pin
and a single-column pin are connected to V-. When Single
Tone Inhibit is tied to V-, only dual tones will be generated.
V- ____
TONE
--L-E
DISAB
9
FUNCTIONAL DESCRIPTION (Continued)
V+
2
15
Rei
4
16 TONE
r---- OUT
(>
R,'I
IRel
3
10 ANY K
DOWN
~
.----COLUMNS
U
U
.----ROWS
V-
V-, Pin 6
Pin 6 is the power supply return pin and it is the
measurement reference for V+ (Pin 1 ).
OSC IN, Pin 7; OSC OUT, Pin 8
The MK5089 contains an on-board inverter with sufficient
loop-gain to provide oscillation when working with a lowcost television color-burst crystal. The inverter's input is Osc
In (Pin 7) and output is Osc Out (Pin 8). The circuit is
designed to work with a crystal cutt03.579545 MHz to give
the frequencies in Table 1. The oscillator is disabled
whenever a keyboard input is not sensed.
Any crystal frequency deviation from 3.579545 MHz will be
reflected in the tone output frequency. Most crystals do not
vary more than ± .02%.
IV-8
OUTPUT FREQUENCY DEVIATION
TYPICALSINGLE- ROW LEVELVS.SUPPLYVOLTAGE
Table 1
Figure 5
Standard
DTMF
(Hzl
Tone Output
Frequency Using
3.579545 MHz Crystal
ITA ~ 25"C)
% Deviation
From Standard
11
12
Row 13
14
697
770
852
941
701.3
771.4
857.2
935.1
+0.62
+0.19 Low
+0.61 Group
-0.63
15
Col 16
17
18
1209
1336
1477
1633
1215.9
1331.7
1471.9
1645.0
+0.57
-0.32 High
-0.35 Group
+0.73
1.0
0.9
en
:;;
+1
c:c:
0.8
'"f--'
0
?
E
0.7
-1 3!
'"
0.6
-2
'j:.
'j:.
::J
0
?
-'
w
-4 w
>
-'
w
-5
-6
-7
-8
-9
-10
-11
z 0.4
0
f-
The Any Key Down output is used for electronic control of
receiver and/or transmitter switching and other desired
functions. It switches to the V- supply when a keyboard
button is pushed, and is open-circuited when not. The AKD
output switches regardless of the Tone Disable and Single
Tone Inhibit inputs.
SINGLE TONE INHIBIT, Pin 15
0
-'
w
0.5
>
w
ANY KEY DOWN, Pin 10
::J
-3 ?
0.3
0.2
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
SUPPLY VOLTAGE IV+) IVOLTS)
-'
w
z
0
f-
10.0
ROW 2 TONE OUTPUT
Figure 6
..
The Single Tone Inhibit input is used to inhibit the
generation of other than dual tones. It has a pull down to the
V- supply and when floating or tied to V-, any input situation
that would normally result in a single tone will now result in
no tone, with all other chip functions operating normally.
V
S-
When forced to the V+ supply, single or dual tones may be
generated as described in the paragraph under RowColumn Inputs.
T
TIME_44.7 fls/div
TONE OUT, Pin 16
COLUMN 4 TONE OUTPUT
Figure 7
The tone output pin is connected internally in the MK5089
to the emitter of an npn transistor whose collector is tied to
V+. The input to this transistor is the on-chip operational
amplifier which mixes the row and column tones together
and provides output level regulation.
The output tone level of the MK5089 is a function of supply
voltage. Figure 5 is a plot of the typical output level of a
single-tone output vs. supply voltage. The level of a dualtone output is the sum of the levels of a single-row and a
single-column output.
,
V
t=S
t-T
TIME __ 19 flS/ div
The row and column output waveforms are shown in
Figures 6 and 7. These waveforms are digitally-synthesized
using on-chip D-to-A converters. Distortion measurement
of these unfiltered waveforms will show a typical distortion
of 7% or less.
all harmonic and intermodulation distortion components
will be -30 dB down when referenced to the strongest
fundamental (column tone).
A commonly-quoted method of dual-tone distortion
measurement is the comparison of total power in the
unwanted components (i.e. intermodulation and harmonic
components) with the total power in the two fundamentals.
The on-chip operation amplifier of the MK5089 mixes the
row and column tones to result in a dual-tone waveform.
Spectral analysis of this waveform will show that typically
IV-9
For the MK5089 dual-tone waveform, THD is -20 dB
maximum.
A simpler measurement may be made directly from the
screen of a spectrum analyzer by relating anycomponentto
one of the fundamentals. The MK5089 dual-tone spectrum
will show all individual harmonic and IMD components are
typically at least 30 dB down with respect to the column
tone.
SPECTRAL ANALYSIS OF WAVEFORM IN FIG. 8
(Vert-10 dB/diy, Horizontal-1 kHz/div)
Figure 9
Figures 8 and 9 show a typical dual-tone waveform and its
spectral analysis.
TYPICAL DUAL-TONE WAVEFORM (ROW 1, COL. 1)
Figure 8
TONE LEVEL TEST CIRCUIT
Figure 10
v+
3.579545 MHz
CRYSTAL
0
7 OSC
TONE 16
IN
OUT
MK5089
8 OSC
OUT
3
Cal'
4
14
COl2
V OUT
Rl ~'O K
-=
ROW1
V6
NOTE: Keyboard connections shown are for Rowtone level test. Only Coi1
(Pin 3) should be connected to V- for Column tone level test.
IV-10
ABSOLUTE MAXIMUM RATINGS*
DC Supply Voltage V+ ............................................................................ 10.5 Volts
Any Input Relative to V+ ...................................................................... " +0.30 Volts
Any Input Relative to V- ......................................................................... -0.30 Volts
Operating Temperature ...................................................................... -30°C to +60°C
Storage Temperature ........................................................................ -55°C to +85°C
Maximum Circuit Power Dissipation .................................. 500 mW @ 25°C (see derating curve below)
lI-Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device, This is a stress rating only and functional operation of the device at
these or any other condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
POWER DISSIPATION DERATING CURVE
60 - 1 - - - - -___
TA 40
(acl 20
SAFE OPERATING
RANGE
DERATE AT 9 mW/'C
WHEN SOLDERED INTO
PC BOARD.
O~--~~--'----r--~r---+----
o
100
200
300
500
400
mW
ELECTRICAL CHARACTERISTICS
DC CHARACTERISTICS
(-30°C::; TA::; 60°C)
MAX
UNITS
3.0
10.0
V
Input "0"
V-
30% ofV+
V
V IH
Input "1 "
70% ofV+
V+
V
RI
Input Pull-Up Resistor
20
100
kO
MAX
UNITS
NOTES
-7
dBm
1,7
3
dB
-20
dB
2,6
5.0
ms
3
SYM
PARAMETER
MIN
V+
Supply Voltage
V IL
TYP
NOTES
AC CHARACTERISTICS
(-30°C::; TA::; 60°C; 3.0 V ::; V+ ::; 10.0 V)
SYM
PARAMETER
MIN
V OUT
Tone Output (R LOAD = 10K)
-10
PE HB
Pre-Emphasis, High Band
2.4
DIS
Output D(stortion
t RISE
Rise Time
IAKD
Any Key Down Sink Current to V-
IAKDO
AKD Off-Leakage
2.0
!J.A@5V
Iso
Supply Current-Operating
2.0
mA@3.5V
5
ISST
Supply Current-Standby
200
!J. A@10.0V
4
V NKD
Tone Output - No Key Down
(R LOAD = 10 kf!)
-80
TYP
2.7
2.8
500
NOTES
1. Single-tone, low-group. Any V+ between 3.4 and 3.6 V. OdBm = .775 V.
2. Anydual-tone. AnyV+ between 3.4 and 1C.DV. See Figure 1Oand Figure 11.
3. Time from a valid keystroke with no bounce to allow the waveform togo from
min. to 90% of the final magnitude of either frequency. Crystal parameters·
RS:S 100 n, LM = 96 mH, CM = 0.02 pF, Ch = 5 pF. f = 3.579545 MHz ±
0.02%, CL = 18 pF.
!J. A @5V
4.
5.
6.
7.
IV-11
dBm
Stand-by condition is defined as no keys activated, To :;: Logical 1, Single Tone
iiiiiT5Tt :;: Logical O.
One key depressed only. Outputs unloaded.
Output Distortion measured in terms of total out-of-band power relative to the
sum of Rowand Column fundamental power.
For 3.4 V:S V+
:s 10.0 V, Tone Output is typically [0.0855 (V+I ± 1 dB] mVrms .
Refer to Figures 5 and 10.
IV-12
MOSTEI(.
TELECOMMUNICATIONS
MK5087/89 Electronic Drive
The purpose of this application brief is to provide
information as to the various means by which the MK5087
and MK5089 keyboard inputs may be electronically driven.
The MK5087 keyboard inputs can be driven by both CMOS
and TIL logic. With the MK5087, the row inputs must be
pulled low for a valid key entry. Since the MK5087 has
internal pull-up resistors on the rows and pull-down
resistors on the columns, external pull-ups are only needed
when driving the column inputs with TIL open-collector
logic. The circuit diagram in Figure 1 shows the interface for
electronically driving the MK5087.
Figure 1
.......<
~~"""""
V+
V+
4.7 K
(4x)
R1
.J"I_ _ _ _ _ _ _ __
R2 - - - - f " L - R3 _ _ _ _ _........I1L--_ __
R4 _ _ _ _ _ _ _-lr"1..C1
-r-1~
_ _ _ _ _ _ __
C2
C3
C4
NUMBER DIALED
rI~
_____
----f"L-rL..1
6
8
V+
~~+--+~~r-1~4~ROW1
Dc)-~---+-+--+-t---:-=tROW 2
iY)-+--f-+--+-_'.;.,3'-1ROW 3 TONE t - - -.....
2 ROW 4 OUT 16
Cx)-....:::;---+-+--+-t-:'':-t
11
MK50B7
-o
~---~ t>-~~~t-4-~COL'
~-~-~-~~-~3COL2
~_f-~_ _ _ _4~COL3
9
D
TONEOUT~
.j
1K
:~_~_ _4-_ _ _ _~5 COL4
7
3.579545
I-tt
j+tid
MHz
~
°1~C
MUTE 10
OSC
BOUT V-
6
V-
* Only needed when using TIL open-collector logic
** Inverters and buffers are not needed if the driving signals Rl - R4 are inverted and R1 - C4 can drive a 4.7 kH load.
NOTE:
U1 is a hex inverter (TTL· 7404. 74LS04; TTL open·collector ·7405. 74LS05; CMOS· 4049)
U2 is a hex buffer (TTL open· collector • 7407, 74LS07. 7417, 74LS1 7; CMOS· 4050)
tt '2:: 50 ms and 45 ms 2: tid 2: 3 5 to meet Bell Specifications PUB 47001, section 4.3
tt ;;: tone duration time
tid;;:: interdigit time
IV-13
TONE
OUTPUT
The MK5089 row and column inputs must be pulled low for
a valid key entry. The MK5089 has internal pull-up resistors
for both the rows and columns. Therefore, the MK5089
keyboard inputs may be driven by CMOS, TTL, and TTL
open-collector logic without the requirement for external
pull-up resistors. The interface for electronically driving the
MK5089 is shown in Figure 2.
Figure 2
v+
R'
JI'---_ _ _.,--_ __
R2
---r--L-.
r1
11-
R3
R4
v·
*
Cx:I--------:-;1
ROW'
'4 _ _
:::O-L..--------,-i
3 BOW 2
_--f----i
1'::0--------,2-iBOW 3
')o-~-------..:.=.tROW
"
C,
.J""l
6
8
---~---~
~cr-------t5 COL3
'OK
~~)--L..--------~9~COL4
D
TONEOUT~
~
4
MK5089
1)O-~-------~41COL2
C3-..r-L-C4 _ _ _ _ _ _---'11NUMBER DIALED'
TONE·
""'-6----<.--0 OUTPUT
3 COL1
r1
C2
TONE
OUT
~tt
3.579545
MHz
--i 1+ tid
7
OSC
IN
OSC
8 OUT
AKD
'0
v6
v* Inverters are not needed i~ the driving signals Rl
- C4 are inverted and can drive a 20 k!lload.
NOTE:
Ul and U2 are hex inverters (TIL - 7404• .74LS04; TIL open-collector - 7405. 74LS05; CMOS - 4049)
tt;::: 50 ms and 45 ms 2:: tid:2:: 3 5 to meet Bell Specifications PUB 47001, section 4.3
tt = tone duration time
tid = interdigit time
V+ andV- ontheMK5087 and MK5089 should be typically
connected to the supply used for the electronic drive
circuitry. However, care must be taken to ensure that V+
does not exceed the 10 volt maximum as specified in the
MK5087 and MK5089 data sheets. The logic levels present
at the MK5087 and MK5089 inputs must meet the criteria
specified in the respective data sheets and repeated in Table
1. The high logic level must not exceedV+ and the low logic
level must not be more negative than V-.
LOGIC LEVEL REQUIREMENTS
Table 1
MK5087
MK5089
Column High
2:: .7 V+
2::.7 V+
Column Low
:5.1 V+
:5.3 V+
Row High
2::.9 V+
2::.7 V+
Row Low
:5.3 V+
:5.3 V+
MOSTEI{®
TELECOMMUNICATIONS
Integrated Tone Dialer
MK5091(N)
FEATURES
PIN OUT
Figure 1
D CEPT Compatible
D High Accuracy tones
OP AMP OUT ___ 1
v+ __ 2
D Digital divider logic, resistive ladder network, CMOS
operational amplifier, and Bipolar driver on chip
TONE
DISABLE-COL1 _ _
D Uses inexpensive 3.579545 MHz television color-burst
crystal
COL2_
COL3 _ _
D
Invalid key entry can result in either single tone or no
tone
3
4
5
6
v---7
OSCIN-OSCOUT--
D Designed for use with calculator type (Class A contact)
8
9
18 _ _ BIPOLAR OUTPUT
17 _ _ BIPOLAR INPUT
16 _ _ SINGLE TONE
INHIBIT
1 5 - - iiQvii1
14 ___ Rc5'W2
13 ___ RCiWJ
1 2 ___ iffiW4
11 _ _ ANY KEY DOWN
10--COL4
keyboards or 2-of-8 keyboards
D Low standby power for continuous on line operation
DESCRIPTION
The MK5091 is a monolithic integrated circuit fabricated
using the complementary-symmetry MOS (CMOS) process.
A member of the TONE II family of integrated tone dialers,
and designed specifically to meet European CEPT
specifications, the MK5091 uses an inexpensive crystal
reference to provide eight different audio sinusoidal
frequencies, which are mixed to provide tones suitable for
Dual-Tone MUlti-Frequency (DTMF) telephone dialing.
crystal reference which eliminates any need for frequency
adjustment.
The keyboard entries select the proper digital dividers to
divide the 3.579545 MHz to obtain the unique audio
frequencies required. These digital signals are then
processed by a R-2R ladder network, and current-to-voltage
transformation is made by an on-chip amplifier. This is a
conventional D-to-A converter and yields sine waves of
sufficient purity that filtering is easily accomplished. The
same amplifier accomplishes summing ofthe low-and-high
group tones to obtain the required dual-tone signal.
Frequency accuracy of the network is obtained via the
The MK5091 meets the following integrated tone dialer
application requirements: compatibility with European
CEPT specifications, regulated-supply operation, single
contact keyboard input, Tone Disable input(TD), Single Tone
Inhibit input (STI), stable output tone level, and an Any Key
Down output (AKD) that is open circuit when no keyboard
buttons are pushed, and pulls to the V+ supply when a
button is pushed.
Supplied in an 18-pin plastic package, the MK5091
provides two pins for tone filtering of the multiple stairstep
output sine wave. Typically, only three resistors, and two
capacitors are needed to produce sine waves of sufficient
purity to meet the CEPT harmonic distortion specification.
The MK5091 high group pre-emphasis before filtering is
typically 2.0 dB. Output level meets European applications.
IV-15
BLOCK DIAGRAM OF MK5091
Figure 2
V+
15
14
12
13
BIPOLAR OUTPUT
T2
RRI
RR
+18
~
V+
RRI
V+
BIPOLAR INPU T
RRI
I
KEYBOARD LOGIC
-
J
ROW
COUNTER
-74
OSC
IN
V+
I
OSC
OUT 9
COLUMN
COUNTER
8
I
KEYBOARD LOGIC
I
17
i
h
SINE
WAVE
COUNTER
f+
CONVERTER
112V>- I-
1= f+
~
SINE
WAVE
COUNTER
VKB
11 ANY KEY
DOWN
V;.J
DIA
~
1
OPAMPOUT
,/
~+
~ DIA
CONVERTER
V+
3
TONE
i5iSAiilE
ReI
ReI
16
ReI
ReI
4
5
6
SINGLE TONE
iiiiHiBiT
V-
10
r
V-
OUTPUT TONE LEVELS
frequency of these poles, but a practical limit is reached
when the amount of pre-emphasis becomes altered.
The output tone level of the MK5091 is proportional to the
appl ied DC supply voltage. Operation wi II norma IIy be with a
regulated supply. This results in enhanced temperature
stability, since the supply voltage may be made temperature
stable.
DISTORTION
The dualtone harmonic requirement ofthe European CEPT
specification is as follows:
The level of any individual unwanted frequency component
relative to the fundamental of the low group shall not
exceed the following limits. (OdBm = 0.775 Volts).
TONE DISABLE, Pin 3
The Tone Disable input is used to disable tone generation
when the keyboard is used for other functions besides
DTMF signaling. This input has a pull up to the V+ supply,
and when left floating or connected to V+, tones are
generated normally. When forced to the V- supply, tone
generation is disabled. All other chip functions operate
normally.
ANY KEY DOWN, Pin 11
In the frequency band 3.4 to 50 kHz - 33 dBm at 3.4 kHz
falling at 12 dB per octave to 50 kHz.
The Any Key Down output is used for electronic control of
receiver and/or transmitter switching and other desired
functions. It switches to the V+ supply when a keyboard
button is pushed, and is open circuited when not. The mute
output switches regardless of the Tone Disable and SingleTone Inhibit inputs.
In the frequency band above 50 kHz - 80 dBm.
SINGLE TONE INHIBIT, Pin 16
A two-pole filter is required to fulfill the above distortion
requirements. This filter may be constructed using the bipolar transistor available at pins 17 and 18 of the MK5091 .
The two poles should be placed at approximately 3.4 kHz.
Additional margin may be obtained by reducing the
The Single Tone Inhibit input is used to inhibit the
generation of other than dual tones. It has a pull up to the V+
supply and when left floating or tied to V+, single or dual
tones may be generated as described in the paragraph
under row-column inputs. When forced tothe V-supply, any
In the frequency band 300 to 3400 Hz - 33 dBm.
IV-16
input situation that would normally result in a single tone
will now result in no tone, with all other chip functions
operating normally.
ROW 2 TONE OUTPUT
Figure 3
OSCILLATOR
The network contains an on-board inverter with sufficient
loop-gain to provide oscillation when working with a low
cost television color-burst crystal. The inverter's input is
OSC IN (pin 8) and output is OSC OUT (pin 9). The circuit is
designed to work with a crystal cut to 3.579545 MHz to give
the frequencies in Table 1.
Any crystal frequency deviation from 3.579545 MHz will be
reflected in the tone output frequency. Most crystals do not
vary more than ± .02%.
v
o
U
T
TIME-44.7I's/div
COLUMN 4 TONE OUTPUT
Figure 4
OUTPUT FREQUENCY DEVIATION
Table 1
Standard
DTMF
(Hz)
Tone Output
Frequency Using
3.579545 MHz Crystal
I,
12
ROW 13
I.
697
770
852
941
701.3
771.4
857.2
935.1
+0.62
+0.19 LOW
+0.61 GROUP
-0.63
15
COL 16
17
18
1209
1336
1477
1633
1215.9
1331.7
147-1.9
1645.0
+0.57
-0.32
HIGH
-0.35 GROUP
+0.73
% Deviation
From Standard
OP AMP OUT, Pin 1
The op amp out pin is connected internally in the MK5091
to the CMOS output transistor of an operational amplifier.
This operational amplifier mixes an output level referenced
to the supply voltage.
BIPOLAR INPUT, Pin 17
The bipolar input pin is connected internally in the MK5091
to the base of a un-committed on-chip bipolar transistor.
This transistor is generally used to construct a multi-pole
filter for low distortion applications.
v
o
U
T
The on-chip operational amplifier of the MK5091 mixes the
row and column tones together to result in a dual-tone
waveform. Spectral analysis of this waveform will show
that typically all harmonic and intermodulation distortion
components will be -30 dB down when referenced to the
strongest fundamental (column tone).
Figures 5 and 6 show a typical dual tone waveform and its
spectral analysis.
TYPICAL DUAL TONE WAVEFORM
(ROW 1. COL 1)
Figure 5
BIPOLAR OUTPUT, Pin 18
The bipolar output pin is connected internally in the
MK5091 to the emitter ofthe bipolar transistor described by
the paragraph Bipolar Input, above.
OUTPUT WAVEFORM
The row column output waveforms are shown in Figures 3
and 4. These waveforms are digitally synthesized using
on-chip D-to-A converters. Distortion measurements of
these unfiltered waveforms will show a typical distortion of
7% or less.
IV-17
KEYBOARD CONFIGURATION
Figure 7
SPECTRAL ANALYSIS OF WAVEFORM
(Vert-10 dB/diy, Horizontal-1 kHz/ divl
Figure 6
~
COL ......I---:-:-:-::7'....
~ ••" - - - - -.....~ ROW
CLASS A KEYBOARD
c; 1.:..
-:_-_-_-_-_.-.-1::1:::
2 OF 8 DTMF KEYBOARD
ELECTRONIC INPUT
Figure 8
VV+_ . . . . . . . . . "
...._ __
..
V+
COLUMNS
, . . . - - - ROWS
V- •••••••••
LJ
ROW AND COLUMN INPUTS
Figure 9
V+
ROW AND COLUMN INPUTS
The MK5091 N features inputs compatible with the
standard 2-of-8 keyboard. the inexpensive single contact
(form Al keyboard, and electronic input. Figure 7 shows how
to connect to the two keyboard types and Figure 8 shows
waveforms for electronic input. The inputs are static, i.e.
there is no noise generation as occurs with scanned or
dynamic inputs.
The internal structure of the MK5091 N inputs is shown in
Figure 9. RRI and Rei pull in opposite directions and hold
their associated input sensing circuit turned off. When one
or more row or column inputs are tied together, however,
the Input Sensing Circuits sense the "1/2 Level" and
deliver a logic signaltothe internal circuitryofthe MK5091
and cause the proper tone or tones to be generated.
When operating with a keyboard, normal operation would
be with STI floating or at V+. This allows single-tone
operation when more than one button is activated.
Activation of diagonal buttons will result in no tones being
generated.
ROW INPUT
COLUMN
INPUT
Typical input impedances of row and column pull-up
resistors may be inferred from Figures 10 and 11.
INPUT-VOLTS
Figure 10
800
ROW
OR
COLUMN
INPUT
CURRENT
-p.A
600
400
200
1
If a single tone is desired for test, but is not desired for
operation, STI can be connected to V-. This allows dual-tone
operation with single key closure, but prevents any output
tOfles when more than one button in the same row or
column is activated.
2 3 4 5 6 7
iI
9 10
INPUT - VOLTS
ROW OR COLUMN INPUT VOLTS
Figure 11
8
When the inputs to the MK5091 are electronically
activated, per Figure 8, inputto a single row and column will
result in that dual-tone digit's being generated. Input to a
single column will result in that column-tone being
generated. Input to multiple columns will result in no tone
being generated.
TYPICAL
PULL UP
CURRENT
RANGE
6
INPUT
CURRENT 4
-p.A
2
0.3
VOLTS
25"C
Activation of a single row is not sensed by the internal
circuitry of the MK5091 N. If a single row tone is desired,
two columns must be activated along with the desired row.
IV-18
.25
.50
.75
INPUT - VOLTS
1.0
1.25
1.5
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage V+ ...................... , ........................................................ 10.5 Volts
Voltage on any pin relative to V- ................................................................... -0.3 Volts
Voltage on any pin relative to V+ ................................................................... +0.3 Volts
Operating Temperature, TA ..... " ............................................................ -30 D C to +60 D C
Storage Temperature ........................................................................ -55 D C to +85 D C
Maximum circuit power dissipation ......................................... 500 mW, @ 25 D C, See derating curve
*Stresses above those listed under "Absolute Maximum Ratings" maycause permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliabiliW.
POWER DISSIPATION DERATING CURVE
60 - t - - - - -__
TA 40
SAFE OPERATING
RANGE
(acl 20
DERATE AT 9 mW/'C
WHEN SOLDERED INTO
PC BOARD.
O;---~----~--T---~---+--
o
100
200
300
400
600
mW
OPERATING CHARACTERISTICS
-30 D C ::::: TA::::: +60 D C; all voltages referenced to V- = 0.0 volts
SYM
PARAMETER
MIN
V+
V+
Supply Voltage
Operating (Generating Tones)
Standby (DC Switching Only)
V IH
V IL
V CIH
VCll
V RIH
VRll
Inputs:
Tone Disable, Single Tone Inhibit
Input High (Logic 1)
Input Low (Logic 0)
Columns (1-4)
Input High (Column ON)
Input
Low (Column OFF)
i
Row (1-4)
Input High (Row OFF)
Input Low (Row ON)
RI
Input Resistance (TD & STI only)
V OUT
Tone Output Level, Pin 1
PE HB
DIS
Pre-Emphasis, Highband (Unfiltered)
Output distortion measured in terms
of out of band power relative to
RMS sum of row and column
fundamental power
TYP
MAX
UNITS
NOTES
3.0
2.0
10.0
10.0
V
V
1
.7V+
0.0
V+
.3V+
V
V
.7V+
0.0
V+
.1 V+
V
V
.9 V+
0.0
V+
.3 V+
V
V
20
100
kO
10
-10.0
-8.5
-7.0
dBm
2,11
1.0
2.0
3.0
dB
3,11
-20
dB
4,11
5
ms
5
J.lA
6
10
J.lA
7
tRiSE
Rise Time
IAKDON
Any Key Down Source Current to V+
IAKDOFF
Any Key Down Off Leakage
lop
Supply Current - Operating @ 3.5 V
@ 10.0V
1.0
5.0
2.0
mA
mA
8
ISB
Supply Current - Standby @ 10.0 V
1.0
200
J.lA
9
V NKD
Tone Output - No Key Down
-80
dBm
ROA
Op Amp Output Resistor
IDA
Op Amp Output Current @ 3.0 V
500
10
250
IV-19
kO
12
J.lA
12
6. AKD is open drain P-channel transistor. Minimum current defined is valid'
with V+ = 3.5 volts, V AKD = 3.0 volts. AKD pulls to V+ when valid key is
depressed.
NOTES
1. Voltage at which mute output will respond to any key closure, chip disable =
7. V+
O.
= 10 volts,
VAKD
= 0 volts.
8. For any ambient temperature in the range *30°C to +60 D C. Single key
depressed only. Crystal as in Note 5. Measured at Pin 6. Outputs open
circuited.
9. Standby condition is defined to be no keys activated, TiS = logical 0, single
tone inhibit = logical 1. Outputs and inputs open circuited.
2. Single tone. low group. Any supply voltage between 3.4 V and 3.6 V. Output
amplitude is linearly proportional to supply voltage. This condition valid for
'-30 o < TA <60°C .. 5ee test circuit
3. High group output level relative to low group level. Valid for -30 o e < TA <
60°C
4. Any supplY,voltage between 3.4 V and 10.0 V. See test circuit.
5. Time from a valid keystroke with no bounce to allow the output waveform to
go from its minimum to' 90% of the final magnitude of either frequency.
Crystal parameters a~e defined to be Rs = 100 n, Lm =96 mHo eM ::0 0.02 pF,
and Ch = 5 pF. F = 3.579545 MHz. Any -30°C < TA < +60°C.
e
10. 25°C.
11 .RLOAD (pin 18) = 620 !l @l 3.4 V <; V+ <; 10 V. See test circuit.
12. Op Amp Output Resistor size is determined by the capacitance on Pin 1. The
10 k!l resistor shown in test circuit is correct for typical filter circ·uit. If
capacitance at this pin is too large, a smaller value or resistance will be
required.
TEST CIRCUIT
Figure 12
2
18
+
-----...-
V SUPPLY
17
MK5091
RLOAD
-
1
-
_L-
---- V BIAS
7
V BIAS = .5 V WHEN V SUPPLY
V BIA,S
=0
~
4,0 V
V WHEN V SUPPLY> 4.0 V
IV-20
--
10 K
--r:-
MOSTEI(.
TELECOMMUNICATIONS
Integrated Tone Dialer
MK5092(N)
FEATURES
PIN CONNECTIONS
Figure 1
o Designed for use with hybrid network
o
Internal regulation of tone amplitudes
o
Tone frequencies within 0.65% for 12 standard
frequencies
o
o
16~TONEOUT
TONE
DISABLE~2
1~3
COLUMN 2+4
13~ROW2
COLUMN 3+5
12~ROW3
V-+6
Internal loop compensation and pre-emphasis
OSCIN+7
o
Uses inexpensive 3.579545 MHz television color-burst
crystal for accurate tones
o
Tone-disable capability
o
Uses either calculator-type (Form A Contact) or 2-of-8
dual-contact keyboard
o
Pin-selectable single-tone capability
o
MUTE output for electronic switching
o
Minimum external parts count
SINGLE TONE INHIBIT
14~ROW1
COLUMN
Meets or exceeds U.S. Telephone Specifications for tone
levels and distortion
15~
osc
OUT~8
11.-ROW4
10+MuTE
9~COLUMN4
The MK5092 was designed for tone-dialer applications that
require the following characteristics: wide range supply
operation with loop-compensated tone regulation, singlecontact keyboard capability, tone-disable capability, and a
mute output that pulls to V- until a keyboard entry is
detected and then pulls to V+.
DESCRIPTION
The MK5092 is a monolithic integrated circuit fabricated
using the complementary-symmetry MOS (CMOS) process.
A member of the Tone 11* family of integrated tone dialers,
the MK5092 uses an inexpensive crystal reference to
provide the eight standard signaling frequencies which are
mixed to provide Dual-Tone-Multi-Frequency (DTMF)
telephone dialing.
Any valid keyboard entry to the Tone 11* family of integrated
tone dialers causes the selection of the proper divisor to
obtain the required frequency from the internal 3.579545
MHz oscillator. Digital-to-analog conversion ofthe resultant
frequency is done internally with a conventional R-2R
ladder network. The tone output is a stairstep approximation
of a sinusoid and requires little filtering for low-distortion
applications.
*Trademark of Mostek Corp.
IV-21
BLOCK DIAGRAM
Figure 2
V+
14
13
11
12
11
RRI
V+
RRI
RRI
RRI
10
VKB
MUTE
I STATIC PROTECTION I
I
o SC
o UT
KEYBOARD LOGIC
t
8
ROW
COUNTER
74
I-
SINE
WAVE
COUNTER
DIA
f--
CONVERTER
-
1/2 V+
o SC
IN
>-
COLUMN ~
COUNTER
7
I
KEYBOARD LOGIC
I
SINE
WAVE
COUNTER
+
VKB
DIA
r-f- CONVERTER
:~
V+
ISTATIC PROTECTION I
RCI
RCI
V+
16
2
TONE
OUT
TONE
DI SABLE
15 S INGLE
RCI
TONE
I NHIBIT
RCI
V-
3
4
5
9
61
VFUNCTIONAL DESCRIPTION
Figure 4 shows how to connect to the two keyboard types
and Figure 5 shows waveforms for electronic input. The
inputs are static, i.e. there is no noise generation as occurs
with scanned or dynamic inputs.
(Refer to Figure 2 for Block Diagram)
V+, Pin 1
Pin 1 connects the positive supply to the MK5092.
TONE DISABLE, Pin 2
TONE DISABLE disables the summing operational
amplifiers and is used to inhibit tone generation to allow the
keyboard to be used for functions other than DTMF
signaling. The TONE DISABLE input has an internal pull-up
resistor and, when left unconnected or connected to V+,
allows normal generation of tones. When connected to V-,
TONE DISABLE inhibits the tone output. MUTE and other
functions operate normally, regardlessofthe status of Pin 2.
ROW AND COLUMN
INPUTS,
Pins 3, 4, 5, 9, 11, 12, 13, 14
The MK5092 features inputs compatible with the standard
2-of-8 keyboard, the inexpensive single-contact (Form A)
keyboard, and electronic inputs.
The internal structure of the MK5092 inputs is shown in
Figures 2 and 3. RRI and ReI pull in opposite directions and
hold their associated input sensing circuit turned off. When
one or more row or column inputs are tied together,
however, the input sensing circuits sense the "Y2level" and
deliver a logic signal to the internal circuitry ofthe MK5092
and cause the proper tone or tones to be generated.
When operating with a keyboard, normal operation is for
dual-tone generation when any single button is pushed and
single-tone operation when more than one button in the
same row or column is pushed. Activation of diagonal
buttons will result in no tones being generated.
When the inputs to the MK5092 are electronically
activated, per Figure 5, an inputtoa single row and a single
column will result in that dual-tone digit being generated.
Input to multiple columns only will result in no tone being
generated.
Activation of a single row is not sensed by the internal
IV-22
circuitry of the MK5092. If a single-row is desired, two
columns must be activated along with the desired row.
MUTE, Pin 10
The MUTE output is used for electronic control of receiver
and/or transmitter switching. The MUTE output is
connected to V- when no keyboard input is present and
switches to V+ upon recognition of a keyboard input. MUTE
switches regardless of the condition of SINGLE TONE
INHIBIT and TONE DISABLE inputs.
ROW AND COLUMN INPUT CIRCUITRY
Figure 3
V+
SINGLE TONE INHIBIT, Pin 15
ROW
INPUT
. The SINGLE TONE INHIBIT input is used to control the
generation of single tones. It hasan internal pull-up resistor
to V+ and when not connected or connected to V+, either
single or dual tones may be produced as described in the
paragraphs on row and column inputs. With SINGLE TONE
INHIBIT connected to V-, any input situations that would
normally produce a single tone will produce no tone.
COLUMN
INPUT
KEYBOARD CONFIGURATION
TONE OUT, Pin 16
1
Figure 4
.._-----64
COL .....
An internal operational amplifier mixes the row and column
tones and regulates the output level. The output of this
amplifier is connected to the base of a ! npn transistor. The
collector of this internal transistor is connected to V+ and
the emitter is brought out to TONE OUT.
..
4'--_ _--''''~ ROW
CLASS A KEYBOARD
~j;_"'COL
~ ·-'-------l"'~ROW
OUTPUT FREQUENCY DEVIATION
Table 1
2-0F-S KEYBOARD
ELECTRONIC INPUT
Figure 5
Standard DTMF
(Hz)
:~ ........ ·TIL-___ COLUMNS
~: .......... LJr--- ROWS
V-, Pin 6
Tone Output
Frequency Using
3.579545 MHz Crystal
11
697
701.3
+0.62
ROW f2
13
770
771.4
852
857.2
+0.19.LOW
+0.61 GROUP
14
941
935.1
15
1209
1215.9
COL 16
17
1336
1331.7
1477
1471.9
+0.57
-0.32 HIGH
-0.35 GROUP
IS
1633
1645.0
+0.73
v-
is the return for the MK5092 supply. All MK5092
voltages and signals are referenced to V-.
ROW 2 TONE OUTPUT
Figure 6
OSC IN, Pin 7; OSC OUT, Pin 8
% Deviation
From Standard
The MK5092 contains an on-board inverter with sufficient
loop gain to provide oscillation using a crystal. The inverter
input is OSC IN and the output is OSC OUT. When using a
3.579545 MHz crystal, the MK5092 will produce the
frequencies in Table 1. Crystal frequency deviation, usually
less than ±O.02%, will be reflected in the tone output
frequency.
IV-23
t
V
0
U
T
+
-0.63
SPECTRAL ANALYSIS OF WAVEFORM IN FIGURE 8
(Vert-10 dB/ div, Horizontal-1 kHz/ div)
COLUMN 4 TONE OUTPUT
Figure 7
Figure 9
OUTPUT WAVEFORM
The row and column output waveforms, shown in Figures 6
and 7, are digitally synthesized sinusoids produced by
internal dividers and digital-to-analog converters. Distortion
measurement, discussed in the next section, of these
unfiltered output waveforms shows a typical total harmonic
distortion of 7% or less. Spectral analysis of the dual-tone
waveforms shows that all harmonic and intermodulation
distortion components are typically at least -30 dB when
referenced to the strongest fundamental. Figures 8 and 9
show a dual-tone waveform and its spectral plot.
TYPICAL DUAL-TONE WAVEFORM
(ROW 1, COL. 1)
Figure 8
DISTORTION MEASUREMENTS
A commonly used method of dual-tone distortion
measurement is the comparison of total power in the
unwanted components (i.e. intermodulation and harmonic
components) with the total power inthetwofundamentals.
For the MK5092 dual-tone waveforms, THD is -20 dB
maximum.
A simpler measurement may be made directly from the
screen of a spectrum analyzer by relating any component to
one ofthe fundamentals. The MK5092 dual-tone spectrum
shows all individual harmonic and intermodulation
distortion components are typically at least -30 dB with
respect to the column tone.
IV-24
ABSOLUTE MAXIMUM RATINGS*
See Note 1
Supply Voltage V+ ............................................................................. +10.5 Volts
Voltage on any Pin Relative to V+ .................................................................. +0.3 Volts
Voltage on any Pin Relative to V- .................................................................. -0.3 Volts
Operating Temperature .............................................................. " ........ O°C to +60°C
Storage Temperature ........................................................................ -35°C to +85°C
Maximum Circuit Power Dissipation ....................................... 500 mW @ 25°C (See Derating Curve)
*Stresses above those listed under "Absolute Maximum Ratings" maycause permanent damage to the device. This is a stress rating only and functional operation of the device at
these or any other condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
POWER DISSIPATION DERATING CURVE
601----_~
40
20
SAFE
OPERATING
RANGE
O~--~--~----~--~--~---
100
200
400
TOTAL DISSIPATION
(mWj
NOTE: Derate 9 mW/oC from 500 mW @ 25°C.
ELECTRICAL CHARACTERISTICS
DC CHARACTERISTICS
(O°C ~ TA ~ 60°C)
See Note 1
SYM
PARAMETER
V+
Supply Voltage
Operating (Generating tones)
(Telephone loop supply)
Operating (Generating tones)
(Fixed voltage supply)
Standby (de switching only)
MIN
TYP
MAX
UNITS
NOTES
3.5
10.0
V
13
3.8
3.0
10.0
10.0
V
V
13
2,13
VIH
VIL
CHIP DISABLE, SINGLE TONE INHIBIT
Input High (Logic 1)
Input Low (Logic 0)
70% ofV+
0.0
V+
30% ofV+
V
V
VIH
VIL
Columns (1-4)
Input High (on)
Input Low (off)
70% ofV+
0.0
V+
10% ofV+
V
V
VIH
VIL
Rows (1-4)
Input High (off)
Input Low (on)
90% ofV+
0.0
V+
30% ofV+
V
V
125
125
kO
kO
kO
kO
RRI
RCI
Pull-Up/Down Resistors
Row Inputs
Column Inputs
TONE DISABLE
SINGLE TONE INHIBIT
20
20
IV-25
15
15
60
60
7,12
7,12
7,13
7,13
I
AC CHARACTERISTICS
(O°C :s: TA :s: 60°C)
See Note 1
SYM
PARAMETER
VOUT
VOUT
Tone Output (RL = 600
3.8 V, VBIAS = 1.5 V)
Row Tone
Column Tone
VOUT
VOUT
Tone Output (RL = 320 n, V+
10.0 V, VBIAS = 3.5 V)
Row Tone
Column Tone
1M
MUTE current
Source
1M
MIN
TYP
MAX
UNITS
NOTES
422
528
531
664
mVrms
mVrms
7,8,9
7,8,9
441
551
555
693
mVrms
mVrms
7,8,9
7,8,9
mA
mA
mA
mA
4,13
5,13
3
3
7,13
13
6,7
n, V+ =
=
V+
V+
V+
V+
Sink
= 10.0V
= 3.0V
= 10.0V
= 3.0V
ISO
ISO
ISS
Supply Current (Outputs unloaded)
Operating
V+ = 3.5 V
Operating
V+ = 10.0V
Standby
V+ = 10.0V
PEHB
Pre-Emphasis, High Band
DIS
Output Distortion, total out
of band power'
Relative to rms sum of
row and column
fundamental power
0.50
0.20
-0.50
-0.20
1.0
1.0
5.0
0.5
2.0
10:0
200
mA
mA
pA
2.0
3.0
dB
-20
dB
10
11
tRISE
Rise Time, Tone Output
,5
ms
VNKD
Tone Output (no key activated)
-80
dBm
NOTES
9. See test circuit, Figure 10.
1. All voltages referenced to V-.
2. Voltage at which MUTE will respond to key input, TONE DISABLE
3. VOUT(MUTE) =0.5 v
4. V OUT (MUTE) = 9.5 v
5. V OUT (MUTE) = 2.5 V
6. Current into Pin 6 with no key input.
7. AtT A = 25"C.
8. True rms rea-ding.
10. Any row plus any column, V+ 2::: 5.0 V.
11. Time from a valid keystroke with no boun"ce to allow the waveform to go from min.
to 90% of the final magnitude of either frequency.- Crystal parameters defined as
RS = lOOn, L = 96 mH, CM =0.02 pF, and CH = 5 pF. Any V+ between 3.8 and
10.0 V. F = 3.579545 MHz.
V-.
12. See Graphs 1Aand lB.
13. With valid keyboard'input.
TEST CIRCUIT
Figure 10
1
2
3
A
4
5
6
B
.
8
9
C
0
#
0
7
l
3.579545
MHz
rd=i
-r-
14
13
12
11
-R1
TONE 16
OUT
'R L*
R2
V OUT
R3
R4
9 C4
5 C3
4
C2
3 C1
MK5092
V-
6
I .
_-_ V+
7 OSC
IN
OSC
OUT
IV-26
_TVBIAS
V+
1
'See V OUT specifications
in AC Characteristics
table for component
values.
Graph 1 A & 1 B - INPUT CURRENT VS. INPUT VOLTAGE
~\:>'<-
800
INPUT
CURRENT
-p.A
v"<>~
600
~'<,.
~~
8
~"<>'V
INPUT
CURRENT
- itA
~~~
400
200
1-""'CAe 'NM C","N:I
PULL-UP RANGE
6
4
2
25'C
25'C
1 2 3 4 5 6 7 8 9 10
INPUT - VOLTS
Graph 1A
.25
.75
1.0
1.25
INPUT - VOLTS
.50
Graph 1 B
APPLICATION
Figure 11 shows the MK5092 used with a 2500-Type
Speech Network. The tone levels and distortion
measurements of this application meet U.S. Telephone
Specifications.
M K5092 TELEPHONE
Figure 11
OSC 7
IN
3 C1
4 C2
5 C3
I
MK5092
2
3
A
4
5
6
B
7
8
9
C
.
0
#
OSC 8
OUT
9 C4
1
14
13
12
R1
V-
R3
11 R'TONE
4 OUT
0
6
R2
16
V+
1~
MUTE
10
6
XMTR
180 n
50 K
U
3.3 K
2N2222
2N3906
1
'N"'t
300 K
.0047P.F
T
C
TELEPHONE
UN'
Sl
I HOOK
~
2500TYPE
SPEECH
NETWORK
RR
~ IswrrcH~Z"'''
I
1.5
(4x)
NOTE: Transient protection circuitry not shown.
IV-27
RCVR
R
GN
B
g579545 MHz
T
IV-2B
MOSTEI(.
TELECOMMUNICATIONS
Integrated Tone Dialer
MK5094'(N)
FEATURES
PIN CONNECTIONS
Figure 1
o Designed for use with hybrid network
o
Internal regulation of tone amplitudes
o
Tone frequencies within 0.65% for 12 standard
frequencies
2
COLUMN 1..-3
o
Internal loop compensation and pre-emphasis
o
Uses inexpensive 3.579545 MHz television color-burst
crystal for accurate tones
o
V+..- 1
-::T::::O':"N::::E"'D:-:I=SA-:-B~L:-::E"-
15~~TONE
INHIBIT
14~ROW1
COLUMN 2..... 4
13..-ROW2
COLUMN 3 ..... 5
1 2..- R6iiii3
v- ..... 6
osclN ..... 7
Tone-disable capability
16..... TONEOUT
oscouT..-8
11~R0iiii4
lO-MUTE
9
~COLUMN4
o Uses either calculator-type (Form AContact) or 2-of-8
dual-contact keyboard
o
Pin-selectable single-tone capability
o
MUTE output for electronic switching
o
Minimum external parts count
The MK5094 was designed for tone-dialer applications that
require the following characteristi.cs: wide range supply
operation with loop-compensated tone regulation, singlecontact keyboard capability, tone-disable capability, anda
mute output that pulls to V- until a keyboard entry is
detected and then pulls to V+.
DESCRIPTION
The MK5094 is a monolithic integrated circuit fabricated
using the complementary-symmetry MOS (CMOS) process.
A member of the Tone 11* family of integrated tone dialers,
the MK5094 uses an inexpensive crystal reference to
provide the eight standard signaling frequencies which are
mixed to provide Dual-Tone-Multi-Frequency (DTMF)
telephone dialing.
Any valid keyboard entry to the Tone 11* family of integrated
tone dialers causes the selection of the proper divisor to
obtain the required frequency from the internal 3.579545
MHz oscillator. Digital-to-analog conversion ofthe resultant
frequency is done internally with a conventional R-2R
ladder network. The tone output is a stairstep approximation
of a sinusoid and requires little filtering for low-distortion
applications.
*y rademark of Mostek Corp.
IV-29
BLOCK DIAGRAM
Figure 2
R1
14
R2
13
R~
12
v
R
_,.4
1Y
11
IRRL
V+
J+
RRI
IRRI
RRI
10
II STATIC PROTECTION I
I
KEYBOARD LOGIC
ose
OUT
ose
IN
I
8
7
~
I
+
ROW
COUNTER
-i-4
COLUMN
COUNTER
KEYBOARD LOGIC
I
SINE
WAVE
COUNTER
h
,.....
D/A
CONVERTER
r--
""'-~K
r -
1=
V
SINE
WAVE
COUNTER
t
I""-
D/A
t-CONVERTER
VKB
I STATIC PROTECTION I
f
IRCI
Rei
Rei
Rei
3
4
5
MUTE
VKB
9
V-
I
16
~
TONE
OUT
2
TONE
DISABLE
15 SINGLE TONE
INHIBIT
l
6,4
v-
FUNCTIONAL DESCRIPTION
Figure 4 shows how to connect to the two keyboard types
and Figure 5 shows waveforms for electronic input. The
inputs are static, i.e. there is no noise generation as occurs
with scanned or dynamic inputs.
(Refer to Figure 2 for Block Diagram)
V+, Pin 1
Pin 1 connects the positive supply to the MK5094.
TONE DISABLE, Pin 2
TONE· DISABLE disables the summing operational
amplifier and is used to inhibit tone generation to allow the
keyboard· to be used for functions other than DTMF
signaling. The TONE DISABLE input has an internal pull-up
resistor and, when left unconnected or connected to V+,
allows normal generation of tones. When connected to V-,
TONE DISABLE inhibits the tone output. MUTE and other
functions operate normally, regardless of the status of Pin 2.
ROW AND COLUMN INPUTS,
Pins 3,4,5,9,11,12,13,14
The MK5094 features inputs compatible with the standard
2-of-8 keyboard, the inexpensive single-contact (Form A)
keyboard, and electronic inputs.
The internal structure of the MK5094 inputs is shown in
Figures 2 and 3. RRI and Rei pull in opposite directions and
hold their associated input sensing circuit turned off. When
one or more row or column inputs are tied together,
however, the input sensing circuits sense the "% level" and
deliver a logic signal to the 'internal circuitry of the MK5094
and cause the proper tone or tones to be generated.
When operating with a keyboard, normal operation is for
dual-tone generation when any single button is pushed and
single-tone operation when more than one button in the
same row or column is pushed. Activation of diagonal
buttons will result in no tones being generated.
When the inputs to the MK5094 are electronically
activated, per Figure 5, an input to a single row and a single
column will result in that dual-tone digit being generated.
Input to multiple columns only will result in no tone being
generated.
IV-30
Activation of a single row is not sensed by the internal
circuitry of the MK5094. If a single row is desired, two
columns must be activated along with the desired row.
loop gain to provide oscillation using a crystaL The inverter
input is OSC IN and the output is OSC OUT. When using a
3.579545 MHz crystal, the MK5094 will produce the
frequencies in Table 1. Crystal frequency deviation, usually
less than ±O.02%, will be reflected in the tone output
frequency.
ROW AND COLUMN INPUT CIRCUITRY
Figure 3
V+
MUTE, Pin 10
The MUTE output is used for electronic control of receiver
and/or transmitter switching. The MUTE output is
connected to V- when no keyboard input is present and
switches to V+ upon recognition of a keyboard input. MUTE
switches regardless of the condition of SINGLE TONE
INHIBIT and TONE DISABLE inputs.
ROW
INPUT
COLUMN
INPUT
SINGLE TONE INHIBIT, Pin 15
The SINGLE TONE INHIBIT input is used to control the
generation of single tones. It has an internal pull-up resistor
to V+ and when not connected or connected to V+, either
single or dual tones may be produced as described in the
paragraphs on row and column inputs. With SINGLE TONE
INHIBIT connected to V-,any input situation that would
normally produce a single tone will produce no tone.
KEYBOARD CONFIGURATION
Figure 4
1...
...
COL ...
• ROiiV
CLASS A KEYBOARD
c:~
TONE OUT, Pin 16
•
COL
An internal operational amplifier mixes the row and column
tones and regulates the output level. The output of this
amplifier is connected to the base of a npn transistor. The
collector of this internal transistor is connected to V+ and
the emitter is brought out to TONE OUT.
• ROW
2-0F-8 ·KEYBOARD
ELECTRONIC INPUT
OUTPUT FREQUENCY DEVIATION
Figure 5
Table 1
V_+ - - - - V
-11<-__
V+
V-- - - - __
.
-
Standard
DTMF
(Hz)
COLUMNS
Tone Output
Frequency Using
3.579545 MHz Crystal
% Deviation
From Standard
.-----ROWS
L-J
697
701.3
+0.62
770
771.4
+0.19
Low
852
857.2
+0.61
Group
'4
941
935.1
-0.63
'1
Row '2
'3
V-, Pin 6
V- is the return for the MK5094 supply. All MK5094
voltages and signals are referenced to V-.
OSC IN, Pin 7; OSC OUT, Pin 8
The MK5094 contains an on-board inverterwith sufficient
IV-31
'5
1209
1215.9
+0.57
Col '6
17
1336
1331.7
-0.32
High
1477
1471.9
-0.35
Group
'8
1633
1645.0
+0.73
ROW 2 TONE OUTPUT
TYPICAL DUAL-TONE WAVEFORM
(ROW 1, COL. 1)
8
Figure 6
,
~l
V
0
U
T
TIME_44.7I's/div
COLUMN 4 TONE OUTPUT
Figure 7
1
0
SPECTRAL ANALYSIS OF WAVEFORM IN FIG. 8
(Vert-10 dB/div, Horizontal-1 kHz/div)
Figure 9
.-
U
T
-
TIME _ 1 9 !'5/div
OUTPUT WAVEFORM
The row and column output waveforms, shown in Figures 6
and 7, are digitally synthesized sinusoids produced by
internal dividers and digital-to-analog converters. Distortion
measurement, discussed in the next section, of these
unfiltered output waveforms shows a typical total harmonic
distortion of 7% or less. Spectral analysis of the dual-tone
waveforms shows that all harmonic and intermodulation
distortion components are typically at least -30 dB when
referenced to the strongest fundamental. Figures 8 and 9
show a dual-tone waveform and its spectral plot.
For the MK5094 dual-tone waveforms, THD is -20 dB
maximum.
DISTORTION MEASUREMENTS
A simpler measurement may be made directly from the
screen of a spectrum analyzer by relating any component to
one ofthe fundamentals. The MK5094 dual-tone spectrum
shows all individual harmonic and intermodulation
distortion components are typically at least -30 dB with
respect to the column tone.
A commonly used method of dual-tone distortion
measurement is the comparison of total power in the
unwanted components (i.e. intermodulation and harmonic
components) with the total power in the two fundamentals.
Graph 1A & 1 B INPUT CURRENT VS. INPUT VOLTAGE
8
INPUT
CURRENT
INPUT
CURRENT
-iJA
-iJA
6
I
TYPICAL INPUT CURRENT
PULL-UP RANGE
..
..
4
25'C
2
2
Graph 1A
3
4
5
6
7
INPUT - VOLTS
8
9
10
.25
Graph 1 B
IV-32
.50
.75 1.0 1.25 1.5
INPUT - VOLTS
ABSOLUTE MAXIMUM RATINGS*
See Note 1
Supply Voltage V+ ............................................................................. +10.5 Volts
Voltage on any Pin Relative to V+ .................................................................. +0.3 Volts
Voltage on any Pin Relative to V- ...........•...................................................... -0.3 Volts
Operating Temperature ................................................ '.' ...................... O°C to +60°C
Storage Temperature ........................................................................ -35°C to +85°C
Maximum Circuit Power Dissipation ....................................... 500 mW @ 25°C (See Derating Curve)
*Stresses above those listed under "Absolute Maximum Ratings" maycause permanent damage tathe device. This is a stress rating only and functional operation of
the device at these or any other condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
POWER DISSIPATION DERATING CURVE
60
TA
('C)
40
20
SAFE
OPERATING
RANGE
0
100
200
NOTE: Derate 9 mW/'C from 500 mW@ 25'C.
300
400
500
TOTAL DISSIPATION
(mW)
ELECTRICAL CHARACTERISTICS
DC CHARACTERISTICS
(O°C ::::: TA::::: 60°C)
See Note 1
SYM
PARAMETER
V+
Supply Voltage
Operating (Generating tones)
(Telephone loop supply)
Operating (Generating tones)
(Fixed voltage supply)
Standby (de switching only)
MIN
TYP
MAX
UNITS
NOTES
3.5
10.0
V
13
3.8
10.0
V
13
3.0
10.0
V
2,13
VIH
VIL
Tone Disable, Single Tone Inhibit
Input High (Logic 1)
Input Low (Logic 0)
70% ofV+
0.0
V+
30% ofV+
V
V
VIH
VIL
Columns (1-4)
Input High (on)
Input Low (off)
70% ofV+
0.0
V+
10% ofV+
V
V
VIH
VIL
Rows (1-4)
Input High (off)
Input Low (on)
90% ofV+
0.0
V+
30% ofV+
V
V
125
125
kO
kO
kO
kO
RRI
RCI
Pull-Up/Down Resistors
Row Inputs
Column Inputs
TONE DISABLE
SINGLE TONE INHIBIT
20
20
IV-33
15
15
60
60
7,12
7,12
7,13
7,13
AC CHARACTERISTICS
(DOC :S TA :S 60°C)
See Note 1
SYM
PARAMETER
MIN
VOUT
VOUT
Tone Output (RL = 320 fl, V+ =
3.8 V)
Row Tone
Column Tone
VOUT
VOUT
Tone Output (RL = 320 fl, V+ =
10.0V)
Row Tone
Column Tone
1M
MUTE current
Source
1M
V+
V+
V+
V+
Sink
= 10.0V
= 3.0V
= 10.0V
= 3.0V
ISO
ISO
ISS
Supply Current (Outputs unloaded)
V+ = 3.5 V
Operating
V+ = 10.0 V
Operating
Standby
V+ = 10.0 V
PEHB
Pre-Emphasis, High Band
DIS
Output Distortion, total out
of band power
Relative to rms sum of
row and column
Fundamental Power
tRISE
Rise Time, Tone Output
VNKD
Tone Output (no key activated)
TYP
MAX
UNITS
NOTES
360
452
453
569
mVrms
mVrms
7,8,9
7,8,9
387
486
487
612
mVrms
mVrms
7,8,9
7,8,9
mA
mA
mA
mA
4,13
5,13
3
3
13,7
13
6, 7
0.50
0.20
-0.50
-0.20
1.0
1.0
5.0
0.5
2.0
15
200
mA
mA
/J. A
2.0
3.0
dB
-20
dB
10
5
ms
11
-80
dBm
8. True rms reading.
NOTES
9. See test circuit, Figure 10.
1. All voltages referenced to V-.
2. Voltage at which MUTE will respond to key input. TONE DISABLE
3. VOUT (MUTE) = 0.5 V
4. VOUT (MUTE) = 9.5 V
5. VOUT (MUTE) = 2.5 V
10. Any row plus any column, V+ 2: 5.0 V.
11. Time from a valid keystroke with no bounce to allow the waveform to go from min.
to 90% of the final magnitude of either frequency. Crystal parameters defined as
RS = 100 fi. L =96 mHo CM =0.02 pF, and CH =5 pF, Any V+ between 3.8 and
10.0 V. F = 3.579545 MHz.
12. See Graphs 1A and 1 B.
13. With valid keyboard input.
= V-.
6. Current out of Pin 6 with no key input.
7. AtTA = 25°C.
TEST CIRCUIT
Figure 10
1
2
3
A
4
5
6
B
7
8
9
C
0
#
D
.
14
13
12
R,
TONE
OUT
-
R2
16
~
11 R4
9 C
4
MK5094
5
6
C3
V4
C2
3 C
1
7 OSC
I
PI
-,3.579545 MHz
RL
320n
V OUT
fV+
IN
'See V OUT specifications
8 0SC
OUT
IV-34
V+
1
in AC Chara cteristics
table for V+ values.
APPLICATION
Figure 11 shows the MK5094 used with a 2500-Type
Speech Network.
MK5094 TELEPHONE
Figure 11
3
4
5
I
9
14
1
2
3
A
4
5
6
B
C1
OSC
IN
7
~
C2
OSC B
OUT
C3
C4
13.579545 MHz
MK5094
R,
13
7
.
R2
12
8
9
C
0
#
V
R3
11
0
~
TONE
OUT V+
MUTE
161
10
1
6
120
Q
50 K
XMTR
3.3 K
2N2222
4:906
~ 300 K
,""on
11
RCVR
fOM7"
C
2500TYPE
SPEECH
NE1WORI{
/:,
TELEPHONE
LINE
Is:~
K
HI
C I
C
R
GN
B
RR
~
1N4004
(4x)
NOTE: Transient protection circuitry not shown.
IV-35
n
IV-36
MOSTEI{.
TELECOMMUNICATIONS
Integrated Tone Dialer
MK5380(N/P/J)
FEATURES
PIN CONNECTIONS
Figure 1
o Low standby power
16_TONEOUT
o Minimum external parts count'
CHIP
DISABLE- 2
o Uses inexpensive 3.579545 MHz television color-burst
crystal to provide high-accuracy tones
COL1- 3
Co"i:2_
o Improved loop compensation
4
15 _
14 _
SINGLE TONE
INHIBIT
Roi.iii1
13_ROW2
COL3_5
12_ROW3
V-_6
11_R0vii4
o Distortion lower than industry standards
OSCIN_7
10_MUTEOUT
o Low voltage operation - 2.5 volts
OSCOUT_a
9_COL4
o Uses low-cost calculator-type keyboard (Form A contact)
or standard 2-of-8 keyboard
o Auxiliary switching functions on chip
o Multiple key entry pin-selectable to either single tone or
no tone
D-to-A conversion for synthesis of the tones is accomplishedon chip by a sinusoidally tapped resistor tree.
DESCRIPTION
Pin connections are shown in Figure'1 and a block diagram
is shown in Figure 2.
The MK5380 is a monolithic integrated circuit fabricated
using Mostek's Silicon Gate CMOS process. A member of
the Tone 111* family of integrated tone dialers, the MK5380
uses an inexpensive crystal reference to provide eight
different audio sinusoidal frequencies, which are mixed to
provide tones suitable for Dual-Tone-Multi-Frequency
(DTMF) telephone dialing.
The MK5380was designed specifically for integrated tonedialer applications that require the following: wide-supply.
operation with regulated output, scanned keyboard inputs,
auxiliary switching functions, and a Chip Disable input.
Keyboard entries to the MK5380 integrated tone dialer
cause the selection of the proper divide ratio to obtain the
required two audio frequencies from the 3.579545 MHz
reference oscillator.
FUNCTIONAL DESCRIPTION
V+, Pin 1
Pin 1 is the positive supply pin. The voltage on Pin 1 should
be between 2.5 and 10.0 volts, measured relative to V- (Pin 6).
CHIP DISABLE, Pin 2
When the Chip Disable input is connected to the V- supply,
tone generation will be inhibited, the keyboard inputs will go
to a high impedance state, and the amplifiers and oscillator
will be powered down. The Chip Disable input has a pull-up
resistor to the V+ supply and when floating or tied to V+, the
MK5380 will operate normally.
'Trademark of Mostek Corporation
IV-37
MK5380 BLOCK DIAGRAM
Figure 2
14
13
12
"1
KEYBOARD SCAN
CIRCUITRY
TONE
OUT
TO~~~~BIT·~1~5t--------+----~--t-~
KEYBOARD SCAN
CIRCUITRY
OD
CD
~
~
Oscillator Disable
Chip Disable
v-
DESCRIPTION (Continued)
KEYBOARD CONFIGURATION
Figure 3
ROW-COL INPUTS,
Pins 3, 4, 5, 9, 11, 12, 13, 14
1
1------.4
COL, .....
.~------------~.~ROW
CLASS A KEYBOARD
L1:___
. ~::
2-0F-8 KEYBOARD
ELECTRONIC INPUT
Figure 4
f----.~I
ro
.l
.
vjj1~01
The MK5380 features inputs compatible with the standard
2-of-8 keyboard, the inexpensive single-contact (Form A)
keyboard, and electronic input. Figure 3 shows how to
connect to the two keyboard types and Figure 4 shows
waveforms for electronic input.
The internal structure of the MK5380 Rowand Column
inputs is shown in Figure 5, These inputs are c;lesigned to
sense a connection between How and Column, or an
electronic input as shown in Figure 4. Table 1 is a functionnl
tru~h table for these inputs. Note that at least one Rowand
one Column'must be active to generate a valid output.
td
VZ1fZ
COLUMNS
When operating with a keyboard, normal operation is for
dual-tone generation when any single button is pushed,
and single-tone operation when more than one button in
the same row or column is pushed. Activation of two or
more diagonal buttons will result in no tones being
generated.
V-, Pin 6
NOTE: td is minimum tone duration minus
oscillator start up time (t RISE )
Pin 6 is the power supply return pin and it is the
measurement reference for V+(Pin 1).
IV-38
FUNCTIONAL TRUTH TABLE
Table 1
ROW AND COLUMN INPUTS
Figure 5
ACTIVE LOW INPUTS
ROW
COLUMN
OUTPUT
One
One
Dual Tone
Two or More
One
Column Tone
One
Two or More
Row Tone
Two or More
Two or More
No Tone
~--.Q
~~---~--~-----.Q
STROBE (ROW}
OR
S'i"R"5"BE(COl)
:
NOTE: STI is floating or tied to V+.
CD is floating or tied to V+.
·STATIC PROTECTION CIRCUITRY
NOTE: Chip Disable is floating or tied to V+.
When Co is tied to V-, Rowand
OSC IN, Pin 7; OSC OUT, Pin 8
Column inputs go to a high impedance state.
The MK5380 contains an on-board inverter with sufficient
loop gain to provide oscillation when working with a lowcost television color-burst crystal. The inverter's input is Osc
In (Pin 7) and output is Osc Out (Pin 8). The circuit is
designed to work with a crystal cut to 3.579545 MHzto give
the frequencies in Table 2. The oscillator is disabled
whenever a keyboard input is not sensed.
SINGLE TONE INHIBIT, Pin 15
Any crystal frequency deviation from 3.579545 MHz will be
reflected in the tone output frequency. Most crystals do not
vary more than ± .02%.
OUTPUT FREQUENCY DEVIATION
Table 2
Standard
DTMF
(Hz)
The Tone output pin is connected internally in the MK5380
to the emitter of an npn transistor whose collector is tied to
V+. The base of this transistor is the output of the on-chip
operational amplifier which mixes the row and column
tones together.
%
Deviation
From
Standard
13
14
697
770
852
941
699.1
766.2
847.4
948.0
+0.31
-0.49
-0.54
+0.74
Low
Group
15
16
17
Is
1209
1336
1477
1633
1215.9
1331.7
1471.9
1645.0
+0.57
-0.32
-0.35
+0.73
High
Group
I,
3.579545
When forced to the V- supply, anytime two or more rows (or
columns) are activated, no tone will result.
TONE OUT, Pin 16
MHz Crystal
ROW 12
COL
Tone Output
Frequency
Using
The Single Tone Inhibit input is used to inhibit the
generation of other than dual tones. It has a pull-up to the
V+ supply and, when floating or tied to V+, single or dual
tones may be generated as described in the paragraph
under Row-Column inputs.
The level of a dual tone output is the sum of the levels of a
single row and a single column output. This level is
controlled by an on-chip reference which is not sensitive to
variations in the supply voltage.
A typical single tone sine wave output is shown in Figure 6.
This waveform is synthesized using a resistor tree with
sinusoidally weighted taps.
MUTE OUT, Pin 10
The Mute output is a conventional CMOS inverter that pulls
to V- with no keyboard input and pulls to the V+ supply
when a keyboard entry is sensed. This output is used to
control auxiliary switching functions that are required to
actuate upon keyboard input. The Mute output switches
regardless ofthe state ofthe Single Tone Inhibit input. Mute
output is not affected by keyboard inputs when CD is tied to
V-.
IV-39
A simple measurement of distortion may be made directly
from the screen of a spectrum analyzer by comparing any
component to one of the fundamentals.
SPECTRAL ANALYSIS OF WAVEFOHM IN FIG. 7
(Vert-10 dB/div. Horizontal - 600 Hz/div.)
FigureS
TYPICAL SINE WAVE OUTPUT - SINGLE TONE
TONE LEVEL TEST CIRCUIT
Figure 9
Vs = 2.5 - 10 V
Figures 7 and 8 show a typical dual-tone waveform and its
spectral analysis.
--'-'~,'Tw·
"
2
7
TYPICAL DUAL-TONE WAVEFORM (Row 1, Col 1)
Figure
7.
3.579545
MHz
CRYSTAL
D
16
OSC
OUT
TONE
OUT
TONE oUT
RE =100n
3
COl1
4
COl2
14
-ROW1
V-
NOTE: The above circuit connections are for a Row 1
single tone test. For a Col1 single-tone
test. connect Row 1 (Pin 14) and Row 2
(Pin 13) to Col 1 (Pin 3).
IV-40
ABSOLUTE MAXIMUM RATINGS*
DC Supply Voltage V+ ............................................................................ 10:5 volts
Any Input Relative to V+ ......................................................................... +0.30 volts
Any Input Relative to V- .......................................................................... -0.30 volts
Operating Temperature ...................................................................... -30°C to +60°C
Storage Temperature ....................................................................... -55°C to + 125°C
Maximum Circuit Power Dissipation ................................... 500mW @ 25°C (see derating curve below)
*Stresses above those listed under "Absolute Maximum Ratings" maycause permanent damage tathe device. This is a stress rating only and functional operation of the device at
these or any other condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
POWER DISSIPATION DERATING CURVE
60-r----------~
TA 40
(OC)
20
O-r-----r----~----~----~----~---100
o
200
300
400
500
mW
DERATE AT 9 mW/oC
WHEN SOLDERED INTO
PC BOARD.
ELECTRICAL CHARACTERISTICS
DC CHARACTERISTICS
(-30°C:::; TA :::; 60°C)
SYM
PARAMETER
V+
DC Operating Voltage
V il
MAX
UNITS
NOTES
2.5
10.0
V
1
Input Voltage Low - "0"
V-
30% ofV+
V
1
VIH
Input Voltage High - "1 "
70% ofV+
V+
V
1
RIP
Input Pull-Up Resistance, STI. CD
20
100
kO
ISSB
Supply Current - Standby and CD
tied to V-
10
10
150
250
pA
3,4,6
3,4,7
Iso
Supply Current - Operating
(CD floating or tied to V+)
1.0
5.0
2.0
10
mA
3,5,6
3,5,7
RKPU
Keyboard Pull-Up Resistance
CD tied to V+
CD tied to V-
100
10
kO
MO
8
Keyboard Pull-Down Resistance
CD tied to V+
CD tied to V-
4.0
10
kO
MO
8
RKPD
MIN
TYP
10lM
Output Drive, MUTE - No Entry
0.5
1.0
2.0
4.0
mA
9
10
10HM
Output Drive, MUTE - Valid Entry
0.5
1.0
2.0
4.0
mA
11
12
IV-41
AC CHARACTERISTICS
(-30 D C :s: TA:S: 60 D C; 2.5 V :s: V+
SYM
PARAMETER
t R1SE
:s: 10.0 V)
MAX
UNITS
NOTES
Tone Output Rise Time
5.0
ms
13,14
TONE NKD
Tone Output-No Key Down or CD
tied to V-
-80
dBm (600n)
2
TONE OUT
Tone Output Voltage
(Key Down and CD floating or tied
to V+)
155
mVrms
15,16,17,18
PE HB
Pre-Emphasis, High Band
2.0
dB
16
DIS
Output Distortion
5.0
10.0
%
16
f KBS
Keyboard Scan Frequency
948
Hz
8
MIN
TYP
699
NOTES
14. Crystal parameters: RS <: 100
3.579545 MHz. CL = 18 pF.
1. All voltages referenced to V- (Pin 6)
2.2.5 V <: V+ <: 10.0 V.
n. LM = 96 mHo CM = 0.02 pF. Ch =5 pF. f =
15. Single-lone, low-group TA ::: 25°C.
16.2.5 V <: V+ <: 10.0 V, RE = lOOn (See Figure 9).
17. TONEOUT measured at Pin 16 (See Figure 9).
18. The tone level, when used in a subscriber set, is a function of the output
resistor RE and the telephone ae resistance (RU. The low-group single-tone
output amplitude is a function of RE and RL by the relationship:
3. All outputs unloaded.
4. Current out of Pin 6, no key depressed.
5. Current out of Pin 6, one key depressed.
6. V+ = 2.5 V
7. V+ = 10.0 V.
8. When Row or Column inputs are sensed, the keyboard inputs are alternately
strobed. When a Row is strobed, the Row pull-down and Column pull-up
resistances are enabled. This strobing alternates in the frequency range of 699 to
948 Hz depending on which row is selected When no inputs exist, either a Rowor
a Column input will be statically sensed.
9. V+ c 2.5 V. VOLM = 0.5 V.
10. V+ = 10.0 V, VOLM 0.5 V.
11. V+ = 2.5 V. VOHM ~ 2.0 V.
12. V+ '0 10.0 V. VOHM 0 9.5 V.
, 3. Time from a valid keystroke with no bounce to allow wave to gofrom minimum to
C
90% of final magnitude of either frequency.
IV-42
1
---R-E-
0.2"
RL
where Vo is the tone output amplitude at the phone line, and RL is the equivalent
ac impedance in shunt with the tone generator (RL typically varies with loop
current), RE is the resistor value from TONEOUTto V-.ln a 2500-Type application
RL will typically vary from 200 to 500 11. Thus, atthe phone line tone output levels
will range from 200 to 400 mV rms , depending on loop current.
TYPICAL APPLICATION
Figure 10 shows an application of the MK5380 in a
standard telephone set that uses the standard 2500-Type
Network.
TYPICAL APPLICATION IN 2500-TYPE TELEPHONE
Figure 10
t
PHONE
LINE
HOOK
SWITCH
•
~-----:l
[i]
18]
I
: [2]
ill IT! A 1-1- - - - - . : .1..,4 ROW 1 V+
IT! ~ B
13 ROW2
~
m
1-:__---:.1,,2 ROW 3
TONE 16
OUT
f-_ _ _....;1..,1 ROW 4
9 __
MK5380
L-----'1COL4
L--------~5COL3
L----------4~COL2
~----------------3,COL1
3.579545c::::J
MHz
100 l!
13V
1 N4743
MUTE~1~0~1---_+-______
70SC
IN
OUT
r--'
V6
.005"F
,-
2500 - TYPE NETWORK
GN
1
1
I
1
~----~----~ 1~>----'---'~r--~~-r~T~~RR'~--~
_ _ ---1
300 K
XMTR
3.3 K
300 K
10 K
NOTE: Transient protection circuitry not shown.
IV-43
IV-44
MOSTEI(®
TELECOMMUNICATION PRODUCTS
Integrated Tone Dialer With Redial
MK5382(N/PI J)
FEATURES
o
Low standby power
o
Uses inexpensive 3.579545 MHz television color-burst
crystal to provide high-accuracy tones
PIN CONNECTIONS
Figure 1
~-1
CHIP
DISABLE-2
1 8 - TONE OUT
ON-HOOK
1 7 - SENSE
1 6 _ ROW1
o
Distortion lower than industry standards
COL1_3
COL2_4
1 5 - ROW2
o
Low voltage operation - 2.5 volts
COL3-5
o
Uses low-cost calculator-type keyboard (Form A contact)
or standard 2-of-8 keyboard
1 4 - ROW3
1 3 _ ROW4
v--6
osclN-7
oscouT-8
o
16-digit last number redial
o
Up to 2 PBX access digits may be dialed before using last
number redial function
o
Off-hook store into memory without dialing
DOn-chip power-up-clear and memory-loss-detect
circuitry
o
Low memory retention current
o
12/16 keyboard or external control key redial access
DESCRIPTION
The MK5382 is a monolithic integrated circuit fabricated
using the complementary - symmetry MOS (CMOS)
process. A member ofthe Tone 111* family of integrated tone
dialers, the MK5382 uses an inexpensive crystal reference
to provide eight different audio sinusoidal frequencies,
which are mixed to provide tones suitable for Dual-ToneMulti-Frequency (DTMF) telephone dialing.
CONTROL-9
1 2 _ ANY KEY DOWN
1 1 - COL4
10_ vM-
The MK5382 was designed specifically for integrated tonedialer applications that require the following: wide-supply
operation with regulated output, scanned keyboard inputs
which recognize either negative-true or Class A closures, a
Chip Disable input, and an Any Key Down output that is
high impedance with no keyboard entry and pulls to the V+
supply when a keyboard button is pushed.
The MK5382 will redial 3 to 16 digits. The redial function
may be employed immediately after going off-hook, after
dialing one PBX access digit, or after dialing two PBX access
digits. An "off-hook store" function allows a number to be
entered into the last number dial memory for later use with
no tones emitted during entry.
On-chip power-up-clear circuitry and memory-Iossdetection circuitry insure that no false numbers, due to
power loss, can be redialed.
*Trademark of Mostek Corporation
IV-45
IV-46
MOSTEI(®
TELECOMMUNICATION PRODUCTS
Integrated Dialer ComparisonTone II vs Tone III
The purpose of this Application Brief is to define the major
differences between Mostek's Tone 11* and Tone IW series
of integrated tone dialers.
DC OPERATING VOLTAGE
D MK5087 - 3.5 to 10.0 V
D MK5089 - 3.0 to 10.0 V
The Tone III series was developed as an improvement over
Tone II. The minimum operating dc voltage of Tone III has
been reduced and loop compensation of the tones
generated has been improved. Distortion has also been
reduced due to a scheme in which DTMF tones are
synthesized using a sinusoidally tapped resistor tree.
D MK5380 - 2.5 to 10.0 V
TONE OUTPUT
D
The Tone III family of integrated tone dialers is fabricated
using Mostek's Silicon Gate CMOS process. Tone III devices
use a scanned keyboard scheme with which various
keyboard types or electronic input may be used. Tone III
dialers also have a Chip Disable feature which causes tone
generation to be inhibited, the keyboard inputs to go to a
high-impedance state, and the amplifiers and oscillator to
be powered down.
The following is a comparison of the major differences
between the MK5087 and MK5089 (Tone II), and the
MK5380 (Tone III).
KEYBOARD TYPE
D MK5087 - Class A; 2-of-7 or 2-of-8 (K/B common
floating)
D MK5089 - 2-of-7 or 2-of-8 (K/B common tied to V-)
D MK5380 - Class A; 2-of-7 or 2-of-8 (K/B common
floating or tied to V-)
AUXILIARY FUNCTIONS
D Pin 2
•
•
o
MK5087 - Bipolar XMTR SW (no key = 1; key input =
open)
MK5089 - Tone Disable
MK5380 - Chip Disable
MK5089 - Low Group: .0855 V DD ± 1 dB V rms into
10 kDload
High Group: 2.7 dB above low group
Thefollowing are designed to deliver U.S. telephone system
tone levels in a telephone. On a fixed supply the levels will
be:
D MK5087 - Low Group: 317-504 mV rms into 1 kDload
High Group: 2.0 dB above low group
D MK5380 - Low Group: 245 mVrms typically (see notes 1
and 2)
High Group: 2.0 dB above low group
TYPICAL APPLICATIONS
D MK5087 (Uses fixed supply or modulating supply in
telephone)
o Telephone tone-dialer applications
D MK5089 (Uses fixed or regulated supply in telephone)
o Electronic or f.1P-dialing applications
o European telephone applications
D MK5380 (Uses fixed supply or modulating supply in
telephone)
• Telephone tone-dialer applications
o Electronic or f.1P-dialing applications
NOTES:
1
TONEOUT (measured at Pin 16 in loop applications) ;::; 155 mVrms (typical).
RE 100 1t
In loop applications, the low-group single-tone output amplitude is a
function of RE and RL by the relationship:
Va
1
=
2.
D Pin 10
• MK5087/5380 - CMOS MUTE SW (no key = 0;
key input = 1)
• MK5089-N-Chnl MUTE SW (AKD) (no key = open;
key input = 0)
TONEOUT
=
0.2 +
~
RL
where Va is the tone output amplitude at the phone line and RL is the
equivalent ae impedance in shunt with the tone generator (RL typically
varies with loop current), RE is the resistor value from TONEOUT to V-.ln a
2500-Type application RL will typically vary from 200 to 500 n. Thus; at the
phone line, tone output levels will range from 200to400 mV rms , depending
on loop current.
'Trademark of Mostek Corporation
IV-47
IV-48
MOSTEI(.
TELECOMMUNICATIONS
Loop Simulator
The following is a simple circuit which can be used to
simulate a telephone loop for most testing purposes.
Potentiometer R2 may be varied to provide various loop
currents simulating different loop lengths. Normal loop
currents range between 20 and 80 mA. Resistor R1 is used
to limitthe loop currentto a maximum of approximately 120
mA{Tip and Ring short-circuited). An ammeter, Lis used to
measure the loop current and capacitor Cl and resistor
R3 are used to simulate the 600 0 impedance of the
telephone line. Inductor L provides a high impedance in
series with the power supply so that the impedance across
Tip and Ring is effectively 600 n.
)---....----------<) TIP
+
v
~-----------------------~---------~ORING
v
48 V (power supply or battery)
Rl
250
R2
2 kO (2 Watts)
R3
600 0 ±1 % (% Watt)
n (5 Watts)
Ammeter (100 mA full scale)
Cl
L
500 ILF, -10%, +50%, (50 V)
2: 10 H up to 150 mA dc
(RL 150 0)
=
IV-49
IV-50
1982 TELECOMMUNICATION PRODUCTS DATA BOOK
Integrated Pulse
Dialers With
Redial
INTEGRATED PULSE DIALER WITH REDIAL
MK50981(N)
FEATURES
PIN CONNECTIONS
o Direct telephone-line operation
o CMOS technology is used for low-voltage, low-power
operation
_
V+
o Uses either a standard 2-of-7 matrix keyboard with pos.
true common or the inexpensive Form A-type keyboard
o Ceramic resonator used as frequency reference for
guaranteed accuracy
o Make/Break ratio pin-selectable
PULSE OUTPUT
2
ON-HOOK/TEST
COl1
3
ROW1
COl2
4
ROW2
COl3
5
ROW3
V-
6
ROW4
OSCIN
7
o Redial with either a * or # input
o Provision for rapid testing
8
-
MUTE OUTPUT
MAKE/BREAK
SELECT
o On-chip voltage regulator
o Power-Up-Clear circuitry
DESCRIPTION
never be more than 17 digits remaining to be. outpulsed.
The MK50981 is a monolithic CMOS integrated circuit which
converts keyboard inputs into pulse signal outputs simulating
a rotary telephone dial. It is designed to operate directly from
the telephone line and can be interfaced properly to meet
telephone specifications in systems utilizing loop-disconnect
signalling. Two outputs, one to pulse the telephone line and
one to mute the receiver, are provided to implement the pulse
dialer function. Accurate timing is accomplished by using a
ceramic resonator as the frequency reference forthe on-chip
oscillator.
The MK50981 also features the rediai function. Any 17-digit
number sequence may be redialed with a * or # key input,
providing that the circuit enters the on-hook mode for a finite
time, tOH (refer to discussion on the On-HooklTest Pin).
An on-chip "Power-Up-Clear" circuit insures reliable
operation of the MK50981. If the supply to the circuit should
become insufficient to retain data in the memory (see
electrical specifications), a "Power-Up-Clea(' will occur upon
regaining a proper supply level. This function will prevent the
"Redial" or spontaneous outpulsing of incorrect data. A new
number sequence may then be entered in normal fashion.
The MK50981 is in either the on-hook or off-hook mode as
determined by the input to the pin designated "OnHooklTest."In order to accept any key inputs, the MK50981
must be in the off-hook state. Upon sensing a key input, the
normally static oscillator is enabled and the row and column
inputs are alternately strobed to verify thatthe keyboard input
is valid. The decoded input is then entered into an on-chip
memory. The memory will store up to 17 digits and allows
keystrokes to be entered at rates comparable to tone dialing
telephones. Entering the first digit (except * or #) clears the
memory buffer and starts the outpulsing sequence. As
additional digits are entered, they are stored in the memory
and outpulsed in turn. The memory has a FIFO-{first-in~firSt
out) type architecture and more than 17 digits may be dialed
in any number sequence. The limitation is that there can
Functions of the individual pins are described below.
V+, Pin 1
This is the positive supply inputto the part and is measured
relative to V- (Pin 6). The voltage on this pin must be
regulated to less than 6 volts using either the on-chip
reference circuitry or an external form of regulation.
The V REF output provides a negative reference voltage
relative to the V+ supply. Its magnitude is a function of the
V-1
ABSOLUTE MAXIMUM RATINGS*
DC Supply Voltage, V+ .............................................................••••............ 6.2 Volts
Operating Temperature ....................................................................... -30°C to +60°C
Storage Temperature .••.....•••.•......•.••....•.......•.••...•...••....•.•••.•..••.••....•• -55°C to +85°C
Maximum Power Dissipation 25°C ......................•........................................•..... 500mW
Maximum Voltage on any Pin .............•........................................... (V+) + 0.3; (V-) -0.3 Volts
·Stresses above these listed under" Absolute Maximum Ratings" maycause permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
-30°C :5 TA :5 60°C
DC CHARACTERISTICS
SYM
PARAMETER
V+
DC Operating Voltage
IMR
Memory Retention Current
lop
DC Operating Current
VREF
Magnitude of (V+ - V REF)
ISUPPLY = 150pA-
1M
Ip
ILKG
TYP
MAX
UNITS
6.0
V
0.7
2.5
pA-
1
100
150
pA-
2
1.5
2.5
3.5
V
Mute Sink Current: V+ = 2.5V,
Vo =0.5V
0.5
2.0
rnA
Pulse Sink Current: V+ = 2.5V,
Vo = 0.5V
1.0
4.0
rnA
MIN
2.5
Mute and Pulse Leakage: V+ =
6.0V, Vo = 6.0V
0.001
1.0
pA-
RKI
Keyboard Contact Resistance
1.0
k!1
CK1
Keyboard Capacitance
30
pF
KIL
"0" Logic Level
V-
20%ofV+
V
KIH
'" " Logic Level
80% ofV+
V+
V
KRU
Keyboard Pull-Up Resistance
KRD
ROH
NOTES
4.0
k!1
3
Keyboard Pull-Down Resistance
100
k!1
3
On-Hook Pull-Up Resistance
100
k!1
'.
NOTES
Typical values BrB to be used as a design aid and are not subject to production
testing.
2. Current required for proper circuit function. Off-Hook Mode. Valid key input,
1. Current necessary for memory to be maintained. All outputs unloaded.
3. Keyboard to be scanned at 500Hz when oscillator enabled. Rowand Column
On-Hook mode.
VREF tied to V-.
to alternately pull high and low.
V-2
.
AC CHARACTERISTICS
(The Timing Relationships are shown in Figure 3)
SYM
PARAMETER
fosc
Oscillator Frequency
(antiresonant mode)
MIN
TYP
MAX
UNITS
NOTES
480
kHz
1
10
ms
tOB
Keyboard Debounce Time
tKD
Time for Valid Key Entry
tos
Oscillator Start-Up Time
6.0
ms
PR
Pulse Rate
10.0
pps
tB
Break Time: Pin 9 tied to V+/
tied to V-.
61.0/67.0
ms
800
ms
t lOP
ms
40
Interdigital Pause
NOTES
"Typical" values are exact values with a nominal 480 kHz frequency reference
(except for oscillator start-up time),
1. Ceramic resonator should have the following equivalent values: R<20 fl. RA •
:2: 70 kil. Co:5 500 pF.
internal parameters which define the minimum operating
v.oltage of each part .. In a typical application, as shown in
Figure4, the V REF pin is simply tied to V-(Pin 6). The internal
circuit with its associated I-V characteristic is shown in
Figure 1.
TYPICAL I-V CHARACTERISTICS
Figure 1
7.0
KEYBOARD INPUTS. Pins 3. 4. 5.11.12.13.14
6.0
The MK50981 incorporates an innovative keyboard
scheme that allows either the standard 2-of-7 keyboard
with positive common or the inexpensive single-contact
(Form A) keyboard to be used. as shown in Figure 2.
5.0
IREF
rnA
4.0
3.0
A valid key entry is defined by either a single row being
connected to a single column or V+ being simultaneously
presented to both a single row and column.
2.0
When in th~ On-Hook mode, the row and column inputs are
held high and no keyboard inputs are accepted. When Off
Hook, the keyboard is completely static until the initial valid
key input is sensed. The oscillator is then enabled and the
row and columns are alternately scanned (pulled high, then
low) to verify the input is valid. The input must remain valid
continuously for 1Oms of debounce time to be accepted.
1.0
2
v+ -
V REF
3
4
5
VOLTS
Suggested equivalent values for the resonator are given in
the timing specification section. These values will insure
proper. oscillator operatiqn in the specified voltage range.
The MK50981 may be driven externally with a 480kHz
signal on Pin 7.
V-. Pin 6
This pfn is the negative supply pin input.
OSCILLATOR IN. OUT. Pin 7. 8
MAKE/BREAK SELECT. Pin 9
TheMK50981 contains an on-chip inverter with sufficient
gain to provide oscillation when working with a low-cost
480kHz ceramic resonator (anti-resonant mode). In addition
to the resonator, two external capacitors are required.
The Make/Break ratio may be selected by connElcting the
pin to either the V+ or V- supply.:rable 1 indicates the two
popular ratios from which the user. can choose.
V-3
KEYBOARD CONFIGURATION
Figure 2
SINGLE-CONTACT APPLICATION
method by which the circuitry is reset. When theoutpulsing
in this mode, which can take up to 300ms, is completed, the
circuit is deactivated and will require only the current
necessary to sustain the memory and Power-Up-Clear
detect circuitry (refer to the electrical specifications).
~
COL ___
.----~
"----_ROW
FORM A KEVBOARO
c±~:
Upon returning Off-Hook, ifthe first key entry is either * or #,
the number sequence stored on-chip will be outpulsed. Any
other valid key entries will clear the memory and outpulse
the new number sequence.
COL
2-0F-7 KEV""BO-A-:-:RC:
D- - - ROW
PULSE OUTPUT, Pin 16
VOL TAGE - FED APPLICATION
V+-
~±~:
~
The Pulse output is an open-drain N-channel transistor.
This output provides the logic necessary to pulse the
telephone line with the correct Make/Break, pulse rate, and
interdigitalpause timings. The timing characteristics of the
Pulse output are shown in Figure 3.
COL
A-------RDW
ELECTRONIC INPUT
TYPICAL APPLICATION
1---1 tKD
Vt-V-
----on
.
The. !,chematic diagram in Figure 4 shows one method
which can be used to interface the pulse dialer with the
telephone line. In the approach shown, the pulse dialer
circuitry is in parallel with the speech network.
L.----COLUMNS
::- - - - - --nL____
ROWS
A current source of some type is desired to present a high
impedance to the telephone line while guaranteeing
sufficient current to power the MK50981 (;::: 150~); The
current is sourced by the co'llector of transistor 02. Its
magnitude is determined by the voltage drop across R1,
caused the forward-biased diodes, 01 and 02. Transistor
01 prQvides the quie!'c.ent current for the diodes and base
drive for 0 2 . ' ,
MAKE/BREAK RATIO SELECTION
Table 1
Input To Make/Break Pin
V+ (Pin 1)
V-(Pin 6)
Pulse Output
Make
Break
61%
39%
67%
33%
by
MUTE OUTPUT, Pin 10
WhElri'in the On-Hook mode, S1 and S2 are open. This
disables the current source and eliminates any excess
current flow through the base-emitter junction of 01 by
allowing the emitter to be pulled to V+ through On-Hook. A
large-value resistor, R3, allows a small amount of current to
maintain the memory on the MK50981.
The Mute Output consists of an open-drain N-channel
transistor. It provides the logic necessary to mute the
receiver while the telephone line is being pulsed. A typical
way to interface this output is shown in the application
diagram in Figure 4. Figure 3 shows the timing
characteristics of the Mute Output.
ON-HOOK/TEST, Pin 15
The "Test" or "On-Hook" input of the MK50981 has a
1OOkn pull-up to the positive supply. A V+ input or allowing
the pin to float sets the circuit in its On-Hook or test mode,
while a V- il)putsets it in the Off-Hook or Normal Mode.
When Off-Hook, the MK50981 will accept key inputs and
outpulse the digits in normal fashion. Upon completion of
the last digit, the oscillator is disabled and the circuit stands
by for additional il)puts.
To return Off-Hook S1 and S2 are closed, thus tying the
On-Hook pin' to V-. The pulse and mute outputs drive
external transistors to perform the outpulsing function. The
speech network is connected through transistor 05 to the
telephone line. Mute holds this transistor on until
outpulsing begins. The first break occurs when Mute
switches low and the speech network is removed from the
line. The pops caused.by breaking the line are then isolated
.from the receiver. The pulse outpUt drives Darlington pair
Q3 and 04 to make and break the line until the digit has
been completely pulsed. Mute then switches high,
returning the spe~fh network to the line.
Switching the MK50981 to On-Hook while it is outpulsing
causes the remaining digits to be outpulsed at 100 x the
normal rate (M/B ratio is then 50/50). Thisfeature provides
a means of rapidly testing the device and is also an efficient
V-4
Other implementations may consider a constant current
diode for the current source or muting the network with a
Darlington. If your application requires muting the network
with a relay, request information on our MK50991
outpulseL
TIMING CHARACTERISTICS
Figure 3
tKD
I--+i
1iflL-_______________________________________
KEY INPUT ~
COLUMN
SCAN
ROW SCAN
ON-HOOK INPUT
l-fruuuuL= -------0Ulllr---lU1JlJlJl
l
PULSE OUTPUT
OSCILLATOR IN
-
-
-
-
-
-' -
-
-
-
-
-
-
~
~-------~~---------------~
T
I
--I 1-- t Da
MUTE OUTPUT
- -
I
:-I...J
DIGIT 2
I
C-D_'_G'_T_'__
I
~--------~
DIGIT4
DIGIT 2
LI!UL---'I-TI--~
~'"'I'lldlll____'___o-'-S'_C_='L:::LA'_T'_'O"_R'_R:.::U_=N_=N:::IN:::G________J.1IWlJIIII
osc. OFF
I ullll~TOR
RUNNING
tj- I~H"lEi·;oo,U~"oo" lL--"'"'''''''__________L__:~_~_~_'_J
(NORMAL!
TEST MODE
NOTE: Pulse Output goes high for Make, low for Break.
TYPICAL APPLICATION
Figure 4
Mia
- - XMTR - - - - - - - -;E~ - - - ,
I
I
I
2 V REF
I
3 C,
.-----------"1
r -____~4 C2
5 C3
,
2
3
" R,
,
5
6
13 R2
7
8
9
12 R3
o
tI
1'R 4
I
I
MK50981
PULSEf"'6'--\--4---j
MITfE r..:.'O"--'L-----------+---l1
FORM A KEYBOARD
c2
Q,
2N5550
0, 2N5401
Q 3 2N5550
Q,
2N5401
Q5
2N6661
D, 1N914
D2 1 N914 ,LOW
C, 20l'F LEAKAGEI
C2 100pF ±20%
C3 100pF ± 20%
R3 22Mfl
R, 390kfl
R, 2.7kfl
Rs 1Mfl
R2 75kfl
Rs 150fl
R7 lookfl
V-5
TEST CIRCUIT
Figure 5
POWER SUPPLY
+
OFF
HOOK
2
MK50981
" } '"0'
12
-!.!-
455kHz Ceramic
10
Resonator
8
0
9
67% BREAK
61% BREAK
l00pF
".~:
KEYBOARD
l00pF
.
MOSTEI(.
INTEGRATED PULSE DIALER WITH REDIAL
MK50982(N)
FEATURES
PIN CONNECTIONS
D Direct telephone-line operation
D CMOS technology is used for low-voltage, low-power
operation
v+_1
D Uses standard 2-of-7 matrix with pas. true common
or the inexpensive Form A-type keyboard
D Ceramic resonator u~ed as frequency reference for
guaranteed accuracy
D Make/Break ratio pin-selectable
D Redial with either
* or #
16 _
PULSE OUTPUT
15 _
ON-HOOK/TEST
V REF 2
COL1- 3
COL2-4
J4_ROW1
13_ROW2
COL3- 5
12_ROW3
V--6
11-ROW4
OSCIN-7
OSCOUT- 8
D Provision for rapid testing
10 MUTE OUTPUT
9_MAKE/BREAK
SELECT .
D On-chip voltage regulator
D Power-Up-Clear circuitry
DESCRIPTION
architecture and more than 17 digits may be dialed in
any number sequence. The limitation is that there can
never be more than 17 digits remaining to be outpulsed.
The MK50982 is a monolithic CMOS integrated circuit
which converts keyboard inputs into pulse signal outputs
simulating a rotary telephone dial. It is designed to
operate directly from the telephone line and can be
interfaced properly to meet telephone specifications in
systems utilizing loop-disconnect signalling. Two outputs, one to puise the telephone line and one to mute
the receiver, are provided to implement the pulse dialer
function. Accurate timing is accomplished 'by using a
ceramic resonator as the frequency reference for the
on-chip oscillator.
The MK50982 also features the redial function. Any
17 -digit number sequence may be redia led with an * or
# key input, providing that the circuit enters the on-hook
mode for a finite time, tOH (refer to discussion on the
On-Hook/Test Pin).
An on-chip "Power-Up-Clear" circuit insures reliable
operation of the MK50982. If the supply to the circuit
should become insufficient to retain data in the memory
(see electrical specifications), a "Power-Up-Clear" will
occur upon regaining ~ proper supply level. This
function will prevent the "Redial" or spontaneous
outpulsing of incorrect data. A new number sequence
may be entered in normal fashion.
The MK50982 is in either the on-hook or off-hook mode
as determined by the input to the pin designated, "OnHook/Test." In order to accept any key inputs, the
MK50982 must be in the off-hook state.
Refer to Figure 1 for a block diagram. Upon sensing a key
input, the normally static oscillator is enabled and the
row and column inputs are alternately strobed to verify
that the keyboard input is valid. The decoded input is
then entered into an on-chip memory. The memory will
store up to 17 digits and allows keystrokes to be entered
at rates comparable to tone dialing telephones. Entering
the first digit (except* or #) clears the memory buffer and
starts the outpulsing sequence. As additional digits are
entered, they are stored in the memory and outpulsed in
turn. The memory has FIFO-(first-in-first-out) type
FUNCTIONAL DESCRIPTION
V+, Pin 1
This is the positive supply input to the part and is
measured relative to V- (pin 6). The voltage on this pin
must be regulated to less than 6 volts using either the
on-chip reference circuitry or an external form of
regulation.
V-7
V-, Pin 6
BLOCK DIAGRAM
Figure 1
v+
v-
This IS the negative supply pin to which VREF is
normally tied (see VREF paragraph).
KEYBOARD INPUTS, Pins 3, 4, 5, 11, 12, 13, 14
The MK50982 incorporates an innovative keyboard
scheme that allows either the standard 2-of-7 keyboard
with positive common or the inexpensive single-contact
(Form A) keyboard to be used, as shown in Figure 3.
A valid key entry is defined by either a single row being
connected to a single col'umn or V+ being simultaneously presented to both a single row and column.
OSC. MAKE/BREAK
When in the On-Hook mode, the row and column inputs
are held high and no keyboard inputs are accepted, thus
preventing any accidental key contacts from causing
excessive current flow.
ON-HOOK
When Off-Hook, the keyboard is completely static until
the initial valid key input is sensed. The oscillator is then
enabled and the row and columns are alternately
scanned (pulled high, then low) to verify the input is
valid. The input must remain valid continuously for
1Oms of debounce time to be accepted.
VREF' Pin 2
The VREF output provides a negative reference voltage
relative to the V+ supply. Its magnitude is a function of
the internal parameters which define the minimum
operating voltage of each part. In a typical application,
as shown in Figure 5, the VREF pin is simply tied to
V-(Pin 6). The internal circuit with its associated I-V
characteristic is shown in Figure 2.
KEYBOARD CONFIGURATION
Figure 3
TYPICAL I-V CHARACTERISTICS
SINGLE CONTACT APPLICATION
Figure 2
1
COL ..._ _ _ _ _....A.
. . . . - - - - _ . ROW
FORM A KEYBOARO
7.0
V+
~±:"'-------'---,-
(PIN 11
COL
~
..
-----~ROW
:z.OF-7 KEYBOARD
6.0
6.0
IREF
mA
VOLTAGE- FED APPLICATION
tr-----"J:.L.._-_-_~~~~~=:::
.
4.0
3.0
V+ ..· - -..
2.0
:z.OF-7 KEYBOARD
(PIN 21
ELECTRONIC INPUT
1---1 tKD
1.0
~+- - . - 3
V+· V REF
4
-
-·n. .
----'--COLUMNS
VOLTS
V+-------n
V
V-8
.
.
L...·-----ROWS
OSCILLATOR IN, OUT, Pins 7,8
The MK50982 contains an on-chip inverter with sufficient gain to provide oscillation when used with a
low-cost 480kHz ceramic resonator (anti-resonant mode).
In addition to the resonator, two external capacitors are
required. Suggested equivalent values for the resonator
are given in the timing· specification section. These
values will insure proper oscillator operation in the
specified voltage range. The MK50982 may be driven
externally with a 480kHz signal on Pin 7.
MAKE/BREAK SELECT, Pin 9
Upon returning Off-Hook, if the first key entry iseither*
or #, the number sequence stored on-chip will be
outpulsed. Any other valid entries will clear the memory
and outpulse the new number sequence.
PULSE OUTPUT, Pin 16
The Pulse output is an open-drain N-Channel transistor
designed to drive an external bipolar transistor. These
transistors would normally be used to pulse the
telephone line! by controlling the loop current through
the network. The timing characteristics of the Pulse
output are shown in Figure 6.
The Make/Break ratio may be selected by connecting
the pin to either the V+ or V- supply. Table 1 indicates
the two popular ratios from which the user can choose.
TEST CIRCUIT
MAKE/BREAK RATIO SELECTION
Table 1
TYPICAL APPLICATION
Input to Make/Break Pin
The schematic diagram in Figure S shows one method
which can be used to interface the pulse dialer with the
telephone line.ln the approach shown, the pulse dialer
circuitry is in series with the speech network.
V+ (Pin 1)
V- (Pin 6)
Pulse Output
MAKE
39%
33%
BREAK
61%
67%
MUTE OUTPUT, Pin 10
The Mute output consists of an open-drain N-channel
transistor. It provides the logic necessary to mute the
receiver while the telephone line is being pulsed. A
typical method of interfacing this output is shown in the
application diagram in FigureS. Figure 6 shows the
timing characteristics of the Mute output.
ON-HOOK/TEST, Pin 15
The "Test" or "On-Hook" input of the MKS0982 has a
100kn pull-up to the positive supply. A V+ input or
allowing the pin to float sets the circuit in its On-Hook or
test mode, while a V- input sets it in the Off-Hook or
Normal Mode. Any digits to be tested in the "OnHook/Test" mode must be entered while "Off-Hook."
When Off-Hook, the MKS0982 will accept key inputs
and outpulse the digits in normal fashion. Upon
completion ofthe last digit, the oscillator is disabled and
the circuit stands by for additional inputs.
Switching the MKS0982 to On-Hook while it is
outpulsing causes the remaining digits to be outpulsed
at 1 00 x the normal rate (M/B ratio is then SO/SO). This
feature provides a means of rapidly testing the device
and is also an efficient method by which the circuitry is
reset. When the outpulsing in this mode, which can take
up to 300ms, is completed, the circuit is deactivated and
will require only the current necessary to sustain the
memory and Power-Up-Clear detect circuitry (refer to
the electrical specifications).
A test circuit is shown in Figure 4. This circuit can be
used to demonstrate the basic operation of the
MKS0982.
A current source of some type is desired to present a
high impedance to the telephone line while
guaranteeing sufficient current to power the MKS0982
(2: 1S0 jJ.A). The current source shown is constructed
with two components, 02 and R1. The current is
regulated by the negative feedback provided by R1 to the
gate of 02. Several other implementations can be
considered, such as a constant current diode, or a
configuration using bipolar transistors.
The purpose of t-ransistor 01 is to take the place of an
additional hookswitch contact. When S1 closes, Q1 is
turned on and On-Hook (pin 1S) is pulled to V-. This sets
the MKS0982 in the normal mode, ready to accept key
inputs.
When going On-Hook, S1 is opened, causing 01 to be
turned off. An on-chipresistor pulls pin 1S to V+ and the
current source is disabled. The purpose of D1 is to limit
any reverse current flow through the current source. A
large-value resistor, R3, allows a small amount of
current to maintain the memory on MKS0982.
To return Off-Hook, S1 is closed, causing 01 to be
turned on thus tying the On-Hook pin to V-. The Pulse
and Mute outputs drive external transistors to perform
the outpulsing function. The receiver is connected
through transistor 06 to the speech network. Mute
causes the transistor to be held on until outpulsing
begins. When Mute switche~ low, the receiver is
removed from the speech network. The pops caused by
breaking the line are then isolated from "the receiver.
The Pulse output drives transistors 03 and OS to make
and break the line until the digit has been completely outpulsed. Mute then switches high, returning the receiver
to the speech network.
V-9
TEST CIRCUIT
Figure 4
POWER SUPPLY
+ '
-
1
16 15kfi
2
15
{-!
--;
FROM
KEYBOARD
--!.
5
t+:-~
30kfi
FROM
KEYBOARD
11
480kHz CERAMIC 7
10
RESONATOR
HOi
OFF·
HOOK
?
*-}
-
MK50982
j
8
9
67%BREA~
61 % BREAK 0 - -
~["100pF~ r-100pF
TYPICAL APPLICATION
Figure 5
>-c-~~
K
TELEP HONE
LINE
>--- AC - r'--
O
°2
s
Rl
~
R2
7 Dl
r-
1
";r=
RS
9
V'
R&
MIS
C1
R6
16
Lq,-~
'Ie.
-11-
v·
1
1
I.
R7
VREF
4 C1 MK50982
C2
16
6
PiJffi
C3
II
2
4
6
7
B
*
0
14
3 1 - - - Rl
13
6 f---- R2
12
9 f---- R3
11
# f---- R4
FORM A KEYBOARD
OSCIN
01. 3. 4 = 2N5550
05.6 = 2N5401
Q2 = 2N3822
GN
=-_B _ _
-
Z
IZ;:Z =
1- i r -
°3
=
-
r-....°4
&
i=C3
01 = 1N914
C1 = 20!,F (low leakage)
C2. 3 = 100pF ± 20%
R1 = 8kO
R2 = 500kO
R3 = 22MO
V-10
"1 r
TYPICAL "600" TYPE
SPEECH NETWORK
OSC
OUT
tJo~t
~----===I
I
1
I
- J
10
MUTE
7
C2
, 0&
RR
3
1
Xro "~
~ °6
R4
ON-HOOK
R4.5 = 390kO
RG.9 = 100kO
R7.8 = 3kO
ABSOLUTE MAxiMUM RATINGS*
DC Supply Voltage, V+ ............... " ......................................................... 6.2 Volts
Operating Temperature ................................................................... -30°C to +60°C
Storage Temperature ....................................................... , . . . . . .. . . .. . -55°C to +85°C
Maximum Power Dissipation (25°C) ... " .......................................................... 500mW
Maximum Voltage on any Pin ..................................................•. (V+) +0.3; (V-) -0.3 Volts
of
• Stresses above U10se listed under "Absolute Maximum Ratnigs" may cause permanent damage to the device. This Isa stress ratmgonly and functional operation
the device at these or any other t;Ondlllon above those Indicated In the operational sections of this specifiCatiOn is not Implied. Exposure to absolute maXimum ratings
for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(-30°C::; TA::; 60°C)
DC CHARACTERISTICS
PARAMETER: SPECIFIC CONDITIONS
SYM
V+
DC Supply Voltage
IMR
Memory Retention Current: Note 1
lop
DC Operating Current: Note 2
VREF
Magnitude of (V+ - VREF): ISUPPLY
1M
Mute Sink Current: V+
= 2.5,
Ip
Pulse Sink Current: V+
= 2.5V,
ILKG
Mute and Pulse Leakage: V+
RKI
TYP*
MIN
MAX
UNITS
6.0
V
0.7
2.5
p.A
100
150
p.A
3.5
V
2.5
= 150 p.A
1.5
2.5
= 0.5V
0.5
2.0
mA
1.0
4.0
mA
Vo
Vo
= 0.5V
= 6.0V,
Vo
= 6.0V
0.001
1.0
p.A
Keyboard Contact Resistance
1.0
k!l
CKI
Keyboard Capacitance
30
pF
KIL
"'0" Logic Level
V-
20% of V+
V
KIH
"'1"' Logic Level
80% of V+
V+
V
KRu
Keyboard Pull-Up Resistance: Note 3
KRD
Keyboard Pull-Down Resistance: Note 3
ROH
On-Hook Pull-Up Resistance
4.0
k!l
100
k!l
100
k!l
NOTES
'TYPlcal values are to be used as a deSign aid and are not subject to production
2.
Current reqUired for proper CIrcuit functIon. Off- Hook model, Valid Key Input,
testing.
1. Current necessary for memory to be maintained. All outputs unloaded.On-
3.
Keyboard to be scanned at 500Hz when OSCIllator enabled. Rowand Column
to alternately pull high and low
Hook mode.
AC CHARACTERISTICS* (The timing Relationships are shown in Figure 6)
MIN
TYP
MAX
UNITS
SYM
PARAMETER: SPECIFIC CONDITIONS
fosc
Oscillator Frequency (antiresonant mode): Note 1
tOB
Keyboard Debounce Time
tKD
Time for Valid Key Entry
tos
Oscillator Start-Up Time
6.0
ms
PR
Pulse Rate
10.0
pps
tB
Break Time: Pin 9 Tied to V+/Tied to V-
tlDP
Interdigital Pause
480
kHz
10
ms
ms
40
61.0/67.0
800
ms
ms
NOTES:
*Typical values are exact with a nominal 480 kHz frequence reference (except
for oscillator start-up time).
Ceramic resonator should have the following equivalent values R <20n. RA ~
70k n. Co:5 500pF.
V-11
TIMING CHARACTERISTICS
Figure 6
tKD
R
r-:;-]'-________________-'--_ _
KEY INPUT ~
=+i k=- tos
, DIGIT 4
I
~g;~MN ~-------=J1JlI~~---------------~
ROWSCAN
~I
~----------=tJ1J~,
---------------~I
!
ON-HOOK INPUT
,...-----
-+I ~tDB
MUTE OUTPUT
PULSE OUTPUT
o.c"~m""
~I
~
TI :f.
.
__
I
i
I I
lOOms
I
I
I
D.IGlT4
I
!
I
DIGIT2 ______~.
DIGIT4
1 ___----','----_
LJLr1JLJ
LJ1JIJ1Jr--1----L,----'LI1J
I
I
I
A::: RUNNlu:iUIIr-O::-:S:=C'--:°l:=F::-I:-'~Irl
' --.--::-OS:-::C"",L-:-LA:-:T:-::O'::'R-R-UN-N-:,N""'G-------:-l-:~-~-:--'sdlllllill
,
OFF-H~~~m~ODE
(NORMAL)
ON· HOOK I
TEST MODE
V-12
REOIAL
MODE---------~,
MOSTEI(@
INTEGRATED PULSE DIALER WITH REDIAL
MK50991(N)
FEATURES
PIN CONNECTIONS
D Direct telephone-line operation
D CMOS technology is used for low-voltage,
V+_1
low-power operation
18 -PULSE OUTPUT
VREF-2
17 ___ ~~S~OOK/
or the inexpensive Form A-type keyboard
COL 1 - - 3
16---ROW 1
D Inexpensive RC oscillator used as frequency
COL 2 _ 4
15 ___ ROW 2
D Uses either a standard 2-of-7 matrix keyboard
reference
D Redial with either a
* or # input
COL 3 _ 5
14---ROW3
V-~6
13 ___ ROW4
RC1~7
D Make/Break ratio and pulse rate are pin-selectable
12 _MUTE OUTPUT
RC2_8
11---M/B SELECT
RC3-g
10---20/10 PPS SELECT
D Provision for rapid testing
D On-chip voltage regulator
D Power-up-clear circuitry
DESCRIPTION
The MK50991 is a monolithic CMOS integrated circuit
which converts keyboard inputs into pulse signal
outputs simulating a rotary telephone dial. It is designed
to operate directly from the telephone line and can be
interfaced properly to meet telephone specifications in
systems utilizing loop-disconnect signalling. Two
outputs are provided to implement the pulse dialer
function, one to pulse the line and another to mute the
receiver. The mute output can be interfaced with a
bistable latching relay in applications with this
requirement.
The MK50991 is in either the on-hook or off-hook mode
as determined by the input to the pin designated "OnHook/Test." In order to accept any key inputs, the
MK50991 must be in the off-hook state. Upon sensing a
key input, the normally static oscillator is enabled and
the row and column inputs are alternately strobed to
verify that the keyboard input is valid. The decoded input
is then entered into an on-chip memory. The memory
will store up to 17 digits and allows keystrokes to be
entered at rates comparable to tone dialing telephones.
Entering the first digit (except * or #) clears the memory
buffer and starts the outpulsing sequence. As additional
digits are entered, they are stored in the memory and
outpulsed in turn. The memory has a FIFO-(first-infirst-out) type architecture and more than 17 digits may
be dialed in any number sequence. The limitation is that
there can never be more than 17 digits remaining to be
outpulsed.
The MK50991 also features the redial function. Any 17digit number sequence may be redialed with a * or # key
input, providing that the circuit enters the on-hook
mode for a finite time, tOH (refer to discussion on the
On-Hook/Test pin).
An on-chip "Power-Up-Clear" circuit insures reliable
operation of the MK50991. If the supply to the circuit
should become insufficient to retain data in the memory
(see electrical specifications), a "Power-Up-Clear" will
occur upon regaining a proper supply level. This
function will prevent the "Redial" or spontaneous
outpulsing of incorrect data. A new number sequence
may then be entered in normal fashion.
V-13
ABSOLUTE MAXIMUM RATINGS*
DC Supply Voltage, V+ .................... ; .................................................... 6.2 Volts
Operating Temperature ................................................................... -30°C to +60°C
Storage Temperature ...................................................................... -55°C to +85°C
Maximum Power Dissipation 25°C .................................. , ............................ 500mW
Maximum Voltage on any Pin ................................................... (V+) + 0.3; (V-) - 0.3 Volts
·Stresses above these listed under "Absolute Maximum Ratings" may cause permanent damage tathe device. This is a stress rating only and functional operation of
the device at these or any other condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
DC CHARACTERISTICS
-30°C:::; TA :::; 60°C
SYM
MIN
PARAMETER
V+
DC Operating Voltage
IMR
Memory Retention Current: (Note 1)
lOp
DC Operating Current: (Note 2)
VREF
Magnitude of (V+ - VREF ):
I supply = 15OIJ-A
TYP*
2.5
= 2.5V, Vo = 0.5V
IML
Mute Sink Current: V+
IMH
Mute Source Current: V+
2.0V
Ip
Pulse Sink Current: V+
ILKG
Mute and Pulse Leakage: V+
6.0V
MAX
UNITS
6.0
Volts
0.7
2.5
IJ-A
100
150
IJ-A
1.5
2.5
3.5
Volts
0.5
2.0
mA
0.5
2.0
mA
1.0
4.0
mA
= 2.5V, Vo =
= 2.5V, Vo = 0.5V
= 6.0V, Vo =
0.001
1.0
IJ-A
RKI
Keyboard Contact Resistance
1.0
kD.
CKI
Keyboard Capacitance
30
pF
KIL
. Keyboard "0" Logic Level
V-
20% of V+
Volts
KIH
Keyboard "1" Logic Level
80% of V+
V+
Volts
KRU
Keyboard Pull-Up Resistance: (Note 3)
100
kD.
KRD
Keyboard Pull-Down Resistance: (Note 3)
4.0
kD.
ROH
On-Hook Pull-Up Resistance
100
kD.
NOTES:
*Typical values are to be used as a design aid and are not subject to production
testing.
1. Current necessary for memory to be maintained. All outputs unloaded.
On-Hook mode. VREF tied to V-.
2. Current r'equiredfor proper Circuit function. Off-Hook Mode. Valid key input.
VREF tied to V-.
3. Keyboard to be scanned at 500Hz when oscillator enabled. Rowand Column
to alternately pull high and low.
V-14
AC CHARACTERISTICS
(The Timing Relationships are shown in Figure 4)
SYM
PARAMETER
MIN
TYP
MAX
UNITS
fOSC
Oscillator Frequency (Note 1)
4.0
kHz
LlfOSCl
Frequency Stability: 2.5 to 3.5V
(Note 2)
±4
%
Llf OSC2
Frequency Stability: 3.5 to 6.0V
(Note 2)
±4
%
LlfOSC3
Frequency Stability: 150-500 JJ.A
(Note 3)
±3
%
PR
Pulse Rate: Pin 10 tied to V+/V-
20/10
pps
tOB
Keyboard Oebounce Time
10
ms
t KO
Time for Valid Key Entry
tB
Break Time: Pin 9 tied to V+/
tied to V-
tIDP, tpop
Interdigital Pause, Predigital Pause
(Note 4)
tMO
Mute Overlap of Pulse
40
ms
66.0/60.0
ms
800+ tM
ms
5
ms
NOTES:
"Typical" values are exact assuming a 4kHz frequency reference.
1. A change in the frequency will result in a proportional chaMge in all circuit
timing.
2. For stated voltages, the given "typical" .6.fdsc holds from part to part over
the stated operating temperature range.
3. Using VREF in conjunction with a current source results in the given
"typical" .6.fOSC from partto part overthe stated operating temperature and
current.
4. Time from last break to next break. tM = 100ms-tB = make time.
Functions of the individual pins are described below:
VREF TYPICAL I-V CHARACTERISTICS
Figure 1
V+, Pin 1
7.0
This is the positive supply input to the part and is
measured relative to V- (pin 6). The voltage on this pin
must be regulated to less than 6 volts ,using either the
on-chip reference circuitry or an external form of
regulation.
6.0
5.0
4.0
The VREF output provides a negative reference voltage
relative to the V+ supply. Its magnitude is a function of
the internal parameters which define the minimum
operating voltage of each part. In a typical application,
as shown in Figure 5, the VREF pin is simply tied to
V-(Pin 6). The internal circuit with its associated I-V
characteristic is shown in Figure 1.
KEYBOARD INPUTS, Pins 3.4. 5. 13. 14, 15. 16
3.0
2.0
PIN 2
-VREF
1.0
1.0
The MK50991 incorporates an innovative keyboard
V-15
2.0
V+
-v REF
3.0
4.0
VOLTS
5.0
scheme that allows either the standard 2-of-7 keyboard
with positive common or theinexpensive single contact
(Form A) keyboard to be used.
A valid key entry is defined by either a single row being
connected to a single column or V- being
simultaneously presented to both a single row and
column.
When in the On-Hook mode, the row and column inputs
are held high and no keyboard inputs are accepted.
When Off-Hook, the keyboard is completely static until
the initial valid key input is sensed. The oscillator is then
enabled and the rows and columns are alternately
scanned (pulled high, then low) to verify the input is
valid. The input must remain valid continuously for 10
ms of debounce time to be accepted.
20/10 PPS SELECT, Pin 10
Tying this input to either V+ (Pin 1) or V- (Pin 6) will
select a pulse rate of either 20 or 10 pps respectively.
MAKE/BREAK SELECT, Pin 11
The Make/Break ratio may be selected by connecting
the pin to either the V+ or V- supply. The table below
indicates the two popular rati'os from which the user
can choose.
MAKE/BREAK RATIO SELECTION
Table 1
INPUT TO
MAKE/BREAK PIN
KEYBOARD CONFIGURATIONS
Figure 2
V_lt~'oc
~
COL~
~ROW
[i::
v-
2-of-7 Matrix Keyboard
~COL
LJ
Electronic I.nput
The MK50991 contains on-chip inverters to provide an
oscillator which will operate with a minimum of
external components. Figure 3 shows the on-chip
configuration with the necessary external components.
Optimum stability occurs with the ratio K = Rs/R equal
to 10. The oscillator period is given by:"
3.5KCs 2K
[ 1.386+C - - K+ 1
In
(
K
) ]
1.5K + 0.5
where Cs is the stray capacitance on Pin 7. Accuracy
and stability will be enhanced'with the capacitance
minimized.
OSCILLATOR CONFIGURATION
Figure 3
DISABLE
8
7
c·
R•
s
66%
V- (Pin 6)
40%
60%
ON-HOOK/TEST, Pin 17
RC OSCILLATOR; Pins 7,8,9
T = RC
BREAK
34%
The Mute output consists of a complementary pair of
CMOS transistors. It provides the logic necessary to be
interfaced with a bistable latching relay to Mute the
speech network. Upon coming off-hook, a negative
transition on Mute will insure the speech network is
properly connected to the telephone line. When
outpulsing begins, a positive transition will switch the
relay, continuously muting the network until the entire
number sequence entered is outpulsed. Figure4 shows,
in detail, the timing diagram of the Mute Output
2·of-7 Matrix Keyboard
Negative Common
v+~
MAKE
V+ (Pin 1)
MUTE OUTPUT, Pin 12
~ROW
U
Form A Type Keyboard
PULSE OUTPUT
9
The "Test" or "On-Hook" input of the MK50991 has a
100kD. pull-up to the positive supply. A V+ input or
allowing the pin to float sets the circuit in its On-Hook or
test mode while a V- input sets it in the Off-Hook or
Normal Mode.
When Off-Hook, the MK50991 will accept key inputs
and outpulse the digits in normal fashion. Upon
completion of the last digit, the oscillator is disabled and
the circuit stands by for additional inputs.
Switching the MK50991 to On-Hook while it is
outpulsing causes the remainingdigits to be outpulsed
at 100 x the normal rate (M/B ratio is then 50/50). This
feature provides a means of rapidly testing the device
and is also an efficient method by which the circuitry is
reset When the outpulsing in this mode, which can take
up to 300ms, is completed, the circuit is deactivated and
will require only the current necessary to sustain the
memory and Power-Up-Clear detect circuitry (refer to
the electrical specifications).
Upon returning Off-Hook, a negative transistion on the
Mute Output will insure the speech network is
connected to the line. If the first key entry is either a * or
#, the number sequence stored on-chip will be
outpulsed. Any other valid key entries will clear the
memory and outpulse the new number sequence.
V-16
TIMING CHARACTERISTICS
Figure 4
DIGIT
DIGIT
KEY INPUT -----~
REDIAL
~r----------
CO~~~~ -lnru-uut_~O~~=-<:?~U~~ ~C!'::: __ ~- ROW SCAN
ON-HOOK
INPUT
MUTE
OUTPUT
PULSE
OUTPUT
RC
- - - -
----=uu--
~_5_0~~:'_R!?,!!_S~~~ _____ ~_________
~
!
:
I
~
~
:
I:
:
I:
I
I I
.ruur---
.J1'-----------~!
i
L---.lJ
I
ILJ
~
t'I
:
U
i: I
:
~ ~
I I
I I I
: I
I!
I :
OUTP~T ~H-=9~CJ~!:~T-O-R------7~J~-----------1~
~ r--bPDP~ ~IjDP~lf.~j l-t
NORMAL DIALING
Hg~K--.....,..------OFF-HOOK
MODE
MO
lb=
I--- RJ8~~L~' ~'
OF~~gEOK
TEST
MODE
PULSE OUTPUT. Pin 18
The Pulse Output consists of an open-drain N-channel
transistor. This output provides the logic necessary to
pulse the telephone line with the correct Make/Break,
pulse rate, and interdigital pause timings. The timing
characteristic of the Pulse Output is shown in Figure 4
above.
TYPICAL APPLICATION
The schematic diagram in Figure 5 shows one method
which can be used to interface the MK50991 with the
telephone line. In this approach. the speech network is
connected directly to the telephone line through a
metallic relay contact. The pulse signalling circuitry is in
parallel with the speech network.
A current source of some type is desired to present a
high impedance to the telephone line while
guaranteeing sufficient current to power the MK50991
(>150J.lA). Transistor Q2 provides the source current to
the device. The magnitude of this current is determined
by the voltage on R1 due to the forward-biased diodes
01 and 02. Transistor Q1 provides a regulated bias
current to the diodes as well as Q2.
When in the On-Hook mode, 51 and 52 are open. The
current SOlirce is disabled in this manner and only a
small amount of current, supplied through R3, is needed
to maintain data in the memory. The relay is open,
thereby disconnecting the speech network from the
telephone line.
When coming Off-Hook, switches 51 and 52 close,
connecting the On-Hook input to V-. Immediately the
output of Mute switches low. This transition pulses the
relay through Q5 and Q6, latching it in the closed
position. The speech network is now attached directly to
the telephone line for normal conversation. Diode 03
will hold the 'pulsing Darlington composed of transistors
Q3 and Q4 off.
Upon receiving a valid key entry, Mute switches high.
This transition pulses the relay to its open state, thereby
muting the network. The loop current is still passed
through the Darlington pair, Q3 and Q4' for a predigital
pause time of approximately 840ms. (tpDP). Break is
accomplished when the Pulse output switches low,
cutting the Darlington off. During break, current flow is
limited to the current source and the Pulse pullup
resistor R4, insuring a high impedence in this interval.
Pulsing of the complete digit continues in this manner.
Each digit in the number sequence dialed is separated
by standard interdigital pauses (tIDP)'
After the final digit is outpulsed, the Mute Output
returns low and the speech network is connected back
to the telephone line through the relay contact for
normal conversation. Returning On-Hook causes Mute
to switch high, removing the network from the line.
Applications which do not require operation with a
bistable relay may use our MK50981 pulse dialer to
better advantage.
V-17
TYPICAL APPLICATION
Figure 5
>---~------~.AC
+
TELEPHONE
LINE
>-------1f---r----1 AC
0,
02
03
04
06
06
R,
R2
R3
R4
R6
R7
Ra
= 2N5550
= 2N5401
= 2N5550
= 2N5550
= 2N2222
= 2N2303
= 2.7kl1
= 75kl1
= 22 Mfl
= 390kfl
= 2 Ml1
= 15011
= 100kfl
= 220kfl
C,
~
Rs
'aa:"
~
z
MUTE
6
r'-,,2~r--+
V-
+-------:---*---~_=f2 VAEF
3 C,
.-----------"1
.--------'94 C2
MK50991 N
sc;
7
22"F
P'U'LsE 18
,6A,
2
3
S
6
a
9
,'5 R3iG
0
#
'3A4
C:i~
390pF
C 3 = 10l'F
0, = 1 N914
O2 = 1N914
0 3 = 1N4004
M/B
20/'0
11
10
L _____________________________________ ...JI
Relay: 1.5V. bistable latching
TEST CIRCUIT
Figure 6
POWER
SUPPLY
t
18
FROM
KEYBOARD
2
17
3
16
{-
OFF
HOOK
1M
-----'..! .
5
}
MK50991N
'"OM
KEYBOARD
6
390pF
11
220K
10
V-18
20pp.
60% BREAK'
66% BREAK
1M
MOSTEI{®
INTEGRATED PULSE DIALER WITH REDIAL
MK50992{N)
FEATURES
PIN CONNECTIONS
o Direct Telephone Line Operation
o
Uses standard 2-of-7 matrix with neg. true common or
the inexpensive Form A-type keyboard
o
CMOS Technology for low-Voltage, low-Power
Operation
o
Supply Voltage Range 2.5 to 6 volts
V+VREF-COL 1__
Cal 2 __
4
Cal 3 - -
5
MK50992
o
MAKE/BREAK Ratio Pin-Selectable
V--
6
o
20/10 pps Pin-selectable
RC1_
7
o
Redial with # or *
RC2_
8
o
Continuous Mute
RC3-
9
o
Inexpensive RC Oscillator
DESCRIPTION
The MK50992 is a monolithic CMOS integrated circuit
which uses an inexpensive RC oscillator for its frequency
reference and provides all the features required for
implementing a pulse dialer with. redial. It operates directly
off the telephone line supply and converts 2-of-7 keyboard
inputs into pulse signals simulating a rotary telephone dial.
When not outpulsing, the MK50992 consumes only microamperes of current.
When off-hook, the MK50992 senses a key down condition,
verifies that only one key is depressed and then enters the
key's code into an on-chip memory.
The memory will store up to 17 digits, and allows keystrokes
to be entered at rates comparable to tone dialing
telephones. Entering the first digit starts a predigital pause
counter and clears the memory buffer. At the end of the
predigital pause, outpulsing begins. As digits are entered.
during the outpulsing period they will also be stored in the
memory. Outpulsing will continue until all entered digits
have been dialed. The first 17 digits entered will be stored in
the on-chip redial memory and can be redialed by pressing
either # or *, provided that the receiver has gone on-hook for
the minimum tOH (refer to the electrical specifications
section).
.
When on-hook, key inputs will not be recognized because
the oscillator is disabled. This oscillator inhibit prevents the
circuit from drawing excessive current when on-hook.
V-19
ABSOLUTE MAXIMUM RATINGS*
DC Supply Voltage, V+ ...............................................•............................ 6.2 Volts
Operating Temperature ....................................................................... -30° to +60°C
Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -55°C to +85°C
Maximum Power Dissipation @ 25°C .....................................•.....................•.... 500mW
Maximum Voltage on any Pin Relative to V- .......................•................................. -0.3 Volts
Maximum Voltage on any Pin Relative to V+ .....................•....•....................•.........+0.3 Volts
·Stressesabovethose listed under"Absolute Maximum Ratings" maycause permanent damage tothedevice. This isa stress rating only and functional operation of
the device at these or any other condition above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
-30°C :s TA :s 60°C
DC CHARACTERISTICS
SYM
PARAMETER
V+
DC Supply Voltage
RKI
CK1
Key Input (Rl - 4R, Cl - C3)
Contact Resistance
Keyboard Capacitance
MIN
TYP
MAX
UNITS
6.0
V
1
30
kn
pF
V-
20% ofV+
V
80% ofV+
V+
V
2.5
KIL
KIH
Key Input Level (Rl - R4, Cl - C3)
2-of-7 input mode and all
electronic switching
K1RU
Keyboard Pull-Up Resistance
100
kn
KIRD
Keyboard Pull-Down Resistance
4.0
kn
1M
Mute Sink Current
@V o =0.5V, V+ = 2.5V
500
pA
Pulse Output Sink Current
@V o =0.5V, V+ = 2.5V
1.0
mA
Ip
NOTES
IMR
Memory Retention Current
0.7
2.5
pA
7
lop
Operating Current
100
150
pA
1
ILKG
Mute or Pulse Off Leakage
V+ = 6.0V
Va = 6.0V
.001
1
pA
IREF
V REF 0fJtput Source Current
(VflEF = -6.0V REF to V+)
1
7
mA
8
internal parameters of the MK50992. V REF provides a
negative voltage reference to the V+ supply. Its magnitude
will be approximately 0.6 volt greater than the minimum
operating voltage of each particular MK50992.
Functions of the individual pins are described below.
V+ (Pin 1)
This is the positive supply pin. The voltage on this pin is
measured relative to V- and is supplied from a 150 J.lA
current source. This voltage must be regulated to less than
6.0 volts.
The typical application would be to connect the VREF pin to
theV-pin(Pin 6). The supplytotheV+ pin (Pin 1) should then
be regulated to 150pA (lop max). With this amount of supply
current, operation of the MK50992 is guaranteed.
V REF (Pin 2)
The VREF output provides a reference voltage that tracks
The internal circuit ofthe VREF function is shown in Figure 1
with its associated I-V characteristic.
V-20
AC CHARACTERISTICS
SYM
PARAMETER
MIN
Fosc
Oscillator Frequency
tOB
Key Input Debounce Time
tKO
Key Down time for Valid Entry
tKR
Key Down Time During Two-Key
Roll Over
TYP
MAX
UNITS
NOTES
4
kHz
4
10
ms
3,6
40
ms
2,3
5
ms
3
Oscillator Start-Up Time
(V+ = 2.5V)
1
ms
t MO
Mute Valid After Last Outpulse
5
ms
3,6
PR
Pulse Output Pulse Rate
10
pps
5
toH
On-Hook Time Required to
Clear Memory
ms
3
tpop
Pre-Digital pause
800
ms
3,6
t lOP
Inter-Digital Pause
800
ms
3,6
llf
Frequency Stability (2.5V - 3.5V)
±4
%
llf
Frequency Stability (3.5V - 6.0V)
±4
%
llf
Frequency Stability (with V REF used)
(IREF = 250pA - 5ooJ,lA)
±2.5
%
tos
300
NOTES:
5. If pin 10 is tied to V+, the Pulse Output Pulse Rate will be 20pps.
6 .. If the 20pps option is selected, the time will be % these shown.
7. Current necessary for memory to be maintained. All outputs unloaded..
1. Output and V REF unloaded.
2. Debounce plus oscillator startup time::;;; 40ms.
3. These times are directly proportional to the oscillator frequency.
4. R~ = 2Mfl, R ;: ; 220Kn. C = 390pF. See oscillator paragraph.
8,c,Refer to Figure 1
V REF TYPICAL I-V CHARACTERISTICS
KEYBOARD INPUTS (Pins 3, 4, 5,13,14,15,16)
Figure 1
The MK50992 incorporates an innovative keyboard
scheme that allows either the standard 2-of-7 keyboard
with negative common or the inexpensive single
contact (Form A) keyboard to be used.
7.0
•. 0
5.0
A valid key entry is defined by either a single row being
connected to a single column or V- being
simultaneously presented to both a single row and
column.
4.0
3.0
PIN 2
2.0
1.0
1.0
20
IV+)-VREF
3.0
4.0
5.0
VOLTS
When in the On-Hook mode, the row and column inputs
are held high and no keyboard inputs are accepted.
When Off-Hook, the keyboard is completely static until
the initial valid key input is sensed. The oscillator is then
enabled and the rows and columns are alternately
scanned (pulled high, then low) to verify the input is
valid. The input must remain valid continuously for
10ms of debounce time to be accepted.
V-21
controlled by connectingV+ orV-tothis pin as shown in
the following table.
KEYBOARD CONFIGURATIONS
Figure 2
L--ROW
COL----..J
FORM A TYPE KEYBOARD
[1::
~t:L--::
MAKE/BREAK RATIO SELECTION
Table 1
Input To
Make/Break Pin
2-0F-7 MATRIX KEYBOARD
NEGATIVE COMMON
V+----r
r - - - - COL
VLJ
V+ ~
r----ROW
VLJ
2-0F-7MATRIX KEYBOARD
Pulse Output
Make
Break
V+ (Pin 1)
34%
66%
v- (Pin 6)
40%
60%
ELECTRONIC INPUT
MUTE OUTPUT (Pin 12)
OSCILLATOR CONFIGURATION
Figure 3
The Mute output is an open-drain N-channel transistor
designed to drive an external bipolar transistor. This
circuitry is usually used to mute the receiver during
outpulsing.
DISABLE
8
7
As shown in Figure 4. the MK50992 Mute output turns
on (pulls to. the V- supply) at the beginning of the
predigital pause and turns off (goes to an open circuit)
following the last break. The delay from the end of the
last break until the Mute output turns off is mute overlap
and is specified as t MO '
9
C*
OSCILLATOR (Pins 7. 8. 9)
TEST/ON HOOK (Pin 17)
The MK50992 contains on-chip inverters to provide an
oscillator which will operate with a minimum of
external components. Figure 3 shows' the on-chip
configuration with the necessary external components.
Optimum stability occurs with the ratio K = Rs/R equal to
10. The oscillator period is given by:
.
The "Test" or "On-Hook" input of the MK50992 has a
100kfl pull-Up to the positive supply. A V+ input or
allowing the pin to float sets the circuit in its On-Hook or
test mode while a V- input sets it in the Off-Hook or
Normal Mode.
T=RC[1.386+(~.5KCs)/C-
(2K/(K+l ))In (K/(1.5K+0.5))]
where Cs is the stray capacitance on Pin 7. Accuracy and
stability will be enhanced with this capacitance
minimized.
V- (Pin 6)
This is the negative supply pin and is normally tied to
V REF (see V REF paragraph).
20/10 PPS (Pin 10)
Tying this pin to V- will select an Output Pulse Rate of
10pps. Tying the pin to V+ will select an Output Pulse
Rate of 20pps.
MAKE/BREAK (Pin 11)
The MAKE/BREAK pin· controls the MAKE/BREAK
ratio of the pulse output: The MAKE/BREAK ratio is
V-22
When Off-Hook. the MK50992 will accept key inputs
and outpulse the digits in normal fashion. Upon
completion of the last digit, the oscillator is disabled and
the circuit stands by for additional inputs,
Switching the MK50992 to On-Hook while it is
outpulsing causes the remaining digits to be outpulsed
at 100 x the normal rate (M/B ratio is then 50/50). This
feature provides a means of rapidly testing the device
and is also an efficient method by which the circuitry is
reset. When the outpulsing in this mode. which can take
up to 300ms. is completed, the circuit is deactivated and
will require only the current necessary to sustain the
memory and Power-Up-Clear detect circuitry (refer to
the electrical specifications).
Upon returning Off-Hook. a negative transistion on the
Mute Output will insure the speech network is
connected to the line. If the first key entry is either a * or
#, the number sequence stored on-chip will be
outpulsed. Any other valid key entries will clear the
memory and outpulse the new number sequence,
The MK50992 Pulse output is an open circuit during
make and pulls to the V- supply during break.
PULSE OUTPUT (Pin 18)
The Pulse output is an open drain N-channel tranistor
designed to drive an external bipolar transistor. These
transistors would normally be used to pulse the
telephone line by disconnecting and connecting the
network.
As shown in Figure 4, outpulsing starts with a make
before break.
A typical application is shown in Figure 6. This circuit
will produce the timing shown in Figure 4.
TIMING CHARACTERISTICS
Figure 4
REDIAL
---------------.~r---------------------
KEY INPUT
COLUMN SCAN ~__5-,?~,:!Z_C9':U_M_N_S~~~ __ ~ _________ ~-ROW SCAN ~__5_0!l_H!_f!~~~~~~_n __~_n_.
ON-HOOK INPUT
MUTE OUTPUT
~
"JI
-----ri
PULSE OUTPUT
:: :
,
::
_______
U
II
.
I
'
:
I
I
I
~
I
'
:
I:
I I
I "
I
I
RC20UTPUT-------i-~irinnn4kHzOSCILLATOR
:::
I'
"
.
:'
,
UUUUL--- ------r-------------'-~------------ ----..,~
. '-i ::=-',:~-i ~,,,~,,~ ~~'""
~
ON
HOOK
NORMAL DIALING
~'.REDIA.'~·
MODE
. . . . - - " - - - - - - O F F HOOK MODE
OFF HOOK
MODE
TEST CIRCUIT
Figure 5
POWER
SUPPLY
+
~
18 1M
~
17
~
~}
{~
FROM
~
KEYBOARD ~ MK509921N) ~
13
6
2M
7
12
H;~
220K
11
9
10
I
OFF
HOOK
,./
FROM
KEYBOARD
60%BREA~
66% BREAK 0---
20PPs~
10pp,
V-23
1M
I
TEST
MODE
TYPICAL APPLICATION
Figure 6
TIP
RING
e-____+-~~----~2,V
v+
6 REF
'--------:-Iv.--____---.:3::.jc:;- MuTErl~2"'----iH
r -____4~C- PULSE~1~8~~~~~
2
5 C3
R,
NRC,
16R"
456
#
R
6
~
15..2. '"
8 C2
R2 " RC2t---"o--9
14-- :::;:
R3
789
o
7
13R;
M/B 11
17
ON
~~~-e----~HOOK
10i20
10
TYPICAL "500" TYPE
SPEECH NETWORK
Rl
R2
R3
R4
R5
R6
= 560k,O
= l.4k,O
= 470k,O
= 330kn
= 2M,O
= 220k,O
R7 = l00k,O
R8 = 3k'o
R9 = 3k'o
Rl0 = l00k,O
Rll=10M'o
01
02
03
04
05
= 2N5401
2N5550
= 2N5550
= 2N5401
= 2N5401
=
V-24
01 = IN4004
02 = IN4004
03 = IN4004
04 = IN4004
05 = IN914
06 = IN914
07 = IN4004
Cl
C2
= 681'F (Low Leakage)
= 390pF
= HOOK SWITCH
Sl
S2 = HOOK SWITCH
Zl = 120-volt, l-watt
zener
MOSTEI(.
TELECOMMUNICATION PRODUCTS
Current Sources
The purpose of this application brief is to discuss the use of
constant current sources in pulse-dialer application circuits.
Current sources serve two important purposes in pulsedialer applications. First, they provide a relatively constant
current to the pulse dialer so that it may operate
consistently during pulsing. Secondly, constant current
sources help maintain the high break impedance that is
required by U.S. telephone specifications for loop
disconnect dialers.
diode drop. The current through Q1 is determined by the
value of R1 according to the equation:
For a typical pulse-dialer application, the following
components are recommended:
Q1 = 2N5401
CR1 = CR2 = 1 N914
R1 = 1.5 kf1
R2 = 560 kf1
There are various configurations of current sources which
can be used to achieve these goals. In this application brief,
three different configurations will be examined. All of these
current sources are interchangeable.
One of the most commonly used configurations consists of
two diodes, one transistor, and two resistors. This
configuration is used in the MK50992 typical application. A
schematic of this current source is shown in Figure 1.
Another frequently used current source configuration
consists of an N-channel JFET, one resistor, and one diode.
This configuration is used in the MK50982 typical
application circuit and is shown in Figure 2.
TO POSITIVE SIDE
OF BRIDGE FROM
TELEPHONE LINE
Figure 2
Figure 1
+
D
G
CR1
Q2
R1
S
TO
BRIDGE
CR2
R3·
R2
CR3
TO V+ (PIN 1)
OF PULSE
DIALER
TO V+ (PIN 1) OF
PULSE DIALER
The operation of this type of current source is as follows.
Diodes CR1 and CR2 ensure that the base oftransistor Q1 is
biased at two diode drops below the voltage at the positive
side of the bridge. Resistor R2 provides bias current for
diodes CR1 and CR2 and transistor Q1. R2 must be carefully
selected to bias CR1 and CR2 past the knee of the currentvoltage curve, yet still satisfy break impedance requirements. The emitter-to-base voltage of Q1 is approximately
equal to one diode drop (VCR = 0.4 - 0.7 V). Therefore, the
voltage drop across R1 is also approximately equal to one
With this type of configuration, the value of resistor R3 and
the characteristics of transistor Q2 determine the amount of
current that flows to the pulse dialer. As current through R3
increases, the voltage across it (which corresponds to V GS
of the FEl) also increases, thus regulating the amount of
current that flows through Q2.
Diode CR3 is used to block reverse-current flow through the
current source to the pulse dialer.
V-25
For a typical pulse-dialer application, the recommended
components are:
Figure 3
02 = 2N3822
R3 = 12 kO
CR3 = 1N914
TO POSITIVE SIDE
OF BRIDGE FROM
TELEPHONE LINE
CR4
This current source scheme can also be constructed using
different types of FETs. The position of R3 will depend upon
the type of FET selected.
This type of current source has two main disadvantages
over the type shown in Figure 1. The first disadvantage is
cost. The FET selected must have a VDS high enough to
withstand open-circuit, telephone-line voltage (1 00 V max),
and will be more expensive than a comparable bipolar
transistor. The second disadvantage is poor stability. The
currentthat flows through 02 will vary with changes in the
Vp(pinch-off voltage) of the FET. Careful selection ofthe FET
used for 02 and the tolerance of R3 will decrease the
variability of this current source.
A third type of current source in common use is the constant
current or regulator diode. This type of current source
configuration is shown in Figure 3.
The constant current diode is composed of a transistor
similar to the one shown in Figure 2, but with a built-in
resistor and feedback loop. These constant current diodes
operate according to the same principles as the current
source shown in Figure 2.
TO V+ (PIN 1) OF
PULSE DIALER
For this type of current source configuration, the
recommended silicon diode(CR5) isa 1N914. Agermanium
diode, such as the 1N270, may be used for CR3' and CR5 in
Figures 2 and 3 respectively if a smaller voltage drop across
the current source is desired. This will enable the pulse
dialer to operate with a slightly lower voltage present at the
telephone line. The constant current diode(CR4)can be any
commercially available regulator diode such as the Siliconix
CR022, the Siliconix J522, or the Teledyne TCR500. Any
constant current diode can be used as long as it"provides the
minimum current required for operation of the selected
Mostek dialer.
V-26
MOSTEI{.
TELECOMMUNICATIONS
Pulse Dialer Comparison
The purpose of this Application Brief is to define the major
differences between Mostek's pulse dialers.
MK5099 - Pin 11 tied to V+ =39%/61 %
Pin 11 tied to V- = 33%/67%
The first Mostek pulse dialers were the MK5098 and the
MK5099. Later, the MK50981 and MK50991 were
developed to meet other requirements which the MK5098
and MK5099 did not meet. However, these are not direct
replacements for the MK5098 and MK5099. Therefore, the
improved MK50982 and MK50992 were designed to
directly replace the MK5098 and MK5099, respectively. All
of Mostek's pulse dialers, except the MK5098, have the
last-number-redial feature.
MK50991 /992 - Pin 11 tied to V+ = 34%/66%
Pin 11 tied to V- =40%/60%
The following is a comparison of all of the major differences
between Mostek pulse dialers.
• Pulse Rate
MK5098/981/982 - 10 pps
MK5099/991 /992 - Pin 10 tied to V+ = 20 pps
Pin 10 tied to V- = 10 pps
OUTPUT LOGIC LEVELS
• Pulse
MK5098/982/99/991 /992 - Pulse output (active low,
KEYBOARD TYPE
o - true output level)
• MK5098/981/982 - Class A or 2-of-7 (K/B common
floating or tied to V+)
MK50981 - Pulse output (active high, 1 - true output
level)
• MK5099 - 2-of-7 (K/B common tied to V-)
• Mute
• MK50991/992 - Class A or 2-of-7 (K/B common
floating or tied to V-)
M K5098/981 /982/99/992 - M ute output (active low, 0 true output level)
MEMORY RETENTION CURRENT
MK50991 - Mute output (active high, 1 - true output
level)
MK5098 - Does not have last-number redial: ISS :5 15
p.A at 2.5 V
• MK5099 - :5 20 p.A at 2.5 V
•
• MK50981 /982/991 /992 - 0.7 p.A typical and 2.5 p.A
maximum
OSCILLATOR
TYPICAL APPLICATION
• MK5098/982/99/992 - The mute and pulse outputs of
these pulse dialers have logic levels and timing
characteristics such that they are easily used in
applications requiring pulsing in series with the speech
network.
• MK5098/981 /982 - 480 kHz Ceramic Resonator (antiresonant mode) plus two 100 pF capacitors
• MK50981/991 - The mute and pulse outputs of these
pulse dialers have logic levels and timing characteristics
that make them more suitable for use in applications
requiring pulsing in parallel with the speech network.
The mute output of the MK50991 provides the logic
necessary for interface with a bistable latching relay to
mute the speech network.
• MK5099/991/992 - RC Oscillator consisting of 2
resistors and one capacitor
PIN-SELECTABLE OPTIONS
• Make/Break Ratio
MK5098/981/982 - Pin 9 tied to V+ = 39%/61 %
Pin 9 tied to V- = 33%/67%
V-27
V-2S
1982 TELECOMMUNICATION PRODUCTS DATA BOOK
MOSTEI(.
REPERTORY DIALER
MK5170
FEATURES
o Repertory of 10,24,50, or 100 20-digit call numbers
o
Repertory size determined automatically by the
amount of memory installed
XTL1--'" 1
XTL2--" 2
SA/MAO~
o
Speed dialing of the desired call number
o
Repertory easily updated by user
o
PIN CONNECTIONS
Figure 1
3
SB/MA 1 -+-- 4
SC/MA2-- 5
Each call number has an associated address code.
Display drive is provided to display the address code
and the 20-digit call number
SD/MA3'-- 6
35...--- Row 3
N/C-- 7
34..-.... Row4
DSO/MA8-- 8
33 ............ Coil
DS1/MA9- 9
32~C0i2
DS2/MA 10--10
o When a phone number is manually dialed, the digits
fviK5170
DS3iMA 11-+--11
will be displayed as they are entered
DS4/RIW _ _ 12
CE 1-+--13
o
o
o
Any number in the repertory can be displayed
The last number dialed is retained in an internal dial
buffer for redialing
Single-button dialing, with up to 32 numbers in two
16-number groups
o
Controls either a tone dialer or a pulse dialer
o
On-chip segment encoding
o
Will interface 2102 or MK41 04 static memory
o
Digital real-time, 12/24-hour, 50/60 Hz clock
o
1OO-hour timer
o
Two keyboard options
31~Co13
30..-......CcT4
29---.- MEM. DATA OUT
28 _ _ #0_#15
CE 2-+--14
27-+-- KBD. SCAN IN
#16_#31- 15
26-+--MEM.DATA IN
SP/MA7~16
25--...~
SG/MAS....-17
24-+--0N-HOOK
SF/MA5--18
23~~
SE/MA4 _ _ 19
22_BLANK DISPLAY
21--N/C
BLOCK DIAGRAM
Figure 2
50/60 H. '='=i~=i'==:::r---l
~~
XTl1
XTL2,--.,,_-'
Pi5C
o Operates on an inexpensive TV color-burst crystal
o
Single +5 volt
±
5% power supply
DESCRIPTION
Several different modes of operation are possible. For
minimal component count, the system of Figure 3 can
be used with the keyboard configuration shown in
Figure 4. This configuration is ideally suited to a 10number repertory system and places the function
control buttons on column 4 of a standard telephone
keypad. For systems with more features, the system of
Figure 5 can be used with the input matrix shown in
The MK5170 is a multi-function Repertory Dialer circuit
utilizing ion-implanted, N-channel silicon gate
technology and advanced circuit design techniques to
provide maximum cost-effectiveness and flexibility. Pin
connections are shown in Figure 1, and a block diagram
is shown in Figure 2.
VI-1
Figure 6. Note that the input matrix of Figure 6 permits
the use of a calculator-type l-of-N keyboard. The matrix
includes both push-buttons and diode-selectable
options. The options are selected by connecting a diode
between the appropriate digit strobe and the keyboard
scan input. Digit strobes are generated by an external
decoder which is driven by the MK5170 (See Figure 7).
Figure 8 provides two single-key dialing configurations.
Up to 32 individual dial entry keys (#0 - #31) are
possible.
BASIC REPERTORY DIALER SYSTEM
Figure 3
POWER
SUPPLY
H
BATTERIES
J 1
1
t•
•
2-0F-B
K
E
Y
B
0
A
R
D
B
U
F
F
E
R
S
~
MK5170
RAM
REPERTORY
DIALER
~
DIALER
PHONE LINE
BASIC SYSTEM KEYBOARD CONFIGURATION
Figure 4
ABC
DEF
1
2
3
GHI
JKL
MNO
4
5
6
PRS
TUV
WXY
INF.
7
8
9
PAUSE
#
CLEAR
C
C
OPER.
*
C
ENTER
--DIAL
STORE
0
C
o
o
o
o
L
L
L
L
1
2
3
4
VI-2
ROW 1
ROW2
ROW3
ROW4
FULL FEATURE REPERTORY DIALER SYSTEM
Figure 5
.~
.
SEGMENT
BUFFERS
MK5170
DISPLAY
REPERTORY
~
DIALER
DIGIT
BUFFERS
DIGIT
DECODE
-
t
,.
i
~
RAM
DIALER
KEYBOARD
t
PHONE LINE
~
,
POWER
SUPPLY
BATTERIES
FULL FEATURE KEYBOARD
Figure 6
D19
D18
D17
D16
D15
D14
D12 Dll
IN914
IN914 IN914
50/60 12/24
Hz
4049
KBD. SCAN IN
IMKS170. PIN 271
Hr.
10K
I
---------------------~
OPTIONS
D10
D9
D8
D7
D6
D5
D4
D3
D2
Dl
EACH
SWITCH,
DIGIT STROBE
r
NOTE. See Figure 7 for 01
-10-.
023.
VI-3
KBD. SCAN IN
DIGIT SELECT ENCODER
Figure 7
------------..--'''1
DSO/MA8 __
OS1/MA9>__-------------..,-t-"'1
DSZ/MA10>__-----------.--I-t-"'1
4028
O.
FROM
MK5170
,
OSJ/MA11
A
DO
'.
OS4/Ri'W
0,
BLANK
,
,
1~ C
4028
TO KEVBOARD
0"
AND DIGIT
DRIVERS
D"
0,
I5iSPLAY
0"
0"
0"
0"
D"
020
D"
D"
TWO CONFIGURATIONS FOR SINGLE-KEY DIALING
Figure 8
016
015
014
013
012
011
010
09
08
07
06
05
04
03
02
01
4049
I # 15 1 # 14 1 # 13 1 # 12 1 #11 I #10 I #9 I #8 I #7 I #61
#51 #4
I #3 I #2 I #1 I #0
I
#0-#15
(MK5 170. PIN 28)
lOOK
4049
I #31 I #30 1#29 1 # 28 1 # 27 1 # 26 1# 25 1 # 24 1 # 23 1 #221 ;'21 1 #20 I # 19 1 # 18 1 ;'
#16-#31
(MK5 170. PIN 15)
17 1 #16\
lOOK
'---'
016
015
014
013
012
011
010
09
08
07
06
05
04
03
02
01
-
'--
4049
NOTE: See Figure 7 for Dl . D16
:xl----t~
#16-#31
(MK5170. PIN 15)
SHIFT KEY
")c>---.....~;o::m
(MK 51 70. PIN 28)
lOOK
VI-4
Four types of functions are used to control the dialer: (1)
ENTER/DIAL allows entry and dialing of telephone
numbers, (2) STORE enables storage of entered
numbers, (3) CLEAR clears erroneous entries or begins
a data entry sequence and (4) PAUSE provides for intergroup pauses while dialing. Note that one of three
lengths of pause may be selected:
(a.) Infinite pause which is terminated either by
pressing the ENTER/DIAL button or by pressing one of
the #0 through #31 keys; (b.) Short pause (1.5 seconds)
which is terminated either by a 1.5-second time-out or
by the means described in (a.); and (c.) Long pause (5
seconds) which is terminated either by a 5-second
timeout or by the means described in (a.).
Two additional buttons are used to control the clock and
the timer. DISP. TIME causes the MK5170 to display the
current time. If this button is pressed and held for more
than 3 seconds, then the MK5170 will enter the settime
mode. During the 3-second timeout, the colons will stop
flashing. At the conclusion of the timeout, the colons
will resume flashing and the time can be set via the
number keys. SIS TIMER provides for displaying the
timer as well as starting and stopping it. If SIS TIMER is
pressed and the timer is not being displayed, the display
will change to show the timer count.lfthe timer is being
displayed when SIS TIMER is pressed, the timer will
start if it is not running and will stop if it is running.
An additional feature of the MK5170 is that, once a
minute, the current time is stored in external RAM. The
storage occurs on the minute transition. For example, as
the time changes from 1 :02 to 1 :03, 1 :02 will be stored.
If AC power is then lost between 1 :03:00 and 1 :03:59,
the clock will power up at 1 :02:00 when AC power is
restored. To further explain the operation of the
Mk5170, a few examples are given below:
3. If digits 1 through 20 are not blank, press the CLEAR
key. Enter the number to be dialed. As the digits are
entered, they will appear on the display beginning at
digit 20. If a pause is required, press the appropriate
pause key. The code corresponding to the key, as
shown in Figure 10, will appear on the display.
4. Press the STORE key. The telephone number shown
in digits 1 through 20 will be stored in the memory
location specified by the address code.
EXAMPLE 2: Dialing
ENTER/DIAL
a
Stored
Number
Using
1. Lift the receiver and press the ENTER/DIAL key.
Digits 21 and 22, the address code, will show only
decimal points.
2. Enter the address code. Entry will be as described in
Step 2 of Example 1. The dialing sequence will begin
when the number is recalled from memory.
3. If the call wasn't completed, hang up the receiver. To
redial the number, lift the receiver and press the
ENTER/DIAL key twice.
EXAMPLE 3: Storing
ENTER/DIAL
a
Dialed
Number
Using
EXAMPLE 1: Storing a Number to be Dialed Later
Using ENTER/DIAL
1. Lift the receiver and dial the number. As the keys are
pressed their corresponding code will appear on the
display. The address code will show only decimal
points. If the keyboard of Figure 4 is used, * and # can
be dialed. If a pause key is pressed, its code will
appear on the display but the pause will not occur. If
the number is redia led or stored and recalled from
memory, the pause will be executed when it is
encountered.
1. With the phone on-hook, press the ENTER/DIAL key.
Digits 21 and 22 (See Figure 9), the address code, will
show only decimal points. The remainder of the
display will show the contents of the dial buffer. Ifthe
dial buffer is empty, only decimal points will be
shown in digits 1 through 20.
2. Before going on-hook, press the ENTER/DIAL key
followed by the desired address code. Entrywill be as
described in Step 2 of Example 1. After digit 21 is
entered, press the STORE key. The telephone
number will be stored in the location specified by the
address code.
2. Enter the address code. As the address code is
entered it will be displayed in digits 21 and 22. If only
1 K of memory has been installed, the first digit will be
entered into digit 21 and digit 22 will be zero.
Otherwise, the first entry will be displayed in digit 22
and the second entry will be displayed in digit 21.
After a number has been entered in digit 21, the
memory contents referenced by the address code will
be shown on the display. If nothi ng has been stored in
the referenced location, only decimal points will
show in digits 1 through 20.
EXAMPLE 4: Storing a Number to be Dialed Later
using #0 - #31
1. With the phone on-hook, press the button (#0 - #31)
corresponding to the desired number. The address
code will be two digits corresponding to the pressed
button.
2. Proceed as described in Steps 3 and 4 of Example 1.
VI-5
EXAMPLE 5: Dialing a Stored Number Using #0 #31
DISPLAY ORGANIZATION
Figure 9
1. Lift the receiver and press the button (#0 - #31)
corresponding to the desired number. The address
code will be two digits corresponding to the pressed
button. As soon as the number is recalled from
memory, the dialing sequence will begin.
Digits 22 & 21
Digits 20 - 1 Digits 20 - 15 Digits 20 - 15 Digits 19 & 17 -
2. If the call was not completed, proceed as described in
Step 3 of Example 2.
Address Code (Rep Dialer Mode)
Dial Buffer Contents (Rep Dialer
Mode)
Real time - H.M.S. (Clock Mode)
Elapsed Time - H.M.S. (Timer Mode)
Decimal Points (Flashing in Clock
Mode; Fixed in Timer Mode)
EXAMPLE 6: Setting the Clock
CHARACTER FONT
Figure 10
1. Press the DISP. TIME button and hold for 3 seconds.
While the key is held, the colons will not flash. After
the 3-second timeout, the colons will resume
flashing.
0
5
I
6
5
Ei
2 2
3 3
4 Lf
7
l
0
1
2. Press the CLEAR key. The time will be reset to 1 a.m.
8 8
9 g
Blank
Asterisk
Pound
Long Pause
Short Pause
Infinite Pause
.
8
8
E3
E3
[3
FUNCTIONAL PIN DESCRIPTION
3. Enter the desired time via the number keys. Illegal
entries will be ignored. If an error is made, repeat step
2. Only the first 4 entries will be accepted.
4. After the correct data has been entered, press the
DISP. TIME key. Clock setting will then be disabled.
EXAMPLE 7: Displaying the Clock
Pin 1, XTL 1 and Pin 2, XTL2
These pins are the time-base inputs. With a crystal
connected between these pins, the MK5170 will
provide the RowlColumn timing shown in the AC
characteristics section. No other oscillator components
are required.
Pin 3, SA/MAO
1. Press the DISP. TIME button. The clock will be
displayed but cannot be set unless the sequence
shown in Example 6 is followed.
This output normally has segment A information forthe
display. During memory access, this output drives the
LSB of the memory address.
Pin 4, SB/MA1
2. If the CLOCK ENABLE diode has been installed (see
Figure 6}, the clock will automatically be displayed 10
seconds after dialing is completed.
This output normally has segment B information for the
display. During memory access, this output drives the
2nd LSB of the memory address.
EXAMPLE 8: Operating the Timer
Pin 5,SC/MA2
1. Whenever it is desired to display the timer, press the
SIS TIMER button.
This output normally has segment C information for the
display. During memory access, this outputdrives the
3rd LSB of the memory address.
2. If the timer is being displayed when the SIS TIMER
button is pressed, one of the following actions will
result: a. If the timer is running, it will stop
b. If the timer is stopped, it will start
Pin 6, SD/MA3
This output normally has segment D information for the
display. During memory access, this output drives the
4th LSB of the memory address.
3. If the timer is being displayed when the CLEAR
button is pressed, it will be cleared to 00.00.00.
Pin 7, N/C
This pin has no user-accessible function but it should
not be used as a tie point.
VI-6
Pin 8, DSO/MA8
Pin 18, SF/MAS
This output normally has the LSB of the digit select
code. During memory access, this output drives the 4th
MSB of the memory address.
This output normally has segment F information for the
display. During memory access, this output drives the
6th LSB of the memory address.
Pin 19, SE/MA4
Pin 9, DS1 /MA9
This output normally has the 2nd LSB of the digit select
code. During memory access, this output drives the 3rd
MSB of the memory address.
This output normally has segment E information for the
display. During memory access, this output drives the
5th LSB of the memory address.
Pin 20, GND
Pin 10, DS2IMA10
This pin is logic and circuit ground.
This output normally has the 3rd LSB of the digit select
code. During memory access, this output drives the 2nd
MSB of the memory address.
Pin 21,N/C
This pin has no user-accessible function but it should
not be used as a tie point.
Pin 11, DS3/MA11
Pin 22, Blank Display
This output normally has the 2nd MSB of the digit select
code. During memory access, this output drives the
MSB of the memory address.
This signal goes low to blank the display by inhibiting an
external digit select decoder.
Pin 12, DS4/R/W
Pin 23, Dialing
This output normally has the MSD of the digit select
code. During memory access, this output drives the
memory read/write line. A low on this pin enables the
write mode; a high allows the memory to be read.
This output goes low during a dialing cycle and is used to
disable the 2-of-8 keyboard.
Pin 24, On-Hook
Pin 14, CE2
If this pin is pulled low, the telephone is on-hook and the
ENTER/DIAL key functions as an ENTER key. If this
input goes low during dialing, dialing is terminated and
the dialer resorts to its normal scanning routine. If this
pin is high, the telephone is off-hook and dialing can
occur.
This output enables the most significant memory chip.
Pin 25, Inh. Dial
Pin 15, #16 - #31
This pin goes low during data entry to inhibit the
MK5090 or MK5098 and prevent tones or pulses from
being generated.
Pin 13, CE1
This output enables the least significant memory chip.
This input is used to interrogate single-key
ENTER/DIAL keys 16 through 31. As shown in Figure 8,
these keys are tied to digit strobes 1 through 16,
respectively.
Pin 16, SP/MA7
This output normally has segment P (decimal point)
information for the display. During memory access, the
output drives the 5th MSB of the memory address.
Pin 26, MEM. DATA IN
The dialer uses this pin to read data from the external
memory.
Pin 27, KBD. SCAN IN
This is the input for the function keys, options and
number keys. The use of the options is described below:
Pin 17, SG/MA6
50/60 Hz (023) (See Figure 6)
This output normally has segment G information forthe
display. During memory access, this output drives the
6th MSB of the memory address.
If a diode is not installed, the MK5170 will require
a 60 Hz timebase for the clock and timer. Installing
a diode indicates that a 50Hz timebase is to be
used.
VI-7
12124 HR (022) (See Figure 6)
Pin 29, MEM. DATA OUT
If a diode is not installed, the MK5170 will display
the clock in 12-hrformat. Installing a diode will
cause the clock to be displayed in 24-hr format
with leading zeroes.
This output is used to transmit data to the external
memory.
Enable Clock (021) (See Figure 6)
These pins are used to interrogate the keyboard
columns and to drive the column inputs of the MK5090
tone dialer or MK5098 pulse dialer.
10 seconds after the MK5170 completes a dialing
cycle, one of two actions will occur: (1) If the
Enable Clock diode is installed, the MK5170 will
display the clock or (2) If the diode is not installed,
the display will be blanked. Pressing any key will
unblank the display.
Pin 30 through Pin 33, COL 4 through COL 1
Pin 34 through Pin 37, ROW 4 through ROW 1
These pins are used to interrogate the keyboard rows
and to drive the row inputs ofthe MK5090 tone dialeror
MK5098 pulse dialer.
The use of the remaining keys is described in Table
1. State Control Sequence for the MK5170
Repertory Dialer.
Pin 38, 50/60 Hz
This input provides the time base for the real time clock.
Pin 39, POC
Pin 28, #0 - #15
This input is used to interrogate single-key
ENTER/DIAL keys 0 through 15. As shown in Figure 8,
these keys are tied to digit strobes 1 through 16,
respectively.
This input can be used to force a power-on-clear.
Pin 40, Vee
+5V, ± 5%
STATE CONTROL SEQUENCE FOR THE MK5170 REPERTORY DIALER
Table 1
STATE
LAST FUNCTION
ENTERED
PRESENT
FUNCTION
RESULTS
Power Up
None
None
Display all decimal points; digits blanked
None
Disp. Time
Display clock. Will show 1.00.00 if memory power
has failed or if this is the first application of power.
Otherwise, it will show the time at which AC power
was lost.
None
SIS Timer
Display timer. 00.00.00. Timer not running
None
E/D
Display phone number. Display will not change.
None
Digits, *, #,
Long/Short/lnf.
Pause
Display the symbol for each digit or function as it is
is entered. Any entries above 20 digits are ignored.
None
Clear
No change
None
Store
No Change
None
#0 - #31
Show the number stored in the corresponding
memory location. If nothing has been stored, display
all decimal points with digits blanked, except for
address code. If off-hook, dial the number.
VI-8
Table 1 Continued
STATE
LAST FUNCTION
ENTERED
PRESENT
FUNCTION
Display Clock
Disp. Time
Disp. Time
No change. Colons will not flash while Disp. Time
switch is held. If switch is held for more than three
seconds, the colons will start flashing and the
MK5170 will enter the set clock state.
SIS Timer
Display timer. Colons not flashing.
E/D
Blank address code, display phone number.
RESULTS
Long/Short/lnf.
No change
Pause, Clear, Store
Display Timer
Manual Entry
Display
Phone Number
SIS Timer
Digits, *, #
E/D
#0 - #31
Show the number stored in the corresponding
memory location. If off-hook, dial the number:
Digits, *, #
Display the digit or function when it is entered. Start
manual entry sequence.
SIS Timer
If timer was running, stop. If timer was not running,
start.
Clear
Clear timer.
Disp. Time
Display clock.
Long/Short/lnf.
Pause, Store
No change
Digits, #, *
Display the digit or function when it is entered. Start
manual entry sequence.
E/D
Blank address code, display phone number
#0 - #31
Show the number stored in the corresponding
memory location. If off-hook, dial the number.
Digits, #, *
Long/Short/lnf.
Pause
Display the symbol for each digit or function as it is
entered. Entries above 20 digits are ignored.
Clear
Clear the display
Disp. Time
Display clock
Store, E/D
No change
#0 - #31
Display the number stored in the corresponding
memory location. If off-hook, dial the number
None
Blank address code, display phone number.
II
Table 1 Continued
STATE
LAST FUNCTION
ENTERED
RESULTS
Digit
Enter digit into address code. If 1 K of memory is
installed, enter digit into LSD and recall phone
number from memory. If off-hook, dial the number.
SIS Timer
Display timer
Disp. Time
Display clock
Store, Long/
Short/lnf.
Pause, *, #
No change
Clear
Clear display
#0 - #31
Display the number stored in the corresponding
memory location. If off-hook, dial the number.
Digit
If second digit and more than 1 K of memory is
installed, store digit in LSD of address code and recall phone number from memory. If off-hook, dial
number. If second digit and 1 K of memory is
installed,store digit in MSD of phone number. If not
second digit, store in next location in phone no.
*,
#, Long/Short/
Inf. Pause
If second digit and more than 1 K of memory is
installed, ignore. If not second digit, store in next
location in phone number.
Clear
If address code is incomplete, clear address code
and phone number. If address code is complete,
clear only the phone number.
Store
If address code is complete, store the phone
number. Otherwise, ignore.
#0 - #31
Display the number stored in the corresponding
memory location. If off-hook, dial the number.
E/D
E/D
Dial the number in the dial buffer (redial).
Digit
SIS Timer
Display timer
Disp. Time
Display clock
Digit
Legal digit will be entered into next location.
Illegal digit will· be ignored.
Clear
Set time to 1.00.00 a.m.
Display
Phone Number
Continued
Digit
Set Clock
PRESENT
FUNCTION
Disp. Time for
greater than 3
seconds
VI-10
Table 1 Continued
STATE
LAST FUNCTION
ENTERED
Set Clock
Continued
PRESENT
FUNCTION
RESULTS
Store, *, #, Long/
Short/lnf. Pause
No change
#0 - #31
Display the number stored in the corresponding
memory location. If off-hook, dial the number.
E/D
Display phone number
SIS Timer
Display timer
Disp. Time
Display clock, leave set clock mode.
APPLICATION INFORMATION
The Basic Repertory Dialer System of Figure 3
represents the minimum number of components
required to implement a repertory dialer system using
MK5170. A 2-of-S keyboard, using the interface shown
in Figure 11, provides the system control functions of
number entry, Enter/Dial, Store, Inf. Pause and Clear. A
quad comparator, an LM2901 or equivalent, is used as a
buffer between the keyboard and the MK5170. The noninverting input of each comparator is biased at Y2 +5M
and the appropriate non-inverting inputs are tied to
their assigned row orcolumn. A key closure will pull two
of the non-inverting inputs within two diode drops of
ground, thus causing the associated comparator
outputs to go low. The MK5170 then senses these two
low levels and, after identifying the key, drives the
DIALING output low, which pulls the inverting inputs
within one diode drop of ground and causes all of the
comparator output transistors to turn off, thus isolating
the keyboard from the MK5170 so that the MK5170 can
apply row and column information to the dialer without
interference from the keyboard.
The dialer interfaces shown in Figure 12 and Figure 13
include level conversion circuitry as well as an Inhibit
Dial feature. The active - low row and column signals
(ROW 1 - COL 3) are applied to the bases of NPN
transistors. Because the power supply to the tone dialer
can vary between 3.4 volts and 10.5 volts and the power
supply to the pulse dialer can vary between 2.5 and 5
volts, level conversion is required between the 0 - to 5 volt row and column signals and the corresponding
inputs to the MK5090 or MK509S. This required level
conversion is provided by the 7 NPN transistors. When
the MK5170 is required to isolate the dialer from the 2of-S keyboard (i.e. during data entry), it does so by
driving the INH. DIAL line low. The INH. DIAL signal is
inverted and used to turn all of the NPN transistors on so
that the signals applied to the row and column inputs of
the MK5090 and MK509S will be at their inactive level.
When the MK5170 starts a dialing cycle, the INH. DIAL
line will go high and the required sequence of row and
column signals will be applied to the bases of the NPN
level converters. The 4050 buffers and 4049 inverting
buffers shown in the dialer interface schematics are
powered from the phone line and provide the buffering
and logic inversion necessary to meet the input
requirements of the MK5090 and MK509S, as well as
permitting the use of 1 megohm pull up resistors at the
collectors of the NPN level converters. Using large value pullup resistors reduces the amount of current
that the buffer circuitry draws from the phone line.
The Full-Feature Repertory Dialer System of Figure 5
implements all the features provided by the MK5170 by
placing all of the keys and option diodes in a 3 x 24
matrix shown in Figure 6 and Figure S. KBD. SCAN IN,
#0 - #15 and #16 - #31 are scanned by the MK5170.
When an active low level is detected on any of the three
scan lines, the MK5170 determines which key has been
pressed and takes appropriate action. Digit strobes for
scanning the input matrix are generated by the circuit
shown in Figure 7, which encodes the 5-bit digit select
code (DSO - DS4) into lof 23 digit strobes (D1 - D23).
These positive pulses are then used to drive the bipolar
digit drivers for the display as well as for scanning the
input matrix. A BLANK DISPLAY input is provided to
inhibit the generation of digit strobes during memory
access, since the segment and digit encoding lines are
shared by memory addresses and read/write control
(See Figure 7).
The Power Supply and Timebase Reference circuit
shown in Figure 14 provides two independent 5-volt
power supplies: (1) +5L which powers the MK5170 and
the display circuitry and (2) +5M which powers the
memory, the memory protect logic and the keyboard
buffers and is provided with a battery backup which
consists of 6 NiCd cells and a charging circuit. The
VI-11
Timebase Reference consists of a comparator with
hysteresis so that power line noise will not reach the
MK5170.
The Memory Protect Logic shown in Figure 15 provides
two functions: (1) The MK5170 will be reset whenever
its power supply dips to 4.75V and (2) on power up and
during a power supply dip to 4.75V, CEl and CE2 will be
forced high so that no memory chip selects can be
generated. This insures that data stored in the MK41 04
will not be destroyed. If a 2102 memory is used, the
memory protect latch is not required. Note, however,
that CEl and CE2 must still be inverted to enable the
memory. CEl and CE2 will be enabled after POC is
removed from the MK5170 and CEl goes high.
Repertory size' is determined automatically by the
amount of memory installed so all that is required to
alter the size of the repertory is to install memory
devices as shown in Figure 16.
Figure 17 shows the suggested LED drive circuitry,
A special "on-hook" circuit, Figure 18, is shown for use
with PBX systems, This circuit prevents the MK5170
from seeing the momentary line-disconnect exhibited
by a PBX system as it switches to out-of-plant lines,
2 OF 8 KEYBOARD TERMINAL
Figure 11
lOOK
(8X)
10K(8X)
COM
--
IN914
(2)()
1,
2
3
ENTER
4
5
6
STORE
7
8
9
INF.
PAUSE
0
""
CLEAR
.
1
i.5IAl
1
hl
1
'i7
ROW 1
(M K5170.
PIN 37)
ROW 2
(M K5170.
PIN 36)
ROW3
(M K5170.
PIN 35)
ROW4
I
( MK5170,
PIN 34)
~
~
COL 1
1M K5170
PIN33)
COL 2
( MK5170.
PIN 32)
COL 3
(MK5170.
PIN 31)
10K
+5M __----~~------_.
DIALING
(MK5170. PIN 23)
IN914
....
A
'
10K
NOTE: Comparator Powered From +SM
VI-12
COL 4
(MK5170.
PIN 30)
·ALSO DRIVES
DIALER INTERFACE
(SEE FIGURE 1 2 & 13)
TONE DIALER INTERFACE
Figure 12
PHONE
LINE
HOOK
r¢:~o,;U:~X1
_
+
15V
PHlIN+
.1
SWITCH
~~
.005 J.lF
100V
(lN3046
fA
(1 N4744
OR EQUIV)
)~
T
10V
(1 N758
OR EQUIV)
)r'VI~-"
INH DIAL
(MK5170.
PIN 25)
10K
+5M
1
6
V+
V-
1M
17XI
4049 (4X)
14
ROW 1· 100KI14XI
IMK5170. PIN 371
r
13
ROiiV1
ROW2
ROW 2
IMK5170. PIN 361
ROW 3
IMK5170. PIN 35)
T ~
12
1~
11
ROW3
MK5090
ROW4
ROW4
~
IMK5170. PIN 341
COL1
IMK5170. PIN 33)
COL 2
IMK5170. PIN 32)
COL 3
IMK5170. PIN 311
T ~
4050 (3X)
3
1~
4
1 '-.
5
h
~- D)
1 ......- -
*-
'"-"
I
I
-
1
-
-
-,
-- c
I
I
I
L :'"'" N"I"
1
I
B)
~
--lR' wee
of!
RCVRLr"""
----
300
K
--=COL3
2 -CHIP
DISABLE
7
16
OSC. TONE
IN
OUT
270
3~~
MHz
-H
1
2N3906
COL2
2N3904":.=
17XI
VN46AF
MUTE
10
COL 1
ro-
-
-
I
I
....J
,~
OSC.
OUT
Q
1
3.3K
300K
-::~
-
XMTR
NOTE: 4049 and 4050 Buffers are Powered From PHlIN+
VI-13
III
PULSE DIALER INTERFACE
Figure 13
PHONE
LINE
1
6
1M
(7X)
v+
v(IN751
OR EQUIV)
-:::-
+5M
100K(14X)
ROW 1 '
ROW 1
(MK5170, PIN 37)
lOOK
ROW 2
(MK5170, PIN 36)
2N
5401
ROW3
(MK5170, PIN 35)
300K 3K
ROW4
ROW4
MK5098
(MK5170, PIN 34)
16
3 COL 1
PULSE
COL 1
(MK5170, PIN 33)
=
COL2
(MK5170, PIN 32)
COL 3
7
(MK5170, PIN 31)
2N3904
(7X)
-=-
100pF
I
455
kHz
CJ
OSC. IN
_ _ 10
MUTE
I
I
I
I
2500. '----~....
I TYPE NETWORK
RCVR
R
L __
NOTE: 4049 and 4050 Buffers are Powered From PHLlN+
VI-14
POWER SUPPLY AND TIMEBASE REFERENCE
Figure 14
IN4001
,----.--DI--r----.-----j IN
117VoII
I
+
12
VAC
AC LINE
1000,'
DUTj---.-----;.. +5L
5V REG.
lM340K
lOR EaUIVf
IN4UUl
COM
IN914
.---~--lJN
QUTj---.-----;.. +5M
200n
'I2W
120K
50/60 Hz
IMK5170. PIN 38}
30K
+5L'--~~~--~----~
15 M
620K
1M
NOTE: COMPARATOR POWERED FROM +5M
MEMORY PROTECT LOGIC
Figure 15
+5l
10K
+5M
5170 GND (MK5170, PIN 20)
12K
lK
2.38V
>--t-.... PiiC
2.5V
10K
* GEl
10K
& eE2 must be inverted to enable memory.
NOTE: ALL ACTIVE DEVICES POWERED FROM +SM
VI-15
(MK5170, PIN 39)
MEMORY CONNECTIONS TO MK5170
Figure 16
b. 24· NUMBER REPERTORY
2102
a. 12· NUMBER REPERTORY
2102
10
'5M
DS3/MA11
-f.l4£
CIT
SA/MAO
SB/MAl
SC/MA2
SO/MA3
SE/MA4
10K
-=-13
8
4
5
6
SP/MA7
DSO/MAB
DS1/MA9
DS4/R;W
MEM. DATA OUT
DOIJT
~
IT
1
:
SA/MAO
se/MAl
SC/MA2
SD/MA3
SE/MA4
SF/MAS
SG/MA6
SP/MA7
aSO/MAS
DS1/MA9
DS4/R{W
~~
16 A7
~:
AS
3 A9_
11
10
.5M
DS3/MA11
m*
AO
A1
A2
A3
7A4
SF/MAS
SG/MA6
Vee
vss
~~~
~~1 N914
10K
---.. ON-HOOK
PHLlN+
(See Fig. 12113)
IN914(2X)
(OR EQUIV)
(MK5170. PIN 24)
NOTE: Comparator is powered from +5M
VI-17
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS*
Temperature under bias ...................................................................... O°C to 70 DC
Storage temperature ...................................................................... -65°C to 150°C
Voltage on any pin with respect to ground .................................................... -1.0V to +7V
Power dissipation ................................................................................... 1 .OW
*Stresses above those listed under "Absolute Maximum Ratings" maycause permanent damage lethe device. This isa stress rating only and function operation afthe
device at these or any other condition above these indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating
conditions' for extended periods may affect device reliability.
DC CHARACTERISTICS
TA = ODC to 70°C. Vcc= 5V
± 5%
SYMBOL
PARAMETER
Icc
Power Supply Current
PIl
Power Dissipation
V IH
Input High Level
VIL
Input Low Level
hll
MIN
TYP
MAX
UNIT
TEST CONDITIONS
55
77
mA
Output Open
275
385
mW
Outputs Open
2.0
5.8
V
-0.3
0.8
V
Input High Current
100
J.l.A
VIII=2.4V
Internal Pull-Up
hL
Input Low Current
-1.6
mA
V II.=O.4V
IOH
Output High Current
-100
J.l.A
V(lH=2.4V
101.
Output Low Current
1.8
mA
V Ol.=O.4V
RIP
Internal Pull-up Resistor
k!1
Output transistor off
AC CHARACTERISTICS
TA = O°C to 70°C. Vcc = 5V
SIGNAL
6
± 5%
SYMBOL
PARAMETER
MIN
to(XTL)
Time base period.
Crystal mode
250
MAX
UNIT
279
ns
ns
558
ns
COMMENTS
4MHz crystal
3.58 MHz crystal
0
to
Internal 0 clock period
500
POC
tRfI
POC hold time. Low
3.75
4.10
J.l.s
J.l.S
4MHz crystal
3.58MHz crystal
50/60Hz
tEll
50/60Hz hold time.
High
3.75
4.10
J.l.S
J.l.S
4MHz crystal
3.58MHz crystal
Row/Col
tRC
Row/Column output
duration & off time
68
ms
ms
4MHz crystal
3.58MHz crystal
tACC
Memory Access Time
10
tllP
Digit Period
10.8
ms
3.58MHz crystal
tlloN
Digit On Time
490
J.l.S
3.58MHz crystal
D.C.
Display Duty Cycle
3.2
%
76
3.2
J.l.s
CAPACITANCE
T A = 25°C. fXTL = 4MHz
SYMBOL
PARAMETER
CIN
Input capacitance.
all pins except XTL 1.
XTL2
CXTL
Input capacitance.
XTL1.XTL2
MIN
18
VI-18
MAX
UNIT
TEST CONDITIONS
7
pF
Unmeasured pins
returned to ground
23
pF
MOSTEI(.
TELECOMMUNICATIONS
Ten-Number Repertory Dialer
MK5175(N)
FEATURES
o
Silicon Gate CMOS process for low-voltage (2.0 V to
10.0 V) and low-power operation
o
Stores ten 16-digit telephone numbers
o
Line operation off-hook, battery operation on-hook
PIN CONNECTIONS
Figure 1
v+-
o
MODE _
Stand-alone Pulse dialer
o Interfaces with Mostek's Tone generators
1
16 _
PULSE/13-KEY"
2
15 _
HKS
COL1_ 3
1 4 _ ROW 1
COi:2 - -
13 _
4
COL3 - - 5
v- - 6
o PABX pause key input
o
Last-number-dialed memory
o Last number dialed may be transferred to anyone of nine
ROW2
12 _
ROW3
11 -
ROW4
OSC/RC" -
7
10 -
MUTE/DO"
OSC/NC' -
8
9 -
M-B/CNTL"
'Dual pin designations correspond to the pUlse/tone modes, respectively
other locations
o Make/break ratio is pin-selectable in the Pulse mode
o Uses either the inexpensive Form A-type keyboard or the
standard 2-of-7 matrix keyboard with common V- (Tone
mode may use SPST switch control key in 13-key mode
to avoid redundancies in key entries)
DESCRIPTION
The MK5175 is a monolithic integrated ten-number
repertory dialer manufactured using Mostek's Silicon Gate
CMOS process. The circuit accepts keyboard inputs and
provides the Pulse and Mute logic levels required for loopdisconnect signaling. For DTMF signaling, the MK5175
may be interfaced with one of Mostek's new Tone
generators with minimum additional circuitry.
The dialer will function in either Tone or Pulse mode,
dependent upon the logic level presented to Pin 2, the
"Mode Select" pin. The interpretation of several inputs and
outputs is dependent upon the mode selected.
An on-chip RAM is capable of storing ten sixteen-digit
telephone numbers including the last number dialed, When
used in a PABX system, a pause(# key) may be stored inthe
number sequence. The repertory dialer will recognize this
pause when automatically dialing and stop until any key
input is received.
The MK5175 repertory dialer uses a standardized pinout
scheme common to all MostekTone and Pulse dialers, This
will facilitate the design of a family of telephone products
using common PC boards and circuit components.
FUNCTIONAL DESCRIPTION
V+, Pin 1
Pin 1 is the positive supply inputto the part and is measured
relative to V- (Pin 6), The voltage on this pin should not
exceed 10 volts. On-chip zener diodes will provide
protection from supply transients in most applications,
MODE, Pin 2
In Pulse mode, the time base for the circuit is a ceramic
resonator which is low-cost, yet provides an accurate
reference. In Tone mode, a single-pin RC oscillator provides
the frequency reference for the circuit. This provides the
least expensive means to adequately control the tone
output rate. The block diagram in Figure 2 illustrates the
general internal structure of the MK5175.
The MK5175 will function in either Tone or Pulse mode,
dependent upon the logic level presented to Pin 2, For Pulse
mode operation, this pin must betied to V-(Pin 6), ForTone
mode, it should be tied to V+ (Pin 1 ), The interpretation of
Pins 7, 8, 9, 10, and 16 are dependent upon the mode
selected.
VI-19
MK5175 BLOCK DIAGRAM
Figure 2
V+
1T
j
~~
COL 2 ~.
COL1
COL3
~.
ROW1 ~'-'
ROW2 ~ ,.)
ROW3 ~.
lJ.
w
.
DATA
LATCH
U
«
"II:
f----
w
!i;U
-113
Oo
11:-'
«
0
~
III
>w
DEBOUNCE
COUNTER
'"
ROW4 -.!.!.
M-B/CNTL
I
.J.j.
ADDRESS
LATCH
I
9
PU
16 13 -
~
STATIC
CMOS
RAM
r-
r----'
PULSE
CONTROL
LOGIC
10
MU
DO
t
CONTROL
LOGIC
I
I
L
j
DIGIT
COUNTERS
I
t
OSCIRC
7
DIVIDER
OSCILLATOR
f------
TIME
COUNTER
-
POWER
ON
RESET
L
8
2
15
61
OSCINC
MODE
HKS
V-
KEYBOARD INPUTS, Pins 3,4,5, 11, 12; 13, 14
closure. This does not affect the normal functioning .of the
tone generator, which begins signaling immediately.
The MK5175 incorporates an innovative keyboard scheme
that allows either the standard 2-of-7 keyboard with
negative common or the inexpensive single-contact (Form
A) keyboard to be used, as shown in Figure 3.
A valid key entry is defined by either a single row being
connected to a single column or V- being simultaneously
presented to both a single row and column.
In the Tone mode, the MK5175 features a bidirectional
keyboard scheme. In this scheme, the MK5175 simulates
key closures so that a tone dialer will perform the repertory
tone-dialing function. As the MK5175 passively monitors
the key inputs, they are debounced, decoded, and stored in
the on-chip LND (Last Number Dialed) buffer. The repertory
dialer will disable the tone generator and scan the keyboard
whenever a command key entry is detected, as shown in
Figure 4.
In the Pulse mode, the MK5175 keyboard inputs are totally
static until an initial valid key input is sensed. The oscillator
is then enabled and the rows and columns are alternately
scanned (pulled high, then low) to verify the input is valid.
Keyboard bounce is ignored for 32 ms after the initial key
down is detected. A key input is accepted if it is valid after
this initial debounce time. This scheme allows any valid key
input to be recognized in less than 40 ms after the initial key
V-,Pin 6
·Pin 6 is the power supply return pin and is the
measurement reference for V+ (Pin 1 ).
OSCILLATOR, Pins 7,8
Inthe Tone mode, onlya resistor and a capacitor are needed
to provide the frequency reference for the MK5175. The
resistor should be connected from Pin 7 (OSC/RC) to V+
(Pin 1) and the capacitor from Pin 7 to V- (Pin 6). Pin 8
(OSC/NC) should be connectedtoV+. Anominal frequency
of 8 kHz will provide a tone rate of 100 ms on and 100 ms
off. This tone rate is directly proportional to the oscillator
frequency.
In the Pulse mode, an accurate frequency reference is
obtained using an on-chip inverter with sufficient gain to
provide oscillation when used with a low-cost 480 kHz
ceramic resonator (anti resonant mode). In addition to the
resonator, two external capacitors are required, as shown in
Figure 6.
M-B/CNTL, Pin 9
In the 13-key Tone mode, Pin 9 can be used'as a Control
VI-20
input by connecting a coritrol k~y (n.o. SPST switch) from
this pin to V- (Pin 6). This feature allows the * and # key
entries to be interpreted simpiy as DTMF signals. When not
used as a key input, this pin should be connected to V+
(Pin 1). (See 13-Key Tone Mode)
In the Pulse mode, the make/break ratio may be selected by
connecting this pin to either the V+ or V- supply. Table 1
indicates the two popular ratios from which the user can
choose.
KEYBOARD GONFIGURATI.ONS
Figure 3
PULSE/13-KEY. Pin 16
In the Tone mode, a V+ level at Pin 16setsthe MK5175 in a
mode in which a control key (n.o. SPST) connected from Pin
9 to V- is used to initiate control functions. With Pin 16 tied
to V-, the MK5175 is set in the 12-key mode and the * and #
keys are used in control functions.
In the Pulse mode, Pin 16 is the Pulse output. It consists of
an open-drain N-channel transistor designed to drive an
external transistor. These transistors could typically be used
to pulse the telephone line by controlling the loop current
through the network: The timing characteristics of the Pulse
output are shown in Figure 5.
OPERATION
Cr
FORM A TYPE KEYBOARD
2-0F-7 MATRIX KEYBOARD
NEGATIVE COMMON
.
coe
%6M~6?{~
/////
COL
v_/////
STORAGE
L--ROW
2-0F-7 MATRIX KEYBOARD
ELECTRONIC INPUT
MAKE/BREAK RATIO SELECTION
Table 1
Input to Make/Break Pin
V+ (Pin 1)
V-(Pin 6)
During normal dialing, each digit is stored in the LND (Last
Number Dialed) buffer, location O. The telephone number
dialed can be left in this temporary LND buffer for later use
or it can be copied into any of the other nine permanent
memory locations.
Pulse Output
MAKE
40%
32%
BREAK
60%
68%
Pin 10 is the output of an open-drain N-channel transistor.
In the Tone mode, Pin 10 is used to provide the tone dialer
with a Dialer-Disable signal. This signal is used to inhibitthe
generation oftones by pulling to V- when command entries
are being made.
In the Pulse mode, Pin 10 is the Mute output. It provides the
logic necessary to mute the receiver while the telephone
line is being pulsed. A typical method of interfacing this
output is shown in the application diagram in Figure 6.
Figure 5 shows the timing characteristics of the Mute
output.
HKS. Pin 15
Pin 15 is the hook switch input pin. Pin 15 requires an
external pull-up resistor to the positive supply. A V+ input
sets the circuit in its on-hook mode, while a V- input sets it
in the off-hook or dialing mode.
Telephone numbers to be automatically dialed by the
MK5175 may be entered into the LND buffer while either
on-hook or off-hook. However, the MK5175 must be in the
on-hook mode for a number to be copied into a permanent
memory location. A number may be copied and stored by .
entering the key sequence ~ EJ, followed by the address
(1-9) of the memory location in which the number is to be
stored. This operation requires 400 ms before going offhook or reinitiating the store function. Information present
inthe LND buffer when new data is entered is replaced and
cannot be recalled.
AUTOMATIC DIALING
The automatic dialing function is implemented by going
off-hook and entering a *, followed by the address (1-9) of
the desired telephone number. Dialing will begin with the
release of the address key and can be interrupted by
initiating a new redial command. The LND buffer will
contain the information last entered. A key sequence ofG,
!QJwill cause the last number entered to be redialed. More
than one number sequence may be automatically dialed
from memory without returning on-hook.
PAUSE/CONTINUE COMMAND
The MK5175 has a feature which allows an . indefinite
pauseto be programmed into the first 15 digitsofa number
sequence by entering a # key at the point in the sequence
where a pause is desired. When the number is
automatically dialed, the circuit will stop dialing when the
pause is encountered. Any key entry after the interdigital
pause (except * key) will cause the MK5175 to contiriue
dialing the remainder of the number. If more than one
pause was originally programmed into the number
VI-21
sequence, a corresponding number of continue commands
must be made in order for the number to be completely
dialed.
NORMAL DIALING
When dialing normally in the Pulse mode, the key entry rate
may exceed the dialing rate. The memory has a FIFO (firstin-first-out) architecture and any length number sequence
may be dialed as long as the key entered is not more than 16
entries ahead of the digit being outpulsed.
In order to dial a * or # DTMF signal when intheTonemode,
the * or # key must be depressed twice consecutively.1This
will cause the MK5175 to enable the tone dialer to generate
the corresponding tone. However, the MK5175 will not
store a * or # as a DTMF signaling digit.
Examples:
1. On-Hook, enter 323-6000
Then enter
323-6000 is stored in location 5
BB[§]
All digit entries, except * and #,are stored in the LND buffer
as they are entered, whether off-hook or on-hook. However,
the MK5175 must be in the on-hook mode for a number to
be copied from the LND buffer into a permanent memory
location. A number may be copied and stored into a
permanent memory location by entering the key sequence
[CJ~(where C is the control key and N is the location, 1-9, in
which the number is to be stored). An indefinite pause may
be programmed into a number by entering a [9 [][] key
sequence at the point desired.
In order to automatically. dial a number in memory, the key·
sequence [Q~ must be entered after going off-hook, where
N is the address of the number to be dialed. Last-number
redial is accomplished by dialing 191Qj. If a pause has been
programmed into the number to be automatically dialed, the
number will be dialed up to the point where a pause is
encountered. Any key entry will cause the MK5175 to
continue dialing theremainder of the number. If more than
one pause was programmed into the number, a
cor~esponding number of continue commands must be
made in order for the number to be completely redialed.
•
•
•
Examples:
Come off-hook
Enter [:J[§J
323-6000 is automatically dialed
1. On-hook, enter 555-2525
Enter
(C is a control key)
555-2525 is stored in location 5
(9ffil
•
2. Off-Hook, dial 42 (PBX access code)
While waiting for dial tone, enter #
Dial 1-214-323-6000
Busy/Hang up
EnterBB@]
(Number is stored in location 3)
•
•
Come off-hook
Enter
555-2525 is automatically dialed
(9ffil
•
•
2. Off-hook, dial 9 (PBX access code)
Enter
(a pause is programmed in, with no tones
emitted)
Once dial tone is established
Dial 1-214-323-6000
Busy/Hang up
Enter [91I1
(Number is stored in location 2)
[gOO
•
Come off-hook
Enter!3ll1
42 is dialed
Wait for dial tone
Enter 3 (continue command)
1-214-323-6000 is dialed
•
13-KEY TONE MODE
An extra feature available on the MK5175 is the ability to
use the entire keyboard for normal signaling such that
when any key is depressed once, including * and #, the
proper DTMF signal is generated. This feature is activated
by connecting Pin 16 to V+. In order to utilize this function,
an extra control key (n.o. SPST) connected from Pin 9
(M-B/CNTL) to V- is required.
'True only for 12-Key Tone Mode
VI-22
•
•
Come off-hook
Enter ~J[ZJ
9 is dialed
Establish dial tone
Enter 2 (continue command)
1-214-323-6000 is dialed
ABSOLUTE MAXIMUM RATINGS*
DC Supply Voltage, V+ ........................................................................... 10.5 Volts
Operating Temperature ...................................................................... -30°C to +60°C
Storage Temperature ........................................................................ -55°C to +85°C
Maximum Power Dissipation (25°C) ................................................................. 500 mW
Maximum Voltage on any Pin ........................................................ (V+) +0.3; (V-) -0.3 Volts
"'Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage tathe device. This is a stress rating only and functional operation of the device at
these or any other condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may
affect device reliability.
POWER DISSIPATION DERATING CURVE
60+----_
T .. 40
SAFE OPERATING
RANGE
(OC)20
O;----r--~--~--~--_+--
600
100
200
300
400
DERATE AT 9 mW/oC
WHEN SOLDERED INTO
PC BOARD.
o
mW
ELECTRICAL CHARACTERISTICS
DC CHARACTERISTICS
-30°C :s TA :s 60°C
SYM
PARAMETER
V+
DC Supply Voltage
IMR
Memory Retention Current
lop
MAX
UNITS
10.0
V
0.5
2.0
p.A
1
DC Operating Current (Tone Mode)
50
100
p.A
2
lop
DC Operating Current (Pulse Mode)
100
200
p.A
2
IML
Mute Sink Current
V+ = 2.0 V, Vo = 0.5 V
0.5
2.0
mA
Pulse Sink Current:
V+ = 2.0 V, Vo = 0.5 V
1.0
4.0
mA
Ip
ILKG
MIN
TYP*
2.0
Mute and Pulse Leakage:
V+ = 10.0 V, Vo = 10.0 V
0.001
1.0
p.A
NOTES
RKI
Keyboard Contact Resistance
1.0
kO
CKI
Keyboard Capacitance
30
pF
KIL
"0" Logic Level
V-
20% ofV+
V
KIH
"1" Logic Level
80% ofV+
V+
V
KRU
Keyboard Pull-Up Resistance
100
kO
3
KRD
Keyboard Pull-Down Resistance
5.0
kD
3
RHKS
HKS Pull-Up Resistance
100
kO
RCNTL
CNTL Pull-Up Resistance
100
kO
II
NOTES
*Typical values are to be used asa design aid and are not subject to production testing.
2.
1.
3.
Current necessary for memory to be maintained. All outputs unloaded. On-hook
mode.
VI-23
Current required for proper circuit function with a valid key input, off-hook or
on-hook mode. V+ ::::: 3.0 V.
Keyboard to be scanned at 125 Hz when oscillator enabled Rowand Column to
alternately pull high and low.
AC CHARACTERISTICS (The timing Relationships are shown in Figures 4 and 5)
SYM
PARAMETER
_fosc
Oscillator Frequency(antiresonant mode)
(Pulse Mode)
t DS
Keyboard Debounce Time
tos
Oscillator Start-Up Time
PR
Pulse Rate (Pulse Mode)
ts
Break Time: Pin 9 Tied to V+/Tied to
V- (Pulse Mode)
UNITS
NOTES
480
kHz
1
32
ms
2
TYP
MIN
MAX
8.0
ms
10.0
pps
60/68
ms
t lDP
Interdigital Pause (Pulse Mode)
840
ms
fosc
Oscillator Frequency (Tone Mode)
8.0
kHz
TR
Tone Out Rate
fosc/ 16OO
tones/sec
3
NOTES
1. Ceramic resonator should have the following equivalent values: R < 20 fl, RA:;::
70 kfl. Co oS 500 pF.
2. A key entry must be present after 32 ms to be valid (oscillator on).
3. lose = , IR, C,. and lor R, = 250 kfl and C, = 500 pF. lose = 8 kHz
TIMING CHARACTERISTICS TONE MODE
Figure 4
KEY
INPUT
DIGIT
1
NORMAL DIALING
DIGIT
9 ,..----,
AUTO DIAL
CONTINUE
HKS
INPU~L~~_ _ _ _ _ _ _- - J
'u
~lllllloSCON IIIID('~ Ilose aNI IDC
VI-24
TIMING CHARACTERISTICS PULSE MODE
Figure 5
DIGIT
-..J
I.- tKD
4
KEY INPUT ~
DIGIT
CO~~~~ ~___
DIGIT
~----------------
_
___
:
_________
---::J1J1.fl.r
ROWSCAN~II
------~----------=lJ1JlJL.
ON-I~~~~ l
I
rli
_ _ ~_tDB
MUTE --:---1
OUTPUT
I DIGIT 2
PULSE
OUTPUT
OSC'UA'~Rr~1
100ms
I
DIGIT 4
b:f
I
II
I
I
I
I
I
II
Ii
I
I
DIGIT 2
I
NG j N
roR R U
111111' - OSC·lOFF
L
.
tIDP--i
OFF-HOOK MODE
(NORMAL)
I
DIGIT 4
um
I
OSCILLATOR RUNNING
REDIAL MODE
~
I
ON-HOOK
TYPICAL APPLICATIONS
Pin 2 (MODE) is connected to V- to set the MK5175 in the
Pulse dialer mode. In this mode, Pins 7 and 8 are defined as
the oscillator pins and Pins 9, 10, and 16 are defined as
M-B, Mute, and Pulse, respectively.
REPERTORY PULSE DIALER
The schematic diagram in Figure 6 shows one method
which can be used to interface the MK5175 with the
telephone line. In the approach shown, the MK5175 is in
the pulse-dialer mode and the pulsing circuitry is in series
with the speech network.
A current source of some type is desired to present a high
impedance to the telephone line while guaranteeing
sufficient current to power the MK5175 while off-hook and
dialing. The current source shown. is constructed using
diodes 01 and 02, resistors R1 and R2, and transistor 01
Other implementations, such as a constant current diode,
may be considered.
The Pulse and Mute outputs drive external transistors to
perform the outpulsing function. Resistor R7 and capacitor
C4 are connected across transistor 03 for suppression of
noise-producing sharp voltage rises generated during
outpulsi ng. The receiver is connected to the speech network
through transistor 04. Mute causes the transistor to be held
on until outpulsing begins. When Mute switches low, the
receiver is removed from the network. The transients
caused by breaking the line are then isolated from the
receiver. The Pulse output drives transistor 03 to make and
break the line until the digit has been completely outpulsed.
Mute then switches high, returning the receiver to the
speech network.
A diode bridge is used to insure the proper voltage polarity
for the MK5175, and hook switch 51 is used to connect the
circuit to the telephone line. Hook switch 52 is used to
provide the logic level necessary at Pin 15 to set the
MK5175 in its off-hook mode.
A 3-volt battery has been included in the circuit to provide
current to the MK5175 to retain the numbers stored in
memory and to provide the power necessary for the onhook entry and storage of numbers.
VI-25
TYPICAL APPLICATION PULSE MODE
Figure 6
TELEPHONE
LINE
A,
D,
D2
a,
D3
A5
V+
A3
A4
MODE
~TE/I-'~O~-t-la2
,
2
3
456
7
8
9
•
0
#
FORM A KEYBOARD
01,4= 2N5401
01;2 = lN914
C2, 3 = 100 pF
02 = 2NS550
03 =lN270
C4 = 0.1 /IF
RS = 3 k!l
03 = 2N6660
04-7 = 1N4004
Rl=l.Sk!l
R6 = l00k!l
BAIT. = 3 V battery
Cl= 10 /IF@ 16 V Low Leakage
R2 = 820k!l
R7 = 330 k!l
R3 = 470 k!l
R8 = l00k!l
S 1,2 = Hook Switch
NOTE: Tr!'nsient protection circuitry not shown.
VI-26
± 20%
R4 = 4.7 M!l
1982 TELECOMMUNICATION PRODUCTS DATA BOOK
MOSTEI(.
INTEGRATED TONE RECEIVER
MK5102(N)-5
FEATURES
o
MK5102 PIN OUT
Detects all 16 standard DTMF digits
o Requires minimum external parts count for
v+
minimum system cost
OSCIN
o Uses inexpensive 3.579545 MHz crystal for
reference
o Digital counter detection with period averaging
insures minimum false response
o
16-pin package for high system density
o
Single supply 5 Volts ± 10%
o
Output in either 4-bit binary code or dual 2-bit
row/column code
o Latched outputs
DESCRIPTION
The MK5102 is a monolithic integrated circuit
fabricated using the complementary-symmetry MOS
(CMOS) process. Using an inexpensive 3.579545 MHz
television colorburst crystal for reference, the
MK5102 detects and decodes the 8 standard DTMF
frequencies used in telephone dialing. The requirement of only a single supply and its construction in a
16-pin package make the MK5102 ideal for applications requiring minimum size and external parts
count.
2
16
IIC
15
IIC
OSC OUT
3
14
IIC
STROBE
4
13
FORMAT.
CONTROL
5
12
V-
6
11
IIC
HIGH-GROUP
INPUT
LOW-GROUP
INPUT
01
7
10
04
02
8
9
03
The MK5102 detects the high and low group DTMF
tones after band splitting using a digital counting
method. The zero crossings of the incoming tones
are counted over several periods and the results
averaged over a longer period. When a minimum of
33 milliseconds of a valid DTMF digit is detected,
the proper data is latched into the outputs and the
output strobe goes high. When a valid digit is no
longer detected, the strobe Will return low and the
data will remain latched into the outputs. Minimum
interdigit time is 35 .milliseconds.
The MK5102 is designed to interface with the
MK5099 Integrated Pulse Dialer with only one additional DIP Package. These two parts working together form a DTMF-to-Pulse converter that meets the
recognized telephone standards;
V"-1
ABSOLUTEMAXIMUM RATINGS'"
DC Supply Voltage V+ (Referenced to V-I ......................... +6.0 Volts
Operating Temperature ........................................ O°C to 70°C
Storage Temperature ...................................... -55°C to 100°C
Maximum Circuit Power Dissipation ....................... ; ......... 300 mW
Voltage on any pin, with respect to V- ............................. -0.3 Volt
Voltage on any pin, with respect to V+ ............................. +0.3 Volt
*Operation Above Absolute Maximum Ratings M§.YD~amage The Devicp
ELECTRICAL CHARACTERISTICS
0° C';;; T A';;; 70° C
V- = 0 Volts
PARAMETER
Supply Voltage (V+)
Lo Group & Hi Group
Inputs
STROBE 01, 02, 03, 04
OUTPUTS
FORMAT CONTROL
Input
CONDITIONS
MIN
(V-=O)
50% Duty Cycle
Square Wave
MAX
UNITS
4.5
5.5
Volts
0.9
V+
Volts
Peak-to-Peak
!'O" Level
0.0
0.4
Volt@.1.6 mA
"1" Level
"0" Level
(V+)-1
V+
0.5
Volts @ 0.1 mA
Volt @ 700fJA
"1" Level
(V+)-0.5
V+
Volt @ 700fJA
0.0
Frequency Detect
Band Width
± 2.0
Tone Coincidence
Duration
33
Interdigit Interval
Signal to Noise Ratio
Supply Current @ 5.5V
TYP
± 2.5
± 2.9
NOTES
1,2
% of fo
ms
4
35
ms
4
18
dB
3
Inputs and
Outputs Unloaded
5
mA
10
NOTES:
1.
Due to internal biasing, this input must be capacitively coupled with
a low leakage .05
2.
3.
fJ F capacitor.
SN = 20 log ~~
where SA
No coupling capacitor is needed if, the DTMF square wave meets
"1"
4.
a. Logic "0". level = 1 Volt (max)
b. Logic "1" level = 4 Volts (min)
= RMS Amplitude of single tone being detected.
NA = RMS white noise in the band from 300Hz to 3.4KHz,
the following criteria:
, -, .. _.. r - l
. LLJ
L
Signal-To-Noise Ratio is defined as:
Tone coincidence duration and interdigit interval measured at Highand Low-group inputs. Filter c;lnd/or limiter or comparator characteristics will affect the overall detect time .
OSCILLATOR
The MK5102 contains an on-board inverter with
sufficient gain to provide oscillation when working
with a low cost television "color burst" crystal.
The inverter input is OSC IN (pin 2) and output is
OSC OUT (pin 3). The circuit is designed to work,
with a crystal cut to 3.579545 MHz to give detection
of the standard DTM F frequencies.
a 4-Bit Binary Code, a Dual 2-Bit Row/Column code,
or high-impedance output for use with bus-structured
circuitry. This three-state input is' controlled as
follows:
FORMAT CONTROL (PIN 5)
The Control pin is used to control the output format
of Pins 01 through 04. This three-state input selects
VII-2
FORMAT
CONTROL,INPUT
VV+
Floating
OUTPUT
DATA FORMAT
High Impedance
4-Bit Binary
Dual 2-Bit Row/Column
FORMAT CONTROL (Continued)
SUGGESTED INPUT LIMITER CIRCUIT
Figure 2
The followina tablE' describes the two output codes.
Tabie 1
Dual 2-Bit Row/Column
Column
Row
4-Bit Binary
D3 D4
Digit D1 D2 D3 D4 D1
D2
1
0
0
0
0
1
0
1
HIGH
GROUP
1
lKH
.05"F
12
FILTER
0
2
0
0
1
0
0
1
1
3
0
0
1
1
0
1
1
1
4
0
1
0
0
1
0
0
1
5
0
1
0
1
1
0
1
0
6
0
1
1
0
1
0
1
1
7
0
1
1
1
1
1
0
1.
8
1
0
0
0
1
1
1
0
9
1
0
0
1
1
1
1
1
0
1
0
1
0
0
0
1
0
*
#
1
0
1
1
0
0
0
1
1
1
0
0
0
0
1
1
A
1
1
0
1
0
1
0
0
B
1
1
1
0
1
0
0
0
C
1
1
1
1
1
1
0
0
[j
DTMF
IN
LOW
GROUP
FILTER
lKH
.05.uF
11
OUTPUTS D1 THRU D4
(PINS 7 THRU 10)
Outputs D1 thru D4 are CMOS push-pull when
enabled and open-Circuited (high impedance) when
disabled by the format control pin.
D1 thru D4 are the data out lines. The output data
can be in two formats as described in the section
about the format control pin (pin 5).
0
0
0
0
0
0
0
0
Figure 1 shows the relationship between the data
output code shown in Table 1 and the standard
DTMF keyboard.
DTMF DIALING MATRIX
Figure 1
MK5102
The Dual 2-Bit Row/Column code decodes with D1
and D2 indicating the row selected, and D3 and D4
indicating the column selected.
The two output codes allow the user to obtain either
1-of-16 or 2-of-8 output data by using only a single
additional package.
I/C (PINS 13 THRU 16)
Col 1
Col 2
Col3
Col4
Pins 13 thru 16 are internally connected and are
intended to be left floating.
Row 1
[!]
STROBE (Pin 4)
8]
0
III
0
Row2
0
Row3
[IJ
0
@J
Row4
~
0
0
0
0
[i1
@]
The STROBE output goes to a "1" when 33 miliseconds of a valid DTM F signal is detected and remains at a "1" until an interdigit interval has been
detected. The data at D 1-D4 are already valid when
STROBE goes to a "1" and will remain unchanged
until the next DTMF digit is detected.
Note: Column 4 is for special applications and is not
normally used in telephone dialing.
DETECTION FREQUENCY
Table 2
Low Group to
Row 1 =
Row 2 =
Row 3 =
Row4 =
697 Hz
770 Hz
852 Hz
941 Hz
High Group to
Column 1 =
Column 2 =
Col,umn 3 =
Column 4 =
1209 Hz
1336 Hz
1477 Hz
1633 Hz
LOW-GROUP INPUT (Pin 11) and HIGH-GROUP
INPUT (Pin 12)
The low- and high-group inputs are comparators that
can detect capacitively-coupled square-wave signals as
small as 0.9 volts peak-to-peak. The circuitry driving
these inputs would typically use back-to-back silicon
diodes as symmetrical limiters to regulate this level.
These inputs are biased to the midpoint of the
supply with a resistive divider. Nominal input impedience is 100K fL.
VII-3
MK5102 BLOCK DIAGRAM
INPUT BAND SPLIT REQUIREMENTS
osc
IN
,1-
r----,
osc
OUT
LOW GROUP
500
H,
1000
2000
3000
H,
H,
H,
FREQUENCY
RHA TlVE INPUT LEVEL VS FREQUENCY
L
NOTES:
1. Dial tone notch filter adequate to maintain SIN ratio of ;;" 18dB
in above pass bands.
2. Filter response described above will normally result in operation to
6dB of twist with 18dB SIN.
VII-4
.. _
.. __ .___ .__--+_._~
MOSTEI(.
MK5102(N)-5 DTMF DECODER
Application Note
This application note will describe all of the requirements for building a high-quality DTMF receiver
using the MK5102N-5 and hybrid filters. The following topics will be discussed:
1.
2.
3.
4.
5.
6.
7.
Power supply requirements
Band separation filter requirements
Squaring circuit requirements
Squaring circuit-to-decoder coupling requirements
Receiver testing
Output formatting
Other system considerations
Since the MK51 02N-5 is intended to be a portion of a
tone receiver SYSTEM, SYSTEM requirements must
be met before a satisfactorY decoder can be constructed. A block diagram of a typical system is
shown in Figure 1. Each portion of the block diagram
is discussed in succeeding paragraphs.
TYPICAL DTMF RECEIVER
Figure 1
FROM
TELEPHONE
ments are not as stringent for the MK51 02N-5 as they
are for competing designs. As shown in figure 2, the
MK5102N-5 requires a band separation of only 33d8
in an average application. The 33dB requirement
allows for a SIN ratio of 18dB, 6dB of twist, and a
detection bandwidth of at least ± 2%. A reduction of
twist margin or SIN requirements will result in a corresponding lower requirement for band separation.
For example, if there is not a requirement for twist
margin, the band separation can be reduced to 27dB.
In a system with no noise and no twist, the band
separation can be 22dB.
The plot shown in Figure 2 depicts corner frequencies
of 683Hz, 960Hz, 1184Hz and 1666Hz. These represent a 2% deviation from theDTMF frequencies of
697Hz, 941 Hz, 1209Hz and 1633Hz, respectively.
This deviation is necessary because of the requirement that a DTMF receiver must detect frequencies
which are 2% higher or lower than the nominal
DTMF frequency. Table 1 lists the 8 DTMF frequencies and the corresponding frequencieS which a
DTMF decoder is required to,detect.
BAND SEPARATION FILTER REQUIREMENTS
LINE
INTERFACE
I
Figure 2
rfi
POWER SUPPLY REQUIREMENTS
3
-lOdS
z
~
~
For proper operation of the MK5102N-5, the V+
power supply must be between 4.5 VDC and 5.5'
VDC, with V- grounded. A power supply decoupling
capacitor (typically .1 u F) should be connected between V+ and V- to insure that no high-frequency
noise is present on the V+ supply. Typically, a 1-volt
peak-to-peak signal may be applied to V+ and the
MI(5102N-5 will function properly.
~
">
~
HIGH·
GROUP
FILTER
1500
Hz
2000
Hz
2500
H,
3000
H,
BAND SEPARATION FilTER REQUIREMENTS
FILTER REQUIREMENTS
NOTES:
For proper operation of the MK51 02N-5, an external
band separation filter must be provided to split the
DTMF signal into its high-group and low-group
components. However, the band separation require-
1. Dial tone notch filter must maintain SIN ratio ;;'18dB
2. Filter response shown will allow operation to 6dB of twist with
18dB SIN.
V/I-5
TABLE I
POSSIBLE INPUT WAVEFORMS
8 STANDARD DTMF FREQUENCIES AND CORRESPONDING UPPER AND LOWER REQUIRED
DETECTION FREQUENCIES
Figure 3
LOWER
DETECTION
DTMF
FREQUENCY
FREQUENCY (HZ) LIMIT (HZ)
697
770
852
941
1209
1336
1477
1633
683
755
834
922
1184
1309
1447
1600
UPPER
DETECTION
FREQUENCY
LIMIT (HZ)
711
786
869
960
1233
1363
1507
1666
f-lt--l'--l--l--+-l---1--+--+--l--+--f-+----I--'t--I'--I---'/
VAll D
f--\-l----\----f--\--f--t--If-+-Hrl-+---I-t-I'----t----l
REJECT
f-ll-f---1r-f--l--l---I--+----\---+++-\---Jf---\r-f'--l----I
REJECT
H---l'--l--l---1--l--+--+--+--l--+-+-+--I-\---t-\---,/
REJECT
HH'---l--f-++-++-+---f---l-I--t----cHH'---l-l VALID
INPUT SQUARING CIRCUITS
DETECTION ALGORITHM
The detection approach used inthe MI<5102N-5 utilizes zero-crossing detection and digital period-counting. To increase the rejection of random noise and the
residue from out-of-band components, an averaging
scheme is used. Figure 3(a) shows nine cycles of a
symmetrical sine wave. If zero-crossings were the only
detection criteria, and if the average period-count obtained over nine periods were acceptable, then the signal in Figure 3(a) represents a valid tone. The jitter of
the zero-crossings is integrated out by the nine-period
average. However, based on the simple nine-period
average, the signal shown in Figure 3(b) would be
accepted as a valid tone. To improve rejection of this
speech-type waveform, the nine-period detection time
can be broken into three period-averaged sub-groups
as indicated by the dashed lines in Figure 3(b). By
combining the nine-period average and the sub-group
average criteria, 200 false hits are obtained on 30
minutes of a standard speech tape. Figure 3(c) represents a type of waveform that would produce a hit
based on the nine-period and sub-group average algorithm. To improve rejection ohhis waveform, requirements must be placed on every single period in addition to the nine-period average and the sub-group
average. However, the waveform of Figure 3(d) will
be detected using only these three criteria. Therefore
an additional requirement must be placed on each
half-period of the waveform. Figure 3(e) shows the
only type of signal which will be accepted by a detection algorithm which requires the follpyving:
1. Valid nine-period average
2. Three valid subcgroup averages
3. Valid single-period
4. Valid half-period
Using these four criteria, the number of hits on a
standard speech tape can be reduced to .Iess than six.
As described above, to minimize the number of false
hits, a detection algorithm must place stringent requirements on each half-period of the input waveform (high group or low group). To successfully meet
these requirements, the duty cycle of the input waveform must be between 49% and 51%. The input
squaring circuit must therefore provide an output
which accurately tracks the input without adversely
affecting the duty cycle. Such a circuit, an inverting
comparator with hysteresis, is illustrated in Figure 4.
INPUT SQUARING CIRCUIT
Figure 4
+5
Cl
~~L~~R >--11--...---1
+5
TO MK5102N·5
R3
Rs
Rl
10K
6eOK
470
C1 is used to ac couple the filter output to the squaring circuit so that DC bias present at the filter output
will not affect the performance of the squaring circuit. R3, R4, and R6 establish a bias level at about
2.5 Volts, and R5 is used to provide the same bias
level at the inverting input of the comparator used in
the squaring circuit. The maximum input bia~ current
for the LM2901 is 500nA, so the DC bias level at the
inverting input is effectively the same as the voltage
at the wiper of R6. R6 must be adjusted so that, for
an input signal level of -28dBm, the output duty
cycle will be 50%. This adjustment compensates for
VII-6
the input offset voltage of the LM2901. R L is the
pullup resistor for the open-collector output of the
comparator. R1 and R2 set the hysteresis level. Their
values are determined by the following approximate
relationships:
VUT=2.5+
(2.5) (R1)
(R1 + R2 + RL)
VLT = (2.5 - VOL) (R2)
(R1 + R2)
where VUT is
the upper
threshold
where VL T is
the lower
threshold and
VOL is the
ou tpu t satu ration voltage
In both cases, any variation due to the current in R5
is ignored.
For central office applications, the tone receiver system must operate over an input signal level range of
-26dBm to +6dBm. The squaring circuit, therefore,
must respond to signal levels of -26d Bm or greater
b_~t is not required to respond to lower signal levels.
To allow for signal attenuation through the band separation filter, the squaring circuit should be set to respond to signal levels of -28dBm or greater. The
-28dBm cutoff point corresponds to a peak-to-peak
voltage of 87.1 mV. For a 50% duty-cycle output
waveform, VUT should be set 43.5mV above and
VL T should be set 43.5mV below the DC bias point.
The passive components for the squaring circuit are
then selected as follows:
RL = 1kD.
R2 = 680kD.
R 1 = 12kD.
R3 = R4 = 470D.
Chosen value.
Chosen value.
Calculated value.
Chosen value for DC bias.
Chosen value. Tradeoff effect on
DC bias vs. drop across R5 due
to 2901 input bias current.
Chosen value. Must be low impedance over frequency range of
683Hz to 1666Hz.
To achieve proper operation at low signal levels, R1
must be 10kD.. The discrepancy between the calculated value and the actual required value results from
component tolerances.
Since many commercially-available filters exhibit a
ringing characteristic at their output, as shown in Figure 5 and Figure 6, additional circuitry is required to
detect the beginning of ringing and squelch the output of the squaring circuit. The required circuitry, an
envelope detector, is shown in Figure 7. The detector
consists of two precision rectifiers, two sample-andhold circuits, and a comparator. C3 is used to couple
the low-group filter output to the envelope detector.
Z1a, 01, C1, R2, and R3 then rectify the incoming
signal and store a peak value. The R2/R3/C1 time
constant is set for 20ms so that the voltage at the inverting input of Z2 will represent Y, the peak value of
the incoming signal. Z1b, 02, R1 and C2 also rectify
the incoming signal and store a peak value, but the
time constant is set for 1.4ms so that the voltage at
the non-inverting input of Z2 will represent the
instantaneous peak value of the incoming waveform.
As long as the instantaneous value is greater than Y, of
the peak value, the comparator output will be high.
However, as soon as the instantaneous value decreases
to less than Y, the peak value (this will occur as ringing begins), the comparator output will go low and
inhibit the output of the squaring circuit. It is necessary to provide only one envelope detector since the
MK5102N-5 will treat the absence of a valid lowgroup/high-group tone combination as interdigit time.
LOW-GROUP FILTER RESPONSE (3044)
Figure 5
DTMF INPUT TO FILTER (5V/DIV.)
LOW·GROUP
FILTER OUTPUT (lV/DIV.)
SQUARING CIRCUIT
OUTPUT (5V/DIV.)
STROBE FROM MK5102N·5
(5V/DIV.)
EACH TIME DIVISION = 10 MS
VII·7
HIGH-GROUP FILTER RESPONSE (3045)
Figure 6
EACH TIME DIVISION
= 10 ms
DTMF INPUT TO FILTER (5V/DIV.)
LOW-GROUP
FILTER OUTPUT (lV/DIV.)
SQUARING CIRCUIT
OUTPUT (5V/DIV.)
STROBE FROM MK5102N·5
(5V/DIV.)
ENVELOPE DECAY DETECTOR
Figure 7
Z1 = 1458
Z2 = 2901
v+
C3
FROM
LOW·GROUP
FILTER
.01/lF
>-----ll---------l
>-_...... TO SQUAR ING
CIRCUIT
4
v-
ENVELOPE DETECTOR OPERATION
Figure 8
LOW-GROUP
FILTER OUTPUT (lV/DIV.)
INSTANTANEOUS PEAK
DETECTOR (lV/DIV.)
AVERAGE PEAK
DETECTOR (lV/DIV.)
LOW-GROUP INPUT
TO 5102N-5 (5V/DIV.)
VII-S
SQUARING
CIRCUIT-TO-DECODER COUPLING
The output of the squaring circuit may be tied directly to the MK5102N-5 if it meets the following requ irements:
The peak-to-peak value of the coupled signal must be
greater than .9 volts but less than V+ volts.
OUTPUT SIGNALS
D 1, D2, D3, and D4 are the data output lines. The
output format present on these pins is determined by
the format control (pin 5) as shown in Table 2.
Logic 1~ 4 volts
Logic 0.;; 1 volt
A squaring circuit with an output that does not meet
these requirements must be capacitively coupled to
the MK5102N-5 with a 0.05J.1F capacitor. The value
of the coupling capacitor is critical because of the
impedance of the bias circuit at the high-group or
!Iow-group input. As shown in Figure 9, the sudden
appearance of a tone burst causes the DC bias point
to shift upward. Until the DC bias returns to its normal level, the input comparator will not switch and
the input signal will be ignored, causing an increase in
the dual-tone detection time. Using a 0.05J.1F capacitor will minimize the effect of this DC level shift.
FORMAT CONTROL FUNCTIONS
TABLE 2
Format
Control Input
Data
Output Format
V-
High Impedance
V+
4-Bit Binary
Floating
Dual 2-Bit Row/Column
SHIFT IN DC BIAS LEVEL CAUSED BY
APPLICATION OF TONE BURST
Figure 9
HIGH-GROUP INPUT (IV/DIV.)
COUPLING CAP. = 1J.1F
SQUARING CIRCUIT
OUTPUT (lV/DIV.)
Table 3 describes the two output codes available.
TABLE 3
OUTPUT FORMAT
Key
Row
Col.
1
2
3
4
5
6
1
1
1
2
2
2
3
3
3
4
4
4
1
2
3
4
1
2
3
1
2
3
1
2
3
2
1
3
4
4
4
4
7
8
9
0
*
#
A
B
C
0
4·Bit Binary
01
02
03
04
0
0
0
0
0
0
0
1
1
1
1
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
0
1
0
1
0
1
0
Oual2·Bit
Row/Column
Column
Row
01
02 03 04
0
0
0
1
1
1
1
1
1
0
0
0
0
1
1
0
1
1
1
0
0
0
1
1
1
0
0
0
1
0
1
0
0
1
1
0
1
1
0
1
0
1
1
0
1
1
1
0
1
0
1
0
0
0
0
0
1
1
1
1
0
0
0
0
'Nhen all detection criteria are present, the. MK5102N-5 will latch the proper data into its outputs
and strobe will go high. After an interdigit time has
been detected, strobe will go low, but the data will remain on D1 through D4.
The dual 2-bit row/column code is useful when interfacing a key-to-pulse converter, as shown in Figure
10. On this circuit, the MK51 02N-5, CD4556 and MK
5099 combine to form a tone-to-pulse converter,
which allows the use of DTMF telephones in rotary
exchanges. The DTM F tones are detected by the MK
5102N-5, which then generates the corresponding
row/column code. Each CD4556 then uses this 2-bit
code to select 1 of 4 active-low outputs. The MK5099
then interprets these signals as a valid key closure and
generates a corresponding series of pulses.
VII-9
For simple remote-control applications, the circuit of
Figure 11 is useful. After a valid tone is detected,
strobe will go high and one of the 16 outputs on the
binary-to-1-of-16 encoder will go true. Thus, a DTMF
transmitter and 16-key keyboard can be used to control 1 of 16 functions in a DTMF receiver. Each control pulse will have its width controlled by Strobe.
TONE-TO-PULSE CONVERTER
Figure 1(}
v+
=3.579545MH.r:
c:::J
3.S79P45MHz
,--,
11 U2
MK51Q211>5
I
TONE OUT
16
10 04
9 03
10K
13 R4
r
., P'tiLsE
15 R2
18
16 Rl
I
14 R3
I
__
I
'-
U4
MK5099
MUTE 12
-
l~CHANNELREMOTECONTROL
V+
Figure 11
=
c:::J
3.579545MHz
3.579545MHz
TRANSMISSION
MEDIUM
,--,
16
TONE OUT
I
V-
•
CD4514 OUTPUTS ARE ACTIVE HIGH
CD4515 OUTPUTS ARE ACTIVE LOW
VII-10
CHANNEL 0
CHANNEL 1
CHANNEL 2
CHANNEL 3
CHANNEL 4
CHANNEL 5
CHANNEL 6
CHANNEL 7
CHANNELS
CHANNEL 9
CHANNEL 0
CHANNEL·
CHI\NNEL#
CHANNEL A
CHANNEL 8
CHANNELC
RECEIVER TESTING
Equipment connections for testing a DTMF receiver
are shown in Figure 12. The setup consists of a cassette player (ideally with a speed adjustment), a digital frequency counter, and a voltmeter. A Mitel
CM7290 Tone Receiver Test Cassette was used in all
the receiver tests described below. This cassette
checks receiver detection bandwidth, maximum
acceptable amplitude ratio (twist), receiver guard
time, dynamic range and acceptable signal-to-noise
ratio. It also evaluates the receiver talk-off rate with a
condensed speech recording equivalent to many hours
of receiver exposure. The CM7290 is available from
Mitel at the locations listed.
Mitel International
Shannon Industrial Estate
Shannon, Ireland
Telephone. 061-61433
Telex: 32208
Mitel Corp.
P.O. Box 13089 Kanata
Ottawa, Ontario, Canada
K2K1X3
Telephone: 613-592-2122
Telex: 053-4596
Cable Mitelcan
Twx: 610-562-8529
Mitel Inc.
St. Lawrence Industrial Park
Ogdensburg, New York 13669
Telephone: 315-393-1212
Twx: 510-259-4071
There are several considerations in setting up a receiver test. First, the recorder should have a speed adjustment and an output level adjustment. Each side of
the CM7290 contains a 1 kHz calibration tone. To set
up properly for the test, the speed of the recorder
should be adjusted so that the tone frequency is 1 kHz
and the cassette player output level should be adjusted to 2 volts RMS. The cassette player must be
able to provide the 2-volt output level without clipping. If a speed adjustment is not available, printed
instructions included with the CM7290 provide a formula for correcting some of the test results. Second,
the strobe output of the MK5102N-5 should be tied
to the input of the event counter and the counter's
sensitivity input adjusted so as to prevent false triggering. This can easily be done by repeating test 2a on
the CM7290 until consistent results are obtained.
Third, any sources of environmental noise (electric
motors, speed controls, etc) should be eliminated so
that they will not introduce count errors on the event
counter.
FILTER EVALUATION
Two commercially-available filters, the CH 1295 and
CH 1296 from Cermetek and the 3044 and 3045 from
ITT North Electric Microsystems, were evaluated.
The addresses of these two filter vendors are listed
below:
EQUIPMENT CONNECTIONS FOR RECEIVER
EVALUATION
Figure 12
I
CASSETTE
FREQ.
COUNTER
PLAYER
o 0
o U1UT SPEto
L EVEL
ADJUST
ADJUST
H
>---- HIGH·GROUP
FILTER
-
I
TRUE
RMS
METER
saUARING
CIRCUIT
SET SPEED SO FREQUENCY
OF CALIBRATION TONE = 1KHz
ADJUST LEVEL OF CALIBRATION
TONE TO 2 VOL T5 RMS
ITT North Microsystems Division
700 Hillsboro Plaza
Deerfield Beach, F L 33441
Telephone: 305-421-8450
Twx: 510-953-7523
......g HIGH·GROUP
INPUT
MK5102N·5
STROBE ~
>---
LOW·GROUP
FILTER
r--
saUARING
CIRCUIT
EVENT
COUNTER
Figure 13 and Table 5 show the test circuit and test
results for the Cermetekfilters. The test circuit and
test results for the North Electric filters are shown in
Figure 13 and Table 4. The tests were performed
using the equipment setup shown in Figure 12. Figures 14 through 17 show the spectral response of the
filters.
-1! LOW·GROUP
INPUT
600
"
-=
Cermetek, Inc.
660 National Avenue
Mt. View, CA 94043
Telephone: 415-969-9433
Twx: 910-379-6931
~
CSC.IN
3.58MHz,C)
L..2 asc. OUT
VII-"
TEST CIRCUIT FOR CERMETEI< AND NORTH ELECTRIC FILTERS
Figure 13
+5
FROM
>-_--...:2='10 INPUT OUTPUT 16
RECORDER
5
+5
13 V+
18 Vl470
GND
CH1296 OR 3045
HIGH·GROUP
FILTER
MK5102N·5
1 .
10K
STROBE
3.58 .. 20SC.
MHzc::::J
IN
+5·
3 0SC .
OUT
i4~0
600
-12
V13
V+
18 GND
Q
_
!
20 INPUT OUTPUT 16
5·
.+5
+12
_
CH1295 OR 3044
- -
L~,~;tROUP
4~7_0~~1~OK~~_~~____~____________~
_~O
TABLE 4
TABLE 5
IVIITEL TAPE TEST RESULTS FOR CERMETEK FILTERS
TEST#
R ESU L TS
BW= 4.7 % of fa
-
2a, b
BW= 5.6 % of fa
BW = 5.7 % of fa
2c,d
BW= 5.2 % of fa
2c,d
2e, f
BW= 5.1 % of fa
2e, f
BW=
2g,h
BW= 5.1 % offo
2g, h
BW = 5.3 % of fa
2i, j
BW= 5.1 % otfo
2i, j
BW=
5.2 % of fa
2k,.1
BW= 4.9 % of fa
2k, I
BW=
5.0 % of fa
2m, n
BW= 5.5 % of fa
2m, n
BW =
5.5 % of fa
20,p
BVV = 5.0 % of fa
20,p
BVV =
3
TO EVENT
COUNTER
LOW·
'>-4__--'-1-"-11 GROUP
INPUT
MITEL TAPE TEST RESULTS FOR NORTH ELECTRIC FILTERS
TEST# IRESULTS
2a, b
4
3
159 decodes
5.0 % of fa
5.0 % of fa
158decodes
4
Acceptable Amplitude Ratio =.13.1dB
4
Acceptable Amplitude Ratio = 12.6dB
5
Dynamic Range = 31.33
6
Guard Time = 34.23 m.
99.!' % Successful Decode at N/S Ratio
5
6
7
Guard Time = 33.4 ms
7
dB
98.33 % Successful Decode at N/S Ratio
of ·12dbV
of ·12dbV
8
Dynamic Range = 31.67 dB
8
3 Hits on Talk·Off Test
VII-.12
3 Hits on Talk·Off Test
SPECTRAL RESPONSE OF 3044 LOW-GROUP
FILTER
SPECTRAL RESPONSE OF CH1295 LOW-GROUP
FILTER
Figure 16
Figure 14
FILTER 0
GAIN
(dB)
-10
FILTER 0
GAIN
(dB)
-10
-20
-20
-30
-30
-40
-40
-50
-50
-60
-60
-70
-70
-80
FREQUENCY
250 350 450 550 650 750 850 950 1050 1150 1250
FREQUENCY
(HZ)
(HZ)
SPECTRAL RESPONSE OF CH1296 HIGH-GROUP
FILTER
SPECTRAL RESPONSE OF 3045 HIGH-GROUP
FILTER
Figure 15
Figure 17
FILTER
GAIN
(dB)
FILTER
GAIN
(dB)
0
950 1150 1350 1550 1750 1950 2150 2350 2550 2750
FREQUENCY
750 950 1150 1350 1550 1750 1950 2150
FREQUENCY
(HZ)
(HZ)
± 2.9% bandwidth. However, adding the noise term
OTHER SYSTEM CONSIDERATIONS
System noise will affect the operation of the
M K51 02N-5 by causing the detection bandwidth to
shrink_ The instantaneous value of the low-group or
high-group waveform is represented by the following
approximate relationship, a = aT sin wTt + aN sin
wNt, where a is the instantaneous amplitude of the
overall waveform, aT is the amplitude of the highgroup or low-group component, and a1\1 is the amplitude of the noise_ If the highly-simplified noise term
(aN sin wNt) were removed, then the remaining term
would represent a pure sine wave and the zero crossings of the waveform would be repeatable from cycle
to cycle. All detection criteria would be present and
the DTMF tone would be detected within a ± 2.0% to
introduces instantaneous amplitude variations which
will effectively alter the duty cycle of the sine wave
by causing the zero crossing points to jitter. If 0.5%
jitter is caused by system noise, detection bandwidth
will be decreased by _5%. Therefore, as the system
noise level increases, the detection bandwidth will decrease.
As noted in the Filter Requirements paragraph, the
33dB band separation requirement allows for a SIN
ratio of 18dB, with 6dB of twist, which means that
the algorithm in the MK5102N-5 has been set up to
provide a ± 2% minimum detection bandwidth in the
presence of noise which is 18dB below the signal
level and in the presence of high-group and low-group
signals with an amplitude difference of 6dB.
VII-13
SUMMARY
The MK5102N-5 provides a high-performance solution for DTMF detection at a lower cost than competing approaches. Band separation requirements for
the MK5102N-5 are not as stringent as for competing
designs, and, as was seen in the test results of Table 4
and Table 5, the MK5102N-5 provides excellent.talkoff rejection. When used in conjunction with either
the Cermetek or the North Electric filters, the
M K51 02N-5 will give the user a high'quality DTM F
receiver which may be used in myriad applications.
VII-14
MOSTEI{.
TELECOMMUNICATION PRODUCTS
MK5102/S3525A
DTMF Receiver System
An inexpensive DTMF receiver system with a low parts
count may be constructed using the Mostek MK5l02 or
MK5l03 Tone Decoder with the AMI S3525A Bandsplit
Filter. The S3525A is an l8-pin monolithic CMOS
switched-capacitor filter. It uses a 3.58 MHz crystal as a
time base and has a buffered clock output to drive the
oscillator of the MK51 02/3. The S3525A also has on-chip
comparators which can be used to construct adjustable
squaring circuits.
will be well within its range.) With the potentiometer
adjusted so that the filter has unity gain, the results listed in
Tables 1,2, and 3 should be obtained. Tables 1 and 2 show
the Mitel test tape (CM7291 ) results for the DTMF receiver
system using the S3525A and the MK5102 or MK5103,
respectively. Table 3 shows the Minimum Tone Coincidence Duration for the system using the MK5102 and
MK5103 at various input levels.
The operation of the circuit shown in Figure 1 has been
verified at temperatures of O°C, 25°C, and 70°C. However,
Tables 1,2, and 3 show only the data for circuit operation at
25°C.
Using the circuit shown in Figure 1, the duty cycle of the
signals provided to the MK51 02 should be within the 50 ±
1% range which is required for reliable operation. (Since the
MK5103 requires a 50 ± 3% duty cycle, the input signals
MK5102/S3525A DTMF RECEIVER SYSTEM
Figure 1
+12 V
'5V
O~~ "F
~22"F
r
o
ItF
DT~II
5.1 K
II
1
= ;= 1 /-,F
FH OUT
r
IN
=:='
10
°ll"F
FHsa 8
11 1N _
HI IN
IN+
'7~
OSC
IN
680K
9
I
I
FORMAT
CONTROL
20 K
330 K
12
II
GH~~~;
2K
MK5102
14
II
BVREF
01"F+
5
LO IN-
"F
FLSQ
°'It"F
7
4 Vss
lOIN+
ose IN
ose OUT
16
6BOK
6
r
OR
4711 pF
1K
J
STROBE
20K
330 K
II
~
VII-15
STROBE
7
8
4-81T
BINARY
'1
8
GL~~~
9
IN
A
v-
y5DM~
D
C
6
10M
4
MK51Q3
2K
17
5
r--
IN
S3525A
FLOUT
v+
I
01"±
HIIN
/
10 K
1K
15
FEEDBACK
~I
1
21
CKOUT
Voo
~
25K
181
10
OUTPUT
MK5102 WITH AMI S3525A
MITEL TAPE (CM7291) TEST RESULTS
MK5103 WITH AMI S3525A
MITEL TAPE (CM7291) TEST RESULTS
Table 1
Table 2
TEST #
TEST #
RESULTS
RESULTS
2a,b
BW
= 4.6% of fa
2a, b
BW = 5.0% of fa
2c,d
BW
= 4.9% of fa
2c,d
BW
= 5.1 %of fa
2e, f
BW
= 4.7% of fa
2e, f
BW
= 4.9% of fa
2g,h
BW
2g,h
BW
= 5.2% of fa
2i,j
= 5.0% of fa
BW = 4.8% of fa
2i,j
BW
= 5.1 % of fa
2k, I
BW
= 4.7% of fa
2k, I
BW
= 5.0% of fa
2m, n
BW
= 4.8% of fa
2m, n
BW
= 5.2% of fa
20,p
BW
= 4.7% of fa
20, p
BW
= 5.1 % of fa
3
160 decodes
4
Acceptable Amplitude Ratio
5
Dynamic Range
6
Guard Time
99.0% Successful Decode at SIN Ratio of
12 dB
7
99.9% Successful Decode at SIN Ratio
of 12 dB
1 Hit on Talk-Off Test
8
1 Hit on Talk-Off Test
3
160 decodes
4
Acceptable Amplitude Ratio
5
Dynamic Range
6
Guard Time
7
8
= 18.2 dB
= 32 dB
= 34.8 ms
MK5102/3 WITH AMI S3525A
MINIMUM TONE COINCIDENCE DURATION
MK5102
Decode Time
MK5103
Decode Time
-28 dBm
43.4 ms
38.9 ms
-25 dBm
37.4 ms
34.7 ms
-20dBm
37.0 ms
34.7 ms
-10dBm
36.3 ms
28.8 ms
OdBm
37.3 ms
28.8 ms
+6dBm
36.5 ms
28.9 ms
dB
= 32 dB
= 32.5 ms
NOTES:
1 More information regarding the S3525A is available from:
American Microsystems Inc.
3800 Homestead Rd.
Santa Clara. CA 95051
Telephone: (408) 246-0330
TWX: 910-338-0018
2. More information regarding the MK5102 and MK5103 is available from:
Table 3
Input Level
dBm (600 0)
= 19.1
Mostek Telecom Dept.
1215 W. Crosby Rd.
Carrollton, Texas 75006
Telephone: (214) 323-1000
3. The AMI S3525A used in this evaluation was a typical part. Slightly different
results may be obtained depending upon the particular S3525A used.
VII-16
MOSTEJ(.
INTEGRATED TONE DECODER
MK5103(N)-5
FEATURES
o
o
Detects all 16 standard DTMF digits
o
Uses inexpensive 3.579545 MHz crystal for
reference
o
PIN CONNECTIONS
Figure 1
Requires minimum external parts count for
minimum system cost
v+
16
N/C
2
15
N/C
OSC OUT
3
14
N/C
STROBE
4 MK510313
(N)-5
OSCIN
Digital counter detection with period averaging
insures minimum false response
o 16-pin package for high system density
FORMAT
CONTROL
o Single supply: 5 volts ±10%
o Output in either 4-bit binary code or dual 2-bit
row/column code
o Will operate at 14dB SIN ratio under worst-case
signal conditions
o Latched outputs
DESCRIPTION
The MK5103 is a monolithic integrated circuit
fabricated using the complementary-symmetry MOS
(CMOS) process. Using an inexpensive 3.579545 MHz
television color-burst crysta I for reference, the MK51 03
detects and decodes the 8 standard DTMF frequencies
used in telephone dialing. The requirement of only a
single supply and its construction in a 16-pin package
make the MK5103 ideal for applications requiring
minimum size and external parts count.
The MK5103 detects the high~ and low-group DTMF
tones after band splitting using a digital counting
method. The zero crossings of the incoming tones are
counted over several periods and the results averaged
5
12
N/C
HIGH-GROUP
INPUT
LOW-GROUP
INPUT
v-
6
11
D
7
10
A
C
8
9
B
over a longer period. When a minimum of 30
milliseconds of a valid DTMF digit is detected, the
proper data is latched into the outputs and the output
strobe goes high. When a valid digit is no longer
detected, the strobe will return low and the data will
remain latched into the outputs. Minimum interdigit
time is 35 milliseconds.
The MK51 03 is designed to interface with the MK5099
Integrated Pulse Dialer with only one additional DIP
package. These two parts working together form a
DTMF-to-Pulse converter that meets the recognized
telephone standards.
A block diagram of the MK5103 is shown in Figure 2.
Functions of the individual pins are described beginning
on page 2.
BLOCK DIAGRAM
Figure 2
VII-17
ABSOLUTE MAXIMUM RATINGS*
DC Supply Voltage V+ (Referenced to V-) ........... " ........................................... +6.0 Volts
Operating Temperature ...................................................................... O°C to 70°C
Storage Temperature ..................................................................... -55°C to 100°C
Maximum Circuit Power Dissipation ........................... ; ............................... , .. 300mW
Voltage on anypin, with respect to V- ............................................................ -0.3 Volt
Voltage on any pin, with respect to V+ ........................................................... +0.3 Volt
*5,tresses above those ,listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
O°C :::; TA :::; 70°C V- = 0 Volts
PARAMETER
CONDITIONS
Supply Voltage (V+)
(V-
Lo Group & Hi Group
Inputs
STROBE, A. B, C, D
OUTPUTS
FORMAT CONTROL
INPUT
MIN
= 0)
TYP
MAX
UNITS
4.5
5.5
Volts
47% - 53% Duty
Cycle Rectangular
Wave
0.9
V+
Volts
Peak-to-Peak
"0" Level
0.0
0.4
Volt @ 1.6 mA
"1" Level
(V+)-1
V+
Volts @ 0.1 mA
"0" Level
0.0
0.5
Volt@ 700J.lA
"1 ".Level
(V+)-0.5
V+
Volt@ 700J.lA
± 2.0
Frequency Detect Band Width
± 2.5
± 2.9
NOTES
1,2
% offo
Tone Coincidence Duration
30
ms
4
Interdigit Interval
35
ms
4
Signal-to-Noise Ratio
14
dB
3,5
Supply Current @ 5.5V
Inputs and Outputs
Unloaded
2
NOTES:
1,
Due to internal biasing, this input must be capacitively coupled with a
low·leakage 0.05 pF capacitor.
2.
3.
~
Signal-To-Noise Ratio is defined as:
SN = 20 log ~!
4.
Tone coincidence duration and interdigit interval measured at High-, and
Low-group inputs. Filter and/or limiter or comparator characteristics
will affect the overall detect time.
5.
Signal-To-Noise Ratio with 33db Filter Separation.
A. Logic "0" level = , Volt (max)
B. Logic ", •. level = 4 Volts (min)
FUNCTIONAL DESCRIPTION
mA
where SA = RMS Amplitude of single tone being detected.
NA = RMS white noise in the band from 300Hz to 3.4KHz.
No CQuplir}g capacitor is needed if the DTMF rectangular wave meets the
following criteria:
"'"
5
3.579545 MHz to give detection of the standard DTMF
frequencies.
OSCILLATOR
FORMAT CONTROL (PIN 5)
The MK5103 contains an on-board inverter with
sufficient gain to provide oscillation when working with
a low-cost television "color-burst" crystal. The inverter
input is OSC IN (pin 2) and output is OSC OUT (pin 3).
The circuit is designed to work with a crystal cut to
The Control pin is used to control the output format of
Pins 7 through 10. This three-state input selects a 4-bit
Binary Code, a Dual 2-Bit Row/Column code, or highimpedance output for use with bus-structured circuitry.
This three-state input is controlled as follows:
V/I-18
Table 3 shows the detection frequency associated with
each row or column:
FORMAT CONTROL FUNCTIONS
Table 1
DETECTION FREQUENCY
Table 3
FORMAT
CONTROL INPUT
OUTPUT
DATA FORMAT
VV+
Floating
High Impedance
4-Bit Binary
Dual 2-Bit Row/Column
Low Group fo
Row
Row
Row
Row
The following table describes the two output codes.
Digit
1
2
3
4
5
6
7
8
9
0
*
#
A
B
C
D
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
1
1
1
1
0
0
0
1
1
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
1
1
1
0
1
0
1
0
1
0
1
1
1
0
1
1
1
0
1
1
1
1
1
1
0
0
0
0
1
1
0
0
0
0
0
1
1
1
0
0
0
0
1
0
1
0
= 1209 Hz
= 1336 Hz
= 1477 Hz
= 1633 Hz
The Dual 2-Bit ROW/Column code decodes with A and B
indicating the column selected, and C and D indicating
the row selected.
0
1
1
0
1
0
1
1
0
1
1
1
0
1
0
0
0
0
1
2
3
4
A thru D are the data out lines. The output data can be in
in two formats as described in the section about the
format control pin (pin 5).
1
1
1
1
Column
Column
Column
Column
Outputs A thru D are CMOS push-pull when enabled
and open-circuited (high impedance) when disabled by
the format control pin.
Dual2-Bit
Row
Column
D
C
B
A
0
0
0
= 697 Hz
= 770 Hz
= 852 Hz
= 941 Hz
OUTPUTS A THRU D
(PINS 7 THRU 10)
Table 2
4-Bit Binary
D
C
B
A
1
2
3
4
High Group fo
The two output codes allow the user to obtain either 1 of-16 or 2-of-8 output data by using only a single
additional package.
N/C (PINS 13 THRU 16)
Pins 13 thru 16 are not internally connected and may be
used as tie points.
0
STROBE (PIN 4)
0
0
Figure 3 shows the relationship between the data
output code shown in Table 2 and the standard DTMF
keyboard.
DTMF DIALING MATRIX
The STROBE output goes to a "1" when 30 milliseconds
of a valid DTMF signal is detected and remains at a "1 "
until an interdigit interval has been detected. The data at
A-D are already valid when STROBE goes to a "1" and
will remain unchanged until the next DTMF digit is
detected.
LOW-GROUP INPUT (PIN 11) AND HIGH-GROUP
INPUT (PIN 12)
Figure 3
Call
Col 2
Col 3
OJ
0
IT]
0
0
0
~
[iJ
Row 3
[2]
[i]
~
[£]
Row4
El
[Q)
0
[QJ
Row 1
Row 2
Note:
The circuitry driving these inputs, as shown in Figure 4,
should be squaring circuits which use resistive dividers
to set the output duty cycle to 50%. The squaring circuit
shown was designed to provide hysteresis and allow the
circuit to respond to signal levels of -28dBm or greater,
where -28dBm corresponds to a peak-to-peak voltage
of 87.1 mV. Any squaring circuit providing a 47% - 53%
duty cycle over the receiver and dynamic range is
sufficient.
Col 4
Column 4 is for special applications and is not normally used in
telephone dialing.
The high-group and low-group signals are provided by
the high-group filter and the low-group filter, as shown
in Figure 4. These filters have the response
characteristics shown in Figure 5 and are used to
separate the DTMF signal into its high-group and lowgroup components.
VII-19
SUGGESTED INPUT LIMITER CIRCUIT
INPUT BAND SEPARATION FILTER
Figure 4
Figure 5
683 Hz
960 Hl
1185 Hz
1666 Hz
OdS
-SdB
-1OdS
,
,
L'
DTMF
IN
"4
-15dB
V
L
·20dS
·25dB
·JOdS
·33dB
470
500
H,
R4
1000
2000
H,
H,
3000
H,
FREQUENCY
RELATIVE INPUT LEVEL VS FREQUENCY
NOTES:
APPLICATIONS
Two possible applications of the MK5103 are shown in
Figure 6 and Figure 7. The dual2-bit row/column code
is useful when interfacing a key-to-pulse converter, as
shown in Figure 6. On this circuit, the MK5103N-5,
C04556 and MK5099 combine to form a tone-to-pulse
converter, which allows the use of OTMF telephones in
rotary exchanges. The OTMF tones are detected by the
MK51 03N-5, which then generates the corresponding
row/column code. Each C045.56 then uses this 2-bit
code to select 1 of 4 active-low outputs. The MK5099
then interprets these signals as a valid key closure and
. generates a corresponding series of pulses.
TONE-TO-PULSE CONVERTER
Figure 6
For simple remote-control applications, the circuit of
Figure 7 is useful. After a valid tone is detected, strobe
will go high and one of the 16 outputs on the binary-to1 -of-16 encoder will go true. Thus, a OTMF transmitter
and 16-key keyboard can be used to control 1 of 16
functions in a OTMF receiver.
V+
V+
CLASS A KEYBOARD
14
1
=
=
3.579545MHz
3.579545MHz
,---,
16
L---------------__
~~3
TONE OUT
.
I
6
v-
STROBE
-=
TRANSMISSION
MEDIUM
10K
V+
13 R4
15 R2
r
16 R1
I
14 R3
I
IL
__
___
MUTE 12
VII-20
U4
MK5099
16-CHANNEL REMOTE CONTROL
Figure 7
V+
v+
CLASS A KEYBOARD
1
Format
14
Control
=3.579545MHz
=
v-
3.579545MHz
TRANSMISSION
MEDIUM
U1
r--,
U2
,,JIK51Q3N·5
I
TONE OUT
A
16
L_-'
STROBE
-=
101<
V+
10K
-=
*C04514 OUTPUTS ARE ACTIVE HIGH
C04515 OUTPUTS ARE ACTIVE LOW
OUTPUT SELECT
PULSE
LATCH
VII-21
1.-
-=
2N2222
CHANNEL 0
CHANNEL 1
CHANNEL 2
CHANNEL 3
CHANNEL 4
CHANNEL 5
CHANrJEl6
CHANNEl7
CHANNEL
CHANNEL
CHANNEL
CHANNEL
CHANNEL
CHANNEL
CHANNEL
CHANNEL
8
9
0
*
#
A
B
C
VII-22
MOSTEI{.
TELECOMMUNICATIONS
DTMF Receiver System
A DTMF receiver system with a low parts count may be
constructed using the MK5102 or MK5103 tone decoder
and the In 3040A and In 3041 A hybrid filter'. The In
3040A and In 3041 A filters have on-chip limiters so that
external squaring circuits are not needed. An alternate
design allowing precise adjustment of external squaring
circuits is described in another Mostek Application Note2.
Tables.1 and 2 show the MITEL (CM7290) tape results
using the In 3040A/41 A with the MK5102 and MK5103.
respectively.
NOTES:
(1)
(2)
ITT 3040A and ITT 3041 A filters with limiters may be obtained from:
ITT North Microsystems Division
700 Hillsboro Plaza
Deerfield Beach, Florida 33441
Telephone: 305-421-8450
TWX: 510-953-7523
MK51 02N-5 DTMF Decoder Application Note, "Design Considerations for a
DTMF Receiver System" is available from:
Mostek· Telecom Dept.
1215 W. Crosby Rd.
Carrollton, Texas 75006
Telephone: 214-323-6000
Figure 1
+5V
+12V
In
4
3041A
Limiter Out
MK5102
or
MK5103
High-Group
Filter
+5V
DTMF
Signal In
Ose 2
In
V+
High12
Group
Input
-12V
+5V
+5V
+12V
5
11
Ose 3
Out
4
~~
Format
LowGroup
Input
B
V-
6
In
3040A
4
Limiter Out
Low-Group
Filter
VII-23
A
9
10
m
3.579545
MHz
Strobe
!
4-Bit Binary
Output
MK5102 with ITT 3040A and ITT 3041.A
MITEL TAPE (CM7290) TEST RESULTS
Table 1
MK5103 with ITT 3040A and ITT 3041A
MITEL TAPE (CM7290) TEST RESULTS
Table 2
TEST #
RESULTS
TEST #
RESULTS
2a,b
BW = 4.7 % of fo
2a, b
BW = 5.3 % of fo
2c, d
BW = 4.8 % of fo
2c, d
BW = 5.2 % of fo
2e, f
BW = 5.4 % of fo
2e, f
BW = 5.0 % of fo
2g, h
BW = 4.9 % of fo
2g, h
BW = 5.4 % of fo
2i, j
BW = 5.3 % of fo
2i, j
BW = 5.6 % of fo
2k, I
BW = 5.4 % of fo
2k, I
BW = 5.3 % of fo
2m, n
BW = 5.6 % of fo
2m, n
BW = 5.4 % of fo
20, p
BW = 4.9 % of fo
20, p
BW = 5.6 % of fo
3
159 decodes
3
159 decodes
4
Acceptable Amplitude Ratio = 19.7 dB
4
Acceptable Amplitude Ratio = 19.9 dB
5
Dynamic Range = 25 dB
5
Dynamic Range = 30 dB
6
Guard Time = 32.9 ms
6
Guard Time = 23.3 ms
7
99.9% Successful Decode at SIN Ratio
of 12 dB
7
99.9% Successful Decode at SIN Ratio
of 12 dB
8
3 Hits on Talk-Off Test
8
9 Hits on Talk-OffTest
VII-24
1982 TELECOMMUNICATION PRODUCTS DATA BOOK
MOSTEI{.
TELECOMMUNICATION PRODUCTS
Active Speech Network
MK5242
FEATURES
PIN CONNECTIONS
o Direct telephone-line operation with no external power
supply
GND_1
o Minimum external parts count
1 5 ~ PREAMP OUT
RCVR OUT 2 -+- 3
14-+- MICIN
BALANCE -+- 4
13-+- DTMF
-5
v+_6
1 2 _ MUTE
o Interfaces directly with Mostek dialers
o Low voltage operation -
3.2 volts (Tip to Ring)
RCVRIN
o On-chip loop current regulation
RLOOP - + -
o Automatically adjusted equalization for loop-length
compensation
16-+- DRIVER IN
RCVR OUT 1 - + - 2
7
cLoo P - + - 8
11_VREG
10
9
N.C.
N.C.
o Direct interface to low-cost transducers
DESCRIPTION
The MK5242 is a monolithic integrated active speech
network manufactured using a bipolar process. The
MK5242 performs the 2-to-4 wire conversion function
typically accomplished using a hybrid transformer-type
speech network. In replacing the conventional speech
network. the MK5242 also provides the capability of
interface with low-cost transducers for the transmitter and
receiver.
The MK5242 is designed such that it may interface with
VIII-1
Mostek tone dialers with minimal external circuitry. It
provides a voltage regulated output for tone-dialer
applications which require fixed supply operation. The
MK5242 will also interface with Mostek pulse dialers.
The MK5242 operates directly from the telephone line with
no external power supply and requires a minimal amount of
external components. It features on-chip loop-current
regulation and will compensate for loop length with
automatically adjusted equalization.
VIII-2
1982 TELECOMMUNICATION PRODUCTS DATA BOOK
TELECOMMUNICATIONS
J-L-255 Law Companding CODEC
MK5116(J/P}
FEATURES
o
± 5-Volt Power Supplies
o
Low Power Dissipation - 30mW (Typ)
o
Follows the w255 Companding Law
o
Synchronous or Asynchronous Operation
o
On-Chip Sample and Hold
an 8kHz rate. A sync pulse input is provided for
synchronizing transmission and reception of multichannel information being multiplexed over a single
transmission line.
The pin configuration of the MK5116 is shown in
Figure 1.
PIN CONNECTIONS
Figure 1
o On-Chip Offset Null Circuit Eliminates Long-Term
o
Single 16-Pin Package
o
Minimal External Circuitry Required
o
o
1
16~+VREF
V+_2
15~-VREF
v-_3
14 ~ANALOG GROUND
ANALOG INPUT _
Drift Errors and Need for Trimming
Serial Data Output of 64kb/s-2.1 Mb/s at 8kHz
Sampling Rate
N/C -
4
13 _ANALOG OUTPUT
MASTER CLOCK -
5
12~
XMITSYNC _
6
11 ~ DIGITAL GROUND
XMIT CLOCK _
7
1 0 ~ RCV CLOCK
8
9~RCVSYNC
OIGITAL OUTPUT~
Separate Analog and Digital Grounding Pins Reduce
System Noise Problems
A block diagram of a PCM system using the MK5116 is
shown in Figure 2.
DESCRIPTION
PCM SYSTEM BLOCK DIAGRAM
Figure 2
The MK5116 is a monolithic CMOS companding
CODEC which contains two sections: (1) An analog-todigital converter which has a transfer characteristic
conforming to the JL-255 companding law and (2) a
digital-to-analog converter which also conforms to the
JL-255 law.
DIGITAL INPUT
r-------I
~:
~:
TRANSMITTER
(A/DI
FROM
{
OTHER
CHANNELS
I
I
These two sections form a coder-decoder which is
designed to meet the needs of the telecommunications
industry for percchannel voice-frequency codecs used
in telephone digital switching and transmission
systems. Digital input and output are in serial format.
Actual transmission and reception of 8-bit data words
containing the analog information is done at a 64kb/s2.1 Mb/s rate with analog signal sampling occuring at
RECEIVER
ID/AI
I
I
I
I
I
I
L
IX-1
~c~ E~~N~ _ _ _
FUNCTIONAL DESCRIPTION: (Refer to Figure 3 for
a Block Diagram)
XM IT SYNC, Pin 6 (Refer to Figure 10 for the Timing
Diagram)
MK5116 BLOCK DIAGRAM
Figure 3
This input is synchronized with XMIT CLOCK. When
XMIT SYNC goes high, the digital output is activated and
the AID conversion begins on the next positive edge of
MASTER CLOCK. The conversion by MASTER CLOCK
can be asynchronous with XMIT CLOCK. The serial
output data is clocked out by the positive edges of XMIT
CLOCK. The negative edge of XMIT SYNC causes the
digital output to become three-state. XMIT SYNC may
remain high longer than 8 XMIT CLOCK cycles, but must
go low for at least 1 master clock prior to the
transmission of the next digital word(Refer to Figure 12).
XMIT
SYNC
XMIT
CLOCK
-+--~J----/----[~~J
ANALOG
INPUT ~
XMIT CLOCK, Pin 7 (Referto Figure 1 0 fortheTiming
Diagram)
The on-chip 8-bit output shift register of the MK5116
is unloaded at the clock rate present on this pin. Clock
rates of 64kHz- 2.1 MHz can be used for XMIT CLOCK.
The positive edge of the INTERNAL CLOCK transfers the
data from the master to the slave of a master-slave flipflop (Refer to Figure 5). If the positive edge ofXMIT SYNC
occurs after the positive edge of XMIT CLOCK, XMIT
SYNC will determine when the first positive edge of
INTERNAL CLOCK will occur. In this event, the hold time
for the first clock pulse is measured from the positive
edge of XMIT SYNC.
MASTER
CLOCK
DIGITAL
INPUT
Rev,
SYNC
Rev.
",--LJL-.. ANALOG
CLOCK
RCV. SYNC, Pin 9 (Refer to Figure 11 for the Timing
diagram)
OUTPUT
RECEIVE
SECTION
This input is synchronized with RCV. CLOCKand serial
data is clocked in by RCV. CLOCK. Duration of the RCV.
SYNC pulse is approximately 8 RCV. CLOCK periods.
The conversion from digital-to-analog starts after the
negative edge of the RCV. SYNC pulse (Refer to Figure
4). The negative edge of RCV. SYNC should occur before
the 9th positive clock edge to insure that only eight bits
are clocked in. RCV. SYNC must stay low for 17
MASTER CLOCKS (min.) before the next digital word is
to be received (Refer to Figure 13).
POSITIVE AND NEGATIVE REFERENCE
VOLTAGES (+VREFand -V REF ) Pins 16 and 15
These inputs provide the conversion references for the
digital-to-analogconverters in the MK5116. +VREF and
-VREF must maintain 100ppM/oC regulation over the
operating temperature range. Variation of the reference
directly affects system gain.
RCV CLOCK, Pin 1 0 (Refer to Figure 11 for Timing
Diagram)
ANALOG INPUT, Pin 1
Voice-frequency analog signals which are bandwidthlimited to 4kHz are input at this pin. Typically, they are then
sampled at an 8kHz rate (Refer to Figure 4). The analog input
must remain between +VREF and -VREF for accurate
conversion. The recommended input interface circuit is
shown in Figure 9.
MASTER CLOCK, Pin 5
This signal provides the basic timing and control signals
required for all internal conversions. It does not have to
be synchronized with RCV. SYNC, RCV. CLOCK, XMIT
SYNC or XMIT CLOCK and is not internally related to
them.
The on-chip 8-bit shift register for the MK5116 is
loaded at the clock rate present on this pin. Clock rates
of 64kHz-2.1 MHz can be used for RCV. CLOCK. Valid
data should be applied to the digital input before the
positive edge of the internal clock (Refer to Figure 5).
This set up time, tRDS, allows the data to be transferred
into the MASTER of a master-slave flip-flop. The
positive edge of the INTERNAL CLOCK transfers the
data to the SLAVE of the master-slave flip-flop. A hold
time. tRDH, is required to complete this transfer. If the
rising edge of RCV. SYNC occurs after the first rising
edge of RCV. CLOCK, RCV. SYNC will determine when
the first positive edge of INTERNAL CLOCK will occur. In
this event. the set up and hold times for the first clock
pulse should be measured from the positive edge of
RCV. SYNC.
IX-2
A/D, D/A CONVERSION TIMING
Figure 4
~1
" " 1 ; - - - - - - - - - - - - - - - 1 2 5 ' " s e c - - - - - - - - - - - - '.
l.
_____-1,
XMIT SYNC
\'-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- - ' , - -
k--=15-20,"sec~
SAMPLE AND HOLi)\I
SAMPLE TIME
~--------------------------------------------------~
--------~
= 32 MASTER CLOCKS
I-I.-------
-N-A-B-L-E-S-A-RE
SAR REQUIRES
=128 MASTER CLOCKS
----------------------------------'1
RCV. SYNC
______________________________.--1
ANALOG OUTPUT UPDATED
DATA INPUT/OUTPUT TIMING
Figure 5
MK5116
Required For Data To Transfer
From Master to Slave
XMIT
Interhal
Clock
DIGITAL
OUT
XMIT SYNC
________.....Jx Valid Data
RCV
Internal
Clock
--l
-1
---.. . . .X'
I-
XMIT CLOCK
Required To Transfer Data
200ns From Master to Slave
DIGITAL
IN
I
RCV SYNC
RCV CLOCK
~ 50ns Required to Load Master
Valid Incoming Data
DIGITAL OUTPUT, Pin 8
The MK5116 output register stores the a-bit encoded
sample of the analog input. This a-bit word is shifted out
under control of XMIT SYNC and XMIT CLOCK. When
XMIT SYNC is low, the DIGITAL OUTPUT is an open
circuit. When XMIT SYNC is high, the state of the
DIGITAL OUTPUT is determined by the value of the
output bit in the serial shift register. The output is
composed of a Sign Bit, 3 Chord Bits, and 4 Step Bits.
The Sign Bit indicates the polarity of the analog input
while the Chord and Step Bits indicate the magnitude. I n
the first Chord, the Step Bit has a value of O.6mV. In the'
second Chord, the StE!P Bit has a value of 1 .2mV. This
doubling of the step value continues for each of the six
successive Chords.
Each Chord has a specific value and the Step Bits, 16 in
each Chord, specify the displacement from that va
(Refer to Table 1). Thus the output, which follows the
1-1-255 law, has resolution that is proportional to the
input level rather than to full scale. This provides the
resolution of a 12-bit AID converter at low input levels
and that of a 6-bit converter as the input approaches full
scale. The transfer characteristic of the A/D converter
(Wlaw Encoder) is shown in Figure 6.
IX-3
----
DIGITAL INPUT, Pin 12
DIGITAL OUTPUT CODE p,-LAW
Table 1
Chord Code
1. 000
2. 001
3. 010
4. 011
5. 100
6. 101
7. 110
8. 111
Chord Value
O.OmV
10.11 mV
30.3mV
70.8mV
151.7mV
313mV
637mV
1.284V
The MK5116 input register accepts the 8-bit sample
of an analog value and loads it under control of RCV.
SYNC and RCV. CLOCK. The timing diagram is shown in
Figure 11. When RCV. SYNC goes high, the MK5116
uses RCV. CLOCK to clock the serial data into its input
register. RCV. SYNC goes low to indicate the end of
serial input data. The 8 bits of the input data have the
same functions described for the DIGITAL OUTPUT. The
transfer characteristic of the 01 A converter (fL-law
Decoder) is shown in Figure 7.
Step Value
0.613mV
1.226mV
2.45mV
4.90mV
9.81 mV
19.61mV
39.2mV
78.4mV
EXAMPLE:
1
011
0010 = + 70.8mV + (2 x 4.90mV)
Sign Bit
Chord Step Bits
If the sign bit were a zero, then both plus signs would be
changed to minus signs.
AID CONVERTER (p,-Law Encoder) TRANSFER
CHARACTER ISTIC
Figure 6
1111 1111
The analog output is in the form of voltage steps (1 00%
duty cycle) having amplitude equal tothe analog sample
which was encoded. This waveform is then filtered with
an external low-pass filter with sinx/x correction to
recreate the sampled voice signal.
OPERATION OF CODEC WITH 64kHz XMIT IRCV
CLOCK FREQUENCIES
i.--'
1111 0000
ANALOG OUTPUT, Pin 13
11100000
11010000
XMITIRCV. SYNC must not be allowed to remain at a
logic "1" state. XMIT SYNC is required to be at a logic
"0" state for 1 master clock period (min.) before the next
digital word is transmitted. RCV. SYNC is required to be
at a logic "0" state for 17 master clock periods (min.)
before the next digital word is received (Refer to Figures
12 and 13).
11000000
1011 0000
1010 0000
1001 0000
.-
1O000000l
oooooooof
0001 0000
0010 0000
0011 0000
01000000
1
0101 0000
01100000
0111 0000
:,..- .....
01111111
-VREF
+VREF
2
-VREF
-2-
+VREF
ANALOG INPUT (VOLTS)
DI A CONVERTER (p,-Law Decoder)
TRANSFER CHARACTERISTIC
Figure 7
II
F
OFFSET NULL
The offset null feature of the MK5116 eliminates
long-term drift errors and conversion errors due to
temperature changes by going through an offset
adjustment cycle before every conversion, thus
guaranteeing accurate AID conversion for inputs near
ground. There is no offset adjust of the output amplifier
because, since the output is intended to be AC - coupled
to the external filter, the resultant DC error (VOFFSET 0)
will have no effect. The sign bit is not used to null the
analog input. Therefore, for an analog input of 0 volts,
the sign bit will be stable.
PERFORMANCE EVALUATION
ANALOG OUTPUT
(VOLTS)
LL
10
go g
§ §
,.-/'--.
o
o
o
o
o
o
0
0
0
0
0
0
The equipment connections shown in Figure 8 can be
used to evaluate the performance of the MK5116. An
analog signal provided by the HP3551 A Transmission
Test Set is connected to the Analog Input (Pin 1) of the
MK5116. The Digital Output of the CODEC is tied
back to the Digital Input and the Analog Output is fed
through a low-pass filter to the HP3551A. Remaining
pins of the MK5116 are connected as follows:
(1)
(2)
g ~
DIGITAL INPUTS
IX-4
RCV. SYNC is tied to XMIT SYNC
XMIT CLOCK is tied to MASTER CLOCK. The signal
is inverted and tied to RCV. CLOCK.
separated from XMIT CLOCK and MASTER CLOCK
should be separated from RCV. CLOCK. XMIT and RCV.
CLOCKS are separated also.
The following timing signals are required:
(1)
(2)
(3)
MASTER CLOCK = 1.536 MHz
XMIT SYNC repetition rate = 8kHz
XMIT SYNC width 8 XMIT CLOCK periods
=
When all the above requirements are met, the setup of
Figure 8 permits the measurement of synchronous
system performance over a wide range of analog inputs.
The data register and ideal decoder provide a means of
checking the encoder portion of the MK5116
independently of the decoder section. To test the system
in the asynchronous mode, MASTER CLOCK should be
Some experimental results obtained with the
MK5116 are shown in Figure 14 and Figure 15. In
each case, both the measured results and the
corresponding 03 Channel Bank specifications are
shown. The MK5116 exceeds the requirements for
Signal-to-Distortion ratio (Figure 14) and for Gain
Tracking (Figure 15).
SYSTEM CHARACTERISTICS TEST
CONFIGURATION
Figure 8
IDEAL
DECODER
~~~~~i' j-:';:.3_ _ _ _ _ _ _ _---<)\
I
SYSTEM
ENCODER
ONLY
I
I
I
L
1.004kHz
NOTCH
FILTER
FILTER
1 HP3551A
L __
SOUl + NOUT
NOTE: The ideal decoder consists of a digital decompander and a 13-bit precision OAC.
ABSOLUTE MAXIMUM RATINGS
DC Supply Voltage, V+ ............................................................................... +6V
DC Supply Voltage, V- ............................................................................... -6V
Ambient Operating Temperature, TA •••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• O°C to 70°C
Storage Temperature .................................................................... -55°C to +125°C
Package Dissipation at 25°C (Derated 9mW/oC when soldered into PCB) ............................ 500mW
Digital Input. ........................................................................... -0.5V :0;;; VIN :0;;; V+
Analog Input .............................................................................. V- :0;;; VIN :0;;; V+
+VREF ............................... '.' ............................................... -0.5V:o;;; +VREF :0;;; V+
-VREF ............................................................................... V- :0;;; -VREF:O;;; +O.5V
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliabilitv.
ELECTRICAL OPERATING CHARACTERISTICS
POWER SUPPLY REQUIREMENTS
SYM
PARAMETER
MIN
TYP
MAX
UNITS
V+
Positive Supply Voltage
4.75
5.0
5.25
V
V-
Negative Supply Voltage
-5.25
-5.0
-4.75
V
+VREF
Positive Reference Voltage
2.375
2.5
2.625
V
1
-VREF
Negative Reference Voltage
-2.625
-2.5
-2.375
V
1
IX-5
NOTES
TEST CONDITIONS: V+= 5.0V, V- = -5.0V, + VREF = 2.5V, -VREF = -2.5V, TA = O°C to 70°C
DC CHARACTERISTICS
UNITS
NOTES
2
k!l
2
Analog Input Resistance Non-Sampling
100
Mn
CINA
Analog Input Capacitance
150
250
pF
2
VOFFSET/I
Analog Input Offset Voltage
±1
±8
mV
2
ROUTA
Analog Output Resistance
20
50
n
10UTA
Analog Output Current
VOFFSET/O
Analog Output Offset Voltage
-200
± 850
mV
IINLOW
Logic Input Low Current (V1N = 0.8V)
Digital Input, Clock Input, Sync Input
± 0.1
±10
jJ.A
3
Logic Input High Current (VIN = 2.4V)
Digital Input, Clock Input, Sync Input
-0.25
-0.8
mA
3
8
12
pF
± 0.1
±10
JlA
0.4
V
4
V
4
SYM
PARAMETER
RINAS
Analog Input Resistance During Sampling
RINANS
IINHIGH
MIN
0.25
TYP
MAX
mA
0.5
Coo
Digital Output Capacitance
IDOL
Digital Output Leakage Current
VOUTLOW
Digital Output Low Voltage
VOUTHIGH
Digital Output High Voltage
1+
Positive Supply Current
4
10
mA
5
1-
Negative Supply Current
2
6
mA
5
IREF+
Positive Reference Current
.4
20
JlA
IREF-
Negative Reference Current
4
20
jJ.A
MIN
TYP
MAX
UNITS
1.5
1.544
2.1
MHz
0.064
1.544
2.1
MHz
3.9
AC CHARACTERISTICS (Refer to Figure 10 and Figure 11)
SYM
PARAMETER
FM
Master Clock Frequency
FR, Fx
XMIT~
PWCLK
Clock Pulse Width (MASTER, XMIT, RCV.)
tRC,tFC
Clock Rise, Fali Time(MASTER, XMIT; RCV.)
tRS, tFS
RCV.Clock Frequency
200
NOTES
ns
Sync Rise, Fall Time (XMIT, RCV.)
25% of
PWCLK
ns
25% of
PWcLi<
'ns
25% of
PWCLK
ns
tOIR; tOIF
Data Input Rise, Fall Time
twsx, tWSR
Sync Pulse Width (XMIT RCV.)
FX(FR)
Jls
tps
Sync Pulse Period (XMIT; ::CV.)
125
jJ.s
txcs
XMIT Clock-to-XMIT Sync Delay
8
50% of
tFC (tRS)
IX-6
ns
6
AC CHARACTER ISTICS (Refer to Figure 10 and Figure 11)
TYP
MAX
UNITS
NOTES
SYM
PARAMETER
MIN
tXCSN
XMIT Clock-to-XMIT Sync (Negative Edge) Delay
200
ns
txss
XMIT Sync Set-Up Time
200
ns
boo
XMIT Data Delay
0
200
ns
4
txop
XMIT Data Present
0
200
ns
4
txoT
XMIT Data Three State
150
ns
4
tOOF
Digital Output Fall Time
50
100
ns
4
tOOR
Digital Output Rise Time
50
100
ns
4
tSRC
RCV. Sync-to-RCV. Clock Delay
50% of
tRC (tFS)
ns
6
50
ns
7
7
tROS
RCV. Data Set-Up Time
tROH
RCV. Data Hold Time
200
ns
tRCS
RCV. Clock-to-RCV. Sync Delay
200
ns
tRSS
RCV. Sync Set-Up Time
200
ns
tSAO
RCV. Sync-to-Analog Output Delay
7
J.ls
SLEW+
Analog Output Positive Slew Rate
1
V/J.ls
SLEW-
Analog Output Negative Slew Rate
1
V/J.ls
DROOP
Analog Output Droop Rate
25
J.lV/J.ls
7
SYSTEM CHARACTERISTICS (Refer to Figures 14 and 15)
SYM
PARAMETER
SID
Signal-to-Distortion Ratio
GT
Gain Tracking
TYP
35
29
24
39
34
29
-0.4
-0.8
-2.5
±0.1
±0.1
±0.2
+0.4
+0.8
+2.5
dB
dB
dB
18
dBrncO
Nlc
Idle Channel Noise
10
TLP
Transmission Level Point
+4
NOTES:
1. +VAEF and -VREF must be matched within ± 1 % in order to meet system
requirements.
2.
MAX
UNITS TEST CONDo
MIN
dB
dB
dB
dB
Analog
Input~O
Analog
Input~-40dBmO
Analog
Input~-45dmO
Analog
Input~+3
Analog
Input~-37
to -50dBmO
Analog
Input~-50
to -55dBmO
Analog
Input~O
to -30dBmO
to -37dBmO
Volts; note 2
600n
RECOMMENDED ANALOG INPUT CIRCUIT
Figure 9
COOEC
Sampling is accomplished by charging an internal capacitor; therefore, the
designer ShOll'::'; avoid excessive source impedance. Input related device
lYPICAL
characteristics are derived using the Recommended Analog Input Circuit.
See Figure 9.
SOURCE I
1~"': i'
3. When a transition from a "'''to a "O"takes place, the user must sink the .""
current until reaching the "0" level.
4. Driving 30pF with IOH = -1 OO~A. IOL
= 500~A.
5.
Results in 30 mW typical power dissipation (clocks applied) under normal
operating conditions.
6. This delay is necessary to avoid overlapping CLOCK and SYNC.
7. The first bit of data is loaded when the Sync and Clock are both "1" during bit
time 1 as shown on ReV. timing diagram.
'V
I
-
I
I
I
I
I
IX-7
C INA. RINAS
1
3K
TRANSMITTER SECTION TIMING
Figure 10
I··-------------------------------twsx------------------------------~
2.4V
XMIT SYNC
XMIT
CLOCK
NOT VALID
V
PCM DATA PRESENT
NOTE: All rise and fall times are measured from O.4V and 2,4V, All delav times are measured from 1.4V.
RECEIVER SECTION TIMING
Figure 11
RCV
CLOCK
r-
----------------------------~\
L
ANALOG OUTPUT
NOTE: All rise and fall times are measured from O.4V and 2.4V. All delav times are measured from 1.4V.
IX-8
64kHz OPERATION, TRANSMITTER SECTION TIMING
Figure 12
~1.~======================================_1_2_5_p_s_ec_-_-~_-_-~~_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-~_-_-_-_-_-_-_-_-~~~.I
I
-.J
I r--U
~ ~CLOCK
XMIT SYNC
1 MASTER
~I 1-
PERIOD
XMIT
CLOCK
(MIN)
r::::\
" THREE
STATE
THREE
I
SIGN BIT
MSB
S~\INEXT WORDI
l~
____________________~
V
PCM DATA PRESENT
NOTE: All rise and fall times are measured from O.4V and 2.4V. All delay times are measured from 1.4V.
64kHz OPERATION, RECEIVER SECTION TIMINGI
Figure 13
1~·'-----------------------------------__ 125psec ______________________________________~.~I
I ~STER
L.--J ~;~~~
.J
I :CV SYNC
~
I~PERIODS
~
r---IMIN)
RCV
NOTE: All rise and fall times are measured from O.4V and 2.4V. All delav times are measured from 1.4V.
MK5116 SID RATIO VS: INPUT LEVEL
MK5116 GAIN TRACKING PERFORMANCE
Figure 14
Figure 15
03 CHANNEL BANK SPECS
INPUT LEVElldBmOI
tNPUT lEVEL ldBmOI
IX-9
IX-10
MOSTEI{.
TELECOMMUNICATIONS
1L-255 Law Companding CODEC
MK5151 (J/P)
FEATURES
o ±5-Volt Power Supplies
o Low Power Dissipation - 30mW (Typ)
o Follows the J.L-255 Companding Law
o Zero Code Suppression and Sign-Magnitude Data
Format
an 8kHz rate. A sync pulse input is provided for
synchronizing transmission and reception of multichannel information being multiplexed over a single
transmission line.
The pin configuration of the MK5151 is shown in Figure
1.
PIN CONNECTIONS
Figure 1
o On-Chip Sample and Hold
XMIT CLOCK--"2
AlB SEL (XMIT)_3
o On-Chip Offset Null Circuit Eliminates Long-Term
Drift Errors and Need forTrimming
22"-MASTER CLOCK
B SIGNAL IN_4
21"-V+
A SIGNAL IN_5
20"-ANALOG INPUT
RCV.SYNC_6
o Single 24-Pin Package
19---+VREF
18---- V REF
17 ___ ANALOG GROUND
RCV. CLOCK_7
AlB SEL. (RCV.)_8
o Minimal External Circuitry Required
o Serial Data Output of 64kb/s - 2.1 Mb/s at 8kHz
Sampling Rate
24-N/C
2:J..-XMIT SYNC
DIGITAL OUTPUT_I
A SIGNAL OUT_9
16-N/C
B SIGNAL OUT..-IO
15-N/C
DIGITAL INPUT-..ll
14-"ANALOG OUTPUT
13..-v-
DIGITAL GROUND-..12
o Separate Analog and Digital Grounding Pins Reduce
System Noise Problems
DESCRIPTION
The MK5151 is a monolithic CMOS companding
CODEC which contains two sections: (1) An analog-todigital converter which has a transfer characteristic
conforming to the w255 companding law and (2) a
digital-to-analog converter which also conforms to the
w255 law.
A block diagram of a PCM system using the MK5151 is
shown in Figure 2.
PCM SYSTEM BLOCK DIAGRAM
Figure 2
r-------I
. :
g]£J
,
!:'t't
, ."
t::t
These two sections form a coder-decoder which is
designed to meet the needs of the telecommunications
industry for per-channel voice-frequency codecs used
in telephone digital switching and transmission
systems. Digital input and output are in serial format.
Actual transmission and reception of 8-bit data words
containing the analog information is done at a 64kb/s2.1 Mb/s rate with analog signal sampling occuring at
TAANSMITIER
I
I
DIGITAL
TAUNK
(AID)
I
RECEIVER
I
lOlA)
I
I
OIGITAl
EMUX
I
I
I
~ L~~ E~H~'::
IX-11
__ _
DIGITAL
tRUNK
FUNCTIONAL DESCRIPTION: (Refer to Figure 3 for
a Block Diagram)
XMIT SYNC. Pin 23 (Refer to Figure 12 for the
Timing Diagram)
MK5151 BLOCK DIAGRAM
Figure 3
This input is synchronized with XMIT CLOCK. When
XMIT SYNC goes high, the digital output is activated and
the AID conversion begins on the next positive edge of
MASTER CLOCK. The conversion by MASTER CLOCK
can be asynchronous with XMIT CLOCK. The serial
output data is clocked out by the positive edges of XMIT
CLOCK. The negative edge of XMIT SYNC causes the
digital output to become three-state. XMIT SYNC must
go low for at least 1 master clock prior to the
transmission of the next digital word. (Refer to Figure
14).
XMIT
SYNC
XMIT
CLOCK
ANALOG_-I_ _ _
INPUT
--l~--__1_--_l;;_;~:r
XM IT CLOCK. Pin 2 (Refer to Figure 12 for the Timing
Diagram) .
AlB SEL.
(XMIT!
The on-chip 8-bit output shift register of the MK5151 is
unloaded at the clock rate present on this pin. Clock
rates of 64kHz -2.1 MHz can be used for XMIT CLOCK.
The positive edge of the INTERNAL CLOCK transfers the
data from the master to the slave of a master-slave flipflop(Referto Figure 5). If the positive edge ofXMIT SYNC
OCCl:lrs after the positive edge of XMIT CLOCK, XMIT
SYNC will determine when the first positive edge of
INTERNAL CLOCK will occur. In this event, the hold time
for the first clock pulse is measured from the positive
edge of XMIT SYNC.
MASTER
CLOCK
AlB SEl.
(RCVJ
DIGITAL---oll_~~~J
INPUT
Rev,
SYNC
ANALOG
OUTPUT
Rev
RCV. SYNC. Pin 6 (Refer to Figure 13 for the timing
diagram)
CLOCK
B SIG, A SIG
OUT
OUT
POSITIVE AND NEGATIVE REFERENCE
VOLTAGES (+VREF and -VREF) Pins 19 and 18
These inputs provide the conversion references for the
digital-to-analog converters in the MK5151 . +VREF and
-VREF must maintain 100ppM/oC regulation over the
operating temperature range. Variation ofthe reference
directly affects system gain.
This input is synchronized with RCV. CLOCK and serial
data is clocked in by RCV. CLOCK. Duration of the RCV.
~YNC pulse is approximately 8 RCV. CLOCK periods.
The conversion from digital-to-analog starts after the
negative edge of the RCV. SYNC pulse (Refer to Figure
4). The negative edge of RCV. SYNC should occur before
the 9th positive clock edge to insure that only eight bits
are" clocked in. RCV. SYNC must stay low for 17
MASTER CLOCKS (min.)'before the next digital word is
to be received (Refer to Figure 15).
RCV CLOCK. Pin 7 (Refer to Figure 13 for Timing
Diagram)
ANALOG INPUT. Pin 20
Voice-frequency analog signals which are bandwidthlimited to 4kHz are input at this pin. Typically, they are
then sampled at an 8kHz rate (Refer to Figure 4.). The
analog input must remain between +VREF and ~VREF
for accurate conversion. The recommended input interface
circuit is shown in Figure 11.
MASTER CLOCK. Pin 22
This signal provides the basic timing and control signals
required for all internal conversions. It does not have to
be synchronized with RCV. SYNC, RCV: CLOCK, XMIT
SYNC or XMIT CLOCK and is not internally related to
them.
The on-chip 8-bit shift register for the MK5151 is loaded
at the clock rate present on this pin. Clock rates of
64kHz-2.1 MHz can be used for RCV. CLOCK. Valid data
should be applied to the digital input before the positive
edge of the internal clock (Refer to Figure 5). This set up
time, tRlls, allows the data to be transferred into the
MASTER of a master-slave flip-flop. The positive edge of
the INTERNAL CLOCK transfers the data to the SLAVE
of the master-slave flip-flop. A hold time, tRI>H. is
required to complete this transfer. If the rising edge of
RCV. SYNC occurs after the first rising edge of RCV.
CLOCK, RCV. SYNC will determine when the first
positive edge of INTERNAL CLOCK will occur. In this
IX-12
AID, DIA CONVERSION TIMING
Figure 4
~1~·E------------------------------125Msec----------------------------~~~1
__-,T
r-
\I...._________--'---_____________
XMIT SYNC
k--=15-20MSeC ~
SAMPLE AND HOLD
\1
________~
SAMPLE TIME
= 32 MASTER CLOCKS
~--------------------~----------------------------~
~......._______________
ENABLE SAR
SAR REQUIRES
=128 MASTER CLOCKS
----------------~------------~/
__________________________________________________________-J/
RCV.SYNC
ANALOG OUTPUT UPDATED
DATA INPUT IOUTPUT TIMING
Figure 5
Required For Data To Transfer
From Master to Slave
XMIT
Internal
Clock
I
MK5151
DIGITAL
OUT
I
XMIT SYNC
- - - - , , - - - -
________________--'X
Rev.
I
-t
Internal
Clock
I
---------.X
Valid Data
t-
XMIT CLOCK
Required To Transfer Data
200ns From Master to Slave
DIGITAL
IN
RCV SYNC
_
~50ns Required to Load Master
RCV CLOCK
Valid Incoming Data
DIGITAL OUTPUT, Pin 1
while the Chord and Step Bits indicate the magnitude. In
the first Chord, the Step Bit has a value of O.6mV. In the
second Chord, the Step Bit has a value of 1.2rriV. This
doubling of the step value continues for each of the six
successive Chords.
The MK5151 output register stores the 8-bit encoded
sample of the analog input. This 8-bit word is shifted out
under control of XMIT SYNC and XMIT CLOCK. When
XMIT SYNC is low, the DIGITAL OUTPUT is an open
circuit. When XMIT SYNC is high, the state of the
DIGITAL OUTPUT is determined by the value of the
output bit in the serial shift register. The output is
composed of a Sign Bit, 3 Chord Bits, and 4 Step Bits.
The Sign Bit indicates the polarity of the analog input
Each Chord has a specific value and the Step Bits, 16 in
each Chord, specify the displacement from that value
(Refer to Table 1). Thus the output, which follows the
1L-255 law, has resolution that is proportional to the
input level rather than to full scale. This provides the
resolution of a 12-bit AID converter at low input levels
and that of a 6-bit converter as the input approaches full
scale. The transfer characteristic of the AID converter
(IL-Iaw Encoder) is shown in Figure 6.
event, the set-up and hold times for the first clock pulse
should be measured from the positive edge of RCV.
SYNC.
IX-13
DIGITAL OUTPUT CODE p.-LAW
Table 1
1.
2.
3.
4.
5.
6.
7.
8.
DIGITAL INPUT, Pin 11
Chord Value
O.OmV
10.11mV
30.3mV
70.8mV
151.7mV
313mV
637mV
1.284V
Chord Code
111
110
101
100
all
010
001
000
The MK5151 input register accepts the 8-bit sample of
an analog value and loads it under control of RCV. SYNC
and RCV. CLOCK. The timing diagram is shown in
Figure 13. When RCV. SYNC goes high, the MK5151
uses RCV. CLOCK to clock the serial data into its input
register. RCV. SYNC goes low to indicate the end of
serial input data. The 8 bits of the input data have the
same functions described for the SERIAL OUTPUT. The
transfer characteristic' of the 01 A converter (Il-Iaw
Decoder) is shown in Figure 7.
Step Value
0.613mV
1.226mV
2.45mV
4.90mV
9.81mV
19.61mV
39.2mV
78.4mV
EXAMPLE:
1
100 1101= +70.8mV + (2 x 4.90mV)
Sign Bit
Chord Step Bits
If the sign bit were a zero, then both plus signs would be
changed to minus signs.
AID CONVERTER (p.-Law Encoder) TRANSFER
CHARACTERISTIC
Figure 6
1000 0000
I I...-
1000 1111
ANALOG OUTPUT, Pin 14
The analog output is in the form of voltage steps (1 00%
duty cycle) having amplitude equal tothe analog sample
which was encoded. This waveform is then filtered with
an external low-pass filter with sinxlx correction to
recreate the sampled voice signal. When the 8th bit of
the word is a signalling bit, it is assigned a value of Vz
step. This results in a lower system quantization error
rate than would result if the bit were arbitarily set to
(no step) or 1 (full step).
a
1001 1111
OPERATION OF CODEC WITH 64kHz XMiT/RCV.
CLOCK FREQUENCIES
10101111
101' , " 1
"Oa 1111
....
'"
ii:....
1101 1111
5'11111111,}
~ 0111111'1
....
G
o
XMITIRCV. SYNC must not be allowed to remain at a
logic "1" state. XMIT SYNC is required to be at a logic
"0" state for 1 master clock period (min.) before the next
digital word is transmitted. RCV. SYNC is required to be
at a logic "0" state for 17 master clock periods (min.)
before the next digital word is received (Refer to Figures
14 and 15).
.
11101111
01101111
01011111
0100" 11
1
II
aOl1 " 11
DOlO 1111
00011",
1/
ODoa ,,,,
AlB SIGNAL IN, Pins 4 and 5
L..-
0000 DOXX
SIGNALING =l,XX=Ql
SIGNALING'" D. XX 10
NO SIGNALLING, XX = 10
-V REF
=
.V
-V
......B.ll
-..!ll£... 'V REF
2
2
ANALOG INPUT (VOL lSI
01 A CONVERTER (p.-Law Decoder) TRANSFER
CHARACTERISTIC
Figure 7
+VREF
These two pins allow insertion of signalling information
into the transmitted data stream. The inserted
information occurs as the 8th bit (LSB) in the
transmitted word. A positive transition occuring on AlB
SEL (XMIT) selects A SIGNAL IN while a negative
transition selects B SIGNAL IN.
AlB SIGNAL OUT, Pins 9 and 10
+VREF
2
ANALOG OUTPUT
(VOLTS)
These two pins are provided to output ·received
signalling information. A positive transition on AlB SEL
(RCV.) routes the signal bit to A SIGNAL OUT while a
negative transition routes the signal bit (bit 8) to B
SIGNAL OUT. Refer to Figure 8.
0
AlB SEL (XMIT), Pin 3
8
g
g
xx "
SIGNALING'" "
01
SIGNALING co D, XX:: 10
NO SIGNALLING, XX", 10
This input selects either A SIGNAL IN or B SIGNAL IN as
described in the AlB SIGNAL IN paragraph above, and
should be changed only at the start of the 6th and 12th
frames as shown in Figure 9.
;;::
DIGITAL INPUTS
IX-14
OFFSET NULL
The offset null feature of the MK5151 eliminates longterm drift errors and conversion errors due to
temperature changes by going through an offset
adjustment cycle before every conversion, thus
guaranteeing accurate AID conversion for inputs near
ground. There is no offset adjust of the output amplifier
because, since the output is intended to be AC - coupled
to the external filter, the resultant DC error (VOFFSET/O)
will have no effect. The sign bit is not used to null the
analog input. Therefore, for an analog input of 0 volts,
the sign bit will be stable.
AlB SELECT TIMING
Figure 8
- - - -- - - , r - - - - - - - - - - - XMIT SYNC,
TIME SLOT 1
I.
TIME SLOT 24
11.4V
------'1'- - - - - - - -
- - - - - -
XMIT
CLOCK
1.4V
PERFORMANCE EVALUATION
AlBIN
-- - - - -, r-----------,
TIME SLOT 24
~
- - --
1.4V RCV. SYNC, TIME SLOT 1 I
_ _ _ _ _- 1I' - _ _ _ _ _ _ _ _ _ ...1'--_ __
The equipment connections shown in Figure 10 can be
used to evaluate the performance of the MK5151. An
analog signal provided by the.HP3551A Transmission
Test Set is connected to the Analog Input (Pin 20) of the
MK5151. The Digital Output of the CODEC is tied back
to the Digital Input and the Analog Output is fed through
a low-pass filter to the HP3551 A. Remaining pins ofthe
MK5151 are connected as follows:
(1)
(2)
(3)
RCV. SYNC is tied to XMIT SYNC.
XMIT CLOCK is tied to MASTER CLOCK. The signal
is inverted and tied to RCV. CLOCK.
The following timing signals are required:
1.4V
AlB SELECT RCV.
AlB SEL. (RCV.) is tied to AlB SEL. (XMIT).
1.4V
A,.S!GNAL OUT OR B SIGNAL OUT
(1). MASTER CLOCK = 1 .536 MHz
(2) XMIT SYNC repetition rate = 8kHz
(3) XMIT SYNC width = 8 MASTER CLOCK periods
SIGNALLING TIMING REQUIREMENTS FOR
PERFORMANCE EVALUATION
Additional timing signals are shown in Figure 9.
Figure 9
When all the above requirements are met, the setup of
Figure 10 permits the measurement of synchronous
system performance over a wide range of analog inputs.
The data register and ideal decoder provide a means of
checking the encoder portion of the MK5151
independently of the decoder section. To test the system
in the asynchronous mode, MASTER CLOCK should be
separated from XMIT CLOCK and MASTER
should be separated from RCV. CLOCK. XMIT CLOCK
and RCV. CLOCK are separated.also.
•
12
Rev, SYNC
I I
I II I
12
I
I
A SIGNAL IN
B SIGNAL IN
AlB SEL (RCV.). Pin 8
. , .'
.
,
Some experimental results obtained with the MK5151
are shown in Figure 16 and Figure 17.ln each case, both
the measured results and the corresponding, D3
Channel Bank specifications are shown. The MK5151
exceeds the requirements for Signal-to-Distortion ratio
(Figure 17) and for Gain Tracking (Figure 16).
This input routes the signalling bit, bit 8, either to A
SIGNAL OUT or to B SIGNAL OUT as described in the
AlB SIGNAL OUT paragraph above; and should be
changed only at the start of the 6th and 12th frames as
shown in Figure 9.
IX-15
SYSTEM CHARACTERISTICS TEST
CONFIGURATION
Figure 10
r- I
- -
-
l
I
1.004 kHz
DIGITAL
INPUT DIGITAL
OUTPUT
DATA
REGISTER
IDEAL
DECODER
MK5151
20
I
~
ANALOG
INPUT
SIGNAL
SOURCE
;
I
I
I
I
I
I
L -- - l
I
I
I
I
IH P3551 A
L - - ------ J
ANALOG
OUTPUT
N
_
OUT
14
~
~
ENCODER
ONLY
SYSTEM
1.004 kHz
FILTER
NOTCH
FILTER
SOUT + NOUT
NOTE: The ideal decoder consists of a digital decompander an::.d::.a..:,:'3::,:-.::::bi:!,!tp~r:::ec:::is:::io:::n:..::D:::A::::C,--,_ _ _ _ _ _ _ _ _ _ _.:..-_ _ _--,-_ _ _ __
ABSOLUTE MAXIMUM RATINGS
DC Supply Voltage, V+ _: ...... '...... : ..........•..........................•.....•.........• _•........ +6V
DC Supply Voltage, V- . '.' .......•.......................•....................•....•........ _..•...... -6V
Ambient Operating Temperature, TA •••••••••••••••••••••••••••••••••••••• ; ••••• _ ••••••••••••••• _ .O°C to 70°C
Storage Temperature •..•......•.. ',' •... , •.....•........•........ _........ __ . _..••....... -55°C to +125°C
Package Dissipation at 25°C(Derated 9mW/oC when soldered into PCB) .... _................. _..... 500mW
Digital Input .•.. ~ ...... '.' ................ __ ......................... _.............. __ .... -D.5V ::; VIN ::; V+
Analog Input. __ • : .. _•....•.... _......... _..•••........ _......... ; •.........•..... _. _..... V- ::; +VIN ::; V+
+VREF' - . - - . '.' ........•••...•..•.... - ....•••......•••....•...•......... .' ..••••..•.•.. -D.5V ::; +VREF ::; V+
-VREF . - ..•..........•' •••...•.. - ....•... - - - ...... - . - ........ - ..................... '.' -.. V- ::; -VREF ::; 0.5V
Stresses above those listed under "AbsoliJte Maximum Ratings" may cause: permanent damage to the deVice. This is' a stress rating only and functional operationaf
the device at these or any other condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods ~ay affect device reliability.
ELECTRICAL OPERATING CHARACTERISTICS
POWER SUPPLY REQUIREMENTS
SYM
PARAMETER
MIN
MAX
UNITS
V+
Positive Supply Voltage
4,75
5.0 '
5.25
V
V-
Negative Supply Voltage
-5,25
-5.0
-4.75
V
2.375
2.5
2.625
V
1
~2.625
-2,5
-2.375
V
1
TYP
NOTES
.'
+VREF
Positive Reference Voltage
-VREF
Negative Reference Voltage
TESTCONDITIONS:V+= 5.0 V, V- =:-5.0 V, + VREF = 2.5 V, -VREF = -2.5 V, TA = O°C to 70°C
DC CHARACTERISTICS
'
SYM
PARAMETER
RINAS
Analog Input Resistance During Sampling
RINANS
CINA
MIN
TYP
MAX UNITS
2
kO
Analog Input Resistance Non-Sampling
100
'MO
Analog Input Capacitance
150
IX-16
250
pF
NOTES
2
..
2
DC CHARACTERISTICS CONTINUED
PARAMETER
VOFFSETII
Analog Input Offset Voltage
±1
±8
mV
ROUTA
Analog Output Resistance
20
50
.n
IOUTA
Analog Output Current
VOFFSET/O
Analog Output Offset Voltage
-200
±850
mV
IINLOW
Logic Input Low Current (V IN = 0.8V)
Digital Input, Clock Input, Sync Input
±0.1
±10
p.A
3
Logic Input High Current (V IN = 2.4V)
Digital Input, Clock Input, Sync Input
-0.25
-0.8
mA
3
8
12
pF
±0.1
±10
p.A
0.4
V
4
V
4
IINHIGH
Coo
MIN
0.25
Digital Output Capacitance
IOOL
Digital Output Leakage Current
VOUTLOW
Logic Output Low Voltage
Digital Output. AlB Signal Out
TYP
MAX UNITS
SYM
NOTES
2
mA
0.5
VOUTHIGH
Logic Output High Voltage
Digital Output, AlB Signal Out
1+
Positive Supply Current
4
10
mA
5
1-
Negative Supply Current
2
6
mA
5
IREF+
Positive Reference Current
4
20
p.A
IREF-
Negative Reference Current
4
20
p.A
3.9
AC CHARACTERISTICS (Refer to Figure 12 and Figure 13)
SYM
PARAMETER
FM
Master Clock Frequency
FR, Fx
Receive, Transmit Clock Frequency
PW CLK
Clock Pulse Width (MASTER, XMIT, RCV.)
t RC
Clock Rise Time (MASTER, XMIT, RCV.)
tRS,tFS
t OIR ' tOIF
TYP
1.5
1.544
2.1
MHz
0.064
1.544
2.1
MHz
Sync Fall, Rise Time (XMIT, RCV.)
Digital Input Rise, Fall Time
Sync Pulse Period (XMIT, RCV.)
NOTES
ns
200
t wsx, t WSR Sync Pulse Width (XMIT, RCV.)
tps
MAX UNITS
MIN
25% of
PWCLK
ns
25% of
PW CLK
ns
25% of
PWCLK
ns
8
Fx(FR)
p's
125
p's
50%of
t FC (t RS )
ns
t xcs
XMIT Clock-to-XMIT Sync Delay
txcsN
XMIT Clock-to-XMIT Sync (Negative Edge) Delay
200
ns
t xss
XMIT Sync Set-Up Time
200
ns
t xoo
XMIT Data Delay
0
200
ns
4
t XDP
XMIT Data Present
0
200
ns
4
t XOT
XMIT Data Three State
150
ns
4
tOOF
Digital Output Fall Time
50
100
ns
4
tOOR
Digital Output Rise Time
50
100
ns
4
IX-17
6
AC CHARACTERISTICS CONTINUED (Refer to Figure 12 and 13)
SYM
PARAMETER
t SRC
RCV. Sync-to-RCV. Clock Delay
t RDS
MIN
TYP
MAX UNITS
NOTES
50% of
t RC (t FS )
ns
6
RCV. Data Set-Up Time
50
ns
7
7
tRDH
RCV. Data Hold Time
200
ns
t RCS
RCV. Clock-to-RCV. Sync Delay
200
ns
tRSS
RCV. Sync Set-Up Time
200
ns
t SAO
RCV. Sync-to-Analog Output Delay
tA/BI
AlB Signalling Input Setup Time
tA/BSH
AlB Select Hold Time
200
ns
tA/BSS
AlB Select Setup Time
400
ns
tAIBa
AlB Signalling Output Delay
SLEW+
Analog Output Positive Slew Rate
1
V/}J.s
SLEW-
Analog Output Negative Slew Rate
1
V/}J.s
DROOP
Analog Output Droop Rate
25
}J.V/}J.s
7
}J.S
200
200
7
400
ns
ns
SYSTEM CHARACTERISTICS (Refer to Figures 16 and 17)
SYM
PARAMETER
SID
Signal-to-Distortion Ratio
GT
Gain Tracking
NIC
TLP
MIN
TYP
35
29
24
39
34
29
-0.4
-0.8
-2.5
±0.1
±0.1
±0.2
Idle Channel Noise
10
Transmission Level Point
+4
NOTES:
1.
+VREF and -VREF must be matched within ± 1% in orderto meet system
requirements.
.
2.
Sampling is accomplished bycharging an internal capacitor; therefore, the
designer should avoid excessive source impedance. Input related device
characteristics are derived using the Recommended Analog Input Circuit.
See Figure 11.
3.
When a transistion from a '" "to a "0" takes place, the user must sink the
4.
5.
6.
7.
MAX
TESTCOND.
UNITS
dB
dB
dB
Analog Input=O to -30dBmO
Analog Input=-40dBmO
Analog Input=-45dmO
+0.4
+0.8
+2.5
dB
dB
dB
Analog Input=+3 to -37dBmO
Analog Input=-37 to -50dBmO
Analog Input=-50 to -55dBmO
18
dBrncO
Analog Input 0 Volts
Note 2
dB
6000.
RECOMMENDED ANALOG INPUT CIRCUIT
Figure 11
"1" current until reaching the "0" level.
Driving 30pF with IOH = -100MA. IOL = 500MA.
Results in 30 mW typical po;wer dissipation (clocks applied) under normal
operating conditions.
This delay is necessary to avoid overlapping CLOCK and SYNC.
The first bit of data is loaded when the Sync and Clock are both "1 "during
bit time 1 as shown on RCV timing diagram.
r
TYPICAL
C INA, RINAS
SOURCE
"::"
IX-18
CODEC
ANe
,: '(
I
3K
I
I
I
I
2K
~ 150pf
TRANSMITTER
SECTION TIMING
Figure 12
2.4V
1.4V
PCM DATA PRESENT
NOTE! All rIse and fall times are measured from Q.4V .tnd 2,4V
All delay times are measured from '.4V.
RECEIVER SECTION TIMING
Figure 13
RCV SYNC
RCV
CLOCK
I
A~~N~A~L~O~G~O~U=T=P~U=T--------------------------------------------------------------------------------------------~'"_
NOTE: All rise & fall times are measured from O.4V and 2.4V. All delay times are
measured from 1.4V.
IX-19
64kHz OPERATION. TRANSMITTER SECTION TIMING
Figure 14
__
~1~ ----------------------------------125Psec----------------------------------~~~1______
I
~
U
XM!TSYNC
1 MASTER
- - ' i..--CLOCK
. - I IPERIOD
I..--- PWCLK
IXMIT
CLOCK
l
V
PCM DATA PRESENT
NOTE: All rise and fall times are measured from O.4V and 2.4V. All delay times are
measured from 1.4V.
64kHz OPERATION. RECEIVER SECTION TIMING
. Figure 15
__
1~~ ------------------------------------125~sec----------------------__----------------~
~
RCVSYNC
NOTE: All rise and fall times are measured from O.4V and 2.4V. All delay times are
measured from' .4V.
17 MASTER
MK5151 GAIN TRACKING PERFORMANCE
MK5151 SID RATIO VS. INPUT LEVEL
Figure 16
Figure 17
z
o
~
"2
INPUT LEVEL IdBmOI
MKS151
INPUT LEVEL Id8mOI
IX-21
IX-22
MOSTEI(@
TELECOMMUNICATIONS
A-Law Companding CODEC
MK5156(J/P)
FEATURES
is provided for synchronizing transmission and reception of
multi-channel information being multiplexed over a single
transmission line.
o
±5-Volt Power Supplies
o
Low Power Dissipation - 30mW (Typ)
o
Follows the A-Law Companding Code
o
Includes 'CCITT
Inversion
o
Synchronous or Asynchronous Operation
o
On-Chip Sample and Hold
o
On-Chip Offset Null Circuit Eliminates Long-Term
Drift Errors and Need for Trimming
Recommended
The pin configuration of the MK5156 is shown in
Figure 1.
PIN CONNECTIONS
Figure 1
Even-Order-Bit
ANALOG INPUT
o
_1
16 -+vREF
15--V REF
14 _ANALOG
Vt_2
v-_3
N/C
-4
MASTER CLOCK
-+5
XMIT SYNC
-.6
Single 16-Pin Package
13 ANALOG OUTPUT
12_ DIGITAL INPUT
11_ DIGITAL GROUND
1 0 - RCV
-.7
OIGITAL OUTPUT- 8
XMIT CLOCK
o
Minimal External Circuitry Required
o
Serial Data Output of 64kb/s-2.1 Mb/s at 8kHz
Sampling Rate
GROUND
9
CLOCK
_RCVSYNC
0' Separate Analog and Digital Grounding Pins Reduce
System Noise Problems
'
A block diagram of a PCM system using the MK5156 is
shown in Figure 2.
PCM SYSTEM BLOCK DIAGRAM
DESCRIPTION
The MK5156 is a monolithic CMOS companding
CODEC which contains two sections: (1) An a~aiog-to
digital converter which has a transfer characteristic
conforming to the A-law companding code and (2) a
digital-to-analog converter which iilso conforms to the
A-law code.
Figure 2
These two sections form a coder-decoder which is designed
to meet the needs of the telecommunications industry for
per-channel voice-frequency codecs used in digital
switching and transmission systems. Digital input and
output are in serial format. Actual transmission and
reception of 8-bit data words containing the analog
information is done at a 64kb/s-2.1 Mb/s rate with analog
signal sampling occuring at an 8kHz rate. A sync pulse input
IX-23
r-------TRANSMITTER
(AID)
F~~:R
HANNEL
RECEIVER
lolAI
IGITAL
TRUNK
FUNCTIONAL DESCRIPTION: (Refer to Figure 3 for
a Block Diagram)
MK5156 BLOCK DIAGRAM
Figure 3
XMIT SYNC. Pin 6 (Refer to Figure 10 for the Timing
Diagram)
This input is synchronized with XMIT CLOCK. When
XMIT SYNC goes high, the digital outputis activated and
the AID conversion begins on the next positive edge of
. MASTER CLOCK. The conversion by MASTER CLOCK
can be asynchronous with XMIT CLOCK. The serial
output data is clocked out by the positive edges of XMIT
CLOCK. The negative edge of XMIT SYNC causes the
digital output to become three-state. XMIT SYNC must
go low for at' least 1 master clock prior to the
transmission of the next digital word (Refer .to Figure
12).
XMIT
SYNC
XMIT
CLOCK
ANALOG-_t----1~--+---{~~~
INPUT
XMIT CLOCK. Pin 7 (Referto Figure 1 0 forthe Timing
Diagram)
Tile on-chip 8-bit output shift register of the MK5156
is unloaded at the clock rate present on this pin. Clock
rates of 64kHz-2.1 MHz can be used for XMIT CLOCK.
The positive edge of the INTERNAL CLOCK transfers the
data from the master to the slave of a master-slave flipflop (Refer to Figure 5). If the positive edge of XMIT SYNC
occurs after the positive edge ofXMIT CLOCK, XMIT
SYNC will determine when the first positive edge, of
INTERNAL CLOCK will occur. In this event, the hold time
for the first clock pulse is measured from the positive
edge of XMIT SYNC.
MASTER
CLOCK
DIGlTAL _ _IL~~~
INPUT
Rev
SYNC
>-~_~~:~~;
Rev.
CLOCK
RCV. SYNC. Pin 9 (Refer to Figure 11 for the Timing
Diagram)
RECEIVE
SECTION
POSITIVE AND NEGATIVE REFERENCE
VOLTAGES (+VREF and -VREF) Pins 16 and 15
These inputs provide the conversion references for the
digital-to-analog converters in the MK5 i 56. +VREF
and -VREF must maintain 100ppM/OCreguiation over
the operating temperature range. Variation of the
reference directly affects system gain.
This input is synchronized with RCV. CLOCK andserial
data is clocked in by RCV.CLOCK. Duration of the RCV
SYNC pulse is approximately 8 RCV. CLOCK periods.
The conversion from digital-to-analog starts after the
negative edge of the RCV. SYNC pulse (RElfer to Figure
4). The negative edge of RCV. SYNC should occur before
the 9th positive clock edge to insure that only eight bits
are clocked in. RCV. SYNC must stay low for 17
MASTER CLOCKS (min.) before the next digital word is
to be received (Refer to Figure 13).
RCV CLOCK. Pin 10 (Refer to Figure 11 for Timing
ANALOG INPUT. Pin 1
D~re~
Voice-frequency analog signals which are bandwidthlimited to 4kHz are input at this pin. Typically, they are
then sampled at an 8kHz rate (Refer to Figure 4.). The
analog input must remain between +VREF and -VREF
for accurate conversion. The recommended input interface
circuit is shown in Figure 9.
MASTER CLOCK. Pin 5
This signal provides the basic timing and control signals
required for all internal conversions. It does not have to
be synchronized with RCV. SYNC, RCV. CLOCK. XMIT
SYNC or XMIT CLOCK and is not internally related to
them.
.
The on-chip 8-bit shift register for the MK5156 is
loaded at the clock rate present on this pin. Clock rates
of 64kHz-2.1 MHz can be used for RCV. CLOCK. Valid .
data should be applied to the digital input before the
positive edge of the internal clock (Refer to Figure 5).
This set up time. tRDS. allows the data to be transferred
into the MASTER of a master-slave flip-flop. The
positive edge of the INTERNAL CLOCK transfers the
data to the SLAVE of the master-slave flipcflop. A hold
time, tRDH, is required to complete this transfer. If the
rising edge of RCV. SYNC occurs after .the first rising
edge of RCV. CLOCK. RCV. SYNC will determine when
the first positive edge of INTERNAL CLOCK will occur. In
IX-24
AID, DIA CONVERSION TIMING
Figure 4
I~~~~-----------------------------125~sec----------------------------~~~1
__-,--,1
XMIT SYNC
\\...._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _, - -
~=15-20~sec~
SAMPLE AND HOLD
SAMPLE TIME
________~
\1
f. . . .----------------
~--------------------------------------------------~
= 32 MASTER CLOCKS
ENABLE SAR
SAR REQUIRES
=128 MASTER CLOCKS
-------------------------------~/
__________________________________________________________-J/
RCV.SYNC
ANALOG OUTPUT UPDATED
DATA INPUT IOUTPUT TIMING
Figure 5
Required For Data To Transfer
From Master to Slave
XMIT
Internal
Clock
DIGITAL
OUT
_____________-'A
RCV
Internal
Clock
MK5156
--..J
XMIT SYNC
Valid Data
I-
XMIT CLOCK
Required To Transfer Data
200ns From Master to Slave
I
.....,
RCV. SYNC
1--50ns Required to Load Master
RCV. CLOCK
--~/-----
1\
DIGITAL
IN
Valid Incoming Data
this event, the set-up and hold times for the first clock
pulse should be measured from the positive edge of
RCV. SYNC.
DIGITAL OUTPUT, Pin 8
The MK5156 output register stores the 8-bit encoded
sample of the analog input. This 8-bitword is shifted out
under control of XMIT SYNC and XMIT CLOCK. When
XMIT SYNC is low, the. DIGITAL OUTPUT is an open
circuit. When XMIT SYNC is high, the state of the
DIGITAL OUTPUT is determined by the value of the
output bit in the serial shift register. The output is
composed of a Sign Bit, 3 Chord Bits, and 4 Step Bits.
The Sign Bit indicates the polarity of the analog input
while the Chord and Step Bits indicate the magnitude. In
the first two Chords, the Step Bit has a value of 1.2mV.
In the third Chord, the Step Bit has a value of 2.4mV.
This doubling of the step value continues for each ofthe
five successive Chords.
Each Chord has a specific value and the Step Bits, 16 in
each Chord, specify the displacement from that value
(Refer to Table 1). Thus the output, which follows the Alaw, has resolution that is proportional to the input level
rather than to full scale. This provides the resolution of a
12-bit AID converter at low input levels and that of a 6bit converter as the input approaches full scale. The
transfer characteristic of the AID converter (A-law
Encoder) is shown in Figure 6.
DIGITAL II\IPUT, Pin 12
The MK5156 input register accepts the 8-bit sample
of an an-alog value and loads it under control of RCV.
SYNC and RCV. CLOCK. The timing diagram is shown in
Figure 11. When RCV. SYNC goes high, the MK5156
uses RCV. CLOCK to clock the serial data into its input
register. RCV. SYNC goes low to indicate the end of
serial input data. The 8 bits of the input data have the
same functions described for the DIGITAL OUTPUT. The
IX-25
transfer characteristic of the 01 A converter (A-law
Decoder) is shown in Figure 7.
DIGITAL OUTPUT CODE: A LAW
Table 1
1.
2.
3.
4.
5.
6.
7.
8.
Chord Value
O.OmV
20.1 mV
40.3mV
80.6mV
161.1mV
332mV
645mV
1.289V
Chord Code
101
100
111
110
001
000
011
010
ANALOG OUTPUT, Pin 13
Step Value
1.221 mV
1.221 mV
2.44mV
4.88mV
9.77mV
19.53mV
39.1 mV
78.1mV
The analog output is in the form of voltage steps (1 00%
duty cycle) having amplitude equal to the analog sample
which was encoded. This waveform is then filtered with
an external low-pass filter with sinx/x correction to
recreate the sampled voice signal.
OPERATION OF CODEC WITH 64kHz XMIT IRCV.
CLOCK FREQUENCIES
EXAMPLE:
1
110
0111 = +80.6mV+ (2 x 4.88mV)
Sign Bit
Chord Step Bits
If the sign bit were a zero, then both plus signs would be
changed to minus signs.
AID CONVERTER (A-Law Encoder) TRANSFER
CHARACTERISTIC
Figure 6
...::>
...
Ul
0-
g
~
(3
c;
1010 1010
1010 0101
10110101
1000 0101
10010101
11100101
11110101
11000101
~I--
OFFSET NULL
The offset null feature of the MK5156 eliminates
long-term drift errors and conversion errors due to
temperature changes by going through an offset
adjustment cycle before every conversion, th us
guaranteeing accurate AID conversion for inputs near
ground. There is no offset adjust of the output amplifier
because, since the output is intended to beAC - coupled
to the external filter, the resultant DC error (VOFFSET/O)
will have no effect. The sign bit is not used to null the
analog input. Therefore, for an analog input of 0 volts,
the sign bit will bestable.
.
11010101}
01010101
0100 0101
01110101
01100101
00010101
0000 0101
00110101
00100101
00101010
1
I..;'
~
-VREF -VREF
XMIT IRCV, SYNC must not be allowed to remain at a
logic "1" state. XMIT SYNC is required to be at a logic
"0" state for 1 master clock period (min.) before the next
digital word is transmitted. RCV. SYNC is required to be
at a logic "0" state for 17 master clock periods (min.)
before the next digital word is received (Refer to Figures
12 and 13).
0
'VREF
2
,VREF
-2-
ANALOG INPUT (VOLTS)
D/A CONVERTER (A-Law Decoder) TRANSFER
PERFORMANCE EVALUATION
CHARACTERISTIC
The equipment connections shown in Figure 8 can be
used to evaluate the performance of the MK5156. An
analog signal provided by the HP3552A Transmission
Test Set is connected to the Analog Input (Pin 1) of the
MK5156. The Digital Output of the CODEC is tied
back to the Digital Input and the Analog Output is fed
through a low-pass filter to the HP3552A. Remaining
pins of the MK5156 are connected as follows:
Figure 7
I
+ VREF
2
ANALOG OUTPUT
(VOLTS)
.-'
(1)
(2)
I
o~
...............
.... 0 0 0 0
0 .................
..... 0 0 0 0
§§§ ~ §
o
0
-. 1o (3
8 8
o ::
~
DlGI'TAllNPUTS
-0
0_
00
_
00
§§
RCV. SYNC is tied to XMIT SYNC
XMIT CLOCK istiedto MASTER CLOCK. The signal
is inverted and tied to RCV, CLOCK.
The following timing signals are required:
(1)
(2)
(3)
MASTER CLOCK =1.536 MHz
XMIT SYNC repetition rate = 8kHz
XMIT SYNC width = 8 XMIT CLOCK periods
When all the above requirements are met, the setup of.
Figure 8 permits the measurement of synchronous
system performance over a wide range of analog inputs.
IX-26
The data register and ideal decoder provide a means of
checking the encoder portion of the MK5156
independently of the decoder section. To test the system
in the asynchronous mode, MASTER CLOCK should be
separated from XMIT CLOCK and MASTER CLOCK
should be separated from Rev. CLOCK. XMIT CLOCK
and RCV. CLOCK are separated also. Some
experimental results obtained with the MK5156 are
shown in Figures 14 and 15.
SYSTEM CHARACTERISTICS TEST
CONFIGURATION
Figure 8
OATA
REGISTER
r-,.--__-----,1
I
I
I
I
IDEAL
DECODER
MK5156
1.020kHz
SIGNAL
SOURCE
I
ANALOG 13
'"
OUTPUT I - - - - - - - - - - - - ( ) \
SYSTEM
I
I
I
I HP3552A
NOUT " - -
L
1.020 kHz
NOTCH
FILTER
L __
~
ENCODER
ONLY
-l
I
II...-_ _~
FILTER
J
SOUT + NOUT
NOTE: The ideal decoder consists of a digital decompander and a 13-bit precision DAC.
ABSOLUTE MAXIMUM RATINGS
DC Supply Voltage, V+ ............................................................................... +6V
DC Supply Voltage, V- ................................................................................ -6V
Ambient Operating Temperature, TA' ............................................................. O°C to 70°C
Storage Temperature .................................................................... -55°C to +125°C
Package Dissipation at 25°C (Derated 9mW/oC when soldered into PCB) ............................ 500mW
Digital Input ............................................................................ -0.5V ::; VIN ::; V+
Analog Input .............................................................................. V-::; VIN ::; V+
+VREF' ..................... , ....................................................... -0.5V ::; +VREF ::; V+
-VREF ............................... ; .......................................... , .... V-::; -VREF ::; +0.5V
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only arid functional operation of
the device at these or any other condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
ELECTRICAL OPERATING CHARACTERISTICS
POWER SUPPLY REQUIREMENTS
NOTES
SYM
PARAMETER
MIN
TYP
MAX
UNITS
V+
Positive Supply Voltage
4.75
5.0
5.25
V
V-
Negative Supply Voltage
-5.25
-5.0
-4.75
V
+VREF
Positive Reference Voltage
2.375
2.5
2.625
V
1
-VREF
Negative Reference Voltage
-2.625
-2.5
-2.375
V
1
IX-27
TEST CONDITIONS: V+ = 5.0V, V- = -5.0V, + V REF = 2.5V, -VREF = -2.5V, TA = O°C to 70°C
DC CHARACTERISTICS
SYM
PARAMETER
RINAS
Analog Input Resistance During Sampling
RINANS
MIN
TYP
MAX
UNITS
NOTES
2
k!1
2
Analog Input Resistance Non-Sampling
100
M!1
CINA
Analog Input Capacitance
150
250
pF
2
VOFFSET/I
Analog Input Offset Voltage
±1
±8
mV
2
ROUTA
Analog Output Resistance
20
50
!1
louTA
Analog Output Current
(VOFFSET/O)
Analog Output Offset Voltage
-200
± 850
mV
hNLOW
Logic Input Low Current (VIN = 0.8V)
Digital Input, Clock Input, Sync Input
± 0.1
±10
}J.A
3
hNHIGH
Logic Input High Current (VIN = 2.4V)
Digital Input, Clock Input, Sync Input
-0.25
-0.8
mA
3
CDO
Digital Output Capacitance
8
12
pF
IDoL
Digital Output Leakage Current
± 0.1
±10
}J.A
VOUTLOW
Digital Output Low Voltage
0.4
V
4
VOUTHIGH
Digital Output High Voltage
V
4
1+
Positive Supply Current
4
10
mA
5
1-
Negative Supply Current
2
6
mA
5
IREF+
Positive Reference Current
4
20
}J.A
IREF -
Negative Reference Current
4
20
}J.A
MIN
TYP
MAX
UNITS
1.5
2.048
2.1
MHz
0.064
2.048
2.1
MHz
0.25
0.5
mA
3.9
AC CHARACTER ISTICS (Refer to Figure 10 and Figure 11)
SYM
PARAMETER
FM
Master Clock Frequency
FR, Fx
XMIT, RCV. Clock Frequency
PWCLK
Clock Pulse Width (MASTER, XMIT, RCV.)
tRe, tFC
Clock Rise, Fall Time (MASTER, XMIT, RCV.)
tRs, tFS
Sync Rise, Fall Time (XMIT, RCV.)
tDIR,tDIF
Data Input Rise, Fall Time
200
ns
25% of
PWCLK
ns
25% of
PWCI..K
ns
25% of
PWCLK
ns
twsx, tWSR
Sync Pulse Width (XMIT, RCV.)
_8_
Fx(FR)
}J.s
tps
Sync Pulse Period (XMIT, RCV.)
125
}J.s
txcs
XMIT Clock-to-XMIT Sync Delay
tXCSN
XMIT Clock-to-XMIT Sync (Negative Edge) Delay
IX-28
NOTES
50% of
tFc(tRS)
ns
200
ns
6
AC CHARACTERISTICS CONTINUED (Refer to Figure 10 and Figure 11)
SYM
PARAMETER
MIN
MAX
txss
XMIT Sync Set-Up Time
200
txoo
XMIT Data Delay
0
200
ns
4
hop
XMIT Data Present
0
200
ns
4
150
ns
4
TYP
UNITS
NOTES
ns
hOT
XMIT Data Three State
tOOF
Digital Output Fall Time
50
100
ns
4
tOOR
Digital Output Rise Time
50
100
ns
4
tSRC
RCV. Sync-to-RCV. Clock Delay
50% of
tRC (tl's)
ns
6
7
7
tRDS
RCV. Data Set-Up Time
50
ns
tRDH
RCV. Data Hold Time
200
ns
tRcs
RCV. Clock-to-RCV. Sync Delay
200
ns
tRSS
RCV. Sync Set-Up Time
200
ns
tSAO
RCV. Sync-to-Analog Output Delay
7
lis
SLEW+
Analog Output Positive Slew Rate
1
Vilis
SLEW-
Analog Output Negative Slew Rate
1
Vilis
DROOP
Analog Output Droop Rate
25
liVllis
7
SYSTEM CHARACTERISTICS (Refer to Figures 14 and 15)
SYM
PARAMETER
MIN
TYP
SID
Signal-to-Distortion Ratio
35
29
24
39
34
29
GT
Gain Tracking
-0.4
-0.8
-2.5
±0.1
±0.1
±0.2
Nlc
Idle Channel Noise
-80
TLP
Transmission Level Point
+4
NOTES:
2.
+VREF and -VREF must be matched within ± 1% in orderta meet system
requirements.
Sampling is accomplished by charging an internal capacitor; therefore, the
designer should avoid excessive source impedance. Input related device
characteristics are derived using the Recommended Analog Input Circuit.
3.
When a transition from a "'" to a "0" takes place, the user must sink the
1.
MAX
UNITS TEST CONDo
dB
dB
dB
Analog Input=O to -30dBmO
Analog Input=-40dBmO
Analog Input=-45dmO
+0.4
+0.8
+2.5
dB
dB
dB
Analog Input=+3 to -37dBmO
Analog Input=-37 to -50dBmO
Analog Input=-50 to -55dBmO
-68
dBmOp
dB
Analog Input=O Volts; note 2.
600n
RECOMMENDED ANALOG INPUT CIRCUIT
Figure 9
CO DEC
See Figure 9.
4.
5.
6.
7.
"'" current until reaching the "0" level.
Driving 30pF with 10H = ., 00 ~A. 10L = 500 ~A.
Results in 30 mW typical power dissipation (clocks applied) under normal
operating conditions.
This delay is necessary to avoid overlapping Clock and Sync.
The first bit of data is loaded when Sync and Clock are both "'" during bit
time 1 as shown on RCV. timing diagram.
IX-29
rANC<: '(
TYPICAL
SOURCE
.".
I
I
C INA•
I
3K
I
21<
R'NAS
~ 150 pf
TRANSMITTER SECTION TIMING
Figure 10
I~------------------------------------twsx----------------------------------~~
XMIT SYNC
2.4V
1.4V
O.4V
V
PCM DATA PRESENT
NOTE: All rise and fall times are measured from O.4V and 2.4V. All delay times are measured from 1.4V.
RECEIVER SECTION TIMING
Section 11
RCV
CLOCK
r-
A~N~A~LO~G~O~U~T~P~U~T~-------------------------------------------------------------------------------------;~
NOTE: All rise and fall times are measured from O.4V and 2.4V. All delav times are measured from 1.4V.
IX-30
64kHz OPERATION, TRANSMITTER SECTION TIMING
Figure 12
~1.~===================================-_1_2_5_~_s_e_C~~~~~~~~~~~~~~~~~~~~~~:~~:::::~~~:~:.~I
I XMIT SYNC
I r--.-J
U 1 MASTER
----! ! . - PWCLK
~ 14--- CLOCK
-I
I~
-I I ~
PERIOD
(MIN)
l~
__________________~
~
__________________)
V
PCM DATA PRESENT
NOTE: All rise and fall times are measured from O.4V and 2.4V. All delay times are measured from 1.4V.
64kHz OPERATION, RECEIVER SECTION TIMING
Figure 13
1~·~---------------------------------125~sec------------------------------------~
~
RCVSYNC
NOTE: All rise and fall times are measured from O.4V and 2.4V. All delay times are measured from 1.4V.
IX-31
MK5156 SID RATIO VS. INPUT LEVEL
M5156 GAIN TRACKING PERFORMANCE
Figure 14
Figure 15
CCITI SPECIFICATIONS
INPUT LEVEL (dBmO)
INPUT lEVEL (dBmO)
IX-32
MOSTEI{.
TELECOMMUNICATION PRODUCTS
Companding CODEC with Filters
MK5316(J)
FEATURES
PIN CONNECTIONS
Figure 1
o Per-channel. single-chip CODEC with filters
o
AT&T D3/D4 and CCITI compatible
o
Pin-programmable !1-law/ A-Iaw/power-down
o
On-chip stable voltage reference
GRDA-1
VF R O _ 2
VBB - 3
vcc- 4
o
±5 volt power supplies, ± 5%
o
Low power dissipation
• 40 mW operating (typ)
• 100 !1W standby (typ)
DR-S
GRDD-6
o
TIL/CMOS-compatible digital inputs and outputs
o
Gain adjust available at the transmit and receive filter
stages
o
Synchronous or asynchronous operation
o
Serial data rate from 64 kb/s to 4.096 Mb/s
o
Separate internal analog and digital grounds reduce
system noise problems
o
Single 16-pin package
o
Minimal external component count
FS R - 7
CLKR-B
16-GSx
1S-VFx l14-VFx OF
13-VFxl c
1 2 -PD/ wA
11_Dx
10-FS x
9 -CLK x
converter. The operational amplifier's output is available for
use in an inverting gain configuration at the transmit stage.
By disabling the amplifier, this output can be used as a
noninverting high-impedance input to the band-pass filter.
The band-pass, switched-capacitor filter provides rejection
ofthe 50-60 Hz power line frequency and the band-limiting
required for an 8 kHz sampling system. The A/D converter
transforms the band-limited, voice-frequency signals into
8-bit words using one of two selectable companding laws.
The encoded data is transmitted in a serial format under the
control of the transmit clock and transmit synchronization
inputs.
DESCRIPTION
The MK5316 is a monolithic device containing a
companding CODEC and PCM filters on a single chip. This
device has been designed to meet the needs of the
telecommunications industry for per-channel, voicefrequency CODECs and PCM filters. Both the transmit and
receive sections have been incorporated into a single
package with negligible loss of crosstalk immunity. Typical
device applications are PBX systems, central offices,
channel banks, and other telephone digital switching and
transmission systems.
The MK5316 transmit section is composed of an input
amplifier, a band-pass filter, and a compressing A/D
The receive section of the MK5316 is composed of an
expanding D/A converter and a low-pass filter. The D/A
converter receives 8-bit words in a serial format under
control of the receive clock and receive synchronization
inputs. The low-pass, switched-capacitor fi Iter smooths the
voltage steps of the D/ A converter and provides
compensation for the sinx/x dE;!coder response. The receive
filter output may then be adjusted to system levels by use of
a voltage divider network.
The MK5316 also features a stable on-chip voltage
reference. This reference provides excellent gain stability
over a wide temperature range and under various supply
voltage conditions.
IX-33
IX-34
MOSTEI{.
INTEGRATED PCM CODEC
Technology Update
INTRODUCTION
A general trend towards the conversion of voice signals to digital information is currently occurring.
TDM PCM is the most popular form of digital transmission.
per word are transmitted in a serial bit stream at
1.544 Mbits/sec. Each voice channel is sampled at an
8kHz rate so this signal must be bandlimited to less
than 4kHz in order to prevent undesirable aliasing.
Today there are several important applications for
this TDM scheme:
1. A high speed digital data link between central
offices to pass many conversations over one pair
of wires.
2. The electronic connection of two different circuit
paths.
3. Concentrators
Figure 1 shows how a 1 kHz input signal is sampled
every 125 flsec. At each of these sampling times, the
analog information is converted into an eight-bit
digital word that is later sent out in serial format at
the 1.544 Mbits/sec rate.
Traditionally this connection had been done by
electromechanical crossreed switches. Very low "on"
resistance, low crosstalk, and immunity from the
large ringing or transient voltages were required. Since
the electromechanical technique was deemed to be of
lower reliability, an all electronic approach was
desired. Electronic cross point switches were designed
and built, but because the electrical requirements
mentioned above are extremely difficult to meet, the
resultswere not entirely satisfying.
The digital approach obviates the analog switch problem by first performing an A to D conversion, then
assigning a time slot for each voice channel. For the
D3 channel bank, 24 channels of digital data of 8 bits
Figure 2 shows how the 24 voice channels are time
division multiplexed onto one wire (for simplicity
only simplex operation is shown).
Channel 1 analog information is first bandlimited to
less than 4kHz, then sampled and converted to a companded digital code. This 8 bit word is serially transmitted to a mu Itiplexer where digital information
from all the other channels are assimalated. The final
bit stream of 1.544mbit/sec is sent to the demu Itiplexer where the appropriate alphanumeric channel is
connected to numeric channel. This control (selection) is done by the main computer or processor.
One may see that any numeric channel could be connected to any alphanumeric channel by means of a
different time slot assignment. This completes the
switching in a completely digital manner.
8kHz SAMPLING SYSTEM
Figure 1
...B _ - -_ _ 6
A
IX-35
24 CHANNEL MULTIPLEXING
Figure 2
DIGITAL
JlSl...ILJL
DIGITAL
2
•
DIGITAL INFO (iil
~
•
-
•
•
•
•
•
•
1.544 Mb/s
•
24~---------------------------
o
m
s:
•
•
•
::!
•
"
~
,...-0
•
•
m
X
m
x§ii§
For T1 carrier systems, the digital PCM information
might be transmitted between central offices. For
PBX applications, the PCM technique is used to allow
the switching to be done digitally. The accuracy of
the subsequent O-A conversion preserves the voice
quality so that insertion loss is not a problem.
We selected the metal gate CMOS process for several
reasons. First it is extremely low power, which is of
great concern. Secondly, it allows for high-quality,
matched capacitors in a minimum of chip size. Critical analog circuit design is done well in CMOS: for
example, high gain ampl ifiers and comparators. Also,
the metal gate CMOS process is one that is well
proven in high volume production.
By using the CMOS process, only two supplies are
necessary, plus and minus five volts. To minimize
power, all the digital logic is run from the plus 5V
supply to ground, and only the analog section operates from ± 5 volts.
CHIP ARCHITECTURE
Figure 3 shows the block diagram representation of
the COOEC chip. The important features of the
scheme used are listed below:
1. Two independent OAC's for encode and decode
functions provide system isolation not achievable
using shared OAC approach. The capacitive two
OAC approach also eliminates external sample/
hold capacitors as well as an external filterfor offset
which is required in the shared DAC approach. This
minimizes the external components required.
2. Complete signalling compatibility with 03 channel bank requirements.
3. Since the companding law is implemented using 8
to 13 bit converter, the OAC is a linear OAC thus
minimizing the number of analog components to
only the minimum required for system implementation, namely two: one comparator and only one
op-amp on the entire chip. Minimizing the linear
IX-36
CO DEC BLOCK DIAGRAM
Figure 3
A SIG
IN
--.t-------,
B I~G -
r----------+--..
DIGITAL
OUTPUT
....1------,
TRANSMIT
SECTION
XMIT
SYNC
XMIT
CLOCK
~--_-+
ANALOG--....
INPUT
___-4__
-i-S~DACl
AlB SEL
IXMITI
AlB SEL
IRCVI
DIGITAL --.!.,---i
INPUT
'----,r---'
RCV
SYNC
RCV
CLOCK
B SIG A SIG
OUT OUT
components helps reduce system operating power
which was the overriding consideration in chip design. Using the CMOS process, the digital portions
dissipate power only during transitions. The linear
sections consume power continuously.
4. The digital companding section allows easy conversion from mu-Iaw to A-law. The CODEC allows
data input/output rates from 64kHz to 2.1 MHz.
5. Asynchronous or synchronous operation.
MODES OF OPERATION
The XMIT and Receive function are completely independent of each other and of the master clock. Thus
the chip can operate in synchronous/asynchronous
mode at various input/output clock rates. The chip
timing diagram is shown in Figure 4 and the Receive
and XM IT modes of operation are described in detail
below:
(a) Receive Mode of Operation
In the receive mode of operation, the serial input
data is shifted into the input buffer at the receive
clock rate during the period receive sync. is high.
The encode process is halted after the falling edge
of receive sync pulse) for about 5 to 7 p'S, and the
translated data from 8 to 13 bit converter is latched
into the 13 bit receive latch which updates the
output ofthe receive DAC with 100% duty cycle. The
receive DAC acts as a sample and hold and is
buffered by the unity gain op amp to the output.
During the signalling frame a 7 bit decode is performed and the 8th data bit is latched into the
SigA/SigB output latch as selected by the A/B Select (RCV) input. When the eight bit of a word is
a signalling bit, it is assigned the value of Y, step.
This results in a lower SID ratio than if it were
arbitrarily set to either a one or zero.
'
(b) Transmit Mode of Operation:
I n this mode of operation the analog signal is
sampled in the input sample/hold which performs
the offset-null function simultaneously as described
in the circuit operation section. Following the hold
mode, the encoding process is completed using
successive approximation technique. The operation
of the XMIT DAC is similar to the operation of the
receive DAC as described earlier. After the encode
IX-37
AID AND DI A CONVERSION TIMING
Figure 4
Ij..,..~-
_ _ _"'---_ _ 125Ps _ _ _ _
t===J[-~
....
---"'~1
____~~~~~~______________,-________~n.
XMITSYC
----1--Jr..-~-4 f - - - - TRANSMIT PREVIOUS SAMPLE
I. .
'" 80
_
L
. ____________
pS
ENABLE
SAR
~~-7pSI~
R....
_____
_
_....J
RCV
SYNC
RECEIVE NEXT SAMPLE
t
UPDATE
____________________________--' ANALOG OUTPUT
I
L _____________________________
~7"SI~
process is completed, the output of the SAR is
loaded into the output buffer. The data is transmitted serially at the output clock rate during the
period the XMIT SYNC is high. During the signalling
frame, signalling information (SigA/SigB) is inserted into the output bit stream in place of the 8th
data bit as selected by the AlB select (SMIT) input.
CIRCUIT DESCRIPTION
The system timing is controlled by the sequence controller which operates at master clock rate of 1.5 - 2.1
MHz. All necessary signals, e.g. and S&H, SAR clock
EncodelDecode control, etc; are generated in this
section. To insure proper encode operation, decode
interrupt is allowed only when the internal SAR clock is
lowthus resulting in a variable (5-7 !lsI decode interrupt
interval.
The 8 to 13 bit converter gives a one-to-one translation between 8 bit companded code at its input to a
13 bit linear code at its output thus allowing the use
of a linear DAC in the digital-to-analog conversion
process.
The 13-bit linear DAC operates on the charge distribution principal of a binary weighted capacitor
ladder.
As shown in Figure 5, the capacitor ladder has two
sections of 7 bits (7 most significant bits) and 6 bits
(6 least significant bits) connected by a 64: 1 capacitor divider. The equivalent circuit of the two sections
can be drawn as shown in Figure 6.
CAPACITOR LADDER
Figure 5
IX-38
rl-\--<1---··
CAPACITOR LADDER EQUIVALENT CIRCUIT
Figure 6
Initially S, is connected to Vin and S2 is.closed. The
op. amp. is operating as a unity gain follower and its
offset voltage (V off), along with the analog input voltage,
is stored on the capacitor.
1.016pf
~. W~" ~
m,'
",M",
WHERE
Wn
=0
~
DAC OUTPUT
Then switch S2 is opened and S, is switched to analog ground. The voltage at the inverting input of the
op-amp is now Voff-Vin. Thus when the amplifier
operates with S2 open it acts as a comparator with
effectively zero offset and -Vin applied on its
inverting input. The other end of the capacitor can
now be operated as a OAC. Thus the capacitor ladder
performs all the necessary functions of offset-null
sample-hold as well as a DAC in the encode section of
the chip.
7
~
n=1
WnC n Vr
127
0 or 1 for the n th bit.
C n = n th bit capacitor.
Vr = Reference Voltage (+Vref or ,Vref)
The output of the OAC can be written as:
VOAC =
~
128
[
7
~
+
Wn Cn
n=1
13 .
~
]
Wn (C n/64)
n=8
which is equivalent to the output of a 13 bit OAC
with an equivalent output capacitance of 128pF.
EXPERIMENTAL RESULTS
The set up of Figure 8 was used to evaluate the chip
performance.
CHIP PERFORMANCE
Figure 8
Unit #1
In the encode section this equivalent capacitor of
128pF is also employed to perform the additional
function of offset~null and sample-hold as shown in
Figure·7.
OFFSET NULL/SAMPLE HOLD
XMIT 1
XMIT 2
RCV 1
RCV 2
The MK5151 CO DEC performance exceeds the AT&
T 03 channel bank specifications. Figure 9 shows the
signal-to-quantizing distortion as a function of input
level.
Figure 7
Idle channel noise of 13-14dBrnCO is better than the
03 spec by 9-10dB. Gain tracking is shown in Figure
10.
SIGNAL-TO-NOISE RATIO
Figure 9
42
42
39
40
33
iii
:£
z
o
30
D3 CHANN EL BANK SPECS
;::
0:
o>-
'"
is
20
o>-
..J
«z
"
-20
;;:
-30
~
w
'Z"
(!)
-16dB.l00Hz
-------~
~TYPICAL
,
TRANSMIT FILTER
TRANSFER FUNCTION
-40
-50
-60
60Hz
100Hz
1kHz
200Hz
FREQUENCY {Hzl
X-2
10kHz
TRANSMIT AND RECEIVE GAIN ADJUSTMENT
Figure 5
MK5912-3
gain of the receive signal may be attenuated by using a
resistor divider as shown in Figure 5. The resistive load
connected to VFRO should be greater than 10 kO. The
maximum output voltage range is ±2.5 V and the output
offset is less than 200 mV.
If the receive filter is to drive a transformer hybrid, VFRO
should be connected to PWRI (Pin 5) as shown in Figure 6.
PWRI, Pin 5
Pin 5 provides the input to the power driver amplifiers which
interface the receive filter to a transformer hybrid. PWRI is a
high impedance input which can be driven by VFRO directly.
The input voltage range is ± 2.5 Vand the gain for a bridged
output is 6 dB. The power amplifiers may be deactivated
when not being utilized by tying PWRI to V BB .
R3
Zl
R4
PWRO+ and PWRO-, Pins 6 and 7
R4 Zl
WHERE: RT ;;- R3 + R4 t Zl ~ 10 kH
This balanced differential-output amplifier stage is provided
to drive low impedance loads directly. The gain of the
receive signal may be adjusted by a voltage divider as
shown in Figure 6. The series impedance of a load resistor
and the hybrid transformer should present an ac load
impedance of 600 0 (min.) to the amplifiers in a bridged
configuration. With a 600 0 load between pins 6 and 7, the
maximum voltage swing across the load is ± 5.0 volts.
These amplifiers may also be used to drive loads which are
connected to ground.
This op amp has a common mode range of ± 1.77 V, low dc
offset (2.5 mV typ.) and can provide a voltage gain greater
than 2000. The unity gain bandwidth is approximately
2 MHz. The transmit filter, excluding the input op amp,
provides a gain of +3 dB in the passband.
GS x , Pin 3
Pin 3 is connected to the output of the gain-adjustment op
amp in the transmit filter section. For proper operation, the
load impedance connected to the GS x output should be
greater than 10 kO in parallel with 20 pF (Referto Figure 5).
Power consumption iscut significantly by tying PWRI to V BB
which deactivates the power amplifiers.
V BB , Pin 8
Pin 8 is the negative supply pin. The voltage supplied to this
pin should be -5 V ± 5%.
Pin 4 is the output of the receive (low-pass) filter and is
capable of driving high impedance electronic hybrids. The
Vcc' Pin 9
TYPICAL CONNECTION OF THE OUTPUT POWER
AMPLIFIER STAGE
Pin 9 is the positive supply pin. The voltage supplied to this
pin should be +5 V ± 5%.
Figure 6
MK5912-3
Pin 10 is the analog input to the receive filter. The receive
signal is typically generated by the decoder section of a p. or
A-law companding COOEC. The receive filter is a low-pass
switched-capacitor filter which will pass frequencies up to
3200 Hz and provides the sin x/x correction needed to give
the COOEC decoder and receive filter pair unity gain over
the passband.
R1
PWRI
R2
TRANSFORMER
- ---,
The receive filter transfer characteristics and specifications,
including the sin x/x response introduced by the decoder,
are shown in Figure 7.
___ -.J
WHERE: R1, R2 0- GAIN SETIING RESISTORS
Rl = SERIES LOAD RESISTOR
X-3
RECEIVE FilTER TRANSFER CHARACTERISTICS
Figure 7
TYPICAL RECEIVE FILTER
TRANSFER FUNCTION
(Filter Only)
+O.15dB. 200Hz
/'
See Note 1
"
m
0.03dB
><
~
z
o
o
m
-O.ldB
3400H,.
-0.1 OdB. 200H,
'(1)
n
~
m
iii
:!a
N
...X
!:i
z
;;:
Cl
g
w
>
5
w
RECEIVE FILTER TRANSFER
FUNCTION WHEN ADDED TO THE
SIN xix OUTPUT RESPONSE OF THE CODEC
(See Note 2)
a:
Z
;;:
Cl
-33dB
OH,
FREQUENCY (Hz)
NOTES
1. The broken line shows the x/sinx response of the filter only. This response
corrects the sin x/x response of the sample and hold output of the CODEC and
provides unity gain in the passband.
2.
The typical filter transfer function shown is the combined response of the CO DEC
and the receive filter. The combined response meets the stated specifications
GRDD, Pin 11
ClK, Pin 12
Pin 11 serves as the digital ground return for the internal
clock. The digital ground is not internally connected to the
analog ground. The digital and analog grounds should be
tied together as close as practical to the system supply
ground.
The digital clock signal should be supplied to Pin 12. Four
clock frequencies (1.536 MHz. 1.544 MHz, 2.048 MHz. or
2.560 MHz) may be used. The desired clock frequency is
selected by the ClKS input (Refer to Table 1). For proper
operation this clock should be tied to the receive clock ofthe
CODEC.
INPUT CLOCK SELECT
Table 1
PDWN, Pin 13
CODEC
Clock
Clock Bits/
Frame
1.536
1.544
2.048
2.560
192
192
256
320
MHz
MHz
MHz
MHz
MK5912-3
CLK Input
Pin 12
MK5912-3
CLKS Input
Pin 14
1.536 MHz
*
VBB • -5 V
V BB • -5 V
2.048 MHz
2.560 MHz
VCC.+5 V
Open Circuit
This control input is used to place the MK5912-3 in the
standby power-down mode. Power down occurs when the
signal on this input is pulled high. Standard TIL levels may
be used. An internal pull up to the positive supply is
provided. A settling time of 15 ms (typ.) should be allowed
after power is restored.
ClKS, Pin 14
*The MK5912-3 can be used with a 1.544 MHz clock in the mode shown above.
This is accomplished by externally suppressing every 193rd bit from the
incoming train of 1.544 MHz clock bits.
The voltage level on this pin will select the desired clock
frequency to drive Pin 12. Table 1 defines the clock
X-4
selection. When using the open circuit (2.560 MHz clock
frequency) mode, the capacitance to adjacent signal lines
should be minimized.
250 mV. This output should be ac coupled to the transmit
(encoder) section of the CO DEC.
GRDA, Pin 15
DECOUPLING RECOMMENDATIONS
Pin 15 serves as the ground retwn forthe analog circuits of
the transmit and receive sections. The analog ground is not
internally connected to the digital ground. The digital and
analog ground should be tied together as close as practical
to the system supply ground.
PC board decoupling should be sufficient to prevent power
supply transients (including turn on and turn off) from
exceeding the absolute maximum rating of the device. A
minimum of 1/-IF is recommended for each power supply.
A 0.05 /-IF bypassing capacitor should also be connected
from each power supply to GRDA at the MK5912-3 device.
However, this decoupling may be reduced depending on
board design and performance.
VFxO, Pin 16
pin 16 is the analog output of the transmit filter. The output
voltage range is ± 2.5 volts and the dc offset is less than
ABSOLUTE MAXIMUM RATINGS
Temperature Under Bias ....•...•....................•. '.........••........................... -10°C to +80°C
Storage Temperature .......•.••....•......•.....•.......••.....•••......................... -65°C to +125°C
Supply Voltage with Respect to VBB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ; ............. -0.3 V to +12.0 V
All Input and Output Voltages with Respect to VBB •••••••••••••••••••••••••••••••••••••••••••• -0.3 V to +12.0 V
All Output Currents .......•...........•........•.....••........•..................................±' 50 rnA
Package Dissipation at 25°C (Derated 9 mW/oC when soldered into PCB) •....•.•....••.•............... '.. 500 mW
Stresses above those list~d under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
.
DC AND OPERATING CHARACTERISTICS
TA = O°C to + 70°C, Vee = +5 V ± 5%, VBB = -5 V
± 5%, GRDA = 0 V, GRDD = 0 V, unless otherwise specified.
DIGITAL INTERFACE
LIMITS
MIN
PARAMETER
ILie
Input load Current
10
p.A
VIN = VIL min to V IH max
ILiO
Input load Current, ClKS
50
p.A
VIN = V BB to VIH max
ILiP
Input load Current, PDWN
-40
p.A
VIN = VIL minto V IH max
VIL
Input low Voltage (except ClKS)
-0.3
0.8
V
VIH
Input High Voltage (except ClKS)
2.2
V ee +
0.25
V
VILO
Input low Voltage, ClKS
V BB
VBB +
0.5
V
V IHO
Input High Voltage, ClKS
IVee -0.5
Vee
V
X-5
TYP
MAX
UNIT TEST CONDITIONS
SYM
II
POWER DISSIPATION
Analog inputs" 0 V, outputs unloaded,unless otherwise specified.
PARAMETER
Icco
V cc Standby Current
100
p.A
PDWN " V 1H min
Isso
Vss Standby Current
100
p.A
PDWN " V 1H min
ICC1
V cc Operating Current, Power
Amplifiers Inactive
3.5
mA
PWRI" Vss
Vss Ope~ating Current, Power
Amplifiers Inactive
3.5
mA
PWRI" Vss
ISS1
MIN
TYP
MAX UNITS TEST CONDITIONS
SYM
ICC2
V cc Operating Current
6
mA
ISS2
Vss Operating Current
6
mA
DC AND OPERATING CHARACTERISITCS
TA " O°C to + 70°C, Vcc " +5 V ± 5%, Vss " -5 V ± 5%, GRDA " 0 V, GRDD " 0 V, unless otherwise specified.
ANALOG INTERFACE, TRANSMIT FILTER GAIN SETTING AMPLIFIER
SYM
PARAMETER
Isxl
Input Leakage Current, VFxl+, VFxl-
R1x1
Input Resistance, VFxl+, VFxl-
VOSX1
Input Offset Voltage, VFxl+, VFxl-
MIN
TYP
MAX
200
nA
-1.7V
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