1982_NEC_Microcomputer_Catalog 1982 NEC Microcomputer Catalog
User Manual: 1982_NEC_Microcomputer_Catalog
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t\'EC
1982 CATALOG
NEe
Electronics U.S.A. Inc.
Microcomputer Division
r-~......-;o!,"",,"",,"-......,....,..rt:'!"9_.,----------
__
Western Microtecbnology
10040 Bubb Road
Cupenino, CA 95014
Phone (408) 715-1660
TWX 910.338-0013
This 1982 Microcomputer Division catalog includes specifications for the current product
lines marketed by the Microcomputer Division of NEC Electronics U.S.A. Inc. In addition, it contains a special section of specifications for the ROM product line marketed
by the Electronic Arrays Division. Both product lines are sold through the NEC Electronics U.S.A. sales network (see last page and back covers for listing).
NEC Electronics U.S.A. Inc., with corporat€! headquarters in San Mateo, California, is a
subsidiary of Nippon Electric Company. NEC Electronics U.S.A. Inc. consists of four
product divisions. The Microcomputer Division, founded in 1975 and now located in
Natick, Massachusetts, markets a wide variety of leading-edge LSI semiconductor
memories and microprocessors. The Electronic Arrays Division, acquired by NEC in
1978, manufactures ROMs and RAMs in Mountain View, California. The Electron Division, founded in 1976 and headquartered in Sunnyvale, California, markets a broad
range of products including linear ICs, vacuum fluorescent displays, tantalum capacitors, discrete semiconductors including optoelectronics and fiber optics. The Board Division is also located in Natick, Massachusetts; it designs, manufactures, and sells
sophisticated board and system products.
NEe Electronics U.S.A. Inc.
Corporate Headquarters
3055 Clearview Way, Suite 310
San Mateo, California 94402
NEe Electronics U.S.A. Inc.
Electron Division
252 Humboldt Court
Sunnyvale, California 94086
NEe Electronics U.S.A. Inc.
Electronic Arrays Division
550 East Middlefield Road
Mountain View, California 94043
NEe Electronics U.S.A. Inc.
Microcomputer Division
One Natick Executive Park
Natick, Massachusetts 01760
NEe
NEe Electronics U.S.A. Inc.
Microcomputer Division
1982 CATALOG
The information in this document is subject to change without notice. NEC Electronics
U.S.A. Inc. makes no warranty of any kind with regard to this material, including, but
not limited to, the implied warranties of merchantability and fitness for a particular
purpose. NEC Electronics U.S.A. Inc. assumes no responsibility for any errors that may
appear in this document. NEC Electronics U.S.A. Inc. makes no commitment to update
nor to keep current the information contained in this document.
No part of this document may be copied or reproduced in any form or by any means
without the prior written consent of NEC Electronics U.S.A. Inc.
© 1982 by NEC Electronics U.S.A. Inc.
Printed in the United States of America
Additional copies of this catalog or other NEe literature may be obtained from your
local representative or distributor (addresses in section 10 of this catalog) or by
writing to:
Communications Department
NEC Electronics U.S.A. Inc.
Microcomputer Division
One Natick Executive Park
Natick, MA 01760 U.S.A.
3
ttlEC
NEe Electronics U.S.A. Inc.
Microcomputer Division
CONTENTS
GENERAL INFORMATION
MEMORIES
RANDOM ACCESS MEMORIES
FIELD PROGRAMMABLE READ ONLY MEMORIES
ELECTRONIC ARRAYS MASK PROGRAMMED READ ONLY MEMORIES
MICROCOMPUTERS
II
fl
11
II
m
SINGLE CHIP 4-BIT MICROCOMPUTERS
m
SINGLE CHIP a-BIT MICROCOMPUTERS
6
MICROPROCESSORS
PERIPHERALS
REPRESENTATIVES & DISTRIBUTORS
m
m
IE
NEe
NEe Electronics U.S.A. Inc.
Microcomputer Division
FUNCTIONAL INDEX
RANDOM ACCESS MEMORIES
Selection Guide. • . . . . . • • . . . . . ••
Dynamic NMOS RAMs
jAPD416.....................
jAPD4164........... .••....••
Static NMOS RAMs
jAPD4104. . . .. . . . . . • . • . . •. . ..
jAPD2114L. . . . . • • . . . . . . . • • . ..
jAPD2147 ... " . •.. . . . • . .•• . ..
jAPD2149. . . . . . .. . . . . . .. . . • ..
jAPD2167. . . .. . . . . . . . . . . . . • ..
jAPD4016......... ....•..•.•.
Static CMOS RAMs
jAPD5101L .•.......••.•.....•
jAPD444 .....................
jAPD446 ............•....•...
jAPD449 ..•......••..........
SINGLE CHIP
a-BIT MICROCOMPUTERS
11
Selection Guide. . . . • • • . . . . . . . ..
Alternate Source Guide ...•.....
ROM-Based Products
Ordering Procedure. . . • . . . • . ..
jAPD7800 . . . . . . . . . . . . . . • . . • . .
jAPD7801 . . . . . . . . . • . . • . . . . . . •
jAPD7802 . . • . . . • . • • . • • • . • . • . .
jAPD78C06 ...•.•........•.•..
jAPD7811G .....•.....•.•....
jAPD8021 •....•.•......... , ..
jAPD8022 •.....•...•.........
jAPD8041 A/8741 A ...•.••.•....
jAPD8048/8748/8035L . ....•...•
jAPD80C48/80C35 . . . . . . . . . . . • .
jAPD8049/8039L . . . . . . . . . . . . . .
jAPD80C49/80C39 ....... " ....
21
31
37
43
47
53
59
63
69
75
79
85
FIELD PROGRAMMABLE
READ ONLY MEMORIES
Selection Guide. • . . • . . . . . . . • . •.
Bipolar
jAPB406/426 ..•.... . . . . . • . . ..
jAPB409/429 .•..... . . . . . • . • ..
jAPB450 .....................
U.V. Erasable
jAPD2716 ...............•....
jAPD2732 . . . . . . . . . . . . . . . . . . .•
jAPD2732A. . . . . . • . • • . . . • . . . ..
jAPD2764 . . . . . . . . . . . . • . • . . . .•
Selection Guide. . . . . . . . • • . . . . ..
Alternate Source Guide .........
jAPD780 ............•.•..•.•.
jAPD8080AF ...•....••.......
jAPD8085A ....•......•...•..•
jAPD8086 . . . . . . . . . . . . • . . . • . • .
jAPD8088 ............••......
93
97
103
105
111
115
119
Selection Guide. . . . . . . . . . . . . • ..
Alternate Source Guide •....•...
ROM-Based Products
Ordering Procedure. . . • . . . • . .•
jAPD765A. . . . • . . . . . . . . . . • . . . .
jAPD7001 ••.....•...........•
jAPD7002 . . . • . . . . . • . . . . . . . . . .
jAPD7201 . . . • . • . . . • . . . . . • . . . .
jAPD7210 ....................
jAPD7220 .•..........•......•
jAPD7225 . . . . . . . . . . . . . . . • . . . .
jAPD7227 . . . . . . . . . . . . • . . . . . . .
jAPD7720 . . . . . . . . . . . . . . . . . . ..
jAPD8155/8156 .......•.......
jAPB8212 .•..........••..•...
jAPB8214 ....... , ....•. '" ., .
jAPB8216/8226 ...... . . . . • . . . .
jAPB8224 . . . . • • . . . • . . . . . • . . . .
jAPB8228 . . . . . . . . . . . . . . . . • . . .
jAPD8237 A-5 . . . . . . . . . • . . . . . . .
jAPD8243 .•...•....• " ....•...
jAPD82C43. . . . . . . . . . . . • . . . . . .
jAPD8251/8251A ..............
jAPD8253-5 ..................
jAPD8255A-5 . . . • . . . . . . • . . . . . .
jAPD8257-5 ......•...•.......
jAPD8259A. . . . . . . . . . . . . . . . . . .
jAPD8279-5 ...•...... . . . . . . . .
jAPB8282/8283 . . . . . . . . . . . . . . .
jAPB8284 . . . . . . . . . . . . . . . . . . . .
jAPB8284A ...................
jAPB8286/8287 . . . . . . . . . . . . . . .
jAPB8288 . . • . . . . . . . . . . . . . . . . .
jAPB8289 . . . . . . . . . . . . . . . . . . . .
jAPD8355/8755A ..............
125
129
133
137
12
15
17
143
157
159
161
163
165
167
169
171
173
177
193
199
205
211
219
225
233
235
241
249
12
15
391
407
421
435
447
.PERIPHERALS
SINGLE CHIP
4-BIT MICROCOMPUTERS
Selection Guide. . . . . . . . . . . • . . ..
Microcomputer Alternate
Source Guide. . . . . . . . • . . . . . ..
ROM-Based Products
Ordering Procedure. . . • . . . . . ..
jACOM-4 ...•............••.•.
jAPD546/547 ....•.......•....
jAPD557L . . . . . . . . . . . . . . . . . . •.
jAPD650/651 .•.......•.......
jAPD547L •.............••....
jAPD552/553 . . . . . . . . . . . . . . . ..
jAPD550/554 ...... . . . . . . . . . . .
jAPD550Ll554L • . . . . . • . . . . . . . .
jAPD652 ........... " ........
jAPD556B Evaluation Chip . . . . . .
jAPD7500 Series Introduction ...
jAPD7501 . . • . . . . • . . . . . . . . . . ..
jAPD7502/7503 .... . . . . . . . . . ..
jAPD7506 . . . . . . . . . . . . . . . . . . . .
jAPD7507/7508 ...............
jAPD7507S ............•.. " ..
jAPD7508A. . . • . . . . . . . • . . . . . . .
jAPD7519 ....................
jAPD7520 . . . . . . . . . . . . . . . . . . . •
jAPD7500 Evaluation Chip ......
MC-430P . . . . . . . . . . . . . . . . . . . .
17
257
269
295
321
325
329
335
341
351
363
371
381
MICROPROCESSORS
11
ELECTRONIC ARRAYS
MASK PROGRAMMED ROMs
EA Ordering Procedure ......•..
jAPD2316E/EA8316E ........•.
jAPD2332A/B/EA8332A/B. . . . • ..
jAPD2364/EA8364 . . . . . . . . . . . . .
12
15
5
12
15
17
459
479
483
487
499
515
537
545
551
569
577
583
591
595
601
607
619
625
631
649
657
665
675
693
703
707
715
723
729
737
745
II
NEe
NEe Electronics U.S.A. Inc.
Microcomputer Division
PRODUCT
NUMERICAL INDEX
PRODUCT
PAGE
"'COM-4 ..................•......
MC-430P . . . . . . . . . . . . . . . . • . . . . • . .
"'PB406 .........................
",PB409 .........•...............
",PD416 .........................
",PB426 .........................
",PB429 .........................
"'PD444 .........................
",PD446 ..............•..........
"'PD449 .........•...............
",PB450 .........................
",PD546/547 .....................
",PD547L ........................
",PD550 .....•...................
",PD550L . . . . . . . . . . . . . . . . . . • . . . . .
",PD552/553 .....................
",PD554 .........................
",PD554L . . . . . . . . . . . • . . . . . . . . . . . .
",PD556B ........................
",PD557L . . . . . . . . . . . . . . . . . . . . . . . .
",PD650/651 •....................
",PD652 ...........••.......•....
",PD765A ..........•........•....
",PD780 .........................
",PD2114L . . . . . . . . . . . . . . • . . . . • . •.
",PD2147 . . . . . . . . . . . . . . . . . . . . . . •.
",PD2149 ....................... ,
",PD2167 .......... ........ ......
",PD2316E .......................
",PD2332A/B . . . . . . . . . . . . . . . . . . . ..
",PD2364 ........•.............•.
",PD2716 . . . . . . . . . . . . . . . . . . . . . . . .
",PD2732 . . . . . . . . . . . . . . . . . . . . . . . .
",PD2732A .......................
",PD2764 . . . . . . . . . . . . . . . . . . . . . . . .
",PD4016 .. ........ .........•....
",PD4104 . . . . . . . . . . . . . . . . . . . . . . ..
",PD4164 .. ................. .....
",PD5101L . . . . . . . . . . . . . . . . . . . . . ..
",PD7001 ........................
",PD7002 . . . . . . . . . . . . . . . . . . . . . . . .
",PD7201 ........................
",PD7210 ........................
",PD7220 ........................
",PD7225 . . . . . . . . . . . . . . . . . . . . . . . .
",PD7227 . . . . . . . . . . . . . . . . . . . . . . . .
",PD7500 . . . . . . . . . . . . . . . . . . . . . . . .
",PD7501 ........................
",PD7502/7503 ...................
",PD7506 . . . . . . . . . . . . . . . . . . . . . . . .
",PD7507/7508 ...................
",PD7507S .......................
",PD7508A .......................
PAGE
",PD7519 ........................ 233
",PD7520 . . . . . . . . . . . . . . . . . . . • . . . . 235
",PD7720 .......................• 551
",PD7800 . . . . . . . . . . . . . . . . . . . . . . . . 257
",PD7801 . . . . . . . . . . . . . . . . . . . . . . . • 269
",PD7802 . . . . . . . . . . . . . . . . . . . . . . . . 295
",PD7811G ....................... 325
",PD78C06 . . . . . . . . . . . . . . . . . . . . . . . 321
",PD8021 ........................ 329
",PD8022 . . . . . . . . • . . . . . . . . . . . . . . . 335
",PD8035L ....................... 351
",PD80C35 . . . . . . . . . . . . . . . . . . . . . • . 363
",PD8039L . . . . . . . . . . . . . . . . . . . . . . . 371
",PD80C39 ....................... 381
",PD8041A ....................... 341
",PD8048 ........................ 351
",PD80C48 . . . . . . . • . . . . . . . . . . . . . . . 363
",PD8049 . . . . . . . . . . . . . . . . . . . . . . . . 371
",PD80C49 ......................• 381
",PD8080AF .................•...• 407
",PD8085A ....................... 421
",PD8086 . . . . . . . • . . . . . . . . . . . . . . . • 435
",PD8088 ........•..............• 447
",PD8155/8156 •.................. 569
",PB8212 ........................ 577
",PB8214 ......•................. 583
",PB8216 ........................ 591
",PB8224 . . . . . . . . . . . . . . . . . . . . . . . . 595
",PB8226 . . . . . . . . . . . . . . . . . . . . . . . . 591
",PB8228 ........................ 601
",PD8237A-5 .............•....... 607
",PD8243 .......•................ 619
",PD82C43 . . . . . . . . . . . . . . . . . . . . . . . 625
",PD8251/8251A .................. 631
",PD8253-5 ...................... 649
",PD8255A-5 . . . . . . . . . . . . . . . . . . . . . 657
",PD8257-5 ...................... 665
",PD8259A . . . . . . . . . . . . . . . . . . . . . . . 675
",PD8279-5 ...................... 693
",PB8282/8283 ................... 703
",PB8284 . . . . . . . . . . . . . . . . . . . . . . . . 707
",PB8284A . . . . . . . . . . . . . . . . . . . . . . . 715
",PB8286/8287 ................... 723
",PB8288 . . . . . . . . . . . . . . . . . . . . . . . . 729
",PB8289 . . . . . . . . . . . . . . . . . . . . . . . . 737
EA8316E ........................ 129
EA8332A1B . . . . . . . . . . . . . . . . . . . . . . 133
EA8364 ......................... 137
",PD8355 ........................ 745
",PD8741A ....................... 341
",PD8748 ........................ 351
",PD8755A ....................... 745
143
249
93
97
21
93
97
75
79
85
103
157
163
167
169
165
167
169
173
159
161
171
459
391
43
47
53
59
129
133
137
105
111
115
119
63
37
31
69
479
483
487
499 .
515
537
545
241
193
199
205
211
219
225
7
II
t-IEC
NEe Electronics U.S.A. Inc.
Microcomputer Division
GENERAL INFORMATION
I
NEe
NEe Electronics U.S.A. Inc.
Microcomputer Division
MEMORY SELECTION GUIDE
DEVICE
SIZE
PROCESS
PACKAGE
ACCESS
TIME
CYCLE
SUPPLY
VOLTAGE
450 ns
200 ns
150 ns
150 ns
150 ns
200 ns
150 ns
25 ns
35 ns
55 ns
450 ns
200 ns
150 ns
150 ns
150 ns
310 ns
150 ns
25ns
35 ns
55 ns
+5
+5
+5
+5
+5
+5
+5
+5
+5
+5
C
C/D
C/D
C/D
C/D
C
C
D
D
D
22
18
24
24
24
18
18
18
18
20
ns
ns
ns
ns
50 ns
50 ns
50 ns
50 ns
+5
+5
+5
+5
C/D
C/D
C/D
C/D
18
18
24
24
200 ns
200 ns
+5
D
48
450
450
250
250
450
450
250
250
ns
ns
ns
ns
+5
+5
+5
+5
D
D
D
D
24
24
24
28
MATERIALI PINS
DYNAMIC RANDOM ACCESS MEMORIES
MPD416
MPD4164
STA TIC RANDOM ACCESS MEMORIES
MPD5101L
MPD444
MPD446
MPD449
MPD4016
MPD4104
MPD2114L
MPD2147
MPD2149
MPD2167
256 x
1K x
2K x
2K x
2K x
4K x
1K x
4K x
1K x
16K x
4 TS
4 TS
8 TS
8 TS
8 TS
1 TS
4 TS
1 TS
4 TS
1 TS
CMOS
CMOS
CMOS
CMOS
NMOS
NMOS
NMOS
NMOS
NMOS
NMOS
FIELD PROGRAMMABLE READ ONL Y MEMORIES
(Bipolar)
1K x 4 OC BIPOLAR
MPB406
1K x 4 TS BIPOLAR
MPB426
2K x 8 OC 'BIPOLAR
MPB409
2K x 8 TS BIPOLAR
MPB429
(Bipolar Logic Array)
9216 bit
BIPOLAR
MPB450
(U.V. Erasable)
2K x 8 TS
NMOS
MPD2716
4K x 8 TS
MPD2732
NMOS
4K x 8 TS
NMOS
MPD2732A
8K x 8 TS
NMOS
MPD2764
50
50
50
50
ns
ns
ns
ns
MASK PROGRAMMED READ ONL Y MEMORIES
MPD2316E/
EA8316E
MPD2316E/
EA8316E-1
MPD2332A/B/
EA8332A/B
MPD2332A/B-1/
EA8332A/B-1
MPD2364/
EA8264
MPD23128/
EA8364
2K x 8 TS
NMOS
450 ns
450 ns
+5
C
24
2K x 8 TS
NMOS
350 ns
350 ns
+5
C
24
4K x 8 TS
NMOS
450 ns
450 ns
+5
C
24
4K x 8 TS
NMOS
350 ns
350 ns
+5
C
24
8K x 8 TS
NMOS
450 ns
450 ns
+5
C
24
16K x 8 TS
NMOS
250 ns
350 ns
+5
C
28
Notes: OC = Open Collector; C = Plastic Package; D
11
= Hermetic Package; TS = 3-State
NEe
NEe Electronics U.S.A. Inc.
Microcomputer Division
MICROCOMPUTER SELECTION GUIDE
SINGLE CHIP 4-81T MICROCOMPUTERS
DEVICE
FAMILY
ROM
RAM
I/O
PROCESS
OUTPUT
~PD546
~COM-43
2000 x 8
96 x 4
35
PMOS
~PD553
~COM-43H
2000 x 8
96 x 4
35
~PD557L
~COM-43SL
2000 x 8
96 x 4
21
~PD650
~COM-43C
2000 x 8
96 x 4
35
CMOS
push-pull
~PD547
~COM-44
1000 x 8
64 x 4
35
PMOS
FEATURES
SUPPLY
VOLTAGE
PINS
-10
42
PMOS
0.0.
0.0.
A
-10
42
PMOS
0.0.
A
-8
28
~PD547L
~COM-44L
1000 x 8
64 x 4
35
PMOS
0.0.
0.0.
~PD552
~COM-44H
1000 x 8
64 x 4
35
PMOS
0.0.
~PD651
~COM-44C
1000 x 8
64 x 4
35
CMOS
push-pull
A
+5
42
-10
42
-8
42
-10
42
+5
42/52
~PD550
~COM-45
640 x 8
32 x 4
21
PMOS
0.0.
A
-10
28
~PD550L
~COM-45L
640 x 8
32 x 4
21
PMOS
A
-8
28
~PD554
~COM-45
1000 x 8
32 x 4
21
PMOS
0.0.
0.0.
A
-10
28
~PD554L
~COM-45L
1000 x 8
32 x 4
21
PMOS
0.0.
A
-8
28
~PD652
~COM-45C
1000 x 8
32 x 4
21
CMOS
push-pull
+5
28
~PD556
~COM-43
External
96 x 4
35
PMOS
0.0.
B
-10
64
MC-430P
~COM-43
2000 x 8
UV EPROM
96 x 4
35
PMOS
0.0.
G
-10
42
iJPD7500
~PD7500
Series
External
256 x 4
46
CMOS
0.0.
C
+2.7 to 5.5
64
~PD7501
~PD7500
Series
1024 x 8
96 x 4
24
CMOS
0.0.
0
+2.7 to 5.5
64
~PD7502
~PD7500
Series
2048 x 8
128 x 4
23
CMOS
0.0.
0
+2.7 to 5.5
64
0
+2.7 to 5.5
64
~PD7503
~PD7500
Series
4096 x 8
224 x 4
23
CMOS
0.0.
iJPD7506
~PD7500
Series
1024 x 8
64 x 4
22
CMOS
iJPD7507
iJPD7500 Series
2048 x 8
128 x 4
32
CMOS
+2.7 to 5.5
28
+2.7 to 5.5
40/52
+2.7 to 5.5
40/52
iJPD7508
~PD7500
Series
4096 x 8
224 x 4
32
CMOS
0.0.
0.0.
0.0.
iJPD7508A
~PD7500
Series
4096 x 8
208 x 4
32
CMOS
0.0.
A
+2.7 to 5.5
40
~PD7519
~PD7500
Series
4096 x 8
256 x 4
28
CMOS
0.0.
F
+2.7 to 5.5
64
~PD7520
~PD7500
Series
768 x 8
48 x 4
24
PMOS
0.0.
E
Notes:
= -35V VF Display Drive
A
B
C
o
E
F
G
= ~COM-4 Evaluation Chip
= iJPD750X Evaluation Chip
= LCD Controller/Driver
= LED
Display Controller/Driver
= VF Display Controller/Driver
= Pin-Compatible with
iJPD546
0.0.= Open Drain
12
-6 to -10
28
NEe
NEe Electronics U.S.A. Inc.
Microcomputer Division
MICROCOMPUTER SELECTION GUIDE
SINGLE CHIP 8·BIT MICROPROCESSORS
DEVICE
SPECIAL FEATURES
ROM
RAM
I/O
PROCESS
OUTPUT
CYCLE
SUPPLY
VOLTAGE
PINS
J.lPD8021
Zero·Cross Detector
1024 x 8
64 x 8
21
NMOS
BD
3.6 MHz
+5
28
J.lPD8022
On.Chip A/D Converter
2048 x 8
64 x 8
NMOS
BD
3.6 MHz
+5
40
J.lPD8035L
J.lPD8048 w/External Memory
External
64 x 8
26
27
NMOS
TS,BD
6 MHz
+5
40
J.lPD8039L
J.lPD8049 w/External Memory
External
128 x 8
27
NMOS
TS,BD
11 MHz
+5
40
J.lPD8041
Peripheral Interface w/Slave Bus
1024 x 8
64 x 8
18
NMOS
TS,BD
6 MHz
+5
40
J.lPD8041A
Enhanced J.lPD8041
1024 x 8
64 x 8
18
NMOS
TS,BD
6MHz
+5
40
40
J.lPD8048
Expansion Bus
1024 x 8
64 x 8
27
NMOS
TS,BD
6MHz
+5
J.lPD8049
High Speed J.lPD8048
2048 x 8
128 x 8
27
NMOS
TS,BD
11 MHz
+5
40
J.lPD8741A
UV.EPROM J.lPD8041A
1024 x 8
64 x 8
18
NMOS
TS,BD
6 MHz
+5
40
J.lPD8748
UV.EPROM J.lPD8048
1024 x 8
64 x 8
27
NMOS
TS,BD
6 MHz
J.lPD80C35
CMOS 8035
External
64 x 8
27
CMOS
TS,BD
6MHz
+5
+2.7 to 5.5
40
40
J.lPD80C48
CMOS 8048
1024 x 8
64 x 8
27
CMOS
TS,BD
6 MHz
+2.7 to 5.5
40
J.lPD80C39
CMOS 8039
External
128 x 8
27
CMOS
TS,BD
6 MHz
+2.7 to 5.5
40
J.lPD80C49
CMOS 8049
2048 x 8
128 x 8
27
CMOS
TS,BD
6 MHz
+2.7 to 5.5
40
J.lPD7800
Development Chip
8080 Expansion Bus
64K Memory Address Space
External
128 x 8
48
NMOS
TS,BD
4 MHz
+5
64
4096 x 8
128 x 8
48
NMOS
TS,BD
4 MHz
+5
64
J.lPD7801
J.lPD7802
Expanded J.lPD7801
6144 x 8
64 x 8
48
NMOS
TS,BD
4 MHz
+5
64
J.lPD78C05
CMOS Microprocessor
External
128 x 8
46
CMOS
TS,BD
4 MHz
+5
64
J.lPD78C06
CMOS Microcomputer
4096 x 8
128 x 8
46
CMOS
TS,BD
4MHz
+5
64
J.lPD7810
Powerful Microprocessor
External
256 x 8
44
NMOS
TS,BD
10 MHz
+5
J.lPD7811
8 Channel AID
4096 x 8
128 x 8
44
NMOS
TS,BD
10 MHz
+5
64
64
MICROPROCESSORS
DEVICE
SUPPLY
VOLTAGES
PRODUCT
SIZE
PROCESS
OUTPUT
CYCLE
f,LPD780
Microprocessor
8·bit
NMOS
3·State
4.0 MHz
+5
PINS
40
f,LPD8080AF
Microprocessor
8·bit
NMOS
3·State
2.0 MHz
+12 ± 5
40
j.lPD8080AF·2
Microprocessor
8·bit
NMOS
3·State
2.5 MHz
+12 ± 5
40
j.lPD8080AF.1
Microprocessor
8·bit
NMOS
3·State
3.0 MHz
+12 ± 5
40
40
j.lPD8085A
Microprocessor
8·bit
NMOS
3·State
3.0 MHz
+5
~lPD8085A·2
Microprocessor
8·bit
NMOS
3·State
5.0 MHz
+5
40
j.lPD8086
Microprocessor
16·bit
NMOS
3·State
5.0 MHz
+5
40
13
NEe
NEe Electronics U.S.A. Inc.
Microcomputer Division
MICROCOMPUTER SELECTION GUIDE
SYSTEM SUPPORT
DEVICE
PRODUCT
SIZE
PROCESS
OUTPUT
CYCLE
SUPPLY
VOLTAGES
PINS
,uPD765AC
Double Sided/Double Density
Floppy Disk Controller
8-bit
NMOS
3-State
8 MHz
+5
40
,uPD781
Dot Matrix Printer
Controller-Epson 500 Printer
8-bit
NMOS
3-State
6 MHz
+5
40
,uPD782
Dot Matrix Printer
ControJler-Epson 200 Printer
8-bit
NMOS
3-State
6 MHz
+5
40
/tPD7001
8-Bit A/D Converter
8-bit
CMOS
Open
Collector
Serial
10 kHz
Conversion
Time
+5
16
/tPD7002
1O-Bit A/D Converter
8-bit
CMOS
3-State
400 Hz
Conversion
Time
+5
28
/tPD7201
Multi-Protocol Serial
Controller
8-bit
NMOS
3-State
4 MHz
+5
40
/tPD721 0
lEE E Controller (Tal ker,
Listener, Controller)
8-bit
NMOS
3-State
8 MHz
+5
40
/tPD7220
Color Graphic Display
Controller
8-bit
NMOS
3-State
5 MHz
+5
40
/tPD7225
Alpha Numeric LCD
Controller /Driver
8-bit
CMOS
-
-
2.7 to 5.5
52
/tPD7227
Dot Matrix LCD
Controller/Driver
8·bit
CMOS
-
-
2.7 to 5.!;
64
,uPD7720
Signal Processor
16-bit
NMOS
3-State
8 MHz
+5
28
/tPD8155
256 x 8 RAM with I/O Ports
and Timer
8-bit
NMOS
3-State
-
+5
40
/tPD8155-2
256 x 8 RAM with I/O Ports
and Timer
8-bit
NMOS
3-State
-
+5
40
,uPD8156
256 x 8 RAM with I/O Ports
and Timer
8-bit
NMOS
3-State
-
+5
40
/tPD8156-2
256 x 8 RAM with I/O Ports
and Timer
8-bit
NMOS
3-State
-
+5
40
/tPB8212
I/O Port
8-bit
Bipolar
3-State
/tPB8214
Priority Interrupt Controller
3-bit
Bipolar
Open
Collector
/tPB8216
Bus Driver Non-Inverting
4-bit
Bipolar
3-State
/tPB8224
Clock Generator Driver
2 phase
Bipolar
High Level
Clock
/tPB8226
Bus Driver Inverting
4-bit
Bipolar
3-State
/tPB8228
System Controller
8-bit
Bipolar
3-State
-
+5
24
3 MHz
+5
24
-
+5
16
+12 ± 5
16
3 MHz
-
+5
16
+5
28
/tPD8243
I/O Expander
4 x 4 bits
NMOS
3-State
-
+5
24
/tPD8251
Programmable Communications
Interface (Async/Sync)
8-bit
NMOS
3-State
A-9.6K baud
S,56K baud
+5
28
/tPD825.1A
Programmable Communications
Interface (Async/Sync)
8-bit
NMOS
3-State
A-9.6K baud
S-64K baud
+5
28
/tPD8253-5
Programmable Timer
8-bit
NMOS
3-State
4.0 MHz
+5
24
/tPD8255A-5
Peripheral Interface
8-bit
NMOS
3-State
-
+5
40
/tPD8257-5
Programmable DMA Controller
8-bit
NMOS
3-State
4 MHz
+5
40
/tPD8279-5
Programmable Keyboard/
Display Interface
8-bit
NMOS
3-State
-
+5
40
/tPB8282/
8283
8-Bit Latches
Bipolar
3-State
5 MHz
+5
20
/tPB8284
Clock Driver
Bipolar
3-State
5 MHz
+5
18
/tPB8286/
8287
8-Bit Bus Transceivers
Bipolar
3~State
5 MHz
+5
20
/tPB8288
Bus Controller
Bipolar
3-State
5 MHz
+5
20
/tPD8355
2048 x 8 ROM with I/O Ports
8-bit
NMOS
3-State
-
+5
40
/tPD8755A
2048 x 8 EPROM with
I/O Ports
8-bit
NMOS
3-State
-
+5
40
14
NEe
NEe Electronics U.S.A. Inc.
Microcomputer Division
MICROCOMPUTER ALTERNATE SOURCE GUIDE
J
MANUFACTURER
AMD
INTEL
PART NUMBER
DESCRIPTION
NEC REPLACEMENT
AMBOBOAl90~OA
Microprocessor (2.0 MHz)
/JPD8080AF
AMB080A-2/90BOA-2
Microprocessor (2.5 MHz)
/JPD8080AF-2
AM8080A-1/90BOA-1
Microprocessor (3.0 MHz)
/JPD8080AF-l
AMB085A
Microprocessor (3.0 MHz)
/JPD8085A
AMB155
Programmable Peripheral Interface
with 256 x B RAM
/JPD8155
AMB156
Programmable Peripheral Interface
with 256 x B RAM
/JPD8156
/JPB8212
AMB212
I/O Port (B-Bit)
AM8214
Priority Interrupt Controller
/JPB8214
AMB216
Bus Driver, Inverting
/JPB8216
/JPB8224
AMB224
Clock Generator/Driver
AMB226
Bus Driver, Non-Inverting
/JPB8226
AMB228
System Controller
/JPB8228
AM8251
Programmable Communications
Interface
/JPD8251
AM8255
Programmable Peripheral Interface
/JPD8255
AMB257
Programmable DMA Controller
/JPD8257
AMB355
Programmable Peripheral Interface
with 204B x B ROM
/JPD8355
AM804B
Single Chip Microcomputer
/JPD8048
8080A
Microprocessor (2.0 MHz)
/JPD8080AF
8080A-2
Microprocessor (2.5 MHz)
/JPD8080AF-2
B080A-1
Microprocessor (3.0 MHz)
/JPD8080AF-l
8021
Microcomputer with ROM
/JPD8021
8022
Microcomputer with A/D Converter
/JPD8022
8035L
Microprocessor
/JPD8035L
8039L
Microprocessor
/JPD8039L
8041A
Programmable Peripheral Controller
with ROM
/JPD8041A
B048
Microcomputer with ROM
/JPD8048
B049
Microcomputer with ROM
/JPD8049
8085A
Microprocessor (3.0 MHz)
/JPD8085A
B085A-2
8086
8155/8155-2
/JPD8085A-2
/JPD8086
/JPD8155/8155-2
8212
Microprocessor (5.0 MHz)
Microprocessor (16-Bit)
Programmable Peripheral Interface
with 256 x 8 RAM
Programmable. Peripheral Interface
with 256 x B RAM
I/O Port (B-Bit)
8214
Priority Interrupt Controller
/JPB8214
B216
Bus Driver, Non-Inverting
/JPB8216
8224
Clock Generator/Driver
/JPB8224
8226
Bus Driver, Inverting
/JPB8226
8228
System Controller
/JPB8228
8243
8251
I/O Expander
Programmable Communications
Interface (Async/Sync)
/JPD8243
/JPD8251
8156/8156-2
15
/JPD8156/8156-2
/JPB8212
J
NEe
NEe Electronics U.S.A. Inc.
Microcomputer Division
MICROCOMPUTER ALTERNATE SOURCE GUIDE
I
MANUFACTURER
INTEL (CONT.)
NATIONAL
T.I.
PART NUMBER
DESCRIPTION
NEC REPLACEMENT
8251A
Programmable Communications
Interface (Async/Sync)
j.LPD8251A
8253·5
Programmable Timer
j.LPD8253-5
8255A-5
Programmable Peripheral lriterface
j.LPD8255A-5
8257-5
Programmable DMA Controller
j.LPD8257-5
8259A
Programmable Interrupt Controller
j.LPD8259A
8272
Double Sided/Double Density
Floppy Disk Controller
j.LPD765
8279-5
Programmable Keyboard/Display
Interface
j.LPD8279-5
8282/8283
8-Bit Latches
j.LPB8282/8283
8284
Clock Driver
j.LPB8284
8286/8287
8-Bit Transceivers
j.LPB8286/8287
8288
Bus Controller
j.LPB8288
8355
Programmable Peripheral Interface
with 2048 x 8 ROM
j.LPD8355
8741A
Programmable Peripheral Controller
with EPROM
j.LPD8741A
8748
Microcomputer with EPROM
j.LPD8748
8755A
Programmable Peripheral Interface
with 2K x 8 EPROM
j.LPD8755A
8274
Multiprotocol Serial Controller
j.LPD7201
INS8048
Microcomputflr with ROM
j.LPD8048
I NS8049
Microcomputer with ROM
j.LPD8049
I NS8080A
Microprocessor (2.0 MHz)
j.LPD8080AF
INS8080A-2
Microprocessor (2.5 MHz)
j.LPD8080AF-2
INS8080A-1
Microprocessor (3.0 MHz)
j.LPD8080AF-1
8212
I/O Port (8-Bit)
j.LPB8212
8214
Priority Interrupt Controller
j.LPB8214
8216
Bus Driver, Non.lnverting
j.LPB8216
8224
Clock Generator/Driver
j.LPB8224
8226
Bus Driver, Inverting
j.LPB8226
8228
System Controller
j.LPB8228
INS8251
Pro!:lrammable Communications
Interface
j.LPD8251A
INS8253
Programmable Timer
j.LPD8253-5
INS8255
Programmable Peripheral Interface
j.LPD8255A-5
INS8257
Programmable DMA Controller
j.LPD8257-5
INS8259
Programmable I nterrupt Controller
j.LPD8259A
TMS8080A
Microprocessor (2.0 MHz)
j.LPD8080AF
TMS8080A·2
Microprocessor (2.5 MHz)
j.LPD8080AF-2
TMS8080A-1
Microprocessor (3.0 MHz)
j.LPD8080AF-1
SN74S412
I/O Port (8-Bit)
j.LPB8212
SN74LS424
Clock Generator/Driver
j.LPB8224
SN74S428
System Controller
j.LPB8228
16
J
NEe
NEe Electronics U.S.A. Inc.
Microcomputer Division
ROM-BASED PRODUCTS ORDERING PROCEDURE
The following NEC products fall under the guidelines set by the ROM-Based Products Ordering Procedure:
IlPD7801
IlPD7802
IlPD7811
IlPD8021
IlPD8022
Il PD8041A
IlPD8048
IlPD80C48
IlPD8049
IlPD80C49
IlPD8355
IlPD546
Il P D547
Il P D547L
Il P D550
IlPD550L
Il P D552
IlPD553
IlPD554
Il PD554L
IlPD557L
IlPD650
IlPD651
IlPD652
Il P D7501
IlPD7502
IlPD7503
IlPD7506
IlPD7507
IlPD7507S
IlPD7508
IlPD7508A
IlPD7519
IlPD7520
IlPD7720
NEG Electronics U.S.A., Inc., Microcomputer Division is able to accept mask patterns in a variety of formats to facilitate
the transferral of ROM mask information. These are intended to suit various customer needs and minimize the turnaround
time. Always enclose a listing of the code and the code submittal form. The following is a list of valid media for code
transferra I.
•
•
•
•
•
•
PROM/EPROM equivalent to ROM parts
Sample ROMs or ROM-based microcomputers
Paper Tape
Timesharing Files
ISIS-II compatible disks
Other (Contact NEC Electronics U.S.A., Inc., Microcomputer Division for arrangements.)
Thoroughly tested verification procedures protect against unnecessary delays or costly mistakes. NEC Electronics U.S.A.,
Inc., Microcomputer Division will return the ROM mask patterns to the customer in the most convenient format.
Unprogrammed EPROMs, if sent with the ROM code, can be programmed and returned for verification.
Earth satellites and the world-wide GE Mark III timesharing systems provide reliable and instant communication of ROM
patterns to the factory. Customers with access to GE-TSS may further reduce the turnaround time by transferring files
directly to NEG Electronics U.S.A., I nc., Microcomputer Division.
The following is an example of a ROM mask transferral procedure. The IlPD8048 is used here; however, the process is the
same for the other ROM-based products.
1. The customer contacts NEG Electronics U.S.A., Inc., Microcomputer Division's Sales Representative, concerning
a ROM pattern for the IlPD8048 that he would like to send.
2. Since an EPROM version of that part is available, the IlPD8748 is proposed as a code transferral medium, or a
paper tape and listing may be used.
3. Two programmed IlPD8748's are sent to NEG Electronics U.S.A., Inc., Microcomputer Division with a listing, a
code submittal form, and a paper tape as back-up.
4. NEC Electronics U.S.A., Inc., Microcomputer Division compares the media provided and enters the code into
GS-TSS. The GE-TSS file is accessed at the NEC factory and a copy of the code is returned to NEG Electronics
U.S.A., Inc., Microcomputer Division for verification. One of the IlPD8748's is erased and reprogrammed with the
customer's code as the NEC factory has it. Both IlPD8748's and a listing are returned to the customer for his final
verification.
5. Once the customer notifies NEC Electronics U.S.A., Inc., Microcomputer Division in writing that the code is
verified and provides the mask charge and hard copy of the purchase order, work begins immediately on
developing his IlPD8048's.
Please contact your local Sales Representative for assistance ~ith all ROM-based product orders, Mask Programmed ROM
products other than those listed above are marketed by Electronic Arrays Division; refer to Section 5 for Electronic Arrays'
ordering procedures.
17
~
NOTES
18
ttiEC
NEe Electronics U.S.A. Inc.
Microcomputer Division
MEMORIES
RANDOM ACCESS MEMORIES
IJ
NEe
",PD416
",PD416-1
",PD416-2
",PD416-3
",PD416-5
NEe Electronics U.S.A. Inc.
Microcomputer Division
16384 X 1 BIT DYNAMIC MOS
RANDOM ACCESS MEMORY
DESCR I PTION
The NE;C J,lPD416 is a 16384 words by 1 bit Dynamic MOS RAM. It is designed for
memory applications where very low cost and large bit storage are important design
objectives.
The J,lPD416 is fabricated using a double-poly-layer N channel si licon gate process
which affords high storage cell density and high performance. The use of dynamic
circuitry throughout, including the sense amplifiers, assures minimal power dissipation.
Multiplexed address inputs permit the f,lPD416 to be packaged in the standard 16 pin
dual-in-line p,!ckage. The 16 pin package provides the highest system bit densities and
is available in either ceramic or plastic. Noncritical clock timing requirements allow
use of the multiplexing technique while maintaining high performance. '
FEATURES
• 16384 Words x 1 Bit Organization
• High Memory Density - 16 Pin Ceramic and Plastic Packages
• Multiplexed Address Inputs
• Standard Power Supplies +12V, -5V, +5V
• Low Power Dissipation; 462 mW Active (MAX), 20 mW Standby (MAX)
• Output Data Controlled by CAS and Unlatched at End of Cycle
• Read-Modify-Write, R'AS-only Refresh, and Page Mode Capability
• All Inputs,TTL Compatible, and Low Capacitance
• ,128 Refresh Cycles
• 5 Performance Ranges:
PIN CONFIGURATION
ACCESS TIME
RIW CYCLE
J,lPD416
300 ns
510 ns
575 ns
J,lPD416-1
250 ns
410 ns
465 ns
J,lPD416-2
200 ns
375 ns
375 ns
J,lPD416-3
150 ns
320 ns
320 ns
J,lPD416-5
120 ns
320 ns
320 ns
"
RMW CYCLE
VBB
VSS
CAS
AO-A6
Address Inputs
DIN
CAS
Column Address Strobe
WRITE
DOUT
DIN
Data In
RAS
Data Out
A6
DOUT
RAS
AO
A3
WRITE
VBB
Read/Write
Power (-5V)
VCC
Power (+5V)
A4
A2
A1
A5
VDD
Vcc
Rev/3
21
--
---
---_.._---
Row Address Strobe
VDD
Power (+12V)
VSS
Ground
,--
flPD416
BLOCK
DIAGRAM
'0
COL
.,~'--------I.~~:.
~T
~s~
-~
"~
.~
~
Operating Temperature.
Storage Temperature .. .
All Output Voltages CD ...........
All Input Voltages CD ............
Supply Voltages VDD, VCC, VSS CD..
Supply Voltages VDD, VCC ~ ...
Short Circuit Output Current
Power Dissipation . . . . . . . .
Notes:
CD
O°C to +70°C
-5SoC to +lS0°C
-O,S to +20 Volts
-O.S to +20 Volts
-O.S to +20 Volts
-1.0 to +1S Volts
" .SOmA
. . . . . . . . 1 Watt
.
.
.
ABSOLUTE MAXIMUM
RATINGS*
Relative to VBB
(2) Relative to Vss
Ta= 2SoC
*COMMENT: Stress above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions above those indicated in the oporational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
T a = O°C to 70°C, VDD
VSS = OV
PARAMETER
I nput Capacitance
(AO·A6), DIN
I nput Capacitance
RAS. CAS. WRITE
Output Capacitance
(DOUT)
= +12V
± 10%. VBB
SYMBOL
MIN
=-SV ±
10%, VCC
LIMITS
TYP MAX
=+SV ± 10%,
UNIT
Cll
4
S
pF
CJ2
8
10
pF
Co
S
7
pF
22
TEST
CONDITIONS
CAPACITANCE
IlPD416
DC CHARACTERISTICS
Ta
= O°C
to +70°CQ), VOO
= +12V
± 10%, VCC
= +5V
± 10%, VSS
= -5V
± 10%, VSS
LIMITS
PARAMETER
SYMBOL
UNIT
TYP
MAX
Supply Voltage
VOO
10.8
12.0
13.2
V
Supply Voltage
VCC
4.5
5.0
5.5
V
MIN
= OV
TEST
CONDITIONS
0
0
V
-5.0
-5.5
V
@
--------@ @
@
@
2.7
7.0
V
@
VIH
2.4
7.0
V
@
Input Low (Logic 0)
Voltage, all inputs
VIL
1.0
0.8
V
@
Operating VOO Current
1001
Supply Voltage
VSS
Supply Voltage
VSS
I nput Hi~o~)
Voltage, RAS, CAS,
VIHC
WRiTE
Input High (Logic 1)
Voltage, all inputs
except RAS, CAS
0
-
4.5
WRiTE
--_._-
Standby VOO Current
1002
RefreshlAIl Speeds
VOO
except "P0416-5
1003
Currentl
1003
"P0416-5
35
1004
Operating VCC
Current
ICCl
Standby V CC Current
ICC2
-10
Refresh VCC Current
ICC3
-10
cycling;
= tRC Min.
tRC
®
mA
RAS
VIHC,OOUT
= High Impedance
25
mA
RAS cycling, CAS
27
mA
1.5
Page Mode VOO
Current
RA"S, CAS
mA
27
=
375 ns
VIHC; tRC
®
RAS = VIL.CAS
cycling; tpc
225 ns@
mA
----
IJA
10
I
JRAS
10
._ICC4
Operating VSS
Current
ISSl
200
Standby VSS
Current
ISS2
Refresh VSS
Current
ISS3
-----.----
RAS = VIHC,
00UT = High
Imptdance
IJA
--"'--'.- ~-----
Page Mode V CC
Current
RAS, CAS cycling.
tRC 375 ns ®
IJA
-
CAS
,,,,,00
VIHC
tRC
375 ns
RAS
.---
--
VIL CAS -
"A
cyclmg tpc
IJA
R AS.Ci'iS cyclmy
tRC 375ns
100
"A
Dour
200
"A
CAS - VIHr:.
"A
RAS· VI L, CAS
cycling;
tpc = 225 ns
Vee - 5V, OV <:
VIN " +7V,
all other pins not
under test = OV
225.':'.:..®.
_.
- - - _...
-
_-
RAS
VIHC.
I-I,qh
Impedance
----~
I
RAS cycling.
tRC
Page Mode Vee
Current
200
lee4
=
375 ns
--
Input Leakage
(any input)
II!Ll
-10
10
IJA
Output Leakage
IO(Ll
-10
10
"A
Output High Voltage
(Logic 1)
VOH
Output Low Voltage
(L.ogic 0)
VOL
Notes:
2.4
0.4
00UT is disabled,
OV
<;;
V
lOUT
V
lOUT
VOUT " +5.5V
-5mA@
= 4.2 mA
CD T a is specified here'for operation at frequencies to tRC ~ tRC
(min). Operation at higher cycle rates with reduced
ambient temperatures and high power dissipation is permissible, however, provided AC operating parameters are met.
See Figure 1 for derating curve.
@AII voltages referenced to
@
@)
®
Vss.
Output voltage wit swing from VSS to Vee when activated with no current loading: For purposes of maintaining
data in standby mode, VGC may'be reduced tD.VSS without affecting refresh operations or data retention. However,
the VOH (min) specification is not guaranteed In this mode.
1001, '003, and 1004 depend on cycle rate. See Figures 2, 3 and 4 for too limits at other cycle rates.
19
leC1 and
C4 de'pend upon output loading. During readout of high level data Vee is connected through a low
impedance 1350 typ) to data out. At all other times ICC consists of leakage currents only.
23
flPD416
AC
CHARACTERISTICS
T•• O'C
'0 +70'C, VOO • +12V • 10%, VCC· +6V ± 10%, Vaa • -SV ± 10%, VSS· OV
jOPD41 I
MIN
MAX
I'PD411-1
MIN
MAX
LIMITS
I'PD411·2
MIN
MAX
'RC
510
410
'RWC
575
465
Page mode cycle time
tpc
330
275
Access ti,ne from
RAS
'RAC
PARAMETER
Random read or write
cvcle time
Read·writl
cycl. time
SYMBOL
300
Access time from
jAPD411-3
MIN
MI>,X
jAPD416-6
MIN
MAX
375
320
320
375
375
320
225
170
200
250
120
CAs
'CAC
200
165
135
100
Output buffer
turn-off delay
'OFF
60
60
50
40
35
Transition time
(rise and fait)
'T
50
50
50
35
RAS precharge time
tAP
200
RASpul.ewid,h
'RAS
300
10.000
250
10,000
rl'iMi
__A=-h_OI_d_'im_'_ _-+-_'~RS",-H,--+-20_0-+_ _-+_1.6:.:.5-+
200
32,000
150
35
32,000
120
10,000
10,000
40
'CAS
200
10.000
165
10,000
135
10,000
100
10,000
60
60
time
'RCO
40
100
35
85
25
65
20
50
15
~,ol'iMi
precharge time
'CRP
-20
Row address
set·uptime
'ASR
Row address
hold time
'RAH
40
35
25
20
15
-10
-10
-10
-10
m
pu I.. wid,h
FfASto ~ delav
Column address
set-up time
-20
135
100
-20
'ASC
hold time
'CAH
90
75
55
45
40
Column address hold
time referenced to
'AR
190
160
120
95
80
40
RAS
®
-20
-10
Column address
®@
®®
100
100
120
TEST
CONDITIONS
160
150
80
150
UNIT
Read command
set-uptime
'RCS
Read command
hold time
'RCH
Write command
hole time
'WCH
90
75
55
45
Write command
hold tim.
referenced to 'FiAS
'WCR
190
160
120
95
80
40
Write command
75
55
45
RAS lead time
'RWL
120
85
70
50
50
Write command to
CAS lead time
'CWL
120
85
70
50
50
90
75
55
45
40
pulse width
'WP
Write command to
90
Data-in set-up time
'os
Data-in hold time
'OH
Data-in hold time
referenced to R AS
'OHR
190
160
120
95
80
(for page mode
cycle only)
'CP
120
100
80
60
60
Refresh period
tREF
®
®
CAS precharge time
WRITE command
set-up time
CAS
'0 WRITE
delay
RAS
delay
Notes:
CD
@
'0 WRITE
-20
-20
20
20
'cwo
140
125
95
70
80
'RWO
240
200
160
120
'20
'WCS
@
AC measurements assume tT = 5 ns.
VIHC (min) or VIH Imin) and VIL (max) are reference levels for measuring timing of Input signals. Also. transItion times are rreasured between VIHC or VIH and VIL
®
The specifications for tRC (min) and IAWC (mini are used only to indicate cycle time at which proper operation over the full temperature range (O°e " T a';; 70°Cl
is assured.
@
Assum~s that tRCD c;;: tRCD (max). If tACO is greater than the maximum recommended value shown in this H·ble, tRAC will increase by the amount that tACO
exceeds the values shown.
®
®
Assumes that tRCD ;;. tRCD (max).
Measured with a load equivalent to 2 TTL loads and 100 pF.
(1) tOFF {maxi defines the time at which the output achieves the open circuit condition and is not referJ!.'nced to output voltage levels.
@ Operation within the tACO Imsxllimit ensures that tRAC (maxi can be met, tRCD (maxi is specified as a reference point only. If tRCD is greater
®
@
than the specified
tACO (max) limit, then access time is controlled exclusively by tCAC
These parameters are referenced to
'CA'S leading edge in early write cycles and to"WR'iTE leading edge in delaye:d write or read-modify-write cycles,
tWCS. tCWD and tAWD are not restrictive operating parameters. They are included in the data sheet 85 ele(;.tricSI characteristics only. If twcs :... twcs (min), the cycle
IS an early write cycle and the data out pin will remain open circuit (high impedance) ;:. tRWD {minI. the cycle is a read-write cycle and the data out Will contain data
read from the selected cell; if neither of the above sets of conditions is ,satisfied the condition of the data out (at access time) is indeterminate.
24
",PD416
CYCLE TIME tRC (ns)
DERATING CURVES
320
1000
I I
50 mA
I
500 400
I
375
300
250
I
/lPD416· 5
..§
320
500
1000
.1 II I
70 --Ta(MAX)
40~ 1375 I~OO
:2
~
z
UJ
iii
:2
«
50
o
1.0
2.0
3.0
SPEC LIMIT
zUJ
250
:J
(J
I 9'"
+c,e~
q \.~,.
/
0
/"
0
2
4.0
~/'
10mA
I'
{l, /
'/
~' /"
~
/
/'
/'
CYCLE RATE (MHz) = 10 3 /tRC (ns)
0
FIGURE 1
o
Maximum ambient temperature versus cycle
rate for extended frequency operation. T a
(max) for operation at cycling rates greater
than 2.66 MHz (tCYC < 375 ns) is deter·
mined by Ta (max) [DC] = 70 - 9.0 x
(cycle rate [MHz] -2.66). For /lPD416·5,
it is Ta (max) [DC] = 70 - 9.0 (cycle rate
[MHz] - 3.125).
320
1000
500 400
300
375 I
II I I
3.0
2.0
1.0
CYCLE RATE (MHz)
=
4.0
10 3 /tRC (ns)
FIGURE 2
Maximum I DDl versus cycle rate for device
operation at extended frequencies.
CYCLE TI ME t RC (ns)
50 mA
,
-<"Y /
20 rnA
X
«
~
((:)'0/
;r;:.
30 mA
c..
c..
:J
//,~
b.'((:) ' / ,,"''/
>..I
(/)
,
0'
(L
(L
"
60
.....
40 mA
.....
"
.....'"
c..
~~
;;(
CYCLE TIME t RC (ns)
CYCLE TIME tpc (ns)
250
1000
I
500
400
300
I
50 mA
250
200
160
I
1/
/lPD416· 5;;(
40 mA
..§
40mA
.....
z·
UJ
CC
cc
30 mA
SPEC LIMIT
I
20 mA
,
10mA
~-.(
...
~/)\ ..."./
0."(,,;
,'"
i-c,e\>;" "ro-~\,
'?'.:.:;~ ,?,o./
,'"
,~
(J
30mA
SPEC LIMIT
>..I
c..
c..
::::l
"
(/) 20mA
'(~
.....
-
o
o
1.0
2.0
3.0
o
4.0
1.0
2.0
3.0
4.0
5.0
CYCLE RATE (MHz) = 10 3 /tRC (ns)
CYCLE RATE (MHz) = 10 3 /tRC (ns)
FIGURE 3
FIGURE 4
Maximum I DD3 versus cycle rate for device
operation at extended frequencies.
Maximum IDD4 versus cycle rate for device
operation in page mode.
25
6.0
",PD416
READ CYCLE
TIMING WAVEFORMS
~------------------tRC------------~3-----~
RAS
V 1HC
v ,L
t------------tRAS----t
- - - - . . I 1 - - - - - - - tAR
:
~--
=-tt~RP
V,HC
CAS
V,L
ADDRESSES
V,H
V,L
V
,HC _ ~i7?,77i.7liIt7J;7J.r--I----------I-_,~7J;7};~;?,
-_:J-
f------tAAC - - - - - - - - l r -_ _
----------OPEN------ tAC (min). Operation at higher cycle ~~. with reduced
ambient temperature' and higher power dissipation Is permissible, however. provided AC operating parameters are met.
®
An Initial pause of 100 ,",S Is required after power-up followed by any 8
achieved.
RAI cycles before proper device operation I.
@ AC measurements assume tT - 5 ns,
@ VIHC (minI or VIH (minI end VIL (m •• lare relorence level. for measuring 'Imlllll of Inpu' signal •. AI.o, tr.nlltlon
times are measured between VIHC or VIH and VIL.
® ~heef=~!~:~~~~:eo~8~~ ~~)..:a~~ ~~~A)II;~~~::d only to Indicate cycle times 8t which proper operation OYer
® AIIumes that tRCS c: tACO (max). If tACS Is greater than the maximum recom,,",n~d value shpwn In this table,
o
®
tRAC will Increllle by the amount that tACO exceeds the values shown.
Assume. that 'RCO > tRCO (m •• ).
Me.,ured wl,h alood 8qulvalen, to 21TL loads and 100 pF.
@ tOFF
(miX) defines the time at which the output echlev•• the open circuit condition and II not referenced to outPut
voltage levels,
@ ()peretlon within tho 'RCO (moxlllmit 8n.ures that tRAC (ma.1 can
o
be met, 'RCO Im •• II••paclflad .. e noloren""
point only. If tRCO Is greatar than the specified tACO (max) limit. then access time I. controlled exclu.lvelv by tCAC.
These parameters are referenced to ~ leading edge In 8arlv write cyclet and to
or read-modlfy-wrlte cycles.
Wft"iTE ,.adlng edge In delllVed writ.
@ 'WCS, leWD and tRWO ano re.trlctlve oper.tlng paramete" In nood-wrl" lOcI reod·modlfy ...rl .. cycl .. only. If 'WeS >
twcs (min), the cycle Is an early write cycle and the data outPut will remain open circuit throughout th.lntlrl cycl •.
If 'CWO> 'CWO Imlnllnd 'RWO > 'RWO Imlnl, tha eyeltll a reod-wrf".nd 'he da'" outpu, will contol" dato nood
from the selected cell. "If neither of the &bow condition. ere met thl condition of the date out (at ecCMI time end until
~goos back to VIHIIs Indotormln ..e.
@
El,her 'RRH or 'RCH must be .. tllfled for I reod cycle.
33
11
fLPD4164
READ CYCLE
TIMING WAVEFORMS
~------------------'RC----------___; } V
1HC
t - - - - - - - - - - - - - - - - - - ' R A S - - - -_
'AR
_ _ _"""" 1 - - - - -
"RAS
V,L
~~:RP
'CSH
V
CAS
'--..,...--+-----~+' --'CPN~
1HC
V,L
V ,H
ADDRESSES
V,L
V ,HC _
~
~--T----r-t-"~.
'1111111111
_
_ _ _ _ _ _ _ _ _'RAC _ _ _ _ _
.t-~~-J--
r-
OPEN
'OFF
WRITE CYCLE (EARLY WRITE)
RAS
CAS
ADDRESSES
------------OPEN----------------READ-WRITE/READ-MODIFY-WRITE CYCLE
V
WRIfE
1He
VOL
vOH
DOUI
0,,,,
VOl
V
1H
VI[
34
#PD4164
"RAS-ONL V" REFRESH
TIMING WAVEFORMS
(CaNT.)
iiAS
v'HC_
V
_
1L
V
ADDRESSES
cvcut
V
_
1H
1L
_
V'HC
CAS
V'L
V
°OUT
V
OH
OL
_
_
------------------------OPEN---------------------------
HIDDEN REFRESH CYCLE
PAGE MODE READ CYCLE
PAGE MODE WRITE CYCLE
RAS
eAs
V'HC_
"'l_
V'HC_
V
V
ADDRESSES
WRiTE
1H
_
V'L_
"IHC-
V
V
D'N
_
1L
V
_
1L
1H
1l
_
_
35
ILPD4164
CAPACITANCE
PACKAGE
MPD4164C OUTLINES
MPD4164D
4164DS-REV 1-1-82-CAT
36
NEe
#-lPD41 04
Microcomputer Division
#-lPD41 04-2
#-lPD4104-1
NEe Electronics U.S.A. Inc.
4096 X 1 STATIC NMOS RAM
DEseR IPTION
The pPD4104 is a high performance 4K static RAM. Organized as 4096 xl, it uses
a combination of static storage cells with dynamic input/output circuitry to achieve
high speed and low power in the same device. Uti I izing NMOS technology, the
pPD4104 is fully TTL compatible and operates with a single +5V ± 10% supply.
FEATURES. Fast Access Time-200ns (pPD4104-2)
•
•
•
•
•
•
Very Low Stand-By Power - 28 mW Max.
Low VCC Data Retention Mode to +3 Volts.
Single +5V ±10% Supply.
Fully TTL Compatible.
Available in 18 Pin Plastic and Ceramic Dual-in-Line Packages.
3 Performance Ranges:
SUPPLY CURRENT
ACCESS TIME
RIWCYCLE
ACTIVE
STANDBY
/JPD4104
300 ns
460 ns
21 mA
SmA
SmA
/JPD41 04-1
250 ns
385 ns
21 mA
5mA
3.3mA
/JPD41 04-2
200 ns
310 ns
25mA
SmA
3.3mA
A3
VCC
A2
AS
A,
A4
AO
A7
A11
A8
A10
Ag
DOUT
PIN NAMES
AO-A11
Address Inputs
CE
Chip Enable
DIN
Data Input
DOUT
Data Output
VSS
Ground
A6
VCC
Power (+SV)
WE
DIN
WE
Write Enable
VSS
CE
Rev/3
37
LOWVCC
IJPD4104
AO-1------------~
A,
BLOCK DIAGRAM'
ROW
MEMORY
ARRAY
DECODER
A2
AND
A3
A4
AS ......------.-------1
64 x 64
COLUMN
DECODER AND
BUFFER
Operating Temperature . . . . . . . . . . . . . . : . . . . . . . . . . . . . . . . . O°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
Voltage on Any Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1 to +7 Volts
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Watt
Short Circuit Output Current . . . . . . . . . . . . . . . . . . . . . . . , . . . . . . . . . 5.0 mA
ROW
SELECT
•
•
•
MEMORY ARRAY
64 ROWS
64 COLUMNS
•
AS
Ag------I>
1/01
1/02 - - - + - I H - - t ~>--t
INPUT
DATA
1/03 - -.....-HH--t :>--tCONTRO L
o
... -1O e to +85°e
o
.. -65°e to +150 e
. -1.5V to +7V CD
.20mA
. .......... 1.2W
Operating Temperature
Storage Temperature ..
Voltage on Any Pin.
DC Output Current . . . . . . . . . . . .
Power Dissipation . . . . . . . . . . . . .
Note:
CD
ABSOLUTE MAXIMUM
RATINGS*
with respect to ground
Ta=25°C
*COMMENT: Stress above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and functional operation of tho device at these or
any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability .
0
T a = 0 0 C to +70 C; V CC = +5V ± 10%, unless otherwise noted.
PARAMETER
SYMBOL
MIN
MAX
UNIT
DC CHARACTERISTICS
TEST CONDITIONS
Input Leakage Current
III
+10
p,A
VIN = GND to VCC
Ouput Leakage Current
ILO
+50
p,A
CS = VIH
VOUT = GND to 4.5V
MA
VIN - VCC: I/O = open
Power Supply Current
ICC
Input Low Voltage
VIL
Input High Voltage
VIH
Output Low Voltage
VOL
Output High Voltage
VOH
Output Short Circuit
Current
lOS
1S0
0.8
2.1
VCC
0.4
2.4
±200
V
V
V
10L= 8 MA
V
IOH =':"4 MA
MA
VOUT = GND to VCC
-
Note: The operating temperature range is guaranteed with transvane air flow exceeding 400 feet per minute.
54
,.,PD2149
CAPACITANCE
CD
Ta = 2S0C; f = 1.0 MHz
LIMITS
PARAMETER
AC CHARACTERISTICS
READ CYCLE +~~-I~:-JCONTROL
IfrllI6
1107
1108
Pin Configuration
Absolute Maximum Ratings *
Ta = 25°C
Temperature Under Bias ............... -10°C to 85°C
Storage Temperature ................. -65°C to 150°C
Voltage on any pin with respect to Ground -0.5V to 7V
D.C. Output Current .................. 20mA
Power Dissipation .................... 1W
*COMMENT: Exposing the device to stresses above those
listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated
under conditions outside the limits described in the operational sections of this specification. Exposure to absolute
maximum rating conditions for extended periods may
affect device reliability.
VCC
AS
A9
As
WE
BE
Al0
Al
CS
AO
1/08
1/07
1/06
1/01
1/05
1/04
VSS
Pin Names
AO-A10
Address Inputs
WE
Write Enable
~
OJ:
Chip Select
1/01 -1/08
Output Enable
Capacitance
Data Input/Output
Ta
VCC
Power (+5V)
VSS
Ground
OE
WE
MODE
1 MHz
LIMITS
Symbol
Min -rTyp
Input Capacitance
CIN
POWER
liD Capacitance
CliO
I
I
Standby
This parameter is sampled and not 100% tested.
Parameter
lI'uth Table
CS
= 25°C, f=
1/0
H
X
X
Not Selected
High-Z
L
L
H
Read
Dout
Active
L
H
L
Write
Din
Active
L
L
L
Write
Din
Active
REV/1
63
1 Max
1 5
T
7
Unit Test Conditions
pF
V,N
pF
VI/O
= OV
= OV
--
J.lPD4016
DC Characteristics
Ta
= o'e to To'e, Vee = 5V
AC Characteristics
:I: 10%
Raad Cycle
Ta
o'e to
=
To'e, Vee 5V :I: 10%
LIMITS
Parameter
Symbol
Min.
Typ.
LIMITS
Max.
Unit Test Conditions
= Max
= GND 10 VCC
VCC = Max, CS = VIH
VOUT = GND 10 VCC
VCC = Max, CS = VIL
VCC
VIN
Input Leakage Current
III
10
J1.A
?utput Leakage Currenl
ILO
10
J1.A
Oper.ating Currenl
ICC
60
rnA
15
VCC • Min 10 Max
rnA
CS VIH
OulpUIS Open
Standby Current
ISB
Input Low Voltage
VIL
-1.5
0.8
2.0
6.0
V
0.4
V
10L
V
10H = lmA
Inpul High Voltage
VIH
Output Low Voltage
VOL
Output High Voltage
VOH
2.4
Output Short Circuit
Current
lOS
TBD
TBD
Parameter
=
V
= 4mA
mA VOUT
= GND to VCC
AC Test Conditions
Input Pulse Levels ................. . o.aVto 2.2V
Input Rise and Fall Times ........... . 10nsec
Input Timing Reference Levels
1.SV
Output Timing Reference Levels ..... . 1.5V
Symbol
J1.PD4016-3 J1.PD4016-2 J1.PD4016-1
Min Max Min. Max. Min. Max.
Unit
Notes
150
nsec
1
Read Cycle Time
IRC
Address Access TIm"
tAA
150
200
250
nsec
Chip Select
Access TIme
tACS
150
200
250
nsec
250
200
2
Output Hold from
Address.Change
tOH
10
10
10
nsec'
Chip Selection to
Output in Low Z
ILZ
10
10
10
nsec
3,4
Chip Deselection to
Output in High Z
tHZ
50
60
80
nsec
3,4
Output Enable to
Output Valid
10E
70
90
110
nsec
Output Enable to
Output in Low Z
tOLZ
Output Disable to
Output In High Z
10HZ
Chip Selection to
Power up TIme
IpU
Chip Deselection to
Power down TIme
IpD
Write Cycle
Ta = o'e to
10
10
50
0
10
60
0
70
80
0
90
110
nsec
3,4
nsec
3,4
nsec
4
nsec
4
Unit
Notes
To'e, Vee 5V :I: 10%
LIMITS
Parameter
+5V
1KIl
1/0------+---,
870n
Symbol
J1.PD4016-3 J1.PD4016-2 J1.PD4016-1
Min Max. Min Max Min Max.
Wrlle Cycle TIme
IWC
150
200
250
nsec
Chip Selection 10
End of Write
tcw
120
160
200
nsec
Address Valid to
End of Write
lAW
90
120
150
nsec
nsec
Address Selup TIme
lAS
0
0
0
100PF
Wrile Pulse Widlh
IWp
80
100
130
nsec
(Including Scope and Jig)
Write Recovery TIme
r
Figure 1 - Output Load
+5V
IWR
10
10
10
nsec
Data Valid to
End of Write
lOW
50
60
80
nsec
Data Hold TIme
IDH
0
0
0
Write Enabled to
Output In Hlgh·Z
IWZ
Output Active
from End of Write
lOW
50
10
60
10
nsec
80
10
5
nsec
6,7
nsec
6,7
Noles:
1. All Read Cycle timings are referenced from the last valid address to the
first transitioningaddress.
_
2. Address valid prior to or coincident with CS transition low.
3. Transition is measured ± 200mV from steady state voltage with specified load of Figure 1 .
4. This parameter is sampled and not 100% tested.
5. If CS and DE are both low before write enabled, tWP = tWZ + DW
6. Transition is measured ±200mV from steady state voltage with specified loading in Figure 2.
7. This parameter is sampled and not 100% tested.
1/0------+-.......,
Figure 2 - Transition Load
64
~PD4016
Timing Waveforms
Write Cycle No.1 (WE Controlled)
I~-----------------twc----------------------
Address
I~-----------tcw--------------I
-tAS-
Data In
_twz_
Data Out
Write Cycle No.2 (CS Controlled)
I~----------------twe----------------------I
l--,tA-,-,S~>---______
lew ___________
Data In
Data Out - - - - - - - - H
65
__ I
JAPD4016
Read Cycle No.1
®
@ @
Address
_~H'AAE
10
4
Vee (V)
IOH (mAl
VOL - IOL (Ta)
tA - VCC (Ta)
0.6
700
0.5
600
0.4
500
;;~
>
0.3
0.2
300
0.1
200
10
oL
15
5
Vee (V)
IOL (mA)
tA-CL
ICCDR -Ta
700
To" 2s"e
Vee ~ 5V
600
500
]
400
;f.
.--
300
-
~
I--
-
~
1.0 ~
9~'-l~
eE2 • +O.2V
.::::;;"'f'-l~ : -
VI" 0 to Vee
c~
~
"
0
~
./'1 .A?
0.1
.~'-l
I-- _'-lee
I
I
0.01
200
--I-100
200
300
400
500
10
20
eL (pF)
30
40
60
60
70
Tare)
PACKAGE OUTLINE
J,LPD5101LC
ITEM
A
G
M
MILLIMETERS
INCHES
1.10Max.
28.0 Mo •.
1.4 Max.
2.54
0.60 0.10
25.4
1'.40
2.54 Min.
O.SMln.
4.7 Max.
5.2 Max.
10.16
8.5
0.18 Max.
0.20 Max.
0.40
0.33
0.25 ~:~~
0.01
0.025Max.
0.10
0:02 0.004
1.0· •
0.055"
0.10Mln.
0.02 Min.
~:::
5101 LDS-R EV1-12-B1-CAT
73
NOTES
74
NEe
IlPD444
IlPD444-1
IlPD444-2
IlPD444-3
NEe Electronics U.S.A. Inc.
Microcomputer Division
1024
DESCRIPTION
X
4-BIT STATIC CMOS RAM
TheJ1PD444 is a high-speed, low power silic'on gate CMOS 4096 bit static RAM organized 1024 words by 4 bits. It uses DC stable (static) circuitry throughout and therefore requires no clock or refreshing to operate. Data access is particularly simple since
address setup times are not required. The data is read out non-destructively and has
the same polarity as the input data. Common input/output pins are provided.
CS controls the power down feature. In less than a cycle time after CS goes high deselecting the J1PD444 - the part automatically reduc~ts power requirements
and remains in this low power standby mode as long as CS is high. There is no minimum CS high time'for device operation, although it will determine the length of time
in the power down mode. When CS goes low, selecting the J1PD444, the J1PD444
automatically powers up.
The J1PD444 is placed in an l8-pin plastic package for the highest possible density.
It is directly TTL compatible in all respects: inputs, outputs, and a single +5V
supply. The J1PD444 is pin-compatible with the J1PD2ll4L NMOS Static RAM.
Data retention is guaranteed to 2 volts on all parts. These devices are ideally suited
for low power applications where battery operation or battery backup for nonvolatility is required.
F EA TU R ES
• Low Power Standby - 1 J1A Typ.
•
•
•
•
•
•
•
•
•
•
•
•
•
PIN CONFIGURATION
Low Power Operation
Data Retention - 2.0V Min.
Capability of Battery Backup Operation
Fast Access Time - 200-450 ns
Identical Cycle and Access Times
Single +5V Supply
No Clock or Timing Strobe Required
Completely Static Memory
Automatic Power-Down
Directly TTL compatible: All Inputs and Outputs
Common Data Input and Output using Three-State Outputs
Available in a Standard l8-Pin Plastic Package
For Operation at +3V Power Supply, Contact the NEC Sales Office.
A6
Vee
A5
A7
AO-A9
Address Inputs
A4
AS
WE
Write Enable
A3
Ag
CS
Chip Select
Ao
1/01
1/01- 1/04
Data Input/Output
Al
1/02
A2
1/03
cs
GND
1/04
WE
Rev/2
75
PIN NAMES
VCC
Power (+5V)
GND
Ground
II
:
~
",PD444
BLOCK DIAGRAM
A4
~
,.::J
~
AS
ROW
~
SELECT
A)
~
Ag
__.__GND
MEMORY ARRAY
64 ROWS
64 COLUMNS
·
~
AS
---vee
··
AS
f--
. ·1
~
1,01
~
f--
:>.
~
~
1'°2
INPuT
DATA
~
1/°3
CONTROL
~
1/0 4
1•
~
~
COLUMN 1·0 CIRCUITS
~~~~ ~
COLUMN SELECT
A,
AO
!
A2
r~
AJ
. . . . .. _40° e to +85° e
.. -55°e to +125°C
-0.3 to Vee +0.3 Volts CD
. ....... +8.0 Volts
Operating Temperature ....
Storage Temperature.
All Input and Output Voltages . . . . . . . . . . .
Supply Voltage .......... .
CD
f--
L
r~
Note:
I---
ABSOLUTE MAXIMUM
RATINGS*
With Respect to Ground
Ta = 25°e
'COMMENT: Stress above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this .peclfication is not
implied. Exposure to absolute maximum rating conditions for extended period. may affect device
reliability .
Ta
= -40
0
e to +85°e; Vee
= +5V
±
DC CHARACTERISTICS
10% unless otherwise noted.
LIMITS
444·3
PARAMETER
SYMBOL
MIN
TYP
444·2
MAX
MIN
444
444·1
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
TEST CONDITIONS
Inout Leakage Current
III
-1.0
1.0
-1.0
1.0
-1.0
1.0
-1.0
1.0
"A
VIN "GNO to Vce
I/O Leakage Current
ILO
-1.0
1.0
-1.0
1.0
-1.0
1.0
-1.0
1.0
"A
es
<
VIH. VI/a" GNO
to Vee
Operating SUpply
leeAl
19
35
15
35
12
35
9
35
mA
es" VIL. VIN "Vee.
Outputs Open
leeA2
23
'0
'9
40
15
40
12
40
mA
es = VIL. VIN" 2.4V.
leeA3
10
20
9
20
8
20
7
20
mA
VIN • GNO or Vee.
Outputs Open f =: 1 MHz,
Current
Average Operating
Supply Curren I
~
____________~____~-+__+-____4-__.~~____~__~+-____+-~~_~____-+__-+~O~ut~y=50~%~__ ..____
1
Standby Supply Current
Ices
Input Low Voltage
VIL
-0.3
2.4
1
5
50
"A
es
10
Input HIgh Voltage
VIH
Output Low Voltage
VOL
Output HIgh Voltage
VOH
Ta
=
2S··C. f
=
0.8
-0.3
Vee + 0.3
2.4
0.4
2.4
0.8
-0.3
Vee + 0.3
2.4
0.4
-0.3
Vee + 0.3
2.4
2.4
2.4
= Vee.
VIN
Vee
0.8
Vee + 0.3
0.4
0.4
1 MHz
PARAMETER
0.8
2.4
CAPACITANCE
SYMBOL
LIMITS
MIN' TYP MAX
Input/Output CapacItance
CliO
10
Input Capacitance
CIN
S
UNIT
TEST CONDITIO
pF
VI/O = OV
pF
VIN = OV
Note: This parameter is periodically sampled and not 100% tested.
76
= GNO
",PD444
AC CHARACTERISTICS
T•• -40·C to +85·C; Vcc = +5V ± 10% unless otherwise noted.
I
LIMITS
PARAMETER
I
444·3
I
444.·2
I
I
I
I
I
I
I
444,,'
444
I
I
I
SYMBOL MIN MAX MIN MAX MIN MAX MIN MAX UNIT
TEST CONDITIONS
READ CYCLE
Read Cycle
'RC
Address Access Time
'AA
'ACS1
Chip Select Access Time Q)
C,hiP Select Access Time (6J
200
Chip Selection to Output in Low Z
'ACS2
'OH
'LZ
Chip Deselect ion to Output in High Z
'HZ
Output Hold from Address Change
250
450
300
200
250
250
300
200
250
50
20
50
20
50
20
80
Input Pulse Levels:
+0.8 to +2.4 Volts
Input Rise and Fall
Times: 10 ns
Input and Output Timing
Levels: 1.5 Volt
Output Load: 1 TTL
Ga'. and CL • 100 pF
50
20
70
60
n'
450
450
500
300
JOO
350
100
WRITE CYCLE
W(lts Cycle Time
LOW VCC DATA
RETENTION
CHARACTE RISTICS
n'
n,
n,
Levels: 1.5 VOl'
Ou'pu' Load: 1 TTL
Ga'. and CL • 100 pF
0
'WR
Notes:
200
'DH
Write Recoverv Time
0
0
'wz
Output Active from End of Write
JOO
150
'OW
'WP
l
230
0
140
120
'AS
Da'a Hold Time
210
180
'AW
Address Setup Time
Write Pulse Width
Write Enabled to Output in High
Input Pulse Levels'
+0.8 to +2.4 Volts
Input Rise and Fall
Times: 10 ns
Input and Output Timing
250
230
'cw
Address Valid to End of Write
Data Valid to End of Write
450
350
350
n,
230
300
250
250
200
180
180
'WC
Chip Selection to End of Write
70
60
80
100
'OW
CD
Chip deselected for greater than 100 ns prior to selection.
(i)
Chip deselected for a finite time that IS less than 100 ns prior to selection. (If the deselect time is
selected and access occurs according to Read Cycle No.1,)
a ns, the chip is by definition
LIMITS
PARAMETER
SYMBOL
Data Retention Supply
Voltage
VCCDR
Data Retention Supply
Current
ICCDR
Chip Deselect to Data
Retention Time
tCDR
Operation Recovery
Time
tR
Notes:
CD
(3)
MIN
TYP
MAX
2.0
UNIT
TEST CONDITIONS
V
CS = VCC,VIN = VCC
to GND
0.01
VCC - 3V, CS = VCC
VIN = VCC to GND
IJA
(2)
ns
0
ns
tRCC!)
tRC = Read Cycle Time
444-1, -2, -3: Value is 2 J.lA
444 Value is 10 J.lA
TIMING WAVEFORMS
READ CYCLE
ADDRESS
DOUT
=1
'AA
'OH
.
.,1
'
PREVIOUS DATA VALID
READ CYCLE
Cs
CD®
IRC
f
XX
DATA VALID
CDCID
.~
~~'"
IACS--
r..'HZ
ILZ
DOUT
DATA VALID
HIGH
IMPEDANCE
HIGH IMPEDANCE
77
IJ
IlPD444
® ® ®
WRITE CYCLE
twc
ADDRESS
.
tcw
~Ir-
\
-J I I
.
tAW
tWR
_twp_
r-----tAS_
)C-
\-'r
~
7
""""tDH
tDW
1
/
'V DATA IN
'\~
twz
'\
DOUT
'\
'\
'\
'\
'\
'\
11//1/L
Notes
IIIII
'\:J
/.Ij
VVVVVV
1"i. L~1'ILJ'\ n 1'\.
VALID
I
~,
~ /
~ \. \.
HIGH IMPEDANCE
/
/
/
\. \. \.
CD WE is high lor Read Cycles.
o
o
@
Device
IS
continuously selected,
CS
= VIL
Address valId prior to or COincident with
CS transition
low.
If the Cs low transition occurs simultaneously wIth the
output buffers remain in a high Impedance state.
WE
low transition, the
® WE must be high during all address tran.itions.
® twp is measured Irom the latter of CS or WE gOing low to the earlier of CS or WE
going high.
LOW VCC DATA RETENTION
DATA
VCC
----------------~I
VCCDR
OV - - - - - - - - - - - - - - - - - - - - - - - - -
I-
~
~
L
H~'
T
B'J
I
J.LPD444C
TT
,~
"
I '
:
PACKAGE OUTLINE
-I
A
c
E
-g--
JU'~
F •
i
G
.
Plastic
ITEM
A
MILLIMETERS
23.2 MAX.
1.44
0.055
2.54
0.1
0,45
0.02
20.32
0.8
1.2
0.05
2.5 MIN.
0.1 MIN.
0.5MIN.
0.02 MIN.
4.6 MAX.
0.18 MAX.
5.1 MAX.
M
INCHES
0.91 MAX.
0.2 MAX.
7.62
0.3
6.7
0.26
0.25
0.01
78
444R E V2-12-81-CA T
NEe
IlPD446
IlPD446-1
IlPD446-2
IlPD446-3
NEe Electronics U.S.A. Inc.
Microcomputer Division
2048 X 8-BIT STATIC CMOS RAM
OESCR IPTION
The t./PD446 is a high speed, low power, 2048 word by 8 bit static CMOS RAM
fabricated using an advanced silicon gate CMOS technology. A unique circuitry
technique makes the t./PD446 a very low operating power device which requires
no clock or refreshing to operate. Minimum standby power current is drawn by this
device when CS' equals VCC independently of the other input levels.
Data retention is guaranteed at a power supply voltage as low as 2V.
The t./PD446 is packaged in a standard 24-pin dual-in-line package and is plug-in
compatible with 16K EPROMs.
F EA TU R ES
• Single +5V Supply
Fully Static Operation - No Clock or Refreshing required
TTL Compatible - All Inputs and Outputs
Common I/O Using Three-State Output
OE Eliminates Need for External Bus Buffers
Max Access/Min Cycle Times Down to 150 ns
Low power Dissipation, 18 mA Max Active/10 t./A Max Standby/
10 t./A Max Data Retention
• Data Retention Voltage - 2V Min
• Standard 24-Pin Plastic and Ceramic Packages
• Plug-in Compatible with 16K EPROMs
• Operating Temperature Range - -40°C to +85°C
•
•
•
•
•
•
PIN ·CONFIGURATION
A7
Aa
2
Ag
21
WE
AO-A10
Address Inputs
5
20
DE'
WE
Write Enable
19
A10
DE
Output Enable
1S
cs
CS
Chip Select
I/OH/08
Data Input/Output
VCC
Power (+5V)
GND
Ground
6
t./PD
446
8
1/01
AS
4
A1
AO
VCC
22
A5
A2
24
23
17
I/OS
16
9
PIN NAMES
1/07
1/02
10
15
I/oa
1/03
11
14
1/05
12
13
1/04
TRUTH TABLE
CS
DE
WE
MODE
H
X
X
NOT SELECTED
L
H
H
L
L
H
L
X
L
I/O
ICC
HZ
STANDBY
NOT SELECTED
HZ
ACTIVE
READ
DOUT
ACTIVE
WRITE
DIN
ACTIVE
79
IlPD446
BLOCK DIAGRAM
A4
A6
A6
A7
CELL ARRAY
128 ROWS
128 COLUMNS
ADDRESS
BUFFER
A8
A9
Al0---L._ _-'
I/:l __-+_ _
~
INPUT
SENSE SWITCH
DATA
I
COLUMN
DECODER
1/~8 _ _-+-_....HCONTROL
OUTPUT
DATA
CONTROL
WE~~~l-r-------------------------~
Supply Voltage . . . . . . . . . . . .
Input or Output Voltage Supplied
Storage Temperature Range "
Operating Temperature Range.
............ 7.0V
.. -0.3 to Vee + 0.3V
-55°C to 125°C
. . . . . -40°C to +85°C
ABSOLUTE MAXIMUM
RATINGS*
Ta = 25°C
*eOMMENT: Stress above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and functional operation of th®@
200± 50/0
28+00/0-20/0
20 ± 0.5
28+ 00/0- 20/0
70 max.
Sense current Interruption
bafore and after address
change
R1
15Vpolnt/
150n load.
700/0 min.
Sense current
Amplitude
Clamp voltage
Ramprste
300Q
mA
V
70 max.
7.5± 50/0
Duty cycle
VCC
Note.
25± 5
Ambient Temparature
Test
Conditions
Unit
Limit
Characteristic
J.l-PB408·1 J.l-PB408·2
J.l-PB428·1 J.l-PB428·2
mA
V
V/J.l-B
15Vpolnt/
150n load.
10mln.
5.0+ 50/0- 00/0
Progremmlng Vee
Maximum sensed voltage
for program mad one
7.0± 0.1
Dalay from trailing adge of
programming pulee before
sanBlng output voltage
O.7mln.
V
v
, . . . . . . - - - - - - -...- - - - - - - - 01 (OUT)
600Q
Addi~ Train
~~
Figure 1
I
710·~51'S
~
IJS
0.71'5
Notes:
CD Output Load: See Figure 1.
® Input Waveform: O.OV for low level and 3.0V for high level, less than 10
ns for both rise and fall times.
@ Measurement References: 1.5V for both inputs and outputs.
@ Ct. in Figure 1 includes jig and probe stray capacitances.
MIN.
___ .- 28V Clamp
_ _ -_'200mAprogrampUlse
-
::::::::-:>'7.0V Ref.
---101'5
~
Output Voltage Sensing
Figure 2 - Typical Output Voltage Waveform
94
·---l00mA Point
=.- --- 20 mA Sensing (Before PI
,"'"
' , : 20 mA SenSing (After PI
'GND
",PB406/426
Package Outlines
jLPB406/426C PLASTIC
jLPB406/426D CERDIP
~ ~ -~
~
IF ~;.;~:\=
II'
::
-M
'
0-15 -j
-
Cerdlp
Plastic
Item
Millimeters
Item
Millimeters
A
23.2 Max.
0.91 Max.
A
23.2 Max.
0.91 Max.
B
1.44
0.055
B
1.44
0.055
C
2.54
0.1
C
2.54
0.1
0
0.45
0.02
0
0.45
0.02
E
20.32
0.8
E
20.32
0.8
0.06
Inches
Inches
F
1.2
0.06
F
1.2
G
2.5 Min.
0.1 Min.
G
2.5 Min.
0.1 Min.
H
0.5 Min.
0.02 Min.
H
0.5 Min.
0.02 Min.
I
4.6 Max.
0.18 Max.
I
4.6 Max.
0.18 Max.
J
5.1 Max.
0.2 Max.
J
5.1 Max.
0.2 Max.
K
7.62
0.3
K
7.62
0.3
L
6.7
0.26
L
6.7
0.26
M
0.25
0.01
M
0.25
0.01
Qualified Programming Equipment
Approved
Manufacturer
Data 1/0
Issaquah, WA
Mlnato Electronics
Tokyo, Japan
Takeda Rlken
Tokyo,Japan
Tokyo Data
Tokyo, Japan
Model No.
Personality
Module
Socket Adaptors
715-1305-5
5, 7, 9, 17, 19
919-1555
1802
/APB4XX
SA-18/B426
TR-429 B
PZ 3834
WZ3256-78
PECKER-O
UN-711F
AD-7115
406/4260S-REV1-1-82-CAT
95
II
NOTES
96
NEe
IlPB409
IlPB429
IlPB409-1
IlPB429-1
IlPB409-2
IlPB429-2
NEe Electronics U.S.A. Inc.
Microcomputer Division
2048 WORD BY 8 BIT BIPOLAR TTL
PROGRAMMABLE READ ONLY MEMORY
DESCRIPTION
FEATURES
PIN CONFIGURATION
The J,LPB409 and J,LPB429 are high-speed, electrically programmable, fully-decoded
16384 bit TTL read only memories. On-chip address decoding, three chip enable
inputs and open-collector/three-state outputs allow easy expansion of memory
capacity. The J,LPB409 and J,LPB429 are fabricated with logic level zero (low); logic
level one (high) can be electrically programmed into the selected bit locations. The
same address inputs are used for both programming and reading.
• 2048 WORDS x 8 BITS Organization (Fully Decoded)
• TTL Interface
• Fast Read Access Time
:50 ns MAX
• Medium Power Consumption :500 mW TYP
• Three Chip Enable Inputs for Memory Expansion
• Open-Collector Outputs (J,LPB409)
• Three-State Outputs (J,LPB429)
• Ceramic 24-Lead Dual In-Line Package (J,LPB409D, /-LPB429D)
• Plastic 24-Lead Dual In-Line Package (J,LPB409C, J,LPB429C)
• Fast Programming Time
:200 /-Ls/bit TYP
:82S190/191
• Replaceable with
HM76160/76161, 3636
and Equivalent Type Devices
A7
VCC
A6
AS
AS
Ag
A4
A10
A3
CE1
PIN NAMES
CE2
AO-A1O
Address Inputs
A1
CE3
CE1-CE3
Chip Enable Inputs
AO
Os
°1-0S
Data Outputs
A2
01
°7
°2
06
03
Os
GND
°4
Rev/1
97
IlPB409/429
. . . . . . . . . . . . . . . . . . . . . . -0.5 to +7.0V
. -0.5 to +5.5V
. . . . . . . . . . . -0.5 to +5.5V
. . . . . . . . . . . . . . . . 50mA
Supply Voltage
Input Voltage ..... .
Output Voltage ..... .
Output Current . . . . . . . . .
Operating Temperature
Storage Temperature
Ceramic Package . . . . . . . . .
Plastic Package . . . . . . . . . .
Ta
=
ABSOLUTE
MAXIMUM RATINGS*
.-65°C to +150°C
. .-55°C to +125°C
25°C
*COMMENT: Stress above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability .
CHARACTERISTIC
SYMBOL
MIN
TYP
UNIT
MAX
Input High Voltage
VIH
Input Low Voltage
VIL
Input High Current
IIH
Input Low Current
-IlL
Output Low Voltage
VOL
Output Leakage Current
10FFl
40
/loA
Output Leakage Current
-IOFF2
40
/loA
Input Clamp Voltage
-VIC
2.0
0.85
40
0.25
V
/loA
VI:5.5V. Vcc=5.5V
mA
VI=0.4V. VCC:5.5V
0.45
1.3
Power Supply Current
ICC
Output High Voltage'
VOH
2.4
Output Short Circuit Current'
-ISC
20
DC CHARACTERISTICS
TEST CONDITIONS
V
100
160
V
10=16 m.
G>
®
The tolerance of 0.6V allows the use of a driver circuit for switching the VPP
supplV pin from +25V to +5V.
During progremming. program inhibit. and program verify. a maximum of +26V
should be applied to the Vpp pin. Overshoot voltages to be generated bv the Vpp
power supplV should be limited to less than +26V.
"PD2716 450 ns
"PD2716·2 390 ns
107
,..PD2716
READ MODE
ADDRESSES VALID
Ao-l0
~/PGM
00.7
----+_
-;JS-
----------oHot+<
HIGH IMPEDANCE
PROGRAM MODE
Ao-l0
VALID INPUT
ADDRESS N +.m
O()'7
CE/PGM _ _ _ _ _ _ _ _ 1
Not.:
uring programming, all inputs are TTL levels
except for OE/Vpp which is pulsed from TTL level to 25V.
Output Enabla High
to Output Float
Addreaa to Output Hold
Ie,.
Note: (j) "PD2732~ (450 ns max)
"PD2732-4 (390 ns max)
,Read Mode
Test Conditions Output Load: 1 TTL gate and CL = 100 pF
Input Rise and Fall TImes: 20 ns
Input Pulse Levels: 0.8 to 2.2V
TIming Measurement Reference Level:
Inputs: 1.0V and 2_0V
Outputs: 0.8V and 2.0V
When CE and OE/Vpp are at low (0) level, READ is set and
data is available at the outputs after toE from the falling
edge of DE and ~cc after setting the address.
Standby Mode
Program, Program Verify and Program Inhibit Mode
T. = 25°C ± 5°C; Vee = +5V ± 5%; V pp = +25V ± 1V
Uml'a
Parameter
Addrea. Setup lime
Symbol
Min
T)E/V••
ICC2
150
mA
OE/V.. =
= V"
Ce = V"
IAPD2732A
DC Characteristics (Cont.)
Er asure of the IAPD2732A programmed data can be
attained when exposed to light with w~velengths shorter
than approximately 4,000 Angstroms (A). It should be noted
that constant exposure to direct sunlight or room level
fluorescent lighting could erase the IAPD2732A. Consequently, if the IAPD2732A is to be exposed to these types
of lighting conditions for long periods of time, its window
should be masked to prevent unintentional erasure.
The recommended erasure procedure for the IAPD2732A is
exposure to AJltraviolet light with wavelengths of 2,537
Angstroms (A). The integrated dose (Le., UV intensity x
exposure time) for erasure should be not less than
15 W-seclcm2. The erasure time is approximately 15 to 20
minutes using an ultraviolet lamp of 12,000 IAW/cm 2 power
rating.
During erasure, the IAPD2732A should be placed within
1 inch of the lamp tubes. If the lamps have filters on the
tubes, the filters should be removed before erasure.
Program, Program Verity and Program Inhibit Mode
Ta - 25 ± 5°C, Vee" +5V ± 1%, V pp = +21V ± O.IV
Limite
Paramatar
Input High Voltage
Svmbol
Input Low VollIIge
V'H
VIL
Input L..klge CUI •• nt
ILl
Output High Voltage
VOH
Output Low Voltlge
VOl
Vee Current
Icc
V•• Current
I..
Min
1)'p
2.0
-0.1
.85
Ma.
Unit
Vee +1
V
0.8
V
0.45
V
150
mA
Taat Conditione
101. = 2.1 mA
AC Characteristics
Read Mode and Standby Mode
T. = O°Cto + 70°C; Vee = +5V ± 5%
Limite
Paramatar
Svmbol
Min
1)'p
Ma.
Unit
Addre.. to Output Delay
tAce
250
ne
'ire to Output Delay
~=~'P=VIL
leE
250
ne
'OE= VIL
Output Eneble
to Output Delay
to.
100
ne
CE=V"
Output Enable High
to Output Float
tOF
Addre.. to Output Hold
~
10
90
Taet Conditione
Operation
n.
~=VIL
ne
~=tm= VOl
The five operation modes of the IAPD2732A are listed in
Table 1. In READ mode, the only power supply required is
a + 5V supply. During programming, all inputs are TTL
levels except for OEIV pp which is pulsed from TTL level to
21V.
Test CondltlonsOutput Load: 1 TTL gate and CL = 100 pF
Input Rise and Falillmes: 20 ns
I"put Pulse Levels: 0.8 to 2.2V
llmlng Measurement Reference Level:
Inputs: 1.0Vand 2.0V
Outputs: 0.8V and 2.0V
Read Mode
When CE and OEIV pp are at low (0) level, READ is set and
data is available at the outputs after tOE from the falling
edge of OE and t ACC after setting the address.
Standby Mode
Program, Program Verity and Program Inhibit Mode
Ta = 21°C ± 5°C, Vce = +5V ± 5%; Vpp = +21V ± O.SV
The IAPD2732A is placed in standby mode with the application of a high (1) level TTL Signal to the CE input. In
this mode, the outputs are in a high impedance state,
independent of the OEIV pp input. The active power
dissipation is reduced by 75% from 788 mW to 184 mW.
Llmne
Paramatar
Svmbol
Min
1)'p
Ma. Unit
Addre •• Setup 11me
t.s
MSetup11me
to,s
/L.
Oltl Setup 11me
tos
/L-
Addre.. Hold 11m.
t' H
/L/L-
CSl Hold 11me
Taet Conditione
/L.
Olt_ Hold 11m.
to'H
tOH
Output Enable to Output
FlolltOelllY
tOF
Oltl Valid from CE
tov
Progrlm Pulle Width
tpw
45
Progrlm Pulse Rise
11me
t pRT
50
V •• Recovery 11me
tVR
Programming
/Le
130
ne
55
me
/L-
50
~= VIL'~=
VIL
n.
/Le
Test Conditions Input Pulse Levels = 0.8V to 2.2V
Input llmlng Reference Level = 1.0V and 2.0V
Output llmlng Reference Level = 0.8V and 2V
Input Rise and Fall Times: 20 ns
Function
The IAPD2732A operates from a single + 5V power supply,
making it ideal for microprocessor applications.
Programming of the IAPD2732A is achieved with a single
50 ms TTL pulse. Total programming time for all 32,768 bits
is only 210 sec. Due to the simplicity of the programming
requirements, devices on boards and in systems may be
easily programmed without any special programmer.
The IAPD2732A features a standby mode which reduces the
power dissipation from a maximum active power dissipation
of 788 mW to a maximum standby power dissipation of
184 mW. This results in a 75% savings with no increase in
access time.
Programming begins with erasing all data and consequently having all bits in the high (1) level state. Data is
then entered by programming a low (0) level TTL signal
into the chosen bit location.
The IAPD2732A is placed in programming mode bY"'!pplying a high (1) level TTL signal to the CE and with OEIV pp at
+ 21V. The data to be programmed is applied to the output
pins in 8-bit parallel form at TTL levels.
Any location can be programmed at any time, either individually, sequentially or at random.
When multiple IAPD2732As are connected in parallel, except
for CE, individuailAPD2732As can be programmed by applying a low (0) level TTL pulse to the CE input of the desired
IAPD2732A to be programmed.
Programming of multiple IAPD2732As in parallel with the
same data is easily accomplished. All the like inputs are
tied together and .E!Pgrammed by applying a low (0) level
TTL pulse to the CE inputs.
Programming Inhibit Mode
Programming multiple IAPD2732As in parallel with different
data is easier with the program inhibit mode. Except for CE,
all like inputs (including OE) of the parallel IAPD2732As may
be common. Programming is accomplished by apE!Ying
tile TTL-level program pulse to the CE input with OEIV pp at
-I- 21V. A high (1) level applied to the CE of the other
I1PD2732A will inhibit it from being programmed.
116
Timing Waveforms
",PD2732A
RINd Mode
Add...... VIIIIcI
0 ..,
High Impedance
_~~I--
VIIliclOlltput
_______ ., _ _ _...,...~
High Impedanca
Notes: H
0
Clock Voltage Low
V>L
-6.0
Input Leakage Current High
iNT,
V
CLO Input, External Clock
VGG
V
CLO I nput, External Clock
ILiH
+10
/loA
Ports A through 0, INT,
RESET, VI = -lV
Input Leakage Current Low
ILiL
-10
/loA
Ports A through 0, INT,
RESET, VI = -11V
Clock Input Leakage Current High
IL>H
+200
/loA
CLO Input, V>H
Clock Input Leakage Current Low
IL>L
-200
/loA
CLO 'nput, V>L
-0.8
= OV
= -llV
VOHl
-1.0
V
Ports C through I,
IOH ·-1.0mA
VOH2
-2.3
V
Ports C through I,
IOH =-3.3 mA
-10
/loA
Ports C through I,
VO=-llV
-50
mA
Output Voltage High
Output Leakage Current Low
ILOL
Supply Current
IGG
-30
Ta = 25°C
CAPACITANCE
LIMITS
PARAMETER
MAX
UNIT
Input Capacitance
CI
15
pF
Output Capacitance
Co
15
pF
Input/Output Capacitance
CIO
15
pF
Ta
a
SYMBOL
MIN
TYP
TEST
CONDITIONS
f = 1 MHz
-10°C to +70°C; VGG - -10V ± 10%
AC CHARACTERISTICS
LIMITS
PARAMETER
SYMBOL
MIN
TYP
MAX
Oscillator Frequency
f
Rise and Fall Times
tr,lf
0
0.3
Clock Pulse Width High
!WH
0.6
6.6
Clock Pulse Width Low
!WL
0.6
6.6
150
440
UNIT
TEST
CONDITIONS
KHz
,.5
,.,
,.s
~----------1/f------------~
EXTERNAL CLOCK
CLOCK WAVEFORM
Vss
V~H
158
546DS-1-82-CAT
NEe
I'PD557L
NEe Electronics U.S.A. Inc.
Microcomputer· Division
4-BIT SINGLE CHIP MICROCOMPUTER WITH
VACUUM FLUORESCENT DISPLAY DRIVE
CAPABILITY
DESCRIPTION
The~PD557L is a 4-bit single chip microcomputer which has the same architecture as
the ,l.LPD553, but is pin-compatible with the ~PD550L and the ~PD554L. The ~PD557 L
contains a 2000 x 8-bit ROM and a 96 x 4-bit RAM, which includes six working registers and the FLAG register. It has a lever-triggered hardware interrupt input INT, a
three-level stack and a 6-bit programmable timer. The ~PD557 L provides 21 I/O lines,
organized into the 4-bit input port A, the 4-bit I/O ports C and 0, and the 4-bit output
ports E and F, and the l-bit output port G. The 17 I/O ports and output ports are
capable of being pulled to -35V in order to drive Vacuum Fluorescent Displays directly.
The ~PD557L typically executes all 80 instructions ohhe extended ~COM-4 family
instruction set with a 25 ~s instruction cycle time. It is manufactured with a modified
PMOS process, allowing use of a single -8V power supply and is available in a 28-pin
dual-in-line plastic package.
The pPD550L andthe ~PD554L are upward-compatible with the pPD557L.
PIN CONFIGURATION
Cl,
PIN NAMES
Clo,
PCo
2
VGG
PAO-PA3
Input Port A
PC,
3
RESET
PCO-PC3
Input/Output Port C
PC2
4
iNT
PDO-PD3
Input/Output Port D
PC3
5
PA3
PEO-PE3
Output Port E
PDo
6
PA2
PFO-PF3
Output Port F
PA,
PGO
jjiji'
Output Port G
PD,
~PD
PD2
557L
8
PAO
PD3
9
PGo
PEO
10
PF3
PE1
11
PF2
PE2
12
PF,
PE3
13
PFo
VSS
14
TEST
ClO-Cl1
Interrupt Input
External Clock Signals
RESET
Reset
VGG
Power Supply Negative
VSS
TEST
Power Supply Positive
Factory Test Pin
(Connect to VSS)
ABSOLUTE MAXIMUM Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -10°Cto+70°C
RATINGS* Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +125°C
Supply Voltage, VGG . . . . . . . . . . . : . . . . . . . . . . . . . . . . . . . . . -: 15 to +0.3V
Input Voltages (Port A, iN"T, RESET) . . . . . . . . . . . . . . . . . . . . . . -15 to +0.3V
(Ports C, D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 to +0.3V
Output Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 to +0.3V
Output Current (Ports C, 0, each bit) . . . . . . . . . . . . . . . . . . . . . . . . . " -4 mA
(Ports E, F, G, each bit) . . . . . . . . . . . . . . . . . . . . . . " - 25 mA
(Total, all ports) . . . . . . . . . . . . . . . . . . . . . . . . . . .. -100 mA
*COMMENT: Stress above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
Rev/1
159
P.PD557L
DC CHARACTERISTICS
LIMITS
PARAMETER
JlYMBOL
Input Voltage High
Input Voltage Low
MIN
TYP
MAX
,'EST
CONDITIONS
UNIT
V,H
0
-2.5
V
Ports A. C. 0, INT. RESET
VIL1
-6.5
VGG
V
Ports A, INT. RESET
V,L2
-6.5
-35
V
Ports C. 0
Clock Voltage High
V.pH
0
-0.6
V
CLO Input; External Clock
Clock Voltage Low
V.pL
-5.0
V
CLO Input. External Clock
Input Leakage Current High
IUH
+10
JlA
lULl
-10
JlA
IUL2
-30
JlA
Ports C. D. V,--35V
'L.pH
+200
JlA
CLQ Input. '1.pH'= OV
CLO Input. ".pL,--9V
VGG
VI~-lV
Ports A. C. D.INT. REseT"
V,--9V
Input Leakage Current Low
Clock Input Leakage Current High
Clock Input Leakage Current Low
IL.pL
-200
JlA
VOHl
-1.0
V
PorU C thJough G.
IOH =-2 ml\.
VOH2
-4.0
V
Ports E. F. G. IOH = -20 mA
ILOLl
-10
JlA
Ports C through G.
Vo =-9V
I LOL2
-30
JlA
Ports C through G.
Vo --35V
-36
mA
Output Voltage High
Output Leakage Current Low
Supply Current
n. INT. RESET
Ports A. C.
-20
IGG
CAPACITANCE
LIMITS
PARAMETER
MAX
UNIT
Input Capacitance
SYMBOL
CI
15
pF
Output Capacitance
Co
15
pF
Input/Output Capacitance
C,O
15
pF
MIN
TYP
TEST
CONDITIONS
f
E
1 MHz
AC CHARACTERISTICS
LIMITS
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
180
kHz
Oscillator Frequency
f
Rise and Fall Times
tr.tf
0
0.3
JlS
Clock Pulse Width High
t.pWH
2.0
8.0
JlS
t.pWL
2.0
8.0
JlS
Clock Pulse Width Low
100
TEST
CONDITIONS
External Clock
~----------1/f------------~
160
CLOCK WAVEFORM
557 LDS-R EV 1-2-82-CAT
NEe
",PD650
",PD651
NEe Electronics U.S.A. Inc.
Microcomputer Division
CMOS 4-81T SINGLE CHIP MICROCOMPUTERS
DESCRIPTION The I-lPD650 and the I-lPD651 are pin-compatible CMOS 4-bit single chip microcomputers which have similar architectures.
The I-lPD650 contains a 2000 x 8-bit ROM,'and a 96 x 4-bit RAM which includes six
working registers and the Flag register. It has a level-triggered hardware interrupt, a
three;level stack, and a programmable 6-bit Timer. The I-lPD650 executes all 80
instructions of the extended I-lCOM-4 family instruction set. The I-lPD651 contains a
1000 x 8-b'it ROM and a 64 x 4-bit RAM. It hasa testable interrupt input 1l\lT, a twolevel stack, and executes all 58 instructions of the I-lCOM-4 family instruction set. The
I-lPD651 is upward-compatible with the I-lPD650.
Both the I-lPD650 and the I-lPD651 provide 35 I/O lines, organized into the 4-bit input
ports A and B, the 4-bit I/O ports C and D, the 4-bit output ports E, F, G, and H, and
the 3-bit output port I. Both devices typically execute their instructions with a 10 IlS
instruction cycle time. The I-lPD650 and the IlPD651 are manufactured with a standard
CMOS process, allowing use of a single +5V power supply, and are available in a 42-pin
Dual-in-line plastic package. The I-lPD651 is also available in a space-saving 52-pin flat
plastic package.
PIN NAMES
PIN CONFIGURATION
Cl l
PCo
PCl
PC2
PC3
TNT
RESET
POo
POI
P02
P03
PEa
PEl
PE2
PE3
PFa
PFI
PF2
PF3
TEST
VCC
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
I-lPD
650C/
651C
41
40
39
3B
37
36
35
34
33
32
31
30
29
28
27
26
26
24
23
22
ClO
VSS
PB3
PB2
PBl
PBa
PA3
PA2
PAl
'PAa
PI2
Pll
Pia
PH3
PH2
PHI
PHO
PG3
PG2
PGl
PGo
iiiiil~!:fftt¥
NC
PAO·PA3
Input Port A
PBO·PB3
Input Port B
PCO·PC3
Input/Output Port C
PDO·PD3
Input/Output Port
PEO·PE3
Output Port E
PFO·PF3
Output Port F
PGO·PG3
Output Port G
PHO·PH3
Output Port H
PIO·PI2
Output Port I
!NT
Interrupt Input
CLO·CL1
External Clock Slgnlll
RESET
Reset
VCC
Power Supply Positive
VSS
Ground
TEST
Factory Teat Pin
(Connect to Vee)
NC
No Connection
NC
NC
NC
PH2
PH3
PE3
PE2
PE,
.Plo
PI,
PEo
PI2
PAO
PA,
PA2
PA3
PD3
PD2
PBo
NC
PD,
PDO
RESET
~:: E. ~ d ~
dl ~ f
161
~I!
°
,..PD650/651
ABSOLUTE MAXIMUM
RATINGS*
Operating Temperature . . . . . . . . . . . . . . . . . . . . .
. ... -30°C to +85°e
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . .
. .. - 550 e to + 1250e
SupplyVoltage, Vee . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +7.0V
Input Voltages (Ports A through D, INT, RESET) . . . . . . . . . . . . .-0.3 to Vee +0.3V
Output Voltages. . . . . . . . . . . . . . . . . . . . . . . . .
. .....-0.3 to Vee +0.3V
Output Current' (Ports e through I,each bit) . . . . . . . . .
.. 2.5 mA
(Total, all ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 mA
*COMMENT: Stress above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions above those indi';ated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
Te = -30·C to +8S·C; vcc· +sv ~10%
LIMITS
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
TEST
CONOITIONS
Input Voltage High
VIH
0.7 Vec
Vee
V
Ports A through D. INT
RESET
Input Voltage Low
VIL
0
0.3 Vec
V
I>orta A through D. INT
RESET
Clock Voltage High
Vt/>H
0.7 Vee
VCC
V
GLO Input. External Clock
Clock Voltage Low
Vt/>L
0
0.3 VCC
V
GLO Input. E;xternal Clock
Input Leakage Current High
ILiH
+10
IJA
;>orts A through D.INT
RESET. VI - Vee
Input Leakaga Current Low
ILIl.
-10
IJA
"orts A through D. INT.
RESET. VI - OV
Clock Input L.akage Current High
Il.t/>H
-1'200
IJA
CLO Input. Vt/>H - Vec
Clock Input Leakaga Currant Low
ILt/>L
-200
IJA
CLO Input. Vt/>L - OV
VOHI
Vec -O.S
V
Pom C through I.
IOH --1.0mA
VOH2
VCC-2.S
V
Ports C through I.
IOH --2.0mA
V
Ports E through I,
10l. - +2.0 mA
V
Portl E through I,
10L - +1.2 mA
Output Voltege High
+0.8
VOl. 1
Output Voltlge l.ow
+0.4
VOl. 2
Output Leakage Currant l.ow
ILOL
SupplV Currant
ICC
-10
+d.8
IJA
DC CHAR'ACTERISTICS
Ports C, D, Vo - OV
mA
+2.0
T.-26°C
LIMITS
,PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
I nput Capacitance
CI
16
pF
Output CIPacltanCI
Co
16
pfl
I nput/Output Capacitance
CIO
16
pfl
MAX
UNIT
440
KHz
TEST
CONDITIONS
CAPACIT ANCE
f -1 MHz
Ta = -30·C to +8SoC; VCC· +5 ± 10%
LIMITS
PARAMETER
SYMBOl.
MIN
160
TYP
Oscillator Fraquency
I
Rise and Fall Times
tr.tl
0
0.3
jJ.S
Clock Pulse Width High
tt/>WH
0.5
5.8
jJ.s
Clock Puis. Width Low
tt/>WL
0,5
6.8
jJ.S
~----------1/f------------~
TEST
CONDITIONS
AC CHARACTERISTICS
EXTERNAL Cl.OCK
CLOCK WAVEFORM
VCC
Vt/lH
Vt/lL
VSS
162
650/651 DS-1-82-CA T
NEe
!-,PD547L
NEe Electronics U.S.A. Inc.
Microcomputer Division
4-BIT SINGLE CHIP MICROCOMPUTER
DESCR IPTION
The J.LPD547L is a 4-bit single chip microcomputer which has the same architecture as
the J.LPD547. It contains a 1000 x 8-bit ROM, a 64 x 4-bit RAM, a testable interrupt
input j'j\jf and a single-level stack:
The J.LP0547 L provides 35 I/O lines, organized into the 4-bit input ports A and 8, the
4-bit I/O ports C and 0, the 4-bit output ports, E, F, G, and H, and the 3-bit output
port I. The J.LP0547L typically executes all 58 instructions of the J.LCOM-4 family
instruction set with a 25 J.LS instruction cycle time. It is manufactured with a modified
PMOS process, allowing use of a single -8V power supply, and is available in a 42-pin
dual-in-line plastic package.
PIN NAMES
PIN CONFIGURATION
CL,
CLO
VGG
PB3
PB2
PB,
PCo
PC,
PC2
PC3
1m
'PBo
RESET
POO
PO,
P02
PA3
PA2
PAl
PAO
PI2
PI,
PIO
P03
PEO
PE,
PE2
J.LPD
647L
PE3
PFo
PF,
PAO-PA3
Input Port A
PBO-PB3
Input Port B
PCO-PC3
Input/Output Port C
POO-P03
Input/Output Port 0
PEO-PE3
Output Port E
PFO-PF3
Output Port F
PGO-PG3
Output Port G
PHO-PH3
Output Port H
PH3
PIO·PI2
Output Port I
PH2
PH,
PHO
/NT
Interrupt Input
PF2
PG3
PF3
TEST
PG2
PG,
Vss
PGo
CLO-CL1
External Clock Signals
RESET
Reset
VGG
Power Suppl y Negative
VSS
Power Supply Posl tlve
TEST
Factory Tilt Pin
(Connect to VSS)
ABSOLUTE MAXIMUM Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -10 o C to-,+70°C
RATINGS* Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +125°C
Supply Voltage, VGG . . . . . . . . . . . . . ' . . . . . . . . . . . . . . . . . . . . . .-15 to +0.3V
Input Voltages . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . .-15 to +0.3V
Output Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-15 to +0.3V
Output Current (Ports C through I, each bit) . . . . . . . . . . . . . . . . . . . . . . . -4 mA
(Total, all ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25 mA
*COMMENT: Stress above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability .
Rev/1
163
P. PD547L
Ta = _10°C to +70°C; VGG --SV ± 10%
DC CHARACTERISTICS
LIMITS
PARAMETER
SYMBOL
Input Voltage High
VIH
Input Voltage Low
VIL
Clock Voltage High
VH
Clock Voltage Low
VL
MIN
TYP
MAX
-1.6
UNIT
TEST
CONDITIONS
V
Ports A through D, INT,
RESET
V
Ports A through D, INT,
RESET
-3.S
VGG
V
CLO Input, External Clock
-5.0
VGG
V
CLO Input, External Clock
/JA
Ports A through D, INT,
RESET, VI = -IV
/JA
Ports A through D, INT,
RESET, VI --9V'
-0.6
Input Leakage Current High
IUH
+10
Input Leakage Current Low
IUL
-10
Clock Input Leakage Current High
ILH
+200
/JA
CLO Input, VH = OV
Clock Input Leakage Current Low
ILL
-200
/JA
CLO Input, VL = -9V
VOHI
-1.0
V
Ports C through I,
IOH ~, -1.0 mA
VOH2
-2.3
V
Ports C through I,
IOH" -3.3 mA
-10
/JA
Ports C through I,
VO.=-9V
-25
mA
Output Voltage High
Output Leakage Current Low
ILOL
Supply Current
IGG
-15
Ta = 25°C
CAPACITANCE
LIMITS
MAX
UNIT
Input Capacitance
CI
15
pF
Output Capacitance
Co
15
pF
Input/Output Capacitance
CIO
15
pF
PARAMETER
SYMBOL
TYP
MIN
TEST
CONDITIONS
1=1 MHz
AC CHARACTE R ISTI'CS
Ta = -10°C to +70°C; VGG = -SV ± 10%
LIMITS
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
KHz
Oscillator Frequency
I
Rise and Fall Times
tr,tl
0
0.3
/JS
Clock Pulse Width High
tWH
2.0
S.O
/JS
Clock Pulse Width Low
tWL
2.0
S,O
/JS
100
ISO
TEST
CONDITIONS
EXTERNAL CLOCK
CLOCK WAVEFORM
~----------1/f
____________~
547 LS-R EV1-1-82-CAT
164
NEe
IlPD552
IlPD553
NEe' Electronics U.S.A. Inc.
Microcomputer Division
4-BIT SINGLE CHIP MICROCOMPUTERS WITH
VACUUM FLUORESCENT DISPLAY DRIVE
CAPABILITY
DESCRIPTION
The IlPD552 and the IlPD553 are pin-compatible 4-bit single chip microcomputers
which have similar architectures.
The IlPD552 contains a 1000 x 8-bit ROM and a 64 x 4-bit RAM. It has a testable
interrupt input INT, a single-level stack, and executes all 58 instructions of the
IlCOM-4 family instruction set. The IlPD552 is upward compatible with the IlPD553.
The IlPD553 contains a 2000 x 8-bit ROM, and a 96 x 4-bit RAM which includes six
working registers and the Flag register. It has a level-triggered hardware interrupt, a
three-level stack, and a programmable 6-bit Timer. The IlPD553 executes all 80
instructions of the extended IlCOM-4 family instruction set.
Both the IlPD552 and the IlPD553 provide 35 I/O lines organized into the 4-bit input
Ports A and B, the 4-bit I/O Ports C and D, the 4-bit output Ports E, F, G, and H, and
the 3-bit output Port I. The 27 I/O ports and output ports are capable of being pulled
to -35V in order to drive Vacuum Fluorescent Displays directly. Both devices typically
execute their instructions with a lOlls instruction cycle time. The IlPD552 and the
IlPD553 are manufactured with a standard PMOS process, allowing use of a single
-lOV power supply, and are available in a 42-pin dual-in-line plastic package.
PIN CONFIGURATION
PIN NAMES
Cll
PCO
PAO-PA3
Input Port A
PCl
PBO·PB3
Input Port B
PC2
PC3
TNi
RESET
POo
POl
P02
P03
PEO
PEl
Il PD
552/
553
PE2
PE3
PFO
PFl
PF2
PF3
TEST
VSS
ABSOLUTE MAXIMUM
RATINGS*
-PBO
PA3
PA2
PAl
PAO
P I2
P I1
PIO
PH3
PH2
PH 1
PHO
PG3
PG2
PG1
PGO
,
PCO,PC3
Input/Output Port C
POO·P03
Input/Output Port 0
PEO·PE3
Output Port E
PFO-PF3
Output Port F
PGO·PG3
Output Port G
PHO·PH3
Output Port H
PIO·PI2
Output Port I
INT
CLO-CL1
External Clock Signals
RESET
Reset
VGG
Power Supply Negative
VSS
Power Supply Positive
TEST
Factory Test Pin
(Connect to VSS)
o
Interrupt Input
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -lO C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +125°C
Supply Voltage, VGG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -15 to +0.3V
Input Voltages (Port A, B, INT, RESET) . . . . . . . . . . . . . . . . . . . . . .-15 to +0.3V
(Ports C, D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40 to +0.3V
Output Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40 to +0.3V
Output Current (Ports C through I, each bit) . . . . . . . . . . . . . . . . . . . . . . -12 mA
(Total, all ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -60 mA
*COMMENT: Stress above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability .
165
m
JlPD552/553
DC CHARACTERISTICS
LIMITS
PARAMETER
Input Voltage High
SYMBOL
VIH
MIN
TVP
0
MAX
-3.5
TEST
CONDITIONS
UNIT
V
Ports A through 0, INT,
RESET
.vILl
-7.5
VGG
V
.Ports A, B, INT, RESET
VIL2
-7.5
-35
V
Ports C, 0
Clock Voltage High
Vq,H
0
Clock Voltage Low
Vq,L
-6.0
Input Leakage Current High
Input Leakage Current Low
Input Voltage Low
V
CLQ !nput, External Clock
VGG
V
CLO
ILIH
+10
Il A
Ports A through 0, INT,
RESET, VI - -lV
lULl
-10
IlA
Ports A through 0, TfiIT,
RESET, VI - -11V
-O.B
~nput,
External Clock
IUL2
-30
pA
Ports C, 0, VI - -35V
Clock Input Leakage Current High
ILq,H
+200
IlA
CLQ Input, Vq,H - OV
Clock Input Leakage Current Low
ILL
-200
IlA
CLQ Input, Vq,L - -11 V
Output Voltage High
-2.0
VOH
V
Ports C through I,
IOH --SmA
ILOL1
-10
IlA
Ports C through I,
VO' -11V
ILOL2
-30
IlA
Ports C through I,
VO.,-35V
-50
mA
Output Leakage Current Low
Supply Current
-30
IGG
CAPACITANCE
LIMITS
MAX
UNIT
Input Capacitance
CI
16
pF
Output Cepacitance
Co
15
pF
Input/Output Capacitance
CIO
16
pF
PARAMETER
SYMBOL
MIN
TYP
TEST
CONDITIONS
f -1 MHz
AC CHARACTERISTICS
T a - -10·C to +70·C; VGG - -10V t 10%
LIMITS
PARAMETER
SYMBOL
MIN
160
TYP
MAX
440
Oscillator Frequency
f
Rise and Fill Times
tr,tf
0
0.3
Clock Pulse Width High
IWH
0.6
6.6
Clock Pul .. Width Low
~WL
0.6
6.6
UNIT
TEST
CONDITIONS
KHz
II'
".
EXTERNAL CLOCK
",
~------------1/f---------------~
CLOCK WAVEFORM
Vss
VI/lL
VGG
166
552/553DS-2-82~CAT
NEe
,..PD550
,..PD554
NEe Electronics U.S.A. Inc.
Microcomputer Division
4·BIT SINGLE CHIP MICROCOMPUTERS WITH
VACUUM FLUORESCENT DISPLAY DRIVE
CAPABILITY
DESCRIPTION
The ~PD550 and the ~PD554 are pin-compatible 4-bit single chip microcomputers
which have the same architecture. The only difference between them is that the
~PD550 contains a 640 x 8-bit ROM, whereas the ~PD554 contains a 1000 x 8-bit
ROM. Both devices have a 32 x 4-bit RAM, a testable interrupt input INT, and a
single-level stack. The ~PD550 and the ~PD554 provide 21 I/O lines organized into'
the 4-bit input port A, the 4-bit I/O ports C and D, the 4-bit output ports E and F,
and the 1-bit output port G. The 17 I/O ports and output ports are capable of being
pulled to -35V in order to drive Vacuum Fluorescent Displays directly. The ~PD550
and the ~PD554 typically execute all 58 instructions of the ~COM-4 family instruction set with a 10 ~s instruction cycle time. Both devices are manufactured with a
standard PMOS process, allowing use of a single -10V power supply, and are available
in a 28 pin dual-in-line plastic package.
PIN NAMES
PIN CONFIGURATION
C L1
CLo
PAO-PA3
Input Port A
PCo
VGG
PCO-PC3
Input/Output Port C
PC,
RESET
PC2
iNT
PC 3
PA3
POo
PA2
P01
PA1
INT
Interrupt Input
P02
PAO
RESET
Reset
P03
PGo
VGG
Power Supply Negative
PEO
PF3
VSS
TEST
Power Supply Positi ve
PE1
PF2
PE2
PF1
PE3
PFO
VSS
TEST
POO-P03
Input/Output Port 0
PEO-PE3
Output Port E
PFO-PF3
Output Port F
PGO
CLO-CL1
Output Port G
External Clock Signals
Factory Test Pi n
(Connect to VSS)
ABSOLUTE MAXIMUM Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -10°C to +70°C
RATINGS· Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +126°C
Supply Voltage, VGG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -15 to +0.3V
Input Voltages (Port A, INT, RESET) . . . . . . . . . . . . . . . . . . . . . . . .-15 to +O.3V
(Ports C, D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40 to +0.3V
Output Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40 to +O.3V
Output Current (Ports C, D, each bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . -4 mA
(Ports E, F, G, each bit) . . . . . . . . . . . . . . . . . . . . . . . . . -15 mA
(Total, all ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 60 mA
*COMMENT: Stress above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability .
167
flPD550/554
Til" -10·C to +70·C; VGG
= -10V t
10%
DC.CHAHACTE R ISTI CS
LIMITS
PARAMETER
Input Voltage Low
MAX
UNIT
0
-2.0
V
VILl
-4.3
VGG
V
Ports A, iNT, RESET
VIL2
-4.3
-36
V
PortsC,D
0
-0.6
V
CLO Inpllt, External Clock
VGG
V
CLO InPl't, External Clock
ILIH
+10
"A
Ports A, C, 0, iNT, RESET
VI--1V
ILILl
-10
"A
Ports A, C, 0, INT, RESET
VI--llV
ILIL2
-30
"A
Ports C,I), VI" -36V
ILq,H
+200
"A
CLO Inpll( Vq,H .. OV
Clock Voltage High
Vq,H
Clock Voltage Low
Vq,L
Input Leakage Currant High
Input Leakage Currant Low
Clock Input Leakage Current High
Clock Input Leakage Current Low
Output Voltage High
MIN
V!H
_SYMBOL
Input Voltege High
TYP
-6.0.
Ports A, G, 0, rnT: RESET
ILq,L
-200
"A
Clo Input, Vq,L" -11 V
VOHl
-1.0
V
Ports C, D, IOH - -2 mA
VOH2
-2.6
V
Ports E, ", G, IOH - -10 mA
ILOLl
-10
IJA
Ports C through G,
Vo --11V
ILOL2
-30
"A
Ports C through G,
Va --35V
-40
mA
Output Leakage Current Low
Supply Current
TEST
CONDITIONS
-20
IGG
CAPACITANCE
LIMITS
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
Input Capacitanca
CI
16
pF
Output Capacitance
Co
16
pF
Input/Output Capacitllnce
CIO
15
pF
TEST
CONDITIONS
f -1 MHz
Te = -10·C to +70·C; VGG· -10V:!: 10%
AC CHARACTERISTICS
LIMITS
MAX
UNIT
Oscillator Frequency
f
150
440
KHz
Rise and Fan Times
t r, tf
0
0.3
IJI
Clock Pulse Width High
tq,WH
0.6
6.6
IJI
Clock Pulse Width Low
~WL
0.6
5.6
IJS
PARAMETER
SYMBOL
MIN
TVP
TEST
CONDITIONS
Ex~ern.1
~----------1/f------------~
Clock
CLOCK WAVEFORM
Vss
Vt/lH
168
550/554DS·1·82·CA T
NEe
",PD550L
",PD554L
NEe Electronics U.S.A. Inc.
Microcomputer Division
4-BIT SINGLE CHIP MICROCOMPUTERS WITH
VACUUM FLUORESCENT DISPLAY DRIVE
CAPABILITY'
DESCRIPTION
The J,LPD550Landthe J,LPD554L are pi~-compatible 4~bit single chip microcomputers
which have the same architectur~. The only difference bet\l\leen them is that the
J,LPD550L contains a 640 x 8··bit ROM,whereas the J,LPD554L contains a 1000 x 8-bit
ROM. Both devices have a 32 x 4-bit RAM, a testableInterrupt input INT, and a singlelevel stack. The J,LPD550L and the J,LPD554L provide 21 I/O lines organized into the
4-bit input port" A,the 4 cbit I/O ports C and D, the 4-bit output ports E and F, and the
1-bit outPllt port .G. The 17 I/O ports and output ports are capable of being pulled to
-35V in order to drive Vacuum Fluorescent Displays directly. The J,LPD550L and the
J,LPD554L typically execute all 58 instructions of the J,LCOM-4 family instruction set
with a 25 J,LS in.struction cycle time. Both devices are manufactured with a modified
PMOS process, allowing use of a single ~8V power supply, and are available in a 28-pin
dual-in-line plastic package.
The J,LPD550L and the J,LPD554L are upward compatible with the J,LPD557L.
PIN NAMES
PAO-PA3
Input Port A
PCO-PC3
Input/Output Port C
PDO-PD3
Input/Output Port D
PEO-PE3
Output Port E
PFO-PF3
Output Port F
PGO
Output Port G
CLO-CL1
External Clock Signals
INT
Interrupt Input
RESET.
Reset
VGG
Power Supply Negative
VSS
Power Supply Positi ve
TEST
Factory Test Pi n
(Connect to VSS)
ABSOLUTE MAXIMUM OperatingTemperature~ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1O°C to +70°C
RATINGS* Storage Temperature ... '.' . . . . . . . . . '.' . . . . . . . . . . . . . . . . -40°C to +125°C
Supply Vol~age, VGG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-15 to +0.3V
Inp~t Voltages (Port A, INT, RESET) . . . . . . . . . . , . . . . . . . . . . . . .-15 to +0.3V
(Ports C, D) . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . .-40 to +O.3V
Output Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40 to +O.3V
Output Current (Ports C, D, each bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . -4 mA
(Ports E, F, G, each bit) . . . . . . . . . . . . . . . . . . . . . . . . . -15 mA
(Total, all ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -60 mA
Ta=25°C
*COMMENT: Stress above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
169
,.PD550L/554L
Ta = -10°C to +70°C; VGG = -S.OV ± 10%
DC CHARACTERISTICS
LIMITS
PARAMETER
Input Voltage High
Input Voltage Low
SYMBpL
TYP
MIN
MAX
UNIT
TEST
CONDITIONS
Ports A, C, :::>, iiiJT. RESET
VIH
0
-1.6
V
VILI
-4.5
VGG
V
Ports A, IN"f. RESET
VIL2
-4.5
-35
V
PortsC, D
Clock Voltage High
VcpH
0
-0.6
V
CLO Input, External Clock
Clock Voltage Low
VcpL
-5.0
VGG
V
CLO Input, External Clock
Input Leakage Current High
ILIH
+10
jlA
Ports A, C, D,
VI· -IV
ILILI
-10
jlA
Ports A, C, 0, INT, RESET
Vl m -9V
ILlL2
-30
jlA
Ports C, D, VI
ILc1>H
+200
jlA
CLQ Input, VcpH = OV
CLO Input, VcpL = -9V
Input Leakage Current Low
Clock Input Leakage Current High
Clock Input Leakage Current Low
Output Voltage High
ILcpL
-200
jlA
-1.0
V
Ports C, D, IOH
VOH2
-2.5
V
Ports E, F, G, IOH
ILOL1
-10
jlA
Ports C thrQ·ugh G,
Vo = -9V
ILOL2
-30
jlA
Ports C through G,
Va = -35V
-24
mA
MAX
UNIT
··12
IGG
SYMBOL
MIN
TVP
Input Capacitance
CI
16
pF
Output Capacitance
Co
16
pF
Input/Output Capacitance
CIO
15
pF
TEST
CONDITIONS
fa 1 MHz
AC CHARACTERISTICS
LIMITS
PARAMETER
Oscillator Frequency
SYMBOL
f
MIN
100
TVP
MAX
UNIT
ISO
KHz
Rise and Fall Times
tr,tf
0
0.3
jll
Clock Pulse Width High
tCPWH
2.0
S.O
jll
S.O
jll
Clock Pulse Width Low
tCPWL
2,0
= -2 mA
= -10 mA
CAPACITANCE
LIMITS
PARAMETER
= -35V
VOHl
Output Leakage Current Low
Supply Current
iN'i', RESET
TEST
(;ONDITIONS
External Clock
1 0 4 - - - - - 1 / f ------..-1
CLOCK WAVEFORM
Vss
V/IIH
170
550 L/554 LDS-2-82-CAT
NEe
J,lPD652
NEe Electronics U.S.A. Inc.
Microcomputer Division
CMOS 4·BIT SINGLE CHIP MICROCOMPUTER
DESCRIPTION
The~P0662 is a CMOS 4-bit single chip microcomputer having the same architecture
as the ~P0664. It contains a 1000 x 8-bit ROM, a 32 x 4-bit RAM, a testable interrupt
input INT, and a single-level stack. The ~P0662 provides 21 I/O lines, organized into
the 4-bit input port A, the 4-bit lio ports C and 0, the 4-bit output ports E and F, and
the 1-bit output port G. The ~P0662 typically executes all 58 instructions of the
~COM-4 family instruction set with a 10 ~s instruction cycle time. It is manufactured
with a standard CMOS process, allowing use of a single +5V power supply, and is available in a 28-pin Oual-in-line plastic package.
PIN NAMES
PIN CONFIGURATION
ABSOLUTE MAXIMUM
RATINGS*
CL,
CLo
PAO-PA3
Input Port A
PCo
VSS
PCo- PC3
Input/Output Port C
Input/Output Port
Output Port E
PC,
RESET
POO-P03
PC2
iNT
PEO-PE3
PC3
PA3
PFO-PF3
Output Port F
PGO
Output Port G
Interrupt Input
°
POO
PA2
P01
PA1
'CLO-CL,
External Clock Signals
P02
PAO
RESET
Reset
P03
PGO
Vec
PEO
PF3
Power Supply Positive
Power Supply Negative
PE1
PF2
VSS
TEST
PE2
PF1
PE3
PFa
VCC
TEST
INT
Factory Test PI n
(Connect toVce)
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , -30°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -56°C to +126°C
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 7.0V
Input Voltages (Ports A, C, 0, INT, RESET) ., . . . . . . . . . . . . .-0.3 to VCC +O.3V
Output Voltages .. , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3 to VCC +0.3V
Output Current (Ports C through G, each bit) . . . . . . . . . . . . . . . . . . . . - 2.6 mA
(Total, all ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -28.0 mA
*COMMENT: Stress above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability .
REV/1
171
/JPD652
Ta
=-30°C to +85°C; VCC = +5V i
10%
DC CHARACTERISTICS
LIMITS
PARAMETER
SYMBOL
MIN
TYP
TEST
CONDITIONS
MAX
UNIT
VCC
V
Ports A, C, D, INT, RESET
0.3VCC
V
Ports A, C, D, INT, RESET
VCC
V
CLO Input, External Clock
0.3VCC
V
CLO Input, External Clock
Input Voltage High
VIH
Input Voltage Low
VIL
Clock Voltage High
Vrj>H
Clock Voltage Low
Vrj>L
Input Leakage Current High
ILIH
+10
"A
Ports A, C, D, INT, RESET,
VI = VCC
Input Leakage Current Low
ILiL
-10
"A
Ports A, C, D, INT, RESET,
VI-OV
0.7 VCC
0.7 VCC
~
Clock Input Leakage Current High
ILrj>H
+200
"A
CLO Input, "WL
O.S
5.6
""
".
,..
TEST
CONDITIONS
AC CHARACTERISTICS
External Clock
~----------1/f------------~
CLOCK WAVEFORM
Vcc
172
652DS-REV1-1-82-CAT
NEe
IlPD556B
NEe Electronics U.S.A. Inc.
Microcomputer Division
IlCOM-4 4-BIT SINGLE CHIP
ROM-LESS EVALUATION CHIP
OESCR I PTION
The MPD556B is the ROM-less evaluation chip for the MCOM-4 4-bit single chip microcomputer family. The MPD556B is used in conjunction with an external 2048 x 8-bit
program memory, such as the MPD2716 UV EPROM, to emulate each of the 14 different MCOM-4 single ch,ip microcomputers.
The MPD556B contains a 96 x 4-bit RAM, which includes six working registers and the
Flag register. It has a level-triggered hardware interrupt, a three-level stack, and a programmable 6-bit timer. The MPD556B executes all 80 instructions of the extended
MCOM-4 family instruction set.
The MPD556B provides 35 I/O lines organized into the 4-bit input Ports A and B, the
4-bit I/O Ports C and D, the 4-bit output Ports E, F, G, and H, and the 3-bit output
Port I. It typically executes its instructions with a 1OMS instruction cycl.e time. The
MPD556B is manufactured with a standard PMOS process, allowing use of a single -1 OV
power supply, and is available in a 64-pin quad-in-line ceramic package.
PIN NAMES
PIN CONFIGURATION
173
PAO-PA3
Input Port A
PBO-PB3
Input Port B
PCO-PC3
Input/Output Port C
PDO-PD3
Input/Output Port D
PEO-PE3
Output Port E
PFO-PF3
Output Port F
PGO-PG3
Output Port G
PHO-PH3
Output Port H
P10-P12
Output Port I
INT
Interrupt Input
10-7
Instruction Input
PCO-10
Program Counter Output
ACC/PC
Accumulator/Program
Counter Select
BREAK
Break Input
STEP
Single Step Input
CLO-CL1
External Clock Source
RESET
Reset
VGG
Power Supply Negative
VSS
Power Supply Positive
TEST
Factory Test Pin
(Connect to VSS)
BLOCK DIAGRAM
I'P 0556 B
ACC/PC
PA3·0
RAM
96 x 4
RAM
DECODER
PB3.0
PC3·0
PD3·0
B-BIT
PE3.0
INSTRUCTION BUS
PF3_0
PG3·0
CONTROL
AND
DeCODE
1-----iNT
~~~~~~~I·· II~~~~~R.'T
CLI
CLO
. Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ' -10°C to +70°C
Storage Temperature. . . . . . . . . . .
. . . . . . . . . . . -40°C to +125°C
. . . . . . . . . . .. -15V to +O.3V
Supply Voltage, VGG ........
All Input Voltages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -15V to +O.3V
All Output Voltages . . . . . . . . . . . . . . . , . . . . . . . . . . . . . .
-15V to +O.3V
Output Current (total, all ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -4 mA
T a =25°C
*COMMENT: Stress above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
174
ABSOLUTE MAXIMUM
RATINGS*
,..PD556B
DC CHARACTERISTICS
Ta
= _10°C
to +70 0 C; VGG
= -10V t
10%, VSS
= OV
LIMITS
PARAMETER
SYMBOL
Input High
Voltage
V,H
Input Low
Voltage
V,L
Clock High
Voltage
V(,'JH
Clock Low
Voltage
V(,'ll
MIN
TYP
MAX
TEST
CONDITIONS
UNIT
-2.0
V
VGG
V
Ports A to D, '7-0
BREAK, STEP, INT, RESET,
and AcdpC
-0.8
V
CLO Input, External Clock
VGG
V
CLO Input, External Clock
110
/1A
Ports A and B, 17-0
INT, RESET, BREAK, STEP,
ACC/PC, V, = -lV
Ports A to D, '7-0
BREAK, STEP, INT, RESET,
and ACC/PC
1------- - ---
Input Leakage
Current High
-6.0
'LiH
110
/1A
Ports C and D, V, - -lV
-10
/1A
Ports A and B, 17-0
INT, RESET, BREAK, STEP,
ACC/PC, V, = -11V
'll L
-10
/1A
Ports Cand D, V, =-11V
Clock Input
Leakage High
'L\',H
1200
/1A
CLO Input, External Clock,
V<,H OV
Clock Input
Leakage Low
'L,;,L
-200
/1A
CLO Input, External Clock,
VL=-11V
VOHl
-1.0
V
Ports C to I, PlO-0
IOH=-1.0mA
VOH2
-2.3
V
Ports C to I. PlO-0
IOH = -3.3 mA
Output Leakage
Current Low
'LOL
-30
/1A
Ports C to I. P 10-0
VO=-l1V
Supply Current
IGG
-50
mA
-30
Ta = -10°C to +70°C, VGG = -10V ± 10%
LIMITS
PARAMETER
SYMBOL
Frequency
f(l)
MIN
TYP
150
MAX
UNIT
440
KHz
Clock Rise and Fa-II Times
tr,tf
0.3
/1S
Clock Pulse Width High·
t<,WH
0.5
5.6
/1S
Clock Pulse Width Low
t¢WL
0.5
5.6
Input Setup Time
tiS
TEST
CONDITIONS
/1S
/1S
Input Hold Time
tlH
BREAK to STEP Interval
tBS
200
/1S
f =. 400 KHz, "1" Written
STEP to RUN Interval
tSB
200
/1S
f
= 400
STEP Pulse Width
tws
30
/1S
f
= 400
KHz, "1" Written
BREAK to ACC Interval
tBA
200
/1S
f
= 400
= 400
KHz, "1" Written
KHz, "1" Written
KHz, "1" Written
/1S
ACC/PC Pulse Width
tWA
30
/1S
f
STEP to ACC Interval
tSAl
200
/1S
f
PC to STEP Overlap
tSA2
/1S
f
= 400
= 400
PC to RUN Interval
tAB
/1S
f
= 400
ACC/PC . P 10-0 Delay
CAPACITANCE
---
Input Leakage
Current Low
Output High
Voltage
AC CHARACTERISTICS
-4.3
KHz, "1" Written
KHz, "1" Written
KH z, "1" Written
tDAPl
15
/1S
f = 400 KHz, "1" Written
tDAP2
15
/1S
f
= 400
KHz. "1" Written
Ta = 25°C
LIMITS
SYMBOL MIN
PARAMETER
TYP
MAX
TEST
UNIT CONDITIONS
pf
Input Cal;>acitance
CI
15
Output Capacitance
Co
15
pf
Input/Output Capac itance
CIO
15
pf
175
f = 1 MHz
[I
,..P0556B
tf~1/~CP_~
tcpWL
tcpWH
v 55.V
_
CLOCK WAVEFORM
r
---V
GG ___
--- VcpL
cpH
TIMING WAVEFORMS
17·0
31--
PACKAGE OUTLINE
ILPD556B
176
556BD5-1-82-CAT
NEe
JAPD7500 SERIES
CMOS 4·BIT SINGLE CHIP
MICROCOMPUTER FAMILY
NEe Electronics U.S.A. Inc.
Microcomputer Division
D Powerful Instruction Set
- From 58 to 110 instructions, including:
- Direct/indirect addressing
- Table Look-up'
- RAM Stack Push/Pop
- Single byte subroutine calls
- RAM and I/O port single bit manipulation
- Accumulator and I/O port Logical operations
- 10 !-,slnstruction Cycle Time, typically
D Extensive General Purpose I/O Capability
- One 4-Bit Input Port
- Two 4-Bit latched tri-state Output Ports
- Five 4-Bit inputllatched tri-state Output Ports
- Easily expandable with !-,PD82C43 CMOS I/O
Expander
- 8-Bit Parallel I/O capability
D Hardware Logic Blocks - Reduce Software
Requirements
- Operation completely transparent to instruction
execution
- 8-Bit Timer/Event Counter
- Binary-up counter generates INTT at
coincidence
- Accurate Crystal Clock or External Event
operation possible
- Vectored, Prioritized Interrupt Controller
- Three external interrupts (INTO, INT 1, INT2)
- Two internal interrupts (INTT, INTS)
- Display Controller/Driver
- Complete Direct Drive and Control of MUltiplexed LCD or Vacuum Fluorescent Display
- Display Data automatically multiplexed from
RAM to dedicated segment/backplane/digit
driver lines
- 8-Bit Serial Interface
- 3-line I/O configuration generates INTS upon
transmission of eighth bit
- Ideal for distributed intelligence systems or
communication with peripheral devices
- Complete operation possible in HALT and STOP
power-down modes
D Built-in System Clock Generator
D Built-in Schmidt-Trigger RESET Circuitry
D Single Power Supply, Variable from 2.7V to 5.5V
D Low Power Consumption Silicon Gate CMOS
Technology
- 900!-,A max at 5V, 400 !-'A max at 3V
- HALT, STOP Power-down instructions reduce
power consumption to 20 !-'A max at 5V,
10!-,A at 3V (Stop mode)
D Extended - 40°C to + 85°C Temperature Range
Available
D Choice of 28-pin or 40-pin dual-in-line packages, or
52-pin or 64-pin flat plastic packages
Description
The ",PD7500 Series CMOS 4-Bit Single Chip
Microcomputer Family is a broad product line of 10
individual devices designed to fulfill a wide variety of
applications. The advanced 4th generation architecture
includes all of the functional blocks necessary for a
single chip controller, including an ALU, Accumulator,
Program Memory (ROM), Data Memory (RAM), four
General Purpose Registers, Stack Pointer, Program
Status Word (PSW), 8-Bit Timer/Event Counter,
Interrupt Controller, Display Controller/Driver, and 8-Bit
Serial Interface. The instruction set maximizes the
efficient utilization of fixed Program Memory space, and
includes a variety of addressing, Table-Look-up,
Logical, Single Bit Manipulation, vectored jump, and
Condition Skip Instructions.
The ",PD7500 Series includes three different devices,
the ",PD7501 , ",PD7502, and ",PD7503, capable of
directly driving Liquid Crystal Displays with up to 12
7-segment digits. The ",PD7508A can directly drive up
to 35V Vacuum Fluorescent Displays with up to 8
7-segment digits, and the ",PD7519 can directly drive up
to 35V Vacuum Fluorescent Displays with up to 16
7-segment digits.
All 10 devices are manufactured with a Silicon gate
CMOS process, consuming only 900",A max at 5V, and
only 400",A max at 3V. The HALT and STOP powerdown instructions can significantly reduce power
consumption even further.
The flexibility and the wide variety of ",PD7500 Series
devices available make the ",PD7500 series ideally
suited for a wide range of battery-powered, solarpowered, and portable products, such as telecommunication devices, hand-held instruments and meters,
automotive products, industrial controls, energy
management systems, medical instruments, portable
terminals, portable measuring devices, appliances, and
consumer products.
Features
D Advanced 4th Generation Architecture
D Choice of 8-Bit Program Memory (ROM) size:
- 1K, 2K, 4K internal, or 8K external bytes
D Choice of 4-Bit Data Memory (RAM) size:
- 64, 96, 128, 208, 224, or 256 internal nibbles
D RAM Stack
D Four General Purpose Registers: 0, E, H, and L
- Can address Data Memory and I/O ports
- Can be stored to or retrieved from Stack
177
6
~PD7500
SERIES
Features
7500 7501 7502 7503 7506 7507 7507S 750a 750aA 7519
Internal ROM
4K
4K
4K
2K
2K
1K
2K
4K
1K
(a.bit words)
Expandable to
8K
RAM
256x4 96x4 128x4 224x4 64x4 128x4 128x4 224x4 208x4 256x4
28
32
32
32
20
110 Unes
32
24
23
23
22
a·Blt Tlmer/Event
•
•
•
•
•
•
•
•
•
•
Counter
a·Blt Serial Interface
•
•
•
•
•
•
•
•
•
4x4
4x4
4x4
4x4
4x4
4x4
2x4
Registers Outside RAM 4x4
2x4
4x4
92
92
92
91
92
Instructions.
110
92
92
58
63
6.67
6.67
6.67
6.67
6.67
6.67
6.67
6.67
Min Cycle Time (/As)
6.67
6.67
4
4
4
4
4
Interrupts
5
4
4
4
2
RAM
RAM
RAM
RAM
RAM
Stack Levels
RAM
RAM
RAM
RAM
RAM
VFD
Display
LC[I
drive
VFD
Controllerl
LCD
LCD
only
Driver
14·blt
Analog 1/0
D/A
Current Consumption
(max)
Normal Operation
900 iiA at !iV ± 10%; 400iiA at 3V ± 10%
Stop Mode
20 iiA at !iV ± 10%; 10iiA at 3V ± 10%
Operating
-10°C
-40°C
Temperature Range
to ..
to
+85°C
+70°C
Packages
28-pln DIP
•
•
4G-pln DIP
•
•
•
52.~ln Flat
•
•
•
64-pln Flat
•
•
•
64-pln QUIi.
•
•
...
...
...
...
-
11'8
JAPD7500 SERIES
Instruction Set
The ",PD7500 Series Instruction Set consists of 110
powerful instructions designed to take full advantage of
the advanced ",PD7500 architecture in your application.
It is divided into two subsets, according to the
complexity of the device.
Instruction Set "A" is available for the higherperformance ",PD7500 Series devices having either a
2K x 8-bit or a 4K x 8-bit Program Memory. It can be
used with the ",PD7500, ",PD7502, ",PD7503, ",PD7507,
",PD7507S, ",PD7508, ",PD7508A, and ",PD7519
products.
Instruction Set "B" is available for the lower-cost
",PD7500 Series devices having a 1K x 8-bit Program
Memory. Its instructions are a compatible subset of
Instruction Set "A," and can be used with the
",PD7500, ",PD7501, and ",PD7506 products.
Instruction Set Symbol Definitions
The following abbreviations are used in the description
of the ",PD7500 Series Instruction sets:
Symbol
A
Accumulator
Bit "n" of Accumulator
Address
Operand specifying one bit of a nibble
Bit "n" of two·blt operand
B1
Bo
Bit Specified
--0 --0 Bit 0 (LSB)
o 1
Bit 1
1
0
Bit 2
1
1
Bit 3 (MSB)
Bank
Bank Flag of PSW (.uPD7500 only)
borrow
Resulting value Is less than OH
C
Carry Flag
Immediate data operand
data
o
o Raglster
Bit "n" of Immediate data operand
On
DE
DE Register Pair
DL
DL Register Pair
"'----_ _ _--=E:...:.R:.:::e.3~2 __.E~ 00
0
3E
SKHEI data
Skip II H = 03-0
Skip II H equala
0
1
1
1
2+S
H = 03-0
70-7F
00
____________________________...!.'!I.medla.!.e dat~_____ ----"-_ _____1>.3__[).2___ 01
~_ _ _ _ _
.,;:-,;0"3:0--------
182
1
02
1
1
01
J.lPD7500 SERIES
Instruction Set
"A" (Cont.)
For the IAPD7500, IAPD7502, IAPD7503, IAPD7507, IAPD7507S, IAPD7508, IAPD7508A, and IAPD7519 devices only
In.tructlon Code
Mnemonic
Function
De.crlptlon
SKLEI data
Skip If L = 03-0
Skip If L equals
Immediate data
SKM8F bit
Skip If (HL)blt = 0
bit = 81-0(0-3)
Skip If Memory
bit false
SKMBT bit
Skip If (HL)blt = 1
bit =
Skip If Memory
bit true
TAMMOO
TMR7_4-A
TMR3-0-(HL)
TCNTAM
A-TCR7-4
(HL)-TCR3_0
Transfer
Accumulator and
Memory to Timer
Modulo Register
Transfer Timer
Count Register to
Accumulator and
Memory
TIMER
TCR7_0-0,
IRFT-O
Start Timer
01 data
IME F/F-O If data = 0
IER3-0-IER3-0 AND NOT
03-0 If data < > 0
Disable Interrupt,
Interrupt Master
Enable F/F or
specified
EI data
IME F/F-1 If data = 0
IER3_0-IER3_0 OR 03-0
Ifdata<>O
SKI data
Skip If IRFn AND 03-0 < > 0
IRFn-IRFn AND NOT 03-0
Enable Interrupt,
Interrupt Master
Enable F/F or
specified
Skip If Interrupt
Request Flag Is
true
SIO
SIOCR-O
IRFO/S-O
SI07_4-A
SI03-0-(HL)
TAMSIO
Byte.
D7
De
De
D4
Conditional Skip (Cont.)
0
1
1
0
1
1
0
0
Start Serial 1/0
Operation
Transfer Accumulator and Memory
to SI Shift
Register
Transfer SI Shift
Register to Accumulator and Memory
TSIOAM
A-SI07-4
(HL)-SI0 3-0
ANP data
P(P3-0)-P(P3-0) AND 03-0
AND output port
latch with
Immediate data
IP port
A-P(P3-0)
IP1 (except
"P07507S)
IP54
A-P(1)
Input from port,
Immediate address
Input from Port 1
IPL
A-P(5)
(HL)-P(4)
A-P(L)
0
P(P3-0)-A
OP3
OP54
OPL
P(3)-A
P(5)-A
P(4)-(HL)
P(L)-A
Oulput to Port 3
Output Byte to
Ports 5 and 4
Output to port
specified by L
ORP data
P(P3-0)-(P3-0) OR 03-0
OR output port
latch with
Skip Condition
Da
D1
DO
HEX
1
03
0
1
02
0
1
01
B1
0
DO
80
3E
50-5F
2+S
L = 03-0
60-63
1+S
(HL)blt = 0
81
80
64-67
1+S
(HL)blt = 1
2+S
IRFn ,. 1
3F
3F
3F
38
3F
32
Interrupt Control
0
1
1
0
0
1
0
0
1
03
1
02
1
01
1
DO
3F
aO-8F
1
03
1
02
1
01
1
DO
3F
90-8F
1
03
1
02
1
0'1
1
DO
3F
40-4F
Serial Interface
0
1
0
1
0
0
3F
33
3F
3E
0
0
Ii)
3F
3A
0
03
Parallel 110
1
0
02
01
0
DO
1
P3
1
P2
0
P1
0
Po
4C
OO-FF
1
P3
1
P2
0'
1
P1
0
1
Po
3F
CO-CF
71
' 1
0
0
Input 8y1e from
Ports 5 and 4
Input from Port
specified by L
Output to port,
Immediate address
OP port
Cycle.
D3
1
P3
0
03
1
02
183
0
01
0
DO
1
P3
1
P2
0
1
P1
1
P2
0
P1
----.---------
3F
38
70
1
Po
3F
EO-EF
73
3F
3C
72
1
Po
40
OO-FF
J.(PD7500 SERIES
Instruction Set
"8"
and IlPD7506 devices only
For the1lPD7500, IlPD7501,
Inatructlon Cod.
Mnemonic
'unctlon
Deacrlptlon
D7
LAOR addr
A-(Oa-o)
Load Accumulator
Irom directly
addressed RAM
Load Accumulator
with Immedlste data
Load Accumulator
from Memory,
poBllble skip
LAI dsta
A-03-0
LAMrp
A-(rp)/
rp .. HL-, HL+, HL
"rp HL -, skip If borrow
If rp = HL + , skip If overflow
ROM addr = PC10-S,
0, C, A3-0
A-[ROM addr)7_4
Load Accumulator
and Memory Irom
Table
H3-0
H2-0- 0 2-0
H3-1-0
HO-04
L-03-0
Load H register with
Immedlste dsts
Load HL register
pair with Immedlata data
ST
STII data
(HL)-A
(HL)-03_0
L-L + 1
Store A to Mamory
Store Immediate
data and
Increment L
XAOR addr
A-(OS-O)
XAH
XAL
XAMrp
XHOR eddr
A-H
A-L
A-(rp)
rp
HL -, HL + , HL
If rp
HL - , skip If borrow
II rp
HL + , aklp If overflow
H-(OS-O)
Exchange A with
directly addre88ed
RAM
Exchange A with H
EXChange A with L.
Exchange A with
Mamory, P08.lble
Skip
XLOR addr
L-(OS-O)
ACSC
A, C-At(HL)+C
skip" carry
AISC deta
A-A + 03-0
skip" overflow
A-A + (HL)
8klp If overflow
=
LAMT
LHI dsta
LHLI data
ASC
=
=
=
ANL
A-A ANO(HL)
EXL
A-AXOR(HL)
ORL
A-A OR (HL)
Exchange H with
directly addre8sad
RAM
Exchange L with
directly addressed
RAM
Add with carry;
skip If carry
Add Immediate;
skip" overflow
Iklp Condition
Da
D4
D3
D2
D1
Do
MIX
Loed
1
0
Os
05
1
04
1
03
0
02
0
01
0
00
38
00-5F
03
02
01
00
10-1F
01
00
50-52
De
CMA
A-NOT A
Complement
Accumulator
RAR
C-Ao
AO-A1
A1-A2
A2-A3
A3-C (old)
Rotate
Accumulator right
through Carry
RC
SC
C-O
C-1
Reset Carry
Set Carry
See explanallon
of "rp" In symbol
definitions
5E
04
Itor.
1
0
IKchena·
1
0
Os
05
02
01
00
2S-2F
02
01
00
CO-OF
1
03
02
01
00
57
40-4F
1
03
0
02
0
01
1
00
39
00-5F
01
00
7A
7B
54-Sa
03
0
1
04
See explanation
or "rp" In symbol
definitions
7C
1+S
Carry
OO-OF
1+S
Overflow
7C
1+S
Carry ,. 1
1
05
1
04
1
03
0
02
1
01
0
00
3A
OO-SF
0
Os
1
05
1
04
1
03
0
02
1
01
1
00
3B
00-5F
Arithmetic
1
1
03
02
01
00
Loglcl.1
0
1
1
0
3F
B2
7E
3F
BS
Accumuilitor
1
0
1
7F
3F
B3
Progrem Itetus Word
1
0
1
1
1
184-
----
o
0
1
String
1+S
0
Os
Add memory; skip
If overflow
ANO Accumulator
and Memory
Excluslva-Or
Accumulator end
Memory
OR Accumulator
and Memory
String
1+S
7S
79
---------~----------
=1
J.(PD7500 SERIES
Instruction Set liB" (Cont.)
For the IlPD7500, IlPD7501, and IlPD7506 devices only
In.tructlon Code
Mnemonic
Function
Byte.
De.crlptlon
D7
OORS addr
(06-0)-(06-0) -1
aklp If (06-0) = FH
OLS
L-L - 1
skip If L = FH
10RS addr
(06-0)-(06-0) + 1
skip If (06-0)
OH
ILS
L-L + 1
skip If L = OH
RMBblt
(HL)blt-O
bit .. B1-0 (0-3)
(HL)blt-1
bit = B1-0 (0-3)
5MBblt
CALL addr
=
(SP -1)-PC7-4
(SP - 2)-PC3-0
(SP-3)-PSW
(SP - 4)-PC1 0-8
SP-SP-4
BANK-O
De
Ds
D4
D3
Increment .nd Decrement
1
0
0
1
1
Oecrement directly
0
04
addressed RAM;
06
05
03
skip If borrow
Oecrement L; skip
If borrow
,0
1
1
0
1
Increment directly
0
06
04
addressed; skip If
05
03
overflow
Increment l; skip If
overflow
ReHt Memory bit
D2
D1
Do
NIX
1
02
0
01
0
00
3C
00-5F
1
02
Bit Manlpul.tlon
0
1
1
0
Set Memory bit
Call subroutine
0
07
Branch
0
1
Os
06
0
0
01
1
00
Cvcle.
Skip Condition
2+8
(Da-O) • FH
56
1+S
L = FH
30
00-5F
2+S
(06-0)
59
1+S
L = OH
B1
BO
66-6B
B1
BO
6C-6F
1
04
03
010
02
09
01
06
DO
30-37
OO-FF
04
03
02
01
00
EO-FF
1
02
1
01
1
00
3F
10-17
02 '
01
00
60-BF
=OH
PC10~0-010-O
CAL addr
(SP-1)-PC7_4
(SP - 2)-PC3-0
(SP-3)-PSW
(SP - 4)-PC10-6
BANK-O
Call short to
CAL address
subrountlne
JAM data
PC10-8-02-0
PC7-4-A
PC3-0-(HL)
JCP addr
PCS-0-05-0
RT
PC10-8-(SP)
BANK -(SP + 1)
PC3-0-(SP + 2)
PC7-4-(SP+3)
SP-SP + 4
Return from
Subroutine
53
RTS
PC10-8-(SP)
BANK-(SP+1)
PC3-0-(SP + 2)
PC7-4-(SP+3)
SP-SP + 4
Skip unconditionally
Return from
Subroutlna; then
skip next
Instruction
5B
TAMSP
SP7-4-A
SP3-1-(HL)3-1
P~~"8;030000201 00
,1
Os
04
03
m
1+S
Unconditional
St.ck
SKABT bit
Skip If Ablt = 1
bit = B1-0(0-3)
SKAEI data
Skip If A "' 03-0
SKAEM
Skip If A = (HL)
SKC
SKLEI data
Skip If C .. 1
SKMBF bit
Skip If L = 03-0
3F
31
Skip If Accumulator
bit true
Skip If Accumulator
equals Immedlata
data
Skip If Accumulator
equals Mamory
Skip If Carry
Skip If L equals
Immediate data
Skip If Memory
bit false
1
03
1
03
0
185
1
02
1
02
B1
BO
74-77
1+S
Ablt = 1
1
01
1
DO
3F
60-6F
2+S
A ,. 03-0
SF
1+S
A - (HL)
0
DO
BO,
1+S
2+S
C • 1
1
01
B1
5A
3E
50-5F
60-63
L .. 03-0
1+S
(HL)blt = 0
B1
BO
64-87
1+S
(HL)blt = 1
J,lPD7500 SERIES
Instruction Set "B" (Cont.)
For the /APD7500, /APD7501, and /APD7506 devices only
Instruction Code
Mnemonic
TAM MOD
TCNTAM
(except ~PD7S06)
TIMER
Function
Bytes
Description
Tr~nsf;;--
TMR7_4-A
TMR3-0-(HL)
TlmerlEvent Counter
------0--0--1--1-
Accumulator and
Memory to Timer
~ ______________________ Modulo R~gIBt!1'__ _
A-TCR7-4
Transfer Timer
(HL)-TCR3_0
Count Register to
Accumulator and
Memory
- Cle;iTlmer
0
0
I
1"
3F
---f
3F
3B
I
3F
32
__ ~lJn!e!_Fle!!~ter
SKI data
Skip If IRFn AND 03-0 < > 0
_________IR_Fn:-IRFn AND NOT 03-0
Interrup;s
------0- - - - 1 - - - - - - - - -
Skip If Interrupt
1
_-",eques_t_FllIltl~ t!ue
TAMSIO
(except I'PD7S06)
SI07-4-A
SI03-0-(HL)
TSIOAM
(except ~PD7S06)
A-SI07_4
HL-SI03-0
Start Serial I/O
Operation
Transfer Accumulator and Memory
to SIO Shift Register
o --0---1o
0
1
___
IPI
_____ ~-iL
IPS4
A-P(S)
________ ~ _ _
(H~)-P(4)
IPL
A-P(L)
Input Byte from
__ _
_ __~0F!II~~_
Input from Port
-1-
o
1
3F
33
1
0
3F
3E
1-
NOP
STOP
------
IRFn
=1
-------------
- ----- - - - - - - - - - - - -
"'0
0
1
o
Parallel
0
I
1
!I
1
1
- -
1
1
1
__P~ __ ~2
0
0
1
PI
---0
1
Po
3F
CO-CF
71
3F
38
70
1
3F
1
73
-----~-------.-.-
0
0
1
1
1
0
0
1
0
0
-- - 0 - 1 - - 1 - - 1 - - - - - - - 0 - - 0 -
_--"-____
1
__ ..'"2_
1
Pl
0
Enter STOP Mode
~
-"I! ___EO-EF
n
3F
36
0
0
- - -1--------1----
00
3F
37
1
Development Tools
For software development, editing, debugging, and
assembly into object code, the NDS Development
System, designed and manufactured by NEC
Electronics U.S.A., Inc., is available. Additionally, for
systems supporting either the ISIS-II (® Intel Corp.),
CP/M (® Digital Research Corp.) or FDOS-II (® Motorola,
Inc.,) operating systems, or Fortran IV ANSI 1966 V3.9,
the ASM75 Cross-Assembler is available.
Once software development is complete, the code can
be completely evaluated and debugged with hardware
by the Evakit-7500 Evaluation Board. Available options
include the Evakit-7500-LCD LCD driver board (for the
/APD7501, /APD7502, and /APD7503), Evakit-7500-VFD
Vacuum Fluorescent Display driver board (for the
/APD7508A and /APD7519), and the Evakit-7500-RTT
Real Time Tracer. The SE-7502 System Emulation
Board will emulate complete functionality of the
--------- --------
3C
1
1
0
o
__ toI0 0J>eratl()~
__
-~---:::-------:-----:3:-::F:-------------
------ ---
Enter HALT Mode
2+S
3F
3A
1
___ lIpecl-"-"~br_'"_
Output to port,
_~l!1l'1le-"'1II1! _~lClclress
Output to Port 3
----
HALT
3F
40-47
-- - 1
1
~~
1
0
OP3
P(3)-A
~x~~tl"'J)lS06t
P(S)::A--- - - - Out-p-ut-B-yt-e-t-o- - - - - - - --------OPS4
____________ ~_::~ _________ ~I)~_~~~_
OPL
~~
OP port
1
DO
1
Transfer SIO Shift
Register to
Accumulator and
_~~X_
Input from port,
_~I1'I~.'!IIIII!~~~s~
1
f-
--_.----_._---
IP port
---------------------- - - - - - - ----------
02
0
Serl.1 Interlace
SIO
SIOCR-O
(except I'PD_?~~!L ____
IR!,O/S-O __
Skip Condition
------~-----
1
1
Cycles
/APD7501, /APD7502, or /APD7503 for demonstrating your
final system design. The SE-7508 System Emulation
Board will emulate complete functionality of the
/APD7506,/APD7507,/APD7507S,/APD7508,or/APD7508A
for demonstrating your final system design. All of these
boards take advantage of the capabilities of the
/APD7500 Rom-less evaluation chip to perform their
tasks.
Complete operation details on any /APD7500 Series
CMOS 4-Bit Microcomputer can be found in the
/APD7500 Series CMOS 4-Bit Microcomputer Technical
Manual.
186
/JPD7500 SERIES
Package Outline
",PD7500Q
IiPD7519G-XXX
XXX denotes mask number
assigned by factory at time of
code verification.
Use. I.C. Socket NP32-64075G4.
It)
...
3.2 Min
~-24.13
nc
I I~-;=
I. I.
19.05~
-18.0 - 20.1
"I
1Rj I.1
0.25±g:~g
I
-23.1 - 25.2
Package Outlines
",PD7501Q-XXX-11
",PD7502Q-XXX-11
",PD7503Q-XXX-11
2.3 Max
XXX denotes mask number
assigned by factory at time of
code verification.
Use. I.C. Socket IC-51-59S.
c
c
c
c
c
C
C
C
C
C
C
C
C
- -
I
+F=-
~
j;
[7
:7:
V
,/ R
en
/
20
-:7
C
V
10
[7
c
9
'c
~
a
>-
=160kQ
Q.
g-
/
en
V
/
/
-_.
I
Xl
P~"
1 r
20
C2
c1
I"-fT
=330kQ
=20pF
=30pF
Rl
Cl
C2
Xtal
10.~
'L
I
X2
= 32.768KHz
Supply Voltage Voo (V)
Supply Voltage VOO (V)
Supply Current
vs
System Clock Oscillation Frequency
(Note
250
Icr;:r
Supply Current
vs
System Clock Oscillation Frequency
(Note
-
~
150
----
----
---
----~-
150
0
>-
.~
~
en
= 3.0V
9
C
9
~
I
200
en
100
100
C
200
300
Oscillation Frequency
400
C = 56pF
C;...39PF
I-
V~~t::-c;;PF
50 ~---~----~~----~-------4------.-+~
100
= 100 pF
50
./
I':;::::::::
~- ~
100
500
't (KHz)
200
.~-~
300
Oscillation Frequency
400
't (KHz)
Notes:
(1) Only RIC system clock is operating and consuming power. All other internal logic blocks are not active.
~ Only crystal oscillator clock is operating and consuming power. All other internal logic blocks are not active.
197
500
" I1PD7501
Operating Characteristics (Cont.)
Typical, Ta
= 25°C
System Clock Oscillation Frequency
vs
Supply Voltage
System Clock Oscillation Frequency
vs
Aeslstance
IC~'I
500
~
N
:z:
~
;- 200
[
.tc:
C
"-
~"
100
0
~
Voo
.~
0
50
250
1
=33pF
= 33pF I
,
Ill'
¥~
200
~
--r--
i
I
j
=~
3V
-
-
A = 82kQ
150
.§
100
A = 160kQ
-
50
t;
50
100
200
500
Supply Voltage VOO (V)
Aesistance A (K ohms)
7501 05-1-82-CA T
198
NEe
~PD7502
~PD7503
NEe Electronics U.S.A. Inc.
CMOS 4·BIT SINGLE CHIP
MICROCOMPUTERS WITH LCD
CONTROLLER/DRIVER
Microcomputer Division
Description
The I-lPD7502 and the I-lPD7503 are pin-compatible
CMOS 4-bit single chip microcomputers which have the
same I-lPD750x architecture.
The I-lPD7502 contains a 2048 x 8-bit ROM, arid a 128 x
4-bit RAM. The I-lPD7503 contains a 4096 x 8-bit ROM,
and a 224 x 4·bit RAM.
Both the I-lPD7502 and the I-lPD7503 contain four 4-bit
general purpose registers located outside RAM. The
subroutine stack is implemented in RAM for greater
nesting depth and flexibility, providing such operations
as the pushing and popping of register values. The
I-lPD7502 and the I-lPD7503 typically execute 92 instruc'tions of the I-lPD7500 series "A"instruction set with a
1OJ,lS instruction cycle time.
.
The I-lPD7502 and the I-lPD7503 have two external and
two internal edge-triggered hardware vectored interrupts. They also contain an 8-bit timer/event counter
and an 8-bit serial interface to help reduce software
requirements. The on-board LCD controller/driver
supervises all Of the timing required by the 24 Port S
segment drivers and the 4 Port COM backplane drivers,
for either a: 12-digit 7-segment quadriplexed LCD, or an
a-digit 7-segment triplexed LCD.
Both the I-lPD7502 and the I-lPD7503 provide 23 I/O
lines, organized into the 3-bit input/serial interface
Port 0, the 4-bit input Port 1, the 4-bit output Port 3,
and the 4-bit I/O Ports 4, 5, and 6. They are manufactured with a low power consumption CMOS process,
allowing the use of a single power supply between 2.7V
and 5.5V. Current consumption is less than 900l-lA max·
imum, and can be lowered much further in the HALT
and STOP power-down modes. The I-lPD7502 and the
I-lPD7503 are available ina space-saving 64-pin flat
plastic package.
The I-lPD7502 is downward compatible with the
I-lPD7501.
"3
COMo
INT1
0
P12C::==
81
c:=:=
82
P1,
jAPD7502
jAPD7503
COM2
2-4,64
P33·P30
4·bll latched tristate output Port 3 (active high).
5
P03/S1
3·blt Input Port O/serlal I/O Inter1aca (active high).
P02/S0
This port can be configured either as a parallel Input port,
or as the 8·bit serial I/O Inter1ace, under control of the serial
mode 'select register. The Serial Input 51 (active high), Serial
Output SO (active high), and the Serial Clock SCK (active
low) used for synchronizing data transfer, comprise the 8-blt
serial I/O Inter1ace.
P01/~
8-11
P63-P60
4·blt Input/latched tristate output Port 6 (active high). Indi·
vidual lines can be configured alther as Inputs or as outputs
und"r control of the Port 6 mode select register.
12,15
P53·P50
4·blt Input/latched tristate output Port 5 (active high). Can
also perform 8·blt parallel 170 In conlunctlon with Port 4.
16·19
P43·P40
4·blt Input/latched tristate output Port 4 (active high). Can
also per10rm 8·blt parallel I/O In conlunctlon with Port 5.
20,21
X2, Xl
Crystal clock/external event Input Port X (active high). A
crystal oscillator circuit Is cOllnected to input Xl and output
X2 for cryatal clock operation. Alternatlveiy, external event
pulses ara connected to Input Xl whlie output X2 Is left
open for external event counting.
22
VSS
Ground.
23·25
VlCD3' VlCD2'
LCD bias voltage supply Inputs to LCD voltage controller.
Apply appropriate voltages from a voltage ladder connected
across VDD'
.
VlCDl
Power supply positive. Apply single voltage ranging from
2.7V to 5.5V for proper operation.
27·30
COM3·COMO
31·54
523. 5 0
LCD backplane driver outputs.
LCD segment driver outputs.
~~~-:---:--
55
INTl
External Interrupt INT 1 (actlva high). This Is a rising edge·
triggered Interrupt.
56
RESET
RESET Input (active high). R/C circuit or pulse Initializes
~PD7502 or ~PD7503 after power·up.
57,59
ell' Cl2
System clock Input (active high). Connect 82kQ resistor
across Cll and Cl2' and connect 33pF capacitor from Cl 1
to VSS' Alternatively, an external clock source may be con·
nected to Cl 1 , whereas Cl2 Is left open.
P13·P10
4-blt Input Port 1 (active high). line P10 Is also shared with
external Interrupt INTO' which Is a rising edge-triggered
Interrupt.
60·63
(PIO/INTO)
0
-O.3Vto +7.0V
-O.3Vto VOO +O.3V
IOH = -20mA
IOL 30mA
*Comment: Stress above those listed under "Absolute
Maximum Ratings" may cause permanent damage to
the device. This is a stress rating only and functional
operation of the device at these or any other conditions
above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
COM3
voo
VLCO,
VLCD2
VLCDa
0
Function
No connection,
=
COM1
69
NC
Operating Temperature
Storage Temperature
Power Supply Voltage, Voo
All Input and Output Voltages
Output-Current (Total, All Output Ports)
."
"
"
So
Pl3e::==: 60
-Ilfmbol
Pin No.
Absolute Maximum Ratings *
Pin Configuration
CL,e::==:
Pin Names
vss
.,
x,
199
6
iJPD7502/7503
Block Diagram.
P03/S1
P02/S0
INTO
P10/INTO
P10·P13
P30·P33
L(4)
H(4)
Program Mamory
2048 x 8-:Blt ROM (I'PD7502)
4096 x 8-:Blt ROM (I'PD7503)
Stack Pointer
P40-P43
Instruction
Decoder
Data Memory
128 x 4-81t RAM (I'PD7502)
224 x 4-81t RAM (I'PD7503)
P50·P53
LCD TIMING PULSE
System
Clock
Generator
I~Comro""'P",,,
Standby
Control
VDD
RESET
VSS
VLCD1'
VLCD2'
VLCD3
Capacitance
T.
= 25°C, VDD = OV
Umlta
P ...ameter
Symbol
M'n Typ
Teat
M••
Unit
Condition.
Input Capacitance
CI
15
pF
f;' 1 MHz,
Output Capacitance
Co
15
pF
Input/Output Capacitance
CliO
15
Unmeasured plna
r~turned to Vas
200
COMO-COM3
P60-P63
~PD7502/7503
DC Characteristics
Ta
= -10°C to + 70°C, VDD =2.7 to I. IV
Parameter
Symbol
V,H
VOO-O.5
VOO
0.9 VOO OR
0
VOO OR +0.2
Input leakage Current low
V
V
0.5
Illt!
3
10
ILil
-3
Il'l
-'10:
.jAA
VOH
Output Voltage low
VOL
Output leakage Current High
IlO H
Output leakage Current low
IlOl
All Inputs Other than Cl1. X1
Cl1. X1
All Inputs Othar than Cl1. X1
V
VOO - 0.5
0.4
V
0.5
-3
VOO = 5V ± 10%.IOH = -1.0 rnA
= -100"A=5V ± 10%. 10l .. 1.8 rnA
VOO = 2.7V to 5.5V. 10H
VOO
VOO" 2.7V to 5.5V. 10l .. 400 "AVO
'"A-
Vo
=VOO
=OV
VOO ., 5V ± 10%
5
COMO to COM3. 2.7V" VlCO" VOO
kQ
20
RS
Supply Voltage
2.0
V
1000
300
900
1'50
400
Supply Current
0.5
10
1000R
0.4
10
VOO '" 5V ± 10%
Normal Operation
"A-
=5V ± 10%
VOO = 2.7V to 5.5V
Data Retention Mode
20
10Ds
VOO = 2.7V to 5.5V
VOO
So to S23. 2.7V .. VlCO" VOO
20
VOO OR
VI = OV
Cl1. X1
"A-
RCOM
Output Impedanca
VI = VOO
Cl1. X1
All Inputs Other than Cl1. X1
"A-
VOO - 1.0
Output Voltage High
Cl1. X1
RESET. Data Retention Mode
0.3 VOO
Il'H
Te.t Condition.
All Inputs Other thsn Cl1. X1
VIHOR
V,l
Input leakage Current High
Unit
VOO
Vil
Input Voltage low
Max
TVp
0.7 VOO
VIH
Input Voltage High
"'mn.
MIn
Stop Mode. X1
VOO
VOO
=OV
VOO
=3V ± 10%
=5V ± 10%
=3V ± 10%
VOO OR = 2.0V
Data Retention Mode
AC ,Characteristics
Ta
= - 10°C to + 70°C, VDD =2.7Vto 5.5V
Umlt.
Para,,..eter
Svmbol
MIn
Typ
Max
120
200
280
80
100
130
Unit
Te.t Condition.
R = 82 kQ ± 2%
VOO = SV ± 10%
_C~=~3~3~p~F~±~5%~_______________
f,
System Clock OlKllllatlon Frequency
60
10
f'Ext
System Clock Rlsa and Fall Times
t r ,. tf,
System Clock Pulse Width
t+WH't'Wl
'x
180
200
0.2
1.5
50
,3.5
50
32
I'll
Cl1. External Clock
I'S
Cl1. External Clock
0.2
X1. External Pulse Input
I'S
X1. Extarnal Pulse Input
I's
X1. External Pulse Input
1.5
txWH' txWl
3.5
4.0
SCK Is an Input
7.0
SCK Cycle Time
tCYK:
1'8
6.7
SCi( Is an output
14.0
1.8
SCK Is an Input
3.3
SCK Pulse Width
tKWH·tKWl
I'll
3.0
SCK Is an output
6.5
SI Setup Time to SCKt
tiS
300
ns
SI Hold Time after SCKt
tlH
450
ns
8S0
SO Delay Time after
SCK~
too
1200
ns
INTO Pulse Width
tIOWH' tlOWl
10
INT 1 Pulse Width
t1 1WH· t 11 Wl
tRWH'tRWl
2/" .
I'll
10
I'll
RESET Pulse Width
RESET Setup Time
tRS
RESET Hold Time
tRH
1'.
ns
ns
201
VOO = SV ± 10%
VOO = 2.7V to S.SV
= SV
± 10%
VOO = 2.7V to s.SV.
X1. X2 Crystal Oscillator
kHz
13S
t rx • tfx
VOO = 3V ± 10%
.VOO = 2.7V to S.SV
VOO
SO
300
'XExt
Counter Clock Pulse Width
: ;:OP~Q±±5~%
Cl1. External Clock
135
Counter Clock Oscillation Frequency
Counter Clock Rise and Fall Times
~~'c~;lk ~
300
10
25
kHz
VOO = SV ± 10%
VOO
=2.7V to S.SV
VOO = SV ± 10%
VOO = 2.7V to 5.SV
VOO = SV ± 10%
VOO = 2.7V to S.5V
VOO = SV ± 10%
VOO = 2.7V to 5.5V
VOO = SV ± 10%
VOO = 2.7V to 5.5V
VOO = sv ± 10%
VOO = 2.7v to S.SV
VOO = SV ± 10%
VOO = 2.7V to S.5V
m
.'
/APD750217503
Timing Waveforms
Clocks
-I~
cL1 _ _ _ _ _ _ _ _ _
tf_+
'X:~~~~~~_-_t'_w_L
''',EXT
_t',;. ,W,;. ,H~
_ _ _ _t r _ + _ _ ' F
~
___
\~
__________
=~::
1__________,4----"w, '''':,:'jF== ~WH~=--__________ =:::
tf
x
Serial Interface
~--------------tCYK------------__~
1 0 . - - - - tKWL - - - - - - I
1 - - - - - tKWH
S C K - - - - - - - - -__
_VIH
~-----------
_VIL
tiS-tjlH
Sl-----------I--------;
-VIH
Inp~~I:~ata
'i.------------------_ VIL
"'----
~D? :r--------------------:lX<:..________-
SO--------------=x
External Interrupts
INTO
INTI
~
~
Valid Output Data
'Ow, -]F="'WH==-t
VDD----------------;
-VIH
-VIL
tl,WL
1J "'WH=1
ResetREsET----------C--tRWL----~----tRWH
Data Retention Mode
VIH
VIL
Data Retenllon
-VIH
-VIL
---\t.___________=~::
MOde--~
tRH
VIH
== VODDR
L..._________________'=
RESET-----.-J'
202
VIHDR
VIL
IJPD750217503
Operating Characteristics
Typical, Ta
= 25°C.
Supply Current
vs
Supply Voltage (Note
Supply Current
VB
Supply Voltage (Note @)
CD)
~~-
200
~
1=
R.
20
33pF
l
100
C
9
C
~
V
/'
C
50
/
0
>-
8:
/
r;:: /
9
C
~
"
V
0
a
/
Q.
/' R = 160kQ
ci!
10
lc
"
VI
/
20
10
~y,
1,
lc
VOO
250
~
1
= 39pF
~
I
J
--'-
B'4"'
0
rC2
= 330kQ
= 20pF
= 30pF
= 32.766KHz
200
m
= 3.0V
Q
9
c
~ 150
150
3
0
f
VI
11;['
VOO
C
9
c
C1
X2
Supply Current
va
System Clock Oscillation Frequency
(Note CD)
= 5.0V
I
200
X1
L
Supply Voltage VOO (V)
Supply Current
vs
System Clock Oscillation Frequency
(Note CD)
Icr;r
I
R1
C1
C2
Xtal
Supply Voltage VOO (V)
250
/
/
/
V
'"
Ci.
Q.
~
100
100
C
50
= 39pF
50
100
200
300
Oscillation Frequency
400
500
100
'+ (KHz)
200
300
Oscillation Frequency
400
'+ (KHz)
Notes:
(1) Only RIC system clock is operating and consuming power. All other internal logic blocks are not active.
(j) Only crystal oscillator clock is operating and consuming power. All other internal logic blocks are not active.
203
500
I1PD750217503
Operating Characteristics (Cont.)
Typical, Ta
= 25°C
System Clock Oscillation Frequency
vs
Supply Voltage
System Clock Oscillation Frequency
VB
Resistance
le~ll
500
:J:
:.:
;- 200
j
C = 33pF
~
N
N
:J:
200
.,"
~
::l
Voo = 3V
50
-
R
=82kQ
R
=160kQ
>u
Voo = 5V
.~
0
1= 33pF
I
~
~
"0
~
letl'
~
"
100
250
I
150
"
.2
~
~
~
100
-
-
---
50
~
50
100
200
500
Supply Voltage Voo (V)
Resistance R (K ohms)
204
7502/7503DS-12-81-CAT-TRIUM
NEe
JAPD7506
CMOS 4·BIT SINGLE CHIP
MICROCOMPUTER
NEe Electronics U.S.A. Inc.
Microcomputer Division
Pin Configuration (Cont.)
Description
The J.lPD7506 is a CMOS 4-bit single chip microcomputer which has the J.lPD750x architecture.
The J.lPD7506 contains a 1024 x 8-bit ROM, and a 64 x
4-bit RAM.
The J.lPD7506 contains two 4-bit general purpose
registers located outside RAM. The subroutine stack is
implemented in RAM for greater nesting depth and flexibility, providing such operations as the pushing and
popping of register values. The J.lPD7506 typically executes 58 instructions of the J.lPD7500 series "B" instruction set with a 10J.ls instruction cycle time.
The J.lPD7506 has one external and one internal edgetriggered testable interrupts. It also contains an 8-bit
timerlevent counter to help reduce software
requirements.
The J.lPD7506 provides 22 1/0 lines, organized into the
2-bit input Port 0, the 4-bit output Port 2, and the 4-bit
1/0 Ports 1, 4, 5, and 6. It is manufactured with a low
power consumption CMOS process, allowing the use of
a single power supply between 2.7V and 5.5V. Current
consumption is less than 600J.lA maximum, and can be
lowered much further in the HALT and STOP powerdown modes. The J.lPD7506 is available either in a
28-pin dual-in-line plastic package, or in a space-saving
52-pin flat plastic package.
The J.lPD7506 is upward compatible with the J.lPD7507
and the J.lPD7507S.
(Top View)
P43
VSS
X2
27
P03/Xl
26
P41
P20/PSTB
P21 /P TOUT
25
P40
24
23
P53
P60
22
21
P52
P51
P61
20
PSo
P62
19
P13
P22
~PD
P23
7506C
P63
18
P12
17
16
P1l
P10
VOO
15
RESET
Pin Names
40-Pln
DIP
52·Pln
Flat
1,25·27
24, 29, 30, 34
P40·P43
4·blt Input/latched tristate output Port 4 (active
high). Can also perform 8·blt parallel 1/0 In con·
junction with Port 5.
2,3
36,41
X2, P0 3 XI
'
Crystal clock/external event input Port X (actlva
high). A crystal oscillator circuit Is connected to
Input Xl and output X2 for crystal clock opera·
tlon. Alternatively, external event pulses are
connected to Input Xl while output X2 Is left
open for external event counting. line XI Is
always shared with Port 0 Input P0 3 .
4·7
42·45
8·11
47·50
P60·P63
4·blt Input/latched tristate output Port 6 (active
high). Individual lines can be configured either
as Inputs or as outputs under control of the Port
6 mode select register.
12,13
3,5
Cll' Cl2
System clock Input (active high). Connect l20kQ
resistor across Cll and Cl2' Alternatively. an
external clock source may be connected to Cl l ,
whereas Cl2 Is left open.
14
7, 33
P20·P23
P20/PSTB
NC
NC
P40
P21/PTOUT
POO/INTO
P22
P53
P23
P52
NC
NC
P80
NC
P6 1
lS
16·19
P51
9·11,16
Voo
Power supply positive. Apply single voltage
ranging from 2.7V to 5.SV for proper operation.
RESET input (active high). RIC circuit or pulse
Initializes ~P07507 or ~P07S08 after power·up.
P10·P13
4·bit input/tristate output Port 1 (active high).
Oata output to Port 1 Is strobed In synchronlza·
tlon with a P2 0/PSTB pulse.
4·blt Inputllatched tristate output Port 5 (active
high). Can also perform 8·blt parallel I/O In can·
junction with Port 4.
'20.23
• 16·18,21
24,3
23,41
28
31
1,2,4,6
12·15,19,20,
25·28,32,
35, 37.40, 46.
51,52
NC
NC
NC
~
U,:j'U ..
u
0
I- 0
~
.. U
2·blt Input Port 0 (active high). Line POO Is
always shared with external Interrupt INTO
(active high). Line P03 Is always shared with
crystal clock/external event Input XI (active
high).
U
zuzdz~!!iO:O:O:zz
II:
Rev/1
205
4·blt latched tristate output Port 2 (active high).
line P20 Is also shared with PSTB, the Port 1
output strobe pulse (active low). Line P21 Is
also shared with PTOUT' the tlmer·out F/F
signal (active high).
RESET
PSO
P13
Function
Symbol
P2l/PTOUT
P20/PSTB
POO/INTO
Cll
Cl2
Pin Configuration
NC
P42
VSS
NC
Ground.
No connection.
m
'.
-
IAPD7506
Block Diagram
POO/lNTJ
----------------------------------------~
~l
P10· P1 3
P20·P23
P20/PSTB.
P21/PTOUT
L(4)
H(4)
Program Memory
Stack Pointer (6)
1024 x 8·Blt ROM (~PD7506)
P40· P4 3
Instruction
Decoder
Data Memory
84 x 1· Bit RAM ("PD7506)
P50·P53
P60·P63
System
Clock
Generator
Standby
Control
CL2
RESET
t
VDD
t
VSS
Absolute Maximum Ratings *
Capacitance
T.
Operating Temperature
Storage Temperature
Power Supply Voltage, VOO
All Input and Output Voltages
Output-Current (Total, All Output Ports)
= 25°C, VDD = OV
LImits
Paramet.,
-O.3Vto +7.0V
-O.3VtoVoO +O.3V
IOH
-20mA
IOL 32mA
=
=
208
MIn
Typ
Max
CI
15
Output Capacitance
Co
15
Input/Output
Capacitance
CliO
15
Input Capacitance
·Comment: Stress above those listed under "Absolute
Maximum Ratings" may cause permanent damage to
the device. This is a stress rating only and functional
operation of the device at these or any other conditions
above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Symbol
Unit
T.st
Conditions
f = 1MHz.
pF
Unmeasured pins
returned to VSS
JAPD7506
, DC Characteristics
Ta
= -10°C to +70
o C,
VDD
=2.7Vto 5.5V
LImit.
Peremeter
Symbol
Min
Input Voltaga High
Input Voltage low
Typ
0.7 VOO
V,H
Me.
V+H
VOO-0.5
VOO
V,HOR
0.9 VOO
VOo
V,l
0
V
RESET. Data Retention Mode
All Inputs Other than Cl,. X,
0.5
Cl,.'X,
All Inputs Other than CL,o X,
,..A
10
'Lll
-3
'l+ l
-10
VOH
All Inputs Other than CL,o X,
VOO = SV
V
VOO - 0.5
VOL
Output leakage Current High
Output leakage Current low
'lOH
IlOl
Supply Voltage
VoO OR
-3
2.0
VOO
1000
600
100
300
Supply Current
±
10%.IOH • -1.0mA
=SV ± 10%. '2l •
I.SmA
VOO- 2.7V to S.SV. 'Ol .400,..A
,..A
Vo
,..A
Vo
V
200
=VOO
=OV
Data Ratentlon Mode
VOO
Normal Operation
1000R
0.3
5
0.4
10
VOo
,..A
= 5V
VOO = 3V
10
100S
V, = OV
VoO = 2.7V to S.SV. 10H • -IOO,..A
V
0.5
=VOo
CL,o X,
0.4
Output Voltage low
V,
Cl,. X,
,..A
VOO - 1.0
Output Voltage tUgh
CL,o X,
V
'LiH
'l+H
Input leakage Current low
All Inputs Other than Cl,. X,
+0.2
OR
0.3 VOO
OR
V+l
Input leakaga Current High
Te.t Condition.
Unit
VOO
Stop Mode. X, - OV
= SV
VOo = 3V
Data Retention Mode
VOo
OR
± 10%
± 10%
± 10%
± 10%
= 2.0V
AC Characteristics
Ta
= -10°C to
+ 70°C, VDD
2.7Vto 5.5V
LImit.
Peremeter
Symbol
t+
System Clock Oscillation Frequency
Min
Typ
200
260
60
100
130
60
10
t+ Ext
System Clock Rise and Fall Times
tr+. tf.
System Clock Pulse Width
t+WH't+Wl
fx
Counter Clock Oscillation Frequency
180
200
10
1.5
50
3.S
SO
32
t rx • tfx
Counter Clock Pulse Width
txWH' txwl
Port 1 Output Setup Time to PSTBt
tp,S
kHz
=
R
=240 kQ
120 kQ ± 2%
± 2%
0.2
kHz
X,. External Pulse Input
,..s
VOO = SV ± 10%
1I(2f."800)
tp,H
nB
SOO
IS00
300
1I(2f."800)
ns
PSTB Pulse Width
tSWl
INTO Pulse Width
tIOWH'tIOWl
10
RESET Pulse Width
tRWH'tRWl
10
RESET Setup Time
tRS
ns
RESET Hold Time
tRH
ns
1I(2f."2000)
207
VOO = 2.7V to S.SV
VOO = SV ± 10%
nB
Voo = SV ± 10%
VOO = 2.7V to S.SV
X,. External Pulse Input
X,. External Pulse Input
1/(2f."2000)
VoO = 2.7V to S.SV
X,. X2 Crystal OsCillator
3.5
3S0
= 3V ± 10%
= 2.7V to S.SV
VOo = SV ± 10%
Cl,. External Clock
135
300
Voo
VOO
Cl,. External Clock
1.5
Port 1 Output Hold Time after PSTBt
Voo = SV ± 10%
CL,o External Clock
,..s
SO
300
XExt
Counter Clock Rise and Fall Times
Cl,. Cl2
R
300
0.2
2S
Teat Condltlona
Unit
135
0
f
Me.
120
Voo = 2.7V to S.SV
VOO = SV ± 10%
VOO
= 2.7V to S.SV
Voo = SV ± 10%
VOO = 2.7V to S.SV
6
0
",PD7506
Timing Waveforms
Clocks
".~
CL1 ______________
".~
xl __________________
II1+EXT
I~WL
\
tr• j f - I + W H
-V+H
y"W" ~
-
V~L
-
V+H
"''''.
txWL
trx
-V+L
Output Strobe
-VIH
Pl0·3
VIL
tP1S
PSTB
-VIH
\
-VIL
tSWL
Extern~:::.-te-r-ru-p-t----------~:~~~~~~~_tIO_W_L_-_-_
~---",W"
-_-_-_-_ -_.-.....
ResetRESET---------------_~~-------tR-W-L----------- -_y-.
-_
Data Retention Mode
VDD--------~---~
=1\.._____________________=: :
---tRWH
---\c...._______________=~::
Data Retention Mode
_
-
RESET - - - - - - - - - "
"------------------------------
208
VIH
VDDDR
VIHDR
VIL
=
IJPD7506
Operating Characteristics
= 25°C
Typical, Ta
Supply Current
vs
Supply Voltage (Note
Supply Current
vs
Supply Voltlge (Nole
__._-
"
1
~
i
~
50
'ISO
R
'100
= 160kQ
~
'-
50
4~
50
100
200
500
Supply Voltage Voo (V)
Resistance R (K ohms)
Not••:
u :J
Z
u
~
~
~ I~
u
Z
g~
a. a.
Pin Identification
4O-Pln
DIP
52·Pln
FI.t
1,40
32,34
2-5
36-39
Symbol
Function
Crystal clOCk/external event Input Port X (aC1lve
high). A cryatal oscillator circuit Is connected to
Input Xl and output X2 for cryetal clock operetlon. Alternatively, external event pulses are con·
nected to Input Xl while output X2 Is left open
for external event counting.
P20-P23
P201PSTB
P21/PTOUT
4-blt latched trl-atete output Port 2 (active high).
Line P20 Is also shared with PSTB' the Port 1
output strobe pulse (active low). line P21 Is also
i:c~~:: ~~~tTOUT' the tlmer-out F/F signal
41-44
P10-P13
4-blt Input/trl-atate output Port 1 (active high).
Data output to Port 1 Is strobed In synchronization with a P201PSTB pulse.
10-13
46-49
P30-P33
4-blt latched trl-state output Port 3 (active high).
14-17
5D-52,2
P70-P73
4-blt Inputllatched trl-state output Port 7 (active
high).
RESET
RESET Input (active high). RIC circuit or pulse
Initializes ,.1"07507 or I'P07508 after power-up.
6-9
18
19,21
5,9
Cll' Cl2
System clock Input (active high). Connect 82kQ
resistor across Cll and Cl2' and connect 33pF
capacitor from Cll to VSS' Alternatively, an
external clock source may be connected to Cll '
whereas Cl2 18 left open.
20
7,33
VOO
Power supply positive. Apply single voltsge
ranging from 2.7V to 5.5V for proper operation.
22
10
INTl
External Interrupt INT1 (active high). This is a
rising edge-triggared Interrupt.
23-26
11,12
15,16
POollNTO
P01/SCK
P02/S0
P03/S1
4-blt Input Port O/SerlalliO Interface (active high).
This port can be configured either as a 4-blt
parallel Input port, or as the 8-blt serial 110 Interface, under control of the serial mode select
reg later . The Serial Input SI (aC1lve high), Ser:!!L
Output SO (aC1lve low), and the Serial Clock SCK
(active low) uaed for aynchronlzlng data transfer
comprise the 8-blt serial 110 Interface. line POo
P62
P60
M
Ill.,.
> a. z
Pll
NC
P63
P33
III
><
. P41
P50
P70
0
0
P13
P51
,..PD7507C
,..PD7508C
N
>< >
Plo
P52
P13
P32
a. a.
NC
P42
P12
~~u
Z
'" f
~
Xl
P201PSTB
P30
§ I~
a. a.
::C~:~:Yh~9s~a:~~c~I:: :~:~~:1~~':.~~1~~~~!8
intarrupt.
211
Il PD7 507/7508
~bsolute
Maximum Ratings *
Pin Identification (Cont.)
4o.Pln
DIP
52·Pln
Flat
27·30
17·20
P60·P63
4-blt Input/latched trl-state output Port 6 (active
high). Individual linea can be conflgurad either
as Inputa or aa outputs under control of the Port
6 mode select register.
31·34
21·24
P50-P53
4-blt Input/latched trl-state output Port 5 (active
high). Can al80 perform B-blt parallel I/O In conJunction with Port 4.
35-38
25,26,
28,30
P40-P43
VSS
NC
-O.3Vto +7.0V
-O_3Vto VOO +O.3V
IOH
-20mA
IOL 30mA
=
=
-"Comment: Stress above those listed under "Absolute
Maximum Ratings" may cause permanent damage to
the device. This is a stress rating only and functional
operation of the device at these or any other conditions
above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
4-blt Input/latched trl-state output Port 4 (active
high). Can al80 parform 8-blt parallel 110 In conJunction with Port 5.
----------------------------39
31
Ground.
1,4,6,8,
13, 14, 27, 29,
35,40,45
()peratlng Temperature
Storage Temperature
j'ower Supply Voltage, VOO
~lIlnput and Output Voltages
Output-Current (Total, All Output Ports)
Function
Symbol
--------------------
No connection.
DC Characteristics
T.
= -10°C to
+ 70°C, VDD
2.7Vto 5.5V
Umlla
Parameter
Symbol
MIn
Input Voltage High
Input Voltage low
Input leakage Current High
All Inputs Other than Cl1' X1
V+H
VOO-0.5
VOO
VIHoR
0.9 VOO
VOO OR +0.2
OR
V
Vil
0.3 VOO
V+l
O.S
-3
-10
VOH
All Inputa Other than Cl1' X1
~A
10
Il+l
All Inputa Other than Cl1' X1
Cl1' X1
ILiH
ILil
Cl1' X1
RESET, Data Retention Mode
V
All Inputa Other thin Cl1' X1
~A
VOL
Output leakage Current High
IlOH
Output leakage Current low
IlOl
Supply Voltaga
VOO OR
VOO = 2.7V to 5.SV, 10H • -100
VOO= 2.7V to S.SV, 10l .. 400 ~A
I'A
-3
2.0
900
1S0
400
Supply Current
Vo .. VOO
I'A
Vo = OV
V
Data Retention Mode
10
0.4
10
VOO = SV ± 10%
Normal Operation
20
0.5
~A
VOO • 5V ± 10%, 10l = 1.6 mA
V
0.5
300
= OV
VOO = SV ± 10%,IOH. -1.0mA
V
VOO - O.S
1000
VI
Cl1' X1
0.4
Output Voltage low
VI = VOO
Cl1' X1
VOO - 1.0
Output Voltage High
Te.t Condition.
Unit
VOO
Il+H
Input leakage Current low
Ma.
TlfP
0.7 VOO
VIH
Stop Mode, X1
I'A
VOO = 3V ± 10%
VOO .. 5V ± 10%
= OV
VOl) = 3V ± 10%
Data Retention Mode
VOO
OR
=2.0V
AC Characteristics
T.
= -10°C to
2.7Vto 5.5V
+ 70°C. VDD
Umlls
Symbol
System Clock Oscillation Frequency
MIn
TlfP
Ma.
120
200
280
60
100
130
60
10
'+EXT
System Clock Rise and Fall Times
180
200
10
,
3.5
25
KHz
R = 120 kQ ± 2%
C=33pF±S%
VOO = SV ± 10%
R = 250 kQ ± 2%
C=33pF±S%
VOO
300
0.2
1.5
System Clock Pulse Width
Cl1, Cl2
Cl1' External Clock
135
tr+' t,.
T.at Condition a
Unit
I'S
Cll' External Clock
I's
Cll' External Clock
50
50
=2.7V to S.5V
VOO = 5V ± 10%
VOO = 2.7V to 5.SV
VOO = 5V ± 10%
50 __
______
VOO
=2.7V to 5.5V
-------3~2~----~~------------~~~--~~~--------~----------
x~____________________________
Counter Clock Oscillation Frequency
300
Xl' X2 Crystal Oscillator
KHz
Xl' External Pulse Input
135
Counter Clock Rise and Fall Times
0.2
I'S
X1, External Pulse Input
I'S
Xl' External Pulse Input
1.5
Counter Clock Pulse Width
VOO = 3V ± 10%
3.5
212
VOO = 5V ± 10%
VOO = 2.7V to 5.5V
VOO
VOO
=5V ± 10%
=2.7V to 5.5V
,..PD750717508
AC Characteristics (Cont.)
Umlt.
P..remeter
Symbol
MIn
T"p
Me.
Te.t Condhlon.
Unit
4.0
ScKla an Input
7.0
SCi< Cycle Time
tCYK
,...
6.7
iCK I. an output
14.0
1.8
SCi( II an Input
3.3
SCK Pulae Width
tKwH,tKWL
",a
3.0
SCi( I. an output
8.S
SI Setup Time to ~
tiS
300
SI Hold Time a'tar ~t
tlH
450
SO Delay Time after
1200
1/(2'.-800)
tP1S
Port 1 Output Hold Time after P§TiJt
tP1H
n.
na
1/(2If2000)
300
VOO = 5V ± 10%
VOO = 2.7V to 5.5V
VOO = 5V ± 10%
VOO = 2.7v to 5.5V
VOO = SV ± 10%
VOO = 2.7V to 5.SV
na
too
Port 1 Output Settlp Time to PSTSt
Voo = 2.7V to 5.5V
na
850
SCK~
VOO = 5V ± 10%
3S0
300
500
1500
f/(2'.-800)
n8
PSTS Puille Width
tSWL
INTO Pulse Width
tlOWH' tlOWL
10
",8
INT1 Pulse Width
tI1WH'tI1WL
tRW!:I,tRWI.
2/" _
10
",a
RESET Pulae Width
RESET Setup Time
tRS
RESET Hold Time
tRH
n8
f/(2'r2000)
VOO = 5V ± 10%
VOO
=2.7V to S.5V
VOO = 5V ± 10%
Voo • 2.7V to S.5V
Voo = 5V ± 10%
VOO = 2.7V to 5.5V
VOO= 5V ± 10%
VOO = 2.7V to S.5V
",a
0
n.
nil
Capacitance
T.
=25°C, VDD =OV
LImit.
Peremeteu
Input Capacitance
Output Capacitance
Input/Output Capacitance
MIn
Typ
Te.t
Condhlon.
Me.
Unit
CI
15
pF
, = 1 MHz
Co
15
pF
CliO
15
Unmeasured pins
returned to VSS
S"mbol
m
213
I-lPD7507/7508
Block Diagram
INT1
INTO
P10·P13
P20·P23
P30·P33
H(4)
Program Memory
Stack Pointer
P4 0·P 4 3
Instruction
Decoder
lJata Memory
P50· P5 3
P60·P63
System
Clock
Generator
Standby
Control
P70·P73
RESET
Voo
VSS
214
/PSTEI.)
P20
( P21/PTOUT
IlPD7507/7508
Timing Waveforms
Clocks
t
c
=e
L1________---..!'..
11f~EXT
',W,
\
=i JF===
1
_~".=r~'.WH
t~~
~
jt
Se"allnl."ace
-VR
'"7.'=1~ ••WH==1~--------
'w,
X1 _ _ _ _ _ _ _..
-V~H
V~H
-
-V~L
~--------------tCyK----·---------------tKWL - - - - - . r~--tKWH
SCK------~----
_VIH
_VIL
tiS
-+-_____
SI _ _ _ _ _ _ _ _ _
-tiH
-VIH
bIF---Va-lId---Input Data
-VIL
So.---·CO?---~
~~_ _ _ _ _ _ _ _ _v_a_lI_d~o=ut:Pu~t~D:at:a_ _ _ _ _ _ _~:X:--------
Output Strobe
-
P10_3
t
-VIH
VIL
------.,..----~fi'_ _ _ _-------=A~r---- -
PSTB;-.
VIH
VIL
p
tP1S----r= ._lH~
__J
_
_
t
-VIH
-VIL
tswL-----
External Interrupts
INTO_ _ _ _ _ _ _ _ _ _
~----tloWL
.
1J-'.WH=1
~-------------
I
~ I
----1 t
NT1--,_----.:;i-"'WH~
tl1WL
----------------
RESET-~-tR_WL-y-.
Reset
,"WH-.\
-VIH
--------
VIL
VDD---------~I---·Data Retention MOde-..j
Data Retention Mode
RH
? f =-\- t-- - - - -
RESET-------=:lA
._VIH
-VDD
'---------------215
VIH DR
DR
VIL
I!
/JPD7507/7508
Operating Characteristics
(Typical, Ta
25°C)
=
Supply Current
vs
Supply Voltage (Note
Supply Current
vs
Supply Voltage (Note
CD)
®)
,---
200
~
R
20
V
C
/ V
1= 33pF
1
100
C
9
~
50
/'
~V
[7
V
/'
...
0
~
V
I
/
X2
I
~,~R'
ClIO lC2
20
10
Xl
/
R = 160kQ
en
/
~
V
Rl
Cl
C2
Xtal
L
~:
=
=
=
=
330kQ
20pF
30pF
32.768KHz
Supply Voltage VOO (V)
Supply Voltage VOO (V)
Supply Current
Supply Current
VII
VII
System Clock Oscillation Frequency
(Note
System Clock OacUlatlon Frequency
CD)
Voo = 5.0V
250
250
NoteQ)
ICr;[,
VOO = 3.0V
1c
I
200
9
~
a
~
C1.
:J
en
150
100
100
c
/
50
50
C .. 39pF
= 100 pF
C=56pF
~
I-
~~~~7iF
/.
I~P100
200
300
400
100
500
Osclliallon Frequency f +(KHz)
200
300
Oscillallon Frequency
400
f+ (KHz)
Not••:
(j) Only RIC system clock is operating and consuming power. All other internal logic blocks are not active.
@ Only crystal oscillator clock is operating and consuming power. All other internal logic blocks are not active.
216
500
",PD7507/7508
Operating Characteristics
(Typical, Ta
250C)
(Cont.)
=
System Clock Oscillation Frequency
V8
System Clock Oscillation Frequency
vs
Resistance
I
I
I
I
500 l -
00 I..-
~
c'~
Ic~~r
C
=33pF I
",
' " Voo = 5V
Supply Voltage
I
50
It
I--
R
C
ls33PF
-
00 -
1
-
~
-
R = 82kQ
0-
R = 180kQ
Voo = 3V
-
50
1
t;>-
T ,
~
I
I
~
so
10
200
500
J
2
3
-'---'
4
5
Supply Voltage VOO (V)
Resistance R (K ohms)
217
7507/7508-1-82- TRIUM-CAT
NOTES
218
NEe
J.LPD7507S
CMOS 4·BIT SING_LECHIP
MICROCOMPUTER
NEe Electronics U.S.A. Inc.
Microcomputer Division
Description
The IlPD7507S is a CMOS 4-bit single chip microcom.
puter which has the same IlPD750x architecture.
The IlPD7507S contains a 2048 x 8-bit ROM, and a 128
x 4-bit RAM.
.
The IlPD7507S contains two 4-bit general purpose
.
registers located outside RAM. The subroutine stack is
implemented in RAM for greater nesting depth and flexibility, providing such operations as the pushing and
popping of register values. The IlPD7507S typically executes 91 instructions of the IlPD7500 series "A" instruction set with a 1OilS 'instruction cycle time.
The IlPD7507S has two external and two internal edgetriggered, hardware vectored interrupts. It also contains, ;.
an 8-bit timer/event counter and an 8~bit serial interface
to help reduce sof1:ware requirements.
The IlPD7507S provides 20 I/O lines organized into the
4-bitinput/serial interface Port 0, the 4-bit output Port 2,
the 4-bit "output Port 3, and the 4-bit 110 Ports 4 and 5.
It is manufactured with a low power consumption
CMOS process, allowing ,the use of a single power supply between 2. 7V and 5.5V. Current consumption is
less than 900llA maximum, and can be lowered much
further in the HALT and STOP power-down modes. The
IlPD7507S is available in a 28-pin dual-in-line plastic
package.
The IlPD7507S is upward compatible with the IlPD7507,
and downward compatible with the IlPD7506.
Pin Identification
Pin'
No.
Function
Symbol
1.25-27
P40-P43
4-blt Inputllatchad trl-atate output Port 4 (active high). Can al80
perform 8-blt parallel 110 In conjunction with Port 5.
2.3
X2' Xl
Crystal clock/external event Input Port X (active high). A
crystal oscillator circuit Is connected to Input Xl end output X2
for crystal clock oparatlon. Alternatively. external event pulaea
are connected to Input Xl while output X2 la left open for
external event counting.
4-7
P20-P23
4-blt latChed trl-atate output Port 2 (active high). Line P21 la
shared with PTOUT' the tlmer-out FIF signal (active high).
P21/PTOUT
8-11
. P30-P33
4-blt latched trl-atste output Port 3 (active high).
12
RESET
RESET Input (active high). RIC circuit or pulse Inltlallzas
I'P07507 or I'P07508 after power-up.
13,1 5
Cll' Cl2
System clock Input (active high). Connect 82kQ resistor
across Cl 1 and Cl2' and connect 33pF capacitor from Cl 1 to
14
VOO
Power supply positive. Apply single voltage ranging from 2.7V
to 5.5V for propar operation.
18
INTl
External Interrupt INT 1 (ectlve high). Thla Is a rlalng edgatriggered Interrupt.
17-20
POOIINTO
4-blt Input Port O/serlal I/O Interface (active high). This port
can be configured either as a 4-blt parallel Input port. or as the
B-blt aerial 110 Interface. under control of the serial mode
select register. The Serial Input 51 (active high). Serial Output
SO (active low). and the Serial Clock ~ (active low) used for
synchronizing data tranafer comprlae the B-blt serial 110 Interface. line POO la always aha red with external Interrupt INTO
(active high) which I. a rising edge-triggered Interrupt.
~S~i..~,It:~:~~::I~'l~n':~!::~:e~~Ck source may be connected
P01/SCK
P02'S0
P03/S1
21-24
P50-P53
4-blt Inputllatched trl-.tete output Port 5 (active high). Can al80
perform 8-blt parallel I/O In conjunction with Port 4.
28
VSS
Ground.
Absolute Maximum Ratings *
Pin Configuration
P43
VSS
Xl
P42
X2
P41
P20
P40
P21/PTOUT
P53
P22
P52
P23
P51
P30
P50
P31
P03/S1
P32
P02/SO
P33
P01/SCK
RESET
POO/INTO
Cll
INTl
Voo
Cl 2
Operating Temperature
Storage Temperature
Power Supply Voltage, VOO
All Input and Output Voltages
Output-Current (Total, All Output Ports)
-65°C to + 150°C
-O.3V to + 7.0V
- O.3V to VOO + O.3V
IOH
-20mA
IOL 30mA
=
=
·Comment: Stress above those listed under "Absolute
Maximum Ratings" may cause permanent damage to
the device. This is a stress rating only and functional
operation of the device at these or any other conditions
above those indicated in the operational sections of this
speCification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
219
m
IJPD7507S
Block Diagram
P0 1/spK
P031S1
P02/S0
INT1
INTO
_---t--l---+----------------,
P201P23
. (P211PTOUT)
P30·P33
H('l)
Program Memory
2048 x 8-81T ROM (jAPD7507S)
P40·P43
Instruction
Decoder
Data Mamory
128 it 8-81T RAM (~PD7507S)
P50·P53
System
Clock
Generator
Standby
Control
RESET
VDD
Vss
220
IiPD7507S
DC Characteristics
T.
= -10
0
Cto +7o o e,vDD
= 2.7VtoS.SV
LImite
Symbol
Parameter
Input Voltage low
Input leakage Current High
V+H
VOO-0.5
VOO
VIHOR
0.9 VOO
VOO
OR
V
Cl1' X1
+ 0.2
Vil
0
OR
0.3 VOO
V+l
0
0.5
RESET, Data Retention Mode
All Inputs Other than Cl1' X1
V
Cl1' X1
All Inputs Othar than Cl1' X1
IllH
"A
10
Illl
-3
Il' l
-10
Cl1' X1
All Inputs Other than Cl1' X1
"A
Cll' XI
VOO - 1.0
Output Voltage IIIgh
Te.t Condition.
All Inputs Other than Cl1' X1
VOO
Il+H
Input leakage Current low
Unit
Ma.
0.7 VOO
VIH
Input Voltage High
Typ
MIn
VO H
VOO = 5V ± 10%,IOH = -1.0 mA
V
VOO - 0.5
VOO = 2.7V to 5.5V, 10H = -100 "A
0.4
Output Voltage L.ow
VOL
Output leakage Current High
IlOH
Output leakage Current low
IlOl
Supply Voltage
VOO OR
VOO = 5V ± 10%, 10l .. 1.8 mA
V
0.6
VOO= 2.7V to 5.5V, 10l .. 400/AA
/AA
-3
2.0
1000
300
900
150
400
Supply Current
Vo .. VOO
=OV
/AA
Vo
V
Data Retention Mode
VOO = 5V ± 10%Normal Operation
VOO = 3V ± 10%
20
0.5
10
0.4
10
VOO = 5V ± 10%
Stop Mode, XI .. OV
"A
VOO = 3V ± 10%
Data Retention Mode
VOO
OR
= 2.0V
AC Characteristics
T.
= -10°C to
+ 70 o e, VDD
= 2.7V to S.5V
LImits
Symbol
Paralneter
MIn
Typ
Ma.
120
200
280
60
100
130
Te.t Condition.
Unit
Cll' Cl
SY8tem Clock Oscillation Frequency
60
10
t+ Ext
SY8tem Clock Rise and Fall Times
180
200
0.2
1.5
50
3.5
50
32
Cll' External Clock
1'8
Cll' External Clock
,,8
Cll' External Clock
300
Counter Clock Rise and Fall Times
0.2
XI' External Pulse Input
I'S
XI' External Pulse Input
/AS
XI' External Pulsa Input
1.5
3.5
4.0
SCI< Is an Input
·'.0
SCK Cycle Time
I'S
6.7
SCK" Is an output
14.0
1.8
SCK Is an Input
3.3
SCK Pul8e Width
IKWH' tKwl
SCK Is an output
6.5
SI Setup Time to &:Kt
tiS
300
tlH
450
SO Delay Time alter
SCK~
ns
650
too
INTO Pulse Width
tIOWH' tlOWl
INT 1 Pulse Width
tllWH'tllWl
RESET Pulse Width
tRWH' tRWl
RESET Selup Time
tRS
RESET Hold Time
tRH
VOO = 2.7V to S.SV
VOO
= 5V ± 10%
= 2.7V to 5.5V
VOO
= 5V
1200
ns
,,8
10
I'S
10
I'S
ns
221
VOO = 5V ± 10%
VOO = 2.7V to 5.5V
± 10%
VOO = 2.7V to 5.5V
VOO = 5V ± 10%
VOO .. 2.7V to 5.SV
VOO = 5V ± 10%
VOO = 2.7V to 5.5V
VOO = 5V ± 10%
VOO .. 2.7V to 5.5V
VOO = 5V ± 10%
VOO = 2.7V to S.SV
I'S
3.0
SI Hold Time alter SCKt
VOO = 2.7V to S.5V
XI' X2 Crystal Oscillator
KHz
135
Counter Clock Pulse Width
VOO = 3V ± 10%
VOO
50
Counter Clock Oscillation Frequency
VOO = 6V ± 10%
VOO = 5V ± 10%
135
10
25
RIC Clolk R = 180 kQ ± 2%
C=33pF±5%
300
I r., t,.
Syslem Clock PulslI Wldlh
KHz
R = 82 kQ ± 2%
C = 33 pF ± 5%
VOO
VOO
= 5V ± 10%
= 2.7V 10 5.5V
II
~PD7S07S
Capacitance
T. = 25°C, VDD
= OV
LImits
P.r.meter
Symbol
Typ
MIn
M.x
Unit
Te.t
Conditions
Input Capacitance
CI
15
pF
1= 1 MHz
Output Capacitance
Co
15
pF
Input/Output Capacitance
CliO
15
Unmeasured pins
returned to VSS
Timing Waveforms
Clocks
_
cL1
i..-----'·w
-t
tl_.~----
1_/f+_E_XT~
c
_______________tf_.:ii=______________
X1 _ _ _ _ _ _ _ _ _
..WC
Serial Interlace
",V==='.WH
~
,'-___________
=:::
==1
'.r'.w· ___________ =:::
,n·EXT
~'--
~--------------lCyK-------------~
1 - - - - - t K w L - - - - - - I f-----tKWH
SCK----------~
_VIH
~------------
VIL
tiS-tjlH
SI-----------+------{
-VIH
Inp~~I~~ta
~------------------_ VIL
'-----
~D?-------------------""':lX-.:.___________-
SO-----,.----------=x
Valid Output Datil
Extern~:~:,-te-r-ru-p-t-s-----------~~~~~~~~~_1I_0W_L~~~~~_-_-_ F'~WH
-.....
,NT1 _ _ _ _ _ _ _ _ _ _
=--1'-___________=: :
H4'-___________=:::
~~~~~~~~~_t_'1_W_L~~~~~~~~~f
....
VIH
VIL
....:======_t'_1W
__
ResetRESET------------_~ ~~~~~~~~~-tR-w-L- --_-_-_-~-----tRwH ----\1...___________=~::
.......
Data
Retention Mode
-___
_~
! - - - o a t a Retention Mode--·
VOO-------~--,
A ==
RS
RESET------~
t
tRH
222
-
'1:._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _. - VIH
VOOOR
= ~:~DR
J,lPD7507S
Operating Characteristics
(Typical, T a
25 o e)
=
Supply Current
vs
Supply Voltage (Note
Supply Current
vs
Supply Voltage (Note
CD)
®)
--,----------
------
lq
200
R
l
1=
C
9
C
~
50
£
33pF
100
,/
:?:V
/
V'
lc
>-
~
10
9
c
~
8,..
:/
/'
0
/
20
f------------
C
V
/
I
R = 160kQ
UI
UI
/
/
/
I
i",
XI
J
fi4"'r
1
Rl
Cl
C2
Xtal
'l
Supply Voltage Voo (V)
X2
Xtal
c1
20
10
/
D
=
=
=
=
C2
330kQ
20pF
30pF
32.768 KHz
Supply Voltage VOO (V)
Supply Current
Supply Current
vs
System Clock Oscillation Frequency
(Note
System Clock
CD)
VB
Oscllla~n
Frequency
(Note \.!})
Voo = 5,OV
250
250
I
Ct;;['
VOO = 3.0V
c
1
= 39pF
lc
200
9
C
~
150
0
>-
Q.
€l-
UI
100 / - - - - ' - - / - - - _ t - - - _ + - - - _ _ + - - - - + - - - - l
100
c
= 100 pF
~
50
~~~
50
./"': - --= ,.I';;::::::: p-
I--r-------i~--_t---_+---__+~
100
200
300
Oscillation Frequency
400
C = 39pF
100
500
It (KHz)
200
C=56pF
300
Oscillation Frequency
~I-
400
It (KHz)
Notes:
(j) Only RIC system clock is operating and consuming power. All other internal logic blocks are not active.
~ Only crystal oscillator clock is operating and consuming power. All other internal logic blocks are not active.
223
C=27jF
500
IJPD7507S
Operating Characteristics (Cont.)
(Typical, T a
25°C)
=
System Clock Oscillation Frequency
VB
System Clock Oscillation Frequency
Supply Voltage
va
Resistance
I~~'I
500
~
¥
It
:;. 200
C • 33pF
i
c
.2
~
~
Voo = 3V
.~
50
4
50
33pF
200
~
i~
J
~~
~
u. 100
I'[.t'
1=
I
'\. Voo = 5V
i
0
250
100
"
200
-
R
= B2kQ
150
u.
~
100
R = 160kQ
-
50
500
Supply Voltage Voo (V)
Resistance R (K ohms)
224
7507SDS-1-82-CAT
NEe
JAPD7508A
CMOS 4·BIT SINGLE CHIP
MICROCOMPUTER WITH VACUUM
FLUORESCENT DISPLAY DRIVE
CAPABILITY
NEe Electronics U.S.A. Inc.
Microcomputer Division
Description
The ~PD7508A is a CMOS 4-bit single chip microcomputer which has the ~PD750x architecture. It is identical
to the ~PD7508, except for a slightly smaller RAM, and
16 lines of vacuum fluorescent display drive capability.
The ~PD7508A contains a 4096 x 8-bit ROM, and a 208
x 4-bit RAM.
The ~PD7508A contains four 4-bit general purpose
registers located outside RAM. The subroutine stack is
implemented in RAM for greater nesting depth and flexibility, providing such operations as the pushing and
popping of register values. The ~PD7508A typically executes 92 instructions of the ~PD7500 series "A" instruction set with a 1O~s instruction cycle time.
The ~PD7508A has two external and two internal edgetriggered hardware vectored interrupts. It also contains
an 8-bit timer/event counter and an 8-bit serial interface
to help reduce software requirements.
The ~PD7508A provides 32 110 lines organized into the
4-bit input/serial interface Port 0, the 4-bit output Port 2,
the 4-bit output Port 3, and the 4-bit I/O Ports 1, 4, 5, 6,
and 7. Ports 3, 4, 5, and 6 are capable of being pulled
to - 35V in order to drive vacuum fluorescent displays
directly. It is manufactured with a low power consumption CMOS process, allowing the use of a single power
supply between 2.7V and 5.5V. Current consumption is
less than 900~A maximum, and can be lowered much
further in the HALT and STOP power-down modes. The
~PD7508A is available in a 40-pin dual-in-line plastic
package.
Pin Names
40-Pln
DIP
X2
VSS
P43
P22
P42
P23
P41
P10
P40
Pl1
PS3
P12
8
P13
9
P51
P30
10
P50
P63
P31
11
12
P62
P33
13
P61
P70
14
P60
P71
15
P03/S1
P72
16
P02/S0
P73
17
P01/SCK
RESET
18
POOIINTO
Cll
19
INTl
VDD
20
Cl2
2-S
P2 0-P2 3
4-blt latched tristate output Port 2 (active high). Line P20 is
also shared with PS'i'B. the Port 1 output strobe pulse (active
low). line P2 1 is also shared with PTOUT' the timer out F/F
signal (active high).
6-9
P10-P13
10-13
P30-P33
4-bitlatched tristate output Port 3 (active high).
14-17
P70-P73
4-blt Inputllatched tristate output Port 7 (active high).
18
RESET
RESET input (active high). RIC circuit or pulse initializes
~PD7507 or ~PD7508 after power-up.
19.21
Cl 1 • Cl2
System clock Input (active high). Connect 82kQ resistor across
Cl 1 and Cl2. and connect 33 pF capacitor from Cl 1 to VSS'
Alternatively. an external clock source may be connected to
Cll' whereas Cl2 Is left open.
20
VDD
Power supply pOSitive. Apply single voltage ranging from 2.7V
to 5.5V for proper operation.
22
INTl
External Interrupt INT 1 (active high). This Is a rising edgetriggered Interrupt.
23-26
POolINTO
4-blt Input Port O/serlal I/O Interface (active high). This port can
be configured either as a 4-bit parallel Input port. or as the 8-bit
serial I/O Interface. under control of the serial mode select
register. The Serial Input SI (active high). Serial Output SO
(active low). and the Serial Clock SCK (active low) used for s y n - I
chronlzlng data transfer compr,lse the 8-bit serial I/O Interface.,
P0 1/SCK
P02/S0
P0 3/S1
4-blt InpUt/tristate output Port 1 (active high). Data output to
Port 1 Is strobed In synchronization with a P20/PSTB pulse.
-.r,
~:;~)P~~I~~ ~~w:~~I~~a:~~:':~~g;:~:;~~:::~;~~:tINTo (active
27-30
P6 0 -P6 3
31-34
4-blt inputllatched tristate output Port 6 (active high). Individual
lines can be configured either as Inputs or as outputs under
control of the Port 6 mode select register.
P5o-PS3
4-bit Inputllatched tristate output Port 5 (active high). Can also
perform 8-bit parallel I/O conlunctlon with Port 4.
35-38
P40-P43
4-blt Inputllatched tristate output Port 4 (active high). Can also
perform 8-blt parallel I/O In conlunctlon with Port 5.
39
VSS
Ground.
Absolute Maximum Ratings *
Operating Temperature
Storage Temperature
-65°C to + 150°C
Power Supply Voltage, Voo
-O.3V to + 7.0V
Input Voltages, Ports 4, 5, and 6
(VOO - 40.0)V to (VOO + O_3)V
All Other Input Ports
- O.3V to VOO + O.3V
Output Voltages, Ports 3, 4, 5, and 6 (VOO - 40.0)V to (VOO + O.3)V
All Other Output Ports
- O.3V to VOO +O.3V
Output-Current (Totar, All Output Ports)
IOH
-150mA
IOl SOmA
P52
P32
Crystal clock external event input Port X (active high). A crystal
oscillator circuit Is connected to Input Xl and output X2 for
crystal clock operation. Alternatively. external event pulses are
connected to Input X 1 while output X2 Is left open for external
event counting.
P21/PTOUT
Xl
P21/PTOUT
X2. Xl
P20PSTB
Pin Configuration
P20/Pffi
Function
S"mbol
1.40
=
=
·Comment: Stress above those listed under "Absolute
Maximum Ratings" may cause permanent damage to
the device. This is a stress rating only and functional
operation of the device at these or any other conditions
above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
Rev/1 device reliability_
225
•
IlPD7508A
Block Diagram
P01/SCK
P03/S1
P02/S0
INTO
Pl0·P1 3
P20·P23
P20/PSTB,
P21/PTOUT
P30·P33
L(4)
H(4)
Stack Pointer
Program Memory
P40·P43
Instruction
Decoder
4096 x 8-811 ROM (I'PD7508A)
Data Memory
208 x 4·811 R,l\M (I'PD7508A)
P50· P53
P60·P63
System
Clock
Generator
Standby
Control
P70·P73
t
RESET
t
VDD
t
VSS
226
",PD7508A
DC Characteristics
T.
=-10°C to + 70°C, VDD =2.7Vto 5.5V
UmHa
P.r.meter
Symbol
Input Voltage High
...x
Tvp
"'n
0.7 VOO
V+H
VOO - 0.5
VOO
VIHOR
0. 9V ODOR
VOOOR + 0.2
VOO
0. 3V OO
VOO": 35.0
VIL2
RESET, Oata Retention Mode
All Inputs Othsr than CL" X" Porta 4, 5, and 6
V
Ports 4, 5, and 6
"A
Ports 4, 5, and 6,
0.5
V+L
All Inputa Other than CL" X" Porta 4, 5, and 6 VI .. VOO
ILIHl
Input Leakage Current High
Input Laakage Current Low
ILIH2
60
IL+H
10
ILlL1
-3
LIL
'
2
'L+L
-30
All Inputs Other than CL"
"A
V
VOO - 0.5
VOL
Output Leakage Current High
ILOH,
iLOH2
0.5
30
-3
Output Leakaga Current Low
'LOL2
ILOL2
Supply Voltage
VOO OR
-30
2.0
1000
'ODS
1000R
Capacitance
'F. 25°C, "DD
=
300
900
150
400
0.5
10
0.4
10
Input Capacitance
Output Capacitance
Input/Output
CapaCitance
VOO .. 2.7V to 5.5V, IOL • 40011A
"A
"A
Vo .. VOO
Porta 3, 4, 5, and 6,
"A
"A
Vo .. OV
V
Oata Retention Mode
"A
Teat
Condltlona
...x
Unit
C,
20
pF
f
• Co
20
pF
Unmeasurad pins
returned to VSS
CliO
"'n
Tvp
VOO .. 5V :I: 10%, 10L • 1.SmA
Ports 3, 4, 5, and 6,
Vo .. -30V
Vo • -30V
VOO .. 5V :I: 10%
VOO. 3V :I: 10%
=OV
Symbol
VOO • 5V :I: 10%, 10H • -1.0mA
Normal Operation
Umlta
P.r.meter
V
20
Supply Current
VI • OV
VI • -30.0V
VOO '" 2.7Vto5.5V,IOH· -10011A
0.4
Output Voltaga Low
X,
Porta 4, 5, and 6,
~C-L,-,-X-,----------------------
-10
VOH
VI • VOO
CL" X,
VOO-1.0
Output Voltaga High
Teat Condltlona
V
0. 3V OO
VILt
Input Voltage Low
Unit
All Inputs Other than CL" X,
VIH
= 1MHz,
20
227
VOO .. 5V :I: 10%
Stop Mode, X, • OV
VOO '" 3V :I: 10%
-~--=---Oata Ratentlon Mode, VOO
• 2.0V
OR
m
•
/1PD7508A
AC Characteristics
Ta
=
- 10 0 C to + 70°C, VDD
= 2.7Vto I.IV
Umlt.
P.r.m.t.r
Svmbol
1+
Tvp
M.II
120
200
280
60
100
130
M',.
Syatem Clock Olclllation Frequency
R .. 82kQ ± 2%
C=33pF±S%
KHz
18(1
60
10
f'Ext
Syatem Clock Rlae and Fall Tlmea
t r •• tf,
System Clock Pulse Width
t,WH' t+Wl
Ix
200
300
13[;
10
0.2
txWH' txWl
Cll.
External
Clock
VOO = SV ± 100/.
=
Cll.
External
Clock
SO
XI. X2 Crystal OSCillator
32
VOO .. 2.7V to 5.SV
KHz
VOO = SV ± 10%
XI' External Pulae Input
135
0.2
Voo = 2.7V to S.SV
,..
XI' External Pulae Input
"S
XI' External Pulse Input
I.S
,..
7.0
tCYK
6.7
14.0
1.8
3.3
tKWH'tKWl
,..
3.0
6.S
SI Setup Time to SCKt
tiS
300
SI Hold Time after SCKt
tlH
4S0
SCK~
tSWL
VOO .. 5V ± 10%
SCK la
an
output
VOO .. 5V ± 10%
VOO .. 2.7V to 5.5V
VOO = 2.7V to 5.5V
VOO .. 2.7V to 5.5V
VOO = 2.7V to S.SV
na
300
VOO = 2.7V to 5.SV
350
SOD
1500
nl
VOO = SV ± 10%
Voo .. 2.7V to 5.5V
1/(21.600)
PSTB Pulse Width
SCK I.
an
Input
VOO • 2.7V to 5.SV
VOO = 5V ± 10%
1/(21,2000)
300
tplH
VOO '" 5V ± 10%
VOO = SV ±
1/(21,800)
Port 1 Output Hold Time after PSTBt
SCK la
an
output
nl
too
tP1S
VOO .. SV ± 10%
ns
1201)
Port 1 Output Setup Time to PSTBt
SCK Is
an
Input
na
850
SO Delay Time after
VOO = SV ± 10%
VOO = 2.7V to S.SV
4.0
SCK Pulsa Width
VOO .. 2.7V to S.5V
VOO. 5V ± 10%
3.S
Sci( Cycle Time
VOO = 3V ± 10%
VOO .. 2.7V to 5.SV
SO
2S
VOO = SV ± 10%
Cll. External Clock
SII
300
Counter Clock Pulae Width
,..
R = 160kQ ±2%
33pF ±5%
C
I.S
Ix Ext
t rx • tlx
,..
Cll. Cl2
RIC Clock
3.S
Counter Clock Oscillation Frequency
Counter Clock Rlaa and Fall Times
T ••t Condition.
U,.lt
VOO = SV ± 10%
na
11(21,2000)
VOO = 2.7V to S.5V
,.."I
INTO Pulae Width
tIOWH' tlOWl
10
INT 1 Pulse Width
tllWH'tllWl
2/1+
RESET Pulae Wldlh
tRWH'tRWl
10
RESET Setup Time
tRS
nl
RESET Hold Time
tRH
nl
"s
228
fJPD7508A
Timing Waveforms
1
~_________tr_+F~ '+WH
ClocksCL1 _ _ _ _ _ _ _ _..:..t..:!.t--l"i"
'!WL
••..XT
~>-----~WL '.'.:T
S...., Inte-'
~
_''"
__________ -
~WH--------:I
F
Xl _ _ _ _ _ _ _ _ _t:..::..
..
\
'IH
_
~----------
tCyK _________________
V+L
-V+L
~
t K W L - - - - -......
~-----------------
_VIH
r----------~--.-
VIL
liS
SI------------------+-------~-Y~---V-a-lId----
____I_np_u_t_Da_ta_ _~~.~--~------------~-VIH
-VIL
~?---
SO~
~~_ _ _ _ _ _ _v_a_"d_Ou_t~Pu~t~D~at=a_ _ _ _ _ _J:X:..._______~-VIH
VIL
Output Strobe
P10·3
~,P,"=1
¥
K.
tP1S
"
INTo-
INTl
VIL
-VIH
..,11
~
External Interrupts
VIH
-
-VIL
-tSWL
~
tioWL
~
t11WL
F~'·WH=1
-VIH
VIL
F~"'WH=1
-VIH
VIL
RESET_~I'------:'_RWL-~-tRWH-\
Reset
-VIH
~--------------
VIL
Data Retention Mode
V D D _ - - - - - - - - - - . l ! - - - - D a t a Retention M O d e - l
r
RESET.-----.,jA
I1~'--
--"tRod-H------________________
229
VIH
-~DDDR
v:r
DR
#-,PD7508A
Operating Characteristics
Typic", T.
=21°C
Supply Current
va
Supply Voltage (Note
~
l=
200
R.
100
/
C
50
'" V
~
Q.
/' R =
:J
/
/
?
Q
u
V
/
160kQ
III
V
/
20
10
1,
~
l
250
l
X1
C1
I
X2
I
Fi~·'
0
rC2
VOO
1
200
=3.0V
B
Q
ia
150
:J
u
150
.i:'
i
i
:J
III
Itt
C .. 39pF
~
i
I
Supply Current
vs
System Clock 08clllation Frequency
(Note (D)
Voo " 5.0V
I
200
/
Supply Voltage Voo (V)
Supply Current
va
System Clock Oscillation Frequency
(Note (D)
Icr;r
'/
R1 = 330kQ
C1 = 20pF
C2 = 30pF
Xtal :I 32.766KHz
Supply Voltaga VOO (V)
250
®)
/
/
C
~
~
(D)
20
33pF
l
Supply Current
vs
Supply Voltage (Note
100
100
C .. 100 pF
/ ,
C=56pF
50
50
C .. 39pF
~
_
~~~~iF
.....-:::
~::;::::::::F-
100
200
300
08clllatlon Frequency
400
100
500
'+ (KHz)
200
300
Oscillation Frequency
400
,+ (KHz)
Not•••
(j) Only RIC system clock Is operating and consuming power. All other internal logic blocks are not active.
(I) Only crystal oscillator clock Is operating and consuming power. All other internal logic blocks are not active.
230
500
I-lPD7508A
Operating Characteristics (Cont )'
Typical, T a
= 25°C
•
System Clock OS~~lalion Frequency
System Clock OS~~lalion Frequency
Supply Voltage
olt1'
Resistance
Ic~rl
r
00
~
¥
:.:
:;- 20 0
i
~o
100
C = 33pF
"~"
~
~.~
o
25
VOO = 3V
50
¥
,
1=
33pF
20 0
~
-
R = 82kQ
g
g:
1
150
c
!~
R
-
100
=
160kQ
50
~t-
I
50
100
~
200
500
2
Resistance R (K ohms)
231
4
5
Supply Voltage VOO (V)
7S08ADS-REV1-1-82-CAT-TRIUM
NOTES
232
NEe
JAPD7519
CMOS 4·BIT SINGLE CHIP
MICROCOMPUTER WITH VACUUM
FLUORESCENT DISPLAY
CONTROLLER/DRIVER
NEe Electronics U.S.A. Inc.
Microcomputer Division
Description
The IAPD7519 is a CMOS 4-bit single chip microcomputer which has the IAPD750x architecture.
The IAPD7519 contains a 4096 x 8-bit ROM, and a 256 x
4-bit RAM.
The IAPD7519 contains four 4-bit general purpose
registers located outside RAM. The subroutine stack is
implemented in RAM for greater nesting depth and flexibility, providing such operations as the pushing and
popping of register values. The IAPD7519 typically executes 92 instructions of the IAPD7500 series "A"
instruction set with a 10u.s instruction cycle time.
The IAPD7519 has two external and two internal edge- •
triggered hardware vectored interrupts. They also contain an 8-bit timer/event counter, an a-bit serial interface, and a 9-bit D/A programmable pulse generator, to
help reduce software requirements. The on-board
vacuum fluorescent display controller/driver supervises
all of the timing required by the 24 Port S segment
drivers either for a 16-digit 7-segment vacuum fluorescent display, or for an 8-character 14-segment vacuum
fluorescent display.
The IAPD7519 provides 28 I/O lines organized into
the 4-bit input/serial interface Port 0, the 4-bit output
Port 2, the 4,·bit output Port 3, and the 4-bit I/O Ports 1,
4, 5, and 6. Additionally, Port 1 can be automatically
expanded to 16 I/O lines through connection to a
IAPD82C43. The IAPD7519 is manufactured with a low
power consumption CMOS process, allowing the use of
a single power supply between 2.7V and 5.5V. Current
consumption is less than 900/AA maximum, and can be
lowered much further in the HALT and STOP powerdown modes. The IAPD7519 is available in a spacesaving 64-pin flat plastic package.
Pin Names
PIN /I
SYMBOL
NC
FUNCTION
No Connecllon.
4·blt latched tristate outpul Port 3 (acllve high).
POa/SI
P02/S0
P01/SCK
POO/INTO
4·blt Input Port O/serlal 1/0 Interface (active high). This port
can be configured either as a parallel Input port. or as Ihe
a·blt serial 1/0 Interface. under control 01 the serial mode
select register. The Serialinpul SI (active high). Serial Output
SO (active high). and the Serial Clock SCK (active low) used
lor synchronizing data transfer comprise the a-bit serial 110
Interface. Line POO Is always shared with external Interrupt
INTO, which Is a rising edge-triggered Interrupt.
4·blt inputllatched tristate output Port 6 (acllve high). Individual lines can be configured either as Inputs or as outputs
under control of the Port 6 mode select register.
4·blt Inputllatched tristate output Port 5 (acllve high). Can
also perfor'!'_a-bit parallel 110 In conjuncllon with Port 4.
4-blt Inputllatched tristate output Port 4 (acllve high). Can
also perform a·blt parallel 110 In conjuncllon with Port,.~:
Crystal clock Input (active high). A crystal oscillator circuit Is
connected to Input X1 and output X2 for system clock operalion. Alternatively, an external clock source may be con·
nected to Input X1 while output X2 Ie left open.
VSS
Ground.
Voo
Power supply positive. Apply single voltage ranging from
2.7V to 5.5V for proper ope~atlon. _ _ _ _ __
External Intarrupt INT 1 (active high). This Is a riSing edgetriggered Interrupt.
RESET
RESET Input (active high). RIC circuit or pulse Initializes
I'P07502 or I'P07503 after power-up.
P13-P10
4·blt Inputllatched tristate output Port 1 (active high).
P23-P20
4·blt latched output Port 2 (active high). Line P20 Is also
-shared with PSTB' the Port 1 output strobe pulse (active
low). Line P21 Is also shared with PTOUT' the timer-out F/F
signal (active high).
P20/PSTB
P21/PTOUT
PPG
1·blt programmable pulse generator output (active high).
Event
1·blt axternal event Input for timer/event counter (active
high).
Vacuum fluorescent display power supply negative. Apply
single voltage between VOO ,·35.0 and VOO for proper
display operation.
SO,S7
Sa/Ta.S15/T15
TO·T7
Pin Configuration
J,LPD7519
Pin Out to be
Determined
233
Vacuum fluorescant display outputs (active high). SO,S7 are
always segment driver outputs, and TO-T7 are always digit
driver outputs, Sa/Ta-S15/T15 can be configured as either
segment driver outputs or as digit driver outputs under control of the display mode select register.
6
""PD7519
Block Diagram
P03/S1
P02/S0
P01/SCK
INT1
Event
POOIINTO
----+---+----+--------------------------,
P10-P13
P20-P23
P30-P33
L(4)
H(4)
Stack Pointer
Program Memory
4096 x 8-811 ROM
(~PD7419)
P40-P43
Instruction
Decoder
Data Memory
25(; x 4-811 RAM (flPD7519)
P50-P53
P60-P63
Standby
Control
Clock
Generator
L
!":,uum Fluorescent Display
Controlier/Driver
Programmable
Pulse
Generator
Itt
RESET VSS VDD
VVFD
SO-57
S8/T8-S15/T15
TO-T7
751905·1·82· TRIUM·CA T
234
NEe
/JPD7520
4·81T SINGLE CHIP
MICROCOMPUTER WITH LED DISPLAY
CONTROLLER/DRIVER
NEe Electronics U.S.A. Inc.
MicrocompllIter Division
Description
The IlPD7520 is a low-cost 4-bit single chip microcomp",ter which shares the 4th generation architecture of
the IlPD7500 series of CMOS 4-bit microcomputers: It
contains a 768 x 8-bit ROM and a 48 x 4-bit RAM. It
has a 2-level subroutine stack, and executes a 47instruction subset of the IlPD7500 series in~tructionset.
The IlPD7520 provides 24 110 lines, organized into the
4-bit input Port 1, the 4-bit 110 Port 4, the 2-bit output
Port 3, the 8-bit output Po~ S, and the 6-bit 'output Port
T. Ports Sand T are controlled by the, on-board programmable LED display controller/driver hardware logic
block, which automatically directly drives either static or
multiplexed common-anode 7-segment LED displays
totally transparent to program execution. The IlPD7520
is manufactured with a low-power consumption PMOS
process, allowing use of a single power 'supply between
- 6V and -10V, and is available in a 28-pin dual-in-line
plastic package.
Pin Names
P31
CLK
RESET
P13
VOG
P12
So
P11
S4
P10
S1
P43
S5
P42
S2
P41
S6
P40
S3
T5
S7
T4
TO
T3
T1
VSS
T2
Segment Drive Output Port S
T0-T5
Digit Drive Output Port T
_ _ _ _ _.:..P1:.!!:0-:::..P313L..-_.....:I:::!np=ut:..:..p.:::ort:...1~----- ..-,. - - - . . P30-P31
Output Po'rt 3 .
P40-P43
CLK
Input/Output Port 4'
Clock Input
RESET
Reset
Voo
Power Supply Negative
Vss
Ground
. Further details on device operation can be found in the
, IlPD7520 4-Bit Single Chip Microcomputer Technical
Manual. .
Absolute Maximum Ratings *
Pin Configuration
P30
So-S7
Operating Temperature
Storage Temperature
Supply Voltage, VGG
Input Voltages
Output Voltages
Output Current (IOH Total)
(IOL Total)
,
-15Vto +O.3V
-15V to + O.3V
-15V to + O.3V
-100mA
90mA
*Comment: Stress above those listed under "Absolute
Maximum Ratings" may cause permanent damage to
the device. This is a stress rating only and functional
operation of the device at these or any other conditions
above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
235
n
U
",PD7520
Block Diagram
P1o-3.
P30-1
768 x 8-Blt
Program Memory
Instruction
Decoder/
Controller
[
P40-1
48 x 4-Blt
Dala Memory
P42-3
VGG _ _
VSS _ _
Clock
Generator
[
T6-7
lED DI,play Controller/Driver
RESET_
ClK
SO-7
236
TO-5
",PD7520
DC Characteristics
T.
= - 10 0 e to + 70 0 e, vaa
-6Vto -10V,
vs.
=ov
Umlts
Paramllter
.ymbol
Input Voltage High
Typ
MIn
Unit
-2.0
-1.8
V
Porta 1, 4, RESET
V
Porta 1, 4, RESET
V
ClK, External Clock
VIH
Input Voltage low
Vil
Clock Voltage High
VtH
Clock Voltage low
Vtl
Input Current High
IIH
Input leakage Current High
Input leakage Current low
Clock Current High
VGG + 1.5
Vaa + 0.8
-5.0
45
200
40
200
V
ClK, External Clock
,.A
Port 1, RESET
=
-BVto -10V
VI '"' OV, VaG = -BV :I: 1V
VI • OV, VaG = -8V to -10V
IllH
+5
JAA
Port 4, VI" OV
-S
,.A
Port 1, RESET, VI" -10V, VaG .. -10V
Illl2
-5
,.A
Port 4, VI .. -10V
0.5
mA
ClK, External Clock, VtH • OV, VGG .. -9V :I: lV
-2.1
mA
ClK, External Clock, V+l .. -5V, Vaa = -BV :I: 1V
Itl
Output Voltage low
VOL
V
VGa + 0.8
-~.O
IOH1
mA
-0.6
IOH2
mA
-1.2
Output Current High
IOH3
IOH4
lOl,
Output Current low
Port 3,
Vo .. -1.0V, VGG .. -9V :I: 1V
Port 4,
=
-8V
Vo .. -1.0V, VaG = -BV :I: 1V
VO" -1.0V, Vaa .. -8V
-5
-10
-3
-6
-1
-3
-24
-48
-13
-27
-9
-18
1.0
2.0
0.3
0.6
Vo .. -2.0V, VaG .. -9V :I: 1V
mA
1.0
Vo .. -2.0V, Vaa .. -8V
VO" -1.0V,VaG = -8Vto -10V
mA
Port T,
Vo .. -1.0V, VaG .. -9V :I: 1V
VO" -1.0V, VaG .. -6V
mA
Port 3;
Vo .. VaG + 1.5V, Vaa .. -9V :I: lV H
A
Accumulator
address
VI/>L
vGG~::::~-------------~==::==~-------
Carry Flag
C
data
Development Tools
The NEC Electronics U.S.A. 's NOS Development
System is available for the development of software
source code, editing, and assembly into object code. In
addition, the ASM75 Cross Assembler is available for
systems supporting the ISIS-II or the CP/M (@ Digital
Research Corp.) Operating Systems.
The EVAKIT-7520 Evaluation Board is available for
production device evaluation and prototype system
debugging.
The ASM75-F9T Cross Assembler is available for
systems supporting fortran IV ANSI Standard
1966-V3.9.
Immediate address
Immediate data
Bit "n" of Immediate data or Immediate address
Register H
H
HL
Register pair HL
L
Register L
P( )
Parallel Input/Output Port addressed by the value
within the brackets
PC n
Bit "n" of Program Counter
Zero when Skip Condition does not occur; the number
of bytes In next Instruction when Skip Condition
occurs
S
Stack
Stack Register
String
String Effect Skip Condition, whereby succeeding
Instructions of the same type are executed as NOP
Instructions
The contents of RAM addressed by the value within
the brackets
The contents of ROM addressed by the value within
the brackets
Load, Store, or Transfer
Exchange
Complement
LOGICAL Exclusive-OR
JI.
Instruction Set
INSTRUCTION CODE
MNEMONIC
FUNCTION
DESCRIPTION
D7
De
DIS
D4
D3
DZ
D1
Do
03
02
01
00
03
02
BYTES
CYCLES
SKIP
CONDITION
LOAD
LAI dltl
A- 0 3.0
LOld A with 4 bitt of Imme'
dllte dltl; IXlcutl suCCllding
LAI In.truction. I' NOP
In.tructlon.
LHI detl
H -01.0
LOld H with 2 bitt of imme·
dlltl dltl
LHLI detl
HL - 04.0
Load HL with 5 bin of
immedllte dltl; execute
luccNding LH LI instructions
a. NOP in.tructlonl
LAMT
A- [PC9-6, 0, C, Al H
LOId the upper 4 bitt of ROM
Table Dlte It Iddre"
Peg.6, 0, C, A to A
(HL) - [PC9-6,
0, C, AJ L
LOId the lower 4 bits of ROM
Table Data at addren
Peg.6, 0, C, A to the RAM
location addrellad by HL
0
04
A-(HL)
Load A with the contents of
RAM addres58d by HL
LIS
A-(HL)
Ls L + 1
Skip If L - OH
Load A with the contents of
RAM addres58d by HL; Increment L; skip if L - OH
LOS
A-(HL)
L= L-l
Skip if L· FH
Load A With the contents of
RAM addressed by HL;
decrement L; .kip If L - FH
0
LADR address
A-(DS-O)
Load A With the contents of
RAM addressed by 6 bitl of
immediate data
0
0
0
0
0
1
Dlj
238
1
04
1
03
0
02
01
DO
01
DO
0
0
0
01
0
DO
String
String
1 +S
L-OH
1 +S
L- FH
#-lPD7520
Instruction Set (Cont.)
SKIP
INSTRucnON CODE
MNEMONIC
FUNCTION
DESCRIPTION
D7
D&
Os
Of
D3
D2
D1
Do
0
03
02
01
DO
BYTES
CYCLES
CONDITION
STORE
ST
(HL) +- A
Store A into the RAM location
addressed by H L
0
STII data
(HL) +- 03-0
L+-L+1
Store 4 bits of immediate data
into the RAM location
addressed by HL; increment L
0
XAH
A1-0 - H1-O
A3-2 +-OOH
ExchanlJll A with H
XAL
A-L
ExchanlJll A with L
0
X
A - (HL)
Exchange A with the contents
of RAM addressed by HL
0
0
XIS
A - (HL)
L+-L+1
Skip if L = OH
Exchange A with the contents
of RAM addressed by HL;
increment L; skip If L = OH
0
0
XOS
A-(HL)
L+-L-1
Skip if L = FH
Exchange A with the contents
of RAM addressed by HL;
decrement L; skip if L = FH
0
0
XAOR address
A - (05-0)
Exchange A with the contents
of RAM addressed by 6 bits of
immediate data
0
0
EXCHANGE
0
0
0
0
1
Os
l'
1
04
0
1
0
1
0
1
0
0
0
0
0
0
1
1
0
OJ
D2
0
01
Do
OJ
D2
01
Do
2
1+S
L=OH
l+S
L= FH
2
ARITltMETIC AND LOGICAL
AISC data
A +-A + 03-0
Skip if overflow
Add 4 bits of immediate data
to A; 5kip if overflow is
generated
0
ASC
A+-A+(HL)
Skip if overflow
Add the contents of RAM
addressed by HL to A; skip if
overflow is generated
0
0
ACSC
A, C+-A + (HL) +C
Skip if C = 1
Add the contents of RAM
addressed by H L and the carry
flag to A; skip if carry is
generated
0
0
EXL
A +- A
Perform a LOGICAL
Exclusive~OR operation
between the contents of
RAM eddressed by HL and
A; store tha result in A
0
v. (HL)
0
0
0
0
1+5
Overflow
1+5
Overflow
1+5
C=1
0
If
ACCUMULATOR AND CARRY FLAG
CMA
A+-A
Complement A
0
1
1
1
RC
C+-O
Reset Carry Flag
0
0
0
0
SC
C +-1
Set Carry Flag
0
0
0
INCREMENT AND DECREMENT
ILS
L+-L+1
Skip if L = OH
Increment L;
Skip if L=OH
0
10RS address
(05-0) +- (05-0) + 1
Skip if (05-01 = OH
I ncrement the contents of
RAM addressed by 6 bits of
immediate data; Skip if the
contents = OH
0
0
OLS
L+-L-1
Skip if L = FH
Decrement L;
Skip If L= FH
0
OORS address
(1)5-0) +- (05-01 - 1
Skip if (05-01 = FH
Decrement the contents of
RAM addressed by 6 bits of
immediate data, skip if the
contents = F H
0
0
0
0
0
0
0
1
05
1
04
0
0
1
1
OJ
D2
0
01
0
05
OJ
L=OH
2+5
(Ds-ol =OH
1+5
L= FH
2
2+5
(Ds-ol = FH
Os
2
2
1
2
2
Do
0
0
0
0
D2
01
Do
0
01
Do
01
Do
0
04
1+5
2
1
BIT MANIPULATION
RMB data
(HL)bit +-0
Reset a single bit (denoted by
01001 of the RAM location
addressed by H L to zero
0
0
5MB data
(HLlbit +- 1
Set a single bit (denoted by
01001 of the RAM location
addressed by H L to one
0
0
JMP acldress
PC9-O +- 09-0
Jump to the eddress specified
by 10 bits of immediate data
0
07
0
Dg
05
0
04
0
Os
OJ
l>?
01
Do
Jump to the addrl!SS specified
by 2 bits of immediate data, A.
and the RAM contents
addressed by HL
0
0
0
0
1
0
1
1
1
0
1
0
1
01
Do
.AJ. ., CALL. AND RETURN
JAM data
PC9-8 +- 01-0
PC7-4 +- A
PC3-0 +- IHL)
0
239
/JPD7520
Instruction Set (Cont.)
SKIP
INSTRUCTION CODE
MNEMONIC
FUNCTION
OESCRIPTION
0]
Os
De
114
Da
D2
D1
Do
BYTES
CYCLES
CONDITION
1 +S
Unconditional
JU.... CALL. AND Rr:n....
0
Os
1()4
Da
Dz
D,
Do
0
1
D5
1
0
03
0
02
De
D,
Os
D4,
04
03
02
0,
DO
JCP address
PC5-O<-D5-O
Jump to the address specified
by the higher-order bitl P~ •
of the PC. and 8 bits of
immediata data
CALL address
STACK <- PC + 2
PCe:o +- De-o
Store a return address (PC + 21
in the stack; call the subroutine
program at the location specified by 10 bits of Immediate
data
CALaddreu
STACK +- PC + 1
PCg-a +- 0104 0 3
00002 0 , 0 0
Store a return address (PC + 1 I
in the stack; call the subroutine
program et one of the 32 11>8clal locations specified by 5
bits of immediata data
RT
PC+-STACK
Return from Subroutine
RTS
PC+-STACK
Skip unconditionally
Return from Subroutine; skip
unconditionally
0
SKC
Skip if C= 1
Skip if cerry flag Is true
0
SKMBTdata
Skip if (HLlbit - 1
0
0
SKMBF data
Skip If (H L1bit - 0
0
0
0
SKABTdata
Skip if
Skip If the Single bit (denoted
by 0,001 of the RAM location addressed by HL is true
Skip if the single bit (denoted
by 0, Dol of the RAM location addressed by H L is false
Skip If the single bit (denoted
by 0, DOl of A is true
SKAEI data
Skip If A
z
1
02
SKAEM
Skip If A
= (HLI
1
03
1
IPL
A+-P(LI
Input the Port addressed
by LtoA
0
D7
Os
DO
0
0
0
SKIP
~it~
1
data
0
0
Skip If A equals 4 bits of
immediata data
0
0
0
1
Skip if A equal I the RAM contentl addressed by H L
0
1
0
I+S
C~1
0,
DO
1 +S
(HUbit = 1
0,
DO
1+S
(HL)bit = 0
0,
DO
1+S
Abit -1
1
0,
1
DO
2+S
A = data
1+S
A= (HLI
0
1
0
0
1
PARALLEL I/O
0
IP1
A-PI
Input Port 1 to A
0
OPL
P(LI-A
Output A to the port
addressed by L
0
OP3
P3 +- A,-O
Output the lower 2 bits of A
to Port 3
0
0
0
0
CPU CONTROL
Perform no operation; consume one machine cycle
NOP
0
0
0
0
0
0
Package Outline jAPD7520C
I•
H
A
fI
-,
hem
A
Millimeter.
38_0 MAX
B
2.49
C
2.54
D
E
0.5 ± 0.1
33.02
Q
2.54 MIN
H
0.5 MIN
5.22 MAX
M
1_496 MAX
0.098
0.10
1.5
K
Inche.
0.02 ± 0.004
1.3
0.059
0.10 MIN
0.02 MIN
0.205 MAX
5.72 MAX
15.24
0.225 MAX
13.2
0.52
0.25
+0.10
-0.05
0.6
0.01
+0.004
-0.002
752005-12-81-TRIUM-CAT
240
NEe
J.'PD7500
CMOS 4·BIT MICROPROCESSOR
J.'PD7500 SERIES ROM·LESS
EVALUATION CHIP
NEe Electronics U.S.A. Inc.
Microcomputer Division
Description
The ",PD7500 is a CMOS 4-bit microprocessor which
has the ",PD750x architecture, and also functions as the
",PD7500 series ROM-less evaluation chip.
The ",PD7500 contains a 256 x 4-bit RAM, and is
capable of addressing up to 8192 x 8-bits of external
program memory.
The ",PD7500 contains four 4-bit general purpose
registers located outside RAM. The subroutine stack is
implemented in RAM for greater nesting depth and flex.ibility, providing such operations as the pushing and
popping of register values. The ",PD7500 typically executes either all 110 instructions of the ",PD7500 series
"A" instruction set, or all 70 instructions of the
",PD7500 series "B" instruction set with a 10",s instruction cycle time.
Th-e ",PD7500 has three external and two internal edgetriggered hardware vectored interrupts. It also contains
an 8-bit timerlevent counter and an 8-bit serial interface
to help reduce software requirements. A display timing
pulse is also provided when emulating the ",PD7501 ,
",PD7502, the ",PD7503, or the ",PD7519.
The ",PD7500 provides 32 110 lines organized into the
4-bit inputlserial interface Port 0, the 4-bit output Port 2,
the 4-bit output Port 3, and the 4-bit 110 Ports 1, 4, 5, 6,
and 7. It is manufactured with a low power consumption
CMOS process, allowing the use of a single + 5V power
supply. Current consumption is less than 900",A maximum, and can be lowered much further in the HALT
and STOP power-down modes. The ",PD7500 is available in a 64-pin quad-in-line plastic package.
Pin Configuration
Xl
X2
TEST
BUS8 C
BUSg
BUS10
BUS11
BUS12
BUS13
P40 C.
P41
P42
P43
PSo
PSl
PS2
PS3
Pso
P6l
P62
P63
P70
P7l
P72
P73
INTl
INTO
INT2
RESET
Cl2
Cll
VDD
J.LPD
7500
Vss
BUS7
BUSs
BUSS
BUS4
BUS3
BUS2
BUSl
BUSO
P13
P12
Pll
Pl0
STB
CSOUT
DISPLAY
PSEN
P2O/PSTB
P2l/PTOUT
P22
P23
P03/SI
P02/S0
POl/SCi<
POo
NC
ALE
i5rnJ'f
P33
P32
P3l
P30
241
Pin Names
Pin
No.
1,2
.unctlon
Symbol
X2, Xl
Crystal clock/external event Input Port X (active high). A
crystal oacllla1or circuit Is connected to Input Xl end output
X2 for crya1al clock opera1lon. Alternatively, external event
pulses are connected to Input Xl while output X2 Is left open
for external event counting.
TEST
Factory test pin (connect to VSS).
4-9, and
56-63
BUSO·BUS13
External dala bus (active high). Connected to external program memory.
10·13
P40·P43
4-blt Input/latched trl·state output Port 4 (active high). Can
al80 perform II-blt parallel I/O In conjunction with Port 5.
14·17
PSO·P53
4-blt Input/latched trl·state output Port 5 (active high). Can
al80 perform II-blt parallel I/O In conjunction with Port 4.
18-21
P60·P63
4-blt Input/latched trl·state output Port S (active high). Indl·
vidual lines can be configured either as Inputs or as outputa
under control of the Port S mode select register.
22-25
P70·P73
4-blt Input/latched trl·state output Port 7 (active high).
26
INTl
External Interrupt INT 1 (active high). This 18 a rising edgetriggered Interrupt.
27
INTO
External Interrupt INTO (active high). This Is a rising edge·
triggered Interrupt.
28
INT2
External Interrupt INT2 (active high). Thla Is a rising edgetriggered Interrupt.
29
RESET
RESET Input (active high). RIC circuit or pulse Inltlallze8
I'PD7500 after power·up.
30,31
Cll, Cl2
System clock Input (active high). Connect 82KQ re81stor
across Cll and Cl2' and connect 33pF capacitor from Cll to
VSS' Alternatively. an external clock source may be con·
nected to Cll' whereas Cl2 Is left open.
32
VDD
Power supply positive. Apply single voltage ranging from
2.7V to 5.SV for proper operation.
33-36
P30·P33
4-blt Inputllatched trl·state output Port 3 (active high).
37
DOUT
Data output (active lOW).
38
ALE
Address latch enable (active high).
39
NC
No connection.
40-43
POO
P01/SCK
P02/S0
P03/S1
4-blt Input Port O/serlal I/O Interface (active high). This port
can be configured either as e 4-blt parallel Input port, or liS
the 8-blt serial I/O Interface, under control of the serial mode
select register. The Serial Input SI (ac.1!¥! high). Serial Output
SO (active low), and the Serial Clock SCK (active low) used
for synchronizing data transfer comprise the 8-blt serial I/O
Interface.
44-47
P20·P23
P2O/PSTB
P2l/PTOUT
4-blt latched trl'state output Port 2 (active high). Line P20 Is
also shared with PSTB, the Port 1 output strobe pulse (active
~~;~~Il~~~rv!lhll~~:~o shared with PTOUT' the tlmer·out F/F
48
PSEN
Program store enable (active low).
49
DISPLAY
DISPLAY timing pulse (active high).
SO
CSOUT
Chip select output (active low). Connected to I'PD82C43.
Sl
STB
STROBE output (active low). Connected to I'PD82C43.
52-S5
P10·P13
4-blt Input/trl·state output Port 1 (active high). Data output to
Port 1 la strobed In synchronization with a P201PsTB pulse.
64
VSS
Ground.
II
IlPD7500
Block Diagram
P03/S1
P02/S0
Display
--t::==-
I\ ..
POO
P10-P13
P20-P23
0(4)
P30-P33
ALE
H(4)
PSEN
DOUT
Stack Pointer (8)
Address Bus
Interface
P40-P43
Instruction
Decoder
BUSo BUS13
Data Memory
256 x 4-BIT RAM (~PD7500)
-----1-----Register
Dump
I
I
P50-P53
Break
Controller
P60-P63
System
Clock
Generator
Standby
Control
P70-P73
RESET
VDD
VSS
242
",PD7500
Absolute Maximum Ratings *
AC Characteristics
=
- 10° tV + 70°C, VDD
T.
Clock Oper.tlon
-100Cto +70°C
-65°Cto +150°C
-O.3Vto +7.0V
- O.3V to VOO + O.3V
IOH = -20mA
IOL = 30mA
Llmlta
P.r.mo,or
DC Characteristics
=-10°C to + 70°C, VDD =IV :t
10%
Llmlta
Per.mo.or Symbol
Input
Voltage
High
VIH
Input
Leakage
Current
High
Input
Leakage
Current
Low
0.7VDD
"""
Unit
VDD
VDD -0.5
0.3 VDD
V+L
0.5
V
,..A
10
ILIL
-3
ILk
-10
Output
Voltage
Low
VOL
Output
Leakage
Current
High
ILOH
Output
Leakage
Current
Low
ILOL
,..A
,..A
IDDS
0.4
IDDOR
CL1 Input Clock Width
(Low)
Count Clock
OeolUatl.,n Fraquency
(X1' X2)
'xx
Count Clock
Input Frequency (X1)
IX
tCH
1.5
f'S
tCL
1.5
".
KHz
32
300
KHz
,..
f'S
x1 Input RI.e Time
tXR
0.2
X1 Input Fall Time
tXF
0.2
~JI~~~ut Clock Width
tXH
1.5
"a
X1 Input Clock Width
(Low)
tXL
1.5
,..
Symbol
M'n
""P
M ••
Unit
tLH
800
n.
tAL
200
na
Addre•• Hold Time
atter ALE~
tLA
100
na
Output Data Setup
Time to Dlffift
tDDO
200
n.
Output Data Hold
Time atter DOUTt
tDOD
100
n.
DOUT Pulae Width
(Low)
tDOL
800
na
Vo
= VDD
Vo = OV
ALE'" Data Input
Valid Time
tLDV
700
na
2000
,..A
Normal Operation
All Output Plna Open
No BUS Conlilcta
Addre ..... Data Input
Valid Time
tADV
900
na
20
I'A
Stop Mode. X1 • OV
10
PSEN Pulae Width
.(Low)
Data Retention Mode
VDD
= 2.0V
DR
pF
COUT
15
pF
CIO
15
pF
I/O Capacitance
f'S
CL1 Input Clock Width
(High)
Addre•• Setup Time
to ALE~
Unit
Output Capacitance
f'S
0.2
CL1. X1
15
CIN
0.2
tCF
ALE Pull,e Width
(High)
M ••
Input Capacitance
M'n
tCR
CL1 Input Fell Time
All Inputs Other VI·OV
than CL1. X1
LImit.
Symbol
KHz
"""
TN' Condltlona
R=82kQ:t 2%
C=33pF:t5~
CL1. Externel Clock
Xtsl OeolUatlon
--"--"-_.. -
_._-----_.
-
LImit.
=21°C, VDD =OV
P.r.me'.r
KHz
CL1 Input RI.e Time
Per.motor
CL1.X1
CapaCitance
T.
280
300
,..A
-3
IDDO
Unit
Bus I/O Operation
V
0.4
10
= VDD
V
VDD - 1.0
200
120
M ••
All Inputl Other than
CL1,X1
CL1.X1
IL+H
VOH
All Inputa Other than
CL1. X1
All Inputa Other VI
than CL1. X1
ILIH
'+
'+
TyP
Min
To •• Condltlona
CL1.X1
VDD
VIL
Output
Voltage
High
Supply
Current
M ••
V
ViH
Input
Voltage
Low
M'n
Symbol
Syatem Clock
Oscillation Frequency
"Comment: Stress above those listed under "Absolute
Maximum Ratings" may cause permanent damage to
the device. This is a stress rating only and functional
operation of the device at these or any other conditions
above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
T.
=IV :t 10%
=
T.
21°C
Operating Temperature
Storage Temperature
Power Supply Voltage, VOO
All Input and Output Voltages
Output-Current (Total, All Output Ports)
T.et Condltlona
1.1MHz
Unmeasured plna
returned to VSS
243
tpSL
PSEN ... Data Input
Valid Time
tpSDV
PSEN ... Data Float
tpSDF
1200
na
800
na
T •• t Condition.
m
/JPD7500
(,)ther Operations
Port 1 110 Operation
Umlts
LImits
Paramatar
Symbol
Min
Typ
Ma.
Unit
Symbol
Min
I..,TO Pul.. Width
tllgh
tlOH
10
III
I ~T0 Pul.. Width
I.ow
tlOl
10
'"
'"
'"
Paramatar
Ta.t C;ondltlons
~~! 1t~§lf!tt Setup
tpST
200
na
Port 1 Outll~t Hold
Time after STBt
tSTP
100
na
STB Pul.e Width
(low)
tSTL1
800
na
INT1 Pule Width
I\lgh
tl1H
2It.
OU1put Data Setup
Time to STBt
tOST
300
na
INT1 Pulse Width
'.ow
tl1l
2It+
Output Date Hold
Time .fter STBt
tSTO
100
na
INT2 Pul.. Width
ttlgh
tl2H
2It.
na
INT 2 Pulse Width
[,.ow
t'2l
2It+
na
':tESET Pul.. Width
"Igh
tRSH
10
tRSl
10
STBI - Input Date
Velld Tim.
tSTOV
STBI - Input Date
Float Time
tSTOF
Co~1
Setup Time
850
to STBI
tesT
200
na
Control Hold Time
after STBI
tSTC
100
na
STB Pul.. Width
(low)
tSTl2
1200
na
CSOUT Setup Time
to STBI
tCSST
200
na
CSOUT Hold Time
.fterml
tSTCS
100
nl
Port Output Mode
AESET Pul.e Width
110 Expander Mode
~ow
Serial Intertace Operation
Um/rl
Paramatar
SCK Cycle Time
SCK Pulse Width
High
Symbol
Min
Ty"
Ma.
Unit
4.0
~a
8.7
'"
Ta.t ConditIon.
Input
tKCY
1.8
~a
Output
Input
tKH
3.0
~a
Output
1.8
,.a
Input
3.0
,.1
Output
SCK Pul.. Width
low
tKl
SI Setup Time
to SCKt
tSIK
300
nl
SI Hold Time efter
SCKt
tKSI
450
na
SO Output Delay efter
SCKt
tKSO
850
na
244
T'If"
Ma.
Unit
'"
'"
'",...
Ta.t Condition.
J.tPD7500
Clock Timing Waveforms
i
Cl11nput
tCl
1IfX---
i.--
\
-tCH
.eRt
L-.
X11nput
i~,
1lfC
-
tXl
-
I\--
tXR_
-
tXH
\.
I
-
--:
f--tXF
Bus 110 Timing Waveforms
Cl1--------
\~---'/
\~_-----J/
f::=..t lH -
ALE
A
/
~t=.
I - - - - t A l - - l I-tlA-
8U90_7
8U910_ 13
8U98 .9
~
Address
~
~
,.
...,
""\.
I
'V
\
)~
l
f-
)
Data Out
f-
I---TDDOT
-llDV-
\
IADV
lOOD
1i1
i----IDOl - - I
\-
j
I---tPSDVj
1I
tPs~
tPsDF
""),
Data In
245
-
-
~
K
m
JAPD7500
Strobe Output Timing Waveforms
P10- P1 3 - - - - - - - - - - -
~----------------
s-ra--------------------~
1==~n,
Port 1 110 Expander Port Timing Waveforms
Expander
Port
Output
~~~
Port Control
II~J
Output Data
tOST
Expander
Port
Input
~
Port Control
f-
Input Data
tSTOV
...3 ....
... ~
f---tSTOF-
f--tSTCf--.---tCST
tSTL2
oJ" l-
CsOuT._~I----·
1/
l..---
i-tSTCS
__
t c S S T - = -_
_ _
Serial Interface Timing Waveforms
t--------tKCV-----j
SCK--------------~
~----tK-L--~ 1~-----tK-H--_~~
SI----------------+--------{I
__________________________________
Input Data
_ _ -----.
SO
~soJ
~~--------O-u-tP-u-to-a-ta--.------~)(~-------------------------------
IAPD7500
Interrupt Input Timing Waveforms
i
INl'O
(RIsing Edge· Triggered)
INTl
(RIsing Edge Triggered)
~
INT2
(Rising Edge Triggered)
}
tlOH
}
tllH
till
H
1
INTl
(Failing Edge Triggered)
~
tlOl
i
tl1H
r
till
N
112l
~
112H
U
RESET Input Timing
i
RESET
~
tRSl
}
lASH
~
Operating Characteristics
Typical, Ta
250
= 25°C
Supply Current
vs
System Clock Oscillation Frequency
(Note -
"~
C
~ 150
u
C = 33pF
~
'N
:.:
9
1/1
I~'I
500
--
50
50 ~---~------~----~-------+-------+~
'4
100
200
300
Oscillation Frequency
400
f~
500
(KHz)
50
100
200
500
Resistance R (K ohms)
Note:
00
Only RIC system clock is operating and consuming power. All other internal logic blocks are
not active.
247
7500DS-1-82-CAT
NOTES
248
NEe
MC·430P
NEe Electronics U.S.A. Inc.
Microcomputer Division
HYBRID UV EPROM
4-BIT SINGLE CHIP MICROCOMPUTER
DESCRIPTION
The MC-430P is a hybrid chip containing a J-lP05568 ROM-less Evaluation chip, a
J-lP02716 2K x 8-bit UV EPROM, a J-lPC7905 3-terminal voltage regulator, and pull-up
resistors on the same ceramic substrate. The MC-430P is pin-compatible with the
J-lP0546C/J-lP0547C, and can emulate the high-voltage drive or CMOS J-lCOM-4 microcomputers with the corresponding I/O line buffers.
The MC-430P contains a 2048 x 8-bit UV EPROM and a 96 x 4-bit RAM which
includes six working registers and the flag register. It has a level-triggered hardware
interrupt, a three-level stack, and a programmable 6-bit timer. The MC-430P executes
all 80 instructions of the extended J-lCOM-4 family instruction set.
The MC-430P provides 35 I/O lines organized into the 4-bit input ports A and 8, the
4-bit I/O ports C and 0, the 4-bit output ports E, F, G, and H, and the 3-bit output
port I. It typically executes its instructions with a 10 J-lS instruction cycle time. The
MC-430P is manufactured with a standard PMOS process, allowing use of a single
-10V power supply, and is available in a 42-pin dual-in-line ceramic hybrid package.
PIN CONFIGURATION·
MC·430P (PIN COMPATIBLE
WITH ~PD546/~PD547)
Cl,
PCO
PC,
PC2
PC3
Vss
ClO
VGG
PS3
PS2
PS,
4·
5
6
TliJ1'
RESET
POD
PO,
P02
PD3
PEO
PEl
PE2
PE3
PFo
PF,
PF2
PF3
TEST
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
EPROM WRITE PADS (~PD2716)
PSo
PA3
PA2
PAl
PAO
PI2
Pll
PIO
PH3
PH2
PHl
PHO
PG3
PG2
PGl
PGo
MC430P
Vee
A6
AS
Input Port A
PBO·PB3
Input Port B
PCO·PC3
Input/Output Port C
POO·P03
Input/Output Port 0
PEO·PE3
Output Port E
PFO·PF3
Output Port F
PGO·PG3
Output Port G
PHO·PH3
Output Port H
PIO·PI2
Output Port I
INT
Interrupt Input
CLO·Cl1
External Clock Signals
RESET
Reset
VGG
Power Suppl y Negative
VSS
Power Supply Posi tive
TEST
Factory Test Pin
(Connect to VSS)
249
A9
A4
Vpp
A3
DE
A2
Ato
At
CE/PGM
AO
07
00
06
at
as
02
a.
GND
03
PIN NAMES
PAO·PA3
AS
AO·AlO
OJ:
0 0 .07
CE/PGM
PIN NAMES
Addresses
Output Enable
Oeta Outputs
Chip Enable/Program
m
BLOCK DIAGRAM
MC-430P
,--Clo
1
I
-,....-.::::....:~no
'0
'7~O7
v"
(,ND
0
i~
'0
I
I
I
I
1'1'0556
I~
1'10
Ao
Vce
A>o
Of
f-
'r;;"",...--
eFt
!'(iM
u PI 2716
(f-PWM}
r
~
~-
[j==---
STI:P
BnrAK
Ace/PC
c:p
I
IJ
V'i(.
V55
~
J
6
6
1 : .uPD556
2 : Pull·Up Resistors
3 : .uPC7905 (3·Terminal 5 Volt Voltage Re!lulator)
4: .uPD2716 (EPROM)
5 : .uPD546C/.uPD547C Compatible Pins (42 Pins)
6 : EPROM Write Pads (24 Pads)
Operating Temperature . . . . . . . . . . . . .
Storage Temperature .. .
Supply Voltage, VGG ... .
Input Voltages . . . . . . . . . . . . .
. Output Voltages . . . . . . . . . . . .
Output Current (Total, all ports)
o
. . . . . . . . . -10°C to +70 C
. . . . . . . . . -25°C to +85°C
. . . . . . . . . -15 to +O.3V
-15 to +O.3V
-15 to +O.3V
. . . . . . . . . . . . . . . . -4mA
*COMMENT: Stress above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and functional operation of tile device at these or
any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability .
250
ABSOLUTE MAXIMUM
RATINGS*
MC-430P
MC-430P 42-PIN OPERATING
SPECI FICATIONS
DC CHARACTEfllSTICS
Ta = -10°C to +70°C' VGG = -10V
+
10% VSS ;'OV·
LIMITS
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
Input Voltage High
VIH
0
-2.0
V
Ports A through D, INT,
RESET
Input Voltage Low
VIL
-4.3
VGG
V
Ports A through D,
RESET
Clock Voltage High
VH
0
Clock Voltage Low
VL
-'6,0
Input Leakage Current High
I nput Leakage Current Low
V
CLO Input, External Clock
V
CLO Input, External Clock
II.IH
+10
jJA
Ports A through D, INT,
RESET, VI =-tv
II.IL
-10
jJA
Ports A through D, INT,
RESET, VI = -IIV
-0.8
Clock Input Leakage Current High
ILH
+200
jJA
CLO Input, VH = OV
Clock Input Leakage Current Low
1l.L
-200
jJA
CLO Input, VL = -llV
VOHI
-1.0
V
Ports C through I,
IOH = -1.0 mA
VOH2
-2.3
V
Ports C through I,
IOH· -3.3 mA
-10
jJA
Ports C through I,
Vo = -ltv
-165
mA
Output Leakage Current Lo",!
Il.OL
Supply Current
IGG
-110
T a --l0·Cto+70·C;VGG":-10V± 10%
LIMITS
PARAMETER
SYMBOL
Oscillator Frequency
Rise and
CAPACITANCE
iNT,
VGG
Output Voltage High
AC CHARACTERISTICS
TEST
CONDITIONS
f!.11
f'
Times
MIN
TYP
150
MAX
440
UNIT
TEST
CONDITIONS
KHz
t •• lf
0
0.3
JJS
Clock Pulse Width High
~WH
0.6
6.6
JJS
Clock Pulse Width Low
~WL
0.6
5.6
JJS
EXTERNAL CLOCK
Ta - 25·C
LIMITS
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
pF
Input Capacitance
CI
15
Output Capacitance
Co
40
pF
Input/Output Capacitance
CIO
30
pF
CLOCK WAVEFORM
.....- - - - - 1 / f - - - - - _ - f
251
TEST
CONDITIONS
f -I MHz
MC·430P
MC430P 24~PAD
J,LPD2716 UV-EPROM
PROGRAMMING SPEC,IFICATIONS
PROGRAM, PROGRAM VERIFY AND PROGRAM INHIBIT MODE
Ta = 2SoC ± SoC; VCC
CD
CD@
= +SV ± S%; Vpp
DC CHARACTERISTICS
= +25V ± 1V
LIMITS
PARAMETER
SYMBOL
MIN.
I nput High Voltage
VIH
+2.0
Input Low Voltage
V IL
-0.1
Input Leakage Current
IlL
TYP.
MAX.
V
+0.8
"A
V I N·5.25V/O.4511
+5
mA
~/PGM • V I L : : : : : : ~~:~~t
+30
mA
~/PGM. VIH Progrem Mode
+100
mA
IpP2
V CC Current'
V
±10
Ippt
Vpp Current
ICC
TEST CONDITIONS
UNIT
Vee +1
PROGRAM, PROGRAM VERIFY AND PROGRAM INHIBIT MODE
Ta = 25°C ± 5°C; VCC
AC CHARACTERISTICS
CD= +SV ± 5%; Vpp~= +25V ± 1V
LIMITS
TEST
SYMBOL MIN TYP MAX UNITS CONDITIONS
PARAMETER
Address Setup Time
tAS
2
/.Is
OE Setup Time
tOES
2
/.Is
Data Setup Time
tDS
2
/.IS
Address Hold Time
tAH
2
/.IS
5'f.Hold Time
-tOEH
2
/.Is
Data Hold Time
tDH
2
Output Enable to Output Float Delay
tDF
0
Output Enable to Output Delay
tOE
Program Pulse Width
tpw
Program Pulse Rise Time
tPRT
5
ns
Program Pulse Fall Time
tPFT
5
ns
45
/.IS
50
120
ns
ff/PGM = VIL
120
ns
a/PGM = VIL
55
ms
Test Conditions:
Input Pulse Levels . . . . . . . . . . O.BV to 2.2V
Input Timing Reference Level. .... 1V and 2V
Not•• :
:ternal memory
references, and goes low when pocations 4096
through 65407 are accessed.
(Tri-State Input/Output, active high) 8-bit true
bi-directional data bus used for external data
exchanges with I/O and memory.
(Input, active high) Level-sensitive interrupt input.
(I nput, active high) R ising-edge sensitive interrupt
input. Interrupts are initiated on low-to-high transitions, providing interrupts are (~nabled.
(Input) INT2 is an edge sensitive interrupt input
where the desired activation trHnsition is programmable. By setting the ES bit in the Mask
Register to a 1, INT2 is rising edge sensitive. When
ES is set to 0, INT2 is falling edge sensitive.
(Input, active low) WAIT, when active, extends
read or write timing to interface with slower
external memory or I/O. WAtT is sampled at
the end of T2, if active processor enters a wait
state TW and remains in that state as long as
WAIT is active.
(Output, active high) when active, M1 indicates
that the current machine cycle is an OP CODE
FETCH.
(Tri-State Output, active low) iNR, when active,
indicates that the data bus holds valid data. Used
as a strobe ~al for external ",emory or I/O write
operations_ WR goes to the high impedance state
during HALT, HOLD, or RESET.
(Tri-State Output, active low) .Al) is used as a
strobe to ~e data from external devices on the
data bus. R goes to the high impedance state
,during HALT, HOLD, and RESET.
(Input/Output) 8-bit I/O configured as a nibble
I/O port or as control lines.
(Input/Output) SCK provides control clocks for
Serial Port Input/Output operations. Data on the
SI line is clocked into the Seriill Register on the rising edge. Contents of the Serial Register is clocked
onto SO line on falling edges.
(Input) Serial. data is input to the processor
through the SI line. Data is clocked into the Serial
Register MSB to LSB with the rising edge of SCK.
(Output) SO is the Serial Output Port. Serial data
is output on this line on the falling edge of SCK,
MSB to LSB.
(Input, active low) ~ini':ia\izes the J.LPD7800.
(Output) Used to simulate J.LPD780117802 Port E
operation, indicating that a Fort E operation is
being performed when active.
(I nput) Clock Input
(Output) 8-bit output port wil:h latch capability.
(Tri-State Input/Output) 8-bit programmable I/O
port. Each line configurable il'ldependently as an
input or output_
258
-PIN DESCRIPTION
IlPD7800
BLOCK DIAGRAM
ABS-IS
16
ABo.7
INC/DEC
PC
INTO
SP
INTI
INT
CONTROL
V
A
C
D
INT2
H
V
A
B
C
D
E
I
I
MAIN
G.A.
DATA
MEMOAY
(12BBYTE)
ALT
G.A.
PC4ITO
PC2/SCS 0 - - - SI
o-----E~~~h
INST
DECODER
VCC
259
Vss
X,
"PD7800
Architecturally consistent with J.tPD7801/7802 devices, the J.tPD7800 ll.ses a slightly
different pin-out to accommodate for the address bus and lack of on-chip clock
generator. For complete J.tPD7800 functional operation, please refer to J.tPD7801
product information. Listed below are functional differences that exist between
J.tPD7800 and J.tPD7801 deyices.
p.PD7800/7801 Functional Differences
1. The functionality of J.tPD1801 Port E is somewhat different on the J.tPD7800.
Because the J.tPD7800 contains no program memory, the address bl,s is made
accessible to address external program memory. Thus, lines normally used for Port
E operation with the J.tPD7801 are used as the address bus on the J.tPD7800. ABOAB15 is active during memory access 0 through 4095.
2. Consequently Port E instructions (PEX, PEN, and PER) have different
fu nctional ity.
PEX Instruction - The contents of Band C register are output to ;·:he address bus .
The value 01 H is output to the data bus. STB becomes active.
PEN Instruction - Band C register contents are output to the address bus. The
value 02H is output to the data bus. STB becomes active.
PER Instruction - The address bus goes to the high impedance state. The value
04H is output to the data bus. STB becomes active.
3. ON-CHIP CLOCK GENERATOR. The J.tPD7800 contains no internal clock generator. An external clock source is input to the X 1 input.
4. PIN 30. This pin functions as the X2 crystal connection on the p.P07801. On the
J.tPD7800, pin 30 functions as a strobe output (STB) and becomes active when a
Port E instruction is executed. This control signal is useful in simulating p.PD7801
Port E operation - indicating that a port E operation is being performed.
5. PIN 2. Functions as the cI> out clock output used for synchronizinJ system external
memory and I/O devices, on the J.tPD7801. On the J.tPD7800, this pin is used to
simulate external memory reference operation of the J.tPD7801. EXT is used to
distinguish between internal and external memory references and goes low when
location 4096 through 65407 are accessed.
RECOMMENDED CLOCK DRIVE CIRCUIT
lK
joIP07800
10K
-~~D
~
T
31 Xl
1------'820
4.00 MHz
260
FUNCTIONAL DESCRIPTION
IlPD7800
ABSOLUTE MAXIMUM
RATINGS*
Operating Temperature ..........
Storage Temperature ...
Voltage On Any Pin ......
0
••••••••
0
o
0
••••
0
0
00
00
0
••
0
•
0
0
0
•
0
0
o
•••
•••••
0
0
0
•••••
o
-10 e to +70 e
o
_65°e to +150 e
-O.3V to +7.0V
••••••••••••••••••••••••••
*COMMENT: Stress above those listed under "Absolute Maximum Ratings" may cause permanent
damage to,the device. This is a stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this speciflcetion Is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliebility.
DC CHARACTERISTICS
T a --10°C-+70°C, VCC=+5.0V± 10%
LIMITS
PARAMETER
SYMBOL MIN
Input Low Voltage
Input High Voltage
Output Low Voltage
MAX
UNITS
TEST
CONDITIONS
VIL
0
0.8
V
VIH1
2.0
VCC
V
Except SCK, X1
VIH2
3.8
VCC
V
sa<.X1
0.45
VOL
Output High Voltage
CAPACITANCE
TYP
VOH1
2.4
VOH2
2.0
Low Level Input Leakage Current
IUL
High Level Input Leakage Current
IUH
Low Level Output Leakage Current
ILOL
High Level Output Leakage Current
ILOH
VCC Power Supply Current
ICC
V
IOL = 2.0mA
V
IOH" -100 IJA
V
IOH =-500 IJA
-10
IJA
VIN =OV
10
IJA
VIN = VCC
-10
IJA
VOUT = 0.45V
10
IJA
VOUT" VCC
110 200
mA
Ta- 25° C,Vcc=GND=OV
LIMITS
PARAMETER
SYMBOL MIN
TYP
MAX
UNITS
Input Capacitance
CI
10
pF
Output Capacitance
Co
20
pF
CIO
20
pF
, Input/Output Capacitance
261
"
TEST
CONDITIONS
fc = 1 MHz
All pins not:
under test at OV
"PD7800
AC CHARACTERISTICS
CLOCK TIMING
LIMITS
PARAMETER
SYMBOL
MIN
MAX
2000
TEST
UNITS CONDITIONS
r,s
tCYX
XOUT Cycle Time
tCYX
454
XOUT Low Level Width
tXXL
212
nl
tXXL
XOUT High Level Width
tXXH
212
rot
tXXH
READ/WRITE OPERATION
LIMITS
PARAMETER
'FfC) L.E. -to X OUT L.E.
SYMBOL
tRX
Address (PEO-1S) -+ Data
Input
tAD1
MIN
MAX
TEST
UNITS CONDITIONS
ns
20
550 + 500 x N
r-I
"FITfT.E. -to Address
tRA
1fU" L.E. -+ Data Input
tRD
'"Ff[)T.E. -to Data Hold
Time
tRDH
lm" Low Level Width
1m'" L.E. -to WATT L.E.
tRR
tRWT
450
liS
Address (PEO-15) -to
WAIT L.E.
tAWT1
6S0
liS
WATT Set Up Time
(Referenced from
XO UT L.E.)
tWTS
180
IlS
- tWTH
0
'1S
WAIT Hold Time
ns
2oo(T3); 7oo(T4)
350+ SOO x N
0
fiB
rlS
850+500xN
liS
(Referenced from
XOUT L.E.l
M1 -to RUL.E.
tMR
200
(IS
'FmT.E.-toM1
tRM
200
ns
ns
101M" -to "FrO L.E.
tlR
200
'FmT.E.-to 101M"
tRI
200
XO UT L.E. -to WR L.E.
txw
270
ns
Address (PEO-1S)-to
XOUTT.E.
Address (PEO-15)-to
Data Output
tAX
300
ns
Data Output -to WFf
T.E.
tow
600 + 500 x N
ns
WR T.E. -to Data
Stabilization Time
two
150
ns
Address (PEO-15)-to
L.E.
tAW
400
ns
WR T.E. -to Address
tWA
200
ns
WR Low Level Width
tww
600 +500 x N
ns
IOIl\lf-toWR L.E.
tlW
500
ns
WR T.E. -to 101M
tWI
2S0
ns
WR
tAD2
ns
450 .
ns
Stabilizetion Time
262
tCYX -500 ns
IlPD7800
AC CHARACTERISTICS
(CONT.)
SERIAL 1/0 OPERATION
PARAMETER
SYMBOL
MIN
MAX
UNIT
CONDITION
SCK Cycle Time
tCYK
BOO
900 4000
ns
ns
SCK Input
SCK Output
SCK Low Level Width
tKKL
350
400
ns
ns
SCK Input
SCK Output
SCi< High
tKKH
350
400
ns
ns
SCK Inpl,lt
SCK Output
ns
Level Width
SI Set-Up Time (referenced from SCK T.E.)
tSIS
140
SI Hold Time (referenced from SCK T.E.)
tSIH
260
SCK L.E. -.. SO Delay Time
tKO
SCSHigh -.. SCK L.E.
tCSK
100
SCK T.E. -.. SCS Low
tKCS
100
SCK T.E. -.. SAK Low
ns
ns
1BO
tKSA
ns
ns
260
ns
MAX
UNIT
PEN, PEX, PER OPERATION
PARAMETER
SYMBOL
X1 L.E. -.. EXT
MIN
tXE
Address (ABO-15) -.. STB L.E.
tAST
Data (DBO-7) -.. STB L.E.
tOST
200
STB Hold Time
tSTST
300
STB -.. Data
tSTD
400
CONDITION
ns
250
200
tCYX
= 500
ns
HOLD OPERATION
PARAMETER
SYMBOL
MIN
MAX
tHDS1
tHDS2
100
lUU
ns
ns
HOLD Hold Time (referenced from ~OUT
L.E.)
tHDH
100
ns
X OUT L.E. -.. HLDA
tXHA
HLDA High -.. Bus Floating (High Z State)
tHABF
HLDA Low -.. Bus Enable
tHABE
100
-150
CONDITION
UNIT
HOLD Set-Up Time (referenced from
X OUT L.E.l
ns
150
ns
350
ns
Notes:
CD
AC Signal waveform '(unless otherwise specified)
2.4
---X
0.45 _ _ _OtI
@
2 . 0 : : > MEASURING
O.B
POINTS
-<
2.0
O.B
X
Output Timing is measured with 1 TTL + 200 pF measuring points are VOH
VOL
@
L.E.
= Leading
Edge, T.E.
= Trailing
263
Edge
_ _ __
= 2.0V
= O.BV
"PD7800
tcvx DEPENDENT AC PARAMETERS
PARAMETER
EOUATION
MINIMAX
UNIT
tRX
(1/25) T
tA01
(3/2 + N) T- 200
tRA (T3)
(1/2) T - 50
MIN
ns
tRA (T 4)
(3/2) T - 50
MIN
ns
MIN
ns
MAX
ns
tRO
(1 +N)T-150
MAX
ns
tRR
(2 + N) T - 150
MIN
ns
ns
fRWT
(3/2) T - 300
MAX
tAWT1
(2) T- 350
MAX
ns
tMR
(1/2) T - 50
MIN
ns
tRM
(112) T - 50
MIN
ns
tlR
(1/2) T - 50
MIN
ns
MIN
ns
tRI
(1/2) T - 50
txw
(27/50) T
tA02
MAX
ns
T- 50
MIN
ns
tow
(3/2+ N) T- 150
MIN
ns
two
(1/2) T - 100
MIN
ns
tAW
T- 100
MIN
ns
ns
tWA
(1/2) T - 50
MIN
tww
(3/2 + N) T - 150
MIN
ns
tlW
T
MIN
ns
MIN
ns
tWI
(1/2) T
tHABE
(1/2) T - 150
tAST
MAX
ns
(2/5) T
MIN
ns
tOST
(2/5) T
MIN
ns
tSTST
(3/5) T
MIN
ns
tSTO
(4/5) T
MIN
ns
Notes:
CD
N = Number of Wait States
@ T=tCYX
@ Only above parameters are tCYX dependent
@ When a crystal frequency other than 4 MHz is used It CYX = 500 ns)
the above equations can be used to calculate AC parametH
values.
264
AC CHARACTERISTICS
(CONT.)
IlPD7800
CLOCK TIMING
TIMING WAVEFORMS
READ OPERATION
ABo.,.
D80·7
lW
-V--+--.:....---::::::=--+-----------------Ilr-
-+--f----{====::t:===t==~~~:j=~-----~-
--t--"""""""
~ --t--~~----~
WRITE OPERATION
ABO.,S
--oJe---------L----.l-------------.,L.-
D~q--1_-----~~::::::::~::::::::::::::::::~::::~
WIf
WAi'f
--+------.;.._..1
----------4-_1
ID/f.l
tIW--_~
265
IlPD7800
TIMING WAVEFORMS
(CaNT.)
SERIAL I/O OPERATION
tCYK
SI-+-C~~so
scs
===C:======::}-+-.-c:~=
__________~ lo------t·
_
tKCS
SAK _ _ _ _ _tKSA
_
PEN, PEX, PER OPERATION
HOLD OPERATION
266
t
IiPD7800
PACKAGE OUTLINE
~PD7800Q
Use. I.C. Socket NP32-64075G4.
(Unlt:mm)
I" I'
n<
I.
I.
24.13
19.05~
18.0 -20.1
"I
11
.1 jI-O.25±g:~
I
23.1 -25.2
7800D5-REV1-12-81-CAT
267
NOTES
268
NEe
"PD7801
NEe Electronics U.S.A. Inc.
Microcomputer Division
HIGH END SINGLE CHIP 8-BIT MICROCOMPUTER
WITH 4K ROM
PRODUCT DESCR IPTION
The NEC J.LPD7801 is an advanced 8-bit general purpose single-chip microcomputer fabricated with
N-Channel Silicon Gate MOS technology.
The NEC J.LPD7801 is intended to serve a broad spectrum of 8-bit designs ranging from enhanced
single chip applications extending into the multi-chip microprocessor range. All the basic functional
blocks - 4096 x 8 of ROM program memory, 128 x 8 of RAM data memory, 8-bit ALU, 48 I/O
lines, Serial I/O port, 12-bit timer, and clock generator are provided on-chip to enhance stand-alone
applications. Fully compatible with the industry standard 8080A bus structure, expanded system
operation can be easily implemented using any of the 8080A/8085A peripherals and memory
products. Total memory space can be increased to 64K bytes.
The powerful 140 instruction set coupled with 4K bytes of ROM program memory and 128 bytes
of RAM data memory greatly extends the range of single chip microcomputer applications. Five
level vectored interrupt capability combined with a 2 microsecond cycle time enable the J.LPD7801
to compete with multi-chip microprocessor systems with the advantage that most of the support
functions are on-chip.
F EA TU R ES
•
•
•
•
•
•
•
•
•
•
•
•
•
•
PIN CONFIGURATION
NMOS Silicon Gate Technology Requiring +5V Supply
Complete Sinqle-Chip Microcomputer with On~Chip ROM, RAM and I/O
- 4K "Bytes ROM
- 128 Bytes RAM
- 48 I/O Lines
Internal 12-Bit Programmable Timer
On-Chip 1 MHz Serial Port
Five Level Vectored, Prioritized Interrupt Structure
- Serial Port
- Timer
- 3 External Interrupts
Bus Expansion Capabilities
- Fully 8080A Bus Compatible
- 60K Bytes External Memory Address Range
On-Chip Clock Generator
Wait State Capability
Alternate Z80™ Type Register Set
Powerful 140 Instruction Set
8 Address Modes; Including Auto-Increment/Decrement
Multi-Level Stack Capabilities
Fast 2 J.LS Cycle Time
Bus Sharing Capabilities
PE15/AB15
(,bOUT
DB7
DB6
DB5
DB4
DB3
DB2
DBl
DBo
INT2
INT1
~~i$
MI
WJ!I
J!m
PC7
pe6
pe5
PC4
PC3
PC2
PCl
PCo
~
51
50
~
X2
Xl
V55(OV)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
TM: Z80 is a registered trademark of Zi109, Inc.
J.lPD
7801
Rev/1
269
Vee (+5V)
PE14/AB14
PE13/AB13
PE12/AB12
PE11/AB11
PE1O/AB1O
PEg/ABg
PEa/ABa
PE7/AB7
PE6/AB6
PE5/AB5
PE4/AB4
PE3/AB3
PE2/AB2
PE1/ABl
PEO/ABO
PB7
PB6
PB5
PB4
PB3
PB2
PBl
PBO
PA7
PA6
PA5
PA4
PA3
PA2
PAl
PAD
"PD7801
PIN NO.
DESIGNATION
1,49-63
2
PEO/ABOPE15/ AB15
¢OUT
3-10
DBO-DB7
11
12
INTO
INT1
13
INT2
14
WAIT
15
M1
16
WR
17
RD
18-25
PCO-PC7
FUNCTION
(Tri~State,
Output) 16-bit address bus.
(Output) ¢OUT provides a prescaled output clock
for use with external I/O devices or memories.
¢OUT frequency is fXTAL/2.
(Tri-State Input/Output, active high) 8-bit true
bi-directional data bus used for external data
exchanges with I/O and memory.
(Input, active high) Level-sensitive interrupt input.
(I nput, active high) R ising-edge sensitive interrupt
input. Interrupts are initiated on low-to-high transitions, providing interrupts are enabled.
(Input) INT2 is an edge sensitive interrupt input
where the desired activation transition is programmable. By setting theES bit in the Mask
Register to a 1, INT2 is rising edge snnsitive. When
ES is set to 0, INT2 is falling edge sensitive.
(Input, active low) WAIT, when actille, extends
read or write timing to interface with slower
external memory or I/O. WAIT is sampled at
the end of T2, if active processor enters a wait
state TW and remains in that state as long as
WAIT is active.
(Output, active high) when active, M1 indicates
that the current machine cycle is an OP CODE
FETCH.
(Tri-State Output, active low) WR, when active,
indicates that the data bus holds valid data. Used
as a strobe ~al for external memory or I/O write
operations. WR goes to the high impedance state
during HALT, HOLD, or RESET.
(Tri-State Output, active low) R'D is used as a
strobe to me data from external devices onto the
data bus. R goes to the high impedance state
during HALT, HOLD, and RESET.
(Input/Output) 8-bit I/O configured as a nibble
I/O port or as control lines.
(Input/Output) SCK provides control clocks for
Serial Port Input/Output operation:;. Data on the
SI line is clocked into the Serial Register on the rising edge. Contents of the Serial Re{lister is clocked
onto SO line on falling edges.
(Input) Serial data is input to the p1Ocessor
through the SI line. Data is clocked into the Serial
Register MSB to LSBwith the rising edge of SCK.
26
SCK
27
SI
28
SO
29
30
RESEi
(Output) SO is the Serial Output Port. Serial data
is output on this line on the falling edge of SCK,
MSB to LSB.
(Input, active low) ~initializes the /JPD7801.
X2
(Output) Oscillator output.
X1
PAO-PA7
PBO-PB7
(Input) Clock Inplit.
(Output) 8-bit output port with la\:ch capability.
(Tri-State Input/Output) 8-bit programmable I/O
port. Each line configurable indep(lndently as an
input or output.
31
33-40
41-48
270
PIN DESCRIPTION
IlPD7801
BLOCK DIAGRAM
,o:=[]
osc
x,
~-'-----+--'--ll
MAON
~-=---+---"----l!
G R
MEMORY
44KBYTE!
!1
VccVss
FUNCTIONAL
DESCRIPTION
Memory Map
The J,lPD7801 can directly address up to 64K bytes of memory. Except for the on-chip
ROM (0-4095) and RAM (65,408-65,535), any memory location can be used as either
ROM or RAM. The following memory map defines the 0-64K byte memory space for
the J,lPD7801 showing that the Reset Start Address, Interrupt Start Address, Call
Tables, etc., are located in the internal ROM area.
RESET
INTERNAL
ROM
(0·4095)
INTO
:~::+-...;....---+
INTS
SOFT I
LOW AD DR
HIGH ADDR
LOWADDR
HIGH ADDR
AREA
271
}t=o
} 1= 1
"PD7801
FUNCTIONAL
DESCRIPTION
(CONT.)
1/0 Ports
PORT
FUNCTIONS
Port A
a-bit output port with latch
Port B
a-bit programmable Input/Output port w/latch
Port C
a-bit nibble I/O or Control port
Port E
16-bit Address/Output Port
PortA
Port A is an a-bit latched output port. Data can be readily ttansferred between the
accumulator and the output latch buffers. The contents of the output latches can be
modified using Arithmetic and logic instructions. Data remains latched at Port A unless
acted on by another Port A instruction or a RESET is issued.
Port B
Port B is an a-bit I/O port. Data is latched at Port B in both the Input or Output modes.
Each bit of Port B can be independently set to either Input or Output modes. The
Mode B register programs the individual lines of Port B to be either an Input
(Mode Bn = 1) or an Output (Mode Bn = 0)'
Port C
Port C is an a-bit I/O port. The Mode C register is used to program the upper 6 bits of
Port C to provide control functions or to set the I/O structure per the following table.
MODE C n = 1
MODE Cn =0
Output
Input
PC1
Output
Input
PC2
SCS Input
Input
PC3
SAK Output
Output
PC4
To Output
Output
PC5
10iM' Output
Output
PCS
HLDA Output
Output
PC7
HOLD Input
Input
PCo
Port E
Port E is a 1S-bit address bus/output port. It can be set to one of three operating modes
using the PER, PEN, or PEX instructions.
• 16-Bit Address Bus - the Per instruction sets this mode for use with external I/O or
memory expansion (up to 60K bytes, externally).
• 4-Bit Output Port/12 Bit Address Bus - the PEN instruction sets this mode which
allows for memory expansion of up to 4K bytes, externally, plus the transfer of 4-bit
nibbles.
• 16-Bit Output Port - the PEX instruction sets Port E to a l6-bit output port. The contents of Band C registers appear on PEa-15 and PEO-7, respectively.
272
IlPD7801
FUNCTIONAL
DESCR IPTION
(CONT.)
Timer Operation
TO
TIMER BLOCK DIAGRAM
A programmable 12-bit timer is provided on-chip for measuring time intervals, generating pulses, and general time-related control functions. It is capable of measuring time
intervals from 4 J1S to 16 JJ.s in duration. The timer consists of a prescaler which
decrements a 12-bit counter at a fixed 4 lis' rate. Count pulses are loaded into the
12-bit down counter through timer register (TMO and TM1). Count-down operationis
initiated upon extension of the STM instruction when the contents of the down
counter are fully decremented and a borrow operation occurs, an interval interrupt
(INTT) is generated. At the same time, the contents of TMO and TM1 are reloaded
into the down-counter and countdown operation is resumed. Count operation may be
restarted or initialized with the STM ins,truction. The duration of the timeout may be
altered by loading new contents into the down counter.
The time'r flip flop is set by the STM instruction and reset on a countdowlJ operation.
Its output (TO) is available externally and may be used in a single pulse mode or general
external synchronization.
Timer interrupt (I NTT) may be disabled through the interrupt.
Serial Port Operation
~
CJ
PCs/SAK
Me3
s
a
A
r8
WAs
RD5
SERIAL PORT BLOCK DIAGRAM
273
IlPD7801
The on-chip serial port provides basic synchronous serial communication functions
allowing the NEC pPD7801 to serially interface with external devices.
Serial Transfers are synchronized with either the internal clock or an external clock
input (SCK). The transfer rate is fixed at 1 Mbit/second if the internal clock is used
or is variable between DC and 1 Mbit/second when an exterral clock is used. The
Clock Source Select is determined by the Mode C register. The serial clock (internal
or external SCK) is enabled when the Serial Chip Select Signal (SCS) goes low. At this
time receive and transmit operations through the Serial Input port (SI)/Serial Output
port (SO) are enabled. Receive and transmit operations are performed MSB first.
Serial Acknowledge (SAK) goes high when data transfers between the accumulator
and Serial Register is completed. SAK goes low when the buffer becomes full after
the completion of serial data receive or transmit operations. While SAK is low, no
further data can be received.
I nterrupt Structure
The pPD7801 provides a maskable interrupt structure capable of handling vectored
prioritized interrupts. Interrupts can be generated from six different sources; three
external interrupts, two internal interrupts, and non-maskable software interrupt.
Each interrupt when activated branches to a designated mer'lory vector location
for that interrupt.
INT
VECTORED MEMORY
LOCATION
PRIORITY
TYPE
INTT
8
3
Internal, Timer
Overflow
INTS
64
6
Internal, Serial
Buffer Full/Empty
INTO
4
2
Ext., level sensitive
INT1
16
4
Ext., Rising edge
sensitive
INT2
32
5
Ext., Rising/Falling
edge sensitive,
SOFTI
96
1
Software Interrupt
274
FUNCTIONAL
DESCRIPTION
(CaNT.)
IlPD7801
FUNCTIONAL
RESET (Reset)
OESCR IPTION
(CONT.)
An active low-signal on this input for more than 4 /lS forces the /lPD7801
into a Reset condition. RESET affects the following internal functions:
•
•
•
•
•
•
•
•
•
•
•
The Interrupt Enable Flags. are reset, and Interrupts are inhibited.
The Interrupt Request Flag is reset.
The HALT flip flop is reset, and the Halt-state is released.
The contents of the MODE B register are set to FFH, and Port B
becomes an input port.
The contents of the MODE C register are set to FFH. Port C becomes
an I/O port and output lines go low.
All Flags are reset to O.
The internal COUNT register for timer operation is set to FFFH and the
timer F/f is reset.
The ACK F'/F is set.
The HLDA F/F is reset.
The contents of the Program Counter are set to OOOOH.
The Address Bus (PEO-15), Data Bus (DBO-7),RD, andWFf go to
a high impedance state.
Once the
REG ISTE RS
'R'Es'ET input goes high, the program is started at location OOOOH.
The /lPD7801 contains sixteen 8-bit registers and two 16-bit registers.
0
I
PC
0'
70'
I
SP
I
V
7
A
B
C
0
E
H
L
V'
A'
B'
C'
0'
E'
H'
L'
Main
Alternate
General Purpose Registers (B, C, 0, E, H, L)
There are two sets of general purpose registers (Main: B, C, 0, E, H, L:
Alternate: B', C',O', H', L'). They can function as auxiliary registers to the
accumulator or in pairs as data pointers (BC, DE, HL,B'C', D'E', H'L'). Auto Increment and Decrement addressing mode capabilities extend the uses for the DE, HL,
D'E', and H'L' register-pairs. The contents of the BC, DE, and HL register-pairs
can be exchanged with their Alternate Register counterparts using the EXX
instruction.
275
"PD7801
Vector Register (V)
When defining a scratch pad area in the memory space, the upper a-bit memory
address is defined in the V-register and the lower 8-bits is defined by the immediate
data of an instruction. Also the scratch pad indicated by the V-register can be used
as 256 x a·bit working registers for storing software flags, parameters and counters.
FUNCTIONAL
DESCRIPTION (CONT.)
Accumulator (A)
All data transfers between the /1PD7801 and external memory or 1/0 are done through
the accumulator. The contents of the Accumulator and Vector Registers can be
exchanged with their Alternate Registers using the EX instruction.
Program Counter (PC)
The PC is a 16-bit register containing the address of the next instruction to be
fetched. Under normal program flow, the PC is automatically incremented. However,
in the case of a branch instruction, the PC contents are from another register or
an instruction's immediate data. A reset sets the PC to OOOOH.
Stack Pointer (SP)
The stack pointer is a 16-bit register used to maintain the top of the stack area (lastin-first-out). The contents of the SP are decremented during a CALL or PUSH
instruction or if an interrupt occurs. The SP is incremented during a R ETU R N or
POP instruction.
Register Addressing
Working Register Addressing
Register Indirect Addressing
Direct Addressing
Auto-Increment Addressing
Immediate Addres!:ing
Auto-Decrement Addressing
Immediate Extended Addressing
Register Addressing
I OPCODE
r
~------------~.~~~ANDI
The instruction opcode specifies a register r which contains the operand.
Register Indirect Addressing
memory
rp
IOPCODE 1-1---I·~I ADDRESSt-1---I.IOot~PERAND I
The instruction opcode specifies a register pair which contains 1:he memory address
of the operand. Mnemonics with an X suffix are ending this address mode.
Auto·1 ncrement Addressing
rp
memory
IOPCODE It-----I..~I ADD REssll--;r..,.---4.......[QPE RAN D I
+L-_ _@]
The opcode specifies a register pair which contains the memory address of the,
operand. The contents of the register pair is automatically incram'ented to point to
a new operand. This mode provides automatic sequential stepping when working with
a table, of operands.
276
ADDRESS MODES
IlPD7801
ADDRESS MODES (CONT.)
Auto-Decrement Addressing
memory
rp
IOPCODEII-- - - - t• ..tIADDfLRE_S_S_'_6 I OPERAND I
Working Register Addressing
memory
PC
PC + 1
The contents of the register is linked with the byte following the opcode to form a
memory address whose contents is the operand. The V register is used to indicate
the memory page. This address mode is useful as a short-offset address mode when
working with operands in a common memory page where only 1 additional byte
is required for the address. Mnemonics with a W suffix ending this address mode.
Direct Addressing
PC
OPCODE
PC + 1
Low Address
PC+ 2
High Address
1
Memory
1-F operand
------
1 byte
2 byte
The two bytes following the opcode specify an address of a location containing the
operand.
Immediate Addressing
PC
PC + 1
I mmediate Extended Addressing
PC
OPCODE
PC + 1
Low Operand
PC + 2
High Operand
277
",PD7801
INSTRUCTION SET
Operand Description
DESCRIPTION
OPERAND
r
r1
r2
Notes:
V,A,B,C,O,E,H,L
B,C,O,E,H,L
A,B,C
sr
PA PB PC MK MB MC TMO TM1 S
S
sr1
PA PB PC MK
sr2
PAPBPCMK
rp
SP, B, 0, H
rp1
V,B,O,H
rpa
B,O,H,O+,~+,O-,H-
rpa1
B,O,H
wa
8 bit immediate data
word
16 bit immediate data
byte
8 bit immediate data
bit
3 bit immediate data
f
FO, F 1, F2; FT, FS,
1. When special register operands sr, sr1, sr2 are used; PA=PorJ: A, PB=Port B,
PC=Port C, MK=Mask Register, MB=Mode B Reg;ster, MC=Mode C
Register, TMO=Timer Register 0, TM 1 =Timer Reg;ster 1, S=Serial Register.
2. When register pair operands rp, rp1 are used; SP=Stack Pointer, B=BC,
O=OE, H=HL, V=VA.
3. Operands rPa, rPa 1, wa are used in indirect addressing and auto-increment/
auto-decrement addressing modes.
B=(BC), O=(OE), H=(HL)
O+=(OE)+, H+=(HL)+, O-=(OE)-, H-=(HL)-.
4. When the interrupt operand f is used; FO=INTFO, Fl=INTF1, F2=INTF2,
FT=INTFT, FS=INTFS.
278
IlPD7801
INSTRUCTION GROUPS
MNEMONIC OPERANDS
NO.
BYTES
CLOCK
CYCLES
SKIP
CONDITION
OPERATION
a·BIT DATA TRANSFER
MOV
r1.A
1
4
r1 -A
MOV
A.r1
1
4
A-r1
MOV
sr. A
2
10
sr-A
MOV
A.sr1
2
10
A-sr1
MOV
r.word
4
17
r .... (word)
MOV
word. r
4
17
(word)'-r
MVI
r. byte
2
7
MVIW
wa. byte
3
13
(V. wa) .... byte
r-byte
MVIX
rpa1. byte
2
10
(rpa1) - byte
STAW
wa
2
10
(V.wa) .... A
LDAW
wa
2
10
A .... (V.wa)
STAX
rpa
1
7
(rpa)-A
LDAX
rpa
1
7
A .... (rpa)
EXX
1
4
Exchang,e register sets
EX
1
4
V.A ... V.A
BLOCK
1
13 (C+1)
(DE)+ .... 'TL)+. C - C - 1
l6·BIT DATA TRANSFER
SBCD
word
4
20
(word) .... C. (word + 1) - B
SDED
word
4
20
(word) - E. (word + 1) - D
SHLD
word
4
20
(word) - L. (word + 1) - H
SSPD
word
4
20
(word) - SPL. (word + 1)
LBCD
word
4
20
C +- (word). B .... (word + 1)
LDED
word
4
20
E .... (word). D .... (word + 1)
LHLD
word
4
20
L - (word). H .... (word + 1)
LSPD
word
4
20
SPL - (word). SPH
PUSH
rp1
2
17
(SP - 1)
POP
rp1
2
15
rp1 L - (SP)
rp1 H .... (SP + 1). SP - SP + 2
LXI
rp.word
3
10
rp-word
19
C +- (PC + 2 + A)
B +- (PC + 2 + A + 1)
TABLE
1
279
+-
+-
+-
SPH
(word + 1)
rp1 H. (SP - 2) - rp1 L
FLAGS
CY Z
",PD7801
INSTRUCTION GROUPS (CONT.)
MNEMONIC OPERANDS
NO.
BYTES
CLOCK
CYCLES
OPERATION
SKIP
CONDITION
FLAGS
CY Z
ARITHMETIC
ADD
A,r
2
8
A-A+r
~
~
ADD
r,A
2
8
r ..... r+A
~
~
ADDX
rpa
2
11
A - A + (rpa)
~
~
ADC
A,r
2
8
A-A + r + CY
~
t
ADC
r,A
2
8
r - r + A + CY
t
t
ADCX
rpa
2
11
A - A + (rpa) + CY
~
t
SUB
A,r
2
8
A-A-r
t
~
SUB
r,A
2
8
r - r- A
~
t
SUBX
rpa
2
11
A-A- (rpa)
~
t
SBB
A,r
2
8
A ..... A- r- CY
~
t
SBB
r,A
2
8
r ..... r- A- CY
t
~
SBBX
rpa
2
11
A - A - (rpa) - CY
;
t-
ADDNC
A .. r
2
8
A-A+r
No Carry
;
t
ADDNC
r,A
2,
8
r-r+A
No Carry
t
;
ADDNCX
rpa
2
11
A ..... A + (rpa)
No .Carry
t
t
SUBNB
A,r
2
8
A ..... A-r
No Borrow
t
t
SUBNB
r,A
2
8
r-r-A
No Borrow
t
t
SUBNBX
rpa
2
11
A-A- (rpa)
No Borrow
t
t
LOGICAL
ANA
A,r
2
8
A-AAr
t
ANA
r,A
2
8
r-rAA
~
ANA X
rpa
2
11
A .... A A (rpa)
t
ORA
A,r
2
8
A-Avr
t
ORA
r,A
2
8
r-rvA
t
ORAX
rpa
2
11
A- Av(rpa)
t
XAA
A,r
2
8
A-AlJr
t
XAA
r,A
2
8
A-rlJA
t
XAAX
rpa
2
11
A -A ¥ (rpa)
t
GTA
A,r
2
8
No Borrow
A- r-1
280
t
t
IlPD7801
INSTRUCTION GROUPS (CONT.)
MNEMONIC OPERANDS
NO.
BYTES
FLAGS
SKIP
CONDITION
CY
Z
A - (rpa)- 1
No Borrow
t
t
CLOCK
CYCLES
OPERATION
LOGICAL (CONT.)
GTAX
rpa
2
11
LTA
A,r
2
8
A-r
Borrow
t
t
LTA
r,A
2
8
r-A
Borrow
t
t
LTAX
rpa
2
11
A- (rpa)
Borrow
t
t
ONA
A,r
2
8
Al\r
No Zero
t
ONAX
rpa
2
11
A 1\ (rpa)
No Zero
t
OFFA
A,r
2
8
AI\ r
Zero
t
2
11
A 1\ (rpa)
Zero
t
,
OFFAX
rpa
NEA
A,r
2
8
A- r
No Zero
t
t
NEA
r,A
2
8
r- A
No Zero
t
t
NEAX
rpa
2
1'1
A - (rpa)
No Zero
t
t
EOA
A,r
2
8
A- r
Zero
t
t
EOA
r,A
2
8
r- A
Zero
t
t
EOAX
rpa
2
11
A- (rpa)
Zero
t
t
IMMEDIATE DATA TRANSFER (ACCUMULATOR)
t
XRI
A,byte
2
7
A+- A ¥ byte
ADINC
A, byte
2
7
A ..... A + byte
No Carry
t
t
SUINB
A, byte
2
7
A ..... A -byte
No Borrow
t
t
ADI
A,byte
2
7
A ..... A + byte
t
t
ACI
A, byte
2
7
A ..... A + byte + CY
t
t
SUI
A,byte
2
7
A - A - byte
t
t
SBI
A,byte
2
7
A ..... A - byte - CY
t
t
ANI
A, byta
2
7
A ..... AI\ byte
t
ORI
A,byte
2
7
A ..... AVbyte
t
GTI
A,byte
2
7
A - byte - 1
No Borrow
t
t
LTI
A,b\lte
2
7
A - byte
Borrow
t
t
ONI
A, byte
2
7
Al\byte
No Zero
t
OFFI
A,byte
2
7
AI\ byte
Zero
t
NEI
A,byte
2
7
A - byte
No Zero
t
t
EOI
A,byte
2
7
A - byte
Zero
t
t
281
D
",PD7801
INSTRUCTION GROUPS (CONT.)
MNEMONIC
OPERANDS
NO.
BYTES
CLOCK
CYCLES
OPERATION
SKIP
CONDITION
FLAGS
CY
Z
IMMEDIATE DATA TRANSFER
t
XRI
r, byte
3
11
r .... r II- byte
ADINC
r, byte
3
11
r .... r + byte
No Carry
t
t
SUINB
r, byte
3
11
r .... r - byte
No Borrow
t
t
ADI
r.,byte
3
11
r .... r + byte
t
t
ACI
r,byte
3
11
r .... r + byte + CY
t
t
SUI
r, byte
3
11
r .... r - byte
t
t
SBI
r, byte
3
11
r <- r - byte - CY
t
t
ANI
r, byte
3
11
r .... r /\ byte
t
t
ORJ
r. byte
3
11
r +- rv byte
GTI
r, byte
3
11
r - byte - 1
No Borrow
t
t
LTI
r. byte
3
11
r - byte
Borrow
t
t
ONI
r, byte
3
11
r /\ byte
No Zero
t
OFFI
r, byte
3
11
r /\ byte
Zero
t
NEI
r, byte
3
11
r - byte
No Zero
t
t
EQI
r, byte
3
11
r - byte
Zero
t
t
XRI
sr2, byte
3
17
sr2
<-
sr2 II- byte
ADINC
sr2, byte
3
17
sr2
<-
sr2 + byte
No Carry
t
t
SUINB
sr2, byte
3
17
sr2
+--
sr2 - byte
No Borrow
t
t
ADI
sr2, byte
3
17
sr2
+-
sr2 + byte
t
t
ACI
sr2, byte
3
17
sr2
+-
sr2 + byte + CY
t
t
SUI
sr2, byte
3
17
sr2
+-
sr2 - byte
t
t
SBI
sr2, byte
17
sr2 .... sr2 - byte - CY
t
t
ANI
sr2, byte
3
17
sr2
+-
sr2 /\ byte
ORI
sr2, byte
3
17
sr2
+-
sr2 V byte
GTI
sr2, byte
3
14
sr2 - byte -
LTI
sr2, byte
3
14
ONI
sr2, byte
3
14
t
IMMEDIATE DATA TRANSFER (SPECIAL REGISTER)
3
t
t
t
No Borrow
t
t
sr2 - byte
Borrow
t
t
sr2/\ byte
No Zero
I
282
t
IiPD7801
INSTRUCTION GROUPS (CONT.)
MNEMONIC
OPERANDS
NO.
BYTES
CLOCK
CYCLES
OPERATION
SKIP
CONDITION
FLAGS
CY
Z
IMMEDIATE DATA TRANSFER (SPECIAL REGISTERI (CONT.I
OFFI
sr2, byte
3
14
sr21\ byte
Zero
NEI
sr2, byte
3
14
ilr2 - byte
No Zero
t
t
EOI
sr2, byte
3
14
sr2 - byte
Zero
t
t
t
WORKING REGISTER
XRAW
wa
3
14
A +- A lJ. (V, wal
ADDNCW
wa
3
14
A+-A+(V,wal
No Carry
t
t
SUBNBW
wa
3
14
A +- A - (V, wa)
No Borrow
t
t
ADQW
wa
3
14
A -A + (V,wa)
t
t
ADCW
wa
3
14
A .- A + (V, wa) + CY
t
t
SUBW
wa
3
14
A -A - (V,wal
t
t
SBBW
wa
3
14
A-A- (V,wa)- CW
t
t
ANAW
wa
3
14
A - AI\ (V, wal
t
ORAW
wa
3
14
A -Av(V,wal
t
GTAW
wa
3
14
A +- (V, wal - 1
No Borrow
t
t
LTAW
wa
3
14
A-(V,wal
Borrow
t
t
ONAW
wa
3
14
A I\(V, wa)
No Zero
t
OFFAW
wa
3.
14
AI\ (V, wal
Zero
t
NEAW
wa
3
14
A - (V, wa)
No Zero
t
t
EOAW
wa
3
14
A - (V, wal
Zero
t
t
ANIW
wa, byte
3
16
(V, wa) - ·(V, wa) 1\ byte
t
ORIW
wa, byte
3
16
(V, wa) +- (V, wa) Vbyte
t
GTIW
wa, byte
3
13
(V, wa) -
LTIW
wit, byte
3
·13
ONIW
we, byte
3
OFFIW
wa, byte
NEIW
by~e
- 1
t
No Borrow
t
t
(V, wa) - byte
Borrow
t
t
13
(V, well\ byte
No Zero
t
3
13
(V, wall\ byte
Zero
t
we, byte
3
13
(V, we) - byte
No Zero
t
t
EOIW
wa, byte
3·
13
(V, wal- byte
Zero
t
t
INA
r2
1
4
INRW
wa
2
13
INCREMENT IDECREMENT
283
+1
Carry
t
IV, wal +- (V, wa) + 1
Carry
t
r2
~
r2
,iPD7801
INSTRUCTION GROUPS (CONT.)
MNEMONIC
OPERANDS
NO.
BYTES
CLOCK
CYCLES
SKIP
CONDITION
OPERATION
W
CY
Z
INCREMENT/DECREMENT (CONT.)
r2- r2-1
Borrow
t
(V, wa)- (V, wa)- 1
Borrow
t
OCR
r2
1
4
DCRW
wa
2
13
INX
rp
1
7
rp - rp+ 1
DCX
rp
1
7
rp-rp-1
DAA
1
4
Decimal Adjust Accumulator
t
STC
2
8
CY-1
1
CLC
2
8
CY-O
0
ROTATE AND SHIFT
RLD
2
17
Rotate Left Digit
RRD
2
17
Rotate Right Digit
RAL
2
8
Am + 1 - Am, AO"" CY, CY - "'7
t
RCL
2
8
Cm + 1 - Cm, Co - CY, CY - C7
t
RAR
2
8
Am - 1 - Am, A7 -CY,CY - AO
t
RCR
2
8
Cm - 1 - Cm, C7 - CY, CY - Co
t
SHAL
2
8
Am + 1-Am, AO-O,CY - A}
t
SHCL
2
8
Cm + 1 - CM, Co - 0, CY - C7
t
SHAR
2
8
Am-1-Am,A7- 0 ,CY- A O
t
SHCR
2
8
Cm - 1 .... Cm, C7 - 0, CY - CC'
t
3
10
1
4
JUMP
JMP
word
JB
PC -word
PCH - B, PCL-C
JR
word
1
13
PC - PC + 1 + jdisp1
JRE
word
2
13
PC - PC.:!' 2 + jdisp
CALL
word
3
16
(SP - 1) - (PC - 3)H, (SP
(PC - 3)L, PC - word
1
13
CALL
CALB
2)--
(SP - 1)- (PC - 1)H, (SP - 2)'(PC - 1) L , PC.H - B, PCl - C
(SP-1)-(PC-2)H, (SP-2)-(PC-2)L
PC15-11-00001,PC10-0~ fa
CALF
word
2
16
CALT
word
1
19
(SP-1)-(PC-1) H, (SP-2)-(PC-1 ) L
PCL-(128-2ta), PCH-·(129+2ta)
1
19
(SP-1)-PSW,SP- 2, (SP- 3) ·-PC
PC - 0060H, SIRO - 1
SOFTI
284
t
",PD7801
INSTRUCTION GROUPS (CaNT.)
MNEMONIC
OPERANDS
NO.
BYTES
CLOCK
CYCLES
OPERATION
SKIP
CONDITION
RETURN
RET
1
11
PCl ..... (SP), PCH ..... (SP + 1)
Sp ..... SP - 2
RETS
1
11+a
PCl +- (SP), PCH ..... (SP + 1),
Sp ..... SP + 2, PC ..... PC + n
RETI
1
15
2
10
SKC
2
SKNC
PCl ..... (SP), PCH ..... (SP + 1)
PSW+-(SP+2), SP+-SP+3, S IRQ<-{)
SKIP
BIT
bit,we
(V,wa)bit
Bit test
= 1)
8
Skip if Carry
CY
2
8
Skip if No Carry
CY = 0
SKZ
2
8
Skip if Zero
Z
SKNZ
2
8
Skip if No Zero
Z=O
8
Skip if INT X = 1,
then reset INT X
f = 1
8
Skip if No INT X
otherwise reset INT X
f=O
SKIT
SKNIT
f
f
2
2
CPU CONTROL
NaP
1
4
No Operation
EI
2
8
Enable Interrupt
01
2
8
Oisable Interrupt
HlT
1
6
Halt
SERIAL PORT CONTROL
SIO
1
4
STM
1
4
Start (Trigger) Serial I/O
Start Timer
INPUT/OUTPUT
IN
byte
2
10
AB15-8 +- B,AB7-O
A+- OB7-O
+-
byte
OUT
byte
2
10
AB15-8 +- B,AB7-O
OB7-O +- A
+-
byte
PEX
2
11
PE15-8
PEN
2
11
PE15-12
PER
2
11
Port E AB Mode
285
+-
B, PE7-O +- C
+-
B7-4
=1
=1
~
CY Z
,.PD7801
Program Status Word (PSW) Operation
OPERATION
REG,MEMORY
IMMEDIATE
SKIP
06
05
--'t4
--'2a
--'t2
J2O.
Z
SK
HC
L1
LO
CY
t
0
t
0
0
t
t
0
•
0
0
•
t
t
t
0
0
t
ADD
ADC
SUB
SBB
ADDW
ADCW
SUBW
SBBW
ADDX
ADCX
SUBX
SBBX
ADI
ACI
SUI
SBI
ANA
ORA
XRA
ANAW
ORAW
XRAW
ANAX
ORAX
XRAX
ANI
ORI
XRI
ADDNC
SUBNB
GTA
LTA
ADDNCW
SUBNBW
GTAW
LTAW
ADDNCX
SUBNBX
GTAX
LTAX
ADINC
SUINB
GTI
LTI
GTIW
LTIW
ONA
OFFA
ONAW
OFFAW
ONAX
OFFAX
ONI
OFFI
ONIW
OFFIW
t
t
•
0
0
•
NEA
EOA
NEAW
EOAW
NEAX
EOAX
NEI
EOI
NEIW
EOIW
t
t
t
0
0
t
INR
OCR
INRW
DCRW
t
t
t
0
0
•
t
0
t
0
0
t
•
•
•
•
•
•
0
0
0
t
0
0
•
0
0
1
0
0
0
1
0
0
•
•
•
•
•
•
0
1
•
•
•
t
•
0
0
•
•
•
1
•
•
0
0
0
0
0
•
•
ANIW
ORIW
DAA
RAL, RAR, RCL, RCR
SHAL, SHAR, SHCL, SHCR
RLD, RRD
STC
CLC
MVI A, byte
MVI L, byte
LXI H, word
BIT
SKG
SKtJC
SKZ
SKNZ
SKIT
SKtJIT
RETS
All other instructions
o
•
Flag
Flag
Flag
Flag
affected according to result of operation
set
reset
not affected
286
0
0
0
0
IlPD7801
ABSOLUTE MAXIMUM Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -lo°C to +70°C
RATINGS* Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
Voltage On Any Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -O.3V to +7.0V
*COMMENT: Stress above those listed under. "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability .
DC CHARACTERISTICS
~1O°C to +70°C, VCC = +5.0V ± 10%
LIMITS
PARAMETER
SYMBOL MIN
Input Low Voltage
Input High Voltage
Output Low Voltage
MAX
0.8
UNITS
TEST
CONDITIONS
V
VIL
0
VIH1
2.0
VCC
V
Except SCK, X1
VIH2
3.8
VCC
V
SCK, X1
V
IOL = 2.0 mA
0.45
VOL
Output High Voltage
CAPACITANCE
TYP
VOH1
2.4
V
IOH = -100 p.A
VOH2
2.0
V
IOH =-500 p.A
Low Level Input Leakage Current
ILIL
-10
p.A
VIN = OV
High Level Input Leakage Current
ILIH
10
p.A
VIN = VCC
Low Level Output Leakage Current
ILOL
-10
p.A
VOUT = 0.45V
High Level Output Leakage Current
ILOH
10
p.A
VOUT = VCC
VCC Power Supply Current
ICC
110 200
mA
Ta = 25°e, Vee = GND -
ov
LIMITS
PARAMETER
SYMBOL MIN
TYP
MAX
UNITS
Input Capacitance
CI
10
pF
Output Capacitance
Co
20
pF
Input/Output Cap.acitance
CIO
20
pF
287
TEST
CONDITIONS
fc = 1 MHz
All pins not
under test at OV
~PD7801
AC CHARACTERISTICS
CLOCK TIMING
LIMITS
PARAMETER
SYMBOL
MIN
MAX
UNIlS
1000
ns
X1 Input Cycle Time
X1 Input Low Level
Width
tCYX
227
tXXL
106
ns
X1 Input High Level
Width
tXXH
106
ns
¢OUT Cycle Time
tCY¢
454
¢OUT Low Level Width
t¢¢L
150
¢OUT High Level Width
t¢¢H
150
¢OUT Rise/Fall Time
tr.tf
2000
TEST
CONDITIONS
ns
ns
ns
40
ns
READIWRITE OPERATION
LIMITS
PARAMETER
"J!it5' L.E. -+ ¢OUT L.E.
SYMBOL
tR¢
Address (PEO-15) -+ Data
Input
tAD1
'Frn"T.E. -+ Address
tRA
"Rl5" L.E."" Data Input
tRD
"Rl5"T.E. -+ Data Hold
Time
tRDH
MIN
MAX
100
TEST
UNITS CONDITIONS
ns
550 + 500 x N
ns
ns
200(T3); 700(T41
350 + 500 x N
IlS
ns
0
ns
'Frn" Low Level Width
tRR
R15' L.E. -+ wATT L.E.
tRWT
450
Address (PEO-151 -+
WAIT L.E.
tAWT1
650
WAIT Set Up Time
(Referenced from
DEPENDENT AC PARAMETERS
PARAMETER
,EQUATION.
~
MIN/MA)~
UNIT
MIN
ns
AC·CHARACTERISTICS
(CONT.)
"
tR¢
Notes:
(1/5) T
tAD1
(3/2 + N) T- 200
MAX
ns
tRA (T3)
(1/2) T - 50
MIN
ns
tRA (T4)
(3/2) T - 50
MIN
ns
tRD
(1 + N) T - 150
MAX
ns
tRR
(2 + N) T - 150
MIN
ns
tRWT
(3/2) T - 300
MAX
ns
tAWTl
(2) T- 350
MAX
ns
tMR
(1/2) T- 50
MIN
ns
tRM
(1/2) T - 50
MIN
ns
tlR
(1/2) T- 50
MIN
ns
tRI
(1/2) T - 50
MIN
ns
t¢w
(1/4) T
MAX
ns
tA¢
(1/5) T
MIN
ns
ns
...
tAD2
T- 50
MIN
tow
(3/2+N)T- 150
MIN
ns
two
(1/2)T-l00
MIN
ns
tAW
T- 100
MIN
ns
tWA
(1/2) T - 50
MIN
ns
tww
(3/2+N)T-150
MIN
ns
tlW
T
MIN
ns
tWI
(1/2) T
MIN
ns
tHABE
(1/2) T - 150
MAX
ns
OUT Cycle Time
tCYct>
454
ct>OUT Low Level Width
tct>ct>L
150
ns
ct>oUT High Level Width
tct>ct>H
tr,tf
150
ns
ct>OUT Rise/Fall Time
2000
40
TEST
CONDITIONS
ns
ns
REAOIWRITE OPERATION
LIMITS
PARAMETER
SYMBOL
"R[) L.E. -+ ct>OUT L.E.
tRct>
Address (PEO-1SI ..... Data
Input
tAD1
FfDT.E. -+ Address
tRA
lUlL.E. -+ Data Input
tRD
"FfIrT:E.
Time
tROH
-+
Data Hold
MIN
MAX
100
TEST
'UNITS CONDITIONS
ns
550 + 500 x N
200(T31; 700(T41
ns
ns
350 + 500 x N
ns
ns
0
lrn" Low Level Width
tRR
R!)"" L.E.
tRWT
450
ns
Address (PEO-1S1 -+
WAIT L.E.
tAWT1
650
ns
WAIT Set Up Time
(Referenced from
ct>OUT L.E.I
WAIT Hold Time
(Referenced from
ct>OUT L.E.I
M1 ..... 'RlJ L.E.
tWTS
290
ns
tWTH
0
ns
tMR
200
ns
"R15 T.E. -+ M1
tRM
200
ns
IO/Kif -+"RU L.E.
tlR
200
ns
"RU T.E. -+ 101M
ct>OUT L.E. -+ WR L.E.
tRI
tct>W
200
Address (PEO-151 .....
ct>OUTT.E.
Address (PEO-1SI-+
Data Output
tAct>
100
tA02
450
ns
Data Output .....'"WFf
T.E.
tow
600+S00xN
ns
WR T.E ...... Data
two
150
ns
Address (PEO-1SI-+
WR"L.E.
tAW
400
ns
WR T.E. -+ Address
tWA
200
ns
WR Low Level Width
tww
600 + 600 x N
nl
IO/M-+WR L.E.
tlW
500
ns
WRT.E ...... IO/M
tWI
260
nl
-+
WAIT L.E.
850 + 500 x N
40
ns
ns
125
300
ns
ns
Stabilization Time
Stabilization Tima
314
tCY¢ = 500 ns
IiPD7802
SERIAL I/O OPERATION
PARAMETER
SYMBOL
MIN
MAX
UNIT
CONDITION
ns
ns
SCKlnput
SCK Output
SCK Cycle Time
tCYK
SOO
900 4000
SCK Low Level Width
tKKL
350
400
ns
ns
SCK Input
SCK Output
SCK High Level Width
tKKH
350
400
ns
ns·
SCK Input
SCK Output,
SI Set-Up Time (referenced from SCK T.E.)
tSIS
140
ns
SI Hold Time (referenced from SCK T.E.I
tSIH
260
SCi< L.E. -+ SO Delay Time
tKO
ns
1S0
~High -+ SCK L.E.
tCSK
100
SCK T.E. -+ SCS Low
tKCS
100
SCK T.E. -+ SAK Low
tKSA
ns
ns
ns
ns
260
HOLD OPERATION
PARAMETER
SYMBOL
HOLD Set-Up Time (referenced from
~OUT L.E.)
HOLD Hold Time (referenced from l'JOUT
L.E.I
MIN
tHDS1
tHDS2
200
200
tHDH
0
~OUT L.E. -+ HLDA
tDHA
110
HLDA High -+ Bus Floating (High Z State)
tHABF
-160.
H LOA Low -+ Bus Eneble
tHABE
MAX
UNIT
CONDITION
ns
ns
ns
100
tCY/f> '" 500 ns
ns
160
ns
350
ns
Notes:
-
O.S
MEAsURING
POINTS
<:::::::
2.0
O.S
X
_ _ __
@
Output Timing is measured with 1 TTL + 200 pF measuring points are VOH - 2.0V
@
L.E.· Leading Edge, T.E ... Trailing Edge
VOL -O.SV
315
IiPD7802
tCYrp DEPENDENT AC PARAMETERS
PARAMETER
tRrp
Notes:
EQUATION
MINIMAX
UNIT
MIN
ns
(1/5) T
tADl
(312 + N) T - 200
MAX
ns
tRA (T3)
(1/2) T - 50
MIN
ns
tRA (T4)
(3/2) T - 50
MIN
ns
tRD
(1 +N)T- 150
MAX
ns
tRR
(2+N)T-150
MIN
ns
tRWT
(3/2) T - 300
MAX
ns
tAWTl
(2) T- 350
MAX
ns
tMR
(1/2) T - 50
MIN
ns
tRM
(1/2) T - 50
MIN
ns
tlR
(1/2) T - 50
MIN
ns
tRI
(1/2) T- 50
MIN
ns
trpW
(1/4) T
MAX
ns
tM>
(1/5) T
MIN
ns
tAD2
T- 50
MIN
ns
tow
(312 + N) T - 150
MIN
ns
ns
two
(1/2) T - 100
MIN
tAW
T- 100
MIN
ns
tWA
(1/2) T - 50
MIN
ns
tww
(312 + N) T ~ 150
tlW
T
MIN
ns
:
MIN
ns
tWI
(1/2) T
MIN
ns
tHABE
(1/2) T - 15q
MAX
ns
AC CHARACTERISTICS
(CONT.)
CD N = Number of Wait States
@ T=tCYtP
@ Only above parameters are tCYtP dependent
@ When a crystal frequency other than 4 MHz is used (tCYtP = sOt) nsl
the above equations can be used to calculate AC parameter
values.
CLOCK TIMING
TIMING WAVEFORMS
316
",PD7802
TIMING WAVEFORMS
(CONT.)
~------------ tCY~--------------~~
<;lOUT
READ OPERATION
OoUT
tRWT ----+:!~~~
i-----I-----tAwTI
IO/fZ'
-ACTive ONLY WHEN 10m IS ENABLED.
WRITE OPERATION
OoUT
PEO.l.
--"'"\J--t-------j-----:----j--------------------------.,,--
tWTS
-ACTIVE ONLY WHEN IOIU IS ENABL6D.
317
IlPD7802
SERIAL I/O OPERATION
leVK
SI-+---C~Hso
=::t===::=:)--t----c::::::::=
SCs _ _ _ _ _ _ _ _ _ _ _-....J
SAK _ _ _ _ __IKSA
HOLD OPERATIOhl
---MACHIN6CVCLl----!
318
t
IlPD7802
PACKAGE INFORMATION
/LPD7802G-XXX
XXX denotes mask number
assigned by factory at time of
code verification.
Use. I.C. Socket NP32-64075G4.
·
I
rr
(Unlt:mm)
--19.0s-1
1-0-1.
I. I.
24.13---n
18.0 - 20.1
23.1 - 2S.2
'Mj
.1
I- 0.2S±g:J~
I
7802DS-Rev 1-12-81-CAT
319
NOTES
320
:NEC
I-lPD78C06
CMOS HIGH END
8·BIT SINGLE CHIP
MICROCOMPUTER
NEe Electronics U.S.A. Inc.
Microcomputer Division
De.crlptlon
The NEe ",PD78C06 is an advanced CMOS 8-bit
general purpose single chip microcomputer intended for
applications requiring 8-bit microprocessor control and
extremely low power consumption; ideally suited for
portable, battery-powered/backed-up products. A subset
of the ",PD7801, the ",PD78C06 integrates an 8-bit ALU,
4K ROM, 128 bytes RAM, 46 1/0 lines, an 8-bit timer,
and a serial 1/0 port on a single die. Fully compatible
with the 8080A bus structure, expanded system operation can easily be implemented using industry standard
peripheral and memory components. Total memory
space can be increased to 64K bytes.
The ",PD78C06 lends itself well to low power, portable
applications by featuring two power down modes to further conserve power when the processor is not active.
The ",PD78C06 is packaged in a 64-pin flat pack. The
",PD78C05 is a ROM-less, version packaged in a 64-pin
QUIL, designed for prototype development and small
volume production.
Feature.
D CMOS Silicon Gate Technology + 5V supply
D Complete Single Chip Microcomputer
- 8-bit ALU
- 4K ROM
- 256 Bytes RAM
D Low Power Consumption
D 46 1/0 Lines
D Expansion Capabilities
- 8080A Bus Compatible
- 60K Bytes External Memory Address Range
D Serial 1/0 Port
'
D 101 Instruction Set
- Multiple Address Modes
D Power Down Modes
- Halt Mode
- Stop Mode
D 8-Bit Timer
D Prioritized Interrupt Structure
- 2 External
- 1 Internal
D On Chip Clock Generator
D 64-Pin Flat Pack
Pin Configuration
",PD78C06
Pin Identification
110 Porta
OataBua
,
Wilt Requelt
Interrupt Requ8lt
Xtel
SCK
81
so
RESET
RO
321
Serial Clock Input/Output
8erlallnput '
Serial Output
Raset
Raad8trobe
WR
Write Strobe
fout
Clock Output
IJ
",PD78C06
Block Diagram
osc
16
Latch
INC/DEC
PC
SP
REL
Data
Memory
(I 26-Byte)
A
B
Program
Memory
(4K-Byte)
c
o
INT1
H
TO
SI
pCs-o
Table 4-1
PB7-o
PA7-0
AD
WR
Reset
Walt
~Out
1 1
vcc
VSS
HALT Mode and STOP Mode
Function
Oscillator
Internal System Clock
Timer
TIMER REG
UPCOUNTER, PRESCALER 0, 1
Serial Interface
Serial Clock
Interrupt Control Circuit
Interrupt Enable Flag
INTO, INT 1 Input
INTT
TS (INTFS)
MASK Register
Pending Interrupts (INTFX)
REL Input
RESET Input
Halt Mode
Stop Mode
Run
Stop
Run
Hold
Stop
Run
Hold
Run
Hold
Function
Set
Cleared
RunG)
Hold
Stop
Reset
Inactive
Active
Hold
Set
Reset
Inactive
Active
Active
Halt Mode
On-Chip RAM
Output Latch in Port A, B, E
Program Counter (PC)
Slack Pointer (SP)
General Registers
(1\, B, C, 0, E, F, L)
Program Status Word (PSW)
Mode B-Register
Standby Control Register (SCO-SC3)
Standby Control Register (SC4)
Timer Mode Register (TMMO_1)
Tin:ler Mode Register (TMM1)
Serial Mode Register (SM)
Hold
Data Bus (DBO-7)
RD, WR Output
High-Z
High
Stop Mode
Hold
Cleared
Unknown
Reset
Hold
Set
Hold
Set
Hold
High-Z
High
Nlote:
(1) Serial clock counter is running and TS is generated; however,
there are no effects by it_
322
IlPD78C08
Package DImension
84-Pln Flat
(Unit: mm)
p.PD78C08G-XXX-11
p.PD78C08G-XXX-12
XXX denotes mask number
assigned by factory at time of
code verification.
Usa. I.C. Socket IC-51-598.
I
7
24.
± 0.4
'I
f
~~
D
0.15+0.10
-0.05
2.36 ±0.2
1.2 ± 0.2
78C08DS-1-82-TRIUM-CAT
323
NOTES
324
NEe
J.lPD7811G
HIGH END SINGLE, CHIP'
8·BIT MICROCOMPUTER
WITH AID CONVERTER
NEe Electronics U.S.A. Inc.
Microcomputer Division
Description
The NEC JAPD7811 G is a high performance single chip
microcomputer integrating sophisticated on-chip peripheral functionality normally provided by external components. The device's internal 16-bit ALU and data paths,
combined with a powerful instruction set and addressing, make the JAPD7811G appropriate in data processing as well as control applications. The device integrates a 16-bit ALU, 4K ROM, 256 Bytes RAM with an
8-channel AID converter, a multifunction 16-bit timerl
event counter, two 8-bit timers, a USART and two zerocross detect inputs on a single die, to direct the device
into fast, high~end processing applications involving
analog signal interface and processing.
The JAPD7811G is the mask-ROM high volume production device embedded with custom customer program.
The JAPD7810G is a ROM-less version for prototyping
and small volume production. The JAPD78PG11 E is a
piggy-back EPROM version for design development.
Pin Configuration
PM
PAt
PA2
PA3
PM
PAS'
PA6
PA7
PBO
PBt
PB2
PB3
PB4
PBS
PB6
PB7
PCO
PCt
PC2
PC3
PC4
PCS
PC6
PC7
INTO
INTt
MI
RESET
MD
X2
XI
VSS
lFeatures
D NMOS Silicon Gate Technology Requiring + 5V
Supply
D Complete Single Chip Microcomputer
- 16-Bit ALU
- 4K ROM'
- 256 Bytes RAM
D 441/0 lines
D Two Zero-Cross Detect Inputs
D Expansion Capabilities
- 8085A Bus Compatible
- 60K Bytes External Memory Address Range
D 8-Channel, 8-Bit AID Converter
- Auto Scan
- Channel Select
D Full Duplex USART
- Synchronous and Asynchronous
D 153 Instruction Set
- 16-Bit Arithmetic, Multiply and Divide
D 1 /As Instruction Cycle Time
D Prioritized Interrupt Structure
- 2 External
- 4 Internal
D Standby Function
D On-Chip Clock Generator
D 64-Quil Package
~PD78ttG
VCC
VDD
PD7
PD6
PD5
PD4
PD3
PD2
POt
PDO
PF7
PF6
PF5
PF4
PF3
PF2
PFt
PFO
ALE
WR
R5
AVCC
VR
AN7
AN6
AN5
AN4
AN3
AN2
ANt
ANO
.--..:.._ _ _ _......;;.;;..r-~AVSS
Instruction Set
In addition to the existing instruction set for JAPD7801,
the following new instructions are incorporated in the
/APD7811.
16-Bit Data Transfer
16-Bit Data Transfer Memory and Extended
Accumulator
16-Bit pata Arithmefic and Logical Operation
16-Bit Addition and SubtraCtion
16-Bit Comparison
16-Bit And, Or, Ex-or Operation
16-B'it' Data Shift and Rotation'
Multiply
8-Bit by 8-Bit
Less than 8 /AS Execution
Divide
16-Bit Divided by 8-Bit
Less than 14 /As Execution
Index Operation
Register Pair HL and DE are used as Index
Reg'ister
325
7
",PD7811G
Block Diagram
f
16
LATCH
INCIOEC
12
PC11RxO
PC21SCK
PB7-Y
/~.Bll
CONTROL
LINE
NMI
INTl
PC31TIIINT2
PC4ITO
P07-Y
h07-O
PC51Cl
PC81COO ....--.............
PC71COl "'--"1-.~~.!.5!lJ 'r-rVI
PF7-Y
AN7-0
8
~B15-8
VAREF
AVCC
AVSS ...,--l...-_ _---J
Voo
Input/Output
8 Analog Input Lines
44 Digital I/O Lines - Five 8-Bit ports (Port A, Port B,
Port C, P6rt D, Port F) and 4.lnput Lines (AN4-7)
1. Analog Input Lines
ANO-7 are configured as analog input lines for .on
chip A/D converter.
2. Port Operation
- Port A, Port B, Port C, Port F
Each line of these ports can be individually programmed as an input or as an output.
- Port D
Port D can be programmed as a byte input or a
byte output.
- AN4-7
In addition to the analog input lines, AN4-7 can
be used as digital input lines for falling edge
detection.
3. Control Lines
Under software control, each line of Port C can be
configured individually to provide control lines for
serial interface, Timer and Timer/Counter.
4. Memory Expansion
In addition to the single-chip operation mode
IAPD7811 has 4 memory expansion modes. Under
software control, Port D can provide multiplexed
low-order address and data bus and Port F can
provide high-order address bus. The relation
between memory expansion modes and the pin
configurations of Port D and Port F is shown in
the table that follows.
11
Vcc
.t.mory Expansion
Non
256 Bytes
4K ByteB
16K Bytes
60K Bytes
vss
Port Configuration
Port
Port
Port
Port
Port
Port
Port
Port
Port
Port
Port
Port
0 F0 F0 -
I/O Port
I/O Port
Multiplexed Address/Data
I/O Port
Multiplexed Addre~s/Oata
FO-3 - Address Bus
F4-7 - I/O Port
0 - Multiplexed Address/Data
FO-5 - Address Bus
F6, 7 - I/O Port
0 - Multiplexed Address/Data
F - Address Bus
8·Blt AID Converter
8 Input Channels
4 Conversion Result Registers
2 Powerful Operation Modes
Auto Scan Mode
Channel Select Mode
Successive Approximation Technique
Absolute Accuracy
± 1.5 LSB (± 0.6%)
Conversion Range
0 rv 5V
Conversion Time
50 JAs
Interrupt Generation
326
Bus
Bus
Bus
Bus
JJPD7811G
Interrupt Structure
11 Interrupt Sources
6 Priority Levels
Non-maskable Interrupt Capability - NMI
Individual Request Mask Capability - Except NMI
AID Converter Block .P1.gram
AVCCO-----------------------~
AVSS 0------------------.
VAREF 0-------'-------------.
ANO_
AN1 0------AN2 0------AN3AN4 0-----_-1
AN5 o--~H--I
AN6 o--....-l~+-I
AN7 o-........+-I~-I
Universal Serial Interface
Full-Duplex, Double Buffering
Synchronous Operation Mode
Search Mode
Receive Mode
Asynchronous Operation Mode
7, 8-Bits/Character
Start/Stop Bit
Even/Odd Parity
Programmable Clock Rate x1, x16, x64
I/O Expansion Mode (J.tPD7801 Serial Mode)
Programmable Communication Rate
2 /-lS, 32 /-lS, Timer 1 and External
Interrupt Generation
INTERNAL BUS
PC1/RxO
r
4
IRQ1
8
IRQ2
16
IRQ3
24
IRQ4
32
IRQS
40
iN'F'I
lim'
INTEO
INTEl
INTEIN
INTAO
INTSR
INTST
ov
ER
SB
AN7-AN4
___.
0---{>-
"'''''''Ko----i
Interrupt
IRQO
NMI
INTTO
INTTl
Universal Serial Interface Block Diagram
t=,-----::~--_
Interrupt
Request
'""RNA' CeoCK
SK2.SKl
PCO/TX0o---<}-----------------------------J
327
Type of Interrupt
InlExt
NMi (Non-maskable interrupt)
External
INTTO (CoinCidence signal from timer 0) Internal
INTT1 (Coincidence signal from timer 1)
INn (Maskable Interrupt)
INT2 (Maskable Interrupt)
INTEO (Coincidence Signal from tlmerl
event counter)
INTE1 (CoinCidence signal from tlmerl
event counter)
INTEIN (Failing signal of C1 and TO
counter)
INTAD (AID converter interrupt)
INTSR (Serial receive Interrupt)
INST (Serial send Interrupt)
External
Internal
InlExternal
Internal
/JPD7811G
Package Information
p,PD7811G·XXX
XXX denotes mask number
assigned by factory at time of
code verification.
Use I.C. Socket NP32-64075G4.
'I!
;
(Unit: mm)
I'
I'
rr
I.
I,
19.05~
24.13
"I
.~
18.0-20.1
23.1-25.2
.lj~0.25±g:~
I
7811 GDS·1 ·82·TRIUM·CAT
328
NEe
,.PD8021
NEe Electronics U.S.A. Inc.
Microcomputer Division
SINGLE' C'H'fP 8·BIT
MICROCOMPUTe,R
DESCRIPTION
FEATURES
The NECpPD8021 is a stand alone 8-bit parallel microcomputer incorporating the
following features usually found in external peripherals. The pPD8021 contains:
1K x 8 bits of mask ROM program memory, 64 x 8 bits of RAM data memory, 21
I/O lines, an 8-bit inter~al timer/event counter, and internal clock circuitry.
• 8-Bit Processor, ROM, RAM, I/O, Timer/Counter
•
•
•
•
•
•
•
'.
•
•
PIN CONFIGURATION
Single +5V Supply (+4.5V to +6.5V)
NMOS Silicon Gate Technology
8.38 ps Instruction Cycle Time
All Instructions 1 or 2 Cycles
Instructions are Subset of pPD8048/8748/8035
High Current Drive Capability - 2 I/O Pins
Clock Generation Using Crystal or Single Inductor
Zero-Cross Detection Capability
Expandable I/O Using p8243's
Available in 28-Pin Plastic Package
vee
P22
P23
PROG
P21
P20
Poo
P17
P16
P01
P15
P14
P02
P03
P04
P13
P12
P11
P07
P10
RESET
ALE
T1
XTAL2
Vss
XTAL1
Rev/2
329
",PD8021
BLOCK DIAGRAM
Operating Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. O°C to +70°C
Storage Temperature (Ceramic Package) . . . . . . . . . . . . . . . . . . . -65°C to +150°C
(Plastic Package). . . . . . .
. ...... -65°C to +150°C
Voltage on Any Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to +7 Volts VIN
;;;. V5S + 0.45V
Vee Supply Current
ICC
100
rnA
50
336
IlPD8022
PIN IDENTIFICATION
PIN
NO.
FUNCTION
SYMBOL
8
TO
Active low interrupt input if enabled. Also testable using the
conditional jump instructions JTO and JNTO.
19
Tl
Zero-cross detector input. After executing a STRT CNT instruction this becomes the event counter input. Also testable using
the conditional jump ins~ructions JT1 and JNT1. Optional ROM
mask pull-up resistor available.
6
ANa
Analog input to the AID converter after execution of the SE L
ANa instruction.
5
AN1
Analog input to the AID converter after execution of the SEL
AN 1 instruction.
22
XTALl
Input for internal oscillator connected to one side of a crystal or
inductor. Serves as an external frequency input also (Non-TTL
compatible V IH ).
23
XTAL 2
Input for internal oscillator connected to the other side of a
crystal or inductor. This pin is not used when employing an
external frequency source.
37
PROG
Strobe output fo; the pPD8243 liD expander.
18
ALE
Active high address latch enable output occurring once every
instruction cycle. Can be used as an output clock.
24
RESET
Active high input that initializes the processor to a defined
state and starts the program at memory location zero.
40
VCC
+5V power supply.
AVCC
+5V AID converter power supply.
VSS
Power supply ground potential.
AVSS
AID converter power supply ground potential. Sets conversion
3
20
7
range lower limit.
4
VA REF
Reference voltage for AID converter. Sets conversion range
upper limit.
V TH
Port a comparator threshold reference input.
21
SUBST
(NC)
Substrate connection used with bypass capacitor to V SS for substrate voltage stabilization and improvement of AID accuracy.
10-17
P -P
OO 07
Port O. 8-bit open drain liD port with comparator inputs. The
reference threshold is set via V TH . Optional ROM mask pull-up
resistors available.
9
25-32
P
1-2
33-36
38-39
P -P
2O 27
lO
-P
17
Port 1. 8-bit quasi-bidirectional port. TTL compatible.
Port 2. 8-bit quasi-bidirectional port. TTL compatible. P2O -P 23
also function as an I/O expander port for the pPD8243.
337
IlPD8022
AC CHARACTER ISTICS
Ta = O°C to 70°C. VCC = 5.5V ± 1V. VSS = OV
LIMITS
PARAMETER
SYMBOL
UNIT
MIN
TYP
MAX
TEST
CONDITIONS
Cycle Time
tCY
8.38
Zero-Cross Detection
Input (T1)
VT1
1
Zero-Cross Accuracy
AZX
Zero-Cross Detection
Input Frequency (T1)
FZX
0.05
Port Control Setup
Before Falling Edge of
PROG
tcP
0.5
IlS
tCY = 8.38 /J.s.
CL = 80 pF
Port Control Hold
After Falling Edge of
PROG
tpc
0.8
/J.S
tCY = 8.38 /J.s.
CL = 80 pF
PROG to Time P2 Input
Must be Valid
tpR
/J.s
tCY = 8.38 /J.s.
CL = 80 pF
Output Data Setup Time
tpp
7.0
/J.s
tCY = 8.38 /J.s.
CL = 80 pF
Output Data Hold Time
tpD
8.3
/J.s
tCY = 8.38 /J.s.
CL = 80 pF
Input Data Hold Time
tPF
0
ns
tCY = 8.38 /J.S.
CL = 80 pF
PROG Pulse Width
tpp
8.3
/J.s
tCY = 8.38 /J.s.
CL = 80 pF
ALE to Time P2 Input
Must be Valid
tPRL
/J.s
tCY = 8.38 /J.s.
CL = 80 pF
Output Data Setup Time
tpL
0.8
/J.s
tCY = 8.38 /J.s.
CL=80pF
Output Data Hold Time
tLP
1.6
/J.s
tCY = 8.38 /J.S.
CL = 80 pF
Input Data Hold Time
tpFL
0
/J.S
tCY - 8.38 /J.S.
CL = 80 pF
ALE Pulse Width
tLL
3.9
/J.s
tCY = 8.3a/J.s
for min.
50.0
IlS
3
VAC pp
±135
mV
1
kHz
1.0
150
3.6
23.0
3.58 MHz XTAL
for tCY min.
AC coupled
60 Hz Sine Wave
TIMING WAVEFORM
PORT 2 TIMING
ALE
EXPANDER
PORT
OUTPUT
EXPANDER
PORT
INPUT
PROG
338
IlPD8022
AID CONVERTER
CHARACTER ISTICS
Ta = o°c to 70°C, VCC = 5.5V
AVccl 2 "'; VAREF"'; AVCC
PARAMETER
±
1V, VSS = OV, AVCC = 5.5V
SYMBOL
Resolution
Absolute Accuracy
±
1V, AVSS = OV
LIMITS
MIN
TYP
MAX
8
(i)
UNITS
TEST
CONDITIONS
BITS
LSB
Sample Setup Before
Falling Edge of ALE
tss
0.20
tCY
CD
Sample Hold After
Falling Edge of ALE
tSH
0.10
tCY
ill
Input Capacitance
(ANO,AN1)
CAD
1
pF
Conversion Time
tCNV
4
Conversion Range
AVSS
Reference Voltage
Note:
VAREF
AVCC/2
4
YAREF
AVCC
tCY
V
V
ill
The analog signal on ANO and AN1 must remain constant during the sample time
tss + tSH"
@
.8% FSR ± 1/2 LSB
ANALOG INPUT
TIMING WAVEFORM
ANI~:;;./___ ~
tss __
339
l_-t_SH===I_
flPD8022
INSTRUCTION SET
The instruction set of the tlPD8022 is a subset of the tlPD8048 instruction set except
for three instructions, SE L ANO, SE LAN 1, and RAD, which are uniQue to the
IlPD8022. The tlPD8022 instruction set is also a superset of the tlPD8021, meaning
that the tlPD8022 will execute ALL of the tlPD8021 instructions PLUS some
additional instructions which are listed below. For a summary of the I.LPD8021 instruc·
tion set, please refer to that section. Symbols used below are defined in the same manner as in that section. Also note that the instructions listed below do not affect any
status flags.
INSTRUCTION CODE
FUNCTION
DESCRIPTION
07
06
05
04
03
02
0,
DO
CYCLES
BYTES
(PCO-7) ..... addr if
TO = 1
(PC) ..... (PC) + 2
if TO = 0
Jump to specified address if
TO is high
0
0
1
1
0
1
1
0
2
2
a7
a6
a5
a4
a3
a2
a1
ao
(PCO-7) ..... addr if
TO = 0
(PC) ..... (PC) + 2
if TO = 1
Jump to specifi~d address if
TO is low
0
0
1
0
0
1
1
0
2
2
a5
a4
a3
a2
a1
ao
(A)
Move to A the contents of
the AID conversion result
register (CRR)
1
0
0
0
0
0
0
0
2
1
SEL ANO
Select ANO as the input
for the AID converter
1
0
0
0
0
1
0
1
1
1
SEL AN1
Select AN 1 as the input
for the AID converter
1 10
0
1
0
1
0
1
1
1
EN I
Enable the external
interrupt input TO
0
0
0
0
0
1
0
1
1
1
DIS I
Disable the external
interrupt input TO
0
0
0
1
0
1
0
1
1
1
EN TCNTI
Enable internal timerl
counter interrupt
0
0
1
0
0
1
0
1
1
1
DIS TCNTI
Disable internal timerl
counter interrupt
0
0
1
1
0
1
0
1
1
1
Return from interrupt and
re-enable interrupt input
loglc
1
0
0
1
0
0
1
1
2
1
MNEMONIC
JTO addr
JNTO addr
RAD
RETI
<--
(CRR)
(SP) ..... (SP) - 1
{PC) ..... ({SP))
a7
! a6
PACKAGE OUTLINE
J,lPD8022C
ITEM
MILLIr~nEAS
51.5 MAX
1.62
2.S4! 0.1
0.5! 0.1
48.26
1.2MIN
2.S4 MIN
O.SMIN
5.22 MAX
5.72 MAX
15.24
13.2
-+ 0,1
M
0.25 _ 0.05'
340
INCHES
2.028 MAX
0.064
0.10! 0.004
0.019! 0.004
1.9
0.047 MIN
0.10MIN
0.019 MIN
0.206 MAX
0.225 MAX
0.600
0.520
-+
0.004
0.010 _ 0.002
8022DS-Rev 1-12-81-CAT
NEe
",PD8041A
",PD8741A
NEe Electronics U.S.A. Inc.
Microcomputer Division
UNWERSALPROGRAMMABLEPER~HERAL
INTERFACE DESCRIPTION
FEATU R ES
8·BIT MICROCOMPUTER
The J,.tPD8041A/8741A is a programmable peripheral interface intended for use
in a wide range of microprocessor systems. Functioning as a totail y self-sufficient
controller, the J,.tPD8041A/8741A contains an 8-bit CPU, 1 K x 8 program
memory, 64 x 8 data memory, I/O lines, counter/timer, and clock generator in a
40-pin DIP. The bus structure, data registers, and status register enable easy interface
to 8048, 8080A or 8085A based systems. The J,.tPD8041 A's program memory is factory mask programmed, while the J,.tPD8741 A's program memory is UV EPROM to
enable user flexibility.
• Fully Compatible with 8048, 8080A, 8085A and 8086 Bus Structure
•
8-Bit CPU with 1K x 8 ROM, 64 x 8 RAM, 8-Bit Timer/Counter,
18 I/O Lines
• 8-Bit Status and Two Data Registers for Asynchronous Siave-to-Master
Interface
• I nterchangeable EPROM and ROM "ersions
• Interrupt, DMA or Polled Operation
• Expandable I/O
• 40-Pin Plasticor Ceramic Dip
• Single +5V Supply
PIN CONFIGURATION
vcc
TO
Xl
X2
RESET
55
CS
EA
RD
AO
WR
SYNC
, DO
Dl
D2
D3
D4
D5
J,.tPD
8041A/
8741A
06
D7
VSS
Rev/2
341
Tl
P27/ DACK
P26/ DRQ
P25/i'B'F
P24/0BF
P17
P16
P15
P14
P13
P12
P11
P10
VDD
PROG
P23
P22
P21
P20
JiPD8041 A18741 A
PIN IDENTIFICATION,
PIN
NO.
SYMBOL
FUNCTION
1,39
TO,T1
Testable input pins using conditional transfer functions
JTO, JNTO, JT1, JNT1. Tl can be made the counter/timer
input using the STRT CNT instruction. The PROM programming and verification on the J,lPD8741A uses TO.
2
Xl
One side of the crystal input for external oscillator or
frequency source.
3
X2
The other side of the crystal input.
4
~
Active-low input for processor initialization. FfESET is also
used for PROM programming-, verification, andJ)ower down.
5
SS
Single Step input (active-low). SS together with SYNC output allows the J,lPD8741A to "single-step" through each
instruction in program memory.
6
CS
Chip Select input (active-low). CS is used to select the
appropriate J,lPD8041A/8741A on a common data bus.
7
EA
'External Access input (active-high). A logic "1" at this input
commands the J,lPD8041A/8741A to perform all program
memory fetches from external memory.
8
RD
Read strobe input (active-low). RD will pulse low when the
master processor reads data and status word, from the DATA
BUS BU F FER or Status Register.
9
AO
Address input which the master processor u:;es to indicate if
a byte transfer is a command or data.
10
WR
Write strobe input (active-low). WR will pul:;e low when the
master processor writes data or status words to the DATA
BUS BUFFER or Status Register.
11
SYNC
The SYNC output pulses once for each J,lPD8041 A/8741 A
instruction cycle. It can function as a strobe for external
circuitry. SYNC can also be used together with SS to
"single-step" through each instruction in program memory.
12-19 DO-D7 BUS
The 8-bit, bi-directional, tri-state DATA BUS BUFFER lines
by which the J,lPD8041 A/8741 A interfaces 'W the 8-bit
master system data bus,
20
Processor's ground potential.
VSS
21-24, P20- P27
35-38
PORT 2 is the second of two 8-bit, quasi-bi-directional I/O
ports. P20-P23 contain the four most significant bits of the
program counter during external memory f€tches. P20-P23
also serve as a 4-bit I/O bus for the J,lPD824:3, INPUT /
OUTPUT EXPANDER. P24-P27 can be used as port lines or
can provide Interrupt Request (IBF and OBF) and DMA
handshake lines (DRG and DACK).
25
PROG
Program Pulse. PROG is used in programmirlg the J,lPD8741A.
It is also used as an output strobe for the uPD8243.
26
VDD
VDD is the programming supply voltage for programming
the J,lPD8741A. It is +5V for normal operation of the
J,lPD8041A/8741A. VDD is also the Low Power Standby
input for the ROM version.
27-34 PlO- P17
PORT 1 is the first of two 8-bit quasi-bi-directional I/O ports.
40
Primary power supply. VCC must be +5V for programming
and operation of the J,lPD8741 A and for tho operation of the
J,lPD8041A.
VCC
342
flPD8041 AJ8741 A
FUNCTIONAL
DESCRIPTION
The pPD8041 A/8741 A is a programmable peripheral controller intended for use
in master/slave configurations with 8048, 8080A, 8085A, 8086 - as well as most
other 8-bit and 16-bit microprocessors. The pPD8041A/8741 A functions as a
totally self-sufficient controller with its own program and data memory to effectively
unburden the master CPU from I/O handling and peripheral control functions. The
pPD8041A/8741A is an intelligent peripheral device which connects directly to the
master processor bus to perform control tasks which off load main system processing
and more efficiently distribute processing functions.
JlPD8041 A/8741 A
FUNCTIONAL
ENHANCEMENTS
The pPD8041 A/8741 A features several functional enhancements to the earl ier
pPD8041 part. These enhancements enable easier master/slave interface and increased
functionality.
1. Two Data Bus Buffers. Separate Input and Output data bus buffers have been
provided to enable smoother data flow to and from master processors.
INPUT DATA
BUS BUFFER
(8)
INTERNAL
DATA BUS
OUTPUT DATA
BUS BUFFER
(8)
2. 8-Bit Status Register. Four user-definable status bits, ST4-ST7, have been
added to the status register. ST 4-ST7 bits are defined with the MOV STS, A
instruction which moves accumulator bits 4-7 to bits 4-7 of the status register.
STO-ST 3 bits are not affected.
FO
ST6
D6
D3
ISF
OBF
D1
DO
MOV STS, A Instruction OP Code 90H
3. RD and WR inputs are edge-sensitive. Status bits IBF, OBF, Fl and INT are
affected on the trailing edge at RD or WR.
RDorWR~~
"-____________________-Jr.xt
p - Flags affected
343
IlPD8041 A18741 A
J.LPD8041 A/8741 A
FUNCTIONAL
4. P24 and P25 can be used as either port lines or Buffer Status Flag pins. This
feature allows the user to make OBF and IBF status available externally to
interrupt the master processor. Upon execution of the EN Flags instruction,
P24 becomes the OBF pin. When a "1" is written to P24, the OBF pin is
enabled and the status of OFB is output. A "0" written to P24 disables the
OBF pin and the pin remains low. This pin indicates valid data is available from
the JlPD8041 A/8741 A. EN Flags instruction execution also enablus P25 indicate that the JlPD8041 A/8741 A is ready to accept data. A "1" written to P25
enables the IBF pin and the status of IBF is available on P25. A "0" written to
P25 disables the IBF pin.
ENHANCEMENTS(CON~)
EN Flags Instruction Op code - F5H.
5. P26 and P27 can be used as either port lines or"DMA handshake lines to allow
DMA interface. The EN DMA instruction enables P26 and P27 to be used as
ORO (DMA Request) and i5AcK (DMA acknowledge) respectively. When a
"1" is written to P26, ORO is activated and a DMA request is issued. Deactivation of ORO is accomplished by the execution of the EN DMA instruction,
DACK anded with Rl5, or DACK anded with WR. When EM DMA has been
executed, P27 (i5ACK) functions as a chip select input for the Data Bus
Buffer registers during DMA transfers.
EN DMA Instruction Op Code - E5H.
BLOCK DIAGRAM
CRYSTAL. Le. OR CLOCK
HA.PHE""'L INTI .. FACE
MASTER SYSTEM INTERF ACE
' - - , -.....1'1
VDO
{
,024.1
~ ",OO .. AM POWER S","LV
Vee ~ +&') 'lJIII'PLY
POWER
RESIDENT
RDM/PRDM
I'ADGRAM MEMORV
Vu ____ OftOUNO
344
",PD8041 Al8741 A
ABSOLUTE MAXIMUM
RATINGS*
Operati'ng Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. O°C to +70°C
Storage Temperature (Ceramic Package) . . . . . . . . . . . . . . . . , -65°C to +150°C
Storage Temperature (Plastic Package). . . . . . . . . . . . . . . . . . , -65°C to+150°C
Voltage on Any Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 to +7 Volts .
31
D6
I
0
d7
efore WR
tAW
Address Setup before Data In
tAFC
Control Pulse to ALE
tCA
Notes:
- --
~
--~
"""---_'""*_,::H____
7v- - -,'-_____Li LI __ J
PROGRAM/VERIFY TIMING
(~PD8748 ONLY)
___..-JI
~
==>- --<
I:~~~!~o
---------~)(
\1..--____----11
'--
X,-_O...;"vT;.;.::":;;:~~,-T--,,>- - - -<,-_...;A.;;;~;.;.~=;;;,;~ss~--,,~ - - -
)(~------------------------VERIFY MODE TIMING
(~PD8048/8748 ONLY)
Note.
<.1) Condition.!;. CS TIL Logic" 1"; Ao TIL Logic "0" must be met. (Use 10K resistor to
®
VCC for CS, and 10K resistor to VSS for Ao)
tCY 51ls can be achieved using a 3 MHz frequency source (LC, XTAL or external) at the
XTAL 1 and XTAL 2 inputs.
357
INSTRUCTION SET
"PD8048/8748/8035L
INSTRUCTION CODE
MNEMONIC
FUNCTION
DESCRIPTION
07
DO
05
04
03
02
FLAGS
01
(AI - (AI + data
ADD A, Rr
(AI - (AI + (Rd
forr ' 0- 7
the Accumulator.
0
d7
Add Immediate the specif ied Data to the
Accumulator.
ADDA,@Rr
(AI - (AI + ((Rdl
for r'" 0·- 1
Add Indirect the contents the data
memory location to the Accumulator.
ADDC A, "data
(AI - (AI + (CI + deta
Add Immedi,!lte with carry the specified
data to the Accumulator.
0
d7
ADDC A, Rr
(AI· (AI + (CI + (Rd
forr=0·7
Add with carry the contents of the
,designated register to the Accumulator.
0
ADDC A,@Rr
(AI - (AI + (CI + ((Rdl
for r = 0- ,
Add Indirect with carry the contents of
=data
ANL A,
(AI· (AI AND data
Logical and spec if ied I mmediate Data
with Accumulator.
d7
Logical and content:; of designated
0
(AI - (AI AND (Rd
for r = 0 - 7
ANLA,@Rr
(AI - (AI AND ((Rdl
for r:l\ 0
CPL A
(AI - NOT (AI
Complement the contents of the
AccumUlator.
CLR A
(AI · 0
CLEAR the contents of the Accumulator.
DAA
,
(AI - (AI +'
Increment by 1 the accumulator's
(AI - (AI OR data
Logical OR specified immediate data
with Accumulator
d7
ORL A, Rr
(AI .- (AI OR (Rd
for r ' 0 - 7
Logical OR contents of designated
register with Accumulator.
(AI - (AI OR ((Rdl
for r - 0 - ,
Logical OR Indirect the contents of data
memory location With Accumulator.
RL A
(AN"I - (ANI
(AOI- (A7 1
for N = 0 - 6
(AN + , I - (ANI; N • 0 - 6
(AOI - (CI
(CI - (A71
Rotate Accumulator left by l·blt wltho'"'t
carry.
(ANI - (AN + 1); N - 0 - 6
(A71 - (AOI
Rotste Accumulator right by l-bit
without carry.
RRCA
(ANI - (AN + , I; N • 0 - 6
(A71 - (CI
(CI· (AOI
Rotate Accumulator right by l-bit
through carry.
(A4-7 1 ;:
#
data
(Ao - 31
(AI .- (AI XOR data
XRL A, Rr
(AI - (AI XOR (Rd
for r =0 - 7
XRL A,@Rr
(AI - (AI XOR ((Rdl
for r ' 0
,
dO
,
,
d{.
dS
d4
0
d3
0
d2
d,
dO
1
d(;
dS
1
d4
0
d3
0
d2
dl
1
dO
dli
0
dS
d4
0
d3
0
d2
d,
dO
0
0
.d.;
dS
d4
d3
0
d2
d,
1
dO
1
0
0
,
Rotate Accumulator left by l-blt through
carry.
RR A
XRL A,
d,
DECREMENT by 1 the accumulator',
contents.
ORlA,@Rr
SWAP A
d2
DECIMAL ADJUST the contents of the
Accumulator.
INCA
RLC A
d3
0
Logical and I ndirect the contents of data
memory with Accumulator.
(AI· (AI
=data
d4
register with Accumulator.
DEC A
ORL A,
dS
data memory location to the
Accumulator.
ANL A, Rr
,
0
dE
0
Add contents of designated register to
CYCLES
,
ACCUMULATOR
ADD A, # data
DO
Swap the 2 4·bit nibbl~ in the
Accumulator.
,
,
Logical XOR specified immediate data
with Accumulator.
d7
Logical XOR c!)ntents of designated
register with Accumulator.
,
Logical XOR Indirect the content. of data
memory location with Accumulator.
BRANCH
DJNZ Rr, addr
(Rd - (Rrl - 1; r - 0 - 7
If (Rd
0;
(PC 0 - 71 - addr
(PC 0 - 71 - addr if Bb • ,
(PCI - (PCI + 2 if Bb • 0
Decrement the specified register and
test Contents.
a7
a-3
as
a4
a3
a2
a,
·0
Jump to spe£ified address if
Accumulator bit is set.
b2
a7
b,
8i;
84
a3
a2
(PC 0 - 71 - addr if C • 1
(PCI - (PCI + 2 if C =0
Jump to specified address if carry flag
isset.
,
bO
"5
a7
a,
85
a4
0
a3
a2
JFOaddr
\PC 0 - 71 - 8ddr if FO • ,
(PCI -)(PCI + 2 if FO • 0
Jump to specified address if Flag FO is
set,
a7
83
as
04
°3
a2
JF' addr
(PC 0- 71 -addr if Fl-1
(PCI - (PCI + 2 if F' • 0
Jump to specified addre .. if Flag F' i.
58t.
0
87
a3
as
a4
a3
a2
,
,
,
.,
(PCS- '01 - addrS-'O
(PC 0 - 71- addr 0 - 7
(PC ,'1'- DBF
Direct Jump to specified address within
the 2K addre .. block,
a,o
87
a3
as
8S
a5
0
a4
0
83
,
,
,
,
a2
a,
JBb addr
JC add,
JMP addr
*
JMPP@A
(P.C 0 - 71 - ((All
Jump indirect to specified address with
with address page.
JNC addr
(PC 0 - 71 - addr if C • 0
(PCI' (PCI + 2 if C • ,
Jump to specified address if carry flag is
low.
JNI addr
(PC 0 - 71 - addr if I = 0
(PCI ~. (PCI + 2 if I - ,
Jump to specified address if interrupt
is low.
358
,
,
0
8,
ao
a,
"0
0,
ao
0
0
ao
0
ao
2·
I
,
~6
a5
.j
87
16
0
a5
87
a4
a3
a2
I,
80
a4
0
a3
a2
a,
0
aO
,
BYTES
C AC
FO
F1
",PD8048/8748/8035L
INSTRUCTION SET (CONT.)
FLAGS
INSTRUCTION CODE
MNEMONIC
FUNCTION
DESCRIPTION
07
Os
05
04
03
02
01
DO
CYCLES
BYTES
BRANCH (CONT.)
a-
a
a-
=a
JNTO oddr
(PC
7) ~ addr if TO ~
(PC) ~ (PC) + 2 if TO - 1
JNTI addr
(PC
7) ~ addr if Tl
(PC) ~ (PC) + 2 if Tl = 1
Jump to specified address if Test 0 is low.
Jump to specified address .f Test 1
IS
JNZ oddr
(PC 0 - 7) ~ addr if A = 0
(PC) ~ (PC) + 2 if A = 0
Jump to specified address If accumulator
JTF addr
(PC 0 - 7) ~ addr if TF = 1
(PC) ~ (PC) + 2 if TF = 0
Jump to specified address If Timer Flag
IS set to 1.
(PC 0 - 7) ~ addr if TO - 1
(PC) ~ (PC) + 2 if TO - 0
Jump to specified address if Test 0 Is a .
JTl addr
(PCO-7) ~addr ifTl-l
(PC) ~ (PC) + 2 if Tl = 0
Jump to specified address if Test 1 is a 1.
JZ addr
(PC
(PC)
JTO addr
a - 7) ~ addr if A = 0
~
(PC) + 2 if A = 0
07
a6
a5
a4
83
a2
al
aO
"7
1
a6
a5
84
a3
1
a2
al
0
ao
low.
a7
0
ao
a5
1
a4
"3
1
a2
al
ao
a7
a6
0
a5
1
04
a3
a2
al
ao
a7
0
a6
as
1
a4
0
03
1
a2
al
0
aO
0
a3
1
85
1
a4
1
"7
1
a6
a6
0
a5
a4
0
03
"2
1
02
·1
1
al
ao
07
d7
0
d6
d5
d4
d3
d2
dl
dO
d7
d6
d5
d4
1
d3
d2
dl
dO
a
Jump to specified address if Accumulator
is O.
a
0
aO
CONTROL
EN I
Enable the External Interrupt input.
DIS I
Disable the External Interrupt Input.
Enable the Clock Output pin TO.
ENTO ClK
SEL MElO
(OBF)
~
0
Select Bank 0 (locations 0
Program Memory.
SEL MEll
(OBF)
~
1
Select Bank 1 (locatIons 2048
Program Memory.
SEL ABO
(SS)
SEL ABI
(SS)~
~O
2047) of
40951 of
Select Bank 0 (locations 0 - 7) of Data
Memory.
1
Select Bank 1 (locations 24
Data Memory.
3110f
DATA MOVES
MOVA.
data
MOV A. Ao
MOV
A,~;)
(A)
~data
(AI~(Ad;r=0-7
Move Immecilate the specifllJd daW Into
the Accumulator
Move the,contents of the deslqnated
registers Into the Accumulator.
Rr
(AI
~
((Ad); r ' 0 - 1
Move Indirect the contents of data
memory local Ion Into Ihe Accumulatol.
MOV A. PSW
(A)
~
(PSW)
Move contents of' the Program Status
Word IOta the Accumulator.
MOV Ar.
data
(Ad
~
data; r - 0 - 7
Move Immediate the specified dala Into
the deSignated register.
MOV Ao, A
(Ar)
~
(AI; r = 0 - 7
Move AccumulCJtor Contents tnto the
deSignated register.
MOV@Ar,A
((Ar))
~
(A); r = 0 - 1
Move Indirect Accumulator Contents
Into data memory locatIon.
MOV@ Rr, :: data
((Ar))
~
data; r = 0-1
Move Immediate the specified data Into
data memory.
MOV PSW. A
(PSWI
~
(A)
Move contents of Accumulator IOta the
program status word.
a-
MOVP A.@A
(PC
7) ~ (AI
(A) ~((PC))
Move dma In the current page IOta the
Accumulator.
MOVP3 A.@A
(PCO-71 ~ (AI
(PC B-1 01 .- 011
(A)·- ((PC))
Move Program data In Pa~e 3 IOta the
Accumulator.
MOVXA.@R
(AI~((Arll;r=O-l
Move Indirect the contents of external
data memory Into the Accumulator.
MOVX QO R. A
((Ar))
Move Indirect the contents of the
Accumulator Into external data memory,
~
(A);r = 0- 1
XCH A, Ar
(AI;:' (Arl;r = 0-7
ExchangfJ the Accumulator and
deSignated register's contents.
XCH A,@Ar
(AI;::((Arll;r=O-1
Exchange Indirect contents of Accumu·
lator and location in data memory.
XCHO fl,,@Ar
(A
31;: ((Ad) 0 - 3));
r = 0-1
a-
1
0
d7
ICI· NOT (CI
Complement Content of carry bit,
(FOlo NOT (FOI
Complement Content of Flag FO.
Complp.ment Cont€'nt of Flag F 1-
CPL Fl
IF 11· NOT (FlI
CLA C
ICI· 0
Clear' content of carry bit to O.
ClA FO
(FOI· 0
Clear contenl of Flag 010 O.
CLA Fl
IF11· 0
Clear content of Flag 1 to O.
d4
0
d3
a
-0
..!.lAGS
CPl C
dS
0
Exchange Indlfect 4·btt contents of
Accumulator and data memory.
CPl FO
d6
1.
0
359
0
d2
dl
dO
C
AC
FO
Fl
JlPD8048/87 48/803~L
INSTRUCTION SET (CONT.)
INSTRUCTION CODE
MNEMONIC
FUNCTION
07
DESCRIPTION
06
FLAGS
05
04
03
02
01
DO
0
d6
dS
d4
1
d3
0
d2
d1
p
P
d7
d6
0
d5
d4
d3
d2
el1
dO
1
0
0
d6
dS
d4
1
d3
d2
dl
dO
0
0
0
d7
O.
d6
dS
d4
d3
d2
p
dl
p
dO
0
0
0
0
0
0
al0
a9
aR
a7
a6
as
a4
a3
'2
al
·0
CYCLES
INPUT/OUTPUT
ANL BUS, " data
(BUS) - (BUS) AND data
Logical and Immediate-specified data
with contents of BUS.
ANL Pp, "data
(Pp) .- (Pp) AND data
p = 1- 2
Logical and Immediate specified data
with deSignated port (1 Or 2)
ANLD Pp, A
IPp) - (Pp) AND IA 0 - 3)
p =4 - 7
Logical and contents of Accumulator with
designated port 14 - 7),
IN A, Pp
IA) -. IPp); p = 1 - 2
Input data from designated port (1 - 21
d7
dO
into Accumulator.
INS A, BUS
IA) -. IBUS)
Infut strobed BUS data into Accumulator.
MOVD A, Pp
IA 0- 3) - IPp); p = 4 - 7
IA 4- 7) - 0
Move contents of designated port 14 - 7)
into Accumulator.
(Pp) - A 0 = 3; p • 4 - 7
Move contents of Accumulator to
designated port 14 - 7l.
MOVD Pp, A
OR L BUS,
data
IBUS) - (BUS) OR data
Logical or Immediate specified dats with
content, of BUS,
IPp) - IPp) OR IA 0 - 3)
p=4-7
ORlD PI>, A
IPp) - IPp) OR data
.p = 1 - 2
OR l Pp, ., data
0
d7
Logical or contents of Accumulator with
designated port 14·- 7),
logical or Immediate specified data with
designated port 11 - 2l.
OUTL BUS, A
IBUS) - IA)
Output contents of Accumulator Onto
BUS,
OUTL Pp, A
IPp) _. IA);p = 1 - 2
Output contents of Accumulator to
designated port 11 - 2l.
DEC R,
(Rd - (Rd
REGISTERS
(Rd
+ 1; r
=0 - 7
IRr) + 1; r = 0 - 7
INC f1<
IRd
INC@R,
IIRr)) - IIRr)) + 1;
~-
r· 0 _ 1
Decrement hy 1 contents of deslqnated
rp.gI5ter.
Increment by 1 contents of deSignated
register
Incfement Indirect by 1 the contents of
data memory location.
SUBROUTINE
CALL add,
I(SP)) - (PCl. IPSW 4 - 7)
ISP) - ISP) + 1
IPCB-10)-addrB-10
IPC 0 - 7) ~ addr 0 - 7
IPC11)-DBF
Call deSignated Subroutine.
RET
(SP) - (SP) • 1
IPC) > - liSP))
Return from SubroutIne Without
restoring Program Status Word.
RETR
ISP) - ISP) = 1
IPC)·- liSP))
IPSW 4 - 7) - liSP))
Return from Subroutine restoring
Program Status Word.
TlMERICOUNTER
EN TCNTI
Enable Internal InierruPt Flag for
Timer/Counter output
DIS TCNTI
Disable Internal Interrupt Flag lor
Timer/Counter output.
MOV A, T
IAI· ITI
MOV T, A
ITI, IAI
0
Move contents of Timer/Counter mto
Accumulator
Move contents of Accumulator Into
Timer/Counter
STOP TCNT
Stop Count for Event Counter.
STRT CNT
Start Count for Event Counter.
STRT T
Start Count for Timer
NOP
No OperatIon performed
MISCELLANEOUS
Notes
CD
Instruction Code DeSIgnations rand p form the binary representalton of the Registers and Port~. Involved.
@
@
The dot under the appropriate flag bit Indicates that Its content IS subject to change by the Instr·jctlon It appears In.
®
References to the address and data are specified
10
bytes 2 and/or 1 of the Instruction
Numeflcal Subscripts appearing in the F UNCTION column reference the specific bits affected.
Symbol Definitions:
SYMBOL
A
AC
addr
Bb
BS
BUS
C
CLK
CNT
D
data
DBF
FO, F,
I
P
DESCRIPTION
The Accumulator
The Auxiliary Carry Flag
Program Memory Address (12 bits)
Bit Designator (b = 0 - 7)
The Bank Switch
The BUS Port
Carry Flag
Clock Signa)
Event Counter
Nibble Designator (4 bits)
Number or Expression (8 bits)
Memory Bank Flip-Flop
Flags 0,1
Interrupt
"In-Page" Operation Designator
SYMBOL
DESCRIPTION
Port Designator (p = I, 2 or 4 - 7)
ProQr-Im Status Word
Regis,er Designator (r = 0, 1 or 0 - 7)
Stack Pointer
Timel
Time,- Flag
TestalJle Flags 0, 1
External RAM
Prefix for Immediate Data
Prefix for Indirect Address
Prognm Counter's Current Value
Contents of External RAM Location
Contents of Memory Location Addressed
by the Contents of External RAM Location,
Replaced By
Pp
PSW
Rr
SP
T
TF
TO. T,
X
@
S
(x)
((x))
~
360
BYTES
C
AC
FO
F1
,..PD8048/8748/8035L
LOGIC SYMBOL
PORT =;1
PORT =2
RESET
READ
SINGLE
STEP
j1PD
8048
FAMILY
WRITE
PROGRAM STORE
ENABLE
ADDRESS LATCH
ENABLE
PORT EXPANDER
STROBE
BUS
8
PACKAGE OUTLINES
J,tPD8048C
J,tPD8035LC
Plastic
ITEM
MILLIMETERS
A
51.5 MAX
8
INCHES
2.028 MAX
1.62
0.064
C
2.54
0
E
F
0.5 ± 0.1
:t
0.1
0.10 ± 0.004
0.019 + 0.004
48.26
1.9
0.047 MIN
1.2 MIN
2.54 MIN
0.10MIN
O.SMIN
0.019 MIN
[
5.22 MAX
0.206 MAX
J
5.72 MAX
15.24
0.225 MAX
K
L
13.2
0.520
G
H
M
0.600
0.25 + 0.1
0.05
0.010 + 0.004
0.002
J,tPD8048D
J,tPD8035LD
Ceramic
ITEM
MILLIMETERS
INCHES
A
51.5
1.62
2.54
0.5 ± 0.1
48.26
1.02
3.2
1.0
3.5
4.5
15.24
14.93
0.25 ± 0.05
2.03
0.06
0.1
0.02 + 0.004
1.9
0.04
0.13
0.04
0.14
0.18
0.6
0.59
0.01 ± 0.0019
B
C
0
E
F
G
H
I
J
K
L
M
361
"PD8048/8748/8035L
PACKAGE OUTLINE
IlPD8748D
Cerdip
I
53.34 max
I
'~::::::::~:::::::J~
1
W
1.3
2.54 . 0.25
0.5 ~ 0.1
1 - < - - - - - - - - 48.26 - - - + 1
8048/8748/8035 LOS-Rev 1-12-81-CAT
362
NEe
JLPD80C48/JLPD80C35
CMOS 8-BIT SINGLE-CHIP
MICROCOMPUTER
NEe Electronics U.S.A. Inc.
Microcomputer Division
Description
Pin
The NEC j'.LPD80C48 is a true stand-alone 8-bit microcomputer fabricated with CMOS technology. The
/LPD80C48 contains all the functional blocks -1 K bytes
ROM, 64 bytes RAM, 28 I/O lines, on-chip 8:-bit Timer/
Event counter, on-chip clock generator - to enable its use
in stand-alone applications. For designs requiring extra
capability the /LPD80C48 can be expanded using industry
standard Ii-PD8080N/LPD8085A peripherals and memory
products. The /LPD80C35 differs from the /LPD80C48 only
in that the JLPD80C35 contains no internal program memory (ROM).
Compatible with the industry-standard 8048, 8748, and
8035, the CMOS-fabricated /LPD80C48 provides significant power consumption savings in applications requiring
low power and portability. In addition to the power savings
gained through CMOS technology, the NEC /LPD80C48
features Halt and Stop modes to further minimize power
drain.
No.
Function
Symbol
The other side of the crystsllnput.
RESET
Single step Input (active-low). SS wltli ALE allows the
processor to "single-step" through each Instruction In
program memory.
7
'NT
Interrupt Input (actlve-low).INT atsrta an Interrupt If an
enable Instruction has been executed. A reset disables ths
Interrupt. iiiiT can be t..ted by Issuing a conditional Jump
Instruction.
EA
External Access Input (active-high). A logic "1" at this Input
commanda the proceasor to perform all program memory
fetches from external memory.
RD
Read strobe output (active-low). ~pulseslow when the
proceasor performs a Bus Read. RD also enables deta onto
the processor Bus from a peripheral device and functlona
as a Read Strobe for external Data Memory.
Program Store Enable output (active-low). PSEN becomes
active only during an external memory fetch.
Features
10
WlI
Write strobe output (active-low). WR pulses low when the
processor performs a Bus Write. WR can also function as a
Write Strobe for, external Data Memory.
1'I
ALE
Address Latch Enable output (active high). Occurlng once
each cycle, the failing edge of ALE latches the addresa for
external memory or peripherals. ALE can also be used aa a
clock output.
12 - 19
Do - 0, BUS
8-blt, bidirectional port. Synchr~us reads and writ.. can
be performed on this port using RD and WR strobes. The
contents of the Do - 0, Bus can be latchad In a static mode.
During an external memory fetch, the Do - 0, Bus holds the
least significant bits of the program counter. PSEN controla
the Incoming addressed Instruction. Also, for an external
RAM data store Instruction the Do - 0, Bus, controlled by
ALE, iffi and \YR, contains addre.. and data Information.
D 8-bit CPU, ROM, RAM, I/O in a single package
D Hardware/Software-compatible with industry standard
8048,8748,8035 products
D 1Kx8 ROM
D 64x8 RAM
D 27 I/O lines
D 2.5 /LS cycle time (6 MHz crystal)
D
D
D
D
D
D
D
D
D
D
D
D
All instructions 1 or 2 cycles
97 instructions: 70% single-byte
Internal Tim~r/Event Counter
Two Interrupts (External and Timer)
Easily.expandable memory and I/O
Bus:-compatible with 8080N8085A peripherals
CMOS technology
Operational over a 2.5 to 6.0V range
Available in 40-pin DIP or 52-pin flat pack
Low-power Standby modes
Halt Mode
1 rnA typical supply current
Maintains internal logic values and control status
Initiated by HALT instruction
Released by External Interrupt or Reset
Stop Mode
1 /LA typical supply current
Disables internal clock generation and internal logic
Maintains RAM
Initiated via Hardware (Voo)
Released via Reset
20
21-24,
35-38
No.
PROG Is used as an output strobe for the ~PD8243.
25
PROG
26
Voo
27-34
PlO -P,,:
PORT 1
39
T1
Testable Input using conditional transfer functions JT1 and
JNT1. T1 cen be made the counter/timer Input using the
STRT CNT Instruction.
40
Vee
Primary Power Supply.
+5V during normal operation. VOQ Is used In Stop Mode. By
forcing Voo low during a reset, the processor enters Stop
Mode.
Port 1 Is one of two 8-blt quasi-bidirectional ports.
AEffi
55
Tfiff
EA
Ri5
?SEN
WR
10
P14
P13
PI1
Pl0
Function
XTAL 1
Processor's Ground potential.
Port 2 Is the aecond of two 8-blt quasi-bidirectional ports.
For external data memory fetches, the four most slgnlflcan
bits of the program counter are contained In p.. - P2,. Bits
p.. - P" are alao used as a 4-blt I/O bus for the ~PD8243,
Inp,Yt/Output Expander.
XTAL2
Symbol
TO
V..
P20 -P,,:
PORT 2
Pin Configuration
Pin Identification
Pin
Active low Input for processor Initialization. RESET Is also
used for Halt/Stop Mode release (non-TTL-compatlble V,H ).
~ff8G
Testable Input using conditional transfer functions JTO. and
JNTO. The Internal State Clock (CLK) la available to To ualng
the ENTO eLK Instruction. To can also be used during programming as a testable flag.
P22
P21
One side of the cryatallnput for external oscillator or frequency (non-TTL-compatible V,H).
Rev1
t:!at:!
IJPD80C48/IJPD80C35
Blo,~k
Diagram
--..
~
cc
pOwER
SUPPLY
Vss
~GAOUND
,LEVEL STACK
(VARIABLE WORD LENGTH
Ace
~~~II~~:; :;~~N
0
Ace BIT TEST
RESIDENT DATA MEMORY
(641(81
READWAtTE
lOW POWER
STANDBY CONTROL
STAOBES
Absolute Maximum Ratings*
Limit.
Parameter
Operating Temperature
Storage Temperature (Ceramic Package)
Storage Temperature (Plastic Package)
Voltage on Any Pin
Supply Voltage
-WC to +85"C
-65"C to +15O"C
-65"C to +125"C
Vss -O.3Vto Vee +O.3V
Vss -0.3 to +10V
*COMMENT: Exposing the device to stresses above those
listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated
under conditons outside the limits described in the operational sections of this specification. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
DC Characteristics
Ta
= - 40°C to
+ 85°C; Vee
Parameter
Symbol
Umlla
Input Low Vultage
(All Except XTAL 1. XTAL 2)
Input High Voltage
(All Except XTAL 1. XTAL 2.
Output Low Voltage
o-;:;tP';-; High voltege(BU5.RD.WFi.
PSEN. ALE)
Output High Voltage (All Other
Outputs)
M..
/LA Vos < V'N < Vee
Input Leakage Current
(EA)
~L1
±3
/LA V•• < V'N< Vee
Output LBBkege Current
(BUS, To ....:. High Impedance
Stille)
10..
±1
/LA V•• < V'N< Vee
10
mA Ta
(T1,1f.IT)
1,,0 +
Halt Power Supply Current
Stop Mode Supply Current
Icc
Icc
RAM Dete Retention Voltage
Vee DR
T••• Condillon.
/LA 6MHz
V
Stop Mode (Voo ,
RE$ET .;; .4V) or
RESET.;; 0.4V
400
nB
2.16
/J.
120
ns
1620
ns
Vee
Address Hold
from ALE
tLA
60
ns
330
ns
Vee
Control Pulse
Width
tcc
700
ns
tDW
500
Date Hold
afterWR
tWD
120
Cycle Time
tCY
2.5
Data Hold
tOR
10l
= 1.0 rnA
10H
= - 100!
V
Vee
V
10l= 2.0mA
V
10H
2.4
V
IoH = -5/LA
V
IoH
0.45
-15 -40
~le
-40
±1
/LA
= --100/LA
=
VIN~
-O.2}LA
/LA Vss <
YIN
Unit
400
ns
t...l
120
n.
Addre.s Hold from ALE
tLA
80
ns
(15§EN. Ro, Wii)
Icc
700
ns
Data Setup before Wft
tow
SOO
na
Data Hold after WR'
two
120
ns
Cyclenme
2.5
Control Pulse Width
OataHold
Icv
loR
'JS!rA, m5 to Data In
t"o
Addre.a Setup before WJ!i
t...w
Addreas Setup before Data In
t...o
Addre.s Float to lm,l55Eiii
t AFC
Control Pul.e to ALE
teA
0
150
c.. = 20pF
/Ls
200
ns
SOO
n.
9SO
ns
230
T••t
CondltlonsG)
ns
ns
10
ns
Notes:
®
/LA VIN~VIL
Max
lL
MI
DO-D7
Memory Read or Write Cycles
This diagram illustrates the timing of memory read or write cycles other than an op
code fetch (M1 cycle). The function of the MREO and RD signals is exactly the same
as in the op code fetch cycle. When a memory write cycle is implemented, the MREO
becomes active and is used directly as a chip enable for dynamic memories, when the
address bus is stable. The WR line is used directly as a R/W pulse to any type of semiconductor memory, and is active when data on the data bus is stable:
~---Memory Read Cycle--_......._ - -
'I>
--+-------~--------~IN}_--+_----!::t:::J~~~!::::::tJ
"Il---- --
396
IiPD780
TIMING WAVEFORMS
(CaNT.)
Input or Output Cycles
This illustrates the timing for an I/O read or I/O write operation. A single wait·state
(TW) is automatically inserted in I/O operations to allow sufficient time for an I/O
port to decode its address and activate the WAIT line, if necessary.
'I,
----OUT
}
Rend
Cycle
Write
} Cycle
Interrupt Request/Acknowledge Cycle
The processor samples the interrupt signal with the rising edge of the last clock at the
end of any instruction. A special M1 cycle is started when an interrupt is accepted.
During the M1 cycle, the 10RO (instead of 'fViREQ) signal becomes active, indicating
that the interrupting device can put an a-bit vector on the data bus. Two wait states
(TW) are automatically added to this cycle. This makes it easy to implement a ripple
priority interrupt scheme.
INT
MI
MREO
IORO
r.I
11:1
WAIT
RD
INSTRUCTION SET
The following summary shows the assembly language mnemonic and the symbolic
operation performed by the instructions of the /JPD780 and /JPD780-1 processors.
The instructions are divided into 16 categories:
Miscellaneous Group
Rotates and Shifts
Bit Set, Reset and Test
Input and Output
Jumps
Calls
Restarts
Returns
8-Bit Loads
16-Bit Loads
Exchanges
Memory Block Moves
Memory Block Searches
8-Bit Arithmetic and Logic
16-Bit Arithmetic
General Purpose Accumulator and Flag Operations
The addressing Modes include combinations of the following:
Indexed
Register
Implied
Register Indirect
Bit
397
Immediate
Immediate Extended
Modified Page Zero
Relative
Extended
"PD780
TIMING WAVEFORM
CD
'I'
AO·~5
AO·A15
DO'7
r
tF IDI
DUT
'caf
M1
RFSH
1-
tr,,-t..r-
MREQ
AD
tOH:j; IWRI
~
V\IR
IORQ
AD
-~
WR
--~
tD IHTJ
tD IHTI
INT
NMI
"I"
Note:
CD
Timing measurements are made at the following voltages unless otherwise specified;
398
"0"
CLOCK
4.2V
O.8V
OUTPUT
INPUT
2.0V
O.8V
2.0V
FLOAT
::"V
O.8V
±O.5V
IlPD780
INSTRUCTION SET TABLE
SYMBOLIC
OPERATION
MNEMONIC
ADC HL, ss
HL~HL+ss+CY
ADCA,r
ADC A,n
A~A
DESCRIPTION
Add with carry reg. pair 55 to HL
Adc; with carry Reg. r to ACC
Add with carry value n to ACC
+ r + CY
A - A + n + CY
NO,
BYTES
NO.T
STATES
C
Z
FLAGS
15
t
t
4
7
t
t
OPCODE
PIV S
N
H
76 543 210
t
a
X
11
01
101
5s1
t
V
tOt
tV!
a t
10
11
nn
10
11
10
dd
11
10
dd
001 rrr@
001 110
nnn nnn
001 110
all 101
001 110
ddd ddd
111 101
001 110
ddd ddd
000 110
nnn nnn
V
101®
010
ADC A, (HL)
A ~ A + (HL) + CY
ADC A, (IX + d) A - A + OX + d) + CY
Add with carry loc. (HL) to ACC
Add with carry loc. (IX + d) to ACC
7
19
t
t
t
V
V
tOt
tOt
ADCA,(IY+d)
A~A+(IY+d)+CY
Add with carry loc. (IY + d) to ACC
19
t
t
V
tOt
ADD A, n
A~A+
I
tV!
a
I
11
nn
ADDA,r
A-A+r
Add Reg. r to ACC
4
!
t
V
t
I
10 000
rrr@
ADD A, (HL)
A-A+(HL)
Add location (HL) to ACC
7
!
t
V
t
I
10 000
110
!
11 011 101
10 000 110
dd ddd ddd
n
t
Add value n to ACC
A + (Ix + d)
Add location (IX + d) to ACC
19
t
I
V
I
a
o
o
ADOA,OY+d) A-A+(IY+d)
Add location OY + d) to ACC
19
t
t
V
!
o
t
11 111 101
10 000 110
dd ddd ddd
ADD HL, ss
HL-HL+ss
Add Reg. pair 55 to HL
I
•
001®
Add Reg. pair pp to IX
15
t
•
X
X
s51
IX - IX + pp
o
o
00
ADD IX, pp
11 all
00 ppl
101©
001
Add. Reg. pair rr to IY
15
I
•
o
X
11
00
111
rrl
101@
001
o
o
t
t
P
P
10
11
nn
10
11
10
dd
11
10
dd
100
100
nnn
100
011
100
ddd
111
100
ddd
rrr®
110
nnn
110
101
110
ddd
101
110
ddd
001 011@
bbb 110
ADD A, OX + d) A
~
'1
ADD !Y, rr
IY -IY
ANDr
AND n
A-AM
A-AJ\n
AND (HL)
AND (IX + d)
A - AJ\(HL)
A ~AJ\(lX + d)
Logical 'AND' of lac. (HL) J\ ACC
Logical 'AND' of lac. (IX + d) J\ ACC
7
19
o
o
t
t
AND (IY + d)
A -AJ\(lY + d)
Logical 'AND' of lac. OY + d) J\ ACC
19
o
I
P
I
0
I
BIT b, (HL)
Z - (HL) b
Test BIT bof location (HL)
12
•
I
X
X
a
I
11
01
BIT b, (IX + d)
Z-
b
Test BIT b at location (tX + d)
20
•
I
X
X
a
1
II OIl 101@
11 001 OIl
dd ddd ddd
01 bbb 110
BIT b, (tY + d)
Z - (1Y+d1 b
Test BIT bat location (IY + d)
20
•
I
X
X
0
1
11 III 101®
11 001 011
dd ddd ddd
01 bbb 110
X
X
+!T
(iXTel")
Logical 'AND' of Reg. r J\ ACC
I Logical 'AND' of value n J\ ACC
BIT b, r
Test BIT of Reg. r
CALL cc, nn
If condition cc false continue,
else same as CA L L nn
CALL nn
(SP _. 1) - PC
H
(Sp·- 2) ~ PCL
PC - nn
Unconditional call subroutine at
Call subroutine at location nn if
a
t
a
t
t
P
I
0
I
P
lOt
t
~~ ~~ ~:~®®
10
II +-i:c-+ 100®
condition cc is true
17
location nn
nn
nn
nnn
nnn
nnn
nnn
11
001
101
nn
nn
nnn
nnn
nnn
nnn
II1
CCF
CY-CY
Complement carry flag
4
t
•
•
•
a
X
00
I II
CP r
CP n
A-r
A-n
Compare Reg. r with ACe
Compare value n with ACC
4
7
t
t
t
t
V
t
I
1
1
t
V
t
CP (HL)
CP OX + d)
A- (HL)
A - OX + d)
Compare lac. (HLI with ACC
Compare lac. (IX + d) with ACC
7
I
t
t
19
V
V
I
t
1
1
I
Compare lac. (IY + d) with ACC
19
t
tV!
1
t
10
II
nn
10
11
10
dd
1I
10
dd
III rrr®
III 110
nnn nnn
111 110
all 101
III 110
ddd ddd
111 101
111 110
ddd ddd
•
II
10
101
101
101
001
•
11 101
10 111
101
001
CP (lY + d)
CPO
A . (HL)
HL ,. HL -I
BC <- BC- 1
Compare location (HLI and ACC,
decrement H Land BC
16
CPDR
A- (HL)
HL < HL ~ 1
BC - BC - I
until A = (HL) or BC
Compare location (HL) and ACC,
decrement HL and BC, repeat until
BC = 0
21 if BC = a
and A 1< (HL)
16 if BC =
Or A= (HL)
=0
399
a
t
t
n
a
INSTRUCTION SET TABLE
(CONT.)
flPD780
SVMBOLIC
OPERATION
MNEMONIC
DESCRIPTION
NO.
BVTES
NO. T
STATES
CPI
A - (HLl
HL - HL + 1
BC - BC - 1
Compare location (HL) and ACC,
increment HL and decrement BC
2
16
CPIR
A - (HL)
HL-HL+l
BC - BC- 1
until
A=(HL)orBC=O
Compare location (HLl and ACC,
increment HL, decrement BC
Repeat until BC = C
2
21 if BC = 0
and A ~ (HLl
16 if BC = 0
or A = (HLl
CPL
A-A
Complement ACC (l's camp.)
1
4
Decimal adjust ACC
1
4
DAA
DEC r
DEC (HLl
DEC (IX + d)
r+- r - 1
(HLl .... (HLl - 1
(IX + d) .... (IX + d) - 1
Decrement Reg. r
Decrement lac. (H Ll
Decrement lac. (Ix + d)
11
23
DEC (IV +d)
(IV + d) .... (IV + d) - I
Decrement lac. (IV + d)
23
DECIX
IX .... IX - I
Decrement I X
DECIY
IY -IY - I
DEC ss
ss-ss-1
4
2
10
Decrement IY
2
10
Decrement Reg. pair ss
1
6
DI
IFF -0
Disable interrupts
1
4
DJNZ, e
B .... B-1 if B = 0
continue if B / 0
PC - PC + e
Decrement B and jump relative if
B=O
2
8
EI
IFF -1
Enable interrupts
1
4
EX (SPl. HL
H - (Si> + 1)
L- (SP)
Exchange the location (SPI and HL
1
19
EX (SPl. IX
IX H •• (SP + 1)
IX L •• (SP)
Exchange the location (SPI and IX
2
23
EX (SP), IY
IY - (SP + 1)
H
IYI. - (SP)
Exchange the location (SPI and IY
2
23
EX AF, AF'
AF·· AF'
Exchange the contents of AF. AF .
1
4
EX DE, HL
DE - HL
Exchange the contents of DE and HL
1
4
EXX
BC - BC'
DE~' DE'
HL - HL'
Exchange the contents of BC, DE, H L
with contents of BC', DE', HL',
respectively
1
4
HALT
Processor Halted
HAL T (wait for interrupt or resetl
1
4
Set Interrupt mode 0
2
8
1M 0
IMI
Set interrupt mode 1
2
8
1M 2
Set Interrupt mode 2
2
8
IN A, (n)
A .... (nl
Load ACC with input from device n
2
11
IN r, (C)
r-(C)
Load Reg. r with input from device
(CI
2
12
INC (HLl
(HLl .... (HLl + 1
Increment location (HLl
1
11
INC IX
IX -IX + 1
Increment IX
2
10
INC (IX + d)
ItX + dl - IIX + d) + 1
Increment location (IX + d)
3
23
INC IY
IV -IY + 1
Increment IY
2
10
INC!lY + d)
ItY +d) -!lY +d) + 1
Increment location (IY + d)
3
23
INC r
r -r + 1
Increment Reg. r
1
4
INCss
ss-ss+ 1
Increment Reg. pair ss
1
6
IND
(HLl - (C)
8 - B'- 1
HL-HL-l
Load location (HL) with input from
port (Cl. decrement HL and B
2
16
400
C
Z
FLAGS
PIV S
N
H
·
·
·· ·· ·
··
·
·
·· ·· ··
·· ·· ··
··· ··· ··· ··· ··· ···
·· ·· ·· ·· ·· ··
·· ·· ··
·· ·· ··
·· ·· ·· ·· ·· ··
·· ·· ··
·· ·· ·· ·· ·· ··
·· ·· ··
·· ·· ··
·· ·· ··
·
·· · · · · ·
·
·· ·· ··
·
··· ;® : · · ·
t
OPCODE
76 543 210
l® t CD ,
1
I
11 101 101
10 100 001
I® ICD I
1
I
11 101 101
10 110 001
1
1
00
101
111
I
00
100
111
00
00
11
00
dd
11
00
dd
rr r
110
011
110
ddd
III
110
ddd
101®
101
101
101
ddd
101
101
ddd
11
00
011
101
101
011
11
00
111
101
101
011
00
ssl
011®
11
110 011
I
P
!
t
I
I
V
V
V
I
1
1
I
I
I
I
t
V
t
I
t
t
t
00 010 000
~-2----
11
111
11
100 011
011
11
11
011 101
100 OIl
11
11
111 101
100 011
00 001
000
11
101
011
11
011
001
01
110 110
11
01
101
000
101
110
11
01
101
010
101
110
11
01
101
011
101
110
11
nn
011
nnn
011
101
rrr
~~~ CD
I
P
I
0
!
11
01
I
V
t
0
t
00 110 100
I
V
t
0
t
11
00
000
011 101
100 011
11 011 101
00 110 100
dd ddd ddd
11
00
111 101
100 011
I
V
I
0
I
11 111 101
00 110 100
dd ddd ddd
I
V
t
0
t
00
rr r
00
ssO 011®
X
1
X
11 101
10 101
l00®
101
010
IlPD780
SYMBOLIC
OPERATION
MNEMONIC
INOR
INI
(HLl - (C)
B - B-1
HL ~ HL - 1 until B
=0
(HLl" (C)
B· B-1
HL~HL+l
INIR
(HL) ~ (C)
B .-. B-1
HL·- HL + 1 until B
=0
NO,
BYTES
DESCRIPTION
NO, T
STATES
Load location (HL) with input from
port (C), decrement HL and decre·
ment B, repeat until B = 0
21
Load location (H Ll with input from
port (C); and increment HL and
decrement B
16
Load location (HLl with input from
port (C), increment HL and decre·
ment B, repeat unti I B = 0
21
C
Z
:@
FLAGS
PIV S
X
X
X
X
X
X
N
H
OP CODE
76 543 210
11
10
101
111
101
010
X
11
10
101
100
101
010
X
11
10
101
110
101
010
JP (HLl
PC·
HL
Unconditional jump 10 (HLl
11
101
001
JP (IX)
PC·
IX
Unconditional jump 10 (I X)
11
11
011
101
101
001
JP (lY)
PC,
IY
Unconditional jump to (IY)
11
11
III
101
101
001
JP cc, nn
If cc t,ue PC . nn else continue
Jump to locatIOn nn if condition cc
10
11 -<:c--' 01O®
10
11
IS true
JP nn
PC· nn
Unconditional jump to location nn
JR C, e
If CeO continue
If C = I PC· PC + e
Jump ,elatlve to PC + e, if carry
,JR e
PC· PC + e
Unconditional jump relative to PC
,JR NC,.
If C = I continue
If C ~ a PC· PC
Jump relative to PC + e If carry
t
1
c
o.
-I-
7 If condition
met 12, If
e
.
000
OIl
00 III 000
--e·2-
12
00 01 I 000
_ _e - 2 _
a
00
e
110
000
~e-2~
JR NZ, e
If Z
=
I continue
Jump relative to PC + e if non-zero
JR Z, e
If Z =
o continue
Jump relative to PC ... elf
(Z = 1)
LD A, IBC)
A·
(BC)
Load ACC With location (BC)
00
001
ala
LD A, (DE)
A·
(DE)
Load ACC with location (DE)
00
gIl
010
l.DA, I
A'
I
Load ACC With I
11
01
101
010
101
111
l.D A, (nn)
A·
Inn)
Load ACC with location nn
00
111
010
t.D A, R
A'
R
Load ACC with Reg. R
11
01
101
all
101
111
lOa___
00
000
__ e·2
(Z "0)
00 101 000
__ e-2 ___
lerO
IFF
13
IFF
1
LO (BCl, A •
(BC) • A
Load location (BC) with ACC
00
000
010
LD (DE), A
(DE) ~A
Load locatIOn (DE) with ACC
00
010
010
LD (HLl, n
(HLl •. n
Load location (HLl with value n
10
00
110
110
LD 55, nn
55' nn
Load Reg, pair ss with value nn
20
00
5S0
~~~®
LD H L, (nn)
H· (nn + 1)
L' (nn)
l.oad HL with location (nn)
16
00
101
010
LD (HLl,'
(HLl •
Load location (HLl with Reg. ,
01
110
"r®
LD I, A
I,
Load I With ACC
II
01
101
000
101
III
LD IX, nn
IX
LO IX, (nn)
,
A
~
nn
nnn
Load IX with value nn
19
11
00
all
100
101
001
IX .- (nn + 1)
H
IX • (nn)
L
Load IX with rocation (nn)
20
11
00
011
101
101
010
LD (IX + dl, n
(IX + d)· n
Load location (IX + d) with value n
19
11
00
dd
nn
all 101
110 110
ddd ddd
LD (IX + dl, r
(IX + d)' ,
Load location (IX + d) with Reg. r
19
11
01
dd
all
110
ddd
401
~~~®
ddd
m
"PD780
INSTRUCTION SET TABLE
(CONT.)
SYMBOLIC
OPERATION
MNEMONIC
LD IY, nn
IY
LD IY. Inn)
IYH~lnn+1)
~
nn
DESCRIPTION
NO.
BYTES
NO. T
STATES
C
Z
FLAGS
P/V S
OPCODE
N
H
76 543 210
Load IY with value nn
14
11
00
111
100
101
001
Load IY with location Inn)
20
11
00
111
101
101
010
ssH~' Inn + 1)
ssL ~ Inn)
Load Reg. pair dd with location Inn)
20
11
01
101
ssl
LD IIY + d), n
IIY+d)~n
Load IIY + d) with value n
19
11 111 101
00 110 110
dd ddd ddd
nnn
LDIIY+d),r
IIY + d) - r
Load location IIY + d) with Reg. r
19
11
01
dd
111
110
ddd
00
1'10
IY L ~ Inn)
LD ss, Inn)
LD Inn), A
Inn) -A
Load location Inn) with ACC
13
~~~®
all
nnon
101®
ddd
010
nnn
LD Inn), ss
(nn + 1) .- ssH
Inn) ~ssL
Load location Inn) with Reg. pair dd
20
11
01
101 101®
ssO 011 .
LD Inn), HL
Inn + 1) •. H
Inn) - L
Load location Inn) with HL
16
00
100
010
LD Inn), IX
Inn + 1) -. IX
H
Inn) .- IX
L
Load location Inn) With IX
20
11
00
011
100
101
010
LD Inn), IY
Inn + 1) '-IY
H
Inn) - IY L
Load location Inn) with IY
20
11
00
111
100
101
010
LD R, A
R-A
Load R with ACC
11
01
101
,001
101
111
all
101®
110
ddd
LOr. (HU
r~IHU
Load Reg. r with location IHU
LDr,IIX+d)
r-I!X +d)
Load Reg. r with location IIX + d)
19
11
01
dd
ddd
LDr,IIY+d)
r -IIY + d)
Load Reg. r With location !lY + d)
19
11
01
dd
ddd
LD r, n
r-n
LD, r, r
r
LD SP, HL
SP·- HL
+-
r'
11O®
01
111
101®
110
ddd
Load Reg. r with value n
00
Load Reg. r wi th Reg. r
01
Load SP with HL
11
111
001
all
111
101
001
110®
nnn
r'r',®
LD SP, IX
SP.- IX
Load SP With IX
10
11
11
LD SP, IY
SP
~
Load SP with IY
10
11
11
111
111
101
001
LDD
(DE) ~ IHU
DE-DE--l
Load location IDE) with location
IHU, decrement DE, HL and BC
16
11
10
101
101
101
000
Load location IDE) with location
IHU
21
~
11
10
101
111
101
000
16
I
11
10
101
100
101
000
11
10
101
110
101
000
11
01
101
000
101
100
IY
HL~HL-l
BC
~
BC - 1
LDDR
(DE) - IHU
DE - DE- 1
HL ~ HL - 1
BC .- BC· 1 until BC
LDI
IDE)·- IHU
DE-DE+l
HL - HL + 1
BC - BC - 1
Load location IDE) wl\h location
IHU, Increment DE, HL; decrement
BC
LDIR
IDE)·- IHU
DE ~ DE + 1
HL - HL + 1
BC ~ BC - 1 until BC
Load location (DE) with location
(HU. Increment DE, HL; decrement
BC and repeat until BC ~ a
NEG
A
~
0-- A
~
~
.
a
<.V •
21 if BC 10
16 if BC ~ 0
0
Negate ACC 12's complement!
402
V
I'PD780
SVMBOLIC
OPERATION
MNEMONIC
NOP
·OR r
OR n
A·- AV r
A· AV
n
DESCRIPTION
NO.
BVTES
NO.T
STATES
000
110
110
rrr®
110
Logical 'OR' of lac. (HLl and ACC
Logical 'OR' of lac. (IX + d) i\ ACC
7
19
OR IIV + d)
A·
AV IIY +d)
Logical 'OR' of loc. (IV + dl ,\ ACC
19
OTIR
1 until B
IC)· (HLl
B·- B
1
HL· HL+luntilB
=
10 110 110
11 all 101
10 110 110
dd ddd ddd
11 111 101'
10 110 110
dd e!dd ddd
to
Load output port (C) with content,
of location IHLl, decrement HL
and B, rapeat until B a
21 If B
16 il B
a
Load output pori (CI wilh location
(HLI, II"lcrnmellt HL, decfnmenl S,
nmeat until B
0
21 II B 4
16 If B C
a
1
HL
OPCODE
76 543 210
000
(IX + d)
(HLl
H
10
11
AV (HLl
(C)·
N
00
A·
HL·
FLAGS
P/V S
Logical 'OR' of Reg. rand ACC
Logical 'OR' of value nand ACC
A·
B· B
Z
No operation
OR IHLl
OR IIX +d)
OTOR
C
X
X
X
11
10
101
111
101
all
X
11
10
101
110
101
011
C
a
X
OUT IC) ••
(C)·
r
Load outpUI pori ICI With Req. I
12
11
01
101
OUT in). A
(n)·
A
Load OUIPUI pori 1111 With ACC
11
'1
010
all
OUTD
(C)· (HLl
B· B-1
HL· HL -- 1
Load output port Ie) With locatloll
(HL\, Increm(~nt HL unci
<.Iecwrnent B
16
11
10
101
101
101
all
Load output port (e) With loeatloll
(HL), Increment HL ilnd
16
1t
I 10
101
100
101
011
OUTI
(C)·
IHLl
B· B
HL·
1
HL. 1
x
x
001
dccrernen I B
-POP IX
IIXXH.· (SP + 1)
(SPI
L
Loae! I X With lOP 01 stack
14
11
11
all
100
101
001
POPIV
IV '(SP'll
H
IV L' ISPI
Load IV With lOP of Slilck
14
11
11
111
100
101
001
POP qq
qqH'- (SP + 11
qqL' (SP)
Load Reg. pall qq With top of stack
10
11
qqO
001@
PUSH IX
(SP
(SP
2)'
Load IX on to stnck
15
11
11
all
100
101
101
(SP
(SP
2)·
Load IY onlO s!
all
001
ddd
10
IJblJ
PUSH IV
11·
1)·
IX
L
IX
H
IV L
IV
H
2)· qqL
PUSH qq
(SP
ISP
RES b. r
Sb'
a
Reset Bit h of Reg. r
RE,S b.IHLl
SI>'
O,IHLl
Reset BII b of lac. IH Ll
15
RE'Sb,IIX+d)
Sb' O,IIX+d)
Resel Bit hof 10c.IIX + dl
23
RES b, (IY + d)
Sb'
Reset BII bof lac. (IY + dl
23
RET
PC ·
L
PC '
RET cc
If t:onUI tlon cc IS false
cant. else (PCL' (SP)
PCH' ISP t 11
H
1).
qqH
0, (IV' dl
ISPI
(SP + 11
RETI
~~ ~~~ ~!!$
Return from subroutine
Return from subroutine If COn(li110n
cc ,s true
10
5 If CC false
•
11 111
11 001
dd ddd
10 bbb
all
110
101
all
ddd
110
101
all
drfd
110
11
001
001
11 'cc . OOO®
11 " CC true
Return from Interrupt
14
11
01
101
001
101
101
RETN
Return from non-mask able interrupt
14
11
01
101
000
101
101
RL r
Rotate left through carry Reg. r
RL (HL)
Rotate left Ihrough carry lac. IHLl
RLIIX+dl
RL(IY+dl
RLA
4iHijJJ
m
r,lHLl,
(IX + d),
IIY + dl, A
ROlate lefl through carry loc. (IX' ell
Rotate left through carry lac. (IY ., dl
Rotate leli ACC through carry
403
11 001 011®
00 010
11 001 all
00 010 110
11 all 101
11 001 all
dd d(id ddd
00 010 110
11 111 101
11 001 all
dd ddd ddd
00 010 110
00
010
111
INSTRUCTION SET TABLE
(CONT.)
IlPD780
SVMBOLIC
OPERATION
MNEMONIC
DESCRIPTION
NO.
BVTES
NO. T
STATES
C
Z
FLAGS
PIV S
N
H
OPCODE
76 543 210
RLC (HLI
Rotate location (H LI left circular
2
15
I
i
P
i
0
0
11 001
00 000
RLC (IX + dl
Rotate location (IX + dl left circular
4
23
I
:
P
I
0
0
11 011 101
11 001 011
dd ddd ddd
00 000 110
Rotate location !IV + dl left circular
4
23
I
P
,
0
0
11
11
rid
00
111
001
ddd
000
RLC r
Rotate Reg. r left CIrcular
2
8
:
;
P
:
0
0
11
00
DOl 011@
000 rrr
RLCA
Rotate left circular ACC
1
4
:
0
0
00 000
III
Rotate digit left and right between
ACC and location (HU
2
18
·
· ··
I
0
11
01
101
101
101
111
11
00
11
00
11
11
dd
00
11
11
dd
00
001
011
001
011
011
001
ddd
011
111
001
ddd
011
011@
rrr
011
110
101
011
ddd
110
101
011
ddd
110
~
RLC (IV + dl
m - r, (HU,
(IX + dL (lY + dL A
A~(HLI
RLD
RR r
RR (HU
RR (IX + dl
L:[fjj:tP
RR (lY + dl
m
r, (HLI,
(IX + dl. (IV + dl. A
RRA
I
P
t
0
011
110
101
011
ddd
110
Rotate right through carry Reg. r
2
t
t
P
t
0
0
1 Rotate right through carry loc. (HU
'4
t
I
P
t
0
0
Rotate right through carry loc.
(IX + dl
6
i
I
P
t
0
0
Rotate right through carry loc.
(IY + dl
6
t
t
P
t
0
0
4
!
0
0
00
011
111
II
00
11
00
11
11
dd
00
11
11
'dd
00
001
001
001
001
011
001
ddd
001
111
001
ddd
001
011@
rr r
011
110
101
011
ddd
110
101
011
ddd
110
Rotate right ACC through carry
1
· ··
RRCr
Rotate Reg. r right circular
2
I
I
P
!
0
0
RRC (HU
Rotate loc. (HU right circular
4
I
I
P
I
0
0
RRC(IX+dl
Rotate lac. (I X + dl right circular
6
:
t
P
I
0
0
Rotate loc. (lY + dl right circular
6
i
I
P
!
0
0
0
0
00
001
111
0
0
11
01
101
100
101
111
11
ttt
111
10
11
nn
10
11
10
dd
11
10
dd
011
011
nnn
OIl
011
011
ddd
111
011
ddd
110
nnn
110
101
110
ddd
101
110
ddd
11
01
101
ssO
101®
010
00
110
111
11
11
001 011@
bbb 110
~
m - r,(HU,
(IX + dl. (lY + dl, A
RRC (IY + dl
· ··
Rotate right circular ACC
1
4
:
Rotate digit right and left between
ACC and location (HU
2
18
·
1)- PCH
(SP
(SP 21 - PCl
PCw 0, PCl' T
Restart to location T
1
11
SSC A, r
SSC A, n
A·-A
A· A
1
4
7
1
1
I
I
SSC A, (HLI
SSC A, (IX + dl
A· A
(HLI CY
A--A - (IX + dl CY
Subtract Reg. r from ACC w/carry
Subtract value n from ACC with
carry
Sub. loc. (HLI from ACC w/carry
Subtract loc. (I X + dl from
ACC with carry
SSC A, (lY + dl
A--A
SBC HL.
HL· Hl
RRCA
A~(Hll
RRD
RST t
55
r
n
CY
CY
(IY + dl
55
CY
CY
Subtract loc. (lY + dl from
ACC with carry
Subtract Reg. pair ss from Hl with
2
·· ·· ··
V
V
1
t
1
1
1
!
t
t
t
1
1
t
t
V
V
t.
!
19
t
t
V
t
1
t
15
t
1
X
CY - I
Set carry flag (C " 1 I
1
4
SET b. (HU
(HUb - 1
Set Bit b of location (HU
2
15
SET b, (IX + dl
(IX + dl
Set Bit b of location (IX + dl
4
23
404
:
7
SCF
'- 1
P
19
carry
b
:
!
V
t
t
· ·· ·· ·· · ·
·· ·· ··
1
0
0
rrr®
11 011 101@
11 001 011
dd ddd ddd
11 bbb 110
IlPD780
SYMBOLIC
OPERATION
MNEMONIC
NO. T
STATES
NO.
BYTES
DESCRIPTION
SET b, (ly + d)
(ly + d)b .-- 1
Set Bit b of location -(lY + d)
4
23
SET b, r
r
Set Bit b of Reg. r
2
8
b
'
1
SLA r
&-8--
SLAliX+d)
0
Z
N
H
SRA r
@--EJ
11
a
11
dd
00
11
11
dd
00
23
1
I
P
I
a
8
1
1
P
1
a
a
Shift loc_ (HL) right arithmetic
15
1
1
P
I
a
a
Shift loc. (IX + d) right arithmetic
23
I
I
P
1
a
a
Shift lac. (IV + d) right arithmetic
23
1
I
P
1
a
a
a
a
0
Shift loc. (IX + d) right logical
23
1
1
P
1
a
0
Shift loc. (IY + d) right logical
23
I
)
P
I
0
a
4
7
I
I
1
1
V
V
t
I
1
1
t
t
I
o~
m - r, (HL), (IX + d), (lY + d)
SRLIIY+d)
SUB r
SUB n
r
A· A
A ~A - n
Subtract Reg. r from ACC
Subtract value n from ACC
SUB (HL)
SUB (IX + d)
A 2
16
INTE
17
DBIN
Data Bus In
(output)
DBIN indicates that the data bus is in the input mode. This
signal is used to enable the gating of data onto the IlPD8080AF
data bus from memory or input ports.
18
WR
Write (output)
WR is used for memory WRITE or I/O output control. The data
on the data bus is valid while the WR signal is active (WR = 0).
19
SYNC
Synchronizing Signal
(output)
The SYNC signal indicates the beginning of each machine cycle.
20
VCC
VCC Supply
Voltage (Input)
+5V ± 5%
21
HLDA
Hold Acknowledge
(output)
HLDA is in response to the HOLD signal and indicates that the
data and address bus will go to the high impedance state. The
HLDA signal begins at:
T3 for READ memory or input operations.
The clock period following T3 for WRITE memory or
OUTPUT operations.
In either case, the HLDA appears after the rising edge of <1>1 and
high impedance occurs after the rising edge of 1/>2.
CD
··
22
1/>1
Phase One (input)
Phase one of processor clock.
23
READY
Ready (input)
The READY signal indicates to the IlPD8080AF that valid memory or input data is available on the IlPD8080AF data bus.
READY is used to synchronize the processor with slower memory
or I/O devices. If after sending an address out, the IlPD8080AF
does not receive a high on the READY pin, the IlPD8080AF enters
a WAIT state for as long as the READY pin is low. (READY can
also be used to single step the processor.)
24
WAIT
Wait (output)
The WAIT signal indicates that the processor is in a WAIT state.
28
VDD
VDD Supply Voltage
(input)
+12V ± 5%
Note:
VIH internal act,ive pull·up resistors will
be switched onto the data bus.
® Minus I-I designates current flow out of the device.
~ I supply I ~ T a
@
Ta
=;
-0.45%f c.
= 25°C, VCC = VDQ = VSS = OV, VBB = -5V.
CAPACITANCE
LIMITS
PARAMETER
Clock Capacitance
I nput Capacitance
Output Capacitance
SYMBOL
0/1
CIN
GoUT
MIN
TYP
MAX
17
6
10
25
10
20
UNIT TEST CONOITIONS
pF
pF
pF
fc = 1 MHz
Unmeasured Pins
Returned to Vss
410
"PD8080AF
AC CHARACTERISTICS
J,tPD8080AF
Ta '" O°c to +70°C. VDD = +12V ± 5%. VCC - +5V ± 5%. VBB = -5V ± 5%. VSS = OV. unless otherwise
specified.
.
LIMITS
PARAMETER
SYMBOL
MIN
MAX
UNIT
Clock Period
tCY'@)
0.48
2.0
50
IlSec
nsec
TYP
Clock Rise and Fall Time
tr.tf
0
>1 Pulse Width
t>1
60
nsec
>2 Pulse Width
t>2
220
nsec
Delay >1 to >2
tD1
0
nsec
Delay >2 to >1
tD2
70
nsec
Delay >1 to >2 Leading Edges
tD3
80
Address Output Delay From >2
tDA@
200
nsec
Data Output Delay From >2
tDD@
220
nsec
Signal Output Delay From >1.
or >2 (SYNC. WR. WAIT.
HLDA)
tDC@
120
nsec
DBIN Delay From >2
tDF @
140
nsec
Delay for Input Bus to Enter
Input Mode
tDI
tDF
nsec
Data Setup Time During >1 and
DBIN
tDS1
30
nsec
Data Setup Time to >2 During
DBIN
tDS2
150
nsec
Data Hold Time From >2 During
CBIN
READY Setup Time During >2
tDH
tiE
tRS
HOLD Setup Time to >2
INT Setup Time During >2
(During >1 in Halt Mode)
INTE Output Delay From >2
Hold Time from >2 (READY.
INT. HOLD)
Delay to Float During Hold
(Address and Data Bus)
Address Stable Prior to
WR
Output Data Stable From WR
CD
CD
200
nsec
tHS
140
nsec
tiS
120
nsec
tH
0
tAW@
tDW 2)
HLDA to Float Delay
tWF
Address Hold Time after DBIN
during HLDA
tAH@
Notes:
= 100 pF
CL = 50 pF
CL=50pF _ _
nsec
5
nsec
6
nsec
nsec
)
two
CL
nsec
120
WR to Float Delay
WR
nsec
nsec
120
tWA ~
tHF (
Address Stable from
2 + t>2 +'tf>2 + tD2 + tr>1
> tCY Min.
TYPICAL A OUTPUT DELAY VS.
A CAPACITANCE
+20
]
>-
~a
~
+10
0
~
~
::>
0
-10
1 Pulse Width
t>1
SO
>2 Pulse Width
t>2
145
nsec
Delay >1 to >2
tD1
0
nsec
Delay >2 to >1
t02
tD3
60
60
nsec
Delay >1 to >2 Leading Edges
Address Output Delay From >2
tOA®
150
nsec
Data Output Delay From >2
tOD®
1BO
nsec
Signal Output Delay From >1.
or >2 (SYNC. WR. WAIT.
HLDA)
tDC ®
DBIN Delay From >2
tDF ®
25
nsec
nsec
110
nsec
130
nsec
tDF
nsec
Delay for Input Bus to Enter
Input Mode
tDI
Data Setup Time During >1 and
DBIN
tDS1
10
nsec
Data Setup Time to >2 During
DBIN
tDS2
120
nsec
Data Hold Time From >2 During
DBIN
INTE Output Delay From >2
tDH
CD
CD
READY Setup Time During >2
tlE®
tRS
CD
200
nsec
nsec
nsec
HOLD Setup Time to >2
tHS
90
120
INT Setup Time During >2
(for all modes)
tiS
100
nsec
Hold Time from >2IREADY.
INT. HOLD)
tH
0
nsec
tFD
Address Stable Prior to WR
tAW®
5
nsec
Output Data Stable Prior to WR
tDW®
~
nsec
120
0
Output Data Stable From WR
two
WR to Float Delay
tWA
tHF ~
tWF (6
Address Hold Time after DBIN
during HLDA
tAH
HLDA to Float Delay
V
®
CL=100pF
CL = 50 pF
CL - 50 pF
nsec
Delay to Float During Hold
(Address and Data Bus)
Address Stable from WR
TEST CONDITIONS
nsec
(Z
(Z
nsec
CL = 100 pF: Address.
Data
CL
nsec
B
nsec
J!
nsec
-20
nsec
= 50 pF: WR.
HLDA.DBIN
Notes Continued:
@
The following are relevant when interfacing the IlPDBOBOAF to devices having V I H = 3.3V.
a. Maximum output rise time from O.BV to 3.3V = lOOns at CL = SPEC.
b. Output delay when measured to 3.0V = SPEC +60 ns at CL • SPEC.
c. If CL ,;. SPEC. add 0.6 ns/pF if CL > CSPEC. subtract 0.3 ns/pF (from modified delay) if
CL < CSPEC.
412
AC CHARACTERISTICS
JlPD8080AF-1
IlPD8080AF
AC CHARACTERISTICS
J,LPD8080AF-2
D
Ta = ODC to +70 C, VDD = +12V ± 5%, VCC = +5V ± 5%, VBB = -5V ± 5%, VSS = OV, unless otherwise
specified.
.
LIMITS
PARAMETER
Clock Period
Clock Rise and Fall Time
.pl Pulse Width
SYMBOL
MIN
tCY@
tr,tf
0.38
.p2 Pulse Width
t.pl
t.p2
Delay.pl to.p2
0
60
TYP
MAX
UNIT
2.0
50
JJsec
nsec
nsec
175
nsec
tDl
0
nsec
70
70
nsec
Delay .p2 to.pl
tD2
Delay.pl to.p2 Leading Edges
tD3
Address Output Delay From .p2
tDA@
175
nsec
Data Output Delay From.p2
tDD@
200
nsec
120
140
nsec
nsec
tDF
nsec
Signal Output Delay From .pl,
or.p2 (SYNC, WR, WAIT,
HLDA)
DBIN Delay From.p2
Delay for Input Bus to Enter
Input Mode
Data Setup Time During.pl and
DBIN
Data Setup Time to.p2 During
DBIN
Data Hold Time From.p2 During
DBIN
INTE Output Delay From.p2
READY Setup Time During.p2
HOLD Setup Time to.p2
tDC@
tDF @
nsec
25
CD
tDI
tDSl
tDS2
CD
tDH
tiE @
tRS
20
nsec
130
nsec
CD
200
nsec
nsec
nsec
tHS
90
120
tiS
100
nsec
tH
0
nsec
Address Stable Prior to WR
tFD
tAW@
-a
Output Data Stable Prior to WR
tDW@
6
Output·Data Stable From WR
Address Stable from WR
two
INT Setup Time During.p2
(for all modes)
Hold Time from.p2 (READY,
INT, HOLD)
Delay to Float During Hold
(Address and Data Bus)
HLDA to Float Delay
WR to Float Delay
tWF (3)
Address Hold Time after DBIN
during HLDA
tAH
Notes Continued:
®.
®
CL = 50 pF
CL = 50 pF
120
nsec
nsec
nsec
nsec
nsec
nsec
nsec
-20
CL = 100 pF: Address,
Data
. CL = 50 pF: WR,
HLDA,DBIN
nsec
tAW
Device
,IIPD8080AF
,IIPD8080AF-2
,IIPD8080AF-l
CL = 100 pF
nsec
0
tWA (£)
tHF (2
TEST CONDITIONS
2 tev - tD3 - t r.p2 - 140
2 tCY - t03 - t r.p2 - 130
2 tCY - tD3 - t r.p2 - 110
~~__D
__
'V_ic_e__1-___________
tD_W
________~
(j)
®
®
If not HLDA, two = tWA = tD3 + t r.p2 + 10 ns. If HLDA, two
tHF = tD3 + t r.p2 - 50 ns.
tWF = tD3 + t r.p2 - 10 ns.
413
= twA '" tWF.
"PD8080AF
PROCESSOR STATE
TRANSITION DIAGRAM
I
I
G)
I HOLD
I MODE
...
-_~
14------ --
I
I
I
.J
RESET HLTA
Notes:
I
2
INTE F/F is reset if internal INT F/F is set.
Internal INT F/F is reset if INTE F/F is reset.
If required, T 4 and T5 are completed simultaneously with entering
hold state.
414
TIMING WAVEFORMS
8
(Note: Timing measurements are made at the following reference voltages: CLOCK "'" = 8.0V,
"0" '" 1.0V; iNPUTS "'" = 3.3V. "0" = O.BV; OUTPUTS "'" = 2.0V, "0" = O.BV.)
4>,
4>2
A,.·Ao
_ _ _'":"":---x __ _
_
-
'OA'-
too· ...J
tOl
'. .
X ________ . . ::
0 .0
7 0
SYNC
.... "
----------------. ' toe
1-
OBIN
.. tOF
~
WR
---------tH
0'1
'RS •... -
WAIT
'H··
toe"
..
'.
:~ toc~--~
~.'
_
READY
I
tRS..•.
_
HOLD
tH
-
~
____
-, t HS ......
~-+-----
.
HLOA
-------------------------------------------------------------~------.--------INT
-
~--+-----------tIS~-
tH ----.
I...
Notes:
:.... -tIE ........
1
_.Jt"'_-_ _________
INTE
CD
@
@
®
®
®
Data in must be stable for this period during OBIN • T3. Both tOSl and tOS2 must be satisfied.
Ready signal must be stable for this period during T2 or TW. (Must be externally synchronized.)
Hold sigr'\al must be stable for this period during T2 or TW when entering hold mode. and during T3. T 4. T5 and TWH when in hold mode.
(External synchronization is not required.)
Interrupt signal must be stable during this period of the last clock cycle of any instruction in order to be recognized in the following instruction.
(External synchronization is not required.)
This timing diagram shows timing relationships only; it does not represent any specific machine cycle.
Timing measurements are made at the following reference voltages: CLOCK "I" = B.OV. "0" = 1.0V; INPUTS "I" = 3.3V; "0" =
OUTPUTS "I" = 2.0V. "0" =
o.av.
II
o.av;
"1::
."
C
00
o
00
o
l>
"T1
IlPD8080AF
The instruction set includes arithmetic and logical operators with direct, register,
indirect, and immediate addressing modes.
Move,load, and store instruction groups provide the ability to move either 8 or 16
bits of data between memory, the six working registers and the accumulator using
direct, register, indirect, and immediate addressing modes.
The ability to branch to different portions of the program is provided with direct,
conditional, or computed jumps. Also the ability to call and return from subroutines
is provided both conditionally and unconditionally. The RESTART (or single byte
call instruction) is useful for interrupt vector operation.
Conditional jumps, calls and returns execute based on the state of the four testable
flags (Sign, Zero, Parity and Carry). The state of each flag is determined by the result
of the last instruction executed that affected flags. (See Instruction Set Table.)
The Sign flag is set (High) if bit 7 of the result is a "1"; otherwise it is reset (Low). The
Zero flag is set if the result is "0"; otherwise it is reset. The Parity flag is set if the
modulo 2 sum of the bits of the result is "0" (Even Parity); otherwise (Odd Parity) it
is reset. The Carry flag is set if the last instruction resulted in a carry or a borrow out
of the most significant bit (bit 7) of the result; otherwise it is reset.
In addition to the four testable flags, the /JPD8080AF has another flag (ACY) that is
not directly testable . It is used for multiple precision arithmetic operations with the
DAA instruction. The Auxiliary Carry flag is set if the last instruction resulted in a
carry or a borrow from bit 3 into bit 4; otherwise it is reset.
Double precision operators such as stack manipulation and double add instructions
extend both the arithmetic and interrupt handling capability of the /JPD8080AF.
The ability to increment and decrement memory, the six general registers and the
accumulator are provided as well as extended increment and decrement instructions to
operate on the register pairs and stack pointer. Further. capability is provided by the
ability to rotate the accumulator left or right through or around the carry bit.
Input and output may be accomplished using memory addresses as I/O ports or the
directly addressed I/O provided for in the /JPD8080AF instruction set.
The special instruction group completes the /JPD8080AF instruction set: NOP, HALT
stop processor execution; DAA provides decimal arithmetic capability; STC sets the
carry flag; CMC complements it;, CMA complements the contents of the accumulator;
and XCHG exchanges the contents of two 16-bit register pairs directly"
INSTRUCTION SET
Data in the /JPD8080AF is stored as 8-bit binary integers. All data/instruction transfers to the system data bus are in the following format:
DATA AND INSTRUCTION
FORMATS
I D 71 D 61 D 51 D41 D 31D21D1 IDol
MSB
DATA WORD
LSB
Instructions are one, two, or three bytes long. Multiple byte instructions must be
stored in successive locations of program memory. The address of the first byte is used
as the address of the instruction.
One Byte Instructions
TYPICAL INSTRUCTIONS
Two Byte Instructions
Register to register, memory
reference, arithmetic or logical
rotate, return, push, pop, enable,
or disable interrupt instructions
1 0 71 D61 D51 D4 I D3 I D21 01 I DO I OP CODE
Immediate mode or I/O instructions
1 D71 D61 D51 D4 I D3 1D21 D1 IDa 1 OPERAND
Three Byte Instructions
ID71D61D51D41D3 ID21D1 IDol
@il D 6 ID 5 B I D3
1D21 D1 I DO
I
OP CODE
Jump: call or ,direct load and
store instructions
LOW ADDRESS OR OPERAND 1
I D 71 D 61 D 51 D 4 I D 3 ID21D1 IDol HIGH ADDRESS OR OPERAND 2
416
INSTRUCTION SET TABLE
IlPD8080AF
FLAGS
4
)0
INSTRUCTION CODE
MNEMONIC'
DESCRIPTION
07
06
05
D.
03
02
2
0,
DO
Clack
Cyclfl 3
g
°Nffi
y.
)0
~ "i
..
INSTRUCTION COOE'
MNEMONIC'
DESCRIPTION
. 07
De
06
D4
03
02
01
DO
0
0
1
Clock
eyel .. 3
LOAD REGISTER PAIR
MOVd.s
MOVM,s
MOVd.M
MVld,DB
MVI M,DS
Move regiuer 10regiSIQr
Old
d
d
Move register to memory
0
1
1
0
Move memory 10 register
Old
d
d
1
1
Move immediate 10 regisler
0
0
d
d
d
1
Move Immediate to memorY
a
0
1
1
0
1
s
LXI 8,016
load Immedi
SPA3
@
@
SPR3
XTHL
SPR3
@ SPW3 ®
DAD RP
PCR4
SPR3
@
SPA3
@
7
@
BCR3
7
INR M and DCA M
PCA4
G)
HLR3
HLW3 ~
10
MVIM
PCR4
Q)
PCR3 ~ HLW3-W
10
MVI A; ADI; ACI; SUI;
SBI; ANI; XAI; ORI; CPI
PCR4
CD
PCR3
@
MOV M.R
PCA4
CD
H LW3
Q)
EI;DI ADD R;
ADC A; SUB R;
SBB R; ANA R; XAA R;
OAA R; CMP A; RLC;
RAC; AAL; RAA;
DAA; CMA; STC;
CMC; NOP; XCHG
PCA4
Q)
OUT
PCA4
G)
PCA3 ( ) ABW3
10
PCR4
PCA3
(j)
10
HLT
PCR4
(j)
(j)
a>
a>
IN
PCX3
(g)
7
7
4
ABA3
7
Machine Cycle Symbol Definition
®-j Status word defining tvpe of machine
TTT =1 "'". ,...
xx
V Z
XXl H L = Regiltars Hand L used as eddre..
"'M W~ IINfAI
Valid Address to Valid Data In
FiEA'r5
'RO
IINTAI
350
'60
515
300
I~
~ (or INTAlto Valid Data
Data Hold Time After
Input
Training Edge of READ to Ae·Enablmg
90
tRAE
of Address
Address (AS,A1S' Valid After ContrOl
50% DC
Note:
STATUS OUTPUTS
Appllas only to T2 ..ate. (8 n. Into T3)
Signal at "POS284 shown for refaranca only.
439
70
D
f.tPD8086
TIMING WAVEFORMS
Minimum Complexity
Systems
®
ClK (8284 Outputl
MJio
r--
ALE
I
ROY (8284 Inputl
@®
READ CYCLE
(WR.
CD
TCHCTV -
INTA = VOHI
OTJR
440
",POSOS6
TIMING WAVEFORMS
Minimum Complexi~
Systems (Con't.) @
CLKI8284 0UTPUTI
M/m
ALE
WRITE CYCLE! AD15:::
ack. Thef'P08086 local AODR/Oata Bus is
floating during both INTA cycles. Control signals shown for second INTA
cycle.
Signals at ",P08284 are shown for reference only.
®
All timing measurements are made at 1 .5V unless otherwise noted.
441
IlPD8086
TIMING WITH .PB8288 BUS CONTROllER
TIMING REQUIREMENTS
JJ,PD8086·2 IPreliminary)
.PDS086
PARAMETER
TEST
CONOITIONS
SYMBOL
MIN
MAX
MIN
MAX
TClCl
200
500
125
500
elK Low Time
TClCH
(2/3 TClCLI-15
(2/3 TClCl) -15
elK High Time
TCHCl
(1/3 TClCl) +2
11/3 TClCLI +2
eLK Rise Time
TCH1CH2
10
10
From 1.0V to 3.5V
CLN Fall Time
TCL2CLI
10
10
From 3.5V to 1.0V
Data in Setup Time
TDVCL
Data in Hold Time
TCLDX
10
10
ROY Setup Time into J.lPD8284
TR1VCL
35
35
ROY Hold Time into ,uPD8284
TCLR1X
READY Setup Time into IJPDB086
TRYHCH
12/3 TCLCLI-15
12/3 TCLCL) -15
TCHRYX
30
20
READY Inactive to elK
TRYLCL
-8
-B
Setup Time for Recognition
TINVCH
30
15
RQ/GT SetuP Time
TGVCH
30
15
AQ Hold Time into IJPD8086
TCHGX
40
30
Input Rise Time
TILIH
20
From O.BV to 2.0V
Input Fall Time
TIHIL
12
From 2.0V to O.BV
elK Cycle Period - J,JPDB086
DEN
(
______________________- J
443
IlPD8086
TIMING WAVEFORMS
Maximum Mode
System Using
IlPB8288.-Q.ontroller
(Con't.) Q)
TW
ClK
S2.Si.!O (EXCEPT HALT)
WRITE CYCLE Q)
DEN
8288 OUTPUTS
INTA CYCLE
® @)
AMi'«: OR AiOWC
CD
AO'5-AOO
(SEE NOTES 3 & 4)
8288 OUTPUTS
@®
INTA
DEN
SOFTWARE HAlT(DEN· VOL; RD. MAi5C. iORC. MWfC.~. ~.
AiOWC.
V OH )
mn..
\
NOTES:
®
MWTC, AMWC,IORC,IOWC. AIOWC,INTA _ DEN) . . tho oct... """
82BB CEN.
All liming _ r _ n l l ... ..-It 1.IIV ....... otlWWlto_.
SIItUIInlCt'"In IIItI lUll prior to T...
444
IlPD8086
ASYNCHRONOUS SIGNAL
RECOGNITION
NMI
INTR
SIGNAL "':_ _ __
"i"EsT
NOTE:
CD
Setup requirements for asynchronous signals only to guarantee recognition
at next elK.
BUS LOCK SIGNAL TIMING
REQUEST/GRANT SEQUENCE
TIMING*
. .O'e·. .Oo
1-1- - - - - - - - - - _ 1 :
A'r,"f_""eJS3
~.Im: 1-1----------- - - - - 1iII1S7
NOTE:
CD
(j)
The coprocessor may not drive the buses outside the region shown without
risking contention.
*for Maximum Mode only
445
",PD8086
HOLD/HOLD
TIMING*
ACKNOWLEDGE
AD16-ADO
I
~/S~/iO.
'
~~/Ss-Al;VS3.
/A.WR.DEN
-for Minimum Mode only
PACKAGE
IlPD8086D OUTLINE
Cerdip
.~
J-r!
.=ct~
;
~5'24
.,~0.25'" 0.05
rr
0_15°
0.5." 0.1
8086DS-REV1-8 2-CAT
446
NEe
JAPD8088
HIGH·PERFORMANCE
8·BIT MICROPROCESSOR
NEe Electronics U.S.A. Inc.
Microcomputer Division
Pin Identification
De.crlptlnn
'The ",PD8088 is a powerful 8-bit microprocessor that is
software-compatible with the ",PD8086. The ",PD8088
has the same bus interface signals as the ",PD8085A,
allowing it to interface directly with multiplexed bus
peripherals. The ",PD8088 has a 20-bit address space
which can be divided into four segments of up to 64K
bytes each.
Feature.
0 8-bit data bus interface
0 16-bit internal architecture
0 Addresses 1 M-byte of memory
0 Software-compatible with the 8086
0 Provides byte, word, and block operations
0 Performs 8- and 16-bit signed and unsigned arithmetic in binary and decimal
0 Multiply and divide instruction
0 Directly interfaces to 8155, 8355, and 8755A mUltiplexed peripherals
0 40-pin DIP
No.
N.me
·rmbol
GND
Ground
2-8,
35-39
A19- A8
Most significant
address bits
ADJ-ADO
Address/Data bus Multiplexed address and data bus. 8-blt perlpherals tied to these blta use Ao to condition chip
select functions. These lines are trl-state durIng
hold and Interrupt acknowledge states.
17
NMI
Non-maskable
Interrupt
This edge-triggered Input causes a type 2 Interrupt. The proceaeor uses a lookup table for vectoring Information.
18
INTR
Interrupt request
This Is a level-triggered Interrupt aampled on the
last clock cycle of each Instruct/on. A lookup
table Is used for vectoring. INTR can be masked
by software by resetting the Interrupt enable bit.
19
CLK
Clock
The clock 18 a 1/3 duty cycle Input providing
basic timing for the proceaeor and bus
controller.
21
RESET
Reset
This active high signal must be high for 4 clock
cycles. When It returns low, the procesaor
restarts execution.
22
READY
Ready
An acknowladgement from memory or 110 that
data will be transferred. Synchronization la done
by the I'PD8284 clock generator.
23
TEST
Test
Thla Input la examlnad by the "WAIT" Instruction and If low, execution continues. Otherwise
the processor walta In an "Idle" state. Synchronized by the proceasor on the leading edga of
CLK.
24
INTA
Interrupt
Acknowledge
This Is a read strobe for reading vectoring Informallon. During T2' T3' and TW of each Interrupt
acknowledge cycle It Is low.
25
ALE
Address Latch
Enable
Used with the I'PD8,282/8283 latches to latch the
addreas during T 1 of any bus cycle.
"9-16
Pin Configuration
24,25 QS1, QSO Queue Status
Min
Mode
GND
A14
A13
A15
A16/S3
A17/S4
A11
A18/S5
m
A8
MN/MX
AD7
AD
HOLD
(lm/errO)
HLDA
(liQ/GTt)
AD4
WR
(LOCK)
AD3
IO/ll
(§i)
AD2
DT/I!!
ADt
DEN
(Si)
(SO)
ADO
ALE
(QSO)
NMI
INTA
TEST
(QS1)
GND
READY
RESET
(Max Mode) Tracks the Internal I'PD8088 Inatructlon queue.
This la the output enable for the I'PD8286/8287
' tranacelvere. It Ie active low during memory and
110 access and INTA cycles.
DTTR
Data Transmit/
Receive
Controls the direction of data flow through the
transceivers.
28
IO/M
IIO/Memory
Status
Separates memory access from 110 access.
WR
Write
The processor Is writing to memory or 11O,
depending on the state of the IO/M line.
'29
LOCK
Lock
(Max Mode) This output Is set by the lock Instructlon to prevent other system bUB mastera from
gaining control.
30
HLDA
Hold
Acknowladga
A response to the HOLD Input, causing the
processor to trl-state the local bus. The bus
becomes active one cycle after HOLD returns
low.
31
HOLD
Hold
When another device requests the local bus,
HOLD Is driven high, causing the I'PD8088 to
Issue a HLDA.
30,31
RQ/GTO
ImiGT1
Request/Grant
(Max Mode) Other local bus masters can force
the processor to rebase the local bus at the end
of the current bus cycle.
32
mJ
Read
Depending on the state of the 'iO"/M line, the
processor Is reading from memory or 11O.
MN/MX
Minimum/
Maximum
This Input tells the processor In which mode It
Is to be used. This affects some of the pin
descriptions.
,33
447
Most significant bits for memory operations,
27
29
(HIGH)
AD6
AD5
ClK
Data Enable
At9/S6
A9
INTR
DEN
VCC
A12
A10
26
{ Max}
Mode,
Function
1,20
34
SSO
Status Line
Equivalent to So In Max Mode.
26-28
~-S2
Status Outputs
(Max Mode)
35-38
S3-S6
Status Outputs
Thesll_outputs from the proceaeor are used by
the ~PD8288 to generate bus control signals.
40
VCC
Power Supply
5V power Input.
m
•
J-lPD8088
Block Diagram.
AC Characteristics
Minimum Mode Timing Requlr.ment.
= OOCto + 70°C, VCC +5V :I: 10%
=
T.
Parameter
Instruction
Stream Byte
,Queue
Interf~~: ~---=""-----l
Unltl-----!::::.----1
AH
BH
CH
Execution I---"D::..:H'---,,L-!=-=----l
Unltl-_~~-___l
01
Symbol
Min
Typ Max
200
500
Unit
ClK Period
tClCl
ClK low Time
tClCH
(213tClCU -15
nB
ClK High Time
tCHCl
(lf3tClCl) + 2
ns
Te.t Conditions
nB
ClK Rise Time
tCH1CH2
10
ns
1.0Vto 3.5V
ClK Fall Time
tCL2Cll
10
nil
3.5V to 1.0V
Data In Setup Time
tDVCl
30
ns
Data In Hold Tlma
tClDX
10
ns
ROY Setup Time
I'PD8284
tClR1X
TrP II•• Unite THt Con4Mlone
tClMl
n.
ns
na
AddreBII Float Delay
tCLAZ
na
StatuB Valid to ALE
High (j)
tSVlH
15
na
tSVMCH
15
ns
80
ns
READY Setup Time
Into "PD8088
tRYHCH
(2/3tClCLl-15
na
Statua Valid to MCE
High (j)
READY Hold Time
Into "PD8088
tCHRYX
30
nl
ClK low to ALE
Valid ~
tCllH
15
ns
na
ClK low to MCE
High
tclMCH
15
n.
nl
ALE Inactive '
Delay (j)
tCHll
15
n.
MCE Inactive
Delay (j)
tClMCl
15
n.
Data Valid Delay
tClDV
15
Data Hold Time
tCHDX
10
Control Active
Delay (j)
tCVNV
Control Inactive
Dela~ ~
tCVNX
READY Inactive to
ClK @
Setup Time for
::,~~TR,
RQ/GT Setup Tlma
RQ Hold Time Into
I'PD8088
tRYlCl
tlNVCH
-8
30
tGVCH
30
tCHGX
40
All signals switch between VOH and VOL unless otherwise specified.
(I) ROY is sampled near the end of T2, T3, TWAIT to determine if TWAIT machine states are
inserted.
Two INTA cycles run back-to-back. The ",P08088 local Addressl Data bus floats during both
INTA cycles. The control signals shown are for the second INTA cycle.
(§) Signals at the ",P08284 are shown for reference.
(j) All timing measurements are taken at 1.5V unlesS otherwise specified.
451
",PD8088
Timing Waveforms (Cont.)
Maximum Mode System Bus Timing
(using 8288 Bus ·Controller)
CLK
~~-CJ
VCH~
~
K---.-;t'VcL ---.I
tct.Av
f--
HE'
r~f\--I~
1 tcHCL
I tCLCH
)
080,08 1
1----
~H
-
tCHSV
)
--
rill; VIII®
----- 1\
~
--111:=
tCLLH
ALE 1ICV
Clock Active (High, Low)
<1>0
Clock Rise Time
r
20
ns
Clock Fall Time
f
20
ns
AO, CS, DACK Set Up Time to RD !-
TAR
0
ns
·TRA
0
ns
TRR
250
AO. CS, DACK Hold Time from
J!rn
t
RD Width
Data Access Timefrom RD
~
ns
40
ns
TRD
DB to Float Delay Time from RD t
TbF
20
200
ns
CL '" 100 pf
100
ns
CL"'100pF
TAW
0
ns
AO, CS, DACK Hold Time to WR t
TWA
0
ns
WR Width
TWW
250
ns
Data Set Up Time to WR t
TOW
150
ns
Data Hold Time from WR t
TWO
5
INT Delay Time from RD t
TRI
600
ns
INT Delay Time from WR t
TWI
500
ns'
AO, CS, DACK Set Up Time to WR
~
ORO Cycle Time
ORO Delay Time from DACK
TMCY
~
ns
13
,",S
200
.TAM
TCWidth
TTC
Reset Width
TRST
1
ns
.tI>CY
14
tl>CY
20r~
WCK Cycle Time
TCY
WCK Active Time (High)
TO
350
ns
WCK Rise Time
Tr
20
ns
WCK Fall Time
Tf
20
ns
Pre-8hift Delay Time from WCK t
TCp
20
100
ns
WDA Delay Time from WCK t
TCD
20
100
ns
ROD Active Time (High)
TROD
40
,",S
1 or 2
80
250
TWCY
TROW
Window Hold Time to/from ROD
'.
ns
MFM =0
2.0
Window Cycle Time
MFM"'O
MFM -1
,",5
1.0
16
ns
MFM=1
TWRD
USO,1 Hold Time to i!niJ/SEEK t
TUS
12
,",5
SEEK/RW Hold Time to LOW CURRENT/
DIRECTION t
TSD
7
,",s
LOW CURRENT/DIRECTION Hold Time to
FAULT RESET/STEP t
TDST
1.0
,",S
USo 1 Hold Time from FAULT
RES'ET/STEP t
TSTU
5.0 .
,",S
STEP Active Time (High)
TSTP
STEP Cycle Time
TSC
FAULT RESET Active Time (High)
TFR
Write Deta Width
USO,1 Hold Time After SEEK
TWDD TO-50
16
TSU
Seek Hold Time from DIR
TDS
30
,",5
DIR Hold Time after STEP
TSTD
24
,",S
TIDX
Index PulMiWidth
-
6.0
33
10
800
'WR !-. Delay from ORO
TMW
250
WE or RD Response Time from ORO t
TMRW
CY must be 4 mHz_
462
"PD765A
AC TEST CONDITlo'N
INPUT/OUTPUT
CLOCK
2.4V
O.·16V
AC TESTING
Inputs are driven at 2.4V for a logic "1" and 0.45V for a logic "0." Timing measurements are made at 2.0V for a logic "1" and O.BV for a logic "0."
Clocks are driven at 3.0V for a logic "1" and 0.3V for a logic "0." Timing measurements are made at 2.4V for a logic "1" and 0.65V for a logic "0."
TIMING WAVEFORMS
PROCESSOR WR ITE OPERATION
PROCESSOR READ OPERATION
AO.
Cs. DACK
:J(
TAR~
)(,,____
-....t
:--TRA
1
-I
'--TDF
,__
1t
RO~TRR _ _
I.----'
TRD
DATA
jz
I
'
-------1-
!~------
I4-TRI-.J
INT - - - - - - - - - - - - - - - - - -________~~
INT
"-I
CLOCK
DMA OPERATION
Cll<
----"po
ORO
FDD WRITE OPERATION
---1 t---To
WRITE CLOCK
I
WR
_ _ _ _-.I
,
I
I
I
1
t---=- T CY--I
1 1-1 '-- TF
,I
TR __: : -
I
WRITE ENABlE.-J
I
I II
- - t t--Tcp
PRESHIFT 0 OR
x::
"'______X,,____
~---'!!IIt.¥11
~-----"";T"=;r
- - , I.o!.-Tco
I
I
WRITE DATA
1-.;;..,---I
PRESHIFT 0
PRESHIFT 1
NORMAL
0
0
lATE
EARLY
0
1
1
0
1
INVALID
1
463
OR RO
..J:
IlPD765A
TIMING WAVEFORMS
(CONT.)
SEEK OPERATION
USO.l
RW/SEEK
=2fu~
-X
---I
tSOt--
DIRECTION
.,*------
~
.~------+-:- _
STABLE
_hoSr--
-----
X"--~:
-----X
tOST----I
1
t---~TU---l
STEP _ _ _ _ _nS_T_O_ _ _
tSTP---!
I..
..."l~
~
1
.1
tsc
FLT RESET
I
.
I
INDEX
~
FAULT RESET = .
FILE UNSAFE RE'SET
:
I
- - - ' TFR ~
I TIDX 1 1 TIDX I
~~
FDD READ OPERATION
REAODATA~~____________~~~I~__________
--t
I
I--TRDD
I
READDATAWINDOW _ _ _ _ _ _ _
Note: Either polarity data window is valid.
I-TwRD-i
I
I
~X
I
I..
----n--I
I
t
I
I
.1
TWCY
RESET
TERMINAL COUNT
TC
'--TRDW~
H
RESET
I--TTC
----I!
~
---l
'-- TRST
The ~PD765 contains two registers which may be accessed by the main system processor; a Status Register and a Data. Register. The a-bit Main Status Register contains the
status information of the FOe, and may be accessed at any time. The 8-bit Data
Register (actually consists of several registers in a stack with only one register presented to the data bus at a time), which stores data, commands, parameters, and FDD
status information. Data bytes are read out of, or written into, the Data Register in
order to program or obtain the results after a particular command. The Staws
Register may only be read and is used to facilitate the transfer of data between the
processor and ~PD765.
The relationship between the Status/Data registers and the signals RD. WR, and AO
is shown below.
AO
Frn
WR
0
0
0
0
1
0
0
0
1
0
0
0
1
0
1
1
1
1
FUNCTION
Read Main Status Register
Illegal
Illegal
Illegal
Read from Data Register
Write into Data Register
464
I NTE RNAL REG ISTERS
IlPD765A
INTEFlNAL REGISTERS
(CaNT.)
The bits in the Main Status Register are defined as follows:
BIT NUMBER
NAME
SYMBOL
DBO
FDD 0 Busv
DOB
OBI
FDD 1 BusV
DIB
DB2
FDD 2 BusV
D2B
DB3
FDD 3 BusV
D3B
DB4
DB5
FDC BusV
Execution Mode
CB
EXM
DBS
Data Input/Output
010
DB7
Request for Master
RQM
DESCRIPTION
FDD number 0 is in the Seek mode. If any of the bits is set FDC will not accept
read or write command.
FDD number 1 is in the Seek mode. If any of the bits is set FDC will not accept
read or write command.
FDD number 2 is in the Seek mode. If any of the bits is set FDC will not accept
read or write command.
FDD number 3 is in the Seek mode. If any of the bits is set FDC will not accept
read or write command.
A read or write command is in process. FDC will not accept any other command.
This bit is set orilV during execution phese in non-DMA mode. When DB5 goes
low, execution phase has ended, and result phase was started. It operates only
during NON-DMA mode of operation.
Indicates direction of data transfer between FDC and Data Register. If 010 = "I"
then transfar Is from Data Register to the Processor. If 010 = "0". then transfer
is from the Processor to Data Register.
Indicates Data Register is ready to send or receive data to or from the Processor.
Both bits DID and RQM should be used to perform the hand-shaking functions of
"ready" and "direction" to the processor.
The DID and ROM bits In the Status RegISter indicate when Data is ready and· '" which direction data Will be transferred on the Data
Bus. The max time between the last RiS or VA during command or result phase and 010 and ROM getting set or reset is 12 I'~or
this reason every time Main Status Register is read the CPU should wait 121's. The max time from the trailing edge of the la.t RD in
the result phase to when DB4 (FDC Bu.vl goa. low i. 121ls.
Out FDC and Into Processor
Data In/Out
(0101
I
Ready
Request for Master
(ROMI
I
Out Processor and Into FOci
,4".
_II
r-t---1
I~.,~
Ready
I I
I
~
h-I I
r1; h
~I
I
J-+J
I
I
I
:
I
~~.:
I
RD~'
I
I
I A I
I
B
I
I
A
I
I
IBI A I
C
I
D I
I
C
II
10 IBI
I
A I
Notes:.~ - Data rl:gis,ter ready to be written into by processor
rID [ill[QJ -
COMMAND SEQUENCE
Data regIster not ready to be written into by processor
Data register ready for next data byte to be read by the processor
Data register not reJdy for next data byte to be read by processor
The J,LP0765 is capable of performing 15 different commands. Each command is initiated by a
multi-byte transfer from the processor, and the result after execution of the command may also
be a multi-byte transfer back to the processor. Because of this multi-byte interchange of information between the J,LP0765 and the processor, it is convenient to consider each command as
consisting of three phases:
Command Phase:
TheFOC receives all information required to perform a particular
operation 'from the processor.
Execution Phase:
The FOC performs the operation it was instructed to do.
Result Phase:
After completion of the operation, status and other housekeeping
information are made available to the processor.
465
flPD765A
INSTRUCTION SET
I
DATA BUS
PHASE
RIW
I
D7
D6
D6 D4
D3 D2
D1
DATA BUS
REMARKS
Dol
PHASE
RIW
I
D7
D6
W
MT
MF SK
X
W
X
0
X
W
W
W
W
W
W
W
X
1
1
HD
US1
Command
Command Codes
USO
C
H
A
N
EOT
GPL
DTL
0
MF
SK
0
0
0
1
X
X
X
X
HD
US1
W
W
MT
MF SK
X
X
header on Floppy Disk.
W
W
W
W
W
W
W
to Command execution
Execution
Data-transfer between t he
FDD and main-system. FOC
read, all data field.
from index hole ·to
Result
STO
ST 1
S'r 2
Sector 10 information after
Command execution
HD US1
Command Codes
Command
to Command execution. The
4 bytes are commanded against
header on Floppy ~isk.
Data-transfer between the
FDD and main-system
ST 0
ST 1
ST 2
C
Sector I D information after
Command execution
MT
MF
0
0
X
X
X
1
X
W
W
W
W
W
W
W
MF
0
0
X
X
X
Commands
HD US1
. Command Codes
Sector 10 information prior
to Command execution. The
4 bytes are commanded against
header on Floppy Disk.
Execution
HD US1
USO
The first correct 10 Information
on the Cylinder is stored in
Data Aegister
A
A
A
ST 0
ST 1
ST 2
C
H
A
N
W
W
0
MF
0
0
X
X
X
X
W
W
W
W
USO
H
A
N
EOT
GPL
DTL
X
Status information after
Command execution
Sector 10 information read
during Execution Phase from
Floppy Disk
FORMAT A TRACK
Command
WRITE DATA
W
W
0
Status information after
Command execution
A
N
Command
W
W
Execution
Result
Execution
A
Sector 10 information after
Command execution
READ 10
USO
A
N
EOT
GPl;
DTL
Ear .
Status information after
Command execution
H
A
N
Sector 10 information prior
Result
Command Codes
Command Bxecution
0
X
REMARKS
USO
Status information after
0
X
I
A
N
EOT
GPl:
DTL
AEAD DELETED DATA
Command
Dn
Sector 10 information prior
W
W
W
W
W
W
W
Sector 10 information prior
to Command execution. The
4 bytes arB commanded against
STO
ST 1
ST 2
C
H
A
N
W
W
Data-transfer between the
F DO and main-system
A
A
D,
READ A TRACK
Execution
Result
D3 D,
D6 D4
READ DATA
Command
CD@
Command Codes
HD
US1
USO
N
SC
GPL
0
Bytes/Sector
Sectors/Track
Gap3
Filler Byte
STO
ST 1
ST 2
C
Status information after
Command execution
FOe formats an entire track
Execution
Result
In this case, the 10 information
has no meaning
A
N
Data-transfer between the
main-system and FDD
SCAN EaUAL
Result
A
A
A
A
A
STO
ST 1
ST 2
C
H
A
N
Status information after
Command execution
Command
Sector 10 information after
Command execution
W
W
W
W
W
W
W
W
W
MT
MF
0
0
X
X
X
0
0
HD
US1
Command Codes
C
If
A
N
EOT
GPL
DTL
Not.:
CD
Sector 10 information prior
to Command execution. The
4 bytes are commanded against
header on Floppy Disk.
1
W
X
X
0
X
C
H
A
N
EOT
GPL
STP
0
0
HD US1
1
Command Code.
USO
Sector 10 information prior
to Command execution
STO
ST 1
ST 2
C
H-----
Data-compared between the
F DO and main-system
Aesult
A
A
A
Status information after
Command execution
Sector 10 information after
Command execution
A
N
Symbol. used in thl. table ere described at the end of thi. section.
® AO should equal binary 1 for all operations.
@)
SK
X
Execution
Data-transfer between the
FOD and main-system
A
A
A
MF
X
USO
Execution
Result
MT
W
W
W
W
W
W
W
WRITE DELETED DATA
Command
W
X - Don't care, usually made to equal binary O.
466
STO
ST 1
ST 2
C
H
Status information after
Command execution
Sector 10 information after
Command execution
INSTRUCTION SET
(CONT.)
PHASE
R/W
.1
I
IlPD765A
I
DATA BUS
07
08
Os 04 ·03· D2
I
Dol
D1
PHASE
REMARKS
R/w
I
06
Os 04
W
MT
W
MF
SK
I
X
X
X
w
HD
USI
W
W
W
Sector 10 information prior
Command execution
X
0
0
X
X
Command
STO
ST I
ST 2
C
H
R
N
W
0
0
0
MT
W
X
W
W
W
W
W
W
W
MF
SK
I
X
X
usa
I
0
0
0
Command Codes
Status information at the end
of s.. k-operation ebout the FOC
SPECIFY
Command
Status Information after
Command execution
W
0
W
W
-SRT
HLT
W
0
0
W
X
X
0
0
III
•
Command Codes
0
HUTNO
....
SENSE DRIVE STATUS
Soctor 10 Information after
Command execution
Command
HD USI
HD USI
usa
Status Information about FDD
SEEK
1
C
H
R
N
EOT
GPL
STP
Command Codes
X
ST3
Rasult
1
X
USI
STO
PCN
SCAN HIGH OR EQUAL
W
Command Codes
I
0
Head retracted to Track 0
Re.ult
FOD and main-system
Command
REMARKS
Dol
Execution
Data-compared between the
R
R
R
R
R
R
R
°1
SENSE INTERRUPT STATUS
Execution
Result
0
X
W
w
usa
C
H
R
N
EOT
GPL
STP
W
W
W
'Command
Command Codes
X
03 02
RECALIBRATE
SCAN LOW OR EQUAL
Command
J
DATA BUS
07
Command Code.
Command
usa
Soctor 10 Information prior
Command execution
W
0
0
W
X
X
W
: Command Codes
HD USI
USO
NCN
Execution
Head is positioned over
proper Cylinder on
Diskette
INVALID
Dat8~ompared
between the
F DO and main-system
Execution
Result
R
R
STO
STI
ST2
H
R
N
COMMAND SYMBOL
DESCRIPTION
Status Information after
Command execution
Command
Result
W
_ _ _ Invalid Codes - -_ _
I nvalld Command Code.
(NoOp - FDC goes into
Standby State)
ST 0
ST 0
z
80
(16)
Sector 10 Information after
Command execution
SYMBOL
DESCRIPTION
NAME
AO
Address Line 0
AO controls selection of Main Status Register (AO = 0) or Data
R·egister (AO = 1 )
C
Cylinder Number
C stands for the current/selected Cylinder (track) number 0
through 76 of the medium.
0
Data
o stands for the data pattern which is going to be written into a
Sector.
07- 0 0
Data Bus
a-bit Data Bus, where 07 stands for a most significant bit, and
DO stands for a least significant bit.
DTL
Data Length
When N is defined as 00, DTL stands for the data length which
users are going to read out or write into the Sector.
EOT
End of Track
EOT stands for the final Sector number on a Cylinder. During
Read or Write operation FDC will stop date transfer after a sector
# equal to ~OT.
GPL
Gap Length
GPL stands for the length of Gap 3. During Read/Write commands
this value dete~mines the number of bytes that VCOs will stay low
after two CRC bytes. During Format command it determines the
size of Gap 3.
H·
Head Address
H stands for head number 0 or 1, as specified in 10 field.
HD
Head
HD stands for a selected head number 0 or 1 and controls the
polarity of pin 27. (H = HD in all command words.)
HLT
Head Load Time
H LT stands for the head load time in the FDD (2 to 254 ms in
2 ms increments).
HUT
Head Unload Time
HUT stands for the head unload time after a read or write operation has occurred (16 to 240 ms in 16 ms increments).
MF
FM or MFM Mode
If MF is low, FM mode is selected, and if it is high, MFM mode is
selected.
MT
Multi-Track
If MT is high, a multi-track operation is to be performed. If MT = 1
after finishing Read/Write operation on side 0 FDC will automatically start search ing for sector 1 on side 1.
467
"PD765A
SYMBOL
DESCRIPTION
NAME
N
Number
N stands for the number of data bytes
written in a Sector.
NCN
New Cylinder Number
NCN stands for a new Cylinder number,
which is going to be reached as a result of the
Seek operation. Desired position of Head.
NO
Non·DMA Mode
NO stands for operation in the Non-DMA Mode.
PCN
Present Cylinder
Number
PCN stands for the Cylinder number at the compietion of SENSE INTERRUPT STATUS
Command. Position of Head at present time.
R
Record
R stands for the Sector number, which will
be read or written.
RIW
ReadlWrite
RIW stands for either Read (R) or Write (W)
signal.
SC
Sector
SC indicates the number of Sectors per
Cylinder.
SK
Skip
SK stands for Skip Deleted Data Address Mark.
SRT
Step Rate Timo
SRT stands for the Stepping Rate for the FOD.
(1 to 16 ms in 1 ma increments.! Stepping Rate
epplies to all drives, (F ,. 1 ms, E - 2 ms, etc.).
STO
ST 1
ST2
ST3
Status
Status
Status
Status
ST 0-3 stand for one of four registers which
store the status information after a command
has been executed. This information is
available during the result phase after command
execution. These registers should not be confused with the main status register (selected by
AO = 0). ST 0-3 may be read only after a command has been executed and contain informatior
relevant to that particular command.
0
1
2
3
During a Scan operation, if STP = 1, the data in
contiguous sectors is compared byte by byte
with data sent from the processor (or DMA);
and if STP = 2, then alternate sectors are read
and compared.
STP
USO, US1
COMMAND SYMBOL
DESCRIPT'ION (CONT.)
US stands for a selected drive num ber 0 or 1.
Unit Select
SYSTEM CONFIGURATION
DB()'7
AO
MeMR
DB()'7
iOR
MmW
loW
WR
AD
cs
cs
INT
HRO
RESET
READ
HLDA
ORO
IIP08257
CON~~;LLER
i5ACK
TC
TERMINAL
COUNT
468
IlPD765A
PROCESSOR I NTE RFACE During Command or Result Phases the Main Status Register (described earlier) must be
read by the processor before each byte of information is written into or read from the
Data Register. After each byte of data read or written to Data Register, CPU should
wait for 12 J.l.s before reading MSR. Bits D6 and D7 in the Main Status Register must
be in a 0 and 1 state, respectively, before each byte of the command word may be
written into the J.l.PD765. Many of the commands require mUltiple bytes, and as a
result the Main Status Register must be read prior to each byte transfer to the J.l.PD765.
On the other hand, during the Result Phase, D6 and D7 in the Main Status Register
must both be l's (D6 = 1 and D7 = 1) before reading each byte from the Data Register.
Note, this reading of the Main Status Register before each byte transfer to the J.l.PD765 .
is required in only the Command and Result Phases, and NOT during the Execution
Phase.
During the Execution Phase, the Main Status Register need not be read. If the J.l.PD765
is in the NON-DMA Mode, then the receipt of each data byte (if J.l.PD765 is reading
data from FDD) is indicated by an Interrupt signal on pin 18 (INT = 1). The generation
of a Read signal (R D = 0) or Write signal (WR = 0) will reset the Interrupt as well as
output the Data onto the Data Bus. If the processor cannot handle I nterrupts fast
enough (every 13 J.l.s) for MFM and 27 J.l.s for FM mode, then it may poll the Main
Status Register and then bit D7 (ROM) functions just like the I nterrupt signal. If a
Write Command is in process then the WR signal performs the reset to the Interrupt
signal.
If the J.l.PD765 is in the DMA Mode, no Interrupts are generated during the Execution
Phase. The J.l.PD765 generates DRO's (DMA Requests) when each byte of data is available. The DMA Controller responds to this request with both a DACK = 0 (DMA
Acknowledge) and a AD = 0 (Read signal). When the DMA Acknowledge signal goes
low (DACK = 0) then the DMA Request is reset (DRO = 0). If a Write Command has
been programmed then a WR signal will appear instead of RD. After the Execution
Phase has been completed (Terminal Count has occurred) or EaT sector was read/
written, then an I nterrupt will occur (INT = 1). This signifies the beginning of the
Result Phase. When the first byte of data is read during the Result Phase, the Interrupt
is automatically reset (INT = 0).
It is important to note that during the Result Phase all bytes shown in the Command
Table must be read. The Read Data Command, for example has seven bytes of data in
the Result Phase. All seven bytes must be read in order to successfully complete the
Read Data Command. The J.l.PD765 will not accept a new command until all seven
bytes have been read. Other commands may require fewer bytes to be read during the
Result Phase.
The J.l.PD765 contains five Status Registers. The Main Status Register mentioned above
may be read by the processor at any time. The other four Status Registers (STa, ST1,
ST2, and ST3) are only available during the Result Phase, and may be read only after
completing a command. The particular command which has been executed determines
how many of the Status Registers will be read.
The bytes of data which are sent to the J.l.PDY65 to form the Command Phase, and are
read out of the J.l.PD765 in the Result Phase, must occur in the order shown in the
Command Table. That is, the Command Code must be sent first and the other bytes
sent in the prescribed sequence. No foreshortening of the Command or Result Phases
are allowed. After the last byte of data in the Command Phase is sent to the J.l.PD765,
the Execution Phase automatically starts. In a similar fashion, when the last byte of
data i:; read out in the Result Phase, the command is automatically ended and the
J.l.PD765 is ready for a new command.
POLLING FEATURE OF
THE J.l.PD765
After the Specify command has been sent to the J,LPD765, the Unit Select line usa and
USlwili automatically go into a polling mode. In between commands (and between
step pulses in the SEEK command) the J,LPD765 polls all four FDD's looking for a
change in the Ready line from any of the drives. If the Ready line changes state (usually
due to a door opening or closing) then the J,LPD765 will generate an interrupt. When
Status Register 0 (STO) is read (after Sense Interrupt Status is issued), Not Ready (N R)
will be indicated. The polling of the Ready line by the J,LPD765 occurs continuously
between commands, thus notifying the processor which drives are on or off line. Each
drive is polled every 1.024 ms except during the ReadlWrite commands.
469
9
"PD765A
READ DATA
A set of nine (9) byte words are required to place the FDC into the Read Data Mode. After the Read Data
command has been issued the FDC loads the head (if it is in the ).mloaded statel. waits the specified head
settling time (defined in the Specify Command), and begins reading ID Address Marks and 10 fields. When
the current sector number ("R") storedin the 10 Register (lOR) compares with the sector number read off
the diskette, then the FDC outputs data (from the data field) byte-ta-byte to the main system via the data
bus.
After completion of the read operation from the current sector, the Sect~r Number is incremented by one,
and the data from the next sector is read and output on the data bus. This continuous read function is called
a "Multi-Sector Read Operation." The Read Data Command may be terminated by the receipt of a Terminal
Count signal. TC should be issued at the same time that the i5ACK for the last byte of data is sent. Upon
receipt of this signal, the FDC stops outputting data to the processor, but will continue to read data from the
current sector, check CRC (Cyclic Redundancy Count) bytes, and then at the end of the sector terminate
the Read Data Command.
The amount of data which can be handled with a single command to the FDC depends upon MT (multitrack), MF (MFM/FM). and N (Number of Bytes/Sector). Table 1 below shows the Transfer Capacity.
Multi-Track
MT
0
0
1
1
0
0
1
1
0
0
1
1
MFM/FM
MF
0
1
0
1
0
1
0
1
0
1
0
1
Bytes/Sector
N
00
01
00
01
01
02
01
02
02
03
02
03
Maximum Transfer Capacity
(Bytes/Sector) (Number of Sactors)
(128)
(256)
(128)
(256)
(256)
(512)
(256)
(512)
(512)
(1024)
(512)
(1024)
(26)
(26)
(52)
(52)
(15)
(15)
(30)
(30)
(8)
(8)
(16)
(16)
=
=
=
=
=
=
=
=
=
=
=
=
3,328
6,656
6,656
13,312
3,840
7,680
7,680
15,360
4,096
8,192
8,192
16,384
Final Sector Reed
from Diskette
26 at Side 0
or 26 at Side 1
26 at Side 1
15 at Side 0
or 1 5 at Side 1
15 at Side 1
8 at SideO
or 8 at Side 1
8 at Side 1
Table 1. Transfer Capacity
The "multi-track" function (MTl allows the FDC to read data from both sides of the diskette. For a
particular cylinder, data will be transferred starting at Sector 1, Side 0 and completing at Sector L, Side 1
(Sector L = last sector on the side). Note, this function pertains to only one cylinder (the same track) on
'
each side of the diskette.
When N = 0, then DTL defines the data length which the FDC must treat as a sector. If DTL is smaller than
the actual data length in a Sector, the data beyond DTL in the Sector, is not sent to the Data Bus. The FDC
reads (internally) the complete Sector performing the CRC check, and depending upon the manner of command termination, may perform a Multi-Sector Read Operation. When N is non-zero, then DTL has no
meaning and should be set to FF Hexidecimal.
At the completion of the Read Data Command, the head is not unloaded until after Head Unload Time
Interval (specified in the Specify Command) has elapsed. If the processor issues another command before
the head unloads then the head settling time may be saved between subsequent reads. This time out is
particularly valuable when a diskette is copied from one drive to another.
If the FDC detects the Index Hole twice without finding the right sec·tor, (indicated in "R"), then the FDC
sets the NO (No Data) flag in Status Register 1 to a 1 (high), and terminates the Read Data Command.
(Status Register 0 also has bits 7 and 6 set to 0 and 1 respectively.)
After reading the 10 and Data Fields in each sector, the FDC checks the CRC bytes. If a read error is
detected (incorrect CRC in 10 field), the FDC sets the DE (Data Error) flag in Status Register 1 to a 1 (high),
and if a CRC error occurs in the Data Field the FDC also sets the DO (Data Error in Data Field) flag in
Status Register 2 to a 1 (high). and terminates the Read Data Command. (Status Register 0 also has bits 7
and 6 set to 0 and 1 respectively.)
If the FDC reads a Deleted Data Address Mark off the diskette, and the SK bit (bit 05 in the first Command
Word) is not set (SK = 0), then the FDC sets the CM (Control Mark) flag in Status Register 2 to a 1 (high),
and terminates the Read Data Command, after reading all the data in the Sector. If SK ~ 1, the FDC skips
the sector with the Deleted Data Address Mark and reads the next sector. The CRC bits in the deleted data
field are not checked when SK - 1.
During disk data transfers between the F DC and the processor, via the data bus, the F DC must be serviced
by the processor every 27 JJS in the FM Mode, and every 13 JJS in the MFM Mode, or the FDC sets the OR
(Over Run) flag in Status Register 1 to a 1 (high), and terminates the Read Data Command.
If the processor terminates a read (or write) operation in the FDC, then the 10 Information in the Result
Phase is dependent upon the state of the MT bit and EOT byte. Table 2 shows the values for C, H, R, and
N, when the' processor terminates the Command.
'
470
FUNCTIONAL
DESCRIPTION OF
COMMANDS
IlPD765A
FUNCTIONAL
DESCRIPTION OF
COMMANDS (CONT.)
10 Information at Result Phase
MT
Final Sector Transferred to Processor
HD
C
H
R
N
Less than EaT
NC
NC
R +1
NC
0
Equal to EaT
C+1
NC
R; 01
1
Less than EaT
NC
NC
R +1
1
Equal to EaT
C+1
NC
R ;01
NC
0
Less than EaT
NC
NC
R + 1
NC
0
Equal to EaT
NC
LSB
R; 01
NC
1
Less than EaT
NC
NC
R +1
NC
1
Equal to EaT
C+ 1
LSB
R ;01
NC
0
0
1
Notes:
NC
--f-NC
1
NC (No Change): The same value as the one at the beginning of command execution.
2
LSB (Least Significant Bit): The least significant bit of H is complemented.
WRITE DATA
A set of nine (9) bytes are required to set the FOC into the Write Oata mode. After the Write Oata command
has been issued the FOC loads the head (if it is in the unloaded state), waits the specified Head Settling Time
(defined in the Specify Command), and begins reading 10 Fields. When all four bytes loaded during the com·
mand (C, H, R, N) match the four bytes of the 10 field from the diskette, the FOC takes data from the
processor byte-by-byte via the data bus, and outputs it to the FOO.
After writing data into the cwrent sector, the Sector Number stored in "R" is incremented by one, and the
next data field is written into. The FDC continues this "Multi-Sector Write Operation" until the issuance of
a Terminal Count signal. If a Terminal Count signal is sent to the FDC it continues writing into the current
sector to complete the data field; If the Terminal Count signal is received while a data field is being written
then the remainder of the data field is filled with 00 (zeros).
TheFDC reads the to field of each sector and checks the CRC bytes. If the FDC detects a read error
(incorrect CRC) in one of the 10 Fields, it sets the DE (Data Error) nag of Status Register 1 to a 1 (high),
and terminates the Write Data Command. (Status Register 0 also has bits 7 lmd 6 set to 0 and 1 respectively.)
The Write Command operates in much the same manner as the Read Command. The following items are the
same, and one should refer to the Read Data Command for details:
It
Head Unload Time Interval
• Transfer Capacity
It
10 Information when the processor terminates command (see Table 2)
• EN (End of Cylinder) Flag
II
Definition of DTL when N = 0 and when N*-O
• NO (No Data) Flag
In the Write Oata mode, data transfers between the processor and FOC, via the Oata Bus, must occur every
27 JJS in the FM mode, and every 13 JJS in the MFM mode. If the time interval between data transfers is
longer than this then the FOC sets the OR (Over Run) flag in Status Register 1 to a 1 (highl, and terminates
the Write Oata Command. (Status Register 0 also has bit 7 and 6 set to 0 and 1 respectively.)
WRITE DELETED DATA
This command is the same as the Write Data Command except a Deleted Data Address Mark is written at the
ooginning of the Data Field instead of the normal Data Address Mark.
READ DELETED DATA
This command is the same as the Read Data Command except that when the F DC detects a Data Address
Mark at the beginning of a Data Field (and SK = 0 (low). it will read all the data in the sector and set the
CM flag in Status Register 2 to a 1 (high), and then terminate the command. If SK = 1, then the FDC skips
the sector with the Data Address Mark and reads the next sector.
READ A TRACK
This command is similar to READ OATA Command except that this is a continuous READ operation
where the entire data field from each of the sectors are read. Immediately after encountering the
INDEX HOLE, the FOC ~tarts reading all data fields on the track, as continuous blocks of data. If the
FDC finds an error in the 10 or OATA CRC check bytes, it continues to read data from the track. The
F DC compares the 10 information read from each sector with the value stored in the I DR, and sets the
iNO flag of Status Register 1 to a 1 (high) if there is no comparison. Multi-track or skip operations are not
'allowed with this command.
This command terminates when number of sectors read is equal to'EOT. If the FDC does not find
an ID Address Mark on the diskette after it encounters the INDEX HOLE for the second time,
then it sets the MA (missing address mark) flag in Status Register 1 to a 1 (high), and terminates
the command. (Status Register 0 has bits 7 and 6 set to 0 and 1 respectively.l
471
flPD765A
FUNCTIONAL
DESCR IPTION OF
COMMANDS (CONT.)
READID
The READ 10 Command is used to give the present position of the recording head. The FDC stores the
values from the first 10 Field it is able to read. If no proper 10 Address Mark is found on the diskette,
before the INDEX HOLE is encountered for tne second time then the MA (Missing Address Mark) flag in
Status Register 1 is set to a 1 (high), and if no data is found then the NO (No Data) flag is also set in Status
Register 1 to a 1 (high). The command is then terminated with Bits 7 and 6 in Status Register 0 set to 0
and 1 respectively. During this command there is no data transfer between FOC and the CPU except (Juring
the result phase.
FORMAT A TRACK
The Format Command allows an entire track to be formatted, After the INDEX HOLE is detected, Data is
~itten on the Diskette; Gaps, Address Marks, 10 Fields and Data Fields, all per the IBM System 34 (Double
Density) or System 3740 (Single Density) Format are recorded. The particular format which will be written
is controlled by the values programmed into N (number of bytes/sector), SC (sectorslcylinder). GPL (Gap
Length). and 0 (Data Pattern) which are supplied by the processor during the Command Phase. The Data
Field is filled with the Byte of data stored in D. The 10 Field for each sector is supplied by the processor;
that is, four data requests per sector are made by the FDC for C (Cylinder Number). H (Head Number),
R (Sector Number) and N (Number of Bytes/Sector). This allows the diskette to be formatted with non·
sequential sector numbers, if desired.
The processor must send new values for C, H, R, and N to the /JP0765 for each sector on the track. If FDC'
is set for DMA mode, it will issue 4 OMA requests per sector. If it is set for interrupt mode, it will issue four
interrupts per sector and the processor must supply C, H, Rand N load for each sector. The contents of
the R register is incremented by one after each sector is formatted, thus, the R register contains a value of
R when it is read during the Result Phase. This incrementing and formatting continues for the whole track
until the FDC encounters the INDEX HOLE for the second time, whereupon it terminates the command.
If a FAU LT signal is received from the F DO at the end of a write operation, then the F DC sets the EC
flag of Status Register 0 to a 1 (high), and terminates the command after setting bits 7 and 6 of Status
Register 0 to 0 and 1 respectively. Also the loss of a READY signal at the beginning of a command
execution phase causes bits 7 and 6 of Status Register 0 to be set to 0 and.1 respectively.
Table 3 shows the relationship between N, SC, and GPL for various sector sizes:
5%" MINI FLOPPY
8" STANDARD FLOPPY
FORMAT
FM Mode
MFM Mode
SECTOR SIZE
N
SC
GPLG)
SECTOR SIZE
N
SC
GPL R), and the scan operation is continued. The scan
operation continues until one of the following conditions occur; tha conditions for scan are met (equal,
low, or high), the last sector on the track is reached (EOT), or the terminal count signal is received.
472
= 00)
IiPD765A
FUNCTIONAL
DESCRIPTION OF
COMMANDS (CONT.)
If the conditions for scan are met then the FDC sets the SH (Scan Hit) flag of Status Register 2 to a 1
(high), and terminates the Scan Command. If the conditions for scan are not met between the starting
sector (as specified by R) and the last sector on the cylinder (EOT), then the FDC sets the SN (Scan Not
Satisfied) flag of Status Register 2 to a 1 (high), and terminates the Scan Command. The receipt of a
TERMINAL COUNT signal from the Processor or DMA Controller during the scan operation will cause the
FDC to complete the comparison of the particular byte which is in process, and then to terminate the com·
mand. Table 4 shows the status of bits SH and SN under various conditions of SCAN.
STATUS REGISTER 2
COMMAND
Scan Equal
Scan Low or Equal
Scan High or Equal
COMMENTS
BIT 2 = SN
BIT 3 = SH
0
1
1
DFDD = DProcessor
0
DFOD
0
1
DFOD = DProcessor
0
0
0
DFDD
1
0
0
1
0
1
0
DFDD = DProcessor
DFDD > DProcessor
DFDD < DProcessor
* DProcessor
<
DProcessor
DFDD> DProcessor
Table 4
If the FDC encounters a Deleted Data Address Mark on one of the sectors (and SK = 0), then it regards the
sector as the last sector on the cylinder, sets CM (Control Mark) flag of Status Register 2 to a 1 (high) and
terminates the command. If SI< = 1, the FDC skips the sector with the Deleted Address Mark, and reads
the next sector. In the second case (5K = 1), the FDCsets the CM (Control Mark) flag of Status Register 2
to a 1 (high) in order to show that a Deleted Sector had been encountered.
When either the STP (contiguous sectors = 01, or alternate sectors = 02 sectors are read) or the MT (Multi·
Track) are programmed, it is necessary to remember that the last sector on the track must be read. For
example, if STP = 02, MT = 0, the sectors are numbered sequentially 1 through 26, and we start the Scan
Command at sector 21; the following will happen. Sectors 21, 23, and 25 will be read, then the next sectol
(26) will be skipped and the I ridex Hole will be el1countered before the EOT value of 26 can be read. This
will result in an abnormal termination of the command. If the EOT had been set at 25 or the scanning
started at sector 20, then the Scan Command would be completed in·a normal manner.
During the Scan Command data is supplied by either the processor or DMA Controller for comparison
against the data read from the diskette. In order to avoid having the OR (Over Run) flag set in Status
Register 1, it is necessary to have the data available in less than 27 p.s (FM Mode) or 13p.s (MFM Model. If
an Overrun occurs the FDC ends the command with bits 7 and 6 of Status Register 0 set to 0 and 1,
respect ivel y.
SEEK
The read/write head within the FDD is moved from cylinder to cylinder under control of the Seek Command. FDC has four independent Present Cylinder Registers for each drive. They are clear only after
Recalibrate command. The FDC compares the PCN (Present Cylinder Number) which is the current head
position with the NCN (New Cylinder Number), and if there is a difference performs the following
operation:
PCN < NCN: Direction signal to FDD set to a 1 (high), and Step Pulses are issued. (Step In.!
PCN> NCN: Direction signal to FDD set to a 0 (low), and Step Pulses are issued. (Step Out.!
The rate at which Step Pulses are issued is controlled by SRT (Stepping Rate Tim~) in the SPECI FY Command. After each Step Pulse is issued NCN is compared against PCN, and when NCN = peN, then the SE
(Seek End) flag is set in Status Register 0 to a 1 (high), and the command is terminated. At this point
FDC interrupt goes high. Bits DBO-DB3 in Main Status Register are set during seek operation and
are cleared by Sense I nterrupt Status command.
During the Command Phase of the Seek operation the FDC is in the FDC BUSY state, but during the
Execution Phase it is in the NON BUSY state. Whi.le the FDC is in the NON BUSY state, another Seek
Command may be issued, and in this manner parallel seek operations may be done on up to 4 Drives at
once. No other command could be issued for as long as F DC is in process of sending Step Pulses to any
drive.
If an FDD is in a NOT READY state at the beginning of the command execution phase or during the seek
operation, then the NR (NOT READY) flag is set in Status Register 0 to a 1 (high), and the command is
terminated after bits 7 and 6 of Status Register 0 are set to 0 and 1 respectively.
If the time to write 3 bytes of seek command exceeds 150 JJ.s, the timing between first two Step Pulses
may be shorter than set in the Specify command by as much as 1 ms.
473
"PD765A
RECALIBRATE
The function of this command is to retractthe read/write head within the FDD to the Track 0 position.
The FDC clears the contents of the PCN counter, and checks the status of the Track 0 signal from the
FDD. As long as the Track 0 signal is low, the Direction signal remains 0 (low) and Step Pulses are issued.
When the Track 0 signal goes high, the SE (SEEK END) flag in Status Register 0 is set to a 1 (high) and the
command is terminated. Ifthe Track 0 signal is still low after 77 Step Pulse have been issued, the FDC sets
the SE (SEEK END) and EC (EQUIPMENT CHECK) flags of Status Register 0 to both 1s (highs), and
terminates the command after bits 7 and 6 of Status Register 0 is set to 0 and 1 respectively.
The ability to do overlap RECALIBRATE Commands to multiple FDDs and the loss of the READY signal,
as described in the SEEK Command, also applies to the RECALIBRATE Command.
SENSE INTERRUPT STATUS
An Interrupt signal is generated by the FDC for one of the following reasons:
1. Upon entering the Result Phase of:
a. Read Data Command
e. Write Data Command
Format aCyl inder Command
b. Read a Track Command
g. Write Deleted Data Command
c. Read I D Command
h.
Scan
Commands
d. Read Deleted Data Command
2. Ready line of FDD changes state
3. End of Seek or Recalibrate Command
4. During Execution Phase in the NON·DMA Mode
Interrupts caused by reasons 1 and 4 above occur during normal command operations and are easily dis·
cernible by the processor. During an execution phase in NON·DMA Mode, DB5 in Main Status Register
is high. Upon entering Result Phase this bit gets clear. Reason 1 and 4 does not require Sense Interrupt
Status command. The interrupt is cleared by reading/writing data to FDC. Interrupts caused by reasons
2 and 3 above may be uniquely identified with the aid of the Sense Interrupt Status Command. This
command when issued resets the interrupt signal and via bits 5,6, and 7 of Status Register 0 identifies
the cause of the interrupt.
SEEK END
BIT5
0
1
1
INTERRUPT CODE
BIT6
BIT7
1
0
1
1
0
0
CAUSE
Ready Line changed state, either polarity
NormaL Termination of Seek or Recalibrate Command
Abnormal Termination of Seek or Recalibrate Command
Table 5
Neither the Seek or Recalibrate Command have a Result Phase. Therefore, it is mandatory to use the Sense
Interrupt Status Command after thase commands to effectively terminate them and to provide verification of
where the head is positioned (PCN).
Issuing Sense Interrupt Status Command without interrupt pending Is treated as an invalid command.
SPECIFY
The Specify Command sets the initial values for each of the threa internal timers. The HUT (Head Unload Time)
defines the time from the end of the Execution Phase of one of the Read/Write Commands to the head unload
state. This timer is programmable from 16 to 240 ms in increments of 16 ms (01 = 16 ms, 02 = 32 ms .... OF =
240 ms). The SRT (Step Rate Time) defines the time interval between adjacent step pulses. This timer is programmable from 1 to 16 ms in increments of 1 ms (F = 1 ms, E = 2 ms, D = 3 ms, etc.). The Hl T (Head load
Time) defines the time between when the Head load signal goes high and when the Read/Write operation starts.
This timer is programmable from 2 to 254 ms in increments of 2 ms (01 = 2 ms, 02 = 4 ms, 03 = 6 ms ... 7F =
254 ms).
The time intervals mentioned above are a direct function of the clock (ClK on pin 19). Times indicated above
ara for an 8 MHz clock, if the c!ock was reduced to 4 MHz (mini·floppy application) then all time intervals are
increased by a factor of 2.
The choice of OMA or NON-OMA operation is made by the NO (NON-OMA) bit. When this bit is high (NO = 1)
the NON-OMA moda is selected, and when NO = 0 the OMA mode is selected.
SENSE DRIVE STATUS
This command may be used by the processor whenever it wishes to obtain the status of the FOOs. Status
Register 3 contains the Drive Status information stored internally in FOC registers.
INVALID
If an invalid command is sent to the FOC (a command not dafined above), then the FOC will terminate the command after bits 7 and 6 of Status Regi~ter 0 are set to 1 and 0 respectively. No interrupt is genarated by the
~P0765 during this condition. 8it 6 and bit 7 (010 and RQMI in the Main Status Register are both high ("1 "I
indi'cating to the processor thet tha ~P0765 is in the Result Phase end the contents of Status Register 0 (STO)
mUlt ba reacl. When the processor reads Status Register 0 it will find a 80 hex indicating an invalid command
was received.
A Sensa Interrupt Status Command must be sant after e Seek or Recalibrate Interrupt, otherwise the FOC will
consider the next command to be an Invalid Command.
In some applications tha user may wish to use this command as a No·Op command, to place the FOC in a
standby or no operation state.
474
FUNCTIONAL
DESCR IPTION OF
COMMANDS (CONT.)
",PD76?A
STATUS REGISTER
IDENTI FICATION
NO.
BIT
NAME
SYMBOL
DESCRIPTION
STATUS REGISTER 0
D7
Interrupt Code
IC
D7 = 0 and D6 = 0
Normal Termination of Command, (NT). Command was completed and properly executed.
D7 = 0 and D6 = 1
Abnormal Termination of Command, (AT).
Execution of Command was started, but was not
successfully completed.
D6
D7 = 1 and D6 = 0
Invalid Command issue, (lC). Command which
was issued was never started.
D7 = 1 and D6 = 1
Abnormal Term ination because during command
execution the ready signal from FDD changed
state.
D5
Seek End
SE
When the FDC completes the SEEK Command,
this flag is set to 1 (high).
D4
Equipment
Check
EC
If a fault Signal is received from the FDD, or if
the Track 0 Signal fails to occur after 77 Step
Pulses (Recalibrate Command) then this flag is
set.
D3
Not Ready
NR
When the FDD is in the not-ready state and a
read or write command is issued, th is flag is set.
If a read or write command is issued to Side 1 of
a single sided drive, then th is flag is set.
D2
Head
Address
HD
This flag is used to indicate the state of the head
at Interrupt.
D1
DO
Unit Select 1
Unit Select 0
US 1
IUS 0
These flags are used to indicate a Drive Unit.
Number at Interrupt.
D7
End of
!Cylinder
EN
D6
D5
When the FDC tries to access a Sector beyond
the final Sector of a Cylinder, this flag is set.
Not used. This bit is always 0 (low).
Data Error
DE
D4
Over Run
OR
D3
D2
No Data
~D
When the FDC detects a CRC error in either the
ID field or the data field, this flag is set.
If the FDC is not serviced by the main-systems
during- data transfers, within a certain time
interval, this flag is set.
Not used. This bit always 0 (low).
During execution of READ DATA, WRITE
DELETED DATA or SCAN Command, if the
FDC cannot find the Sector specified in the IDR
Register, th is flag is set.
STATUS REGISTER 1
During executing the READ ID Command, if
the FDC cannot read the ID field without an
error, then this flag is set.
During the-execution of the READ A Cylinder
Command, if the starting sector cannot be
found, then this flag is set.
475
"PD765A
BIT
NO.
NAME
SYMBOL
DESCRIPTION
STATUS REGISTER 1 (CONT.)
D1
Not
Writable
NW
During execution of WRITE DATA, WRITE
DELETED DATA or Format A Cylinder Command, if the FDC detects a write protect signal
from the FDD, then this flag is set.
DO
Missing
Address
MA
If the FDC cannot detect the I D Address Mark
after encountering the index hole twice, then
th is fl ag is set.
Mark
If the FDC cannot detect the Data Address Mark
or Deleted Data Address Mark, this flag is set.
Also at the same time, the MD (Missing Address
Mark in Data Field) of Status Register 2 is set.
STATUS REGISTER 2
Not used. This bit is always 0 (low).
D7
D6
Control
Mark
CM
During executing the READ DATA or SCAN
Command, if the F DC encou nters a Sector wh ich
contains a Deleted Data Address Mark, this
flag is set.
If the FDC detects a CRC error in the data field
then this flag is set.
D5
Data Error in
Data Field
DD
D4
Wrong
Cylinder
WC
This bit is related with the ND bit, and when the
contents of C on the medium is different from
that stored in the IDR, this flag is set.
D3
Scan Equal
Hit
SH
During execution, the SCAN Command, if the
condition of "equal" is satisfied, th is flag is set.
D2
Scan Not
Satisfied
SN
During executing the SCAN Command, if the
FDC cannot find a Sector on the cylinder which
meets the condition, then this flag is set.
D1
Bad
Cylinder
BC
This bit is related with the ND bit, and when the
content of C on the medium is different from
that stored in the IDR and the content of C is
FF, then this flag is set.
DO
Missing
Address Mark
in Data Field
MD
When data is read from the medium, if the F DC
cannot find a Data Address Mark or Deleted
Data Add'ress Mark, then this flag is set.
D7
Fault
FT
This bit is used to indicate the status of the
Fault signal from the F DD.
D6
Write
Protected
WP
This bit is used to indicate the status of the
Write Protected signal from the FDD.
D5
Ready
RY
This bit is used to indicate the status of the
Ready Signal from the FDD.
D4
Track 0
TO
This bit is used to indicate the status of the
Track 0 signal from the FDD.
D3
Two Side
TS
Th is bit is used to indicate the status of the
Two Side signal from the FDD.
D2
Head Address
HD
This bit is used to indicate the status of Side
Select signal to the FDD.
D1
Unit Select 1
US 1
This bit is used to indicate the status of the Unit
Select 1 signal to the FDD.
DO
Unit Select 0
US9
This bit is used to indicate the status of the Unit
Select 0 signal to the FDD.
STATUS REGISTER 3
476
STATUS REGISTER
IDENTI FICATION (CONT.)
",PD765A
It is suggested that you utilize the following applications notes:
VREF.
The AID conversion is started with CS going to a high level and at tha final step of the first AID
conversion the EOC is at a low.
The conversion time is:
tCONV - 14 x 4 x 1/fCK
For fSCK > 600 kHz, the load capacitor (stray capacitance included) and the pull-up resistor which
are connected to serial output are required to be not more than 30 pF and 4 Kn respectively.
481
I'PD7001
TIMING WAVEFORMS
DIGITAL DATA OUTPUT
~---------~II~-------------
ANALOG CHANNEL SELECTION
SCK
J-.-i tSIK
H tHKI
SI:===========:X",___D1_@_2__,,~_D_O_@_- - - - - ~tHKDL
DL
Notes:
IC=
....
cs
AO,A' _ _ _ _- '
~~------tRR--------~. .--~
.,..-----....;,---~-
--
'----------1- - 485
IJ-PD7002
CONTROL TERMINALS
CS
RD
WR
A1
AO
MODE
H
x
x
x
x
Not selected
L
H
H
x
x
Not selected
L
H
L
L
L
Write moda
INTERNAL
FUNCTION
CONTROL TERMINAL
FUNCTIONS
DATA INPUT-OUTPUT
TERMINALS
High impedanca
Data latch
Input status, 01, DO - MPX address
AID start
03 - 8 bitll0 bit conversion
designation.
02 - Flag Input
TxA>RxB>TxB
1 PRIORITY RxA>RxB>TxA>TxB
o
o
0
o
1
8085 MASTER MODE
8085 SLAVE MODE
8086 MODE
UNDEFINED
INTERRUPT VECTORED/NON-VECTORED
ALWAYS ZERO
o
RTSB PIN 10
SYNCB PIN 10
WRITE REGISTER 3
Rx ENABLE
SYNC CHARACTER L.OAD INHIBIT
~--- ADDRESS SEARCH MODE (SDLC)
~-------RxCRCENABL.E
' - - - - - - - - ENTER HUNT PHASE
' - - - - - " ' - - - - - - AUTO ENAB LES
o
o
0
o
Rx
Rx
Rx
Rx
5
7
6
8
BITS/CHARACTER
BITS/CHARACTER
BITS/CHARACTER
BITS/CHARACTER
WRITE REGISTER 4
PARITY ENABLE
PARITY EVEN/ODD
o
o
o
o
o
o
0
1
o
0
1
o
0
1
o
SYNC MODES ENABLE
1 STOP BIT/CHARACTER
1 1/2 STOP BITS/CHARACTER
2 STOP BITS/CHARACTER
8 BIT SYNC CHARACTER
16 BIT SYNC CHARACTER
SDLC MODE (01111'110 FLAG)
EXTERNAL SYNC MODE
X1 CLOCK MODE
X16 CLOCK MODE
X32 CL.OCK MODE
X64 CLOCK MODE
496
JLPD7201
WRITE REGISTER
BIT FUNCTIONS
(CONT.)
WRITE REGISTER 5
Tx CRC ENABLE
RTS
'------CRC·16/CRC·CCITT
' - - - - - - - - T x EN,.,BLE
'------------------SENDBREAK
o
o
0
1
o
Tx
Tx
Tx
Tx
5
7
6
8
BITS (OR LESS)/CHARACTER
BITS/CHARACTER
BITS/CHARACTER
BITS/CHARACTER
DTR
WRITE REGISTER 6
1 07 1 Os I
05
I
04
1 03 1 02 1 0 1 I
I
I
DO
I
L:
SYNC
SYNC
SYNC
SYNC
SYNC
SYNC
SYNC
SYNC
BITO1 \
BIT
BIT 2
BIT 3
BIT4
BIT 5
BIT 6
BIT 7
ALSO SDLC
ADDRESS FIELD
WRITE REGISTER 7
I 07
lOs
I 05 I 04 I 03 I 02 I 01 I DO I
I
l
L.
~~~~ ~iH~ \
SYNC
SYNC
SYNC
SYNC
Note:
CD
BIT
BIT
BIT
BIT
12
13
14
15
CD
.
For SDLC it must be programmed to "01111110" for flag recognition.
497
",PD7201
INTERRUPT STRUCTURE
RECEIVE CHARACTER
PARITY ERROR
-RECEIVE OVERRUN ERROR
FRAMING ERROR
END OF FRAME (SDLC)
FIRST DATA CHARACTER
FIRST NON-SYNC
CHARACTER (SYNC)
VALID ADDRESS
BYTE (SDLC)
"PD7201
INTERRUPT
DCD TRANSITION
CTS TRANSITION
SYNC TRANSITION
Tx UNDERRUN/EOM
BREAK/ABORT DETECTION
I
BUFFER BECOMING EMPTY
WR2s BITS
INCH.A
-PRIN
x
x
1
0:Il1 :Ell> :Il ::!
.5'
mo
-I 7\
,uPD721 0
DMAREQ
I-
DMAACKt--"H"
T/R3-1
~
l
BUS TRANSCEIVERS
--...-
I
~
~"'7
~
~~
0
~IC:Il!;;~ ~ m
00
~ :Il
TIMER OUT
Z
,uPD8155
l>
0
00
l>
....C
dJ
o :Ill oil> :Il
1
~
0
~iC:E!;;g:~
~
,uPD8355
CEI--
"H"
IORt--
"H"
PA7-O. PB7-O
PA7-8
PB7-8
PC5-6
llun
r-
SWITCHES
-,
II
J
DISPLAY
"1:
"'0
C
~
G')
a
~
III
....
o
I\)
flPD7210
/JP07210
GPIB
MC3448AX4
mOg
DATA A
DATA B
OATAC
DATA 0
Q.!Qz.
~
I 5
Di04
~
01°2'
010,
T/R,
T/R3 (EOIOE)
'Ern'
riA\7
'fim'rn
NDAC
T/R2 (CIC)
~
ATf:T
1fm
m!
BUSA
BUS B
BUS C
BUS 0
~:g~
..- S/RA-O
PEA.O I-
DATA A
DATA B
OATAC
DATA 0
~ S/RA-O
BUSA
BUS B
BUSC
BUS 0
PEA·O .....
--{>---t>-S/RA
DATA A
' - S/R8
DATA B
r - - - S/RC
OATAC
S/Ro
DATA 0
-
-{>--
BUSA
EOI
BUS B
OAV
BUSC
NRFO
BUS 0
PEA.O I-
NOAC
8USA
SRO
S/RA
DATA A
L - - S/RB
DATA B
r- S/RC
OATAC
~ S/Ro
DATA 0
BUS B
ATN
BUS C
REN
BUS 0
PEA·O -
IFC
TT
"H""L"
Note:
01°8
01°7
"L"
In this example, high-speed data transfer cannot be made since the bus
transceiver is of the open collector type (Set 82 = 0).
OIOa
Os
BS
I 7
07
06
05
04
B7
B6
B5
SN75160 B4
B3
B2
B1
'I5iOs
riIOs
!51Q,i
l5iD,
03
02
01
T/R3 (PE)
PE
01°3
01°2
/JP0721 0
TE
GPIB
T/R1
TE
T/R2 (CIC)
DC
SRQ
SRO
ATN
ATN
EOI SN7516'
OAV
NRFO
NDAC
5Ai7
~
NDAC
IFC
REN
Note:
In the case of low-speed data transfer (82 = 0), the T/R3 pin can be used as a
TRIG output. The PE input of SN75160 should be cleared to "0."
510
MINIMUM 8085 SYSTEM
WITH J.,LPD7210 (CONT.)
IlPD7210
ABSOLUTE MAXIMUM
RATINGS
(Ta .. 25"C)
Parameter
Symbol
Supply Voltage
DC CHARACTERISTICS
Ratings
Test Conditions
Unit
VCC
-0.5"" + 7.0
V
Input Voltage
VI
-0.5"" +7.0
V
Output Voltage
Vo
-0.5"" +7.0
V
0-+70
°c
Operating Temperature
Topt
Storage Temperature
Tstg
-65"" +125
°c
(Ta'" 0 - +70°C, VCC= 5V ± 10%)
Limits
Parameter
CAPACITANCE
Symbol
Test Conditions
Min.
Typ ..
Max.
Unit
Input Low Voltage
VIL
-0.5
+0.8
V
Input High Voltage
VIH
+2.0
VCC + 0.5
V
Low Level
Output Voltage
VOL
10L = 2mA
(4 mA : T/R1 Pin)
+0.45
V
High Level
Output Voltage
VOH1
10H" -400J'A
(Except INT)
+2.4
High Level
Output Voltage
(lNT Pin)
10H = -400J'A
+2.4
VOH2
10H =-50J'A
+3.5
Input Leakage
Current
IlL
VIN· = OV - VCC
-10
+10
J'A
Output Leakage
Current
10L
VOUT = 0.45V - VCC
-10
+10
J'A
Supply Current
ICC
+180
mA
(Ta = 25°C,VCC
V
V
= GND = OV)
Limits
Parameter
Symbol
Test Conditions
= 1 MHz
Input CapaCitance
CIN
f
Output Capacitance
COUT
Ali Pins Except Pin Under
Test Tied to AC Ground
I/O Capacitance
CliO
511
Min.
Typ,
Max
Unit
10
pF
15
pF
20
pF
IlPD7210
AC CHARACTERISTICS
LlmLts
Parameter
Symbol
Conditions
Min.
Max
Unit
PPSS -+ PPAS,ATN = True
260
ns
EOI.\.-+T/R1t
tEOT11
PPSS -+ PPAS, ATN = True
155
ns
EOlt-+T/RH
tEOT12
PPAS-+ PPSS, ATN
= Felse
200
ns
ATN.J. -+ NOAC.J.
tATNO
AIOS-+ ANRS, LIDS
155
ns
TACS + SPAS -+ TAOS, CIOS
155
ns
ATN.J. -+ T/R2.\.
tATT2
TACS + SPAS -+ TAOS, CIOS
200
ns
OAVl- -+ OMAREO
tOVRO
ACRS -+ ACOS, LACS
600
ns
OAV.\. -+ NRFO.\.
tOVNR1
ACRS-+ACOS
350
ns
OAV.\. -+ NOACt
tOVN01
ACRS -+ ACOS -+ AWNS
650
ns
AWNS-+ANRS
350
ns
AWNS -> ANRS -+ ACRS
350
ns
ANRS-+ACRS
LACS, 01 reg. selected
500
ns
NOACt -+ OMAREOt tNORO
STRS -+ SWNS -+ SGNS, T ACS
400
ns
NOACt -+ OAVt
STRS -+ SWNS -+ SGNS
350
ns
twOI
SGNS -+ SOYS, BO
reg. selected
250
ns
tNROV
SOYS -+ STRS, T1 = True
350
ns
830
ns
i5A'Vt -+.NRFDt
tOVNR2
twov
TRIG
Pulse Width
tTRIG
SGNS -+ SOYS -+ STRS
BO reg. selected, RFO = True
N F - fc = 8 MHz,
T 1 (High Speed)
+tSYNC
50
512
ns
IlPD7210
AC CHARACTERISTICS
('CO NT.)
(Ta - 0"" 70°C, VCC'" 5V ± 10%)
limits
Parameter
Symbol
Test Conditions
Min
Max.
Unit
RSO- RS2
85
ns
Cs'
0
ns
tRA
0
ns
Ri5 Pulse Width
tRR
170
ns
Data Delay from Address
tAD
250
ns
Data Delay from RD.j.
tRD
150
ns
Output Float Delay from ROt
tDF
0
80
n8
Ri5 Recovery Time
tRV
250
ns
Address Setup to WR
tAW
0
ns
tWA
0
ns
tww
170
ns
tow
150
ns
WR
two
0
ns
WR Recovery Time
tRV
250
ns
DMAREQ.j.Delay from DMAACK
tAKRQ
130
ns
tAKD
200
ns
Address Setup to
AD
Address Hold from
Address Hold from
REi
WR
WR Pulse Width
Data Setup to
WR
Data Hold from
Data Delay from
DMA'A'Ci<
513
t~R
"PD7210
TIMING WAVEFORMS
CS, RS2 - 0
______+-________~I~-----tRR------~u_----------------~.
.....- - - t R V
-----~
07-0
\.\t
~~KRQ-::t~__________________________________
AKO
OMAREQ
07-0
721 OOS-R EV 1-1-82-CA T
514
NEe
NEe Electronics u.s.A. Inc. ~
is. GRAPHICS DISPLAY ",PD7220/GDC
CONTROLLER
~\.,.
Microcomputor Division ...."f\,.'\,~))l
Description
~
The J,tP07220 Graphics Display Controller (GOC) is an
intelligent microprocessor peripheral designed to be the
heart of a high-performance raster-scan computer graphics
and character display system. Positioned between the
video display memory and the microprocessor bus, the
GOC performs the tasks needed to generate the raster display and manage the display memory. Processor software
overhead is minimized by the GOC's sophisticated instruction set,' graphics figure drawing, and OMA transfer capabilities. The display memory supported by the GOC can be
configured in any number of formats and sizes up to 256K
16-bit words. The display can be zoomed and panned,
while partitioned screen areas can be independently
scrolled. With its light pen input and multiple controller
capability, the GOC is ideal for advanced computer
graphics applications.
Features
o Microprocessor Interface
OMA transfers with 8257- or 8237-type controllers
FIFO Command Buffering
o Display Memory Interface
Up to 256K words of 16 bits
Read-Modify-Write (RMW) Display Memory cycles
in under 800ns
Dynamic RAM reresh cycles for nonaccessed memory
o Light Pen Input
o External video synchronization mode
o Graphics Mode:
Four megabit, bit-mapped display memory
o Character Mode:
8K character code and attributes display memory
[J Mixed Graphics and Characters Mode
64K if all characters
1 megapixel if all graphics
[J Graphics Capabilities:
Figure drawing of lines, arc/circles, rectangles, and
graphics character in 800ns per pixel
Display 1024-by-1 024 pixels with 4 planes of color
or grayscale.
Two independently scrollable areas
[J Character Capabilities:
Auto cursor advance
Four independently scrollable areas
Programmable cursor height
Characters per row: up to 256
Character rows per screen: up to 100
[J Video Display Format
Zoom ma~}nification factors of 1 to 16
Panning
Command-settable video raster parameters
[J Technology
Single +5 volt, NMOS, 40-pin DIP
[] OMA Capability:
Bytes or word transfers
4 clock periods per byte transferred
REV/2
515
System Considerations
The GOC is designed to work with a general purpose
microprocessor to implement a high-performance computer graphics system. Through the division of labor
established by the GOC's design, each of the system
components is used to the maximum extent through sixlevel hierarchy of simultaneous tasks. At the lowest level,
the GOC generates the basic video raster timing, including
sync and blanking signals. Partitioned areas on the screen
and zooming are also accomplished at this level. At the
next level, video display memory is modified during the figure drawing operations and data moves. Third, display
memory addresses are calculated pixel by pixel as drawing
progresses. Outside the GOC at the next level, preliminary
calculations are done to prepare drawing parameters. At
the fifth level, the picture must be represented as a list of
graphics figures drawable by the GOC. Finally, this representation must be manipulated, stored, and communicated. By handling the first three levels, the GOC takes care
of the high-speed and repetitive tasks required to implement a graphics system.
GDe Components
The GOC block diagram illustrates how these tasks are
accomplished.
Microprocessor Bus Interface
Control of the GOC by the system microprocessor is
achieved through an 8-bit bidirectional interface. The
status register is readable at any time. Access to the FIFO
buffer is coordinated through flags in the status register
and operates independently of the various internal GOC
operations, due to the separate data bus connecting the
interface and the FIFO buffer.
Command Processor
The contents of the FIFO are interpreted by the command
processor. The command bytes are decoded, and the succeeding parameters are distributed to their proper destina~
JAPD7220
tions within the GDC. The command processor yields to the
accepted as a valid light pen detection. A status bit indibus int~rface when both access the FIFO simultaneously.
cates to the system microprocessor that the light pen register contains a valid address.
DMAControl
The DMA control circuitry in the GDC coordinates transfers
Programmer's View of GDC
over the microprocessor interface when using an external
The GDC occupies two addresses on the system microDMA controller. The DMA Request and Acknowledge
processor bus through which the GDC's status register and
handshake lines directly interface with a JLPD8257 or
FIFO are accessed. Commands and parameters are writJLPD8237 DMA controller, so that display data can be
ten into the GDC's FIFO and are differentiated based on
moved between the microprocessor memory and the disaddress bit AD. The status register or the FIFO can be read
play memory.
as selected by the address line.
Parameter RAM
AO
WRITE
READ
The 16-byte RAM stores parameters that are used repetiSTATUS REGISTER
PARAMETER INTO FIFO
tively during the display and drawing processes. In charac0
ter mode, this RAM holds four sets of partitioned display
I I I I I I I
I I I I I I I
area parameters; in graphics mode, the drawing pattern
FIFO READ
COMMAND INTO FIFO
and graphics character take the place of two of the sets of
1
parameters.
I I I I I I I
I I I I I I I
Video Sync Generator
ODe
MIcroprocessor
Bus
Interface
RegIsters
Based on the clock input, the sync logic generates the raster timing signals for almost any interlaced, non-interlaced,
Commands to the GDC take the form of a command byte
or "repeat field" interlaced video format. The generator is
followed by a series of parameter bytes as needed for
programmed during the idle period following a reset. In
specifying the details of the command. The command procvideo sync slave mode, it coordinates timing between mulessor decodes the commands, unpacts the parameters,
tipleGDCs.
loads them into the appropriate registers within the GDC,
and initiates the required operations.
Memory Timing Generator
The memory timing circuitry provides two memory cycle
The commands available in the GDC can be organized
types: a two-clock period refresh cycle and the readinto five categories as described in the following section.
modify-write (RMW) cycle which takes four clock periods.
GDC Command Summary
The memory control signals needed to drive the display
memory devices are easily generated from the GDC's ALE
Video Control Commands
and r::mft\j outputs.
1. RESET: Resets the GDC to its idle state.
Zoom & Pan Controller
2. SYNC:
Specifies the video display format.
Based on the programmable zoom display factor and the
3. VSYNC: Selects master or slave video syndisplay area entries in the parameter RAM, the zoom and
chronization mode.
pan controller determines when to advance to the next
4. CCHAR: Specifies the cursor and character
row heights.
memory address for display refresh and when to go on to
the next display area. A horizontal zoom is produced by
Display Control Commands
,
slowing down the display refresh rate while maintaining the
1. START: Ends Idle mode and unblanks the
video sync rates. Vertical zoom is accomplished by repeatdisplay.
edly accessing each line a number of times equal to the
2. BCTRl: Controls the blanking and unblanking
horizontal repeat. Once the line count for a display area is
of the display.
exhausted, the controller accesses the starting address
3. ZOOM:
Specifies zoom factors for the display
and line count of the next display area 'from the parameter
and graphics characters writing.
RAM. The system microprocessor, by modifying a display
4. CURS:
Sets the pOSition of the cursor in
area starting address, can pan in any direction, independisplay memory.
dent of the other display areas.
5. PRAM:
Defines starting addresses and lengths
Drawing Processor
of the display areas and specifies the
The drawing processor contains the logic necessary to
eight bytes for the graphics character.
calculate the addresses and pOSitions of the pixels of the
6. PITCH:
Specifies the width of the X dimenvarious graphics figures. Given a starting pOint and the
sion of display memory.
appropriate drawing parameters, the drawing processor
Drawing Control Commands
needs no further assistance to complete the figure drawing.
1. WDAT:
Writes data words or bytes into display
Display Memory Controller
memory.
The display memory controller's tasks are numerous. Its
2. MASK:
Sets the mask register contents.
primary purpose is to multiplex the address and data infqr3. FIGS:
Specifies the parameters for the drawing
mation in and out of the display memory. It also contains
processor.
the 16-bit logic unit used to modify the display memory con4. FIGD:
Draws the figure as specified above.
tents during RMW cycles, the character mode line counter,
5. GCHRD: Draws the graphics character into disand the refresh counter for dynamic RAMs. The memory
play memory.
controller apportions the video field time between the varData Read Commands
ious types of cycles.
1. RDAT:
Reads data words or bytes from display
Light Pen Deglitcher
memory.
Only if two rising edges on the light pen input occur at the
2. CURD: Reads the cursor position.
same point during successive video fields are the pulses 516
3. LPRD:
Reads the light pen address.
I
I I
I
I
I I
I
J.lPD7220
DMA Control Commands
1. DMAR: Requests a DMA read transfer.
2. DMAW: Requests a DMA write transfer.
17161514131211101
1111L
_~~~~=:~Y
' - - - - - - - FIFO Empty
' - - - - - - - - Drawing In Progress
DMAExecule
' - - - - - - - - - - - - Vertical Sync Active
- - - - - - - - - - - - H o r l z o n t a l Blank Active
------------lIghIPenOetecl
Status Register (SR)
Status Register Flags
SR-7: light Pen Detect
When this bit is set to 1, the light pen address (LAD)
register contains a deglitched value that the system microprocessor may read. This flag is reset after the 3-byte
LAD is moved into the FIFO in response to the light pen
read command.
SR-6: Horizontal Blanking Active
A 1 value for this flag signifies that horizontal retrace blanking is currently underway.
SR-5: Vertical Sync
Vertical retrace sync occurs while this flag is a 1. The vertical sync flag coordinates display format modifying commands to the blanked interval surrounding vertical sync.
This eliminates display disturb~nces.
SR-4: DMA Execute
This bit is a 1 during DMA data transfers.
SR-3: Drawing in Progress
While the GDC is drawing a graphics figure, this status bit
is a 1.
SR-2: FIFO Empty
This bit and the FIFO Full flag coordinate system microprocessor accesses with the GDC FIFO. When it is 1, the
Empty flag ensures that all the commands and parameters
previously sent to the GDC have been processed.
SR-1: FIFO Full
A 1 at this flag indicates a full FIFO in the GDC. A 0
ensures that there is room for at least one byte. This flag
needs to be checked before each write into the GDC.
SR-O: Data Ready
When this flag is a 1, it indicates that a byte is available to
be read by the system microprocessor. This bit must be
tested before each read operation. It drops to a 0 while the
data is transferred from the FIFO into the microprocessor
interface data register.
into the GDC causes the FIFO to store a flag value alongside the data byte to signify whether the byte was written
into the command or the parameter address. The command processor in the GDC tests this bit as it interprets the
entries in the FIFO.
The receipt of a command byte by the command processor
marks the end of any previous operation. The number of
parameter bytes supplied with a command is cut short by
the receipt of the next command byte. A read operation
from the GDC to the microprocessor can be terminated at
any time by the next command.
The FIFO changes direction under the control of the system microprocessor. Commands written into the GDC
always put the FIFO into write mode if it wasn't in it already.
If it was in read mode, any read data in the FIFO at the time
of the turnaround is lost. Commands which require a GDC
response, such as RDAT, CURD and LPRD, put the FIFO
into read mode after the command is interpreted by the
GDC's command processor. Any commands and parameters behind the read-evoking command are discarded
when the FIFO direction is reversed.
Read-Modify-Write Cycle
Data transfers between the GDC and the display memory
are accomplished using a read-modify-write (RMW) memory cycle. The four clock period timing of the RMW cycle is
used to: 1) output the address, 2) read data from the memory, 3) modify the data, and 4) write the modified data back
into the initially selected memory address. This type of
memory cycle is used for all interactions with display memory including DMA transfers, except for the two clock
period display and RAM refresh cycles.
The operations performed during the modify portion of the
RMW cycle merit additional explanation. The circuitry in the
GDC uses three main elements: the Pattern register, the
Mask register, and the 16-bit Logic Unit. The Pattern register holds the data pattern to be moved into memory. It is
loaded by the WDAT command or, during drawing, from the
parameter RAM. The Mask register contents determine
which bits of the read data will be modified. Based on the
contents of these registers, the Logic Unit performs the
selected operations of REPLACE, COMPLEMENT, SET, or
CLEAR on the data read from display memory.
The Pattern register contents are ANDed with the Mask
register contents to enable the actual modificatior:J of the
memory read data, on a bit-by-bit basis. For graphics drawing, one bit at a time from the Pattern register is combined
with the Mask. When ANDed with the bit set to a 1 in the
Mask register, the proper single pixel is modified by the
FIFO Operation & Command Protocol
Logic Unit. For the next pixel in the figure, the next bit in the
The first-in, first-out buffer (FIFO) in the GDC handles the
Pattern register is. selected and the Mask register bit is
command dialogue with the system microprocessor. This
moved to identify the pixel's location within the word. The
flow of information use~ a half-duplex technique, in which
Execution word address pointer register, EAD, is also
the single 16-location FIFO is used for both directions of
adjusted as required to address the word containing the
data movement, one direction at a time. The FIFO's direcnext pixel.
tion is controlled by the system microprocessor through
In character mode, all of the bits in the Pattern register are
the GDC's command set. The microprocessor coordinates
used in parallel to form the respective bits of the modify
these transfers by checking the appropriate status
data word. Since the bits of the character code word are
register bits.
used in parallel, unlike the one-bit-at-a-time graphics drawThe command protocol used by the GDC requires the difing process, this facility allows any or all of the bits in a
ferentiation of the first byte of a command sequence from
memory word to be modified in one RMW memory cycle.
the succeeding bytes. This first byte contains the operation
The Mask register must be loaded with 1s in the positions
code and the remaining bytes carry parameters. Writing . 517 where modification is to be permitted.
",PD7220
The Mask register can be loaded in either of two ways. 'In
graphics mode, the CURS command contains a four-bit
dAD field to specify the dot address. The command processor converts this parameter into the one-of-16 format used
in the Mask register for figure drawing. A full 16 bits can be
loaded into the Mask register using the MASK command.
In addition to the character mode use mentioned above,
the 16-bit MASK load is convenient in graphics mode when
all of the pixels of a word are to be set to the same value.
The Logic Unit combines the data read from display memory, the Pattern Register, and tne Mask register to generate
the data to be written back into display memory. Anyone of
four operations can be selected: REPLACE, COMPLEMENT, CLEAR or SET. In each case, if the respective Mask
bit is 0, that particular bit of the read data is returned to
memory unmodified. If the Mask bit is 1, the modification is
enabled. With the REPLACE operation, the modify data
simply takes the place of the read data for modification
enabled bits. For the other three operations, a 0 in the modify data allows the read data bit to be returned to memory.
A 1 value causes the specified operation to be performed in
the bit positions with set Mask bits.
The table below summarizes these operations for each
direction.
Figure Drawing
dAD will always be 1, so that the EAD value will be incremented or decremented for each cycle regardless of direction. One RMW cycle will be able to effect all 16 bits of the
word for any drawing type. One bit in the Pattern register is
used per RMW cycle to write all the bits of the word to the
same value. The next Pattern bit is used for the word, etc.
For the various figures, the effect of the initial direction
upon the resulting drawing is shown below:
The GDC draws graphics figures at the rate of one pixel per
read-modify-write (RMW) display memory cycle. These
cycles take four clock periods to complete. At a clock frequency of 5MHz, this is equal to 800ns. During the RMW
cycle the GDC simultaneously calculates the address and
position of the next pixel to be drawn.
The graphics figure drawing process depends on the display memory addressing structure. Groups of 16 horizontally adjacent pixels form the 16-bit words which are
handled by the GDC. Display memory is organized as a lin'early addressed space of these words. Addressing of individual pixels is handled by the GDC's internal RMW logic.
During the drawing process, the GDC finds the next pixel of
the figure which is one of the eight nearest neighbors of the
last pixel drawn. The GDC assigns each of these eight
directions a number from 0 to 7, starting with straight down
and proceeding counterclockwise.
Whole word drawing is useful for filling areas in memory
with a single value. By setting the Mask register to all1s
with the MASK command, both the LSB and MSB of the
OPERATIONS TO ADDRESS THE NEXT PIXEL
DIR
EAD + P .... EAD
000
EAD+P .... EAD
001
a 10
dAD (MSB)
= 1 : EAD + 1 .... EAD
dAD .... LR
dAD (MSB)
= 1 : EAD + 1 .... EAD
dAD .... LR
EAD~P
all
.... EAD
dAD (MSB)
100
101
=
1 : EAD + 1 .... EAD
EAD~P
.... EAD
EAD~P
.... EAD
dAD .... LR
dAD (LSB)
= 1 : EAD ~ 1 .... EAD
dAD .... RR
110
dAD (LSB)
= 1 : EAD +
1 .... EAD
dAD .... RR
111
EAD+ P .... EAD
1 .... EAD
dAD .... RR
dAD (LSB)
= 1 : EAD +
Where P "" Pitch, lR == left Rotate. RR = Right Rotate
EAD "" Execute Word Address
dAD = Dot Address stored in the Mask.Register
DIR
LINE
ARC
CHARACTER SLANT CHAR, RECTANGLE
f\N
~
000
~=
all
~
"
tN
100
110
111
Drawing Directions
Figure drawing requires the proper manipulation of the
address and the pixel bit position according to the drawing
direction to determine the next pixel of the figure. To move
to the word above or below the current one, it is necessary
to subtract or add the number of words per line in display
memory. This parameter is called the pitch. To move to the
word to either side, the Execute word address cursor, EAD,
must be incremented or decremented as the dot address
pointer bit reaches the LSB or the MSB of the Mask register. To move to a pixel within the same word, it is necessary
to rotate the dot address pointer register to the rigHt or left.
DMA
WI'" (J
~
~ ~~:,-,) ~
f
D
~
<>
~
Z .
- - - -
~
Note that during line drawing, the angle of the line may be
anywhere within the shaded octant defined by the DIR
value. Arc drawing starts in the direction initially specified
by the DIR value and veers into an arc as drawing proceeds. An arc may be up to 45 degrees in length. DMA
transfers are done on word boundaries only, and follow the
arrows indicated in the table to find successive word
addresses. The slanted paths for DMA transfers indicate
the GOC changing both the X and Y components of the
word address when moving to the next word. It does not
follow a 45 degree diagonal path by pixels.
518
~
-
fJPD7220
Drawing Parameters
In preparation for graphics figure drawing, the GOC's
Drawing Processor needs the figure type, direction and
drawing parameters, the starting pixel address, and the
pattern from the microprocessor. Once these are in place
within the GOC, the Figure Draw command, FIGO, initiates
the drawing operation. From that point on, the system
microprocessor is not involved in the drawing process. The
GOC Drawing Processor coordinates the RMW circuitry
and address registers to draw the specified figure pixel by
pixel.
The algorithms used by the processor for figure drawing
are designed to optimize its drawing speed. To this end, the
specific details about the figure to be drawn are reduced by
the microprocessor to a form conducive to high-speed
address calculations within the GOC. In this way the repetitive, pixel-by-pixel calculations can be done quickly,
thereby minimizing the overall figure drawing time. The
table below summarizes the parameters.
,
to draw the bytes into display memory starting at the
cursor. The zoom magnification factor for writing, set by
the zoom command, controls the size of the character
written into the display memory in integer multiples of 1
through 16. The bit values in the PRAM are repeated
horizontally and vertically the number of times specified
by the zoom factor.
The movement of these PRAM bytes to the display memory is controlled by the parameters of the FIGS command. Based on the specified height and width of the
area to be drawn, the parameter RAM is scanned to fill
the required area.
For an8-by-8 graphics character, the first pixel drawn
uses the LSB of RA-15, the second pixel uses bit 1 of
RA~15, and so on, until the MSB of RA-15 is reached.
The GOC jumps to the corre~ponding bit in RA-14 to
continue the drawing. The progression then advances
toward the LSB of RA-14. This snaking sequence is
continued for the other 6 PRAM bytes. This progression
matches the sequence of display memory addresses
02
01
OM
DC
0
DRAWING TYPE
-1
,calculated by the drawing processor as shown above. If
8
8
-1
Initial Value"
0
Line
2(1"01-1"11)
21"01
the area is narrower than 8 pixels wide, the snaking will
1"11
21"01-1"11
2(r-l)
rsln e.
Arc··
r sin Ot
r-l
-1
advance to the next PRAM byte before the MSB is
8-1
A-I
3
A-I
-1
Rectangle
reached. If the area is less than 8 lines high, fewer
A
A
8-1
Area Fill
bytes in the parameter RAM will be scanned. If the area
A
8-1
A
Graphic Character" " "
is larger than 8 by 8, the GOC will repeat the contents
W-l
Read & Write Data
of the parameter RAM in two dimensions, as required to
OMAW
0-1
C-l
fill the area with the 8-by-8 mozaic. (Fractions of the
OMAR'
0-1
C-l
(C-l)/2*
8-by-8 pattern will be used to fill areas which are not
" Initial values for the various parameters are loaded during the handling of the FIGS
op code byte.
, multiples of 8 by 8.)
"" Circles are dl'awn with 8 arcs, each of which span 45°, so that sin 0 = Iii/"2 and
sin e = o.
Parameter RAM Contents: RAM Address RA
" ". Graphic characters are a special case of bit-map area filling in which 8 and A " 8.
Oto
15
If A = 8 thero Is no need to load 0 and 02.
The parameters stored in the parameter RAM, PRAM,
Where:
-1 = all ONES value.
are available for the GOC to refer to repeatedly during
All numbers are shown In base 10 for convenience. The GOC accepts base 2 numbers ,(2s
complement notation where appropriate).
figure'drawing and raster-scanning. In each mode of
- = No parameter bytes sent to GOC for this parameter.
operation the values in the PRAM are interpreted by the
"I = The larger at Ax or "y.
GOC in a predetermined fashion. The host microproc"0 = The smaller at Ax or "y.
essor must load the appropriate parameters into the
r = Radius at curvature, In pixels.
proper PRAM locations. PRAM loading command
+ = Angle from major axis to end at the arc. +" 45°.
e = Angle from major axis to start at the arc. e .. 45°.
allows the host to write into any location of the PRAM
t = Round up to the next higher Integer .
and transfer as many bytes as desired. In this way any
• = Round down to the next lower Integer.
stored parameter byte or bytes may be changed without
A = Number of pixels In the Initially specified direction.
influencing the other bytes.
8 = Number of pixels In the direction at right angles to the Initially specified direction.
The PRAM stores two types of information. For specifyW = Number 0'1 words to be accessed.
ing the details of the display area partitions, blocks of
C = Number a" bytes to be transferred In the Initially specified direction. (Two bytes
per word If word transfer mode Is selected).
four bytes are used. The four parameters stored in each
o = Number of words to be accessed In the direction at right angles to the Initially
block include the starting address in display memory of
specified direction.
each display area, and its length. In addition, there are
DC = Drawing count parameter which Is one less than the number of RMW cycles to
be executed.
two mode bits for each area which specify whether the
OM = Dots masked from drawing during arc drawing.
area is a bit-mapped graphics area or a coded char'" = Needed only for word reads. .
acter area, and whether a 16-bit or a 32-bit wide display
Graphics Character Drawing
cycle is to be used for that area.
Graphics characters can be drawn into display memory
The other use for the PRAM contents is to supply the
pixel-by-pixel. The up to 8-by-8 character is loaded
pattern for figure drawing when in a bit-mapped
into the GOC's parameter RAM by the system micrographics area or mode. In these situations, PRAM bytes
processor. Consequently, there are no limitations on the
8 through 16 are reserved for this patterning informacharacter set used. By varying the drawing parameters
tion. For line, arc, and rectangle drawing (linear figures)
and drawing direction, numerous drawing options are
locations 8 and 9 are loaded into the Pattern Register
available. In area fill applications, a character can be
to allow the GOC to draw dotted, dashed, etc. lines. For
written into display memory as many times as desired
area filling and graphics bit-mapped character drawing
without reloading the parameter RAM.
locations 8 through 15 are referenced for the pattern or
character to be drawn.
Once the parameter RAM has been loaded with up to
Details of the bit assignments are shown on the following
eight graphics character bytes by the appropriate
PRAM command, the GCHRO command can be used 519 pages for the various modes of operation.
IAPD7220
Character Mode
RA-O
1
(I
I
'
0
0
2(1
-I
3
i
0
LENIL
WDI
•
i'
0
.
I'
•
.
DI.~loV P.rtilion A,oo 1
)
~ .'o,lIng odd,o.. wllh low'
SADI H
I
0
0
high olgnlll.on.o 11.ld.
(wo,d odd,...),
0
0
\
~
I LENIH
: : .:
.
.
r-
SAD2 L
R....4
0
o
I
LEN2L
WD2\
0
0
or
GCHR5
GCHR4
13
GCHR3
14
GCHR2
15
GCHRI
SYNC:
0
0
o
I
LEN3L
10
11
r-
SAD3 L
WD3\
DllpilY Pertliion 3
llartlng Idd,... Ind
length
0
0
0
CCHAR:
a
a
1
START:
o
0
14
15
starting address and
r- length
SAD4 L
0
o
I
SAD4H
LEN4L
W04\
0
\
I
0
0
I
DE
ZOOM:
Display Partltlon 4
R.... ,2
DE
o
LEN3 H
0 \
I
M
BeTRL:
13
charactsr drawing,
o
SAD3H
I
Graphics charactsr bylas
be moved Into display
r-- to
memory wlth graphics
[/
I
o l'
I
I
o
0
VSYNC:
RMI
Pattern of 16 bits used for
flgure drawing to pattern
dotted, dashed, etc, line••
Command Bytes Summary
RESET:
0
~
GCHR7
11
LEN2H
0 \
PTNH
GCHR8
12
SAD2H
I
or
GCHR6
A Wide DlopllV oV.I. wldlh
0111N0 wordl pe' .... mooy cy.l.
I. Mllcted lor Ihl. dl.pllV
.... Illhl. bill. nllo • 1.
Tho dl.pl.V Idd .... count., I. thin
Inc,.mlnled by 2 lor I •• h dllpllV ICln cy.ll,
Olh., mllIIOfY oV.11 typel I .. not Inllu.nced,
Display PertHlon 2
IWrtlng Idd.... lnd
length
PTNL
Rlrl0
L.ngth 01 DI.pl.V Portilion 1
(lino count) with high ond
low .Ignlll.on •• 11.ld.,
t
0
d
SADI L
./
CURS:
0
0
PRAM:
SA
LEN4H
PITCH:
Graphics and Mixed Graphics and Character Modes
R....O
2
3
r---------------,
SADI
L
I----'-_"-----'-_"---L~_...............__II :::::(;!~ ~~,:~),Iflcanca
I
\ I
WDI
o a
LEN1 L·
~
I-- ~~I~~~I~':llr~hcounl),
LENIH
MASK:
1\
FIGS:
(l~
Display Partltlon Area 2
I
\
0
o
I
I
CURD:
I
o
I
LPRD:
I
o
1
DMAR:
I
DMAW: .
I
SAD2 H
LEN2H
520
.9
RDAT:
bli. as In a'ea 1.
SAD2 M
t
GCHRD:
ltarting add,ess and
I-- length
with Image ldentlly
SAD2 L
WD211M
alMoD
FIGD:
In mixed mode, a 1 Indicate. an
Image 0' g'"phlcs Irea, and I 0
' - - - - - - - - - - - Indlcale. a cha,acler arel, In
g,aphlcs mode Ihls bll mus, be O.
LEN2L
TYPE
l.&ngthOIDlBPlaYPlrtilion
1M
R....4
'1
WDAT:
Dlnplay PartlUon Area 1
Itsrtlng add.... with low,
1
1
0
'1
1
1
I
I
I 01
TYPE
TYPE
o
I
I
1
1
~-
MOD
0
TYPE
~J;
I
I
MOD
MOD
I
1-\
",PD7220
Modes ot Operation Bits
Video Control Commands
Reset
~G:o.o.o.o.o.o
C G
Blank the dleplay. enter
Idle mode, and InlHallze
within the ODe:
-FIFO
- Command Proceaaor
01
-Intemal Counters
This command can be executed at any time and does not
modify any of the parameters already loaded into the GDC.
If followed by parameter bytes, this command also sets the
sync generator parameters as described below.
Idle mode is exited with the START command.
PI
Mode 01 Opera~on select bUs.
Seebalow.
P2
Active Olepley Words per line - 2. Must
be .ven number with lilt 0 =
o.
Horlzontel Sync Width -1
Vertical Sync WlcIIh, low blta
VS H
CHFP,
"
PS
PS
P7
P8
~
o
0
\;
VertIcal Sync WIcIIh, high bIta
HBP
~ Horizontal Back Porch Width -1.
VFP
I-- Vartlcal Front Porch WlcIIh
low bits
I
Mixed Graphics & Character
1
Graphics Mode
1
0
Character Mode
1
1
Invalid
Video Framing
0 0
Nonlnterlaced
0 1
Invalid
1 0
Interlaced Repeat Field for Character Displays
1 1
Interlaced
2 Field Sequence with V21ine offset between otherwise identical
fields.
Interlaced Framing:
2 Field Sequence with V2 line offset.· Each field displays alternate
lines.
Noninterlaced Framing: 1 field brings all of the information
to the screen.
f-- A~ve Display Unea per VIdeo field,
AL H .
0
0
Repeat Field Framing:
Horizontal Front Porch Width -1.
AI. L
CV~P
l--
0
I S
P3
P4
Display Mode
f-- A~ve
Total scanned lines in interlace mode is 'Odd. The sum
of VFP + VS + VBP + AL should equal one less than
the desired odd number of lines.
Display Unas per VIdeo field,
hlghblls
Vertical Beck Porch WlcIIh
In graphics mode, a word is a group of 16 pixels. In character mode, a word is one character code and its attributes, if
any.
The number of active words per line must be an even number from 2 to 256.
An all-zero parameter value selects a count equal to 2"
where n = number of bits in the parameter field for vertical parameters.
All horizontal widths are counted in display words.
All vertical intervals are counted in lines ..
D
Dynamic RAM Refresh Cycles Enable
0
No Refresh - STATIC RAM
1
Refresh -
Dynamic RAM
Dynamic RAM refresh is important when high display zoom
factors or DMA are used in such a way that not all of the
rows in the RAMs are regularly accessed during display
raster generation and for otherwise inactive display
memory.
SYNC Oenerator Period Constraints
Horizontal Back Porch Constraints
1. In general:
HBP ;;?; 3 Display Word Cycles (6 clock cycles).
2. If the IMAGE or WD modes change within one
video field:
HBP ;;?; 5 Display Word Cycles (10 clock
cycles).
Horizontal Front Porch Constraints
1. If the display ZOOM function is used at other than
1X:
HFP ;;?; 2 Display Word Cycles (4 clock cycles).
2. If the GDC is used in the video sync Slave mode:
HFP
;;?; 4 Display Word Cycles (8 clock cycles).
3. If the Light Pen is used:
HFP ;;?;6 Display Word Cycles (12 clock
cycles).
Horizontal SYNC Constraints
1. If Interlaced display mode is used:
HS ;;?; 3 Display Word Cycles (6 clock cycles).
F
Drawing Time Window
o
Drawing during active display time and retrace blanking
Drawing only during retrace blanking
Access to display memory can be limited to retrace blanking intervals only, so that no disruptions of the image are
seen on the screen.
SYNC Format Specify
SYNC:
10
00
IloEI'
L-.... Th. dlepl.y I. enabled by
'--'-----"-.L...--L---"---'----'..........
.1, _
521
blanked by a O.
IlPD7220
PI
Mode of Operation select bits. '
See below.
P2
Activi Dllplay Word. per Unl. MUlt
be Iven number with bit 0 = O.
P3
Cursor & Character Characteristics
HS
\
~
PI
DC
' - - - - HorIzontal Sync WlcIth
_ _ _ _ _ _ _ _ VertlC81 SyncWlclth, low bite
_-L-~I-- ~:~sor
P3
1- Steady Cursor
- - - ' - BUnk Rate, lower bits
~I--C-B~OT---.,...--B-RU-.....,~
!
HBP
Horizontal Back Porch WlcIth
P6
VFP
Verllca Front Porch WlcIth
I
PB
VBP
A~H
I--
L-...L...--'----".,..\--"_.L..-~__'____.J.
.L--_'________
Blink Rate, upper bits
Cursor Bottom line number in
the row
In graphics mode, LR should be set to 0,
The blink rate parameter controls both the cursor and
attribute blink rates. The cursor blink-on time = blink-off
time = 2 x SR (video frames). The attribute blink rate is
always Y2 the cursor rate but with a 3/4 on-% off duty cycle.
Active Display Unes per Video Field,
low bit.
P7
Top Une number in the
IL__~_____ o-Blinklng Cursor
[
~--'---'--'-'~\=====~-Horlzontal Front Porch Width
P5
Lines per character row
LI_B-+R_L--1...1s.c...JI'---'----'-CT_O....
P
V~H ~-Vertl';"1 Sync WlcIth, high bits
HFP
I----
LR
0
l ___________ DlsplayCursorifl
P2
P4
I I
Display Control Commands
Active Display Une. per Video FIeld,
high bits
Start Display & End Idle Mode
' - - - - - - - - V e r t l c a l Back Porch WlcIth
START:
This command also loads parameters into the sync
generator. The various parameter fields and bits are
identical to those at the RESET command. The GOC is
not reset nor does it enter idle mode.
I
0
, 1
, 1
,0
, 1
,1
,0
1
I
Display Blanking Control
~I'- ...I..-~----'---'-----''---.J...-0 ~D~EE
I'
~
..J.I
_0
Vertical Sync Mode
1_0--'---'-_'----'---'-_....l---LI~M--l1
l _ ().~~~p~~:::.~:~IC.I
The display 18 enabled
by a I, and blanked by
.0,
VSYNC: ...
Zoom Factors Specify
1-Generate 81 Output Vertical
Sync - Master Mode
,ZQ.QM:
When using two or more GDCs to contribute to one image,
one GOC is defined as the master sync generator, and the
others operate as its slaves. The VSYNC pins of all GDCs
are connected together.
PI
I
0
I
0
0
DlSP
I
r---
GCHR
ZOom factor for graphics
character writing
L----------------------~~factor
Slave Mode Operation
A few considerations should be observed when synchronizing two or more GOCs to generate overlayed
video via the VSYNC INPUT/OUTPUT pin. As mentioned above, the Horizontal Front Porch (HFP) must be
4 or more display cycles wide. This is equivalent to
eight or more clock cycles. This gives the slave GOCs
time to initialize their internal video sync generators to
the proper point in the video field to match the incoming vertical sync pulse (VSYNC). This resetting of the
generator occurs just after the end of the incoming
VSYNC pulse, during the HFP interval. Enough time
during HFP is required to allow the slave GOC to complete the operation before the start of the HSYNC
interval.
Once the GOCs are initialized and set up as Master and
Slaves, they must be given time to synchronize. It is a
good idea to watch the VSYNC status bit of the Master
GOC and wait until after one or more VSYNC pulses
have been generated before the display process is
started, The START command will begin the active
display of data and will end the video synchronization
process, so be sure there has been at least one VSYNC
pulse generated for the Slaves to synchronize to.
Zoom magnification factors of 1 through 16 are available
using codes 0 through 15, respectively.
Cursor Position Specify
CURS:
PI
P2
P3
1
I 0
I
I
I
dAD
C
I
EAD
~ Execute Word Address,Iow byte
EAD
~ Execute Word Address, . . - byte
I
0
!
0
I EA~
(Gn1phIcs_on/y)
Word Address, top bits
Dol Address _ n the_
In character mode, the third parameter byte is not needed.
The cursor is displayed for the word time in which the display scan address (OAO) equals the cursor address.
In graphics mode, the cursor word address specifies the
word containing the starting pixel of the drawing; the dot
address value specifies the pixel within that word.
522
IlPD7220
Parameter RAM Load
For byte writes, the unspecified byte is treated as all zeros
during the RMW memory cycle.
PRAM:~._I~._I~._I~I~~_S~A~~
In graphics bit-map situations, only the LSB of the
WDAT parameter bytes is used as the pattern in the
RMW operations. Therefore it is possible to have only
an all ones or all zeros pattern. In coded character applications all the bits of the WDAT parameters are used
to establish the drawing pattern.
The WDAT command operates differently from the other
commands which initiate RMW cycle act"ivity. It requires
parameters to set up the Pattern register while the
other commands use the stored values in the parameter
RAM. Like all of these commands, the WDAT command
must be preceeded by a FIGS command and its
parameters. Only the first three parameters need be
given following the FIGS opcode, to set up the type of
drawing, the DIR direction, and the DC value. The DC
parameter + 1 will be the number of RMW cycles done
by the GDC with the first set of WDAT parameters. Additional sets of WDAT parameters will see a DC value
of 0 which will cause only one RMW cycle to be executed.
•
C
~I
\--1tOI6byte810beIOSded
Inlo Ihe parameler RAM
r-.--------.....
i
:::'I~~~s:AMaddrass
~
Pn
From the starting address, SA, any number of bytes may
be loaded into the parameter RAM at incrementing
addresses, up to location 15. The sequence of parameter
bytes is terminated by the next command byte entered into
the FIFO. The parameter RAM stores 16 bytes of information in predefined locations which differ for graphics and
character modes. See the parameter RAM discussion for
bit assignments.
Pitch Specification
PI'
.
rI·
L........-'----'----J_-'---~--'---I~
Numberofwordaddrasaas
In display memory In the
horizontal dlrecllon
Mask Register Load
This value is used during drawing by the drawing processor
to find the word directly above or below the current word,
and during display to find the start of the next line.
The Pitch parameter (width of display memory) is set by
two different commands. In addition to the PITCH command, the RESET (or SYNC) command also sets the
pitch value. The "active words per line" parameter,
which specifies the width of the raster-scan display,
also sets the Pitch of the display memory. In situations
in which these two values are equal there is no need to
execute a PITCH command.
o __-
REPLACE with Pattam
I _
COMPLEMENT
o RESET to zaro
I_SETlol
' - - - - - - - - O a t a Transfer Type:
o _wo----_ _ _ _ Word, Low than High byle.
- ' - - - - - L o w Byle of the Word
•
High Byt. 01 the Word
•
Invilid
r~.--'-_L-.
W,OROL,or BVT, E
0
0'
I
~L
I
MH
I
f---1----
Low Significance byte
-High slgnlflcance byte
The Mask register is loaded both by the MASK command
and the third parameter byte of the CURS command. The
MASK command accepts two parameter bytes to load a
16-bit value into the Mask register. All 16 bits can be individually one or zero, under program control. The CURS
command on the other hand, puts a "1 of 16" pattern into
the Mask register based on the value of the Dot Address
value, dAD. If normal single-pixel-at-a-time graphics figure
drawing is desired, there is no need to do a MASK command at all since the CURS comm~nd will set up the
proper pattern to address the proper pixels as drawing
progresses. For coded character DMA, and screen setting
and clearing opertions using the WDAT command, the
MASK command should be used after the CURS command if its third parameter byte has been output.
RMW Memory cycle Logical
Operallon:
I-
Word Low Data Byte'or
r--- Single
Byte Data value
P2
r
WO,RD
L
__
Word transfer only:
elc.~
....---I._'----'----'.'----'----'---'---'!- --High Data Byte
PI
I
This command sets the value of the 16-bit Mask register of
the figure drawing processor. The Mask register controls
which bits can be modified in the display memory during a
read-modify-write cycle.
Write Data into Display Memory
o
PI
P2
Drawing Control Commands
I
I
MASK:
Figure Drawing Parameters Specify
---1.._.1.-.- - - , _ , , - -.....
FIGS:
H
Upon receiving a set of parameters (two bytes for a word
transfer, one for a byte transfer), one RMW cycle into Video
Memory is done at the address pointed to by the cursor
EAD. The EAD pointer is advanced to the next word,
according to the previously specified direction. More
parameters can then be accepted.
PI
I
0
I I
I
, 0
, 0
I
Drawing OlrKllon Ba..
Figura Type Seloct lit.:
'-------Lin. (Voctor)
Gr.phlc. Chlrleter
Arc/Clrel.
Rtctlngl.
Sllntld Grlphlc. Chlrleter
523
9
IAPD7220
~~~=~~~~=~~r-- ~-.-
:1'1
DC
L
~H
l.-...J-~==~~======:::::!-I
....
00
1
'or
Orlphlel Drlwlng fllg
UII In
Mlxld Orephlcl Ind ChI ...I.. Mode
:1========p
:1
:1
""1-00-------- 0
DL
o
I
Based on parameters loaded with the FIGS command, this
command initiates the drawing of the graphics character or
area filling pattern stored in Parameter RAM. Drawing
begins at the address in display memory pointed to by the
EAD anc;l dAD values.
Data Read Commands
Read Data from Display Memory
Drlwlng ""rameler
I
RDAT:I'
DH
,
D2H
,
~~~~~rOIL
I
D1H
,
t--
01 Drawing Parameter
OM Drlwlng Paramaler
dillerenlinierprelations 'or
different figure types.
!!
~ GC
1.
o
0
0
0
0 Character Display Mode Drawing,
Individual Dot Drawing, DMA, WDAT,
and RDAT
o
0
0
0
o
o
0
0
o
MOD
Data Tran.' .. Type:
0"
Word, low then high byte
o •
Low Byte of the Word only
1 ..
High Byte
1 ..
InYalid
0'
the Word only
Cursor Address Read
Valid Figure Type Select Combinations
SL
I°I
Using the DIR and DC parameters of the FIGS command
to establish direction and transfer count, multiple RMW
cycles can be executed without specification of the cursor
address after the initial load (DC = number of words or
bytes).
As this instruction begins to execute, the FIFO buffer direction is reversed so that the data read from display memory
can pass to the microprocessor. Any commands or parameters in the FIFO at this time will be lost. A command byte
sent to the GDC will immediately reverse the buffer direction back to write mode, and all RDAT information not yet
read from the FIFO will be lost. MOD should be set to 00
if no modification to video buffer is desired.
The peramalerslake on
-
~:ll!l,1
Operation
,0,0,0,0,01
The following bytes are relurned by the GDC:
PI
A7
Execute Address (EAD), Low Byte
P2
A1S
Execute Address (EAD), Middle Byte
Straight Line Drawing
o
000
J:
°
D2L
o
-r;PE
Graphics Character Drawing and
Area filling with graphics
character pattern
0
0 Arc and Circle Drawing
0
0 Rectangle Drawing
P3
Execute Address (EAD), High Bits
~""-"""""'"
Dot Address
0
0 Slanted graphics character
drawing and slanted
area filling
Only these bit combinations assure correct drawing
operation. .
.
The Execute Address, EAD, points to the display memory
word containing the pixel to be addressed.
The Dot Address, dAD, within the word is represented as a
1-of-16 code for graphics drawing operations.
Light Pen Address Read
Figure Draw Start
~~ 10,1,',0,'
(dAO)~ High Byte
11
"
,
°1
The following byte. are returned by the a DC:
01
I
On execution of this instruction, the GDC loads the parameters from the parameter RAM into the drawing processor
and starts the drawing process at the pixel pointed to by the
cursor, EAD, and the dot address, dAD.
A7
LA?L
AO
~-
r--
1
....A_1S--'----'-_'--LA
.....O....;M--'-_'----',_A---'S
Light Pen Address, Low Byte
Light Pen Address. Middle Byte
LI_o--'----'-_'---'----'-_O_LI_LA--"...;OH:....JI--- Light Pen Address. High Bits
Graphics Character Draw and· Area Filling Start
The light pen address, LAD, corresponds to the display
word address, DAD, at which the light pen input signal is
detected and deglitched.
524
J.(PD7220
The light pen may be used in graphics, character, or mixed
modes but only indicates the word address of light pen
position.
AC Characteristics
t.A
DMA Read Request
= OOC to 70°C; Vcc = 5.0V ± 10%j GND = OV
,Read Cycle
S~mbol
~>---------Dala 'll'anslerType:
o --o--------Word,Lowlhenhlghbyte
0 __1 - -_ _ _ _ _ _ Low Byte 01 the Word
-_0-------- High Byte 01 the Word
1
CPU)
Limits
~ ~._O~__~T_V~PE__~1_1_\~M_O~D~
1
(GDC -
•
Invilid
Parameter
Max
Min
Addreas Setup to
tRA
Addreas Hold from RDt
tRR1
PO Pulse Width
tRD1
Data Delay from
tDF
Data Floating from RDt
tRCY
RD Pulse Cycle
Test
Conditions
ns
RD~
tAR
Unit
na
tRD1 + 20
RD~
80
na
80
na
100
na
Cl
= 50pF
na
4tClK
DMA Write Request
DMAW:~.o~__1~I__T~v_PE~I~1~I__M_O~D~1
£
o
Write Cycle
CPU)
rlml,s
REPLACE with Plttern
1 __ COMPLEMENT
0_
Mln-
Parameter
S);mbol
Addreas Setup to
tWA
Address Hold from WRf
1_SETloDne
tww
Wi!! Pulae Width
o - . _ - - - - - W o r d , Low than high byte
o - . _ - - - - - L o w Byte 01 tha WOrd
•
Max
Unit
ns
100
n.
na
tDW
Data Setup to WRf
80
tWD
Data Hold 'rom WRt
0
tWCY
WR Pulse Cycle
na
ns
4tClK
High Byte oltha Word
1 -.o__----Invilid
DMA Read Cycle
(GDC -
CPU)
Limits
Symbol
Absolute Maximum Ratings * (Tentative)
Ambient Temperature under Bias
ooC to 70°C
Storage Temperature
- 65°C to 150°C
Voltage on any Pin with respect to Ground
-0.5Vto
Power Dissipation
+7V
1.5 Watt
*COMMENT: Exposing the device to stresses above
those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be
operated under conditions outside the limits described
in the operational sections of this specification. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
DC Characteristics
ta
= O°C to 70
0
Cj
Parameter
Input low Voltage
Input High Voltage
Output low Volta"e
Output High Voltage
Input low leak Current
Input High leak Current
Output low leak Current
Output High leak Current
Clock Input low Voltage
Clock Input High Voltage
_VCC Supply Current
Capacitance
ta = 25°Cj vec
Symbol
Vil
VIH
VOL
VOH
III
IIH
10l
10H
VCl
VCH
ICC
= GND
h1Put Capacitance
110 Capacitance
Output Capacitance
Clock Input Capacitance
Min
tKR
i:iACK Setup to RD~
tRK
DACK Hold 'rom RDt
tRR2
RD Pulse Width
tRD2
Data Delay from
tREQ
DREQ Delay 'rom 2XCClKt
tQK
DREQ Setup to
DACK Pulse Cycle
tKQ(R)
DREQ
Delay from
na
na
Cl = SOpF
120
ns
Cl = SOpF
na
ns
tClK
ns
4tClK
DACK~
DMA Write Cycle
=
± 10%; GND
Min
-O.S
2.0
= OV
2 tClK + 120
(GDC -
Limits
Max
0.8
VCC + O.S
0.4S
2.4
-O.S
3.9
-10
+10
-10
+10
0.6
VCC + 1.0
270
Unit
V
V
V
V
,..A
,..A
,..A
,..A
V
V
Teat Condltlona
ns
Cl = SOpF
Unit
Test
Conditions
CPU)
10l
10H
VI
VI
Vo
Vo
Min
DACK Setup to
tWK
DACK Hold from WRf
tKQ(R)
DREQ
R/M/W
Cycle
~
Max
ns
WR~
tKW
Delay 'rom
ns
DACK~
tClK + 120
na
Cl = SOpF
= 2.2 mA
= -400,..A
= OV
(GDC -
= VCC
Display Memory)
llm7ts
= ov
s);mbol
= VCC
Parameter
Min
tAD
Address/Data Delay
from 2XCClKt
tOFF
Address/Data Floating
from 2XCClKt
10
tDIS
Input Data Setup to
40
Max
Unit
Teat
Conditions
130
na
Cl = SOpF
na
CL = 50pF
130
na
2XCClK~
OV
Symbol
Parameter
Symbol
Teat
Conditions
1.S tClK + 80
DACK~
DACR' High level Width
Unit
na
RD~
tDK
~
Max
tRD2 + 20
tE
tOIH
Parameter
Parameter
Limits
= 5V
vcc
Teat
Conditions
ns
WR~
tAW
o __ RESET 10 Zero
1 - - - - - - - Dalll 'll'ansl.rType:
1
(GDC -
RMW Memory Logical Operation:
.J:1aJJJL.
Min
Input Data Hold from
na
2XCClK~
Max
Unit
CIN
CVO
10
20
pF
pF
COUT
C+
20
20
pF
pF
Test Condltlona.
tOBI
fc = 1 MHz
V1
(unmeasured) = OV
525
90
OBIN Dalay 'rom
2XCClK.
ns
Cl = 50pF
tRR
AlEt Delay 'rom
2XCClKt
30
110
ns
Cl = SOpF
tRF
ALE. Delay 'rom
,.xCCLK.
20
90
ns
CL=SOpF
tRW
ALE Width
1/3tClK
CL = SO pF
m
JAPD7220
Display Cycle
(GDC - Display Memory)
Llmltll_
Symbol
tvo
Parametar
Min
Video Signal Delay
from 2XCClKt
Input Cycle
Max
Unit
Teat
Conditions
120
nl
Cl·50pF
(GDC - Display Memory)
Tnt
Condltlonl
Limit'
Symbol
Parameter
tps
Input Signal Setup to
2XCClKt
tpw
Mllx
Min
Unit
20
na
Input Signal Width
tClK
na
Parameter
Min
Clock
LImits
Symbol
Dax
T881
Conditions
Unit
tCR
Clock Rlae Time
10
ns
tCF
Clock Fall Time
10
nl
tCH
Clock High Pulae Width
95
nl
tCl
Clock low Pulse Width
,95
ns
tClK
Clock Cycle
200
nl
2000
Timing Waveforms
Display Memory RMW Timing
Microprocessor Interface Write Timing
AO:
Valid
Invalid
Invalid
Valid
1
f
-----:-~:~-;--rAw
WR: _____________
1WA
tww
t
080"'7:
Invalid
I
~
Invalid
tWCy'------------------~
I
526
IlPD7220
Timing Waveforms (Coni.)
Microprocessor Interlace Read Timing
AO:
Invalid
:xt
~___I_nv_a_lId_ _J)(~
Valid
_______
-----"J'tAR
AD:
080"'7:
-------+1
High Impedance
High Impedance
t---------tRCy'--------
Microprocessor Interlace DMA Write Timing
2xWCLK:
OREQ:
-~EQ~
J~tQK
DAC'R:
WR:
Microprocessor Interlace DMA Read Timing
2xWCLK:
OREQ:
DACR:
~
tQK
im:
High Impedance
527
",PD7220
Timing Waveform_IConl.)
Display Memory Dlspl.y Cyc/et Timing
2xWClK:
ADO"'15:
--:--<1
A111, A17:
Light Pen and External Sync Input Timing
2xWCLK:
LPEN'_~··
EX. SYNC:
_
._;.....-_ _ __
tpw
Clock Timing
tCR
tCF
-'I..------'VCH .. 3;9
VCl .. 0.8
Test Level (for AC Tests)
2.0_
...-- 2.0
MISCELLANEOUS:~0.8
_
Test Pol"t_ 0.8
528
x=
VOH.2.0
VIH .. 2.0
VOL .. 0.8
Vll .. 0.8
::!
Video Sync Signals Timing
a
5'
CD
•••
c
2xWCLK:
H BLANK:
I~
.
1H
-,
i
Jl.Jl.Jl...ILJL ____ . __ ~ ____ .n..n..r-.. --JlJL ___ JL ~
J
---------1
..r f
..
------ _ .:...
_______________________
_______________________r
-~
H SYNC:
AD0-15:
-:J.
c..::::::)
I
c.:::-:J
I
(:::_::J.
:-.-___L
I
I
1
LC0-4:
I
~1 H
_
_ ______ - - - - - - - - - - - - - - -
X
..J
~ ;hx--------------:pI::::_
::::-r::JJ:X::~::: :-.: :-:.: ---_:::__ ____ ::.:____-:JJ:::J:£::--xr::.
!
___
_
_________________
___
I
C1I
ADO-15:
I\)
(0
-x-= ___-:x=.. ___
I
LC0-4:
___
~_
I
ROW:
ROW:
-------_______________
I
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ .J
C~:~~-;
f
I
X
L- _________
V BLANK:
V SYNC:
__:.::::x::..
C
~I
j
~
----------
f ~----------------------------------------------------
i
1 V (FRAME)
4
::_~I
_uL
..
I
'l:
-a
a--..
N
N
o
EJ
/JPD7220
Timing Waveforms (Cont.)
Interlaced Video riming
HBLANK:
JL1-: . . •
VBLANK:
JLJL.s---::: -fLIL:::-fLIL::: JL
: ··· __ JL ::: -fYL::-_-f-r1L:::
I
•
• ___
.
•
L
i';
~
VSYNC:
(INTERLACE)
i ..
ODD' FIELD
__ • • -
r
•
I
I
•
:i
I
I
•
,
'L-
EV~N FIELD --i---------<-
j•
VSYNC:
(NO INTERLACE)
Video Sync Generator Parameters
~1"------------------1H----------------~'1
HBLANK:
~
---.J
________________________________________________________ ,
~r--
,
~~----____~:~________________________________________________________________~_
HSYNC:
,
--1 HFP
I
-,
I
I
I
:
:
I
I
t- HBP .....
I
I
+-/.....- - - - - -
I
C/R - - - - - - - - -..........,
.---iHSt-1~4~~-----------------------1V------------~.~1
VBLANK:
,
,
I
VSYNC:
:
~------~------------------------------------------------~I--------~~~------------~-,
,
I,
I,
I
'I
--t
t--VBP-l.......
, ...- - - - L/F -----------~......I
VFP ........ '
:
J..-VBP ~
I
I
I
I
I
~vsl--
530
",PD7220
Timing Waveforms (Cont.)
Display and RMW Cycl.s (1 x Zoom)
Display
Cycle
---If---D2---l--
2xWCLK:
ALE:
DBIN:~~--------~--------~~------~------~
ADIH5:
A18, 17:
-~"------------------+-t""------------------------------H-"------------
H~r=~;_-:~::::::~---------~----~~--------------------~--~~-----VlEXT SYNC:
Display and RMW Cycl.s (2x Zoom)
ADO-15:
L1°"..........·
'-----I
I~
Input Data
>---<
Output Addre..
I
Output Data
>-<
IX
Output Addre..
A18,17:
j
J
I
i
531
r
Output Addre..
I
,
IJPD7220
Timing W.v.forms (Cont.)
Zoomed Display Operation with RMW Cycle (3x Zoom)
2xWCLK:
ALE:
91N:
Output Addr...
Output Addr...
Input Data
AO~15:--~~::::~--------------------------------~::::::~--~::::::)-~:
A18.17:~~
______________________________________
BIMk:~~~
~~
____________________________________
______________________________________
~J
532
Output Addr...
~~
________
/JPD7220
Video Field Timing
~~______________~HS~Y~N~C~O~U~TP~U~T________________ ~
~f~:-:,------~
:
~
________~B~~~N~K~O~U~T!P~UT~
_____________ ~
---+------
VERTICAL SYNC LINES
I
-- -------
VERTICAL BACK PORCH BLANKED LINES
1
HORIZONTAL
SYNC
PULSE -~
HORIZONTAL
FRONT PORCH- ~
BLANKING
,
S
AS
o
0
(.)
z
~
ACTIVE
DISPLAY
LINES
HORIZONTAL
BACK PORCH
BLANKING
~
~
~
~
VERTICAL FRONT PORCH BLANKED LINES
~
Drawing Intervals
DRAWING INTERVAL
ADDITIONAL DRAWING INTERVAL WHEN IN FLASH MODE
DYNAMIC RAM REFRESH IF ENABLED, OTHERWISE
ADDITIONAL DRAWING INTERVAL
DMA Reque.t Intervals
DMA REQUEST INTERVAL
ADDITIONAL DMA REQUEST INTERVALS WHEN IN FLASH MODE
533
",PD7220
Pin Identification
Pin Configuration
PIn
No.
IWftIIboI
2xWCLK
IN
Clock Input
DiiN
OUT
Display Memory Relld Input Flag
HSYNC
OUT
Horizontal Video Sync Output
VlEXT SYNC
IN/OUT
Vertical Video Sync Output or External VSYNC Input
BLANK
OUT
CRT Blanking Output
AU~(RAS)
OUT
Addr... Latch Enable Output
ORQ
OUT
DMA Requllt Output
DACK
IN
DMA Acknowledge Input
RD
IN
Read Strobe Input for Mlcropl'OCllllOr Interface
10
ViR
IN
Write Strobe Input for Microprocaaaor Interface
11
AO
IN
Addre.. Select Input for Mlcroprocesaor Interf_
IN/OUT
Bidirectional Data Bus to Host MlcroproceB8or
IN
Light Pen Detect Input
22-34 ADO to 12
IN/OUT
Addre.. and Data LInes to Display Memory
35-37 AD13 to 15
IN/OUT
Utilization Varl.. with Mode of Operation
A16
OUT
Utilization Varl.. with Mode of Operation
39
A17
OUT
Utilization Varle. with Mode of Operation
40
Vee
12-19 D80to 7
20
GND
21
LPEN
38
2xWCLK
DBIN
HSYNC
V/EXTSYNC
BLANK
ALE
ORO
DACK
AD
WR
AO
DB-O
DB-1
DB-2
DB-3
DB-4
DB-5
DB-6
DB-7
GND
Function
Direction
Ground
+5V ± 10%
Character Mode Pin Utilization
N_.
PIn
No.
.35-37 AD13 to 15
Direction
Function
OUT
LIne Counter Bits 0 to 2 Outputs
38
A18
OUT
LIne Counter Bit 3 Output
39
A17
OUT
Cureor Output
Mixed Mode Pin Utilization
PIn
No.
NIIIII.
35-37 AD13 to 15
DIrection
IN/OUT
Function
Addr... ancl Data Bits 13 to 15
38
A18
OUT
Attribute Blink and Clear Line Counter' Output
39
A17
OUT
Cursor and BII-Map Area' Flag Output
* = Output during the HSYNC interval. Use the trailing edge at
HSYNC to clock this value into a flop for reference during the rest of
the video line.
Graphics Mode Pin Utilization
PIn
No.
DIrection
35-37 AD13 to 15
IN/OUT
Function
Addrellland Data ISIts 13 to 15
38
A16
OUT
Addre.. Bit 16 Output
39
A17
OUT
Addre.. Bit 17 Output
534
vee
A-17
A-16
AD-15
AD-14
AD-13
AD-12
AD-11
AD-10
AD-9
AD-8
AD-7
AD-6
AD-5
AD-4
AD-3
AD-2
AD-1
AD-O
LPEN
J,lPD7220
Block Diagram of a Graphics Terminal
CLOCK
~P07220
GDC
080-7
HOST
COMPUTER
535
/JPD7220
Package Outlines
IAPD7220D
Hi
B~
I I
I
.
C=:
~o,r
J
G
M
Ceramic
ITEM
MILLIMETERS
INCHES
A
B
C
0
E
51.5 MAX
1.62 MAX
2.54±0.1
0.5 ± 0.1
48.26 ± 0.1
1.02 MIN
3.2 MIN
1.0MIN
3.5 MAX
4.5 MAX
15.24 TYP
14.93 TYP
0.25 ± 0.05
2.03 MAX
0.06 MAX
0.1 ± 0.004
0.02 ± 0.004
1.9 ~ 0.004
0.04 MIN
0.13MIN
0.04 MIN
0.14 MAX
0.18 MAX
0.6 TYP
0.59 TYP
0.01 ± 0.0019
F
G
H
I
J
K
L
M
IlPD7220C
1r~1
.
T':J
l ~.
:=±ci
II
~I=
H,
A
I
.
tI!I-
•
~
~D
'
-j C
'.
I
_1 _ _ _ _ _
_
M
0" - 15°
>--
Plastic
ITEM
MILLIMETERS
A
51.5 MAX
B
2.54
D
0.5
E
48.26
F
2.028 MAX
0.064
1.62
C
~
INCHES
!
0.1
0.10 ± 0.004
0.1
0.019 ± 0.004
1.9
1.2 MIN
0.047 MIN
G
2.54 MIN
0.10MIN
H
0.5 MIN
0.019 MIN
I
5.22 MAX
0.206 MAX
J
5.72 MAX
0.225 MAX
K
15.24
L
13.2
M
0.25
0.600
0.520
+ 0.1
0.05
0.010
+ 0.004
0.002
7220DS-REV2-2-82-CAT
536
JAPD7225
INTELLIGENT ALPHANUMERIC
LCD CONTROLLER/DRIVER
t-IEC
NEe Electronics U.S.A. Inc.
MicrocompllIter Division
Pin Configuration
Description
The ~PD7225 is an intelligent peripheral device designed
to interface most microprocessors with a wide variety of
alphanumeric LCDs. It can directly drive any static or
multiplexed LCD containing up to 4 backplanes and up
to 32 segments and is easily cascaded for larger LCD
applications. The ~PD7225 communicates with a host
microprocessor through an 8-bit serial interface. It
includes a 7-segment numeric and a 14-segment alphanumeric segment decoder to reduce system software
requirements~ The ~PD7225 is manufactured with low
power consumption CMOS process allowing use of a
single power supply between 2.7V and 5.5V and is
available in a space-saving 52-pin flat plastic package.
57
520
521
25
56
55
42
24
523
43
23
54
524
44
22
53
525
45
21
52
526
46
522
I~eatures
41
IlPD7225
51
527
47
19
50
528
48
18
COM3
529
17
COM2
530
16
COMI
15
COMo
0
531
[J Single-chip LCD Controller with Direct LCD Drive
[J Low-cost Serial Interface to most Microprocessors
[J Compatible with:
7-Segment Numeric LCD Configurations-up to 16
Digits
14-Segrnent Alphanumeric LCD Configurations-up
to 8 Characters
[J Selectable LCD Drive Configuration:
Static, Biplexed, Triplexed, or Quadriplexed
[J 32-Segment Drivers
[J Cascadable for Larger LCD Applications
[J Selectable LCD Bias Voltage 'Configuration:
Static, 112, or 1/3
[J Hardware Logic Blocks Reduce System Software
Requirements
- 8-Bit Serial Interface
- Two 32 x 4-Bit Static RAMs for Display Data and
Blinking Data Storage
- Programmable Segment Decoding Capability
- 16-Character, 7,.Segment Numeric Decoder
- 64-Character, 14-Segment USASCII Alphanumeric Decoder
- Programmable Segment Blinking Capability
- Automatic Synchronization of Segment Drivers
with Sequentially Multiplexed Backplane Drivers
[J Single Power Supply, Variable from 2.7V to 5.5V
[J Low Power Consumption CMOS Technology
[J Extended - 40°C to + 85°C Temperature Range
Available
[J Space-saving 52-Pin Flat Plastic Package
20
Cll
N~888
-
N
M
NC
lu _ IV>
~
I. .
~
o¥
...J
...J...J ...J
0
I:::>
w
UU'»»»(/)VlUCDUcr:
1>-
! Pin
I:l
12
Description
Pin
No.
3-5
7,33
537
'unction
Symbol
CL2
System clock output (active high). Connect to CL1 with
180kQ re,l,tor, or leave open.
SYNC
Synchronlzallon pon (acllve low). For multlchlp oparatlon
lie all SYNC line, together.
VLCD1'
VLCD2'
VLCD3
LCD bla, voltage ,upply In puIs to LCD vollege conlroller.
Apply approprlale vollage. from I voltagl ladder connected across VDD'
VSS
Ground.
VDD
Power supply positive. Apply ,Ingle voltage ranging from
2.7V 10 5.SV for proper operallon.
sCK
Serial clock Input (active low). Synchronize. 8-bll .erlll dall
tran.fer from mlcroproe88lOr 10 "PD7225.
SI
Serialinpul (active high). Dltl InpU1 from mlcroprocelaor.
10
CS
Chip select Inpul (active low). Enlble. "PD7225 for dill
Input from mlcroproce.aor. Display can alao be updlted
when "PD7225 Is deselected.
11
BUSY
Bu,y output (acllve low). Handshake line Indicate. that
"PD7225 Is ready 10 receive naxt dlla byte.
12
C/O
Command/data Hleet Input (active both high Ind low).
DI.tlngul.he, serially Input dati byte I. a command or a.
dl.play dltl.
13
RESET
Re.et Input (acllve low). RIC circuit or pulse Inltllllze.
"PD7225 after power-up.
14
NC
No connection.
15-18
COMO-COM3
LCD Backplane Driver OutpU1•.
19-32,
34-51
SO-S31
LCD Segment Driver Outpul •.
52
CL1'
Sy.tem clock Input (active high). Connecllo CL2 with
180kQ re.l.tor, or to external clock lOurce.
m
JAPD7225
Block Diagram
COMO-COM3
LCD Driver
32
Display latch
32
VDD
VlCD,
LCD
Voltage
Controller
VlCD2
VlCD3
32 x 4 Bit
Display RAM
Segment
Decoder
32x4Blt
Blinking RAM
Vss
Cl, - :
Cl2
Clock
-----IL....__O_Sc_lII_ato_r_...J
RESET _
Buller
Interface
Controller
Command
Decoder
Serial Interface
cs
C/O BUSY
SI
SCK
Command Summary
In.tructlon Cod.
Blne..,
Commend
1. MODE SET
D••crlptlon
Initialize the ~PD7225. including selection of:
1) LCD Drive Configuration
2) LCD Bias Voltage Configuration
3) LCD Frame Frequency
HEX
D7 D. D. D. D:a D. Dt D.
0
0
0 4 0 3 O2 0, Do 40-5F
2. UNSYNCHRONOUS DATA Synchronize Display RAM data transfer to
TRANSFER
Display Latch with CS
0
0
0
0
0
3. SYNCHRONOUS DATA
TRANSFER
Synchronize Display RAM data transfer to
Display Latch with LCD Drive Cycle
0
0
0
0
0
4. INTERRUPT DATA
TRANSFER
Interrupt Display RAM data transfer to
Display Latch
0
0
0
0
5. LOAD DATA POINTER
Load Data Pointer with 5 bits of Immediate
Data
6. CLEAR DISPLAY RAM
Clear the Display RAM and reset the Data
Pointer
7. WRITE DISPLAY RAM
Write 4 bits of Immediate Data to the Display
RAM location addressed by the Data
Pointer; Increment Data Pointer
8. AND DISPLAY RAM
Perform a Logical AND between the Display
RAM data addressed by the Data Pointer
and 4 bits of Immediate Data; Write result to
same Display RAM location. Increment Data
Pointer
538
0
30
31
0
38
D4 D3 D2 D, Do EO-FF
0
0
0
0
0
0
0
0
20
0
D3 D2 D, Do DO-DF
0
D3 D2 D, Do 90-9F
",PD7225
Command Summary CCont.)
Instr__ ctlon Code
HEX
Binary
Command
9. OR DISPLAY RAM
D.scrlptlon
Perform a Logical OR between the Display
RAM data addressed by the Data Pointer
and 4 bits of Immediate Data; Write result to
same Display RAM location; Increment Data
Pointer
0
1
0 3 O2 0 1 Do BO-BF
10. ENABLE SEGMENT
DECODER
Start use of the Segment Decoder
0
0
0
0
0
11. DISABLE SEGMENT
DECODER
Stop use of the Segment Decoder
0
0
0
0
0
15
0
14
12. ENABLE DISPLAY
Turn on the LCD
0
0
0
0
0
0
13. DISABLE DISPLAY
Turn off the LCD
0
0
0
1
0
0
0
0
10
14. CLEAR BLINKING RAM
Clear the Blinking RAM and reset the Data
Pointer
0
0
0
0
0
0
0
0
00
15. WRITE BLINKING RAM
Write 4 bits of Immediate Data 'to the Blinking
RAM location addressed by the Data
Pointer; Increment Data Pointer
0
0
0 3 O2 0 1 Do CO-CF
16. AND BLINKING RAM
Perform a Logical AND between Blinking
RAM data addressed by the Data Pointer
and 4 bits of Immediate Data; Write result to
same Blinking RAM Location; Increment
Data Pointer
0
0
0
0 3 O2 0 1 Do BO-BF
17. OR BLINKING RAM
Perform a Logical OR between Blinking
RAM data addressed by the Data Pointer
and 4 bits of Immediate Data; Write result to
same Blinking Location; Increment Data
Pointer
0
0
0 3 O2 0 1 Do AO-AF
·IB. ENABLE BLINKING
Start Segment Blinking at the Frequency
Specified by 1 bit of Immediate Data
0
0
0
0
19. DISABLE BLINKING
Stop Segment Blinking
0
0
0
0
T.
. Do 1A-1B
0
0
1B
= -10°C to + 70°C; VDD = +5.0V:t 10%
LImit.
Parame'.r
Absolute Maximum Ratlnls *
=21°C
Supply Voltage, VOO
All Inputs and Outputs with Respect to VSS
Storage Temperature
IOperatlng Temperature
11
DC Characteristics
Details of operation and application examples can be
found in the "",PD7225 Intelligent Alphanumeric LCD
Controller/Driver Technical ManuaL"
T.
DJ D. D. D4 Da D. Dt D.
- O.3V to + 7.0V
- O.3V to VOO + O.3V
-65°eto + 150 0 e
-10 o e to + 70 0 e
Symbol
input Voltage
High
VIH
Input Voltage
Low
VIL
MIn
Typ
0.7 VOO
T••,
Max
Unit
VOO
V
0.3
VOO
V
Condition.
,..A
VIH = Voo
,..A
VIL - OV
V
BUSY. SVN'C.
10H ~ -101lA
Input Leakage
Current High
ILiH
Input Leakage
Current Low
ILIL
Output Voltage
High
VOH
Output Voltage
Low
VOLl
0.5
V
iIDS'l. 10L
VOL2
1.0
V
§9m!. 10L - 900 IIA
,..A
VOH - VOO
·COMMENT: Stress above those listed under "AbsoIlute Maximum Ratings" may cause permanent damage
Ito the device. This is a stress rating only and functional
operation of the device at these or any other conditions
;above those indicated in the operational sections of this
:specification is not implied. Exposure to absolute max"mum rating conditions for extended periods may affect
device reliability.
Output Leakage
Current Low
539
-2
VOO -0.5
ILOH
ILOL
Output Short
Circuit Currant
lOS
Backplane Orlver
Output Impedence
RCOM
Segment Orlver
Output Impedence
RSEG
Supply Current
100
100
- 100 "A
-2
,..A
VOL - OV
-300
IIA
SYNC. VOS - 1.0V
kQ
COMO-COM3.
VOO > VLCO'
Applle. to .tatlc-.
1/2-. and 1/3-LCO
bla. voltage scheme.
14
kQ
80- 8 31.
VOO > VLCO'
Appll.. to .tatlc-.
112-. and 1/3-LCI)
bla. voltage schem4\'
250
IIA
CLl external clock.
200 KHz
f. -
m
~PD7225
DC Characteristics (Cont.)
AC Characteristics (Cont.)
T.
T• • O'Cto +70·C,VDD. 2.7VtoB.BV
= O'C to + 70'C, VDD •
2.7 to B.BY
UmI••
P.,o",o'or
Input Volt-ae
High
••",bol
MIn
TV"
V1H,
0. 7V OO
VOO
V
Exc.pt SCK
0.8 VOO
VOO
0.3
VOO
0.2
VOO
V
eR
V
ExceptSeK
VIl2
Input leokogo
Curront High
IllH
Input lookage
Current low
ILll
Outp\ll Voh-ae
High
VOH
Output Voh-ae
low
VOl
Output leok-ao
Current low
IlOl
lOS
Backplone Driver
Output Impedlnce
RCOM
Supply Current
VOO -0.75
l
VOl2
IlOH
Output Short
Circuit Curront
Segment Driver
Output Impedlnce
-2
30
100
SCK
1'VP
tlSK
"I
tlHK
"I
8th fit to
iiii§'n DeilY
Time
tKOB
"I
ClOAO • 50 pF
tCOB
,,0
ClOAO • 50 pF
"A
VOH - Voo
"A
VOL - OV
-200
"A
SYNC, VOS - 0.5V
kl2
COMO-COM3'
VOO > VlCO'
AppUoo to "otlc-,
112-, ond "3-lCO
blao voltoge ochem..
kl2
"A
Unit
SO-S31,
VOO> VlCO'
AppU.. to Itotlc-,
112·, Ind tl3-lCO
bill voltago ochom..
Cl, externll clock,
VOO - 3.0V ± 10%,
f+ = 140 KHz
KHz
R • 180 kQ + 5%
"I
,,0
Cl" extornal clock
JeRCycie
tCYI!:
900
tKWH
400
nl
tKwl
400
nl
tBHK
51 Setup Tlmo to
ICRt
tl8K
100
n.
200
nl
tKOB
tCOB
DeilY Time
~:-~Jlme
tOSK
cif5 Hold Tlmo
tOHK
1.5
"I
"I
,,0
i::!Pul.. Wldth
High
tCWH
81f+
i::!Pul .. Width
low
tCWl
81f+
",
After 8th JeRt
tKWl
1.8
a~to BUSY~
Delay Time
~~t~~Jlme
tOSK
CIO Hold Time
After 8th IeKt
tOHK
CS Hold Time
Aftor 8th 'lCR't
tCHK
CS Pul.. Width
High
tCWH
81f+
C§ Pul .. Width
low
tCWl
81f+
SYNC load
Clpocltonce
ClOAO
T.
tCHK
"I
18
"I
,,0
,,0
"I
"I
50
pF
f• • 200 KHz
=25°C
Uml ••
Poro"'o'or
Cl" oxtornol clock
•• mbol
MIn
To ••
Condltlono
T"" Ma. Unit
10
pF
Input Clplcltonco
CI
Output Capacitance
COJ
CO 2
20
15
pF
pF
11m'
Input/Output
Capacitance
CIO
15
pF
"1VJm
Clock Copocltonco
C+
30
pF
no
"I
"I
,,0
Aftor 8th SCKt
~HoldTlmo
1.8
nl
!1JIVt to JeR~
Hold Tlmo
CS~ to BuSY~
tKWH
Capacitance
KHz
175
t+Wl
tCYIS
Too•
Condltlono
200
Clock Pul.. Width
low
tlHK
Cl" external clock
51 Hold Time
After'iCKt
400 "A
-2
2
81 Hold Tlmo
After8CKt
"I
"I
,,0
no
t+WH
8thseKt to
BuS'i~ DeilY Time
18
!!.§.etup Time to
SCKt
IVRC, 10l -
Clock PUIH Width
High
low
".
t+Wl
tBHK
50
I'CR PUIH Width
t+WH
BUSYt to SCK~
Hold Time
85
mpul.. Wldih
High
R. l80kl2 + 11%,
VOO • 3.0V ± 10%
Cl" externol clock
RK PUIH Width
low
V
18
KHz
100
lCK Pullo Width
0.5
18
140
To••
Condition.
BUSY, SYNC,
10H - -7"A
f+
130
KHz
V
fOSC
Clock Frequoncy
Unit
140
18
'ICK Cycle
Hlllh
iU§Y, 10l - l00,.A
Mo.
50
Mo.
Vil - OV
Um".
MIn
••",bol
fOSC
T."
"A
= -10'C to +70'C; YDD = + B.OY :t 100/0
Per_tor
. Clock Pul.. Width
low
f+
50
VIH - VOO
AC Characteristics
T.
Clock Pul.. Width
High
MIn
..",bol
"A
V
100
Poro",oter
Clock Frequency
0.5
12
RSEG
V
LIIIIIt.
To ••
Condition.
Unit
VIH2
Vll,
Input Voh-ae
low
Mo.
ClOAO .. 50 pF
ClOAO • 50 pF
540
Excopt 1ftmV·
Cl,lnput
~n:'o~~u:d
plnl return
toOV.
.JlPD7225
AC Timing Ch.r.cte"atlca
-_-_-:: :: : : _ :. _\ \...vI.:.'
\ --.- --- --- -- --- --- ---- -.- - ----- --/~
.
...:.....-_._---
Alltnput.
- - - -- - - - - - - - - -/------~ --~ :: : :: :.\~:
'--._-\ .-------------.
All OUtput.
Timing W.v.forma
Clock
--=L_
CL1---~r-----_-t+WL-I'"+---;---~,..---=-t-+WH
~---------------------~m----------~----------I
~--------------------------------T_--r- - - "'\
\
\
\
t----,I'--- - - - .- - - - - - - ' - -
tBHK---
81----------"""""
'-----
1-1-------t
DsK
~6------------~~--------------
541
tD_H_.~~----__-
______
/JPD7225
Characteristics Curves
T.
= 25°C
Supply Voltage v. Osclllition Frequency
External Reslltance vs Oscillation Frequency
~
U
uR
140
R
200
~
£120
f
1
I
V
~
J
100r-----r-------~~~~--------~~--~
c
I
50~--~~--------~--------~~~~,-,-,~
R7V
100
/
I/
'.
80
100
500
200
~
External Re.lstance R (kQ)
Supply Voltaga v. Supply Currant
~
External Clock
100
l
D
.9
~
tg-
= 200 KHz
v/
'E
d
f /
/ /
f=7
50
III
./'
20
~
Supply Voltaga VOO (V)
542
4
Supply Voltage VOO (V)
I-'PD7225
Package Dimensions (Unit: mm)
Use IC Socket IC·53·11 for all packages.
~D7225G-01
2.8 Max
-.Lo
T'
I I
1
0.15
l'
~g:~g rf=r::(o
I
-
-
-I -
-
4 +0.2
-0.1
-
-
-
-
-
-
I
:
~4
I
0 000000000 0
f. . ~:; -Ma~ =
25.6 ± 0 . 4 - - - -
2.8 Max
~D7225G·OO
722S0S-1-82-CAT
543
NOTES
544
fiPD7227
NEe
NEe Electnlnics U.S.A. Inc.
Microcomputer
I~ivision
fiPD7227 INTELLIGENT DOT·MATRIX
LCD CONTROLLER/DRIVER
DESCR IPTION
The ~PD7227 Intelligent Dot-matrix LCD Controller/Driver is a peripheral device
designed to interface most microprocessors with a wide variety of dot matrix LCDs.
It can directly drive any multiplexed LCD organized as 8 rows by 40 columns, and is
easily cascaded up to 16 rows and 280 columns. The ~PD7227 is equipped with
'several hardware logic blocks; such as an 8-bit serial interface, ASCII character
generator, 40 x 16 static RAM with full read/write capability, and an LCD timing
controller; all of which reduce microprocessor system software requirements. The
~PD7227 is manufactured with a single 5V CMOS process, and is available in a
space-saving 64-pin flat plastic package.
FEATU R ES
• Single-chip LCD controller with direct LCD drive
• Compatible with most microprocessors
• Eight row drives
- Designed for dot-matrix, LCD configurations up to 280 dots
- Designed for 5 x 7 dot-matrix character LCD configuration; up to 8 characters
- Cascadable to 16 row drives
• 40 column drives
- Cascadable to 280 column drives
• Hardware logic blocks reduce system software requirements
- 8-bit serial interface for communication
- ASCII 5 x 7 dot-matrix character generator with 64-character vocabulary
40 x 16 bit static RAM for data storage, retrieval, and complete back-up
memory capability
Voltage controller generates LCD bias voltages
Timing controller synchronizes column drives with sequentially-multiplexed
row drives
• Single +5V power supply
• CMOS technology
PIN CONFIGURATION
~
M
~
N
0
~ ~ ~ ~ ~ ~ ~ ~ § §§ §~
V)
u u u u u a: a:: cr. a: c:: a: a: a: > > > > l; lu
C5
sCi<
C6
sO/BTiSY
C7
C/D
CB
SI
Cg
RESET
ClO
VO'D
Cll
0
IiPD7227
C12
C13
C14
C15
0
CLOCK
VOO
VSS
C39
C3B
0
C37
C36
C16
C35
545
IlPD7227
PIN NUMBER
SYMBOL
1
NC
2-24,47 -57,
59-64
CO-C39
PIN DESCRIPTION
FUNCTION
No connection.
LCD Column Driver Outputs.
25
VSS
Ground
26,58
VDD
Power supply positive. Apply single voltage
ranging from 2.7V to 5.5V for proper
operation.
27
CLOCK
System Clock input (active high) connect to
external clock source.
28
RESET
Reset input (active high), R/C circuit or
pulse initializes pPD7227 after power-up.
29
SI
Serial input (active high), Data input from
microprocessor.
30
C/O
Command/Data Select input (active both
high and low). Distinguishes serially input
data byte as a command or as display data.
31
SO/BUSY
Serial Output (active high)/Busy output
(active low)' Data output from pPD7227
to microprocessor when in READ MODE
and C/D is low. Handshake output indicates
that pPD7227 is ready to receive/send next
data byte.
32
SCK
Serial Clock input (active lowl'. Synchronizes
8-bit serial data transfer between microprocessor and pPD7227.
33
CS
Chip Select Input (active low) enables
pPD7227 for communication with microprocessor.
34
SYNC
Synchronization port (active high). For
multichip operation tie all SYNC lines
together, and configure with MODE SET
command.
35-38
VLCD1' VLCD2'
VLCD3' VLCD4
LCD Bias Voltage supply inputs to LCD
Voltage Controller. Apply appropriate voltages from a voltage ladder connected across
VDD.
RO/8- R7115
39-46
LCD Row Driver Outputs.
BLOCK DIAGRAM
SYNC
VDD
VLCDl
VLCD2
vLCD3
VLCD4
vss
CLOCK
cs
C/O
546
50/BDSY 5CK
51
"PD7227 _
COMMAND SUMMARY
I nstruction Code
Binary
Description
07
06
Os
04
Initialize the ~PD7227.
including selection of
1. LCD Drive
0
0
0
1
1
Command
1, MODE SET
HEX
03 02
01
DO
02
01
DO
1S-1F
Configur~tion
1,",
2; RoiN Driver Port
Function
3. RAM Bank
4. SYNC Port Function
2. FRAME FREOUENCY SET
Set LCD Fr~me
Frequency
0
0
0
1
0
02
01
DO
10-17
3. LOAD DATA
POINTER
Load Data Pointer with
7 bits of Immediate
Data
1
06
Os
04
03
02
01
DO
SO-E7
4. WRITE MODE
Write Display Byte in
Serial Register to RAM
location addressild by
Data Pointer; modify
Data Pointer
0
1
1
0
0
1
01
DO
64-67
5. READ MODE
Load RAM contents
addressed by Data
Pointer into Serial
Register for output;
modify Data Pointer
0
1
1
0
0
0
01
DO
60-63
6.AND MODE
Perform a Logical AN 0
between the display
byte in the Serial
Register and the RAM
contents addressed by
D-ata Pointer; write
result to same RAM
location; modify Data
Pointer
0
1
1
0
1
1
01
DO
6C-6F
7.0R MODE
Perform a Logical OR
between the display
byte In the Serial
Register and the RAM
contents addressed by
Data Pointer; write
Result to same RAM
location; modify Data
Pointer
0
1
1
0
1
0
01
DO
68-6B
S. CHARACTER
MODE
Decode display byte In
Serial Register into
5 x 7 character with
Character Generator;
write character to RAM
location addressed by
Date Pointer; increment
Data Pointer by 5
0
1
1
1
0
0
1
0
72
9.SET BIT
Set sh;gle bit of RAM
location addressed by
Dete Pointer; modify
Deta Pointer
-0
1
0
04
03
02
01
DO
40-SF
,
10. RESET BIT
Reset single bit of RAM
location eddre~!ed by _;
Data Pqinter; modify
)
Deta Pointer
0
0
1
04
03
02
01
DO
20-3F
11. ENABLE
DISPLAY
Turn
0
0
0
0
1
0
0
1
09
12. DISABLE
DISPLAY
Turnoff th!lr- L~CD
0- 0
0
0
1
0
0
0
08
01)
the LCD -
Further details of operation can be found in the "fJPD7227 Intelligent Dot-Matrix
LCD Controller/Driver Technical Manual."
547
"PD7227
Power Supply, Voo .........••......•.•.. '...•..•.•.•. -O.3V to +7.OV
All inputs and outputs with respect to VSS ....•.......... -O~3V to VOO +0.3
Storage Temperature ....••.••....•.....••.......... -40°C to +125°C
o
Operating Temperature ............•......•.•.....•..• -10°C to +70 C
ABSOLUTE MAXIMUM
RATINGS*
·COMMENT: Exposing the device to stre.... above those lI.ted In Absolute Maximum Rating.
could causa permenent damage. The device I. not meant to be operated under condition. outside
the limit. described In the operational section. of thl. specification. ExpolUre to absolute maximum rating condition. for extended period. may affact device reliability.
Ta
= _10°C to +70°C, Voo = + 5.0V
± 10%
DC CHARACTERISTICS
LIMITS
PARAMETER
SVMBOL
MIN
Input Voltage
High
VIH
Input Voltage
Low
VIL
Input Leakage
Current High
Input Leakage
Current Low
TVP
MAX
UNIT
0.7 VOO
VOO
V
0
0.3 VOC
V
ILIH
+10
jJA
VIH
=
VOO
ILIL
-10
jJA
VIH
=
OV
CONDITIONS
SO/ii'liSV, 10H • -400 jJA
Output Voltage
High
VOH,
VOH2
SYNC, 10H • -l00"A
Output Voltage
Low
VOL,
SO/BU'§?, 10L = +1.7mA
V
VOO-0.5
0.45
V
SYNC. 10L = +100 jJA
VOL2
Output Leakage
Current High
ILOH
+10
jJA
VOH = VOO
Output Leakage
Current Low
ILOL
-10
jJA
VOL = OV
LCD Operating
Voltage
VLCO
3.0
8-Row Multiplexed LCD
Drive Configuration
VOO
V
16-Row Multiplexed LCD
Drive Configuration
VOO
Row Drive
Output
Impedance
RROW
4
8
kO
Column Drive
Output
Impedance
RCOLUMN
10
15
kO
Supply Current
100
200
400
jJA
f = 400 KHz
T a - -25°C, VOO - OV
CAPACIT ANCE
LIMITS
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
CI
10
pF
Output Capacitance
Co
25
Input/Output Capacitance
CIO
15
Input Capacitanca
CONDITIONS
11/»- 1 MHz
pF
Unmeasured pins
pF SYNC returned to Ground.
548
IiPD7227
AC CHARACTER.lSTICS
'fa • ...10°C to
+'7ffc, VOO· +s.ov ±.10%
LIMITS
SYMBOL
MIN
f
....
...-
00- 0 7
SO,
SORa
'§(5!f1
RD'
WR
Cs
"P07720
OMA
INTERFACE
i5ACi<
{
INT
RESET
CLOCK
RST
ClK
SI
mN
ORO
INTERRUPT
SERIAL I/O
INTERFACE
SCK
Ao
Po
OUTPUT PORT
}
P,
Serial I/O
Two shift registers (SI, SO) that are software-configurable to 8 or 16 bitsland are
externally clocked (SCK) provide simple interface between the SPI and serial peripherals such as, A/Oand O/A converters, codecs, or other SPls.
SERIAL I/O TIMING
SCK
4>S
SORa
Sl5m
\~-----------------..------------------~'-------------
OUTPUT
DATA
SOACK
HIGHZ
lBORS
.J
~
SIREG
LOAS~ :~~E
o.;.14_0~R.:.;8:..A..;.;;..;;~,'_____'_ _
~~
____________________________________-JI
---------------------------------------------------~~~------r----L.
Dltl clocked out on failing edge of SCK.
Dati clocked In on riling edge of SCK.
@ Brok.n llna denot.1 conlacinlv. IIndlng of naxt data.
PARALLE L I/O
The 8-bit parallel I/O port may be used for transferring data or reading the SPI's
status. Data transfer is handled through a 16-bit Data Register (DR) that is softwareconfigurable for double or single byte data transfers. The port is ideally suited for
operating with 8080, 8085 and 8086 processor buses and may be used with other
processors and computer systems.
555
",porno
PARALLEL RIW OPERATION
cs
AO
WR
1
X
X
X
X
1
~}
0
0
0
1
0
0
1
0
DR to IDB ROM not set. IN DMA DRO not set.
(2) First bit in goes to MSB, last bit to LSB.
@ First bit in goes to LSB, last bit to MSB (bit reversed).
Table 7 - List of Registers Specified by the Source Field (SRC)
559
"PD7720
Table 8. OP, RT, LDI
DST Field
Mnemonic
Specified Register
03 02 01 DO
@NON
0
0
0
@A
0
0
0
1
ACC A (Accumulator A)
@B
0
0
1
0
ACC B (Accumulator B)
@TR
0
a
1
1
TR Temporary Register
@DP
a
1
a
a
DP Data Pointer
@RP
a
1
a
1
RP ROM Pointer
@DR
a
1
1
a
DR
@SR
a
1
1
1
SR Status Register
' NO Register
0
Data Register
@SOL
1
a
a
a
SO Serial Out LSB
CD
@SOM
1
a
a
1
SO Serial Out MSB
(2)
@K
1
a
1
a
K (Mult)
@KLR
1
a
1
1
lOB -+ K ROM -+ L
@KLM
1
1
a
a
Hi RAM -+ K I DB -+ L
@L
1
1
a
1
L (Mult)
@NON
1
1
1
a
NO
@MEM
1
1
1
1
RAM
Notes:
CD
@
®
Register
LSB is first bit out.
@ MSB is first bit out.
@ Internal data bus to K and ROM to L register.
@ Contents of RAM address specified by DPe = 1
(i.e., 1, DP5, DP4, DPa) is placed in K register. IDB
is placed in L.
Table 8 - List of Registers Specified by the Destination Field (DST)
B)
Jump/Call/Branch
22
10
21
20
19
18
17
16
15
14
13
12
11
10 9
7
NA
CND
BRCH
8
6
5
4
3
2
1 0
[//1
JP Instruction Field Specifications
Three types of execution address modification instructions are accommodated by the
processor and are listed in Table 9. All of the instructions, if unconditional or the
specified condition is true, take their next program execution address from the Next
Address field (NA), otherwise PC = PC + 1.
Table 9. Branch Field Selections (BRCH)
20 19 18
Instruction
1
0
0
Uncondition jump
1
a
1
Subroutine call
a
1
0
Condition jump
For the conditional jump instruction, the condition field specifies the jump condition.
Table 1a lists all the instruction mnemonics of the J/C/B OP codes.
The SPI offers all the execution modification instructions necessary for efficient, data,
I/O and arithmetic control.
560
"POrno
Table 10. Condition Field Specifications
BRCH/CND Fields
Mnemonic
D20 D19 D18 D17 D16 D15 D14 D13
Conditions
No Condition
JMP
1
0
0
0
0
0
0
0
CALL
1
0
1
0
0
0
0
0
No Condition
JNCA
0
1
0
0
0
0
0
0
CA=O
JCA
0
1
0
0
0
0
0
1
CA= 1
JNCB
0
1
0
0
0
0
1
0
CB = 0
JCB
0
1
0
0
0
0
1
1
CB = 1
JNZA
0
1
0
0
0
1
0
0
ZA=O
JZA
0
1
0
0
0
1
0
1
ZA= 1
JNZB
0
1
0
0
0
1
1
0
ZB = 0
0
1
0
0
0
1
1
1
ZB = 1
JZB
JNOVAO
0
1
0
0
1
0
0
0
OVAO= 0
JOVAO
0
1
0
0
1
0
0
1
OVAO= 1
JNOVBO
0
1
0
0
1
0
1
0
OVBO= 0
JOVBO
0
1
0
0
1
0
1
1
OVBO= 1
JNOVAl
0
1
0
0
1
1
0
0
OVAl =0
OVA1=1
JOVAl
0
1
0
0
1
1
0
1
JNOVBl
0
1
0
0
1
1
1
0
OVBl
JOVBl
0
1
0
0
1
1
1
1
OVB1=1
JNSAO
0
1
0
1
0
0
0
0
SAO = 0
JSAO
0
1
0
1
0
0,
0
1
SAO = 1
JNSBO
0
1
0
1
0
0
1
0
SBO= 0
JSBO
0
1
0
1
0
0
1
1
SBO = 1
JNSAl
0
1
0
1
0
1
0
0
SAl = 0
JSAl
0
1
0
1
0
1
0
1
SAl = 1
JNSBl
0
1
0
1
0
1
1
0
SBl = 0
JSBl
0
1
0
1
0
1
1
1
SBl = 1
JDPLO
0
1
0
1
1
0
0
0
DPL
JDPLF
0
1
0
1
1
0
0
1
DPL = F (HEX)
JNSIAK
0
1
0
1
1
0
1
0
SI ACK
JSIAK
0
1
0
1
1
'0
1
1
SI ACK = 1
=0
=0
=0
JNSOAK
0
1
0
1
1
1
0
0
SO ACK = 0
JSOAK
0
1
0
1
1
1
0
1
SO ACK = 1
JNROM
0
1
0
1
1
1
1
0
ROM=O
JROM
0
1
0
1
1
1
1
1
ROM = 1
*BRCH or CND values not in this table are prohibited.
561
flPD7720
C)
Load Data (LOU
22
21
20
19
18
17
16
15
14
11
13
12
11
10
9
8
7
6
5
4
3
VI
10
2
1
0
DST
The Load Data instruction will take the l6·bit value contained in the Immediate Data
field (10) and place it in the location spl~cified by the Destination field (DST) (see
Table 8).
Voltage (Vee Pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to +7.0 Volts l
-0.5
ClK High Voltage
VrJ>H
3.5
Output Low Voltage
VOL
Output High Voltage
VOH
Input load Current
ILIL
-10
IJ.A
VIN
Input Load Current
ILiH
10
IJ.A
VIN
Output Float Leakage
ILOl
-10
IJ.A
VOUT
Output Float Leakage
ILOH
Power Supply Current
ICC
PARAMETER
CLK, SCK Input
Capacitance
SYMBOL
CrJ>
0.8
V
0.45
V
VCC +0.5
V
0.45
2.4
MIN
V
VCC +0.5
V
IOL = 2.0 mA
V
IOH = -400 IJ.A
10
IJ.A
180
280
mA
TVP
MAX
UNIT
20
pF
Input Pin Capacitance
CIN
10
pF
Output Pin Capacitance
COUT
20
pF
562
= OV·
= VCC
= 0.47V
VOUT = VCC
CONDITION
fc = 1 MHz
CAPACITANCE
".porno
AC CHARACTERISTICS
Ta
=-10"'" +70°C, VCC '" +5V ± 5%
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
CONDITION
ns
CD
ClK Cycle Time
t/>CY
ClK Pulse Width
t/>D
ClK Rise Time
t/>R
10
ns
ClK Fell Time
t/>F
10
ns
Address Setup Time for
Fil5
122
2000
60
ns
tAR
0
ns
Address Hold Time for R 0
tRA
0
ns
R 0 Pulse Width
tRR
250
Data Delay from Ff[5
tRD
Read to Date Floating
tDF
10
Address Setup Time for WR
tAW
0
ns
Address Hold Time for \iVA
tWA
0
ns
\iVA Pulse Width
tww
250
ns
Data Setup Time for WR
tow
150
ns
Data Hold Time for WA
two
0
ns
RD, WR, Recovery Time
tRV
250
ORO Delay
tAM
DACK Delay Time
tDACK
SCK Cycle Time
tSCY
480
230
CD
CD
ns
150
ns
Cl~100pF
100
ns
Cl = 100 pF
ns
150
t/>D
1
DC
@
ns
@
ns
SCK Pulse Width
tSCK
SCK Rise/Fall Time
tRSC
ns
SORO Delay
tDRO
30
SOEN Setup Time
tsoc
50
ns
SOEN Hold Time
tcso
30
ns
SO Delay from SCK '" lOW
tDCK
150
ns
SO Delay from SCK withSOROt
tDZRO
20
300
ns
SO Delay from SCK
tDZSC
20
300
ns
20
ns
CD
150
ns
Cl'" 100 pF
@
@
SO Delay from SOEN
tOZE
20
180
ns
®
SOEN to SO Floating
tHZE
20
200
ns
SCK to SO Floating
tHZSC
20
300
ns
50 Delay from 5CK wlth SORO.j.
tHZRO
70
300
ns
@
@
@
SIEN, SI Setup Time,
toc
55
ns
@
SIEN,51 Hold Time'
tCD
30
ns
PO, P1 Delay
top
RST Pulse Width
tRST
4
t/>CY
INT Pulse Width
tiNT
8
t/>CY
Notes:
CD
@
t/>CY
+150
Voltage at measuring point of timing 1.0V and 3.0V
Voltage at measuring point of AC Timing
Vil = Val = 0.8V
VIH = VOH = 2.0V
Input Waveform of AC Test (except ClK, SCK)
2.4
2.0
2.0
0.45
0.8
0.8
563
ns
",porno
'CLOCK
TIMING WAVEFORMS
CLK
READ OPERATION
AO. CS. i5ACK
- - . . . , . - . t R R - - -...
Ri5-----
WRITE OPERATION
DMA OPERATION
DACK
,oj
DRO
564
I'PD7720
TIMING WAVEFORMS
(CON'T.)
SERIAL TIMING
SCK
SORa
tOZE
rtHzt =--rtHZRQ
.,
-~-----
SO
SI
Notes:
G)
For SO timing, the data at rising edge of SCK is valid and the other data is invalid. In set-up
hold time of data for SCK, the most strict specifications are the following.
set-up
=tSCK -
tDCK
hold = tHZRQ
®
Voltage at measuring point of trsc and tfsc for SCK timing
G)
3.0V
®
1.0V
565
IlPon20
PRODUCT EXAMPLE
USING THE "PD7720
.
~
MICROPHONE
THERMAL
PRESSURE
LIGHT
...... ...
•••• : e.
•••••
FREa_
BANDLIMITING
FILTER
SPECTRUM ANALYSIS SYSTEM
AN ANALOG TO
ANALOG DIGITAL
PROCESSING SYSTEM
USING A SINGLE SPI
ANALOG
IN
Lr:-'
ANALOG
OUT
F
I----... SI
SPI
t--...--.-ImJi[
SPI
SO t - - - . - I SI
"SUm
SORa t - - -....
~
A SIGNAL PROCESSING SYSTEM USING
CASCADED SPII & SERIAL COMMUNICATION,
HOST
CPU
MEMORY
B
A SIGNAL PROCESSING
SYSTEM USING SPill)
AS A COMPLEX COMPUTER
PERIPHERAL
ORa 1
DMA
~~D~A~C~K~1~~ CONTROLLER
566
ANALOG
OUT
IlPD7720
PACKAGE DIMENSIONS
t-1-------36.2MAX.------'1
I ~8
15
,....&-.U-L..L-..L..L.L.oL.&......L..&...L-&.~I'
o
~'T'T'"T'T""'TT"-rr-rT'TT"T'TT'J
14
0-10"
.......- - - - - 33.02
-------<"'"'
7720DS-R EV2/1-82-CAT
567
NOTES
568
NEe
IlPD8155
IlPD8155-2
IlPD8156
IlPD8156-2
NEe Electronics U.S.A. Inc.
Microcomputer Division
2048 BIT STATIC MOS RAM WITH
1/0 PORTS AND TIMER
OESCR IPTION
FEATURES
PIN CONFIGURATION
The J.,tPD8155 and J.,tPD8156 are J.,tPD8085A family components having 256 X 8 Static
~AM, 3 programmable I/O ports and a programmable timer. They directly interface
to the multiplexed J.,tPD8085A bus with no external logic. The J.,tPD8156 has an active
low chip enable while the J.,tPD8156 is aCtive high.
• 256 X 8·Bit Static RAM
•
Two Programmable 8·Bit I/O Ports
•
One Programmable 6·Bit I/O Port
•
Single Power Supplies: +5 Volt, ±10%i
•
Directly interfaces to the J.,tPD8086A and J.,tP08085A·2
•
Available in 40 Pin Plastic Packages
vcc
PC3
PC4
TIMER IN
RESET
PC5
i'i1lER 0U"f
101M
CE/~·
RD
WR
ALE
ADO
AD1
AD2
AD3
AD4
ADs
ADs
AD7
J.,tPD
8155/
8156
Vss
·",PD81SS: ~
",PD8156: CE
Rev/3
569
PC2
PC1
PCo
PB7
PBS
PB5
PB4
PB3
PB2
PB1
PBo
PA7
PAS
PAS
PA4
PA3
PA2
PA1
PAo
m
"PD8155/8156
The J..lPD8155 and J..lPD8156 contain 2048 bits of Static RAM organized as 256 X 8.
The 256 word memory location may be selected anywhere within the 64K memory
space by using combinations of the upper 8 bits of address from the J..lPD8085A as a
chip select.
FUNCTIONAL
DESCRIPTION
The two general purpose 8·bit ports (PA and PB) may be programmed for input or
output either in interrupt or status mode. The single 6-bit port (PC) may be used as
control for PA and PB or general purpose input or output port. The J..lPD8155 and
pPD8156 are programmed for their system personalities by writing into their
Command/Status Registers (C/S) upon system initialization.
The timer is a single 14-bit down counter which is programmable for 4 modes of operation; see Timer Section.
Vce (+5V)
BLOCK
DIAGRAM
I
-.
8
,....-
~
L
A
T
C
CE
f-r-
p
A
R
A
M
r--
---
---C
I-----
L
l
8
--- --p
C
-
J
1.
B
-
:-
0
TIMER IN
p
I.....-
0
N
T
R
RESET
8
---
H
ALE
--
~
TIMER
6
L
I
TIMER OUT
I
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . O°C to +70°C
Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -65°C to +150°C
Voltage on Any Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to +7 Volts--
Plastic
ITEM
A
B
C
0
E
F
G
H
I
J
K
L
M
MILLIMETERS
51.5MAX
1.62
2.54 ± 0.1
0.5tO.l
48.26
1.2MIN
2.54 MIN
0.5 MIN
5.22 MAX
5.72 MAX
15.24
13.2
+0.1
0.25 _ 0.05
576
INCHES
2.028 MAX
0.064
0.10t 0.004
0.019 ± 0.004
1.9
0.047 MIN
0.10MIN
0.019 MIN
0.206 MAX
0.225 MAX
0.&00
0.520
+ 0.004
0.010 _ 0.002
8166/66DS·REV 3·12-81·CAT
NEe
",PB8212
NEe Electronics U.S.A. Inc.
Microcomputer Division
EIGHT-BIT INPUT IOUTPUT PORT
DESCR I PTI ON
The t1PB8212 input/output port consists of an 8-bit latch with three-state output
buffers along with control and device selection logic. Also included is a service request
flip-flop for the control and generation of interrupts to the microprocessor.
The device is multimode in nature and can be used to implement latches, gated buffers
or multiplexers. Thus, all of the principa1peripheral and input/output functions of a
microcomputer system can be implemented with this device.
FEATU RES
• Fully Parallel 8·Bit Data Register and Buffer
•
PIN CONFIGURATION
Service Request Flip-Flop for Interrupt Generat[on
•
Low Input Load Current - 0.25 mA Max
•
Three State Outputs
•
Outputs Sink 15 mA
•
3.65V Output High Voltage for Direct Interface to 8080A Processor
•
Asynchronous Register Clear
•
Replaces Buffers, Latches and Multiplexers in Microcomputer Systems
•
Reduces System Package Count
•
Available in 24-pin Plastic and Cerdip Packages
55 1
VCC
MO
INT
01 1
01 8
PIN NAMES
0°1
008
01 1 -. 01 8
Data In
01 2
01 7
001 - 008
Data Out
0°2
0°7
OS1,OS2
Device Select
01 3
01 6
MO
Mode
003
006
STB
Strobe
01 4
01 5
INT
Interrupt (Active Low)
0°4
005
CLR
Clear (Active Low)
STB
CLR
GNO
OS2
Rev/2
577
,..PB8212
BLOCK DIAGRAM
!is,
INT
011
j)-----------I-+-I
01 2
0e-------------''-L-+-I
01 3
0)>-----------+--+-I
01 4
0~---------~+I
DiS
@f------------+-+I
DiS
@I---------------'-+-I
01 7
@)I-------------++I
DiS
@I--_________---L.-J.-j
m
@1----I-AC-T-IV-E-LO-W-I---a:::OO+-----4I----..J
ISTB MO (~1- OS2)
0
I
0
0
0
0
0
0
Three-State
Three-State
Data Latch
Data Latch
I
Data
Data
Data
Data
0
I
I
I
0
I
0
0
I
0
I
I
I
I
I
Notes:
DATA OUT
eQUALS
Internal SA flip-flop
~ Previous data remains
Operating Temperature ....... .
Storage Temperature . . . . . . . . . .
All Output or Supply Voltages ... .
All Input Voltages . . . . . . . . . . . . . .
Output Currents.
........
0°Cto+70°C
..... -65°Cto+150°C
. ..... -0.5 to +7 Volts
. -1.0 to +5.5 Volts
. . . . . . . . . . . . . . . . . . . . ".... 125mA
*COMMENT: Stress above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification Is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
578
ABSOLUTE MAXIMUM
RATINGS*
"PB8212
DC CHARACTE RISTICS
Ta - 0°Cto70°C; VCC-+5V ± 5%
SYMBOL
PARAMETER
:
Input Load Current STB, OS2,
LIMITS
MIN
MAX
UNIT TEST CONDITIONS
IILl
-0.25
mA
VF =,0.45V
Input Load Current MD Input
IIL2
-0.75
mA
VF
Input Load Current 'Oil, Input
Input Leakage Current STB
IIL3
IIHI
-1.0
mA
VF = 0.45V
10
/1A
VR = 5.25V
CLR, 01, - 018 Inputs
=0.45V
OS, CLR, 01, - OIB Inputs
IIH2
30
/1A
VR
i5S,
IIH3
40
/1A
VR·5.25V
Vc
.-1.0
0.85
V
Ic=-5mA
V
0.4B
V
V
IOL·,5mA
-75
V
mA
IOH--1mA
VO·OV VCC = 5V
10.
20
/1A
Vo
ICC
130
mA
Input Leakage Current
Input
Input Forward Voltage Clamp
Input "Low" Voltage
Input ','High" Voltage
VIL
VIH
Output "Low" Voltage
VOL
Output "High" Voltage
VOH
105
Short Circuit Output Current
Output Leakage Current High
Impedance State' 000 - DOB
Power Supply Current
CAPACITANCE
CD
=5.25V
Input Leakage Current MD
Input
2.0
3.65
-15
=0.45V/5.25V
Ta = 2SoC; VCC = +5v'; VSIAS =2.5V; f = 1 MHz
LIMITS
PARAMETER
SYMBOL
Input Gapacitance
Input Capacitance
Output Capacitance
CIN
CIN
Note: '
AC CHARACTERISTICS
Ta
CD
MIN MAX
CoUT
o
C; VCC
pF
pF
pF
OS1, MO
OS2, crR, STB, 011 - DiS
001 - DOS
12
9
12
= +5V ± 5%
PARAMETER
SYMBOL
,tpw
Pulse Width
Data To Output Delay
tpd
Write Enable To Output Delay twe
Data Setup Time
tset
Data Hold Time
th
Reset to Output Delay
tr
Set To Output Delay
,ts
Output Enable/Disable Time
te/td
Clear To Output Delay
tc
CD
TEST CONDITIONS
Th is parameter is periodically sampled and not 100% tested'
= o°c to +70
Notes:
UNIT
LIMITS
'UNIT' TEST CONDITIONS
MIN MAX
30
ns
nS
'ns
ns
40
30
45
55
ns
ns
ns
ns
15
20
R1 = 300n/10Kn; R2 = 6000/1 KO
579
30
40
~s
Input Pulse
Amplitude = 2.5V
Input Rise and Fall
Times = 5 ns
Between 1V and 2V
Measurement made
at 1.5V with 15 mA
and 30 pF
CDI Test Load
"PB8212
Data Latch
FUNCTIONAL DESCRIPTION
The 8 flip-flops that compose the data latch are of a "0" type design_ The output (a)
of the flip-flop follows the data input (D) while the clock input (C) is high. Latching
occurs when the clock (C) returns low.
The data latch is cleared by an asynchronous reset input (~).
(Note: Clock (C) Overrides Reset (CLR).)
Output Buffer
The outputs of the data latch (a) are connected to three-state, non-inverting output
buffers. These buffers have a common control line (EN); enabling the buffer to transmit the data from the outputs of the data latch (a) or disabling the buffer, forcing the
output into a high impedance state (three-state).
This high-impedance state allows the designer to connect the iJPB8212 directly to the
microprocessor bi-directional data bus.
Control Logic
The iJPB8212 has four control inputs: iSS 1, OS2, MO and STB. These inputs are
employed to control device selection, data latching. output buffer state and the
service request flip-flop.
OS1, DS2 (Device Selectl
These two inputs are employed for device selection. When r5S1 is low and OS2 is high
(OS1 • OS2) the device is selected. In the selected state the output buffer is enabled and
the service request flip-flop (SR) is asynchronously set.
Service Request Flip-Flop (SR)
The (SR) flip-flop is employed to generate and control interrupts in microcomputer
systems. It is asynchronously set by the
input (active low). When the (SR) flipflop is set it is in the non-interrupting state.
m
The output (a) of the (SR) flip-flop is connected to an inverting input of a "NOR"
gate. The other input of the "NOR" gate is non-inverting and is connected to the
device selection logic n>Sl • OS2). The output of the "NOR" gate (iNT) is active
low (interrupting state) for connection to active low input priority generating circuits.
MD (Mode)
This input is employe~ to control the state of the output buffer and to determine the
source of the clock input (Cl to the data latch.
When MO is in the output mode (high) the output buffers are enabled and the source
of clock (C) to the data latch is from the device selection logic (oSl • OS2).
When MO is in the input mode (low) the output buffer state is determined by the
device selection logic (DS1 • OS2) and the source of clock (C) to the data latch is
the STB (Strobe) input.
STB (Strobe)
STB is employed as the clock (C) to the data latch for the input mode (MO = 0) and
to synchronously reset the service request flip-flop (SR).
Note that the SR flip-flop triggers on the negative edge of STB which overrides CLR.
580
"PB8212
T-1
VC~
TIMING WAVEFORMS
TO
D.U.T
CD
.
I-2
-
30 pF...
B
} B
INTERRUPT
FLlp·F lOP
PRIORITY
COMPARATOR
INTERRUPT
DISABLE
F LlP·F lOP
INTE
7}-----------------------------------~
ClK
6}-----------------------------------------
Operating Temperature . . . . . . . . . . .
Storage Temperature . . . . . . . . . . . . .
All Output and Supply Voltages .... .
All Input Voltages
........ .
Output Currents
.... O°C to +70°C
-65°C to +150°C
. -0.5 to +7 Volts
. ....... -1.0 to +5.5 Volts
. . . . . . . . . . . . . . . . . 100mA
*COMMENT: Stress above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sec.tions of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
584
ABSOLUTE MAXIMUM
RATINGS*
",PB8214
DC CHARACTERISTICS
Ta
= oOe to +7oo e, vee = 5V ± 5%
PARAMETER
SYMBOL
Input Clamp Voltage_ (all inputs)
Input Forward Current: ETLG input
all other inputs
Input Reverse Current: ETLG input
all other inputs
Input lOW Voltage: all inputs
Input HIGH Voltage: all inputs
Power Supply Current
Output LOW Voltage: all outputs
Output HIGH Voltage: ENLG output
Short Circuit Output Current: ENLG output
Output Leakage Current: rm and A'O-A"2
CAPACITANCE @
Ta
LIMITS
MAX
-55
V
mA
mA
Jl.A
IJA
V
V
mA
V
V
mA
100
IJA
~·0.25
80
40
0.8
IR
V,L
V,H
ICC
VOL
VOH
lOS
ICEX
UNIT
-1.0
-0.5
Vc
IF
'F
'IR
2.0
130
.45
2.4
-20
TEST CONDITIONS
IC= 5mA
VF=0.45V
VR-5.25V
VCC=5.0V
VCC=5.0V
CD
IOl~10mA
10H=-lmA
VOS=OV, VCC=5.0V
VCEX=5.25V
25°e
=
PARAMETER
AC CHARACTERISTICS
MIN
SYMBOL
LIMITS
MIN
MAX
UNIT
TEST CONDITIONS
Input Capacitance
CIN
10
pF
VBIAS=2,5V
Output Capacitance
COUT
12
pF
VCC=5V
f=1mHz
Ta
= oOe to +7oo e, Vee = +5V ± 5%
PARAMETER
SYMBOL
ClK Cycle Time
ClK,
tCY
tpw
ECS, iN'f Pulse Width
INTE Setup Time to ClK
tlSS
INTE Hold Time after ClK
LIMITS
MIN
MAX
UNIT
TEST CONDITIONS
80
ns
Input pulse
25
ns
amplitude: 2.5 Volts
16
ns
tlSH
tETCS@
. tETCH@
20
ns
25
'ns
20
ns
times: 5 ns between
tECCS@
tECCH@
80
ns
1 and 2 Volts
0
ns
ECS Setup Time to ClK
tECRS(!J'
110
ns
ECS Hold Time After ClK
tECRH@
ECS Setup Time to ClK
tECSS@
tECSH@
tDCS@
0
75
ns
ETlG Setup Time to elK
ETlG Hold Time After ClK
ECS Setup Time to CD<
ECS Hold Time After ClK
ECS Hold Time After ClK
SGS and 60-62 Setup Time to QI(
SGS and 60-62 Hold Time After t"lK
RO-R7 Setup Time to ClK
Output loading of
70
0
90
ns
ns
ns
ns
RO-R1 Hold Time After ClK
mT Setup Time to ClK
tiCS
ClK to INT Propagation Delay
tCI
RO-R7 Setup Time to INT
RO-R7 Hold Time After INT
tRIS®
10
tRIH®
35
RO-R7 to AO-A2 Propagation Delay
ElR to AO-A2 Propagation Delay
tRA
tELA
ECS to AO-A2 Propagation Delay
tECA
120
ns
ETlG to AO-A2 Propagation Delay
tETA
70
ns
SITS and BO-B2 Setup Time to ECS
tDECS®
15
tDECH®
tREN
15
70
ns
ns
ns
lfo-1f7 to ENlG Propagation Delay
El TG to EN lG Propagation Delay
0
55
25
ns
ns
ns
100
ns
55
ns
25
90
ns
ECS to ENlG Propagation Delay
tETEN
tECRN
ECS to ENlG Propagation Delay
tECSN
55
ns
Notes:
G)
@
®
®
®
15 mA and 30 pF.
ns
ns
0
tDCH@
tRCS@
tRCH@
SITS" and Bo-'B2 Hold Time After "E"CS
Input rise and fall
Speed measurements
taken at the 1.5 Volts
levels.
ns
8O-B2, SGS, elK, RO-R4 grounded, all other inputs and all outputs
open.
This parameter is not 100% tested.
Required for proper operation if INTE is enabled during next clock pulse.
These times are not required for proper operation but for desired
chenge in interrupt flip-flop.
Required for new request or status to be properly loaded,
585
IlPB8214
General
The J,LPB8214 is an lSI device designed to simplify the circuitry required to
implement an interrupt driven microcomputer system. Up to eight interrupting
devices can be connected to a J,LPB8214, which will assign priority to incoming
interrupt requests and accept the highest. It will also compare the priority of the
highest incoming request with the priority of the interrupt being serviced. If the
serviced interrupt has a higher priority, the incoming request will not be accepted.
A system with more than eight interrupting devices can be implemented by interconnecting additional J,LPB8214s. In order to facilitate this expansion, control
signals are provided for cascading the controllers so that there is a priority established among the controllers. In addition, the interrupt and vector information
outputs are open collector.
Priority Encoder and Request latch
The priority encoder portion of the J,LPB8214 accepts up to eight active low
interrupt requests (RO-R7)' The circuit assigns priority to the incoming requests,
with R7 having the highest priority and RO the lowest. If two or more requests.
occur simultaneously, the J,LPB8214 accepts the one having the highest priority.
Once an incoming interrupt request is accepted, it is stored by the request latch and
a three-bit code is output. As shown in the following table, the outputs,
are the complement of the request level (modulo 8) and directly correspond to the
bit pattern required to generate the one byte RESTART (RST) instr.uctions
recognized by an 8080A. Simultaneously with the AO-A2 outputs, a system
interrupt request (I NT) is output by the J,LPB8214. It should be noted that incoming
interrupt requests that are not accepted are not latched and must remain as an
input to the J,LPB8214 in order to be serviced.
(Ao-Ai)
Interrupt Control Circuitry
The J,LPB8214 contains two flip-flops and several gates which determine whether an
accepted interrupt request to the J,LPB8214 will generate a system interrupt to the
8080A. A condition gate drives the D input of the interrupt flip-flop whenever an
interrupt request has been completely accepted. This requires that: the ETlG
(Enable This level Group) and INTE (Interrupt Enable) inputs to the J,LPB8214 are
high; the ElR input is low; the incoming request must be of a higher priority than
the contents of the current status register; and the J,LPB8214 must have been enabled
to accept interrupt.requests by the clearing of the interrupt disable flip-flop.
Once the condition gate drives the D input of the interrupt flip-flop high, a system
interrupt (INT) to the 8080A is generated on the ne~t rising edge of the ClK input
to the J,LPB8214. This ClK input is typically connected to the ¢2 (TTL) output of an
8224 so that 8080A set-up time specifications are met. When INT is generated, it
sets the interrupt disable flip-flop so that no additional system interrupts will be
generated until it is reset. It is reset by driving ECS (Enable Current Status) low,
thereby writing into the current status register.
It should be noted that the open collector INT output from the J,LPB8214 is active
for only one clock period and thus must be externally latched for inputting to the
8080A. Also, because the INT output is open collector, when J,LPB8214's are
cascaded, an INT output from anyone will set all of the interrupt disaIJle flipflops in the array. Each J,LPB8214's interrupt disable flip-flop must then be
cleared indiVidually in order to generate subsequent system interrupts.
586
FUNCTIONAL
DESCRIPTION
IlPB8214
FUNCTIONAL
DESCRIPTION
(CONT.)
RESTART GENERATION TABLE
PRIORITY
REQUEST
LOWEST
"0
1"1
1ff2
1""3
1""4
; Fr5
Fr6
HIGHEST 1f7
'CAUTlON:
07
06
05
04
03
02
0,
DO
RST
1
1
A2
Ai
AO
1
1
1
7
8
6
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
0
1
1
1
1
1
1
0
1
1
1
1
1
1
1
0,
1
1
1
0
1
1
0
0
1
1
1
1
1
1
1
1
.1
0
0
0
1
1
1
..
3
2
1
1
1
,1
O'
0
1
0
RST 0. 'will vector the pr~am counter to location 0 (zero) and
invoke the same routine, as, the "RESET" input to 8080A.
Current Status Register
The cu'rrent status register is designed to prevent an incoming interrupt request from
overriding the servicing of an interrupt with higher priority. Via software, the priority
level of the interrupt being serviced by the microprocessor is written into the current
status register on BO-B2' The bit pattern written should be the complement of the
interrupt level.
The interrupt level cl,lrrently being serviced is written into the current status register
by driving ECS (Enable Current Status) low. The IlPB8214 will only accept interrupts
with a higher priority than the value contained by the current status register. Note
that the programmer is free to use the current status register for other than as above.
Other levels may be written in.t,oit. The comparison may be completely disabled by
driving SGS (Status Group Select) low when ECS is driven low. This will cause the
IlPB8214 to accept incoming interrupts only on the basis of their priority to each
other.
Priority Comparator
The priority comparator circuitry compares the level of the interrupt accepted by the
priority encoder and request latch with the contents of the current status register.
If the incoming request has a priority level higher than that of the current status
register, the INT output is enabled. Note that this comparison can be disabled by
loading the current status register with SGS=O.
Expansion Control Signals
A microcomputer design may often require more than eight different interrupts. The
IlPB8214 is designed so that interrupt system expansion is easily performed via the
use of three signals: ETlG (Enable This level Group); ENlG (Enable Next level
Group); and ElR (Enable level Read). A high input to ETlG indicates that the
IlPB8214 may accept an interrupt. In a typical system, thecNlG output from one
IlPB8214 is connected to the ETlG input of another IlPB8214, etc. The ETlG of
the IlPB8214 with the highest priority is tied high. This configuration sets up
priority among the cascaded jJPB8214 's. The EN lG output will be high for any
device that does not have an interrupt pending, thereby allowing a device with lower
priority to accept interrupts. Thelli input is basically a chip enable and allows
hardware or software to selectively disable/enable individiJaIIlPB8-214's. A low on
the E1:R input enables the device.
587
9
"PB8214
Ro·Rj
r------------------)
-------, .
X--------
, '- ____ -.I ,.._ _ _ __
TIMING WAVEFORMS
IRCS
ETLG
INTE
ENLG
'REN
-----------------X ___________________ _
'ECSN
vee
OUT.
t~::::
TeST CIRCUIT
TYPICAL IJPB8214
CIRCUITRY
8080A DATA BUS
6
ClK
02 (TTL )
- tfk ~TE
INI~R,R2,--- f;it;i--I-...,
_--0 DB,
01,
DB,
00,
01 (r---i--f.:»----il--...,
2
"'--0 OB 2
01
2
0°2
01
OB
RESULT
0
01 "DB
1
0
0
3
Cs
C!
0
r-;- -1
3
0°3
OlEN 0 - -.....- - _........
D.IEN
~---r~----QCs
OlEN
592
DB -+00
1
JHiQh Impedance
IiPB8216/8226
AtlSOLUTE MAXIMUM
RATINGS*
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . O°C to 70°C
. . . . . • . . . . . . . . . . . . . . . . . . . -65°C to +150°C
Storage Temperature
All Output and Supply Voltages . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to +7 Volts
All Input Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0 to +5.5 Volts
Output Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . 125 mA
*COMMENT: Stress above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability .
DC CHARACTE R ISTICS
U
Ta = OU c to +70 C VCC = +5V'5%
SYMBOL
PARAMETER
LIMITS
MIN
TYP
CD
MAX
TEST. CONDITIONS
UNIT
Input Load Current
mrn.~
IF 1
-0.5
mA
VF
= 0.45
Input Load Current All
Other Inputs
IF2
-0.25"
mA
VF
= 0.45
Input Leakage Current
IRI
20
iJ. A
VR
= 5.25V
Input Leakage Current
01 Inputs
IR2
10
iJ.A
VR
= 5.25V
Input Forward Voltage
Clamp
Vc
-1.0
V
IC
Input "Low" Voltage
VIL
Input "High" Voltage
VIH
Output Leakage Current DO
(3·State)
DB
10
10
20
100
iJ. A
ICC
ICC
130
120
mA
mA
Dmii. CS
Power Supply Current
8216
8226
V
V
VOLl
Output "Low" Voltage
0.48
Vo
= 0.45/5.25V
DO Outputs 10L = 15 mA
DB Outputs 10l = 25 mA
V
8216
VOL2
0.7
V
DB Outputs 10L = 55 mA
8226
0.7
V
DB Outputs 10H - 50 mA
Output "High" Voltage
VOL2
VOHI
3.65
V
DO Outputs 10H
Output "High" Voltage
VOH2
2.4
V
DB Outputs 10H - -10 mA
Output "Low" Voltage
Output Short
Current
Note:
CAPACITANCE
0.95
2.0
= -5mA
CD
Cir~uit
-15
-30
lo!':
lOS
-65
-120
mA
mA
= -1
mA
DO Outputs Vo = OV
DB Outputs VCC - 5.0V
u
Typical values are lor T a = 25 C. V CC = 5.0V.
CD
LIMITS
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
TEST
CONDITIONS
Input Capacitance
CIN
pF
VBrAS = 2.5V
Output Capacitance
COUTl
1O
DO Output.
@ DB Output.
593
8
100% tested.
IlPB8216/8226
Ta; O°C to +70°C; VCC; +5V±5%
PARAMETER
AC CHARACTERISTICS
SYMBOL
Input to Output Delay
DO Outputs
Input to Output Delay
8216
8226
8216
2
XTAL 1
XTAL2
}
}
Processor
Clocks
Crystal
Connections
Used With
TANK
Overtone
Crystal
Oscillator
OSC
<1>2 (TTL)
Rev/2
595
Output
<1>2 CLK
(TTL Level)
VCC
+5V
VDD
GND
+12V
OV
IlPB8224
FUNCTIONAL DESCR IPTION
Clock Generator
The clock generator circuitry consists of a crystal controlled oscillator and a
divide-by-nine counter. The crystal frequency is a function of the SOSOA
processor speed and is basically nine times the processor frequency, i.e.:
Crystal freque~cy = ~
tCY
where tCY is the SOSOA processor clock period.
A series resonant fundamental mode crystal is normally used and is connected
across input pins XTAL 1 and XTAL2. If an overtone mode crystal is used, an
additional LC network, AC coupled to ground, must be connected to the
TANK input of the J,LPB8224 as shown in the following figure.
r-------,
:
I
I
I
I
I
I
I
:J
LC _( 1 \2
I
I
I
-W)
L : FOR OVERTONE CRYSTALS ONLY
D~
r_±_,3.10 PF
I
1I0NL Y NEEDED
L_ -~ABOVE10MHz'
I
' - - - - - - - - ~ 13
14
15
ANK XTAL1
XTAL2
11
The formula for the LC network is:
LC
=(_1)2
2rrF
where F is the desired frequency of oscillation.
The output of the oscillator is input to the divide-by-nine counter. It is also
buffered and brought out on the OSC pin, allowing this stable, crystal controlled
source to be used for derivation of other system timing signals. The divide-bynine counter generates the two non-overlapping processor clocks, ¢1 and ¢2,
which are buffered and at MOS levels, a TTL level ¢2 and internal tim ing signals.
The ¢1 and ¢2 high level outputs are generated in a2-5-2 digi~al pattern,with ¢1
being high for two oscillator periods, ¢2 being high for five oscillator periods, and then
neither being high for two oscillator periods. The TTL level ¢2,¢2 (TTL), is normally used
for OMA activities ·by gating the external device onto the SOSOA bus once a Hold
Acknowledge (H LOA) has been issued.
Additional Logic
I n addition to the clock generator circuitry, the J.LPBS224 contains additional logic
to aid the system designer in the proper timing of several interface signals.
The STSTB signal indicates, at the earliest possible moment, when the status
signals output from the 8080A processor are stable on the data bus. STSTB is
designed to connect directly to the J.LPB8228 System Controller and automatically
resets the J.LPB8228 during power-on Reset.
The RESIN input to the J.LPB8224 is used to automatically generate a RESET
signal to the SOSOA during power initialization. The slow rise of the power
supply voltage in an external RC network is sensed by an internal Schmitt
Trigger. The output of the Schmitt Trigger is gated to generate an S080A com;
patible RESET. An active low manual switch may also be attached to the RC
circuit for manual system reset.
The ROYIN input to the J.LPB8224 accepts an asynchronous "wait request"
and generates a R EAOY output to the aOaOA that is fully synchronized to
meet the 80S0A timing requirements.
596
BLOCK DIAGRAM
",PB8224
---{:>----©
XTAll
XTAl2
osc
TANK
ABSOLUTE MAXIMUM
RATINGS*
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . oove to +7o:e
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 e to +150 C
All Output Voltages (TTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to +7 Volts
All Output Voltages (MOS) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to +13.5 Volts
All Input Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0 to +7 Volts
Supply Voltage Vee . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to +7 Volts
Supply Voltage VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to +13.5 Volts
Output Currents . . . . . . . . . . : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 rnA
'COMMENT: Stress above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of .this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
DC CHARACTERISTICS
T." O·C to +70·C: vCC" +5V .5%; VDD' +12V ,5%
PARAMETER
SYMBOL
LIMITS
MIN
TYP
UNIT
TEST CONDITIONS
MAX
-0.25
rnA
VF "0.45V
Input Leakage Current
IR
10
~A
VR ' 5.25V
Input Forward Clamp Voltage
Ve
-1.0
V
Ie' -5 rnA
Input CUrrent Loading
IF
Input "Low" Voltage
Vil
Input "High" Voltage
VIH
RESIN Input Hysteresis
Output "low" Voltage
VIH-VIL
0.8
Vec' 5.0V
Reset Input
2.6
2.0
All Other Inputs
0.25
Vee' 5.0V
VOL
0.45
1t/l1. (,'.12), Ready. Reset. ~
0.45
All Other Inputs
IOl' 2.5 rnA
IOl'15rnA
Output "High" Voltage
VOH
<1>1.<1>2
9.4
IOH' -100
READY. RESET
3.6
IOH'
All Other Outputs
Output Short Circuit Current
2.4
ISC G)
-10
IOH'-lrnA
-60
rnA
(All low Voltage OutPUts Only)
ICC
115
rnA
Power Supply Current
100
12
rnA
Note:
CD
Caution, 4'1 and 2 Pulse Width
t1 to <1>2 Delay
t01
<1>2 to 2 Delay
t03
2tCY
2 Rise Time
tR
<1>1 and <:>2 Fall Time
tF
<1>2 to 1>2 (TTLl Delay
to2
'"'9"
CL = 20 pF to 50 pF
-14n.
2tCY
'"'9"
9
+20n.
20
20
-5
+15
ns
<1>2 TTL, CL = 30 pF
R1 = 300n
R2 = 600n
92 to STSTB Delay
toss
STSTB Pulse Width
tpw
RDYIN Setup Time
tORS
to STSTB
RDYIN Hold Time
BtCY
tCY
"'9
-9-
ns
-1.5n.
50n5-
STSTB, CL = 15 pF
4tCY
g-
n.
R1 = 2K
A2 = 4K
4tCY
After STSB
tDRH
-9-
READY or RESET
tOR
4tCY
to <:>2 Delay
BtCY
-9- -30 n5
9"
Aeady and Aeset
ns
-25n.
CL=10pF
Rl = 2K
R2 = 4K
Crystal Frequency
!CLK
Maximum Oscillating
'MAX
MHz
l
ICY
27
MHz
Frequency
Note:
CD
tCY repre.ents the processor clock period
-I
VCC
A,
INPUT>-r
J.
Cl
GND
-=-
A2
GND
TEST CIRCUIT
TIMING WAVEFORMS
412!TTLJ
------------------~
SYNC
IFROM PROCESSOR)
ROVIN OR
AE'SiN
-IDA
Voltage Measurement Points: ¢1, ¢2 Logic "0" = 1.0V, Logic "1"
All other signals measured at 1.5V.
598
= 8.0V.
,..PB8224
CRYSTAL REQUIREMENTS
Note:
PACKAGE OUTLINE
~PB8224C
0.005% at 0°C-70°C
Series (Fundamental) CD
20-35 pF
75-20 ohms
. .. 4mW
Tolerance . . . . .
Resonance
Load Capacitance
Equivalent Resistance.
Power Dissipation (Min)
CD With tank circuit use 3rd overtone mode.
,....-----A
(PLASTIC)
ITEM
MILLIMETERS
INCHES
A
19.4 MAX
0.76 MAX.
0.81
0.03
2.S4
0.10
0.5
0.02
17.78
0.70
1.3
2.54
0.051
MI~
0.10 MIN
O.SMIN.
0.02 MIN
-----
4.0S MAX
0.16MAX
4.55 MAX
0.18 MAX
7.62
0.30
0.25
6.4
M
0.25
.-
-0.10
0.01
O.OS
~PB8224D
(CERDIP)
ITEM
MILLIMETERS
INCHES
0.784 MAX
19.9 MAX
1.06
0.042
2.S4
0.10
0.46! 0.10
0.018' 0.004
17.78
0.70
1.5
0.059
2.54 MIN
0.10MIN
0.5MIN
0.019 MIN
4.58 MAX
0.181 MAX
5.08 MAX
0.20 MAX
7.62
0.30
6.8
M
0.25+
0.27
~:~~
0.0098 :
599
~::~:
8224DS-REV 2-12-81-CAT
NOTES
600
NEe
flPB8228
NEe Electronics U.S.A. Inc.
Microcomputer Division
8080A SYSTEM CONTROLLER
AND BUS DRIVER
DESCR IPTION
The ~PB8228 is a single chip controller and bus driver for aOaOA based systems. All
the required interface signals necessary to connect RAM, ROM and I/O components
toa J,lPDaOaOA are generated.
The ~PBa228 provides a bi-directional three-state bus driver for high TTL fan-out and
isolation of'the processor data bus from the system data bus for increased noise
immunity.
The system controller portion of the ~PB8228 consists of a status latch for definition
of processor machine cycles and a gating array to decode this information for direct
interface to system components. The controller can enable gating of a multi-byte
interrupt onto the data bus or can automatically insert a RESTART 7 onto the data
bus without any additional components.
FEA TU RES
• System Controller for 80aOA Systems
•
Bi-Directional Data Bus for Processor Isolation
• 3.60V Output High Voltage for Direct Interface to 80aOA Processor
•• Three State Outputs on System Data Bus
•
Enables Use of Multi-Byte Interrupt Instructions
•
Generates RST 7 Interrupt Instruction
• ~PBa22a for Small Memory Systems
•
Reduces System Package Count
• Schottky Bipolar Technology
PIN CONFIGURATION
,STS'i'B
VCC
'i7OW
HLOA
WR
PIN NAMES
MEMW
OBIN
OB4
04
I/OR
07 - Do
DS7 - DS(
MEMR
IIOR
IIOW
INTA
OB7
07
OB3
'B'O'SEN
MEMR
MEMW
Os
DBIN
INTA
OBS
03
OB2
02
05
BUSEN
OB5
STSTB
01
OB1
DBa
OQ
GNO
NC: No Connection
Rev/2
601
HLDA
WR
VCC
GND
Data Bus (Processor Side 1
Oata Bul (System Sidel
1/0 Read
1/0 Write
Memory Read
Memory Write
DBIN (From ProcllllOrI
I nter",pt Acknowledge
HLDA (From PrOC8l1Or)
WR (From PrOceuor)
Bul Enable Input
Statui Strobe (From "PB8224)
+6V
aVailS
IlPB8228
Bi-Directional Bus Driver
The eight bit, bi-directional bus driver provides buffering between the processor data
bus and the system data bus. On the processor side, the ,uPB8228 exceeds the minimum input voltage requirements (3.0V) of the ,uPD8080A. On the system side, the
driver is capable of adequate drive current (10 mAl for connection of a large number
of memory and I/O devices to the bus. Single flow in the bus driver is controlled by
the gating array and its outputs can be forced into a high impedance state by use of
the BUSEN input.
FUNCTIONAL DESCRIPTION
Status Latch
The Status Latch in the ,uPB8228 stores the status information placed on the data bus
by the 8080A at the beginning of each machine cycle. The information is latched
when STSTB goes low and is then decoded by the gating array for the generation of
control signals.
Gating Array
The Gating Array generates "active low" control signals for'direct interfacing to system
components by gating the contents of the status latch with control signals from the
8080A.
MEM/R, I/OR and INTA are generated by gating the DBIN signal from the processor
with the contents of the status latch. I/OR is used to enable an I/O input onto the
system data bus. MEM/R is used to enable a memory input.
INTA is normally used to gate an interrupt instruction onto the system data bus. When
used with the ,uPD8080A processor, the ,uPB8228 will decode an interrupt acknowledge status word during all three machine cycles for a multi-byte interrupt instruction.
For 8080A type processors that do not generate an interrupt acknowledge status word
during the second and third machine cycles of a multi-byte interrupt instruction, the
,uPB8228 will internally generate an INTA pulse for those machine cycles.
The,uPB8228 also provides the designer the ability to place a single interrupt instruction onto the bus without adding additional components. By connecting the +12 volt
supply to the INT A output (pin 23) of the ,uPB8228 through a 1 K ohm series resistor,
RESTART 7 will be gated onto the processor data bus when DBIN is active during an
interrupt acknowledge machine cycle.
MEM/W and I/OW are generated by gating the WR signal from the processor with the
contents of the status latch. I/OW indicates that an output port write is about to
occur. MEM/W indicates that a memory write will occur.
The data bus output buffers and control signal buffers can be asynchronously forced
into a high impedance state by placing a high on the BUSEN pin of the ,uPB8228.
Normal operation is performed with BUSEN low.
BLOCK DIAG RAM
PROCESSOR
DATA
BUS
D3
SYSTEM DATA BUS
VCC@-GND@-l
STSTB
DBIN
0 . . .-----------~
4
r-------------,----,
WR~~------------------------~
HLDA
0--------,---------1
602
"PB8228
ABSOLUTE
MAXIMUM RATINGS*
Operating Temperature . .;, . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . o°c to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
All Output or Supply Voltages . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to +7 Volts
All Input Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . ; -1.0 to +7.0 Volts
Output Currents . . . . . . . . . . . . . . . . . . . . . . . . "•...•........... 100 mA
Ta = 25°C
*COMMENT: Stress above those listed under "Absolute Maximum Ratings" may cause permenent
damage to the device. This is a stress rating only and functional operation of the device at these or
any othor conditions above those Indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
DC CHARACTE R ISTICS
LIMITS
PARAMETER
SYMBOL
Input Clamp Voltage, All Inputs
Vc
Input load Current, STSTB
IF
MIN
TYP
MAX
UNIT
TEST CONDITIONS
V
VCC • 4.75V; ICC· -5 mA
-1.0
500
/lA
02 and 06
750
/lA
VCC·5.25V
00,01,04,05, and 07
250
/lA
VF·0.45V
All Other Inputs
250
/lA
100
/lA
20
/lA
100
/lA
I nput leakage Current, STSTB
IA
VCC·5.25V
OBO through oB7
VA·5.0V
All Other Inputs
Input Threshold Voltage, All Inputs
VTH
Power Supply Current
ICC
Output low Voltage, DO through 07
VOL
0.8
2.0
VOH
All Other Outputs
Short Circuit Current, All Outputs
lOS
Off State Output Current;
All Control Outputs
10(of!)
INTA Current
liNT
mA
VCC·5V
VCC·5.25V
0.45
V
VCC,· 4.75V; 10l - 2 mA
0.48
V
10l -10mA
3.6
V
VCC -4.75V; 10H· -10/lA
2.4
V
All Other Outputs
Output High Voltage, DO through 07
V
190
15
90
mA
10H --1 mA
VCC·5V
100
/lA
VCC· 5.25V; Vo - 5.0V
-100
/lA
Vo = 0.45V
5
mA
(See Figure below)
+12V
" 1
INTA~
tXH
!to%
liNT
INTA TEST CIRCUIT
CAPACITANCE
Ta
= 25
D
C
LIMITS
MAX
UNIT
TEST
CONDITIONS
CIN
12
pF
VSIAS = 2.5V.
Output Capacitance
Control Signals
COUT
15
pF
VCC
I/O Capacitance
(Dor DB)
CliO
15
pF
f = 1 MHz
PARAMETER
SYMBOL
Input Capacitance
MIN
NOTE: This parameter is not '100% tested.
603
TVP
z
5.0V.
",PB8228
Ta - O·C to 70·C, VCC' 5V t 5%
AC CHARACTERISTICS
LIMITS
PARAMETER
SYMBOL
Width of Statu. Strobe
tpw
Setup Time, Status Inputs
00- 0 7
tss
Hold Time, Status Inputs 00-07
'SH
Delay from STSTB to any
Control Signal
'DC
Delay from OBIN to Control
Outputs
Delay from OBIN to Enable'
Disable B080A Bus
Delay from Syst..., Bus to
B080A Bus during Aead
Delay from
Outputs
WJ!I' to Control
MIN
TYP
MAX
UNIT
TEST
CONDITIONS
22
20
60
CL -100pF
'AA
30
CL - tOO pF
tAE
45
CL - 25 pF
tAD
30
CL - 25 pF
tWA
45
CL-l00pF'
Delay to Enable System Bus
OBO-OB7 after S'i'S'fB
tWE
30
CL -100pF
Delay from 8OBOA Bus 00-07
to System Bus OBO-OB7 during
Write
two
40
CL -100pF
Delay from System Bus Enable
to System Bu. OBO-OB7
tE
30
CL .100pF
HLOA to Read Status Outputs
tHO
25
Setup Time, System Bu.
Inputs to HLOA
tos
10
Hold Time. System BUI
Inputs to HLDA
tOH
20
CL -100pF
VCC
For 00-07' AI - 4 Kfi. A2 - ~fI.
CL· 25 pF. For all other outputs:
~::0
AI
Al - SOOfi. A2 - 1 KfI, CL -100pF,
OUTPUT
PIN
~ :LNO
~
TEST CIRCUIT
TIMING WAVEFORMS
---'I'-++_"!'-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
PROCESSOR OATA 8US _ _ _ _
INTA.liOR.;;m;m------h.
'+-_ _-+-__-+JI
DURING HLDA
-t-J~----_:__.I/""--------------
SYSTEM 8US DURING READ _ _ _ _ _ _ _
".PB8228
/.IP98238
-4--'1''----+-'1'-- -
- - --- -
-
- - --
i7OiiiorM"E'M'W'
iiOW Of MeM'W
PROCESSOR BUS DURING WRITE
SYSTEM BUS DURING WRITE _ _ _ _ _ -
-
-
-
-=:}
8USEN
SYSTEMBUSOUTPUTS------ -
----
,
Y
tE~
------------ -- - -- - ---
VOLTAGE MEASUREMENT POINTS: 0 0 .0 7 (whln outgun) Logic "0"· a.BV. Logic ","" 3.0V. All other ligna1. mlalurftt
.t 1.5V
604
,..PB8228
STATUS WORD CHART
DO
01
02
03
04
INTA
WO
STACK
HLTA
OUT
CD®00®®0®®@
o
000
0
0
001
1
0
0
0
0
1
1
0
0
0
1
0
0
1
0
0
0
0
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
0
0
0 I 0
0
0
0
0
0
I
0
0
1
0
0
1
O·
0
0
1
0
0
0
05
06
Ml
1
INP
0
26
MEMW
1
1
0
1
0
1
1
1
1
1
25
I/OR
1
1
1
1
1
0
1
1
1
1
27
23
I lOW
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
0
0
1
PI~
NO\
\
0
SIGNAL STATUS
605
OUTPUT
0
~------------------/-IPB8228 CONTROL SIGNALS
/-IP08080A
/-IPB8228
OUTPUT
",PB8228
PACKAGE OUTLINE
IlPB8228C
(Plastic)
ITEM
MILLIMETERS
INCHES
A
38.0 MAX
1.496 MAX
B
2.49
0.098
C
2.54
0.10
0
o 5;t 0.1
0.02 ± 0.004
1.3
E
33.02
F
1.5
0.059
G
2.54 MIN
0.10MIN
H
0.5MIN
0.02 MIN
I
5.2~
MAX
0.205 MAX
5.72 MAX
0.225 MAX
J
K
15.24
0.6
L
13.2
0.52
M
025 + 0.10
. - 0.05
+ 0.004
0.01 _ 0.002
IlPB8228D
(Ceramic)
ITEM
MILLIMETERS
INCHES
A
36.2 MAX
1.59 MAX
2.54
0.46 ± 0.05
33.02
1.02
3.2 MIN
1.0
3.5
4.5
15.24
14.93
0.25 ± 0.05
1.43
0.06
0.1
0.02 ± 0.004
1.3
0.04
0.13
0.04
0.14
0.18
0.6
0.59
0.Q1 ± 0.002
B
C
0
E
F
G
H
I
J
K
L
M
606
-
8228DS-R EV2-1-82-CA T
NEe
NEe Electronics U.S.A. Inc.
Microcomputer Division
/APD8237A-5
HIGH PERFORMANCE
PROGRAMMABLE DMA CONTROLLER
Description
The IlPD8237A-5 High Performance DMA Controller is a
peripheral interface circuit for microprocessor systems.
It is designed to improve system performance by allowing external devices to directly transfer information to or
from the system memory. Memory-to-memory transfer
Gapability is also provided. The IlPD8237A-5 offers a
wide variety of programmable control features to
Emhance data throughput and allow dynamic reconfiguration under program control.
The IlPD823·7A-5 is designed to be used with an external
B-bit address register such as the 8282. It contains four
independent channels and may be expanded to any
number of channels by cascading additional controller
chips.
The three basic transfer modes allow the user to pro~Jram the types of DMA service. Each channel can be
individually programmed to Autoinitialize to its original
condition following an End of Process (EOP).
Each channel has a full 64K byte address and word
count capabillity.
Features
[J Memory-to-memory transfers
[J Memory block initialization
[J Address increment or decrement
[J Four independent DMA channels
[] Multiple transfer modes: block, demand, Single word,
cascade
[] Independent Autoinitialization of all channels
[] EnablelDisable control of individual DMA requests
[J Independent polarity control for DREQ and· DACK
signals
[J End of Process input for terminating transfers
[J Software DMA requests
[J High performance: transfers up to 1.6 M-bytesl
second
[J Directly expandable to any number of channels
[J 40-pin plastic or ceramic DIP
Pin Configuration
I/OR
I/OW
MEMR
MEMW
READY
HlDA
ADDSTB
AEN
HRQ
CS
ClK
RESET
OACK2
DACKa
DRQ3
DRQ2
DRQl
DRQO
GND
A7
A6
AS
A4
EOP
A3
A2
Al
AO
VCC
DO
01
02
03
04
DACKO
DACKl
05
06
07
Pin· Identification
No.
Function
Symbol
Direction
I/OR
IN/OUT
In Idle state, I/OR is an Input control line used
by the CPU 10 read control r!.l!!!lers. In Active
stale, the I'PD8237A·5 uses I/OR as an OUlput
control signal to access data from a peripheral
durin!! a DMA Write.
I/OW
IN/OUT
In Idle state, the CPU uses I/OW as an Input
control signal to load Information to the
I'PD8237A·5. In Active slate, the I'PD8237A-5
uses I/OW as an oulput control signal to load
data 10 a peripheral during a DMA Read.
The rising edge of WR musl follow each data
byte transfer In order for .the CPU to write to
the 1'~237A-5. Holding I/OW low while 10g!!lIn!! CS does not eroduce the same effeCI.
MEMR
OUT
MEMR accesses data from a specified memory
location during memory-Io-perlpheral or
memor~-to-memor~ transfers.
MEMW
OUT
MEMW writes data to a specified memory location during perlpheral-to-memory or memory-tomemor~ transfers.
IN
Pin 5 Is
READY
IN
The READY signal can extend memory read and
write pulses for slow memories or I/O
eerleherals.
HlDA Indicates that th.e CPU has relinquished
control of the sl(slem buses.
alwa~s
tied high.
HlDA
IN
ADDSTB
OUT
This signal slrobes the upper address byte from
Do·Dzlnto an external latch.
AEN
OUT
This signal allows the exlernal latch to output
the upper address byte by disabling the system
bus during DMA cycles. You should use HlDA
and AEN to deselect I/O peripherals that may be
erroneously accessed during DMA transfers.
The I'PD8237A-5 deselects IIsalf during DMA
transfers.
10
HRQ
OUT
This signal requests control of the system bus.
The ,..PD8237 A-5 Issues this signal In response
to software requests or DRQ· inputs from
peripherals.
11
CS
IN
The CPU uses CS to Hleel the I'PD8237A-5 as
an 110 device during an 110 Read or Write by
~: ~:~·b~~.sti°~~;~~~I:~:m~~:I~~I~:~~
pie transfers to or from the I'P08237A-5 as long
as i70R or fiOW Is toggled following each
transfer.
12
ClK
IN
Controls Internal operations and data transfer
rate.
13
RESET
IN
Clears the Command, Status, Request, and
Temporary registers, the first/last fllplfiop, and
sets the Mask register. The I'PD8237A-5 Is In
Idle state after a Reset.
14,15
24,25
DACKo'
DACK 3
OUT
These lines Indicate an active channel. They
sre sometimes used to select a peripheral. Only
one DACK may be active at any time. All OACK
lines are Inactive unless OMA has conlrol of the
bus. You may program tha polarity of these
lines; however, Reset Initializes them to active
low.
16-19
DRQ O-DRQ3
IN
These are asynchronous channel requast Inputs
used by peripherals to request DMA service. In
a Fixed Priority scheme, DRQO has the highest
prlorlly and DRQ3 has the lowest. You may program the polarity of these IInss; however, Reset
Initializes them 10 active high.
20
GND
21·23,
28·30
00- 0 7
Ground.
IN/OUT
During an 110 Read, the CPU enables theH
lines as outputs, allowing It to read an Address
register, a Word Count register, or the Status or
Temporary register. During an 110 Write, theH
lines are enabled as Inputs, allowing the CPU to
r.::sg~ ~~~:a?:~:~,:~::' ::'!'':::;r~:-
are output to the data bus to be strobed to an
external latch via ADDSTB.
31
607
V!:i!:i
Power Supply.
D
",PD8237A-5
No.
32-35
36
Symbol
Direction
During DMA Idle states, these linea ara Inputa,
allowing the CPU to load or examlna control
reglstere. During DMA Active atatea, these linea
are outputs that provide the 4 LSB 01 the output address.
IN/OUT
EOP signals that DMA service has been completed. When the word count 01 a channel
becomea zero, tha I'PD8237A-5 pulaaa EOP
low to nollfy the peripheral that DMA service
la complete. The peripheral may pull EOP low
to prematurely end DMA service. Internal or
external receipt 01 EOP csuse. the currenlly
acllve channel to end service, set Ita l'C bit In
the Status reglater, and reaet It. request bit. II
tha channel la pmgrammed lor Autolnillallzalion, the current registers are updated Irom
the base reglsterll. Otherwl.e, the channel'.
mask bit I. aet and the content, 01 the register
are unaltered.
EOP la output when TC lor channel 1 occurs
during memory-to-memory trans'era. EOP
applies to the channel with an acllve DACK.
Whan DACKo-DACK3 are Inactive, external
EOPs are Ignored.
It la racomrnended that you use an external
pullup resistor 01 3.3kQ or 4.7kQ. This pin cannot sink the current pa8Sad by a lkQ pullup.
37-40
81, 82, 83, and 84. If more time is needed for a
transfer, a wait state, 8W, can bOe inserted using the
READY line.
A memory-to-memory transfer requires read-frommemory and write-to-memory operations. The states
811, 812, 813, and 814 provide the read-from operation. 821, 822, 823, and 824 provide the write-to part
of the transfer. The byte is stored in the Temporary
register between operations.
Idle State
When there are no pending service requests, the
IJPD8237A-5 is in the Idle state; more specifically, in 81.
ORO lines and C8 are sampled to determine requests
for DMA service and CPU attempts to inspect or modify
the registers of the IJPD8237A-5, respectively. The CPU
can read or write to the registers when C8 and HLDA
are low. AO-A3 are used as inputs to ~PD8237A
and select the registers affected. The liaR and IIOW
lines select and time the reads and writes. An internal
flip-flop generates an additional address bit which
determines the upper or lower byte of the Address and
Word Count registers. This flip-flop can be reset by
master Clear, Reset, or a software command.
When C8 and HLDA are low (Program Phase), the
IJPD8237A-5 can execute special software commands.
When C8 and IIOW are active, the commands are
decoded as addresses and do not use the data bus.
Active State
When a channel requests service while the IJPD8237A-5
is in Idle state, the IJPD8237A-5 outputs an HRO to the
CPU and enters the Active state. DMA service takes
place in the Active state, in one of the four modes
described below.
Byte Transfer Mode
In this mode, a one-byte transfer is made during each
HRO/HLDA handshake. HRO goes active when ORO
goes active. The CPU responds by making HLDA active,
and the one-byte transfer takes place. After the transfer, HRO goes inactive, the word count is decremented,
and the address is incremented or decremented. If the
word count goes to zero, a Terminal Count (TC) causes
Function
IN/OUT
These linea are outputs that provide the lour
LSB of the address. Theae lines are active
only during DMA aarvlce.
Functional Description
The IJPD8237A-5 has three basic control logic blocks,
as shown in the block diagram. The Command Control
block decodes commands issued by the CPU to the
IJPD8237A-5 before DMA requests are serviced. It also
decodes the Mode Control word of each channel. The
Timing Control block generates the external control
signals and the internal timing. The Priority Encoder
block settles priority contentions among channels
simultaneously requesting service.
DMA Operation
The IJPD8237A-5 operates in two states: Idle and Active.
Each of these is made up of several smaller states
equal to one clock cycle. The inactive state, 81, is
entered when there are no pending DMA requests. The
controller is inactive in 81, but the CPU may program it.
80 is the initial state for DMA service; the IJPD8237A-5
requests a hold, but the CPU has not acknowledged.
Transfers may begin upon acknowledgement from the
CPU. The normal working states of DMA service are
Block Diagram
AO-A3
RESET
READY
CLOCK
AEN
AOOSTB
MEMR
MEMW
1I0R
1I0W
DO-D7
ORao-ORa3
HLOA
HREa
OACKO-OACK3
608
",PD8237A-5
an Autoinitialize if the channel has been programmed
for it.
ORO is held active only until the corresponding OACK
goes active when a single transfer is performed. If ORO
is held active for a longer period, HRO will become
inactive after each transfer, become active again, and a
one-byte transfer will be made after each rising edge of
HLOA. This assures a full machine cycle between OMA
transfers in SOSOAlSOS5A systems. Timing between the
/APOS237A-5 and other bus control protocols depends
on the CPU being used.
2nd Level
CPU
Hold
~PD8237A-5
1st Level
DACK
HLDA
Initial
Device
Block Transfer Mode
In this mode, the /APOS237A-5 makes transfers until it
encounters a TC or an external EOP. Hold ORO active
only until OACK goes active. The channel will Autoinitialize at the end of the OMA service if it has been programmed to do so.
Demand Transfer Mode
In this mode, the /APOS237A-5 makes transfers until it
encounters a TC or an external EOP, or until ORO
becomes inactive. This allows the device requesting
service to stop the transfers by sending ORO inactive.
The device can resume service by making ORO active.
The Current Address and Current Word Count registers
may be examined during the time between services
when the CPU is allowed to operate. Autoinitialization
can occur only after a TC or EO'P at the end of the
OMA service. After an Autoinitialization, there must be
an active-going ORO edge to begin new OMA service.
Cascade Mode
In this mode, you can expand your system by cascading several /APOS237A-5s together. Connect the HLOA
and HRO signals from the additional /APOS237A-5s to
the ORO and OACK signals of a channel of the initial
/APOS237A-5. This scheme allows the additional devices
to send the OMA requests through the priority resolution circuitry of the preceding device, preserving the
priority chain and forcing the device to wait its turn to
acknowledge requests. The cascade channel in the initial device does not output any address or control
signals because its only function is that of assigning
priorities. The /APOS237A-5 responds to ORO with
OACK, but all outputs except HRO are disabled.
The following figure shows two /APOS237A-5s cascaded
into two channels of another one, forming a two-level
OMA system. You could add more devices at the second level by using the leftover channels of the first
level; likewise, you could add more devices to form a
third level by cascading into the channels of the second
level.
~PD8237A-5
Additional
Devices
Memory-to-Memory Transfers
Use Block Transfer mode for memory-to-memory transfers. Mask out channels 0 and 1, and initialize the
channel o word count to the same value as channel 1.
Setting bit CO of the command register to 1 makes
channels 0 and 1 operate as· memory-to-memory transfer channels. Channel 0 is the source address, channel
1 is the destination address, and the ch-annel 1 word
count is used. Initiate the memory-to-memory transfer
by setting a OMA request for channel O. You can write
a single source word to a block of memory when channel 0 is programmed for a fixed source address. The
/APOS237A-5 responds to external EOP signals during
these transfers, but no OACK outputs are active. The
EOP input may be used by data comparators doing
block searches to end service when a match is found.
Au~oinltlalizatlon
A channel may be set for Autoinitialize by programming
a bit in the Mode register. Autoinitialize restores the
original values of the Current Address and Current
Word Count registers from the Initial Address and Initial
Word Count registers of that channel. The CPU loads
the Current and Initial registers simultaneously and they
are unchanged through OMA service. EOP does not set
the mask bit when the channel is in Autoinitialize. The
channel can repeat its service following Autoinitialize
without CPU intervention.
Priority Resolution
Two software-selectable priority resolution schemes are
available on the /APOS237A-5: Fixed Priority and Rotating Priority. In the Fixed Priority scheme, priority is
assigned by the value of the channel number. Channel
3 is the lowest priority and channel 0 is the highest
priority.
In the Rotating Priority scheme, the channel that was
just serviced assumes the lowest priority and the other
channels move up accordingly. This guarantees that a
device requesting service can be acknowledged after
no more than three other devices have been serviced,
preventing any channel from monopolizing the system.
Transfers
There are three types of transfers that can be performed
by the three active transfer modes: Read, Write, and
Verify. Read transfers activate MEMR and I/OW to
move memory data to an I/O device. Write transfers
activate I/OR and MEMW to move data from an I/O
device to memory. Verify transfers are not really transfers; the /APOS237A-5 goes through the motions of a
transfer but the memory and I/O lines are not active.
1st Service
Highest
o
Lowest
2
3
2nd Service
I-Service"
609
3rd Service
2--Servlce
3-Request""-.
........ 0
1
3-Servlce
0
\...1
2
fJPD8237 A·5
The highest priority channel is selected on each activegoing HLDA edge. Once service to a channel begins, it
cannot be interrupted by a request from a higher priority channel. A higher priority channel gets control only
when the lower priority channel releases HRQ. The
CPU gets bus control when control passes from channel to channel, ensuring that a rising HLDA edge can
be generated to select the new highest priority request.
Current Word Count Register
There is a Current Word Count register for each channel. Program this register with the value of the number
of words to be transferred, minus one. The word count
is decremented after each transfer and intermediate
values are stored in this register during the transfer. A
TC is generated when the word count is zero. The CPU
writes or reads this register in a-bit bytes during Program Phase. An Autoinitialize restores this register to
its initial value. After an internally generated EOP, the
contents of this register will be FFFFH.
Initial Address and Initial Word Count Registers
There is an Initial Address register and an Initial Word
Count register for each channel. The initial values of
the associated Current registers are stored in these registers. The values in these registers are used to restore
the Current registers at Autoinitialize. During DMA programming, the CPU writes the Initial registers and the
corresponding Current registers at the same time, in
a-bit bytes. Intermediate values in the Current registers
are overwritten if you write to the Initial regil?ters while
the Current registers contain intermediate values. The
CPU cannot read the Initial registers.
Transfer Timing
You can cut transfer timing, if the system allows, by
compressing the transfer time to two clock periods.
Since state 3 (S3) extends the access time for the read
pulse, you can eliminate S3, making the width of the
read pulse equal to the write pulse. A transfer is then
made up of S2 to change the address and S4 to perform the read or write. When the~address lines Aa-A15
need to be updated, S1 states occur.
Generating Addresses
The eight MSBs of the address are multiplexed on the
data lines. These bits are output to an external latch
during S1, after which they can be placed on the
address bus. The falling edge of ADDSTB loads the bits
from the data lines to the latch. AEN places the bits on
the address bus. The eight LSBs of the address are
directly output on lines AO-A7. Connect AO-A7 to the
address bus.
Sequential addresses are generated during Block and
Demand Transfer mode operations because they include
several transfers. Often, data in the external address
latch does not change; it changes only when a carry or
borrow from A7 to Aa occurs in the sequence of
addresses. S1 states are executed only when Aa-A15
need to be updated. In the course of lengthy transfers,
S1 states may be executed only once every 256
transfers.
Registers
The following chart summarizes the registers of the
J.lPDa237A-5.
Register
Current Address registers (4)
Current Word Count registers (4)
Initial Address registers (4)
Initial Word Count registers (4)
Command register
Mode registers (4)
Request register
Mask register
Status register
Temporary register
Temporary Address register
Temporary Word Count register
8lgnal.
Channel
Operation
Ci
IIOR IIOW A3
6
4
4
Current Address Register
There is a Current Address register for each channel.
This register holds the address used for DMA transfers;
the address is incremented or decremented after each
transfer and the intermediate values are stored here
during the transfer. The CPU writes or reads this register in a-bit bytes. An Autoinitialize restores this register
to its initial value.
0
0
AO·A7
A8· A 15
Current
Address Read
0
0
0
0
0
0
0
0
AO·A7
AO·A15
Initial & Current
Word Count Write
0
0
0
0
0
0
0
1
1
WO,W 7
WO,W 15
Current
Word Count Read
0
0
0
0
0
0
0
1
1
WO,W 7
WO,W 15
0
0
1
1
AO·A7
AO·A15
0
0
0
0
1
1
AO·A7
AO·A15
0
0
0
0
1
1
WO,W 7
WO,W 15
0
0
1
1
WO,W 7
WO,W 15
Initial & Current
Word Count Write
0
Current
Word Count Read
0
Initial & Current
Address Write
0
0
1
1
0
0
0
0
Ao·A7
AO·A15
Current
Address Read
0
0
1
1
0
0
0
0
AO·A7
AO·A15
0
0
1
1
0
0
1
1
WO,W7
WO,W15
0
0
1
1
0
0
1
1
WO,W7
WO,W 15
Initial & Current
Address Write
0
0
1
1
AO·A7
AO·A15
Current
Address Read
0
0
1
1
AO·A7
AO·A 15
0
0
1
1
WO,W7
WO,W15
0
0
Initial & Current
Word Count Write
0
Current
Word Count Read
0
Word Count and Addre •• Regl.ter Command Code.
610
DO·D 7
0
0
Current
Word Count Read
16
16
Internal
Flip.
Flop
0
0
Initial & Current
Word Count Wrlta
a
a
AO
0
0
Current
Address Read
a
Ai
Initial & Current
Address Write
Initial & Current
Address Write
Bits
16
16
16
16
A2
WO,W 7
WO,W15
/JPD8237 A·5
7654321
Command Register·
The CPU programs this ·register during Program Phase,
The register can be cleared with Reset.
o Memory-to-memory disable
O·Reset request bit
1 Set request bit
1 Memory-to-memory enable
o Channel 0 address hold disable
1 Channel 0 address hold enable
XlfbltO=O
Mask Register
There is a mask bit for each channel which can disable
an incoming ORO. If the channel is not set for Autoinitialize, each mask bit is set when its channel produces
an EOP. Each bit can be set or cleared under software
control. Reset clears the register. This disallows OMA
requests until they are permitted by a Clear Mask
Register instruction.
o Controller enable
1 Controller disable
o Normal Timing
1 Compressed Timing
X If bit 0 =1
o Fixed Priority
1 Rotating Priority
o Late write
1 Extended write
X If bit 3 = 1
L.
-------...,.-t[
' - - - - - - - - - - - - 1[
0 ORO active high
1 ORO active low
0 DACK active low
1 DACK active high
o Clear malk bit
1 Set mask bit
Mode Register
There is a Mode register associated with each channel.
When the CPU writes to this register during the Program Phase, bits 0 and 1 determine on which channel
Mode r~gister the operation is performed.
- You may also write all four bits of the Mask register
with a single command.
o Clear Channel 0 mask bit
1 Set Channel 0 malk bit
o Clear Channel 1 malk bit
~.
1 Set Channel 1 maak bit
00
01
10
11
Channel
Channel
Channel
Channel
0
1
2
3
00 Verify transfer
01 Write transfer
10 Read transfer
11 Illegal
. · X X If bits 6 and 7
o Clear Channel 2 mask bit
1 Set ·Channel 2 mask bit
o Clear Channel 3 mask bit
1 Set Channel 3 mask bit
=
11
Status Register
The Status register indicates which channels have
made OMA requests and which channels have reached
TC. Each time a channel reaches TC, including after
AutOinitialization, bits 0-3 are set. Status Read and
Reset clear these bits. Bits 4-7 are set when a channel
is requesting service. The CPU can read the Status
register.
o Disable autoinitialize
1 Enable autoinitialize
o Address Increment
1 Address decrement
00
01
10
11
Demand mode
Single mode
Block mode
Cascade mode
Request Register
This register allows the J.lP08237A-S to respond to OMA
requests from software as well as hardware. There is a
bit pattern for each channel in the Request register.
These bits can be prioritized by the Priority Resolving
circuitry and are not maskable. Each bit is set or reset
under software control or cleared when TC or an external
EOP is generated. A Reset clears the entire register.
The correct data word is loaded by software to set or
reset a bit.
Software requests receive service only when the chan~
nel is in Block mode. The software request for channel
o should be set at the beginning of a memory-to-memory
transfer.
1
1
1
1
Channel
Channel
Channel
Channel
1 Channel
1 Channel
1 Channel
1 Channel
0 TC
1 TC
2 TC
3 TC
0 DMA
1 DMA
2 DMA
3 DMA
request
request
request
request
Temporary Register
The Temporary register holds data during memory-tomemory transfers. The CPU can read the last word
moved when the transfer is complete. This register
always contains the last byte transferred in a memoryto-memory transfer unless cleared by a Reset.
611
1:1
U
",PD8237A-S
Software Commands
There are two software commands that can be executed in the Program Phase. These commands are independent of data on the data bus.
Clear First/Last Flip-Flop
You may issue this command before reading or writing
any word count or address information. It allows the
CPU to access registers, addressing upper and lower
bytes correctly, by initializing the flip-flop to an identifiable state.
Master Clear
This command produces the same effect as Reset. It·
clears the Command, Status, Request, Temporary, and
Internal First/last Flip-Flop registers, sets the Mask register, and causes the JAP08237A-S to enter Idle state.
The following chart illustrates address codes for the
software commands.
A3
A2
A1
AO
./OW
./OR
C)per..lon
0
1
1
1
1
1
0
1
1
1
0
0
0
0
0
1
0
0
Read Status register
Write to Command register
Write to Request register
Write a Mask register bit
Write to Mode register
Clear byte pointer f"p-flop
Read Temporary register
Master Clear
Write a" Mask register bits
A" other bit combinations are "'egal.
Application Example
The following diagram shows an application using the
/AP08237A-S with an 8088. The /AP08237A-S sends a
hold request to the CPU whenever there is a valid OMA
request from a peripheral device. The JAP08237A-S
takes control of the Address, Oata, and Control buses
when the CPU replies with an HlOA signal. The
address for the first transfer appears in two bytes: the
eight lSBs are output on AO-A7 and the eight MSBs
are output on the data bus pins. The contents of the
Handshake with Device
Requesting Service
data bus pins are latched to the 8282 to make up the
16 bits of the address bus. Once the address is latched,
the data bus transfers data to or from a ~emory location or I/O device, using the control bus Signals generated by the /AP08237A-S.
AC Characteristics Supplementary Information
All AC timing measurement points are 2.0V for hig~ and
0.8V for low, for both inputs and outputs. The loading
on the outputs is one TTL gate plus 100 pF of capacitance for the data bus pins, and one TTL gate plus
SO pF for all other outputs.
Recovery time between successive read and write
inputs must be at least 400 ns. I/O or memory write
pulse widths will be TCy-100 ns for normal OMA
transfers and 2 TCy-100 ns for extended cycles. I/O
or memory reads will be 2 TCY - SO ns for normal reads
and TCY- SO ns for compressed cycles. T001 and
T002 are measured on two different levels. T001 at
2.0V, T002 at 3.3V with a 3.3 kQ pull-up resistor.
OREO and OACK are both active high and low. OREO
must be held in the active state (user defined) until
OACK is returned from the /AP08237A-5. The AC waveforms assume these are programmed to the active high
state.
Absolute Maximum Ratings *
Tentative
Ambient Temperature under Bias
Storage Temperature
Voltage on any Pin with respect to Ground
Power Dissipation
O°C to + 70°C
- 65 °C to 150°C
- 0.5V to + 7V
1.5 Watt
"COMMENT: Exposing the device to stresses above
those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits described in
the operational sections of this specification. Exposure
to absolute maximum rating conditions for extended
periods may affect device reliability.
DC Characteristics
Ta
=O°C.to + 70°C; VCC = +5V:t 5%
LImits
Parameter
8088
CPU
Symbol
Typ----\
~
I---
- - - - - l l f_ _ _ _ _ _ _
E'tern.'~
~ r---·---------
I-
'DCTR
-
I-tAFC
r~-r---U
tOCTW
"-'__~/'<-_~
'"(ForE,tended.J~'lte)
--
)jl-I-------
~~~~--.--.........- - I - I E P W -
-
,~r-I---_tDCTW
-4,~~r'AK
_ _ _ _ _ _ _ _ __
~I
~ \\ \ \ \\W~ ill IV/I /11 1// I
s •• Note 2, AC Characteristics. Dp.4A Mode
615
-
/JPD8237A-S
Timing Waveforms (Coni.)
Memory·to-Memory Transfer
so
S14
S21
S22
S23
S1
S24
ADDSTB
rAO-A7------+--{
IAFAB'_
IAHS
Addre •• Valid
00-07 - - - - - - 1 1 - - - (
EOP
OUT
. Ii
IEPW
EXT EOP
\\\\\\\S\\\\\\\~ZZZZZZZ
Ready
elK
IRS
READY
\\\\\\\\\\\1
616
~PD8237A·5
Timing Waveforms (Cont.)
Compressed Transfer
ClK
---_.....
AO-A7
READY
Reset
V_C_C_ _ _ _ _
-J;1~-----------------tRSTD----------------~
/I
1 - - - - - - tRSTW--------i
)t-
RESET_ _ _ _ _ _ _ _ _ _ _ _ _ _- J
tRSTS=i
-----------------------------------------------------------1ltl----~
I/ORorliOW
-------
Package IOutllne
",PD8237 AC-5
Plastic
Item
A
~
.: .:
- ----- r-~Fr]
H.l1Vltlt1
:,rinJ
jt
~'I=------=~G
• • -..
B
MHllmet.,.
51.5 Max
1.82
Inche.
2.028 Max
0.084
_____~c~__________~2~.M~±~0~.~1__________~0~.1~0~±~0.~00=4~----D
E
F
G
H
_
K
0.5 ± 0.1
48.28
1.2 Min
2.M Min
0.5 Min
5.22 Max
5.72 Max
15.24
13.2
0.019 ± 0.004
1.9
0.047 Min
0.10 Min
0.019 Min
0.208 Max
0.225 Max
0.600
0.520
M
8237A·5DS·1·82·TRIUM·CAT
61-7
II
•
NOTES
618
NEe
"PD8243
NEe Electronics U.S.A. Inc.
Microcomputer Division
INPUT/OUTPUT EXPAN,DER FOR
JLPD8048 FAMILY
OEseR IPTION
The J,lPD8243 input/output! expander is directly compatible with the J,lPD804,8 family
of single-chip microcomputers. Usirtg NMOS technology the J,lPD8243 provides high
drive capabilities while requiring only a single +5V supply voltage.
The J,lPD8243 interfaces to the J,lPD8048 family through a 4·bit I/O port and offers
four 4-bit bi-directional static I/O ports. The ease of expansion allows for multiple
J,lPD8243's to be added using the bus port.
The bi-directional 1/0 ports of the J,lPD8243 act as an extension of the I/O capabilities
of the J,lPD8048 microcomPlJter family. They are accessible with their own AN L, MOV,
and OR L instructions.
FEATURES
• Four 4-Bit I/O Ports
• Fully Compatible with J,lPD8048 Microcomputer Family
• High Output Drive
• NMOS Technology
• Single +5V Supply
• Direct Extension of Resident J,lPD8048 I/O Ports
• Logical AND and OR Directly to Ports
• Compatible with Industry Standard 8243
• Available in a 24-Pin Plastic Package
P50
vee
P40
P51
P41
P52
P42
PS3
P43
P60
cs
P61
PROG
P62
P23
P63
P22
P21
P71
P20
P70
Rev/1
619
I]
",PD8243
General Operation
The I/O capabilities of the J-LPD8048 family can be enhanced in four 4-bit I/O port
increments using one or more J-LPD8243's. These additional I/O lines are addressed as
ports 4-7. The following lists the operations wh ich can be performed on ports 4-7.
• Logical AND Accumulator to Port.
• Logical OR Accumulator to Port.
• Transfer Port to Accumulator.
• Transfer Accumulator to Port.
Port 2 (P20-P23) forms t!:'te 4-bit bus through which the J-LPD8243 communicates with
the host processor. The PROG output from thepP()8048 family provides the necessary timing to the J-LPD8243. There are two 4-bit nibbles il')volved in each data transfer.
The 'first nibble contains the op-code and port address followed by the secondnibble
containing the 4-bit data. Multiple J-LPD8243's can be used for additional I/O. The
output lines from the J-LPD8048 family can be used to form the chip selects for the
additional J-LPD8243's.
'
Power On Initialization
Applying power to the J-LPD8243 sets ports 4-7 to the tri-state mode and port 2 to the
input mode. The state of the PROG pin at power on may be either high or low. The
PROG pin must make a high-to-Iow transition in order to exit from the power on
mode. The power on sequence is initiated any time VCC drops below lV. The table
below shows how the 4-bit nibbles on Port 2 correspond to the J-LPD8243 operations.
Port Address
Op-Code
P21
0
P20
Address Code
0
0
1
1
Instruction Code
Port 4
P23
0
P22
0
1
Port 5
0
1
Write
0
Port 6
1
0
ORLD
1
Port 7
1
1
ANLD
Read
For example an 0010 appearing on P20-P23, respectively, would
result in a Write to Port 4.
Read Mode
There is one Read mode in the J-LPD8243. A falling edge on the PROG pin latches the
op-code and port address from input Port 2. The port address and Read operation are
then decoded causing the appropriate outputs to be tri-stated and the input buffers
switched on. The rising edge of PROG terminates the Read operation. The Port
(4,5,6, or 7) that was selected by the Port address (P21-P20) is returned to the tri-state
mode, and Port 2 is switched to the input'mode.
Generally, in the read mode, a port will be an input and in the 'write mode it wiil be an
output. If during program operation, the J-LPD8243's modes are changed, the first read
pulse immediately following a write should be ignored. The subsequent read signals a~e
valid. Reading a port will then force that port to a high impedance state.
Write Modes
There are three write modes in the J-LPD8243. The MOVD Pp,A instruction from the
J-LPD8048 family writes the new data directly to the specified port (4,5,6, or 7). The
old data previously latched at that port is lost. The OR LD Pp,A instruction performs
a logical OR between the new data and the data currently latched at the selected
port. The result is then latched at that port. The final write mode uses the AN LD
Pp,A instruction. It performs a logical AND between the new data and the data currently latched at the specified port. The result is latched at that port.
The data remains latched at the selected port following the logical manipulation until
new data is written to that port.
620
.FUNCTIONAL
DESCRIPTION
,..PD8243
BLOCK DIAGRAM
PIN IDENTIFICATION
PIN
NO.
SYMBOL
2-5
1,21-23
17-20
13·16
P40- P43
P50- P53
P60- P63
P70- P73
The four 4-bit static bi-directional I/O ports. They
are programmable into the following modes:
input mode (during a Read operation); low
impedance latched output mode (after a Write
operation); and the tri-state mode (following a
Read operation). Data appearing on I/O lines
P20-P23 can be written directly. Tl)at data can
also be logically ANDed or ORed with the previous
data on those lines.
6
~
Chip Select input (active-low). When the J-LPD8343
is deselected (Cs = 1), output or internal
status changes are inhibited.
7
PROG
Clock input pin. The control and address information are present on port lines P20-P23 when PROG
makes a high-to-Iow transition. Data is present on
port lines P20-P23 when PROG makes a low-to-high
transition.
8-11
P20- P 23
P20-P23 form a 4-bit bi-directional port. Refer to
PROG function for contents of P20-P23 at the
rising and falling edges of PROG. Data from a
selected port is present on P20-P23 prior to the
rising edge of PROG if during a Read operation.
12
GND
The J-LPD8041 /8741 ground potential.
24
VCC
+5 volt supply.
621
FUNCTION
",PD8243
Operating Temperature
Storage Temperature ....
Voltage on Any Pin
Power Dissipation . . . . . . . . . . . . . .
Note:
CD
... O°C to +70°C
-65°C to +150°C
-0.5 to +7 VoltsCD
.... " .... 1 W
ABSOLUTE MAXIMUM
RATINGS*
With respe.ct to grOlmd.
Ta = 25°C
*COMMENT: Stress aDOve those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
Ta = O°C to +70°C; VCC = +5V ±10%
DC CHARACTERISTICS
LIMITS
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
0.8
V
TEST
CONDITIONS
Input Low Voltage
VIL
-0.5
Input High Voltage
VIH
~.O
Output Low VoLtage (Ports 4· 7)
VOLl
Output Low Voltage (Port 7)
VOl2
Output Low Voltage (Port 2)
VOLJ
Output High Voltage (Ports 4·7)
VOHI
2.4
V
IOH = 240 IlA
Output High Voltage (Port 2)
VOH2
2.4
V
IOH = 100 IlA
5 mA Each Pin
VCC + 0.5
V
0.45
V
IOL = 5 mAW
V
IOL=20mA
V
IOL = 0.6 mA
0.45
Sum of All IOl From 16 Output.
IOL
100
mA
Input Leakage Current (Ports 4·7)
IILI
-10
20
IlA
VIN = VCC to OV
Input Leakage Current (Port 2,
IIL2
-10
10
IlA
VIN = VCC to OV
20
mA
CS, PROG)
V CC Supply. Current
Note:
CD
10
ICC
Refer to graph of additional sink current drive.
Ta = O°C to T70°C; VCC = +5V ±10%
AC CHARACTERISTICS
LIMITS
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
TEST
CONDITIONS
80 pF Load
Code Valid Before PROG
tA
100
Code Valid After PROG
tB
60
20 pF Load
Data Valid Before PROG
tc
200
80 pF Loed
20
Data Valid After PROG
to
Port 2 Floating After PROG
tH
PROG Negative Pulse Width
tK
Ports 4·7 Valid After PROG
tpo
Ports 4·7 Valid BeforelAfter PROG
tLP1
Port 2 Valid After PROG
tACC
CS Valid BeforelAfter PROG
tcs
20 pF Loed
150
20 pF Load
700
100 pF Loed
650
80 pF Load
700
100
50
TIMING WAVEFORMS
PROG
PORT 2
I------'ACC-'-----t
PORT 2
PORTS4-7 __________~----------~~~--~----~------~----------~
PORTS 4-7
622
",PD8243
CURRENT SINKING
CAPABI L1TY
CD
125
3
5
6
/0 ,'1 1'2 1'3 ,14 1'5 ,'6·
MAXIMUM SINK CURRENT AT ANY PIN (VOL = 0.4VI
MAXIMUM IOL WORST CASE PIN IN rnA.
Note;
1ge
VIH
Vee - 2.0
Output Low Voltage
VOLl
MAX
UNIT
TEST
CONDITIONS
0.8
Vee
0.45
IOL
(Ports 4·7)
Output Low Voltage (Port 7)
VOL2
Output Low Voltage (Pori 2)
VOL3
OLltput High Voltage
VOHl
Vee··0.5
Output High Voltage {Port 21
VOH2
Vee - 0.5
Sum of AII10l From 16
IOL
80
Input Leakage Current
(Ports 4·7)
IILl
+1
SmA
l'J
IOV20 mA
0.45
IPort,4·71
rnA
5 rnA Each Pin
Outputs
Input Leakage Current
Cs, PROGI
IIL2
V CC Supply Current
leel
300
Power Down SUlOPly Current
lee2
10
-1
+1
(Port 2,
Note.
T a'- - 40"'C to + 8Soc.
CD Refer 10 graph of additional Sink current drive.
Vee -
+5V
AC CHARACTERISTICS
+ 10~
LIMITS
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
TEST
CONDITIONS
Code Valid Before PROG
tA
100
ns
Code Valid After PROG
tB
60
n,
20 pF Load
Data Valid Before PROG
tc
200
n,
BO pF Load
Data Valid After PROG
to
20
ns
20 pF Load
Port 2 Floating After PROG
tH
0
ns
20 pF Load
PROG Negative Pulse Width
tK
900
PortS 4·7 Velid After PROG
tpo
PortS 4·7 Valid Before/After PROG
tLPl
Port 2 Valid Aher PROG
tACC
~ Valid Before/Aher PROG
tcs
150
BO pF Load
n,
700
ns
100 pF Load
nB
100
160
n.
BO pF Load
ns
50
TIMING WAVEFORMS
PROG
PORT 2
......- - - - ' A C C - - - - - - t
PORT 2
PORTS 4·7 -----r------..;.:;::-.:.:;::,;;;;:;.;;;;;.:.;.;;;.;.;.;;;;;:.;;..------r-----~
PORTS~·7
628
flPD82C43
CURRENT SINKING
CAPABI LlTY
CD
3
4
5
6
7
9
10 11
12
13
MAXIMUM SINK CURRENT AT ANY PIN 1VOl· 0.4VI
MAXIMUM IOl WORST CASE PIN IN mAo
14
15
16
Note: (]) This curve plots the guaranteed worst case current sinking capability of any 1/0 port line versus the total sink current of all pins.
The /JP082C43 is capable of sinking 5 mA (for VOL =: O,4VI through each of the 161/0 lines simultaneously. The current sinking
curve shows how the individual 110 line drive increases if all the Ifa lines are not fully loa~ed.
PACKAGE' OUTLI NE
J,tPD82C43
:===A__--;I:~ ~------~-rr~~
:
---'------oo-il t
G
+~
0-15°
\--
PLASTIC
ITEM
A
o
G
M
MILLIMETERS
INCHES
33 MAX
1.3 MAX
2.&3
0.1
2.54
0.1
0.5! 0.1
0.02! 0.004
27.94
1.1
1.5
0.059
2.54 MIN
0.1 MIN
0.5 MIN
0.02 MIN
5.22 MAX
0.205 MAX
5.72 MAX
0.225 MAX
15.24
0.6
13.2
0.52
0.25 +0.10
-0.05
+0.004
0.01 -0.0019
iii
82C43DS-REV1-1-82-CAT
629
NOTES
630
NEe
",PD8251
",PD8251A
NEe Electronics U.S.A. Inc.
Microcomputer Division
PROGRAMMABLE COMMUNICATION INTERFACES
DESCRIPTION
FEATURES
The pPD8251 and pPD8251A Universal Synchronous/Asynchronous Receiver/
Transmitters (USARTs) are designed for microcomputer systems data communications.
The USART is used as a peripheral and is programmed by the 8080A or other
processor to communicate in commonly used serial data transmission techniques including IBM Bi-Sync. The USART receives serial data streams and converts them into
parallel data characters for the processor. While receiving serial data, the USART will
also accept data characters from the processor in parallel format, convert them to serial
format and transmit. The USART will signal the processor when it has completely
received or transmitted a character and requires service. Complete USART status
including data format errors and control signals such as TxE and SYNDET, is available
to the processor at any time.
• Asynchronous or Synchronous Operation
•
•
•
•
•
•
•
•
•
Asynchronous:
.
Five 8-Bit Characters
Clock Rate - 1, 16 or 64 x Baud Rate
Break Character Generation
Select 1, 1-1/2, or 2 Stop Bits
False Start Bit Detector
Automatic Break Detect and Handling (pPD8251A)
Synchronous:
Five 8-Bit Characters
Internal or External Character Synchronization
Automatic Sync Insertion
. Single or Double Sync Characters
Baud Rate (lX Mode) - DC to 56K Baud (pPD8251)
- DC to 64K Baud (pPD8251A)
Full Duplex, Double Buffered Transmitter and Receiver
Parity, Overrun and Framing Flags
Fully Compatible with 8080A/8085/pPD780 (Z80™)
All Inputs and Outputs are TTL Compatible
Single +5 Volt Supply, ± 10% (8251A) ± 5% (8251)
Separate Device Receive and Transmit TTL Clocks
28 Pin Plastic DIP Package
N-Channel MOS Technology
PIN NAMES
PIN CONFIGURATION
02
03
00
07-0 0
Oet.
C/fj
Control or Dlt. il to bt Written or R,k1
Reed D,g Command
1m
WR
CS
BUI
18 bits)
Write Oat.
01'
Control Command
RxD
VCC
GNO
°4
J!fXC
0'fR
CLK
AESET
ChipEnabl.
Cloc~ Pul .. (TTLI
A_.
T.C
Transmitter Clock (TTL)
TxO
AxC
AxO
A.AOY
TxAOY
Transmitter O.t.
@i
Oat. Set Re8dy
Data Terminal Reedy
05
ffi
06
OSR
°7
RESET
hl
WR
ClK
~
TxE
c/15
AD
RxROY
TM:
0,
TxO
mSYNOET ("P082511
SYNOET/BD ("PD8251A)
TkROY
Z80 is a registered trademark of 2ilog, Inc.
Rev/5
631
OTA
SYNOET
SYNOET180
ATS
CTS
TxE
VCC
GNO
Receiver Clock (TTL)
Receiver Data
Receiver R• .,V (h. charKter for 8080)
Tr~smitter
R• .,V (ready for chlr. from 808(n
Sync Oetect
Sync Deteetl8reak Detect
".ques. '0 Sond Dot.
Ct.... to Send Dig
Transmitter Empty
+5 Vol. Supplv
Ground
m
",PD8251 18251 A
The IlPD8251 and IlPD8251A Universal Synchronous/Asynchronous Receiver/
Transmitters are designed specifically for 8080 microcomputer systems but work with
most 8-bit processors. Operation of the IlPD8251 and IlPD8251A, like other I/O devices
in the 8080 family, are programmed by system software for maximum flexibility.
FUNCTIONAL
DESCRIPTION
In the receive mode, the IlPD8251 or IlPD8251A converts incoming serial format data
into parallel data a'nd makes certain format checks. In the transmit mode, it formats
parallel data into serial form. The device also supplies or removes characte'rs or bits that
are unique to the communication format in use. By performing conversion and formatting services automatically, the USART appears to the processor as a simple or "transparent" input or output of byte-oriented parallel data.
The pPD8251A is an advanced design of the industry standard 8251 USART. It
operates with a wide range of microprocessors, including the 8080, 8085, and
pPD780 (Z80™). The additional features and enhancements of the pPD8251 A over
the pPD8251 are listed below.
J.LPD8251A FEATURES AND
ENHANCEMENTS
1. The data paths are double-buffered with separate I/O registers for control, status,
Data In and Data Out. This feature simplifies control programming and minimizes processor overhead.
2. The Receiver detects and handles "break" automatically in asynchroJlous
operations, which relieves the processor of this task.
3. The Receiver is prevented from starting when in "break" state by a refined Rx
initialization. This also prevents a disconnected USART from causing unwanted
interrupts.
4. When a transmission is concluded the TxD line will always return to the marking
state unless SBRK is programmed.
5. The Tx Disable command is prevented from halting transmission by the Tx
Enable Logic enhancement, until all data previously written has been transmitted. The same logic also prevents the transmitter from turning off in the middle of a word.
6. Internal Sync Detect is disabled when External Sync Detect is programmed. An
External Sync Detect Status is provided through a flip-flop which clears itself
upon a status read.
7. The possibility of a false sync detect is minimized by:
ensuring that if a double sync character is programmed, the characters be
contiguously detected.
clearing the Rx register to all Logic 1s (VOH) whenever the Enter Hunt command is issued in Sync mode.
8. The RD and WR do not affect the internal operation of the device as long as the
pPD8251A is not selected.
9. The pPD8251A Status can be read at any time, however, the status update will
be inhibited during status read.
10. The IlPD8251 A has enhanced AC and DC characteristics and is free from
extraneous glitches, providinn higher speed and improved operating margins.
11. Baud rate from DC to 64K.
c/o
0
0
1
1
X
X
RD
0
1
WR
CS
0
0
0
0
1
0
1
1
0
1
0
X
X
1
1
0
BASIC OPERATION
IlPD8251/IlPD8251A ~ Data Bus
Data Bus ~ pPD8251/pPD8251A
Status ~ Data Bus
Data Bus ~ Control
Data Bus
~
3-St2te
'TM: Z80 is a registered trademark of Zilog, Inc.
632
,.,PD8251 18251 A
BLOCK DIAGRAM
TxD
TxADY
TxE
SYNDET ("PDB251I
SYNDET/BD ("PDB251 AI
ABSOLUTE MAXIMUM
RATlNGS*
.......... -ooe to +70°C
o
Operating Temperature .... .
Storage Temperature ... .
All Output Voltages . . . . . . .
All Input Voltages ..... .
Supply Voltages .
Ta
=
-65°e to +150 e
-0.5 to +7 Volts
-0.5 to +7 Volts
-0.5 to +7 Volts
25°e
*COMMENT: Stress above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability .
DC CHARACTERISTICS
Ta
= o°c to 70°C; VCC = 5.0V ± 10% for 8251A and ± 5% for 8251; GND = OV.
LIMITS
uPD8251A
PD8251
SYMBOL MIN TYP
PARAMETER
CAPACITANCE
Input Low Voltage
V,L
-0.5
Input High Voltage
V,H
2.0
Output Low Voltage
VOL
Output High Voltage
VOH
Data Bus Leakage
IDL
Input Load Current
',L
Power S.upply Current
ICC
Ta = 25°C; VCC
MAX
MIN
MAX
O.S
0.5
O.S
VCC
2.2 VCC
0.45
0.45
UNIT
TEST CONDITIONS
V
V
V
IJ PD S251 :
2.4
2.4
V
-50
-10
10
10
10
10
lolA
SO
100
mA
IJPDS251 :
'OH· -lOG lolA
IJ P DS251A: 'OH· -400 lolA
VOUT·0.45V
lolA
VOUT
= VCC
At 5.5V
IJPDS251A: All Outputs·
=GND·
45
Logic 1
OV
LIMITS
PARAMETER
'OL·l.7mA
IJPDS251A: 'OL· 2.2 mA
SYMBOL
MIN
TV'
MAX
UNIT
TEST
CONDITIONS
Input Capacitance
C'N
10
pF
le·l MHz
1/0 Capacitance
C,IO
20
pF
Unmeasured
pins returned
toGNO
633
"PD8251 18251 A
AC CHARACTERISTICS
T•• O°C to 70°C; VCC' 5.0V ± 10% for 8251A; GND' OV; VCC· 5.0V t 5% for 8251
I
I
PARAMETER
SYMBOL
J
LIMITS
I
jlPD8251
I
MIN
I
MAX
jlPD8215A
MIN
I
MAX
I
TEST
CONDITIONS
I UNIT
READ
Address S'able before READ. {~, ml
'AR
Address Hold T,me for READ, (CS, COl
'RA
50
50
50
ReAlS' Pulse Width
'RR
Data Delay from READ
'RO
350
250
Fi"EA15 10 Data
'OF
200
100
Floating
430
250
25
"P08251· CL - 100 pF
"P08251A· CL' 150 pF
ns
CL -100pF
CL=15pF
"P08251
10
WRITE
Address Stable before WRITE
'AW
20
Address Hold Time for WRITE
'WA
20
50
'WW
400
250
'OW
200
150
'WO
40
30
'RV
6
wl'i"ln Pulse W,d,h
Data Set-Up Time for WRITE
Data Hold Time for'WJ!fTT'E"
Recovery Time Between WRITES
CV
50
'CY
OTHER TIMING
Clock Period
Q)
0.420
'CY
Clock Pulse Width High
'¢W
Clock Pulse Width Low
1.35
220
0.7,CY
1.35
140
tCy·90
ns
gO
'W
Clock Rise and Fall Time
0.32
50
'R,'F
20
TxO Delay from Falling Edge of TxC
'OTx
Rx Data Set-Up Time to Sampling Pulse
tSRx
lIS
Rx Data Hold Time to Sampling Pulse
tHRx
jlS
Transmitter Input Clock Frequency
fTx
1 X Baud Rate
16X Baud R.,e
64X Baud Rate
DC
DC
DC
I ransln.tter Input Clock PUlse Wldtn
1X Baud Rate
16X and 64X Baud Rate
'TPW
Transmitter Input Clock Pulse Delay
lX Baud Rate
'TPO
56
64
310
615
520
520
Receiver Input Clock Frequency
12
12
'cv
15
3
15
'cv
J
'Cy
fRx
IX Baud Ra,e
16X Baud Ra,e
DC
DC
64X Baud Rate
DC;
Receiver Input Clock Pulse Width
lX Baud Rate
16X and 64X Baud Rate
'RPW
Receiver Input Clock Pulse Delay
lX Baud Rate
16X and 64X Baud Rate
'RPO
TxADY Delay from Center of Data Bit
56
64
310
615
520
5:lu
12
1
'cv
15
15
3
'cv
J
'CV
'CY
'Tx
16
'RX
20
24
Internal SYNDET Delay from Center
of Data Bit
'IS
2S
24
EXternal SYNDET Set-Up Time before
'ES
Fall,ng Edge of RxC
TxEMPTY Delay from Center of Data Bit
.!!.2m '3..l.!.iDg Edge of
WRITE {TxE, OTR, RTSI
Control '0 READ Se'·Up T,me (OSR, CTSI
-
+10~---4~---+-----b~--1
«
..J
LIJ
o
~
O~---+----~---;----,
::::l
a.
~
::::l
24K (8251)
6K (8251A)
o
-10~--~~---+-----+----'
<3
-20~-L~
-100
Figure 1.
____
-50
~
____
o
~
__
+50
~
+100
6 CAPACITANCE (pF)
Typical t::. Output
Delay Versus t::. Capacitance (pF)
TEST LOAD CIRCUIT
634
",PD8251 18251 A
TIMING WAVEFORMS
CLOCK
SYSTEM CLOCK INPUT
TPW
~.
:11XMODEI
.
tTPD,.---..j
~.I
.._
TxC 116x MODEl
===>r
-
Tx DATA
!--tDTX
'.
tDTX
I--
~I:-----------x:::::
TRANSMITTER CLOCK AND DATA
Rx DATA
RxC
fix MODEl
~116MODEI
tNT SAMPLING
PULSE
RECEIVER CLOCK AND DATA
WRITE DATA CYCLE (PROCESSOR -+ USART)
READ DATA CYCLE (PROCESSOR + USART)
635
flPD8251 18251 A
0)
5TR.RTS--------------------------------~~---------
------------------------~~~--------
WR _________________.~r_--tw-c-~---------~
DATA IN (O.B.)
----------~tl==ljf-----------
c/O _ _ _ _ _ _ _•...J
cs-------__.
WRITE CONTROL OR OUTPUT PORT CYCLE
(PROCESSOR -+ USART)
o
i5SR. C'i'S - - - -..... ,..--------------------------__
RD --------~-DATAOUT ___________________-1~t=:::::::::tj--------(O.B.)
C/t5 _____________ .__J
~
---------_1
READ CONTROL OR INPUT PORT CYCLE
(PROCESSOR -+- USART)
<2) TwC Includu the ,..pon .. timing 0'. control bytt.
NOTES:
o
TCR Includfll the effect of CTI on ,he T.ENBl circuitry
Tx EMPTY - - - - _
Tx READY
(STATUS BIT!
~----------~~------~
. Tx READY
(PIN)
cio
Wr SBRK
~--~---~--~
Tx DATA
-------~
,.,..,..,.".,rvv-AlLlnmru' D(Xlmrrt~-------:\L:XD[i,,__L
DATA CHAR 1
DATACHAR2
DATACHAR3
O .... NM .. "'HD
DATA CHAR 4
I-
iii
EXAMPLE FORMAT' 7 BIT CHARACTER WITH PARITY AND 2 STOP BITS.
TRANSMITTER CONTROL AND FLAG TIMING
(ASYNC MODE)
636
~
«
o
TIMING WAVEFORMS
(CONT.)
IlPD8251 18251 A
TIMING WAVEFORMS
(CaNT.)
BREAKDETECT~(~-P-D8~2~5-1A~I------______--------------------------~
OVERRUN ERROR
(STATUS BITI--------------_--::t----:t":::'R-X":::'R~DY-:---...;.--4
r--n~----¥
C/5;!~;=========~~==4=====jJ~~===;~~~~
Rx ROY ---------------~
WTl Wr RXEn,--1-----------t-t------+-------t-~ F"------""I-\
~---------------~r_--_t------~ r-~------_t--~---Rx DATA - - - - - - - - - " ' \
'DATA CHAR 1 DATA CHAR 2 DATA CHAR 3
EXAMPLE FORMAT = 7 81T CHARACTER WITH PARITY AND 2 STOP BITS,
RECEIVER CONTROL AND FLAG TIMING
(ASYNC MODE)
rn
h EMPTY
"---1-_
T'---------f
T'READV---+----+,
ISTATUS BIT!
Tx READY
IPINI'
~~~====~~'~'P~A~Rto~~AxR~~pXA~Ral~PA~Rpj~PA~Rxn~PArR~T~~S~PA~C:,N~G~I~5a~~ID~~ETC
DATA
DATA
CHAR 1 CHAR 2
SYNC SYNC
CHAR I CHAR 2
DATA
DATA
LSTATE
CHAR 3 CHAR 4WKING
STATE
"MARK'iiiiG
STATE
DATA
CHAR 5
SYNC
CHAR
EXAMPLE FORMAT· 5 BIT CHARACTER WITH PARITY AND 2 SYNC CHARACTERS
TRANSMITTER CONTROL AND FLAG TIMING
(SYNC MODE)
SYNDET
SYNDE T IS.BI
OVERRUN
ERROR IS,BI
----------------4'
--------------1f------+-t-----.I
+-__"-1
R, RDY IPINI _ _ _ _ _ _ _ _ _ _ _ _ _
CD
Wr EH'
R,E~n'---------~-~t~f-4+r---~__. ~I-~~
AD --+----------r-~-+'\ I r"'\II;r---h.1
EXIT HUNT MODE
I
SET SYNDET (STATUS BIT!
RECEIVER CONTROL AND FLAG TIMING
(SYNC MODE)
Notes: (j) Internal sync; 2'sync characters, 5 bits, with parity.
C2> External sync, 5 bits, with parity.
637
SET SYNDET ISTATUS BIT!
"PD8251 18251 A
PIN IDENTIFICATION
PIN
NO.
SYMBOL
1,2,
27,28
5-8
D7 -DO
FUNCTION
NAME
An 8-bit, 3-state bi-directional buffer used to
interface the USART to the processor data
bus. Data is transmitted or received by the
buffer in response to input/output or Read/
Write instructions from the processor. The
Data Bus Buffer also transfers Control words,
Command words, and Status.
Data Bus Buffer
26
VCC
V CC Supply Voltage
+5 volt supply
4
GND
Ground
Ground
This logic block accepts inputs from the processor Control Bus and generates control signals
for overall USART operation. The Mode
Instruction and Command Instruction registers
that store the control formats for device functional definition are located in the Read/
Write Control logic.
Read/Write Control logic
21
RESET
Reset
A "one" on this input forces the USART into the
"Idle" mode where it will remain until reinitialized with a new set of control words. Minimum
RESET pulse width is 6 tCY.
20
ClK
Clock Pulse
The ClK input provides for internal device timing and is usually connected to the Phase 2 (TTL)
output of the IJPB8224 Clock Generator.
External inputs and outputs are not referenced
to ClK, but the ClK freq\,Jency must be at
least 30 times the Receiver or Transmitter
docks in the synchronous mode and 4.5
times for the asynchronous mode.
10
WR
Write Data
A "zero" on this input instructs the USART
to accept the data or control word which
the processor is writing out on the
data bus.
13
RD
Read Data
A "zero" on this input instructs the USART
to place the data or status information
onto the Data Bus for the processor to
read.
12
C/D
Control/Data
11
CS
Chip Select
--
--
Modem Control
~ Con!.!:2J/Data input, in conjunction with the
WR and RD inputs, informs the USART to
accept or provide either a data character,
control word or status information via the
Data Bus. 0 = Data; 1 = Control.
A "zero" on this input enables the USART to
read from or write to the processor.
The IJPD8251 and IJPD8251 A have a set of
control inputs and outputs which may be used to
simplify the interface to a Modem.
22
DSR
Data Set Ready
The Data Set Ready input can be tested by the
processor via Status information. The 5SR input
is normally used to test Modem Data Set Ready
condition.
24
DTR
Data Terminal Ready
The Data Terminal Ready output can be controlled via the Command word. The DTR output
is normally used to drive Modem Data Terminal
Ready or Rate Select lines.
23
RTS
Request to Send
The Request to Send output can be controlled
via the Command word. The RTS output is
normally used to drive the Modem Request to
Send line.
17
CTS
Clear to Send
A "zero" on the Clear to Send input enables the
USART to transmit serial data if the TxEN bit in
the Command Instruction register is enabled
(onel.
638
",PD8251 /8251 A
TRANSMIT BUFFER
The Transmit Buffer receives parallel data from the Data Bus Buffer via the internal
data bus, converts parallel to serial data, inserts,the necessary characters or bits needed
for the programmed communication format and outputs composite serial data on the
TxD pin.
PIN IDENTIFICATION
• PIN
(CONT.)
NO.
SYMBOL
FUNCTION
NAME
The Transmit Control logic accepts and outputs
all external and internal signals necessary for
serial data transmission.
Transmit Control logic
15
TxRDY
Transmitter Ready
Transmitter Read'y' signals the processor that the
transmitter is ready to accept a data character,
TxRDY can be used as an interrupt or may be
tested through the Status information for polled
operation. Loading a character from the processor
automatically resets TxRDY, on the leading edge,
18
TxE
Transmitter Empty
The Transmitter Empty output signals the
processor that the USART has no further char·
acters to transmit. TxE is automatically reset
upon receiving a data character from the pro·
cessor. In half·duplex, TxE can be used to signal
end of a transmission and request the processor
to "turn the line around," The TxEn bit in the
command instruction does not effect TxE,
In the Synchronous mode, a "one" on this out·
put indicates that a Sync character or charac·
ters are about to be automatically transmitted
as "filiers" because the next data character has
not been loaded.
9
TxC
Transmitter Clock
The Transmitter Clock controls the serial charac
tertransm iss ion rate. In the Asynchronous
mode, the TxC frequency is a multiple of the
actual Baud Rate. Two bits of the Mode Instruc·
tion select the multiple to be 1 x, 16x, or 64x
the Baud Rate. In the Synchronous mode. the
TxC frequency is automatically selected to
equal the actual !:laud Rate.
Note that for both Synchronous and Asynchro·
nous modes, serial data is shifted out of the
USART by the falling edge of TxC.
19
/lPD8251 AN D /lPD8251 A
INTERFACE TO 8080
STANDARD SYSTEM BUS
TxD
Transmitter Data
)
The Transmit Control Logic outputs the
composite serial data stream on this pin.
\
ADDRESS BUS
AO
~
\
CONTROL BUS
I/O R
~
ilOW
RESET
,)2
(TTL)
\
DATA BUS
A
8
V
(
C/D
-
CS
()
D7 - DO
-RD
pPD8251/8251A
639
-(
WR
RESET
ClK
"PD8251 18251 A
The Receive Buffer accepts serial data input at the RxD pin and converts the data
from serial to parallel format. Bits or characters required for the specific communication technique in use are checked and then an eight-bit "assembled" character is
readied for the processor. For communication techniques which require less than
eight bits, the IlPD8251 and IlPD8251 A set the extra bits to "zero."
PIN IDENTIFICATION
PIN
SYMBOL
NO.
FUNCTION
NAME
(CONT.)
This block manages all activities related to
incoming data.
Receiver Control Logic
14
RxRDY
Receiver Ready
The Receiver Ready output indicates that the
Receiver Buffer is ready with an "assembled"
character for input to the processor. For Polled
operation, the processor can check RxRDY
using a Status Read or RxRDY can be connected to the processor interrupt structure.
Note that reading the character to the processor automatically resets RxRDY.
25
RxC
Receiver Clock
The Receiver Clock determines the rate at which
the incoming charac~ received. In the Asynchronous mode, the RxC frequency may be 1.16
or 64 times the actual Baud Rate but in the Synchronous mode the RXC frequency must equal
the Baud Rate. Two bits in the mode instruction
select Asynchronous at 1 x, 16x or 64x or Synchronous operation at 1 x the Baud Rate.
Unlike TxC, data is sampled by the IJPD8251 and
IJPD8251 A on the rising edge of RxC.
ntrol words.
USART PROG RAMMING
The USART must be loaded with a group of two to four control words provided by
the processor before data reception and transmission can begin. A RESET (internal or
external) must immediately proceed the control words which are used to program the
complete operational description of the cOrTlmunications interface. If an ~xternal
RESET is not available, three successive 00 Hex or two successive 80 Hex CO,mmand
instructions (C/i) =1) followed by a, software reset commC\nd instruction (40 Hex)
can be used to initialize th~ pPD8251 and pPD8251A.
There are two control word formats:
1. Mode Instruction
2. Command Instruction
MOD E I NST R UCTI ON
COMMAND INSTRUCTION
This control word specifies the general characteristics of the interface regarding the
Synchronous or Asynchronous mode, BAUD rate factor, character length, parity, and
number of stop bits. Once the Mode I nstruction has been received, SYNC characters
or Command Instructions may be inserted depending on the Mode Instruction content.
a
This control word will be interpreted as SYNC charac,ter definition if immediately
preceded by a Mode Instructio,n, which specified a Synchronous format. After the
SYNC character(s) ,are specified or after an Asynchronous Mode Instruction, all subsequent contro.! words will be interpreted as an update to the Command Instruction.
Command Instruction updates may occur at any time during the data block. To
modify the Mode Instruction, a bit may be set in the Command Instruction which
causes an internal Reset which allows a new Mode Instruction to be accepted.
641
I'PD8251 18251 A
ctiS -
MODE INSTRUCTION
c/o -
SYNC CHARACTER 1
ctiS
SYNC CHARACTER 2
citS
COMMAND INSTRUCTION
cliS - 0
DATA
C/O ~ 1
COMMAND INSTRUCTION
c/iS
C
NOTE
CD
/is
c
0
~ 1
f
TYPICAL DATA BLOCK
SYNC MODE
}
ONLY
CD
...
DATA
r-----------------,
COMMAND INSTRUCTION
The second SYNC character is skipped if MODE instruction has programmed the /JPD8251 and /JPD8251A to single character Internal
SYNC Mode. Both SYNC characters are skipped if MODE
instruction has programmed the /JPD8251 and /JPD8251 A to ASYNC
mode.
The J.lPD8251 and J.lPD8251A can operate in either Asynchronous or Synchronous
communication modes. Understanding how the Mode Instruction controls the
functional operation of the USART is easiest when the device is considered to be two
separate components (one asynchronous and the other synchronous) which share the
same support circuits and package. Although the format definition can be changed at
will or "on the fly," the two modes will be explained separately for clarity.
MODE INSTRUCTION
DEFINITION
When a data character is wri tten into the J.lPD8251 and I1PD8251 A, the USA RT
automatically adds a START bit (low level or "space") and the number of STOP bits
(high level or "mark") specified by the Mode Instruction. If Parity has been enabled,
an odd or even Parity bit is inserted jus~~ore the STOP bit(s), as specified by the
Mode Instruction. Then, depending on CTS and TxEN,the character may be transmitted as a serial data stream at the TxD output. Data is shifted out by the falling
edge of TxCat -'--;ZC, TxC/16 or TxC/64, as defined by the Mode Instruction.
ASYNCHRONOUS
TRANSM ISSION
If no data characters have been loaded into the J.lPD8251 and J.lPD8251A, or if all
available characters have been transmitted, the TxD output remains "high" (marking)
in preparation for sending the START bit of the next character provided by the
processor. TxD may be forced to send a BREAK (continuously low) by setting the correct bit in the Command Instruction.
The RxD input line is normally held "high" (marking) by the transmitting device.
A falling edge at RxD signals the possible beginning of a START bit and a new
character. The START bit is checked by testing for a "low" at its nominal center
as specified by the B,LWD RATE. If a "low" is detected again, it is considered valid,
and the bit assembling CDunter starts counting. The bit counter locates the approximate center of the data, parity (if specified), and STOP bits. The parity error flag (PEl
is set, if a parity error occurs. Input bits are sampled at the RxD pin with the rising
edge of RxC. If a high is not detected for the STOP uit, which normally signals the end
of an input character, a framing error (FE) will be set. After a valid STOP bit, the input
character is loaded into the parallel Data Bus Buffer of the J.lPD8251 and J.lPD8251A
and the RxRDY signal is raised to indicate to the processor that a character is ready to
be fetched. If the processor has failed to fetch the previous character, the new character replaces the old and the overrun flag (OE) is set. All the error flags can be reset
by setting a bit in the Command Instruction. Error flag conditions will not stop subsequent USART operation.
642
ASYf\JCH RONOUS
RECEIVE
"PD8251/8251A
I
s21
s l l EP IpENI L21'LI 1 B21 Bll:
'~L
BAUD RATE FACTOR
0
1
0
'0
0
1
1
. SYNC
MODE
(1.X)
(16X)
(64X)
1
CI;!ARACTER LENGTH
0
1
"0
0
0
1
1
5
6
BITS
7
BITS
8
BITS
·BITS
,
PARITY ENABLE
1 ENABLE
0
,.
1
DISABLE
EVEN PARITY GENERATION/CHE CK
0 ODD
1 .EVEf\!
NUMBER OF
TxD
BITS
1
0
0
0
1
1
INVALID
1
81T
11,
BITS
2
BITS
..
,
STQ~
0
1
..
ST,&;t
BITS
L
MARKING
TRANSMITTER OUTPUT
DO
RxD
,--_S_TB_~_~
01
02
t t ~
...
T,...'_.
D_A_~~;
L.I_ _
-
STOn
BITS
L
Br'_T_S_......,J'--_ _ _...J
RECEIVER INPUT
PROCESSOR BYTE (5-8 BITS/CHAR)
DATA
C~~RACTEn.
ASSEMBLED SERIAL DATA OUTPYT (TxD)
'--S_T_:_I~_T~
D_A_TA~~HARACTER
STOn.
BITW
____
TRANSMISSI'ON FORMAT
SERIAL DATA ',NPUT (RxD)
'--____~_________~ ~------~------~---~_{i~
PROCESSOR BYTE (5-8 BITS/CHAR)
Q)
DATA CH;;ACTER
RECEIVE FORMAT
Notes:~,
2
3
.
Generated bv !,PD8251 /8251 A
Does not appear on the Data Bus.
II character fength is defined as 5, 6, or 7 bits, the
unused bi ts, are set to "zero,"
643
~PD8251/8251 A
SYNCHRONOUS
TRANSMISSION
As in Asynchronous transmission, the TxD output remains "high" (marking)
until the J,lPD8251 and J,lPD8251 A receive the first character (usually a SYNC
character) from the processor. After a Command Instruction has set TxEN and
after tlear to Send (eTs') goes low, the first character is serially transmitted.
Data is shifted out on the falling edge of TxC and the same rate as TxC.
Once transmission has started, Synchronous Mode format requires that the serial data
stream at TxD continue at the TxC rate or SYNC will be lost. If a data character is
not provided by the processor before the IJPD8251 and J,lPD8251A Transmit
8uffer becomes empty, the SYNC character(s) loaded directly following the Mode
Instruction will be automatically inserted in the TxD data stream. The SYNC
character(s) are inserted to fill the line and maintain synchronization until new data
characters are available for transmission. If the J,lPD8251 and J,lPD8251 A become
empty, and must send the SYNC character(s). the TxEMPTY output is raised to signal
the processor that the Transmitter Buf'fer is empty and SYNC characters are being
transmitted. TxEMPTY is automatically reset by the next character from the processor.
In Synchronous Receive, character synchronization can be either external or internal.
If the internal SYNC mode has been selected, and the Enter HUNT (EH) bit
has been set by a Command Instruction, the receiver goes into the HUNT mode.
SYNCHRONOUS
RECEIVE
Incoming data on the RxD input is sampled on the rising edge of RxC, and the
Receive Buffer is compared with the first SYNC character after each bit has been
loaded until a match is found. If two SYNC characters have been programmed, the
next received character is also compared. When the SYNC character(s) programmed
have been detected, the J,lPD8251 and fJPD8251A leave the HUNT mode and are in character synchronization. At this time, the SYNDET (output) ~ set high. SYNDET is
automatically reset by a STATUS READ.
If external SYNC has been specified in the Mode Instruction, a "one" applied
to the SYNDET (input) for at least one RxC cycle will synchronize the USART.
Parity and Overrun Errors are treated the same in the Synchronous as in the
Asynchronous Mode. If not in HUNT, parity will continue to be checked even
if the receiver is not enabled. Framing errors do not apply in the Synchronous
format.
The processor may command the receiver to enter the HUNT mo~e with a Command
Instruction which sets Enter HUNT (EH) if synchronization is lost.
07
06
05
04
03
l
scs}sDl EP lPENl L?
I
02
0,
Do
I I II
I
L,
0
CI;lARACTER LENGTH
0
1
0
0
0
1
1
5
6
BITS
7
BITS
8
BITS
l
MODE INSTRUCTION
FORMAT
SYNCHRONOUS MODE
0
.
BITS
PARITY ENABLE
11
ENABLEI
10 DISABLE I
EVEN PARITY GENERATION/CHE CK
1 EVEN
o
.
1
000
EXTERNAL SYNC DETECT
SYNOET IS AN INPUT
SYNOET IS AN OUTPUT
1
0
SINGLE CHARACTER SYNC
SINGLE SYNC CHARACTER
DOUBLE SYNC CHARACTER
644
IlPD8251 18251 A
TRANSMIT/RECEIVE
FORMAT
SYNCH RONOUS MODE
PROCESSOR BYTES 15-8 BITS'CHARI
OAT A C:\RACTERS
ASSEl\lAL ED SERIAL DATA OUTPUT IT,D}
SYNC
CHAR 1
SYNC
CHAR :,
OATACH~R;~A_C_TE_R_S
______
~
TRANSMIT FORMAT
SERIAL DATA INPUT (R.DI
DA T A CHAR:...
A_C_T_ER_S_ _ _...J
PROCESSOR BYTES 15-8 BITS CHAR!
CD
UA'AC:~
RECEIVE FORMAT
Note
COMMAND INSTRUCTION
FORMAT
STATUS READ FORMAT
PA R I TV ERR 0 R
OVERRUN ERROR
, FRAMING ERROR
tjpo---
OUTPUT TO PERIPHERAL
BASIC OUTPUT (WRITE)
MODE 1
WR --------'"\.
6BF
--------1---1-""""11
INTR - - - - - -__
ACR------------~-~-~I
OUTPUT TO PERIPHERAL
STB FROM PERIPHERAL
IBF
-------'1
tSIT t-~----,J
INTR _ _ _ _ _ _ _ _ _ _
~~
R5-------------~-4-~1
~-~----J
INPUT FROM
PERIPHERAL
661
IiPD8255A-5
TIMING WAVEFORMS
(CaNT.)
MODE 2
INTR
ACK FROM PERIPHERAL
STB FROM PERIPHERAL
IBF --------~
PERIPHERAL
BUS
tRIB
R5----------~----------~~~---~
DATA FROM
PERIPHERAL TO ~PD8255A-5
DATA FROM
TO PERIPHERAL
~PDB255A-5
READ DATA FROM
TO ~PD8080A
~PD8255A-5
Note:
WR
R5
CD
Any sequence where
occurs before ACK and STB occurs before
(lNTR = IBF· MASK· STB· AD + OBF· MASK· ACt<. WR)
@
When the ~PD8255A-5 is set to Mode 1 or 2, OBF is reset to be high (logic 1).
is permissible.
The I'PD8255A-5 can be operated in modes (0, 1 or 2) which are selected by appropriate
control words and are detailed below.
MODES
•
MODEQ
MODE 0 provides for basic Input and Output operations through each of the ports
A. B. and C. Output data is latched and input data follows the peripheral. No "handshaking" strobes are needed.
16 different configurations in MODE 0
Two S-bit ports and two 4-bit ports
I nputs are not latched
Outputs are latched
MODE 1 provides for Strobed Input and Output operations with data transferred
through Port A or B and handshaking through Port C.
MODEl
Two I/O Groups (I and II)
Both groups contain an S-bit data port and a 4-bit control/data port
Both S-bit data ports can be either Latched Input or Latched Output
MODE 2 provides for Strobed bidirectional operation using PAO-7 as the bidirectional latched data bus. PC3-7 is used for interrupts and "handshaking" bus flow
controls similar to Mode 1. Note that PB(). 7 and PCO-2 may be defined as Mode 0
or 1. input or output in conjunction with Port A in Mode 2_
An S-bit latched bidirectional bus port (PAO-7) and a 5-bit control port (PC3-7)
Both inputs and outputs are latched
An additional B-bit input or output port with a 3-bit control port
662
MODE 2
IlPD8255A-5
BASIC OPERATION
INPUT OPERATION (READ)
Al I
o I
o I
1 I
A!Ll
0
1
0
Al
0
0
1
1
AO
0
1
0
1
Al
AO
X
X
X
X
NOTES:
FORMATS
RD I WRI
1 I
o I 1 I
o I 1~
I o I
I
I
cs
0
I
I
PORT A_DATA BUS
PORfB_DATABUS
I PORT C _ _ DATA BUS
o I
0
OUTPUT OPERATION (WRITE)
RD
WR I CS
DATA BUS ___ PORT A
1
o I 0
DATA BUS __ PORT B
1
o~ 0
DATA BUS __ PORT C
1
0
0
DATA BUS __ CONTROL
1
o I 0
DISABLE FUNCTION
RD
WR
CS I
DATA BUS ___
X
X
1
HIGH Z STATE
! DATA BUS ___
1
1
0
I HIGH Z STATE
I
G)
0)
X means "DO NOT CARE."
All conditions not listed are illegal and should
be avoided.
10, I0.1 0,\ 0,\ 0, I0, I0, I00 I
10, ID. 0, 10,1 0, I0, I0, 100 I
L,J
~
/
OAOUPU
\
PORTCllOWEAl
I -INPUT
~ OUTPUT
o
PORTS
1 -INPUT
a-OUTPUT
MODE SELECTION
O'Mooeo
I-MODE I
~~
OON"r
1 -INPUT
O· OUTPUT
CARE
l ' INPUT
O-OUTPUT
~
I
MODE SELECTION
01 -MODE 1
1)( -MODE2
663
J"
S 61
1 0
1 0
0
000011'
J
~oeSETFLAG
1 -ACTIVE
." ..,,"
012
0'
1 80
II
0101' 1'1 0101' I' Is"
oo-,.,OOEO
MODE DEFINITION
I
BITSETIAESET.
1 SET
O-RESET
BIT/RESET
I
1
BIT SET/RESET FLAG
a-A.CTlVE
82
J
IiPD8255A-5
I
I
H:==K==:iI
,;nT, J..----.: L1~
HJ.~=:fo
.
,
IIp UUIU
,A
lr Qc~_U
U_
U_U_J--J,..Jer U U U.F/
G
M 00 _160
PACKAGE OUTLINE
f.lPOB255AC/O-5
\4-
Plastic
ITEM
MILLIMETERS
A
51.5 MAX
B
C
0
E
F
INCHES
2.028 MAX
1.62
0.064
2.54±0.1
0.10 ± 0.004
0.5 ± 0.1
0.019 ± .0.004
48.26
1.2 MIN
1.9
0.047 MIN
G
2.54 MIN
0.10MIN
H
I
.0.5 MIN
0 •.019 MIN
5.22 MAX
.0.206 MAX
5.72 MAX
.0.225 MAX
J
K
15.24
L
13.2
M
.0.6.00
.0.52.0
0.25 + 0.1
0..05
.0.010 + 0.004
.0..002
G
t---------E-------....-l
Ceramic
ITEM
MILLIMETERS
INCHES
A
B
C
51.5 MAX
1.62 MAX
2.54±0.1
0.5 ± 0.1
48.26 ± 0.1
1.02 MIN
3.2 MIN
1.0MIN
3.5 MAX
4.5 MAX
15.24 TYP
14.93 TYP
0.25 ± 0.05
2.03 MAX
0.06 MAX
0.1 ± 0.004
0.02 ± 0.004
1.9 ± 0.004
0.04 MIN
0.13MIN
0.04 MIN
0.14 MAX
0.18 MAX
0.6TYP
0.59 TYP
0.01 ± 0.0019
0
E
F
G
H
I
J
K
L
M
825'5DS-R EV3-1-B2-CAT
664
~EC
NEe Electronics U.S.A. Inc..
IlPD8257-5
Microcomputer Division
PROGRAMMABLE DMA CONTROLLER
DESCR IPTION
The J.LPD8257-5 is a programmable four-channel Direct Memory Access (DMA) controller. It is designed to simplify high speed transfers between peripheral devices and
memories. Upon a peripheral request, the J.LPD8257-5 generates a sequential memory
address, thus allowing the peripheral to read or write data directly to or from memory.
Peripheral requests are prioritized within the J.LPD8257-5 so that the system bus may
be acquired by the generation of a single HOLD command to the 8080A. DMA cycle
counts are maintained for each of the four channels, and a control signal notifies the
peripheral when the preprogrammed member of DMA cycles has occurred. Output control signals are also provided which allow simplified sectored data transfers and expansion to other J.LPD8257-5 devices for systems requiring more than four DMA channels.
FEATU RES • NEC Now Supplies J.LPD8257-5 to J.LPD8257 Requirements
•
•
.•
•
•
•
•
•
•
Four Channel DMA Controller
Priority DMA Request Logic
Channel Inhibit Logic
Terminal Count and Modulo 128 Outputs
Automatic Load Mcide
Single TTL Clock
Single +5V Supply ±10%
Expandable
40· Pin Plastic Dual-In-Line Package
PIN CONFIGURATION
MEMR
MEMW
MARK
READY
HlOA
AOOSTB
AEN
HRO
cs
J.LPD
8257-5
ClK
RESET
.OACK 2
OACK3
OR03
OR02
OR01
OROo
GNO
A7
A6
AS
A4
TC
A3
A2
A,
AO
VCC
Do
0,
O2
03
~
OACKo
OACK,
Os
06
07
Rev/4
665
PIN NAMES
D7- DO
Data Bus
ArAo
I/OR
Address Bus
IIOW
I/O Read
1/0 Write
MEMR
Memorv~
MEMW
Memorv Write
ClK
Clock Input
RESET
Reset Input
READY
Readv
HRQ
Hold Request (to BOBOA)
HlDA
Hold Acknowledge (from BOBOA)
AEN
Address Enable
ADSTB
Address Strobe
TC
Terminal Count
MARK
Modulo 128 Mark
DRQa-DR_Clo
DMA Request Input
DACK3-DACKO
DMA Acknowledge Out
CS
Chip Select
VCC
GND
+5 Volts
Ground
IlPD8257-5
BLOCK DIAGRAM
o
Operating Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. oOe to +70 e
o
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°e to +150 e
Voltage on Any Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to +7 Volts (j)
Power Dissipation
1 Watt
ABSOLUTE MAXIMUM
RATINGS*
Note: (j) With Respect to Ground
Ta
=
25°e
*COMMENT: Stress above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
Ta
= oOe to +70o e; Vee'" +5V ±10% GND'" OV:
PARAMETER
SYMBOL
Input Low Voltage
V IL
-0.5
Input High Voltage
V IH
2.0
Output Low Voltage
VOL
Output High Voltage'
V OH
DC CHARACTERISTICS
LIMITS
MIN.
TYP.
MAX.
O.S
UNIT
TEST CONDITIONS
Volts
Vee + 0.5 Volts
0.45
2.4
Vee
Volts
IO'L = 1.7 mA
Volts
IOH '" ~ 150p.A for AB,
DB andAEN
IOH - -so p.A for others
HRQ Output High Voltage
V HH
3.3
Vee
Volts
IOH "'-SOp.A
Vee Current Drain
ICC
120
mA
Input Leakage
IlL
10
JJA
V IN = Vee
Output Leakage During Float
IOFL
10
JJA
vOUiD
Note:
CD Vec > V OUT > GND + 0.45V
Ta = 25°C; VCC = GND = OV
CAPACITANCE
LIMITS
SYMBOL
Input Capacitance
C IN
10
pF
fc = 1 MHz
CI/O
20
pF
Unmeasured pins
returned to GND
I/O Capacitance
MIN.
TYP.
MAX.
UNIT
TEST CONDITIONS
PARAMETER
666
AC CHARACTE R ISTICS
PERIPHERAL (SLAVE) MODE
",PD8257-5
BUS PARAMETERS
CD
Ta -0·Ct070·C;VCC=5V±10%;GND=OV
I
LIMITS
SYMBOL
PARAMETER
I
1
jjPD8257·5
MIN
TYP
UNIT
TEST
CONDITIONS
MAX
READ
Adr or
CS)
Setup to
Rd)
TAR
Adr or CSI Hold from Rd!
TRA
D8t8 Access from Ad!
TRnE
170
DB-Float Delay from Rdl
TROF
100
CL
CL
20
Rd Width
=
=
100 pF
15 pF
250
TRW
WRITE
Adr Setup to ViTr'l
TAW
Adr Hold from Wrt
TWA
Data Setup to Wr 1
Tnw
Oat. Hold from Wr t
Twn
WrWidth
TWWS
20
200
200
OTHER TIMING
Reset Pulse Width
TRSTW
300
Power Supply! (VCC) Setup to Reset)
TRSTD
500
Signal Rise Time
20
Signal Fall Time
20
Reset to First IOWR
Note:
TIMING WAVEFORMS
PERIPHERAL (SLAVE) MODE
-~-T
~
TSTL_
~
AOOSTB_
~
T~CL_
r:. ...
~
....
M EMWA/iioWR ___
---
~
TRS~ ~
r
READY ___
f
! - - TRWM
..______
--!
7L
.2
,.-TOCT .
TOCl
17
TRH
1(
...
I--T ASC
-0
~-~
I--TWWME
f
~---- HLDA
I-
AEN
ADDo-7
~--- ILOWERADRI
-------<::::::>-- ----- ----------
DATAo_7
(UPPER ADRI
\
I
.. -- .. ~).-
-
.
/
\
Ir--TOBC
7
----~~-
"
i~
\..:H-.
I--- TAHR
1-------I---- TAHW
TWWM
f
\
--------
ADRSTB
----- DACKo_3
\.
-I
'"-1
TAFC
-------\
f
f
~
TRS--oo\
X
I---
1--I--T RS
----
MEMRD/iiORD
--- MeMWR/l7OWR
---
READY
~~~~~~::~:=~T:AK~
~l:::~
~
;----:\ ________~~--------~r===\c:::~----------------------~/-------------\~-------TC/MARK
ts
-
T AK TC/MARK __ _
HRO
-""\
TASS
I'" ~TOCT
_ _ _ _ TFAc-olf-IEMROIl/O RO ___
"'
. t------'""""
------4)-~It---------
-I--~
OROo_3
..z.
~TAEA
---.. .~~
... ~;~~----I"'.. ~~
~
''''[h"1
TAK
TAFAB~
-0
T AH ...
[-TSTT
l- I-
I...
i--ASM
---------
_T
AEL
_.~f
).
II-
-I I-- IHS
T
CLOCK
lOS
f
"
I - - THS
TAET
-0
OATAo.7
TFAOB-O
(UPPER AORI ____
OACKO·3
-=--I'II.
.. '---_./&.
I-
TAEL_
l(
lI-- ~
TOH
~
T
HLOA
r-
TOO_
~~~
--_.
-~
.,.
-4
-I
NOT READY SE~UENCE ~
S4~~_}.\J\_f-\.:~~I~
~~i T8~ TOS._~
CLOCK
CD
CD
CO
I
I~CONTROl OVERRIDE S~OUENCE
'"
____
1:
'tI
C
01)
N
CIt
a
-:-a
CIt
flPD8257-5
The J1PD8257-5 is a programmable, Direct Memory Address (DMA) device. When used
with an 8212 I/O port device, it provides a complete four-channel DMA controller
for use in 8080A/8085A based systems. Once initialized by an 8080A/8085A CPU,
the J1PD8257 -5 will block transfer up to 16,364 bytes of data between memory and a
peripheral device without any attention from the CPU, and it will do this on all 4-DMA
channels. After receiving a DMA transfer request from a peripheral, the following
sequence of events occurs within the JlPD8257 -5.
•
It acquires control of the system bus (placing 8080A/8085A in hold mode).
•
Resolves priority conflicts if multiple DMA requests are made.
• A l6-bit memory address word is generated with the aid of an 8212 in the following manner:
The J1PD8257-5 outputs the least significant eight bits (AO-A7) which go directly
onto the address bus.
The J1PD8257-5 outputs the most significant eight bits (A8-A15) onto the data
bus where they are latched into an 8212 and then sent to the high order bits on
the address bus.
• The appropriate memory and I/O read/write control signals are generated allowing
the peripheral to receive or deposit a data byte directly from or to the appropriate
memory location.
Block transfer of data (e.g., a sector of data on a floppy disk) either to or from a
peripheral may be accomplished as long as the peripheral maintains its DMA Request
(DRO n ). The J1PD8257-5 retains control of the system bus as long as DRO n remains
high or until the Terminal Count (TC) is reached. When the Terminal Count occurs,
TC goes high, informing the CPU that the operation is complete.
There are three different modes of operation:
•
DMA read, which causes data to be transferred from memory to a peripheral;
•
DMA write, which causes data to be transferred from a peripheral to.memory; and
•
DMA verify, which does not actually involve the transfer of data.
The DMA read and write modes are the normal operating conditions for the J1PD8257-5.
The DMA verify mode responds in the same manner as read/write except no memory
or I/O read/write control signals are generated, thus preventing the transfer of data. The
peripheral gains control of the system bus and obtains DMA Acknowledgements for its
requests, thus allowing it to access each byte of a data block for check purposes or
accumulation of a CRC (Cylic Redundancy Code) checkword. In some applications it
is necessary for a block of DMA read or write cycles to be followed by a block of DMA
verify cycles to allow the peripheral to verify its newly acquired data.
670
FUNCTIONAL
DESCRIPTION
IlPD8257-5
DMA OPE RATION
Internally the J.LPD8257-5 contains six different states (SO, Sl, S2, S3, S4 and SW). The
duration of each state is determined by the input clock. In the idle state, (Sl), no DMA
operation is being executed. A DMA cycle is started upon receipt of one or more DMA
Requests (DROn ), then the J.LPD8257-5 enters the SO state. During state SO a Hold
Request (H RO) is sent to the 8080A/8085A and the J.LPD8257-5 waits in SO until the
8080A/8085A issues a Hold Acknowledge (HLDA) back. During SO, DMA Requests
are sampled and DMA priority is resolved (based upon either the fixed or priority
scheme). After receipt of HLDA, the DMA Acknowledge line (DA'C'K n ) with the highest priority is driven low, selecting that particular peripheral for the DMA cycie. -The
DMA Request line (DRO n ) must remain high until either a DMA Acknowledge
(DACK n ) or both DACK n and TC (Terminal Count) occur, indicating the end of a
block or sector transfer (burst model).
The DMA cycle consists of four internal states; Sl, S2, S3 and S4. If the access time
of the memory or I/O device is not fast enough to return a Ready command to the
J.LPD8257·5 after it reaches state S3, then a Wait state is initiated (SW). One or more
than one Wait state occurs until a Ready signal is received, and the J.LPD8257-5 is
allowed to go into state S4. Either the extended write option or the DMA Verify mode
may eliminate any Wait state.
If the J.LPD8257·5 should lose control of the system bus O.e., HLDA goes low) then the
current DMA cycle is completed, the device goes into the Sl state, and no more
DMA cycles occur until the bus is reacquired. Ready setup time (tRS), write setup
time (tOW), read data access time (tRD) and HLDA setup time (tOS) should all be
carefully observed during the handshaking mode between the J.LPD8257·5 and the
8080A/8085A.
During DMA write cycles, the I/O Read (I/O R) output is generated at the beginning
of state S2 and the Memory Write (MEMW) output is generated at the beginning of
S3. During DMA read cycles, the Memory Read (MEMR) output is generated at the
beginning of state S2 and the I/O Write (I/O W) goes low at the beginning of state S3.
No Read or Write control signals are generated during DMA verify cycles.
RESET
DMA OPERATION
STATE DIAGRAM
Notes:
1
8224
11
}Q
ffiTB
.p2(TTLl
6
I
I
I
I
7
<1>2
I
I
I
A15
~3
4
13
16
11
9
5
18
20
7
~
~
8
8228
-~:~-j
~
1,
~
~
~
:6
ADDRESS
8US
I
~
T,5
REsiN --2.c
AO
13
21
17
18
HOLD
HlDA
D81N
WR
r.,D!'m~
14
25
26
27
29
13(
31
32
33
34
35
1
40
37
38
39
36
MEMR
MEMW
IIOR
IIOW
INTA
DO
I
I
DATA
\8US
I
D7
24
26
26
27
23
CONTROL
RUS
ii'O'mii
7
10
HlDA HRO
22
~
....
f¥-
~
~
~
t#--
~
37
f-4
26
38
23
22
21
3
4
1
2
13
12
11
CHIP SELECT
READY
II
39
40
19
25
/JPD
8257-5
18
24
RESET
ClK
17
14
cs
READY
16
15
36
5
IAEN ADSTE
8
9
11
113
DS2
ST8
~
DISABLE 1/0
ADDRESS BUS
,4
~
6
8
10
15
17
19
21
L..--.l
~
8212
18
20
22
Vce -1!.c:
ern
MD
2
GND
672
DSi
yl
DROo
DACKO
DROI
i5'Ac'K 1
DR02
DACK2
DR03
DACK3
TC
MARK
IlPD8257-5
PACKAGE OUTLINE
IlPD8257C-5
Plastic
ITEM
MILLIMETERS
INCHES
A
51.5MAX
1.62
2.54 ± 0.1
2.028 MAX
0.064
0.10± 0.004
0.5±0.1
48.26
.1.2 MIN
0.019 ± 0.004
1.9
0.047 MIN
0.10MIN
8
C
0
E
F
G
H
1
J
K
L
M
673
2.54 MIN
0.5 MIN
5.22 MAX
5.72 MAX
15.24
13.2
+ 0.1
0.25 _ 0.05
0.019 MIN
0.206 MAX
0.225 MAX
0.600
0.620
+ 0.004
0.010 _ 0.002
8257 -5DSR EV 4-1-82-CAT
NOTES
674
NEe
IlPD8259A
NEe Electronics U.S.A. Inc.
Microcomputer Division
PROGRAMMABLE INTERRUPT CONTROLLER
oESC RIPT ION
F EATU RES
The N EC tLPD825.9A.is a programmable interrupt controllerdirectly compatible with
the 8080A/8085A/8086/8088 microprocessors. tt can service eight levels of interrupts
and contains on-chip logic to expand interrupt capabilities up to 64 levels with the
addition of other tLPD8259As. The user is offered a selection of priority algorithms to
tailor the priority processing to meet his system requirements."These can be dynamically modified during operation, expanding the versatility of the system.
The tLPD8259A is c~mpletelY upwa~d compatible witt! the j.(PD8259-5, so software
written for the tLPD8259-5 will run on the tLPD8259A.
• Eight Level Priority Controller
•
•
•
•
•
•
•
PIN CONFIGURATION
Programmable Base Vector Address
Expandable to 64 Levels .'
Programmable Interrupt Modes (Algorithms)
Individual Request Mask Capability
Single +5V Supply (No Clocks)
Full Compatibility with 8080A/8085A/8086/8088
Available in 28-Pin Plastic and Ceramic Packages
cs
vcc
WR
AD
iNTA
AO
PIN NAMES
07
IR7
Os
IR6
07- 0 0
RD
05
IRS
~
04
IR4
Ca.
I.R3
02
IR2
01
IR1
DO
IRO
CASO
INT
CAS1
SP/EN,
GNQ
CAS 2
Rev/1
675
AO
CAS2- CASO
SP/EN
INT
iNTA
IRO-IR7
~
Data Bus (Bi-Directional)
Read Input
Write Input
Command Select Address
Cascade Lines
Slave Program Input I
Enable Buffer
Interrupt Output
Interrupt Acknowledge Input
Interrupt Request Inputs
Chip Select
m
"PD8259A
BLOCK DIAGRAM
PROCESSOR
PROCESSOR PROCESSOR
ADDRESS
BUS
CONTROL
BUS
INTERNAL
DATA
BUS
BUS
SLAVE
_____
PROGRAM
CASCADE
ENABLE
LINES
BUFFER
Operating Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. O°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150o C
Voltage on Any Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 to +7 Volts
Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1W
Data Bus Data Bus
PROCESSOR OUTPUT OPERATION (WRITE)
0
0
0
1
0
0
1
0
1
X
X
X
X
X
X
X
X
X
Data
Data
Data
Data
Bus -l> OCW2
Bus -l> OCW3
Bus -l> ICWl
Bus -l> OCW 1, ICW2, ICW3 ~
DISABLE FUNCTION
Notes:
Data Bus -l> 3-State
Data Bus -l> 3-State
TEST POINTS
~O
na
0.45
< )L
2~
ns
TIMING
WAVEFORMS
WRITE MODE
WR ----------------~
~------------~ I,--~~--------------~--,I ~-------ADDRESS BUS
AO ____________J
~__~~--------------~~
~--_____
DATA BUS
READ/iN'i'A MODE
RD/iN'i'A-----------_
1 - - - - - t R L R H - - - - I .,_______________
EN--------------+_~
tRI.EL
tRHAX
~----------~ ~~-----------------+-~ ~----------ADDRESS BUS
AO--------__- J
~~------------------+_~
~
____________
tRLD=iV
tAHDV
DATA BUS- - - - -
-
- - -
- - - - - - -
AC CHARACTERISTICS
(CONT.)
- - -
"""-_ _ _ _ _ _ _____'
OTHER TIMING
680
,..PD8259A
TIMING WAVEFORMS
(CONT.)
iiii'fA SEQUENCE
'"Jd),r-_~"_'"C_"'--'-
\~_1
____
-----"'o.
..... ®
-
\.
INT,
mTA - - - - - - - - , .
DB - - - - ~ - - - - - - - -
tCVDV --
CO·2----------------~---'+--~~--~-----------~
-tIALCV-
DETAI LED OPERATIONAL
DESCRIPTION
The sequence used by the IlPD8259A to handle an interrupt depends upon whether
an 8080A/8085A or 8086/8088 CPU is being used.
The following sequence applies to 808OA/8085A systems:
The IlPD8259A derives its versatility from programmable interrupt modes and the
ability to jump to any memory address through programmable CALL instructions. The
following sequence demonstrates how the IlPD8259A interacts with the processor.
1. An interrupt or interrupts appearing on IRO-7 sets the corresponding I R bites)
high. This in turn sets the corresponding IRR bites) high.
2. Once the IR R bites) has been set, the IlPD8259A will resolve the priorities
according to the preprogrammed interrupt algorithm. It then issues an INT signal
to the processor.
3. The processor group issues an
iNfA to the IlPD8259A when it receives the INT.
4, The iNTA input to the IlPD8:z59A from the processor group sets the highest
priority ISR bit and resets the corresponding IRR bit. The i'N'TA also signals the
IlPD8259A to issue an 8-bitCALL instruction op-code (11001101) onto its Data
bus lines.
5. The CALL instruction code instructs the processor group to issue two more
i'N'TA pulses to the IlPD8259A.
6~ The two i'N'TA pulses:signal the IlPD8259A to place its preprogrammed interrupt
vector address onto the Data bus. The first iN'TA releases the low-order 8-bits
of the address and the second iNfA releases the high-order 8-bits.
7. The IlPD8259A's CALL instruction sequence is complete. A preprogrammed
EOI (End-of-Interrupt) command is issued to the IlPD8259A at the end of an
interrupt service routine to reset the ISR bit and allow the IlPD8259A to service
the next i,nterrupt.
'
For 8086/8088 systems the first three steps are the same as described above, then the
following sequence occurs:
4. During the first i"N'TA from the processor, the IlPD8259A does not drive the
data bus. The highest priority ISR bit is set and the corresponding I R R bit is
reset.
5. The IlPD8259A puts vector onto the data bus on the second iNTA pulse from
the 8086/8088.
6. There is no third INTA pulse in this mode. In the AEOI mode the ISR bit is
reset at the end of the second INT A pulse, or it remains set until an EOI command is issued.
681
9
IlPD8259A
INTERRUPT
8080A/8085A MOOE
SEQUENCE
For these processors, the JlPD8259A is controlled by three INTA pulses. The first
INTA pulse will cause the JlPD8259A to put the CALL op-code onto the data bus. The
second and third INTA pulses will cause the upper and lower address of the interrupt
vector to be released on the bus.
07
DI
OS
D4
03
02
01
DO
I
FIRSTINTA
CALL CODE 1<-_1_ _ _ _ _ _ _ _ _ _ _ _---'1
1ft
1"'-1.4
07
DI
05
D4
03
02
01
DO
T
A7
A&
A5
1
1
1
0
0
6
A7
A&
A5
1
1
0
0
0
5
A7
A&
A5
1
0
1
0
0
A7
0
•:3
A6
A5
1
0
0
0
A7
A6
A5
0
1
1
0
2
A7
A&
A5
0
1
0
0
0
1
A7
A8
A5
0
0
1
0
0
0
A7
A8
AS.
0
0
0
0
0
07
DI
05
04
02
01
DO
0
1111
0
SECONO"'i'NfA
In'.",.I.e
03
7
A7.
A6
1
1
1
0
0
6
5
A7
A6
1
1
0
0
0
0
A7
A6
1
0
1
0
0
0
4
A7
A6
1
0
0
0
0
0
3
A7
A6
0
1
1
0
0
2
A7
A6
0
1
0
0
0
0
0
1
A7
A6
0
0
1
0
0
0
0
A7
A6
0
0
0
0
0
0
07
DI
05
D4
03
02
01
DO
A15
A14
A13
A12
All
Al0
A9
A8
In this mode only two INTA pulses are sent to the JlPD8259A. After the first INTA
pulse, the JlPD8259A does not output a CALL but internally sets priority resolution.
If it is a master, it sets the cascade lines. The interrupt vector is output to the data bus
on the second INTA pulse.
IR7
IR6
IR5
IR4
IR3
IR2
IR1
IRO
07
T7
T7
T7
T7
T7
T7
T7
T7
06
05
D4
03.
T6
T6
T6
T6
T6
T6
T6
T6
T5
T5
T5
T5
T5
T5
T5
T5
T4
T4
T4
T4
T4
T4
T4
T4
T3
T3
T3
T3
T3
T3
T3
T3
682
02
1
1
1
1
0
0
0
0
01
1
1
0
0
DO
1
0
1
0
1
1
1
0
0
1
0
0
THIROTNTA
"PD8259A
INITIALIZATION ICW1 AND ICW2
COMMAND WORDS A5- A 15. Page starting address of service routines. In an 8085A system, the 8 request
levels generate CALLs to 8 locations equally spaced in memory. These can be programmed to be spaced at intervals of 4 or 8 memory locations, thus the 8 routines
occupy a page of 32 or 64 bytes, respectively.
The address format is 2 bytes long (AO-A15). When the routine interval is 4, AO-A4 are
automatically inserted by the IlPD8259A, while A5-A15 are programmed externally.
When the routine interval is 8, AO-A5 are automatically inserted by the IlPD8259A,
while A6-A15 are programmed externally.
The 8-byte interval maintains compatibility with current software, while the 4:-byte
interval is best for a compact jump table.
In an MCS-86 system, T7-T3 are inserted in the five most significant bits of the vectoring byte and the IlPD8259A sets the three least significant bits according to the interrupt level. Al0-A5 are ignored and ADI (Address Interval) has no effect.
LTIM:
If LTIM = 1, then the IlPD8259A operates in the level interrupt mode.
Edge detect logic on the interrupt inputs is disabled.
ADI:
CALL address interval. ADI = 1 then interval = 4; ADI = 0 then
interval = 8.
SNGL:
Single. Means that this is the only IlPD8259A in the system. If SNGL =
1 no ICW3 is issued.
If this bit is set - ICW4 has to be read. If ICW4 is not needed, set
IC4 = O.
IC4:
ICW3
This word is read only when there is more than one IlPD8259A in the system and cascading is used, in which case SNGL = O. It will load the 8-bit slave register. The functions of this register are:
a. In the master mode (either when SP = 1, or in buffered mode when MIS = 1 in
ICW4) a "1" is set for each slave in the system. The master then releases
byte 1 of the call sequence (for 8085A system) and enables the corresponding slave to release bytes 2 and 3 (for 8086/8088 only byte 2) through the
cascade lines.
b. In the slave mode (either when SP = 0, or if BUF = 1 and MIS = 0 in ICW4)
bits 2-0 identify the slave. The slave compares its cascade input with these bits
and if they are equal, bytes 2 and 3 of the CALL sequence (or just byte 2 for
8086/8088) are released by it on the Data Bus.
ICW4
SFNM:
If SFNM = 1 the special fully nested mode is programmed.
BUF:
If BUF = 1 the buffered mode is programmed. In buffered mode SP/EN
becomes an enable output and the masterlslave determination is by
MIS.
MIS:
If buffered mode is selected: MIS = 1 means the IlPD8259A'is programmed to be a master, MIS = 0 means the IlPD8259A is programmed
to be a slave. If BUF = 0, MIS has no function.
AEOI:
If AEOI
IlPM:
Microprocessor mode: IlPM = 0 sets the IlPD8259A for 8085A system
operation, IlPM = 1 sets the IlPD8259A for 8086 system operation.
=
1 the automatic end of interrupt mode is programmed.
683
"PD8259A
OJ
DI
DI
1M
DO
INCIL
IC4
ICWI
Al0
Ai
AI
ICWI
521102
81/101
SOliDO
ICW•
......
1CW4
".,
AI5/17
If
•
INITIALIZATION
SEQUENCE
DI
DI
AlOI
684
liPD8259A
OPPERATIONAL COMMAND Once the JlPD8259A has been programmed with Initialization Command Words,
WORDS (oew's) @ it can be programmed for the appropriate interrupt algorithm by the Operation
Command Words. Interrupt algorithms in the JlPD8259A can be changed at any time
during program operation by issuing another set of Operation Command Words. The
following sections describe the various algorithms available and their associated OCW's.
INTERRUPT MASKS
The individual Interrupt Request input lines are maskable by setting the corresponding
bits in the Interrupt Mask Register to a logic "1" through OCW1. The actual masking
is performed upon the contents of the In-Service Register (e.g., if Interrupt Request
line 3 is to be masked, then o~ly bit 3 of the IMR is set to logic "1." The IMR in turn
acts upon the contents of the ISR to mask b~t 3). Once the JlPD8259A has acknowledged
:an interrupt, Le." the JlPD8259A has sent an INT signal to the processor and the system
controller has sent it an TNTA signal, the Interrupt input, although it is masked,
inhibits lower priority requests from being acknowledged. There are two means of
enabling these lower priority interrupt lines. The first is by issuing an End-of-Interrupt
(EOI) through Operation Command Word 2 (OCW2), thereby resetting the appropriate ISR bit. The second approach is 'to select the Special Mask Mode through OCW3.
The Special Mask Mode (SMM) and End-of-Interrupt (EOI) will be described in more
detail further on.
FULLY NESTED MODE
The fully nested mode is the JlPD8259A's basic operating mode. It will operate in this
mode after the initialization sequence, without requiring Operation Command Words
for formatting. Priorities are set IRO through IR7, with IRO the highest priority. After
the interrupt has been acknowledged by the processor and system controller, only
higher priorities will be serviced. Upon receiving an INTA, the priority resolver
determines the priority of the interrupt, sets the corresponding IR bit, and outputs the
vector address to the Data bus. The EOI command resets the corresponding ISR bits at
the end of its service routines.
Notes:
G)
Reference Figure 2
® Reference Figure 3
685
"PD8259A
ROTATING PRIORITY MODE COMM~NDS
The two variations of Rotating Priorities are the Auto Rotate and Specific Rotate
modes. These two modes are typically used to service interrupting devices of equivalent
priorities.
1. Auto Rotate Mode
Programming the Auto Rotate Mode throuQh OCW2 assign's priorities 0-7 to the
interrupt request input lines. Interrupt line IRO'is set to the highest priority and
I R7 to the lowest. Once an interrupt has been serviced it is automatically
assigned the lowest priority. That same input must then wait for the devices
ahead of it to be serviced before it can be acknowledged again. The Auto Rotate
Mode is selected by programming OCW2 in the foilowing way (refer to Figu~e 3):
set Rotate Priority bit "R" to a logic "1"; program EOI to a logic "1" and SEOI
to a logic "0." The EOI and SEOI commands are discussed further· on. The
following is an example of the Auto Rotate Mode with devices requesting
interrupts on lines t~2 and IRS.
Before Interrupts are Serviced:
In-Service Register
IS7
IS6
I I
0
0
ISS
IS4
IS3
IS2
ISl
ISO
I I I I I 0"
0
0
0
Priority Status
Register
-----
Highest
Priority
Aceordingto the Priority Status Register, I R2 has a higher priority th~1n I R5 and
will be serviced first.
After Servicing:
157
In-Service Register
I0
156
0
155
IS4
IS3
IS2
0
0
0
ISl
ISO
I I0
0
~
Priority Status
Register
Highest
Priority
IIR211R11 1R O IIR711R611R511R411R3 I
At the completion of I Rts service routine the corresponding In-Service Register
bit, IS2 is reset to "0" by the preprogrammed EOI command. I R2 is then assigned
the lowest priority level in the Priority Status Register. The J.LPD8259A is now
ready to service the next highest interrupt, which in this case, is IRS'
2. Specific Rotate Mode
The priorities are set by programming the lowest level through OCW2. The
J.LPD8259A then automatically assigns the highest priority. If, for example, IR3 is
set to the lowest priority (bits L2, L 1, LO form -the binary code of the bottom
priority leve!), then IR4 will be set to the highest priority. The Specific Rotate
Mode is selected by programming OCW2 in the following manner: set Rotate
Priority bit "R" to a logic "1," program EOI to a logic "0," SEOI to a logic "1"
and L2, Ll, LO to the lowest priority level. If EOI is set to a logic "1," the ISR
bit defined by L2, Ll, LO is reset.
686
OPERATIONAL COMMAND
WORDS (CONT.)
IlPD8259A
OPERATIONAL COMMAND
WORDS (CONT.)
END·Of·INTERRUPT (EO!) AND SPECifiC END·Of-INTERRUPT (SEOI)
The End-of-Interrupt or Specific End-of-Interrupt command must be issued to reset the
appropriate In-Service Register bit before the completion of a service routine. Once the
ISR bit has been reset to logic "0," the JlPD8259A is ready' to service the next interrupt.
Two types of EOls are available to clear the appropriate ISR bit depending on the
JlPD8259A's operating mode:
1. Non-Specific End-of-Interrupt (EOI)
When operating in interrupt modes where the priority order of the interrupt inputs
is preserved (e.g., fully nested mode). the particular ISR bit to be reset at the completion of the service routine can be determined. A non-specific EOI command
automatically resets the highest priority ISR bit of those set.1The highest
priority ISR bit must necessarily be the interrupt being serviced and must necessarilY be the service subroutine returned from.
2. Specific End-of-Interrupt (SEOI)
When operating in interrupt modes where the priority order of the interrupt
inputs is not preserved (e.g., rotating priority mode) the last serviced interrupt
level may not be known. In these modes a Specific End-of-Interrupt must be
issued to clear the ISR bit at the completion of the interrupt service routine.
The SEOI is programmed by setting the appropriate bits in OCW3 (figure 2)
to logic "l"s. Both the EOI and SEOI bits of OCW3 must be set to a logic "1"
with L2, L 1, LO forming the binary code of the ISR bit to be reset.
SPECIAL MASK MODE
Setting up an interrupt mask through the Interrupt Mask Register (refer to Interrupt
Mask Register section) by setting the appropriate bits in OCWl to a logic "1"
inhibits lower priority interrupts from being acknowledged. In applications requiring
that the lower priorities be enabled while the IMR is set, the Special Mask Mode can be
used. The SMM is programmed in OCW3 by setting the appropriate bits to a logic "1."
Once the SMM is set, the JlPD8259A remains in this mode until it is reset. The Special
Mask Mode does not affect the higher priority interrupts.
POLLED MODE
In Poll Mode the processor must be instructed to disable its interrupt input (INT).
Interrupt service is initiated through software by a Poll Command. Poll Mode is
programmed by setting the Poll Mode bit in OCW3 (P = 1), during a WR pulse. The
following RO pulse is then considered as an interrupt acknowledge. If an interrupt
input is present, that R D pulse sets the appropriate ISR bit and reads the interrupt
priority level. Poll Mode is a one-time operation and must be programmed through
OCW3 before every read. The word strobed onto the Data bus during Poll Mode is of
the form:
07
06
05
04
03
02
01
DO
I I I X I X I ~ I X I W2 I Wl I Wo I
where:
1- 1 if there is an interrupt requesting service
= 0 if there are no interrupts
W2-0 forms the binary code of the highest priority
level of the interrupts requesting service
Poll Mode can be used when an interrupt service routine is common to several interrupt inputs. The INTA sequence is no longer required, thus saving in ROM space.
Poll Mode can also be used to expand the number of interrupts beyond 64.
687
",PD8259A
INITIALIZATION COMMAND
WORD FORMAT
ICW'
, ICIIM HEEDED
0 NO ICIM ..UDlD
o
I.
o•
SINGlE
CASCADE MODE
CALL ...DOIIED I.. UIIYAL
'oINTlIIV ..."
0 0 INUIIV ... L 0"
0'"
, • LEVEL TRIGGERED MODE
EDGE TRIGGERED MODE
o•
ICWJ
....
DJ
0,
D•
=:""
~~~~OF
(MCSIOIU MODE)
~~61~=:':T
ICW:l IM .... UII DEVICEI
(1OIe1eoel MODE)
, • III INPUT "AS'" SL ... VE
o • III INPUT DOn NOT HAVE
... SL ...VE
....
l'
ICWJ III. ...VI OEVICII
DJ
0.
a.
D.
~
0,
L7
0,
I 01 01 0 1 01 °1~1~1~1
5,,"'VllOl"
,
o ,
:I
o , o ,
o 0
o
o 0
..
"
,
•
0
J
,
,,0 ,,
0 ,,,,
0
0
, . lOIe,eDllMODE
MODI
o•
MCa-eo,.
,. AUTO EOI
0 NDllIII..... EO.
o
EEm
Il
,
I
. IlION IUFfEIIEO MODI
- IUfFEIIEO MODIISL ... VI
- IUFfIIlIO MODI ....... UII
NOtE 1: SLAVE 10 IS EQUAL TO THE CORRESPONDING MASTER IR INPUT.
688
"PD8259A
READING
~PD8259
STATUS
The following major registers' status is available to the processor by appropriately
formatting OCW3and issuing AD command.
INTERRUPT REQUEST REGISTER (8-BITS)
The Interrupt Request Register stores the interrupt levels awaiting acknowledgement.
The highest priority in-service bit is reset once it has been acknowledged. (Note that
the Interrupt Mask Register has no effect on the IRR.) A WR command must be issued
with OCW3 prior to issuing theRD command. The bits which determine whether the
IRR and ISR are being read from are RIS and ERIS. To read contents of the IRR, ERIS
must be logic "1~' and R IS a logic "0."
IN-SERVICE REGISTER (8-BITS)
The In-Service Register stores the priorities of the interrupt levels' being serviced.
Assertion of an End-of-Interrupt (EOI) updates the ISR to the next priority level. A
WR command must be issued with OCW3 prior to issuing the RD command. Both ERIS
and RIS should be set to a logic "1."
INTERRUPT MASK REGISTER (8-BITS)
The Interrupt Mask Register holds mask data modifying interrupt levels. To read the
IMR status a WR pulse preceding the RD is not necessary. The IMR data is available to
the data bus when RD is asserted with AO at a logic "1."
A single OCW3 is sufficient to enable successive status reads providing it is of the same
register. A status read is over-ridden by the Poll Mode whEln bits P and ERIS of OCW3
are set to a logic "1."
OPESATION COMMAND
WORD FORMAT
OCW1:
OCW2:
Ao
07
I0 I
R
De
05
04
03
02
I 5EOIleOI I 0 I 0 I
L2
I'
01
I
Ll
DO
I
Lo
BINARY LEVEL TO BE RESET
OR PUT INTO LOWEST PRIORITY
I
o
I L- oo
J
1 2 3 4 & 6 7
1
o
o
1
0 1 1 0
1 0 1
o
1 1
o 0 o 0 1 1 1 1
NON-speCIFIC END OF INTERRUPT
1 • Reset thl H~hHt Priority
J
I O.~:~~::
I SPECIFICENO OF INTERRUPTI
I O·
1· L2. Ll. Lo Bill or. u.d
No AClion
I ROTATE PRIORITY
t ~: ~:~~:tlt.
OCW3:
I
0
I - I
ESMM
I
SMM
I
0
I
1
I
P
I
ERIS
I
RIS~
r
I RNd In·SelVico R.......
0
0
1
0
1
0
1
1
1
RNd81na'V~o'
Highet. L_ R_lItlng
I.....rup. on NIX. 11'5 PuIM
No .....1on
No Acllon
No Acllon
RNd.!.!! Roe. on
N... ROPuI.
RNd IS Rill-on
_.""'Pul.
Polling
0
t. '....I.. _ k _
I 0 10 I No .....1on
I
1
NoAc.1on
01 RNd .... IoIM.k
11 1 I SttSpocIolMotok
0
11
689
I
1
1
I
I
I
INSTRUCTION SET SUMMARY
flPD8259A
SUMMARY OF 8259A INSTRUCTION SET
Inlt.'
,
ICW'
A
2
3
ICW'
B
ICW'
C
4
ICW'
ICW'
0
5
8
E
F
7
ICW'
ICW'
G
8
ICW'
H
9
ICW'
'0
ICW'
ICW'
ICW,
K
L
ICW'
ICW'
M
N
"
'2
'3
'4
'5
'8
17
lew, 0
lew., p
leW3
M
5
A
ICW4
e
23
24
leW4
0
leW4
E
25
leW4
F
26
leW4
G
27
leW4
H
28
29
leW4
leW4
30
leW4
3'
leW4
32
leW4
leW4
M
N
35
leW4
ICW4
38
leW4
37
leW4
38
ICW4
ICW4
0
P
NA
NB
NC
NO
NE
NF
NG
NH
NI
NJ
NK
NL
NM
NN
NO
NP
20
2'
22
33
34
39
40
41
42
43
44
ICW4
ICW4
ICW4
leW4
45
ICW4
ICW4
46
47
ICW4
ICW4
48
49
ICW4
ICW4
50
ICW4
ICW4
5'
52
53
54
55
56
59
60
61
OCWl AI5
58
ASE
A
CA
AS
P
A8
A8
A5
A5
o
,
,
,
0
0
A7
A8
A5
o
A7
A8
A5
1
1
o
o
0
0
A7
A8
o
0
,
,
0
0
o
o
0
0
A7
A8
A7
A7
A8
A8
0
0
0
0
A7
A8
A5
A7
A8
A5
A7
A8
A5
A7
A8
A5
A7
A7
A8
A8
A7
A8
A7
A8
0
0
0
0
Format = 4, single, edge triggered
o
I
o
}
,
0
o
0
o
,
,
o , o
, , o
o 0 ,,
,
0
0
o
A'O
52
o
o
A9
0
a
a
0
o
o
o
o
a
a
a
1
M7
M6
a
o
o
0
a
a
a
0
0
0'
M5
Format 4, lingle, level triggered
Format- 4, not lingle, edge triggered
ICW4 Required
Format. 4, not alngle, level triggered
Format. 8, lingle, edge triggered
Format. 8, lingle, level triggered
Format. 8, not alngle, edge triggered
a
a
0
1
1
1
0
1
o
0
ma.ter
N6n-bliffered mode, AEOI, 80/85
Non-buffered mode, AEOI, 8086/8088
No action, redundant
Non-buffered mode, no AEOI, 8086/8088
Non-buffered mode, AEOI, 80/85
Non-buffered mode, AEOI, 8086/8088
Buffered mode, slave. no AEOI, 80/85
Buffered mode, slave, no AEOI. 8086/8088
Buffered mode, slave, AEOI, 80/85
Buffered mode, slave, AEOI, 8086/8088
Buffered mode, master, no AEOI, 80/85
Buffered mode, master, no AEOI, 8086/8088
Buffered mode, master, AEOI, 80/85
Buffered mode, master AEOI, 8086, 8088
}
Fully nested mode, 8085A, non-buffered, no AEOI
ICW4 NB through ICW4 NO are identical to
ICW4 B through ICW4 0 with the addition of
Fully Nested Mode
Fully Nested "Mode, 80/85, non-buffered, no AEOI
ICW4 NF through ICW4 NP are identical to
ICW4 F through ICW4 P with the addition 01
Fully Nested Mode
1
0
1
1
000
Non-specific EOI
0
o
o
o
o
o
L2
Specific EOI, LO-L2 code of IS FF to be reset
\)
0
0
0
0
0
0
0
0
o
o
o
=
Byte' Initialization
0
1
a
Format. 4, lingle, edge triggered
0
1
a
Format = 8, single, level triggered
Format - 8, not lingle, edga triggered
Format = 8, not lingle, level triggered
M3
a
a
Format = 4, not single, level triggered
Format = 8, single, edge triggered
M4
1
0
o
0
0
1
1
a
a
o
a
1
a
No leW4 Requlrpd
Byte 3 Initialization - Ilave
No action, redundant
Non-butfered mode, no AEOI, 8086/8088
,
o
Format = 4, single, level triggered
Format = 4, not single, edge triggered
Format.8, not alngle, level triggered
5' so
0
0
0
0 52 5' so
00000
0
0
0
00000001
o 0 0 0 000
000000'
,
0000000
o 0 0 0 0
o 0 0 0 0
00000
o 0 0 0
o 0
o 0 1
o 0 0 0
o
0
000
o 1 1
000
0
o 0
000
0
o 1
o 0 0 0
o
000
0
o 1 1
000
o 0 0 .Q
000
o 0 0 1
000
000
000
000
o 0
000
o
0
o 0
o
1
000
o
a
o 1 1 1
000
000
000
000
Byte' Initialization
Byte 2 Initialization
Byte 3 Initialization -
A8
o
K
OCW'
OCW2 E
OCW2 SE
OCW2 AE
A7
A7
A,5 A'4 A'il A,2 A"
57 56 55 54 53
B
OCW2
OCW2
OCW2
OCW2
OCWl
57
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
ICW2
leW3
leW4
leW4
'8
'9
Operation Descrtptlon
Mnemontc
M2
Ml
Ll
MO
LO
Load mask register, read mark register
a
0
Rotate on Non-Specific EOI
L2
Ll
La
Rotate on Specific EOI LO-L2 code of line
0
0
0
0
0
0
L2
1
Ll
0
LO
0
Rotate in Auto EOI (set)
Rotate in Auto EOI (clear)
Set Priority Command
Poll mode
o
Read IS register
690
IlPD8259A
SUMMARY OF OPERATION
COMMAND WORD
PROGRAMMING
AO
04
03
OCW1
1
X
X
OCW2
0
0
0
OCW3
SEOI
EOI
0
0
0
No Action
0
0
1
Non-Specific End-of-Interrupt
0
1
0
No Action
0
1
1
Specific-End-of-Interrupt L2. L,. LO forms binary rapr.llntetlon
of level to be relit.
1
0
0
No Action
1
0
1
Rotate Priority at End-of-Interrupt (Auto Model
1
1
0
Rotate Priority. L2•. L,.
End-of-Interrupt
1
1
1
Rotate Priority at End-of-Interrupt (Specific Mode). L2. L,. LO
specifies bottom priority. and In In-Service Register bit is rlilt.
ESMM
SMM
0
0
1
1
0
Raset Special Mask
1
Set Special Mask
1
La specifi .. bottom prloritv without
Special Mask not affected
0
ERIS
LOWER MEMORY
INTERRUPT VECTOR
ADDRESS
AD reeds status
R
1
0
0
IMR Unterrupt Mask Register) WR loads IMR detl Wlill
M7-M0
RIS
0
0
0
1
No Action
1
0
Read IR Register StatUI
1
1
Reed IS Register Status
INTERVAL-S
INTERVAL -4
07
IR7
A7
IRa
A7
IRS
A7
IR4
A7
IR3
A7
iR2
A7
IR1
A7
IRO
A7
De
Ae
As
As
As
As
As
As
As
Os
04
03
02
0,
DO
07
De
Os
04
03
02
0,
AS
1
1
1
0
0
A7
1
1
1
0
0
0
AS
1
1
0
0
0
A7
1
1
0
0
0
0
AS
1
0
1
0
0
A7
·1
0
1
0
0
0
AS
1
0
0
0
0
A7
1
0
0
0
0
0
AS
0
1
1
0
0
A7
As
As
As
As
As
0
1
1
0
0
0
AS
0
1
0
0
0
A7
Aa
0
1
0
0
0
0
AS
0
0
1
0
0
A7
0
1
0
0
0
0
0
0
0
0
A7
As
As
0
AS
0
0
0
0
0
0
DO
FIGURE 4
Note: Insure that the processor's Interrupt input is disabled during the execution of any control command and
Initialization sequence for all ",PD8259A's.
l
I'fIOCESSOR,II,DO''lEsseulntl
t
PROCIISSOACONTROLIUS
)
P'ROCESIORDAT.... UIIII
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-- --- ---
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---
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""D8269A
CAS'
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11'111'111'1
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CAS 2
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11'1
11'1
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11'111'1
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CAS.
,.PD8261A
""D82I111A
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1ft
,
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",PD8259A
PACKAGE OUTLI NE
J.lPD8259AC
Plastic
ITEM
MILLIMETERS
38.0 MAX.
2.49
0.098
2.54
0.10
o ~~ 0.1
0.02' 0.004
33.02
M
INCHES
1.496 MAX.
1.3
1.5
0.059
2.54 MIN.
O.IOMIN.
0.5 MIN.
0.02 MIN.
5.22 MAX.
0.205 MAX.
6.72 MAX.
0.225' MAX.
15.24
0.8
13.2
0.52
0.25~~::
0.01
~~:::
J.lPD8259AD
Ceramic
ITEM
A
o
G
M
MILLIMETERS
36.2 MAX.
1.59 MAX.
2.54 t 0.1
0.46' 0,01
33.02 ± 0.1
1.02 MIN.
3.2MIN.
1.0MIN.
3.5 MAX.
4.5 MAX.
15.24 TYP.
14.93 TYP.
0.25 ± 0.06
692
INCHES
1.43 MAX.
0.06 MAX.
0.1 , 0.004
0.02 t 0.004
1.3' 0.004
0.04 MIN.
0.13MIN.
0.04 MIN.
0.14 MAX.
0.18 MAX.
0.6 TYP.
0.59 TYP.
0,01.0.002
8259A DS-R EV1-1-82-CA T
NEe
IlPD8279-5
NEe Electronics U.S.A. Inc.
Microcomputer Division
PROGRAMMABLE KEYBOARD/DISPLAY
INTERFACE
OESCR IPTION
The J.LPD8279-5 is a programmable keyboard and display Input/Output device. It
provides the user with the ability to display data on alphanumeric segment displays
or simple indicators. Thedisplay RAM can be programmed as 16 x 8 or a dual
16 x 4 and loaded or read by the host processor. The display can be loaded with
right or left entry with an auto-increment of the display RAM address.
The keyboard interface provides a scanned signal to a 64 contact key matrix expandable to 128. General sensors or strobed keys may also be used. Keystrokes are stored
in an 8 character FIFO and can be either 2 key lockout or N key rollover. Keyboard
entries generate an interrupt to the processor.
FEATURES
• Programmable by Processor
•
32 HEX or 16 Alphanumeric Displays
•
64 Expandable to 128 Keyboard'
•
Simultaneous Keyboard and Display
•
8 Character Keyboard - FIFO
•
2 Key Lockout or N Key Rollover
•
Contact Debounce
•
Programmable Scan Timer
•
Interrupt on Key Entry
•
Single +5 Volt Supply, ±10%
• Fully Compatible with 8080A, B085A, J.LPD780 (Z80™)
•
PIN CONFIGURATION
Available in 40 Pin Plastic Package
PIN NAMES
RL2
RL3
VCC
RL,
RLO
CNTL/STB
SHIFT
CLK
'IRQ
RL4
RLS
RL6
RL7
RESET
J.LPD
8279-5
SL3
SL2
SL,
SLO
OUT BO
OUTB,
OUT B2
OUTB3
OUT'AO
OUTA,
OUTA2
OUTA3
BD
Cs
AO
TM: Z80 is a registered trademark of Zilog, Inc.
Rev/1
693
Data Bus (Bi-directional)
DBO-7
CLK
Clock Input
RESET
Reset Input
B
Chip Select
RD
Read Input
Wi!!
Write Input
AO
IRQ
Buffer Address
SLO·3
RLO_7
SHIFT
Scan Lines
Shift Input
CNTL/STB
Control/Strobe Input
Interrupt Request Output
Return Line.
OUT AO.3
DllPlav (AI Output.
OUT BO.3
DilPllIV (BI Outputs
1m
Bland DllPlev Output
IlPD8279-5
The /-LPD8279-5 has two basic functions: 1) to control displays to output and 2) to
control a keyboard for input. Its specific purpose is to unburden the host processor
from monitoring keys and refreshing displays. The /-LPD8279-5 is designed to directly
interface the microprocessor bus. The microprocessor must program the operating
mode to the /-LPD8279-5, these modes are as follows:
FUNCTIONAL
DESCRIPTION
Output Modes
• 8 or 16 Character Display
• Right or Left Entry
Input Modes
• Scanned Keyboard with Encoded 8 x 8 x 4 Key Format or Decoded 4 x 8 x8
Scan Lines.
• Scanned Sensor Matrix with Encoded 8 x 8 or Decoded 4 x 8 Scan Lines.
• Strobed Input.
BLOCK DIAGRAM
CLK RESET
DBO·7
IRQ
KEYBOARD
DEBOUNCE
AND
CONTROL
OUT AO.3
OUT BO.3
SLO·3
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . O°C to +70°C
o
. -65°C to +150 C
Storage Temperature ..... .
-0.5 to +7 VoltsCD
All Output Voltages . . . . . . . . . . . . . . .
-0.5 to +7 VoltsCD
All Input Voltages . . . . . . . . . . . .
-0.5 to +7 VoltsCD
Supply Voltages . . . . . . . . . . .
. .....•.... 1W
Power Dissipation . . . . . . .
Note:
CD With respect to vss
*COMMENT: Stress above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability .
694
ABSOLUTE MAXIMUM
RATINGS*
IiPD8279-5
PIN IDENTIF ICATION
PIN
NO.
SYMBOL
DESCRIPTION
NAME
1,2,5,
6,7,8,
38,39
RLO-7
Return Lines
3
elK
IRQ
Clock
4
9
10
_ _o
__
11
12·19
1--'
Return line inputs which are connected to the scan
lines through the keys or sensor switches. They
have active internal pullups to keep them high until
a switch closure pulls one low. They also serve as an
8-bit input in the Strobed Input mode.
Clock from system used to generate internal timing.
Interrupt
Request
. Interrupt Request. In a keyboard mode, the interrupt line is high when there is data in the FIFO/
Sensor RAM. The interrupt line goes low with each
FIFO/Sensor RAM read and returns high if there
is still information in the RAM. In a sensor mode,
the interrupt line goes high whenever a change in a
sensor is detected.
. A high signal on this pin resets the J-IPD8279-5.
Reset
Reset Input
RD
Read Input
WR
Write Input
Input/Output read and write. These signals enable
the data· buffers to either send data to the external
bus or receive it from the external bus.
- - - - - r------'
0 _ _ _ _ _ _-
DBO·7
Data Bus
20
VSS
Ground
Reference
21
AO
Buffer Address
Buffer Address. A high on this line indicates the
signals in or out are interpreted as a command or
status. A low indicates that they are data.
22
CS
Chip Select
Chip Select. Alow on this pin enables the interface functions to receive or transmit.
23
BD
Blank Display
Output
24-27
OUTA0-3
Display A
Outputs
28-31
OUT BO-3
Display B
Outputs
Blank Display. This output is used to blank the
display during digit switching or by a display
blanking command.
-_._-These two ports are the outputs for the 16 x 4
display refresh registers. The data from these outputs is synchronized to the scan lines (SlO-Sl3)
for multiplexed digit displays. The two 4-bit ports
may be bl an ked independently. These two ports
may also be considered_ as one 8-bit por!.
32-35
SlO-3
Scan lines
Scan Lines which are used to scan the key switch
or sensor matrix and the display digits. These
lines can be either encoded (1 of 16) or decoded
(10f4).
36
Shift
Shift Input
37
CNTL/STB
Control/
Strobe Input
40
VCC
+5V Input
The shift input status is stored along with the key
position on key closure in the Scanned Keyboard
modes. It has an active internal pullup to keep it
high until a switch closure pulls it low.
For keyboard modes this line is used as a control
input and stored like status on a key closure. The
line is also the strobe line that enters the data into
the FIFO in Strobed input mode (Rising Edge). It
has an active internal pullup to keep it high until
a switch closure pulls it low.
-------Power Supply Input
Bi-Directional data bus. All data and commands
between the processor and the J-IPD8279-5 are
transmitte.d on these lines.
------Power Supply Ground
---
695
"
--
IiPD8279-5
DC CHARACTERISTICS
LIMITS
PARAMETER
SYMBOL
Input Low Voltage for
Return Lines
1.4
0.8
Input Low Voltage (Others)
VIL2
-0.5
VIHl
2.2
Input High Voltage (Others)
VIH2
2.0
Output Low Voltage
VOL
Input Currenfon Shift,
Control and Return Lines
UNIT
MAX
-0.5
Input High Vbltage for
Return Lines
Output High Voltage on
Inten lIpt Lille
TVP
MIN
VILl
TEST
CONDITIONS
V
V
V
V
V
IOL; 2.2 mA
+3.5
V
IOH
+2.4
V
IOH
0.45
IRQ
Pin
I----
OTHERS
+2.4
= -50/1 A
= -400/1A
IOH = -400/1A
V
+10
J..I.A
VIN ; VCC
-100
J..I.A
VIN; OV
I'L2
±10
J..I.A
VIN ; VCC to OV
Output Float Leakage
IOFL
+10
J..I.A
VOUT = Vce to OV
Powel Supply Current
ICC
120
mA
IILl
~-
Input Leakage Current
(Othelsl
PARAMETER
SYMBOL
Input Capacitance
CIN
Output Capacitance
COUT
Ta
LIMITS
MIN
TYP
UNIT
MAX
TEST
CONDITIONS
= VCC
= VCC
5
10
pF
VIN
10
20
pF
VOUT
= O°C to +70°C; Vec = +5V ± 10%; VSS = OV
PARAMETER
SYMBOL
AC CHARACTER ISTICS
LIMITS
MIN TYP MAX
UNIT
TEST
CONDITIONS
READ
J1EAU'
Hold Time for i1E'Ai'5
Address Stable Before
tAR
0
ns
Address
tRA
0
ns
READ Pulse Width
tRR
250
Data Delay from FfEAi)
tRD
150
ns
CL = 150 pF
Address to Data Valid
tAD
250
ns
CL = 150 pF
J1EAU' to Data
tDF
Floating
Read Cycle Time
tRCY
Address Stable Before WR ITE
lO
ns
100
ns
1
J,lS
tAW
0
ns
Address Hold Time for WR ITE
tWA
0
ns
WR ITE Pulse Width
tww
250
ns
Data Set Up Time for ~
tDW
150
ns
Data HoldTime for WRITE
Write Cycle Time
two
0
ns
WRITE
1jis
OTHER
Clock Pulse Width
t>W
120
ns
Clock Period
tCY
320
ns
GENERAL TIMING
Keyboard Scan Time:
Keyboard Debounce Time:
Key Scan Time:
Display Scan Time:
5.1 ms
10.3 ms
80lls
10.3 ms
CAPACITANCE
Digit-on Time:
Blanking Time:
Internal Clock Cycle:
696
480lls
160lls
10lls
IlPD8279-5
TIMING WAVEFORMS
INPUT FOR AC TESTS
2.4
0.45
READ
,-_,.P----------~-".~-------- (SYSTEM'S
AO,
CS
ADDRESS BUSI
(READ CONTROLI
~---
DATA BUS
(OUTPUTI
--~~~~~~~_4-~~-~~-+_-----------
WRITE
AO,
CS
-_J.---J:======~~~~=====:::~--
DATABUS----------~~~------·,.--------(lNPUTI
DATA MAY CHANGE
CLOCK INPUT
697
(SYSTEM'S
ADDRESS BUSI
",PD8279-5
The following is a description of each section of the J.lPD8279-5. See the block
diagram for functional reference.
I/O Control and Data Buffers
Communication to and from the J.lPD8279-5 is performed by selecting CS, AO, RD and
The type of information written or read by the processor is selected by AO. A
logic 0 states that information is data while a 1 selects command or status. R D and WR
select the direction by which the transfer occurs through the Data Buffers. When the
chip is deselected (CS = 1) the bi-directional Data Buffers are in a high impedance state
thus enabling the J.lPD8279-5 to·be tied directly to the processor data bus.
WR.
Timing Registers and Timing Control
The Timing Registers store the display and keyboard modes and other conditions programmed by the processor. The timing control contains the timing counter chain. One
counter is a divide by. N scaler which may be programmed to match the processor
cycle time. The scaler must take a value between 2 and 31 in binary. A value which
scales the internal frequency to 100 KHz gives a 5.1 ms scan time and 10.3 ms switch
debounce. The other counters divide down to make key, row matrix and display scans.
Scan Counter
The scan counter can operate in either the encoded or decoded mode. In the encoded
mode, the counter provides a count which must be decoded to provide the scan lines.
In the decoded mode, the counter provides a 1 out of 4 decoded scan. In the encoded
mode the scan lines are active high and in the decoded mode they are active low.
Return Buffers, Keyboard Debounce and Control
The eight return lines are buffered and latched by the return buffers. In the keyboard
mode these lines are scanned sampling for key closures in each row. If the debounce
circuit senses a closure, about 10 ms are timed out and a check is performed again. If
the switch is still pressed, the address of the switch matrix plus the status of shift and
control are written into the F IFa. In the scanned sensor mode, the contents of
return lines are sent directly to the sensor RAM (F IF 0) each key scan. In the strobed
mode, the transfer takes place on the rising edge of CNTLISTB.
FifO/Sensor RAM and Status
This section is a dual purpose 8 x 8 RAM. In strobe or keyboard mode it is a
FIFO. Each entry is pushed into the FIFO and read in order. Status keeps track of the
number of entries in the FIFO. Too many reads or writes to the F I Fa will be treated
as an error condition. The status logic generates an IRQ whenever the FIFO has an
entry. In the sensor mode the memory is a sensor RAM which detects changes in the
. status of a sensor. If a change occurs, the IRQ is generated until the change is
acknowledged.
Display Address Registers and Display RAM
The Display Address Register contains the address of the word being read or written
by the processor, as well as the word being displayed. This address may be programmed to auto-increment after each read or write. The display RAM may be read
by the processor any time after the mode and address is set. Data entry to the display
RAM may be set to either right or left entry.
698
OPE RATIONAL
DESCRIPTION
",PD8279-5
COMMAND OPE RATION
The commands programmable to the pPD8279-S'via the data bus with
and AO high are as follows:
CS active
(0)
Keyboard/Display Mode Set
1010]01DIDIKIKIKI
lSB
MSB
Display Mode:
DO
o
0
o
1 G)
16-8 bit character display - left entry
o
8-8 bit character display - Right e,tltry
8-8-bit character display - left entry
16-8 bit character display - Right entry
Note:
CD Power on default condition
Keyboard Mode:
KKK
0
0
0
0
0
0
0
Encoded Scan - 2 Key lockout
0
Encoded Scan - N Key Rollover
Decoded Scan - 2 Key lockout
1
1
Decoded Scan - N Key Rollover
0
0
Encoded Scan-Sensor Matrix
0
Strobed Input, Encoded Display Scan
Decoded Scan-Sensor Matrix
0
Strobed Input, Decoded Display Scan
Program Clock
loioldplplplpipi
Where PPPPP is the prescaler value between 2 and 31 th is prescaler divides the external
clock by PPPPP to develop its internal frequency. After reset, a default value of 31 is
generated.
Read FIFO/Sensor RAM
10 11 10 IAll X I A I A I A I
AO
=
0
Al is the auto-increment flag. AAA is the row to be read by the processor. The read
command is accomplished with (Cs. RD·
by the processor. If Al is 1, the row
select counter will be incremented after each read. Note that auto-incrementing has
no effect on the display.
Ac»
Read Display RAM
Where Al is the auto-increment flag and AAAA is the character which the processor
is about to read.
Write Display RAM
where AA.AA is the character the processor is about to write.
Display Write Inhibit Blanking
1
1
1
0
1
1 1
Xl ~1~wl~ll~l
I
Where IWA and IWB are I nhibit Writing· nibble A and B respectively, and BlA, BlB
are blanking. When using the display as a dual 4-bit, it is necessary to mask one of the
4-bit halves to eliminate interaction between the two halves. This is accomplished with
the IW flags. The Bl flags allow the programmer to blank either half of the display
independently. To blank a display formatted as a single B-bit, it is necessary to set
both BlA and BlB. Default after a reset is all zeros. All signals are active high (1).
699
",PD8279-5
Clear
o
CD
CD
CD
o
X
1
X
CA
All zeros
AB = 2016
All ones
Disable clear display
1 o
o
I CD I CD I CD I CF
X
This command is used to clear the display RAM, the FIFO, or both. The CD options
allow the user the ability to clear the display RAM to either all zeros or all ones.
CF clears the FIFO.
CA clears all.
Clearing the display takes one complete display scan. During this time the processor
can't write to the display RAM.
CF will set the FIFO empty flag and reset I RO. The sensor matrix mode RAM pointer
will then be set to row O.
CA is equivalent to CF and CD. The display is cleared using the display clear code
specified and resets the internal timing logic to synchronize it.
End Interrupt/Error Mode Set
1111111ElxlxlxlxI
In the sensor matrix mode, this instruction clears IRO and allows writing into RAM.
In N key rollover, setting the E bit to 1 allows for operating in the special Error mode.
See Description of FIFO status.
FIFO Status
I DU I S/E I 0 I U I
Where: DU
S/E
FIN I N N
Display Unavailable because a clear display or clear all command is in
progress.
Sensor Error flag due to multiple closure of switch matrix.
o
FIFO Overrun since an attempt was made to push too many
characters. into the FIFO.
U = FIFO Underrun. An indication that the processor tried to read an
empty FIFO.
F
NNN
FIFO Full Flag.
The Number of characters presently in the FIFO.
The FIFO Status is Read with AO high and CS, RD active low.
The Display not available is an indication that the CD or CA command has not
completed its clearing. The S/E flags are used to show an error in multiple closures has
occurred. The 0 or U, overrun or underrun, flags occur when too many characters are
written into the FIFO or the processor tries to read an empty FI FO. F is an indication
that the FIFO is full and NNN inhe number of characters in the FIFO.
Data Read
Data can be read during AO = 0 and when CS, RD are active low. The source of the
data is determined by the Read Display or Read FIFO commands.
Data Write
Data is written to the chip when AO, CS, and WR are active low. Data will be written
into the display RAM with its address selected by the latest Read or Write Display
command.
700
COMMAND OPERATION
(CONT.)
"PD8279-5
Data Format
COMMAND OPERATION
(CONT.)
:SCAN:
In the Scanned Key mode, the characters in the FIFO correspond to the above format
where CNTL and SH are the most significant bits and the SCAN and return lines are
the scan and column counters.
I
RL7
I
R L6
I
R LS
I
R L4
I
R L3
I
R L2
I
RL1
I
R LO
I
In the Sensor Matrix mode, the data corresponds directly to the row of the sensor
RAM being scanned. Shift and control (SH, CNTL) are not used in this mode.
Control Address Summary
~
DATA
MSB
LSB
0
0
0
0
0
I
D
K
K
K
Keyboard Display Mode Set
P
P
P
P
P
Load Program Clock
A1
X
A
A
A
Read FIFO/Sensor RAM
0
0
I
0
0
I
A1
A
A
A
A
Read Display RAM
0
I0
A1
A
A
A
A
Write Display RAM
0
I I I
IW
A
IW
B
BL
A
BL
B
ICD I CD I CD
CF
CA
0
X
I I
0
~I
IDU
PACKAGE OUTLIN E
J,LPD8279-5C
D
E
I I
S/E
0
U
I
I I
X
X
X
X
F
N
N
N
Display Write Inhibit/Blanking
I
Clear
End Interrupt/Error Mode Set
I
FIFO Status
F 91
l~J1i:~-i
H~~G
~-15. ~
I
.
K
I
A
M
(Plastic)
ITEM
MILLIMETERS
A
51.5 MAX
INCHES
2.02BMAX
1.62
0.064
C
2.54:! 0.1
0.10 ± 0.004
0
0.5 ± 0.1
0.019 ± 0.004
B
E
4B.26
1.9
0.047 MIN
F
1.2 MIN
G
H
2.54 MIN
0.10 MIN
0.5MIN
0.019 MIN
5.22 MAX
5.72 MAX
0.20'6 MAX
I
J
K
15.24
L
13.2
M
0.225 MAX
0.600
0.520
0.25 + 0.1
0.05
0.010
+ 0.004
0.002
8279-5DS-R EV 1-1 ~82-CAT
701
NOTES
702
NEe
JlPB8282
JlPB8283
NEe Electronics U.S.A. Inc.
Microcomputer Division
OCTAL LATCH
DESCRIPTION
FEATURES
The j,LPB8282/8283 are 8-bit latches with tri-state output buffers. The 8282 is noninverting and the 8283 inverts the input data. "These devices are ideal for demuxing
the address/data buses on the 8085A/8086 microprocessors.
The 8282/8283 are fabricated using NEC's Schottky bipolar process.
• Supports 8080, 8085A, 8048; 8086 Family Systems
•
•
•
•
•
Tnmsparent During Active Strobe
FLilly Parallel 8-Bit Data Register and Buffer
High Output Drive Capability (32 mAl for Driving the System Data Bus
Tri.State Outputs
20-Pin Package
01 0
01 1
; vee
01 0
01 1
vee
000
01 2
001
01 2
0°1
000
01 3
0°2
01 3
0°2
01 4
003
01 4
003
01 5
004
01 5
004
01 6
; 0°5
01 6
005
006
01 7
; 006
01 7
OE
007
OE
007
GNO
STB
GNO
STB
PIN NAMES
FUNCTIONAL
DESCRIPTION
01 0- 01 7
OATAIN
0°0 0 °7
OATA OUT
DE
OUTPUT ENABLE
STB
STROBE
The pPB8282/8283 are 8-bit latches with tri-state output buffers. Data on the inputs
is latched into the data latches on a high to low transition of the STB line. When STB
is high, the latches appear transparent. The OE input enables the latcheddata to be
transferred to the output pins. When OE is high, the outputs are put in the tri-state
condition. OE will not cause transients to appear on the data outputs.
Rev/1
703
J£PB8282/8283
BLOCK DIAGRAMS
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . O°C to 70°C
Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 65°C to +150°C
All Output and Supply Voltages .....
. ... -0.5V to +7V
All Input Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to 5.5V
Ta = 25°C
ABSOLUTE MAXIMUM
RATINGS*
*CQMMENT: Stress above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a strass rating only and functional operation of thedevice at these or
any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to ebsolute maximum rating conditions for extended periods may affect device
reliability .
Conditions: VCC = 5V ± 10% T a = OoC to 70°C
PARAMETER
SYMBOL
MIN
DC CHARACTERISTICS
MAX
TEST CONDITIONS
UNITS
Input Clamp Voltage
Vc
-1
V
Power Supply Current
ICC
160
mA
IC =-5 mA
Forward Input Current
IF
-0.2
mA
VF -O.45V
Reverse Input Current
IR
50
JJA
VR - 5.25V
Output Low Voltage
VOL
Output High Voltage
VOH
Output Off Current
IOFF
Input Low Voltage
VIL
Input High Voltage
VIH
Input Capacitance
CIN
0.45
2.4
±50
O.S
2.0
12
V
IOL - 32 mA
V
IOH --5 mA
JJA
VOFF -0,45to 6.25V
V
V CC=5.0VG)
V
VCC-5.0VQ)
pF
VBIAS=2.5V, VCC=5V
Ta=25°C. F=l MHz
Note:(j) Output Loading IOL - 32 mA, IOH - -5 mA, CL
= 300 pF
704
"PB8282/8283
Conditions: VCC = 5V ± 10%, Ta = O°C to 70°C
AC CHARACTE'RISTICS
Loading: Outputs - IOL = 32 mA, IOH = -5 mA CL = 300 pF
PARAMETER
TIMING WAVEFORMS
SYMBOL
MAX
UNITS
5
22
30
ns
ns
10
10
40
45
ns
ns
5
22
ns
10
30
ns
MI.N
Input to Output Delay
-Inverting
-Non-Inverting
TIVOV
STB to Output Delay
-Inverting
-Non-Inverting
TSHOV
Output Disable Time
TEHOZ
Output Enable Time
TELOV
Input to STB Setup Time
TIVSL
0
Input to STB Hold Time
TSLIX
25
ns
STB High Time
TSHSL
15
ns
5
ns
Input; Output Rise Time
TILIH T OLOH
20
ns
Input, Output Fall Time
TIHIL, T OHOL
12
nw
INPUTS
TSLIX
STB
TEHOZ
OUTPUTS
-&=
TELOV
------
1.6V
l.4V
Note: Output may be momentarily invalid following the lJ.igh going into STB transition.
1.5V
1.5V
OUT~'00n
330
r
OUT
300 pF
300 pF
3-STATE TO VOH
3-STATE TO VOL
AC TESTING INPUT,
OUTPUT WAVEFORM
A.C. TESTING: INPUTS ARE DRIVEN AT 2.4V FOR A LOGIC "1" AND 0.45V FOR
A LOGIC "0" TIMING. MEASUREMENTS ARE MADE AT 1.5V FOR BOTH
A lOGIC "1" AND "0."
705
OUT~4:.m
r
300 pF
SWITCHING
IlPB8282/8283
PACKAGE OUTLINES
IlPB8282C
IlPB8283C
120
1
ITEM
MILLIMETERS
INCHES
A
26.7 MAX.
1.05
2.54
0.5 ± 0.1
22.86
1.4
1.1
2.54 MIN.
0.5MIN.
3.55
5.08 MAX.
7.62
6.4
0.25+0.10
- 0.05
1.0R
1.05 MAX.
0.041
0.1
0.02' 0.004
0.9
0.055
0.043
0.1 MIN.
0.02 MIN.
0.14
0.2 MAX.
0.3
0.25
0.01 + 0.004
-0.002
O.04R
B
G
H
I
J
K
L
M
R
A
11
I
"i::::::::]I
Plastic
C
0
E
F
F'
.
10
IlPB8282D
IlPB8283D
120
.
A
11 1
"i::::::::]L
1
10
eerdip
ITEM
MILLIMETERS
INCHES
A
B
26.7 MAX.
0.7
2.54
0.46 ± 0.1
22.86
1.4
1.05 MAX.
0.028
0.1
0.018 ± 0.004
0.9
0.055
C
o
E
F
P
B9
BroS
G
H
I
J
K
L
M
2.54 MIN.
0.5 MIN.
4.32 MAX.
5.08 MAX.
7.62
6.8
0.25 + 0.10
- 0.05
0.8R
0.1 MIN.
0.02 MIN.
0.17 MAX.
0.2 MAX.
0.3
0.27
0.01 + 0.004
-0.002
0.03R
R
8282/8283DS/R EV 1/-1-82-CA T
706
IlPB8284
NEe
NEe Electronics U.S.A. Inc.
Microcomputer Division
CLOCK GENERATOR AND DRIVER FOR
8086/8088 MICROPROCESSORS
D ESC R I PT I ON
FEATURES
The j.tPB8284 is a clock generator and driver for the 8086 and 8088 microprocessors
This bipolar driver provides the microprocessor with areset signal and also provides
properly synchronized READY timing. A TTL clock is also provided for peripheral
devices.
• ,Generate System Clock for the 8086 and 8088
• Frequency Source can be a Crystal or a TTL Signal
• MOS [evel Output for the Processor
'. TTL Level Output for Peripheral Devices
• Power·Up Re~et for the ProceSsor
• READY Synchronization
'. +5V Supply
• 18 Pin Package
PIN NAMES
PIN CONFIGURATION
Xl. X2
CYSNC
VCC
Crystal Connections
TANK
For Overtone Crystal
FIC
Clock Source Select
PClK
Xl
EFI
External Clock Input
AEi\i1
X2
CSYNC
Clock Synchronization Input
RDYl
TNK
RDY1}
RDY2
Ready Signal from
READY
EFI
Address Enable Qualifiers
Multibus TM * Systems
RQY2
Fie
~}
AEN2
for the two ROY Signals
A"EN"2
OSC
RES
Reset Input
ClK
REs
RESET
Synchronized Reset Output
GND
RESET
OSC
Oscillator Output
ClK
MOS Clock for the Processor
PClK
TTL Clock for Peripherals
READY
Synchronized Ready Output
*TM· Multibus is a tra'demark of Intel Corporation.
Rev/1
707
"PB8284
PIN IDENTIFICATION
PIN IDENTIFICATION
NO.
SYMBOL
NAME
FUNCTION
1
CSYNC
Clock Synchronization
An active high signal which allows
multiple 8284s to be synchronized.
When CYSNC is low, the internal
counters count and when high the
counters are reset. CYSNC should
be grounded when the internal
oscillator is used.
2
PCLK
Peripheral Clock
A TTL level clock for use with peripheral devices. This clock is onehalf the frequency of ClK.
3, 7
AEN1, AEN2
Address Enable
This active low signal is used to
qualify its respective RDY inputs.
If there is only one bus to interface
to, AEN inputs are to be grounded.
4,6
RDY1, RDY2
Bus Ready
This signal is sent to the 8284 from
a peripheral device on the bus to
indicate that data has been received
or data is available- to be read.
5
READY
Ready
The READY signal to the microprocessor is synchronized by the
RDY inputs to the processor elK.
READY is cleared after the guaranteed hold time to the processor has
been met.
8
ClK
Processor Clock
This is the MOS level clock output
of 33% duty cycle to drive the
microprocessor and bipolar support
devices (8288) connected to the
processor. The frequency of elK is
one third of the crystal or EFI
frequency.
10
RESET
Reset
This is used to initialize the processor. Its input is derived from an RC
connection to a Schmitt trigger
input for power up operation.
11
RES
Reset In
This Schmitt trigger input is used to
determine the timing of RESET out
via an RC circuit.
12
ose
Oscillator Output
This TTL level clock is the output
of the oscillator circuit running at
the crystal frequency.
13
FIe
Frequency Crystal Select
FIe is a strapping oPtion used to
determine where ClK is generated.
A high is for the EFI input, and a
low is for the crystal.
14
EFI
External Frequency In
A square wave in at three times the
elK output. A TTL level clock to
generate elK.
Xl, X2
Crystal In
A crystal is connected to these
inputs to generate the processor
clock_ The crystal chosen is three
times the desired elK output.
15
TNK
Tank
This is used for overtone type
crystals. (See diagram below.)
18
vce
vce
+5V
16,17
708
IlPB8284
BLOCK DIAGRAM
~------------------------------~
RESET
~---~~------__4 ~-------~-----------OSC
.----------.-CLK
F/C--_ _-4
"""!~-----------Jlfi.
EFI-------------------L~
PCLK
CSYNC------------------------------~~----_+----~
CK
RDY1---------------~=====r~
Arni------:=----I
Q I------~_
~-----ID
READY
A"'E"N'2
RDY2 ______________
ABSOLUTE MAXIMUM
RATINGS*
~
0
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . oOe to 70 e
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65° e to +150° e
All Output and Supply Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V
All Input Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to +5.5V
*COMMENT: Stress above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
DC CHARACTE R ISTICS
Conditions: Ta = DoC to 70°C; VCC = 5V ± 10%
SYMBOL
PARAMETER
MIN
MAX
UNIT
TEST
CONDITIONS
Forwar,d Input Current
IF
-0.5
mA
VF = 0.45V
Reverse Input Current
IR
50
J.1A
VR = 5.25V
Input Forward Clamp Voltage
Vc
-1.0
V
IC=-5mA
Power Supply Current
ICC
Input low Voltage
VIL
V
VCC = 5.0V
Input High Voltage
V!H
2.0
V
VCC = 5.0V
Reset Input High Voltage
VIHR
2.6
V
VCC= 5.0V
Output low Voltage
VOL
V
5 rnA =IOl
Output High Voltage ClK
Other Outputs
VOH
4
2.4
V
V
-1 rnA}
-1rnA IOH
RES Input Hysteresis
VIHR,VllR
0.25
V
VCC = 5.0V
709
140
0.8
0.45
rnA
IlPB8284
The clock generator can provide the system clock from either a crystal or an external
TTL source. There is an internal divide by three counter which receives its input from
either the crystal or TTL source (EFI Pin) depending on the state of the Fie input
strapping. There is also a clear input (C SYNC) which is used for either inhibiting the
clock, or synchronizing it with an external event (or perhaps another clock generator
chip). Note that if the TTL input is used, the crystal oscillator section can still be used
for an independent clock source, using the OSC output.
FUNCTIONAL DESCRIPTION
For driving the MOS output level, there is a 33% duty cycle MOS output (ClK) for the
microprocessor, and a TTL output (PClK) with a 50% duty cycle for use as a peripheral
clock signal. This clock is at one half of the processor clock speed.
Reset timing is provided by a Schmitt Trigger input (R ES) and a flip-flop to synchronize
the reset timing to the falling edge of ClK. Power-on reset is provided by a simple RC
circuit on the RES input.
There are two READY inputs, each with its own qualifier (AEN1, AEN2). The unused
AEN signal should be tied low.
The READY logic in the 8284 synchronizes the RDY1 and RDY2 asynchronous inputs
to the processor clock to insure proper set up time, and to guarantee proper hold time
before clearing the ready signal.
~--- osc
X1
CJ
~
3 TO 10pF
........- - - ClK
........- - - PClK
X2
8284
VCC
r
~
~
t----RESET
TANK
1
r - - - - - - - · - - - ---,
I
I
I
IL
l
1
f
= 2"
JlCT
I
I
USED WITH OVERTONE
CRYSTALS ONLY
CBP I.
CTI . I
~ ____
~_ _ JI
_______
The tank input to the oscillator allows the use of overtone mode crystals.
The tank circuit shunts the crystal's fundamental and high ovartone frequencies and allows the third harmonic to oscillate. The external LC network is connected to the TANK input and is AC coupled to ground.
710
TANK INSERT
CIRCUIT DIAGRAM
"PB8284
AC CHARACTE R ISTICS
Conditions: Ta
=
O·C to 70·C; VCC
=
5V ± 10%
TIMING REQUIREMENTS
PARAMETER
SYMBOL
MIN
MAX
UNITS
TEST
CONDITIONS
External Frequency High Time
TEHEL
13
ns
External Frequency Low Time
TELEH
13
ns
90%-90% VIN
10%-10% VIN
EFI Period
TElEl
ns
----------10
RESET
t----------- ClK
EFI---========C)l.PClK
CSYNC--------------~----------------+_----+_--~
ROY1--------------~--~~
Am'l-----=-----4
!-----_REAOY
AErii2
RDY2----~~-----Ilr--~~
~----------------~
ABSOLUTE MAXIMUM
RATINGS*
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . O°C to 70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65° C to +150° C
All Output and Supply Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V
All Input Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to +5.5V
*COMMENT: Stress above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions above· those indicated in the oparational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
DC CHARACTERISTICS
Conditions: Ta = O°C to 70°C; VCC = 5V ± 10%
PARAMETER
SYMBOL
MIN
MAX
UNIT
TEST
CONDITIONS
Forward Input Current
IF
-0.5
mA
VF = 0.45V
Reverse Input Current
IR
50
pA
VR = 5.25V
Input Forward Clamp Voltage
Vc
V
IC =-5 mA
Power Supply Current
ICC
-1.0
140
mA
Input Low Voltage
V,L
V
VCC = 5.0V
Input High Voltage
V,H
2.0
V
VCC = 5.0V
2.6
V
VCC = 5.0V
0.8
Reset Input High Voltage
V,HR
Output Low Voltage
VOL
V
5 mA =IOl
Output High Voltage ClK
Other Outputs
VOH
4
2.4
V
V
-1 mA}
-lmA IOH
RES Input Hysteresis
VIHR-VILR
0.25
V
VCC = 5.0V
717
0.45
"PB8284A
The clock generator can provide the system clock from either a crystal or an external
TTL source. There is an internal divide by three counter which receives its input from
either the crystal or TTl'source (EFI Pin) deperiding on the state of the Fie input
strapping. There is also a clear input (C SYNC) which is used for either inhibiting the
clock, or synchronizing it with an external event (or perhaps another clock generator
chip). Note that if the TTL input is used, th~ crystal oscillator section can still be used
for an independent clock source, using the OSC output.
FUNCTIONAL DESCRIPTION
For driving the MOS output level, there is a 33% duty cycle MOS output (ClK) for the
microprocessor, and a TTL output (PClK) with a 50% duty cycle for use as a peripheral
clock signal. This clock is at one half of the processor clock speed.
Reset timing is provided by a Schmitt Trigger input (m) and a flip-flop to synchronize
the reset timing to the falling edge of ClK. Power-on reset is provided by a simple RC
circuit on the RES input.
There are two READY inputs, each with its own qualifier (AEN1, AEN2). The unused
AEN signal should be tied low.
The READY logic in the 8284A synchronizes the RDY1 and RDY2 asynchronous inputs
to the processor clock to insure proper set up time, and to guarantee proper hold time
before clearing the ready signal.
Conditions: Ta
Z
O°C to 70°C; VCC
a
5V ± 10%
AC CHARACTERISTICS
'TIMING REQUIREMENTS
PARAMETER
External Frequency High Time
SYMBOL
External Frequency Low Time
TEHEL
TELEH
EFI Period
TELEL
XTAl Frequency
TR1VCl
TCLR1X
MAX
UNITS
ns
ns
13
13
TEHEL+TELEH+6
12
ROY1, ROY2 Hold to ClK
ROY1, ROY2 Set-Up to ClK
MIN
ns
25
35
ns
0
ns
AEN1, AEN2 Set-Up to ROY1, ROY2
TA1VR1V
15
ns
AEN1, AEN2 Hold to ClK
TClA1X
TYH,EH
0
ns
20
ns
CSYNC Hold to EFI
TEHYl
CSYNC Width
RES Set-Up to ClK
RE_S Hold to ClK
ROY1, ROY2 Active Set-Up to ClK
ROY1, ROY2 Inactive Set-Up to ClK
TYHYl
TI1HCl
20
2 TElEl
65
20
35
35
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ASYNC Set-Up to ClK
ASYNC Hold to ClK
Input Rise Time
Input Fall Time
tR1VCH
tR1VCl
tAYVCl
tClAYX
lJllH
tlLll
0
20
12
718
90%-90% VIN
10%-10% VIN
(1)
MHz
CSYNC Set-Up to EF I
TCLl1H
TEST
CONDITIONS
(2)
_(!2
ASYNC = lOW
From O,BV to 2.0V
From 2.0V to O.BV
IlPB8284A
AC CHARACTERISTICS
(CONT.)
TIMING RESPONSES
PARAMETER
C lK Cycle Period
ClK High Time
ClK low Time
ClK Rise and Fall Time
PClK High Time
PClK low Time
(4J
Ready Inactive to ClK
(3)
Ready Active to ClK
ClK To Reset Delay
ClK to PClK High Delay
ClK to PClK low Delay
OSC to ClK High Delay
OSC to ClK low Delay
Output Rise Time (except ClKl
Output Fall Time (except ClKl
Notes:
16
SYMBOL
TClCl
TCHCl
TClCH
TCH1CH2
TCl2Cl1
TPHPl
TPlPH
TRYlCl
TRYHCH
TCLIl
TClPH
TClPl
TOlCH
TOlCL
tOlOH
.tOHOl
MIN
UNITS
TEST
CONDITIONS
ns
ns
ns
Figure 3 and Figure4
Figure 3 and Figure 4
10
ns
1.0V to 3.5V
40
22
22
12
22
20
12
ns
n.
ns
ns
n.
ns
ns
ns
ns
ns
n.
MAX
125
(1/3 TClCll +2.0
(2/3 TClCll-15.0
TClCl -20
TClCl -20
-8
(2/3 TClCll-15.0
-5
2
Figure 5 and Figure 6
Figure 5 and Figure 6
From 0.8V to 2.0V
From 2.0V to 0.8V
= EFI rise (5 ns max) + EFl fall (5 ns maxI.
Set up and hold only necessary to guarantee recognition at next clock.
Applies only to T3 and TW states.
4 Applies only to T2 states.
TIMING WAVEFORM*
~I----~-- .~--~--''---~~~'~--~--------------~----------_r-----
READVO!_-I-__ ..I-I--+_ _ _ _ _--4Ir----+--...,\.._ _ _ _
~-----_r--
"All TIMING MEASUREMENTS ARE MADE AT 1.5V UNLESS OTHERWISE NOTED.
719
IlPB8284A
v C
AC TEST CI RCUITS
FIr:
~PF
X,
24MHlc:::J
FIGURE.2
CLOCK HIGH AND lOW TIME
FIGURE 1
CLOCK HIGH AND lOW TIME
FIGURE 4
READY TO ClK
FIGURE 3
READY TO ClK
TEST
POINT
. LOAD
VCC
ALL DIODES 1N3064
OR EaUIVALENT
OUTPUT
NOTES:
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