1982_National_COPS_Microcontrollers 1982 National COPS Microcontrollers
User Manual: 1982_National_COPS_Microcontrollers
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COPS
MICROCONTROLLERS
DATABOOK
NATIONAL
SEM ICON DUCTOR
CORPORATION
Introduction COPS Family
Single-Chip Microcontrollers
1"11"" •• 1 _ _ _
• • ~ ________ 1
___
11____
nv IVI":'~~ IVI.". U"UII LI UII~I::»
Piggyback Microcontrollers
MICROWIRE™ Peripherals
Standard Controllers
EPROMs and Support Circuits
Development Systems and User's Manuals
COPS Application
AppendiX/Physical Dimensions
i.
#P-II
_ __
~
LIFE SUPPORT POLICY
NATIONAl.:8 PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and whose failure to
perform, when properly used in accordance with in·
structions for use provided in the labeling, can be rea·
sonably expected to result in a significant injury to the
user.
2. A critical component is any component of a life support
device or system whose failure to perform can be rea·
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
TRI·STATE is a registered trademark of National Semiconductor Corp.
COPS, ISE, MICROBUS, MICROWIRE, STARPLEX and STARPLEX" are trademarks of National
Semiconductor Corp.
ii.
The COPSTM Family
The COPS Family of microcontrollers provides a
flexible, cost-effective system solution in applications
requiring timing, counting or other control functions_
COPS can be used to replace discrete logic in highvolume consumer products and low-volume industrial
products allowing you to add features, miniaturize and
reduce component count.
Standard peripherals inexpensively add distributed
processing and unique capabilities. Two of these
devices are of special interest for their ability to
increase speed and reduce power requirements. The
COP452 Frequency/Counter assists the processor in
handling high-frequency information, increasing
system speed by a factor of up to 100. The COP498
RATTM Chip (CMOS RAM and Timer) allows the CPU to
"sleep" and "wake up" under software control,
reducing an NMOS controller's power consumption to
a level approaching CMOS controllers at a much lower
system cost. Both of these devices have other capabilities that are detailed in their respective data
sheets.
All of the programmable microcontrollers in the COPS
Family share a common architecture, pin-out and
instruction set, so that once you have programmed
one, you can design with the entire family. I n addition,
compatible standard peripherals and pre-programmed
microcontrollers can add extra capability to your
design at off-the-shelf prices.
MICROWIRETM makes effiCient use of every I/O line.
The COPS Family is designed with National's MICROWIRE system, which permits serial data exchange with
only three wires_ This reduces 1/0 lines, enabling the
use of a more cost-effective package (i.e., fewer
number of pins) or the addition of more features and
capability to your final product.
National Semiconductor recognized the need for a
family of controllers that would grow with our customers' needs. The COPS Family, with its programming
and cost efficiency, versatility and ease of development is at the leading edge of technology. We are committed to keeping it there by continually phasing in
new design concepts and fabrication methods. This
systematic evolution brings you state-of-the-art
devices to drive your products into the future.
cops: Design Flexibility
Never before have so many options been available
with a common architecture and pin-out. Once you
choose the COPS Family, any of the following options
can be selected or modified during the product development cycle:
COPS devices are produced on some of the largest
fabrication lines in the semiconductor industry.
Located around the world, these lines actually
"second source" each other, ensuring you a steady
supply of products when you need them. Availability,
combined with the money that is saved by not having
to retrain from one product to the next, has made the
COPS Family a standard for many companies.
• Capacity. Memories range from 0.5 k ROM and
32 x 4-bit RAM to 4k ROM and 256 x 4-bit HAM. The
2k ROM-size devices are available with either single
or dual CPUs.
cops: Cost-efficiencv
•
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ho
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the optimum process technology for any application, from high-speed NMOS to low-power NMOS to
very low-power CMOS. And operating temperature
ranges are available from -55°C to +125°C.
The COPS Family was designed with efficiency in
mind. The more the controller can do, the greater are
your product alternatives. Several approaches have
been taken to allow you to add capability to your
products while lowering costs:
• Mask-programmable options. Several options can
be masked onto COPS devices simultaneously with
the user's program. They include up to four basic
clock oscillators, as well as an array of 1/0 configurations (i.e., LED drive, open-drain and TRI-STATE'"
circuitry). In addition, COPS devices can serve as
"smart" microprocessor peripherals by selecting
the MICROBUSTM option, National's standard interconnect for 8-bit data transfer_
We've designed the industry's most ROM-efficient
instruction set. Every COPS microcontroller uses the
same ROM-efficienct instruction set, which often
requires significantly less ROM to carry out a set of
tasks than with other 4- or even 8-bit devices. As your
program develops and you find that you require less
(or more) ROM than you originally anticipated, you can
easily go to other COPS devices-of larger or smaller
ROM size-without starting over.
cops: Development Ease
Our dual CPUs are an economical alternative to bigger
memories. National is the first to develop an architecture that permits two CPUs to be placed onto a single
device. Speed is increased because one CPU can process regular events while the other handles random
tasks, eliminating the need to shuffle back and forth
between diverse, time-critical operations_ Since both
CPUs access common memories, program efficiency
is virtually doubled at little extra cost.
The COPS Family places a variety of tools and professional support at your disposal to make designing
easier. Several alternatives are available to you,
depending on your in-house capabilities, product mix
and marketing strategies. Regardless of which path
you choose, National Semiconductor's field and factory applications specialists are available throughout
the design process.
iii.
• COP400 Product Development System (PDS). This
powerful, easily understood programming system
performs complex software development and debug
tasks with a minimum of effort-and investment.
You interact with the system via a teletype or CRT
console and can attach a printer for fast program
listings. Data is stored on a floppy diskette for fast,
easy access and for convenience in providing
National with the mask program. A real-time insystem emulator board allows you to develop and
debug your COPSTM device from within your
hardware environment.
range of programmable products.
• Prototyping. ROM less or piggyback COPS devices
can be interfaced with a standard PROM to facilitate
development and debugging, particularly when premarket testing is desirable prior to masking the final
part. They can also provide an effective alternative to
mask-programming in low-volume applications or
when your competitive environment demands fast
product modifications.
o
National's complete PDS training course will teach
you how to develop all of your products with the
COPS Family. So if your company needs to develop
in-house design capabilities for a minimal capital
outlay, PDS makes a lot of sense.
National's COPS Controller Engineering Group.
New companies, or those with little time or in-house
design expertise, can take advantage of our Controller Engineering Group. These professionals will put
their vast COPS programming and applications experience to work in implementing your specifications into a COPS-controlled system.
A Mutual Commitment
• The COPS In-System Emulator (lSETM) Package is
for companies who already own, or are considering,
a STARPLEXTM Development System. A target board
plugs directly into any STARPLEX or STARPLEX WM
system, giving it virtually the same diskette storage
and real-time emulation capabilities as the COP400
PDS. The powerful STARPLEXsystem also supports
National's state-of-the-art programmable microprocessors, making it ideal if your company uses a wide
National Semiconductor has committed extensive
design and fabrication resources to providing you with
a steady stream of cost-effiCient, flexible, easily developed COPS devices. This data book will help familiarize you with the many alternatives that are currently
available to help you bring your ideas to market.
iv.
Section 1 Introduction COPS Family
COPSTM Microcontroller Family Guide .................................... 1-3
COPS ROM less Microcontroller Family Guide ............................ 1-3
Section 2 Single·Chip Microconlroliers
COP410C/COP411C, COP310C/COP311C
Fully Static, Single·Chip CMOS Microcontrollers ......................... 2-3
COP410LlCOP411 L, COP310LlCOP311 L
Single·Chip N·Channel Microcontrollers ................................ 2-5
COP420/COP421/COP422, COP320/COP321/COP322
.
Single·Chip N·Channel Microcontrollers ............................... 2-23
COP420C/COP421C, COP320C/COP321C
Single·Chip CMOS Microcontrollers ................................... 2-45
COP420LlCOP421 LlCOP422L, COP320LlCOP321 LlCOP322L
Single·Chip N·Channel Microcontrollers ............................... 2-64
COP440/COP441/COP442, COP340/COP341/COP342
Single·Chip N·Channel Microcontrollers ............................... 2-88
COP444C/COP445C, COP344C/COP345C
Single·Chip CMOS M icrocontrollers .................................. 2-111
COP444L1COP445L, COP344L1COP345L
Cln"l .... ,...h: ...... I'rI.ll"'h ................. 1 lA: ...................... _.&. ...... II ..... __
. .. _..... _._-_ .... _..._._ .............................. COP464 and COP484 Single·Chip 3k and 4 k Microcontrollers ............... 2-134
.
..
COP2440/COP2441/COP2442, COP2340/COP2341/COP2342
Single·Chip Dual CPU Microcontrollers ............................... 2-135
Section 3 ROMless MicrocontrolJers
COP401L ROMless N·Channel Microcontroller ............................. 3-3
COP402/COP402M, COP302/COP302M
ROM less N·Channel Microcontrollers ................................. 3-17
COP404/COP304 ROM less N·Channel Microcontrollers .................... 3-36
COP404L1COP304L ROM less N·Channel Microcontrollers .................. 3-46
COP2404/COP2304 ROM less Dual CPU Microcontrollers ................... 3-65
Section 4 Piggyback Microcontrollers
COP420R/COP444LR Piggyback-EPROM Microcontroller ................... 4-3
COP440R/COP2440R Piggyback-EPROM Microcontroller ................... 4-18
v.
Table of Contents (continued)
Section 5 MICROWIRETM Peripherals
COP431, COP432, COP434, COP438 8-Bit Serial I/O AID Converters
with Multiplexer Options ............................................. 5-3
COP452/COP453, COP352/COP353 Frequency Generator and Counter ........ 5-13
COP470, COP370 V. F. Display Driver .................................... 5-44
. COP472 Liquid Crystal Display Controller. ............................... 5-51
COP498/COP398 Low Power CMOS RAM and Timer (RATTM),
COP499/COP399 Low Power CMOS Memory ........................... 5-58
DS8906 AM/FM Digital Phase-Locked Loop Synthesizer .................... 5-70
DS8907 AM/FM Digital Phase-Locked Loop Frequency Synthesizer ........... 5-76
DS8908 AM/FM Digital Phase-Locked Loop Frequency Synthesizer ............ 5-82
MM5445, MM5446, MM5447, MM5448 VF Display Drivers .................... 5-89
MM5450, MM5451 LED Display Drivers ................................... 5-92
MM5452, MM5453 Liquid Crystal Display Drivers .......................... 5-97
MM5480 LED Display Driver. ...•...................................... 5-102
MM5481 LED Display Driver. .......................................... 5-105
MM5484, MM548516-, 11-Segment LED Display Drivers .................... 5-108
MM58201 Multiplexed LCD Driver ...................................... 5-111
MM58248, MM58241 High Voltage Display Drivers ......................... 5-116
MM58348, MM58341 High Voltage Display Drivers ......................... 5-119
Section 6 Standard Controllers
MM57409 Super Number Cruncher ....................................... 6-3
MM57436 Decimal/Binary Up/Down Counter. .............................. 6-6
MM57455 Advanced Educational Arithmetic Game ......................... 6-13
MM57459 8-Digit LED Direct-Drive Memory Calculator ...................... 6-16
Section 7 EPROMS and Support Circuits
MM2716 16,384-Bit (2048 x 8) UV Erasable PROM ..... , ..................... 7-3
"NMC27C1616,384-Bit (2048K8) UV Erasable CMOS PROM ................... 7-9
MM2758 8192-Bit (1024 x 8) UV Erasable PROM ............................ 7-15
MM54C373/MM74C373 TRI-STATE@ Octal D-Type Latch
MM54C374/MM74C374 TRI-STATE Octal D-Type Flip-Flop ................. 7-21
DM54LS373/DM74LS373, DM54LS374IDM74LS374 Octal D-Type
Transparent Latches and Edge-Triggered Flip-Flops ...................... 7-27
vi.
Table of Contents (continued)
Section 8 Development Systems and User's Manuals
COP400-PDS Product Development System ............................... 8-3
COP400 Product Development System User's Manual ....................... 8-5
COP400 In-System Emulator Boards User's Manual ....................... 8-113
STARPLEXTM Development System .................................... 8-134
STARPLEX WM Development System ................................... 8-141
COPSTM In-System Emulator (ISETM) Package ............................. 8-157
STARPLEX COPS Cross-Assembler User's Manual .................... 8-163
SPM-A15, SPM90/A15 COP400 Emulator User's Manual .................... 8-240
Section 9 COPS Application
COPSTM Family User's Guide ............................................ 9-3
COP Note 1 Analog to Digital Conversion Techniques With COPSTM
Family Microcontrollers ................................. 9-78
COP Note 2 COPSTM Television Controller. ............................. 9-113
COP Note 3 Design Considerations for a COP420C-Based
Telephone-Line Powered Repetory Dialer .................. 9-118
COP Note 4 The COP444L Evaluation Device 444L-EVAL. ................ 9-123
COP Note 5 Oscillator Characteristics of COPSTM Microcontrollers ......... 9-128
COP Note 6 Triac Control Usino the COP400 Microcontroller Familv ........ 9-152
COP Note 7 Testing of COPSTM Chips ................................. 9-159
COP Brief 1 SIO Input/Output RegisterDescription ...................... 9-166
COP Brief 2 Easy Logarithms for COP400 .............................. 9-168
COP Brief 3 Use of Macro-Assembled Code ............................ 9-179
COP Brief 4 Bus Considerations ..................................... 9-181
COP Brief 5 Software and Opcode Differences in the COP444L
Instruction Set ........................................ 9-182
COP Brief 6 RAM Keep-Alive ......................................... 9-183
COP Brief 7 MICROBUSTM Programming Considerations ................. 9-184
COP Brief 8 COPSTM Peripheral Chips .............................. , .. 9-185
COP Brief 9 Serial Interface Between COPsn~ Microcontrollers
and Peripheral Chips .................................. 9-187
COP Brief 11 Power Seat with Memory ...................... : .......... 9-189
COP Brief 12 An Automotive Diagnostics Display ........................ 9-193
COP Brief 13 An Electronic Speedometer and Odometer with Permanent
Mileage Accumulation ................................. 9-195
COP Brief 14 COP420C Voltage, Current, and Frequency .................. 9-201
Section 10 Appendix
COP420-HGZ/N Preprogrammed Single·Chip Microcontroller for Musical Organ10-3
COP420L-HSB Digital Tuning System Controller: .... : ..................... 10-5
Ordering Information/Physical Dimensions .............................. 10-10
vii.
Alphanumerical Index
COP302
COP302M
COP304
COP304L
COP310C
COP310L
COP311C
COP311 L
COP320
COP320C
COP320L
COP321
COP321C
COP321 L
COP322
COP322L
COP340
COP341
COP342
COP344C
COP344L
COP345C
COP345C
COP352
COP353
COP370
COP398
COP399
COP401L
COP402·
COP402M
COP404
COP404L
COP410C
COP410L
COP411 C
COP411 L
COP420
COP420C
CO'P420L
ROMless N-Channel Microcontrollers .......................... 3...:17
ROM less N-Channel Microcontrollers .......................... 3-17
ROM less N-Channel Microcontro.llers ......................... 3-36
ROM less N-Channel Microcontrollers ......................... 3-46
Fully Static, Single-Chip CMOS Microcontroller .................. 2-3
Single-Chip N-Channel Microcontroller ...................•..... 2-5
Fully Static, Single-Chip CMOS Microcontroller .................. 2-5
Single-Chip N-Channel Microcontroller ......................... 2-.5
Single-Chip N-Channel Microcontroller ........................ 2-23
Single-Chip CMOS Microcontroller ............................ 2-45
Single-Chip N-Channel Microcontroller ........................ 2-64
Single-Chip N-Channel Microcontroller ........................ 2-23
Single-Chip CMOS Microcontroller ............................. 2-45
Single-Chip N-Channel Microcontroller. ....................... 2-64
Single-Chip N-Channel Microcontroller .... ' .... ; ............... 2-23
Single-Chip N-Channel Microcontro.ller. .......... , ............ 2-64
Single-Chip N-Channel Microcontroller ........................ 2-88
Single-Chip N-Channel Microcontroller ........................ 2-88
Single-Chip N-Channel Microcontroller ........................ 2-88
Single-Chip CMOS Micro.controller ........................... 2-111
Single-Chip N-Channel Microcontroller ................ : ....... 2-112
Single-Chip CMOS Microcontroller ........................... 2-111
Single-Chip N-Channel Micro.controller. ....................... 2-112
Frequency Generator and Counter .......................•.... 5-13
Frequency Generator and Cou.nter ............................ 5-13
V. F. Display Driver ....................................... '," .5-44
Low Power CMOS RAM and Timer (RATTM) ...................... 5-58
Low Power CMOS Memory .............................. : .... 5-58
ROM less N-Channel Microcontroller. .......................... 3-3
ROM less N-Channel Microcontroller ........................... 3-17
ROMless N-Channel Microcontroller ........................... 3-17
ROM less N-Channel Microcontroller .......................... 3-36
ROM less N-Channel Microcontroller .......................... 3-46
Fully Static, Single-Chip CMOS Microcontroller .................. 2-3
Single-Chip N·Channel Microcontroller. ........................ 2-5
Fully Static, Single-Chip CMOS Microcontroller .................. 2-3
Single-Chip N-Channel Microcontroller ......................... 2-5
Single-Chip N-Channel Microcontroller ........................ 2-23
Single-Chip CMOS Microcontro.ller. .... : ...................... 2-45
Single-Chip N-Channel Microcontroller ........................ 2-64
viii.
Alphanumericai index (continued)
COP420R
COP421
COP421C
COP421 L
COP422
COP422L
COP431
COP432
COP434
COP438
COP440
COP440R
COP441
COP442
COP444C
COP444L
COP444LR
COP445C
COP445L
Piggyback-EPROM ........................................ 4-3
Single-Chip N-Channel Microcontrolier ...................... 2-23
Single-Chip CMOS Microcontroller .......................... 2-45
Single-Chip N-Channel Microcontrolier ...................... 2-64
Single-Chip N-Channel Microcontrolier ...................... 2-23
Single-Chip N-Channel Microcontrolier ...................... 2-64
8-Bit Serial 110 AID Converter ................................ 5-3
8-Bit Serial 110 AID Converter with Multiplexer Options ........... 5-3
8-Bit Serial 110 AID Converter with Multiplexer Options ........... 5-3
8-Bit Serial 110 AID Converter with Multiplexer Options ........... 5-3
Single-Chip N-Channel Microcontrolier ....................... 2-88
Piggyback-EPROM Microcontrolier. ......................... 4-18
Single-Chip N-Channel M icrocontrolier. ...................... 2-88
Single-Chip N·Channel Microcontrolier ....................... 2-88
Single-Chip CMOS Microcontroller .......................... 2-111
Single-Chip N-Channel Microcontrolier ...................... 2-112
Piggyback-EPROM M icrocontrolier .......................... 4-3
Single·Chip CMOS Microcontroller .......................... 2-111
Single·Chip N-Channel Microcontrolier ...................... 2-112
t:'ro.",II.ont"'\I r-.onor~tl"\1'· !::Inn r.:nllntor'
COP453
COP464
COP470
COP472
COP484
COP498
COP499
COP2304
COP2340
COP2341
COP2342
COP2404
COP2440
COP2440R
COP2441
COP2442
DM54LS373
DM54LS374
DM74LS373
DM74LS374
~_1~
Frequency Generator and Counter ........................... 5-13
Single-Chip 3k Microcontrolier ............................. 2-134
V. F. Display Driver ........................................ 5-44
Liquid Crystal Display Controlier ............................ 5-51
Single·Chip 4k Microcontrolier ............................. 2-134
Low Power CMOS RAM and Timer (RApM) .................... 5-58
Low Power CMOS Memory ................................. 5-58
ROMless Dual CPU Microcontrolier. ......................... 3-65
Single-Chip Dual CPU Microcontrolier ....................... 2-135
Single-Chip Dual CPU Microcontrolier ....................... 2-135
Single-Chip Dual CPU Microcontrolier ....................... 2-135
ROM less Dual CPU M icrocontrolier. ......................... 3-65
Single-Chip Dual CPU Microcontrolier ....................... 2-135
Piggyback-EPROM Microcontrolier .......................... 4-18
Single-Chip Dual CPU Microcontrolier ....................... 2-135
Single-Chip Dual CPU Microcontrolier ....................... 2-135
Octal D-Type Transparent Latch and Edge-Triggered Flip-Flop .... 7-27
Octal D-Type Transparent Latch and Edge-Triggered Flip-Flop .... 7-27
Octal D-Type Transparent Latch and Edge-Triggered Flip-Flop .... 7-27
Octal D-Type Transparent Latch and Edge-Triggered Flip-Flop .... 7-27
ix.
Alphanumerical Index (continued)
DS8906
DS8907
DS8908
- MM2716
MM2758
MM5445
MM5446
MM5447
MM5448
MM5450
MM5451
MM5452
MM5453
·MM5480
MM5481
MM5484
MM5485
MM57409
MM57436
MM57455
MM57459
MM58201
MM58241
MM58248
MM58341
MM58348
MM54C373
MM54C374
MM74C373
MM74C374
NMC27C16
AM/FM Digital Phase-Locked Loop Synthesizer __ .. _........... 5-70
AM/FM Digital Phase:Locked Loop Frequency Synthesizer ...... 5-76
AM/FM Digital Phase-Locked Loop Frequency Synthesizer ...... 5-82
16,384-Bit (2048 x 8) UV Erasable PROM ....................... 6-3
8192-BIt (1024 x 8) UV Erasable PROM ........................ 7-15
V. F. Display Driver ................. , ...................... 5-89
V. F. Display Driver ........................................ 5-89
V. F. Display Driver ........................................ 5-89
V. F. Display Driver ........................................ 5-89
LED Display Driver .............. , .................. ; ...... 5-92
LED Display Driver ........................................ 5-92
Liquid Crystal Display Driver ............................... 5-97
Liquid Crystal Display Driver ............................... 5-97
. LED Display Driver ....................................... 5-102
LED Display Driver ....................................... 5-105
16-Segment LED Display Driver ............................. 5-108
11-Segment LED Display Driver. ............................ 5-108
Super Number Cruncher .................................... 6-3
Decimal/Binary Up/Down Counter. .......... '.' ............... 6-6
Advanced Educational Arithmetic Game ...................... 6-13
8-Digit LED Direct-Drive Memory Calculator. .................. 6-16
Multiplexed LCD Driver. .................................. 5-111
High Voltage Display Driver. ............................... 5':'116
High Voltage Display Driver ................................ 5-116
High Voltage Display Driver ................................ 5-119
High Voltage Display Driver ................................ 5-119
TRI-STATE@ Octal D-Type Latch. ~ ........................... 7-21
TRI-STATE@ Octal D-Type Flip-Flop ........................... 7-21
TRI-STATE@ Octal D-Type Latch ............................. 7-21
TRI-STATE@ Octal D-Type Flip-Flop ........................... 7-21
16,384-Bit (2048 x 8) UV Erasable CMOS PROM .................. 7-9
x.
Section 1
Introduction
COPS Family
National Samiconduc'jor COPSTM Microcontroller Family Guide
COP:
ROM x 8
RAM x 4
Inputs
Bidirectional
TRI-STATE@I/O
Bidirectional 110
Outputs
Serial 110 and
External Event Counter
Internal Time
Base Counter
Time Base Counter
Programmable
Interrupt
Stack Levels
MICROBUSTM Option
Instruction Cycle (~s)
Min.-Max.
PackaQe Size (Pins)
Availability
410L 1 410C
411L
ROM x 8
RAM x 4
Inputs
Bidirectional
TRI-STATE® 110
Bidirectional 110
Outputs
Serial 1/0 and
External Event Counter
Internal Time
Base Cou nte r
Time Base Counter
Programmable
3
2
Yes
Yes
External ROM
X8
RAM x 4
Inputs
Bidirectional
TRI-STATE'" 110
Bidirectional 110
Outputs
Serial 110 and
External Event Counter
Internal Time
Base Counter
Time Base Counter
Programmable
Interrupt
Stack Levels
MICROBUSTM Option
Instruction Cycle (~s)
Min.-Max.
Package Size (pins)
Availabilitl
I
SIO
1
Yes
24
20
Future
No
Now
Yes
I
4-10
115-40 115-245-
I
No
No
Ves
4-0C
Future
I
Now
Future
128
3072
192
160
0
I
4
8
16
4
4
8
0
1
1
No
1
No
Yes
4
Sources
Nn
Ves
15-40 1 4-0C
15-40
28
I
Now
401L
Up to
512
32
0
I
4
4
Ves
Yes
Ves
Yes
Yes
Yes
Yes
No
No
I
Ves
4
Sources
4 Iler CPU
Ves
I
Yes
Now
I
Ves
sou~ces
Yes
40
28
24
Future
I
402M
Up to 1024
No
Ves
No
I
4-25
40
I
28
I
24
24
28
4-25
COPSTM ROMless Microcontroller Family Guide
404C
404L
404
Up to 2048
I
2404
409
Up to
32768
512
408
Up to
4096
256
128
4
160
4
8
8
8
16
8
4
4
4
4
4
4
8
4
4
4
Yes
Yes
Yes
Ves
Yes
No
Yes
Yes
Yes
No
No
Yes
I
No
I
Yes
Yes
No
No
Yes
3
3
Yes
24
Future
64
4
No
2
No
I
28
Future
Now
No
I
4
4
No
No
4-10
Samiconduc~or
402
No
4-0C
24
Future
4
4
sou~ces
I
1 a
4
4
4
y,< __ I
~,In
I
a
4
I
485
4096
256
8
8
Yes
I
I
484
8
4
Yes
Yes
4
0
465
8
16
Yes
No
I
4
8
I
115-40
20
Now
Future
Now
2048
4
4-10
24
28
I
4-0C
15-245
4-10 115-40
Samiconduclor COPSTM Microcontroller Family Guide (continued)
464 I
440 I 441 I 442 I 2440
2441 I 2442
445L I 445C
444C
No
Ves
No
3
15-40 1 4-0C
I
2
2
Ves
SIO
Yes
15-40 1 4-DC
444L
1 422L
I
I
4
4
Yes
No
No
2
No
I
422
Ves
No
Now
Future
421C
421C
1 421L
1024
64
0
No
[\lational
cop:
421
I
4
4
3
Instruction Cycle (~s)
Min.-Max.
PackaQe Size (pins)
Availability
Futuro
420C
420C
8
4
4
Stack Levels
nntinn
l
4
Ves
rcTl.~
.1 420L
8
Interrupt
u If'OnOI
420
0
i'~a'!ional
COP:
1 411C
512
32
Yes
No
4
Yes
Yes-4 sources
4
I 4 per CPU
Yes
No
Ves
4
8
No
15-40
4-10
4-0C
15-40
4-10
4-25
40
Now
40
Now
40/48
40
Now
48
Now
40
Future
Future
1-3
Section 2
Single-Chip
Microcontrollers
II
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~National
~
D Semiconductor
o
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COP410C/COP411C and COP310C/COP311C
Fully Static, Single-Chip CMOS Microcontrollers
~
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P
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General Description
Features
The COP410C, COP411C, COP310C, and COP311C fully
static, single-chip CMOS microcontrollers are members
of the COPSTM family, fabricated using double-poly,
silicon gate complementary MOS technology. These
microcontrollers are complete microcomputers containing all system timing, internal logic, ROM, RAM, and 1/0
necessary to implement dedicated control functions in
a variety of output configuration options, with an instruc.
tion set, internal architecture, and I/O scheme designed
to facilitate keyboard input, display output, and BCD
data manipulation. The COP411C is identical to the
COP410C but with 161/0 lines instead of 19. They are an
appropriate choice for use in numerous human interface
control environments. Standard test procedures and
reliable high·density fabrication techniques provide the
medium to large volume customers with a customized
Controller Oriented Processor at a low end product cost.
• Lowest power dissipation (40J.'W typical)
The COP310C/COP311C are exact functional equivalents, but extended temperature range versions of the
COP410C/COP411C.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
"C
Low cost
Power saving HALT mode with Continue function
Powerful instruction set
512x8 ROM, 32x4 RAM
19 1/0 lines (COP410C)
Two-level subroutine stack
DC to 4J.'s instruction time
Single supply operation (2.4V to 5.5V)
General purpose and TRI-STATE® outputs
Internal binary counter register with MICROWIRETM
serial 1/0 capability
LSTTLICMOS compatible in and out
Software/hardware compatible with other members
of the COP400 family
MICROWIRETM compatible serial I/O
Extended temperature range device available (-40°C
to +85°C)
TRI.sTATE Is a registered trademark of National Semiconductor Corp.
COPS and MICROWIRE are trademarks of National Semiconductor Corp.
D,'
D,'
D,
D,
r;:;:::;::;:;:::;::;r""-:: I
MICROWIRE 110
"
G,·
G,
G,
G,
·COP41I1Cpln$Gnly
NlIllYaiLlblltnC0P411C
5
I
1
•
1011
12
13
Figure 1. COP410C/COP411C Block Diagram
2-3
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2; Connection Diagrams
a..
o()
oo
2;
l4
20
l5
. Vee
19
L3
18
L2
17
L1
16
LO
15
14
13
12
11
L6
L7
RESET
CKI
00
01
G2
Gl
GO
S2
a..
SO
SK
GND
o()
c5
9
10
GNO
CKO
24
23
CKI
RESET -
"
21
20
L7
19
L6
L5
L.
VCC
L3
L2
L1
"
10
11
12
17
16
15
14
13
00
01
02
03
G3
G2
Gl
GO
SK
SO
SI
LO
COP410C/COP310C
COP411C/COP311C
T"'
~
a.. Functional Description
o
()
oo
Oscillator
There are three basic clock oscillator configurations:
~
a) Crystal Controlled Osci lIator
o
()
b) External Oscillator
a..
c) RC Controlled Oscillator
HALT Mode
The COP410C/COP411C is a fully static circuit; therefore, the user is able to either stop the system oscillator
input (CKI), or place the device in its "HALT" mode by
either software or hardware control. Once in the HALT
mode, the internal circuitry does not receive any clock
signal, and is therefore frozen in the exact state it was
in at the moment of the HALT stimulus_ Since the circuit
is fully static, all information is retained. The HALT mode
is also the minimum power dissipation state of the
device.
1/0 Options
a) Standard (Push-Pull) - An N-channel device to ground
in conjunction with a P-channel device to Vcc , compatible with CMOS and LSTTL_
b) Low Current - This is the same as a) above except
that the source current is approximately ten times
smaller_
c) Open Drain - An N-channel device to ground only,
allowing external pull-up as required by the user's
application_
d) Standard TRI.-STATE® L Output - A CMOS output
buffer which may be disabled by program control.
e) Low Current TRI-STATE L Output - This is the same
as d) above except that the source current is approximately ten times smaller.
f) Open Drain TRI-STATE L Output - This has only the
N-channel device to ground, which may be disabled
by program control.
g) An on-Chip pull·up load device to Vee (input option).
h) A Hi-Z input which must be driven by user logic.
eKO Pin Options
In a crystal-controlled oscillator system, CKO is used as
an output to the crystal network. CKO will be forced
high during the execution of a HALT instruction, thus
inhibiting tne crystal network. If a one-pin oscillator
system is chosen (RC or external), CKO will be a conversational 1/0 port used to flag the execution of a HALT
instruction. CKO can at any time and in any clock configuration be externally forced high to execute a Hardware
Halt, but the continue function (force CKO low to restart
the device) is only available when using a one-pin oscillator.
Instruction Set
Exactly the same as the COP410L/COP411L with the
additional instruction:
HALT
2-4
Halt System Oscillator
o
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~National
a
~
Semiconductor
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COP410L/COP411L and COP310L/COP311L
Single·Chip N·Channel Microcontrollers
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General Description
Features
The COP410L and COP411L Single-Chip N-Channel Micro·
controllers are members of the COPSTM family, fabricated
using N·channel, silicon gate MOS technology. These
Controller Oriented Processors are complete microcom·
puters containing all system timing, internal logic, ROM,
RAM and 1/0 necessary to implement dedicated control
functions in a variety of applications. Features include
single supply operation, a variety of output configuration
options, with an instruction set, internal architecture and
I/O scheme designed to facilitate keyboard input, display
output and BCD data manipulation. The COP411L is identical to the COP410L, but with 16 1/0 lines instead of 19.
They are an appropriate choice for use in numerous
human interface control environments. Standard test
procedures and reliable high·density fabrication techniques provide the medium to large volume customers
with a customized Controller Oriented Processor at a
low end·product cost.
• I.ow cost
• Powerful instruction set
• 512x8ROM,32x4RAM
r
~
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~
• 19 1/0 lines (COP410L)
• Two·level subroutine stack
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~
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• 161"s instruction time
• Single supply operation (4.5-6.3V)
~
• Low current drain (6mA max.)
• Internal binary counter register with MICROWIRETM
serial I/O capability
• General purpose and TRI·STATE® outputs
• LSTTLICMOS compatible in and out
• Direct drive of LED digit and segment lines
• Software/hardware compatible with other members
of COP400 family
The COP310L and COP311L are exact functional equivalents but extended temperature versions of COP410L
and COP411L respectively.
The COP401 L may be used for exact emulation.
• Extended temperature range device COP310LlCOP311 L
(-40°C to +85°C)
• Wider supply range (4.5-9.5V) optionally available
"'0
~,
tNSTRUCTION CLOCK (SYNCl
OJ·
0,·
0,
00
1.=====::;-1-"'-
SKI
SOl
51
G3·
G,
G,
Go
'COP410lpin,only
Notava,\able,nCOP411l
5
6
1
8
10
11
12
13
Figure 1. COP410Ll411L Block Diagram
COPS and MICROWIRE are trademarks of National Semiconductor Corp.
TRI·STATE is a registered trademark of National Semiconductor Corp.
2-5
MICROW1RE 110
.....
.-
0
...I
~
~
COP410UCOP411L
o
Absolute Maximum Ratings
:J
Voltage at Any Pin Relative to GND
Ambient Operating Temperature
Ambient Storage Temperature
Lead Temperature (Soldering, 10 seconds)
Power Dissipation
COP410L
Q.
o
o
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oo
-0.5V to +10V
O°Cto +70°C
-65°C to +150°C
300°C
0.75 Watt at 25°C
0.4 Watt at 70°C
0.65 Watt at 25°C
0.3 Watt at 70°C
120mA
100mA
,.j
~
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COP411L
Total Source Current
Total Sink Current
Absolute.maximum ratings indicate limits beyond which damage
to the device may occur. DC and AC electrical specifications are
not ensured when operating the device at absolute maximum
ratings.
DC Electrical Characteristics
O°C" TA " +70°C, 4.5V" Vee" 9.5V unless otherwise noted.
Parameter
Standard Operating Voltage (Ved
Conditions
Note 1
Optional Operating Voltage (Ved
Power Supply Ripple
peak to peak
Operating Supply Current
all inputs and outputs open
Min.
Max.
Units
4.5
6.3
V
4.5
9.5
V
0.5
V
6
mA
0.4
V
V
0.7 Vee
-0.3
0.6
V
V
0.7 Vee
-0.3
0.6
V
V
2.0
2.5
V
Input Voltage Levels
CKI Input Levels
Ceramic Resonator Input (';'8)
Logic High (VIH)
Logic Low (VILl
2.0
-0.3
Schmitt Trigger Input (+4)
Logic High (V IH )
Logic Low (VILl
RESET Input Levels
Logic High
Logic Low
(Schmitt Trigger Input)
SO Input Level (Test mode)
Note 2
All Other Inputs
Logic High
Logic High
Logic Low
Vee = Max.
with TTL trip level options
selected, Vee = 5V ± 5%
3.0
2.0
-0.3
0.8
V
V
V
Logic High
Logic Low
with high trip level options
selected
3.6
-0.3
1.2
V
V
Input Capacitance
-1
Hi·Z Input Leakage
Output Voltage Levels
LSTTL Operation
Logic High (VOH )
Logic Low (VoLl
Vee=5V±5%
IOH =-25,.,A
IOL=0.36mA
CMOS Operation
Logic High
Logic Low
IOH =-10,.,A
IOL=+10,.,A
7
pF
+1
,.,A
2.7
0.4
V
V
0.2
V
V
Vee- 1
Note 1: Vee voltage change must be less than 0.5V in alms period to maintain proper operation.
Note 2: SO output "0" level must be less than,O.BV for normal operation.
2-6
(")
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COP410LlCOP411L
DC Electrical Characteristics
Parameter
Output Current Levels
Output Sink Current
SO and SK Outputs (loll
(continued) O°C '" TA
",
+70°C, 4.5V '" Vee'" 9.5V unless otherwise noted.
Conditions
Min.
Max.
(")
...L
mA
mA
mA
Vee = 9.5V, VOL = O.4V
Vee = 6.3V, VOL = O.4V
Vee = 4.5V, VOL = O.4V
0.8
0.5
0.4
mA
mA
mA
Do- D3 Outputs with High
Current Options (loll
Vee = 9.5V, VOL = 1.0V
Vee = 6.3V, VOL = 1.0V
Vee = 4.5V, VOL = 1.0V
15
11
7.5
mA
mA
mA
Do- D3 Outputs with Very
High Current Options (loll
Vee = 9.5V, VOL = 1.0V
Vee = 6.3V, VOL = 1.0V
Vee = 4.5V, VOL = 1.0V
30
22
15
mA
mA
mA
Vee = 4.5V, V1H = 3.5V
Vee = 4.5V, VOL = O.4V
2
0.2
mA
mA
Standard Configuration,
All Outputs (lOH)
Vee = 9.5V, VOH = 2.0V
Vee = 6.3V, VOH = 2.0V
Vee = 4.5V, VOH = 2.0V
-140
-75
-30
Push·Pull Configuration
SO and SK Outputs (lOH)
Vee = 9.5V, VOH = 4.75V
Vee = 6.3V, VOH = 2.4V
Vee = 4.5V, VOH = 1.0V
-1.4
-1.4
-1.2
LED Configuration, Lo-L7
Outputs, Low Current
Driver Option (IOH)
Vee = 9.5V, VOH = 2.0V
Vee = 6.0V, VOH = 2.0V
LED Configuration, Lo-L7
Outputs, High Current
Driver Option (IOH)
CKI (Single-pin RC oscillator)
CKO
Output Source Current
-800
-480
-250
"A
"A
"A
mA
mA
mA
-1.5
-1.5
-18
-13
mA
mA
Vee = 9.5V, VO H = 2.0V
Vee = 6.0V, VO H = 2.0V
-3.0
-3.0
-35
-25
mA
mA
Current Driver Option (lOH)
Vee = 9.5V, VOH = 5.5V
V~~ = R::lV. Vn'J = ::l.2V
Vee = 4.5V, VOH = 1.5V
-0.75
-0.8
-0.9
mA
mA
mA
TRI·STATE@ Configuration,
Lo-L7 Outputs, High
Current Driver Option (lOH)
Vee = 9.5V, VOH = 5.5V
Vee = 6.3V, VOH = 3.2V
Vee = 4.5V, VOH = 1.5V
-1.5
-1.6
-1.8
mA
mA
mA
Vee = 5.0V, V1L = OV
-10
TRI-STATE@ Configuration,
1 ,,-I ..., nlltnllh::L I nw
Input Load Source Current
-140
"A
1.5
mA
+2.5
"A
100
100
4
4
2.0
mA
mA
mA
mA
mA
120
60
60
25
1.5
mA
mA
CKO Output
RAM Power Supply Option
Power Requirement
o"'C
~
1.8
1.2
0.9
LSTTL Do-D3 Outputs (loll
c:
Units
Vee = 9.5V, VOL = O.4V
Vee = 6.3V, VOL = O.4V
Vee = 4.5V, VOL = O.4V
1.0- L7 Outputs, GO-G 3 and
~
o
VR =3.3V
TRI·STATE@ Output Leakage
Current
-2.5
Total Sink Current Allowed
All Outputs Combined
D Port
L7- L4, G Port
L3-Lo
Any Other Pin
Total Source Current Allowed
All 1/0 Combined
Lr L4
L3-Lo
Each L Pin
Any Other Pin
2-7
mA
mA
mA
r
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COP310LlCOP311 L
o
Absolute Maximum Ratings
:J
o
2?
Voltage at Any Pin Relative to GND
Ambient Operating Temperature
Ambient Storage Temperature
Lead Temperature (Soldering, 10 seconds)
Power Dissipation
COP310L
Il..
o
Il..
o
o
...r
,..
~
Il..
-0.5V to +10V
-40°C to +85°C
-65°C to + 150°C
300°C
0.75 Watt at 25.o C
0.25 Watt at 85°C
0.65 Watt at 25°C
0.20 Watt at 85°C
120mA
100mA
COP311L
oo
Total Source Current
Total Sink Current
o
Absolute maximum ratings indicate limits beyond which
damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute
maximum ratings.
:J
~
oo
DC Electrical Characteristics
-40°C" TA " +85°Cj 4.5V " Vee" 7.5V unless otherwise noted.
Conditions
Parameter
Standard Operating Voltage (Vee)
Note 1
Optional Operating Voltage (Vecl
Power Supply Ripple
peak to peak
Operating Supply Current
all inputs and outputs open
Max.
Units
4.5
5.5
V
4.5
7.5
V
Min.
0.5
V
8
mA
Input Voltage Levels
Ceramic Resonator Input(+8)
Crystal Input
Logic High (V IH )
Logic Low (VILl
2.2
-0.3
0.3
V
V
Schmitt Trigger Input ( + 4)
Logic High (V IH )
Logic Low (VILl
0.7 Vee
-0.3
0.4
V
V
0.7 Vee
-0.3
0.4
V
V
2.2
2.5
V
RESET Input Levels
Logic High
Logic Low
(Schmitt Trigger Input)
SO Input Level (Test mode)
Note 2
All Other Inputs
Logic High
Logic High
Logic Low
Vee = Max.
with TTL trip level options
selected, Vee = 5V ± 5%
3.0
2.2
-0.3
0.6
V
V
V
Logic High
Logic Low
with high trip level options
selected
3.6
-0.3
1.2
V
V
Input Capacitance
-2
Hi-Z Input Leakage
Output Voltage Levels
LSTTL Operation
Logic High (VOH)
Logic Low (Vall
Vee=5V±5%
IOH =-20/AA
IOL=0.36mA
CMOS Operation
Logic High
Logic Low
IOH =-10/AA
IOL=+10/AA
7
pF
+2
/AA
2.7
0.4
V
V
0.2
V
V
Vee- 1
Note 1: Vee voltage change must be less thim O.5V in a 1ms period to maintain proper operation.
Note 2: SO output" 0" level must be less than O.6V for normal operation.
2-8
o
o
."
COP310LlCOP311L
DC Electrical Characteristics
(continued) -40·C " TA " +85·C, 4.5V " Vee" 7.5V unless otherwise noted.
Parameter
Output Current Levels
Output Sink Current
SO and SK Outputs (Iou
=
Max.
Units
1.4
1.0
0.8
mA
mA
mA
Lo-L7 Outputs, GO-G 3 and
LSTTL, Do-D3 Outputs (loll
Vee = 7.5V, VOL = O.4V
Vee = 5.5V, VOL = 0.4V
Vee = 4.5V, VOL = 0.4V
0.6
0.5
0.4
mA
mA
mA
Do-D3 Outputs with High
Current Options (loll
Vee = 7.5V, VOL=1.0V
Vee = 5.5V, VOL 1.0V
Vee = 4.5V, VOL 1.0V
12
9
7
mA
mA
mA
Do-D3 Outputs with Very
High Current Options (loll
Vee = 7.5V, VOL = 1.0V
Vee = 5.5V, VOL = 1.0V
Vee = 4.5V, VOL = 1.0V
24
18
14
mA
mA
mA
CKI (Single'pin RC oscillator)
CKO
Vee = 4.5V, V1H = 3.5V
Vee = 4.5V, VOL = 0.4V
1.5
0.2
mA
mA
Output Souree Current
Standard Configuration,
All Outputs (loH)
I
=
Min.
Vee 7.5V, VOL O.4V
Vee = 5.5V, VOL = 0.4V
Vee = 4.5V, VOL = 0.4V
,
I
Conditions
=
=
=
-900
-600
-350
Vee 7.5V, VOH = 2.0V
Vee = 5.5V, VO H = 2.0V
Vee = 4.5V, VO H = 2.0V
-100
-55
-28
Push·Pull Configuration
SO and SK Outputs (IOH)
Vee = 7.5V, VOH = 3.75V
Vee = 5.5V, VOH 2.0V
Vee = 4.5V, VO H = 1.0V
-0.85
-1.1
-1.2
LED Configuration, Lo-L7
Outputs, Low Current
Driver Option (IOH)
Vee = 7.5V, VOH = 2.0V
Vee 5.5V, VOH 2.0V
-1.4
-0.7
-27
-15
mA
,..A
LED Configuration, Lo-L7
Outputs, High Current
Driver Option (lOH)
Vee = 7.5V, VO H = 2.0V '
Vee = 5.5V, VOH = 2.0V
"':2.7
-1.4
-54
-30
mA
,..A
Vee = 7.5V, VO H = 4.0V
-0.7
-
TRI·STATEt- VOL
I Zrz z'"',..------i[I7'"'2.A
I
. . . _____. . I7. ....Z'-'ZJ/
I(r r
l-tSETUP-II..-tHOLO
Gl-~~i~:UL~S 7I7,zrZ"Z,",Z7Z7I7,zrzrZ""Z7Z7zz-rzrzrZ""Z"'Z7ZZ"'jX
GC;~~O,OS30~~~
~nZ"TZTzrZ""Z""Z"'I7"TZTzrz""z""z
X",Z.f.>.f.4. :rV~OU.L_______
r,Z/ZZztVOH
OUTPUTS
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Figure 3, InputlOutput Timing Diagrams (Ceramic Resonator Divide,by-B Mode)
."
~
o
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-II-two
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Figure 3a, Synchronization Timing
Functional Description
A block diagram of the COP410L is given in Figure 1,
Data paths are illustrated in simplified form to depict
how the various logic elements communicate with each
other in implementing the instruction set of the device,
Positive logic is used, When a bit is set, it is a logic "1"
(greater than 2 volts), When a bit is reset, it is a logic "0"
(less than 0,8 volts),
select 1 of 4 data registers and lower 3 bits of the 4-bit
Bd select 1 of 8 4-bit digits in the selected data register,
While the 4-bit contents of the selected RAM digit (M) is
usually loaded into or from, or exchanged with, the A
register (accumulator), it may also be loaded into the Q
latches or loaded from the L ports, RAM addressing
may also be performed directly by the XAD 3,15 instruction, The Bd register also serves as a source register for
4-bit data sent direclly to the D outputs,
All functional references to the COP410LlCOP411L also
apply to the COP310LlCOP311L,
The most significant bit of Bd is not used to select a
CAU rli"i+ ,"-,.on,.....o. o'!:lI,..h nh\lQ;I"'!l1 rli,.,it nf 1:1'.l~.PI..'" rT'I!:li\J no
selected by two different values of Bd as shown in
Figure 4 below, The skip condition for XIS and XDS
instructions will be true if Bd changes between 0 and 15,
but NOT between 7 and 8 (see Table 3),
Dr""",ra.rn U.a.I'ft"'_'
-
Program Memory consists of a 512-byte ROM, As can be
seen by an examination of the COP410Ll411L instruction set, these words may be program instructions,
program data or ROM addressing data, Because of the
special characteristics associated with the JP, JSRP,
JID and LQID instructions, ROM must often be thought
of as being organized into 8 pages of 64 words each,
BdVAlUE
ROM addressing is accomplished by a 9-bit PC register.
Its binary value selects one of the 512 8-bit words
contained in ROM, A new address is loaded into the PC
register during each instruction cycle, Unless the
instruction is a transfer of control instruction, the PC
register is loaded with the next sequential 9-bit binary
count value, Two levels of subroutine nesting are implemented by the 9-bit subroutine save registers, SA and
SB, providing a last-in, first-out (LIFO) hardware
subroutine stack.
RAM DIGIT
15"
,..
",'"
to'
9'
ROM instruction words are fetched, decoded and executed by the Instruction Decode, Control and Skip Logic
circuitry,
Data Memory
0'
Data memory consists of a 128-bit RAM, organized as 4
data registers of 8 4-bit digits, RAM addressing is implemented by a 6-bit B register whose upper 2 bits (Br)
~CAN
BE DlREen Y ADDRESSED BY
lBllNSTAUCTION (SEE TABLE l}
Figure 4, RAM Digit Address to Physical RAM Digit Mapping
2-11
~ r-----------------------------~----------~------------------------,
.....
z;;
Q.
o
~
o
z;;
Q.
8
J.....
io
~
o
The 4-bit A register (accumulator) is the source and destination register for most I/O, arithmetic, logic and data
memory access operations. It can also be used to load
the Bd portion of the B register, to load 4 bits of the S-bit
Q latch data, to input 4 bits of the S-bit L I/O port data
and to perform data exchanges with the SIO register.
1. The least significant bit of the ,enable register, ENe,
selects the SIO register as either a 4-blt shift register.
or a 4-blt binary counter. With ENe set, SIO is an
asynchronous binary counter, decrementing its value
by one upon each low-going pulse ("1" to "0")
occurring on the SI input. Each pulse must be at least
two instruction cycles wide. SK outputs the value of
SKL. The SO output is equal to the value of EN a. With
ENe reset, SIO Is a serial shift register shifting left
each Instruction cycle time_ The.data present at SI
goes Into the least significant bit of SIO. SO can be
enabled to output the most significant bit of SIO
each cycle time. (See 4 belOW.) The SK output
becomes a logic-controlled clock.
A 4-bit adder performs the arithmetic and logic functions of the COP410U411L, storing its results in A. It
also outputs a carry bit to the 1-bit C register, most
often employed to Indicate arithmetic overflow. The C
register, in conjunction with the XAS instruction and the
EN register, also serves to control the SK output. C can
be outputted directly to SK or can enable SK to be a
sync clock each instruction cycle time. (See XAS
instruction and EN register description, below.)
::;
The G register contents are outputs to 4 generalpurpose bidirectional I/O ports.
8
The Q register is an internal, latched, S-blt register, used
to hold data loaded from M and A, as well as S-bit data
from ROM. Its contents are output to the L I/O ports
when the L drivers are enabled under program control.
(See LEI instruction.)
Q.
The EN register Is an internal4-bit register loaded under
program control by the LEI instruction. The state of
each bit of this register selects or deselects the
particular feature associated with each bit of the EN
register (EN a- ENe).
Internal Logic
2. EN, is not used. It has no effect on COP410UCOP411L
operation.
3. With EN2 set, the L drivers are enabled to output the
data in Q to the L I/O ports. Resetting EN2 disables
the L drivers, placing the L I/O ports in a highimpedance input state.
The S'L drivers, when enabled, output the contents of
latched Q data to the L I/O ports. Also, the contents of L
may be read directly into A and M. L I/O ports can be
directly connected to the segments of a multiplexed
LED display (using the LED Direct Drive output configuration option) with Q data being outputted to the Sa-Sg
and decimal point segments of the display.
4. EN a, In conjunction with ENe, affects the SO output.
With ENe set (binary counter option selected) SO will
output the value loaded into EN a. With ENe reset
(serial shift register option selected), setting ENa
enables SO as the output of the SIO shift register,
outputting serial shifted data each Instruction time.
Resetting ENa with the serial shift register option
selected disables SO as the shift register output;
data continues to be shifted through SIO and can be
exchanged with A via an XAS Instruction but SO
remains reset to "0." Table' I provides a summary of
the modes associated with ENa and ENe.
The SIO register functions as a 4-bit serlal-in/serial-out
shift register or as a binary counter depending on the
contents of the EN register. (See EN register
description, below.) Its contents can be exchanged with
A, allowing it to input or output a continuous serial data
stream. SIO may also be used to provide additional
parallel I/O by connecting SO to external serial·inl
parallel-out shift registers.
Initialization
The XAS Instruction copies C into the SKL Latch. In the
counter mode, SK is the output of SKL In the shift
register mode, SK outputs SKL ANDed with Internal
Instruction cycle clock.
The Reset Logic will initialize (clear) the device upon
power-up if the power supply rise time is less than 1 ms
and greater than 1"S. If the power supply rise time is
greater than 1 ms, the user must provide an external RC
Enable Register Modes -
Bits EN3 andENo
ENs
ENo
SIO
SI
SO
0
0
Shift Register
Input to Shift Register
0
SK
If SKL
If SKL
1
0
• Shift Register
Input to Shift Register
Serial Out
If SKL
If SKL
0
1
Binary Counter
Input to Binary Counter
0
If SKL
If SKL
1
1
Binary Counter
Input to Binary Counter
1
If SKL
If SKL
2-12
= 1, SK
= 0, SK
= 1, SK
= 0, SK
= 1, SK
= 0, SK
= 1, SK
= 0, SK
= Clock
=0
= Clock
=0
=1
=0
=1
=0
Oscillator
network and diode to the RESET pin as shown below
(Figure 5). The RESET pin is configured as a Schmitt
trigger input. If not used it should be connected to Vcc.
Initialization will occur whenever a logic "0" is applied
to the RESET input, provided it stays low for at least
three instruction cycle times.
There are four basic clock oscillator configurations
available as shown by Figure 6.
a. 'Resonator Controlled Oscillator. CKI and CKO are
connected to an external ceramic resonator. The
instruction cycle frequency equals the resonator
frequency divided by B. This Is' not available in the
COP411L.
.
b. External Oscillator. CKI is an external clock Input
signal. The external frequency is divided by 8 to give
the instruction frequency time. CKO is now available
to be used as the RAM power supply (VR), as a SYNC
Input, or no connection. (Note: No CKO on COP411L)
P +
o
~~
W
E
R
VCC
RESET COP410L
S
U
P
P
L
Y
"r-
c. RC Controlled Oscillator. CKI is configured as a
single pin RC controlled Schmitt trigger oscillator.
The Instruction cycle equals the oscillation frequency
divided by 4. CKO Is available as the RAM power sup·
ply (VR) or no connection.
GNO
RC;;' 5 x POWER SUPPLY RISE TIME
d. Externally Synchronized Oscillator. Intended for use
in multi·COP systems, CKO Is programmed to function
as an input connected to the SK output of another
COP chip operating at the same frequency (COP chip
with Lor C suffix) with CKI connected as shown. In
this configuration, the SK output connected to CKO
must provide a SYNC (instruction cycle) signal to
CKO, thereby allowing synchronous data transfer
between the COPs using only the SI and SO serial 110
pins in conjunction with the XAS Instruction. Note
that on power·up SK Is automatically enabled as a
SYNC output. (See Functional Description, Initialization, above.) This Is not available in the COP411L.
Figure 5. Power·Up Clear Circuit
Upon initialization, the PC register is cleared to 0 (ROM
address 0) and the A, B, C, D, EN, and G registers are
cleared. The SK output is enabled as a SYNC output,
providing a pulse each instruction cycle time. Data
Memory (RAM) is not cleared upon initialization. The
first instruction at address 0 must be a CLRA.
(SYNC)
I
~
CKI
A
t
..f1J
t
(V R OR N/C)
EXTERNAL
CLOCK
CKI
CKO
CKI
CKO
SK~
0
COP410L
COP410L
SO
r----
sll_
SI
SO
RC Controlled Oscillator
Ceramic Resonator Oscillator
Component Values
Resonator
Value
R1 (Q)
455kHz
4.7k
I R2 (Q) I C1 (pF) I C2 (pF)
I
1M
I
220
I
220
R(kQ)
C (pF)
Instruction
Cycle Time
in lAs)
51
B2
100
56
19±15%
19±13%
Note: 200kQ
360pF
Figure 6. COP410Ll411l0sciliator
2-13
~
~
R ~ 25kQ
C ~ 50pF
...J
,..
~
a..
o()
::J
o
~
a..
o
()
...i
,..
~
eKO Pin Options
a..
RAM Keep-Alive Option
::J
Selecting CKO as the RAM power supply (VR) allows the
user to shut off the chip power supply {Vecl and maintain
data in the RAM. To insure that RAM data integrity is
maintained, the following conditions must be met:
o()
o
~
a..
o
()
a_ Standard - an enhancement-mode device to ground
in conjunction with a depletion-mode device to Vee,
compatible with LSTTL and CMOS input requirements.
Available on SO, SK, and all D and G outputs.
In a resonator controlled oscillator system, CKO is used
as an output to the resonator network. As an option
CKO can be a SYNC input as described above. As
another option, CKO can be a RAM power supply pin
(VR), allowing its connection to a standby/backup power
supply to maintain the integrity of RAM data with
minimum power drain when the main supply is inoperative or shut down to conserve power. Using no connection
option is appropriate in applications where the COP410L
system timing configuration does not require use of the
CKO pin.
b. Open-Drain - an enhancement-mode device to
ground only, allowing external pull-up as required by
the user's application. Available on SO, SK, and all D
and G outputs.
c_ ,Push-Pull - an enhancement-mode device to ground
in conjunction with a depletion-mode device paralleled
by an enhancement-mode device to Vee. This configuration has been provided to allow for fast rise and fall
times when driving capacitive loads. Available on SO
and SK outputs only.
d. Standard L - same as a., but may be disabled.
Available on L outputs only.
1. RESET must go low before Vee goes below spec during power-off; Vee must be within spec before RESET
goes high on power-up.
e_ Open Drain' L - same as b., but may be disabled.
Available on L outputs only.
f. LED Direct Drive - an enhancement mode device to
ground and to Vee, meeting the typical current sourc·
ing requirements of the segments of an LED display.
The sourcing device is clamped to limit current flow.
These devices may be turned off under program control (see Functional Description, EN Register), placing
the outputs in a high·impedance state to provide required LED segment blanking for a multiplexed dis·
play. Available on L outputs only.
2. During normal operation, VR must be within the operating range of the chip with (Vce '-1) ,;; VR ,;; Vee.
3. VR must be;;' 3.3V with Vee off.
1/0 Options
COP410Ll411L inputs and outputs have the following
optional configurations, illustrated in Figure 7:
a. Standard Output
b. Open·Draln Output
c. Push·Pull output
DISABLE~~
(.... IS DEPLETION DEVICE)
d. Standard L Output
e. Open· Drain L Output
f. LED (L Output)
Vee
r-I
J
#6
INPUT~(
g. TRI·STATE'" Push· Pull (L Output)
h. Input with Load
Figure' 7. Input and Output Configurations
2-14
HI·Z Input
g. TRI·STATE® Push·Pull- an enhancement·mode device
shown in a. or b. Note that when inputting data to the G
ports, the G outputs should be set to "1." The L outputs
can be configured as in d., e., t., or g.
to ground and Vcc. These outputs are TRI·STATE® out·
puts, allowing for connection of these outputs to a
data bus shared by other bus drivers. Available on L
outputs only.
An important point to remember if using configuration
d. or t. with the L drivers is that even when the L drivers
are disabled, the depletion load device will source a
small amount of current. (See Figure 8, device 2.) How·
ever, when the L port is used as input, the disabled deple·
tion device CANNOT be relied on to source sufficient
current to pull an input to a logic "1".
h. An on·chip depletion load device to Vcc.
i. A Hi·Z input which must be driven to a "1" or "0" by
external components.
The above input and output configurations share com·
mon enhancement·mode and depletion·mode devices.
Specifically, all configurations use one or more of six
devices (numbered 1-6, respectively). Minimum and max·
imum current (lOUT and VOUT) curves are given in Figure
8 for each of these devices to allow the designer to ef·
fectively use these 1/0 configurations in designing a
COP410Ll411L system.
COP411L
If the COP410L is bonded as a 20'pin device, it becomes
the COP411L, illustrated in Figure 2, COP410Ll411L
Connection Diagrams. Note that the COP411L does not
contain D2, D3, G3, or CKO. Use of this option of course
precludes use of D2, D3, G3, and CKO options. All other
options are available for the COP411L.
The SO, SK outputs can be configured as shown in a.,
b., or c. The D and G outputs can be configured as
Input Current for LO through
L7 when Output Programmed
Off by Software
-100
-90
-80
-70
:i
-60
c
-50
~
-40
-30
DEVICEd#2
ANDf#2
-800
-700
"- r-...
:i
"
15
IMAX@
VCC=4.5V
"':':,.
t-.
IN_r vcr ~.5V
:~C'4.5V
o
o
DEVICE a #2
ANy d #2
-900
1'\.1 MAX@VCC· 9.5V
-10
...... f::::: ....
1.0
2.0
-600
"
-500
r-,-..
"J/¥H::
K"
"-
7
9.5
8
VOH (VDLTS)
Source Current for LO through
L7 in TRI·STATE'
Configuration (Low Current
Option)
Source Current for LO through
L7 in TRI·STATE"
Configuration (High Current
Option)
Source Current for SO and SK in
Push· Pull Configuration
r-T1r---1r-11,--r---1'--;'--"',..",...",...,
'MAX @VCC' 9.5 V
;'\.1
I'\.
IMAX@
-400 ts'CC' 4.5~
-300 f-' ' \ ' M'N @
VCC - .5~.!.
-200
i'.~ 'M'N
-100
J.'I...
0
o 1 2 3 4 5 6
V 110
V ,N (VOLTS)
1.5
Source Current for Standard
Output Configuration
-1000
I
I
I
-20
9.5
1.5
1.5 .--..-,.,,-,-..-,.-..-,-,-,
VCC=
.l..1.IMAX@
9.5V
1.0
HI\--IHl-i---'f.+iI-"'f-t-t-H
IMIN~~
1.0
.... VC =9.5V
1.0
I--I-H-+-+-++
IMAX@
~CI4.5V
0.5
0.5
0.5 f-Hf-F-t-Ht-H-t-t-;
IMIN@
o
1
2 3
4
5 6
VDHIVDLTS)
7
8
9 10
DEVICE ,#2
AND #3
C
o
o"C
~
-'"
r
o
o"C
~
o
a
o
"C
~
r-
Input Current RESET, SI
1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0
~
o
-'"
Typical Performance Curves
~
o
o"C
o
1
l1rn
2 3
4
5 6 7
DEVICE
g#5
DEVICE
g#5
8
9 10
a
VOHIVOLTS)
Figure 8a, COP410L/COP411L 1/0 DC Current Characteristics
2-15
8
1
VDH(VOLTS)
9 10
,...
,...
('I)
a.
...J
LED Output Direct Segment
and Digit Drive
High Current Options on
LO·L7
Very High Current Optilms on
00·03
0
0
::J
LED Output Source Current
(for High Current LED Option)
0
I'
LED Output Source Current
(for Low Current LED Option)
~
-5 0
DEVICE I #2 AND #4
DEVIICE a OR b #1
a.
A~D
0
0
J
,...
~
a.
-40
IMAX
ONE SEGMENTS..........
~
"<
..s
..s
-30
!:
'"
§
-20
0
0
LV
........V
-10
..-··l...... ~ ....
::::"1. .•.••.
::J
0
2
~
3
a.
4
5
6
1
8
9
-
V
V,MAXEIGHT
SEGMENTS ON
IMIN
I
1
10
10
~~~
VCC (VOLTS)
~~~
0
0
LED Output Direct
Segment Drive
-50
Output Sink Current for LO·L7
and Standard Drive Option for
00·03 and GO·G3
Output Sink Current for SO
and SK
VOH"2.oV
DEVICE I
#2 AND #4
-4 0
of--
r- ~M~ro~IGH CURRENT I -
l:/'-;t:'Jw
OPTION
-10
."
.....
0
CURRENT
_
........•
../r~INHIGH
CURRENT OPTION
....... II--~MIN
LOW
!::"::::::
cu'iiRENT OPTION
10
VCC (VOLTS)
VOL(VOLTS)
VOLIVOLTS)
Output Sink Current for
00·03 (for High Current
Option)
Output Sink Current for 00·03
with Very High Current Option
120
100
80
VCC=9.5V
L
20
DEVICE 8#1
AND b#l
/
r-"..-..-..-..-..--==:-:::1
100r-+++-+-~-r-+-+-+~~
--IIF:MAX@
VCC=4.5V
/l,MINI@
40
120
IrJ IMAX@i~:-:!
80~~~~~~~-i-i~
~CC~9.~V
~ 60r-t-~-r-t-i~~~+-1-~
52
,...
40 H-f-h;l"'--t
~t-
V I~INI@ ~CCI4.~V
o 1 2 3 4 5 6
7
8
9 lD
VOL(VDLTS)
VOL(VOLTSI
Figure 8a. COP410L./COP411 L 110 DC C'!rrent Characteristics (continued)
2-16
o
Input Current RESET, SI
-250
- 120
-200 r--.... .......
)"-....
z
=-100
'"
1'---
" f\
IMAX @
IMAX @
NCC~4.5V
i"--
r
IMIN @
\
VCC ~ 7.5V
o
o
~
E
;; -0.6
9
1--f'..ri--I--f-"..,{:-4--1---(
-0.4
-0. 2 ~-=t"'-.!~h"+-+--"~-+--l
-20
1\
I--'''-I---II--+-+__+-="n.:::dfd",.#:.:2t--i
-O.B 1--+--4'::':t--t--+--+-~--j
=>
!2 -40
\
-1. 0
;;r:
~ -60~--~~---+----~----~
1\
IMIN @
VCCt 4 V
-50
1 -80
VCC~7.5V
~
-1.2 r-...,-'--'~'-""-'--~
OEVICE " H2
r---~----r----'-----'
DEVICE d #2
ANO I #2
-100 ~r-~-----+-----r~--~
DiVICi h # 6
o"'tJ
Source Current for
Standard Output
Configuration
Input Current for LO·L7
when Output Programmed
Off by Softwa re
"'tJ
~
.....
r
o
o"'tJ
~
Source Current for SO
and SK in Push·Pull
Configuration
VI/O (VOLTSI
VOH (VOLTSI
Source Current for LO·L7
in TRI·STATE' Configuration
(High Current Option)
--------_.-
Source Current for LO·L7
in TRI·STATE'· Configuration
(Low Current Option)
1.5
1.5 ,-,rr--'''''''--'--''''O'''E'''V'''IC''"E-c#"'2'"
AND #3
o
1.5 r--r----.-rr-..-r-,....,O"'E"'VI"'C"'E-g#"'5'"
DEVICE g#5
1
1--++++--\-1--++-+-1--1
IMIN@
E
IMIN@
VCC = 7.5V
VCC~4.5V
~
I
0.5
0.5
o
1---H--+--i--t--H--+--I--1
1.0
1.0
;;r:
I--- j---J IMAX
I
@
~CCf\'1
o
I
+--
IMAX@
TG
0.5
5V
OL.......L--"'--.L.>......L.l..J.--'.L.......L-
o
B'
VOH(VOLTSI
VOH(VOLTSI
VOH(VOLTSI
LED Output Source
Current (for Low Current
LED Option)
LED Output Source
Current (for High Current
LED Option)
Output Sink Current for
SO and SK
-30r--r~-.--r-.--.--r--'
-20
~
~IMAX @VCC=7.5V
9
IMAX @ VCC=4.5V
,
,
,
IMIN @ VCC = 7.5V
-10
I-II--il--""I~IN
@ V'CC=4.5V
o "--__.L....__..L.-__....L..__--'-__--'
o
VOH (VOLTSI
VOH (VOLTSI
VOLIVOLTSI
Output Sink Current for
00·03 (for
High Current Option)
Output Sink Current
for 00·03 with Very High
Current Option
Output Sink Current for
LO·L7 and Standard Drive
Option for 00·03 and GO·G3
4"nn---'---'~-'--~
120
120
.---~-,--..-==---,-------.
100
100
BO
BO
~,I
~
1_ 1
J
III
60
U
20
o
IMAX @ VCC~4.5~
II
~
~
V
~
'i;;;;;:@ JCC~7.5V
"iMINI @ JCC=~.5V
o
VOL(VOLTSI
Figure 8b. COP310L/COP311L Input/Output Characteristics
2-17
DEVICE ,#1
ANO b#1
II J-t-I I
40
20
J
IMAX @VCC=7.5V
;;r:
VOLIVOLTSI
o
o
o
C
15
0.5
VIN (VOLTS I
1.0
o
C
VOLIVOLTSI
o"'tJ
~
.....
r-
-
..J
C ")
0-
o
~
c
COP410Ll411L INSTRUCTION SET
Table 3 provides the mnemonic, operand, machine code,
data flow, skip conditions and description associated
with each instruction in the COP410Ll411 L instruction
set.
Table 2 is a symbol table providing internal architecture,
instruction operand and operational symbols used in
the instruction set table.
l;
0-
o
o
-
...i
~
0-
oo
:J
c
~
oo
Table 2. COP410U411 L Instruction Set Table Symbols.
Symbol
Oollnltlon
Symbol
INTERNAL ARCHITECTURE SYMBOLS
A
4·blt Accumulator
B
6·bit RAM Address Register
Br
Upper 2 bits of B (register address)
Bd
Lower 4 bits of B (digit address)
C
1·blt Carry Register
0
4·blt Data Output Port
EN
4·blt Enable Register
G
4·blt Aeglster to latch data for G 110 Port
L
a·blt TRI·STATE 110 Port
M
4·blt contents of RAM Memory pointed to by B
Register
9·bit AOM Address Register (program counter)
PC
Q
a·blt Register to latch data for L 110 Port
SA
9·bit Subroutine Save Register A
SB
9·bit Subroutine Save Aegister B
SIO
4·bit Shift Register and Counter
SK
Loglc·Controlied Clock Output
Oollnilion
INSTRUCTION OPERAND SYMBOLS
4·bit Operand Field, 0-15 binary (RAM Digit Select)
d
r
2·blt Operand Field, 0-3 binary (RAM Register
Select)
a
9·blt Operand Field, 0-511 binary (ROM Address)
4·blt Operand Field, 0-15 binary (Immediate Data)
Contents of RAM location addressed by s
Contents of AOM location addressed by t
Y
RAM(s)
ROM(t)
OPERATIONAL SYMBOLS
Plus
+
Minus
Replaces
Is exchanged with
Is equal to
A
The one's complement of A
Exclusive·OR
-=
.,
Range of values
Table 3. COP410Ll411L Instruction Set
Mnemonic Operand
Hex
Code
Machine
Language Code
(Binary)
Data Flow
Description
Skip Conditions
ARITHMETIC INSTRUCTIONS
ASC
30
10 0 1 110 0 0 01
A + C + RAM(B) - A
Carry - C
Carry
Add with Carry, Skip on
Carry
ADD
31
10011100011
A + RAM(B)- A
None
Add RAM to A
5-
10 1 0 11
A + y- A
Carry
Add Immediate, Skip on
Carry (Y" 0)
CLRA
00
10000100001
0- A
None
Clear A
COMP
40
10 1 00100001
A-A
None
One's complement of A to
A
NOP
44
10 1 0010 1 001
None
None
No Operation
RC
32
10 0 1 110 0 1 01
"0"- C
None
Reset C
SC
22
100 1 0100 1 01
"1" - C
None
Set C
XOR
02
10000100 1 01
A .. RAM(B)- A
None
Exclusive·OR RAM with A
AISC
Y
y
I
2-18
I
o
o
~
o
Table 3_ COP410U411L Instruction Set (continued)
Mnemonic Operand
Hex
Code
Machine
Language Code
(Binary)
Data Flow
Description
Skip Conditions
FF
JID
JMP
a
6-
-JP
a
None
a- PC
None
Jump
I
a - PC6:0
None
Jump within Page
(Note 3)
I
a - PC5:0
1
PC + 1 - SA - SB
1011o l000iasi
a7:0
I
Jump Indirect (Note 2)
ROM (PCS,A,M) PC7:0
11111111111
I
--
a6:0
111
(pages 2,3 only)
--
11 11
a5:0
(all other pages)
a
--
110 1
a5:0
6-
101101100iasi
--
I
RET
4S
RETSK
49
a
None
Jump to Subroutine Page
(Note 4)
None
Jump to Subroutine
10100110001
SB - SA - PC
None
Return from Subroutine
10100110011
SB - SA - PC
Always Skip on Return
Return from Subroutine
then Skip
A - 07:4
RAM(B) - 03:0
None
Copy A, RAM to 0
\
MEMORY REFERENCE INSTRUCTIONS
CAMO
LD
r
LOID
33
3C
10 0 1 110 0 1 11
\0011\1100/
-5
10 0 r 10 1 0 11
RAM(B)- A
Br .. r - Br
None
Load RAM into A,
Exclusive-OR Br with r
BF
11011111111
ROM(PCS,A,M) - 0
SA - SB
None
Load 0 Indirect (Note 2)
I
RMB
0
1
2
3
4C
45
42
43
10100111001
\ 0 1 0 0\0 1 0 1/
\0 1 00\00 1 01
10 1 00100 1 11
0000-
RAM(B)O
RAM(B)j
RAM(B)2
RAM(B)3
None
Reset RAM Bit
5MB
0
1
2
3
4D
47
46
4B
1010011 1011
10100101 1 11
10 1 0010 1 1 01
101001101 11
1111-
RAM(B)o
RAM(B)j
RAM(B)2
RAM(B)3
None
Set RAM Bit
STII
y
7-
10 1 1 11
y - RAM(B)
Bd+1-Bd
None
Store Memory Immediate
and Increment Bd
-6
1001 r 10 1 1 01
RAM(B)- A
Br .. r - Br
None
Exchange RAM with A,
Exclusive-OR Br with r
23
BF
100 1 0100 1 11
RAM(3,15) -
None
1101 111 1 1 11
Exchange A with RAM
(3,15)
XDS
-7
1001 r 101 1 11
RAM(B)- A
Bd-1-Bd
Br .. r - Br
Bd decrements past 0
Exchange RAM with A
and Decrement Bd,
Exclusive-OR Br with r
XIS
-4
1001 r 10 1 001
RAM(B) - A
Bd + 1 - Bd
Br .. r - Br
Bd increments past 15
Exchange RAM with A
and Increment Bd,
Exclusive-OR Br with r
X
XAD
3,15
y
o
o"tJ
~
o
C
o
PC + 1 - SA - SB
a- PC
a7:0
.....
o"tJ
010 - PCS:6
a - PC5:0
JSR
~
r
or
JSRP
?5
o"tJ
TRANSFER OF CONTROL INSTRUCTIONS
A
2-19
~
.....
r-
.,...
...I
Table 3. COP410Ll411L Instruction Set (continued)
2;
D-
O
~
c
2;
D-
O
o
...r
,...
;;:
Mnemonic Operand
Hex
Code
Machine
Language Code
(Binary)
Data Flow
Skip Conditions
Description
REGISTER REFERENCE INSTRUCTIONS
CAB
50
10 1 0 110 00 01
A- Bd
None
Copy A to Bd
CBA
4E
1010011 1101
Bd - A
None
Copy Bd to A
I
r,d - B
Skip until not a LBI
Load B Immediate with
r,d (Note 5)
y - EN
None
Load EN Immediate
(Note 6)
LBI
r,d
--
100 1 r I(d-l)
(d = 0,9:15)
LEI
Y
33
6-
10011100111
10110 1 y
D-
O
~
c
TEST INSTRUCTIONS
D-
SKC
20
10 0 1 010 0 0 01
C = "1"
Skip if C is True
o
SKE
21
10 0 1 010 0 0 11
A.= RAM(B)
Skip if A Equals RAM
SKGZ
33
10.0 1
G3:0 = 0
21
10 0 1 010 0 0 11
Skip if G is Zero
(all 4 bits)
;;:
O
SKGBZ
0
SKMBZ
I
110 0 1 11
33
100111001 11
1st byte
01
10 0 0 010 0 0 11
}~,~"
Skip if G Bit is Zero
GO = 0
1
11
10 0 0 110 0 0 11
2
03
10 0 0 010 0 1 11
3
13
10 0 0 110 0 1 11
0
01
10 0 0 010 0 0 11
1
11
10 0 0 110 0 0 11
RAM(B)O = 0
. RAM(Bh = 0
2
03
13
10 0 0 010 0 1 11
10 0 0 110'0 1 11
RAM(B)2 = 0
RAM(B)3 = 0
3
Gl = 0
G2 = 0
G3 = 0
Skip if RAM Bit is Zero
INPUT/OUTPUT INSTRUCTIONS
ING
INL
OBD
OMG
XAS
G-A
None
Input G Ports to A
L7:4 - RAM (B)
L3:0 - A
None
Input L Ports to RAM,A
1001011 1101
Bd - D
None
Output Bd to D Outputs
RAM(B)- G
None
Output RAM to G Ports
33
1001 11001 11
2A
10 0 1 011 0 1 01
33
1001 1100111
2E
33
10011100111
3E
1001 111 1 101
33
1001 11001 11
3A
1001 1110101
4F
1010011 1 111
;
A -'SIO, C - SKL
None
Exchange A with SIO
(Note 2)
Note 1: All subscripts for alphabetical symbols indicate bit numbers unless explicitly defined (e.g., Br and Bd are explicilly defined). Bits are
numbered 0 to N where 0 signifies the least significant bit (low-order, right-most bit). For example, A3 indicates the most significant (left-most)
bit o(the 4·bit A register.
Note 2: For additional information on the operation of the XAS, JID, and LQID instructions, see below.
Note 3: The JP instruction allows a jump, while in subroutine pages 2 or 3, to any ROM location within the two·page boundary of pages 2 or 3.
The JP Instruction, otherwise, permits a jump to a ROM location within the current 54·word page. JP may not jump to the last word of a page.
Note 4: A JSRP transfers program control to subroullne page 2 (0010 is loaded into the upper 4 bits of Pl. A JSRP may not be used when in pages
2 or 3. JSRP may not lump to the last word in page 2.
Note 5: The machine code for the lower 4 bits of the. LBI instruction equals the binary value of the "d" data minus 1, e.g., to load the lower four
bits of B (Bd) with the value 9 (10012), the lower 4 bits of the LBI instruction equal 8 (10002)' To load 0, the lower 4 bits of the LBI instruction
should equal 15 (11112).
Note 5: Machine code for operand fieid y for LEI Instruction should equal the binary value to be latched into EN, where a "1" or "0" in each bit of
EN corresponds with the selection or deselection of a particular function associated with each bit. (See Functional Description, EN Register.)
2-20
o
o
Option List
The following information is provided to assist the user
in understanding the operation of several unique instructions and to provide notes useful to programmers in
writing COP410Ll411 L programs_
The COP410Ll411L mask-programmable options are assigned numbers which correspond with the COP410L pins_
The following is a list of COP410L options. When specifying a COP411 L chip, Option 2 must be set to 3, Options
20,21, and 22 to O. The options are programmed at the
same time as the ROM pattern to provide the user with
the hardware flexibility to interface to various I/O components using little or no external circuitry.
XAS Instruction
XAS (Exchange A with SIO) exchanges the 4-bit contents
of the accumulator with the 4-bit contents of the SIO
register. The contents of SIO will contain serial-in/serialout shift register or binary counter data, depending on
the value of the EN register. An XAS instruction will also
affect the SK output. (See Functional Description, EN
Register, above.) If SIO is selected as a shift register, an
XAS instruction must be performed once every 4 instruction cycles to effect a continuous data stream.
Option 1 = 0: Ground Pin -
JID Instruction
JID (Jump Indirect) is an indirect addreSSing instruction,
transferring program control to a new ROM location
pointed to indirectly by A and M. It loads the lower a bits
of the ROM address register PC with the contents of
ROM addressed by the 9-bit word, PCs, A, M. PCs is not
affected by this instruction.
no options available
Option
= 0:
= 1:
= 2:
= 3:
2: CKO Output (no option available for COP411L)
Clock output to ceramic resonator
Pin is RAM power supply (V R) input
Multi-COP SYNC input
No connection
Option
=0:
= 1:
= 2:
3: CKI Input
Oscillator input divided by a (500kHz max.)
Single-pin RC controlled oscillator divided by 4
External Schmitt trigger level clock divided by 4
Option 4: RESET Input
= 0: Load device to Vee
= 1: Hi-Z input
Note that JID requires 2 instruction cycles to execute.
Option
= 0:
= 1:
= 2:
= 3:
= 4:
= 5:
LaiD Instruction
LQID (Load Q Indirect) loads the a-bit Q register with the
contents of ROM pOinted to by the 9-bit word PCs, A, M.
LQID can be used for table lookup or code conversion
such as 8CD to seven-segment. The LQID instruction
"pushes" the stack (PC + 1 - SA - S8) and replaces the
least significant a bits of PC as follows: A - PC 7:4,
RAM(8) - PC 3:o, leaving PCs unchanged. The ROM data
pOinted to by the new address is fetched and loaded
into the Q latches. Next, the stack is "popped" (S8 - SA
- PC), restoring the saved value of PC to continue
sequential program execution. Since LQID pushes SAS8, the previous contents of S8 are lost. Also, when
L.l.IIU pops me slacK, me preVIoUSlY pusneo Gomems 01
SA are left in S8. The net result is that the contents of
SA are placed in S8 (SA - S8). Note that LQID takes two
instruction cycle times to execute.
5: L7 Driver
Standard output
Open-drain output
High current LED direct segment drive output
High current TRI-STATE® push-pull output
Low-current LED direct segment drive output
Low-current TRI-STATE® push-pull output
Option 6: La Driver
same as Option 5
Option 7: Ls Driver
same as Option 5
Option 8: L4 Driver
C!~mQ ~C!
nntinn l:;,
Option 9: Vee Pin
=0: 4.5V to 6.3V operation
= 1: 4.5V to 9.5V operation
Option 10: L3 Driver
same as Option 5
Instruction Set Notes
a. The first word of a COP410Ll411L program (ROM
address 0) must be aCLRA (Clear A) instruction.
Option 11: L2 Driver
same as Option 5
b. Although skipped instructions are not executed, one
instruction cycle time is devoted to skipping each
byte of the skipped instruction. Thus all program
paths except JID and LQID take the same number of
cycle times whether instructions are skipped or executed. JID and LQID instructions take 2 cycles if executed and 1 cycle if skipped.
Option 12: L1 Driver
same as Option 5
Option 13: La Driver
same as Option 5
Option 14: SI Input
= 0: load device to Vee
= 1: HI-Z input
c. The ROM is organized into a pages of 64 words each.
The Program Counter is a 9-bit binary counter, and
will count through page boundaries. If a JP, JSRP,
JID or LQID instruction is located in the last word of
a page, the instruction operates as if it were in the
next page. For example: a JP located in the last word
of a page will jump to a location in the next page.
Also, a LQID or JID located in the last word of page 3
or 7 will access data in the next group of 4 pages.
Option
= 0:
= 1:
= 2:
15: SO Driver
Standard Output
Open-drain output
Push-pull output
Option 16: SK Driver
same as Option 15
2-21
"tI
~
o
C
o
o"tI
~
......
.r
o
o
"tI
~
o
a
o
"tI
~
......
r-
...I
.....
z;;
a..
Option 17: Go 1/0 Port
= 0: Standard output
= 1: Open-drain output
Option 25: L Input Levels
= 0: Standard TTL input levels ("0" = 0.8V, "1" = 2.0V)
= 1: Highervoltage input levels ("0" =1.2V, "1"=3.6V)
o.
Option 18: G1 1/0 Port
same as Option 17
Option 26: G Input Levels
. same as Option 25
§
z;;
a..
8
Option 19: G2 1/0 Port
same as Option 17
J.....
Option 20: G3 1/0 Port (no option available for COP411L)
same as Option 17
a..
Option 21: 0 3 Output (no option available for COP411L)
= 0: Very-high sink current standard output
=1: Very-high sink current open-drain output
= 2: High sink current standard output
= 3: High sink current open-drain output
= 4: Standard LSTTL output (fanout = 1)
= 5: Open-drain LSTTL output (fanout = 1)
:;;:
oo
::J
o
:;;:
a..
oo
Option 27: 51 Input Levels
same as Option 25
Option
= 0:
= 1:
= 2:
28: COP Bonding
COP410L (24-pin device)
COP411L (20-pin device)
Both 24- and 20-pin versions
Test Mode (Non-Standard Operation)
Option 22: O2 Output (no option available for COP411L)
same as Option 21
The SO output has been configured to provide for
standard test procedures for the custom-programmed
COP410L. With SO forced to logic "1", two test modes
are provided, depending upon the value of 51:
Option 23: 0 1 Output
same as Option 21
a. RAM and Internal Logic Test Mode (51 = 1)
b. ROM Test Mode (51 = 0)
Option 24: Do Output
same as Option 21
These special test modes should not be employed by
the user; they are intended for manufacturing test only.
2-22
o
o"tI
~National
~
~ Semiconductor
eo
COP420/COP421/COP422 and COP320/COP321/COP322
Single-Chip N-Channel Microcontrollers
Features
The COP420, COP421, COP422, COP320, COP321 and
COP322 Single-Chip N-Channel Microcontrollers are
members of the COPSTM family, fabricated using Nchannel, silicon gate MOS technology_ They are complete
microcomputers containing all system timing, internal
logic, ROM, RAM and I/O necessary to implement dedicated control functions in a variety of applications_ Features include single supply operation, a variety of output
configuration options, with an instruction set, internal
architecture and I/O scheme designed to facilitate keyboard input, display output and BCD data manipulation_
The COP421 is identical to the COP420, except with 19
I/O lines instead of 23; the COP422 has 151/0 lines_ They
are an appropriate choice for use in numerous human
interface control environments_ Standard test procedures
and reliable high-density fabrication techniques provide
the medium to large volume customers with a customized
Controller Oriented Processor at a low end-product cost.
• Low cost
• Powerful instruction set
~
o
o"tI
Co)
• True vectored interrupt, plus restart
• Three-level subroutine stack
• 4_0/-,s instruction time
• Single supply operation
• Internal time-base counter for real-time processing
• Internal binary counter register with MICROWIRETM
compatible serial I/O capability
o"tI
Co)
~
o
o
"tI
• TTL/CMOS compatible in and out
I\)
I\)
• LED direct drive outputs
• MICROBUSTM compatible
• Software/hardware compatible with other members
of COP400 family
• Extended temperature range device COP320/COP321/
COP322 (-40°C to +B5°C)
CKG
t,
I
""'~~"V~~LUCK
COUNTER
DIVIDER
GENERATOR
(DIVIDE 8'1' 1(24)
INSTRUCTION CLOCK {SYNC)
SKI
Ir=====~---"-- SOl MICROWIRE 110
SI
G3
G,
GJ"
Go·
12
~
o
• General purpose and TRI-STATE® outputs
LI
8
~
oo
,!')
• 1kxB ROM, 64x4 RAM
• 23 I/O lines (COP420, COP320)
OK'
1
-'="
"tI
General Description
The COP320 is the extended temperature range version
of the COP420 (likewise the COP321 and COP322 arEi
the extended temperature range versions of the COP421/
COP422)_ The COP320/321/322 are exact functional
equivalents of the COP420/421/422_
o"tI
\l
20 111 9
19
IN3' 1N2" 1Nl'INa'
14
15
* Not available on C9P322fCOP422.
Figure 1. COP420/COP4211COP422, COP320/COP321/COP322 Block Diagram
2-23
Co)
C\I
~
a..
o
S2
N
a..
oo
C')
(3
~
a..
o
o
~
a..
o
o
-
COP420/COP421/COP422 and COP320/COP321/COP322
Absolute Maximum Ratings
Voltage at Any Pin
Operating Temperature Range
CO P420/COP421/CO P422
CO P320/CO P321/CO P322
Storage Temperature Range
Total Sink Current
Total Source Current
COP420/CO P421 ICO P422
DC Electrical Characteristics
Lead Temperature (soldering, 10 sec.)
O°C", TA ", 70°C, 4.5V '" Vce'" 6.3V unless otherwise noted.
Max.
4.5
6.3
V
Peak to Peak (Note 3)
0.4
V
Supply Current
Outputs Open
38
mA
Supply Current
Outputs Open,
Vee =5V, TA=25°C
30
mA
3.0
2.0
-0.3
0.4
V
V
2.0
-0.3
0.8
V
V
0.7 Vee
-0.3
2.0
0.6
3.0
V
V
V
3.0
2.0
-0.3
0.8
V
V
V
3.6
-0.3
1.2
V
V
-4
-100
-800
-800
Il A
Il A
7
pF
-1
+1
Il A
o
oo
Package Power Dissipation
20pin
Min.
Parameter
Operation Voltage
~a..
O°Cto 70°C
-40°C to +85°C
-65°C to +150°C
75mA
95mA
750 mW at 25°C
400 mW at 70°C
250 mW at 85°C
650 mW at 25°C
300 mW at 70°C
200mWat 85°C
300°C
Package Power Dissipation
24 and 28 pin
Absolute maximum ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings.
N
o::t
a..
o
-0.3Vto+7V
Power Supply Ripple
Input Voltage Levels
CKI Input Levels
Crystal Input
Logic High
Logie High
Logic Low
TTL Input
Logic High
Logic Low
Schmitt Trigger Inputs
RESET, CKI (+4)
Logic High
Logic Low
SO Input Level (Test Mode)
All Other Inputs
Logic High
Logic High
Logic Low
Input Levels High Trip Option
Logic High
Logic Low
Input Load Source Current
CKO
All Others
Conditions
Vee = Max.
Vee=5V±5%
Units
Vee=5V±5%
Vee = Max.
Vee=5V±5%
Vee = 5V, VIN = OV
Input Capacitance
Hi-Z Input Leakage
Vee=5V
Output Voltage levels
Standard Outputs
TTL Operation
Logic High
Logic Low
CMOS Operation
Logic High
Vee=5V±5%
IOH =-100 IlA
IOL= 1.6mA
2.4
-0.3
IOH =-10IlA
Vee- 1
2-24
0.4
V
V
V
I
o
o-a
COP42Q/COP421/COP422
DC Electrical Characteristics
(Cont'd)
Parameter
Output Current Levels
LED Direct Drive Output
Logic High
CKI Sink Current (RIC Option)
CKO (RAM Supply Current)
TRI-STATE® or Open Drain
Leakage Current
Output Current Levels
Output Sink Current (loll
o·c .. TA .. 70·C, 4.5V .. Vee" 6.3V unless otherwise noted.
Conditions
Vee=6V
VOH =2.0V
V1N =3.5V
VR=3.3V
Min.
Max.
Units
2.5
2
14
mA
mA
mA
3
~
Vee=5V
-2.5
Vee=6.3V, Vo L =O.4V
Vee = 4.5 V, VOL = 0.4 V
-2.0
-1.0
Vee = 6.3 V, VOH = 3.0 V
Vee = 4.5V, VOH=2.0V
-200
-100
Vee = 6.3V, VOH = 3.0V
Vee=4.5V, VOH=2.0V
-1.0
-0.4
mA
rnA
Vee = 6.3 V, VO H = 3.0V
Vee = 4.5 V, VOH = 2.0V
-2.0
-0.8
mA
mA
Vee = 6.3V, VO H = 3.0V
Vee = 4.5V, VOH=2.0V
-1.0
-0.5
mA
mA
+2.5
Push-Pull Configuration
SO, SK Outputs
-900
-500
;/
LED Configuration
YJ-L7 Outputs
Allowable Sink Current
Per Pin (L, D, G)
Per Pin (All Others)
Per Port (L)
Per Port (D, G)
Allowable Source Current
Per Pin (L)
Per Pin (All Others)
2-25
-a
~
8-a
/AA
/AA
o
TRI-STATE Configuration
YJ-L7 Outputs
!§
o
o
mA
mA
Output Source Current (lOH)
Standard Configuration
All Outputs
~
o-a
10
2
16
10
mA
mA
mA
rnA
-15
-1.5
mA
rnA
~
-a
Co)
-oo
~
-a
~
I\)
~c..
oo
COP320/COP321/COP322
-~
DC Electrical Characteristics
o
~
Power Supply Ripple
Peak to Peak (Note 3)
0.4
V
Supply Current
TA = -40°C, Outputs Open
40
mA
2.2
-0.3
0.3
V
V
2.2
-0.3
0.6
V
V
0.7Vee
-0.3
2.0
0.4
3.0
V
V
V
3.0
2.2
-0.3
0.6
V
V
V
3.6
-0.3
1.2
V
V
-4
-100
-800
-800
7
"A
"A
pF
-2
+2
"A
c..
~
c..
oo
N
~
c..
o
~
~
c..
oo
a
c..
o
o
Parameter
-40°C
~
TA
~
+85°C, 4.5V
~
Conditions
Operation Voltage
Input Voltage Levels
CKI Input Levels
Crystal Input
Logic High
Logic Low
TTL Input
Logic High
Logic Low
Schmitt Trigger Inputs
RESET, CKI (+4)
Logic High
Logic Low
SO Input Level (Test Mode)
All Other Inputs
Logic High
Logic High
Logic Low
Input Levels High Trip Option
Logic High
Logic Low
Input Load Source Current
CKO
All Others
Vee
~
5.5V unless otherwise noted.
Min.
Max.
Units
4.5
5.5
V
Vee=5V±5%
Vee = Max.
Vee=5V±5%
Vee = 5V, VIN = OV
Input Capacitance
Hi·Z Input Leakage
,
Output Voltage levels
Standard Outputs
TTL Operation
Logic High
Logic Low
CMOS Operation
Logic High
Logic Low
Vee=5V
Vee=5V±5%
IOH =-75"A
IOl=1.6mA
2.4
-0.3
0.4
V
V
IOH =-10"A
IOl= 10"A
Vee- 1
-0.3
0.2
V
V
Output Current Levels
LED Direct Drive Output
Logic High
CKI Sink Current (RIC Option)
CKO (RAM Supply Current)
Vee = 5V (Note 4)
VO H =2.0V
VIN =3.5V
VR=3.3V
1.0
2
TRI·STATE® or Open Drain
Leakage Current
Vee=5V
-5
Allowable Sink Current
Per Pin (L, 0, G)
Per Pin (All Others)
Per Port (L)
Per Port (0, G)
Allowable Source Current
Per Pin (L)
Per Pin (All Others)
2-26
12
4
mA
mA
mA
+5
"A
10
2
16
10
mA
mA
mA
mA
-15
-1.5
mA
mA
AC Electrical Characteristics
COP420/COP421/COP422
COP320/COP321/COP322
O°C ..TA .. 70°C, 4.5V .. Vc c .. 6.3V unless otherwise noted.
-40°C .. TA .. +B5°C, 4.5V .. Vcc .. 5.5V unless otherwise noted.
Parameter
Conditions
Instruction Cycle Time
Operating CKI Frequency
CKI Duty Cycle (Note 1)
Rise Time
Fall Time
CKI Using RC (Figure Bc)
Frequency
Instruction Cycle Time
CKO as SYNC input (Figure Bd)
tsyNc
Inputs:
SI
tSETUP
tHOLO
All Other Inputs
tSETUP
tHOLO
Output Propagation Delay
SO and SK
tpd1
tpdO
CKO
tpd1
tpdO
All Other Outputs
tpd1
tpdo
MICROBUSTM Timino
+16 mode
+B mode
Min.
Figure 3a
Test Conditions:
RL=5kQ, CL =50pF, VouT =1.5V
Units
4
10
1.6
O.B
4.0
2.0
I's
MHz
MHz
40
60
60
40
%
ns
ns
0.5
4
1.0
B
MHz
I's
Freq. =4MHz
Freq.=4MHz
+4 mode
R=15kQ±5%, C=100pF±10%
Max.
50
ns
0.3
250
I's
ns
1.7
300
I's
ns
300
ns
1.0
1.0
I's
I's
0.25
0.25
I's
I'S
1.4
1.4
I's
I's
375
250
ns
ns
ns
ns
ns
700
ns
ns
ns
ns
ns
ns
C, =100oF. Vr.r.=5V±5%
Read Operation (Figure 4)
Chip Select Stable before RD-tCSR
Chip Select Hold Time for RD-tRCS
RD Pulse Width-t RR
Data Delay from RD-tRO
RD to Data Floating-toF
65
20
400
Write Operation (Figure 5)
Chip Select Stable before WR-tcsw
Chip Select Hold Time forWR-twcs
WR Pulse Wldth-tww
Data Set-Up Time for WR-tow
Data Hold Time for WR-two
INTR Transition Time from WR-twi
65
20
400
320
100
Note 1: Duty cycle = tW1/(tW1 + two).
Note 2: See Figure 9 for additional I/O characteristics.
Note 3: Voltage change must be less than 0.5 volts in a 1 ms period.
Note 4: Exercise great care not to exceed maximum device power dissipation limits when direct driving LEOs (or sourcing similar
loads) at high temperature.
2-27
N
~
Q.
o
-
GNO
CKO
CKI
o
~
Q.
o
REID
L7
L6
L5
L4
INI
IN2
VCC
L3
L2
S:2
~
Q.
oo
l1
N
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
00
01
02
03
G3
G2
Gl
GO
IN3
INO
SK
SO
SI
LO
GNO
CKO
CKI
iiffi"f
L7
L6
L5
L4
VCC
L3
L2
l1
COP420, COP320
N
00
01
02
03
G3
G2
Gl
GO
SK
SO
SI
LO
24
23
22
21
20
19
18
17
16
15
14
13
10
11
12
CKO
20
GNO
CKI
19
02
RESET
18
U3
L7
17
G3
L6
16
G2
L5
15
SK
L4
14
SO
VCC
13
SI
12
LO
11
Ll
l3
L2
10
COP422, COP322
COP421, COP321
~
Q.
Order Number COP420N, COP320N
NS Package N28A
o
Order Number COP422N, COP322N
NS Package N20A
Order Number COP421N, COP 321N
NS Package N24A
S:2
Figure 2. Connection Diagrams
N
~
Q.
o
~
Pin
8 bidirectional 1/0 ports with TRI-STATE@
~
Ga-G a
4 bidirectional 1/0 ports
oo
Da-Da
4 general purpose outputs
Q.
Description
Pin
Description
L7-Lo
INa-INa'
4 general purpose inputs (COP420/320
only)
SI
Serial input (or counter input)
SO
Serial output (or general purpose output)
SK
Logic-controlled clock (or general
purpose output)
CKI
System oscillator input
CKO
System oscillator output (or general
purpose input or RAM power supply)
RESET
System reset input
Vee
Power supply
GND
Ground
CKI
,.;..;;.;",:1.:-".------;...... 1- tpoo
SK lAS A
CLOCK
IN3-INo.
L
G3- GO
.........
VO"'L':-~=___+;---'
tSETUP
tHOLO
I-
--I I--
ckJi. 8i _________-:-__.Jx"'--:___--Jx......______
INPUTS
r.tP01-+1
GC;~~o.~t~~~
I
~VOH
OUTPUTS
Figure 3. Input/Output Timing Diagrams (crystal divide by 16 model
CKI
CKIJLnJ
-I
CKO
(INPUT)
\
~~lj
[-- tSYNCO
I
tPo~tPOO
1
.
Figure 3B. CKO Output Timing
Figure 3A. Synchronization Timing
2-~
(')
IIN11
All
(L)-LOI
D)-DO
•
tRR
---+---,.,\1'
\1'-----,-----',
-tcSR-I~tRD--t
~ tRes
o"'D
~
1
--':'1
~
_ t D F _____
----------t{_____________.
\
IIN31
(L)-LOI
I
_ twcs
-!.
1
___ tow_
WR
---
D)-DO
,
(Gol
tww
tWI
.
two
o"'D
~
~
(;
Figure 4. MICROBUS™ Read Operation Timing
tcsw-. •
e
(')
.1X
INTR
o"'D
~
j')
(')
o"'D
(A)
~
(')
Figure 5. MICROBUS™ Write Operation Timing
o"'D
CN
~
Functional Description COP420/COP421/COP422, COP320/COP321/COP322
of 16 4·bit digits in the selected data register. While the
4-bit contents of the selected RAM digit (M) is usually
loaded into or from, or exchanged with, the A register
(accumulator), it may also be loaded into or from the a
latches or loaded from the L ports. RAM addressing
may also be performed directly by the LDD and XAD
instructions based upon the 6-bit contents of the
operand field of these instructions. The Bd register also
serves as a source register for 4-bit data sent directly to
the. D outputs.
For ease of reading this description, only COP420 and/or
COP421 are referenced; however, all such references
apply equally to the COP422, COP322, COP320 and/or
COP321, respectively.
A block diagram of the COP420 is given in figure 1. Data
paths are illustrated in simplified form to depict how the
various logic elements communicate with each other in
implementing the instruction set of the device. Positive
logic is used. When a bit is set, it is a logic "1" (greater
than 2 volts). When a bit is reset, it is a logic "0" (less
than 0.8 volts).
Internal Logic
The 4-bit A register (accumulator) is the source and
rlg,,!in,,!inn rAni"tAr for most I/O. arithmetic, logic and
data memory access operations. It can also be used to
load the Br and Bd portions of the B register, to load and
input 4 bits of the 8-bit a latch data, to input 4 bits of the
8-bit L I/O port data and to perform data exchanges with
the SIO register.
Program Memory
Program Memory consists of a 1,024 byte ROM. As can
be seen by an examination of the COP420/421 instruction
set, these words may be program instructions, program
data or ROM addressing data. Because of the special
characteristics associated with the JP, JSRP, JID and
LaID instructions, ROM must often be thought of as
being organized into 16 pages of 64 words each.
A 4-bit adder performs the arithmetic and logic functions of the COP420/421, storing its results in A. It also
outputs a carry bit to the 1-bit C register, most often employed to indicate arithmetic overflow. The C register, in
conjunction with the XASinstruction and the EN register,
also serves to control the SK output. C can be outputted
directly to SK or can enable SK to be a sync clock each
instruction cycle time. (See XAS instruction and EN register description, below.)
ROM addressing is accomplished by a 10-bit PC
register. Its binary value selects one of the 1,024 8-bit
words contained in ROM. A new address is loaded into
the PC register during each instruction cycle. Unless
the instruction is a transfer of control instruction, the
PC register is loaded with the next sequential 10-bit
binary count value. Three levels of subroutine nesting
are implemented by the 10-bit subroutine save registers,'
SA, SB and SC, providing a last-in, first-out (LIFO)
hardware subroutine stack.
Four general-purpose inputs, IN3-INo, are provided; IN 1 ,
IN2 and IN3 may be selected, by a mask-programmable
option, as Read Strobe, Chip Select and Write Strobe
inputs, respectively, for use in MICROBUSTM applications.
.
ROM instruction words are fetched, decoded and executed by the Instruction Decode, Control and Skip Logic
circuitry.
The D register provides 4 general-purpose outputs and
is used as the destination register for the 4-bit contents
of Bd.
Data Memory
Data memory consists of a 256-bit RAM, organized as 4
data registers of 16 4-bit digits. RAM addressing is
implemented by a 6-bit B register whose upper 2 bits (Br)
select 1 of 4 data registers and lower 4 bits (Bd) select 1
The G register contents are outputs to 4 general-purpose
bidirectional I/O ports. Go may be mask-programmed as
an output for MICROBUSTM applications.
2-29
(;
o"'D
~
N
N
~
D-
O
~
~
D-
O
~
~
D-
O
o
N
~
DO
~
~
D-
O
o
a
~
DO
o
The Q register is an internal, latched, 8-bit register, used
to hold data loaded to or (rom M and A, as well as 8-bit
data from ROM. Its contents are output to the L I/O
ports when the L drivers are enabled under program
control. (See LEI instruction). With the MICROBUSTM
option selected, Q can also be loaded with the 8·bit
contents of the L I/O ports upon the occurence of
write strobe from the host CPU.
1. The least significant bit of the enable register, ENo,
selects the SIO register as either a 4·bit shift register
or a 4·bit binary counter. With ENo set, SIO is an
asynchronous binary counter, decrementing its value
by one upon each low·going pulse ("I" to "0")
ocurring on the SI input. Each pulse must be at least
two instruction cycles wide. SK outputs the value of
SKL. The SO output is equal to the value of EN 3. With
ENo reset, SIO is a serial shift register shifting left
each instruction cycle time. The data present at SI
goes into the least significant bit of SIO. SO can be
enabled to output the most significant bit of SIO
each cycle time. (See 4 below.) The SKoutput becomes
a logic·controlled clock.
a
The 8 L drivers,when enabled, output the contents of
latched Q data to the L I/O ports. Also, the contents of L
may be read directly into A and M. As explained above,
the MICROBUSTM option allows L I/O port data to be
latched into the Q register. L I/O ports can be directly
connected to the segments of a multiplexed LED display
(using the LED Direct Drive output configuration option)
with Q data being outputted to the Sa-Sg and decimal
point segments of the display.
2. With EN 1 set the IN1 input is enabled as an interrupt
input. Immediately fOllowing an interrupt, EN1 is
reset to disable further interrupts.
The SIO register functions as a 4-bit serial·in/serial-out
shift register or as a binary counter depending on the
contents of the EN register. (See EN register description,
below.) Its contents can be exchanged with A, allowing
it to input or output a continuous serial data stream.
SIO may also be used to provide additional parallel I/O
, by connecting SO to external serial-in/parallel·out shift
registers. For example of additional parallel output cap·
acity see Application #2.
3. With EN2 set, the L drivers are enabled to output the
data in Q to tlW L I/O ports. Resetting EN2 disables
the L drivers, placing the L I/O ports in a high·
impedance input state.
'
4. EN 3, in conjunction with ENo, affects the SO output.
With ENo set (binary counter option selected) SO will
output the value loaded into EN 3. With ENo reset
(serial shift register option selected), setting EN3
enables SO as the output of the SIO shift register,
outputting serial shifted data each instruction time.
Resetting EN3 with the serial shift register option
selected disables SO as the shift register output;
data continues to be shifted through SIO and can be
exchanged with A via an XAS instruction but SO
remains reset to "0." The table below provides a
summary of the modes associated with EN3 and ENo.
The XAS instruction copies C into the SKL latch. In the
counter mode, SK is the output of SKL; in the shift
register mode, SK outputs SKL ANDed with the clock.
The EN register is an internal 4-bit register loaded under
program control by the LEI instruction. The state of
each bit of this register selects or deselects the
particular feature associated with each bit of the EN
register (EN3- EN o).
Enable Register Modes -
Bits EN3 and ENO
EN3
ENo
SIO
SI
SO
0
0
Shift Register
Input to Shift Register
0
SK
If SKL= 1, SK = CLOCK
If SKL = 0, SK = 0
1
0
Shift Register
Input to Shift Register
Serial Out
If SKL = 1, SK = CLOCK
If SKL = 0, SK = 0
0
1
Binary Counter
Input to Binary Counter
0
If SKL = 1, SK = 1
If SKL = 0, SK = 0
1
1
Binary Counter
Input to Binary Counter
1
IfSKL = 1,SK = 1
If SKL = 0, SK = 0
2-30
(")
o"'D
Interrupt
The following features are associated with the IN1
interrupt procedure and protocol and must be considered by the programmer when utilizing interrupts.
"p on the WR line, providing the "handshaking capability
necessary for asynchronous data transfer between the
host CPU and the COP420.
a. The interrupt, once acknowledged as explained
below, pushes the next sequential program counter
address (PC + 1) onto the stack, pushing in turn the
contents of the other subroutine-save registers to the
next lower level (PC + 1 - SA - SB - SC). Any
previous contents of SC are lost. The program counter
is set to hex address OFF (the last word of page 3)
and EN1 is reset.
This option has been designed for compatibility with
National's MICROBUSTM - a standard interconnect
system for S-bit parallel data transfer between MOS/LSI
CPUs and interfacing devices. (See MICROBUSTM
National Publication.) The functioning and timing relationships between the COP420 signal lines affected by
this option are as specified for the MICROBUSTM
interface, and are given in the AC electrical characteristics and shown in the timing diagrams (figures 4 and 5).
Connection of the COP420 to the MICROBUSTM is
shown in Figure 6.
b. An interrupt will be acknowledged only after the
following conditions are met:
1. EN1 has been set.
POWER
SUPPL Y
2. A low-going pulse ("1" to "0") at least two instruction cycles wide occurs on the IN1 input.
3. A currently executing instruction has been completed.
!§
(=)
o"'D
~
~N
(")
o"'D
N'
e(")
o"'D
a·BIT OATA BUS
MICROPROCESSOR
o"'D
fA)
CLOCK
INTERRUPT IINTRJ
4. All successive transfer of control instructions and
successive LBls have been completed (e.g., if the
main program is executing a JP instruction which
transfers program control to another JP instruction,
the interrupt will not be acknowledged until the
second JP instruction has been executed.
~
e(")
fA)
-o
~
REAO STROBE (Rill
CHIP SElECT ICSI
WRITE STROBE IWRI
IN
SK
OUT
( ")
"'D
fA)
~
c. Upon acknowledgement of an interrupt, the skip
logic status is saved and later restored upon popping
of the stack. For example, if an interrupt occurs
during the execution of ASC (Add with Carry, Skip on
Carry) instruction which results in carry, the skip
logic status is saved and program control is transferred to the interrupt servicing routine at hex
address OFF. At the end of the interrupt routine, a
RET instruction is executed to "pop" the stack and
return program control to the instruction following
the original ASC. At this time, the skip logic is
enabled and skips this instruction because of the
previous Atilj carry. ;:)uoroullnes ana LI..IIU III:;lIUV
tions should not be nested within the interrupt service routine, since their popping the stack will enable
any previously saved main program skips, interfering
with the orderly execution of the interrupt routine.
Figure 6. MICROBUS™ Option Interconnect
Initialization
The Reset Logic, internal to the COP420/421, will initialize (clear) the device upon power-up if the power supply
rise time is less than 1ms and greater than 1"s. If the
power supply rise time is greater than 1 ms, the user
must orovide an external RC network and diode to the
RESET pin as shown below. The RESET pin is contigurea
as a Schmitt trigger input. If not used it should be connected to Vee. Initialization will occur whenever a logic
"0" is applied to the RESET input, provided it stays low
for at least three instruction cycle times.
d. The first instruction of the interrupt routine at hex
address OFF must be a NOP.
Upon initialization, the PC register is cleared to 0 (ROM
address 0) and the A, B, C, D, EN, and G registers are
cleared. The SK output is enabled as a SYNC output,
providing a pulse each instruction cycle time. Data
Memory (RAM) is not cleared upon initialization. The
first instruction at address 0 must be a CLRA.
e. A LEI instruction can be put immediately before the
RET to re-enable interrupts.
Microbus™ Interface
The COP420 has an option which allows it to be used as
a peripheral microprocessor device, inputting and outputting data from and to a host microprocessor (JAP).
IN 1, IN2 and IN3 general purpose inputs become
MICRO~USTM compatible read-strobe, chip-select, and
write-strobe lines, respectively. IN1 becomes RD - a
logic "0" on this input will cause Q latch data to be
enabled to the L ports for input to the "P. IN2 becomes
CS - a logic "0" on this line selects the COP420 as the
"p peripheral device by enabling the operation of the RD
and WR lines and allows for the selection of one of
several peripheral components. IN3 becomes WR - a
logic "0" on this line will write bus data from the L ports
to the Q latches for input to the COP420. Go becomes
INTR a "ready" output, reset by a write pulse from the
P
o
W
E
R
S
+-_.....---..,
VCC
RESET COP42D/421
U
P
P
L
Y
RC" 5 x POWER SUPPLY RISE TIME
Figure 7. Power-Up Clear Circuit
2-31
gf
C"')
c.
Oscillator
CKO Pin Options
o(J
There are four basic clock oscillator configurations
available as shown by figure 8.
N
a. Crystal Controlled Oscillator. CKI and CKO are
connected to an external crystal. The instruction
cycle time equals the crystal frequency divided by 16
(optional by 8).
In a crystal controlled oscillator system, CKO is used as
an output to the crystal network. As an option CKO can
be a SYNC input as described above. As another option
CKO can be a general purpose input, read into bit 2 of A
(accumulator) upon execution of an INIL instruction. As
another option, CKO can be a RAM power supply pin
(VA), allowing its connection to a standby/backup power
supply to maintain the integrity of RAM data with minimum power drain when the main supply is inoperative
or shut down to conserve power. Using either option is
appropriate in applications where the COP420/421 system timing configuration does not require use of the
CKO pin.
C"')
c.
o(J
~
C"')
c.
o(J
gf~
o::t
C.
o
~
~
o
c.
g
~
c.
o(J
b. External Oscillator. CKI is an external clock input
signal. The external frequency is divided by 16
(optional by 8) to give the instruction cycle time. CKO
is now available to be used as the RAM power supply
(VA) or as a general purpose input.
c. RC Controlled Oscillator. CKI is configured as a
single pin RC controlled Schmitt trigger oscillator.
The instruction cycle equals the oscillation frequency
divided by 4. CKO is available for non·timing func·
tions.
RAM Keep-Alive Option (Not available on COP422)
Selecting CKO as the RAM power supply (VA) allows the
user to shut off the chip power supply (Vce) and
maintain data in the RAM. To insure that RAM data
integrity is maintained, the following conditions must
be ,met:
d. Externally Synchronized Oscillator. Intended for use
in multi·COP systems, CKO is programmed to function
as an input connected to the SK output of another
COP420/421 with CKI connected as shown. In this
configuration, the SK output connected to CKO must
provide a SYNC (instruction cycle) signal to CKO,
thereby allowing synchronous data transfer between
the COPs using only the SI and SO serial I/O pins in
conjunction with the XAS instruction. Note that on
power· up SK is automatically enabled as a SYNC output (See Functional Description, Initialization, above).
1. RESET must go low before Vce goes below spec during
power off; Vee must be within spec before RESET goes
high on power up.
2. VA must be within the operating range of the chip,
and equal to Vec ± 1V during normal operation.
3. VA must be ;;'3.3V with Vee off.
COP420142t
.J1..J
EXTERNAL
CLOCK
Crystal Oscillator
COP4201421
so
(VR OR GENERAL
so
PURPOSE INPUT
PINl
External Oscillator
RC Controlled Oscillator
Externally Synchronized Oscillator
RC Controlled Oscillator
Crystal Oscillator
Crystal
Value
R (kQ)
C (pF)
Instruction
Cycle Time
(I's)
12
6.8
8.2
22
100
220
300
100
5±20%
5.3±23%
8±29%
8.6± 16%
Component Values
R1 (Q)
R2 (Q)
1M
C (pF)
27
4MHz
1k
3.58MHz
1k
1M
27
2.09 MHz
1k
1M
56
Note: 50kQ ;;. R;;. 5kQ
360pF;;. C;;' 50pF
Figure B. COP420/421/COP320/321 Oscillator
2-32
o
o"'D
1/0 Options
COP420/421 outputs have the following optional configurations, illustrated in Figure 9a:
COP420/COP421 inputs have the following optional
configurations:
~
S2
a_ Standard - an enhancement mode device to ground
in conjunction with a depletion-mode device to Vee,
compatible with TTL and CMOS input requirements.
Available on SO, SK, and all D and G outputs.
h. An on-Chip depletion load device to Vee.
o"'D
b. Open-Drain - an enhancement-mode device to
ground only, allowing external pull-up as required by
the user's application. Available on SO, SK, and all D
and G outputs.
The above input and output configurations share common enhancement·mode and depletion-mode devices.
Specifically, all configurations use one or more of six
devices (numbered 1- 6, respectively). Minimum and
maximum current (lOUT and VOUT) curves are given in
Figure 9b for each of these devices to allow the
designer to effectively use these 1/0 configurations in
designing a COP420/421 system.
i. A Hi-Z input which must be driven to a "1" or "0" by
external components.
c. Push-Pull - An enhancement-mode device to ground
in conjunction with a depletion-mode device paralleled
by an enhancement-mode device to Vee. This configuration has been provided to allow for fast rise and fall
times when driving capacitive loads. Available on SO
and SK outputs only.
The SO, SK outputs can be configured as shown in a.,
b., or c. The D and G outputs can be configured as
shown in a. or b. Note that when inputting data to the G
ports, the G outputs should be set to "1." The L outputs
can be configured as in d., e., f. or g.
d. Standard L - same as a., but may be disabled.
Available on L outputs only.
e_ Open Drain L - same as b., but may be disabled.
Available on L outputs only.
An important paint to remember if using configuration
d. or f_ with the L drivers is that even when the L drivers
are disabled, the depletion load device will source a
small amount of current (see Figure 9b, device 2);
however, when the L lines are used as inputs, the
disabled depletion device can not be relied on to source
sufficient current to pull an input to logic "1".
f. LED Direct Drive - an enhancement-mode device to
ground and to Vee, meeting the typical current
sourcing requirements of the segments of an LED
display. The sourcing device is clamped to limit
current flow. These devices may be turned off under
program control (See Functional Description, EN
Register), plaCing the outputs in a high-impedance
state to provide required LED segment blanking for a
multiplexed display.
g. TRI-STATE® Push-Pull - an enhancement-mode device to ground and Vee. These outputs are TRI-STATE
outputs, allowing for connection of these outputs to
a data bus shared by other bus drivers.
a. Standard Output
COP421
If the COP420 is bonded as a 24-pin device, it becomes
the COP421, illustrated in Figure 2, COP420/421 Connection Diagrams. Note that the COP421 does not contain
the four general purpose IN inputs (IN3 -INo). Use of this
option precludes, of course, use of the IN options, interrupt feature, and the MICROBUSTM option which uses
IN 1 -IN 3. All other options are available for the COP421.
c. Push·Pull Output
b. Open· Drain Output
""Bl'~~
(&IS DEPLETION DEVICE)
d. Standard L Output
e. Open· Drain L Output
f. LED (L Output)
'cc
c;?"
'''"'~(
g.
TRI·STATE~
Push·Pull (L Output)
h. Input with Load
Figure 9a. Input/Output Configurations
2-33
i. HI·Z Input
o
~
o
o
"'D
~
N
j\)
o
o"'D
Co)
N
o
oo
"'D
~
oo
"'D
Co)
N
N
~
L Output Depletion Load OFF
0..
o
Output Sink Current
1/
N
C")
0..
J..r-
10
o
L
~
II
oo
a
o
I'..
-1.0
l/VCC = 4.5V (MIN)
VCC=5.5V
(MIN)
I\)
I\)
DEVICE 2 AND 3
-10
-R
::>
,,
,
-4~,~'-+--+-4-~
3
4
VOUT (VOLTS)
o L---'_-'-_-'----J
DEVICE 4 AND 2
4~
TRISTATE OUTPUT SOURCE CURRENT
~5
LO
VCC (VOLTS)
L5
LO
DEVICE 4 AND 2
INPUT LOAD SOURCE CURRENT
-0.2 f-!...---4-+~~~:--+2
4
VOUT (VOLTS)
3
4
VOUT (VOLTS)
DEVICE 5
Figure 9c. COP320/COP321 Input/Output Characteristics
2-35
~
n
o
c;,.)
;;C
2
o""0
4
I--+--hf-.-f--
-6
~
2
-14 1--1--+--,A--
::
~
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""0
LED OUTPUT SOURCE CURRENT
§.
o""0
I'.
LED OUTPUT DEVICE LED DRIVE
-12
(')
1\..' ~
VOUT (VOLTS)
DEVICE 2
!"
c;,.)
\ 1/
~14.5V' \ /
[/\
f...." II...
4
VOUT (VOLTS)
VCC =14.5V
(MAXlr
\ 1\
VCC
- 0.5 (MIN)
>."-.-'" ~
(MAX
\
-2.0
:: -1. 5
VC~X;t5V
1
1\
-2. 5
::
-
~
-0.25
DEVICE 2
-3. 0
I
'\
f:)
PUSH PULL SOURCE CURRENT
\
-0.5 (MI~
""0
~NI\
E
_-:\
VCC - 5.5V
n
o
VOUT (VOLTS)
['XVCC =4.5V (MAi)
1 .0
.....
§-0.75
!::i
DEVICE 1
VCC = 5.5V (MAX)
"<
.;..
~AX
STANDARD OUTPUT SOURCE CURRENT
-1.75
~
~
(')
1/ .rC=rV (jIN)_
10
o""0
DEVICE 6
~
oo
0.
-~
COP420/COP421/COP422/COP320/COP321/COP322 Instruction Set
0.
o
~
Table 2 provides the mnemonic, operand, machine code,
data flow, skip conditions, and description associated
with each instruction in the COP420/COP421/COP422
instruction set.
Table 1 is a symbol table providing internal architecture,
instruction operand and operational symbols used in
the instruction set table.
Table 2. COP420/4211422/320/321/322 Instruction Set Table Symbols
Definition
Symbol
Definition
Symbol
~
INTERNAL ARCHITECTURE SYMBOLS
INSTRUCTION OPERAND SYMBOLS
oo
A
B
Br
Bd
C
D
EN
d
4-bit Operand Field, 0-15 binary (RAM Digit
Select)
r
2-bit Operand Field, 0-3 binary (RAM Register
Select)
a
10-bit Operand Field, 0-1023 binary (ROM
Address)
y
4-bit Operand Field, 0-15 binary (Immediate
Data)
0.
~
"lit
0.
o
~
~
0.
o
~
"lit
G
IL
IN
L
M
0.,
o
o
PC
Q
SA
SB
SC
SIO
SK
4-bit Accumulator
6-bit RAM Address Register
Upper 2 bits of B (register address)
Lower 4 bits of B (digit address)
1-bit Carry Register
4-bit Data Output Port
. 4-bit Enable Register
4-bit Register to latch data for G 1/0 Port
Two 1-bit latches associated with the IN3 or
INa inputs
4-bit Input Port
8-bit TRI-STATE® 1/0 Port
4-bit contents of RAM Memory pointed to by
B Register
10-bit. ROM Address Register (program
counter)
8-bit Register to latch data for L 1/0 Port
10-bit Subroutine Save Register A
10-bit Subroutine Save Register B
10 Subroutine Save Register A
4-bit Shift Register and Counter
Logic-Controlled Clock Output
RAM(s) Contents of RAM location addressed by s
ROM(t) Contents of ROM location addressed by t
OPERATIONAL SYMBOLS
+
~
-
Plus
Minus
Replaces
Is exchanged with
=
Is equal to
A
The one's compler:nent of A
Exclusive-OR
:
Range of values
Table 2. COP420/4211422/320/3211322 Instruction Set
Mnemonic Operand
Hex
Code
Machine
Language Code
(Binary)
Data Flow
Skip Conditions
Description
ARITHMETIC INSTRUCTIONS
ASC
30
10011100001
A+C+ RAM(B) - A
Carry - C
Carry
Add with Carry, Skip on
Carry
ADD
31
1°°111°°011
A+RAM(B)- A
None
Add RAM to A
ADT
4A
101 ° °11 01 01
A+1010- A
None
Add Ten to A
5-
1° 101 1
A+y- A
Carry
Add Immediate, Skip on
Carry (y '" 0)
CASC
10
10 ° 01 10 ° 0 01
A + RAM(B) + C - A
Carry - C
Carry
Complement and Add with
Carry, Skip on Carry
CLRA
00
10 ° ° 010 ° ° 01
0- A
None
Clear A
None
One's complement of A to A
AISC
Y
y
I
COMP
40·
101 °°1°°°°1
A-A
NOP
44
1°10°1° 1 001
None
None
No Operation
RC
32
1°°111°°1 °1
"O"-C
None
Reset C
SC
22
10 ° 1 010 01 01
"1"- C
None
Set C
XOR
02
1°00°1°0101
A", RAM(B)- A
None
Exclusive·OR RAM with A
2-36
o
o
."
~
Table 2. COP420/421/422/320/321/322 Instruction Set (continued)
Mnemonic Operand
Hex
Code
Machine
Language Code
(Binary)
Data Flow
~
o
Skip Conditions
Description
TRANSFER OF CONTROL INSTRUCTIONS
JID
JMP
JP
a
a
FF
11111111111
ROM (PC9:8, A,M) - PC7:0
None
Jump Indirect (Note 3)
a - PC
None
Jump
None
Jump within Page (Note 4)
6-
1011 °IOOla9:sl
--
I
--
III
-JSRP
a
--
87:0
I
a - PC6:0
1111 85:0 I
(ali other pages)
a - PC5:0
a5:0
I
6-
1011011°la9sl
--
I
RET
48
1°100110001
RETSK
49
JSR
a
87:0
Co)
N
PC + 1 - SA - SB - SC
0010 - PC9:6
a - PC5:0
None
PC + 1 - SA - SB - SC
a- PC
None
Jump to Subroutine
SC- SB- SA- PC
None
Return from Subroutine
SC - SB - SA - PC
Always Skip on Return
Return from Subroutine
then Skip
A- 07:4
RAM(B) - Q3:0
None
Copy A, RAM to Q
Q7:4 - RAM (B)
Q3:0- A
None
Copy Q to RAM, A
None
Load RAM into A,
Jump to Subroutine Page
(Note 5)
CQMA
LD
LDD
r
r,d
LOID
RMB
5MB
°
33
10011100111
3C
10011111001
33
1°°111°0111
2C
1°°1°1 11 °°1
-5
1001 rl~_~1
RAM(B)- A
23
1001 °1°° 11 1
100 1 r I d I
RAM(r,d) - A
None
Load A with RAM pointed
to directly by r,d
BF
11011111111
ROM(PC9:8,A,M) - Q
SB-SC
None
Load Q Indirect (Note 3)
4C
10 1 0011 1 001
0- RAM(B)O
None
Reset RAM Bit
45
101 001 01 0 11
0- RAM(Bh
None
Set RAM Bit
-
-
2
42
101 °°1°° 10 1
0- RAM(B)2
3
43
101001°0 111
0- RAM(Bl3
°
40
1°10°1 1101 1
1 -RAM(B)O
47
1- RAM(Bh
1- RAM(B)3
2
46
1°1°°1 1101 1
1°1 0 010 11 01
3
4B
1°1°°1 1011 1
e •• _I ...... ; ".... j"'\c D ..... lit'" ..
1- RAM(B)2
2-37
~
o
."
Co)
MEMORY REFERENCE INSTRUCTIONS
CAMQ
o
o."
I
1°100110011
~
~N
a6:0
I
(pages 2,3 only)
or
11 °1
o."
!§
o
o."
-oo
~
."
Co)
N
N
N
~
c..
o
Table 2. COP420/421/422/320/321/322 Instruction Set (continued)
~
\
N
C')
c..
o
a
o
c..
Mnemonic Operand
Hex
Code
~
Description
y
7-
10111 1 y
I
y- RAM(B)
Bd+1-Bd
None
Store Memory Immediate
and Increment Bd
X
r
-6
1001 r 1011 01
RAM(B)- A
Brer-Br
None
Exchange RAM with A,
Exclusive·OR Br with r
XAD
r,d
23
10010100111
RAM(r,d)- A
None
I
Exchange A with RAM
pointed to directly by r,d
--
1101 r
XDS
r
-7
100lrl01111
RAM(B)-A
Bd-1- Bd
Br e r - Br
Bd decrements past 0
Exchange RAM with A
and Decrement Bd,
Exclusive·OR Br with r
XIS
r
-4
1001 r 101 001
RAM(B)-A
Bd+1-Bd
Brer- Br
Bd increments past 15
Exchange RAM with A
and Increment Bd,
Exclusive·OR Br with r
o
a
o
Skip Conditions
STI!
~
c..
Data Flow
MEMORY REFERENCE INSTRUCTIONS (continued)
o
~
o
Machine
Language Code
(Binary)
d
I
REGISTER REFERENCE INSTRUCTIONS
c..
CAB
50
10101100001
A- Bd
None
Copy A to Bd
o
CBA
4E
101 001 11 1 01
Bd - A
None
Copy Bd to A
1001 r l(d-1)1
(d = 0, 9:15)
or
r,d - B
Skip until not a LBI
Load B Immediate with r,d
(Note 6)
y- EN
None
Load EN Immediate (Note 7)
A - Br (0,0 - A3.A2)
None
Exchange A with Br
LBI
LEI
r,d
Y
XABR
-33
10011100111
--
d
1101 r
(any d)
33
100 1 1100 1 11
6-
10 11°1
12
10001100101
I
y
I
I
TEST INSTRUCTIONS
SKC
20
10010100001
C="1"
Skip if C is True
SKE
21
10010100011
A=RAM(B)
Skip if A Equals RAM
SKGZ
33
10011100111
G3:0=0
Skip if G is Zero (all 4 bits)
21
10010100011
SKGBZ
0
SKMBZ
SKT
33
100 11100 111
01
10000100011
1st byte
Skip if G Bit is Zero
GO=O
1
11
10001100011
2
03
10000100111
G2=0
3
13
10001100111
G3=0
0
01
10000100011
RAM(B)O=O
1
11
10001100011
RAM(Bl1 =0
2
03
10000100111
RAM(B)2=0
3
13
10001100111
RAM(B)3=0
41
10100100011
A time·base counter
carry has occurred
since last test
G1=0
2nd byte
·2-38
Skip if RAM Bit is Zero
Skip on Timer (Note 3)
o
o
"tJ
t)
S2
Table 2. COP420/421/422/320/321/322 Instruction Set (continued)
Mnemonic Operand
Hex
Code
o
Machine
Language Code
(Binary)
Data Flow
Skip Conditions
Description
INPUT/OUTPUT INSTRUCTIONS
ING
ININ
INIL
INL
OBD
OGI
OMG
XAS
y
33
10011100111
2A
100 1 011 0 1 01
33
10011100111
28
10010110001
33
10011100111
29
10010110011
33
2E
G-A
None
Input G Ports to A
IN-A
None
Input IN Inputs to A (Note 2)
o"tJ
~
o
-
o"tJ
t)
~
o
IL3, CKO, "0", ILa - A
None
Input IL Latches to A
(Note 3)
10011100111
L7:4 - RAM(B)
None
Input L Ports to RAM,A
10 01 01111 01
L3:0- A
~
S2
33
10011100111
Bd - D
None
Output Bd to 0 Outputs
3E
10 0111111 01
o
"tJ
33
10011100111
5-
y
10101 1
33
10011100111
3A
10011110101
4F
10100111111
o"tJ
o
(0)
-o
~
y-G
None
Output to G Ports Immediate
o
RAM(B)- G
None
Output RAM to G Ports
"tJ
A - SIO, C - SKL
None
Exchange A with SIO
(Note 3)
I
Nole 1: All subscripts for alphabetical symbols indicate bit numbers unless explicitly defined (e.g., Br and Bd are explicitly defined). Bits are numbered 0 to N
where 0 signifies the least significant bit (low-order. right·most bit). F6r example. A3 indicates the most significant (left·most) bit of the 4·bit A register.
Note 2: The ININ instruction is not available on the COP4211COP321 and COP4221COP322 since these devices do not conlain the IN inputs.
Note 3: For additional information on the operation of the XAS, JID, laiD, INIL, and SKT Inslructions, see below.
Nole 4: The JP instruction allows a jump, while in subroutine pages 2 or 3, to any ROM location within Ihe Iwo·page boundary of pages 2 or 3. The JP
instruction. otherwise, permits a jump to a ROM location within the current 64-word page. JP may not jump to the last word of a page.
Nole 5: A JSRP transfers program control to subroutine page 2 (0010 is loaded into the upper 4 bits of Pl. A JSRP may nol be used when in pages 2 or 3. JSRP
I11ClY [lUI JUIIIIJ lV lilt;: I", .......... 'y ;" 1-'''':;1'' : .
Nole 6: LBI i,s a single·byte instruction if d. = 0,9,10,11,12,13,14, or 15. The machine code for the lower 4 bits equals the binary value of the "d" data minus 1,
e.g., to load the lower four bits of B (Bd) with the value 9 (10012>, the lower 4 bits of the LBI Inslruction equalS (10002)' To load 0, the lower 4 bils of the LBI
instruction should equal 15 (11112)'
Nole 7: Machine code for operand field y for LEI inslruction should equal the binary value to be latched into EN, where a "1" or "0" in each bit of EN
corresponds with the selection or deselection of a particular function associated with each bit. (See Functional Description, EN Register.)
~
C'\I
~
a..
o()
-N
C")
a..
LQID Instruction
o
XAS Instruction
~
XAS (Exchange A with SID) exchanges the 4·bit con·
tents of the accumulator with the 4·bit contents of the
SID register. The contents of SID will contain serial·inl
serial·out shift register or binary counter data, depending
on the value of the ENregister. An XAS instruction will
also affect the SK output. (See Functional Description,
EN Register, above.) If SID is selected as a shift register,
an XAS instruction must be performed once every 4
instruction cycles to effect a continuous data stream.
()
C")
a..
o
()
~
a..
o
~
ij
a..
o
~
JID (Jump Indirect) is an indirect addressing instruction,
transferring program control to a new ROM location
pOinted to indirectly by A and M. It loads the lower 8 bits
of the ROM address register PC with the contents of
ROM addressed by the 10·bit word, PC9:S, A, M. PC9 and
PCs are not affected by this instruction.
a..
Note that JID requires 2 instruction cycles to execute.
~
o
()
LQID (Load Q Indirect) loads the 8·bit Q register with the
contents of ROM pointed to by the 10·bit word PC 9, PCs,
A, M. LQID can be used for table lookup or code conver·
sion such as BCD to seven·segment. The LQID instruc·
tion "pushes" the stack (PC + 1 -+ SA -+ SB -+SC) and
replaces the least significant 8 bits of PC as follows: A
-+ PC7:4, RAM (B) -+ PC3:a, leaving PC9 and PCs
unchanged. The ROM data pOinted tp by the new address
is fetched and loaded into the Q latches. Next, the stack
is "popped" (SC -+ SB -+ SA -+PC), restoring the saved
value of PC to continue sequential program execution.
Since LQID pushes SB -+ SC, the previous contents of
SC are lost. Also, when LQID pops the stack, the previ·
ously pushed contents of SB are left in SC. The net result
is that the contents of SB are placed in SC (SB -+ SC).
Note that LQID takes two instruction cycle times to
execute.
The following information is provided to assist the user
in understanding the operation of several unique instruc·
tions and to provide notes useful to programmers in
writing COP420/421 programs.
JID Instruction
SKT Instruction
The SKT (Skip On Timer) instruction tests the state of an
internal 10·bit time·base counter. This counter divides
the instruction cycle clock frequency by 1024 and pro·
vides a latched indication of counter overflow. The SKt
instruction tests this latch, executing the next program
instruction if the latch is not set. If the latch has been
set since the previous test, the next program instruction
is skipped and the latch is reset. The features associ·
ated with this instruction, therefore, allow the COP4201
421 to generate its own time·base for real·time proces·
sing rather than relying on an external input signal.
INIL Instruction
INIL (Input IL Latches to A) inputs 2 latches, IL3 and ILa
(see figure 10) and CKO into A. The IL3 and ILa latches
are set if a low·going pulse ("1" to "0") has occurred on
the IN3 and INa inputs since the last INIL instruction,
provided the input pulse stays low for at least two
instruction times. Execution of an INIL inputs IL3 and
ILa into A3 and AO respectively, and resets these latches
to allow them to respond to subsequent low·going
pulses on the IN3 and INa lines. ff CKO is mask
programmed as a general purpose inpJt, an INIL will
input the state of CKO into A2. If CKO has not been so
programmed, a "1" will be placed in A2. A "0" is always
placed in A1 upon the execution of an INIL. The general
purpose inputs IN3-INa are input to A upon execution of
an ININ instruction. (See table 2, IN IN instruction.) INIL
is useful in recognizing pulses of short duration or
pulses which occur too often to be read conveniently by
an ININ instruction.
For example, using a 2.097 MHz crystal as the time·base
. to the clock generator, the instruction cycle clock fre· .
quency will be 131 kHz (crystal frequency .,.16) and the
binary counter output pulse frequency will be 128 Hz.
For time-of·day or similar real·time processing, the SKT
instruction can call a routine which increments a "sec·
onds" counter every 128 ticks.
Instruction Set Notes
a. The first word of a COP420/421 program (ROM ad·
dress 0) must be a CLRA (Clear A) instruction.
b. Although skipped instructions are not executed, one
instruction cycl.e time is devoted to skipping each
byte of the skipped instruction. Thus all program
paths take the same number of cycle times whether
instructions are skipped or executed except JID and
LQID. LQID and JID take two cycle times if executed
and one if skipped.
c. The ROM is organized into 16 pages of 64 words
each. The Program Counter is an 10·bit binary
counter, and will count through page boundaries. If a
JP, JSRP, JID or LQID instruction is located in the
last word of a page, the instruction operates as if it
were in the next page. For example: a JP located in
the last wo·rd of a page will jump to a location in the
next page. Also, a LQID or JID located in the last
word of page 3, 7,11 or 15 will access data in the next
group oUour pages.
Note: IL latches are not cleared on reset.
C0P420
ININ
..L
INoIlNJ
INIL
Figure 10.
2-40
o
o"tJ
Option List
The COP420/421/422 mask-programmable options are assigned numbers which correspond with the COP420 pins.
Option
= 0:
= 1:
= 2:
The following is a list of COP420 options. When specifying a COP421 or COP422 chip, Options 9, 10, 19, 20 and
29 must all be set to zero. When specifying a COP422
chip, Options 21, 22, 27 and 28 must also be zero, and
Option 2 must not be a 1. The options are programmed
at the same time as the ROM pattern to provide the user
with the hardware flexibility to interface to various 1/0
components using little or no external circuitry.
Option 1 = 0: Ground Pin -
Option 18: SK Driver
same as Option 17
Option 20: IN3 Input
same as Option 9
Option
= 0:
= 1:
= 2:
= 3:
= 4:
= 5:
Option 22: G1 1/0 Port
same as Option 21
Option 23: G2 1/0 Port
same as Option 21
Option 24: G3 1/0 Port
same as Option 21
3: CKI Input
crystal input divided by 16
crystal input divided by 8
TTL external clock input divided by 16
TTL external clock input divided by 8
single-pin RC controlled oscillator (+4)
Schmitt trigger clock input (+4)
Option 25: D3 Output
= 0: Standard output (A)
= 1: Open-Drain output (8)
Option 26: D2 Output
same as Option 25
Option 27: D1 Output
same as Option 25
Option 4: RESET Pin
= 0: Load devices to Vce
= 1: Hi-Z input
Option
= 0:
= 1:
= 2:
= oJ;
Option 28: Do Output
same as Option 25
5: L7 Driver
Standard output (figure 9D)
Open-Drain output (E)
LED direct drive output (F)
I nh:> 11-11
c~
pu:;n-pull
Option 29: COP Function
= 0: normal operation
= 1: MICR08USTM option
-
.
-- \Jvr
---
VtJLlVl1 oJV.
OUtPUt l\.:l)
=0:
=1:
= 2:
=3:
-
..
~UIIUIII~
COP420 (28-pin device)
COP421 (24-pin device)
28- and 24-pin device
COP422 (20-pin device)
= 4: 28- and 20-pin device
= 5: 24- and 20-pin device
= 6: 28-, 24- and 20-pin device
Option 6: Ls Driver
same as Option 5
Option 7: L5 Driver
same as Option 5
Option 8: L4 Driver
same as Option 5
Option 9: IN1 Input
= 0: load device to Vee (H)
= 1: Hi-Z input (I)
Option 31: IN Input Levels
=0: normal input levels
= 1: Higher voltage input levels
("0" = 1.2V, "1" =3.6V)
Option 10: IN2 Input
same as Option 9
Option 32: G Input Levels
same as Option 31
Option 11
= 0:
Vee Pin -
no options available
Option 33: L Input Levels
same as Option 31
Option 12: L3 Driver
same as Option 5
Option 34: CKO Input Levels
same as Option 31
Option 13: L2 Driver
same as Option 5
Option 35: SI Input Levels
same as Option 31
Option 14: L1 Driver
same as Option 5
Option 15: Lo Driver
same as Option 5
Option 16: SI Input
same as Option 9
2-41
"tJ
~
o"tJ
.1:10
Option 21: Go 1/0 Port
= 0: Standard output (A)
= 1: Open-Drain output (8)
no options available
~
o
o
Option 19: INo Input
same as Option 9
Option 2: CKO Pin
= 0: clock generator output to crystal
(0 not available if option 3 = 4 or 5)
= 1: pin is RAM power supply (VR ) input
(Not available on COP422/COP322)
= 2: general purpose input with load device
= 3: multi-COP SYNC input
= 4: general purpose Hi Z input
i
17: SO Driver
standard output (A)
open-drain output (8)
push-pull output (C)
I\)
~I\)
o
o"tJ
(0)
I\)
e
o
o"tJ
(0)
~
o
o
"tJ
~
I\)
TEST MODE (Non·Standard Operation)
/
The SO output has been configured to provide for
standard test procedures for the custom·programmed
COP420. With SO forced to logic "1," two test modes
are provided, depending upon the value of 51:
a. RAM and Internal Logic Test Mode (51
b. ROM Test Mode (51 0)
=
2. The D3- Do outputs drive the digits of the multiplexed
display directly and scan the columns of the 4 x 4
keyboard matrix.
3. The IN3-INo inputs are used to input the 4 rows of the
keyboard matrix. Reading the IN lines in conjunction
with the current value of the D outputs allows
detection, debouncing, and decoding of anyone of
.
the 16 keyswltches.
=1)
These special test modes should not be employed by
the user; they are intended for manufacturing test only.
4. CKI is configured as a single'pin oscillator input
allowing system timing to be controlled by a singlepin RC network. CKO is therefore available for use as
a VR RAM power supply pin. RAM data Integrity is
thereby assured when the main power supply is shut
down (see RAM Keep-Alive Option description).
5. 51 is selected as the input to a binary counter input.
With 510 used as a binary counter, SO and 5K can be
used as general purpose outputs.
6. The 4 bidirectional G 1/0 ports (G3-GO) are available
for use as required by the user's application.
APPLICATION #1: COP420 General Controller
Figure 8 shows an Interconnect diagram for a COP420
used as a general controller. Operation of the system is
as follows:
1. The L7- La outputs are configured as LED Direct Drive
outputs, allowing direct connection to the segments
of the display.
VR
LO
Vee
L,
":'
GND
4·OIGIT
LED DISPLAY
GND
":'
COP4Z0
DO
D,
D,
D,
RESET
4 GENERAL
liD
~o
G,
,.,
~E:SWITCH
,., I--+-+""--P---P---P+
I--+-+""--P---P---P+
MATR'X
EVENT
COUNTER - - - . .
INPUT
'NO
s"
'N,
'51, SO and SK may also be used lor serial 110
Figure 11. COP420 Keyboard/Display Interlace
2::42
APPLICATION #2: Musical Organ and Music Box
followed by the corresponding "Sharp Key," the LEDs
will be lighted up one by one to indicate the notes of the
selected tune. The LEO will remain "on" until the player
presses the correct musical key; the LEO for the next
note will then be lighted up.
Play Mode: Twenty·five musical keys and 25 LEOs are
provided to denote F to F with half notes in between. All
the keys and LEOs are directly detected and driven by the
microprocessor. Depression of the key will give the corres·
ponding musical note and light up the corresponding LED.
Clear: Memory is provided to store a played tune. Depres·
sion of the CLEAR key erases the memory and the micro·
processor is ready to store new musical notes. A maximum
of 28 notes can be stored where each note can be of one
to eight musical beats. (Two bytes of memory are reo
qUired to store one musical note. Any note longer than
eight musical beats will require additional memory space
for storage.)
Pause: In addition to the 25 musical keys, there is a
special pause key. The depression of this key generates
a blank note to the memory.
Note: In the Learn Mode when playing "Oh Susanna," the
pause key must be used.
Playback: Depression of this button will playback the
tune stored in the memory since last "clear."
Preprogrammed Tunes: There are ten preprogrammed
tunes (each has an average of 55 notes) masked in the
chip. Any tune can be recalled by depressing the "Tune
Button" followed by the corresponding "Sharp Key."
o"tJ
Vibrato: This is a switch control to vary the frequency
vibration of the note.
S2
Tunes Listing: The following is a listing of the ten pre·
programmed tunes: 1) Jingle Bells, 2) Twinkle, Twinkle
Little Star, 3) Happy Birthday, 4).Yankee Doodle, 5) Silent
Night, 6) This Old Man, 7) London Bridge Is Falling Down,
8) Auld Lang Syne, 9) Oh Susanna, 10) Clementine.
Learn Mode: This mode is for the player to learn the ten
preprogrammed tunes. By pressing the "Learn Button"
o
Tempo: This is a control input to the musical beat time
oscillator for varying the speed of the musical tunes.
eN
N
o
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Vee
11
Vee
L7
IN3
sw
veeL~
'0
L6
470,F
L5
roy
'-4
L3
L,
So
~~MPO ~
17
L1
Lo
Go
, SK
18
G1
eOP4'O·HGZ
G,
vee
G3
220_F
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00
01
102
0,
eKI
~100PF
~
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03
LEOS
~
Circuit Diagram of COP420 Musical Organ
2-43
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IN4148
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120k ...-_..,a.;.11:..--.,
Vee
20
IN3
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£:L
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f
o
100pF
r-------------------~6~L6 .
r-__________~8 L4
-~.
13 L2
o
21
eOP420-HGZ
Go
o
B
£:L
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GNO
Music Box Application with Direct Key Access
~
If
Vee
IN4148
JUlIUl
4.7~ nnU~:
33k
PIN 18 SK------'W~-_IC NSOllEY
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.
ULJ-
This circuit automaticaliy turns off the
musical organ if none of the keys are
pressed with in approximately 30 seconds.
This additional circuit provides tinkling
effect for the musical note.
Bell Sound Circuit
Auto Power Shut-Off Circuit
2-44
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~National
D Semiconductor
.1:10
COP420C/COP421C and COP320C/COP321C
Single-Chip CMOS Microcontrollers
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General Description
Features
The COP420C, COP421 C, COP320C, and COP321 C Single·
Chip CMOS Microcontrollers are members of the COPSTM
family, fabricated using complementary MOS technology.
They are complete microcomputers containing all system
timing, internal logic, ROM, RAM and I/O necessary to
implement dedicated control functions in a variety of
applications. Features include single supply operation,
a variety of output configuration options, with an instruc·
tion set, internal architecture and I/O scheme designed
to facilitate keyboard input, display output and BCD and
binary data manipulation. The COP421C is identical to
the COP420C, except with 19 I/O lines instead of 23. They
are an appropriate choice for use in numerous human
interface control environments. Standard test procedures
and reliable high·density fabrication techniques provide
the medium to large volume customers with a customized
Control Oriented Processor at a low end·product cost.
• Lowest power dissipation (50I'W typical)
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• Power saving "Idle" state
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• Powerful instruction set
Q
• 1k x 8 ROM, 64 x 4 RAM, 23 I/O lines (COP420C)
• True vectored interrupt, plus restart
• Three·level subroutine stack
• Single supply operation (2.4·5.5V)
• Internal time·base counter for real·time processing
• MICROWIRETM compatible serial I/O
• General purpose and TRI·STATE® outputs
• LSTTLICMOS compatible
• MICROBUSTM compatible
• Software/hardware compatible with other members
of COP400 family
• Extended temperature range device
COP320C/COP321C (-40°C to +85°C)
COP420C/421C and COP320C/321C Block Diagram
Vee
0.0
CK!
I
I
I
•
CKe
TIME·8ASE
COUNTER
DlVIDEBY,024)
0,
0,
0,
00
r,=====:;i-"-- "I
SOl MltRDWIRE 110
HEVELSTACK
51
-
--,
G3
G,
G,'
Go'
5
6
1
a
12
13
Zil 10 g
19
INJINZIN,INO
2-45
14
15
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...
o
c.:I
• 151's instruction time, plus software selectable
osci Ilators
The COP320Cis the extended temperature range ver·
sion of the COP420C (likewise the COP321C is the ex·
tended temperature range version of the COP421C). The
COP320C/321C are exact functional equivalents of the
COP420C/421 C.
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COP420C/COP421C and COP320C/COP321C
Absolute Maximum Ratings
Voltage at Any Pin
-0.3V to Vee + 0.3V
Operating Temperature Range
COP420C/COP421C
0·Ct070·C
-40·C to +85·C
COP320C/COP321C
-65·C to +150·C
Storage Temperature Range
300·C
Lead Temperature (Soldering, 10 seconds)
700mWat 25·C
300mWat 70·C
150mWat 85·C
40mA
40mA
Package Power Dissipation
Total Sink Current
Total 'Source Current
Absolute maximum ratings Indicate limits beyond which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings.
DC Electrical Characteristics
COP420C/421C: O·C .. TA" 70·C, 2.4V .. Vee" 5.5V unless otherwise noted.
COP320C/321C: -40·C .. TA" +85°C, 3.0V .. Vee"" 5.3V unless otherwise noted.
Parameter
Conditions
Operation Voltage
COP420C/421C
COP320C/321C
Power Supply Ripple
peak to peak (Note 1)
Supply Current
Vee = 2.4 V,
Vee = 5.0V,
Vee = 5.0V,
Vee = 5.0V,
Idle State Current
Vee = 2.4V, fiN =32kHz
Vee = 5.0V, fiN = Max.
fiN
fiN
fiN
fiN
Output Current Levels
Sink Current
CKO
All Others
All Others
Source Current
CKO
All Others
All Others
Max.
Units
2.4
3.0
5.5
5.3
V
V
= 32 kHz (+8 mode)
= 32 kHz (+8 mode)
= Max. (+8 mode)
= Max. (+16 mode)
Input Voltage Levels
Schmitt Trigger Inputs
RESET; DO (as clock)
Logic High
Logic Low
All Other Inputs
Logic High
logic Low
. Output Voltage levels
Standard Outputs
LSTTL Operation
Logic High
Logic Low
CMOS Operation
Logic High
logic Low
Min.
0.1 Vee
V
35
100
800
1200
/-fA
/-fA
/-fA
/-fA
15
250
/-fA
/-fA
0.1 Vee
V
V
0.9 Vee
V
0.6 Vee
Vee=5V±5%
IOH=-100/-fA
IOL=O.4mA
Vee> 3V
IOH =-10/-fA
IOL=10/-fA
0.25Vee
V
0.4
V
V
0.2
V
V
2.7
Vee- 0.2
VOUT = Vee
Vee=5V
Vee=5V
Vee = Min.
100
1.2
0.2
/-fA
mA
mA
VOUT=OV
Vee=5V
Vee=5V
Vee = Min.
-100
-0.2
-0.1
/-fA
mA
mA
2-46
()
o"tJ
DC Electrical Characteristics
(Cont'd)
COP420C/421C: O°C';; TA';; 70°C, 2.4V .;; Vee';; 5.5V unless otherwise noted.
COP320C/321C: -40°C';; TA .;; +85°C, 3.0V .;; Vee';; 5.3V unless otherwise noted.
Parameter
Conditions
Min.
Allowable Sink Current
Per Pin (SO, SK, CKO)
Per Pin (All Others)
Per Port (L)
Per Port (0, G)
Allowable Source Current
Per Pin
Max.
Units
2
8
16
8
mA
mA
rnA
rnA
()
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-5
rnA
()
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Hi-Z Input Leakage
Vee=5V, VIN=O
Vee = Min., VIN = 0
Vee = 5V (COP420C/421C)
Vee = 5V (COP320C/321C)
-25
-6
-1
-2
-300
-75
+1
+2
iJ. A
iJ. A
iJ. A
iJ. A
TRI-STATE'" or Open Drain
Leakage Current
(COP420C/421C)
(COP320C/321C)
-2.5
-5
+2.5
+5
iJ. A
iJ. A
Input Load Source Current
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AC Electrical Characteristics
o·c ..
COP420C/COP421C:
TA <; 70·C, 2.4V .. TA" 5.5V unless otherwise noted.
COP320C/COP321C: -40·C .. TA .. +85·C, 3.0V .. Vee" 5.3V unless otherwise noted.
Min.
Max.
Units
Instruction Cycle Time
CO P420C/421 C
Parameter
Vee ~ 4.5V
Vee ~ 2.4V
15
50
245
245
,..s
,..s
Operating CKI Frequency
COP420C/421C
+8 mode
+16 mode
Vee ~ 4.5V
+32 mode
Dual Clk or IT
32
64
128
500
1000
2097
500
kHz
kHz
kHz
kHz
+8 mode
+16 mode
Vee ~ 2.4V
+32 mode
Dual Clk or IT
32
64
128
160
320
640
160
kHz
kHz
kHz
kHz
Instruction Cycle Time
COP320C/321C
Vee> 4.5V
Vee> 3.0V
20
50
125
125
,..s
,..s
Operating CKI Frequency
COP320C/321C
+8 mode
+16 mode
Vee ~ 4.5V
+32 mode
Dual Clk or IT
64
128
256
400
800
1600
400
kHz
kHz
kHz
kHz
+8 mode
+16 mode
Vee ~3.0V
+32 mode
Dual Clk or IT
64
128
256
160
320
640
160
kHz
kHz
kHz
kHz
CKI Duty Cycle
30
50
%
Inputs:
tSETuP
tHOLO
2.0
0.6
~
o
M
~
D.
oo
Output Propagation Delay
tpd1
tpdO
MICROBUSTM Timing
Conditions
Test .Conditlons:
Vee> 4.5V; RL = 5 kQ,
CL=50pF, VouT=1.5V
,..s
,..S
6
6
,..S
,..S
375
250
ns
ns
ns
ns
ns
700
ns
ns
ns
ns
ns
ns
CL =50pF, Vee=5V±5%
Read Operation .(Flgure 4)
Chip Select Stable before RD-tesR
Chip Select Hold Time for RD-tRes
RD Pulse Width-tRR
Data Deiay from RD-tRo
RD to Data Floating-toF
65
20
400
Write Operation (Figure 5)
Chip Select Stable before WR-tesw
Chip Select Hold Time for WR-twes
WR Pulse Wldth-tww
Data Set·Up Time for WR-tow
Data Hold Time for WR-two
INTR Transition Time from WR-twi
65
20
400
320
100
Note 1: Voltage change must be less than 0.5 volts in a 1 ms period.
Note 2: Supply current Is measured on the Vee pin with a square wave clock, all Inputs at Vee, SO = 1, Lo-L7 =0 and outputs open. See
COP Brief #14 for further Information.
2-48
()
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-1=10
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GNO
28
27
DO
01
GNO
CKO
02
OJ
GJ
CKI
RESET
17
26
25
24
L6
2J
G2
CKO
CKI
RrnT
L5
L4
INI
IN2
VCC
LJ
L2
L1
COP420C
22
21
20
19
18
17
10
11
12
lJ
14
16
15
INO
SK
SO
SI
DO
2J
22
01
21
L7
L6
L5
L4
Gl
GO
INJ
24
COP421C
VCC
LJ
L2
9
L1
12
10
11
20
19
18
17
16
15
14
lJ
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Q
02
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GJ
G2
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Gl
GO
SK
SO
SI
LO
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LO
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Order Number COP420C/N, COP320C/N
NS Package N28A
Order Number COP421C/N
NS Package N24A
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Figure 2. Connection Diagrams
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Pin
Description
Pin
Description
LrLo
G3 ·Go
0 3.0 1
8 bidirectional 1/0 ports with TRI·STATE®
SK
Logic·controlled clock
4 bidirectional 1/0 ports
3 general pu rpose outputs
CKI
System oscillator input
Do
General purpose output or oscillator input
IN 3·IN o
SI
SO
4 general purpose inputs (COP420C only)
CKO
System oscillator output (or general purpose
input)
RESET System reset input
Serial input
Serial output
Vee
Power supply
GNO
Ground
Figure 3. Input/Output Timing Diagrams (divide by 8 mode)
---.~---
..
-.-.----.-----------~---.----.---~.--------------
2-49
()
N
C")
c..
(lN21
eli
.
(lN11
Rfj
,
(L)-LOI
D)-DO
0
-
()
()
C
N
tRR
• - t Rcs
4
I
·~tOF_~
_tCSR ___ tRO_(
C")
D-
O
Figure 4. MICROBUSTM Read Operation Timing
()
cS
tcsw~
N
ItI:t
(lN21
D-
O
()
()
C
N
ItI:t
cs
(lNJI
WR
(L)-LOI
D)-DO
•
\
O
(Gol
• ....--twcs-.. ~t
I
.-tow _ _
-,
D-
twW
'WI
'W0.1-
.
X
INTR
()
Figure 5. MICROBUSTM Write Operation Timing
Functional Description
select 1 of 16 4-bit digits in the selected data register.
While the 4-bit contents of the selected RAM digit (M) is
usually loaded into or from, or exchanged with, the A
register (accumulator), it may also be loaded into or
from the a latches or loaded from the L ports. RAM
addressing may also be performed directly by the LDD
and XAD instructions based upon the 6-bit contents of
the operand field of these instructions. The Bd register
also serves as a source register for 4-bit data sent
directly to the D outputs.
For ease of reading this description, only COP420C andl
or COP421C are referenced; however, all such references
apply equally to COP320C andlor COP321C, respectively.
A block diagram of the COP420C is given in Figure 1.
Data paths are illustrated in simplified form to depict
how the various logic elements communicate with each
other in implementing the instruction set of the device.
Positive logic is used. When a bit is set, it is a logic "1".
When a bit is reset, it is a logic "0".
Program Memory
Internal Logic
Program Memory consists of a 1,024-byte ROM. As can
be seen by an examination of the COP420C/421C in·
struction set, these words may be program instructions,
program data or ROM addressing data. Because of the
special characteristics associated with the JP, JSRP,
JID and LaID instructions, ROM must often be thought
of as being organized into 16 pages of 64 words each.
The 4-bit A register (accumulator) is the source and
destination register for most 1/0, arithmetic, logic and
data memory access operations. It can also be used to
load the Br and Bd portions of the B register, to load and
input 4 bits of the 8-bit a latch data, to input 4 bits of the
8-bit L 1/0 port data and to perform data exchanges with
the SIO register.
ROM addressing is accomplished by a 10-bit PC
register. Its binary value selects one of the 1,024 8'bit
words contained in ROM. A new address is loaded into
the PC register during each instruction cycle. Unless
the instruction is a transfer of control instruction, the
PC register is loaded with the next sequential 10·bit
binary count value. Three levels of subroutine. nesting
are implemented by the 10-bit binary subroutine save
registers, SA, SB and SC, providing a last-in, first-out
(LIFO) hardware subroutine stack.
A 4·blt adder performs the arithmetic and logic
functions of the COP420C/421C, storing its results in A.
It also outputs a carry bit to the 1-bit C register, most
often employed to indicate arithmetic overflow. The C
register, in conjuction with the XAS instruction and the
EN register, also serves to control the SK output, C can
be outputted directly to SK or can enable the SK to be a
sync clock each instruction cycle time. (See XAS instruction and EN register description, below.)
ROM instruction words are fetched, decoded and
executed by the Instruction Decode, Control and Skip
Logic circuitry.
Data Memory
Four general'purpose inputs, IN3-INa, are provided; IN 1,
IN2 and IN3 may be selected, by a mask-programmable
option, as Read Strobe, Chip Select and Write Strobe
inputs, respectively, for use in MICROBUSTM applications.
Data Memory consists of a 256-bit RAM, organized as 4
data registers of 16 4-bit digits. RAM addressing is
implemented by a 6-bit B-register whose upper 2 bits
(Br) select 1 of 4 data registers and lower 4 bits (Bd)
The 0 register provides 4 general purpose outputs and
is used as the destination register for the 4-bit contents
of Bd. In the dual clock mode, D-register bit 0 controls
the clock selection (see dual oscillator below).
L _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
2-50
o
The G register contents are outputs to 4 general-purpose
bidirectional 1/0 ports. Go may be mask-programmed as
an output for MICROBUSTM applications.
The EN Register is an internal 4-bit register loaded
under program control by the LEI instruction. The state
of each bit of this register selects or deselects the
particular feature associated with each bit of the EN
register (EN3-ENo).
The Q register is an internal, latched, S-bit register, used
to hold data loaded to or from M and A, as well as S-bit
data from ROM. Its contents are output to the L 1/0
ports when the L drivers are enabled under program
control (see LEI instruction). With the MICROBUSTM
option selected, Q can also be loaded with the S-bit
contents of the L 1/0 ports upon the occurence of a
write strobe from the host CPU.
1. ENo controls the SO and SK outputs. With ENo reset,
SK is a logic-controlled clock and SO is serial data
out. With ENo set, SO and SK become general-purpose
outputs.
2. With EN1 set the IN1 input is enabled as an interrupt
input. Immediately following an interrupt, EN1 is
reset to disable further interrupts.
The 8 L drivers, when enabled, output the contents of
latched Q data to the L 1/0 ports. Also, the contents of L
may be read directly into A and M_ As explained above,
the MICROBUSTM option allows L 1/0 port data to be
latched into the Q register ..
3. With EN2 set, the L drivers are enabled to output the
data in Q to the L 1/0 ports. Resetting EN2 disables the
L drivers, plaCing the L 1/0 ports in a high-impedance
input state. If the MICROBUSTM option is being used,
EN2 does not affect the L drivers.
The 510 register functions as a 4-bit serial-in/serial-out
serial shift register shifting left each instruction cycle
tlme_ The data present at SI goes into the least significant bit of SIO. SO can be enabled to output the most
significant bit of SIO each cycle time (see 4 below). The
SK output becomes a logic-controlled clock_ The SIO
contents can be exchanged with A, allowing it to input
or output a continuous serial data stream_ SIO may also
be used to provide additional parallel 1/0 by connecting
SO to external serial-in/parallel-out shift registers.
4. EN 3, in conjunction with ENo, affects the SO output.
If ENo = 0, setting EN3 enables SO as the output of
the SIO shift register, outputting serial shifted data
each instruction time. Resetting EN3 disables SO as
the shift register output: data continues to be shifted
through SIO and can be exchanged With A via an XAS
instruction, but SO remains reset to "0". If ENo =1,
SO will output the value of EN 3. The table below provides a summary of EN3 and EN o.
The XAS instruction copies C into the 5KL Latch. SK outputs SKL ANDed with the internal instruction cycle clock_
WARNING: If ENo is set, do NOT use the contents of
SIO_
Enable Register Modes -
Bits EN3 and ENo
EN3
ENo
510
51
SO
0
0
Shift Register
Input to Shift Register
0
5K
If SKL
If SKL
0
Shift Register
Input to Shift Register
Serial Out
If SKL
If SKL
0
Not Used
Not Used
0
If SKL
If SKL
Not Used
Not Used
If SKL
If SKL
2-51
= 1, SK = Clock
= 0, SK = 0
= 1, SK = Clock
= 0, SK = 0
= 1, SK = 1
= 0, SK = 0
= 1, SK = 1
= 0, SK = 0
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COP420C/421C
and COP430C/321C Instruction Set
Table 1 is a symbol table providing internal architecture,
instruction operand, and operational symbols used in
the instruction set table.
Table 2 provides the mnemonic, operand, machine code,
data flow, skip conditions, and description associated
with each instruction in the COP420C/421C/320C/321C
instruction set.
Table 1. COP420C/421C and COP320C/321C Instruction Set Table Symbols
D..
o(.)
cS
~
o
D..
~o
~
D..
o(.)
Symbol
. Definition
Symbol
Definition
INTERNAL ARCHITECTURE SYMBOLS
INSTRUCTION OPERAND SYMBOLS
A
B
Br
Bd
C
d
4·bit Operand Field, 0-15 binary (RAM Digit
Select)
r
2·bit Operand Field, 0-3 binary (RAM Register
Select)
a
9·bit Operand Field, 0-511 binary (ROM
Address)
y
4-bit Operand Field, 0-15 binary (Immediate
Data)
0
EN
G
iL
IN
L
M
PC
Q
SA
SB
SC
SIO
SK
4·bit Accumulator
S·bit RAM Address Register
Upper 2 bits of B (register address)
Lower 4 bits of B (digit address)
1·bit Carry Register
4·bit Data Output Port
4-bit Enable Register
4-bit Register to latch data for G I/O Port
Two 1-bit Latches Associated with the IN3 or
INa inputs
4-bit Input port
B-bit TRI-STATE® I/O Port
4-bit contents of RAM Memory pointed to by
B Register
10-bit ROM Address Register (program
counter)
B-bit Register to latch data for L I/O Port
10-bit Subroutine Save Register A
10-bit Subroutine Save Register B
10-bit Subroutine Save Register C
4-bit Shift Register and Counter
Logic-Controiled Clock Output
RAM(s) Contents of RAM location addressed by s
ROM(t) Contents of ROM location addressed by t
OPERATIONAL SYMBOLS
+
-
-
Plus
Minus
Replaces
-
Is exchanged with
=
Is equal to
A
The one's complement of A
(!j
Exclusive-OR
:
Range of values
!
Table 2.. COP420C/421C, COP320C/321C Instruction Set Table (Note 1)
Mnemonic Operand
Hex
Code
Machine
Language Code
(Binary)
Data Flow
Skip Conditions
Description
ARITHMETIC INSTRUCTIONS
ASC
30
10011100001
A+C+ RAM(B) - A
Carry - C
Carry
Add with Carry, Skip on
Carry
ADD
31
10011100011
A+RAM(B)- A
None
Add RAM to A
ADT
4A
101 0011 01 01
A+1010- A
None
Add Ten to A
5-
y
10101 1
A+y- A
Carry
Add Immediate, Skip on
Carry (y 0)
CASC
10
10001100001
A+RAM(B)+C- A
Carry - C
Carry
Complement and Add with
Carry, Skip on Carry
CLRA
00
10000100001
O-A
None
Clear A
COMP
40
10100100001
A-A
None
One's complement of A to A
NOP
44
10100101001
None
None
No Operation
RC
32
1°0 1 1100 1 01
"0"- C
None
Reset C
SC
22
100101°0 10 1
"1"- C
None
Set C
1000°1°0101
A", RAM(B)- A
None
Exclusive·OR RAM with A
AISC
XOR
Y
02
I
2-52'
*
Table 2. COP420C/421C, COP320C/321C Instruction Set Table (continued)
Mnemonic Operand
Hex
Code
Machine
Language Code
(Binary)
Data Flow
Description
Skip Conditions
TRANSFER OF CONTROL INSTRUCTIONS
JID
JMP
JP
FF
11111111111
ROM (PC9:8, A,M) - PC7:0 None
Jump Indirect (Note 3)
a
6-
10 1 1 010 0la9:61
a- PC
None
Jump
I
a
---
a6:0
111
(pages 2,3 only)
or
I
a - PC6:0
None
Jump within Page (Note 4)
I
a - PC5:0
I
PC+1- SA- SB- SC
0010- PC9:6
a - PC5:0
None
Jump to Subroutine Page
(Note 5)
PC+ 1 - SA - SB - SC
a- PC
None
Jump to Subroutine
-JSRP
a
JSR
a
I
a7:0
1111 a5:0
(all other pages)
--
1101
a5:0
6-
10 11 011 0la9:61
--
I
RET
46
10100110001
SC - SB - SA - PC
None
Return from Subroutine
RETSK
49
10100110011
SC - SB - SA - PC
Always Skip on Return
Return from Subroutine
then Skip
IT
33
10011100111
PC- PC
39
10011110011
I
a7:0
Idle till Timer overflows
then continue
MEMORY REFERENCE INSTRUCTIONS
CAMO
COMA
LD
LDD
r,d
33
10011100111
3C
100 111 11001
RMB
5MB
Copy A, RAM to 0
07:4 - RAM(B)
A
None
Copy 0 to RAM, A
33
10011100111
,- _. :,"
-5
1001 r 101011
RAM(B)- A
Brmr-Br
None
Load RAM into A,
Exclusive·OR Br with r
10 a 1 010 a 1 11
RAM(r,d)-A
None
Load A with RAM pointed
to directly by r,d
11011111111
ROM(PC9:6,A,M) - 0
SB-SC
None
Load 0 Indirect (Note 3)
4C
10 1 a 0111 001
0- RAM(B)O
None
Reset RAM Bit
45
10100101011
0- RAM(BI1
·None
Set RAM Bit
23
BF
a
None
",..
Inn04 nl ..
1001 r
LQID
A- 07:4
RAM(B) - 03:0
I
of
.
-,
nnl
-
d
O~·n-
I
2
42
10100100101
0- RAM(B)2
3
43
10 1 a 010 a 1 11
0- RAM(B)3
a
40
10100111011
1 - RAM(B)O
47
10 1 00111 011
1 - RAM(BI1
2
46
10 1 a 010 1 1 01
1 - RAM(B)2
3
4B
10 1 a 011
1 - RAM(B)3
a 111
2-53
Table 2. COP420C/421C, COP320C/321C Instruction Set Table (continued)
Mnemonic Operand
Hex
Code
Machine Language
Code (Binary)
Data Flow
Skip Conditions
Description
MEMORY REFERENCE INSTRUCTIONS (continued)
STII
y
7-
10111 1
I
y - RAM(B)
Bd+l-Bd
None
Store Memory Immediate
and Increment Bd
X
-r
-6
1001 r 1011 01
RAM(B)- A
BrEI! r - Br
None
Exchange RAM with A,
Exclusive-OR Br with rc
23
100 1 01001 11
110 1 r I d I
RAM(r,d)-A
None
--
Exchange A with RAM
pointed to directly by r,d
XAD
r,d
y
XDS
r
-7
100IrlOl111
RAM(B)- A
Bd-l-Sd
BrEI! r- Br
ad decrements past 0
Exchange RAM with A
and Decrement Bd,
ExclUSive-OR Br with r
XIS
r
-4
1001 riO 1 001
RAM(B)- A
Bd+l-Bd
BrEI! r- Br
Bd Increments past 15
Exchange RAM with A
and Increment Bd,
Exclusive-OR Br with r
A- Bd
None
Copy A to Bd
1010011 110 1
Bd - A
None
Copy Bd to A
100 1 r I (d-l) I
(d = 0,9:15)
or
100 1 11061 11
1101 r 1 d 1
(any d)
r,d - B
Skip until not a LBI
Load B Immediate with
r,d (Note 6)
33
6-
1001 1100 11 1
101101 y
I
y- EN
None
Load EN Immediate
(Note 7)
12
1000 11 001 0
A-
None
Exchange A with Br
SKC
20
001 010000
C::: "1 "
Skip if C is True
SKE
21
001010001
A = RAM(B)
Skip If A Equals RAM
SKGZ
33
21
001110011
001010001
G3:0 =' 0
Skip if G is Zero
(all 4 bits)
0
1
2
3
33
01
11
03
13
001110011
00001 0001
000110001
00001001 1
00011001 1
0
1
2
3
01
11
03
13
00001 0001
000110001
00001001 1
00011001 1
RAM(B)O
RAM(S)l
RAM(B)2
RAM(B)3
41
010010001
A time-base counter
overflow has occurred
since last test
REGISTER REFERENCE INSTRUCTIONS
CAB
50
CBA
4E
LSI
r,d
-33
-LEI
y
XABR
101 0110000
I
I
Br (0,0 - A3,A2)
TEST INSTRUCTIONS
SKGSZ
SKMBZ
SKT
1st byte
Skip if G Bit is Zero
}>w~'
GO = 0
Gl '" 0
G2 = 0
G3 = 0
2-54
'" 0
=0
=0
=0
Skip if RAM Bit Is Zero
Skip on Timer
(Note 3)
Table 2. COP420C/421C, COP320C/321C Instruction Set Table (continued)
Mnemonic Operand
Hex
Code
Machine
Language Code
(Binary)
Data Flow
Skip Conditions
Description
INPUT/OUTPUT INSTRUCTIONS
ING
ININ
INIL
INL
OBD
OGI
OMG
XAS
y
33
10011100111
2A
1001 011 010 1
33
10011100111
28
10010110001
33
10011100111
29
1001°11~
G-A
None
Input G Ports to A
IN-A
None
Input IN Inputs to A
(Note 2)
ILa, "0", ILO - A
None
33
10011100111
L7:4 -
2E
100 1 011 1 1 01
L3:0- A
Bd -
33
10011100111
3E
10011111101
33
10011100111
5-
y
10101 1
33
10011100111
3A
10011110101
4F
10100111111
Input IL Latches to A
(Note 3)
None
Input L Ports to RAM,A
None
Output Bd to D Outputs
y-G
None
Output to G Ports Immediate
RAM(B)- G
None
Output RAM to G Ports
A - SIO, C - SKL
None
Exchange A with 510
(Note 3)
RAM(B)
D
I
Note 1: All subscripts for alphabetical symbols Indicate bit numbers unless explicilly defined (e.g., Br and Bd are explicilly defined). Bits are numbered 0 to N
where 0 signifies the least significant bit (Iow-order, right·most bit). For example, A3 indicates the most significant (Ieft'most) bit of the 4-bit A register.
Note 2: The ININ instruction is not available on the 24'pln COP421C since this device does not contain the IN inputs'.
Note 3: For additional information on the operation of the XAS, JID, LQID, INIL, and SKT InstrUctions, see below.
Note 4: The JP instruction allows a jump, while In subroutine pages 2 or 3, to any ROM locallon within the two-page boundary of pages 2 or 3. The JP
instruction, otherwise, permits a jump to a ROM location within the current 64-word page. JP may not jump to the last word of a page.
Note 5: A JSRP transfers program control to subroullne page 2 (0010 Is loaded Into the upper 4 bits of p). A JSRP may not be used when in pages 2 or 3. JSRP
may not jump to the last word In page 2.
-- ..
, .... 1 •• _ _
--'."
_--_. ...........................
Note 6: LSI is a sincle·bvte instruction if d = n. R. 1n. 11 19 1~ 1.4 nr 11::; Tht:o rno,..hin"" ............ " f,.. ........ t"', ....... Aha....... --:,._1- ..... - ... :---~
- - -_.- ......
e.g.,to load the lower four bils of B (Bd) with the value 9 (10012), the lower 4 bits of the LBllnstruction equal 8 (10002)' To load 0, the lower 4 bilsof the LBI
instruction should equal IS (11112)'
.
~~
.
Note 7: Machine code for operand field y for LEI Instruction should equal the binary value to be latched into EN, where a "I" or "0" In each bit of EN
corr.esponds with the selection or deselection of a particular function associated with each bit. (See Functional Description, EN Register.)
2-55
()
N
('I)
Interrupt
Il..
The following features are associated with the IN1 interrupt procedure and protocol and must be considered by
the programmer when utilizing interrupts.
o()
(3
~
('I)
Il..
o()
0'
N
"lilt
Il..
o
~
~
Il..
o
()
This option has been designed for compatibility with
National's MICROBUSTM - a standard interconnect
system for a-bit parallel data transfer between MOS/LSI
CPUs and interfacing devices. (See MICROBUSTM,
National Publication.) The functioning and timing
relationships between the COP420C signal lines
affected by this option areas specified for the
MICROBUSTM interface, and are given in the AC electrical characteristics and shown in the timing diagrams
(Figures 4 and 5). Connection of the COP420C to the
MICROBUSTM is shown in Figure 6.
a_ The interupt, once acknowledged as explained
below, pushes the next sequential program counter
address (PC + 1 ... SA ... SB ... SC). Any previous
contents of SC are lost. The program counter is set to
hex address OFF (the last word of page 3) and EN1 is
reset.
b. An interrupt will be acknowledged only after the
following conditions are met:
1) EN1 has been set.
2) A low-going pulse ("1" to "0") of at least two
instruction cycles wide occurs on the IN1 input.
3) A currently executing instruction has been
completed.
4) All successive transfer of control instructions and
successive LBls have been completed (e.g., if the
main program is executing a JP instruction which
transfers program control to another JP instruction the interrupt will not be acknowledged until
the second JP instruction has been executed.
POWER
SUPPLY
CLOCK
INTERRUPT CiNTRI
B·BIT DATA BUS
00-01
MICROPROCESSOR
READ STROBE IAliI
IN
CHIPSELECT Itsl
WRITE STROBE IWliI
SK
c. Upon acknowledgement of an interrupt, the skip
logic status is saved and later restored upon the
popping of the stack. For example, if an interrupt
occurs during the execution of ASC (Add with Carry,
Skip on Carry) instruction which results in carry, the
skip logic status is saved and program control is
transferred to the interrupt servicing routine at hex
address OFF. At the end of the interrupt routine, a
RET instruction is executed to "pop" the stack and
return program control to the' instruction following
the original ASC. At this time, the skip logic is
enabled and skips this instruction because of the
previous ASC carry. Subroutines and the LaID
instruction should not be nested within the interrupt
servicing routine since their popping of the stack
enables any previously saved main program skips,
interfering with the orderly execution of the interrupt
routine.
OUT
Figure 6. MICROBUSTM Option Il1lerconnect
Initialization
The Reset Logic, internal to the COP420C/421C, will
initialize (clear) the device upon power-up if the power
.supply rise time is less than 1 ms and greater than 11's.
If the power supply rise time is greater than 1 ms, the
user must provide an external RC network and diode to
the RESET pin as shown below. The RESET pin is configured as a Schmitt trigger input. If not used it should
be connected to Vee. Initialization will occur whenever a
logic "0" is applied to the RESET input, provided it stays
low for at least three instruction cycle times.
d. The first instruction of the interrupt routine at hex
address OFF must be a NOP.
Upon initialization, the PC register is cleared to 0 (ROM
address 0) and the A, B, C, D, EN, and G registers are
cleared. The SK output is enabled as a SYNC clock,
providing a pulse each instruction cycle time. Data
Memory (RAM) is not cleared upon initialization. The
first instruction at address 0 must be a CLRA.
e. A LEI instruction can be put immediately before the
RET to re-enable interrupts.
MICROBUSTM Interface
The COP420C has an option which allows it to be used
as a peripheral microprocessor device, inputting and
outputting data from and to a host microprocessor (JAP).
IN 1, IN 2, and IN3 general purpose inputs become
MICROBUSTM compatible read-strobe, chip-select, and
write-strobe lines, respectively. IN1 becomes RD - a
logic "0" on this input will cause a latch data to be
enabled to the L ports for input to the I'P. IN2 becomes
CS - a logic 0 selects the COP420C as a I'P peripheral
device and allows for the selection of one of several
peripheral components. IN3 becomes WR - a logic "0"
on this line will write bus data from the L ports to the a
latches for input to the COP420C. Go becomes INTR a
"ready" output, reset by a write pulse from the I'P on the
WR line, providing the "handshaking" capability
necessary for asynchronous data transfer between the
host CPU and the COP420C.
P + --1t-.....- - - ,
o
W
E
R
VCC
S
U
P
P
L
GNO
Y
RC;;;;' 5 x POWER SUPPL V RISE TIME
Figure 7. Power· Up Clear Circuli
--------------------------------------2-56
~--------------------------------------~-------------------'O
o"'tJ
LQID Instruction
The following information is provided to assist the user
in understanding the operation of several unique instructions and to provide notes useful to programmers
in writing COP420C/421C programs.
LaID (Load a Indirect) loads the 8-bit a register with the
contents of ROM pOinted to by the 10-bit word PCg, PCB,
A, M. LaiD can be used for table lookup or code conversion such as BCD to seven-segment. The LaiD instruction "pushes" the stack (PC + 1 - SA - SB -SC) and replaces the least significant 8 bits of PC as folloiNs: APC 7:4 , RAM(B) - PC3:0 , leaving PCg and PCB unchanged.
The ROM data pOinted to by the new address is fetched
and loaded into the a latches. Next, the stack is
"popped" (SC - SB - SA -PC), restoring the saved value
of PC to continue sequential program execution. Since
LaiD pushes SB - SC, the previous contents of SC are
lost. Also, when LaiD pops the stack, the previously
pushed contents of SB are left in SC. The net result is
that the contents of SB are placed in SC (SB - SC). Note
that LaiD takes two instruction cycle times to execute.
XAS Instruction
XAS (Exchange A with SIO) exchanges the 4-bit contents of the accumulator with the 4-bit contents of the
SIO register. The contents of SIO will contain serialin/serial-out shift register data. An XAS instruction will
also affect the SK output, providing a logic controlled
clock. An XAS instruction must be performed once every
4 instruction cycles to effect a continuous data stream.
JID Instruction
JID (Jump Indirect) is an indirect addressing instruction,
transferring program control to a new ROM location
pointed to indirectly by A and M. It loads the lower 8 bits
of the ROM address register PC with the contents of
ROM addressed by the 10-bit word, PC 9:B, A, M. PCg and
PCB are not affected by this instruction.
The SKT (Skip On Timer) instruction tests the state of an
internal 10-bit time base counter. This counter divides
the instruction cycle clock frequency by 1024 and provides a latched indication of counter overflow. The SKT
instruction tests this overflow latch, executing the next
program instruction if the latch is not set. If the latch
has been set since the previous test, the next program
instruction is skipped and the latch is reset. The features associated with this instruction, therefore, allow
the COP420C/421C to generate its own time base for
real-time processing rather than relying on an external
input signal.
INIL Instruction
INIL (Input IL Latches to A) inputs 2 latches, IL3 and ILo
(see Figure 8) and CKO into A. The IL3 and ILo latches
are set if a low-going pulse ("1" to "0") has occurred on
the IN3 and INo inputs since the last INIL instruction,
provided the input pulse stays low for at least two instruction times. Execution of an INIL inputs IL3 and ILo
into A3 and Ao respectively, and resets these latches to
allow them to respond to subsequent low-going pulses
on the IN3 and INo lines. If CKO is mask programmed as
a general purpose input, an INIL will input the state of
CKO into A2' If CKO has not been so programmed, a "1"
will be placed in A2. A "0" is always placed in Al upon
IIlfJUl~
g
o"'tJ
~
s>
o
o"'tJ
Co)
~
Q
o
o"'tJ
Co)
SKT Instruction
Note that JID'requires 2 instruction cycles to execute.
U It;; t:'At;:l,;UlIUII VI ell I II 'It IL.. lilt: yt:'IIt;:1 ell fJUI tJuO)t:'
~
For example, using a 32kHz watch crystal for the oscillator, the counter pulse frequency will be 4 Hz. For timeof-day or similar real-time processing, the SKT instruction can call a routine which increments a "seconds"
counter every 4 ticks.
""3-
IT Instruction
INo are input to A upon execution of an ININ instruction.
(See Table 2, ININ instruction.) INIL is useful in recognizing pulses of short duration or pulses which occur
too often to be read conveniently by an ININ instruction.
Note that IL latches are not cleared on reset. IL latches
are not available on the COP421C.
The user may choose to use the IT function instead of
the SKT function. The IT (Idle till Timer) instruction halts
the processor and puts it in an idle state. This idle state
reduces current drain since all logic (except the oscillator and time base counter) is stopped. The time base
counter always divides CKI by 8192 regardless of the
divide-by option selected (see Figures 10 and 11).
If in the divide-by-8 mode, the chip will come out of the
idle state when the time base counter overflows. If in the
divide-by-16 mode, the chip will come out of the idle state
after the time base counter overflows TWICE. The IT
instruction cannot be used in the divide-by-32 mode.
ININ
1
Therefore, the number of instruction cycles that the chip
remains in the idle state is the SAME for both divide-by-8
and divide-by-16. For example, if CKI is 262kHz (divideby-16) or is 131 kHz (divide-by-8), the chip will come out of
idle 16 times per second.
INO/IN3
'NIL
If using the dual clock feature, the user MUST switch the
processor to theCKI oscillator (DO = 0) before executing
the IT instruction.
Note: If using the dual clock feature or the IT instruction,
contact the factory for emulation assistance.
Figure 8. INIL Hardware Implementation
2-57
~
o
Using Both SKT and IT Instructions
If specific guidelines are adhered to, the SKT instruction may be used when the IT instruction is enabled.
(option 31 = 4 to 7).
1. Use divide by 8 CKI (option 3 = 1).
a. Crystal Controlled Oscillator. CKI and CKO are
connected to an external crystal (or resonator). The
instruction cycle time equals the crystal frequency
divided by 32, 16 or 8.
2. If using Dual clock, execute SKT only when operating
from CKI clock.
b. External Oscillator. CKI is connected to an external
clock input Signal. CKO is now available to be used
as a general purpose input.
3. After executing an SKT which gives a skip, execute
another SKT instruction.
c. Dual Oscillator. By selecting the dual clock option,
pin DO is now a clock input. The user may connect a 32
kHz watch crystal to CKI and CKO and up to a 500 kHz
clock to DO (RIC or external). The user may then software select between the DO oscillator for faster processing (DO = 1) or the crystal for minimum current
drain (DO = 0). The time-base counter runs off the CKI
oscillator even when the user selects DO as the clock.
Thus, a real time clock can be maintained by the IT
instruction even when running off the RC oscillator.
The SKT instruction is restricted when using the dual
clock feature.
Sample Code:
SKT
JP
SKT
NOP
NO
YES:
;
;
;
;
;
test timer
no overflow
do another SKT
defeat skip
process timer overflow
(continue program)
; no timer overflow, continue
NO:
Using this technique, a careful programmer can use
both SKT and IT.
CKO Pin Options
In a crystal controlled oscillator system, CKO is used as
an output to the crystal network. As an option CKO can
be a general purpose input, read into bit 2 of A (accumu·
lator) upon executiOn of an INIL instruction.
Oscillator
There are three basic clock oscillator configurations
available as shown by Figure 9.
R1'
22M
..Jl.f"
EXTERNAL
CLOCK
VCC
c
~
t
t
CKO
CKI
I
/b
a
R
DO
GENERAL
PURPOSE INPUT
EXTERNAL OSCILLATOR
C1
CRYSTAL OSCILLATOR
32kHz
I
C2
DUAL CLOCK
Crystal Oscillator
RIC Oscillator
Component Values
Crystal
Value
R1'
C1
C2
2.097MHz
1k
5-36pF
32kHz
220k
5-36pF
30pF
30pF
500kHz
4.7k
47pF
82pF
'Selected based on Crystal used.
Figure 9.
2-58
Instruction
Cycle Time
R (Q)
Vec
120k±10%
4.5 to 5.5V
15"s to 60"s
160k
3V
30"s to 120"s
180k
2.4V
50"s to 200"s
IO~_U_T________________________~~~ TO
CKO
1\
I
A2
p(
SYSTEM
CLOCKS
(INCLUOING SKI
Figure lOa. Oscillator Options Block Diagram Using SKT Instruction
r-1~:
':',
~
INIL
..L
~ TO
A2
INPUT
OSC. OUT
TIME BASE COUNTER
(~B1921
CKI
I
"C3h--JJ
Figure lOb. Oscillator Options Block Diagram Using IT Instruction
2~59
_ _ ._ _
~
L -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ . _ _ _ _ _ _ _
~
Figure 11. Dual Clock Option Block Diagram
_ _ _ _ _ _ _ _ _ __
o
~
a.
oo
o
~
1/0 Options
COP420C/421C inputs have the following options:
CO P420C/421 C outputs have the following optional configurations, illustrated in Figure 13:
f. An on-chip pullup load device to Vee.
g. A Hi-Z input which must be driven by user logic.
a. Standard - An N-channel device to ground in conjunction with a P-channel device to Vee, compatible
with CMOS and LSTTL_
The above input and output configurations share common devices. Specifically, all configurations use one or
more of four devices (numbered 1-4, respectively). Minimum and maximum current (lOUT and VOUT) curves are
given in Figure 12 for each of these devices to allow the
designer to effectively use these 1/0 configurations.
C")
oo
a.
b. Open-Drain - An N-ehannel device to ground only,
allowing external pull-up as required by the user's
application_
cJ
c. TRI·STATE® L Output - A CMOS output buffer wh ich
l\i
oo:t
a.
may be disabled by program control. These outputs
meet the requirements associated with the
MICROBUSTM option.
~
d. Standard L Output - This is the same configuration
as c. above except that the sourcing current is
standard_
o
~
oo
COP421C
If the COP420C is bonded as a 24-pin device,it becomes
the COP421C, illustrated in Figure 2, COP420C/421C Connection Diagrams. Note that the COP421C does not contain the four general purpose IN inputs (lN3-INo). Use of
this option precludes, of course, use'of the IN options, in'
terrupt feature, and the MICROBUSTM option which uses
IN1-IN3' All other options are available for the COP421C.
e. Open Drain L Output- This has the N-channel
device to ground only_
COP420C/421C 110 Characteristics
Standard· Output
Minimum Sink Current
TRI·STATE Output
Minimum Source Current
3.--r--.-~--'---r-~
<'
~
<'
....
~
!2
-1
'"
!2
VOL (VOLTS)
VOH (VOLTS)
Standard Output
Source Current
-2_5
-2.0
<' -1.5
~
-...... ........
I
VCC=4.5V
(MAX.)
VCC=2.4V'r--,
~
'"
o
I
"
-250
Idl-
1-200
'\VCC=5.5V
VCC=4.~V(MI~;\
-0.5
-300 I-::-+--,-""t:--+----+-_+_---I
r"-t'-,
.............
!2 -1.0
Input Load
Source Current
-350 r-~----'---"'-----r--'---'
VCC=5.5V
~
\(MAX.)
\
(MIN.)_~
-150 H---t-+--'k---+-\--f_+_--;
-100
I\.
o
2.
VIN (VOLTS)
VOH (VOLTS)
2-60
COP320C/321C I/O Characteristics
Standard Output
Minimum Sink Current
TRI·STATE Output
Minimum Source Current
3
/'
;,
/
,/'"
-
VGG=5~V
~
~ -1 r--+--+---r-~~+-~
"
!2
:..-- ~3.0V
o
o
VOH (VOLTS)
VOL (VOLTS)
Standard Output
Source Current
Input Load
Source Current
r---r--,--.----r-..,----.
-400
r--r-...,--r---r-...,---,
-2.5
F""....r---t---t--+-+-~
-350
I---+""""'..c--I---+--t---l
-2.0
t--+---t-""r-'-+--::-:::+-~
-3.0
-300 I---t--+--~
~
~
~ -1.5
"
!2
-1.0
-250
r--+--+---I-'\;-+--+-~
~ -200
I-+-+--+---f--'\:--+---l
-150
H--++--+---r--+~+--I
-100
t--f"1"-.::
-50
I=*F=F¥l;:;::±--l'rl
o t=±::±:::~--1~:s....J
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VOH (VOLTS)
VIN (VOLTS)
2-61
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Instruction Set Notes
Il.
a. The first word of a program (ROM address 0) must be
a CLRA (Clear A) instruction.
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Il.
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ci
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§
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will typically cause the 420C to draw 100llA more than
with a square wave oscillator input. Power will increase
with loading capacitance and frequency of the outputs.
b. Although skipped instructions are not executed, one
instruction cycle time is devoted to skipping each
byte of the skipped instruction. Thus all program
paths except LaiD or JID.take the same number of
cycle times whether instructions are skipped or executed. LaiD and JID take two cycle times if executed
and o.ne if skipped.
The lowest possible current drain is when the processor
is in the idle mode (see IT instruction).
Another method to red uce power is to use the dual clock
option. The overall current drain will be an average of the
low frequency current and the high frequency current,
based on the amount of time spent at each frequency.
c. The ROM is organized into 16 pages of 64 words
each. The Program Counter is an 10-bit binary counter,
and will count through page boundaries. If a JP, JSRP,
JID or LaiD instruction is located in the last word of
a page, the instruction operates as if it were in the
next page. For example: a JP located in the last word
of a page will jump to a location in the next page. Also,
a LaID orJID located in the last word of page 3, 7, 11,
or 15 will access data in the next group of 4 pages.
COP420C TTL Interface
The COP420C outputs can directly drive one standard
LSTTL load. A pull-up device should be selected on inputs driven by TTL in order to bring the input signal up
to the required logic "1" level.
TEST MODE (Non-Standard Operation)
The SO output. has been configured to provide for
standard test procedures for the custom-programmed
COP420C. With SO forced to logic "1", two test modes
are provided, depending upon the value of SI:
COP420C Power Dissipation
The lowest power configuration is at minimum
voltage and lowest frequency. The. user should take
care that all Inputs swing to fuil supply levels to
insure that there are no DC current paths on inputs.
An external square wave oscillator will use less
current than a crystal or resonator since an input from
a crystal Is slow to transcend logic levels. For
example: at 500 kHz, a crystal (or resonator)
a. RAM and Internal Logic Test Mode (SI =1)
b. ROM Test Mode (SI = 0)
These special test modes should not be employed by
the user; they are intended for manufacturing test only.
Vee
r~p
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#2 ...
b. Open Drain
a. Standard
Vee
Jtg:~
Vee
DI~SABLE ~
P '3
N "
d. Standard L Output
c. TRI STATE@ L Output
Vee
DISABLE
~
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e. Open Drain L Output
f. Input with Load
g. HI Z Input
Figure 13. I/O Configurations
2-62
(")
o
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Option List
The COP420C/320C mask·programmable options are
assigned numbers which correspond with the COP420C
pins.
~
The following is a list of COP420C options. When
specifying a COP421C chip, Options 9, 10, 19, and 20
must all be set to zero. The options are programmed at
the same time as the ROM pattern to provide the user
with the hardware flexibility to interface to various 110
components using little or no external circuitry.
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Option 1 = 0: Ground Pin
Not an option
Option 18: SK Driver
same as Option 17
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Option
00 =
02 =
04 =
2: CKO Output
Oscillator Output
General Input, Vee Load
General Input, Hi·Z
Option 19: INo Input
same as Option 9
~
Q
Option
00 =
01 =
02 =
3: CKI Input
Oscillator IN (-;'16)
Oscillator IN (-;'8)
Oscillator IN (-;'32)
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Option 21: Go 110 Port
same as Option 17
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Option 22: G1 110 Port
same as Option 17
Option 23: G2 110 Port
same as Option 17
5: L7 Driver
Standard Output
Open Drain
High Current TRI·STATE®
Option 24: G3 110 Port
same as Option 17
Option 25: D3 Output
same as Option 17
Option 6: Ls Driver
same as Option 5
Option 26: D2 Output
same as Option 17
Option 7: Ls Driver
same as Option 5
Option 27: D1 Output
same as Option 17
Option 8: L4 Driver
same as Option 5
Option 28: Do Output
00 = Standard Output
Option 9: IN1 Input
uu=
(")
Option 20: IN3 Input
same as Option 9
Option 4: RESET Input
00= Load Vee
01 = Hi·Z
Option
00 =
01 =
02 =
Co)
VI -
LUi;1U Vee
01 = Hi·Z
-
VtJCill
-
L.llo..lll \VI
-.
L.lUo.l VIUI.JI'\}
Option 29: COP Function
00= Normal
01 = MICROBUSTM
Option 10: IN2 Input
same as Option 9
Option 30: COP Bonding
00 = COP420C (28·pin package)
01 = COP421C (24·pin package)
02:0 COP420C and COP421C, same ROM (same die
purchased in both 24· and 28·pin versions)
Option 11: Vee pin
not an option
Option 12: L3 Driver
same as Option 5
Option 13: L2 Driver
same as Option 5
Option 31: Clock/Timer Mode
02 = XtallExt. Osc. in; SKT instruction enabled; no IT
04' = XtallExt. Osc. in; IT instruction enabled; SKT
restricted
06' = XtallExt. Osc. in; Dual Clock (RC); IT enabled
SKT restricted
07' = XtallExt. Osc. in; Dual Clock (Ext.) IT enabled;
SKT restricted
Option 14: L1 Driver
same as Option 5
Option 15: La Driver
same as Option 5
Option 16: SI Input
same as Option 9
Option 17: SO Driver
00 = Standard Output
01 = Open Drain
'Contact factory for emulation assistance. Also note CKI
maximum frequency specifications (page 3).
2-63
.....
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~National
U Semiconductor
:J
CO P420L/COP421 L/COP422L and
~
a.. COP320L/COP321L/COP322L
o() Single-Chip N·Channel Microcontrollers
:J General Description
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Features
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• Low cost
• Powerful instruction set
The COP420L, COP421L, COP422L, COP320L, COP321L,
and COP322L Single·Chip N·Channel Microcontrollers
are members of the COPSTM family, fabricated using
N-channel, silicon gate MOS technology. These controller
oriented processors are complete microcomputers con·
taining all system timing, internal logic, ROM, RAM, and
1/0 necessary to implement dedicated control functions
in a variety of applications. Features include single sup·
ply operation, a variety of output configuration options,
with an instruction set, internal architecture, and 1/0
scheme designed to facilitate keyboard input, display
output, and BCD data manipulation. The COP421L and
COP422L are identical to the COP420L, but with 19 and
15 1/0 lines, respectively, instead of 23. They are an
appropriate choice for use in numerous human interface
control environments. Standard test procedures and
reliable high·density fabrication techniques provide the
medium to large volume customers with a customized
controller oriented processor at a low end·product cost.
• lkx8 ROM, 64x4 RAM
• 23 1/0 lines (COP420L)
• True vectored interrupt, plus restart
• Three·level subroutine stack
• 161's instruction time
• Single supply operation (4.5-6.3V)
• Low currerit drain (8mA max.)
• Internal time·base counter for real-time processing
• Internal binary counter register with MICROWIRETM
compatible serial 1/0
• General purpose and TRI-STATE Configuration,
Lo- L7 Outputs, Low
Current Driver Option (IOH)
Vee = 9.5V, VO H 5.5V
Vee = 6.3V, VOH 3.2V
Vee = 4.5V, VOH = 1.5V
TRI-STATEi!> Configuration,
Lo-L7 Outputs, High
Current Driver Option (IOH)
Vee 9.5V, VOH = 5.5V
Vee 6.3V, VO H = 3.2V
Vee = 4.5V, VO H = 1.5V
Push-Pull Configuration
SO and SK Outputs (loH)
Input Load Source Current
Vee = 9.5V, VOH
Vee = 6.3V, VOH
Vee = 4.5V, VOH
=
=
=
=
Vee
-800
-480
-250
-1.4
-1.4
-1.2
,..A
,..A
,..A
mA
mA
mA
-0.75
-0.8
-0.9
mA
mA
mA
=
=
-1.5
-1.6
-1.8
mA
mA
mA
=5.0V, VIL =OV
-10
-140
,..A
3.0
mA
+2.5
,..A
120
120
4
4
1.5
mA
mA
mA
mA
mA
120
60
60
30
1.5
mA
mA
mA
mA
mA
CKO Output
RAM Power Supply Option
Power Requirement
VR=3.3V
TRI-STATEi!> Output Leakage
Current
-2.5
Total Sink Current Allowed
All Outputs Combined
0, G Ports
L7-~
L3-Lo
All Other Pins
Total SOurce Current Allowed
All 110 Combined
L7-~
L3-Lo
Each L Pin
All Other Pins
2-66
(')
o"'tJ
COP320LlCOP321L1COP322L
Absolute Maximum Ratings
~
Voltage at Any Pin Relative to GND
Ambient Operating Temperature
Ambient Storage Temperature
Lead Temperature (Soldering, 10 seconds)
Power Dissipation
COP320LlCOP321L
C
(')
-0.5V to +10V
-40·C to +85°C
-65°C to +150°C
300°C
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ao
0.75 Watt at 25°C
0.4 Watt at 85°C
0.65 Watt at 25°C
0.20 Watt at 85°C
120mA
120mA
COP322L
Total Source Current
Total Sink Current
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Absolute maximum ratings indicate limits beyond which damage
to the device may occur. DC and AC electrical specifications are
not ensured when operating the device at absolute maximum
ratings.
DC Electrical Characteristics
~
c(')
-40°C ~ TA ~ +85°C, 4.5V ~ Vee ~ 7.5V unless otherwise noted.
Parameter
Standard Operating Voltage (Vecl
c.,)
Conditions
Note 1
Optional Operating Voltage (Vecl
Max.
Units
4.5
5.5
V
~
4.5
7.5
V
C
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Power Supply Ripple
peak to peak
0.5
V
Operating Supply Current
all inputs and outputs open
11
mA
c.,)
(')
c.,)
~
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Input Voltage Levels
CKI Input Levels
Crystal Input
Logic High (V IH )
Logic Low (VILl
Schmitt Trigger Input
Logic High (VIH)
Loaie Low (V" )
RESET Input Levels
o"'tJ
Min.
2.2
-0.3
0.3
V
V
0.7 Vee
-0.3
0.4
V
V
0.7 Vee
-0.3
0.4
V
V
2.2
2.5
V
Schmitt Trigger Input
Logic High
Logic Low
SO Input Level (Test mode)
All Other Inputs
Logic High
Logic High
Logic Low
Vee = Max.
with TTL trip level options
selected, Vee = 5V ± 5%
3.0
2.2
-0.3
0.6
V
V
V
Logic High
Logic Low
with high trip level options
selected
3.6
-0.3
1.2
V
V
Input CapaCitance
7
-2
HI-Z Input Leakage
Output Voltage Levels
LSTIL Operation
Logic High (VOH )
Logic Low (VoLl
Vee=5V±5%
IOH=-20,..A
IOL=0.36mA
CMOS Operation
Logic High
Logic Low
IOH =-10,..A
IOL=+10,..A
+2
0.4
V
V
0.2
V
V
2.7
Vee- 1
Note 1: Vee voltage change must be less than O.5V In a 1 ms period to maintain proper operation,
2-67
pF
,..A
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COP320LlCOP321L1COP322L
DC Electrical Characteristics
Parameter
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Output Current Levels
Output Sink Current
SO and SK Outputs (loll
(continued) -40·C" TA " +85·C, 4.5V" Vee" 7.5V unless otherwise noted.
Conditions
Min.
Max.
Units
Vee = 7.5V, VOL = O.4V
Vee = 5.5V, VOL = 0.4V
Vee = 4.5V, VOL = 0.4V
1.4
1.0
0.8
mA
mA
mA
4J- L7 Outputs and Sta'ndard
Go-G 3, 00-03 Outputs (lad
Vee = 7.5V, VOL == 0.4V
Vee = 5.5V, VOL=0.4V
Vee = 4.5V, VOL = 0.4V
0.6
0.5
0.4
mA
mA
mA
GO-G3 and 00-03 Outputs with
High Current Options (lad
Vee = 7.5V, VOL = 1.0V
Vee = 5.5 V, VOL = 1.0V
Vee = 4.5V, VOL = 1.0V
12
9
7
mA
mA
mA
GO-G3 and 00-03 Outputs with
Very High Current Options (loll
Vee = 7.5V, VOL = 1.0V
Vee = 5.5V, VOL = 1.0V
Vec = 4.5V, VOL = 1.0V
24
18
14
mA
mA
mA
CKI (Single'pin RC oscillator)
CKO
Vee = 4.5V, V1H = 3.5V
Vee = 4.5V, VOL = 0.4V
2
0.2
mA
mA
Vee = 7.5V, VO H = 2.0V
Vee = 5.5V, VOH = 2.0V
Vec = 4.5V, VOH = 2.0V
-100
-55
-28
Push·Pull Configuration
SO and SK Outputs (IOH)
Vee = 7.5V, VOH = 3.75V
Vee = 5.5V, VOH = 2.0V
Vee = 4.5V, VOH = 1.0V
-0.85
-1.1
-1.2
LED 9onfiguration, 4J-L7
Outputs, Low Current
Driver Option (IOH)
Vee'=7.5V, VOH=2.0V
Vee = 6.0V, VOH = 2.0V
Vee = 5.5V, VOH = 2.0V
-1.4
-1.4
-0.7
-27
-17
-15
mA
mA
mA
LED Configuration, 4J-L7
Outputs, High Current
Driver Option (lo H)
Vee =7.5V, VOH = 2.0V
Vee = 6.0V, VOH = 2.0V
Vee = 5.5V, VOH = 2.0Y
-2.7
-2.7
-1.4
-54
-34
-30
mA
mA
mA
TRI·STATE@ Configuration,
4J-L7 Outputs, Low
Current Driver Option (lo H)
Vee == 7.5V, VOH = 4.0V
Vee = 5.5 V, VOH = 2.7V
Vee = 4.5V, VOH = 1.5V
-0.7
-0.6
-0.9
mA
mA
mA
TRI-5TATE@Configuration,
4J-L7 Outputs, High
Current Driver Option (lOH)
Vee = 7.5V, VOH = 4.0V
Vee = 5.5V, VOH = 2.7V
Vee = 4.5V, VOH = 1.5V
-1.4
-1.2
-1.8
mA
mA
mA
Vee = 5.0V, VIL=OV
-10
Output Source Current
Standard Configuration,
All Outputs (lOH)
Input .Load Source Current
-900
-600
-350
j./A
j./A
j./A
mA
mA
mA
-200
j./A
4.0
mA
+5
j./A
120
120
4
4
1.5
mA
mA
mA
mA
mA
120
60
60
30
1.5
mA
mA
mA
mA
mA
CKO Output
RAM Power Supply Option
Power Requirement
VR=3.3V
TRI·STATEI!J ~utput Leakage
Current
-5
Total Sink Current Allowed
All Outputs Combined
D, G Ports
L7- L4
L3- LO
All Other Pins
Total Source Current Allowed
All 110 Combined
L7-L4
~-Lo
Each L Pin
All Other Pins
2-68
o
o
AC Electrical Characteristics
~
COP420LlCOP421L1COP422L: O°C", TA'" 70°C, 4.5V '" Vcc'" 9.5V unless otherwise noted.
COP320LlCOP321UCOP322L: -40°C", TA '" +85°C, 4.5V '" Vcc'" 7.5V unless otherwise noted.
Parameter
Conditions
Instruction Cycle Time CKI
Input Frequency -
tc
fl
Duty Cycle
Rise Time
Fall Time
CKI Using RC (+4)
+32 mode
+16 mode
+8 mode
+4 mode
~
Max.
Units
15
40
jJs
0.8
0.4
0.2
0.1
30
2.1
1.0
0.5
0.26
60
120
80
MHz
MHz
MHz
MHz
%
ns
ns
.r
jJs
o"'CI
fl=2MHz
~
co
o"'CI
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o
R=56kQ±5%
C=100pF±10%
15
Instruction Cycle Time
28
CKO as SYNC Input
ns
400
tSYNC
INPUTS:
IN3-INo, G3-Go, L7-Lo
tSETUP
tHOLD
SI
tSETUP
tHOLD
OUTPUT PROPAGATION DELAY
~
o
Min.
8.0
1.3
jJS
jJs
2.0
1.0
jJs
jJs
2-69
~
~
o"'CI
~
8
"'CI
~
Test condition:
CL =50pF, RL=20kQ, VouT=1.5V
SO, SK Outputs
tpd10 tpdO
All Other Outputs
tpdl, tpdo
Co)
r4.0
jJs
5.6
jJS
-I
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GNO
CKO
CKI
g
28
27
26
25
24
2J
RIm'
N
L7
L6
L5
L4
IN1
IN2
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VCC
L3
L2
L1
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7
COP420Ll
CUPJ20L
10
11
12
1J
14
15
DO
01
02
DJ
GJ
G2
G1
GO
INJ
INO
SK
SO
SI
LO
DO
D1
02
OJ
GJ
G2
G1
GO
SK
SO
SI
LO
24
GND
CKO
CKI
i!m'i'
L7
L6
L5
l4
VCC
LJ
L2
L1
COP421L1
COP321L
10
11
12
CKO
20
CKI
19
02
RESET
18
OJ
L7
mml'
L6
L5
L4
GNO
17
G3
16
15
G2
14
SO
SK
VCC
13
SI
L3
12
LO
11
U
L2
10
....r
Order Number COP420UN, COP320UN Order Number COP421UN, COP321UN Order Number COP422UN, COP322UN
NS Package N28A
NS Package N24A
NS Package N20A
Q.
Figure 2. Connection Diagrams
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Pin
Description
Description
Pin
L7-Lo
8 bidirectional I/O ports with
TRI-STATE"
SK
Logic'controlled clock (or general
purpose output)
G3-Go
D3- DO
4 bidirectional I/O ports
CKI
System oscillator input
4 general purpose outputs
CKO
IN3-INo
4 general purpose inputs (COP420L only)
51
Serial input (or counter input)
RESET
System oscillator output (or general
purpose input, RAM power supply or
SYNC input)
System reset input
SO
Serial output (or general purpose output)
Vce
GND
Ground
Power supply
Figure 3. Input/Output Timing Diagrams (Crystal Divide·by·16 Mode)
CKI
CKO
(INPUT)
Figure 3a. Synchronization Timing
2-70
o
o
Functional Description
For ease of reading this description, only COP420L andl
or COP421L are referenced; however, all such references
apply also to COP320L, COP321L, COP322L, or COP422L.
also serves to control the SK output. C can be outputted
directly to SK or can enable SK to be a sync clock each
instruction cycle time. (See XAS instruction and EN register description, below.)
A block diagram of the COP420L is given in Figure 1.
Data paths are illustrated in simplified form to depict
how the various logic elements communicate with each
other in implementing the instruction set of the device.
Positive logic is used. When a bit is set, it is a logic "1"
(greater than 2 volts). When a bit is reset, it is a logic "0"
(less than 0.8 volts).
Four general-purpose inputs, IN 3 -IN o, are provided.
The D register provides 4 general-purpose outputs and
is used as the destination 'register for the 4-bit contents
of Bd. The D outputs can be directly connected to the
digits of a multiplexed LED display.
The G register contents are outputs to 4 general-purpose
bidirectional 1/0 ports. G 1/0 ports can be directly
connected to the digits of a multiplexed LED display.
Program Memory
Program Memory consists of a 1,024 byte ROM. As can
be seen by an examination of the COP420Ll421 L instruction set, these words may be program instructions,
program data or ROM addressing data. Because of the
special characteristics associated with the JP, JSRP,
JID and LaiD instructions, ROM must often be thought
of as being organized into 16 pages of 64 words each.
The a register is an internal, latched, 8-bit register, used
to hold data loaded to or from M and A, as well as 8-bit
data from ROM. Its contents are outputted to the L 1/0
ports when the L drivers are enabled under program
control. (See LEI instruction.)
The 8 L drivers, when enabled, output the contents of
latched a data to the L 1/0 ports. Also, the contents of L
may be read directly into A and M. L 1/0 ports can be
directly connected to the segments of a multiplexed LED
display (using the LED Direct Drive output configuration
option) with a data being outputted to the Sa-Sg and
decimal point segments of the display.
ROM addressing is accomplished by a 10-bit PC register. Its binary value selects one of the 1,024 8-bit words
contained in ROM. A new address is loaded into the PC
register during each instruction cycle. Unless the instruction is a transfer of control instruction, the PC
register is loaded with the next sequential 10-bit binary
count value. Three levels of subroutine nesting are
implemented by the 10-bit subroutine save registers,
SA, SB and SC, providing a last-in, first-out (LIFO)
hardware subroutine stack.
The 510 register functions as a 4-bit serial-in/serial-out
shift register or as a binary counter depending on the
contents of the EN register. (See EN register description, below.) Its contents can be exchanged with A, allowing it to input or output a continuous serial data
stream. 510 may also be used to provide additional
parallel 1/0 by connecting SO to external serial-inl
parallel-out shift registers. For example of additional
parallel output capacity see Application #2.
ROM instruction words are fetched, decoded and executed by the Instruction Decode, Control and Skip Logic
circuitry.
Data Memory
Data memory consists of a 256-bit RAM, organized as 4
oala regl::Her:; or 10 'I-UII Olgll:;. r1f-\IVI Gloore:;:;lng I:; IIfIplemented by a 6-bit B register whose upper 2 bits (Br)
select 1 of 4 data registers and lower 4 bits (Bd) select 1
of 16 4-bit digits in the selected data register .. While the
4-bit contents of the selected RAM digit (M) is usually
loaded into or from, or exchanged with, the A register
(accumulator), it may also be loaded into or from the a
latches or loaded from the L ports. RAM addressing may
also be performed directly by the LDD and XAD instructions based upon the 6-bit contents of the operand field
of these instructions. The Bd register also serves as a
source register for 4-bit data sent directly to the D
outputs.
The XAS instruction cooies C into the SKL latch. In the
counter mode, SK is the output of SKL; in the shift register mode, SK outputs SKL ANDed with the clock.
The EN register is an internal 4-bit register loaded under
program contol by the LEI instruction. The state of each
bit of this register selects or deselects the particular
feature associated with each bit of the EN register
(EN 3 - EN o)·
1. The least significant bit of the enable register, ENo,
selects the 510 register as either a 4-bit shift register
or a 4-bit binary counter. With ENo set, 510 is an
asynchronous binary counter, decrementing its value
by one upon each low-going pulse ("1" to "0")
occurring on the SI input. Each pulse must be at least
two instruction cycles wide. SK outputs the value of
SKL. The SO output is equal to the value of EN 3 . With
EN o reset, 510 is a serial shift register shifting left
each instruction cycle time. The data present at 51
goes into the least significant bit of 510. SO can be
enabled to output the most significant bit of 510
each cycle time. (See 4 below.) The SK output
becomes a logic-controlled clock.
2. With ENj set the IN j input is enabled as an interrupt
input. Immediately following an interrupt, EN j is
reset to disable further interrupts.
3. With EN2 set, the L drivers are enabled to output the
data in a to the L 1/0 ports. Resetting EN2 disables
Internal Logic
The 4-bit A register (accumulator) is the source and destination register for most 1/0, arithmetic, logic and data
memory access operations. It can also be used to load
the Br and Bd portions of the B register, to load and
input 4 bits of the 8-bit a latch data, to input 4 bits of the
8-bit L 1/0 port data and to perform data exchanges with
the 510 register.
A 4-bit adder performs the arithmetic and logic functions of the COP420/421 L, storing its results in A. It also
outputs a carry bit to the 1-bit C register, most often employed to indicate arithmetic overflow. The C register, in
conjunction with the XAS instruction and the EN register,
2-71
"~
C
c:
o
o
"~
...&.
c:
o
o
"-'="
I\)
I\)
!""
o
o
"
CN
I\)
C
c:
o
o
"
CN
~
c:
o
o
"
CN
I\)
I\)
r-
...J
C\I
~
D..
o
o
:::r
N
C')
oD..
o
:::r
o
~
the L drivers, placing the Lila ports in a high·
impedance input state.
4 . EN 3, in conjunction with EN o, affects the SO output.
With ENo set (binary counter option selected) SO will
output the value loaded into EN 3. With ENo reset
(serial shift register option selected), setting EN3
enables SO as the output of the SIO shift register,
.Enable Register Modes -
outputting serial shifted data each instruction time.
Resetting EN3 with the serial shift register option
selected disables SO as the shift register output;
data continues to be shifted through SIO and can be
exchanged with A via an XAS instruction but SO
remains reset to "0." The table below provides a
summary of the modes associated with EN3 and ENo·
Bits EN3 and ENO
EN3
ENo
510
51
50
0
0
Shift Register
Input to Shift Register
0
5K
If SKL = 1, SK = Clock
If SKL = 0, SK = 0
D..
o
o
1
0
Shift Register
Input to Shift Register
If SKL = 1, SK = Clock
Serial Out
If SKL = 0, SK = 0
.J'
C\I
~
1
0
Binary Counter
Input to Binary Counter
If SKL = 1, SK = 1
0
If SKL = 0, SK = 0
D..
o
o
1
,
1
Binary Counter
Input to Binary Counter
:::r
~
D..
Interrupt
:::r
The following features are associated with the IN j
interrupt procedure and protocol and must be consid·
ered by the programmer when utilizing interrupts.
oo
~
D..
oo
IfSKL = 1,SK = 1
1
If SKL = 0, SK = 0
within the interrupt servicing routine since their
popping the stack will enable any previously saved
main program skips, interfering with the orderly
execution of the interrupt routine.
a. The interrupt, once acknowledged as explained
below, pushes the next sequential program counter
address (PC + 1) onto the stack, pushing in turn the
contents of the other subroutine·save registers to the
next lower level (PC + 1 .... SA .... SB .... SC). Any
previous contents of SC are lost. The program counter
Is set to hex address OFF (the last word of page 3)
and EN j is reset.
d. The first instruction of the interrupt routine at hex ad·
dress OFF must be a Nap.
e. A LEI instruction can be put immediately before the
RET to re·enable interrupts.
Initialization
The Reset Logic will initialize (clear) the device upon
power·up if the power supply rise time is less than 1 ms
and greater than 1,..s. If the power supply rise time Is
greater than 1 ms, the user must provide an external RC
network and diode to the RESET pin as shown below.
The RESET pin is configured as a Schmitt trigger input.
If not used it should be connected to Vce. Initialization
will occur whenever a logic "0" is applied to the RESET
input, provided it stays low for at least three instruction
cycle times.
b. An interrupt will be acknowledged only after the fol·
lowing conditions are met:
1. ENj has been set.
2. A low·going pulse ("1" to "0") at least two instruc·
tion cycles wide occurs on the INj input.
3. A currently executing instruction has been com·
pleted.
4. All successive transfer of control instructions and
successive LBls have been completed (e.g., if the
main program is executing a JP instruction which
transfers program control to another JP instruction,
the interrupt will not be acknowledged until the
second JP instruction has been executed).
c. Upon acknowledgement of an interrupt, the skip
logic status is saved and later restored upon popping
of the stack. For example, if an Interrupt occurs during
the execution of ASC (Add with Carry, Skip on Carry)
instruction which results in carry, the skip logic
status is saved and program control is transferred to
the interrupt servicing routine at hex address OFF. At
the end of the interrupt routine, a RET instruction is
executed to "pop" the stack and return program con·
trol to the instruction following the original ASC. At
this time, the skip logic is enabled and skips this
instruction because of the previous ASC carry. Sub·
routines and LQID instructions should not be nested
Upon initialization, the PC register is cleared to 0 (ROM
address 0) and the A, B, C, D, EN, and G registers are
cleared. The SK output is enabled as a SYNC output,
providing a pulse each instruction cycle time. Data
Memory (RAM) is not cleared upon initialization. The
first instruction at address 0 must be a CLRA.
---'1
P
+ - . -......
~
~~
&
- f-
RESET
S
U
P
~
Vee
eOP420l/4Z1l
f
GNO
Re,. 5, POWER SUPPl V RISE TIME
Power·Up Clear Circuit
2-72
o
-a
o
Oscillator
There are four basic clock oscillator configurations
available as shown by Figure 4.
SYNC output (See Functional Description, Initializa·
tion, above).
a. Crystal Controlled Oscillator. CKI and CKO are con·
nected to an external crystal. The instruction cycle
time equals the crystal frequency divided bY,32 (op·
tional by 16 or 8).
CKO Pin Options
In a crystal controlled oscillator system, CKO is used as
an output to the crystal network. As an option CKO can
be a SYNC input,as described above. As another option
CKO can be a general purpose input, read into bit 2 of A
(accumulator) upon execution of an INIL instruction. As
another option, CKO can be a RAM power supply pin (VR),
allowing Its connection to a standby/backup power sup·
ply to maintain the integrity of RAM data with minimum
power drain when the main supply is inoperative or shut
down to conserve power. Using either option is appro·
priate in applications where the COP420Ll421L system
timing configuration does not require use of the CKO pin.
b. External Oscillator. CKI is an external clock input
signal. The external frequency is divided by 32 (option·
al by 16 or 8) to give the instruction cycle time. CKO
is now available to be used as the RAM power supply
(V R), as a general purpose input, or as a SYNC input.
c. RC Controlled Oscillator. CKI is configured as a
single pin RC controlled Schmitt trigger oscillator.
The instruction cycle equals the oscillation frequen·
cy divided by 4. CKO is available as the RAM power
supply (V R) or as a general purpose input.
RAM Keep·Alive Option (Not available on COP422L)
d. Externally Synchronized Oscillator. Intended for use
in multi·COP systems, CKO is programmed to function
as an input connected to the SK output of another
COP chip operating at the same frequency (COP chip
with Lor C suffix) with CKI connected as shown. In
this configuration, the SK output connected to CKO
must provide a SYNC (instruction cycle) signal to
CKO, thereby allowing synchronous data transfer be·
tween the COPs using only the SI and SO serial I/O
pins in conjunction with the XAS instruction. Note
that on power·up SK is automatically enabled as a
Selecting CKO as the RAM power supply (VR) allows the
user to shut off the chip power supply (Vecl and maintain
data in the RAM. To insure that RAM data integrity is
maintained, the following conditions must be met:
1. RESET must go low before Vee goes below spee duro
ing power·off; Vee must be within spec before RESET
goes high on power·up.
2. During normal operation VR must be within the oper·
ating range of the chip, with (Vee -1) .;; VR';; Vee.
3. VR must be
CKI
CKO
~
3.3V with Vee off.
,
*...---IOl-----,
I
~ * . . .- -,--------.,
(SYNC)
I
I
CKO
COP4Z0/4Z1 L
CKO
t
SLr
EXTERNAL
CLOCK
VCC
(VR OR GENERAL
PURPOSE INPUT
PIN)
(VR OR GENERAL
PURPOSE INPUT
OR SYNC PIN)
RC Controlled Oscillator
Crystal Oscillator
Crystal
Value
455kHz
2.097 MHz
C2 (PF)
R (kQ)
C(pF)
Instruction
Cycle Time
(,.is)
51
82
100
56
19±15%
19±13%
Component Values
R1 (Q)
R2(Q)
C1 (pF)
4.7k
1M
220
220
1k
1M
30
6-36
Note: 200k,. R ,. 25k
360pF,. C,. 50pF
Figure 4. COP420/421L Oscillator
2-73
~
?5
o-a
~
c:
o
o-a
t
.r
I\)
...J
N
~
1/0 Options
Q.
o(.)
COP420U421L outputs have the following optional con·
figurations, illustrated in Figure 5:
::J
Q.
a. Standard - an enhancement mode device to ground
in conjunction with a depletion·mode device to Vee,
compatible with LSTTL and CMOS input require·
ments. Available on SO, SK, and all 0 and G outputs.
go
b. Open· Drain - an enhaneement·mode device to
. ground only, allowing external pull·up as required by
the user's application. Available on SO, SK, and all 0
and G outputs.
Q.
c. Push· Pull - An enhancement·mode device to ground
in conjunction with a depletion·mode device paralleled
by an enhancement·mode device to Vee. This configu·
ration has been provided to allow for fast rise and fall
times when driving capacitive loads. Available on SO
and SK outputs only.
d. Standard L - same as a., but may be disabled. Avail·
able on L outputs only.
~
o
~
o(.)
....f
N
~
Q.
o
(.)
::J
N
0:::/"
Q.
o(.)
:J
o
~
Q.
o(.)
The above input and output configurations share com·
mon enhaneement·mode and depletion·mode devices.
Specifically, all configurations use one or more of six
devices (numbered 1- 6, respectively). Minimum and
maximum current (lOUT and VOUT) curves are given in
Figure 6 for each of these devices to allow the designer
to effectively use these 1/0 configurations in designing
a COP420U421L system.
The SO, SK outputs can be configured as shown in a.,
b., or c. The o and G outputs can be configured as
shown in a. or b. Note that when inputting data to the G
ports, the G outputs should be set to "1". The L outputs
can be configured as in d., e., I. or g.
An important point to remember if using configuration
d. or I. with the L drivers is that even when the L drivers
are disabled, the depletion load device will source a
small amount of current (see Figure 6, device 2); however,
when the L lines are used as inputs, the disabled deple·
tion device cannot be relied on to source sufficient cur·
rent to pull an input to a logic 1.
e. Open Drain L - same as b., but may be disabled.
Available on L outputs only.
f. LED Direct Drive - an enhancement·mode device to
ground and to Vee, meeting the typical current
sourcing requirements of the segments of an LED
display. The sourcing device is clamped to limit
current flow. These devices may be turned off under
program control (See Functional Description, EN
Register), placing the outputs in a high·impedance
state to provide required LED segment blanking for a
multiplexed display. Available on L outputs only.
g. TRI·STATE@ Push·Pull - an enhancement·mode
device to ground and Vee. These outputs are TRI·
STATE outputs, allowing for connection of these
outputs to a data bus shared by other bus drivers.
~vailable on L outputs only.
COP421L
If the COP420L is bonded as a 24·pin device, it becomes
the COP421L, illustrated in Figure 2, COP420Ll421L
Connection Diagrams. Note that the COP421L does not
contain the four general purpose IN inputs (IN3;'INo).
Use of this option precludes, of course, use of the IN
options and the interrupt feature. All other options are
available for the COP421 L.
COP422L
If the COP421L is bonded as a 20'pin device, it becomes
the COP422L, as illustrated in Figure 2. Note that the
COP422L contains all the COP421L pins except Do, 0"
Go, and G,. COP422L also does not allow RAM power
supply input as a valid CKO pin option.
COP420LlCOP421L inputs have the following optional
configurations:
h. An on·chip depletion load device to Vee.
I. A Hi·Z input which must be driven to a "1" or "0" by
external components.
2-74
a. Standard Output
b. Open· Drain Output
OISABLE'~
c. Push·Pull Output
i·
(")
o"'tJ
(... IS DEPLETION DEVICEI
d. Standard L Output
fd
f. LED (L Output)
e. Open·Orain L Output
o
c::
Vcc
r-I
rt
(")
#6
"'"'~f
g. TRI·STATE® Push· Pull
(L Output)
o"'tJ
INPUT~~
Co)
~
c::
(")
o"'tJ
i. Hi·Z Input
h. Input with Load
Figure 5. Output Configurations
Input current INo-IN3
-100
-B
" 1\
-6 o
Q
-s
~
E
A~Ofr
o~ I MAX@Vr.r.=9.5V
!
~
~
Source current for
standard output
configuration
1 1 DEVICE d #2
-90
"\
o
-4
I"'
-3 o
IMAX}
Vcc ~ 4.SV
0
-2
°gsC~9.S
-1 o
~~
MIN@VCC~4.S
~I "I'
o
1.0 2.0 3.0 4.0 5.0 6.0 7.0 B.O
~
r-
Input current for
Lo- L7 when output
programmed OFF by
software
t-:: 1::0.
1
9.5
1.0
VIN (VOLTS)
o
2.0
1
2
3
VI/D
Source current for SO
and SK in push·pull
configuration
9.S
4
VOH fVOLTSI
Source Current for LO- L7
in TRI·STATE® Configura·
tion (High Current Option)
Source Current for LO- L7
in TRI·STATE® Configura·
tion (Low Current Option)
1.5
U
I .
:~~
I.. @-~j--~
JIIMAX@
1.0
l-H-l-+-+-+++-=+r+-+-I
fMIN@
.... VCC=9.5V
1.0
\
-1.2 .--...,----,---,-r-...,----..-r--,
DeVICE a, *2
and d *2
-120 ,-----,---r--....,..----,
DEVICE d #2
AND I #2
-100 I-'\.--+---+----j-----l
-2S0
-200
Source current for
standard output
configuration
Input Current for LO- L7
when Output Programmed
Off by Software
ha.-+-+'-'-t-:-I-+-+-I
=
~ -lS~+-~-1~+-+--+~f---i
!:
o L----'__---'-__....l..__....L-__..J
6
o
7
VOH (VOLTS)
VOH (VOLTS)
Output sink current for
Lo- L7 and standard drive
option for 00-03 and GO-G3
Output Sink Current GO-G 3
and 0 0-03 with Very High
Current Option
VOLiVOLTS)
Output sink current for
GO-G3 and 00-03 (for
high current option)
120 '--'--TT"--,-r--r--.,.-.,---,
4ro
700
ns
ns
ns
ns
ns
ns
CL=100pF, Vcc=5V±5%
TRI·STATE® outputs
65
20
400
65
20
400
320
100
al-ICSW----~/W-- -~,cs-I
k
I
1'"
J
X
IGO)
Figure 2a. MICROBUSTM Read Operation Timing
INTR
'W,
- 'W'IX
==1'--___
Figure 2b. MICROBUS Write Operation Timing
2-93
~
o
o"'D
~
~
oo
"'D
~
~t
o
o"'D
~o
o"'D
~
oo
"'D
~
~
Q.
o
~
,.. .
Ll
LO
SI
SO
SK
INO
IN3
GO
Gl
G2
G3
HO
HI
H2
H3
03
02
01
~
o
o
,!
Q.
oo
l
00
GNO
~
:i
8
10
11
12
13
14
15
16
17
18
19
20
COP4401
COP340
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
Vcc
L2
L3
IN2
INI
L4
L5
L6
L7
RO
Rl
R2
R3
R4
R5
R6
R7
L7
L6
L5
L4
INI
IN2
VCC
L3
L2
Ll
REm
CKI
CKO
Order Number COP440N, COP340N
NS Package N40A
Q.
GNO
CKO
CKI
RESET
8
23
COP4411
COP341 22
21
20
10·
19
11
18
12
17
13
16
14
15
7
GNO
CKO
CKI
RESET
L7
L6
L5
L4
VCC
L3
L2
Ll
Order Number COP441N, COP341N
NS Package N28A
10
11
12
24
23
22
21
20
COP4421
COP342 19
18
17
16
15
14
13
00
01
02
03
G3
G2
Gl
GO
SK
SO
SI
LO
Order Number COP442N, COP342N
NS Package N24A
Figure 3. Connection Diagrams
!
Q.
00
01
02
03
G3
G2
Gl
GO
IN3
INO
SK
SO
SI
LO
28
27
26
25
24
Pin
L7-Lo
Description
Pin
Description
8·blt bidirectional 1/0 port with
TRI·STATE~
CKI
System oscillator input
CKO
System oscillator output (or general
purpose input or RAM power supply)
System reset input
G3-Go
4·blt bidirectional 1/0 port
03- 0 0
4·bit general purpose output port
RESET
IN3-INo
4·blt general purpose Input port (not
available on COP4421COP342)
Vee
Power supply
GNO
Ground
H3- HO
4·bit bidirectional 1/0 port
(COP440/COP340 only)
R7-Ro
8·bit bidirectional 1/0 port with
TRI·STATE (COP440/COP340 only)
SI
Serial input
SO
Serial output (or general purpose output)
SK
Logie-controlled clock (or general
purpose output)
Figure 4. Input/output Timing Diagrams (Divide by 16 Mode)
2-94
o
o"'D
Functional Description
The block diagram of the COP440 is shown in Figure 1.
Data paths are illustrated in simplified form to depict
how the various logic elements communicate with each
other in implementing the instruction set of the device.
Positive logic is used. When a bit is set, it is a logic "1"
(greater than 2.0 volts). When a bit is reset, it is a logic
"0" (less than 0.8 volts).
A 4·bit adder performs the arithmetic and logiC func·
tions of the COP440, storing its results in A. It also
outputs a carry bit to the 1·bit C register, most often employed to indicate arithmetic overflow. The C register, in
conjunction with the XAS instruction and the EN register,
also serves to control the SK output. C can be outputted
directly to SK or can enable SK to be a sync clock each
instruction cycle time. (See XAS instruction and EN register description, below.)
Program Memory
The 8·bit T counter is a binary up counter which can be
loaded to and from M and A. The input to this counter is
software selectable from two sources: the first coming
from a divide-by-four prescaler (from instruction cycle
frequency) thus providing a 10·bit time base counter; the
second coming from IN2 input, changing the T counter
into an 8-bit external event counter (see EN register
below). In this mode, a low-going pulse ("1" to "0") of at
least 2 instruction cycles wide will increment the counter.
When the counter overflows, an overflow flag will be set
(see SKT insruction below) and an interrupt signal will
be sent to processor X. The T counter is cleared on reset.
Program Memory consists of a 2,048 byte ROM. As can
be seen by an examination of the COP440 instruction
set, these words may be program instructions, con·
stants, or ROM addressing data. Because of the special
characteristics associated with the JP, JSRP, JID, LaiD,
and LID instructions, ROM must often be thought of as
being organized into 32 pages of 64 words each.
ROM addressing is accomplished by an 11-bit PC register.
Its binary value selects one of the 2,048 8·bit words con·
tained in ROM. A new address is loaded into the PC
register during each instruction cycle. Unless the instruction is a transfer of control instruction, the PC register is
loaded with the next sequential 11·bit binary count value.
Four general·purpose inputs, IN 3-INQ, are provided; IN 1 ,
IN2 and IN3 may be selected, by a mask-programmable
option, as Read Strobe, Chip Select, and Write Strobe
inputs, respectively, for use in MICROBUSTM applications; IN 1 , by another mask-programmable option, can
be selected as a true zero·crossing detector with the
output triggering an interrupt or being interrogated by
an instruction. These two mask·programmable options
are mutually excl usive.
ROM instruction words are fetched, decoded and exe·
cuted by the Instruction Decode, Control and Skip Logic
circuitry.
Data Memory
Data memory consists of a 640·bit RAM, organized as 10
data registers of 16 4-bit digits. RAM addressing is im·
plemented by an 8·bit B register whose upper 4 bits (Br)
select 1 of 10 (0-9) data registers and lower 4 bits (Bd)
select 1 of 16 4·bit digits in the selected data register.
While the 4·bit contents of the selected RAM digit (M) is
usually loaded into, or from, or exchanged with the A
register (accumulator), it may also be loaded into or from
the a latches, L port, R port, EN register, and T counter
\IIHernGtI lillie UC:1titj c.;UUlllt:::I). nMIVI Illay
d.1~U
The D register provides 4 general-purpose outputs and
is used as the destination register for the 4·bit contents
of Bd.
The G register contents are outputs to a 4-bit generalpurpose bidirectional 1/0 port. Go may be mask·
programmed as an output for MICROBUS applications.
ut::: IUdU,=,U
The H register contents are outputs to a 4-bit generalpurpose bidirectional 1/0 port.
from 4 bits of a ROM word. RAM addressing may also be
performed directly to the lower 8 registers by the LDD
and XAD instructions based upon the 7·bit contents of
the operand field of these instructions. The Bd register
also serves as a source register for 4·bit data sent directly
to the D outputs. RAM register 8 (Br = 8) also serves as a
subroutine stack. Note that it is pOSSible, but not recom·
mended, to alter the contents of the stack by normal data
memory access commands.
Internal Logic
The a register is an internal, latched, 8·bit register, used
to hold data loaded to or from M and A, as well as 8-bit
data from ROM. Its contents are outputted to the L 1/0
ports when the L drivers are enabled, under program
control. With the MICROBUS option selected, a can
also be loaded with the 8·bit contents of the L 1/0 ports
upon the occurence of a write strobe from the host CPU.
Note that unlike most other COPSTM controllers, a is
cleared on reset.
The 4·bit A register (accumulator) is the source and destination register for most 1/0 arithmetic, logiC, and data
memory access operations. It can also be used to load
the Br and Bd portions of the B register, N register, to
load and input 4 bits of the 8-bit a latch, EN register, or
T counter, to input 4 bits of a ROM word, Lor R 1/0 port
data, to input 4·bit G, H, or IN ports, and to perform data
exchanges with the SIO register. The accumulator is
cleared upon reset.
The 8 L drivers,when enabled, output the contents of
latched a data to the L 1/0 ports. Also, the contents of L
may be read directly into A and M. As explained above,
the MICROBUS option allows L 1/0 port data to be
latched into the a register. The L 1/0 port can be directly
connected to the segments of a multiplexed LED display
(using the LED Direct Drive output configuration option)
with a data being outputted to the Sa-Sg and decimal
point segments of the display.
The R register, when enabled, outputs to an 8-bit general·
purpose, bidirectional, 1/0 port.
2-95
e
0l:Io
o
o"'D
~
oo
"'D
0l:Io
ft
o
o"'D
~
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o
o"'D
Co)
-oo
:9::
"'D
Co)
~
~
a..
oo
o
The SIO register functions as a 4·bit serial·in/serial·out
shift register for MICROWIRE™ I/O and COPSTM periph·
erals, or as a binary counter (depending on the contents
of the EN register; see EN register description, below).
Its contents can be exchanged with A, allowing it to in·
put or output a continuous serial data stream.
The EN register is an internal 8-bit register loaded under
program control by the LEI instruction (lower 4 bits) or
by the CAME instruction. The state of each bit of this
register selects or deselects the particular feature associated with each bit of the EN register:
a..
The XAS instruction copies the C flag into the SKL latch.
In the counter mode, SK is the output of SKL; in the shift
register mode, SK outputs SKL ANDed with the instruc·
tion cycle clock.
selects the SIO register as either a 4-bit shift register
or a 4-bit binary counter. With ENo set, SIO is an
asynchronous binary counter, decrementing its value
by one upon each low-going pulse ("1" to "0") occurring on the SI input. Each pulse must be at least two
instruction cycles wide. SK outputs the value of SKL.
The SO output is equal to the value of EN 3. With ENo
reset, SIO is a serial shift register left shifting 1 bit
each instruction cycle time. The data present at SI
goes into the least significant bit of SIO. SO can be
enabled to output the most significant bit of SIO
each cycle time. The SK output becomes a logiccontrolled clock.
-~
a..
~
oo
~
a..
o
~
;a..
oo
!
a..
o
o
I.
O. The least significant bit of the enable register, EN o,
The 2-bit N register is a stack pOinter to the data memory
register 8 where the subroutine return address is located.
It pOints to the next location where the address may be
stored and increments by 1 after each push of the stack,
and decrements by 1 before each pop. The N register
can be accessed by exchanging its value with A and is
cleared on reset. The stack is 4 addresses deep, 12 bits
wide, and does not check for overflow or empty conditions. The RAM digit locations where the addresses are
stored are shown in Figure 5. The LSBs of the addresses
are at digits 0, 4, 8, and 12. The MSBs of digits 2, 6, 10,
and 14 contain an interrupt status bit (see Interrupt
description, below). The four unused digits (3, 7, 11, and
15) can be used as general data storage. When a subroutine call or interrupt occurs, an 11-bit return address
and an interrupt status bit are stored in the stack. The N
register is then incremented. When a RET or RETSK
instruction is executed, the N register is decremented
and then the return address is fetched and loaded into
the program counter. The address and interrupt status
bits remain in the stack, but will be overwritten when
the next subroutin'e call or interrupt occurs.
1. With EN, set, interrupt is enabled with EN4 and EN5
selecting the interrupt source. Immediately following
an'interrupt, EN, is reset to disable further interrupts.
2. With EN2 set, the L drivers are enabled to output the
data in Q to the L I/O port. Resetting EN2 disables the
L drivers, placing the L I/O port in a high-impedance
input state. A special feature of the COP440 and
COP441 is that the MICROBUSTM option will change
the function of this bit to disable any writing into Go
when EN2 is set.
3. EN3, in conjunction with ENo, affects the SO output.
With ENo set (binary counter option selected) SO will
output the value loaded into EN3. With ENo reset
(serial shift register option selected), setting EN3
enables SO as the output of the SIO shift register,
outputting serial shifted data each instruction time.
Resetting EN3 with the serial shift register option
selected disables SO as the shift register output;
data continues to be shifted through SIO and can be
exchanged with A via an XAS instruction but SO
remains set to "0." Table 1 below provides a summary of the modes associated with EN3 and ENo.
DIGITS NDT USED IN STACK
DATA
MEMDRY
REGISTER 8
DIGIT
Figure 5. Subroutine Return Address
Stack Organization
Table 1. Enable Register Modes EN3
ENo
0
0
1
Bits EN3 and ENo
51
SO
Shift Register
Input to Shift Register
0
If SKL
If SKL
0
Shift Register
Input to Shift Register
Serial Out
If SKL
If SKL
0
1
Binary Counter
Input to Binary Counter
0
If SKL
If SKL
1
1
Binary Counter
Input to Binary Counter
1
If SKL
If SKL
510
,
2-96
SK
= 1, SK = Clock
= 0, SK = 0
= 1, SK = Clock
= 0, SK = 0
= 1, SK = 1
= 0, SK = 0
= 1, SK = 1
= 0, SK = 0
o
o
interrupt may be enabled only if the interrupt source
is not changing. A sample code for changing the inter·
rupt source and enabling the interrupt is as follows:
CAME
; disable Interrupt & alter interrupt source
5MB
; set interrupt enable bit
CAME
; enable interrupt
f. An interrupt status bit is stored together with the
return address in the stack. The status bit is set if an
interrupt occurs at a point in the program where the
next instruction is to be skipped; upon returning from
the interrupt routine, this set status bit will cause the
next instruction to be skipped. Subroutine and inter·
rupt nesting inside interrupt routines are allowed.
Note that this differs from the COP420/420C/420U444L
series.
4, EN5 and EN4 select the source of the interrupt signal.
5. The possible sources are as follows:
EN5 EN4
Interrupt Source
o 0 IN1 (Iow'going pulse)
o 1 CKO input (if mask·programmed as an input)
0 Zero·crossing (or IN1 level transition)
1
1
1 T counter overflows
EN4 determines the interrupt routine location.
6. With ENs set, the internal 8·bit T counter will use IN2
as its input. With EN6 reset, the input to the T counter
is the output of a divide by four prescaler (from in·
struction cycle frequency), thus providing a 10·bit
time·base counter.
7. With EN? set, the R outputs are enabled; if EN? = 0,
the R outputs are disabled.
The folJowing features are associated with the interrupt
procedure and protocol and must be considered by the
programmer when utilizing interrupts.
b. An interrupt wiIJ be acknowledged only after the
folJowing conditions are met:
1. EN1 has been set.
• • •___ , ___ ,
G.
I
VI
0.11
I;;iA~II;;iIII!WI.1
11I~"""Ut-'~
'''t-' ... ~,
H ......... :;:, ...... ,
_
•. 1 _ -
ho.+lAu~an
t"' ............
the hnC!t r.DII ~nri thlQ r.np!=; nrnr.A~~nr_
Gin Ollt-
put can be separated from other G outputs by the EN2
bit (see EN description above).
must be at least two instruction cycles wide.
3. A currently executing instruction has been com·
pleted·.
4. AIJ successive transfer of control instructions and
successive LBls have been completed (e.g., if the
main program is executing a JP instruction which
transfers program control to another JP instruction,
the interrupt wiIJ not be acknowledged until the
second JP instruction has been executed.
.
C. The instruction at hex address OFF must be a NOP.
d. A CAME or LEI instruction may be put immediately
before the RET instruction to re·enable interrupts.
This option has been designed for compatibility with
National's MICROBUS - a standard interconnect sys·
tem for 8·bit parallel data transfer between MOS/LSI
CPUs and interfacing devices. (See MICROBUS National
Publication.) The functional and timing relationships
between the COPS processor signal lines affected by this
option are as specified for the MICROBUS interface, and
are given in the AC electrical characteristics and shown
in the timing diagrams (Figure 2). Connection of the
COP440 to the MICROBUS is sh9wn in Figure 6.
Note: TRI·STATE@ outputs must be used on L port.
e. If the interrupt signal source is being changed, the
interrupt must be disabled prior to, or at, the same
time with the change to avoid false interrupts. An
2-97
~t"
o
o
"
~
":!:t
Co)
The COP440 series have an option which allows them to
be used as peripheral microprocessor devices, inputting
and outputting data from and to a host microproces·
sor (JAP). IN 1, IN2 and IN3 general purpose inputs become
MICROBUS·compatible read'strobe, chip·select, and
write·strobe lines, respectively. IN1 becomes RD - a
logic "0" on this input will cause a latch data to be en·
abled to the L ports for input to the "P. IN2 becomes CS
- a 10gic"0" on this line selects the COPSTM processor
as the lAP peripheral device by enabling the operation of
the RD and WR lines and allows for the selection of one
of several peripheral components.IN3 becomes WR - a
logic "0" on this line will write bus data from the L ports
to the a latches for input to the COPS processor. Go be·
comes INTR, a "ready" output, reset by a write pulse
from the lAP on the WR line, providing the "handshaking"
capability necessary for asynchronous data transfer
a. The interrupt, once acknowledged as explained
below, pushes the next sequential program counter
'address (PC + 1) together with an interrupt status bit,
onto the program counter stack residing in data memo
ory. Any previous contents at the bottom of the stack
are lost. The program counter is set to hex address
OFF (the last word of page 3) and EN1 is reset. If EN4
is reset, the next program address is hex 100; if EN4
is set, the next program address is hex 300; thus pro·
viding a different interrupt location for different inter·
rupt sources.
o
o
"~
oo
o
MICROBUS™ Interface
(not available in COP442, COP342)
Interrupt
"~
o
o
"~
POWER
SUPPLY
CLOCK
INTERRUPT (INTR)
MICROPROCESSOR
READ STROBE (liii)
CHIP SELECT (CS)
WRITE STROBE (WII)
IN
OUT
H3-HD
RESET
Figure 6.
MICROBUSTM Option Interconnect
Zero·Crossing Detection
(not available on the COP442, COP342)
The following features are associated with the IN, pin:
ININ and INIL instructions Input the state of IN, to A,;
IN, interrupt generates an interrupt pulse when a lowgoing transition ("1" to "0") occurs on IN,; zero-crossing
interrupt generates an interrupt pulse when an IN, transition occurs (both "1" to "0" and "0" to "1").
(see Figure 7b), IN, will have logic HIGH and LOW levels
that are defined for the IN port (see option list).
The zero-crossing detector input contains a small hysteresis (SOmV typical) to eliminate signal noise, and Is
not a high impedance input but contains a resistive load
to ground. Since this input can withstand a voltage
range of -0.8V to +12V, an external clamping diode is
needed for most input signals, as shown In Figure 7a, to
limit the voltage below ground. An external resistor, Rs
may be needed for the following two cases:
If the zero-crossing detector is mask-programmed in (see
Figure 7a), the INILinstructlon and zero-crossing interrupt
will Input the state of IN, through the true zero-crossing
detector ("1" If input> OV, "0" if input < OV). The ININ
instruction and IN, interrupt will then have unique logic
HIGH and LOW levels depending on the IN port Input
level chosen. If normal (TTL) level is chosen, logic HIGH
level Is 3.0V (3.3V for COP340/341) and logic LOW level
Is 0.8V (0.6V for COP340/341); If high trip level Is chosen,
logic HIGH level Is S.4V and logic LOW level is 1.2V. If
the zero-crossing detector Is not mask-programmed In
a. Input signal exceeds 12V; Rs and the internal resistor
act as a voltage divider to reduce the voltage at the
Input pin to below 12V.
b. Signal comes from a low Impedance source; when
the voltage at the pin is clamped to -0.7V by the forward bias voltage of an external diode, Rs limits the
current going through the diode.
IN IN
....L.
00
V-V
RS
IN'
IN' INTERRUPT
(EN5.EN4=OO)
(NEGATIVE EDCE)
EXTERNAL
t--::i>-~--..J
DIDDE
CLAMP
ZERO-CROSSING INTERRUPT
(EN5.EN4=IO)
(POSITIVE & NEGATIVE EDGE)
·NOTE: THIS INPUT HAS A DIFFERENT
SET onOGIC HIGH AND LOW LEVELS;
SEE ABOVE DESCRIPTION
a. Zero·Crossing Detect Logic Option
ININ
....L.
........",,,. INI INTERRUPT
(EN5.EN4=OO)
(NEGATIVE EDGE)
ZERO-CROSSING INTERRUPT
(EN5,EN4='O)
(POSITIVE &. NEGATIVE EDGE)
b. IN, without Zero-Crossing Detect Logic
Figure 7_ IN, Mask·Programmable Options
2-98
o
o."
Initialization
The reset logiC, internal to the COP440, will initialize
the device upon power-up if the power supply rise time
is less than 1 ms and greater than 1"s_ If the power
supply rise time is greater than 1 ms, the user must
provide an external RC network and diode to the RESET
pin as in Figure 8_ The RESET pin is configured as a
Schmitt trigger input. If not used, it should be connected
to Vee. Initialization will occur whenever a logic "0" is
applied to the RESET input, provided it stays low for at
least three instruction cycle times.
b. External Oscillator. CKI Is an external clock Input signal. The external frequency is divided by 16 (optional
by 8 or 4) to give the cycle frequency. If the divide;by-4
option Is selected, the CKllnput level is the Schmitttrigger level. CKO is now available to be used as the
RAM power supply (VR) or as a general purpose input.
c. RC Controlled Oscillitor. CKI is configured as a single
pin RC controlled Schmitt trigger oscillator. The cycle
frequency equals the oscillation frequency divided
by 4. CKO is available for non-timing functions.
Upon initialization, the PC register is cleared to 0 (ROM
address 0) and the A, B, C, D, EN, G, H, IL, L, N, a, R, and
T registers are cleared. The SK output is enabled as a
SYNC output by setting the SKL latch, thus providing a
clock. RAM (data memory and stack) is not cleared. The
first instruction at address 0 must be a CLRA.
P +
o
W
E
R
S
U
P
P
L
y
-....
eKO Pin Options
As an option, CKO can be an oscillator output. In a
crystal controlled oscillator system, this signal Is used
as an output to the crystal network. As another option,
eKO can be an Interrupt Input or a general purpose input,
reading Into bit 2 of A (accumulator) through the INIL
Instruction. As another option, eKO can be a RAM power
supply pin (VR), allowing its connection to a standbyl
backup power supply to maintain the data integrity of
RAM registers 0-3 with minimum power drain when the
main supply Is inoperative or shut down to conserve
power. Using either of the two latter options is appropriate in applications where the system configuration
does not require use of the eKO pin for timing functions.
I
Vcc
COP440
.4~
RESET
T
GNO
RC,. 5 x POWER SUPPL Y RISE TIME
RAM Keep·Allve Option
Figure 8. Power-Up Clear Circuit
Selecting eKO as the RAM power supply (VR) allows the
user to shut off the chip power supply (Ved and maintain
data in the lower 4 registers of the RAM. To insure that
RAM data Integrity Is maintained, the following conditions must be met:
Oscillator
There are three basic clock oscillator configurations
available, as shown by Figure 9.
1. RESET must go low before Vcc goes below spec
during power-off; Vcc must be within spec before
RESET goes high on power·up.
a. Crystal Controlled Oscillator. CKI and CKO are connected to an external crystal. The cycle frequency
equals the crystal frequency divided by 16 (optional
by 8). Thus a 4 MHz crystal with the dlvlde-bY·16 option
"",IA"tAr! will oive a 250kHz cvcle frequency (4"s
Instruction cycle time).
2. When Vcc Is on, VR must be within the operating
voltage range of the chip, and within 1 volt of Vcc.
;j. vR must oe ~ .:J.,;JV Willi ·yee v;;.
A
CKI
Crystll Osclilitor
C
CKO
10M
..n..r
Rl
EXTERNAL
CLOCK
(CLOCK OUTPUT,
VR OR GENERAL
PURPOSE INPUT PIN)
Crystll Vllue
R1
4MHz
3.58MHz
2.10MHz
lk
lk
2k
RC Controlled Osclilitor
5-36 pF
a. Crystal Oscillator
b. External Oscillator
c. RC Controlled Oscillator
R(kQ)
C(pF)
Instruction
Execution
Time ("s)
13
6.8
8.2
22
100
220
300
100
5.0±20%
5.3±23%
8.0±22%
8.2±17%
Note: 5kQ " R " 50kQ
SOpF" C" 360pF
Figure 9. COP440/441/442 Oscillators
2-99
t
eo
o
t'
...I.
(5
o."
fto
o."
~
o."
CN
~
(5
o
."
~
~
C"')
11.
oo
~
C"')
11.
o
~
11.
oo
~
11.
oo
~
oo:t
11.
o
~oo:t
11.
oo
1/0 Options
Notes:
1. When the driver is disabled, the depletion device
may cause the output to settle down to an intermediate level betwee,n Vee and GND. This voltage
cannot be relied upon as a "1" level when reading
the L inputs. The external signal must drive it to a
"1" level.
2. Much power is dissipated by this driver in driving
an LED. Care must be taken to limit the power dissipation of the chip to within the absolute maximum ratings specified.
COP440 inputs have the following optional configurations, illustrated in Figure 10:
a_ An on-chip depletion load device to Veeb_ A Hi-Z input which must be driven to a "1" or "0" by
external components_
c_ A resistive load to GND for the zero-crossing input
option (IN, only)_
'
COP440 outputs have the following optional configurations:
d. Standard - an enhancement mode device to ground
in conjunction with a depletion-mode device to Vee,
compatible with TTL and CMOS input requirements.
Available on SO, SK, D, G, and H outputs.
i. TRI·STATE® Push· Pull - an enhancement-mode
device to ground and Vee. These outputs are TRISTATE outputs, allowing for connection of these
outputs to a data bus shared by other bus drivers.
Available on Land R outputs only (in TRI-STATE mode
on reset).
e. Open· Drain an enhancement-mode device to
grou'nd only, allowing external pull-up as required by
the user's application. Available on SO, SK, D, G, L, H,
and R outputs.
j. Push·Pull R - same as f., but may be disabled. Available on R outputs only.
f. Push· Pull - An enhancement-mode device to ground
in conjunction with a depletion-mode device paralleled by an enhancement-mode device to Vee. This
configuration has been provided to allow for fast rise
and fall times when driving capacitive loads. Available
on SO and SK outputs only.
g. Standard L,R - same as d., but may be disabled.
Available on Land R outputs only (disabled on reset).
h. LED Direct Drive - an enhancement-mode device to
ground and Vee together with a depletion device to
Vee meeting the typical current sourcing requirements
of the segments of an LED display. The sourcing
devices are clamped to limit current flow. These
devices may be turned off under program control
(See Functional Description, EN Register), placing
the output in a high-impedance state to provide
required LED segment blanking for a multiplexed
display. Available on L outputs only.
k. Additional depletion pull·up - a depletion load to Vee
with the same current sourcing capability as the input
load a., in addition to the output drive chosen. Available on Land R outputs only. This device cannot be
disabled; therefore, open-drain outputs with "1"
output and TRI-STATE outputs do not show highimpedance characteristics. This device is useful in
applications whlilre a pull-up with low source current
is desired, e.g., reading keyboards and switches.
The above input and output configurations share common enhancement-mode and depletion-mode devices.
Specifically, all configurations use one or more of six
devices (numbered 1-6 respectively). Minimum and
maximum current (lOUT and VOUT) curves are given in
Figures 11 and 12 for each of these devices to allow the
designer to effectively use these 110 configurations
in designing a COP440 system.
Vcc
r-I
rt
#,
INPUT~
".,~ '''~
~2i~
a. Input with Load
f. Push·Pull Output
b. Hi-Z Input
c. Zero·Crossing Input
g. Standard L,R Outputs
DlSABLE~#~VCC
::-t .. #4
d. Standard Output
i. TRI·STATE® Push·Pull
(L,R) Outputs
4c_5.:.
C
L.R OUTPUT _
e. Open-Drain Output
.....
#3
k. Additional L,R Outputs
Pull-Up
j. Push·Pull R Outputs
Figure 10. Input/Output Configurations
2-100
(A'S DEPLETION DEVICE)
..:_,...
h. LED (L) Outputs
(")
30
0.3
0.2
'i
""E
I
~
52
'\ '\
"\ r--.
20
::>
!2
0.1
//
""EI
VCC~6.3V
~
~
E
o"'0
t
10
(MA~
:/
E
VCC~4.5v'" ~
I
V
..........
\
!?
\
-
£.I -
,.;-
(MIN.)
OEVICE 1
VOUT - VOLTS
a. Input Load Source Curent
~
20
VCC~4.5V (MAXyi-"'"
0.3
I
~
!2
~
§
0.5
~
~
""E
0.2
15
VCC~6.3V
'\
""E
1.0
~
o
20
VOUT - VOLTS
""~
1.0
OEVICE 3
0.2 I----'K--f---j--f_-+--/
":bhllill
VOUT - VOLTS
OEVICE 5
VOUT - VOLTS
h. TRI·STATE® Output Source Current
DEVICE 4
i. Depletion Load OFF Current
.---,-r--r---,-,----,-.,
20
l/\
1'---t-~f_-f--I-+--f-_1
2.0
15 I---'\+---I~
""EI
I
~
10 f_-t-~f_--+\-I-+--I__I
::>
!2
1.0
II
'I
VOUT~2V
~
15
(MAX.)
""
\ vcc ~ 6.3V
1\
o
VOUT - VOLTS DEVICES 4 ANO 6
./
/'
\
\
o
~
10
§
o
k. LED Output Minimum Source Current
Figure 11. COP440/4411442 1/0 Characteristics
2-101
V
/'
-
4.5
VOUT - VOLTS DEVICES 4 ANO 6
/'
V
E
VCCi4.5i\
j. LED Output Source Current
I
o
0.3 I\--+--f---j--f_-+--/
VOUT - VOLTS OEVICES 4 AND 5
25
I--
I. Output Sink Current
0.5
g. Push· Pull Source Current
~I::r(M+-
DEVICE 4
~
0.5
~
'"'-
1.5
!2
§
/'
'"
~}6.31 (MIN.)I
/
~
f/;
VOUT - VOLTS
:;
~
"-
I
10
e. Standard Output Minimum Source
Current
1.5
I
'\
o
DEVICE 4
d. Standard Output Source Current
""E
~
\
t-- VICC~i·5V
VOUT - VOLTS
""EI
'\.
~
0.1
o
,...
I.;--VCC~6.3V (MAX.)
\
1.0
DEVICE 2
c. Zero·Crossing Detect Input
Current
1\
1.5
I
VIN - VOLTS
b. Input Load Minimum Source Current
0.4
""E
OEVICE 1
(MIN.)
I
5.5
o"'0
~
n
o"'0
J;;
-1
VOUT - VOLTS
(")
6.5
VOUT - VOLTS OEVICES 4 AND 6
I. LED Output Direct LED Drive
(")
o"'0
Co)
~
a
o
"'0
Co)
::
(;
o"'0
Co)
~
I\)
N
0I:t'
C')
D..
o
3D
0.3
~
~
D..
o
io
~
0.2
c
I
~
"
20
"3.
I
....
:::I
E
10
-
4
~
D..
.
D..
oo
!
Ei
1----+--''-
i!!
....I
101----t-\r-\+--1---+-~
§
1.0
£
r
;( \~,...,,\
o
VCC - VOLTS DEVICES 4 AND 6
j. LED Output Source Current
o
r---
\
VCcr'SV
4
15
i!!
I
~
10
,/
/
/"
:=
i\
1\ ~
(MIN.)
o
4.5
VOUT - VOLTS DEVICES 4 AND 6
k. LED Output Minimum Source Current
Figure 12. COP340/3411342 I/O Characteristics
2-102
5.0
5.S
6.0
VDUT - VOLTS DEVICES 4 AND 6
I. LED Output Direct LED Drive
(')
Power Dissipation
In order not to damage the device by exceeding the absolute maximum power dissipation rating, the amount of
power dissipated inside the chip must be carefully controlled_ As an example, an application uses a COP440 in
a room temperature (25°C) environment with a Vee power
supply of 6V; IN and SI inputs have internal loads; G and
o ports drive loads that may sink up to 2 mA into the chip;
H port with standard output option reads switches; L
port with the LED option drives a multiplexed sevensegment display; R, SO and SK drive MOS inputs that do
not source or sink any current.
g_ R, SO, and SK do not dissipate any significant amount
of power because they do not not need to source or
sink any current.
Total power dissipation (TPO) inside the device is the
sum of items b through g above_
TPO =210+9+6+ 36+476mW= 737mW
This is within the 750mW limit at room temperature_
If this application has to operate at 70°C, then the
power dissipation must be reduced to meet the limit
at that temperature_ Some ways to achieve this would
be to limit the LED current or to use an external LED
driver.
a_ At 25°C, maximum power dissipation allowed = 750mW_
b_ Power dissipation by chip except 1/0 = Ice x Vec =
35mA x6V =210mW_
At 70°C the absolute maximum power dissipation
rating drops to 400mW_ The user must be careful not
to exceed this value_
c_ Maximum power dissipation by IN, SI =
5xO_3mAx6V=9mW
d_ G and 0 ports are sinking current from external loads;
maximum output voltage with 2mA sink current is
less than OAV_ Power dissipation by G and 0 ports =
2mA xOAVx8=6AmW
COP440 Series Devices
f. When the seven segments of the LED are turned on,
the output voltage is about 2V, so that the segment
current is 17mA_ Power dissipation by L port =
7x 17mA x(6V -2V)=476mW
This power dissipation caused by driving LEOs is
usually the highest among the various sources_
COP340, COP341, and COP342 are extended temperature versions of the COP440, COP441, and COP442, respectively_
COP440 Series Instruction Set
Table 2 is a symbol table providing internal architecture,
Table 3 provides the mnemonic, operand, machine code,
instruction operand and operation symbols used in the
data flow, skip conditions and description associated with
instruction set table_
each instruction in the COP440 series instruction set.
Table 2_ COP440 Series Instruction Set Symbols
---,
Symbol
Definition
Definition
Symbol
INTERNAL ARCHITECTURE SYMBOLS
INSTRUCTION OPERAND SYMBOLS
A
B
Br
Bd
C
D
EN
G
H
IL
d
IN
IN,Z
L
M
N
PC
Q
R
SID
SK
T
4-bit Accumulator
8-bit RAM Address Register
Upper 4 bits of B (register address)
Lower 4 bits of B (digit address)
1-bit Carry Register
4-bit Data Output Port
8-bit Enable Register
4-bit Register to latch data for GilD Port
4-bit Register to latch data for H 110 Port
Two 1-bit Latches associated with the IN3 or
INo Inputs
4-bit Input Port
Zero-Crossing Input
8-bit TRI-STATE® 110 Port
4-bit contents of RAM Memory painted to by
B Register
2-bit subroutine return address stack pointer
11-bit ROM Address Register (program
counter)
8-bit Register to latch data for L 110 Port
8-bit Register to latch data for R TRI-STATE
110 Port
4-bit Shift Register and Counter
Logic-Controlled Clock Output
8-bit Binary Counter Register
2-103
r
a
y
RAM(s)
RAMN
ROM(t)
4-bit Operand Field, 0-15 binary (RAM Digit
Select)
4-bit Operand Field, 0-9 binary (RAM
Register Select)
11-bit Operand Field, 0-2047 binary (ROM
Address)
4-bit Operand Field, 0-15 binary (Immediate
Data)
Content of RAM location addressed by s
Content of RAM location addressed by
stack pointer N
Content of ROM location addressed by t
OPERATIONAL SYMBOLS
+
-
-=
Ii.
..
:
V
~
o'tJ
~
o'tJ
(;
~
(')
o'tJ
~
(')
If the COP440 is bonded as a 28- or 24-pin device, it becomes the COP441 or COP442, respectively, as illustrated
in Figure 3_ Note that the COP441 and COP442 do not
include Hand R ports_ In addition, the COP442 does not
include IN inputs; use of this option precludes the use of
the IN options, the interrupt feature with IN as input, the
zero-crossing detect option, IN2 external event counter
input, and the MICROBUSTM option_ All other options
are available_
e_ Maximum power dissipation by H port =
4x 1_5mA x6V =36mW
o'tJ
Plus
Minus
Replaces
Is exchanged with
Is equal to
The one's complement of A
Exclusive-OR
Range of values
OR
o'tJ
(0)
-o
~
( ')
'tJ
(0)
~
~
Table 3. COP440 Series Instruction Set
CO)
0-
oo
-~
Mnemonic Operand
Hex
Code
Machine
Language Code
(Binary)
Data Flow
Description
Skip Conditions
0-
ARITHMETIC/LOGIC INSTRUCTIONS
~
ASC
30
10011100001
A+C+RAM(B) - A
Carry - C
Carry
Add with Carry, Skip on
Carry
o
ADD
31
\0011\0001\
A+RAM(B)- A
None
Add RAM to A
o
,0
ADT
4A
\01 00\1 01 01
A+10 10 -A
None
Add Ten to A
:~
AISC
5-
\0101\
A+y-A
Carry
Add Immediate, Skip on
Carry (y '" 0)
o
0-
CASC
10
\0001\0000\
A+ RAM(B)+C - A
Carry - C
Carry
Complement and Add with
Carry, Skip on Carry
~
:
CLRA
00
\0 ° ° 010 ° ° 0\
O-A
None
Clear A
0-
COMP
40
\010°1°000\
A-A
None
One's complement of A to A
~
NOP
44
\01 00\0 1 00\
None
None
No Operation
Av M-A
None
OR RAM with A
0-
o
Y
OR
o
\
33
1A
10 0 11 10 011\
RC
32
\°011\ 001 °1
"O"-C
None
Reset C
SC
22
\001 °1°° 1 01
"1"- C
None
Set C
XOR
02
1°°0°1°°1 °1
A .. RAM(B)- A
None
Exclusive-OR RAM with A
0-
o
Y
\0 ° ° 1\1 ° 1 01
TRANSFER OF CONTROL INSTRUCTIONS
JID
JMP
JP
a
a
FF
11111111111
ROM (PC10:8, A,M) - PC7:0 None
Jump Indirect (Note 3)
6-
10 1 1 0IOlalO:sl
a- PC
None
Jump
--
87:0
86:0
111
(pages 2,3 only)
or
I
a - PC6:0
None
Jump within Page (Note 4)
\11\ a5:0 I
(all other pages)
a - PC5:0
PC+1- RAMN
N+1- N
00010 - PC10:6
a - PC5:0
None
Jump to Subroutine Page
(Note 5)
PC+1 - RAMN
N+1- N
a - PC
None
Jump to Subroutine
--
-JSRP
a
JSR
a
I
--
\1 °1
85:0
I
I
6-
1° 110\1\ alO:81
--
I
a7:0
RET
48
1°1°°1 10 °°1
N-1- N
RAMN- PC
None
Return from Subroutine
RETSK
49
1°1°°1 1001 1
N-1- N
RAMN - PC
Always Skip on Return
Return from Subroutine
then Skip
I
2-104
o
o"'C
Table 3. COP440 Series Instruction Set (continued)
Mnemonic Operand
Hex
Code
:t
Machine
Language Code
(Binary)
E!
Data Flow
Skip Conditions
Description
MEMORY REFERENCE INSTRUCTIONS
o
o"'C
~
CAME
CAMO
CAMT
CEMA
COMA
CTMA
33
1°°111°0111
1F
A- EN7:4
None
Copy A, RAM to EN
None
Copy A, RAM to 0
None
Copy A, RAM to T
None
Copy EN 10 RAM, A
1°001111111
RAM (B) - EN3:0
33
1°0111°0111
A- 07:4
3C
1°0111110°1
RAM (B) - 03:0
33
1°°111°°111
A- T7:4
3F
1°°11111111
RAM(B) - T3:0
33
1°0111°0 111
EN7:4 - RAM(B)
OF
1°0°°111111
EN3:0- A
33
1°0111°0111
Copy 0 10 RAM, A
1° 01 °111 001
07:4 - RAM(B)
03:0- A
None
2C
None
Copy T to RAM, A
1°0111°0 111
T7:4 - RAM(B)
2F
1°°1 °1 1111 1
T3:0- A
r
-5
1°°1 r 1°1011
r=0:3
RAM(B)- A
Brer- Br
None
Load RAM Into A,
Exclusive·OR Br with r
LDD
r,d
23
10 °1 1 010 ° 111
d
101 r
r=0:7
RAM(r,d)- A
None
Load A with RAM pOinted
to dl reclly by r,d
33
1°0111°0111
ROM (PC'O:B,A,M) -M,A
None
Load RAM, A Indirect
19
1°001110011
BF
11011111111
ROM(PC'O:B,A,M) - 0
None
Load 0 Indirect (Note 3)
°
1
4C
10 1 ° °11 1 001
10100101011
0- RAM(B)O
None
Reset RAM Bit
2
42
43
1°1°°1°° 1 °1
101 °°1°° 11 1
0- RAM(B)2
3
4D
1°10°1 1101 1
1- RAM(B)O
None
Set RAM Bit
47
1- RAM(Bh
1- RAM(B)3
y- RAM(B)
Bd+1 -Bd
None
Store Memory Immediate
and Incremenl Bd
LID
LOID
RMB
5MB
STII
°
I
0- RAM(B)1
0- RAM(B)3
2
46
1°1°°1°1111
1° 1 0°1° 11 01
3
4B
1°1°°1 1011 1
Y
7-
1° 111 1
-6
1°°1 r 1011°1
r=0:3
RAM(B)-A
Bre r - Br
None
Exchange RAM with A,
Excluslve·OR Br with r
23
1001 °1°0111
RAM(r,d)- A
None -
Exchange A with RAM
pointed to directly by r,d
X
XAD
45
r,d
y
I
"'C
fto
o"'C
Co)
~
o
"'C
LD
I
o
o
Co)
33
--
~
1- RAM(B)2
I
dl
111 r
r=0:7
XDS
-7
1001 r 101111
r-O:3
RAM(B)-A
Bd-1-Bd
Brer-Br
Bd decrements past °
Exchange RAM with A
and Decrement Bd,
Exclusive-OR Br with r
XIS
-4
1001 r 101001
r=0:3
RAM(B)-A
Bd+1-Bd
Brer- Br
Bd Increments past 15
Exchange RAM with A
and Incremenl Bd,
Exclusive-OR Br with r
2-105
~
oo
"'C
~
~c..
Table 3. COP440 Series Instruction Set (continued)
o
~
:;
CO)
c..
oo
25
(S!;
c..
oo
l
o
~
Mnemonic Operand
o
I
oo
Machine
Language Code
(Binary)
Data Flow
Skip Conditions
Description
REGISTER REFERENCE INSTRUCTIONS
CAB
50
10101100001
A- Bd
None
Copy Ato Bd
CBA
4E
10100111101
Bd-A
None
Copy Bd to A
1001 r l(d-1)1
r -0:3,d - 0,9:15
or
r,d- B
Skip until not a LBI
Load B Immediate with r,d
(Note 6)
y':' EN3:0
None
Load lower half of EN
Immediate
LBI
r,d
-33
LEI
y
3
c..
Hex
Code
XABR
XAN
--
1°0111°0111
d
111 r
r-0:7,any d
I
I
33
10011100111
6-
y
10110 1
12
100011°0101
A-Br
None
Exchange A with Br
A - N(O,O - A3h)
None
Exchange A with N
I
33
10011100111
OB
10000110111
SKC
20
10010100001
C="1"
Skip If C Is True
SKE
21
10010100011
A=RAM(B)
Skip If A Equals RAM
SKGZ
33
10011100111
G3:0=0
Skip If G Is Zero (all 4 bits)
21
1001°100011
33
10011100111
01
10000100011
TEST INSTRUCTIONS
SKGBZ
0
SKMBZ
SKSZ
SKT
S/nt drain (11 mA max.)
Internal time-base counter for real-time processing
Internal binary counter register with MICROWIRETM
serial I/O capability
General purpose and TRI-STATE® outputs
LSTTLICMOS compatible in and out
Direct drive of LED digit and segment lines
Software/hardware compatible with other members
of COP400 family
Extended temperature range devices
COP344L1COP345L (-40°C to +85°C)
Wider supply range (4.5-9.5V) optionally available
COPS and MICROWIRE are trademarks of National Semiconductor Corp.
TRI-STATE is a registered trademark of National Semiconductor Corp.
GND
CKl
L
~,
CKD
L
TIME-SASE
COUNTER
(DIVIDE BY 10241
OJ
0,
0,
DO
t----'--r--""'-SK
1r::;:=======~I:::"" so
J.tEVELSTACK
51
I/O CONTROLS
C0P444LONLY
--,
,..........--+1
G3'
I
I
G,
G,
I
Go
I
I
5
6
1
8
121]
14
15
20109
19
IN]INZ INt INO
Figure 1. COP344L1COP34SL, COP444L/COP445L Block Diagram
2-112
MICROWIRE 1/0
()
o"C
COP444L1CO P445L
~
t
c()
Absolute Maximum Ratings
Voltage at Any Pin Relative to GND
Ambient Operating Temperature
Ambient Storage Temperature
Lead Temperature (Soldering, 10 seconds)
Power Dissipation
-0.5V to +10V
O°Cto +70°C
-65°C to +150°C
300°C
0.75 Watt at 25°C
0.4 Watt at 70°C
120mA
120mA
Total Source Current
Total Sink Current
o"C
~
~
C1I
.r
()
o"C
Absolute maximum ratings indicate limits beyond which damage
to the device may occur. DC and AC electrical specifications are
not ensured when operating the device at absolute maximum
ratings.
DC Electrical Characteristics
t
c()
o"C
O°C", TA ", +70°C, 4.5V '" Vee'" 9.5V unless otherwise noted.
Parameter
Standard Operating Voltage (Veel
CN
Conditions
Note 1
Optional Operating Voltage (Veel
CN
Min.
Max.
4.5
6.3
V
4.5
9.5
V
Units
Power Supply Ripple
peak to peak
0.5
V
Operating Supply Current
all inputs and outputs open
13
rnA
2.0
-0.3
0.4
V
V
0.7 Vee
-0.3
0.6
V
V
0.7 Vee
-0.3
0.6
V
V
Input Voltage Levels
CKI Input Levels
Crystal Input (732, 716, ';'8)
Logic High (V IH )
Logic Low (VILl
Schmitt Trigger Input (';'4)
Logie High (V IH )
Logic Low (VILl
RESET Input Levels
Logic High
Logic Low
;:;U
Schmitt trigger input
--
Inpul Level \ I eSl moae)
All Other Inputs
Logic High
Logic High
Logic Low
Logic High
Logic Low
<..v
Vee = Max.
with TTL trip level options
selected, Vee = 5V ± 5%
with high trip level options
selected
3.0
2.0
-0.3
3.6
-0.3
Input Capacitance
-1
Hi-Z Input Leakage
Output Voltage Levels
LSTTL Operation
Logic High (V OH )
Logic Low (VoLl
Vcc=5V±5%
IOH =-25}JA
IOL=0.36mA
CMOS Operation
Logic High
Logic Low
IOH =-10}JA
IOL=+10}JA
--
..
0.8
V
V
V
V
V
".~
1.2
7
pF
+1
}JA
2.7
0.4
V
V
0.2
V
V
Vee- 1
Note 1: Vee voltage change must be less than O.5V in a 1 ms period to maintain proper operation.
2-113
~
C1I
r-
COP444L1COP445L
DC Electrical Characteristics
Parameter
Output Current Levels
Output Sink Current
SO and SK Outputs {lod
J
3
g
;
~
oo
Conditions
Min.
Max.
Units
Vee = 9.5V, VOL = 0.4V
Vee = 6.3V, VOL = 0.4V
Vee = 4.5V, VOL = 0.4V
1.8
1.2
0.9
mA
mA
mA
~-L7 Outputs and Standard
GO-G 3, 00-03 Outputs {lod
Vee = 9.5V, VOL = 0.4V
Vec=6.3V, VOL=0.4V
Vee = 4.5V, VOL = 0.4V
0.8
0.5
0.4
mA
mA
mA
GO-G3 and Do-D3 Outputs with
High Current Options {lod
Vee = 9.5V, VOL = 1.0V
Vee = 6.3V, VOL = 1.0V
Vee = 4,5V, VOL = 1.0V
15
11
7.5
mA
mA
mA
GO-G3 and 0 0- D3 Outputs with
Very High Current Options {lod
Vee = 9.5V, VOL = 1.0V
Vee = 6.3V, VOL = 1.0V
Vee = 4.5V, VOL = 1.0V
30
22
15
mA
mA
mA
CKI (Single-pin RC oscillator)
CKO
Vee = 4.5V, V1H = 3.5V
Vee = 4.5V, VOL = O.4V
2
0.2
mA
mA
Vee = 9.5V, VO H = 2.0V
Vee = 6.3V, VOH = 2.0V
Vee = 4.5V, VOH = 2.0V
-140
-75
-30
Vee = 9.5V, VOH = 4.75V
Vee = 6.3V, VO H = 2.4V
Vee = 4.5V, VOH = 1.0V
-1.4
-1.4
-1.2
LED Configuration, ~-L7
Outputs, Low Current
Driver Option (lOH)
Vee = 9.5V, VOH = 2.0V
Vee = 6.0V, VOH = 2.0V
-1.5
-1.5
-18
-13
mA
mA
LED Configuration, ~-L7
Outputs, High Current
Driver Option (lOH)
Vee = 9.5V, VOH = 2.0V
Vee = 6.0V, VOH = 2.0V
-3.0
-3.0
-35
-25
mA
mA
Vee = 9.5V, V OH = 5.5V
Vee = 6.3V, VOH = 3.2V
Vee = 4.5V, VOH = 1.5V
-0.75
-0.8
-0.9
mA
mA
mA
Vee = 9.5V,
Vee = 6.3V,
Vee = 4.5V,
-1.5
-1.6
-1.8
mA
mA
mA
~
o
(continued) O°C .,; TA .,; +70°C, 4.5V .,; Vee"; 9.5V unless otherwise noted.
Output Source Current
Standard Configuration.
All Outputs (lOH)
Push-Pull Configuration
SO and SK Outputs (lOH)
TRI-STATE~
Configuration,
~- L7 Outputs, Low
Current Driver Option (loH)
TRI-STAT~
Configuration,
~-L7 Outputs, High
Current Driver Option (lOH)
Input Load Source Current
VOH = 5.5V
VOH = 3.2V
VOH = 1.5V
Vee = 5.0V, V1L = OV
-10
-800
-480
-250
J.lA
J.lA
J.lA
mA
mA
mA
-140
J.lA
3.0
mA
+2.5
J.lA
120
120
4
4
1.5
mA
mA
mA
mA
mA
120
60
60
30
1.5
mA
mA
mA
mA
mA
CKO Output
RAM Power Supply Option
Power Requirement
TRI-STATE~
VR=3.3V
Output Leakage
-2.5
Current
Total Sink Current Allowed
All Outputs Combined
0, G P~rts
L7-l,j
L3-~
All Other Pins
Total Source Current Allowed
All 1/0 Combined
L7-l,j
4-~
Each L Pin
All Other Pins
2-114
COP344L1COP345L
Absolute Maximum Ratings
-0.5V to +10V
-40°C to +85°C
-65°C to +150°C
300°C
0.75 Watt at 25°C
0.25 Watt at 85°C
120mA
120mA
Voltage at Any Pin Relative to GND
Ambient Operating Temperature
Ambient Storage Temperature
Lead Temperature (Soldering, 10 seconds)
Power Dissipation
Total Source Current
Total Sink Current
Absolute maximum ratings indicate limits beyond which damage
to the device may occur. DC and A C electrical specifications are
not ensured when operating the device at absolute maximum
ratings.
DC Electrical Characteristics
-40°C" TA
Parameter
Standard Operating Voltage (Vecl
"
+85°C, 4.5V" Vee" 7.5V unless otherwise noted.
Conditions
Note 1
Optional Operating Voltage (Vecl
Min.
Max.
Units
4.5
5.5
V
4.5
7.5
V
Power Supply Ripple
peak to peak
0.5
V
Operating Supply Current
all inputs and outputs open
15
mA
2.2
-0.3
0.3
V
V
0.7 Vee
-0.3
0.4
V
V
Input Voltage Levels
CKI Input Levels
Crystal Input
Logic High (VIH)
Logic Low (VILl
Schmitt Trigger Input
Logic High (VIH)
Logic Low (VILl
RESET Input Levels
Logic High
Schmitt Trigger Input
Lnnir. I nw
SO Input Level (Test mode)
V
0.7Vee
-n "l
nA
\I
2.2
2.5
V
All Other Inputs
Logic High
Logic High
Logic Low
Vee = Max.
with TTL trip level options
selected, Vee = 5V ± 5%
3.0
2.2
-0.3
0.6
V
V
V
Logic High
Logic Low
with high trip level options
selected
3.6
-0.3
1.2
V
V
7
pF
+2
"A
Input Capacitance
-2
Hi·Z Input Leakage
Output Voltage Levels
LSTTL Operation
Logic High (Vo H)
Logic Low (VoLl
Vee=5V±5%
10H =-20"A
IOL=0.36mA
CMOS Operation
Logic High
Logic Low
IOH=-10"A
IOL=+10"A
0.4
V
V
0.2
V
V
2.7
Vee- 1
Note 1: Vee voltage change must be less than O.5V In alms period to maintain proper operation.
2-115
I
I
COP344L1COP345L
DC Electrical Characteristics
Parameter
Output Current Levels
Output Sink Current
SO· and SK Outputs (loll
(continued) -40·C .. TA" +85·C, 4.5V .. Vee" 7.5V unless otherwise noted.
Conditions
Min.
Max.
Units
Vee = 7.5V, VOL = O.4V
Vee = 5.5V, VOL = O.4V
Vee = 4.5V, VOL = 0.4V
1.4
1.0
0.8
mA
mA
mA
Vee = 7.5V, VOL = 0.4V
Vee = 5.5V, VOL = 0.4V
Vee = 4.5V, VOL = 0.4V
0.6
0.5
0.4
mA
mA
mA
Vec = 7.5V, VOL = 1.0V
Vee = 5.5V, VOL = 1.0V
Vee = 4.5V, VOL = 1.0V
12
9
7
mA
mA
mA
Very High Current Options (loll
Vee = 7.5V, VOL = 1.0V
Vee = 5.5V, VOL = 1.0V
Vee = 4.5V, VOL = 1.0V
24
18
14
mA
mA
mA
CKI (Single·pin RC OSCillator)
CKO
Vee = 4.5V, VIH = 3.5V
Vee = 4.5V, VOL = 0.4V
2
0.2
mA
mA
Vec = 7.5V, VOH = 2.0V
Vee = 5.5V, VO H = 2.0V
Vec = 4.5V, VO H = 2.0V
-100
-55
-28
Push·Pull Configuration
SO and SK Outputs (lOH)
Vee =7.5V, VOH = 3.75V
Vee = 5.5V, VOH = 2.0V
Vec = 4.5V, VOH = 1.0V
-0.85
-1.1
-1.2
LED Configuration, lQ-L7
Outputs, Low Current
Driver Option (lOH)
Vee = 7.5V,
Vee = 6.0V,
Vee = 5.5V,
VO H = 2.0V
VOH = 2.0V
VOH = 2.0V
LED Configuration, lQ-L7
Outputs, High Current
Driver Option (IOH)
lQ- L7 Outputs, and Standard
Go- G3, 00- 03 Outputs (loll
Go-G 3 and 0 0-03 Outputs with
High Current Options (loll
GO-G 3 and 00-03 Outputs with
Output Source Current
Standard Configuration,
All Outputs (IOH)
-900
-600
-350
"A
"A
"A
mA
mA
mA
-1.4
-1.4
-0.7
-27
-17
-15
mA
mA
mA
Vee = 7.5V, VO H = 2.0V
Vee = 6.0V, VOH = 2.0V
Vee = 5.5V, VOH = 2.0V
-2.7
-2.7
-1.4
-54
-34
-30
mA
mA
mA
TRI·STATE® Configuration,
lQ-L7 Outputs, Low
Current Driver Option (lOH)
Vee = 7.5V, VOH = 4.0V
Vee = 5.5V, VOH = 2.7V
Vee = 4.5V, VOH = 1.5V
-0.7
-0.6
-0.9
mA
mA
mA
TRI·STATE® Configuration,
lQ- L7 Outputs, High
Current Driver Option (I OH )
Vee = 7.5V, VOH = 4.0V
Vee = 5.5V, VO H = 2.7V
Vee = 4.5V, VOH = 1.5V
-1.4
-1.2
-1.8
mA
mA
mA
Input Load Source Current
Vee = 5.0V, V1L = OV
-10
CKO Output
RAM Power Supply Option
Power Requirement
VR=3.3V
TRI·STATE® Output Leakage
Current
-5
Total Sink Current Allowed
All Outputs Combined
0, G Ports
L7-L4
L3- Lo
All Other Pins
Total Source Current Allowed
All 1/0 Combined
L7- L4
L3-lQ
Each L Pin
All Other Pins
2-116
-200
"A
4.0
mA
+5
"A
120
120
4
4
1.5
mA
mA
mA
mA
mA
120
60
60
30
1.5
mA
mA
mA
mA
mA
I
I
o
o'tJ
AC Electrical Characteristics
t
COP444L1445L: O°C" TA " 70°C, 4.5V " Vee" 9.5V unless otherwise noted.
COP344L1345L: -40°C" TA" +85°C, 4.5V" Vee" 7.5V unless otherwise noted.
Parameter
Conditions
Instruction Cycle Time CKI
Input Frequency -
te
II
Duty Cycle
Rise Time
Fall Time
CKI Using RC (+4)
+32 mode
+16 mode
+8 mode
+4 mode
Min.
Max.
Units
15
40
,..s
0.8
0.4
0.2
0.1
30
2.1
1.0
0.5
0.26
60
120
80
MHz
MHz
MHz
MHz
%
ns
ns
28
,..s
11=2MHz
R=56kQ±5%
C=100pF±10%
Instruction Cycle Time
15
CKO as SYNC Input
400
tSYNe
ns
INPUTS:
IN3-INQ, G3- GQ, L7 -Lo
tSETuP
tHOLD
51
tSETUP
tHOLD
OUTPUT PROPAGATION DELAY
8.0
1.3
,..s
,..S
2.0
1.0
,..s
,..s
4.0
,..S
5.6
,..S
Test condition:
CL=50pF, RL=20kQ, VouT=1.5V
SO, SK Outputs
tpdl, tpdQ
All Other Outputs
tpdl, tpdQ
2-117
~
o'tJ
~
.r
o
o'tJ
Co)
:t
~
o'tJ
~
r-
....I
~c..
oo
::J
GNO
~
28
27
26
25
24
23
CK'
CKI
REm
c..
17
16
l5
l4
INI
IN2
oo
...i
~
Vee
LJ
12
L1
o
~
COP444LI
CDP344l
10
"12
13
14
22
21
20
19
18
17
16
15
DO
01
D2
OJ
OJ
GNO
CK'
CK!
imTI
17
16
l5
l4
G1
GI
GO
IN'
INO
o
)
Vee
SK
LJ
12
so
LI
10
"
12
CDP445L/
COP345L
DO
"
D2
OJ
OJ
G2
~
GI
GO
SK
so
51
LD
51
LD
Order Number COP444UN, COP344UN
NS Package N28A
io
,
24
23
22
21
20
19
18
17
16
15
14
13
Order Number COP445L1N, COP345UN
NS Package N24A
Figure 2. Connection Diagrams
Pin
Description
Pin
Description
L7 -4J
8 bidirectional I/O ports with
TRI-STATE@
SK
Logic-controlled clock (or general
purpose output)
G3 -G O
4 bidirectional I/O ports
CKI
System oscillator input
4 general purpose outputs
CKO
System oscillator output (or general
purpose input, RAM power supply, or
SYNC input)
03- 0 0
IN3 - INo
4 general purpose inputs (COP444L only)
SI
Serial inp~t (or counter input)
RESET
System reset input
SO
Serial output (or general purpose output)
Vce
GNO
Ground
Power supply
Figure 3. Input/Output Timing Diagrams (Crystal Divide·by·16 Model
-II-two
CKI
--I
CKO
(INPUT)
I-- twl
\
j
1- 'SYNC
'-_ _ _--'~-----_
Figure 3a. Synchronization Timing
2-118
o
o"0
Functional Description
A block diagram of the COP444L Is given in Figure 1.
Data paths are illustrated in simplified form to depict
how the various logic elements communicate with
each other in implementing the instruction set of the
device. Positive logic is used. When a bit Is set, it is a
logic "1" (greater thim 2 volts). When a bit is reset, it
is a logic "0" (less than 0.8 volts).
also serves to control the SK output. C can be out·
putted directly to SK or can enable SK to be a sync
clock each instruction cycle time. (See XAS instruction and EN register description, below.)
Four general·purpose inputs, IN3-INo, are provided.
The D register provides 4 general·purpose outputs
and is used as the destination register for the 4-bit
contents of Bd. The D outputs can be directly connected to the digits of a multiplexed LED display.
All functional references to the COP444L1COP445L
also apply to the COP344L1COP345L.
Program Memory
The G register contents are outputs to 4 generalpurpose bidirectional I/O ports. G I/O ports can be
directly connected to the digits of a multiplexed LED
display.
Program Memory consists of a 2048 byte ROM. As
can be seen by an examination of the COP444L1445L
instruction set, these words may be program instruc. tions, program data or ROM addressing data. Because
of the special characteristics associated with the JP,
JSRP, JID, and LaID instructions, ROM must often be
thought of as being organized into 32 pages of 64
words each.
The a register is an internal, latched, 8·bit register,
used to hold data loaded to or from M and A, as well
as 8-bit data from ROM. Its contents are output to the
L 110 ports when the L drivers are enabled under
program control. (See LEI instruction.)
ROM addressing is accomplished by a 11-bit PC register. Its binary value selects one of the 2048 8-bit words
contained in ROM. A new address is loaded into the
PC register during each instruction cycle. Unless the
instruction is a transfer of control instruction, the PC
register is loaded with the next sequential 11-blt binary
count value. Three levels of subroutine nesting are
implemented by the 11-bit subroutine save registers,
SA, SB, and SC, providing a last-in, first-out (LIFO)
hardware subroutine stack.
The 8 L drivers,when enabled, output the contents of
latched a data to the L I/O ports. Also, the contents
of L may be read directly into A and M. L 1/0 ports can
be directly connected to the segments of a multiplexed
LED display (using the LED Direct Drive output configuration option) with a data being outputted to the
Sa-Sg and decimal point segments of the display.
The SIO register functions as a 4·bit serial-in/serialout shift register or as a binary counter depending on
the contents of the EN register. (See EN register
description, below.) Its contents can be exchanged
with A, allowing it to input or output a continuous
serial data stream. SIO may also be used to provide
additional parallel I/O by connecting SO to external
serial-in/parallel-out shift registers.
ROM instruction words are fetched, decoded and
executed by the Instruction Decode, Control and Skip
Logic circuitry.
Data Memory
Data memory consists of a 512-blt RAM, organized as
The XAS instruction copies C into theSKL latch. In the
8 nata rAni!'ltAr!'l nf 16 4-hit ninit!'l. RAM andrA!'l!'linn i!'l
l,;UUllLtU IIIUU'=', \:11"\ I:; Llltf OULIJUL UI "1"\1-, III Lilt:;; O)IIIIL
implemented by a 7·bit B register whose upper 3 bits
(Br) select 1 of 8 data registers and lower 4 bits (Bd)
select 1 of 16 4-bit digits in the selected data register.
While the 4-bit contents of the selected RAM digit (M)
is usually loaded into or from, or exchanged with, the
A register (accumulator), it may also be loaded into
or from the a latches or loaded from the L ports. RAM
addressing may also be performed directly by the
LDD and XAD instructions based upon.the 7-bit contents of the operand field of these instructions. The
Bd register also serves as a source register for 4-bit
data sent directly to the D outputs.
register mode, SK outputs SKL ANDed with the
clock.
The EN register is an internal 4-bit register loaded
under program control by the LEI instruction. The
state of each bit of this register selects or deselects
the particular feature associated with each bit of the
EN register (EN3-ENo). \
Internal Logic
The 4·bit A register (accumulator) is the source and
destination register for most 1/0, arithmetic, logic
and data memory access operations. It can also be
used to load the Br and Bd portions of the B register,
to load and input 4 bits of the 8-bit a latch data, to
input 4 bits of the 8-bit L I/O port data and to perform
data exchanges with the SIO register.
A 4-bit adder performs the arithmetic and logic func· .
tions, storing its results in A. It also outputs a carry
bit to the 1-bit C register, most often employed to
indicate arithmetic overflow. The C register, in con·
junction with the XAS instruction and the EN register,
2-119
1. The least significant bit of the enable register,
ENo, selects the SIO register as either a 4-bit shift
register or a 4-bit binary counter. With ENo set, SIO
is an asynchronous binary counter, decrementing
its value by one upon each low-going pulse ("1" to
"0") ocurring on the SI input. Each pulse must be
at least two instruction cycles wide. SK outputs
the value of SKL. The SO output is equal to the
value of EN3. With ENo reset, SIO is a serial shift
register shifting left each instruction cycle time.·
The data present at SI goes into the least significant bit of SIO. SO can be enabled to output the
most significant bit of SIO each cycle time. (See 4
below.) The SK output becomes a logic-controlled
clock.
2. With EN, set the IN, input is enabled as an interrupt input. Immediately following an interrupt, EN,
is reset to disable further interrupts.
:t
~
o"0
,J:Io
t
U1
.r
o
o
"0
t
~
o
"0
~r-
EN3 enables SO as the output of the SIO shift regis·
ter, outputting serial shifted data each instruction
time. Resetting EN3 with the serial shift register
option selected disables SO as the shift register
output; data continues to be shifted through SIO
and can be exchanged with A via an XAS instruction but SO remains reset to "0". The table below
provides a summary of the modes associated with
EN3 and ENo.
3. With EN2 set, the L drivers are enabled to output
the data in Q to the L I/O ports. Resetting EN2
disables the L drivers, placing the L I/O ports in a
high·impedance input state.
4. EN3, in conjunction with ENo, affects the SO out·
put. With ENo set (binary counter option selected)
SO will output the value loaded into EN3. With ENo
reset (serial shift register option selected), setting
J
~
Il.
oo
Enable Register Modes -
Bits EN3 and ENO
EN3
ENo
510
51
SO
0
0
Shift Register
Input to Shift Register
0
5K
If SKL= 1, SK = CLOCK
:J
If SKL = 0, SK = 0
i
1
o
0
0
.Shift Register
Input to Shift Register
Serial Out
Il.
o
If SKL = 1, SK = CLOCK
If SKL = 0, SK = 0
1
Binary Counter
Input to Binary Counter
0
If SKL = 1, SK = 1
If SKL = 0, SK = 0
1
1
Binary Counter
1
Input to Binary Counter
If SKL = 1, SK = 1
If SKL = 0, SK = 0
Interrupt
"pop" the stack and return program control to the
instruction following the original ASC. At this
time, the skip logic is enabled and skips this
instruction because of the previous ASC carry.
Subroutines and LQID instructions should not be
nested within the interrupt service routine, since
their popping the stack will enable any previously
saved main program skips, interfering with the
orderly execution of the interrupt routine.
d. The first instruction of the interrupt routine at hex
address OFF must be a Nap.
The following features are associated with the IN,
interrupt procedure and protocol and must be consi·
dered by the programmer when utilizing interrupts.
a. The interrupt, once acknowledged as explained
below, pushes the next sequential program counter
address (PC + 1) onto the stack, pushing in turn the
contents of the other subroutine·save registers to
the next lower .level (PC + 1 ~ SA'~ SB ~ SC). Any
previous contents of SC are lost. The program
counter is set to hex address OFF (the last word of
page 3) and EN, is reset.
e. A LEI instruction can be put immediately before
the RET to re-enable interrupts.
b. An interrupt will be acknowledged only after the
following conditions are met:
1 . EN, has been set.
2. A low·going pulse ("1" to "0") at least two
instruction cycles wide occurs on the IN, input.
3. A currently executing instruction has been
completed.
4. All successive transfer of control instructions
and successive LBls have been completed (e.g.,
if the main program is executing a JP instruction which transfers program control to another
JP instruction, the interrupt will not be acknow·
ledged until the second JP instruction has been
executed.
Initialization
The Reset Logic will initialize (clear) the device upon
power-up if the power supply rise time is less than
1 ms and greater than 11's. If the power supply rise
time is greater than 1 ms, the user use provide an
external RC network and diode to the RESET pin as
shown below. If the RC network is not used, the
RESET pin must be pulled up to Vec either by the internalload or by an external resistor (;;'40kQ) to Vee. The
RESET pin is configured as a Schmit! trigger input.
Initialization will occur whenever a logic "0" is
applied to the RESET input, provided it stays low for
at least three instruction cycle times.
c. Upon acknowledgement of an interrupt, the skip
logic status is saved and later restored upon
popping of the stack. For example, if an interrupt
occurs during the execution of ASC (Add witl)
Carry, Skip on Carry) instruction which results in
carry, the skip logic status is saved and program
control is transferred to the interrupt servicing
routine at hex address OFF. At the end of the
interrupt routine, a RET instruction is executed to
iP'-~-i---""
Vee
s
u
f!ESff
P
P
L
y
GNO
RC> 5xPDWERSUPPL'( RISE TIME (R;:'4Dk)
Power·Up Clear Circuit
2-120
I
!
I
I
o
Upon initialization, the PC register is cleared to 0 (ROM
address 0) and the A, B, C, D, EN, and G registers are
cleared. The SK output is enabled as a SYNC output,
providing a pulse each instruction cycle time. Data
Memory (RAM) is not cleared upon initialization. The
first instruction at address 0 must be a CLRA.
c. RC Controlled Oscillator. CKI is configured as a
single pin RC controlled Schmitt trigger oscillator.
The instruction cycle equals the oscillation fre·
quency divided by 4. CKO is available as the RAM
power supply (V R) or as a general purpose input.
d. Externally Synchronized Oscillator. Intended for
use in multi·COP systems, CKO is programmed to
function as an input connected to the SK output of
another COP chip operating at the same frequency
(COP chip with Lor C suffix) with CKI connected
as shown. In this configuration, the SK output con·
nected to CKO must provide a SYNC (instruction
cycle) signal to CKO, thereby allowing synchronous
data transfer between the COPs using only the SI
and SO serial 110 pins in conjunction with the XAS
instruction. Note that on power·up SK is automati·
cally enabled as a SYNC output. (See Functional
Description, Initialization, above.)
Oscillator
There are four basic clock oscillator configurations
available as shown by Figure 4.
a. Crystal Controlled Oscillator. CKI and CKO are
connected to an external crystal. The instruction
cycle time equals the crystal frequency divided by
32 (optional by 16 or 8).
b. External Oscillator. CKI is an external clock input
signal. The external frequency is divided by 32
(optional by 16 or 8) to give the instruction cycle
time. CKO is now available to be used as the RAM
power supply (V R), as a general purpose input, or
as a SYNC input.
R2
RI
t
t
.J1..j
EXTERNAL
CLOCK
*
_..J
1_ ...
CKO
CKO
-=
t
a
o
"tI
~
r
o
o
"tI
t
co
o"tI
~
r-
CKO
0
~
:t
Co)
ISYNC)
CKI
o"tI
VCC
IVR OR GENERAL
PURPOSE INPUT
PIN)
COP444l/445l
SI
~~_ _ _ _ _S~II~~SO_ _ _ _ _ _ _ _~
IVR OR GENERAL
PURPOSE INPUT
OR SYNC PIN)
RC Controlled Oscillator
Crystal Oscillator
Crystal
Value
R1 (Q)
R2 (Q)
C1 (pF)
C2(pF)
R(kQ)
C (pF)
Instruction
Cycle Time
(j.Is)
455kHz
2.097 MHz
4.7k
1k
1M
1M
220
30
220.
6-36
51
82
100
56
19±15%
19±.13%
Component Values
Note: 200 kQ ;;. R ;;. 25 kQ
360pF;;. C;;' 50pF
Figure 4. COP444L1445L Oscillator
2-121
...J
~
11.
o
(J
::J
3
CO)
11.
o(J
...r
;
11.
o
It)
g
CKO Pin Options
In a crystal controlled oscillator system, CKO is used
as an output to the crystal network. As an option
CKO can be a SYNC input as described above. As
another option CKO can be a general purpose input,
read into bit 2 of A (accumulator) upon execution of
an INIL instruction. As another option, CKO can be a
RAM power supply pin (VR), allowing its connection
to a standby/backup power supply to maintain the
integrity of RAM data with minimum power drain
when the main supply is inoperative or shut down to
conserve power. Using either option is appropriate in
applications where the COP444L1445L system timing
configuration does not require use of the CKO pin.
COP444U445L outputs have the following optional
configurations, illustrated in Figure 5:
o
a. Standard - an enhancement mode device to
ground in conjunction with a depletion-mode device
to Vcc , compatible with LSTTL and CMOS input
requirements. Available on SO, SK, and all D and
G outputs.
~
h. An on-chip depletion load device to Vee.
I. A Hi-Z input which must be driven to a "1" or "0"
by external components.
The above input and output configurations share common enhancement-mode and depletion-mode devices.
Specifically, all configurations use one or more of six
devices (numbered 1-6, respectively). Minimum and
maximum current (lOUT and VOUT curves are given in
Figure 6 for each of these devices to allow the designer
to effectively use these I/O configurations in designing
a system.
1/0 Options
"II:t
(J
COP444L1COP445L inputs have the following optional
configurations:
The SO, SKoutputs can be configured as shown in a."
b_, or c. The D and G outputs can be configured as
shown in a_ or b. Note that when inputting data to the
G ports, the G outputs should be set to "1." The L
outputs can be configured as in d., e., I. or g_
An important pOint to remember if using configuration d. or f. with the L drivers is that even when the L
drivers are disabled, the depletion load device will
source a small amount of current (see Figure 6, device
2); however, when the L-lines are used as inputs, the
disabled depletion device can not be relied on to
source sufficient current to pull an input to logic "1".
b. Open-Drain - an enhancement-mode device to
ground only, allowing external pull-up as required
by the user's application_ Available on SO, SK, and
all D and G outputs.
c_ Push-Pull An enhancement-mode device to
ground in conjunction with a depletion-mode device
paralleled by an enhancement-mode device to Vee.
This configuration has been provided to allow for
fast rise and fall times when driving capacitive
loads_ Available on SO and SK outputs only_
RAM Keep-Alive Option
Selecting CKO as the RAM power supply (VR) allows
the user to shut off the chip power supply (Ved and,
maintain data in the lower four (Sr =0,1,2,3) registers
of RAM. To insure that RAM data integrity is
maintained, the following conditions must be met:
d_ Standard L - same as a_, but may be disabled.
Available on L outputs only_
e_ Open Drain L - same as b_, but may be disabled.
Available on L outputs only.
1. RESET must go low before Vee goes low during
power off; Vee must go high before RESET goes
high on power-up.
2. VR must be within the operating range of the chip,
and equal to Vee ± 1 V during normal operation.
3. VR must be ~ 3.3V with Vee off.
f. LED Direct Drive - an enhancement-mode device
to ground and to Vee, meeting the typical current
sourci ng requirements of the segments of an LED
display. The sourcing device is clamped to limit
current flow. These devices may be turned off
under program control (See Functional Description, EN Register), placing the outputs in a highimpedance state to provide required LED segment
blanking for a multiplexed display. Available on L
outputs only.
g_ TRI-STATE@ Push-Pull - an enhancement-mode
device to ground and Vee. These outputs are TRISTATE outputs, allowing for connection of these
outputs to a data bus shared by other bus drivers.
Available on L outputs only.
COP445L
If the COP444L is bonded as a 24-pin device, it becomes the COP445L, illustrated in Figure 2, COP444L1
445L Connection Diagrams. Note that the COP445L
does not contain the four general purpose IN inputs
(IN3-INo). Use of this option precludes, of course, use
of the IN options and the interrupt feature, which uses
IN 1 . All other options are available for the COP445L.
2-122
a. Standard Output
c. Push· Pull Output
b. Open· Drain Output
DISABLE~~
(... ,S DEPLETION DEVICE)
f. LED (L Output)
e. Open· Drain L Output
d. Standard L Output
VCC
r-H~
#6
''""'~f
g. TRI·STATE'" Push· Pull (L Output)
INPUT
0-----1 {"
i. Hi·Z Input
h. Input with Load
Figure 5. Output Configurations
Input Current for La through L7
when Output Programmed Off
by Software
Current for Inputs with Load
Device
-1000
-100
1 1 1 1 1
1 1 1 1 1
-90
-BO
-70
j
:3
~
c
~
I-
=>
E'
-60
-50
Source Current for Standard
Output Configuration
I\.. IMAX
"
1\.1
@ Vee =
DEVICE d #Z
AND f #Z
DEVICE, #Z
AN~ d #Z
-900
-BOO
9.5V
1 1 1
""
....
E'
-40
-30
1
'\
-700
'\
-600
1
'-
h ... vl@\I,.,.::al;V
-500
-400
-300
-200
k:h'l'o.:+-+
-100 I::-¥-+"T'~o..:.!:~
O~L-~~~~~~
1.0 Z.O 3.0 4.0 5.0 6.0 7.0 B.O
9.5
o
2.0
VOH (VOLTS)
V,N (VOLTS)
1.5 r-Tr-r-1rr-.-...-.,--r""",,,,,,,,..,
Source Current for Lo through
L7 in TRI·STATE" Configura·
tion (Low Current Option)
Source Current for La through
L7 in TRI·STATE" Configura·
tion (High Current Option)
Source Current for SO and SK
in Push· Pull Configuration
1.5
1.5
IMlx~
V~r.9.5V
IMAX@
1.0
HIHHl--f--I-+i-='i-t-r-H
0.5
r
1.0
~~L
~
IMIN
VCC =9.SV
IMIN@
VCC=9.5V
1.0
IMAX@!r
IMAX@
VCC=4.SV
FI
0.5
I~c=nv
0.5
IMIN~
IMIN@
o
1
3
4
5
6
VOH(VOLTS)
__~~
1
7
8 9 10
DEVICE e#2
AND #3
o
l1lT
1
3
4
S
,
5
2-123
~1lr5r
DEVICE
9#5
6
VOH(VOLTS)
7
8
9 10
J
o
1
3
4
S
DEVICE
9#5
6
VOH(VDLTS)
7
8
9 10
...I
II)
"'It
C")
D..
LED Output Direct Segment
Drive
.
High Current Options on Lo·L 7
Very High Current Options on
on 0 0.0 3 or GO·G3
0
0
::.
"'It
LED Output Source Current
(for High Current LED Option)
LED Output Source Current
(for Low Current LED Option)
"'It
C")
D..
-50
OEVICE f #2 AND #4
A~D DEV1ICE. OR b #1
0
-40
JII)
-3D
0
"'It
"'It
D..
IMAX
ONE SEGEMENT O~
:<
:<
.5
.5
!:
!:
..IV
:r
:r
-20
........V
0
0
.....
-10
.......
...... .......
:J
....
"'It
"'It
"'It
D..
4
6
7
B'
9
",/
KAXEIGHT .. _
~.....
SEGMENTS ON
•
IMIN
I
1
10
10
VOH (VOLTS)
VOH (VOLTS)
0
5
:-
VCC (VOLTS)
0
LED Output Direct Segment
Drive
-50
VOH=2.0V
Output Sink Current for Lo·L 7
and Standard Drive Option for
0 0.0 3 and GO·G3
.
Output Sink Current for SO
and SK
4~-rr---~--r-~r--'
4·ITT'"TT--r--=--..,....~
OEVICE f
#2 ANO #4
-40
:<
-3~
r- ~M~rO~IGH CURRENT
-
.5
:r
!:
-20
-10
.'.'
.'.'
.'
........
....
.... ......
/t:Jw
OPTION
~
CURRENT
-
/ r " " ' N HIGH
.CURijENT O~ION
r-~MIN LOW
CU'RRENT OPTION
I
-
10
VCC (VOLTS)
.YOL(YOLTS)
YOL(YOLTS)
Output Sink Current
Go·G 3 and 0 0.03 with Very
High Current Option
Output Sink Current for Go·G 3
and 0 0.0 3 (for High Current
Option)
= __...,
«
§
120 ,...,-r-r:-~---r--r-...
120
100 H+-I+-+--b"'+-+-
100 I-+++-+--+-+-+-t-l-t---i
60 I-hlt---'l-+-t--t-I-+-+-+--l
«
§
'--"-IT""""--'-r...,.-~----"
DEYICE a#1
AND b#1
60~t-~-+--t-i-~~~~~·
9
9
o
1
2 3
4
5
6
7
8
2··3·456
9 10
YoL(YOLTS)
YoL(YOLTS)
figure Sa. COP444UCOP445L'lnput/Output Characteristics
2-124
8
9 10
o
Input Current for LO- L7
when Output Programmed
Off by Software
Input Current INo -IN3
-2 50
-2 Oll, ........
"-
~-1 50
3
z
= -1 00
"- r----
j\
IMIN @
VCC~7.5V
0
«
r---~----'----------'
-100
f--'I.----+--+--t---i
-1.0
-80 f-'...--''<-t---t---j---i
-0.8
OEVICE d #2
ANO f #2
*
-60f--~~-+--t_---i
1\
!? -40
-20
_\
~
'"
-0.2
.:::::
o
o
1.5
VIN (VOLTS)
VI/O (VOLTSI
Source Current for SO
and SK in Push·Pull
Configuration
1.5
"-
- "-::z...,.,
-
IMIN @
Vvcc ~4.5V
MIN
/' NVCC
~@
7.5V
~
~
1
VOH (VOLTS)
Source Current for LO- L7
in TRI·STATE® Configura·
tion (High Current Option)
1.5 "rr---r...........---r..-;;0"'EV"'IC"'E'""'C...,#"'2
AND #3
1"'-
"-
Source Current for LO- L7
in TRI·STATE® Configura·
tion (Low Current Option)
1.5 ,-...----,--,,-,rr-"'-;;;OE"'V"'lc"'"E-:-g#""'5"'
OEVICE g#5
t
U1
r
o
o"'tJ
(,)
t
a
o
"'tJ
~
U1
....
f-+--+-I-HH---+t-+--+--l
«E
1.0
1.0
1M IN @
VCC~4.5V
~
o
OL-.l....-.....L..:~...._=:;",,.;:,,....J
o
;;r:
IMIN@
r-- t-i IMAX@
I
~cCK51
o
I
IMAX @
IMIN@
E
VCC~7.5V
I
0.5
0.5
~
--
T(r
VCC~7.5V
I
0.5
0
LED Output Source
Current (for High Current
LED Option)
LED Output Source
Current (for Low Current
LED Option)
I
0
VOH(VOLTS)
VOH(VOLTS)
3
4
VOH(VOLTS)
Output Sink Current for
SO and SK
-
-30r-,-~--.-.-~--.--r-,
OL-__.l.-_ _- ' -_ _- ' -_ _........_ _- - '
o
VOH (VOLTSI
VOH (VOLTS)
Output Sink Current for
Lo - L7 and Standard Drive
Option for Do - D3 and Go - G3
Output Sink Current GO-G3
and Do- D3 with Very High
Current Option
2
3
VOL(VOLTS)
Output Sink Current for
Go - G3 and Do - 03 (for
High Current Option)
12°r-'-rr-'--r-'-~~r-,
4r-rrr--'r-~~-'---'
100
80
«
E 60 f+j-l--+---j"'-
~
40
H+-t-I4-+--+-l--l--+-l
20
/t-;/'1;>'-,-
OL-.__.l.-_ _- ' -_ _- ' -_ _........_ _- - '
o
VOLIVOLTS)
t-'="
co
o"'tJ
IMAX @
VCC=7.5V
-0.6 ~MAX @
VCC ~ 4.5V
-0.4
0.5
1.0
jE
~
=>
\
OEVICE a, #2
and d *2
;,
3
IMAX @ ~
"- N.~C
=45V
IMIN @
VCCt 4·r V
50
IMAX @
VCC ~ 7.5V
-U:'
-120
0iVIC, h H6
.......
o"'tJ
Source Current for
Standard Output
Configuration
VOL(VOLTS)
Figure 6b. COP444UCOP445L Input/Output Characteristics
2-125
VOL(VOLTSI
COP444L1COP445L1COP344L1COP345L Instruction Set
Table 1 is a symbol table providing internal architecture,
instruction operand and operational symbols used in
Jhe instruction set table.
Table 2 provides the mnemonic, operand, machine code,
data flow, skip conditions, and description associated
with each instruction in the COP444L1COP445L instruction set.
Table 1. COP444L1445L1344L1345L Instruction Table Symbols
Symbol
Jit)
3D..
o
~
!
D..
oo
Definition
Symbol
Definition
INTERNAL ARCHITECTURE SYMBOLS
INSTRUCTION OPERAND SYMBOLS
A
d
4-bit Operand Field, 0-15 binary (RAM Digit
Select)
r
3-bit Operand Field, 0- 7 binary (RAM Register
Select)
a
11-bit Operand Field, 0-2047 binary (ROM
Address)
y
4-bit Operand Field, 0-15 binary (Immediate
Data)
B
Br
Bd
C
D
EN
G
IL
IN
L
M
PC
Q
SA
SB
SC
SIO
SK
4-bit Accumulator
7-bit RAM Address Register
Upper 3 bits of B (register address)
Lower 4 bits of B (digit address)
1-bit Carry Register
4-bit Data Output Port
4-bit Enable Register
4-bit Register to latch data for G 1/0 Port
Two 1-bit latches associated with the IN3 or
INo inputs
4-bit Input Port
8-bit TRI-STATE® 1/0 Port
4-bit contents of RAM Memory pointed to by
B Register
11-bit ROM Address Register (program
counter)
8-bit Register to latch data for L 1/0 Port
11-bit Subroutine Save Register A
11-bit Subroutine Save Register B
11-bit Subroutine Save Register C
4-bit Shift Register and Counter
Logic-Controlled Clock Output
RAM(s) Contents of RAM location addressed by s
ROM(t) Contents of ROM location addressed by t
OPERATIONAL SYMBOLS
+
Plus
....
Replaces
=
Is equal to
A
The one's complement of A
e
:
Exclusive-OR
-
2-126
Minus
Is exchanged with
Range of values
(")
o""D
Table 2. COP444L1445L Instruction Set
Mnemonic Operand
Hex
Code
Machine
Language Code
(Binary)
Data Flow
0I:loo
0I:loo
0I:loo
Description
Skip Conditions
ARITHMETIC INSTRUCTIONS
c:
o""D
(")
t
1001 11 0000 1
A+C+RAM(B}- A
Carry - C
Carry
Add with Carry, Skip on
Carry
31
10011100011
A+ RAM(B} - A
None
Add RAM to A
ADT
4A
101 0011 01 01
A+ 1010 - A
None
Add Ten to A
AISC
5-
10101 1
A+y - A
Carry
Add Immediate, Skip on
Carry (y" O)
CASC
10
1°°011°°°°1
A+RAM(B}+C- A
Carry - C
Carry
Complement and Add with
Carry, Skip on Carry
CLRA
00
10 ° ° 010 0001
0- A
None
Clear A
0I:loo
COMP
40
101 °°1°°°°1
A-A
None
Ones complement of A to A
r-
NOP
44
101001°10°1
None
None
No Operation
RC
32
10 ° 1 11° 01 01
"0" - C
None
Reset C
SC
22
1001 01° 01 01
"1"- C
None
Set C
XOR
02
100001°01 °1
A
None
Exclusive·OR RAM with A
ASC
30
ADD
Y
y
I
C1I
r
(")
o""D
(0)
0I:loo
0I:loo
c:
(")
o""D
(0)
C1I
ill
RAM(B) - A
TRANSFER OF CONTROL INSTRUCTIONS
JID
JMP
JP
a
a
Jump Indirect (Note 3)
FF
1111 111 1 1 11
ROM (PC10:8, A,M) - PC7:0 None
6-
1011 °IOla10:81
a - PC
None
Jump
--
I
a6:0
111
I
(pages 2,3 only)
a - PC6:0
None
Jump within Page (Note 4)
11 11 a5:0 I
(all other pages)
a - PC5:0
PC + 1 - SA - SB - SC
00010 - PC10:6
a - PC5:0
None
Jump to Subroutine Page
(Note 5)
PC + 1 - SA - SB - SC
a - PC
None
Jump to Subroutine
None
Return from Subroutine
Always Skip on Return
Return from Subroutine
then Skip
--
a7:0
I
_.
JSRP
a
JSR
a
11 °1
6-
a5:0
1011°11IalO:81
I
a7:0
I
RET
48
101001100°1
sc -
RETSK
49
1°10°1 1001 1
SC - SB - SA - PC
SB - SA - PC
2-127
-
Table 2. COP444U445L Instruction Sei (continued)
Mnemo.nlc Operand
Hex
Code
Mllchl.ne
Language Code
(Binary)
Data Flow
Skip Conditions
Description
MEMORY REFERENCE INSTRUCTIONS
CAMO
,
...i
3a..
§
ia..
oo
COMA
LD
r
LDD
r,d
LaiD
RMB
5MB
°
1
33
10011100111
3C
10011J11ool
A - 07:4
RAM(B) - 03:0
None
Copy A, RAM to a
07:4 - RAM (B)
03:0 - A
None
Copy a to RAM, A
33
1°°111°0111
2C
1° 01 °111 001
-5
1001 r 1° 101 1
(r=0:3)
RAM(B)- A
Brl!! r- Br
None
Load RAM into A,
Exclusive·OR Br with r
RAM(r,d)- A
None
Load A with RAM pointed
to directly by r,d
23
10 ° 1 010 ° 1 11
--
101 r
I
BF
J1011J11111
ROM(PC1O:8.A,M) - a
SB- SC
None
Load a Indirect (Note 3)
4C
1° 1 °°111 001
0- RAM(B)O
None
Reset RAM Bit
45
1°10°1° 1 011
0- RAM(B)1
None
Set RAM Bit
Store Memory Immediate
and Increment Bd
d
I
2
42
1° 1 0°1° ° 1 01
0- RAM(B)2
3
43
1° 1 °°1°° 111
0- RAM(B)3
°
1
40
101 °°111 01 1
1 -. RAM(B)O
47
1°1°°1 1101 1
1 - RAM(BI1
·2
46
1°10°1° 11 °1
1 - RAM(B)2
3
4B
10 1 ° 0p ° 1 11
1 .• RAM(B)3
STII
Y
7-
1° 111 1
I
y- RAM(B)
Bd+1-Bd
None
X
r
-6
1001 r 1011°1
(r=0:3)
RAM(B)- A
Brl!! r- Br
None
1° 01 °1°° 111
d
I
RAM(r,d)- A
None
XAD
r,d
23
--
y
Exchange RAM with A,
Exclusive-OR Br with r
Exchange A with RAM
pointed to directly by r,d
111 r I
XDS
r
-7
1001 r 1° 111 1
(r-0:3)
RAM(B)- A
Bd-1-Bd
Brl!! r- Br
Bd decrements past °
Exchange RAM with A
and Decrement Bd,
Exclusive-OR Br with r
XIS
r
-4
1001 riO 1 001
(r = 0:3)
RAM(B)- A
Bd+1-Bd
Brl!! r- Br
Bd increments past 15
Exchange RAM with A
and Increment Bd,
Exclusive-OR Br with r
REGISTER REFERENCE INSTRUCTIONS
CAB
50
1°1011000°1
A- Bd
None
Copy A to Bd
CBA
4E
1° 1 ° 0P11 01
Bd - A
None
Copy Bd to A
1001 r l(d-1)1
(r = 0:3;
d =0. 9:15)
or
r,d - B
Skip until not a LBI
Load B Immediate with r,d
(Noie 6)
LBI
r,d
-33
-LEI
XABR
y
33
,
1°°111°0111
PI r I d I
(any r, any d)
-
1°°111°0011
1° 11 °1 y I
y- EN
None
Load EN Immediate (Note 7)
612
1°0011001 °1
A-Br(0-A3)
None
Exchange A with Br
2-128
o
o""D
Table 2. COP444U445L Instruction Set (continued)
.110
t
c
Machine
Hex
Code
Lan~uage Code
SKC
20
10 a 1 010 a a a
C
= "1"
Skip if C is True
SKE
21
10 a 1 010 a a 1
A
= RAM(B)
Skip if A Equals RAM
SKGZ
33
10 01 110 a 11
G3:0
21
10 a 1 010 a 01
Mnemonic
Operand
Data Flow
Binary)
Description
Skip Conditions
TEST INSTRUCTIONS
SKGBZ
SKMBZ
33
10 01 110 a l l
a
01
10 a a 010 a 01
1
11
10 a a 110 a 01
2
03
10 a a 010 01 1
3
13
10 a a 110 a 1 1
a
01
10 a a 010 a a 1
1
11
10 a a 110 a 01
2
03
10 a a 010 a 1 1
3
13
1000110011
41
10 10 010 a 01
SKT
=a
Skip if G is Zero
(all 4 bits)
Skip if G Bit is Zero
1st byte
Go
Gl
2nd byte
G2
1
G3
=0
=a
=a
=a
IN IN
INIL
33
10 a 1 110 a 1 11
2A
10 a 1 all 01 01
=a
RAM(B)1 = a
RAM(B)2 = a
RAM(BI3 = a
Skip if RAM Bit is Zero
A time·base counter
carry has occurred
since last test
Skip on Timer
(Note 3)
G-A
None
Input G Ports to A
IN- A
None
Input IN Inputs to A
(Note 2)
1l3, CKO,"O", ILa - A
None
Input I L Latches to A
(Note 3)
10 01 110 0111
28
100 10110001
33
10011100111
29
10010110011
2E
1001 011 1 101
L3:0 - A
33
10 01 1100111
3E
100"1"'01
33
II"IIL
OBD
OGI
Y
5OMG
XAS
..
1__ .. ,
Bd - D
None
Output Bd to 0 Outputs
100"100111
y
10 10 '1
y-G
None
Output to G Ports
Immediate
RAM(B)- G
None
Output RAM to G Ports
A -
None
Exchange A with SIO
(Note 3)
IV U
I
'IV v
-"
I
II
L.f.4
.. -.
II,",I"I\~I
I
33
10 a 1 110 0111
3A
10011110101
4F
10'0011"'1
SIO, C - SKL
I
0 ............
+.... OJ\I\oA A
Nole 1: All subscripts for alphabetical symbols Indicate bit numbers unless explicitly defined (e.g., Br and Bd are explicitly defined). Bits are numbered 0 to
N where 0 signifies the least significant bit (Iow-order, rlght·most bit). For example, A31ndicates the most significant (Ieft'most) bit of the 4·blt A register.
Nole 2: The IN IN instruction Is not available on the 24'pln COP445L or COP345L since these devices do
n.at contain the IN Inputs.
Nole 3: For additional information on the operation of the XAS, JID, LQID, INIL, and SKT Instructions, see below.
Nole 4: The JP instruction allows a jump, while in subroutine pages 2 or 3, to any ROM location within the two·page boundary of pages 2 or 3. The J P
instruction, otherwise, permits a jump to a ROM location within the current 54-word page. JP may not jump to the last word of a page.
Nole 5: A JSRP transfers program control to subroutine page 2 (0010 Is loaded Into the upper 4 bits of Pl. A JSRP may not be used when In pages 2 or 3.
JSRP may not jump to the last word in page 2.
Nole 6: LBlls a slngle'Qyte Instruction If d = 0,9,10,11,12; 13, 14, or 15. The machine code for the lower 4 bits equals the binary value of the "d" data
minus 1, e.g., to load the lower four bits of B (Bd) with the value 9 (100121, the lower 4 bits of the LBllnstruction equal 8 (10002)' To load 0, the lower 4 bits of
the LBI instruction should equal 15 (11112).
Nole 7: Machine code for operand field y for LEI instruction should equal the binary value to be latched Into EN, where a "I" or "0" in each bit of EN
corresponds with the selection or deselection of a particular function associated with each bit. (See Functional Description, EN Register.)
2-129
~
r
o
0,
""D
!
~
""D
RAM(B)O
33
o""D
o
INPUT/OUTPUT INSTRUCTIONS
ING
-
o
~
r-
.....
~
C-
The following information is provided to assist the
user in understanding the operation of several unique
instructions and to provide notes useful to program·
mers in writing COP444L1445L programs.
::J
XAS Instruction
en
oo
~
C-
O
o
.J'
~
C-
O
o
::J
3
C-
oo
COP444l
ININ
1
INo/lNa
XAS (Exchange A with SIO) exchanges the 4·bit con·
tents of the accumulator with the 4·bit contents of
the SIO register. The contents of SIO will contain
serial-in/serial·out shift register or binary counter
data, depending on the value of the EN register. An
XAS instruction will also affect the SK output. (See
Functional Description, EN Register, above.) If SIO is
selected as a shift register, an XAS instruction must
be performed once every 4 instruction cycles to
effect a continuous data stream.
INll
Figure 7. INIL Hardware Implementation
value of PC to continue sequential program execu·
tion. Since LaiD pushes SB - SC, the previous
contents of SC are lost. Also, when LaiD pops the
stack, the previously pushed contents of SB are left
in SC. The net result is that the contents of SB are
placed in SC (SB - SC). Note that LaiD takes two
instructiun cycle times to execute.
JID Instruction
JID (Jump Indirect) is an indirect addressing instruc·
tion, transferring program control to a new ROM
location pOinted to indirectly by A and M. It loads the
lower a bits of the ROM address register PC with the
contents of ROM addressed by the 11·bit word,
PC'O:8, A, M. PC,o, PCg and PCa are not affected by
this instruction.
SKT Instruction
The SKT (Skip On Timer} instruction tests the state of
an internal 10·bit time·base counter. This counter
divides the instruction cycle clock frequency by 1024
and provides a latched indication of counter over·
flow. The SKT instruction tests this latch, executing
the next program instruction if the latch is not ·set. If
the latch has been set since the previous test, the
next program instruction is skipped and the latch is
reset. The features associated with this instruction,
therefore, allow the COP444L1445L to generate its
own time·base for real·time processing rather than
relying on an external input signal.
Note that JID requires 2 instruction cycles to execute.
INIL Instruction
INIL (Input IL Latches to A) inputs 2 latches, IL3 and
ILa (see Figure 7) and CKO into A. The IL3 and ILa
latches are set if a low'going pulse ("1" to "0") has
occurred on the IN3 and INo inputs since the last INIL
instruction, provided the input pulse stays low for at
least two instruction times. Execution of an INIL
inputs IL3 and ILa into A3 and AO respectively, and
- resets these latches to allow them to respond to sub·
sequent low·going pulses on the IN3 and INo lines. If
CKO Is mask programmed as a general purpose
input, an INIL will input the state of CKO into A2. If
CKO has not been so programmed, a "1" will be
placed in A2. A "0" is always placed in A1 upon the
execution of an INIL. The general ·purpose Inputs
IN3-INo are input to A upon execution of an ININ
instruction. (See Table 2, ININ instruction.) INIL is
useful in recognizing pulses of short duration or
pulses which occur too often to be read conveniently
by an IN IN instruction.
For example, using a 2.097 MHz crystal as the time·
base to the clock generator, the instruction cycle
clock frequency will be 65kHz (crystal frequency -+- 32)
and the binary counter output pulse frequency will be
64Hz. For time·of·day or similar real·time processing,
the SKT instruction can call a routine which incre·
ments a "seconds" counter every 64 ticks.
Instruction Set Notes
a. The first word of a COP444L1445L program (ROM
address 0) must be a CLRA (Clear A) instruction.
b. Although skipped instructions are not executed,
one instruction cycle time is devoted to skipping
each byte of the skipped instruction. Thus all
program paths except JID and LaiD take the same
number of cycle times whether instructions are
skipped or executed. JID and LaiD instructions
take 2 cycles if executed and 1 cycle if skipped.
Note: IL latches are not cleared on reset; IL3 and ILa
not input on 445L
LQID Instruction
LaiD (Load a Indirect) loads the a·bit a register with
the contents of ROM pointed to by the 11·bit word
PC1O, PCg, PCa, A, M. LaiD can be used for table
lookup or code conversion such·as BCD to seven·
segment. The Lal D instruction "pushes" the stack
(PC + 1 -+ SA - SB -SC) and replaces the least signi·
ficant a bits of PC as follows: A - PC7 :4 , RAM (B) PC3:0 , leaving PC,o, PCg and PCa unchanged. The
ROM data pointed to by the new address is fetched
and loaded into the a latches. Next, the stack is
"popped" (SC - SB - SA -PC), restoring the saved
c. The ROM is organized into 32 pages of 64 words
each. The Program Counter is an 11·bit binary
counter, and will count through page boundaries. If
a JP, JSRP, J.ID or LaiD instruction is located in the
last word of a page, the instruction operates as if
it were in the next page. For example: a JP located
in the last work of a page will jump to a location in
the next page. Also,-a LaiD or JID located in the
last word of page 3, 7,11,15,19,23, or 27 will access
data in the next group of four pages.
2-130
(')
o"'tI
Option List
The COP444L1445L mask-programmable options are
assigned numbers which correspond with the COP444L
pins_
Option 16: SI Input
same as Option 9
Option
= 0:
= 1:
= 2:
The following is a list of COP444Loptions_ When specifying a COP445L chip, Options 9, 10, 19, and 20 must all be
set to zero_ The options are programmed at the same
time as the ROM pattern to provide the user with the
hardware flexibility to interface to various 110 components using little or no external circuitry_
Option 1 = 0: Ground Pin -
Option 18: SK Driver
same as Option 17
no options available
Option 2: CKO Output
= 0: clock generator output to crystal/resonator
(0 not allowable value if option 3 = 3)
= 1: pin is RAM power supply (V R) input
= 2: general purpose input, load device to Vee
= 3: general purpose input, Hi-Z
= 4: multi-COP SYNC input (CKI+ 32, CKI+16)
= 5: multi-COP SYNC input (CKI+ 8)
Option
= 0:
= 1:
=2:
= 3:
= 4:
3: CKI Input
oscillator input divided by 32 (2 MHz max_)
oscillator input divided by 16 (1 MHz max.)
oscillator input divided by 8 (500kHz max.)
single-pin RC controlled oscillator divided by 4
oscillator input divided by 4 (Schmitt)
21: Go 110 Port
very-high current standard output
very-high current open-drain output
high current standard output
high current open-drain output
standard LSTTL output (fanout = 1)
open-drain LSTTL output (fanout = 1)
Option 25: D3 Output
same as Option 21
Option 26: D2 Output
same as Option 21
Option 27: D1 Output
same as Option 21
Option 28: Do Output
~':lrT'l.o !l~
(",\1"'\+1,," ')1
Option 29: L Input Levels
= 0: standard TTL input levels
("0" = 0.8V, "1" = 2.0V)
= 1: higher voltage input levels
("0" = 1.2V, "1" = 3.6V)
Option 8: L4 Driver
same as Option 5
Option 9: IN1 Input
= 0: load device to Vee
= 1: Hi-Z input
Option 30: IN Input Levels
same as Option 29
Option 31: G Input Levels
same as Option 29
Option 10: IN2 Input
same as Option 9
Option 32: SI Input Levels
same as Option 29
Option 11: Vee pin
=0: 4.5V to 6.3V operation
=1: 4.5V to 9.5V operation
Option 12: L3 Driver
same as Option 5
Option
= 0:
= 1:
= 2:
Option 13: L2 Driver
same as Option 5
Option 34: CKO Input Levels (CKO= input; Option 2=2,3)
same as Option 29
Option 14: L1 Driver
same as Option 5
Option
= 0:
= 1:
= 2:
Option 15: La Driver
same as Option 5
2-131
c.n
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Co)
Option 24: G3 110 Port
same as Option 21
Option 7: Ls Driver
same as Option 5
./:10
./:10
Option 20: IN3 Input
same as Option 9
Option 23: G2 110 Port
same as Option 21
Option 6: La Driver
same as uptlon 0
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Option 22: G1 110 Port
same as Option 21
5: L7 Driver
Standard output
Open-drain output'
High current LED direct segment drive output
High current TRI-STATE@ push-pull output
Low-current LED direct segment drive output
Low-current TRI-STATE@ push-pull output
c:
(')
Option 19: INa Input
same as Option 9
Option
= 0:
= 1:
= 2:
= 3:
= 4:
= 5:
Option 4: RESET Input
= 0: load device to Vee
= 1: Hi-Z input
Option
= 0:
= 1:
= 2:
= 3:
= 4:
= 5:
17: SO Driver
standard output
open-drain output
push-pull output
./:10
./:10
./:10
33: RESET Input
Schmitt trigger input
standard TTL input levels
higher voltage input levels
35 COP Bonding
COP444L (28-pin device)
COP445L (24-pin device)
both 28- and 24-pin versions
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./:10
c:
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./:10
c.n
.-
...I
~
D.
o
~
~
COP444L Evaluation (See COP Note 4)
TEST MODE (Non·Standard Operation)
. The SO output has been configured to provide for
standard test procedures for the custom·program·
med COP444L. With SO forced to logic "1," two test
modes are provided, depending upon the value of 51: ,
D.
a. RAM and Internal Logic Test Mode (51 = 1)
b. ROM Test Mode (51 0)
...i
These special test modes should not be employed by
the user; they are Intended for manufacturing test
only.
D.
APPLICATION #1: COP444L General Controller
:J
Figure 8 shows an interconnect diagram for a COP444L
used as a general controller. Operation of the system
is as follows:
oo
Lt)
:
oo
!
D.
o
o
The 444L·EVAL is a pre·programmed COP444L, con·
taining several routines which facilitate user famil·
iarization and evaluation of the COP444L operating
characteristics. It may be used as an up/down counter
or timer, Interfacing to any combination of (1) an LED
digit or lamps, (2) 4·digit LED Display Controller, (3) a
4·diglt VF Display Controller, and/or (4) a 4·diglt LCD
Display Controller, alternatively, it may be used as a
simple music synthesizer.
=
Sample Circuits
1. By making only the oscillator, power supply and
"L7" connections, (Fig. 9) an approximate 1 Hz
square wave will be produced at output"D1." This
output may be observed with an oscilloscope, or
connected to additional TIL or CMOS circuitry.
1. The L7-Lo outputs are configured as LED Direct
Drive outputs, allowing direct connection to the
segments of the display.
2. The Da- Do outputs drive the digits of the multi·
plexed display directly and scan the columns of
the 4 x 4 keyboard matrix.
3. The INa-INo inputs are used to input the 4 rows of
the keyboard matrix. Reading the IN lines In
conjunction with the current value of the 0
outputs allows detection, debouncing, and decod·
Ing of anyone of the 16 keyswitches.
4. CKI is configured as a single·pin oscillator input
allowing system timing to be controlled by a
slngle·pin RC network. CKO is therefore available
for use as a general·purpose input.
5. 51 is selected as the input to a binary counter
input. With 510 used as a binary counter, SO and
SK can be used as general purpose outputs.'
6. The 4 bidirectional G I/O ports (Ga-Go) are avail·
able for use as required by the user's application.
7. Normal reset operation Is selected.
2. By making the indicated connections to a small
LED digit (NSA1541A, NSA1166, or equiv. -larger
digits will be proportionately dimmer), the counter
actions may be observed. Place the "up/down"
switch in the "up" (open) position and apply a TIL·
compatible signal at the "counter·input." PlaCing
the "up/down" switch In the "down" (closed)
position causes the count to decrement on each
high·to·low input transition.
3. AI14 digits of the counter may be displayed by
connecting a standard display controller (COP470
for VF,' COP472 for LCD, MM5450 for LED) as
.
shown In Figure 9.
Any combination of the Single LED digit and
display controllers may be used simultaneously,
and will display the same data.
4. The Simple counter described above becomes a
timer when the 1 Hz output is connected to the
"counter input." Up or down counting may be used
with input frequencies up to 1kHz. Improved timing
accuracies may be obtained by substituting the
L0I-"'"'iI'1!='!I'I""_""
L'I--""'''-''''.......,
4·DlGIT
LED DISPLAY
Vee
RESET
COP444L •
00
"
"
'3
'K'
INo
,.,
IN,
IN3
Figure 8. COP444L KeyboardlDlsplay Interface
2-132
4,4
KEYSWITCH
MATRIX
o
2.097MHz crystal oscillator circuit of Figure 4a for
the RC network shown in Figure g, or by connecting
a more stable external frequency to the "counter
input" in place of the 1Hz signal.
followed by "Store;" the tune will be played for
immediate audition. Subsequent depression of
"Play" and "Store" will replay the last stored
tune.
5. An "entertaining" use of the 444L-EVAL is as a
simple music synthesizer (or electronic organ). 8y
attaching a simple switch matrix (or keyboard), a
speaker or piezo-ceramic transducer, and grounding "L7", the user can play "music" (Figure 10).
Three modes of operation are available: Playa
note, play one of four stored tunes, or record a
tune for subsequent replay.
Note: The accuracy of the tones produced is a function of the oscillator accuracy and stability; the
crystal oscillator is recommended.
Vee
00
OSCILLATOR
I
I
I
Vee
OKI
CKO
I I
Twelve keys, representing the 12 notes in one
octave, are labeled "C" through "8"; depressing a key causes a square wave of the corresponding frequency to be outputted to the
speaker. Depressing "LShift" or "UShift" causes
the next note to be shifted to the next lower
octave (one-half frequency) or the next upper
octave (double frequency), respectively.
r--
(0)
G'
E
C
I--
INO
11'
A
F
C'
I--
IN'
111
A'
F'
0
f--
INI
,
,
G
O'
-
IN3
PLAY
STORE
SPKfl
Any combination of notes and rests up to a total
of 48 may be stored in RAM for later replay. To
store a note, press the appropriate note key, followed by the duration of the note (¥a-note, 'I.-note,
'/,-note, whole (1)-note, followed by "Store;" a rest
is stored by selecting the duration and pressing
"Store." When the tune is complete, press "Play"
"'tJ
t
c
o
o
444L·EVAl
l
SHIFT
~
r-
en
U
SHIFT - $ I
~ ~]~."
GNO
17
GO
-4- -4-
TRANSDUCER
Figure 9. Counter/Timer
b
4-0IGtTLEO
DISPLAY
(2EA NSNS84)
$I
UP
INI
i---vZ;-i
I
I
I
I
I
I
I
I
I
I
I
4HL-EVAL
01
f - -.....-+-+-..,
so f--+-~~-l
ffES"El
I
:*
I
GNO
..
·OISPLAYVOLTAGE
I
L ____ .J
L2
L3
l4
L5
L6
CLK
s,
s~
s,
O
03
Vee
c. Record Tune
oowr
S-
"'tJ
Depressing "Play" followed by "y,", "'I.", "'/,", or
"1" will cause one of 4 stored tunes to be
played.
ItJPUl
o"'tJ
ten
o
'/8
b. Play Stored Tune
COUNTH
t
co
02
01
a. Play A Note
o"tI
CON70
s~
S,
SI
s~
~+-4-~~-+-4~--+---~a
lEO DIGIT
INSA11650AEQUIV.)
··SEE "INITIALIZATION
Vee
VCG
Figure 10. Music Synthesizer
2-133
4-0IGITVF
OISPLAY
rFUTABA4-LT-51Aj
FILAMENTS
~
c.. ~National
PRELIMINARY
oo
D Semiconductor
ic..
COP464 and COP484 Single-Chip 3k and 4k
oo Microcontrollers (COP464/COP465, COP364/COP365
and COP484/COP485, COP384/COP385)
General Description
Features
The COP464, COP465, COP484 and COP485 Single-Chip
Microcontrollers are members of the COPSTM family,
fabricated using National's XMOS-II technology. These
microcontrollers contain all system timing, internal logic,
ROM, RAM and I/O necessary to implement dedicated
control functions in a variety of applications. Features
include single supply operation, various output configuration options, and an instruction set, internal architecture
and I/O scheme designed to facilitate keyboard input, display output and data manipulation. The COP464/465 have
3k of on-chip ROM and 192 digits of RAM, the COP484/485
have 4k of ROM and 256 digits of RAM. The COP464 and
COP484 are 28-pin chips. The COP465 and COP485 are
24-pin versions (four inputs removed). The COP364/365
and COP384/385 are functional equivalents of the above
devices, but operate with an extended temperature range
(-40°C to +85°C). Standard test procedures and reliable
high-density fabrication techniques provide the mediumto-large volume customers with a customized microcontroller at a low end-product cost. These microcontrollers are appropriate choices In many demanding control
environments, especially those with human interface.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
COPS and MICAOWIRE are trademarks of National Semiconductor Corp.
TRI·STATE is a registered trademark of National Semiconductor Corp_
Low cost
Powerful instruction set
4k x 8 ROM, 256 x 4 RAM (COP484/485)
3k x 8 ROM, 192 x 4 RAM (COP464/465)
23 I/O lines (COP464 and COP484)
True vectored interrupt, plus restart
Four-level subrou·tine stack
4"s execution time
Single supply operation (4.5V-6.3V)
Low current drain (14mA at 25·C)
Standby current 2mA at 3.3V (Keep entire RAM
alive.)
Time-base counter for real-time processing
Internal binary counter/register with MICROWIRETMcompatible serial 1/0
.
General purpose and TRI-STATE'" outputs
TTL/CMOS-compatible in and out
LED drive capability
Software/hardware compatible with other members
of COP400 family
Extended temperature range devices COP364/365
and COP384/385 (-40·C to 85·C)
=
GND
~,
TIME·BASE
COUNTER
(DIVIDE 8Y 1024!
D3
D2
D,
DD
"
"
so MICROWIRElIO
SKI
"
4-LEVELSTACK
ON 28·PlNONLV
,...---......
'3·
D2
'1
DO
5
6
1
8
12131415
20111 9
19
LN)IN2 INI INO
Figure 1. COP484/COP485 Block Diagram
2-134
(')
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~National
I\)
~
~ Semiconductor
~
(')
COP2440/COP2441/COP2442 and
CO P2340/CO P2341 ICO P2342
Single-Chip Dual CPU Microcontrollers
o"tI
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~
~
( ')
o
General Description
Features
The COP2440, COP2441, COP2442, COP2340, COP2341,
and COP2342 Single-Chip Dual CPU Microcontrollers
are members of the COPSTM family, fabricated using
N-channel, silicon gate MOS technology. These microcontrollers contain two identical CPUs with all system
timing, internal logic, ROM, RAM, and 1/0 necessary to
implement dedicated control functions in a variety of
applications. Features include single supply operation,
various output configuration options, and an instruction
set, internal architecture, and 1/0 scheme designed to
facilitate keyboard input, display output, and data manipulation. The COP2440 is a 40-pin chip and the COP2441
is a 28-pin version of the same circuit (12 1/0 lines removed). The COP2442 is a 24-pin version (4 more input
lines removed). The COP2340, COP2341, COP2342 are
functional equivalents of the above devices respectively,
but operate with an extended temperature range (-40'C
to +85'C). Standard test procedures and reliable highdensity fabrication techniques provide the medium to
large volume customers with a customized dual CPU
microcontroller at a low end-product cost.
• Two independent processors
• Dual CPU simplifies task partitioning-easy to
program
• Enhanced, more powerful instruction set
• 2kx8 ROM, 160x4 RAM
• 35 1/0 lines (COP2440)
• Zero-crossing detect circuitry with hysteresis
• True multi-vectored interrupt from 4 selectable
sources (pi us restart)
• Four-level subroutine stack for each processor (in
RAM)
• 4,..s execution time per processor (non-overlapping)
• Single supply operation (4.5V-6.3V)
• Programmable time-base counter for real-time processing
• Internal' binary counterlregister with MICROWIRETMcompatible serial 1/0
• General purpose and TRI-STATE® outputs
• TTL/CMOS-compatible in and out
• LED drive capability
• MICROBUS-compatible
• Softwarelhardware compatible with other members
of the COP400 family
• Extended temperature range devices COP2340,
COP2341. COP2342 {-40'r. In "-il'i'r.\
These microcontrollers are appropriate choices in many
demanding control environments, especially those with
human interface. Further, the high throughput and
MICROBUSTM 1/0 facilitate numerous machine interface
applications. The two CPUs provide the ability to handle
two simultaneous but totallv indeoendent real timp.
events on one chip.
coPS,
• Compatible single-processor device available
(COP440 series)
MICROBUS, and MICROWIRE are trademarks of National Semiconductor Corp.
TAl-STATE is a registered trademark of National Semiconductor Corp.
MEMORY
2048x 8 ROM
16Dx4 RAM
SI~Lr---.,
SO
SK
Vee
GND
110
L
PORT
G
PORT
0
PORT
IN
PORT
Figure 1. COP2440 Architecture
2-135
R
PORT
H
PORT
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~
~
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o
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.....
(5
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CO P2440/CO P2441 ICO P2442
Absolute Maximum Ratings
Voltage at Zero-Crossing Detect Pin
Relative to GND
Voltage at Any Other Pin Relative to GN 0
Ambient Operating Temperature
Ambient Storage Temperature
Lead Temperature (Soldering, 10 seconds)
Power Dissipation
-1.2Vto +15V
-0.5Vto +7V
O'Cto +70'C
-65'Cto +150'C
300'C
0.75 Watt at 25'C
0.4 Watt at 70'C
150mA
75mA
Total Source Current
Total Sink Current
Absolute maximum ratings Indicate limits beyond which damage
to the device may occur. DC and AC electrical specifications are
not ensured when operating the device at absolute maximum
ratings.
DC Electrical Characteristics
O·C" TA" + 70'C, 4.5V .. Vee" 6.3V unless otherwise noted.
Conditions
Parameter
Min.
Units
Operating Voltage (Vecl
Note 3
6.3
V
Power Supply Ripple
(peak to peak)
0.4
V
Operating Supply Current
(All Inputs and outputs open)
TA=O'C
TA=25'C
TA=70'C
41
35
27
mA
mA
mA
2.5
2.0
-0.3
0.4
V
V
V
0.7Vee
-0.3
0.6
V
V
0.7Vee
-0.3
0.6
V
V
Input Voltage ~evels
CKI Input Levels
Crystal Input (+16, +8)
Logic High (VIH)
Logic High (VIH)
Logic Low (VIIJ
Schmitt Trigger Input (+4)
Logic High (VIH)
Logic Low (VIU
RESET Input Levels
Logic High
Logic Low
Zero-Crossing Detect Input
Trip Point
logic High (VIH) Limit
Logic Low (VIU Limit
SO Input Level (Test Mode)
All Other Inputs
Logic High
Logic High
Logic Low
4.5
Max.
Vee=Max.
Vee=5V±5%
. (Schmitt Trigger Input)
See Figure 9
-0.15
2.5
V
V
V
V
2.5
2.0
-0.3
0.8
V
V
V
3.6
-0.3
1.2
V
V
7.0
pF
-1.0
+1.0
".A
-0.8
2.0
Vee = Max.
Vee=5V±5%
Input Levels High Trip Option
Logic High
Logic Low
Input Capacitance
Hi·Z Input Leakage
2-136
0.15
12
I
o
COP2440/COP2441/COP2442
DC Electrical Characteristics
Parameter
Output Voltage Levels
Standard Output
TTL Operation
Logic High (VoH )
Logic Low (Vou
CMOS Operation
Logic High (VOH )
Logic Low (Vou
Output Current Levels
Standard Output Source Current
LED Direct Drive Output
Logic High (IOH)
TRI·STATE® Output Leakage Current
CKO Output
Oscillator Output Option
Logic High
Logic Low
VA RAM Power Supply Option
Supply current
CKI Sink Current (RC Option)
Input Current Levels
Zero·Crossing Detect Input
Resistance
Input Load Source Current
o"'CI
(Cont'd)
Min.
Conditions
Max.
Units
o"'CI
IOH = -100,..A
10L= 1.6rnA
2.4
IOH = -10,..A
IOL=10,..A
Vee -0.4
Vee = 4.5V, VOH = 2.4V
Vee=6V
VOH=2V
0.4
V
V
0.2
V
V
-100
-650
,..A
-2.5
-2.5
-17
+2.5
rnA
,..A
VoH =2V
VOL = O.4V
~
VA =3.3V
V1H = 3.5V, Vee = 4.5V
V1H = 1.0V
V1H = 2.0V, Vee = 4.5V
-0.2.
0.4
rnA
rnA
3.0
2.0
Total Sink Current Allowed
All 1/0 Combined
Each L, R Port
Each D, G, H Port
SO,SK
75
20
10
2.5
mA
mA
rnA
mA
Total Source Current Allowed
All 1/0 Combined
150
,--
mA
70
70
23
1.6
mA
rnA
mA
mA
..
Lr L4
L3- LO
Each L Pin
All Other Output Pins
2-137
1.5
14
rnA
rnA
kQ
,..A
n_~
I\)
~
:::
oo
"'CI
~o
o"'CI
I\)
Co)
~
4.6
230
I
~
o
S2
o
o"'CI
I\)
~
o
o
"'CI
I\)
~
N
oo:t
C")
N
D..
o
S:2
~
N
D..
o
~
C")
N
D..
o
o
g
oo
-~
D..
COP2340/COP2341/COP2342
Absolute Maximum Ratings
Voltage at Zero-Crossing Detect Pin
Relative to GND
Voltage at Any Other Pin Relative to GND
Ambient Operating Temperature
Ambient Storage Temperature
Lead Temperature (Soldering, 10 seconds)
Power Dissipation
-1.2Vto +15V
-0.5Vto +7V
-40'C to +85'C
-65·C to + 150'C
300'C
0.75 Watt at 25'C
0.25 Watt at .85·C
150mA
75mA
Total Source Current
Total Sink Current
Absolute maximum ratings Indicate /lmlts beyond which
damage to the device may occur. DC and AC electrical specifications are not ensured when operating. the device at absolute
maximum ratings.
DC Electrical Characteristics
-40'C" TA " +85'C, 4.5V " Vcc " 5.5V unless otherwise noted.
Parameter
Conditions
Mln_
Max_
Units
4.5
Operating Voltage (Vcel
Note 3
5.5
V
N
Power Supply Ripple
(peak to peak)
0.4
V
o
Operating Supply Current
(All inputs and outputs open)
TA = -40,'C
TA=25°C
TA=85°C
54
35
25
mA
mA
mA
2.2
-0.3
0.3
V
V
0.7Vcc
-0.3
0.4
V
V
0.7Vcc
-0.3
0.4
V
V
D..
!
N
D..
oo
Input Voltage Levels
CKI Input Levels
Crystal Input (+16, +8)
Logic High (V1H)
Logic Low (VII)
Schmitt Trigger Input (+4)
Logic High (V1H)
Logic Low (VII)
RESET Input'Levels
Logic High
Logic Low
Zero-Crossing Detect Input
Trip Point
Logic High (VIH) Limit
Logic Low (VIL) Limit
(Schmitt Trigger Input)
See figure 9
-0.15
0.15
12
V
V
V
-0.8
SO Input level (Test Mode)
All Other Inputs
Logic High
Logic Low
2.2
2.4
V
2.2
-0.3
0.6
V
V
Input Levels High Trip Option
Logic High
Logic Low
3.6
-0.3
1.2
V
V
7.0
pF
+2.0
,..A
Input CapaCitance
-2.0
Hi-Z Input Leakage
2-138
DC Electrical Characteristics
Parameter
Output Voltage Levels
Standard Output
TTL Operation
Logic High (VOH)
Logic Low (VoLl
CMOS Operation
Logic High (Vo H)
Logic Low (VoLl
Output Current Levels
Standard Output Source Current
LED Direct Drive Output
Logic High (IOH)
TRI·STATE'" Output Leakage Current
CKO Output
Oscillator Output Option
Logic High
Logic Low
VA RAM Power Supply Option
Supply current
CKI Sink Current (RC Option)
Input Current Levels
Zero·Crossing Detect Input
Resistance
Input Load Source Current
(Cont'd)
Conditions
Min.
Max.
Units
0.4
V
V
0.2
V
V
-100
-BOO
",A
-1.5
-5.0
-15
+5.0
rnA
",A
IOH= -100fJA
IOL= 1.6 rnA
2.4
IOH= -10",A
IOL = 10fJA
Vee- 0.5
Vee = 4.5V, VO H = 2.4V
Vee = 5V (Note 4)
VOH=2V
-0.2
0.4
VoH =2V
VOL = O.4V
mA
mA
4.0
VA = 3.3V
Vee = 4.5V, V1H = 3.5V
2.0
VIH = 1.0V
VIH = 2.0V, Vee = 4.5V
1.4
14
rnA
rnA
4.6
280
",A
Total Sink Current Allowed
All 1/0 Combined
Each L, R Port
Each 0, G, H Port
SO,SK
75
20
10
2.5
rnA
rnA
rnA
rnA
Total Source Current Allowed
All 1/0 Combined
L Port
Lr L4
150
120
70
rnA
rnA
rnA
-~
"-~-~
kQ
_A
rnA
rnA
Each L Pin
All Other Output Pins
2-139
AC· Electrical Characteristics
COP2440/COP2441/COP2442: o·c .. TA" + 70·C, 4.5V .. Vee" 6.3V unless otherwise noted.
COP2340/COP2341/COP2442: -4Q·C .. TA .. +85°C, 4.5V .. Vee" 5.5V unless otherwise noted.
Conditions
Parameter
Instruction Execution Time -
tE
CKI Frequency
Duty Cycle (Note 1)
Rise Time
Fall Time
CKI Using RC (Figure 11C)
Frequency
Instruction Execution Time -tE
CKO
tpd1, tpdQ
tpd1, tpdQ
SO,SK
t pd1, tpdQ
All Other Outputs
MICROBUSTM TIMING
Read Operation (Figure 6)
Chip Select Stable Before RD-tesR
Chip Select Hold Time for RD-tRes
RD Pulse Width-tRR
Data Delay from RD-tRO
RD to Data Floating-toF
Max.
Units
Each Processor (Figure 3)
4.0
10
lAs
+16 mode
+8 mode
+4 mode
fl=4MHz
fl = 4 M Hz external clock
fl = 4 MHz external clock
1.6
0.8
0.4
30
4.0
2.0
1.0
60
60
40
MHz
MHz
MHz
%
ns
ns
0.5
4.0
1.0
8.0
MHz
lAs
+4 mode
R=15kQ:t5%, C=100pF:t10% .
INPUTS: (Figure 3)
SI
tSETUP
tHOLO
All Other Inputs
tSETUP
tHOLO
OUTPUT PROPAGATION DELAY
Min.
0.3
300
ns
1.7
300
lAs
ns
/AS
Test ConditIon:
C L =50pF, VOUT= 1.5V
Crystal Input
Schmitt Trigger Input
O.H
0.3,
lAs
lAs
RL=2.4kQ
RL =5.0kQ
1.0
1.4
lAs
lAs
375
250
ns
ns
ns
ns
ns
700
ns
ns
ns
ns
ns
ns
CL = 100 pF, Vee = 5V:t 5%
TRI·STATEIll outputs
65
20
400
Write Operation (Figure 7)
Chip Select Stable Before WR-tesw
Chip Select Hold Time for WR-twes
WR Pulse Width-tww
Data Set·Up Time for WR-tow
Data Hold Time for WR-two
INTR Transition Time from WR-twi
65
20
400
320
100
=
Note 1: Duty Cycle tWI/(tWI + two).
Note 2: See Figure for additional I/O Characteristics.
Note 3:· Vee voltage change must be less than 0.5 V In a 1ms period to maintain proper operation.
Note 4: Exercise great care not to exceed maximum device power dissipation limits when dlrect·drlving LEOs (or sourcing similar
loads) at high temperature.
'2-140
I
()
0
GND
OKI
"tJ
CKG
I\)
~
~
-
0
()
0
"tJ
I\)
~
~
()
0,
0
0,
"tJ
0,
I\)
~
~
00
j\)
()
SO MICROWIRE 110
SKI
0
51
I\)
CA)
~
"tJ
e
IN,-::-'..f--+-~t--4-
()
G,
0
G,
IN2 37
IN135
"tJ
G,
INo-'-6..f---_~-_
I\)
CA)
GO
~
()
0
"tJ
I\)
CA)
~
I\)
Figure 2. COP2440 Block Diagram
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ INSTRUCTION CYCLE TIME ( I c l - - - - - - - - - - - - - - - - - _
-----1---CK!
..
lNl ZEROCROSSING OPTION
51
All OTHER
INPUTS
SO, SK
OUTPUTS
I-'POD~
,
AllOTHER ,
OUTPUTS
VOL
~~~--------------------------------
_VOH
I-~#
Figure 3. Input/Output Timing Diagrams (Divide by 16 Mode)
2-141
Ll
LO
SI
SO
SK
INO
IN3
GO
Gl
G2
G3
HO
HI
H2
H3
03
D2
Dl
DO
GNO
40
39
38
37
36
VCC
L2
L3
IN2
INI
L4
L5
COP24401
COP2340
11
)2
13
14 .
15
16
17
18
19
20
22
21
L6
L7
RO
Rl
R2
R3
R4
R5
R6
R7
RESET
CKI
CKO
GNO
CKO
CKI
RESEt
L7
L6
L5
L4
INI
IN2
VCC
L3
L2
Ll
28
27
26
4
25
5
24
23
COP24411 22
COP2341
8
21
9
20
10
19
11
18
12
17
13
16
14
15
DO
01
02
03
G3
G2
Gl
GO
IN3
INO
GND
CKO
CKI
RESET
L7
L6
L5
L4
VCC
L3
L2
Ll
SK.
SO
SI
LO
Order Number COP2440N, COP2340N Order Number COP2441N, COP2341N
NS Package N40A
NS Package N28A
6
~g~~~:r
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
00
01
D2
03
G3
G2
Gl
GO
SK
SO
SI
LO
Order Number COP2442N, COP2342N
NS Package N24A
Figure 4. Connection Diagrams
Pin
Description
L7 -Lo
B·bit bidirectional 1/0 port with
TRI·STATE'"
G3-G O
4·bit bidirectional 1/0 port
03- 0 0
IN3-INo
Pin
Description
CKI
System oscillator input
CKO
System oscillator output (or general
purpose input or RAM power supply)
4·bit general purpose output port
RESET
System reset input
4·bit general purpose input port (not
available on COP24421COP2342)
Vee
Power supply
GNO
Ground
H3- HO
4·bit bidirectional 1/0 port
(COP2440/COP2340 only)
R7- RO
B·bit bidirectional 1/0 port with
TRI·STATE'" (COP2440/COP2340 only)
SI
Serial input
SO
Serial output (or general purpose output)
SK
Logic·controlled' clock (or general
purpose output)
2-142
Functional Description
cessor can address any word in the program memory. A
new address is loaded into the PC register during each
instruction cycle. Unless the instruction is a transfer of
control instruction, the PC register is loaded with the
next sequential 11·bit binary count value. Since either of
the two processors can address any part of the ROM,
they can share any subroutines or codes.
The internal architecture of the COP2440 is shown in
Figure 1 and a more detailed block diagram is given in
Figure 2. Data paths are illustrated in simplified form to
depict how the various logic elements communicate with
each other in implementing the instruction set of the
device. Positive logic is used. When a bit is set, it is a
logic "1" (greater than 2.0 volts). When a bit is reset, It is
a logic "0" (less than 0.8 volts).
ROM instruction words are fetched, decoded and exe·
cuted by the Instruction Decode, Control and Skip Logic
circuitry.
Dual Processor
The COP2440 provides an ease of programming and a
degree of efficiency not previously available in a single
chip microcontroller. the dual CPUs allow easy partitioning of tasks. Simultaneous events can be monitored
and handled with ease. Furthermore, each CPU has
complete access to all of the ROM and RAM. Both subroutines and main line codes can be shared and both
processors can access the same code simultaneously
or at different times so that very efficient programs can
be written.
Data Memory
Data memory consists of a 640-bit RAM, organized as 10
data registers of 16 4·bit digits. RAM addressing for each
processor is implemented by its own 8-bit B register
whose upper 4 bits (Br) select 1 of 10 (0-9) data registers
and lower 4 bits (Bd) select 1 0116 4·bit digits in the
selected data register. While the 4-bit contents of the
selected RAM digit (M) is usually loaded into, or from, or
exchanged with the A register (accumulator), it may
also be loaded into or from the a latches, L port, R port,
EN register, and T counter (internal time base counter).
RAM may also be loaded from 4 bits of a ROM word. RAM
addressing may also be performed directly to the lower
8 registers by the LDD and XAD instructions based upon
the 7-bit contents of the operand field of these instruc·
tions. The Bd register also serves as a source register
for 4-bit data sent directly to the 0 outputs. The upper 2
registers of RAM also serve as subroutine stacks for the
two processors. Processor X uses register 8 as its stack,
and processor Y uses register 9. Note that it is possible,
but not recommended, to alter the contents of the stack
by normal data memory access commands.
The chip contains two internal processors, X and Y. In
order to distinguish between the two processors, start
with the RESET pin low; the chip is then in the reset
mode, with SK being a clock output; processor X executes when clock output is high and processor Y exe·
cutes when the clock output is low. When the RESET pin
goes high, both X and Y start at location 0 which con·
tains a CLRA instruction, then Y jumps to location 401
followed by X to location 1. The processors will then
alternately execute 1 byte of code each.
At maximum clock frequency, the instruction execution
time (single byte instruction) for each processor is
4Ils,hence, the instruction cycle time for either processor
is twice that amount, i.e., 81ls.
Internal Logic
Each processor has its own set of status registers: 4-blt
A register (accumulator), 8·bit B register (data memory
_ _ l_.l. __ '
t" ............ "
...
1_'1
_
Each processor contains its own 4-bit A register
(accumulator! whir.h i" thp. "nurr.p. OV, "0" if input < OV).
The ININ instruction and IN1 interrupt will then have
unique logic HIGH and LOW levels depending on the IN
port input level chosen. If normal (TTL) level is chosen,
logic HIGH level is 3.0V (3.3V for COP2340/2341) and
logic LOW level is 0.8V (0.6V for COP2340/2341); if high
trip level is chosen, logic HIGH level is 5.4V and logic
LOW level is 1.2V. If the zero·crossing detector is not
mask·programmed in (see Figure 9b), IN1 will have logic
111111
..L
OA
o"'C
RS
IN' INTERRUPT
(EN5,EN4=00)
(NEGATIVE EDGE)
\TV
ZERO· CROSSING INTERRUPT
(EN5.EN4=10)
(POSITIVE & NEGATIVE EDGE)
"NOTE: THIS INPUT HAS A DIFFERENT
SET OF LOGIC HIGH AND LOW LEVELS;
SEE A80VE DESCRIPTION
a. Zero·Crossing Detect Logic Option
ININ
..L
IN1 INTERRUPT
(EN5,EN4=00)
(NEGATIVE EDGE)
ZERO·CROSSING INTERRUPT
(EN5,EN4='0)
(POSITIVE & NEGATIVE EDGE)
b. IN1 without Zero·Crossing Detect LogiC
Figure 9. IN1 Mask·Programmable Options
2-147
~
o"'C
I\)
~
o
o
"'C
I\)
(0)
~
I\)
C\I
oo::t
C")
C\I
Q.
oo
-:;:
C")
C\I
Q.
oo
~
C\I
Q.
oo
~
Initialization
The reset logic, internal to the COP2440, will initialize
the device upon power·up if the power supply rise time
is less than 1 ms and greater than 1",s. If the power
supply rise time is greater than 1 ms, the user must
provide an external RC network and diode to the RESET
pin as in Figure 10. The RESET pin is configured as a
Schmitt trigger input. If not used, it should be connected
to Vcc. Initialization will occur whenever a logic "0" is
applied to the RESET Input, provided it stays low for at
least three instruction cycle times.
b. External Oscillator. CKI is an external clock input
signal. The external frequency is divided by 16 (op·
tional by 8 or 4) to give the execution frequency. If the
divide·by·4 option is selected, the CKI input level is
the Schmitt·trigger level. CKO is now available to be
used as the RAM power supply (V R) or as a general
purpose input.
c . RC Controlled Oscillator. CKI is configured as a
single pin RC controlled Schmitt trigger oscillator.
The execution frequency equals the oscillation fre·
quency divided by 4. CKO is available for non·timing
functions.
Upon initialization, the PC register is cleared to 0 (ROM
address 0) and the A, B, C, D, EN, G, H, IL, L, N, Q, R, and
T registers are cleared. The SK output is enabled as a
SYNC output by setting the SKL latch, thus providing a
clock. RAM (data memory and stack) is not cleared. The
first instruction at address 0 must be a CLRA.
eKO Pin Options
As an option, CKO can be an oscillator output. In a
crystal controlled oscillator system, this signal is used
as an output to the crystal network. As another option,
CKO can be an interrupt input or a general purpose input,
reading into bit 2 of A (accumulator) through the INIL
instruction. As another option, CKO can be a RAM power
supply pin (VR), allowing its connection to a standby!
backup power supply to maintain the data integrity of
RAM registers 0-3 with minimum power drain when the
main supply is inoperative or shut down to conserve
power. Using either of the two latter options is appro·
priate in applications where the system configuration
does not require use of the CKO pin for timing functions.
C\I
Q.
o
o
-:i
P +
0
C\I
Q.
oo
y
~
~~
COP2440
RESET
.:=:
GND
RC" 5 x POWER SUPPL Y RISE TIME
Figure 10. Power·Up Clear Circuit
Q.
o
o
Vcc
-~
W
E
R
S
U
P
P
L
RAM Keep·Alive Option
Selecting CKO as the RAM power supply (VR) allows the
user to shut off the chip power supply (Ved and maintain
data in the lower 4 registers of the RAM. To insure that
RAM data Integrity is maintained, the following condi·
tions must be met:
1. RESET must go low before Vee goes below spec
during power·off; Vee must be within spec before
RESET goes high on power·up.
2. When Vee is on, VR must be within the operating
voltage range of the chip, and within 1 volt of Vee.
Oscillator
There are three basic clock oscillator configurations
available, as shown by figure 11.
a. Crystal Controlled Oscillator. CKI and CKO are con·
nected to an external crystal. The ~xecution frequency
equals the crystal frequency divided by 16 (optional
by 8). Thus a 4 MHz crystal with the divide·by·16 option
selected will give a 250 kHz execution frequency (4",s
execution time) and a 125 kHz instruction cycle fre·
quency (8",s instruction cycle time).
3. VR must be ;;. 3.3V with Vee off.
Crystal Oscillator
A
CKI
CKI
CKO
10M
...flJ
EXTERNAL
CLOCK
a. Crystal Oscillator
I
I-b
-=-
(CLOCK OUTPUT,
VR OR GENERAL
PURPOSE INPUT PIN)
b. External Oscillator
CKO
Vcc
Y' Y
t
(CLOCK OUTPUT,
VR OR GENERAL
PURPOSE INPUT PIN)
c. RC Controlled Oscillator
Crystal Value
Rl
4MHz
3.58MHz
2.10MHz
1k
1k
2k
RC Controlled Oscillator
R (kQ)
C (pF)
Instruction
Execution
Time (",s)
13
6.8
8.2
22
100
220
300
100
5.0±;20%
5.3±23%
8.0±22%
8.2± 17%
Note: 5kQ .. R .. 50kQ
50pF .. C .. 360pF
. Figure 11. COP2440/244112442 Oscillators
2-148
o
o"'D
1/0 Options
COP2440 inputs have the following optional configurations, illustrated in figure 12:
Notes:
1. When the driver is disabled, the depletion device
may cause the output to settle down to an intermediate level between Vee and GND. This voltage
cannot be relied upon as a "1" level when reading
the L inputs. The external signal must drive it to a
"1" level.
2. Much power is diSSipated by this driver in driving
an LED. Care must be taken to limit the power dissipation of the chip to within the absolute maximum ratings specified.
I. TR/·STATE'" Push-Pull an enhancement-mode
device to ground and Vee. These outputs are TRISTATE outputs, allowing for connection of these
outputs to a data bus shared by other bus drivers.
Available on Land R outputs only (in TRI-STATE mode
on reset).
1_ Push-Pull R - same as t, but may be disabled_ Available on R outputs only_
a_ An on-chip depletion load device to Vcc.
b. A Hi-Z input which must be driven to a "1" or "0" by
external components_
c_ A resistive load to GND for the zero-crossing input
option (IN, only).
COP2440 outputs have the following optional configurations:
d_ Standard - an enhancement mode device to ground
in conjunction with a depletion-mode device to Vcc ,
compatible with TTL and CMOS input requirements.
Available on SO, SK, D, G, and H outputs.
e_ Open-Drain - an enhancement-mode device to
ground only, allowing external pull-up as required by
the user's application. Available on SO, SK, D, G, L, H,
and R outputs.
#. Push-Pull - An enhancement-mode device to ground
in conjunction with a depletion-mode device paralleled by an enhancement-mode device to Vee. This
configuration has been provided to allow for fast rise
and fall times when driving capacitive loads. Available
on SO and SK outputs only.
g_ Standard L,R - same as do, but may be disabled.
Available on Land R outputs only (disabled on reset).
h_ LED Direct Drive - an enhancement-mode device to
ground and Vee together with a depletion device to
Vee meeting the typical current sourcing requirements
of the segments of an LED display_ The sourcing
devices are clamped to limit current flow. These
devices may be turned off under program control
(See Functional Description, EN Register), placing
the output in a high-impedance state to provide
required LED segment blanking for a multiplexed
display. Available on L outputs only.
k. Additional depletion pull·up - a depletion load to Vee
with the same current sourcing capability as the input
load a., in addition to the output drive chosen. Avail·
able on Land R outputs only. This device cannot be
disabled; therefore, open-drain outputs with "1"
output and TRI·STATE outputs do not show highimpedance characteristics. This device is useful in
applications where a pull-up with low source current
is desired, e.g., reading keyboards and switches.
r-l
ri
Vee
'"'~
b. Hi·Z Input
c. Zero·Crosslng Input
a. Input with Load
f. Push-Pull Output
r-- ~~
"-'[]----/>-
#1
~2i
g. Standard L,R Outputs
OISABLE~#~vee
:;-J .. #4
d. Standard Output
~f
e. Open·Draln Output
i. TRI·STATE'" Push·Pull
(L,R) Outputs
r_5.:e~:. .
L.R OUTPUT _ _...
k_ Additional L,R Outputs
Pull·Up
Push-Pull R Outputs
Figure 12. Input/Output Configurations
2-149
(&IS DEPLETION DEVICE)
1 ...
#3
I.
o"'D
I\)
;
-
o
o"'D
~
~~
o
o"'D
~
-I:a
S2
o
o"'D
I\)
~
(=)
o"'D
I\)
The above Input and output configurations share common enhancement-mode and depletion-mode devices.
Specifically, all configurations use one or more of six
devices (numbered 1-6 respectively). Minimum and
maximum current (lOUT and VOUT) curves are given in
Figures 13 and 14 for each of these devices to allow the
designer to effectively use these I/O configurations in
designing a COP2440 system.
Vee
INPUT~
~o
h. LED (L) Outputs
~
C"II
~
C"II
0.3
D..
o
30
~
~
C"II
D..
o
o
o
oo:t
0.2
""E
"i
I
~
!;
20
o
\
7
1\
VoUT - VOLTS
VIN - VOLTS
D..
oo
20
\.
1.5
/-fj-VCC=6.3V (MAX.)
0.3
""EI
...I
...=>
§
0.2
'"
o
VCC=6.3V
"- \..
~
VOUT - VOLTS
D..
o
""~
...=>
.1
I
1.5
VOUT - VOLTS
1.0
\
9
0.5
II
VCC=4~~\
t-(i
o
IN .)
.l
\.
o
l-t
1\\
.!(MIN/-
""EI
VCC=4.5V
(MAX.)
~
\
~ :::-.
\
1\-
1.0
\
\
0.5
"
o
rt
VCC=4.5V
(MIN.) 1
VCC=6.3V
(MIN.)-
i
1
'1i
0.3
""T
1
0.2
\(MAX.)
9
0.1
\
o
~MjN.)\
o
DEVICE 5
VOUT - VOLTS
DEVICE 4
i. Depletion Load OFF Current
20
i<-+-¥-+--+-f--+-I
""E
...I
9
t--t--T'r--p,...--1c----+-t--j
1.0
15
/
II
(MAX.)
"\
I\VCC=6.3V
\
'I
VCCi4.5i \
o
VOUT - VOLTS DEVICES 4 AND 6
j. LED Output Source Current
VoUT=2V
1\
2.0
15 I--''tt--t-Y
10
OEVICE 3
1\
!;
h. TRI·STATE® Output Source Current
...I
§
1
o
VOUT - VOLTS
25
20
-
f. Output Sink Current
..1
.1
VCC=4.5V(MAX.)
VoUT - VOLTS
1
OEVICE 4
\ \1 1
o
VOUT - VOLTS OEVICES 4 ANO 5
g. Push· Pull Source Current
o
.1
.1_
VCC=6.3V(MAX.)
\
1.5
VCC=6.3V
L
e. Standard Output Minimum Source
Current
VCC=6.3V(MAX.)
I-
""-
o
~cr 6.3 1(MIN.)-
It ~ ~14(M+-
"'" "'"
"-
DEVICE 4
d. Standard Output Source Current
V
10
§
c---- V1CC=i·5V
o
,J
""E
'\
0.1
~o
15
"- \..
k"
VCC=4.5V (MA~
\
""E
OEVICE 2
c. Zero·Crossing Detect Input
Current
0.4
C"II
f(M;;;:
-
DEVICE 1
b. Input Load Minimum Source Current
~
'lit
L-
V
-1
DEVICE 1
a. Input Load Source Curent
/'
l'- r-.....
o
VOUT - VOLTS
""I
~
o
D..
~
~
VCC=4.5V""",
o
D..
V
(MAXyV
E
I\.VCC=6.3V
10
C")
~
'\1\
1'\
9
0.1
C"II
-
t\
\
o
""E
...I
k. LED Output Minimum Source Current
Figure 13. COP2440/2441/2442 1/0 Characteristics
2-150
V
/'"
10
V
§
(MIN.)
o
~
4.5
VOUT - VOLTS OEVICES 4 AND 6
",,,,,/
5.5
6.5
VoUT - VOLTS DEVICES 4 ANO 6
I. LED Output Direct LED Drive
0.3
,
30
~
0.2
20
""'"I
""E
"\
....
I
~
-
10
I
o
VOUT - VOLTS
'""
""EI
""EI
1.0
\
OEVICE 1
I
0.1
....
=>
'\
VCCr·5V
o
o
VOUT - VOLTS
10
5.0
f
0
//
1---+--++-\++-44 Vcc ~4.5 V
I I (MAX.)
. 'r-\I
I
0.5
I
VCC=5.5V
....
=>
52
VOUT - VOLTS
o
-VCC=4.5V\
(MIN.)
I
o
DEVICES 4 ANO 5
g. Push· Pull Source Current
0.21--~--r-+--,1---+-~
1\\
0.1
~IN.)\
\\
VOUT - VOLTS
OEVICE 3
.::I\L,IIIII
!\
1
4.5V (MIN.)
f. Output Sink Current
....I
§:
-(Mlr)
0.5
VCC
0
VCC=5.5V
'$
VCC=51V (Mli')-
~
DEVICE 4
1.5 I---+--++-l-H--+-(MAX.)
"2
I
....
§:
I
/
e. Standard Output Minimum Source
Current
1.5
I
f-.. VCC=4.5V (M1AX.)
0>
" '"'"~
OEVICE 4
d. Standard Output Source Current
""EI
VCC=5.5V
DEVICE 2
~CC=~.5V (JAX)
:.-
15
'\
52
VOUT - VOLTS
VIN - VOLTS
c. Zero·Crossing Detect Input
Current
\
I\. I\.
0.5
-(MIN.)
~ f--" f...--
20
"\ "\
0.2
....=>
....
§:
VOUT - VOLTS
7
\ \
b. Input Load Minimum Source Current
0.3
//
-1
VOUT - VOLTS
1.5
/V
~
o
OEVICE 1
a. Input Load Source Current
2.0
~
~
I
J
(MA/
""E
VCC=5.5V
VCC~~
=>
52
0.1
4.0
o~~--~~--~~~~
o
~
OEVICE 5
VOUT - VOLTS
OEVICE 4
i. Depletion Load OFF Current
h. TRI·STATE® Output Source
Current
20
VOUT=2V
;:
2.0
~
15 1----+-\--+,,,,
I
....
§:
10
f--+-\t----\+--f--t----j
""E
....I
9
1.0
~
~
\
VCCr·5V
o
VCC - VOLTS OEVICES 4 ANO 6
j. LED Output Source Current
(MAXY
\"""-
15
r--
""E
I
....
§:
10
V
/
V
1\ \
\
(MIN.)
.\..
o
o
r-
4.5
VOUT - VOLTS DEVICES 4 ANO 6
k. LED Output Minimum Source Current
Figure 14. COP2340/2341/2342 1/0 Characteristics
2-151
5.0
5.5
6.0
VOUT - VOLTS DEVICES 4 AND 6
I. LED Output Direct LED Drive
Power Dissipation
g. R, SO, and SK do not diSSipate any significant
amount of power because they do not not need to
source or sink any current.
In order not to damage the device by exceeding the
absolute maximum power dissipation rating, the
amount of power dissipated inside the chip must be
carefully controlled. As an example, an application uses
a COP2440 in a room temperature (25°C) environment
with a Vcc power supply of 6V; IN and SI inputs have in·
ternalloads; G and D ports drive loads that may sink up
to 2 mA into the chip; H port with standard output option
reads switches; L port with the LED option drives a
multiplexed seven·segment display; R, SO and SK drive
MOS inputs that do not source or sink any current.
Total power dissipation (TPD) inside the device is the
sum of items b through g above.
TPD =210 +9+6+36 +476mW= 737mW
This is within the 750mW limit at room temperature. If
this application has to operate at 70°C, then the power
diSSipation must be reduced to meet the limit at that
temperature. Some ways to achieve this would be to
limit the LED current or to use an external LED driver.
a. At 25°C, maximum power dissipation allowed = 750mW.
b. Power dissipation by chip except 1/0 = Icc x Vcc =
35mAx 6V=210mW.
At 70°C the absolute maximum power dissipation rating
drops to 400 mW. The user must be careful not to exceed th is val ue.
c. Maximum power dissipation by IN, SI =
5xO.3mA x 6V =9mW
COP2440 Series Devices
d. G and D ports are sinking current from external loads;
maximum output voltage with 2mA sink current is
less than O.4V. Power dissipation by G and D ports =
2mAx0.4V x 8=6.4mW
If the COP2440 is bonded as a 28· or 24-pin device, it
becomes the COP2441 or COP2442, respectively, as il·
lustrated in Figure 4. Note that the COP2441 and
COP21142 do not include Hand R ports. In addition, the
COP2442 does not include IN inputs; use of this option
precludes the use of the IN options, the interrupt
feature with IN as input, the zero·crossing detect option, IN2 external event counter input, and the
MICROBUSTM option. All other options are available.
e. Maximum power dissipation by H port =
4 x 1.5mA x 6V =36mW
f. When the seven segments of the LED are turned on,
the output voltage is about 2V, so that the segment
current is 17 mAo Power dissipation by L port
7x 17mA x(6V - 2V)=476mW
This power dissipation caused by driving LEDs is
usually the highest among the various sources.
=
COP2340, COP2341, and COP2342 are extended temper,
ature versions of the COP2440, COP2441, and COP2442,
respectively.
COP2440 Series Instruction Set
Table 3 provides the mnemonic, operand, machine code,
data flow, skip conditions and description associated with
each instruction in the COP2440 series instruction set.
Table 2 is a symbol table providing internal architecture,
instruction operand and operation symbols used in the
Instruction set table.
Table 2. COP2440 Series Instruction Set Table Symbols
Symbol
Symbol
Dellnillon
Definition
INTERNAL ARCHITECTURE SYMBOLS
INSTRUCTION OPERAND SYMBOLS
A
d
B
Br
Bd
C
D
EN
G
H
IL
IN
IN,Z
L
M
N
PC
Q
R
SIO
SK
T
X
Y
4·bit Accumulator
B·bit RAM Address Register
Upper 4 bits of B (register address)
Lower 4 bits of B (digit address)
1·bit Carry Register
4·bit Data Output Port
B·bit Enable Register
4·bit Register to latch data for G 110 Port
4·bit Register to latch data for H 110 Port
Two 1·bit Latches associated with the IN3 or
INa Inputs
4·bit Input Port
Zero·Crossing Input
-B·bit TRI·STATE" 110 Port
4·bit contents of RAM Memory pointed to by
B Register
2-bit subroutine return address stack pointer
"-bit ROM Address Register (program
counter)
B·bit Register to latch data for L 110 Port
B·bit Register to latch data for R TRI·STATE
110 Port
4·bit Shift Register and Counter
Logic·Controlied Clock Output
B·bit Binary Counter Register
First On·Chip Processor
Second On·Chip Processor
2-152
-r
a
y
RAM(s)
RAMN
ROM(t)
4·bit Operand Field, 0-15 binary (RAM Digit
Select)
4·bit Operand Field, 0-9 binary (RAM
Register Select)
"·bit Operand Field, 0-2047 binary (ROM
Address)
4·bit Operand Field, 0-15 binary (Immediate
Data)
Content of RAM location addressed by s
Content of RAM location addressed by
stack pointer N
Content of ROM location addressed by t
OPERATIONAL SYMBOLS
+
-
~
=
A
ffi
V
Plus
Minus
Replaces
Is exchanged with
Is equal to
The one's complement of A
Exclusive·OR
Range of values
OR
Table 3. COP2440 Series Instruction Set
Mnemonic Operand
Hex
Code
Machine
Language Code
(Binary)
Data Flow
Description
Skip Conditions
ARITHMETIC/LOGIC INSTRUCTIONS
ASC
30
[0011[0000[
A + C + RAM(B) - A
Carry - C
Carry
Add with Carry, Skip on
Carry
ADD
31
10011100011
A+ RAM(8) - A
None
Add RAM to A
ADT
4A
10 1 0011 01 01
A+ 10'0 c.. A
None
Add Ten to A
5-
[0101 1 y
A+y - A
Carry
Add Immediate, Skip on
Carry (Y" 0)
CASC
10
/0001100001
A + RAM(8) + C - A
Carry - C
Carry
Complement and Add with
Carry, Skip on Carry
CLRA
00
10000100001
O-A
None
Clear A
COMP
40
101 001 0000 1
A-A
None
One's complement of A to A
NOP
44
1010010 1 001
None
None
No Operation
OR
33
1A
10 a 1 110 01 11
AvM -A
None
OR RAM with A
10001110101
RC
32
10 01110 0 1 0\
"0" -C
None
Reset C
SC
22
100 10100 10 1
"1" - C
None
Set C
XOR
02
10000100101
A
None
Exclusive·OR RAM with A
AISC
Y
I
EO
RAM(8)- A
TRANSFER OF CONTROL INSTRUCTIONS
JID
JMP
or-
a
FF
11111111111
ROM (PC'O:8, A,M) - PC7:0 None
Jump Indirect (Note 3)
6-
10 11 0101 a1081
a- PC
None
Jump
--
I
1'1 a6:0
(pages 2,3 on Iy)
or
I
a- 1-'(.;6:0
None
Jump within Page (Note 4)
I
a - PC5:0
PC+1-RAMN
N+l- N
00010 - PC'O:6
a - PC5:0
None
Jump to Subroutine Page
(Note 5)
PC+1-RAMN
N+l - N
a- PC
None
Jump to Subroutine
a
a7:0
I
[11[ a5:0
(all other pages)
JSRP
a
JSR
a
110 1
6-
a5:0
10 1 1 0111 a,o:sl
I
a7:0
I
RET
48
10 1 0011 0001
N-l- N
RAMN - PC
None
Return from Subroutine
RETSK
49
10100110011
N-l- N
RAMN - PC
Always Skip on Return
Return from Subroutine
then Skip
2-153
Table 3. COP2440 Series Instruction Set (continued)
Machine
Mnemonic Operand
Hex
Code
Lan~Uage Code
Binary)
Data Flow
Skip Conditions
Description
MEMORY REFERENCE INSTRUCTIONS
CAME
CAMO
CAMT
CEMA
COMA
CTMA
LD
r
LDD
r,d
33
10011100111
A- EN7:4
1F
10001111111
RAM(B) - EN3:0
33
10011100111
A- 0 7:4
3C
10011111001
RAM(B) - 03:0
33
10011100111
A- T7:4
3F
10011111111
RAM(B) -T3:0
33
10011100111
EN7:4 - RAM(B)
OF
10000111111
EN3:0- A
RMB
None
Copy A, RAM to T
None
Copy EN to RAM, A
10011100111
07:4 - RAM(B)
03:0 - A
None
Copy 0 to RAM, A
10010111001
None
Copy T to RAM, A
33
10011100111
T7:4 - RAM(B)
2F
10010111111,
T3:O - A
-5
1001r'101011
r-0:3
RAM(B)-A
Brer-Br
None
Load RAM Into A,
Exclusive-OR Br with r
23
10011 0100 111
RAM(r,d)-A
None
Load A with RAM pointed
to directly by r,d
ROM (PC10:8,A,M) -M,A
None
Load RAM, A Indirect
None
Load 0 Indirect (Note 3)
I
d
101 r
r=0:7
I
1001110011 j
19
10001110011
BF
/1011111111
ROM(PC1O:a.A,M) - 0
0
4C
10100/11001
0- RAM(BIo
1
45
10 1 0010 1 0 11
0- RAM(Blt
2
42
10100100101
0- RAM(B)2
3
43
10100100111
0- RAM(B)3
0
40
101 001 11 0 11
1 - RAM(B)O
1
47
10 1 0010 11 11
1 - RAM(Blt
2
46
1°100101101
1- RAM(B)2
3
41il
101 001 1011 1
1- RAM(B)3
STII
y
7-
y
10111 1
I
X
r
-6
XAD
r,d
5MB
None
33
33
LOID
Copy A, RAM to EN
(Processor Y loads EN2,
EN7 only)
Copy A, RAM to 0
2C
-LID
None
. None
Reset RAM Bit
None
Set RAM Bit
y- RAM(B)
Bd+1 -Bd
None
Store Memory Immediate
and Increment Bd
1001 r 101101
r=0:3
RAM(B)-A
Brer-Br
None
Exchange RAM with A,
exclusive-OR Br with r
23
10010100111
RAM(r,d) -A
None
--
d
/11 r
r=0:7
Exchange A with RAM
pointed to directly by r,d
I
I
XDS
r
-7
1001 r 10 11 11
r-0:3
RAM(B)-A
Bd-1 - Bd
Bre r - Br
Bd decrements past 0
Exchange RAM with A
and Decrement Bd,
Exclusive-OR Br with r
XIS
r
-4
10°1 r 10 1 001
r-0:3
RAM(B)-A
Bd+1 - Bd
Brer-Br
Bd increments past 15
Exchange RAM with A
and Increment Bd,
Exclusive-OR Br with r
2-154
Table 3. COP2440 Series Instruction Set (continued)
Mnemonic Operand
Hex
Code
Machine
Lanyuage Code
Binary)
Data Flow
Description
Skip Conditions
REGISTER REFERENCE INSTRUCTiONS
CAB
50
101011000°1
A - Bd
None
Copy A to Bd
CBA
4E
101 0 011 11 01
Bd -A
None
Copy Bd to A
--
1001 r l(d-111
r=0:3,d-O,9:15
or
r,d - B
Skip until not a LBI
LBI
LEi
r,d
y
XABR
XAN
33
10 a 1 110 a 1 11
--
d
111 r
r=0:7,any d
I
Load B Immediate with r,d
(Note 6)
I
33
10 a 1 110 a 1 11
6-
10 11 01
12
y - EN3:0
None
Load lower half of EN
Immediate
(Processor Y loads EN2 only)
10001100101
A - Br
None
Exchange A with Br
A - N(O,O - A3,A-;j
None
Exchange A with N
y
I
33
10 a 1 110 a 111
OB
10000110111
TEST iNSTRUCTIONS
SKC
20
10010100001
C="1"
Skip if C is True
SKE
21
10 a 1 010 a 011
A=RAM(B)
Skip if A Equals RAM
SKGZ
33
10011100111
G3:0=0
Skip if G is Zero (ali 4 bits)
21
1°010100011
33
10011100111
01
10 0 0 010 a 011
SKGBZ
a
SKMBZ
SKSZ
SKT
Skip if G Bit is Zero
1st byte
Go=O
1
11
10 a a 110 0 a 11
2
03
10000100111
OJ
lJ
IUUU'IUU' '1 J
G3=O
0
01
10000100011
RAM(Blo=O
1
11
1000 110 0 0 11
RAM(B)1 =0
2
03
10000100111
RAM(B)2=0
3
13
10 00 1100 1 11
RAM(B13=O
SIO=O
Skip if SIO is Zero
T counter carry has
occurred since last
test
Skip on Timer (Note 3)
33
100 1 1100 1 11
1C
10001111001
41
10100100011
1'"' "''
G 1 =0
G2=0
2-155
Skip if RAM Bit is Zero
N
oo::t
Table 3. COP2440 Series Instruction Set (continued)
M
N
a..
0
-,..
()
oo::t
Mnemonic Operand
Hex
Code
Machine
Lan~uage Code
Binary)
M
INPUT/OUTPUT INSTRUCTIONS
a..
CAMR
N
0
oo::t
ING
M
33
100 1 1100 1 11
A - R7:4
3D
10011111011
RAM (B) - R3:0
33
10011100111
2A
10010110101
N
a..
0
INH
()
N
oo::t
oo::t
ININ
33
10 0 1 1100 1 11
2B
·1001Oj10111
33
10011100111
28
10010110001
N
a..
0
-
INIL
()
~
INL
oo::t
N
a..
0
-
INR
()
0
oo::t
oo::t
OBD
N
a..
0
()
Skip Conditions
Description
\
()
0
Data Flow
OGI
OMG
OMH
XAS
Y
None
Output A,RAM to R Port
G-A
None
Input G Port to A
H-A
None
Input H Port to A
IN-A
None
Input IN Inputs to A (Note 2)
IL3, CKO, IN1Z, ILo - A
None
33
100 1 1100 1 11
29
10010110011
33
10011100111
L7:4 - RAM(B)
2E
10010111101
L3:0- A
Input IL Latches to A
(Note 3)
None
Input L Port to RAM,A
None
Input R Port to RAM,A
33
100 1 1100 1 11
R7:4 - RAM(B)
2D
10 0 1 011 1 0 11
R3:0 - A
Bd - D
None
Output Bd to 0 Port
y-G
None
Output to G Port Immediate
RAM(B)- G
None
Output RAM to G Port
RAM(B)- H
None
Output RAM to H Port
A - SIO, C - SKL
None
Exchange A with SIO
(Note 3) Processor X only
33
10011100111
3E
10011111101
33
100 1 1100 1 11
I
5-
10101 1
33
100 1 1100 1 11
3A
10011110101
y
33
100 1 1100 1 11
3B
10011110111
4F
10100111111
Nolel: All subscripts for alphabetical symbols Indicate bit numbers unless explicitly defined (e.g.. , Br and Bd are explicitly defined). Bits are numbered 0 to N
where 0 signifies the least significant bit (Iow'order, right·most bit). For example, A3 indicates the most significant (ieft'most) bit of the 4·bit A register.
Nole 2: The ININ instruction Is not available on the 24·pln COP2442/COP2342 since this device does not contain the IN inputs.
Nole 3: For additional information on the operalion of the XAS, JID, LaiD, INIL, and SKT Instructions, see below.
Not. 4: The JP Instruction ailows a jump, while in subroutine pages 2 or 3, to any ROM location within the two-page boundarY of pages 2 or 3. The JP
Instruction, otherwise, permits a jump to a ROM location within the current 64·word page. JP may not Jump to the last word of a page.
Nole 5: A JSRP transfers program control to subroutine page 2 (00010 is loaded Into the upper 5 bits of Pl. A JSRP may not be used when In pages 2 or 3. JSRP
may not jump to the last word in page 2.
Not.6: LBI is a singie·byte instruction If d = 0,9,10, 11, 12, 13, 14, or 15. The machine code for the lower 4 bits equals the binarY value of the "d" data minus 1,
e.g., to load the lower four bits of B (Bd) with the value 9 (10012), the lower 4 bits of the LBI Instruction equal B (10002>. To load 0, the lower 4 bits of the LBI
instruction should equal 15 (11112>.
2-156
o
o."
Description of Selected Instructions
sending a "1" if the input is above zero volts and a "0" if
it is below zero volts. INIL is useful in recognizing pulses
of short duration or pulses which occur too often to be
read coriveniently by an ININ instruction. It is also useful
in checking the status of the zero-crossing detect input.
The general purpose input IN3-INo are input to A upon
execution of an ININ instruction, and the IN, input does
not go through zero-crossing logic so that it has the
same logic level as the other IN inputs for the ININ instruction (see Figure 9).
The following information is provided to assist the user
in understanding the operation of several unique instructions and to provide notes useful to programmers
in writing COP2440 programs.
XAS Instruction
XAS (Exchange A with SIO) can only be executed by
processor X. It exchanges the 4-bit contents of the accumulator with the 4-bit contents of the SIO register. The
contents of SIO will contain serial-in/serial-out shift
register or binary counter data, depending on the value
of the EN register. An XAS instruction will also affect
the SK output. (See Functional Description, EN register,
above). If SIO is selected as a shift register, an XAS
instruction must be performed once every 4 instruction
cycles to effect a continuous data stream. Processor Y
treats XAS as Nap.
Note: IL latches are cleared on reset. This is different
from the COP420/420C/420Ll444L series.
LaiD Instruction
LaID (Load a Indirect) loads the a-bit a register with the
contents of ROM pointed to by the 11·bit word PC1Q:PCa,
A, M. LaiD can be used for table lookup or code conver·
sion such as BCD to seven-segment. Note that LaiD
takes two instruction cycles if executed and one in·
struction cycle if skipped. Unlike most other COPSTM
processors, this instruction does not push the stack.
JID Instruction
JID (Jump Indirect) is an indirect addressing instruction,
transferring program control to a new ROM location
pointed to indirectly by A and M. It loads the lower a bits
of the ROM address register PC with the contents of
ROM addressed by the 11-bit word, PC'O:B, A, M. PC,o,
PCg and PCB are not affected by this instruction.
LID Instruction
Note that JID requires 2 instruction cycles if executed, 1
instruction cycle time if skipped.
LID (Load Indirect) loads M and A with the contents of
ROM pointed to by the 11·bit word PC,o:PC a, A, M. Note
that LID takes three instruction cycles if executed and
two if skipped.
INIL Instruction
SKT Instruction
INIL (Input IL Latches to A) inputs 2 latches, IL3 and ILo,
CKO and IN, into A (see Figure 15). The IL3 and ILa latches
are set if a low-going pulse ("1" to "0") has occurred on
the IN3 and INa inputs since the last INIL instruction,
provided the input pulse stays low for at least one instruction cycle. Execution of an INIL inputs IL3 and ILa
into A3 and AO respectively, and resets these latches to
The SKT (Skip On Timer) instruction tests the state of
the T counter (see internal logic, above) overflow latch,
executing the next program instruction if the latch is not
set. If the latch has been set since the previous test, the
next program instruction is skipped and the latch is reset.
The features associated with this instruction allow the
processor to generate its own time·base for real·time processing, rather than relying on an external input signal.
..... 11 ........ +hol'T"l tn rcC!~nnrl tn cUlh~pnllpnt
Inw-noinn Dulses
on the IN3 and INa lines. If CKO is mask-programmed as
a general purpose input, an INIL will input the state of
CKO into A2. If CKO has not been so programmed, a "1"
will be placed in A2. Unlike the COP420/420C/420Ll444L
series, INIL will input IN, into A1. If zero-crossing detect
is selected, the IN, input will go through the detection
logic, thus allowing the user to interrogate the input,
Instruction Set Notes
a. The first word of a COP2440 program (ROM address
0) must be a CLRA (Clear A) instruction.
b. Although skipped instructions are not executed, they
are still fetched from program memory. Thus program
paths take the same number of cycle times whether
instructions are skipped or executed, except for LID,
LaiD, and JID.
ININ
c . The ROM is organized into 32 pages of 64 words
each. The Program Counter is an 11-bit binary counter,
and will count through page boundaries. If a JP, JSRP,
JID, LaiD, or LID instruction is the last word of a page,
the instruction operates as if it were in the next page.
For example: a JP located in the last word of a page
will jump to a location in the next page. Also, a LaID
or JID located in the last word of page 3, 7, 11, 15,
19,23,27, or 31 will access data in the next group of
four pages.
1.
IND/IN3
t
RESET
INll
Figure 15. INIL Hardware Implementation
2-157
~
o
o
."
~
o
o
."
N
fto
o
."
N
eo
Co)
o
."
N
Co)
::
oo
."
N
Co)
~
I
('II
. To load 0, the lower 4 bits of the LBllnstruction should equal 15
(11112)·
Note 6: Machine code for operand field y for LEI Instruction should equal the binary value to be latched Into EN, where a "1" or "0" In each bit of EN
corresponds with the selection or deselection of a particular function associated with each bit. (See Functional Description, EN Aeglster.)
3-13
•
....I
~
o
(,)
Instruction Set Notes
The following Information is provided to assist the user
in understanding the operation of several unique il'1struc·
tions and to provide notes useful to programmers in
writing COP401L programs.
a. The first word of a COP401L program (ROM address 0)
must be a CLRA (Clear A) instruction.
b. Although skipped instructions are not executed, one
instruction cycle time is devoted to skipping each
byte of the skipped instruction. Thus all program
paths except JID and LaiD take the same number of
cycle times whether instructions are skipped or exe·
cuted. JID and LaiD instructions take 2 cycles if exe·
cuted and 1 cycle if skipped.
XAS Instruction
XAS (Exchange A with SIO) exchanges the 4·blt contents
of the accumulator with the 4·blt contents of the SIO
register. The contents of SIO will contain serlal·in/serial·
out shift register or binary counter data; depending on
the value of the EN register. An XAS Instruction will also
affect the SK output. (See Functional Description, EN
Register, above.) If SIO is selected as a shift register, an
XAS instruction must be performed once every 4 instruc·
tion cycles to effect a continuous data stream.
JID Instruction
Jib (Jump Indirect) Is an indirect addressing instruction,
transferring program control to a new ROM location
pOinted to indirectly by A and M. It loads the lower 8 bits _
of the ROM address register PC with the contents of
ROM addrlilssed by the 9·blt word, PCs, A, M. PCs is not
affected by this Instruction.
c. The ROM is organized into 8 pages of64 words each.
The Program Counter is a 9·bit binary counter, and
will count through page boundaries. If a JP, JSRP,
JID or LaiD instruction is located in the last word of
a page, the instruction operates as if it were in the
next page. For example: a JP located in the last word
of a page will jump to a location in the next page.
Also, a LaiD or JID located in the last word of page 3
or 7 will access data in the next group of 4 pages.
Typical Applications
Note that JID requires 2 Instruction cycles to execute.
PROM·Based System
LQID Instruction
The COP401L may be used to emulate the COP410L.
Figure 8 shows the interconnect to implement a COP401L
hardware emuiation. This connection uses one MM5204
EPROM as external memory._Other memory can be used
such as bipolar PROM or RAM.
LaID (Load a Indirect) loads the 8·bit a register with the
contents of ROM pOinted to by the 9·bit word PCs, A, M.
LaiD can be-used for table lookup or code conversion
such as BCD to seven·segment. The LaiD instruction
"pushes" the stack (PC + 1 - SA - SB) and replaces the
least significant 8 bits of PC as follows: A - PC7:4,
RAM(B) - P,C3:0, leaving PCa unchanged. The ROM data
pOinted to by the new address Is fetched and loaded
Into the a latches. Next, the stack Is "popped" (SB SA - PC), restoring the saved value of PC to continue
sequential program execution. Since LaiD pushes SASB, the previous contents of 58 are lost. Also, when
LQID pops the stack, the previously pushed contents of
SA are left In S8. The net result Is that the contents of
SA are placed In 58 (SA - 58). Note that LQID takes
two Instruction cycle times to execute.
Pins IP7-IPO are bidirectional inputs and outputs. When
the ADIDATA clocking output turns on, the EPROM
drivers are disabled and IP7-IPo output addresses. The
8·bit latch (MM74C373) latches the addresses to drive
the memory.
When AD/DATA turns off, the EPROM is enabled and
the IP7-IPO pins will Input the memory data. P8 outputs
the most significant address bit tei the memory. (SKIP
output may be used for program-debug If needed.)
24 of the COP401L pins may be configured exactly the
same as a COP410L. -
3-14
("')
o
"tJ
~
g
r-
12
-12V
20
~
-TI
Y
-#
14
13
11
10
9
8
VLL
VOO
A8
A7
A6
A5
MM5204
512x8 EPROM
A4
A3
7 A2
6
Al
AD
615~
19 16 15 12 9
+5V
VSS
VBB
PROGRAM
Q8 07 Q6 Q5 Q4 Q3 Q2 Ql
VCC
GND
MM74C373
LE
DUTPUT DIS
D8 D7 D6 D5 D4 D3 D2 Dl
18 17 14 13 8
7 14
3
PS
B7
B6
22
n
4---
CS 1.....B5
21
B4
20
B3
19
B2
18
Bl
17
Bo
15
16
RL=5.7K
A ...
:r:r
....
+5V
.""
:A:A""
' ..T
9
35
-#22
II
I
~--
~-t-t-t-
COP410L { GND CKO CKI RESET L7
PINOUT
1
2
3
4
5
P8
SKIP
36
10
IP6
---
3
IP5
1
2
4
11
--
---lLl
L6
IP7
5
IP4
6
IP3
7
IP2
8
IPl
NC
40
39
38
37
31
30
COP401 L
13
14
- L5
L4
15
-
16
17
18
19
20
r
33 134
AD/DATA
IPO
21
23
24
25
26
27
28
I
1
G3
20
D3
21
II
2
VCC
L3
10
L2
11
L1
12
LO
13
SI
14
SD
15
SK
16
Figure 8. COP401L Used to Emulate a COP410L
3-15
GO
17
Gl
18
G2
19
D2
22
Dl
23
DO
24
....I
i
11.
oo
COP401L Mask Options
The following COP410L options have been implemented
in this basic version of the COP401 L.
Option Value
Option Value
Comment
Comment
Option 1 = 0
Ground - no option
Option 14 = 0
81 has load to Vee
Option 2 = 1
CKO is RAM power supply input
Option 15 = 2
80 is push·pull output
Option 3 = N/A CKI is external clock divide·by·32 (not
available on COP410L)
Option 16 = 2
8K is push·pull output
Option 4=0
Option 18=0
Option 17=0
Reset has load to Vee
Option 5=2
Option 6=2
Option 7 =2
Option 19=0
Option 20=0
L outputs are LED direct·drive
Option 21 =0
Option 8=2
Option 9 = 1
G outputs are standard
Option 22=0
D outputs are standard
very high current
Vee pin 4.5V to 9.5V operation
Option 23=0
Option 10=2
Option 24=0
Option 11 =2
L outputs are LED direct·drive
. Option 25=0
L
Option 26=0
G
Option 27 = 0
81
Option 12=2
Option 13=2
Have standard TTL input levels
Option 28 = N/A 40·pin package
3-16
o
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~National
~
~ Semiconductor
~
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COP402/COP402M and COP302/COP302M
ROMless N·Channel Microcontrollers
General Description
Features
The COP402/COP402M and COP302/COP302M ROM less
Microcontrollers are members of the COPSTM family, fabbricated using N-channel silicon gateMOS technology.
Each part contains CPU, RAM, and I/O, and is identical
to a COP420 device, except the ROM has been removed;
pins have been added to output the ROM address and to
input ROM data. In a system, the COP402 or 402M will
perform exactly as the COP420; this important benefit
facilitates development and debug of a COP420 program
prior to masking the final part. These devices are also
appropriate in low volume applications, or when the program may require changing. The COP402M is identical
to the COP402, except the MICROBUSTM interface option
has been implemented.
•
•
•
•
•
•
•
•
•
•
•
•
•
~
N
~
Low cost
Exact circuit equivalent of COP420
Standard 40-pin dual-in-line package
Interfaces with standard PROM or ROM
64 x 4 RAM, addresses up to 1k x 8 ROM
MICROBUSTM compatible (COP402M)
Powerful instruction set
True vectored interrupt, plus restart
Three-level subroutine stack
4_0f's instruction time
Single supply operation (4.5V to 6.3V)
Internal time·base counter for real·time processing
Internal binary counter register with MICROWIRETM
serial I/O capability
• Software/hardware compatible with other members
of COP400 family
• Extended temperature range COP302 and COP302M
(-40°C to +85°C) available
The COP402 may also be used to emulate the COP410L,
411L, 420L or 420C by appropriately reducing the clock
frequency. The COP302 and COP302M are the extended
temperature range versions of the COP402 and COP402M.
o
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cops, MICROBUS, and MICROWIRE are trademarks of National Semiconductor Corp.
TRI-STATE is a registered trademark of National Semiconductor Corp.
ADIIDiiA
.-
"
"
"Jm
'"
"2
'"
"0
OJ
02
0,
DO
1.=====:::;-1"--:: I
MICROWIREl/D
GJ
G2
G,
Go
11
21
12
13
14
18
19
2Q
21
161526
IN) IN2 INI
ING
L7
L(j
LS
l4
lJ
l2
Ll
LO
Figure 1. COP402l402MBIock Diagram
3-17
:!:
N
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N
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a..
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:!:
N
~
a..
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N
o
.qa..
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COP402/COP402M and COP302/COP302M
Absolute Maximum Ratings
Voltage at Any Pin
-0.3Vto+7V
Operating Temperature Range
COP402/COP402M
O°Cto 70°C
COP302/COP302M
-40°C to +85°C
Storage Temperature Range
-65°C to +150·C
Lead Temperature (soldering, 10 seconds)
300°C
Package Power Dissipation
750 mW at 25°C
400mWat 70°C
250mWat 85°C
50mA
70mA
Total Sink Curr,ent
Total Source Current
Absolute maximum ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings.
COP402/COP402M
DC Electrical Characteristics
Parameter
Operation Voltage
Power Supply Ripple
Supply Current
Input Voltage Levels
CKI Input Levels
Crystal Input
. Logic High
Logic Low
Schmitt Trigger Input
RESET
Logic High
Logic Low
All Other Inputs
Logic High
Logic High
Logic Low
Input Load Source Current
Input Capacitance
Hi·Z Input Leakage
Output Voltage levels
D, G, L, SK, SO Outputs
TTL Operation
Logic High
Logic Low
IPO-IP7, P8, P9, SKIP, CKO,
ADIDATA
Logic High
Logic Low
CMOS Operation
Logic High
Logic Low
Output Current Levels
LED Direct Drive (COP402)
Logic High
TRI·STATE® (COP402M) Leakage Current
O°C,;; TA
,;;
70°C, 4.5V
~
Conditions
Vee
~
6.3V unless otherwise noted.
Min.
Max.
Units
.4.5
6.3
0.4
40
V
V
mA
2.4
-0.3
0.4
V
V
0.7 Vee
-0.3
0.6
V
V
peak to peak (Note 3)
all outputs open Vee = 5V
I
Vee = Max.
Vec=5V±5%
Vee = 5V, VIN = OV
3.0
2.0
-0.3
-100
-1
Vee=5V
0.8
-800
7
+1
V
V
V
J.lA
pF
J.lA
Vee=5V±5%
10H =-100J.lA
IOL=1.6mA
2.4
-0.3
0.4
V
V
IOH =-75J.1A
IOL=400J.lA
2.4
-0.3
0.4
V
V
IOH =-10J.lA
IOL= 10J.lA
Vec- 1
-0.3
0.2
V
V
Vee=6V
VOH =2.0V
Vee=5V
2.5
-2.5
Allowable Sink Current
Per Pin (L, D, G)
Per Pin (All Others)
Per Port (L)
Per Port (D, G)
Allowable Source Current
Per Pin (L)
Per Pin (All Others)
3-18
14
+2.5
mA
10
2
16
10
mA
mA
mA
mA
-15
-1.5
mA
mA
J.lA
o
COP302/COP302M
DC Electrical Characteristics
Parameter
Operation Voltage
Power Supply Ripple
Supply Current
Input Voltage Levels
CKI Input Levels
Crystal Input
Logic High
Logic Low
Schmitt Trigger Input
RESET
Logic High
Logic Low
All Other Inputs
Logic High
Logic High
Logic Low
Input Load Source Current
Input Capacitance
Hi-Z Input Leakage
Output Voltage levels
D, G, L, SK, SO Outputs
TTL Operation
Logic High
Logic Low
IPO-IP7, P8, P9, SKIP, CKO,
ADIDATA
Logic High
Logic Low
CMOS Operation
Logic High
Logic Low
Output Current Levels
LEU Uirect Urive (vUI-';jUZ)
Logic High
CKI Sink Current (RIC Option)
CKO (RAM Supply Current)
TRI·STATE® (COP302M) Leakage Current
o"'tJ
!;
-40°C" TA" +85°C, 4.5V " Vee" 5.5V unless otherwise noted.
Conditions
Min.
Max.
Units
4.5
5.5
peak to peak (Note 3)
0.4
V
V
TA = -40°C, outputs open
50
mA
2.4
-0.3
0.3
V
V
0.7Vee
-0.3
0.4
V
V
Vee = Max.
Vec=5V±5%
Vee = 5V, VIN = OV
3.0
2.2
-0.3
-100
-2
Vee=5V
V
V
V
0.6
-800
7
"A
pF
+2
"A
Vee=5V±5%
IOH =-75"A
IOL= 1.6mA
2.4
-0.3
0.4
V
V
IOH =-75"A
IOL=400"A
2.4
-0.3
0.4
V
V
IOH =-10"A
IOL= 10"A
Vcc- 1
-0.3
0.2
V
V
vee = ov (NOte
VOH=2.0V
VIN =3.5V
VR=3.3V
4)
I
1.0
2
-5
Vce=5V
A'iowable Sink Current
Per Pin (L, D, G)
Per Pin (All Others)
Per Port (L)
Per Port (D, G)
Allowable Source Current
Per Pin (L)
Per Pin (All Others)
3-19
12
4
+5
mA
mA
mA
"A
10
2
16
10
mA
mA
mA
mA
-15
-1.5
mA
mA
~
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~
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s:
,-
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o
CO)
D..
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AC Electrical Characteristics
COP402/COP402M o·c ~TA'; 70·C, 4.5V ~vcc ';6.3V unless otherwise noted.
COP302/COP302M
-40·C ~TA ';+85·C, 4.5V ~Vcc ~5.5V unless otherwise noted.
Parameter
Conditions
N
oCO)
Instruction Cycle Time
D..
Operating CKI Frequency
.;.16 mode
CKI Duty Cycle (Note 1)
Rise Time
Fall Time
Freq.=4MHz
Freq. =4MHz
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C\I
iD..
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~
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Inputs:
SI
tSETUP
tHOLO
All Other Inputs
tSETUP
tHOLO
Output Propagation Delay
Min.
Units
4
10
j.ts
1.6
4.0
MHz
40
60
60
40
%
ns
ns
0.3
250
j.ts
ns
1.7
300
j.ts
ns
Test Conditions:
RL = 5k, CL = 50 pF, VOUT = 1.5V
SO and SK
tpd1
tpdQ
CKO
tpd1
tpdQ
ADIDATA, SKIP
tpd1
tpdQ
All Other Outputs
tpd1
tpdQ
MICROBUSTM Timing
Max.
1.0
1.0
j.ts
j.ts
0.2~
0.25
j.ts
j.ts
0.6
0.6
j.ts
j.ts
1.4
1.4
j.ts
j.ts
375
250
ns
ns
ns
ns
ns
700
ns
ns
ns
ns
ns
ns
CL =100pF, Vcc=5V±5%
Read Operation (Figure 4)
Chip Select Stable before RD-tCSR
Chip Select Hold Time for RD-tRcs
RD Pulse Width-tRR
Data Delay from RD-tRo
RD to Data Floating-toF
65
20
400
Write Operation (Figu're 5)
Chip Select Stable before WR-tcsw
Chip Select Hold Time for WR-twcs
WR Pulse Width-tww
Data Set·Up Time for WR-tow
Data Hold Time for WR-two
INTR Transition Time from WR-twi
65
20
400
320
100
Note 1: Duty cycle = tW1/(tW1 +tWQ).
Note 2: See Figure 9 for additional I/O characteristics.
Note 3: Voltage change must be less than 0.5 volts in alms period.
Note 4: Exercise great care not to exceed maximum device power dissipation limits when direct driving LEOs (or sourcing similar
loads) at high temperature.
J
3-20
0
0
00
CKO
40
CKI
39
01
IP4
3B
02
RESET
37
03
IP3
36
IP5
IP2
35
PB
IP1
34
PO
IPO
33
AD/DATA
32
SKIP
31
G3
IP7
CQP402
IP6
10
L7
11
30
G2
L6
12
20
G1
L5
13
2B
GO
L4
14
27
IN3
INI
15
26
INO
IN2
16
25
SK
Vee
17
24
SO
COP402M
"tI
J:o.
0
~
0
0
"tI
J:o.
0
N
s:
0
0
"tI
(,.)
0
~
0
0
L3
18
23
SI
L2
19
22
GNO
Ll
20
21
LO
"tI
(,.)
0
N
s:
Order Number COP402N, COP402MN
NS Package N40A
Figure 2. Connection Diagram
Pin
Description
Description
Pin
. ADIDATA Address outldata in flag
LrLo
B bidirectional 1/0 ports with TRI·STATE®
G3 -G O
4 bidirectional 1/0 ports
SKIP
Instruction skip output
0 3 -0 0
4 general purpose outputs
CKI
System oscillator input
IN3-INo
4 general purpose inputs
CKO
System oscillator output
SI
Serial input (or counter input)
RESET
System reset input
SO
Serial output (or general purpose output)
SK
Logic·controlled clock (or general purpose
output)
Vee
Power supply
GND
Ground
IP7-IPO
B bidirectional ROM address and data ports
PB, pg
2 most Significant ROM address outputs
I
l-______~~4'!11f&jW1il~;oH---------~--.~m
=""""","VO,,,L~
-- tpDO
G3- GO, 03- 00, _ _
L7-LJu~~u~~
--
tPDO
1"""-
I
SKIP OUTPUT
"';'Wk;;'W;"ffi"'WI"';'W"'WI";'/~-.....! _ _ _ _ _ _ _
'PD1-!
P9, PB,IP7-IPO
OUTPUTS; _ _ _ _...I_r.rt_IIIII<_:i.:i.r.rt.IlI._IlI._
- ,
POO-
1~'sETUP- I-'HOLD
'tJp-J1'~ _ _#;/,iI#MWW$_. .~mWm~'"0im:~'"'Wd?'"'I0'"'!0'"'WII'"'~'"0i"'wII""%
Figure 3a. Input/Output Timing Diagrams (Crystal + 16 Mode)
~I~I
CKI
CKoivW
,pol-I r-
-I
!---'PDO
Figure 3b. CKO Output Timing
3-21
_ _ _ _ __
rt1IIII
e-
:::i:
~
C")
(lNzl
CS
.1
Il.
o
IRR
"
~
Il.
Figure 4. MICROBUSTM Read Operation Timing
o
o
.. I~tcsw--- . .
::E
(lNzl
cs
~
tlJ'JW
• --- twcs---I
I
\.
_tDW _ _
-
Il.
o
~oo
IWI
(Gol
INTR
twD
.1_
. I
{'------
Figure 5. MICROBUSTM Write Operation Timing
Functional Description
A block diagram of the COP402 is given in Figure 1.
Data paths are illustrated in simplified form to depict
how the various logic elements communicate with
each other in implementing the instruction set of the
device. Positive logic is used. When a bit is set, it is a
logic "1" (greater than 2 volts). When a bit is reset, it
is a logic "0" (less than o.a volts).
or from the Q latches or loaded from the L ports. RAM
addressing may also be performed directly by the
LDD and XAD instructions based upon the 6-bit
contents of the operand field of these instructions.
The Bd register also serves as a source register for
4-bit data sent directly to the 0 outputs.
Program Memory
Internal Logic
Program Memory consists of a 1,024·byteexternal
memory (typically PROM). Words of this memory may
be program instructions, program data or ROM
addressing data. Because of the special character·
istics associated with the JP, JSRP, JID and LQID
instructions, ROM must often be thought of as being
organized into 16 pages of 64 words each.
The 4-bit A register. (accumulator) is the source and
destination register for most I/O, arithmetic, logic
and data memory access operations. It can also be
used to load the Br ahd Bd portions of the B register,
to load and input 4 bits of the a-bit Q latch data, to
input 4 bits of the a·bit L I/O port data and to perform
data exchanges with the SIO register.
ROM addressing is accomplished by a 10·bit PC
register. Its binary value selects one of the 1,024 a·bit
words contained in ROM. A new address is loaded
into the PC register during each instruction cycle.
Unless the instruction is a transfer of control instruc·
tion, the PC register is loaded with the next
sequential 10·bil binary count value. Three levels of
subroutine nesting are implemented by the 10·bit
subroutine save registers, SA, SB and SC, providing a
last·in, first·out (LIFO) hardware subroutine stack.
A 4·bil adder performs the arithmetic and logic func·
tions of the COP402/402M, storing its results in A. It
also outputs a carry bit to the 1-bit C register, most
often employed to indicate arithmetic overflow. The
C register, in conjunction with the XAS instruction
and the EN register, also serves to control the SK
output. C can be outputted directly to SK or can
enable SK to be a sync clock each instruction cycle
time. (See XASinstruction and EN register descrip·
tion, below.)
.
ROM instruction words are fetched, decoded and
executed by the Instruction Decode, Control and
Skip Logic circuitry.
Four general·purpose inputs, IN 3 -IN o, are provided;
IN"IN 2 and IN3 may be selected, by a mask-programmable option, as Read Strobe, Chip Select and Write
Strobe inputs, respectively, for use in MICROBUSTM
applications.
Data Memory
Data memory consists of a 256·bit RAM, organized as
4 data registers of 16 4·bit digits. RAM addressing is
implemented by a 6·bit B register whose upper 2 bits
(Br) select 1 of 4 data registers and lower 4 bits (Bd)
select 1 of 16 4·bit digits in the selected data register.
While the 4·bit contents of the selected RAM digit (M)
is usually loaded into or from, or exchanged with, the
A register (accumulator), it may also be loaded into
The D register provides 4 general-purpose outputs
and is used as the destination register for the 4·bit
contents of Bd.
The G register contents are outputs to 4 generalpurpose bidirectional I/O ports. Go may be maskprogrammed as a "ready" output for MICROBUSTM
applications.
3-22
(")
a
Register shifting left each instruction cycle time.
The data present at SI goes into the least
significant bit of SIO. SO can be enabled to output
the most significant bit of SIO each cycle time.
(See 4 below.) The SK output becomes a logiccontrolled clock.
The
register is an internal, latched, B-bit register,
used to hold data loaded to or from M and A, as well
as B-bit data from ROM. Its contents are output to the
L I/O ports when the L drivers are enabled under
program control. (See LEI instruction.) With the
MICROBUSTM option selected, Q can also be loaded
with the B-bit contents of the L I/O ports upon the
occurrence of a write strobe from the host CPU.
2. With ENl set the INl input is enabled as an interrupt input. Immediately following an interrupt, ENl
is reset to disable further interrupts.
The 8 L drivers, when enabled, output the contents of
latched Q data to the L I/O ports. Also, the contents
of L may be read directly into A and M. As explained
above, the MICROBUSTM option allows L I/O port data
to be latched into the Q register. L I/O ports can be
directly connected to the segments of a multiplexed
LED display (using the LED Direct Drive output configuration option) with Q data being outputted to the
Sa-Sg and decimal point segments of the display.
3. With EN2 set, the L drivers are enabled to output
the data in Q to the L I/O ports. Resetting EN2
disables the L drivers, placing the L I/O ports in a
high-impedance input state. If the MICROBUSTM
option is being used, EN2 does not affect the L
drivers.
4. ENs, in conjunction with EN o, affects the SO
output. With ENo set (binary counter option
selected) SO will output the value loaded into ENs.
With ENo reset (serial shift register option
selected), setting ENs enables SO as the output of
the SIO shift register, outputting serial shifted
data each instruction time. Resetting ENs with the
serial shift register option selected disables SO as
the shift register output; data continues to be
shifted through SIO and can be exchanged with A
via an XAS instruction but SO remains reset to
"0." The table below provides a summary of the
modes associated with ENs and ENo.
The 510 register functions as a 4-bit serial-in/serialout shift register or as a binary counter depending on
the contents of the EN register. (See EN register
description, below.) Its contents can be exchanged
with A, allowing it to input or output a continuous
serial data stream. SIO may also be used to provide
additional parallel I/O by connecting SO to external
serial-in/parallel-out shift registers.
The XAS instruction copies C into the SKL latch. In
the counter mode, SK is the output of SKL. In the
shift register mode, SK outputs SKL ANDed with
internal instruction cycle clock.
The EN register is an internal 4-bit register loaded
under program control by the LEI instruction. The
state of each bit of this register selects or deselects
the particular feature associated with each bit of the
EN register (EN s- EN o).
a. The interrupt, once acknowledged as explained
below, pushes the next sequential program
r.nllntpr :=!rlrlrp~~
IPr, . . . . 1\ nntn tho
~t!:l .... k
"I.chin"
in turn the contents of the other subroutine-save
registers to the next lower level (PC + 1 ~ SA ~
SB ~ SC). Any previous contents of SC are lost.
The program counter is set to hex address OFF
(the last word of page 3) and ENl is reset.
Bits ENs and ENo
EN3
ENo
510
51
SO
SK
0
0
Shift Register
Input to Shift Register
0
If SKL = 1, SK = SYNC
If SKL = 0, SK = 0
Input to Shift Register
Serial Out
If SKL
If SKL
0
Binary Counter
Input to Binary Counter
0
Input to Binary Counter
If SKL
If SKL
3-23
= 1, SK = SYNC
= 0, SK = 0
If SKL = 1, SK = 1
If SKL
Binary Counter
o
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o
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w
o
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w
o
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Interrupt
Enable Register Modes -
Shift Register
.j::o,
The following features are associated with the INl
interrupt procedure and protocol and must be
considered by the programmer when utilizing intertupts.
1. The least significant bit of the enable register,
EN o, selects the SIO register as either a 4-bit shift
register or a 4-bit binary counter. With ENo set, SIO
is an asvnchronous binarv counter. decremenfinn
its value by one upon each low-going pulse ("1" to
"0") occurring on the SI input. Each pulse must be
at least two instruction cycles wide. SK outputs
the value of SKL. The SO output is equal to the
value of ENs. With ENo reset, SIO is a serial shift
0
o"tJ
= 0, SK = 0
= 1, SK = 1
= 0, SK = 0
i ..
C
system for S·bit parallel data transfer between MOSI
LSI CPUs and interfacing devices. (See MICROBUSTM,
National Publication.) The functioning and timing relationships between the COP402M signal lines affected
by this option are as specified for the MICROBUSTM
Interface, and are given in the AC electrical characteristics and shown In the timing diagrams (Figures 4
and 5). Connection to the MICROBUSTM is shown in
'
. Figure 6.
b. An Interrupt will be acknowledged only after the
following conditions are met:
1. EN 1 has been set.
2. A low·going pulse ("1" to "0") at least two
Instruction cycles wide occurs on the IN1 input.
3. A currently executing instruction has been
·completed.
4. All s~ccessiv~ transfer of control Instructions
and successive LBls have been completed (e.g.,
if the main program is executing a JP instruction
which transfers program control to another JP
instruction, the interrupt will not be acknowl·
edged until the second JP instruction has been
executed.
POWER
TY YOj
INTERRUPT IINTRI
c. Upon acknowledgement of an interrupt, the skip
logic status is saved and later restored upon the
popping of the stack. For example, if an interrupt
occurs during the execution of ASC (Add with
Carry, Skip on Carry) instruction which results in
carry, the skip logic status is s'aved and program
control is transferred to the interrupt servicing
routine at hex address OFF. At the end of the
interrupt routine, a RET instruction is executed to
"pop" the stack and return program contrQI to the
instruction following the original ASC. At this
time, the skip logic is enabled and skips this
instruction because of the previous ASC carry.
Subroutines and the LaiD instruction should not
be nested within the interrupt servicing routine
since their popping of the stack enables any
previously saved main program skips, interfering
with the orderly execution of the interrupt routine.
MICROPROCESSOR
Go
... a·BIT DATA BUS
00-07
.
LO-L7
READ STROBE (Ali)
IN1
COP40ZM
r.:::CH:::IP~SE,::,:L;;;EC:::T~(C'i;;SI~·IINZ
WRITE STROBE (WRI
INJ
t
Figure 6. MICROBUSTM Option Interconnect
Initialization
The Reset Logic will Initialize (clear) the device upon
power-up if the power supply rise time is less than
1ms and greater than 1!-,s. If the power supply rise
time is greater than 1ms, the user must provide an
external RC network and diode to the RESET pin as
shown below. The RESET pin is configured as a
Schmitt trigger input.· If not used it should be
connected to Vee. Initialization will occur whenever a
logic "0" is applied to the RESET input, provided it
stays low for at least two instruction cycle times.
d. The first Instruction of the interrupt routine at hex
address OFF must be a NOP.
e. A LEI instruction can be put immediately before
the RET to re·enable interrupts.
MICROBUS™ Interface
The COP402M can be used as a peripheral micro·
processor device, inputting and outputting data from
and to a host microprocessor (!-,P). INh IN 2, and IN3
general purpose inputs become MICROBUSTM com·
patible read·strobe, chlp·select, and write·strobe
lines, r~spectively. IN1 becomes RD - a logic "0" on
this Input will cause a latch data to be enabled to the
L ports for input to the !-,P. IN2 becomes CS - a logic
"0" on this line selects the COP402M as the !-,P
peripheral device by enabling the operation of the RD
and WR lines and allows for the selection'of one of
several peripheral components. IN3 becomes WR a logic "0" on this line will write bus data from the L
ports to the a latches for input to the COP402M. Go
becomes INTR, a "ready" output reset by a write
pulse from the !-,P on theWR line, providing the
"handshaking" capability necessary for asynchro·
nous data transfer between' the host CPU and the
COP402M.
Upon initialization, the PC register is cleared to 0
(ROM address 0) and the A, B, C, D, EN, G, and SO are
cleared. The SK output is enabled as a SYNC output,
providing a pulse each instruction eycle time. Data
Memory (RAM) is not cleared upon Initialization. The'
first instruction at address 0 must be a CLRA.
This option has been designed for compatibility with
National's MICROBUSTM - a standard interconnect
Figure 7. Power·Up Clear Circuit
P + - . -....- - - - . ,
~
~
s·
.
~ ~~
~
VCC
COP40Z/40ZM
---- ..... RESET
U
r
P
GNO
y_ ......_ - - - -....I
RC" 5. POWER SUPPLY RISE TIME
3-24
(')
o"C
Oscillator
There are two basic clock oscillator configurations
available as shown by Figure B.
~
P9
-PB
a. Crystal Controlled Oscillator. CKI and CKO are
connected to an external crystal. The instruction
cycle time equals the crystal frequency divided
by 16.
;--
~
o"C
COP402
AO/OATA
1P7 - 1Po
I"
B
b. External Oscillator. CKI is driven by an external
clock signal. The instruction cycle time is the
clock frequency divided by 16.
~ICLK
g
~
[lATA
'('
~
(')
0
I
LATCH
0
B
(.,)
A
~ a
~;.CKO
AO·A7
00·07
L..-.,.. CE
R2
_AB
...f1..J
NOT USEO
o
MEMORY
A9
EXTERNAL
o
"C
CLOCK
§
(')
o"C
(.,)
C
I\)
s:
Figure 9. External Memory Interface to COP402
Crystal
Value
4MHz
R1
Component Values
R2
C
1k
1M
Input/Output
27pF
3.5BMHz
1k
1M
27pF
2.09MHz
1k
1M
56pF
COP402 outputs have the following configurations,
illustrated in Figure 9:
a. Standard - an enhancement·mode device to
ground in conjunction with a depletion·mode
device to Vee, compatible with TIL and CMOS
input requirements.
Figure 8. COP402l402M Oscillator
b. High Drive - same as a. except greater current
sourcing capability.
External Memory Interface
c. Push· Pull - an enhancement·mode device to
oround in coni unction with a depletion·mode
device paralleled by an enhancement·mode device
to Vee. This configuration has been provided to
allow for fast rise and fall times when driving
capacitive loads.
The COP402 and COP402M are designed for use with
an external ~rogram IVlemory. I nls melTlury "lay ut:
implemented using any devices having the following
characteristics:
1. random addressing
2. TTL·compatible TRI·STATE® outputs
d. LED Direct Drive - an enhancement·mode device
to ground and to Vce , meeting the typical current
sourcing requirements of the segments of an LED
display. The sourcing device is clamped to limit
current flow. These devices may be turned off
under program control (see Functional Descrip·
tion, EN Register), placing the outputs in a high·
impedance state to provide required LED segment
blanking for a multiplexed display.
3. TTL·compatible inputs
4. access time =1.0I-'s, max.
Typically these requirements are met using bipolar or
MaS PROMs.
During operation, the address of the next instruction
is sent out on P9, PB, and IP7 through IPO during the
time that ADIDATA is high (logic "1" = address
mode). Address data on the IPlines is stored into an
external latch on the high·to·low transition of the
ADIDATA line; P9 and PB are dedicated address
outputs, and do not need to be latched. Wh.en
ADIDATA is low (logic "0" = data mode), the output
of the memory is gated onto IP7 through IPO, forming
the input bus. Note that the ADIDATA output has a
period of one instruction time, a duty cycle of approx·
imately 50%, and specifies whether the IP lines are
used for address output or instruction input. A sim·
plified block diagram of the external memory inter·
face is shown in Figure 9.
e. TRI·STATE® Push· Pull - an enhancement·mode
device to ground and Vce intended to meet the
requirements associated with the MICROBUSTM
option. These outputs are TRI·STATE® outputs,
allowing for connection of these outputs to a data
bus shared by other bus drivers.
/. Inputs have an on·chip depletion load device to
Vee, as shown in Figure 101.
The above input and output configurations share
common enhancement·mode and depletion·mode
devices. Specifically, all configurations use one or
3-25
E
C
:!:
C\I
o
('f)
a..
o()
N
o
('f)
a..
o()
:!:
~
a..
o
~
o
o::t
a..
o()
more of six devices (numbered 1-6, respectively).
Minimum and maximum current (lOUT and VOUT)
curves are given in Figure 10 for each of these
devices.
The following information is provided to assist the
user in understanding the operation of several
unique instructions and to provide notes useful to
programmers in writing programs.
The SO,SK outputs are configured as shown in
Figure 10c. The D and G outputs are configured as
shown in Figure 10a. Note that when inputting data
to the G ports, the G outputs should be set to "1." The
L outputs are configured as in Figure 10d on the
COP402. On the COP402M th.e L outputs are as in
figure 10e.
XAS Instruction
XAS (Exchange A with SIO) exchanges the 4·bit contents of the accumulator with the 4-bit contents of
the SIO register. The contents of SIO will contain
serial·in/serial-out shift register or binary counter
data, depending on the value of the EN register. An
XAS instruction will also affect the SK output. (See
Functional Description, EN Register, above.) If SIO is
selected as a shift register, an XAS instruction must
be performed once every 4 instruction cycles to
effect a continuous data stream.
An important point to remember if using configuration d with the L drivers is that even when the L
drivers are disabled, the depletion load device will
source a small amount of current. (See Figure 11.)
IP7 through IPO outputs are configured as shown in
Figure 10c; P9, P8, SKIP, and ADIDATA are configured
as shown in Figure 10b.
J I D Instruction
COP402/402M Instruction Set
•
JID (Jump Indirect) is an indirect addressing instruction, transferring program control to a new ROM
location pointed to indirectly by A and M. It loads the
lower 8 bits of the ROM address register PC with the
contents of ROM addressed by the 10·bit word, PCg:s,
A, M. PCg and PCs are not affected by this instruc·
tion.
Table 1 is a symbol table providing internal architec·
ture, instruction operand and operational symbols
used in the instruction set table.
Table 2 provides the mnemonic, operand, machine
code, data flow, skip conditions and description
associated with each instruction in the COP402/402M
instruction set.
Note that JID requires 2 instruction cycles.
~~
~~a. Standard
b. High Drive
c. Push·Pull
'"."'~~
d. LED
e. TRI·STATE@ Push·Pull
1.o.IS DEPLETION DEVICE)
Figure 10. Input/Output Configurations
3-26
f. Input with Load
Depletion Load OFF
Source Current
Output Sinl' Current
15rTTr~---r~---'~--,
Standard Output Source
Current
-2.0
-0.4
r---,--,--,----,--,----,--,
-1.75 f---t---j---j---j--t---j---j
-D.)
10
!
1\
\
MIfJ
1
1\ MAX
-'\1
,,~--P""-r-j--+---I--1
-0.5 1oo---f'~~1l-'~++---t---j
!
-0.25 r--F"-W--"'~-tI-"""';j---j--1
VOUT (VOLTS)
VOUT (VOLTS)
DEVICE 1
Push· Pull Source Current
...--r---,-r----,-r----,---,
-20
1
-18
1
-16
VCCj 6.3jMAX)
-2
-6
~
.sr-
.§
~
1c---+"--+--'I!----i--f--+_--1
"
-1
-1
1\
\
\
\
VCC r·5V
(MIN)
rt--
VCC = 6.3V
(MIN)
I
I I
-t-V~C=4\V
\ (MAX) '{
1\ ~ ~J
~
-12
~
-10
.s
-8
-6
-4
-2
4
Your (VOLTS)
DEVICE 2h
/
V
VOUT (VOLTS)
DEVICE 3
I
1'\.
I
~ Vcc = 6.3V (MAX)
J':,.
-14
I--
DEVICE 2
LED Output Source Current
-)
-6 f--'tt--j
-4
k---t-"""-i""----'1;'---j--,--j---j
- -0.75
\{
DEVICE 1
High Drive Source Current
~
~ -1.0
5
VOUT (VOLTS)
<
-1.25 1--''<+--+----i--j--+---I--1
E
~
-10
~
I
-0. 1
3
-1.5 k--+"----'j-'---I---j--t---j---j
T
[v.-
~
\
Vcc = 4.5V (MAX)
1
L\
-
Vcc = 4.5V (MIN)
X
\
~
f""'"" """'<
L
1
1
L
'<:::t:S
1
Vcc = 6.3V (MINI
I
L'-J. J
VOUT (VOL TS)
DEVICE 4
C
G
TRI·STATE'
Output Source Current
LED Output Direct LED Dri'le
Input Load Source Current
-lnr-·r-~-r-.-r-._,--r_r--
-16
-15
-14
-12
1 -10
~
.sr-
r-
~
"
-10
~
-8
"
-6
-5
-4
-2
O.
4
4.5
5.5
VCC (VOLTS)
6.5
DEVICE 4
VOUT (VOLTS)
DEVICE 5
Figure 11. COP402/COP402M Input/Output Characteristics
3-27
VDUT (VOLTS)
DEVICE 6
:iE
C\I
15
D..
C")
D..
0
0
~
VCC = 5.5V (MAX)
I
I
t- VCC = 4.5V (MAX)
0
0
N
0
L OUTPUT DEPLETION LOAD OFF
SOURCE CURRENT
OUTPUT SINK CURRENT
0
C")
l-
1'10
y
~
!2
<- -0.4
//TC=r(T-
g<-
g
~
-0.2
,'II
:Ii
~
-0.3
!2
VCC = 4.5V (MINI)
-0.1
'lilt
NAX
~NJ\
1,
4
D..
VOUT (VOLTS)
0
0
VOUT (VOLTS)
DEVICE 1
STANDARD OUTPUT SOURCE CURRENT
N
0
-1.75
D..
-1.5
'lilt
0
0
-1.25
!
...
-1.0
VCC
"<
1\
\
§-D.75
-0.5
-0.25
PUSH PULL SOURCE CURRENT
-3.0
J
5.5V iMAX)
\ \
-2.5
l1\ \ V
\/
:>
!2
I\. 1\
-1.0
:\ '\ l/CC = 4.5V (MIN)
VCC =4.5V\
- 0.5 (MIN)I
- L"
7-
r-:::-- II... ~ ~
3
4
VOUT (VDLTS)
VCC J.5V
(MAX'c
l~
i
-;: -1.5
\
VCCXIi 5.5V
(MAX
\
-2.0
rxVCC - 4.5V (MAi)
VCC =5.5V
~
DEVICE 2
VCC =5.5V
(MIN)
I\" , ~
['..
2
4
3
VOUT (VOLTS)
DEVICE 2
LED OUTPUT DEVICE LED DRIVE
I
LED OUTPUT SOURCE CURRENT
-14
/
-12
II
MAX
-10
<'
g
...
/
-8
1/
:>
!2
-6
I'
I
-4~~-{--r~~--r.--+--,
-4
-2
4
VDUT (VOLTS)
DEVICE 2 AND 3
5
DEVICE 4 AND 2
o
VOUT= 2.0V
I
....... ~
4.0
TRISTATE OUTPUT SOURCE CURRENT
I
I
4.5
.-
V
5.0
VCC (VOLTS)
5.5
6.0
DEVICE 4 AND 2
INPUT LOAD SOURCE CURRENT
-15
!2
-5
-0.2 r----t--+---"'~i"'io;:___j____j
2
4
VDUT (VOLTS)
3
4
VOUT (VOLTS)
DEVICE 5
Figure 11 a. COP302/COP302M Input/Output Characteristics
3-28
DEVICE 6
o
o"'tJ
Table 1. COP402/COP402M Instruction Set Table Symbols
~
o
Symbol
IN
L
M
P
PC
Q
SA
SB
SC
SIO
SK
o
INSTRUCTION OPERAND SYMBOLS
INTERNAL ARCHITECTURE SYMBOLS
A
B
Br
Bd
C
D
EN
G
IL
~
Definition
Symbol
Delinition
4·bit Accumulator
6·bit RAM Address Register
Upper 2 bits of B (register address)
Lower 4 bits of B (digit address)
1·bit Carry Register
4·bit Data Output Port
4·bit Enable Register
4·bit Register to latch data for G 1/0 Port
Two 1·bit Latches Associated with the IN3 or
INa inputs
4·bit Input port
a·bit TRI·STATE® 1/0 Port
4·bit contents of RAM Memory pointed to by
B Register
2·bit ROM Address Port
10·bit ROM Address Register (program
counter)
a·bit Register to latch data for L 1/0 Port
10·bit Subroutine Save Register A
10·bit Subroutine Save Register B
10·bit Subroutine Save Register C
4·bit Shift Register and Counter
Logic·Controlled Clock Output
d
4·bit Operand Field, 0-15 binary (RAM Digit
Select)
r
2·bit Operand Field, 0-3 binary {RAM Register
Select)
a
9·bit Operand Field, 0- 511 binary (ROM
Address)
y
4·bit Operand Field, 0-15 binary (Immediate
Data)
RAM{s) Contents of RAM location addressed by s
ROM{t) Contents of ROM location addressed by t
o"'tJ
~
oI\)
s:
o
o"'tJ
Co)
o
~
o
o"'tJ
Co)
oI\)
s:
OPERATIONAL SYMBOLS
+
-
--
=
A
Plus
Minus
Replaces
Is exchanged with
Is equal to
The one's complement of A
Ell
Exclusive·OR
:
Range of val ues
Table 2. COP402/402M Instruction Set Table (Note 1)
Machine
Mnemonic Operand
Mex
Code
Language ,",oat!
(Binary)
Data Flow
Skip Conditions
Description
ARITHMETIC INSTRUCTIONS
ASC
30
10011100001
A + C + RAM (B) - A
Carry - C
Carry
Add with Carry, Skip on
Carry
ADD
31
10011100011
A+RAM(B)- A
None
Add RAM to A
ADT
4A
101 0011 0 1 01
A+1010- A
None
Add Ten to A
5-
y
10101 1
A+y- A
Carry
Add Immediate, Skip on
Carry (y 0)
CASC
10
10001100001
A+RAM(B)+C - A
Carry - C
Carry
Complement and Add with
Carry, Skip on Carry
CLRA
00
10000100001
O-A
None
Clear A
COMP
40
10100100001
A-A
None
One's complement of, A to A
NOP
44
10 1 0010 1 001
None
None
No Operation
RC
32
10011100101
"O"-C
None
Reset C
SC
22
1001 01 001 01
"1"- C
None
Set C
XOR
02
10000100101
A", RAM(B) - A
None
Exclusive·OR RAM with A
AISC
Y
I
3-29
*
,-
Table 2. COP402/COP402M Instruction Set Table (continued)
Hex
Code
Mnemonic Operand
Machine
Language Code
(Binary)
Data Flow
Skip Conditions
Description
TRANSFER OF CONTROL INSTRUCTIONS
JID
JMP
JP
a
FF
11111111111
ROM (PC9:S, A,M) - PC7:0 None
J~mp
6-
101101001"9:81
a- PC
None
Jump
--
I
a - PC6:0
None
Jump within Page (Note 4)
--
a
I
I
(pages 2,3 only)
Indirect (Note 3)
a7:0
III
a6:0
or
-JSRP
a
JSR
a
I
a - PC5:0
1111 a5:0
(all other pages)
--
1101
I
PC+ 1 - SA - SB - SC
0010 - PCg:6
a - PC5:0
None
Jump to Subroutine Page
(Note 5)
PC + 1 - SA - SB - SC
a- PC
None
Jump to Subroutine
a5:0
6-
1011 011 01"9:81
--
I
RET
48
101 OOp 0001
SC - SB - SA - PC
None
Return from Subroutine
RETSK
49
10100110011
SC - SB - SA - PC
Always Skip on Return
Return from Subroutine
then Skip
A- 07:4
RAM (B) - 03:0
None
Copy A, RAM to 0
07:4 - RAM(B)
03:0- A
None
Copy 0 to RAM, A
-
I
a7:0
MEMORY REFERENCE INSTRUCTIONS
CAMO
COMA
LD
r
LDD
r,d
5MB
100111°0111
10011111001
33
1°011100111
2C
10010111001
-5
1° 01 r 10 1 ° 11
RAM(B)-A
Bre r - Br
None
Load RAM into A,
Exclusive·OR Br with r
RAM(r.d)-A
None
Load A with RAM pointed
to directly by r,d
23
100 1 °100 1 11
--
1001 r
I
BF
11011111111
ROM(PC9:S,A,M) - 0
SB-SC
None
Load 0 Indirect (Note 3)
0
4C
10100111001
0- RAM(B)O
None
Reset RAM Bit
1
45
101 001 01 0 11
0- RAM(BI1
None
Set RAM Bit
LOID
RMB
33
3C
d
I
2
42
1010 010 01 01
0- RAM(B)2
3
43
10100100111
0- RAM(B)3
0
40
10100111011
1 - RAM(B)O
1
47
10100111011
1 - RAM(BI1
2
46
101 001 011 01
1- RAM(B)2
3
4B
1010°110111
1- RAM(B)3
3-30
(')
o"'D
Table 2. COP402/COP402M Instruction Set Table (continued)
J:o,
Mnemonic Operand
Hex
Code
o
~
Machine
Language Code
(Binary)
Data Flow
Description
Skip Conditions
MEMORY REFERENCE INSTRUCTIONS (continued)
(')
o"'D
J:o,
o
STII
y
7-
10 1111
I
y - RAM (B)
Bd+l-Bd
None
Store Memory Immediate
and Increment Bd
N
X
r
-6
1001 r 101101
RAM(B)- A
BrEll r - Br
None
Exchange RAM with A,
Exclusive·OR Br with r
(')
XAD
r,d
23
100 1 0100 111
RAM(r,d)- A
None
--
1101 r
Exchange A with RAM
pointed to directly by r,d
I
y
d
I
XDS
r
-7
1001 r 10 1111
RAM(B)- A
Bd-l - Bd
Br .. r - Br
Bd decrements past
a
Exchange RAM with A
and Decrement Bd,
Exclusive·OR Br with r
XIS
r
-4
1001 r 10 1001
RAM(B)- A
Bd+l- Bd
Br .. r - Br
Bd increments past 15
Exchange RAM with A
and Increment Bd,
Exclusive·OR Br with r
REGiSTER REFERENCE INSTRUCTIONS
CAB
50
10 1 a 1100001
A- Bd
None
Copy A to Bd
CBA
4E
10 1 001111 01
Bd - A
None
Copy Bd to A
--
10 01 r (d -1)1
(d -0, 9:15)
or
I
r,d- B
Skip until not a LBI
Load B Immediate with r,d
(Note 6)
LBI
LEI
r,d
y
XABR
33
100 11100 111
--
d
1101 r
(any d)
33
100 111 0011 1
10 11 01 y
y- EN
None
Load EN Immediate (Note 7)
612
10001100101
A - Br (0,0 - A3.A2)
-
None
Exchange A with Br
I
I
I
TEST INSTRUCTIONS
SKC
20
10010100001
C="I"
Skip if C is True
SKE
21
10010100011
A=RAM(B)
Skip if A Equals RAM
SKGZ
33
10011100111
G3:0=0
Skip if G is Zero (all 4 bits)
21
100 1 01000 11
33
100 111 0011 1
SKGBZ
SKMBZ
SKT
Skip if G Bit is Zero
1st byte
a
01
11
1""1""1
}
10001100011
2
03
10000100111
G2=0
3
13
10001100111
G3=0
a
01
10000100011
RAM(B)O=O
11
1000 11000 11
RAM(Blt =0
2
03
10000100111
RAM(B)2=0
3
13
10001100111
RAM(B)3=0
41
10100100011
A time·base counter
carry has occurred
since last test
GO=O
Gl=O
2nd byte
3-31
Skip if RAM Bit is Zero
Skip on Timer (Note 3)
s:
o"'D
Col
o
~
(')
o"'D
~
N
s:
:E
-N
0
Table 2. COP402/COP402M Instruction Set Table (continued)
C")
0..
0
Hex
Code
Machine
Language Code
(Binary)
0
Mnemonic Operand
0
INPUT/OUTPUT INSTRUCTIONS
0..
ING
N
C")
0
0
:i
N
IN IN
0..
INIL
0
"It
0
0
N
INL
0
"It
0..
0
OBD
0
y
OGI
33
10011100111
2A
10010110101
33
10011100111
28
10010110001
33
10011100111
29
10010110011
XAS
Skip Conditions
- None
G-A
Description
Input G Ports to A
IN-A
None
Input IN Inputs to A
(Notes 2 and 8)
IL3, "0", ILO - A
None
Input IL Latches to A
(Note 3)
None
Input L Ports to RAM,A
33
10011100111
L7:4 - RAM(B)
2E
10010111101
L3:0- A
Bd- D
None
Output Bd to D Outputs
33
10011100111
3E
1°011111101
33
1°°111°0111
y
1° 101 1
y-G
None
Output to G Ports Immediate
RAM(B)- G
None
Output RAM to G Ports
A - SIO, C - SKL
None
Exchange A with SIO
(Note 3)
5OMG
Data Flow
I
33
10011100111
3A
10011110101
4F
1°100111111
°
Note 1: All subscripts for alphabetical symbols indicate bit numbers unless explicitly defined (e.g., Br and Bd are explicitly defined). Bits are numbered to N
where signifies the least significant bit (Iow-order, right-most bit). For example, A3 Indicates the most significant (left-most) bit of the 4·blt A register.
°
Note 2: The IN IN Instruction Is not available on the 24'pln COP421 since this device does not contain the IN Inputs.
Note 3: For additional Information on the operation of the XAS, JID, LaiD, INIL, and SKT Instructions, see below.
Note 4: The JP Instruction allows a Jump, while In subroutine pages 2 or 3, to any ROM location within the two-page boundary of pages 2 or 3. The JP
Instruction, otherwise, permits a jump to a ROM location within the current 64·word page. JP may not Jump to the last word of a page.
Note 5: A JSRP transfers program control to subroutine page 2 (0010 is loaded Into the upper 4 bits of Pl. A JSRP may not be used when In pages 2 or 3. JSRP
may not Jump to the last word In page 2.
Note 6: LBlls a single-byte instruction If d = 0,9,10,11,12,13,14, or 15. The machine code for the lower 4 bits equals the binary value of the "d" data minus 1,
e.g., to load the lower four bits of B (Bd) with the val ue 9 (10012), the lower 4 bits of the LBI instruction equal 8 (10002). To load 0, the lower 4 bits of the LBI
Instruction should equal 15 (11112>.
'
Note 7: Machine code for operand field y for LEI Instruction should equal the binary value to be latched Into EN, where a "1" or "0" In each bit of EN
corresponds with the selection or deselection of a particular function associated with each bit. (See Functional Description, EN Register.)
Note 8: The COP402M will always read a "1" into AI with the ININ Instruction.
3-32
(')
o
INIL Instruction
not set. If the latch has been set since the previous
test, the next program instruction is skipped and the
latch is reset. The features associated with this
instruction, therefore, allow the controller to generate
its own time-base for real-time processing rather
than relying on an external input signal.
INIL (Input IL Latches to A) inputs 2 latches, IL3 and
ILa (see Figure 12) and CKO into A. The IL3 and ILa
latches are set if a low·going pulse ("1" to "a") has
occurred on the IN3 and INa inputs since the last INIL
instruction, provided the input pulse stays low for at
least two instruction times. Execution of an INIL
inputs IL3 and ILa into A3 and AO respectively, and
resets these latches to allow them to respond to subsequent low-going pulses on the IN3 and INa lines. If
CKO is mask programmed as a general purpose
input, an INIL will input the state of CKO into A2. If
CKO has not been so programmed, a "1" will be
placed in A2. A "a" is always placed in A1 upon the
execution of an INIL. The general purpose inputs
IN3-INa are input to A upon the execution of an ININ
instruction. (See Table 2, ININ Instruction.) INIL is
useful in recognizing pulses of short duration or
pulses which occur too often to be read conveniently
by an ININ instruction.
1
INOIINJ
Instruction Set Notes
o""0
c. The ROM is organized into 16 pages of 64 words
each. The Program Counter is a 10-bit binary
counter, and will count through page boundaries.
If a JP, JSRP, JID or LaID instruction is located in
the last word of a page, the instruction operates
as if it were in the next page. For example: a JP
located in the last word of a page will jump to a
location in the next page. Also, a LaiD or JID
located in the last word of page 3, 7,11, or 15 will
access data in the next group of 4 pages.
INll
Figure 12. INoI1N3 Latches
LQID Instruction
LaiD (Load a Indirect) loads the 8-bit a register with
the contents of ROM pointed to by the 10-bit word
PCg, PCa, A, M. LQID can be usea ror laDle IOOl\UfJ UI
code conversion such as 8CD to seven-segment. The
LQID instruction "pushes" the stack (PC + 1 - SAS8 - SC) and replaces the least significant 8 bits of
PC as follows: A - PC 7:4 , RAM(8} - PC 3:0 , leaving
PCg and PCa unchanged. The ROM data painted to by
the new address is fetched and loaded into the Q
latches. Next, the stack is "popped"(SC - S8 - SA
- PC), restoring the saved value of PC to continue
sequential program execution. Since LQID pushes
S8 - SC, the previous contents of SC are lost. Also,
when LQID pops the stack, the previously pushed
contents of S8 are left in SC. The net result is that
the contents of S8 are placed in SC (S8 - SC). Note
that LaID takes two instruction cycle times to
execute.
Typical Application: PROM·Based System
The COP402 may be used to exactly emulate the
COP420. Figure 12 shows the interconnect to implement a COP420 hardware emulation. This connection
uses two MM5204 EPROMs as external memory.
Other memory can be used such as bipolar PROM or
RAM.
Pins IP7 -IPO are bidirectional inputs and outputs.
When the ADIDATA clocking output turns on, the
EPROM drivers are disabled and IP7 -IPO output
addresses. The 8-bit latch (MM74C373) latches the
addresses to drive the memory.
When ADIDATA turns off, the EPROMs are enabled
and the IP7-IPO pins will input the memory data. P8
and P9 output the most significant address bits to
the memory. (SKIP output may be used for program
debug if needed.)
SKT Instruction
The SKT (Skip on Timer) instruction tests the state of
an internal 10-bit time-base counter. This counter
divides the instruction cycle clock frequency by 1024
and provides a latched indication of counter
overflow. The SKT instruction tests this latch,
executing the next program instruction if the latch is
The other .28 pins of the COP402 may be configured
exactly the same as a COP420. The COP402M chip
can be used if the MICR08USTM feature of the
COP420 is needed.
3-33
~
I\)
~
b. Although skipped instructions are not executed,
one instruction cycle time is devoted to skipping
each byte of the skipped instruction. Thus all
program paths take the same number of cycle times
whether instructions are skipped or executed,
except JID and LQID. LQID and JID take two cycle
times if executed and one if skipped.
ININ
o
For example, using a 2.097MHz crystal as the timebase to the clock generator, the instruction cycle
clock frequency will be 131 kHz (crystal frequency +
16) and the binary counter output pulse frequency
will be 128Hz. For time-of-day or similar real-time processing, the SKT instruction can call a routine which
increments a "seconds" counter every 128 ticks.
a. The first word of a program (ROM address a) must
be a CLRA (Clear A) instruction.
COP420
I
(')
o""0
~
~
3:
:::iE
~
(t)
D-
o()
~D-
o
()
Vee
:€
GNO
24
Lll
12
~
23
1
2
3
4
5
6
7
8
D-
o
~
iDo
()
19 16 15 12 9
20
Vee
---rl
5~
6
U8 07 U6 US U4 U3 U2 Ul
Vee
GNO
MM74e373
LE
OUTPUT DIS
08 07 06 05 04 03 02 01
18 17 14 13 8
7
4 l3
Vee
vpp
GNO
A8
A7
A6
AS
A4
A3
A2
Al
AD
MM2758
DR Y, OF
MM2716
06
17
-422
IP7
P8
SKIP
GNO
22
A9
05
16
04
15
10
9
35
.!.!L-
DE ~
IT lL-
07
~
AID
36
IP6
03
14
3
IPS
IP3
01
11
5
IP4
1
2
4
11
02
13
DO
10
6
9
7
IP2
8
IPI
33
AD/DATA
IPO
34
P9
40
39
38
37
31
COP402
l!!.-
r-ll
13
COP420
PINOUT
I
--
GNO CKO CKIRESET L7
11
2
3
4
5
L6
6
L5
14
L4
15
INI
16
I
17
IN2 Vcc
10 11
18
L3
12
19
L2
13
20
11
14
21
LO
15
23
SI
16
24
SO
17
25
SK
18
26
INO IN3
19 20
Figure 13. COP402 Used to Emulate a COP420
3-34
27
28
GO
21
29
Gl
22
G2
23
G3
24
03
25
02
26
01
27
DO
28
(")
o."
COP402 Mask Options
The following COP420 options have been implemented in this basic version of the COP402. Subsequent versions of
the COP402 will implement different combinations of available options; such versions will be identified as
COP402·A, COP402·B, etc.
Option Value
Option 1 = 0
Option 2
Option 3
Option 4
=0
=0
=0
Option 5 = 2 (402)
= 3 (402M)
Option 6
Option 7
Option 8
= 2,3
= 2,3
= 2,3
Comment
CKO is clock generator output to crystal
CKI is crystal input +16
(may be overridden externally)
L7 has LEO direct-drive output
L7 has TRI·STATE'" push·pull output
L6 same as L7
Option 11 = 0
Vee pin -
Option 12 = 2,3
L3 same as L7
L2 same as L7
= 2,3
L1 same as L7
Option 15 = 2,3
LO same as L7
Option 16 = 0
51 has load device to Vee
Option 17 = 2
SO has push-pull output
Option 18 = 2
SK has push-pull output
Option 19 = O'
INO has load device to Vec
Option 20 = 0 (402)
= 1 (402M)
IN3 has load device to Vee
Option 21 = 0
GO has standard output
G1 same as GO
=0
G2 same as GO
Option 24 = 0
G3 same as GO
Option 25 = 0
03 has standard output
Option 26 = 0
02 same as 03
Option 27 = 0
01 same as 03
Option 28 = 0
Option 29
Option 30
= 0 (402)
= 1 (402M)
= N/A
N
3:
Hi Z
Option 22 = 0
Option 23
ao
no option available
Option 13 = 2,3
Option 14
~
~
L4 same as L7
IN2 has load device to Vee
Hi Z
o
."
.,,'
L5 same as L7
Option 10 = 0 (402)
= 1 (402M)
~
j:
(")
RESET pin has load device to Vee
IN1 has load device to Vee
HiZ
a
o
."
Ground Pin - no option available
Option 9 = 0 (402)
= 1 (402M)
8
D-
00 same as-03
normal operation
MICROBUSTM operation
40-pin package
3-35
'lilt
~
D..
o
~
o
~National
a
Semiconductor
'lilt
D..
o COP404lCOP304 ROMless N·Channel Microcontrollers
()
General Description
Features
The COP404/COP304 ROM less N·Channel Microcontrol·
lers are members of the COPSTM family, fabricated
using N·channel, silicon gate MOS technology. Each
microcontroller contains all system timing, internal
logic, RAM and I/O necessary to implement dedicated
control functions in a variety of applications, and is
identical to the COP440/COP340 devices, except that
the ROM has been removed; pins have been added to
output the ROM address and to input ROM data. In a
system, the COP404 will perform exactly as the
COP440; this important benefit facilitates development
and debug ,of a COP440 program prior to masking the
final part. Features include single supply operation,
various output configurations, and an instruction set,
internal architecture, and I/O scheme designed to
facilitate keyboard input, display output and data
manipulation. Standard test procedures and reliable
high·density fabrication techniques provide the medium
to large volume customers with a controller·oriented
processor at a low end·product cost. COP304 is an
exact functional equivalent version of COP404, but with
an extended temperature range (-40°C to +85°C).
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Exact circuit equivalent of COP440
Standard 48·pin dual·in·line package
Interfaces with standard PROM or ROM
Enhanced, more powerful instruction set
160 x 4 RAM, addresses up to 2k x 8 ROM
MICROBUSTM compatible
Zero·crossing detect circuitry with hysterisis
True multi·vectored interrupt from four selectable
sources (plus restart)
Four·level subroutine stack (in RAM)
41's cycle time
Single supply operation (4.5V-6.3V)
Programmable time·base counter for real·time
processing
.
Internal binary counter/register with MICROWIRETM
compatible seri<;ll I/O
'
General purpose and TRI·STATE® outputs
TTL/CMOS compatible in and out
Software/hardware compatible with other members
of COP400 family
Extended temperature range device COP304
(-40°C to +85°C)
Compatible dual CPU device available
TRt·STATE is a registered trademark of National Semiconductor Corp.
COPS, MICROBUS, and MICROWIRE, are trademarks of National Semiconductor Corp.
AD/wi
Del<
'k1
.£....1P7
+:~
47
IP4
-,~
~11'2
:L::~
, - - - - - - t - " " - ::lM,CROW,AE 110
SI
INa
--2l..-H~-+-+--
::~±.~==t=:t::
lNo--1!.....I--......- _
Mil
24
OJ
MICAOBUS
FUNCTION
SELECT
Figure 1. COP404 Block Diagram
3-36
o
o"tJ
8
COP404
Absolute Maximum Ratings
~
Voltage at Zero-Crossing Detect Pin
Relative to GND
Voltage at Any Other Pin Relative to GND
Ambient Operating Temperature
Ambient Storage Temperature
Lead Temperature (Soldering, 10 seconds)
Power Dissipation
o
o
-1.2Vto +15V
-0.5Vto +7V
O·Cto +70·C
-65·C to +150·C
300·C
0.75 Watt at 25·C
0.4 Watt at 70·C
150mA
90mA
Total Source Current
Total Sink Current
"tJ
(0)
o
01:00
Absolute maximum ratings indicate limits beyond which damage
to the device may occur. DC and AC electrical specifications are
not ensured when operating the device at absolute maximum
ratings.
DC Electrical Characteristics
O·C'" TA '" + 70·C, 4.5V '" Vee'" 6.3V unless otherwise noted.
Parameter
Conditions
Min.
Units
Operating Voltage (Vee)
Note 3
6.3
V
Power Supply Ripple
(peak to peak)
0.4
V
Operating Supply Current
(All inputs and outputs open)
TA=O·C
TA =25·C
TA=70·C
44
37
30
mA
mA
mA
3
mA
VR RAM Power Supply Current
Input Voltage Levels
CKI Input Levels (';'16)
Logic High (V IH )
Logic High (VI H)
Logic Low (Vld
RESET Input Levels
Logic High
4.5
Max_
VR=3.3V
Vee = Max.,
Vee=5V±5%
~
Trip Point
Logic High (V IH ) Limit
Logic Low (Vld Limit
IN1
Logic High
Logic Low
All Other Inputs
Logic High
Logic High
Logic Low
0.4
V
V
V
0.7Vee
-0.3
0.6
V
V
(Schmitt Trigger Input)
........ ..... ..
_......
Zero-Crossing Detect Input (IN 1)
2.5
2.0
-0.3
Zero-Crossing Interrupt
Input; INIL Instruction
-0.15
0.15
12
-0.8
Interrupt Input;
ININ Instruction;
MICROBUSTM Input
3.0
-0.3
2.5
2.0
-0.3
Vee = Max.
Vee=5V±5%
V
V
V
0.8
V
V
0.8
V
V
V
IN1 Input Resistance to Ground
VIH=1.0V
1.5
4.6
kQ
Input Load Source Current
VIH = 2.0V, Vee = 4.5V
14
230
",A
7.0
pF
-1.0
+1.0
",A
Input Capacitance
Hi-Z Input Leakage
3-37
COP404
DC Electrical Characteristics
(Cont'd)
Conditions
Parameter
Output Voltage Levels
Standard Output
TTL Operation
Logic High (Vo H)
Logic Low (VoLl
CMOS Operation
Logic High (VO H)
Logic Low (VoLl
TRI·STATE~ Output
TTL Operation
Logic High (Vo H)
Logic Low {VoLl
CMOS Operation
Logic High (VOH)
Logic Low (VoLl
Output Current Levels
Standard Output Source Current
TRI'STATE Output Leakage Current
Max.
Units
0.4
V
V
0.2
V
V
0.4
V
V
0.4
V
V
-650
+2.5
I'A
I'A
90
mA
2.4
IOH = - 1OO IlA
IOL= 1.6mA
Vee -0.4
IOH = - 1O I'A
IOL= 1OI'A
2.4
IOH = - 1OO IlA
IOL=1.6mA
33kQ~ RL~4.7kQ
Vee- 0.5
IOH= - 1OI'A
IOL=1.6mA
Vee = 4.5V, VOH = 2.4V
Total Sink Current Allowed
All 1/0 Combined
Each L, R Port
Each D, G, H Port
SO,SK
IP
Total Source Current Allowed
All 1/0 Combined
L Port
L7-l.,j
L3-La
Each L Pin
All Other Output Pins
Min.
-100
-2.5
20
rnA
10
2.5
1.8
mA
mA
mA
150
120
70
70
23
1.6
rnA
rnA
rnA
rnArnA
rnA
Note 4
I
I
3-38
COP304
Absolute Maximum Rating.s
Voltage at Zero·Crosslng Detect Pin
Relative to GND
Voltage at Any Other Pin Relative to GND
Ambient Operating Temperature
Ambient Storage Temperature
Lead Temperature (Soldering, 10 seconds)
Power Dissipation
-1.2Vto +15V
-0.5Vto +7V
-40·C to +85·C
-65·C to +150·C
300·C
0.75 Watt at 25·C
0.25 Watt at 85·C
150mA
90mA
Total Source Current
Total Sink Current
Absolute maximum ratings indicate limits beyond which
damage to the device may occur. DC and AC electrical speclfica·
tions are not ensured when operating the device at absolute
maximum ratings.
DC Electrical Characteristics
-40·C';; TA .;; +85·C, 4.5V';; Vee';; 5.5V unless otherwise noted.
Parameter
Conditions
Min.
Max.
4.5
5.5
Units
,
Operating Voltage (Vecl
Note 3
Power Supply Ripple
(peak to peak)
0.4
V
Operating Supply Current
(All inputs and outputs open)
TA=-40·C
TA =25·C
TA=85·C
57
37
29
mA
mA
mA
4
mA
2.2
-0.3
0.3
V
V
0.7 Vee
-0.3
0.4
V
V
VR RAM Power Supply Current
Input Voltage Levels
CKI Input Levels (+16)
Logic High (VIH)
Logic Low (VILl
VR=3.3V
RESET Input Levels
Logic High
Logic Low
..,_~_
,.. ____ ! _ _
r"\_"' __ '"
V
(Schmitt Trigger Input)
1 __ .....
II~I
\
--'- - Input; INIL Instruction
Trip Point
Logic High (VIH) Limit
Logic Low (VILl Limit
Logic High
Logic Low
All Other Inputs
Logic High
Logic Low
-0.15
0.15
12
-0.8
Interrupt Input;
ININ Instruction;
MICROBUSTM Input
V
V
V
3.3
-0.3
0.6
V
V
2.2
-0.3
0.6
V
V·
IN1 Input Resistance to Ground
VIH=1.0V
1.4
4.6
kQ
Input Load Source Current
VIH=2.0V, Vee=4.5V
14
230
/J A
7.0
pF
-2.0
+2.0
~
Input Capacitance
Hi·Z Input Leakage
3-39
L
C
~
Q.
I
Q.
oo
COP304
DC Electrical Characteristics
(Cont'd)
Parameter
Output Voltage Levels
Standard Output
TTL Operation
Logic High (VOH)
Logic Low (VoLl
CMOS Operation
Logic High (VOH )
Logic Low (VoLl
TRI·STATE~ Output
TTL Operation
Logic High (VoH)
Logic Low (VoLl
CMOS Operation
Logic High (VoH)
Logic Low (VoLl
Conditions
Min.
IOH = -100"A
IOL=1.6mA
2.4
IOH = -10"A
IOL=10"A
Vee- 0.5
IOH = -100"A
IOL=1.6mA
2.2
Max.
Units
0.4
V
V
0.2
V
V
0.4
V
V
0.4
V
V
33kQ~RL~4.7kQ
Vec- 0.7
IOH= -10"A
IOL=1.6mA
Output Current Levels
Standard Output Source Current
Vee = 4.5V, VOH = 2.4V
TRI·STATE Output Leakage Current
Total Sink Current Allowed
All 110 Combined
Each L, R Port
Ea.ch D, G, H Port
SO,SK
IP
Total Source Current Allowed
All I/O Combined
" L Port
-100
-800
"A
-5.0
+5.0
"A
75
20
10
2.5
1.8
mA
mA
mA
mA
mA
150
120
70
70
23
1.6
mA
mA
mA
mA
mA
rnA
Note 4
L7-~
La-La
Each L Pin
All Other Output Pins
\
3-40
(')
o"til
AC Electrical Characteristics
COP404: o·c ~ TA ~ + 70·C, 4.5 V ~ Vee ~ 6.3 V unless otherwise noted.
a
COP304: -40·C ~ TA ~ +B5·C, 4.5V ~ Vee ~ 5.5V unless otherwise noted.
Parameter
Instruction Cycle Time -
Conditions
tE
CKI Frequency
Duty Cycle (Note 1)
Rise Time
Fall Time
INPUTS: (Figure 3)
SI
tSETUP
tHOLD
IP
tSETUP
tHOLD
tHOLD
All Other Inputs
tSETUP
tHOLD
OUTPUT PROPAGATION DELAY
IP
tpd1A, tpdQA
, tpd 1B, tpdQB
+16 mode
fl=4MHz
f l =4MHz
fl=4MHz
From AD/DATA rising edge
Min.
Max.
Units
4.0
10
!Is
1.6
30
4.0
60
60
40
MHz
%
ns
ns
0.3
300
!IS
ns
0.25
250
0
!IS
ns
ns
1.7
300
!Is
ns
!IS
j./S
DCK
tpd1, tpdQ
375
ns
ADIDATA
t pd1, tpdQ
300
ns
MICROBUSTM TIMING
Read Operation
Chip Select Stable Before RD-tesR
\,;nlp ::ieleet NOlO lime Tor nU-IReS
RD Pulse Width-tRR
Data Delay from RD-tRO
RD to Data Floating-toF
"til
g
Test Condition:
CL=50pF, VOUT= 1.5V
1.94
0.94
SO,SK
tpd10 tpdQ
All Other Outputs
8
RL=2.4kQ
1.0
!Is
RL=5.0kQ
1.4
!IS
CL =100pF, Vee=5V±5%
outputs
TRI-STATE~
65
ns
400
375
250
ns
ns
ns
700
ns
ns
ns
ns
ns
ns
--
Write Operation
Chip Select Stable Before WR-tesw
Chip Select Hold Time for WR-twes
WR Pulse Width-tww
Data Set·Up Time for WR-tow
Data Hold Time for WR-two
INTR Transition Time from WR-twi
65
20
400
320
100
Note 1: Duty Cycle = tWI/(tWI + two).
Note 2: See Figure for additional 110 Characteristics.
Note 3: Vee voltage change must be less than 0.5 V In a 1 ms period to maintain proper operation.
Note 4: Exercise great care not- to exceed maximum device power dissipation limits when direct-driving LEOs (or sourcing similar
loads) at high temperature.
3-41
I:
G
~
0
C")
D..
Pin
0
0
~
0
IP1
IPO
~
D..
0
VRAM
CKI
CKDI
RESET
0
R7
R6
R5
R4
R3
R2
R1
RO
L7
L6
L5
l4
IN1
IN2
VCC
13
L2
MB
48
47
46
45
44
43
42
41
40
10
39
11
38
12
37
COP404/304
13
36
14
35
15
34
16
33
17
32
18
31
19
3D
20
29
21.
28
22
27
23
26
24
25
IP2
IP3
IP4
IP5
IP6
1P7
AD/DATA
DCK
H3
H2
H1
HO
G3
G2
G1
GO
IN3
INO
SK
SO
SI
GND
LO
L1
Figure 2. Connection Diagram
Description
L7-Lo
B·bit bidirectional TRI·STATE® I/O port
G3 -Go
4·bit bidirectional I/O port
IN3-INo
4·bit general purpose input port
H3- HO
4·bit bidirectional I/O port
R7- RO
B·bit bidirectional TRI·STATE I/O port
SI
Serial input
SO
Serial output (or general purpose output)
SK
Logic·controlled clock (or general
purpose output)
CKI
System oscillator input
CKOI
General purpose input
VRAM
Power supply to first 4 registers of RAM
MB
MICROBUSTM function select
DCK
Clock output to latch D outputs and high
order address bits
ADIDATA
Address out/data in flag
IP1- IPo
B·bit bidirectional port for ROM address,
ROM data and D outputs
RESET
System reset input
Vee
Power Supply
GND
Ground
Order Number COP404N, COP304N
NS Package N48A
Timing Diagram
CKI
SKAS
ACLDCK
-=======~
CROSSINGOPTIDN _
IN1ZERO-
ALL OTHER
INPUTS _ _ _ _-'=
.OK
All OTHER
OUTPUTS
Figure 3. Input/Output Timing Diagrams (+16 Mode)
3-42
Flmctlonal Description
Figure 3 shows the timings for IP port and the external
memory interface clocks- DCK and AD/DATA. While
DCK is low, the upper three address bits, P10-P8, of the
next instruction to be executed appear at IP2-IPO
respectively; D3-DO appear at IP7-IP4 and IP3 contains
the SKIP output used by the COPSTM Program Develop·
ment System (PDS). The rising edge of DCK clocks these
data into D flip·flops, e_g., 74LS374. The timing of D port
data is then the same for COP404 and COP440. After
DCK has risen to a "1" level, the remaining address bits
(P7-PO) appear at IP7-IPO_ The falling edge of AD/DATA
latches these data into flow-through latches, e.g.,
74LS373. The latched addresses provide the inputs to
the external memory. When ADIDATA goes low, the IP
outputs are disabled and the IP lines become program
memory inputs from the external memory. Note that
DCK has a duty cycle of about 50% and ADIDATA has a
duty cycle of about 75%. Figure 4 shows how to emulate
the COP440 using a COP404 and an EPROM as the external memory.
The COP404 is a ROM less microcontroller for emulating
the COP440 or for stand-alone applications_ Please refer
to the COP440 description for detail functional description_ The following describes functions that are unique
to the COP404 or are different from those in COP440_ All
references to COP404 also apply to COP304_ Figures 1
and 2 show the COP404 block diagram and pin-out.
Program fvlemory
Program memory consists of 2048 bytes of external
memory (on-chip in the COP440) that can be accessed
through the IP port. See External Memory Interface
below_
D PorI
The D3-DO outputs are missing from this 48-pin package,
but may be recovered through the IP port (see External
Memory Interface below)_ Note that the recovered signals
Ilave the same timing but different output drive capability
as those from·the COP440 (see D Port Characteristics
below)_
1/0 Options
All inputs except IN1 and CKI have on-Chip depletion
load devices to Vee. IN1 has a resistive load to GND due
to the zero-crossing input. CKI is a Hi·Z input.
rlfilCROBUSTM and Zero-Crossing
Deiect Input Option
G and H ports have standard outputs. Land R ports
have TRI·STATE outputs. IP port, DCK, ADIDATA, SO
and SK have push-pull outputs.
Tile MICROBUS compatible I/O, selected by a mask
option on the COP440, is selected by tying the MB pin
directiy to ground. When the MICROBUS compatible I/O
is not desired, the MB pin should be tied to Vce- Note that
none of the IN inputs are Hi-Z_ Since zero-crossing detect
input (used by INIL instruction and zero-crossing interrupt feature) is chosen for IN1, the IN1 input "1" level for
ININ instruction, IN1 interrupt, and MICROBUS input is
3V. Even though the MICROBUS option and zero-crossing detector option appear on the COP404, they are
mutually exclusive on the COP440_
LED Drive
The TRI-STATE outputs of L port may be used to drive
the segments of an LED display. External current limiting resistors of 100 ohms must be connected between
the L outputs and the LED segments.
D Port Characteristics
Since the D port is recovered through an external latch,
the output drive is that OT tne latcn and not tnat or
COP440. Using the set-up as shown in Figure 4, at an
output "0" level of O.4V, the 74LS374 may sink 10 times
as much current as the COP440. At an output "1" level
of 2.4 V, the 74LS374 may source 10 times as much
current as the COP440. On the other hand, the output
"1" level of 74LS374 latch does not go to Vee without an
external pull-up resistor. In order to better approximate
the COP440 output characteristics, add a 74C906 buffer
to the output of the 74LS374, thus emulating an open
drain D output. A pull·up resistor of 10k should be added
to the input of the buffer. To emulate the standard
output, add a pull·up resistor between 2.7k and 15k to
the output of the 74C906.
CKI is an external clock input signal. The clock frequency is divided by 16 to give the execution frequency_
c[m
Pin Options
Two diiferent CKO functions of the COP440 are available on the COP404_ VRAM supplies power to the lower
four registers of RAM, and CKOI is an interrupt input or
a general purpose input, reading into bit 2 of A (accumulator) through the INIL instruction_
External Memory Interface
The COP404 is designed for use with an external program memory_ This memory may be implemented using
any devices having the following characteristics:
1. Random addressi ng
2. TTL-compatible TRI-STATE® outputs
3_ TTL-compatible inputs
4_ Access time = 450 ns maximum
Typically these requirements are met using bipolar or
MOS PROMs.
3-43
&
c
oo::t
0
('I)
a..
0
U
~
0
oo::t
a..
0
U
COP440
PINOUT
20
GNO
DO
19
1
18
17
D1
1ti
OJ
15
H3,~
"
ONO
1P7
H2,~
14
1P6
HI ~
13
12
1P5
HO,-2!..
IP'
G2.~
'P3
IP2
G3:~
11
10
Gl ----li
GO,----11
'PI
,PO
1N3:---1.!.
oeK
18
43
44
17
45
14
.6
13
47
8
4B
7
2
3
41
11
06 - ; ; - -
03
03
D1
D1
01
01
CLOCK
INO,-21
SK
08 16
07"'-;---
06
05
05,=-D4DM74lS374046SKIP
•
1
J
DB
07
00
GND
1
2
10
19
5
"
2
23
~24
2D
12
,.......!!
11
40
Vee
42
39
l2
37
IN2
36
IN1
-r!!-
l4 -~
34
L5
33
L6
32
L7
31
RD
3D
R1
29
R2
28
R3
26
25
24
23
j-!l.
r!!-
•
f1i
fl!.
3
~
-.!!COP440
DB
08
07
07
05
05
04
D.
03
03
D1
02
01
A8
01
11
19
I
Vss
OE
MM2716
1B
1
16
2
15
3
12
•
5
9
VPP
Vee
6
6
5
7
2
8
CE
A7
A6
A5
A4
A3
A2
AI
AD
07 06 (15 04 Q3 02 01 00
1311 I. 9
-~
1171''1' 1'
-t-!!-
R4
2.
MlI
CKI -...!.
eKOI
PINOUT
2D
06 OM74LS373 06
7
-fl2.
RS -f-l
R6 -fo-!
R7 -t-l
RESET -fo-!
22
10
[£
~
~
~
~8
-~
35
27
1
00 GNO Vee
COP404
,-flJ.
L3:-fl1.
38
2D
AD/DATA
-2!.
-,ll
A9
vee
so,---'1
LO,.......!!
A10
CKD
VRAM
\f\'
-
6
47kQ
vee
~
MICROBUS FUNCTION OPTION SELECT
GNO
eKD FUNCTION
OPTION SELECT
Figure 4. COP204 Used to Emulate a COP440
3-44
(')
o"'tI
COP404 Mask Options
~
The following COP4400ptions have been implemented in
the COP404.
Option Value
Option
Option
Option
Option
Option
Option
Option
Option
Option
~
(')
Comment
1- 2=3
3
=0
4
=2
5
=2
6
=0
7
=0
8-11 = 0
12-15= 0
16-19=N/A
Option 20
Option 21
Option 22
L outputs are TRI·STATE®
SI has load to Vee
SO is push-pull output
SK is push·pull output
INO has load to Vee
IN3 has load to Vee
G outputs are standard
H outputs are standard
D outputs are derived from
external latch, see Figure 4
=N/A GND-Nooption
= 1,2 CKO is replaced by VRAM and
CKOI
CKI is input clock divided by 16
=0
RESET has load to Vee
R outputs are TRI-STATE
L outputs are TRI·STATE
IN1 is zero-crossing detect input
IN2 has load to Vee
L outputs are TRI·STATE
Vee - No option available
MICROBUSTM option is pin
selectable
Option 42-48= 0
Inputs have standard TTL levels
= N/A No option available
Option 49
Option 50
= N/A 48·pin package
Option
Option
Option
Option
Option
Option
Option
Option
3-45
23
=0
24-31 = 3
32-35= 3
36
=2
37
=0
38-39= 3
40
= N/A
41
=0,1
o"'tI
CN
o
-'="
.....
~ ~National
~
a
~
COP404L/COP304L ROMless N-Channel Microcontrollers
~
o
(.)
Semiconductor
General Description
Features
The COP404L ROMless Mlcrocontrolier Is a member of
the COPSTM family, fabricated using N-channel, silicon
gate MOS technology. The COP404L contains CPU, RAM,
1/0 and Is Identical to a COP444L device except the ROM
has been removed and pins have been added to output
the ROM address and to Input the ROM data. In a system
the COP404L will perform exactly as the COP444L. This
Important benefit facilitates development and debug
of a COP program prior to masking the final part. The
COP404L is also appropriate In low volume applications,
or when the program might be changing. The COP404L
may be used toemulatetheCOP444L, COP445L, COP420L;
and the COP421 L.
•
•
•
•
•
•
•
•
•
•
•
The COP304L Is an exact functional equivalent of the
COP404L, but with extended temperature range.
•
•
•
I;
•
cops and MICROWIRE are trademarks of National
Exact circuit equivalent of COP444L
Low cost
Powerful Instruction set
128 x 4 RAM, addresses 2048 x 8 ROM
True vectored interrupt, plus restart
Three-level subroutine stack
151-'s Instruction time
Single supply operation (4.5-9.5V)
Low current drain (16mA max.)
Internal time-base counter for real-time processing
Internal binary counter register with MICROWIRETM
compatible serial 1/0
General purpose outputs
LSTTLICMOS compatible in and out
Direct drive of LED digit and segment lines
Softwarelhardware compatible with other members
of COP400 family
Extended temperature range (-40°C to +85°C)
device COP304L
Semiconductor Corp.
AD/DATA
IP,
IP,
IP,
IP,
IP,
IP,
IP,
IP,
Po
P'~----'~-----'
SKIP/P10
0,
0.
1.=:::::::::;:;::::::;1--"- "I
so I
MICROWIRE 110
S1
G,·
G,
Gl
Go
11
27 16
CKO
15
12
13
14 18 19
20 21
26
IN) IN2 INI INO
(CDP404LP ONLY)
Figure 1. COP404L Block Diagram
3-46
o
o"'0
COP404L
Absolute Maximum Ratings
.t::o.
Voltage at Any Pin Relative to GND
Ambient Operating Temperature
Ambient Storage Temperature
Lead Temperature (Soldering, 10 seconds)
Power Dissipation
o
.t::o.
C
-0.5V to +10V
0°Cto+70°C
-65°C to +150°C
300°C
0.75 Watt at 25°C
0.4 Watt at 70°C
120mA
140mA
Total Source CUrr6:1t
Total Sink Current
o
o
"'0
Co)
o
.t::o.
r-
Absolute maximum ratings indicate limits beyond which damage
to the device may occur. DC and AC electrical specifications are
not ensured when operating the device at absolute maximum
ratings.
DC Electrical Characteristics
O°C"; TA
Parameter
.,;
+70°C, 4.5V"; Vee"; 9.5V unless otherwise noted.
Conditions
Min.
Max.
Units
4.5
9.5
V
Operating Voltage (Vee)
(Note 2)
Power Supply Ripple
peak to peak
0.5
V
Operati ng Supply Current
all inputs and outputs open
16
mA
2.0
-0.3
0.4
V
V
0.7Vec
-0.3
0.6
V
V
O.B
V
V
V
1.2
V
V
7
pF
0.4
V
V
0.4
V
V
Input Voltage Levels
CKI Input Levels
Crystal Input
Logic High (V 1H )
Logic Low (VILl
RESET Input Levels
Logic High
Logic Low
IPO-IP7, SI Input Levels
Logic High
Logic High
Logic Low
Schmitt Trigger Input
2.4
2.0
-0.3
Vee=9.5V
Vee=5V±5%
All Other Inputs
I nnir. Hinh
hinh trin Ipvp.1 nnfinn!=;
Logic Low
selected
::l.n
-0.3
Input Capacitance
Output Voltage Levels
LSTTL Operation
Logic High (Vo H)
Logic Low (VoLl
Vee=5V±5%
IOH = - 25 f'A
IOL=0.36mA
2.7
IPO-IP7, PB, P9, SKIP/P10
Logic High (COP404LS only)
Logic Low
(Note 1)
10H =-1OO f'A
IOL=1.6mA
2.4
SO and SK Outputs (loll
Vee = 9.5V, VOL = 0.4V
Vee = 4.5V, VOL = O.4V
1.B
0.9
mA
mA
Lo-L7 Outputs
Vec = 9.5V, VOL = O.4V
Vec = 4.5V, VOL = O.4V
O.B
0.4
mA
mA
GO-G 3 and Do-D3 Outputs
Vce = 9.5V, VOL = 1.0V
Vee = 4.5V, VOL = 1.0V
30
15
mA
mA
CKO (COP404LS)
Vee = 4.5V, VOL = O.4V
0.2
mA
Output Current Levels
Output Sink Current
3-47
-I
~
a..
§
COP404L
DC Electrical Characteristics
Parameter
§
Output Source Current:
0 0 -03, Go-G 3 Outputs (IOH)
oo
SO and SK Outputs (lOH)
a..
Lo- L7 Outputs
Input Load Source Current (lid
(continued) O°C" TA" +70°C, 4.5V" Vec" 9.5V unless otherwise noted.
Conditions
Vee = 9.5V,
Vce = 4.5V,
Vee =9.5V,
Vee = 4.5V,
Vce = 9.5V,
Vee = 6.0V,
VOH = 2.0V
VOH = 2.0V
VOH = 4.75V
VO H = 1.0V
VOH = 2.0V
VO H = 2.0V
Vee = 5.0V, VIL = OV
Total Sink Current Allowed
All Outputs Combined
0, G Ports
L7-~
L3-Lo
All Other Pins
Total Source Current Allowed
All 1/0 Combined
Lr L4
L3-Lo
Each L Pin
All Other Pins
3-48
Min.
Max.
Units
-140
-30
-1.4
-1.2
-3.0
-3.0
-800
-250
-35
-25
Il A
Il A
rnA
rnA
rnA
rnA
-10
-140
Il A
140
120
4
4
1.8
rnA
rnA
rnA
rnA
rnA
120
60
60
30
1.5
rnA
rnA
rnA
rnA
rnA
COP304L
Absolute Maximum Ratings
Voltage at Any Pin Relative to GND
Ambient Operating Temperature
Ambient Storage Temperature
Lead Temperature (Soldering, 10 seconds)
Power Dissipation
Total Source Current
Total Sink Current
-0.5V to +10V
-40°C to +85°C
-65°C to +150°C
300°C
0.75 Watt at 25°C
0.25 Watt at 85°C
120mA
140mA
Absolute maximum ratings indicate limits beyond which damage
to the device may occur. DC and AC electrical specifications are
not ensured when operating the device at absolute maximum
ratings.
DC Electrical Characteristics
-40°C
Parameter
~
TA
~
+85°C, 4.5V
Conditions
~
Vee
~
7.5V unless otherwise noted.
Min.
Max.
Units
4.5
7.5
V
ulJ""i:1iiIlY 'v'uiii:1yt:: i'v'eel
ii'ute 2)
Power Supply Ripple
peak to peak
0.5
V
Operating Supply Current
all Inputs and outputs open
21
mA
2.2
-0.3
0.3
V
V
0.7 Vee
-0.3
0.4
V
V
0.6
V
V
V
1.2
V
V
7
pF
0.4
V
V
0.4
V
V
Input Voltage Levels
CKI Input Levels
Crystal Input
Logic High (V'H)
Logic Low (V,Ll
RESET Input Levels
Logic High
Logic Low
IPO-IP7, SI Input Levels
Logic High
Logic High
Logic Low
....
.. Of
Schmitt Trigger Input
2.4
2.2
-0.3
Vee = 7.5V
Vee=5V±5%
-_ .......... ... ---
_
.. L.., _ _
&
I _ _ •• .L_
Logic High
Logic Low
high trip level options
selected
3.6
-0.3
Input Capacitance
Output Voltage Levels
LSTTL Operation
Logic High (VOH )
Logic Low (VoLl
Vee=5V±5%
IOH =-20I'A
IOL=0.36mA
2.7
IPO·IP7, P8, P9,SKIPIP10
Logic High
Logic Low
RL =5.6kQ (Note 1)
IOH =-100I'A
IOL=1.6mA
2.4
Vee = 7.5V, VOL = O.4V
Vee = 4.5V, VOL = O.4V
1.4
0.8
mA
mA
Lo- L7 Outputs
Vee = 7.5V, VOL = O.4V
Vee = 4.5V, VOL = 0.4V
0.6
0.4
mA
mA
GO-G3 and Do-D3 Outputs
Vee = 7.5V, VOL = 1.0V
Vee = 4.5V, VOL = 1.0V
Vee = 4.5V, VOL = O.4V
24
14
0.2
mA
mA
mA
Output Current Levels
Output Sink Current
SO and SK Outputs (loll
CKO (COP404LS)
3-49
c
COP304L
DC Electrical Characteristics
Parameter
(continued) -40°C" TA " +85°C, 4.5V" Vcc " 7.5V unless otherwise noted.
Min.
Conditions
Max.
Units
Output Source Current:
Do-Da, Go-G a Outputs (lOH)
SO and SK Outputs (IOH)
Lo- L7 Outputs
Input Load Source Current (11Ll
Vce = 7.5V,
Vce = 4.5V,
Vee = 7.5V,
Vee = 4.5V,
Vee '= 7.5V,
Vee = 6.0V,
VO H = 2.0V
VOH = 2.0V
VOH = 3.75V
VOH = 1.0V
VOH = 2.0V
VOH = 2.0V
-100
-28
-0.85
-1.2
-2.7
-2.7
-900
-350
Jl.A
Jl.A
-54
-34
mA
mA
mA
mA
-10
-200
Jl.A
Total Sink Current Allowed
All ()utputs Combined
0, G Ports
Lr L4
La-Lo
All Other Pins
140
120
4
4
1.8
mA
mA
mA
mA
mA
Total Source Current Allowed
All 1/0 Combined
L7- L4
La-La
Each L Pin
All Other Pins
120
60
60
30
1.5
mA
mA
mA
mA
mA
Min.
Max.
Units
15
40
Jl.S
0.8
30
2.1
60
120
80
MHz
2.0
1.0
Jl.S
Jl.s
8.0
1.3
Jl.s
Jl.S
4.0
Jl.s
5.6
Jl.s
7.2
Jl.S
6.0
Jl.s
Vee = 5.0V, VIL = OV
COP404L1COP304L
AC E;lectrical Ctlaracteristics
C'QP404L: O°C" TA " +70°C, 4.5V" Vee" 9.5V unless otherwise specified.
COP304L: -40°C" TA " +85°C, 4.5V " 7.5V unless otherwise specified
Parameter
Conditions
Instruction Cycle Time
CKI
Input Frequency fl
Duty Cycle
Rise Time
Fall Time
(+32 mode)
fl = 2.097 MHz
%
ns
ns
INPUTS:
-
81,IP7-IPO
tSETUP
tHOLD
INa-INo, Ga-Go, L7-Lo
tSETUP
t HOLD
OUTPUT PROPAGATION DELAY
SO, SK Outputs
t pd1, tpdO
Test condition:
CL =50pF, VOUT·=1.5V·
RL =20kQ
Da-Do, Ga-Go, L7-Lo
tpd1, tpdO
RL=20kQ
IP7-IPO, P8, P9, SKIP
tpd1, tpdO
RL=5kQ
P10
t pd1, tpdo
RL=5kQ
Note 1: Pull-up resistors required on COP404LP only; COP404LS has Push·Pull drivers on these outputs.
Note 2: Vee voltage change must be less than O.5V in a 1 ms period to maintain proper operation.
3-50
0
0
CKO
40
DO
."
CKI
39
01
§
IP4
02
RESET
03
IP3
IP5
IP2
P8
C
0
0
IPI
P9
IPo
AD/DATA
."
Co)
0
~
SKIP/Plo
IP1
eOP404lP
eOP404lS
1P6
r
G3
G2
11
11
l6
12
Gl
l5
13
GO
l4
14
IN]
INI
15
INo
IN2
16
SK
Vce
l3
11
SO
l2
19
22
GNO
II
20
21
LO
SI
18
Figure 2. Connection Diagram
Order Number COP404UN, COP304UN
NS Package N40A
Pin
Description
L7 -Lo
Pin
8 bidirectional I/O ports with
TRI-STATE~
G3- GO
Description
CKI
System oscillator input
CKO
General purpose Input (COP404LP)
System oscillator output (COP404LS)
4 bidirectional I/O ports
03- 0 0
4 general purpose outputs
~
System reset input
IN3-IN o
4 general purpose inputs
Vee
SI
Serial input (or counter Input)
Power supply
Ground
SO
Serial output (or general purpose output)
GND
IP7-IPO
SK
Logic-controlled clock (or general
P8, P9
ntJrnO!=lA nlltnllt\
AD/DATA
CKI
Address out/data In flag
-I I---I
~
pdl
AD/DATA, SK
(AS A CLOCK)
INO·IN3, Go-G3,
Lo-L1, CKo. SI
IPO-IP7 INPUTS
GO-G3, 00-03,
Lo·L7, SO, SI
OUTPUTS
I_ _~
~t,do
~ YOH
IC!Ol· 1IIIIIII//I
I
!-IsETUP--+_IHolO--!
________
>&W:
r~=I~I~~H~I--~~~
I
SKIP/P10
OUTPUT
YOH
(SKIP)
_IPdl'--';'~;;;;I...
1-1-
IPO-IP7, PB, pg
OUTPUTS
;;:'r\..,...',....IV
8 bidirectional ROM address and data
ports
2 ROM address outputs
m~HUC1l0n SKIp OUIPUI ana mosl
significant ROM address bit output
~~~~~l
__
I-~
~(P1~O~)______~~~V~Ol~~
_ _ ------- -
3-51
__________
~ YOL
~~,~H
D_
Functional Description
cycle time. (See XAS instruction and EN register des·
cription, below.)
A block diagram of the COP404L is given in Figure 1. Data
paths are illustrated in simplified form to depict how the
various logic elements communicate with each other in
implementing the instruction set of the device. Positive
logic is used. When a bit is set, it is a logic "1" (greater
than 2 volts). When a bit is reset, it is a logic "0" (less
than 0.8 volts).
.
Four general·purpose inputs, INa-INo, are provided.
The D register provides 4 general·purpose outputs and
is used as the destination register for the 4·bit contents
of Bd. The D outputs can be directly connected to the
digits of a multiplexed LED display.
All functional references to the COP404L also apply to
the COP304L.
The G register contents are outputs to 4 general·,
purpose bidirectional I/O portse G I/O ports can be
directly connected to the digits of a multiplexed LED
display.
Program Memory
Program Memory consists of a 2048 byte external memo
ory. As can be seen by an examination of the COP404L
instruction set, these words may be program instruc·
tions, program data or ROM addressing data. Because of
the special characteristics associated with the JP, JSRP,
JID and LaiD instructions, ROM must often be thought
of as being organized into 32 pages of 64 words each.
The a register is an internal,latched, 8·bit register, used
to hold data loaded to or from M and A, as well as 8·bit
data from ROM. Its contents are output to the L I/O
ports when the L drivers are enabled under program
control. (See LEI instruction.)
The 8 L drivers,when enabled, output the contents of
latched a data to the L I/O ports. Also, the contents of L
may be read directly into A and M. L I/O ports can be
directly connected to the segments of a multiplexed
LED display (using the LED Direct Drive output configu·
ration option) with a data being outputted to the Sa-Sg
and decimal point segments of the display.
ROM addressing is accomplished by a 11·bit PC register.
Its binary value selects one of the 2048 8·bit words con·
tained in ROM. A new address is loaded into the PC
register during each instruction cycle. Unless the instruc·
tion is a transfer of control instruction, the PC register
is loaded with the next sequential 11·bit binary count
value. Three levels of subroutine nesting are imple·
mented by the 11·bit subroutine saves registers, SA, SB,
and SC, providing a last·in, first·out (LIFO) hardware
subroutine stack.
The SIO register functions as a 4·bit serial·in/serial·out
shift register or as a binary counter depending on the
contents of the EN register. (See EN register descrip·
tion, below.) Its contents can be exchanged with A, al·
lowing it to input or output a continuous serial data
stream. SIO may also be used to provide additional
parallel I/O by connecting SO to external serial·in/parallel·
out shift registers.
ROM instruction words are fetched, decoded and
executed by the Instruction Decode, Control and Skip
Logic circuitry.
Data Memory
The XAS instruction copies C into the SKL latch. In the
counter mode, SK is the output of SKL; in the shift
register mode, SK outputs SKL ANDed with the clock.
Data memory consists of a 512·bit RAM, organized as 8
data registers of 16 4·bit digits. RAM addressing is im·
plemented by a 7·bit B register whose upper 3 bits (Br)
select 1 of 8 data registers and lower 4 bits (Bd) select 1
of 16 4·bit digits in the selected data register. While the
4·bit contents of the selected RAM digit (M) is usually
loaded into or from, or exchanged with, the A register
(accumulator), it may also be loaded. into or from the a
latches or loaded from the L ports. RAM addressing may
also be performed directly by the LDD and XAD instruc·
tions based upon the 7·bit contents of the operand field
of these instructions. The Bd register also serves as a
source register for 4·bit data sent directly to the D
outputs.
The EN register is an internal 4·bit register loaded under
program control by the LEI instruction. The state of
each bit of this register selects or deselects the
particular feature associated with each bit of the EN
register (EN3 - ENo).
1. The least significant bit of the enable register, ENo,
selects the SIO register as either a 4·bit shift register
or a 4·bit binary counter. With ENo set, SIO is an
asynchronous binary counter, decrementing its value
by one upon each low·going pulse ("1" to "0") ocur·
ring on the SI input. Each pulse must be at least two
instruction cycles wide. SK outputs the value of SKL.
The SO output is equal to the value of EN 3. With ENo
reset, SIO is a serial shift register shifting left each
instruction cycle time. The data present at SI goes
into the least significant bit of SIO. SO can be
enabled to output the most significant bit of SIO
each cycle time. (See 4 below.) The SK output be·
comes a logic·controlled clock.
Internal Logic
The 4·bit A register (accumulator) is the source and
destination register for most I/O, arithmetic, logic and
data memory access operations. It can also'be used to
load the Br and Bd portions of the B register, to load and
input 4 bits of the 8·bit a latch data, to input 4 bits of the
8·bit L I/O port data and to perform data exchanges with
the SIO register.
2. With EN1 set the IN1 input is enabled as an interrupt
input. Immediately following an interrupt, EN1 is
.
reset to disable further interrupts.
A 4·bit adder performs the arithmetic and logic func·
tions, storing its results in A. It also outputs a carry bit
to the 1·bit C register, most often employed to indicate
arithmetic overflow. The C register, in conjunction with
the XAS instruction and the EN register, also serves to
control the SK output. C can be outputted directly to SK
or can enable SK to be a sync clock each instruction
3. With EN2 set, the L drivers are enabled to output the
data in a to the L I/O ports. Resetting EN2 disables
the L drivers, placing the L I/O ports in a high·
impedance input state.
3-52
4. EN 3, in canjunctian with EN o, affects the SO autput.
With ENo set (binary caunter aptian selected) SO will
autput the value laaded into. EN3' With ENo reset
(serial shift register aptian selected), setting EN3
enables SO as the autput af the SIO shift register,
autputting serial shifted data each instructian time.
Resetting EN3 with the serial shift register aptian
selected disables SO as the shift ,register autput;
data cantinues to. be shifted through SIO and can be
exchanged with A via an XAS instructian but SO reo
mains reset to. "0." The table belaw pravides a summary af the mades assQciated with EN3 and ENo.
is saved and pragram cantral is transferred to. the
interrupt servicing rautine at hex address OFF. At the
end af the interrupt rautine, a RET instructian is executed to. "pap" the stack and return pragram cantrol
to. the instruct ian fallawing the ariginal ASC. At this
time, the skip lagic is enabled and skips this instructian because af the previaus ASC carry. Subrautines
and LaiD instructians shauld nat be nested within
the interrupt service rautine, since their papping the
stack will enable any previausly saved main program
skips, interfering with the arderly executian af the
interrupt rautine.
d. The first instructian af the interrupt rautine at hex
address OFF must be a Nap.
Interrupt
Thefallawing features are assaciated with the IN1
interrupt pracedure and pratacal and must be cansidered by the programmer when utilizing interrupts.
e. A LEI instructian can be put immediately be fare the
RET to. re-enable interrupts.
Initialization
a. The interrupt, ance ac'knawledged as explained
belaw, pushes the next sequential pragram caunter
address (PC + 1) anta the stack, pushing in turn the
c;ulli.mi::; oi iil~ oiil~r ,;uiJrouiine-save registers to tne
next lawer level (PC + 1 - SA - SB - SC). Any
previaus cantents af SC are last. The pragram
caunter .is set to. hex address OFF (the last ward af
page 3) and EN1 is reset.
b.An interrupt will be acknawledged anly after the fallawingcanditians are met:
1. EN1 has been set.
2. A law-gaing pulse ("1" to. "0") at least twa instructian cycles wide occurs an the IN1 input.
3. A currently executing instructian has been
.campleted.
4. All successive transfer af cantral instructians
ahd successive LBls have been campleted (e.g.,
if the main pragram is executing a JP instructian which transfers pragram cantral to. anather
.ID incdrl'f"ti"n tho into .. r'"n+ u.lill
C.
""+
The Reset Lagic will Initialize (clear) the device upan
pawer-up if the pawer supply rise time Is less than 1 ms
elnU gr~aier lnan i !,s. ii tne pawer suppiy rise lime is
greater than 1 ms, the user must provide an external RC
netwark and diade to. the RESET pin as shawn belaw.
The RESET pin is canfigured as a Schmitt trigger input. If
the RC netwark is nat used, the RESET pin shauld be left
apen. Initializatian will occur whenever a lagic "0" is
applied to the RESET input, pravided it stays law for at
least three instructian cycle times.
P +
0
W
E
R
S
U
P
P
.~
R>
I
h.o. 0,..1..."1"'\\&1_
Y
ledged until the secand JP instruct ian has been
executed.
Upan acknawledgement af an interrupt, the skip
lagic status is saved and later restared upan papping
af the stack. Far example, if an interrupt accurs during
the executian af ASC (Add with Carry, Skip an Carry)
instructian which results in carry, the skip lagic status
I
~
j
vcc
~
RESET
,
1==
Bits EN3 and ENO
ENo
510
51
SO
o
Shift Register
Input to. Shift Register
o
5K
If SKL = 1, 5K
If SKL
o
Shift Register
W-
GNO
RC" 5 x POWER SUPPL Y RISE TIME (R>40k)
Enable Register Modes -
o
--------.
-
= CLOCK
= 0, SK = 0
If SKL = 1, SK = CLOCK
Input to. Shift Register
If SKL = 0, SK = 0
o
Binary Caunter
Input to. Binary Caunter
o
If SKL
If SKL
Binary Caunter
Input to. Binary Caunter
If SKL
= 1, SK = 1
= 0, SK = 0
= 1, SK = 1
. If SKL = 0, SK = 0
3-53
~
...J
~D-
oo
::J
~
oo
Upon initialization, the PC register is cleared to 0 (ROM
address 0) and the A, B, C, 0, EN, and G registers are
cleared. The SK output is enabled as a SYNC output,
providing a pulse each instruction cycle time. Data
Memory (RAM) is not cleared upon initialization. The
first instruction at address 0 must be a CLRA.
b. Open·Draln - an enhancement-mode device to
ground only, allowing external pull'up as requited by
the. user's application. (Used on IP, Pand SKIP/P10
outputs on COP404LP only).
An enhancement·mode device to
c • Push· Pull ground In conjunction with a depletlon-mode device
paralleled by an enhancement·mode deVice to Vee.
This configuration has been provided· to allow for
fast rise and fall times when driving capacitive loads.
(Used on SO and SK outputs on COP404LP and
404LS; also used on IP, P and SKIP/P10 outputs on
COP404LS only.)
d •LED Direct Drive - an enhancement·mode device to
ground and to Vec, meeting the typical current
sourcing reqUirements of the segments of an LED
display. The sourcing device Is clamped to limit
current flow. These devices may be turned off under
program control (See Functional Description, EN
Register), plaCing the outputs In a hlgh·lmpedance
state to provide required LED segment blanking for a !
multiplexed display. (Used on L outputs).
External Memory Interface
The COP404L is designed for use with an external
Program Memory. This memory may be implemented
using any devices having the following characteristics:
1.
2.
3.
4.
random addressing
TTL-compatible TRI·STAT~ outputs
TTL-compatible inputs
access time=5,..s max.
Typically these requirements are met using bipolar or
MOS PROMs.
During operation, the address of the next instruction is
sent out on P10, P9, P8, and IP7 through IPO during the
time that ADIDATA is high (logic "1" = address mode).
Address data on the IP lines is stored into an external
latch on the high·to·iow transition of the AD/DATA line;
P9 and P8 are dedicated address outputs, and do not
need to be latched. SKIP/P10 outputs address data
when AD/DATA Is low. When AD/DATA is low (logic
"0" =data mode), the output of the memory is gated
onto IP7 through IPO, forming the input bus. Note that
the AD/DATA output has a period of one instruction
time, a duty cycle of approximately 50%, and specifies
whether the IP lines are used for address output or
instruction input.
COP404L Inputs have an on-chlp depletion load device
to Vce.
The above hiput and output configurations share com·
mon enhancement-mode and depletion-mode devices.
Specifically, all configurations use one or more of six
devices (numbered 1-6, respectively). Minimum and maxi·
mum current (lOUT and VOUT) curves are given In Figure 8
for each of these devices to allow the designer to effec·
tlvely use these 1/0 configurations In deSigning a system.
An Important point to remember Is that even when the L
drivers are disabled, the depletion load device will source
a small amount of current (see Figure 8, device 2); how·
ever, when the L·llnes are used as Inputs, the disabled
depletion device can not be relied on to source sufficient
current to pull an Input to a logic "1".
Oscillator
Two basic clock oscillator configurations have been
implemented, as shown in Figure 4.
a. Crystal Controlled Oscillator (COP404LS only). CKI
and CKO are connected to an external crystal. The
instruction cycle time equals the crystal frequency
divided by 32
COP404LP and COP404LS
Two versiOns of the basic eOP404L have been Imple·
mented: the eOP404LP, with open-draln memory Inter·
face drlvers,ls used only In the COP400-E04L Emulator
Card; the COP404LS, with push-pull memory Interface,
Is Intended for use In small to medium volume produc·
tlon applications.
b. External Oscillator (COP404LP only). CKI is an
external clock input signal. The external frequency is
divided by 32 to give the Instruction cycle time. CKO
Is used as a general purpose input.
The COP404LP has an oscillator output option on eKOj
the COP404LS has a general purpose Input option.
CKO as an Input
On the COP404LP, CKO has been configured as a general·
purpose Input. The logic level applied to CKO will be
read Into bit 2 of A (accumulator) upon execution of an
INIL Instruction.
Input/Output Configurations
COP404L outputs have the following configurations, II·
lustrated In figure 5:
a. Standard - an enhancement mode device to ground
In conjunction with a depletion·mode device to Vee,
compatible with LSTTL and CMOS input require·
ments. (Used on 0 and G outputs.)
3-54
(")
o
"'0
~
~
C
(")
o"'0
Co)
~
r-
COP4D4LS
COP4D4LP
1M
EXTERNAL
CLOCK
...JU""L
I
GENERAL
PURPOSE INPUT
Figure 4. Oscillator
Vcc
---II
'-1
ti
"3
a. Standard Output
Vcc
--II" ~-l ~ # 2
#2
"'-1
b. Open· Drain Output
d. L Output (LED)
c. Push· Pull Output
e. Input with Load
(A IS DEPLETION DEVICE)
Figure 5. Output Configurations
3-55
..J
~
Input Current for Lo through
L7 when Output Programmed
Off by Software
Current for Inputs with
Load Device
Q.
§
-1000
-100
!
-70
Q.
j
oo
~
~
Q
5
!2
-60
-50
-40
-30
-900
-600
1\..1 MAX @VCC c 9.IV
-700
""
"
1
j
I'..
IMIN ~ VCC" 9.5
~
~N@VCC"4.5V ~
~I
"i
I
~
o
-10
o
9.5
"\
-600
"\ IMAX @VCC" 9.5 V
-500
'\.1
I'\. "1
IMAX@
-400 ~CC"4.SV
I MAX}
VCC"4.5V
-300 f--'KI7:MiN@
Vcc" .SV
-200
-20
1.0 2.0 3.0 4.0 5.0 6.0 7.0 6.0
DEVICE a #2
DEVICE d #2
1
-90
-60
Source Current for Standard
Output Configuration
1.0
o
v I/O
Source Current for SO and SK
L Output Source Current
r-_
o
2.0
VIN (VOLTS)
7~~ J/~~~" 9.S
-100
....
I
(VOLTS)
"
.'K'"N-l:
2
3
4
5
6
7
VOH (VOLTS)
"'"
6
9.5
LED Output Direct Segment
and Digit Drive
-S 0
DeVICE d '2 AND 14
AND DeVICE a 11
-40
IMAX
ONE SEGMENTS.,.........
1.0 I--fl-I--I-HH-'i---=-'f-t-rl-l
Ci
-30
E
-20
.s
.....
//
0.5
........
-10
;';;;'1::::::'
,/
'.'"
V
.......-;'MAX EIGHT
SEGMENTS ON
IMIN
1
1
10
VOH (VOLTS)
VOH(VOlTSi
LED Output Direct Segment
Drive
-50
VOH"2.0V
Vcc (VOLTS)
Output Sink Current for SO
and SK
Output Sink Current for Lo
through L7
4~rTr---~--'---.---~
OEVICE d
12 AND *4
-40
4
.s
"
!2
-30
IMV'
-20
-10
.--
-
.........
.'
.... ......
IMIN
10
Vcc (VOLTS)
VOL(VOLTS)
VOUVOLTS)
Output Sink Current IPO-IP7,
P8, P9, SKIP/P10, AD/DATA
Output Sink Current GO-G 3
and 0 0 -0 3
120
100
L~IMAX@
<
~r-.----.r--------'
VCC=4_5V
80
S
2.0
VCC=9.5V
DEVICE a#l
'1 IMAX@i~"T
AND b#l
IfiMINI @
~CC~9.~V
<
;: 1.0 1H--f--1'---~-'-"-----l
60
s:
=>
I
40
s:
V f- I-
20
~
o
1
IrINI@
2 3
~cci4.~v
4
5
6
7
8
O~0--------~O~.5--------~1.0
9 10
VOUT (VOLTS)
VOUVOLTS)
Figure 6a. COP404L I/O Characteristics
3-56
()
o"U
§
a
o
"U
Input Current for Lo-L7
When Output Programmed
Off by Software
Input Load Source Current
INO-IN3'
-2S0
-zoo
1-
r-....
~
........
......
z
-50
D
-1.2
1
°iV'Cj
150
= -100
I"-....
j
o
-;; -0.6
!?
\
-0.4
3
1
-so
DEVICE I
#2 AND #4
/
-40
1.0
IMIN@
VCC=4.SV
~IIMAX@
vccrSI
oI
o
-20
v,c,r
3
7
4
kIMAX@
vcc = S.DV
W "'
1,\ \
IMIN @
vcc = 7.5V
-10
1\
1\
IMIN @
vcc = S.OV
I I \
I
0~1>..L
~ 1"j.., 'b-N
1
\jMAX @
Vcc = 7.5V
)
IMIN@
VCC=7.SV
IMAX@
I I
O.S
4
Output Sink Current for
SO and SK
L Output Source Current
-5 0
g=
I--?-n-I---P'r 110 Port
4-bit contents of RAM Memory pointed to by
B Register
3-bit ROM Address Register Port
11-bit ROM Address Register (program
counter)
S-bit Register to latch data for L 110 Port
11-bit Subroutine Save Register A
11-bit Subroutine Save Register B
11-bit Subroutine Save Register C
4-bit Shift Register and Counter
Logic-Controlled Clock Output
RAM(s) Contents of RAM location addressed by s
ROM(t) Contents of ROM location addressed by t
OPERATIONAL SYMBOLS
+
-
..-
3-58
Plus
Minus
Replaces
Is exchanged with
=
Is equal to
A
The one's complement of A
Ell
Exclusive-OR
:
Range of values
0
0
Table 2. COP404L/304L In.tructlon Set
""CJ
§
Machine
M_1c Operand
Hex
Code
Lln,UIgI Code
Bln8ry)
Date Flow
Skip CondHIon8
Description
""CJ
ASC
30
10011100001
A+C+RAM(B)- A
Carry- C
Carry
Add with Carry, Skip on
Carry
ADD
31
10011100011
A+RAM(B)- A
None
Add RAM to A
ADT
4A
10100110101
A+10l0- A
None
Add Ten to A
S-
\0101 1 y
A+y-A
Carry
Add Immediate, Skip on
Carry (y" 0)
CAse
10
10001100001
A+RAM(B)+C-A
Carry- C
Carry
Complement and Add with
Carry, Skip on Carry
CLRA
00
10000100001
O-"A
None
Clear A
COMP
40
10100100001
'A-A
None
One's complement of A to A
HOP
44
iu 1 uuiu 1 uui
l'Ione
l'1U"a
''1'''' "" .... U.UU ... II
fie
32
10011100101
"O"-C
None
Reset C
None
Set C
None
exclusive-OR RAM with A
AISC
Y
~
0
ARITHMETIC IN~UCTIONS
\
,
.. ,_
SC
22
10010100101
111"_0
XOR
02
100001°0101
Ae RAM(B)- A
§
r-
..... ____ .. 1 __
TRANSFER OF CONTROL INSTRUCTIONS
JII)
-IMP
a
FF
11111111111
ROM (PC'0:8, A,M) - PC7:0 None
Jump Indirect (Note 3)
8-
1011 0l0I-10:81
a-PC
None
Jump
a-PO&:O
None
Jump within Page (Note 4)
I
JP
I
118":0
111
I
(pages 2,3 only)
a
87:0
or
I' 'I "0:\1 I
(aU other pages)
JSRP
a
JSR
a
85:0
\101
8-
~ 11 ~11811)·..1
I
I
\1 0001
87:0
RET
48
10100
RETSK
40
\0100110011
I
All
.-
;J:v
......
PC+l- SA- SB- SC
00010 - PCl0:8
a - PC5:0
None
Jump to Subroutine Page
(Note 5)
PC+l - SA- S8 - SC
a-PC
None
Jump to Subroutine
SC-SB-SA-PC
None
Return from Subroutine
SC-SB-SA-PC
Always Skip on Return
Return from Subroutine
then Skip
3-59
...I
"lit
Table 2. COP404U304L Instruction Set (continued)
~
4.
0
0
Hex
Code
Machine
Language Code
(Binary)
::J
Mnemonic Operanci
ia.
MEMORY REFERENCE INSTRUCTIONS
"lit
0
CAMa
0
CaMA
LD
LDD
r,d
33
1°011100111
3C
10011111001
STII
A-a7:4
RAM(B) - a3:0
None
Copy A, RAM to a
a7:4 - RAM(B)
a3:0- A
None
Copy a to RAM, A
33
10011100111
100 1 0/11 001
-5
1001 r 10 1 0 11
(r-0:3)
RAM(B)-A
BrG>r-Br
None
Load RAM Into A,
Excluslve·OR Br with r
23
10010100111
RAM(r,d) - A
None
Load A with RAM pointed
to directly by r,d
I
d
I
ROM(PC10:8,A,M) - a
SB-SC
None
Load a Indirect (Note 3)
0
4C
10100/11001
0- RAM(B)O
None
Reset RAM Bit
1
45
10100101011
0- RAM(B)1
None
Set RAM Bit
y- RAM(B)
Bd+1-Bd
None
Store Memory Immediate
and Increment Bd
RAM(B)-A
BrG>r-Br
None
Exchange RAM with A,
RAM(r,d)- A
None
Exchange A with RAM
Bd decrements past 0
Exchange RAM with A
and DecremMt Bd,
Exclusive-OR Br with r
2
42
1010010.0101
O~ RAM(B!:!
3
43
10100100111
0.- RAM(B)3
0
40
10100/11011
1- RAM(B)O
47
10100111011
1 - RAM(BI1
2
46
10100101101
1- RAM(B)2
3
4B
10100110111
Y
r,d
XDS
r
I
7-
y
10111 1
-6
1001 r 101101
(r-0:3)
23
10010100111
111 r
XIS
Description
/1011111111
X
XAD
,
2C·
101 r
5MB
Skip Conditions
BF
LaiD
RMB
Data Flow
I
d
1- RAM(B)3
Excluslve-QR Br with r
I
pointed to directly by r,d
-7
1001 r 101111
(r=0:3)
RAM(B)- A
Bd-1- Bd
BrG> r - Br
-4
10°1 r 101001
(r-0:3)
RAM(B)-A
Bd+1- Bd
BrG>r- Br
Bd Increments past 15
Exchange RAM with A
and Increment Bd,
Exclusive-OR Br with r
REGISTER. REFERENCE INSTRUCTIONS
CAB
50
10101100.001
A- Bd
None
Copy A to Bd
CB,A
4E
10100111101
Bd-A
None
Copy Bd to A
I
r,d- B
Skip until not a LBI
Load B Immediate with r,d
(Note 6)
y- EN
None
Load EN Immediate (Note 7)
None
Exchange A with Br
LBI
r,d
10 °1 r (d - 1)1
(r-0:3;
d ';0,9:15)
or
33
10011100111
111 r 1 d 1
(any. r, any d)
LEI
XABR
Y
33
10011100011
6-
y
10110 1
12
1°0011°01°1
1
A- Br (0-
Aal
3-60
Table 2. COP404L1304L Instruction Set (continued)
Hex
Code
Machine
Language Code
(Binary)
SKC
20
10010100001
C="l"
Skip if C is True
SKE
21
10010100011
A=RAM(B)
Skip if A Equals RAM
SKGZ
33
10011100111
G3:0=0
Skip if G is Zero (ali 4 bits)
21
10010100011
33
10011100111
01
10000100011
Mnemonic Operand
Dala Flow
Skip Condilions .
Descrlpllon
TEST INSTRUCTIONS
SKGBZ
0
SKMBZ
Skip If G Bit is Zero
1st byte
GO=O
1
11
10001100011
2
03
10000100111
G2=0
3
13
10001100111
G3=0
0
01
10000100011
RAM(B)O=O
1
11
10001100011
RAM(Bh =0
2
03
100001001 '1
nAiviiol£ -
3
13
10001100111
RAM(B)3=0
41
10100100011
A time·base counter
carry has occurred
since last test
Skip on Timer (Note 2)
G-A
None
Input G Ports to A
IN-A
None
Input IN Inputs to A
IL3, CKO,"O", ILa - A
None
Input IL Latches to A
(Note 2)
RAMIB\
None
Input L Ports to RAM A
SKT
Gl=O
2nd byte
Skip if RAM Bit Is Zero
~
INPUT/OUTPUT INSTRUCTIONS
ING
IN IN
INIL
.....
33
10011100111
2A
10010110101
33
10011100111
28
10010110001
33
10011100111
29
10010110011
~~
Inn 111nn 111
I
OBD
OGI
OMG
XAS
Y
,
I
~.A -
2E
1°°1°111101
L3:0- A
Bd- D
None
Output Bd to D Outputs
y-G
None
Output to G Ports Immediate
RAM(B)- G
None
Output RAM to G Ports
A - SIO, C - SKL
None
Exchange A with SIO
(Note 2)
33
1°011100111
3E
1°0111111°1
33
5-
1°0111°0111
1° 1 ° 11
yl
33
1°0111°0111
3A
100111101°1
4F
1°100111111
Note 1: All subscripts for alphabetical symbols indicate bit numbers unless explicitly defined (e.g., Br and Bd are explicitly defined). Bits are numbered Oto
N where 0 signifies the least significant bit (Iow-order, right·most bit). For example, A3 indicates the most significant (Ieft·most) bit of the 4·blt A register.
Note 2: For additional information on the operation of the XAS, JID, LaiD, INIL, and SKT instructions, see below.
Note 3: The JP instruction allows a jump, while in subroutine pages 2 or 3, to any ROM location within the two·page boundary of pages 2 or 3. The JP
instruction, otherwise, permits a jump to a ROM location within the current 64·word page. JP may not jump to the last word of a page.
Note 4: A JSRP transfers program control to subroutine page 2 (0010 is loaded into the upper 4 bits of Pl. A JSRP may not be used when in pages 2 or 3.
JSRP may notiump to the last word in page 2.
Note 5: LBI is a single·byte instruction if d = 0.9,10, ", 12, 13, 14, or 15. The machine code for the lower 4 bits equals the binary value of the "d" data
minus I, e.g., to load the lower four bits of B (Bd) with the value 9 (10012), the lower 4 bits of the LBllnstruction equal 8 (10002)' To load 0, the lower 4 bits of
the LBI instruction should equal 15 (,,1'2).
Note 6: Machine code for operand field y for LEI instruction should equai the binary value to be latched Into EN, where a "1" or "0" in each bit of EN
corresponds with the selection or deselection of a particular function associated with each bit. (See Functional Description, EN Register.)
3-61
The following information is provided to assist the user
in understanding the operation of several unique instructions and to provide notes useful to programmers in
writing COP404L programs.
COP404L
ININ
1
INotlN3
XAS Instruction
XAS (Exchange A with SIO) exchanges the 4-blt contents
of the accumulator with the 4-blt contents of the SIO
register. The contents of SIO will contain serlal-inl
serlal-out shift register or binary counter data, depending
on the value of the EN register. An XAS Instruction will
also affect the SK output. (See Functional Description,
EN Register, above.) If SIO Is selected as a shift register, an XAS Instruction must be performed once every 4
Instruction cycles to effect a continuous data stream.
INIL
Figure 7. INIL Hardware Implementation
JID Instruction
JID (Jump Indirect) Is an Indirect addressing Instruction,
transferring program control to a new ROM location
pointed to indirectly by A and M. It loads the lower 8 bits
of the ROM address register PC with the contents of
ROM addressed by the 11-blt word, PC,o:s, A, M. PC,o,
PCs and PCs are not affected by this Instruction.
SKT Instruction
Note that JID requires 2 Instruction cycles to execute.
The SKT (Skip On Timer) instruction tests the state of an
internal 1()'bit time-base counter. This counter divides
the Instruction cycle clock frequency by 1024 and provides a latched Indication of counter overflow. The SKT
Instruction tests this latch, executing the next program
instruction if the latch is not set. If the latch has been
set since the previous test, the next program instruction
is skipped and the latch is reset. The features associated with this Instruction, therefore, allow the COP404L
to generate its own time-base for real-time processing
rather than relying on an external Input signal.
INIL Instruction
INIL (Input IL Latches to A) inputs 2 latches, IlJ and ILa
(see figure 7) and CKO Into A. The IlJ and ILa latches are
set if a low-going pulse ("1" to "0") has occurred on the
IN3 and INo inputs since the last INIL instruction, provided the input pulse stays low for at least two Instruction times. Execution of an INIL inuts IlJ and ILa into A3
and AO respectively, and resets these latches to allow
them to respond to subsequent low-going pulses on the
IN3 and INo lines. INIL will input the state of CKO into A2
on the COP404LP ("1" into A2 for the COP404LS). A "0"
is always placed in A1 upon the execution of an INIL.
The general purpose Inputs IN3-INo are input to A upon
execution of an IN IN instruction. (See table 2, ININ instruction.) INIL is useful in recognizing pulses of short
duration or pulses which occur too often to be read con,
veniently by an ININ Instruction.
For example, using a 2.097 MHz oscillator as the timebase to the clock generator, the instruction cycle clock
frequency will be 65kHz (crystal frequency"," 32) and the
binary counter output pulse frequency will be 64Hz. For
time-of-day or similar real-time proceSSing, the SKT instruction can call a routine which increments a "seconds"
cou'nter every 64 ticks.
Instruction Set Notes
Note: IL latches are not cleared on reset.
a. The first word of a COP404L program (ROM address
0) must be a CLRA (Clear A) instruction.
b. Although skipped instructions are not executed, one
instruction cycle time is devoted to. skipping each
byte of the skipped instruction. Thus all program paths
except JID and LaiD take the same number of cycle
times whether instructions are skipped or executed.
JID and LaiD Instructions take 2 cycles if executed
and 1 cycle if skipped.
c. The ROM is organized into 32 pages of 64 words
each. The Program Counter is an 11-bit binary counter, and will count through page boundaries. If a JP,
JSRP, JID or LaiD Instruction is located in the last
word of a page, the instruction operates as if it were
in the next page. For example: a JP located in the last
word of a page will jump to a location in the next
page. Also, a LaiD or JID located in the last word of
page 3, 7, 11, 15, 19, 23 or 27 will access data in the
next group offour pages.
LQID Instruction
LaiD (Load a Indirect) loads the 8-bit a register with the
contents of ROM pointed to by the 11-bit word PC,o,
PCg, PCs, A, M. LaiD can be used for table lookup or
code conversion such as BCD to seven-segment. The
LaiD instruction "pushes" the stack (PC + 1 .... SA .... SB
.... SC) and replaces the least significant 8 bits of PC as
follows: A .... PC7:4, RAM(B) .... PC3:0 , leaving PC,o, PCs
and PCs unchanged. The ROM data pointed to by the
new address is fetched and loaded into the a latches.
Next, the stack is "popped" (SC .... SB - SA -PC),
restoring the saved value of PC to continue sequential
program execution. Since LaiD pushes SB .... SC, the
previous contents of SC are lost. Also, when LaiD pops
the stack, the previously pushed contents of SB are left
In SC. The net result Is that the contents of SB are placed
in SC (SB .... SC). Note that LaiD takes two Instruction
cycle times to execute.
3-62
o
o"'CJ
Typical Applications
~
PROM·Based System
~
The COP404L may be used to exactly emulate the
COP444L. Figure 8 shows the interconnect to imple'
ment a COP444L hardware emulation. This connect!on
uses a MM27t6 EPROM as external memory. Other
memory can be used such as bipolar PROM or RAM.
When ADIDATA turns off, the EPROM is enabled and the
IP7·IPO pins will input the memory data. P8, P9 and
SKIP/PtO output the most significant address bits to
the memory. (SKIP output may be used for program
debug if needed.)
Pins IP7·IPO are bidirectional inputs and outputs. When
the ADIDATA clocking output turns on, the EPROM
drivers are disabled and IP7·IPO output addresses. The
8·bit latch (MM74C373) latches the addresses to drive
the memory.
The other 28 pins of the COP404L may be configured ex·
actly the same as a COP444L. The COP404L Vce can
vary from 4.5V to 9.5V. However, 5 volts is used for the
memory.
12
1
2
3
!
4
5
6
7
~
+5V
-
For In·Circuit emulation, see also COP404LR.
~+5V
Vee
Vpp 21
GND
A7
A6
As
A,
MM2716
LU.tO
A
jj i:rou:,~
AlO
19
"
A3
A,
A,
As
1L-
A,
DE
IT
2E.
.:!
Ao
07 06 05 04 03 0, 0, 00
17 16 15 14 13 11 10 9
19 16 15 12 9 6 5 2
as 07 06 05 0, 03 a, 0,
~ Vee
~
.....2
GND
Rl-5.6k
[E11
MM74C373
REOUIRED ON
COP404lP ONLY
OUTPUT OIS
Os 07 D6 05 D4 03 02 01
lB 17 14 13 B 7 4 3
+5V
',,;,,---
I'
22
9 10 36 3 5 6 7 B
IP7 1P6 IP5 IP, 1P3 IP, IP, IPo
I
33 35 34 32
AD/ Ps P, SKIP/
DATA
PlO
1
40
2
39
4
11
COP404lP
COP404lS
-31
12
~
14 15 16 17 lB 19 20 21
GND CKOCKIRESETl7 l6 L5
1234567
3B
E-
23 24 25 26 27 2B 29 30
L, INI IN2 Vee L3 L, L, Lo SI SO SK INo IN3 G, G, G,
B 9 10 11 12 13 14 15 16 17 lB 19 20 2 i 22 23
Figure 8. COP404L System Diagram
3-63
G3 03 0, 0, 00
24 25 26 27 2B
I
COP444L
PINOUT
r:
o
o"'CJ
~r-
-"
~
D.
COP404L Mask Options
oo
The following COP444L options have been implemented on the basic versions of the COP404L:
i
Option 1 =0
Option 2 = 0 (404LS)
::J
D.
oo
=2 (404LP)
Option 3=0
Option 4=0
Ground, no option available
CKO is clock generator output
to crystal/resonator
CKO Is general purpose input
with load device to Vee
CKI is oscillator input (divide
by 32)
RESET pin has load device to
Vee
6=2
7=2
8=2
9=0
10=0
Option 11 = 1
Option 12=2
Option 13=2
Option 14=2
Option 15=2
Option 16=0
Option 17=2
SO has push-pull output
Option 18=2
SK has push-pull output
Option 19=0
INO has load device to Vee
Option 20=0
IN3 has load device to Vee
Option 21 =0
Option 22=0
Option 5=2
Option
Option
Option
Option
Option
Comment
Option Value
Comment
Option Value
G'}
Option 23=0
G1 have very high current
G2 standard output
Option 24=0
G3
~}
4 have LED direct-drive
Ls output
L'}
Option 25=0
L4
IN1 has load device to Vee
IN2 has load device to Vee
Vee 4.5 to 9.5V operation
Option 27=0
02 have very high current
0 1 standard output
Option 28=0
Do
Option 26=0
Option 29=1
Option 30=1
Option
Option
Option
Option
Option
:}
L2 have LED direct-drive
L1 output
Lo
51 has load to Vee
3-64
31 = 1
32=0
33=0
34=0
35 = NIA
~N
)have higher voltage
G Input levels
SI has standard input level
RESET has Schmitt trigger Input
CKO has standard input levels
40-pin package
o
o
."
~National
U Semiconductor
COP2404/COP2304 ROMless Dual CPU Microcontrollers
I
o
."
I\)
(0)
General Description
Features
The COP2404/COP2304 ROM less Dual CPU Microcontrollers are members of the COPSTM family, fabricated using N-channel, silicon gate MOS technology.
Each microcontroller contains two identical CPUs with
all system timing, internal logic, RAM and I/O necessary
to implement dedicated control functions in a variety of
applications, and are identical to COP2440/COP2340
devices, except that the ROM has been removed; pins
have been added to output the ROM address and to
input ROM data. In a system, the COP2404 will perform
exactly as the COP2440; this important benefit facili!~!e" -:le""lnf'mpnt "nri rip-hug of a COP2440 proQram
prior to masking the final part. Features include single
supply operation, various output configurations, and an
instruction set, internal architecture, and I/O scheme
designed to facilitate keyboard input, display output
and data manipulation. Standard test procedures and
reliable high-density fabrication techniques provide the
medium to large volume customers with a dual CPU
microcontroller at a low end-product cost. COP2304 is
an exact functional equivalent version of COP2404 with
an extended temperature range (-40°C to +85°C).
•
•
•
•
•
These microcontrollers are appropriate choices in many
demanding control environments, especially those with
human interface. Further, the high throughput and
MICROBUSTM I/O facilitate numerous machine interface
applications. The two CPUs provide on one chip the
ability to handle two simultaneous but totally inde_ _ _ ...J _ _ '"
.......... 1 .: ................. " ..... "'to:!-
•
•
•
•
•
•
•
•
•
•
•
•
!!I
•
•
o,f:a
Exact circuit equivalent of COP2440
Standard 48-pin dual-in-line package
Interfaces with standard PROM or ROM
Two independent processors
Dual CPU simplifies task partitioning -easy
to program
Enhanced, more powerful instruction set
160 x 4 RAM, addresses up to 2k x 8 ROM
MICROBUS compatible
Zero-crossing detect circuitry
True multi-vectored interrupt from 4 selectable
sources (PIUS resiarij
Four-level subroutine stack for each processor
(in RAM)
4 f's execution time per processor (non-overlapping)
Single supply operation (4.5V-6.3V)
Programmable time-base counter for real-time
processing
Internal binary counter/register with MICROWIRETM
compatible serial I/O
General purpose and TRI-STATE® outputs
TTL/CMOS compatible in and out
Software/hardware compatible with other members
of COP400 family
Extended temperature range device COP2304
(-40°C to +85°C)
Compatible single-processor device available
r-··--··· . ---
TRI·STATE Is a registered trademark of National Semiconductor Corp.
COPS, MICROBUS, and MICROWIAE are trademarks of National Semiconductor Corp.
ROM
CKI
INTERFACE
CLOCKS
aPPORT
"
BUFFERS
VRAM
RtSET
MICRDWIRE
'"
{
$I
so
"
Vee
OND
M.
(MICROBUS
FUNCTION
OPTION
SELECT)
CKOI
L
(GENERAL
PURPOSE
INPUT)
PORT
G
PORT
IN
PORT
R
PORT
H
PORT
Figure 1. COP2404 Block Diagram
3-65
.
"'I:t
o
(f)
('II
11.
o(.)
§
('II
11.
o(.)
COP2404
Absolute Maximum Ratings
Voltage at Zero-Crossing Detect Pin
Relative to GND
Voltage at Any Other Pin Relative to GND
Ambient Operating Temperature
Ambient Storage Temperature
Lead Temperature (Soldering, 10 seconds)
Power Dissipation
-1.2Vto +15V
-0.5Vto +7V
O·C to + 70·C
-65·Cto +150·C
300·C
0.75 Watt at 25·C
0.4 Watt at 70·C
150mA
90mA
Total Source Current
Total Sink Current
Absolute maximum ratings indicate limits beyond which damage
to the device may occur. DC and AC electrical specifications are
not ensured when operating the device at absolute maximum
ratings.
DC Electrical Characteristics
O·C.;; TA .;; + 70·C, 4.5V';; Vee';; 6.3V unless otherwise noted.
Parameter
Conditions
Min.
Max.
Units
Operating Voltage (Vecl
Note 3
6.3
V
Power Supply Ripple
(peak to peak)
0.4
V
Operating Supply Current
(All inputs and outputs open)
TA=O·C
TA =25·C
TA =70·C
44
37
30 .
mA
mA
mA
3
mA
2.5
2.0
-0.3
0.4
V
V
V
0. 7Vee
-0.3
0.6
V
V
VR RAM Power Supply Current
Input Voltage Levels
CKI Input Levels (+16)
Logic High (VIH )
Logic High (VIHl
Logic Low (Vlu
RESET Input Levels
Logic High
Logic Low
Zero·Crossing Detect Input (IN 1)
Trip Point
Logic High (V IH ) Limit
Logic Low (Vld Limit
IN1
Logic High
Logic Low
All Other Inputs
Logic High
Logic High
Logic Low
4.5
VR=3.3V
Vee = Max.
Vee=5V±5%
(Schmitt Trigger Input)
Zero·Crossing Interrupt
Input; INIL Instruction
-0.15
0.15
12
-0.8
Interrupt Input;
ININ Instruction;
MICROBUSTM Input
3.0
-0.3
2.5
2.0
-0.3
Vee = Max.
Vee=5V±5%
V
V
V
0.8
V
V
0.8
V
V
V
IN1 Input Resistance to Ground
VIH=1.0V
1.5
4.6
kQ
Input Load Source Current
VIH = 2.0V, Vee = 4.5V
14
230
7.0
"A
pF
-1.0
+1.0
"A
Input Capacitance
Hi-Z Input Leakage
3-66
COP2404
DC Electrical Characteristics
.
(')
o
(Cont'd)
Parameter
Conditions
Min.
Max.
Units
~
(')
o
Output Voltage Levels
Standard Output
TTL Operation
Logic High (VOH)
Logic Low (VoLl
CMOS Operation
Logic High (VOH )
Logic Low (VoLl
TRI·STATE Output
TTL Operation
Logic High (Vo H)
Logic Low (VoLl
CMOS Operation
Logic High (Vo H)
Logic Low (VOL)
IOH = -100!lA
IOL= 1.6mA
2.4
IOH = -10!lA
IOL =10!lA
Vcc- 0.4
IOH= -1001'A
IOL= 1.6mA
33kQ;;.RL;;'4.7kQ
IOH= - 1OI'A
IOL=1.6mA
0.4
V
V
0.2
V
V
0.4
V
V
0.4
V
V
-650
+2.5
!lA
!lA
90
20
10
2.5
1.8
mA
mA
mA
mA
mA
150
120
70
70
23
1.6
mA
mA
mA
mA
mA
mA
2.4
Vce- 0.5
Output Current Levels
S~e~~~~~ O'l~!"I_lt !=;nllrl'!A
8"
Currant
Vr.r. = 4.5V. Vm< = 2.4V
TRI·STATE Output Leakage Current
Total Sink Current Allowed
All 1/0 Combined
Each L, R Port
Each D, G, H Port
SO,SK
IP
Total Source Current Allowed
All 1/0 Combined
L Port
L7 -L!
L3 -i..o
Each L Pin
All Other Output Pins
-100
-2.5
Note 4
3-67
"
~
Co)
~
COP2304
Absolute Maximum Ratings
Voltage at Zero-Crossing Detect Pin
Relative to GND
Voltage at Any Other Pin Relativeto GND
Ambient Operating Temperature
Ambient Storage Temperature
Lead Temperature (Soldering, 10 seconds)
Power Dissipation
-1.2Vto +15V
-0.5Vto +7V
-40·C to +85·C
-65·Cto +150·C
300·C
0.75 Watt at 25·C
0.25 Watt at 85·C
150mA
90mA
Total Source Current
Total Sink Current
Absolute maximum ratings indicate limits beyond' which
damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute
maximum ratings.
DC Electrical Characteristics
-40·C '" TA '" +85·C, 4.5V '" Vee'" 5.5V unless otherwise noted.
Parameter
Conditions
Min.
Max_
Units
4.5
Operating Voltage (Ved
Note 3
5.5
V.
Power Supply Ripple
(peak to peak)
0.4
V
Operating Supply Current
(All inputs and outputs open)
TA= -40·C
TA =25·C
TA=85,·C
57
37
29
mA
mA
mA
4
mA
2.2
-0.3
0.3
V
V
0. 7Vec
-0.3
0.4
V
V
VA RAM Power Supply Current
VA=3.3V
Input Voltage Levels
CKI Input Levels (+16)
Logic High (VIH)
Logic Low (Vld
RESET Input Levels
Logic High
Logic Low
Zero-Crossing Detect Input (IN,)
(Schmitt Trigger Input)
Zero-Crossing Interrupt
Input; INIL Instruction
-0.15
Trip Point
Logie High (VIH) Limit
l.!ogic Low (Vld Limit
Logic High
Logic Low
All Other Inputs
Logie High
Logic Low
0.15
12
V
V
V
3.3
-0.3
0.6
V
2.2
-0.3
0.6
-0.8
Interrupt Input;
ININ Instruction;
MICROBUSTM Input
V
IN, Input Resistance to Ground
VIH=1.0V
1.4
4.6
Input Load Source Current
VIH=2.0V, Vec=4.5V
14
230
-2.0
+2.0
Input Capacitance
7.0
Hi-Z Input Leakage
3-68
COP2304
DC Electrical Characteristics
(Cont'd)
Parameter
Conditions
Output Voltage Levels
Standard Output
TTL Operation
Logic High (VOH)
Logic Low (VoLl
CMOS Operation
Logic High (VOH )
Logic Low (VoLl
TRI·STATE@ Output
TTL Operation
Logic High (VOH)
Logic Low (VoLl
CMOS Operation
Logic High (VOH)
Logic Low (VoLl
Max.
Units
0.4
V
V
0.2
V
V
0.4
V
V
0.4
V
V
-100
-800
iAA
-5.0
+5.0
J.LA
75
20
10
2.5
1.8
mA
mA
mA
mA
mA
150
120
70
70
23
1.6
mA
mA
mA
mA
mA
mA
Min.
IOH= -100J.lA
IOL=1.6mA
2.4
IOH = -10J.lA
IOL=10J.lA
Vee- 0.5
IOH = -100J.LA
IOL=1.6mA
2.2
33kQ~RL~4.7kQ
Vee- 0.7
IOH = -10J.lA
IOL=1.6mA
Output Current Levels
.... _
....
_
'"'UL ....... L .... .., ... , .................... ~
~_
....... _
r" ...............
.... , _ _ ...1 __ ...1
vtc;lIIUQI U
'.';:,;; - '!-5'/, '/;:;;: = 2 /J.V
TRI·STATE Output Leakage Current
Total Sink Current Allowed
All 1/0 Combined
Each L, R Port
Each D, G, H Port
SO,SK
IP
Total Source Current Allowed
All 1/0 Combined
L Port
L7 -4
L3-Lo
Each L Pin
All Other Output Pins
Note 4
3-69
~
('101
Q.
o
~o
Q.
o
AC Electrical Characteristics
COP2404: o·c", TA ", + 70·C, 4.5V '" Vee'" 6.3V unless otherwise noted.
COP2304: -40·C .. TA ", +85·C, 4.5V .. Vee" 5.5V unless otherwise noted.
Conditione
Parameter
Instruction Execution Tlme-tE
Each Processor (F/gure 3)
CKI Frequency
Duty Cycle (Note 1)
Rise Time
Fall Time
+16 mode
f,=4MHz
f,=4MHz
f, =4MHz
MIx.
Unitt
4.0
10
1.6
30
4.0
60
60
40
".
MHz
Min.
%
n8
n8
INPUTS: (Figure 3)
,..
,..
51
0.3
tSETUP
tHOLD
n8
300
IP
0.25
250
tSETUP
tHOLD
tHOLD
From AD/DATA rl81ng edge
All Other Inputs
tSETUP
tHOLD
OUTPUT PROPAGATION DELAY
IP
tpdlA, tpdOA
tpdlB, tpdOB
n8
n8
0
1.7
".
300
n8
Test Condition:
C L =50pF, VOUT=1.5V
1.94
0.9.-
,..
DCK
tpdl, tpdO
375
n8
AD/DATA
tpdl, tpdo
300
n8
RL=2.4kQ
1.0
,..
RL =5.0kQ
1.4
11&
SO,SK
tpdh' tpdO
All Other Outputs'
MICROBUSTM TIMING
Read Operation
Chip Select Stable Before RD-tCSR
Chip Select Hold Time for RD-tRCS
RD Pulse Width-tRR
Data Delay from RD-tRD
RD to Data Floating-tDF
118
C L =100pF, Vec=5V±5%
TRI·STATE-, outputs
65
250
na
na
n&
n8
n&
700
n&
n&
na
na
na
n&
20
400
375
Write Operation
Chip Select Stable Before WR-tesw
Chip Select Hold Time for WR-twes
WR Pulse Width-tww
Data Set-Up Time for WR-tDw
Data Hold Time for WR-tWD
INTR Transition Time from WR-tw,
65
20
400
320 ,
100
=
Note 1: Duty Cycle tw,/(tw, + two).
Note 2: See Figure for additional 110 Characteristics.
Note 3: Vec voltage change must be less than 0.5 V In a 1ms period to maintain proper operation.
Note 4: Exercise great care not to exceed maximum device power dissipation IImitl when dlrect-driYing lEO. (or sourcing limilar
loads) at high temperature.
3-70
C')
10
11
12
13
48
47
46
45
44
43
42
41
40
39
38
37
COP2404/2304 36
14
15
16
17
18
19
20
21
22
35
34
33
32
31
30
29
28
27
23
24
26
25
IPI
IPO
VRAM
CKI
CKOI
RESET
R7
R6
R5
R4
R3
R2
Rl
Ro
L7
L6
L5
L4
INI
IN2
VCC
L,
~
MB
=i
IP2
IP3
IP4
IP5
IP6
IP7
AD/DATA
DCK
H3
H2
HI
HD
G3
G2
Gl
Go
IN3
INo
SK
SO
SI
.GND
!==
LO
Ll
Order Number COP2404N, COP2304N
NS Package N40A
Description
L7- LO
S·bit bidirectional TRI·STATE'" 1/0 port
G3-Go
4·bit bidirectional 1/0 port
IN3-INo
4·bit general purpose input port
0
~
H3- HO
4·bit bidirectional 1/0 port
0
R7- Ro
S·bit bidirectional TRI·STATE 1/0 port
SI
Serial input
SO
Serial output (or general purpose output)
SK
Logic·controlled clock (or general
purpose output)
CKI
System oscillator input
CKOI
General purpose input
VRAM
Power supply for first 4 registers of RAM
MB
MICROBUSTM function select
DCK
Clock output to latch D outputs and high
order address bits
ADIDATA
Address out/data in flag
IP7-IPO
B·bit directional port Tor HUM aaaress,
ROM data and D outputs
RESET
System reset input
Vee
Power supply
Ground
GND
Figure 2. Connection Diagram
0
Pin
"'tJ
I\)
~
C')
"'tJ
I\)
Co)
C
~
Timing Diagram
1---_____________ INSTRUCTlON.iYCLET1ME tlcl
OK!
S'
VCC
MICROBUS FUNCTION OPTION SELECT
GNO
CKO FUNCTION
OPTION SELECT
Figure 4. COP2404 Used to Emulate a COP2440
3-72
o
o
."
Functional Description
The COP2404 Is a ROM less microcontroller for emlating
the COP2440 or for stand-alone applications. Please
refer to the COP2440 description for detail functional
description. The following describes functions that are
unique to the COP2404 or are different from those In
COP2440. All references to COP2404 also apply to
COP2304. Figures 1 and 2 show the COP2404 block diagram and pin-out.
Suppose we are looking at the IP port when processor X
Is executing. While DCK Is low, the upper three address
bits, P10-P8, of the next Instruction to be executed by
processor x are sent out to IP2-IPO respectively. D3-DO
are sent out to IP7-IP4. IP3 contains the SKIP output
which Is used by the COPSTM Program Development
System (PDS). These data are clocked Into D flip-flops by
the riSing edge of DCK. The timing of D port data Is then
the same for COP2404 and COP2440. After DCK goes to
a "1" level, the remaining address bits (P7-PO) are sent
out to IP7-IPO. They are latched Into flow-through
latches, e.g., 74LS373 when ADIDATA goes low. The
latched addresses provide the Inputs to the external
memory. When ADIDATA goes low, the IP lines become
program memory inputs from the external memory. Note
that DCK has twice the cycle frequency of COP2404 with
a duty cycle of about 50% and AD/DATA has twice the
cycle frequency with a duty cycle of about 75%. Figure 3
shows the timings for IP port, DCK and ADIDATA. Figure
4 shows how to emulate the COP2440 using a COP2404
and an EPROM as the external memory.
Program Memory
Program memory consists of 2048 bytes of external
memory (on-chip in the COP2440) that can be accessed
through the IP port. See External Memory Interface below.
D Port
The D3-DO outputs are missing from this 48-pin
package, but may be recovered through the IP port (see
External Memory Interface below). Note that the recovered signals have the same timing but different out!"Illl drive caoabilitv as those from the COP2440 (see D
Port Characteristics below).
~
o
."
N
~
~
ROM Interface Timing Example
MICROBUSTM and Zero-Crossing
Detect Input Option
The following example shows the timing relationship
between IP port 1/0 data (to and from external ROM) and
the present instruction that is being executed by a processor. A sample program starts with the following instructions:
The MICROBUS compatible 1/0, selected by a mask
option on the COP2440, is selected by tying the MB pin
directly to ground. When the MICROBUS compatible 1/0
is not desired, the MB pin should be tied to Vee. Note
that none of the IN inputs are Hi-Z. Since zero-crossing
detect input (used by INIL instruction and zero-crossing
interrupt feature) is chosen for IN1, the IN1 input "1"
level for ININ instruction, IN1 interrupt, and MICROBUS
input is 3V. Even though the MICROBUS option and
zero-crossing detector option appear on the COP2404,
they are mutually exclusive on the COP2440.
Oscillator
..... ,,' , .... -"
N
~
OP
ADD CODE
000 00
CLRA
;CLRA IS 1ST
INSTRUCTION
PROCESSOR X STARTS HERE
001
80
-----.
__
=_ ............. : ........... 1· Th ......... 1" .......
....- ............
-. _.- I __
.. ........ -. _..... .
frequency is divided by 16 to give the execution frequency.
JSRP CLREG ;CLEAR REGISTER
E
I~
~
SUBROUTINE PAGE
CKO Pin Options
080
081
082
083
Two different CKO functions of the COP2440 are
available on the COP2404. VRAM supplies power to the
lower 4 registers of RAM, and CKOI is an interrupt input
or a general purpose input, reading into bit 2 of A (accumulator) through the INIL instruction.
00
04
80
48
CLREG:CLRA
XIS
JP .-2
RET
PROCESSOR Y STARTS HERE
External Memory Interface
401 OE
402 333E
404 56
The COP2404 is designed for use with an external
program memory. This memory may be implemented
using any devices having the following characteristics:
1. Random addressing
2. TTL-compatible TRI-STATE® outputs
3. TTL-compatible inputs
4. Access time = 450ns maximum
Typically these requirements are met using bipolar or
MOS PROMS.
LBI
OBD
AISC
0,15 ;OUTPUT 15 TO D
6
;PUT 6TO
ACCUMULATOR
Figure 5 shows what IP inputs and outputs are in relationship with the instructions that are being executed
during the first few cycles of the above program.
3-73
C
~
Timing Diagram (Continued)
Q.
i
oo
PROCESSOR
X
X
Y
X
Y
X
000
ODD
DOD
401
001
402
Y
X
080
403
081
XISO
FO 1821
OCK
PRESENT
ADDRESS
INSTRUCTION
IP OUTPUTS
CLRA
CLRA
CLRA
LBI0.15·
JSRP80
OBO(l st byte)
CLRA
OBD(2nd byte)
00 1001
04 1011
00 1011
04 102 1
00 1801
04 1031
00 1811
FC 1041
IP INPUTS
NEXT
ADDRESS
IDE
100
000
401
133
180
001
080
402
13E
100
403
104
081
lao
156
404
082
D OUTPUTS
SKIP
NOTE: THE LAST 3 ROWS-NEXT ADDRESS. D OUTPUTS AND SKIP MAY BE DECODED FROM IP OUTPUTS
Figure 5. IP Port 1/0 Timing
110 Options
COP2404 Mask Options
All inputs except IN1 and CKI have on-chip depletion
load device to Vce. IN1 has a reSistive load to GND due
to the zero-crossing input. CKI is a HI·Z Input.
G and H ports have standard outputs. Land R ports
have TRI-STATE!!) outputs. IP port, DCK, AD/DATA, SO
and SK have push-pull outputs.
The f~lIowing COP2440 options have been implemented
in the COP2404.
Option
Option
Option
Option
Option
Option
Option
Option
Option
Option
LED Drive
The TRI-STATE outputs of L port may be used to drive
the segments of an LED display. External current limit·
ing resistors of 100 ohms must be connected between
the L outputs and the LED segments.
o Port 9haracteristics
Option
Option
Option
Option
Option
Option
Option
Option
Option
. Option
Option
Option
Option
Option
Since the 0 port Is recovered through an external latch,
the output drive is that of the latch and not that of
COP2440. Using the set·up as shown in Figure 4, at an
output "0" level of 0.4V, the 74LS374 may sink 10 times
as much current as the COP2440. At an output "1" level
of 2.4V, the 74LS374 may source 10 times as much
current as the COP2440.0n the other hand, the output
"1" level of 74LS374 latch does not go to Vee without ·an
external pull·up resistor. In order to better approximate
the COP2440 output characteristics, add a 74C906
buffer to the olitput of the 74LS374, thus emulating an
open drain 0 output. A pull-up resistor of 10k should be
added to the input of the buffer. To emulate the
standard output, add a pull-up resistor between 2.7k
and 15k to the output of the 74C906.
3-74
Value
Comment
1-2 = 3 L outputs are TRI-STATE!!)
3
=0 SI has load to Vee
4
= 2 SO is push-pull output
5
= 2 SK is push-pull output
=0 INO has load to Vce
6
7
=0 IN3 has load to Vec
8-11 = 0 G outputs are standard
12-15 = 0 H outputs are standard
16-19 = N/A 0 outputs are derived from external
latch, see Figure 4
20
= N/A GND - No option
21
= 1,2 CKO is replaced by VRAM and CKOI
22
= 0 CKI is input clock divided by 16
23
= 0 RESET has load to Vcc
24·31 = 3 R outputs are TRI-STATE
32-35 = 3 L outputs are TRI-STATE
36
=2 IN1 is zero-crossing detect input
37
= 0 IN2 has load to Vcc
38-39 =3 L outputs are TRI-STATE
40
= N/A Vee - No option available
41
=0,1 MICROBUS option is pin selectable
42-48 = 0 Inputs have standard TTL levels
49
= N/A No option available
50
= N/A48-pin package
Section 4
Piggyback
. Microcontrollers
II
~National
a
Semiconductor
COP420R/COP444LR Piggyback-EPROM Microcontroller
General Description
Features
The COP420R and COP444LR Piggyback-EPROM microcontrollers are members of the COPSTM family. The
COP420R and COP444LR devices are identical to the
COP420 and COP444L respectively except that the pro·
gram ROM has been removed. In place of the ROM each
device package incorporates the circuitry and socket to
accommodate the Piggyback·EPROM.
• Exact equivalent of the COP420 and COP444L plugs into same socket
• Socket and interface for industry standard EPROMs
• Self-contained voltage regulator for EPROM on
COP444LR
• Powerful instruction set
• True vectored interrupt, plus restart
• Three-level subroutine stack
• Compatible with all COPS family peripherals
• Internal binary counter register with MICROWIRETM
family peripherals compatible serial I/O
• Software and hardware compatible with other
~e~~e!"~ C'~ !!'"!e COPS fe~!!~1
• Single supply operation
• Internal presettable time base counter for real time
processing
• 41'S instruction time (COP420R)
• 16).1s instruction time (COP444LR)
The socket provided on the package accepts an
MM2716, NMC27C16, MM2758A, or MM2758B EPROM.
Each part is a complete microcontroller system with
CPU, RAM, I/O, and EPROM socket provided in a single
28-pin package. In a system the COP420R and COP444LR
will perform exactly as its mask programmed equivalent.
.,..~
_ _ _ _ _ 1_ .. _ _ _ _ ' . _ _ _ _ , , _ _ _
••• ~ .... Vlllt-"II;OL'C'
"'Q,","'Cl~'C'
1/"
•••
•
. '
~
QIIVVVi:) IICIU 1C'':;L UI d
:JiY;:)Lt::1I1 III
its final electrical and mechanical configuration. This
important benefit facilitates development and debug of
a COP400 program prior to masking of a production part.
These devices are also economical in low and medium
volume applications or when the program may require
changing.
• 23 I/O lines
COPS and M1CROWIRE are trademarks of National Semiconductor Corp.
r -_ _ _ _ _ _ _~12 GND
r-_ _ _ _ _~'A7
.--_ _ _ _-:-1' A6
.--_ _ _-"1' AS
. - - - - - , ' A4
.--_ _,5 A3
EPROM
SOCKET
COP444LR
A9 22
6 A2
AS 23
7 AI
n
1,111,,1, I. I r,1AO
VPROM
-f19
~
~
191615129652
08 07 06 05 04 03 02 01
Vee
GND
ONLY
18
O!F-
07 06 05 04 03 02 01 00
171615141311109
~
LE"
74C373
DUTDIS
08 07 06 05 04 03 D2 01
18 17 14 13
·rI"
r- VPRDM
H
5
22
9 10 36 ,
6 7 •
IP7 IPS IPS IP4 IP3 IP2 IP' IPO
F
33 35 34 32
AD! pa P9 SKIP!
PlD
Dill
,
1
,
~
40
39
COP404lP
DR
CDP402
,---l!
f!-fL-
r2!-
13
1"1"1"1171181"120121123124),52627)"129130.
GND
1
eKO CKI RESET 17 l6 15
234567
I I I I I I I I I I I II
l4 IN1 IN2 vee l3 l2 II lO 51 50 5K INO IN3 GO G1 G2
891011121314151617181920212223
Figure 1. COP420R/COP444LR Block Diagram
4·-3
G3 03 02 01 DO
2425262728
a:
...I
3
D-
oo
Ii:
~
oo
COP420R
Absolute Maximum Ratings
-0.3V to +7.0V
O°C to 70°C
-65°C to 150°C
300°C
see Figure 15
50mA
70mA
Voltage at any Pin
Operating Temperature Range
Storage Temperature Range
Lead Temperature (soldering, 10 sec.)
Package Power Dissipation
Total Sink Current
Total Source Current
Absolute maximum ratings indicate limits beyond which
damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at
absolute maximum ratings.
DC Electrical Characteristics
O°C to 70°C, 4.5V to 6.3V unless otherwise noted
Parameter
Operation Voltage
Power Supply Ripple
Supply Current
Input Voltage Levels
CKI Input Levels
Crystal Input
Logic High
Logic Low
Schmitt Trigger Input
RESET
Logic High
Logic Low
All Other Inputs
Logic High
Logic High
Logic Low
Input Load Source Current
Input Capacitance
Hi-Z Input Leakage
Output Voltage Levels
0, G, L, SK, SO Outputs
TTL Operation
Logic High
Logic Low
Ag-Ao, CKO Outputs
Logic High
Logic Low
CMOS Operation
Logic High
Logic Low
Output Current Levels
LED Direct Drive (COP402)
Logic High
Conditions
Min.
Max.
Units
4.5
6.3
0.4
V
V
mA
(peak to peak) note 3
All outputs open, no EPROM installed
38
2.0
-0.3
0.4
V
0.7Vee
-0.3
0.6
V
V
V
V
V
Vee = 5.0V, VIN = 0
3.0
2.0
-0.3
-100
0.8
-800
Vee = 5.0V
-1.0
7.0
+1.0
!,A
pF
!,A
Vee=5.0V±5%
IOH=-100!,A
IOL=1.6mA
2.4
-0.3
0.4
V
V
IOH = -75!-iA
IOL=400!,A
2.4
-0.3
0.4
V
V
IOH=-10!,A
IOL=10!,A
Vee- 1
-0.3
0.2
V
V
2.5
14
mA
10
2.0
16
10
mA
mA
mA
mA
-15
-1.5
mA
mA
Vcc=Max.
Vce = 5.0V ± 5%
Vee=6.0V
VO H =2.0V
Allowable Sink Current
Per Pin (L, 0, G)
Per Pin (all others)
Per Port (L)
Per Port (0, G)
Allowable Source Current
Per Pin (L)
Per Pin (all others)
4-4
V
o
AC Electrical Characteristics
Parameter
Conditions
Instruction Cycle Time
Operating CKI Frequency
CKI Duty Cycle (note 1)
Rise Time
Fall Time
Min.
Max.
Units
4.0
1.6
40
10
4.0
60
60
40
I-'S
MHz
%
ns
ns
.;.16 mode
Frequency =4.0 MHz
Frequency =4.0 MHz
Inputs:
SI
tSETUP
tHO LD
All other Inputs
tSETUP
tHOLD
Output Propagation Delay
SO and SK
tpD1
tpDO
CKO
tpD1
tPDO
ADIDATA
tpD1
t pDO
A7-AO
tpD1
t pDO
All other Outputs
tpD1
tpDO
o"'C
O°C to 70°C, 4.5V to 6.3V unless otherwise noted
~
o
"'C
~
tr-
:::D
0.3
250
I-'s
ns
1.7
300
I-'s
ns
Test Conditions: RL =5.0 k, CL =50 pF, VOUT =1.5V
1.0
1.0
I-'S
I-'s
U.LO
0.25
I-'S
I-'s
0.6
0.6
I-'s
I-'S
2.0
2.0
I-'s
I-'s
1.5
1.5
I-'s
1-'5
Note 1: Duty cycle = tW1/(tW1 + tWO).
Note 2: See Figure 6 for additional 1/0 characteristics.
Note 3: Voltage change must be less than 0.5 volts in a 1 ms period.
Note 4: Exercise great care not to exceed maximum device power dissipation limits when direct driving LEOs (or sourcing similar loads)
at high temperature.
-----GND
28
DO
CKO
27
01
CKI
26
02
A7
24
vee
RESET
25
03
A6
23
AS
17
24
G3
A5
22
A9
16
23
G2
A.
21
l5
22
G1
A3
20
vpp
Of (G)
l4
21
GO
A2
19
AIO
IN1
20
IN3
A1
18
CE/PGM (E/P)
10
19
INO
AD
17
07 (07)
Vee
11
18
'K
DO (ao)
16
06(06)
13
12
17
so
01 (Ol)
10
15
05(05)
12
13
16
SI
02 (02)
11
14
04(04)
l1
14
15
LO
Vss
12
13
03(03)
IN2
COP420
24 Pin Socket
Figure 2. COP420R Connection Diagrams
Pin
~
C
Description
Description
Pin
LrLo
G3-G O
8 bidirectional 1/0 ports with TRI-STATE®
ADIDATA
Address out/data in flag
4 bidirectional 1/0 ports
CKI
System oscillator input
0 3-00
4 general purpose outputs
CKO
General purpose input
IN3-INo
4 general purpose inputs
RESET
System reset ,input
SI
Serial input (or counter input)
SO
Serial output (or general purpose output)
SK
Logic-controlled clock (or general purpose
output)
Vee
GND
0 7-0 0
Ground
PROM data lines
Ag-AO
PROM address outputs
4-5
Power supply
a::
..I
ia..
0
~
S
a..
~
0
0
.
CKI
AD/DATA, SK
(AS A CLOCK)
IN3-INO,
G3-GO, L7-LO,
CKO " SI INPUTS
G3-GO, 03-00,
L7-LO, SO, SK
OUTPUTS
A8,A9
OUTPUTS
A7-AO
OUTPUTS
07-00
INPUTS
Figure 3a. COP420R Input/Output Timing Diagrams (Crystal + 16 Mode)
!W1 'I' 'I' 'I'!WO
CKISLJU
CKo~/l~/T
'PD1.-.!
~
-II--'PDD
Figure 3b. COP420R CKO Output Timing
Oscillator
There are two basic clock oscillator configurations
available for the COP420R as shown by Figure 4.
a. Crystal Controlled Oscillator. CKI and CKO are can·
nected to an external crystal. The instruction cycle
time equals the crystal frequency divided by 16.
b. External Oscillator. CKI is driven by an external clock
signal. The instruction cycle time is the clock frequency divided by 16.
SO, 5K Push· Pull Output
A
CKI
EXTERNAL
CLOCK
NOT USED
...I'U'"L
L7-LO LED Output
Component Values
Crystal
Value
Vcc
R1
R2
C
4MHz
1k
1M
27pF
3.58 MHz
1k
1M
27pF
2.09MHz
1k
1M
56pF
. rmt
#6
".,~~
Reset, 51, IN3-INo Input with Load
(.,5 DEPLETION DEVICE)
Figure 4. COP420R Oscillator
Figure 5. COP420R Input/Output Configurations
4-6
Input Current for Lo- L7
when Output Programmed
Off by Software
Reset, SI, IN3-INo Input
Load Current
-0.4
-0.75
P-.ct--f-+---+.:::-::t...-.f..=-I
-0.3
1.
-0.5
<.ftf-h
.§
~-O.2
l-
E
-0.25
l\
\
MAX
1::-+-f-A8------'1..-+--+----l
-0. 1
MIN
~
~
--'i
OEVICE 2
VOUT IVOLTS)
SO, SK Output Source
Current
-3
-2
ee t-Igure lZ ana I aOle Z.
The COP420R is shipped with jumpers A, E, and F
installed.
The COP444LR is shipped with jumpers B, C, and F
installed.
EPROM SOCKET
(TOP)
eeeGe8e88®®@
Figure 12. Jumper Locations
4-13
o"tJ
it
o
~o
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t
r-
::0
General Vee Considerations
The CPU portion of the COP420R is the COP402. The
Vee operating range for the COP402 is 4.SV to 6.3". The
CPU portion of the COP444LR is the COP404LP. The Vee
operating range for the COP444LP is 4.SV to 9.SV.
If the jumper at A is replaced by a diode the Vee operating range will be changed. For example, if the diode
voltage is O.BV and the EPROM selected Is 4.SV to S.SV
the operating range of the COP420R becomes:
Due to the fact that the Vee operating range for the
EPROMs is either 4.7SV toS.2SV or 4.SV to S.SV the
EPROMs become the Vee limiting device. Because of
these limitations jumpers have been added on the
COP420R; jumpers and a regulator have been added on
the COP444LR.
4.SV + O.BV toS.SV + O.BV or S.3V to 6.3V.
WARNING: THIS CHANGE SHOULD BE MADE WITH
EXTREME CAUTION. IMPROPER
INSTALLATION VOIDS WARRANTY.
Remove solder from jumper A and insert the anode of
the diode through the hole connected to the bottom of
the jumper A and the cathode of the diode through the
hole connected to the top of jumper A as shown in
Figure 13B.
A 0.1/AF decoupllng capacitor should be connected be·
tween Vee and Ground as close to the device as possible.
Vee Considerations for the COP420R
In the COP420R, jumper A is connected (Figure 13a).
With A in this configuration the Vee operating range be·
comes the Vee operating range of the EPROM selected.
I---+-Vcc
I----Vcc
a. Standard Configuration
b. Diode Configuration
H
=
.c;
'-:1e:: : ---::::e:-:8::::-~-::::8:-:e::::-~-::::e:-:8::::-~-::::e:-8::::-~-:::®:-®::::-::·-:::@~I
leeeeeeeee®®@1
c. Jumpers for Standard Configuration as Shipped
from NSC
o
o
o
o
d. Jumpers for Diode Configuration as Modified by User
Figure 13. COP420R Jumper Connections
4-14
(")
o
."
Vee Considerations for the COP444LR
Power Considerations for COP420R/COP444LR
In the COP444LR, jumper B is connected (Figure 14).
With B in this configuration the 5.0V regulator is con·
nected to the EPROM and the latch. The Vee range of
the COP444LR is then determined by the V1NIVoUT speci·
fication of the regulator; which is 2.0V. Therefore, the
Vce range of the COP444LR is 7.0v to 9.5V.
The absolute maximum power dissipation of the
COP420R and the COP444LR Is shown in Figure 15. In
addition, the COP444LR contains a regulator with an
absolute maximum power dissipation of 305 mW at 70·C.
For an MM2716 EPROM the maximum operating current
is 105mA and the maximum current in the standby
, mode is 30 mAo The COP444LR is designed such that
the EPROM is in the standby mode for 50% of the time.
Therefore the power consumed by the regulator is:
(9.5 - 5.0)(105 + 30)/2 = 304 mW.
If the jumper is removed from the B position and eon·
nected in the A position, the same limitations apply that
are discussed above in the section on Vee Considera·
tions for the COP420R.
WARNING: THIS CHANGE SHOULD BE MADE WITH
EXTREME CAUTION. IMPROPER
INSTALLATION VOIDS WARRANTY.
A
l
t-~---"""---VCC
s. Regulator Configuration
I®®®®®®®®®®®@I
WGDBecaif
H
=
=
<:::7
~
l
E
leeeeeeeee®®@1
I
lleeeeeeeee®®@1
=7.0 to 9.5 V as
c. COP444LR Jumpers for Vcc = 4.5 to 5.5 V as '
Modified by User
Figure 14. COP444LR Jumper Connections
1100
!i 1000
~ 900
51 800
I ~::
I'
'" 500
400
w 300
~
~..
200
100
o
o 10
615mW@25°C
Nil
I NI
I I
'I
'----_---J
'----_-----J
b. COP444LR Jumpers for Vcc
Shipped from NSC
H
=
ff:
"'!o..
270mW@70"C
I I
I I
20 3D 40 50 60 70 80 90100110
TEMPERATURE (OC)
Figure 15. Maximum Power Dissipation for the COP420R/COP444LR
4-15
~
~
o
i
r-
::D
a:
...I
-.:t
3Q.;
o()
~
o
~
Q.;
o()
mum current we need to set the voltage on the L pin = 4.8V
at 6.0 mA. The D line will sink this current at 0.4 V. There·
fore, the resistor and LED must make up the difference.
For the' absolute maximum power dissipation of the
COPS devices, all so,urces of power dissipation must be
taken into account. For example:
V, =Vo+ IR+ VLEO
4.8 = 0.4 + 0.006R + 2.0
2.4 = 0.006R
R=400Q
Wheh the COP outputs are used to drive loads directly
the power consumed in the outputs must be considered
in the maximum power dissipation of the package. Fig·
ure 16a shows an LED segment obtaining its source cur·
rent from the LO output and DO sinking that current. In
this configuration all the power required to drive the
LED, with the exception of the portion consumed by the
LED itself, is consumed within'the chip. Assuming that
the COP444LR is the driving device, Figure 11 shows the
currents available on these outputs.
At the other end of the curve, when the L line sources
the maximum curren't, assume the LED and the D line
will have the same voltage drop.
V,=0.4+IR+2.0
V, =2.4 + IR
If we assume the VSOlJRCE resistor is not inserted, the
device has a Vcc of 9.5 V, and that the voltage drop
across the LED is 2.0V we cim calculate the power dis·
sipation in these outputs. The minimum current that DO
can sink ai 1.0V is 35 mAo LO,can source up to 35 mA at
3.0V. Therefore, the power dissipation tor the LO output
could be: (9.5 - 3.0)0.035 = 227 mW. The power in the DO
output could be: 1(0.035) = 35 rnW.
From the curve of Figure 11 we see that at 6.4V the L line
will source 10 mAo Therefore: V, = 2.4 + 0.01 (400) = 6.4 V.
In the case of the D line driving the base of the PNP in
Figure 16b, let us assume the 420R with a Vcc of 4.5V, a
base to emitter reSistor of 5.1 kQ, VSE = 1.0V, and a worst
case base drive requirement of 3.0mA. We see that we
must supply 200~ to the base·emitter resistor to turn
the transistor on.
Figure 16b depicts the DO output driving the base of a
PNP transistor with a current limiting resistor. Without
the curent limiting resistor the absolute maximum sink
current of the DO output would be exceeded.
1.0V/S.1 kQ =200~
From Figure 6 we see that at 1.0V the D line can sink
3.2 mAo To calculate the value of the current limiting
resistor we have:
Current Limiting Resistor Calculations
In order to calculate the current limiting resistor for the
case shown in Figure 16a, LED Drive, we must refer to
Figure 11, LO-L7 output source current. This figure
shows that at Vcc = 9.SV the minimum current curve
peaks at 1= 6.0 mA and VSOURCE =4.8V. The current curve
is actually very flat between 4.0 and S.O volts. For maxi·
R = (Vcc - VSE - Vo)/1
R = (4.5 - 1.0 -1.0)/0.0032 = 780 Q
At 6.3V the D line can sink more than enough current at
0.3V, and if the VSE is 0.7V we can calculate the maxi·
mum D line current:
I = (Vee - VSE - Vo)/R
1= (6.3 - 0.7 - 0.3)1780 = 6.3 mA
LO
Vcc
400Q
-=
vcc
~&
VSOURCE
X-LEO
00
VSINK
-=
a. LED Drive
b. PNP Drive
Figure 16. COP Output Loading
4-16
o
o
Emulation of Other Members of the COPS™ Family
The pin configurations for members of the COPS family
of microcontrollers are shown in Figure 17.
The COP444LR will emulate the COP420L if the
limitations on ROM and RAM are observed. Also, with
appropriate pin scramblers, the COP444LR will emulate
the COP421L and COP422L.
The COP420R, with an EPROM, is an exact emulator for
the COP420. With appropriate pin scramblers, the
COP420R will faithfully emulate the COP421 and COP422.
The COP444LR can be used to emulate tile COP410L
and COP411L with a pin scrambler, but caution must be
used. The COP410L and the COP411L not only have less
ROM but the RAM registers are organized differently
and the stack only has two (2) levels.
The COP444LR, with an EPROM, is an exact emulator
for the COP444L. With a pin scrambler, the COP444LR
will emulate the COP445L.
l4
LS
CKO
20
GNO
VCC
20
L6
CKI
19
02
L3
L7
RESET
18
03
L2
RESET
L7
17
G3
CKI
L6
16
G2
DO
LS
1S
SK
SI
01
L4
7
14
SO
SO
G2
VCC
8
13
SI
G1
L3
12
LO
GO
L2
11
L1
GND
COP422
COP422L
10
GNO
28
GNO
24
DO
CKO
27
01
CKO
23
01
CKI
26
D2
CKI
22
02
RESET
25
D3
iim'f
21
03
L7
24
G3
L7
COP445L
COP421
COP421L
L6
L5
l4
VCC
L3
10
DO
20
G3
L6
19
G2
L5
18
17
G1
l4
21
GO
GO
IN1
20
IN3
16
SK
IN2
19
INO
1S
SO
VCC
18
SK
COP444L
COP420
COP420L
23
G2
22
G1
L2
11
14
SI
L3
17
SO
L1
12
13
LO
L2
16
SI
15
LO
L1
14
Figure 17. COPS Family Pin Configurations
4-17
i
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D
a:
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oo
a:
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oo
~ National
'
.
Semiconductor
PRELIMINARY
COP440R/COP2440R
Piggyback-EPROM Microcontroller
General Description
Features
The COP440R/2440R Piggyback-EPROM Mlcrocontrollers
are members of the COPSTM family. The COP440R and
COP2440R devices are Identical to the COP440 and
COP2440 respectively except that the program ROM has
been removed. In place of the ROM, each device package
incorporates the circuitry and socket to accommodate
the Piggyback-EPROM.
- Exact equivalent of the COP440/COP2440
The socket provided on the package accepts an MM2716
or NMC27C16. Each part Is a complete microcontroller
system with CPU, RAM, I/O, and EPROM socket provided
In a single 40-pin package. In a system, the piggyback
device will perform exactly as its mask-programmed
equivalent.
- 160 x 4 RAM, addresses up to 2k x 8 ROM
_ MicROBUSTM compatible
The complete package allows field test of a system In its
final electrical and mechanical configuration. This Important benefit facilitates development and debug of a
COP400 program prior to masking of a production part.
These devices are also economical in low and medium
volume applications or when the program may require
changing.
COPS and MICROBUS are trademarks of National Semiconductor Corp.
TRI.sTATE Is a registered trademark of National Semiconductor Corp.
- Socket and interface for industry standard EPROMs
- Two independent processors (COP2440)
- Dual CPU simplified task partitioning-easy to
program COP2440
- Enhanced, more powerful instruction set
- Zero-cros~lng detect circuitry
- True multi-vectored Interrupt from four selectable
sources (plus restart)
- Four level subroutine stack for each processor
(In RAM)
II 4"s execution time per processor (non-overlapping)
- Single supply operation (4.5V-6.3V)
- Programmable time-base counter for real-time
processing
- Software/hardware compatible with other members
of COP400 family
I
VCC~24:..oj~_-----_ _ _ _---.
12 GND
r.::. .::.::.::.~~=~~:-i:~
!
A5
r---->-I
5 A4
---t
A3
~7~ :I
Vh
~~CW:
0605 04030201
VPP~
o~ r.:h~3--:·4-0-----..,
1·1171615141311109
~0=8~07~06~0~50~40=3~02~01~
t:===
.::t~~C
.
+-
2 ..._ _ _ _...,
AID ti2~2~-_-_-.:-_-_-_-_-_-_-.:-.:-_-~'
A9 '23
I·W
SKIP
.~0~'~02~03~04l-~_~
C~:S175 ~~~ U
74LS373
[f
GNO
D8 D7 06 05 04 03 D2 Dl
GND ~
01 02013014 ! -='="_
I-H+++~--+-+---'
1:1'1'---'
DCK
1P1'P6IP5'P41P3'P2'P1,PO AD/iiAfA
GNO
.r-...
M8
VRAM r-
6" 8
y, _(j
DATA IN (01)
DON'T
CARE
""
SAR STATUS
(SARS)
!
SE {DATA OUT
LOW
USING
SE TO
CONTROL
LSB FIRST
OUTPUT
(DO)
r"
SELECT
BITO
<':.::::1 DON'T CARE
SGLlDIF
SELECT
' -_ _ _-..•....::.BI:..:T..:l~__'
MUX CONFIGURATION WORD
TRISTATE
j'
- - - - -
MUX
SEITLING
TIME
TRI-STATE-----j
I- ·1·
I'
I
_------'
DlSABLElfTINTll~NEXT CONVERSION CYCLE)
S§'C-:->§§§§?~
A/D CON' 'ERSION IN PROCESS
j-._ _I-,-
SHIFT
ENA~E
(SE)
DATA
OUT
(DO)
I
(01
DA'A SHIFTED MSB FIRST
•
I·
I
BIT 7
TRISTATE
-------------1
DATA S~ IFTED LSB FIRST
I r,
BIT 3
DATA HELD TlME+-FOR
ARBITRARY
~~~-.
I
BIT 4
BIT 5
•
BIT 6
I
BIT 7
DATA SHIFTED LSB FIRST
-----1
TRISTATE
m
1
r--'1
.-L.........J
TRI-STATE~
MSB
BIT 7
BIT 6
BI'
(8&80~)0" pUB t&8000" '(';&8000" '~&8000")
iJ&tdOO PUB t&tdOO '(';&tdOO '~&tdOO
MUX Addressing
2-, 4- and 8-channel multiplexer options are available.
These multiplexers are software configurable as singleended or differential inputs. The configuration and channel assignment of the multiplexer is accomplished with a
serial input word which must be preceded by a leading "1"
or start bit (leading zeros are ignored).
ing differential mode the sign may also be selected. Channel 0 may be selected as the positive input and channel 1
as the negative input or vice versa.
Data is always shifted in on the rising clock edge and
shifted out on the falling clock edge. The only exception is
the ADC0831 which requires no input data since it does
not have a multiplexer. If CS goes high, the conversion is
stopped and all internal circuitry is reset. If another conversion is desired, CS must make a high to low transition
followed by address information.
Differential inputs are restricted to adjacent channel
pairs. For example channel 0 and channel 1 may be
selected as a differential pair. Channel 0 or 1 cannot act
differentially with any other channe!.ln addition to select-
TABLE I. MULTIPLEXER/PACKAGE OPTIONS
Part
Number
Alternate
Part Number
ADC0831
ADC0832
ADC0834
ADC0838
COP431
COP432
COP434
COP438
Number of Analog Channels
Single-Ended Differential
Number of
Package Pins
1
1
2
4
0
2
4
8
8
8
14
20
TABLE II. MUX ADDRESSING: ADC0838
Single· Ended MUX Mode.
Analog Single· Ended Channel #
MUX Address
SGU 0001 SELECT
DIF SIGN 1
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
0
0
0
1
1
0
1
0
5
4
3
2
6
7
COM
-
+
+
-
+
+
+
1
-
+
+
1
-
+
Differential MUX Mode
MUXAddress
SGU 0001 SELECT
DIF SIGN 1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Analog Differential Channel-Pair #
1
0
0
1
+
-
-
+
5-8
2
2
3
+
-
-
+
3
4
5
+
-
-
+
6
7
+
-
-
+
MUX Addressing
(Continued)
TABLE III. MUX ADDRESSING: ADC0834
Single·Ended MUX Mode
SGU
DIF
1
1
1
1
Channel #
MUXAddress
SELECT
0001
1
SIGN
0
0
1
1
0
1
2
3
+
0
1
0
1
+
+
+
COM is internally tied to A GND
Differential MUX Mode
SGU
DlF
0
0
0
0
MUXAaaress
SELECT
0001
1
SIGN
0
1
0
0
0
1
1
""nanntH
If
0
1
2
3
+
+
-
-
+
-
+
1
TABLE IV. MUX ADDRESSING: ADC0832
Single·Ended MUXMode
Channel #
.... ...,
_
"' ....... ,
DIF
SIGN
0
1
1
0
1
+
1
+
COM is internally tied to GND
Differential MUX Mode
MUX Address
SGLI
0001
DIF
SIGN
Channel #
0
1
0
0
+
-
0
1
-
+
5-9
Typical Applications
(Continued)
MUXADDRESS
~::::=i:::::::;::::::;:::::~-o5VDC
-START BIT
5lk(41
SGL/ffii;
Ne
INPUT SHIFT REGISTER
DO
10
14
74Cl&5
SVoc
6Voc
1
STARTt---+--=i-.....I
PUSHT
START THE
N•
AID CONVERSION
CLR
OUTPUT SHIFT REGISTER
QA
11
11·
10
74C184
NSL5G27 (II
·Plnouts shown for COP43B.
For all other products tie to
pin functions as shown.
DATA DISPLAY
A "Stand-Alone" Hook-Up for COP438 Evaluation
5-10
t
17
t. t
010
CS 0 lB
R
START
R
t
.1
I
J
R
5-81T SHIFT REGISTER
SGL/Oii'
ODD/SIGN
I
8
',
"'0
~
w
CO
R
SELECT 1
"11
c:
SEll
I
16
• I
::::J
I ~ TART CONV AND ENABLE TSL OUTPUT BUFFER
2.
CLK
1
CH 0'
CH 1*
3
CH 2*
4
CH3'
5
....
......
, .....
......
,.....
..
....
, ...... I , ......
9
....
.........
,.....
-
,.....
-
, ....
~
c
iii"
CD
3
ANALOG
MUX
(EQUIVALENT,'
---<
I
I , .....
0
VCC0 20
,
19
10
""'1
A GNo 011
~
EOC
C
.6
,
,
J
i!F
---f-,
TO INTERNAL
B5
SAR
LOGIC
AND
LATCH
CIRCUITRY
7V ZENER
v"
+
R
r; '7
12
cs
CS
COM*
VREF
I»
;;
.........
.....
,...... I '''''''
B
CH 7'
-
~
., ...... I ,......
CH 6*
.....
I , .....
7
CH 5
::::J
g
~~
....
, ..... I , .....
, ...... I , ......
\
§E'
,NOTE 1
+1-1 (
.....
6
NOTE 1
m
..........
....... I , ......
,.....
CH4
~
,......
.....
,.....
2
CJI
C)"
13
MUX
ADDRESS
VCC
~
INPUT
INPUT PROTECTION
L
L
I
4
TO
INTE lNAL
CIR[ JlTS
B4
B3
B2
9·BIT
SHIFT
REGISTER
cs ......~
~oO
Bl
COMP
ALL LOGI : INPUTS.
"rf
*Some of these functions/pins are not available with other options.
Nolo 1: For the COP434, DI is input directly to the D input of SELECT 1. S ,LECT 0 is forced to a "1".
(8&8000V pUB t&8000V '~&900aV '~&800aV)
8&tdOO pue t&tdOO '~&tdOO '~&tdOO
ooco
"'=too
('1)('1)
0.0
00
00
"C:(
C"
«1C
"'=t«1
('I)"'=t
"'=t('l)
0.00
00
00
~O
~c:(
"'=t
~
o.C'II
O~
0 0
~O
...-0
~c:(
0.
~
02;
0 00
0
0
Connection Diagrams
COP434 4·Channel MUX
COP438 8·Channel MUX
Dual·ln·Llne Package
Dual·ln·Line Package
20
CH 0
VCC
19
CH 1
18
CH 2
17
CH 3
v+
V+
cs
Cs
01
CH4
16 ClK
CH 5
15 SARS
CH 0
ClK
CH 1
SARS
CH 2
14
CH 6
CH 3
13 _
SE
COM
12 VREF
VREF
AGNO
o GNO
DO
CH 7
6
TOP VIEW
0
:$.
o GNO
10
11
Order Number COP434BN, COP434CN
NS Package N14A
A GNO
TOP VIEW
Order Number COP438BN, COP438CN
NS Package N20A
COP432 2·Channel MUX
COP431 Single Differential Input
Dual·ln·Line Package
Dual·ln·Line Package
VCC
CS
ClK
VIN(+)
DO
VIN(-)
GNO
01
7
6
4
5
elK
DO
VREF
TOP VIEW
TOP VIEW
Order Number COP432BN, COP432CN
NS Package N08A
Order Number COP431BN, COP431CN
NS Package N08A
Ordering Information
# of Maximum
Analog Input
Channels
8
8
4
4
2
2
1
1
Linearity
LSBs
± 1/2
±1
± 1/2
+1
± 1/2
±1
± 1/2
±1
Part Number
ADC0838BCN
ADC0838CCN
ADC0834BCN
ADC0834CCN
ADC0832BCN
ADC0832CCN
ADC0831BCN
ADC0831CCN
5-12
COP438BN
COP438CN
COP434BN
COP434CN
COP432BN
COP432CN
COP431BN
COP431CN
o
~National
o
COP452/COP453 and COP352/COP353
Frequency Generator and Counter
o
a
~
Semiconductor
~
~
en
~
o
General Description
Features
The COP452/COP453 and COP352/COP353 are peripheral
members of the COPSTM family fabricated using Nchannel silicon gate MOS technology. Containing two
independent 16-bit counter/register pairs, they are well
suited to a wide variety of. tasks involving the measurement and/or generation of times and/or frequencies.
Included in the features are multiple tone generation,
precise duty cycle generation, event counting, waveform
measurement, frequency bursts, delays, and "white
noise" generation. An on-chip zero crossing detector can
trigger a pulse wl.th a programmed delay and duration.
Th~ (,:OP4'5~ !~ !d~!"!t!':~! !':I !~e C0P"!52, b~! ::;::::-:.!:: ":::!h
supply voltages up to 9.5 volts. The COP352/COP353 are
extended temperature versions of the COP452/COP453,
respectively. The COP352/COP353 are functional equivalents of the COP452/COP453.
• Unburdens microcontroller by performing "mundane"
tasks
The COP452 series peripheral devices can perform
numerous functions that a microcontroller alone cannot
perform. They can execute one or more complex tasks,
attaining higher accuracies over a broader frequency
range than a mlcrocontroller alone. These devices remove repetitive yet demanding counting, timing, and
frequency related functions from the microcontroller,
thereby freeing It to perform other tasks or allowing the
use of a simpler mlcrocontroller In the system.
• Wider range and greater accuracy than microcontroller alone
• Generates frequencies, frequency bursts, and complex waveforms
• Measures waveform duty cycle
• Two independent pulse/event counters
• True zero crossing detector triggers output pulse
• Compatible with all COP400 mlcrocontrollers
• MICROWIRETM compatible serial I/O
• 14-pln package
• Single supply operation
(4.5-6.3V, COP452; 4.5-5.5V, COP352)
(4.5-9.5V, COP453; 4.5-7.5V, COP353)
• Low cost
• Crystal or external clock
(25kHz to 4.44 MHz, COP452/COP453)
(64 kHz to 4.0 MHz, COP352/COP353)
• TTL compatible
MICROWIRE and COPS are trademarks of National Semiconductor Corp.
TRI-STATE Is a registered trademark of National Semiconductor Corp.
CKI
1.
eKD
L
DI
0.
Z/
ZOI~-----....I
IN':t=~C)--..l-+-1
DB
EN'
">--n_ _
•
IICC
~~oo
GND
Figure 1. COP452/COP453, COP352/COP353 Block Diagram
5-13
o""D
w
~o
""D
~
w
Absolute Maximum Ratings
Voltage at any pin (except ZI) relative to GND
COP452
-0.5 V to + 7.0V
COP453
-0.5Vto +10V
Voltage at pin ZI relative to GND
-0.8V to +10V
Sink current, output OA
15mA
Sink current, all other outputs
5mA
Total sink current
35mA
Source current, outputs OA,OB
Source current, all other outputs
Total source current
Ambient operating temperature
Ambient storage temperature
Lead temperature (soldering, 10 sec.)
Power dissipation
5mA
1mA
10mA
O°C to +70°C
-65°C to +150°C
300°C
0.5 Watt at 25°C
0.2 Watt at 'WOC
Absolute maximum ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings.
O°C ~ TA ~ 70°C, 4.5 V ~ Vee
unless otherwise specified
DC Electrical Characteristics
Parameter
Conditions
Operating Voltage {Veel
COP452
COP453
Operating Supply Current
Input Voltage Levels
CKI Input Levels
Logic High (VIH)
Logic Low {Vld
DI,INB,ENB,SK,CS
Logic High
Logic High (VIH)
Logic Low (Vld
ZI Input Voltage
Min.
Max.
Units
4.5
4.5
6.3
9.5
V
V
14
12
mA
mA
0.4
V
V
V
0.8
+10
V
V
V
V
All outputs open
TA = O°C, Vee = Max.
TA = 25°C, Vee = Max.
3.0
2.0
Vee = Max.
Vee = 5.0V ± 5%
3.0
2.0
Vee = Max.
Vee=5.0V±5%
-0.8
Impedance to GND at ZI
2.6
7.8
kQ
150
mV
0.4
V
V
(Note 2)
(Note 2)
(Note 3)
15
5.0
35
mA
mA
mA
(Note 2)
(Note 2)
(Note 3)
-5.0
-1.0
-10
mA
mA
mA
ZI Offset Voltage
(Note 1)
Output Voltage Levels
TTL Operation
Logic High (VOH)
Logic Low {Vou
Vee=5.0V±5%
IOH =100,..A
IOl= -1.6mA
Maximum Allowable Output
Current Levels
Sink Current
OA
All Other Outputs
Total Sink Current
Source Current
OA,OB
All Other Outputs
Total Source Current
~ 6.3 V (COP452), 4.5 V ~ Vee ~ 9.5 V (COP453)
2.4
Note 1: ZI offset voltage Is the absolute value of the difference between the voltage at ZI and ground (pin 9) that will cause the zero detect
circuit output to change state. This is the maximum value which takes into account the worst case effects of process, temperature, volt·
age, and gain variation.
Note 2: The maximum current for the specified pin must be limited to this value or less.
Note 3: The total current In the device must be limited to this value or less.
5-14
o
COP452/COP453
AC Electrical Characteristics
Duty Cycle
Rise Time (t,)
O°C .. TA .. 70°C, 4.5 V .. Vcc .. 6.3 V (COP452), 4.5 v .. Vcc" 9.5 V (COP453)
unless otherwise specilied
Min.
Max.
Units
+4 mode
+1 mode
100
25
4440
1110
kHz
kHz
+4
+1
30
45
55
55
%
%
50
40
ns
ns
Parameter
CKI Input Frequency (liN)
o""0
Conditions
IIN=4.44MHz
liN = 4.44 MHz
Fall Time (ttl
~
o
o""0
01:00
en
JA'
o
o""0
(0)
en
~
SK Input Frequency
SK Duty Cycle
25
30
250
70
kHz
Internal Clock Frequency (II)
25
1110
kHz
o""0
I nternal Count Rate
0
11/2
Hz
(0)
11/131072
11/2
Hz
Output Frequency
%
Inputs
01
I
~
.. -
Rnn
tSETUP
tHOLD
1.0
fls
Outputs
CKO
tpd1
tpdQ
CL=50pF
0.2
0.2
fls
fls
OA,OB
tpd1
tpdQ
CL=50pF
0.4
0.3
fls
fls
ZO
tpd1
tpdQ
ZI = sine wave (Figure 4)
0.7
0.6
fls
fls
DO
tpd1
tpdQ
CL =50pF
1.0
0.6
fls
fls
5-15
o
(0)
en
(t)
It)
(t)
c..
oo
N
~
c..
o
o
Absolute Maximum Ratings
Source current, outputs OA,OB
Source current, all other outputs
Total source current
Ambient operating temperature
Ambient storage temperature
Lead temperature (soldering, 10 sec.)
Power dissipation
Voltage at any pin (except ZI) relative to GND
COP352
-0.5Vto +7.0V
COP353
-0.5V to +10V
Voltage at pin ZI relative to GND
-O.BVto +10V
Sink current, output OA
15mA
Sink current, all other outputs
5mA
Total sink current
35mA
(t)
It)
oc:t
5mA
1mA
10mA
-40·Cto +B5·C
-65·Cto +150·C
300·C
0.5 Watt at 25·C
0.125 Watt at B5·C
c..
Absolute maximum ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifIcations are not ensured when operating the device at absolute maximum ratings.
N
~
DC Electrical Characteristics
oo
-40·C';; TA ,;; B5·C, 4.5 V';; Vee';; 5.5 V (COP352), 4.5 V';; Vee';; 7.5 V (COP353)
unless otherwise specified
c..
oo
Parameter
Conditions
Operating Voltage {Veel
COP352
COP353
Operating Supply Current
Input Voltage Levels
CKI Input Levels
Logic High (V1H)
Logic Low (V1d
DI,INB,ENB,SK,CS
Logic High
Logic High (V 1H)
Logic Low (Vld
ZI Input Voltage
Max.
Units
4.5
4.5
5.5
7.5
V
V
15
12
rnA
rnA
0.3
V
V
V
0.6
+10
V
V
V
V
All outputs open
TA = -40OC, Vee = Max.
TA = 25·C, Vee = Max.
3.0
2.2
Vee = Max.
Vee = 5.0V ± 5%
3.0
2.2
Vee = Max.
Vee =5.0V±5%
-O.B
7.B
kQ
150
mV
0.4
V
V
(Note 2)
(Note 2)
(Note 3)
15
5.0
35
rnA
rnA
rnA
(Note 2)
(Note 2)
(Note 3)
-5.0
-1.0
-10
rnA
rnA
rnA
Impedance to GND at ZI
2.6
ZI Offset Voltage
(Note 1)
Output Voltage Levels
TTL Operation
Logic High (VOH)
Logic Low (Vou
Vec = 5.0V ± 5%
IOH =100flA
IOL= -1.6mA
Maximum Allowable Output
Current Levels
Sink Current
OA
All Other Outputs
Total Sink Current
Source Current
OA,OB
All Other Outputs
Total Source Current
Min.
2.4
Note 1: ZI offset voltage Is the absolute value of the difference between the voltage at ZI and ground (pin 9) that will cause the zero detect
circuit output to change state. This is the maximum value which takes into account the worst case effects of process, temperature, volt·
age, and gain variation.
Note 2: The maximum current for the specified pin must be limited to this value or less.
Nota 3: The total current in the device must be limited to this value or less.
5-16
o
COP352/COP353
AC Electrical Characteristics
Parameter
CKI Input Frequency (liN)
Duty Cycle
o
."
-40'C~ TA~ +85'C, 4.5V~ Vcc ~ 5.5 V (COP352), 4.5V~ Vcc~ 7.5V(COP353)
unless otherwise specilied
Min.
Max.
Units
+4 mode
+1 mode
256
64
4000
1000
kHz
kHz
+4
+1
35
50
55
55
%
%
Conditions
Rise Time (t,)
IIN=4.0MHz
50
ns
Fall Time (tt)
IIN=4.0MHz
40
ns
SK Input Frequency
25
250
kHz
SK Duty Cycle
30
70
%
Internal Clock Frequency (II)
25
1000
kHz
Internal Count Rate
0
11/2
Hz
11/131072
11/2
Hz
Output Frequency
01
ns
800
1.0
tSETUP
tHOLD
I's
Outputs
CKO
tpd1
tpdo
C L =50pF
0.25
0.25
OA,OB
tpd1
tpdO
C L =50pF
0.45
0.35
I'S
I's
I'S
I's
ZO
tpd1
tpdO
ZI = sine wave (Figure 4)
0.8
0.7
I'S
I's
DO
tpd1
tpdo
C L =50pF
1.1
0.7
I's
I'S
5-17
C;
~
o
o
."
0l:Io
C1I
~
o
o."
~
o
."
~
Co)
C")
LD
C")
Il.
0
0
CKI
CKI
~
C")
Il.
0
0
CKO
OA,OB
tpdO
ctf
~
Il.
IDA, DB CHANGES ON POSITIVE GOING CKI)
Figure 2b. OA alid 08 Output Timing
Figure 2a. CKO Output Timing
0
0
N
~
SK~
Il.
0
0
tHOLO
tSETUP
01
......
.-
tpdl/-
tpdO
.I.I..JfvOH
DO _ _ _ _ _ _
I"lgure 3a. Synchronous Data Timing
SK
Dt
M=1 FOR MODE
= 0 FOR INSTRUCTION
Figure 3b. Instruction Timing (Except Read/Write)
~~~
______________________________
~r-
.IlflIL-
SK
r--~~'~-~rl~
DI
L.--------.l.--.JI'o.=::::.II--I
~
.1
1 - - - - 1 6 DATA BITS
Figure 3c. Write Instruction Timing
~
____________________
~r--
JUL
SK
01
TRI·
I TRI·
DOSTATEIr--::;::~~:::-::~::::-:;==-::=="=.'-::::::=::::-""\J",::,:~.r--\l/~
~
A/hI - READ REGISTER A
=0 - READ REGISTER B
16 DATA BITs----l
Figure 3d. Read Instruction Timing
5-18
o
o"tI
.j:Io
ZI VOFFSET
oV
--::~t::::::::::::~:;:~::::::::::::::~~::::=
U1
~
o
"tI
~
J~
o
ZO
o"tI
CJ,)
Figure 4a. ZO Timing.
VOFFSET
~
> OV
o"tI
CJ,)
U1
CJ,)
~
L
ZI v~c~~~ ---/r---------'~\-------7r----
/
ZO
Ipd1
Ipd1
Figure 4b. ZO Timing,
Pin
Description
VOFFSET
< OV
Description
Pin
ZO
Zero Cross Output Signal
CKI
Crystal Oscillator Input
OA
Counter A, Logic Controlled Output
GND
Ground
_VUIILCI
Lol, J;;.A~t::IIIClI IlIfJUL
ENB
Enable for INB
OB
Counter B Output
Vee
CKO
Power Supply
v~
vnip ::ieleel
SK
Serial Data I/O Clock Input
01
Serial Data Input
DO
. ZI
Crystal Oscillator Output
Serial Data Output
AC Wavefo~ Input, Counter A External Input
ZO
ZI
OA
00
INB
ENB
DB
3
eOP452
eOP453
eOP352 11
eOP353 10
Of
SK
cs
Vee
GNU
eKO
eKI
Order Number COP452N, COP352N
NS Package N14A
Order Number COP452D, COP352D
NS Package D14A
Figure 5. Pin Connection Diagram
5-19
Output Characteristics
DO Source Current
OA,OB Source Current
, 1M IN
IMAX IMAX .IMAX
1.75 r-@Vee- @Vee-@Vee-@Vee
=4.5V =6.3V 9.5V
=6.3V ...
1.5
t
_ 1.25
/
0.75
1\ \
IMIN
@Vee
=4.5V
0.25
\
\ \\
o
o
1
3
!\
1
\
4
5
7
1/ IMIN@v~e=6.3~_
r
/
I
I
I
o
o
8
I
IMAX@Veej4.5V_
/ 1/ I~MAi
1/ / /
g
0.5
IMIN
2.25 r - @Vee
r - /4.5V
IMIN@Vee=4.5V
IMiN t-@Vee
9.5V ;--
c
.s:c
ZO Source Current
2.5
10
@Vee
\
1.5
'"i:
1.25
1
g
~
fi::I..
1 2 3 4 5
VOH(VI
6
7
\
\
0.5
0.25
"'t-..
o
9 10
8
IMIN
@Vee
=9.5V
I
0.75
@9~~~-
~
/iMA~@d+=
<"
E
,;MAX.__
@ Vee
\9.5V,-IMIN -
,
IMAX @ Vee =4.5V-
1.75
i
1\\ =6.3V
Z~IN ~@ ~ee!6.3Iv+
\ \
\ \
"-
~
\.
I\,
r--..
~
1"1.
o 1 2 3 4 5 6 7 8 9 10
VOH(VI
VOH(V)
c.
b.
8.
IMAX._
@Vee
'{.5V -
DO,ZO,OB Sink Current
OA Sink Current
16r-;--r-;--r-'--r--~
141-1i1=j:j:=:j:::::;;IF
12
0.2
0.4
0.6
0.8
1fII;:lf=:A===!:=
2
1.0
VOL (VI
I~AX @ Vee = 4.5V
I~IN
=5r
1.25
@Vee
l
§
i\r-
f-
0.5
0.25
1\
IIMIN
@Vee
\
\
f-=t 1\
5V
o
o
IM~X
1.75
@Vee
5.5V
1
I-
3
ZO Source Current
OA,OB Source CUrrent
[0-
0.75
e.
Figure 6. COP452/COP453
DO SOurce Current
1.5
6
VOL (VI
d.
1.75
3
...s
<"
IMIN
@vee
1.5 r--h-+-H-f-~-tr-+--I---l
t--t+;.-+t-l\-~-tt-+-
_ 1.25
~4~\I--l'H
:c
g
g
rv
0.5
IMAX
@Vee
=~.5V
0. 25
1·
4
VOH(V)
3
4
5
6
7
3
VOH(VI
c.
b.
8.
4
VOH(VI
DO;ZO,OB Sink Current
OA Sink Current
16r-'--r-'--r-'-~~--'
14~ttt=~~~~~~
12 . .-lI--hPi_
.
_ 10
~+-C;<+---=l=
~ 8~Hr?P~~+-1--+~~
g
0.2
d.
0.4
0.6
VOL (VI
0.8
3
1.0
4
VOL (V)
Figure 7. COP352/COP353
5-20
e.
5
5
o
Functional Description
A block diagram of the COP452 is given in Figure 1.
Positive logic is used. The COP452 can execute ten in·
structions as indicated in Figure 8a. and has eleven
operating modes. The operating mode is under user
software control.
The COP452, COP453, COP352, and COP353 are func·
tionally identical devices. They differ only in Vee range
and/or operating temperature range, and certain electri·
cal parameters associated with those temperature and
voltage ranges. The following information will refer only
to the COP452. All the information, however, applies
equally to the COP452, COP453, COP352, and COP353.
The device basically consists of two sixteen bit shift
registers and two sixteen bit binary down counters
organized as two register·counter pairs. In most operat·
ing modes, the two register·counter pairs are completely
independent of one another. For frequency generation,
both the register and counter of a given pair are utilized.
The counter counts down to zero where a toggle flip flop
is toggled. Then the data in the register is loaded, auto·
matically, to the counter and the process continues. A
similar procedure is used in the duty cycle mode and
number of pulses modes. For counting, the counters
count the pulses at their respective Inputs. There is no
automatic counter-register transfer in the count modes.
The counters wraparound from 0 to FFFF in the count
modes. Data I/O is via the serial Dort and the registers.
The counters are not involved in the input/output process
at all.
Instruction Set and Operating Modes
The COP452 has ten instructions and eleven operating
modes as indicated in Figure 8. The information for the
instruction or mode is sent to the COP452 via the serial
interface. The MSB is always a "1" and is properly viewed
as a start bit. The second MSB identifies the communi·
cation as an instruction or a mode. The lower four bits
contain the command for the device.
Opcode I
Ilnstruc'l
lion
MSB LSB
LDRB
LDRA
RDRB
RDRA
TRCB
TRCA
TCRB
TCRA
CK1
CK4
LDM
100000
100001
100010
100011
100100
100101
100110
100111
101000
101001
11xxxx
Comments
Load register B from DI
Load register A from DI
Read register B to DO
Read register A to DO
Transfer register B to counter B
Transfer register A to counter A
Transfer counter B to register B
Transfer counter A to register A
CKI divide by one
CKI divide by four
Load mode latches
The device requires a low chip select signal. When the
device is selected (CS low) the driver on the DO pin is
enabled and the device will accept data at 01 on each
SK pulse. When the device is deselected (CS high) the
DO driver is TRI·STATE'" and the I register is reset to O.
Note that chip select does not affect any other portion
of the device. The mode latches are not affected. The
COP452 will continue to operate in the mode specified
by the user until the mode is changed by the user.
The COP452 contains a clock generator. The user may
connect a crystal network to CKI and CKO or he may drive
CKI from an external oscillator. Certain RC and LC
networks may also be used. See the applications section
for further information.
Figure 8a. COP452 Instruction Set
ODeratina Mode
I MSBOpcodeLSB I
Reset
Dual Frequency
Frequency and Count
Dual Count
Numberof Pulses
Duty Cycle
Waveform Measurement
Triggered Pulse
Triggered Pulse and Count
White Noise and Frequency
Gated White Noise
111111
110000
110100
110101
110010
110011
110110
110001
110111
111000
111001
The user also has control over whether the clock gener·
ator divides the CKI signal by 4 or 1. This allows the user
to quickly get a 4 to 1 change in frequency output or
input count rates. Alternatively, it allows the user to use
a higher speed crystal or clock generator. The internal
clock frequency (the frequency after the divider) must
remain between the specified limits to guarantee proper
operation. The state of the divider is not affected by CS.
There is an internal power·on reset circuit which places
the device in the Reset mode (mode latches all set to 1)
and sets the clock divider to divide by four. If the CKI
frequency is less than four times the minimum internal
frequency the first access of the COP452 must be the
command to set the divider to divide by 1. This command
will be accepted and will be processed. Proper operation
of the COP452 is not guaranteed if the internal fre·
quency is less than the specified minimum. The power·
on reset circuit does not affect the counter and regis·
ters of the COP452.
Figure 8b. COP452 Operating Modes
5-21
o
"0
~
c.n
~
o
o"0
~
c.n
$>l
o
o
"0
Co)
c.n
~
o
"0
Co)
c.n
Co)
C")
Lt)
C")
Il.
Instruction Description
oo
1. Load Register (LDRA/LDRB) - The selected register
(AlB) is loaded with 16 bits of data shifted in on DI
and clocked in by SK.
C")
2. Read Register (RDRA/RDRB) - The data in the selected register (AlB) is shifted out serially onto DO.
At the same time the data is recirculated back to the
register.
~
Il.
oo
M
Lt)
ooqIl.
oo
N
Lt)
ooqIl.
oo
Where:
A = Contents of register A
8 = Contents of register 8
t = Period of internal clock
= Period of CKI oscillator (.;-1 mode)
= 4 x period of CKI oscillator (.;-4 mode)
Period of output square wave = 2(N + l)t
Where t is defined above
N = Contents of register
3. Load Counter (TRCA/TRCB) - The contents of the
selected register are transferred to its associated
counter. (Counter A is loaded from register A; counter
B is loaded from register B). The contents of the register are unaffected.
o .;
N .; 65535 (0 .; N .; FFFFI6)
3. Frequency and Count - A single frequency is output
at OA. Counter B counts external pulses on INB (when
ENB =1). There is no automatic clear of the counter.
Since counter B counts down from whatever state it
is in it is usually desirable to preload the counter.
Preloading the counter with all zeroes will give the
two's complement of the count.Preloading the
counter with all ones will give the one's complement
of the count.
4. Copy Counter (TCRAITCRB) - The contents of the
selected counter are transferred to its associated
register. (Counter A loads register A; counter B loads
register B). The contents of the counter are unaffected.
5. CKI Divide by One - The oscillator divider at the CKI
input is set to divide by one. The internal frequency is
therefore equal to the CKI frequency. This instruction
should not be used if the CKI frequency is greater
than the maximum internal frequency.
OA
6. CKI Divide by Four - The oscillator divider at the CKI
input is set to divide by four. The internal frequency is
therefore equal to one-fourth of the CKI frequency.
This instruction should not be used if the CKI frequency is less than four times the minimum internal
frequency.
Where:
7_ Load Mode Latches - The four mode latches are
loaded with the lower four bits of the instruction.
06 toggles each time counter 8 counts through zero.
Mode Description
Where:
1_ Reset Mode - This mode sets OA and OB to "0". The
mode latches are all set to "1". No counting occurs;
the COP452 is in an idle condition. The registers and
counters are not altered in any way.
Minimum pulse width required for reliable counting = t
where t = period of internal clock.
2. Dual Frequency - Two frequencies are generated one at output OA and one at output OB. The period of
the square wave at OA is determined by the contents
of register A. The period of the square wave at OB is
determined by the contents of register B. In frequency
generation modes, the counters count down until
they reach zero. At that point the output toggles and
the counters are automatically loaded from the res·
pective registers. The counters are only loaded when
they count down to zero. Therefore it may be necessary to initially load the. counters. The frequency
outputs at OA and OB are completely independent of
one another. The respective counter inputs (INB, ZI)
have no effect on the counters in this mode.
4. Dual Count - In this mode counter A and counter B
are enabled as external event or pulse counters.
Counter A counts pulses at ZI and counter B counts
pulses at INB (when ENB = 1). There is no automatic
clear of either counter. Each counter counts down
from whatever state it starts in. Thus, to ease reading
the information, the counters should be preloaded.
Preloading the counters with all zeroes will give the
two's complement of the count. Preloading the counters with all ones will give the one's complement of
the count. The cirCUitry which decrements the count· .
ers is enabled by the high to low transition at the
count input. There is no interaction between the two
register counter pairs.
A = Contents of register A
t = PeriOd of internal clock
(as previously defined)
0.; A'; 65535 (0 .; A'; FFFFI6)
Maximum count rate at IN8 = fl/2
fl = Internal clock frequency
= CKI input frequency (.;-1 mode)
=CKI input frequency.;-4 (.;-4 mode)
OA toggles every time counter A counts through "0".
OB J_IB
OB toggles every time counter B counts through "0".
L
.1
The counters, when counting, count down and wrap·
around from 0 to FFFF and continue counting down.
IB-I
Maximum count rate = fl/2
where: fl = internal clOCk frequency
Minimum pulse width = t
where t = period of internal clock
(as previously defined).
tA=(A+l)t
tB = (8 + l)t
o .;
A .; 65535; 0'; 8 .; 65535
5-22
o
o."
to register A and then cleared. On the low to high
transition counter B is transferred to register Band
then cleared. The counters, therefore, count down from
zero. Therefore the value read from the registers is a
two's complement value. The transfer from the counter
to register is Inhibited during a read instruction.
There is no requirement that the count signal be symmetrical. The pulse width low must be at least equal to
1. The pulse width high must also be at least equal to 1.
5_ Number of Pulses Mode - This mode outputs at OA a
specified number of pulses of a specified width_ The
number of pulses Is specified by the contents of register B_ The pulse width is specified by the contents of
,register A.
The outputs OA and OB toggle each time the respec·
tive counter counts through zero.
The minimum pulse width, either high or low, that can
be measured, is the period of the internal frequency.
The maximum pulse width that can be measured is
the maximum count (65535) multiplied by the period
of the internal frequency.
OA
tA=(A+l)t
N=B+l
Where:
'" J=.
A = Contents of register A
B Contents of register B
t = Deriod of internal clock
(as previously defined)
1 .. A .. 65535, A 0 (1" A .. FFFF16)
0 .. B .. 65535
(0 .. B .. FFFF16)
=
*
Where:
roo ............ ,.. ........ ,.. .... i ........... 1 i .................... +.......... +
,,~L....-
-1-" ·1
~
~
tA
tB
~
~
t
t
I = period of internal clock
8. Triggered Pulse Mode - This mode outputs a pulse
triggered by the zero crossing of a Signal at ZI. The
delay from the zero crossing is specified by the contents of register A. The pulse width is specified by
the contents of register B. Input INB is ignored. See
applications section for further information.
6. Duty Cycle Mode - This mode generates a rectangular waveform at OA. The pulse width high is specified
by the contents of register A. The pulse width low is
specified by the contents of register B. A combination
~,
no
OA
tA=At
tB=Bt
tA+B=(A+B)t
Where:
IA = (A + 1.5)1
tB=Bt
tA+ B=(A+ B + 1.5)t
A = Contents of register A
B = Contents of register B
t = period of internal clock
(as previously defined)
1 .. A .. 65535, A 0 (1" A .. FFFF16)
1 .. B .. 65535, B 0 (1" B .. FFFF16)
Where:
*
*
A = Contents of register A
B = Contents of register B
t = period of internal clock
(as previously defined)
0 .. A .. 65535
(0 .. A .. FFFF16)
1 .. B .. 65535, B 0 (1" B .. FFFF16)
*
7. Waveform Measurement Mode - This mode measures the high and low times of an external waveform
at INB (with ENB 1). Counter A counts the pulse
width high and counter B counts the pulse width low.
On the high to low transition counter A is transferred
=
5-23
ao
."
0l:Io
U'I
!A
o
o
."
Co)
ao
U'I
."
65535t
65535t
OB toggles each time a pulse train is generated at OA.
The pulse train is generated each time the COP452 is
selected and an instruction is sent to the device.
Counter B Is automatically loaded from register B
after the N pulses are generated. Counter A Is automatically loaded from register A at each transition of
OA. Therefore simply reloading the number of pulses
mode will repeat the previous sequence.
0l:Io
U'I
Co)
U'I
Co)
M
IJ')
M
c..
o()
N
IJ')
M
c..
o()
M
IJ')
9. Triggered Pulse and Count Mode - This mode out·
puts a pulse at OA triggered by the zero crossing of
a signal at ZI. The contents of register A specify the
delay from the zero crossing. The pulse remains high
until the next zero crossing of the signal at ZI.
OA
,
.
DB_II I L
Independently of the zero detection, counter S counts
external events at INS (when ENS =0 1). The conditions
on the counter as described previously apply here.
oq-
c..
o
()
t8=(B+ 1)t
Wilere:
N
IJ')
oq-
c..
B = Contents of register B
t = period of internal clock
(R8 previously defined)
a~
o
()
I
l-tB~I~-tB_I~-tB-_1
I
OA~~
L
A
=.
General Notes
Contents of register .A.
t = period 01 interned clod..
(as previously defined)
0'$; A
~
G5535
(O·-Z;: f..
~
FFFF16)
CS, other than removing DO from the TRI·STATE'· condition and allowing data to come into the I register via 01,
does not affect tne operation of the device. CS must go
high between accesses in order to clear the I register.
Since the I register is cleared when CS goes high, the
user must insure that CS does not go high before the
COP452 has accepted the information in the I register.
See the software interface section for further explana·
tion on this point. CS does not affect the mode latches.
08 toggles each time counter 8 cOllnts through 0
10. Whiie Noise and Frequency Mode - Reqister Ais
converted to a 17-stage shift register ge;erator for
the generation of pseudo·random noise at output OA.
OS outputs a square wave whose period is specified
by the contents of register S. The shift register generator is shifted at the internal frequency (=0 CKI fre·
queney or '/,CKI flGquency aepending on the oscil·
lator divider). See the applic8tions section for more
information on the white noise generator.
OA
(0 <; B,;; FFFF16)
The master timing reference in the COP452 is the inter·
na! frequency. This is the CKI frequency after it has
passed through the divider. This frequency must remain
within its specified limits. The maximum count rate at
either input is this frequency divided by 2. The minimum
pulse width that can be measured is the period of this
irequency.
tA~{A+1.5)t
Where:
B " 65535
In ttlOse modes where there is an automatic transfer
from the register to the counter (frequency generation,
duty cycle, number of pulses, triggered pulse), care must
be exercised when reading or writing the register. To
insure proper, "glltch·free" operation, one of the two
procedures below must be followed:
JlJLJlJlJl
1. Place the COP452 in the RESET mode.
2. Read or write the appropriate register.
3. Place the COP452 back in the original mode.
OB
Alternatively:
1. Read or write the appropriate register.
Where:
2. Send the instruction to copy the appropriate register
to its counter.
B = Contents of register 8
t = period of internal clock
(as previously defined)
0<; 8 <; 65535
(0';; B", FFFF16)
WARNING: Failure to observe one or the other of these
procedures can cause some faulty output conditions.
The COP452 powers up in the RESET mode and with
oscillator divide by 4. If the CKI input frequency is less
than 4 times the minimum internal clock frequency the
user must set the oscillator divider to divide by 1 before
attempting any operation with the COP452. The instruc·
tion setting the oscillator divider will be accepted regardless of the value of the internal clock frequency. Caution:
Failure to observe this requirement will result in the
improper operation of the COP452.
11. Gated White Noise Mode -
This mode generates
pseudo·random noise ANDed with a square wave.
OA outputs this combined signal. OB outputs a
square wave frequency. Register A is converted into
a 17·stage shift register generator which is shifted at
the internal frequency rate. Counter A is not used.
Counter S and register B are used in the frequency
generation. See the applications section for further
information on the white noise generation.
5-24
o
o""D
Applications Information
~
Zero Cross
The delay from the true zero crossing of the input waveform has other parameters that must be considered.
The equation is of the form:
The ZI input normally requires a resistor and diode external to the device as indicated in Figure 9a. The resistor
is part of a voltage divider used to ensure that the voltage
at pin ZI does not exceed 10 volts peak and to protect
the diode which is required to clamp the negative voltage
swing at the input to less than -0.8 volts. Figure 9b. is
the recommended input circuit if logic level pulses are
input to ZI for counting.
T=(A + 1.5)t ± IX l l +X 2 +X 3
where: T, A, t are as defined previously
Xl = time for input waveform to reach the trip
point of the zero cross detection circuit
As indicated above, the input voltage at ZI must not
exceed 10 volts peak. For inputs less than 10 volts peak,
the resistor in Figure 9a. is required only to protect the
diode. Otherwise, the resistor should be selected to
guarantee that the voltage at pin ZI does not exceed 10
volts peak. Figure 10 shows this resistor (Rs) and the
impedance (R IN ) which forms the first part of the input
circuit at ZL The absolute value of RIN can vary widely
with process variation. The user should compute the
divider with Rs and the worst case maximum of RIN so
.I.'---_.L
LlIc;lL
'.1. ____
.1.'- _ _ _
LIIO YVILo.yC
.I.
C:lL
_~_
1-1111
.."
~_
L..
,~
..on .. _ • .&. _ _ _
IV
"'VIL~
VI
• ___
10..,..,.
"1"'-_
I
~IO
X2 = propagation delay through the zero cross
detection circuit
X3 = input synchronization delay
Parameter Xl is dependent on the peak voltage at pin ZI
and on the frequency of the input signal. The peak voltage at ZI is in turn dependent on the Rs-RIN voltage
divider and the input voltage. The Xl time is added or subtracted because the trip point of the zero cross detection
circuit may be either above or below zero. In the worst
.I._I
................ ' +100. ....
................ ,
IVI-
~
.....
+...••i ............
i .... + i ... th,.. ...... ""vi ...... ,'rn "lfcoat l"'IoF 1J;n m\1 ~I"\r
t' ,... ..................... _,. .......... - " - - ' ' ' ' ' ' . _ - . . . . . . _.
~
a.sine wave Signal, Xl is determined as follows:
lowing relationship should be used when the input voltage is greater than 10 volts peak:
VOFFSET = Vp sin[211f(Xl)]
RIN(MAX.)
- - - - - - X VIN .;;; 10 volts peak
Rs + RIN(MAX.)
1
. VOFFSET
Xl = 211f arcsin -----.::;;--
Substituting the maximum value for RIN and solving for
Rs gives:
and
VIN
Rs .;;;-x7.8k-7.8k
10
substituting we have
where: VIN = peak input voltage.
Rs+
Xl = -1- arcsin (VOFFSET -RIN)
-
Note that this equation is not valid for VIN less than 10
volts. In this case, the value of Rs is chosen primarily for
protection of the diode and not to divide the voltage
down to acceptable values.
2~
~N~N
where: VOFFSET = zero crossing offset or trip point
.
\/_ -
Zero Cross Offset
nC!:IIi.- inn. It \f"lt~".c. ~t nin 71
.
.....
f = frequency of input Signal
RIN = internal impedance to ground at pin ZI
As the electrical characteristics indicates, the ZI input
has a worst case offset of 150 mV in the zero crossing
detection. Therefore, the output of the zero cross detection circuit will change state within ±150 mV of zero
volts. There are no directional characteristics to this,
i.e., approaching zero from the positive or negative
direction has no effect on where the output of the zero
cross detection circuit will change state (see Figure 4).
The offset further indicates that the voltage at pin ZI
must exceed 150 mV peak in order to guarantee that the
zero crossings will be detected and the appropriate signals generated.
Both VOFFSET and RIN vary from device to device. It is
clear from the equation above that the maximum value
of IX 11 is obtained when VOFFSET is at its maximum of
150 mV and RIN is at its minimum of 2.6kQ. The minimum
value of IX l l is obtained if VOFFSET is O. USing this information, the following range of IX 11 is obtained:
Triggered Pulse Modes
Parameter X2 is the propagation delay through the zero
crossing detection circuit and its range is given by:
Rs = external series resistance at ZI
o .;;; IXl l .;;;
The delays from the zero crossing in the triggered pulse
modes are measured from the point where the output of
the zero crossing detection circuit changes state - the
trip point of this circuit. As stated before, the delay time
from this trip paint is:
1
- - arcsin
2~
Rs+2.6k
0.15 --'=--~Nx2~k
0.3I-'s';;; X2 .;;; 0.61-'s
Parameter X3 is the internal synchronization delay and
is dependent upon when the zero crossing occurs relative to the internal timing which reads the output of the
zero crossing detection circuit. The range for X3 is:
T=(A+1.5)t
where: T = delay time from trip point
A = contents of register A
where: t = period of internal clock
t = period of internal clock
5-25
~
o""D
~
~
o
o""D
(,.)
~
o""D
(,.)
en
(,.)
~D..
o
~
With the preceeding information, minimum and maxi·
mum values of the delay from true zero can be derived
by simply substituting into the original equation.
D..
,
1
~
RS+2.6k~ +0.3"s
.
TM1N =(A+1.5)t--- arcsin 0.15
V1N x 2.6
2nf
~
1 arcsin ~0.15 Rs+2.6k~ 0.6"s +t
TMAX=(A+1.5)1+-'2nf
V1N x2.6k
2
Ll)
C")
o
(,)
~
D..
o
~
D..
o(,)
during the programmed delay time is ignored and there·
fore lost. However, if the delay time is counted out and
the zero crossing occurs during the pulse width high
time, the zero crossing will be recognized and the delay
time will start counting again while the pulse width high
time is being counted. This can result in a variety of pos·
sible conditions at the output - ranging from the appar·
ent loss of that zero crossing to an effective very short
delay from the zero crossing. What will occur depends
on the values of the two counters and on their relation·
ship to the times between zero crossings. Some interest·
ing output waveforms can be produced, but their utility
is questionable. Therefore, the user should exercise ex·
treme caution in this mode and make' sure that the times
are such that all zero crossings occur at the "right"
times. Otherwise, the user must be prepared to accept
the bizarre effects that this situation can produce.
The preceeding information should enable the llser to
determine more closely the actual delay from zero of
output OA of the COP452. This analysis applies to both
of the triggered pulse modes. The three parameters, X1,
X2, X3, also apply in the same way in the triggered pulse
and count mode when OA returns to 0 since it is the zero
cross detection circuit that causeS the output to return
to zero in that mode.
Count Modes
As stated before, the counters are 16·bit down counters.
Preloading them when they are enabled as external
event counters with one's or zeroes will give the one's or
two's complement of the count. To read the counters it
is necessary to first copy the counter to its respective
register and then read the register.
Vp:::z::u-
The user can utilize the fact that the outputs toggle when
the counter counts through zero. The counter can be
preloaded with a value that represents the number of
events the user wishes to count. When the output
corresponding to that counter toggles, the specified
number of events have occLJrred. Thus, the user can
know that the required number of events have occurred
without having to actually read the counter.
Figure 9a.
Vee
20k .----~
o.~t
-ir~ ZI
eOP452
The counters require a pulse width greater than or equal
to the period of the internal frequency in order to be reli:
ably decremented. It is possible for a narrower pulse to
decrement the counter, but it is not guaranteed. A narrower pulse will decrement the counter if it appears at
the count input at the right time relative to the internal
timing of the device. Since the user does not have access
to this internal timing, it is impossible for him to synchronize the count input to this timing and effectively
reduce the required width of the count pulse. Therefore,
applying pulses at the count input of less than one period
of the internal frequency in width may cause erratic
counting in the sense that some of the pulses may be
recognized and some may not be recognized. Reliable
counting is assured only if the width of the count pulse
is greater than or equal to one period of the internal frequency.
,-
.. ~
Figure 9b.
RIN =5.2 kQ±50%
The counters decrement on a low·going pulse at the
input. As stated above, the pulse must remain low at
least one internal frequency period to give reliable
counting. Similarly, the count signal must go high and
remain high at least one internal frequency period before
it goes low again. However, the count signal does not
have to be symmetrical.
Figure 10_
Triggered Pulse Modes: Intervening Zero Crossings
In the triggered pulse modes, it is possible to specify a
delay from the zero crossing ""hich will!extend beyond
the next zero crossing. In the triggered pulse and count·
mode, the intervening zero crossing is ignored arid there·
fore lost. The device will still continue to operate prop·
erly. The situation is somewhat different in the "pure"
triggered pulse mode where both a delay and a pulse
width are specified. Any zero crossing which occurs
COP452 Oscillator
The COP452 will operate over a wide range of oscillator
input frequencies. The input frequency may be supplied
from an external source or CKI and CKO can be used
5-26
o
o'"tJ
with a crystal or resonator to generate the oscillator
frequency. Figure 11 indicates some crystal networks
for some typical crystal values.
the RC and LC networks previously described. However,
these networks will work and are usable. The user should
be prepared to experiment with the networks to determine component values, stability, oscillation frequency,
etc. These networks should be viewed as the starting
point for a user who wishes to use networks of this type
to generate the COP452 oscillation frequency.
RC and LC networks can also be connected between CKI
and CKO to produce the oscillation frequency. Figure 12
indicates some examples of such networks. Figure 12a.
is the recommended RC network for use in this manner.
With C 1 =0.005"F, R = 1.5 kQ, and C2 between 10 pF and
400 pF oscillation frequencies between about 1 MHz
and 3 MHz should be obtainable. The oscillation fre·
quency decreases with increasing values of C2 . The
user should feel free to experiment with the Rand C
value:;;, and with the network configuration, to produce
the oscillation frequency desired.
The RC networks provide an inexpensive way to generate
the oscillation frequency. It is foolish, however, to expect
any significant degree of frequency stability or accuracy
over temperature and voltage with a Simple RC network
- especialy if inexpensive, uncompensated compo·
nents are used. LC and RLC networks can produce very
stable and accurate frequencies. Regardless of the network used, the user must consider the variation of the
external components in his design if accuracy and stability are important considerations in his application.
Figures 12b. and 12c. indicate LC networks that can be
used to produce the COP452 oscillation frequency. In
Figure 12b. with L =100"H and C =100 pF, a frequency of
about 2 MHz should be produced. In Figure 12c., with
L 56 "H, C2 27 pF, and C1 between 25 pF and 0.01 "F,
frequencies between about 1.5 MHz and 3 MHz can be
prociuceci.
=
The crystal networks of Figure 11 provide frequency stability and accuracy and are easy to use. If the application
requires oscillation frequency accuracy and stability the
=
••
,
,
_
\';1 Y;jldl IIt::::lWUII'\;) c:t1C' 1t:::\.IUI III tlC't
' __ '
tuC'u
__
__
'-'-_I~
.L
There is, in effect, an inverter between CKI and CKO.
This inverter was designed for use with a crystal and its
associated network. It was not designed for use with
COP452
COP452
CKI
i
CKO
~~
fc
Crystal
Value
CKI
R2
Component Values
R,
R2
C
4.44 MHz
1k
1M
27pF
4.OMHz
1k
1M
27pF
3.58MHz
1k
1k
1M
1M
1k
1M
27pF
56pF
56pF
2.0MHz
1.0MHz
CKO
Cj"
~D~
Crystal
Value
455kHz
1M
32kHz
.1M
Figure 11. COP452 Crystal Oscillator
5-27
Component Values
R1
R2
_ _ ' ••
"'~
__
0';:' lilt;:; UC'':>l ';:'UIUlIVII.
C1
C2
16k 80pF 80pF
220k 6-36pF 30pF
01:>-
C11
~
o
o'"tJ
01:>-
C11
J-l
o
o'"tJ
CN
C11
~
o
o'"tJ
CN
C11
CN
a.
c.
b.
COP452
COP452
COP452
CKI
CKO
C2
Figure 12. RC and LC Networks to Produce COP452 OsciUator Frequency
White Noise Generation Modes
either white noise mode presets the 16th and 17th stages
to a 1 and connects the 17th stage to the shift register. If
the user wishes, he can write register A and then enter
the white noise and frequency mode. The output at OA
will then be two "1's", and the lower 15 bits of the data
user had written to register A. Following that, the poly·
nomial sequence dictates the output. This injection of a
1 into the 16th and 17th stages prevents the lockup con·
dition that occurs if all the stages are O.
In the two white noise modes register A is converted
into a 17·stage shift register, or polynomial, generator.
With feedback taps at stages 17 and 14, as indicated in
Figure 13, a maximal length sequence is generated. With
these feedback taps the characteristic polynomial of
the sequence is:
x17
+ X3 + 1.
The output of this generator Is a pseudo·random se·
quence. Since the register is shifted at the internal fre·
quency rate, the sequence repeats after a period equal to
(2 17 -1)t, where t is the period of the internal frequency.
Warning: To insure proper operation, the white noise
must be entered from the Reset mode. The COP452 must
be in the Reset mode before the desired white noise
mode and there may be no intervening modes between
Reset and the desired white noise mode.
The first 16 stages of the shift register are the 16 bits of
register A that the user may read or write. Entering
PRESET~~-r---'
WHITE NOISE &
FREQUENCY MOOE
OUTPUT OA
08
GATEOWHITE
NOISE MOOE
Figure 13. COP452 White Noise Generator
5-28
(')
Interface to COPSTM Microcontrollers
Interface Software lor tOG COP452
Figure 14 indicates the typical intefface between the
COP452 and a COPS microcontroller. As is obvious from
the figure. the interface is the standard MICROWIRETM.
G 2 is indicated as the chip select line because it is avail·
able on all COPS microcontrollers. Obviously, any con·
venient output of the microcontroller may be used as
the chip select for the COP452.
Sample software for interfacing COPS microcontrollers
to the COP452 is given below. The code is completely
general and will 'Nork in any COPS microcontroller. The
following assumplions are made:
1. Pin G2 is used as the chiD select for the COP452 (be·
cause G 2 is available on all COPS microcontrollers)
2. G2 is assumed high on entry to the routines.
3. The SK ciock is off (Oi on entry to the routines.
4. Register 0 of the microcontroiler is arbitrarily chosen
as 1I',e 110 register.
COP411L
OR
LARGER
5. The leading digit sent out is of the form 001X where 1
is a start bit; X is 1 or 0, depending on the operation.
6. The next lower digit contains the remaining 4 bits of
the command.
7. If data is being sent, it is in the next 16 bits of infol'
mation sent.
8. Location GSTATE chosen as RAM address 0,15.
COP452
COP453
COP352
COP353
SI
Figure 14.
9. SK frequency is less than or equal to the internal
frequency.
ThF! CS oin of the COP452 must be toggled between sue·
5iru"rt:; i.ln:;: ~Cr'~~~ ;~ ~;-: !/C' -:::!~'.'!r:'e. ~ho r.nrlp. tHkes precautions to insure that SO is 0 prior to enabling the SK
clock. (This is a wise precaution to talle in any system
witil 110 peripherals on the serial porL)
cessi.ve communications with the device. Tne Internal i
register (instruction register) is held reset (all zero) when
CS is high. Since this is the only way in which the I reg·
ister is cleared,failure to take CS high between accesses
will result in improper oper".tion.
Two version of the WRITE routine are provided. The
destructive WRITE routine desiroys the information in
the microcontroller as the data is being sent out to the
COP452. The nondestructive WRITE routine preserves
the data in the microcontroller as that data is being sent
out to the COP452. The destructive routine is a little
more code efficient than the nondestructive routine.
The COP452 contains an internal power·on reset circuit
which sets the mode latches to one, i.e., places the
COP452 in the RESET mode, and sets the oscillator di·
vider to divide by 4. The counters and registers are not
affected by this reset circuit and are therefore undefined
at power up.
WRCMND:
CLRA
AISC
JP
; SET UP POINTER FOR COMMAND ONLY WRITE
WRITE
. N:T 110 or""T':R ':OR
VynUMIM.
WRITE:
SEND:
FINISH:
DONE:
AISC
LBI
RMB
OMG
CAB
LEI
RC
CLRA
XAS
SC
LD
XAS
XDS
JP
RC
XAS
LBI
5MB
OMG
LEI
RET
CODE TO WRITE COP452 -
5
GSTATE
2
8
r:()MMAND AND DATA WRITE
; GSTATE = LOCATION 0,15
;
;
:
:
SEND COP452 CHIP SELECT LOVJ
POINT TO PROPER LOCATION FOR OUTPUT
ENABLE SHIFT REGISTER MODE
JUST TO INSURE SO = 0 BEFORE CLOCK ON
; THESE 3 WORDS FOR SAFETY ONLY
; SO SK WILL TURN ON AT NEXT XAS
SEND
; ALL DONE, SK OFF, DESELECT COP452, ."'ND SET
; SO TO ZERO
GSTATE
2
0
DATA DESTROYED IN MICROCONTROLLER
5-29
o
"tI
~
~
(')
o"tI
~
(J1
~CN
(')
o
"tl
CN
(J1
~
(')
o"tI
CN
(J1
CN
('I)
Lt')
('I)
0..
o
o
~
('I)
The code below is the code to read the COP452. It is
written so that the command to the COP452 is sent out
nondestructively, I.e., the data in the microcontroller is
preserved. A routine which sends out the data destruc·
0..
READ:
oo
fi
oo:t
10..
oo
~o
SEND2:
o
RDLOOP:
CLRA
AISC
LBI
RMB
OMG
CAB
SC
CLRA
LEI
XAS
LD
XDS
JP
XAS
CLRA
AISC
CAB
NOP
NOP
NOP
CLRA
XAS
XDS
JP
RC
XAS
JP
tively could be easily generated but is not shown here.
The user is referred to the techniques in the WRITE
routines to determine how to modify this READ routine
to send the command out destructively.
; READ INSTRUCTION IN 0, 1 AND 0, 0 AND IS
; OF THE FORM 00100010 OR 00100011 IF READ
GSTATE; RA OR RB
2
; SELECT THE COP452
; SO THAT ZEROES GO OUT FIRST
8
SEND2
; NONDESTRUCTIVE SENDING OF READ INSTRUCTION
; SET UP TO READ
2
; NOW WAIT FOR THE DATA
RDLOOP
DONE
;
;
;
;
;
TURN OFF THE CLOCK
READ LAST 4 BITS
COMMON EXIT WITH WRITE ROUTINE
EXITS WITH DATA IN LOWER 3 DIGITS OF RO
AND IN THE ACCUMULATOR
SAMPLE CODE TO READ THE COP452
WRCMND:
WRDATA:
WRITE:
SEND:
FINISH:
DONE:
CLRA
AISC
JP
CLRA
AISC
LBI
RMB
OMG
CAB
RC
CLRA
LEI
XAS
SC
CLRA
XAS
LD
XDS
JP
XAS
CLRA
NOP
RC
XAS
LBI
5MB
·OMG
LEI
RET
CODE TO WRITE COP452 -
; SET UP POINTER FOR COMMAND ONLY WRITE
WRITE
; SET UP POINTER FOR COMMAND AND DATA WRITE
5
GSTATE
2
; SELECT THE COP452 ; LOAD THE POINTER
8
G2 LOW
; ENABLE SHIFT REGISTER MODE
; SEND OUT ZEROES
; FIRST TIME THROUGH, TURNS ON CLOCK
; THEN SENDS DATA
SEND
; SEND LAST 4 BITS
; ALL DONE, SK OFF
GSTATE
2
; DESELECT THE COP452
0
; SEND SO LOW
DATA PRESERVED IN MICROCONTROLLER
5-30
(')
o'"'D
The software interface routines provided above are
general purpose routines written to work in the general
case for all COPSTM microcontrollers. They are written
as subroutines to be called by the main program. There
is no question that other routines can be written to per·
form the required function. It is also clear that these
routines can be reduced in specific applications. These
routines should be viewed as providing a framework
from which the user can develop routines which are
optimal to a specific application.
We will select the CKI frequency of the COP452 as 1 MHz
primarily for ease in computation. Therefore, in divide
by.1 mode, the internal frequency is 1 MHz. Since the
registers in the COP452 are loaded with a number related
to the period of ttie frequency, we need the periods of f1
and f2.
1
~
f1 = t1 =1062.7I'S; 2 = 531.351's
1
Assumption 9 mentioned prior to the code itself presents
an important requirement for the interface software.
There must be a time delay greater than 3 periods of the
internal frequency between the time the SK clock is
turned off and the time the COP452 is deselected. This
is required because the COP452 reads the instruction
register with timing based on its internal frequency.
When the microcontroller deselects the COP452, CS
goes high and the instruction register is automatically
cleared. Therefore, depending on the relative speeds of
SK and the internal frequency, it is possible that the
!~~!~~~!!~~ ~~2!~!er ~~~' ~e ~!~e.retj ~l?'f0re ~h'?
As stated earlier, the period of an output frequency in the
COP452 in the frequency generation mode is given by:
Figure 15 indicates a connection diagram for this appli.
cation. The software to accomplish this task is indicated
below. The software indicates several aspects of the
usage of the COP452. The code first resets the COP452,
then loads the reaisters with the proper values, transfers
the registers to the counters, puts the COP452 in the CKI
divide by 1 state, and then loads the dual frequency
mode. The output frequency generation begins when
the dual frequency mode is loaded. Tt~e code as written
is independent of the COP microcontroller used. The
code uses the WRITE routines as described in the soft·
ware interface section and assumes that these routines
are located in the subroutine page .
Generation of Multiple Tones
The requirement is to generate the following two DTMF
frequencies:
f1 =941 Hz
f2 = 1336 Hz
. PAGE
GSTATE
POWUP:
a
0, 15
CLRA
XAS
LBI
STII
LBI
OMG
LBI
JSRP
LBI
STII
STII
JSRP
; TURN OFF SK CLOCK (C = a AT POWER UP)
GSTATE
15
GSTATE
; MAKE SURE COP452 IS DESELECTED
0,0
CLEAR
0,0
15
3
; CLEAR REGISTER a
NOW SET UP TO SEND RESET MODE TO COP452
RESET COMMAND AND START BIT
WRCMND
5-31
(')
o'"'D
W
01
~
(')
01
With the internal frequency at 1 MHz, the value of t is
11's. Therefore, the N values with which the registers
must be loaded to generate the frequencies specified
above are 530 (212 hex) and 373 (175 hex). Note that the
fractional parts of the numbers are lost since the COP452
cannot be loaded with fractional numbers. Note that the
fractional parts may be reduced or eliminated by judi·
cious choice of the CKI frequency. With the numbers
here, the COP452 will generate a frequency with a period
of 10621's (941.62 Hz) and a frequency with a period of
74811s (1336.9 Hz). Note that these values are accurate to
within 0.7% of th,e desired output frequencies.
The COP452 makes the generation of two independent
frequencies a simple task. This application indicates
how to generate frequencies with the COP452 and also
indicates other aspects or conUOI or me aevlce.
-'="
01
~W
where: t = period of internal clock
N = register value
T
Caution: Failure to observe this time delay will result in
improper operation of the COP452.
o'"'D
o'"'D
N="2t- 1
G0pt1.13?
~
(')
T = 2(N+1)t
Solving for N, the equation becomes:
has accepted the information. The sample code provided
automatically satisfies the requirement mentioned
above whenever the SK frequency is less than or equal
to the counter clock frequency. When SK is faster than
the internal frequency, some delay may be required
between the time SK is turned off and the time the
COP452 is deselected. The time delay is not required
when reading or writing the COP452 registers or when
changing the oscillator divider.
Application #1 -
t2
12= t2= 748.5I's; 2= 374.251's
-'="
01
W
W
M
Lt)
M
a.
o(.)
C\i
Lt)
M
a.
o(.)
M~
Lt)
.qo
a.
o(.)
C\i
Lt)
.qo
a.
o(.)
; THE COP452 IS NOW RESET, NOW SETUP to WRITE REGISTER A TO
; GENERATE OUTPUT FREQUENCY OF 941 HZ AT OA
LBI
0, a
STII
; 0212 HEX = 530, GIVE PERIOD OF 1062~s
2
STII
1
STII
2
STiI
a
STII
1
STII
; START BIT PLUS CODE TO WRITE RA
2
JSRP
WRDATA
; REGISTER A IS NOW LOADED. NEXT TRANSFER REGISTER A TO COUNTER A
LBI
0, a
STII
5
STII
2
; INSTRUCTION TO TRANSFER PLUS START BIT
JSRP
WRCMND
; ALL DONE WITH REGISTER AND COUNTER A, NEXT WORK ON REGISTER B
LBI
0,0
; WRITE REGISTER B WITH 0175 HEX (373)
STII
5
; TO GIVE FREQUENCY OF 1336 HZ
STII
7
STII
1
STII
a
STII
a
; INSTRUCTION TO WRITE RB
STII
2
JSRP
WRDATA
REGISTER B IS NOW LOADED. NEXT TRANSFER RB TO CB
LBI
STII
STII
JSRP
; NOW LOAD CKI DIVIDE BY 1
°
O.
4
2
WRCMND
; INSTRUCTION TO TRANSER RB TO CB
°
LIB
0,
STII
8
STII
2
JSRP
WRCMND
; NOW PUT THE COP452 IN DUAL FREQUENCY MODE
°
LBI
0,
STII
STII
3
JSRP
WRCMND
; NOW THE CODE MAY PROCEED TO DO WHATEVER ELSE IS REQUIRED IN
; niE APPLICATION.
; THE SUBROUTINES USED IN THIS APPLICATION ARE CLEAR AND THE
; WRITE ROUTINES. THE ADD ROUTINE IS USED IN THE EXAMPLE BELOW
. PAGE
2
CLEAR:
CLRA
XIS
JP
CLEAR
RET
ADD:
SC
2,9
; ROUTINE ADDS 1 TO COUNTER
LBI
ADD1:
CLRA
ASC
NOP
XIS
JP
ADD1
RET
°
WRCMND:
; SEE SOFTWARE INTERFACE FOR THIS ROUTINE
WRDATA:
; SEE SOFTWARE INTERFACE FOR THIS ROUTINE
5-32
(")
o
"'tI
limits in either the divide by 1 or divide by 4 condition.
Therefore, this characteristic of the device can be used
to quickly multiply or divide the output frequency by 4.
An interesting siren effect can thus be created. Sample
code to do this is given below. This code assumes that
the registers have been loaded and that the COP452 is
in dual frequency mode. Again, the code is written to be
independent of the COPSTM microcontroller used.
The preceding has done a lot with the COP452. It is
clear that the code can be reduced and specialized. The
purpose here was to illustrate the various communica·
tions with the device.
An interesting effect can now be produced by making
use of the 4 to 1 CKI divider. With the CKI frequency at
1 MHz, the internal frequency is well within the specified
SIREN:
PLUS1 :
PLUS1A:
LSI
JSRP
LSI
STII
STII
JSRP
JSRP
SKC
JP
LSI
STII
STII
.j5F\r
LSI
JSRP
JSRP
SKC
JP
JP
USE REGISTER 2 AS COUNTER FOR DELAY TIME
2, 9
CLEAR
0,
~
U1
~
o"'tI
~
U1
~
(")
o
"'tI
Co)
°
U1
~
;' CKI DIVIDE SY 1
8
2
WRCMND
ADD
(")
o"'tI
INCREMENT COUNTER FOR DELAY
Co)
U1
PLUS1
EXIST DELAY LOOP WHEN COUNTER OVERFLOWS
0,0
9
2
; CKI DIVIDE BY 4
'v··inCiv~i~u
2,9
CLEAR
ADD
; AGAIN, TIME OUT VIA THE COUNTER
PLUS1A
SIREN
; DONE, START OVER AGAIN
As is obvious from this code, it is a simple matter to
create this effect. As was mentioned earlier, the code
here is general purpose. This necessarily means that it
can be reduced in specific applications. The user should
view this code as representative of the techniques involved and then optimize or rewrite the routines to suit
his particular application.
Vee
OSCILLATOR
INPUT
Vee
Vee
G2
eOP411L
OR
LARGER
es
SO
01
SI
00
SK
SK
eOP452
OA
DB
":"
CKO
":"
OR
CKI
1MQ
OA
":"
DB
1 MHz
0
6-36pF
":"
Figure 15. Dual Frequency Application
5-33
Co)
CW)
Lt)
CW)
Il..
o
~
Lt)
CW)
Il..
oU
M
Lt)
oo:t
Il..
o
~
Il..
oU
Application #2
crystal as the time base for the COP452. With the oscil·
lator divide by 4 selection, this gives an internal fre·
quency period of 1.11745"s. With this information we can
determine the number that needs to be loaded to register
A to give a pulse width of 5 ms. From application #1 we
have the following equation which is valid here:
This application makes use of the number of pulses
mode of the COP452 to control a stepping motor. The
technique is equally applicable in any situation where a
number of pulses must be generated based upon the
state of the system. Figure 16 indicates the system inter·
connect. Since the oscillator frequency is 3.579545 MHz
and the CKO pin of the COP452 is being used to drive the
CKI of the microcontroller, a COP420 is specified as the
microcontroller. If a separate oscillator were provided,
any COPS™ microcontroller could be used. The software
is completely general and will work in any COPS micro·
controller.
T = (N
+ 1)t
where: T = pulse width
N
= contents of register A
t = period of internal clock
Solving for N we have:
The application has the following specifications:
N = (T/t)-1
1. The pulse width required for the stepping motor is
5ms±5%.
=(5 ms/1.11746"s)-1
=4474.34-1
=4473.43
2. The system has 4 return lines which indicate 4 possible variations in the number of output pulses reo
quired. These four conditions are:
a. 10 pulses required
b. 100 pulses required
C. Repeat the last number of pulses sent
d. Send one more than the last number of pulses
The fractional part is discarded, so register A must be
loaded with 4473 (1179 hex) to give a 5 ms pulse. The
error created by the truncation of the number is 0.5"s.
There is an error of 0.01 % - well within the tolerance
limits required.
3. The system has a signal available indicating that the
return lines contain valid information.
The code to operate this system is given below. The
interconnect of Figure 16 is assumed. The code uses
the READ and WRITE subroutines as given in the soft·
ware interface section of this data sheet. The code further assumes that those routines are located in the
subroutine page.
4. One pulse is required at power up.
A flow chart to implement this system is indicated in Fig·
ure 17. Figure 16 is the interconnect used in this applica·
tion. As the figure indicates, we will use a 3.579545 MHz
3.579545 MHz
0
CKO
COP42D
L4
L3
L2
G2
CS
SI
DO
COP452
SO
01
SK
SK
STEPPING
MOTOR
PLUS
SYSTEM
HARDWARE
OA
L1
S4
T
A
T
E
S
T
A
T
E
2
Figure 16. COP452 in Stepping Motor Contro.1
5-34
S
T
A
T
E
R
E
A
0
Y
(')
o"tI
~
en
~
(')
WRITE RA/CA
OF COP452
o"tI
1 - RBICB
OF COP452
~
en
!N
SET NUMBER
OF PULSES MOOE
RESET COP452
(')
0064 - REG.
"tI
o
(0)
en
~
(')
o
"tI
(0)
en
(0)
RESET COP452
OOOA - REG.
RESET COP452
READ RB - REG.
REG.+ 1 - REG.
Figure 17. Flow Diagram for Application #2
· PAGE
GSTATE
POWRON:
o
0,15
CLRA
XAS
LBI
STI!
LBI
OMG
LD
CAMQ
LEI
LBI
STI!
STI!
STI!
STI!
STI!
STI!
JSRP
; TURN OFF SK CLOCK
GSTATE
15
GSTATE
DESELECT THE COP452 -
4
0,0
9
7
2
WRDATA
G2 HIGH
DRIVE THE L LINES HIGH FOR READING
ENABLE THE L OUTPUTS
; WRITE RA OF COP452 WITH 1179 HEX TO GET
; 5MS PULSE
5-35
LBI
0, a
STII
5
; TRANSFER RA TO COUNTER A
STII
2
JSRP
WRCMND
; NOW WRITE RB WITH THE NUMBER OF PULSES
lBI
0, a
STII
1
RBWRT:
STII
a
; ONE PULSE REQUIRED AT POWER UP
RBWRT2:
STII
a
STII
a
RBWRT3:
STII
a
STII
2
JSRP
WRDATA
LBI
0, a
; NOW TRANSFER RB TO COUNTER B
STII
4
STII
2
JSRP
WRCMND
PULSE:
LBI
0, a
STII
2
; SET NUMBER OF PULSES MODE
STII
3
JSRP
WRCMND
; AT THIS POINT THE COP452 IS IN NUMBER OF PULSES MODE. ONE
; PULSE IS OUTPUT AT OA. NOW MUST READ THE RETURN LINES, MAKE
; THE APPROPRIATE DETERMINATION OF THE STATE OF THE SYSTEM
; AND UPDATE THE COP452 ACCORDINGLY. ALSO AT THIS POINT, THE
; COP452 IS SET UP TO AGAIN GENERATE A SINGLE PULSE 5MS WIDE
; IF THE DEVICE IS ACCESSED AGAIN.
STATE:
STATE1:
TEST2:
STATE2:
TEST3:
STATE3:
LBI
LD
CAMQ
LEI
LBI
INL
SKMBZ
JMP
AISC
JMP
STII
STII
JSRP
LBI
STII
JMP
AISC
JMP
STII
STII
JSRP
LBI
STII
STII
JMP
AISC
JMP
JMP
GSTATE
4
; CONTENTS OF GSTATE = 15 HERE
; MAKE SURE L LINES ARE HIGH AND
; ENABLED
0, 0
a
STATE
8
TEST2
15
3
WRCMND
0,0
10
RBWRIT
4
TEST3
15
3
WRCMND
0,0
4
6
RBWRT2
2
TEST4
PULSE
;
;
;
;
READ THE L LINES TO A AND M(O, 0)
TEST DATA - RETURN LINES - VALID
DATA NOT VALID, WAIT FOR IT TO BE VALID
DATA IS VALID, DECODE A
; POINTING AT 0, a
; RESET THE COP452 FOR STATE 1
; NOW SET UP TO SEND 10 PULSES
; SHARE COMMON CODE
; IN STATE2, MUST SEND 100 PULSES
; FIRST RESET THE COP452
; WRITE 100 (0064 HEX) TO RB OF COP452
STATE 3 MERELY SENDS THE SAME NUMBER OF PULSES AGAIN.
THEREFORE, MERELY SEND THE NUMBER OF PULSES MODE COMMAND
AGAIN
5-36
(')
o"tI
TEST4:
STATE4:
PLUS1:
~
,AISC
JMP
STII
STII
JSRP
LBI
STII
STII
JSRP
LBI
XIS
XIS
XIS
XIS
LBI
SC
CLRA
ASC
NOP
XIS
CSA
AISC
12
JMP
RBWRT3
, PAGE
2
STATE
15
: ALL L LINES WERE 0, JUMP BACK TO MAIN
; RESET THE COP452
WRCMND
0,0
; NOW READ THE COP452
2
2
; COMMAND TO READ RB
a
o"tI
~
JIl
(')
o
"tI
; MOVE DATA TO LAST 4 DIGITS OF RO
Co)
c.n
~
(')
0,
a
o
; NOW INCREMENT THE VALUE BY 1
"tI
Co)
c.n
Co)
HAVE INCREMENTED THE VALUE, SEND IT OUT
READ:
WRDATA:
~
(')
c.n
READ
0,
c.n
; SEE SOFTWARE INTERFACE SECTION FOR THESE
; ROUTINES
WRCMND:
These are general routines and can be reduced in specific
applications, The application itself was kept general so
that it can be ,easily adapted to particular applications,
The user should view this code as the basis from which
to work to optimize the code for a specific application,
Application #3
An "nnlir.Rlion such as a tachometer requires the count·
ing of external pulses that occur within a given time
period, The COP452 can be used both to perform the
counting and to establish the "viewing window", or time
period, during which to count the pulses. By using the
frequency and count mode of the COP452, a frequency
can be generated which will establish this viewing time.
The other counter can then be used to count the pulses.
Figure 18 provides a diagram of the interconnect in this
application.
-
a frequency of 2 Hz. Using the equation developed
ei:::Hllt:H lUI Ut:at:OlllI;II;I'~ ~:,'-' .:..:.:...;::~::- .::.~-.::':' .. ,"'" h.-:a\lo·
N=.!.-1
2t
= (500 ms/8 !-is) - 1
= 62500-1
N = 62499 =F423 hex
Therefore, register A must be loaded with the hex value
F423 to generate a frequency of 2 Hz at ~A. Counter B
will count pulses when OA is high by virtue of the ENB
input. When OA is low, the microcontrolier will read and
reset the counter and perform any necessary operations.
As Figure 18 indicates, the oscillator frequency for the
COP452 has been selected as 250 kHz. With the oscillator
divider set at divide by 1, the internal frequency is also
250 kHz. At this frequency, the minimum pulse width that
can be reliably expected to decrement the counter is
4 f's - the period of the internal frequency.
With the values above for the internal frequency and the
viewing window, the tachometer range is 240 RPM to
62,500 RPM. By making use of the divide by 1/divide by 4
features of the oscillator di)lider, the range can be ex·
tended down to 60 RPM. The range when the oscillator
A viewing time of 250 ms is arbitrarily selected. This
means that the period of the output frequency is 500 ms
5-37
~
(")
;
0..
(")
0..
oo
fo
is divided by 4 is 60 RPM to 15,625 RPM. However, a
penalty is paid for this range extension. The viewing
window goes from 250ms to 1 second. The minimum
reliable pulse width also increase from 4"s to 16"s. The
added time spent counting mayor may not be acceptable. It can be reduced somewhat by changing the value
of RA to give a faster frequency at the reduced counter
clock frequency. However, as the OA frequency increases,
the low end of the range increases.
includes only the COP452 inter,tace and control. Other
system requirements, e.g., display interface, arithmetic,
etc., are not included here. Other data sheets and appli·
cation notes provide sufficient information to fill in
those details.
The hardware interface indicated in Figure 18 and the
code below, are completely general and valid for any
COPSTM microcontroller. In specific applications both
the hardware and software may be optimized to a greater
extent than that shown here.
A flow chart for this application is provided in Figure 19.
Sample code is given below. Note that the sample code
~
oo
OSCILLATOR
INPUT
VCC
I
I
CKI
L7
EXPAN OEO
LOW RA NGE
Y
00- L3
COP411L
OR LARGER
0
*
250 kHz
G2
51
L
OA
VCC
I
+
CKI
ENB
CS
00
SO
01
SK
SK
-DI
..I1..I1.
COP452
*
INB
_to.
SA-SH
8
01-04
to.
4
COP470
' - - - SK
CS
I
. Figure 18. COP452 in Wide Range Tachometer Application
5-38
MOTOR /I
ASSOCIATEO
ELECTRONICS
4 DIGIT
VF OISPLAY
(")
o"'tI
~
(J1
~
(")
WRITE F423
- RA/CA
o"'tI
WRITE FFFF
TO RB/C3
~
(J1
~w
(")
o"'tI
w
(J1
~
(")
NO
o"'tI
w
w
(J1
OUTPUT TO
DISPLAY
Figure 19. Flowchart for Tachometer Application
· PAGE
GSTATE
POWRON:
o
0, 15
CLRA
XAS
LBI
OBD
STII
LBI
OMG
LD
CAMO
LBI
STII
STII
STII
STII
; TURN OFF THE SK CLOCK-C = 0 AT POWER UP
GSTATE
; DRIVE D LINES HIGH TO DESELECT DISPLAY
15
GSTATE
; DESELECT THE COP452
; SET THE 0 REGISTER TO ALL l'S FOR INPUT
0, 0
3
2
4
15
; NOW SET UP TO WRITE RA OF COP452
; WRITE RA WITH F423 HEX
5-39
C")
LO
C")
D-
o
o
N
LO
C")
D-
O
o
M
LO
~
D-
O
~
TSTOAO:
LO
~
D-
O
o
ONECMP:
STII
STII
JSRP
LBI
STII
STII
JSRP
JSR
JS,R
LEI
LBI
INL
SKMBZ
JP
LBI
STII
STII
JSRP
LBI
STII
STII
JSRP
LBI
COMP
XIS
COMP
XIS
COMP
XIS
COMP
2
WRDATA
0,0
5
; REMEMBER COP452 IS RESET AT POWER UP
; TRANSFER RA TO CA
2
WRCMND
RSTRB
RANGE
4
0,0
;
;
;
;
RESET RB AND COUNTER B WITH FFFF
TEST RANGE AND SET OSCILLATOR DIVIDER
ENABLE Q TO L-DRIVE L LINES HIGH
LOOK FOR OA=O
3
. TSTOAO
0,0
6
2
WRCMND
0, a
; OA IS 0, READ COUNTER
; FIRST TRANSFER CB TO RB
; THEN READ RB
2
2
READ
0, a
; NOW TAKE THE 1'S COMPLEMENT
X
XFER1:
LBI
LD
XIS
JP
JSR
0,0
1
1
XFER1
RSTRB
; NOW SAVE VALUE IN R1
; RESET RB AND CB WITH FFFF FOR NEXT TIME
; AT THIS POINT INSERT THE APPROPRIATE CODE FOR ANY NECESSARY
; ARITHMETIC, BINARY/BCD CONVERSION, DISPLAY OUTPUT, AND ANY OTHER
; SYSTEM REQUIREMENTS. AFTER THESE ARE COMPLETE, JUMP TO LABEL
; TSTRNG WHICH HAS BEEN ARBITRARILY PLACED IN PAGE 4.
2
. PAGE
WRDATA:
WRCMND:
; SEE SOFTWARE INTERFACE SECTION FOR THESE
; THREE ROUTINES
READ:
TSTRNG:
TSTOA1:
. PAGE
JSR
LEI
LBI
INL
SKMBZ
JMP
JP
4
RANGE
4
0,0
; CHECK THE RANGE
; BE SURE Q IS ENABLED TO L
; LOOK FOR OA = 1
3
TSTOAO
TSTOA1
; THE SUBROUTINES RANGE AND RSTRB ARE INSERTED HERE
RANGE:
LEI
LBI
INL
X
CLRA
4
3,15
; MAKE SURE L ENABLED
; WILL SAVE RANGE STATUS IN 3, 15
; NOW PREPARE TO SET OSCILLATOR DIVIDER
5-40
o
o"tI
LOW:
HILOW:
AISC
SKMBZ
JP
AISC
LBI
XIS
STII
JMP
8
3
~
; AN 8 MEANS DIVIDE BY 1
o
HILOW
o"tI
; IF DIVIDE BY 4, WANT A 9 IN A
0,0
~
2
WRCMND
8
; THE FOLLOWING SUBROUTINE USES A SUBROUTINE LEVEL. IT RESETS BOTH
; REGISTER B AND COUNTER B OF THE COP452 TO FFFF
"tI
CA»
(J'I
RSTRB:
LBI
STII
STII
STII
STII
STII
STII
JSRP
LBI
15
15
15
15
~
CA»
0
2
WRDATA
; WRITE FFFF TO RB
0,0
C:-TII
STII
JMP
~
o"tI
0,0
;'
T~.A.~!S!=!::~ R~
TO
t::~
2
WRCMND
Application #4
The delay from the zero cross trip point is given by:
The triggered pulse mode of the COP452 provides the
capability of generating the appropriate signals for triac
control. Figure 20 is a general diagram of such an appli·
cation.
T=(A+ 1.5)t
where: T = delay from zero cross trip point
A = contents of register A
t = period of internal clock
Assume the requirement is to switch on the triac 45
degrees into the waveform. With a 60 Hz sine wave
signal. the 45 degree delay is 2.0833 ms from the zero
crossing. Assume also that the triac requires a gate
pulse width of 150"s. As the diagram indicates, a
2.097 MHz crystal provides the oscillator input to the
~~:'~:~. \_A_/~~~ ~'a...,,:,
':"'h .......... ;nf ..... l"rn"!lltinn the tUln \I!:1IllIac::
Solving for A we have:
A = (TIt) -1.5
= (2.0833 ms/1.9075"s) - 1.5
A = 1090.66 rounded up to lUlll
ttu:~t
must be loaded in the COP452 can be determined. With
CKI at 2.097 MHz and the oscillator divider at divide by 4,
the period of the internal frequency is 1.9075"s. From
the description of the triggered pulse mode, the pulse
width is given by:
Therefore register A and counter A must be initialized
with 1091 (0443 hex) to delay 2.0833ms (45 degrees at
60 Hz) from zero cross.
Once the data has been given to the COP452 and the
device placed in the triggered pulse mode, no further
attention is required. The COP452 will generate the
pulses with the appropriate delay as long as the power
is applied and the input sine wave is available. It is a
trivial matter to change any of the information. Merely
write the appropriate register/counter pair. Thus very
easy control is available over the firing angle of triacs.
T=8t
where: T = desired pulse width
8 = contents of register 8
t = period of internal clock
Solving for 8 is trivial and gives:
8 = Til
= 150"s/1.9075"s
=78.64
Sample code to accomplish this function is given below.
The code is general purpose and is written to work in
any COPSTM microcontroller.
Since the register and counter can be loaded with whole
numbers only. register 8 and counter 8 must be initial·
ized with 79 (002F hex) to give a pulse width of 150"s.
5-41
(II)
an
(II)
D..
2.097 MHz
0
0
0
C'
I
an
(II)
D..
1kQ
-=
VCC
OSC.
IN·
1MQ
0
0
CKI
-I-
56PF
CKO
(f)
an
COP411l
OR
LARGER'
"lit
D..
0
SO
01
SI
DO
OA
SK
SK
~
an
COP452
ZI
"lit
-=
D..
0
1BOVPEAK
60Hz 0
0
-=
VCC
RS
150kQ
-=
V
RS " ViN/10 x 7.Bk -7.Bk
" 1BO/10x7.Bk-7.Bk
:. RS ;i. 132.6kQ
:. ARBITRARILY SELECT RS = 150 kQ
Figure 20. COP452 as Triac Controller
. PAGE
GSTATE
POWRON:
CLRA
XAS
LBI
STII
LBI
OMG
LBI
STII
STII
STII
STII
STII
STII
JSRP
LBI
STII
STII
JSRP
LBI
STII
STII
STII
STII
STII
STII
JSRP
LBI
STII
STII
JSRP
LBI
STII
0
0,15
;
T~RN
OFF THE SK CLOCK
GSTATE
15
GSTATE
0,0
15
2
0
0
0
2
WRDATA
0,0
4
; DESELECT THE COP452-G2 HIGH
; NOW WRITE RB/CB WITH 002F HEX TO GIVE
; 150"s PULSE WIDTH
; TRANSFER RB TO CB
2
WRCMND
0,0
3
4
4
0
; NOW WRITE RA/CA WITH 0443 HEX FOR THE DELAY
2
WRDATA
0,0
5
2
WRCMND
0,0
; TRANSFER RA TO CA
9
5-42
()
o'"tJ
;
;
;
;
;
;
2
; SET OSCILLATOR DIVIDER TO DIVIDE BY 4
STII
JSRP
WRCMND
LBI
0, 0
; SET TRIGGERED PULSE MODE
STII
1
STII
3
JSRP
WRCMND
ALL COMPLETE AT THIS POINT. ROUTINES WRCMND AND WRDATA ASSUMED
IN PAGE 2 AND ARE THE SAME AS GIVEN IN SOFTWARE INTERFACE SECTION.
THE COP452 WILL NOW GENERATE THE 150 ~s PULSE DELAYED BY 2.0833 ms
FROM EVERY ZERO CROSSING. THE USER CAN NOW IGNORE THE TRIAC CONTROL
AND DO WHATEVER ELSE IS REQUIRED IN THE SYSTEM. FURTHER ATTENTION
IS REQUIRED ONLY WHEN THE DATA IN THE COP452 MUST BE CHANGED.
,j:o.
U1
~
()
o
'"tJ
-'="
U1
~CN
()
o
""CJ
CN
U1
~
()
Let us now compute the minimum and maximum delays
from the true zero crossing in this application. As indicated earlier, the period of the internal frequency here is
1.9075I-'s. Counter A contains 0443 hex (decimal 1091).
Rs is 150 k and the peak input voltage is 180 volts. A
60 Hz sine wave is assumed. As given earlier, the minimum time is:
As is obvious from the preceding analysis, the parameter previously defined as X, is the most significant of
the additional factors that define the time delay from
true zero. This factor can be minimized by using as
small a series resistance as possible. The frequency
and input voltage will be governed by the application.
The user must also remember that the minimum and
maximum times calculated in this manner are absolute
worst case values derived using the worst case
conditions.
1
~0.15 Rs +2.6k)+0.3f's
TMIN=(A+1.5t)---arcsin
2rrf
VIN x2.6k
Substituting we have:
TMIN = 1092.5t -
12~rr
arcsin
~.1518~5~.~.~ ~+ 0.3f'S
= 2093.9f's -129.7 f's + 0.3f's
TMIN = 1954.51-'s
Similarly, the maximum time is given as:
1
~0.15 RS+2.6k~+0.6I-'s+-t
TMAX =(A+1.5)t+--arcsin
2d
~Nx2.6k
2
Substituting we have:
TMAX = 1092.5t +
12~rr arcsin ~.1518~5~.~.~ ~+ 0.6f's +
1.9075 f's
2
= 2083.9f's + 129.7 f'S + 0.6f's + 0.9538f's
TMAX = 2215.151-'s
5-43
o'"tJ
CN
U1
CN
~
Q.
o(,)
~
Q.
o(,)
~'National
a
Semiconductor
COP470 and COP370 V.F. Display Driver
General Description
Features
The COP470 is a peripheral member of National's
COPSTM Microcontroller family. It is designed to directly
drive a multiplexed Vacuum Fluorescent display. Data is
loaded serially and held in internal latches. The COP470
has an on-chip oscillator to multiplex four digits of eight
segment display and may be cascaded and/or stacked
drive more digits, more segments, or both.
• Directly interfaces io multiplexed 4 digit by 8
segmenf Vacuum Fluorescent displays
• Expandable to drive 8 digits and/or 16 segments
• Compatible with all COP400 processors
• Needs no refresh from processor
• Internal or external oscillator
• No "glitches" on outputs when loading data
• Drives large and small displays
• Programmable display brightness
• Small (20·piri) dual·in-line package
• Operates from 4.5V to 9.5V
• Outputs switch 35 volts and require no external
resistors
• Static latches
• MICROWIRETM compatible serial I/O
• Extended temperature device COP370 (-40°C to
+85°C)
.
to
With the addition of external drivers, the COP470 also
provides a convenient means of Interfacing to a largedigit LED display. The COP370 is the extended temperature range version of the COP470.
COPS and MICROWIRE are trademarks
of National Semiconductor Corp.
Connection and Block Diagrams
SA
SC
S8
4
SO
2D
Sf
sc
19
SB
SA
18
17
SF
SG
SH
16
NOT USED
osc
voo
COP470
15
VGG .
14
D4
os
"
12
D2
VSS
11
0'
DI
SK
'0
3
SE
SO
2
01
SG
SF
SH
120191817
osc
03
02
04
11121314
03
Order Number COP470N, COP370N
NS Package N20A
Order Number COP470D,.COP370D
NS Package D20A
Figure 1. COP470 Pin
·Connection
DI-4-----------o~
~voo
.!!!.Vss
SK~-----------~~--_1
cs~-~---------~----4----~
Figure 2. COP470 Block Diagram
5-44
~VGG
o
Absolute Maximum Ratings
o
(Vss = 0)
"
oI:ao
Voltage at Display Outputs
+0.3V to -35V
Voltage at All Other Pins
+0.3V to -20V
Operating Temperature
COP4l0
O°C to +70°C
-40°C to +85°C
COP370
Storage Temperature
-65·C to +150·C
Lead Temperature (Soldering, 10 seconds)
300·C
Package Power Dissipation
400 mW at 25°C
200 mW at 70·C
125 mW at 85°C
DC Electrical Characteristics
P
o
o
"......
(0)
<:)
Vss=o, Voo =-4.5V to -9.5V, VGG =-30V to -35V, TA=O°C to 70°C for
COP470 and TA = 40·C to 85·C for COP370 unless otherwise specified.
Min.
Parameter
Max.
Unit
Power Supply Voltage
Voo
VGG (COP470)
VGG (COP370)
I
-9.5
-35
-32
-4.5
Voo
Voo
V
V
V
5
1
mA
mA
Power Supply Current
100
IGG (Display Blanked)
Input Levels
V1H
V1L
Output
IOH
IOH
IOL
-1.5
-10.0
Drive Digits and Segments
@ VoH=Vss-3V
@ VoH =Vss -2V
@ VoL =VGG+2V (See Note 1.)
Output Drive @ VGG=Voo=Vss-5V
IOH @ Vo H =Vs s-2V
+0.3
-4.0
V
V
10
7
10
mA
mA
1
mA
Allowable Source Current
Per Pin
IULo.J lUI vCylllt:::lll,="
,.A
20
mA
uv
1111"'\
Input Capacitance
7
pF
Input Leakage
1
JJ.A
20
JJ.s
AC 1::lectrical Characteristics
osc
Period (internal or external)
4
OSC Pulse Width
1.5
Clock Period T (twice Osc. period)
Display Frequency
4 digits = 1/64T
8digits=1/128T
SK Clock Frequency
SK Clock Width
JJ.s
8
40
JJ.s
390
190
2000
1000
Hz
Hz
0
250
kHz
1.5
JJ.s
1.0
50
JJ.s
ns
tSETUP
tHOLO
1.0
1.0
JJ.s
JJ.s
Duty Cycle
4 digits
8 digits
1/64
11128
Data Set·up and Hold Time
tSETUP
tHOLO
CS Set·up and Hold Time
Note 1.
10L
15/64
15/128
current is to VGG with the chip running. Current is measured just after the output makes a high·lo·low transition.
5-45
o
~
Il..
Timing Diagram
-I
-I - 1-l-sKw'DTH
oo
CS SETUP
~--'~~
~
________________
I I
Il..
H~tD
1-
~~r--
I
SK
oo
I0
DI~IOI
-I
-SETUP
-I-HDLD
Figure 3. Serial Load Timing Diagram
Performance Characteristic
-28
-24
.
-20
E
-12
E
-16
-8
-4
-2
-4
-6
-8 -10 -12 -14
VOH VOLTS
OUTPUT SOURCE CURRENT
Functional Description
The fifth and sixth bits control the multiplex digits. To
enable the COP470 to drive a 4 digit multiplex display,
set both bits to one. If two COP470s are used to drive an
8 digit display, bit five is set on the left COP470 and bit
six is set on the right COP470 (see Fig. 6). In the eight
digit mode, the display duty cycle is on time/128.
Segment Data Bits
Data is loaded in serially in sets. Each set of segment
data is in the following format:
I SA I SB I SC I SO I SE I SF I SG I SH I
Data is shifted into an eight bit shift register. The first
bit of the data is for segment H, digit 1. The eighth bit is
segment A, digit 1.
The seventh bit selects internal or external oscillator.
The OSC pin of the COP470 is either an output of the
internal oscillator (bit 7 = 0) or is an input allowing the
COP470 to run from an external oscillator (bit 7 = 1).
A set of eight bits is shifted in and then loaded into the
digit one latches. The second set of 8 bits is loaded into
digit two latches. The third set into digit three latches
and the fourth set is loaded into digit four latches.
The eighth bit is set to synchronize two COP470s. For
example, to set the COP470 to internal osc, 4 digits, and
maximum brightness, send out six ones and two zeros.
Display on Time and Control Bits
The fifth set of 8 data bits contains blank time data and
control data in the following format:
Display Digits
I
Sync
Ext. I Right
Left i....- On Time _
Osc. 14 of 814 of 81 LSB
I
I MSB I
the first four bits Shifted in contain the on time. This is
used to control display brightness. The brightness is a
function of the on time of each segment divided by the
total time -(duty cycle). The on time is programmable
from 0 to 15 and the total time is 64. For example, if the
on time is 15, the duty cycle is 15/64 which is maximum
brightness. If on time is 8, the duty cycle is 8/64, about
112 brightness. There are 16 levels of brightness from
15/64 to 0/64 (off).
Figure 4. System Diagram -
5-46
4 Digit Display
(')
0
"'0
.;..
.......
~o
11~15T-1
(')
64T
ANY SEGMENT
~
U
ON
0
'\
T __
OFF
ON
"'0
Col
.......
ON
0
r--
01J
ON TIME = 15
(MAX BRIGHTNESSI
01
03
04
1
OFF
1~15T~I_T
n
ANY SEGMENT
I
I
ON TIME = B
01~
I
II
n
n
Dl~
ON TIME = 1
Figure 5. Segment and Digit Output Timing Diagram
I
_ _ .-I! _ _
.... _ _ _ _ _ _ _ _ _
- - - - ••• t; - ........ - _ •• __ •
This synchronizes both chips, sets to external
oscillator, and to right four of eight digits. Thus
both chips are synchronized and the oscillator
is stopped.
Step
1
2
3
4
5
6
Turn CS Low.
7
Turn CS high.
Clock in 8 bits of data for digit 1.
4.
5.
6.
7.
Clock in 8 bits of data for digit 2.
Clock in 8 bits of data for digit 3.
Clock in 8 bits of data for digit 4.
Clock in 8 bits of data for on time and control
bits.
8.
Note: CS may be turned high after any step. For example, to
load only 2 digits of data do steps 1,2,3, and 7. CS must
make a high to low transition before loading data in order to
reset internal counters.
Turn CS high to both chips.
Turn CS low to the left COP470.
Shift in 32 bits of data for the left 4 digits.
Shift in 4 bits of on time, a one and three zeros.
This sets this COP470 to internal oscillator and
to left four of eight digits. Now both chips start
and run off the same oscillator.
Turn CS high.
The chips are now synchronized and driving eight digits
of display. To load new data simply load each chip
separately in the normal manner.
8 Digit Displays
16 Segment Display
Two COP470s may be tied together in order to drive an
eight digit multiplexed display. This is shown in Figure
6. The following is the loading sequence to drive an
eight digit display using two COP470s.
Two COP470s may be tied together in order to drive a
sixteen segment dispiay. This is shown in Figure 8. To
do this, both chips must be synchronized, one must run
off external oscillator while the other runs off its
internal oscillator outputting to the other. Similarly, four
COP470s could be tied together to drive eight digits of
sixteen segments.
1.
Turn CS low on both COP470s.
2.
Shift in 32 bits of data for the right 4 digits.
5-47
o
"""
Q.
o
()
o
C")
8 DIGIT VF DISPLAY
sa,
SA.
III 02 03 04
SC,
so,
SE, SF, S6, P
05060708
{)
oo::t
"""
Q.
o()
8
j
SA·SH
SEGMENTS
I
I
SA·SH
COP470
ICHIP 81
COP470
ICHIPAI
r---
so
SK
011
CS
I
I
I
SK
COP400
SK
011'
cS"1
00
01
'---
Figure 6. System Diagram 8 Digit Display
-----,~__~01~___C~H~IP~A________________________________~~~________
CHIP A
- f 0 2 l~~~~--------------------~
03
rcHiPAlL -____________________________
~r
04
CHIP A
01
CHIP 8
r____,
r__I~
______ 02 __
~
~~
CHIP 8
________
________________________
~r___lL_
__________________
______~
03 __~~
CHIP B ____________~r____,L______________
______ 04 __
~
---,
~~
CHIP B
SEGMENT CHIP A
__________________
r---I~
~r___l~
__________________
__________
~r___lL_
________~S~EG~M~EN~T~C~HIP~8~________·~~____~r__I~
______________
RESULTANT SEGMENT
SEG. CHIP A & SEG. CHIP 8 WIRED TOGETHER
Figure 7. Segment and Digit Output Timing Diagram for 8
Digits
4 OIGIT, 16 SEGMENT
VF DISPLAY
~~
~~
8
SEG.
SA·SH
I
01 02 03 04
COP470
SK
01
-
so
SK
cOP
'DO
1
cs
I
OSC
B
SEG.
II
SA·SH
0' 03 02 01
COP47Q
01
I
1
00
01
Figure 8. System Diagram for 16 Segment Display
5-48
____
SK
cs
LED Display
The COP470 may be used to drive LED displays. The
COP470 can drive the segments directly on small, low
current LED displays as shown in Figure 9. By adding
display drivers, large, high current LED displays can be
driven as shown in Figure 10.
Example:
COP420 Code to Load COP470
(Display Data is in Memory 0, 12 -
I ()()p.
0, 15)
LB10,12
; Point to first display data
aBO
; Turn CS low (DO)
GLR.A
LOID
: Look up segment data
COMA
; Copy data from 0 to M & A
SC
XAS
Nap
; Set C to turn on SK
Nap
; Delay
; Output lower 4 bits of data
; Delay
LD
; Load A with upper 4 bits
XAS
; Output 4 bits of data
NOP
Nap
; Delay
RC
; Reset C
; Delay
XAS
; Turn off SK clock
XIS
; Increment B for next data
_.
,VI\ltJ
SC
o.
~III;:'
JUllltJ a l l e l
1000:H UI~ll
; Set C
CLRA
AISC 15
; 15 to A
XAS
NOP
; Output on time (max brightness)
CLRA
AISC 12
; 12 to A
XAS
Nap
; Output control bits
LB10,15
; 15 to B
RC
; Reset C
XAS
; Turn off SK
aBO
; Turn CS high (DO)
5-49
1-11-1 • 1-11-'
l Il 1 • l Jl ,
,
1
-20 VOLTS ---'-
8
12 10
5
6
3
2 13
..:::J 14
11
7
16 240 Q
9L
4
*
+5 ylTS
A
00
COP420
SO
SK
B
C
0
E
F
G H
01
CS
01
02
03
04
VGG
r-I - - - - 20 VO LTS
COP470
SK
VOO
..L
..L
Figure 11. Sample V.F. System
5-50
~ +5 VOLTS
o
o"'D
'?'A National
D Semiconductor
.a:=o
......
I\)
COP472 Liquid Crystal Display Controller
General Description
Features
The COP472 Liquid Crystal Display (LCD) Controller is a
peripheral member of the COPSTM family, fabricated
using CMOS technology. The COP472 drives a multi·
plexed liquid crystal display directly. Data is loaded
serially and is held in internal latches. The COP472
contains an on-chip oscillator and generates all the
multi-level waveforms for backplanes and segment
outputs on a triplex display. One COP472 can drive 36
segments multiplexed as 3 x 12 (4 % digit display). Two
COP472 devices can be used together to drive 72
segments (3 x 24) which could be an 8% digit display.
• Direct interface to TRIPLEX LCD
• Low power dissipation (1001'W typ.)
•
•
•
•
•
•
Low cost
Compatible with all COP400 processors
Needs no refreSh from processor
On·chip oscillator and latches
Expandable to longer displays
Software compatible with COP470 V.F. Display Driver
chip
• Operates from display voltage
MlljH0vvIHt:~;·; compalioie seriai ii0
•
• 20-pin dual-in-line package
COPS and MICROWIRE are trademarks of National Semiconductor Corp.
BPA BPe BPc
12 SEGMENT BUFFERS
12
VDD
GND
DI~I----I
SK--~----------~--~
~--r-----------------------~------------J
COP472 Block Diagram
5-51
~
-.:t.
Il..
oo
Absolute Maximum Ratings
Voltage at CS, DI, SK pins
Voltage at all other Pins
Operating Temperature Range
Storage Temperature
Lead Temperature (Soldering, 10 Seconds)
-.0.3V to + 9.5V
-0.3V to VDD + 0.3V
O'Ct070'C
-65'Cto +150'C
300'C
DC Electrical Characteristics
GND =ov, VDD =2.4V to 5.5V, TA =O°C to 70°C
(depends on display characteristiCs)
Parameter
Min.
Max.
Units
2.4
5.5
Volts
VDD=5.5V
250
jJA
V DD=3V
100
jJA
0.7VDD
0.8
9.5
Volts
Volts
VDD-O.6
0.6
VDD
Volts
Volts
VDD -0.4
0.4
VDD
Volts
Volts
During
BP+Time
VDD-IN
V,V DD -IN
VDD
V,VDD+IN
Volts
Volts
During
BP- Time
0
2/,VDD -IN
IN
2/,VDD+AV
Volts
Volts
During
BP+ Time
0
·V,VDD-AV
AV
V,VDD+AV
Volts
Volts
During
BP- Time
VDD-AV
V,VDD'-AV
VDD
V,VDD+AV
Volts
Volts
Conditions
Power Supply Voltage, V DD
Power Supply Current, IDD (Note 1)
Input Levels
DI, SK, CS
V1L
V1H
BPA (as Osc: In)
V1L
V1H
Output Levels, BPC (as Osc. Out)
VOL
VOH
Backplane Outputs (BPA, BPB, BPC)
VBPA, BPB, BPC ON
VBPA, BPB, BPC OFF
VBPA, BPB, BPC ON
VBPA, BPB, BPC OFF
Segment Outputs (SAl'" SA4)
VSEG ON
VSEG OFF
VSEG ON
VSEG OFF
Internal Oscillator Frequency
15
80
kHz
Frame Time (Int. Osc. -;- 192)
2.4
12.8
ms
Scan Frequency (1/TscAN )
39
208
Hz
4
250
kHz
SK Clock Frequency
SK Width
1.7
jJs
1.0
100
IJ.S
ns
1.0
1.0
IJ.s
IJ.s
DI
Data Setup, tSETUP
Data Hold, tHOLD
CS
tSETUP
t HOLD
100
Output Loading Capacitance
Note 1: Power supply current is measured in stand·alone mode with all outputs open and all inputs at VDD.
Note 2: AV =O.05VDDfor VDD;;>3V. AV=O.15V for VDD<3V.
5-52
pF
COP472
Connection Diagram
SB.
SC3
20
19
SB'
cs
18
17
V"
.6
GNO
15
DI
SA2
SB'
SB2
14
13
12
10
11
SA'
SA3
SCI
BPB
BPC
BPA
SK
SC'
SC2
SAl
Description
Pin
Voo
Chip select
Power supply (display voltage)
GND
Ground
01
Serial data input
Serial clock input
Display backplane A(or oscillator in)
CS
SK
BPA
BPs
BPc
Order Number COP472N
NS Package N20A
Order Number COP472D
NS Package D20A
Display backplane B
Display backplane C (or oscillator out)
SA 1'" SC4
12 multiplexed outputs
Figure 2. Connection Diagram
cs
__I I-cs
--r
r-
I-
SETUP
SK WIDTH
I
I I.
SK
01
1-I
II
101
-.!-I
SETUP
-HOLD
I=lnllrA
~_
SArlal LDad Tlmlno Dlaaram
USC
VDD
SCI
'h
BPA '13
o
SAl
SBI
~~.;ok
A
Voo
BPB ~,
.:T:.
,/,
o
Voo
8pe
:Z:~~+_--J
-o
U
L...._ _ _
Voo
'I,
SEGMENT ,/,
o
Figure 4.. Backplane and Segment Waveforms
SP
1if
Figure 5. Typical Display Internal Connections
Epson LD-370
5-53
BPB
Functional Description
Segment Dala bits
The COP472 drives 36 bits of display information organized as twelve segments and three backplanes. The
COP472 requires 40 information bits: 36 data and 4 can·
trol. The function of each control bit is described below.
Display information format is a function of the LCD
interconnections. Atypical segm~nt/backplane configu·
ration is illustrated in Figure 5, with this configuration
the COP472 will drive 4 digits of 9 segments.
Data is loaded in serially, in sets of eight bits. Each set
of segment data is in the following format:
I SA I SB I SC I SO I SE I SF I SG I SH I
Data is shifted into an eight bit shift register. The first
bit of the data is for segment H, digit 1. The eighth bit is
segment A, digit 1. A set of eight bits is shifted in and
then loaded into the digit one latches. The second set of
8 bits is loaded into digit two latches. The third set into
digit three latches, and the fourth set is loaded into digit
four latches.
To adapt the COP472 to any LCD display configuration,
the segment/backplane multiplex scheme is iIIustated in
Table 1.
Two or more COP472 chips can be cascaded to drive ad·
ditional segments. There is no limit to the number of
COP472's that can be used as long as the output loading
capacitance does not exceed specification.
Control Bits
The fifth set of 8 data bits contains special segment
data and control data in the following format:
ISYNC I
Table 1. COP472 Segment/Backplane Multiplex Scheme
Data to
Numeric Display
BII Number
Segment, Backplane
1
2
3
4
5
6
7
8
SA1, BPC
SB1, BPB
SC1, BPA
SC1, BPB
SB1, BPC
SA1, BPB
SA1,BPA
SB1, SPA
SH
SG
SF
SE
SO
SC
SB
SA
9
10
11
12
13
14
15
16
SA2,BPC
SB2,BPB
SC2,BPA
SC2, BPB
'SB2,.BPC
SA2, BPB
SA2,BPA
SB2, BPA
SH
SG
SF
SE
SO
SC
SB
SA
Digit 2
17
18
19
20
21
22
23
24
SA3; BPC
SB3,BPB
SC3,BPA
SC3, BPB
SB3, BPC
SA3,BPB
SA3,BPA
SB3, BPA
SH
SG
SF
SE
SO
SC
SB
SA
Digit 3
25
26
27
28
29
30
31
32
SA4, BPC
SB4, BPB
SC4, BPA
SC4, BPB
SB4, BPC
SA4,BPB
SA4, BPA
SB4, BPA
SH
SG
SF
SE
SO
SC
SB
SA
Digit 4
33
34
35
36
37
38
39
40
SC1, BPC
SC2, BPC
SC3, BPC
SC4, BPC
not used
06
07
SYNC
SP1
SP2
SP3
SP4
Digit
Digit
Digit
Digit
07
I
06
I
X
I SP4 I
SP3
I SP2 I
SP1
I
The first four bits shifted in contain the special character
segment data. The fifth bit is not used. The sixth and
seventh bits program the COP472 as a stand alone LCD
driver or as a master or slave for cascading COP472's.
BPC of the master is conected to BPA of each slave.
The following table summarizes the function of bits six
and seven:
07
Digit 1
a6
BPe Output
BPA Output
Slave
Backplane
Output
Stand Alone
Backplane
Output
Backplane
Output
O·
Not Used
Internal
Osc. Output
Oscillator
Input
0
Master
Internal
Osc. Output
Backplane
OU)put
o
o
Function
. Oscillator
Input
The eighth bit is used to synchronize two COP472's to
drive an 8Y2-digit display.
1
2
3
4
5-54
Vee
Loading Sequence to Drive a 4Y2·Digit Diaplay
Steps:
1. Turn CE low.
2. Clock in 8 bits of data for digit 1.
COP42D
3. Clock in 8 bits of data for digit 2.
4. Clock in 8 bits of data for digit 3.
5. Clock in 8 bits of data for digit 4.
GND
SO
SK
DO
1-----1
6. Clock in 8 bits of data for special segment and control
function of BPC and BPA.
o
!
0
1
1
DISPLAY
VOLTAGE
~-----I
1-----1
' - - - - r - -.....
SP4 SP3 SP2 SP1
7. Turn CS high.
Figure 6. System Diagram -
Note: CS may be turned high after any step. For example
to load only 2 digits of data, do steps 1,2,3, and 7.
4% Digit Display
CS must make a high to low transition before loading
data in order to reset internal counters.
I ,..,~ft;n,.. c:..o.nl u~",..a in nrh,.o ~n
- - - - - - - - . - - - . - - - - - - - - - - - . - ---
8'1, DIGIT LCD
A 11" .ni"it nie:nl!:llu
-
--
--""-- - - - r - - ..
Vee
Two or more COP472's may be connected together to
drive additional segments. An eight digit multiplexed display is shown in Figure 7. The following is the loading sequence to drive an eight digit display using two COP472's.
The right chip is the master and the left the slave.
VDD
COP420
Steps:
SO
SK
DO
1. Turn CS low on both COP472's.
2. Shift in 32 bits of data for for the slave's four digits.
GND
3. Shift in 4 bits of special segment data: a zero and
three ones.
01
-=
I 1 I 1 I 1 ! 0 I SP4 I SP3 I SP2 I SP1 I
This synchronizes both the chips and BPA is oscillator input. Both chips are now stopped.
4 Tmn CS hieh te both chios.
Figure 7. System Diagram - 8 th Digit Display
5. Turn CS low to master COP472 ..
6. Shift in 32 bits of data for the master's 4 digits.
7. Shift in four bits of special segment data, a one and
three zeros.
! 0 I 0 I 0 I 1 I SP4 ! SP3 ! SP2 I SP1 I
This sets the master COP472 to BPA as a normal
backplane output and BPC as oscillator output. Now
both the chips start and run off the same oscillator.
8. Turn CS high.
The chips are now synchronized and driving 8 digits of
display. To load new data simply load each chip separately in the normal manner, keeping the correct status
bits to each COP472 (0110 or 0001).
5-55
VDD
~
:.
8
Example Software
Example 1
COP420 Code to load a COP472 [Display data is in M(O, 12)-M(O, 15), special segment data is in M(O, 0)]
LOOP:
LBI 0, 12
OBD
CLRA
LQID
CQMA
SC
XAS
NOP
NOP
LD
XAS
NOP
NOP
RC.
XAS
XIS
JP LOOP
SC
LBI 0, 0
LD
XAS
NOP
CLRA
AISC 12
XAS
NOP
LBI 0, 15
RC
XAS
OBD
; POINT TO FIRST DISPLAY DATA
; TURN CS LOW (DO)
; LOOK UP SEGMENT DATA
; COPY DATA FROM Q TO M & A
; SET C TO TURN ON SK
; OUTPUT LOWER 4 BITS OF DATA
; DELAY
; DELAY
; LOAD A WITH UPPER 4 BITS
; OUTPUT 4 BITS OF DATA
; DELAY
; DELAY
; RESET C
; TURN OFF SK CLOCK
; INCREMEI'-IT B FOR NEXT DATA
; SKIP THIS JUMP AFTER LAST DIGIT
; SET C
; ADDRESS SPECIAL SEGMENTS
; LOAD INTO A
; OUTPUT SPECIAL SEGMENTS
; 12 to A
; OUTPUT CONTROL BITS
; 15 to B
; RESET C
; TURN OFF SK
; TURN CS HIGH (DO)
5-56
Example 2
COP420 Code to load two COP472 parts [display data is in M(O, 12)-M(0,15) and M(1, 12)-M(1, 15), special segment data is
in M(O, 0) and M(1, 0)]
INIT:
LBI
OBD
LEI
RC
XAS
LBI
STII
LBI
JSR
0,15
8
; TURN BOTH CS'S HIGH
; ENABLE SO OUT OF S_ R_
3,15
7
0,12
OUT
; TURN OFF SK CLOCK
; USE M(3, 15) FOR CONTROL BITS
; STORE 7 TO SYNC BOTH CHIPS
; SET B TO TURN BOTH CS'S LOW
; CALL OUTPUT SUBROUTINE
MAIN DISPLAY SEQUENCE
DISPLAY:
LBI
STII
LBI
JSR
LBI
c::TII
LBI
JSR
3,15
8
0, 13
OUT
3, 15
'1," 14
OUT
; SET CONTROL BITS FOR SLAVE
; SET B TO TURN SLAVE CS LOW
; OUTPUT DATA FROM REG_ 0
-
~~T
r.ONTROI
RIT~ ~OR
MASTER
; SET B TO TURN MASTER CS LOW
; OUTPUT DATA FROM REG. 1
OUTPUT SUBROUTINE
OUT:
LOOP:
OBD
CLRA
AISC
CAB
CLRA
LaiD
COMA
SC
XAS
NOP
NOP
; OUTPUT B TO CS'S
12
; 12 TO A
; POINT TO DISPLAY DIGIT (BD=12)
; LOOK UP SEGMENT DATA
TO M & A
; COPY DATA FROM
a
; OUTPUT LOWER 4 BITS OF DATA
; DELAY
; DELAY
LU
, LUAU A VVII M ut"'t"'t:.t1 4 011 v
XAS
NOP
NOP
RC
XAS
XIS
JP
SC
NOP
LD
XAS
NOP
LBI
LD
XAS
NOP
NOP
RC
XAS
OBD
RET
; OUTPUT 4 BITS OF DATA
; DELAY
; DELAY
; RESET C
; TURN OFF SK
; INCREMENT B FOR NEXT DISPLAY DIGIT
; SKIP THIS JUMP AFTER LAST DIGIT
; SET C
LOOP
; LOAD SPECIAL SEGS. TO A (BD=O)
; OUTPUT SPECIAL SEGMENTS
3,15
; LOAD A
; OUTPUT CONTROL BITS
; TURN OFF SK
; TURN CS'S HIGH (BD=15)
5-57
en
~ ~National
8is a Semiconductor
~
COP4981COP398 Low Power CMOS RAM and Timer (RArM)
oo COP499/COP399 Low Power CMOS Memory
~
fo
I
o
o
General Description
Features
The COP498/398 Low Power CMOS RAM and Timer (RAT)
and the COP499/399 Memory are peripheral members of
the COPSTM family, fabricated using low power CMOS
technology. These devices provide external data storage
and/or timing, and are accessed via the simple MICROWIRETM serial interface. Each device contains 256 bits
of read/write memory organized into 4 registers of 64 bits
each; each register can be serially loaded or read by a
COPS controller.
• Low power dissipation
The COP498/398 also contain a crystal·based timer for
timekeeping purposes, and can provide a "wake-up"
signal to turn on a COPS controller. Hence, these devices
are Ideal for applications requiring very low power drain
In a standby mode, while maintaining a real-time clock
(e.g., electronically-tuned automobile radio). Power is
minimized bY'cycling controller power off for periods of
time when no processing is required.
The COP499/399 contain circuitry that enables the user
to turn a controller on and off while maintaining the
integrity of the memory.
A COP400 series N-channel mlcrocontroller coupled
with a COP498 (or 499) RAM/Timer offers a user the lowpower advantages of an all CMOS system and the lowcost advantage of an NMOS system. This type of system
is Ideally suited to a wide variety of automotive and instrumentation applications.
• Quiescent current = 40 nA typical (25°C, Vee = 3.0V)
• Low cost
• Single supply operation (2.4V-5.5V)
• CMOS-compatible I/O
• 4 x 64 serial read/write memory
• Crystal-based selectable timer 32.768 kHz (COP498/398)
• Software selectable 1 Hz or 16 Hz "wake-up" signal
for COPS controller (COP498/398)
• External override to "wake-up" controller
• Compatible with ali COP400 processors (processor
Vee" 9.5V)
• MICROWIRE-compatlble serial I/O
• Memory protection with write enable and write disable
instructions
• 14-pin dual-in-line package (COP498/398) or' 8-pin
dual-in-line package (COP499/399)
TRI-8TATE Is a registered trademark of National Semiconductor Corp.
qops, MICROWIRE. and RAT a,re trademarka of National Semiconductor Corp.
osc
13
XOUT
"N
CE
_r--",-"
'------
••••••
Y
~~~ ....................
1
2
3
4
5
."
ct
I
~
~'I"" Vee=4.5V '"
~
ct
ao
.-----,--,..-,----.---r----,
1.
Vee=~!., •••
E
."
600 1---+--="'k-+--+--1---I
BOO
,-o~e, oJ ONLY
I
1. 25
Minimum Source Current
lor DO, 1Hz
o
~
6
VOUT-V
VOUT- V
eo
o
."
Maximum Standby
Current lor COP4981398
..1 I I
1. •
I
---
....
!
1 1I]
fy'N = 2.1 MHZII,
'"
>-
:ill
z
200
j!
'"
~
/
400
::>
Maximum Sink Current
lor mil
400
300
I
~.-+---l--1--+---l---j
1.
I
~ 10~-+-~~~~--r~
~ 200 I-\---/--+-t---/---t----I
~
~
z
",/
rxl~=32.~~
::I~-+--~-+~~-~-;
Minimum Source Current
lor ON
::>
I
100
f-4
Vce - v
VOUT-V
Maximum COP4981398
Operating Current
VOUT V
XOUT Minimum Sink
Current with XSEL = 1
XOUT Minimum Source
Current with XSEL = 1
1000 .-----,--,..-,----.---r----,
I
:Fkf·1111
~
.4t--t-~~~-t--t---l
1.
I 750
~
E
~
.50 t--t-7f-;,,;""+--t--t---l
~
::>
co
.25 t--H'--+--+--t--t---l
300
"T'"
4
SK FREQUENCY - kHz
VOUT
V
VOUT V
XO UT Minimum Sink
Current with XSEL = 0
Maximum COP4991399
Operating Current
XOUT Minimum Source
Current with XSEL = 0
40t--t-+--t--t--t----I
I
300~-+-1--t--+--r--;
VCC=5.5V
15
'"
'"
B
z
'"z
Ei
~
co
1.
~ 20t--t--t--+-~~-t---j
200
~
100~-+~-~~~-+~~--;
SKFREQ - kHz
w
'"
'"
~
20 I==+="",,~lc--+--+--l
"T
10t--t--,~-+--t--t---j
VOUT-V
5-63
10
VOUT-V
i
0)
0)
C")
D..
0
0
as
WRITE
0)
C")
D..
r
L
CS
01
0
0
c»
SK
0)
1 _ REAOINSTR==
oqo
D..
DI
0
0
READ
as
DO
~
D..
0
______-'1
1
1
\
0
n-
~X.__
. "_DO......., _ _ _ _ _-1/,/'-_ _ _ _ __
I':~~~~~~~~~~~~_TR_I-S_T_AT_E"~~~~~~~~~~~~:'i!
__
~CL_DA_T-0:
0
TO VCO's
P~~:~~~ t-"'-'lNIr--I
:JT~~~r-------~~VV~-t
OATA
L-_ _.I CLOCK
VOIAS
DS0900
PLl SYNTHESIZER
(20·PIN)
PROGRAM
RESISTORS
L...--_-Il.90 MHz
PROGRAM
RESISTOR
BIT 19 OUT
L...----~50 Hz
BIT 18 OUT
VCCM
UNSWITCHEO
0+
VCCI
SWITCHED B+
TO RAOIO
5-87
GNO
TO RADIO CONTROL CIRCUITS
(MUTE. GAIN. AM. FM. STEREO)
D58908
r-
o
CQ
5"
AM/FM PLL/Synthesizer(Serial Data 20-Pin Package)
2
1.98 MHz
I»
CQ
;
3
osc B
r<'
1:.....0
1
t::::I
+2
......-.t
1
+11
,
~
1 +91
,
~I
50 Hz
OUTPUT
+2
OSC C
3.96 MHz
XTAL
10kHz
U1
I
~
r-------......
~~~~GE
1•
FM
LO
RpRDGRAM
OUTPUT
VCC2
CLOCK
CLOCK IGATED)
~
OPAMP
OUTPUT
~1
18-BITSHIFT REGISTER
,
DATA
~
ENABLE
~
•
VBIAS
19
•
•
D>o-----+I
5V
----0lIl
VCCI
5V~VCCM
• Sections operating from VCCM supply.
•• Address (1,1)
BIT 19
OUTPUT
BIT 18
OUTPUT
r
GND
~National
a
Semiconductor
MM5445, MM5446, MM5447, MM5448
VF Display Drivers
General Description
The MM5445 through MM5448 are monolithic MaS integrated circuits utilizing P-channel metal gate low threshold, enhancement mode and ion-implanted depletion
mode devices. They are available in 40-pin molded dualin-line packages. Each output can source up to 500l'A at
2.0V maximum output voltage. A single pin controls the
VF display brightness by selting the positive output
voltage level.
• Wide power supply operation
• TTL compatibility
• 33,34 or 35 outputs, 500l'A source capability
• Alphanumeric capability
• Input data format compatible with MM5450,
MM5451 LED drivers and MM5452, MM5453 LCD
drivers
-4nnli~$11linn~
,-.- .... __ .... _.. _• cOPS or microprocessor displays
• Industrial control indicator
• Digital clock, thermometer, counter, voltmeter
• Continuous brightness control
• Serial data input
• No load signal required
• Enable (on MM5445 and MM5446)
• Instrumentation readouts
200 kll
Block Diagram
Vss
OUTPUT 33
25
OUTPUT 1
• • •
1B
200kll
200kll
19
Voo --"+I
VG.
OUTPUT 34 IMM5446. 47. 4B)
~~~~~~1:l;~~~~4::1~--"":;::j--.
DATA
BRIGHTNESS CONTROL IMM5447)
OATA..----..-.
CLOCK ~----=..;t-I
,r-...::=:...:::::::':"=:::..:r::.l
>----..
':' vo.
Connection Diagrams
40
VDD
J9
OUTPUT BIT 17
3B
OUTPUT BIT 16
J7
OUTPUT BIT 15
J6
OUTPUT SIT 14
J5
OUTPUT SIT 13
34
OUTPUT BIT 12
OUTPUT BIT 11
OUTPUT BIT 10
OUTPUT BIT9
OUTPUT'SIT 8
OUTPUT BIT 1
OUTPUT SIT6
OUTPUT BITS
OUTPUT 81T 4
OUTPUT BIT 3
OUTPUT BIT2
OUTPUT BIT 1
VGG
V,S
(Dual-In-Line Packages)
10
11
MM54451
MM5446
OUTPUT SIT 17
3D
"
2B
14
21
15
26
"
"
18
2J
"
2Z
24
Z1
40 OUTPUT 81T 18
"
JB
OUTPUT81T19
OUTPUT 81T 20
OUTPUT BIT 20
OUTPUT BIT 16
DUTPUTBIT21
OUTPUT BIT 15
OUTPUT BIT 21
OU1PUT81122
OUTPUT81T14
OUTPUT 81T 22
OUTPUT BIT 23
OUTPUT BIT 13
OUTPUT 81T 23
OUTPUT BIT 24
OUTPU181112
OUTPUT BIT 24
OUTPUT BIT 25
OUTPUT BIT 11
OUTPUT BIT 10
OUTPUT BIT9
OUTPUT 81T27
29
2D
VDO
OUTPUT BITU
JJ
OUTPUT BIT 25
J2
OUTPUT BITZI
J1
12
"
OUTPUT BIT 18
OUTPUT BIT 28
OUTPUT BITB
OUTPUT BIT 29
OUTPUT BIT 1
OUTPUT BIT 30
OUTPUT BITI
OUTPUT BIT 31
OUTPU18115
OUTPUT BIT 32
OUTPU1BIT4
OUTPUT BIT 33
OUTPUT Bll 3
BRIGHT CONTR/OUTPUT 81T 34
OUTPUT BIl2
I!ATXlllAm
OUTPUT BIT 1
DATA IN
VGG
CLOCK IN
Vss
TOP VIEW
OUTPUT BIT 26
10
11
MM54471
MM5448
J1
3D
12
29
"
"
2B
11
"23
14
27
16
"
25
18
"
2Z
21
lD
OUTPUTBIT2l
OUTPUT 81T 28
OUTPUTBIT29
OUTPUT BIT 30
OUTPUT BIT 31
OUTPUT BIT 32
OUTPUT BIT 33
OUTPUT BIT 34
BRIGHT CONTR/OUTPUT BIT 35
DATA IN
CLOCK IN
TOP VIEW
Order Number MM5445N, MM5446N
NS Package N40A
Order Number MM5447N, MM5448N
NS Package N40A
Figure 2a
Figure 2b
5-89
Absolute Maximum Ratings
Voltage at Any Pin
Operating Temperature
Storage Temperature
Power Dissipation
Junction Temperature
l,ead Tempe~ature (Soldering, 10 seconds)
Electrical Characteristics
TA within operating range, Voo = OV, Vss = 4.5 to 5.5V, unless otherwise specified.
Parameter
Power Supply
Vss
VGG
Vss
Power Supply Current
Iss
IGG
Brightness Control
Input Logic Levels
Logic "0" Level
Logic "1" Level
Logic "0" Level
Logic "1" Level
Input Currents
DATA IN and CLOCK
PATA ENABLE
BRIGHTNESS CONTROL
Output Source Current
Segment OFF
Segment ON
Vss to Vss - 30V
-40'Cto +85'C
-65'Cto +150'C
560mWat +85'C
1Wat +25'C
+150'C
300'C
Conditions
Vss=5V
Voo=VGG=O
Vss = 5V, VGG = -25V
Voo=O
With respect to Vss
-25V'; VGG'; -7V
-25V'; VGG'; -7V
Voo=VGG=O
Voo=VGG=O
Min.
Typ.
Max.
Units
4.5
-25
12
5.0
5.5
-7
18
V
V
V
9
-2
(Vss - VGG)/2
Vss
mA
mA
V
-0.3
2.2
-0.3
Vss-1
0.7
Vss+0.3
1
Vss+0.3
V
V
V
V
-10
-10
10
35
2
IlA
IlA
mA
-2
250
IlA
IlA
kHz
60
%
0.5
V
Excluding Output Loads
(Note 2)
VOUT = (Vss - VGG)/2
Your = Vss - 2V (Notes 1 and 2)
500
Input Clock Frequency
0
Duty Cycle
40
Output Matching
50
-0.5
lour= 5OOIlA
Nole 1: With Brightness Control lied to Vss (MM5445 and MM5447) and VGG = -25V.
Nole 2: All output source current is provided from the Brightness Control input pin (MM5445 and MM5447).
Functional Description
The MM5445 Series are specifically designed to operate
4 or 5·digit alphanumeric displays with minimal inter·
face with the display and the data source. Character
generation is done external to the MM5445 Series. Serial
data transfer from the data source to the display driver is
accomplished with 2 Signals, serial data and clock. Using
a format of a leading "1" followed by the 35 data bits
allows data transfer without an additional load signal.
The 35 data bits are latched after the 36th bit is complete,
thus providing non·multiplexed, direct drive to the dis·
play. Outputs change only if the serial data bits differ
from the previous time. Display brightness is determined
by control of the positive output voltage level.
Figure 4 shows the input data format. A start bit of logi·
cal "1" precedes the 35 bits of data. At the 36th clock a
LOAD Signal is generated synchronously with the high
state of the clock, which loads the 35 bits of the shift
registers into the latches. At the low state of the clock a
RESET signal is generated which clears all the shift reg·
isters for the next set of data. The shift registers are
static master·slave configuration. There is no clear for
the master portion of the first shift register, thus allowing
continuous operation.
There must be a complete set of 36 clocks or the shift
registers will not clear.
When the chip first powers ON an internal power ON
reset signal is generated which resets all registers and
all latches. The START bit and the first clock return the
chip to its normal operation.
A block diagram is shown in Figure 1.
Figure 2 shows the pin·out of the MM5445 series. Bit 1 is
the first bit following the start bit and it will appear on
pin 18. A logical "1" at the input will turn on the
appropriate VF display segment.
Figure 3 shows the timing relationships between data,
clock and data enable. A maximum clock frequency of
250kHz is assumed.
5-90
Typical Applications
CLOCK~
OATA
----~~
""'OA"'"TA'"'E"'NA""B,-;oLE
MIN
100 ns
MIN
Ir=tl ~ 50ns
Figure 3
1
36
CLOCK~
START BIT 1
BIT 34 BIT 35
CY~$~~$$~,-----
n
LOAO
!lNTERNALI _ _ _ _ _ _ _ _ _ _~~tt---------I
L _ _ __
n'---___
RESET
!INTERNAL) ---------«(~2----------I
Figure 4. Input Data Format
AM
FM
}
Il- -11-1
11:::1 :::1 LI
-
34---1
MM5446
DISPLAY DRIVER
KEYBOARD
COPs
ELECTRONIC TUNING
CONTROLLER
111
STATION
DETECT. ETC.
Basic Electronically Tuned Radio System
5-91
PLL
SYNTHESIZER
.
Semiconductor
~National
a
MM5450, MM5451 LED Display Drivers
General Description
The 5450 and MM5451 are monolithic MaS integrated
circuits utilizing N-channel metal-gate low threshold,
enhancement mode, and ion-implanted depletion mode
devices_ They are available in 40-pin molded dual-in-line
packages_ A single pin controls the LED display brightness by setting a reference current through a variable
resistor connected to VOD -
• Enable (on MM5450)
• Wide power supply operation
• TTL compatibility
• 34 or 35 outputs, 15mA sink capability
• Alphanumeric capability
Applications
• cops or microprocessor displays
Features
• Industrial control indicator
• Continuous brightness control
• Serial data input
• Relay driver
• Digital clock, thermometer, counter, voltmeter
• No load signal required
• Instrumentation readouts
Block Diagram
VOO
BRIGHTNESS
CONTROL
OUTPUT 34
OUTPUT 1
r-"'--=~:----.
24
DATOAU~~~:~~ l~~~:~~:
SEOR~~~
18
....---"""1-...
....----=-1-1
CLOCK ....----'-'i-i
>------'
FIGURE 1
Connection Diagrams (Dual-In-Line Packages)
40
Vss
39
OUTPUT BIT 17
3B
OUTPUT BIT 16
37
OUTPUT BIT 15
36
OUTPUT BIT 14
35
OUTPUT BIT 13
34
OUTPUT B1T 12
33
OUTPUT BIT 11
32
OUTPUT BIT 10
OUTPUT BIT 9
OUTPUT BIT 8
OUTPUT BIT 7
OUTPUT BIT 6
OUTPUT BITS
OUTPUT BIT 4
OUTPUT BIT 3
OUTPUT BIT 2
OUTPUT BIT 1
BRIGHTNESS CONTROL
10
11
31
MM5450
30
12
29
13
28
14
27
15
26
16
17
18
OUTPUT BIT 18
Vss
OUTPUT BIT 19
OUTPUT BIT 17
OUTPUT BIT 20
OUTPUT BIT 16
OUTPUT BIT 21
OUTPUT 81T 15
OUTPUT BIT 22
OUTPUT 81T 14
OUTPUT BIT 23
OUTPUT BIT 13
OUTPUT BIT 24
OUTPUT BIT 12
OUTPUT BIT 25
OUTPUT BIT 11
OUTPUT BIT 26
OUTPUT BIT 10
OUTPUT BIT 27
OUTPUT BIT 9
OUTPUT BIT 8
OUTPUT BIT 28
OUTPUT BIT 29
OUTPUT BIT 7
OUTPUT BIT 30
OUTPUT 81T 6
OUTPUT BIT 31
OUTPUT BIT 5
OUTPUT BIT 32
OUTPUT BIT 4
OUTPUT BIT 33
OUTPUT BIT 3
OUTPUT BIT 34
OUTPUT BIT 2
DATA ENABLE
OUTPUT BIT 1
19
20
21
VOO
BRIGHTNESS CONTROL
DATA IN
CLOCK IN
40
39
38
37
36
35
34
33
32
10
11
31
MM5451
30
12
29
13
28
14
27
15
26
16
25
17
24
18
23
19
22
20
21
VOO
OUTPUT BIT 18
OUTPUT BIT 19
OUTPUT BIT 20
OUTPUT BIT 21
OUTPUT BIT22
OUTPUT BIT 23
OUTPUT BIT 24
OUTPUT BIT 25
OUTPUT BIT 26
OUTPUT BIT 27
OUTPUT BIT 28
OUTPUT BIT 29
OUTPUT BIT 30
OUTPUT BIT 31
OUTPUT BIT 32
OUTPUT BIT 33
OUTPUT BIT 34
OUTPUT BIT 35
DATA IN
CLOCK IN
TOP VIEW
TOP VIEW
Order Number MM5450N, MM5451N
NS Package N40A
Order Number MM5450D, MM5451D
NS Package D40C
FIGURE 2b
FIGURE 2a
5-92
Absolute Maximum Ratings
Voltage at Any Pin
Operating Temperature
Storage Temperature
Power Dissipation
VSS to VSS + 12V
-25° C to +85° C
-65°C to +150°C
560 mW at +85°C
lW at +25°C
+150°C
300°C
Junction Temperature
Lead Temperature (Soldering, 10 seconds)
Electrical Characteristics
T A within operating range, VDD =4.75V to 11.0V,VSS = OV, unless otherwise'specified.
PARAMETER
CONDITIONS
Power Supply
Power Supply Current
MIN
TVP
MAX
4.75
Excluding Output Loads
UNITS
11
V
7
mA
Input Voltages
Logical "0" Level
±10 J.lA Input Bias
Logical "1" Level
4. 75 SVDDS5.25
VDD
-0.3
> 5.25
Brightness Input (Note 2)
0.8
V
2.2
VDD
V
VDD -2
VDD
V
0
G.i'~
"'~
Output Sink Current (Note 3)
= 3.0V
Segment OFF
VOUT
Segment ON
VOUT = lV (Note 4)
Brightness Input
Brightness Input Voltage (Pin 19)
= OIlA
0
10
IlA
10
4
IlA
mA
Brightness Input = 100 IlA
2.0
Brightness Input = 750 IlA
15
25
mA
Input Current = 750 J.lA
3.0
4.3
V
Input Clock Frequency
0
Duty Cycle
40
2.7
0.5
MHz
60
%
±20
%
50
Output MatChing (Note 1)
Note 1: Output matching is calculated as the percent variation from IMAX + IMINJ2.
Note 2. With a fixed reSistor on the ongntness Input pin tiOIJl~ VdrldliVl1 III Utlyll\llt;;~;:, "~III ... " ......... '
~
~
.:.:~~.:.
Note 3: Absolute maximum for each output should be limited to 40mA.
Note 4: The VOUT voltage should be regulated by the user. See Figures 6 and 7 for allowable VOUT vs. lOUT operation.
I ...... '"
..... , ......
..... _
••
......
_ ••
..
Functional Description
Figure 4 shows the input data format. A start bit of
logical "1" precedes the 35 bits of data. At the 36th
clock a LOAD signal is generated synchronously with
the high state of the clock, which loads the 35 bits of
the shift registers into the latches. At the low state of
the clock a RESET signal is generated which clears all
the shift registers for the next set of data. The shift
registers are static master-slave configuration. There
is no clear for the master portion of the first shift
register, thus allowing continuous operation.
Both the MM5450 and the MM5451 are specifically
designed to operate 4 or 5-digit alphanumeric displays
with minimal interface with the display and the data
source. Serial data transfer from the data source to the
display driver is accomplished with 2 signals, serial
data and clock. Using a format of a leading "1" followed by the 35 data bits allows data transfer without
an additional load signal. The 35 data bits are latched
after the 36th bit is complete, thus providing nonmultiplexed, direct drive to the display. Outputs change
only if the serial data bits differ from the previous
time. Display brightness is determined by control
of the output current for LED displays. A 0.001 capacitor should be connected to brightness control, pin
19, to prevent possible oscillations.
There must be a complete set of 36 clocks or the shift
registers will not clear.
When the chip first powers ON an internal power ON
reset signal is generated which resets all registers and all
latches. The START bit and the first clock return the
chip to its normal operation.
A block diagram is shown in Figure 1. For the MM5450
a DATA ENABLE is used instead of the 35th output.
The DATA ENABLE input is a metal option for the
MM5450. The output current is typically 20 times
greater than the current into pin 19, which is set by
an external variable resistor. There is an internal limiting
resistor of 400n nominal value.
Figure 2 shows the pin-out of the MM5450 and MM5451.
Bit 1 is the first bit following the start bit and it will
appear on pin 18. A logical "1" at the input will turn
on the appropriate LED.
5-93
Functional Description
(Continued)
Figure 3 shows the timing relationships between data,
clock and data enable. A max clock frequency of 0.5
MHz is assumed.
where:
Tj ~ junction temperature +150°C max
VOUT ~ the voltage at the LED driver outputs
I LED
For applications where a lesser number of outputs are
used, it is possible to either increase the current per
output, or operate the part at higher than 1 V VOUT.
The following equation can be used for calculations.
~
the LED current
124°C/W ~ thermal coefficient of the package
TA
~
ambient temperature
The above equation was used to plot Figure 5, Figure 6,
and Figure 7.
FIGURE 3
36
CLOCK
n
n
LOAO _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _.....
(lNTERNALI
..._ _ _ __
R~" _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _..l
(INTERNAL)
FIGURE 4. Input Data Format
5-94
1._ _ __
Typical Applications
1.0
~
0.8
"i=
0.6
is
0.4
Q
:;:
ill
0:
~
~
0.2
20
40
60
80
100
TEMPERATURE (CI
FIGURE 5
2.5
2.0
-=
~
~
>
1.5
1.0
1I I [U1\\ 1\\'I I
\1\
TA"85'C
T," 150'C (MAXI
'"
-~~
'%.
9'~
~
,>;
I
110
100
J
~
~u
.E
80
r--
~
5
...."'~":4,
~
0.5
1
70
_
60
50
!;
40
~
3D
1,1
I
,,
r-Tl ~OUT: IV
20
16
20
24
28
>.- I I
l\ I'- VOUT" 2V -I - I\!.(
'\:
-
I'...: ...... .........
-.
10
FIGURE 6
15
20
25
FIGURE 7
Basic Electronically Tuned Radio System
LED DISPLAY
AM
FM
Il- -11-1
11:::1 :::1 LI
.} -34--3
MM5450
DISPLAY
DRIVER
COPs
ELECTRONIC
TUNING
CONTROLLER
111
STATION
OETECT, ETC.
5-95.
I
I
NUMBE R OF SEGMENTS
'LED (mAl
KEYBOARD
I
TA ",85°C
VOUT"1.5~_
10
12
H
PLL
SYNTHESIZER
30
34
~
Typical Applications
(Continued)
:!
:!
g
~
:!
:e
Duplexing 8 Digits with One MM5450
MM5450
CLOCK IN ~-----I
OATAIN ......._ _ _ _--J
BRIGHTNESS
CONTROL
lOOK
TYP.
5-96
~National
a
Semiconductor
MM5452, MM5453 Liquid Crystal Display Drivers
General Description
The MM5452 is a monolithic integrated circuit utilizing
CMOS metal gate, low threshold enhancement mode
devices. It is available in a 40-pin molded package. The chip
can drive up to 32 segments of LCD and can be paralleled to
increase this number. The chip is capable of driving a
4 112-digit 7-segment display with minimal interface between the display and the data source.
The MM5452 stores the display data in latches after it is
clocked in, and holds the data until new display data is
received.
• DATA ENABLE (MM5452)
• Wide power supply operation
• TIL compatibility
• 32 or 33 outputs
• Alphanumeric and bar graph capability
• Cascaded operation capability
Applications
• COPs or 'microprocessor displays
. -_ _ .1. ____ _
• Industrial control indicator
rca lUI C;:,
• Digital clock, thermometer, counter, voltmeter
• Serial data input
• Instrumentation readouts
• No load signal required
• Remote displays
Block and Connection Diagrams
OUTPUT 33
(MM545J)
LOAD
------+--------.
DATA ENABLE (MM5452l ......
SERIAL
DATA
~-------""-'I_-----i ,.~-------{2I~~~$~
CLOCK
~----.-:':.:.'I_-------i
>---------'
FIGURE 1
Dual-In-Line Package
Vss
39
OUTPUT BIT 17
3B
OUTPUT BIT 16
37
OUTPUT BIT 15
36
OUTPUT BIT 14
35
OUTPUT BIT 13
34
OUTPUT BIT 12
33
OUTPUT BIT 11
32
OUTPUT BIT 10
OUTPUT BIT 9
OUTPUT BIT 8
OUTPUT BIT 7
OUTPUT BIT 6
OUTPUT BIT 5
OUTPUT BIT 4
OUTPUT BIT 3
OUTPUT BIT 2
OUTPUT BIT 1
OSC IN
Dual-In-Line Package
40
10
11
31
MM5452
30
12
29
13
2B
14
27
15
26
16
25
17
24
18
23
19
22
20
21
VOD
OUTPUT BIT lB
vss
OUTPUT BIT 19
OUTPUT BIT 17
OUTPUT BIT 20
OUTPUT BIT 16
OUTPUT BIT 21
OUTPUT BIT 15
OUTPUT BIT 22
OUTPUT BIT 14
OUTPUT BIT 23
OUTPUT BIT 13
40
39
3B
37
36
35
34
OUTPUT BIT 12
OUTPUT BIT 24
OUTPUT BIT 25
OUTPUT BIT 11
OUTPUT BIT 26
OUTPUT BIT 10
OUTPUT BIT 27
OUTPUT BIT 9
OUTPUT BIT 8
OUTPUT BIT 2B
OUTPUT BIT 7
OUTPUT BIT 29
OUTPUT BIT 30
OUTPUT BIT 6
OUTPUT BIT 5
OUTPUT BIT 31
OUTPUT BIT 32
OUTPUT BIT 4
DATA ENABLE
OUTPUT BIT 3
BACKPLANE IN
OUTPUT BIT 2
BACKPLANE OUT
OUTPUT BIT 1
OATA IN
OSC IN
CLOCK IN
JJ
32
10
11
31
MM5453
12
29
13
2B
14
27
15
26
16
25
17
24
18
23
19
22
20
21
VOO
TOP VIEW
TOP VIEW
FIGURE 2a
FIGURE 2b
Order Number MM5452N, MM5453N
NS Package N40A
5-97
30
OUTPUT BIT 18
OUTPUT BIT 19
OUTPUT BIT 20
OUTPUT BIT 21
OUTPUT BIT 22
OUTPUT BIT 23
OUTPUT BIT 24
OUTPUT BIT 25
OUTPUT BIT 26
OUTPUT BIT 27
OUTPUT BIT 28
OUTPUT BIT 29
OUTPUT BIT 30
OUTPUT BIT 31
OUTPUT BIT 32
OUTPUT BIT 33
BACKPLANE IN
BACKPLANE OUT
DATA IN
CLOCK IN
Absolute Maximum Ratings
Voltage at Any Pin
Operating Temperature
Storage Temperature
Vss to Vss + 10V
-40°C to +85°C'
Power Dissipation
300 mW at + 85'C
350 mW at +25'C
Junction Temperature
+ 150'C
Lead Temperature (Soldering, 10 seconds)
300'C
- 65' to + 150'C
Electrical Characteristics
TA within operating range, Voo = 3.0V to 10V, Vss = OV, unless otherwise specified.
Parameter
Min
Conditions
Power Supply
Typ
Max
3
Power Supply Current
Units
10
V
40
10
p.A
p.A
500
kHz
0.1 Voo
0.8
V
V
Voo
Voo
V
V
-20
p.A
Excluding Outputs
OSC = Vss , BP IN @ 32 Hz
V DO = 5V, Open Outputs, No Clock
Clock Frequency
Input Voltages
Logical '0' Level
V oo <4.75
Logical '1' Level
Voo~4.75
-0.3
-0.3
V oo >5.25
V oo :S5.25
0.9 Voo
2.0
Output Current Levels
Segments
Sink
V oo =3V, V ouT =0.3V
Source
V oo =3V, VOUT = Voo - 0.3V
p.A
20
Backplane
Sink
Voo = 3V, VOUT= Voo - 0.3V
Output Offset Voltage
p.A
-320
V oo =3V, VouT =0.3V
Source
p.A
320
Segment Load 250 pF
Backplane Load 8750 pF
mV
±50
Functional Description (Continued)
Figure 4 shows the input data format. A start bit of logical
"1" precedes the 32 bits of data. At the 36th clock a LOAD
Signal is generated synchronously with the high state of
the clock, which loads the 32 bits cif the shift registers into
the latches. At the low state of the clock a RESET signal is
generated which clears all the shift registers for the next
set of data. The shift registers are static master-slave configuration. There is no clear for the master portion of the
first shift register, thus allowing continuous operation.
The MM5452 is specifically designed to operate 4 1/2·digit,
7-segment displays with minimal interface with thedisplay
and the data source. Serial data transfer from the data
source to the display driver is accomplished with 2 signals,
serial data and clock. Since the MM5452does not contain a
character generator, the formatting of the segment information must be done prior to inputting the data to the
MM5452. Using a format of a leading "1" followed by the 32
data bits allows data transfer without an additional load
signal. The 32 data bits are latched after the 36th clock is
complete, thus providing non-multiplexed, direct drive to
the display. Outputs change only ilthe serial data bitsdiffer
from the previous tim.e.
If the clock is not continuous, there must bea complete set
of 36 clocks otherwise the shift registers will not clear.
Figure 2a shows the pin-out of the MM5452. Bit 1 is the first
bit following the start bit and it will appear on pin 18.
A block diagram is shown in Figure 1. For the MM5452 a
DATA ENABLE is used instead of the 33rd output If the
DATA ENABLE Signal is not required, the33rdoutputcan be
brought out. This is the MM5453 device.
Figure 3 shows the timing relationships between data,
clock and DATA ENABLE.
CLOCK~
DATA
"'DA"'T'"A~EN~A~B~LE
----_-..JI~-+_-3--00-lIs\
MIN
--II-lOOns
MIN
TIME ,.----
n
LOAD _ _ _ _ _ _ _ _ _ _11-1_ _ _ _ _ _ _...1
(INTERNAL)
L._ _ _ __
-------.....1n
RESET
(INTERNAL) _ _ _ _ _ _ _ _ _ _"1__
--TIME
FIGURE 4. Input Data Format
FIGURE 3
5-98
L._ _ __
Functional Description (Continued)
Figure 5 shows a typical application. Note how the input
data maps to the output pins and the display. The MM5452
and MM5453 do not have format restrictions, as all outputs
are controllable. This application assumes a specific
display pinout. Different display/driver connection pat·
terns will, of course, yield a different input data format.
5egmen t Identification
l~/b
~r
d
_1
BP GI Fl
1
AI
I
Bl G2 F2 A2 B2 G3 F3 A3 B3 G4 F4 A4
I l-I l-I l-I l-:"I
I./~/./~/./~./~
1~~~~~~~~~~ro~~H~~~
~
I!
-'~
i......-
I
L---
'"'""""-
'"'""""L---
-
'---
'--':'
Vss
IB
17
19
16
20
15
21
----;
?-r~
24
13
12
lI
1
11
25
10
26
9
21
I I I
2B
I I
I
~
B
I
1
29
6
3D
5
31
IM"...!-
T
410pF
MM5453
4
32
3
BACKPLANE OUT
2
BACKPLANE IN
1
33
OSC IN
DATA IN
VOO
r-=
~OCKIN
T
v+
DATA FORMAT
TlME-LEFT END
DECIMAL
POINT
3RD
DECIMAL
POINT
2ND
DECIMAL
POINT
4TH
DECIMAL
POINT
j
I
NULLS
I
Consult LCD manufacturer's data sheet for specific pinouts
FIGURE 5. Typical 4V.·Digit Display Application
5-99
Functional Description
(Continued)
Figure 8 shows a four wire remote display that takes advan·
tage of the device's serial input to move many bits of
display information on a few wires.
Using an External Clock
Deviations from a50% duty cycle result in an offset voltage
on the LCD. In Figure 7, a flipflopis usedtoassurea50% duo
ty cycle. The oscillator input is grounded to prevent oscilla·
tion and reduce current consumption in the chips. The
oscillator is not used.
The MM5452, MM5453 LCD Drivers can be used with an ex·
ternally supplied clock, provided it has a duty cycle of 50%.
DISPLAY
BACKPLANE
T
BP
OSC OUT
IN
BP
IN
C'
L . - -......
OSC
IN
.. The minimum recommended value for R for the oscillator input is 9 kn. An RC time constant of approximately
4.91 x 10 - 4 should produce a backplane frequency between 30 Hz and 150' Hz.
FIGURE 6. Parallel Backplane Outputs
DISPLAY
BACKPLANE
BP
OUT
BP
IN
50% DUTY CYCLE
2 X BACKPLANE
DRIVE FREDUENCY
~-+.....
CK
FIGURE 7. External Backplane Clock
5-100
Functional Description
(Continued)
Using an external clock allows synchronizing the display
drive with AC power, internal clocks, or DVM integration
time to reduce interference from the display.
The next clock pulse increments the staircase and clocks
the new data in.
With a buffer amplifier, the same staircase waveform can
be used for many displays. The digital-to-analog can·
verter need not be linear; logarithmic or other non·linear
functions can be displayed by using weighted resistors
or special DACs. This system can be used for status in·
dicators, spectrum analyzers, audio level and power
meters, tuning indicators, and other applications.
Figure 9 is a general block diagram that shows how the
device's serial input can be used to advantage in an
analog display. The analog voltage input is compared
with a staircase voltage generated by a counter and a
digital·to·analog converter or resistor array. The result of
this comparison is clocked into the MM5452, MM5453.
OISPLAY
l-' ,-,
l-Ili
l-I
,-,
,-,
,-,
'-'.'-'.'-'.'-'
l
11 n
BACKPLANE
~
OATA
OATA IN
Voo
BP OUT
VSS
OSC IN
BP IN
BYPASS-~
CAPACITOR -
....
CLOCK
CLOCK IN
t
V-
R
_ ..... C
-,-
FIGURE 8. Four Wire Remote Display
LCO BAR GRAPH DISPLAY
11111000000
ANALOG VOLTAGE IN
BACKPLANE
COUNT
CLOCK
CLOCK
LOW TO SET
START BIT
OSC
IN
~. """
r-I---""
~START
BIT
Data is high until staircase>input
FIGURE 9. Analog Display
5-101
~-----------------------
~National
~ Semiconductor
MM5480 LED Display Driver
General Description
The 5480 is a monolithic MaS integrated circuit utilizing
N·channel metal gate low threshold, enhancement mode
and ion·implanted depletion mode devices. It utilizes
the MM5451 die packaged in a 28'pin package making it
ideal for a 3% digit display. A single pin controls the
LED display brightness by selting a reference current
through a variable resistor connected either to VDD or to
a separate supply of 11V maximum.
• Wide power supply operation
• TTL compatibility
• Alphanumeric capability
• 3% digit displays
Applications
• cops or microprocessor displays
Features
• Industrial control indicator
• Continuous brightness control
• Relay driver
• Digital clock, thermometer, counter, voltmeter
II Instrumentation readouts
• Seri al data input
• No load signal required
Block Diagram
Voo
OUTPUT 23
OUTPUT 1
--::--::::::-=---...
BRIGHTNESS ,.......
CONTROL
Figure 1
Connection Diagram
(Dual·ln·Line Packages)
Vss
28
OUTPUT BIT 11
OUTPUT BIT 10
OUTPUT BIT 9
OUTPUT BIT 8
OUTPUT BIT 7
OUTPUT BIT 6
OUTPUT BIT 5
OUTPUT BIT 4
OUTPUT 81T 3
OUTPUT BIT 2
OUTPUT BIT 1
BRIGHT. CONT.
Voo
OUTPUT BIT 12
OUTPUT BIT 13
OUTPUT BIT 14
OUTPUT BIT 15
OUTPUT BIT 16
OUTPUT BIT 17
OUTPUT BIT 18
OUTPUT BIT 19
OUTPUT BIT 20
OUTPUT BIT 21
OUTPUT BIT 22
OUTPUT BIT 23
DATA IN
CLOCK
Order Number MM5480N
NS Package N28A
Figure 2
5-102
Absolute Maximum Ratings
Voltage at Any Pin
Operating Temperature
Storage Temperature
Power Dissipation
Junction Temperature
Lead Temperature (Soldering, 10 seconds)
Electrical Characteristics
Parameter
Vss to Vss + 12V
-25·Cto +85·C
-65·Cto +150·C
490mWat +85·C
940mWat +25·C
+150·C
300·C
TA within operating range, Voo = 4.75 to 11.0V, Vss = OV, unless otherwise specified.
Conditions
Min.
Power Supply
Power Supply Current
Input Voltages
Logical "0" Level
Logical "1" Level
4.75
Excluding Output Loads
±10jiA Input Bias
4.75 ~ Voo ~ 5.25
Voo> 5.25
Max.
Units
11.0
V
mA
7.0
-q.3
2.2
Voo-2
0
Brightness Input (Note 2)
Output Sink Current (Note 3)
begmen! UI-ISegment ON
Typ.
vour=~·uv
0.8
Voo
Voo
0.75
V
V
V
mA
lU.U
f'A
10.0
4.0
25.0
f'A.
mA
mA
40.0
mA
Your = 1V (Note 4)
Brightness Input =Of'A
Brightness Input = 1OOf'A
Brightness Input = 750f'A
0
2.0
15.0
Input Current = 750 f'A
3.0
4.3
V
Input Clock Frequency
0
0.5
MHz
Duty Cycle
Output Matching (Note 1)
40
60
%
±20
%
2.7
Maximum Segment Current
Brightness Input Voltage (Pin 13)
Nole 1:
Nole 2:
Nole 3:
Nole 3:
Nole 4:
50
Output matching is calculated as the percent variation from IMAX + IMINI2.
With a fixed resistor on the brightness input pin some variation in brightness will occur from one device to another.
Absolute maximum for each output should be limited to 40rilA
rhe Your voltage should be regulated by the user.
The Your voltage should be. regulated by the user.
Functional Description
isters for the next set of data. The shift registers are
static master-slave configuration. There is no clear for
the master portion of the first shift register, thus allowing continuous operation.·
.
The MM5480 is specifically designed to operate 31f2-digit
alphanumeric displays with minimal interface with the
display and the data source. Serial data transfer from
the data source to the display driver is accomplished
with 2 signals, serial data and clock. Using a format of a
leading "1" followed by the 35 data bits allows data
transfer without an additional load signal. The 35 data
bits are latched after the 36th bit is complete, thus providing non-multiplexed, direct drive to the display. Outputs change only if the serial data bits differ from the
previous time. Display brightness is determined by control of the output current for LED displays. A 0.001 capacitor should be connected to brightness control, pin 13,
to prevent possible oscillations.
There must be a complete set of 36 clocks or the shift
registers will not clear.
When the chip first powers ON an internal power ON
reset signal is generated which resets all registers and
all latches. The START bit and the first clock return the
chip to its normal operation.
Figure 5 shows the Output Data Format for the 5480.
Because it uses only 23 of the possible 35 outputs, 12 of
the bits are 'Don't Cares'.
A block diagram is shown in Figure 1. The output current
is typically 20 times greater than the current into pin 13,
which is set by an external variable resistor. There is an
internal limiting resistor of 400Q nominal value.
Figure 3 shows the timing relationships between data,
clock, and data enable. A maximum clock frequency of
0.5MHz is assumed.
For applications where a lesser number of outputs are
used, it is possible to either increase the current per
output, or operate the part at higher than 1V Your. The
following equation can be used for calculations.
Figure 4 shows the input data format. A start bit of logical "1" precedes the 35 bits of data. At the 36th clock a
LOAD signal is generated synchronously with the high
state of the clock, which loads the 35 bits of the shift
registers into the latches. At the low state of the clock a
RESET signal Is generated which clears all the shift reg-
TJ = (Vour) (ilE[i) (No. of segments) (132·C/W)+ TA
5-103
Functional Description
(Continued)
where:
Tj =junction temperature + 150·C max.
VOUT = the voltage at the LED driver outputs
ILED = the LED current
132 ·C/W = thermal coefficient of the package
TA = ambient temperature
Figure 3
36
LOAD
(INTERNAL)
-----------(2;21-..-------....
RESET
(INTERNAL)
- - - - - - - - - - - r U ; ) - - - - - - - - -.....
Figure 4. Input Data Format
Figure 5. Output Data Format
CLOCK
DATA
Basic 3 Y2 Digit Interface
5-104
~National
a
Semiconductor
MM5481 LED Display Driver
General Description
The 5481 is a monolithic MaS integrated circuit utilizing
N-channel metal gate low threshold, enhancement mode
and ion-implanted depletion mode devices_ It utilizes
the MM5450 die packaged in a 20-pin package making it
ideal for a 2 digit display_ A single pin controls the LED
display brightness by setting a reference current through
a variable resistor connected either to VDD or to a separate supply of 11 V maximum_
• Wide power supply operation
Features
Applications
• Continuous brightness control
• COPS or microprocessor displays
• Industrial control indicator
• Serial data input
• No load signal required
• TTL compatibility
• Alphanumeric capability
• 2 digit LED driver
• Relay driver
• Instrumentation readouts
• Data enable
Block Diagram
OUTPUT 14
VDD
OUTPUT 1
BRIGHTNESS
CONTROL
CLOCK ---'+-1>------"
-::-
Figure 1
Connection Diagram
(Dual-In-Line Package)
OUTPUT BIT B
OUTPUT BI17
OUTPUT BIT6
OUTPUT BIT5
OUTPUT BI14
OUTPUT BIT 3
OUTPUT BIT2
OUTPUT BIT 1
BRIGHT CONTR.
VOD
5481
10
20
19
1B
17
16
15
14
13
12
11
OUTPUT BIT 9
OUTPUTBIT 10
OUTPUT BIT 11
OUTPUT BIT 12
OUTPUT BIT 13
Vss
OUTPUT BIT 14
DATA ENABLE
DATA IN
CLOCK
Top View
Order Number MM5481N
NS Package N20A
Figure 2
5-105
Absolute Maximum Ratings
Voltage at Any Pin
Operating Temperature
Storage Temperature
Power Dissipation
Junction Temperature
Lead Temperature (Soldering, '10 seconds)
Electrical Characteristics
Parameter
Vss to Vss + 12V
-25'Cto +85'C
-65'Cto +150'C
450mWat +85'C
860mWat +25'C
+150'C
300'C
TA within operating range, Voo = 4]5 to 11.0V, Vss = OV, unless otherwise specified.
Conditions
Min.
Power Supply
Power Supply Current
Input Voltages
Logical "0" Level
Logical "1" Level
Excluding Output Loads
-0.3
2.2
Voo-2
0
±10~A Input Bias
4.75 '" Voo'" 5.25
Voo > 5.25
Brightness Input (Note 2)
Output Sink Current (Note 3)
Segment OFF
Segment ON
Typ.
4.75
VouT=3.0V
VOUT = 1V (Note 4)
Max.
Units
11
V
7
mA
0.8
Voo
Voo
0.75
V
V
V
mA
10
~A
10
4.0
25
mA
mA
~A
Brightness Input = 0 ~A
Brightness Input = 100 ~A
Brightness Input = 750 ~A
0
2.0
15
40
mA
input Current = 750~A
3.0
4.3
Input Clock Frequency
0
0.5
V
MHz
Duty Cycle
40
60
±20
%
%
2.7
Maximum Segment Current
Brightness Input Voltage (Pin 9)
Output Matching (Note 1)
50
Note 1: Output matching is calculated as the percent vanatiun frum IMAX + IMINI2.
Note 2: With a fixed resistur un the brightness inpul pin sume variation in brightness will uccur frulll une device » an,.dler.
Note 3: Absulute maximum for each output should be limited tu 40 mA
Note 4: The
VOUT vultage should be regulated by the user.
Functional Description
registers into the latches. At the low state of the clock a
RESET signal is generated which clears all the shift reg·
isters for the next set of data. The shift registers are
static master·slave configuration. There is no clear for
the master portion of the firsi shift register, thus allowing continuous operation.
The MM5481 uses the 5450 die which is packaged to
operate 2-digit alphanumeric displays with minimal in·
terface with the display and the data source. Serial data
transfer from the data source to the display driver is ac·
complished with 2 signals, serial data and clock. Using
a format of a leading "1" followed by the 35 data bits
allows data transfer without an additional load signal.
The 35 data bits are latched after the 36th bit is complete,
thus providing non-multiplexed, direct drive to the dis·
play. Outputs change only if the serial data bits differ
from the previous time. Display brightness is determined
by control of the output current for LED displays. A 0.001
capacitor should be connected to brightness control, pin
9, to prevent possible oscillations.
There must be a complete set of 36 clocks or the shift
registers will not clear.
When the chip first powers ON an internal power ON
reset signal is generated which resets all registers and
all latches. The START bit and the first clock return the
chip to its normal operation.
Figure 5 shows the Output Data Format for the 5481.
Because it uses only 14 of the possible 34 outputs, 20 of
the bits are 'Don't Cares'. Note that only alternate groups
of 4 outputs are used.
A block diagram is shown in Figure 1. The output current
is typically 20 times greater than the current into pin 9,
which is set by an external variable resistor. There is an
internal limiting resistor of 400Q nominal value.
Figure 3 shows the timing relationships between data,
clock, and data enable. A maximum clock frequency of
0.5 MHz is assumed.
Figure 4 shows the input data format. A start bit of logical "1" precedes the 35 bits of data. At the 36th clock a
LOAD signal is generated synchronously with the high
state of th~ clock, which loads the 35 bits of the shift
L - '_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ • • _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ . , - _ _ _ _ • • _ _ _ _
5-106
..J
Functional Description
(Continued)
For applications where a lesser number of outputs are
used, it is possible to either increase the current per
output, or operate the part at higher than 1V VOUT. The
following equation can be used for calculations.
CLOCK
Ti = (VOUT) (lLED) (No. of segments) (145 'C/W) + TA
OATA
where:
%1, . . - - 1 0 - 0 - n ' - - - - MIN
Tj = junction temperature + 150 'C max.
VOUT = the voltage at the LED driver outputs
ILED = the LED current
145'C/W=thermal coefficient of the package
TA = ambient temperature
~
---------'1
OA~ENABLE
'\~_________________
Figure 3
n
--(((&--_ _ _ _ _ _ _ _--'n'-_ _ __
(INTERNAL) -----------~(2,t---------..I
RESET _ _ _ _ _ _ _ _ _ _
(INTERNAL)
Figure 4. Input Data Format
Figure 5. Output Data Format
Basic Electronically Tuned Television System
5-107
L -_ _ __
~National
~ Semiconductor
MM5484,MM5485 16-, 11-Segment LED Display Drivers
General Description
The MM5484, MM5485 are low threshold N-channel
metal gate circuits using low thieshold enhancement
and ion implanted depletion devices. the MM5484 is
available in a 22-pin molded package and is capable of
driving 16 LED segments while the MM5485 is available
in a 16-pin molded package and is capable of driving 11
LED segment outputs.
• TTL compatibility
• No load signal required
• Non multiplex display
• 2% digit capability-MM5484
1V2 digit capability-MM5485
Features
Applications
• Serial data input
• Wide power supply operation
• COPSTM or microprocessor displays
• 16 or 11 output~, 15mA sink capability
• Industrial control indicator
• MM5484 is cascadeable
• Relay driver
• Instrumentation readouts
COPS is a trademark of National Semiconductor Corp.
Block Diagrams
16 SEGMENT OUTPUTS
ENABlE
0--+-----1
ENABLE
DATA
OUT
CLOCK
DATA IN
11 SEGMENT OUTPUTS
0--t------1
CLOCK_--....._
0--------1
OATA IN 0 - - - - - - - - '
Figure 1. MM5484
Figure 2. MM5485
Connection Diagrams (Top Views)
013
22
012
014
21
011
015
20
010
016
19
09
DATA OUT
18
ENABLE
17
CLOCK IN
16
VSS
MM5484
VOO
DATA IN
• 7
01
02
9
15
08
14
07
03
10
13
06
04
11
12
05
Order Number MM5484N
NS Package Number N22A
05
16
06
15
03
07
14
02
VSS
4 MMS4BS 13
12
5
01
CLOCK IN
ENABLE
11
Voo
DB
10
011
09
9
010
04
OATA IN
Order Number MM5485N
NS Package Number N16A
Figure 4.
5-108
Absolute Maximum Ratings
Voltage at LED outputs
Vss -0.5Vto Vss +12V
Voltage at other pins
Vss -0.5 V to Vss +10 V
Operating Temperature
-40°C to 85°C
Storage Temperature
-40°C to 150°C
Lead Temperature (Soldering, 10 seconds)
300°C
Maximum Power Dissipation
MM5484
500mW
400mW
MM5485
DC Electrical Characteristics
Parameter
VOD = 4.5 to 9V, TA = -40°C to 85°C unless otherwise specified
Conditions
Supply Voltage
Supply Current
Logic One
Input High Level V1H
Logic Zero
Input Low Level V1L
Input Current
Input Capacitance
Outputs
Data Output Voltage
High Level VOH
Low Level VOL
Segment Off (logic zero on
input)
Output Current
Segment On (logic one on
input)
Output Voltage
Typ.
Max.
Units
5
9
10
V
mA
2.4
VD~+0.5
V
0
0.8
V
~
pF
Min.
4.5
High or Low Level
±l
7.5
(Only for MM5484)
IOUT=0.1 mA
lOUT = - 0.1 mA
VOUT = 12V
REXT =400 Q
VDo -0.5
0.5
IOUT= 15mA
VDo ;;,6V
V
V
0.5
50
f1A
1.0
V
Nole 1: Under no condition should the power dissipated by the segment driver exceed 50mW nor the entire chip power dissipation
exceed 500mW for the MM5484 and 400mW for the MM5485.
A\,; I:.leClnCal \,;naraClenSliCS (See Figure 3.) VDD = 4.5 to 9V, TA = -40·C to 85 u C unless otherwise SpeCITIea
Symbol
tS1
tH1
tS2
tH2
tpd
Parameter
Conditions
Clock Frequency
Data Setup Time
Data Hold Time
Enable Setup Time
Enable Hold Time
Clock Rise Time
Data Out Delay
Clock Period t( = 1/f)
Min.
Typ.
Max.
Units
1
MHz
JJs
JJs
JJs
JJs
JJs
JJs
JJs
0.5
0.5
0.5
0.5
0.5
0.5
2
5-109
Functional Description
The MM5484 and MM5485 are designed to drive LED dis·
plays directly. Serial data transfer from the data source
to the display driver is accomplished with 3 signals,
DATA IN, CLOCK and ENABLE. The signal ENABLE acts
as an envelope and only while this signal is at a logic '1'
do the circuits recognize the clock signal.
For the MM5484, data is output from the serial DATA
OUT pin on the falling edge of clock so cascading is
made'simple with race hazards eliminated.
The MM5485 is essentially a metal mask option of the
MM5484 where only 11 segments are used. However, the
MM5485 contains a 12·blt shift register and so when
entering new data to this device 12 ciock puises should
be input with the data in a 'don't care' state for the 12th
clock pulse. See Figure 2.
While ENABLE is high, data on the serial data input is
transferred and shifted in the internal shift register on
the rising clock edge, i.e. a logic '0' to logic '1' transition.
When the chip first powers on, an internal power on
reset signal is generated which resets the SR and
latches to zero so that the display will be off.
When the ENABLE signal goes to a low (logic zero state),
the contents of the shift register is latched and the dis·
play will show the new data. While new data is being
loaded into the SR the display will continue to show the
old data.
Timing Diagram
CLOCK
ENABLE
DATA IN
-l
,
DATA OUT
t;=IPd
"
Figure 3.
5-110
\
~National
~ Semiconductor
MM58201 Multiplexed LCD Driver
General Description
Features
The MM58201 is a monolithic CMOS LCD driver capable of
driving up to 8 backplanes and 24 segments. A 192·bit
RAM stores the data for the display:Serial input and out·
put pins are provided to interface with a controller. An RC
oscillator generates the timing necessary to refresh the
display. The magnitude of the driving waveforms can be
adjusted with the VTC input to optimize display contrast.
Four additional bits of RAM allow the user to program the
number of backplanes being driven, and to designate the
driver as either a master or slave for cascading purposes.
When two or more drivers are cascaded, the master chip
drives the backplane lines, and the master and each slave
chip drive 24 segment lines. Synchronizing the cascaded
drivers is accomplished by tying the RC OSC pins together
• Drives up to 8 backplanes and 24 segment lines
• Stores data for display
• Cascadable
• Low power
• Fully static operation
Applications
• Dot matrix LCD driver
• Multiplexed 7·segment LCD driver
• Serial in/serial out memory
The MM58201 is packaged in a 40·lead dual-in·line
package.
Block Diagram
Connection Diagram
BACKPlANE
OUTPUTS
Dual·ln-Line Package
511
39
S10
3B
S9
37
SB
36
S7
35
56
J.
S5
33
S4
32
S3
RC
OSC
S2
Sl
10
31
11
30
29
BPB
2B
BP7
27
BP6
26
BP5
SEGMENT
WAVEFORM
LOGIC
25
BP4
BP3
BP2
BP1
24
1B
23
19
22
20
21
VSS
SEGMENT
OUTPUTS
TOP VIEW
Order Number MM58201N
NS Package N24A
FIGURE 2
cs
elK IN
DATA
IN
DATA
OUT
FIGURE 1
5-111
VOO
S12
S13
S14
S15
~lh
S17
S18
S19
S20
S21
S22
S23
S24
VTC
cs
CLK IN
OATA IN
DATA OUT
RC OSC
Absolute Maximum Ratings
Voltage at Any Pin
Operating Temperature Range
Storage Temperature Range
Package Dissipation
Operating Voo Range
Lead Temperature(Soldering, 10 seconds)
Vss - 0.3V to Vss + 18V
O°C to 70°C
-65°C to + 150°C
500mW
Vss + 7.0V to Vss + 18.0V
300°C
DC Electrical Characteristics Minimax limits apply across temperature range unless otherwise noted.
Parameter
Icc
Quiescent Supply Current
Conditions
Typ
Min
Max
Units
0.3
mA
VIN(1)
Logical "1" Input Voltage
0.45 Voo
Voo+0.3
V
VIN(O)
Logical "0" Input Voltage
Vss -' 0.3
1.0
V
VOUT(O)
Logical "0" Output Voltage
ISINK = 0.6 mA
0.4
V
IOUT(1)
Logical "1" Output Leakage
Current
VOUT=Voo
0
±10
p.A
IIN(1)
Logical "1" Input Leakage
Current
VIN =Voo
0
1.0
p.A
IIN(O)
Logical "0" Input Leakage
Current
VIN =Vss
-1.0
0
p.A
VTC
Input Voltage
4.5
Voo+0.3
V
VTC
Input Impedance
10
30
kn
ZOUT
Output Impedance
Backplane and Segment
Outputs
10
kn
DC Offset Voltage
Between Any Backplane
and Segment Output
±10
mV
0
AC Electrical Characteristics TA and V DO within operating range unless otherwise noted.
Parameter
Min
Conditions
Typ
Max
Units
losc
Oscillator Frequency'
1281)
4001)
Hz
IClKIN
Clock Frequency
DC
100
kHz
tON
Clock Pulse Width
5.0
p's
tOFF
Clock OFF Time
5.0
P.s
ts
Input Data Set·Up Time
2.0
p's
tH
Input Data Hold Time
1.0
P.s
tAcc
Access Time
tr
Rise Time
Backplane, Segment Outputs
Cl= 2000 pF
60
I'S
tf
Fall Time
Backplane, Segment Outputs
C l =2000 pF
60
I'S
5.0
* IJ is the number of backplanes programmed.
..
5-112
P.s
Switching Time Waveforms
i-----tON---.,..-j
CLK IN
OATA IN,
CS
OATA OUT
VALID
VALID
Segment Output
Backplane Output
O.B8VTC
~II~
_~
.
O.32VTC - -
Functional Description
A block diagram of the MM58201 LCD driver is shown in
Figure 1, A connection diagram is shown in Figure 2,
within that time interval. The formula below can be used to
estimate the minimum clock rate:
fCLK IN = (300 + 7 ts)/tLCD
Serial Inputs and Output
,A.
:--::;:.!:'::
~:::-:~
==;:: ::":
~~: C'~
:...... , ...
i ... l+i ... +"" .......
where ts is the processor's set-up time between each read
fr ... .,.,~
.....• -
l_ ...... _ _ l_:_ .. _
....... _ ......................... ..... 1-,
.... , ........ ... J ........ , ........... LvU· .................... _ .... _ ... _ .. -- -_ ..
The CS input must then stay low for at least one rising
edge of ClK IN, and may not be pulsed low again for the
next 31 clocks. At least one clock must occur while CS is
high. If ClK IN is held at a logic "1'; CS is disabled. This
allows the signal that drives CS to be used for other purposes when the MM58201 is not being addressed.
time of the LCD as specified by the LCD manufacturer.
The DATA OUT output is an open drain N-channel device to
Vss (Figure 4). With an external pull-up this configuration
allows the controller to operate at a lower supply voltage,
and also permits the DATA OUT output to be wired in
parallel with the DATA OUT outputs from any other drivers
in the system.
ClK IN latches data from the DATA IN input on its rising
edge. Data from the DATA OUT pin changes on the falling
edge of ClK IN and is valid before the next rising edge.
To program the number of backplanes being driven and
the MIS bit, load address 11000, a write bit, three bits for
the number of backplanes (Table I), and the MIS bit. The remaining 20 data bits will be ignored but it is necessary to
provide 21 more clocks before initiating another frame.
The first five bits of data following CS are the address bits
(Figure 3). The address selects the column where the
operation is to start. Bit 1 is the MSB and bit 5 is the lSB.
The sixth bit is the readlwrite bit. A logic "1" specifies a
read operation and a logic "a" specifies a write operation.
The next 24 bits are the data bits. The first data bit corresponds to the BP1 row of the display, the second data bit
to the BP2 row, and so on. After the eighth and sixteenth
data bits, the column pointer is incremented. When starting address 10110 or 10111 is specified, the column pOinter
increments from 10111 to 00000.
TABLE I. BACKPLANE SELECT
Numberof
Backplanes
2
3
4
5
6
7
8
During a read or write cycle, the LCD segment outputs do
not reflectthe data in the RAM. To avoid disrupting the
pattern viewed on the display, the read or write cycle time
should be kept short. Since the LCD turn-on time can be as
little as 30 ms, a clock rate of at least 10 kHz would be
required in orderto address the entire contents of the RAM
5-113
B2
B1
BO
a
a
0
1
1
a
0
1
1
1
1
1
1
a
a
a
1
1
a
1
1
Functional Description
(Continued)
RCOSC Pin
This oscillator generates the timing required for multiplex·
ing the liquid crystal display. The oscillator operates at a
frequency that is 4~ times the refresh rate of the display,
where ~ is the number of backplanes programmed. Since
the refresh rate should be in the range from 32 Hz to
100 Hz, the oscillator frequency must be:
128~:5
The voltage source on the VTC input must be of relatively
low impedance since the input impedance of VTC ranges
from 10 kD to 30 kD. A suitable circuit is shown in Figure 5.
In a standby mode, theV TC input can be set to Vss. This
reduces the supply current to less than 300 I'A per driver.
f osc:5 400~
Backplane and Segment Outputs
The frequency of oscillation is related to the external R
and C components in the following way:
fosc=
Connect the backplane and segment outputs directly to
the LCD row and column lines. The outputs are designed
to drive a display with a total ON capacitance of up to
2000 pF.
__1_ ±30%
1.25 RC
The value used for the external resistor should be in the
range from 10 kD to 1 MD.
The output structure consists of transmission gates
tapped off of a resistor string driven by VTC (Figure 6).
The value used for the external capacitor should be less
than 0.005 I'F.
VTC Pin
A critical factor in the lifetime of an LCD is the amount of
DC offset between a backplane and segment signal.
Typically, 50 mV of offset is acceptable. The MM58201
guarantees an offset of less than 10 mV.
The VTC pin is an analog input that controls the contrast of
the segments on the LCD. If eight backplanes are being
driven (~= 8), avoltage of typically 8V is required at 25·C.
The voltage for optimum contrast will vary from display to
display. It also has a Significant negative temperature
coefficient.
The BP1 output is disabled when the MIS bit is set to zero.
This allows the BP1 output from the master chip to be con·
nected directly to it so that synchronizing signals can be
generated. Synchronization occurs once each refresh
cycle, so the cascaded chips are assured of remaining
synchronized.
CLK IN
DATA IN
OO~'T CARE
I
A4
A3
A2
Al
AO
I RiW I
01
02
03
024
oATAOUT------~----------------------_[~0~1=r~0~2][~0~3][
Sl
S2
S3
S4
S5
S6
S7
SB
S9
SID
Sl1
S12
BPI
B~2
022
S13
S14
S15
01
09
017
02
010
018
BP3
03
011
019
BP4
04
012
020
BP5
05
013
021
BP6
06
014
022
BP7
07
015
023
DB
016
024
0
1
1
0
0
0
1
1
0
1
0
1
1
1
0
BPB
A4
A3
A2
Al
AO
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
1
1
0"
0
1
0
0
0
0
1
0
1
0
0
1
1
0
0
0
1
1
1
0
1
0
0
0
0
1
0
0
1
0
1
0
1
0
0
1
0
1
1
S16
S17
023
SIB
I 024
S19
S20
I
I
DON'T CARE
S21
S22
S23
5-114
-.,
B2 I
--I
81 I
-I
BO I
--I
MiS I
_J
0
1
1
1
1
1
0
0
0
0
1
0
0
0
1
1
0
0
1
0
1
0
0
1
1
1
0
1
0
0
1
0
1
0
1
1
0
1
1
0
Diagram above shows where data will appear on display if starting address 01100 Is specified in data format.
FIGURE 3. Data Format
S24
1
0
1
1
1
1
1
0
0
0
Functional Description
(Continued)
FIGURE 4. DATA OUT Structure
COP42DL
L..:0:::D_...;D::,:l_--=,:SK~----,,;S0c-_SI
CS
15V
CLK
IN
15V
DATA
IN
CS
CLK
IN
DATA DATA
IN
OUT
15V
MM582Dl
RC OSC
RC OSC
VSS
MM58201
VOO
~O.DD1/lF
-
-
8x48 DOT MATRIX
lInUID CRYSTAL DISPLAY
FIGURE 5. Typical Application
VTC
t
t}-BACKPLANE OR
SEGMENT OUTPUT
T
SELECT
FIGURE 6. Structure of LCD Outputs
5-115
-
PRELIMINARY
~National
a
Semiconductor
MM58248,MM58241 High Voltage Display Drivers
General Description
The MM58248 series are monolithic MOS Integrated circuits utilizing a combined CMOS/Bipolar process with
both MOS and Junction F.E.T. devices. They are available In 40-pin dual-in-line packages, or as dice. Each
output can source 1 mA at 2V maximum output voltage,
and also has an internal Junction F.E.T. to the display
supply voltage which can be up to 60V. The possibility
of brightness control is also provided.
• Compatible with VF, high voltage LCD, and
colloidal displays
Features
Applications
• Direct interface to 60V VF display
• Brightness and display blanking control input
(MM58241)
• COPSTM or microprocessor displays
• MICROWIRETM compatible (MM58241)
• Simple to cascade (MM58241)
• Wide supply operation
• TTL compatible inputs
• Software compatible with NS display driver family
• Instrumentation readouts
• Integrated dashboard displays
• Word processor text display
• No resistors needed
• No load signal required (MM58248)
CO~S
AND MICROWIAE are trademarks of National Semiconductor Corp.
Block Diagram
(58241)
OUT 32
OUT 1
---+---Ij~~~~D----t-vOiS
8RIGHTNESS/BLANKING
INPUT (58241) -
'-r==~r-' .--f__+-OATA OUT
--t-t>--I~§J~~~~
DATA IN_
CLOCK
(58241)
---+-t.::>--.......
ENABLE
(58241)
Figure 1. Block Diagram
Connection Diagrams
VsS(OV)
OUTPUT 17
40
39
OUTPUT 18
OUTPUT 19
VsslOVI
OUTPUT 17
OUTPUT 16
OUTPUT 15
OUTPUT 14
38
37
36
35
34
33
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
32
31
30
29
28
OUTPUT 26
OUTPUT 27
OUTPUT 28
OUTPUT 29
OUTPUT 30
OUTPUT 31
OUTPUT 32
OUTPUT 33
OUTPUT 34
OUTPUT 35
DATA IN
CLOCK
OUTPUT 16
OUTPUT 15
OUTPUT 14
OUTPUT 13
OUTPUT 12
OUTPUT 11
OUTPUT 10
OUTPUT 9
OUTPUT 8
OUTPUT 7
OUTPUT 6
OUTPUT 13
OUTPUT 12
OUTPUT 11
OUTPUT 10
OUTPUT 9
OUTPUT 8
OUTPUT 7
OUTPUT 6
OUTPUT 5
OUTPUT 4
OUTPUT 3
OUTPUT 2
OUTPUT 1
VOIS
Voo(+5VI
10
11
12
13
14
15
16
17
18
19
20
MM58248
27
26
25
24
23
22
21
20
21
22
23
24
25
OUTPUT 5
OUTPUT 4
OUTPUT 3
OUTPUT 2
OUTPUT 1
VOIS
VOOI+5V)
10
11
12
13
14
15
16
17
18
19
20
Order Number MM58248N, MM58241N
NS Package Number N4DA
Figure 2.
5-116
MM58241
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
. 24
23
22
21
OUTPUT 18
OUTPUT 19
OUTPUT 20
OUTPUT 21
OUTPUT 22
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
23
24
25
26
27
OUTPUT 28
OUTPUT 29
OUTPUT 30
OUTPUT 31
OUTPUT 32
BRIGHTNESS/BLANKING CONTROL
ENABLE
DATA OUT
DATA IN
CLOCK
Absolute Maximum Ratings
Voltage at Any Input Pin
Voltage at Any Display Pin
Operating Temperature
Storage Temperature
Power Dissipation
Voo +0.3V to Vss -0.3V
Voo to Voo -65V
-40°C to 85°C
-65°C to 150°C
500mW.at 85°C
750mW at 25°C
Junction Temperature
130°C
Lead Temperature (Soldering, 10 seconds)
300°C
Electrical Characteristics
TA within operating range, Voo = 5V ± 0.5V, Vss = OV, unless otherwise specified
Parameter
Power Supply
Voo
V01S
Power Supply Current
Iss
In~c:
I
Input Logic Level
Data In, Clock Enable
Conditions
Vss=OV
Voo=5V
Vss=OV
Min.
Typ.
Max.
Units
4.5
-10
5.0
5.5
-55
V
V
10
100
JAA
5
12
mA
Voo=5V
Vss=OV
Vn ,,,, =-55V
Voo = 5.0 ± 0.5V
Vss=O
Logic "0"
Logic "1"
Vss
2.4
Input Current
Data In, Clock Enable
Output Impedance
Output Off
Output On
Input Clock
Frequency
Rise Time
-----
VOIS = -40 V, VOUT = VOIS + 2V
ISOURCE = 1 mA
Voo=4.5V
0.8
Voo
V
10
JAA
2
kQ
kQ
500
200
kHz
ns
200
Functional Description
Figure 4 illustrates both possible microprocessor Interfaces. In 4a, a start bit of logic '1' precedes the 35 bits of
data. At the 36th clock a LOAD signal is generated synchronously with the high state of the clock, which loads
the 35 bits of shift registers into the latches. At the low
state of the clock a RESET signal is generated which
clears all the shift registers for the next set of data.
Hence a complete set of 36 clocks is needed or the shift
register will not clear.
This series of products is specifically designed to drive
either 4 or 5 digit non·multiplexed high voltage displays
(e.g., dynamic scattering LCD or gas discharge) or multi·
digit dot matrix high voltage displays (e.g., VF). Character generation is done externally in the microprocessor,
with a serial data path to the display driver. Two data
transfer modes and display brightness controls exist.
The MM58248 uses two signals, data and clock, with a
format of a leading '1' followed by the 35 data bits,
hence allowing data transfer without an additional load
signal. Display brightness can be achieved through
software control with the MM58248. The MM58241 uses
a standard MICROWIRETM interface for data transfer.
Display brightness is determined by the duty cycle of
the brightness/blanking input. Full brightness is obtained with a logic '0' at this input and blanking with a
logic '1'. A block diagram is shown in Figure 1.
In Figure 4b, the ENABLE signal acts as an envelope
and only while this signal is at a logic '1' does the circuit
accept CLOCK input signals. Data is transferred and
shifted in the internal shift register on the rising clock
edge, i.e., '0' - '1' transition. When the ENABLE signal
goes low, the contents of the shift register are latched
and the display will show new data. During data transfer, the display will continue to show old data. DATA
OUT is also provided in this mode, being output on the
falling clock edge.
Figure 2 shows the pinout of the MM58248 series. Bit 1
is the first bit to be loaded (following the start bit of
MM58248). A logic '1' at the input will turn on the appropriate display segment output. Figure 5 describes the
combined MaS and Junction F.E.T. output structure.
The Junction F.E.T. has a pinch-off voltage in excess of
60V and may be viewed simply as a high impedance
resistor.
When the chip first powers on, an internal reset is generated which resets all registers and latches. The chip
returns to normal operation on appl ication of the start
bit and the first clock for MM58248 or an application of
ENABLE for MM58241. All interface signals from the
microprocessor should be inactive at power on.
MICROWIRE Is a trademark of National Semiconductor Corp.
5-117
Timing Diagram
CLOCK~<
,-I',50_ns_I-_ _____
DATA
W
--------~~~-------______
<
__
Figure 3.
Data Format
n
LOAD
(INTERNAL) _ _ _...,--_ _ _ _ _ _~I,I!_-----....
1.._ _ _ __
n
RESET
(INTERNAL) _ _ _ _ _ _ _ _ _ _~I,I!_------....
1.._ _ __
Figure 4a. MM58248 Microprocessor Interface
CLOCK
,I-~I~n'
-1-'50ns
1
r-+---;--i-----MI-N<-------......J
IMM5834',---
Figure 1. Block Diagram
Connection Diagrams
VSS(OV)
OUTPUT 17
OUTPUT 16
OUTPUT 15
OUTPUT 14
OUTPUT 13
OUTPUT 12
OUTPUT 11
OUTPUT 10
OUTPUT 9
OUTPUT 8
OUTPUT 7
OUTPUT 6
OUTPUT 5
OUTPUT 4
OUTPUT 3
OUTPUT 2
OUTPUT 1
VOIS
VOOI+5V)
10
11
12
13
14
15
16
17
18
19
20
MM58348
40
39
3B
37
36
35
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
18
19
20
21
22
23
VSS(OV)
OUTPUT 17
OUTPUT 16
40
39
3B
OUTPUT 15
OUTPUT 14
OUTPUT 13
.34
33
32
31
30
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
24
25
26
27
2B
29
28
27
26
25
24
23
22
OUTPUT 29
OUTPUT 30
OUTPUT 31
OUTPUT 32
OUTPUT 33
OUTPUT 34
OUTPUT 35
OUTPUT 12
OUTPUT 11
OUTPUT 10
OUTPUT 9
OUTPUT 8
OUTPUT 7
37
36
35
34
33
32
31
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
30
29
28
27
26
25
24
23
22
21
OUTPUT 28
OUTP~T 29
OUTPUT 30
OUTPUT 31
OUTPUT 32
BRIGHTNESS/BLANKING CONTROL
ENA8LE
DATA OUT
DATA IN
CLOCK
21
OUTPUT 6
OUTPUT 5
OUTPUT 4
OUTPUT 3
OUTPUT 2
OUTPUT 1
VOIS
DATA IN
CLOCK
VOOI+5V)
10
11
12
13
14
15
16
17
18
19
20
Order Number MM58348, MM58341
NS Package N40A
Figure 2_
5-119
MM58341
lB
19
20
21
22
23
24
25
26
27
Absolute Maximum Ratings
Voltage at Any Input Pin
Voltage at Any Display Pin
Operating Temperature
Storage Temperature
Power Dissipation
Voo +0.3 V to Vss -0.3 V
Voo to Voo -40V
-40·C to 85·C
-65·C to 150·C
500mWat 85·C
750mW at 25·C
Junction Temperature
130·C
Lead Temperature (Soldering, 10 seconds)
300·C
Electrical Characteristics
TA within operating range, Voo = 5V ± 0.5V, Vss = OV, unless otherwise specified
Parameter
Power Supply
Voo
Vols
Power Supply Current
Iss
, IDis
Input Logic Level
Data In, Clock Enable
Conditions
Vss'=OV
Voo=5V
Vss=OV
Min.
Typ.
Max.
Units
4.5
-10
5.0
5.5
-27
V
V
10
100
,..A
5
12
mA
Voo=5V
Vss=OV
VDls=-25V
Voo = 5.0 ± 0.5V
Vss=O
Logic "0"
Logic "1"
Vss
2.4
Input Current
Data In, Clock Enable
Output Impedance
Output Off
Output On
Input Clock
, Frequency
Rise Time
VOIS = -27V, VOUT = VOIS + 2
ISOURCE = 3mA
Voo=4.5V
.
200
250
0.8
Voo
V
10
,..A
400
kQ
Q
500
200
kHz
ns
Functional Description
This series of products Is specifically designed to drive
either 4 or 5dlglt non·multlplexed high voltage displays
(e.g., dynamic scattering LCD or gas discharge) or multi·
digit dot matrix high voltage displays (e.g., VF). Charac·
ter generation is done externally In the microprocessor,
with a serial data path to the display driver. Two data
transfer modes and display brightness controls exist.
The MM58348 uses two signals, data and clock, with a
format of a leading '1; followed by the 35,data bits,
hence allowing data transfer without an additional load
signal. Display brightness can be achieved through
software control with the MM58348. The MM58341 uses
a standard MICROWIRETM Interface for data transfer.
Display brightness is determined by the duty cycle of
the brightness/blanking input. Full brightness Is
obtained with a logic '0' at this Input and blanking with
a logic '1'. A block diagram Is shown In Figure 1.
Figure 4 illustrates both possible microprocessor Interfaces. In 4a, a start bit of logic '1' precedes the 35 bits of
data. At the 36th clock a LOAD signal Is generated syn·
chronously with the high state of the clock, which loads
the 35 bits of shift registers Into the latches. At the low
state of the clock a RESET signal Is generated which
clears all the shift registers for the next set of data.
Hence a complete set of 36 clocks Is needed or the shift
register will not clear.
In Figure 4b, the ENABLE signal acts as an envelope
and only while this signal Is at a logic '1' does the circuit
accept CLOCK Input signals. Data is transferred and
shifted in the Internal shift register on the rising clock
edge, i.e., '0' - '1' transition. When the ENABLE signal
goes low, the contents of the shift register are latched
and the display will show new data. During data
transfer, the display will continue to show old data.
DATA OUT Is also provided In this mode, being output
on the failing clock edge.
Figure 2 shows the pinout of the MM58348 series. Bit 1
is the first bit to be loaded (following the start bit of
MM58348). A logic '1' at the Input will turn on the'
appropriate display segment output. Figure 5 describes
the combined MOS and Junction F.E.T. output structure. The Junction F.E.T. has a pinch-off voltage In
excess of 32V and may be viewed simply as a. high
Impedance resistor.
When the chip first powers on, an internal reset Is gen·
erated which resets all registers and latches. The chip
returns to normal operation on application of the start
bit and the first clock for MM58348 or an application of
ENABLE for MM58341. All Interface signals from the
microprocessor should be Inactive at power on.
MICAOWIRE Is a trademark of National Semiconductor Corp,
5-120
Timing Diagram
CLOCK
DATA
~
~
/ \
-J
~I_
-.----""""")K. . ______
Figure 3.
Data Format
~
1
CLDCK~~
START BIT 1
BIT 35
~~~L--_
n
LOAD
(INTERNAL) _ _ _ _ _ _ _ _ _ _~I_---___:_-.....
1/
RESET
(INTERNAL) _ _ _ _ _ _ _ _ _ _~I_------......I
, I,
II
Figure 4a. MM58348 Microprocessor Interlace
CLOCK
.I_~I~~S
r-+----i--i----------~·L
ENABLE
DATA IN
I
-'ir
y--"""'"'\
MAX"
50ons
DATA OUT
----------------~
-----------
Figure 4b. MM58341 Microprocessor Interlace
Typical Application
VDD
INPUT
FROM
LATCH
OUTPUT
VoD
VOIS
·For high current displays, MM58348 outputs may need"to be paralleled or, as an
alternative, the 058881 may be required to be used as a grid driver.
Figure 5. Output Structure
Figure 6. Word Processor Application
5-121
Section 6
Standard
Controllers
~National
PRELIMINARY
s:
s:
CJ1
.....
~ Semiconductor
~
CD
MM57409 Super Number Cruncher
General Description
The MM57409 Super Number Cruncher is designed to
function as a peripheral arithmetic processor in micro·
processor applications. Data and instructions are trans·
ferred asynchronously between processor and peripheral
using the standard B·bit MICROBUSTM. Software develop·
ment is greatly simplified when using the MM57409's cal·
culator keyboard level language. This means that com·
plex arithmetic functions can be incorporated in micro·
processor software quickly and easily by any program·
mer familiar with the operation of a scientific calculator.
Besides arithmetic operations, the device has internal
number storage, input/output instructions and test and
branch capability. In the stand·alone mode, an B·bit
address is present on the PCO-PC7 pins for interface to
an external program PROM, ROM, or RAM.
• Flexible input/output
- Multidigit I/O instructions (IN, OUT) with floating
pOint or scientific notations
- Programmable mantissa digit count for IN, OUT
instructions
- Sense input and flag outputs
• Branch control
- Conditional and unconditional program branching
• Interface simplicity
- On·chlp clock OSC
- MICROBUS interface
Applications
• Instruments
• Microprocessor/minicomputer peripheral
Features
• Test equipment
• Scientific calculator instructions (RPN)
- Up to 12·digit mantissa, 2·digit exponent
- Four·register stack, one memory register
- Trigonometric functions, logarithmic functions,
VX, eX, pi
- Error flag generation and recovery
• Process controllers
MICROBUS Is a trademark of National Semiconductor Corp.
CLOCK
VCC
CKO
R7
R6
R5
R.
R3
R2
Rl
RO
SUPER
NUMBER
CRUNCHER
(28) DO
(27) 01
(26) 02
(25) 03
2' PC7
25 PC6
26 pe5
27 PC4
28
29
30
31
PC3
PC2
PCl
peD
19 00
18 0,
17 02
16 0
PC FOR STAND ALONE
MOOE OR GENERAL 110·
l
8·BIT DATA BUS
00·07
GENERAL PURPOSE
OUTPUTS
SNC
RiiS
MICROPROCESSOR
WRS
+V
cs
=
READ STROBE
WRITE STROBE
INTR/ROY
CHIP SELECT
·THESE PINS DELETED
FOR 28·PIN PACKAGE.
NUMBERS IN PARENTHESES
ARE PIN NUMBERS FOR 2B·PIN
PACKAGE.
SYNC RIVI
Super Number Cruncher Interface
with 8·BIt Microprocessor
Figure 1. Super Number Cruncher- Pinout
6-3
Data Entry Instructions
a
1
Mantissa or exponent digits. On first digit (d),
if prior code was not EN (Enter), get stack push:
was
2
3
4
5
6
7
Z-t
V-Z
X-V
d-X
If prior code was EN, get simply d.
Set number entry mode. See number entry de·
scription.
SIF3
RIF3
Set internal flag 3.
Reset internal flag 3.
SIF4
RIF4
Set internal flag 4.
Reset internal flag 4.
Math Instructions
CLRX
EN
B
9
DP
EE
CS
Pi
Decimal poinl. Digits that follow will be man·
tissa fraction. If first "numeric" entry, initiates
number entry mode as above.
Enter Exponenl. Digits that follow will be exponent. If first "numeric" entry, initiates number
entry mode as above and loads 1 to mantissa.
Change Sign. If EE instruction was executed
after last number entry initiation, changes
exponent sign X; else changes sign X mantissa. Does not initiate number entry.
3.14159265359-X; iffirst numeric entry, initiate
number entry mode (stack push) as above.
AIN1
Single-Digit Asynchronous input initiates number entry as above. See input/output description.
NOP1
No operation. Do nothing. Status not altered in
anyway.
NOP2
ROLL
Multidigit inpLit instruction - SNC accepts all
required data for input. See input/output description for further explanation.
AIN2
Asynchronous input 2. 2-byte instruction. Write
a single digit, any digit, in x. Second byte of form
Nx where N =O-F for digit address in register
x = BCD data. See input/output description for
further explanation.
I DPC
Load PC/B-bit general 110 port with daa contained in next byte. 2-byte instruction.
Terminate number entry; no other operation.
NOP2
DEG
RIO
RPC
NORND
RND
FLP
SCI
SIF1
RIF1
SIF2
RIF2
SIN
Sin (x)-x; y,z,t,m unchanged.
COS
TAN
COS (x)-+x; y,z,t,m unchanged.
Tan (x)-x; y,z,t,m unchanged.
10X
SQ
SQRT
LN
Mode and Flag Instructions
RAD
Roll Stack
+-+x-y-z-t-+
ARCSIN Sin-1 (x)-+x; y,z,t,m unchanged.
ARCCOS COS-1 (x)-x; y,z,t,m unchanged.
ARCTAN Tan-1 (x)-x; y,z,t,m unchanged.
Terminates number entry, no other operation.
NOP2
Clear Error Flag.
ECLR
Convert x; radians to degrees y,z,t,m unchangRTD
ed.
Convert x; degrees to radians y,z,t,m unchangDTR
ed.
POP
Pop Stack:
y-x
z-y
t-z
o-t
MCLR
Clear all internal registers and outputs; 10 MDC
scientific notation; rouna to MDC on output.
XEV
Exchange X,y x +-+y
EX
eX-x; y,z,t,m unchanged.
Data Input
IN
a-x
Enter, terminate number entry and push stack.
z-t
y-+z
x-y
same number in x and y.
Terminate number entry, no other operation.
Set radian angular mode.
Set degrees angular mode default mode.
Enable R as general 110.
Enable R as program counter.
Disable round to MDC on output.
LOG
1/X
vx
+
Disable round to MDC on output default mode.
Set floating point 110 mode.
Set scientific notation 110 mode-default
mode.
Set internal flag 1.
Reset internal flag 1.
Set internal flag 2.
Reset internal flag 2.
x
6-4
10x -x; y,z,t,m unchanged.
x2 -x; y,z,t,m unchanged.
(X)O.5_ X; y,z,t,m unchanged.
In x-+x; y,z,t,m unchanged.
log x-x; y,z,t,m unchanged.
1/x-x; y,z,t,m unchanged.
yX-x; z-y, t-+z, O-t.
x+y-x; z-y, t-z, 0-+1.
x-y-x; z-y, t-z, 0-1.
x ·y-x; z-y, t-z, 0-1.
x/y-+x; z-y, t-+z, O-t.
NOP2
LSH
Terminate number entry, no other operation.
Left shift x mantissa, DP unchanged, MSD
saved in guardllink digit.
RSH
Right shift x mantissa, DP unchanged, link/
guard digit MSD.
Test Instructions
Digit Count Control
TJC
If jump condition (input JC) true, load PC with
data in second byte.
SMDC1
SMDC2
If X = 0, load PC with data in second byte.
If X the
Display Select input is ignored and has no effect whatsoever on the display. This input may be hard wired to
either Vee or ground; may be controlled by a switch or
may be controlled by a logic signal. The input may be
changed at any time by the user without impairing the
operation of the device.
4I8-Di9it Decimal (16/32-Bit Binary) - With this pin left
open or tied to Vee the MM57436 is a 4-digit decimal or
16-bit binary counter. Connecting this pin to ground
converts the MM57436 to an 8-dlgit decimal or 32 bit
binary counter. The counter length is a strap option and
may not be changed while the device is running.
6-8
;
:~
:
General Operation
Initialization
The RESET logic will clear the MM57436 if the power
supply rise time is between 1 ms and 1,..s. If the power
supply rise time is greater than 1 ms, the user must pro·
vide an external RC network and diode to the RESET pin
as shown below (Figure 2). The RESET input is configured
as a Scbmitt trigger input. The user may control this
with an external signal if desired as long as the proper
levels are maintained. The RESET pin is the means by
which the user may clear the counter. RESET may be
brought low at any time. The MM57436 will be cleared
whenever the proper "0" level is applied at the RESET
input provided the input stays low.for at least 16 clock
cycles. If the reset pfn is not used it should be connected
toVcc ·
The external oscillator is recommended when the counting speed and/or the stability of the counting speed Is
critical. The internal RC oscillator is only accurate to
about ±15% to ±20%. However, if practical in the
application, the RC network can be tuned for the cleslred
operating frequency. Some typical RC values that place
the operating speed at near the maximum are shown
below (Figure 3).
Power Supply
The MM57436 has two Vcc pins: VCC1 and VCC2 - and two
ground pins: GND1 and GND2. Both VCC1 and VCC2 must
be connected to the positive supply (Vcd.' Both GND1
and GND2 must be connected to ground. Failure to do
this will result in improper operation of the MM57436.
Count Input
\\:C2
t----I
S
U
RESET
The MM57436 counts negative-going pulses at the
::::::.:;-:~ !;-:~:.:!. T~e ',i,irlth nf the negative-ooino (logic "1"
to logic "0") must be at least 8 times the oscillator cycle
time.
MM57436
P
P
In order to maximize the counting speed and not to miss
any pulses, during the display cycles, the MM57436 has
a 4-bit register at the COUNT Input which will accumulate
up to 15 counts. This register Is added/subtracted from
the counter. Therefore at the higher input count speeds,
when the counter is changed from an up counter to a
down counter or vice versa, there Is a window'of up to 15
counts - the max'imum value In the input register - In
the count. This effect is completely unobservable at
slow input count speeds and gradually becomes more
noticeable as the repetition rate of the count pulse
increases. If the up/down mode is not changed during
operation, the only observable effect of the input register
Is that the display may appear to increment or decrement
L
Y
Re ;. 5 x POWER SUPPLY RISE TIME
Figure 2. Power· Up Clear Circuit
Oscillator
The user has the option of connecting an RC network to
the OSC IN pin and using the internal oscillator or he
may supply an external oscillator to the OSC IN pin. The
OSC IN input is a Schmitt trigger input and the user must
insure that the proper levels are met when supplying an
external cloCk.
:-~ . . . ':' . .
, .... 0:0
~ .. ooot.o.r th~n
1
Vec
MM57436
OSC IN
O. 7Vec
ill ~'
MM57436
J
f
OSCIN
I
O.6V
EXTERNAL CLOCK
RC Controlled Oscillator
R(kQ)
C(pF)
asc IN Period !/As)
51
82
100
56
4.75 ± 15%
4.75 ± 13%
Figure 3. MM57436 Oscillator
6-9
•
Input/Output Characteristics
. Inputs
Outputs
The MM57436 has three types of inputs. Figure 4a is the
input with a depletion load to Vcc found on pins 17, 18,
and 19 (Decimal/Binary, Up/Down, 4/8 Digit). Figure 4b is
a slightly different type of input with a depletion load to
Vcc found on pins 4 and 14 (RESET, COUNT). The remaining input, pin 5-Display Select, has no load device
'(Figure 4c).
There are only two types of outputs on the MM57436:
the segment drivers (Figure 5a) and the digit drivers
(Figure 5b).
Vee
Vee
.. = DEPLETION DEVICE
INPUT
INPUT
a_ Pins 17, 18, 19
b. Pins 4, 14
c. Pin 5
Figure 4. Input Configurations
Vee
Vee
.. = DEPLETION DEVICE
b. Digit Driver Outputs
a. Segment Driver Outputs
Figure 5_ Output Configurations
6-10
Input Current Decimal!
Binary, UplDown, 418
Digit
Input Current RESET,
Count
-200
-1000
-900
I
.......
-150
r-....
.......
.......
r-....
1\
r-....
IMIN @
1
::
"\
-600
-500
IMAX @ Vee = 9.5V
~
IMAX @
:'\
-400 Vee = 4.5
~ iMIN @
-300
r-'Ree=4.5
~~
IMIN @
-200
r-+-~ Vee = 9.5
-100
I'\.
\
LIMIN @
Vee - 9.5V
..::ie ~\5y 1\
o
t"-
"
-700
:J:
IMAX @
vee=4r
-50
-800
IMAX @
~e=9.5V
\
r- Ho!, .:'k./"'i--.
1.0 2.03.04.05.06.07.08.0
1 2 3 4
9.5
l......
Sa-Sg LED Output
Source Current
LED Output Direct
Segment and Digit Drive
-50
IMJ
-40
«E
_
-30
§.
::
:: -20
./
:J:
V
-10
...........
3
4
5
6
7
IMIN
8 9 10
10
\lnll /\InIT~\
Vee (VOLTS)
LED Output Direct
Segment Drive
-50
SEGMENTS ON
!....
:::::L......
2
VI~AX EI~HT
V V
........
-10
I
ON~-
""
;; -20
1
9.5
VIN (VOLTS)
VIN (VOLTS)
o
~
5 6 7 8
Output Sink Current
lor 0 0 -0 3
)
VOH =2.0V
-40
«
§.
l-
-30
IMAy
:J:
V
9 -20
.'
,.'
-10
....."
.... .......
o
IMIN
4
10
1
Vee (VOLTS)
2 3
4
5
6 7
VOL (VOLTS)
Figure 6. I/O DC Current Characteristics
6-11
8
9
10
-,
~
~
II)
:Ii
:Ii
i
Vee
4/8 VCC1
OIGIT
Vee OR N/C
13
RESET
Vee
Sb
COUNT UP
Sc
18
Sd
UP/OOWN
COUNT DOWNl
12
11
10
S,
Sf
Sg
MM57436
OECIMAL!
BINARY
lSLJ
14
COUNT
D3
02
0,
DISPLAY
SELECT GND1- GND2
00
17
24
23
22
21
20
-::-
-::-
Figure 7_ MM57436 as 16-Bit Binary Counter with RC Oscillator and Switch-Controlled Up/Down Mode
Vee
13
Sb
-::Vee OR N/C
Sc
17
19
Vee
Sd
OECIMAL/8INARY
4/8 DIGIT
-::-
12
11
10
S,
•
Sf
Sg
MM57436
DISPLAY TOP
4 DIGITS
1
OISPLAY
SELECT
DISPLAY LOWER
4 DIGITS
lSLJ
03
14
02
COUNT
0,
GND1 GND2
00
24
23
22
21
20
Figure 8_ MM57436 as 8-Digit Decimal Down Counter with Extenal Oscillator
6-12
I
~National
a
Semiconductor
MM57455 Advanced Educational Arithmetic Game
General Description
Figure 1 contains an electrical diagram of a complete
teaching game system.
• Internal timer gives the user about 10 seconds to
answer. If he doesn't answer, the problem is counted
wrong
Features
• Ten problems in each problem set
• Number of problems correct appears in the display at
the end of a problem set, with the green LED flashing
• Produces add, subtract, multiply, and divide problems
which teach basic arithmetic
• "TABLE" button causes non-random problems to be
generated
• 6,562 different problems are produced
• Problems are generated randomly and al,ltomatically
• Automatic entry, no "ENTER" key is needed
• "COMPLEX" button causes algebra-type problems to
be generated
• "AMATEUR/PRO" buttons select easy/hard addition
and subtraction problems
• If the wrong answer is entered, "E" appears in the
display and the user gets a second try
• "NORMAL/FAST" buttons select 10 or 3 seconas io
answer a problem
• If the user answers incorrectly on both tries, the correct answer is flashed in the display
• Automatically begins game on power "ON"
• Low system cost (Figure 1)
Electrical Diagram
S.-Sg
15-12
B-6
28
27
26
25
21
22
MM57455
23
24
19
9
10
20
CKI
3
Vee
t
RESET
4
lB SK
"2
D3
D4
D5
D6
D7
INo
..
Vee
I
lOOk
AMATEUR
7
4
1
SLOW
PRO
B
5
2
FAST
ALGEBRA
9
6
3
0
TABLE
I
x
-
+
IN,
L
INz
II
IN3
Vee
:~
47k
rl00PF
Do
D,
2N2907
.,,<
GREEN
? / LED
-I-
IO.l~F
50012
-'-
6-13
Absolute Maximum Ratings
Voltage at Any Pin Relative to GN 01
Ambient Operating Temperature
Ambient Storage Temperature
Lead Temperature (Soldering, 10 Seconds)
Power Dissipation
-O.3Vto +10V
O·Cto +70·C
-65·Cto +150·C
300·C
0.75 Watt at 25·C
0.4 Watt at 70·C
"Absolute Maximum Ratings" indicate limits beyond which dam·
age to the device may occur. DC andAC electrical specifications
are not ensured when operating the device at absolute maximum
ratings.
DC Electrical Characteristics
Parameter
O·C" TA
"
70 ·C, 4.5V " Vcc " 9.5V, unless otherwise specified
Min.
Conditions
4.5
Operating Voltage (Vccl
Operating Supply Current
Typ.
Max.
Units
9.5
V
8
mA
(all inputs and outputs open)
Input Voltage Levels
I
OSCIN,~
Logic High (V1H )
Logic Low (VIlJ
All Other Inputs
Logic High (V1H )
Logic High (V1H)
Logic Low (VII)
Output Current Levels
Ouptut Sink Current
0 0 -07 (loJ
S.-Sg (loJ
Output Source Current
S.-Sg (IOH)
0.6
V
V
0.8
V
V
V
0.7Vcc
3.0
2.0
Vcc=9.5V
Vcc.=5V± 10%
Vcc = 9.5V,
Vcc = 4.5V,
Vcc = 9.5V,
Vee = 4.5V,
VOL = 1.0V
VOL = 1.0V
VOL = 0.4V
VOL = 0.4V
mA
mA
mA
mA
30
15
0.8
0.4
-3.0
-3.0
Vee = 9.5V, VOH = 2.0V
Vee = 6.0V, VOH = 2.0V
-35
-25
mA
mA
Functional Description
Display Configuration
Number Keys, "0-9"
The special LED display used with the MM57455 displays
any of the 4 symbols" + ", "- ", "x ", "I" in the third digit
position. An "=" is displayed in the sixth digit position.
The remaining 6 digits are normal 7·segment numeral
displays.
These keys are used io enter answers to problems. After
a problem appears in the display, the user has 2 tries to
answer it correctly.
Power "ON"
If the user keys in the correct answer to a problem, the
green LED lights up immediately for 1 V. seconds. Then
a new problem appears.
Green LED
Upon powering "ON" the MM57455, it begins displaying
the sysmbols "+", "_", "x", "I", "+", ... one after another, each lasting about V. second. This indicates that it
is at the beginning of a "problem set" and ready to accept a function key input.
Incorrect Answer Indicator
If the user keys in a wrong answer to a problem, his
answer disappears in the display and an "E" appears.
Key Operations
Second Try
Function Keys u+" "_" IIX" I'/,'
One of these keys i~ dep;essed to begin a problem set.
After pressing one of these keys, a randomly generated
problem appears in the display. The problem is either
"+", "_", "x", "I", depending on the key that was
pressed.
If the user answers incorrectly, he gets a second try.
Whe;l the "E" appears (indicating that the answer is
wrong), he types in his second try. Again, the green LED
lights if correct, and an "E" appears if wrong.
6-14
Functional Description
(cont'd)
Internal Timer
A non·random table digit can be selected by depressing
the desired number (1·10) just before pressing a function
button at the start of a problem set.
The MM57455 has an internal timer which allows the user
10 seconds to answer a problem. If he doesn't answer in
10 seconds, an "E" appears in the display, indicating a
wrong answer. The user then gets a second try and again
must answer within 10 seconds.
Example: press 9 x
and these problems will appear:
Flashing of a Correct Answer
9x1=
9x2=
9x3=
In the user answers wrong on both tries, the correct
answer flashes in the display. Then the next problem
appears.
Ten Problems per Problem Set
9xO=
New problems appear one after another until 10 prob·
lems have been done.
"ALGEBRA" Key
If the "ALGEBRA" key is depressed just before pressing
a function key at the start of a problem set, algebra·type
problems will be displayed (the answer is present and
nnp of the factors is blank, as: (15 +
= 21). The user
must enter the missing factor. (Note. Both "ALGEBRA"
and "TABLE" buttons may be pressed before pressing a
function key. This will cause algebra·type table problems
to be displayed.) The order of depression is unimportant;
i.e., "ALGEBRA" or "TABLE" may be pressed first.
Score at End of Problem Set
After 10 problems are done, the number of problems the
I
I ~I;~'h~~.i g~;~: f~;~~~:~~~;~r;;~!~~'U~~;d!~~r~:~~~it~~
16 flashes, the MM57455 again displays "+", "-", "x",
, "I", "+ ", ... and is ready for another function key entry.
"TABLE" Key
"AMATEUR/PRO" Keys
If the "TABLE" key is depressed just before pressing a
function key at the start of a problem set, table problems
will appear, with a random table digit.
These keys select easy ("AMATEUR") or hard ("PRO")
addition and subtraction problems. Easy means sum < 30
and difference < 20. Hard means sum < 100 and differ·
ence < 100.
Example: press "TABLE" x
and these problems may appear:
When power is turned "ON", the machine is in easy
("AMATEUR") mode.
6x1=
6x2=
6x3=
"NORMAL/FAST" Keys
T&.o..-:- ........ L,~:/e. !:Ire IIQo.n tn
Qo.lpr.t 10 s,p.:cond ("NORMAL II )
or
3 second ("FAST") answer time.
6x 10=
When power is turned "ON", the machine is in the 10
second ("NORMAL") mode.
6-15
m
~ ~National
~
Semiconductor
::E
a
MM57459 a-Digit LED Direct-Drive Memory Calculator
General Description
Features
The single-chip MM57459 calculator was developed using
an N-channel enhancement and depletion mode MOS/LSI
technology with a primary object of low end-product cost.
A complete calculator as shown in Figure 1 requires
only the MM57459 calculator chip, and X-Y matrix keyboard, an NSA1188 LED display and a 9V battery_
• 8 Digits with four key memory (M+, M-, MR, MC)
Keyboard decoding and key debounce circuitry, all
clocks, and timing generators, power-on clear, and
7-segment output display decoding are included onchip, and require no external components_ Segments
and digits can usually be driven directly from the
MM57459, as the segments source up to 30mA max.
peak current and the digit drivers sink 30 mA min.
Leading zero suppression and a 'floating negative sign
allow convenient reading of the display and conserve,
power. Up to 8 digits for positive numbers and 7 for
negative numbers can be displayed, with the negative
sign displayed in the left-most position.
• Low voltage operation (single power supply)
• Direct interface with digits and segments of LED display
• Percent function with add-on/discount
• Automatic constant on all five functions
•
•
•
•
•
•
Floating minus sign
Leading zero suppression
Internal clock generator
Internal encoding for keyboard inputs
Internal debouncing for keyboard inputs
Display flash in calculator overflow state
Typical Keyboard and Connection Diagram
BBEJEJ
I
CLEAR
108
0000
00~[J
GND
24
DO
INO
23
D1
CKI
22
D2
RESET
21
D3
Sf
20
D4
Sb
19
D5
18
D6
Sg
MM57459
Sd
D7
00[!]G
VCC
Se
N.C.
G0c:JCJ
Sa
IN1
Sp
Sc
N.C.
Top View
Order Number MM57459N
NS Package N24A
6-16
Absolute Maximum Ratings
-0.3V to + 10V
O°Cto +70°C
-65°Cto +150°C
300°C
0.75 Watt at 25°C
0.4 Watt at 70 °C
Voltage at Any Pin Relative to GND1
Ambient Operating Temperature
Ambient Storage Temperature
Lead Temperature (Soldering, 10 Seconds)
Power Dissipation
Absolute Maximum Ratings indicate limits beyond which damage to
the device may occur. DC and AC electrical specifications are not en·
sured when operating the device at absolute maximum ratings.
DC Electrical Characteristics
Parameter
O°C" TA
..
70°C, 4.5V" Vee" 9.5V, unless otherwise specified
Conditions
Min.
Operating Voltage (Vee)
4.5
Operating Supply Current
(all inputs and outputs open)
Units
Max.
9.5
V
8
mA
0.6
V
V
0.8
V
V
V
I
inpui 'v'oiiClyt: i...~vt::i'>
CKI, RESET
Logic High (V'H)
Logie Low (V,d
['
Typ.
0.7 Vee
All Other Inputs
Logie High (V'H)
Logie High (V'H)
Logic Low (V,d
Vee =9.5V
Vee = 5V ± 10%
Output Current Levels
Ouptut Sink Current
0 0 -0 3 (Iod
Vee = 9.5V,
Vee = 4.5V,
Vee = 9.5V,
Vee = 4.5V,
Sa,-S9' Sp (Iod
Output Source Current
Sa-S9' Sp (IOH)
--
30
15
VOL = 1.0V
VOL = 1.0V
VOL = O.4V
VOL = O.4V
Vee = 9.5V, VOH = 2.0V
~ R OV v~ .. =? OV
1/__
I
3.0
2.0
mA
mA
mA
mA
0.8
0.4
,
6-17
-3.0
-3.0
-35
-25
mA
mA
-
,
1. Key Definition
~-
0-0-8
The first number key in a sequence will clear the display
and enter the digit in the LSD of the display. Successive
entries will shift the display left and enter data in the
LSD. The first decimal point entered is effective. An at.
tempted entry of more than 8 digits or 7 decimal places
will be ignored.
~
-
Clear
Clears the display and constant registers, and the result
overflow indicator. Memory register is not affected by
key. In the memory overflow condition, this key is opera·
tive as a clear memory key.
~
-
8-
Memory Recall
Transfers the contents of the memory register into the
display register. Memory is retained except in the memo
ory overflow condition. In this case, memory is cleared
and its previous contents are displayed in the result over·
flow mode.
Clear Entry
Clears the display of a number entry. In the result overflow mode, this key resets the overflow condition and
allows calculation to continue; however this key is inoperative during memory overflow.
B - Memory Plus
Add the current display to the contents of memory. M +
will termniate a number entry.
~ - Memory Clear
Clears the memory.
B - Memory Minus
8- Plus
Subtracts current display from the contents of memory.
M- will terminate a number entry.
Stores an addition operation and performs a possible
preceding operation. Successive depression of the plus
key will not affect the display.
[J -
Percent
The purpose of the percent key is to allow forthe calcu·
lation of add·on and discount. Determination of add·on
requires the principal amount to be the first enter fol·
lowed by the + or x key, with the percentage being
the second entry. Depression of the percent key yields
the amount to be added·on, such as tax or interest. De·
pression of the = key adds this amount to be principal.
Discount is determined in a similar manner using the key (x and - keys). In the constant mode, new percent·
ages to be added-on may be entered while retaining the
principal amount.
2. Error Conditions
Minus
Result Overflow
Stores a subtract operation and performs a possible
preceding operation. Repeat subtraction by the minus
key will not be possible. If this is depressed after a % ,
+ ,or = key, subtraction becomes the pending opera·
tion. Immediately following a x or ... key, this acts as
a data entry and -0. is displayed.
If the result in absolute value exceeds 108 -1, the display
will flash, and only the C and CE keys are operative.
Memory Overflow
If a M + or M - operation causes the contents of
memory to exceed the above value, the display will flash.
In this overflow condition, only the C key is operative.
0- Multiply
Operates the same as the plus key except that a multiply
command is stored. Successive depression of the mUltiply key will not alter the display.
3. Operation Characteristics
Ej- Divide
Data Entry
Operates the same as the plus key except that a divide
command is stored. Successive depression of the divide
key will not alter the display.
Entry is always floating. On data entry, the data will be
right hand justified with the last digit entered always
appearing in the least significant digit position. The dis·
play register will left shift the display one digit as each
new digit is entered.
GJ - Equal
Executes any previous operation and maintains that
operation for possible use in the implied constant mode.
The first factor entered for multiplication and the second
factor entered for division, subtraction, and addition,
are retained for the constant operation. Completes the
add·on or discount mode when used following the %
key. The first depression of the equal key immediately
following a + or - key will not alter the display.
Data Output
The output data as a result of a calculation will be right
hand justified such that trailing insignificant zeros after
the decimal are not displayed. Numbers less than one (1)
will be displayed with one leading zero (0.25 for example).
Numbers greater than one (1) will not display zeros to
the left of the most significant digit.
6-18
Output Display
I
Character Display SA S8 SC SD SE SF SG SP
The output segments are fully decoded for standard
seven-segment display. The digit outputs are multiplexed
with the segment scan to provide the output.
n
'-'
0
•
•
•
Digit and Segment Buffers
2
The segment buffers provide constant drop and operate
in conjunction with the constant current digit buffers to
provide display current ..
3
4
Constant Operation
6
The MM57459 has an implied constant mode of operation
on +, - , x , .,. ,and % operations. The constant
calculation is performed automatically by the = key,
% key, or % = keys without a constant switch. The
second operand is treated as the constant for add, subtract, and divide and the first operand is the constant
for multiplication.
7
:::J
L.
:1
Y
5
5
5
• •
.•
•
I
B
9
8
9
•
•
•
•
•
•
•
•
Minus Sign
Dec. Pt.
.
'
RESULT OVF: THE DISPLAY WILL FLASH.
MEMORY OVF: THE DISPLAY WILL FLASH.
For A ± B%-type calculations, the first operand is treated
as the constant with the percentage displayed with the
proper sign.
Floating Minus Sign
Decimal Alignment
When displaying a negative number the minus indication
will be located one digit to the left of the MSD display.
The results of addition or subtraction remain aligned to
the preceding entry having the most decimal places unless a right shift Is needed to keep the eight most significant digits (in which case the least significant decimal
digits are lost).
The results of multiplication and division are completely
right justified such that only the most significant digits are
displayed (the digits not displayed will be truncated).The
C key resets decimal alignment.
Display Font
Successive Operations
The following table shows the required segment outputs
as a function of the display. In the truth table, the symbol
• Is used to indicate a selected segment.
Only the last operation entered is performed unless a entry follows a x or .,. which sets up the calculator for
numeric entry only.
II
+V
I
'--'
~~
9
51k
100pF
13
Vee
~
12
Sp
S.
11
S,
10
S,
,
8
Sd
7
Sg
6
Sb
15
S,
V+
100k
ta
~
RESET
MM57459N
CKI
r
10.1"F
GND
-¥
IN, INo
14 2
06 05 04 03 02 0, Do
18· 19 20 21 22 23 r4
CE C
MC
7
07
17
,
4
2
5
3
6
.°
+
-
=
%
...
8
MR
9
M-
x
M+
KEYBOARD/'"'
Figure 1. Typical Calculator Application
6-19
C DP A E 0 G B
NSA1188 LED DISPLAY
1 2 3 4 5 6 7
F
8
Section 7
EPROMs and
Support Circuits
~National
D Semiconductor
MM271616,384-Bit (2048 x 8) UV Erasable PROM
General Description
Features
The MM2716 is a high speed 16k UV erasable and
electrically reprogrammable EPROM ideally suited for
applications where fast turn-around and pattern experimentation are important requirements.
•
•
2048 x 8 organization
525 mW max active power, 132 mW max standby
power
•
Low power during programming
•
Access time-MM2716, 450 ns; MM2716-1, 350 ns;
MM2716-2, 390 ns
•
Single 5V power supply
the device by following the programming procedure.
•
Inputs and outputs TTL compatible during both
read and program modes
This EPROM is fabricated with the reliable, high volume,
time proven, N-channel silicon gate technology.
• TRI-STATE® output
The MM2716 is packaged in a 24-pin dual-in-line package with transparent lid. The transparent lid allows
the user to expose the chip to ultraviolet light to erase
••
I',
lilt;
Ull tJOllt::lll.
__
.~
____
1\
r"'\
___ . • • . __ ...... _ .•. _ _ _ ._
... 1..- __
I";;;~II
l ' ...... ' .........
j-'Ullvlll
..... UII
L..._
. " ........ __
. _ .... _
" " ' . l ........ ' I l l l V
Block and Connection Diagrams *
Dual-In-Line Package
-+--
14
AJ
VPP+5V
+- VCC+5V
+-- VSS GND
13
AS
AS
11
A4
VPP
DE iGi
A3
10
A1
19 AI0
18
Al
17
AD
V GATING
16
00 (00)
16,384
BIT MATRIX
A8
22 A9
DATA OUTPUTS (PROGRAM INPUTS)
00-07 .1 00- 071
vee
15
0, (011 10
14
01 (01) 11
vss
11
13
EElPGM (EiP)
07 (07)
Dli (06)
Os (OS)
04 (04)
03 (03)
TOP VIEW
Order Number MM2716Q, MM2716Q-1
or MM2716Q-2
See NS Package J24CQ
Pin Connection During Read or Program
Pin Names
PIN NAME/NUMBER
MODE
Read
Program
CE/PGM
(E/P)
18
OE
(G)
20
VPP
VCC
OUTPUTS
21
24
9-11,13-17
VIL
VIL
5
5
DOUT
Pulsed VI L
to VIH
VIH
25
5
DIN
*Symbols in parentheses are proposed industry standard
7-3
AO-A10
00-07 (00-07)
CE/PGM (E/P)
OE ((3)
VPP
VCC
VSS
Address Inputs
Data Outputs
Chip Enable/Program
Output Enable
Read 5V, Program 25V
Power (5V)
Ground
Absolute Maximum Ratings
(Note 1)
-2SoC to +8SoC
-6SoC to +12SoC
Temperature Under Bias
Storage Temperature
All Input or Output Voltages with
Respect to VSS (except VPP)
6V to -0.3V
1.SW
300°C
Power Dissipation
VPP Supply Voltage with Respect
Lead Temperature (Soldering, 10 seconds)
26.SV to -0.3V
to VSS
READ OPERATION (Note 2)
DC Operating Characteristics
TA = oOe to +7oOe, vee = 5V ±5%, (vee = 5V ±10% for MM2716-1),
Vpp = vee ±O.6V (Note 3), VSS = OV, unless otherwise noted.
PARAMETER
SYMBOL
CONDITIONS
Input Curr,ent
VIN = 5.25V or VIN
ILO
Output Leakage Current
VOUT = 5.25V. CE/PGM = 5V
IPPI
VPP Supply Current
VPP = 5.85V
ICCl
VCC Supply Current (Standby)
CE/PGM = VIH. OE = VIL
ICC2
vee Supply Current (Active)
CE/PGM = OE = VI L
VIL
Input Low Voltage
0.1
VIH
Input High Voltage
2.0
VOH
Output High Voltage
10H = 400 pA
VOL
Output Low Vol tage
10L = 2.1 rnA
AC Characteristics
-
TYP
MIN
MAX
= VIL
III
10
--
57
UNITS
10
pA
10
pA
5
rnA
25
rnA
100
rnA
0.8
V
VCC + 1
V
0.45
V
V
2.4
(Note 4)
TA = oOe to +70o e, vee = 5V ±5%, (vee = 5V ±10% for MM2716-1),
Vpp = vee ±O.6V (Note 3), VSS = OV, unless otherwise noted.
SYMBOL
PARAMETER
ALTERNATE
MM2716
CONDITIONS
MIN
= OE = VIL
tACC
TAVOV
Address to Output Delay
CE/PGM
tCE
TELOV
CE to Output Delay
OE
tOE
TGLOV
Output Enable to Output Delay
CE/PGM
= VIL
tDF
TGHOZ
Output Enable High to Output Hi·Z
CE/PGM
= VIL
0
tOH
TAXOX
Address to Output Hold
CE/PGM
= OE = VIL
0
too
TEHOZ
CE to Output Hi·Z
OE
CapaCitance
MM2716-1
MM2716-2
UNITS
STANDARD
= VIL
= VIL
0
MAX
MIN
MAX
MIN
MAX
450
350
390
ns
450
350
390
ns
120
120
120
ns
100
ns
100
0
100
0
100
0
0
100
0
0
ns
100
ns
(Note 5)
T A = 25°e, f = 1 MHz
SYMBOL
PARAMETER
CI
Input Capacitance
CO
Output Capacitance VOUT
CONDITIONS
TYP
MAX
4
6
pF
8
12
pF
VIN ,;OV
= OV
UNITS
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating
temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation,
Note 2: Typical conditions are for operation at: T A
Note 3: VPP may be connected"to
and the program voltage,
= 25° C,
VCC
= SV, VPP
= VCC, and VSS = OV.
vee except during program. The ±O'.6V tolerance allows a circuit to switch VPP between the read voltage
Note 4: Output load: 1 TTL gate and CL
= 100 pF.
Input rise and fall times
Note 5: Capacitance is guaranteed by periodic testing,
7-4
<::: 20
ns.
I
Switching Time Waveforms *
Read Cycle (CE/PGM; VIL)
ADDRESSES
VIH m~~~~-r-----------~
VALID
VIL
___________
~~~~~~
VALID
~
IOH
--(TAXDX)-VIH ~~~~~~~~~~
OUTPUT ENABLE
VIL ------t-----~--..,._------J
1-__
..----i..
-1- 10E
tDF
tACC
(TGLDV)
(TGHDZ)-_ __________~I~·~~===i(T~A~V!D~V)~__~..~------------------~~
VOH
Hi-Z
VALID
OUTPUT
VOL-------------~_ _ _ _ _ _ _ _J
Hi-Z
Read Cycle (OE ; VI L)
VIH
ADDRESSES
VALID
VAllO
VIL
IOH
--(TAXDX)-VIH
CHIP ENABLE
VIL
..
VOH
~
Hi-Z
OUTPUT
tOD
(TEHDZ)
I-ICE
__tA~f_______
(TELDV)
VOL
P
VAllO
Hi-Z
Standby Power Down Mode (OE ; VI L)
VIH~~~~~~~~~~~~~--------------
ADDRESSES
VALID
VALID
VIL~~~~~~~~~~~~~----------------
VIH
CHIP ENABLE
--------1------"1\"-1
VIL===="f
---
VOH====V~A=L~ID==F~OR=====\
OUTPUT
VOL
STANDBY
STANDBY
tOD
(TEHDZ)
Hi-Z
CURRENT ADDRESS
;;;;;;;;;;;;;;;;;;;;;;;;;;;;:;;::;;;;;;;;;;;;;;~
*Symbols in parentheses are proposed industry standard
7-5
VALID FOR
CURRENT ADDRESS
Hi-Z
PROGRAM OPERATION
. DC Electrical Characteristics and Operating Conditions (Notes 1 and 2)
(TA; 25°C±5°C) (VCC; 5V ±5%, VPP;.25V±lV)
SYMBOL
PARAMETER
TYP
MIN
III
Input Leakage Current (Note 3)
VIL
I nput Low Level
-0.1
VIH
Input High Level
2.0
ICC
IPP.1
IPP2
MAX
UNITS
10
Il A
0.8
V
VCC + 1
V
VCC Power Supply Current
100
mA
VPP Supply Current (Note 4)
5
mA
VPP Supply Current During
30
mA
Programming Pulse (Note 5)
AC Characteristics and Operating Conditions
(Notes 1, 2, and 6)
(T A; 25°C ±5°C) (VCC; 5V ±5%, VPP; 25V ±1V)
SYMBOL
ALTERNATE
STANDARD
PARAMETER
MIN
TYP
MAX
UNITS
tAS
TAVPH
Address Setup Time
2
IlS
tos
TGHPH
OE Setup Time
2
IlS
tDS
TDVPH
Data Setup Time
2
IlS
tAH
TPLAX
Address Hold Time
2
IlS
tOH
TPLGX
OE Hold Time
2
IlS
tDH
TPLDX
Data Hold Time
2
IlS
tDF
TGHQZ
Chip Disable to Output Float
0
100
ns
120
ns
55
ms
Delay (Note 4)
tCE
TGLQV
Chip Enable to Output Delay (Note 4)
tpw
TPHPL
Program Pulse Width
45
tpR
TPH1PH2
Program Pulse Rise Time
5
ns
tpF
TPL2PL 1
Program Pulse Fall Time
5
ns
50
Note 1: vee must be applied at thE' same time or before VPP and removed after or at the same time as VPP. To prevent damage to
the device it must not be inserted into a board with power applied.
Note 2: Care must be taken to prevent overshoot of the VPP supply when switching to +25V.
Note
Note
Note
Note
3: 0.45V~ VIN ~ 5.25V.
4: CE/PGM " VI L, VPP " VCC + O.6V.
5: VPP"26V.
6: Transition times::;' 20 ns unless noted otherwise.
7-6
Timing Diagram *
ADDRESSES
Program Mode
VIH ==tr--~----t------,
VIL
DATA
==f-'r-------+-.....,.----{ '1-_ _ __
VIH===\'
VIL===~
GVIH
VIL
----Y---j-t--;;;;;-:-t-"t:-,
E/P VIH - - - - - - - i i ' 2
VIL=====;;;;;;1f
Functional Description
DEVICE OPERATION
The MM2716 has 3 modes of operation in the normal
system environment. These are shown in Table I.
Standby Mode (Power Down)
The MM2716 may be powered down to the standby
mode by making CE/PGM ~ VIH. This is independent of
OE and automatically puts the outputs in their Hi·Z
state. The power is reduced to 25% (132 mW max)
of the normal operating power. VCC and VPP must be
maintained at 5V. Access time at power up remains
either tACC or tCE (see Switching Time Waveforms).
Read Mode
The MM2716 read operation requires that OE ~ VI L,
CE/PGM ~ VIL and that addresses AO-Al0 have been
stabilized. Valid data will appear on the output pins
after tACC, tOE or tCE times (see Switching Time
Waveforms) depending on which is limiting.
Deselect Mode
PROGRAMMING
The MM2716 is deselected by making OE ~ VIH. This
mode is independent of CE/PGM and the condition of
the addresses. The 'outputs are Hi·Z when OE ~ VIH.
This allows OR·tying 2 or more MM2716's for memory
The MM2716' is shipped from National completely
erased. All bits will be' at a "1" level (output high)
in .this initial state and after any full erasure. Table II
snows tne J programming modes .
... ~~ ........ 'oIIV".
TABLE I. OPERATING MODES (VCC ~ VPP ~ 5V)
PIN NAME/NUMBER
MODE
CE/PGM
IE/P)
18
OE
20
9-11.13-17
VIL
VIL
DOUT
Re~d
Deselect
Don't Care
Standby
OUTPUTS
(G)
VIH
VIH
Hi·Z
Don't Care
Hi·Z
TABLE II. PROGRAMMING MODES (VCC = 5V)
PIN NAME/NUMBER
MODE
Program
CE/PGM
IE/P)
18
OE
VPP
OUTPUTS Q
Pulsed VIL
to VIH
VIH
25
21
9-11,13-17
(G)
20
Program Verify
VIL
VIL
25(5)
Program Inhibit
VIL
VIH
25
*Symbols in parent~eses are proposed industry standard
7-7
DIN
DOUT
Hi·Z
Functional Description
(Continued)
Program Mode
The MM2716 is programmed by introducing "O"s into
the desired locations. This is done 8 bits (a byte) at a
time. Any individual address, a sequence of addresses,
or addresses chosen at random maY be programmed.
Any or all of the 8 bits associated with an address
location may be programmed with a single program
pulse applied to the chip enable pin. All input voltage
levels, including the program pulse on chip enable are
TTL compatible. The programming sequence is:
a unit while inhibiting the program pulse to a unit will
keep it from being programmed and keeping DE = V IH
will put its outputs in the Hi-Z state.
ERASING
The MM2716 is erased by exposure to high intensity
ultraviolet light through the transparent window. This
exposure discharges the floating gate to its initial state
through induced photo current. It is recommended
that the MM2716 be kept out of direct sunlight. The
UV content of sunli!lht may cause a partial erasure
of some bits in a relatively short period of time. Direct
sunlight can also cause temporary functional failure.
Extended exposure to room level fluorescent lighting
will also cause erasure. An opaque coating (paint, tape,
label, etc.) should be placed over the package window
if this product is to be operated under these lighting
conditions.
With VPP = 25V, VCC = 5V, DE = VIH and CE/PGM
= VI L, an address is. selected and the desired data
word is applied to the output pins. (VIL = "0" and
VI L = "1" for both address and data.) After the
address and data signals are stable the program pin
is pulsed from VIL to VIH with a pulse width between 45 ms and 55 ms.
Multiple pulses are not needed but will not cause device
damage. No pins should be left open. A high level
(VIH or higher) must nqt be maintained longer than
tpW(MAX) on the program pin during programming.
MM2716's may be programmed in parallel with the
same data in this mode.
.
An ultraviolet source of 2537 A yielding a total integrated dosage of 15 watt-seconds/cm 2 is required.
This will erase the part in approximately 15 to 20
minutes if a UV lamp with a 12,000 p.W/cm 2 power
rating is used. The MM2716 to .be erased should be
placed 1 inch away from the lamp and no filters should
be used.
Program Verify Mode
The programming of the MM2716 may be verified
either 1 word at a time during the programming (as
shown in the timing diagram) or by reading all of the
words out at the end of the programming sequence.
This can be done with VPP = 25V (or 5V) in either case.
An erasure system should be calibrated periodically.
The distance from lamp to unit should be maintained
at 1 inch. The erasure time is increased by the square
of the distance (if the distance is doubled the erasure
time goes up by a factor of 4). Lamps lose intensity
as they age. When a lamp is changed, the distance is
changed, or the lamp is aged, the system should be
checked to make certain full erasure is occurring. Incomplete erasure will cause symptoms that can be
misleading. Programmers, components, and system
designs have been erroneously suspected when incomplete erasure was the basic problem.
Program Inhibit Mode
The program inhibit mode allows programming several
MM2716's simultaneously with different data for each
one by controlling which ones receive the program pulse.
All similar inputs of the MM2716 may be paralleled.
Pulsing the program pin (from VI L to VIH) will program
7-8
PRELIMINARY
~National
D Semiconductor
z
s:
(')
I\)
.....
(')
......
en
NMC27C16 16,384·Bit (2048 x 8) UV Erasable CMOS PROM
Parameter/Part Number
NMC27C16Q·45
NMC27C16Q·55
NMC27C16Q·65
450
550
650
5
5
5
0.1
0.1
0.1
Access Time (ns)
Active Current (rnA)
Standby Current (rnA)
General Description
Features
The NMC27C16 is a high speed 16k UV erasable and
electrically reprogrammable CMOS EPROM ideally suited
for applications where fast turn·around, pattern ex·
perimentation and low power consumption are important
requirements.
• CMOS power consumption
53 mW max active
5.3 mW max standby
• Performance compatible to NSC800 CMOS microproc·
essor and NMC6716 synchronous CMOS EPROM
Ti-~
. I t ....
...
lkA,...r')7,...·II~
'~IWI
..... _ ...... , ....
: ............ I ...... ,.. ... ~
: ......
, ....
'"
t"' ......... n
.....
~
...........
')A
. . . . . . . -,
.... i ....
~ ..... I
.... ' , .............
i .... Ii ... ,..
,"
, . , .....
package with transparent lid. The transparent lid allows
the user to expose the chip to ultraviolet light to erase the
bit pattern. A new pattern can then be written into the
device by following the programming procedure.
This EPROM is fabricated with the reliable, high volume,
time proven, P2 CMOS silicon gate technology.
•
~0~~ v
•
•
•
•
•
Pin compatible to 2716
Access time down to 450 ns
Single 5V power supply
Static-no clocks required
Inputs and outputs TTL compatible during both read
and program modes
8- nr~~ni7.Atinn
• TRI·STATE@ output
Dual·ln·Line Package
Block and Connection Diagrams
A7
. - - - vpp
.--- vee
.--- vss
23 AS
A6
22 A9
A5
DATA OUTPUTS (PROGRAM INPUTS)
II vpp
A4
0 0- 0 7
20 iIT
A3
19 A10
A2
Al
18 CE/PGM
AO
17 07
V GATING
16 Os
0,
01
16,384
BIT MATRIX
02
vss
10
15 0 5
11
12
TOP VIEW
Pin Connection During Read or Program
Pin Names
AO-A1D
Pin Name/Number
Mode
Read
Program
CE/PGM
18
DE
VIL
Pulsed VIL
to VIH
20
VPP
21
VCC
24
Outputs
9-11,13-17
VIL
VIH
5
25
5
5
DOUT
DIN
TRI·STATE~ is a registered trademark of -National Semiconductor Corp.
7-9
0 0-0 7
CE/PGM
BE
VPP
VCC
VSS
Address Inputs
Data Outputs
Chip Enable/Program
Output Enable
Read 5V, Program 25V
5V
Ground
co
,..
()
,....
Absolute Maximum Ratings (Note 1)
N
()
Temperature Under Bias
Storage Temperature
VPP Supply Voltage with Respect
toVSS
Input Voltages with Respect to
VSS (except VPP) (Note 4)
:e
z
-25·Cto +B5·C
-65·Cto + 125·C
26.5V to - 0.3V
Output Voltages with Respect VCC + 0.3V to VSS - 0.3V
toVSS
300·C
Lead Temperature (Soldering, 10 seconds)
VCC + 1 to - 0.3V
READ OPERATION (Note 2)
DC Operating Characteristics TA = o·c to
Symbol
Parameter
~ 70·C, VCC = 5V ± 5%, VSS = OV, unless otherwise noted.
Conditions
Min
Typ
(Note 2)
Max
Units
III
Input Current
VIN = VCC or GND
10
p.A
ILO
Output Leakage Current
VOUT = VCC or VSS (GND)
CEIPGM=VIH
10
p.A
VIL
Input Low Voltage
VIH
Input High Voltage
(Note 4)
VOL1
Output Low Voltage
IOL=2.1 mA
VOH1
Output High Voltage
10H= -400p.A
VOL2
Output Low Voltage
10L=0p.A
VOH2
Output High Voltage
10H =0 p.A
IPP1
VPP Supply Current
VPP=5.25V
ICC1
VCC Supply Current Active
(TTL Levels)
CEIPGM, OE = VIL (Note 5)
Addresses = VIH or VIL
Frequency 1 MHz, 110 = 0 mA
VCC Supply Current Active
(CMOS Levels)
CEIPGM, OE = VIL (Note 5)
Addresses = GND or VCC
Frequency 1 MHz, 110=0 mA
ICCSB1
VCC Supply Current Standby
CEIPGM = VIH (Note 5)
ICCSB2
VCC Supply Current Standby
ICC2
-0.1
2.2
Parameter
Conditions
CI
Input Capacitance
CO
Output Capacitance VOUT=OV
VIN=OV
V
0.45
V
V
2.4
0.1
V
10
p.A
2
10
mA
1
5
mA
1
mA
100
p.A
V
0.1
CEIPGM = VCC (Note 5)
Typ
V
VCC-0.1
Capacitance (Note 3) TA = 25·C, f = 1 MHz
Symbol
0.8
VCC+1
AC Test Conditions
Max Units
4
6
pF
B
12
pF
Input Pulse Levels
Input Rise and Fall Times
Timing
Inputs
Outputs
Reference Levels
Output Load
0.8Vt02.2V
20ns
1Vand2V
0.8Vand2V
1.5V
1 TTL Gate and CL = 100 pF
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. The functional operation of the device at
these or any other conditions beyond those indicated in the "DC/AC Operating Characteristics" tables Is not Implied. Exposure to the absolute maximum
rated conditions for extended periods may affect device reliability.
Note 2: Typical conditions are for operation at: TA= 2S"C, VCC=SV, VPP=VCC, and VSS=OV.
Note 3: CapaCitance Is guaranteed by periodic testing. TA = 2S"C, f = 1 MHz.
Note 4: The inputs (Address, OE, CE) may go above VCC by one volt with no latch up danger. Only the output (data inputs during programming) need be
restricted to VCC + O.3V to VSS - O.3V.
7-10
AC Characteristics TA = o·c to
Symbol
Alternate Standard
+ 70·C, VCC = 5V ± 5%, VSS = OV, unless otherwise noted.
Parameter
=OE =VIL
TAVQV
Address to Output Delay CE/PGM
tCE
TELQV
CE to Output Delay
tOE
TGLQV
Output Enable to Output CE/PGM = VIL
Valid
TGHQZ Output Enable High to
Output Hi·Z
NMC27C16·45
Min
Max
Conditions
OE = VIL
CE/PGM = VIL
tOH
TAXQX
Address to Output Hold CE/PGM
too
TEHQZ
CE to Output Hi·Z
=OE =VIL
OE =VIL
NMC27C16-55 NMC27C16-65 Units
Min
Max
Min
Max
450
550
650
ns
450
550
650
ns
120
120
120
ns
ns
o
100
o
100
o
100
o
o
100
o
o
100
o
o
100
Switching Time Waveforms
Read Cycle (CE/PGM = VIL)
----------,\1
.""""". VIH
;;m;;~;;~;;~;;~~ru'r-fl
,,"""""""" VIL
~/.~~~~~~_ _ _ _""':":":LO:"_____
.f '-___"_"_"'_"__. . . ,.
I1~(TAXnX)~
tOH
OUTPUT ENABLE
~II: ------t----i\I-..__:-:-_____--111
1______
'AC/
'DE
ITGLQV)
'OF
ITGHQZ)--
VOH--~--~~:~.Z-~IT~A~VQ~V~)-~·.r---------i
OUTPUT
VOL-----------------------~~
VALID
_ _ _ _ _ _ __1
Hi·Z
Read Cycle (OE =VIL)
VIH~
AOORESSES ....
~
\/
I}\
VALID
VALID
--------
'OH
~ITAXQX)--VIH
=====:j====\:
VIL
------·--t-------I~-~__:'-----...1
CHIP ENABLE
----
~{T~AJ8v)--OUTPUT VOH ---------cH~i.Zc-
ICE
ITELQV)
'00
ITEHQZI-
VALID
V O L - - - - - - - - - - - - - - - - - ' -_ _ _ _ _ _ _ _- '
Hi·Z
Standby Power· Down Mode (OE = VIL)
VIH===========~f------------
AOORESSES
~
VAllO
VALID
VIL~~~~~~~~~~~f4I-..-------------
VIH
CHIP ENABLE
/
STANDBY
VIL====7
,'00
J--ITEHQZ)
VOH
OUTPUT VOL
1
-------J-------K
___
ICE
--ITELQV)
ACTIVE
STANDBY
'ACC
ITAVQV)-
=~VA~L~10~F~0~R=~I\.}----"H;.:i.Z'----_<1---V-AL-10-FO-R--""'\.
CURRENT AOORESS
l/
CURRENT
AOORESS
' -_
___
_ _---J/
7-11
Hi·Z
ns
ns
CD
o
......
PROGRAM OPERATION
N
()
:!!:
z
DC Electrical Characteristics and Operating Conditions (Notes 5 and 6)
(TA = 25°C ± 5°C) (VCC = 5V ± 5%, VPP = 25V ± 0.5V)
-
Symbol
Parameter
III
Input Leakage Current
VIL
Input Low Level
VIH
Input High Level (Note 4)
ICC
VCC Power Supply Current
IPP1
IPP2
Min
Typ
-0.1
2.2
Max
Units
10
p.A
0.8
V
VCC+1
V
10
mA
VPP Supply Current (Note 7)
10
p.A
VPP Supply Current During
Programming Pulse (Note 6)
30
mA
2
AC Characteristics and Operating Conditions (Notes 1 and 2)
(TA = 25°e ± 5°C) (Vee = 5V ± 5%, VPP = 25V ± 1.0V)
Symbol
Parameter
Min
Typ
Max
Units
tAS
Address Set·up Time
2
,,5
tos
OE Set·up Time
2
tos
Data Set·up Time
2
,,5
,,5
tAH
Address Hold Time
2
1<5
tOH
OE Hold Time
2
,,5
tOH
Data Hold Time
2
p's
tOF
Output Disable to Output TRI·STATE Delay (Note 7)
0
tOE
Output Enable to Output Delay (Note 7)
t pw
Program Pulse Width
45
tpR
Program Pulse Rise Time
5
ns
tpF
Program Pulse Fall Time
5
ns
tvs
VPP Set·Up Time
2
p's
tVH
VPP Hold Time
2
~s
100
50
ns
120
ns
55
ms
vee must be applied at the same time or before VPP and removed after or at the same time as VPP. To prevent damage tethe device it must
not be inserted into a board with power applied.
Note 5:
Note 6: Care must be taken to prevent overshoot of the VPP supply when switching to under 26V max.
Note 7: CEIPGM
=VIL, VPP =VCC.
Note 8: The input timing reference level is 1V for VIL and 2V for VIH.
7-12
z
o
s:
PROGRAM Timing Diagrams
Single Address Programming Followed by a Verify Mode
'---_+-_____ u:;':~' _____I -_ _ _ PR~~~~MM~~WV----I
I-----PRO(;R..
ADDRESS
Multiple Address Programming Followed by a Verify Mode"
PROGRAM· VERIFY
!READ.MODEI
PROGRAM
etlPGM
" All timings are the same as the single address programming mode. A dummy read is required only if the last programmed byte is the first byte to
be verified.
Functional Description
Deselect Mode
The NMC27C16 is deselected by making 6E = VIH. This
mode is independent of CE/PGM and the condition of the
addresses. The outputs are Hi-Z when OE = VIH. This
allows OR-tying 2 or more NMC27C16s for memory
expansion.
DEVICE OPERATION
The NMC27C16 has 3 modes of operation in the normal
system environment. These are shown in Table I.
Read Mode
Standby Mode (Power Down)
The NMC27C16 read operation requires that 6E = VIL,
CElPGM = VIL and that addresses AO-A 10 have been stabilized. Valid data will appearon the output pins aftertACc,
tOE or tCE times (see Switching Time Waveforms) depending on which is limiting.
The NMC27C16 may be powered down to the standby
mode by making CE/PGM = VIH. This is independent of 6E
and automatically puts the outputs in their Hi-Z state.
The power is reduced to 0.4% of the normal operating
power. VCC must be maintained at 5V. Access time at
power up remains either t ACC or tCE (see Switching Time
Waveforms).
.
. TABLE I, OPERATING MODES (VCC = 5V)
Pin Name/Number
Mode
Read
Deselect
Standby
CEIPGM
OE
Outputs
18
20
9-11,13-17
VIL
Don't Care
VIH
VIL
VIH
Don't Care
DOUT
Hi-Z
Hi-Z
PROGRAMMING
The NMC27C16 is shipped from National completely
erased_ All bits will be at a "1" level (output high) in this
initial state and after any full erasure. Table II shows the 3
programming modes.
7-13
~
o
.......
en
Functional Description (Continued)
Program Inhibit Mode
The program inhibit mode allows programming several
NMC27C16s simultaneously with different data for each
one by controlling which ones receive the program pulse.
All similar Inputs of the NMC27C16 may be paralleled.
Pulsing the program pin (from VIL to VIH) will program a
unit while inhibiting the program pulse to a unit will keep it
from being programmed and keeping BE = VIH will put its
outputs in the Hi-Z state.
TABLE II. PROGRAMMING MODES (Vee = 5V)
Pin Name/Number
Mode
Program
Program Verify
Program Inhibit
CE/PGM
OE
VPP
Outputs Q
18
20
21
9-11,13-17
Pulsed VIL
toVIH
VIL
VIL
VIH
25
DIN
VIL
VIH
5
25
DOUT
Hi·Z
ERASING
The NMC27C16 is erased by exposure to high intensity ultraviolet light through the transparent window. This expo·
sure discharges the floating gate to its initial state
through induced photo current. It Is recommended that
the NMC27C16 be kept out of direct sunlight. The UV content of sunlight may cause a partial erasure of some bits in
a relatively short period of time. Direct sunlight can also
cause temporary functional failure. Extended exposure to
room level fluorescent lighting will also cause erasure. An
opaque coating (paint, tape, label, etc.) should be placed
over the package window if this product is to be operated
under these lighting conditions. Covering the window also
reduces ICC due to photodiode currents.
p,rogram Mode
The NMC27C16 is programmed by introducing "O"s Into
the desired locations. This is done 8 bits (a byte) at a time.
Any individual address, a sequence of addresses, or ad·
dresses chosen at random may be programmed. Any or all
of the 8 bits associated with an address location may be
programmed with a single program pulse applied to the
chip enable pin. All input voltage levels, including the pro·
gram pulse on chip enable are TIL compatible. The pro·
gramming sequence is:
With VPP = 25V, VCC = 5V, BE = VIH and CE/PGM = VIL,
an address Is selected and the desired data word Is applied to the output pins. (VIL ="0" and VIL = "1" for both
address and data.) After the address and data signals
are stable the program pin is pulsed from VIL to VIH with
a pulse width between 45 Ins and 55 ms.
An ultraviolet source of 2537A yielding a total integrated
dosage of 15 wall-seconds/cm 2 is required. This w"l erase
the part in approximately 15 to 20 minutes if a UV lamp
with a 12,000 p.W/cm 2 power rating is used. The NMC27C16
to be erased should be placed 1 inch away from the lamp
and no filters should be used.
Multiple pulses are not needed but will not cause device
damage. No pins should be left open. A high level (VIH or
higher) must notbe maintained longer than tpw(MAX) on the
program pin during programming. NMC27C16s may be
programmed in parallel with the same data in this mode.
An erasure system should be calibrated periodically. The
distance from'lamp to unit should be maintained at 1inch.
The erasure time is increased by the square of the dis·
tance (if the distance is doubled the erasure time goes up
by a factor of 4). Lamps lose intensity as they age. When
a lamp is changed, the distance is changed, or the lamp
is aged, the system should be checked to make certain
full erasure is occurring. Incomplete erasure will cause
symptoms that can be misleading. Programmers, components, and system designs have been erroneously suspected when incomplete erasure was the basic problem.
Program Verify Mode
The programming of the NMC27C16 is verified in the pro·
gram verify mode which has VPP at VCC (see Table II).
After programming an address, that same address cannot
be immediately verified without an address change (dum·
my read).
7-14
~National
D Semiconductor
.
MM2758 8192·Bit (1024 x 8) UV Erasable PROM
General Description
Features
The MM2758 is a high speed 8k UV erasable and electrically reprogram mabie EPROM id~ally suited for
applications where fast turn-around and pattern experimentation are important requirements.
•
1024 x 8 organization
•
525 mW max active power, 132 mW max standby
power
•
Low power during programming
The MM2758 is packaged in a 24-pin dual-in·line package with transparent lid. The transparent lid allows
the user to expose the chip to ultraviolet light to erase
•
Access time-450 ns
•
•
Single 5V power supply
Static-no clocks required
!:-:j::":-:::: :::~~ ~~~~'~!~ ~TL
read and program modes
~I-
-
lilt;;
I_:~
.__ ...... _ .. _
UH.
tJU~U:;'II.
__ ••. __ ...... ______ +1- __ h ....... , .. i++n .... i .... +....
" " .... ~v t-' ..... ~ ... II .............................. ,.~~ ..... "
.... _
,,
~
the device by following the programming procedure.
•
This EPROM is fabricated with the reliable, high volume,
time proven, N-channel silicon gate technology.
('''m!"'~tihlp
rillring hoth
TRI-STATE® output
Block and Connection Diagrams *
Dual-In-Line Package
4--
f!-vcc
A7....!.
VPP+5V
+-- VCC+5V
+-- VSS GNO
A6
~A8
2
A5..2.
f!-A9
DATA OUTPUTS (PROGRAM INPUTSI
DO-OJ (OO-OJI
A4..!
~VPP
ttt++t+t
A3..!
~iiEiGI
fiE ((i)--.......rl---r-n-..-TD-n-"-oD-n-o-D'.-.- - - ,
A2
19 ARt
Al
18 EE/PGM (E/PI
AD
lJ OJ (OJI
Y GATING
16 06 (nsl
0 0 (no)
16,384
BIT MATRIX
01 (011
10
15 05 (051
14 04 (041
02 (021 11
vss
12
L..-_ _ _ _- - ' 13 03 (031
Pin Connection During Read or Program
TOP VIEW
Order Number MM2758AO
or MM2758BO
See NS Package J24CO
PIN NAME/NUMBER
MODE
Read
Program
CE/PGM
!EtP)
18
OE
(G)
VPP
VCC
OUTPUTS
20
21
24
9-11,13-17
VIL
VIL
5
5
DOUT
Pulsed VIL
to VIH
VIH
25
5
DIN
*Symbols in parentheses are proposed industry standard
tFor MM2758A AR = VIL for all operating modes
For MM27588 AR = VIH for all operating modes
7-15
Pin Names
AO-Al0
00-07 (00-07)
CE/PGM (E/P)
OE (G)
VPP
VCC
VSS
Address Inputs
Data Outputs
Chip Enable/Program
Output Enable
Read 5V, Program 25V
Power (5V)
Ground
Absolute Maximum Ratings
Temperature Under Bias
Storage Temperature
vpp Supply Voltage with Respect
to VSS
(Note 1)
All Input or Output Voltages with
Respect to VSS (except VPP)
Pow~r Dissipation
Lead Temperature (Soldering, 10 seconds)
-25°C to +B5°C
~5°C to +125°C
2B.5V to -0.3V
BV to -0.3V
1.5W
300°C
READ OPERATION (Note 2)
DC Operating Characteristics
TA = oDe to +7oO e, vee = 5V ±5%,
vpp = vee ±O.6V (Note 3), VSS = OV, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
III
Inp'ut Current
VIN " 5.25V or VIN "VIL
10
I1A
ILO
Output Leakage Current
VOUT" 5.25V. CE/PGM - 5V
10
I1A
IPPI
VPP Supply Current
VPP" 5.85V
ICCI
VCC Supply Current (Standby I
CE/PGM " VIH. OE
CE/PGM •. OE - VIL
-
10
--
ICC2
VCC Supply Current (Activel
VIL
Input Low Voltage
VIH
Input High Voltage
VOH
Output High Voltage
IOH" 400l1 A
VOL
Output Low Voltage
IOL=2.1rnA
AC Characteristics
VIL
57
,
0.1
5
rnA
25
rnA
100
rnA
0.8
2.0
V
Vee' 1
V
0.45
V
2.4
V
(Note 4)
+7o o e,
TA = oDe to
vee = 5V ±5%,
vpp = vee ±O.6V (Note 3), VSS = OV, unless otherwise noted.
SYMBOL'
MM2758
CONDITIONS
PARAMETER
MIN
ALTERNATE STANDARD
.
tACC
TAVQV
Address to Output Delay
CE/PGM = OE = VIL
tCE
TELQV
CE to Output Delay
OE = VIL
tOE
TGLQV
Output Enable to Output Delay
CE/PGM = VIL
tDF
TGHQZ
Output Enable High to Output Hi·Z
CE/PGM= VIL
Address to Output Hold
CE/PGM = OE = VIL
0
CE to Output Hi·Z
OE = VIL
0
tOH
too
TAXQX
TEHQZ
CapaCitance
0
UNITS
MAX
450
ns
450
ns
120
ns
100
ns
ns
100
ns
(Note 5)
TA = 25°e, f= 1 MHz
SYMBOL
PARAMETER
TYP
MAX
CI
IntJut Capacitance
VIN = OV
4
6
pF
CO
Output Capacitance
VOUT = OV
8
12
pF
CONDITIONS
UNITS
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation.
Not. 2: Typical conditions are for operation at: TA = 25°C, VCC = 5V, VPP = VC:C, and VSS = OV.
Not. 3: VPP may be connected to VCC except during program. The ±O.BV tolerance allows a eirc,!it to switch VPP between the read voltage
and the program vOltage.
Not. 4: Output load: 1 TTL gate and CL = 100 pF. Input rise and fall times S. 20 ns.
Nota 5: Capacitance is guaranteed by periodic testing.
7-16
Switching Time Waveforms *
Read Cycle (CE/PGM ~ VI L)
VIH~~~~~~------------------------~
ADDRESSES
VIL~~~~~~
VALID
VALID
________________________- {
IDH
--(TAXUX)-VIH
::::=========t:======~
OUTPUT ENABLE
VIL-----------t--------~----~~------------J
I_..
_--~
.._I-IOE
IDF
(TGLUV)
(TGHUZ)-IACC
_
VOH ____________~:·~~===i(T~A~V~U~V~)-----~.r--------------------1
Hi-Z
OUTPUT
VALID
_________________J
Hi-Z
VOL------------------------~
Read Cycle (OE ~ VIL)
VIH
ADDRESSES
VALID
VALID
VIL
10H
--(TAXUX)-VIH
CHIP ENABLE
VIL
.
VOH
OUTPUT
t
IACC
ITAVUV)------
~..
Hi-Z
VOL
100
ITEHUZ)
(TELUV)
lCE
VALID
P
Hi-Z
Standby Power Down Mode (OE ~ VI L)
ADDRESSES
VIH
CHIP ENABLE
VIL
VOH
OUTPUT
VOL
STANDBY
--
VALID FOR
CURRENT ADDRESS
STANDBY
100
(TEHUZ)
Hi-Z
*Symbols in parentheses are proposed industry standard
7-17
VALID FOR
CURRENT ADDRESS
Hi-Z
PROGRAM OPERATION
DC Electrical Characteristics and Operating Conditions (Notes 1 and 2)
(TA ; 25°C ±5°C) (VCC; 5V ±5%, VPP ; 25V ± 1V)
SYMBOL
PARAMETER
ILl
Input Leakage Current (Note 3)
VIL
I nput Low Level
-0.1
VIH
Inp'ut High Level
io
ICC
VCC Power Supply Current
IPPI
VPP Supply Current (Note 4)
IPP2
VPP Supply Current During
30
mA
MIN
TYP
MAX
UNITS
10
/1A
0.8
V
VCC + 1
V
100
mA
5
mA
Programming Pulse (Note 5)
AC Characteristics and Operating Conditions (Notes I, 2, and 6)
(TA; 25°C ±5°C) (VCC; 5V ±5%, VPP; 25V ±lV)
SYMBOL
ALTERNATE
PARAMETER
STANDARD
MIN
TYP
MAX
UNITS
tAS
TAVPH
Address Setup Time
2
/1S
tos
TGHPH
OE Setup Time
2
/1S
tDS
TDVPH
Data Setup Time
2
!1S
tAH
TPLAX
Address Hold Time
2
/1S
tOH
TPLGX
OE Hold Time
2
/1S
tOH
TPLDX
Data Hold Time
2
/1S
tOF
TGHQZ
Chip Disable to Output Float
a
100
ns
120
ns
55
ms
Delay (Note 4)
tCE
TGLQV
Chip Enable to Output Delay (Note 4)
tpw
TPHPL
Program Pulse Width
45
tpR
TPH1PH2
Program Pulse Rise Time
5
ns
tpF
TPL2PL1
Program Pulse Fall Time
5
ns
50
Note 1: vee must be applied at the same time or before VPP and removed after or at the same time as VPP. To prevent damage to
the device it must not be inserted into a board with power applied.
Note 2: Care must be taken to prevent overshoot of the VPP supply when switching to +25V.
Note 3: 0.45V,::: VIN <: 5.25V.
Note 4: CE/PGM VIL, VPP vee + O.6V.
0
Note 5: VPP o 26V.
Note 6: Transition times
0
S 20 ns unless noted otherwise.
/
7-18
Timing Diagram *
Program Mode
PROGRAM VERIFY
DE '" Vil
VIH
===\-y-------t------"""'\ ..1-----
VIL
==d-}-______!--_____
ADDAESSES
~
VIH===~
DATA
VIL===:(
_ VIH
G
Vil
IOH
'os
__
(TPlDXl~
ITDVPH)
tDS
-(TGHPH)--
VIH
'/P
--------H"
VIL======~
tpA
tpF
ITPLIPLI}
(TPH1PH2)~
Functional Description
..... r-~I.~.- _nr-n ,..TI'-"'I\I
VL- v ..... L.. . . . . . . . . . . . ,..... ...........
Standby Mode (Power Down)
The MM2758 has 3 modes of operation in the normal
system environment. These are shown in Table I.
The MM2758 may be powered down to the standby
mode by making CE/PGM ~ VIH. This is independent of
OE and automatically puts the outputs in their Hi·Z
state. The power is reduced to 25% (132 mW max)
of the normal operating power. VCC and VPP must be
maintained at 5V. Access time at power up remains
either tACC or tCE (see Switching Time Waveforms).
Read Mode
The MM2758 read operation requires that OE ~ VIL,
CE/PGM ~ VI L and that addresses AO-A 10 have been
stabilized. Valid data will appear on the output pins
after tACC, tOE or tCE times (see Switching Time
Waveforms) depending on which is limiting.
Deselect Mode
PROGRAMMING
The MM2758 is shipped from National completely
erased. All bits will be at a "1" level (output high)
in this initial state and after any full erasure. Table II
shows the 3 programming modes.
The MM2758 is deselected by making OE = VIH. This
mode is independent of CE/PGM and the condition of
the addresses. The outputs are Hi·Z when OE = V IH.
ThiC' :::>llnlj\J<:: nR-t\linn ? or mom
MM2716's
for memory
expansion.
TABLE I. OPERATING MODES (VCC
= VPP = 5V)
PIN NAME/NUMBER
'MODE
OUTPUTS
OE
CE/PGM
(E/P)
18
(<3)
20
9-11,13-17
VIL
DOUT
Deselect
Don't Care
VIH
Hi·Z
Standby
VIH
Don't Care
Hi·Z
Read
VIL
TABLE II. PROGRAMMING MODES (VCC = 5V)
PIN NAME/NUMBER
MODE
CE/PGM
(E/P)
18
OE
Pulsed VI L
to VIH
VIH
Program Verify
VIL
VIL
2515)
Program Inhibit
VIL
VIH
25
Program
*Symbols in parenth~ses are proposed industry standard
7-19
VPP
OUTPUTS
21
9-11,13-17
Q
(<3)
20
25
DIN
DOUT
Hi·Z
Functional Description
(Continued)
Program Mode
a unit while inhibiting the program pulse to a unit will
keep it from being programmed and keeping OE = VIH
will put its outputs in the Hi·Z state.
The MM2758 is programmed by introducing "O"s into
the desired locations. This is done 8 bits (a byte) at a
time. Any individual address, a sequence of addresses,
or addresses chosen at random may be programmed.
Any or all of the 8 bits associated with an address
location may be programmed with a single program
pulse applied to the chip enable pin. All input voltage
levels, including the program pulse on chip. enable are
TTL compatible. The programming sequence is:
With VPP
= 25V,
VCC
= 5V, OE = VIH
ERASING
The MM2758 is erased by exposure to high intensity
ultraviolet light through the transparent window. This
exposure discharges the floating gate to its initial state
through induced photo current. It is recommended
that the MM2758 be kept out of direct sunlight. The
UV content of sunlight may cause a partial erasure
of some bits in a relatively short period of time. Direct
sunlight can also cause temporary functional failure.
Extended exposure to room level fluorescent lighting
will also cause erasure. An opaque coating (paint, tape,
label, etc.) should be placed over the package window
if this product is used under these lighting conditions.
and CE/PGM
= VIL, an address is selected and the desired data
word is applied to the output pins. (VI L = "0" and
VIL = "1" for both address and data.) After the
address and data signals are stable the program pin
is pulsed from VIL to VIH with a pulse width be·
tween 45 ms and 55 ms.
Multiple pulses are not needed but will not cause device
damage. No pins should be left open. A high level
(VIH or higher) must not be maintained longer than
tpW(MAX) on the program pin during programming.
MM2758's may be programmed in parallel with the
same data in this mode.
An ultraviolet source of 2537 A yielding a total integrated dosage of 15 watt·seconds!cm 2 is required.
This will erase the part in approximately 15 to 20
minutes if a UV lamp with a 12,000 pW!cm 2 power
rating is used. The MM2758 to be erased should be
placed 1 inch away from the lamp and no filters should
be used.
Program Verify Mode
The programming of the MM2758 may be verified
either 1 word at a time during the programming (as
shown in the timing diagram) or by reading all of the
words out at ,the end of the programming s~quence.
This can be done with VPP = 25V (or 5V) in either case.
An erasure system should be calibrated periodically.
The distance from lamp to unit should be maintained
at 1 inch. The erasure time is increased by the square
of the distance (if the distance is doubled the erasure
time goes up by a factor of 4). Lamps lose intensity
as they age. When a lamp is changed, the distance is
changed, or the lamp is aged, the system should be
checked to make certain full erasure is occurring. Incomplete erasure will cause symptoms that can be
misleading. Programmers, components, and system
designs have been erroneously suspected when incomplete erasure was the basic problem.
Program Inhibit Mode
The program inhibit mode allows programming several
MM2758s' simultaneously with different data for each
one by controlling which ones receive the program pulse.
All similar inputs of the MM2758 may be paralleled.
Pulsing the program pin (from VIL to VIH) will program
7-20
~National
~ Semiconductor
MM54C3731MM74C373 TRI-STATE® Octal D-Type Latch
MM54C3741MM74C374 TRI-STATE® Octal D-Type Flip-Flop
General Description
The MM54C373(MM74C373, MM54C374(MM74C374
are integrated, complementary MaS (CMOS), 8-bit
storage elements with TR I-ST ATE® outputs_ These
outputs have been specially designed to drive highly
capacitive loads, such as one might find when driving
a bus, and to have a fan-out of 1 when driving standard
TTL. When a high logic level is applied to the OUTPUT
DISABLE input, all outputs go to a high impedance
state, regardless of what signals are present at the other
InPUts and tne state oT 1ne sIoraye·eielllt:Ili..~.
the set-up and hold time requirements, is transferred to
the Q outputs on positive-going transitions of the
CLOCK input.
Both the MM54C373(MM74C373 and the MM54C374(
MM74C374 are being assembled in 20-pin dual-in-line
packages with 0_300" pin centers_
Features
'1nll
The MM54C373(MM74C373 is an 8-bit latch_ When
LATCH ENABLE is high the Q outputs will follow the
D inputs_ When LATCH ENABLE goes low, data at the
D inputs, which meets the set-up and hold time requirements, will be retained at the outputs until LATCH
ENABLE returns high again_
1 hll
High noise immunity
Low power consumption
•
TTL compatibility
•
•
•
Bus driving capability
TRI-STATE outputs
Eight storage elements in one package
•
Single CLOCK/LATCH ENABLE and OUTPUT
DISABLE control inputs ,
20-pin dual-in-line package with 0_300" centers takes
half the board space of a 24-pin package
•
The MM54C374(MM74C374 is an 8-bit, D-type, positiveedge triggered flip-flop_ Data at the D inputs, meeting
tn
0.45 VCC typ
•
•
fan-out of 1 driving
standard TTL
Connection Diagrams
Dual-In-Line Package
Dual-In-Line Package
OUTPUT
DISA8LE
OUTPUT
OISABLE
VCC
01
VCC
01
08
08
01-+--t-i
H~--+~08
01-+--H
H---t"'--OB
02-+--t-i
H~--+~07
02-+--t-i
H---t"'--07
02
07
02
07
03
06
03
06
03-+--t-i
H~--+~06
03-+--t-i
H---t"'--06
04-"t---t-i
H~--+"-- os
04 -"t---t-i
H--+'--OS
04
04
os
GNO
os
GNO
CLOCK
TOP VIEW
TOP VIEW
Order Number MM54C373J or MM74C373N
See NS Package J20A or N20A
Order Number MM54C374J or MM74C374N
See NS Package J20A or N20A
7-21
Absolute Maximum Ratings
Voltage at Any Pin
(Note 1)
- 0.3V to VCC
-i-
Package Dissipation
0.3V
Operating Temperature Range
500mW
3V to 15V
Operating VCC Range
MM54C373, MM54C374
-55°C to +125°C
MM74C373, MM74C374
-40° C to +85° C
Storage Temperature Range
-65°C to +150°C
Electrical Characteristics
Absolute Maximum VCC
18V
Lead Temperature (Soldering, 10 seconds)
300°C
Min/max limits apply across temperature range, unless otherwise noted.
CONDITIONS
PARAMETER
MIN
TYP
MAX
UNITS
CMOS TO CMOS
Logical "1" Input Voltage
VIN(l)
Logical "0" Input Voltage
VIN(O)
Logical "1" Output Voltage
VOUT(l)
Logical "0" Output Voltage
VOUT(O)
IIN(1I
Logical" 1" I nput Current
IINIOI
'Logical "0" Input Current
10Z
VCC = 5V
3.5
V
VCC = 10V
8.0
V
VCC = 5V
1.5
V
VCC = 10V
2.0
V
VCC=5V,10=- lO /lA
4.5
VCC = 10V, 10 = -10/lA
9.0
0.5
VCC= 10V, 10= 10/lA
1.0
V
1.0
/lA
0.005
-1.0
VCC = 15V, VIN = OV
Supply Current
-0.005
0.005
VCC = 15V, Vo = 15V
-1.0
VCC = 15V, Vo = OV
ICC
V
VCC= 5V, 10= 10/lA
VCC= 15V, VIN = 15V
TRI·STATE Leakage Current
V
/lA
1.0
-0.005
0.05
VCC = 15V
V
/lA
/lA
300
/lA
CMOS/LPTTL INTERFACE
VINll)
VINIO)
VOUT( 11
VOUT(O)
Logical "1" Input Voltage
Logical "0" Input Voltage
Logical "1" Output Voltage
Logical "0" Output Voltage
54C, VCC = 4.5V
VCC-l.5
74C, VCC = 4.75V
VCC-l.5
V
V
54C, VCC = 4.5V
0.8
V
74C, VCC = 4.75V
0.8
V
54C, VCC = 4.5V, 10 = -360 /lA
VCC-O.4
V
74C, VCC = 4.75V, 10 = -360 /lA
VCC-O.4
V
54C, VCC = 4.5V, 10 = -1.6 rnA
2.4
V
74C, VCC = 4.75V, 10 = -1.6 rnA
2.4
V
54C, VCC = 4.5V, 10 = 1.6 rnA
0.4
V
74C, VCC = 4.75V, 10 = 1.6 rnA
0.4
V
OUTPUT DRIVE
ISOURCE Output Source Current
VCC = 5V, VOUT = OV, T A = 25°C,
-12.0
-24
rnA
-24.0
-48
rnA
6.0
12
rnA
24.0
48
rnA
INote 4)
ISOURCE Output Source Current
VCC = 10V, VOUT = OV, TA = 25°C,
INote 4)
ISINK
Output Sink Current (N-Channel)
VCC = 5V, VOUT = VCC, TA = 25°C,
(Note 4)
ISINK
Output Sink Current (N-Channell
VCC = 10V, VOUT = VCC, TA
= 25°C,
(Note 4)
SWitchi.ng Characteristics
T A = 25°C, CL = 50 pF, tr = tf = 20 ns, unless otherwise specified.
PARAMETER
tpdl, tpdO
CONDITIONS
MIN
TYP
MAX
UNITS
Propagation Delay, LATCH ENAB LE
VCC- 5V, CL - 50pF
165
330
ns
to Output
VCC = 10V, CL = 50 pF
70
140
ns
VCC= 5V, CL = 150 pF
195
390
ns
VCC = 10V, CL = 150 pF
85
170
ns
MM54C373, MM74C373
7-22
Switching Characteristics
(Continued)
T A: 25°C, CL: 50 pF, tr: tf: 20 ns, unless otherwise specified.
PARAMETER
tpd1. tpdO
tpWH
TYP
MAX
UNITS
LATCH ENABLE = VCC
Output
VCC=5V, CL = 50pF
155
310
ns
VCC = 10V, CL = 50 pF
70
140
ns
Propagation Delay CLOCK.to Output
MM54C374/MM74C374
tSET·UP
MIN
Propagation Delay Data In to
MM54C373, MM74C373
tpdl, tpdO
CONDITIONS
VCC = 5V, CL = 150 pF
185
370
ns
VCC = 10V, CL = 150 pF
85
170
ns
VCC = 5V, CL = 50 pF
150
300
ns
VCC = 10V, CL = 50 pF
65
130
ns
VCC = 5V, CL = 150 pf
180
360
ns
VCC = 10V, CL = 150 pF
80
160
ns
Minimum Set·Up Time Data In to
tHOLD = 0 ns
CLOCK/LATCH ENABLE
VCC= 5V
70
140
ns
VCC= 10V
35
70
ns
Minimum LATCH ENABLE Pulse
VCC= 5V
75
150
ns
Width
VCC= 10V
55
110
ns
VCC= 5V
70
140
ns
Vee = 10V
50
100
MM54C373, MM74C373
tpWH, tPWL Minimum CLOCK Pulse Width
MM54C374, MM74C374
fMAX
ns
Maximum LATCH ENABLE
VCC = 5V
3.3
6.7
MHz
Frequency
VCC= 10V
4.5
9.0
MHz
VCC= 5V
3.5
7.0
MHz
VCC= 10V
5.0
10.0
MHz
MM54C373, MM74C373
fMAX
Maximum CLOCK Frequency
MM54C374, MM74C374
tlH, tOH
tHl, tHO
Propagation Delay OUTPUT
R L = 10k, CL = 5 pF
DISABLE to. High Impedance
VCC = 5V
105
210
ns
State (From a Logic Level)
VCC= 10V
60
120
ns
Propagation Delay OUTPUT
RL = 10k, CL = 50 pF
DISABLE to Logic Level (From
VCC= 5V
105
210
ns
High Impedance State)
VCC= 10V
45
90
ns
VCC= 5V, CL = 50pF
65
130
ns
V('(' = 10V. CI = 50 of
35
70
ns
ns
lTHL. tTLH Transition Time
t r, tf
VCC = 5V, CL = 150 pF
110
220
VCC= 10V,CL= 150pF
70
140
Maximum LATCH ENABLE Rise
VCC= 5V
NA
/ls
and Fall Time
VCC= 10V
NA
/ls
ns
MM54C373, MM74C373
t r, tf
Maximum CLOCK Rise and Fall Time
MM54C374, MM74C374
CCLK, CLE Input Capacitance
COD
I nput Capacitance
VCC = 5V
15
>2000
/ls
VCC= 10V
5
>2000
/ls
CLOCK/LE Input, (Note 2)
7.5
10
pF
OUTPUT DISABLE Input,(Note 2)
7.5
10
pF
CIN
Input Capacitance
Any Other Input,(Note 2)
5,0
7.5
pF
COUT
Output Capacitance
High Impedance State, (Note 2)
10
15
pF
CPO
Power Dissipation Capacitance
Per Package, (Note 3)
200
pF
Per Package, (Note 3)
250
pF
MM54C373, MM74C373
CPO
Power Dissipation Capacitance
MM54C374, MM74C374
Note 1; "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating
Range" they are· not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics" provides
conditions for actual device operation.
Note 2: Capacitance is guaranteed by r:>eriodic testing.
Note 3: CpO determines the no load ac power consumption of any CMOS device. For complete explanation see 54C/74C Family Characteristics
application note, AN-SO.
'
Note 4: These are peak output curren~ capabilities. Continuous output current is rated at 12 rnA max.
7-23
Typical Performance Characteristics
MM54C373/MM74C373
Propagation Delay, LATCH
ENABLE to Output vs Load
Capacitance
300
g 100
]
>
Q
Q
;;:
'"go
VCC '10V
I
s-'"
Q
VICC"5V
0
0
100
s0
50
100
150
CL - LOAO CAPACITANCE IpF)
~ 0.75
g
w
u
z
0.5
:; 0.15
~
'"w
~
Vc~'
10V
s-'"
0
0
5
10
15
Vcc - POWER SUPPLY VOLTAGE IVI
0
100
150
50
CL - LOAD CAPACITANCE IpFI
MM54C373/MM74C373,
MM54C374/MM74C374
Output Sink Current vs VOUT
100
90
80
70
60
.!
'"z 50
~ 40
30
10
10
0
VCc,'0V
I
1
0
vCC' 5V
;=
;;
;;:
100
~
-+VCC"5V
0
150
50
100
CL - LOAD CAPACITANCE IpF)
MM54C373/MM74C373,
MM54C374/MM74C374 Output
Source Current vs VCC - VOUT
0
-10
-10
-30
.!
w
u -40
VCC ·15V
"
;'"
~ 100
VCC' 5V
";=0
~
MM54C373/MM74C373
Propagation Delay, Data In to Output
vs Load Capacitance
300
~
!>
";;:'"
TA = 25°C
I
VCC' 5Vt'~
"
VCC-l0V
!5
~
VCC' 5V
,
VICC"0V
-50
i-"
-60
Vci
-70
-80
16 14 11 10 8 6 4 1
vcc - VOUT IV)
I
IL
0 1 4 6 8 10 11 14 16
VOUTIVI
0
Truth Tables
MM54C374/MM74C374
MM54C373/MM74C373
OUTPUT LATCH
DISABLE ENABLE
L
H
L
H
D
Q
H
L
H
L
L
L
X
Q
H
X
X
Hi-Z'
OUTPUT
DISABLE
L
CLOCK
D
Q
~
H
L
H
L
~
L
X
Q
L
L
H
X
Q
H
X
X
Hi-Z
L
L
= low logic level
H
=
high logic level
X = irrelevant
~= low to high logic level transition
Q = preexisting output level
Hi-Z = high j'mpedance output state
Typical Applications
Data Bus Interfacing Element
Simple, Latching, Octal, LED Indicator Driver with Blanking
For Use As Data Display, Bus Monitor,
pP Front Panel Display, Etc.
0----,
BLANKtNO
CONTROL
~
TRI-STATE
~
MMS4C373/
MM74C313
OR
MM54C374!
MM74C374
""-r--
DATA BUS
I
~7
MM54CJ7JI
MM74C373
OR
MM54C374/
MM74CJ74
-.(7
~
1~-
IN
.m
_
-
-
PERIPHERAL DEVICE
ClOCKING/LATCHIN~
CONTROL
7-24
DI
00
Vy'
Vec
02
.,
.2
OJ
04
MMS4CJ13!
MM7ri~J73
05
06
MM54C374/
MM74CJ74
01
.4
.,
.S
.6
-
08 eLK/IT GND
o---J
.3
J
.8
::M:
iM~M:M:~M
Logic Diagrams
s::
s::
MM54C373/MM74C373 (1 of 8 Latches)
(J1
~
(')
Vee
(A)
-ss::::
'-I
(A)
~
(')
(A)
'-I
JIl
s::
s::
(J1
~
(')
~
D
OUTPUT
DISABLE
(A)
00
-ss::::
~
MM54C374/MM74C374 (1 of 8 Flip-Flops)
i
Vee
eL
-L....
---t>o--4>J
0
OUTPUT
DISABLE
-1iI--,--
00
Ci
eL
T
TRI·STATE® Test Circuits and Timing Diagrams
t1H, tH1
Vee
OUTPUT
DISABLE
Ij
-----J/
tOH-1
50 %
-=
tOH, tHO
tHO, CL = 50 pF
vee
vee
10k
OUTPUT Vee - - -i-::::gD,,,"r.- - DISABLE
OUTPUT
DISABLE
50%
10%
GNO
-=
~
tOH
eL
"J"
Vee
OUTPU~
~~
10%
VOL
7-25
'
~
~
.;-)
(A)
~
Switching Time Waveforms
MM54C373/MM74C373
DATA
IN
GNO
VCC --~:';"';';""'-f-"'\
GND----4-----+----~--J
n
OUTPUT
GNO
MM54C374/MM74C374
OUTPUT DISABLE
= GND
DATA
IN
GNO
CLOCK
GNO---~I
VCC------'-----~.i:"::=----"";,,i.1
n
OUTPUT
GNO---......::~
OUTPUT DISABLE = GND
7-26
~National
~ Semiconductor
DM54LS373/DM74LS373, DM54LS3741DM74LS374
Octal D-Type Transparent Latches
and Edge-Triggered Flip-Flops
General Description
These a·bit registers feature totem·pole TR I·STATE®
outputs designed specifically for driving highly·capacitive
or relatively low impedance loads. The high impedance
TR I·ST ATE and increased high logic level drive provide
these registers with the capability of being connected
directly to and driving the bus lines in a bus·organized
system without need for interface or pull·up com·
ponents. They are particularly attractive for imple·
menting buffer registers, I/O ports, bidirectional bus
drivers, and working registers.
The a latches of the DM54LS373 are transparent D·
type latches meaning that while the enable (G) is high
the Q outputs will follow the data (D) inputs. When
the enable is taken low the output will be latched
at the level of the data that was set up.
The a flip·flops of the DM54LS374/DM74LS374 are
edge·triggered D-type flip-flops. On the positive transition
of the clock, the Q outputs will be set to the logic states
that were set up at the D inputs.
A buffered output control input can be used to place
the a outputs in either a normal logic state (high or low
logic levels) or a high impedance state. In the high
impedance state the outputs neither load nor drive the
bus lines significantly.
The output control does not affect the internal operation
of the latches or flip-flops. That is, .the old data can be
retained or new data can be entered even while the
outputs are OFF.
Features
•
Choice of a latches or aD-type flip·flops in a single
package
• TR I-STATE bus driving outputs
• Full parallel access for loading
• Buffered control inputs
• PNP inputs reduce DC loading on data lines
Connection Diagrams and Truth Tables
DM54LS374/DM74LS374
Dual-In-line Package
DM54LS373/DM74LS373
Dual-In-Line Package
vee
20
t:11I~I:iLt
U8
19
08
07
17
18
U7
U6
16
06
15
14
05
13
US
12
G
11
VCC
20
U8
19
08
18
07
17
U7
U6
16
15
06
05
14
13
U5
12
CLOCK
11
10
OUTPUT
CONTROL
Ul
01
02
U2
U3
03
TOP VIEW
ENABLE
G
D
OUTPUT
H
H
H
H
L
L
L
X
00
04
U4
GNO
OUTPUT
CONTROL
at
01
02
02
03
04
03
TOP VIEW
CLOCK
t
t
D
OUTPUT
H
H
L
L
L
X
00
When output control is high, the output is disabled to high impedance state; however, sequehtial
operation of these devices are not affected.
7-27
U4
GNO
Recommended Operating Conditions
Absolute Maximum Ratings
7V
7V
7V
Supply Voltage (Note 11
Input Voltage
OFF-State Output Voltage
Supply Voltage (VCCI
DM54LS373, DM54LS374
DM74LS373, DM74LS374
Operating Temperature Range
MIN
MAX
UNITS
4,5
4.75
5.5
5.25
V
V
5.5
V
High Level Output Voltage (VOHI
DM54LS373, DM54LS374
DM74LS373, DM74LS374
-55°C to +125°C
O°C to +70°C
-65°C to +150°C
Storage Temperature Range
High Level Output Current IIOHI
DM54LS373, DM54LS374
DM74LS373, DM74LS374
-1
-2.6
rnA
rnA
Width of Clock/Enable Pulse (twl
High
Low
15
15
ns
ns
Data Set-Up Time (tsu I
DM54LS373/DM74LS373
DM54LS374/DM74LS374
01
20t
ns
ns
Data Hold Time (tHI
DM54LS373/DM74LS373
DM54LS374/DM74LS374
151
5t
ns
ns
Temperature (TAl
DM54LS373, DM54LS374
DM74LS373, DM74LS374
-55
0
°c
°c
+125
+70
The arrow indicates the transition of the clock/enable input
used for reference: t for the low-to-high transition; I for the
high-ta-Iow transition.
Electrical Characteristics
Over recommended operating free-air temperature range (unless otherwise noted)
DM54lS373,
DM54lS374
TYP
MIN (Note 31 MAX
CONDITIONS
(Note 21
PARAMETER
2
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
VIK
Input Clamp Voltage
Vee = Min, 11= -18 rnA
VOH
High Level Output Voltage
VCC ='Min, VIH = 2V, VIL = VIL(MAXI,
10H = Max
VOL
Low Level Output Voltage
Vee = Min, VIH = 2V,
VIL = VIL(MAXI
IOZH
OFF State Output Current,
High Level Voltage Applied
10Zl
OFF State Output Current,
Low Level Voltage ,Applied
2.4
I IOL = 12 rnA
I 10L - 24 rnA
DM74lS373,
DM74lS374
TYP
MIN (Note 3) MAX
V
2
0.7
0.8
V
-1.5
-1.5
V
3.4
0.25
UNITS
2.4
0.25
0.35
0.4
V
3.1
0.4
0.5
V
V
Vee = Max, VIH = 2V, Va = 2.7V
20
20
IlA
Vee = Max, VIH = 2V, Va = O.4V
-20
-20
"A
0.1
0.1
rnA
II
Input Cur'rent at Maximum
Input Voltage
Vee = Max, VI = 7V
IIH
High Level Input Current
Vee = Max, VI = 2.7V
20
20
"A
IlL
Low Level Input Current
Vee = Max, VI = O.4V
-0.4
-0.4
rnA
lOS
Short Circuit Output Current
-130
rnA
lee
Supply Current
24
40
27
45
rnA
rnA
(Note 41
-30
Vee = Max
Vee = Max, Output
Control at 4.5V
I DM54LS373/DM74LS373
I DM54LS374/DM74LS374
7-28
-130
24
27
40
45
-30
Switching Characteristics
PARAMETER
fMAX
Maximum Clock Frequency
tPLH
Propagation Delay Time,
Low-ta-High Level Output
tpHL
Propagation Delay Time,
High-to-Low Level Output
tPLH
Propagation Delay Time,
LOW-la-High Level Output
tpHL
Propagation Delay Time,
High-ta-Low Level Output
tPZH
Output Enable Time to
High Level
tPZL
Output Enable Time to
Low Level
tpHZ
Output Disable Time from
High level
1"\ .... _ ....
'(" L..L..
~~'I"'''''
VCC~5V,TA~25°C
FROM
INPUT
TO
OUTPUT
1"'\:._1...'_
"'T"' __
.................... ,,'"
L
• _.
"VIO'
DM54LS374!
DM74LS374
MIN
TVP
MAX
35
Data
Any Q
Data
Any Q
CL
= 45 pF,
RL
MHz
50
12
18
ns
12
18
ns
20
30
16
28
ns
= 667S1,
Any Q
Clock or Enable
Any Q
18
30
22
34
ns
Output Control
Any Q
15
28
16
28
ns
Output Control
Any Q
22
36
22
28
ns
Output Control
Any Q
12
20
10
18
ns
15
25
INotes 5 and 6)
= 5pF,
Any Q
= 667S1,
j "'-,,"'
".-.-
Output Control
RL
-I
I I I
14
24
Note 1: Voltage values are with respect to network ground terminal.
Note 2. For conditions shown as min or max, use the appropriate value specified under recommended operating conditions.
Note 3: All typical values are at V CC '= 5V, T A = 25° C.
Note 4: Not more than one output should be shorted at a time and duration of the short circuit should not exceed one second.
Note 5: Maximum clock frequency is tested with all outputs loaded.
Note 6: See load circuits and waveforms.
Logic Diagrams
DM54LS373/DM74LS373
Transparent Latches
OUTPUT
CONTROL
111
(3)
01
UNITS
Clock or Enable
CL
Low Level
DM54LS373!
DM74LS373
MIN
TVP
MAX
CONDITIONS
~
DM54LS374/DM74LS374
Positive-Edge-Triggered Flip-Flops
OUTPUT
CONTROL
(1)
(3)
01
Q1
~
01
(4)
02
02
02
03
03
111
03
03
(8)
04
04
04
04
(131
05
05
05
06
(141
06
06
(111
07
07
07
08
CLOCK
7-29
(18)
ns
Schematic Diagrams
DM54LS373/DM74LS373
Equivalent of Data, Enable, and
Output Control Inputs
'
Typical of All Outputs
--------4~-vcc
vcc------------~
INPUT~t_-. .t_~..
OUTPUT
Data: Aeq = 20 kl1 typ
Output control: Aeq = 18 kl1
DM54LS374/DM74LS374
Equ ivalent of Data Inputs
, Equivalent of Output
Control Clock Inputs
Vcc-~---_""-
V C C - - - - - 4..
30k TYP
INPUT -.;...-
-+--
.......
INPUT ~t--"I---"
Typical of All Outputs
-------4.....-
VCC
OUTPUT
7-30
Section 8
Development Systems
and User's Manuals
8
.I
n
o"tJ
~National
~
~ Semiconductor
"tJ
COP400-PDS Product Development System
C
en
General Description
Features
a
a.
A single development tool which supports microcontroller development activities through every phase from concept to production, the COP400 Product Development
System is built around a powerful 16-bit microcomputer
to allow rapid execution of sophisticated, efficient utilities. The sytem meets the total product development
need. An editor and assembler are provided to handle
source code entry, conversion to object code, and maintenance of documentation. The emulator card attachment allows object code to be executed under the careful
control of the COPMON debug utility. A cable can be
connected from the PDS to the final product; in this
~0r:t~. tht:' f~!! r.:a~'..A_"?r ~r!~ ,!~!,,~:!!!!!!~I ,::,f the PDS !~ '?~
tended to the product-ta-be for real time emulation during
development. When a program is complete and ready to
be committed to production, the PDS generates a transmittal disc that NSC will use to assure accurate masking
of the final components. The usefulness of the PDS
does not end there: a fixture is available for the incoming
functional test of the ROM programmed COP400 devices.
Thus, the COP400-PDS actively supports every step of
a microcontroller product development activity.
• Supports the entire COP400 and COP300 microcontroller fam i1y
!l
"tJ
• A total concept-to-production tool
• Low cost
• 32k bytes RIW memory
• 12k bytes PROM (firmware)
• Disk-based
• Macro·assembler
•
H:)-c
CI)
E
c..
0
Q)
>
-...
CI)
C
0
:::I
't:J
0
Q.
C
C
'o:t
Q.
0
()
8-8
0
0
"'tI
~
0
0
...."'tI
0
Co
C
(')
Section
Description
12.1
12.2
12.3
12.4
12.5
12.6
12.7
12.8
12.9
12.10
12.11
12.12
Introduction ................................................... .
ALTER DATA BUFFER Command .................................. .
BASE Command ................................................ .
CHIP Command ................................................ .
COMPARE Command ............................................ .
DEPOSIT Command .. ~ .......................................... .
DUMP Command ............................................... .
ERASE Command ............................................... .
HELP Command ........... '..................................... .
LIST Command .. , ............................... , .......... , .... .
LOAD Command ., ....... ; .... , ....... , ..... , .............. , .... .
PROGRAM Command ........................................... .
Page
Chapter 12. COP400 PDS PROM Programmer (PROG)
8-101
8-101
8-101
8-101
8-101
8-101
8-102
8-102
8-102
8-102
8-102
8-102
Sample·Program .................................. , .... , ....... ,. 8-104
Page
Figure
Illustrations
1-1
PDS as Shipped from the Factory , ... , ............................. , 8-12
1-2
PDS Front Panel .' , . : ........................................... . 8-12
1~3
PDS Rear Panel. , ...................... , ..... , ................ , .. 8-12
1-4
PDS Rear Panel Connectors ....................... '.' , ............ . 8-12
1-5
PDS In·System Emulation System .................... , ....... , . , . , . 8-14
2-1
Inserting a Diskette into the Drive ................... , .... , . , ... , . , .. 8-18
.
&:::_1
""",np""+;"""""'!I1 Q: ...... "' .. ,.....,. ... ot'Io ",f nlCLt" I:'nlT lAnnl:
5-2
6-1
6-2
9-1
DISK EDIT MODE Edit Window Operator ...... , ..................... .
DSPLY.SRCSourceCode ......... , ...... , .......... , ... , ........ .
DSPLY. SRC Assembly Output Listing, ..... '... , ......... , , . , , . , .... .
Typical Cross Reference Listing .................. , . , .... ,. , ....... .
,
8-9
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8-73
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Table
Tables
Page
1-1
Recommended Peripheral Devices ........ i ......................... 8-13
1-2
Edge Connector Assignments ........... . f. • • • • • • . • • • • • • . • • • . . • • • • •• 8-15
2-1
TTY Connector(Current Loop). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-17
2-2
Printer and CRT Connectors (RS232) ................................ 8-17
2-3
PDS'System Program Names and Prompts ........................... 8-19
2-4
PDS Console Input Control Characters .............................. 8-20
2-5
System Default M/odifiers ......................................... 8-20
2-6
PDS Internal File;Types .......................................... . 8-20
2-7
Protection Levels and Safeguard Provisions ......................... . 8-21
2-8
Disk File Error Messages ......' ................................... . 8-22
2-9
PDS Device N~mes .............................................. . 8-22
2-10 Syste,m Commands .............................................. 8-23
2-11 Operand Parameters ............................................. 8-23
3-1
File Manager Command Summary ............... '. . . . . . . . . . . . . . . . . .. 8-26
4-1
DSKIT Command Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-27
4-2
Command Parameter Description ............... '................... 8-27
DSKITCommand Option Description ................................ 8-28
4-3
5-1
Editor Commands ............ : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-40
5-2
Command Format Definitions .. i. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-41
5-3
Error Messages .............. ;. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-42
Edit Command Control Characters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-43
5-4
6-1
ASM Arithmetic and Logical Operators ........... ',' . . . . . . . . . . . . . . . .. 8-48
6-2
COP400 Instruction Set .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-51
6-3
COP400 Instruction SetTable Symbols .............................. 8-54
6-4
Alphabetical Mnemonic Index of COP400 Instructions ................. 8-54
6-5
Table of COP400 Instructions Listed by OP Codes (Hexadecimal) . . . . . . . .. 8-55
Summary of Assembler Directives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-57
6-6
6-7
List Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-57
6-8
ASCII Character Set in Hexadecimal Representation ........... : . . . . . .. 8-58
Display Digit Segments ................. ' ........................ ' 8-59
6-9
7-1
Valid Chip Numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-81
7-2
Summary of COPMON Console Commands ......................... ' 8-87
7-3
Operand Syntax ...................................... '. . . . . . . . . .. 8-88
7-4
GO Operation Summary ................................. : . . . . . . . .. 8-89
8-1
Summary of List Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-90
10-1 MASKTR Command Summary ............ , ............... , . . . . . . . .. 8-97
12-1 PROM Programmer Command Summary ............................. 8-101
12-2 Summary of PROG Operands .............. ,." .......... , ......... 8-103
8-10
o
Introduction and Overview
1.1 General Description
The COP400 Product Development System (PDS) is designed to aid in the development of products using
National Semiconductor's COP400 Microprocessor
series_
The PDS is a disk-oriented system. It is capable of creating and acceSSing data and program files stored on
a floppy diskette. This allows fast and easy access to
system software, rapid access to program files, and a
convenient way to provide National Semiconductor
with program data for the mask-making process.
The PDS provides for debugging of the COP400 device.
Debugging uses hardware and software to single-step
through a COP400 program, breakpoint on an address,
trace program execution, and dump out Internal COP400
registers. This feature speeds up the development cycle.
The user interacts with the PDS via a system console
sucn as a teletype or l,;H I. An optional printer can De
attached to obtain p'rogram listings quickly. The PDS
front panel allows the user to perform specific development functions without a system console. Connectors
on the rear panel of PDS can be connected to an emulator board, which emulates a COP400 chip in the user's
system. A PROM programmer on the PDS front panel
allows the emulator board to be portable, for emulation
in the final environment of the user's system.
The following sections provide an overview of the
COP400 PDS Hardware; COP400 PDS Software, and
Emulation and Debugging.
1.2 Hardware Overview
This section provides a general description of the PDS
hardware consisting of the following: I
-
-
rlVll1. allY nl:l'QI
On the left side of the PDS front panel is the floppy
disk drive door. The door latches are closed and opened with the rectangular button to the left of it. In the
center of the button is an indicator light which lights
when the drive Is in use.
The PDS rear panel is shown in Figure 1-3. On each
side there is a cooling fan filter screen. Below the left
screen is a fuse holder and a plug for the power cable.
Above this screen are six connectors used to connect
peripheral devices to PDS.
1.2.2 Peripheral Devices
Peripheral devices provide user interface with the PDS.
A console is required for entering commands. A console may be a CRT or TTY, i.e., any device with an RS232 or a current loop inteface. A printer for producing hard copy output is required when using a CRT,
ana optional woen uSing a I I Y. A r I Y provlaes its own
hard copy output. An emulator board is required for
user's system emulation. Emulator Boards are discussed in the In-System Emulator Boards Manual\ Publication No. 420306469.
~
There are six connectors on the PDS rear pan I used to
connect peripheral devices to the PDS, see Fi ure 1-4
for a close~up view. TTY is a 9-pin connector f r
teletype or other current loop device connecti n. CRT
is a standard 25-pin RS232 connector for a CRT or
other RS232 device. PRINTER is a standard 25-pin
RS232 connector used to connect a printer to:the PDS.
The console device (CRT or TTY) may operate at one of
the following baud rates: 110, 150, 300, 600, 1200, 2400,
4800 or 9600. The user can set EVEN or NO parity, and
carriage return and line feed delays from 0 to 1000ms
-
rC;UIOI~
• Peripheral Devices
Figure 1-1 shows the PDS as shipped from the factory.
1.2_1 Front and Rear Panels
The PDS front panel Is shown in Figure 1-2. The switch
in the lower right corner is the power switch. To the left
of the power switch are five switches. Two switches, labeled PROGRAM LOAD, are used to load and execute
the COP Monitor discussed in Chapter 7. A third
switch, labeled DIAG, Is for a diagnostic test on the
PDS Internal memory and the disk drive_ A fourth
switch, labeled INIT, is for PDS system initialization. A
fifth switch, labeled AUX, is a spare, not currently used
by the PDS. The five switches are discussed In more
detail inChapter 2.
the various allowable baud rates are as follows:
110 Baud:
8-bit data (No Parity - PDS resets bit 8 = 0),
2 Stop bits, Full Duplex operation
150-9600 Baud: .
8-bit data (No Parity - PDS resets bit 8 = 0),
1 Stop bit, Full Duplex operation; or 7-bit data,
Even Parity, 1 Stop bit, Full Duplex operation.
If the console uses a current loop interface, PDS will
assume a 110 Baud rate with the set-up as shown above.
The printer device must meet the same requirements
listed above for a console. The user can set EVEN or
NO parity, and carriage return, line feed, form feed, and
vertical tab delays from 0 to 1000ms for the printer.
Table 1-1 lists some typical peripheral devices.
In the center of the PDS front panel is a quick-release
socket that is used for programming MM2758, MM2716,
MM2732, MM2724 EPROMs.
8-11
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Figure 1-1. PDS as Shipped from the Factory
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Figure 1-2. PDS Front Panel
RS232P~INTER
IELETYpt C!lNSOLE
CONNECTOR
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Figure 1-3. PDS Rear Panel
CONNECTOR
If[MAtEl
13
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14
9000001
25
.
EMULATOR I
COPEM~LATOR
COItN£C1l11l1
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COP EMULATOR
CONNECTOR 2
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Figure 1-4. PDS Rear Panel Connectors
8-12
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1.3 COP400 PDS Software Overview
1.3.2 File Manager Program (FM)
PDS software is divided into two parts:
The File Manager (FM) is a PDS system program that
provides an inteface to disk files. FM enables the user
to copy files, delete and undelete files, list the disk
directory, duplicate disks, list file size and type, list
space available on a disk, list and change the disk
name and perform various other functions. The File
Manager Program is described in Chapter 3.
• Firmware in ROM
• Software on disk
The firmware contains general routines for console and
printer configuration, system initialization, diagnostics,
and program loading. The user invokes a general rou·
tine by entering a command name at the console or by
pressi ng one of the five switches on the PDS front panel.
1.3.3 Disk Initialization and Test Program (DSKIT)
The Disk Initialization and Test Program is a PDS
system program that initializes new disks. Initializa·
tion consists of writing sector sync marks on each
sector, writing and verifying a test pattern on each sec·
tor, writing the volume name and header onto the disk,
and create an empty directory. The Disk Initialization
and Test Program is described in Chapter 4.
The software contains the programs for file editing,
assembly, debugging, and PROM programming. The
PDS Programs are interactive programs. The user in·
vokes the program by entering the program name at the
console, followed by a carriage return. The system
responds with a message and prompts for user·entered
commands. Each program has several commands.
1.3.4 Text File Editor (EDIn
This section gives an overview of the following
COP400 commands and programs:
The Text File Editor (EDIT) is a system program which
creates or changes text files. The Text File Editor can
insert. delete. alter. and list program text as well as
write the text to a floppy disk. EDIT can accept source
from either disk files or console entry. The Text File
Editor is described in Chapter 5.
• System Configuration and Diagnostic Commands
• File Manager Program (PM)
• Disk Initialization and Test Program (DSKIT)
• Text File Editor (EDIT)
• COP Cross·Assembler (ASM)
• COPSTM Monitor and Debugger (COPMON)
1.3.5 COPS Cross·Assembler (ASM)
The COPS Cross·Assembler (ASM) is a PDS system
program which translates symbolic program files (cre·
ated with the Text File Editor) into object code files con·
taining program instruction in machine language. The
COPS Cross·Assembler also generates output listings
containing source statements, corresponding machine
code and memory locations, and error messages. The
COPS Cross·Assembler is described in Chapter 6.
• File List Program (LIST)
• Cross Reference Program (XREF)
• Mask Transmittal Program (MASKTR)
• Memory Diagnostic (MDIAG)
• PROM Programmer (PROG)
1.3.1 System Configuration and
Diagnostic Commands
1.3.6 COPS Monitor and Debugger (COPMON)
The system configuration commands are used to con·
figure the console. The diagnostic command performs a
The COPS Monitor and Debugger (COPMON) is a PDS
system program which can monitor the execution of
snOrl olagnosllc rOUllnt::t on Ult::l HlltH I li;:tl IlItHllury dliU lilt::
programs.
disk drive. The System Configuration commands and
the Diagnostics are described in Chapter 2.
tracing and examination and modification of system
registers during program execution. The COPS Monitor
and Debugger is described in Chapter 7.
Table 1-1. Recommended Peripheral Devices
111t::ll.tUt"IYIUI~
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1.3.7 File List Program (LIST)
Device
CRT:
Vendors
The File List Program (LIST) is a PDS system program
which lists files on the system console or printer. LIST
has several printing options. The File List Program is
described in Chapter 8.
1. Lear Siegler Model ADM·3,
Part No. 129450
Lear Siegler
714 No. Brookhurst SI.
Anaheim, CA 92803
2. Hazeltine Model 1500
Hazeltine Industrial Products Div.
Greenlawn, NY 11740
PRINTER:
1. Centronics Mod. 702 w/RS232
interface
Centronics Data Computer Corp.
Hudson, NH 03051
2. FACIT Mod. 4555 w/RS232 interface
(Sweden)
3. G.E. TERMINET w/RS232 interface
TTY:
1. Teletype Mod. ASR3320/3JC
manual read
2. Decwriter
3. Silent 700
1.3.8 Cross Reference Program (XREF)
The Cross Reference Program (XREF) is a PDS system
program which prints a symbol map of COP assembly
language programs. The symbol map shows the name
of every symbol in the program, the line number where
the symbol is defined, and all of the line numbers
where the symbol is used. The Cross Reference
Program is described in Chapter 9.
Note: A Silent 700 with RS232 interface requires pins 5 and 8 to be
connected together.
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1.3.9 Mask Transmittal Program (MASKTR)
1.3.10 Memory Diagnostic (MDIAG)
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The Memory Diagnostic (MDIAG) is a PDS system pro·
gram which runs diagno'stics on PDS memory. This
program will run ADDRESS, BIT, WORD, and GALPAT
tests. The Memory Diagnostics Program is described
in Chapter 11.
E
1.3.11 COP400 PDS PROM Programmer (PROG)
o
The COP400 PDS PROM Programmer (PROG) Is a PDS
system program which operates the PROM program·
mer located in the center of the PDS front panel. The
PROM programmer programs MM2716, MM2732,
MM2724, and MM2758 EPROMs. The COP400 PDS
PROM Programmer is described in Chapter 12.
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The PDS In·Circuit Emulation System is shown in
Figure 1-5. The Emulator Card emulates the COP chip
by using a special 400 device which is identical to a
masked·ROM COP. The ROM of the special COP400
device has been replaced by a connection to an exter·
nal memory. The external memory may consist of
PROMs which plug into the emulator card, or random
access memory located within the PDS. Random
access memory used by both the emulator card and
PDS is called "shared memory."
The Mask Transmittal Program (MASKTR) Is a PDS
system program which creates the Transmittal File
used by National Semiconductor to create the COP
chip ROM/OPTIONS mask. The Mask Transmittal Pro·
gram is described in Chapter 10.
The contents of shared memory may be first loaded
from a disk file, then altered and/or listed using the
PDS system software (COPMON) described in Chapter 7.
1.4 COP400 Emulation and Debugging Overview
A TARGET cable, supplied with the PDS, connects the
PDS to the Emulator card. One end of the TARGET
cable attaches to the 50·pin edge connector on the
card. The other end splits into two connectors, one
male and one female, that attach to the PDS rear panel
connectors labeled "EMULATOR 1 and 2." Table 1-2
shows the wiring of these connectors. Five types of
signals come across the TARGET cable:
The following COP400 Emulation and Debugging facil·
itate COP400 system development:
1. Shared memory address and data lines-used by
the emulator card to access shared memory.
• In·Circuit Emulation
2. +5 Voc and GND power supply lines-used to
power the emulator card. These lines are from the
PDS power supply and should never be used to
power the user's system.
3. RESET line-permits PDS software reset of the
emul ator card (see Chapter 7).
4. External event lines - permit breakpoint and single·
step on signals from external devices. Signals must
be TTL compatible.
• Trace
• Breakpoint
• Single·Step
Emulation and Debugging commands are described in
Chapter 7.
1.4.1 In·Clrcult Emulation
In·Circuit Emulation refers to execution and testing of
COP400 programs while under PDS control. The PDS
In·Circuit Emulator emulates the operation of the
user's COP400 system and permits user programs to
be tested in the user environment. The user may modi·
fy and re·test programs if errors are found. This
ensures that the program is correct before dedicating
it to mask·making.
DEVELOPMENT
SYSTEM
5. Trigger out line-permits the PDS to signal external
devices such as oscilloscopes. The signal is TTL
compatible.
The Emulator Card is described in detail in the In·
Circuit Emulator Cards Manual, Publication No.
420306469.
STRIPE TO PIN 1
COP
EM~k~~OR
::z:-===-....::;;:;:;:;:;o.:::..4-,/
/
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PIN·FDR·PIN
IDENTICAL
COP PLUG
COP
. IN·SYSTEM
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CABLE
Figure 1-5. PDS In·System Emulation System
8-14
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Table 1-2. Edge Connector Assignments
Connector No.
Name
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
GND
GND
Vcc
Vcc
EX2
EX1
EX4
EX3
ClK
SKIP
A8
A9
. A3
A7
A1
A2
A4
AO
A6
A5
Not Used
A10
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
BO
07
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
B2
B5
B3
B4
B6
B1
TRIGGER OUT
Not Used
RST
PROM DISABLE
See Note 1
See Note 1
Vcc
Vcc
GND
GND
0
0
""tJ
....0
Description
Signal and power return
Signal and power return
+5Voc power from Development System
+5V oc power from Development System
Buffered External Event
Buffered External Event
Buffered External Event
Buffered External Event
Buffered ADIDATA signal from COP4XX
COP4XX skip status line
COP4XX program counter address bit
Address Bit
Address Bit
Address Bit
Address Bit
Address Bit
Address I:!It
least significant address bit
Address Bit
Address Bit
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least significant COP object code bit
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Object code bit
Object code bit
Object code bit
Object code bit
Object code bit
Object code bit
BREAKPOINT/TRACE indicator
Same as RESET
Select PROM or Shared Memory mode
+5Voc power from Development System
+5Voc power from Develoment System
Power ~nd signal return
Power and signal return
Note 1: Pins 45 and 46 are used as follows:
pos with target board 980306552 REV A or later, normally not used.
pos with target board 980305551 REV F or earlier, -12Voc from the POS.
8-15
1.4.2 Trace
A trace records the path of execution control through
the user program.
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occur before a break is initiated. At the time that break
is initiated, a positive edge occurs on the Trigger Out
(T.O.) signal post on the emulator card. This signal can
be used for triggering oscilloscopes or logic analyzers.
A trace may store up to 254 consecutive COP instruc- "
tion addresses in the PDS Trace memory. A trace can
be initiated on user command or it can be set up by
the user to initiate when one of these conditions
occurs:
1. The COP chip program counter attains a specific
address.
2. External· Events 1 and 2 attain specific values.
The user can specify that a given number of occurrences (from 1 to 256) of the above conditions must
occur before trace is initiated. At the time that trace is
Initiated, a positive edge occurs on the Trigger Out
(T.O.) signal post on the emulator card. This signal can
be used for triggering oscilloscopes or logic analyzers.
The user may specify the number of COP instruction
addresses that are to be stored prior to the trigger.
This number may be from 0 to 253. The remainder of
trace memory will automatically store as many instruc·
tion addresses as possible following the trigger. The
user can thus perform pre-triggering, post·triggerlng,
and mid-triggering.
When break is initiated, the COP chip instruction lines
are switched from shared memory or PROMs over to a
special transparent memory containing a dump program. This program causes the special COP400 chip
on the emulator card to dump all internal registers and
memory to PDS, where it is available for inspection by
the user. The program then restores all registers and
maintains the COP chip in a waiting state until commanded by the user to continue normal program
execution.
1.4:3 Breakpoint
-Breakpoint provides a means to examine internal COP
registers at specific points within program execution.
A break can be initiated Immediately on user command, or it can be set up by the user to initiate automatically when one of the following conditions occurs:
1. The COP chip program counter attains a specific
address.
2. External Events 1 and 2 attain specific values.
In addition to COP instruction addresses, trace
memory stores the following data:
1.4.4 Single·Step
1. COP chip SKIP flag, which indicates whether or not
the corresponding instruction was skipped.
2. The four external event signals connected by the
user to the emulator card posts labeled 1,2,3, and 4.
Single-step provides a means for single-stepping the
COP chip by breakpolnting on each consecutive
instruction. Internal COP registers are available to the
user after each step.
The user can specify that a given number of occurrances (from 1 to 256) of the above conditions must
8-16
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PDS Installation and Initialization
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2.1 Introduction
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Table 2-1. TTY Connector (Current Loop)
This chapter provides a description of PDS installation
and initialization procedures. Also discussed is the can·
sale input, including command syntax, printer output,
system configuration, diagnostics and error messages.
Q.
Installation of the PDS involves a physical check of
the PDS, connection of the peripheral devices to the
PDS, and application of power to both the PDS and the
peripheral devices. To install the PDS, do the following:
1. Remove the PDS top cover by removing the two
screws located toward the rear of the cover and slid·
ing the cover off. Make sure that all six PC boards'
are seated and firmly fastened. Replace the top
cover.
2. Connect the peripheral devices to the PDS. The user
must orovide aopropriate cables for connection
between the peripheral devices and the connectors
on the PDS rear panel. Pin assignments are shown
in Tables 2-1 and 2-2.
3. Plug the power cable into the rear of the PDS. The
PDS is now ready for operation.
2.3 System Initialization
System Initialization involves powering up the PDS and
configuring system peripherals. To initialize the
system, do the following:
1. Turn on power to the PDS and system peripheral
devices. (The PDS is powered up using the front
panel key switch.) The system displays
CR?
()
TTY Xmitter ( + )
TTY Printer (+)
Reader Relay (+ )
Not connected
Not connected
TTY Xmitter Return ( - )
TTY Printer Return (-)
Reader Relay Return (- )
Not connected
1
2
3
4
5
6
7
8
9
2.2 PDS Installation
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Signal Name
Pin Number
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Table 2-2. Printer and CRT Connectors (RS232)
RS232
Data Set
Pin No.
1
2
3
4
5
6
7
8-19
20
Signal Name
Printer
Pin No.
CRT
Pin No.
1
2 not conn.
1
2
3
4 not conn.
5
6
7
8-19
not conn.
20
not conn.
21-25
not conn.
-
Chassis Ground
Transmitted Data
Received Data
Request to Send
Clear to Send
Data Set Ready
Signal Ground
Data Terminal
Ready
21-25
3
4
5
6
7
8-19
not conn.
20
21-25
not conn.
on the front LED display.
The MONITOR switch loads the COPMON program
described in Chapter 7.
sale. The system performs an initialization routine,
sets the console baud rate and type (RS232 or cur·
rent loop), and then displays message:
EXEC Rev A
The DIAG switch loads the Diagnostic routine des·
cribed in Section 2.7.
The INIT switch resets the PDS. The user may then
initialize the PDS as described above.
E>
at the console. The system is now in the executive
(EXEC) program. E> is the program prompt.
3. Configure console and printer operation using the
System Configuration Commands (see Section 2.6).
Note that console configuration can be skipped if
the default configuration is sufficient. Default can·
figuration for current loop interface is 110 baud, no
parity, two stop bits, and full duplex operation.
Default for RS232 is 1200 baud, no parity, and no
line feed or carriage return delays.
2.4 Console Input
2.4.1 Commands and Command Line Syntax
The PDS commands cause the system to perform a
specified operation or load a PDS program from disk·
ette into memory. A PDS command consists of
symbols, names, and operands that specify the command type and the operation to be performed. The operands specify the diskette files, numbers, names, and
options that are to be used during command operation.
4. Insert the PDS MASTER diskette in the PDS floppy
disk drive and close the door (see Figure 2-1).
The user enters PDS commands at the command line.
The command line is a line at the system console containing a program prompt. A prompt consists of a
letter followed by the ">" symbol, e.g., "E>" is the
EXEC program prompt. The prompt indicates which program the system is currently executing. Each PDS
program has a unique prompt. Table 2-3 lists the
prompts of the various PDS programs.
The PDS is now ready to accept PDS commands. The
user may enter a command or program name at the
console as described in the next section or press the
PDS front panel switches MONITOR, DIAG, and INIT.
8-17
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8-18
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Table 2-3. PDS System Program Names and Prompts
System
Program
Name
ASM*
COPMON*
DSKIT*
EDIT*
FM*
L1ST*
MDIAG*
PROG*
XREF*
MASKTR*
EXEC**
Function
COP Macro Assembler
COP Monitor
Disk Initialization and Test
Text File Editor
File Manager Program
Text File Listing
PDS Memory Diagnostic
Program
PROM Programming Utility
COP Program Cross
Reference
Mask Transmittal Program
PDS Executive Program
Blanks or commas, when present in command
strings, are significant; they must be entered as
shown. Multiple blanks may be used in place of a
single blank.
.
Prompt
< >-angle brackets enclose descriptive names (in
lower·case) for user·supplied namesllabels for
commands, parameters, devices, and files.
A>
C>
D>
E>
F>
L>
M>
{ } - braces enclose more than one item out of
which one, and only one, must be used. The items
are separated from each other by a logical OR sign
"I"·
[]-brackets enclose optional items(s). Brackets
within a bracket enclose item(s) which may be
optionally entered only if the item outside that inner
bracket is entered.
P>
R>
I-logical OR sign separates items out of which
one and only one may be used.
.. , -three consecutive periods indicate optional
repetition of the preceding item. If a comma pre·
r:",ri"" th" thr"A !'IA,inri", thAn Aach item must be
separated from the other by a comma.
T>
X>
* System program on Master Diskette.
•• System program In Firmware.
When a prompt appears, the system is ready to accept
a command. The PDS commands are divided into three
types:
2.4.2 Control Characters
PDS uses a console input routine which has several
features that allow the user to correct typing mistakes.
Among the features are the ability to backspace and to
abort a line using control characters. Table 2-4 des·
scribes the various control characters and the function
of each one. These control characters c;:an be used at
any time when the user is typing on the PDS console.
If a hardcopy console is being used, most of the can·
trol characters cannot be used because of the inability
to back up and change characters that have already
been typed. However, the Shift/a, Control/Q, Control/I,
and carriage return characters can be used.
• System Configuration Commands
• Program liwocation Commands
• Program Commands
The System Configuration commands configure the
system peripheral devices. The commands consist of
two "at signs" (@@);acommand name, and com·
mand operands. Commands must be terminated by a
carriage return.
The Program Invocation commands load PDS pro·
grams from diskette in memory and change the current
nrnnram nrnmot. The commands consist of an "at
sign" (@), a program name, and program operands and
must be terminated by a carriage return.
2.4.3 Disk Files
A disK rile IS a COllection or oata storeo on a OI:>K anu
given a name. (The words disk, diskette, and disc are
used interchangeably throughout this manual.) A PDS
filename has the following syntax:
The Program commands cause the current PDS pro·
gram to perform a specific operation. The commands
consist of a command name'and command operands
and must be terminated by a carriage return. Each PDS
program has a unique set of Program commands.
[:] [. ]
The brackets ([]) around a term indicate that the term
is optional and may be left off. An example of a file·
name is PDS:SAMPLE.SRC. The volume name is PDS,
the name is SAMPLE, and the modifier is SRC.
The syntax of a PDS command depends on the com·
mand function and/or the program to which it belongs.
In describing command syntax, the following conven·
tlons are used. Upper·case and lower·case letters are
used in these conventions; any combination of upper·
case and lower·case letters may be used when
actually entering the commands.
The volume name is a name given to a diskette. All
files on a particular diskette have the same volume
name. The volume name is given to the diskette when
it is initialized (see Chapter 4) and can be changed
with the File Manager program (see Chapter 3). It
consists of one to eight alphanumeric charactersblanks and special characters are not permitted. The
volume name is optonal in a filename. If PDS encoun·
ters a filename with no volume name, it will use the
volume name of the diskette that is currently in the
PDS disk drive. If given, the volume name must be sep·
arated from the remainder of the filename by a colon.
UPPER·CASE letters show the command names and
keywords. Mandatory items are shown outside of
the brackets []; they must be included in the
command.
If an item shown consists of underscored letters
followed by non·underscored letters, then that item
may be entered in an abbreviated form. Minimum
legal abbreviation of such items is the underscored
letters i>0rtion; in addition, any number of the non·
underscored letters that follow may also be used.
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Table 2-4. PDS Console Input Control Characters
Character
Function
U)
ControliH
U)
Shift/O ("<-" on some TTY)
ControllO
Carriage return
ControliT or Controlll
ControliX
ControliL
ControliA
ControliB
ControliF
ControliC
ControliD
ControliE
ControliS
ControliO or ControliZ
ControliP or ControllW
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Backspace one character, but do not delete the character that Is backspaced
over.
Delete one character back.
Abort line and try again.
Line is completed. Must be entered at end of each line.
Tab. (See @@TAB Command for setting tabs.)
Delete character at current CRT cursor position.
Forward space one character.
Insert characters before current cursor character.
Backspace one word.
Forward space one word.
Forward space to third t.ab position (for comments).
Same as carriage return except line Is truncated at current cursor position.
Forward space to end of line.
Backspace to start of line.
Forward space to next occurrence of next character typed.
Forward space one character beyond next occurrence of next character
typed.
Note: If no characters have been typed on a line, forward spacing will space over the last line typed, a useful means of repealing the last line.
If the last line ended In "'PR",lt will not appear on the repeated line.
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The name part of a filename may consist of one to
eight alphanumeric characters. The first character
must be an,alphabetic-blanks and special characters
are not permitted.
Eachflle has a special number called an Internal File
Type (1FT) maintained by PDS In the diskette directory.
The 1FT Is not alterable by the user. It Is used by PDS
to indicate the type of data in each file (source text,
system program data, etc.). This allows PDS to prevent
the user from accidentally assembling a binary data
file, or attempting to execute a source text file. The
1FT Is not related to the file mOdifier. The·modifier Is
selected by the user; the PDS selects the correct 1FT
regardless of what modifier is used. Table 2-6 lists the
PDS IFTs.
The modifier part of a fIIename,may consist of up to
three alphanumeric characters-blanks and special
characters are not permitted. It is separated from the
beginning part of the filename by a period. A period
with no character following it specifies a modifier with
zero characters. The modifier Is usually used to des·
cribe the type of a file. For example, SRC is used for,
text files and MP is used for PDS system program
files. This convention is not mandatory. The user may
choose any modifier. The modifier and its preceding
period are optional. If left off, PDS will provide a
default modifier. Table 2-5 lists the default modifiers.
Table 2-6. PDS Internal File Types
Table 2-5. System Default Modifiers
Modifier
SRC
LM
MP
LST
SYT
TRN
Definition
Source Text
COP Load Module
PDS System Program
Listing File
Special System File
PDS Transmittal File
Each file on a diskette has a unique NAME. MODIFIER
combination. The user creates flies using the PDS file
manager, text editor, or assembler programs. PDS
maintains a directory on each diskette, describing the
name and other information for each file on it. The
directory can be listed by using the PDS File Manager
program (see Chapter 3).
File Type
Definition
SYM
LM
MP
Symbolic Text .\
COP Load Module
PDS System Program
A file whose 1FT Is SYM (symboliC) consists of ASCII
data written on the disk. The PDS File Manager pro·
gram generates the SYM file type when copying ASCII
data to the disk or when copying another SYM file. The
PDS Text Editor program (see Chapter 5) requires a
SYM file when reading data from the disk, and gener·
ates a SYM file when writing data to the disk. The PDS
Assembler program requires a SYM file as input, and
generates a SYM file when creating a listing file.
A file whose 1FT Is LM (Load Module) consists of binary
data In COP load module format. The PDS Assembler
program (ASM) generates an LM file as object code
output. The COP Monitor program (COPMON) requires
an LM file for loading into shared memory.
A file whose 1FT Is MP (Main Program) consists of
binary data In a format that allows it to be executed by
PDS with an @ command, described later ,In this chap·
ter. The PDS programs FM and Edit are examples of
this file type.
8-20
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20 average lines of text. The diskette directory requires
at least eight sectors of its own. The File Manager
DIRECTORY command can be used to list the size of
each file (see Section 3.5).
PDS maintains another' number for each file, called a
protection level. This is used to prevent accidental destruction of files. Table 2-7 is a list of protection levels
and their safeguard provisions. System programs such
as FM and Edit create files for the user as level 2 files.
All system programs are initially level 3 files. The protect level of any file can be changed with the File Manager PROTECT command (see Section 3.12).
Table 2-7.
Protection Levels and Safeguard Provisions
Protection User Notified
Level
of Creation?
If PDS is directed to write into an existing file, it will
delete the existing file and recreate a new file of the
same name, type, and protection level. A file cannot be
recreated if its protection level is 3, and if its protection
level is 2, the user must give permission for recreation.
A deleted file is not removed from the diskette. It still
exists and can be undeleted with the File Manager
UNDELETE command, provided that the disk has not
been packed (see Section 3.15).
0
2
3
No
Yes
Yes
Yes
User Approval Required
to Delete or Modify File?
No
No
Yes
Delete/Modify not allowed
The PDS disk file manipulation routines will generate an
error message when certain conditions occur. A file error message has the following format:
A third number for each file, called the version number,
is set to 1 the first time the file is created. Each time
the file is recreated, as, for example, when a text file is
edited using the editor program, the version number is
incremented. This number is to keep an up-to-date
backup of a file. It is recommended that the user always
keep a backup of every file, because diskettes go bad
occasionally. The File Manager DUPLICATE command
is used to back up a file (see Section 3.6).
DISK ERROR, FILE
error message 1
[error message 2]
Table 2-8 is a list of the error messages and their meanings. Normally only the first nine messages given in the
table will occur. In some messages there is no filename
involved, in which case only":." will be printed for the
filename. Sometimes two error messages will be
printed.
.
A diskette is divided into sectors. There are 616 sectors
on each diskette. One sector will hold approximately
8-21
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Table 2-8. Disk File Error Messages
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Error Message
Problem
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WRONG DISK VOLUME
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DRV NOT RDY
No disk in drive, drive door isn't shut, or diskette is jammed.
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FILENAME SYNTAX
User typed an illegal filename.
ENDOF FILE
User tried to read past the end of the file while using the text editor.
END OF DISK
Diskette is full, no more data can be stored on it. See WARNING in Chapter 7
concerning this error.
CANT DELETE
Attempt to delete a file whose protect level is 3, or user didn't give
permission to delete a file whose protect level is 2.
ILLEGAL DEVICE
User referred to an illegal device.
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User referred to a file on a diskette other than the one in the drive.
FILE NOT FOUND
Reference was made to a file that is not on the diskette.
NO SYNC/WRT PRTCT
Attempt to write on write-protected diskette, or else disk is bad.
WRTCRC ERR
Couldn't write on disk, disk may be bad.
C
RDCRC ERR
Couldn't read from disk, disk may be bad.
U
CANT RD NST
Drive not ready or disk is bad.
DISK/DIR FULL
c..
Diskette is full, no more data can be stored on it. See WARNING in Chapter 7
concerning this error.
CANT RD DIR
Drive not ready or disk is bad.
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Drive not ready or disk is bad.
c..
CANTWRT DIR
Disk may be bad.
RD ERR
Disk is bad.
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Disk is bad.
CANT MODIFY
Attempt to modify a file whose protect level is 3, or user didn't give
permission to modify a file whose protect level is 2.
ADDR ERR
System hardware or software error.
ILLEGALGMD
System hardware or software error.
NO DISKIO ERRS
System hardware or software error.
NO ERRS
System hardware or software error.
NOT OPEN FOR RD
System hardware or software error.
NOT OPEN FOR WRT
System hardware or software error.
NOT OPEN FOR MOD
System hardware or software error.
ALREADY OPEN
System hardware or software error.
TOO MANY FILES
System hardware or software error.
NSTIDIR CONT MATCH
System hardware or software error.
PAST END OF DIR
System hardware or software error.
BADCHNL TBL
System hardware or software error.
NO END OR DIR
System hardware or software error.
TOO MANY VOLUMES
System hardware or software error.
2.5 Printer Output
In a few system commands, a device name is acceptable in place of a filename. A device name is specified
by an, asterisk, followed by two alphabetic characters
indicating a peripheral device. At present, only two
device names are allowed. These are shown in Table 2-9.
If a PDS command line has' PR at the end of it, PDS
will direct output generated by that command to the
printer. This can be done with any PDS system program command. If a printer is not connected to the
system, PDS will wait until one Is connected. The system must be reinitialized to terminate this wait state.
Table 2-9. PDS Device Names
Name
Device
'CN
'PR
System Console
Printer
Example:
F>C TEST1.SRC, TEST2.SRC, TEST3.SRC 'PR
CREATING FILE CDS:TEST3.SRC
(This line Is printed on the printer.)
8-22
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2.6 System Configuration Commands
and vertical tab delays are added. At system initializa·
tion time, the print parameters are set to 1200 baud,
RS232, no parity, zero delays.
System configuration commands set and change the
certain PDS system parameters. System configuration
commands may be entered at the EXEC level or at any
program level. Tables 2-10 and 2-11 list the commands
and their parameters.
Example:
X> @@ P 110,c,e,20,20,500,100
A system configuration command is invoked by typing
@ @ followed by a Command name and operands. The
four·system configuration commands are described
hereafter.
2.6.3 @ @ TAB Command
Syntax: @@TAB [,[,[,lll
The TAB command sets the tab columns for Control/T
or Controlll input line control characters. Three tab
columns can be set. Initial and default tabs are col·
umns 9, 17, and 33.
Table 2-10. System Commands
Directive
Function
Section
CONSOLE @@C[,[,
[,[,< Ifdly> llll
PRINTER @@P[,[,
[, [, < Ifdly>[, < ffdly>
[, llllll
TAB
@@T[,[,[,lll
WI nTH
(iiJ
rm WI rl
Example:
X> @ @T 10,20,30
2.6.1
2.6.4 @ @ WIDTH Command
2.6.2
2.6.3
Syntax: @@ WIDTH [l
The WIDTH command sets the printer and console
column width. At svstem initialization this Darameter
is set to 72. Minimum setting is 10, maximum setting
is 80.
?R4
Table 2-11. Operand Parameters
Command
Example:
X>@@WI80
Description
baud rate listed in Table 2·3
carriage return delay in milli·
seconds (1-1000)
form feed delay (1-1000ms)
line feed delay (1-1000ms)
E for even parity, N for no parity
tab column 1
tab column 2
tab column 3
R for RS232, C for current
loop device
vertical tab delay (1·1000ms)
_
.• !_.L _ _ _ --'
2.7 Diagnostics
Syntax: .QIAGNOSTIC
The Diagnostics command, the only command in the
EXEC program, causes a PDS diagnostic test to be
performed. The test performs a 7·minute diagnostic of
the system memory followed by a brief disk drive test.
If the memory test passes, the message:
MEMORY TEST PASSED
is displayed on the console. If the test fails, a memory
address is displayed on the console and servicing by
National tiemlconauctor Will oe necessary. An Inillal'
ized disk must be inserted in the disk drive for the disk
test to succeed. The message:
_ _ ._ _ _ • _ _ _ • • • _ _
I~idi'h'(1-0~80)-"--'- w._ .....
2.6.1 @ @ CONSOLE Command
DIAGNOSTICS PASS
Syntax: @@ CONSOLE[,[,
[,[, llll
The CONSOLE command sets the console parameters.
The baud rate must be one of the following: 110, 150,
300, 600, 1200,2400, 4800 or 9600. Type must be an "R"
for RS232 or a "c" for current loop console. Parity
must be "E" for even parity or "N" for no parity. Crdly
is the carriage return delay in milliseconds. It must be
a number from 0 to 1000. Lfdly is for line feed delay. It
must be a number from 0 to 1000. Default parameters
are RS232, no parity, zero delays. Console parameters
are automatically set up when CR is typed at PDS
initialization.
is displayed on the console when the disk drive test
passes. If the test fails, the message:
DISK TEST FAILED
is displayed.
Example:
X>Q
DIAGNOSTICS PASS
The diagnostic test is also performed whenever the
front panel DIAG switch is pressed. If the memory test
(which takes about seven minutes) fails, the fail
address will be given in the left side of the front panel
display, and the test type (address, word, or bit) will be
given in the right side. If this occurs, servicing by
National Semiconductor is necessary. If the memory
test passes, the disk test will be performed. As with
the console diagnostic operation, it takes only a few
seconds and requires that an initialized diskette be in
the disk drive. If this test fails, DISK ERRS will be
displayed on the front panel. If both tests pass, DIAG
PASS will be displayed on the front panel.
Example:
X>@@C1200,R,N,10,5
2.6.2 @ @ PRINTER Command
Syntax: @@ PRINTER[,[,
[, < crdly>[, < Ifdly> [, < ffdly>[, llllll
The PRINTER command sets the printer parameters.
Parameter description and defaults are the same as
for @ @ CONSOLE command, except that form feed
8-23
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3.1 Introduction
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The File Manager program (FM) provides an interface
to system disk files. FM enables the user to copy files,
delete and undelete files, list the disk directory, dupli·
cate disks, list file size and type, list space available on
a disk, list and change the disk name, and perform various other functions. This chapter describes the File
Manager commands and gives examples of their use.
F>DETEST.SRC, SAMPLE.MP
CANNOT DELETE FILE PDS:TEST.SRC
(protect level 3)
OK TO DELETE FILE PDS:SAMPLE. MP
(YIN, CR = YES)? CR
3.5 Directory Command
To call FM, the user types in the @ command:
Syntax: QI RECTORY [< option >[.