1982_OKI_Memory_Data_Book 1982 OKI Memory Data Book

User Manual: 1982_OKI_Memory_Data_Book

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MEMORY
DATABOOK

1982

IC MEMORY LINE-UP AND
TYPICAL CHARACTERISTICS

D

PACKAGING

H

RELIABILITY INFORMATION

D

MOSMEMORY
HANDLING PRECAUTIONS

[I

EPROM WRITING
AND ERASURE

n

MASK ROM CUSTOMER
PROGRAM SPECIFICATIONS

n

MASK ROM
DEVELOPMENT FLOWCHART
TERMINOLOGY
AND SYMBOLS
DATA SHEET
CROSS REFERENCE LIST
APPLICATIONS

0
HI
II
iI!I
iii

CONTENTS
IC MEMORY LINE-UP AND TYPICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . .

2

• DYNAM IC RAMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . "

3

• STATIC RAMS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

3

• EPROMS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

4

• MASK ROMS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

4

PACKAGING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

6

.16 PIN PLASTIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . "

7

• 16 PIN CERAMIC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

7

• 16 PIN CERAMIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . "

8

.18 PIN PLASTIC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

8

• 18 PIN CERAMIC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

9

.22 PIN CERAMIC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

9

.24 PIN PLASTIC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10
.24 PIN CERDIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

10

.24 PIN CERAMIC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

11

.24 PIN CERDIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . "

11

.28 PIN PLASTIC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

12

.40 PIN CERAMIC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

12

RELIABILITY INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

1. INTRODUCTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 14
2. QUALITY ASSURANCE SYSTEM AND UNDERLYING CONCEPTS. . . . . . . . . . . . . . ..
3. EXAMPLE OF

RE~IABILITY

TEST RESULTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . "

14
16

4. SEMICONDUCTOR MEMORY FAILURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
MOS MEMORY HANDLING PRECAUTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
EPROM WRITING AND ERASURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
MASK ROM CUSTOMER PROGRAM SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
MASK ROM DEVELOPMENT FLOWCHART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . "

34

TERMINOLOGY AND SYMBOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
DATA SHEET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
• MOS DYNAMIC RAMS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 45
MSM3716-2AS/RS

16384-Word x 1-Bit RAM (NMOS) . . . . . . . . . . . . . . . . . . . . . . . "

MSM3716-3AS/RS

16384-Word x 1-Bit RAM (NMOS) . . . . . . . . . . . . . . . . . . . . . . . . . 46

46

MSM3732-12AS/RS

32768-Word x 1-Bit RAM (NMOS) . . . . . . . . . . . . . . . . . . . . . . . "

MSM3732-15AS/RS

32768-Word x 1-Bit RAM (NMOS) . . . . . . . . . . . . . . . . . . . . . . . .. 55

55

MSM3732-20AS/RS

32768-Word x 1-Bit RAM (NMOS) . . . . . . . . . . . . . . . . . . . . . . . "

55

MSM3764-12AS/RS

65536-Word x 1-Bit RAM (NMOS) . . . . . . . . . . . . . . . . . . . . . . . "

71

MSM3764-15AS/RS

65536-Word x 1-Bit RAM (NMOS) . . . . . . . . . . . . . . . . . . . . . . . . . 71

MSM3764-20AS/RS

65536-Word x 1-Bit RAM (NMOS) . . . . . . . . . . . . . . . . . . . . . . . . . 71

MSM37256AS/RS

262144-Word x 1-Bit RAM (NMOS) . . . . . . . . . . . . . . . . . . . . . . . . 87

• MOS STATIC RAMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
MSM2114L-2RS

1024-Word x 4-Bit RAM (NMOS) . . . . . . . . . . . . . . . . . . . . . . . . "

MSM2114L-3RS

1024-Word x 4-Bit RAM (NMOS). . . . . . . . . . . . . . . . . . . . . . . . .. 90

90

MSM2114LRS
MSM2128-1 AS

1024-Word x 4-Bit RAM (NMOS) . . . . . . . . . . . . . . . . . . . . . . . . . , 90
2048-Word x 8-Bit RAM (NMOS) . . . . . . . . . . . . . . . . . . . . . . . . . , 94

MSM2128-13AS

. 2048-Word x 8-Bit RAM (NMOS). . . . . . . . . . . . . . . . . . . . . . . . .. 94

MSM2128-12RS

2048-Word x 8-Bit RAM (NMOS). . . . . . . . . . . . . . . . . . . . . . . . . . 98

MSM2128-15RS

2048-Word x 8-Bit RAM (NMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . 98

MSM2128-20 RS

2048-Word x 8-Bit RAM (NMOS). . . . . . . . . . . . . . . . . .. . . . . . . . 98

MSM51 04-2 RS

4096-Word x 1-Bit RAM (CMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . 103

MSM5104-3RS

4096-Word x 1-Bit RAM (CMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . 103

MSM5114-2RS

1024-Word x 4-Bit RAM (CMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . 108

MSM5114-3 RS

1024-Word x 4-Bit RAM (CMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . 108

MSM5114RS

1024-Word x 4-Bit RAM (CMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . 108

MSM5115-2 RS

1024-Word x 4-Bit RAM (CMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . 113

MSM5115-3 RS

1024-Word x 4-Bit RAM (CMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . 113

MSM5128-12RS

2048-Word x 8-Bit RAM (CMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . 118

MSM5128-15RS

2048-Word x 8-Bit RAM (CMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . 118

MSM5128-20RS

2048-Word x 8-Bit RAM (CMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . 118

MSM5188AS/RS

8192-Word x 8-Bit RAM (CMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . 123

• MOS MASK ROMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
MSM2916RS

2048-Word x 8-Bit Mask ROM (NMOS) . . . . . . . . . . . . . . . . . . . . . . 126

MSM2932RS

4096-Word x 8-Bit Mask ROM (NMOS) . . . . . . . . . . . . . . . . . . . . . . 129

MSM2965RS

8192-Word x 8-Bit Mask ROM (NMOS) . . . . . . . . . . . . . . . . . . . . . 132

MSM38128RS

16384-Word x 8-Bit Mask ROM (NMOS) . . . . . . . . . . . . . . . . . . . . . 135

MSM28101AS

1MBit Mask ROM (NMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

MSM28201AS

1MBit Mask ROM (NMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

MSM53256AS/RS

32768-Word x 8-Bit Mask ROM (CMOS) . . . . . . . . . . . . . . . . . . . . . 149

• MOS EPROMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
MSM2750AS

256-Word x 8-Bit EPROM (NMOS) . . . . . . . . . . . . . . . . . . . . . . . . . 152

MSM2708AS

1024-Word x 8-Bit EPROM (NMOS) . . . . . . . . . . . . . . . . . . . . . . . . 157

MSM2716AS

2048-Word x 8-Bit EPROM (NMOS) . . . . . . . . . . . . . . . . . . . . . . . . 162

MSM2764AS

8192-Word x 8-Bit EPROM (NMOS) . . . . . . . . . . . . . . . . . . . . . . . . 167

CROSS REFERENCE LIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177
64K BIT DYNAMIC RAM APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
CMOS RAM BATTERY BACK-UP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
MASK ROM KANJI GENERATION MEMORY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . 191

(All specifications and details published are subject to change without notice.)

ii

ICMEMORY D
LINE-UP AND TYPICAL
CHARACTERISTICS

o

Ie MEMORY LINE-UP AND TYPICAL
CHARACTERISTICS

* Under development
2

- - - - - - - - . I C MEMORY-UP AND TYPICAL CHARACTERISTICS •
• DYNAMIC RAMS

Model Name

Memory
Capacity

Circuit Function

Memory
Configuration

Number of
Pins
per
Package

Access
Time
MAX
(ns)

Cycle
Time
MIN
(ns)

Power
Consumption
MAX
(mw)
Operating!
Standby

Power
Supply
Voltage
(V)

MSM3741

4K

22 Pin Dynamic

4096 x 1

22

300

550

750/5

+12, +5,
-5

MSM3746

4K

22 Pin High Speed
Dynamic

4096 x 1

22

100

230

600/10

+12, +5,
-5

150

375

528/20

16K

16 Pin Dynamic

16,384 x 1

16
200

375

528/20

120

240

248/28

150

270

248/28

200

330

248/28

120

240

248/28

150

270

248/28

MSM3732L-20

200

330

248/28

MSM3764-12

120

240

248/28

150

270

248/28

200

330

248/28

MSM3716-2
MSM3716-3
MSM3732H-12
MSM3732H-15

32K

16 Pin Dynamic
A7 (Column) = H

32,768 x 1

16

MSM3732H-20
MSM3732L-12
MSM3732L-15

MSM3764-15

32K

64K

16 Pin Dynamic
A7 (Column) = L

16 Pin Dynamic

32,768 x 1

65,536 x 1

16

16

MSM3764-20
MSM37256

256K

16 Pin Dynamic

262,144 x 1

16

100/120 200/240

+12, +5,
-5

Equivalent
Device

TMS4060

MK4116-2
MK4116-3

+5

+5

+5

TMS4164-15
TMS4164-20

300/28

+5

Cycle
Time
MIN
(ns)

Power
Consumption
MAX
(mw)
Operating/
Standby

Power
Supply
Voltage
(V)

200

200

396

300

300

396

450

450

396

200

200

798

300

300

798

120

120

660/110

150

150

550/110

200

200

550/110

• NMOS STATIC RAMS

Model Name

Memory
Capacity

Circuit Function

Memory
Configuration

Number of Access
Pins
Time
per
MAX
Pack(ns)
age

MSM2114L-2
MSM2114L-3

4K

Static, Common I/O

1024x4

18

MSM2114L
MSM2128-1
16K

Static, Common I/O

2048 x 8

24

MSM2128-13
MSM2128-12
MSM2128-15
MSM2128-20

16K

Static, Common I/O
with Power Down Mode

2048x8

24

Equivalent
Device

2114.L2
+5

2114L3
2114L

+5

TMS4016

+5

TMM2016
M58725

3

I)

.IC MEMORY-UP AND TYPICAL CHARACTERISTICS . - - - - - - - - • CMOS STATIC RAMS

Model Name

Memory
Capacity

Circuit Function

Memory
Configuration

Number of Access
Pins
Time
per
MAX
Pack(ns)
age

MSM5114-2
MSM5114-3

4K

Fully Static,
Common I/O

1024x4

18

MSM5114
MSM5115-2
4K
MSM5115-3
MSM51 04-2
4K
MSM51 04-3

Clocked Static,
Common I/O

1024 x4

Clocked Static,
Common I/O

4096 x 1

Fully Static,
Common I/O

2048 x8

16K

Power
Consumption
MAX
(mw)
Operating/
Standby

200

192/0.04

300

300

192/0.04

450

450

192/0.04

200

300

33/0.04

300

420

33/0.04

200

300

33/0.04

300

420

33/0.04

120

120

330/0.275

150

150

300/0.275

200

200

275/0.275

Cycle
Time
MIN
(ns)

Power
Consumption
MAX
(mw)
Operating/
Standby

Power
Supply
Voltage
(V)

18

24

MSNl5128-20

Power
Supply
Voltage
(V)

200

18

MSM5128-12
MSM5128-15

Cycle
Time
MIN
(ns)

+5

Equivalent
Device

TC5514
~PD444

+5

HM6514

+5

HM6504

+5

HM6116
~PD446

• EPROMS
Model Name

Memory
Capacity

Circuit Function

Memory
Configuration

Number of Access
Pins
Time
per
MAX
Pack(ns)
age

Equivalent
Device

MSM2750

2K

24 Pin EPROM

256x8

24

1000

1000

2000

+5,-9

1702

MSM2708

8K

24 Pin EPROM

1024x 8

24

450

450

800

+12, +5,
-5

2708

MSM2716

16K

24 Pin EPROM

2048 x 8

24

450

450

525/132

+5

2716

MSM2732

32K

24 Pin EPROM

4096 x8

24

250

250

787/158

+5

2732A

MSM2764

64K

28 Pin EPROM

8192 x8

28

200

200

790/185

+5

2764

Cycle
Time
MIN
(ns)

Power
Consumption
MAX
(mw)
Operating/
Standby

Power
Supply
Voltage
(V)

Equivalent
Device

• MASK ROMS
Model Name

Memory
Capacity

MSM2816

Circuit Function

Memory
Configuration

Number of Access
Time
Pins
per
MAX
(ns)
Package

24 Pin MASK ROM

2048x8

24

450

450

525/132

+5

2716 EPROM

24 Pin MASK ROM

2048 x8

24

250

250

550

+5

2716 EPROM

16K
MSM2916
MSM2932

32K

24 Pin MASK ROM

4096x8

24

300

300

550

+5

2532 EPROM

MSM2965

64K

24 Pin MASK ROM

8192 x 8

24

300

300

687

+5

2564 EPROM

128K

28 Pin MASK ROM

16,384x8

28

450

450

660/110

+5

MSM38128

1M
MSM28201

MSM53256

4

JIS-Chinesecharacter
coding system
0-7,16-47

40 Pin MASK RAM

MSM28101

256K

18 x 16 Ch i nese-character font output

3760x 16
x 18

40

28 Pin CMOS MASK
ROM

32,768 x 8

28

25~s

61~s

630

+5
JIS Chinesecharacter
coding system
48-87

250

250

+5

PACKAGING

PACKAGING
Packages
I

fI

AS

RS

Name
No. of Pins

PLASTIC

CERDIP

CERAMIC

0

MSM3746

22

3716

16

0

0

3732

16

0

0

3764

16

0

0

37256

16

0

0

2114L

18

0

2128-1

24

5114

18

0

5115

18

0

5104

18

0

5128

24

0

5188

28

0

0

2916

24

0

0

2932

24

0

0

2965

24

0

0

38128

28

0

0

28101

40

0

28102

40

0

53256

28

2708

24

0

2716A

24

0

2732

24

0

2128

24

0

0

0

~-

--

0

Note: Model names suffixed by RS denote plastic mold devices, while AS denotes cerdip or ceramic devices.
Ex.
MSM2916RS
plastic mold device
MSM2916AS . . . . . . . . . cerdip or ceramic device

6

----------------------------------------------.PACKAGING •
• 16 PIN PLASTIC

20.0MAX

~NDEX MARK
7.62±O.30

MSM3716
MSM3764
2.54±O.25

• 16 PIN CERAMIC

20.6MAX
i----------------- --4
I

'

I

\ INDEX MARK

MSM3716

7

.PACKAGING.I-------------------------------------------• 16 PIN CERAMIC

206MAX

~

~

~

~

~

DJ~ ~ ~ ~ I

x

«

:2E
N
co

-=

~

~

"

\INDEXMARK

7.62±O.30

~

\

MSM3764

2.54±O.25

O.6MAX

M

\

O.35MAX

Seating
Plane

• 18 PIN PLASTIC

24.5MAX

7.62±O.30

MSM2114L
MSM5104
MSM5114
MSM5115

8

------------------------------------------------PACKAGING• 18 PIN CERAMIC

23:2MAX

x

«
~

LO
00

,..:

Zx
-«

MSM2114L
MSM51 04
MSM5114
MSM5115

7.62±O.30

.'1

: =: : :;~i!·
O.3SMAX
2.54±O.S2

O.6MAX

Seating
Plane

• 22 PIN CERAMIC

27.7SMAX

x

«
~
....
....o
LO

10.16±O.30

MSM3746

O.3SMAX

9

.PACKAGING.-------------------------------------------• 24 PIN PLASTIC

x

«
~

o
M
.....

x x I

««

MSM2128
MSM5128
MSM2916
MSM2932
MSM2965

~mrmii~i
0.65N1k~ ~
2.54±0.25

\ Seating
Plane

15.24±O.30

15°MAX

• 24 PIN CERDIP

32.5MAX

z
i~

MSM2708
MSM2716
MSM2732

10

~
,,

2.54±O.25

15.24±O.30

-------':-~r~
O.6MAX

t~

,

i~

Seating
Plane

15°MAX

I
0.6MAX

---------------------------------------------.PACKAGING •
• 24 PIN CERAMIC

30.83MAX

x

«
~
....
~
....
It)

15.24±O.30

MSM2128-1
MSM5128

_i-------+_2.-54-±O.25

O.35MAX

O.6MAX
Seating
Plane

• 24 PIN CERDIP

32.5MAX

x

«
~

"M

~

X

15.24±O.30

.... «
~

MSM2128
MSM2916
MSM2932
MSM2965

~

Egwnm~!¥Hi
2.54±O.25

Seati ng
Plane

11

.PACKAGING.--------------------------------------------• 28 PIN PLASTIC

38MAX

~x

MSM38128

Lfty~ ~yw~~~~
2.54±0.25

0

O.6MAX

0.65 MAX\ Seating 15 MAX
Plane

• 40 PIN CERAMIC

I-

545MAX

r
xl

T
o
M
ci

00

OQ

I

itMI

+1

co

1
!
I

I
1

1
X

z
OJ

rI

Quality Assurance
& Quality Control
Staff Activities

Service

I

-i

-<
2

I
I

Reliability
Engineering

II

Quality Management and Education

I

-Quality and Reliability
Information Analysis
- Quality Evaluation
-Failure Analysis

"T1

0

::c

!:
l>
-i

I..

(J'1

Quality Control Program + Reliability Program
y
Quality Assurance

)

0
2

•

• RELIABILITY INFORMATION ••1 - - - - - - - - - - - - - - - - Fig.2 Defect Processing Flowchart

Failure report processing

Request for
technical
improvement

r-Re~;t~~-I
I

results of
investigation
& improvement

Failure report
delivery
Quality
Assurance
Department
I

Report on
results of
investigation
& improvement

....

o

C

Q)

...... -E
(j)~Q)
Q)'- >

::lco
C'.c

0.

a:Q)~E
_._

I
L --------

Request for
manufacturing
improvement

(1)

appearance, labels, dimensions
and electrical characteristics inspection
(2) Group B tests: check of durability under thermal
and mechanical environmental
stresses, and operating life characteristics
(3) Group C tests: performed periodically to check
operational life etc on long term
basis.
Note: Like the reliability tests, the group B tests conform to the following standards.
MIL-STD-883B, JIS C 7022, EIAJ-IC-121
Devices which pass these lot guarantee inspections are
stored in a warehouse awaiting shipment to customers.
Standards are also set up for handl ing, storage and
transportation during this period, thereby ensuring
quality prior to delivery.
5) At Oki Electric, all devices are subjected to thorough
quality checks. If, by chance, a failure does occur after
delivery to the customer, defective devices are processed
and the problem rectified immediately to minimize the
inconvenience to the customer in accordance with the
following flowchart.

16

Group A tests:

3. EXAMPLE OF RELIABILITY TEST
RESULTS
We have outlined the quality assurance system and
the underlying concepts employed by Oki Electric.
Now, we will give a few examples of the reliability tests
performed during the developmental and production
prototype stages. All reliability tests performed by Oki
Electric conform with the following standards.
MI L-STD-883B, JIS C 7022, EIAJ-IC-121

- - - - - - - - - - - - - - - - 1 . RELIABILITY INFORMATION.
OKI MEMORY-LSI RELIABILITY TEST RESULTS
Device

MSM3764-15AS

MSM3764-15RS

MSM2128-1AS

Function

64Kbit DRAM

64Kbit DRAM

16Kbit SRAM
(Asynchronous)

Test
Structure

Test item

Steady state
operating lift
test

Test condition
Ta = 150°C
Vcc = 5.5 V

150 e
Ta

Moisture
resistance
(storage)

85°C 85%
Plastic only

2000

0

30

2000

0

26

5000

0

85°e 85%
Plastic only
* indicates on/off
operation
121°e,
2 atmospheric
pressure

*

*

*

120

2000

0

100

300

0

MSM5128-RS

MSM38128-XXRS

Function

16Kbit SRAM
(Asynchronous)

128Kbit Mask ROM
(Asynchronous)

CMOS Si gate
24-pin plastic

N-channel Si gate
E/D MOS
28-pin plastic

Test condition

Number
of test
samples

Ta = 150°C
Vcc = 5.5 V

50

2000

0

Ta = 125°e
Vcc = 5.5 V

100

1000

0

Test Defechours tives

150°C
H igh-temperatu re
storage test

Ta =

Number
Test Defecof test
samples hours. tives

Moisture
resistance
(storage)
Moisture
resistance
(operation)
Pressure
cooker

0

20

2000

0

MSM2716AS
16Kbit EPROM
N-channel Si gate
E/D MOS
24-pin ceramic
Number
Test Defecof test
samples hours tives
375

48

3000

0

20

3000

0

50

0

40

0

44

250 e

1685000

4
Data
erasure

1000

0

50

0

200 e
300 e

Low-tem peratu re
operating lift test

2000

0

Device

Structure

Steady state
operating lift
test

30

2000

50

o

Ta = -30 e
Vcc = 6 V

Test item

180

0

Low-temperatu re
operating lift test

Test

0

250 e
300 e

Pressure
cooker

2000

200°C
0

Moisture
resistance
(operation)

145

Ta=125°e
Vcc = 5.5 V
0

High-temperature
storage test

N-channel 2-layer Si gate N-channel 2-layer Si gate
N-channel Si gate
MOS
MOS
E/D MOS
16-pin ceramic
16-pin plastic
24-pin ceramic
Number
Number
Number
Test DefecTest DefecTest Defec- of test
of test
of test
hours
tives
samples hours tives
samples hours tives
samples

0
31 D ata
19 frasure

o

Ta = -30 e
Vcc = 6 V

48

85°C 85% RH
Plastic only

20

2000

85°C 85% RH
Plastic only
* indicates on/off
operation

40

1000

0

30

2000

121°e,
2 atmospheric
pressure

48

168

0

60

168

*

*

2000

0

0

*

0

0

17

II

• RELIABILITY INFORMATION . - - - - - - - - - - - - - - - - OKI's MEMORY LSI ENVIRONMENTAL STRESS ENDURANCE TEST RESULTS
MSM3764-15AS
Classification

....I:

Test name

Test condition

Resistance
to soldering
heat

Subjected to 260°C
for
10 seconds

Thermal shock

(Water) 0° C ~ 100° C 10 cycles
5 min 5 min

iijQ)

EEI: ....en
~

Q)oQ)

.c.: ....

1->
I:

Temperature
cycle

Q)

Q)

1500G 0.5msec
5 times each in X, Y, and Z
directions

Acceleration
(steady state)

10000G or 20000G 1 min
Once in X, Y , and Z
directions

>

~I:

Q)

100
Cycles

Shock

....

g...

150°C
or
125°C
30 min

100 ~ 2000 Hz 20G
4 min. percycle x 4 times
in XYZ directions

5Q)

~e!
!.J._

.....

Vibration
-I:

'c

-55°C
or
-65°C
30 min

Electro static
discharge test

OKI capacitor
discharge system
C = 200pF
Surge voltage applied
for 5 times
No series resistance

Number
of test
samples

20

Defectives

Defectives

0

20

0

200

0

120

0

60

0

20

0

Passed after
improvement

MSM5128RS
Classification

....I:

Test name

Test condition

Resistance
to soldering
heat

Subjected to 260°C
for
10 seconds

Thermal shock

(Water) 0° C ~ 100° C 10 cycles
5 min 5 min

iijQ)

EEI: ...

~

II>
Q)

Q) 0
.c
......

1->
I:
Q)

....

Temperature
cycle

100 ~ 2000 Hz 20G
4 min. percycle x 4 times
in XYZ directions

Shock

1500G 0.5msec
5 times each in X, Y I and Z
directions

Acceleration
(steady state)

10000G or 20000G 1 min
Once in X, Y , and Z
directions

5Q)

g. .

~
e$
.!.J._
Q»

~I:
Q)

Electro static
discharge test

18

100
Cycles

Vibration

-I:

'c

-55°C
150°C
..... or
or
125°C
-65°C
30 min
30 min

OKI capacitor
discharge system
C = 200pF
Su rge voltage applied
for 5 times
No series resistance

MSM3764-20RS
Number
of test
samples

MSM2128-1AS
Number
Defecof test
tives
samples

30

0

20

0

Passed

Passed

MSM38128-XXAS
Number
Defecof test
tives
samples

MSM2716AS
Number
Defecof test
tives
samples

Number
of test
samples

Defectives

25

0

20

0

20

0

65

0

120

0

40

0

18

0

24

0

30

0

Passed

Passed

Passed

- - - - - - - - - - - - - - - - . RELIABILITY INFORMATION •

• Data example 1
Device:
Test:
Test conditions:

MSM3764·1SAS
Continuous operation under high temperature
Ta = lS0°C, Vcc = S.SV, f = SOOkHz

Test circuit

MAX

Measurement:
V CC = 4.SV March pattern
Ta = 2SoC

so

I

MEAN
MIN

tCAC
(ns)

70

1--J.,t\,'V'--_VCC
5.5V

Signal
input
Signal
input

60

T

I

I

OH

16SH

I
500H

I
1000H

I

2000H

Start

~-

Test time

VCC
5.5V

Test timing f = SOO kHz
1~s

Measured at absolute maximum VCC

RASll

-

I
I

'-,-'-,- - - - - '

I~~s
CAS

;

__

!~i~ ~

I
I

:

I

I

~

I~

I

L
L

Measu rement:
March pattern
Ta = 2SoC
VCC
(V)

4

0.3~s
"H" Read

WE--r-----------------r---"L" Write

3

OH

16SH

500H

Start

Diagonal scanning for addresses Ao to A7

~

Test time

Exceptionally stable performance
demonstrated for all characteristics

19

• RELIABILITY INFORMATION ••- - - - - - - - - - - - - - - -

• Data Example 2
Device:
Test:
Test conditions:

D

MSM5128RS
Continuous operation under high temperature
Ta = 150°C, Vcc = 5.5V, f = 500 kHz

Test circuit

Measurement:
Vcc = 4.5V
March pattern
Ta = 25°C

100
Vee

= 5.5V

tae
(ns)

fMAX
MEAN
MIN

90

80

fs

P---

f7

f9

f6

flo

f,

f 12

f4

60

A3

f3
f2

70

fll

AI

168H
OH
Start

fo

500H

1000H 1500H 2000H
---+

Test time

fl

1/01
1/02
1/03
GND

Measurement:
Vcc = 5.5V
Ta = 25°C

lee1
(rnA) 2

o
I nput of waveforms halved successively
from f 0 to f 1 3
fo: 500 kHz

Since these reliability tests must determine performance
under actual working conditions in a short period of
time, they are performed under severe test conditions.
For example, the 125°C high temperature continuous
operation test performed for 1000 hours is equivalent
to testing device life from 2 to 300 years of use at
Ta = 40°C.

20

OH
Start

168H

500H

1000H 1500H 2000H
---+

Test time

By repeating these accelerated reliability tests, device
quality is checked and defects analyzed. The resulting
information is extremely useful in improving the manufacturing processes. Some of the more common defects
in memory LSI elements and their analysis are described
below.

- - - - - - - - - - - - - - - - - . RELIABILITY INFORMATION.

4. SEMICONDUCTOR MEMORY
FAILURES
The life-span characteristics of semiconductor elements
in general (not only semiconductor IC devices) is
described by the curve shown in the diagram below.
Although semiconductor memory failures are similar to
those of ordinary integrated circuits, the degree of
integration (miniaturization), manufacturing complexity
and other circuit element factors influence their
incidence.


*

II

Initial SHIPPING
failure

+

Wear-out
failure

Chance
failure

\
\

m> 1

2) Oxide Film Insulation Destruction (Pin Holes)
Unlike surge destruction, this kind of failure is caused
by manufacturing defects. Local weakened sections are
ruptured when subjected to external electrical stress.
Although this problem is accentuated by the miniaturization of circuit elements, it can be resolved by maintaining an Ultra-clean manufacturing environment and
through 100% burn-in screening.

I

\

\
\

,
"

~

General
electronic
devices

m=1

/

3) Surface Deterioration due to Ionic Impurities
Under some temperature and electric field conditions,
charged ionic impurities moving within the oxide film
previously resulted in occasional deterioration of silicon
surfaces. This problem has been eliminated by new
surface stabilization techniques.

Time

4) Photolithographic Defects
Integrated circuits are formed by repeated photographic
etching processes.
Dust and scrathces on the mask
(which corresponds to a photographic negative) can
cause catastroph ic defects.
At present, component
elements have been reduced in size to the order of 10-4
cm through miniaturization. However, the size of dust
and scratches stays the same. At Oki Electric, a high
degree of automation, minimizing human intervention
in the process, and unparalleled cleal iness solves this
problem.

I

/

J---///

/

m<1
'"---v----"

Debugging by burn-in
screening

Semiconductor
elements

-+

1) Surge Destruction
This is destruction of the input/output stage circuits by
external surge currents or static electricity.
The
accompanying photograph shows a point of contact
between aluminum and poly-silicon that has been
dissolved by a surge current. A hole has formed in the
substrate silicon, leading to a short circuit. This kind of
failure is traceable in about 30% of defective devices
returned to the manufacturer. Despite minaturization
of semiconductor memory component elements (which
means the elements themselves are less resistant), these
failures usually occur during assembly and other handling operations.
At Oki Electric, all devices are subjected to static
electricity intensity tests (under simulated operational
conditions) in the development stage to reduce this type
of failure. I n addition to checking endurance against
surge currents, special protective circuits are incorporated
in the input and output sections.

Photolithographic Defect
(Gate not formed in circled area)

Example of surge destruction

21

D

• RELIABILITY INFORMATION ••- - - - - - - - - - - - - - - 5) Aluminum Corrosion
Aluminum corrosion is due to electrolytic reactions
caused by the presence of water and minute impurities.
When aluminum dissolves, lines break. This problem is
unique to the plastic capsules now used widely to reduce costs. Oki Electric has carefully studied the possible cause and effect relationship between structure
and manufacturing conditions on the one hand, and
the generation of aluminum corrosion on the other.
Refinements incorporated in Oki LSls permit superior
endurance to even the most severe high humidity
conditions.
6) Alpha-Particle Soft Failure
This problem occurs when devices are highly mInIaturized, such as in 64-kilobit RAMs. The inversion of
memory cell data by alpha-particle generated by radioactive elements like uranium and thorium (present in
minute quantities, measured in ppb) in the ceramic
package material causes defects. Since failure is only
temporary and normal operation restored quickly, this
is referred to as a "soft" failure. At Oki Electric we
have eliminated the problem by coating the chip surface
of 64-kilobit RAMs with a resin which effectively
screens out these alpha-particle.

Package ceramic
cover

7) Degradation in Performance Characteristics Due to
Hot Electrons
With increased miniaturization of circuit elements,
internal electric field strength in the channels increases
since the applied voltage remains the same at 5 V. As
a result, electrons flowing in the channels, as shown in
the accompanying diagram, tend to enter into the oxide
film near the drain, leading to degradation of performance. Although previous low-temperature operation
tests have indicated an increase of this failure, we have
confirmed by our low-temperature acceleration tests,
including checks on test element groups, that no such
problem exists in Oki LSls.

Drain

+VG
Gate

~

I

VD
•
1

Source

p

Hot electron

Substrate silicon

Characteristic deterioration caused by hot electron
--,----:-,----:--I----:-7""'!""':.,--,~::-:-

Si I icon oxide
--'-~----'--r'--'-'--~'--'--"-...:-:.-:.;...:..:....:.~~ fil m

p

Substrate silicon

Ionization along
the 
"'0
0

E

u

0
0
a>

III
III

~

"'0
"'0

ro

c

0

-.::;
ro

[[

a>
0.

~

Next record

. .,

~

-"..--"..-

a>
"'0

a>
"'0

a>
"'0

U

U

u

0

r

0

0

"E

E

a

~

0

a>

0
0
a>
[[

.s=U

0

0
...J

'-,,-'

~
ro

0

c:

E

"E

0
0
a>
[[

---..-a>
"'0
0

u

-"..- '-..--'
III
III

a>

15
"'0
ro

c:

0

-.::;
ro

a>
0.

~

"E
0
0
a>

[[

E

a

~

0

a>

"I

I"

Feed
600 frames min.

.s=U

0

0
...J

Record mark:
Code no.:

colon ":"
Represents the code no. in 1 record
by a 2-digit hexadecimal number.

Maximum no. is 10 (hexadecimal)
with 00 denoting the final record.
Location address: Address of head data of that record.
These are 4-digit hexadecimal nos.
with 0000 denoting the final record.
Record type:
Record type denoted by a 2-digit
hexadecimal number. This is normally
00, but 01 for final record.
Code:
Single byte of data expressed by

32

Check sum:

4.

2-digit hexadecimal number.
Value obtained by sequential decrementing of code no., location
address, record type and codes from
initial value expressed as 2-digit
hexadecimal no.

EPROM Specifications
(1) MSM2716, MSM2764, Intel 2716,2732,2764 or
equivalent device may be used.
(2) Prepare 2 EPROMs containing identical data.

MASK ROM
DEVELOPMENT
FLOWCHART

o

MASK ROM DEVELOPMENT FLOWCHART

..

ROM data
check list

l Examination 1

Mask ROM
automatic
designing program

User's
ROM data

t------:-------------'

1T

Ground pin

VSS

VSS

Vacant terminal

NC

NC

36

VSS

VSS

- - - - - - - - - - - - - - - . TERMINOLOGY AND SYMBOLS.
2. Absolute Maximum Ratings
Term

EPROM

Voo, Vee
Power supply voltage

ROM

Static RAM

Vee

Vee

Voo,Vee

VSS

VSS

VSS

VT

VT

VBB

VGG,VBB
VSS

Oynamic RAM

Terminal voltage

VT

Input voltage

V,

V,

V,

V,

Output voltage

Vo

Vo

Vo

Vo

I nput current

Output current

10

Output shorting current

lOS
I

Load capacitance

Permissible loss

Po

Po

Po

Po

Operating temperature

Topr

Topr

Topr

Topr

Storage temperature

Tstg

Tstg

Tstg

Tstg

37

• TERMINOLOGY AND SYMBOLS . - - - - - - - - - - - - - 3. Recommended Operation Conditions
Term

EPROM

VOO, VCC
Power supply voltage

ROM

Static RAM

VCC

VCC

VSS

VSS

VGG,VSS
VSS

Dynamic RAM

VOO, VCC
VSS

"H" clock input voltage

VSS

VIHC

"H" input voltage

VIH

VIH

VIH

VIH

"L" input voltage

VIL

VIL

VIL

VIL

Data storage voltage

VCCH

Load capacitance

CL

CL

Fan-out

N

N

N

Operating temperature

Topr

Topr

Topr

38

Topr

- - - - - - - - - - - - - - - . TERMINOLOGY AND SYMBOLS.
4. DC Characteristics
Term

EPROM

ROM

Static RAM

Dynamic RAM

"H" output voltage

VOH

VOH

VOH

VOH

ilL" output voltage

VOL

VOL

VOL

VOL

"H" output current

10H

"L" output current

Input leak current

III

III

III

III

Output lea,k current

ILO

ILO

ILO

ILO

I/O leak current

Program terminal current

ILO
IpP1,IpP2

Peak power on current

Power supply current

IpO

IPO,lSSp

100, ICC

ICC,ICCS

ICC,ICCA

1001,ICC1,ISS1

ISS,ICC1

ICCA

ICC1,ICC2

1002,ICC2,ISS2

ICCS,ICCS1

1003, ICC3, ISS3

ISS

1004, ICC4, ISS4

ICC2

39

• TERMINOLOGY AND SYMBOLS . - - - - - - - - - - - - - - 5. AC Characteristics
(1) Read cycle
Term

EPROM

Read cycle time

tc, tRC, tCYC

tRC

Address access time

tACC

tAA, tACC

tA, tAC,
tACC, tAA

Chip select access time

tco

tcs

tco, tACS1,
tACS2

Chip enable access time

tCE

tACE

tAC

Output enable access time

tOE

tco

tOE

tLZ

tcx, tLZ

Output setting time

II

Static RAM

ROM

Output valid time

tOH

tOH

tOH, tOHA

Output disable time

tDF

tHZ

tOTD, tHZ,
tOFF

Address set-up time

tAS

tAS

Address hold time

tAH

tAH

Chip enable off time

tcc

Chip enable pulse width

tCE

Power-up time

tpu

tpu

Power-down time

tPD

tpD

Address enable pulse width

tAE

Data valid access time

tVA

Data valid delay time

tVD

Clock delay time

tVH

Clock pule width

tH

Clock delay time

tL

Output delay time

tDD

Output access time

tDA
- - - - ..

Output hold time

-.-~-

tDH
~--~---~--

Address enable set-up time

tAES
---'---

40

r--

Dynamic RAM
tRC

tOFF

- - . TERMINOLOGY AND SYMBOLS.
(2) Write Cycle
Term

ROM

EPROM

Write cycle time

Static RAM
twc

Address set-up time

tAS

tAS, tAW

Write pulse width

tpw

tw, twp

Write recovery time

Oynamic RAM
twc

twp

tWR

Oata set-up time

tos

tos, tow

tos

Oata hold time

tOH

tOH

tOH

Output off time

tOF

tOTW, twz

tOFF

Chip select set-up time

tcss

tcw

Address hold time

tAH

tAH, tWR

Chip enable off time

tcc

Chip enable pulse width

tcw, tCE

Write enable set-up time

tws

Write enable read time

tWCL

Write enable hold time

tWH

Address/write enable setting time

tAW

Write enable output activation

tow

Output enable set-up time

tOES

Output enable hold time

tOEH

Program read delay time

tOPR

Output enable delay time

tOE

Chip enable data valid time

tov

Program pulse rising edge time

tPRT

Program pulse falling edge time

tPFT

VPP restoration time

tVR

Chip enable hold time

tCH

--

41

DATA SHEET

MOS
DYNAMIC
RAMS

OK.I

semiconductor

MSM3716-AS/RS
16384 WORD X 1 BIT DYNAMIC RAM

GENERAL DESCRIPTION
The Oki N-MOS integrated circuit MSM3716- x AS/RS is an address multiplex type dynamic RAM with a 16,384
word x 1-bit configuration, featuring a wide operational margin and high-speed low power consumption while using a
single transistor.

FEATURES
• 16,384 words x 1 bit
• 150ns access time and 375ns cycle time
(MSM3716-2AS/RS)
200ns access time and 375ns cycle time
(MSM3716-3AS/RS)
• Standard 16-pin layout
• Low power consumption: 528mW (operation), 20mW
(standby)

• Output data controlled by CAS only, while system
design freedom is increased by not latch at cycle end.
• Read modify write, RAS only refresh and page mode
operations possible.
• TTL compatible low capacitance for all inputs.
• 1 28 refresh cycle.

PIN CONFIGURATION

II

•1

16

2

15

3

14

4

13

5

12

6

11
10

8

1

VBB

9

Vcc

2

DIN

10

As

3

WRITE

11

A4

4

RAS

12

A3

5

Ao

13

A6

6

A2

14

DOUT

7

Al

25

CAS

VDD

16

VSS

8

46

9

- - - - - - . - - - - - - - - - . DYNAMIC RAM . MSM3716-AS/RS.
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
D

(Ta = 25 C)

Item

Symbol

Conditions

Rating

-1.0

VOO
Respect to Vss

Vcc
Power supply voltage

Respect to Vss VOO - Vss

VBB

Unit

+15.0

-1.0 - +15.0

> 0·0

0

- -20.0

-0.5 - +20.0

VOO
Vcc

V

-0.5 - +20.0

Respect to VBB

-0.5 - +20.0

Vss
I nput voltage

~

-0.5 - +20.0

VI
Respect to VBB

Output voltage

Vo

-0.5 - +20.0

Storage temperature

Tstg

-55 - +150

DC

Permissible loss

Po

1

W

RECOMMENDED DC OPERATING CONDITIONS

Item

Power supply voltage

Symbol

Conditions

Recommended Operating
Conditions
Min.

Typ.

Max.

VOO

10.8

12.0

13.2

VCC

4.5

5.0

5.5

-4.5

-5.0

-5.5

VBB
"H" clock input voltage (note 1)

VIHC

Vss = 0

V

2.7

6.0

"H" input voltage (note 2)

VIH

2.4

6.0

"L" input voltage (note 3)

VIL

-1.0

0.8

Operating temperature

Topr

0

Notes:

Unit

70

DC

1. RAS, CAS and WRITE inputs
2. Ao - A6 and DIN inputs
3. All inputs

47

.DYNAMIC RAM .

MSM3716-AS/RS.~-------------

DC CHARACTERISTICS
(Voo = 12.0V±10%, Vcc = 5.0V±10%, V88 = -5.0V±10%, Vss = OV, Ta = 0-70°C)
Special Ratings
Item

Symbol

Min.
10D1
Average power supply current
during operation

ICC1

1002

Refresh power supply current

ICC2

mA

4

200

iJ.A

1.5

mA

10

iJ.A

5

RAS = VIHC

-10

00UT = High Impedance
100

iJ.A

1003

27

mA

ICC3

tRC = 375 ns

-10

1883

ICC4

10

iJ.A

200

iJ.A

29

mA

RAS=VIL

Input leak current

1L1

V88 = -5V
0::; VI < 6.0V

Output leak current

ILO

00UT = Oisable
0::; Vo ::; 5.5V

"H" output voltage

VOH

10 = -5 mA

VOL

10 = 4.2 mA

4

4
5

tpc = 225 ns

1884

"L" output voltage

40

1882

1004
Page mode power supply current

Note

Max.

tRC = 375 ns

1881
Power supply current during
standby mode

Unit

Conditions

200

iJ.A

-10

10

iJ.A

-10

10

iJ.A

0.4

V

V

2.4

Notes: 4. 1001,1003 and 1004 depend on cycle time.
5. ICCl and ICC4 are changed by output load. Vcc is connected to 00UT at low impedance during reading
of "H" level data.

48

- - - - - - - - - - - - - - - . DYNAMIC RAM . MSM3716-AS/RS.
AC CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS
c

(VDD = 12.0V±10%, Vcc = 5.0V±10%, VBB = -5V±100Al, Vss = OV, Ta = 0-70 C) (Notes; 6,7.8)
MSM3716-2AS/RS
Parameter

MSM3716-3AS/RS

Symbol

Units
Min.

Max.

Min.

Random read/write cycle time

tRC

375

375

ns

Read and write cycle time

tRWC

375

375

ns

Page mode cycle time

tpc

170

Access time from RAS

tRAC

150

200

Access time from CAS

tCAC

100

135

ns

Output turn-off delay time

225
9, 11

tOFF

0

40

0

50

ns

Rise and fall time

tT

3

35

3

50

ns

RAS precharge time

10,000

200

10,000

135

tRP

100

RAS pulse width

tRAS

150

RAS hold time

tRSH

100

CAS pulse width

tCAS

100

CAS hold time

tCSH

150

RAS and CAS delay time

tRCD

25

RAS and CAS precharge time

tCRP

-20

Row address set-up time

10,000

10,000

ns
ns

200
30

ns
ns

135

50

65

ns

-20

ns

tASR

0

0

ns

tRAH

20

25

ns

Column address set-up time

tASC

-5

-5

ns

Column address hold time

tCAH

45

55

ns

Column address hold time from RAS

tAR

95

120

ns

0

0

ns

tRCS

Read command hold time

10, 11

ns

120

Row address hold time

Read command set-up time

Note

Max.

tRCH

0

0

ns

Write command hold time

tWCH

45

55

ns

Write command hold time from R AS

tWCR

95

120

ns

Write command pulse width

twp

45

55

ns

Write command and RAS read time

tRWL

60

80

ns

Write command and CAS read time

tCWL

60

80

ns

Data input set-up time

12

tDS

0

0

ns

13

Data input hold time

tDH

45

55

ns

13

Input hold time for data from RAS

tDHR

95

120

ns

CAS precharge time

tcp

60

80

ns

Write command set-up time

twcs

-20

-20

ns

14

CAS and write command delay time

tCWD

70

95

ns

14

160

ns

14

RAS and write command delay time

tRWD

Refresh cycle

tREF

120
2

2

ms

49

_DYNAMIC RAM· MSM3716-AS/RS-'-------------NOTES: 6. Normal memory operation may not be possible unless at least 8 cycles of operation are performed
after the power is switched on.
7. AC measurements when tT = 5ns.
8. Prescribed timing input levels of VIHC (MIN), VIH (MIN) and VIL (MAX).
9. In the case of tRCO ::; tRCO (MAX); tRAC is increased only for tRCO-tRCO (MAX) for tRCO >
tRCO (MAX) case.
10. For tRCO ? tRCO (MAX) case.
11. For 2TTL + 100pF load case.
12. tRCO (MAX) is the value guaranteed by tRAC (MAX), and when tRCO > tRCO (MAX) it is distributed by tCAC.
13. tos and tOH are specified by the CAS falling edge during the write cycle (early write), and by the
WR ITE falling edge during read modify write cycle.
14. twcs, tcwo and tRWO are not parameters specifying operational limits.
twCS? twcs (MIN) results in write cycle (early write) with high impedance output.
tcwo ? twcs (MIN) and tRWO ? tRWO (MIN) result in read modify write cycle.

READ CYCLE

tRC
tRAS
VIHC RAS
VIL -

CAS VIHCVIL -

ADDRESSES

VIH VIL -

WRITE VIHCVIL-

11

°OUT

VOHVOL-

OPEN

~ "H", "L"=Oon't Care

50

- - - - - - - - - - - - - - . D Y N A M I C RAM· MSM3716-AS/RS.
WRITE CYCLE (EARLY WRITE)

~------------------tRC----------------~~
~------------tRAS----------~~

RAS VIHC------.. . 1
VIL-

1,--------.1

VICH-'
WRITE VIL- '~~~~~~~-_~~~_~~~LL~~~4L~~LLLL~~~

DIN VIHVIL-

DOUT

VOHVOL- - - - - - - - - - - - - - - - - - - - - O P E N - - - - - - - - - - ~ "H", "L"=Don't Care

READ-WRITE/READ-MODIFY-WRITE CYCLE
~-------------------tRWC------------------------~
~------------------tRAS----------------~ I _ _ _ _ _~I
~------tAR----~~
I~

~--~------tRSH----------~~

-----+----+------tCAS----------~

ADDRESSES VV IH IL-

tOFF
VOHDOUT VOL- ----~-----------OPEN--------~

~--------tRAC----------~

DIN

VIH VIL ~ ;;-H", "L"=Don't Care

51

• DYNAMIC RAM . MSM3716-AS/RS ••' - - - - - - - - - - - - - - - IIRAS-ONLY" REFRESH CYCLE CAS

= VIHC, WRITE = Don't Care

VIHCRAS VIL-

ADDRESSES ~:~=

;Wmffffi0r:JI,oR~ss =!I///III121I1////1!1/1/I/£ 1/;'i

DOUT VOH- - - - - - - - - VOL-

OPEN

~ "H","L"=Don't Care

PAGE MODE READ CYCLE

~-------------tRAS-----------~

VIHCRAS V
IL-

VIHCCAS V
ILtASR
ADDRESSES VIH-VIL--

DOUT

VOH- _ _ _~
VOL--

~ "H","L"";Don't Care

52

- - - - - - - - - - - - - - . D Y N A M I C RAM· MSM3716-AS/RS.
PAGE MODE WRITE CYCLE

J~--------------------tRAS--------------------~

CAS

VIHC----+~--~

VIL-

ADDRESSES VIHVIL-

WRITE

DIN

VI HC-""""""'''''''''+''''''''''''''''''''''''''''
VIL-

VIHV I L -L...L.L...L..~

30

~..p
-$

20

~".>
,Q

-<.-4~

/

/

10

'xco

~

/

/
/
0
0

1.0

3.0

2.0

4.0

Frequency (MHz) = 103 /tRC (ns)

Cycle time tRC (ns)
100

Cycle time tpc (ns)

~

...c:

!f

40

$'

f

CJ

~0

11

0

...c:

/

:;
CJ

....
Q)

::

30

30

~\)e

~

o::t

20

0
0

E
::l
E

::l

E 10

'xco

'xco

~

p

~0(\~e

0
0-

,QQ /

E

~I>-~' /

20

\:

\~:~~V '
/'"

10

... /

./

//

/" V
./

~

0

0
0

1.0

3.0

2.0

Frequency (MHz)

54

40

f

~'?' .l..Q.
~

0-

0

.§

~~ /1

:;

300 250

~

/

~tr)

500 400

50

/

e

~.;;j

.§

1000

300 250

500400

50

=

4.0

103/tRC (ns)

o

1.0

2.0

3.0

4.0

Frequency (MHz) = 103/ tpC (ns)

OK.I

semiconductor

MSM3732 -AS/RS
32,76B-BIT DYNAMIC RANDOM ACCESS MEMORY

GENERAL DESCRIPTION
The Oki MSM3732H/L is a fully decoded, dynamic NMOS random access memory organized as 32,768 one-bit words.
The design is optimized for high-speed, high performance applications such as mainframe memory, buffer memory,
peripheral storage and environments where low power dissipation and compact layout is required.
Multiplexed row and column address inputs permit the MSM3732 to be housed in a standard 16 pin DIP. Pin-outs
conform to the JEDEC approved pin out.
The MSM3732 is fabricated using silicon gate NMOS and Oki's advanced Double-Layer Polysilicon process. This
process, coupled with single-transistor memory storage cells, permits maximum circuit density and minimum chip
size. Dynamic circuitry is employed in the design, including the sense amplifiers.
Clock timing requirements are noncritical, and power supply tolerance is very wide. All inputs and output are TTL
compatible.

FEATURES
e32,768 x 1 RAM, 16 pin package
eSilicon-gate, Double Poly NMOS, single transistor cell
e Row access time,
120 ns max (MSM3732-12)
150 ns max (MSM3732-15)
200 ns max (MSM3732-20)

•
•
•
•
•

• Cycle time,
240 ns min (MSM3732-12)
270 ns min (MSM3732-15)
330 ns min (MSM3732-20)
• Low power: 248 mW active,
28 mW max standby
• Single +5V Supply, ±10% tolerance

•
•
•
•

All inputs TTL compatible, low capacitive load
Three-state TTL compatible output
"Gated" CAS
128 refersh cycles
Common I/O capability using "Early Write"
operation
Output unlatched at cycle and allows extended page
boundary and two-dimensional chip select
Read-Modify-Write, RAS-only refresh, and PageMode capabil ity
On-chip latches for Addresses and Data-in
On-chip substrate bias generator for high
performance

PIN CONFIGURATION

NC

Vss

Din

CAS

Pin Names

Function

WE

Dout

Ao ""A 7
RAS

Address Inputs

RAS

A6*

CAS

Column Address Strobe

Ao'

WE
A3'

Write Enable

Din

Data Input

A,'

A4

'

AI'

As *

Vee

A7

Row Address Strobe

Dout

Data Output

VCC

Power (+5V)

VSS

Ground (OV)

* Refresh Address

55

_DYNAMIC RAM· MSM3732-AS/RS---------------

BLOCK DIAGRAM

'-"---WE

Column t - - - - - - - - J \ ,
Address
Buffers r--------vl.......,_ _ _ _--.-..J

Dout

Row
Address
Buffers

Memory
Cells

.-..----Din

y-- '------'

VSS--V
CC-_

On chip VBB

ABSOLUTE MAXIMUM RATINGS

(See Note)

Symbol

Value

Unit

VIN, VOUT

-1 to +7

V

Rating
Voltage on any pin relative to VSS
Voltage on Vee supply relative to VSS

Vec

-1 to +7

V

Operating temperature

Topr

o to 70

°e

Storage temperature

T stg

-55 to +150

°e

Po

1.0

W

50

mA

Power dissipation
Short circuit output current

Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure
to absolute maximum rating conditions for extended periods may affect device reliability.

RECOMMENDED OPERATING CONDITIONS
(Referenced to VSS)

Parameter

Supply Voltage

56

Symbol
Vee
VSS

Min.

Typ.

4.5
0

5.0
0

--

Max.

Unit

5.5
0

V
V

r------

Operating
Temperature

o

Input High Voltage, all inputs

VIH

2.4

6.5

V

Input Low Voltage, all inputs

VIL

-1.0

0.8

V

oOe to +70 e

I

- - - - - - - - - - - - - - - - . DYNAMIC RAM . MSM3732-AS/RS.
DC CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.)
Parameter

Min.

Max.

Unit

ICC1

45

mA

STANDBY CURRENT
Power supply current
(RAS = CAS = VIH)

ICC2

5.0

mA

REFRESH CURRENT
Average power supply current
(RAS cycling, CAS = VIH; tRC = min.)

ICC3

35

mA

PAGE MODE CURRENT*
Average power supply current
(RAS = VIL, CAS cycling; tpc

ICC4

42

mA

Symbol

OPERATING CURRENT*
Average power supply current
(RAS, CAS cycling; tRC = min.)

Notes

= min.)

INPUT LEAKAGE CURRENT
I nput leakage current, any input
(OV :::; VIN :::; 5.5V, all other pins not
under test = OV)

III

-10

10

J..LA

OUTPUT LEAKAGE CURRENT
(Data out is disabled,
OV :::; VOUT :::; 5.5V)

ILO

-10

10

J..LA

OUTPUT LEVELS
Output high voltage (IOH = -5 mAl
Output low voltage (lOL = 4.2 mAl

2.4

VOH
VOL

0.4

V
V

Note*: ICC is dependent on output loading and cycle rates. Specified values are obtained with the output open.

CAPACITANCE
(Ta

= 25°C, f = 1 MHz)
Max.

Unit

5

pF

10

pF

Parameter

Symbol

Typ.

Input Capacitance (Ao ~ A 7 , DIN)

CIN1

4.5

CIN2

7

COUT

5

7

pF

Input Capacitance (RAS, CAS, WE)
Output Capacitance (DOUT)
Capacitance measured with Boonton Meter.

57

.DYNAMIC RAM . MSM3732-AS/RS . 1 - - - - - - - - - - - - - AC CHARACTERISTICS
Notes 1, 2, 3

Under Recommended
Operating conditions

Parameter
Refresh period

tREF

Random read or write cycle time

11
I

Units

MSM3732-12

MSM3732-15

MSM3732-20

Min.

Min.

Min.

ms

Max.

Note

2

Max.
2

tRC

ns

240

270

330

tRWC

ns

240

270

330

Page mode cycle time

150

tpc

ns

Access time from R AS

tRAC

ns

Access time from CAS

170
120

tCAC

ns

Output buffer turn-off delay

tOFF

ns

Transition time

tT

RAS precharge time

tRP

RAS pulse width

tRAS

ns

120

RAS hold time

tRSH

ns

80

35

ns

3

35

ns

90

CAS precharge time

tcp

ns

50

CAS pulse width

tCAS

ns

80

CAS hold time

tCSH

ns

120

RAS to CAS delay time

tRCD

ns

20

CAS to RAS precharge time

tCRP

ns

0

Row Address set-up time

225
150

80
0

100
0

40

3

35

100
10,000

150

10,000

20
0

135

5,6

0

50

3

50

200

10,000

80
10,000

150
40

4,6

135

60
100

200

120

100

10,000

Max.
2

Read-write cycle time

--

-

Symbol

135

10,000

200
50

25

7

65

0

tASR

ns

0

0

0

Row Address hold time

tRAH

ns

20

20

25

Column Address set-up time

tASC

ns

0

0

0

Column Address hold time

tCAH

ns

40

45

55

Column Address hold time
referenced to RAS

tAR

ns

80

95

120

Read command set-up time

tRCS

ns

0

0

0

Read command hold time

tRCH

ns

0

0

0

Write command set-up time

twcs

ns

-10

-10

-10

Write command hold time

tWCH

ns

40

45

55

Write command hold time
referenced to RAS

tWCR

ns

80

95

120

Write command pulse width

twp

ns

40

45

55

Write command to RAS lead time

tRWL

ns

40

45

55

Write command to CAS lead time

tCWL

ns

40

45

55

Data-in set-up time

tDS

ns

0

0

0

Data-in hold time

tDH

ns

40

45

55

Data-in hold time referenced
to RAS

tDHR

ns

80

95

120

CAS to WE delay

tCWD

ns

50

60

80

8

RAS to WE delay

tRWD

ns

90

110

145

8

Read command hold time
referenced to R AS

tRRH

ns

20

20

25

58

8

I

- - - - - - - - - - - - - - - - D Y N A M I C RAM . MSM3732-AS/RSNOTES: 1 ) An initial pause of 100 IlS is required after power-up followed by any 8 RAS cycles (Examples; RAS
only) before proper device operation is achieved.
2) AC measurements assume tT = 5 ns.
3) VIH (Min.) and VIL (Max.) are reference levels for measuring timing of input signals. Also, transition
times are measured between VIH and VIL.
4) Assumes that tRCO < tRCO (max.1.
If tRCO is greater than the maximum recommended value shown in this table, tRAC will increase by
the amount that tRCO exceeds the values shown.
5) Assumes that tRCO < tRCO (max.)
6) Measured with a load circuit equivalent to 2 TTL loads and 100 pF.
7) Operation within the tRCO (max.) limit insures that tRAC (max.) can be met. tRCO (max.) is specified as a reference point only; if tRCO is greater than the specified tRCO (max.) limit, then access
time is controlled exclusively by tCAC.
8) twcs, tcwo and tRWO are not restrictive operating parameters. They are included in the data sheet
as electrical characteristics only; if twcs ~ twcs (min.), the cycle is an early write cycle and the data
out pin will remain open circuit (high impedance) throughout the entire cycle; if tcwo :;;:: tcwo
(min.) and tRWO > tRWO (min.) the cycle is read-write cycle and the data out will contain data read
from the selected cell; if neither of the above sets of conditions is satisfied the condition of the data
out (at access time) is indeterminate.

READ CYCLE TIMING

~---------------------tRC--------------------~~
~------·-------tRAS--------------~

RAS

. CAS

VIHVIL -

VIH VIL -

------~I ~------tAR------~.~1

------------------~~ ~----+--tCAS------~ r---r---------~
~------.--r---+-----~tCSH--------~

Addresses

WE

VIHVIL -

VIHVIL-

~tCAC----~
~-----------tRAC----------~~

°OUT

VOH-

tOFF

OPEN

VOL~"H", "L" = Don't Care

59

.DYNAMIC RAM· MSM3732-AS/RS.-------------WRITE CYCLE TIMING
(EARLY WRITE)

~-----------------tRC--------~------~

VIH - - - - - - - . J ~:=====-tA-R-----_-_--.-~-rtRAS---------tlPI
VIL-

Addresses V I H -

VIL -

V IH -

1 , - - - -..... 1

0.
Tr'I"J777".r777'7777~r'777\ 1 - 4 - - -

VIL-,~~~~~~~---r--~----~~~~~~~~~~~~~~~~

~---tDHR--~~

DOUT VOHVOL- ---------1

OPEN

READ-WRITE/READ-MODIFY-WRITE CYCLE

~---------------------tRWC--------------------~
---------------tRAS----------------~

VIHVIL-

~

tAR

--I

-----------------~.
---------------------~-----------tRSH-----------tRCD----~----------tCAS----------~

VI H _ --------+--..
VIL -

f""""--7---~

~----------~--~I tCSH----------------~

Addresses VV IH - ,

IL -

~ "H", "L" ==

60

Don't Care

- - - - - - - - - - - - - - - . D Y N A M I C RAM· MSM3732-AS/RS.
RAS ONLY REFRESH TIMING
(CAS: VIH,~ & DIN: Don't care)

RAS

Addresses

VIHVIL -

~ASR~

trtRAH

~:~ _~

Row Address

VOH DOUT

OPEN

VOL -

~ "H", "L" = Don't Care

PAGE MODE READ CYCLE

~----------------tRAS------------------~-

CAS

VIHVIL -

VIHAdresses VI L -

I

tOFF
DOUT VOH - - - - - - - -

~~~~

__---__

~~~--------~S~~

I

____

~~-t-R~-H-~~~~
~"H" ,"L"= Don't Care

61

.DYNAMIC RAM . MSM3732-AS/RS - . - - - - - - - - - - - - - PAGE MODE WRITE CYCLE

~-----------------tRAS----------------~~

Addresses VvlH-

IL-

lJMI'Rro>N:f}'XR

~"H", "L" = Don't Care

PAGE MODE, READ-MODIFY-WRITE CYCLE

RAS

VIH
VIL

CAS

VIH
VIL

Addresses

VIH
VIL

WE

VIH
VIL

DIN

VIH
VIL

DOUT VOH
VOL
~ "H" . "L"

62

=

Don't Care

- - - - - - - - - - - - - - - - - - O Y N A M I C RAM· MSM3732-AS/RSHIDDEN REFRFSH

Addresses

~:~ ~~~ ~tCAC
~tRAC

V OH
DOUT VOL ---OPEN

___-------------------------_ _ _ _ _ _V_a_l_id_D_a_ta_ _ _ __

DESCRIPTION
Address Inputs:
A total of fifteen binary input address bits are required
to decode any 1 of 32,768 storage cell locations within
the MSM3732. Eight row-address bits are established on
the input pins (Ao '""'-'A 7 ) and latched with the Row
Address Strobe (RAS). The seven column-address bits
(Ao through A 6 ) are established on the input pins and
latched with the Column Address Strobe (CAS). All
input addresses must be stable on or before the falling
edge of RAS. CAS is internally inhibited (or "gated")
by RAS to permit triggering of CAS as soon as the Row
Address Hold Time (tRAH) specification has been
satisfied and the address inputs have been changed from
row-addresses to column-addresses.
One Column Address (A 7 ) has to be fixed at logic "0"
(low level) for MSM3732L, and at logic "1" (high level)
for MSM3732H.

Write Enable:
The read mode or write mode is selected with the WE
input. A logic high (1) on WE dictates read mode;
logic low (0) dictates write mode. Data input is disabled when read mode is selected.

Data Input:
Data is written into the MSM3732 during a write or
read-write cycle. The last falling edge of WE or CAS is
a strobe for the Data In (DIN) register. In a write
cycle, if WE is brought low (write mode) before CAS,
DIN is strobed by CAS, and the set-up and hold times
are referenced to CAS. In a read-write cycle, WE will
be delayed until CAS has made its negative transistion.
Thus DIN is strobed by WE, and set-up and hold times
are referenced to WE.

Data Output:

a fan-out of two standard TTL loads. Data-out is the
same polarity as data-in. The output is in a high impedance state until CAS is brought low. In a read cycle,
or read-write cycle, the output is valid after tRAC from
transition of RAS when tRCO (max.) is satisfied, or
after tCAC from transition of CAS when the transition
occurs after tRCD (max.). Data remain valid until CAS
is returned to a high level. In a write cycle the identical
sequence occurs, but data is not valid.

Page Mode:
Page-mode operation permits strobing the row-address
into the MSM3732 while maintaining RAS at a logic
low (0) throughout all successive memory operations in
which the row-address doesn't change. Thus the power
dissipated by the negative going edge of RAS is saved.
Further, access and cycle times are decreased because
the time normally required to strobe a new row-address
is eliminated.

Refresh:
Refresh of the dynamic memory cells is accompl ished
by performing a memory cycle at each of the 128 rowaddresses (Ao -A 6 ) at least every two milliseconds.
During refresh, either VIL or VIH is permitted for A 7 •
RAS only refresh avoids any output during refresh
because the output buffer is in the high impedance
state unless CAS is brought low. Strobing each of 128
row-addresses with RAS will cause all bits in each rwo
to be refreshed. Further HAS-only refresh results in a
substantial reduction in power dissipation.

Hidden Refresh:
RAS ONLY REFRESH CYCLE may take place while
maintaining valid output data. This feature is referred
to as Hidden Refresh.
Hidden Refresh is performed by holding CAS as VIL
from a previous memory read cycle.

The output buffer is three-state TTL compatible with

63

• DYNAMIC RAM . MSM3732-AS/RS . - - - - - - - - - - - - - TYPICAL CHARACTERISTICS
Access time from RAS
(Relative value) v.s. Ta

Access time from RAS
(Relative value) v.s. Vee

>
o
Lri
II

"'"

1.1

S

2:

~ 1.0

.g:
1
2:

l

Ta=25°C

0.9

u

«

°In

'"

4.5

i'

1.1

N

V

II

co
l-

t)

~

«

~

....a:

4.0

Vcc = 5.0V

(3

5.0

5.5

-

1.0

....a:

.~

./

(;

I-

U
«
....a:

0.9

o

6.0

25

75

50

Vcc[V]

Access time from CAS
(Relative value) v.s. Vee

ICC1 hRAS: Constant)
v.s. Vee
50~--~----~----~--~

>
o
Lri

1 .1

I------'lk-----"r---t----f

o
o

co

~

u
«
u

«E

1.0t----~~-~-~+---;

.~
Q)

~

0-

Uo

Q

>
«

Ta = 25°C
I
tRAS = 140 ns
40 t-----+--_+_

0.9 t-------1I----f3~-:1Ir--~

U

U 20t-----4~__~~-+--~

1oo0ns

U

8

4.0

5.5

6.0

4.5

4.0

ICC1 (tRAS: Constant)
v.s. Cycle rate

5.5

6.0

ICC1 hRAS: Constant)
v.s. Ta
50~~-~---~--~~

50~--~----~----~-~

Ta = 25°C

«

5.0
Vee [V]

Vee [V]

I

tRAS = 140 ns
VOO = 5.5V
E 40 t-----+----+----.-.n.-----1
5.0V
c:
4.5V
o
.;;

:;r:
E

Vee = 5.5V
I
I
tRAS = 140 ns
tR
40

~

Q)

0.

Q

U

20 t---?~---+-----+_---1

U

2

3

4

Cycle Rate (1/tRC) [MHz]

64

5

o

25

50

75

- - - - - - - - - - - - - - - . O Y N A M I C RAM . MSM3732-AS/RS.

ICC1 (tRP: Constant)
v.s. Cycle rate

ICC1 (tRP: Constant)
v.s. Vee

50r---~-----r---~----'

50~--~----~----~--~

<(

E

Ta= 25 C
tRP= lOOns

Ta = 25°C
tRP = 100 ns
401-----+---+--

co

co

4.5V

'';;

'';;

~

~

c.

c.

Q)

Q)

2

U
()

20~~~~-+--~---~

4.0

U
()
2

6.0

5.5

5.0

4.5

2

3

5

4

Vee [V]

Cycle Rate (1/tRC) [MHz]

ICC1 (tRP: Constant)
V.s. Ta

ICC2 (MSM3764-12)
V.s. Vee

50~~--~--~--~~

Vee = 5.5V
tRP = 100'ns

VIH = max.

5.0~----t----+----+-----l
<{

40 I--~=---..r.=---

co

.~

E
~

301---"......~~---+:~~........-i

Q)

c:
co

§

c.

2
U

4.01-------+--

-6

3.0~---4-~~~~+---~

N
20~+---~----r~~~-i

()
()

2.01--~---+--~---+---4

-

()

o

50

25

4.0

75

4.5

5.0

5.5

6.0

Vee [V]

ICC2 (MSM3764-15/-20)
v.s. Vee

ICC2 V.S. Ta

VIH: max.

~
E

5.0
<{

E

~ 4.0

>

-6c:

co

§

3.0

N

()
()

2.0
4.0

-4.5

:fa

---

O°C
25°C
!=;o-C

==

--

-

75°C
~~
6.0
5.0
5.5

4.0~~---4---~----+--4

.n

-6c:
!!!
~

3.0~~...::---+--+-~~

N
()
()

-

2.01--+---+--+-....::::!Ioo,~

o

75

Vee [V]

65

-DYNAMIC RAM . MSM3732-AS/RS - . - - - - - - - - - - - - - -

ICC3 hRAS: Constant)
v.s Vee

ICC3 hRAS: Constant)
v.s. Cycle rate

40r---~-----T----~--~

Ta = 25°C
tRAS = 140 ns

40~--~----~----~--~

<
..§.

30~---+----+-~.

Ta = 25°C
tRAS = 140 ns
30r----+----~----~--~

Qj
(j

>

U

.r:.
en

~CIJ

~M

u
.9

10 L.__--4---~~===*====~

4.5

4.0

5.0

6.0

5.5

2

Vee [V]

Cycle rate (lItRe) [MHz]

ICC3 (tRAS: Constant)
v.s. Ta

ICC3 (tRP: Constantl
v.s. Vee

40~~----r---~----_r~

«

E

5

4

3

Vee = 5.5VI
tRAS = 140 ns
30~~~~~--~·----~~

40~--~----~----~----~



u

~

~CIJ
a:

10~--~----_+----~----~
M

M

U
U

U
U

o

4.5

4.0

75

5.0

5.5

6.0

Vee [V]

ICC3 (tRp: Constant)
V.s. Ta

ICC3 (tRP: Constant)
v.s. Cycle rate

40~-r_--.--_r---._,

«

«

E

E

Qj

Cii
(j
>

5.0V
4.5V

U

~
u

.r:.
(II

~

~CIJ
a:

~CIJ
a:
M 10~--~-----+----~----~

u
u

M

u

30 ~~=----'t--

~==1=--~~~
20~~~--~~--~~

10~~---~--~-----+~

u

L-~

2

3

4

Cycle rate (1 /tpC) [MHz]

66

5

o

_ _ _ _~_ _~~_ _~~

25

50

75

- - - - - - - - - - - - - - - - - . O Y N A M I C RAM· MSM3732-AS/RS.

ICC4 (tCAS: Constant)
v.s. Cyel e rate

ICC4 (tCAS: Constant)
V.s. Vee
Ta = 25°C
tCAS = 100 ns

:;{
E

~

E.

Ta = 25°C
tCAS = 100 ns
40
Vee = 5.5V

Q)

~

u 30
Q)

Cl

co

e:.

v 20
u

u

4.0

5.0

4.5

2

6.0

5.5

6

4

Cycle rate (1/tpC) [MHz]

Vee [V]

ICC4 (tCAS: Constant)
V.s. Ta

ICC4 (tcp: Constant)
V.s. Vee

~

:;{

E

E

Q)

Q)

(j

Ta = 25°C
tcp = 50 ns
40~---+----+---~~

(j

u>- 30

>- 30

u

Q)

Q)

Cl

Cl

co

co
~

e:.

v 20
u
u

v
u 20

~

o

25

75

50

4.0

4.5

5.5

5.0

6.0

Vee [V]

ICC4 (tcp: Constant)
V.s. Ta

ICC4 (tCP: Constant)
V.s. Cycle rate
Ta = 25°C
tcp = 50 ns
~
E 40

~
E

Q)

Q)

C3

Vee = 5.5V/
tcp = 50 ns
40~~----~---+-----+~

(j

u>- 30

u>-

Q)

Q)

Cl

Cl

co

co

e:.

e:.

v 20
u

v

u
u

~

2

4

6

o

25

50

75

Cyele rate (1 /tpC) [MHz]

67

.DYNAMIC RAM· MSM3732·AS/RS.---------------

Address Input
v.s Vee

~

Data Input
v.s. Vee

2.0

5'
Qi

Qi

> 1.5

~

~
....

0.

0.

....:::l

-=

2.0

:::l

c:

1.0

4.0

4.5

5.0

5.5

6.0

4.0

4.5

Vee [V]

Address Input
v.s. Ta

I

Ta = 25°C

Vee

2.0

5'

Qi

I

=

5.0V

2.0

VIH min

Qi

~
....:::l

> 1.5

~

VIL max

....

:::l

0.

-=

6.0

Vee [V]

Clock Input
v.s. Vee

5'

5.5

5.0

0.

-=

1.0

4.5

4.0

5.5

5.0

1.0

o

6.0

25

50

75

Vee [V]

Clock Input
v.s. Ta

Data Input
v.s. Ta

.I

J

.I

5'

2.0

5'

Qi

~

....:::l

~
....

I
VIL max

0.

c:

0.

-=

68

25

50

VIHmin
1.5

:::l

1.0

o

2.0

Qi

VIH min

1.5

J.

Vee = 5.0V

Vee = 5.0V

75

VIL max

1.0

o

25

50

75

-------------~.DYNAMIC

RAM· MSM3732-AS/RS.

RAS/CAS CYCLE LONG RAS/CAS CYCLE RAS ONLY CYCLE PAGE MODE CYCLE
RAS
CAS

r\

I

t

\

~

\~

I

J

\

\. ~ J rl -

~

~

80

II

60
ICC
[rnA] 40

(1 1~

20

'-"

~

h

...

:A

lJ ~ f\ )\ \1 \~ \
\)

-:v

it

\

!

J\

\ U N\,. \ -

Il

!/ \
~

J~

V

\.

J~ "\~
v

50 ns/div

69

• DYNAMIC RAM . MSM3732-AS/RS . - - - - - - - - - - - - - MSM3732 Bit MAP (Physical-Decimal) [PS-1]

/
191 190
255 255

129 128
255 255

192 193
255 255

254 255
255 255

63
255
63
254

62
255
62
254

1 0
255 255

64 65
255 255

1 0
254 254

127
255
127
254

191
254
191
253

190
254
190
253
62
253
62
252

129
254
129
253
1
253
1
252
129
252

64 65
254 254
192 193
254 254

126
255
126
254

192 193
253 253

254
254
254
253

255
254
255
253

64
253
64
252
192
252

126
253
126
252
254
252

127
253
127
252
255
252

63
253
63
252
191 190
252 252
191 190
251 251

-

128
254
128
253
0
253
0
252
128
252

'"'

129 128
251 251

\

MSM3732L BIT MAP
[A7 column = "LuI

MSM3732H BIT MAP
[A7 column = "H"I

65
253
65
252
193
252

254 255
251 251

192 193
251 251

190
127
62
127
62
126

129 128
127 127

r-e--

1 0
127 127
1 0
126 126

~

191 190
126 126

129 128
126 126

~

191
125
63
125
63
124
191
124

129
125
1
125
1
124
129
124

191
127
63
127
63
126

190
125
62
125
62
124
190
124

191 190
123 123

~

128
125

~

0
125
0
124
128
124

>-&-

~

PIN 16

\

254 255
127 127

r 64 65

126 127
127 127
126 127
'126 126

127 127
64 65
126 126
192 193
126 126

r

254 255
126 126
254 255
125 125

192 193
125 125
~ 64 65
125 125
65
:r 64 124
124
192 193
124 124
192 193
123 123

~

129 128
123 123

0

192 193
127 127

~

126
125
126
124

127
125
127
124

254
124
254
123

255
124
255
123

(Column)

I

1 0
130 130

64
131
64
130

193
132
193
131
65
131
65
130

254255
13 2 132
25 4 255
13 1 131
126 127
13 1 131
126 127
13 0130

191 190
4 4
191 190
3 3
63 62
3 3
63 62
2 2

129 128
4
4
129 128
3 3
1 0
3
3
1 0
2
2

191 190
130 130

129 128
130 130

192 193
130 130

25 4 255
13o 130

191 190
2 2

129 128
2 2

~

190
129

129 128
129 129

193
129

191 190
1 1

129 128
1
1

~

192 193
1
1

254 255
1
1

1 0
129 129

65
129

2 54
129
126
129

255
129

62
129

192
129
64
129

127
129

63 62
1 1

~

64 65
1 1

63 62
128 128
191 190
128 128

1 0
128 128
129 128
128 128

64
128
192
128

65
128
193
128

126 127
128 128
2 54 255
128128

63 62
0 0
191 190
0 0

126 127
1 1
126 127
0 0

191 190
132 132

129 128
132 132

191 190
131 131

129 128
131 131

63 62
131 131
63 62
130 130

1 0
131 131

191
129
63
129

192
132
1:32
131

rn [[]1/&m
• R.f",h Add""
(63 - 0)

,

.1

Din
(Positive)

I

6

I\"'f"'h Add"
I

01

2

(64 -> 127)

I

01

L

O2

A
8

B
70

:

Cell

A = Row Address (Decimal)
8 = Column Address (Decimal)

Sub Amp (C

=

Number of Bus Line)

0
1

0
0
129 128
0
0

4r

r

4r

r

254
4
254
3
126
2
126
2

65
3
65
2
193
2

~

127
3
127
2

254 255
2 2

64 65
0 0
192 193
0 0

~

255
4
255
3

254 255
0 0

.R.f",h Add"'!, ~~'f"'h Add",,_

I

(63-0)

!

Din
(Negative)

0

~

193
4
193
3

[I] ill I~ [I] ill

~

Pin 8

1
1
1
0

192
4
192
3
64
3
64
2
192
2

~

(Positive)

04

L

_
0

3

(64->127)

I

ill

I

I

Om

0

3

04

I

~

Din
(Negative)

(Row)
Word Driver

Sense Amp

OK.I

semiconductor

MSM3764-AS/RS
65,536-BIT DYNAMIC RANDOM ACCESS MEMORY

GENERAL DESCRIPTION
The Oki MSM3764 is a fully decoded, dynamic NMOS random access memory organized as 65536 one-bit words.
The design is optimized for high-speed, high performance applications such as mainframe memory, buffer memory,
peripheral storage and environments where low power dissipation and compact layout is required.
Multiplexed row and column address inputs permit the MSM3764 to be housed in a standard 16 pin DIP. Pin-outs
conform to the JEDEC approved pin out.
The MSM3764 is fabricated using silicon gate NMOS and Oki's advanced Double-Layer Polysilicon process. This
process, coupled with single-transistor memory storage cells, permits maximum circuit density and minimum chip
size. Dynamic circuitry is employed in the design, including the sense amplifiers.
Clock timing requirements are noncritical, and power supply tolerance is very wide. All inputs and output are TTL
compatible.

FEATURES
.65,536 x 1 RAM, 16 pin package
.Silicon-gate, Double Poly NMOS, single transistor cell
• Row access time,
120 ns max (MSM3764-12)
150 ns max (MSM3764-15)
200 ns max (MSM3764-20)

•
•
•
•
•
•

• Cycle time,
240 ns min (MSM3764-12)
270 ns min (MSM3764-15)
330 ns min (MSM3764-20)
• Low power: 248 mW active,
28 mW max standby
.Single +5V Supply, ±10% tolerance

•
•
•

All inputs TTL compatible, low capacitive load
Three-state TTL compatible output
"Gated" CAS
128 refersh cycles
Common I/O capability using "Early Write"
operation
Output unlatched at cycle and allows extended page
boundary and two-dimensional chip select
Read-Modify-Write, RAS-onlyrefresh, and PageMode capability
On-chip latches for Addresses and Data-in
On-chip substrate bias generator for high
performance

PIN CONFIGURATION

H

NC

vss

Din

CAS

WE

Dout

Ao""-A,
RAS

Address Inputs

A6"

CAS

WE

Column Address Strobe
Write Enable

Din

Data Input

Ao'

A3 "

A2 "

A4 "

Pin Names

Function
Row Address Strobe

Dout

Data Output

VCC

Power (+5V)
Ground (OV)

AI"

As"

VSS

Vee

A7

• Refresh Address

71

• DYNAMIC RAM . MSM3764-AS/RS . - - - - - - - - - - - - - - BLOCK DIAGRAM

"'-"'---WE

Dout
Row
Address
Buffers
Memory
Cells

t------Din

y-'___

V
CC----..
VSS---

-..J

On chip VBB

ABSOLUTE MAXIMUM RATINGS

(See Note)

Rating
Voltage on any pin relative to VSS

Symbol

Value

VIN, VOUT

-1 to +7

V

Vee

-1 to +7

V

Voltage on Vee supply relative to VSS

Unit

Operating temperature

Topr

o to 70

°e

Storage temperature

T stg

-55 to +150

°e

PD

1.0

W

50

mA

Power dissipation
Short circuit output current

Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure
to absolute maximum rating conditions for extended periods may affect device reliability.

RECOMMENDED OPERATING CONDITIONS
(Referenced to VSS)

Parameter
Supply Voltage

72

Symbol
Vee
VSS

Min.

Typ.

Max.

Unit

4.5
0

5.0
0

5.5
0

V
V

Input High Voltage, all inputs

VIH

2.4

6.5

V

Input Low Voltage, all inputs

VIL

-1.0

0.8

V

Operating
Temperature

OOeto+70oe

- - - - - - - - - - - - - - - - . DYNAMIC RAM . MSM3764-AS/RS.
DC CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.)
Parameter

ICC1

STANDBY CURRENT
Power supply current
(RAS = CAS = VIH)

ICC2

REFRESH CURRENT
Average power supply current
(RAS cycling, CAS = VIH; tRC

Min.

Symbol

OPERATING CURRENT*
Average power supply current
(RAS, CAS cycling; tRC = min.)

Max.

Unit

45

mA

5.0

Notes

mA

ICC3

35

mA

PAGE MODE CURRENT*
Average power supply current
(RAS = VIL, CAS cycling; tpc = min.)

ICC4

42

rnA

INPUT LEAKAGE CURRENT
I nput leakage current, any input
(OV ~ VIN ~ 5.5V, all other pins not
under test = OV)

III

-10

10

IJ.A

OUTPUT LEAKAGE CURRENT
(Data out is disabled,
OV ~ VOUT ~ 5.5V)

ILO

-10

10

IJ.A

= min.)

OUTPUT LEVELS
Output high voltage (IOH = -5 mAl
Output low voltage (IOL = 4.2 mAl

2.4

VOH
VOL

0.4

V
V

Note*: ICC is dependent on output loading and cycle rates. Specified values are obtained with the output open.

CAPACITANCE
(Ta= 25°C,f= 1 MHz)
Parameter

Symbol

Typ.

Max.

Unit

Input Capacitance (Ao - A 7 , DIN)

CIN1

4.5

5

pF

Input Capacitance (RAS, CAS, WE)

CIN2

7

10

pF

Output Capacitance (DOUT)

COUT

5

7

pF

Capacitance measured with Boonton Meter.

73

• DYNAMIC RAM . MSM3764-AS/RS . - - - - - - - - - - - - - AC CHARACTERISTICS

Notes 1, 2, 3

Under Recommended
Operating conditions

Parameter
Refresh period

Symbol

Units

MSM3764-12

MSM3764-15

Min.

Min.

MSM3764-20
Note

Max.

Max.

Min.

tREF

ms

Random read or write cycle time

tRC

ns

240

270

330

Read-write cycle time

tRWC

ns

240

270

330

tpc

ns

150

170

225

Page mode cycle time

-Access time from RAS

2

2

Max.
2

tRAC

ns

120

150

200

4,6

Access time from CAS

tCAC

ns

80

100

135

5,6

Output buffer turn-off delay

tOFF

ns

0

35

0

40

0

50

Transition time

tT

ns

3

35

3

35

3

50

RAS precharge time

tRP

ns

90

RAS pulse width

tRAS

ns

120

RAS hold time

100
10,000

150

120
10,000

200

tRSH

ns

80

100

135

CAS precharge time

tcP

ns

50

60

80

CAS pulse width

tCAS

ns

80

CAS hold time

tCSH

ns

120

RAS to CAS delay time

tRCD

ns

20

CAS to RAS precharge time

tCRP

ns

0

10,000

100

10,000

150
40

20
0

135

10,000

10,000

200
50

25

65

7

0

Row Address set-up time

tASR

ns

0

0

0

Row Address hold time

tRAH

ns

20

20

25

Column Address set-up time

tASC

ns

0

0

0

Column Address hold time

tCAH

ns

40

45

55

Column Address hold time
referenced to R AS

tAR

ns

80

95

120

Read command set-up time

tRCS

ns

0

0

0

Read command hold time

tRCH

ns

0

0

0

Write command set-up time

twcs

ns

-10

-10

-10

Write command hold time

tWCH

ns

40

45

55

Write command hold time
referenced to RAS

tWCR

ns

80

95

120

Write command pulse width

twp

ns

40

45

55

Write command to RAS lead time

tRWL

ns

40

45

55

Write command to CAS lead time

tCWL

ns

40

45

55

Data-in set-up time

tDS

ns

0

0

0

Data-in hold time

tDH

ns

40

45

55

Data-in hold time referenced
to RAS

tDHR

ns

80

95

120

CAS to WE delay

8

tCWD

ns

50

60

80

8

RAS to WE delay

tRWD

ns

90

110

145

8

Read command hold time
referenced to R AS

tRRH

ns

20

20

25

74

- - - - - - - - - - - - - - - - . DYNAMIC RAM . MSM3764-AS/RS.
NOTES: 1 ) An initial pause of 100 J.LS is required after power-up followed by any 8 RAS cycles (Examples; RAS
only) before proper device operation is achieved.
2) AC measurements assume tT = 5 ns.
3) VIH (Min.) and VIL (Max.) are reference levels for measuring timing of input signals. Also, transition
times are measured between VIH and VIL.
4) Assumes that tRCO < tRCO (max.).
If tRCO is greater than the maximum recommended value shown in this table, tRAC will increase by
the amount that tRCO exceeds the values shown.
5) Assumes that tRCO < tRCO (max.)
6) Measured with a load circuit equ ivalent to 2 TTL loads and 100 pF.
7) Operation within the tRCO (max.) limit insures that tRAC (max.) can be met. tRCO (max.) is specified as a reference point only; if tRCO is greater than the specified tRCO (max.) limit, then access
time is controlled exclusively by tCAC.
8) twcs, tcwo and tRWO are not restrictive operating parameters. They are included in the data sheet
as electrical characteristics only; if twcs ~ twcs (min.), the cycle is an early write cycle and the aata
out pin will remain open circuit (high impedance) throughout the entire cycle; if tcwo ~ tcwo
(min.) and tRWO > tRWO (min.) the cycle is read-write cycle and the data out will contain data read
from the selected cell; if neither of the above sets of conditions is satisfied the condition of the data
out (at access time) is indeterminate.

READ CYCLE TIMING

~---------------------tRC--------------------~~

~--------------tRAS---------------;~

RAS

VIHVIL-

------~I ~------tAR------~.~1

~----r--tRSH-------;~

CAS

VIH VIL -

------------------~~ ~----+--tCAS------~ ~~r_--------~
~-------+---+-----+tCSH--------~

Addresses

WE

VIHVIL -

VIHVIL-

1---tCAC------I
~-----------tRAC----------~~

°OUT

VOHVOL-

tOFF

OPEN
~ "H", "L" = Don't Care

75

• DYNAMIC RAM . MSM3764-AS/RS.-------------WRITE CYCLE TIMING
(EARLY WRITE)

~-----------------tRC--------~------~
lr---"""I

VI H - - - - - - - , [ :::=====-tA-R-----___
- ---<-.,-rtRAS-------tl.,j
RAS

VIL~~---tRSH--~.,

________+-______~---~~------tCAS----~~
CAS

VIHVIL-

Addresses V I H VIL

r--~----~

__

1)

-1/1

V IH -

'TTrJ"T7'T'.~'TTrJ-rrl:r'7'77\. ~-­

VIL-.~""~~~~~--_+--~----~~~~~~~~~~~~~~~~

VIH-;'::
VIL-,-,-,-,-I...L.I..J..<...t..L.J;..J...I..L.J.~"""""I...L.I..J.'"
~---tDHR-------<~

DOUT

VOHVOL -

-----------------1

OPEN

READ-WRITE/READ-MODIFY-WRITE CYCLE

Addresses VV IH -

IL -

~ "H", "L" = Don't Care

76

- - - - - - - - - - - - - - - . DYNAMIC RAM . MSM3764-AS/RS.
RAS ONLY REFRESH TIMING
(CAS: VIH,~ & DIN: Don't care)

--

RAS

V'HV'L-

~:~ _~

~RAH

tASR

Addresses

Row Address

VOH DOUT

OPEN

VOL -

~ "H", ilL" = Don't Care

PAGE MODE READ CYCLE

1-4---------tRAS-------------<~

VIHAdresses V I L -

~"H","L"=Don't Cars

77

• DYNAMIC RAM . MSM3764-AS/RS . - - - - - - - - - - - - - - PAGE MODE WRITE CYCLE

~-----------------tRAS----------------~~

RAS

VIHVIL -

Addresses ~ I H - '7,\jilR(ilii'tIi?\.l'C

~~"""".u.J.+",-,.u ~=-=1'-"'~~"""'"'".:..:.§?:...t.I

IL -

~"H", "L" = Don't Care

PAGE MODE, READ-MODIFY-WRITE CYCLE

IJ

RAS

VIH
VIL

CAS

VIH
VIL

Addresses

VIH
VIL

WE

VIH
VIL

DIN

VIH
V'IL

VOH
DOUT
VOL

/

1'r- tCAC~OFFI_
rtcAch
OPEN

~

~ "H" . "L"

78

=

Don't Care

- - - - - - - - - - - - - - - - . DYNAMIC RAM . MSM3764-AS/RS.
HIDDEN REFRFSH
-------+----RAS only cycle

Addresses

~: ~

WIII////II!t
~tCAC.____________________________
~tRAC

VOH
DOUT VOL ----OPEN

~

_ _ _ _ _ _V_a_l_id_D_a_ta_ _ _ __

~ "H", "L" = Don't Care

DESCRIPTION
Address Inputs:
A total of sixteen binary input address bits are required
to decode any 1 of 65536 storage cell locations within
the MSM3764. Eight row-address bits are established on
the input pins (Ao "'-'A 7 ) and latched with the Row
Address Strobe (RAS). The eight column-address
bits are established on the input pins and latched with
the Column Address Strobe (CAS). All input addresses
must be stable on or before the falling edge of RAS.
CAS is internally inhibited (or "gated") by RAS to
permit triggering of CAS as soon as the Row Address
Hold Time (tRAH) specification has been satisfied and
the address inputs have been changed from row-addresses
to column-addresses.

Write Enable:
The read mode or write mode is selected with the WE
input. A logic high (1) on WE dictates read mode;
logic low (0) dictates write mode. Data input is disabled when read mode is selected.

Data Input:
Data is written into the MSM3764 during a write or
read-write cycle. The last falling edge of WE or CAS is
a strobe for the Data In (DIN) register. In a write
cycle, if WE is brought low (write mode) before CAS,
DIN is strobed by CAS, and the set-up and hold times
are referenced to CAS. I n a read-write cycle, WE will
be delayed until CAS has made its negative transistion.
Thus DIN is strobed by WE, and set-up and hold times
are referenced to WE.

Data Output:
The output buffer is three-state TTL compatible with
a fan-out of two standard TTL loads. Data-out is the

same polarity as data-in. The output is in a high impedance state until CAS is brought low. In a read cycle,
or read-write cycle, the output is valid after tRAC from
transition of RAS when tRCD (max.) is satisfied, or
after tCAC from transition of CAS when the transition
occurs after tRCD (max.). Data remain valid until CAS
is returned to a high level. In a write cycle the identical
sequence occurs, but data is not valid.

Page Mode:
Page-mode operation permits strobing the row-address
into the MSM3764 while maintaining RAS at a logic
low (0) throughout all successive memory operations in
which the row-address doesn't change. Thus the power
dissipated by the negative going edge of RAS is saved.
Further, access and cycle times are decreased because
the time normally required to strobe a new row-address
is eliminated.

Refresh:
Refresh of the dynamic memory cells is accomplished
by performing a memory cycle at each of the 128 rowaddresses (Ao -A 6 ) at least every two milliseconds.
During refresh, either VIL or VIH is permitted for A 7 •
RAS only refresh avoids any output during refresh
because the output buffer is in the high impedance
state unless CAS is brought low. Strobing each of 128
row-addresses with RAS will cause all bits in each rwo
to be refreshed. Further RAS-only refresh results in a
substantial reduction in power dissipation.

Hidden Refresh:
RAS ONLY REFRESH CYCLE may take place while
maintaining valid output data. This feature is referred
to as Hidden Refresh.
Hidden Refresh is performed by holding CAS as VIL
from a previous memory read cycle.

79

.DYNAMIC RAM· MSM3764-AS/RS-_-------------TYPICAL CHARACTERISTICS
Access time from RAS
(Relative value) v.s. Ta

Access time from RAS
(Relative value) V.s. Vee

>
o
Lri
II

Ta

=

.~

1.1

CJ
CJ

>

U
« 1.0
a:

25°C

°NLO

""",

0.9

u

«

a:

+'

4.0

4.5

Vcc = 5.0\1
~

1.1

II

co
l-

t)

'"

~

'8
C.

l

u

5.0

~

«

1.0

co
IU

0.9

~

.~

~

V

«
a:

+'

5.5

o

6.0

25

75

50

Vcc[V1

Ta[OC1

Access time from CAS
(Relative value) V.s. Vee

ICC1 (tRAS: Constant)
v.s. Vee
50~--~----~----~--~

o>
Lri

1.11------Ik--~---_r_--l

CJ
CJ

>
U
u«
.:::

uCJ
2:

1.0 t--------'~-->\t--_JllE_r_--l

~

Ta = 25°C
I
tRAS = 140 ns
40 t-----+----t-

co

.~
Q)

0.

Q
0.91-----t----P~-~-~

u

U 201----~~__~~--+---~

U

«
9
4.0

4.5

5.0

5.5

1 000 os
4.5

4.0

6.0

D

ICC1 (tRAS: Constant)
V.s. Cycle rate

6.0

50~~--~-----r---~~

Ta = 25°C
I

tRAS = 140 ns

5.5

ICC1 (tRAS: Constant)
V.s. Ta

50~-~---r----~--~

~

5.0
Vee [V1

Vee [V1

VDD = 5.5V

E 40 t----+---+----ho-~
5.0V
c:
4.5V
o

~
E

Vee = 5.5V
I
I
tRAS = 140 ns

40 t-=r--~=Efitc

';;
~

Q)

0.

Q

U

20 I--.....,~"c;---+----_r_-~

U

2

3

4

Cycle Rate (1ItRe) [MHz)

80

5

o

25

50

75

- - - - - - - - - - - - - - __ DYNAMIC RAM . MSM3764-AS/RS.

ICC1 (tRP: Constant)
V.s. Cycle rate

ICC1 (tRP: Constant)
V.s. Vee
50~--~-----r----~---'

«

E

50~--~----~----~--~

Ta = 25°C
tRP = foo ns
401-----+----+_

Ta= 25 C
I
tRP = 100 ns

co

co

4.5V

.;;
co

.;;

f?CIl

~

a.

a.

Q

Q

u
u
2

6.0

5.5

5.0

4.5

4.0

3

5

4

Vee [V]

Cycle Rate (1!tRcl [MHz]

ICC1 (tRP: Constant)
v.s. Ta

ICC2 (MSM3764-12)
V.s. Vee

50~~--~-----r----~~

«

E

Vee = 5.5V
tRP = 100lns

VIH

«

40~~::::IIII-..I..",.---

=

max.

5.0t------t-----+-----+-----i

E

]- 4.0 ...-----+---

~

o
.;;

-6
c:

~

co

CIl

§

a.

Q

3.0t-----+--~~~~+--~

~

u
u

U

- 2.01-----+-----+-----+-----i

o

50

25

4.0

75

5.0

4.5

5.5

6.0

Vee [V]

ICC2 (MSM3764-15/-20)
v.s. Vee

n

ICC2 V.S. Ta

VIH: max.

.!l

-6
c:
~

!:!2. 3.0
N
U
U

-

2.0
4.0

Ta

--

== O°C

25°C
E:\O'C

-

4.5

-

7So C

Vee [V]

--

c:

co

§

-

--

~
5.5
5.0

4.0

-6

3.0

N

U

u
2.0

6.0

0

25

75

Ta rOC]

81

• DYNAMIC RAM . MSM3764-AS/RS ••- - - - - - - - - - - - - -

ICC3 (tRAS: Constant)
v.s Vee

ICC3 (tRAS: Constant)
v.s. Cyele rate

40r---~----~----~--~

Ta = 25°C
tRAS = 140 ns
E
301-----+-----+-..,...
OJ
(j
>

<

40~--_r----~--~----~



(j

>

U
.s::.

U
.s::.

en

en

~
a:

~

(I)

Q)

a:

M

10r----+----~--~r_--~

u

U

o

75

50

25

4.0

4.5

5.5

5.0

6.0

Vee [V]

ICC3 {tRP: Constant)
v.s. Ta

ICC3 (tRP: Constant)
v.s. Cyele rate

40~-~--~----.----.-.



u

~

~
a:

Q)

M 10r---~-----r----+_--~

u

u

2

3

4

Cyele rate (1!tPC) [MHz]

82

5

o

25

50

75

- - - - - - - - - - - - - - - - - - - . DYNAMIC RAM . MSM3764-AS/RS.

ICC4 (tCAS: Constant)
v.s. Vee

ICC4 (tCAS: Constant)
v.s. Cycle rate

Ta = 25°C
tCAS = 100 ns

«

E

Ta = 25°C
tCAS = 100 ns
40
Vee = 5.5V

Q)

U

>
()

30

CIl

0)

co

e:.
o::t

()
()

4.0

4.5

5.0

20

6

4

2

6.0

5.5

Cycle rate (1ItpC) [MHz]

Vee [V]

ICC4 (tCAS: Constant)
v.s. Ta

ICC4 (tcp: Constant)
v.s. Vee
Ta = 25°C
tcp = 50 ns

~

E 40
Q)

Q)

u

(j

o

30 I--....._;::,--+-----:~I-!c~

>

()

Q)
0)

CIl

0)

co

~

(5

a..

20 t---+---+------'F-....~r--i

()

o

25

o::t

()
()

75

50

4.0

4.5

5.5

5.0

6.0

Vee [V]

ICC4 (tCP: Constant)
v.s. Cyele rate

:;(

E
Q)

u

o

ICC4 (tCP: Constant)
v.s. Ta

Ta = 25°C
tcp = 50 ns
401----+---~----+----4
Vee = 5.5V

nv

E

Vee = 5.5VI
tcp = 50 ns
40~~----r----+-----+~

Q)

u>

30 ~__-+____.....p~~T-:::::;o4;.;.;.5:::..V.=..t

()

20~--~----~----+----4

e:.
(5

CIl

CIl

0)

g

(5

:;(

0)

co

()

20t---+-----r----+~~

()

2

4

6

o

25

50

75

Cycle rate (1 /tpc) [MHz]

83

• DYNAMIC RAM . MSM3764-AS/RS . - - - - - - - - - - - - - - - -

Address Input

Data I"put
V.s. Vee

v.s Vee

>"

>"

Qj

Qj

..

1.5

-=

1.0

>

~

2.0

..

~

1.0 t----+---+-"".......-.=~.....",....

:::J
Q.

:::J
Q.

c:

1.5 ~~+----+--+----l

4.0

4.5

5.0

5.5

6.0

4.0

4.5

Vee [V]

5.5

5.0

6.0

Vee [V]

Clock Input

Address Input

v.s. Vee

v.s. Ta

V~=5.0J
>"

2.0

>"

2.0

VIH min

Qj

..

> 1.5

~

VIL max

:::J
Q.

1.0 ~~4----iI----t---~

4.0

4.5

5.5

5.0

-=

1.0

o

6.0

50

25

75

Vee [V]

-'

Data Input

Clock Input

v.s. Ta

V.s. Ta

J

J

>"

2.0

>"

Qj

..

~

:::J
Q.

84

25

50

..

-=

1.0

:::J
Q.

1.0

o

VIH min
1.5

~

VIL max

c:

2.0

Qj

VIH min

1.5

J.

Vee = 5.0V

Vee = 5.0V

75

VIL max

o

25

50

75

- - - - - - - - - - - - - - - . DYNAMIC RAM . MSM3764-AS/RS.
RAS/CAS CYCLE LONG RAS/CAS CYCLE RAS ONLY CYCLE PAGE MODE CYCLE
RAS

'"'\

I

~

I

CAS

J

\

\

\

\.

\- r--'

~

J r\ ~

80
I

60

n

ICC
[mAl 40

r\ lV lJ \

20
~

\J

.

f\

~

'\rJIr\rd \' \

It

\

\ ) "V~

50 ns/div

A

V'

1\

I
'- ~

I~

J~

I~\. ~v ~

'V

85

• DYNAMIC RAM . MSM3764-AS/RS . - - - - - - - - - - - - - MSM3764 Bit MAP (Physical-Decimal) [PS-1]

/
191 190
255 255

129 128
255 255

192 193
255 255

254 255
255 255

63
255
63
254

62
255
62
254

1 0
255 255
1 0
254 254

64 65
255 255

126
255
126
254

191
254
191
253

190
254
190
253
62
253
62
252
190
252

129 128
254 254
129 128
253 253
1 0
253 253
1 0
252 252
129 128
252 252

192
253
64
253
64
252
192
252

191 190
251 251

129 128
251 251

192 193
251 251

63
253
63
252
191
252

\

MSM3732L BIT MAP
[A7 column = "L"j

MSM3732H BIT MAP
[A7 column - "H"j

64 65
254 254
192 193
254 254

0

254 255
127 127

64 65
127 127
64 65
126 126
192 193
126 126

126 127
127 127

129 128
127 127

191 190
126 126

129 128
126 126

~

129
125
1
125
1
124
129
124

~

127
253
127
252
255
252

191 190
125 125
63 62
125 125
63 62
124 124
191 190
124 124

128
124

~

192 193
124 124

254 255
251 251

191 190
123 123

129 128
123 123

~

192 193
123 123

127
255
127
254

193
253

254 255
254 254
254 255
253 253

65
253
65
252
193
252

126
253
126
252
254
252

r--e--

1 0
127 127
1 0
126 126

~ ~

f-&- r

128
125
0
125
0
124

-e-

r

-e--

~

PIN 16 \

192 193
127 127

190
127
62
127
63 62
126 126

191
127
63
127

192
125
64
125

126
'126
254
126

127
126

254
124
254
123

255
124
255
123

255
126
254 255
125 125
126 127
125 125
126 127
124 124

193
125

65
125
64 65
124 124

(Column)

191 190
132 132
191 190
131 131

129 128
132 132
129 128
131 131

192
132
1:l2
131

193
132
193
131

63 62
131 131
63 62
130 130

1 0
131 131
1 0
130 130

64
131
64
130

65
131
65
130

191 190
130 130

129 128
130 130

191 190
129 129
63 62
129 129

129 128
129 129

63
128
191
128

1 0
128 128
129 128
128 128

~

62
128
190
128

~

~

129 128
4 4
129 128
3 3
1 0
3 3
1 0
2 2

255
132
255
131
126 127
131 131
126 127
130 130

191 190
4 4
191 190
3 3
63 62
3 3

191 190
2 2
191 190
1 1

129 128
2 2

192
4
192
~
3
64
f-&-~ 3
64
f-&-~ 2
192
~
2

129 128
1 1

~

1 0
1 1
1 0
0 0
129 128
0 0

63 62
2 2

192
129
64
129

193
129

254 255
130 130
254 255
129 129

65
129

126 127
129 129

63 62
1 1

64
128
192
128

65
128
193
128

126
128
254
128

127
128

63 62
0 0
191 190

192 193
130 130

'"'

1 0
129 129

254
132
254
131

255
128

0

0

~

193
4
193
3

254
4
254
3
126
2
126
2

65
3
65
2

255
4
255
3
127
3
127
2

193
2

254 255
2 2

192 193
1 1

254 255
1 1

f-e- r 641 651

126 127
1 1
126 127
0 0
254 255
0
0

64 65
0 0
192 193

~

~

0

0

ITI OJ
rn rnl/~'rn
, OJ ill 'I~'~"""h
7.
~""'h Add"".

• A.'",h Add .."

"

(63<--0)
I

Din
(Positive)

I

I

I

(

O2

01

01

0

(64----127)

'L
O2

~

86

:

Cell

I

~

Din
(Negative)

Pin 8
A
B

.A.""h Add"'l.

J

A = Row Address (Decimal)
B = Column Address (Decimal)

Sub Amp (C = Number of Bus Line)

(63 <-- 0)
~
Om
(Positive)

Add""

m

I

(

04

03

(64 ---- 127)

L

-0

3

'L
0

I

~

Din
4
(Negative)

( Row)

Word Driver

Sense Amp

OK.I

semiconductor

MSM37256-AS/RS
262,144-BIT DYNAMIC RANDOM ACCESS MEMORY

GENERAL DESCRIPTION
The Oki MSM37256 is a fully decoded, dynamic NMOS random access memory organized as 262,144 one-bit words.
The design is optimized for high-speed, high performance applications such as mainframe memory, buffer memory,
peripheral storage and environments where low power dissipation and compact layout is required.
Multiplexed row and column address inputs permit the MSM37256 to be housed in a standard 16 pin DIP, Pin-outs
conform to the JEDEC approved pin out.
The MSM37256 is fabricated using silicon gate NMOS and Oki's advanced VLSI Double-Layer Polysilicon process.
This process, coupled with single-transistor memory storage cells, permits maximum circuit density and minimum
chip size. Dynamic circuitry is employed in the design, including the sense amplifiers.
Clock timing requirements are noncritical, and power supply tolerance is very wide. All inputs and output are TTL
compatible.

FEATURES
.262,144 x 1 RAM, 16 pin package
• Silicon-gate, Double Poly NMOS, single transistor cell
• Row access time,
100 - 120 ns max
• Cycle time,
200 - 240 ns max
• Low power: 300 mW active,
28 mW max standby
• Single +5V Supply, ±10% tolerance

•
•
•
•
•
•
•
•
•

All inputs TTL compatible, low capacitive load
Three-state TTL compatible output
"Gated" CAS
256 refresh cycles
Common I/O capability using "Early Write"
operation
Output unlatched at cycle and allows extended page
boundary and two-dimensional chip select
Read-Modify-Write, RAS-only refresh, and PageMode capability
On-chip latches for Addresses and Data-in
On-ch ip su bstrate bias generator for high
performance

PIN CONFIGURATION

As

1

•

Vss

Din

CAS

WE

Dout

Ao

RAS

R ow Address Strobe

RAS

An*

CAS

Column Address Strobe

Ao*

A3*

WE

Write Enable

Al *

11

A4*

A,'

As'

Vee

A,*

Pin Names
~

As

Function
Address Inputs

Din

Data Input

Dout

Data Output

VCC

Power (+5V)

VSS

Ground (QV)

* Refresh Address

87

• DYNAMIC RAM . MSM37256-AS/RS ••r - - - - - - - - - - - - - - -

BLOCK DIAGRAM

Column
Address
Buffers

Ao - As

Dout

Row
Address
Buffers

VCC
VSS - - - -

88

y

Row
De-

Word
Drivers

On chip VBS

Memory
Cells

Din

MOS
STATIC
RAMS

OK.I

semiconductor

MSM2114LRS
4096-BIT (1024 x 4) STATIC RAM

GENERAL DESCRIPTION
The Oki MSM2114L is a 4096-bit static Random Access Memory organized as 1024 words by 4 bits using Oki's
reliable N-channel Silicon Gate MOS technology. It uses fully static circuitry and therefore requires no clocks or
refreshing to operate. Directly TTL compatible inputs, outputs and operation from a single +5V supply simplify
system designs. Common data input/output pins using three-state outputs are provided.
The MSM2114L series is offered in an 18-pin dual-in-line plastic (RS Suffix) package. The series is guaranteed for
operation from 0° C to 70° C.

FEATURES
• Low Power Dissipation
• Single +5V Supply (±10% Tolerance)
• High Density 300-mil 18-Pin Package

• Fully Static Operation
• Directly TTL Compatible
• Common I/O Capability using • N-channel Silicon Gate MOS Technology
Three-State Outputs
• Interchangeable with Intel 2114L Devices
2114L-3

2114L-2
Max. Access Time (NS)
Max. Power Dissipation (MW)

2114L

200

300

450

370

370

370

FUNCTIONAL BLOCK DIAGRAM
A,

----t=>--i

A'---L>--I
A,

----t=>--i

A,--

Vee
MEMORY ARRAY
64 x 64

ROW
SELECT

A, _ _-[>--;

A.,

---[>--;

PIN CONFIGURATION
A,

Vee

A,

A_

A,

A,

A,

A,

A"

1/0,

A,

1/0,

A,

1/0,

CS

1/0,

Vss

WE

Ao ~ Ay: Address Inputs
WE: Write Enable
CS: Chip Select
I/O, -1/0 4 : Data Input/Output
Vcc: +5V Supply
Vss : Ground

90

CS

WE

H

X

Hi-Z

Not Selected

L

L

H

Write 1

L

L

L

Write 0

L

H

D-out

Read

I/O

Mode

--

Vss

- - - - - - - - - - - - - - - - - - . S T A T I C RAM· MSM2114LRS.
ABSOLUTE MAXIMUM RATINGS
Rating

Value

Symbol

Conditions

Unit

o to +70

°c

Temperature Under Bias

Topr

Storage Temperature

T stg

-55 to +150

Supply Voltage

Vee

-0.5 to +7

Input Voltage

VIN

-0.5 to +7

V

Output Voltage

VOUT

-0.5 to +7

V

Power Dissipation

Po

°c
V
Respect to VSS

W

1.0

Note: Stresses above those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or at any other condition
above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

OPERATING CONDITIONS
Parameter
Supply Voltage
Input Signal Level
Operating T emperatu re

Min.

Typ.

Vee

4.5

5

5.5

V

VIH

2.0

5

5.5

V

VIL

-0.5

0

0.8

V

Topr

0

Symbol

Max.

Unit

Conditions
5V ±10%
Respect to VSS

+70

°c

DC CHARACTERISTICS
(Vee = 5V ±10, Ta = O°C to +70°C, unless otherwise noted)
Parameter
I nput Load Current

Symbol

Min.

III

Typ.

Max.

Unit

Conditions

10

J.LA

VIN = 0 to +5.5V

I/O Leakage Current

ILOL

-10

J.LA

CS = 2.4V
VI/O = O.4V

I/O Leakage Current

ILOH

10

J.LA

CS = 2.4V
VI/a = 5.5V

Output High Voltage

VOH

Vee

V

IOH =-0.2mA

Output Low Voltage

VOL

0.4

V

IOL = 2.0mA

Power Supply Current

lee

70

mA

Vee = 5.25V
I/O = OmA
TA = O°C

Power Supply Current

lee

72

mA

Vee 5.5V
I/O = OmA
T A = O°C

2.4

91

_STATIC RAM .

MSM2114LRS._~---------------

AC CHARACTERISTICS
READ CYCLE
(Vec = 5V ±10%, Ta = O°C to +70° C)
2114L-2
Parameter

Symbol

Read Cycle Time

tRC

Min.

2114L

2114L-3

Max.

Min.

Min.

Max.

300

200

Max.

Unit
ns

450

Access Time

tAC

200

300

450

ns

Chip Selection to Output
Valid

tco

70

100

120

ns

Chip Selection to Output
Active

tcx

Output 3-state from
Deselection

tOTO

Output Hold from
Address Change

tOHA

20

20

ns

20

60

80

10

100
10

10

ns
ns

tRC

\If

"

j~

J\
tAC

,

'(

11

\

!4-- t OTO---+

tco
.-..tcx---+
INPUT/OUTPUT

1/ 1
1\

Notes:

1.
2.
3.
4.
5.
6.

,

,

tOHA-t--

)

J'"
'"

A Read occurs during the overlap of a low CS and a high WE.
tOHA and tOTO are specified by the time when DATA OUT is floating.
Input Pulse Levels: 0.8V to +2.0V
Input Rise and Fall Time: 10ns
Timing Measurement Reference Levels: 1.5V
Output Load: 1 TTL Gate and CL = 50pF

WRITE CYCLE
(Vcc

= 5V ±10%, T a

= o°c to 70°C)

2114L-2
Parameter

92

Symbol

Min.

Max.

2114L-3
Min.

Max.

2114L
Min.

Max.

Unit

Write Cycle Time

twc

200

300

450

ns

Write Time

tw

120

150

200

ns

Write Release Time

tWR

20

30

50

ns

Address Setup Time

tAS

0

0

0

ns

Data Setup Time

tos

120

150

200

ns

Data Hal d From
Write Time

tOH

0

0

0

ns

- - - - - - - - - - - - - - - - - - . S T A T I C RAM· MSM2114LRS.
WRITE CYCLE
twc

"

,~

),-

j~

'~
tWR----+-

tw

~tAS~!\

tos

~

J
~ .... tOH

,~

INPUT/OUTPUT

Notes:

)~

DATA IN STABLE

"

j\

1. A Write occurs during the overlap of a low CS and a low WE.
2. Input Pulse Levels: 0.8V to +2.0V
3. Input Rise and Fall Time: 10ns
4. Timing Measurement Reference Levels: 1.5V
5. tw: Overlap time of a low CS and low WE
6. tAS is specified from CS or WE, whichever occurs last.
7. tWR, tos and tOH are specified from CS or WE, whichever occurs first.
8. tOTW is specified by the time when DATA OUT is floating, not defined by output level.
9. When I/O pins are Data output mode, don't force inverse signal to those pins.

CAPACITANCE
ITa

= 25°C, f = 1MHz)
Parameter

Symbol

Min.

Typ.

Max.

Unit

I nput/Output Capacitance

CI/O

6

8

pF

Input Capacitance

C'N

4

6

pF

Note: This parameter is periodically sampled and not 100% tested.

93

OK.I

semiconductor

MSM2128-1AS
16,384-BIT (2048

x 8) STATIC RAM

GENERAL DESCRIPTION
The Oki MSM2128-1 is a 16384-bit static Random Access Memory organized as 2048 words by 8 bits using Oki's
Advanced N-channel Silicon Gate MOS technology. It uses fully static circuitry and therefore requires no clocks or
refreshing to operate. Directly TTL compatible inputs, outputs and operation from a single +5V supply simplify
system designs. Common data input/output pins using three-state outputs are provided.
The MSM2128-1 series is offered in an 24-pin dual-in-line ceramic (AS suffix) package. Operation is guaranteed
from 0° C to 70° C.

FEATURES
• Low Power Dissipation
.Single +5V Supply (±10% Tolerance)
.2048-word x 8-bit Organ ization
• Fully Static Operation

• Common I/O Capability using ThreeState Outputs
• Directly TTL Compatible
• Advanced N-channel Silicon Gate
2128-1
200
800

Max. Access Time (NS)
Max. Power Dissipation (MW)

MOS Technology
• Pin compatible with MSM2716,
16,384 Bit UV Erasable PROM

2128-13
300
800

FUNCTIONAL BLOCK DIAGRAM

__r------,
-----t::...------,

A3-------t~

A4

As-----t...;;;t'

A6 - - - - t

PIN
CONFIGURATION

A?

----t-::~__,

As

----.r::::::p-----,

A9

----C:;o----.

ROW
SELECT

VCC
As
INPUT
DATA
CONTROL

A9

WE
DE
AIO

csI/O s
I/O?
1/0 6
1/0 5

1/04

Ao""A 10 : Address Inputs
1/0 1",,1/0 8 : Data Input!
Output
Vee: +5V Supply
VSS: Ground
WE: Write Enable
es: Chip Select
OE: Output Enable

94

-cs

MEMORY ARRAY
128 ROWS
16 COLUMNS
x 8 8LOCK

Vee

-

Vss

- - - - - - - - - - - - - - - - - - S T A T I C RAM· MSM2128-1AS_
ABSOLUTE MAXIMUM RATINGS
Rating

Symbol

Value

Unit

o to + 70

°c

Temperature Under Bias

Top

Storage Temperature

T stg

-55 to + 150

Supply Voltage

VCC

-0.5 to + 7

V

Input Voltage

V,N

-0.5 to + 7

V

Output Voltage

VOUT

-0.5 to + 7

Power Dissipation

PD

Conditions

°c

Respect to VSS

V

W

1.0

Note: Stresses above those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or at any other condition
above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

OPERATING CONDITIONS
Symbol

Parameter
Supply Voltage
Input Signal Level
Operating Temperature

Min.

Typ.

Max.

Unit

VCC

4.5

5

5.5

V

V,H

2.0

5

6.0

V

V,L

-0.5

5

O.S

V

Topr

0

+70

Conditions
5V ± 10%
Respect to VSS

°c

DC CHARACTERISTICS
(Vce = 5V ± 10%; Ta = O°C to

+ 70°C

Parameter

unless otherwise noted)
Symbol

Min.

Typ.

Max.

Unit

Conditions

Input Load Current

III

-10

10

p.A

VCC= +5.5
V,N = Oto VCC

1/0 Leakage Current

ILO

-10

10

p.A

CS = OE = 2.4V
Vec = +5.5V
VOUT = 0 to VCC

Output High Voltage

VOH

Output Low Voltage

VOL

Power Supply Current

2.4

V
0.4
145

ICC

10H = -1.0 mA

V

10L = 2.1 mA

mA

Vec = +5.5V
'110 = 0 mA

AC CHARACTERISTICS
READ CYCLE
(VCC = 5V ±10%, Ta = o°c to +70° C)
Parameter

Symbol

MSM212S-1

Read Cycle Time

tRC

Access Time

tA

Chip Selection to Output Valid

tco

Chip Selection to Output Active

tcx

Output 3-State from Deselection

tOTD

Output Hold from Address Change

tOHA

MSM212S-13
Unit

MIN

MAX

200

MIN

ns

300
200

300

ns

70

100

ns

SO

ns

10

ns

10
60

20

MAX

20

ns

95

.STATIC RAM· M S M 2 1 2 8 - 1 A S . - - - - - - - - - - - - - - - -

READ CYCLE

~----------------tRC--------------~~

HIGH
IMPEDANCE

I/O

Notes:

1.
2.
3.
4.
5.
6.
7.
S.

DATA VALID

A Read occurs during the overlap of a low CS, a low OE and a high WE.
tco and tcx are specified from CS or CE, whichever occurs last.
tOTS is specified from CS or OE, whichever occurs first.
tOTO and tOHA are specified by the time when DATA OUT is floating.
Input Pulse Levels: O.SV to +2.0V
Input Rise and Fall Time: 10 ns
Timing Measurements Reference Level: 1.5V
Output Load: 1 TTL Gate and CL = 50 pF

WRITE CYCLE
(VCC

= 5V ±10%, Ta = O°C to +70° C)
MSM212S-1 AS
Parameter

Write Cycle Time
Write Time
Write Release Time
Output 3-State from Write
Data to Write Time Overlap
Data Hold from Write Time
Address to Write Setup Time

96

Symbol

Min.

Max.

MSM212S-13AS
Min.

Max.

Unit

twc

200

300

tw

120

150

ns

twR

20

30

ns

60

tOTW

ns

SO

ns

tow

120

150

ns

tDH

0

0

ns

tAW

0

0

ns

- - - - - - - - - - - - - - - - - _ S T A T I C RAM . MSM2128-1AS_
WRITE CYCLE

twc

\/
j\

\V
/r\.
---tWR--/

\

J

\.

-tAW-

tw

I

\

\.

I

I--tOTW-\

I/O

\

\

\

\

\

\

I I 1/1 / /

Notes:

1.
2.
3.
4.
5.

6.
7.
8.
9.
10.

f---tDW- -tDH-HIGH
IMPEDANCE

=/ DATA IN STABLE ~ ,x-v.
x'A \

A Write Cycle occurs during the overlap of a low CS and low WE.
OE may be both high and low in a Write Cycle.
tAW is specified from CS or WE, whichever occurs last.
tw isa overlap time of a low CS and low WE.
tWR, tow and tDH are specified from CS or WE, whichever occurs first.
tOTW is specified by the time when DATA OUT is floating, not defined by output level.
When I/O pins are Data output mode, don't force inverse signal to those pins.
Input Pulse Levels: 0.8V to + 2.0V
Input Rise and Fall Time: 10 ns
Timing Measurements Reference Level: 1.5V

n

CAPACITANCE
(Ta = 25°C, f = 1MHz)
Parameter
Input/Output Capacitance
Input Capacitance

Symbol

Typ.

Max.

CI/O

4

6

pF

CIN

4

6

pF

Min.

Unit

Note: This parameter is periodically sampled and not 100% tested.

97

OK.I

semiconductor

MSM2128-RS
2 KW x 8 BIT STATIC RAM

GENERAL DESCRIPTION
OKI MSM2128 is a 16384 bits static Random Access Memory organized as 2048 words by 8 bits using Advanced
N-channel Silicon Gate MOS technology. It uses fully static circuitry through out and no clocks or refresh required.
The reduced standby power dissipation is automatically performed by CS control. Single +5 V Power supply. All
inputs and outputs are directly TTL compatible. Common data I/O using three-state outputs. 24 pin package is pin
compatible with 16 K UV Erasable Programmable ROM.

FEATURES
MSM2128-12RS
660mW (max)
110mW (max)

• Single power supply
• External clock and refresh operation not required
• Access time
120ns (max)
MSM2128-12RS
150ns (max)
MSM2128-15RS
200ns (max)
MSM2128-20RS
• Low power dissipation
during operation
MSM2128-15RS/20RS
. . . 550 mW (max)

•
•
•
•
•

during standby
TTL compatible I/O
Tristate I/O
Common data I/O capability
Power down mode using chip select signal
Convertibility of pins used in 16KEPROM MSM2716

BLOCK DIAGRAM

--VCC

A4

~

A,

:::;r--

A,

:::r-

A,
As

D

~

A,o

-0--

liD,
liD,

::::c--

~
-V

98

16 COLUMNS
x 8 Block

I--

.

:::c~
~

~

-L-

I
IL

l

~I..........

--GND

MEMORY ARRAY
128ROWS

ROW
SELECT

~

liD,
liO,
liD,

liD,
liD,
liD,

Ao "vA1o: Address Inputs
1/0 1 'VI/Os: Data InputlOutput
Vee: Power (5V)
VSS: Ground
WE: Write Enable
es: Chip Select
OE: Output Enable

-0--

A.

PIN ARRANGEMENT

I--

~
INPUT
DATA
CONTROL

I

I

COLUMN 1/0 CIRCUITS
COLUMN SELECT

¥¥¥¥
Ao

A,

A,

A,

~

11~ ~~n

nln n~n ~~

- - - - - - - - - - - - - - - - - - . S T A T I C RAM· MSM2128-RS.
ABSOLUTE MAXIMUM RATINGS
Symbol

Value

Unit

Vee

-0.5 to 7

V

Input Voltage

VIN

-0.5 to 7

V

Operating Temperature

Item
Supply Voltage

Conditions
Respect to V ss

Topr'

Oto 70

°c

Storage Temperature

Tstg

-55 to 150

°c

Power Dissipation

Po

1.0

W

DC AND OPERATING CHARACTERISTICS
(Ta = o°c to

+

70°C, VCC = 5V ± 10% unless otherwise notes.)

2128-12
Item

2128-15/20

Symbol
Typ.

Min.

Max.

Min.

Typ.

Unit

Condition

Max.

Input Load
Current

III

-10

10

-10

10

IJA

Vee = Max.
VIN = GND to Vee

Output Leakage
Current

ILO

-10

10

-10

10

IJA

CS = OE = VIH,
Vee = Max.
V out = GND to Vee

Operating
Current

ICC

120

100

mA

Vee = Max. CS = V I L
I I/O = 0 mA teye = Min.

Standby
Current

ISS

20

20

mA

Vee = Min. to Max.
CS = VIH

Peak Power-on
Current

ISSp

20

20

mA

Vee = GND to Vee = Min.
CS = Lower of Vee
or VIH

5

6

V

0

0.8

V

Vee

V

0.4

V

2

VIH

Input Voltage

Output Voltage

VIL

-0.5

VOH

2.4

5

6

0

0.8

-0.5

Vee

2.4

2

0.4

VOL
Notes 1. Typical limits are at Vee

Respect to V ss

= -1.0 mA
10L = 2.1 mA

10H

= 5V, Ta = 25°C, and specified loading.

AC CHARACTERISTICS
(Ta = o°c to

+ 70°C,

VCC

=

5V ± 10%, unless otherwise noted.)

AC TEST CONDITIONS
ITEM

CONDITIONS

Input High Level

2.0V

I nput Low Level

0.8V

Input Rise and Fall Times

10 ns

Input and Output Timing Levels

1.5V

Output Load

CL

= 100 pF, lTTL Gate
99

·STATIC RAM· M S M 2 1 2 8 - R S - . - - - - - - - - - - - - - - - READ CYCLE

(1)

Item

Symbol

2128-12
Max.

Min.
Read Cycle Time

tRC

2128-15
Min.

Max.

. Unit

Max.

tAC

120

150

200

ns

tOE

50

60

70

ns

Chip Select Access Time

tco

120

150

200

ns

Chip Selection to
Output in Low Z

tCX(2)

Chip Selection to
Output in High Z

tOTD(3)

Output Hold from
Address Time

tOHA

Chip Select to
Power Up Time

tpu

Chip Select to
Power Down Time

tPD

Address Access Time
Output Enable to
Output Delay

10

10
40

0

0

ns

10
50

0

60

ns

10

10

10

ns

0

0

0

ns

50

60

Condition

ns

200

150

120

2128-20
Min.

80

ns

READ CYCLE NO.1 (8) (9)
tRC
Ao'VAlo
tAC
tOE

OE

I/O(out)

DATA VALID

READ CYCLE NO.

D

2(8)(10)

tRC
CS
tco
OE

I/O(out)

Vcc

ICC

~.~~~~--~t-Pu--------------------tP-D~

____

Supply
Current
Notes:

100

8. ~ is high for Read Cycle.
9. Device is continuously selected. CS = VI L.
10. Address valid prior to or coincident with "CS" transition low.

-----------~-----.STATIC

WRITE CYCLE

RAM· MSM2128-RS.

(4)(5)
2128-12

Item

2128-15

2128-20

Symbol
Min.

Max.

Min.

Max.

Unit
Min.

Write Cycle Time

twc

120

150

200

ns

Chip Selection to End
of Write

tcw

100

120

150

ns

Address Setup Time

tAS

20

20

20

ns

Write Pulse Width

twp

60

80

100

ns

Write Recovery Time

tWR(6)

10

10

10

ns

Data Valid to End of Write

tDS(6)

50

70

90

ns

Data Hold Time

tDH(6)

10

15

15

ns

Write Enabled to Output
in High Z

tOTW(7)

0

Output Active from
End of White

twx

5

Notes

40

0
5

50

0
5

Condition

Max.

60

ns
ns

1. A read occurs during the overlap of a low CS, a low OE and a high WE.
2. tcx is specified from CS or OE, whichever occurs last.

3. tOTD is specified from CS or OE, whichever occurs first.
4.
5.
6.
7.

A write occurs during the overlap of a low CS and a low WE.
OE may be allowed in a Write Cycle both high and low.
tWR, tDS, and tDH are specified from CS or WE, whichever occurs first.
tOTW is specified by the time vyhen DATA OUT is floating, not defined by output level.

WRITE CYCLE NO.

1(11)(13)

twc
Ao"vAIO

tcw

HI

CS

twp
WE

twx

tOTW
I/O
(DOUT)
tDS

tDH

I/O
(DIN)

101

_STATIC RAM· M S M 2 1 2 8 - R S . - - - - - - - - - - - - - - - - - WR ITE CYCLE NO. 2(12) (13)

...

twc
Ao'VAIO
tAS
tcw
CS

I ..

twp

WE

tOTW
I/O
(DOUT)
tDS
I/O
(DIN)

Notes 11. WE control mode
12. CS control mode
13. When I/O pins are Data output mode, don't force inverse signal to these pins.

FUNCTION TRUTH TABLE
CS

WE

OE

Mode

Output

Power

H

X

X

Not Selected

High Z

Standby

L

L

X

Write

High Z

Active

L

H

L

Read

DOUT

Active

L

H

H

Not Selected

High Z

Active

CAPACITANCE
Item
Input Capacitance
I nput/Output Capacitance

102

Symbol

Min.

Max.

Unit

CIN

6

pF

CliO

8

pF

Condition

= OV
VI/O = OV
VIN

OK.I

semiconductor

MSM5104,RS
4096-BIT (4096 x 1) CMOS STATIC RAM

GENERAL DESCRIPTION
The Oki MSM5104 is a 4096-bit static Random Access Memory organized as 4096 words by 1 bit using Oki's reliable
Silicon Gate CMOS technology. Microwatt power dissipation typical of all CMOS is exhibited in all static state.
Directly TTL compatible inputs, output, operation from a single +5 V supply and on-chip address-data registers
simplify system designs.
The MSM5104 series is offered in an 18-pin plastic (RS suffix) package. The series is guaranteed for operation from
O°C to 70°C and over a 4 V to 6 V power supply range.

FEATURES
• Low Power Dissipation
40J.LW Max. Standby Power
33mW/MHz Max. Operating Power
• Data Retention to VCC=2V
• Single 4"" 6V Power Supply

• High Density 300-mil 18-Pin
Package
• On-Chip Address and Data
Registers
• Separate Data I nput and Output

5104-2
200
33
40

Max. Access Time (NS)
Max. Operating Power (MW/MHz)
Max. Standby Power {J-L)

•
•
•
•

Three-State Ouput
Directly TTL/CMOS Compatible
Silicon Gate CMOS Technology
Pin-compatible with Mostek 4104,
I nterchangeable with Harris 6504

5104-3
300
33
40

FUNCTIONAL BLOCK DIAGRAM

64x 64
64

MATRIX

PIN CONFIGURATION
Ao

Vee

Al

All

A4

A lo

As

A9

A2

As

A3

A,

DOUT

A6

WE

DIN

Vss

"Ct:

DIN

A

A

~

To All: Address Inputs
WE: Write Enable
CE: Chip Enable
DIN: Data Input
DOUT: Data Output
VCc: +5V Supply
VSS: Ground

103

.STATIC RAM· M S M 5 1 0 4 R S . - - - - - - - - - - - - - - - ABSOLUTE MAXIMUM RATINGS
Rating

Symbol

Value

Unit

Supply Voltage

VCC

-0.3 to 7.0

Input Voltage

VIN

-0.3 to VCC

Output Voltage

VOUT

Storage Temperature

T stg

V

+ 0.3

V
V

o to VCC

°c

-55 to 150

Note: Stresses above those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or at any other condition
above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

OPERATING CONDITIONS
Parameter
Supply Voltage
I nput Signal Level
Operating Temperature

Symbol

Typ.

Min.

Max.

VCC

4

5

6

VIH

2.4

5

VCC

V

0.8

V

VIL

-0.3

Topr

0

0

70

Conditions

Unit

5V ± 20%

V

Respect to Vss

°c

DC CHARACTERISTICS
(VCC = 5V ± 10%; Ta = O°C to +70°C, unless otherwise noted)
Parameter

Symbol

Min.

Typ.

Max.

Unit

Conditions

Input Load Current

III

-1

1

IJA

VIN = Oto VCC

Output Leakage Current

ILO

-1

1

IJA

VI/O = 0 to VCC

Output High Voltage

VOH

Output Low Voltage

VOL

Output High Current

IOH

Standby Supply Current

ICCS

Operating Supply Current

ICC

4.2

V
0.4

-1.0
0.2

lOUT = -401JA

V

IOUT= 1.6mA

mA

VOUT= 2.4V

50

IJA

VIN = 0 or VCC

6

mA

VIN = 0 or VCC,
tRC = 1IJs

AC CHARACTERISTICS
(VCC=5V±10%, Ta

= o°c to +70°)
5104-2

Parameter
Read/Write Cycle Time

Symbol
tRC, twc

Min.

5104-3
Max.

Min.

Max.

420

300

Unit
ns

Chip Enable Access Time

tAC

Chip Enable Pulse Width

tCE

200

300

ns

Chip Enable Off Time

tcc

100

120

ns

Address Hold Time

tAH

40

50

ns

Address Setup Time

tAS

0

Output Disable Time

tOFF

0

Write Enable Pulse Width

twp

Write Enable Setup Time

tws

104

300

200

0
70

0

ns

ns
100

ns

100

130

ns

0

0

ns

- - - - - - - - - - - - - - - - . S T A T I C RAM· MSM5104RS.
5104-2
Parameter

Symbol

Write Enable Hold Time

Min.

5104-3
Max.

120

twH

Min.

Max.

Unit

150

ns

Data Setup Time

tDS

0

0

ns

Data Hold Time

tDH

60

SO

ns

Data Valid Time to Write Pulse

tDV

0

0

ns

150

200

ns

Write Enable Read Time

twCL

AC TEST CONDITIONS
Input Pulse Levels: O.SV to 2.4V
Timing Measurement Reference Levels: 1.5V
Input Rise and Fall Time: 10 ns

Vee

Dout

o-----~~----~

50 pF (Including Scope and Jig)

READ CYCLE

~~~----------------teE------------------~

tOFF
HIGH

DOUT -11ji;Mii5pii:E:r:;D~A~N~C:j;:E--"%OOOO~
WE ___

~H~IG~H~

VALID DATA OUTPUT

~ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- J

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ___

105

• STATIC RAM· M S M 5 1 0 4 R S - . - - - - - - - - - - - - - - - EARLY WRITE CYCLE

HIGH

HIGH

DOUT~I~M~P~E~DA~NC~E~----------------------------------------~I~M~P~E~DA~N~C~E~

READ MODIFY WRITE CYCLE

HIGH

DOUT --:-:IM~P=-=E~D~A~N7:C:-::E:------;<..;>Q(~

106

VALID DATA OUTPUT

---------------~I.STATIC

RAM· MSM5104RS.

LOW VCC DATA RETENTION CHARACTERISTICS
(Ta = o°c to +70°C, unless otherwise noted.)
Parameter
V CC for Data Retention

Symbol

Min.

VCCH

2

Typ.

Max.

Unit
V

0.1

,.,.A

Data Retention Current

ICCH

20

CE to Data Retention Time

tsu

0

ns

Operation Recovery Time

tR

tRC

ns

Conditions
VIN = OVor VCC
VCC = 2V VCE = VCC
VIN = OV or VCC

LOW VCC DATA RETENTION WAVEFORM

STANDBY MODE

VCC
5V ----=--=----+------..

4.5V- -

--

VIH - - - VCCH

GND -

-- - ---------- --- -- -

---- --- -- - - --

CAPACITANCE
(Ta = 25°C, f = 1 MHz)
Parameter
Input/Output Capacitance
Input Capacitance

Symbol

Min.

Typ.

Max.

Unit

CI/O

10

pF

CIN

8

pF

Note: This parameter is periodically sampled and not 100% tested.

107

OK.I

semiconductor

MSM5114·RS
4096-BIT (1024 x 4) CMOS STATIC RAM

GENERAL DESCRIPTION
The Oki MSM5114 is a 4096-bit static Random Access Memory organized as 1024 words by 4 bits using Oki's
reliable Silicon Gate CMOS technology. It uses fully static circuitry and therefore requires no clocks or refreshing
to operate. Microwatt power dissipation typical of all CMOS is exhibited in all static states. Directly TTL compatible inputs, outputs and operation from a single +5V supply simplify system designs. Common data input/output
pins using three-state outputs are provided.
The MSM5114 series is offered in an 18-pin plastic (RS suffix) package. The series is guaranteed for operation from
0° C to 70° C and over a 4V to 6V power supply range.

FEATURES
• Fully Static Operation
• Low Power Dissipation
40,.,.W Max. Standby Power
165mW/MHz Max. Operating
Power

•
•
•
•

Max. Access Time (NS)
Max. Operating Power (MW/MHz)
Max. Standby Power (,.,.W)

Data Retention to VCC=2V
Single 4 ""' 6V Power Supply
High Density 300-mil 18-Pin Package
Common I/O Capability using ThreeState Outputs
5114-2
200
165
40

• Directly TTL/CMOS Compatible
• Silicon Gate CMOS Technology
• Interchangeable with Intel 2114L
Devices

5114-3
300
165
40

5114
450
165
40

FUNCTIONAL BLOCK DIAGRAM
A.---[>--I
As---I~>---1

A,---[>--I
MEMORY ARRAY
64 x 64

A,---L>--I
A8----""""-----'

A.---I~>---1

I/O,----r------,.~--,

PIN CONFIGURATION

~

To A9: Address Inputs
WE: Write Enable
CS: Chip Select
I/O 1",,1/0 4 : Data Input/Output
Vec: +6V Supply
VSS : Ground

108

1/0, --'+-1---1">--1

CS

WE

I/O

Mode

H

X

Hi-Z

Not Selected

L

L

H

Write 1

L

L

L

Write 0

L

H

D-out

Read

- - - - - - - - - - - - - - - - I . S T A T I C RAM· MSM5114RS.
ABSOLUTE MAXIMUM RATINGS
Rating

Symbol

Supply Voltage
Input Voltage

Value

Conditions

Unit

VCC

-0.3 to 7.0

V

VIN

-0.3 to V CC + 0.3

V

Respect to VSS

Data I/O Voltage

VD

-0.3 to V CC + 0.3

V

Storage Temperature

T stg

-55 to 150

°c

Note: Stresses above those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the
device. This is a stress rating only and functional operations of the device at these or at any other condition
above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

OPERATING CONDITIONS
Parameter
Supply Voltage
I nput Signal Level
Operating Temperature

Symbol

Min.

Typ.

Max.

Unit

VCC

4

5

6

V

VIH

2.4

5

VCC

V

VIL

-0.3

0

0.8

V

Topr

0

70

Conditions
5V ± 20%
Respect to V SS

°c

DC CHARACTERISTICS
(VCC = 5V ± 10%; Ta

= O°C to +70°C, unless otherwise noted.)

Parameter

Symbol

Min.

Typ.

Max.

Unit

Conditions

Input Load Current

III

-1

1

J.LA

VIN = 0 to VCC

Data 1/0 Leakage Current

ILO

-1

1

J.LA

VI/O = 0 to VCC

Output High Voltage

VOH

Output Low Voltage

VOL

Output High Current

10H

Standby Supply Current

ICCS

Operating Supply Current

ICC

4.2
0.4
-1.0
0.2
30

50

V

IOUT= -40J.LA

V

10UT= 1.6 mA

mA

VOUT= 2.4V

J.L.A

VIN= OorVcc

mA

VIN = 0 or VCC,
tRC = 1 J.LS

109

.STATIC RAM· M S M 5 1 1 4 R S - . - - - - - - - - - - - - - - - AC CHARACTERISTICS

READ CYCLE
(Vcc = 5V ±10%, Ta

= o°c to +70°C)
5114-2

Parameter

Min.
Read Cycle Time

tRC

5114

5114-3

Symbol
Max.

200

Min.

Unit

Max.

Min.

Max.

450

300

ns

Access Time

tAC

200

300

450

ns

Chip Selection to Output
Valid

tco

200

300

450

ns

Chip Selection to Output
Active

tcx

Output 3-state from
Oeselection

tOTO

Output Hold from Address
Change

tOHA

20

20

20

SO

60

10

ns

100

ns

10

10

ns

READ CYCLE
tRC

\V

\V

Ji\

II\.
tAC

\

I

I\.

I
---tOTO-tco

I---tcx--INPUT/OUTPUT

'OHAt---

V

"-

Notes:

1.
2.
3.
4.
5.

/
\

I
\

\/\

IV

A Read occurs during the overlap of a low CS and high WE.
Input Pulse levels: O.SV to +2.4V
Input Rise and Fail Time: 10 ns
Timing Measurement Reference Levels: 1.5V
Output Load: 1 TTL Gate and CL = 50 pF

WRITE CYCLE
(Vcc

=

5V ±10%, Ta

= o°c to +70°C)
5114-2

Parameter
Write Cycle Time

Symbol
twc

Write Time

tw

Write Release Time

tWR

Min.
200

Max.

5114

5114-3
Min.
300

Max.

Min.

Unit
Max.

450

ns

150

190

250

ns

20

30

50

ns
ns

Address Setup Time

tAS

20

20

20

Data Setup Time

tos

120

150

200

ns

0

0

0

ns

Data Hold From Write Time

110

tOH

· - - - - - - - - - - - - - - - - - - S T A T I C RAM· MSM5114RS_
WRITE CYCLE
twc

\/
/\

\V

Jr\
\
1\
tw

f---tAS~\

twR-

tDS

7

V

r---\V
J~

INPUT /OUTPUT

Notes:

1.
2.
3.
4.
5.
6.
7.

tDH

\1
/\

DATA IN STABLE

A Write occurs during the overlap of a low CS and low WE.
Input Pulse Levels: 0.8V to +2.4V
Input Rise and Fall Time: 10 ns
Timing Measurement Reference Levels: 1.5V
tW: Overlap time of a low CS and low WE.
tAS: Low WE from address or low CS from address
tWR, tDS and tDH are defined from High CS or High WE, whichever occurs first.

LOW VCC DATA RETENTION CHARACTERISTICS
(Ta = 0° C to +70° C, unless otherwise noted.!
Parameter
VCC for Data Retention

Symbol

Min.

VCCH

2

Typ.

Max.

Unit
V

20

Data Retention Current

ICCH

CE to Data Retention Time

tsu

0

ns

Operati on Recovery Ti me

tR

tRC

ns

0.1

IJA

Conditions
VIN

=

OT or VCC

VCC = 2V VCS = VCC
VIN = OV or VCC

LOW VCC DATA RETENTION WAVEFORM
---0+----- ST AN DBY MODE

----+-00>---

5V _ _
V.=C.=C_-+-_ _---..
4.5V - - - - -

VCCH---CS
VIL------J
GND--- - - - - - - - - - - - - - - -

-

-

-

- - - -- - -- -

- ---

111

• STATIC RAM· MSM5114RS ••- - - - - - - - - - - - - - - - CAPACITANCE
(Ta

= 2SoC, f = 1 MHz)
Parameter
Input/Output Capacitance
Input Capacitance

Symbol

Min.

Max.

Unit

CliO

10

pF

CIN

8

pF

Note: This parameter is periodically sampled and not 100% tested.

112

Typ.

OK.I

semiconductor

MSM5115RS
4096-BIT (1024 x 4) CMOS STATIC RAM

GENERAL DESCRIPTION
The Oki MSM5115 is a 4096-bit static Random Access Memory organized as 1024 words by 4 bits using Oki's reliable
Silicon Gate CMOS technology. Microwatt power dissipation typical of all CMOS is exhibited in all static states.
Directly TTL compatible inputs, outputs, operation from a single +5 V supply and on-chip address registers simplify
system designs. Common data input/output pins using three-state outputs are provided.
The MSM5115 series is offered in an 18-pin plastic (RS suffix) package. The series is guaranteed for operation from
O°C to 70°C and over a 4 V to 6 V power supply range.

FEATURES
• Low Power Dissipation
40/-f.W Max. Standby Power
33mW/MHz Max. Operating Power
• Data Retention to V CC = 22V
• Single 4,." 6V Power Supply

Max. Access Time (NS)
Max. Operating Power (MW/MHz)
Max. Standby Power (/-f.W)

• High Density 300-mil 18-Pin
Package
• On-Chip Address Register
• Common I/O Capability using
Three- State Outputs
5114-2
200
33
40

• Directly TTL/CMOS Compatible
• Silicon Gate CMOS Technology
• Pin-compatible with Intel 2114,
Interchangeable with Harris 6514

5115-3
300
33
40

FUNCTIONAL BLOCK DIAGRAM

GATED
ROW
DECODER

64

PIN CONFIGURATION
I/O,n---+---+---=< t - - - - - t - - - " - - - t - 1

I/O, n---.+---+---=< t - - - - - t - - - 4 - - - t - 1

64 x 64
MATRIX

GATED COLUMN
DECODER
AND
DATA
INPUT/OUTPUT

liD. (}---.+---+--=< t - - - - - t - - - 4 - - - t - 1

Ao To A9: Address Inputs
Write Enable
CE: Chip Enable
1/° 1 ,.,,1/° 4 : Data Input/Output
Vce: +5V Supply
VSS: Ground

W1::

113

.STATIC RAM· M S M 5 1 1 5 R S . - - - - - - - - - - - - - - - - - ABSOLUTE MAXIMUM RATINGS
Rating

Symbol

Value

Unit

Supply Voltage

VCC

-0.3 to 7.0

V

Input Voltage

VIN

-0.3 to V CC + 0.3

V

Data I/O Voltage

VD

-0.3 to VCC + 0.3

V

Storage Temperature

T stg

-55 to 150

°c

Note: Stresses above those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or at any other condition
above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

OPERATING CONDITIONS
Parameter

Symbol

Supply Voltage

VCC

Input Signal Level
Operating Temperature

Typ.

Min.
4

Max.
6

5

Unit

VIH

2.4

5

VCC

V

VIL

-0.3

0

0.8

V

Topr

0

Conditions
5V ± 20%

V

Respect to VSS

°c

70

DC CHARACTERISTICS
(VCC = 5V ± 10%; Ta = O°C to +70°C, unless otherwise noted)
Typ.

Conditions

Min.

III

-1

1

JJ.A

VIN = Oto VCC

Data I/O Leakage Current

ILO

-1

1

JJ.A

VI/O = 0 to VCC

Parameter

Output High Voltage

VOH

Output Low Voltage

VOL

Output High Current

10H

Standby Supply Current

ICCS

Operating Supply Current

ICC

Max.

Unit

Symbol

Input Load Current

V

4.2
0.4

V

10UT= 1.6mA

mA

VOUT= 2.4V

50

JJ.A

VIN = 0 or VCC

6

mA

VIN = 0 or VCC,
tRC = 1 JJ.s

-1.0
0.2

10UT= -40JJ.A

AC CHARACTERISTICS
(Vcc = 5V ±10%, Ta

= o°c to +70°C)

Parameter

5115-2

Symbol
Min.

Read/Write Cycle Time

tRC, twc

5115-3
Max.

Min.

Max.

420

300

Unit
ns

Chip Enable Access Time

tAC

Chip Enable Pulse Width

tCE

200

300

ns

Chip Enable Off Time

tcc

100

120

ns

Address Hold Time

tAH

40

50

ns

Address Setup Time

200

300

tAS

0

Output Disable Time

tOFF

0

Write Enable Pulse Width

twp

100

130

ns

tws

0

0

ns

Write Enable Setup Time

114

0

ns

70

0

ns
100

ns

- - - - - - - - - - - - - - - - - - . S T A T I C RAM· MSM5115RS.

Parameter

5115·3

5115·2

Symbol

Min.

Max.

Min.

Unit

Max.

Write Enable Hold

tWH

170

250

ns

Data Setup Time

tDS

100

130

ns

Data Hold Time

tDH

0

0

ns

Data Valid Time to Write
Pulse

tDV

0

0

ns

Write Enable Read Time

tWCL

150

200

ns

READ CYCLE

tCE

-tcc
I

{

\

---.I

tAC
I/O

HIGH

\

j

\

tOFFNYX~

VALID DATA OUT

\

--

~
HIGH

j
~\
IMPEDANCE
IMPEDANCE
WE _____
H_IG_H
__________________________________________________________

WRITE CYCLE

~I

~tAH:j.1

A.-A.~VALIDAD~--N-E-X-T-A-D-D
~--------------------twc----------------------~
--~~----------------tCE--------------~~

~------------tWCL----------~

-r-r~~~,...-;-~~~~~ ~---------twP ------------I r7I'"7I'f'7"I7"7'""1':'""",("",,\"'I"""">,,,,""~~

I/O

HIGH
IMPEDANCE

-----.;..~~--+----------rVALI

0 DATA

HIGH
IMPEDANCE

INPUT>--------.:...;..;:;.~----

~----tDS-----4~-tDH

1------------- twH --------------1

115

• STATIC RAM· MSM5115RS ••- - - - - - - - - - - - - - - READ MODIFY WRITE CYCLE

tCE

I/O _ _...;H...;.;I;..;;G;.;.,H~_ _+__---I~"'Y\t."I
IMPEDANCE

Notes:

1. Input Rise and Fall Time: 10 ns
2. Timing Measurement Reference Levels: 1.SV
3. Output Load: CL = SO pF
4. Input Pulse Levels: 0.8V to 2.4V

LOW VCC DATA RETENTION CHARACTERISTICS
(T a

= 0° C to + 70° C, unless otherwise noted)
Symbol

Min.

VCC for Data Retention

VCCH

2

Data Retention Current

ICCH

CE to Data Retention Time

tsu

0

ns

Operation Recovery Time

tR

tRC

ns

Parameter

Typ.

Max.

Unit
V

0.1

20

IJ.A

Conditions
VIN = OV or VCC
VCC = 2V.jCE = VCC
VIN = OVor VCC

LOW VCC DATA RETENTION WAVEFORM

~----STANDBY MODE---~­

SV _ _v_c:::::.;c:::..--+-_ _----.
4.SV - - - - -

VCCH---CS
VIL----'
GND--- - -

116

-- --- ----- - - -

-- -

-

- - --- -- -

- ---

- - - - - - - - - - - - - - - - - - _ S T A T I C RAM· MSM5115RS.
CAPACITANCE
(T a =2SoC,f= 1 MHz)

Parameter
Input/Output Capacitance
Input Capacitance

Symbol

Min.

Typ.

Max.

Unit

CliO

10

pF

CIN

8

pF

Note: This parameter is periodically sampled and not 100% tested.

117

OK.I

semiconductor

MSM5128RS
2048-WORD x 8-BIT C-MOS STATIC RAM

GENERAL DESCRIPTION
MSM5128RS is a 2048-word 8-bit CMOS static RAM featuring 5V power supply operation and direct TTL coupling
for inputs and outputs. And since the circuitry is completely static, external clock and refreshing operations are
unnecessary, making this device very easy to employ. MSM5128RS is also a CMOS silicon gate device which requires
very little power during standby (maximum standby current of 501JA) when there is no chip selection. Stored data is
retained if the power voltage drops to 2V, thereby enabl ing battery back-up.
A byte system is adopted, and since there is pin compatibility with ultra-violet erasable type programmable ROMs,
this device is ideal for use as a peripheral memory for microcomputers and data terminal units etc. In addition, CS
and OE signals enable OR ties with the output terminals of other chips, thereby facilitating simple memory expansion
and bus line control etc.

FEATURES
• Direct TTL Compatible. (Input and Output)
• 3-State Output
• Pin Compatible with
16K EPROM
(MSM2716)
16K NMOS SRAM (MSM2128)

•
•
•
•

Single 5V Supply
Battery Back-up at 2V
Operating temperature range Ta = -30°C to +85°C
Low Power Dissipation
275IJ.W MAX
Standby;
Operation; 200 mW TYP
• High Speed (Equal Access and Cycle Time)
MSM5128-12/15/20; 120 ns/150 ns/200 ns MAX

FUNCTIONAL BLOCK DIAGRAM

Ao~----~-f---'

As 0 - - -

A6o---

PIN CONFIGURATION
24 VCC

13 1/0'

A,D------l::l<'
As o - - - - - - t : : r ,

A90------t::r'
AIO o-----~=t._-l

1/0 1
1/0 2
1/0 3
1/04
1/0 5
1/0 6
I/O,
I/Os

CS
WE

Ao "vAl0: Address
I/Ol"vI/08: Data Input/Output
CS: Chip Select
WE: Write Enable
OE: Output Enable
VCC, VSS: Supply Voltage

118

OE

Q---<~---l>----f

o--t.----t>--l-l
o--Iff---I>--H
o--~--I>--H

0--1+++_-1>-+-1
o--I+++ff--l>-+-l
r">-----l-W-J.++.---b---l-l
o->+++-~-c>--'H

MEMORY ARRAY
128 ROWS
16 COLUMNS
x8 BLOCK

--aVec
~Vss

.STATIC RAM· MSM5128RS ••- - - - - - - - - - - - - - - TRUTH TABLE
110 Operation

Mode

CS

WE

OE

Standby

H

X

X

L

H

H

High Z

L

H

L

DOUT

L

L

X

DIN

Read
Write

High Z

X: H or L

ABSOLUTE MAXIMUM RATINGS
Item
Supply Voltage
Input Voltage

Symbol

Rating

Unit

VCC

-0.3 to 7.0

V

VIN

-0.3 to VCC + 0.3

V

Conditions
Respect to GND

Operating Temperature

Topr

-30 to 85

Storage Temperature

T stg

-55 to 150

°c
°c

Power Dissipation

Po

1.0

W

RECOMMENDED OPERATING CONDITION
Item
Supply Voltage

Symbol

Min.

Typ.

Max.

VCC

4.5

5

5.5

Input Voltage

Output Load

VCCH

2

VIH

2.2

VIL

-0.3

CL
TTL

5

V

Conditions
5V ± 10%

V

0

VSS
Data Storage Supply Voltage

Unit

5.5

V

VCC + 0.3

V

0.8

V

100

pF

1

119

.STATIC RAM· M S M 5 1 2 8 R S . - - - - - - - - - - - - - - - - - DC CHARACTERISTICS

Item

MSM5128-12

Symbol

Min.

Typ.

MSM5128-15

Max.

Min.

Typ.

MSM5128-20

Max.

Min.

Typ.

Unit

Test Condition

Max.

Input
Leakage
Current

III

-1

1

-1

1

-1

1

IJA

VIN = 0 to VCC

Output
Leakage
Current

ILO

-1

1

-1

1

-1

1

IJA

CS + VIH or
OE = VIH
VI/O = 0 to VCC

VOH

2.4

Output
Voltage

Standby
Supply
Current

2.4

0.4

VOL

ICes

ICCS 1
Operating
Supply
Current

2.4

ICCA

0.4

V

IOH=-1mA

0.4

V

IOL =4mA
(5128/12)
IOL = 2.1 mA
(5128-15/20)

0.1

50

0.1

50

0.1

50

IJA

CS = V CC-0.2V
VIN ~ 0.2V or
VIN ~ VCC-0.2V

3

7

3

7

3

7

mA

CS = VIH
tcyc = Min. cycle

40

60

37

55

35

50

mA

40

67

37

62

35

57

mA

Min. Ta=0..... 85°C
cycle Ta=-30..... 85°C

AC CHARACTERISTICS
Test Condition
Item

Conditions

I nput Pulse Level
Input Rise and Fall Times

10 ns

I nput and Output
Timing Reference Level

1.5V

Output Load

CL=100 pF, 1 TTL Gate

READ CYCLE
(V cc

= 5V ± 10%, Ta = -30°

to +85° C)

Item

Symbol

MSM5128-12

MSM5128-15

MSM5128-20

Min.

Min.

Min.

Max.

Max.

150

120

Max.

200

Unit
ns

Read Cycle Time

tRC

Address Access Time

tAC

120

150

200

ns

Chip Select Access Time

tco

120

150

200

ns

Output Enable to Output Valid

tOE

Chip Selection to Output Active
Output Hold Time From
Address Change
Output 3-state from Oeselection

120

100

80

120

ns

tcx

10

15

20

ns

tOHA

10

15

20

ns

tOTO

0

50

0

50

0

60

ns

- - - - - - - - - - - - - - - - - - _ S T A T I C RAM· MSM5128RSREAD CYCLE

~---------------tRC----------------~

DATA OUT VALID

I/O

Notes:

1.
2.
3.
4.

A Read occurs during the overlap of a low CS, a low OE and a high WE.
tcx is specified from CS or OE, whichever occurs last.
tOTD is specified from CS or OE, whichever occurs first.
tOHA and tOTD are specified by the time when DATA OUT is floating.

WRITE CYCLE
(V cc

= 5V ± 10%, T a = -30

0

C to +S5° C)

Item

Symbol

MSM512S-12

MSM512S-15

Min.

Min.

Max.

Max.

MSM512S-20
Unit
Min.

Max.

twc

120

150

200

ns

Address to Write Setup Time

tAS

15

20

20

ns

Write Time

tw

70

90

120

ns

Write Recovery Time

tWR

15

20

20

ns
ns

Write Cycle Time

Data Setup Time

tDS

50

60

SO

Data Hold from Write Time

tDH

5

10

10

Output 3-5tate from Write
Notes:

1.
2.
3.
4.
5.
6.
7.

tOTW

50

50

ns
60

ns

A Write Cycle occurs during the overlap of a low CS and a low WE.
OE may be both high and low in a Write Cycle.
tAS is specified from CS or WE, whichever occurs last.
tw is an overlap time of a low CS and a low WE.
twR, tDS and tDH are specified from CS or WE, whichever occurs first.
tOTW is specified by the time when DATA OUT is floating, not defined by output level.
When I/O pins are Data output mode, don't force inverse signal to those pins.

121

_STATIC RAM· M S M 5 1 2 8 R S . - : - - - - - - - - - - - - - - - - - WRITE CYCLE

~-------------~C--------------~

"-) > - - - - - - -

I/O

/

LOW VCC DATA RETENTION CHARACTERISTICS
(T a = _300 C to +85 C. unless otherwise noted)
0

Symbol

Min.

V CC for Data Retention

Parameter

VCCH

2

Data Retention Current

ICCH

CE to Data Retention Time

tsu

Operation Recovery Time

tR

Typ.

Max.

V
0.05

Conditions

Unit

20

J.£A

0

ns

tRC

ns

VIN

= OV or VCC

VCC = 2V VCS = VCC
VIN = OV or VCC

- ; - - - - - ST ANDBY MODE ----~5V _ _
V-=C-=C_-+-_ _- ,
4.5V - - - - -

VCCH---CS
VIL----J
GND- - - - -

-- -- ------ -

- -

-- -

-

- - --- -- -

- ---

CAPACITANCE
(Ta = 25°C. f = 1 MHz)
Parameter

Symbol

I nput/Output Capacitance

CliO

8

pF

Input Capacitance

CIN

6

pF

Min.

Note: This parameter is periodically sampled and not 100% tested.

122

Typ.

Max.

Unit

OK.I

semiconductor

MSM5188RS/AS
8,192-WORD x 8-BIT C-MOS STATIC RAM

GENERAL DESCRIPTION
MSM5188 is a 8192 word 8-bit CMOS static RAM featuring 5V power supply operation and direct TTL coupling for
inputs and outputs. And since the circuitry is completely static, external clock and refreshing operations are
unnecessary, making this device very easy to employ. MSM5188 is also a CMOS silicon gate device which requires
very low power during standby (standby current of 2mA) when there is no chip selection.
A byte system is adopted, and since there is pin compatibility with ultra-violet erasable type programmable ROMs,
this device is ideal for use as a peripheral memory for microcomputers and data terminal units etc. In addition, CE,
CE and OE signals enable OR ties with the output terminals of other chips, thereby facilitating simple memory
expansion and bus line control etc.

FEATURES
• Direct TTL Compatible. (Input and Output)
• 3-State Output
• Pin Compatible with
64K EPROM
(MSM2764)
64K NMOS SRAM (MSM2188)
.28-pin DIP PKG

• Single 5V Supply
• O°C,.., 70°C
• Low Power Dissipation
Standby; 100",W TYP
10mW MAX
Operation; 100mW TYP 150mW MAX
• High Speed (Equal Access and Cycle Time)
100 - 120 ns MAX

PIN CONFIGURATION

FUNCTIONAL BLOCK DIAGRAM
A5O-----~~~---.

A6 o-------1IT":-t

A, o------{,.-..,
As O-----{:;lC:J

NC

A9 O-----j~::l
AlO cr------I~-,
Au

cr------I~--,

MEMORY ARRAY
256 ROWS
32 COLUMNS
x 8 BLOCK

----.0

Vee

~Vss

All o-------t~=L_ __.J

1/0 1 0-..------1>--1
1/0 2 cr-~----II>-H
1/0 3 D--t-H---t>-:lH
1/04 O-+t-i+-----1I>---,H
I/O s D-+H-+.----II>-H
1/06 o-+t-i~---il>---,H
Vss

1/0, D--t+t++t.-ti>---'H
II0 s cr-+H+t+.....-t>--t-l
I/O.

Ao - Al2
: Address
1/0 1 - 1/0 8 : Data Input/Output
CE, CE
WE
OE

: Chip Select
: Write Enable
i Output Enable

Vee, VSS : Supply Voltage

CE

a:
WE
CE ~===a~--------------------------------~

123

MOS
MASK
ROMS

OK.I

semiconductor

MSM2916RS
16,384-BITS STATIC 16 K MASK ROM

GENERAL DESCRIPTION
The MSM2916RS is a 16,384-bits static, N channel MOS Read only memory organized as 2,048 words by 8 bits.
The three-state outputs and TTL inputs/outputs level allow for direct interface with common system bus structures.
The MSM2916RS single +5 V power supply and 250 ns access time are both ideal for usage with high performance
m icrocompu ters.
The three chip selects CS 1 , CS z and CS 3 may be defined by customer and fixed during the masking process.
ROM DATA Accepting flow from customer.
Preparing next two in customer's side
1) Two master d~vices, programming finished 16K Ep·ROM.
2)
Chip select CS 1 , CS z and CS 3 logic table.
After received customer's ROM DATA, print out ROM DATA in Hex CODE and copy finished 16K EP·ROM send to
customer.
Verified ROM DATA in customer's side, OKI send engineering samples mask programed customer's ROM DATA.

FEATURES
•
•
•
•
•
•

Organization .
Static Operation
Supply Voltage .
Access Time ..
Power Dissipation
Input Voltage . . .

2048W x 8 bit
No clocks required
5 V ±10%
250 ns Max.
550mW Max.
VIH = 2.0V Min.
VIL = 0.8 V Max.

• Output Voltage.
• Package . . . . .

VOH = 2.4 V Min.,
VOL = 0.45 V Max.
24 PIN DIP

FUNCTIONAL BLOCK DIAGRAM

Do D 1 - - - - - - - - __ D7

PIN CONFIGURATION

Vcco-Vsso--

A7

Vee

A6

As
A9

eS 2
es,
AIO

eS 3
D7
D6
D,

Ds
D.
D3

Note:

126

CS 1 ' CS 2 and CS 3 are programmable
CHIP SELECTS

- - - - - - - - - - - - - - - - - - - . MASK ROM . MSM2916RS.
ABSOLUTE MAXIMUM RATINGS
Symbol

Value

Unit

Supply Voltage

Rating

Vee

-0.5 to +7.0

V

Input Voltage

VI

-0.5 to +7.0

V

Vo

-0.5 to +7.0

V

Output Voltage
Operating Temperature

Topr

o to +70

°c

Storage Temperature

Tstg

-55 to +150

°c

RECOMMENDED OPERATING CONDITIONS
Symbol

Min.

Typ.

Max.

Unit

Supply Voltage

Vee

4.5

5.0

5.5

V

"H" I nput Voltage

VIH

2.0

Vee

V

-0.5

0.8

V

Parameter

"L" Input Voltage

VIL

DC CHARACTERISTICS
(Vee = 5 V ± 10%, Vss = 0 V, Ta = O°C to +70°C)
Parameter

Symbol

"H" Input Voltage

Conditions

VIH

"L" I nput Voltage

V'L
IOH

= -100~A

IOL

= 1.6mA

Min.

Typ.

Max.

Unit

2.0

Vee

V

-0.5

0.8

VOH

"L" Output Voltage

VOL

I nput Leak Current

III

Output Leak Current

ILO

Vo = 0 - Vee

10

~A

Power Supply Current

Icc

Vee = 5.5V

100

mA

Input Capaei ty

C1

6

pF

12

pF

VI

2.4

V

"H" Output Voltage

V

= 0 - Vee

0.4

V

10

~A

V I = OV, Vo = OV
Output Capacity

Co

f

= 1 MHz

Ta=25°C

AC OPERATING CHARACTERISTICS
(Vee = 5 V ± 10%, Vss = 0 V, Ta = O°C to +70° C)
Symbol

Min.

Read Cycle time

tCYC

250

Address Access time

Parameter

Max.

Unit
ns

tACC

250

ns

Chip Select Access time

tcs

100

ns

Output Disable Delay time

tDF

100

ns

127

• MASK ROM . MSM2916RS ••-.- - - - - - - - - - - - - - - -

VIH

= 2.0V,

Output Load

ADDRESS

~1$V
... 1

1.5V+ - t c s - -

I

128

HIGH Z

VOL

X
tACC

CHIP SELECT

Output

= O.8V, VOH = 2.0V,
= 1 TTL GATE + 100PF

VIL

/
'\

J

---"
tDF

= O.8V

OK.I

semiconductor

MSM2932RS
32,76B-BITS STATIC-32K MASK ROM

GENERAL DESCRIPTION
The MSM2932RS is a 32,768-bits static, N channel MOS Read only memory organized as 4,096 words by 8 bits.
The three-state outputs and TTL inputs/outputs level allow for direct interface with common system bus structures.
The MSM2932RS single +5 V power supply and 300 ns access time are both ideal for usage with high performance
microcomputers.
The two chip selects CS 1 and CS 2 may be defined by customer and fixed during the masking process.
ROM DATA Accepting flow from customer.
Preparing next two in customer's side
1)
Two master devices, programming finished 32K Ep· ROM.
2)
Chip select CS 1 and CS 2 logic table.
A fter received customer's ROM DATA, print out ROM DATA in Hex CODE and copy finished 32K EP· ROM send to
customer.
Verified ROM DATA in customer's side, OKI send engineering samples mask programed customer's ROM DATA.

FEATURES
•
•
•
•
•
•

Organization
Static Operation
Supply Voltage
Access Time
Power Dissipation
Input Voltage

4096W x 8 bit
No clocks required
5 V ±10%
300 ns Max.
550mW Max.
V,H = 2.0V Min.,
V,L = 0.8V Max.

• Output Voltage
• Package

VOH = 2.4 V Min.,
VOL = 0.45 V Max.
24 PIN DIP

FUNCTIONAL BLOCK DIAGRAM

VccO----

PIN CONFIGURATION

Note:

A7

Vee

A6

As

As

A9

A3

eS 2
es,

A2
A,

AID

Ao

07

0,

06
Os

Vss 0----

AIl

O2

04

Vss

03

CS 1 , CS 2 are programmable CHIP SELECTS

129

• MASK ROM . MSM2932'RS ••r - - - - - - - - - - - - - - - - - ABSOLUTE MAXIMUM RATINGS
Symbol

Value

Unit

Supply Voltage

Rating

Vee

-0.5 to +7.0

V

Input Voltage

VI

-0.5 to +7.0

V
V

°c
°c

Output Voltage

Vo

-0.5 to +7.0

Operating Temperature

Topr

o to +70

Storage Temperature

Tstg

-55 to +150

RECOMMENDED OPERATING CONDITIONS
Parameter

Symbol

Min.

Typ.
5.0

Max.

Unit

Vee

4.5

5.5

V

"H" I nput Voltage

VIH

2.2

Vee

V

"L" I nput Voltage

VIL

-0.5

0.8

V

Supply Voltage

DC CHARACTERISTICS
(Vee = 5V ± 10%, Vss = OV, Ta = O°C to +70°C)
Conditions

Symbol

Parameter
"H" Input Voltage

I

Min.

Typ.

Max.

Unit

2.0

' Vee

V

-0.5

0.8

V

VOL

IOL = 1.6 mA

0.4

V

VIH

"L" Input Voltage

VIL

"H" Output Voltage

VOH

IOH = -100J.LA

"L" Output Voltage
Input Leak Current

V

2.4

III

VI = 0 - Vee

10

J.LA

Output Leak Current

ILO

Vo = 0 - Vee

10

J.LA

Power Supply Current

Icc

Vee = 5.25V

100

mA

6

pF

12

pF

V I = OV, V 0 = OV
I nput Capacity

C1

Output Capacity

Co

f = 1 MHz

Ta = 25°C

AC OPERATING CHARACTERISTICS
(Vee

=

5 V ± 10%, Vss

=

0 V, Ta

=

O°C to +70°C)

Parameter

Symbol

Min.

Read Cycle time

tCYC

300

Address Access time

tACC

Chip Select Access time
Output Disable Delay time

-----

130

Max.

Unit
ns

300

ns

tcs

100

ns

tDF

100

ns

- - - - - - - - - - - - - - - - - - . MASK ROM . MSM2932RS.

VIH = 2.0V. VIL
Output Load

ADDRESS

= 1 TTL

VOH

= 2.0V.

= O.8V

X
tACC
1.5V

HIGH Z

VOL

GATE + 100PF

t1.5V

CHIP SELECT

Output

= O.8V.

.1

tcs---

/

"-

/

----"
tDF

I

131

OK.I

semiconductor

MSM2965RS
65,536 BITS STATIC 64K MASK ROM

GENERAL DESCRIPTION
The MSM2965RS is a 65336-bits static, N channel MOS Read only memory organized as 8,192 words by 8 bits.
The three·state outputs and TTL inputs/outputs level allow for direct interface with common system bus structures.
The MSM2965RS single +5 V power supply and 300 ns access time are both ideal for usage with high performance
m icrocompu ters.
CS 1 may be defined by customer and fixed during the masking process.
ROM DATA Accepting flow from customer.
Preparing next two in customer's side
1)
Two master devices, programming finished 64K EP. ROM or two 32K EP. ROMs.
2)
Chip select CS logic table.
After received customer's ROM DATA, print out ROM DATA in Hex CODE and copy finished 64K EP. ROM or two
32K EP. ROMs send to customer.
Verified ROM DATA in customer's side, OKI send engineering samples mask programed customer's ROM DATA.

FEATURES
•
•
•
•
•
•

8192W x 8 bit
No clocks required
5 V ± 10%
300 ns Max.
687 mW Max.
VIH = 2.0 V Min.,
VIL=O.8VMax.

Organization
Static Operation
Supply Voltage
Access Time
Power Dissipation
Input Voltage

• Output Voltage
• Package

VOH = 2.4 V Min.,
VOL = 0.4 V Max.
24 PIN DIP

FUNCTIONAL BLOCK DIAGRAM

Do

..

---.-~~-- -~----------------I

Vee

PIN CONFIGURATION
Vee
As

A"
A,

A9

AJ

es

A,

AIO

A,

All

An

D7

A"

D"
D,
D.
D.,

Note:

132

CS is programmable CHIP SELECTS.

0----

vss~

Dl - - - - - - - - D 7

- - - - - - - - - - - - - - - - - ' . MASK ROM . MSM2965RS.
ABSOLUTE MAXIMUM RATINGS
Rating

Symbol

Value

Unit

Vee

-0.5 to +7.0

V

I nput Voltage

VI

-0.5 to +7.0

V

Output Voltage

Vo

-0.5 to +7.0

V

Supply Voltage

Operating Temperature

Topr

Storage Temperature

Tstg

o to

°c

+70

°c

-55 to +150

RECOMMENDED OPERATING CONDITIONS
Symbol

Parameter

Min.

Typ.
5.0

Max.

Unit

Vee

4.5

5.5

V

"H" Input Voltage

VIH

2.0

Vcc

V

"l" Input Voltage

Vil

-0.5

0.8

V

Max.

Unit

Supply Voltage

AC OPERATING CHARACTERISTICS
(Vee

=5 V

= 0 V, Ta = O°C to

± 10%, Vss

+70°C)

Parameter

Symbol

Min.

tCYC

300

Read Cycle time

ns

tACC

300

ns

Chip Select Access.time

tcs

100

ns

Output Disable Delay time

tDF

100

ns

Address Access time

DC CHARACTERISTICS
(Vee

=5 V

± 10%, Vss

= OV, Ta = O°C to

Parameter
"H" Input Voltage
"l" I nput Voltage

Symbol

+70°C)
Conditions

Min.

Typ.

Max.

Unit

VIH

2.0

Vec

V

Vil

-0.5

0.8

V

"H" Output Voltage

VOH

"l" Output Voltage

VOL

Input leak Current

III

VI = 0

Output leak Current

IlO

Vo = 0

Power Supply Current

Icc

Vee = 5.5V

Input Capacity

C1

Output Capacity

Co

IOH = -100/-LA
IOl = 1.6 mA
~

Vce

~

Vcc

2.4

V
0.4

V

10

/-LA

10

/-LA

125

mA

6

pF

12

pF

V I = OV, V 0 = OV
f = 1 MHz

Ta = 25°C

133

• MASK ROM . MSM2965RS ••- - - - - - - - - - - - - - - - - -

= 2.0V, VIL = O.8V, VOH = 2.0V,
Output Load = 1 TTL GATE + 100PF
VIH

ADDRESS

*1.5V

X
tACC

_I

CHIP SELECT
'{--tcs-I
Output

134

HIGH Z

VOL

,

/

J

tDF
t-----

...

= O.8V

O~I semiconductor

MSM38128RS
16384 WORD X 8 BIT MASK ROM

GENERAL DESCRIPTION
MSM38128RS is an N-channel silicon gate E/D MaS device ROM with a 16,384 word x 8 bit capacity. It operates on
a 5V single power supply and the all inputs and outputs can be directly connected to the TTL. The adoption of an
asynchronous system in the circuit requires no external clock assuring extremely easy operation. The availability of
power down mode contributes to the low power dissipation which is as low as 20 mA (max) when the chip is not
selected. The application of a byte system and the convertibility of the pins with a programmable ROM whose
memory can be erased by ultraviolet ray radiation is most suitable for use as a large-capacity fixed memory for
microcomputers and data terminals.
Since it provides both CE and OE signals, the connection of output terminals of other chips with the wired OR is
possible ensuring an easy expand operation of memory and bus line control.

FEATURES
• 16384 words x 8 bits
.5V single power supply
• Access time: 450 ns MAX

• Input/output TTL compatible
.3-state output

• Power down mode
.28-pin DIP

FUNCTIONAL BLOCK DIAGRAM

PIN CONFIGURATION
Vee

NC

~-D7

Note:

A3
A4

As

As

Ag

A6
A,

A3

DE

A2

A lo

CE

OE
Vcc, Vss
Ao-A13

AI
A2

AI3

All

Ao

0,

Do

06

0

Os

1

Ao

O2

04

Vss

03

As

Ag
A lo
All
AI2
AI3

Output enable
Power supply voltage
Address input
Data output
Chip enable

The 0 E active level is
specified by customer.

135

- - - - - - - - - - - - - - - - - 1 . MASK ROM . MSM38128RS.

ABSOLUTE MAXIMUM RATINGS
(Ta = 25°C)
Symbol

Rating

Unit

Power Supply Voltage

Vee

-0.5 to 7

V

I nput Voltage

VI

-0.5 to 7

V

Output Voltage

Vo

-0.5 to 7

V

Item

Operating Temperature

Topr

Oto 70

°c

Storage Temperature

T stg

-55 to 150

°c

Conditions

Respect to V ss

OPERATING CONDITION AND DC CHARACTERISTICS
Rating
Item

Symbol

Measuring Condition
Typ.

Max.

4.5

5

5.5

Vss

0

0

0

V

VIH

2

5

6

V

-0.5

0

0.8

V

Vee

V

Vee

Power Supply Voltage

I nput Signal Level

VIL
VOH

Output Signal Level

10H = -400,."A

2.4

0.4

V

VOL

10L = 2.1 mA

III

VI = OVor Vee

-10

10

,."A

Output Leak Current

ILO

Vo = OV or Vee
Chip not selected

-10

10

,."A

Icc

Vee = Max. 10 = 0 mA

120

mA

Ices

Vee = Max.

20

mA

Peak Power ON Current

Ipo

Vee = GND ~ Vee Min.
CE = Veo or VIH

20

mA

Operating Temperature

Topr

70

°c

0

AC CHARACTERISTICS
TIMING CONDITIONS
Item

Conditions

I nput Signal Level
Input Rising, Falling Time

tr=ty=15 ns
Input Voltage=1.5V

Timing Measuring Point Voltage
Output Voltage=0.8 & 2.0V
Loading Condition

136

V

Input Leak Current

Power Supply Current

D

Unit
Min.

CL=100 pF

+ 1 TTL

- - - - - - - - - - - - - - - - - - - MASK ROM . MSM38128RS_
READ CYCLE
Specification Value
Item

Symbol

Unit
Min.

Cycle Time

tc

Address Access Time

tAA

ns

tACE

450

ns

150

ns

Output Delay Time

tco
tLZ

Output Disable Time

tHZ

0

Output Retaining Time

tOH

20

Power Up Time

tpu

Power Down Time

tpD

1) READ CYCLE-1

ns

450

Output Setting Time

ns

20

0

Remarks

Max.

450

Chip Enable
Access Time

Typ.

120

ns
ns

120

ns

120

ns

(1)

~-----------------tc--------------~

Address

OE (3)
(4)

t------tHZ ----11-1
Dout

2)

READ CYCLE-2(2)

t----------------tc--------------~

OE (3)

Dout
tpu
Vcc
supply
current

Icc
Iccs

137

- - - - - - - - - - - - - - - - - - . MASK ROM . MSM38128RS.
Note:

(1)
(2)
(3)

CE is "L" level.

(4)

teo and tLZ are determined by the later CE "L" or OE "L".

The address is decided at the same time as or ahead of CE "L" level.
OE is shown in the negative logic here, however the active level is freely selected.
tHz is determined by the earlier CE "H" or OE "H".
tHz shows time until floating therefore it is not determined by the output level.

INPUT/OUTPUT CAPACITY
(Ta = 25°C, f = 1 MHz)

Item

Symbol

Specification
Value
Min.

138

Unit

Remarks

Max.

I nput Capacity

CI

8

pF

VI=OV

Output Capacity

Co

10

pF

VO=OV

OK.I

semiconductor

MSM28101AS
CHINESE·CHARACTER GENERATING 1M BIT MASK ROM

GENERAL DESCRIPTION
MSM28101AS is a 1M Bit Mask ROM using the N channel silicon gate MOS process which stores 3,760 characters of
numeric characters, Japanese cursive and square syllabarys, JIS 1st standard chinese-characters, etc., in one chip.
Since it is of large capacity, chinese-character pattern of 3,760 characters can be generated with only one chip.
Furthermore, since the dot matrix character form of 18 lines x 16 strings is available from the data out pin by only
inputting the JIS chinese-character code into the address pin, it excels in functioning property and proves optimum
for constituting the chinese-character terminal.
The power supply voltage is of 5 V single power supply, the input level is of TTL compatible, the data output is of
3-state output, the data valid is the output of the open collector and is packaged on the 40-pin DIP.

FEATURES
18 x 16 chinese-character font
output
Configuration
Duplex configuration of cellarray using the defect permissible
technique
Storage capacity 1082880 Bits
Number of
3,418 characters
generating
characters
Storage
Partition 0 - 7 and partition
character range 16 - 47 of chinese-character code
system for JIS information
processing
14 Bits (A o -A 13 )
Address input
16 Bits (0 0 -0 15 , 3-state)
Data output
16 Bits x 18 times transfer
Output mode
Address enable 1 each (AE)
1 each (DV, open collector output)
Data valid

• Function
•

•
•

•

•
•
•
•
•

• Clock
• Used temperature
• Access time
• Data transfer
rate
• Interface
• Power supply
voltage
• Power consumption
• Package
• Process
• Memory cell

1 each (¢r)DC - 500 kHz
Ta = 0 - 70°C
25p.s MAX
8M Bit/s
TTL level
5V single power supply (±5%)
500 mW TYP

Semi-ceramic 4~pin DIP
E/D MOS process
Multi-gate ROM

This specification is sometimes subject to change without
notice

PIN CONFIGURATION

Ao-A IS : Address input
Do-~: Data output
AE: Address enable
DV: Data valid output
¢r: Clock input
VCC: Power supply voltage (5V)
VSS: GND (QV)

(Note) Connect all VCC and VSS terminals.

Vss =-____--'=

139

D

• MASK ROM . MSM28101AS ••- - - - - - - - - - - - - - - -

FUNCTIONAL BLOCK DIAGRAM

AE

DV

?iT
Ao
AI

A3

Do

Address
&
Decoder

A2

o--

Data
latch

1M Bit cell array

~

n;
n;

A.
As

~

A6

L>s

Selector

l5;

A7
As

D,

A9

0!J9

AIO
Data
latch

1M Bit cell array

All

1),0

r>U

AI2

~

AI3

013
J:il4
~

ABSOLUTE MAXIMUM RATINGS
(Ta = 25°C)
Item

Symbol

Conditions

Unit

Rating

Power supply voltage

Vcc

Respect to Vss

-0.3

~7

Input terminal voltage

VIN

Respect to Vss

-0.3

~7

V

Respect to Vss

-0.3

~7

V

0~70

°c
°c

Output terminal voltage
Permissible loss

VOUT

Topr

Storage temperature

Tstg

W

2

Po

Operating temperature

V

-35 - 125

RECOMMENDED OPERATING CONDITIONS
Specification value
Item
Power supply voltage
Power supply voltage
Input signal level
Operating temperature

140

Symbol

Conditions

Vcc

5V ± 5%

Unit
Min.

Typ.

Max.

4.75

5

5.25

V

0

0

0

V

VIH

Respect to Vss

2.0

5

6

V

VIL

Respect to Vss

-0.3

0

0.8

V

Vss

Topr

0

70

°c

- - - - - - - - - - - - - - - -•• MASK ROM· MSM28101AS.
DC CHARACTERISTICS
(Vcc

= sv ±S%, Ta = o°c to + 70°C)
Conditions

Symbol

Item

Specification value
Unit
Min.

V

IOL =1.6 mA

0.6

V

=O.B mA

0.4

V

IOH=-0.2 mA

VOL
VOL

Input leak current
Output leak current

Max.
Vcc

VOH
Output signal level

Typ.

IOL

2.4

III

VIN=O ..... Vcc

-10

10

p.A

ILO

VOUT=O ..... Vcc
VAE=O.BV

-10

10

p.A

Average power supply current
ICCA

tRC=61 p.s,
tC=2 p.s
tAR=SOO ns

120

mA

ICCS

VAE=O.BV

120

mA

Steady state power supply current

AC CHARACTERISTICS
TIMING CONDITIONS
Conditions

Item
Input signal level

VIH = 2.0V, VIL = O.BV

Input rising, falling time

tr

Input timing level

1.SV

Loading condition

CL = so pF, 1TTL Gate

= tf = 1S ns

READ CYCLE
(Vcc = sv ±S%, Ta = o°c to

+ 70°C)
Specification Value

Item

Symbol

Unit

Conditions
Min.

Read Cycle Time

tRC

Address Setting Time

Typ.

Max.

61

p.S

tAS

0

ns

AE Pulse Width

tAE

SOO

ns

Address Retaining Time

tAH

300

OV Access Time

tVA

OV Delay Time

tvo

400

ns
2S

p.S

BOO

ns

900

ns

OV Retaining Time

tVH

cJ>r Pulse Width

tH

200

ns

cJ>r Delay Time

tL

1BOO

ns

Output Delay Time

too

Output Access Time

tOA

Output Retaining Time

tOH

AE Setting Time

tAES

ns

0

BOO

ns

400

ns

0

ns

141

• MASK ROM . MSM28101AS -.------~----------

3 f

(Ao
-A )
ADDRESS

VALID

13

-

____________________________________
___
DON'T CARE

'A~

I . . . . - - - '

AS
AE

~-----------------------tRC----------------------~

DOUT

(Da-O-;s)
High Impedance

(Note
(Note
(Note
(Note
(Note

1)
2)
3)
4)
5)

(Note 6)

High Impedance

DV is determined by the falling of c/>T.
DV changes with the falling of c/>T.
c/>T and On DATA are repeated 18 times during DV is Low.
The On timing levels are 2.0 V and 0.8 V.
Sometimes it will not normally operate unless input is made at least once with
AE as the dummy after input of power supply.
DV is an open collector output and On is a 3-stage output.

INPUT/OUTPUT CAPACITY
(Ta = 25°C, f = 1 MHz)

Item

Symbol

Condition

Specification value
Min.

Typ.

Max.

Unit

Input capacity (excluding AE)

CIN

VIN = OV

15

pF

Input capacity (AE terminal)

CIN

VIN = OV

35

pF

VOUT= OV

10

pF

Output capacity

142

COUT

- - - - - - - - - - - - - - - - - - . MASK ROM . MSM28101AS.
FUNCTIONAL CHARACTERISTICS
Item

Specification

Unit

Font type

18 lines x 16 strings dot matrix

Output mode

16 bits x 18 times transfer

Number of generating
characters

3418

Storage character range

o '" 7 (Non chinese-character area)

(Note 1)
Word
Partition

16", 47 (JIS 1st standard)
(Note 1)

Remarks

(Note 2)

The correspondence of the 181i nes x 16 strings matrix and the data out pins are as shown in the diagram
below.
Output for the character portion will be Low (Vod and the output for the background portion will be
High (VOH).

....- - - - - - - - 1 6 lines - - - - - - -......-

18
stri

-+--t--+-+~ t=AT17
...........__........... t=AT18

DV

~I----------~lt~-----------------------

¢T

I

I

.1.

I-

ATI

(Note 2)

I

..I
AT z

The correspondence of the 1st and 2nd bytes of JIS C 6226 and the address pins are as shown below.

Address pin

First byte

Second byte

JIS C 6226
b7
Al3

b,

bs

b4

b3

bz

bl

b7

b6

bs

b4

b3

bz

bl

Al2

All

AlO

A9

As

A7

Ali

As

A4

A3

Az

Al

Ao

143

OK.I

semiconductor

MSM28201AS
1M BIT MASK ROM FOR CHINESE-CHARACTER PATTERN

GENERAL DESCRIPTION
MSM28201 is a 1M-bit mask ROM employing an N-channel silicon gate MOS process, and with 3760 chinese-characters (kanji conforming with JIS no.2 standards) incorporated in a single chip.
With this large capacity, 3760 chinese-character patterns can be generated in a single chip. And by only a single
input of JIS chinese-character code via the address pin, 18-row x 16-column dot matrix character forms can be
obtained from the data output pin, making this device ideal for construction of functionally versatile chinese-character terminals.
The power supply voltage is 5V single, the input level TTL compatible, outputs are tri-state data out, and data valid
is denoted by open collector. The device is mounted in a 40-pin DIP.

FEATURES
· 18 x 16 chinese-character font
output
Configuration
. Duplex configuration employing
defect permissible technique
Storage capacity. . 1082880 bits
Number of generated
characters . . . . . . 3384 characters
Accommodation . . . Chinese-character encoded
character region
partitions 48 to 87 for JIS
data processing.
· 14 bits (Ao to Au)
Address input
· 16 bits (Do to D 15 ' tristate)
Data output .
· 16 bit x 18 transfers
Output mode

• Function ...
•
•
•
•

•
•
•

•
•
•
•
•
•
•
•
•
•
•
•

Address enable .. ,
Data valid . . . . . .
Clock . . . . . . . . .
Operating temperature . . . . . . . . . .
Access time . . . . .
Data transfer rate . .
Interface . . . . . . .
Power supply voltage
Power consumption.
Package. . .
. ..
Process . . .
. . .
Memory cell
.•.

1 (AE)
1 (DV, open collector output)
1 (I/>T) DC to 500kHz
Ta=O°C to 70°C
25us MAX.
8M Bits/sec.
TTL level
5V single (±5%)
500mW TYP
Ceramic 40-pin DIP
E/D MOS process
Multi-gate ROM

PIN CONFIGURATION

Vss 20

Ao - A 13 : Address inputs
Do - DIs: Data outputs
AE: Address enable
DV: Data valid output
I/>T: Clock input
Vcc: Power supply voltage (5 V)
Vss: GND (0 V)
Note: All Vss pins are to be connected

144

- - - - - - - - - - - - - - - - - - . MASK ROM . MSM28201AS.

FUNCTIONAL BLOCK DIAGRAM

AE

DV

Ao
A.
A2
A3
A4
As
A6
A,

05;,

1 MBit
Cell Array

0.

0.

~

0:

Os

Selector

0.
D,

As
A9
A. o
All
An
Au

0.
~

1 MBit
Cell Array

0. 0
011

0;2
0. 3
D ••
00. 5

ABSOLUTE MAXIMUM RATINGS
(Ta = 25°C)
Item

Symbol

Rating

Unit

-0.3 ...... 7

VI

Respect to Vss

-0.3 ...... 7

V

Vo

Respect to Vss

-0.3 ...... 7

V

Vcc

Input voltage
Output voltage

Conditions
Respect to Vss

Power supply voltage

V

Permissible loss

Po

Operating temperature

Topr

0 ...... 70

°c

Storage temperature

Tstg

-35 ...... 125

°c

W

2

RECOMMENDED OPERATING CONDITIONS
Item
Power supply voltage

Symbol
Vcc

Power supply voltage

Vss

"Hit input voltage

VIH

"L" input voltage

VIL

Operating temperature

Topr

Conditions

MIN

Range Value
TYP
MAX

Unit

4.75

5

5.25

V

0

0

0

V

Respect to Vss

2.0

5

6

V

Respect to Vss

-0.3

0

0.8

V

70

°c

5V ± 5%

0

145

• MASK ROM . MSM28201AS ••- - - - - - - - - - - - - - - DC CHARACTERISTICS
(Vcc = 5V ±5%, Ta = o°c to + 70°C)

Item

Symbol

Range Value

Conditions
MIN

"H" output voltage
"L" output voltage
Input leak current

TYP

2.4

Unit
MAX

VOH

IOH=-0.2mA

Vee

V

VOL

IOL=1.6mA

0.6

V

VOL

IOL=0.8mA

0.4

V

III

VI=O'" Vee

-10

10

#LA

Output leak current

ILO

VO=O'" Vee
VAE=0.8V

-10

10

#LA

Average power supply current

ICCA

tRC=611ls, tc= 2lls
tAE=500ns

120

mA

Rated power supply current

ICCS

VAE=0.8V

120

mA

AC CHARACTERISTICS
TIMING CONDITIONS
Item

Conditions

Input signal level
I nput rise/fall time

tr=tf=15ns

Input timing level

1.5V

Output load

CL=50pF, 1TTL Gate

READ CYCLE
(VCC

= 5V ±5%, Ta = o°c to +70°C)
Range Value
Item

Symbol

Unit

Conditions
TYP

MIN
Read cycle time

MAX

tRC

61

Address set-up time

tAS

0

O=ns

AE pulse width

tAE

500

O=ns

Address hold time

tAH

300

O=ns

o V access time

tVA

25

IlS

800

O=ns

900

O=ns

OV delay time

tvo

OV hold time

tVH

~T

pulse width

tH

200

O=ns

~T

delay time

tL

1800

O=ns

0

O=ns

Output delay time

too

Output access time

tOA

Output hold time

tOH

AE set-up time

146

tAES

400

IlS

800
400

O=ns
O=ns
O=ns

- - - - - - - - - - - - - - - - - - . MASK ROM . MSM28201AS.

Address
(Ao "",Au) _ _ _..J

DON'T CARE

VALID

AE

tVA

tc

(Note 3)
D
OUT
(Do "",DIs)

------------------~r_--------__u
High Impedance

NOTE:

(Note 4)

High Impedance

1. DV is determined by the cpT falling edge.
2. DV is changed by the cpT falling edge.
3. cpT and DnDATA are repeated 18 times when DV is low.
4. Dn timing levels of 2.0V and 0.8V.
5. Normal operation may not be possible unless there is at least one AE dummy input after
the power is switched on.
6. DV denotes open collector output, and On the tristate output.

INPUT/OUTPUT CAPACITY
(Ta=25°C, f=1 MHz)

Range Value
Item

Symbol

Conditions
MIN

Input capacity (excluding AE)

TYP

Unit
MAX

CI

VI=OV

15

Input capacity (AE pin)

CI

VI=OV

35

pF

Output capacity

Co

VO=OV

10

pF

pF

147

• MASK ROM . MSM28201AS ••; - - - - - - - - - - - - - - - - - - - FUNCTIONAL CHARACTERISTICS
Remarks

Unit

Range

Item
Font format

18-row x 16-column dot matrix

Output mode

16 bit x 18 transfers

(Note 1)
Word

Number of characters generated

3384

Character accommodation region

48.....87 (JIS No.2 standard)

Partition

(Note 2)

Note 1. The relation between the 18-row x 16-column matrix and the data output pins is outlined below. The output
is low (VOL) for the character portion, and high (VOH) for the background area.

t - - - - - - - - - - 1 6 columns ------~
t=l:!.-r l
t=l:!.-r z

I

I
I

I
I
I

I
I

18 rows I--+--t--+--+--

I
I

I

i

I
I

I

tt:t~~tt~:.t~~tt

Data output pins

0;; 0: Oz OJ

~ 05 0'6

D,Da 0'9 0100110120U014015

~I------------~1}~----------------------~

I

q,T
I
11

I

.: ..
I

I:!.Tl

I

1

I

~:I

I

1

I-

.-,

1:!.-r18

I:!.T z

Note 2. The address pins are related to the JIS C6226 no.1 and no.2 bytes in the following way.
No.1 bytes

No.2 byte
JIS C 6226
Address pin

148

Tb, I bs I b4 I b I bz I b1
A 13 TAl I All J Al I A9 I As I A7
b7

J

Z

0

b7
A,

I b, Tb s I b 4 I b3 I bz

I As

T A4

1A3 I A z I Al

b1
Ao

OK.I

semiconductor

MSM53256AS/RS
32,768 WORD X 8 BIT MASK ROM

GENERAL DESCRIPTION
MSM53256AS/RS is a silicon gate C-MOS device ROM with a 32,768 words x 8 bit capacity. It operates on a 5 V
single power supply and all inputs and outputs can be directly connected to the TTL. The adoption of an
asynchronous system in the circuit requires no external clock assuring extremely easy operation. The availability of
power down mode contributes to the low power dissipation which is as low as 50 J.l.A (max) when the chip is not
selected. The application of a byte system is most suitable for use as a large-capacity fixed memory for microcomputers and data terminals.
Since it provides CE, CS and OE signals, the connection of output terminals of other chips with the wired OR is
possible ensuring an easy expand operation of memory and bus line control.

FEATURES
• 32,768 words x 8 bits
• 5V single power supply
• Access time: 250 ns MAX

• Input/output TTL compatible
.3-state output

• Standby current 50 J.l.A MAX
.28-pin DIP

FUNCTIONAL BLOCK DIAGRAM

PIN CONFIGURATION
Vee

Ao
AI
A2
A3

AI3

A.

As

As

A9

A6
A7

All

DE
A2

A lo

CE

OE
Vee, Vss
Ao~AI 3
Do~D7

CE"
CS

Note:

Ao

07

Do

06

01

Os

O2

D.

Vss

D3

As
A9

CE

A lo
All

5E

AI2

CS

AI3
AI,

es

Or

Output enable
Power supply voltage
Address input
Data output
Chip enable
Chip select
The- CS active level is
specified by customer.

149

n

MOS
EPROMS

OK.I

semiconductor

MSM2750AS
2048-BIT UV ERASABLE ELECTRICALLY -PROGRAMMABLE
READ-ONLY MEMORY

GENERAL DESCRIPTION
MSM 2750 is a Programmable Read-Only Memory (PROM) of P-channel structure capable of electric write from
outside and rewrite after erasion by ultraviolet rays.

PIN CONFIGURATION

FUNCTIONAL BLOCK DIAGRAM

Data Output 0

Data Output 7

Output Butter

DATA OUTO 4

oun

5

DATA OUT2

6

DATA OUT3

7

DATA

2048 Bit (256 x 8)

Program

Memory Matrix

VGG

Address Decoder

VBB

cs
PROGRAM

Address Butter

ABSOLUTE MAXIMUM RATINGS
Rating

Unit

Read

+0.5'" -20

V

Program

+0.5 "'-48

V

Symbol

Parameter
Input and Supply Voltage

I

I

Power Dissipation
Storage Temperature

152

Po
Tstg

2 Max.
-55'" +125

W

°c

---------------------------------------.EPROM .

MSM2750AS.

READ OPERATION
RECOMMENDED OPERATING CONDITIONS
Parameter

Supply Voltage

Operating Temperature

Symbol

Conditions

Range

Unit

VCC

5 ± 0.25

V

VDD

-9 ± 0.45

V

VGG

-9 ± 0.45

V

Topr

o ~ +70

°c

Load Number

N

1

TT L Gate Load

STATIC ELECTRICAL CHARACTERISTICS
Parameter

Symbol

Conditions

Min.

Typ.

Max.

Unit

Input "H" Voltage

VIH

Vee
-2

Vee
+0.3

V

Input "L" Voltage

VIL

-1.0

Vee
-4.2

V

0.45

V

Output "H" Voltage

VOH

10H = -100 #LA

Output ilL" Voltage

VOL

10L = 1.6 mA

Input Leakage Current

V

3.5

IlL

VIN = OV

1

#LA

Output Leakage Current

ILO

VOUT= OV
CS = Vee - 2V

5

#LA

Gate Supply Current

IGG

1

#LA

Supply Current

100

CS=OV
DATAOUT OPEN

45

mA

Output Clamp Current

ICF

VOUT = -1.0V

13

mA

Max.

Unit

100

nS

30

AC CHARACTERISTICS
Parameter

Symbol

Oata Valid Time

tOH

Access Time

tACC

Chip Select Delay

tcs

Output Delay from cs

tco

Output Deselect

too

(Note)

Conditions

Input Pulse Amplitude
=0~4V

Rise and Fall Time of
Input Pulse ~ 50 nS
Output Load
= 1 TTL Gate

Min.

Typ.

X
V:a:

nS

1.2

nS

300

900

nS

300

nS

Numerals above and below the oblique line respectively show the values of each MSM2750-1 A and
MSM2750-2A.

153

• EPROM . MSM2750AS ••- - - - - - - - - - - - - - - - - - -

CYCLE TIME

I"
I

VIH
ADDRESS
VIL

= 1/FREQ

-I

=>{10%

X

: 90%

I
----I tcs

'{

I
I

VIH
CS

I
I

VIL

I

I
I tOH

r---

I

I"

I

~

,
I
1

I

I

I

\ y~-r1

VOH
DATAOUT
VOL

DATA OUT
INVALID

:

I

I

tACC

I"

"I

DATA OUT
INVALID

ADDR;~ ~:~------------------~~~-------------l~:
90%
__

L-/:
1

--I~ 1

VOH
DATA OUT
VOL

~~1-00-~---------------------

I

I

I

VI,'

~tODI--~-------1

I

----, tco r-----

PROGRAMMING
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage
Operating Temperature

154

Symbol
VBB

Conditions

Range

Unit

11 - 13

V

Vcc,CS

0

V

Topr

20- 30

°c

- - - - - - - - - - - - - - - - - - - . EPROM . MSM2750AS.
STATIC ELECTRICAL CHARACTERISTICS
Parameter
Input "H" Voltage

Conditions

Symbol

Min.

Typ.

VIHP

Max.

Unit

0.3

V

Data Input Pulse ilL" Voltage

VILP1

-46

-48

V

Address Input Pulse "L"
Voltage

VILP2

-40

-48

V

"L" VDD Input Pulse Voltage

VILP3

-46

-48

V

Program Input Pulse ilL"
Voltage

VILP4

-46

-48

V

VGG Input Pulse ilL"
Voltage

VILP5

-35

-40

V

I DD Pulse Supply Current

IDDP

VDD = V prog = -48V
VGG = -35V

Address Data I nput Leakage
Current

IILP1

VIN = -48V

10

mA

Program VGG Leakage
Current

IILP2

VIN =-48V

10

mA

Max.

Unit

20

%

3

mS

200

mA

AC CHARACTERISTICS
Parameter

Symbol

Conditions

Min.

Duty Cycle (VDD, VGG)
Program Pu Ise Width

t(j>PW

Data Setup Time

tDW

Data Hold Time

tDH

Rise and Fall Time
of Input Pulse
Time ~ 1 J,J.S

25

J,J.S

10

J,J.S
J,J.S

VDD, VGG Setup Time

tvw

100

VDD, VGG Hold Time

tVD

10

100

J,J.S

tACW

25

J,J.S

Address Complement Hold Time

tACH

25

J,J.S

Address True Setup

tATW

10

J,J.S

tATH

10

J,J.S

Address Complement Setup Time

Address True Hold

155

• EPROM· MSM2750AS - . - - - - - - - - - - - - - - - - - -

o
ADDRESS

-40 to -48

!----..

tAcw-----+\

BINARY COMPLEMENT
ADDRESS OF WORD
TO BE PROGRAMMED

BINARY COMPLEMENT
ADDRESS OF WORD
TO BE PROGRAMMED
I

I

POWER SUPPLY

: '\
I
I I

-40 to -48

o

1

____________

~

I

1

II

I ----1

----------------\1::
1

PULSED VDOD

I

I

I

ItATW

I

1:1, - - - - - - 1 " - - -

II

/:
I

1

I

I

I

1

I

-35 to -40

I

I

1

ItVW
_____________---ll----,~II . t(j>PW

:~~:AMMING

!"

-46to-48

I
1

I

o
DATAINPUT
(DEVICE OUTPUT
LINES)

-46 to-48

156

DATA CAN
CHANCE

)

i
I
1

I

I
I

y;--tATH~
~)'

I

tow

:

I

I

o

I

I

1i!

PULSED VDD
POWER SUPPLY

I - - tVD

---....,

I tDH

1---+1
1

DATA STABLE
TIME

I----I

I
1
I

I

DATA CAN
CHANCE

OK.I

semiconductor

MSM2708AS
8192-BIT UV ERASABLE ELECTRICALLY-PROGRAMMABLE
READ-ONLY MEMORY

GENERAL DESCRIPTION
The Oki MSM2708 AS (Compatible to the Intel 2708) is a 8192~bit ultraviolet light erasable and electrically reprogrammable EPROM, ideally suited where fast turnaround and pattern experimentation are important requirements.
All data inputs and outputs are TTL compatible during both the read and program modes. The outputs are threestate, allowing direct interface with common system bus structures.
The MSM2708 AS is fabricated with the N-channel silicon gate FAMOS technology and is available in a 24-pin dual
in-line package.

FEATURES
• Data Inputs and Outputs TTL
Compatible during both Read and
Program Modes

• Three-State Outputs - OR-Tie
Capability

• Static - No Clocks Required

Max. Power

Max. Access

Organization

800mW

450 ns

1K x 8

MSM 2708 AS

FUNCTIONAL BLOCK DIAGRAM

DATA OUTPUT

PIN CONFIGURATION
CS/WE

AoA,_
A,_
A,_

o

ADDRE$j
INPUTS
VDD

CHIP SELECT
LOGIC

OUTPUT BUFFERS

Y
DECODER

Y GATING

X
DECODER

64 x 128
ROM ARRAY

OIl

~;==.

~~==

A,A,-

PROGRAM

Address Inputs
Data Outputs/Inputs
CS/WE

Chip Select/Write
Enable Input

157

.EPROM . MSM2708AS.-----------------------------------PIN CONNECTION DURING READ OR PROGRAM
PIN Number
Data I/O
9"" 11,
13 '" 17

Mode

I

Address
Inputs
1 ..... 8,
22,23

VSS
12

Program
18

VOD
19

eS/WE
20

Vss
21

Vee
24

Read

DOUT

AIN

GND

GNO

+12

VIL

-5

+5

Deselect

High Impedance

Don't Care

GND

GNO

+12

VIH

-5

+5

Program

DIN

AIN

GND

Pulsed
26V

+12

VIHW

-5

+5

ABSOLUTE MAXIMUM RATINGS*
•
•
•
•
•
•
•
•

Temperature Under Sias ..
Storage Temperature . . . .
VDD with Respect to VSS
Vee and VSS with Respect to VSS . ..
. .......... .
All Input or Output Voltages with Respect to VSS during Read.
eSIWE Input with Respect to VSS during Programming .
Program Input with Respect to VSS .
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . .

*

_25°C to +85°e
-65°C to +125°e
+20V to -0.3V
+15V to -0.3V
+15V to -0.3V
+20V to -0.3V
+35V to -0.3V
1.5W

Stresses above those listed under "Absolute Maximum Rating" may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

DC AND AC OPERATING CONDITIONS DURING READ
Temperature Range

158

Vee Power Supply

5V ± 5%

VOD Power Supply

12V ± 5%

Vss Power Supply

-5V ± 5%

- - - - - - - - - - - - - - - - - - . EPROM· MSM2708AS.
READ OPERATION
DC AND OPERATING CHARACTERISTICS
Parameter

Symbol

Address and Chip Select
Input Leakage Current

III

Output Leakage Current

ILO

Typ.!2)

Min.

Max.

Units

1

10

J.I.A

V'N=5.25V or V'N=V'L

1

10

J.I.A

VOUT=5.5V, CS IWE=5V
Worst Case Supply
Currents
All Il1puts High:

VOO Supply Current

100(3)

50

S5

mA

V CC Supply Current

ICC(3)

S

10

mA

VBB Supply Current

IBB(3)

30

45

mA

Input Low Voltage

V,L

Input High Voltage

V,H

Output Low Voltage

VOL

Test Conditions

VSS

0.S5

V

3.0

VCC+ 1

V

0.45

V

CSIWE=5V; T a=O° C

IOL=1.SmA

Output High Voltage

VOH1

3.7

V

IOH=-100 A

Output High Voltage

VOH2

2.4

V

IOH=-lmA

Power Oissipation

Po

mW

800

Ta=70°C

Note: 1. VBB must be applied prior to VCC and VOO.VBB must also be the last power supply switched off.
2. Typical values are for T a = 25° C and nominal supply voltages.
3. The total power dissipation is not calculated by summing the various currents (100, 'CC, and 'BB)
multiplied by their respective voltages since current paths exist between the various power supplies and
VSS. The 100, ICC and IBB currents should be used to determine power supply capacity only.

RANGE OF SUPPLY CURRENTS
VS. TEMPERATURE

ACCESS TIME VS. TEMPERATURE

500

80
ALL POSSIBLE OPERATING
CONOITIONS:
VCC= 5.25V
VOO = 12.SV
VBB = -5.25VEo::: HIGH

W

-;c

i

en

IZ

~

w

a:
a: 40
::>
u

100

>-

...J

a..
a..
::> 20
en

u
u

«
I-

~

300

200

IBB

-

----

~

~

100

......
0

I

400

CSiw

SO

I

1TTL LOAO + 100pF

0

• ••••••• JICC
20

40

SO

80

100

o-20

o

20

40

SO

80

159

• EPROM· M S M 2 7 0 8 A S . - - - - - - - - - - - - - - - - - A.C. CHARACTERISTICS
Parameter

Symbol

Min.

Address to Output Delay

tACC

Chip Select to Output Delay

tco

Chip Deselect to Output Float

tDF

0

Address to Output Hold

tOH

0

Typ.

Max.

Units

350

450

ns

120

ns

120

ns

60

CAPACITANCE(1 )
(Ta = 25°C, f = 1 MHz)
Parameter

Symbol

Typ.

Max.

Unit.

Conditions

Input Capacitance

CIN

4

6

pF

VIN = OV

Output Capacitance

COUT

8

12

pF

VOUT = OV

Note: 1. This parameter is periodically sampled and is not 100% tested.

AC TEST CONDITIONS:
Output Load:
Input Rise and
Fall Times:

1 TTL gate and CL = 100 pF
<20 ns

Timing Measurement
Reference Levels:
0.8V and 2.8V for inputs;
0.8V and 2.4V for outputs.
Input Pulse Levels: 0.65V to 2.0V

WAVEFORMS

X,.-------X
I

ADDRESS

_ _ _- J

CS/WE

i

I

:

i---tOH~

I
::
I

I.

DATA
OUT

160

\

'---------------

}_--~I------

/i!

tDF :

I

I

I~------------------J,

f-----tCO--j
tACC
"I

j:tt:::I?:&!N~T:T~y,~~m::::::::::::jP----Vppo>----VssO--'-

~----------~·I~_________ u~t-b-u-ff-e-r--------~1
O_u_tP
__

f

Memory matri x 65536 bi ts
(8192 x 8)
CE 0 - - - - - ------

PGM 0-- - - - - "

OE 0-----------+1

CE
circuit

PGM
circuit

Address decoder

OE
circuit

Address buffer

167

CROSS
REFERENCE
LIST

-...J

(Note)

o

Type No.
Package Material
L -_ _ _ _ _

1. DYNAMIC RAM
Struc- Total Or- INurngani- Iber of
ture
Bit
zation Pin

Oki

Hitachi

Intel

Texas

Mostek

2117-5
3001p·G
HM4716A-4

TMS4116-25

MK4116-4

2501p·G

250 I P.G.C

250 I P.G

MSM3716-3

HM4716A-3

2117-3

TMS4116-20

MK4116-3

16k 16384
x 1

16

200 t

C

200 t P.G

2001p·G

MSM3716-2

HM4716A-2

2117-2

150

I

C

150

I P.G

I P.G

' 150 Ip·G

NEC

MCM4116-30

IlPD416

300

2117-4

250

Motorola

200

I P.G.C

TMS4116-15
150

I P.G.C

200

I

P.G

MK4116-2
150

I

P.G

I G.C

MCM4116-25
250

J G.C

MCM4116-20
200

I

G.C

MCM4116-15
150

I G.C

300

J P.G

IlPD416-2
200

I

P.G

IlPD416-3
150

Toshiba

Mitsubishi

Fujitsu

TMM416-4

M5K4116-4

MB8116N

I P.G

IlPD416-1
250

Access Time (ns) max.

I P.G

250

I

G

250

I P.G

TMM416-3

M5K4116-3

I

200 1 P.G

200

G

TMM416-2
150

I

G

M5K4116-2
150

I P.G

HM4716A-1
120

250

I

C

MB8116E
200

I

C

MB8116H
150

I

C

MB8216E

I P.G

120

I

C

HM4816
100

I

C

MSM3764-12
64k

65536
x 1

120
16

j

J

C

MSM3764-20
200

I

120

C

MSM3764-15
150

MK4164-12

C

HM4864-2

2164-15

TMS4164-15

1

1501 C

150 1

150

C

HM4864-3
200

I

C

C

1 C

MK4164-15
150

1

C

MK4164-20
200.1

C

MCM6664-15
150

I

C

MCM6664-20
200

1

C

",PD4164-3
150

J

C

IlPD4164-2
200

I

C

TMM4164C-3 M5K4164-15

150

1

C

150

1

C

TMM4164C-4 M5K4164-20
150

I

C

200

I

C

MB8264-15
150

l

C

MB8264-20
200

I

C

2. STATIC RAM
NumStruc- Total Orture
Bit gani- ber of
Pin
~ation

Hitachi

Oki
MSM2125H-2

1k

1024
x 1

16

I

25

I

Intel

Texas

I

20

200

I

P

45
HM472114A
-1

TMS4045-15

150

150

I

P.G

HM472114A
~114/L-2
-2
200

I

P

2001p·G

200

1024
x4

18

300

l

P

I

P.G.C

MSM2114L
450

I

P

I

P.G

HM472114-4
450

I P.G

l

C

l

70

I

C

I

450 P.G

150
MK4114-3
200

I P.C

MK4114-4
250

I

P.C

300

I P.C

TMS40/
L45-45
450

MCM21/
L14-20
200

I

P.C

MCM21/
L14-25
250

I

P.C

MCM21/
L 14-30
300

I

P.C

MCM21/
L 14-30

I P.G.C

450

MB8114H

I

P.C

I P.G

#-,PD2114L-3
200

I

P.G

150
TMM314A/
L1

200

1

P

2048
x8

250

1

MSM2128-12
120

I

P

I P.G

MB8114EL
200

I P.C

P.G
M5L2114L
-3

#-,PD2114 L-1
300

I P.G

#-,PD2114
450

I P.G

300
TMM314A/L
450

I

P

I P.G

MB8114NL
300

I

P.C

•

M5L2114L
450

I P.G

(")
jJ

o

IG

55
(HM6148)
70

I

P

IG

2148
70

IG

jJ

MCH2148
55

I

m

"

C

m
jJ

MK2148
70

MB8168

m
2
(")
m

I

r-

I
100

24

200

I P.C

#-,PD2114L-2

TMM2016P-1
16k

M5L2114L
-2

(I)
(I)

2148-3

C

MSM2148-70

I

2114/L

C
#-,PD2114L-5

MK4114-5

300 P.G

45

MSM2148-55
55

Fujitsu

2148H

MSM2148-45
45

I P.G.C

HM472114-3 ~114/L-3
300

I

I P.G.C

TMS40/
L45-20

250

4k

Mitsubishi

MC2125

TMS40/
L45-25

MSM2114L-3

Toshiba

IG

C

MSM2114L-2

NEC

Motorola

2125H-1

C

MSM2125H-3
35

NMOS

Mostek

I

P

100

ei)
-i

•

S:~~~t_IT~;~1 r9~~;- ~e~~_;__

--

-

atlon

.

Oki

Pm

---c-----

Hitachi

--------------

MSM2128-15
I

'

,

150

I
I

I

i

l

~

Texas

.1_nt._e_ljl

Mostek

NEC

Motorola

TMM2016P

I

I

P

__

_ _ __

__

___

150 !

--c-----------

P

58725-15
150

----t-------~

I

I

i

200

I

MSM2128-1

,

I

I

I 200
I

P

~O

C

I

200

I
I ___ _
300

I

1

JJ

m
m
JJ
m
."

I

P.C

200

I

---i---+I~---+---

--

m

--

r-

en
-t

----+-----------+-:----+-----+------1
MB8404E

i

250

I

P

I

H_M~4~3_1_5

p __+-___

I

~------~-------~M-C--M~1_46_5_0_4~
i
J
450

P.C

______

~1 C~5_50_4 ~
i
r;o I
_T
__
I 450!

P__

________

~

________

TC5504-1

I

P

I

TC5504-2
800

I

P

MSM5115-2
200

I

P
I

1024
x4

18

MB8414E
250

MSM5115-3
300

I

P

en

!

P --

-+~-I
__

4K

150

JJ

Z

I

!L_ _

MB8168

o
en

(")

(")

~04-3

18

P.C

•

TMS4016

~------ti--t------+----

P

I

I

Fujitsu

58725
I

-r---t-IM-S-IV-15'-1-04--2--+~~--r
4096
x1

Mitsubishi

MSM2128-20

I

I

COMS

Toshiba

I

P

~

•

Struc- Total Or- Numgani- ber of
ture
Bit
7ation Pin

Hitachi

Oki

Intel

Texas

Mostek

NEC

Motorola

Toshiba

Mitsubishi

Fujitsu

TC5047-1
4k

1024
x4

550

18

MSM5128-12
120

I

P

MSM5128-15
2048
x8

P

TC5047-2
800

16k

I

24

150

1P

MSM5128-20
200

I

P

HM6116/L-2
120

1

P

HM6116/L-3
150

I

P

HM6116/L-4
200

I

P

I

P

J,tPD446-2
120

I

P

J,tPD446-1
150

I

P

J,tPD446
200

I

P
TC5516

COMS
250
MSM5114-2
200

I

I

P

J,tPD444-3

P

200

I

P

•

J,tPD444-2
250
MSM5114-3
4k

1024
x4

18

300

I

P

MSM5114
450

I

P

HM4334-3
300

I

P

HM4334-4
450

I

P

I

(")

P

JJ

o(I)

J,tPD444-1
300

I

J,tPD444
450

I

(I)

P

P

JJ

TC5514
450

I

P

TC5514-1
650

I

P

TC5515-2
800

I

P

M58981-45
450

I

G

m
"T1
m
JJ

m
:2

(")

m

r-

en
-I

•

•

3. MASK ROM

C')

Struc- Total Or- Numture
Bit gani- ber of
zation Pin

16k

2048
x8

24

Oki

Hitachi

Intel

MSM2916

HN462316E

2316E

I

I

450

P

450

P

Texas

I

450 P.G

Mostek

Motorola

MK34000-3

MCM68A
316A

350

I

P.C

MK31 000-3
550

32k

4096
x8

MSM2932

2332A

I

4501 P.G

450
24

P
HN46332
350

I

T P.G

MK32000-5
300

I P.G

MK3600(}5
300
24
64k

8192
x8

I

,uPD2316
450

P

I P.G

350

450r P.G
MSM38128
450

I

P.C

I

P.G

450

I

P

TMM333
450

I

P

I

250

650

r

r

P

P.C

M58334

P.C

650
,uPD2364
450

I

P.G

,uPD23128
250

I

C

TMM2364
250

I

P

I

::D

m

."

m

::D

m

Z

m

P.G

M58333
650

o

C')

I P.C

I

I

P

M58731

MCM68A
364

350
2364A

28

P.G

TMM331A

:D

en
en
450

MCM68A
332

28

128k

I

I

Fujitsu

MB8316

P

MCM68A
364

HN48364
350

450

450

450

NMOS

I P.C

Mitsubishi

TMM334

I P.C

MCM68A
316A
350

Toshiba

,uPD2332

TMS4732

P

I P.C

350

NEC

P

MB8332
200

T

P

ren

-I

•

4.

EPROM

Or- NumStruc- Total
ture
Bit gani- ber of
zation Pin

Oki

Hitachi

Intel

Texas

2716-1
350

IC

16k

2048
x8

24

450ns
cerdip

HN462716
450

I

C

MK2716-6

MCM27A

I

C

350

I

NEC

Toshiba

Mitsubishi

Fujitsu

MB8.516

C

MK2716-7

IC

400

2716
450

Motorola

350

2716-2
390

Mostek

IC

I

C

MK2716-8

MCM2716

,uPD2716

TMM323

M5L2716

I

I

I

I

I

450

C

450

C

450

C

450

C

450

C

450

I

C

M5L2716
-65
650

1C

TMS2516
450

NMOS

HN462732
450 1
32k

4096
x8

C

I

G.C

2732

M5L2732
450

4501 C

450ns
cerdip

I

C

M51.2732-6

24
550
HN462532
450

I

C

TMS2532
450

I

G.C

I

C

MB8532
450

I

C

•::c
n

oen

en
::c
m

'T1

m

:xl

m
2
n
m

r-

en
-I

•

APPLICATIONS

64K BIT DYNAMIC RAM APPLICATION NOTES
Reliability
n
R = (rH) + nC l

1. MEMORY SYSTEM RELIABILITY
1.1

Reliability Determination Factors

The memory system reliability depends upon the four
factors shown in the left column of the following table.
These factors are determined as shown in the right
column of this table.
Memory system
reliability factor

Factor determination

System-required
reliability

Determined by the user-required
specifications (MTBF).

Unit capacity

Q:

Parts reliability

Logic element
Hard error
Memory element---.L.soft error

(2)

m

(2)

Probability of all bits being correct

®

Probability of error occurrence for only one
bit

-lit-----'--:---'------11

R = (rn) == e

k blocks

I

1.4 Reliability Calculation Method

Hard error
Soft error

178

rH = e-AH·t (AH: Hard error rate)
rS = e-AS·t (AS: Soft error rate)

I

n bits

1.5 Reliability Calculation Result Example
(1 )

Comparison of 64k. byte, 128k byte, and 256k
byte configurations (without ECC)

CD 64kbyte
Element

AH
(Fit)

AS
(Fit)

MTBF
(years)

64k

100

1000

11.5

200

10.6

100

15.9

50

21.1

200

12.7

100

21.1

50

31.7

100

* .single~rror ~orrect - Qouble ~rror Qetect
(one bit error correction and two bit error detection)

MTBF for a hard error and a soft error
(1) Memory element reliability

®

ill

CD

Only parity error detection without bit correction
Find a value for t which satisfies the following
expressi~n :

I nput data pattern dependability
Refresh margin
Temperature cycle dependability
I nsufficient power margin
I nsufficient system noise margin
particle failure

Parity........ Error detection only (makes no
contribution to the MTBF enhancement)
ECC ......... The SEC-DED* is used in general

Memory unit reliability
Assume a memory unit whose size is n bits in bit
width and k blocks in address capacity. The
memory element reliability is expressed as
follows:
r = e-At (A: error rate)
One bit correcti()n
Find a value for t which satisfies the following
expression:
R = {()
..!.-.-n + ~n-1 (1 -r) }k_
=e ~

(II) Soft error
A soft error is a transient error that does not repeat. The
following are the six causes for soft errors:

(1)

Probability of one bit hard error followed
by no hard or soft error
l

(I ) Hard error
A hard error is a permanent error which occurs each
time a certain address is accessed.

The following are the two typical means for the enhancement of system reliability.

~

Find a value for t when the value of R is e- .
The following calculations are based on the assumption
that there is a low probability of two bit soft error
occurrence.

1.2 Hard Error and Soft Error

1.3 Measures for Reliability Enhancement

n-1)
·(1 - rH

Probability of no hard error

~

[MB] = [word depth] x
[bit count]

Items (1) through (5) are largely influenced by the
system design. For item (6), it is required to consider
whether a remedy such as ECC should be taken or not
to satisfy the system-required reliability based on the
parts reliability (pertaining to hard errors and soft
errors). See 1.3 and 1.4 for details.

(rH 'rs)

(D

(j)

Cost

(1)
(2)
(3)
(4)
(5)
(6)

•

16k

50

- - - - - - - - - . 6 4 K BIT DYNAMIC RAM APPLICATION NOTES.

® 128kbyte

® 256kbyte
MTBF
(years)

Element

AH
(Fit)

AS
(Fit)

64k

100

1000

5.8

200

5.3

100

7.9

50

10.6

100

16k

Element

AH
(Fit)

AS
(Fit)

MTBF
(years)

64k

100

1000.

2.9

200

2.6

100

4.0

50

5.3

200

3.2

100

5.3

50

7.9

100

16k

50

200

6.3

100

10.6

50

15.9

50

Notes:

1. The bit width is 9 bits for each case.
2. 1 bit is used for parity error detection.

Comparison of 1M byte configurations (with ECC)

(2)

Reliability (years)
Element

AH (Fit)

AS (Fit)
Bit width: 22 bits

Bit width: 39 bits

100
(100%)

1000

8.2 (0.76)

7.9 (0.79)

100
(50%50%)

1000

13.9 (0.76)

14.5 (0.79)

100
(100%)

100

8.3 (1.05)

6.8 (1.08)

100
(50% 50%)

100

13.0 (1.05)

10.7 (1.08)

64k

16k

Notes:

1. When the bit width is 22 bits, six bits are
used for the ECC.
2. When the bit width is 39 bits, seven bits are
used for the ECC.
3. Values in parentheses are the reliabilities in
the case of parity error detection without
ECC.

4. The (50%, 50%) in the AH column means
that 50% of the hard error rate AH is handled as the total bit hard error rate and the
remaining 50% is handled as the one bit
hard error rate (which reflects the hard
error mode analysis result confirmed so far).

iII
179

• 64K BIT DYNAMIC RAM APPLICATION NOTES ••- - - - - - - - -

2. DECOUPLING CAPACITORS
The dynamic MOS RAM is featured by the great
power current at the active time in comparison
to that at the standby time.
For example, the rated value (lcc1) of the mean
power current of the MSM3764 is 45mA, while
the standby current (lcc2) of the MSM3764-12
(120ns version) is 5mA. The former is approximately
10 times greater than the latter. The peak current
of the MSM3764 approaches 90mA in the worst case.
It is approximately 20 times as great as the standby
current Icc2.
Therefore, the power circuit must be designed so
as to prevent the above current variation from
causing an erroneous operation of the memory.
A by-pass capacitor must be inserted for this
purpose. There are two types of by-pass capacitors: high frequency capacitor and low frequency
capacitor.
2.1

High Frequency Capacitor

In the Icc current waveform, the peak current
rises at a high speed such as 10ns, and a high
by the following
frequency noise represented
expression is caused to occur by the L component of the current applied to the capacitor:
6i
6V=L6t

To reduce the fluctuation 6V, the value of L
must be reduced.
For this purpose, the capacitor must be placed as
close as possible to the power pin of the IC. Further, sufficient capacity for supplying the peak
current is required. The standard capacity for a
double sided circuit board (two layer circuit
board) is 0.05 """ 0.1~F or more. The capacity
may be less than this value for a multi layer
circuit board since the L component is less than
the former.
When designing a board, mount one capacitor
with excellent high frequency characteristics for
every two or three MOS IC memory chips, near
the power pins of these IC chips.
2.2 Low Frequency Capacitor

OJ

A low frequency capacitor is required for suppressing the power fluctuation due to a sudden
current variation (for example, current variation
caused by a status change from the standby
status to the continuous access status or concurrent refreshment of the entire board) in a board
unit. The power fluctuation in this case is a slow
variation of several handred ns.
For this reason, the low frequency capacitor
must have a capacity larger than the high frequency capacitor.
Though the capacity requirement depends upon
the number of memories which operate simultaneously (bit width), 50~F is enough for a 16 """

180

32 bit system in a practical use.
As an example of capacitor which satisfies the
requirements in both 2.1 and 2.2 above, a
small-sized
tantalum
capacitor
with
excellent
high frequency characteristics is shown in the
following table. It is desirable to mount a low
frequency capacitor near the power input pin in
order to suppress the fluctuation of power supplied from outside, even if this capacitor is
mounted.
Model

Manufacturer
Oki Ceramic Co.

Capacity (~F)

Model CA
0.1 """ 20l'F
tantalum capacitor

The
frequency
characteristics
of
the
above
capacitor and the power bus bar are illustrated
in attached figure 1.

3. PRINTED CIRCUIT BOARD
3.1

Number of Layers

Considering the measures against power noise which was
described in 2. above and the routing to be described in
3.2, two layers are enough in principle.
3.2 Routing
An example of routing on a two-layer circuit board is
shown in attached drawing 2. I n designing the routing,
note the following four points:
The MOS drive line based on the TTL must be as
short as possible to prevent ringing (reflection) and
reduce crosstalk.
(I t) Considerations are required to lower the impedance of the power line (including the ground). (For
example, make a solid or grid-formed power line
pattern. It is desirable that the power line pattern
has width of at least 1.27mm.)
(III) If a signal line is to be branched for multi drive,
the line must be branched at the driving end.
(See the following figure.)
(I V) The memory matrix must be designed in an integrated form, and peripheral drivers must be placed
near the memory matrix.
(I)

Memory element

- - - - - - - - - - . 6 4 K BIT DYNAMIC RAM APPLICATION NOTES.

4. PERIPHERAL CONTROL CIRCUIT
The three types of dynamic RAM control ICs shown in
the fol/owing table are available at present.

Model

Manufacturer

Functions

Intel

i-3242

Motorola

MC-3242

o Seven-bit address mUltiplex function (for 16K bit
dynamic RAM)
o Seven-bit refresh address count function
o Direct driving of memory elements (for approx. 20 elements.
250 pF/25 ns 15 pF/9 ns)
a Application to a 64K bit dynamic RAM, example
(see the following figure)

Texas Instruments
(T. I)

74LS601
603

o Refresh timer using an RC multivibrator
o Timing generation
o Refresh address (7-bit address)

Advanced Micro
Device (AM D)

Am2964A

o Address latch/multiplex function (16-bit address)
o Refresh address counter
o RAS decoder (2 ,.., 4)

REF

ENABLE

Ao

Ao
3242
Au

A,

MSM3764

A,
Au

A1S------------~

m

ROW ENABLE

181

• 64K BIT DYNAMIC RAM APPLICATION NOTES.

5. NOTES ON MOUNTING 1 MB
MEMORY ON A BOARD

The advent of a 64K bit dynamic RAM such as the
MSM3764 has made it extremely easy to mount 1 MB

Point to be noted
Mounting of
memory
elements

memory on a board from the viewpoint of mounting
space. In this case, however, note the following points
since the number of memory elements mounted is so
large as 128"" 176 (when redundant bits are provided).

Consideration
Memory elements may be integrated or
divided.
(Design the memory array(s) to make
the drive lines shortest.)

Practical example

loriverl

IIIIIIII

ffiIE

Memory array
Memory
element
driving method

Measures
against noise

Timing design

Thermal deSign

m
182

Take care about the delay time and
undershoot noise of the drive element.
(If the condition VILmin = -lV recommended for the MOS dynamic RAM
operation is satisfied, the memory elements
will display the full reliability.)

II
LJ

Driver

Memory
Iarray

ffiIE

Memory array

Drive element

~
Element

Delay
time

(mA)
NOise
IOL

7404

Medium
speed

16

0

74S04

High
speed

20

X

o Two layers are enough for a board.
(Pay attention to the power line pattern.)
o High frequency noise

Mount a 0.1 "" 1 #LF capacitor for every two
memory elements.

o Low frequency noise

Mount a tantalum capacitor etc. of 50 #LF
or more near the power input pin of the
memory package.

o Prevent skew between each timing in order
to enhance the system access speed.

Use ICs of the same tipe for racing timing
(for example, RAS or CAS).

o Make a sufficient margin in timing design.

Skew and mounting delay

Thermal design under the worst condition
is required.

Operation at a case temperature of 70°C
must be guaranteed.

- - - - - - - - - , . 6 4 K BIT DYNAMIC RAM APPLICATION NOTES.
6. MEMORY DRIVER
There are problems in driving MOS ICs by a TTL driver:
increase of driver delay time due to capacitive load and
ringing waveform at the falling edge.
An example of the increase of delay time due to capacitive load is shown in the following figure.
The number of load memory elements must be taken
into consideration when designing the timing.

• If the number of load memory elements is 20 - 40
(150 - 300pF) on a two layer board, an undershoot
of -2 to -3V (peak voltage) occurs. Therefore, measures against ringing must be taken as described in the
following,
• Measures against ringing
(1)
(2)

In case of LS
PROPAGATION DELAY TIMES
vs
LOAD CAPACITANCE
20

o
I

VCC= 5V
18 RL = 25n
= 25°C
16 Ta

/"

VV

E 14

V

j::

>- 12

~

V
.....

V ~V
-.. I--""

co

10

. .V
~

(3)

V

........... V
(4)

g 8

'';:;

~

6

~

4

0.

o

For memory arrays, however, termination with
pull up or bleeder resistance is not effective.
I nstead, series resistance (damping resistance) is
su itable for memory arrays.
Make the signal lines as short as possible. MUltilayer board design is effective in reducing the
undershoot (as the signal line impedance is
lowered).
The optimul value of series resistance differs
depending upon the speed, pattern status, and
driver. Experiences will help much in determining
the optimul series resistance.
As a standard, a resistance of 10 - 1000n is
suitable.
Note that the speed will be lowered if the resistance is so great. An example is shown in attached
drawing 3.

2

o

No consideration is required for the rising edge
since there is a margin.
Since a ringing may be considered as a reflection
due to mismatching between the driver output
impedance and signal line impedance, it can be
prevented by taking the line matching (termination).

1 0 20 30 40 50 60 70 80 90 100
CL - Load Capacitance - pF

In case of S
'S112, 'S113, 'S114
AVERAGE PROPAGATION DELAY TIME
CLOCK TO OUTPUT
vs
LOAD CAPACITANCE
Q)

E 16

j::

r;

q;

o

c:

VCC = 3V
14 RL = 280n
Ta = 25°C
12

o

'';:;

~

co

10

.,...........

0.

o

,t

8

Q)

Cl

~

6

«>

4

Q)

/'

V

~

~

v

.....

.............

iii

I
...J

:I:

2

+N

o

~

:I:

o

25

50

75 100 125 150 175 200

...J

....a..

CL - Load Capacitance - pF

183

• 64K BIT DYNAMIC RAM APPLICATION NOTES . - - - - - - - - - - " . . , 7. MEMORY COMPARISON
STANDARD
In general, power, speed, and usability are required for
memory elements. At present, 64K bit dynamic RAMs
can be supplied by a lot of manufacturers, and these
elements have almost unified specifications.

Point
to be noted
Power

Timing
margin

In designing a circuit board to achieve stable system
operation, however, considerations must be given to the
specification values and margins against the specification
values, pertaining to the points shown in the following
table. Factors that will affect the stable system operation are power, temperature, aging, clock skew, uneven
operation of peripheral ICs, and so forth.

Actual item to be considered

Reason

a Currents (Icc1, Icc3, and Icc4) at the operating
time and current (Icc2) at the standby time

The power system must be noted.
(example: with battery backup)

a Current waveform (especially the peak current
value)

The noise margin must be strict for
memories with large peak current.

a Address setup (tASR, tAscl and hold (tRAH,
tCAH) timing

In system designing, these timing pulses
are directly related to the access time.

a Data setup (tDS) timing and write pulse width

These timing pulses are related to the
cycle time in writing.

(twp)

Voltage, temperature, and dependability of each
timing (especially the tREF and tRAcl

The temperature inclination must be
little for the timing pulses tREFand
tRAC·

Voltage
margin

It is impossible to achieve the ideal voltage status
when used within a system.

A sufficient voltage margin must be
provided under consideration of various
factors wh ich will affect the system
operation stability.

Attached drawing 1
Frequency characteristics of capacitor and Q/PAC

50

- - - Model CB tantalum 1.01J.F
capacitor (manufactured
by the Oki Seramic)

a/PAC sectional view

PinlClin2

(n)

10

Model CB
a-PAC
(1.0IJ.F)
(between pins
Y1and2)

Z

a-PAC
(between pins
2 and 3)
500PF
600PF

m

0.5

0.05

0.5

5

50
(MHZ)

184

100

- - - - - - - - - - - . 6 4 K BIT DYNAMIC RAM APPLICATION NOTES.
Attached drawing 2
Two layer board circu it pattern example

r

i .-

I

I .

-~~

l~'-

~ ~

I .-

1

(II

185

.64K BIT DYNAMIC RAM APPLICATION NOTES . - - - - - - - Attached drawing 3
Input waveform example

m
186

Horizontal:
( Vertical:

50 ns/div )
1 volt/div

CMOS RAM BATTERY BACK-UP
A practical example of formation of nonvolatile data by CMOS static RAM battery
back-up is outlined below.
1. System power and battery switching
circuit
The most simplest RAM power supply (CMOS Vcc) is
outlined in Fig. 1. In this case, the CMOS Vcc for
normal operation is kept at a voltage O.7V below the
system voltage by the voltage drop across a diode
(forward direction).

System
battery

Battery

Fig. 1

Note: CS floating capability
Power down possible irrespective of other input
levels when memory has not been selected (i.e.
when CS = HI.
Consequently, if the TTL Vcc level is greater than the
CMOS RAM supply Voltage, and the RAM driver is at
the TTL Vcc level, the CMOS RAM input voltage will
exceed CMOS Vcc + O.3V (a situation which must be
avoided). Therefore, in order to reduce the voltage
difference between CMOS Vcc and TTL Vcc with the
battery voltage set to at least 4.5V or 4.75V (due to
the RAM operating supply voltage range), the 02 diode
may be added to abtain a system voltage level at least
O.7V above 4.5 ~ 4.75V (which will keep CMOS Vcc
and TTL Vcc within the respective CMOS and TTL
operating supply voltage ranges).
To cope with (1) and (3), a CMOS driver which will also
operate at a low voltage Vcc during data hold may be
employed, or else, the open collector and open drain
buffer may be pulled up to CMOS Vcc in order to drive
the RAM.
A control circuit for coping with (2) when an abnormal
system power supply is detected is also required.

2. Switching Circuit Modifications

Fig. 2 is an example of use of a chargeable Ni-Ca battery
as the back-up battery. While the system power is being
employed, the Ni-Ca battery is gradually charged up via
Rc. As in Fig. 1, the diode voltage drop also poses a
problem in this circuit.

Modification of the diode switching circuit can employ
PNP transistors. Voltage drops by PNP transistor V CE
are smaller by about O.2V, and this can lead to the
generation of a system "power fail" signal.

02 (optional)
System
battery

i- -~ - -I

...

-~-"'1r~-----'-~""'· TTL Vcc

'----1:.....-~~-.~
01

CMOS Vcc

>

~Rc

System ....+-___---2--..N36/"3-8----1~-....
battery
-3.9V

-=- Ni-Ca battery
J:

_f

Rc

1N914

1K2N222~

TTL
Vcc

Option

-

1

Fig. 2
The conditions for formation of non-volatile data (data
retention) by battery back-up are listed below.
(1) The input signal H level must not exceed Vcc +
O.3V when the CMOS RAM Vcc power voltage is
dropped.
(2) CE (or CS) must maintain CMOS Vcc "H" level.
(3) In order to minimize power consumption, WE,
AD, DIN (or lID) must be se! to GND level or to
the same "H" level as CMOS Vcc. (This is not
necessary, however, for CMOS RAMs with chip
select floating capability).

Fig.3
Fig. 3 outlines a switching circuit employing a PNP
transistor. The Rc used when a chargeable battery is
employed is replaced by a diode when a non-chargeable
battery is used. In this case, switching occurs at the
zener diode voltage, so "power fail" must be detected
by another circuit, and CE set to CMOS Vcc "high"
level.

187

rn

• CMOS RAM BATTERY BACK-UP ••- - - - - - - - - - - - - Figs. 4 and S are examples of circuits capable of generating a POWER FAIL output signal. In these circuits, the
C2 capacitance must be rather large, the important

point being the need for a smooth gradual change in
CMOS Vcc when the system power is cut. See next page
for further details.

TTL Vcc
System
battery

CMOS Vcc

01
02
R3
Rs
01

POWER
FAIL

: 2N2907 or 2SA49S
: 2N2222 or 2SC372
:1K
R2
:100
: SOO R4
: 47K
: 3.6V Rc
: 2.00
Ni-Cad : 3.6V
(70mAH)

Fig. 4

. . - - - - - - - . POWER FAIL signal

. - - - - - - . . . - - - - - . - - + - - - - - - -.... TTL Vcc or system Vcc
System ...._-+-_,
battery

.r-:---4--.......---4--+-_----.--... CMOS Vee

-=-

Ni-Cad
lSOOmAH

Fig. S

SV
System battery 0

1

r-~~-----'

i

4.SV/oetermined by CT
.,......_ _ _ _ _ _ Example.
3V 2: 2.0V

-=- Battery

m

3V

CE? 3V
'+-_ _ _ _ _ _ CMOS Vce

CT

= C2 + (another decoupling capacitor)

-0.1 -0.2V

GNO

Fig. 6

188

2: 1.SV

- - - - - - - - - - - - - - - - . CMOS RAM BATTERY BACK-UP.
is cut until it reaches the power voltage for data retention (practically equivalent to the battery Voltage, or
else reduced by the diode voltage drop). And although
CE traces the slope of CMOS Vcc reduction at this time,
a smooth change in CE is also a necessary condition for
actual circuits.
(4) When switching to retention mode, or from retention mode to operation mode, CE must exhibit a
smooth change. If noise is generated in CE in this case,
the data will be subject to rewriting.

3. Data Retention Mode
The RAM driver (peripheral circuit) is determined
according to conditions (1) and (3) required for data
retention. In Oki Electric CMOS RAMs, the power
voltage during data retention is kept at a minimum of
2.0V. The CE (or CS) voltage at this time has to be kept
at about Vcc -0.2V. And as was mentioned earlier, the
CMOS Vcc must drop smoothly when the system power

J-

Cmos Vcc SV ±10%
CE input VTH =
Vcc - 2.0V
(MIN)

,

(MGANX~

Must be free of noise
(RAMP waveform)

~,==========~:~======~~2.0V (MIN)

I

'F
J +i---.r' ______
I,

Other inputs VI L =
O.8V

Data retention mode

_____
t = 0

Vcc - 0.2V

I~ _ _ _ _ _ O.SV (MAX)

May be longer

Fig. 7
(S) When switching to operation mode, commence
operation after elapse of tRC (read cycle time) following

Data
retention
mode

CMOS Vcc

CE

----i

Operation
mode
.J------+------.:...:....:;.- CMOS Vcc

I
,

,

Vcc reaching the operating power voltage range.

'

,- - - - - - --VIH
2.SV = 1/2Vcc

I

j I

= SV ± 10%

= Vcc -

2.0V
(MIN)

I

I"

CE VIL = 0.8V (MAX)
GND-----~---- ~~-----~-----GND
May be longer

ill

tRC min.

Fig. 8

189

m

• CMOS RAM BATTERY BACK-UP . - - - - - - - - - - - - - 4.

Interfacing

A) TTL Interface
In the case of CMOS RAM drive by TTL, use an opencollector type TTL according to conditions (1) and (3) .

When the system power line (j.e. TTL Vec) is cut, the
open-collector TTL 02 in Fig. 9 is turned off, followed
by 01 also being turned off, resulting in the CMOS
RAM input being pulled-up to CMOS Vcc.

CMOS Vcc

TTL Vcc

----,

Switching CircUit-- System power line
or TTL Vcc

1K

I

-r

I

r-~rl------~--~IN

I

CMOS
RAM

I
I
________ ..J

I

l

Fig. 9
When the power line voltage in LS type TTL is dropped
to ground, the output is also dropped to ground,
thereby making the pull-up resistors for address line
buffers etc no longer necessary. In this case, however, it
will not be possible to employ this as a control line
buffer which must be switched to "high" during CE (or
CS) data retention.
(6) In order to minimize the consumption current
during data retention, all inputs except CE (or CS, this
being designated as either "high" or "Iow") must be

---

f1 ~

r-:-l

1

......

I

I

,

'r--.
......

Vcc
CMOS
RAM

,
I

CMOS Interface
I n systems where the CMOS RAM is driven by CMOS
buffer, operation must be at the data retention power
voltage, and the corresponding output voltage must
satisfy the requirements indicated in Figs. 7 and 8.
B)

1

I

1':-

maintained at either GND or CMOS Vcc. (This does
not apply, however, for CMOS RAMs equipped with CS
floating function).

I

I

L"J;_I

~

Fig. 10

5. Miscellaneous
In order to further reduce power consumption during
data retention by even a small margin, the use of aMOS
FET as the transistor generating the POWER FAIL
output signal is recommended. This is in order to
prevent flow of current from the 14kn resistor.

190

........

CMOS Vcc

MASK ROM KANJI GENERATION MEMORY

DESCRIPTION
1.· KANJI GENERATION MEMORIES
Number
of codes

Character storing
capacity

Configuration

Character
style

Bit
capacity

Access
time

18

JIS standard No.1
3418 characters

24 x 24

Ming style

128K bits

450#-,s max

10

JIS standard No.1
3418 characters

16 x 18

Gothic style

128K bits

450#-,s max

M 5 M28101

1

JIS standard No.1
3418 characters

16 x 18

Gothic style

1M bits

25#-,s max
(16 x 18 transfer)

M S M28201

1

JIS standard No.2
3384 characters

16 x 18

Gothic style

1M bits

25#-,s max
(16 x 18 transfer)

IC
models
M 5 M38128- 00
'C

2
In

m.~0
E

M 5 M38128- 17

Q.
In

.r:

CI)

~E

M 5 M38128- 18

2
M 5 M38128- 27

'C
CI)

In
CI)

8. .;::
0
:: ~
In

.3 E

is represented by low level output.

2. MSM38128 SERIES
The electrical specifications of the MSM38128 series
high speed kanji generation memory ICs conform to the
specifications of the MSM38128 16384 word x 8 bit
mask ROM, except that the output enable (OE) signal is
active when set at a low level. The character data is
represented by high level output and background data

2.1
(1)

Pattern Storing Method
24 x 24 ..... Ming style
The 8 address x 8 bit data per character is stored
in one chip, and one character is configured with
nine chips.

Data

T

n

I

n+1
n+2

c

o

.~
:0

~
-0
'C

«

8a~~

J

11~~==1_
Data direction

~-----------

24 bits

-----------~

~
-0

:¥

n +3

n + 4 1--4-----1-----4---1--n+5
n+6
n+7

1--+--+---1--+--t---I---+--+-t---I---1
L..-.L.----L---L--lL-.L.--...J

Data direction and
address direction

ill

One character storing method
(24x 24)

191

• MASK ROM KANJI GENERATION MEMORY DESCRIPTION . - - - - Since approximately 2K bits of character data
can be stored in nine chips, the3418JIS standard
No.1 characters are divided into two for storing
in two groups of nine chips.
The nine codes to form a character are stored in
nine chips as shown in the following figure.

MS M38128

M S M38128
-01

M S M38128
-02

M S M38128
-03

M S M38128
-04

M S M38128
-05

M S M38128
-06

M S M38128
-07

M S M38128
-08

-00

M S M38128
-09

M S M38128
-10

M S M38128
-11

M S M38128
-12

M S M38128
-13

M S M38128
-14

M S M38128
-15

M S M38128
-16

M S M38128

-17

Correspondence of chips to nine codes of a character

t

4ad dresses ~.
r-r-

Data

+ ~I.

-t-

(.J

~

:0

•

en
en

~

"0
"0

,

4 ad dresses

~

~

"0
"0

«

n
n+1
n+2
n+3

~+--t-'---...J..----L-~_

«

d~esses~
t

2 bits

..

c:

0
'';;

+-- .I

4 ad

16 x 18 ..... Gothic style
The 4 address x 8 bit data per character is stored
in one chip, and one character is configured with
ten chips. Each character data is associated with
unused data of two addresses.

I.

4 addresses
18 bits
4ad dresses

(2)

Data direction and address direction

•
•

unused all 0 area
Data direction

___

-I

One character storing method
(16x 18)

The ten cOdes to form a character are stored in
ten chips as shown in the following figure.

m
192

M S M38128
-18

M S M38128
-19

M S M38128
-20

M S M38128
-21

M S M38128
-22

M S M38128
-23

M S M38128
-24

M S M38128
-25

M S M38128
-26

M S M38128
-27

- - - - - - - . MASK ROM KANJI GENERATION MEMORY DESCRIPTION.
2.2 Coda Compression
The MSM38128 series memories perform code compression so that a correspondence can be established
between the JIS kanji codes and compressed, codes.

Y (second byte)

00

20

60

40

7F

00

2121

20

Non-kanji area

r///;® j///////®// / / / / /©i/ A
3021

X (first byte)

40

/"

27 7E

JIS standard No.1
4F 7E

60

K anji code

7F

20

00

Second byte
40

60

7F

Undefined area 0021
First byte

10
1F

II

®

0

@

®

o

Note:

JIS standard
No.1

~

1F7E

Compressed code

: 0901 - OF1 F }

: 1100 -

171 F
:1900-1F1E

Non-kanji area

I n the case of 24 x 24 character data, the part
above the broken line is stored in the MSM38128-00
to 08 chips and the part under the broken line is
stored in the MSM38128-09 to 17 chips.

193

• MASK ROM KANJI GENERATION MEMORY DESCRIPTION . - - - - < Compressed code>
First byte
Second byte

0

0

a 12

all

a lO

a9

as

a,

a6 .

as

a4

a3

a2

a1

The following rule applies to the code conversion from JIS kanji code to compressed code.

JIS kanji code
First byte

Second byte

Y,

I I
Y,

Y,

y.

I I
y,

y,

y,

1 Compressed code I

< Non-kanji area >
First byte

I

0

a 12

all

Y,

Y6

0

< JIS standard No.1

I

0

111
194

I I
0

Xs

Second byte

a 10

I I
X,

kanji area

X4

a9

as

a,

a6

as

a4

a3

a2

a1

X2

XI

0

0

Ys

Y4

Y3

Y2

YI

Y,

Y6

Ys

Y4

Y3

Y2

YI

>

I I I I
X,

X2

Xl

- - - - - - - . MASK ROM KANJI GENERATION MEMORY DESCRIPTION.
2.3 Code Compressing Conversion Circuit Example

74157
1A
18
2A
28
3A

Xs
X4

Y,

38
4A

YIS

48

1Y

au

2Y

all

3Y

a,

4Y

o alS

SELECT
-::-

X7
X6

0-----1

Ys

0

o as

Y4

0

o a4

Y3

0

o a,

Y2

0

o a2

YI

0

o al

Xl 0

o a lO

X2

0

o a9

X3

0

o as

JIS kanji code

iii

Compressed code

195

• MASK ROM KANJI GENERATION MEMORY DESCRIPTION .1----2.4 Simultaneous Reading of 24 Hirizontal Bits of 24 x 24 Character Data, Example
Compressed code

[a 12 all
MSB

Row address within a
character

........................

< 12 bits>

al a l )
LSB

< S bits>

[b s b 4 b a b l b l )
MSB
LSB

The correspondence between the MSM38128 address input signal and compressed code is shown in the following
table.

Address input

A13

Au

All

A 10

Compressed code

all

a to

~

aa

A9

Aa

a,

a6

A,

as

A6

a4

As

A4

a2

aa

A3

al

Al

ba

Al

Ao

bl

bl

For the selection of ROM codes, a decode signal composed of bits b4, bS, and a12 is input to the CE andOE pins.
a 12

bs

b4

0

0

0

MSM38128-00, -01,002

0

0

1

MSM38128-03, -04, -OS

0

1

0

MSM38128-06, -07, -08

1

0

0

MSM38128-09, -10, -11

1

0

1

MSM38128-12, -13, -14

1

1

0

MSM38128-1S, -16,-17

ROM codes

2.S Simultaneous Reading of 16 Horizontal Bits of 16 x 18 Character Data, Example
Compressed code

[all all························
MSB

al a l )
LSB

Row address within a character [b s b 4 b a b l b l ]
MSB
LSB

The correspondence between the MSM38128 address input signal and compressed code is shown in the following
table.

ID

Address input

Ala

A12

All

A 10

A9

Aa

A,

A6

As

A4

Aa

Al

Al

Ao

Compressed code

au

all

a 10

a9

aa

a,

a6

as

a4

aa

a2

al

bz

bl

196

--'--~---.

MASK ROM KANJI GENERATION MEMORY DESCRIPTION.

For the selection of ROM codes, a decode signal composed of bits b 3 , b 4 , and b s is input to the CE and

bs

b4

b3

0

0

0

MSM38128-18, -19

0

0

1

MSM38128-20, -21

0

1

0

MSM38128-22, -23

0

1

1

MSM38128-24, -25

1

0

0

MSM38128-26, -27

a E pins.

ROM codes

3. MSM28101, MSM28201
For the MSM281 01 and MSM28201, refer to the product catalogs.

iii
197

---

Oki Electric Industry Co., Ltd.

Oki Semiconductor Inc.

Oki Electric Europe GmbH

10-3 Shibaura 4-chome, Minato-ku,
Tokyo 108, Japan
Tel:
Tokyo 454-2111
Telex: J22627

Suite 401, 1333 Lawrence Expy
Santa Clara, Calif. 95051, U.S.A.
Tel:
408-984-4842
Telex: 9103380508 OKI SNTA

Emanuel-Leutze Str. 8, 4000,
Dusseldorf 11 , West Germany
Tel:
0211-592031
Telex: 858-7218

E3S0021Z

82-05-2B. PR INTED IN JAPAN (T)



---

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