1982_PMI_Linear_Integrated_Circuits_Product_Catalog 1982 PMI Linear Integrated Circuits Product Catalog
User Manual: 1982_PMI_Linear_Integrated_Circuits_Product_Catalog
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Copyright© 1981
Precision Monolithics Incorporated
PMI reserves the right to make changes to the products contained in this data book to improve performance,
reliability, or manufacturability.
Although every effort has been made to insure accuracy of the information contained in this data book, PMI
assumes no responsibility for inadvertent errors.
PMI assumes no responsibility for the use of any circuits described herein and makes no representation that
they are free of patent infringement.
The products in this catalog are manufactured under one or more of the following patents: 4,055,773;
4,056,740; 4,092,639; 4,088,905; 4,118,699; 4,131,884; 4,138,671; 4,168,528; 4,109,215; 4,142,117; 4,068,254;
4,228,367; 4,210,830; 4,260,911; 4,272,656; 4,285,051.
PRECISION MONOLITHICS, INC. LIFE SUPPORT APPLICATION POLICY
As a general policy, Precision Monolithics Inc. does not recommend the use of its components of any type in
"Life Support Applications" wherein failure or malfunction of the PMI component threatens life or makes
injury probable. Any manufacturer which incorporates PMl's components within a life support system must
obtain PMl's prior consent based upon assurance to PMI that a malfunction of PMl's component does not pose
direct or indirect threat of injury or death, and leven if such consent is given I shall indemnify PMI from any
claim, loss, liability, and related expenses arising from any injury or death resulting from use of PMI components in a life support application. PMl's warranty is limited to replacement of defective components and does
not cover injury to persons or property or other consequential damages.
TABLE
OF
CONTENTS
TABLE OF CONTENTS
PRODUCT
TITLE
PAGE
SECTION 2 • ORDERING INFORMATION
Ordering Information
2-2
SECTION 3 • a.A. PROGRAM
Q.A. Program
3-3
SECTION 4 • IC CROSS REFERENCE
Analog Devices •••••••••••••.•••••••••••••.•••.••.••.••.•••••.•••.•.•••.•.•••••••••••..•..• 4-3
Advanced Micro Devices ••••••••••••••.•••••••••••••••••.•.•..•••.•..•.••.••••••••.••••..•• 4-4
Burr Brown ••••.••.••..•.••••.••••••.••••••.••.•••.••.•••.•.•...•...•.••••••••.•.••.••.•••. 4-5
Datel .••.••..•..••.•...•.•..•.•...•.••.•.•..••.••..••.•...•.••.••..•.••••..•.••..•••••••.• 4-6
Fairchild .•..•.••...•.•...••.•••..•.•..•.•.....••.•.•••.••••••.•••.•.•••.•..•..•..••••••..• 4-7
Harris •..•.....••....••..•....••..•....•.•.........•.••..••..•...•.••••..•.......•.....•..• 4-7
Hybrid •••.••••••••••••.••••••••••.••.•••••••••.••••••••••.•..••...•.•.•••.••••.•....•••..• 4-8
Intersil ••••••.••••••.•••••••••.••..•..••.•••.••.••..••.•......•.....•.••.•••••..••.•..•.••• 4-8
Micro Networks .••.••..•• • • . • • • • • . . . . . • . . • . . • . . • • • • • • . • . • • . . • • . . . . . • . • • . • . . . . . . . • • . . • • . • .• 4-9
Motorola .....••.•..•..••......•......•..•.......•..••....•..••••••••.....•.•.•••.•••••••.• 4-9
National Semiconductor •.••.••..••...•.•......••..•..•..••.•••••.•.•.•.•...•••••••••••••. 4-10
Raytheon ..•••••..••.•••••••••.••••••..••.••.••••••.••••••••.•••••..••..........•.•..••.• 4-11
RCA .•••.•..•••.•...•.....•...•..•.•..........••...•.•...•..••..•.•••••.•.••..•.••••••••. 4-12
Signetics •...•.••..••.••..•••..••.••.•...•....•.•..•.•....•••••.••••.••••..•.••••••••••••. 4-12
Siliconix •.•••.••..••.••..••.••••.•.••...•....•••....•••.••.•••••.•••••..•.•••••••••••.•.. 4-13
Texas Instruments .••.••••••.••.••••••.••••••.•••••••••••••••••••••••...•..••••••••••..•.. 4-13
SECTION 5 • OPERATIONAL AMPLIFIERS
OP-01
OP-D2
OP-03
OP-04
OP-05
OP-D6
OP-D7
OP-08
OP-09
OP-10
OP-11
OP-12
OP-14
OP-15
OP-16
OP-17
OP-18
OP-19
OP-20
OP-21
OP-24
OP-27
OP-34
OP-37
OP-207
OP-215
OP-220
OP-227
Inverting High-Speed Operational Amplifier. • . • • • • • • . . • • • • • • • • . . • • • • • • . • • . . . . • . . • • . • • . • • • • • •• 5-8
High-Performance General-Purpose Operational Amplifier ••.•...•..•...•.•...•...•.•.••••••. 5-14
Dual-Matched High-Performance Operational Amplifiers .•.••...••.......•••••.••••••••.••.. 5-22
Dual-Matched High-Performance Operational Amplifiers (See OP-03) .....•.•••••..•..•..•... 5-22
Instrumentation Operational Amplifier ...................................................... 5-30
High-Gain Instrumentation Operational Amplifier .••.•••..•.•••.•..•....•••..•••••••.••.••.. 5-39
Ultra-Low Offset Voltage Operational Amplifier ............................................. 5-47
Precision Low Input Current Operational Amplifier .......................................... 5-57
Quad-Matched 741-Type Operational Amplifier •..•.•••..•.•.•.•....•.••.•••••.••..•...•.••.. 5-65
Dual-Matched Instrumentation Operational Amplifier •••••.•.•.••.••••••••....•...•.••.•••••. 5-74
Quad-Matched 741-Type Operational Amplifier (See OP-D9) •••••••.••••.•.•........•........ 5-65
Precision Low Input Current Operational Amplifier .......................................... 5-85
Dual-Matc;hed High-Performance Operational Amplifier (See OP-03) •..•.•••••.•............• 5-22
Precision JFET Input Operational Amplifier •••••••..••..•...•.••..••••••••••••...•.••..••..• 5-90
Precision JFET Input Operational Amplifier •••••••••.•.••.••••••.••••••.•..•..•.••.••.•••.•• 5-90
Precision JFET Input Operational Amplifier •••••••.•••••••••••••••••••.•..•..•...••••••••••• 5-90
High Performance General Purpose Externally Compensated Operational Amplifier ........•. 5-104
High-Performance General-Purpose Operational Amplifier (See OP-02) •.•.••.....•.••..••.•• 5-14
Micropower Precision Operational Amplifier ............................................... 5-112
High-Speed Low-Power Precision Operational Amplifier •••••••••••.•••.••....•..••.••.••••• 5-118
Ultra-Low Noise Operational Amplifier •...•..•••.••.••••.•••••.••••••.••.••.•.••••••.••••• 5-122
Ultra-Low Noise Precision Operational Amplifier ........................................... 5-131
Ultra-Low Noise Operational Amplifier (See OP-24) ........................................ 5-122
Ultra-Low Noise Precision High-Speed Operational Amplifier .••••••••••••••..•......•..•..• 5-140
Ultra-Low Vos Dual Instrumentation Operational Amplifier ••.••...•.•....••...•••.•••••••.•• 5-148
Dual Precision JFET Input Operational Amplifier ........................................... 5-155
Micropower Precision Dual Operational Amplifier .......................................... 5-162
Ultra-Low Noise. Low Offset Dual Instrumentation Operational Amplifier ...•.••••••••••••••. 5-171
PAGE 1-2
TABLE OF CONTENTS
PRODUCT
TITLE
PAGE
~
Z
SECTION 5 • OPERATIONAL AMPLIFIERS (continued)
OP-420
OP-421
PM108A
PM155A
PM156A
PM157A
PM725
PM741
PM747
PM1458/1558
PM2108A
PM4138
JM38510/10104
JM38510/10106
JM38510/11401
JM11402/114031
JM11404/11405/11406
Quad Micropower Operational Amplifier ...........................•..•.......•...........•
High Speed, Quad Micropower Operational Amplifier .......•...............................
Low Input Current Operational Amplifier ....•...................•.........................
Monolithic JFET Input Operational Amplifier ..•...........................•.........•......
Monolithic JFET Input Operational Amplifier ...............................................
Monolithic JFET Input Operational Amplifier ........................ " ................... "
Instrumentation Operational Amplifier .............................. " .....................
Compensated Operational Amplifier .•..............•...•...........•......................
Dual Compensated Operational Amplifier ..................................................
Dual Compensated Operational Amplifier ..................................................
Low Input Current Operational Amplifier (See PM108A) ...............•....................
Quad 741-Type Operational Amplifier .............••.......................................
JAN Single Low Input Current Operational Amplifier .......................................
JAN Single Low Input Current Operational Amplifier ..................................•....
JAN JFET Input Operational Amplifier .....................•............................... 5-220
Precision Buffer/Voltage-Foliower .........................•.......•........................ 6-3
High-Speed BIFET BufferlVoltage-Foliower .••....•..........••...•................•...•...• 6-8
Very High-Speed BufferlVoltage-Foliower .............•...•................................ 6-12
SECTION 7 • COMPARATORS
CMP-01
CMP-02
CMP-04
CMP-Q5
Fast Precision Comparator .....................................•.•....................•.... 7-5
Low Input Current Precision Comparator ........•...............•.......................... 7-14
Low Power Precision Quad Comparator .........................•.•..................•••..• 7-22
High-Speed Precision Comparator With Latch Circuit ...•. '" .....•.•....................... 7-30
PM139/239/339
PM139A1239A1339A
Low Power Quad Voltage Comparator
7-37
SECTION 8 • MATCHED TRANSISTORS
MAT-01
Ultra-Matched Monolithic Dual Transistor .......•.•.•••••.........••...•......•.....••...•.. 8-4
SECTION 9 • VOLTAGE REFERENCES
REF-Q1
REF-Q2
REF-05
REF-10
+ 10V Precision Voltage Reference .....•....................•...•....•.........•.........•.• 9-3
+5V Precision Voltage Reference/Temperature Transducer •....•••••••...................... 9-10
+5V Precision Voltage Reference With Guaranteed Long-Term Stability ..•..................• 9-19
+10V Precision Voltage Reference With Guaranteed Long-Term Stability ...•............•••.. 9-26
SECTION 10. D/A CONVERTERS
DAC-Q1
DAC-Q2
DAC-Q3
DAC-04
DAC-05
DAC-06
DAC-08
DAC-1O
DAC-20
DAC-76
DAC-78
6-Bit Voltage Output 01 A Converter ..••....•....•...•...••.....•....•••......•.........•..
10-Bit Plus Sign Voltage Output D/A Converter ....•.•...............••..•..•...........•.•
10-Bit Plus Sign Voltage Output D/A Converter (See DAC-02) .•.•...........•.•...•......•.
Two's Complement 10-Bit D/A Converter ............•.•....•..••••••..•...•......•........
10-Bit Plus Sign Voltage Output D/A Converter (See DAC-02) .....••...•........•..........
Two's Complement 10-Blt D/A Converter (See DAC-Q4) ..............•••.......•...........
8-Bit High-Speed Multiplying D/A Converter •......•••.•.••..•..•...•.•...................
10-Bit High-Speed Multiplying D/A Converter •....•..•.•.......••••.........•.....•.......
2-Digit BCD High-Speed Multiplying D/A Converter .......................................
COMDAC@ Companding D/A Converter .....•...........•........•.......•...............
COMDAC@ Companding D/A Converter .......................... '........................
PAGE 1-3
...Z
UI
5-182
5-188
5-194
5-197
5-197
5-197
5-203
5-206
5-208
5-208
5-194
5-211
5-214
5-217
SECTION 6 • BUFFERS (VOLTAGE FOLLOWERS)
BUF-Q1
BUF-02
BUF-03
III
10-12
10-16
10-16
10-21
10-16
10-21
10-26
10-36
10-44
10-52
10-69
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TABLE OF CONTENTS
PRODUCT
TITLE
PAGE
SECTION 10 • D/A CONVERTERS (continued)
10-Bit 01 A Converter ..................................................................... 10-79
10-Bit 01 A Converter ••...••••..•••...•......•......•....••....•....•.•......•..•••.•..... 10-79
6-Bit Voltage Output D/A Converter ....................................................... 10-87
9-Bit Digital-to-Analog Converter (8 Bits Plus Sign) ..••••••••••••.••••••..••..•...•••••••.. 10-91
11-Bit Digital-to-Analog Converter (10 Bits Plus Sign) ...................................... 10-94
12-Bit High-Speed Multiplying D/A Converter ............................................. 10-99
8-Bit High-Speed "Microprocessor Compatible" Multiplying D/A Converter .•..•.....•••.••. 10-111
8-Bit High-Speed "Microprocessor Compatible" Multiplying D/A Converter .....••.•.••••••. 10-122
8-Bit Multiplying D/A Converter ...•••...•••.•...•••.••••..••••....•...••••••.••••......• 10-134
JM38510/11301/11302 JAN 8-Bit Digital-to-Analog Converter ................................................... 10-140
DAC-100
DAC-101
DAC-206
DAC-208
DAC-210
DAC-312
DAC-808
DAC-888
DAC-1508N1408A
SECTION 11. MULTIPLEXERS/ANALOG SWITCHES
MUX-08
MUX-16
MUX-24
MUX-28
SW01/02
SW03/04
SW06
SW201
SW202
SW751017511
8 Channel BI-FET Analog Multiplexer ...................................................... 11-5
16 Channel BI-FET Analog Multiplexer. .. .. .. .. .. . .. .. . .. . .. . .. . .. .. ... . .. .. ... .. .. .. .. ... 11-14
Dual4-Channel BI-FET Analog Multiplexer ..•........•..••....•••....•......•.•....••..••.• 11-5
Dual 8-Channel BI-FET Analog Multiplexer. .. .• .. . . . .• .•. • •. . .• • •• .. •. . . ..•. .•• .. •• •••• ••. 11-14
Quad SPST BI-FET Analog Switches •.........................••.•..••........•..•..••••.. 11-24
Quad SPST BI-FET Analog Switches ..•••....•.......•....••..•.....•....•...••.•••••••.•. 11-24
Quad SPST BI-FET Analog Switch ...•.....•....•..•...............•....•...•..•••..•.•... 11-30
Quad SPST BI-FET Analog Switches ....•.......•........•....•••...•........••..•.••••.•. 11-40
Quad SPST BI-FET Analog Switches ...••.•..•..•..........................•.••••.•.•••... 11-40
Quad SPST BI-FET Analog Switches •••••..•••..•.••...••...•••.....•...•..••...•...••..•. 11-47
SECTION 12 • SAMPLE AND HOLD AMPLIFIERS
SMP-10/11
GAP-01
PKD-01
Low Droop Rate/Accurate Sample and Hold Amplifiers ...................................... 12-5
Analog Signal Processing Subsystem ..................................................... 12-14
Monolithic Peak Detector •.........••....••...•••••••••••.••••.••••.•••••••••.•••..•••... 12-29
SECTION 13 • TELECOMMUNICATION
DAC-86
DAC-87
DAC-88
DAC-89
DMX-88
MUX-88
RPT81/82
SMP-81
COMDACcI!l Companding D/A Converter ................................................... 13-3
COMDACcI!l Companding D/A Converter ••...•......•...•.•..•.••...•...•.•.•••..••••.••.• 13-11
COMDACcI!l Companding D/A Converter •.••••..••••.....•..............•...•••..••.••••.. 13-18
COMDACcI!l Companding D/A Converter .•••••..••••.••••••.•••••.••...••.•••..••...••.•.. 13-25
8-Channel Analog De-Multiplexer for PCM Codecs ••••••••.•••••.•••.•••.•••....••..•....• 13-32
8-Channel Analog Multiplexer for PCM Codecs ............................................ 13-37
PCM Carrier Repeaters •••...•••....••••....•..•.....•..••...•••...•.........••.•.•••••.. 13-42
Telecommunications Sample and Hold Amplifier .•..•....••..........•..••...•••.•••••••••. 13-52
SECTION 14 • CUSTOM WAFER FAB
PMI's Custom Wafer Fabrication Facility .................................................... 14-2
SECTION 15 • APPLICATION NOTES
AB-1
AB-2
AB-3
AB-4
AB-5
AB-6
AB-7
AB-8
AN-6
Strobing the DAC-08 Under Logic Control •.•..•••..•.•.•.•..•.•.....•..••..••..•........••• 15-3
OP-10 Instrumentation Amplifier CMRR vs Frequency Improvement ••••.••.•••.•...•.•....••. 15-4
Digital Nulling of OP-05, OP-07 and OP-07 .........•.•...•...•.•....•.••..••......••....•.. 15-5
REF-02 Temperature Controller .................••.••••.••••.•••••..•...•.•..••.••.•••...•. 15-6
The DAC-03~P Controlled D/A ••...•....•••.•.•••..••••..••...••....•..••.••...••.......••. 15-7
Single Supply Operation of the DAC-08 and DAC-20 •.•...••...•.•.•....••.•••..•.•.....•••. 15-8
Negative Supply Loss Protection for PMI Multiplexers ....................................... 15-9
3-Digit BCD D/A Converter ........................ ; ...................................... 15-10
A Low Cost, High-Performance Tracking NO Converter •.•••.••••••••••••.••...•...••.•••.• 15-11
PAGE 1-4
TABLE OF CONTENTS
PRODUCT
TITLE
PAGE
AN-10
AN-11
AN-12
AN-13
AN-14
AN-15
AN-16
AN-17
AN-18
AN-19
AN-20
AN-21
AN-22
AN-23
AN-24
AN-25
AN-26
AN-27
AN-28
AN-29
AN-30
AN-31
AN-32
AN-33
AN-34
AN-35
AN-36
AN-37
AN-38
AN-39
AN-40
AN-41
AN-42
AN-43
AN-44
AN-45
AN-47
AN-48
AN-49
AN-50
AN-53
•
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SECTION 15 • APPLICATION NOTES (continuedl
Simple Precision Millivolt Reference Uses No Zeners ..•..............•...•....•...•....•... 15-16
A Low Cost, Easy-to-Build Successive Approximation
Analog-to-Digital Converter .......•.......•....•..•.•...•.•.•........................•••. 15-17
Temperature Measurement Method Based On Matched Transistor
Pair Requires No Reference ...........................•.....••......... " •..•.••••...•.... 15-24
The OP-07 Ultra-Low Offset Voltage OP AMP - A Bipolar OP AMP
that Challenges Choppers, Eliminates Nulling .••.••....•••.•.••.••••••.••.•.•..••••....•••. 15-29
Interfacing Precision Monolithics Digital-to-Analog Converters with CMOS LogiC .....•••.... 15-39
Minimization of Noise in Operational Amplifier Applications ...............••..••••......... 15-43
Low Cost, High Speed Analog-to-Digital Conversion with the DAC-08 .•••..........••....... 15-52
DAC-08 Applications Collection ..........••.•.•••.•••.•.•••••.•••.••••.........•.•••..•... 15-59
Thermometer Applications of the REF-02 .................................................. 15-70
Differential and Multiplying Digital-to-Analog Converter Applications •...•............•••..•. 15-73
Exponential Digitally Controlled Oscillator Using DAC-76 •..................•...•......••.• 15-81
3 IC 8-Bit Binary Digital-to-Process Current Converter with 4-20mA Output .........••....... 15-85
Software Controlled Analog-to-Digital Conversion Using DAC-08
and the 808A Microprocessor .......•......•••.....•.....•.•..•................•...••••... 15-87
Digital-to-Analog Converter Generates Hyperbolic Functions ............................•.. 15-91
The OP-17, OP-16, OP-15 as Output Amplifiers for High-Speed D/A Converters ...........•... 15-93
The 725 OP AMP as a Low Level Comparator ............................................... 15-95
Low Cost Four Channel DAC Gives BCD or Binary Coding .••••....•..•..........•••••..... 15-99
Polarity Programmable Peak Detector .................................................... 15-103
Audio Applications for the DAC-76 Companding D/A Converter ..............•.•.........•. 15-105
Getting Started in Active Filters .•.....•..•...............................••.•.•••........ 15-112
Data Conversion Interfacing with the 8080 Microprocessor ........•...... " ..••. , .•........ 15-119
Successive Approximation Register Design for MUlti-Channel CODECs ...........•........ 15-130
Single Supply Operation of PMI Multiplexers ...•................•........................ , 15-134
A Guide to Hybrid Integrated Circuit Design .............................................. 15-136
BCD DAC's Simplify Intelligent Instrument Design .•.....•.......•.•.•.•••................ 15-140
Understanding Crosstalk in Analog Multiplexers .......................................... 15-149
DAC-08 Control of 555 Timers ..............•.......••.•..•.•••......•.........•.••••.••. 15-157
Eight-Channel CODEC Demonstrator ..•................•.....•....•••........•.•........ 15-161
Four-Channel Shared Codec ........................••.•...••••......•.........•.••••.•.. 15-168
Companding Digital-to-Analog Converter ................................................. 15-174
A Buffer Applications Collection ......................................................... 15-186
Improved Shared-Channel CODEC Design with PMl's New Companding DACs ............. 15-190
A 1kHz, 0 dBmO Standard Signal Generator .............................................. 15-198
The DAC-76 in Control Applications ...................................................... 15-200
Composite Buffer Provides Speed, Accuracy .............................................. 15-204
Time Sharing Permits Design of Controller with Single DAC •.•..••.•••••.•.•......•.•...•. 15-206
BCD DAC Makes Programming of Function Generator Simple •••......•.••........••....•• 15-210
DeSigning Digital Repeaters with IC's . .. .. • . .. . .. . . .. .. . .. . .. • .. .. . .. .. . .. .. .. . .. . .. • . .. •. 15-214
Designing a Multiple-Channel Coder/Decoder with Bipolar Devices ........•..•.••......•.. 15-221
A Variable-Frequency, Clock Recovery Circuit Using the RPT-81 or RPT-82 ...•....•........ 15-230
Sample/Hold Circuit Monitors Two Input Signals and Tracks the Smaller or Larger Signal ..•. 15-232
SECTION 16 • PACKAGE INFORMATION
Mechanical Dimensions - CANS
TO-78 (H) .••...................•.....•...•.•.•.....•.•.....•••.......•••.......••••.•.• 16-3
TO-99 (J) .........••.......•.......•.......•.•............•........•.................•. 16-3
TO-100 (K) .•••......••...•••....•..••....•.........•.........................•••..•...• 16-3
PAGE 1-5
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TABLE OF CONTE .... TS
PRODUCT
TITLE
PAGE
SECTION 16 • PACKAGE INFORMATION (continued)
Mechanical Dimensions - DIP's
8-Pin Epoxy B Mini-DIP •....•••••.••••.•....•••.•...•....•.•.•...•...••...•....•..•.••••
8-Pin Hermetic DIP (Z) ...•..•....•.•....•.•...•••.••.••••...•••...•..••....••••.••.•..••
14-Pin Hermetic Dual-in-Line (V) ........•.....•••....•...•..••.•......•••••••..•••....••
16-Pin Hermetic Dual-in-Line (Q) •.....••.......................•......••.•••.........•••
18-Pin Hermetic Dual-in-Line (X) •..•••.•••...••.•....•......•.......•••..••..........•••
20-Pin Hermetic Dual-in-Line (R) ........................................................
24-Pin Hermetic Dual-in-Line (V) .••••...•.••..•••.....•••...••••..••.•..•..•.•••.••••.••
28-Pin Hermetic Dual-in-Line (T) .•..•..•...•.••....•......•......•..••••.•••.........•..
Mechanical Dimensions - FLATPACKS
10-Pin Hermetic Flatpack (L) •....••.••....••••••.••••....•••...••.•••••....•...•...••..•
14-Pin Hermetic Flatpack (M) .....•••....•.•••.•••••••..••..•..••..••.........•••.••.•..•
24-Pin Hermetic Flatpack (N) ••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••
SECTION 17 • SALES OFFICES, REPRESENTATIVES AND DISTRIBUTORS
PAG.E1-6
16-4
16-4
16-5
16-5
16-5
16-6
16-6
16-6
16-7
16-7
16-7
ORDERING
INFORMATION
ORDERING INFORMATION
DAC
08
A
Q
Device
Type
Model
Number
Electrical
Grade
Package
Suffix
How to order standard product.
1.
Select device type from catalog:
BUF .•....••..
CMP .•..•••...
DAC •....•..••
DMX .•••.•.•••
GAP .••.....•.
MAT .••.•..•..
MUX ....••.•..
OP •.•..•...••
PKD ...•....••
PM ...........
REF .••.......
RPT .•........
SMP •••...•...
SW .•.. . . . . . ..
Buffer
Comparator
Digital-to-Analog Converter
DeMultiplexer
General Purpose Analog Processor
Matched Transistor
Multiplexer
Proprietary Operational Amplifier
Peak Detector
Second-Source Industry Specs
Voltage Reference
PCM Line Repeater
Sample and Hold
Analog Switch
2.
Select Model Number from Catalog (see Device Section ...- - - - - - - - - '
and Selection Guides)
3.
Select Electrical Grade from Catalog. See Data Sheet for
specific suffix, DAC-02, DAC-03, DAC-04, DAC-05,
DAC-06 and DAC-l00 have multi-letterelectrical grades.
4.
Select package from appropriate data sheet In catalog.
H ......•••..••
J .............
K .......•.....
L ..........•.•
M ....•....••.•
N ...••..•.••.•
P .••...•••..•.
Q .............
R ...••...•.•..
T ...•......•..
V ..••..•...••.
X .......••...•
Y •.•.•.••.....
z. . • . . . . . . . . . .
e----------------'
6 lead TO-78
8 lead TO-99
10 lead TO-l00
10 lead Hermetic Flatpack } SPECIAL
14 lead Hermetic Flatpack
ORDER
24 lead Hermetic Flatpack Only
Epoxy 8 DIP (ALL)
16 lead Hermetic DIP
20 lead Hermetic DIP
28 lead Hermetic DIP
24 lead Hermetic DIP
18 lead Hermetic DIP
14 lead Hermetic DIP
8 lead Hermetic 01 P
All PMI -55°C to +125°C devices are available with
Class B, MIL-STD-883 screening as standard products.
To order an 8838 part, simply include the designation
"/833" in the part number after the package suffix. For
example, the DAC-08AQ screened to 883B requirements
would be ordered as a DAC-08AQ/883. The DAC-l00
data sheet is an exception to this procedure. Consult the
DAC-l00 data sheet for MIL-STD-883 ordering information.
PMl's factory is certified to produce JAN parts per MILM-38510. Consult the factory for availability of specific
slash sheet parts not listed in this catalog.
PAGE 2-2
DICE ORDERING INFORMATION
DAC-08
All PMI chips are available with either plain backing or, at
extra cost, 1-micron thick eutectic-bonded gold backing.
Electrical performance is specified at 25 0 C for all products
in the data sheet section of this catalog. Visual inspection
criteria is as listed below.
For price and delivery information or quotations for gold
backed dice or special devices, contactthe nearest PMI sales
office or representative listed in the back of this Catalog.
1.
Select device type from catalog:
BUF ...............
CMP ..............
DAC ..............
DMX ..............
GAP ..............
MAT ..............
MUX ..............
OP .. .. . . .. . . . . . . ..
PKD ..............
PM ...............
REF ...............
RPT.. .. .. .... .....
SMP ..............
SW ...............
Select Model Number from Catalog (see Device Section
and Selection Guides).
3.
Select electrical grade from data sheet.
4.
Add 1250 C Testing Option ("T") if desired.
5.
Select visual screening level.
6.
Select backing suffix.
T
B
DeviceT~pe
z
o
ELECTRICAL GRADE
N=Top
G= Middle
GR = Lowest
5
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T = Temperature
Tested
(125°C) Die Option
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VISUAL CRITERIA
A = MIL-STD-883, Method 2010.2,
Test Condition A.
B = MIL-STD-883, Method 2010.2,
Test Condition B.
C = PMI "C" Visual, Based on MILSTD-883, Method 2010. Issued
1 May 1968.
1
BURNED-IN DEVICES
PMI now offers all commercial and industrial grade parts with
160 hour orequivalent (at our option) burn-in. Parts with this
option are specified with the letters BI added between the
model number and the electrical grade. Forexample, to order
a DAC-D8AQ with burn-in, the part number will be: DAC08BIAQ. This service provides customers with the extra margin of safety required in various programs where early life
failures must be reduced as much as possible.
SPECIAL DEVICES
Precision Monolithics, Inc. will be pleased to furnish quotations on requirements for devices with special electrical testing, extra reliability processing and/or qualification data per
MIL-STD-883, condition A or MIL-M-38510. Please refer
these requests to the authorized representatives or PMI sales
office listed in Section 17 of this Catalog.
PAGE 2-3
C
Backing Suffix
C= Plain
CG= Gold
Backed
& Model
Number
J
Buffer
Comparator
Digital-to-Analog Converter
DeMultiplexer
General Purpose Analog Processor
Matched Transistor
Multiplexer
Proprietary Operational Amplifier
Peak Detector
Second-Source Industry Specs
Voltage Reference
PCM Line Repeater
Sample and Hold
Analog Switch
2.
N
FEATURES
•
•
•
•
•
•
•
•
•
•
OAC·08
Hlghe.t yield. .•........ 25° C Parameter. Guaranteed
Highest Performance ••.••••••..• Tight Specifications
Hlghe.t Reliability-Exclusive "Triple Pa8llvatlon "Proce81
Wide Temperature Range Operallon.
Excellent Ole Attach •.••• Thick Gold or Standard Backing
100% Visually Inspected to MIL-STD-883 Criteria
Tight Distributions .•...•.. Precision Process Control
carefully Packaged •••..••• No Loss During Shipment
Guaranteed Dimensions •.•...••••...••....... ±3mlls
Guaranteed Pad Size ......................... 4 mils
B
N
t
C
t
Backing Suffix
C= Plain
CG= Gold
Backed
Device Type
& Model
Number
ELECTRICAL GRADE
N=Top
G= Middle
GR= Lowest
GENERAL DESCRIPTION
The superior performance of most Preci$ion Monolithics
products is available to the hybrid microcircuit designer. All
chips are 100% electrically tested for all guaranteed DC
parameters at 25°C and are 100% visually inspected to MILSTD-883 visual criteria. Each die is protected with our "Triple
Passivation" Process incorporating an advanced Silicon
Nitride ion barrier plus a thick glass coating over the metallization. Dice are packaged in waffle-pack carriers with an
anti-static shield and cushioning strip placed over the active
surface to assure extra protection during shipment. Precision Monolithics dice provide the highest performance
available coupled with lowest overall finished costs.
For price and delivery information or quotations for special
devices, contact the nearest PMI sales office or representative listed in the back of this catalog.
TRIPLE PASSIVATION
MECHANICAL INFORMATION
Triple Passivation is a three-step process which provides
superior reliability and protection for all Precision Monolithics integrated circuits. First, a specially treated thermal
silicon dioxide layer is grown. This protects the junctions
and also attracts any residual ionic impurities to the top
surface of the oxide, where they are held fixed. Next, a layer
of silicon nitride is applied to prevent the entry of any poten-
VISUAL CRITERIA
A = MIL-STD-883, Method 2010.2,
Test Condition A.
B = MIL-ST0-883, Method 2010.2,
Test Condition A.
C = PMI "c" Visual, Based on MILSTD-83, Method 2010. Issued
1 May 1968.
DIMENSIONS
All dimensions are nominal and in mils (10-3 inches). Die
thickness is 8 mils min. to 22 mils max.
METALLIZATION
Aluminum metallization with a nominal thickness of 10,000
angstroms is standard for all devices.
BONDING PADS
Minimum bonding pad size is 4.0 mils x 4.0 mils for all
EMITIER
BASE
devices.
COLLECTOR
TESTING
VISUAL INSPECTION
All dice are 100% visually inspected to the applicable visual
criteria per MIL-STD-883, Method 2010, Test Condition B.
Devices with visual inspection to MIL-STD-883 Method 2010
Test Condition A are available on special order only.
ELECTRICAL TESTING
tial contamination or impurities. The third step is the thick
glass overcoat layer which leaves only the bonding pads
exposed. This "glassivation" protects the die from damage
during assembly and is especially important in minimizing
yield loss during shipment and assembly of dice for hybrid
circuits.
All dice are 100%. tested to the +25°C DC specifications
listed in the data sheet section of this catalog. Sample
assembly and testing in standard packages to specified
LTPO of units from customer's dice lot are available at extra
cost.
ASSEMBLY PROCEDURES
ORDERING INFORMATION
All PMI dice are available with either plain backing, orat extra
cost, 3000). minimum alloyed gold backing. Electrical performance is specified at 25° C for all products in the data
sheet section of this catalog. Visual inspection criteria is as
listed below:
Proper shipping and storage, die attachment, and bonding
are required to take advantage of the full performance built
into PMI devices, PMI provides this information but cannot
assume responsibility 'for technology and interface problems in applying dice, nor guarantee results in using the
suggested processing methods; this information is for user
assistance only and is to be used at the user's own discretion.
PAGE 2-4
STORAGE
Assembly begins with storage, because dice which are
metallized with aluminum will slowly oxidize if exposed to
air. This action is very slow, but eventually a thin layer of
aluminum oxide will form on the bonding pads. To keep
oxidation to a minimum, PMI dice are stored in a temperature
and humidity controlled nitrogen atmosphere at the factory
until shipment.
Oxidation is a more serious problem with thermal compression gold ball bonding than it is with ultrasonic aluminum
wire bonding. Ultrasonic aluminum wire bonding can penetrate a thicker layer of aluminum oxide than gold ball bonding. If thermal compression gold ball bonding is used, the
devices should be bonded within a few weeks after shipment.
Storage under dry nitrogen conditions is highly recommended for dice to be used with either type of bonding.
evidence of balling or flaking of die-attach material. After
completing the die-attach operation remove the package
from the heater block.
The die should be level and flat with respect to the package
surface. Die attach material should not touch the top surface
of the die or stand vertically above the edge of the die.
z
CONDUCTIVE EPOXY DIE ATTACHMENT
A solvent and other contaminant-free conductive epoxy
should be used, specifically designed for die-attach use.
Manufacturer's instructions should be carefully followed.
While PMI uses eutectic die-attach exclusively, conductive
epoxy die-attach can be used, although this technique is not
as well-established.
Protection during shipment is provided by the waffle-pack
carrier and its antistatic shield and cushioning strip. In addition the waffle pack is vacuum-sealed in a polyethylene bag.
EUTECTIC DIE ATTACHMENT CONDITIONS
The die-attach area of the package should be gold plated.
While preforms are not generally required, they may be
necessary in some cases depending on die size and the
thickness olthe package's gold plating. If required, preforms
of approximately 0.65 or 0.90 mm diameter with a composition of gold-silicon 98/2 are recommended.
The heater-block used should have a sufficiently large thermal mass plus adequate control to assure a constant package temperature of 420°C ±10°C during the die-attach
operation. Inert gas protection, nitrogen with a flow of
approximately 30 liters/hour, is also recommended.
For ease of handling in die attachment, dice should first be
transferred from their waffle packs to flat glass or metal
plates. Allow the package to soak a sufficient time to acquire
a uniform temperature. (Where necessary place a preform on
the mounting surface.)
Using suitable tweezers, carefully pick up the die from the
supply plate, orient properly and gently scrub in a circular or
back-and-forth motion until eutectic melt is visible completely around the die. Eutectic melt should be visible completely around the periphery of the die. There should be no
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PMI uses ultrasonic aluminum wire bonding and recommends its use for best performance. It is also more economical than gold-ball bonding. For specific procedures with
either method, the detailed operation instructions of the
manufacturer of the specific bonding equipment used should
be carefully followed. Asuitable wire for ultrasonic bonding
is Aluminum-Silicon alloy 99/1, Diameter 0.001", elongation
0.5 - 2% tensile strength 14 -16g; but again, specific instructions/recommendations related to the bonding equipment
used should be observed. An average bond pull strength of 4
- 6g, and a minimum limit of 2g should be maintained to
assure mechanical bond quality.
UNUSED PADS
All pads marked with (+) are not to be bonded to by user.
These pads are used by the factory for testing or adjusting
(zener zap) electrical parameters.
QUALITY ASSURANCE
EUTECTIC DIE ATTACHMENT PROCEDURE
o
~
II:
ULTRASONIC ALUMINUM WIRE BONDING
SHIPPING
•
Precision Monolithics believes that quality and reliability
must be built into the product; no amount (If testing can
replace these inherent properties. For this reason, devices
are fabricated and processed to MIL-STD-883 requirements
as standard practice with many exclusive processes and
controls added to improve quality and reliability. The integrity of aluminum metallization is confirmed by sampling
wafer lots using a Scanning Electron Microscope (SEM)
examination per Method 2018 specifications. QA testing of
dice is provided by normal production testing of packaged
devices.
PAGE 2-5
QUALITY
ASSURANCE
PROGRAM
a.A. PROGRAM
INDEX
PRODUCT
TITLE
PAGE
a.A. Program ....................•..•..•.......... :....................................... 3-3
PAGE 3-2
QUALITY ASSURANCE
PROGRAM DOCUMENTATION
By Howard Autry, VF¥QA
• CLASS B - Devices inteded for use where maintenance
and replacement can be performed, but are
difficult and expensive, and where reliability is
vital.
INTRODUCTION
Precision Monolithics, Inc., in establishing standard procedures for Manufacturing, Screening, Qualification, and Conformance, has incorporated the requirements of both MILSTD-883, and MIL-Q-9858. Devices meeting Class B screening requirements of MIL-STD-883, are available off-the-shelf
as standard catalog items. Requests for devices with Class S
or other special requirements are invited. The internal procedures designed to control and guarantee production ofthese
devices are described herein.
• CLASS C - Devices intended for use where maintenance and replacement can be readily accomplished and down time is not a critical factor.
Screening procedures for all 3 classes and for Precision
Monolithics standard devices are shown on the following
page.
PMI standard "883" parts designate devices which have been
subjected to 100% screening in accordance with Method
5004 of MIL-STD-883, Class B, and have been subjected to
Group A Quality Conformance Testing per Method 5005.
All PMI standard products (excapt PM series and plastics)
are screened In accordance with Method 5004 of MIL-STD883, clas. C or better,·
Complete Quality Conformance Testing (Groups A, B, C, D)
in accordance with Method 5005 of MIL-STD-883 is available
on special order.
QUALIFICATION AND QUALITY CONFORMANCE
PROCEDURES
MIL-STD-883 Method 5005 establishes Qualification and
Quality Conformance Procedures for the 3 classes of devices
and divides these procedures into group A, B, C and D tests:
"The full requirements of group A, B, C and 0 tests and
1) Generic Group C & 0 Quality Conformance Data is available on special order. Generic Test Data is defined in
accordance with D.E.S.C. selected item drawings as data
STANDARD MANUFACTURING PROCEDURE FOR ALL DEVICES
I
I
l
INCOMING MATERlALIN"«TlON
SAMPLING PER MILoSTD·106 OR
I I ''''
•
I I
•
COLORMETRIC IN"'ECTION
TO GUARANTEE SILICON NITRIDE
CAPACITOR DiElECTRIC THICKNESS
MIL-M-385,O
•
•
WAFER FABRICATION
100'lI0 MASK ALIGNMENT
IN PROCESS INSPECTION
•
I
100% OXIDE REMOVAL
IN PROCESS INSPECTION
I
100% DifFUSION
TEMPERATURE
PROfiLE INSPECTION
•
I
I
I
I
I
o.A. SAMPLE WAFER INSPECTION
I
J
SCANNING ElECTRON MICRosco""l
ISEMI MONITOR PER
METHOD 2018
ISAMPLE BASIS OR AS REQUIREDI
I ..,. •
ElECTRICAL PROBE
OF FINISHED WAFER TO IDENTIFY
DICE THAT DO NOT MEET
i
I
I
I
I I
ELECTRICAL REOUIREMENTS
+
I
WAFER SAW
AND BREAK
TO SEPARATE DICE
I
REMOVAL Of
ELECTRICAL REJECTS
•
I
from devices In the same microcircuit group (3.1.3(h) of
MIL-M-38510) and package type, produced within 180
days of the deliverable devices.
SCREENING LEVELS
MIL-STD-883 DEFINES 3 LEVELS OF MICROELECTRONIC
SCREENING:
• CLASS S - Devices intended for use where maintenance and replacement are extremely difficult
or impossible, and reliability is imperative.
'EFFECTIVE DATE CODE 8101.
I
I
I
I
l
I
100% VISUAL DIE INSPECTION
UNDER HIOH MAGNIFICATION
•
,
,
QUALITY MONITOR
DIE ATTACHMENT
ULTRASONIC LEAD BONDING
•
QUALITY MONITOR
+
,
SeAL
SCREENING PROCEOURES
I
I
I
I
I
I
I
inspections are Intended for use In Initial device qualification,
requaliflcatlon in the event of product or process change and
periodic testing for retention of qualification. Group A and B
tests and inspections are intended for quality conformance
inspection of individual inspection lots as a condition for
acceptance for delivery."
Group A, B, C and D quality conformance tests are performed using a sample size determined from the LTPD table
below. An initial sample size corresponding to zero rejects
(an acceptance number of 0) is normally used; if necessary
the sample size will be increased once to a higher number to
meetthe LTPD requirementforthe class of device under test.
PAGE 3-3
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SCREENING PROCEDURES
MIL-STD-8B3
METHOD 5004
CLASS S
MIL-STD-883
METHOD 5004
CLASS 8
Mll-STD·883
METHOD 5004
CLASS C
PMI STANDARD
DEVICES
PRESEAL INTERNAL
VISUAL METHOD 2010
DT
a.
A. SAMPLE
INSPECTION
STABILIZATION BAKE
METHOD 1008
CONDITION C (24 HRSI
TEMPERATURE CYCLING
METHOD 1010
CONDITION C
CONSTANT ACCELERATION
METHOD 2001
CONDITION E Yl PLANE
SEAL METHOD
1014
CONDITION A III C
FINAL ELECTRICAL
TEST AT 25Q C
NOTES:
1.
TEMP TESTING PERFORMED AS REQUIRED TO GUARANTEE DATA SHEET
SPECIFICATIONS.
*AS REQUIRED BY DETAIL SPEC.
BURN-IN PERFORMED AS REQUIRED TO STABILIZE DEVICES WITH INTERNAL REFERENCES.
LOT TOLERANCE PERCENT DEFECTIVE (LTPD) TABLE (per MIL-M-38510)
ACCEPTANCE
NUMBER"
LTPD 20
LTPD 15
0
1
2
3
4
11
18
25
32
38
15
25
34
43
52
LTPD 10
LTPD7
Minimum Sample Size
22
38
52
65
78
*Maximum allowable number of failures.
PAGE 3-4
32
55
75
94
113
LTPD5
LTPD3
45
76
129
176
221
265
77
105
132
158
GROUP A ELECTRICAL TESTS:
Reference MIL-STD-883 Method 5005
(ELECTRICAL TESTS PER APPLICABLE DATA SHEET SPECIFICATIONS)
SUBGROUP
1
TEST DESCRIPTION
Static tests at 25° C
Static tests at maximum rated operating temperature
Static tests at minimum rated operating temperature
Dynamic tests at 25°C
Functional tests at 25° C
Switching tests at 25° C
2
3
4
7
9
CLASSS .. B
LTPD
CLASSC
LTPD
5
7
7
5
5
7
5
10
10
5
5
10
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GROUP B TESTS FOR CLASS S DEVICES 1/
MIL-STD-883
TEST
Subgroup 1
(a) Physical dimensions
(b) I nternal water vapor content
Subgroup 2
(a) Resistance to solvents
(b) I nternal visual for DPA
(c) Bond Strength
(1) Ultrasonic
(d) Die shear test
Subgroup 3
Solderability 3/
Subgroup 4
Lead integrity
Seal
(a) Fine
(b) Gross
Lid torque
METHOD
CONDITION
2016
CLASSS
QUANTITY/(ACCEPT NO.)
OR LTPD
2(0)
3(0) or 5(1)
4/51
2/
2015
2013 &
2014
Failure criteria from design and
construction requirements of
applicable procurement document.
4(0)
2(0)
2011
(1) Test Condition D
Per Table 1 of Method 2019 for
the applicable die size
LTPD=10 6/
3(0)
2003
Soldering temperature of 260° C
±10°C
LTPD=15
2004
1014
Test Conditions B2, lead fatigue
A1 and C
2(0)
2024
5/
2019
Subgroup 5
(1) Electrical parameters
(2) Steady state life test
1005
(3) Seal
(a) Fine
(b) Gross
(4) Electrical parameters
1014
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Group A, Subgroups 1, 2, 3:
Read and record, subgroups 4,
7, 9 attributes.
Condition B, 125°C, 1000 HR or
150° C, 184 HR.
A1 and C
Group A, Subgroups 1, 2, 3:
Read and record, subgroups 4,
7, 9 attributes.
NOTES:
1. Electrical reject devices from the same Inspection lot may be used for all
subgroups when end pOint measurements are not required.
2. For Class S lot quality conformance testing, all samples for Subgroup B2
must have been through the complete sequence of Subgroup B6 tests.
3. All devices must have been through the temperature/time exposure in
burn-in. The LTPD applies to the number of leads Inspected except In no
LTPD=5
case shall less than three devices be used to provide the number of leads
required.
4. Not required If Group D performed on same lot.
5. Glass frlt sealed devices only.
6. LTPD refers to the number 01 wires to be pulled from a minimum of four
devices.
7. Required for initial qualification or redesign only.
PAGE 3-5
GROUP B TESTS FOR CLASS S DEVICES (Continued)
TEST
METHOD
MIL-STD-ee3
CONDITION
1010
2001
1014
Group A, Subgroups 1, 2, 3:
Read and record
Condition C 100 cycles/min.
Test Condition E: V, axes
Test Condition A, and C
Subgroup 6 2/
(a) Electrical parameters
(b) Temperature cycling
(c) Constant acceleration
(d) Seal
(1) Fine
(2) Gross
(e) Electrical parameters
Subgroup 7 71
(a) Electrical parameters
(b) Electrostatic discharge
sensitivity
(c) Electrical parameters
CLASSS
QUANTITY/(ACCEPT NO.)
OR LTPD
LTPD=15
Group A, Subgroups 1, 2, 3:
Read and record
Group A, Subgroup 1
3015
Test Condition A or B
Group A, Subgroup 1
NOTES:
,. Electrical relect deviceslrom the same Inspection lot may be used lor all
subgroups when end point measurements are not required.
2. For Class S lot quality conlormance tasting, all sampleolor Subgroup B2
must have been through the complete sequence 01 Subgroup B6 teots.
3. All devices must have been through the temperatureltlme exposure In
burn-In. The LTPD applies to the number 01 leads Inspected except in no
15(0)
case shall less than three devices be used to provide the number 01 leads
required.
4. Not required II Group 0 performed on same lot.
5. Glass frit sealed devices only.
6. LTPD relers to the number 01 wires to be pulled Irom a minimum 01 lour
7.
devices.
Required lor initial qualification or redesign only.
GROUP B TEST FOR CLASSES BAND C 11
TEST
Subgroup 1
Physical dimensions
METHOD
MIL-STD-ee3
CONDITION
CLASSES B&C
LTPD
QUANTITY/(ACCEPT NO.)
2 devices (No
2016
failures)
Subgroup 2
Resistance to solvents
4 devices (No
2015
failures)
Subgroup 3
Solderability 3/
2003
Soldering temperature of 260· C
15
±10·C
Subgroup 4
Internal visual and mechanical
SubgroupS
Bond strength 21
Ultrasonic or wedge
Subgroup 7
Seal
(a) Fine
(b) Gross
2014
Failure criteria from design and
construction requirements of
applicable procurement document.
2011
1 device (No
failures)
15
Test Condition D
5
1014
e
Subgroup 4/
(a) Electrical parameters
(b) Electrostatic discharge
sensitivity
(c) Electrical parameters
Group A, Subgroup 1
3015
Test Condition A or B
Group A, Subgroup 1
NOTES:
,. Electrical reject devices Irom the same Inspection lot may be used lor all
burn-in. The LTPD applies to the number 01 leads Inspected except In no
case shall less than three devices be used to provide the number 01 leads
subgroups when end point measurements are not required.
2. LTPD relers to number 01 wires to be pulled Irom a minimum 014 devices.
3. All devices must have been through the temperature/time exposure In
15(0)
required.
4. Required lor initial qualillcatlon or redesign only.
PAGE 3-8
GROUP C (DIE-RELATED TESTS) FOR CLASSES BAND CONLY
MIL-STD-883
TEST
CONDITION
METHOD
LTPD
Subgroup 1
Steady state life test 11
End point electrical parameters
Subgroup 2
Temperature cycling
Constant acceleration
Seal
(a) Fine
(b) Gross
Visual examination
End point electrical parameters
1005
Test Condition B (1000 hours, +125°C) or
(184 hours, +150°C)
As specified in the applicable device specification
1010
2001
1014
Test Condition C
Test Condition E min. Yl axis
Test Condition Al and C
5
II
15
:::E
0(
a:
"a:
0
21
Q,
1&1
As specified in the applicable device specification
0
Z
NOTES:
1. See 40.4 of Appendix B of MIL-M-38510 and 3.1 of Method 1005.
0(
a:
2. Visual examination shall be in accordance with method 1010 or 1011.
:l
III
III
0(
>
I-
::i
0(
:l
0
GROUP D (PACKAGE RELATED TESTS) FOR ALL CLASSES
MIL-STD-883
TEST
METHOD
CONDITION
LTPD
Subgroup 1
Physical dimensions
Subgroup 2
Lead i nteg rity
Seal
(a) Fine
(b) Gross
Lid torque 41
Subgroup 3 11
Thermal shock
Temperature cycling
Moisture resistance
Seal
(a) Fine
(b) Gross
Visual examination
End point electrical parameters
2016
2004
1014
15
Test Condition B2 (lead fatigue)
Conditions Al and C
2024
1011
1010
1004
1014
Test Condition B as a minimum, 15 cycles
minimum
Test condition C, 100 cycles minimum
15
Condition Al and C
Per visual criteria of method 1004 and 1010
As specified in the applicable device specification
NOTES:
1.
2.
Devices used in subgroup 3, "Thermal and Moisture Resistance" may be
used in subgroup 4, "Mechanica''',
Visual examination shall be in accordance with method 1010 at a magnifica-
3. Visual examination shall be performed In accordance with method 2007 for
evidence of defects or damage to case, leads, or seals resulting from
tion of 5X to lOX.
4. Glass frit sealed devices only.
testing (not flxturlng). Such damages shall constitute a failure.
PAGE 3-7
GROUPD (PACKAGE RELATED TESTS) FOR ALL CLASSES (Continued)
MIL-STD-883
TEST
Subgroup 4 1/
Mechanical shock
Vibration variable frequency
Constant acceleration
Seal
(a) Fine
(b) Gross
Visual examination
End point electrical parameters
Subgroup 5
Salt atmosphere
Seal
(a) Fine
(b) Gross
Visual examination
Subgroup 6
Internal water - vapor content
Subgroup 7
Adhesion of lead finish
CONDITION
METHOD
2002
2007
2001
1014
LTPD
Test Condition B
Test Condition A
Test Condition E, Yl axis
Condition Al and C
15
3/
As specified in the applicable device specification
1009
Test Condition A
1014
Condition Al and C
Per visual criteria of method 1009
1018
5,000ppm max water content at 100' C
2025
1010 or 1011
NOTES:
1. Devices used In subgroup 3, "Thermal and Moisture Resistance" may be
used In subgroup 4, "Mechanical",
2. Visual examination shall be in accordance with method 1010 at a magnification of5X to lOX,
15
3 Devices
(0) Failure
5 Devices
(1) Failure
15
3, Visual examination shall be performed in accordance with method 2007 for
evidence of defects or damage to case, leads, or seals resulting from
testing (not fixturing). Such damages shall constitute a failure.
PMI STANDARD PRODUCT FLOW FOR:
PM SERIES AND PLASTIC PACKAGED DEVICES.
...
,
LTPO"5
"
..
LTPD=5
LTPD"'6
...
,
,,,",
LTPD=5
NOTE: TEMP TESTING PERFORMED AS REQUIRED TO GUARANTEE DATA SHEET SPECIFICATIONS.
SEAL TEST NOT APPLICABLE TO PLASTIC PACKAGED DEVICES.
PAGE 3-9
PMI MIL-STD-883 CLASS B SCREENING AND QUALITY CONFORMANCE TESTING·
LTPD
m
5
100%
II
100%
100%
:IE
C
II:
CJ
0
LTPD"S
100%
II:
D.
III
U
Z
C
II:
100%
100%
:)
II)
II)
C
100%
....:::;>C
:)
0
100%
EVERV
INSP
LOT
100%
100%
* Applicable
to all standard "883" grade devices.
PAGE 3-9
I.C. CROSS
REFERENCE
I.C. CROSS REFERENCE
INDEX
PRODUCT
PAGE
TITLE
Analog Devices ••..••.•..•••.•••••••..••••.••••.••••.•....•..••....•••.••••••...•.••••..••• 4-3
Advanced Micro Devices .••.•.••.••••••••...•••....••.•...•.•.••...••..•.••.•...•.••••••••• 4-4
Burr Brown ••••••••.••••.••••..•••.••.•.•••.•.••••.•••..•••••••••••.••..•....••••••••••.•• 4-5
Datel .•••••••••••••••••.•••••..••••.....•.....••..•••••.••.•..•••...•..••.••••.•••.....••• 4-6
Fairchild ................................................................................... 4-7
Harris .••....•.....•••...•••..••••..••••••.••••••.••..•.••.••••...•••.•••••••..•...••.••••• 4-7
Hybrid ••.••••••..••....•...•.•.•...••••.•••••.••••.•••••••••••••••..•.•..•..•••.•••••••..• 4-8
Intersil •••••••••.••••••••..•••...••.•..•.•.....••...••••..••.•.•.•.•.•..••.••••••••..•.•••• 4-8
Micro Networks ••..•....•.••.•••••.••••••.•••••.•••..••••.••.•.•••••••••.•.••••..•••••••.• 4-9
Motorola •.••••..•.....••...•.•••.•.•••.•••••••••••••.••••.•••••.••..••...•..•••.•••••••.•• 4-9
National Semiconductor ••.....•...•••..•••.•..••••.•••••.••...••••.•••.•..•••••••••.•...• 4-10
Raytheon .••••.••••..•••.••••.....•....••••...•.••.••.••.•.....•.......••••••..••.•..•..• 4-11
RCA •...••••• , •••..••••..•••••.••••....••.......•.•..••.•..........•..••.••........•..••• 4-12
Signetics ..•..••....••.•..•.•..•••••.••••...•••.••.•..••••.•••••••••••••..•.•..••.•••.•••• 4-12
Siliconix .•.••..••••...••....•.....••....•.•..•..•..•••...•....•.....•..••.•••.••••....... 4-13
Texas Instruments •..••••••.••.•..••....•...............•..•..•.•...•..••.•••...•.•.•...•• 4-13
PAGE 4-2
IC CROSS REFERENCE
The following tables show both direct and functional equivalents to other manufacturers' devices. Performance and functionality
are ·similar for functional replacements although electrical and mechanical specifications differ. Pin-for-pin equivalents are
similar in electrical performance and are direct, plug-in replacements.
ANALOG
DEVICES
PIN-FOR-PIN
EQUIVALENT
AD DAC08
DAC-08
AD07
OP-07
AD101
OP-18
PMINEAREST
FUNCTIONAL
EQUIVALENT
PMI
DIFFERENCES
a
w
ADG200
(,)
ai
No DC balance capability. Prime grade has O.5mV Vos
and 8p.Vlo C TCVos.
Bipolar, immune to static electricity.
SW-05
II:
W
II.
W
II:
rn
rn
o
II:
ADG201
SW-201/SW-01
AD381
OP-15
Use SW-01 for temperature compensated RON.
AD503
OP-15
TCVos of 5p.VloC offset null to V+.
AD504
OP-05
Nulled.
AD507
TCVos = 5p.Vlo C.
OP-16/0P-17
AD509
OP-16
Fast settling.
AD510
oP-05/0P-07
Unnulled. O.6p.VloC TCVos. Pin compatible.
AD517
OP-21/0P-07
350p.A power consumption. Pin compatible. O.6p.VloC
TCVos. Pin compatible
AD518
OP-01
Inverting configuration only. 2mV, Vos, 8p.VloC TCVos.
AD540
OP-15
O.5mV, Vos, 5p.VloC, TCVos. Offset null to V+.
AD542
OP-15
O.5mVlVos offset null to V+.
AD544
OP-15
Offset null to V+.
AD545
OP-15
10Vlp.s slew rate.
AD558
DAC-888
Multiplying, faster.
AD559
DAC-08
Multiplying.
AD561
DAC-100/DAC-101
Not pin-for-pin.
AD580
REF-02
+5V reference.
AD581
REF-01
AD582
SMP-10
Faster acquisition time.
AD583
SMP-10/SMP-11
Very low droop rate. Pin compatible in unity gain
configuration.
AD590
REF-02
Has pin providing output voltage proportional to
temperature.
PAGE 4-3
(,)
~
ANALOG
DEVICES
PIN-FOR-PIN
EQUIVALENT
AD741
OP-02
ADS10
MAT-01
ADS1S
PMINEAREST
FUNCTIONAL
EQUIVALENT
PMI
DIFFERENCES
See MAT-01 Selection Guide.
MAT-01
Log amplitude.
AD2700
REF-01
IC and low power.
AD7110
DAC-7S
DAC-7S has higher resolution.
AD7501
MUX-OS
Immune to static electricity.
AD7502
MUX-OS
Immune to static electricity.
AD7503
MUX-OS
Immune to static electricity. Inverted enable logic.
AD140S/150S
DAC-140S/150S
AD7506
MUX-16
Immune to static electricity.
AD7507
MUX-2S
Immune to static electricity.
AD7510
SW-7510
Immune to static electricity.
AD7511
SW-7511
Immune to static electricity.
AD7516
SW-7510
Wider analog signal range.
AD75201753017533
DAC-1O
Bipolar, high compliance.
AD7524
DAC-SOS/DAC-SSS
Bipolar.
HDH OS02
DAC-20S
Monolithic, low cost, slower.
'HDH 1003
DAC-210
Monolithic, low cost, slower.
HDH 1025
DAC-10
Monolithic, low cost, slower.
FET Op-Amps
OP-15/0P-16/0P-17
Select according to application.
PMINEAREST
FUNCTIONAL
EQUIVALENT
PMI
DIFFERENCES
ADVANCED
MICRO DEVICES
PIN-FOR-PIN
EQUIVALENT
AM140S
DAC-140S
AM150S
DAC-150S
AM6012
DAC-312
AM6070
DAC-76
DAC-OS
DAC-OS
SSS725
OP-06
SSS741
OP-02
PAGE 4-4
PMINEAREST
FUNCTIONAL
EQUIVALENT
PMI
DIFFERENCES
AM685
CMP-05
Lower Error.
AM686
CMP-05
Lower Error.
AM687
CMP-05
Lower Error.
AM6071
DAC-89
Improved Specs.
AM6072
DAC-88
Improved Specs.
w
w
!&.
w
AM6080
DAC-888
Faster.
UI
UI
ADVANCED
MICRO DEVICES
PIN-FOR-PIN
EQUIVALENT
SS8747
OP-03/0P-04
S881508
DAC-1508
II
w
U
Z
a:
a:
0
a:
u
~
PMINEAREST
FUNCTIONAL
EQUIVALENT
PMI
DIFFERENCES
883500
OP-15
Vos 0.5mV. TCVos 5p.VJo C.
883501
OP-15
Null to V+. f t = 4MHz
883505
OP-16
Highest speed applications.
883506
OP-15/0P-16/0P-17
Medium speed application. Depends on
configuration.
883510
OP-07
Pin compatible. 25p.V. Vos.
883521
OP-15
Null to V+. 10VJp.s slew rate.
883522
OP-15
Null to V+. 10VJp.s slew rate.
883542
OP-15
Null to V+. 10VJp.s slew rate.
883550
OP-15
Null to V+. 10VJp.s slew rate.
DAC-82
DAC-208
Different REF. faster response.
BURR-BROWN
PIN-FOR-PIN
EQUIVALENT
MPC4D
MUX-24
High immunity to static electricity.
MPC8D
MUX-28
High immunity to static electricity.
MPC8S
MUX-08
High immunity to static electricity.
MPC16S
MUX-16
High immunity to static electricity.
SHC298
SMP-10/SMP-11
PAGE 4-5
Specified zero-scale error.
PMINEAREST
FUNCTIONAL
EQUIVALENT
DATEL
PIN-FOR-PIN
EQUIVALENT
PMI
DIFFERENCES
MV-SOS
MUX-OS
High immunity to static electricity.
MV-1606
MUX-16
High immunity to static electricity.
MVD-409
MUX-24
High immunity to static electricity.
MVD-S07
MUX-2S
High immunity to static electricity.
MX-SOS
MUX-GS
High immunity to static electricity.
MX-1606
MUX-16
High immunity to static electricity.
MXD-409
MUX-24
High immunity to static electricity.
MXD-S07
MUX-2S
High immunity to static electricity.
SHM-IC-1
SMP-10/11
Pin-for-pin replacement in unity gain configuration.
SHM-LM-2
SMP-10/11
Improved input specifications.
DAC-19SB
DAC-20S
Monolithic, faster.
DAC-9SBIR
DAC-100
Monolithic, faster.
DAC-9SBI
DAC-10
Monolithic, faster.
DAC-19SBI
DAC-OS
Monolithic, faster.
DAC-29S8
DAC-20S
Monolithic, faster.
DAC-4910B
DAC-210
Monolithic, faster.
DAC-4910BI
DAC-10
Monolithic, faster.
DAC-IS8
DAC-OS
Monolithic, faster.
DAC-110B
DAC-10
Monolithic. faster.
DAC-UPS8
DAC-SSS
Multiplying, faster.
DAC-IC108
DAC-10
Faster.
DAC-VS8
DAC-20S
Faster, monolithic.
DAC-V108
DAC-210
Faster, monolithic.
DAC-ICS8C/8M
DAC-150S/140S
DAC-OSBC/BM
DAC-OS
PAGE 4-6
PMINEAREST
FUNCTIONAL
EQUIVALENT
FAIRCHILD
PIN-FOR-PIN
EQUIVALENT
PMI
DIFFERENCES
LM108
PM-108/0P-08
LM208
PM-208/0P-08
LM308
PM-308/0P-08
725
OP-06
741
PM-741/0P-02
1&1
747
PM-747/0P-04
1&1
II
CJ
Z
II:
801
DAC-08
1&1
IL
1&1
802
DAC-1508
In
In
714
OP-07
I'A155/6/7
PM-155/6/7
OP-15/16/17
II:
0
CJ
~
II:
I'A255/6/7
PM-255/6/7
o P-15/16/17
I'A355/6/7
PM-355/6/7
OP-15/16/17
HARRIS
SEMICONDUCTOR
PIN-FOR-PIN
EQUIVALENT
PMINEAREST
FUNCTIONAL
EQUIVALENT
PMI
DIFFERENCES
HA-2420
SMP-10/SMP-11
Pin compatible in unity gain configurations.
HA-2425
SMP-10/SMP-11
Pin compatible in unity gain configurations.
HA-2510
OP-16
PMI's OP-15/16/17 replaces several Harris types in
some applications.
HA-2720
OP-20
Improved DC specs.
HA-2900
OP-07
See also AN-13.
HA-4950
CMP-05
Superior input specifications.
HA-4900
CMP-04
Single supply operation
HA-4905
CMP-04
Single supply operation
HI-201
SW-201
Use SW-01 for temperature compensated RON.
HI-200
SW-05
Over voltage protected.
HI-506
MUX-16
Over voltage protected.
HI-506A
MUX-16
Lower RON.
PAGE 4-7
PMINEAREST
FUNCTIONAL
EQUIVALENT
HARRIS
SEMICONDUCTOR
PIN-FOR-PIN
EQUIVALENT
HI-S07
MUX-2B
Over voltage protected.
HI-S07A
MUX-2B
Lower
HI-SOB
MUX-OB
Over voltage protected.
HI-SOBA
MUX-OB
Lower
HI-S09
MUX-24
Over voltage protected.
HI-S09A
MUX-24
Lower
PMI
DIFFERENCES
RON'
RON'
RON'
HI-1B2BA
MUX-24
Lower leakage currents.
HI-S610
DAC-10
1B-Pin package, similar specs/speed.
HI-1818A
MUX-08
Lower leakage currents.
HI-S618
DAC-08
16-Pin package, similar specs/speed.
PMINEAREST
FUNCTIONAL
EQUIVALENT
PMI
DIFFERENCES
DAC221M-10
DAC-10
Monolithic, laster.
DAC337C
DAC-D3
Monolithic, laster, flexible supplies.
DAC331-8
DAC-08
Faster, better specs.
DAC337
DAC-208
Faster, better specs.
DAC371
DAC-100
Faster, better specs, monolithic.
DAC371V
DAC-208
Faster, better specs, monolithic.
DAC372
DAC-208
Faster, better specs, monolithic.
DAC38S1
DAC-100
Faster, better specs, monolithic.
DAC331-10
DAC-10
Faster, better specs, monolithic.
DAC3721-10
DAC-100
Faster, better specs, monolithic.
DAC371-10
DAC-210
Faster, better specs, monolithic.
PMINEAREST
FUNCTIONAL
EQUIVALENT
PMI
DIFFERENCES
DAC-1O
Bipolar, high compliance/speed.
HYBRID
SYSTEMS
INTERSIL
PIN-FOR-PIN
EQUIVALENT
PIN-FOR-PIN
EQUIVALENT
AD7S20/30/33
IH200
SW-OS
Break-belore-make switching.
IH201
SW-201
Use SW-01 lor temperature compensated
PAGE 4-8
RON'
PMINEAREST
FUNCTIONAL
EQUIVALENT
I~TERSIL
PIN-FOR-PIN
EQUIVALENT
PMI
DIFFERENCES
IH202
SW-202
Use SW-02 for temperature compensated RON'
IH6006
MUX-16
Full TTL/CMOS logic compatibility.
IH6l08
MUX-08
Full TTL/CMOS logic compatibility.
IH6208
MUX-08/MUX-24
Full TTL/CMOS logic compatibility.
IH6216
MUX-28
Full TTL/CMOS logic compatibility.
•
III
U
Z
III
II:
III
I&.
III
II:
PMI NEAREST
FUNCTIONAL
EQUIVALENT
PMI
DIFFERENCES
II:
MN3013/3014
DAC-208
Monolithic, better specs.
~
MN300S/9
DAC-208
Monolithic.
MN3000/l/2/6
DAC-208
Monolithic, faster.
MN3003/4/5/7
DAC-2l0
Monolithic, faster.
MN3015
DAC-l0/DAC-l0l
Monolithic, faster.
MN3020
DAC-808
Current output.
MN3005
DAC-03
Monolithic, faster, flexible supplies.
MN3010
DAC-20
Monolithic, faster, more accurate.
MN3l00
DAC-l0
Monolithic, faster, flexible supplies.
PMINEAREST
FUNCTIONAL
EQUIVALENT
PMI
DIFFERENCES
MICRO
NETWORKS
PIN-FOR-PIN
EQUIVALENT
MOTOROLA
PIN-FOR-PIN
EQUIVALENT
MC1504U5
REF-02
MC1404U5
REF-02
MC1404Ul0
REF-Ol
MC1408
DAC-1408
MC1504Ul0
REF-Ol
MC1458
OP-14
MC1508
DAC-1508
MC1500U5
REF-02
MC1500Ul0
REF-Ol
MC1558
OP-14
PAGE 4-9
Ul
Ul
0
u
MOTOROLA
PIN-FOR-PIN
EQUIVALENT
MC1400U5
REF-02
MC1400U10
REF-01
PMINEAREST
FUNCTIONAL
EQUIVALENT
MC3502
OP-15/0P-16
MC3510
DAC-100/DAC-10
MC34022
OP-15/0P-16
MC3302
CMP-04
NATIONAL
SEMICONDUCTOR
PIN-FOR-PIN
EQUIVALENT
PMI
DIFFERENCES
Faster, higher compliance.
Improved specs.
PMINEAREST
FUNCTIONAL
EQUIVALENT
PMI
DIFFERENCES
DAC-10
Bipolar, high speed/compliance.
DAC1020
DAC-10
Bipolar, high speed.
DAC1220
DAC-312
Bipolar, high speed.
DAC1201
DAC-312
Current output, ext. ref.
AD7520
DAC0800/0801/0802
DAC-08
DAC0808/0807/0806
DAC-1408/1508
LF155
PM-155
LF156
PM-156
LM139
PM-139/CMP-04
Improved specs.
CMP-05
Improved input specs.
LF198/298/398
SMP-10/11
Low zero scale error.
LM199
REF-01/02
Lower power consumption.
LM161
LF157
PM-157
LF255
PM-255
LF256
PM-256
LF257
PM-257
LF356
PM-356
LF357
PM-375
LF11202112201/13201
SW-01
Use SW-02 for temperature compensated RON.
LF11202/12202/132P2
SW-02
Use SW-02 for temperature compensated RON.
LF11331/12331/13331
SW-04
Temperature compensated RON.
PAGE 4-10
NATIONAL
SEMICONDUCTOR
PIN-FOR-PIN
EQUIVALENT
LF11332/12332/13332
PMINEAREST
FUNCTIONAL
EQUIVALENT
PMI
DIFFERENCES
SW-03
Temperature compensated RON'
LF1150S/1250S/1350S
MUX-OS
Lower RON
LF11509/12509/13509
MUX-24
Lower RON
LHOO2
BUF-03
Improved DC accuracy.
LHOOO1
OP-20
Improved DC specs.
LHOO23
SMP-10/11
Low zero scale error.
III
w
U
Z
w
a:
w
w
a:
IL
LHOO33
BUF-03
Improved DC accuracy.
LHOO43
SMP-10/11
Improved speed and DC accuracy.
LHOO44
OP-07
Applications where less than 1mA supply current is
required.
LHOO53
SMP-10/SMP-11
Improved speed and DC accuracy.
LHOO70
REF-01
Low power dissipation.
LHOO71
REF-01
Low power dissipation.
LH210S
PM-210S/PM-210SA
LH220S
PM-220S/PM-220SA
LH230S
PM-230S/PM-230SA
LMDACOS
DAC-OS
LM10S/20S/30S
PM-10S/20S/30S
Improved Vas.
LM110/210/310
BUF-01/BUF-02
Total D.C. error lower.
LM114/115
MAT-01
See MAT-01 Selection Guide.
PMINEAREST
FUNCTIONAL
EQUIVALENT
PMI
DIFFERENCES
RAYTHEON
PIN-FOR-PIN
EQUIVALENT
LM10S
PM-10S/OP-OS
LM20S
PM-20S/OP-OS
LM30S
PM-30S/OP-OS
RC725
PM-725/0P-06
RC741
PM-74110P-02
RC747
OP-03/0P-04
RC145S
PM-145S/OP-14
RC4132
OP-20
PAGE 4-11
!II
!II
0
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PMINEAREST
FUNCTIONAL
EQUIVALENT
RAYTHEON
PIN-FOR-PIN
EQUIVALENT
RC4136
PM-4136/0P-09
RM725
PM-725/0P-06
RM741
PM-741/0P-02
RM747
PM-747/0P-03/0P-04
RM155S
PM-155S/0P-14
RM4136
PM-4136/0P-09
RM4132
OP-20
DACOS
DAC-OS
RCA
PIN-FOR-PIN
EQUIVALENT
CA10S
PM-10S
CA20S
PM-20S
CA30S
PM-30S
CA741
PM-741/0P-02
CA747
PM-'747/0P-03/0P-04
CA145S
OP-14
CA155S
PM-155S/0P-14
SIGNETICS
PIN-FOR-PIN
EQUIVALENT
MC140S/150S
PMI
DIFFERENCES
PMINEAREST
FUNCTIONAL
EQUIVALENT
PMI
DIFFERENCES
PMINEAREST
FUNCTIONAL
EQUIVALENT
PMI
DIFFERENCES
DAC-140S/150S/
DAC-OS
Improved replacement.
SMP-11
Improved performance.
NE/SE5534
OP-27/37
Lower noise, current out.
NE511S/5119
DAC-SSS
501S
DAC-SOS
NE5537
NE/SE5007/500S
DAC-OS
NElSE5009
DAC-08
1S-Pin package, current out.
PAGE 4-12
PMINEAREST
FUNCTIONAL
EQUIVALENT
SILICONIX
PIN·FOR·PIN
EQUIVALENT
DG200
SW-05
Over voltage protected.
DG201
SW-201
Lower RON.
DG211
SW-01
Temperature compensated RON.
DG300
DG506
PMI
DIFFERENCES
BIFET.
SW-05
MUX-16
Over voltage protected.
•
w
(J
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DG507
MUX-28
Over voltage protected.
DG508
MUX-08
Over voltage protected.
w
w
IL
w
DG509
MUX-24
Over voltage protected.
(/)
a:
a:
(/)
0
a:
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~
TEXAS
INSTRUMENTS
PIN·FOR·PIN
EQUIVALENT
SN52558
PM-1558/0P-14
SN52741
PM-741/0P-02
SN72747
PM-?47/0P-03/0P-04
SN72558
DAC-1458/0P-14
SN72741
PM-741/0P-02
SN72747
oP-03/0P-04
TL081
OP-16
TL085
OP-215
PMINEAREST
FUNCTIONAL
EQUIVALENT
PAGE 4-13
PMI
DIFFERENCES
OPERATIONAL
AMPLIFIERS
OPERATIONAL AMPLIFIERS
INDEX
PRODUCT
TITLE
OP-01
OP-02
OP-03
OP-04
OP-05
OP-06
OP-07
OP-08
OP-09
OP-10
OP-11
OP-12
OP-14
OP-15
OP-16
OP-17
OP-18
OP-19
OP-20
OP-21
OP-24
OP-27
OP-34
OP-37
OP-207
OP-215
OP-220
OP-227
OP-420
OP-421
PM108A
PM155A
PM156A
PM157A
PM725
PM741
PM747
PM1458/1558
PM2108A
PM4136
JM38510/10104
JM38510/10106
JM38510/11401
JM11402/114031
JM11404/11405/11406
Inverting High-Speed Operational Amplifier ...........................•...................... 5-8
High-Performance General-Purpose Operational Amplifier ................................... 5-14
Dual-Matched High-Performance Operational Amplifiers ........................•..........• 5-22
Dual-Matched High-Performance Operational Amplifiers (See OP-Q3) ........................ 5-22
Instrumentation Operational Amplifier ...................................................... 5-30
High-Gain Instrumentation Operational Amplifier ........................................... 5-39
Ultra-Low Offset Voltage Operational Amplifier ............................................. 5-47
Precision Low Input Current Operational Amplifier .......................................... 5-57
Quad-Matched 741-Type Operational Amplifier ....................•......................... 5-65
Dual-Matched Instrumentation Operational Amplifier ....................................... , 5-74
Quad-Matched 741-Type Operational Amplifier (See OP-09) •................................ 5-65
Precision Low Input Current Operational Amplifier .......................................... 5-85
Dual-Matched High-Performance Operational Amplifier (See OP-03) ......................... 5-22
Precision JFET Input Operational Amplifier ................................................. 5-90
Precision JFET Input Operational Amplifier ................................................. 5-90
Precision JFET Input Operational Amplifier ................................................. 5-90
High Performance General Purpose Externally Compensated Operational Amplifier .......... 5-104
High-Performance General-Purpose Operational Amplifier (See OP-02) ...................... 5-14
Micropower Precision Operational Amplifier ............................................... 5-112
High-Speed Low-Power Precision Operational Amplifier .................................... 5-118
Ultra-Low Noise Operational Amplifier ....................................•............... 5-122
Ultra-Low Noise Precision Operational Amplifier ........................................... 5-131
Ultra-Low Noise Operational Amplifier (See OP-24) ........................................ 5-122
Ultra-Low Noise Precision High-Speed Operational Amplifier ............................... 5-140
Ultra-Low Vas Dual Instrumentation Operational Amplifier .................................. 5-148
Dual Precision JFET Input Operational Amplifier ........................................... 5-155
Micropower Precision Dual Operational Amplifier .......................................... 5-162
Ultra-Low Noise, Low Offset Dual Instrumentation Operational Amplifier .................... 5-171
Quad Micropower Operational Amplifier ................................................... 5-182
High Speed, Quad Micropower Operational Amplifier ....................................... 5-188
Low Input Current Operational Amplifier .................................................. 5-194
Monolithic JFET Input Operational Amplifier ............................................... 5-197
Monolithic JFET Input Operational Amplifier ............................................... 5-197
Monolithic JFET Input Operational Amplifier ............................................... 5-197
Instrumentation Operational Amplifier ..................................................... 5-203
Compensated Operational Amplifier ....................................................... 5-206
Dual Compensated Operational Amplifier ................................................ " 5-208
Dual Compensated Operational Amplifier .................................................. 5-208
Low Input Current Operational Amplifier (See PM108A) .................................... 5-194
Quad 741-Type Operational Amplifier ...................................................... 5-211
JAN Single Low Input Current Operational Amplifier ....................................... 5-214
JAN Single Low Input Current Operational Amplifier ....................................... 5-217
PAGE
JAN JFET Input Operational Amplifier ..................................................... 5-220
PAGE 5-2
INTRODUCTION
At Precision Monolithics we introduced our first Op Amp in
1970 and since then we have constantly strived to meet the
needs of the electronic industry. PMI has done this by offering a complete and versatile series of operational amplifiers.
The Op Amp product line at PMI includes a variety of widely
accepted proprietary and second-source products. These
products are designed and manufactured from a diverse
technology base that inciudeslinear bipolar, super-beta, and
BIFET processing techniques along with Zener Zap trimming.
This technology base combined with superiordesign,layout,
and processing techniques provides products with outstanding performance and reliability. Single, Dual, and Quad
amplifiers are offered in plastic, metal and ceramic packages
in military, industrial, and commercial temperature ranges.
Over the past several years, the sophistication and diversity
required of op amps has increased dramatically. High speed,
high input impedance, low noise, and ultra low power have
been just a few of the many areas in which monolithic op
amps have made significant inroads. This has often made the
selection of appropriate operational amplifiers as difficult as
the design of a system using them. As with most designs,
over-specification can be costly and under-specification can
seriously affect system performance.
To overcome this problem, we've developed the selection
guides on the following pages. The simplified guide below
lists the basic application requirements for Op Amps and the
PMI amplifier family that is most likely to fill that requirement.
Consult the following pages for selection guides listing the
key performance parameters of the products in these families.
REQUIREMENTS
High Speed
Low Power Consumption
Low Input Offset Voltage
High Input Impedance
Stability with Time and Temp
Single Supply
Ultra High Gain
Matched Performance Duals
Matched Performance Quad
PRODUCT FAMILY
JFET Input, Audio/
Commercial
Super p, /LPower
Instrumentation
JFET Input, Super p
Instrumentation, Super p
/LPower
Instrumentation
Instrumentation Duals,
General Purpose Duals
General Purpose Quads
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PAGE 5-3
DEFINITIONS
AVERAGE BIAS CURRENT DRIFT (TCl a)
INPUT RESISTANCE-DIFFERENTIAL MODE (RIN)
The ratio of the change in the inputbiascurrentto the change
in temperature producing it.
The ratio of the small-signal change in input voltage to the
change in input current ateither inputterminal with the other
grounded.
AVERAGE OFFSET CURRENT DRIFT (TClos)
The ratio of the change in the input offset current to the
change in temperature producing it.
AVERAGE OFFSET VOLTAGE DRIFT (TCVos)
The ratio of the change in the input offset voltage to the
change in temperature producing it.
AVERAGE OFFSET VOLTAGE DRIFT WITH EXTERNAL
TRIMMING (TCVosw
The ratio of the change in the input offset voltage to the
change in temperature producing it, with the input offset
voltage trimmed to zero at room temperature.
INPUT VOLTAGE RANGE (IVR)
The range of input voltage for which the device will operate
linearly.
LARGE-SIGNAL VOLTAGE GAIN (Avo)
The ratio of the change in output voltage (over a specified
range) to the change in input voltage producing it.
OPEN-LOOP OUTPUT RESISTANCE (Ro)
The small-signal driving pOint resistance of the outputterminal with respect to ground at a specified quiescent dc output
voltage and current.
COMMON-MODE INPUT RESISTANCE (RlnCM)
OUTPUT VOLTAGE SWING (Va)
The ratio of the input voltage range to the change in input
bias current over this range.
The peak output voltage that can be obtained without
clipping.
COMMON-MODE REJECTION RATIO (CMRR)
POWER DISSIPATION (Pd )
The total power dissipated in the amplifier with the output at
zero volts with no load.
The ratio of the common-mode voltage range (CMVR) to the
peak-to-peak change in equivalent input offset voltage (CME)
over this range. CMRR is specified for a specific CMVR.
CMRR = 20 10910 (CMVR/CME)
POWER-SUPPLY REJECTION RATIO (PSRR)
The frequency at which the open-loop gain equals unity.
The inverse ratio of the change in input offset voltage to the
change in power supply voltage producing it. PSRR can be
specified in dB or p.v/V.
INPUT BIAS CURRENT (Ia)
SLEW RATE (SR)
The average ofthe cu rrents into the two input termi nals when
the output is at zero volts with no load.
The ratio of a change in output voltage to the minimum time
required to effect this change under large-signal drive conditions. Slew rate may be specified separately for positive and
negative-going changes.
GAIN-BANDWIDTH PRODUCT (GBW)
INPUT NOISE CURRENT (i np- p )
The peak-to-peak noise current within a specified frequency
band.
SUPPLY CURRENT (Isv)
The current required from the power supply to operate the
amplifier with no load and the output at zero volts.
INPUT NOISE CURRENT DENSITY (In)
The rms noise current in a 1Hz band centered on a specified
frequency.
UNITY-GAIN CLOSED-LOOP BANDWIDTH (BW)
INPUT NOISE VOLTAGE (8np.,.)
The frequency at which the magnitude of the small signal
voltage gain of the amplifier, operated closed-loop as a unitygain follower, is 3dB below unity.
The peak-to-peak noise voltage within a specified frequency
band.
INPUT NOISE VOLTAGE DENSITY (en)
The rms noise voltage in a 1Hz band centered on a specified
frequency.
MATCHING PARAMETER DEFINITIONS
INPUT OFFSET VOLTAGE MATCH (.:1Vos)
INPUT OFFSET CURRENT (los)
The difference between the currents into the two input terminals when the output is at zero volts with no load.
INPUT OFFSET VOLTAGE (Vos)
The voltage which must be applied between the input terminals to obtain zero output voltage with no load.
The difference between the offset voltages of side A and side
B (VOS A - Voss). If VOSA = Voss, the net differential offset
voltage at the output of the amplifier pair equals zero.
INPUT OFFSET VOLTAGE TRACKING (TC.:1Vos)
The ratio of the change in .:1Vosto the change in temperature
producing it.
PAGE 5-4
AVERAGE NON-INVERTING BIAS CURRENT (18+)
The average of the side Aand side B non-inverting input bias
currents:
IBA+ + IBB+
2
AVERAGE DRIFT OF NON-INVERTING OFFSET CURRENT
(TClos+)
The ratio of the change in non-inverting offset current to the
change in temperature producing it.
COMMON-MODE REJECTION RATIO MATCH
NON-INVERTING INPUT OFFSET CURRENT (105+)
The difference between the non-inverting input bias currents
of side A and side B; (I BA+ - I BB+).
(~CMRR)
The difference between the common-mode rejection ratios
(expressed in volt/volt) of side A and side B. ~CMRR in dB =
20 10glO (~CMRR in volt/volt).
SUPPLY-VOLTAGE REJECTION-RATIO MATCH
INVERTING INPUT OFFSET CURRENT (Ios-)
(~PSRR)
The difference between the inverting input bias currents of
side A and side B; (leA--IBEr).
The difference between the power-supply rejection-ratios
(expressed in volt/volt) of side A and side B. ~PSRR in dB =
20 10glO (~PSRR in volt/volt).
AVERAGE DRIFT OF NON-INVERTING BIAS CURRENT
(TCIB+)
CHANNEL SEPARATION
The ratio of the change in non-inverting bias current to the
change in temperature producing· it.
The ratio of the change in offset voltage of one channel tothe
change in output voltage in the second channel producing it.
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....
cz
PRODUCT SELECTOR - OPERATIONAL AMPLIFIERS
0
~
II:
Product
Offset
Voltage
(mV)
Bias
Current
(nA)
Offset
Current
(nA)
Drift
(p.Vl o C)
Bandwidth
(MHz)
SR
(Vlp.s)
Supply
Current
(mA)
0.7
0.5
0.5
0.5
5
30
30
50
50
500
2
2
5
5
200
8.0
8.0
8.0
8.0
30
2.5
0.8
6
0.8
0.8
18
0.25
0.25
0.8
0.25
3.0
2.4
3.0
3.0
2.8
0.5
0.5
0.5
2
2
2
0.11
0.13
0.13
0.15
0.19
0.19
.022
.025
.025
.040
.050
.050
5
5
5
5
5
5
4
6
20
2.5
4
15
10
18
45
3
10
40
4
7
7
4
7
7
0.15
0.2
0.025
0.025
0.025
±2
70
±2
±40
±40
2
2
2
35
35
0.5
0.6
0.6
0.6
0.6
0.4
1000
0.4
5.0
45
0.1
100
0.1
1.7
11
4
4
4
4.7
4.7
SINGLE OP AMPS
GENERAL PURPOSE
OP-01
OP-02
OP-18
OP-19
PM-741
JFETINPUT
OP-15
OP-16
OP-17
PM-155
PM-156
PM-157
INSTRUMENTATION
OP-Q5
OP-Q6
OP-Q7
OP-27
OP-37
PAGE 5-5
1&1
G.
0
PRODUCT SELECTOR - OPERATIONAL AMPLIFIERS
Offset
Voltage
(mV)
Bias
Current
(nA)
Offset
Current
(nA)
Drift
(,.V/·C)
Bandwidth
(MHz)
(V/,.s)
Supply
Current
(mA)
0.15
0.15
0.5
2
2
2
0.2
0.2
0.2
2.5
2.5
5
0.8
0.8
0.8
0.12
0.12
0.12
0.6
0.6
0.6
OP-20
OP-21
0.25
0.1
25
100
1.5
4.0
1.5
1.0
0.1
0.6
0.05
0.25
0.08
0.30
AUDIO/COMMERCIAL
OP-24
OP-34
0.17
0.17
±85
±85
90
90
2.0
2.0
5.0
45
1.7
11
4.7
4.7
0.75
0.75
0.75
5.0
6.0
50
50
50
500
500
5
5
5
200
200
8
8
8
30
30
0.8
0.8
0.8
0.8
0.8
0.25
0.25
0.25
0.25
0.25
6.0 (Total)
6.0 (Total)
6.0 (Total)
5.7 (Total)
5..0 (Total)
1.0
0.3
0.1
10
3.5
10.0
8.5 (Total)
0.5
0.1
0.08
'±3
±3
±40
2.8
2.8
30
1.0
1.3
1.0
0.6
1.2
5.0
0.17
0.25
1.7
8.0 (Total)
8.0 (Total)
8.0 (Total)
Product
SR
SINGLE OP AMPS
SUPER BETA
OP-D8
OP-12
PM-108
MICRO POWER
DUALOPAMPS
GENERAL PURPOSE
OP-03
OP-D4
OP-14
PM-747
PM-1458/1558
JFETINPUT
OP-215
INSTRUMENTATION
OP-10
OP-207
OP-227
PAGE 5-6
PRODUCT SELECTOR - OPERATIONAL AMPLIFIERS
Product
Offset
Voltage
(mV)
Bias
Current
(nA)
Offset
Current
(nA)
Drllt
(ILV/DC)
Bandwidth
(MHz)
SR
(V/ILS)
Supply
Current
(mAl
0.5
2
0.2
5
0.8
0.12
1.2 (Total)
0.1
20
1.5
1.0
0.15
0.05
0.17 (Total)
DUAL
SUPER BETA
PM-2108
MICRO POWER
OP-220
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'QUAD OP AMPS
GENERAL PURPOSE
OP-09
OP-11
PM-4136
0.5
0.5
5.0
300
300
500
20.0
20.0
200.0
10
10
30
1.5
1.5
1.5
0.7
0.7
0.5
6.0 (Total)
6.0 (Total)
11.4 (Total)
2.5
2.5
20
50
1.5
5.0
10
10
0.15
1.0
0.05
0.25
0.3 (Total)
1.8 (Total)
MICRO POWER
OP-420
OP-421
PAGES-7
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OP-Ol
PMI
INVERTING HIGH-SPEED
OPERATIONAL AMPLIFIER
®
FEATURES
•
•
•
•
•
•
•
•
•
•
Fast Settling Time ..................... 1,..stoO.1%
High Slew Rate ............................ 18V/,..s
Power Bandwidth ... . . . . . . . . . . . . . . . . . . . . .. 250kHz
Low Power Consumption . . . . . . . . . .. 90mW Maximum
Excellent DC Specifications
Internally Compensated
Ideal DAC Output Amplifier
MIL-STD-883 Processing Available
Fits Standard 741 Sockets
Low Cost
GENERAL DESCRIPTION
The OP-01 Series of monolithic Inverting High-Speed Operational Amplifiers combines high slew rate, fast settling time
and excellent DC input characteristics. An internal feedforward frequency compensation network provides simplicity
of application - no external capacitors are required for
stable, high-speed performance. The fastoutput response is
achieved without sacrifice of input bias current or power
consumption. A 250kHz power bandwidth is attained with a
small signal bandwidth of 2.5MHz, allowing non-critical
board layout. The OP-Q1 is completely protected at both
input and output, fits standard 741 sockets, and is offset
nulled with a 10kCl potentiometer.
The low offset voltage. input bias current, and offset voltage
drift vs. temperature provide accurate DC performance in
applications such as channel preamplifiers, fast integrators
and precision summing amplifiers. The fast output response
and excellent settling time makes the OP-01 ideal for use in
Df A converter output amplifiers.
PIN CONNECTIONS
8 A· 0 '
N.C. 7V+
ORDERING INFORMATION
t
-IN 2
sOUT
PACKAGE
TA" 25' C
vos
Max.
(mV)
0.7
HERMETIC
TO-"
8 Pin
OP01J'
+IN 3
DIP
8 Pin
14 Pin
OP01Z'
OP01Y'
0.7
OP01HJ
OP01HZ
OP01HY
2.0
OP01FJ'
OP01FZ'
OP01FY'
2.0
OP01EJ
OP01EZ
OP01EY
5.0
OP01GJ'
OP01GZ'
OP01GY'
5.0
OP01CJ
OP01CZ
OP01CY
PLASTIC
DIP
8 Pin
OPERATING
TEMPERATURE
RANGE
MIL.
OP01HP
COM.
OP01EP
COM.
TO-99
14-PIN HERMETIC DIP
(Y-Sufflx)·
MIL.
(J-Suffix)
EPOXY B MINI-DIP
(P-Suffix)
MIL.
OP01CP
5 BAL
4 V- (CASEI
&
COM.
• Also available with MIL-STO-883B processing. To order add/883 as a suffix to
the part number.
t All listed parts are available with 160 hour burn-in. See Ordering Information,
Section 2.
8-PIN HERMETIC DIP
(Z-Sufflx)
• Not recommended for new designs.
SIMPLIFIED SCHEMATIC
V+
+Q1, 02, Q3 AND Q4 FORM A
THERMALLY CROSS-COUPLED
QUAD. Q5,Q5I,Q6ANDQ6 1
COMPRISE A SIMILAR
THERMALLY CROSS-COUPLED
QUAD.
0'0
, - - -....--oOUTPUT
An
0'
BALANCE
03
05
BALANCE
PAGES-8
OP·01 INVERTING HIGH·SPEED OPERATIONAL AMPLIFIER
ABSOLUTE MAXIMUM RATINGS (Note 2)
Lead Temperature (Soldering. 60 sec) ....•......... 300°C
Total Supply Voltage. OP-01. OP-01 F. OP-01 E. OP-01H.
OP-01N. OP-01NT. OP-01G. OP-01GT •....••...••• ±22V
OP-01G. OP-01C. OP-01GR ....................... ±20V
Power Dissipation (Note 1) ..................... 500mW
Differential Input Voltage .•..•.•..•......•....••• ± 30V
Input Voltage (Note 3) ........................... ± 15V
Short Circuit Duration .......................... Indefinite
Operating Temperature Range
OP-01. OP-01F. OP-01G .............. -55°C to +125°C
OP-01H. OP-01E. OP-01C ...........•..... O°C to +70°C
DICE Junction Temperature (Tj) .....•. -65°C to +150°C
Storage Temperature Range
J. Y. and Z Packages ............... -65°C to + 150°C
P Package ........................ -65°C to + 125°C
NOTES:
1. See table for maximum ambient temperature rating and derating factor.
Package Type
Derate Above Maximum
Ambient Temperatura
Maximum Ambient
Temperature lor Rating
8O'C
7.1mW/·C
14-Pin Hermetic DIP (y)
l00'C
10.0mW/·C
8·Pin Hermetic Dip (Z)
75'C
6.7mW/'C
8-Pin Plastic DIP (p)
35'C
5.6mW/'C
TO·99 (J)
2. Absolute maximum ratings apply to both packaged parts and DICE.
unless otherwise noted.
3.
For supply Yoltages less than ± 15V. the maximum input voltage is the
supply voltage.
II
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(I)
ELECTRICAL CHARACTERISTICS
OP-D1F
OP·01E
OP·01
OP·01H
PARAMETER
SYMBOL CONDITIONS
Input Ollset
Voltage
Vos
Input Olfset
Current
los
Input Bias Current
Is
Input Voltage
Range
IVR
Common Mode
Rejection Ratio
CMRR
VCM= ±10V
Rs s20kll
PSRR
Vs=±5Vto±20V
Rs s20kll
Va
RL",5kll
RL",2kll
Avo
RL",2kll
Vo= ±10V
Power Supply
Rejection Ratio
Output Voltage
Swing
Large Signal
Voltage Gain
MIN
Rss20kll
TYP
MAX
0.3
MIN
85
MAX
0.7
1.0
0.5
2.0
18
30
10
Power Consumption Pd
VOUT=O
Av= -1
(Note 1 & 2)
VIN =5V
Slew Rate
(Notes 2 & 3)
Av = -1. Rs = 3K to 5KIl
50
UNITS
.....
2.0
2.0
5.0
mV
o
1.0
5.0
2.0
20
nA
20
50
25
100
nA
± 12.0 ±13.0
V
80
100
dB
100
±12.5
±12.0
±13.5
±13.0
±12.5
±12.0
±13.5
±13.0
V
50
100
25
75
V/mV
30
100
100
100
150
pVN
50
90
50
90
50
90
mW
0.7
1.0
0.7
1.0
0.7
1.0
pS
12
18
12
18
12
18
VIpS
Large Signal
Bandwidth
(Notes 3 & 4)
150
250
150
250
150
250
kHz
Small Signal
Bandwidth
(Notes:i & 4i
1.5
2.5
1.5
2.5
1.5
2.5
MHz
Risetime
tr
Overshoot
Os
Av= -1
V1N =50mV
NOTES:
1. RL = 2kll; CL = 5OpF. See Sellling Time Test Circuli.
2. Sample tested.
150
150
150
ns
2
2
2
%
3. See application inlormation.
4. Guaranteed by design.
PAGES-9
0(
MAX
80
60
±12.5 ±13.5
±12.0 ±13.0
MIN
II.
TYP
± 12.0 ±13.0
110
ii:
::::i
::E
OP·01G
OP·01C
TYP
± 12.0 ±13.0
Settling Time
to 0.1 % (Summing ts
Node Error)
SR
II:
W
at Vs = ±15V. TA = 2S·C. unless otherwise noted.
~
fi
II:
W
II.
o
OP·01 INVERTING HIGH·SPEED OPERATIONAL AMPLIFIER
ELECTRICAL CHARACTERISTICS
at Vs= ±15V, -55·C:sTA :s +125·C forOP'()1, OP'()1F, OP·01G and O·C:sTAs +70·C for
OP'()1H, OP'()1E, OP'()1C, unless otherwise noted.
OP-Il1F
OP-Il1E
OP·01
OP·01H
PARAMETER
SYMBOL CONDITIONS
Input Offset
Voltage
Vos
Input Offset
Current
MIN
Rs:s20kll
TYP
MAX
0.4
MIN
OP-Il1G
OP.01C
TYP
MAX
1.0
t.5
MIN
TYP
MAX.
UNITS
3.0
3.0
6.0
mV
los
1.0
4.0
2.0
10
4.0
40
nA
Input Bias Current
Ie
30
50
40
100
50
200
nA
Input Voltage
Range
IVR
± 10.0 ±13.0
Common Mode
Rejection Ratio
CMRR
VCM= ±10V
Rs:s20kll
Power Supply
Rejection Ratio
PSRR
Vs= ± 5V to ±20V
Rs:s20kll
Large Signal
Voltage Gain
Avo
RL>:2kll,
VO= ±10V
Output Voltage
SWing
Offset Voltage
Drift (Note 2)
Va
TCVes
RL>:5kll
RL,,2kll
Rs:s5kll
85
80
110
10
30
80
±12.5
±12.0
±13.5
±13.0
2.0
± 10.0 ±13.0
±10.0 ±13.0
80
30
25
80
100
100
8.0
NOTE:
2. Sample tested.
PAGE 5-10
3.0
10.0
100
100
15
80
±12.5 ±13.5
±12.0 ±13.0
V
dB
150
pVN
50
VlmV
±12.5 ±13.5
±12.0 ±13.0
V
5.0
20.0
pV/"C
OP·01 INVERTING HIGH·SPEED OPERATIONAL AMPLIFIER
DICE CHARACTERISTICS (125° C TESTED DICE AVAILABLE)
1. NULL
2. INVERTING INPUT
3. NON-INVERTING INPUT
4. V5. NULL
8. OUTPUT
II
7. V+
:o
VI
a::
DIE SIZE 0.048 X 0.042 Inch
III
it
Refer to Section 2 for additional DICE Information.
i::Ii
C
ELECTRICAL CHARACTERISTICS at Vs = ± 15V, TA = + 25° C for OP-01 N, OP-01 G and OP-01 GR devices, T A = + 125° C for
OP-01NT and OP-01GT devices, unless otherwise noted.
OP-01NT
PARAMETER
SYMBOL CONDITIONS
Input Offset Voltage
Vos
As ,,20kn
OP-01N
OP-01GT
OP-01G
OP-01GR
LIMIT
LIMIT
LIMIT
LIMIT
LIMIT
UNITS
1.0
0.7
3.0
2.0
5.0
mVMAX
Input Offset Current
los
4.0
2.0
10.0
5.0
20.0.
nAMAX
Input Bias Current
Is
50
30
100
50
100
nAMAX
Input Voltage Aange
IVA
±10.0
±12.0
±10.0
±12.0
±12.0
VMIN
Common Mode
Aejectlon Aatio
CMAA
85
85
80
80
80
dB MIN
Power Supply
Aejectlon Ratio
PSRA
60
60
100
100
150
".VIVMAX
Output Voltage
Swing
YOM
A L 2:5kn
RL 2:2kn
±12.5
±12.0
±12.5
±12.0
±12.5
±12.0
±12.5
±12.0
±12.5
±12.0
VMIN
Large Signal
Voltage Gain
Avo
AL2: 2kn
Vo= ±10V
30
50
25
50
25
VlmV MIN
Power Consumption
Pd
VOUT=O
90
90
mWMAX
VcM =±10V
As ,,20kn
Vs = ±5V to ±20V
As" 20kn
90
NOTE: For25' C characteristics of NT & GT devices. see N & G characteristics
respectively.
TYPICAL ELECTRICAL CHARACTERISTICS at Vs = ±15V, TA = 25°C, unless otherwise noted.
ALL GRADES
PARAMETER
SYMBOL CONDITIONS
Slew Rate
SA
TYPICAL
UNITS
Rs = 3kn to 5kn
18
VI"..
V'N=5V
A v =-l
RL = 2kn (See Settling Time Test Circuit)
C L = 50pF
1.0
"..
Large Signal
Bandwidth
250
kHz
Small Signal
Bandwidth
2.5
MHz
150
ns
Settling Time to
t.
0.1%
(Summing Node Error)
Risetime
tr
AVCL =-1
V'N= 50mV
A v =-l
PAGE 5-11
~
o
~a::
~
o
OP·01 INVERTING HIGH·SPEED OPERATIONAL AMPLIFIER
TYPICAL PERFORMANCE CURVES
SMALL-SIGNAL PULSE RESPONSE
LARGE-SIGNAL PULSE RESPONSE
TIME (100ms/DIVI
OP-Ol
Vs = ±16V, Ay .. -1, RL '" 21en. C l .. 50pF
TIME 1500ms/DIVI
OP-01
Vs'" ±15V. AV .. -1, Rl = 2kO. CL .. 60pf
UNITY GAIN BANDWIDTH
vs SOURCE RESISTANCE
1.
1~I.I~.~~
2.
RS = 5.DkO
3.
RS'" lDkn
RS = 33kfl
..
4-
120 rTT_-nTrmrmm.-nmmr-rnnmr-mmmrTr1'mI
12
I
.......
2rr' ~, •
~
1. INVERTING
AV=-l
2. NON·
INVERTING
,
AV>50
3. NON·
INVERTING
,
•
RS'" lOO1dl
ON
•
LARGE SIGNAL OUTPUT
SWING vs FREQUENCY
OPEN LOOP GAIN
vs FREQUENCY
I
!\
AV= 10
4. NON·
INVERTING
AV= 1
(VOLTAGE
,
fOLLOWER)
I
1\
,"\
I
1
0.01
0.10
1.00
10.0
1000 10,000
0.001
0.01
0.10
1.00
fREQUENCY (MHz)
FREQUENCY (MHz)
APPLICATIONS INFORMATION
FAST INVERTING AMPLIFIER"
The OP·01 incorporates an internal feed· forward compensa·
tion network to provide fast slewing and settling times in all
inverting and moderate-to·high gain non-Inverting applica·
tlons. Unity gain bandwidth Is a function of the total
equivalent source resistance seen by the inverting terminal,
and proper choice of this resistance will allow the user to
maximize bandwidth while assuring proper stability. The
equivalent inverting terminal resistance Is defined as
RIN i RF• A total equivalent input terminal resistance ",,3.3kO
will assure stability in all closed loop gain configurations in·
cluding unity gain. Should RIN ~ RF s3.3kO, a resistor (Rs)
may be placed between the inverting input and the sum
node to provide the required reSistance. (See Fast Inverting
Amplifier Diagram.) Lower values of total equivalent
resistance may be used to improve bandwidth in higher
closed loop gain configurations, as indicated by the Open
Loop Gain vs. Frequency plot.
••
REa· RS+RIN II RF
FOR Ay- -l.Reo> 3.3Idl
Rp" Rea
·PINOUTS SHOWN APPLY TO J, P AND Z PACKAGES.
PAGE 5-12
10.0
OP·CI1 INVERTING HIGH-SPEED OPERATIONAL AMPLIFIER
SETTLING TIME TEST CIRCUIT *
FAST VOLTAGE OUTPUT O/A CONVERTER
Settling time may be measured using the circuit shown; this
circuit incorporates the "false sum node" technique to pro·
duce more accurate, repeatable results. For a 5 volt input
step, 0.1 % settling will be achieved when the false sum
node settles to within ±2.5mV of Its final value. The
oscilloscope used for observation of the false sum node
should have wide bandwidth, fast overload recovery time,
and be used with a low capacity probe (,,;;10pF, including
strays). A Tektronix 7504 scope with a 7A11 probe or
equivalent is suggested. The pulse generator should have a
5011 output impedance and be capable of a 5V rise time in
,,;;2Ons with ringing less than 2.5mV after 0.5,..s. 0.1%
measurements require RIN to equal RF within 0.01 %; R5 and
As are used as trimming resistors to achieve this matching.
BIT 10
0-lOV
TYPICAL SETTLING
II
'.7kll
~
TIME ....&,.tIEC
o
o~---------,
VA TO SCOPE CIN = 10pf
l_
r-- RF -----.
H8
H6
1111..0+.5% 160:!:1%
, - - nlN - - - ,
R6
l5Ot'%
BIT 1
*
R7
1'*.0:1.5%
PRECISION POWER BOOSTER CIRCUIT
*
A
INPUT
~
ru-=-Ra
SO
R1
6kD±.K
-=- R9
R2
SkiS
OUTPUT
L"
"5Y~0"'FU"'1L"
~
op 0' 7
r'#--"""
"'II
',IV
C
SOpF
,Okll
4 D.1Io1F:t10%
f-----l
-15V
":'"
-:
'Okll
'''11
Y,N
Your
TYPICAL APPLICATIONS
OFFSET NULLING CIRCUIT
•
*
'00ll
20kll
TYPICAL PERFORMANCE:
SLEW RATE---~-----'" ,8V/Jd;EC
0.1% SETTLING ------4pSEC (R L = !?OOI
QUIESCENT SUPPLY CURRENT ---1.5mA
Y-
'PINOUTS SHOWN APPLY TO J, P AND Z PACKAGES
PAGE 5-13
-1SV
OP-02/0P-19
PMI
HIGH-PERFORMANCE GENERAL-PURPOSE
OPERATIONAL AMPLIFIERS
®
FEATURES
All Devices:
• Excellent DC Input Specifications
• Low Noise .......••••...•......••...•......• 0.65j.1Vp _p
• Low Drift (TCVos) Max ....••....••••.......... 8j.1V1° C
• 0°CI+70°C and -55° C1+125° C Models
• Silicon-Nitride Passivation
• Guaranteed Rile Time and Overshoot
• 125° C Tested Dice
• "Premium" 741 and 107 Replacement
• High Speed (OP-19) ......•......•.. 1.0V/j.ls Slew Rate
GENERAL DESCRIPTION
The PMI Series of High-Performance GenElral-Purpose Operational Amplifiers provides significant improvements over
industry-standard and "premium" 741 and 741 HStypes while
maintaining pin-for-pin compatibility, ease of application,
and low cost. Key specifications such as Vos, los, I B, CMRR,
PSRR and Avo, are guaranteed over the full operating
temperature range. Precision Monolithics' exclusive SiliconNitride "Triple Passivation" process reduces "popcorn noise."
A thermally-symmetrical input stage design provides low
TCVos, TClos, and insensitivity to output load conditions.
The OP-02 is a direct replacement for the 741. It is ideal for
upgrading existing designs where accuracy improvements
are required and for eliminating special low-drift or low-noise
selected types.
The OP-19 is a high-speed replacement for the 741. It's high
slew rate increases the maximum undistorted output frequencyfrom 5kHz to 10kHz making it ideal fortelecommunications applications.
ORDERING INFORMATIONt
PIN CONNECTIONS
PACKAGE
HERMETIC
T" = 2SoC
VosMAX
(mV)
TO-"
8-PIN
a-PIN
14·PIN
0.5
OP02AJ'
OP19AJ'
OP02AZ'
OP19AZ'
OP02AY'
0.5
OP02EJ
OP19EJ
OP02EZ
OP19EZ
OP02EY
2.0
OP02J'
OP19BJ'
OP02Z'
OP19BZ'
OP02Y'
2.0
OP02CJ
OP19FJ
OP02CZ
OP19FZ
OP02CY
5.0
OP02BJ'
OP19CJ'
OP02BZ'
OP19CZ'
OP02BY'
5.0
OP02DJ
OP19GJ
OP02DZ
OP19GZ
OP02DY
DIP
PLASTIC
OPERATING
DIP
TEMPERATURE
a·PIN
RANGE
MIL
OP02EP
_1.:Lr!:3\":~
.,.VaAL
COM
4 V- (CASE)
TO-99
(J-Sulflx)
MIL
OP02CP
14-PIN HERMlmc
DtP (Y-Sufflx)" OP-02
• Not recommended for
new designs.
COM
MIL
OP02DP
COM
, Also available with MIL-STD-883B processing. To order add/883 as a suffix to
the part number.
t All listed parts are available with 160 hour burn-in. See Ordering Information.
Section 2.
a-PIN HERMETIC DtP
(Z-Sufflx)
EPOXY B MINI-DIP
(P-Sufflx) OP-02
SIMPLIFIED SCHEMATIC
"Qt, 02, Q3 AND Q4 FORM A
TH£RMALLV CROSS-COUPLED
QUAD. 06, 06', Q8 AND 06'
COMPRise A SIMILAR THER·
MALLY CROSS.coUPLEOQUAD.
-IN
o--------t--------,
RI.
+IN
Rl1
PAGE 5-14
OP-02/0P-19 HIGH-PERFORMANCE GENERAL-PURPOSE OPERATIONAL AMPLIFIERS
ABSOLUTE MAXIMUM RATINGS (Note 2)
'NOTES:
Supply Voltage .............................. ±22V
Power Dissipation (Note 1) ...................... 500mW
Differential Input Voltage. . . . . . . . . . . . . . . . . . . . .. ±30V
Input Voltage ........................ Supply Voltage
Output Short Circuit Duration. . . . . . . . . . . . . .. Indefinite
Operating Temperature Range
OP-02A, OP·02, OP-028 ............ , - 55 to + 125"C
OP-02E, OP·02C, OP-02D . . . . . . . . . . . .. O"C to + 70"C
OP-19A, OP-198, OP-19C ........... -55° C to +125° C
OP-19E, OP-19F, OP-19G ................ 0° C to +70°C
1.
See table for maximum ambient temperature rating and derating factor.
Derate Above Maximum
Ambient Temperature
Maximum Ambient
Package Type
Temperature lor Rating
TO-99 (JI
80'C
7.1mW/'C
100'C
10.0mW/'C
8-Pin Plastic DIP (PI
36 'C
S.6mW/'C
8-Pin Hermetic
Dip (ZI
7S'C
6.7mW/'C
14-Pin Hermetic DIP (V!
Storage Temperature Range ........ -65°C to +150"C
Lead Temperature (Soldering, 60 sec.) ........... 300"C
DICE Junction Temperature (Tj ) ••••••• -65°C to +150°C
2.
E
Absolute maximum ratings apply to both packaged parts and DICE, unless
otherwise noted.
SYMBOL CONDITIONS
Input Offset Voltage
Vos
Input Offset Current
lOS
Input Bias Current
Input Voltage Range
MAX
TYP
MAX
1.0
2.0
3.0
5.0
mV
OP-02
OP-19
0.5
0.5
2.0
5.0
1.0
1.0
5.0
6.0
5.0
5.0
25
25
nA
OP-02
OP-19
18
18
30
50
20
20
50
60
30
30
100
100
nA
(Note 21
3.8
Va
RL ~ 2kO
Large Signal
Avo
RL> 2kO
85
100
Input Noise
Voltage Density
10 == 10Hz
fo = 100Hz
fo= 1000Hz
Input Noise Current
0.1 Hz to 10Hz
fo == 10Hz
10 = 100Hz
fo = 1000Hz
SR
Large Signal
Bandwidth
Risetime
Overshoot
BW
80
95
30
60
250
50
50
50
70
90
Sample tested.
Mil
±10.0 ±13.0
V
70
85
100
100
dB
150
±12.0 ±13.0
200
25
V
150
50
50
90
90
~VIV
VlmV
90
90
mW
0.65
0.65
0.65
25
22
21
25
22
21
25
22
21
12.8
12.8
12.8
1.4
0.7
0.4
1.4
0.7
0.4
1.4
0.7
0.4
pA/y'Hz
nVly'Hz
(Note 11
OP-02
OP-19
0.25
0.8
0.5
1.0
0.25
0.8
0.5
1.0
0.25
0.5
1.0
VI~S
Vo = 20V p _p
(Note 11
OP-02
OP-19
4.0
11.0
8.0
20.0
4.0
11.0
8.0
20.0
4.0
8.0
20
kHz
0.8
1.3
0.8
1.3
0.8
1.3
MHz
AVCL = +1.0
(Note 11
AV=+1
V,N = 50mV (Note 11
(Note 11
OP-02
OP-19
200
300
200
10
15
15
2. Guaranteed by design.
PAGE 5-15
300
200
10
NOTE:
1.
UNITS
5.0
1.0
±12.0 ±13.0
40
50
0.1 Hz to 10Hz
7.0
±10.0 ±13.0
100
10
OP-02
OP-19
Power Consumption
Input Noise
Current Density
2.3
±12.0 ±13.0
___
Vo_l_ta~g_e_G_a_in_________________V~0,,-~±10V
e np _p
7.5
±10.0 ±13.0
IVR
Output Voltage Swing
Closed Loop
Bandwidth
MIN
TVP
0.5
Vs = ±5 to ±20V
Rs" 20kll
Slew Rate
MIN
MAX
PSRR
Input Noise Voltage
MIN
0.3
CMRR
Rejection Ratio
OP-02B/OP-19C
OP-020/0P-19G
TVP
VCM = ±10V
Rs" 20kll
Power Supply
OP-02/0P-19B
OP-02C/OP-19F
w
ii:
:::i
a.
::E
«
....I
«
Z
o
~
a:
w
Input ResistanceDifferential Mode
Common Mode
Rejection Ratio
a:
OP-02A10P-19A
OP-02E/OP-19E
RS" 20kll
a.
o
Ul
ELECTRICAL CHARACTERISTICS Vs = ±15V, TA = 25°C, unless otherwise noted.
PARAMETER
£9'"
300
10
15
ns
%
a.
o
OP-G2/0P-19 HIGH-PERFORMANCE GENERAL-PURPOSE OPERATIONAL AMPLIFIERS
ELECTRICAL CHARACTERISTICS at Vs = ± 15V, -55' C::; TA ::; + 125' C, unless otherwise noted.
PARAMETER
Inp~t
Offset Voltage
Average Input Offset
Voltage Drift (Nota 1)
SYMBOL CONDITIONS
3.0
6.0
mV
TCVos
Rs=500
2.0
8.0
4.0
10.0
8.0
20
p.V!·C
1.0
1.0
5.0
10.0
2.0
2.0
10.0
12.0
5.0
5.0
50.0
50.0
nA
7.5
75
15
150
30
300
pA/'C
30
80
30
100
40
40
100
120
50
50
200
200
nA
Input Bias Current
Ie
OP-02
OP-19
OP-Q2
OP-19
±10.0 ±13.0
Input Voltage Range
IVR
Common Mode
Rejection Ratio
CMRR
VcM =±10V
Rs $20kO
PSRR
Vs = ±5 to ±20V
Rs $20kO
Avo
RL ,,2kO
Vo =±10V
Va
RL ,,2kO
80
50'
±10.0 ±13.0
95
10
3.0
UNITS
1.0
TClos
Output Voltage Swing
1.4
0.5
Average Input Offset
Current Drift (Note 1)
Large Signal
Voltage Gain
OP-02B/OP-19C
MIN TVP MAX
Rs$20kO
los
Rejection Ratio
OP-02/0P-19B
MIN TVP MAX
Vas
Input Offset Current
Power Supply
OP-02A10P-19A
MIN TVP MAX
80
60
100
95
30
25
±12.0· ±13.0
±10.0 ±13.0
70
100
60
100
25
±12.0 ±13.0
V
85
dB
150
p.V/v
80
VlmV
±10.0 ±13.0
V
ELECTRICAL CHARACTERISTICS Vs = ±15V, D'C::; TA ::; +7D'C, unless otherwise noted.
OP-02E/OP-19E
MIN TVP MAX
OP-02C/OP-19F
MIN TVP MAX
OP-02D/OP-19G
MIN TVP MAX
Rs $20kO
0.4
1.0
1.2
3.0
3.0
6.0
mV
Rs=500
2.0
8.0
4.0
10.0
8.0
20
p.VI·C
0.7
0.7
4.0
10.0
1.4
1.4
10.0
10.0
5.0
5.0
50
50
nA
7.5
120
15
250
70
500
pA/'C
50
100
25
25
100
100
50
50
200
200
nA
PARAMETER
SYMBOL CONDITIONS
Input Offset Voltage
Vas
Average Input Offset
Voltage Drift (Note 1 )
TCVos
Input Offset Current
los
Average Input Offset
Current Drift (Note 1)
TClos
Input Bias Current
Ie
Input Voltage Range
IVR
OP-02
OP-19
22
22
OP-02
OP-19
±10.0 ±13.0
Common Mode
Rejection Ratio
CMRR
VcM =±10V
Rs $20kO
Power Supply
Rejection Ratio
PSRR
Vs = ±5 to ±20V
Rs $20kO
Large Signal
Voltage Gain
Avo
RL ,,2kO
Vo =±10V
Output Voltage SwIng
Va
RL ,,2kO
80
100
10
50
±10.0 ±13.0
100
±12.0 ±13.0
NOTE:
1. Sample tested.
PAGE 5-18
80
90
30
60
25
±10.0 ±13.0
80
±12.0 ±13.0
70
100
15
V
85
100
UNITS
dB
150
p.V/v
25
VlmV
±10.0 ±13.0
V
OP-02/0P-19 HIGH-PERFORMANCE GENERAL-PURPOSE OPERATIONAL AMPLIFIERS
DICE CHARACTERISTICS (125° C TESTED DICE AVAILABLE)
1.
2.
3.
4.
5.
8.
NULL
INVERTING INPUT
NON-INVERTING INPUT
V-
NULL
OUTPUT
7. V+
Refer to Section 2 for additional DICE Information
ELECTRICAL CHARACTERISTICS at Vs =± 15V, TA =+ 25° C for N, G and GR. T A =+ 125° C for NT and GT devices. unless
otherwise noted.
en
PARAMETER
SYMBOL CONDITIONS
Input Offset Voltage
Vos
Input Offset Current
los
Input Bias Current
I.
Input Voltage Range
IVR
Common Mode
Rejection Ratio
CMRR
PSRR
Power Supply
Rejection Ratio
Output Voltage Swing
R s S20kO
OP-02NT
OP-02N
OP-19N
OP-02GT
OP-02G
OP-19G
OP-02GR
OP-19GR
LIMIT
LIMIT
LIMIT
LIMIT
LIMIT
UNITS
1.0
0.5
3.0
2.0
5.0
mVMAX
5
6
6
25
nAMAX
60
200
nAMAX
:;
±13
±13
±13
±13
±13
V
:2
VCM = ±10V
R s S20kO
80
85
80
80
70
dBMIN
C
Z
Vs = ±5V to ±20V
RsS 20kO
60
60
100
100
150
±12
±12
±12
±12
±12
VMIN
50
100
25
50
25
V/mVMIN
90
90
mWMAX
R L ,,2kO
Avo
Power Consumption
Pd
Vo=OV
90
~VIV
MAX
NOTE: For 25° C characteristics of NT and GT devices, see Nand G characteristisc, respectively.
TYPICAL ELECTRICAL CHARACTERISTICS at Vs = ± 15V, TA = 25° C, unless otherwise noted.
OP-02GT
OP-02G
OP-19G
OP-02GR
OP-19GR
TVPICAL
TYPICAL
TYPICAL
UNITS
7.5
7.0
5.0
MO
0.65
0.65
0.65
~Vrr~
25
22
21
25
22
nVl$.
21
25
22
21
12.6
12.8
12.8
pAp-p
1.4
0.7
0.4
1.4
0.7
0.4
1.4
0.7
0.4
pAl$.
OP-02NT
OP-02N
OP-19N
SYMBOL CONDITIONS
Input Resistance
R'N
e np_!;!
0.1Hz to 10Hz
'0= 10Hz
Input Noise
Voltage Density
en
Input Noise Current
I np-e
O. I Hz to 10Hz
in
'0= 10Hz
'0= 100Hz
'0= 1000Hz
Input Noise
Current Density
Slew Aate
Closed Loop
Bandwidth
f o = 100Hz
'0= 1000Hz
1.0
1.0
1.0
VI~.
Vo =20Vp_p
20
20
20
kHz
AveL =+1.0
1.3
1.3
1.3
MHz
Av=+1
V'N= 50mV
200
200
200
ns
15
15
15
%
2.0
4.0
8
~VloC
7.5
15
30
pA/oC
SR
Large Signal
Bandwidth
BW
Risetime
Overshoot
Average Input Offset
Voltage Drift
Average Input Offset
Current Drift
TCVos
UI
60
R L ,,2kO
Vo =±10V
Input Noise Voltage
(I)
II:
50
Vo
Differential Mode
~
o
50
Large Signal
Voltage Gain
PARAMETER
II
Rs = 5000
TClos
PAGE 5-17
i:
IL
c
..I
o
~
II:
UI
IL
o
OP-02l0P-19 HIGH-PERFORMANCE GENERAL-PURPOSE OPERATIONAL AMPLIFIERS
BURN-IN CIRCUITS
TO-99 (J) PACKAGE/a-PIN HERMETIC DIP (Z) PACKAGE
14-PIN HERMETIC DIP (Y) PACKAGE (OP-02 ONLY)
+22V
~
N"
5V02~
10
-22\1
-2211
OFFSET NULLING CIRCUITS
14-PIN HERMETIC DIP (Y) PACKAGE (OP-02 ONLY)
TO-99 (J) PACKAGE/a-PIN HERMETIC DIP (Z) PACKAGE
TYPICAL PERFORMANCE CURVES
INPUT SPOT NOISE
VOLTAGE vs FREQUENCY
1000
100
10
VS"±15V
TA'" 25"C
AS 500
1111111
TYPICAL
INPUT WIDEBAND NOISE vs
BANDWIDTH (0.1 Hz TO
FREQUENCY INDICATED)
INPUT SPOT NOISE
CURRENTvsFREQUENCY
:~S:~~~
f=
, I
f-
VS-±15V
TA +25°C
I
/
; TYPIC.~L
1.0
./
1
0.01
·0.1
0.1
0.10
1.0
10
FREQUENCY 1Hz)
100
1000
0.01
0.10
1.0
10
FREQUENCY (Hzl
PAGE 5-18
100
1000
0.1
1.0
10
BANDWIDTH 1kHz)
100
OP-02/0P-19 HIGH-PERFORMANCE GENERAL-PURPOSE OPERATIONAL AMPLIFIERS
,.
,.
I
100
I
POSITIVE SW 'NG
TA=25"C
VS= :!:.15V
POWER CONSUMPTION
VI POWER SUPPLY
INPUT RESISTANCE
VI TEMPERATURE
OUTPUT VOLTAGE vs
LOAD RESISTANCE
_
1000
_
TA-25"C::
FF
~ . -_:~
=-=:r--1-- - t---
NEGAT1VESW 'NG
2
!
z 100
0
8
-
o
t
I!J
ia:
• '/
IL
10
~
II
1
-to
~1L--L~
0.1
1.0
LOAD RESISTANCE TO GROUND Ikn)
10
-80
__L-~~~__~-L~~
-20
+20
+100
+60
TEMPERATURE
1.0
20
40
80
TOTAL SUPPLY VOLTAGE. V+TO V-(YOLTS)
+140
rc)
1/1
a:
w
ii:
:::;
Ii.
::Ii
POWER CONSUMPTION
vs TEMPERATURE
50
as
V"I "5~
~z
\
Q 45
i
300
J TT.l1
OP·02A
OP·19A
®VINIPIN 3) .. +lOmV, VO" -15V
\
~40
I- I--
+ 20
+60
TEMPERATURE
+100
15
+140
re)
/
,
I'-
1"'- .........
OP-02C OP-02
1""-<~OP-19B
t-.....
OP"l -f-::..b,
OP-02E
1'-4-
OF-D2A
OP-19A
TEMPERATURE
re)
+140
a
~~~~~-r-i--t--r-i--r--r-i
~
P"'r--,k::--t"'--"k,,-i-t g~~~ t-- OP-02
~
30
~
20
10
I"
..........
1""'-
-20
+20
+flO
+100
TEMPERATURE 1°C)
PAGE 5-19
+140
OP·198
I-~--t---l---li OP-Q-;-F"'t"-+.,..+r--1
o I-+-+-t---i OPj'9E
0
+100
+140
15
a:40k.-r-i--r-i--t--r-i--t--r-~
0
+60
+100
(~C)
S50~-r-i--t---r-+--t--~-+--t--;
• 1\1'\
+20
+20
+60
TEMPERATURE
'i
'\
-20
I"
INPUT BIAS CURRENT
vs TEMPERATURE
2.•
-60
~
0
INPUT OFFSET CURRENT
vs TEMPERATURE
•
w
o
511
-20
--GO
-20
fi
a:
100
TIME FROM OUTPUT BEING SHORTED (MINUTES)
UNTRIMMED OFFSET VOLTAGE
vs TEMPERATURE
"
z
o
Ii.
!!;
1"- i'f""...
,. o
c:-....
"',50
\ I\-
3.
-20
~200
§"
\\
I'--. l"-
......
;;
z
OP-02E,C
II:
v~.,~.v
0
r- r-
:
INPUT OFFSET CURRENT
va TEMPERATURE
1.751=t=+=::r::++=r~~r=n
INPUT BIAS CURRENT
VB TEMPERATURE
2.5
._601-+-+-+-I1-+--r-+-I-t-~
1.50
~
~ 1.25
g
1 2.0 '\
~ 1.5 '\,
a
1'\
I-+-+-+-I-t--:l-£t-+
~ 1.00 ~t-=t~~~~.
o
~ 0.75
;;
II:
f-o-F-+-+-I-+-+-+-I-"'---j
~
:t
o
1.0
.........
~
~ 0,5
~
"-
~ .......
3 0.251--1="""......=+-+--+-1-+-+--1
§
u
OP.Q4C - OP.Q4
r----~
~E f - ~
p-
OP-,4A
o
-20
+20
+60
TEMPERATURE
+100
-60
+140
-20
rei
+20
+60
TEMPERATURE
OPEN LOOP GAIN vs
POWER SUPPLY VOLTAGE
120
TA.! 25'C
RL:; 10k
110
.........
<'"
+100
/
OP-14 & OP-l4C
'20
1111111111
~~I~ 2soe
RS
11111
~
50n
100
j:: 10
Iill
~
!ll0
z
w
"~
0
z
>-
10
iii0:
op.o.
OP-14
r-
/1
-20
+20
+60
""00
+140
rei
OP·04A & OP-04E
OP-14A & OP-14E
WI!11U
llllilll
TA =
25~C
OP-04 &
OP.Q4C
90
'1\
OP-14 &
OP·14C
.
\
50
.0
100
lk
FREQUENCV 1Hz)
•
i
TYPICAL
j:: 100
110
101e:
I ....
'0
100
lk
'Ok
tOOk
FREaUENCY (Hz)
INPUT WIDEBAND NOISE vs
BANDWIDTH (0.1 Hz TO
FREQUENCY INDICATED)
INPUT SPOT NOISE
CURRENT vs FREQUENCY
~
........
+-+-+-1
OP-l4C
CMRR vs FREQUENCY
70
100
VS=+16V
TA - 2sOe
~
-60
70
POWER SUPPLV (VOL TSI
1000
....-
""'-
.0 I-+--+-+-t oP~l"""'I--+'-+.----j
f---+-+-+--+ oPtE OP.Q4A~~P.~'A
so
INPUT SPOT NOISE
VOLTAGE vs FREQUENCY
OP-04C
"
TEMPERATURE
eo
.t15
,......
;;;
so
.
~
30
~ 20
120
OP-04A & OP·04E
Op·l4A & OP-14E
J.lll~lr.!ttl
90
V
:1:10
~
rei
lJlllnffi 1\
100
±5
+140
~
PSRR vs FREQUENCY
300
-
OP·I'
~
OP-04E
OP-04A
--80
._+--+-f--. .- .
----
;: 50 I-+-+-+-,I-+--r-+-I-+-~
iii _.-. .. r- - -f-- -- f~ .. h,,-+-I-+--r-+-II-+-+--+---l
10~~mI
~
t--
Vs = ±15V
VS=+15V
TA = +25°C
TA'"2S"C
"
TVPICAL
I
0:
:::>
u
0
>
0.01
0.10
1.0
10
FREQUENCY (Hz)
100
1000
iI
0.'
0.01
0.10
1.0
10
FREOUENCY 1Hz)
PAGE 5-27
100
1000
o.~~I~~~~I.O~~~~'~O~-LUL~,oo·
BANDWIDTH (kHzl
-
OP-03/0P-04/0P-14 DUAL-MATCHED HIGH-PERFORMANCE OPERATIONAL AMPLIFIERS
TYPICAL PERFORMANCE CURVES (Each Amplifier)
300
>
~200
z
~
'20
V~' ':5V
~
/
...
'" "
~
m,oo
100
"\
I\.
,"
"\
"-
"\
'\
'\
o
-<10
'20
--2ll
+60
'.00
TEMPERATURE C-C)
....
D.'
-
10
1k
10k lOOk
TA=+25°C
1M
10M
10
lk
10k
,OOk
FREQUENCV 1Hz)
100
~'2
.
POSITIVE SWING
NEGATIVE SWING
..,- ~
I!J
1\
\
;II
'I
8
i'-
o
1
10
100
•
0.1
1000
1.0
10
0.1
-80
~
TA-2."C
l000~~
36
60
Vs· :!:15V
\;
r
I
OP.Q4A
.1
I
OP-l4A
\
TOTAL SUPPLY VOLTAGE. V+ TO V- (VOLTS)
J
J .1
-
r\
OP.Q4.
r\\
\ l\.
~OP-14E
11: ..
36
-<10
VS'".V
@VINIPIN3)0=+10mV, VO'" -15V
....... l"-
Ii!
80
TA = +25°C
t-- -Cl)vIN)PIN 311. -10mV. VO' ',.V
II:
'.0 ':-'--'-..J...-=-...I..-J.....J---I:,..-J--'-..J.1.....J.
+140
OUTPUT SHORT-CIRCUIT
CURRENT VB TIME
POWER CONSUMPTION
VB TEMPERATURE
POWER CONSUMPTION
VB POWER SUPPLY
..
+20
+80
+100
TEMPERATURE I·C)
-20
LOAD RESISTANCE TO GROUND (km
FREQUENCY (kHz)
20
.OM
1M
INPUT RESISTANCE
vs TEMPERATURE
~
~
~'6
I'
100
2"~
VS"':t15V
•• TA~
:120
~
100
OUTPUT VOLTAGE VB
LOAD RESISTANCE
,.
VS= :!:15V
~
1.0
fREQUENCV 1Hz)
11111111
"-
-20
-40
MAXIMUM UNDISTORTED
OUTPUTnFREQUENCY
.~
TA"25°C -
"\
TA-'25"'C-
60
28
Vs= :!:15V
so
VS.I,.6V I
I!;
~N
I
f-- r -
"\
'\
CLOSED LOOP RESPONSE FOR
VARIOUS GAIN CONFIGURATIONS
OPEN LOOP
FREQUENCY RESPONSE
OPEN LOOP GAIN
VB TEMPERATURE
-20
+ 20
t-
+80
TEMPERATURE
rei
PAGE 5-28
--
+'00
+I . .
I.
1'-'i"-
I.........
o
1
2
4
TIME FROM OUTPUT BEING SHORTED (MINUTES)
OP-03/0P-04/0P-14 DUAL-MATCHED HIGH-PERFORMANCE OPERATIONAL AMPLIFIERS
ABSOLUTE VALUE CIRCUIT *
TYPICAL APPLICATIONS
INSTRUMENTATION AMPLIFIER 2 OP-AMP DESIGN
R1
R2
R3
R4
RS
lOkn
10k!]:
lOkn
R4
R3
ErN
.,
01
fD3333
10kH
OTOil0V
II
02
FD3333
R2
10kn
EO = (ErN 2
- ErN)
(, + R3
~)PROVIDED .!!!
- ~
1
RZ-R3
Positive Input
11VA =0,02011,01 on
GENERAL DESIGN CONSIDERATIONS
Assuming ideal amplifiers, the expression for output
voltage is:
(-~)(-::)
21 EO=EIN
R3R5
:: E in R1 R4
31 With Rl
Eo
=
R3= R4= R5:
= E in
Negative Input
1) 01 off, 02 on
2) -Ein
Rl
31 Eo
=
VA
R2
+~
UI
R3 + R4
w
ii:
:::i
VA(1 + ~
)
R3+ R4
41 With R3 = R4 = RS:
Eo
=
a:
IL
~
...I
l.SV A
C
Z
With ideaGIreSistojrs[thiS
Eo=
s~m~Plifies to:
R,
R4
EO = EIN
+ 2VOSB
Ein2-Ein, 1 +"R provided-=-3
(R21 (R3 + R41 (1.51 E in
4) Vas error included:
R2
5IEo=-
Rl (R2+R3+R41
61 With Rl = R2 = R3 = R4:
R3
Eo
==
*PIN..()UTS SHOWN
FOR J, P, AND Z
PACKAGES ONLY.
-0,5VOS A
81 For Both Inputs:
Eo = + IEjnl
14-PIN HERMETIC DIP (Y) PACKAGE ONLY
v.
BURN-IN CIRCUIT (1/2 of OP-03, OP-04, OP-14)
~
~w
v-
PAGE 5-29
w
IL
OFFSET NULLING CIRCUITS (OP-03/0P-04)
DIFFERENTIAL OFFSET VOLTAGE
The amplifier's differential input offset voltage (EOS 1 - EOS2)
will be the major error factor_ If the individual input offset
voltages are of equal magnitude and polarity they appear as
a common mode input and are rejected_
~a:
o
-Ein
7) Vas error included:
EO = -EIN + ,,5 VOSB
COMMON MODE REJECTION
Because the dual op amp has a high common mode rejection ratio match, the ability to reject common mode inputs
becomes primarily a function of resistor ratio matching_
This device eliminates the need for special op amp selections in many instrumentation amplifier applications_
o
v-
OP-05
PMI
INSTRUMENTATION
OPERATIONAL AMPLIFIER
FEATURES
• Low Noise ..•..••••.. 0.6,Np-p Maximum, 0.1 to 10Hz
• Low Drift vs. Temperature ......•. 0.5,N/oC Maximum
• Low Drift vs. Time . . . • . • • . . . • •. 0.2l'V/Month Typical
• Low Bias Current . . . . . . . • . . . . . . . •. 2.0nA Maximum
• High CMRR . . . . . . . . . • • . . . • • . . . . .. 114dB Minimum
• High PSRR . . . . . . . . • • . . • . • . • . . . • .. 100dB Minimum
• High Gain .........•....•....... 300,000 Minimum
• High RIN Differential .. . . . . . . • . . . • •. 3OMO Minimum
• High RIN CM . . • .. . .. . .. .. . .. .. . . ... 2OOGO Typical
• Internally Compensated . . . . . .. Stable to SOOpF Load
• Easy to Use • • • . . . • . . . . . . . . . • • . . . .. Fully Protected
• Fits 725, 106A and 741 Sockets
• 125° C Temperature Telted Dice
with very high levels of gain. input impedance. CMRR. and
PSRR.
The OP-QS is a direct replacement in 72S. 108Aand unnulled
741 sockets allowing instant system performance improvement without redeSign. The OP-QS is an excellent choice for a
wide variety of applications including strain gauge and
thermocouple bridges, hlgh-gain active filters. buffers. integrators. and sample-and-hold amplifiers. For dual-matched
versions refer to the OP-207 and OP-l0 data sheets.
PIN CONNECTIONS
VOSTe~7V+
GENERAL DESCRIPTION
The OP.Q5 Series of monolithic Instrumentation Operational
Amplifiers combines superlative performance In low signal
level applications with the flexibility and ease of application
of a fully protected. internally compensated op amp. The
OP-OS has low input offset voltage and bias current combined
1.3
OPOSAJ'
OPOSJ'
OPOSEJ
OPOSCJ
+
PLASTIC OPERATING
TEMPERATURE
OIP
8-PIN
RANGE
MIL
OPOSAZ' OPOSAY'
MIL
OPOSZ' OP05Y'
OP05EZ OP05EY OPOSEP
COM
COM
OPOSCZ OP05CY OP05CP
, Also available with M I L·STD·8838 processing. To order add/883 as a sufllx to
the part number.
t All listed parts are available with 160 hour burn·in. See Ordering Information,
Section 2.
-IN
8 OUT
+IN 3
5 N.c.
•
V-(eASE)
TO·99
(J-8ufflx)
ORDERING INFORMATIONt
PACKAGE
HERMETIC
TA - 25°C
OIP
Vo.MAX TO·.
(mV)
I·PIN
a·PIN
14·PIN
0.1S
O.S
O.S
_IN 2
VOSTRIM
EPOXY B MINI·DIP
(P·Sufflx)
&
8-PIN HERMETIC DIP
(Z·Suffix)
14·PIN HERMETIC DIP
(V·Sufflx)·
'Not recommended
for new deSigns.
SIMPLIFIED SCHEMATIC
R28
R'B
RS
08
OUTPUT
04
NON
INVERTING
INPUT
028
INVERTING
INPUT
R'O
OZI
02
t--+---COZO
02B
RS
PAGE 5-30
OP·05 INSTRUMENTATION OPERATIONAL AMPLIFIER
ABSOLUTE MAXIMUM RATINGS
(Note 3)
..............................
±22V
Supply Voltage
Internal Power Dissipation (Note 1) .•••..•••..• 500mW
±30V
Differential Input Voltage •••••••••••...•...•.•
Input Voltage (Note 2) ••••••..•..••.•.•....•... ±22V
NOTES:
1. See table for maximum ambient temperature rating and derating factor.
DICE Junction Temperature •••••••••••
eo·c
7.1mWI·C
10.0mWI·C
8·Pin
Hermetic DIP (2)
75·C
6.7mWI·C
a-Pin Plastic DIP (P)
36·C
5.6mW/·C
14-Pin Hermetic DIP (V)
Storage Temperature Range
J, Y, and Z Packages ............... -65°C to + 150°C
Derate Above Maximum
Ambient Temperature
100·C
TO·99 (J)
Output Short-Circuit Duration •••.•..•...•... Indefinite
P Package
•••••••••••••••••••••••• -65°C to + 125°C
Operating Temperature Range
OP-05A, OP-05 .•••••••••.••....• -55·C to +125·C
OP-05E, OP-05C •.••..•.•••.•••••••.• O·C to + 70·C
Lead Temperature Range (Soldering, 60 sec.) .•••• 300·C
Maximum Ambient
Temperature for Rating
Package Type
2.
For supply voltages less than ±22V, the absolute maximum input voltage is
equal to the supply voltage.
3.
Absolute maximum ratings apply to both packaged parts and DICE unless
otherwise noted.
-65·C to +150°C
•
II)
9
a.
0
til
ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
Input Offset Voltage
Vos
Long Term Input Offset
Voltage Stability
w
CONDITIONS
OP-OSA
MIN TYP MAX
OP-OS
MIN
TYP MAX
0.07
0.2
0.15
aVosfTime
los
Input Bias Current
Ie
(Notes 1 & 2)
1.0
0.2
1.0
"V/Mo
2.0
1.0
2.8
nA
±0.7
±2.0
±1.0
±3.0
nA
0.6
"Vp.p
18.0
13.0
11.0
nVlVHZ
enp-p
0.35
0.6
Input Noise Voltage Density
(Note 2)
on
10=10Hz
fo =100Hz
fo= 1000Hz
10.3
10.0
9.6
18.0
13.0
11.0
10.3
10.0
9.6
Input Noise Current
(Note 2)
inpop
0.1 Hz to 10Hz
in
fo =10Hz
fo= 100Hz
f o =1000Hz
RIN
(Note 3)
Input Resistance -
Differential Mode
mV
0.2
0.35
(Note 2)
Ut.llTS
0.7
O.IHz to 10Hz
Input Noise Current Density
0.5
Input Resistance Common Mode
RINCM
Input Voltge Range
IVR
Common Mode Reiectlon Ratio
CMRR
Power Supply Rejection Ratio
PSRR
Vs=±3Vto ±18V
Large Signal Voltage Gain
Avo
RL,,2k!l, Vo= ±10V
RL,,5000, Vo= ±.5V
Vs = ±3V (Note 2)
Output Voltage Swing
Vo
RL,,'0k!l
RL,,2kll
RL,,'kll
14
30
14
30
pA p.p
0.32
0.14
0.12
0.80
0.23
0.17
0.32
0.14
0.12
0.80
0.23
0.17
pA/VHZ
60
Mil
200
200
Gil
±13.5 ±14.0
±13.5 ±14.0
30
VCM= ±13.5V
20
80
114
126
300
150
500
500
4
114
126
200
150
500
500
10
±12.5 ±13.0
±12.0 ±12.8
±10.5 ±12.0
V
dB
10
"VN
V/mV
±12.5 ±13.0
±12.0 ±12.B
±10.5 ±12.0
V
Slewing Rate (Note 2)
SR
RL ,,2kIJ
0.1
0.3
0.1
0.3
VlMs
Closed Loop Bandwidth
(Note 2)
BW
AVCL = +1.0
0.4
0.6
0.4
0.6
MHz
Open Loop Output Resistance
Ro
Vo = 0.10 =0
60
Pd
No load
Vs = ± 3V, No load
90
120
4
·6
Power Consumption
Offset Adj ustment Range
ii:
:::i
a.
:2
c(
-'
c(
Input Offset Current
Input Noise Voltage (Note 2)
a:
at Vs = ±1SV, TA =2S'C, unless otherwise noted.
60
4
Rp =2Okll
NOTES:
90
II
120
6
mW
mV
-------
the first 30 operating days are typically 2.5"V. Refer to typical perfor·
1. Long Term Input Offset Voltage Stability refers to the averaged trend
line of Vos vs. Time over extended periods after the first 30 days of
operation. Excluding the initial hour of operation, changes in Vos during
mance curve.
2. Sample tested.
3.
PAGE 5-31
Guaranteed by design.
Z
0
~a:
W
a.
0
OP..CJ5 INSTRUMENTATION OPERATIONAL AMPLIFIER
ELECTRICAL CHARACTERISTICS
at Vs= ±15V, -55°CsTA s +125°C, unless otherwise noted.
OP'c)5
OP·05A
PARAMETER
SYMBOL
IRput Offset Voltage
Vos
Average Input Offset Voltage
Drift Without External Trim
With External Trim
TCVes
TCVOSn
Input Offset Current
los
Average Input Offset Current
Drift
TClos
CONDITIONS
Rp = 20kll (Note 31
(Note 21
Input Bias Current
Is
Average Input Bias Current Drift
TCl s
Input Voltage Range
IVR
Common Mode Relectlon Ratio
CMRR
VCM = ±13.0V
Power Supply Rejection Ratio
PSRR
Vs= ±3V to ±18V
Large Signal Voltage Gain
Ava
RL ,,2kll, Vo= ±10V
Output Voltage Swing
Va
RL,,2kll
ELECTRICAL CHARACTERISTICS
MIN
(Note 21
TVP
MAX
TVP
MAX
UNITS
0.10
0.24
0.3
0.7
mV
0.3
0.2
0.9
0.5
0.7
0.3
2.0
1.0
pVloC
1.0
4.0
1.8
5.6
nA
5
25
8
50
pArC
±1.0
±4.0
±2.0
±6.0
nA
8
25
13
50
pAl"C
±13.0 ±13.5
110
123
200
400
MIN
±13.0 ±13.5
123
150
400
±12.0 ±12.6
VlmV
±12.0 ±12.6
V
SYMBOL
Input Offset Voltage
Vas
Long Term Input Offset
Voltage Stability
53D
~
~ 25
g
i...
20
o
~
15
OFFSET VOLTAGE CHANGE
DUE TO THERMAL SHOCK
I
*=
2SOC
-
10
laO
TIME (HOURSI
I
~
o~
0
~
i
'- 1.0
:3
Ii:
~I
ffi
DEVICE IMMERSED
!. .
20
0."
o
B~I I I I
IA I I I I
e OIL BATH
eo
40
o
~
l~
IN 700
IL
"'
~
g
TA "'70"C
-I I I
Sf
IU
a:
c
'"
~ -0.5
~
ffi
80
100
-1.0 L...I.....J.....J.......L...J..-l...-I...J...JJ......I.....J...J
0.2
0.4
0.6
0.8
1.0
1.2
TIME (SECONDSJ
UNTRIMMED OFFSET VOLTAGE MATCH liVOS (mV)
ICURVES ARE SYMMETRICAL ABOUT ZERO FOR liVOS < O}
MAXIMUM ERROR
VB SOURCE RESISTANCE
II IIIII
-s5"c TO
ffi
'"'"o
lli'"
1111
ffi~
!'i,.
i
RS'" R, - R2
10
100
MATCHED OR UNMATCHED SOURCE RESISTANCE (len)
OP-05
-65°C TO 126°C
VS"'±15V'111
1.0
'"
$
'"
$
TRIMMED -56"'c TO 125°C
1.0
~
ffi
'"
125°C
10
i
~
0.1
11111111
i
i
~
UNTRIMMED 26"C
0.01
0.'
V~'}")-
o
~
a:
u
MAXIMUM ERROR
UNTRIMMED
~
I I I
f-.I I I
. ; _1 J.
C
Z
VB SOURCE RESISTANCE
1.0
:l!
lli
10k
OP-D5A
-66°C TO 126°C
Vs ±15V
~
i'"
lk
::;
IL
OFFSET
VOLTAGE DRIFT WITH TIME
--8L.U.IIWIL.wIIUlL..LJ.i.IIIIIL..l.
0.001 0.01
0.'
1.0
i&:
UNTRIMMED ...·c ITJ]l1l~
UNTRIMMED 25"C
1111
0.1
I mmr
~
0.01 L-...J....u.wJJl.....-I...J..J.J..ILlJ.U...J..I....L.J.L.WJJ
1.0
10
1DO
0.1
SOURCE RESISTANCE (kG)
PAGES-3S
i
II
I-"""
TRIMMED _55°C TO 125"C
RS'" R 1 • R2
11111111
0.01
0.1
1.0
1111
10
MATCHED SOURCE RESISTANCE (knl
100
OP·05 INSTRUMENTATION OPERATIONAL AMPLIFIER
TYPICAL PERFORMANCE CURVES
~
10
~
..fil
$..
i
ffi
1i,.
i
VS~"J
OP__
O"c TO 700C
.,~
INPUT OFFSET
CURRENT vs TEMPERATURE
INPUT BIAS
CURRENT vs TEMPERATURE
MAXIMUM ERROR
vs SOURCE RESISTANCE
VS-±15V
VS=±15V
UNTRIMMED O"C to 70"C
1.0
0.1
UNTRIMMED 26°C
TRtJE6IJJJI~0
RS
11111111
0.01
0.1
I-'
70"C
,
R,· R2
~I -
'--
.......
OP·OSC
:::t:.- V
I'-- ~
... OP",
.......
~ ~05IE V
OP-05
J"-... . . .
./
-- --
.......- V
j--...
OP-OSA
r-Oj
1111111
1.0
~
10
.....
100
MATCHED SOURCE RESISTANCE (knl
-50
TEMPERATURE
OP'()S LOW FREQUENCY NOISE
50
100 126
50
TEMPERATURE
rei
INPUT WIDEBAND NOISE
vs. BANDWIDTH
(O.1Hz TO FREQUENCY INDICATED)
10
100
rei
INPUT SPOT NOISE
VOLTAGE vs FREQUENCY
1000
F
== ~!-:~~c
RS1 = RSZ = 200kn
THERMAL NOISE OF sOURCE
~"-I
RESISTORS INCLUDED
EXCLUDED
~
/
1.0
.......
,-
(SEE NOISE TEST CIRCUIT)
R8=0
VS= '15V
TA = 2S"C
0.1
I III
1.0
1.0
0.1
10
100
1.0
120
lllI1
OP-OSC
120
Jll'11111 IJ~~I!~5~ 1111
110
-TA"'+25"C
~
VCM = ±13.5V
~
~
10
100
lk
FREQUENCY (Hz)
10k
/;
400
-
.........
"" .......
200
80
60
1.0
800
~
70
~
c- T~=+2~C
BOO
go
80
1000
Vs = ±3V TO ±lav
JlllI[
go
100
70
OPEN LOOP GAIN vs
POWER SUPPLY VOLTAGE
.I ~~~1~5.~lll!~
J~~!~
100 -OP __
110
90
FREQUENCY 1Hz)
PSRR vs FREQUENCY
CMRR vs FREQUENCY
130
1000
100
'0
BANDWIDTH 1kHz)
100k
50
0.1
~
1.0
10
100
FREQUENCY (Hz)
PAGE 5-36
"
o
10k
o
±5
±10
±15
POWER SUPPLY VOLTAGE (VOLTS)
±20
OP·05 INSTRUMENTATION OPERATIONAL AMPLIFIER
TYPICAL PERFORMANCE CURVES
120
-
80
OPEN-LOOP
FREQUENCY REPONSE
'" "-"10
100
100
vsl=±15~ _ r-~
1"\
lk
Z
'"'"
10k 100k
28
ai
'"
60
§"
"'
MAXIMUM UNDISTORTED
OUTPUT vs FREQUENCY
Vi'±15)-
80
TA = +25"C
-40
0.1
CLOSED-LOOP RESPONSE FOR
VARIOUS GAIN CONFIGURATIONS
.
20
vs~ ,W
r-
TA = +25"C
TA '" 25"C
~
1;
~
f\
II
'-1\
\
(II
-20
1M 10M
10
100
FREQUENCY (Hz)
lk
10k
1M
lOOk
10M
10
FREQUENCY 1Hz}
100
1000
FREQUENCY (kHz)
a::
w
ii:
::::i
A.
~
-'
INPUT BIAS CURRENT vs
DIFFERENTIAL INPUT VOLTAGE
POWER CONSUMPTION
vs POWER SUPPLY
1000
~
;;
30
...
TA'" +25"C
I-
ill
AT
IVDIi=FI~1.0V. 11811 ~ ~~ :::~I
~
~
V
a
~
iii
_
E;; 7nA (OP.()5C) ---:
20
V
10
~
L-
V"
i2
-10
'Z" -10
~
>
~
-20
10
/'
,/
VS"'±15V -
20
40
60
TOTAL SUPPLY VOLTAGE, V+ TO V-IVOLTS)
I
~
II II
a::
w
ls,LJl!JJ
A.
o
0
C
NEGATIVE SWING
I-
II
"
[I
~
20
TA=25~C,_
~
I
iii 15
~
~ +2~.J
TA
VS=±15V
VIN=±10mV
0
Z
1.0
f-
'z~" 10
V
~
I
20
-20
I-
~
o
OUTPUT SWING vs LOAD
-30
-30
-30
I I I
30
0.1
-20
-10
10
20
30
DIFFERENTIAL INPUT VOLTAGE (VOLTS)
TYPICAL OFFSET VOLTAGE TEST CIRCUIT
1.0
LOAD RESISTANCE TO GROUND (kn)
TYPICAL LOW FREQUENCY NOISE TEST CIRCUIT *
+15V
200kn
50!"!
1000
>---+---0 va
loon
INPUT REFERRED NOISE =
~=
::acm
= 2oonV/em
::::::10Hz FilTER
* OBSERVATION TIME LIMITED TO 10 SECONDS MAXIMUM.
PAGE 5-37
10
OP·05 INSTRUMENTATION OPERATIONAL AMPLIFIER
swings; larger capacitances should be decoupled with SOil
decoupllng resistor. The designer is cautioned that stray
thermoelectric voltages generated by dissimilar metals at
the contacts to the Input terminals can prevent realization
of the drift performance indicated. Best operation will be obtained when both input contacts are maintained at the same
temperature, preferably close to the temperature of the
device's package.
OFFSET NULLING CIRCUIT
v+
OUTPUT
TYPICAL APPLICATIONS
INPUT
STABLE, HIGH IMPEDANCE BUFFER
SR·O.25V/p.ac
*
BURN·IN CIRCUIT
ZIN .. 200Gn
OUTPUT NOISE" O.35IlV P-P TVP
OUTPUT OFFSET'" O.2mV TVP
BANDWIDTH" 1.2MHz
"'200 x 1Q1n
IN" ±1.0nA
HIGH IMPEDANCE, HIGH COMMON MODE REJECTION
INSTRUMENTATION AMPLIFIER
OUTPUT
R'
r*
I
*PIN OUTS SHOWN FOR J. P. AND Z PACKAGES.
ZIN" 1DQGfl
R3
liN
an
=±1.DnA
R6
an
2kIl
APPLICATIONS INFORMATION
OP·05 Series devices may be fitted directly to 725 and 1081
108A Series sockets with or without removal of external
compensation components. Additionally, OP..Q5 may be fitted
to unnulled 741 Series sockets; however If conventional 741
nulling circuitry is in use, it should be modified or removed
to enable proper OP'()5 operation. The OP'()5 provides stable
operation with load capacitances up to 500pF and ±10V
• TQ-99 package only.
PAGE 5-38
SR
=t
2.5V/fI,r4C
MoM
R6
20kn
ADJUST R7 FOR MAXIMUM CMRR
R7
R6 (2RI
Ay -Ai
R3
.1
+1f
PMI
OP-06
HIGH-GAIN INSTRUMENTATION
OPERATIONAL AMPLIFIER
®
FEATURES
• Very High Voltage Gain .......... 1,OOOVlmV Minimum
• Low Offset Voltage and Offset Current
• Low Drift vs. Temperature
(TCVos) ..................... O.8I"V/·C Maximum
• Low Input Voltage and Current Noise
• Low Offset Voltage Drift with Time
• High Common Mode Rejection ......... 120dB Typical
• High Power Supply Rejection . . . . . . .. 21"VN Maximum
• Wide Supply Range. . . . . . . . . . . . . . . .. ±3.0V to ±22V
• ± 30V Input Overvoltage Protection
• MIL·STD·883 Processing Available
• Slew Rate to ............................ 100VII"s
GENERAL DESCRIPTION
The OP·06 monolithic Instrumentation Operational
Amplifier is specifically deSigned for accurate high-gain
amplification of low level input signals in the presence of
large common-mode voltages. Superior DC input characteristics include very low offset voltage and current, extremely
high open-loop gain, low 1/f and wideband noise, and a
minimum of "popcorn"noise. The extremely low offset
voltage drift is further improved by an advanced nulling
technique that provides optimum TCVos performance when
Vos has been nulled to zero. Very high common mode and
power supply rejection enable accurate performance in the
presence of large spurious signals.
Flexible external compensation provides wide bandwidth
and high slew rate operation in high closed-loop gain applications. The superior long term stability, and compatibility
with MIL-STD-883 processing, make the OP-06 an excellent
choice for high reliability process control and aerospace
applications; including strain gauge and thermocouple amplifiers, low noise audio amplifiers, and instrumentation amplifiers. The OP-06 is a direct replacement for all 725 types
providing superior DC and noise performance plus the unique feature of complete input differential voltage and output
short circuit protection.
See AN-25 for additional information.
PIN CONNECTIONS
+
-IN 2
HERMETIC
DIP
TO-SS
I-PIN
I-PIN
14-PIN
OPERATING
TEMPERATURE
RANGE
6 OUT
0.2
0.2
0.5
0.5
1.3
1.3
OP06EJ
OP06AJ'
OP06FJ
OP06BJ'
OP06GJ
OP06CJ'
OP06EZ
OP06AZ'
OP06FZ
OP06BZ'
OP06GZ
OP06CZ'
OP06EY
OP06AY'
OP06FY
OP06BY'
OP06GY
OP06CY'
COM
MIL
COM
MIL
COM
MIL
+IN 3
5 caMP
4
v-teASEl
TO·99 (J·Suffix)
8
Vas TRIM
-IN
14-PIN DIP (V-Suffix)"
Vas TRIM
* Not Recommended for
2
New Designs
• Also available with MII-STD-SS3B processing. To order add /883 as a suffix to
the part number.
tAil listed parts are available with 160 hour burn-in. See Ordering Information.
COMP
S-PIN DIP (Z·Sufflx)
Section 2.
SIMPLIFIED SCHEMATIC
A19""
t------1---< OUTPUT
R3
Y-+--r1~ 026
"Q27, 028, R2l, A22, COM·
PRISE THE INPUT PROTEC·
TION CIRCUIT.
*+023, 029, A19, RZO COMPRISE THE OUTPUT PROTECTION CIRCUIT.
PAGE 5-39
IL
o
III
II:
W
i&:
:::l
IL
::E
c
....
c
z
o
~
II:
o
PACKAGE
T A =25·C
VosMAX
(mV)
CD
'i'
W
IL
VOSeTn7V+
ORDERING INFORMATIONt
•
OP-08 HIGH-GAIN INSTRUMENTATION OPERATIONAL AMPLIFIER
ABSOLUTE MAXIMUM RATINGS (Note 3)
NOTES:
1. See table for maximum ambient temperature rating and derating factor.
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . • .. ±22V
Internal Power DIssipation (Note 1) ............. 500mW
Differential Input Voltage. . . . . . . . . . . . . . . . . . . . .. ±30V
Input Voltage (Note 2) ......................... ±22V
Output Short Circuit Duration ............... Indefinite
Storage Temperature Range. . . . . . . .. -S5 °c to + 150°C
Operating Temperature Range
OP-oSA, OP-OSB, OP-OSC ......... -55°Cto +125°C
OP-OSE, OP-OSF, OP-06G . . . . . . . . . . . .. 0 °C to + 70°C
Lead Temperature Range (Soldering, 60 sec.) ..... 300°C
DICE Junction Temperature ..•.....•.. -S5°C to +150°C
Maxlmuln Ambient
Perated Above Maximum
Tamparatura lor Rating
Ambient Temperatura
Package Type
TO·99 (J)
80'C
7.1mW/'C
14-PIN HERMETIC
PIP(y)
100'C
10.0mW/'C
8·PIN HERMETIC
DIP (Z)
75'C
6.7mV/'C
2. For supply voltages Ie•• than ±22V. the absolute maximum Input voltage Is
equal to the supply voltage.
3. Absolute ratings apply to both DICE and packaged parts. unless otherwise
noted.
ELECTRICAL CHARACTERISTICS at Vs = ± 15V, TA = 25° C, unless otherwise noted.
OP-06A/E
PARAMETER
SYMBOL CONDITIONS
Input Offset Voltage
VOS
Input Offset Current
MAX
0.06
lOS
Input Bias Current
Ie
Input Noise Voltage
Density
en
(Note 1) fa = 100Hz
fo = 1000Hz
In
(Note 1) 10 = 100Hz
'0= 1000Hz
Input Resistance
RIN
(No!e31
Large Signal
Voltage Gain
AvO
Output Voltage
Swing
Vo
Density
ASS: 20kO I Note 2)
f o =10Hz
'0 =
10Hz
RL~2kn.
VO =±10V
RLi!:10k0
RL,,2k11
RL"lkll
Input Voltage Range
IVR
Common Mode
Rejection Ratio
CMRR
VCM= ±13.5V
RSs20kD
Power Supply
Rejection Ratio
PSRR
VS-±3Vto±18V
RS,,2Okll
Power Consumption
Pd
Large Signal
Voltage Gain
AVO
RLi!:500G!Note 31
VO= ±0.5V
VS= ::t:3V
Power Consumption
Pd
VS= ±3V
0.8
OP-6C/G
OP-6B/F
TYP
Input Noise Current
MIN
MIN
TYP
MAX
0.2
0.2
0.5
0.3
2.0
0.75
5.0
30
70
30
80
9.0
8.0
7.0
15.0
9.0
7.5
9.0
8.0
7.0
0.5
0.25
0.15
1.2
0.6
0.25
0.5
0.25
0.15
I.B
0.7
1.000.000 3.000,000
MIN
TYP
MAX
UNITS
0.4
1.3
mV
13
nA
40
110
nA
15.0
9.0
7.5
9.0
8.0
7.0
15.0
9.0
7.5
nVl$<
1.2
0.6
0.25
0.8
0.3
0.2
1.4
0.7
0.3
pA/.JHz
1.8
1.5
Mil
500,000 3,000,000
VN
0.5
1,000,000 3,000,000
±12.5
±12.0
:t:11.0
::t:13.0
::t:12.8
±12.5
:t12.5
:t12.0
:t11.0
±13.0
:t12.8
::t:12.5
±12.0
±11.5
±13.0
±12.8
±12.0
:t:13.5
::t:14.0
::t:13.5
::t:14.0
±13.5
::t:14.0
V
114
120
114
120
110
115
dB
100,000
V
0.5
2.0
1.0
5.0
2.0
10
/AVIV
90
120
90
120
110
150
mW
100,000
800,000
800,000
80,000
VN
800,000
mW
NOTES:
1. Sample tested.
2. Thermoelectric voltages generated by dissimilar metals at the contacts to
the input terminals can prevent the realization of the performance indi-
cated If both sides of the contacts are not kept at approximately the same
temperature. Temperature gradients should therefore b-e minimized.
3.
PAGE 5-40
Guaranteed by design.
OP-08 HIGH-GAIN INSTRUMENTATION OPERATIONAL AMPLIFIER
ELECTRICAL CHARACTERISTICS
at Vs= ±15V, -55"CsTA s +125"C, unless otherwise noted.
OP·06A
PARAMETER
SYMBOL CONDITIONS
Input Offset Voltage
(Without external
trim)
Vos
RS:s20kO rNole 21
Average Input Offset
Voltage Drift (WIthout external trim)
TCVOS
AS = 50D (Notes 1,2)
Average Input Offset
Voltage Drift (With
external trim)
TeVOS n
Input Offset Current
lOS
TAMAX
TAMIN
TCIOS
(No'.')
IB
TAMAX
TAMIN
CMRR
VCM - ±13.5V
AS:s20kO
PSRR
VS=±3Vto±18V
AS:s20kO
Average Input Offset
Current Drift
Input Bias Current
Common Mode
Rejection Ratio
Power Supply
Rejection Ratio
MIN
RS=SOO (Notes 1,2)
Rp = 20kn
I
AVO
TAMAX
TAMIN
Output
Voltage Swing
Va
AL~2kO
MAX
UNITS
0.7
0.5
1.8
mV
0.7
2.0
1.4
4.5
p.VloC
0.6
0.28
1.0
0.5
1.5
p.VloC
0.25
0.8
1.0
4.0
0.6
2.0
4.0
18.0
2.0
3.0
15
25
nA
90
14
150
pAl"C
22
40
60
120
70
180
35
45
110
180
nA
II:
dB
::;
p.VfV
C
0.08
MIN
TYP
MAX
0.28
0.3
0.3
0.8
0.2
20
109
OP·06C
TYP
MAX
I
VO= :t10V;
Large Signal
Voltage Gain
OP·068
TYP
25
45
112
109
1.0
5.0
95
112
2.0
MIN
8.0
110
3.0
15
II
.
CjI
'D.
0
In
W
ii:
D.
2
-'
C
Rl~2kn
1,000,000 3,500,000
700,000 2,000,000
±12.0
1,000,000 3,500,000
700,000 1,800,000
±12.6
±12.0
400,000 3,200,000
300,000 1,700,000
±12.6
::t11.0
V/V
V
:t12.6
Z
0
~II:
W
D.
0
ELECTRICAL CHARACTERISTICS
at Vs = ±15V,
O°C ~
TA~
70°C,
unless otherwise noted.
OP·06F
OP·06E
TYP
MAX
0.08
RS = 500 (Notes 1,2)
TCVOS n
RS = son (Notes 1,2)
Rp= 20kn
Input Offset Current
lOS
TAMAX
TAMIN
Average Input Offset
Current Drift
TCIOS
(Not. 1)
IB
TAMAX
TAMIN
PARAMETER
SYMBOL CONDITIONS
Input Offset Voltage
(Without external
trim)
VOS
Rss20kO I Note 21
Average Input Offset
Voltage Drift (With·
out external trim)
TCVOS
Average Input Offset
Voltage Drift (WIth
external trim)
Input Bias Current
Common Mode
Rejection Ratio
Power Supply
Rejection Ratio
CMRR
PSRR
±13.5V
RSs20kO
VCM
MIN
MIN
MAX
0.28
0.25
0.3
0.8
0.2
109
MIN
TYP
MAX
UNITS
0.6
0.5
1.6
mV
0.7
2.0
1.4
4.5
p.V/·C
0.6
0.28
1.0
0.5
1.5
p.woC
0.25
0.8
1.0
4.0
0.65
2.0
5.0
18.0
2.0
3.0
15
25
nA
90
14
150
pAl"C
22
40
60
120
30
4.
80
180
35
45
110
180
nA
20
Vs""±3Vto±18V
RSs20kO
OP·06G
TYP
112
109
1.0
5.0
112
1 .•
95
7.0
dB
110
3.0
15
p.VlV
VO= ±10V; RL2:2kO
Large Signal
Voltage Gain
AVa
TAMAX
TAMIN
Output
Voltage Swing
Va
RL0!:2kO
1,000,000 3,500,000
800,000 2,000,000
±12.0
1,000,000 3,500,000
BOO,OOO 1,BOO,000
±12.6
±12.0
NOTES:
1. Sample tested.
2. Thermoelectric voltages generated by dissimilar metals at the contacts to
PAGE 5-41
±12.6
400,000 3,200,000
300,000 1,700,000
±11.0
±12.6
VIV
V
the input terminals can prevent the realization of the performance indicated if both sides of the contacts are not kept at approximately the same
temperature. Temperature gradients should therefore be minimized.
OP.CJ6 HIGH-GAIN INSTRUMENTATION OPERATIONAL AMPLIFIER
DICE CHARACTERISTICS
1. NULL
2. INVERTING INPUT
3. NON-INVERTING INPUT
4. V5. COMPENSATION
6. OUTPUT
7. V+
6. NULL
DIE SIZE 0.094 x 0.050 Inch
Refer to Section 2 for additional DICE Information.
ELECTRICAL CHARACTERISTICS at Vs = ±15V. T A = +25°C. unless otherwise noted.
PARAMETER
SYMBOL
CONDITIONS
Input Offset Voltage
Vos
Rs " 20kO
Input Offset Current
los
Input Bias Current
I.
Input Resistance
Differential Mode
RIN
Input Voltage Range
IVR
Common Mode
Rejection Ratio
CMRR
Power Supply
Rejection Ratio
PSRR
Output Voltage Swing
Vo
Large Signal
Voltage Gain
Avo
OP-06N
OP-06G
OP-06GR
LIMIT
LIMIT
LIMIT
UNITS
0.2
0.5
1.3
mVMAX
5
13
nAMAX
70
80
110
nAMAX
0.8
0.7
0.5
MOMIN
±13.5
±13.5
±13.5
VMIN
114
114
110
dB MIN
5
10
p.VNMAX
RL ;" 10kO
RL ;"2kO
RL ;" lkO
±12.5
±12.0
±11.0
± 12.5
± 12.0
±11.0
±12.0
.± 11.5
VMIN
RL ;"2kO
±10V
1000
1000
500
VlmVMIN
±30
±30
±30
VMAX
120
120
150
mWMAX
INote 11
VCM~±13.5V
Rs ,,20kO
Vs~±3Vto±18V
R s ,,20kO
Vo~
Differential Input
Voltage
Power Consumption
(VOUT~OV)
Pd
TYPICAL ELECTRICAL CHARACTERISTICS at Vs = ±15V, TA = +25° C, unless otherwise noted.
PARAMETER
SYMBOL
CONDITIONS
Average Input Offset
Voltage Drift
TCVos
R s ,,500
Nulled Input Offset
Voltage Drift
TeV osn
Average Input Offset
Current Drift
TClos
OP-06N
OP-06G
OP-06GR
TYPICAL
TYPICAL
TYPICAL
UNITS
0.3
0.7
1.4
p.V/oC
0.2
0.28
0.5
p.VloC
3
8
14
pArC
R s ,,50kO
Rp~20kO
NOTE:
1. Guaranteed by design.
PAGE 5-42
OP-06 HIGH-GAIN INSTRUMENTATION OPERATIONAL AMPLIFIER
TYPICAL DYNAMIC PERFORMANCE CURVES
OPEN LOOP RESPONSE
FOR VALUES OF COMPENSATION
90
§
I-"'~po...,---~~+-'~-f"''''''''+---i
60 t--~---"''k:---''''i::----''k::----''
100
10
±20
45
'"
:fl
./
±1S
/'
10
~
100
rt--i
TA=25"C _
Vs = ±15V
..;; 40nA OP.06~ ONLY
5
H-+H+-+'l.H4-H-GAIN '"
OUTPUT SHORT-CIRCUIT
CURRENT
---i-+-I , I
20 -
~
a
f---
--=-
POWER SUPPLY VOLTAGE (VOLTS)
INPUT BIAS CURRENT vs
DIFFERENTIAL
INPUT VOLTAGE
1
±10
w
A.
-,
.±5
GAIN ~ 10,000
GAIN =
o
10·
160
GAIN .. ,
o
~a:
10
---- 1--.. I - - ._- TA=25~C~
I--- 1--
1-_-'-_-'-_-'-_--'_ _'-----'
-80
:::..::
--
..
28
-
L
V
~
z
MAXIMUM UN DISTORTED
OUTPUTvsFREQUENCY
OPEN LOOP GAIN vs POWER
SUPPLY VOLTAGE
T
I.
1
30
TIME FROM OUTPUT BEING SHORTED (MINUTES)
Note: For further information refer to AN-15, "Minimization of Noise in Operational Amplifier Applications".
PAGE 5-45
~i5
100
a:
10
i
,.
1/
~
I
Tr~"~
40
50
50
10
20
TOTAL SUPPLY VOLTAGE, V+ TO V- (VOLTS)
oP-IIe HIGH-GAIN INSTRUMENTATION OPERATIONAL AMPLIFIER
GUARANTEED PERFORMANCE CURVES
'0
i
i
00_
-56"C TO 126°C
i
~
Ii!rr: '.0
~
fa
i
Y UNTRIMMED -55"e TO 128"C
IIIII!
ZUNTRIMMED ..·C
!i:E
W TRIMMED -56"c TO 126"C
I
Ili
0.01
0.0'
!
10
I
Y UNTRIMMED O"c TO 7O"C
II
111111
i
111111
1.0
10
SOURCE RESISTANCE, R1 (kn)
Z UNTRIMMED 25"c
'00
L
0.1
i
III
·SOURCE RESISTANCE. R1 (ItO)
1.0
rr:
rr:
0
rr: G.,
i
OP.....
O"CT07O"C
i
~
~
10
WliiijlJ[CliJ I
C
0.01
0.01
1.0
10
SOURCE RESISTANCE. R1 (kn)
00.....
O"C TO 7O"c
i
~
Y UNTRIMMED O"c TO 7O"C
1.0
These graphs depict maximum error
referred to the Input as a function of
source resistance (R,). Curves Ware
shown with Vas trimmed at +25'C and
Include errors due to Vas and los over
the Indicated temperature range. Curves
Y and Z plot maximum errors with Vas
not trimmed.
=Z UNTRIMMED ..·C
~
~
§
0.1
Ili
W TRIMMED O"e TO 7O"c
~
i
III
1111111
0.01
0.01
II
1.0
10
SOURCE RESISTANCE. R1 (len)
'00
PAGES-4.
'00
OP-07
PMI
ULTRA-LOW OFFSET VOLTAGE
OPERATIONAL AMPLIFIER
®
FEATURES
•
•
•
•
•
•
•
•
•
Ultra-Low Vos .............................. lOI'V
Ultra-Low Vos Drift ....................... O.2I'V/oC
Ultra-Stable vs Time. . . . . . . . . . . . . . . . . .. O.2l'V/Month
Ultra-Low Noise . . . . . . . . . . . . . . . . . . . . . . . .. O.35I'Vp.p
No External Components Required
Large Input Voltage Range ................. ±14.0V
Wide Supply Voltage Range. . . . . . . . . .. ±3V to ±18V
Fits 725, 108A1308A, 741, AD510 Sockets
125° C Temperature Tested Dice
GENERAL DESCRIPTION
The OP-07 Series represents a breakthrough in monolithic
operational amplifier performance - Vos of lOp, V, TeVos of
0.2p,V/o e, and long-term stability of 0.2p,V/month are achieved
by a low-noise, bipolar input transistor amplifier circuit. Elimination of external components for offset nulling, frequency
compensation, and device protection improves the system
MTBF and reduces cost. Excellent device interchangeability
provides reduced system assembly time and eliminates field
recalibrations.
True differential inputs with wide input voltage range and
outstanding common-mode rejection provide excellent performance in high-noise environments and non-inverting
applications. Low bias currents and extremely-high input
impedances are maintained over the entire temperature
range.
The OP-07 provides unparalleled performance for low noise,
high-accuracy amplification of very low-level signals in
transducer applications. Devices are available in chip form
for use in hybrid circuitry. The OP-07 is a direct replacement
for 725, 108A/308A', and OP-05 amplifiers; 741-types may be
directly replaced by removing the 741's nulling potentiometer.
*TO-99 package only. For Matched Dual see OP-207.
VO:I:R~M~~:OUT
25
75
75
150
150
OP07AJOP07EJ
OP07J'
OP07CJ
OP07DJ
PLASTIC
OPERATING
DIP
TEMPERATURE
RANGE
a-PIN
DIP
a-PIN
14-PIN
OP07AZ'
OP07EZ
OP07Z'
OP07CZ
OP07AY'
OP07EY
OP07Y'
OP07CY
OP07EP
OP07CP
OP07DP
+INv'N.c
4 V- (CASE)
TO-99 (J-Suffix)
MIL
COM
MIL
COM
COM
14-PIN HERMETIC DIP
(V-Suffix)"
*Not recommended for new designs
Also available with MIL-STO-8838 processing. To order add/883 as a suffix to
the part number.
t All listed partsareavailable with 160 hour burn-in. See Ordering Information,
*
EPOXY B MINI-DIP (P,Suffix)
8-PIN HERMETIC DIP
(Z-Suffix)
Section 2.
SIMPLIFIED SCHEMATIC
A2A·
(OPTIONAL NULL)
"NOTE:
1
R2A AND R2B ARE
ELECTRONICAllY
ADJUSTED ON CHIP
AT FACTORY FOR
MINIMUM INPUT
OFFSET VOLTAGE.
NON
3
INVERTING 0 - INPUT
2
INVERTING )-INPUT
8~
R1A
; ,-; ;
III
a:
iL
:::i
D.
~
c(
...
c(
z
o
~
a:
IU
D.
PACKAGE
TO-99
a-PIN
D.
o
o
PIN CONNECTIONS
HERMETIC
(~v)
...9
IU
ORDERING INFORMATIONt
TA - 2S'C
vas MAX
II
Ql,
f¥~
~.-;
., ~~J=L .__~~_~_--------'~
PINOUTS FOR J, Z AND P PACKAGES.
PAGE 5-47
OP-07 ULTRA-LOW OFFSET VOLTAGE OPERATIONAL AMPLIFIER
ABSOLUTE MAXIMUM RATINGS (Note 21
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ±22V
Internal Power Dissipation (Note 1) ............ 500mW
Differential Input Voltage. . . . . . . . . . . . . . . . . . . . . ±30V
Input Voltage (Note 31 ........................ ±22V
Output Short Circuit Duration. . . . . . . . . . . . . .. Indefinite
Storage Temperature Range
J, Y, and Z Packages ............... -65° C to + 150° C
P Package ......................... -65° C to + 125° C
Operating Temperature Range
OP-07A, OP-07 ..................... -55 to +125·C
OP-07E, OP-07C, OP-07D . . . . . . . . . . . .. O·C to + 70°C
Lead Temperature Range (Soldering, 60 sec.) ..... 300·C
DICE Junction Temperature (Tjl ...... _ -65°C to +150°C
ELECTRICAL CHARACTERISTICS at Vs
NOTES:
1.
See table for maximum ambient temperature rating and derating factor.
2.
Absolute maximum ratings apply to both packaged parts and dice, unless
otherwise noted.
3. For supply voltages less than ±22V, the absolute maximum input voltage is
equal to the supply voltage.
= ±1SV, TA = + 2S·C,
Maximum Ambient
TO-99 (J)
14-Pin Hermetic DIP (Y)
SO"C
7.1mW/"C
100"C
10.0mW/"C
S·Pin Hermetic Dip (Z)
75"C
6.7mW/"C
8-Pin Plastic Dip I p)
36"C
5.6mW/"C
unless otherwise noted.
OP-07A
PARAMETER
SYMBOL
CONDITIONS
Input Offset Voltage
Vos
Long Term Input Offset
Voltage Stability
LlVoslTime
Input Offset Current
los
Input Bias Current
18
Input Noise Voltage
e np _p
Input NOise Voltage Density
Input NOise Current
Derate Above Maximum
Ambient Temperature
Temperatufe for Rating
Package Type
OP·07
TYP
MAX
TYP
MAX
(Note 1)
10
25
30
75
"V
(Note 2)
0.2
1.0
0.2
1.0
.V/Mo
nA
MIN
MIN
UNITS
0.3
2.0
0.4
2.S
± 0.7
±2.0
±1.0
±3.0
nA
0.1 Hz to 10Hz (Note 3)
0.35
0.6
0.35
0.6
/lV p_p
en
fo =10Hz
fa = 100Hz (Note 3)
fo= 1000Hz
10.3
10.0
9.6
IS.0
13.0
11.0
10.3
10.0
9.6
IS.0
13.0
11.0
nVl$z
i np·p
0.1 Hz to 10Hz (Note 3)
Input Noise Current Density
in
fa = 10Hz
fa = 100Hz (Note 3)
fo= 1000Hz
Input Resistance Differential Mode
RIN
(Note 4)
Input Resistance Common Mode
R1NCM
IVR
Common Mode Rejection Ratio
CMRR
VCM = ±13V
Power Supply Rejection Ratio
PSRR
Vs ±3V to ±ISV
Large Signal Voltage Gain
Avo
RL ,,2kll, Vo= ±10V
RL ,,5001l, VO= ± 0.5V
Vs = ±3V (Note 3)
Output Voltage Swing
Vo
RL ,,10kll
RL ,,2k!!
RL "lkll
30
14
30
pA p.p
O.SO
0.23
0.17
0.32
0.14
0.12
O.SO
0.23
0.17
pAl,/Hz
60
Mil
200
200
Gil
±13.0 ±14.0
±13.0 ±14.0
V
110
126
dB
30
Input Voltage Range
14
0.32
0.14
0.12
SO
20
110
126
300
500
200
500
150
400
150
400
Vim V
±12.5 ±13.0
±12.0 ±12.S
±10.5 ±12.0
V
4
4
10
±12.5 ±13.0
±12.0 ±12.S
±10.5 ±12.0
10
~VIV
Slewing Rate
SR
RL ,,2kll
(Note 3)
0.1
0.3
0.1
0.3
V/lts
Closed Loop Bandwidth
BW
AVCL= +1.0
(Note 3)
0.4
0.6
0.4
0.6
MHz
Open Loop Output Resistance
Ro
Vo = 0,10 = 0
60
Power Consumption
Pd
Vs = ± 15V, No load
Vs = ± 3V, No load
75
4
Rp= 20kll
±4
Offset Adjustment Range
60
120
6
75
±4
I!
120
6
mW
mV
NOTES:
1. OP-07A grade Vos is measured one minute after application of power. For
all other grades Vas is measured approximately 0.5 seconds after application of power.
2. Long Term Input Offset Voltage Stability refers to the averaged trend line of
Vas vs. Time over extended periods after the first 30 days of operation.
Excluding the initial hour of operation, changes in Vas during the first 30
operating days are typically 2.5p.V - refer to typical performance curves.
Parameter is sample tested.
3. Sample tested.
4. Guaranteed by design.
PAGE 5-48
OP·07 ULTRA· LOW OFFSET VOLTAGE OPERATIONAL AMPLIFIER
ELECTRICAL CHARACTERISTICS at Vs=
±1SV, -SS"CsTAs +12S"C, unless otherwise noted.
OP"()7A
MAX
TYP
MAX
UNITS
(Note 1)
25
60
60
200
~V
TCVos
(Note2)
0.2
0.6
0.3
1.3
TCVos"
Rp=20kO
0.2
0.8
0.3
1.3
0.8
4.0
1.2
5.6
nA
25
8
50
pA/"C
±1.0
±4.0
±2.0
±6.0
nA
8
25
13
50
pA/"C
SYMBOL
CONDITIONS
Input Offset Voltage
Vas
Average Input Offset Voltage
Drift Without External Trl m
With External Trim
OP"()7
TYP
PARAMETER
Input Offset Current
los
Average Input Offset Current
Drift
TClos
Input Bias Current
IB
Average Input Bias Current Drift
TCI B
MIN
INote 21
(Note2)
(Note2)
Input Voltage Range
IVR
Common Mode Rejection Ratio
CMRR
VCM= ±13V
±13.0 ±13.5
Power Supply Rejection Ratio
PSRR
Vs= ±3V to ±18V
Large Signal Voltage Gain
Ava
RL ",2kO, Vo= ±10V
Output Voltage Swing
Va
RL ,,2kO
106
~V/"C
±13.0 ±13.5
123
5
200
MIN
123
150
400
V/mV
±12.0 ±12.6
V
20
400
±12.0 ±12.6
V
106
5
dB
20
~VN
II
....
c;o
II.
0
II)
a:
III
Ii:
::::i
II.
:2
c
NOTES:
...I
C
Z
0
1. OP·07 A grade Vas is measured one minute after application of power. For
all other grades Vas Is measured approximately 0.5 seconds after appliea-
2. Sample tested.
TYPICAL OFFSET VOLTAGE TEST CIRCUIT
TYPICAL LOW FREQUENCY NOISE TEST CIRCUIT
tion of power.
~
a:
III
II.
0
2OOk0
lOon
11'' '
600
>.:...............JoM,---1I---O O~TPUT
>--+--ovo
INPUT REFERRED NOISE ..
*
OPTIONAL OFFSET NULLING CIRCUIT
BURN·IN CIRCUIT
>--.....- - - - - 0 v+
INPUT
7 •
>-----0 OUTPUT
*
*
'PINOUTS FOR p. J ANO Z PACKAGES.
PAGE 5-49
2~ggo 6i&~~00'
""ZOOnV/cm
OP·07 ULTRA·LOW OFFSET VOLTAGE OPERATIONAL AMPLIFIER
ELECTRICAL CHARACTERISTICS
at Vs = ±15V, TA = 25'C, unless otherwise noted.
OP-07C
OP·07E
PARAMETER
SYMBOL CONDITIONS
Input Offset
Voltage
Vos
TYP
MAX
(Note 1)
30
Long Term Vos
Stability
VoslTime (Note 2)
Input Offset
Current
los
Input Bias Current
18
Input Noise
Voltage
e np _p
Input Noise
Voltage Density
en
MIN
Input Noise
Current Density
Input Resistance Differential Mode
Input Resistance Common Mode
Inp.p
In
RIN
Power Supply
Rejection Ratio
150
~V
0.3
1.5
0.4
2.0
0.5
3.0
~V/Mo
0.5
3.8
0.8
6.0
0.8
6.0
nA
±1.8
±7.0
±2.0
±12
nA
0.38
0.65
0.38
0.65
~Vp.p
fo =10Hz
10.3
18.0
10.5
20.0
10.5
20.0
10.0
13.0
10.2
13.5
10.3
13.5
9.6
11.0
9.8
11.5
9.8
11.5
14
30
15
35
15
35
fo=10Hz
0.32
0.80
0.35
0.90
0.35
0.90
fo = 100Hz (Note 3)
0.14
0.23
0.15
0.27
0.15
0.27
fo= 1000Hz
0.12
0.17
0.13
0.18
0.13
0.18
fo = 100Hz (Note 3)
0.1 Hz to 10Hz
(Note 3)
(Note 41
15
50
±13.0
106
PSRR
120
Gil
±14.0
±13.0
±14.0
V
120
94
110
dB
±13.0
123
100
200
500
RL",5001l,
Vo= ± 0.5V
Vs= ±3V (Note 31
150
400
RL ",10kll
±12.5
RL",2kll
±12.0
RL ",lkll
±10.5
±12.0
pAl.JHz
Mil
±14.0
5
pAp-p
31
33
RL ",2kll,
Vo= ±10V
nVI.JHz
7
S
120
160
VS= ±3V
to ±lSV
Vo
60
0.6
VCM= ±13V
Output
Voltage Swing
UNITS
150
±4.0
CMRR
Avo
MAX
60
0.35
RINCM
Large Signal
Voltage Gain
TYP
75
MIN
±1.2
lriput Voltage Range IVR
Common Mode
Rejection Ratio
MAX
O.lHz to 10Hz
(Note 3)
fo =1000Hz
Input Noise
Current
OP-07D
TYP
MIN
20
32
7
120
400
120
100
400
±13.0
±12.0
±13.0
±12.0
±13.0
±12.8
±11.5
±12.S
±11.5
±12.S
32
"VN
400
V/mV
400
V
±12.0
±12.0
Slewing Rate
SR
RL '" 2kll (Note 3)
0.1
0.3
0.1
0.3
0.1
0.3
V/p.a
Closed Loop
Bandwidth
BW
AVCL= +1.0
(Note 3)
0.4
0.6
0.4
0.6
0.4
0.6
MHz
Open Loop Output
Resistance
Ro
Vo=O,lo=O
60
Pd
Vs = ± 15V, No load
Vs = ± 3V, No load
75
4
Power
Consumption
Offset Adjustment
Range
Rp =20kll
60
60
120
6
SO
4
±4
80
4
150
S
±4
NOTES:
±4
Il
150
S
mW
mV
operation. Excluding the initial hour of operation. changes in Vos during
1. Input offset voltage measurements are performed by automated test
equipment approximately 0.5 seconds after application of power.
2. Long Term Input Offset Voltage Stability refers to the averaged trend
line of Vos vs. Time over extended periods after the first 30 days of
the first 30 operating days are typically
2.5~V
manee curves. Parameter is sample tested.
3. Sample tested.
4.
PAGES-50
Guaranteed by design.
- refer to typical perlor-
OP-G7 ULTRA·LOW OFFSET VOLTAGE OPERATIONAL AMPLIFIER
ELECTRICAL CHARACTERISTICS
at Vs= %15V, O·CsTAs +70·C, unless otherwise noted.
OP·07E
PARAMETER
Input Offset
Voltage
Average Input Off·
set Voltage Drift
Without External
Trim
With External
Trim
Input Offset
Current
SYMBOL CONDITIONS
Vos
(Note 1)
TCVos
(Note 2)
TCVOSn
Rp =20k!l (Note 2)
los
OP·07C
TYP
MAX
45
MIN
OP·07D
TYP
MAX
MIN
TYP
MAX
UNITS
130
85
250
85
250
~V
0.3
1.3
0.5
1.8
0.7
2.5
~V1·C
0.3
1.3
0.4
1.6
0.7
2.5
~V/·C
0.9
5.3
1.6
8.0
1.6
8.0
nA
II
....
CjI
Average Input Off·
set Current Drift
TClos
Input Bias Current
la
Average Input Bias
Current Drift
TCla
Input Voltage
Range
IVR
Common Mode
Rejection Ratio
CMRR
Power Supply
Rejection Ratio
MIN
(Note 2)
(Note 2)
8
35
12
50
12
50
pA/·C
±1.5
±5.5
±2.2
±9.0
±3.0
±14
nA
13
35
18
50
18
50
pArc
IL
0
II)
a:
IU
iL
::::i
:IE
±13.0
±13.5
±13.0
±13.5
±13.0
±13.5
V
IL
103
123
97
120
94
106
dB
-'
cC
VCM = ±13V
PSRR
Vs = ±3V to ±18V
Large Signal
Voltage Gain
Avo
RLo.2k!l,
Vo= ±10V
Output
Voltage Swing
Vo
RL o.2k!l
10
32
180
450
100
400
51
10
100
400
51
~VN
V/mV
cC
Z
0
~
a:
IU
IL
0
±12.0
±12.6
±11.0
±12.6
NOTES:
1. Input offset voltage measurements are performed by automated test
equipment approximately 0.5 seconds after application of power.
2. Sample tested.
PAGES-51
±11.0
±12.6
V
OP-07 ULTRA-LOW OFFSET VOLTAGE OPERATIONAL AMPLIFIER
DICE CHARACTERISTICS (125°C TESTED DICE AVAILABLE)
I. BALANCE
2. INVERTING INPUT
3. NON-INVERTING INPUT
4. V-
6. OUTPUT
7. V+
•. BALANCE
Refer to Section 2 for additional DICE Information.
DIE BIZE 0.100 x 0.053 Inch
ELECTRICAL CHARACTERISTICS
TA = +12SoC
for
OP-07NT
and
at Vs = ±1SV, TA = +2SoC for
unless otherwise noted.
OP-07N, OP-07G
and
OP-07GR
devices,
OP-07GT,
PARAMETER
SYMBOL CONDITIONS
Input Offset Voltage
Vos
OP-07NT
LIMIT
OP-07N
LIMIT
40
140
Input Offset Current
los
Input Bias Current
I.
Input Resistance
Differential Mode
RON
Input Voltage Range
IVR
Common Mode
Rejection Ratio
CMRR
VcM =±13.0V
Power Supply
Rejection Ratio
PSRR
Vs = ± 3V to ± 18V
OP-07GT
LIMIT
210
OP-07G
LIMIT
80
OP-07GR
LIMIT
UNITS
150
"V MAX
4.0
2.0
5.6
2.8
6.0
nAMAX
±4.0
±2.0
±6.0
±3.0
±7.0
nAMAX
20.0
8.0
MnMIN
±13.0
±13.0
±13.0
±13.0
±13.0
VMIN
100
110
100
110
100
dBMIN
20
10
20
10
30
"VNMAX
±12.0
±12.0
±11.S
±10.S
±12.0
±11.S
VMIN
20.0
(Note 2)
Output Voltage Swing
Vo
RL = 10kn
RL =2kn
RL = lkn
±12.0
±12.S
±12.0
±10.S
Large Signal
Voltage Gain
Avo
RL = 2kn
Vo =±10V
200
200
150
120
120
VlmVMIN
±30
±30
±30
±30
±30
V MAX
120
150
mWMAX
Differential Input
Voltage
Power Consumption
Po
120
VOUT=OV
NOTE:
1. For 25° C characteristics of OP-07NT and OP-07GT, see OP-07N and OP07G characteristics, respectively.
TYPICAL ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL CONDITIONS
Average Input
Offset Voltage Drift
TCVos
Nulied Input
Offset Voltage Drift
TCVOSn
Average Input
Offset Current Drift
TClos
2.
Guaranteed by design.
at Vs = ±1SV, TA = +2SoC, unless otherwise noted.
OP-07NT
TVP
OP-07N
TVP
OP-07GT
TVP
OP-07G
TVP
OP-07GR
TVP
UNITS
Rs=SOn
0.2
0.2
0.3
0.3
0.7
"VloC
Rs= 5On, Rp= 20kn
0.2
0.2
0.3
0.3
0.7
"VloC
5.0
5.0
8.0
8.0
12.0
pAloC
0.3
VI"s
0.6
MHz
Slewing Rate
SR
R L 2:2kn
Closed Loop
Bandwidth
BW
AVCL =
+ 1.0
0.3
0.3
0.3
0.3
0.6
0.6
0.6
0.6
PAGES-52
OP·07 ULTRA·LOW OFFSET VOLTAGE OPERATIONAL AMPLIFIER
TYPICAL PERFORMANCE CURVES
OPEN-LOOP GAIN VB
TEMPERATURE
OFFSET VOLTAGE CHANGE DUE
TO THERMAL SHOCK
1 1 1 1 1 V~'}15)I I I I
111.1
1
... _f--
I
1
~ BOO 1---+-+----1f--+-+----I-+---1
TA'" 25"C TA = 70·C
~
g400 1--1'::::...+----1I--+-+--+--+--l
_f-"'
-
-
~
~
2OOr--r~--~-1--+--+--+--4
50
TEMPERATURE
1
..
so
~
i r
;!
u
5
OP-07E
~
~
OPT
w
':;
IN 7ife Oil BATH
20
OP-07C
~
~ ~EVICE IMMERSED
100
•
15
w
I
IA I I I
rei
lsoc
Vs = ±15V
~ 10
A" I I
-
TA =
>
~
~~
-
I'~20
o
It
o
~~
-
w
~
I I I I
., BOOI--+-+----1I--+-+--+--+--l
WARM·UP DRIFT
~25
..
100
TIME (SECONDS)
A
o
r~7
U)
II:
W
00
TIME AFTER POWER SUPPL V TURN ON (MINUTES)
ii:
::::i
II.
~
~
....
~
1.0
MAXIMUM ERROR VB
SOURCE RESISTANCE
r----'::..:...:c:.:,:.-=-=:.:.:.,.:...:....:----,
l
TA ==25"C
Vs = :!:15V
I-
--55"C.;; T"
VS=':I-15V
~~81-----~----+-----A
1.2
~25"C
~~6~----+------1---~~
/
$
g~~.~----+----+--~~~
ill
0.1
1.0
10
100
1.0
0.1
MATCHED OR UNMATCHED SOURCE RESISTANCE (kn)
10
AT IVOIFF 1.... '.OV.lla I
0;; 2nA (OP·07A)
.:;: 3nA {0f'-071 . 0;; 7nA IOP-07G , - : ;
I
V
r-~
I-
iii
~
§
u
!
10
i
"
a:
Z
;:
~
20
VS=±1SV -
TA=25"C _
I I I
-20
-10
10
20
30
30
INPUT OFFSET CURRENT VB
TEMPERATURE
2.6
-201
-10
100
10
1.0
MATCHED OR UNMATCHED SOURCE RESISTANCE (kOI
INPUT BIAS CURRENT VB
TEMPERATURE
-30
30
-
OP-07E
100
MATCHED OR UNMATCHED SOURCE RESISTANCE (kOI
INPUT BIAS CURRENT VB
DIFFERENTIAL INPUT VOLTAGE
1
/
//
---- /
OP-07C
V
OP-07A
i
I
/
--/ j
OP·07
~~2~::::::~=:~~~~~~~1
1;
l-
O"Co:;; To;; 70 0 e
VS=±1SV
~
z
o
~
II:
MAXIMUM ERROR VB
SOURCE RESISTANCE
MAXIMUM ERROR VB
SOURCE RESISTANCE
Vs= "5J
VS=':t15J
13
I-
i
::>
u 2
~
OP-07
iii
I-
::>
~
1
OP-07A
~
\
~~
t""-..... ~ ~~ ....... V
V V
r--_
.
-50
TEMPERATURE (OCI
DIFfERENTIAL INPUT VALUE (VOL lSI
OP-07C
1\
OP~7
~ L\:...... r-~
V::
--r- f-"': f-"
OP·07E
rp~f'
100
-611
o
..
rei
TEMPERATURE
PAGE 5-53
100
W
II.
o
OP'()7 ULTRA·LOW OFFSET VOLTAGE OPERATIONAL AMPLIFIER
TYPICAL PERFORMANCE CURVES
INPUT WIDEBAND NOISE vs
BANDWIDTH (0.1 Hz TO
FREQUENCY INDICATED)
TOTAL INPUT NOISE VOLTAGE
vs FREQUENCY
OP·07 LOW FREQUENCY NOISE
1000
E
~
~~,
~
I
_.
\
II
j
-
\
'"'~
V
i RS-O
P
VS""±15V
'.0
~-"5V
TA-+25·C
I-
::"
RESISTORS ~~~t~g~g\
I
(SEE NOISE TEST CIRCUIT)
'0
it
~=1~~!i ~~,:~nOF SOURCE ~
II
Tiil
i
~
,iI: i Ii
10
1.0
0.1
100
1000
FREQUENCY (Hz)
PSRR VB FREQUENCY
CMRR vs FREQUENCY
130
120
'1m
.
ii
I'
!;
:i
i'00
I
:I!I
~! ,
I
~
110
I
1111111
1!loJ.JJ
OP·Q7C
I
. II
,~
9D
I
120
I!l~~1
110
lWl.
~~~I~..~
100 -QP-D7C
ili~,I;
111I ~I!
70
9D
1.0
10
100
1k
10k
~
i
'"
I
I
i !
1-++HlIHI--I-H+IHII--H+RII!I.4+Ht!IiI-t-I+HIII
!I
.. L.J..J.WILJ..lJ..UlWI....I.J.
0.1
'00k
100
FREQUENCY 1Hz)
1.0
10
OPEN LOOP
FREQUENCY RESPONSE
r-
"'""- "-
8D
VSI",.t - -
"-
"- '\.
\
.....
0.'
1
10
100
1k
111k lOOk
FREQUENCY (Hz)
1M 10M
-20
10
100
"'"'-
1k
10k
lOOk
FREQUENCY (Hz)
PAGES-54
±2O
MAXIMUM UNDISTORTED
OUTPUT vs FREQUENCY
-
1111
VS=±15V
TA s +25"C
TA = 26°C
"'-
...............
16
±10
:i1S
POWER SUPPLY VOLTAGE (VOLTS)
28
I I
r-.....
2IlO
10k
VS=,'6V_
8D
-
./
§400
CLOSED LOOP RESPONSE FOR
VARIOUS GAIN CONFIGURATIONS
100
TA" +25·C
,.~J
~6DO
I
i
I-+Hl!IIH+l+!iIlll--l-+
fREQUENCY 1Hz)
12/l
>"
~ 9D 1-HIttlIlII-tt+tlllll:'\--'+
UNTRIMMED OFFSET VOLTAGE
vs TEMPERATURE
85 r---r-r---r-r---r"""Tr---r--,
:- 75
~
g~
.~. so
o
f--
r
V
I ,.
OP·07A
OP-07E
3. OP·07
4, OP-07e
1
--V
OP·07E
.z f-;7'--V-
""~:-~~s
i
h
---
~ --ts~j:2rl-50
o
/
:') r~ ·-1;1
\ \ / V%/
"- f},.\ II) V
~ - - - - J - - ~J...-;;;1'07A
-so
/
\
:Q
~25 I---+--+--j---+--+--j--~~~
5
11-- bt
lit bL
~
OP·07
-
~ IlL.
-I'I--t-+-++-+-t--j--j--i--t-+-i
-16L.~~~-L-L~~~~~~~
so
-so
100
100
1
TEMPERATURE (~C)
TEMPERATURE (Oe)
2
3
4
5
6
7
8
9
10 11
TIME (MONTHS)
TYPICAL APPLICATIONS
HIGH SPEED, LOW Vos COMPOSITE AMPLIFIER
ADJUSTMENT·FREE PRECISION SUMMING AMPLIFIER
RF
EIN
R4
lOkn
Rl
Rl
10kn
"
"
'0
R'
lOkn
R3
lOkn
'0
'3
R5
2.Skn
-:::
*
*
'PINOUTS SHOWN FOR J, P AND Z PACKAGES,
PAGf5-55
~
W
G-
!
-
Z
o
II:
Vas TRIMMED TO -.....--ovo
PAGE 5-59
~
W
COMPENSATION CIRCUITS
"2
Z
0
a:
V
Vs =±15V
IMPROVES REJECTION Of POWER
V
OUTPUT
Q.
0
Op·os PRECISION LOW INPUT CURRENT OPERATIONAL AMPLIFIER
ELECTRICAL CHARACTERISTICS atVs=±15VforG Grade and Vs =±20VforEor F Grades, O·CSTA S+70· C, unless
otherwise noted.
OP·OBE
PARAMETER
SYMBOL CONDITIONS
Input Offset
Voltage
Average Input
Offset Voltage
Drift
OP·OBF
TYP
MAX
Vos
0.10
Tevos
Input Offset
Current
Average Input
Offset Current
Drift
MAX
0.26
0.23
0.50
2.5
lOS
0.08
TCIOS
Input Bias Current
18
IVR
Common Mode
Rejection Ratio
CMRR
Power Supply
Rejection Ratio
PSRR
Large Signal
Voltage Gain
Avo
Vs= ±15V
Output
Voltage Swing
RL ,,10kll
VS= ±15V
RL,,2kll,
VS=±15V
Power
Consumption
Vs= %15V
MAX
UNITS
0.45
0.32
1.4
mY·
1.0
3.5
1.5
10
0.30
0.11
0.60
0.12
6.5
nA
0.50
2.5
1.0
5.0
2.0
50.0
pA/'C
1.0
2.6
1.2
5.2
1.4
6.5
nA
%14.0
100
116
Vs = ±5V to ±15V
RL,,2kll,
Vo= ±10V
RL,,10kll
VO= ±10V
VS= %15V
TYP
±13.5
MIN
OP·OBG
TYP
Input Voltage
Range
MIN
MIN
%13.5 ±14.0
100
116
10
2
%13.5
%14.0
V
80
112
dB
3
10
100
25
100
25
100
60
200
60
200
25
150
±13.0
%14.0
±13.0
±14.0
±13.0
±14.0
±10.0
±12.0
±10.0
±12.0
±10.0
±12.0
60
V/mV
V
9
18
9
18
15
24
LOW FREQUENCY NOISE TEST CIRCUIT (0.1 to 10Hz)
"II<"
+16V
1.5IlF
tOkO
SIB
"II<"
-15V
NOTES:
1000
1.
2.
51 CLOSED MEASURES 8n (Voll.
S1 OPEN MEASURES en AND In (V02). In IS COMPUTED FROM
3.
THE TWO MEASUREMENTS.
COMPENSATION COMPONENTS NOT SHOWN BUT THEY ARE CONNECTEO.
4.
"VN
SEe NOISE PHOTO OF en IN TYPICAL PERFORMANCE CURVES
SECTION.
PAGE 5-60
1M"
'''''''
r
mW
OP-08 PRECISION LOW INPUT CURRENT OPERATIONAL AMPLIFIER
DICE CHARACTERISTICS (125° C TESTED DICE AVAILABLE)
1.
2.
3.
4.
6.
7.
8.
COMPENSATION
INVERTING INPUT
NON-INVERTING INPUT
VOUTPUT
V+
COMPENSATION
+25 C for OP-OSN and OP-OSG. V S= ±20V and T A = +125
+25° C for OP-OSGR. unless otherwise noted.
ELECTRICAL CHARACTERISTICS at VS= ±20V and T A =
OP-OSNT
and OP-OSGT. V S = ± 15V and TA =
•
Refer to Section 2 for additional DICE Information
DIE SIZE 0.058 x 0.042 Inch
0
0
C for
II)
II:
W
u:
UNITS
::i
a..
:::E
Input Offset Voltage
Vos
0.3S
0.3
0.60
O.S
1.0
mVMAX
....I
Input Offset Current
los
0.2
0.2
0.4
0.4
O.S
nAMAX
Input Bias Current
18
nAMAX
Input Voltage Range
IVR
Common Mode
Rejection Ratio
CMRR
Power Supply
Rejection Ratio
PSRR
Output Voltage Swing
Vo
OP-OSN
OP-OSNT
PARAMETER
SYMBOL CONDITIONS
Vs= ±1SV
V cM =±13V
Vs= ±1SV
V s =±SVto±1SV
LIMIT
LIMIT
OP-OSGT
LIMIT
OP-OSG
LIMIT
OP-OSGR
LIMIT
ooC
2.0
2.0
4.0
4.0
5.0
±13.S
±13.S
±13.S
±13.S
±13.S
VMIN
100
104
100
104
64
dB MIN
o
63
"VIV MAX
±13
±10
±13
±10
VMIN
40
10
10
V s =±1SV
Large Signal
Voltage Gain
(V o =±lOV)
Avo
Input Resistance
R'N
Supply Current
RL;e 10kfl
±13
RL;e 2kfl
RL;e Skfl
±10
ISY
±13
±10
±13
±10
RL;e 10kfl
80
80
RL;e 2kfl, Vs = ±1SV
SO
SO
RL;e Skfl, Vs= ±ISV
VOUT=O
V/mVMIN
40
40
(Note 2)
10UT=0, V s =±1SV
2S
0.6
0.6
NOTES:
I. For 25° C characteristics of NT & GT devices, see N & G characteristics,
0.6
2S
10
mflMIN
0.6
0.8
mAMAX
2. Guarante!3d by design.
respectively.
TYPICAL ELECTRICAL CHARACTERISTICS at Vs = ±15V. unless otherwise noted.
OP-OSNT
PARAMETER
Average Input Offset
Voltage Orift
Average Input Offset
Current Drift
SYMBOL CONDITIONS
ooC
Z
o
~
II:
OP-OSN
OP-OSGT
OP-OSG
OP-OSGR
TYPICAL
TYPICAL
TYPICAL
TYPICAL
TYPICAL
UNITS
TCVos
0.5
O.S
1.0
1.0
1.S
"Vice
Telos
0.5
O.S
0.5
O.S
1.0
pAre
PAGE 5-61
W
a..
OP.()8 PRECISION LOW INPUT CURRENT OPERATIONAL AMPLIFIER
TYPICAL PERFORMANCE CURVES
SMALL SIGNAL
TRANSIENT RESPONSE
LOW FREQUENCY NOISE
LARGE SIGNAL
TRANSIENT RESPONSE
R '0, BW '"' O.1Hz to 10Hz
5~V/djv AT READOUT
O.5j..1V/div REFERRED TO INPUT
TRANSIENT RESPONSE TEST CIRCUIT
10pF
10k11
OUT
IN
101cll
100
--,
120
240
,:--.,
PHASE-
"'-' "', C.-3o'1_ 4-•••
C("30pF
......: -'
,
- C.-l00.'....:.. ~
-r-- e:~±16~c
TA· 25
Q
II
C.-,OO.' P. f-----
1"'-
"'-,
~FA
Cf'30pF
,,-
14O§
120100 ~
80'"
OO~
100
12S C
Q
~
I
..
-66°C
1M
1aM
r- r-
.1'
25°C
100
.1
20
,",1k
'Ok 100k
FREQUENCY (Ha)
! 110
~
-- r-.
RL =2kU
40
~
'\:
10
1.'
220
200
'f- ~:I
-20
,
INPUT BIAS CURRENT
AND INPUT OFFSET CURRENT
VI TEMPERATURE
OPEN LOOP GAIN
VI SUPPLY VOLTAGE
OPEN LOOP GAIN AND PHASE
VI FREQUENCY
120
lOOp'
.06
DO L-____
±5
~
_______ L_ _ _ _
±10
±15
SUPPLY VOLTAGE (VOL TSI
PAGE 5-62
~
±20
o
" I"---
-66 -36 -15
5
25 46 86
TEMPERATURE (OCI
86
105
125
OP.()8 PRECISION LOW INPUT CURRENT OPERATIONAL AMPLIFIER
TYPICAL PERFORMANCE CURVES
SUPPLY CURRENT
VB SUPPLY VOLTAGE
POWER SUPPLY
REJECTION RATIO (PSRRI
vs FREQUENCY
SUPPLY CURRENT
VB TEMPERATURE
600
100
...
iD
NO LOAD
'"
•
080
~
-
25"c
-
_55°C
125¢C
~
~
400
~
It~-:t:4=::t::::l,:lTI
is''
;::
!il
~40
is
~
~
~ zoo
a:
~
100
•
±5
CD
~20
1-+-+--+---11-+-+-+--1-1
'i'
a..
.
0
In
a:
w
.L.--'-....L.---L___L--...L.......L.--l.---I--I
±10
±15
SUPPL V VOLTAGE (VOL lSI
-56 -35 -15
±20
5 25 45 95
TEMPERATURE ("'Cl
85 105 125
it
FREQUENCY (Hz)
::;
a..
:2
APPLICATIONS INFORMATION
to (Hz)
The OP-08 series has extremely low input offset and bias
currents; the user is cautioned that stray printed circuit
board leakages can produce significant errors, especially at
high board temperatures. Careful attention to board layout
and cleaning procedure is required to fully realize the OP-08
performance. It is suggested that effects of board leakage
be minimized by encircling the input pins with a conductive
guard ring operated at a potential close to that of the inputs.
This guard ring should be driven by a low impedance source,
such as the amplifier's output for non-inverting circuits or
ground for inverting circuits.
TYPICAL APPLICATIONS
Cl
C
C2
32
0.181'F
0.0181'F
64
0.11'F
0.011'F
125
0.0471'F
0.00471'F
250
0.0221'F
0.00221'F
500
0.0121'F
0.00121'F
1k
O.OO56I'F
560pF
2k
0.00271'F
270pF
4k
0.00151'F
150pF
8k
680pF
68pF
16k
360pF
36pF
OCTAVE EQUALIZER
Cl
~ST_ .-----lll-----,
Because of the low input bias current of the OP-08 the
resistors could be scaled up by a factor of ten, and thereby
reduce the values of C 1 and C2 at the low frequency end. In
addition ten sections as shown above will only draw a combined supply current of 6mA maximum.
.
Rl
10k!}
BILATERAL CURRENT SOURCE
R2
R'
1%
lMa
V,N O-~O---_NI/'----......---=-f
*
2MU
Rl
~
"",m
~.:
1kH
R5
1%
30pF
2M!]
R'
1%
The above circuit is one section of an octave equalizer used
in audio systems. The table shows the values of C 1 and C2
needed to achieve the given center frequencies. This circuit
is capable of 12dB boost or cut as determined by the position of R2.
PAGE 5-63
_ ER4
It '" R3R S
IF Rl=R3 AND R2=R4+R5 THEN
IL IS INDEPENDENT Of VARIATIONS
IN RL
t'L
....
c
z
0
~
a:
w
a..
0
OP·08 PRECISION LOW INPUT CURRENT OPERATIONAL AMPLIFIER
The bilateral current source circuit shown on the previous
page will produce the indicated current relationship to within
2% using 1% values for R1 through RS. This includes variations in RL from 1000 to 20000. The use of large resistors for
R1 through R4 minimizes the error due to RL variations. The
large resistors are possible because of the excellent input
bias cu rrent performance of the OP-OS.
S-POLE ACTIVE FILTER
12.61kSl
o.0047pF
10k"
10k"
11kn
,.""
12
2.7kO
10k"
INPUT
4.42kfl
10kO
38.4kO
4. . .""
10ks)
12
10k"
3.16kO
... p = - \ - 5.pOLE TElECOMM.
FILTERUSING EIGHT OP·08'S,
1Od. I---+- ~~:::F~:;r;:I~~~;:~
ON AN H·P 3551A TEST SET.
" .... I----t-- *03 TYPE
~
RECEIVE. FILTER.
~.I----hr--~~-----4
~d.I---~-+-r-----~
-63.1dB
OO'.L-_ _ _ _ _ _ _L-________
1kHz
10kHz
f {kHz}
~
100kHz
The above realization of a type 03 receive filter is ac·
compllshed using eight OP.Q8's. As can be seen from the
response curve, the >30dB attenuation in the stop band requirement has been met. In addition, the noise performance
of -----i-------f----'
'---1---+--+-<> OUTPUT
PAGE 5-65
OUT{C}
14-PIN HERMETIC DIP
......iii
Ii'
A.
o
III
C
~
Z
III
A.
OP-0910P-11 QUAD-MATCHED 741-TYPE OPERATIONAL AMPLIFIER
ABSOLUTE MAXIMUM RATINGS (Note 2)
Supply Voltage .............................. ±22V
OP-09GR and OP-11GR (Only) ......•........... ±18V
Internal Power Dissipation (Note 1)
V-Package ............................... 800mW
P-Package ............................... 500mW
Differential Input Voltage ...................... '±30V
Input Voltage. . . . . . . . . . . . . . . . . . . . . . .. Supply Voltage
Output Short Circuit Duration . . . . . . . . . . . .. Continuous
(One Amplifier Only)
Storage Temperature Range
V-Package .•..••.••.•••••••••.••••• -65· C to + 150· C
P-Package ......................... -65·C to +125·C
Lead Temperature Range (Soldering, 60 sec.) .... ; 3OO·C
DICE Junction. Temperature (Tjl ....... -65·C to +150·C
Operating Temperature Range
OP-09A, OP-09B, OP-09C • . . . . . . . .. - 55·C to + 125·C
OP-09E,OP·09F,Op·09G .......•...... O·Cto +70·C
OP·11A, OP·11B, OP·11C ........... -55·Cto +125·C
OP·11E,OP·11F,OP·11G •.............. O·Cto +70·C
NOTES:
1. See table for maximum ambient temperature and derating factor.
MAXIMUM AMBIENT
TEMPERATURE
FOR RATING
14-Pin Hermetic DIP IY)
14-Pin Plastic DIP (P)
DERATE ABOVE
MAXIMUM AMBIENT
TEMPERATURE
70·C
10.0mW/·C
42·C
6mW/"C
2. Absolute maximum ratings apply to both DICE and packaged parts. unless
otherwise noted.
MATCHING CHARACTERISTICS at Vs = ±15V, TA = + 25·C, Rss 100ll, unless otherwise noted.
OP-09A, OP-G9E
OP-11A,OP-11E
PARAMETER
SYMBOL
Input Off~et Voltage Match
I1Vos
Common Mode Rejection
Ratio Match
I1CMRR
CONDITIONS
MIN
VCM= ±12V
VCM= ±12V
94
TYP MAX
OP-09B, OP-09F
OP-11B, OP-11F
TYP
MAX
0.5
0.75
MIN
0.8
2.0
mV
1.0
120
20
1.0
120
20
~VN
94
UNITS
dB
MATCHING CHARACTERISTICS at Vs = ±15V, -55·C:S; TA:S; +125°C for OP-09A, OP-09B, OP-11A and OP-11B,
O·C:s; TA:S; +70·C for OP-09E, OP-09F, OP-11E and OP-11F, Rs:S; 1000, unless otherwise noted.
OP-09A, OP-09E
OP-11A,OP-11E
PARAMETER
SYMBOL
Input Offset Voltage Match
I1Vos
Common Mode Rejection
Ratio Match
I1CMRR
CONDITIONS
MIN
VCM= ±12V
VCM = ±12V
94
PAGE 5...
TYP MAX
OP-otIB, OP-09F
OP-11B,OP-11F
MIN
TYP MAX
UNITS
0.6
1.0
1.0
2.5
mV
3.2
20
3.2
20
",VN
110
94
110
dB
OP-09/0P-11 QUAD-MATCHED 741-TYPE OPERATIONAL AMPLIFIER
ELECTRICAL CHARACTERISTICS (Each Amplifier)
at Vs= ::t:15V. TA = 25°C. unless otherwise noted.
OP-09A1E
OP-11A1E
OP-09B/F
OP-11B/F
OP-09CIG
OP-11C/G
MIN TYP MAX
MIN TYP MAX
MIN TYP MAX
PARAMETER
SYMBOL
CONDITIONS
Input Offset Voltage
Vas
Rs",10kll
I nput Offset Current
los
5.5
Input Bias Current
Is
180 300
-
0.30 0.50
-
20
UNITS
0.60
2.5
1.2
5.0
mV
25
50
75 200
nA
300 500
300 500
nA
Input Resistance Differential
Mode
RIN
Input Voltage Range
IVR
Common Mode Rejection Ratio
CMRR
VCM - ±12V. RsS 10kO
Power Supply Rejection Ratio
PSRR
Vs=:l:5 to :I: 15V. RsslOkIl
Output Voltage Swing
Va
RL,,2kll
:1:11 :1:13
:1:11 :1:13
:1:11 :1:13
V
Large Signal Voltege Gain
Ava
RL,,2kll. Vo= :l:l0V
100 650
100 650
50 500
V/mV
(Note 3)
0.20 0.40
0.20 0.40
0.20 0.40
:1:12 :1:13
:1:12 :1:13
:1:12 :1:13
V
100 120
100 120
70 100
dB
4
4
32
Mil
10 .100
32
I'VN
Power Consumption (Note 1)
Pd
Vo=OV
105 180
123 160
210 340
Input Noise Voltage
e np _p
O.lHz to 10Hz
0.7
0.7
0.7
Input Noise Voltage Density
en
f o =10Hz
f o = 100Hz
fo=l000Hz
18
14
12
18
14
12
18
14
12
nVl.JHz
Input Noise Current
Inp-p
O.lHz to 10Hz
17
17
17
pAp.p
Channel Separation
CS
100 130
100 130
130
dB
1.8
1.5
1.2
1.8
1.5
1.2
1.8
1.5
1.2
pAl.JHz"
1.0
V/~
Input Noise Current Density
In
Slew Rate (Note 3)
SR
fo= 10Hz
f o =l00HZ
f o =l000Hz
0.70
1.0
0.70
1.0
0.70
mW
~Vp.p
11
16
11
16
11
16
kHz
1.5
2.0
1.5
2.0
1.5
2.0
MHz
Rlsetlme (Note 2)
t,
Av= +1. VIN=50mV
Overshoot (Note 2)
Os
25
NOTES:
1. Total dissipation for all four amplifiers In package.
2. Sample tsated.
3. Guaranteed by design.
PAGES-17
80 120
15
25
A-
(/.I
II:
W
::;
A-
~
.....
C
Z
~
II:
AVCL= +1.0
15
'l
0
0
Va = 20Vp.p
80 120
......
CD
ii:
BW
Large Signal Eandwldth (Note 3)
Closed Loop Bandwidth (Note 3)
•
80 120
ns
15
%
25
W
A-
0
OP-09fOP-11 QUAD-MATCHED 741-TYPE OPERATIONAL AMPLI.FIER
ELECTRICAL CHARACTERISTICS (Each Amplifier) at Vs= :!:15V, -55·C,,;TA ,,; +125·C, unless otherwise noted.
PARAMETER
SYMBOL
CONDITIONS
Input Offset Voltage
Vos
Rssl0kO
Average Input Offset Voltage
Drift (Note 2)
TCVos
Rssl0kO
OP·09A
OP·11A
OP-09B
OP-11B
OP·09C
OP·11C
MIN TYP MAX
-
Input Offset Current
los
Average Input Offset Current
Drift (Nole 2)
TCios
Input Bias Current
Ie
Input Voltage Range
IVR
Common Mode Rejection
Ratio
CMRR
VcM =±12V, Rs Sl0kO
PoWer SupplY Rejection Ratio
PSRR
Vs= ±5 to :o15V, Rs sl0k[!
Large Signal Voltage Gain
Avo
RL",2kll, Vo= ±10V
-
MIN TYP MAX
MIN TYP MAX
0.40
1.0
1.0
3.5
1.5
2.0
10
4.0
15
4.0
20
40
40
80
250 300
nA
0.30 0.60
·nA/'C
400 800
nA
0.10 0.30
200 375
Output Voltage Swing
Vo
RL ",2kO
Power Consumption (Note 1)
Pd
VO=OV
-
400 650
mV
~V/'C
:012 ±13
:012 ±13
V
100 120
100 120
70 100
dB
32
4
=
0.30 0.60
UNITS
:012 :013
4
50 250
50 250
±11 :013
:011 ±13
115 200
ELECTRICAL CHARACTERISTICS (Each Amplifier) at Vs
-
6.0
10 100
32
~5
100
±11 ±13
115 200
~VIV
V/mV
V
250 400
mW
± 15V, 00 C :0; TA:O; + 700 C, unless otherwise noted.
OP·09E
OP·11E
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
OP·09F
OP·11F
MIN TYP MAX
Input Offset Voltage
Average Input Offset Voltage
Drift (Note 2)
Vos
Rssl0kO
0.40
0.8
0.8
3.0
1.5
TCVos
Rssl0kO
2.0
10
4.0
15
4.0
14
30
40
60
250 300
nA
0.30 0.60
0.30 0.60
nArC
400 800
nA
Input Offset Current
los
Average Input Offset Current
Drift (Note 2)
TClos
0.10 0.30
Input Bias Current
Ie
Input Voltage Range
IVR
Common Mode Rejection
Ratio
CMRR
VCM = ±12V, RsS 10kO
Power Supply Rejection Ratio
PSRR
Vs= ±5 to ±15V, Rs sl0kO
Large Signal Voltage Gain
Avo
RL ",2kO, Vo= ±10V
Output Voltage Swing
Vo
RL",2kO
Power Consumption (Note 1)
Pd
VO=OV
200 350
1. Total dissipation for ali four amplifiers in package.
2. Sample tested.
PAGE 5-68
400 550
6.0
UNITS
mV
~V/'C
±12 ±13
±12 ±13
±12 ±13
V
100 120
100 120
70 100
dB
4
32
4
32
10 100
50 250
50 250
25 100
:011 ±13
±11 ±13
±11 ±13
115 200
NOTES:
OP·09G
OP·11G
MIN TYP MAX
115 200
-
250 400
~VIV
V/mV
V
mW
OP-09/0P-11 QUAD-MATCHED 741-TYPE OPERATIONAL AMPLIFIER
DICE CHARACTERISTICS
(125° C TESTED
DICE AVAILABLE)
OP-09
OP-11
1.
2.
3.
4.
5.
8.
1.
2.
3.
4.
5.
6.
7.
INVERTING INPUT (A)
NON-INVERTING INPUT (A)
OUTPUT (A)
OUTPUT (B)
NON-INVERTING INPUT (B)
INVERTING INPUT (B)
7. V-
9. OUTPUT (C)
10. INVERTING INPUT (C)
SYMBOL CONDITIONS
Inpul Olfsel Voltage
Vos
Input Olfset Current
los
Input Bias Current
I.
Input Voltage Range
IVR
Common Mode
Rejection Ratio
CMRR
..
11. NON-INVERTING INPUT (e)
12. V+
13. NON-INVERTING INPUT (D)
14. INVERTING INPUT (D)
15. OUTPUT (D)
;;;
Ii'
D.
DIE SIZE 0.085 X 0.070 Inch
NOTE:
Either or both V+ pads may be used without any change in performance.
o
See Section 2 for additional DICE Information.
II)
ELECTRICAL CHARACTERISTICS at Vs = ± 15V, TA = + 25° C for OP-09/11 N,
TA = +125°C for OP'-09/11 NT and OP-09/11GT devices, unless otherwise noted.
PARAMETER
•
B. V+
B. INVERTING INPUT (C)
8. NON-INVERTING INPUT (C)
10. OUTPUT (C)
11. V+
12. OUTPUT (D)
13. NON-INVERTING INPUT (D)
14. INVERTING INPUT (D)
15. V+
DIE SIZE 0.OB5 X 0.070 Inch
OUTPUT (A)
INVERTING INPUT (A)
NON-INVERTING INPUT (A)
VNON-INVERTING INPUT (B)
INVERTING INPUT (B)
OUTPUT (B)
II:
W
OP-09/11 G
and
OP-09/11 GR
iL:
::i
devices,
D.
~
C
.....
C
OP-09NT
OP-11NT
OP-09N
OP-11N
OP-09GT
OP-11GT
OP-09G
OP-11G
OP-09GR
OP-11GR
LIMIT
LIMIT
LIMIT
LIMIT
LIMIT
UNITS
1.0
0.5
3.5
2.5
5.0
mVMAX
20
20
50
50
200
nAMAX
300
300
500
500
500
nAMAX
±12
±12
±12
±12
±12
VMIN
100
100
100
100
70
dBMIN
32
32
32
32
100
"VNMAX
Rs" 10kO
VcM =±12V
Rs" 10kO
V s =±5Vto±15V
Z
Power Supply
Rejection RatiO
PSRR
Output Voltage Swi ng
Vo
RL " 10kO
RL = 2kO
±11
±11
±12
±11
±11
±11
±12
±11
±11
±11
VMIN
Large Signal
Voltage Gain
AyO
RL ,,2kO
Vo =±10V
50
100
50
100
50
VlmVMIN
Po
Vour=O
No Load
200
180
200
180
340
mWMAX
Power Consumption
(Four Amplifiers)
Rs" 10kO
NOTE: For 25° C characteristics of NT & GT devices, see N & G characteristics,
respectively.
TYPICAL ELECTRICAL CHARACTERISTICS at
PARAMETER
SYMBOL CONDITIONS
Slew Rate
SR
Unity Gain Bandwidth
GBW
Ay= 1
Vs
= ± 15V, TA = +25°C, unless otherwise noted.
OP-09NT
OP-11NT
OP-09N
OP-11N
OP-09GT
OP-11GT
OP-09G
OP-11G
OP-09GR
OP-11GR
TVP
TVP
TYP
TYP
TYP
1.0
1.0
1.0
1.0
1.0
VI"s
2.0
2.0
2.0
2.0
2.0
MHz
130
130
130
130
130
dB
RL" 2kO
Channel Separation
CS
Ay= 100
f= 10kHz
Rs= lkO
UNITS
PAGE 5-69
o
~
II:
W
D.
o
OP·D9/0P.11 QUAD·MATCHED 741-TYPE.OPERATIONAL AMPLIFIER
TYPICAL PERFORMANCE CURVES
.
OFFSET VOLTAGE VI
TEMPERATURE
I I I
-.10
OFFSET CURRENT VI
TEMPERATURE
J),J
V"-t11V
s ~..
.!
!i
.... ......
i--.1O
~
o
......
-AO
~
......
,/
20
-80 __ -20
'tEMPERATURE rC)
aoo
7110
r--.
/'
lL
V~
-10 -40 -20
NORMALIZED AlC PARAMETERS
VI TEMPERATURE
,..
I
.....
Vs. t1SY
~
_
SLEW RATE
'\
""
BANDWIDTH "'-
..
o
-20
0
20
40
80
20 40 80 80 1ao 120 '40
TEMPERATURE reI
V
/
/
I
TA=+2&"CRL -2kn
_
'00
10
1S
POWER SUPPLY VOLTAGE (:tV)
~~~~~+H~4+
100
V•• "BV
1111 .Pi-.t+tH. TA=2&"C
1-+I. ...,..l"tii,
100
,
7110
/
,..
.
,.
.
OPEN LOOP GAIN VI
SUPPLY VOLTAGE
/
i
80
80
CMRR VI FREQUENCY
ih
lill\!1 111111111 I
I--+MM--t-4'ilF't'-""-0 EO
1) Eo=
Eln1(1 + ::) (- ::) + Ein2 (1 +
~)
With ideal resistors this simplifies to:
E1N2
0 - - - - - - - - - -......
2) Eo =
COMMON MODE REJECTION
Because the dual op amp has a high common mode rejection ratio match, the ability to reject common mode inputs
becomes primarily. a function of resistor ratio matching.
( Eln2 - Ein1) (1 +
~)
provided :: = ::
DIFFERENTIAL OFFSET VOLTAGE
The amplifier's differential Input offset voltage (Eo• 2 - Eo.1)
will be the major error factor. If the individual input offset
voltages are of equal magnitude and polarity they appear as
a common mode input and are rejected.
FIVE POLE ACTIVE FILTER
12.B1kn
3500Hz
"'B
, ..n
''''B
2 2WB
6-POLE TE~ECOMM. FILTeR·
USING TWO or..Q9'S.
1---+- ~~l~E~~:~n~I~:S~':~~
ON AN H.p3&61A TEST SET.
1----+- "D3 TVPE RECEIVE FILTER.
~
30dB
INPUT
4C>IB
....
-53.1dB
IIOdB
1kHz
10kHz
f (kHz)
100kHz
'Okn
38.4kll
'Okn
,.""
The above realization of a type D3 receive filter Is accomplished using two OP-09's. As can be seen from the
response curve, the >30dB attenuation In the stop band
requirement has been met. In addition, the noise performance of --F---oN.C.
0
SIDE......
~
•
OP·10
+IOV
~
11
11
'>--1"----0 N.C.
I.
a.
aurA
.2
v-
I/)
v-
ii:
•
~.;~
.0
";"
'3
5
-18V
INPUT
II
20kG
I.
0
a:
w
:::;
a.
:E
CC
OUT 8
.....
CC
Z
• !-•
L...
0
7
~a:
20kn
w
a.
v+
0
TYPICAL PERFORMANCE CURVES
MATCHING CHARACTERISTICS
TRIMMED OFFSET VOLTAGE
MATCH va TEMPERATURE
~
..
r-
f-- I- Vas TRIMMED TO
f--
f--
NULLING POT" 2OkO
~
~
~30
g I-- ~
p
f--
m
020
r-.
2 O'·lOE
, 01'-1.
•
MATCHING CHARACTERISTICS
CHANNEL SEPARATION
va FREQUENCY
~ 1.0
.50
'40
1
J
III
iii
i ,
., !
"
f
I
l'
!
110
z
~
•
~! I: i~~~cI2
,
!al.2O
_L
> •
r"-I'
i'30
/
,
1)\'
'\.'\
I•
bi
u
4 OP·1OC
I
~
3.
<~v AT 26"c
MATCHING CHARACTERISTICS
TRIMMED MATCHED OFFSET
VOLTAGE DRIFT AS A
FUNCTION OF TRIMMING POT
(Rp) SIZE AND .1Vos
.00
U
2
80
!A r/
80
-50
o
TEMPERATURE
60
rei
• 00
0.2
0.4
0.8
0.8
1.0
1.2
UNTRIMMED OFFSET VOLTAGE MATCH aVos (mVI
(CURVES ARE SYMMETRICAL ABOUT ZERO fOR
< 0)
avos
PAGE 5·79
0. •
'.0
.0
FREQUENCY (kHz)
'00
OP·1D DUAL·MATCHED INSTRUMENTATION OPERATIONAL AMPLIFIER
TYPICAL PERFORMANCE CURVES
MATCHING CHARACTERISTIC
MAXIMUM INPUT ERROR vs
SOURCE RESISTANCE
MATCHING CHARACTERISTIC
MAXIMUM INPUT ERROR vs
SOURCE RESISTANCE
TYPICAL LOW FREQUENCY
NOISE TEST CIRCUIT
~ 10
+16V
~
1011"
~
1000
1.0
I=-"t+hrtll--f--,-rr:.,jjj--,--,,...,.,=;:!
0.1
f;,==::a.~~~~1I§$§~~~
a:
~
a:
a:
2.5Mn
(""10Hz FILTER)
~
~
~
INPUT REfERENCE NOISE '"
25~ .. ~.~ •
ZOOnVlcm
i
0.01 L-..l....w.J.I.I.I.U.......I.....I..J..J..O-'W_J..Ju..J.llLlI
0.1
1.0
100
10
0.01
L-..l....w.J.J.J.w.......J.....I..~.o.JJ1
SOURCE RESISTANCE (kill
OP·10 LOW FREQUENCY NOISE
SOURCE RESISTANCE (knl
INPUT WIDEBAND NOISE
vs BANDWIDTH
(0.1 Hz TO FREQUENCY
INDICATED)
TOTAL INPUT NOISE VOLTAGE
vs FREQUENCY
1000
_ _...JI...UJl
10
~
is 'IIi
~"6V
=
AS' = AS2 = 200kH
THERMAL NOISI! OF SOURCE
RESISTORS INCLUDED
+25~~
TA
EXCLUDED
t:--
V
-
RS'" 0
.....
VS- '15V
TA = 25"C
[ [,I
1.0
1.0
0.1
1.0
0.1
10lI0
100
10
100
10
BANDWIDTH 1kHz)
FREQUENCY 1Hz)
OFFSET VOLTAGE DRIFT
WITH TIME
TYPICAL OFFSET VOLTAGE
STABILITY vs TIME
TRIMMED OFFSET VOLTAGE
vs TEMPERATURE
10
MIN
_ 30
~
r--r-,-...,-,--,--,--,-.,
Vos T::~~~GT~~
~1{2~k'g 25" C
~ 1--+-+-"-+~1-..-
g20
~o
H'--t---7t-l
~
o
w
::>
~ 101--+-+-~~~-f+t~-~~
~'
0.01
TIME (MONTHS)
0.1
1.0
10
TIME (HOURS)
PAGES-8D
100
lk
10k
100 125
--50
TEMPERATURE (OCI
OP-10 DUAL-MATCHED INSTRUMENTATION OPERATIONAL AMPLIFIER
TYPICAL PERFORMANCE CURVES EACH AMPLIFIER
CMRR VI FREQUENCY
130
lrli+
120
112 OP-1OC
I
110
1/20P·1Q
111
110
~
II
'00
,
i
100
,
Ii!
I
i
[I
90
I
so
,
:
100
"
I
,
"
,
BO
~
,
TA'" 25 C
"- ~
!
~ Ii'
j
Ii ".~
Ililil ~,
!
lk
L"s)-
' i
' ,
II
~ I·
~
II
I!,
'I
1/20P-10C
'00
,
TA'" 25 C
llllIJ
I·
I,
so
10
,:I,!
1\;J"M~,~'
II i
iii,
1.0
PSRR VI FREQUENCY
'20
111.lli.I[IJI
CLOSED LOOP RESPONSE
FOR VARIOUS GAIN
CONFIGURATIONS
10k
so
50
0.1
'Ollk
'~
11
o
l\.
";'
IL
o
1\
In
II:
W
-20
'.0
10
FREQUENCY (Hz)
100
1k
'Ok
,0
FREQUENCY (Hz!
lk
'00
10k
tOOk
1M
10M
FREQUENCY (Hz)
iL
:::i
::E
IL
c
c
-'
OPEN LOOP FREQUENCY
RESPONSE
r-
'20
so
'",
40
1000
VSI."S~
-
TA=+25 C
'""-"-
OPEN LOOP GAIN VI
TEMPERATURE
OPEN LOOP GAIN VI POWER
SUPPLY VOLTAGE
I--
1--
r--,--'-,-+--,--=-=r--r-=-'---'
r- T~' +2'5°C -r---t--r-t-+----l
B.. 1--+--1-+-+-+--+-I----i
Loo
2 1--+-+~~~~~~-+-I--+--1
.--.-1-,---,-.,---.-,-..,---,
'ODD
- - VS= '15V -
r--
-""-
BOO I--+--+-+-+--+-t---i
-1---"
~0~+~-+-4-+--+-+-~
~
I---V:/+-+--l-- -.."..~
§ 400 I--I--+--+-+--+--+--f-........:>o.j
"-1\
iii
~
2OD1--+-+-+--+-+-+-1--~
--40
0.1
1
10
100
tk
10k tOOk
1M
10M
±5
fREQUENCY (Hz)
±15
±to
-so
±20
50
TEMPERATURE
POWER SUPPLY VOLTAGE (VOLTS)
MAXIMUM UNDISTORTED
OUTPUT VI FREQUENCY
r-
vs
I
POWER CONSUMPTION VI
POWER SUPPLY
OUTPUT SWING VI LOAD
20
TA~+2~ocl III
VS=:!:15V
t
l. !,JJ II
TA '" +2SOC
VIN = ±10mV
'00
(~C)
+·lllHj
'ODD
=
TA
+2!i"C
Illil
I
POSITIVE SWING
,
V
NEGATIVE SWING
I
/
\
o
0.00'
,
0.1
FREQUENCY (MHz)
'.0
0.1
1/
III; ,
:1
-rtltttl
II
0.01
I'
-t. Ih
11/
'.0
LOAD RESISTANCE TO GROUND (kO)
PAGE 5-81
'0
'.0
I
o
20
4D
TOTAL SUPPLY VOLTAGE, V+ TO V- (VOLTS)
so
z
o
5
II:
W
IL
o
OP·10 DUAL-MATCHED INSTRUMENTATION OPERATIONAL AMPLIFIER
TYPICAL PERFORMANCE CURVES
INPUT BIAS CURRENT VI
DIFFERENTIAL INPUT
VOLTAGE
OFFSET VOLTAGE CHANGE
DUE TO THERMAL SHOCK
30
I I I 1
I I I I
.1
AT IVDIFFI "".OV, 1181 ..:;anA 111,rc;;~·)
vs" ±16V
r-
-la
1 1 1 1
1-1-
-~
f-+- ~A"I I
IA I I I
1-1---
i3
ia:
-"
TA'"25'C TA=70 C
1-1-
~
Vs t15J
IIBI"7nAI1/2OP'lv~ -20
Vos NULLED TO
<&,.IV AT 26°C
.
INPUT BIAS CURRENT VI
TEMPERATURE
-30
b-:J0C-r -
a:
iI>
~
la
I
V
IMMERSED
1-1- ~ DEVICE
IN 7CrC OIL BATH
VS= '16V-
T~'f5
C
80
100
-30
........
1
~ t:-~~",aE ./
'~OP-,aA
20
_
1
~a
20
40
80
TIME (SECONDSI
i
./
['-.
30
-20
-10
0
10
20
30
-2& ....
100 126
01 FFERENTIAL INPUT VALUE (VOL18)
APPLICATIONS INFORMATION
.3
SPECIAL NOTES ON THE APPLICATION OF DUAL·
MATCHED OPERATIONAL AMPLIFIERS
r-
ADVANTAGES OF DUAL MATCHED OPERATIONAL
AMPLIFIERS
.,
Dual Matched Operational Amplifiers provide the engineer a
powerful tool for the solution of a number of difficult circuit
design problems including true Instrumentation amplifiers,
extremely low drift, high common-mode rejection DC amplifiers, low DC drift active filters, dual tracking voltage references and many other demanding applications. These designs
are based on the principle that careful matching between two
operational amplifiers can, to a large extent, eliminate the
effect of DC errors inherent in the individual amplifiers.
Reference to the circuit shown, a differential·in, differentialout amplifier, shows how the reductions in error can be accomplished. Assuming the resistors used are Ideally
matched, the gain of each side will be Identical; if the offset
voltages of each amplifier are perfectly matched, then the
net differential voltage at the amplifiers output will be zero.
Note that the output offset error of this amplifier is not a
function of the offset voltage of the Individual amplifiers,
but only a function of the difference (degree of matching)
between the amplifiers' offset voltages. This error-cancellation prinCiple holds for a considerable number of input referred error parameters - offset voltage, offset voltage
drift, inverting and non-inverting bias currents, common
mode and power supply rejection ratios. Note also that the
impedances of each input, both common mode and dlfferen- .
tial mode, are extremely high and can also be tightly
matched, an important feature not possible with single
operational amplifier circuits. Common-mode rejection can
be made exceptionally high; this is especially important in
*
• ,
1
3
•
+
.
2Ok!l
~v+
-SIDE
......
.....
13
V
OP·10
NPUT
-
11
••
*
la
+
~
V
ouT>UT
•
-
.4
Instrumentation amplifiers where errors due to large common mode voltages can be far greater than those due to
noise or drift with temperature.
(For example, consider the case of two op amps, each with
BOdS (100I'VN) CMRR. However, if the CMRR of one device
is +100I'VN while CMRR of the the other is -100I'VN for a
net 200I'VlV CMRR match, the resultant input referred error
over a 10V common mode input signal will be 2mV.)
POWER SUPPLIES
The V+ supply terminals are completely independent and
may be powered by separate supplies if desired (this approach, however, would sacrifice the advantages of the
power supply rejection ratio matching). The V- supply terminals are both connected to the common substrate and
must be tied to the same voltage.
PAGE 5-82
OP-10 DUAL-MATCHED INSTRUMENTATION OPERATIONAL AMPLIFIER
OFFSET TRIMMING
TYPICAL PERFORMANCE OF
INSTRUMENTATION AMPLIFIERS
GAIN=100
Offset trimming terminals are provided for each amplifier of
the OP-l0 - however, guaranteed performance over temperature can be obtained by trimming only one side (side A)
to match the offset of the other for a net differential offset
of zero_ This is due to the specific procedure used during
factory testing of the devices; however, results which are
essentially the same may be obtained by trimming side B to
match side A, or by nulling each side individually.
20PAMP
DESIGN
PARAMETER
.004%
Gain NonlinBarity
3 DP AMP
DESIGN
.001 % (OP-05)
.002% (OP-Ol)
75~V
Initial Input Offset Voltage
vs. Temperature (amplifier
A nulled with 20k pot)
The OP-l0 is designed to provide lowest drift performance
when trimmed with a 20k{J potentiometer; this value provides about ± 4mV of adjustment range which should be
considerably more than adequate for most applications.
Where finer resolution of trimming is desired, or where unwanted changes in potentiometer position with time and
temperature could create unacceptable offsets, the sensitivity to offset vs. potentiometer position may be reduc by
using the circuit shown below.
O.3~V/·C
3.5~V/month
vs. Time
Input Bias Current
vs. Temperature
Input Offset Current
vs. Temperature
Input Impedance
Differential
Common Mode
3.5~V/month
±1.0nA
±1.0nA
10pAl'C
10pAl'C
O.8nA
0.8nA
v+
Model
OP-10AY, OP·l0Y,
OP-l0EY
RB
RC
NULL
Null Range
NULL
RA, Ra
Potentiometer
Re
5.1k!l
10.0kll
Fixed Resistors
±1.2mV
l00G!l
iL
::::i
l00G!l
l00G!l
:I
z
o
~
II:
14pAp-p
14pAp-p
Common Mode Rejection
120dB
120dB
Power Supply Rejection
112dB
112dB
Small Signal ( - 3d B)
6.0Hz
26kHz (OP-05)
85kHz (OP-Ol)
Full Power
2.5Hz
4.3kHz (OP-05)
43kHz (OP-Ol)
0.17V/~ee
4.0V/~ec
TRIPLE OP-AMP INSTRUMENTATION AMPLIFIER
R4
R6
..."
R1
9k"
Vas"
O.08nlV
Tevos", Q.3!lVrC
NOISE'" O.S#lVP-P
RIN '" 1000n
liN '" ~ 1.0nA
l,
>----0 OUTPUT
R3
2kn
R'
SkU
Your
RS
R7
""'"
PAGE 5-83
=
VIN (1 + Rl
~3R2)
M
GAIN = 100
GAIN LIN = !O.OO2%
SLEW RATE = 2.5V/p.5eC
PSRR = 112dB
"'''
II:
III
Q.
c
....
c
III
(OP-05)
(OP-Ol)
by trimming a Single resistor (R3) and of wide common mode
voltage handling capability at any overall gain, plus improved
gain linearity. Slew rate, small-signal bandwidth, and full
power bandwidth are also superior. Speed may be further
improved by use of an OP-Ol series op amp for the output
stage.
"'''
o
1/1
80GIl
Slew Rate
Instrumentation Amplifiers with excellent performance can
be easily and compactly built using the OP-l0. Typical performance for a two and three-amplifier design are given in
the table. The three-amplifier design, while more complex,
has the advantages of convenient overall gain adjustment
Q.
12pAl'C
Frequency Response
INSTRUMENTATION AMPLIFIERS USING OP-l0
o
";'
12pAl'C
Input Noise Voltage (0.1 to 10Hz)
Input Noise Current (0.1 to 10Hz)
II
IF~=~
THEN CMRR = 120dB
ADJUST R7 FOR MAXIMUM CMRR
Q.
o
OP-10 DUAL-MATCHED INSTRUMENTATION OPERATIONAL AMPLIFIER
CMRR vs FREQUENCY
INSTRUMENTATION AMPLIFIER (3 OJ)-AMP DESIGN)
PRECISION DUAL TRACKING VOLTAGE REFERENCES
USING OP-10
125
Y+
120
I
,~
~Ih
1\
!
..
2. RS = 1oon, 1kn,
UNBALANCED
3. RS
=
20kn,
BALANCED
1.0
10
"5
1\
1 1\1
I
1\
"6
I
1. RS = 100kn,
BALANCED
"4
"2
"z
,
!
lDO
"'
R6"'=:;;:
I
Yl
Y2
II II'
1000.
lDO
fREQUENCY (Hz)
ALSO
see
AN·02
PRECISION DUAL TRACKING VOLTAGE REFERENCES
USING OP-10
INSTRUMENTATION AMPLIFIER (2 OP·AMP DESIGN)
Precision .dual tracking voltage references using a single
reference source are easily constructed using OP-10. These
references exhibit low nOise, excellent stability vs. temperature and time, and have excellent power supply rejection.
In the circuit shown, A3 should be adjusted to set IREF to
operate VREF at its minimum temperature coefficient current. Proper circuit start-up is assured by Rz, Zl, and D1.
VZ1 :;; VREF + 2.0V
IREF = (V1 - VREF)/A3
V1
A2
= VREF (1 +~)
A1
-AS
V2 = V1 ( - )
A4
Output Impedance (.lIL:1.0mA-S.OmA) ... 0.2S.1030
PAGE 5-84
R"
99ka
OP-12
PMI
PRECISION LOW INPUT
CURRENT OPERATIONAL AMPLIFIER
®
INTERNALLY COMPENSATED
FEATURES
GENERAL DESCRIPTION
Low Offset Voltage ................ 150l'V Maximum
Low Offset Voltage Drift .......... 2.51'V/oC Maximum
Load Current Capability ............... 5 mA Minimum
Internal Frequency Compensation
125° C Temperature Tested Ole
Low Offset Current . . . . . . . . . . . . . . .. 200pA Maximum
Low Bias Current . . . . . . . . . . . . . . . . .. 2.0nA Maximum
Low Power Consumption. . .. 18mW Maximum @ ± 15V
High Common Mode Input Range ...... ±13V Minimum
MIL·STD·883 Class B Processing Available
Silicon· Nitride Passivation
ORDERING INFORMATIONt
The PMI OP-12 is an improved version olthe popular LM108A
low-power op amp. The OP-12 is internally compensated and
its chip dimensions are only 42 x 58 mils. Additionally, the
OP·12 has a three times lower offset voltage and a two times
lower offset voltage drift. The total worst case input offset
voltage over-55°C to +125°C for the OP-12Alis only 350l'V
while the 108A has 900l'V to 1000l'V for these conditions. In
addition, the OP-12 drives a 2k!1load. This is five times the
output current capability of the 108A. This excellent performance is achieved by applying PMl's ion-implanted super
beta process and on·chip zener-zap trimming capabilities.
The internal compensation makes this op amp ideal for
hybrid assembly applications.
PACKAGE
II
N
;[
o
III
II:
W
iL
::;
D-
~
CC
....I
CC
Z
o
5
II:
HERMETIC
TA " 2SoC
VosMAX
(mV)
TO-99
8-PIN
DIP
8-PIN
OPERATING
TEMPERATURE
RANGE
0.15
0.15
0.30
0.30
1.0
1.0
OP12AJ"
OP12EJ
OP12BJ"
OP12FJ
OP12CJ"
OP12GJ
OP12AZ"
OP12EZ
OP12BZ"
OP12FZ
OP12CZ"
OP12GZ
MIL
COM
MIL
COM
MIL
COM
W
PIN CONNECTIONS
D-
O
N.C.
s
_INN2?~V:OUT
.. Also available with MIL-STO-8838 processing. To order add/883 as asuffix to
the part number.
t All listed parts are available with 160 hour burn-in. See Ordering Information,
"sc:::tc
v-
4
(CASE)
TO-99 (J-Sufflx)
8-PIN HERMETIC MINI-DIP
(Z-Suffix)
Section 2.
SIMPLIFIED SCHEMATIC
R6
OUTPUT
L---_-+_.......---<>.
R8
PAGES-8S
OP·12 PRECISION LOW INPUT CURRENT OPERATIONAL AMPLIFIER
ABSOLUTE MAXIMUM RATINGS (Note 4)
Supply Voltage
OP·12A, OP·12B,
OP·12E, OP·12F, All DICE except GR. • . • • • . • • •• ±20V
OP-12C, OP-12G, GR DICE Only .••••••...•.••• ±18V
Operating Temperature Range
OP·12A,OP·12B,OP·12C •••.•••.•. -55·Cto +125·C
OP·12E,OP·12F,OP·12G .••.•••.•••••• O·Cto +70·C
Storage Temperature Range •••••••• -65·C to +150·C
Lead Temperature Range (Soldering, 60 sec.) • • ••• 300·C
Internal Power DIssipation (Note 1) • • • • • • . • • • •• 500mW
Differential Input Current (Note 2) •• . ••• . • ••• •• ±10mA
.Input Voltage (Note 3) • • .. .. • • . .. • .... . • .. • . • .• ± 15V
Output Short Circuit Duration • • • • • . • • • • • . • •. Indefinite
DICE Junction Temperature (lj) ....... -65°C to +150°C
ELECTRICAL CHARACTERISTICS at
NOTES:
1. See table for maximum ambient temperatura rating arid derating factor.
Maximum Ambient
Tamperature lor Rating
Package Type
Derate Above Maximum
Ambient Temperature
TO·gg (J)
SO'C
7.1mW/'C
Hermetic
8-Pin DIP (Z)
75'C
6.7mW/'C
2. The Inputs are shunted with back·to·back diodes for overvoltage protec'
tlon. Therefore, excessive current will flow If a differential Input voltage
In excess of tV Is applied between the Inputs unless some limiting
resistance Is provided.
3. For supply voltages less than :I: 15V, the absolute maximum Input
voltage Is equal to the supply voltage.
4. Absolute maximum ratings apply to both DICE and packaged parts, unless
otherwise noted.
Vs = ±20V and TA = 25° C for A,
B. E and
F grades, Vs = ± 15V. and TA =25° C for C
and G grades, unless otherwise noted.
OP-12A1E
PARAMETER
SYMBOL CONDITIONS
Input Offset
Voltage
MIN
OP-12B/F
TYP
MAX
Vos
0.07
Input Offset
Current
los
Input Bias Current
Is
Input ResistanceDifferential Mode
RIN
(Note 1)
Input Voltage
Range
IVR
Vs= ±15V
Common Mode
Rejection Ratio
CMRR
Vcu =±13.0V
Power Supply
Rejection Ratio
.PSRR
Vs =±5Vto :l:15V
Output Voltage
Swing
Vo
RL " 10kO. Vs -±15V :1:13.0
RI.."2kO, Vs =±15V :1:10.0
Large Signal
Voltage Gain
Avo
RL «10kll
VO= ±10V
RL«2kll
Vo= :l:l0V
OP-12C/G
TYP
MAX
TYP
MAX
UNITS
0.15
0.18
0.30
0.25
1.0
mV
0.05
0.20
0.05
0.20
0.08
0.50
nA
0.80
2.0
O.SO
2.0
1.0
5.0
26
70
:1:13·0
±14.0
104
120
MIN
26
10
70
±13.0 :1:14.0
104
MIN
120
Mil
:1:13.0 :1:14.0
V
116
dB
84
7
:1:14.0
±12.0
4
:1:13.0 :1:14.0
±10.0 ±12.0
80
300
80
300
50
150
50
150
nA
50
63
:1:13.0 :1:14.0
±10.0 ±12.0
40
I'VN
V
250
·V/mV
100
Power Consumption Pd
Vs-±15V,NoLoad
Vs =±5V.NoLoad
Input Noise Voltage enp.p
O.IHz to 10Hz
0.9
0.9
0.9
I'Vp.p
Input Noise
Voltage Density
fo=10Hz
fo =I00Hz
fo =10ooHz
22
21
20
22
21
20
22
21
20
nV/.,jHz
en
Input Noise Current Inp-p
Input Noise
Current Density
O.IHz to 10Hz
9
3
18
6
9
3
18
6
12
4
24
8
mW
3
3
3
pAp-p
In
fo= 10Hz
fo = 100Hz
fo=loo0Hz
0.15
0.14
0.13
0.15
0.14
0.13
0.15
0.14
0.13
pAl,JHz
Slewing Rate
SR
RL ,,2kll
0.12
0.12
0.12
V/p.a
Closed Loop
Bandwidth
BW
AveL= +1.0
0.80
O.SO
O.SO
MHz
Open Loop Output
Resistance
Ro
Vo=O,lo=O
200
200
200
II
NOTE:
1. Guaranteed by design.
PAGE 5-86
OP·12 PRECISION LOW INPUT CURRENT OPERATIONAL AMPLIFIER
ELECTRICAL CHARACTERISTICS aIVs=±15V, for C grade, V s =±20Vfor Aand Bgrades,-55°C$TA$+ 125°C, unless
otherwise noted.
OP·12B
OP·12A
PARAMETER
SYMBOL CONDITIONS
MIN
TYP
MAX
UNITS
0.60
2.0
mV
1.0
3.5
1.5
10
0.40
0.12
0.40
0.18
1.0
0.50
2.5
0.50
2.5
1.0
5.0
1.2
3.0
1.2
3.0
1.8
10
MAX
MIN
TYP
InpulOllset
Voltage
Vos
0.t2
0.35
0.28
Average Input
Ollset Voltage
Drift
TCVos
0.50
2.5
Input Ollset
Current
lOS
0.12
Average Input
Ollset Current
Drift
TCIOS
MAX
MIN
II
N
Input Bias Current
Input Voltage
Range
IVR
Common Mode
Rejection Ratio
CMRR
Power Supply
Rejection Ratio
PSRR
Vs= ±5 to ±15V
AvO
RL,,5kll
Vo=±10V
Large Signal
Voltage Gain
OP·12C
0.40
TYP
Vs
= ±15V
±13.0
±14.0
100
116
±13.0 ±14.0
100
116
";"
Q,
o
nA
//I
1&1
±14.0
V
80
112
dB
:::i
Q,
::Ii
p.v/V
...I
u::
CC
Output Voltage
4
Power Consumption Pd
10
10
80
VlmV
o
±13.0
±14.0
±10.0
±13.0
±13.0
±10.0
±14.0
±12.0
V
1&1
40
RL,,10kll, Vs= ±15V±13.0
±14.0
±13.0
18
9
18
15
24
mW
ELECTRICAL CHARACTERISTICS at Vs = ± 15V, for G grade, Vs = ±20V for E and F grades, 0° C $ TA $ 70° C, unless
OP·12E
MIN
MAX
UNITS
0.45
0.32
1.4
mV
1.0
3.5
1.5
10
0.30
0.11
0.60
0.12
0.70
nA
0.50
2.5
1.0
5.0
1.0
5.0
pA/OC
1.0
2.6
1.2
5.2
1.4
6.5
nA
MAX
MIN
TYP
Input Offset
Voltage
Vos
0.10
0.26
0.23
Average Input
Ollset Voltage
Drift
TCVOS
0.50
2.5
Input Ollset
Current
lOS
0.08
Average Input
Ollset Current
Drift
TCIOS
Input Bias Current
Input Voltage
Range
IVR
Vs
Common Mode
Rejection Ratio
CMRR
VCM = ±13.0V
Power Supply
Rejection Ratio
PSRR
Vs= ±5 to ±15V
Large Signal
Voltage Gain
AVO
= ±15V
R L ,,10k!l
Output Voltage
Swing
Power Consumption Pd
Vo=±10V
RL,,2kll
Vo=±10V
RL ,,10k!l
Vs= ±15V
RL ,,5kU
Vs= ±15V
Vs = ±15V, No Load
±13.0 ±14.0
100
Op·12G
OP·12F
TYP
TYP
±13.0 ±14.0
116
4
MAX
100
10
116
4
MIN
±13.0
± 14.0
V
80
112
dB
10
6
25
100
150
60
200
60
200
25
100
25
100
±13.0
±14.0
±13.0
±14.0
±13.0
±14.0
±10.0
±12.0
±10.0
±12.0
±10.0
±12.0
VlmV
80
V
9
18
For typical performance curves, see Op-08 data sheet. Assume
CC= 30pF.
PAGE 5-87
9
18
15
~
a:
Q,
otherwise noted.
SYMBOL CONDITIONS
CC
Z
15
120
Vs = ±15V, No Load
100
120
40
R L ,,5kll, V s =±15V ±10.0
Swing
PARAMETER
a:
±13.0
24
mW
o
OP·12 PRECISION LOW INPUT CURRENT OPERATIONAL AMPLIFIER
DICE CHARACTERISTICS
(125° C TESTED DICE AVAILABLE)
1.
2.
3.
4.
B.
NO CONNECTION
INVERTING INPUT
NON.INVERTING INPUT
VOUTPUT
7. V+
8. NO CONNECTION
DIE SIZE 0.058 X 0.042 Inch
ELECTRICAL CHARACTERISTICS
Refer to Section 2 for additional DICE informalton
at VS= ±15V, TA = +125°C for OP·12NT and OP·12GT, TA =+25°C for OP·12N,
OP·12G and OP·12GR, unless otherwise noted. (Note 2)
OP·12N
LIMIT
Vos
0.35
0.3
0.6
0.5
t.O
mVMAX
Input Offset Current
los
0.2
0.2
0.2
0.2
0.5
nAMAX
Input Bias Current
Ie
2.0
2.0
2.0
2.0
5.0
nAMAX
Input Voltage Range
IVR
±13
±13
±13
±13
±13
VMIN
Common Mode
Rejection Ratio
CMRR
VCM =±13V
100
104
100
104
84
dBMIN
Power Supply
Rejection Ratio
PSRR
Vs= ±5V to ±15V
10
7
10
63
/lVIV MAX
±13
±10
±13
Vo
RL " 10kll
RL " 2kll
RL " 5kll
±13
Output Voltage Swing
±13
±10
±13
±10
VMIN
80
50
40
SYMBOL
Input Offset Voltage
±10
OP·12GR
LIMIT
UNITS
±10
80
R'N
(Note 1)
25
25
13
13
10
Mil MIN
ISY
10UT= 0
VOUT= 0
0.6
0.6
0.6
0.6
0.8
mAMAX
Avo
Input Resistance
VlmVMIN
40
40
NOTES:
1. Guaranteed by design.
TYPICAL ELECTRICAL CHARACTERISTICS
80
50
80
RL " 10kll, Vo= ±10V
RL ,,2kll, Vo =±10V
RL ,,5kll, Vo =±10V
Large Signal
Voltage Gain
Supply Current
CONDITIONS
OP·12GT
LIMIT
Op·12G
LIMIT
OP·12NT
LIMIT
PARAMETER
2. For 25° C specifications of OP·12NT and OP·12GT, see OP·12N and
OP-12G, respectively.
at Vs = ±15V, unless otherwise noted.
OP-12NT
TYPICAL
OP-12N
TYPICAL
OP-12GT
TYPICAL
OP-12G
TYPICAL
OP-12GR
TYPICAL
UNITS
TCVos
1.0
1.0
1.0
1.0
1.5
"woC
TClos
0.5
0.5
1.0
1.0
1.0
pArC
PARAMETER
SYMBOL CONDITIONS
Average Input Offset
Voltage Drift
Average Input Offset
Current Drift
PAGE 5-88
OP·12 PRECISION LOW INPUT CURRENT OPERATIONAL AMPLIFIER
LOW FREQUENCY NOISE TEST CIRCUIT (0.1 to 10Hz)
10k"
.
SIA
(IV02/6AV)2 - (VOl/6Avj 2 - 2f4kT.6.fR Sj'12
_
In -
6
2Rsl
+15V
+1SV
RS
1M"
II
'.5~F
RS
1M"
10""
N
TOkn
SI.
loon
-15V
NOTES:
1.
2.
3.
81 CLOSED MEASURES 8n (Vo11.
81 OPEN MEASURES en AND in (V021. in IS COMPUTED FROM
THE TWO MEASUREMENTS.
COMPENSATION COMPONENTS NOT SHOWN BUT THEV ARE
1M"
CONNECTED.
lOon
r
io
fI)
a:
w
ii:
:i
II.
:::E
c(
~
Z
OFFSET VOLTAGE TEST CIRCUIT
BURN·IN CIRCUIT
o
~
a:
w
II.
o
200k"
~----~-----OVo
PAGE 5-89
OP-15/0P-16/0P-17
PMI
PRECISION JFET-INPUT
OPERATIONAL AMPLIFIERS
FEATURES (All Devices)
•
•
•
•
•
•
•
•
•
•
•
•
Significant Performance Advantages over LF1SS, 156 and
157 Devices.
Low Input Offset Voltage •••.••.•.•••.. SOOpV Maximum
Low Input Offset Voltage Drift •.•.•••••.•..••• 2.0pVr C
Minimum Slew Rate Guaranteed on All Models
Temperature-Compensated Input Bla8 Currents
Guaranteed Input Bias Current @ 1250 C
Bias Current Specified WARMED UP Over Temperature
Internal Compensation
Low Input Noise Current •.•.•.•...••••... O.01pAlVHZ
High Common-Mode Rejection Ratio •..••••••.•• 100dB
Models With MIL-STD-863 Class B Processing Available
From Stock
1250 C Temperature Tested DICE
OP-1S
•
•
•
•
156 Speed With 155 Dissipation ••...•.•. (60mW Typical)
Wide Bandwidth ................................ 6MHz
High Slew Rate.. • • .. .. • .. .. .. .. .. .. .. . . .. . .. .• 17V1ps
Fast Settling to ±O.1% •.••••••.....•.•......•... 900ns
OP-16
• Higher Slew Rate ••••..•..••••••••••••.•••••••• 2SV/ps
• Faster Settling To ±O.1% ......................... 700ns
• Wider Bandwidth ............................... 6MHz
OP-17
• Highest Slew Rate ......................... 70Vlps
• Fastest Settling to ±O.1% ..................... 400ns
• Highest Gain Bandwidth Product ••• . . • • • • • • •• 30MHz
performance to many dielectrically-isolated and hybrid opamps. All devices offer offset voltages as low as 0.5mV with
TeVOS guaranteed to 5pVJ o C. A unique input bias cancellation
circuit reduces the I B by a factor of 10 over conventional
designs. In addition, PMI specifies IBand los with the devices
warmed up and operating at 25°C ambient.
These devices were deSigned to provide real precision performance along with high speed. Although they can be
nulled, the design objective was to provide low offset-voltage
without nulling. Systems generally become more cost effective as the number of error correcting "knobs" is decreased.
PMI achieves this performance by use of an improved BIFET
process coupled with on-chip, zener-zap offset trimming.
The OP-15 provides an excellent combination of high speed
and low input offset voltage. In addition, the OP-15 offers the
speed of the 156A op amp with the power dissipation of a
155A. The combination of a low input offset voltage of 500pV,
slew rate of 17V1ps, and settling time of 900 ns to 0.1 % makes
the OP-15 an op amp of both precision and speed. The additional features of low supply current coupled with an input
bias current of 9nA at 1250 C ambient (not junction) temperature makes the OP-15 ideal for a wide range of applications.
The OP-16 features a slew rate of 25VJps and a settling time of
700 ns to 0.1% which represents a 100% improvement in
speed overthe 156. Also the OP-16 has all the D.C. features of
the OP-15.
GENERAL DESCRIPTION
The OP-17 has a slew rate of 70VJps and is the best choice for
applications requiring high closed-loop gain with high speed.
Applications include high-speed amplifiers for current output DACs, active filters, sample-and-hold buffers, and
photocell amplifiers.
The PM I BI FET Series of devices offers clear advantages over
industry-generic BIFET's and is superior in both cost and
See the OP-215 data sheet for a dual configuration of the
OP-15.
SIMPLIFIED SCHEMATIC DIAGRAM
V+l7Io----r----r--:--,--...--...--r--~-----,--___,
..,
NON-INV (3)
' 'UT
, - - - - - - t - - - t - - o I 6 1 OUTPUT
-NOTE: "7, RI ARE ELECTRONICAL.LV
ADJUSTeD ON CHIP FOR
MINIMUM OFFSET VOLTAGE.
4----'_'-_______
V-(4! ( ) - - ' - - ' - - '_ _ _ _ _ _ _ _ _
PAGE 5-90
~
_ _' -_____-
_
_L._'____'
OP-15/0P-1810P-17 PRECISION JFET-INPUT OPERATIONAL AMPLIFIERS
ORDERING INFORMATIONt
PIN CONNECTIONS
PACKAGE
TA =25'C
VosMAX
(mV)
TO...
a-PIN
a-PIN
HERMETIC
DIP
OPERATING
TEMPERATURE
RANGE
OP15AJ'
OP16AJ'
OP17AJ'
OP15AZ'
OP16AZ'
OP17AZ'
MIL
OP15EJ
OP16EJ
OP17EJ
OP15EZ
OP16EZ
OP17EZ
COM
1.0
OP15BJ'
OP16BJ'
OP17BJ'
OP15BZ'
OP16BZ'
OP17BZ'
MIL
1.0
OP15FJ
OP16FJ
OP17FJ
OP15FZ
OP16FZ
OP17FZ
COM
3.0
OP15CJ'
OP16CJ'
OP17CJ'
OP15CZ'
OP16CZ'
OP17CZ'
MIL
OP15GJ
OP16GJ
OP17GJ
OP15GZ
OP16GZ
OP17GZ
COM
0.5
0.5
3.0
N."
•
BA~L_
7V_
-IN!
+IN 3
+
•
TO-99
(J-Sufflx)
8 OUT
& BAL
v- (CASEI
a-PIN HERMETIC DIP
(Z-Sufflx)
II
(II
II:
W
ii:
::::i
CI.
~
~
z
, Also available with MIL-STD-863B processing. To ordar add/883 as a suffix to
the part number.
t All listed parts are available with 160 hour burn-in. See Ordering Information,
Section 2.
o
fiII:
~
o
ABSOLUTE MAXIMUM RATINGS (Note 2)
Supply Voltage
All Devices Except C, G (Packaged) & GR Grades .. ±22V
C, G (Packaged) & GR Grades ........ , ......... ±18V
Internal Power Dissipation (Note 1) ..... , ......... SOOmW
Operating Temperature
A, B, & C Grades ................... -SS' C to + 12S' C
E, F & G Grades ........................ O'C to +70'C
Maximum Junction Temperature ........•....... +1S0'C
DICE Junction Temperature (Tj) ....... -6S' C to + 1S0' C
Differential Input Voltage
All Devices Except C, G (Packaged) & GR Grades .. ±40V
C, G (Packaged) & GR Grades .................. ±30V
Input Voltage (Note 3)
All Devices Except C, G (Packaged) & GR Grades .. ±20V
C, G (Packaged) & GR Grades .................. ±16V
Input Voltage
OP-1SA, OP,15B, OP·1SE, Op·1SF ... , ... , . . . . .. ±20V
OP·15C, Op·15G ............................ ±16V
Op·16A, OP·16B, OP·16E, Op·16F .... . . . . . . . .. ±20V
OP·16C.Op·16G .................. , . . . . .. ... ±16V
OP·17A, Op·17B, OP·17E, OP·17F •.. . . . . . . . . .. ±20V
OP·17C,OP·17G ........................... , ±16V
Output Short Circuit Duration . . . . . . . . . . . . . .. Indefinite
Storage Temperature Range ........ -6S'C to +150'C
Lead Temperature Range (Soldering, 60 sec.) ... +300'C
NOTES:
1. See table for maximum ambient temperature rating and derating factor.
PACKAGE TYPE
TO"'(J)
B-Pln Hermetic 011' (Z)
MAXIMUM AMBIENT
TEMPERATURE
FOR RATING
DERATE ABOVE
MAXIMUM AMBIENT
TEMPERATURE
80'C
7.1mW/'C
75'C
6.7mWl'C
2. Absolute maximum ratlngupply to both packaged parts and DICE, unless
otherwise noted.
3. Unless otherwise specified the absolute maximum negative Input voltage Is
equal to the negative power supply voltage.
PAGE 5-91
OP-15/0P-1610P-17 PRECISION JFET-INPUT OPERATIONAL AMPLIFIERS
ELECTRICAL CHARACTERISTICS Vs = ± 15V, T,,: = 25 0 C, unless otherwise noted.
OP-1SAlE
OP-16A1E
OP-17A1E
PARAMETER
SYMBOL CONDITIONS
Input Offset Voltage
Input Offset Current
los
TYP
MAX
TYP
MAX
TYP
MAX
UNITS
0.2
0.5
0.4
1.0
0.5
3.0
mV
TJ = 25'C (Note 1)
3.0
5.0
3.0
5.0
10
22
10
25
6.0
10.0
6.0
10.0
20
40
20
50
12
20
12
20
50
100
50
125
pA
15
18
15
20
50
110
50
130
30
40
30
40
100
200
100
250
60
Device Operating
OP-15
OP-16/0P-17
Device Operating
TJ =25'C (Note 1)
Device Operating
Input Bias Current
TJ = 25'C (Note 1)
OP-15
OP-16/0P-17
Device Operating
1012
Input Resistance
Large Signal
Voltage Gain
Ava
Output Voltage
Swing
Supply Current
ISY
Slew Rate
SR
Gain Bandwidth
Product
Closed Loop
Bandwidth
Settling Time
MIN
GBW
CLBW
RL 2:2kO
Vo =±10V
100
RL =10kO
RL =2kO
±12
±13
±11 ±12.7
OP-15
OP-16/0P-17
AVCL = +1.0(Note 3)
OP-15
OP-16
OP-17
(Note 3)
10
18
MIN
75
220
2.7
4.6
400
200
500
200
VlmV
±12
±13
±11 ±12.7
V
50
4.0
7.0
2.8
4.8
5.0
8.0
mA
7.5
12
35
16
24
66
5.0
45
17
25
70
25
15
23
62
4.0
6.0
20
6.0
8.0
30
3.5
5.5
15
5.7
7.6
28
3.0
5.0
11
5.4
7.2
26
MHz
MHz
9.0
OP-15
OP-16
OP-17
14
19
11
13
18
10
12
17
9
to 0.01%
to 0.05% (Note 2)
to 0.10%
2.2
1.1
2.3
1.1
2.4
OP-15
0.9
0.9
to 0.01%
to 0.05% (Note 2)
to 0.10%
OP-16
to 0.01%
to 0.05% (Note 4)
to 0.10%
OP-17
A VCL =+1.0
pA
1012
±12
±13
±11 ±12.7
4.0
7.0
200
80
60
80
10 12
240
2.7
4.6
~~:~:
AVCL = +5.0 (Note 3) OP-17
AVCL =+5.0
t,
OP-1SC/G
OP-16C/G
OP-17C/G
RS= 500
TJ = 25'C (Note 1)
MIN
OP-1SB/F
OP-16B/F
OP-17B/F
1.7
1.7
"0.9
0.9
0.7
0.7
1.5
0.5
0.4
1.5
0.5
0.4
1.2"
1.0
1.8
1.0
0.8
1.6
0.6
0.5
±10.5
Input Voltage Range
IVR
Common Mode
Rejection Ratio
CMRR
VCM =±10.5V
VcM =±10.3V
PSRR
Vs = ±10V to ±18V
Vs = ±10V to ±15V
10
en
fo= 100Hz
fo= 1000Hz
20
15
20
15
20
15
nVly'Hz
fo= 100Hz
'0= 1000Hz
0.01
0.01
0.01
pA/y'Hz
3.0
3.0
3.0
pF
Power Supply
Rejection Ratio
Input Noise
Voltage Density
Input Noise
Current Density
±10.5
I'S
86
100
86
±10.3
82
51
V
100
10
96
51
16
Input Capacitance
dB
80
I'ViV
NOTES:
1.
2.
Input bias current is specified for two different conditions. The T j = 25°C
specification is with the junction at ambient temperature; the Device
Operating specification is with the device operating in a warmed-up condition at 25 Q C ambient. The warmed-up bias current value is correlated to the
junction temperature value via the curves of Ie vs T j and Ie vs T A. PMI has a
bias current compensation circuit which gives improved bias current over
the standard JFET input op amps. Ie and los are measured at V eM = O.
Settling time is defined here for a unity gain Inverter connection using 2kfl
resistors. It is the time required for the error voltage (the voltage at the
inverting input pin on the amplifier) to settle to within a specified percent of
its final value from the time a 10V step input is applied to the inverter. See
settling time test circuit.
3.
Sample tested.
4.
Settling time is defined here for a Av =-5 connection with R F= 2kO.lt is the
time required for the error voltage (the voltage at the inverting input pin on
the amplifier) to settle to within 0.01% of Its final value from the time a 2V step
PAGE 5-92
input is applied to the inverter. See settling time test circuit.
OP-15/0P-16/0P-17 PRECISION JFET-INPUT OPERATIONAL AMPLIFIERS
ELECTRICAL CHARACTERISTICS Vs = ±15V. -55 0 C ~
PARAMETER
SYMBOL CONDITIONS
Input Offset Voltage
Vos
Rs~
TA ~
1250 C. unless otherwise noted.
OP-15A116A117A
MIN TYP MAX
OP-15B/16B/17B
MIN TYP MAX
OP-15C116C/17C
TYP
MAX
UNITS
0.4
0.9
0.7
2.0
0.9
4.5
mV
2.0
5.0
3.0
to
4.0
son
MIN
Average Input
Offset Voltage Drift
Without External
Trim
With External
Trim
(Note 21
TCVos
~VloC
TeVosn
Rp~
l00kn
2.0
125°C
TA~ 125°C
Device Operating
0.6
4.0
0.8
6.0
1.0
9.0
0.8
7.0
1.2
11
1.5
17
TJ~
Input Offset
Current (Note I)
los
OP-15
0.6
OP-16/0P-17
Device Operating
TJ~
125°C
TA ~ 125°C
Current (Note I)
OP-15
Device Operating
18
3.0
4.0
4.0
0.8
6.0
1.3
14.5
5.0
1.5
9.0
2.2
1.2
5.0
2.0
11
1.0
8.5
1.2
1.7
1.0
9"
9.0
1.7
22
7.5
1.8
10
14
2.7
19
125°C
TA~ 125°C
Device Operating
1.5
7.5
1.8
10
OP-16/0P-17
2.5
18
3.0
25
iii
.....
on
9"
":'
a..
0
fII
IE:
W
nA
TJ~
II
...
nA
T J ~ 125°C
TA ~ 125°C
Input Bias
t5
ii:
:::;
a..
:IE
C
..,j
Input Voltage Range
Common Mode
Rejection Ratio
Power Supply
Rejection Ratio
±10.4
IVR
CMRR
PSRR
VCM~±10.4V
85
±10.4
97
85
±10.25
97
VCM ~ ± 10.25V
80
Vs~±10Vto±18V
15
15
57
Avo
Va~±10V
Output Voltage
Swing
Va
RL" 10kn
93
100
~V/v
120
30
110
25
100
VlmV
±12
±13
±12
±13
±12
±13
V
junction temperature value via the curves of Ie vs Tj and 'e VB TA- PMI has a
bias current compensation circuit which gives improved bias current over
the standard JFET input op amps. 'Band los are measured at VCM = O.
2. Sample tested.
PAGE 5-93
Z
~
W
a..
0
35
NOTES:
1. Input bias current is specified for two different conditions. The T j = 25° C
specification is with the junction at ambient temperature; the Device
Operating specification Is with the device operating in a warmed-up condition at 25D C ambient. The warmed-up bias current value is correlated to the
C
0
IE:
23
RL " 2kn
dB
57
Vs ~ ±10V to ±15V
Large Signal
Voltage Gal n
V
OP·15/0P·1610P-17 PRECISION JFET·INPUT OPERATIONAL AMPLIFIERS
ELECTRICAL CHARACTERISTICS
at VS'"
± 15V, O· C :S TA:S 70· C, unless otherwise noted.
OP-1SE
OP-16E
OP-17E
PARAMETER
SYMBOL CONDITIONS
Input Offset Voltage
Vos
Average Input
Offset Voltage Drift
Without External
Trim
With External
Trim
TCVos
MIN
Rs= 500
Input Bias
Current (Note 11
Input Voltage Range
Common Mode
Rejection Ratio
TVP
MAX
TVP
MAX
TVP
MAX
UNITS
0.3
0.75
MIN
0.55
1.5
0.7
3.8
mV
2.0
5.0
3.0
10
4.0
MIN
(Note 2)
15
pV,·C
TCVos.
2.0
Rp= 100kO
TJ =70·C
InputOff.et
Current (Note 11
OP-1SG
OP-16G
OP-17G
OP-1SF
OP-16F
OP-17F
TA = 70·C
Device Operating
los
10
4.0
0.04
0.30
0.06
0.45
0.08
0.65
0.06
0.55
0.08
0.80
0.10
1.2
0.04
0.30
0.06
0.45
0.08
0.65
0.07
0.70
0.10
1.1
0.15
1.7
0.10
0.40
0.12
0.60
0.14
0.80
0.13
0.75
0.16
1.1
0.19
1.5
0.10
0.40
0.12
0.60
0.14
0.80
0.15
0.90
0.20
1.4
0.25
2.0
nA
TJ = 70·C
TA = 70·C
Device Operating
OP-16/0P-17
TJ = 70·C
TA = 70·C
Device Operating
OP-15
nA
TJ = 70·C
TA =70·C
Oevice Operating
IVR
CMRR
OP-15
3.0
OP-16/0P-17
±10.4
85
VcM =±lO.4V
VCM = ±10.25V
±10.4
98
85
±10.25
80
V.=±10Vto±18V
13
57
V
98
13
dB
94
57
Power Supply
Rejection Ratio
PSRR
Large Signal
Voltage Gain
Avo
Rl " 2kO
V o =±lOV
85
200
50
180
35
160
VlmV
Output Voltage
Swing
Vo
Rl " 10kO
±12
±13
±12
±13
±12
±13
V
20
Vs= ±10V to ±15V
NOTES:
1.
Input bilts current is specified for two different conditions. The TJ = 25° C
specification is with the iunctlon at ambient temperature; the Device Operati ng specification is with the device operating in a warmed-up condition at
25° C ambient. The warmed-up bias current value is correlated to the
junction temperature value via the curves of 1avsTJand 1 avsTA' PMI has a
bias current compensation circuit which gives improved bias current over
the standard JFET Input op amps. 1 Band los are measured at VCM = O.
2. Sample tested.
PAGE 5·94
100
pVN
OP·15/0P·16/0P·17 PRECISION JFET·INPUT OPERATIONAL AMPLIFIERS
DICE CHARACTERISTICS (125° C TESTED DICE AVAILABLE)
OP·15
OP-16
OP-17
•
DIE SIZE 0.064 X 0.045 Inch
1.
2.
3.
4.
5.
6.
DIE SIZE 0.064 X 0.045 Inch
BALANCE
INVERTING INPUT
NON·INVERTING INPUT
VBALANCE
OUTPUT
DIE SIZE 0.064 X 0.045 Inch
1. BALANCE
2. INVERTING INPUT
3. NON·INVERTING INPUT
1.
2.
3.
4.
5.
6.
7.
4. V5. BALANCE
6. OUTPUT
7. V+
7. V+
BALANCE
INVERTING INPUT
NON·INVERTING INPUT
VBALANCE
OUTPUT
I/)
II:
.....
ii:
::i
Q.
~
V+
C
....I
C
Z
See Section 2 'or additional DICE in.ormatlon.
o
~
II:
.....
Q.
ELECTRICAL CHARACTERISTICS at Vs = ±15V, TA = +25°C for OP-15/16/17N, OP-15/16/17G and
devices, TA = + 125° C for OP-15/16/17NT and OP-15/16/17GT devices, unless otherwise noted.
PARAMETER
SYMBOL CONDITIONS
Input Offset Voltage
Vas
R s =50n
Large Signal
Voltage Gain
Ava
Vo =±10V
RL =2kn
Input Voltage Range
IVR
Common Mode
Rejection Ratio
CMRR
Power Supply
Rejection Ratio
PSRR
OP-15NT
OP-16NT
OP-17NT
LIMIT
OP-15N
OP·16N
OP-17N
LIMIT
0.9
0.5
OP-15GT
OP-16GT
OP-17GT
LIMIT
2.0
OP·15G
Op·16G
OP·17G
LIMIT
1.0
o
OP-15/16/17GR
OP-15GR
OP-16GR
OP-17GR
LIMIT
UNITS
3.0
mVMAX
35
100
30
75
50
VlmV MIN
±10.4
±10.5
±10.4
±10.5
±10.3
VMIN
VcM=±IVR
85
86
85
86
82
dBMIN
Vs= ±10V to ±20V
57
51
57
51
±12
±12
±11
±12
±12
±11
±12
±11
VMIN
4.0
7.0
5.0
8.0
mAMAX
80
Vs = ±10V to ±15V
MViV MAX
Output Voltage
Swing
Va
RL = 10kn
RL = 2kn
Supply Current
ISY
OP·15
OP·16,OP·17
Input Bias Current
Ie
OP·15
OP·16, OP··17
9.0
11.0
14.0
18.0
nA MAX
los
OP·15
OP·16,OP·17
7.0
8.5
11.0
14.5
nAMAX
Input Offset Current
4.0
7.0
NOTE: For 25°C characteristics of Op·15/16/17NT and OP·15/16/17GT, see
Op·15/16/17N and OP·15/16/17G characteristics, respectively.
PAGE 5·95
OP-15/0P-16/0P-17 PRECISION JFET-INPUT OPERATIONAL AMPLIFIERS
DICE CHARACTERISTICS (continued)
TYPICAL ELECTRICAL CHARACTERISTICS at Vs = ± 15V, TA = +25 0 C, unless otherwise noted.
PARAMETER
SYMBOL CONDITIONS
Average Input Offset
Drift Unnulled
TCVos
Average Input Offset
Drift Nulled
TeVosn
Input Offset Current
Input Bias Current
Slew Rate
OP-15NT
OP-16NT
OP-17NT
TYP
OP-15N
OP-16N
OP-17N
TYP
2.0
Rp= 100kn
OP-15GT
OP-16GT
OP-17GT
TYP
2.0
3.0
OP-15G
OP-16G
OP-17G
TYP
3.0
OP-15GR
OP-16GR
OP-17GR
TYP
UNITS
4.0
MV/'C
2.0
2.0
3.0
3.0
4.0
MVI'C
lOS
3.0
3.0
3.0
3.0
3.0
pA
19
15
15
15
15
15
pA
OP-15
OP-16
OP-17
17
25
70
17
25
70
16
24
66
16
24
66
15
23
62
VlMS
100.01%
100.05%
100.10%
OP-15
2.2
1.1
0.9
2.2
1.1
0.9
2.3
1.1
0.9
2.3
1.1
0.9
2.4
1.2
1.0
100.01%
100.05%
100.10%
OP-16
1.7
0.9
0.7
1.7
0.9
0.7
1.7
0.9
0.7
1.7
0.9
0.7
1.8
1.0
0.8
100.01%
100.05%
100.10%
OP-17
1.5
0.5
0.4
1.5
0.5
0.4
1.5
0.5
0.4
1.5
0.5
0.4
1.6
0.6
0.5
OP-15
OP-16
OP-17
6.0
8.0
30
6.0
8.0
30
5.7
7.6
28
5.7
7.6
28
5.4
7.2
26
MHz
OP_15
OP-16
OP-17
14
19
11
14
19
11
13
18
10
13
18
10
12
17
9
MHz
SR
AVGl =+1
AVCL
Settling Time
I,
(see settling time test circuits)
= +5
MS
Gain Bandwidth
Product
GBW
Closed Loop
Bandwidth
CLBW
Input Noise Voltage
Density
eo
f= 100Hz
f= 1000Hz
20
15
20
15
20
15
20
15
20
15
nVly'Hz
Input Noise Current
Density
io
f= 100Hz
f= 1000Hz
0.01
0.01
0.01
0.01
0.01
0.D1
0,01
0.01
0.01
0.01
pA/y'Hz
Input Capacitance
C'N
3
pF
AVCL = +1
AVCL = +5
3
PAGE 5-96
OP-15/0P-16/0P-17 PRECISION JFET-INPUT OPERATIONAL AMPLIFIERS
TYPICAL PERFORMANCE CURVES (OP-15/0P-16/0P-17)
COMMON MODE INPUT
VOLTAGE RANGE
VB SUPPLY VOLTAGE
OUTPUT VOLTAGE SWING
va LOAD RESISTANCE
30
7
,
IIII
01::'
17
1
~
5
25·C
85"C
2
!J
9
±151-----+-----t-------,/'---T--i
'"
g~
±101-----+----~~___,L-1-----1
1000,----,-----,-----,----,-----,
~
1001-----1----+----t
101-----1----+----t---AtC-:~9
l-
i<
V,i,
•
~
~
:w
±S
POSITIVE
~
0
0.1
'"~
~
-25"C
8
±2Dr------r-----,------r---~
:;
~
I
J
1111
I ~~ =t15V
VOLTAGE NOISE VB
SOURCE RESISTANCE
~
1.0
10
OUTPUT LOAD RESISTANCE (Kfl)
100
~
~
NEGATIVE
UI
a:
°OL-----'~5~----'~,0~---'~1~5----~±20
w
SUPPLY VOLTAGE (VOL TSJ
ii:
:::i
SOURCE RESISTANCE (11)
a.
:::E
INPUT BIAS CURRENT
vs COMMON MODE VOLTAGE
VB
100
i; 5o CDOVERCANCELLED 18 = -t6pA «>,
l-
a:
a:
--
40
""
~
,
20
0
0
-1 0
-20
-30
V
f..-
H-
1
VCM = Of!
~
..
30
i
OPEN-LOOP
VOLTAGE GAIN
SUPPLY VOLTAGE
<])
0
2
4
~
200K
~
g
-
~'25"C
tOOK
7
"- "\
ii:
Q
:;
o
>
\.
3
2
1
"- I"-
""'>-.
II
i
6
0
10K
8 10 12
0
±5
;1;10
OFFSET VOLTAGE DRIFT
va TEMPERATURE OF
REPRESENTATIVE UNITS
'>
.s
::1-3
"z _,
2
'"
~
g
.......
....-" .....::;;.
0
I-
~
TYPICAL DRIFT.
f-BANO
I
I I
r--...
-2
-4
........
30
100
300
><
I--
~ r-- r---
>- -~
.c:.
::::::
P<
-I--
(UNITS AI"
1000
Rp-TRIMMING POTENTIOMETER VALUE (Kn)
-6
-50
-26
25
i
1
75
100
50
TEMPERATURE (OC)
PAGE 5-97
125
r
RMEO UPI
1 1 1
VVV
156AMA~
10nA
155ATV
V
~/
. V VV
InA
VJr
AX
VoP-l~T~P
v~ V
,~ ~ V' vV'
,
l00pA
..y
Vs = ±15V
-5
10
----- --- r:
---- f'--
<20
INPUT BIAS CURRENT vs
AMBIENT TEMPERATURE (UNITS
ARE WARMED-UP IN FREE AIR)
--........
o
-2
/
;:5
:t10
~15
SUPPLY VOLTAGE (VOLTS)
i20
±15
SUPPLY VOLTAGE (VOLTS)
~ -1
ffi
V
a.
!';
~
I,
Ii:
V
/
RL = 2 K n -
IDOnA
8
3>
'"a!
RL = 2K
TA = 2S"C
~
NULLED OFFSET
VOLTAGE DRIFT
vs POTENTIOMETER SIZE
rs
~II!
W
25"C
INPUT COMMON-MODE VOLTAGE (VOLTS)
.3
L
o
-
§
V
,
o
!--------- _55°C
;
'"
v
-12 -10 -8 -6 -4 -2
~ =~
300K
Z
OUTPUT VOLTAGE SWING
VB SUPPLY VOLTAGE
40
1M
90 ttt:WARMEO-UP IN FREE AIRlt±t=
Vs = ±15V
o
TA=2S"C
I I
I I I I I
o 0) UNDERCANCElLED 18 = +16pA (., VCM = 0
eo ,-l......--'>,d---+---l
~ -'0
L-_...L.._.l.J~_..L._...L::~....J
o
0.'
'.0
1.5
SETTLING TIME (pSEC)
PAGE 5-98
2.0
2..
OP-1S/0P-16/0P-17 PRECISION JFET-INPUT OPERATIONAL AMPLIFIERS
TYPICAL PERFORMANCE CURVES (OP-1S)
CLOSED-LOOP BANDWIDTH
AND PHASE SHIFT vs FREQUENCY
,.
18
t-
"12
10
iii
'"
PHASE
90
100
IMA~G1~ ~ I~!
\.
\
w
'"
~ ~
"
-6
\.
-6
2.
140
..,:t 20
150
i"
160
l-
11.
~
130
\
~
Vs = ±15V
"e
1
...........
:;:
CLlEDLt
I _
--
........... ~IDTHAV=+l
o
-50
100
r--
60
25
-25
75
100
100
V~ ±llv
I-- r.....
=
'"
'"w
~ eo
0
>
~
~
40
,
10
100
TEMPERATURE (OCI
FREQUENCY (MHz)
~
lK
•
r\.
2.
-2.
125
TA =25"C-
~
80
!:;
'"-
Av =+1
10
~
VS " ±20V IS <5%
GAIN BANDWIDTH
PRODUCT
r--
:il
OS;;;
z
'
12
Z
180
190
200
±5V
16
\\. II
-10
BANDWIDTH VARIATION FROM
12.
r-...
r---r- i\AV> 10 \
Z
120
28
11.
VS'" ±15V
TA =25°C
OPEN-LOOP
FREQUENCY RESPONSE
BANDWIDTH vs TEMPERATURE
'"
10K
tOOK 1M
~
10M 100M
FREQUENCY (Hz)
III
II:
W
ii:
::;
Do
::Ii
UNDISTORTED OUTPUT SWING
vs FREQUENCY
70
-
Vs = ±16V
TA = 25°C
1\
100
60
J.,
AV=+l
1
~GATIVE
;Ii
1---
"o
lOOk
30
I'-
o
10M
-50
~
is
~
a:
~
t
il
a:
~
~
100
90
50
:
25
60
75
100
0
125
10
-"
"-
TA =
1K
10K
100K
""- "-
OUTPUT IMPEDANCE
vs FREQUENCY
"
30
"-
20
10
IK
10K
lOOK
FREQUENCY (Hz)
1M
~
10M
IW1111,5~
!
~ 100
~
e
80
~
60
w
g
/
"
Illlill
~'20
AV= 10
"-
·ll~l~
/
/
TA
o
10M 100M
VOLTAGE NOISE
vs FREQUENCY
~."C-
""- [\..
1M
FREQUENCY{Hz)
T
'\. POS,4IVeSUPPLY
NEGATIVE
100
100
140
40
10
-25
'"''
!---SUPPlV
50 r---
o
\
VS" ±lSV
TA': 25°C
AMBIENT TEMPERATURE (OCI
POWER SUPPLY REJECTION
vs FREQUENCY
'o"
\
I
10
1M
T
"'26°C
1/1 CORNER FREQUENC
w
!II 40
~
"5V
i
25"C
20
;!;
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11llJl ......L.L111111
IK
10K
lOOK
FREQUENCY 1Hz)
PAGES-99
1M
10M
•
10
~II:
o
1\
20 ~ ~TIVE
FREQUENCY (Hz)
120
-
--- -
i!!
~
AV
Vs = ±15V
o
W
Do
""" i\
- --- -
50
~ 40
ii 110
COMMON-MODE REJECTION
RATIO vs FREQUENCY
SLEW RATE vs TEMPERATURE
c
....
c
z
100
FREQUENCY 1Hz)
IK
10K
OP-15/0P-1610P-17 PRECISION JFET-INPUT OPERATIONAL AMPLIFIERS
TYPICAL PERFORMANCE CURVES (OP-16)
LARGE-SIGNAL
TRANSIENT RESPONSE
SMALL-SIGNAL
TRANSIENT RESPONSE
SETTLING TIME
~
~"
Or---f----r---
w
~
g
-5r---~.---~--_t----t----i
I
2.0
CLOSED-LOOP BANDWIDTH
AND PHASE. SHIFT
va FREQUENCY
Vs
'\
14
1,\
8i--AV';-' 10
\
4
z
;;
"
~
g
-4
MARGIN" 60
\
130
140
f-
6
Z
~
"
Bf--1 0
o
~~--~--~--~--~--~~
-50
-25
FREOUENCY (MHz)
UNDISTORTED OUTPUT SWING
va FREQUENCY
2B
I--1-1\
II
~
BANDWIDTH VARIATION FROM
±5V ~ Vs ~ ±lOV IS <5%
100
~!:~~~
0
26
50
75
TEMPERATURE lOCI
100
125
-20
1\
----
1""-
--
10
1""100
100
N~GATIJE
60
-- -
--
1K
10K lOOK 1M
FREQUENCY (Hz)
AV 0: +1
_ VS= ±15V_
I"
~
- - t--
-l\--
o --
100M
--t--
t---
---
-
l\
Vs= '15V
TA = 25'C
~
o
1M
FREQUENCY 1Hz)
1"-
10M
'\
~ ~OSITIVE
1111<
--f-
1""-
1
r-
COMMON MODE REJECTION
RATIO vs FREQUENCY
SLEW RATE
10
"~V
0
AV= +1
"'-
=
TA"'26ac~
LS
r- 1--
va TEMPERATURE
70
I I_I
---
v;
20
200
10
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1,\
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lBO
1\
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w
160
160
PHiASE
AV" +1
0
-2 --_. - -
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I
I
2
w·
.'5~rtt1
120
PHAS~
iii 6
os
=
120
100
110
TA=2S"C
2
10
OPEN-LOOP
FREQUENCY RESPONSE
BANDWIDTH va
TEMPERATURE
90
t-
Bi '\
16
2.5
~sec
SETTLING TIME -
''''
-50
-25
0
25
50
75
100
AMBIENT TEMPERATURE (OC)
PAGE 5-100
125
0
10
100
lK
10K
100K
FREaUENCYIHzl
1M
10M 100M
OP-15/0P-18/0P-17 PRECISION JFET-INPUT OPERATIONAL AMPLIFIERS
TYPICAL PERFORMANCE CURVES (OP-16)
POWER SUPPLY REJECTION
VB FREQUENCY
120
j
110
o
100
~
90
il
110
a:
t;
~
a:
~
""
'"''
"'. ~ --+--
70
~
60
NEGATIVE
0 - - r-.-SUPPlY
t
40
~
30
0-- -.-
::>
~
I(
..
I~ r'(--
..
100
~,2O
~
TA=2S"C-
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['\..
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~ 801-~-tttlIi---Ii---HltHf--++~ffi-11+#~
A
~
v
~
lK
10K
100K
10M
1M
FREQUENCY (Hz)
lK
I
v
10K
w
,--+fitl
'O
HV ttH-tllI'-V/+-H-tt1JIfV
""-
100 I-hi-tttlIi---li---HltHf--+-+t
~
-POSITIVE - SUPPLY
10
0
10
VOLTAGE NOISE
VI FREQUENCY
- - - --~l~- - ._-_. .. ·····1---
=::::
_
OUTPUT IMPEDANCE
VI FREQUENCY
lOOK
60
1--t-'-'-Mit--t+'-ttTHt-htltt.Jt--+ttttltll
~
40
I--J-i-.-.t+f"",-
~
~r;~~~
I1111111
~
25
z
~
20
~
II
II)
10M
1M
II
a::
w
i&:
FREQUENCY 1Hz)
FREQUENCY (Hz)
::;
D.
:E
C
~
TYPICAL PERFORMANCE CURVES (OP-17)
Z
LARGE-SIGNAL
TRANSIENT RESPONSE
SMALL-SIGNAL
TRANSIENT RESPONSE
o
~
a::
SETTLING TIME
w
D.
+10
~0
"e;
,.
o
Vs = !15V
TA = 2S"C
Av --5
+5
0
IE
'"
z
~
1.0
0.5
1.5
2.5
2.0
3.0
SETTLING TIME (,uSEe)
CLOSED-LOOP BANDWIDTH
AND PHASE SHIFT
VI FREQUENCY
28
"'"''\
,"'
I
1"'-
24
20
16
AV = +5
RS = soon
Rf = 2OOkf2
12
f-
r .-.
f---;
r---t-i
90
Vs = '15V
TA = 25'C
+-++-4+
I
1\1
AV;"SO-:\
I .
-
I
,
OPEN-LOOP
FREQUENCY RESPONSE
BANDWIDTH VB
TEMPERATURE
120
110
- rr.....
,1'1
\,
PHASE MARGIN'" 63
I
I
f+\ l\\
I
:j:
I:
1\
N.." \
I
I
I'
I
1"\
\\,\ i
\\ I
\,1
10
FREQUENCY (MHz)
1
'-
I,
,
'-
1
II,
till
100
-60
-25
25
50
75
TEMPERATURE (QCJ
PAGE 5-101
"',
D-~!:~~~
I I
-20
BANDWIDTH VARIATION
FROM
±5V0;;; Vs';;;; ±20 V IS <5%
100
125
1
10
100
1k
10k lOOk
FREQUENCY 1Hz!
1M
10M 100M
OP-1S/0P-16/0P-17 PRECISION JFET-INPUT OPERATIONAL AMPLIFIERS
TYPICAL PERFORMANCE CURVES (OP-17)
UNDISTORTED OUTPUT SWING
V8 FREQUENCY
2.
Vs'
~ 24
~
AV=+5
'"z
~
~6
"~
~
"
~
=
110
±,.v'+
Ii
TA
2SOC
I........ ...........
ugo
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1\
\
.
12
II
~
!
~
~
~ go
w 70
\
~
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60
4
1
40
'M
,00k
-50 -25
'OM
-
-,
~
100
o
~
SO
-
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is
~;;:
I"
"
"~
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SUPPLY
NE~AlIVE ~U~
c-----40
iil
0:
~
20
10
100
lk
10k
lOOk
-
~
1M
10M
I I
0
7.
50
100
10
12.
100
lk
10k lOOk
140
1111I1
-
~
1
~ 100
"z
w 10
u
S
;'1
e-
1'1
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~
0
bO
:;"
"
60
w
0
Z5"C
1/' CORNER FREOUENC
'"0z
40
~
20
e-
0,1 L-..£JJJ.ll"--Li......c,.L..l.-LUlIL.l..LliillIJ
1k
10k
lOOk
1M
10M
=
O
w
1
:>
I
t~llll! 15~
T
>
1.0
FREQUENCY (Hz)
10M 100M
VOLTAGE NOISE
vs FREQUENCY
~ 120 I--
~
1M
FREQUENCY {Hz)
100
"\.
60
2.
\
VS· ;t16V
TA=Z!i"C
vs FREQUENCY
'A'i5'c .~--
0:
~
----
1\
r-.
OUTPUT IMPEDANCE
POWER SUPPLY REJECTION
vs FREQUENCY
~-
1\
AMBIENT TEMPERATURE ( C)
FREQUENCY (Hz)
120
\
I
50
1\
r--.... r-.......
--r--....
I
I
"'\
VS= "5V-
~ POSITIVE
~
100
L.+.'
........... ~GATIVE
100
20
COMMON MODE REJECTION
RATIO vs FREQUENCY
SLEW RATE
vs TEMPERATURE
o
10
1
FREQUENCY (Hz)
100
lK
10K
FREOUENCY (Hz)
BASIC CONNECTIONS
INPUT OFFSET VOLTAGE NULLING
SETTLING TIME TEST CIRCUIT - OP-15/0P-16
2KSl 0.'%
+16V
V+
:ov ro--+-"',,"vO'.,.".....
'-=-t
..J
Sku
0.'%
VOUT
-16V
Sku 0.1%
2N4416
NOTE: Ves CAN BE TRIMMED WITH POTENTIOMETERS
RANGING FROM 10kUTO 1MU, FOR MOST UNITS
TCVes WILL BE MINIMUM WHEN Vas IS ADJUSTED
WITH A 100kU POTENTIOMETER.
PA~ES-102
+15V
OP-15/0P-16/0P-17 PRECISION JFET-INPUT OPERATIONAL AMPLIFIERS
SETTLING TIME TEST CIRC=-U=-I_T_---=O_P_-1_7_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- - ,
2kn 0.1%
+1SV
:OYo--..--400__
,."
"",0/'y0'_%+--'-1
0.1%
II
-15V
Av= -1
Sk.!!
0.1%
+15V
2N4416
----0
1
fI)
a:
w
u:
::::i
Q.
TYPICAL APPLICATIONS
~
:;!
CURRENT-TO-VOLTAGE AMPLIFIER OUTPUT
order to ensure stability. For example, resistors from the
output to an input should be placed with the body close to
the input to minimize "pick-up" and maximize the frequency
of the feedback pole by minimizing the capacitance from
the Input to ground.
A feedback pole Is created when the feedback around any
amplifier is resistive. The parallel resistance and capacitance
from the input of the device (usually the inverting input) to
AC ground set the frequency of the pole. In many instances
the frequency of this pole is much greater than the expected
3dB frequency of the closed loop gain and consequently
there is negligible effect on stability margin. However, if the
feedback pole is less than approximately six times the ex-
APPLICATION INFORMATION
DYNAMIC OPERATING CONSIDERATIONS
As with most amplifiers, care should be taken with lead
dress, component placement, and supply decoupling in
pected 3dB frequency a lead capacitor should be placed
from the output to the negative input of the op amp. The
value of the added capacitor should be such that the RC
time constant of this capacitor and the resistance it
parallels is greater than,or equal, to the original feedback
pole time constant.
PAGE 5-103
Z
o
~
a:
w
Q.
o
PMI
OP-18
HIGH PERFORMANCE GENERAL PURPOSE
EXTERNALLY COMPENSATED
OPERATIONAL AMPLIFIER
®
FEATURES
•
•
•
•
•
•
•
•
•
Excellent D.C. Input Specifications
Fits Standard 748, 101 and 777 Sockets
Low Noise. . . . . . . . . . . . . . . . . . . . . . .. . . . . .. 0.65 p.Vp-p
Low Drift (TCVoS> .......................... 8p.V/oC
"Premium" 748 and 101 Replacement
-25°C/ + 85°C and - 55°C/ + 125°C Models
MIL·STD·883 Processing Available
SlIicon·Nitride Passivation
Low Cost
GENERAL DESCRIPTION
The OP·18 Series of High Performance General Purpose
Operational Amplifiers provides significant improvements
over industry·standard and "premium" 748, 101 and 777
types while maintaining pin·for·pin compatibility, ease of
application, and low cost. Key specifications, such as Vos,
los, Ie, CMRR, PSRR and Avo, are guaranteed over the full
operating temperature range. Precision Monolithics' ex·
clusive Silicon·Nitride "Triple Passivation" process reduces
"popcorn noise." A thermally·symmetrical input stage
design provides low TCVos. TClos and insensitivity to output load conditions. The OP·18 Series is ideal for upgrading
existing designs where accuracy improvements are required
and for eliminating special low drift or low noise selected
types. OP·18's with MIL·STD-883 processing are available.
The choice of the compensating capaCitor allows the user
to tailor slew rate, open loop bandwidth and maximum un·
distorted output swing for the application.
SIMPLIFIED SCHEMATIC
"Q1, Q2, Q3 AND Q4 FORM A
THERMALLY CROSS..cOUPLED
QUAD. as, OS', Q6 AND 06'
COMPRISE A SIMILAR THERMALLY CROSS·COUPLED QUAD.
-IN
0--------+--------
"N
OUTPUT
R'
R3
R2
R5
PAGE 5-104
RB
OP-18 HIGH PERFORMANCE GENERAL PURPOSE EXTERNALLY COMPENSATED OPERATIONAL AMPLIFIER
ABSOLUTE MAXIMUM RATINGS
(Note 2)
Supply Voltage .•...•..••..•...•.....••......• :l:22V
Power Dissipation (Note 1) ••••••••••••••••.••••• 500mW
Differential Input Voltage .•.......•••..•..•.•... :l:30V
Input Voltage •.•..••...•........••.... Supply Voltage
Output Short Circuit Duration ...........•.••. Indefinite
Operating Temperature Range
OP-18A, OP-18B, OP-18C .•••••..•.•. -55°C to +125°C
OP-18E, OP-18F, OP-18G •.........•..• -25°C to +85°C
DICE Junction Temperature (Tj )
.......
ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL CONDITIONS
Input Offset
Voltage
Vos
-65°C to +150°C
Storage Temperature Range •••...•.•• -65°C to +150°C
Lead Temperature (Soldering, 60 Sec.) •..•........ 300°C
Maximum Ambient
De,ate Above Maximum
Tem!!!,atu .. 10' Ratlns Ambient Tem!!e,atu..
Package Type
TO·99 (J)
S-Pin He,metic DIP (Z)
80'C
75'C
7.1mW/'C
6.7mW/'C
NOTES:
1. See table for maximum ambient temperature rating and derating factor.
2. Absolute maximum ,atings apply to both DICE and packaged parts, unless
otherwise noted .
CD
at Vs = :l:15V, TA =25"C, Cc = 30pF, unless otherwise noted.
MIN
Op·18A
TYP MAX
MIN
OP·18B
TYP MAX
";'
A.
MIN
OP·18C
TYP MAX
0
UNITS
0.3
0.5
1.0
2.0
3.0
5.0
mV
los
0.5
5.0
1.0
6.0
5.0
25
nA
Input Bias Current
Ie
18
50
20
60
30
100
nA
Input ReSistance·
Differential Mode
Rln
Input Voltage
Range
IVR
(Note 2)
CMRR
Power Supply
Rejection Ratio
PSRR
Vs = ±5 to ±20V
Rss2Dkll
Output Voltage
Swing
Vo
RL~2kll
Ava
Rl ;;:2kll
Vo= ±10V
85
Power Consumption Pd
VO=OV
Input Noise Voltage enp .p
O.IHz to 10Hz
Input Noise
Voltage Density
10= 10Hz
10= 100Hz
10= 1000Hz
en
Input Noise Current Inp.p
Input Noise
Current Density
in
Slew Rate
SR
Slew Rate
SR
3.8
7.5
2.3
±13.0
VCM= ±10V
Rs ",20kll
Large Signal
Voltage Gain
III
a:
Rs",20kll
Input Offset
Current
Common Mode
Rejection Ratio
II
±12.0
±13.0
100
250
50
O.IHz to 10Hz
10=10Hz
10 = 100Hz
10 = 1000Hz
Cc = 3pF
1.0
±13.0
100
10
7.0
80
60
95
30
±12.0
±13.0
50
200
go
50
70
100
5.0
Mil
±13.0
V
85
100
dB
150
±12.0 ±13.0
25
go
V
V/mV
150
50
~VIV
90
mW
0.65
0.65
0.65
~Vp.p
25
22
21
25
22
21
25
22
21
nV/-/Hz
12.8
12.8
12.8
pAp.p
1.4
0.7
0.4
1.4
0.7
0.4
1.4
0.7
0.4
pAl-/Hz
(Note 1)
0.25
0.5
0.25
0.5
0.25
0.5
V/~
(Note 1)
2.0
4
2.0
4
2.0
4
V/,.s
Large Signal
Bandwidth
Vo=20Vp.p
(Note 1)
4.0
8.0
4.0
8.0
4.0
8.0
kHz
Closed Loop
Bandwidth
BW
AVCL= +1.0
(Note 1)
0.8
1.3
0.8
1.3
0.8
1.3
MHz
Rlaetime
tr
Av= +1
VIN = SOmV (Note 1)
Overshoot
Os
(Note 1)
200
300
200
300
200
300
ns
15
5
15
5
15
%
NOTE:
1. Sample tested.
2. Guaranteed by design.
PAGE 5-105
W
ii:
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A.
:IE
C
..I
C
Z
0
~
a:
W
A.
0
OP-18 HIGH PERFORMANCE GENERAL PURPOSE EXTERNALLY COMPENSATED OPERATIONAL AMPLIFIER
ELECTRICAL CHARACTERISTICS
at Vs= ±ISV, -SS'C"TA " +12S'C, unless otherwise noted.
Op·18B
OP·18A
PARAMETER
SYMBOL CONDITIONS
Input Offset
Voltage
Vas
Ass20kll
Average Input
Offset Voltage
Drift
TCVos
As = 501l
Input Offset
Current
los
Average Input
Offset Current
Drift
TClos
Input Bias Current
IB
Input Voltage
. Aange
IVA
Common Mode
Rejection Ratio
(Note 1)
TYP
MAX
0.5
MIN
PSAA
Vs = ±5 to ±20V
As s20kll
MAX
1.0
1.4
3.0
2.0
8.0
4.0
10.0
1.0
10.0
2.0
12.0
7.5
75
15
150
30
100
40
120
Large Signal
Voltage Gain
Ava
AL,,2kll
VO= ±10V
Output
Voltage Swing
Vo
AL,,2kll
10
MIN
80
60
95
70
30
TYP
MAX
UNITS
6.0
mV
20
~V/'C
50
nA
30
300
pA/'C
50
200
nA
8
±13.0
95
80
OP·18C
TYP
±13.0
CMAA
Rejection Ratio
-
(Note 1)
VCM= ±10V
Ass20kll
Power Supply
MIN
100
13.0
V
85
dB
100
150
.VN
50
100
25
60
25
60
V/mV
±12.0
±13.0
±12.0
±13.0
±10.0
±13.0
V
NOTE:
1. Sample tested.
ORDERING INFORMATIONt
PIN CONNECTIONS
PACKAGE
TA - 2S'C
VosMAX
(mV)
0.5
0.5
2.0
2.0
5.0
5.0
TO-99
8-PIN
HERMETIC
DIP
8-PIN
OPERATING
TEMPERATURE
RANGE
OP18AJ'
OP18EJ
OP18BJ'
OP18FJ
OP18CJ'
OP18GJ
OP18AZ'
OP18EZ
OPI8BZ'
OP18FZ
OP18CZ'
OP18GZ
MIL
INO
MIL
INO
MIL
INO
COMP
•
COMPEJ.'v+
-IN 2
v-
, Also available with MIL-STO-883B processing. To order add/883 as a suffix to
the part number.
t All listed partsareavailable with 160 hour burn¥in. See Ordering Information,
Section 2.
PAGES-l06
..,
6 OUT
."
4
(CASE)
10·99
(J·Suffix)
8 PIN HERMETIC DIP
(Z·Sufflx)
OP-t8 HIGH PERFORMANCE GENERAL PURPOSE EXTERNALLY COMPENSATED OPERATIONAL AMPLIFIER
ELECTRICAL CHARACTERISTICS
at Vs= :t15V, TA=25°C, C c =30pF, unless otherwise noted.
Op·18F
OP·18E
PARAMETER
SYMBOL CONDITIONS
MIN
TYP
MAX
0.3
Op·18G
TYP
MAX
TYP
MAX
UNITS
0.5
1.0
2.0
3.0
5.0
mV
MIN
MIN
Input Offset
Voltage
Vas
Input Offset
Current
los
0.5
5.0
1.0
6.0
5.0
25
nA
Input Bias Current
Is
18
50
20
60
30
100
nA
Input Resistance·
Differential Mode
Rln
Input Voltage
Range
IVR
Common Mode
Rejection Ratio
CMRR
VCM= ±10V
Rs ,,20kll
Power Supply
Rejection Ratio
PSRR
Vs= ±5 to ±2OV
Rs s20kll
Output Voltage
Swing
Va
RL",2kll
Large Signal
Voltage Gain
Rs,,20kll
(Note 21
7.5
2.3
±13.0
85
7.0
1.0
±13.0
100
10
±12.0
80
30
60
±13.0
95
±12.0
70
100
±13.0
Mil
±13
V
85
dB
'i
0
~VN
en
100
±12.0
II
5.0
150
±13.0
ID
Do.
II:
11.1
VlmV
ii:
:::i
:I
mW
C
V
Do.
AyO
RL '" 2kfl
Vo= ±10V
100
Power Consumption Pd
Vo=OV
Input Noise Voltage enp-p
O.lHz to 10Hz
Input Noise
Voltage Density
'0= 10Hz
'0= 100Hz
= 1000Hz
en
Input Noise Current i np _p
Input Noise
Current Density
3.8
In
Slew Rate
SR
Slew Rate
SR
Large Signal
Bandwidth
50
'0
O.lHz to 10Hz
'o=10Hz
'0= 100Hz
'0 = 1000Hz
Cc =3pF
250
(Note 1)
0.25
(Note 1)
2.0
50
90
25
200
50
150
50
90
90
0.65
0.65
0.65
~Vp.p
25
22
21
25
22
21
25
22
21
nVl,JHz
12.8
12.8
12.8
pAp.p
1.4
0.7
0.4
1.4
0.7
0.4
1.4
0.7
0.4
pAl,JHz
0.5
0.25
0.5
0.25
0.5
VI~s
2.0
4
2.0
4
V1~s
4.0
8.0
4.0
8.0
4.0
8.0
kHz
0.8
1.3
0.8
1.3
0.8
1.3
MHz
BW
AYCL= +1.0
(Note 1)
Rlsetime
Ir
Ay= +1
V1N = 50mV (Note 1)
Overshoot
Os
(Note 1)
200
300
200
300
15
5
15
NOTE:
1. Sample tested.
2. Guaranteed by design.
PAGES-t07
200
..I
Z
0
!;i
II:
11.1
Do.
Vo=2OVp.p
(Noie 1)
Closed Loop
Bandwidth
C
300
ns
15
%
0
OP-18 HIGH PERFORMANCE GENERAL PURPOSE EXTERNALLY COMPENSATED OPERATIONAL AMPLIFIER
ELECTRICAL CHARACTERISTICS
at Vs= ±l,5V, -25°CsTAS +85°C, unless otherwise noted.
Op·18E
PARAMETER
SYMBOL CONDITIONS
Inpui Offset
Voltage
Vos
Rss20kll
Average Input
Offset Voltage
Drift
TCVos
Rs=5OIl
Input Offset
Current
los
MIN
(Note 1)
Op·18F
Op·18G
TYP
MAX
TYP
MAX
UNITS
1.0
1.2
3.0
3
6.0
mV
2.0
8.0
4.0
10.0
8
20
~V1°C
0.7
10
1.4
12
5
50
nA
7.5
120
15
250
70
500
pAloC
22
100
25
120
50
200
nA
TYP
MAX
0.4
MIN
MIN
Average Input
Offset CUrrent
Drift'
Input Bias Current
Ie
Input Voltage
Range
IVR
Common Mode
Rejection Ratio
Power Supply
Rejection Ratio
(Note 1)
TClos
±13.0
±13.0
CMRR
VCM = ±10V
Rss20kll
PSRR
Vs = ±5 to ±20V
Rss20kll
Large Signal
Voltage 'Gain
Avo
Rl ",2k!l
Vo= ±10V
Output
Voltage Swing
Vo
Rl,,2kll
BO
100
10
50
BO
30
BO
100
100
V
85
dB
100
150
~VN
60
15
25
V1mV
±12.0 ±13.0
±10.0
±13.0
V
25
±12.0 ±13.0
70
90
13.0
NOTE:
1. Sample tested.
BURN-IN CIRCUIT
RECOMMENDED COMPENSATION VALUES
CLOSED LOOP GAIN
1000
100
10
COMPENSATION CAPACITOR (CC>
lpF
2pF
5pF
30pF
NOTE:
C c Is connected between pins 1 and 8.
-22V
PAGES-1G8
OP-1B HIGH PERFORMANCE GENERAL PURPOSE EXTERNALLY COMPENSATED OPERATIONAL AMPLIFIER
DICE CHARACTERISTICS
1.
2.
3.
4.
B.
COMPENSATION
INYERTING INPUT
NON-INYERTING INPUT
YOUTPUT
7. Y+
B. COMPENSATION
DIE SIZE 0.044 X 0.041 Inch
Refer 10 Secllon 2 for addilional DICE Informallon.
ELECTRICAL CHARACTERISTICS at Vs = ±15V, TA = +25°C for N, G and GR, unless otherwise noted.
II
CD
"';"
PARAMETER
SYMBOL
CONDITIONS
OP-18N
OP-18G
LIMITS
LIMITS
a.
OP-18GR
LIMITS
UNITS
Input Offset Voltage Range
Vos
0.5
2.0
5.0
mVMAX
Input Offset Current
los
5.0
6.0
25
nAMAX
Input Bias Current
I.
50
60
100
nAMAX
Input Voltage Range
IVR
±13
±13
±13
V
85
60
70
dB MIN
60
100
150
~VNMAX
±12
±12
±12
VMIN
Rs 520kll
CMRR
VCM=±10V
R s 520kll
Power Supply
Rejection Ratio
PSRR
Vs = ±5V to ±20V
Rs520kll
Output Voltage Swing
Vo
RL ,,2kll
Common Mode
Rejection Ratio
0
II)
a:
UI
iL
:::::;
a.
::::E
00(
...I
00(
Z
0
~a:
UI
a.
0
Large Signal
Voltage Gain
Avo
RL ,,2kll
Vo =±10V
Power Consumption
Pd
Vo=OV
TYPICAL ELECTRICAL CHARACTERISTICS at Vs
100
50
25
VlmVMIN
90
90
90
mWMAX
= ± 15V, TA = + 25°C, unless otherwise noted.
OP-18N
PARAMETER
SYMBOL
Input Resistance
Differential Mode
Rin
CONDITIONS
TYP
7.5
enp-p
0.1 Hz to 10Hz
0.65
Input Noise Voltage Density
en
'.= 10Hz
'0= 100Hz
'0= 1000Hz
25
22
21
Input Noise Current
inpRp
O.lHz to 10Hz
Input Noise Current Density
in
'0= 10Hz
'0 = 100Hz
'0= 1000Hz
Slew Rate
SR
Slew Rate
SR
Input Noise Voltage
Large Signal Bandwidth
Cc =3pF
OP-18G
TYP
OP-18GR
TYP
UNITS
7.0
5.0
Mil
0.65
0.85
Il VF!::.P
25
22
21
25
22
21
nVl$.
12.8
12.8
12.8
PAp-e
1.4
0.7
0.4
1.4
0.7
0.4
1.4
0.7
0.4
pAl$.
0.5
0.5
0.5
VI~S
4
4
4
VII'S
Vo =20Ve•p
8.0
8.0
8.0
kHz
Closed Loop Bandwidth
BW
AVCL =+1.0
1.3
1.3
1.3
MHz
Risetime
tr
Av=+1
V'N=50mV
200
200
200
nS
Overshoot
Os
Rs=501l
2.0
4.0
8.0
p.VlGC
7.5
15
70
pA/GC
Average Input Offset
Voltage Drift
TCVos
Average Input Offset
Current Drift
TClos
%
PAGES-109
OP·18 HIGH PERFORMANCE GENERAL PURPOSE EXTERNALLY COMPENSATED OPERATIONAL AMPLIFIER
TYPICAL PERFORMANCE CURVES
INPUT WIDEBAND NOISE
BANDWIDTH l 0.1 Hz TO
FREQUENCY INDICATED)
INPUT SPOT NOISE
CURRENT VB FREQUENCY
INPUT SPOT NOISE
VOLTAGE VB FREQUENCY
VB
100
1000
10
±15~~
'
VS" ±15V
TA
RS ..
1111111
,TYPICAL
Vs -
25°C
CC ..
t=
t--
TA = 26"C
son
Cc - 30pF
to
!
30pF
,
~
0
z
I
c'
II
'
:
,;
~
I
1
','
I
0
"u
.....
1.0
10
FREOUENCY 1Hz)
100
1000
0.01
0.10
1.0
10
,.
~:!:IIH:::t-!-Ill-W-t1I~A I. ~,~II
~ 25"~
~-+t1K-tt-++ttt--il Cc = 3~~
~ ~
1.0
10
100
BANDWIDTH (kHz)
INPUT RESISTANCE VB
TEMPERATURE
;"S'~'V~ !.:,~~
f-""'
NEGATIVESW
100
FrfTl'q~~~~~~
~~ •. ~
--=
.. - - r--r--'r-- --- t--j-
ING
I~
II
8
'0. 1
0.1
VS=:!:lSV
~'2~-HH-~~~-+~1~1~~~
!1
1000
OUTPUT VOLTAGE VB
LOAD RESISTANCE
TA
14
I~S' ±l.V
!
100
FREQUENCY (Hz)
MAXIMUM UN DISTORTED
OUTPUT VB FREQUENCY
16
il
I
0.1
0.10
1:15V
TYPICAL
.~
0,01
Vs
TA'"' +2SOC
t-
J
1\
'l
1\
I-+--+--i--- t - ---t-t--t--1--1
o
lk
10k
100k
1M
0.1
10M
FREQUENCY (Hz)
POWER CONSUMPTION
VB POWER SUPPLY
1000
TA-2.'C:
1.0
LOAD RESISTANCE TO GROUND (km
10
0·~-L-..l--20-"---'--+-=2O:--'-+60':-.L-+:':100:-L.-+~'40
TEMPERATURE re)
POWER CONSUMPTION
VB TEMPERATURE
OUTPUT SHORT·CIRCUIT
CURRENT VB TIME
JRl
so
36
TA" +25~C
Vs"'±16V
VS=±15V
I OP-18 A,B,C
'\
I
ij'00
i
..
~
t - t-bv,N)PIN 31'.
'i
I-
rO
-l.~.F,G
1\
f'.
10
I"- ..... r1.0
20
40
80
TOTAL SUPPL Y VOLTAGE, V+ TO V- (VOLTS)
35
-80
-lL, vL +lL -
(%) VIN(PIN 3) = +10mV, Vo = -16V
r-
-
+20
+60
+100
TEMPERATURE (·e)
PAGE 5·110
~
\ I'\.
+140
•
I"I'-........
TIME fROM OUTPUT BEING SHORTED (MINUTES)
OP-18 HIGH PERFORMANCE GENERAL PURPOSE EXTERNALLY COMPENSATED OPERATIONAL AMPLIFIER
TYPICAL PERFORMANCE CURVES
UNTRIMMED OFFSET VOLTAGE
vs TEMPERATURE
INPUT OFFSET CURRENT
vs TEMPERATURE
INPUT BIAS CURRENT
vs TEMPERATURE
2.'
2.0
1.5
70
K
--
I--~ ---
~
"-
1.0
I"-- ........
0.'
-60
-20
+20
+60
+100
300
v~ • ,;'V
c~
""-
~
........
OP·18F
"ffi
E. 50
~~
+20
I,
~
r--...
::>
r---..
~ 30
>-
OP.18B
-4-
~ 20
._.-
OP-l8E
-20
Vs = i15V
--- TA = 25°C
100
-++\.-~
f---
-~
150
\.
-
40
40
20
20
c~ •
I
c~ "' 30p~
+140
10
TEMPERATURE (DC)
-
RL = 10k
Cc '" 30pF
10k
lOOk
1M
10
10M
110
/'
..........
~~;~~II. ~~I;~~I
100
'""\
10k
100
100
I
I
90
I
90
1
80
~~;~~II& ~~I,I~~1
lOOk
1M
11111111
110
TA'" 2SOC
Cc = 30pF
200
IL
lk
~
,
CC=5PF~ '\\
III
T~"~I 2SOC
U 1m
Cc = 30PF
I Jllil r\
I
Ir\
oj ,IJJ ~I
-
-
r-- r--
--
,5
..
~-
,'0
_.-
-..
-~
,"
POWER SUPPLY (VOLTS)
I
Ii
:t,
1
i! i'
80
70
:
IJI
"
II
100
~-
10M
PSRR vs FREQUENCY
'20
U~II!I~.J
o~,I~~I~1 o~
=3~
FREQUENCY (Hz)
CMRR vs FREQUENCY
120
300
TA! 25°C I
lk
FREQUENCY {Hz}
OPEN LOOP GAIN vs
POWER SUPPLY VOLTAGE
-
100
Cc
I
-20
+100
+60
Z
o
~
a:
~-
1
70
I
-.-~
~
±20
1
60
.
60
r\
50
10
100
1k
FREaUENCY (Hz)
PAGE5-111
10k
lOOk
10
100
'k
FREQUENCY (Hz)
10k
a:
w
Li:
::::i
A.
---
2PF
III
~
c(
...J
c(
Vs""V
-:~:
~~kCn ~
_
Cc = lpF
60
50
+20
+140
±_±
~-
100
-20
oJ {aAI-
-
---T---T--
ao
~
;[
o
FREQUENCY RESPONSE
FOR VARIOUS
CLOSED LOOP GAINS
RL;;o 10kD.
./
...
+20
+60
+100
TEMPERATURE ("C)
120
120
~
~P.18B
I
+1-40
+100
---~
---
10
T
II
~
OP·18F
........
r.......
o:;,aA
+60
"- r-....
/'
60
a
I
Cc '" 30pF
200
-+,
OPEN LOOP VOLTAGE GAIN
AS A FUNCTION OF
FREQUENCY FOR VARIOUS
GAIN/COMPENSATION OPTIONS
OPEN LOOP GAIN
vs TEMPERATURE
......
--
TEMPERATURE reI
TEMPERATURE (nC)
250
-
~ 40
-20
+140
---
100k
w
A.
o
PMI
OP-20
MICROPOWER PRECISION
OPERATIONAL AMPLIFIER
®
SINGLE OR DUAL SUPPLY
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
Low Supply Current ........................... 40!,A
Single Supply Operation. . . . . . . . . . . . . .. + 3V to + 30V
Dual Supply Operation. . . . . . . . . . . . . .. ± 1.5V to ± 15V
Low Input Offset Voltage ...................... 55!'V
Low Input Offset Voltage Drift ............. O.75!,V/ o C
High Common Mode Input Range ... V- toV+ (-1.5V)
High CMRR and PSRR ...................... HOdB
High Open Loop Gain. . . . . . . . . . . . . . . . . . . . . .. 126dB
±30V Input Overvoltage Protection
No External Components Required ........ Easy to Use
Single Chip Monolithic Construction
741 Pinout and Nulling
operation. Offset voltages as low as 250!'V maximum and
offset voltage drifts as low as 1.5!,V/o C maximum are available
with supply currents ranging between 45!,A and 95!,A maximum. Common-mode input voltage range includes ground
to accommodate low, ground·referenced inputs from strain
gauges or thermocouples. The OP-20 pinout and offset
nulling technique is identical to the industry standard 741
device, offering an instant system upgrade in many applica·
tions. The monolithic construction makes the OP·20 ideal
for use in hybrid designs, replacing devices such as the
LM108, LMl12, LM4250, ICL8021 and others.
PIN CONNECTIONS
GENERAL DESCRIPTION
The OP·20 is a monolithic precision micropower operational
amplifier that can be used either in single or dual supply
ORDERING INFORMATION
t
N.C.
B
BAL9'v+
~
-IN 2
6 OUT
PACKAGE
T A =2So c
VosMAX
(~V)
250
250
250
500
500
500
1000
TO-99
8-PIN
HERMETIC
DIP
8·PIN
OP20BJ·
OP20FJ
OP20BZ·
OP20FZ
OP20CJ"
OP20GJ
OP20CZ"
OP20GZ
PLASTIC
DIP
8·PIN
OPERATING
TEMPERATURE
RANGE
OP20FP
OP20HJ
OP20HZ
OP20GP
OP20HP
+IN 3
TO·99
(J·Suffixl
5 BAl
v_
4
(CASE)
MIL
INO
COM
MIL
INO
COM
COM
EPOXY B MINI·DIP
(P·Suffixl
AND
8-PIN HERMETIC DIP
(Z·Suffixl
"Also available with MIL-STD-8838 Processing. To order add /883 as a suffix to
the part number.
t All listed parts are available with 160 hour burn-in. See Ordering Information,
Section 2.
SIMPLIFIED SCHEMATIC
OUTPUT
·'N
+'N
o---+---+-----l-----l---
aJJ
PAGE 5-112
OP·20 MICROPOWER PRECISION OPERATIONAL AMPLIFIER
ABSOLUTE MAXIMUM RATINGS (Note 2)
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 18V
Power Dissipation (Note 1) .................... 500mW
Differential Input Voltage. . . . . . . . . . . . . . . . . . . . . .. ±30V
Input Voltage. . . . . . . . . . . . . . . . . . . . . . . .. Supply Voltage
Output Short Circuit Duration. . . . . . . . . . . . . . .. Indefinite
Storage Temperature Range
J and Z Packages .................. -65° C to
150° C
P Package ......................... -65° C to + 125° C
OP·20HJ,OP·20HZ ................... O·C to + 70·C
Lead Temperature (Soldering, 60 Sec.) ............ 300·C
DICE Junction Temperature ...........
NOTES:
MAXIMUM AMBIENT
TEMPERATURE
FOR RATING
+
Operating Temperature Range
OP·20B, OP·20C (J or Z package)
-55·C to + 125·C
OP·20F, Op·20G (J or Z package) ..... -25·C to +85·C
OP·20FP, Op·20GP, Op·20HP
-65° C to + 150° C
1. See table for maximum ambient temperature rating and derating factor.
2. Absolute ratings apply to both DICE and packaged parts unless otherwise
noted.
DERATE ABOVE
MAXIMUM AMBIENT
TEMPERATURE
II
TO·99 (J)
8-Pin Plastic DIP
8·Pin Hermetic DIP(Z)
!;:
D.
o
ELECTRICAL CHARACTERISTICS
at Vs
= ± 2.5V to ± 15V, TA = + 25°C,
III
II:
unless otherwise noted.
W
Op·20B/F
PARAMETER
SYMBOL CONDITIONS
Input Offset Voltage Vas
Vs
=
MIN
± 15V
Input Offset Current los
Input Bias Current
Is
Input Voltage Range IVR
Common Mode
Rejection Ratio
V+ = +5V,
V- =OV
VS= ±15V
CMRR
95
Vs=±15V
-15V"VCM
oS + 13.5V
V+ =5V. V- =OV
RL = 100kn
VS =±15V,
RL = 25kn
MAX
UNITS
300
1000
0.15
1.5
0.2
2.5
0.3
4.0
"V
nA
12
25
14
30
16
40
nA
105
90
95
85
V
dB
100
110
94
105
90
500
1000
300
800
1000
2000
800
2000
100
10
10
32
"VIV
500
Vim V
4.1
0.6
±14.1
0.7
500
4.1
1000
0.8
4.0
V
±14.0
± 14.1
AVCL= +1.0,
RL = 10kn
100
100
100
kHz
SR
VS=±15V
0.05
0.05
0.05
Vf/J.s
RL = 25kn
ISY
no load
Vs = ±15V,
no load
40
55
44
63
45
70
55
80
57
85
60
95
~
NOTES:
1. Sample tested.
PAGE 5-113
ii:
::::i
II.
:e
CC
....
CC
Z
o
~
II:
W
II.
o
90
BW
Vs= ±2.5V,
Supply Current
MIN
+ 3.5V
V+ = +5V,
V- =OV (Note 1)
Vs= ±15V,
RL =25kn
Slew Rate
TYP
500
+38/-{).2
Avo
Bandwidth
MAX
150
+13.8/-15.2
Large Signal
Voltage Gain
Closed Loop
MIN
+4.0/-{).2
Vs = ± 2.5V to ± 15V;
and V- = OV,
V+ =5V to 30V
Swing
TYP
250
+ 14.01-15.2
PSRR
Vo
MAX
55
+4.0/-{) 2
Power Supply
Rejection Ratio
Output Voltage
TYP
+14.0/-15.2
V+ = +5V,
V- =OV
OV::; VCM :5
Op·20H
Op·20C/G
OP·20 MICROPOWER PRECISION OPERATIONAL AMPLIFIER
ELECTRICAL CHARACTERISTICS atVs =
±2.5Vto±15V, -55° C TA:5+125° Cfor OP-20BJ/BZ and OP-20CJ/CZ, -25° C
~ T A :5 +85°C for OP-20FJ/FZ and OP-20GJ/GZ, and O°C:5 T A :5 +70°C for OP-20FP, OP-20GP, OP-20HP, OP-20HZ and
OP-~OHJ, unless otherwise noted.
PARAMETER
SYMBOL CONDITIONS
Average Input
Offset Voltage
Drift (Note 1)
TCVos
TCVOsn
Input Offset Voltage Vos
MIN
Unnulled
Nulled, Rp = 10kO
Vs= ±15V
Input Offset Current los
Input Bias Current
Input Voltage
Range
Ie
IVR
V+ = +5V,
V- =OV
Vs= ±15V
MAX
MIN
3.0
1.5
7.0
155
400
250
800
500
1700
~V
0.5
2.5
1.0
3.5
1.5
5.0
nA
12
27
14
33
16
45
nA
+13.7
Large Signal
Voltage Gain
Avo
Vs= ±15V,
RL =25k!l
Output Voltage
Swing
(Note 2)
Vo
V+ =5V, V- =OV,
RL=10kll
Vs= ±15V,
RL = 25kll
Supply Current
Isy
V
90
100
85
90
80
85
98
110
90
105
85
100
dB
Vs= ±2.5V to
±15V
V- =OV,
V+ =5V to 30V
Vs = ±2.5V, no
load or +5V, OV
Vs= ±15V,
no load
~V/'C
1.0
+3.7/-{).1
PSRR
UNITS
1.5
+3.9/-{).1
V+ = +5V,
V- =OV
OV"VCM,,3.3V
Vs= ±15V
-15V",VCM
"13.3V
Op·20H
TYP
MAX
0.75
+ 13.9/-15.0
Power Supply
Rejection Ratio
Sample tested
TYP
+3.9/-{).1
CMRR
I.
MIN
+13.9/-15.0
Common Mode
Rejection Ratio
(Note 3)
NOTES:
Op·20C/G
Op·20B/F
TYP
MAX
4
10
6
10
500
700
+0.8
400
10
32
10
57
250
600
+0.9
+ 4.0
±14.0
18
18
+3.9
±13.9
400
+1.0
I'VIV
V/mV
+ 3.8
V
±13.9
50
65
53
75
55
85
64
95
68
100
72
115
~
2. RL =50k for -5S'C"TA " +125'C, Vs= ±15V.
3. BJ and CJ grades tested to VCM" 150mV above negative supply voltage.
PAGE 5-114
OP·20 MICROPOWER PRECISION OPERATIONAL AMPLIFIER
DICE CHARACTERISTICS
1.
2.
3.
4.
5.
6.
7.
BALANCE
INYERTING INPUT
NON·INYERTING INPUT
Y-
BALANCE
OUTPUT
Y+
II
0
DIE SIZE 0.088 x 0.045 Inch
:z0
Refer to Section 2 for additional DICE Information.
II)
a::
ii:
:::i
IL
::E
III
ELECTRICAL CHARACTERISTICS at Vs
=
±15V, TA
=
+25°C unless otherwise noted.
OP-20N
OP-20G
c
OP-20GR
LIMIT
LIMIT
LIMIT
UNITS
Vos
300
600
1000
~VMAX
Input Offset Current
los
1.5
2.5
4.0
nAMAX
Input Bias Current
18
20
25
30
nAMAX
4.0/-0.2
4.0/-0.2
3.8/-0.2
+14.0/-15.2
+14.0/-15.2
+13.8/-15.2
100
90
94
85
90
6
10
32
1000
800
500
V/mVMIN
0,7/4.2
±14.1
0.8/4.1
± 14.1
0.9/4.0
± 14.0
VMIN
45
50
65
70
80
80
PARAMETER
SYMBOL
Input Offset Voltage
Input Voltage Range
IVR
CONDITIONS
V+ =+5V. V-= OV
Vs =±15V
Common Mode
Rejection Ratio
CMRR
Power Supply
Rejection Ratio
PSRR
Vs = ±2.5V to ±15V
V-=OV, V+=+5V
to+30V
Large Signal
VOltage Gain
Ava
RL = 25kn
Output Voltage
Swing
Va
Supply Current
No Load
Isy
V + = + 5V, V - = OV, OV" VCM" +3.5V
Vs = ± 15V, -15V" V CM" ± 13,5V
RL = l00kll, V+ = +5V, V-= OV
RL = 25kll, Vs = ± 15V
Vs = ±2.5V
Vs =±15V
95
V,MIN
dB MIN
~V/V
MAX
~AMAX
TYPICAL ELECTRICAL CHARACTERISTICS at Vs = ±15V, TA = +25°C, unless otherwise noted.
PARAMETER
Average Input
Offset Voltage Drift
Large Signal
Voltage Gain
SYMBOL
CONDITIONS
OP-20N
OP-20G
OP-20GR
TYPICAL
TYPICAL
TYPICAL
TCVos
Un nulled
1.0
1.5
2.5
TCVoSn
Nulled, Rp = 10kn
1.0
1.5
2.5
Ava
RL = 25kn
2000
2000
1000
UNITS
~V/·C
PAGE 5-115
V/mV
-'
C
Z
0
~a::
III
IL
0
OP·20 MICROPOWER PRECISION OPERATIONAL AMPLIFIER
TYPICAL PERFORMANCE CURVES
'50
'25
TRIMMED OFFSET VOLTAGE
vs TEMPERATURE
..
,
VS=±16V
f-
RS = 600
II
-25
-15
'00
/
25
\ r-..
V
l/
~80
II
25
Rs = son
....-
'0
-
RL",25kU
I'..
AVCL = 1000
r-..... r---
..
11111 nIT
i--
AVCL = 100
t--
I~~~~ =I,~I
20
75
0
±5
'15
'25
±10
-20
:!:15
0.0'
SUPPLY VOLTAGE (VOLTS)
700
...
r-----
70
..
v~."~v
500
50
II
40
J
-
200
=1
Till I I
'.0
10
100
lk
'00k
'Ok
FREClUENCY 1Hz)
--
SUPPLY CURRENT
vs SUPPLY VOLTAGE
INPUT OFFSET CURRENT
vs TEMPERATURE
~s = ~'5vl
1111 I I
AVCL
0
INPUT BIAS CURRENT
vs TEMPERATURE
'2
'00
80
TEMPERATURE (OC)
'4
f-
TA = 25°C
!l
> ..
NULLED TO ZERO OFFSET AT 25°C
WITH 10k POT
-2.
I I
~
\
~~
'20
TA" 26°C
'20
'00
CLOSED LOOP GAIN
vs FREQUENCY
INPUT OFFSET VOLTAGE
vs POWER SUPPLY VOLTAGE
30
/
TA. l250C
..... I.---' ~
~
L-- ~
I.---'
'u
~
I I I
~1
TA" -56°C
20
./
'00
-100
-50
50
TEMPERATURE (OCI
150
100
-100
-50
'0
50
TEMPERATURE 1°C)
'Nb
SMALL-SIGNAL TRANSIENT RESPONSE
UT
+OP.2O
1+.
100
150
t5
:!:10
SUPPLY VOLTAGE (VOLTS)
±15
LARGE-SIGNAL TRANSIENT RESPONSE
OUTPUT
OUT.PUT
CL
~~'OO'F
PAGES-11S
RL
25k
..I.
CL
'OOpF
OP·20 MICROPOWER PRECISION OPERATIONAL AMPLIFIER
TYPICAL PERFORMANCE CURVES
INPUT VOLTAGE NOISE
DENSITY VI FREQUENCY
MAXIMUM OUTPUT VOLTAGE
vs LOAD RESISISTANCE
17.5
1000
'vi.',UJ
TA '" 2SoC
15
VS" +6V, OV
/. ~
I
V
1k
10
'"
/'
V
INPUT CURRENT NOISE
DENSITY VI FREQUENCY
.........
"1
IIIII
LUll
10k
0.1
10
100
lk
10k
0
:z0
/I)
0.01
0.1
1
lOOk
"",
II
10
100
lk
FREQUENCY (Hz)
FREQUENCY (Hz)
RLOAD (OHMS)
10k
a::
w
ii:
:::i
IlL
::Ii!
~
....
~
TYPICAL APPLICATIONS
Z
0
TEMPERATURE SENSOR
5a::
w
IlL
,------..---------t-----------.,------o+9VOlTS
100k!l
1kn
lkU
0
lOOk!!
>-4----0 OUTPUT
DESIGN EQUATIONS
~VBE~~
.l~~E
In
(~)
'" 85.S In
(:~~)
I/.IV! K I
VOUT = 101(.lVBE)
IF
-Rl AND R2 SHOULD BE SELECTED TO KEEP lel AND IC2
-=-
LESS THAN 20IJA
PAGE 5-117
GND
~ = 3.2, THEN
TCVOUT
~
10mV! C
OP-21
PMI
HIGH-SPEED LOW POWER
PRECISION OPERATIONAL AMPLIFIER
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
Low Supply Current . . . . . . . .. .. .. . . . .. . . . . ... 170,..A
High Slew Rate. . . . . . . . . . . . . . . . . . . . . . . . . .. O.25V/,..s
Dual Supply Operation. . . . . . . . . . . . . .. ± 1.5V to ± 15V
Low Input Offset Voltage. . . . . . . . . . . . . . . . . . . . .. 4O"V
Low Input Offset Voltage Drift .............. O.5"V/·C
High Common Mode
Input Range ............ V- (+O.5V)toV+ (-1.5V)
High CMRR and PSRR ...................... 110dB
High Open Loop Gain . . . . . . . . . . . . . . . . . . .. 2000VlmV
±30V Input Overvoltage Protection
No Extemal Components Required ....... Easy to Use
Single Chip Monolithic Construction
741 Pinout and Nulling
1250 C Temperature Tested DICE
GENERAL DESCRIPTION
The OP·21 is a precision low-power operational amplifier offering the benefits of low offset voltage and high slew rate
with the advantages of low power. Supply ranges of ±1.5V
to ± 15V allow a wide range of. applications.
.
Two military temperature range models and three industrial
temperature range models are available in TO-99 CANs and
B-Pin Hermetic DIPs. Industrial temperature range models
are also available in 8-Pin Plastic DIPs. For quads see OP-421.
PIN CONNECTIONS
ORDERING INFORMATIONt
N.C .
•
PACKAGE
T.. - 25·C
vas MAX
(I'V)
TO-99
a-PIN
100
100
200
200
OP21AJ'
OP21EJ
OP21BJ'
OP21FJ
OP21GJ
500
HERMETIC PLASTIC
DIP
DIP
a-PIN
a-PIN
OP21AZ'
OP21EZ
OP21BZ'
OP21FZ
OP21GZ
OP21EP
OP21FP
OP21GP
OPERATING
TEMPERATURE
RANGE
MIL
INO
MIL
INO
INO
BALS'V'
-IN 2
:
+IN 3
6 OUT
EPOXY B MINI·DIP
(P·Sufflx)
6 BAL
4
v- (CASE)
&
8-PIN HERMETIC DIP
(Z·Sufflx)
To·gg (J·Sufflx)
• Also available with MIL-STO-8838 processing. To order add/883 as a suffix to
the part number.
t All listed parts are available with 160 hour burn-in. See Ordering Information.
Section 2.
SIMPLIFIED SCHEMATIC
Q33
v-
PAGES-118
OP·21 HIGH·SPEED LOW·POWER PRECISION OPERATIONAL AMPLIFIER
ABSOLUTE MAXIMUM RATINGS (Note 2)
DICE Junction Temperature ........... -65°C to +150°C
Lead Temperature Range (Soldering, 60 sec.) . . . . .. 300 °C
Supply Voltage ............................... ±18V
Power Dissipation (Note 1) ...................... 500mW
Differential Input Voltage. . . . . . . . . . . . . . . . . . . . . .. ±30V
Input Voltage. . . . . . . . . . . . . . . . . . . . . . . .. Supply Voltage
Output Short Circuit Duration . . . . . . . . . . . . . . .. Indefinite
Storage Temperature Range
J and Z Packages .................... -65° C to + 125° C
PPackage ........................... -65°Cto+125°C
Operating Temperature Range
OP·21A, OP·21 B . . . . . . . . . . . . . . . . .. -55°C to + 125 °C
OP·21E,OP·21F,OP·21G ............ -25°Cto +85°C
NOTES:
1. See table for maximum ambient temperature rating and derating factor.
2. Absolute maximum ratings apply to both packaged parts and dice. unless
otherwise noted.
MAXIMUM AMBIENT
TEMPERATURE
FOR RATING
DERATE ABOVE
MAXIMUM AMBIENT
TEMPERATURE
TQ.gg (J)
80·C
7.1mW/·C
8-Pin Plastic Dip (PI
36·C
5.6mW/·C
8-Pin Hermetic Dip (Z)
75·C
6.7mW/·C
II
...
:lc
ELECTRICAL CHARACTERISTICS at Vs = ±2.5V to ±15V and TA = +25° C, unless otherwise noted.
OP·21A1E
PARAMETER
SYMBOL CONDITIONS
MIN
OP·21B1F
TYP
MAX
MIN
III
OP·21G
TYP
MAX
MIN
TYP
MAX
UNITS
a:
w
ii:
::::i
Q.
Input Offset Voltage
Vos
40
100
150
200
300
500
.V
Input Offset Current
los
0.6
4
0.8
5
1.2
6
nA
~
Input Bias Current
Ie
50
100
60
120
70
150
nA
...J
Input Voltage Range
IVR
Vs= ±15V
Common Mode
Rejection Ratio
CMRR
Vs=±15V. no load
-14.5V"VCM
.. 13.5V
Vs= ±15V
-14.5
+14.0
100
-14.5
+14.0
90
110
C
-14.5
+13.8
84
105
C
V
100
dB
Z
0
~
a:
w
Q.
Power Supply
Rejection Ratio
PSRR
Vs= ±2.5V
to ±15V. no load
Large Signal
Voltage Gain
Avo
Vs= ±15V,
RL =10kll
1000
Output Voltage
Swing
Vo
Vs= ±15V.
RL =10kll
-13.7
+14.0
Slew Rate
SR
CL=100pF,
RL = 25kll
0.25
0.25
0.25
VI".
Closed Loop
Bandwidth
BW
AVCL= +1,
RL =10kll
600
600
600
kHz
Supply CUrrent
ISY
Vs= ±2.5V,
No load
Vs= ±15V,
No load
10
500
2000
1500
10
500
-13.7
+13.9
32
1000
/,VlV
V/mV
-13.6
+13.8
V
170
230
180
275
190
300
230
300
235
360
250
420
~
PAGES-119
0
OP·21 HIGH·SPEED LOW·POWER PRECISION OPERATIONAL AMPLIFIER
ELECTRICAL CHARACTERISTICS at Vs =± 2.5V to ± 15V, -55°C:STA:S+ 125°C for OP-21AandOP-21B, -25°C:STA:S
+ 85°C for Op-21E, OP-21F and OP-21G, unless otherwise noted.
PARAMETER
SYMBOL CONDITIONS
Average Input Offset
Voltage Drift
(Note 1)
TCVos
TCVOSn
Input Offset Voltage
Input Offset Current
MIN
Unnulled
Nulled
OP·21A1E
TYP
MAX
MIN
OP·21BJF
TYP
MAX
MIN
Op·21G
TYP
MAX
~V/·C
0.5
1.0
1.0
2.0
2.5
5.0
Vos
75
200
200
500
500
1000
"v
lOS
1.5
5
2.0
6
2.0
8
nA
50
110
60
130
70
165
nA
Input Bias Current
18
Input Voltage Range
IVR
Common Mode
ReJeclion Rallo
CMRR
Power Supply
Rejection Rallo
PSRR
Large Signal
Voltage Gain
",",0
VS= ±15V,
RL =2Okll
500
Output Voltage
Swing
Vo
Vs= ±15V,
RL =20kll
-13.5
+13.8
Supply Current
ISY
Vs= ±2.5V,
No load
Vs= ±15V,
No load
-14.3
+13.5
No load,
Vs =±15V,
-14.5VsVCM
s13.5V
96
-14.3
+13.5
-14.3
+13.5
105
Vs= ±2,5V
66
1500
80
250
95
dB
18
18
6
10
to ± 15V, no load
100
V
1300
250
57
1000
~VN
V/mV
-13.5
+13.6
-13.5
+13.7
V
205
275
215
330
230
360
275
360
285
430
300
500
~
NOTE:
I. Sample tested.
NOISE CHARACTERISTICS
INPUT SPOT NOISE CURRENT
vs FREQUENCY
INPUT SPOT NOISE VOLTAGE
VI FREQUENCY
1000
UNITS
r--..,.---+---,r--..,.-...,
10
I
'" "'"
0.01
0.1
'D~.I~~--~ID--'~'D=D--7.'k--='IDk
FREOUENCY 1Hz)
PAGE 5-120
"'-
10
100
FREQUENCY IH~)
,k
10k
OP·21 HIGH·SPEED LOW·POWER PRECISION OPERATIONAL AMPLIFIER
DICE CHARACTERISTICS (125° C TESTED DICE AVAILABLE)
1.
2.
3.
4.
5.
8.
BALANCE
INVERTING INPUT
NON-INVERTING INPUT
VBALANCE
OUTPUT
7. V+
DIE SIZE 0.068 X 0.045 Inch
See Section 2 for addilional Dice Informallon.
ELECTRICAL CHARACTERISTICS at VS =± 15V, T A = +25° Ctor OP-21 N, OP-21 G and OP-21 GR devices; T A =+ 125° Ctor
OP-21 NT and OP-21 GT devices, unless otherwise noted.
OP-21NT
OP-21N
OP-21GT
OP-21G
OP-21GR
LIMIT
LIMIT
LIMIT
LIMIT
LIMIT
UNITS
Vas
200
100
500
200
500
p.VMAX
Input Offset Current
los
4
4
5
6
nAMAX
Input Bias Current
18
nAMAX
Input Voltage Range
IVR
PARAMETER
SYMBOL CONDITIONS
Input Offset Volt~ge
100
100
120
120
150
-14.3
+13.5
-14.5
-14.3
-14.5
+14.0
+13.5
-14.5
+14.0
+13.8
96
100
66
90
84
dBMIN
10
6
18
10
32
p.VNMAX
VMIN
CMRR
No Load
CMVR= IVR
Power Supply
Rejection Ratio
PSRR
Vs= ±2.5V to ±15V
No Load
Large Signal
Voltage Gain
Avo
RL = 10kO
500
1000
250
500
500
VlmV MIN
Output Voltage Swing
Va
RL = 10kO
-13.5
+13.8
-13.7
+14.0
-13.5
+13.7
-13.7
+13.9
-13.6
+13.8
VMIN
Supply Current
ISY
300
300
360
360
420
p.AMAX
NOTE: For 25° Ccharacteristics of NT & GT devices, see N & G characteristics
respectively.
TYPICAL ELECTRICAL CHARACTERISTICS at Vs = ±15V, TA = +25°C, unless otherwise noted.
OP-21NT
OP-21N
OP-21GT
OP-21G
OP-21GR
TYP
TYP
TYP
TYP
TYP
UNITS
Unnulled
0.5
0.5
2.5
p.VI"C
TCVOSn
Nulled, Rp = 10kll
0.5
0.5
2.5
p.VI"C
Large Signal
Voltage Gain
Avo
RL = 10kO
2000
2000
1500
1500
1000
VlmV
Slew Rate
SR
RL = 25kll
CL = 100pF
.25
.25
.25
.25
.25
VII's
Closed Loop
BW
600
600
600
600
600
kHz
SYMBOL CONDITIONS
Average Input
Offset Voltage Drift
TCVos
Nulled Input
Offset Voltage Drift
Bandwidth
AveL = +1
RL = 10kll
PAGE 5-121
...
:lo
II)
Common Mode
Rejection Ratio
PARAMETER
•
II:
W
it
::i
Q.
~
:izi!
o
~
II:
W
Q.
o
PMI
OP-24/0P-34
ULTRA-LOW NOISE
OPERATIONAL AMPLIFIERS
®
FEATURES
•
•
•
•
•
•
Ultra Low Nolle ........... 5nVlVHz at 30Hz Maximum
High Speed .. . . . . . . • . . . . . . • . • . .• Slew Ratel to 17V/ 1'1
Low Vos ...........•......•.......... 170jLV Maximum
Low Ib and los •............•........•• 90nA Maximum
Doubla Buffer Output .••.•......•. ±11.5 Voltllnto 6000
Socket Compatible with 5534
The OP-24 is pin compatible with the 5534 and can often be
used to upgrade de,signs through direct replacement of the
5534. For high gain applications (Av>5),the decompensated
OP-34 is recommended. AC performance can be improved
substantially through use ofthe OP-34 for high-gain applications. These two amplifiers, the OP-24 and OP-34, offer
excellent AC performance for audio, active filter, and data
conversion applications, while retaining the low DC offsets
which are characteristic of PMI products.
GENERAL DESCRIPTION
The OP-24 and OP-34 op amps offer a unique combination of
low noise, wide bandwidth, and high gain without sacrifice
of input offset performance. Input bias current is under
85nA and maximum input offset voltage is only 170jLV. In
addition, a double-buffered output stage can deliver ±11.5V
into a 6000 load.
This excellent performance in a low cost, plastic minidip
package makes the OP-24 and OP-34 an ideal choice for use
in professional and consumer audio equipment; such as
phono, tape, and microphone pre-amplifiers. The guarantees
in maximum noise and minimum slew rates assure high
performance on a production basis. In many AC amplifier
applications, the low DC offsets allow direct coupling between
gain stages. The usual coupling capacitors can often be
eliminated when using the PMI OP-24/0P-34.
ORDERING INFORMATION 8. PIN CONNECTIONS
EPOXY B MINI-DIP
(PSUFFIX)
OP-24GP
OP-34GP'
• Available May 1982
SIMPLIFIED SCHEMATIC
r--...-----____1~--._.,..-____1>---"f---...-____1>----c 17)VI+)
Q40
NON-INVERTING
INPUT (+)
.1310--...-.....
--1''---1::
(6) OUTPUT
INVERTING
INPUT (-) 1 2 J o - _ -......- - - - t - - - - - - '
.....
'------4>__-_---~_-
PAGE 5-122
-_-~
_
__<> 14) VI-I
OP-24/0P-34 ULTRA-LOW NOISE OPERATIONAL AMPLIFIERS
NOTES:
ABSOLUTE MAXIMUM RATINGS
1.
Supply Voltage •••••••••••••••••••••••••••••••••••• ±22V
Internal Power Dissipation (Note 1) ••••••••••••••• 500mW
MAXIMUM AMBIENT
TEMPERATURE
FOR RATING
PACKAGE TYPE
8-Pin Epoxy Mini-Oip (PI
36°C
Input Voltage (Note 3) ••••••••••••••••••••••••••••• ±22V
Output Short Circuit Duration ••••••••••••••••••• Indefinite
Differential Input Voltage (Note 2) •••••••••••••••••• ±0.7V
Differential Input Current (Note 2) ••••••••••••••••• ±25mA
See table for maximum ambient temperature rating and derating factor.
DERATE ABOVE
MAXIMUM AMBIENT
TEMPERATURE
5.6mW/OC
Operating Temperature Range • • • • • • • • • • • •• 0° C to + 70° C
2. The OP-24/34's inputs are protected by back-to-back diodes. Current
limiting resistors are not used in order to achieve low noisB. If differential
input voltage exceeds ±O.7V, the input current should be limited to 25mA.
Lead Temperature Range (Soldering, 60 sec) •••••••• 300°C
DICE Junction Temperature ••••••••• - 65° C to + 150° C
3. For supply voltages less than ±22V.the absolute maximum input voltage is
equal to the supply voltage.
Storage Temperature Range •••••••••••• -65°C to +125° C
ELECTRICAL CHARACTERISTICS
at Vs
= ± 15V, TA = 25° C, unless otherwise noted.
SYMBOL
CONDITIONS
MIN
or~
OP-34
TYP
MAX
.
<')
OP-24
PARAMETER
•
MIN
TVP
MAX
UNITS
a.
0
Input Offset Voltage
Vos
50
170
50
170
"V
II)
Input Offset Current
los
12
90
12
90
nA
IU
±15
±85
±15
±SS
Input Bias Current
Ie
Input Noise Voltage
8n
0.1Hz to 10Hz
0.1
en
fo= 10Hz (Note 11
fo = 30Hz (Note 1)
fo = 1000Hz (Note 1)
3.7
3.3
3.2
1.9
;n
fo= 10Hz
fo = 30Hz
fo= 1000Hz
p-e
Input Noise
Voltage Density
Input Noise
Current Density
Input ResistanceDifferential Mode
R'N
Input ReslstanceCommon Mode
R'NCM
Input Voltage Range
IVR
Common Mode Rejection Ratio
CMRR
Power Supply Rejection Ratio
VCt, ,-±11V
2
GO
±11.0 ±12.3
120
50
500
500
Output Voltage
Swing
Vo
RL ;" 2kO
RL ;"8000
2
Slew Rate
SR
RL ;" 2kO (Note 2)
1.7
2.8
5.0
8.0
(Note 2)
fo = 10kHz (Note 2)
fo=1MHz
Open Loop Output Resistance
Ro
Vo=O.lo=O
Power Consumption
p.
No Load
100
120
50
500
2
20
17
45
63
40
"VN
VlmV
V
VI"s
MHz
70
170
100
±4.0
10kO
20
MHz
70
100
V
dB
±11.5 ±13.5
±10.0 ±11.5
11
0
170
±4.0
mW
mV
2. Guaranteed by Design.
ELECTRICAL CHARACTERISTICS
at Vs
=±
15 V, O· C:s; T A:S; + 70· C, unless otherwise noted.
OP-24
PARAMETER
SYMBOL
Input Offset Voltage
OP-34
TVP
MAX
TVP
MAX
Vos
55
250
55
250
"V
Input Offset Current
los
20
135
20
135
nA
Input Bias Current
Ie
±25
±150
±25
±15(,
nA
Input Voltage Range
IVR
Common Mode Rejection Rallo
CMRR
VcM =±10V
Power Supply Rejection Ratio
PSRR
Vs =±4.5Vto±18V
Large Signal Voltage Gain
Avo
RL ;" 2kO, Vo = ±10V
Output Voltage Swing
Vo
RL ;"2kO
CONDITIONS
MIN
±10.5 ±11.8
96
118
30
400
20
±11.0 ±13.3
PAGE 5-123
MIN
±10.5 ±11.8
UNITS
V
96
118
30
400
VlmV
±11.0 ±13.3
V
32
20
~
a:
a.
IU
500
±11.5 ±13.5
±10.0 ±11.5
GBW
Z
2
100
a.
e
....
e
0
±11.0 ±12.3
Avo
GBW
nVl$.
MO
Vs = ±4V to· ±18V
Gain Bandwidth Product OP-24
~
4
0.8
4
RL ;"2kO, Vo -±10V
RL ;"1kO,Vo =±10V
Gain Bandwidth Product OP-34
9.5
5.0
4.5
pAl$.
0.8
(Note 21
R~=
3.7
3.3
3.2
1.1
0.45
PSSR
Offset Adjustment Range
9.5
5.0
4.5
nA
"Vp-p
1.9
1.1
0.45
Large Signal
Voltage Gain
NOTES:
1. Sample Tested.
0.1
a:
u:
::;
dB
32
"VlV
0
OP-24/0P-34 ULTRA-LOW NOISE OPERATIONAL AMPLIFIERS
TYPICAL PERFORMANCE CURVES
A COMPARISON OF
OP AMP VOLTAGE
NOISE SPECTRUMS
VOLTAGE NOISE DENSITY vs
SUPPLY VOLTAGE
LOW FREQUENCY NOISE
100
10
9
•
~7
120
~
80
~
40
~>
-40
iii
~
az
~
w
"~
0
>
:', ,
-80
4
*
i'-
r::
,
~
......
0
~
LOW NOISE AUDIO
OP-AMP
10
~~/f CORNER
~
i5
l/f CORNER
= 2.7Hz
1/1 CORNEA
~2.7Hz
z
w
"!:;
2
III
0
INSTRUMENTATION
•
RANGE, TO DC
>
1
OP-24
'j..
~
!:;
0
>
a.1Hz TO 10Hz PEAK-lO-PEAK NOISE
1/1 CORNER
l
3
aZ
-120
741
~
TA = 25°C
Vs = ±15V
I
AUDIO RANGE
~
1
1
10
INPUT WIDEBAND VOLTAGE
NOISE VB BANDWIDTH (O.1Hz
TO FREQUENCY INDICATED)
100
1000
10
1
1000
100
FREQUENCY (Hz)
FREQUENCY (Hz)
TOTAL NOISE vs SOURCE
RESISTANCE
VOLTAGE NOISE DENSITY vs
TEMPERATURE
r=
100 E=t=t=FffFffiE===='9l
10
TA
Vs
=TA~25°C
25°C
+15V
I
~
Vs'" !:lSV
1--_V_Sj-~_±T'5_Vt+++H+f--_ ~
f---+--+-++++I++-- RS '" 2Rl
-
AT 10Hz
1
I--"
AT 1kHz
fI--
!-./
1
0.0 1
0.1
1.0
10
100
100
10k
BANDWIDTH {kHd
1k
SOURCE RESISTANCE (H)
VOLTAGE NOISE DENSITY vs
SUPPLY VOLTAGE
CURRENT NOISE DENSITY vs
FREQUENCY
Tl '"
--
10.0
25°C
~01.0
AT 1kHz
~
az
ia
o. 1
1
w
w
~
TOTAL SUPPLY VOLTAGE (V+ - V-I (VOLTS)
~
100n 500k
. .
500'
in =
'00
+
4.0
TA=700~
[eno 2 - 030nVIZ) %
1M!] X 100
Q
1/1 CORNER
- = 140Hz
1
100
k
~
~
10k
5
P'
:?'
~-I
1.0
lk
FREQUENCY (Hz)
PAGE 5-124
....- ~ ?
TA = 25 C"
3.0
11111111
10
75
SUPPLY CURRENT vs
SUPPLY VOLTAGE
2.0
-
50
25
TEMPERATURE (OC)
10kll
=
"
o
5.0
=
r::
l-
o
2SOC
I=VS =i15V
AT 10Hz
I---
1= TA
1
15
25
J5
TOTAL SUPPLY VOLTAGE (VOLTS)
45
OP-24/0P-34 ULTRA-lOW NOISE OPERATIONAL AMPLIFIERS
TYPICAL PERFORMANCE CURVES
INPUT BIAS CURRENT
va TEMPERATURE
INPUT OFFSET CURRENT
va TEMPERATURE
40
SHORT CIRCUIT CURRENT
va TIME
50
JS"'5t -
60
Vs = 1:!:15V
1 40
t---
00
i
-
l\..
~ r-
()
~
.,
20
I-
it
25
50
TEMPERATURE lOCI
10
-
'sc f+l
~
r---
IL
o
10
00
75
Vs = ±15V
I--'SC~)
30
::>
is
•
TA = +2SO
l-
25
50
o
75
TEMPERATURE (OCI
til
TIME FROM OUTPUT SHORTED TO GROUND (MINUTES)
a::
w
u::
::::i
:::I!
IL
CC
.....I
COMMON MODE INPUT RANGE
va SUPPLY VOLTAGE
CMRR va FREQUENCY
140
,.
IWI~"l) II
~
~
TA = +25°C
1\
VCM = :!:10V
12
w
"~ ,
-JA/ /
~ 140
o
~
oc -,
" _TA~
~
I
~
u
~
~
-1.
40
103
104
105
FREQUENCY (Hz)
106
107
o
-POSITI\~
NEGATIVe
~UPPLY
SUPPLY
~
40
w
±5
±10
±15
SUPPl V VOLTAGE (VOLTS)
PAGE 5-125
80
~
~
I'-....
±20
25O~_
- ~
~ 60
t
iil
I
-12
120
~ 100
......
w
TAl.,
Vs"'±4V TO ±18V
~
./
i
'\
o
PSRR VI FREQUENCY
'.0
v
CC
Z
20
10
102
103
104
~
105
FREQUENCY (HZ')
~
106
107
108
~
a::
w
IL
o
OP-2410P-34 ULTRA-LOW NOISE OPERATIONAL AMPLIFIERS
OP-24 ONLY, TYPICAL PERFORMANCE CURVES
SLEW RATE, GAIN BANDWIDTH
PRODUCT, PHASE MARGIN VI
TEMPERATURE
OPEN-LOOP GAIN VB
FREQUENCY
130
110
"\
70
I'..
"\
w
50
-
0
I'..
o
I'\.
>30
10
'\
-10
100
lk
10k lOOk
FREQUENCV (Hz)
1M
,
~
0:
~
.o.
:J:
b
~z
,::I
"
25
6
60
5
500
80
""- \
-5
1
10
FREQUENCY (MHz)
14
"i
1000
1500
2000
CAPACITIVE LOAD (pF)
2500
I-jlTlJe
10k
tOOk
1M
FREQUENCV (Hz)
SMALL-SIGNAL TRANSIENT
RESPONSE
I"
NEGATIVE
SWING
h
t--
I"'1k
8
......
SWING
~ 6
i3 4 ~
1\
o
-2
10M
0.1
TA = 2SOC
Vs '" tlSV
I III
1.0
LOAD RESISTANCE (kn)
LARGE-SIGNAL TRANSIENT
RESPONSE
+50mV
ov
-'"'mV
AVCL = +1, CL "" 15pF
AVCL" +1
Vs = ±16V
Vs'" :t15V
TA -25°C
TA =25°C
PAGE 126
200
-220
100
18
~'2 I~'0
1
\
,.
k.LLATION
(V.+l
I
~ 80
MAXIMUM OUTPUT SWING VI
RESISTIVE LOAD
1/
V
=700
-10
1~~1'2W
Vs = ±15V
VIN = 100mV-
40
PHASE \
MARGIN
0
Vs =±15V
/
,
20
> 0
'6
00
\
\
w
MAXIMUM UNDISTORTED
OUTPUT VI FREQUENCY
80
60
2
Vs .. t15V
Z
::;:
28
./
TlJ W ,
~u
15
~10
~
-80
'W
TEMPERATURE (aC)
100
20
t;
c
0
~
10M 100M
SMALL-SIGNAL OVERSHOOT
VI CAPACITIVE LOAD
40
~
::>
SL~W
I
'\
10
25
20
9~
I'..
"
~
JS"15~-
~M
~ 90
~
1
0
-
GAIN, PHASE SHIFT VI
FREQUENCY
10
OP-24/0P-34 ULTRA-LOW NOISE OPERATIONAL AMPLIFIERS
OP-34 ONLY, TYPICAL PERFORMANCE CURVES
AVCL:?! 5 MINIMUM
SLEW RATE, GAIN BANDWIDTH
PRODUCT, PHASE MARGIN
VB TEMPERATURE
0
8.
C/>M
0
VI
7.
70
6.
GBW
60
0
.
••
SL~W
+25
+50
TEMPERATURE
rei
".
v. 1= ~,~~ I'
r'\.
.0
80
•
VI
80 . .""rrrmn--r"TTT11r--'-"T"1"T1'1"T11 -80
I
•
GAIN, PHASESHIFT
FREQUENCY
20
TA =
-100
T A '" +25~C
401--HH'1V). the output waveform will look as shown in the
pulsed operation diagram.
OFFSET NULLING CIRCUIT
During the fast feedthrough-like portion of the output, the
input protection diodes effectively short the output to the
input and a current, limited only by the output short circuit
protection, will be drawn by the signal generator. With R,;::
5000, the output is capable of handling the current requirements (I L $ 20mA at 10V) and the amplifier stays in its active
mode and a smooth transition will occur.
~......---ov+
>-"::""-00 OUTPUT
OPTIMIZING LINEARITY
Best linearity can be obtained by designing for the minimum
output current required for the application. High gain and
excellent linearity can be achieved by operating the op amp
within an output current range of ±10mA.
As with all operational amplifiers, when R,> 2kO a pole will be
created with R, and the amplifier's input capacitance (8pF),
creating additional phase shift and reducing the phase margin. A small capacitor (20 to 50pF) in parallel with R, will
eliminate this problem.
PULSED OPERATION
COMMENTS ON NOISE MEASUREMENTS
The extremely low noise of the OP-24 and OP-34 implies that
its precise measurement is a difficult task. In order to realize
the 80nV peak-to-peak noise specification of the op amp in
the 0.1 Hz to·10 Hz frequency range, the following constraints
have to be observed:
(1) The device has to be warmed up for at least five minutes.
As the op amp warms up, its offset voltage changes typically
4p.V due to its chip temperature increasing 14 to 20· C from
the moment the power supplies are turned on. In the 10sec
measurement interval these temperature-induced effects
can easily exceed tens of nanovolts.
PAGE 5-128
OP-24/0P-34 ULTRA-LOW NOISE OPERATIONAL AMPLIFIERS
AUDIO APPLICATIONS
The following applications information has been abstracted
from Electronic Design magazine and updated. The authors
are G. Erdi, T. J. Schwartz, S. Bernardi of Precision Monolithics, Inc. and Walter Jung, an independent audio consultant.
FIGURE 1
C4(2)
220,uF
(+1
(+)
OUT
IN
O.47}JF
OUTPUT
:;.6k
This circuit is capable of very low distortion over its entire
range, generally below 0.01% at levels up to 7-V rms. At 3-V
output levels, it will produce less than 0.03% total harmonic
distortion at frequencies up to 20 kHz.
Capacitor C3and resistor R4 form a simple-6-dB-per-octave
rumble filter, with a corner at 22 Hz. As an option, the switchselected shunt capacitor C 4, a non polarized electrolytic,
bypasses the low-frequency rolloff. Placing the rumble filter's high-pass action after the preamp has the desirable
result of discriminating against the RIAA-amplified lowfrequency noise components and pickup-produced lowfrequency disturbances.
R5
lOOk
~~
C3
For the values shown, the gain is just under 100 (or 40 dB).
Lower gains can be accommodated by increasing R3, but
gains higher than 40 dB will show more equalization errors,
because of the 8-MHz gain-bandwidth of the OP-24.
~.1~F ~:k
A preamplifier for NAB tape playback is similar to an RIAA
phono preamp, though more gain is typically demanded,
along with equalization requiring a heavy low-frequency
boost. The circuit in Fig. 1 can be readily modified for tape
use, as shown by Fig. 2.
C2
O.D1.u F
II)
IE:
W
ii:
::::i
a.
::I!
CC
...I
CC
Z
R3
1000
o
FIGURE 2
~
+*)
G = 1kHz GAIN
=0.101 (1
•
IE:
W
= 98.677 (39.9 dB) AS SHOWN
O.47,uF
TAPE
HEAD
R,
C,
R1
313kn
Figure 1 is an example of a phono pre-amplifier circuit using
the OP-24 for AI; R1-Rz-C 1-C 2 form a very accurate RIAA
network with standard component values. The popular method
to accomplish RIAA phono equalization is to employ
frequency-dependent feedback around a high-quality gain
block. Properly chosen, an RC network can provide the three
necessary time constants of 3180, 318 and 75 pS.l
For initial equalization accuracy and stability, precision
metal-film resistors and film capacitors of polystyrene or
polypropylene are recommended, since they have low voltage
coefficients, dissipation factors, and dielectric absorption. 4
(High-K ceramic capacitors should be avoided here, though
low-K ceramics-such as NPO types, which have excellent
dissipation factors, and somewhat lower dielectric absorptioncan be considered for small values or where space is at a
premium.)
NOISE AND GAIN CONSIDERATIONS
The OP-24 brings a 3.2-nV/y'HZ voltage noise and 0.45pAly'HZ current noise to this circuit. To minimize nOise from
other sources, R3 is set to a value of 100-0, which generates a
voltage noise of 1.3 nVly'HZ. The noise increases the 3.2nVly'HZ of the amplifier by only 0.7 dB. With a 1-kO source,
the circuit nOise measures 63 dB below a 1-mV reference
level, unweighted, in a 20-kHz noise bandwidth.
Gain (G) of the circuit at 1-kHz can be calculated by the
expression:
G=0.101 (1
+ :;).
R2
5kr!
100.11
f
T1 = 3180.u5 T2 = 50"S
While the tape-equalization requirement has a flat highfrequency gain above 3 kHz (Tr 50 ps), the amplifier need
not be stabilized for unity gain. The decompensated OP-34
provides a greater bandwidth and slew rate. For many applications, the idealized time constants shown may require
trimming of Rl and R2 to optimize frequency response for
non ideal tape-head performance and other factors. 5
The network values of the configuration yield a 50-dB gain at
1 kHz, and the dc gain is greater than 70 dB. Thus, the
worst-case output offset is just over 500 mY. A single 0.47-pF
output capacitor can block this level, without affecting the
dynamic range.
The tape head can be coupled directly to the amplifier input,
since the worst-case bias current of 85 nA with a 400-mH,
100-pin. head (such as the PRB2H7K) will not be troublesome.
One potential tape-head problem is presented by amplifier
bias-current transients which can magnetize a head. The
OP-24 and OP-34 are free of bias-current transients, upon
power up or power down. However, it is always advantageous
to control the speed of power-supply rise and fall, to eliminate transients.1
PAGE 5-129
a.
Q
OP-24/0P-34 ULTRA-LOW NOISE OPERATIONAL AMPLIFIERS
In addition, the dc resistance of the head should be carefully
controlled, and preferably below 1-kO. For this configuration, the bias-current-induced offset voltage can be greater
than the 170-pV maximum offset, if the head resistance is not
sufficiently controlled.
FIGURE 4
C2
1800pF
Rl
A simple but effective fixed-gain transformerless microphone preamp (Fig. 3) amplifies differential signals from lowimpedance microphones by SO dB, and has an input impedance of 2 kO. Because of the high working gain of the
circuit, an OP-34 helps to preserve bandwidth, which will be
110 kHz. As the OP-34 is a decompensated device (minimum
stable gain of S), a dummy resistor, R p, may be necessary, if
the microphone is to be unplugged. Otherwise the 100%
feedback from the open input may cause the amplifier to
oscillate.
121n
R2
1100.0.
OUTPUT
150.11
SOURCE
*Tl=JENSEN JE-115K-E
JENSEN TRANSFORMERS
10735 Burbank Blvd.
N. Hollywood Ca. 91601
FIGURE 3
Rl
R3
Cl
1k
316k
5M'
lOW IMPEDANCE
MICROPHONE INPUT~
(Z = 50 TO 200n)
R3
Rl
R4
R2
R2
lk
R6
100£1
~~k
Rp
30k
Gain may be trimmed to other levels if desired, by adjusting
R2 or R1. Because of the low offset voltage of the OP-24, the
output offset of this circuitwili be very low, 1.7 mVor less, fora
40-dB gain. The typical output blocking capacitor can be
eliminated in such cases, but is desirable for higher gains to
eliminate switching transients.
OUTPUT
Capacitor C 2and resistor R2 form a 2-p.s time constant in this
circuit, as recommended for optimum transient response by
the transformer manufacturer. With C 2 in use, A1 must have
unity-gain stability. For situations where the 2-p.s time constant is not necessary, C 2 can be deleted, allowing the faster
OP-34 to be employed.
R4
316k
Common-mode input-noise rejection will depend upon the
match of the bridge-resistor ratios. Either close-tolerance
(0.1%) types should be used, or R4should be trimmed for best
CMRR. All resistors should be metal-film types, for best stability and low noise.
Noise performance of this circuit is limited more by the input
resistors R1 and R2 than by the op amp, as R1 and R2 each
generate a 4-nVlVRZ' noise, while the op amp generates a
3.2-nV/v'Hz noise. The rms sum of these predominant noise
sources will be about 6 nVlv'Hz, equivalent to 0.9 p.V in a
20-kHz noise bandwidth, or nearly 61 dB below a 1-mV input
signal. Measurements confirm this predicted performance.
For applications demanding appreciably lower noise, a highquality microphone-transformer-coupled preamp (Fig. 4)
incorporates the internally compensated OP-24. T1 is a
JE-11SK-E 1S00/1S-kO transformer which provides an
optimum source resistance for the OP-24 device. The circuit
has an overall gain of 40 dB, the product of the transformer's
voltage setup and the op amp's voltage gain.
Some comment on noise is appropriate to understand the
capability of this circuit. A 1S0-0 resistor and R1 and R2 gain
resistors connected to a noiseless amplifier will generate 220
nV of noise in a 20-kHz bandwidth, or 73 dB below a 1-mV
reference level. Any practical amplifier can only approach
this noise level; it can never exceed it. With the OP-24 and T1
specified, the additional noise degradation will be close to 3.6
dB (or -69.S dB referenced to 1 mV).
Reterencea
1. Lipshitz, S.P., "On RIAA Equalization Networks," JAES, Vol. 27, June 1979,
p.458-481.
2. Jung, w.G., IC Op Amp Cookbook, 2nd Ed., H.w. Samo and Company,
1980.
3. Jung, W.G., Audio IC Op Amp Applications, 2nd Ed .. H.W. Sams and
Company, 1978.
4. Jung. WG., and Marsh, A.M., "Picking Capacitors," Audio, February &
March, 1980.
5.
Otala, M .• "Feedback-Generated Phase Nonlinearity in Audio Amplifiers,"
London AES Convention, March 1980, preprint 1576.
6. Stout. D.F.• and Kaufman. M .• Handbook of Operational Amplifier Circuit
Design, New York, McGraw Hill, 1976.
PAGE 5-130
OP-27
PMI
ULTRA-LOW NOISE, PRECISION
OPERATIONAL AMPLIFIER
FEATURES
• Unprecedented Low Noise ... {. BOn V p-p,O.1Hz to 10Hz
....... 3nV/VHz at 1kHz
• Ultra Stable ................. { .............. O.2IlVloC
........... O.21lV/Month
• Fast ........................ { ...... 2.BVIIlS Slew Rate
.. BMHz Gain Bandwidth
• Low Vas. . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . .. 10llV
• Excellent CMRR .... 126dB Over Input Voltage of ±11V
• High Gain ................................ 1.B Million
• Fits 725, OP-07, OP-05, .AD510, AD517 sockets
GENERAL DESCRIPTION
The world's first triple threat Op Amp, the OP-27, offers the
ideal features of precision, low noise and high speed in one
monolithic device. This low-noise instrumentation Op Amp
combines the exceptional DC performance of the OP-07
(Vos of10IlV, TCVos of 21lV/°C) with a truly awesome noise
performance (en = 3.5nV/VHz at 10Hz) and a remarkably low
1/f noise corner frequency (2.7Hz). The high-speed performance is assured by a gain-bandwidth product of 8MHz and
a slew rate of 2.8Vllsec.
In addition, this device has a gain of 1.5M with 1kflload while
consuming 3mA. The OP-27 also features an I B of ± 1OnA and
ORDERING INFORMATIONt
PACKAGE
HERMETIC
OPERATING
TO-99
TEMPERATURE
DIP
B-PIN
RANGE
a-PIN
25
OP27AJ'
0P27AZ'
MIL
25
0P27EJ
OP27EZ
INO
60
OP27BJ'
OP27BZ'
MIL
60
OP27FJ
OP27FZ
INO
100
0P27CJ'
OP27CZ'
MIL
100
OP27GJ
OP27GZ
INO
• Also available with MIL-STO-883B processing. To order add /883a. a suffix to the
part number.
t ~~~~T~~dlarts are available with 160 hour burn-in. See Ordering Information,
TA=ZS·C
VosMAX
(/lV)
an los of 7nA. These surprisingly low currents are realized
through the use of a unique input bias current cancellation
circuit which typically holds IB and los of ±20nA and 15nA
resepectively, over the full military temperature range .
Other sources of input referred errors, such as PSRR and
CMRR, are reduced by factors in excess of 120dB. These
characteristics, coupled with long term drift of O.2IlV/month,
allow the circuit designer to achieve performance levels previously attained by only the most complex and expensive
hybrid or discrete designs.
II
1/1
II:
W
Low cost, high volume production of OP-27 is achieved by
electronic adjustment of an on-chip zener-zap offset trimming network during initial factory testing. This reliable and
stable zener-zap trimming scheme has demonstrated its
effectiveness over seven years of production history.
ii:
:::i
A.
:E
The OP-27 provides unparalleled performance for low noise,
high accuracy amplification of very low level signals in
transducer applications. Other applications include stable
integrators, precision summing amplifiers for analog computation and test equipment, ultra-precise voltage threshOld
detectors, comparators, and audio ci rcuits such as tape head
and microphone preamplifiers.
o
~
II:
The OP-27 is a direct replacement for 725, OP-06, OP-07 and
OP-05 amplifiers; 741 types may be directly replaced by
removing the 741's nulling potentiometer.
PIN CONNECTIONS
Vas
TR'M08~R~:
Vas
-IN 2
Vas
TRtM8- v+
8
7
+IN 3
6 OUT
tiN J
v- •
~
N.C.
5 N.C.
• V- (CASE)
TO-99
(J-Suffix)
B-PIN HERMETIC DIP
(Z-Sufflx)
SIMPLIFIED SCHEMATIC
r-----~~------~--------~--~--~------4r------~~~~4r-oV.
OUTPUT
NON
INVERTING
INPUT o."I'-t---if--t-+--t:::.
INVERTING
INPUT;"":..I........---'-1f-------f-------..J
L---__________---'~__4_------~________~--~~~~v-
PAGE 5-131
Vas TRIM
-IN 2
SOUT
c
c
z
....
W
A.
o
OP-27 ULTRA-LOW NOISE PRECISION OPERATIONAL AMPLlFIE,R
ABSOLUTE MAXIMUM RATINGS (Note 4)
NOTES:
1. See table for maximum ambient temperature rating and derating factor.
Supply Voltage .•. • • • • • • • • . . . . . • . . . . •• . • • • • • • • • • •• ±22V
Internal Power Dissipation (Note 1) .......•.....• 500mW
Input Voltage (Note 3) ..•.•••••..••...•.•......... ±22V
Output Short Circuit Duration .......••••....•. Indefinite
Differential Input Voltage (Note 2) •••.•............ ±0.7V
Differential Input Current (Note 2) ..••.••...•.... ±25mA
Storage Temperature Range ........•.. ~5·C to +150·C
Operating Temperature Range
OP-27A, OP-27B, OP-27C ..... -55·C to +125·C
OP-27E, OP-27F, OP-27G ...... -25·C to +85·C
Lead Temperature Range (Soldering, 60 sec) ..... 300·C
DICE Junction Temperature ........... -65·C to +150·C
Pickage Type
Mlxlmum Ambl.nl
D..... Above Mlxlmum
Tempe..lurelor Riling Ambl.nl Tempo..lure
TO-99 (J)
80°C
7.1mW/oC
8-Pln Hermelic Dip (Z)
75°C
6.7mW/oC
2. The OP-27's inputs are protected by back-to-back diodes. Current limiting
resistors are not used in order to achieve low noise. If differential input
voltage exceeds ±O.7V, the input current should be limited to 25mA.
3. For supply voltages less than ±22V. the absolute maximum input voltage is
equal to the supply voltage.
4. Absolute maximum ratings apply to both DICE and packaged parts, unless
otherwise noted.
ELECTRICAL CHARACTERISTICS at Vs = ± 15V, TA = +25· C, unless otherwise noted.
OP-27B/F
OP-27A1E
TYP
MAX
(Notol)
10
MAX
TYP
MAX
UNITS
25
20
60
30
100
pV
(Note 2)
0.2
1.0
0.3
1.5
0.4
2.0
"VlMo
50
12
75
nA
±10
±40
±12
±55
±15
±60
nA
0.08
0.18
0.08
0.18
0.09
0.25
pVp-p
3.5
3.1
5.5
3.8
8.0
3.1
4.5
3.3
5.8
fo = 1000Hz (Note 3)
3.0
5.5
4.5
3.8
3.5
fo = 30Hz (Note 3)
3.0
3.8
3.2
4.5
fo = 10Hz (Note 3, 6)
1.7
1.0
0.4
1.7
4.0
2.3
0.8
1.7
1.0
0.4
0.6
SYMBOL CONDITIONS
Input Offset Voltage
Vos
Vas/Time
Long Term VOS
Stability
Input Offset Current
MIN
MIN
35
los
Input Bias Current
O.1Hz to 10Hz
Input Noise Voltage
OP-27C/G
TYP
PARAMETER
MIN
(Note 3. 5)
fo = 10Hz (Note 3)
Input Noise
Voltage Density
Input Noise
fo = 30Hz (Note 3,6)
Current Density
fo == 1000Hz (Note 3, 6)
Input Resistance -
(Note 4)
Differential Mode
4.0
2.3
1.0
0.4
0.6
1.2
1.5
Input Resistance -
Common Mode
Rejection Ratio
Power Supply
Rejection Ratio
IVR
CMRR
PSSR
0.8
MO
AvO
RL~ 1kO, VO= ±10V
(Note4) RL =600n, VO==±1V. VS=±4V
Output Voltage
Swing
GO
±11.0
±12.3
±11.0
±12.3
±11.0
±12.3
v
114
126
106
123
100
120
dB
10
10
Vs = ±4V to ±18V
RL~ 2kO, Vo= ±10V
Large Signal
Voltage Gain
pA/v'Hz
2.5
Common Mode
Input Voltage Range
nVlVHz
1000
800
250
1800
1500
700
±12.0
±10.0
±13.8
±ll.S
1000
800
20
",V/V
700
1500
1500
250
1800
1500
700
200
500
±12.0
±10.0
±13.8
±11.5
±11.S
±10.0
±13.5
±ll.S
v
VlmV
Slew Rate
SR
RL ~ 2kO (Note 4)
1.7
2.8
1.7
2.8
1.7
2.8
tf Vlp.s
Gain Bandwidth Prod.
GBW
(Note 4)
5.0
8.0
5.0
8.0
5.0
8.0
MHz
70
o
Open Loop Output
Resistance
Power Consumption
Offset Adjustment
Range
Pd
VO~O.IO~O
70
VO~O
90
Rp~
tOkO
70
140
90
±4.0
±4.0
NOTES:
1. Input Ollsel Voliage measurements are performed by automated tesl
equipment approximately 0.5 seconds after application of power. AlE
grades guaranteed fully warmed up.
2. Long Term Input Offset Voltage Stability relers to Ihe average lrend line
of VOS vs. Time oyer extended periods after the first 30 days 01 operallon.
3.
4.
5.
6.
140
100
±4.0
170
mW
mV
Excluding the initial hour of operation, changes in Vos during the first 30
days are Iypically 2.51'V - reler to typical performance curve.
Sample tested.
Guaranteed by design.
See lest circuit and Irequency response curve for 0.1 Hz to 10Hz tesler.
See test circuit for current noise measurement.
PAGE 5-132
OP-27 ULTRA-LOW NOISE PRECISION OPERATIONAL AMPLIFIER
ELECTRICAL CHARACTERISTICS for Vs = ±15V. -55°C ~ TA~ +125°C. unless otherwise noted.
OP-27A
PARAMETER
SYMBOL CONDITIONS
Input Offset Voltage
Vos
Average Input
Tevos
Offset Drift
TCV OSN
Input Offset Current
'os
Input Bias Current
'8
Input Voltage Range
'VA
Common Mode
Rejection Ratio
Power Supply
Rejection Ratio
Output Voltage
Swing
MAX
(Note 11
30
I Note 21
0.2
VCM""±10V
PSAR
Vs"" ±4.5V to ±18V
MIN
OP-27C
TYP
MAX
MIN
TYP
MAX
60
50
200
70
300
.V
0.6
0.3
1.3
0.4
1.8
/lVre
UNITS
15
50
22
85
30
135
nA
±20
±60
±28
±95
±35
±150
nA
±10.3
±11.5
±10.3
±11.5
±10.2
±11.S
V
108
122
100
119
94
116
dB
20
16
II
....
~
0
51
IlV/V
U)
Large Signal
Voltage Gain
OP-27B
TYP
CMAR
MIN
AvO
RL =:: 2kfl. Vo
Vo
RL :::: 2kn
= ±10V
600
±11.5
1200
±13.5
500
1000
300
800
V/mV
±11.0
±13.2
±10.5
±13.0
V
II:
W
ii:
::::;
A.
::E
CC
...I
CC
z
0
ELECTRICAL CHARACTERISTICS for Vs = ± 15V. -25° C ~ T A ~ +85° C. unless otherwise noted.
OP-27E
PARAMETER
SYMBOL CONDITIONS
Input Offset Voltage
Vos
Average Input
Offset Drift
Tevos
TCV OSN
MIN
INote21
Input Offset Current
'OS
Input Bias Current
'8
Input Voltage Range
'VA
Common Mode
Rejection Ratio
CMAA
VCM~±10V
Power Supply
Rejection Ratio
PSRR
V s "" ±4.5V to ±18V'
Large Signal
Voltage Gain
AvO
RL <:: 2kJl, Va '" ±10V
Output Voltage
Swing
Vo
R L <:: 2kH
OP-27F
TYP
MAX
20
MIN
~
OP-27G
TIP
MAX
UNITS
140
55
220
.V
0.3
1.3
0.4
1.8
.Vloe
14
85
20
135
nA
±lB
±95
±25
±150
nA
TYP
MAX
50
40
0.2
0.6
10
50
±14
±60
MIN
±10.5
±11.8
±10.5
±11.B
±10.5
±11.8
V
110
124
102
121
96
118
dB
16
15
~VlV
32
750
1500
700
1300
450
1000
VlmV
±11.7
±13.6
±11.4
±13.5
±11.0
±13.3
V
NOTES:
1.
Input Offset Voltage measurements are performed by automated test
equipment approximately 0.5 seconds after application of power. AlE
Grades Guaranteed Fully Warmed up.
2. The TCVos performance is within the'specifications unnulled or when
nulled with Rp = 8kll to 20kll.
PAGE 5-133
II:
W
A.
0
OP-27 ULTRA-LOW NOISE PRECISION OPERATIONAL AMPLIFIER
DICE CHARACTERISTICS
1. NULL
2. (-) INPUT
3. (+) INPUT
4. V6. OUTPUT
7. V+
B. NULL
Reier to Section 2 lor additional DICE Inlormatlon.
DIE SIZE 0.054 X 0.096 Inch
ELECTRICAL CHARACTERISTICS at Vs = ± 15V. T A = +25°C. unless otherwise noted.
PARAMETER
SYMBOL
CONOITIONS
Input Offset Voltage
Vos
(Note 1)
Input Offset Current
los
Input Bias Current
I.
Input Voltage Range
IVR
Common Mode
Rejection Ratio
GMRR
VCM~±11V
PSRR
Vs= ±4V to ±18V
Power Supply
Rejection Ratio
Large Signal
Voltage Gain
Avo
R L "'2kn,
R L ", 1kn,
Output Voltage Swing
Vo
RL'" 2kn
R L ", 600n
Power Consumption
Pd
Vo~O
OP-27N
OP-27G
LIMIT
LIMIT
LIMIT
UNITS
35
60
100
~VMAX
Vo~±10V
Vo~
±10V
OP-27GR
35
50
75
nAMAX
±40
±55
±BO
nAMAX
±11.0
±11.0
±11.0
VMIN
114
106
100
dBMIN
10
10
20
1000
BOO
1000
BOO
700
±12.0
±10.0
±12.0
±10.0
±11.5
±10.0
VMIN
140
140
170
mWMAX
~V/v
MAX
VlmV MIN
TYPICAL ELECTRICAL CHARACTERISTICS at Vs = ±15V. T A = +25° C. unless otherwise noted.
PARAMETER
SYMBOL
CONDITIONS
Average Input Offset
Voltage Drift
TeVos or
TeV osn
Nulled or Unnulled
Rp~ Bkn to 20kn
Average Input Offset
Input NOise
Voltage Density
en
Input Noise
Current Density
in
fo~
fo~
fo~
fo~
fo~
fo~
OP-27GR
TYPICAL
TYPICAL
UNITS
0.3
0.4
~V/"G
BO
130
1BO
pAl"G
100
160
200
pA/"G
10Hz
30Hz
1000Hz
3.5
3.1
3.0
3.5
3.1
3.0
3.B
3.3
3.2
nV/VHZ
10Hz
30Hz
1000Hz
1.7
1.0
0.4
1.7
1.0
0.4
1.7
1.0
0.4
pA/VHZ
O.OB
O.OB
0.09
~Vp-p
2.8
2.8
2.8
VI~s
B.O
B.O
B.O
MHz
TGlos
TGI.
OP-27G
TYPICAL
0.2
Current Drift
Average Input Bias
Current Drift
OP-27N
Input Noise Voltage
e np _p
0.1Hz to 10Hz
Slew Rate
SR
RL;? 2k!1
Gain Bandwidth Product
GBW
NOTE:
1. Input Offset Voltage measurements are performed by automated test
equipment approximately 0.5 seconds after application of power.
PAGE 5-134
OP-27 ULTRA-LOW NOISE PRECISION OPERATIONAL AMPLIFIER
TYPICAL PERFORMANCE CURVES
,00 ,-,rnmrnr-,-,-rnmr-'-TTmn,-rrTT11rm
'00
'0
9
8
7
l~
:;;
~70~~~~~~~-+++Hfflt-~tw~
~ 4
"g60 ~~~~~~'IIH--+++Hfflt-t+\tt~
"w 3
'"~
=
74'
TA = 25 u C
,
Vs = ±15V
......
,
-
1/1 CORNER
r-....
AUDIO
~ ~k..0~ 1~IMP
111 CORNER
2.7Hz Ii'
II IIIII
'0
'00
10
'000
III
til
AUDIO RANGE
TO 20kHz
100
'000
FREaUENCY (Hz)
FREQUENCY (Hz)
FREQUENCY (Hz)
IIIIII
INSTRUMENTATION
RANGE, TO DC
,
,,
1/1 CORNER
-- -
~ ~OP.27
2
II
LOW NOISE
0
l/fCOANER
= 2.7Hz
o
1-1"
25 C
, i'
0
>
TEST TIME OF tOsee MUST BE USED TO
LIMIT LOW FREQUENCY «a.1Hz) GAIN.
TA
6
,,5
50
A COMPARISON OF
OP AMP VOLTAGE
NOISE SPECTRUMS
OP-27 VOLTAGE NOISE vs
FREQUENCY
0.1 Hz TO 10Hz P-P NOISE TESTER
FREQUENCY RESPONSE
a:
w
ii:
:::;
Q.
::e0(
....I
0(
Z
INPUT WIDEBAND VOLTAGE
NOISE vs BANDWIDTH (0.1Hz
TO FREQUENCY INDICATED)
TOTAL NOISE vs SOURCE
RESISTANCE
o
~
VOLTAGE NOISE vs
TEMPERATURE
a:
w
Q.
'00 F=i=Ff=f1=rffF======t\
~TA=25C.
o
=~
r-t--_v_s j-=_±-t'5_Vr+t+ttt-_ ~
~
~-I-+-I-+t+H+-- RS = 2Rl
OS
w
~'0!!l_
~
f- AT
10H;!!
AT 1kHz
0.0' L-...LLLlllJlL-l-L1l1lill_Ll...L1.ll.!JJ
0.1
1.0
10
'00
BANDWIDTH (kHz}
'00
VOLTAGE NOISE vs
SUPPLY VOLTAGE
1k
SOURCE RESISTANCE (HI
'Ok
-50
r
OS
w
~3
-
~
100
125
10k"
l=aEI=(~,~
1
4 .0
AT 10Hz
I--
25
50
75
TEMPERATURE ('C)
5.0,-,--,-----,----,----,
'O.OF===mfF==-===""I
TA=2S'C
0
SUPPLY CURRENT vs
SUPPLY VOLTAGE
CURRENT NOISE vs
FREOUENCY
T! = 25°C
-25
~
AT 1kHz
~ 3.0
=>
"~
'"~
t
~
02
>
2.0
~""-7'1----+---t----;
1lfCORNER
-+-++ttH+--++++++ttl
0.' ,:---,-,-11..ill
IIII~
IIII --L.LWJJ,----'-J..J.J.J..J..W
--= '4OH,
'0
20
30
TOTAL SUPPLY VOLTAGE (V+ - V-I (VOLTS)
40
10
100
lk
FREQUENCY (Hz)
PAGES-13S
10k
TA = -55"C
'.0':-5----:"5:---:':25:---,3::5---'45
TOTAL SUPPLY VOLTAGE (VOLTS)
OP-27 ULTRA-LOW NOISE PRECISION OPERATIONAL AMPLIFIER
TYPICAL PERFORMANCE CURVES
LONG TERM OFFSET
VOLTAGE DRIFT OF
REPRESENTATIVE UNITS
OFFSET VOLTAGE DRIFT OF
REPRESENTATIVE UNITS
vs TEMPERATURE
0
0
~
I""-
20
I:::::::'
..,,-
..,,- . . . . r<
OP-27C
1/
./
V
V
OP-27B
op-r
V
~
A
OP-278
OP·27A
f-" '<::
-40
t'-..
OP·27B
........
I
""
T~VDS,
50 -25
0
25
50
75
~r-...
,,-'" '"
o
>
100
I
~
I
I
ei
4
5
~ 25
o
>
~
TA
~ 20
~
lop.,,"
-6
2S C
~
~ 15 f- -
a
TIME (MONTHS)
TIME AFTER POWER ON (MINUTES)
INPUT BIAS CURRENT
vs TEMPERATURE
INPUT OFFSET CURRENT
vs TEMPERATURE
w
ei
10
Z
~
u
5
~
~
~
-
["-./
-2
oP.J B/F
I~ l..---
h.
A.
a
so
I I I I
I I I I
.1
V .--..-
/
./""
~
+2J
DP-2l C/G
6
ei
0
Vs = .:!:lSV
~ -6
o
OFFSET VOLTAGE CHANGE
DUETO THERMAL SHOCK
.3 30
T1
I---
L-.
-4
TEMPERATURE (OC)
;;
'--
::-
ei
I
l""-
TRIMMING WITJ""'"
10k POT DOES
NOT CHANGE
-75
I
OP·2lA
I-"""
c--r---
-20
2
0
w
~ -2
f.-""
V
WARM-UP OFFSET
VOLTAGE DRIFT
1
'"
200
1\
10
FREQUENCY (MHd
220
100
OP-27 ULTRA-LOW NOISE PRECISION OPERATIONAL AMPLIFIER
TYPICAL PERFORMANCE CURVES
OPEN LOOP VOLTAGE GAIN
vs SUPPLY VOLTAGE
28
2.5
I--TJ25C
2.0
~
z
24
Y
V
RL=lkH
1.5
§ 1.0
a;
is
0.5
20
V'
NEGATIVE
SWING
b
if
\
30
40
1k
50
-
.....
o
10
•
;;..---
SWING
-
12
0.0
o
- POSilTlJE
I
16
~ /"
'/
~
"
16
Vs = ±15V
20
/' / -
18
I~~I~ l.ll
RL" 2kH
:;
MAXIMUM OUTPUT SWING vs
RESISTIVE LOAD
MAXIMUM UN DISTORTED
OUTPUTvsFREQUENCY
lOOk
10k
1M
TA = 25°C
10M
II:
IU
I III
1.0
0.1
FREQUENCY (Hz)
TOTAL SUPPLY VOLTAGE (VOLTS)
II)
Vs = ±15V
-2
10
LOAD RESISTANCE (km
u::
::;
A.
::E
oC
....
~
o
SMALL SIGNAL OVERSHOOT
vs CAPACITIVE LOAD
LARGE SIGNAL TRANSIENT
RESPONSE
SMALL SIGNAL TRANSIENT
RESPONSE
IU
A.
o
100
80
60
I/~
40
/
20
o
./
'5V
'5V
OV
ov
--5V
-5V
~LLATION
Vs
= ±15V
VIN = lOOmV-
V
o
AVCL ,. +1, CL = 15pF
=+1
(V
500
1000
1500
I
2000
AVCL '" +1
T A " +25°C
Vs = ±15V
TA = 25°C
Vs = :t15V
2500
CAPACITIVE LOAD (I)F)
SHORT CIRCUIT CURRENT
vs TIME
0
TA ~25QC
o~ r--....'scj-I
~
COMMON MODE INPUT RANGE
vs SUPPLY VOLTAGE
CMRR vs FREQUENCY
140
50
30
fiII:
i6r-----~-----r------r-~~,
1111U1~
120
~
Vs = ±15V
VCM = ±lOV
Vs = :t15V
\
o
w
a
o
~
z
10 2
,
10
-4~-----~~~-+------r-----~
~ -Br-----~--~~~r
\.
0
00
4r-----~~~-+------r-----~
z
100
TIME FROM OUTPUT SHORTED TO GROUND, (MINUTES)
8
~
7i
ISC(+I
10
i5
?
I--..
0
121-----+--
~
-12r-----+------+--~~k.----~
-16 ':---C±5':---C-!::---~--'-'-~
1()4
105
FREQUENCY (Hzl
PAGE 5-137
106
SUPPL v VOLT AGi! (VOL TSI
OP-27 ULTRA-LOW MOISE OPERATIONAL AMPLIFIER
TYPICAL PERFORMANCE CURVES
O.1Hz TO 10Hz NOISE TEST CIRCUIT
LOW FREQUENCY NOISE
120
r
80
40
-40
OPE
Xl
-80
AIN"" 1MH
-120
110k
0.1 Hz TO 10Hz PEAK-TO-PEAK NOISE
NOTE: ALL CAPACITOR VALUES ARE FOR
NON POLARIZED CAPACITORS ONLY,
OPEN LOOP VOLTAGE GAIN vs
LOAD RESISTANCE
2.'
2.
21-
;;
J-
~2.0
~1. 8
~
~
1. 6
PSRR vs FREQUENCY
160
~AI"12~1~1'
I I
~ 140
Vs = ±15V
TA '" 2S"C'-
g
!;i 1201-0:
II
~ 100
t
"~ 1.•
°~ 1.2
°9 1.0
~ 80
0:
~
t--POSITI~
NEGATIVE
~UPPLY
SUPPLY
~ 60
Z
~
o
ffi
~ O. 8
~
9·6
~
40
20
~
D.•
0.1
1.0
10
100
10
LOAD RESISTANCE (kU)
102
103
1()4
105
~
106
101
108
FREQUENCY (Hz)
APPLICATION INFORMATION
OP-27 Series units may be inserted directly into 725, OP-06,
OP-07 and OP-05 sockets with or without removal of external
compensation or nulling components. Additionally, OP-27
may be fitted to unnulled 741-type sockets; however, if conventlonal.741 nulling circuitry is in use, it should be modified
or removed to enable proper OP-27 operation. OP-27 offset
voltage may be nulled to zero (or other desired setting)
through use of a potentiometer (see offset nulling circuit).
The OP-27 provides stable operation with load capacitances
up to 2000pF and ±10V swings; larger capacitances should
be decoupled with a son decoupling resistor.
The designer is cautioned that stray thermoelectric voltages
generated by dissimilar metals at the contacts to the input
terminals can prevent realization of the drift performance
indicated. Best operation will be obtained when both input
contacts are maintained at the same temperature, preferably
close to the temperature of the device's package.
OFFSET VOLTAGE ADJUSTMENT
The input offset voltage of the o P-27 , and its drift with
temperature, are permanently trimmed at wafer testing to a
very low level. However, if further adjustment of Ves is necessary, nulling with a 10kn potentiometer will not degrade
TCVes (see offset nulling circuit). Other potentiometer
values from 1kn to 1Mn can be used with a slight degradation
(0.1 to 0.2p.Vlo C) of TCVes. Trimming to a value other than
zero creates a drift of (Vesl300)p.Vo C, e.g. if Ves is adjusted
to 100p.V, the change in TCVes will be 0.33p.VloC. The offset
voltage adjustment range with a 10kn potentiometer is
±4mV.lf smaller adjustment range is required, the sensitivity
and/or resolution of the nulling can be increased by using a
smaller pot in conjunction with fixed resistors. For example,
4.7k
lk POT
4.71<
this network will have a ±280p.V adjustment range.
PAGE 5-138
OP-27 ULTRA-LOW NOISE PRECISION OPERATIONAL AMPLIFIER
OPTIMIZING LINEARITY
Best linearity can be obtained by designing for the minimum
output current required for the application. High gain and
excellent linearity can be achieved by operating the op amp
within an output current range of ±10mA.
UNITY GAIN BUFFER APPLICATIONS
When Rt S 100.0 and the input is driven with a fast, large
signal pulse (> W), the output waveform will look as shown
in the pulsed operation diagram.
A noise-voltage density test is recommended when measuring
noise on a large number of units. A 10 Hz noise-voltage density
measurement will correlate well with a 0.1 Hz-to-10 Hz peak-topeak noise reading since both results are determined by the
white noise and the location of the 1/f corner frequency.
TYPICAL APPLICATIONS
II
BURN-IN CIRCUIT
During the fast feedthrough-like portion of the output, the
input protection diodes effectively short the output to the
input and a current, limited only by the output short circuit
protection, will be drawn by the signal generator. With Rt 2:
500.0, the output is capable of handling the current requirements (ILS 20mAat 10V) and the amplifier stays In its active
mode and a smooth transition will occur.
As with all operational amplifiers when R, > 2kn, a pole will
be created with Rt and the amplifier's input capacitance
(8pF), creating additional phase shift and reducing the phase
margin. A small capacitor (20 to 50pf) in parallel with Rtwill
eliminate this problem.
OFFSET NULLING CIRCUIT
COMMENTS ON NOISE MEASUREMENTS
The extremely low noise of the OP-27 implies that its precise
measurement is a difficult task. In order to realize the 80nV
peak-to-peak noise specification of the op amp in the 0.1 Hz
to 10 Hz frequency range, the following constraints have to
be observed:
(1) The device has to be warmed up for at least five minutes.
As shown in the warm-up drift curve, as the op amp warms
up, its offset voltage changes typically 4/JV due to its chip
temperature increasing 14 to 20°C from the moment the
power supplies are turned on. In the 10 sec measurement
interval these temperature-induced effects can easily
exceed tens of nanovolts.
5-0......---<> v+
>-.:!..---OOUTPUT
PULSED OPERATION
(2) For similar reasons, the device has to be well shielded
from air currents to eliminate the possibility of thermoelectric effects in excess of a few nanovolts invalidating
the measurements.
(3) Sudden motion in the vicinity of the device can also "feedthrough" to increase the observed noise.
(4) The test time to measure 0.1 Hz to 10 Hz noise should not
exceed 10 sec. As shown in the noise tester frequency
response curve the 0.1 Hz corner is defined by only one
zero. The test time of 10 sec acts as an additional zero to
eliminate noise contributions from the frequency band
belOW 0.1 Hz.
PAGE 5-139
PMI
OP-37
ULTRA-LOW NOISE PRECISION
HIGH-SPEED OPERATIONAL AMPLIFIER [AVCL > 5)
®
FEATURES
•
.. SOnY pop 0.1Hz to 10Hz
Unprecedented Low Noise ... J
3 VI 'H- t 1kH
1....... nvnza
z
1········· .. ·..
• Ultra Stbl
a e................. .............
02·0.2p.V/oC
p. VIM on th
• F t
J •.••••• 17V/p.s Slew Rate
as ....................... '1 .. 63MHz Gain Bandwidth
•
•
•
•
Low Vos ....................................... 10p.V
Excellent CMRR .... 126dB Over Input Voltage of ±11V
High Gain ................................ 1.S Million
Replaces 725, OP-05, OP-06, OP-07, AD510, AD517,
SE5534 In gains> 5
GENERAL DESCRIPTION
A matchless combination of precision D.C. performance,low
noise and wide bandwidth is featured in the OP-37 ~ an
Operational Amplifier designed to maximize speed in applications requiring gains greater than five.
This low-noise instrumentation Op Amp combines the exceptional DC performance of the OP-07 (Vos of 10p.V,
TCVos of O.2p.V/OC) with a truly awesome noise perfor-
ORDERING INFORMATIONt
TA=25°.C
VOSMAX
(p.V)
25
25
60
60
100
10Q
PACKAGE
HERMETIC
TO-99
DIP
B-PIN
B-PIN
OP37AJ'
OP37AZO
OP37EJ
OP37EZ
OP37BJ'
OP37BZ'
OP37FJ
OP37FZ
OP37CJ'
OP37CZ'
OP31GJ
OP37GZ
OPERATING
TEMPERATURE
RANGE
mance (en = 3.5nV/y'Hz at 10Hz) and a remarkably low 1/f
noise corner frequency (2.7Hz). The high speed performance is assured by a gain-bandwidth product of 63MHz,
and a slew rate of 17V1p.sec .
In addition, this device has a gain of 1.5 million with a 1kO
load while consuming 3mA. The OP-37 also features an 18 of
± 1OnA and an los of7nA. These surprisingly low currents are
realized through the use of a unique input bias current cancellation circuit which typically holds 18 and los of ±20nA
and 15nA, respectively, over the full military temperature
range.
Other sources of input referred errors, such as PSRR and
CMRR, are reduced by factors in excess of 120dB. These
characteristics, coupled with long term drift of O.2p.Vlmonth
allow the circuit deSigner to achieve performance levels previously attained .by only the most complex and expensive
hybrid or discrete designs.
The OP-3i brings low nOise instrumentation type performance to such diverse applications as microphone, NABtape
head, and RIAA phone preamplifiers, high speed signal conditioning for data acquisition systems, wide bandwidth instrumentation and high !lpeed analog controllers. The OP-37
also can be used as a comparator to discriminate extremely
low voltages.
PIN CONNECTIONS
Mil
INO
Mil
INO
Mil
INO
Vas TRIM08
Vas :R~:
-IN2
• Also available with MIL-ST0-8838 proceSSing. To order add/883 as a suffix to
the part number.
t All listed parts are available with 160 hour burn-in. See Ordering Information,
Section 2.
+IN 3
60Ul
5 N.C.
4 V-ICASEI
TO-99 (J-SUFFIX)
S-PIN HERMETIC DIP
(Z-SUFFIX)
SIMPLIFIED SCHEMATIC
OUTPUT
NON
INVERTING
INPUT
to.:+)-f--+-~+--l~
INVERTING
+ ___-----'
INPUTo.:t-1---4.~~-+--+-_ _ _
~------~--+----~----~~~~~~v-
PAGE 5-140
OP-37 ULTRA-LOW NOISE PRECISION HIGH-SPEED OPERATIONAL AMPLIFIER
NOTES:
1. See table for maximum ambient temperature rating and derating factor.
ABSOLUTE MAXIMUM RATINGS (Note 4)
Supply Voltage. . . . . • . . . . . . . . . • . . . . . . . . • . • • . . • . . .• ±22V
Internal Power Dissipation (Note 1) ..••.......... 500mW
Input Voltage (Note 3) ............................ ±22V
Output Short Circuit Duration. " ....••...... ,. Indefinite
Differential Input Voltage (Note 2) ......•.......... ±0.7V
Differential Input Current (Note 2) ............... ±25mA
Storage Temperature Range •••..•..... --65·C to +150·C
Operating Temperature Range
OP-37A, OP-37B, OP-37C .•.•. -55·Cto +125·C
OP-37E, OP-37F, OP-37G ..•... -25· C to +85· C
Lead Temperature Range (Soldering, 60 sec) ..•.. 300· C
DICE Junction Temperature •••........ -65· C to + 150· C
Maximum Ambient
Derate Above Maximum
Temparature lor RaUng Ambient Temparature
PaclcageTypa
TO-99 (J)
80·C
7.1mW/·C
8-Pin Hermetic DIP (Zl
75·C
6.7mW/·C
2. The OP-37's inputs are protected by back-ta-back diodes. Current limiting
resistors are not used in order to achieve low noise. If differential input
voltage exceeds ±O.7V, the input current should be limited to 2SmA.
3. For supply voltages less than ±22V. the absolute maximum input voltage is
equal to the supply voltage.
4. Absolute maximum ratings apply to both DICE and packaged parts, unless
otherwise noted.
II
,..
"?
Go
o
ELECTRICAL CHARACTERISTICS at Vs
PARAMETER
SYMBOL CONDITIONS
Vas
Long Term Vas
Vas/Time
Stability
Input Offset Current
_ln~p_u_tB_i_.s_C_u_"_.n_t
a:
w
OP-37B/F
OP-37A1E
Input Offset Voltage
III
= ± 15V, TA = + 25·C, unless otherwise noted.
TYP
MAX
TYP
MAX
TYP
MAX
(Note 1)
10
25
20
60
30
100
(Note 2)
0.2
1.0
0.3
1.5
0.4
2.0
pV/Mo
35
9
50
12
75
nA
MIN
lOS
MIN
OP-37C/G
MIN
UNITS
-C
...I
____I~B____________________________~±l~O____~±4O
________________±_1_2____±_5_5______________±~1~5____±~60
__________n~A~
Input Noise Voltage
0.06
0.18
0.08
0.18
0.09
0.25
3.5
3.1
3.0
5.5
4.5
3.8
3.5
3.1
3.0
5.5
4.5
3.8
3.8
3.3
3.2
8.0
fa = ~OHz (Note 3, 6)
1.7
=30Hz (Note 3, 6)
1.0
'a = 1000Hz (Note 3, 6)
0.4
4.0
2.3
0.6
1.7
1.0
0.4
4.0
2.3
0.6
1.7
1.0
0.4
pVp-p
(Note 3, 5)
fo= 10Hz (Note 3)
fa == 30Hz (Note 3)
Voltage Density
fa = 1000Hz (Note 3)
Input Noise
Current Density
in
Input Resistance -
fa
1.5
(Note 4)
Differential Mode
1.2
Input Resistance -
Common Mode
Rejection Ratio
Power Supply
Rejection Ratio
IVA
CMRR
PSSR
Large Signal
Vs
AVO
RL2:1kO,VO=±lDV
(Note 4) Rl = 6000, Vo = ±lV, Vs = ±4V
Output
Voltage Swing
Range
GO
±12.3
±11.0
±12.3
±1'.0
±12.3
v
114
126
106
123
100
120
dB
1000
800
250
1800
1500
700
1000
800
250
1800
1500
700
700
1500
1500
500
V/mV
±12.0
±10.0
±13.8
±11.5
±12.0
±10.0
±13.8
±11.5
±13.5
±11.5
v
to
10
20
400
200
±1'.5
±10.0
pVN
17
11
17
11
17
VIpS
45
63
40
45
fo=1MHz
63
40
63
40
MHz
RO
VO=O,IO=O
70
70
n
Pd
Vo =0
Open Loop Output
Offset Adjustment
Mn
0.8
11
SR
GBW
Power Consumption
pAl$.
0.6
45
Slew Rate
Gain Bandwidth Prod.
Resistance
nVl-!HZ
±1'.0
=±4V to ±lBV
RL2: 2kO. Vo = ±10V
Voltage Gain
5.6
4.5
2.5
Common Mode
Input Voltage Range
Rl2: 2kO (Note 4)
10
=10kHz
Rp= 10kn
(Note 4)
-C
Z
o
~
a:
w
Go
O.1Hz to 10Hz
Input Noise
ii:
::::i
Go
:::E
eo
70
140
90
±4.0
±4.0
NOTES:
1. Input Offset Voltage measuremenls are parlormed by automated tesl
equipment approximately 0.5 seconds after application of power. AlE
grades guaranteed lully warmed up.
2. Long Term Input Offset Voltage Stability reters 10 the average trend line
of VOS vs. Time over e.lended periods after the first 30 days 01 operation.
3.
4.
5.
6.
140
100
±4.0
170
mW
mV
Excluding the initial hour 01 operation, changes in Ves during the first 30
days are typically 2.5pV - reler to typical perlormance curve.
Sample tested.
Guaranteed by design. ,
See test circuit and frequency response curve for 0.1Hz to 10Hz tester.
See test circuit for current noise measurement.
PAGE 5-141
o
OP-37 ULTRA-LOW NOISE PRECISION HIGH-SPEED OPERATIONAL AMPLIFIER
ELECTRICAL CHARACTERISTICS for V s = ±15V, -55· C:s T A:S +125· C, unless otherwise noted.
OP-378
OP-37A
PARAMETER
SYMBOL CONDITIONS
TYP
MAX
Input Offset Voltage
Vos
(Nota ,)
30
Average Inpot
TCVoS
OffletDrlft
TCVOSN
(Note 2)
Input Offset Current
loS
Input Bias Current
Ie
Input Voltage Range
IVR
Common Mode
Rejection Ratio
CMRR
VCM= ±10V
Power Supply
Rejection Ratio
PSRR
Vs = ±4.5V to ±18V
Large Signal
Voltage Gain
AvO
RL~2kn,
Vo
RL~2kn
Output
Voltage Swing
MIN
±'0.3
MIN
MAX
TYP
MAX
UNITS
60
50
200
70
300
/IoV
0.2
0.6
0.3
'.3
0.4
'.6
p.VfOC
'5
50
22
65
30
'35
nA
±20
±60
±28
±65
±35
±,50
nA
±,0.3
±".5
'08
'22
'00
Vos
Average Input
Off.etDrlft
TCVos
TCVOSN
Input Offset Current
lOS
Ie
Input Voltage Range
IVR
Common Mode
Rejection Ratio
CMRR
VCM =±10V
Power Supply
Rejection Ratio
PSRR
Vs = ±4.5V to ±18V
Large Signal
Voltage Gain
AvO
RL<:! 2kn, Vo= ±10V
Output
Voltage Swing
Vo
RL~2kn
,.
V
"6
dB
5'
.VN
'200
500
'000
300
800
VlmV
±".5
±,3.5
±".O
±'3.2
±,0.5
±,3.0
V
Vs
MIN
(Note 2)
Input Bias Current
"9
94
±".5
20
=±
15V, -25·C:S TA:S + 85·C,
unless otherwise noted.
OP-37F
OP-37E
Input Offset Voltage
±'0.2
600
ELECTRICAL CHARACTERISTICS for
SYMBOL CONDITIONS
MIN
±".5
'6
VO=±10V
PARAMETER
OP-37C
TYP
MAX
TYP
MAX
50
40
140
55
220
"V
0.6
0.3
'.3
0.4
'.8
p.VfOC
MAX
20
0.2
MfN
OP-37G
TYP
TYP
MIN
UNITS
10
50
'4
65
20
135
nA
±14
±eo
±,8
±95
±25
±150
nA
±,0.5
±11.8
±10.5
±1'.8
±10.5
±11.8
V
1'0
124
102
'21
96
lIB
dB
32
16
15
.VN
750
1500
700
'300
450
'000
VlmV
±'1.7
±13.6
±'1.4
±'3.5
±I,.O
±,3.3
V
NOTES:
Input Offset Voltage measurements are performed by automated test
equipment approximately 0.5 seconds after application of power. AlE
grades guaranteed fully warmed up.
2. The TeVos performance is within the specifications unnulled or when
nulled wllh Rp = 8kO to 2OkO.
PAGE 5-142
OP-37 ULTRA-LOW NOISE PRECISION HIGH-SPEED OPERATIONAL AMPLIFIER
DICE CHARACTERISTICS
1. NULL
2. (-) INPUT
3. (+)INPUT
4. VS. OUTPUT
7. V+
S. NULL
II
:z"'0"
For additional DICE Information
see Section 2.
II)
a:
IU
DIE SIZE 0.054 X 0.098 Inch
ii:
::::i
IL
::I
...cc
ELECTRICAL CHARACTERISTICS at Vs = ± 15V, TA = +25 0 C, unless otherwise noted.
OP-37N
PARAMETER
SYMBOL
CONDITIONS
(Note 1)
Input Offset Voltage
Vos
Input Offset Current
los
Input Bias Current
I.
Input Voltage Range
IVR
Common Mode
Rejection Ratio
CMRR
VcM =±11V
Power Supply
Rejection Ratio
PSRR
Vs =±4V to ±1BV
Large Signal
Voltage Gain
Avo
RL ",2kO Vo =±10V
RL ", 1kO Vo =±10V
Output Voltage Swing
Vo
RL ",2kO
RL ",6000
Power Consumption
Pd
Vo=O
LIMIT
OP-37G
OP-37GR
LIMIT
LIMIT
Z
UNITS
35
60
100
p.VMAX
35
50
75
nAMAX
±40
±55
±BO
nAMAX
±11.0
±1'.0
±11.0
VMIN
114
106
100
dB MIN
10
10
20
p.VNMAX
1000
1000
700
800
800
±12.0
±10.0
±12.0
±10.0
±11.5
±10.0
VMIN
140
140
170
mWMAX
VlmVMIN
TYPICAL ELECTRICAL CHARACTERISTICS at Vs = ±15V, TA = +25°C, unless otherwise noted.
PARAMETER
SYMBOL
CONDITIONS
Average Input
Offset Voltage Drift
TCVosor
TCVOSN
Nulled or Un nulled
Rp = BkO to 2OkO
Average Input
Offset Current Drift
TCIOS
Average Input Bias
Current DrIft
TCI.
OP-37N
OP-37G
TYP
TYP
OP-37GR
TYP
UNITS
0.2
0.3
0.4
p.VI·C
BO
130
160
pAl'C
100
160
200
pAl'C
3.B
3.3
3.2
nVl,/Hz
Input Noise Voltage Density
en
10= 10Hz
10= 30Hz
10= 1000Hz
3.5
3.1
3.0
3.5
3.1
3.0
Input Noise Current Density
in
10= 10Hz
10= 30Hz
10= 1000Hz
1.7
1.0
0.4
1.7
1.0
0.4
1.7
1.0
0.4
pAl,/Hz
O.OB
0.08
0.09
p.Vp-p
17
17
17
VII's
63
63
63
MHz
0.1 Hz to 10Hz
Input Noise Voltage
Slew Rate
SR
Gain Bandwidth Product
GBW
10= 10kHz
NOTE:
1. Input Offset Voltage measurements are perlormed by automated test
equipment approximately 0.5 seconds after application of power.
PAGE 5-143
0
~a:
IU
IL
0
OP-37 ULTRA-LOW NOISE PRECISION HIGH-SPEED OPERATIONAL AMPLIFIER
TYPICAL PERFORMANCE CURVES
0.1 Hz TO 10Hzp-p NOISE TESTER
FREQUENCY RESPONSE
'00
A COMPARISON OF
OP AMP VOLTAGE
NOISE SPECTRUMS
OP·37 V.OLTAGE NOISE
VI FREQUENCY
'00
-
90
r-iI'
74'
[\\
80
,
""
70
1ft~QRNER
LOW NOISE
llfCORNER
80
I.
2.7Hz
~
50
TEST TIME OF 10tec MUST BE USED TO
o
30
0.1
1.0
10
'L,--~~~,O~~~~'oo~~~~,~ooO
'00
'O.~
'00
VfCORNER
m.""-37
111111
INSTRUMENTATION
RANGE. TO DC
lilll
AUDIO RANGE
TO 20kHz
10
1000
100
FREQUENCY (Hz)
TOTAL NOISE VI
SOURCE RESISTANCE
VOLTAGE NOISE vs
TEMPERATURE
F=!=FI'=t=f'fFIF====='R
=
=TA" 25°C
TA = 2SOC
I--_VS-j-"_±'r-'V-r-t+tl*=-
Vs '" ±15V
R1
~
1---J-H-H++ILf-- RS
~
OP AMP
FREaUENCY (Hd
FREQUENCY (Hz)
INPUT WIDEBAND VOLTAGE
NOISE VI BANDWIDTH (O.1Hz
TO FREQUENCY INDICATED)
,
AUDIO
~
JJ UIII
ri'i'llll~i Flillli~rY iTI'l ililGTi
0.01
I
= 2Rl
~
w
~'O!!_
;:
0.,. . .
AT 10Hz
i:!
~kHz
O.010':.'...J...J...Ju..u~,':.0--'...,L..LJ.L"':'::,O--'...,L..LJ.L~,OO
100
BANDWIDTH (kHz)
lk
SOURCE RESISTANCE IW
10k
w
~
3
~
w
~
100
1~
SUPPLY CURRENT
,.O,..-----.,-----.,..------r----,
10kll
10Ok\l soak!!
5DOlr.lI
~
.".,
4.01----+----+----="----:-=:-1
~
AT 10Hz
t--
OS
0
VI SUPPLY VOLTAGE
10.0
T! "2"C
--
-~
TEMPERATURE fOCI
CURRENT NOISE
vs FREQUENCY
VOLTAGE NOISE VI
SUPPLY VOl..TAGE
f
'L-...J.--~--~~---L--~~.
-~
w
AT 1kHz
~
~ 1.
[eno2 _ 1130nV1 2 J1/2
in"--lMH----x-1~
O~
3.0
f-
ffi
"~
a:
a:
il
02
>
r-
O.
'0
20
30
TOTAL SUPPLY VOLTAGE'(V+ - V-I (VOLTS)
40
2.01-L,7"f-----+---+----I
llfCORNER
, r-1"I'liiiil I
'0
100
lk
FREQUENCV (Hzl
PAGE 5-144
'Ok
'.0'-----,'='----.....25,...-----'3'------'4'
TOTAL SUPPLY VOLTAGE (VOLTS)
OP-37 ULTRA-LOW NOISE PRECISION HIGH-SPEED OPERATIONAL AMPLIFIER
TYPICAL PERFORMANCE CURVES
OFFSET VOLTAGE DRIFT OF
REPRESENTATIVE UNITS
vs TEMPERATURE
60
40
r-
...~
........,
0
"
~
>
...-
K
I--'"
V OP-37C
V / ' OP-37B
V
OP-37A
f-""
OP-37B
OP-J7A
a
OP-37A
""'"
~
-40
...... rWITH~
TRIMMING
10k POT DOES
NOT CHANGE
-75 -50 -25
0
25
50
w
2
0
o
-2
-4
>
OP-37B
75
100
1
1
WARM-UP OFFSET
VOLTAGE DRIFT
r- Tl. +2.J
..-
- .-"
"-v ""
Vs = ±15V
~
o
/
/
6
":;;
is
OP-37C
125 150 175
"" .......,
".
/'-
0
-2
-.-.
II
OP-3tc/G
>- -.
1
" "i'-
T~VOS
-60
~
~
I
~ -2 0
LONG TERM OFFSET
VOLTAGE DRIFT OF
REPRESENTATIVE UNITS
-
-......
~ V--
~
...
r-
f-""
"?
a.
OP-37A/E
o
V
o
TEMPERATURE(Ocl
oP-3iB/F
II)
a::
w
ii:
::::i
a.
:::E
TIME AFTER POWER ON (MINUTES)
TIME (MONTHS)
CC
~
Z
OFFSET VOLTAGE CHANGE
DUE TO THERMAL SHOCK
;;
-"30
I I I
I I I
~
~ 25
INPUT BIAS CURRENT
V8 TEMPERATURE
o
>-
V~,J15)-
TA
25"C
10
f-I-
1 1 1
~
0
f-f-
"
5
3
~
«
RESPONSE
B~ 1
IA 1 I
f-I- ~ DEVICE IMMERSED
o·
40
20
r--t'-~
80
-25
+2sLc
75
Vs = ±15V R L ;;;" 2kH
'" '"
60
40
70
6.
60
55
r\.
20
5
\.
102
10 3
104
FREQUENCY
105
(H~)
25
10 6
Vs =
50
~'5V
75
10 7
j
125
150
-75
-50
-25
85
75
70
GBW
~
0
-50
--r--
66
80
~
50
,,1'1
>-
g
c
80
g:
40
+25
+50
+75
PAGE 5-145
+100
+125
~
z
~
Vs
75
100
125
b
~
z
"
-00
I. ~,~~ II
-100
TA '" +2s<'C
1-1'"
-120
PHASE
30
GAIN
\
,.
-140
MAR
GIN \
=7
-180
20
\
:J:
55
•• ";;:'I'z
TEMPERATURE (OC)
50
..
l'
40
~
;;
0
50
SLEW
-25
25
GAIN, PHASE SHIFT vs
FREQUENCY
80
V
-- -
0
TEMPERATURE (OC)
•
108
OP-37B
t-
OP-37A
100
$M
0
\
10
0
SLEW RATE, GAIN BANDWIDTH
PRODUCT, PHASE MARGIN
V8 TEMPERATURE
80
TAl",
80
~ ['-.
TEMPERATURE ("C)
140
100
I'.
II I
-50
100
OPEN LOOP GAIN
vs FREQUENCY
f\.
,I'"
OP-378
I4J.J
0
60
1--1-
1"-
0
l'
~
TIME (SECONDS)
120
i"
OP-37C
OP-37A
IN 7rfC OIL BATH
0
-20
h
OP-37C
1\1\
SHOCK
2
J.J-
0
Vs'" ±15V
TA ~ 7rPC
~I
f-f- THERM~
f-I-
"~
IIII
0
~ 15
~
w
0
0
~
>w
~ 20
INPUT OFFSET CURRENT
VI TEMPERATURE
10
AV
=5
-180
\
-200
-220
-10
0.1
1.0
10
FREQUENCY (MHz)
100
o
~
a::
w
a.
o
OP-37 ULTRA-LOW NOISE PRECISION HIGH-SPEED OPERATIONAL AMPLIFIER
TYPICAL PERFORMANCE CURVES
OPEN LOOP VOLTAGE GAIN
va SUPPLY VOLTAGE
2.
MAXIMUM UN DISTORTED
OUTPUT va FREQUENCY
28
:-TJ~C
Rl
0=
TA
=
2SOC
14
1\
20
/' /"--
16
Vs = '15V
24
RL=11d!
18
I III
2kH
Y
/'
MAXIMUM OUTPUT SWING
va RESISTIVE LOAD
//
f/
2
5
TA
-
I'10
20
30
40
105
50
TOTAL SUPPl Y VOL TAGE (VOLTS)
r--
I I II
40
V
20
/
/'
LARGE SIGNAL TRANSIENT
RESPONSE
SMALL SIGNAL TRANSIENT
RESPONSE
+50mV
+10V
--
ov
ov
-lOV
II
-50mV
AV = +5
TA = +2Soc
AV = +5
TA = +2S"C
1000
1500
2000
2500
iiiii
Vs = ±15V
Vs = :t15V
500
10
OSCILLATION
80
60
1.0
LOAD RESISTANCE (kH)
v~" ±15~
VIN = 20mV
AV = +5
25°C
0.1
107
FREQUENCY (Hz)
SMALL SIGNAL OVERSHOOT
va CAPACITIVE LOAD
120
10 6
=
Vs = ±15V
2
0.0
100
--
SWING
NEGATIVE
SWING
12
//
poJITIJE
a
16
~/
0-
-
12
C L =2SpF
3000
CAPACITIVE LOAD (pF)
SHORT CIRCUIT CURRENT
va TIME
60
-
140
120
"-
T A = +250
Vs = ±15V
15C H
~ -~
-
ISC(+)
COMMON MODE INPUT RANGE
va SUPPLY VOLTAGE
CMRR va FREQUENCY
100
r-
I-
121-----+---
T A = +2S0C
VCM
1\
=
i'!
±10V
5
8
"
4 I-----""'~£..-_+----__I------I
~
I-
;i
\
r-
80
16r-----,-----~------r-~~
l!ll~l"l) I
~
a
~
~
a
-4
z
a
~
-8
8
60
-12
0
103
TIME FROM OUTPUT SHORTED TO GROUND{MINUTES)
-16
40
104
105
FREQUENCY (Hz)
PAGE 5-146
106
107
0
OP-37 ULTRA-LOW NOISE PRECISION HIGH-SPEED OPERATIONAL AMPLIFIER
TYPICAL PERFORMANCE CURVES
O.1Hz TO 10Hz
NOISE TEST CIRCUIT
OPEN LOOP VOLTAGE GAIN
VB LOAD RESISTANCE
LOW FREQUENCY NOISE
2.
2.
~
~2.0
80
w
~
Z
2kn
VOLTAGE GAIN
.. SO,OOO
+--"""'N'--+2:~~I22~~:Mn
NOTE: ALL CAPACITOR VALUES ARE FOR
1/
1.6
II
"~ 1.4
::
~
±1SV
•
~
0
w
~.' 12~!~11
I- Vs
~ 1.
40
~
: f-
;;
120
o
>
1.2
~
is
31.0
-120
z
o
~ 0.8
o
i"~
'= "::-
a.1Hz TO 10Hz PEAK-TO-PEAK NOISE
NOTE:
Observation time limited to 10 seconds
to insure 0.1 Hz cutoff.
NON POLARIZED CAPACITORS ONLY.
O.G
(I)
D.•
0.1
1.0
10
LOAD RESISTANCE (k!1)
100
a::
i&:
::l
UI
A.
~
PSRR
VB
FREQUENCY
SLEW RATE VB LOAD
19
160
TAl" 2501_
0
0""""
,. r---
~
r-- POSITI~ ~UPPLY
VB
TA =
15
AV = +5
Vo = 20Vp-p
NEGATIVE
o
17
10
SUPPLY
~
0
0
10
102
~
V
,.
~
103 104
lOS 106
FREQUENCY (Hzl
107
0.1
0
1.0
10
100
at
+5
~~
~
I---
~ r--
±3
±6
FALL
±9
±12
±15
±18
±21
SUPPLY VOLTAGE (VOL TSI
LOAD RESISTANCE (km
APPLICATION INFORMATION
Offset Voltage Adjustment
OP-37 Series units may be inserted directly into 725. OP-06,
OP-07 and OP-05 sockets with or without removal of external compensation or nulling components. In addition, the
OP-37 may be fitted to unnulled 741-type sockets; however,
if conventional 741 nulling circuitry is in use, it should be
modified or removed to enable proper OP-37 operation. OP37 offset voltage may be nulled to zero (or other desired
setting) through use of a potentiometer (see offset nulling
circuit).
The input offset voltage of the OP-37 and its drift with
temperature are permanently trimmed at wafer testing to a
very low level. However, iffurther adjustment of Vos is necessary, nulling with a 10kO potentiometer will not degrade
TCVos (see offset nulling circuit). Other potentiometer
values from 1 kO to 1MOcan be used with a slight degradation
(0.1 to 0.2I'VlOC) of TCVos. Trimming to a value other than
OFFSET NULLING CIRCUIT
The OP-37 provides stable operation with load capacitances
up to 2500pF and ±10V swings; larger capacitances should
be decoupled with a 500 decoupling resistor.
The designer is cautioned that stray thermoelectric voltages
generated by dissimilar metals at the contacts to the input
terminals can prevent realization of the drift performance
indicated. Best operation will be obtained when both Input
contacts are maintained at the same temperature, preferably
close to the temperature of the device's package.
PAGE 5-147
~r-f"---oV+
>--"-----+''----0 N.C.
NPUT
'0
~
6
~'::, .....
• ~•
'-
PAGE 5-151
6
7
2Ok"
v+
OUT (AI
vv-
OUT 181
OP-207 DUAL, ULTRA-LOW Vos, MATCHED OPERATIONAL AMPLIFIER
INDIVIDUAL AMPLIFIER CHARACTERISTICS
at Vs =
± 15V, T A = 25° C, unless otherwise noted.
OP-207B/F
OP-207A1E
PARAMETER
SYMBOL
CONDITIONS
Input Offset Voltage
Vos
Rs= toon
Input Offset Voltage
Stability
TYP
MAX
TYP
MAX
35
100
60
200
~V
aVos/Time (Note 1)
0.3
1.5
0.4
2.0
~V/Mo
Input Offset Current
los
0.9
2.8
1.5
6.0
nA
Input Bias Current
Ie
1.0
3.0
2.0
7.0
nA
Input Noise Voltage
enE!-E!:
O.IHz to 10Hz (Note 2)
0.35
0.6
0.35
0.6
~Vp_p
Input Noise
Voltage Density
en
10= 10Hz
(Note 2) '0 =IOOHz
'0= 1000Hz
10.3
10.0
9.6
18.0
13.0
10.3
10.0
9.6
18.0
13.0
nV/.rHz
Input Noise Current
i ne-e
(Note 2) O.IHz to 10Hz
Input Noise Current
Density
in
10= 10Hz
(Note 2) 10= 100Hz
'0= 1000Hz
Input Resistance Differential Mode
R'N
(Note3!
Input Resistance Common Mode
R 'NCM
Input Voltage Range
Common Mode
VCM=±13V
Power Supply Rejection
Ratio
PSRR
Vs= ±3V to ±18V
Large Signal Voltage
Gain
Avo
R L ",2kn. Vo= ±10V
Output
Voltage Swing
20
IVR
CMRR
Rejection Ratio
MIN
MIN
UNITS
14
30
14
30
pA p_p
0.32
0.14
0.12
0.80
0.23
0.32
0.14
0.12
0.80
0.23
pAl.rHz
60
30
Mn
200
120
Gn
±13.0
±14.0
±13.0
±14.0
V
106
123
100
120
dB
20
32
200
500
150
400
R L ",10kn
±12.5
RL ",2kn
R L ",lkn
±12.0
±10.0
±12.5
±12.0
±10.0
±13.0
Vo
±13.0
±12.8
±12.0
..VN
VimV
±12.8
±12.0
V
Vi~s
0.2
Slewing Rate
SR
RL ",2kn
Closed Loop Bandwidth
ew
AveL = +1.0
0.6
0.6
MHz
Open Loop Output
Resistance
Ro
Vo=O.lo=O
60
60
n
Power Consumption
Pd
No load
90
R E= 20kn
±4
Offset Adjustment Range
Input Capacitance
0.2
C 'N
120
8
NOTES:
1. Long Term Input Offset Voltage Stability relers to the averaged trend
line 01 Vos vs. Time over extended periods aiter the first 30 days 01
operation. Excluding the initial hour 01 operation, changes In Vos during
the Ilrst 30 operating days are typically 2.S,.V. Paremeter is sample tested.
2.
3.
PAGE 5-152
Sample tested.
Guaranteed by design.
100
±4
150
mW
mV
pF
OP-207 DUAL, ULTRA-LOW Vos, MATCHED OPERATIONAL AMPLIFIER
INDIVIDUAL AMPLIFIER CHARACTERISTICS at Vs = ± 15V, -55'C ,;TA s; 125'C, unless otherwise noted.
PARAMETER
SYMBOL
CONDITIONS
Input Offset Voltage
Vos
Rs= 100ll
MIN
OP-207A
TYP
MAX
MIN
OP-207B
TYP
MAX
UNITS
75
230
100
400
"V
0.4
1.3
0.7
1.8
Average Input Offset
Voltage Drift
Without External Trim
TCVoS
With External Trim
TCVoSn
Input Offset Current
Rp =20kll (Note 1)
0.4
los
1.8
TClos
10
Input Bias Current
Ie
3.0
Average Input Bias
Current Drift
TCle
12
I nput Voltage Range
IVR
Average Input Offset
Current Drift
Common Mode
Rejection Ratio
Power Supply Rejection
CMRR
VCM = ±13V
"VI'C
0.7
5.6
12.0
3.0
12
4.0
5.6
nA
pArc
14.0
nA
18
pArc
....
0
~
a.
0
±13.0
±13.5
±13.0
±13.5
V
CI)
103
120
97
117
dB
i&:
:::i
a.
:E
7
32
51
10
PSRR
Vs = ±3V to ±18V
Large Signal Voltage
Gain
Avo
RL ",2kll, Vo= ±10V
150
400
120
350
V/mV
Output
Voltage Swing
Vo
RL ",2kll
12.0
12.8
12.0
12.8
V
Ratio
•
"VN
II:
III
C
~
C
Z
0
~II:
III
INDIVIDUAL AMPLIFIER CHARACTERISTICS at Vs =
PARAMETER
SYMBOL
CONOITIONS
Input Offset Voltage
Vos
Rs = 1001l
± 15V, o·e $
MIN
70·e,
TA $
OP-207E
TVP
MAX
60
200
0.4
1.3
MIN
OP-207F
TYP
MAX
UNITS
90
350
"V
0.7
1.8
(Note 2)
"vrc
Average Input Offset
Voltage Drift
Without External Trim
TCVos
With External Trim
TCVosn
Input Offset Current
Average Input Offset
CUrrent Drift
Input Bias Current
Average I nput Bias
Current Drift
Input Voltage Range
Common Mode
Rp = 20kll (Note 1)
0.7
0.4
1.4
los
2.5
5.0
2.0
Ie
3.0
5.0
12
nA
pA/'C
11.0
nA
18
pAl'C
±13.0
±13.5
±13.0
±13.5
V
103
120
97
117
dB
TCl e
IVR
10.0
12
10
TClos
a.
0
unless otherwise noted.
CMRR
VCM=±13V
Power Supply Rejection
Ratio
PSRR
Vs = ±3V to ±18V
Large Signal Voltage
Gain
Avo
R L ",2kll. Vo= ±10V
150
400
120
350
VlmV
Output
Voltage Swing
Vo
RL ",2kll
12.0
12.8
12.0
12.8
V
Rejection Ratio
7
NOTES:
1. Exclude first hour of operation to allow for stabilization of external circuitry.
2. Sample tested.
PAGE 5-153
10
32
51
"VlV
OP-207 DUAL, ULTRA-LOW Vas, MATCHED OPERATIONAL AMPLIFIER
APPLICATION OF DUAL MATCHED OPERATIONAL
AMPLIFIERS
ADVANTAGES OF DUAL MATCHED OPERATIONAL
AMPLIFIERS
Dual Matched Operational Amplifiers provide the engineer a
powerful tool for the solution of a number of difficult circuit
design problems including true instrumentation amplifiers,
extremely low drift, high common mode rejection DC amplifiers, low DC drift active filters, dual tracking voltage references and many other demanding applications. These designs are based oil the principle that careful matching
between two operational amplifiers can, to a large extent,
eliminate the effect of DC errors inherent in the individual
amplifiers.
Reference to the circuit, a differential-in, differential-out
amplifier, shows how the reductions in error can be accomplished. Assuming the resistors used are ideally matched,
the gain of each side will be identical; ifthe offset voltages of
each amplifier are perfectly matched, then the net differential voltage at the amplifiers output will be zero. Note that the
output offset error of this amplifier Is not a function of the
offset voltage ofthe individual amplifiers, but only a function
of the difference (degree of matching) between the amplifiers' offset voltages. This error-cancellation principle holds
for a considerable number of input referred error parameters
- offset voltage, offset voltage drift, inverting and. nonInverting bias currents, common-mode and power supply
R.
Rl
*.
•
2Ok!!
1
14
- .....
SiDE.....
4
I.
V
OUTPU
11
R'
*
.
OP·20"
IN PUT
-
10
~
V
R4
POWER SUPPLIES
The V+ supply terminals are completely independent and
may be powered by separate supplies if desired (this
approach, however. would sacrifice the advantages of the
power supply rejection ratio matching). The V- supply terminals are both connected to the common substrate and
must be tied to the same voltage.
J
V.
NULL
Rc
RB
NULL
OFFSET TRIMMING
f-o o..----ov+
,
rejection ratios. Note also that the impedances of each input,
both common-mode and differential mode, are extremely
high and can also be tightly matched, an important feature
not possible with single operational amplifier circuits. Common mode rejection can be made exceptionally high; this is
especially important in instrumentation amplifiers where
errors due to large common-mode voltages can be far
greater than those due to noise or drift with temperature.
(For example, consider the case of two op amps, each with
BOdS (100IOVIV) CMRR. However, if the CMRR of one device
is +100IOVIV while CMRR of the other is -100I'VlV for a net
200l'VlV CMRR match, the resultant input reference error
over a 10V common-mode input signal will be 2mV.
6
-
Offset trimming terminals are provided for each ampllfer of
the OP-207 - however. guaranteed performance over temperature can be obtained by trimming only one side (side A)
to match the offset of the other for a net differential offset of
zero. This is due to the specific procedure used during factory testing of the devices; however. results which are essentially the same may be obtained to trimming side S to match
side A, or by nulling each side individually.
The OP-207 is designed to provide lowest drift performance
when trimmed with a 20kO potentiometer; this value provides about ±4mV of adjustment range which should be
considerably more than adequate for most applications.
When finer resolution of trimming is desired, or where
unwanted changes in potentiometer position with time and
temperature could create unacceptable offsets. the sensitivity to offset potentiometer position may be reduced by using
the circuit.
PAGE 5-154
PMI
OP-215
DUAL PRECISION JFET INPUT
OPERATIONAL AMPLIFIER
®
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
High Slew Rate .............................. 18V/ILs
Fast Settling Time ............................ 900ns
Low Input Offset Voltage Drift .............. 3.0ILV/oC
Wide Bandwidth ............................... 6MHz
Temperature Compensated Input Bias Currents
Guaranteed Input Bias Current ..... 18nA Max (125° C)
Bias Current Specified WARMED UP Over Temperature
Low Input Noise Current ................ O.OlpAlv'Hi
High Common Mode Rejection Ratio .......... 100dB
PIN compatible with Standard Dual Pinouts
125°C Temperature Test DICE
Models with MIL-STD-883 Class B Processing
Available from Stock
GENERAL DESCRIPTION
tracking and convenience advantages of a Dual Op-Amp
configuration.
Low input offset voltages, low input currents and minimal
drift parameters are featured in these high speed amplifiers.
On-chip Zener Zap trimming is used to achieve low Vos while
a bias current compensation scheme gives a low input bias
current at elevated temperatures. Thus the OP-2l5 features
an input bias current of l8nA at 125°C ambient (not junction)
temperature which greatly extends the application usefulness of this device.
Applications include high speed amplifiers for current output DACs, active filters, sample-and-hold buffers, and photocell amplifiers. For additional precision JFETop amps, see
the OP-15, OP-16 and OP-17 data sheets.
PIN CONNECTIONS
The OP-2l5 offers the proven BIFET performance advantages of high speed and low input bias current with the
ORDERING INFORMATIONt
T.. - 25°C
VosMAX
(mV)
TO-99
a-PIN
1.0
1.0
2.0
2.0
4.0
6.0
OP215AJ'
OP215EJ
OP215BJ'
OP215FJ
OP215CJ'
OP215GJ
HERMETIC HERMETIC OPERATING
DIP
DIP
TEMPERATURE
a-PIN
RANGE
14-PIN
OP215AZ'
OP215EZ
OP215BZ'
OP215FZ
OP215CZ'
OP215GZ
+_
OP215AY'
OP215EY
OP215BY'
OP215FY
OP215CY'
OP215GY
MIL
COM
MIL
COM
MIL
COM
7 OUT IB)
-INIAl
1
+IN (A)
2
Ei +IN IS)
•
vTO-99
(J-Sufflx)
BAL (A)
J
BAL IB)
5
a.
o
v+
(BI-
+IN IBI 6
9
-IN (BI
8 BAL (81
1
14 PIN HERMETIC DIP
(V-Suffix)
• Also available with MIL-STO-8838 processing. To order add/BS3as a suffix to
8 PIN HERMETIC DIP
(Z-Sufflx)
the part number.
t All listed parts are available with 160 hour burn-in. See Ordering Information,
Section 2.
SIMPLIFIED SCHEMATIC DIAGRAM (1/2 OP-21S)
-NOTE: R7, RS ARE ELECTRONICALLY ADJUSTED
ON CHIP FOR MINIMUM OFFSET VOLTAGE.
01.
024
017
NON-INV
INPUT +
.'3
022
, . - - - - 1 - - - - 4 - - 0 OUTPUT
v·
PAGE 5-155
~
~
'V+ (A) & V+ (B) iNTERNALLY CONNECTED.
v+
C
II:
W
6 -IN (8)
+IN (A) 3
ii:
::::i
a.
:2
Z
•
(A)~_
-IN IA) 2
en
II:
W
o
v+
OUT
PACKAGE
•
OP-215 DUAL PRECISION JFET INPUT OPERATIONAL AMPLIFIER
ABSOLUTE MAXIMUM RATINGS (Note 2)
(Unless otherwise specified the absolute maximum
negative input voltage is equal to the negative power
supply voltage.)
Output Short Circuit Duration ............... Indefinite
Storage Temperature Range ........ -65·Cto +150·C
Lead Temperature (Soldering, 60 sec) ........... 300·C
DICE Junction Temperature (Tj) ....... -65·C to + 150·.C
Supply Voltage
OP-21SA, OP-21SB, OP-21SE, OP-21SF
(All DICE except GR) ....................... ±22V
OP-21SC, OP-21SG (GR DICE only) ............ ±18V
Internal Power Dissipation (Note 1) .............. SOOmW
Operating Temperature Range
OP-215A,OP-215B,OP-21SC ....... -55·Cto +125·C
OP-215E,OP-215F,OP-215G ........... O·Cto +70·C
Maximum Junction Temperatllre (TJ) .......... + 150·C
Differential Input Voltage
OP-21SA, OP-215B,}
OP-215E,OP-215F
(All DICE except GR) '" ± 40V
NOTES:
1. See table for maximum ambient temperature rating and derating faptor.
MAXIMUM AMBIENT
TEMPERATURE
FOR RATING
14-Pin Hermetic DIP (V)
l00·C
8O·C
7S'C
TC>-99 (J)
OP-215C, OP-21SG (GR DICE only) ............ ± 30V
Input Voltage
OP-215A, OP-21SB,}
±20V
OP-21SE,OP-215F
(All DICE except GR)
DERATE ABOVE
MAXIMUM AMBIENT
TEMPERATURE
SOPon Hermetic DIP (Z)
10.0mW/·C
7.1mW/·C
6.7mW/·C
2·. Absolute maximum ratings apply to bOth packaged parts and dice, unless
otherwise noted.
OP-215C, OP-215G (GR DICE only) ............ ± 16V
ELECTRICAL CHARACTERISTICS at Vs '" ±1SV, T A'" 25· C, unless otherwise noted,
OP-21SA/E
PARAMETER
Input Offset
Voltage
Input Offset Current
SYMBOL,
vos
CONDITION
RS -SOO
'G' Grade
=25°C (Note 1)
IB
Input Resistance
RIN
Large 81gnal Voltage
Gain
.Output Voltage
Swing
Avo
Vo
Current
Gain Bandwidth
Product
Closed Loop
Bandwidth
Settling Time
Input Voltage Range
Common Mode
Rejeetion Ratio
Power Supply
Rejection Ratio
ISY
Input capacitance
TYP
MAX
UNITS
2.0
2.0
2.5
4.0
6.0
mV
3.0
3.0
50
3.0
100
5.0
100
5.0
2DD
15
·300
18
600
TJ == 25 C (Note 1)
15
100
15
200
Device Operating
18
300
18
400
RL22kO
150
VO=±1DV
500
75
±12
±13
±12
±13
Al =2kO
±11
±12.7
±11
±12.7
10.0
7.0
12.0
3.5
5.7
3.5
5.7
3.0
5.4
MHz
13
12
MHz
2.3
2.3
2.4
1.1
1.1
1.2
.s
0.9
0.9
1.0
+10.2
+14.8
+10.2
+14.8
+10.1
+14.8
-10.2
-1.1.5
-10.2
-11.5
-10.1
-11.5
A, B, C Grades
86
100
86
100
82
96
E, F, G Grades
82
100
82
100
80
96
Vs = ±10V to ±16V
mA
VIps
to 0.10%
IVR
V
7.0
15
to 0.05% (Note 2)
CIN
±12.7
5.0
100.01%
in
±13
±11
18
13
en
VlmV
7.5
AVCl =+1.0
VCM=±IVR
n
2DD
±12
8.5
pA
'0 '2
18
CLBW
PSRR
8.0
pA
10.0
(Note 3)
CMRA
8.5
50
'G' Grade
GBW
Is
220
Rt. -10kO
6.0
MIN
1012
1012
AVCl = +1.0 (Note 3)
Input Noise
Current Density
MAX
0.8
SA
Input Noise
Voltage Density
TYP
1.0
5.0
Supply
Slew Rate
MIN
OP-21SC/G
MAX
0.2
Device Operating
D
Input Bias Currant
OP-21SB/F
TYP
50
100
TJ
lOS
MIN
10
10
51
16
fo= 100Hz
20
20
to= 1000Hz
15
15
20
15
'0= 100Hz
0.01
0.01
0.01
fo= 1000Hz
0.01
0.01
0.01
3.0
3.0
3.0
dB
80
Vs = ±10V 10 ±15V
NOTES:
1, Input bias current is specified for two different conditions. The T J = 25° C
specification is with the junction at ambient temperature; the Device Operati ng specification is with the device operating in a warmed-up condition at
25° C ambient. The warmed-up bias current value is correlated to the
junction temperature value via the curves of Is vs T j and's vs TA • PMI has a
bias current compensation circuit which gives improved bias current and
bias current over temperature vs standard JFET !nput op amps. laand los
V
100
.VIV
nV/.vHZ
pAl.,fFfL
pF
are measured at V OM = O.
2.
Settling time is defined here for a unity gain inverter connection using 2kn
resistors. It is the time required for'the error voltage (the voltage at the
inverting input pin on the amplifier) to settle to within a specified percent
of its final value from the time a 10V step input is applied to the inverter.
See settling time test circuit.
3. Sample tested.
PAGE 5-156
OP·215 DUAL PRECISION JFET INPUT OPERATIONAL AMPLIFIER
ELECTRICAL CHARACTERISTICS at Vs
= ±15V. -55°e s
TA$ +125°e. unless otherwise noted.
OP·215B
OP·215A
PARAMETER
SYMBOL
CONDITION
Input Offset Voltage
Vos
AS""
MIN
son
TYP
MAX
0.5
2.0
10
MIN
Op·215C
TYP
MAX
MIN
TYP
MAX
UNITS
1.5
3.0
3.0
6.0
mV
3.0
10
6.0
Average Input Offset
Voltage Drift
Without External Trim
Tevos
INole31
3.0
With External Trim
TeVOS n
Rp:= 100kn
3.0
3.0
+ 125°C
TA == + 125°C
0.8
0.8
TJ ==
Input Offset Current
(Note 11
lOS
+ 125°C
TA == + 125°C,
TJ ==
Input Bias Current
(Note 1)
Input Voltage Range
Common Mode
Rejection Ratio
Power Supply
Rejection Ratio
Device Operating
IVR
CMAA
PSRR
AVO
1.0
12
1.2
14
1.2
14
1.5
22
1.5
10
1.5
10
1.8
15
18
2.2
18
2.7
28
-
2.2
+10.2
+14.6
+10.2
+14.6
+10.1
+14.6
-10.2
-11.3
-10.2
-11.3
-10.1
-11.3
82
97
82
97
80
93
VCM=±IVR
10
Vs "" ±10V to ±16V
100
15
nA
II:
1&1
126
p.V/V
:J
IL
:::i!
2kO
Vo = ±10V
30
110
30
110
25
100
V/mV
±12
±13
±12
±13
±12
±13
V
oJ
II:
1&1
IL
ELECTRICAL CHARACTERISTICS at Vs= ±15V. OOG $ T A $ +70 e. unless otherwise noted.
Op·215E
OP·215F
SYMBOL
CONDITION
TYP
MAX
TYP
MAX
Input Offset Voltage
VOS
RS::: 500
0.4
1.65
1.4
2.65
15
3.0
15
MIN
MIN
o
OP·215G
PARAMETER
MIN
TYP
MAX
UNITS
3.5
8.0
mV
Average Input Offset
Voltage Drift
6.0
Without External Trim
TCVos
(Note 3)
3.0
"Vith External Trim
TCVOSn
Rp::: 100kO
3.0
TJ=+70°C
0.06
0.45
0.06
0.45
0.08
0.65
lOS
TA::: + 70 D C, Device Operating
0.08
0.80
0.08
0.80
0.10
1.2
TJ=+70°C
0.12
0.70
0.12
0.70
0.14
0.9
T A ::: +700 C, Device Operating
0.16
1.40
0.16
1.40
0.19
1.8
Input Offset Current
Input Bias Current
(Note 1)
'B
Input Voltage Range
IVR
Power Supply
Rejection Ratio
CMRR
PSRR
Output Voltage
Swing
VCM=±IVR
3.0
4.0
+10.2
+14.7
+10.2
+14.7
+10.1
+14.7
-10.2
-11.4
-10.2
-11.4
-10.1
-11.3
80
98
80
98
76
94
Vs = ±10V to ±16V
13
13
100
nA
nA
dB
100
Vs == ±10V to ±15V
20
159
p.VlV
RL 2': 2kO
Large Signal
Voltage Gain
Z
o
5
o
Rejection Ratio
C
C
Swing
Common Mode
rn
dB
iL
23
Output Voltage
(Notel)
II
nA
100
Vs == ±10V to ±15V
RL~
Large Signal
Voltage Gain
Device Operating -
4.0
AVO
VO""±10V
50
180
50
180
35
130
±12
±13
±12
±13
±12
±13
NOTES:
1. Input bias current is specified for two different conditions. The T j = 25°C
specification is with the junction at ambient temperature; the Device Operating specification is with the device operating in a warmed-up condition at
25° C ambient. The warmed-up bias current value is correlated to the
junction temperature value via the curves of 'B vs Tjand 'Bvs T A. PMI hasa
bias current compensation circuit which gives improved bias current and
bias current over temperature vs standard JFET input op amps. 'Band los
are measured at VeM = O.
2.
Settling time is defined here for a unity gain inverter connection using 2kO
resistors. It is the time required for the error voltage (the voltage at the
inverting input pin on the amplifier) to settle to within a specified percent
of its final value from the time a 10V step input is applied to the inverter.
See settling time test circuit.
3. Sample tested.
PAGE 5·157
V/mV
OP-215 DUAL PRECISION JFET INPUT OPERATIONAL AMPLIFIER
DICE CHARACTERISTICS
(125° C TESTED DICE AVAILABLE)
1.
2.
3.
4.
5.
8.
7.
8.
INVERTING INPUT (A)
NON·INVERTING INPUT (A)
NULL (A)
VNULL(B)
NON·INVERTING INPUT (I)
INVERTING INPUT (I)
NULL (I)
9. Vt
10. Vo(l)
11. V+
12. VolA)
13. V+
14. NULL (A)
DIE SIZE 0.058 x 0.083 Inoh
Refer to Section 2 for additional DICE Information.
All V+ PADS ARE INTERNALLY CONNECTED
ELECTRICAL CHARACTERISTICS at Vs = ± 15V, TA = +25° C for OP-215N,
= +125°C for OP-215NT and OP-215GT devices, unless otherwise noted.
OP-215G
and
OP-215GR
devices,
TA
PARAMETER
SYMBOL CONDITIONS
Input Offset Voltage
Vos
Rs = 500
OP-21SNT
LIMIT
OP-21SN
LIMIT
OP-215GT
LIMIT
OP-21SG
LIMIT
OP-21SGR
LIMIT
UNITS
2.0
1.0
3.0
2.0
6.0
mVMAX
Input Bias Current
Is
16
16
Input Offset Current
los
14
14
Large Signal
Voltage Gain
Avo
Input Voltage Range
IVR
Common Mode
Rejection Ratio
Power Supply
Rejection Ratio
Output Voltage Swing
Vo =±10V,
RL =2kn
VcM=±IVR
nAMAX
30
150
30
75
50
VlmVMIN
±10.2
±10.2
±10.2
±10.2
±10.1
VMIN
82
dB MIN
100
p.VIVMAX
± 12
±II
± 12
± II
VMIN
8.5
12.0
mAMAX
82
B6
B2
86
PSRR
Vs = ±10 to ±16V
Vs= ±10 to ±15V
100
51
100
80
Vo
RL = 10kn
RL =2kn
±12
CMRR
± 12
±II
±12
Supply Current
8.5
Isv
NOTE: For 25°C characteristics of NT & GT devices. see N&G characteristics respectively.
TYPICAL ELECTRICAL CHARACTERISTICS at Vs =
PARAMETER
Average Input
Offset Voltage Drift
Average Input
Offset Voltage Drift
nAMAX
OP-21SNT
TVP
OP-215N
TVP
OP-215GT
TVP
OP-215G
TVP
OP-21SGR
TYP
UNITS
2.0
2.0
3.0
3.0
4.0
p.VloC
0.5
0.5
2
p.V/oC
3.0
3.0
3.0
3.0
3.0
pA
IS
IS
IS
15
IS
pA
17
2.2
1.1
0.9
17
16
2.3
1.1
0.9
16
2.3
1.1
0.9
IS
2.4
1.2
1.0
VII's
2.2
1.1
0.9
6.0
6.0
5.7
5.7
5.4
MHz
AVCL =+1
14
14
13
13
12
MHz
fo= 100Hz
20
IS
20
15
20
15
20
IS
20
IS
nVlVHZ
0.01
0.01
0.01
0.01
0.01
pAlVHZ
3
3
3
SYMBOL CONDITIONS
Un nulled
TCVos
Re= lOOkn
Nulled
TCVOSn
Re= lOOkn
Input Offset Current
los
Input Bias Current
Is
Slew Rate
SR
Settling Time
t,
Gain Bandwidth
Product
GBW
Closed Loop
Bandwidth
CLBW
Input Noise
Voltage Density
en
Input Noise
Current Density
In
Input Capacitance
C 'N
± 15V, T A = +25° C, unless otherwise noted.
AVCL =+1
to 0.01%
to 0.05%
to 0.10%
f o = 1000Hz
f o = 100Hz
fo=1000Hz
3
PAGES-1S1
p.s
pF
OP-215 DUAL PRECISION JFET INPUT OPERATIONAL AMPLIFIER
TYPICAL PERFORMANCE CURVES
SETTLING TIME
LARGE SIGNAL
TRANSIENT RESPONSE
SMALL SIGNAL
TRANSIENT RESPONSE
II
11>
N
Q.
-10
'-_.....!_----'u.J'-_.L._---l-"'-_-'
o
0.5
1.0
2.0
1.5
2.5
o
III
cr.
SETTLING TIME (pSEC)
III
ii:
::::i
Q.
:::E
«
«
Z
o
....I
CLOSED LOOP BANDWIDTH
AND PHASE SHIFT vs FREQUENCY
-...
18
16
14
. PHASEIMAL,IN I=I~!
'\
12
\
10
BANDWIDTH vs TEMPERATURE
90
100
28
110
24
VS'" ±15V
120
TA"'25°C
130
120
Vs
-
\AV> 10
20
150
\
z
"-
16
170
-2
'\
-S
I---
190
'\.
-6
200
AV'" +1
\ \1 II
-10
JoP
~
CLOlED
! ...........~IDTIH AV '" +1
12
180
-4
20
16
12
Vs = ±15V
T A =25°C
AV '" +1
I
I
\
r-r--
I'
I
"T
"'- i
I
100kHz
lMHz
I'
FREQUENCY (Hz)
-
-25
25
50
75
100
70
60
~
I
I
>~ 30
I
~
NEGATIVE
I\..
I\..
'"
20
10
100
lK
10K
lOOK
~
1M
-
"
10M 100M
COMMON MODE REJECTION
RATIO vs FREQUENCY
100 r---,--'""':-r--,--,--,--,-,
801---+'-+--+
Vs = ±15V
60 I---+-+-~'f
I
'
I
I
---+-j---+_.....
40
'
I
:----..... ~IVEI
20
10
I
o
-50
oL--L_J-_L--L_J-_L-.....J._-'
-25
25
50
75
100
AMBIENT TEMPERATURE (OC)
PAGE 5-159
125
cr.
III
Q.
o
-r-----r-_
w
!
10MHz
-tAV
I L/~
r-- ~-+---
40
I\..
FREQUENCY (Hz)
SLEW RATE vs TEMPERATURE
50
TA '" ?5~C -
40
125
~
v~=+lL
........
60
TEMPERATURE eel
~
-
-20
-50
100
UNDISTORTED OUTPUT SWING
-
I
PRODUCT
FREQUENCY (MHz)
24
i-
GAIN BANDWIDTH
o
10
28
100
80
160
\
""
±15V
=
BANDWIDTH VARIATION FROM
±5V .;; Vs .;; ±20V IS < 5%
140
-
~
OPEN LOOP
FREQUENCY RESPONSE
1
100M
FREaUENCY(Hz)
OP-21S DUAL PRECISION JFET INPUT OPERATIONAL AMPLIFIER
TYPICAL PERFORMANCE CURVES
POWER SUPPLY REJECTION
VB t'REQUENCY
120
'iii 110
3!
."
100
z
60
~
70
">
t
Oil
"~
50
0
;::
0
ff!
~
90
-
60
-
140
~120 I-
I
~5·C-
" r
" '""- "'- '"
""
fA =
"'" I'\.
10
100
1.
I
I'\.
'\..
20
w
10K
TOOK
t'\.
~
:"-.
1M
10
roo
l-
Q
!~!lll'6!
w
AV"'D
~
1/
v
v
";:!
60
~
40
g
10K
lK
FREQUENCY (Hz)
l-
T • 26°C
so t1/1 CORNER fREQUENC
i ..
o
0.1 ' -
10M
1111111
!
§
POSI)IVESUPPLY
NEGATIVE
_SUPPLY
30
10
VOLTAGE NOISE
VB FREQUENCY
"1
40
o
OUTPUT IMPEDANCE
vs FREQUENCY
lOOK
1M
100
10
1
10M
,.
fREQUENCY 1Hz)
FREQUENCY (Hz)
BASIC CONNECTIONS
SETTLING TIME TEST CIRCUIT
2KO 0.'%
+1SV
:~cr-4~~2~kn~0"r%-e__~
.. 0
0.1%
-15V
SUMMING
NODE
",'-1
5kfi 0.1%
+15V
(PINOUT FOR "J" AND "Z" PACKAGES ONLYI
SLEW RATE TEST CIRCUIT
INPUT OFFSET VOLTAGE NULLING
v+ 0-----..,.-----,
10pf
-IN
>"-----{)DUf (AI
+IN
L--------ov_
TOOpf
NOTE:
Vas CAN BE TRIMMED WITH POTENTIOMETERS RANG·
ING FROM 10k{} TO 1MO. FOR MOST UNITS TCVOS WILL
BE MINIMUM WHEN Vos IS ADJUSTED WITH A 100kO
POTENTIOMETER.
(PINOUT FOR "J" AND "Z" PACKAGES ONLYI
("Y" PACKAGE ONLY)
PAGE5-1BO
10K
OP-215 DUAL PRECISION JFET INPUT OPERATIONAL AMPLIFIER
BASIC CONNECTIONS
APPLICATION INFORMATION
TYPICAL BURN-IN CIRCUIT
DYNAMIC OPERATING CONSIDERATIONS
As with most amplifiers, care should be taken with lead
dress, component placement and supply decoupling in
order to ensure stability. For example, resistors from the
output to an input should be placed with the body close to
the input to minimize "pick-up" and maximize the frequency
of the feedback pole by minimizing the capacitance from the
input to ground.
+lSV
100kH
200kH
lOOk!}
NOTES:
1) T A = 125'C TO +lS0"C
2) RESISTORS ARE TYPE
RN55D, .'1%
-15V
("J" AND .. z.. PACKAGES ONLY)
A feedback pole is created when the feedback around any
amplifier is resistive. The parallel resistance and capacitance
from the input of the device (usually the inverting input) to
AC ground sets the frequency of the pole. In many instances
the frequency of this pole is much greater than the expected
3dB frequency of the closed loop gain and consequently
there is negligible effect on stability margin. However, if the
feedback pole is less than approximately six times the
expected 3dB frequency, a lead capacitor should be placed
from the output to the negative input of the op amp. The
value of the added capacitor should be such that the RC time
constant of this capacitor and the resistance it parallels is
greater than or equal to the original feedback pole time
constant.
•
I/)
~o
en
II:
IU
ii:
:::i
Go
~
60
II
40
25
75
TEMPERATURE (~Cl
17.
125
INPUT BIAS CURRENT
VB TEMPERATURE
14
I VS',
12
!
•o
7 ••
'.I~V
80
-
AVCL = 100
'~~~~ .',~I
20
±5
±10
SUPPLY VOLTAGE (VOLTS)
'~~~~ ,' ,'11
160
1.5k
,.Dk
16.
Vs = '15V
180
i
~
,.0
-100
.0
-60
f-+---:J.""I--'--+-
"" 120 f-+-+-+-/-::;.....9-----1---1----l
~
ii,l100 f--j-..4'--+-f-~-+
....-V
TEMPERATURE rOC)
140
II:
/
100
f-+--+--+-+
~'60r-t--+--r-+~~r-+-~-+-~
/
200
100
16
FREQUENCY (Hz)
J
50
lillJ
IIII
I.'
INPUT OFFSET CURRENT
vs TEMPERATURE
!!!
o
-20
0.015
.:1:15 ±16.7
.00
-so
'"'
40
8
-100
AVCL" 1000
6.
600
r---,
, / I--"""
10
...........
RL=25kn
TA = 25°C
20
NULLED TO ZERO OfFSET AT 25 C
WITH 10k POT
-2'
~
~s 1,1 ~\.~ I
100
RS '" 50!!
r'\.
CLOSED LOOP GAIN
VB FREQUENCY
120
Tl.~·c r-
I ••
/
25
INPUT OFFSET VOLTAGE
POWER SUPPLY VOLTAGE
12.
100
7.
VB
140
100
I ••
60 !:-.-'--'-..l:-....J..---L_L-L...L_"L• . . .I±16.7
TEMPERATURE reI
LARGE SIGNAL TRANSIENT RESPONSE
SMALL SIGNAL TRANSIENT RESPONSE
OUTPUT
OUTPUT
::zT'00PF
25k~
PAGE 5-168
AL
CL
2"~' ••PF
OP-220 MICROPOWER PRECISION DUAL OPERATIONAL AMPLIFIER
TYPICAL PERFORMANCE CURVES
NOISE CIRCUIT MODEL
~
~
II
II)
a:
w
RLOAD (OHMS)
ii:
:::i
A::E
c
VOLTAGE NOISE DENSITY (en)
VB FREQUENCY
:izi!
CURRENT NOISE DENSITY linl
vs FREQUENCY
o
~a:
'0
'000.
.
.
.
w
~
..
!
!!J0
...~
A-
~
o
~
'00
2
....
ffi
II! 0.10
a
g
'0
0.'
'0
0.01
'00
0.'
'000
'.0
'00
'0
'000
FREQUENCY (Hz)
FREQUENCY (Hz)
SPECIAL NOTES ON THE APPLICATION OF
DUAL MATCHED OPERATIONAL AMPLIFIERS
R3
ADVANTAGES OF DUAL MONOLITHIC
OPERATIONAL AMPLIFIERS
",.n
Dual Matched Operational Amplifiers provide the engineer
with a powerful tool for the solution of a number of difficult
circuit design problems, including true instrumentation
amplifiers, extremely low drift, high common mode rejection
DC amplifiers, low DC drift active filters, dual tracking vOltage references, and many other demanding applications.
These designs are based on the principle that careful matching between two operationsal amplifiers can, to a large
extent, eliminate the effect of DC errors inherent in the individual amplifiers.
Reference to the circuit shown in Figure 1, a differential-in,
differential-out amplifier, shows how the reductions in error
can be accomplished. Assuming the resistors used are
ideally matched, the gain of each side will be identical. If the
offset voltages of each amplifier are perfectly matched, then
the net differential voltage at the amplifier's output will be
v-
R,
'2
OUTPUT
OP·2lO
INPUT
'0
FIGURE 1.
Y PACKAGE ONLY
PAGES-18B
OP-220 MICROPOWER PRECISION DUAL OPERATIONAL AMPLIFIER
zero. Note that the output offset error of this amplifier is not a
function of the offset voltage of the individual amplifiers, but
only a function of the difference (degree of matching) between the amplifiers' offset voltages. This error-cancellation
principle holds for a considerable number of input referred
error parameters - offset voltage, offset voltage drift, inverting and non-inverting bias currents, common-mode and
power supply rejection ratios. Note also that the impedances
of each input, both common-mode and differential mode, are
extremely high and can also be tightly matched, an important feature not possible with single operational amplifier
circuits. Common mode rejection can be made exceptionally
high; this is especially important in instrumentation amplifiers where errors due to large common-mode voltages can be
far greater than those due to noise or drift with temperature.
For example, consider the case of two op amps, each with
BOdB (1OO!,V/v) CMRR. However, if the CMRR of one device
is +100!'V/v while CMRR of the other is -100!'V/v for a net
200!'V/v CMRR match, the resultant input referred error over
a 10V common-mode input signal will be 2mV.
OFFSET TRIMMING -
Y PACKAGE ONLY
Offset trimming terminals are provided for each amplifier of
the OP-220.
The OP-220 is designed to provide lowest drift performance
when trimmed with a 10kO potentiometer; this value provides about ±4mV of adjustment range which should be
considerably more than adequate for most applications.
Where finer resolution of trimming is desired, or where
unwanted changes in potentiometer position with time and
temperature could create unacceptable offsets, the sensitivity to offset vs. potentiometer position may be reduced by
using the circuit of Figure 2.
vRS
NULL
~11(~------10kn T O T A L - - - - - - _ . I
MODEL
NULL RANGE
FIXED RESISTORS
RA, Rs
POTENTIOMETER
RC
OP-220
IN Y
±800J,lV
2.7kn.
5.0kn
PACKAGE
FIGURE 2.
compactly built using the OP-220. The 3-amplifier design,
while more complex, has the advantages of convenient overall gain adjustment by trimming a single resistor (R3) and of
wide common-mode voltage handling capability at any
overall gain, plus improved gain linearity. Slew rate, small
signal bandwidth, and full power bandwidthare also superior
and may be further improved by choosing a high-speed
op-amp such as the OP-21 series for the output op-amp.
INSTRUMENTATION AMPLIFIER 2 OP-AMP DESIGN
R1
990k
INSTRUMENTATION AMPLIFIERS USING OP-220
n
V1
Instrumentation Amplifiers with performance surpassing
those costing many hundreds of dollars can be easily and
INSTRUMENTATION AMPLIFIER -
RC
NULL
3 OP-AMP DESIGN
Y PACKAGE ONLY
OFFSET NULLING CIRCUIT
VR4
20k
R6
200kn
R1
90k.l1
12
INPUT
R3
OUT A
OUTPUT
2Ok~
OP-2lO
R2
90kf!
RS
20k!1
Vour" VIN (1 + R1;3 R2)
GAIN LIN
eo
•
~
INPUT
0.002%
"">_-I.'."0'---__0:.oU7 s
GAIN'" 100
SLEW RATE" O.05V/rSEC
R7
PSRR'" 104dB
200kn
IF~=Ws
THEN CMRR '" 148dB
ADJUST R7 FOR MAXIMUM CMRR
V-
Y PACKAGE ONLY
PAGE 5-170
PMI
OP-227
ULTRA-LOW NOISE, LOW OFFSET DUAL
INSTRUMENTATION OPERATIONAL AMPLIFIER
®
achieve AC performance previously unattainable with op-amp
based instrumentation designs.
FEATURES
•
•
•
•
•
•
•
•
•
•
Excellent Individual Amplifier Parameters
LowVos .....••........•................••..... 2O,.V
Tight Oftset Voltage Match ...................... 25 p.V
Tight Oftset Voltege Match VI. Temperature . .. 0.3 p.V/o C
....•.•.......•..• 3nVl.JHi
Unprecedented Low Noise { ......•.••........ 0.2 ,.Vp-p
Fast....................................... 2.& VI p.I8C
..•....••..•.....••.••.................... &MHz
Steble .•................................... 0.3,.VloC
•..•......•..•..•..............•..... 0.2p.VlMo
High Gain •...•.••..................•...... 1.& million
Excellent Gain Match ..•.•................•...... 1.5%
High Channel Separation ............•......•.. 154 db
When utilized in a three op-amp instrumentation amplifier
configuration, the OP-227 can easily achieve a CMRR in
excess of 100 db at 10 KHz. In addition, this device has an
open-lOOp gain of 1.5 M with a 1KO load and a gain match of
1.5% between amplifiers. The OP-227 also features an I S of
±10nA, an los of 7nA, and guaranteed matching of input
currents between amplifiers. These outstanding input current
specifications are realized through the use of a unique inputcurrent cancellation circuit which typically holds Isand los to
±20 nA and 15 nA respectively over the full military temperature range.
Other sources of input-referred errors, such as PSRR and
CMRR, are reduced by factors in excess of 120dB for the
individual amplifiers. D.C. stability is assured by a long-term
drift specification of 0.2 p.Vlmonth.
GENERAL DESCRIPTION
The OP-227 is the first dual amplifier to offer a combination of
low offset, low noise, high speed and guaranteed amplifier
matching characteristics in one device. The OP-227 with aVos
match of 25p.V, a TCV os match of 0.3,.wo C, and a lIf corner of
only 2.7 Hz is the best choice for precision low noise deSign.
These D.C. characteristics coupled with a slew rate of 2.8 VI,.s
and a small-signal bandwidth of 8 MHz allow the deSigner to
Matching between channels is provided on all critical parameters including offset voltage, tracking of offset voltage vs.
temperature, non-inverting bias current, CMRR, and power
supply rejection ratio. This unique dual amplifier allows the
complete elimination of external components for offset nulling
and frequency compensation.
The OP-227 is pin compatible with the OP-10 and OP-207.
ORDERING INFORMATIONt
TA-2S'C
vosMAX
I,.V)
HERMETIC
DIP
14-PIN
OPERATING
TEMPERATURE
RANGE
80
80
120
120
180
180
OP227AY'
OP227EY
OP227BY'
OP227FY
OP227CY'
OP227GY
MIL
INO
MIL
INO
MIL
INO
PIN CONNECTIONS
14-PIN CERAMIC DIP
(Y-SUFFIX)
NOTE:
Device may be operated even II
Insertion Is reversed; this 18 due
to Inherentsymmelry of pin locations 01 ampliliers A and B.
• Also available with MIL-STD-883S processing. To order add/883 as a suffix to
the part number.
t All listed parts are available with 160 hour burn-in. See Ordering Information,
Section 2.
SIMPLIFIED SCHEMATIC (Va OP-227)
OUTPUT
NON
INVERTING
INPUT!o.+)'-+-+--~'-+----l:..
INVERTING
INPUT (-)
~~~-1~------~--------~
L - - -_ _ _ _ _-4_ _
~----~
PAGE 5-171
_ _ _ _-4__
~~~-+~v_
I
OP-227 ULTRA-LOW NOISE, LOW OFFSET DUAL INSTRUMENTATION OP AMP
ABSOLUTE MAXIMUM RATINGS
Supply Voltage ..............•.................... ±22V
Internal Power Dissipation (Note 1) •....••....••• 500mW
Input Voltage (Note 3) .••.••..•.•.•..••••..••...•. ±22V
Output Short Circuit Duration ..........•••.... Indefinite
Differential Input Voltage (Note 2) ••...•••..••••..• ±0.7V
Differential Input Current (Note 2) .••..•.....••.• ±25mA
Storage Temperature Range ...•....•••• -65· C to +150· C
Operating Temperature Range
OP-227A, OP-227B, OP-227C ....•... -55·C to +125·C
OP-227E, OP-227F, OP-227G .......... -25·C to +85·C
Lead Temperature Range (Soldering, 60 sec) .....• 300·C
NOTES:
1. See table for maximum ambient temperature rating and derating factor.
Package
Temperature lor Rating
Derate Abo.e Maximum
Ambient Temperature
14-Pin (V)
106'C
11.3mW/·C
Maximum Ambient
2. The OP-227's inputs are protected by back-to-back diodes. Current
limiting resistors are not used in order to achieve low noise. If differential
input voltage exceeds ±0.7V, the input current should be limited to 25mA.
3.
For supply voltages less than ±22V, the absolute maximum input voltage is
equal to the supply voltage.
INDIVIDUAL AMPLIFIER CHARACTERISTICS at Vs = ±15V, T A = 25· C, unless otherwise noted.
OP-227A1E
TYP
MAX
{Note II
20
TVP
MAX
UNITS
so
40
120
80
180
pV
(Note 21
0.2
1.0
0.3
1.5
0.4
2.0
pVlMo
50
12
75
nA
±IO
±40
±12
±55
±15
±80
nA
O.OS
0.20
0.08
0.20
0.09
0.2S
pVp-p
6.0
4.7
3.9
3.5
3.1
3.0
6.0
4.7
3.9
3.S
3.3
3.2
9.0
5.9
4.6
nVly'Hz
'0'" 1000Hz (Note 3)
3.5
3.1
3.0
'0= 10Hz (Note 3, 61
'0= 30Hz (Note 3,61
'0 = 1000Hz (Note 3, 61
1.7
1.0
0.4
4.5
2.5
0.7
1.7
1.0
0.4
4.5
2.5
0.7
1.7
1.0
0.4
0.7
CONDITIONS
Input Offset Voltage
Vos
Long Term Vas
Stability
VOg/Time
Input Offset Current
lOS
Input Bias Current
I.
35
0.1 Hz to 10Hz
Input Noise Voltage
MIN
OP-227C/G
MAX
SYMBOL
MIN
OP-227B/F
TVP
PARAMETER
MIN
(Note 3, 5)
Input Noise
Voltage Density
Input Noise
Current Density
en
in
Input Resistance -
(Note 41
Differential Mode
Input Resistance Common Mode
Input Voltage Range
Common Mode
Rejection Ratio
Power Supply
Rejection Ratio
'0 = 10Hz (Note 31
to == 30Hz (Note 3)
PSSR
RL~600n,vo=±lV
Vs = ±4V (Note 4)
Output Voltage Swing
Slew Rate
SR
GBW
Power Consumption
Offset Adjustment
Range
MO
(Note 41
GO
±12.3
±11.0
±12.3
±11.0
±12.3
v
114
126
106
123
100
120
dB
1000
SOO
IS00
1500
1000
SOO
1800
1500
700
1500
1500
250
700
250
700
200
500
±12.0
±13.S
±12.0
±13.8
±10.0
±11.5
±10.0
±11.5
±11.5
±10.0
±13.5
±11.5
1.7
2.S
1.7
2.S
1.7
2.S
VIpS
5.0
B.O
5.0
8.0
5.0
S.O
MHz
10
VO=O,IO=O
70
Each Amplifier
90
10
70
140
90
±4.0
±4.0
Rp= 10kO
NOTES:
1. Input Offset Voltage measurements are performed by automated test
equipment approximately 0.5 seconds after application of power. AlE
Grades Guaranteed Fully Warmed up.
2.
4
±11.0
Vs::: ±4V to ±18V
RL;;::2kO, Vo- ±10V
R L ;:::lkO,V O =±10V
Gain Bandwidth Prod.
O.B
2.5
CMRR
Voltage Gain
Resistance
1.2
R1NCM
IVR
Large Signal
Open Loop Output
1.5
pAly'Hz
20
pVN
VimV
v
o
70
140
100
170
±4.0
mW
mV
Excluding the initial hour of operation, changes in Vas during the first
3.
Long Term Input Offset Voltage Stability refers to the average trend line
of Vas vs. Time over extended periods after the first 30 days of operation.
30 days are typically 2.5"V - refer to typical per'ormance curve.
Sample tested.
4. Parameter is guaranteed by design.
5. See test circuit and frequency response curve for 0.1 Hz to 10Hz tester.
6. See test circuit for current noise measurement.
PAGE 5-172
OP-227 ULTRA-LOW NOISE, LOW OFFSET DUAL INSTRUMENTATION OP AMP
INDIVIDUAL AMPLIFIER CHARACTERISTICS for Vs =
±1511, -55°C:5 T A:5 +125°C,
OP-227A
PARAMETER
SYMBOL
CONDITIONS
Input Offset Voltage
Vas
Average Input
TCVos
TCVOSN
Offset Drift
Input Offset Current
loS
Input Bias Current
I.
Input Voltage Range
IVR
Common Mode
Rejection Ratio
Power Supply
Rejection Ratio
Large Signal
Voltage Gain
Output Voltage Swing
CMRR
OP-227B
TYP
MAX
(Note 1)
eo
(Note 2)
0.3
VCM =±10V
MIN
unless otherwise noted.
MIN
OP-227C
TYP
MAX
MIN
TYP
MAX
UNITS
180
80
270
110
350
~V
1.0
0.4
1.5
0.5
1.8
~VI·C
15
50
22
85
30
135
nA
±20
±60
±28
±95
±35
±150
nA
±10.3
±11.5
±10.3
±11.S
±10.2
±11.5
V
108
122
100
119
94
116
dB
•
.
N
~
PSRR
VS = ±4.5V to ±18V
Ava
RL2::2kO, V o =±10V
Va
RL 2:'2kO
16
20
~VIV
51
IL
0
!II
600
1200
500
1000
300
800
V
±11.5
±13.5
±11.0
±13.2
±10.5
±13.0
V
a:
1&1
ii:
::i
IL
:2
ct:
....I
INDIVIDUAL AMPLIFIER CHARACTERISTICS for Vs =
±15V, -25° C :5 T A:5 85° C,
ct:
z
unless otherwise noted.
0
Op·227E
PARAMETER
SYMBOL
CONDITIONS
Input Offset Voltage
Vas
Average Input
TCVos
Offset Drift
TCVOSN
I nput Offset Current
los
Input Bias Current
I.
Input Voltage Range
IVR
Common Mode
TYP
MAX
(Note 1)
40
(Note 2)
0.5
CMRR
VCM = ±10V
PSAA
Vs = ±4.5V to ±18V
Large Signal
Voltage Gain
Ava
RL:2!2kO, Vo =±10V
Output Voltage Swing
Va
RL~2kn
Rejection Ratio
Power Supply
Rejection Ratio
NOTES:
1.
OP-227F
Input Offset Voltage measurements are performed by automated test
equipment approximately 0.5 seconds after application of power.
MIN
OP-227G
TYP
MAX
140
60
1.0
0.4
MIN
MIN
TYP
MAX
UNITS
200
85
280
~V
1.5
0.5
1.8
~VI·C
10
50
14
85
20
135
nA
±14
±ao
±18
±95
±25
±150
nA
±10.5
±11.8
±10.5
±11.8
±10.5
±11.8
V
110
124
102
121
96
118
dB
15
16
~VIV
32
750
1500
700
1300
450
1000
V/mV
±11.7
±13.6
±11.4
±13.5
±11.0
±13.3
V
2. The TeVos performance is within the specifications unnulled or when
nulled with Rp = 8kfl to 20kfl, optimum performance is obtained with Rp =
8kO.
PAGE 5-173
~
a:
1&1
IL
0
OP-227 ULTRA-LOW NOISE, LOW OFFSET DUAL INSTRUMENTATION OP AMP
MATCHING CHARACTERISTICS for Vs = ±15V, T A = 25·C, unless otherwise noted.
OP-227A1E
TVP
MAX
UNITS
80
35
150
65
300
pV
±10
±4O
±12
±55
±15
±SO
nA
Non--Invertlng Offset Current
±12
±80
±15
±80
±20
±13O
nA
Inverting Offset Current
±12
±80
±15
±80
±20
±13O
nA
Input Offset Voltage Match
4Vos
CONDITIONS
Average Non-Inverting
Bias Current
Common Mode Rejection
Ratio Match
Power Supply Rejactlon
Ratio Match
Channel Separation
Gain Match
4CMRR
4PSRR
VS =±4Vto±18V
cs
(Note 1)
tJ.AYQ
MAX
25
110
123
126
154
MIN
103
120
126
154
10
1.= 100 KHz (Note I)·
RL2: 2kn. Vo ""
TVP
OP-227C/G
MAX
SYMBOL
MIN
OP-227B1F
TVP
PARAMETER
1.5
± 10V
MIN
97
117
126
154
dB
10
8.0
1.5
20
6.0
dB
9.0
2.0
MATCHING CHARACTERISTICS at VS = ±15V, T A =~5· C to +125· C, unless otherwise noted.
OP-227B
OP-227A
PARAMETER
SYMBOL
Inpul Offsel yollage Malch
4Vos
Input Offset Voltage
Tracking
TC4Vos
CONDITIONS
MIN
Nulled or
Unnulled (Note 2)
Average Non-Inverting
Bias Current
Average Drift 01 Non-
Non-Inverting Offset Current
los+
Inverting Offset Current
Ratio Match
Ratio Match
MAX
UNITS
75
300
100
480
pV
0.3
1.0
0.4
1.5
0.5
1.8
pVfOC
±20
±80
±28
±95
±35
±170
MIN
±25
4CMRR
4PSRR
105
±35
±90
±14O
±45
±35
±90
97
114
±45
90
3
16
±250
nA
pArC
250
±14O
nA
pArC
200
200
118
Vs = ±4.5V to ±18V
MIN
180
130
Inverting Offset Current
Power Supply Rejection
TVP
180
55
±25
Average Drift 01 Non-
Common Mode Rejactlon
MAX
MAX
100
Inverting Bias Current
OP-227C
TVP
TVP
±250
110
nA
dB
20
51
pVN
MATCHING CHARACTERISTICS for Vs = ±15V, T A = -25·C to +85·C, unless otherwise noted.
OP-227E
OP-227F
OP-227G
_PAR
__A_M_ET
__E_R__________SY
__
M_B_O_L____C_O_N_D_IT_IO_N_S
__________M_I_N__TV
__P__M_A_X______M_I_N___
TV_P___
MAX
________
M_IN___TV
__
P__M_AX
_____ UNrrS
Input Offset Voltage Match
Input Offset Voltage
Tracking
TC4VOS
Nulled or
Unnulled (Nole I)
Average Non-Inverting
Bias Current
Average Drift 01 NonlOS+
Inverting Offset Current
Ratio Match
Rallo Malch
210
90
400
pV
0.3
1.0
0.4
1.5
0.5
1.8
pVfOC
±14
±80
±18
±95
±25
±170
nA
±14O
±35
140
±25
±90
±20
4CMRR
VCM= ±1OV
4PSRR
Vs = ±4.5V to ±18V
108
98
15
NOTES:
1. Sample lesled.
2. Guaranteed by design.
PAGE.6-174
±25
±90
120
pArC
180
200
130
Inverting Offset Current
Power Supply Rejection
65
±20
Average Drift of Non-
Common Mode Rejection
140
80
Inverting Bias Current
Non-Inverting Offset Current
40
±250
pArC
250
±35
±14O
117
90
16
nA
±250
nA
dB
112
32
pVN
OP-227 ULTRA-LOW NOISE, LOW OFFSET DUAL INSTRUMENTATION OP AMP
TYPICAL PERFORMANCE CURVES
0.1 Hz TO 10 Hz NOISE TEST CIRCUIT
0.1 HZ TO 10 HZ pop NOISE CIRCUIT SCHEMATIC
O.1,11F
120
BACK·TO·BACK
~
ill
47\
10n
80
40
~
w
~-40
g -SO
II
-120
O.1Hz TO 10Hz PEAK-TO-PEAK NOISE
NOTE: OBSERVATION TIME MUST BE LIMITED TO 10 SECONDS
TO INSURE 0.1 Hz CUTOFF.
II)
lie
III
ii:
::::i
A-
COMPARISON OF OP-AMP
VOLTAGE NOISE SPECTRUMS
VOLTAGE NOISE
vsFREQUENCY
100
1-'"
,
:>
"ill
,
oz
llfCORNER
1/fCORNER
2.7Hz
J
~~
1111111
INSTRUMENTATION
RANGE, TO DC
111111
1000
10
100
FREQUENCY (Hz)
0.0 1
0.1
10.0
_
,.<'"
~
~
w
~
i 1°1~;!!!!!!!1I"1l"!!!l!!!I
1.0
."'
[en0 2 - (130nVj2j ~
lMn x 100
a:
a:
1lfCORNER
r--- 1-=
-50
-25
0
25
50
75
TEMPERATURE reI
PAGES-17S
100
125
140Hz
11111111
o. 1
10k
in =
I"-
a
AT 1kHz
,.
,+
":" 500kr.!
~
r- AT 10H,
SOURCE RESISTANCE (U)
10kH
500kn
I---+-+-H-++ttt-- RS = 2Al
100
100
CURRENT NOISE
vs FREQUENCY
w
5
10
BANDWIDTH (kHz)
100F=!=R=R"FFFF====="R
=TA=25'C
~
1-__v_Sj-=_±-t'5_Vt++++++-_ ~
~
1.0
VOLTAGE NOISE
vs TEMPERATURE
TOTAL NOISE vs
SOURCE RESISTANCE
==
./
II
1
FREQUENCY (Hz)
III
A-
o
~ 0, 1
AUDIO RANGE'
TO 20kHz
C
Z
~lie
1
g
1/fCORNER
-
2"C
+15V
~
AUDIO
OP AMP
~OP227
TA
Vs
w
LOW NOISE
0
~
...I
o
10
741
.......
'~'--~~~'~0~~~~'00~~~~'000~
INPUT WIDEBAND
NOISE vs BANDWIDTH
(O.1Hz TO FREQUENCY INDICATED)
10
I
100
lk
FREQUENCY (Hz)
10k
OP-227 ULTRA-LOW NOISE, LOW OFFSET DUAL INSTRUMENTATION OP AMP
TYPICAL PERFORMANCE CURVES
OFFSET VOLTAGE DRIFT
OF REPRESENTATIVE UNITS
SUPPLY CURRENT
vs SUPPLY VOLTAGE
10
o±c
I~
100
80
V
fA' +25'e,
'--fA;~
,.
v::
f..- f:\:: ~ ~
~~V
w
~
'~"
--
20
g
0
-t-
['.
-20
>
-40
~
~
25
~
$
~
V
~
~ 25
I~V
V
g
w
'"
~ 20
OP22~C/G
it'"
15
w
\0
;;;
OP-227A/E
~~
V
g
t--+t-t-
5
t-t0
0
0
1\ 0
t--..
-25
0
25
-4
V~'~15)-
~
t-
I I
lJ
o
1
2
3
4
5
6
7
8
9
10 11 12
60
U.Ll
II
RESPONSE
1,!lI OP-227C
BA'
1\
zo
IA I
1\
I' I' 1'1"-
I
t'-
10
I"-
~ DEVICE IMMERSED
~
OP-2278
I4.J .1
OP-227A
IN 7rPC OIL BATH
0
50
80
-50
100
-25
0
25
JJJ
50
75 100
125
150
TEMPERATURE 1°C)
SLEW RATE, GAIN- BANDWIDTH
PRODUCT, PHASE MARGI.N vs TEMP.
O~"M
VS=±15V-
r-GBW
'\
~
0
4
I'\.
>30
3
r-SLEW
0
'\
OP~Z7A
75
1"- r
111
INPUT BIAS CURRENT
vs TEMPERATURE
~
SHOCK
"
o
OP227B
50
-6
f--'
~
~50
!:;
TEMPERATURE 1°C)
I A'--1"--1---'
~
,.- ~t"'
TIME (MONTHS)
I'...
-I 0
-50
is
r
I-
"'"I-'
0
;;;"0
w
-
-3
\
--
......
~~
I
'"
-I--
~
"-
;; 7 0
OP227C
0
-75
130
'z"
,~ ~ :---...
I
VOLTAGE GAIN
vs FREQUENCY
Jjl\.
~ r'\
0
TIME (SECONDS)
.
II
~
w
25 46 65 85 105 125 145166
~
-20
INPUT OFFSET CURRENT
vs TEMPERATURE
30
t:
-1
rrMA~
t-t-
~
TIME AFTER POWER ON (MINUTES)
0
A JJiO.2pV/M0t::
-2
t- op.k,c
o.2pV~
i
~
1 1
t-t-
5
50
2
TA = 7cPC
TA=
25"C
o
OP221'B/F
--
/
3
i!:
g
I
I I
I I
w
±15V
!Ii;::
OP~227A
i'-
JJ
4
OFFSET VOLTAGE CHANGE
DUE TO THERMAL SHOCK
330
0
"
-100
-75 -56 -35 -15 5
:>
fl ..z..J
=
oP.~7B
'" °TA
~
TEMPERATURE fOCI
WARM-UP DRIFT
o r - Vs
./
V
k L,.-ol-""'i'I
.... t--- g=:~:
.......
j,...- II
-80
~
TOTAL SUPPLY VOLTAGE (VOLTS)
5
./
j,...- ;Xt--.
l"-
-60
ro
5
50
~
~A=-66°C
'"
2
:>
3·
l./
OFFSET VOLTAGE
STABI LITY WITH TIME
100
125
10
100
lk
10k lOOk
FREQUENCY (Hz)
PAGE 5-176
1M
10M 100M
2
-75
-50 -25
0
25
50
TEMPERATURE
fe)
76
100
125
OP-227 ULTRA-LOW NOISE, LOW OFFSET DUAL INSTRUMENTATION OP AMP
TYPICAL PERFORMANCE CURVES
25
20
15
~10
GAIN, PHASE SHIFT
vs FREQUENCY
~Ll
f\.
r\
Z
~
T~ J2~~1
i'-kl
5
Vs = ±15V
"i'-..
2.
;;
~
z
;;
1.
160
§,.
180
iii
IS
16
Y
:r-J25 C
/
5
o
/'
0
5
I POJmJe
14
RL=lkU
~i-"""
-
12
....N
//
V
'1'
IL
0
TA = 25°C
I-220
100
II
NEGATIVE
SWING
200
10
r;--
SWING
10
~V
IV
"
o.
i\
-10
100
OUTPUT SWING
vs RESISTIVE LOAD
,.
2.
Rl = 2kU
140
\
\
-5
80
120
f\
PHASE
M~~~,IN
OPEN-LOOP GAIN
vs SUPPLY VOLTAGE
10
20
30
40
50
a:
I III
-2
0.0
FREQUENCY (MHz)
II)
Vs = ±15V
TOTAL SUPPLY VOLTAGE (VOLTS)
III
10
1.0
0.1
LOAD RESISTANCE (kH!
ii:
::;
IL
:IE
c
....
c
z
SMALL SIGNAL OVERSHOOT
vs CAPACITIVE LOAD
MAXIMUM UNDISTORTED
OUTPUTvsFREQUENCY
2.
11~~Uoil
Vs
=
100
60
0
50
./
\
20
.....
10k
lOOk
1M
FREQUENCY (Hz)
/
/
TA = +250
Vs = ±15V
K.llATION
0"
L
40
1k
~
a:
III
IL
0
±15V
0
o
0
SHORT CIRCUIT
CURRENT vs TIME
0
r-'S'j"'
~ ......
'SC(+)
Vs '" ±1SV
VIN = 100mV-
(V' +1,
0
10
500
10M
1000
1500
2000
o
2500
CAPACITIVE LOAD (pFI
SMALL SIGNAL
TRANSIENT RESPONSE
TIME FROM OUTPUT SHORTED
TO GROUND (MINUTES)
MATCHING CHARACTERISTIC
CMRR MATCH V8 FREQUENCY
LARGE SIGNAL
TRANSIENT RESPONSE
140
+5V
+5V
120
ov
OV
100
-5V
-5V
f\..
80
AVCL = +1, CL '" 15pF
AVCL = +1
VS =±15V
VS =±15V
TA=25°C
TA =25°C
104
1(,5
FREQUENCY (Hz)
PAGE 5-177
lOS
107
OP-227 ULTRA-LOW NOISE, LOW OFFSET DUAL INSTRUMENTATION OP AMP
TYPICAL PERFORMANCE CURVES
OPEN-LOOP VOLTAGE GAIN
vs LOAD RESISTANCE
COMMON-MODE INPUT RANGE
vs SUPPLY VOLTAGE
16r-----r-----,-----.-~~,
12
1------1---
::: r-- ~.I = 12~~IIt-+++++tItt--t-+t-I-tHti
2.0 r- Vs = ±15V",t--t-tl*l+IIt--+-H",iII
1.8 f--+--+-++!+!H--.f.~+++++H+-+++++H+l
1.6 1--H-t+ttttlIH/-H+tHtI-++-+++ttH
1.41--+-1-H+IIIt-+++J.+!jiH-++++H1l1
1.2 1-+-1-Hfflt-+++J.+!j!H--++++ttttl
1.0 1--+-1-+l1-H1t-+++J.+!jiH-++++H1l1
0.8 1--+-1-t1+fjjt-+++J.+!jiH--++++ttttl
0.6
-16'-____' -____-'-____,-'--____-'
±5
±10
t15
SUPPLY VOLTAGE (VOLTS)
±20
100
;;
.3
:J:
,.~
.............
t-....
40
~
20
-20
-40
0
~
,/
-60
r-....
:::::,..,
r- ......
~
>
V
100
~0
80
"a:a:
60
a:
a:
z
if
........
10
-35 -15
dp-227A
120
104
\
\
MATCHING CHARACTERISTIC;
CMRR MATCH vs TEMPERATURE
125
103
\OP-227C
'OP-227C
OP-2277::'
1
-120
-75 -55 -35 -16
102
MATCHING CHARACTERISTIC;
AVERAGE OFFSET
CURRENT vs TEMPERATURE
(INVERTING OR NON-INVERTING)
'\OP-227C
-100
10
50
10
1
1
FREQUENCY (Hz)
MATCHING CHARACTERISTIC;
AVERAGE NON-INVERTING
BIAS CURRENT vs TEMPERATURE
OP-~7C
L-" roc r~
j
I-+-1LH-ttt1+-+++t+t1Itt--++t+Httl
OP-227A
>< r- r-....
V
~ -<10
l- I- r- O'-f
.......
V'"
~
....
120
40
I
I'"
60
140
LOAD RESISTANCE (kHl
MATCHING CHARACTERISTIC;
DRIFT OF OFFSET VOLTAGE MATCH
OF REPRESENTITIVE UNITS
80
PSRR AND
~
:izi!
o
~
a:
0.1
0
0.0 1
0.1
11
111111
1.0
10
FREQUENCY (Hz)
PAGE 5-187
100
II
1000
OP-421
PMI
HIGH SPEED QUAD
LOW POWER
OPERATIONAL AMPLIFIER
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
ORDERING INFORMATIONt
Wide Bandwidth ........................... 1MHz
Low Supply Current •••.••.•••••••••••••.••• 600/LA
Slew Rate •••••••.•••••••••••••••••••••.•• O.5V//Ls
Single Supply Operation •••.••••••••••• +3V to +30V
Low Input Offset Voltage .................... 500/LV
Low Input Offset Voltage Drift ............... 5/LV/oC
High Common Mode Input Range. • .• V- to V+ (-1.5V)
High CMRR ••••.••••••••••••••••••••••••.• 100dB
High Open Loop Gain •••••••••••••••••.•• 400V/mV
±30V Input Overvoltage Protection
No External Components Required • • • . • •• Easy to Use
Single Chip Monolithic Construction
Pin Compatible With LM124, LM148 and OP·11
TA;25°C
VOSMAX
(mV)
HERMETIC
DIP
14-PIN
2.5
2.5
4
4
6
OP421 BY'
OP421FY
OP421CY'
OP421GY
OP421HY
OPERATING
TEMPERATURE
RANGE
MIL
INO
MIL
INO
COM
'Also available with MIL-STD-883B processing. To order add /883 as a suffix to
the part number.
t All listed parts are available wi~h 160 hour burn-in. See Ordering Information,
Section 2.
PIN CONNECTIONS
GENERAL DESCRIPTION
The OP·421 Quad Low·Power Operational Amplifier is a
single-chip quad op amp patterned after the OP-21 HighSpeed Precision Low-Power single Operational Amplifier.
The PNP input stage allows the input common mode voltage
to include V-. Combined with a low'power supply current
(150/LA/section at 5V), the OP-421 offers a unique solution
for designs requiring high function density, wide bandwidth
and low-power operation. Examples of applications ideally
suited to use of the OP·421 would include low-power active
filters, battery-operated remote line filters, signal preconditioning amplifiers, and a variety of multiple gain block arrays.
In addition, the ever present problem of crossover distortion
in low-power devices is eliminated by a unique double buffered output section.
14-PIN
HERMETIC DIP
(Y·SUFFIX)
SIMPLIFIED SCHEMATIC (1/4 Shown)
v+
-IN
+IN
0---+---+---+----+----'
PAGES-1SS
OP-421 HIGH-SPEED QUAD LOW-POWER OPERATIONAL AMPLIFIER
ABSOLUTE MAXIMUM RATINGS (Note 2)
Supply Voltage ............................... ±18V
Internal Power Dissipation (Note 1) ......•......•• 500mW
Differential Input Voltage ...................... ±30V
Input Voltage ......................... Supply voltage
Output Short Circuit Duration .............. Continuous
(One Amplifier Only)
Storage Temperature Range ......... -65·Cto +150°C
Lead Temperature Range (Soldering, 60 sec) ...... 300°C
Operating Temperature Range
OP-421 BY, OP-421 CY ............... -55°C to +125°C
OP-421 FY, OP-421 GY . . . . .. . . . . . . . ... -25° C to +85° C
OP-421HY
O°C to +70°C
.............................
DICE Junction Temperature
.............
-65°C to +150°C
NOTES:
1. See table for maximum ambient temperature rating and derating factor.
MAXIMUM AMBIENT
TEMPERATURE
FOR RATING
14-Pin Hermetic DIP (VI
DERATE ABOVE
MAXIMUM AMBIENT
TEMPERATURE
l00·C
10mW/·C
2. Absolute maximum ratings apply to both packaged parts and DICE, unless
otherwise noted.
II
.,.
N
a.
0
ELECTRICAL CHARACTERISTICS at Vs
=
± 15V, TA +
25°C, unless otherwise noted.
0
a::
OP-421B
OP-421F
PARAMETER
SYMBOL CONDITIONS
Input Offset Voltage
Vos
Input Offset Current
Input Bias Current
0.5
2.5
'OS
Vs =: ±2.SV to ±15V
0.6
5.0
2.0
10
5.0
20
nA
-C
'B
Vs = ±2.5V to ±15V
20
50
50
eo
100
150
nA
0
fo= 10Hz (Note 1)
20
40
20
40
20
40
fo = 100Hz (Note 1)
15
30
15
30
15
30
0.3
0.6
0.3
0.6
0.3
0.6
0.4
0.2
004
0.2
Input Noise Current
Density
Input Voltage Range
fa
in
,VR
= 10Hz (Note 1)
Rejection Ratio
V+=+SV. V-""OV.
OV:S: VCM:S: + 3.5V
CMRR
Vs
= ± 15V.
- 15V:s: VCM:S: + 13.5V
Power Supply
Rejection Ratio
PSRR
Vs = ± 2.5V to ± 15V; and
v- = OV, V + = 5V to 30V
AVO
RL"" 10kO
-15
V+=5V,V-=OV
Output
Vo
Voltage Swing
RL"" 10kn
Closed Loop
Bandwidth (Note 2)
Supply Current
BW
AVCL"" +1.0,
RL
'sv
=10kn
3.5
MAX
-15
13.5
0.4
3.5
-15
eo
98
78
90
83
100
eo
98
76
90
nVl.,fHz
10
200
20
30
100
400
50
200
30
100
eo
200
4.0
0.8
3.9
0.9
3.8
-14
+14
-13.9
+13.9
-13.8
+13.8
V
.VN
V
1.0
1.9
1.0
1.9
1.0
1.9
MHz
0.6
1.0
0.7
1.5
0.9
2.0
=±15V, no load
1.2
1.B
1.4
2.3
1.B
3.0
mA
SlewAate
SR
(Notel)
0.25
0.5
0.25
0.5
0.25
0.5
Vlid
Channel Separation
CS
(Note 1)
100
120
100
120
100
120
dB
NOTE:
1. Sample tested,
2. Guaranteed by design.
PAGE 5-189
C
Z
5a::
III
VlmV
0.7
=e
....
a.
pAl.,fHz
dB
V S = ±2.5V. no load
Vs
UNITS
13.5
100
Rl"" 5kO
VS=±15V,
TYP
83
Large Signal
Voltage Gain
13.5
MIN
mV
3.5
V+=+5V. V-=OV
VS= ±15V
Common Mode
0.2
fo = 100Hz (Note 1)
MAX
:::;
a.
Vs = ±2.SV to ±15V
en
TYP
iO:
MAX
MIN
MIN
III
OP-421H
TYP
Input Noise Voltage
Density
OP-421C
OP-421G
0
OP-421 HIGH-SPEED QUAD LOW-POWER OPERATIONAL AMPLIFIER
ELECTRICAL CHARACTERISTICS at Vs=±15V.-55·CS T AS+125· Cfor OP-421 Band OP-421C.-25·CST AS +85· C
for OP-421 F and OP-421 G. and O· CST AS +70· C for OP-421 H. unless otherwise noted.
OP-421B
OP-421F
PARAMETER
Average Input Offse.
Voltage"Drlft (Note 1)
SYMBOL CONDITIONS
MIN
TYP
Vos
VS=±2.5Vto ±15V
Input Off8et Current
lOS
Vs
=±2.5V to ±15V
1.6
Input Bias Current
18
VS:::: ±2.SV to ±15V
25
Input Voltage Range
IVR
Rejection Ratio
Power Supply
Rejection Ratio
CMRR
Voltage Gain
-15
VS:m±15V
V + == + 5V, V-:::: OV.
OV S VCM :::; + 3,5V
- 15V:S VCM:5
+ 13.SV
Vs = ± 2.SV to
± 15V; and
AvO
Rl =20kO
Rl = 10kO
5.5
3.0
15
60
12.
10
13.5
15
UNITS
p,V/·C
7.5
mV
6.0
30
nA
140
230
nA
3.5
-15
MAX
3.5
-15
13.5
74
94
73
86
78
96
74
94
73
88
V
15
50
2.
80
40
100
1.
50
25
60
40
100
200
50
100
50
100
.VlV
VlmV
0.8
3.9
0.9
3.8
1.0
3.7
-13.8
+13.8
-13.7
+13.7
-13.7
+13.7
V
VS=±15V,
Vs
Isy
1.8
TYP
96
Rl =20kO
Supply Current
MIN
78
100
V+ = 5V. V- = OV
Voltage Swing
MAX
15
70
13.5
OP-421H
dB
± 15V,
v- = ov, V + = 5V to 30V
Vo
TVP
3.5
PSRR
Output
MIN
3.6
V+=+5V, V-=OV
Vs::::
Large Signal
MAX
10
TCVOS
Input Offset Voltage
Common Mod.
OP-421C
OP-421G
=±2.SV, no load
VS:::: ±15V, no load
0.68
1.2
1.5
2.0
2.5
NOTE:
1. Sample tested.
BURN-IN CIRCUIT
-18V
GNO
.. 18V
PAGE 5-190
0.88
1.5
2.0
2.5
3.2
0.68
2.0
3.0
3.2
4.0
mA
OP-421 HIGH-SPEED QUAD LOW-POWER OPERATIONAL AMPLIFIER
DICE CHARACTERISITICS
1. OUTPUT 1
2. INVERTING INPUT 1
3. NON-INVERTING INPUT 1
4. V+
•
5. NON-INVERTING INPUT 2
6. INVERTING INPUT 2
7. OUTPUT 2
8. OUTPUT 3
9. INVERTING INPUT 3
10. NON-INVERTING INPUT 3
11. V12. NON-INVERTING INPUT 4
13. INVERTING INPUT 4
14. OUTPUT4
zo
II)
II:
Refer to Section 2 for additional DICE informalton.
III
DIE SIZE 0.086 x 0.062 Inch
ii:
::i
A-
~
~
Z
ELECTRICAL CHARACTERISTICS at Vs
=
o
± 15V. TA = + 25°C. unless otherwise noted.
~
II:
OP-421N
OP-421G
OP-421GR
LIMIT
LIMIT
LIMIT
UNITS
20
mVMAX
PARAMETER
SYMBOL
CONDITIONS
Input Offset Voltage
Vas
V s = +2.5V to ±15V
2.5
Input Offset Current
los
V s = ±2.5V to ±15V
5.0
10
150
nAMAX
Input Bias Current
18
Vs = ±2.5V to ±15V
50
80
150
nAMAX
Input Voltage Range
IVR
-15/+13.5
-15/+13.5
-15/+13.5
VMIN
83
80
76
dBMIN
30
50
80
p.VlV MAX
0.7/4.0
± 14
0.8/3.9
± 13.9
0.9/3.8
±13.8
V MIN
1.0
1.8
1.5
2.3
2.0
3.0
mAMAX
Common Mode
Rejection Ratio
CMRR
V + = + 5V. V- = OV.
OV" VCM " + 3.5V
Vs=± 15V.
- 15V:5 VCM:5
Vs
+ 13.5V
= ± 2.SV to ± 15V; and
Power Supply
Rejection Ratio
PSRR
V- = OV. V + = 5V to 30V
Output Voltage Swing
Va
V+ = +5V. V- = OV. RL = 5kn
Vs = ±15V. RL = 10kn
Supply Current
Isv
Vs = ± 2.5V. No Load
Vs= ± 15V. No Load
TYPICAL ELECTRICAL CHARACTERISTICS at Vs
PARAMETER
= ± 15V. TA + 25°C. unless otherwise noted.
OP-421N
OP-421G
OP-421GR
TYPICAL
TYPICAL
TYPICAL
UNITS
20
15
20
15
20
15
nv;'iHZ
1.9
1.9
MHz
0.5
0.5
VII'S
120
dB
SYMBOL
CONDITIONS
Input Noise Voltage
Density
en
fo= 10Hz
fo= 100Hz
Closed Loop
Bandwidth
BW
AVCL = +1.0
RL = 10kn
1.9
Slew Rate
SR
0.5
Channel Separation
CS
120
120
PAGE 5-191
III
A-
o
OP-421 HIGH-SPEED, QUAD LOW-POWER OPERATIONAL AMPLIFIER
TYPICAL PERFORMANCE CURVES
OPEN LOOP
FREQUENCY RESPONSE
120
w
~
>
"\
80
iii
:s
'\
60
20
IIIII
40
'\
20
"-
"'"
~
100
lk
10k
RL
2k"
1\
100
\
10
RL = 20kn
120
z
'\
1.0
OUTPUT SWING
VB FREQUENCY
VS'"±15V
z
"'"'"
OPEN LOOP GAIN
POWER SUPPLY VOLTAGE
140
r-,
100
~
VB
~
80
100k
1M
10M
10
FREQUENCY (Hz)
20
1k
JO
10k
100k
1M
FREQUENCY (Hz)
TOTAL SUPPLY VOLTAGE (VOLTS)
SUPPLY CURRENT VB
SUPPLY VOLTAGE
GAIN BANDWIDTH VB
SUPPLY VOLTAGE
2.6
2.4
12r-----+------r--~~
ii
¥
! 2.2
"
G
~ 2.0
~
"
~
~ 1 1----''-:::;;1.'''''''''-=--+=,..._9
Z 1.B
iii
~
1.6
",
~
---
.- t -
V
1.4
10
100
lk
10k
lOOk
LOAD RESISTANG,E (.0)
10
1M
20
30
±2.5
TOTAL SUPPL V VOLTAGE (VOLTS)
i5
±7.5
POWER SUPPLY REJECTION
RATIO VB FREQUENCY
COMMON MODE REJECTION
RATIO VB FREQUENCY
120
POSITIVE SUPPLY
120
I'
iii
:s
""
If
80 ~+H~-Himl-H
60
I-rtHlIffiI---+HtlIIHI-+1
20
H-++IHIIf--HHHtIll-H
t~
10
100
1k
10k
100k
O.lK
FREQUENCY 1Hz)
1k
10k
FREQUENCV (Hz)
PAGE 5-192
±10
±12.5
SUPPLY VOLTAGE (VOL TSI
100k
1M
±15
OP-421 HIGH-SPEED QUAD LOW-POWER OPERATIONAL AMPLIFIER
TYPICAL PERFORMANCE CURVES
VOLTAGE FOLLOWER
LARGE-SIGNAL RESPONSE
VOLTAGE FOLLOWER
SMALL-SIGNAL RESPONSE
OUTPUT
OUTPUT
50mV/OIV
2}.!siOIV
1 VOLT/DIV
5~s/DIV
INPUT
INPUT
II
N
'f
A.
o
RL = 10kn
TA = 2SoC
UI
a:
w
CL = 50pf
Vs'" OV, +15V
RL = 10kn
TA '" 2SoC
Vs = OV, +15V
G:
::::i
A.
~
oC
....I
oC
Z
o
~
a:
NOISE CHARACTERISTICS
w
A.
INPUT NOISE VOLTAGE
DENSITY vs FREQUENCY
o
INPUT NOISE CURRENT
DENSITY vs FREQUENCY
1000
10
r--..
"-
--
"
0.01
0.1
1.0
0.1
'" "
"-
I
10
100
lk
10k
FREQUENCY (Hz)
PAGE 5-193
10
100
FREQUENCY (Hzl
lk
10k
PM 108A/PM2108A
PMI
LOW INPUT CURRENT
OPERATIONAL AMPLIFIERS
®
PM 108A/PM208A/PM308A/PM l08/PM208/PM308
PM2108A/PM2108/PM2208A/PM2208/PM2308A/PM2308
FEATURES
•
•
•
•
•
•
•
•
•
•
Low Offset Current ........................ 200pA Max
Low Bias Current ..................... 2.0nA Maximum
Low Power Consumption ..... 18mW Maximum @±15V
Wide Supply Range. . . . . . . . . . . . .. . . . . . . .. ± 3V to ± 20V
High Power Supply Rejection Ratio ..... 96dB Minimum
Low Offset Voltage Drift ........... 5.0"V/oC Maximum
High Common Mode Input Range .... ±13.5V Minimum
High Common Mode Rejection Ratio ... 96dB Minimum
MIL-STD-883 Class B Processing Models Available
Silicon-Nitride Passivation
GENERAL DESCRIPTION
The PM108A Series of precision monolithic operational amp·
lifiers features extremely low input offset and bias currents.
Although directly interchangeable with industry-standard
types, Precision Monolithics' advanced processing technique provides a significant improvement in input noise
voltage. Low supply current drain over a wide power supply
range makes the PM108A attractive in battery operated and
other low power applications: Low offset current and low
bias current provide excellent performance with piezoelectric and capacitive transducers and in high impedance
circuits such as long period integrators and sample-andholds. For improved performance see OP-08, OP-12, OP-20
and OP-21.
The PM2108A series contains two superbeta, PM108A op
amps in a Single 16-pin DIP. Models are provided for
-55° /+125° C, -25° C/+85 ° C and 0° C/+70° C operation in low
power applications. Compared to the single PM108A types,
these models offer higher packaging density, closer thermal
tracking between the two amplifiers, and reduced insertion
cost. For improved performance see OP-220.
PIN CONNECTIONS
EPOXY B MINI-DIP
(P-SUFFIX)
AND
8-PIN HERMETIC DIP
(Z-Suffix)
ORDERING INFORMATIONt
PACKAGE
HERMETIC
T. - 25°C
vos MAX
(mV)
TO-99
a-PIN
a-PIN
0.5
0.5
0.5
2.0
2.0
7.5
PM108AJ'
PM208AJ
PM308AJ
PM108J'
PM208J
PM308J
PM108AZ'
PM208AZ
PM308AZ
PM108Z'
PM208Z
PM308Z
DIP
16-PIN
PLASTIC
OPERATING
TEMPERATURE
DIP
a-PIN
RANGE
PM2108AO'
PM2208AO
PM2308AO PM308AP
PM21080'
PM2208Q
PM23080
PM308P
COMP
OUT
OUT COMP (A)
MIL
INO
COM
MIL
INO
COM
8
COMPS'V'
-IN 2
-
"N 3
•
v* Also avai lable with M I L-STO-8838 processing. To order add/8S3 as a suffix to
the part number.
t All listed parts are available with 160 hour burn-in. See ordering information,
16-PIN HERMETIC DIP
(a-SUFFIX)
Section 2.
SIMPLIFIED SCHEMATIC (Pin numbers for PM108 only. Circuit is 1/2 2108.)
111 COMPENSATION
INPUTS
{{211-~',., ---':=:j::::~=='
'"
PAGE 5-194
6 OUT
5 N.C.
•
(CASE)
TO-99 (J-Suffix)
PM-108A/2108A LOW INPUT CURRENT OPERATIONAL AMPLIFIERS
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
PM108A, PM108, PM208A, PM208,
PM2108A, PM2108, PM2208A, PM2208 •.•..••.• ± 20V
PM308A, PM308, PM2308A, PM2308 •....••...•. ± 18V
Internal Power Dissipation (Note 1) , •••••••••••••• 500mW
Differential Input Current (Note 2) •.••••.••••••••.• ±10mA
Input Voltage (Note 3) .............................. ±15V
Output Short Circuit Duration ••••••.••••.•.•..•. Indefinite
Operating Temperature Range
PM108A, PM108, PM2108,
PM2108A ............................ -55°C to +125°C
PM208A, PM208, PM2208,
PM2208A ............................. -25° C to +85° C
PM308A, PM308, PM2308,
PM2308A ............................... O°C to +70°C
Storage Temperature Range
Lead Temperature Range
(Soldering, 60 sec.) .............................. 300° C
NOTE 1. Maximum package power dissipation vs ambient temperature:
Derate Above Maximum
Maximum Ambient
Temperature for Rating Ambient Temperature
Package Type
TO·gg (J)
BO'C
7.1mW/·C
Plastic B-Pin Dip (P)
36'C
S.6mW/·C
Hermetic B·Pin Dip (Z)
7S'C
6.7mW/·C
100'C
10.0 mW/·C
Hermetic 16-Pin Dip (0)
CD
is provided.
NOTE 3. For supply voltages less than ±15V, the absolute maximum input
voltage is equal to the supply voltage.
(Q-, J-, or Z-Package) •••.•.•.•..•. -65°C to + 150°C
(P-Package)
•
c(
Note 2. The inputs are shunted with back-la-back diodes for overvoltage
protection. Therefore, if a differential input voltage in excess of 1V is applied
between the inputs, excessive current will flow, unless some limiting resistance
o
~
t!!
iII.
1/1
II:
....................... -65°C to + 125°C
W
iL
:::i
ELECTRICAL CHARACTERISTICS
PM108A1PM2108A
PM208A1PM2208A
PARAMETER
SYMBOL
II.
at ±5V:5 VS:5 ±20V and TA = 25°C, unless otherwise noted.
CONDtTIONS
MIN
TYP
MAX
~
...
PM108/PM2108
PM208/PM2208
MIN
TYP
c(
MAX
UNITS
Input Offset Voltage
Vas
0.3
O.S
0.7
2.0
mV
Input Offset Current
lOS
O.OS
0.2
O.OS
0.2
nA
Input Bias Current
18
O.B
2.0
O.B
2.0
nA
Input Resistance
RIN
(Note 1)
30
70
30
70
Mil
Large Signal Voltage Gain
Avo
Vs= ±lSV, VOUT= ±IOV,
RL"IOk!l
80
300
SO
300
VlrroV
S~pply
Isy
lOUT = 0, VOUT - 0, Each amplifer
Current
0.3
0.6
0.3
0.6
mA
ELECTRICAL CHARACTERISTICS at ±5V:5 VS:5 ±20V, -55° C:5 T A :5 + 125° C for PM108A, PM108, PM2108A and PM2108,
-25° C :5 T A :5 +85° C for PM208A, PM208, PM2208A and PM2208, unless otherwise noted.
PM108A1PM2108A
PM208A1PM2208A
PARAMETER
SYMBOL
Input Offset Voltage
Vas
Average Input Offset
Voltage Drift
CONDITIONS
MIN
TYP
MAX
0.4
1.0
PM108/PM2108
PM208/PM2208
MIN
TYP
MAX
UNITS
1.0
3.0
mV
TCVos
1.0
5.0
3.0
15
pV/'C
Input Offset Current
los
0.1
0.4
0.1
0.4
nA
Average Input Offset
Current Drift
TClos
O.S
2.S
O.S
2.S
pA/'C
Input Bias Current
18
1.0
3.0
1.0
3.0
AvO
Vs= ±15V, VOUT= ±10V,
RL"IOk!l
Output Voltage Swing
Vo
Vs = ±15V, RL = 10k!l
Input Voltage Range
IVR
VS=±lSV
Common Mode Rejection Ratio
CMRR
Vs = ± lSV, VCM = ± 13.5V
Supply Voltage Rejection Ratio
PSRR
Vs = ± 5V to ± 20V
Supply Current
ISY
VOUT = 0, TA = MAX, Each amplifier -
Large Signal Voltage Gain
40
200
±13
±14
±13.5
NOTE:
1. Guaranteed by deSign.
PAGE 5-195
96
200
V/mV
±13
±14
V
100
dB
V
±13.5
110
nA
2S
BS
3
15
15
100
INN
0.15
0.4
0.15
0.4
mA
Z
o
~
II:
W
II.
o
PM-108A12108A LOW INPUT CURRENT OPERATIONAL AMPLIFIERS
ELECTRICAL CHARACTERISTICS at ±5V::; VS::; ±15V and TA = 25·C, unless otherwise noted.
PM30SAlPM2308A
PARAMETER
SYMBOL
Input Offset Voltage
Input Offset Current
Input Bias Current
Vos
los
IS
Input Resistance
RIN
Large Signal Voltage Gain
Avo
Supply Current
Isy
CONDITIONS
MIN
TYP MAX
0.3
0.2
0.5
1.0
7.0
(Note 1)
10
1.5
40
Vs= ±15V, VOUT= ±10V,
RL,,10kll
10UT= O. VOUT= O. Each ampHfer
80
300
0.3
PM308/PM230S
MIN
TYP MAX
2.0
7.5
0.2
1.0
7.0
1.5
10
40
25
300
0.3
0.8
UNITS
mV
nA
nA
Mil
VlmV
0.8
mA
ELECTRICAL CHARACTERISTICS at ±5V::; VS::; ± 15V and O· C ::; TA ::; +70· C, unless otherwise noted.
PM30SAlPM2308A
PARAMETER
Input Offset Voltage
Average Input Offset
Voltage Drift
SYMBOL
Input Offset Current
Average Input Offset
Current Drift
Input Bias Current
'MIN
CONDITIONS
PM30S/PM230S
MIN
TYP MAX
3.0 10.0
UNITS
mV
Vos
0.4
0.73
TCVos
1.0
5.0
6.0
30
.VloC
1.5
nA
los
0.3
1.5
0.3
TClos
2.0
10
2.0
10
pAloC
IS
2.0
10
2.0
10
nA
Large Signal Voltage Gain
Avo
Vs= ±15V, VOUT= ±10V,
RL,,10kll
Output Voltage Swing
Input Voltage Range
Vo
IVR
VS= ±15V, RL=10kll
Vs= ±15V
Common Mode Rejection Ratio
CMRR
PSRR
96
VCM =± 13.5V
Vs = ± 5V to ± 15V
VOUT = 0, TA = MAX, Each amplifier
Supply Voltage Rejection Ratio
Supply Current
TYP MAX
Isy
60
200
15
100
VlmV
±13
±14
±13
±14
V
V
±13
±14
110
80
15
0.23
100
15
0.23
dB
100
p.VN
mA
NOTE:
1. Guaranteed by design.
APPLICATION INFORMATION
The PM108A series has extremely low input offset and bias
currents; the user is cautioned that stray printed circuit
board leakages can produce significant errors, especially at
high board temperatures. Careful attention to board layout
and cleaning procedure is required to fully realize the
PM108A's performance. It is suggested that effects of board
leakage be minimized by enCircling the input pins with a
conductive guard ring operated at a potential close to that
of the inputs. This guard ring should be driven by a low impedance source such as the amplifier's output for noninverting circuits, or be tied to ground for inverting circuits.
COMPENSATION CIRCUITS
STANDARD
ALTERNATE
R2
R2
R1
R1
R3
R3
0>-"---......- - 0 OUTPUT
R1
Cf
OUTPUT
CS"'l00pF
;""Fi'1'+R2Co
Co =
,>=---0
30pF
(IMPROVES REJECTION OF POWER SUPPLY NOISE BY A FACTOR Of TEN)
PAGE 5-196
PMI
PM155A, PM156A, PM157A
MONOLITHIC JFET INPUT
OPERATIONAL AMPLIFIERS
®
PM155A/PM355A/PM155/PM255/PM355 LOW SUPPLY CURRENT
PM 156A/PM356A/PM 156/PM256/PM356
PM157A/PM357A/PM157 IPM257 IPM357
WIDE BANDWIDTH DECOMPENSATED (AVMIN = 5) •
FEATURES
GENERAL DESCRIPTION
All Devices
• Internal Compensation
• Low Input Bias and Offset Currents
• Low Input Offset Voltage ................•..... 1.0mV
• Low Input Offset Voltage Drift .............. 3.0JJV/0 C
• Low Input Noise Current ................. O.01pAlJiji
• High Common-Mode Rejection Ratio ... . . . . . . .. 100dB
• Models With MIL-STD-883 Class B Processing
Available From Stock
• 1250C Temperature Tested Dice
(See OP-15, 16,17 Data Sheet)
The PM BIFET Series provides low input current, high slew
rate, and direct interchangeability with LF155, 156, and 157
types. These operational amplifiers use a new process which
allows fabrication of matched JFET transistors and standard
bipolar transistors on the same chip. High accuracy and low
cost make the PM BIFET Series useful in new designs and as
-replacements for modular and hybrid types. Unlike many
designs, nulling the input offset voltage does not degrade
common-mode rejection ratio or input offset voltage drift.
Low input voltage noise and current noise plusa low 1/f noise
corner frequency allow these amplifiers to be used in a variety of low noise, wide bandwidth applications.
•
PM155 (Only) ...•..•.••.......... LF155 Replacement
Low Supply Current ............................. 2mA
•
•
PM156 (Only) .................... LF156 Replacement
High Slew Rate ............................ 12V/JJsec
Fast Settling to ±O.01% ....................... 1.5JJsec
•
•
•
PM157 (Only) .................... LF157 Replacement
Wide Bandwidth (AVCL = 5 Min) ............... 20MHz
Higher Slew Rate .......................... 50v/JJsec
Fast Settling to ±O.01% ....................... 1.5JJsec
Dynamic specifications for the PM155 include a slew rate of
5V1JJs, a 2.5MHz gain bandwidth product, and settling time to
within ±O.01% of final value in 4.0JJs. The PM156 has a slew
rate of 12V/JJs and a settling time of 1.5JJs to ±O.01% of final
value.
The PM157 is a very fast decompensated device. This results
in a 50VlJJs slew rate, a 20MHz gain bandwidth product, and a
settling time of 1.5JJs. Decompensation requires a minimum
closed loop gain of five because of stability considerations.
For improved performance see the OP-15/0P-16/0P-17 data
sheet. For duals see the OP-215 data sheet.
SIMPLIFIED SCHEMATIC
PAGE 5-197
......
~
..~
II>
:I
D-
en
II:
w
u:
:::;
D-
:I
c
...I
C
Z
o
~
II:
W
D-
O
PM155A1PM156A/PM157A MONOLITHIC JFET INPUT OPERATIONAL AMPLIFIERS
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
PM155A, PM156A, PM157A, PM155, PM156, PM157,
PM255, PM256, PM257,
PM355A, PM356A, PM357A ................... ±22V
PM355, PM356, PM357 .......................... ± 18V
Internal Power Dissipation
PM155A, PM156A, PM157A, PM155, PM156,
PM157 ...........................•.•....... 670mW
PM255, PM256, PM257 ........................ 570mW
PM355A, PM356A, PM357 A, PM355, PM356,
PM357 ..................................... 500mW
(Derate based on a thermal resistance of 150° C/W junction to ambient or 45° C/W junction to case.)
Operating Temperature Range
PM155A, PM156A, PM157A, PM155, PM156,
PM157 ........................... -55°C to +125°C
PM255, PM256, PM257 ............... -25°C to +85°C
PM355A, PM356A, PM357 A, PM355, PM356,
PM357 ............................... 0°Cto+70°C
Maximum Junction Temperature (Ti )
PM155A, PM156A, PM157A, PM155, PM156,
PM157 ..................................... +150°C
PM255, PM256, PM257 ........................ +115°C
PM355A, PM356A, PM357 A, PM355, PM356,
PM357 ..................................... +100°C
Differential Input Voltage
PM155A, PM156A, PM157A, PM155, PM156, PM157,
PM255, PM256, PM257, PM355A, PM356A,
PM357A ..................................... ±40V
PM355, PM356, PM357 .......................... ±30V
Input Voltage
PM155A, PM156A, PM157A, PM155, PM156, PM157,
PM255, PM256, PM257, PM355A, PM356A,
PM357A ..................................... ±20V
PM355, PM356, PM357 .......................... ± 16V
(unless otherwise specified the absolute maximum
negative input voltage is equal to the negative power
supply voltage.)
Output Short Circuit Duration ................. Indefinite
Storage Temperature Range ........... -65°C to +150°C
Lead Temperature Range (Soldering, 60 sec.) ... +300°C
ELECTRICAL CHARACTERISTICS at± 15V:5 Vs:5±20V, -55° C :5 TA :5 + 125° C and T HIGH=+ 125° Cfor PM155A, PM156A
and PM157 A, 0° C:5 TA :5 +70° C and THIGH = + 70° C for PM355A, PM356A and PM357 A, unless otherwise noted.
PM155A1
PM156AI
PM157A
PARAMETER
SYMBOL CONDITIONS
TYP
MAX
TYP
MAX
Input Offset Voltage
Vos
Rs~
son
1.4
2.5
1.2
2.3
mV
Input Offset Voltage Drift
TCVos
Rs~
son
3.0
5.0
3.0
5.0
"V/oC
(~TCVos) Rs~ son
0.5
Change jn Input Offset
Drift with Vas Adjust
Input Offset Current
Input Bias Current
Large Signal Voltage Gain
Output Voltage Swing
MIN
PM355A1
PM356A1
PM357A
~Vos
MIN
UNITS
IlV/oC per mV
0.5
los
T j '; THIGH (Note 1)
4.0
10
0.4
1.0
nA
18
T j ,; THIGH (Note 1)
10
25
2.0
5.0
nA
Avo
Vs ~ ±15V. Vo
RL ~ 2kn
~
±10V.
Vo
Vs ~ ±15V. RL
Vs ~ ±15V. RL
~
10kn
2kll
Input Voltage Range
IVR
Vs ~ ±15V
Common Mode Rejection
Ratio
CMRR
V CM
Power Supply Rejection
Ratio
PSRR
(Note 2)
~
25
75
25
75
V/mV
±12
±10
±13
±12
±12
±10
±13
±12
V
+15.1
• ±10.4
-12.0
V
+15.1
±10.4
-12.0
= ±IVR
85
100
10
NOTES:
1. Input bias current is specified for two different conditions The Tj = 25 0 C
specification is with the junction at ambient temperature; the Device Operating specification is with the device operating in a warmed-up condition at
25° C ambient. The warmed-up bias current value is correlated to the
junction temperature value via the curves of Is vs TJand 18 vs TAo PMI has a
2.
PAGE 5-198
85
57
100
10
dB
57
"V/v
bias current compensation circuit which gives improved bias current over
the standard JFET input op amps. Is and los are measured at V eM = O.
Power supply rejection ratio is measured for both supply magnitudes
increasing or decreasing simultaneously, in accordance with common
practice.
PM155A1PM156A/PM157A MONOLITHIC JFET INPUT OPERATIONAL AMPLIFIERS
ELECTRICAL CHARACTERISTICS at ±15V:S VS:S ±20V, TA = 25°C, unless otherwise noted.
PM355AI
PM356A1
PM357A
PM155AI
PM156A1
PM157A
PARAMETER
SYMBOL CONDITIONS
TYP
MAX
TYP
MAX
UNITS
Input Ollset Voltage
Vos
Rs= son
1.0
2.0
1.0
2.0
mV
Input Offset Current
los
T i = 25'C (Note 11
3.0
10
3.0
10
pA
Input Bias Current
I.
Ti = 25'C (Note 11
30
50
30
50
pA
Input Resistance
R'N
large Signal Voltage Gain
Avo
Supply Current
ISY
Vs = ±15V
Slew Rate
SR
AveL = +1, Vs = ±15V
AveL =+5, Vs =±15V
GBW
AveL =+1, Vs =±15V
AveL =+5, Vs =±15V
Settling Time (to±O.OI%1
ts
Vs=±15V(Note21
Vs=±15V(Note31
Rs = lOOn, I = 100Hz
Rs = loon, I = 1000Hz
Input Noise Voltage
en
Rs = lOOn, I = 100Hz
Rs = loon, I = 1000Hz
Input Noise Current
in
Input Capacitance
C 'N
MIN
10 12
Vs = ±15V, Vo = ±10V,
RL = 2kn
Gain Bandwidth Product
MIN
50
2.0
5.0
PM155
PM156/PM157
PM155
PM156
PM157
200
3.0
10
40
5.0
12
50
4.0
15
2.5
4.5
20
50
4.0
7.0
10 12
n
200
V/mV
2.0
5.0
3.0
10
40
5.0
12
50
4.0
15
2.5
4.5
20
4.0
7.0
II
....
mA
VI"s
~
........
...:::E
II>
II>
D.
PM155
PM156
PM157
PM155
PM156
PM157
PM155
PM156/PM157
I = 100Hz, Vs = ±15V
I = 1000Hz, Vs = ±15V
NOTES:
1. Input bias current is specified for two different conditions. The T j = 25° C
specification is with the junction at ambient temperature; the Device Operating specification is with the device operating in a warmed-up condition at
25° C ambient. The warmed-up bias current value is correlated to the
junction temperature value via the curves of lavs Tjand lavs TA- PMI hasa
bias current compensation circuit which gives improved bias current over
the standard JFET input op amps. la and los are measured at V eM = O.
4.0
1.5
1.5
4.0
1.5
25
25
20
20
MHz
W
"s
1.5
15
15
12
12
2. Settling time is defined here for a unity ~ain inverter connection using 2kn
PAGE 5-199
ii:
:J
D.
:::E
C
..J
C
Z
nVlv'Hz
0
~II:
W
D.
0.01
0.01
0.01
0.01
pA/v'Hz
3.0
3.0
pF
resistors. It is the time required for the error voltage (the voltage at the
inverting input pin on the amplifier) to settle to within 0.01% of its final value
from the time a 10V step input is applied to the inverter. See settling time
test circuit.
3.
til
II:
Settling time Is defined hereforaA v =-5 connection with R F =2kO.lt Isthe
time required for the error voltage (the voltage at the inverting input pin on
the amplifier) to settle to within 0.01% of its final value from the time a 2V
step input is applied to the inverter. See settling time test circuit.
0
PM155A/PM158A/PM157A,MONOLITHIC JF!,T INPUT OPERATIONAL AMPLIFIERS
ELECTRICAL CHARACTERISTICS at TA = +25°C, :t15V:S Vs:S ±20V for PM155, PM156, PM157, PM255, PM256 and
PM257, Vs =.±15V for PM355, PM356 and PM357, unless otherwise noted.
PM355/
356/357
PM155/1561157
PM255/256/257
PARAMETER
SYMBOL CONDITIONS
Input Ollset Voltage
Vos
Input Offset Current
lOS
Input Bias Current
MIN
Rs=500
T j = 25'C (Note 1)
Input Resistance
AVO
Vs = ±15V. Vo = ±10V.
RL = 2kO
Supply Current
ISY
Vs =±15V
Slew Rate
SR
AveL =+1. Vs =±15V
AveL =+5, V s =±15V
GBW
AveL =+1, V s =±15V
AveL = +5, Vs= ±15V
Settling Time (to ±0.01%)
Vs = ±15V (Note 2)
Vs = ±15V (Note·3)
Input Noise Voltage
Rs = 1000, I = 100Hz
R s = 1000, I = 1000Hz
R s = 1000, I = 100Hz
Rs = 1000. I = 1000Hz
Input Noise Current
MAX
TYP
MAX
UNITS
3.0
5.0
MIN
3.0
10
mV
3.0
20
3.0
50
pA
30
100
30
200
pA
10"
Large Signal Voltage Gain
Gain Bandwidth Product
TYP
50
PM155
PM156/PM157
PM155
PM15fi
PM157
200
2.0
5.0
25
4.0
7.0
10 12
0
200
V/mV
2.0
5.0
4.0
10
mA
5.0
12
50
5.0
12
50
V/p.s
PM155
PM156
PM157
2.5
5.0
20
2.5
5.0
20
MHz
PM155
PM156
PM157
4.0
1.5
1.5
4.0
1.5
1.5
p.s
25
25
20
20
15
12
15
12
0.01
0.01
7.5
30
PM155
PM156/PM157
I = 100Hz, Vs = ±15V
nV/,fHZ
I = 1000Hz, Vs = ±15V
Input Capacitance
3.0
NOTES:
1. !.nput bias current is specified for two different conditions. The T j = 25° C
specification is with the junction at ambient temperature: the Device Operating specification is with the device operating in a warmed-up condition at
25° C ambient. The warmed-up bias current value is correlated to the
junction temperature valuevia the curvesof 18 vs Tjand lavs TA. PMI hasa
bias current compensation circuit which gives improved bias current over
the standard JFET input op amps. 18 and los are measured at V eM = O.
2. Settling time is defined here for a unity gain inverter connection using 2kn
3.0
pAl,fHZ
pF
resistors. It is the time required for the error voltage I the voltage at the
inverting input pin on the amplifier •to settle to within 0.01% of its final value
from the time a 10V step input is applied to the inverter. See settling time
test circuit.
3. Settling time is defined here lora A v =-5 connection with RF=2kll.ltisthe
time required lor the error voltage (the voltage althe Inverting input pin on
the amplifier) to settle to within 0.01% 01 its Iinal value Irom the time a 2V
step Input is applied to the inverter. See settling time tast circuit.
PAGE 5-200
PM155A1PM156A/PM157A MONOLITHIC JFET INPUT OPERATIONAL AMPLIFIERS
ELECTRICAL CHARACTERISTICS at ±15V,:S V s :S±20V, -55°C:S T A :S+125°C and T HIGH= +125°C for PM155, PM156
and PM157, ±15V:S Vs:S±20V,-25° C:S T A :S+85°C and T HIGH=+85° Cfor PM255, PM256 and PM257, Vs=±15V, O°C:STA:S
+70° C and THIGH = +70°C for PM355, PM356 and PM357, unless otherwise noted.
PM1551156/157
TYP
MAX
MIN
PM255/256/257
MIN
TYP
MAX
3.5
6.5
PM355/356/357
PARAMETER
SYMBOL CONDITIONS
Input Offset Voltage
Vas
Rs =50n
4.0
Input Offset Voltage
Drift
TCVos
Rs =50n
5.0
5.0
5.0
Change In Input Offset (LI TCVos )
Rs =50n
Drift With Vas Adjust. LIVas
0.5
0.5
0.5
Input Offset Current
los
T j :5T HIGH (Note 1)
8.0
20
0.5
1.0
1.0
2.0
nA
Input Bias Current
I.
T j :5 THIGH (Note 1)
20
50
2.0
5.0
3.0
8.0
nA
Large Signal Voltage
Gain
Ava
Vs =±15V, Vo =±10V
RL = 2kn
25
75
25
75
15
50
Va
Vs =±15V, RL = 10kn
Vs =±15V, RL =2kn
±12
±10
±13
±12
±12
±10
±13
±12
±12
±10
±13
±12
V
±10.4
+15.1
-12.0
±10.4
+15.1
-12.0
±10.0
+15.1
-12.0
V
100
85
100
80
100
dB
7.0
MIN
TYP
MAX
5.0
13
UNITS
mV
~V/'C
~V/'C
permV
II
....
II)
po
CD
II)
po
......
Output Voltage Swing
Input Voltage Range
Common Mode
Rejection Ratio
Power Supply
Rejection Ratio
IVR
Vs= ±15V
V/mV
II)
II)
po
::I!
IL
II)
II:
W
ii:
:::J
IL
CMRR
VcM=±IVR
PSRR
(Note 2)
85
10
57
NOTES:
I. Input bias current is specified for two different conditions. The T j = 25° C
specification is with the junction at ambient temperature; the Device Operating specification is with the device operating in a warmed-up condition at
25° C ambient. The warmed-up bias current value is correlated to the
junction temperature value via the curves of Isvs Tjand Is vs TA. PMI hasa
bias current compensation circuit which gives improved-bias cu·rrent over
10
57
10
100
p.VIV
the standard JFET input op amps. IBand lOS are measured at V CM = O.
For PM155: T) = +125'C. For PM255: T j = +85'C. For PM355: T j = +70'C.
::I!
...
c(
c(
Z
0
~
II:
W
IL
0
2. Power supply rejection ratio is measured for both supply magnitudes
increasing or decreasing simultaneously, in accordance with common
practice.
PAGE 5-201
PM155A1PM156A1PM157A MONOLITHIC JFET INPUT OPERATIONAL 'AMPLIFIERS
ORDERING INFORMATIONt
INPUT OFFSET VOLTAGE NULLING
PACKAGE
TA =25°C
YosMAX
(mY)
v+
TO-99
a-PIN
a-PIN
HERMETIC
DIP
OPERATING
TEMPERATURE
RANGE
2.0
PM155AJ'
PM156AJ'
PM157AJ'
PM155AZ'
PM156AZ'
PM157AZ'
MIL
2.0
PM355AJ
PM356AJ
PM357AJ
PM355AZ
PM356AZ
PM357AZ
COM
PM155J'
PM156J'
PM157J'
PM155Z'
5.0
5.0
PM255J
PM256J
PM257J
PM255Z
PM256Z
PM257Z
INO
10
PM355J
PM356J
PM357J
PM355Z
PM356Z
PM357Z
COM
NOTE:
PM156~'
PM1S,Z'
APPLICATION INFORMATION
INPUT VOLTAGE CONSIDERATIONS
'Also available with MIL-STO-BB3B processing. To order add/BB3 as a suffix to
the part number.
t All listed parts are available with 160 hour burn-In, See Ordering Information.
Section 2.
PIN CONNECTIONS
9
N.C.
•
AL
•
-IN 2
~
+IN 3
7V
+
The PM Series JFET input stages can accommodate large
input differential voltages without external clamping as long
as neither input exceeds the negative power supply. An input
voltage which is more negative than V- can result in a
destroyed unit.
If both inputs exceed the negative common mode voltage
limit, the amplifier will be forced to a high positive output. If
only one input exceeds the negative common mode voltage
limit, a phase reversal takes place forcing the output to the
corresponding high or low state, In either of the above conditions, normal operation will return when both inputs are
returned to within the specified common mode voltage range.
Exceeding the positive common-mode limit on a single input will not change the phase of the output. However, if both
inputs exceed the limit, the output of the amplifier will be
forced to a high state.
6 OUT
5 BAL
v-
FOR POTENTIOMETERS WITH A TEMPERATURE COEFFICIENT';;; 100ppmfC
THE ADDED TevOS WITH NULLING IS "" O.5p.vrC/mV OF ADJUSTMENT.
MIL
4
(CASE)
a-PIN HERMETIC DIP
TO-99 (J-Sufflx)
(Z-Suffix)
POWER SUPPLY CONSIDERATIONS
Power supply polarity reversal can result in a destroyed unit.
BASIC CONNECTIONS
DYNAMIC OPERATING CONSIDERATIONS
SETTLING TIME TEST CIRCUIT
As with most amplifiers, care should be taken with lead
dress, component placement and supply decoupling in
order to ensure stability. For example, resistors from the
output to an input should be placed with the body close to
the input to minimize "pick-up" and maximize the frequency
of the feedback pole by minimizing the capacitance from
the input to ground.
2kUO.l%
+15V
:To--+-'''''","",O",''%_-=-t
5kU
0.1%
V OUT
-15V
Ay=-l
5kn 0.1%
2N4416
... 4OO0±O.1% for PM157A
··1kfl±O.1%for PM157A
+16V
A feedback pole is created when the feedback around any
amplifier is resistive. The parallel resistance and
capacitance from the input of the device (usually the invertIng input) to AC ground set the frequency of the pole. In
many instances the frequency of this pole is much greater
than the expected 3dB frequency of the closed loop gain
and consequently there is negligible effect on stability
margin. However, if the feedback pole is less than approxImately six times the expected 3dB frequency a lead
capacitor should be placed from the output to the inverting
input of the op amp. The value of the added capacitor should
be such that the RC time constant of this capacitor and the
resistance it parallels is greater than or equal to the original
feedback pole time r:onstant.
PAGE 5"202
PM725
PMI
INSTRUMENTATION
OPERATIONAL AMPLIFIER
®
FEATURES
•
•
•
•
•
•
•
•
provides maximum reliability and long-term stability of
parameters for lowest overall system operating cost. For
improved specifications, see the OP-06 Series data sheet. For
devices with internal frequency compensation see the OP-05
instrumentation and Op-07 Ultra-low Offset Voltage Operational Amplifier data sheets.
Extremely High Voltage Gain .............. 3M Typical
Low Offset Voltage and Offset Current
Low Drift with Temperature
Low Input Voltage and Current Noise
High Common Mode ReJection ....... 110dB Minimum
High Power Supply Rejection ...... 10p.VlV Maximum
Silicon-Nitride Passivation
Differential Input Overvoltage Proteclion
e
en
PIN CONNECTIONS
GENERAL INFORMATION
VOS T n
The PM725 Series of monolithic Instrumentation Operational
Amplifiers provides industry-standard 725 specifications. In
addition, Precision Monolithics' exclusive Silicon-Nitride
"Triple Passivation" process minimizes "popcorn noise" and
-IN 2
+
+IN 3
ORDERING INFORMATIONt
PACKAGE
II:
III
ii:
~
~
7V'
~
6 OUT
5 ceMP
•
Z
8-PIN HERMETIC DIP
(Z-Sufflx)
V-leASE)
&
TO-99
(J-Sufflx)
EPOXV B MINI-DIP
(P-Sufflx)
HERMETIC
T" - 25°C
VosMAX
(mV)
TO-"
8-PIN
DIP
8-PIN
14-PIN
1.0
PM725J'
PM725Z'
PM725Y'
2.5
PM725CJ
PM725CZ
PM725CY
OPERATING
PLASTIC
DIP
TEMPERATURE
RANGE
8-PIN
14-PIN DIP*
(V-Suffix)
MIL
PM725CP
COM
·Not recommended
'Also avallabla with MIL-STD-8838 processing. To orderadd/883 as a suffix to
the part number.
for new design.
t All listed part.ar. available with 160 hour burn-In. See Ordering Information,
Section 2.
SIMPLIFIED SCHEMATIC
V+
A19
OUTPUT
A3
04
v-
PAGE 5-203
11
o
~
II:
~
o
PM725 INSTRUMENTATION OPERATIONAL AMPLIFIER
ABSOLUTE MAXIMUM RATINGS
Lead Temperature Range (Soldering, 60 sec) ..• ;. 300·C
PM725C ••....•••••..........••••.•••.• O·C to +70·C
Supply Voltage ..•••.•...•. :, ••••••••••.•..•....•. ±22V
Internal Power Dissipation (see note) •........... 500mW
Differential Input Voltage •••••.••.••.........••••• ±30V
Input Voltage ••••••••..........•.•..•••• Supply Voltage
Output Short Circuit Duration ••••..•.•...•.•.• Indefinite
Storage Temperature Range
J, Y, and Z Packages .....•...•..... -65·C to + 150·C
P Package . . . . . . . . . . . . • . . . . . • . . • .. -65· C to + 125· C
Operating Temperature Range
PM725 ...........•...•.•.•••••••.••. -55·C to +125·C
Package Type
Maximum Ambient
Temperature lor·Raling
Derate AbOVe! Maximum
TO·gg (J)
80·C
7.1mW/·C
Ambient Temperature
8-Pin Plastic DIP (P)
36·C
S.6mW/·C
8-Pin Hermetic DIP (Z)
7S·C
6.7mW/·C
14-Pin Hermetic DIP(Y)
·100·C
10.0mW/·C
NOTE:
1. See table for maximum ambient temperature rating and derating factor.
ELECTRICAL CHARACTERISTICS at Vs = ± 15V, TA = 25·C, unless otherwise noted.
PM725C
PM725
TYP
MAX
TYP
MAX
UNITS
0.5
1.0
0.5
2.5
mV
los
2.0
20
2.0
35
nA
Ie
42
100
42
125
nA
PARAMETER
SYMBOL
CONDITIONS
Input Offset Voltage
Vos
RsSl0kO
Input Offset Current
Input Bias Current
Input NOise Voltage
en
MIN
'0= 10Hz
'0= 100Hz
10= 1kHz
MIN
15
9.0
8.0
'"put Resistance
RIN
Input Voltage Range
IVR
Large Signal Voltage Gain
AvO
RL 2 2kll, Vo =±10V
Common Mode
Rejection Ratio
CMRR
Rs S 10kll, VOM = ± 13.5V
Power Supply Rejection
Ratio
PSRR
Rs S 10kO, Vs = ± 5V to ± ISV
Output Voltage Swing
Vo
R L 210kO.
R L 22kO
Output Resistance
Ro
Vo= 0,10 = 0
Power Consumption
Pd
No load
1.5
±13.5
±14
1,000,000
3,000,000
110
120
2.0
±12.0
±10.0
1.5
MO
V
250,000 3,000,000
VIV
120
dB
94
10
2.0
±12.0
±10.0
150
80
nVlIHZ
±14
±13.5
±13.5
±13.5
15
9.0
8.0
105
35
"VIV
±13.5
±13.5
V
150
11
80
150
mW
ELECTRICAL CHARACTERISTICS at Vs = ±15V, -55· C :5 T A:5 +125· C for PM725, O· C :5 T A:5 +70· C for PM725C, unless otherwise
noted,
PM725C
PM725
PARAMETER
SYMBOL
CONDITIONS
Input Offset Voltage
Vos
RsSl0kll
Average Input Offset
Voltage Drill
TCVos
Rs = 500, Unnulled
Average Input Offset
Voltage Drill
TCVos n
Rs = 500, Nulled
0.6
Input Offset Current
los
TA=MAX
TA = MIN
1.2
7.5
20
40
1.2
4.0
Averege Input Offset
Current Drill
TClos
35
150
10
20
100
200
30
100
MIN
TYP
MAX
MIN
TYP
1.5
(Note 1)
2.0
(Note 1)
Input Bias Current
Ie
TA=MAX
TA=MIN
Large Signal Voltage Gain
Avo
RL22kn, TA = MAX
RL22kn, TA = MIN
Common Mode
Rejection Ratio
CMRR
Rs S 10kll, VOM = ± 13.5V
Power Supply
Rejection Ratio
PSRR
Rs S 10kn, Vs = ± 5V to ± 15V
Output Voltage Swing
Vo
R L 22kn
80
3.5
5.0
1,000,000
250,000
20
NOTE:
1. Sample tested.
PAGES-204
±10
UNITS
mV
2.0
"VloC
0.6
"V/oC
125,000
125,000
100
±10
MAX
35
50
nA
pAloC
125
250
nA
VlV
115
dB
20
"VIV
V
PM725 INSTRUMENTATION OPERATIONAL AMPLIFIER
COMPENSATION CIRCUIT
VOLTAGE OFFSET NULL CIRCUIT
R3"
Rl
Cl
V-OR~
GND
.USE R3 -= SU2 WHEN THE AMPLIFIER
IS OPERATED WITH CAPACITIVE LOAD.
-:-
*
II)
COMPENSATION COMPONENT VALUES
R,
C,
R2
C2
AV
1m
(/-IF)
1m
(J.!F)
10,000
10k
50pF
1,000
470
0.001
0.05
270
0.05
39
0.0015
0.02
....
N
:::E
IL
III
II:
W
-~-- 0.01
'0
,
27
,0
II
u:
::::i
:::E
-.~--.----
IL
"FOR MAXIMUM PSRR VS FREQUENCY
COMPENSATION NETWORK SHOULD
BE RETURNED TO V-
c(
....
c(
Z
*
o
~
'PINOUTS FOR J, Z AND P PACKAGES.
II:
W
IL
o
PAGE 5-205
PM741
PMI
COMPENSATED OPERATIONAL AMPLIFIER
FEATURES
•
•
•
•
•
•
and long term stability of parameters for lowest overall
system operating cost. For very high performance general
purpose op amps, refer to the OP-02 Series data sheet. For
duals see OP-03, OP-04 and OP-14.
Industry Standard 741 Specifications
Internal Frequency Compensation
Continuous Short Circuit Protection
MIL-STD-883 Processing Available
Silicon-Nitride Passivation
Low Noise
PIN CONNECTIONS
8 N.C.
BAL~'V+
GENERAL DESCRIPTION
The PM741 Series of Internally Compensated Operational
Amplifiers provides industry-standard 741 specifications_ In
addition, Precision Monolithics' exclusive Silicon-Nitride
"Triple Passivation" process provides maximum reliability
HERMETIC PACKAGE
10-99
5.0
6.0
6 OUT
+IN 3
5 BAL
4 V-(eASE)
TO-99
(J-Suffix)
ORDERING INFORMATIONt
TA =25"C
VosMAX
(mV)
-IN 2
a-PIN
DIP
8-PIN
DIP
14-PIN
OPERATING
TEMPERATURE
RANGE
PM741J'
PM741CJ
PM741Z'
PM741CZ
PM741Y'
PM741CY
MIL
COM
8-PIN HERMETIC DIP
(Z-Sufflx)
14-PIN HERMETIC DIp·
(V-Suffix)
'Also available with MIL-STD-8838 processing. To order add 1883 as a suffix tothe
part number.
t Ail listed parts are available with 160 hour burn-in. See Ordering Information.
* Not Recommended for
new designs.
Section 2.
SIMPLIFIED SCHEMATIC
ft9
OUTPUT
,----+--0
ft ••
ft.
ft3
ft.
BALANCE
PAGE 5-206
PM741 COMPENSATED OPERATIONAL AMPLIFIER
ABSOLUTE MAXIMUM RATINGS
O°C to + 70°C
PM741C
Supply Voltage
PM741 ...•.......•.............•.....••... ±22V
PM741C .•....••.....•......•.•.......••... ±18V
Internal Power Dissipation (Note 1) •............ 500mW
Differential Input Voltage. . . • • . . . . . . . . . . . . . . . .. ±30V
Input Voltage ........................ Supply Voltage
Output Short Circuit Duration .•......•...... Indefinite
Storage Temperature Range. . . . • . . .. -65·C to + 150·C
Lead Temperature Range (Soldering, 60 sec.) ..... 300·C
Operating Temperature Range
PM741 ....................•.... -55·Cto +125·C
NOTE:
1.
See table for maximum ambiAnt temperature rating and derating factor.
MAXIMUM AMBIENT
TEMPERATUARE
FOR RATING
PACKAGE TVPE
DERATE ABOVE
MAXIMUM AMBIENT
TEMPERATURE
TO·99 (J)
80°C
7.1mW/'C
14-PIN HERMETIC DIP iV'
100°C
10.0mW/OC
fl.PIN HERMETIC
DIP (Z)
75°C
6.7mW/'C
11
~
::E
a..
ELECTRICAL CHARACTERISTICS at TA =25'C, Vs = ±15V, unless otherwise noted.
CI)
PM741
SYMBOL
CONDITIONS
Input Offset Voltage
Vos
Rs ,s10kll
Input Offset Current
lOS
Input Bias Current
Ie
500
Input Resistance
RIN
INote 11
Large Signal Voltage Gain
Avo
RL,,2kll,
ISY
Your
Supply Current
~
MIN
TVP
MAX
MAX
UNITS
5.0
6.0
mV
200
200
nA
500
nA
0.3
Vo~
0
±10V
a:
w
PM741C
PARAMETER
TYP
MIN
0.3
50.000
------_.
2.8
Mil
25,000
VIV
mA
2.8
- - - - - _ . _.._.
ELECTRICAL CHARACTERISTICSat-55°CSTAS+ 125°C for PM741, O°CS TAS+70°CforPM741C, Vs=±15V, unless
otherwise noted.
PM741C
PM741
MAX
UNITS
MIN TVP MAX
-_.._ - - - - - - - - - - 7.5
mV
SYMBOL
CONDITIONS
Input Offset Voltage
Vos
Rs ,s10kll
Input Offset Current
los
500
300
nA
Input Bias Current
Ie
1.5
0.8
pA
Large Signal Voltage Gain
Output Voltage Swing
Avo
RL,,2kll
Vo~ ±10V
Vo
RL,,10kll
RL,,1kll
Input Voltage Range
IVR
Common Mode Rejection Ratio
CMRR
VCM~
Power Supply Rejection Ratio
PSRR
RS,s10kll
MIN
TVP
PARAMETER
6.0
VIV
25,000
15,000
±12
±12
±10
±10
±12
±12
V
70
70
dB
±10V
V
..
142
142
NOTE:
1. Guaranteed by design.
TYPICAL OFFSET NULLING CIRCUIT·
TYPICAL BURN-IN CIRCUIT"
OUTPUT
-22V
*
*
'PINOUTS FOR J AND Z PACKAGES.
PAGE 5-207
_-~VIV
ii:
:::i
a..
::E
c(
....
c(
Z
o
~
a:
w
a..
o
PM747/PM1458/1558
PMI
DUAL COMPENSATED
OPERATIONAL AMPLIFIERS
®
FEATURES
PIN CONNECTIONS
• Industry Standard 741 Specifications
• Dual PM741 Internally Compensated Operational
Amplifier .............•..... ... . .. PM747 and PM1458
• Internal Frequency Compensation
• Low Power Consumption
• Continuous Short Circuit Protection
• MIL-STD-883 Processing Available
• Silicon-Nitride Passivation
v-
N,C.
B
OUT
'0
IA)~_
_
_ _
-IN (AI 2
+IN (AI 3
7 OUT I.)
6 -IN (8)
.
5 +IN IB)
4
GENERAL DESCRIPTION
The PMI Series of Internally Compensated Operational
Amplifiers provides industry-standard 747 and 1458 specifications. In addition, Precision Monolithics' exclusive Silicon-Nitride "Triple Passivation" process provides maximum
reliability and long term stability of parameters for lowest
overall system operating cost. For very high performance
dual general-purpose op amps, refer to the OP-0310P-041
OP-14 data sheet.
v_
v_
TO-99
(J-Suffix)
TO-100
(K-Suffix)
-IN {AI
1
+IN {AI
2
BALANCE (A)
3
v-
4
BALANCE (B)
5
+IN (8)
7
ORDERING INFORMATIONt
14
BALANCE (AI
8
BALANCE (BI
PACKAGE
HERMETIC
DIP
a·PIN
t'·PIN
TA=25°C
YosMAX
(mY)
5.0
6.0
TO·BI
TO·tOO
to·PIN
a·PIN
PM1558J*
PM747K·
PM1558Z·
PM1458J
PM747CK
PM1458Z
PM747Y·
PM747CY
OPERATING
TEMPERATURE
RANGE
MIL
COM
8-PIN HERMETIC DIP
(Z-Sufflx)
·V+ (A) AND V+ (BIINTERNALLY.CONNECTED
14-PIN DIP
(Y-Sufflx)
• Also available with MIL-STO-883B processing. To order add 1883 as asuffix to
the part number.
t All listed parts are available with 160 hour burn-in. See Ordering Information,
Section 2.
SIMPLIFIED SCHEMATIC
(1/2 OF CIRCUIT SHOWN)
R9
OUTPUT
~--+-- 2kO. Vo = ±10V
MIN
Input Voltage Range
IVR
Common Mode Rejection
Ratio
CMRR
R s $10kO. VCM = ± 10V
PSRR
R S $10kO
MIN
±12
±10
±14
±13
±12
±10
±14
±13
V
25
50
15
25
VlmV
±12
±13
±12
±13
V
70
90
70
90
dB
Vs':' ±5V to ±20V
Vs = ±5V to ±18V
30
150
30
150
"V/v
ISY
TA - MAX Per Amplifier
TA = MIN No Load
1.5
2.0
2.5
3.3
1.5
2.0
2.5
3.3
mA
Power Consumption
Pd
T A = MAX Per Amplifier,
TA =MIN No Load
45
60
75
100
45
60
75
100
mW
Channel Separation
CS
Power Supply Rejection
Ratio
Supply Current
120
TYPICAL OFFSET NULLING CIRCUIT'
TYPICAL BURN-IN CIRCUIT'
-22V
120
-22V
'PINOUTS FOR J AND Z PACKAGES ONLY
'PINOUTS FOR Y PACKAGE ONLY
TYPICAL APPLICATION
HIGH IMPEDANCE DIFFERENTIAL AMPLIFIER'
!10k"
10k"
10kO
9Ok"
OUTPUT
'PINOUTS FOR J AND Z PACKAGES ONLY
PAGE 5-210
dB
PMI
PM4136
QUAD 741-TYPE
OPERATIONAL AMPLIFIER
®
FEATURES
•
•
•
•
•
•
•
•
RM4136 and RC4136. Each of the four amplifiers has the
proven OP-02 family advantages of low noise, low drift, and
excellent long term stability. Precision Monolithics' exclusive
Silicon-Nitride "Triple Passivation" process reduces "popcorn noise" and provides maximum reliability and long term
stability of parameters for lowest overall system operating
cost.
RM4136JRC4136 Direct Replacements
Low Noise
Silicon-Nitride Passivation
Internal Frequency Compensation
Low Crossover Distortion
Con~inuous Short-Circuit Protection
Lo,," Input Bias Current
Low Input Offset Voltage
The PM4136 Series is ideal for use in designs requiring minimum space and cost while maintaining OP-02-type performance. PM4136's with processing per the requirements of
MIL-STD-8838 and M I L-M-38S1 0 are available. For dual-7 41type versions, see the OP-03/0P-04/0P-14 data sheet. For
improved performance see the OP-09 data sheet.
GENERAL DESCRIPTION
:::Ii
a.
I/)
a:
1&1
ii:
:::i
a.
:::Ii
0(
0(
Z
PIN CONNECTIONS
ORDERING INFORMATIONt
o
~
a:
1&1
a.
(mV)
HERMETIC
DIP
14-PIN
OPERATING
TEMPERATURE
RANGE
5.0
6.0
PM4136Y'
PM4136CY
MIL
COM
o
• Also available with MIL-STD-883B Processing. To order add 1883 as a suffix to
the part number.
tAil listed parts are available with 160 hour burn~in. See Ordering Information,
Section 2.
14-PIN HERMETIC DIP
(Y-Suffix)
SIMPLIFIED SCHEMATIC
(1/4 CIRCUIT SHOWN)
v+
-IN
+IN
~
~
..I
The PM4136 Series provides four 741-type operational amplifiers in a single 14-pin DIP package, pin compatible with the
TA = 25°C
VosMAX
II
o--+-------t---
L - - + - - + - - + - o OUTPUT
v-
PAGE 5-211
PM4136 QUAD 741·TYPE OPERATIONAL AMPLIFIER
(Note 4)
ABSOLUTE MAXIMUM RATINGS
Operating Temperature Range
PM4136 ............................. -55°C to + 125°C
PM4136C............................... O'Cto +70'C
Lead Temperature Range (Soldering, 60 sec). . . . . . .. 300'C
Supply Voltage, PM4136........................... ±22V
Supply Voltage, PM4136C. PM4136GR ............ ±18V
Internal Power Dissipation (Note 1) . . . . . .. .. . . . . .. 800mW
Differential Input Voltage. . . . . . . . . . . . . . . . . . . . . . . . .. ±SOV
Input Voltage (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 15V
Output Short Circuit Duration (Note 3). . . . . . . . . .. Indefinite
Storage Temperature Range. . . . . . . . . .. -65'C to + 150'C
DICE Junction Temperature (TJ) ••••••• -65°C to +150°C
ELECTRICAL CHARACTERISTICS At
NOTES:
1. Rating applies lor ambient temperature 01 +25' C; derate linearly at
6.4mW'· C lor ambient temperatures above +25' C.
2. For supply voltages less than ± 15V. the absolute maximum input voltage Is
equal to the supply voltage.
3. Short-circuit may be ground. one amplifier only. Isc = 45mA (typical).
4.
Absolute maximum ratings apply to both DICE and packaged parts. unless
otherwise noted.
TA = +25'C and Vs = ±15V unless otherwise specified.
PM4136
PARAMETER
SYMBOL
CONDITIONS
Input Offset Voltage
Vas
Rs ,,10k{l
Input Ollset Current
PM4136C
TYP
MAX
TYP
MAX
UNITS
0.5
5.0
0.5
6.0
mV
los
5.0
200
5.0
200
nA
Input Bias Current
18
40
500
40
500
Input Resistance
R'N
Large-Signal Voltage Gain
Output Voltage Swing
MIN
(Note 1)
0.3
50.000 300.000
20.000 300.000
V/V
RL ,,2kll. VOUT= ±10V
RL ,,10k{l
±12
±14
±12
±14
V
Va
RL,,2kll
±10
±13
±10
±13
V
±12
±14
±12
±14
V
70
100
70
100
dB
Common Mode Rejection Ratio
CMRR
Rs';; 10kn. VCM = ± 12V
Power Supply Rejection Ratio
PSRR
Rs" 10kn. Vs =±5V to±15V
10
150
10
150
,V/v
No load. VOUT = 0
210
340
210
340
mW
t,
Y,N = 20mV. RL = 2kll.
CL ,;; l00pF. AVCL = + 1.0
0.13
0.13
,s
OS
Y,N = 20mV. RL = 2kll.
C L "l00pF. AVCL = +1.0
5.0
5.0
%
Power Consumption (Four Amplifiers)
Overshoot
Mil
Ava
IVR
Transient Response
nA
5.0
0.3
Va
Input Voltage Range
Transient Response
Risetime
5.0
MIN
Pd
Closed Loop Bandwidth
BW
AVCL =+ 1.0
3.0
3.0
MHz
Slew Rate
SR
RL '" 2kn. AVCL = + 1.0
1.5
1.0
VI,s
CS
I = 10kHz. Rs= lkU
open loop
105
105
dB
CS
I = 10kHz. Rs = 1kll.
AveL = 100
105
105
dB
Channel Separation
Channel Separation (Gain-l00)
ELECTRICAL CHARACTERISTICS
At -5S'C"TA " +125'C for PM4136. O'C"TA " +70'C for PM4136C. and Vs= ±15V unless
otherwise specified.
PM4136
PARAMETER
SYMBOL
CONDITIONS
Input Offset Voltage
Vas
Rs ,,10kll
Input Offset Current
MIN
TYP
PM4136C
MAX
UNITS
7.5
mV
los
500
300
nA
Input Bias Current
18
1500
800
Large-Signal Voltage Gain
Ava
Output Voltage Swing
Va
RL ,,2kU
Pd
TA = High. No load
180
300
180
300
mW
Pd
TA = Low. No load
240
400
240
400
mW
Power Consumption
25.000
15.000
±10
NOTE:
1. Guaranteed by design.
PAGE 5-212
MIN
TYP
6.0
RL ,,2kll. VOUT= ±10V
MAX
nA
V/V
V
±10
PM4136 QUAD 741·TVPE OPERATIONAL AMPLIFIER
DICE CHARACTERISTICS
1.
2.
3.
4.
5.
INVERTING INPUT (A)
NON·INVERTING INPUT (A)
OUTPUT (A)
OUTPUT (8)
NON·INVERTING INPUT (8)
B. INVERTING INPUT (8)
7. VB. INVERTING INPUT (C)
9. NON·INVERTING INPUT (C)
10.
11.
12.
13.
14.
15.
DIE SIZE 0.085 x 0.070 Inch
ELECTRICAL CHARACTERISTICS at Vs = ± 15V,
OUTPUT (C)
V + (CONNECTED INTERNALLY TO PAD 15)
OUTPUT (D)
NDN·INVERTING INPUT (D)
INVERTING INPUT (D)
V + (CONNECTED INTERNALLY TO PIN 11)
II
CD
CO)
~
Refer 10 Secllon 2 for additional DICE Informallon.
TA = + 25°C,
::::E
A-
m
a:
w
unless otherwise noted.
ii:
:i
PM4136GR
PARAMETER
SVMBOL CONDITIONS
Input Offset Voltage
Vos
Input Ollset Current
los
Rs $10kn
LIMIT
UNITS
6.0
mVMAX
200.0
nAMAX
Input Bias Current
I.
500.0
nAMAX
I nput Voltage Range
IVR
±12.0
VMIN
Common Mode
Rejection Ratio
CMRR
VCM =± 12V.
Rs $10kn
Power Supply
Rejection Ratio
PSRR
Rs $10kn.
Vs =±5Vto±15V
Output Voltage Swing
Vo
Large Signal
Voltage Gain
Power Consumption
(Four Amplifiers)
70.0
dBMIN
150.0
"VNMAX
RL ,,10kn
RL ,,2kn
±12.0
± 10.0
VMIN
Avo
RL ,,2kn
V o =±10V
20,000
VNMIN
p.
VOUT= 0
No Load
340
mWMAX
TYPICAL ELECTRICAL CHARACTERISTICS at VS= ±15V, TA = +25°C, unless otherwise noted.
PM4136GR
PARAMETER
UNITS
AVCL = + 1.0
RL ,,2kn
1.5
+ 1.0
3.0
MHz
105
dB
Slew Rate
SR
Closed Loop Bandwidth
BW
AVCL =
CS
AVCL = 100
f= 10kHz
Channel Separation
TYPICAL
SYMBOL CONDITIONS
Rs= lkn
NOTE:
Either or both V+ pads may be used without any change in performance.
PAGE 5-213
A::::E
c
....I
C
Z
0
~
a:
w
0
A-
JM38510/10104
PMI
JAN SINGLE LOW INPUT CURRENT
OPERATIONAL AMPLIFIER EXTERNALLY COMPENSATED
PIN CONNECTIONS AND ORDERING INFORMATION
GENERAL DESCRIPTION
This data sheet covers the electrical requirements for a monolithic, low input current externally compensated operational
amplifier as specified in MIL-M-38510/101 for device type 04.
Devices supplied to this data sheet are manufactured and tested
at PMI's MIL-M-38510 certified facility and are listed in QPL-38510.
COMP
B
COMP9'v'
Complete device requirements will be found in MIL-M-38510
and MIL-M-38510/101 for Class B processed devices.
-IN 2
-
"N 3
v-
GENERIC CROSS-REFERENCE INFORMATION
This cross-reference information is presented for the convenience of the user. The generic-industry types listed may not have
identical operational performance characteristics across the military temperature range or reliability factors equivalent to the
MIL-M-38510 device.
Military Device Type
04
•
6 OUT
TO-99 (J-Sufflx)
5 N.C.
•
(CASEI
Jan Device
PMI Device Type
JM38510/10104BGC PM108AJlI38510
NOTE: Lead Finish: Gold Plale.
Check with factory for other qualified lead finishes.
Generic-Industry Type
LM108A
POWER AND THERMAL CHARACTERISTICS
CASE OUTLINE
casa outline
Package
Per MIL-M-38510, Appendix C, Case Outline A-1 (8 Lead Can).
Package Type DeSignator "Gu.
8 Lead Can
G
Maximum allowable
power dlaalpaUon
330mW al TA = 125" C
Maximum
9J-A
40" C/W
lSO"c/W
(TO-99)
SIMPLIFIED SCHEMATIC
COMPENSATION
8
INPUTS
Rl
21<
026 ::I---+-~
R12
820
028
029:::1-------"1 Rl.
80k
NOTE:
1. All resistance and capacitance values are nominal.
R19
64k
R17
500
PAGE 5-214
Rl'
1k
Maximum
9J-C
v-
--~~~+---~--~--~~------~.
JM38510/10104 JAN SINGLE LOW INPUT CURRENT OPERATIONAL AMPLIFIER
ELECTRICAL CHARACTERISTICS at 5V :5 ± VCc:5 20V and -55 0 C:5 TA :5 + 125 0 C, unless otherwise noted.
PARAMETER
SYMBOL
Input Offset Voltage
V,o
Input Offset Voltage
Temperature Sensitivity
CONDITIONS
TA~ 2SoC
-55°C:::; TA :5125°C
(Note 2)
Rs~SOO
av,o
LiT"
dTAfrom -55°C to +25°C
~TA from +25°C to +125°C
TA~2SoC
Input Offset Current
1'0
(Note 2)
Input Offset Current
Temperature Sensitivity
-:rr-
al,o
.6.TA from -55°C to +25°C
.6.TA from +25°C to +125°C
+118
(Note 2)
-I'B
(Note 2)
-55°C:::; TA:S: 125°C
2soC"TA " 12SoC
-55°C:5TA :5+25°C
Input Bias Current
Power Supply Rejection Ratio
+PSRR
Power Supply Rejection Ratio
-PSRR
Input Voltage
Common Mode Rejection
Adjustment For
Input Offset Voltage
Adjustment For
Input Offset Voltage
+Vcc~
20V
-Vcc~-10V
V'N~
Rs~
Rs~
son
Rs~
son
TA~2SoC
-55°C:5"TA 125°C
TA~2SoC
-SSoc" TA " 12SoC
UNITS
-O.S
-1.0
+O.S
+1.0
mV
-S.O
-S.O
+S.O
+S.O
"V/oC
-0.2
-0.4
+0.2
+0.4
nA
-2.S
-2.S
+2.S
+2.S
pA/oC
-0.1
-0.1
-0.1
-0.1
+2.0
+3.0
+2.0
+3.0
-16
-16
+16
+16
"V/v
...::I!
-16
-16
+16
+16
"V/v
III
Output Voltage Swing
(Maximum)
nA
±Vcc~20V
V'O
ADJ (-)
±Vcc~20V
105(+)
los 1-)
±Vcc~
±Vcc~
VOP
dB
ISV
t$2SmS
ISV
t:5:25mS
ISV
mV
IS
rnA
IS
rnA
TA~+2SoC
0.8
0.6
rnA
TA~+12SoC
0.6
±16
2OV, RL ~ 10kO
RL ~2kO
V
±Vcc~
20V
RL ~ 10kO
TA~2SoC
80
40
VlmV
20
V/mV
Avs
Open Loop Voltage Gai n
(Single Ended) (Note 1)
Avs
Transient Response Rise Time
TRltr)
CF~
10pF
1000
nsec
Transient Response Overshoot
TRIOS)
CF~
10pF
SO
%
Noise (Referred to Inpul)
Popcorn
-SsoC" TA " 12SoC
VOUT~±ISV
±Vcc~SV
RL ~ 10kO
VOUT~±2V
N,(BB)
N,(PC)
±Vcc~20V
Bandwidth
a:
tI.
::I!
~
SkHz
±Vcc ~20V
Bandwidth = 5kHz
NOTES:
1. Note that gain is not specified at V 10 {ADJ) extremes. Some gain reduction is
usually seen at VIC (ADJ) extremes. For closed loop applications (closed
loop gain less than 1,000), the open loop tests (Avs) prescribed herein
should guarantee a positive, reasonably linear, transfer characteristic.
They do not, however, guarantee that the open loop gain is linear, or even
positive, over the operating range. If either of these requirements exist
TA~
2SoC
IS
p.V rms
TA~
2SoC
40
"V peak
(positive open loop gain or open loop gain linearity). they should be
specified in the individual procurement document as additional requirements.
2. Tests at common mode
3.
PAGE 5-215
VCM~
0, V CM ~-ISV, and
4(
Z
0
Open Loop Voltage Gain
(Single Ended) (Notel)
Noise (Referred to Input)
Broadband
...
....I
mV
±Vcc~20V,
(±)
1;)
4(
(Note 3)
±Vcc~
Icc
co
~
....
CO
ii:
No
External
Adjustment
No
External
ADJ.
(Note 3)
±Vcc~
.
CD
96
TA~-SSoC
Supply Current
nA
II
:::i
20V
±ISV
son
V'O
ADJ (+)
Output Short Circuit Current
(For Negative Output)
-Vcc~
10V
20V
MAX
±Vcc~
CMR
Output Short Circuit Current
(For Positive Output)
+Vcc~
25°C:5TA :5125°C
-55°C::; TA$+25°C
MIN
VCM~
+ISV.
Continuous short circuit limits will be considerably less than the indicated
test limits. Continuous losat T A :5 75°C will cause T j to exceed the maximum of 175°C. For dual devices, los is measured one channel at a time.
~
a:
III
tI.
0
JM38510/10104 JAN SINGLE LOW INPUT CURRENT OPERATIONAL AMPLIFIER
ELECTRICAL CHARACTERISTICS at 5V:O; ±VCC:O; 20V and -55'C:O; TA:O; +125'C, unless otherwise noted.
MAX
PARAMETER
SYMBOL
CONDITIONS
MIN
Slew Rate
SR (+)
Av= 1
-55'C" TA" 25'C
V'N=+5V TA = 125'C
0.05
0.05
VI~sec
Slew Rate
SR (-)
Av=1
-55'C" TA" 25'C
V'N=±5V TA = 125'C
0.05
0.05
VI~sec
t s (+)
Selliing Time
t s (-)
T A =25'C
-55°C"TA ,,125°C
TA = 25°C
-55°C" TA" 125°C
NOTES:
1. Note thatgain is not specified at VIO (ADJlextremes. Some gain reduction is
usually seen at VIO (ADJ) extremes. For closed loop applications (closed
loop gain less than 1,000), the open loop tests (Avs) prescribed herein
should guarantee a positive, reasonably linear, transfer characteristic.
They do not, however, guarantee that the open loop gain is linear. or even
positive, over the operating range. If either of these requirements exist
(positive open loop gain or open loop gain linearity). they should be
specified in the individual procurement document as additional requirements.
2. Tests at common mode VCM = 0, V cM =-15V, and VCM = +15V.
3. Continuous short circuit limits will be considerably less than the indicated
test limits. Continuous losat TAS 75°C will cause T J to exceed the maxi·
mum of 175°C. For dual devices, los is measured one channel at a time.
For Test Circuit Diagrams See MIL-M-38510/101
PAGE 5-216
UNITS
ns
ns
JM38510/10106
PMI
JAN DUAL LOW INPUT CURRENT
OPERATIONAL AMPLIFIER EXTERNALLY COMPENSATED
PIN CONNECTIONS AND ORDERING INFORMATION
GENERAL DESCRIPTION
This data sheet covers the electrical requirements for a dual low
input current externally compensated operational amplifier as
specified in MIL-M-38510/101 for device type 06.
OUTCOMP (AI
IN caMP (AI
Devices supplied to this data sheet are manufactured and tested
at PMl's MIL-M-38510 certified facility and are listed in QPL-38510.
•
Complete device requirements will be found in MIL-M-38510
and MIL-M-38510/101 for Class B processed devices.
II)
This cross-reference information is presented for the convenience of the user. The generic-industry types listed may not have
identical operational performance characteristics across the military temperature range or reliability factors equivalent to the
MIL-M-38510 device.
Military Device Type
06
II:
W
16 PIN HERMETIC DIP
(Q-Suffix)
GENERIC CROSS-REFERENCE INFORMATION
Jan Device
JM38510/10106BEB
PMI Device Type
PM2108AQ2/38510
::Ii!
0(
~
Z
Note: Lead Finishe: Acid Tin Plate
Check with factory for other qualified lead finishes.
Generic-Industry Type
LM2108A
ii:
:::i
a..
o
~
II:
W
a..
o
POWER AND THERMAL CHARACTERISTICS
CASE OUTLINE
Per MIL-M-38510, Appendix C, Case Outline D-2 (16-pin DIP).
Package Type Designator "E".
Caae outline
Package
E
Dual-in-line
Maximum allowable
power dissipation
400mWat TA ~ 125'C
Maximum
Maximum
9J-C
OJ-A
120'C/W
35'C/W
SIMPLIFIED SCHEMATIC
COMPENSATION
COMPENSATION
v+
INPUTS
o---~------------~~~
Rl
2k
R2
2.
R12
8,.
~8
NOTES:
1. All resistance and capacitance values are
nominal,
2. The circuit shown is for each amplifier, and
pins 7 and 14 have no connection.
Rl'
1k
PAGE 5-217
v-
JM38510/10106 JAN DUAL LOW INPUT CURRENT OPERATIONAL AMPLIFIER
ELECTRICAL CHARACTERISTICS at 5V:S; ±VCC:S; 20V and -55°C:S; TA:S; +125°C. unless otherwise noted.
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNITS
Input Offset Voltage
v,o
(Note 2)
Rs=SOO
-0.5
-1.0
+0.5
+1.0
mV
Input Offset Voltage
Temperature Sensitivity
LlV,o
LIT
LlTA from -SS'C to +25'C
LlTA from +2S'C to +12S'C
-5.0
-S.O
+5.0
+5.0
IfoV/'C
Input Offset Current
1'0
(Note 2)
-0.2
-0.4
+0.2
+0.4
nA
Input Offset Current
Lll,o
~
LlTA from -5S'C to +25'C
ATA from +25°C to+125°C
-2.S
-2.5
+2.5
+2.5
pAl'C
25°C~
-0.1
-0.1
-0.1
-0.1
+2.0
+3.0
+2.0
TA = 2S'C
-5S'C"TA 12S'C
-16
-16
+16
+16
IfoV/v
TA = 2S'C
-16
-16
+16
+16
IfoV/v
Temperature Sensitivity
+1'8
(Note 2)
Input Bias Current
Power Supply Rejection Ratio
TA = 25'C
-55'C"TA ",2S'C
TA = 25'C
-55°CSTA$125°C
TAS 125°C
-SS'C" TA" +2S'C
25°CSTA:::; 125°C
-I'B
(Note 2)
+PSRR
+Vcc= 10V
-Vcc= 20V
-SS'C"TA ,,+2S'C
Rs=
son
-PSRR
+Vcc=20V
Rs=
-Vcc=-IOV
Input Voltage
Common Mode Rejection
CMR
±Vcc=20V
V'N=±ISV
Rs= son
Adjustment For
Input Offset Voltage
V,o
ADJ (+)
±Vcc= 20V
Adjustment For
V,O
ADJ (-I
±Vcc= 20V
105(+)
±Vcc= ISV
(Note 3)
t,,2SmS
±Vcc= 15V
t::;25mS
Power Supply Rejection Ratio
Input Offset Voltage
Output Short Circuit Current
(For Positive Output)
son
-55°C::; lAS 125°C
+3.0
96
nA
nA
dB
No
External
Adjustment
No
External
Adjustment
IS
mV
mV
mA
Output Short Circuit Current
(For Negative Output)
'OSH
(Note 3)
Supply Current
Icc
±Vcc=ISV
Output Voltage Swing
(Maximum)
VOP
±Vcc= 20V. RL = 10kO
±Vcc= 20V, RL = 2kO
Open Loop Voltage Gain
(Single Ended) (Note I)
Avs ~±\
±Vcc= 20V
TA =2S'C
RL = 10kO
-SS'C"TA ",2S'C
Vour=±ISV
80
40
V/mV
Open Loop Voltage Gain
(Single Ended) (Notel)
A vs
±Vcc=SV
RL = 10kO
V our =±2V
20
VlmV
Transient Response Rise Time
TRI!r)
C F = 10pF
1000
nsec
Transient Response Overshoot
TRIOS)
C F = 10pF
SO
%
Noise (Referred to Input)
Broadband
N,(BB)
±Vcc= 20V
T = 2S'C
Bandwidth = 5kHz A
IS
#JVrms
Noise (Referred to Input)
Popcorn
N,(PC)
±Vcc=20V
T =25'C
Bandwidth = SkHz A
40
IfoV peak
TA =-5S'C
TA =+2S'C
TA =+12S'C
NOTES:
1. Note that gain is not specified at V 10 (ADJ) extremes. Some gain reduction is
usually seen at V'C (ADJI extremes. For closed loop applications (closed
loop gain less than 1,000), the open loop tests (Avs) prescribed herein
should guarantee a positive, reasonably linear, transfer characteristic.
They do not, however, guarantee that the open loop gain is linear, or even
positive, over the operating range. If either of these requirements exist
IS
mA
0.8
0.6
0.6
mA
±16
V
(positive open loop gain or open loop gain linearity). they should be
specified In the individual procurement document as additional requirements.
2. Tests at common mode V CM = 0, VcM=-ISV, and V CM = +15V.
3. Continuous short circuit limits will be considerably less than the indicated
test limits. Continuous losat TAS 75°C will cause T J to exceed the maximum of 1750 C. For dual devices, los is measured one channel at a time.
PAGE 5-218
JM38510/1D106 JAN DUAL LOW INPUT CURRENT OPERATIONAL AMPLIFIER
ELECTRICAL CHARACTERISTICS at 5V S
PARAMETER
Slew Rate
Slew Rate
SYMBOL
SR(+)
SR (-)
t s (+)
Settling Time
ts (-)
± VCC S 20V and -55
0
C S TA S +125 0 C, unless otherwise noted.
CONDITIONS
Av= 1
-55°CSTAS25°C
V'N= +5V
T A = 125°C
-55°CSTA S25°C
Av= 1
V'N= ±5V TA = 125°C
MIN
MAX
UNITS
0.05
0.05
V/lJ.sec
0.05
0.05
V/~sec
TA =25°C
-55°CS TAS 125°C
TA = 25°C
ns
ns
-55°CS TAS 125°C
•
--------------------------------------~-----------------------------------------------
Channel Separation
CS
±Vcc=20V
TA =25°C
NOTES:
1. Note that gai n is not specified at V 10 (ADJ t extremes. Some gal n reduction Is
usually seen at VIC (ADJ) extremes. For closed loop applications (closed
loop gain less than 1,000). the open loop tests (Avs) prescribed herein
should guarantee a positive, reasonably linear. transfer characteristic.
They do not, however, guarantee that the open loop gain is linear, or even
positive, over the operating range. If either of these requirements exist
(positive open loop gain or open loop gain linearity). they should be
specified in the individual procurement document as additional requirements.
2. Tests at common mode VCM = O. V CM =-15V. and V cM =+15V.
3. Continuous short circuit limits will be considerably less than the indicated
test limits. Continuous los at TA ::;: 75°C will cause T j to exceed the maximum of 175D C. For dual devices, los is measured one channel at a time.
80
dB
In
a:
w
ii:
:::i
A.
::Ii
...-c-c
z
o
~
a:
For Test Circuit Diagrams See MIL-M-38510/101
w
A.
o
PAGE 5-219
PMI
JIW38510/11401/11402/
11403/11404/11405/11406
®
JAN JFET INPUT OPERATIONAL AMPLIFIERS
GENERAL DESCRIPTION
GENERIC CROSS-REFERENCE INFORMATION
This data sheet covers the electrical requirements for a
monolithic, low-power, internally compensated BIFET
operational amplifier as specified in MIL-M-38510/114 for
device types 01 to 06. Devices supplied to this data sheet are
manufactured and tested at PMl's MIL-M-38510 certified
facility and are listed in QPL-38510.
This cross·reference information is presented for the convenience of the user. The generic-Industry types listed may
not have identical operational performance characteristics across the military temperature range or reliability
factors equivalent to the MIL-M-38510 device.
Complete device requirements will be found in MILM-38510 and MIL-M-38510/114 for Class B processed
devices.
Military Device Type
01
04
02
05
03
06
Generic-Industry Type
LF-155
LF-155A
LF-156
LF-156A
LF-157
LF-157A
SIMPLIFIED SCHEMATIC
NOTE: For values of Cl, C2, R5, RS see the
following table:
PAGE 5-220
01/04
02105
03/06
Cl
7pF
5pF
1.7pF
C2
7pF
5pF
1.7pF
R5
7.2kO
3.akO
3.SkO
RS
7.2kO
3.6kO
3.SkO
JM38510/11401/11402111403/11404/11405111406 JAN JFET INPUT OPERATIONAL AMPLIFIERS
ABSOLUTE MAXIMUM RATINGS
Supply Voltage Range •..•••.••.••.•••.•••....•
Input Voltage Range (Note 1) • • • . . • • • . • • • • • • • • • ••
Differential Input Voltage Range. • . • • . . • • . • . • . • •.
±22V
±20V
±40V
NOTES:
1. The absolute maximum negative input voltage is equal to the
negative power supply voltage.
2. Short circuit may be to ground to either supply. Rating applies
to + 125"C case temperature or + 75"C ambient temperature.
Lead Temperature (Soldering, 60 sec.) • . . • • . . . . . .. 300·C
Junction Temperature .............. T J 175·C(Note 3)
Storage Temperature Range: . •• .. . . .• -65·Cto +150·C
Output Short·Circuit Duration ...•..... Unlimited (Note 2)
=
3. For short·term test (in the specific burn·in and life test con·
figuration when required and up to 168 hours maximum),
TJ = 275 "C.
RECOMMENDED OPERATING CONDITIONS
Supply Voltage Range •..••...•••.•..••. ±5 to ±20 VDC
Ambient Temperature Range . • . . . • . .•
-55·C to
+ 125·C
ELECTRICAL CHARACTERISTICS at
Vcc from ±5V to ±20V; source resistance = 50 ohm; ambient temperature range = -55"C
to +125"C and figure 1, unless otherwise noted.
PARAMETER
SYMBOL
01 LIMITS
MIN
MAX
CONDITIONS
±Vcc= ±5V, VCM=OV
TA =25·C
±Vcc= ±20V
VCM = ±15V, OV
-55·CsTA s + 125·C
Input Offset
Voltage
Input Offset Voltage
Temperature Sensitivity
±VCC= ±20V
VCM=OV
Input Offset CUrrent
±VCC= ±20V, VCM=OV,
TJ=25·C
TJ = 125·C
+IIB
Input Bias Current
(Note I)
(Note 2)
(Note 3)
-liB
MAX
-5
-2
2
-7
-2.5
2.5
UNITS
30
-10
10
-20
20
-20
20
-20
-20
20
20
pA
nA
-100
-10
3500
60
-100
-10
3500
60
pA
nA
-100
-10
300
50
-100
-10
300
50
pA
nA
-100
-10
100
50
-100
-10
100
50
pA
nA
85
dB
Input Voltage Common
Mode Rejection (Note 4)
CMR
±VCC= ±2OV
VIN = ±15V
85
85
dB
Adjustment lor
Input Offset Voltage
VIO ADJ(+)
VloADJ(-)
±Vcc= ±20V
+8
Icc
TA= -55·C
±VCC= ±15V, TA = +25·C
TA = +125·C
Output Voltage Swing
(Maximum)
Open Loop
Voltage Gain
(Single Ended)
(Note 6)
Open Loop
Voltage Gain
(Single Ended) (Note 6)
VOP
AVS(+)
AVS(_)
Avs
+8
-8
Supply Current
-50
mV
-8
mA
-50
50
50
mA
6
6
4
4
mA
4
±16
±15
±16
±15
V
±VCC= ±20V, Vour= ±15V
RL =2kll, TA =25·C
-55·CsTA s +125·C
50
25
50
25
V/mV
±VCC= ±5V
RL=2kll
Vo ur = ±2V
10
10
V/mV
±VCC= ±2OV, RL = 10kll
±VCC= ±2OV, RL=2kll
PAGE 5-221
~
I.
I/)
a:
w
ii:
::i
A.
:E
c
~
z
o
~
a:
±VCC= ±20V
±VCC= ±15V
ts25ms
(Short Circuit to Ground)
;;;
....
,..
85
'OS(_)
i,..,..
~
Power Supply
Rejection Ratio
Output Short Circuit Current
(lor Negative Output)
(Note 5)
j
,..
:;
+VCC=IOV, -Vcc=-20V
+Vcc=20V, -VCC= -IOV
±VCC= ±15V
ts25ms
(Short Circuit to Ground)
....co
,..
:!::
+PSRR
-PSRR
Output Short Circuli Current
(lor Positive Output) (Note 5) 10S(+)
(j)
i,..
,..
mV
-30
±VCC= ±2OV, VCM = +15V
TI =25"C
ts25ms
TI =125·C
±Vcc=±15V, VCM=+IOV
T)=25·C
ts25ms
T) =125·C
±VCC= ±20V, -15VsVCM sOV
T)=25·C
ts25ms
T)=125·C
04 LIMITS
MIN
•
w
A.
o
JM38510111401/11402I11403l11404/11405/11406 JAN JFET INPUT OPERATIONAL AMPLIFIERS
ELECTRICAL CHARACTERISTICS at
to
Vee from ±5V to ±20V; source resistance = 50 ohm; ambient temperature range = -55 'C
+ 125 'C and figure 1, unless otherwise noted.
01 LIMITS
MIN
04 LIMITS
MAX
MIN
MAX
UNITS
SYMBOL
CONDITIONS
Transient Response
Rise Time
T~tr)
±Vee= ",15V. RL=2k(l, AV=l
C L = 100pF, See Figure 2
VIN =50mV
150
150
ns
Transient Response
Overshoot
TR(os)
±Vce= :t15V, RL=2k(l, AV=1
C L = l00pF, See Figure 2
V IN=50mV
40
40
%
Slew Rate
SR(+)
and
SR(-)
VIN= ±5V, ±Vec= ±15V
AV = 1, See Figure 2
TA =25'C
TA = -55'C, +l25'C
Settling Time
ts( +)
and
ts(-)
±Vee= ",15V (0.1% error)
TA=25'C AV= -1
See Figure 3
Noise (Referred to Input)
Broadband
NI(BB)
Noise (Referred to Input)
Popcorn
NI(PC)
PARAMETER
VI"s
3
1.5
2
1
1500
1500
±Vee=20V, TA=25'C
Bandwidth = 5kHz
10
10
I Vee = 20V, TA=25'C
Bandwidth = 5kHz
80
80
ns
p,V rms
~Vpk
NOTES:
1. Bias currents are actually junction leakage currents which double (ap·
proximately) for each 10'C increase in junction temperature TJ. Mea·
surement of bias current is specified at TJ rather than TA, since normal
warmup thermal transients will affect the bias currents. The measure·
ments for bias currents must be made within 25ms after power is first
applied to the device for test. Measurement at TA = - 55 'C Is not
necessary since expected values are too small for typical test systems.
IIBlnAI
I.
100
/
_ _ _ _...l._-'---+_..L._L---'-_-'-_ _ _ TAI"C)
2. Bias current Is sensitive to power supply voltage, common mode
--60
voltage and temperature as shown by the following typical curves:
26
-25
50
75
100
0.01
3. Negative liB minimum limits reflect the characteristics of devices with
bias current compensation.
IIBlpA)
±Vee = ±2OV
400
4. CMR is calculated from VIO measurements at VCM = + 15V and -15V.
200
5. Continuous limits shall be considerably lower. Protection for shorts to
either supply exists providing that TJ(max)" 175 ·C.
---,fI'!J~::=--""I!!'!!~=C---'---"v'mIV)
-15/-10
-5
10
15
6. Because of thermal feedback effects from output to input, open loop
gain is not guaranteed to be linear or positive over the operating range.
These requirements, If needed, should be specified by the user In additional procurement documents.
POWER AND THERMAL CHARACTERISTICS
CASE OUTLINE
Per MIL-M-38510, Appendix C, Case Outline A-1 (8 Lead
Can). Package Type Designator "G".
Package
8 Lead Can
(TD-99)
Case oulline
Maximum allowable
powe, dissIpation
G
330mWatTA =125'C
PIN CONNECTIONS & ORDERING INFORMATION
N.C•
•
OF:~~re7
+Vcc
-IN 2
6 OUT
+IN 3
6 OFFSET
NULL
4
-Vee
(PIN 4 CONNECTED TO CASE)
Jan Device
JM38510/11401 BGC
JM38510/11404BGC
JM38510/11402BGC
JM38510/11405BGC
JM38510/11403BGC
JM38510/11406BGC
Note: Lead Finish-Gold Plate.
Check with factory for other qualified lead finishes.
PAGE 5-222
PMI Device Type
PM155J1/38510
PM155AJ1I38510
PM156J1I38510
PM156AJ1/38510
PM157 J1I38510
PM157AJ1/38510
Maximum MaxImum
SJ - C
SJ - A
40·C/w
150·C/w
JM38510/11401/11402I11403/11404/11405/11406 JAN JFET INPUT OPERATIONAL AMPLIFIERS
ABSOLUTE MAXIMUM RATINGS
Supply Voltage Range ......................... ±22V
Input Voltage Range (Note 1) . . . . . . . . . . . . . . . . . . .. ±20V
Differential Input Voltage Range. . . . . . . . . . . . . . . .. ±40V
NOTES:
1. The absolute maximum negative input voltage is equal to the
negative power supply voltage.
2. Short circuit may be to ground to either supply. Rating applies
to + 12S'C case temperature or + 7S'C ambient temperature.
Lead Temperature (Soldering, 60 sec.) ... . . . . . . . .. 300'C
Junction Temperature .............. TJ = 175'C (Note 3)
Storage Temperature Range ........ " -65'C to +150'C
Output Short-Circuit Duration ....... " Unlimited (Note 2)
3. For short·term test (in the specific burn·in and life test con·
figuration when required and up to 168 hours maximum),
TJ =27S'C.
RECOMMENDED OPERATING CONDITIONS
Supply Voltage Range .................. ±5 to ±20 VDC
Ambient Temperature Range .... " . .. -55'C to +125'C
ELECTRICAL CHARACTERISTICS at
Vee from ±5V to ±20V; source reSistance = SO ohm; ambient temperature range = -SS'C
to +12S'C and figure 1, unless otherwise noted.
PARAMETER
SYMBOL
02 LIMITS
MAX
CONDITIONS
MIN
±Vee= ±5V, VeM=OV
TA =25'C
Inpul Offset
Voltage
-5
5
05 LIMITS
MAX
MIN
UNITS
-2
mV
±Vee= ±20V
VeM = ±15V. OV
-7
-2.5
2.5
-10
10
-55'C"TA " + 125'C
Input Offset Voltage
Temperature Sensitivity
±Vee= ±20V
VeM=OV
Input Offset Current
-30
30
±Vee= ±20V, VeM =OV,
TJ =25'C
-20
20
-20
20
pA
TJ = 125'C
-20
20
-20
20
nA
-100
-10
3500
60
-100
-10
3500
60
pA
nA
-100
300
50
-100
-10
300
50
pA
nA
100
-100
-10
100
50
pA
nA
±Vee= ±20V, VeM= +15V
Tj =25'C
t,,25ms
TI =125'C
+IIB
Input Bias Current
(Note 1)
-liB
(Note 2)
±Vee= ±15V, VeM= +10V
Ti =25'C
Ti =125'C
t,,25ms
±Vee= ±20V, -15V"VeM "OV
Ti=25'C
t,,25ms
Tj = 125'C
(Note 3)
Power Supply
Rejection Ratio
+PSRR
-PSRR
+Vee=10V, -Vee= -20V
Input Voltage Common
Mode Reiectlon (Note 4)
CMR
±Vee= ±20V
VIN = ±15V
Adjustment for
Input Offset Voltage
VIO ADJ(+)
V IO ADJ(-)
±Vee= ",20V
-10
-100
-10
85
dB
85
85
dB
+8
+8
85
+Vee=20V, -Vee = -10V
-8
±Vee= ±20V
±Vee= ±15V
Output Short Circuit Current
t,,25ms
(for Positive Output) (Note 5) 105(+)
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _-'-(St,ort Circuit to Ground)
Output Short Circuit Current
(for Negative Output)
(Note 5)
10S(_)
±Vee= ±15V
t:s;25ms
(Short Circuit to Ground)
Supply Current
Icc
±Vcc= ±15V, TA= +25°C
Open Loop
Voltage Gain
(Single Ended)
(Note 6)
Open Loop
Voltage Gain
(Single Ended) (Note 6)
AV5(+)
AVS(_)
Avs
50
50
11
7
11
rnA
mA
±Vee = ±20V, RL = 10k!!
±16
±16
± Vee = ±20V, RL = 2k!!
±15
±15
±Vee= ±20V, VOUT= ±15V
RL =2kll, TA =25'C
-55'C"TA" +125'C
50
50
25
25
±Vcc= ±5V
RL=2kll
VOUT= ±2V
10
10
PAGE 5-223
rnA
7
TA = +125'C
VOP
rnV
-8
-50
-50
TA=-55'C
Output Voltage Swing
(Maximum)
50
v
VlmV
VlrnV
•
JM38510/11401111402I11403J1140411t405111406 JAN JFET INPUT OPERATIONAL AMPLIFIERS
ELECTRICAL CHARACTERISTICS at Vee from ±5V to ±20V; source resistance = 50 ohm; ambient temperature range = -55'C
to +125'C and figure 1, unless otherwise noted.
05 LIMITS
02 LIMITS
MIN
SYMBOL
CONDITIONS
Transient Response
Rise Time
TR(tr)
,"Vee = ,"15V; RL=2kll, AV=I
CL = loopF, See Figure 2
VIN =50mV
Transient Response
Overshoot
TR(OS)
,"Vee = ,"15V, RL=2kll, AV=I
CL = loopF, See Figure 2
VIN =50mV
Slew Rate
SR(+)
and
SR(-)
VIN= ,"5V, ,"Vee= ,"15V
AV = I, See Figure 2
TA =25'C
TA = -55'C, +125'C
Settling Time
t8(+)
and
ts(-)
,"Vee = ±15V(0.1% error)
TA=25'C AV= -I
See Figure 3
Noise (Referred to Input)
Broadband
NI(BB)
,"Vee =20V, TA =25'C
Bandwidth = 5kHz
NOise (Referred to Input)
Popcorn
NI(PC)
IVee= 20V, TA=25'C
Bandwidth = 5kHz
PARAMETER
MAX
UNITS
100
100
ns
40
40
%
MAX
MIN
7.5
V/~s
10
5
1500
1500
ns
10
10
,N rms
80
80
~VPk
NOTES:
1. Bias currents are actually junction leakage currents which double (approximately) for each 10 0 e increase in junction temperature TJ . Measurement of bias current is specified at TJ rather than TA. since normal
warmup thermal transients will affect the bias currents. The measurements for bias currents must be made within 25ms after power is first
applied to the device for test. Measurement at TA = - 55'C 18 not
necessary since expected values are too small for typical test systems.
2. Bias current is sensitive to power supply voltage, common mode
voltage and temperature as shown by the following typical curves:
IIBlnA)
100
10
_ _ _ _---'L--'-_+_'---'_-"-_.l...-_ _-I~ TAI'C)
25
50
75
100
0.01
IIB/pA)
400
200
-'5/-'0
-5
10
4. CMR is calcu)ated from VIO measurements at VeM = + 15V and -15V.
5. Continuous limits shall be considerably lower. Protection tor shorts to
either supply exists providing that TJ(max) '" 175 'C.
15
3. Negative liB minimum limits reflect the characteristics of devices with
bias current compensation.
6. Because of thermal feedback effects from output to input, open loop
gain is not guaranteed to be linear or positive over the operating range.
These requirements. if needed, should be specified by the user in additional procurement documents.
PAGE 5-224
JM38S10/11401/11402111403/11404/1140S/11406 JAN JFET INPUT OPERATIONAL AMPLIFIERS
ABSOLUTE MAXIMUM RATINGS
Supply Voltage Range ......................... ±22V
Input Voltage Range (Note 1) . . . . . . . . . . . . . . . . . . .. ±20V
Differential Input VOltage Range. . . . . . . . . . . . . . . .. ±40V
NOTES:
1. The absolute maximum negative input voltage is equal to the
negative power supply voltage.
2. Short circuit may be to ground to either supply. Rating applies
to + 125'C case temperature or + 75'C ambient temperature.
Lead Temperature (Soldering, 60 sec.) . . . . . . . . . . .. 300'C
Junction Temperature .............. TJ = 175'C (Note 3)
Storage Temperature Range. . . . . . . . .. -65'C to +150'C
Output Short-Circuit Duration . . . . . . . .. Unlimited (Note 2)
3. For short-term test (in the specific burn-in and life test configuration when required and up to 168 hours maximum),
TJ =275'C.
RECOMMENDED OPERATING CONDITIONS
Supply Voltage Range .................. ±5 to ±20 VDC
Ambient Temperature Range ......... -55'Cto +125'C
•
ELECTRICAL CHARACTERISTICS at
Vcc from ±5V to ±20V; source resistance = 50 ohm; ambient temperature range = -55'C
to +125'C and figure 1, unless otherwise noted.
03 LIMITS
PARAMETER
Input Offset
Voltage
SYMBOL
VIO
CONDITIONS
±Vcc= ±20V
VCM = ±15V, OV
-55'CsTA s + 125'C
-7
-2.5
2.5
-10
10
Input Offset Current
110
(Note 3)
-30
30
±Vcc= ±20V, VCM=OV,
TJ =25'C
-20
20
-20
20
pA
TJ = 125'C
-20
20
-20
20
nA
-100
-10
3500
60
-100
-10
3500
60
pA
nA
±Vcc= ±15V, VCM = +10V
TJ =25'C
ts25ms
Tj =125'C
-100
-10
300
50
-100
-10
300
50
pA
nA
±VCc= ±20V, -15VsVCM sOV
Tj =25'C
ts25ms
TJ =125'C
-100
-10
100
50
-100
-10
100
50
pA
nA
+PSRR
+VCc= 10V, -VCc= -20V
-PSRR
+Vcc=20V, -VCc= -10V
Input Voltage Common
Mode Rejection (Note 4)
CMR
Adjustment for
Input Offset Voltage
VIO ADJ(+)
V IO ADJ(-)
Power Supply
Rejection Ratio
85
dB
±VCC= ±20V
VIN ",±15V
85
85
dB
±VCC= ±20V
+8
+8
mV
-8
±Vcc= ±20V
10S(+)
±VCC= ±15V
ts25ms
(Short Circuit to Ground)
Output Short Circuit Current
(for Negative Output)
(Note 5)
105(-)
±VCc= ±15V
ts25ms
(Short Circuit to Ground)
Supply Current
Icc
Open Loop
Voltage Gain
(Single Ended)
(Note 6)
Open Loop
Voltage Gain
(Single Ended) (Note 6)
VOP
AVS(+)
A VSI _)
Avs
-50
TA = -55'C
±VCc= ±15V, TA = +25'C
TA = +125'C
±VCC= ±20V, RL =10k!l
± VCC = ±20V, RL = 2k!l
±Vcc= ±20V, Vour = ±15V
RL =2k!l, TA=25'C
-55'CsT A s +125'C
±VCc= ±5V
RL =2kO
Vour = ±2V
PAGES-22S
-8
mA
-50
50
50
11
11
III
II:
W
u:
:;
II.
:2
C
85
Output Short Circuit Current
(for Positive Output) (Note 5)
Output Voltage Swing
(Maximum)
UNITS
mV
±Vcc'" ±20V, VCM '" +15V
Tj ",25'C
ts25ms
Ti =125'C
-liB
MAX
-2
±Vcc= ±20V
VCM=OV
Input Bias Current
(Note 1)
(Note 2)
MIN
-5
:-
"~
"
0
-6
'-----,W"'A"'V=EF"'O"'."'M:":2:------'----:W"A""V:::E"'FO::':."'M:-:3:----.T1ME (PSI
(POSITIVE SLEW RATEI
PARAMETER
SYMBOL
TRI',I
DEVICE
TYPE
ALL
INPUT PULSE
SIGNAL AT
t r s50ns
OUTPUT
PULSE
SIGNAL
+50mV
WAVEFORM.
EQUATION
TR 1t,I = ...
+50mV
WAVEFORM 1 TR 10SI = 100 ("VoNOI"
SRI+I
0., 02, 04, 05
03,06
-5V to +5V STEP
-1V to +1V STEP
:~~~~~:~ ~
SR(-I
01, 02, 04, 05
03,06
+5V to -5V STEP
-1V,0 +1V STEP
TR(OSl
ALL
Figure 2. Test Circuit for Transient Response and Slew Rate
PAGE 5-228
SR 1+1 = "VOI+)/ "'1+1
(NEGATIVE SLEW RATEI
JM38510/11401111402/11403l11404111405/11406 JAN JFET INPUT OPERATIONAL AMPLIFIERS
•
§...
...
§...
...
§...
...&is
!...
~...
:!::
§...
...
NOTES:
1. RESISTORS ARE :1:1.0% AND CAPACITORS ARE ±10% UNLESS OTHERWISE
SPECIFIED.
2.
3.
4.
PRECAUTION SHALL BE TAKEN TO PREVENT DAMAGE TO THE D.U.T. DURING INSERTION INTO SOCKET AND IN APPLYING POWER.
FOR DEVICE TYPES 01 and 04, 81 IS OPEN, AV = -1 AND VIN = lOY.
SETTLING TIME, ts. MEASURED ON PIN 5, IS THE INTERVAL DURING WHICH
THE SUMMING NODE IS NOT NULLED WITHIN THE SPECIFIED ACCURACY
REFERRED TO THE OUTPUT. .
CS
ii
Figure 3. Test Circuit for Settling Time
...51
I/)
BURN·IN
a:
III
Devices supplied by PMI have been subjected to burn·in per
method 1015 of MIL·STD·883 using test condition C with cir·
cuit shown on Figure 4 or test condition F usfng circuit
shown on Figure 5.
+40V
4'''''
ii:
::;
CL.
....
=
~
o
~
a:
III
CL.
o
Figure 4. Test Circuit. Bum·ln (Steady·State Power and
Reverse Bias) and Operating Life Test
Figure 5. Accelerated Bum·ln and Life Test Circuit
PAGE 5-229
BUFFERS
(VOLTAGE FOLLOWERS)
BUFFERS (VOLTAGE FOLLOWERS)
INDEX
PRODUCT
TITLE
BUF-01
BUF-02
BUF-03
Precision Buffer/Voltage-Follower ..•.........•...••.......•.....•........••.••.......•..... 6-3
High-Speed BIFET BufferlVoltage-Foliower ....•.•..•..••.•.....•.•........•....•.•..•..•.•. 6-8
Very High-Speed Buffer/Voltage-Follower ......................•.•..•.•.•..•...•...••..•..• 6-12
PAGE
INTRODUCTION
Analog buffers, as the name implies, are used to buffer a
high-impedance source from a low-impedance load while
accurately reproducing the input signal. Consequently, the
most important criterion for a buffer is that it introduces
minimal error between input signal and output signal. Inaccuracies such as those due to offsets, bandwidth limitations,
or non-unity gain must be considered when specifying an
analog buffer. The buffer is like an op amp operating in the
voltage follower mode. Many manufacturers specify buffers
as if they were operational amplifiers making the error
analysis of a buffer a tedious chore.
PMl's buffers are unique in specifying maximum DC output
error for a wide range of input signals, source resistances, and
load impedances. Output error includes errors Introduced by
offset voltage (Vas), input bias current (Ie), voltage gain (Av),
common-mode rejection ratio (CSMRR) and output loading
(Ra/(RL + ra)).
PMI tests, specifies and guarantees the maximum output
error. For people using op amps as buffers, a worst-case
analysis must be performed to determine what the maximum DC output error could be.
The Important specs for a buffer are output error, slew rate,
bandWidth, Input bias current, and output drive capability. A
brief scan of the PMI buffer specifications will show the
premium performance that has been achieved through
PMI's high-technology processing which includes triple
passivation, Zener Zap trimming and superior design. Common applications of buffers Include Sample/Hold circuits,
ADCs, analog commutators,and Impedance converters.
Three PMI voltage buffers (also known as unity-gain amplifiers or voltage followers) satisfy most buffer applications. The
BUF-01 stresses accuracy and is suitabie in low-speed applications. The BUF-02 provides high speed along with accuracy. The BUF-03 delivers very high speed and bandwidth
while surpassing the accuracy specifications of comparable
devices. The BUF-03 is especially well-suited to drive large
capacitive loads.
PAGE 8-2
BUF-Ol
PMI
PRECISION BUFFER/WLTAGE FOLLOWER
WITH OVERVOLTAGE PROTECTION
FEATURES
voltage, input bias current, gain, CMRR and output loading.
This ensures that the TOTAL output error will not exceed the
maximum under any combination of input or output.
•
•
•
•
•
•
Output Error Fully Specified. . . . . . .. 250l'V Maximum
Low Input Offset Voltage. . . . . . . . . . . . .. 6OI'V Typical
Pin Compatible with LM110
Drives 10kO Load to ±10V
Low Voltage Gain Error . . . . . . . . . . . . . . . . . . .. 0.001 %
Excellent Power Supply
Rejection Ratio ................... 106dB Typical
• Low Output Impedance . . . . . . . . . . . . . .. 0.030 Typical
• Low Input Noise Voltage. . . . . . . . .. 0.8I'Vp.p Maximum
Pin compatible with the LM110, the BUF'()1 features low output Impedance (0.030 typical), high gain and excellent power
supply rejection (106dB typical) with extremely low input
voltage noise.
Fabricated with Precision Monolithics' exclusive SiliconNitride "Triple Passivation'· Process," the BUF-01 utilizes
on-chip zener-zap trimming to achieve very low offset voltage with excellent long-term stability. This eliminates the
need for offset nulling in all but the most stringent applications.
GENERAL DESCRIPTION
~
•
TO-"
I-PIN
DIP
8-PIN
100
100
150
150
BUF01AJ'
BUF01EJ
BUF01BJ'
BUF01FJ
BUF01AZ'
BUF01EZ
BUF01BZ'
BUF01FZ
W
"!:i
NULLe7V+
ORDERING INFORMATIONt
VosMAX
(IlV)
OPERATING
TEMPERATURE
RANGE
N.C. 2
MIL
o
2!.
(/)
5 N.C.
v-
COM
c
6 OUTPUT
INPUT 3
II:
W
•
I&.
I&.
'(CASEI
::I
ID
MIL
COM
8 PIN HERMETIC DIP
(Z·Sufflx)
TO·99
(J·Sufflx)
• Also available with MIL-STO-883B processing. To order add/883 as asufllx to
the part number.
t All listed parts are available with 160 hour burn-in. See Ordering Information.
Section 2.
SIMPLIFIED SCHEMATIC
V+
OPTIONAL OFFSET NULLING CIRCUIT
>-_--oV+
INPUT
0--"""'«-£---1
II:
o....
....
oI&.
PIN CONNECTIONS
NULL
HERMETIC PACKAGE
iii
W
The BUF'()1 is the first precision voltage follower tested and
guaranteed with a Maximum Output Error specification.
Maximum Output Error includes errors introduced by offset
TA =25°C
•
...--r-WV----+----+--+--oOUTPUT
INPUT
>"--<> OUTPUT
V-
PAGE 1-3
BUF'()1 PRECISION BUFFERIVOLTAGE FOLLOWER
ABSOLUTE MAXIMUM RATINGS
(Note 3)
Supply Voltage .................................... ±22V
Internal Power Dissipation (Note 1) ••••••••••••••• 500mW
Input Voltage (Note 2) ••••••••••••••••••••••••••••• ±22V
Output Short Circuit Duration ••••••••••••••••••• Indefinite
Storage Temperature Range •••••••••••• -65·C to +150·C
Operating Temperature Range
BUF-01A, BUF-01B ••••••••••••••••••• -55·C to +125·C
BUF-01E, BUF-01F ...................... O·Cto +70·C
DICE Junction Temperature (Tj ) ••••••••• -65·C to +150·C
Lead Temperature Range (Soldering, 60 see) •••••••• 300·C
ELECTRICAL CHARACTERISTICS
PARAMETER
NOTES:
I. See lable lor maximum ambient temperature rating and derating lactor.
2. For supply vollagesless than ±22V, theabsolut. maximum Inputvollage Is
equal to the supply voltage.
3. Abaolute ratings apply to both DICE and packaged parts unleBS otherwise
noted.
Maximum Ambient
Temperature Rating
Paclaige Type
Derate Above Maximum
Ambient Temperature
TO-99IJ)
8O'C
7.ImWI'C
8 PIN HERMETIC DIP (Z)
75'C
6.7niW'C
at Vs = ± 15V, TA = + 25·C, unless otherwise noted.
BUF·01A
BUF·01E
TYP
MAX
SYMBOL
CONDITIONS
Maximum Output Error
OUTerror
VIN = +IOV, OV, -IOV
Rs=O to 20kll
RL 2: 10Kfl lin all combinations.)
Input Oflset Voltage
Vos
VIN=OV, Rs=5011
Input Current
liN
Input Resistance
RIN
MIN
0.1
BUF·01B
BUF'()1F
TYP
MAX
MIN
0.25
0.2
0.5
UNITS
mV
80
100
80
150
~V
±2.0
±7.0
±2.0
±7.0
nA
0.0025
0.001
0.005
%
lO"
II
'O'l
Large·Signal Voltage Gain Error AVE
RL",10kll, Vo= ±10V
0.001
Output ReSistance
Ro
Vo = 0,10 =0
Input Voltage Range
VIN
Output Current
10
Power Supply Rejection Ratio
PSRR
±3V"VS" ±I8V
Small Signal Bandwidth
BW
I Note I)
Input Noise Voltage
en pop
0.1 Hz to 10Hz INote 2)
0.5
0.8
0.5
0.8
~Vp.p
Input Noise Current
in pop
O.IHz to 10Hz INote 2)
15
40
15
40
PAp.p
Slew Rate
SR
RL 2: 10kfl (Note I)
Power Consumption
Pd
Vs=±15V,Vo=0
Vs = ±3V, Vo =0
0.03
±12.0
0.03
±13.0
±12.0
±13
-5VsVO'" +5V
5
0.4
V
±I3
mA
20
0.4
0.7
0.1
0.2
I'VN
MHz
V/~
0.2
120
75
6
32
7
0.7
0.1
11
±13.0
150
80
8
rnw
at Vs = ± 15V, - 55· C ~ TA ~ + 125· C for BUF-01 A and FUB-01 B,
O·C gA ~ + 70·C for BUF-01E and BUF-01F, unless otherwise noted.
ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
CONDITIONS
Maximum Output Error
OUTerror
VIN= +IOV, OV, -IOV;
Rs=O to 20kll
RL 2: 10kfl (In all combinations)
Input Offset Voltage
Vas
VIN=OV, RS = 5011
Large-Signal Voltage Gain Error AvE
RL",IOkll, Va= ±IOV
Average Input Offset
Voltage Drift
TCVas
I Note 21
Input Current
liN
Average Input
Current Drift
TCliN
MIN
BUF·01A
BUF'()1E
TYP
MAX
0.2
MIN
0.35
BUF'()1B
BUF'()1F
TYP
MAX
UNITS
0,8
mV
~V
0.4
80
280
120
400
0.002
0.0035
0.002
0.008
%
0.2
1.8
0.3
2.5
~V/'C
±I2
nA
120
pAJ'C
±I2
(Note 2)
Input Voltage Range
VIN
Power Supply Rejection Ratio
PSRR
Vs= ±3V to ±18V
Power Consumption
Pd
Vo·=O
10
±II.5
80
NOTES:
1. Guaranteed by design.
2. Sample tested.
PAGE 6-4
120
±12.6
12
±II.O
±12.6
V
32
10
51
I'VIV
150
90
180
mW
BUF-01 PRECISION BUFFER/VOLTAGE FOLLOWER
TYPICAL PERFORMANCE CURVES
BUF·01 LOW
FREQUENCY NOISE
SMALL-SIGNAL
TRANSIENT RESPONSE
LARGE-SIGNAL
TRANSIENT RESPONSE
II
TOTAL INPUT NOISE
VOLTAGE vs FREQUENCY
'000
p.o.,
f--
~'
Rs"2OOkn
~
~
I III
,..
10
100
'000
." ."
TRIMMED OFFSET VOLTAGE
vs TEMPERATURE
"'
~o
---
Vas TRIMMED TO <5101V AT 25"C
NULLING POT'" 20kn
I
/
/
~
!/
\.
I!;
I!;
"'310
'00
O.3,uVl~o.
,
2
3
4
,
,
,
'
TREND LlNEt ¥'~~{;"~'INE
6
6
7
B
9
10 11 12
TIME (MONTH)
INPUT BIAS CURRENT
vs TEMPERATURE
POWER CONSUMPTION
vs POWER SUPPLY
'000
I"
Vs - ±16V
"
"-
-
V
r- r-
TA " +2s<'C
.,...
/"
II
\
"'
I
10
-'2
-'8
BANDWIDTH (kHz)
/
\.
~
1.0
r--
Vs = ±15V
> 2.
,
~
:....
-
(O:2f:V/mO.TREND LINE
?' "'~~V/m0'I~END LlNEr¥·.tE~~~·INE
V
RS = 0
FREQUENCY (Hz)
30
~,fe~~tINE~....:..r=.~.-~
".
VS- :!:16V
:>
'2
VS" ±15V
TA" +25"C
~
TA "25"C
.!!
OFFSET VOLTAGE STABILITY
vs TIME
'8
-
RESISTO~~ :~IU\ED
1111111
,.0
,.
TH'ERMAL NOISE OF SOURCE
r-
INPUT WIDEBAND NOISE
vs BANDWIDTH
(0.1 Hz TO FREQUENCY
INDICATED)
\ /
-60
/
-
-
60
TEMPERATURE I·C)
'00
••rei
-60
TEMPERATURE
PAGE 6-5
'00
.•
"
20
80
40
TOTAL SUPPLY VOLTAGE, V+ TO V-.IVOLTS)
BUF-01 PRECISION BUFFER/VOLTAGE FOLLOWER
TYPICAL PERFORMANCE CURVES
OUTPUT VOLTAGE
MAXIMUM UNDISTORTED
OUTPUT vs FREQUENCY
PSRR vs FREQUENCY
120
vs LOAD RESISTANCE
2O..-----,---,-.,..-rn'TTT-.,..--r.,--r-rrm
1---+-++ IJ~ ~
-+--+-f-HTAffl
" +r-2&0C
1j! ,.
!!.V
1111111111
110
T~"~ 2!i"C
I
100
j
~
NEGATIVE SWING
1'0~-+-7'r~~~~~-+++~
90
0:
~
I I II
I I I IIII
POSITIVE SWING
~
80
/
O.r-4/~++~~-+~rH~
r..,
70
60
50
0.1
10
1.0
100
,.1\
'.0
10k
FREQUENCY (Hz)
FREQUENCY (kHz)
GAIN AND PHASE vs
FREQUENCY RESPONSE
+5
!
Il~!N
90
\
INPUT
,11111
Vcc=±15VIII
-15
SECOND-ORDER LOWPASS FILTER
180
iW~E
-10
RL "1Mn
CL = 30pF
.0
LOAD RESISTANCE TO GROUND Iknl
WO=R~
c.
-90
1\
OUTPUT
R
a=,,?
-180
\
Your = 5Om~r-P
-270
-20
1111111
-25
10kHz
100kHz
-360
1MHz
10MHz
FREQUENCY (MHz)
HIGH-IMPEDANCE DIFFERENTIAL AMPLIFIER
TYPICAL APPLICATIONS
-INPUT
SECOND-ORDER HIGHPASS FILTER
6NPUT I
C
C
Rl
~
~r-7
OUTPUT
+ INPUT
R3
THEN AV =
1
W (I '" C
v'Fi'iR2
R4
a=.JRlIR2
2
PAGE 6-8
R2
'ii1
BUF-01 PRECISION BUFFER/VOLTAGE FOLLOWER
TRANSIENT RESPONSE TEST CIRCUIT
BUFFERED REFERENCE
+13 TO+40V
OUTPUT
INPUT
+15V
REF
--
BUF·02 HIGH SPEED BI·FET BUFFERIVOLTAGE FOLLOWER
ABSOLUTE MAXIMUM RATINGS
BUF·02A, BUF·02B ............... -25·Cto +125·C
BUF·02E, BUF·02F ................... O·Cto +70·C
Lead Temperature Range (Soldering 60 sec.) ...... 300 ·C
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ±18V
Internal Power Dissipation (Note 1) ............ 500mW
Input Voltage (Note 2) . . . . . . . . . . . . . . . . . . . . . . . .. ±15V
Output Short Circuit Duration. . . . . . . . . . . . . .. Indefinite
Storage Temperature Range ........ -65·C to +150·C
Operating Temperature Range
ELECTRICAL CHARACTERISTICS
Temperatur. 'or Rating
O,r._e Above Maximum
Ambient Temperatur.
TO·99 rJI
80·C
7.1mWI"C
a-Pin Hermetic Dip (Zl
75°C
6.7mWfOC
Maximum Ambient
Package Type
at Vs= ±15V, T A =25·C, unless otherwise noted.
BUF·02A
BUF·02E
PARAMETER
MIN
BUF·02B
BUF·02F
TYP
MAX
UNITS
1.5
4.0
mV
1.0
1.0
3.0
mV
0.2
0.2
0.5
nA
SYMBOL
CONDITIONS
TYP
MAX
Maximum Output Error
OUTerror
Y,N = + 10V, OV, -10V
Rs=O 10 20kll
RL ~ 10k!}. in all combinations.
0.8
1.5
Input Offset Voltage
Vos
V,N=OV, Rs ,,501l
0.5
Input Current
liN
(Note 41
0.1
Input Resistance
RIN
MIN
10 12
Large Signal Voltage Gain Error AVE
10 12
0.001
RL" 10kll, aVIN = ±10V
0.015
Ro
Input Voltage Range
VIN
Input Noise Voltage Density
en
Rs= 1001l, f= 100Hz
Input Noise Current Density
in
f = 100Hz
Slew Rate
SR
RL ,,10kll (Note 3)
Power Consumption
Pd
Vo=OV
±10.5
Output Current
±11.5
Settling Time
ts
aVIN = 10V, to 0.1 %
aVIN = 10V, to 0.02%
V
nVl.j'RZ
0.01
0.01
pAl.j'RZ
12
24
9.0
150
10
±10V::s;VSs ±15V
Il
±11.5
15
10
PSRR
±10.5
%
0.03
15
-5V"Vo " +5V
Power Supply Rejection
0.04
0.001
0.03
Output Resistance
Il
18
210
V/"s
240
160
10
20
57
0.7
1.5
63
II
...~
~
ID
iii
II:
W
......
0
0==
...
W
CJ
~
0
'"
;
Vs "" ± 15VJ TA
~--+---+---
~~~H+-~~-~--+--~
!
= 25°C
-10 0!-_*"Ll-,l,,..--,,~-.,L2.0,--......,,.!2.5
SETTLING TIME (#oIS8C)
30
~ 27
lo.;::;
V
~ 24
~ 21
~
!;
,.
II
3
8
;; 7
lDnA
Vs =:t16V
BUF-02B/F"
'"A
V
'OOpA
'1/
TOpA
1.0
10
OUTPUT LOAD RESISTANCE
0.1
100
ldB
LU
OdB
-2dB
-3dB
-&lB
r-
~
27.
50
70
90
110
130
r--
-,
120
'iD 110
Vs'" :!:15V
~100
Rl
S so
2kn
~
1M
10M
FREQUENCY (Hz)
"
1M
FREQUENCY 1Hz)
PAGE 8·10
1000
:
- """
""-
NEGATIVE
0 - _SUPPLY
!
20
'"
10
0
10M
10
f"c-
TA"
"'\. POS'~'VE'\.
SUPPLY
'\.
"\.
'\.
'" "-
'\.
'\.
a:
I'r-
lOOK
100
i ~•
-BO
-270
100M
r--.
II
30
i5 so
-180
I I I I
POWER SUPPLY REJECTION
vs FREQUENCY
I II
=
-..;;;
Rp.TRIMMING POTENTIOMETER VALUE (Kn)
a:
I I
f-BAN,D
10
1S0
..........
TYPICAL DRIFT
::: -3
~ ...
LARGE SIGNAL
FREQUENCY RESPONSE
24
.........
'\..
-1
S -2
I
i
......
Rl '"' lMn; CL ;;; 30pF
Vee;;; ±16V
1004<
1
r+
~os
>~ 0
BO
ViNI" ~T~II
g
"
AMBIENT TEMPERATURE (OCI
GAIN-PHASE
-4<1B
3
-5
30
18.
III
.lll
III
-1dB
I
10
I
'"~
~ 2
UNITS ARE WARM!"
IN FREE AIR
I i
Rp
"-
a:
o
1\- BUF.Q2A/E
I I I
V'"
"i
Ii:
V
vV VV
V
~S··15
(KO)
SMALL SIGNAL
FREQUENCY RESPONSE
'"
V
~
o
\,.
.3
+1~~~~
~
~
f5
JII II
~ I~~~C
0 ,2
~
~
100nA
III I I
_55°C
e: 15
::>
OFFSET VOLTAGE
VS TEMPERATURE
OF REPRESENTATIVE UNITS
INPUT CURRENT VS
AMBIENT TEMPERATURE
OUTPUT VOLTAGE
vs LOAD RESISTANCE
I'\.
.~
100
lK
10K
TOOK
FREQUENCY 1Hz)
1M
10M
BUF·02 HIGH SPEED BI·FET BUFFERNOLTAGE FOLLOWER
TYPICAL PERFORMANCE CURVES
.
HIGH·SPEED SINGLE·SUPPLY AC BUFFER
VOLTAGE NOISE
VI FREQUENCY
,
III I
O.22~F
W!I~,s~
V,N
o---j 1--.........-1
T -26"C
"NEEDED FOR lOW IMPEDANCE AT HIGH
FREQUENCIES
II
'LOW AT VIN = 1.45Hz
1/t CORNER FREQUENe
'LOW AT Your '" 1.69Hz
-3dS
ASSUME VIN = 10V p.p SINE WAVE 15V PEAK)
THEN FULL POWER BANDWIDTH IS
APPROXIMATELY 800kHz .
,.
•
,.
'00
FREQUENCY (Hz)
'.K
DIFFERENTIAL INPUT INSTRUMENTATION AMPLIFIER
iii'
II:
TYPICAL APPLICATIONS
1&1
~
o...
...
oIL
BILATERAL CURRENT SOURCE
1&1
CI
R'
SOk.,
0.1%
INPUT
OUTPUT
INPUTS
; .. ;1
R'
&0.
Q,1%
=~ ~~N
0.'%
ID
OPTIONAL OFFSET NULLING CIRCUIT
SECOND-ORDER HIGH-PASS ACTIVE FILTER
~t----~V+
R'
'Ok
INPUT
.,.
o--j
0-----1
:>::---~OUTPUT
C2"
0.0011
~
IL
:;:)
R3-R4+R5
R1 .. R2
INPUT 0.0022
~
UI
II:
R2
'00k.,
V+
lOUT '"
Av"'~
...o~
'Ok
OUTPUT
--/I--.....--"M-=-j
R2
'Ok
-VALUES ARE FOR 10kHz CUTOFF. USE
METALIZEo POLYCARBONATE CAPACITORS
FOR GOOD TEMPERATURE STABILITY.
HIGH IMPEDANCE METER DRIVER
MAXIMUM OUTPUT ERROR
The Maximum Output Error specification combines errors
introduced by offset voltage, input bias current, gain, CMRR
and device output impedance. The speCification is 100%
tested for a given combination of source resistance, load
resistance and input voltages. The tlldious chore of
performing a worst case summation of component error
terms is not necessary.
The individual parameters of offset voltage, input current,
voltage gain and PSRR are also given.
INPUT
It should be noted that an error analysis may yield a figure
higher than the Maximum Output Error specification. This
is due to the potential cancellation of the effects of one
error source by another. In situations such as this, the
Maximum Output Error specification supersedes results
from any error analysis.
PAGE 8-11
PMI
BUF-03
VERY HIGH-SPEED
BUFFER/VOLTAGE FOLLOWER
®
FEATURES
•
•
•
•
•
•
•
•
•
•
Very High Slew Rate . . . . . . . . . . . . . . . . . . . .. 3OOVI/£S8C
Wide Bandwidth. . . . . . . . . . . . . . . . . . . . . . . . . .. 63MHz
Load Drive Current ..................... 70mA Peak
Easily Drives any Capacitive Load without Oscillation
High Input Resistance .................... 5 x 10 11 0
Low Output Resistance.. .. .. .. .. .. .. .. .. .. .. ... 20
Very Low Bias Current (Warmed Up) ........... 150pA
Low Offset Voltage. .. . .. .. . .. .. . . .. .. . .. . .. .. 2mV
Unity Gain .............................. O.997VN
Excellent Gain Linearity .................... 0.015%
in an open-loop circuit employing source followers and emitter followers, the BUF-03 utilizes a quasi-quad FET input
structure to optimize both speed and D.C. input characteristics. On-chip zener-zap trimming is used to achieve low offset
voltage while careful biasing throughout results in excellent
gain linearity over the full input voltage range ..
Applications for which the BUF-03 is well suited include highspeed line drivers, isolation amplifiers for driving reactive loads
and high-speed data conversion and sample-hold circuits.
PIN CONNECTIONS
N.C.
NULL~8,v+
GENERAL DESCRIPTION
The BUF-03 is the first very high-speed monolithic volta~e
follower. Featuring performance previously unobtainable in
a monolithic unit, it offers a combination of both exceptional
speed and excellent input/output specifications. Implemented
N,C. 2
TO-99 (J·Silffix)
6 OUTPUT
INPUT 3
5 NULL
•
V-leASE)
ORDERING INFORMATIONt
TA=2S"C
YosMAX
(mY)
PACKAGE
TO-99
I-PIN
6
6
15
15
BUF03AJ'
BUF03EJ
BUF03BJ'
BUF03FJ
OPERATING
TEMPERATURE
RANGE
OPTIONAL OFFSET NULLING CIRCUIT
MIL
COM
MIL
COM
~f--1>-----oV+
>--"------0 OUTPUT
INPUTQ--"""":'-!
• Also available with MIL-STD-8836 processing. To order add 1883 as a suffix to
the part number.
t All listed parts are available with 160 hour burn-in. See Ordering Information,
Section 2.
SIMPLIFIED SCHEMATIC
r--~--~-~~-~---------f--1~V+
OUTPUT
~----*-----~>----+---~-~~V_
PAGE 6-12
BUF·03 VERY HIGH·SPEED BUFFERIVOLTAGE FOLLOWER
ABSOLUTE MAXIMUM RATINGS (Note)
Supply Voltage (V + to V - ). . . . . . . . . . . . . . . . . . . . . . . . .. 36V
Internal Power Dissipation (Pd ) (see curves)
in still air, no heat sink. . . . . . . . . . . . . . . . . . . . . . . .. 1.05W
with heat sink, 8JA = 90 ·CIW . . .. . . . . . . . . . . . . . . .. 1.40W
Input Voltage (for Vs< ±18V, maximum input
voltage is equal to supply) . . .. . . . . . . . . . . . . . . . . .. ± 18V
Continuous Output Current. . . . . . . . . . . . . . . . . . . . . .. 70mA
Peak Output Current ............................. 100mA
Short Circuit Protection (Maximum Pd or Tj
not to be exceeded) ..... . . . . . . . . . .. Indefinite at 80mA
ELECTRICAL CHARACTERISTICS
at Vs
Maximum Junction Temperature (Tj ) .............. 175·C
Storage Temperature Range. . . . . . . . .. -65·C to + 175·C
Operating Temperature Range
BUF·03A,BUF·03B ................. -55·Cto +125·C
BUF·03E, BUF-03F ..................... O·C to + 70·C
Lead Temperature (soldering, 60 sec). . . . . . . . . . . . .. 300·C
DICE Junction Temperature (T j ) ••••••• -65· C to +175· C
NOTE: Absolute ratings apply to both DICE and packaged parts. unless
otherwise noted.
= ± 15V, TA = 25 ·C, T CHIP =75 ·C, device fully warmed up, unless otherwise noted. (Note 1)
BUF-03B/F
BUF-03A1E
PARAMETER
SYMBOL
CONDITIONS
Slew Rate
SR
RL " 2kll. CL = 50pF (Note 2)
Power Bandwidth
PBW
Y'N -IOVp_p• RL " 2kn
Bandwidth
BW
aV ,N = :;; 2Vp-p
Settling Time
ts
to 0.1%, ±10V step
Capacitive Load Capability
C LOAD
Propagation Delay
t.
Rise Time
MIN
TYP
220
300
MAX
MIN
TYP
180
250
II
0')
MAX
UNITS
Ii'
IL
:J
AC SPECIFICATIONS
ID
VI.sec
9
MHz
63
50
MHz
iii'
II:
W
~
nsec
0
No Oscillations
"F
nsec
0
t,
aV=O.5V
nsec
CJ
Wide Band Input Noise Voltage
Vn
DC to 50MHz
Input Noise Voltage
Density
en
f= 10kHz
90
100
350
400
,N RMS
50
60
nVIJFfZ
18
Input Resistance
RIN
Voltage Gain (VIN = ± 10V)
AvO
Maximum Output Error
NL
OUTerror
Rs ,,20k!!
0
~
150
0.9960
0.9975
0.9940
0.9970
0.9945
0.9960
0.9930
0.9950
RL"lkll
0.9925
0.9945
0.9905
0.9930
0.015
0.023
0.017
0.03
0.023
0.015
0.03
40
60
50
85
No Load
Ro
Offset Voltage Nulling Range
:Nos
VIV
0.013
Vs= ±6V to ±18V
pA
II
VIN = ±7V. RL"lkll
PSRR
IL(PK)
700
VIN = ±IOV. RL ,,2kll
ISY
Peak Load Current
180
mV
4x10"
RL ,,2kll
Power Supply Rejection Ratio
Output Resistance
400
RL"IOkll
VIN = + 10V, OV. -IOV
Rs =0 to 20kll
RL~2kn in all combinations
W
15
6
5x10'1
Supply Current
%F.S.
----_._-mV
._-----------_._- - - - - - - 0.10
0.71
0.15
18
22
19
70
70
±80
±80
_.._-1.42
-_.--- . --25
.- -
mVIV
~-
---
mA
----mA
---_._-----
-----_ .. -------- Rp"lkll
II
---
mV
~--.--.------
Input Voltage Range
(Reduced Accuracy)
W
;!
;.J
II:
VOS
Input Bias Current
Nonlinearity (Note 3)
IL
III
DC SPECIFICATIONS
Input Offset Voltage
....I
....I
IVR
±11.5
±11.5
V
- ---_._------_.
NOTES:
I. The BUF·03 package thermal resistance, in still air,ls 145·Ctw (45·Ctw
junction to case, 100 ·Ctw case to ambient). The chip temperature of 75·C
Is achieved by reducing the case to ambient thermal resistance to 45·CIW.
An inexpensive heat sink, such as the Thermalloy 2271 or 6203, is rec·
om mended for use in this application. In addition, if the device Is
operated in a forced·air environment, or is attached to a PC board which
has good thermal conductivity, the chip temperature may be further
reduced.
If no heat sinking is used, the chip temperature lin still air) may exceed
lOS ·C. The effect of this elevated temDerature Will be to Increase the in'
put bias current by a factor of eight; increase the Vos specification by
TCVos x 30·C, and reduce device speed by 10'10.
2. Guaranteed by design.
3. Nonlinearity is computed using linear regression techniques with data
from five points (e.g., -10V, -5V, OV, +5V, and +IOV for ±IOV fullscale linearity).
PAGE 6-13
IL
IL
:J
ID
BUF·03 VERY HIGH·SPEED BUFFERNOLTAGE FOLLOWER
ELECTRICAL CHARACTERISTICS at Vs=± t5V, -55· C:STAS+125· C, T CHIP(MAX) =+165· C, device fully warmed-up,
unless otherwise noted. (Note 1)
BUF·03B
BUF·03A
PARAMETER
SYMBOL
CONDITIONS
Slew Rate
SR
RL " 2kll. C L = 50pF
Input Offset Voltage
Vos
Rs:;;2kll
MIN
TYP
MIN
MAX
260
10
TCVos
Rs:;; 2kll (Nole 2)
50
Input Bias Current
Is
TA = +125'C
25
Voltage Gain
Avo
R L "2kn. V ,N =±10V
100
UNITS
._-------
220
20
Average Input Offset Voltage
Drift
MAX
TYP
VlJlsec
35
mV
170
,M'C
-- ---_._._-------
90
--.--.--~--.--.-.------.--------~--
30
75
---~-----.---.---
0.9920
Gain Drift with Temperature
0.9955
nA
_.. - - - - - - - - - - - - - - - _ . _
-
0.9902
5
Power Supply Rejection Ratio
PSRR
Vs= ±7V to ±15V
Supply Current
ISY
TA= +125'C
90
0.9942
VIV
8
ppml'C
0.15
1.26
0.20
0.24
mVIV
t7
21
18
24
mA
ELECTRICAL CHARACTERISTICS at Vs= ±15V, O·C:S TA:S +70·C, TCHIP (MAX) = + 120· C, device fully warmed-up,
unless otherwise noted.
BUF·03F
BUF·03E
PARAMETER
SYMBOL
CONDITIONS
Slew Rate
SR
RL ,,2kll
Input Offset Voltage
Vos
Rs:;;2kll. C L =50pF
Average Input Offset Voltage
Drift
TCVos
Rs:;;2kll (Note 2)
Input Bias Current
Is
TA =+70'C
Voltage Gain (V,N = ± 10V)
Avo
RL ,,2kll
Power Supply Rejection Ratio
PSRR
Vs= ±7V to ±15V
Supply Current
ISY
TA=+70'C
MIN
TYP
MIN
MAX
TYP
14
0.9935
Gain Drift with Temperature
MAX
240
260
40
90
1.5
5.0
0.9958
0.9918
28
mV
80
150
.VI·C
1.8
8.0
0.9946
nA
VIV
8
5
UNITS
VI.sec
ppml'C
0.12
1.0
0.16
1.78
mVIV
18
22
19
25
mA
NOTES:
1. In order to operate the device at an ambient temperature of + 1250 C, more
extensive heat sinking must be used to ensure that the chip temperature
never exceeds the absolute maximum of + 1750 C. The chip temperature of
+ 1650 C is achieved by reducing the case to ambient thermal resistance to
ao'CIW (e.g., Thermalioy 2227).
2. Guaranteed by design.
PAGE 6-14
aUF-03 VERY HIGH SPEED aUFFERIVOLTAGE FOLLOWER
DICE CHARACTERISTICS
1. NULL
3. INPUT
4. NEGATIVE SUPPLY
5. NULL
6. OUTPUT
7. POSITIVE SUPPLY
II
DIE SIZE 0.070 X 0.048 Inch
iii"
Refer to Section 2 for eddltlonal DICE Informalton
lie
W
~....I
ELECTRICAL CHARACTERISTICS at Tj = 25° C, Vs = ± 15V, unless otherwise noted.
BUF-G3N
PARAMETER
SYMBOL
CONDITIONS
Input Offset Voltage
Vas
Rs ,,20kO
Slew Rate (Note 1 )
SR
RL 2 2kO. C L = 50pF
Voltage Gain
Ava
RL 210kO, V'N=±IOV
Power Supply Rejection Ratio
PSRR
Vs =±6Vto±18V
Supply Current
ISY
No Load
....I
o
BUF-03G
I&.
W
LIMIT
LIMIT
UNITS
6
15
mVMAX
250
180
V/p.soc MIN
0.9980
0.9940
VIVMIN
~
0.71
1.42
mVIV MAX
III
lie
22
25
mAMAX
CI
~
;.,
o
W
II:
:::»
II
TYPICAL ELECTRICAL CHARACTERISTICS at VS =
± 15V, Tj = 25° C, unless otherwise noted.
BUF-G3N
PARAMETER
SYMBOL
Peak Load Current
Input Bias Current
BUF-03G
TYPICAL
TYPICAL
UNITS
IL(PK)
70
70
mA
I.
40
80
pA
5Xl0"
5Xl0"
0
CONDITIONS
Input Resistance
R'N
Output Resistance
Ra
Offset Voltage Nulling Range
aVas
Input Voltage Range
(Reduced Accuracyl
IVR
Power Bandwidth
PBW
V'N= 10Vp-p, RL 22kO
Bandwidth
BW
"V'N" 2Vp-p
Settling· Time
ts
To 0.1%, ±IOV step
90
100
capacitive Load Capacity
C LOAD
No Oscillations
Propagation Delay
td
Rise Time
t,
Rp21kO
2
0
±80
±80
mV
±11.5
±11.5
V
9
8
MHz
63
55
MHz
7
Vn
DCto50MHz
Input Noise Voltage Density
en
1= 10kHz
ns
ns
"V'N= 0.5V
Wide Band Input Noise Voltage
ns
p.F
NOTE:
I. Sample tested.
PAGE 6-15
350
400
P.VRMS
50
60
nV/yHz
BUF·03 VERY HIGH·SPEED BUFFERNOLTAGE FOLLOWER
TYPICAL PERFORMANCE CURVES
SLEW RATEvs
CAPACITIVE LOAD
't
500
I
TA = 25"C
TA' 25"C
±15V
400
Vs"
Vs = ±15V
J
TA" zs"c
SR = 3OOV//lssC
1BO
-GAIN
_
CL -lOpF
./
-
."
1\
I I III
240
GAIN
CL = 5Op~
III
i'..
"
LARGE SIGNAL
FREQUENCY RESPONSE
GAIN AND PHASE RESPONSE
vs FREQUENCY
1
1111
-2
PHASE
CL = lOpF
70
'\.
-6
50
100
-B
150
200
300
400 600
700
-40
46810204080100
FREQUENCY (MHzl
1000
CAPACITIVE LOAD (pF)
MAXIMUM POWER
DISSIPATION vs
AMBIENT TEMPERATURE
r\
\
\
INPUT BIAS CURRENT vs
TEMPERATURE (WARMED·UP)
AMBIENT HEAT
51
SINK
eJA = 76"C/W
" 'b( \\
46"C/W CASE TO
AMBIENT HEAT SINK
eJA
ioor J
0.2
25
50
75
"
j-tci
I--- _
NO HEAT SINK
IN STILL AIR
100
125
_
1SO
I-176 200
-
-60
-80
-15
-10
INPUT BIAS CURRENT
vs INPUT VOLTAGE
360
WARMED UP
.....
~
0
5
10
340
~ 10-
-
Vs = ±15V
eJA" 9DO cIW
-6
-
f-"'"
NEGATIVE
f'.. ...........
r- r-
-202
6
INPUT VOLTAGE WOLTS)
-0.70
GAIN ERROR
vs TEMPERATURE
r-1,....,-,....,....,.-,--.--r--rT""T"""r-,....,
-0.60
H--+-+++-+ RL = 1kG +-+::!:;........
..........
POSITIVE
........
280
80
-10
15
SLEW RATE
vs TEMPERATURE
TA = 25"C
..... I---" ~
../
-6
..-
Y
OUTPUT VOLTAGE (VOL 'fSI
200
VS. t15V
AJA = 9rY'clW
I
I
SAFE OPERATING
AREA 101'
Vs" ±15V
'fA "2SOC
eJA a 9lrCIW
AMBIENT TEMPERATURE (OCI
~
~
,.,..,/
3tr'C/W CASE TO
\
100
./
60
\
I--
4060
FREQUENCV (MHz)
lDO
80
1.2
461020
OUTPUT CURRENT
vs OUTPUT VOLTAGE
1.4
lBO
./
.....
-4
10
240
-50
-as
0
25
50
""-
75
TEMPERATURE (OC)
PAGE 6-16
"-
""
100
125
HH--+-+-+++-+- Vs = ±15V
-o.l°·HH--+-+-++++V~~"=~~%1W
-
o~~~~~~~~~~~~~
-50
-25
25
50
75
TEMPERATURE {OCI
100
125
BUF-03 VERY HIGH SPEED BUFFER/VOLTAGE FOLLOWER
TYPICAL PERFORMANCE CURVES
O.OS
50
r- t- RL = 600D.j r- r-
TA = 25C C
Vs = t15V
0."
1/
V
0.02
/'
RLi?
H--t::
AL",'Okn"-
-so
±6
±s
±7
±9
,.
17
1.
,,/
./
/
V
I
±9
I--
-6
'5
-50
±24
f80
70
r-.... ""'-
r\.
50
-25
0
25
50
TEMPERATURE
l--
V
)-,/~
V
V / 'V
V
./
RISE
FALL
/
V
150
100
-5
'7
t.9
-1t
!
13
SUPPLY VOLTAGE (VOLTS)
=1_15~=125"~
-
75
rei
100
125
-'5
PAGE 6-17
'0
-2
0
2
INPUT VOLTAGE (VOL TSI
II
-VIN
r-I'"H
VIN "'+lOV
-TOV
III
1
'r1ar1cIIRe!,T
,0 jROiNDt - 20
40
60
80
100
TIME FROM SHORT (SECONDS)
SLEW RATE
350
TA = 2SOC
Vs
ITA
TA = 25°C
Vs = ±1SV
0JA = 9f1'C/W
r'\~
r-
SLEW RATE VB
SUPPLY VOLTAGE
300
"'!""
OUTPUT SHORT CIRCUIT
CURRENT VB TIME
80
tT2
±TS
±TS
±2l
SUPPLY VOLTAGE I±VOlTS)
R~'
/
I
.
I
'7
15
f.--"
......
RL I' 2Oj' 7
-'0
'6
±6
I
.....
Vs"' '15V
HJA ., 9O"CIW
,. ~
,. "'- t'-..... .......
I
1.
'0
-2026
INPUT VOLTAGE (VOLTS)
2'
20
7
son
-300
-6
SUPPLY CURRENT
VB TEMPERATURE
I
Rl =
'00
2OOn'~
AL =
./
/
SUPPLY CURRENT
21
IT
I
I
200
-200
V
VB SUPPLY VOLTAGE
20 -TA = 25°C
300
-100
VV
-'0
,.'0
FULL SCALE (VOLTSI
I~ V
~ ~L''''''''_
V r/ r
-30
0.00
.6
....::; ~
-10
~
I- 1-'-
RL = 2kn
10
~
f.--" ~
0.01
V
1.11/
6< V ./
RL = lkn
30
/
V
r- ~s. ~'5VI
TA" 25°C
V
0.03
GAIN ERROR VB
INPUT VOLTAGE
GAIN ERROR VB
INPUT VOLTAGE
NON·LINEARITY VB
FULL·SCALE VOLTAGE
120
II
BUF-03 VERY HIGH SPEED BUFFERIVOLTAGE FOLLOWER
APPLICATIONS INFORMATION
HIGH SPEED 6-BIT AID BUFFER
OPERATING THE BUF·03 AT REDUCED
POWER SUPPLIES
+15V
--6V
24 N.C.
In most video applications the signal levels are slgnifl·
cantly lower than the 20V peak·to·peak capability of the
BUF·03. This suggests operating the BUF·03 at reduced
power supplies; for example, at ± BV supplies ± 2V
signals can be handled. The obvious advantage of reduced
supplies is the accompanying decrease in power dlssipa·
tion: from a typical 540 mW (= 30V x 18 mAl to 195 mW
(=12V x 1B.2 mAl at ± BV. At lower supply voltages heat
sinking is no longer necessary. However, as shown on the
slew rate vs supply voltage curve, slew rate does degrade
at lower supplies. This occurs because of higher Internal
node capacitances at lower voltages and because of the
slightly decreased operating current.
HIGH-SPEED SAMPLE/HOLD AMPLIFIER
1 -__"N~--+--"""~------------<>-15V
ANALOG
INPUT
±5V
+1SV
0-----,
ANALOG
OUTPUT
o------.---------1r----.-----,
LOGIC
IN
HOLD -7V
R'
DIGITAL _
150
GROUND -
ANALOG
":' GROUND
tOO
100
43D
-15V
o---,.--+-----------~
PAGE 8-18
COMPARATORS
COMPARATORS
INDEX
PRODUCT
TITLE
CMP-01
CMP-02
CMP-04
CMP-05
PM 139/239/339
PM139A1239A1339A
Fast Precision Comparator .••••••••••••.•.••••••.•.•••••.•••••.•.••..•••••..•••.••••••••••• 7-5
Low Input Current Precision Comparator .•.•....•.•.•.•••.•....••...•...•.•.•••.•.••••••••• 7-14
Low Power Precision Quad Comparator ..••.••••. ; ...••••••..•.••••• : •.••••.••.....•••••••• 7-22
High-Speed Precision Comparator With Latch Circuit ...••••..•••••••.••••••.•.••.•••••••••• 7-30
PAGE
Low Power Quad Voltage Comparator ...................................................... 7-37
PAGE 7-2
INTRODUCTION
A comparator provides a logic output indicating the
amplitude relationship between two analog signal inputs.
When selecting a comparator, certain device parameters
must be considered for proper design and application.
These parameters are:
Vos (Input Offset Voltage)
Response Time
Slew Rate and Response Time
PSRR (Power Supply Rejection)
18 (Input Bias Current)
CMVR (Common-Mode Voltage Range)
Output Configuration
Voltage Gain
voltage variation will be required at the input to effect a
change in the output state. This minimum sensitivity will be
determined from the voltage gain of the comparator. The
relationship is as follows:
AV1N(MIN)
=
!No
Tv
The quantity AVo which is the difference between the high
and low state of the output is generally chosen to be 2.5V to
insure the matching of the comparator with the TTL load.
Precision Monolithic's comparator product line has expanded to five devices.
The Input offset voltage (Vos) for a comparator should be as
small as possible because In a high gain circuit it is the
dominating factor that determines the exact threshold level.
For this reason, comparators should be nulled or a Precision Comparator used so that the input differential voltage
is as close to zero as practical when the output is at the
logic switching threshold.
The voltage gain (Av) determines the sensitivity and
threshold accuracy of a comparator. For the Ideal comparator, the gain could be considered infinite; and an extremely small voltage applied between the two inputs will
cause a change in the output. In practice, some minimum
The CMP01 is a fast precision comparator with low offset
voltage. The CMP02 offers the CMP01's offset voltage performance along with lower input bias currents.
The quad CMP04 offers both low power and low offset
voltages. Existing "139" type applications can be upgraded
by the pin compatible CMP04. The PM139/239/339 devices
provide equal performance to "13912391339" type comparators.
The CMP05 brings together superior input specifications
with very fast response times. This combination makes the
CMP05 the Ideal choice In high-accuracy 10 and 12-bit data
systems.
•
III
a:
o
!ca:
:::::I!
o
U
PAGE 7-3
cur and still be recognized and held at the output. Specified
for a given input voltage step size and overdrive.
COMPARATOR DEFINITIONS
COMMON MODE REJECTION RATIO (CMRR)
The ratio, expressed in dB, of the change in the arithmetic
mean of voltage present at the device inputs with respect to
the device reference ground (<1 common mode voltage) to
the change in input offset voltage (<1Vo s).
CMRR (dB) = 2010g
(<1CMVI~Vos)
OFFSET VOLTAGE ADJUSTMENT RANGE
The change in offset voltage that can be obtained by adjusting a specified external nulling potentiometer.
OUTPUT LEAKAGE CURRENT (lLEAKl
COMMON-MODE VOLTAGE RANGE (CMVR)
The range of common mode voltage on the input terminals
for which operation within specifications is assured.
The current into the output terminal with a given output
voltage and input drive equal to or greater than a specified
value.
OUTPUT SINK CURRENT (lsINKl
DIFFERENTIAL INPUT RESISTANCE (R 1N)
The resistance looking into either input terminal with the
other grounded.
The maximum negative current that can be delivered by the
comparator.
OVERDRIVE
DIFFERENTIAL INPUT VOLTAGE
The range of voltage between the input terminals for which
operation within specifications Is assured.
INPUT BIAS CURRENT (Is)
The input step voltage of specified size drives the comparator from some initial input voltage to an input level just
barely in excess of that required to bring the output from its
high or low state to the logic threshold voltage. This excess
is defined as the voltage overdrive.
The average of the two input currents, with the inputs tied
together.
POSITIVE OUTPUT VOLTAGE (VOH)
INPUT OFFSET CURRENT (loS>
The high output voltage level with a given load and input
drive equal to or greater than a specified value.
The difference in the currents into the two input terminals
when the output is within a specified voltage range.
POWER SUPPLY REJECTION RATIO (PSRR)
INPUT OFFSET VOLTAGE (VoS>
The ratio of the maximum change in input offset voltage to
the specified change in power supply voltage.
The voltage between the input terminals when the output is
within a speCified voltage range.
INPUT SLEW RATE
The maximum rate of change in differential andlor common·
mode input voltage which the input stage can follow. The
comparator's total response time for any input voltage step
with arbitrary overdrive is equal to the sum of the response
time for the small signal (100mV) step with the same overdrive, plus the slewing time (= initial differential input
voltage divided by input slew rate).
RESPONSE TIME (t,)
The interval between the application of an input step function and the time when the output crosses the logic
threshold voltage. Logic threshold is defined as the voltage
at the output of the comparator at which the loading logic
circuitry changes its digital state, or, as 1.4V when the
loading logic circuitry is not used.
SATURATION VOLTAGE (VSAT)
The low output voltage level with a given sink current and
drive less than or equal to a specified value.
INPUT TO OUTPUT HIGH PROPAGATION DELAY (tpd+)
The time measured between the Input signal's Vos crossing
and the output voltage's 50% low-to-high transition point.
Specified for given input voltage step size and overdrive.
STROBE CURRENT (ISTB)
The current out of the strobe terminal when it is active.
STROBED OUTPUT VOLTAGE (VO(STB~
INPUT TO OUTPUT LOW PROPAGATION DELAY (tpd-)
The time measured between the input signal's Vos crossing
and the output voltage's 50% high-to-Iow transition point.
Specified for a given input voltage step size and overdrive.
LATCH DISABLE PROPAGATION DELAY (tLPD)
The time measured between the 50% transition pOints of
the latch enable signal's high-to-Iow transition and the output signal's low-to-high or high-to-Iow transition point.
The DC output voltage - independent of input conditions
- with the strobe function active.
SUPPLY CURRENTS
The currents required from the positive or negative supplies
to operate the comparator with no output load. The currents
will vary with input voltage, but are maximum when the output is low, and, therefore, are specified with the input drive
less than or equal to a given value.
LATCH SET-UP TIME (ts>
VOLTAGE GAIN (Av)
The minimum time required before the low-to-high latch
enable signal transition that an input signal change can oc-
The ratio of the change in output voltage (over a specified
range) to the change in input voltage producing it.
PAGE 7-4
CMP-Ol
PMI
FAST PRECISION COM PARATOR
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
Fa.t Re.pon.e Time .• 110n. Typical, 180n. Maximum
High Input Slew Rate •..•........•.•......... 92V1 p..
Low Offset Voltage •.. 0.3mV Typical, 0.8mV Maximum
Low Offset Current •..•.• 4nA Typical, 2SnA Maximum
Low Offlet Drift •.••••...•..•..•.. 1.0"V/oC,30pA/oC
Standard Power.Supplles ..••.........•. ±SV to ±18V
Guaranteed OperaUon from Single +SV Supply
No Pull-Up Re.h/tor Required for TTL Drive
Wired OR Capablilty
Fit. 111, 106. 710 Sockets
Easy Off.et Nulling .•.••.... Single 2kO Potentiometer
Easy to U.e ..•••....•.•....... Free from Oscillation.
Diode process. It features fast response time to both large
and small input signals. while maintaining excellent input
characteristics. The CMP-01 is capable of operating over a
wide range of supply voltages including single ended 5 volt
supply. The large output current sinking and high output
voltage capability assure good application flexibility, while
the combination of fast response, high accuracy, and freedom from oscillation assure performance in precision level
detectors and 12 and 13-bit AID converters. The CMP-01 is
pin-compatible to earlier 111, 106, and 710 types. For applications requiring lower input offset and bias currents, refer
to the CMP-02 data sheet.
PIN CONNECTIONS
•
GENERAL DESCRIPTION
v+
The CMP-01 is a monolithic fast precision voltage comparator using an advanced compatible NPN-Schottky Barrier
PACKAGE
HERMETIC
vos
(mV)
O.S
2.S
PLASTIC
'DIP
BPin
OPERATING
TEMPERATURE
RANGE
CMP01EP
COM
CMP01CP
COM
DIP
TO-98
B Pin
BPln
14 Pin
CMP01J'
CMP01Z'
CMP01Y'
CMP01EJ
CMP01EZ
CMP01EY
CMP01BJ'
CMPOlBZ'
CMP01BY'
CMP01CJ
CMP01CZ
CMPOlCY
+ONG:?~;:l\O:T~LANCE
II:
~
II:
::E
-ONV.~LANCE
•
ORDERING INFORMATIONt
+25°C
III
o
o
U
v- (CASEI
TO-99
(J-Suffix)
14-PIN HERMETIC DIP
(Y-Sufflx)
MIL
8-PIN HERMETIC MINI-DIP
(Z-Suffix)
MIL
'Also available with MIL-STO-SS3B processing. To order add/883 as a suffix to
the part number.
t All listed parts are available with 160 hour burn-in. See Ordering Information.
Section 2.
EPOXY B MINI-DIP
(P-Suffix)
SIMPLIFIED SCHEMATIC
V+~----1-----~----~----~-----+-----+-----'----~----~~--~
INVERTING
INPUT
<>---+--t:"
soo
V-~----+-----4---~
PAGE 7-5
CMP-01 FAST PRECISION COMPARATOR
ABSOLUTE MAXIMUM RATINGS (Note 2)
Total Supply Voltage, V+ to V- .•.....•.•..•..•••..• 36V
Output to Ground .......................... -5V to +32V
Output to Negative Supply Voltage •.•.•••••...••••• 50V
Ground to Negative Supply Voltage ••.••••....••••. 30V
Positive Supply Voltage to Ground ••...•...•••••• + 30V
Positive Supply Voltage to Offset Null.. • •. ••. .•.. 0 to 2V
Power Dissipation (See Note) .. , •.•.•••..••...•• 500mW
Differential Input Voltage ......................... ±11V
Input Voltage (Vs = ±15V) .•••..•.••.•••••••..••.•• ±15V
Output Sink Current (Continuous Operation) ...••• 75mA
Operating Temperature Range CMP-01, CMP-01B ••...•••.......••• -55°C to +125°C
CMP-01E, CMP-01C .................... O°C to +70°C
DICE Junction Temperature (TI) .•••.•. -65°C to +150°C
Storage Temperature Range •...•.....• -65°C to +150°C
ELECTRICAL CHARACTERISTICS
at Vs =
±
Lead Temperature (Soldering, 60 sec) •.•••..••..• 300°C
Output Short Circuit Duration - to ground •••• Indefinite
to V+ .......... 1 Minute
NOTES:
1. Maximum package power dissipation vs. ambient temperature.
Derate Above MlIXlmum
Maximum Ambient
Temperature lor Rating Ambient Temperatura
Package Type
TO-99 (J) - 8-Pin
Dual-In-Line (V) 14-Pln
80°C
7.1mW/OC
100°C
10.0mW/OC
Epoxy Mini-Dip (P) S-Pin
36°C
5.6mW/oC
Hermetic Mini-Dip (Z) S-Pin
75'C
6.7mW/oC
2.
Absolute ratings apply to both DICE and packaged parts unless otherwise
noted.
15V, T A = 25°C, unless otherwise noted.
CMP-01
CMP-01E
PARAMETER
SYMBOL CONDITIONS
Input Offset Voltage
Vos
Rs" 5kll (Note 1)
Input Offset Current
los
(Note 1)
Input Bias Current
Ie
Differential Input
Resistance
R'N
(Note 2)
3.0
14
1.0
10
mil
Voltage Gain
Av
Vo= O.4V to 2.4V (Notes 1 and 2)
200
500
100
500
VlmV
Response Time
MIN
CMP01B
CMP01C
TYP
MAX
0.3
0.8
MIN
TYP
MAX
UNITS
0.4
2.8
mV
80
nA
900
nA
25
350
100mV step. SmV overdrive
No Load (No Pull-Up) (Note 3)
5kllto 5V (Pull-Up)
TTL Fan-Out = 4, No Pull-Up
110
110
110
5V Step SmV Overdrive
No Load (No Pull· Up)
5kll to 5V (Pull-Up)
TTL Fan-Out = 4. No Pull-Up
160
160
160
t,
Input Slew Rate
600
400
180
110
110
110
180
ns
160
160
160
92
92
VI","
Input Voltage Range
CMVR
±12.5
±13.0
±12.5
±13.0
V
Common Mode
Rejection Ratio
CMRR
'94
110
90
110
dB
Power Supply
Rejection Ratio
PSRR
5V SVs +S18V,
-18V :>Vs_ SlV
74
98
dB
Positive Output
Voltage
VO H
Y,N ,,3mV, 10= 320,.11
Y,N ,,3mV, 10= 240~A
Y,N ,,3mV, 10= OmA
2.4
2.4
3.4
4.8
V
Saturation Voltage
VOL
Y,N :>-10mV, I slnk :>6.4mA
Y,N :>-10mV, I.ink :512mA(CMp-ol only)
80
100
2.4
3.2
2.4
4.8
V1N s~10mV.lsink= OA
0.16
0.3
0.36
+ 30V
0.4
0.45
0.5
0.16
0.31
0.4
0.45
0.03
2.0
0.05
8.0
~A
5.6
8.0
5.6
8.5
mA
V
Output leakage Current
I LEAK
V,N " 10mV, Vo =
Positive Supply Current
1+
Y,N :>-10mV
Negative Supply Current
1-
Y,N :>-10mV
1.3
2.2
1.3
2.2
mA
Power Dissipation
Pd
Y,N :>-10mV
103
153
103
161
mW
Offset Voltage
Adjustment Range
Nulling Pot'" 2kll
±5
NOTES:
1. These Parameters are specified as the maximum values required to drive
the output between the logiC levels of 0.4V and 2.4V with a lkilioad tied to
+5V; thus, these parameters define an error band which takes Into account
the worst case effects of voltage gain and Input impedance.
2. Guaranteed by design.
3. Sample tested.
PAGE 7-6
±5
mV
CMp·01 FAST PRECISION COMPARATOR
ELECTRICAL CHARACTERISTICS
at Vs+ = 5V, V s - = OV, TA = 25°C, unless otherwise noted.
CMP01B
CMP01C
CMP·01
CMp·01E
PARAMETER
SYMBOL CONDITIONS
Input Offset Voltage
Vos
Rs:5 Skll (Note 1)
Input Offset Current
los
(Note 1)
Input Bias Current
Ie
Voltage Gain
Av
Response Ti me
t,
MIN
TYP
MAX
0.4
1.5
MIN
TYP
MAX
UNITS
0.5
3.5
mV
65
nA
21
250
Vo = O.4V to 2.4V (Notes 1 and 2)
300
500
720
nA
50
&0
V/mV
150
150
150
150
ns
100mV Step, SmV Overdrive
SkU to 5V (Pull-Up)
TTL Fan-Out = 4, 5kll to 5V
(Pull-Up)
Input Voltage Range
CMVR
1.7-3.8
3.5
1.7-3.8
3.5
Saturation Voltage
VOL
V IN :::::; -10mV, Isink ::;6.4mA
1.8
0.3
0.45
0.3
0.45
V
Positive Supply Current
1+
VIN s;-10mV
2.3
3.2
2.4
3.8
mA
Power Dissipation
Pd
VIN :=;-10mV
11.5
16.0
12.0
19.0
mW
ELECTRICAL CHARACTERISTICS
1.8
V
•
9a.
at Vs= ±15V, -55°C:5 TA :5125°C, unless otherwise noted.
:=!!
()
CMp·01B
CMP·01
PARAMETER
SYMBOL CONDITIONS
Input Offset Voltage
Vos
MIN
Rs:5 5kU (Note 1)
Vs_ = 5V, Vs_ = OV (Note 1)
TYP
MAX
0.5
0.6
1.6
2.8
MIN
TYP
MAX
UNITS
0.5
0.6
3.5
4.3
mV
Input Offset Current
Average Input Offset
Current Drift
0(
a.
TCVos
TCVOS n
Rs= SOil
loS
TA = +12SoC (Note 1)
TA=-SSoC (Note 1)
TClos
25
45
+25°C ::::=TA :s:+125°C
Ie
TA = +125°C
TA=-SSoC
Voltage Gain
Av
Vo = O.4V to 2.4V (Notes 1 and 2)
Response Time
t,
1OOmV Step, SmV Overdrive
TA=+12SoC No Load
TA = -SsoC, No Load
1.8
1.2
1.5
1.0
330
SSO
100
"V/oC
80
120
12
40
12
3S
-55°C ::;TA ::;;+25°C
Input Bias Current
600
1400
340
4S0
70
soo
pA/oC
900
1200
500
220
220
100
100
nA
nA
V/mV
ns
Input Voltage Range
CMVR
±12.0
±13.0
±12.0
±13.3
V
Common Mode
Rejection Ratio
CMRR
88
106
86
108
dB
5V :::::::VS+ s15V, -15V :s:Vs_ ::s;OV
7S
96
70
88
dB
2.4
Power Supply
Rejection Ratio
~
II:
Ave,age Input Offset
Voltage Drift
Without External Trim
With External Trim
en
0
II:
PSRR
Positive Output Voltage
V OH
VIN ,,4mV, 10= 200pA
Saturation Voltage
VOL
V 1N :5-10mV, Isink = 0
V 1N :5-10mV, I sink = 6.4mA
3.0
0.20
0.32
NOTES:
3.2
0.17
0.31
V
0.4
O.S
V
+5V: thus, these parameters define an error band which takes into account
the worst case effects of voltage gain and Input impedance.
1. These Parameters are specified as the maximum values required to drive
the output between the logic levels of O.4V and 2.4V with a 1kllioad tied to
2.4
0.4
0.5
2. Guaranteed by design.
PAGE 7·7
:=!!
0
()
CMP-01 FAST PRECllIlON COMPARATOR
ELECTRICAL CMARACTERISTICS
at
vs;
±15V, O'C" TA ,,70'C, unless otherwise noted,
CMP-01E
PARAMETER
SYMBOL CONDITIONS
Input Offset Voltage
Vos
MIN
CMP-01C
TYP
MAX
Rs,,5kll (Note 1)
Vs' = 5V, Vs. = OV (Note 1)
0.4
0.5
1.4
2.4
TCVOS
TCVosn
RS = son
1.5
1.0
los
TA = +70'C (Note 1)
TA= O'C (Note 1)
4
5
TClos
+25C>C ::::;TA :s+70°C
DoC ::::::TA :s+25°C
12
35
Input Bias Current
la
TA = +70°C
TA=O'C
Voltage Gain
Av
Vo = 0.4V to 2.4V (Notes 1 and 2)
Response Time
t,
TA = +70 0 C, No Load
MIN
TYP
MAX
UNITS
0.5
0.6
3.5
4.3
mV
Average Input Offset
Voltage Drift
Without External Trim
With External Trim
Input Offset Current
Average Input Offset
Current Drift
330
400
100
1.B
1.2
25
45
6
",VI'C
80
120
12
40
340
450
600
950
70
500
nA
pA/'C
900
1200
nA
500
V/mV
220
100
ns
100mV Step, 5mV Overdrive
220
100
TA = O'C, No Load
Input Voltage Range
CMVR
±12.0
±13.3
±12.0
±13.3
V
Common Mode
Rejection Ratio
CMRR
90
108
86
108
dB
77
98
70
88
dB
Power Supply
PSRR
5V ,;Vs.'; 15V, -15V ,; VS_ ';OV
Positive Output Voltage
VOH
V'N '" 4mV, 10= 200",A
Saturation Voltage
VSAT
Rejection Ratio
2.4
3.2
0.17
0.3
V 1N :5 -10mV, 'sink = 0
VIN :::;-10mV, 'sink = 6.4rnA
NOTES:
1. These Parameters are specified 8S the maximum values required to drive
the output between the logic levels of 0.4V and 2.4V with a 1kll load tied to
2.4
0.4
0.5
V
3.2
0.17
0.31
0.4
0.5
V
+5V; thus. 'these parameters define an error band which takes into accQunt
the worst case effects of voltage gain and input Impedance.
2. Guaranteed by design.
PAGE 7-8
CMP-01 FAST PRECISION COMPARATOR
DICE CHARACTERISTICS
1. GROUND
NON-INVERTING INPUT
INVERTING INPUT
NEGATIVE SUPPLY
BALANCE
BALANCE
OUTPUT
POSITIVE SUPPLY
2.
3.
4.
5.
6.
7.
8.
DIE SIZE
0.065 x 0.042 Inch
•
Refer 10 Section 2 for additional DICE Informallon •
ELECTRICAL CHARACTERISTICS for Vs = ±15V at 25° C.
PARAMETER
SYMBOL CONDITIONS
Input Offset Voltage
Vos
CMP-01N
CMP-01GR
LIMIT
LIMIT
0.8
2.8
mVMAX
nAMAX
RSS5kO (Note 1)
Input Offset Current
los
25
80
Input Bias Current
Is
600
900
Differential Input Resistance
RIN
3.0
1.0
(Note 2)
UNITS
nAMAX
MOMIN
Input Voltage Range
IVR
±12.5
±12.5
Common Mode Rejection Ratio
CMRR
VCM=±CMVR
94
90
dBMIN
Power Supply Rejection Ratio
PSRR
5VSVs+S 18V
-18V S Vs -S OV
80
74
dBMIN
Positive Output Voltage
VOH
V IN ",3mV, 10=320~A
V 1N '" 3mV, 10 = 240~A
Saturation Voltage
VOL
ISink = S.4mA
0.45
0.45
Output Leakage Current
I LEAK
V1N '" 10mV, Vo = 30V
4.0
8.0
~AMAX
mAMAX
2.4
2.4
VMIN
VMIN
V MAX
Positive Supply Current
1+
V 1N S-l0mV
8.0
8.5
Nagative Supply Current
1-
V1N S-l0mV
2.2
2.2
mAMAX
Power Consuri1ption
Pd
VINs-l0mV
153
161
mWMAX
NOTES:
1. These Parameters are specified as the maximum values required to drive
the output between the logic levels of 0.4V and 2.4V with a 1kO load tied to
+5V; thus. these parameters define an error band Which takes into account
the worst case effects of voltsge gain and Input impedance.
2. Guaranteed by design.
ELECTRICAL CHARACTERISTICS at Vs+ = 5V and Vf> = OV at 25° C.
CMP-01N
CMP-01GR
LIMIT
LIMIT
Vos
1.5
3.5
mVMAX
lOS
21
65
nAMAX
PARAMETER
SYMBOL CONDITIONS
Input Offset Voltage
Input Offset Current
UNITS
TYPICAL ELECTRICAL CHARACTERISTICS at Vs = ± 15V, and 25°C.
PARAMETER
SYMBOL CONDITIONS
Average Input Offset
Voltsge Drift
TCVos
Average Input Offset
Current Drift
TClos
Response Time
t,
Rs = 500 (Note 1)
100mV Step. 5mV Overdrive
No Load (No Pull-Up)
PAGE 7-9
CMP-01N
CMP-01GR
TYPICAL
TYPICAL
UNITS
1.5
1.8
~V/oC
35
40
pAloC
100
100
ns
CMP-01 FAST PRECISION COMPARATOR
TYPICAL PERFORMANCE CURVES
RESPONSE TIME TEST CIRCUIT
RESPONSE TIME, 100mV STEP, SmV OVERDRIVE, VARIOUS LOADS
5
~±T~~
TA=25"C
RS= son
~
o
C.
-0.10
FAN OUT,. 4
-0.15
-60
~
~~~nG:~:~OAD -
i r 'I·
~
N3\ ~ ~
0.10
w
"~ -0.05 I--/--+--I-~:
~
\!~\L;;>
_
I
3.
f--
60
120
90
-60
150
~
V
~
1.
1=
0.10
~
o
TYPICAL
~IIII
I III
1.
eMP·01
2.
CMP-01E
CMP·01C
1
~
1
10
-so
-25
~5V"~S-~0I
,
!J.. I\!l..
I"""-.. .........
tr1L tY>J
r--;:,
1.
eMp·Ol
eMP·01E
(DOC TO 70"C)
2.
eMp·Ole
-25
-
I I
~s+ =1 ,5v
..... I--.J.
~
~
1
0
25
"-
Rs '" son
ILll
50
75
100
-75
125
eMP·O'
eMP·OlE
We TQ70"C)
2.
eMP·Ole
-25
600
~
~
1--+-+-+-+-+-I--1----jf-.~+-+_l100
200
~
~
125
ffi
a
300
~
300
400
5
Z 200
z
!
~
7nA CHANGE
~
~
500 C!I
Z
I--l--+--tl--+--I--I-I-
Vs = ±15V
t-
600
-8
-4
DIFFERENTIAL INPUT VOLTAGE (VOLTS)
PAGE 7-10
ffi
>
TA = 25°C
f:t:J::ijjj=tt=t=t±~
0 _~
-50
-12
~VS+"'5V
Vs+" 1SV
t--
700
12
Vs+ - 5V_
I-- l - i S + T -
25
75
125
(~CI
INPUT VOLTAGE RANGE
VI TEMPERATURE
400
100
0
--,
TEMPERATURE
~
75
~
1.
Vs = t15V -
>-
>
25
r\~UIL~ ~
~
~ 500
r-- Vs+=5V
r-
TEMPERATURE (OC)
~ !'@
hr,)
750
1700
I
1
INPUT BIAS CURRENT VI
DIFFERENTIAL INPUT VOLTAGE
INPUT BIAS CURRENT
vs TEMPERATURE
600
2.
~
(O"C TO 70"e)
CMP'()lC
TEMPERATURE (C)
MATCHED SOURCE RESISTANCE (k.l1)
""-
\
eMP·Ol
eMP·01E
~
0.0 1
100
I
6.1..(,
UNN~ED
>=>
500
1
1--15V';;;VS-,z;;o
~
1""\1
1.0
INPUT OFFSET CURRENT
VB TEMPERATURE
,
o
>
i;;
o. 1
(VOS" OVERDRIVE)
\. RISE: (Vos- OVERDRIVE)
10
.......-
jDRr NSE
-75
V'N~ FALL:
150
OFFSET VOLTAGE VB
TEMPERATURE
F-VI II
0
120
RESPONSE TIME InSEC)
1.0
f=
~!:~!:~t-
o
TTL GATE LOAD
FAN OUT = 4
NO LOAD
90
60
INPUT OFFSET ERROR VB
SOURCE RESISTANCE
100
soon TO 5V
~-O.05 ~
RESPONSE TIME (nSEC)
0
CL = 12pF INCLUDING PROBE
AND JIG CAPACITANCE
~
v+
V+-O.5
h'"Cn=~~I::J
~ V+ -1.0 1---+_--1-_+--==1=="--+_~tlv:::S+=-"-f-.v-l
5~ V+ -1.5 I--+--l---Ie.--+-+--+
w
~ V+ -2.0 I---+-+--If-.-+-+--+-I-+-l
~
w
"~V-+,ol--+--+-~e.--+--+--H--+~
g +l.s!--::r:===t===1"",+-.J.-d=+--l
V-
~ v- +1,0 f---I----I--~-+
V- +0.5 1--1----!-->---+-+--I-+--I
125
-25
TEMPERATURE (OCI
CMP-01 FAST PRECISION COMPARATOR
TYPICAL PERFORMANCE CURVES
RESPONSE TIME VI SOURCE
RESISTANCE
RESPONSE TIME FOR 100mV STEP AND VARIOUS INPUT OVERDRIVES
N~LOA~
r- Vs'" <1SV
TA '" 25"C
- RS '" SOU
w
"~ -0,05
~ -0.10
}.
4'"
/
3
/
...
1
~
0 0
1\
\ \
(til ,0
b
1\
~
~
~
g
1- 2."
3.
l l
0.10
120
240
360
>
1,,,"~ V
V
,/
i5
~ 0.4
~
I?
!5 0.2 A
§
,,-
V
:,....~
"'"
o
o
20
V
\
0
w
-
-
:.--
w
r!
~
120
240
360
40
o
I
I
TA-""C
o
i
~
OUT~UT LOW
f--
°ucrrUT~
VS'" '15V
TA = 25"C
IIIIII
1.0
100
10
POWER CONSUMPTION
VI TEMPERATURE
r--r-,--r--r--.--r--..-.,
r--+--J--t- Vs = ±15V, Vo = LOW_
OO
1-f-"....d.-...-4-=j:I=t:::::jI:::=~
11:" r--+--J--r--+-+-t--+--j
~ r--+--J-- V~
NEGATIVE SUPPLY
20
t5
t10
±1&
±SUPPLY VOLTAGE ( VOLTS!
= 5V, Vi = ov, Vo = LOW
~'=&---60~--~a~~o7--a~~50~~~=-~'~oo~~,~
'20
TEMPERATURE
ret
RESPONSE TIME FOR SV STEP AND SmV OVERDRIVE
/
l!
~
-,
~
-2
~
-.
/
l!
.~
."'2g!
/
INPUT
&
OUTPUT
/
i~
1
.
~~ L~:5~TA '" 26°C
fts = 5 O ( l -
-I
--6
100
20D
RESPONSE TIME (nSEC)
PAGE 7-11
I
300
~
"
00
•
o
a:
o
!c
~
Go
r ~+-I-+-I-+-II-+--I
/
V+
STROBE
-_.
t
,/
/'~
3.3k1l
,
~·t=:t::1;;;t~ViS==~'~'5~V~.V~O~=~HliG~H~-
/
%i'T,VE SUPPLY
OFFSET TRIMMING AND
STROBE CIRCUIT
OUTPUT
-:
2
SOURCE RESISTANCE (kH)
M!NIMU~
v-:::
50
...(,"
0.1
'20
/
-I- -
30
,,.
;::
-
POS!TlVE
SUPPLV IS +4.5V
r--
OUTPUT SINK CURRENT (mA)
V-
...
"
"
1 ~
NO LOAD
1200 ~RS MATCHED TO 1.0%
i =
"
12
f-
25"~
, / _56°C
~~~v~~ve~ ~~~
10
g
SUPPLY CURRENT VI
SUPPLY VOLTAGE
V
/'
0.6
!:;
RESPONSE TIME InSEC)
SATURATION VOLTAGE
VI SINK CURRENT
1.0
!
3 ~
2
lmV
2.3. ~:~~
t-4. 20mV
120
420
RES1'ONSE TIME (nSEC)
~ 0.8
w
_
2mV OVERDRIVE
5mV OVERDRIVE
20mV OVERDRIVE
100mVSTEP
2.
3.
~
1.
0.05
1.
VS'" ±1SV_ 4 0
TA = 2SoC
RS = son
~~ -0.05
-0.15
~
~
NO LOAD
w
lmV
2mV
5mV
- r-4j 20jV
-
~
~
2g
./
jJ/
~
!
/
((yep ¢
~
K
I
:1
i!!
t?'" /
.,0 "/ V
12k
I I
~.
~.
~3
~
r"
0 '
liD
\
INPUT
NO LOADVs = ±15V
TA =25°CRS = 600
\
OUTPUT
\
\
l-
E
!
100
200
RESPONSE TIME InSEel
300
:I
o
o
CMP·01 FAST PRECISION COMPARATOR
APPLiCATION NOTES
The CMP-01 provides fast response times even with small
input overdrives; to achieve this performance requires very
high gain at high frequencies. The CMP-Q1 is completely free
of oscillations; however. small values of stray capacitance
from output to Input when combined with high-source resistances can cause an unstable .condition. DC characteristics
are not affected. but when the Input is within a few microvolts
of the transition level. certain conditions can create an oscillation region. The width ofthls oscillatory region and the size
of source resistance where oscillations begin Is a strong
function ofthe stray coupling present. The following suggestions are offered as a guide towards minimizing the conditions for oscillation: matched source resistors. minimized
stray capacitances (e.g .• a ground plane between output and
input). capacitive output loading (Cu. or a capacitor from
the compensation terminal to AC ground (DIP only). The
capacitive loading techniques will eliminate the oscillations.
but result in slower response time. Positive resistive feedback creating a hysteresis condition can be very effective see level detector below. Matched bypass capacitors across
the input resistors also can eliminate the Instability. .
and if C 2: 20pF maximum step size
S
minimum overdrive
the response time will approximate the response time for low
values of R& It should be noted that the offset nulling terminals do not require bypassing for stability. As with all wldeband circuits. it Is recommended that the supplies be
bypassed near the socket of the device.
PRECISION, DUAL LIMIT, GOINO GO TESTER
OUTPUT
INI'UT
~~Ro---_ _ _. ,
=~ E~:H~~TTI~S~
CEEP~D.
-1""
OUTPUT IS HIGH WHEN IN·
PUT IS WITHIN LIMITS.
8 -BIT TRACKING AID CONVERTER
CLOCK IN
MAXIMUM CLOCK RATE" ..OM....
~~
'f.' :
• C
-15V
•
•
~
.
.
FOR CLOCK"RATE'" 3.OMHz
C .. 410pF
~ lN91.:"i
RIN
'1!!
-~
~~
4.8kn
..
1
UP/DOWN
OUT
.COUNTER
,
~ CARRY
.. •
COUNTER
• ,
HOLD
~
fL-l
z"
.J/
\
j
Dl.OITAL
OUTPUT
if
13 12 "
'D
MS.
••
7
•
+5 V
I. T•
+llV
LS8
lNltl.
.. :::'l
DAC·100CCQ3
10-8IT DlA, CONVERTER
"'80
11
ANALOG
INPUT
111 .....
FULL="t'
MAXIMUM FULL SCALE
SINE WAVE INPUT
IS 4000Hz.
+IV TRACK
1
OUT
..~,
vlN = 0 TO +lOV
• C
....
·1'4-7400
2400
":'
U/D
Q
-
~ .......
~
• C
1/2 7474
TYPE "0"
FlIP·FLOP
l
PAGE 1-12
~ :::'l~
J
....1&V
CMP-01 FAST PRECISION COMPARATOR
3 IC LOW COST AID CONVERTER
LEVEL DETECTOR WITH HYSTERESIS(Polltlve Feedback)
"2
ANALOG
INPUT
o TO +lOV
VREf
"'
O-....,M"--.....-"-I
>-'--....---<>
R1 II HZ
INPUT
OUTPUT
O--.M"----=-J
HYSTERESIS WIDTH" 4V R1
~1 H2
v-
BURN-IN CIRCUIT
II
v+
8ERIAL
OUTPUT
START
CONVERSION
COMPLETE
TTL CLOCK
INPUT
2.2OM'"
0--------'
en
II:
o
CONNECT ''START'' TO ''CONVERSION
COMPLETE" FOR CONTINUOUS
~
CONVERSIONS,
V-(CASEJ
Mll-S'ro·8B3. METHOD 1015, CONDITION B
~
::Ii
o(,)
4-CHANNEL DIGITALLY MULTIPLEXED RAMPED AID CONVERTER
OAC-01
QUAD
LATCH
DIGITAL
} OUTPUT
+----\-I-STATuS BIT
ANALOG
INPUT
IDENTIFIER
j.+------+----------'-------------oAESET
WORST CASE CONVERSION TIME
12~SEC PER CHANNEL
PAGE 7-13
CMP-02
PMI
LOW INPUT CURRENT
PRECISION COMPARATOR
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Low Offset Voltage ... 0.3mV Typical, 0.8mV Maximum
Low Offset Current .... 0.3nA Typical, 3.0nA Maximum
Low Bias Current ....... 28nA Typical, SOnA Maximum
Low Offset Drift ................... 1.0I'V/oC,4pA/oC
High Gain ......................... 200,000 Minimum
High CMRR ........... 110dB Typical, 94dB Minimum
High Input Impedance ........................ 16MO
Fast Response Time .. 190ns Typical, 270ns Maximum
Standard Power Supplies ..........•.... ±SV to ±18V
Guaranteed Operation from Single +5V to ±18V
No Pull-Up Resistor Required for TTL Drive
Wired-OR Capability
Fils 111, 106, 710 Sockets
Easy Offset Nulling ........• Single 2kO Potentiometer
Easy to Use ................... Free from Oscillations
process. It features superior input characteristics with extremely low offset voltage, offset current, bias current and
temperature drift. High common mode and power supply
rejection plus good response time contribute to excellent
performance in the most demanding applications. The balanced offset nulling, large output drive, and wired-OR capability combined with internal pull-up maximize application
convenience. The CMP-02 is capable of operating over a
wide range of supply voltages, including single plus 5 volt
supply operation, and is pin-compatible to earlier 111, 106,
and 710 types. For applications requiring faster response
time, please refer to the CMP-01 Fast Precision Comparator
data sheet.
PIN CONNECTIONS
v.
GENERAL DESCRIPTION
The CMP-02 is a monolithic low input current comparator
using an advanced compatible NPN-Schottky Barrier Diode
ORDERING INFORMATIONt
(mV)
0.8
2.8
6 BALANCE
5 BALANCE
4
v- (CASE)
HERMETIC
vos
+IN 2 :
-IN 3
PACKAGE
+25°C
GNeDS7OUT
DIP
TO-99
SPin
SPin
14 Pin
CMP02J'
CMP02Z'
CMP02Y'
CMP02EJ
CMP02EZ
CMP02EY
CMP02BJ'
CMP02BZ'
CMP02BY'
CMP02CJ
CMP02CZ
CMP02CY
PLASTIC
DIP
SPin
OPERATING
TEMPERATURE
RANGE
CMP02EP
COM
TO-99
(J-Sufflx)
14-PIN HERMETIC DIP
(Y-Sufflx)
MIL
8-PIN HERMETIC MINI-DIP
(Z·Sufflx)
MIL
CMP02CP
COM
'Also available with MIL-STO-883B processing. To order add/8B3 as a sulfix
to the part number.
t All listed parts are available with 160 hour burn-in. See Ordering Information,
Section 2.
EPOXY B MINI-DIP
(P·Sufflx)
SIMPLIFIED SCHEMATIC
v+
NON·INVERTING
INPUT
INVERTING
SD9
v-~
____
~
____+-__
~
PAGE 7-14
CMP-02 LOW INPUT CURRENT PRECISION COMPARATOR
ABSOLUTE MAXIMUM RATINGS (Note 2)
Total Supply Voltage, V+ to V- ..................... 36V
Output to Ground .......................... -5V to +32V
Output to Negative Supply Voltage ................. 50V
Ground to Negative Supply Voltage ................ 30V
Positive Supply Voltage to Ground ................. 30V
Positive Supply Voltage to Offset Null. .. . . . . . . ... 0 to 2V
Power Dissipation (See Note) ................... 500mW
Differential Input Voltage ......................... ±11 V
Input Voltage (Vs = ±15V) ......................... ±15V
Output Sink Current (Continuous Operation) ...... 75mA
Operating Temperature Range CMP-01, CMP-01B .................. -55°Cto+125°C
CMP-01E,CMP-01C .................... 0°Cto+70°C
DICE Junction Temperature (T j ) ••••••• -65°C to +150°C
Storage Temperature Range
........... -65°C to +150°C
ELECTRICAL CHARACTERISTICS
at Vs
=±
15V, TA
Lead Temperature (Soldering, 60 sec) ............ 300°C
Output Short Circuit Duration - to ground .... Indefinite
to V+ .......... 1 Minute
NOTES:
1. Maximum package power dissipation vs. ambient temperature.
Maximum Ambient
Derate Above Maximum
Temperature for Rating Ambient Temperature
Package Type
TO-99 (J) - B-Pin
BO·C
7.1mW;oC
Dual-in-Line (Y) 14-Pin
100·C
10.0mW;oC
Mini-Dip (P) - B-Pin
36·C
S.6mW;oC
Hermetic Mini-DIP (Z)8-Pin
7S·C
6.7mW;oC
2.
=25°C, unless otherwise noted.
CMP-02B
CMP-02C
CMP-02
CMP-02E
PARAMETER
Input Offset Voltage
Input Offset Voltage
•
Ratings apply to both DICE and packaged parts, unless otherwise noted.
SYMBOL CONDITIONS
MIN
MIN
Ul
TYP
MAX
TYP
MAX
UNITS
Vas
Rs oS SkU (Note 1)
0.3
0.8
0.4
2.8
mV
Vas
RsoSSOkU (Note t)
0.3
0.9
0.4
3.0
mV
Input Offset Current
los
(Note 1)
0.3
3.0
0.4
15
nA
Input Bias Current
Is
28
50
3.5
100
Differential Input
Resistance
R'N
(Note 2)
Voltage Gain
Ava
Va = O.4V to 2.4V (Notes 1 and 2)
t,
1OOmV Step SmV Overdrive
No Load (No Pull-Up)
SkU to SV (Pull-Up)
TTL Fan-Out = 4. No Pull-Up
Response Time
(Note 3)
nA
5.0
16
1.5
12
MU
200
500
100
500
V/mV
190
190
190
Input Slew Rate
270
190
190
190
15
270
ns
V/~s
15
Input Voltage Range
CMVR
±12.5
±13.0
±12.5
±13.0
V
Common Mode
Rejection Ratio
CMRR
94
110
90
110
dB
Power Supply
Rejection Ratio
PSRR
5V ,;;Vs+ ,;;18V, -18V ,;;Vs_ ';;OV
80
100
74
98
dB
Positive Output
Voltage
V'N«3mV,lo=320~A
2.4
3.2
VOH
Y,N «3mV, 10= 240~A
V 1N ;;:::3mV, 'a-OIlA
4.8
2.4
2.4
3.4
4.8
V
2.4
Saturation Voltage
VSAT
VIN :5-10mV, 'sink = OA
VIN :5-10mV,l sink :s6.4mA
Y,N ,;;-10mV, I'ink ,;;12mA (CMP-02 only)
0.16
0.3
0.36
0.40
0.45
0.5
0.16
0.31
0.4
0.45
Output Leakage Current
'LEAK
VIN« 10mV, Va = 30V
0.03
2.0
0.05
8.0
~A
Positive Supply Current
1+
VIN ,;;-10mV
5.5
8.0
5.6
8.5
mA
Negative Supply Current
1-
VIN :=;-10mV
1.1
2.2
1.2
2.2
mA
Power Dissipation
Pd
VIN s;-10mV
99
153
102
161
mW
Nulling Pot «2kU
±S
Offset Voltage
Adjustment Range
NOTES:
1. These Parameters are specified as the maximum values required to drive
the output between the logic levels of O.4V and 2.4V with a 1kn load tied to
+SV; thus, these parameters define an error band which takes into account
2.
3.
PAGE 7-15
±5
the worst case effects of voltage gain and input impedance.
Guaranteed by design.
Sample tested.
V
mV
a:
o
~
a:
::::E
oo
CMP-02 LOW INPUT CURRENT PRECISION COMPARATOR
ELECTRICAL CHARACTERISTICS
at Vs
=SV, Vs- =av, TA =2S'C, unless otherwise noted.
CMP-02B
CMP-D2C
CMP-02
CMP-02E
PARAMETER
SYMBOL CONDITIONS
Input Offset Voltage
Vos
Input Ollset Current
los
Input Bias Current
Ie
Voltage Gain
Av
Vo = 0.4V to 2.4V (Note. 1 and 2)
Response Time
tr
100mV Step, 5mV Overdrive
5kn to 5V (Pull-Up)
TTL Fan-Out = 4, 5kn to 5V
MIN
RsS5kn(Note 1)
TYP
MAX
MIN
TYP
MAX
UNITS
0.4
1.5
0.5
3.5
mV
0.25
3.0
0.35
14
nA
24
45
30
90
50
50
250
250
250
250
nA
v/mV
n.
Input Voltage Range
CMVR
Saturation Voltage
VSAT
VIN ,,-3.5mV, I'ink "6.4mA
Positive Supply Current
1+
Y,N "-10mV
2.2
3.0
2.3
3.6
mA
Power Dissipation
Pd
Y,N ,,-10mV
11.0
15.0
11.5
18.0
mW
TYP
MAX
UNITS
0.5
0.6
3.5
4.3
mV
1.8-3.5
ELECTRICAL CHARACTERISTICS
1.7-3.8
0.3
1.8-3.5
0.45
0.3
CMP-02
SYMBOL CONDITIONS
Input Offset Voltage
VOS
With External Trim
Input Offset Current
Average Input Oll.et
Current Drift
V
0.45
V
at Vs = ±1SV, -SS'C " T A " 12S'C, unless otherwise noted,
PARAMETER
Average Input Ollset
Voltage Drllt
Without External Trim
1.7-3.8
MIN
CMP-02B
TYP
MAX
RsS5kn (Note 1)
Vs. = 5V, Vs_ = OV (Note 1)
0.4
0.5
1.6
2.8
TCVos
TCVOSn
RS= 50n
RS = 50n
1.5
1.0
los
TA = +125'C (Note 1)
TA = -55'C (Note 1)
0.3
0.4
TClos
+25°C STA:5+125°C
-55°C STA:5+25°C
2.0
4.0
25
45
MIN
1.8
1.2
4.0
12.0
0.4
0.5
pVl'C
15
25
3.0
5.0
Ie
Voltage Gain
Avo
Vo = 0.4V to 2.4V (Notes 1 and 2)
Response Time
tr
100mV Step, 5mV Overdrive
TA = +125'C, No Load
TA = -55' C, No Load
Input Voltage Range
CMVR
±12.0
±13.0
±12.0
±13.0
V
CMRR
88
106
86
106
dB
dB
Common Mode
Rejection Ratio
100
33
42
pAl'C
TA = +125'C
TA=-55'C
Input Bias Current
50
120
nA
70
500
310
155
VlmV
225
180
ns
PSRR
5V "VS+ ,,15V, -15V "VS_"OV
75
96
70
88
Positive Output Voltage
VOH
Y,N ;,:4mV, 10= 200pA
2.4
3.0
2.4
3.2
VSAT
0.20
0.32
VIN S-10mV, 'sink = 0
V,N ,,-10mV, I,'nk = 6.4mA
PAGE 7-16
0.4
0.5
nA
500
Power Supply
Rejection Ratio
Saturation Voltage
100
160
0.17
0.31
V
0.4
0.5
V
CMP-02 LOW INPUT CURRENT PRECISION COMPARATOR
ELECTRICAL CHARACTERISTICS
at Vs= ±15V, O·C,:; TA ,:;70·C, unless otherwise nOled.
CMP-02E
PARAMETER
SYMBOL CONDITIONS
MIN
CMP-02C
TYP
MAX
0.4
0.5
1.4
2.4
Input Offset Voltage
Vos
RsS 5kll (Note 1)
Vs+ = 5V. Vs- = OV (Note 1)
Average Input Offset
Voltage Drill
Without External Trim
With External Trim
TCVos
TCVOS n
Rs= 5011
Rs = 5011
1.5
1.0
I "put Offset Current
los
TA=+70·C (Note 1)
TA =O·C(Notel)
0.3
0.4
Average Input Offset
Current Drill
TClo s
+25°C ::;TA ::5+70°C
ooe ::sTA :5+25°C
2.0
4.0
Input Bias Current
Ie
TA=+70·C
TA = O·C
26
34
Voltage Gain
Av
Vo = 0.4V to 2.4V (Notes 1 and 2)
Response Time
t,
l00mV Step, SmV Overdrive
TA = +70·C, No Load
TA = O·C. No Load
Input Voltage Range
CMVR
±12.0
±13.0
ComrnonMode
Rejection Ratio
CMRR
90
Power Supply
Rejection Ratio
PSRR
5V ::sVs+ ::;;15V, -15V :5Vs_ :s;OV
Positive Output Voltage
VOH
VIN <:4mV, 10= 200~A
Saturation Voltage
VSAT
VIN ,:;-10mV, I slnk = 0
VIN ,:; -10mV, I sink = 6.4mA
MIN
TYP
MAX
UNITS
0.5
0.6
3.5
4.3
mV
1.8
1.2
3.0
6.0
0.4
0.5
~VI·C
15
25
3.0
5.0
50
80
33
42
nA
pArC
100
160
nA
500
VlmV
225
180
ns
±12.0
±13.0
V
108
86
108
dB
77
98
70
88
dB
2.4
3.2
2.4
3.2
V
100
500
70
225
180
II
:f:I
CJ
II)
a::
0,17
0.30
0.4
0.5
0.17
0.31
0.4
0.5
V
0
tc
a::
~
:I
0
CJ
PAGE 7-17
CMP·02 LOW INPUT CURRENT PRECISION COMPARATOR
DICE CHARACTERISTICS
1. GROUND
2. NON·INVERTING INPUT
3. INVERTING INPUT
4. NEGATIVE SUPPLY
5. BALANCE
6. BALANCE
7. OUTPUT
8. POSITIVE SUPPLY
Refer to Section 2 for additional DICE Information.
ELECTRICAL CHARACTERISTICS for Vs = ±15V at 25° C.
PARAMETER
SYMBOL CONDITIONS
Rs S5kO
Rs S50kO
CMP-02N
CMP-02GR
LIMIT
LIMIT
0.8
0.9
2.8
3.0
UNITS
Input Offset Voltage
Vos
Input Offset Current
los
3.0
15
nAMAX
Input Bias Current
Is
50
100
·nAMAX
MOMIN
mVMAX
Differential Input Resistance
RIN
5.0
1.5
Input Voltage Range
IVR
±12.5
±12.5
Common Mode Rejection Ratio
CMRR
VCM~±CMVR
94
90
dB MIN
Power Supply Rejection Ratio
PSRR
5VSVS+S 18V
-18VSVs-SOV
80
74
dBMIN
Positive Output Voltage
VO H
V ,N eo 3mV. 10 ~ 320!,A
V,N eo 3m\/, 10 ~ 240!,A
Saturation Voltage
VSAT
'sink=6.4mA
0.45
0.45
V MAX
Output Leakage Current
'LEAK
V,N eo 10mV, Vo~30V
4.0
8.0
!'AMAX
mAMAX
2.4
2.4
VMIN
VMIN
Positive Supply Current
1+
V ,N S-l0mV
8.0
8.5
Negative Supply Current
1-
V ,N S-l0mV
2.2
2.2
mAMAX
Power Consumption
Pd
V ,N S-l0mV
153
161
mWMAX
CMP·02N
CMP-02GR
LIMIT
LIMIT
1.5
3.5
mVMAX
3.0
14
nAMAX
ELECTRICAL CHARACTERISTICS at Vs+ = 5V and Vs- = OV at 25°C.
PARAMETER
SYMBOL CONDITIONS
Input Offset Voltage
Vos
Input Offset Current
lOS
RS S5kO
UNITS
TYPICAL ELECTRICAL CHARACTERISTICS at Vs = ± 15V, and 25°C.
PARAMETER
SYMBOL CONDITIONS
Average Input Offset
Voltage Drift
TCVos
Average Input Offset
Current Drift
TClos
Response Time
If
Rs~500
lOOmV Step, 5mV Overdrive
No Load (No Pull-Up I
PAGE 7·18
CMP-D2N
CMP-02GR
TYPICAL
TYPICAL
UNITS
1.5
1.8
!'vrc
4.0
5.0
pArC
180
180
ns
CMP·02 LOW INPUT CURRENT PRECISION COMPARATOR
TYPICAL PERFORMANCE CURVES
RESPONSE TIME TEST CIRCUIT
RESPONSE TIME, 100mV STEP, 5mV OVERDRIVE, VARIOUS LOADS
5_
1.
2.
-4<""'1---+-+-1 4
~
CL '" 12pF INCLUDING PROBE
AND JIG CAPACITANCE
0
"~
w
3
+-I--+--jl..:!.(-1""q.----j 2 g
!;
~
o
~
~
~
w
1
~
o
0.10
w
~ -0.05
"~
-t-~I----t-i Vs '" ±15V
g
-t--I----t-i RS = son
~-O.'0
0.05
g
TA= 25°C
~ -O.OS
-60
0
120
150
180
RESPONSE TIME (nSEC)
120
-60
210
150
180
210
\. RISE: (Vos - OVERDRive,
RESPONSE TIME (nSEC)
OFFSET VOLTAGE vs
TEMPERATURE
INPUT OFFSET ERROR vs
SOURCE RESISTANCE
100
INPUT OFFSET CURRENT
vs TEMPERATURE
800
1.0
~ 1. g~~!~E
r- 2. eMP·Ole
~
~ 0.10
,
~
o
I
'lE1!llII
2
TYPICAL
"~H
TA
Vs - 25°C
1111111
0.1
0.001
1.
0.010
0.100
1.00
10.0
==
8
~
~
40
, ,
~
30
"""
20
\.!.J
VS'~'5V:_
\!); r--I
~
I
Vs+ '" 5V
10
1.
CMP-02
eMP·OlE
(O°e TO 70 e)
0
2.
-15
I
i
CMP 02C
-25
I '- -
I I
II I
VS'j 15V
'"
fI
25
50
75
100
f-
125
25
15
-75
125
CMP-02
CMP-02E
1
40
-25
V+-l.0
l1
Vs '" ±1SV
TA '" 25°C
III
DIFFERENTIAL INPUT VOLTAGE (VOLTS)
PAGE 7·19
0
25
75
125
V'-2.0
----t--~J Vs+ '" 5V
1--+-+-I-----f""".,........I;;:c-,--j
~ V+-l.51--+-+-I--+-+---;-~
:1
11
I--- eMP-02E -I
1
I
w
3
g v- +1_51---=t=+=!=-t--*-~!:::C-+---l
~
20
-4
VS' j 5V
21
- f - f-'
-8
-
V'O:uB~I=l
V+ -0.5
~
:
30
-12
,..(1)b......
INPUT VOLTAGE RANGE
vs TEMPERATURE
0
7
10
IVS +=5V-
TEMPERATURE (OC)
I
-15V
TA '" 25°C
,/
-65"e
~~~~~::~:1~~
o
M'~'MU~ 'OS'~'VE
SUPPLY IS +4.5V
25°~
/
V /'
~
-
-- -
/
0 0.6
>
V
/
/
w
-
POWER CONSUMPTION
vs TEMPERATURE
SUPPLY CURRENT vs
SUPPLY VOLTAGE
I-- -
10
20
30
40
OUTPUT SINK CURRENT ImAl
"---
..
•o
:t
100
t--t-T:::::::;t:-;.:V;:S~=.:.±1:r5V.:;.:.:V,O~•. :L::OWr-==I
i
IY
I I
1--"1'-=---+-1--+--+---1-+--1
~ 40
1--+-+-1--+--+---1-+--1
~
2 20t--t-+-t-~~="L6~wVS-"'ov. f--
NEGATIVE SUPPLY
±20
±5
±10
:!:15
SUPPLY VOLTAGE (VOLTS)
120
v+
roo
80
:J
l;!
OFFSET TRIMMING
AND STROBE CIRCUITS
,.,........
..,...
t-....
40
ili
t= 1 MI~
I-
I
20
MIL-ST0-8S3, METHOD 1015, CONDITION B
f0
~
-4.t .. 10 SEC
0
V-lCASE)
rUT'U1T SIHOrTEO AT = I.
t
15
10
OUTPUT VOLTAGE IVOl TSI
0
RESPONSE TIME vs SOURCE
RESISTANCE
RESPONSE TIME FOR 100mV STEP AND VARIOUS INPUT OVERDRIVES
I
1.
I
3.
lmV
2mV
5mV
4-
20mV
2.
~
/
ct
~2)
/
1}l5
1
TA = 25°C
Rs=50n -
;r
.[
120
240
RESPONSE TIME (nSEC)
..~
11
1
\
\
\
\
1
0.10
~
0) E...
...
KD
\
"
420
-
:J
00
4-
-
3~
2g
1.
2.
3.
0.05
12,000
10amV STEP
r!
NO LOAD
'cl~
1mV·
2mV
5mV
As MATCHED TO 1:0%
irl
.
~ 1200
";::
~0
F"..
~
~3.
12
120
240
RESPONSE TIr,tE (nSEcl
PAGE 7-20
360
420
./
~ 1-(1
2
~.
ex 120
'QmV
~Z -0.06
[
360
i
\
G; ~
~
~
.~~:?:s~-
-0,05
'g; -0.15
-60
VS=±15V
TA"'25~C
RS= 50n
./
~ -0.10
[\
No lOAD·
V
/
w
"~
[
V
I
V /
CfJ
~
5
......-: ~ :::=.
/
128
t = 1 SEC
.....
"-
50
:J
...'iex
25
75
TEMPERATURE ,"CI
I
t--
[\
ex
"t::
-25
-75
II I
TA " 25"c
Vs = ±15V
...
illex
Vs .. ±16V. Vo '" HIGH
80
OUTPUT SHORT-CIRCUIT CURRENT
vs OUTPUT VOLTAGE
STANDARD BURN-IN CIRCUIT
-
z
~ OUTPUT HIGH
/..
r---r-'T'"-,---,---,--,--r--.
L. I-+-+-I---:-:'--±---:-'~±---l
v.oSITIVE SUPflL Y
/
120
•. 1
I
2mV OVERPRIVE
5mV OVERDRIVE
20mV OVERDRIVE
II lUll
[
[
VS=.t16V
TA = 26°C
1.0
10
SOURCE RESISTANCE (kG)
1011
CMP-02 LOW INPUT CURRENT PRECISION COMPARATOR
APPLICATION NOTES
The CMP-02 provides fast response times even with small
input overdrives; to achieve this performance requires very
high gain at high frequencies. The CMP-02 is completely free
of oscillations; however, small values of stray capacitance
from output to input when combined with high-source resistances can cause an unstable condition. DC characteristics are not affected, but when the input is within a few
microvolts of the transition level, certain conditions can
create an oscillation region. The width of this oscillatory
region and the size of source resistance where oscillations
begin is a strong function of the stray coupling present. The
following suggestions are offered as a guide towards minimizing the conditions for oscillation: matched source resistors, minimized stray capacitances (e.g., a ground plane
between output and input), capacitive output loading (Cd,
or a capacitor from the compensation terminal to AC ground
(DIP only). The capacitive loading techniques will eliminate
the oscillations, but result in slower response time. Positive
resistive feedback creating a hysteresis condition can be
very effective - see level detector below. Matched bypass
capacitors across the input resistors also can eliminate the
instability,
and if C
2:
s
20pF ( m~~imum step s~ze )
minimum overdnve
the response time will approximate the response time for low
values of Rs. It should be noted that the offset nulling terminals do not require bypassing for stability. As with all wideband circuits, it is recommended that the supplies be
bypassed near the socket of the device.
PRECISION DUAL LIMIT GO/NO GO TESTER
+1&V
UPPER
LIMIT
INPUT
LAMP
-,&V
OUTPUT
LOWER
LIMIT
-,&V
PAGE 7-21
•
VL " :rzv
IL < 7&mA
PMI
CMp·04
LOW POWER PRECISION
QUAD COMPARATOR
®
FEATURES
GENERAL DESCRIPTION
•
•
•
•
•
•
•
•
•
High Gain ........................ 200V/mV Typical
Single or Dual Supply Operation
Input Voltage Range Includes Ground
Low Power Consumption (1.5mW/Comparator)
Low Input Bias Current ....................... 25nA
Low Input Offset Current ................... :t 2.0nA
low Offset Voltage . . . . . . . . . . . . . . . .. :t O.4mV Typical
low Output Saturation Voltage ........ 250mV @ 4mA
logic Output Compatible with TTL, DTl, ECL, MOS and
CMOS
• Directly Replaces lM139/2391339 Comparators
Four precision Independent comparators comprise the
CMP.()4. Performance highlights include a very low offset
voltage, low output saturation voltage and high gain in a
single supply design. The Input voltage range includes
ground for Single supply operation and V - for split supplies. A low power supply. current of 2m A, which is independent of supply voltage, makes this the preferred comparator for precision applications requiring minimal power
consumption. Maximum logic interface flexibility is offered
by the open-collector TTL output.
ORDERING INFORMATIONt
PIN CONNECTIONS
2S·C
vos
(mV)
DIP PACKAGE
HERMETIC
14 PIN
PLASTIC
14 PIN
OPERATING
TEMPERATURE
RANGE
CMP04BY·
CMP04FY
MIL
INO
CMP04FP
COM
• Also available with MIL-STD-883B processing. To order add 1883 as a suffix to
the part number.
14 PIN HERMETIC DIP
(Y SUFFIX)
t All listed parts areavailable with tOO hour burn-in. See Ordering Information,
Section 2.
SIMPLIFIED SCHEMATIC (1/4 CMP·04)
TYPICAL INTERFACE
Driving CMOS
100kn
PAGE 7-22
14 PIN EPOXY DIP
(P SUFFIX)
CMP-04 LOW POWER PRECISION QUAD COMPARATOR
ABSOLUTE MAXIMUM RATINGS (Note 2)
Supply Voltage ............................•. 36V or ± 18V
Differential Input Voltage .......................... 36Voc
Input Voltage ............................. -0.3V to +36V
Power Dissipation (Note 1) ....................... 500mW
Operating Temperature Range
CMP-04 FY .........••••.•....••...•.. -25·C to +85·C
CMP-04 BY ........••.........•...... -55·C to +125·C
CMP-04 FP ............................. O·C to +70·C
DICE Junction Temperature (Tj ) •••••••• -65·C to +150·C
Storage Temperature Range .••......••• -65·C to +150·C
Input Current (V IN < -3.0V) ........................ 50mA
Output Short Circuit to GND •........••..•... Continuous
Lead Temperature (soldering, 10 sec) .•.....•....... 300· C
NOTES:
1. See table for maximum ambient temperature rating and derating factor.
2. Absolute maximum ratings apply to both packaged parts and dice. unless
otherwise noted.
Temperature
lor RaHng
Derate Above
Maximum Ambient
Temperature
l00·C
50·C
10 mW/·C
6mW/·C
Mexlmum Ambient
Package
Hermetic DIP (V)
Plastic 01 P (P)
ELECTRICAL CHARACTERISTICS at V+ = +5V, TA = 25·C, unless otherwise noted.
CMP-04B/F
PARAMETER
MAX
UNITS
0.40
1.0
mV
I,N(+) -I'N(-)
RL =5.1kn
Vo= 1.4V
2.0
10
nA
Ie
I,N(+) or
I'N(-) (Note I)
25
100
nA
Av
RL2: 15k, V+= 15V (Note 6)
t,
Y,N = TTL Logie Swing
VREF = 1.4V (Note 5)
VRL = 5V. RL = 5.1kn
CONDITIONS
Input Ollset Voltage
Vos
Rs=On, RL =5.1kn
Vo = I.4V (Note 1)
Input Ollset Current
los
Input Bias Current
Voltage Gain
Large Signal Response Time
Small Signal Response Time
MIN
TYP
SYMBOL
t,
80
200
VlmV
ns
300
,...
1.3
IVR
(Note 2)
(Note 4, Note 6)
80
100
V+-l.5
dB
Power Supply Rejection Ratio
PSRR
V+ = +5V to 18V (Note 6)
80
100
dB
Saturation Voltage
VSAT
V,N (-)2:1V
V,N (-) =0
I SINK s4mA
Output Sink Current
'SINK
V,N (-)2:1V
V,N (+) = 0, Vo S 1.5V
Output Leakage Current
'LEAK
V,N(+) 2:1V
V,N(-) = 0, Vo = 5V
0.1
100
nA
1+
RL = m, All Comps
V+=30V
0.8
2.0
mA
0
250
2. The input common~mode Yoltage or either input signal voltage should not
be allowed to go negative by more than O.3V. The upper end of the
common-m'ode voltage range is V+ -1.5V, but either or both inputs can go
to +30V without damage.
6.0
400
16
V
mV
mA
3. Operating temperature ranges are:
By ............................................... -55·C to +125·C
FY ................................................ -25· C to +85· C
FP .................................................. O·C to +70·C
4. RL ;" 15kn V+ = 15V. VOM = 1.5V to 13.5V.
5. Sample tested.
6. Guaranteed by design.
PAGE 7-23
~
~
C
:::I!
0
CJ
CMRR
At output switch pOint. Vo = I.4V, Rs on on with V+lrom 5V; and over the full
input common-mode range (OV to V+ -1.5V).
0
IL
Input Voltage Range
1.
:::I!
CJ
~
Y,N = 100mV Step (Note 5)
5mV Overdrive
VRL = 5V, RL = 5.1kn
NOTES:
....
~
1/1
Common Mode Rejection Ratio
Supply CUrrent
II
CMP-04 LOW POWER PRECISION QUAD COMPARATOR
ELECTRICAL CHARACTERISTICS at Vs+=5V. For CMP-04BY, -55° C:5TA :5125° C. For CMP-04FY, -25°C:5 TA :5 85° C.
For CMP-04FP, O°C:5 TA :5 70°C, unless otherwise noted.
CMP-04B/F
(Note 3)
SYMBOL
CONDITIONS
TYP
MAX
UNITS
Vos
Rs=OO, RL =5.1kO
Vo = 1.4V (Note 1I
1.0
2.0
mV
Input Offset Current
los
I'N(+I -I'N(-I
RL = 5.1kO
Vo= 1.4V
4.0
20
nA
Input Bias Current
I.
I'N(+lor
I'N(-I (Note 11
40
200
nA
Voltage Gain
Av
RL ;;'15k, V+=15V(Note61
Large Signal Response Time
t,
V'N = TTL Logic Swing
VREF = 1.4V (Note 51
VRL = 5V, RL = 5.1kO
Small Signal Response Time
t,
V'N = 100mV Step (Note 51
5mV Overdrive
VRL = 5V, RL = 5.1kO
PARAMETER
Input Offset Voltage
MIN
70
125
VlmV
300
ns
1.3
Input Voltage Range
IVR
(Note 21
Common Mode Rejection Ratio
CMRR
(Note 4, Note 61
60
0
100
V+-1.5
dB
Power Supply Rejection Ratio
PSRR
V+ = +5V to +18V
80
100
dB
Saturation Voltage
V SAT
V'N(-I;;' 1V
V'N (+1 =0
I S 'NK$4mA
Output Sink Current
ISINK
V'N(-);;' 1V
V'N(+) = 0, Vo $1.5V
Output Leakage Current
I LEAK
V'N(+);;' 1V
V'N(-) = 0, Vo = 5V
Supply Current
1+
RL = 00, All Comps
V+=30V
250
NOTES:
1. At output switch point, Vo= 1.4V, Rson 00 with V+lrom5V;and over the lull
input common-mode range (OV to V+ -1.5VI.
2. The input common-mode voltage or either input signal voltage should not
be allowed to go negative by more than O.3V. The upper end of the
common-mode voltage range is V+ -1.5V, but either or both inputs can go
to +30V without damage.
5.0
700
16
V
mV
mA
0.1
200
nA
1.2
3.0
mA
3. Operating temperature ranges are:
By ............................................... -55·C to +125·C
FY ................................................ -25·C to +85·C
FP .................................................. O·C to +70·C
4. RL ;;' 15kO V+ = 15V, VCM = 1.5V to 13.5V.
5. Sample tested.
6. Guaranteed by design.
PAGE 7-24
CMP-04 LOW POWER PRECISION QUAD COMPARATOR
DICE CHARACTERISTICS
1.
2.
3.
4.
5.
••
7.
e.
e.
10.
11.
12.
13.
14.
OUTPUT (2)
OUTPUT (1)
POSITIVE SUPPLY
INVERTING INPUT (1)
NON·INVERTING INPUT (1)
INVERTING INPUT (2)
NON·INVERTING INPUT (2)
INVERTING INPUT (3)
NON·INVERTING INPUT (3)
INVERTING INPUT (4)
NON·INVERTING INPUT (4)
GROUND
OUTPUT (4)
OUTPUT (3)
Refer to Section 2 for addHlonal DICE Information.
' - -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ... _. __ .. _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _..--l
ELECTRICAL CHARACTERISTICS at V+ = +5V. TA = 25° C. unless otherwise specified.
~
CMP-04N
CMP-04G
CMP-04GR
LIMIT
LIMIT
LIMIT
UNITS
RS=Ofi. RL =S.lkfi
Vo= l.4V (Note 1)
1.0
2.0
S
mVMAX
los
I'N(+) -I'NI-)
RL = S.lkO
Vo= 1.4V
10
2S
50
nAMAX
Input Bias Current
Ie
I'N(+)or
I'NI-) (Note 1)
100
100
250
nAMAX
Voltage Gain
Av
80
SO
SO
VlmVMIN
PARAMETER
SYMBOL CONDITIONS
Input Offset Voltage
Vas
Input Offset Current
IVR
(Notes 2. 3)
V+-l.S
V+-l.S
V+-2.0
V MAX
(Note 4)
80
80
80
dB MIN
Power Supply Rejection RatiO
PSRR
V++Sto+18V
80
80
80
dB MIN
Saturation Voltage
VSAT
V'N(-)",lV
V'N(-)=O
I S'NK,,4mA
400
400
400
mVMAX
Output Sink Current
ISINK
V'N(-) '" 1V
VIN (+) = O. Va" 1.SV
6.0
6
6
mAMIN
Output Leakage Current
ILEAK
V'N(+) '" 1V
VIN (-) = 0, Vo=SV
100
100
100
nAMAX
Supply Current
1+
RL = '", All Comps
V+=30V
2.0
2.0
2.0
mAMAX
ELECTRICAL CHARACTERISTICS at V+ = +5V. unless otherwise specified.
CMP-04N
SYMBOL CONDITIONS
t,
Small Signal Response Time
t,
V'N = 100mV Step (Note S)
SmV Overdrive
VRL = SV, RL = S.lkfi
At output switch point, Va = 1.4V, Rs on 00 with V+from SV; and over the full
Input common·mode range (OV to V+ -l.SV).
2. The input common-mode voltage or either input signal voltage should not
be allowed to go negative by more than 0.3V. The upper end of the
CMP-04G
CMP-04GR
TVP
TVP
TVP
UNITS
300
300
300
ns
1.3
1.3
1.3
p.
common-mode voltage range is V+ -l.SV, but either or both Inputs can go
to +30V withoul damage.
NOTES:
1.
f4
IIC
!cIIC
~
CMRR
Large Signal Response Time
CJ
:I
Input Voltage Range
V'N = TTL Logic (Note S)
Swing VREF = 1.4V
VRL = SV, RL = S.lkfi
:I
0
Common Mode Rejection Ratio
PARAMETER
II
3. Guaranteed by deSign.
4. R L ", lSkfi. V+ = lSV. VOM = 1.SV to 13.SV .
S. Sample tested.
PAGE 7-25
0
CJ
CMP-04 LOW POWER PRECISION QUAD COMPARATOR
TYPICAL PERFORMANCE CURVES
OFFSET VOLTAGE
VB TEMPERATURE
<0.2
~
......
<0.1
i~
" , r\
r-
I'"
!:;
o
>
0
-0.1
TA • 25"CI7rf'C
~
~::
g
"-
"-
II
~ 110
I
35
-3.0
40
J
~
0.9
",
ffi 0.7
a:
..
r-
,"",
1l
~ 0.5
~
I 90
0.3
60
TA=O"C
.""
,
~
~
o
--40 -20
20
.,.
/
40
60
~
so
100 120 140
TEMPERATURE (OCI
OUTPUT VOLTAGE VB
OUTPUT CURRENT AND
TEMPERATURE
SUPPLY CURRENT
vs SUPPLY VOLTAGE
>
"
-
....... r-.,.
-1.0
1. 1 T ·-'6·"C_ _
A
I
~ 120
~
10
15
20
25
30
V+ - SUPPl V VOLTAGE (VOCI
100 120 140
-r--.,
I
1;
-I-
0 20 40 60 80
TEMPERATURE lOCI
160
1.0
I
VOLTAGE GAIN
vs TEMPERATURE
160
a:
::>
.p -2.0
-0.3
-40 -20
2.0
"
~
T A " 126"C
""-
8
> -0.2
1
...
i:iia:
~"~55ec
I
~ 100
3.0
60
<0.3
i
INPUT OFFSET CURRENT
VB TEMPERATURE
INPUT BIAS CURRENT
V + TEMPERATURE
VB
-- -+-.
\-
TA "+10"C
~2"C
.!C-
~
~
70
60
-40 -20
0 20 4D 60 80
TEMPERATURE rei
10
100 120 140
20
30
10
40
10 - OUTPUT SINK CURRENT (rnA)
SUPPLY VOLTAGE (Voe'
RESPONSE TIME FOR
VARIOUS INPUT
OVERDRIVES - NEGATIVE
TRANSITION
6.0
w
~
4.0
g
3.0
5~
2.0
!;-
V
I
2jm,
+6~DC
IN
1.0
INPUT OVERDRIVE = 10DmV
w
.~...
100mV
0>
B.O
I
5.0 mY" INPUT OVERDRIVE
5.0
RESPONSE TIME FOR
VARIOUS INPUT
OVERDRIVES - POSITIVE
TRANSITION
0
•
~
1.0
1.5
4.0
3.0
\ J
5mV
1
I
IJ-.~~
0> 1.0
i
1
1/
5~2.0
5.1K
I L
I I
TI.~"C
0.6
~
g
!;-
VOUT
\~
'"
5.0
VIN
-
-
I
+
I--TA"'26"C-
I
I
I
I
I I I
2.0
0.5
~
I I
1.0
TIMEI~ECI
TIME (I'IECI
PAGE 7-26
Vour
1.6
I
2.0
100
CMP-G4 LOW POWER PRECISION QUAD COMPARATOR
TYPICAL APPLICATIONS
INVERTING COMPARATOR WITH HYSTERESIS
OUTPUT STROBING
v+
v+
+VIN
6.2kn
3kn
0--------1
lMn
Vo
>----.---ovo
STROBE
INPUT
lMn
"OR LOGIC WITHOUT
PULLUP RESISTOR
":'"
LIMIT COMPARATOR
II
SQUAREWAVE OSCILLATOR
V+
4.3kn
lOOk"
UI
LED
II:
o
+VREf HI o--~"I'---I
~
~
8
:::E
lOOkn
+VREF LOW O---./ItY---i
NON-INVERTING COMPARATOR WITH HYSTERESIS
COMPARING INPUT VOLTAGES OF OPPOSITE POLARITY
V+
v+
+VREf
0------;
YIN1 O--......,NY~....,
3kn
&.lkn
>--~VO
IOkn
Vo
PAGE 7-27
CMP-04 LOW POWER PRECISION QuAD COMPARATOR
TYPICAL APPLICATIONS
OR GATE
ONE-SHOT MULTIVIBRATOR
V+
V'l
.,
0-
10k"
l00pF
'VIN
o--j 1--.------1r--4----i
Vo
1N914
lMn
"0"
AND GATE
.., ..
PULSE GENERATOR
V+
V+
01
R1
1M"
15k!}
1N914
lOOk"
lOOk"
FOR LAROE RATIOS OF Rl/R2
D1 CAN BE OMlnED.
lMn
.'0.... , ..
ONE-SHOT MULTIVIBRATOR. WITH INPUT LOCK OUT
ft.
---.
+4V
18
o
lMO
1Mn
lOMa:
58Ok!l
16kn
::::JEr
Vo
to
.,
T = O.3mSEC
ozon
CMP-cJ4 LOW POWER PRECISION QUAD COMPARATOR
TYPICAL APPLICATIONS
TIME DELAY GENERATOR
Y+
..
,"
,"""
"2ODkn
1"0
10MO
..r-
Y+
o
tOka:
IO
Y03
61kO
Y+
v+
aT
- - - - - - - - - - : ;..... __
10
V3
Vel
II
'2
Y02
Y2
V2
5'''''
I
..
-.-
3.0ka
'0MIl
'000
Y+
.T
.,
10
Yo,
,....
10
":'"
II:
o
~
:o
:Ii
J.
..
INPUT GATING SIGNAL
(I)
c,
o.OOlpF
+VIN
BURN·IN CIRCUIT
·~'o-ft-~-=~~~~---t---t-~--o·~
<10k
MIL-8TD-883. METHOD 1016. CONDITION B
PAGE 7-29
5'''''
u
CMP-05
PMI
HIGH-SPEED PRECISION COMPARATOR
WITH LATCH CIRCUIT
®
FEATURES
GENERAL DESCRIPTION
•
The CMP05's very high speed and precision input specifications make it the ideal comparator in systems needing 12-bit
accuracy along with high speed. By using "Zener Zap" trimming input offset voltage is less than 1/10 LSB 112-bit, 10-volt
system). An exceptionally fast response time of 50 nsec is
possible with only 1/2 LSB overdrive 112-bit, 1O-volt system '.
•
•
•
•
•
Precision Input Stage
Input Offset Voltage . . . . . . . . . . . . . . . . . . . . .. 100"V
Input Offset Current . . . . . . . . . . .. . . . . . . . . . .. 15nA
Fast Response Time (SmV 00) .. . . . . . . . . . . .. 3Snsec
High Voltage Gain. . . . . . . . . . . . . . . . . . . . . .. 16,000V/V
Latch Function with TTL Compatible Input
TTL Compatible Output
Available in Hermetic Mini·DIP Package
The CMP05 design makes it the ideal component in systems
requiring high speed with excellent low-level analog signal
resolution. High-speed 12-bit successive approximation AID
converters, zero crossing detectors and logic threshold detectors are typical system applications.
ORDERING INFORMATIONt
PACKAGE
25°C
Vos
(IlV)
250·
600·
250
600
250
600
HERMETIC
PLASTIC
TO·99
SPIN
DIP
SPIN
CMP05AJ
CMP05BJ
CMP05EJ
CMP05FJ
CMP05AZ
CMP05BZ
CMP05EZ
CMP05FZ
PIN CONNECTIONS
DIP
SPIN
OPERATING
TEMPERATURE
RANGE
CMP05EP
CMP05FP
MIL
MIL
INO
INO
COM
COM
Vs'
B
DIGITALe'
OUT
,
GROUND
+IN 2
-
6
-IN 3
~~~~~E
15N.C.
4
Vs- iCASE)
• Also available with MIL-STO-8838 processing. To order add/883 as a suffix to
the part number.
TO-99
(J·Suffix)
t All listed parts are available with 160 hour burn-in. See Ordering Information,
MINi·DIP
(Z-Suffix)
Section 2.
SIMPLIFIED SCHEMATIC DIAGRAM
r-~--------~--~~--~----------------~----------------------------------~--~-oVS'
R141.4k
INTERNAL BIAS
LATCH
3.5V
061
R1
R2
ENABLE
R15
soon
soon
soon
INTERNAL BIAS
1.1k
OUT
2.4V
a'
063
1k
R.
.oon
INTERNAL
BIAS
RB
900n
023
-IN
GAIN
= 0.8
800\~
~--~----~~-------+----------+--------+--------~----+-----------------~Vs~
PAGE 7-30
CMP·OS HIGH·SPEED PRECISION COMPARATOR WITH LATCH CIRCUIT
ABSOLUTE MAXIMUM RATINGS
(Note 2)
Positive Supply Voltage •••.••••••••••••••••••••.••.•• +6V
Negative Supply Voltage ••••..••••.••.••••.••.•••••• -18V
Power Dissipation (Note 1) ••••••••••••••••••••.•• 500mW
Differential Input Voltage ••••..•••••••..•.••.•••••••. ±5V
Latch Enable Input Voltage •••••••••.• -O.5V to V+ Supply
Operating Temperature Range
CMP-05A/B (J or Z Package)
(Note 3) ••••••••••••.•••••••••••••• -55·Cto+125·C
CMP-05E/F (J or Z Package) ••...•.•••. -25·C to +85·C
CM P-05E/F (P Package) •.•••••.•••.••••.. O· C to +70· C
DICE Junction Temperature (T j ) ••••••• -65· C to + 150· C
Storage Temperature Range ••..•••.•••• -65· C to +150· C
Lead Temperature (Soldering, 60 Sec) •••••••.•••••• 300· C
ELECTRICAL CHARACTERISTICS
Output Short Circuit Duration -
to ground .••.•• Indefinite
to V+ = 5.0V •.•• 1 Minute
Maximum Ambient
Temperatur.
Maximum Ambient
Derate Above
lor Rating
Temperature
TO·99{J)
Epoxy Mini-DIP (P)
80·C
36·C
7.1 mWI"C
5.6 mWI"C
Hermetic Mini-DIP (Z)
75·C
6.7mW'·C
Package
NOTES:
1. See table for maximum ambient temperature rating and derating factor.
2. Absolute maximum ratings apply to both packaged parts and dice, unless
otherwise noted.
3. Latch is functional for -55 0 C ~ TA :5: +85 0 C.
V s + = 5.0V, Vs- = -5.0V, TA
= 25·C and
Latch Enable grounded, unless otherwise
noted.
II
on
CMP-05A1E
PARAMETER
SYMBOL
CONDITIONS
Input Ollset Voltage
Vos
Rs=500
Input Ollset Current
los
Input Bias Current
18
600
~V
15
80
30
150
nA
0.6
1.2
0.8
1.8
~A
UNITS
14
V/mV
84
89
dB
±3.0
±3.3
±3.0
±3.3
V
Vs = ±4.75V to Vs = ±5.25V
V;,+ = 5V, Vs- = -5V to -15V
51
15
126
51
64
18
126
63
"VIV
V'N"'0mV,lo=0~
V'N " 10mV, 10 = 320~A
V'N " 10mV, 10 = 200l'A
2.4
2.4
2.9
2.9
2.4
2.9
2.4
2.9
Vcm = ±3.0V, Note 1
IVR
Note 1
Power Supply Reiection Ratio
PSRR
Output High Voltage
VOH
Is+
MAX
200
MIN
16
Input Voltage Range
Positive Supply Current
TVP
250
91
Co~mon
VSAT
MAX
100
8
Avo
CMRR
Saturation Voltage
TVP
86
Note 1
Voltage Gain
Mode Rejection Ratio
MIN
CMP-05B/F
V
0.13
0.40
0.32
0.40
Vo " 2.4V, Note 1
Vo SO.4V
7.5
10
V1N S -10mV, 'sink = OmA
V IN:5: -10mV, I slnk = SmA
VIN~-10mV, I sink = 12.SmA
Negative Supply Current
Is-
Vo SO.4V
11
Power Dissipation
Pd
Vo SO.4V
105
Logic 1
VLH
Over Operating Temp. Range
Note 1
Logic 0
VLL
Over Operating Temp. Range
0.13
0,28
0.40
0.40
11
15
8.0
11
12
16
16
12
18
mA
155
115
170
mW
V
mA
Latch Input Voltage
2.0
2.0
V
0.60
Note 1
0.80
Latch Input Current
Lagle 1
Logic 0
Input to Output High
Response Time
Input to Output Low
Response Time
Latch Disable
Latch Set-Up Time
ILH
ILL
VLH = 3.0V. Note 1
VLL = 0.8V, Note 1
10
6
t pd +
Voo = 1.2mV, Notes 1,2
Voo = 5.0mV, Notes " 2
50
37
t pd-
Voo = 1.2mV, Notes " 2
Voo = 5.0mV, Notes " 2
35
Notes " 3
18
ttpd+'
t,,,.
t,
45
25
10
6
45
25
55
50
37
60
55
47
35
60
47
6
Voo= l00mV. Notes " 4
18
~A
ns
ns
ns
ns
NOTES:
1. Guaranteed by design.
2. Times are for 100mV step inputs. See switching time waveforms.
4. With overdrive signals less than 100mV set-up time decreases and may
become negative. Large overdrive signals represent worst case conditions
for set·up time.
3. See switching time waveforms.
PAGE 7-31
:t:Ii
0
en
a:
0
!Ca:
~
:Ii
0
0
CMP·05 HIGH-SPEED PRECISION COMPARATOR WITH LATCH CIRCUIT
ELECTRICAL CHARACTERISTICS at Vs + =5.0V, Vs 125·C. For CMP..()5E1F; -25·C S TA S 85·C
= -5.0V, and Latch Enable grounded. ForCMP-Q5A1B, -55· CS TAS
(J,Z Packages) and O·C S TA S 70·C (P Package), unless otherwise noted.
PARAMETER
SYMBOL
CONDITIONS
Input Offset Voltage
Vos
Rs=500
Input Off8at Voltage Drift
TC vos
CMp·05A1E
TYP MAX
MIN
0.25
CMP·058/F
TYP MAX
MIN
0.80
0.40
1.5
1.5
2.5
UNITS
mV
"W·C
Input Offsat Current
los
40
250
70
400
nA
Input Bias Current
Ie
1.1
2.5
1.5
3.8
"A
Voltage Gain
Avo
Note 1
Common Mode Rejection Ratio
CMRR
Vcm= ±2.9V, Note 1
Input Voltage Range
IVR
Note 1
Power Supply Rejection Ratio
PSRR
Output High Voltage
VOH
Saturation Voltage
VSAT
6
11
5
10
WmV
S3
90
80
66
dB
±2.9
±3.2
±2.9
±3.2
V
±4.75V S Vs S ±5.25V
S3
178
60
252
~V/v
V'N'" 10mV, 10= O"A
V'N"'10mV,l o =24O"A
V'N'" 10mV. 10 = 180"A
2.4
2.4
2.4
V
2.4
VIN S -10mV, Islnk = OmA
V'N S -10mV. I.'nk = 9.8mA
V'N S -10mV. I.'nk = 8.4mA
0.18
0.2
0.40
0.40
0.20
0.40
0.30
0.40
V
Positive Supply Current
Is+
VoSO.4V
11
16
12
17
Negative Supply Current
Is-
Vo SO.4V
12
17
13
19
mA
Power Dissipation
p.
VoSO.4V
115
165
125
180
mW
Latch Input Current
Logic 1
Logic 0
ILH
ILL
V LH = 3V. Note 1
VLL = 0.8V. Note 1
18
10
90
18
10
90
Input to Output High
Response Time
tpd+
Voo = 1.2mV. Notes 1. 2
Voo= 5.0mV. Notes 1. 2
125
125
92
92
Input to Output Low
Response Time
tpd_
Voo= 1.2mV. Notes 1. 2
Voo = 5.0mV. Notes 1. 2
115
115
Latch Disable
Latch Set-Up Time
50
50
mA
"A
ns
ns
66
66
ted
Notes 1. 2. 5
38
38
ns
t.
Notes2.4.5
6
6
n.
NOTES:
1. Guarentasd by design.
2. Times are for 100mV step Inputs. See switching time waveforms.
4. With overdrive signals less then 100mV set-up time decreases and may
become negative. Large overdrive signals represent worst case conditions
for set-up time.
3. A high on the latch enable Input will cause the latch to assume the state of
the comparator and not follow subsequent inputs.
5. Latch is functional for -55· CSTAS +85· C.
PAGE 7-32
CMP·05 HIGH·SPEED PRECISION COMPARATOR WITH LATCH CIRCUIT
DICE CHARACTERISTICS
1.
2.
3.
4.
••
7.
8.
DIGITAL GROUND
NON-INVERTING INPUT
INVERTING INPUT
NEGATIVE SUPPLY
LATCH ENABLE
OUTPUT
POSITIVE SUPPLY
Refer to Section 2 for additional DICE Information.
DIE SIZE 0.051 )( 0.045 Inch
ELECTRICAL CHARACTERISTICS Vs = ± 5V,
TA
= 25°C, unless otherwise noted.
CMP-GSN
PARAMETER
SYMBOL CONDITIONS
Input Ollset Voltage
vos
Input Offset Current
CUP-G5G
LIMIT
LIMIT
250
600
"V MAX
los
SO
150
nAMAX
Input Bias Current
Ie
1.2
1.8
,.A MAX
Voltage Gain
Avo
Note 1
8
Input Voltage Range
IVR
Note 1
±3.0
±3.0
Power Supply Rejection Ratio
PSRR
±4.75 S VSS ±5.25
Vs+ = 5V, Vs- = -5V to -15V
78
86
S4
Positive Output Voltage
VOH
VIN'" 10mV,10=0"A
2.4
2.4
Saturation Voltage
VSAT
VIN S 10mV, 10 = O,.A
0.4
0.4
V MAX
Positive Supply Current
1+
VoSO.4V
15
16
mAMAX
Rs=500
UNITS
V/mVMIN
75
VMIN
dB MIN
1-
VoSO.4V
16
18
mAMAX
Negative Supply Current
1-
V-=-15V, VO SO.4V
18
20
mAMAX
Latch Input Voltage
Logic 1
Logic 0
V LH
VLL
Latch Enabled
Latch Disabled
2.0
0.8
2.0
0.8
VMIN
V MAX
CMRR
Vc.. = ±2.9V
Note 1
83
80
dlilMIN
ILH
ILL
V LH = 3.0V, Note 1
VLL = 0.8V, Note 1
45
25
25
Input-to-Output High
Response Time
tpd+
Voo = 5.0mV, Notes 1, 2
55
80
ns MAX
Input-to-Output Low
Response Time
tpd_
Voo= 5.0mV, Notes 1, 2
55
80
ns MAX
Latch Input Current
Logic 1
Logic 0
ELECTRICAL CHARACTERISTICS Vs
PARAMETER
45
,.A MAX
= ± 5V, TA = 25°C, unless otherwise noted.
SYMBOL CONDITIONS
CMP-GSN
CMP-G5G
TYPICAL
TYPICAL
50
50
ns
UNITS
Input-ta-Output High
Response Time
tpd+
Voo = 1.2mV, Note 2
Input-ta-Output Low
Response Time
tpd-
Voo = 1.2mV, Note 2
47
47
ns
Latch Disable Time
t1pd+'
tlpd-
Notes
16
18
ns
Voo=l00mV
3
3
ns
Latch Set-Up Time
NOTES:
1. Guaranteed by design.
2. Times are for 100mv step Inputs.
ts
3. With overdr.lve signals less than l00mV set-up time decreases and may
become negative. Large overdrive signals represent worst case conditions
for set-up time.
PAGE 7-33
....
C\'
D.
:I
U
en
a:
0
~
a:
INPUT CURRENTS va
TEMPERATURE
120
110
50-
1"\
1
l-
!\
'\
"iii0:
.."
'o.lpH
I-
~ 0,006
o
10
>=
~
/
25
50
75
....... 11
11111
20
,---,---,..---,..---..,----r--...
100 I---I---r-~'f-++---+_--I
m751---r-~f-~l---+---+_--I
100
125
RESPONSE PHOTOGRAPH
TEST SETUP
GENERATOR
RESPONSE TO 25M Hz
SINE WAVE
INPUT
~ROBE
OUTPUT
50"
NO
(RS<2OOn1
"CLEAN" SET
18
BALANCeD SOURCE RESISTANCE Ik'()HMSI
FET
OSC~~LATION
0.002
16
I
0
\
CAPACITANCE > O.lpf
8
10 12 14
ILOAD (mAl
~12&
/
./
V
!/
STRAY FEEDBACK
,.!5 0.004
6
roo
j
•..."
SET·UP
4
V'Smv OVERDRIVE
~
f---
-60
V
J
__ INTERNAL TO
Jll!l~l
III
Z
/
11111111
:i!
ia· O•OOB
i
80
50n
1.1! 0.012 t-- TA _ 25"C
~
I"
i
I-""
30
2
"'
176
TEMPERATURE ("C)
MINIMUM INPUT SIGNAL SLEW
RATE va BALANCED SOURCE
RESISTANCE
0.014
I
V
100
0:60
"""
'U>AD
~ ~ ~".,
I
100mV INPUT STEP
I: r--.
.... i---" "
RESPONSE TIME va BALANCED
SOURCE RESISTANCE
200
r-V~'±6J
~
....
/. ~
o
RESPONSE TIME va
TEMPERATURE
.
Vs· ±6V
1000
0.100
DIFFERENTIAL INPUT VOLTAGE (mV)
1200
~
0.250
0.160
~,..
"-~---::'-----!---"""----"""-,""50
100
,.
~ ;,-
~ ,..... TA-"""C
.,.. ~ ~D",~
DU"'"'
400
200 f----t---:~--+---'' - 0.3V) •.•.•...••.•....••..• SOmA
Operating Temperature Range
PM339A/339 ........................... 0° C to +70° C
PM239A/239 ......................... -25° C to +85° C
PM139A/139 ........................ -55°C to +125°C
Storage Temperature Range ........... -65° C to +150° C
Lead Temperature (Soldering, 10 sec) ............ 300°C
TYPICAL APPLICATIONS
AND GATE
OR GATE
V+
•
V+
39."
200k1l
"0"
"'"
+O.015V
10OkO
1k1l
A<>-~W.--,
100kn
Ao--W..-.....,
100k1l
100k1l
100k1l
100k1l
"0" "'"
TIME DELAY GENERATOR
V+
.
,"
111<11
10Mn
3.Okf2
V+
r-
a
10ka
IO
..
V03
3.0kn
51kn
I
V+
10M&)
w
----------;a---
aT
10""
Ye1
I
3.0kn
51""
10Mn
-.-
10""
V;=rL lOkn
. ..
INPUT GATING SIGNAL
-=
J.
e1
O.OOl,aF
+VIN
PAGE 7-39
51""
v+
oT
to
'1
PM139/PM239/PM338, PM139A1PM239A1PM339A LOW POWER QUAD VOLTAGE COMPARATOR
TYPICAL APPLICATIONS
ONE-SHOT MULTIVIBRATOR WITH INPUT LOCK-OUT
V+
1Mn
1Mn
10Ma
560kn
15kO
:::IE~+
>-+-oVO
to
"
T "" O.3mSEC
l00kn
lOMn
100pF
62kn
ONE-SHOT MULTIVIBRATOR
240kn
I
BURN-IN CIRCUIT
~~o-......--------<,.............- -.......-----.-o?:~
V+
V+l
0-
to
lMn
100pF
o-jl-t----t--I
+VIN
"
+36Vo-,/+--t---:------j-----j--t--o+36V
MIL-8TD.IJ83, METHOD 1015, CONDITION B
DRIVING CMOS
DRIVING TTL
••DV
PAGE 7-40
MATCHED
TRANSISTORS
MATCHED TRANSISTORS
INDEX
PRODUCT
TITLE
MAT-01
Ultra-Matched Monolithic Dual Transistor ...........................••..•...........•........ 8-4
PAGE
INTRODUCTION
BROADBAND NOISE VOLTAGE (enRMS>
Matched transistors such as the MAT-01 have applications in
a variety of systems from temperature sensors to analog
multipliers. The inherent close. thermal proximity resulting
from single-chip construction minimizes the errors introduced by temperature excursions.
The root-mean-square noise voltage referred to the input in
a specified bandwidth at a speCified collector voltage and
current.
Other useful characteristics of matched transistors include
log conformity for use in analog multiplier applications,
emitter-base voltage matching for amplifier front-end circuits, and a large matched hFE for current mirrors.
CURRENT GAIN MATCH ~hFe)
The difference In hFE between the transistors at a specified
voltage and current, expressed as a percentage of the I.ower
of the two hFE's.
I -
The MAHl1 consists of four hlgh-gain transistors connected In cross-coupled pairs for excellent thermal tracking.
The experience PMI has gained in the manufacture of PrecIsion op amps has been applied to the MAT-01. The result is a
matched tranSistor pair that exhibits low noise, low
leakage, and low drift.
hFEl X 100
hFE2
NOISE VOLTAGE (8np-p)
The peak-to-peak noise voltage referred to the input in a
specified bandwidth at a specified collector voltage and
current.
NOISE VOLTAGE DENSITY (e,.)
The rms noise voltage referred to the input within a 1Hz band
centered on a specified frequency. It is measured at a
specified collector voltage and current.
DEFINITIONS
AVERAGE OFFSET CURRENT DRIFT (TCloS>
OFFSET CURRENT (loS>
The ratio of the change in los to the change in temperature
producing It.
The difference between the base currents at a specified collector voltage and current.
AVERAGE OFFSET VOLTAGE DRIFT (TCVes>
OFFSET CURRENT CHANGE (aloslaVca)
The ratio of the change In Vos to the change in temperature
prodUCing it.
The ratio of the change in offset current to the change in
collector-base voltage producing It.
BIAS CURRENT (Ia)
OFFSET VOLTAGE (VoS>
The average of the base currents at a specified collector
voltage and current.
The difference between the base-emltter voltages (VaElVaEl!l at a specified collector voltage and current.
PAGEB·2
CROSS REFERENCE -
MAT·01 TO MONOLITHIC DUAL TRANSISTORS (Ic = 10pA)
DEVICE
BVCEO
MIN
(y)
Vos
MAX
(my)
TCVos
MAX
(I'V/oC)
hFE
MIN
los
MAX
(nA)
45
60
60
0.1
0.1
0.5
0.5
0.5
2.0
0.5
2.0
3.0
1.5
1.0
0.5
1.0
0.5
0.5
1.8
1.8
2.0
10
2.0
10
15
7.5
5.0
2.5
5.0
500
330
250
250
500
250
250
250
100
200
400
200
200
0.6
0.8
3.2
3.2
2.0
10
2.0
10
2.0
10
2.5
5
10
MAT·01AH
MAT·01H
MAT·01FH
MAT'()10H
LM114A
LM114
LM115A
LM115
A08lO)
AD811
AD812
AD813
AD818
45
45
45
60
60
35
45
DISCONTINUED 35
45
20
CROSS REFERENCE -
TClos
MAX
(pAloC)
90
110
150
150
600
300
300
300
300
MAT·01 TO 2N TYPES (Ic = 10pA)
BVCEO
MIN
(V)
Vos
MAX
(my)
TCVos
MAX
(I'v/oC)
hFE
MIN
%hFE
MATCH
MAX
los
MAX
(nA)
TClos
MAX
(pAl·C)
MAT·010H
2N2639
2N2640
2N2642
2N2643
2N2915
2N2915A
2N2916
2N2916A
2N2917
2N2918
45
45
45
45
45
45
45
45
45
45
45
0.5
5.0
10
5.0
10
3.0
2.0
5.0
2.0
10
5.0
1.8
10
20
10
20
10
5.0
10
5.0
20
20
250
50
50
100
100
60
60
150
150
60
150
8
10
20
10
20
10
15
10
15
20
20
3.2
20
40
10
20
17
26
7
10
17
7
150
1000
2000
500
375
600
900
N.C.
300
1450
750
MAT·01FH
2N2919
2N2919A
2N2920
2N2920A
2N2060
2N2060A
2N2060B
60
60
60
60
60
60
60
60
0.5
3.0
1.5
3.0
1.5
5.0
3.0
1.5
1.8
10
5.0
10
5.0
10
5.0
5.0
250
60
60
150
150
25
25
25
8
10
10
10
10
10
10
10
3.2
17
17
7
7
40
40
40
150
600
600
N.C.
300
N.C.
N.C.
N.C.
DEVICE
NOTES:
I. TClos Max and los Max calculated from published data.
2. N.C. = Insufficient published data to calculate.
3.
All of the abcve are physically Interchangeable pln·for·pln with MAT-01 series.
PAGE 1·3
•
~
~
::E
1/1
IE:
0
I1/1
iii
z
C
IE:
I-
aw
%
(J
~
::E
PMI
MAT-Ol
ULTRA-MATCHED MONOLITHIC
DUAL TRANSISTOR
®
EXCELLENT LOG CONFORMANCE
FEATURES
GENERAL DESCRIPTION
•
The MAT-01 series are monolithic ultra-tightly matched dual
NPN transistors, fabricated using an exclusive Silicon Nitride
"Triple-Passivation" process which provides extreme stability of critical parameters versus both temperature and time.
Outstanding matching characteristics include offset voltage
of 40pV, temperature drift of Vos of 0.15pV/oC and hFE
matching of 0.7%. Very high hFEis provided over a six decade
range of collector current, including an exceptional hFE of
590 at Ic = 10nAI Excellent logarithmic conformance over a
seven decade collector current span suggests application in
log/antilog and multiplier/divider circuitry. The very low
values of noise voltage and current make the MAT-01 ideal
for usage in critical low-level input stages while the 6-pin
TO-99 package allows direct replacement of most previous
dual transistors for immediate performance improvements.
The very high h FE at low collector currents also makes the
MAT-01 attractive in all high impedance and micropower
circuit designs.
•
•
•
•
•
•
•
•
•
•
Tight VOS (VBE Match) .........•....... 40pV Typical,
100pV Maximum
Low TCVos ... 0.15pVloC Typical, 0.5pV/oC Maximum
Tight hFE Match ...••.... 0.7% Typical, 3.0% Maximum
High hFE ..•....•..•.•...... 77- Typical, 500 Minimum
Excellent hFE Linearity from 10nA to 10mA
High hFE at Low Ie ........... 590 Typical @ Ie = 10nA
Low Noise Voltage ........ 0.23pVp _p - 0.1Hz to 10Hz
Excellent Long-Term Stability ... 0.2pVlMonth, Typical
High Breakdown •..•.......... 45V and 60V Minimum
Precision Logarithmic Conformance
Direct Replacement for Most Dual Transistors
ORDERING INFORMATIONt
TA=25°C
VosMAX
(mV)
PACKAGE
OPERATING
TEMPERATURE
RANGE
0.1
0.1
0.5
0.5
MAT01AH"
MAT01H"
MAT01GH"
MAT01FH"
MIL
MIL
MIL
MIL
PIN CONNECTIONS
C§'7'7
8'2
NOTE: Substrate is connected to case
6~
* Also available with MIL-STD-8838 Processing. To order add /883 as a suffix to
the part number.
E13
t All listed parts are available with 160 hour burn-in. See Ordering Information,
5 E2
Section 2.
ABSOLUTE MAXIMUM RATINGS (Note 4)
Collector-Base Voltage (BVCBO)
MAT-01AH, GH, N ..............................
MAT-01H, FH .........•.................•.......
Collector-Emitter Voltage (BVcEol
MAT-01AH, GH, N ..........•................•..
MAT-01H, FH ...................................
Collector-Collector Voltage (BVccl
MAT-01AH, GH, N .....•......•.•...............
MAT-01H, FH ...................................
Emitter-Emitter Voltage (BVEE)
MAT-01AH, GH, N ..............................
MAT-01H, FH ...................................
45V
60V
45V
60V
45V
60V
Emitter-Base Voltage (BVEBO) (Note 1) ...............• 5V
Collector Current (lcJ ............................. 25mA
Emitter Current (IEl ............................... 25mA
Total Power Dissipation
Clj,Se Temperature :540°C (Note 2) .............. 1.8W
Ambient Temperaure:5 70·C (Note 3) .......... 500mW
Operating Ambient Temperature ....... -55·C to +125·C
Operating Junction Temperature ........ -55· C to +150° C
Storage Temperature ................•.. -65°C to +150°C
Lead Temperature (Soldering, 60 sec) ...•......•. 300°C
DICE Junction Temperature ••..•... , •. -65· C to + 150· C
45V
60V
NOTES:
1. Application of reverse bias voltages in excess of rating shown can result in
degradation of hFEand hFEmatching characteristics. Do not attempt to
measure BV EBO greater than the 5V rating shown.
2.
Rating applies to applications using heat sinking to control case temperature. Derate linearly at 16.4mW/O C for case temperatures above 40° C.
3. Rating applies to applications not using heat sinking; device in free air
only. Derate linearly at 6.3mWrC for ambient temperatures above 70 0 e.
4. Absolute maximum ratings apply to both DICE and packaged devices.
PAGE 8-4
MAT-01 ULTRA-MATCHED MONOLITHIC DUAL TRANSISTOR
ELECTRICAL CHARACTERISTICS
at VeB ; 15V, Ie; 10"A, T A ; 25° C, unless otherwise noted.
MAT-D1AH
PARAMETER
SYMBOL
CONDITIONS
MIN
Breakdown Voltage
Offset Voltage
TYP
MAT-D1GH
MAX
MIN
TYP
MAX
UNITS
0.10
0.5
mV
v
45
45
0.04
Vas
0.1
Offset Voltage Stability
First Month
Long-Term
VOS/Time
Offset Current
lOS
Bias Current
Ie
(Note 1)
(Note 2)
2.0
0.2
Ie; 10nA
le= 10l'A
le= 10mA
Current Gain
2.0
0.2
0.1
0.6
0.2
3.2
nA
13
20
18
40
nA
590
770
500
250
840
0.7
Current Gain Match
100nA,;; Ie';; 10mA
Low Frequency Noise
Voltage
Broadband Noise
Voltage
I'V/Mo
3.0
1.0
1.2
8.0
0.4
0.23
0.4
0.8
0.1Hz to 10Hz (Note 3)
0.23
1Hz to 10kHz
0.60
430
560
610
%
II
0.60
7.0
9.0
7.0
9.0
6.1
6.0
7.6
7.5
6.1
6.0
7.6
7.5
Offset Voltage Change
0.5
3.0
0.8
8.0
Offset Current Change
2.0
15
3.0
70
pAN
II)
VeB = 30V, IE= 0
(Note 4)
15
50
25
200
pA
l-
veE = 30V, VeE = 0
(Note 4)
50
200
90
400
pA
o
20
200
30
400
pA
II:
l-
0.20
0.12
0.8
0.25
V
l:
450
MHz
2.8
2.8
pF
!c:::E
8.5
8.5
pF
Noise
fo = 10Hz
fo= 100Hz (Note 3)
to = 1000Hz
Voltage Density
Collector-Base
Leakage Current
leBO
Collector-Emitter
Leakage Current
II)
Collector-Collector
Leakage Current
lee
Vee
Collector Saturation
Voltage
VeE(SAT)
le= 0.1mA,le= 1mA
le= 1mA,le= 10mA
0.12
0.8
veE = 10V, Ie = 10mA
450
Gain-Bandwidth Product
Output Capacitance
Collector-Collector
Capacitance
= 30V
Vee 15V, IE = 0
C ee
ELECTRICAL CHARACTERISTICS
SYMBOL
Offset Voltage
Vas
Average Offset
Voltage Drift
TCVOS
Offset Current
lOS
Average Offset
Current Drift
TCIOS
CONDITIONS
MIN
(Note 5)
(Note 5)
Bias Current
Current Gain
167
MAT-D1GH
TYP
MAX
TYP
MAX
0.06
0.15
0.14
0.70
mV
0.15
0.:;0
0.35
1.8
~V/"C
0.9
8.0
1.5
15.0
nA
10
90
15
150
pA/OC
28
60
36
130
nA
MIN
77
400
UNITS
300
Collector-Base
Leakage Current
leBO
TA = 125"C, Vee = 30V,
IE = 0 (Not'; 4)
15
80
25
200
nA
Collector-Emitter
Leakage Current
leEs
TA = 125"C, VeE = 30V,
VBE 0 (Note 4)
50
300
90
400
nA
Collector-Collector
Leakage Current
lee
TA = 125"C, Vee = 30V
30
200
50
400
nA
=
NOTES:
3.
Sample tested.
1.
Exclude first hour of operation to allow for stabilization of external
circuitry.
4.
2.
Parameter describes long-term average drift trend after first month of
operation.
The collector-base (leBO) and collector-emitter (I CEO) leakage currents
may be reduced by a factor of two to ten times by connecting the substrate
(package) to a potential which is lower than either collector voltage.
5.
Guaranteed by design.
PAGE 8-5
~
e
w
at Vee; 15V, Ie; 10"A, -55°C ,;;TA ,;;+125°C, unless otherwise noted
MAT-D1AH
PARAMETER
II:
o
(J
MAT-01 ULTRA-MATCHED DUAL TRANSISTOR SERIES
ELECTRICAL CHARACTERISTICS
at Vca = 15V, Ic = 10llA, TA = 25'C, unless otherwise noted.
MAT-G1H
PARAMETER
SYMBOL
Breakdown Voltage
BVCEO
Offset Voltage
Vas
Offset Voltage Stability
First Month
Vas/Time
Long-Term
CONDITIONS
la
Current Gain
hFE
Ic= 10nA
IC= 10"A
Ic= lamA
Current Gain Match
.lhFE
laOnA sic slOmA
Low Frequency Noise
Voltage
8 np- p
MIN
TYP
MAX
UNITS
0.10
0.5
mV
60
(Note 1)
(Note 2)
los
0.1
2.0
0.2
2.0
0.2
"VlMo
0.1
0.8
0.2
3.2
nA
15
30
18
40
nA
520
680
740
330
V
250
430
560
610
0.7
0.8
2.7
1.0
1.2
8.0
0.1 Hz to 10Hz (Note 3)
0.23
0.4
0.23
0.4
8 nRMS
1Hz to 10kHz
0.60
en
10= 10Hz
10= 100Hz I Note 3)
10= 1000Hz
7.0
6.1
6.0
9.0
7.6
7.5
7.0
6.1
6.0
9.0
7.6
7.5
Noise
Voltage Density
MAT-G1FH
MAX
0.04
Bias Current
Voltage
TYP
60
Offset Current
Broadband NOise
MIN
0.60
%
"Vp-p
"VRMS
nVl.I"HZ
Offset Voltage Change
.lVos/.lVca
a sVcas45V
0.5
3.0
0.8
8.0
"VlV
Offset Current Change
.llosl.lVca
OsVca s45V
2.0
15
3.0
70
pAN
Icao
Vca=45V.IE=0
INote 4)
15
50
25
200
pA
ICES
VCE = 45V, VaE = a
(Note 4)
50
200
90
400
pA
pA
Collector-Base
Leakage Current
Collector-Emitter
Leakage Current
Collector-Collector
Icc
Vee = 45V
20
200
30
400
Collector Saturation
Voltage
VCEISAT)
la= O.lmA. Ic= lmA
la= lmA,lc= lamA
0.12
0.8
0.20
0.12
0.6
0.25
Gain-Bandwidth Product
IT
VCE = 10V, Ic = lamA
450
450
MHz
Output Capacitance
COb
VCE = 15V. le=O
2.8
2.8
pF
Vcc=O
8.5
8.5
pF
Leakage Current
Collector-Collector
Capacitance
C cc
ELECTRICAL CHARACTERISTICS
at Vca = 15V, Ic = 10llA, -55'C STA S +125'C, unless otherwise noted
MAT-G1FH
MAT-G1H
PARAMETER
SYMBOL
Offset Voltage
Vas
Average Offset
Voltage Drilt
TCVos
Offset Current
los
Average Offset
Current Drift
TCl os
Bias Current
la
Current Gain
hFE
Collector-Base
Leakage Current
Icao
Collector-Emitter
ICES
Leakage Current
Collector-Collector
Leakage Current
CONDITIONS
MIN
INote 5)
(Note 5)
105
TYP
MAX
TYP
MAX
UNITS
0.06
0.15
0.14
0.70
mV
0.15
0.50
0.35
1.8
"VI'C
0.9
9.0
1.5
15:0
nA
11
110
15
150
pN'C
30
95
36
130
nA
nA
350
MIN
77
300
TA = 125'C. Vca=45V,
IE = 0 (Note 4)
15
80
25
200
TA = 12S'C, VCE=45V,
50
300
90
400
30
200
50
400
VaE = 0 (Note 4)
Icc
V
TA = 125'C, Vcc= 45V
nA
nA
NOTES:
3. Sample tested.
1. Exclude first hour of operation to allow for stabilization of external
4. The collector-base (I cao> and collector-emltter (I CEO> leakage currents
may be reduced by a lactorol two to ten times by connecting the .ubstrate
(package) to a potential which is lower than either collector voltage.
5. Guaranteed by design.
circuitry.
2. Parameter describes long-term averege drift trend alter lirst month 01
operation.
PAGE 8-8
MAT-Ol ULTRA-MATCHED DUAL TRANSISTOR SERIES
DICE CHARACTERISTICS
1. COLLECTOR (1)
2. BASE (1)
3. EMITTER (1)
5. EMITTER (2)
6. BASE (2)
7. COLLECTOR (2)
DIE SIZE 0.035 x 0.025 Inch
Refer 10 Secllon 2 for addilional DICE Informallon
ELECTRICAL CHARACTERISTICS at 2So C for V CB = 1SV and Ic = 10!,A, unless otherwise noted.
MAT-01N
PARAMETER
SYMBOL
Breakdown Voltage
BV CEO
Offset Voltage
CONDITIONS
LIMITS
UNITS
45
VMIN
Vos
0.5
mVMAX
Offset Current
los
3.2
nAMAX
Bias Current
la
40
nAMAX
Current Gain
hFE
250
MIN
Current Gain Match
~hFE
8.0
% MAX
Offset Voltage Change
~Vosf~Vca
OSV ca S30V
8.0
"VNMAX
Offset Voltage Change
~los/~Vca
OS Vca S30V
70
pAN MAX
Collector-Base-Leakage Current
Icao
V ca =30V,I E=0
200
pAMAX
Collector-Emitter-Leakage Current
ICES
VcE =30V,V aE =0
400
pAMAX
Collector Saturation Voltage
VeE (SAT)
la=O.lmA, Ic= lmA
0.25
V MAX
TYPICAL ELECTRICAL CHARACTERISTICS at Vce = 1SV and Ic = 10!,A, TA = 2SoC, unless otherwise noted.
MAT-01N
PARAMETER
SYMBOL
Average Ollset Voltage Drift
TCVos
Average Offset Current Drift
TClos
Gain Bandwidth Product
IT
~VosfT
Offset Voltage Stability
CONDITIONS
UNITS
0.35
"VI'C
15
pAl'C
V CE = 10V, Ic= 10mA
450
MHz
First Month (Note 1)
Long-Term (Note 2)
2.0
0.2
"VlMo
NOTES:
1.
TYPICAL
Exclude first hour of operation to allow for stabilization of external
circuitry.
2. Parameter describes long-term average drift after first month of operation.
PAGE 8-7
•
MAT-01 ULTRA.MATCHEDDUAL TRANSISTOR SERIES
TYPICAL PERFORMANCE CURVES
OFFSET VOLTAGE
vs TEMPERATURE
200
'10
~
~
MAT-O'F_
~~
- --
OV<'vcfI""IN
---
V
Io
o
-60
.
~AT.O!A
g4
to
~
2
o
~
~-2
./
• BOO
z
L
~
./
ili400
a:
.
a
/..
.. -'0
'00
125
150
1
2
3
4
6
8
7
8
'oA
r--r-r--r-;-""T-'-,---r--:l
TA "26°C
""DEVI~TI~ IF~OM
"
TIME (MONTHS)
ti
TA "'25c C _
V eB = 15V
2OOI-....L--l_.l-..J.._l...-...l--1.......J
,~
10Qs1;A 1rnA 10mA 100rnA
-16 -50
COLLECTOR CURRENT· Ie
r---r--r---r--r--,
I
MAT..'
NOISE VOLTAGE DENSITY
1'00 1-_-+__ TA "'25 C
~
j
0
-26
0
25
&0
i ~'!!II~~I!~~~II
~.,L.-~~W-~~~~~~L.-L.U~~
0.01
0.1
,~O
I¥'1
MAT..o1
!c
i
a '.0
MAT.O'V/
'e =1~A TYPICAL
li1
Ie = 3Oo,...A TYPICAL
/
/
~
~'~~,--~-~,.-----,oo~---,~.----~Uk
uno
'000
~ '0.• \------.1:--+--1---+---1
a:
10.0
GAIN·BANDWIDTH
vs COLLECTOR CURRENT
NOISE CURRENT DENSITY
NOISE CURRENT DENSITY
TA =2s<'C
Do
~
w
1.0
COLLECTOR CURRENT (mAl
TEMPERATURE (t)
NOISE VOLTAGE
~
DEVICE''C''
MAT-01
/~
1nA 10nA 100nA 'lolA
I~
-
~-
"""
o
'::'?
-
~
"
~
V-
I
VJ
~ 1~
~-8
a
200
'000
•
.... ~.~-
3-8
J
;
1\\
G -4.
CURRENT GAIN
vs COLLECTOR CURRENT
BOO
ri
!,..o"
fl."i'--
6"
/
I--~....-+---""I:-'-:':':':'-F---I
~
~
I
----,L..--""""'••,
O.'o.L,----.....--......--......;:......
FREQUENCY (Hz)
PAGES..
TA -2SOC_
V eE ·1OV
/
/
10s1A
1(JOpA
1mA
10rnA
COLLECTOR CURRENT
100mA
MAT-01 ULTRA-MATCHED DUAL TRANSISTOR SERIES
MAT-01 TEST CIRCUITS
MAT-01 MATCHING MEASUREMENT CIRCUIT
+16.5V
+1S.6V
VOUT
,OOkIl
,%
TEST
SIA
SIB
Vos
X
X
VOUT,
1mV per volt
los
0
0
V OUT2 -VOUT,
1nA per volt
10OkO
",
UNITS
•
Iii
~
:I
v-
II)
II:
0
t;
iii
z
C
MAT-01 NOISE MEASUREMENT CIRCUIT
II:
l-
e
+'6V
III
%
."'''
CJ
~
:I
+15V
3.3kn
VOl
4k1l
LOW
FREQUENCY
NOISE
":"
-15V
• Matched to O.Ot%
TEST
Noise Voltage Density
SI A SI 8 S2
X
A
VO
0
0
X
A
vo/..j2J:i:O
X
X
0
B
V02
(Per Transistor)
Low Frequency Noise
(Referred to Input)
/.J'2
X
(Per Transistor)
Noise Current Density
READING
S3
X
PAGE 8-9
PEAK-TO-PEAK
25,000
MAT-01 ULTRA-MATCHED DUAL TRANSISTOR SERIES
PRECISION OPERATIONAL AMPLIFIERS
APPLICATION NOTES
Application of reverse bias voltages to the emitter-base junctions in excess of ratings (5V) may result in degradation of
hFE and hFE matching characteristics; circuit designs should
be checked to insure that such reverse bias voltages cannot
be applied during transient conditions, such as at circuit
turn-on and turn-off.
+16V
+16V
The designer is cautioned that stray thermoelectric voltages
generated by dissimilar metals at the contacts to the input
terminals can prevent realization of the drift performance
indicated. Best operation will be obtained when both input
terminals are maintained at the same temperature, preferably close to the temperature of the device's package.
RL-
TYPICAL APPLICATIONS
PRECISION REFERENCE
-1SV
THIS CONFIGURATION CAN ALSO BE USED WITH THE lOW POWER OP·21.0R
MICROPOWER op..zo TO ACHIEVE A LOW NOISI:: AND LOW POWER PRECISION
Op·AMP.
...-------~----oVREF
vos
Maximum
TCVos
Maximum
...-----~-------~ C2
los
Maximum
Ie
Maximum
VREF ,.. 7.0V
TCVREF .., 10~C
RO ,.. 40Il
Gain
Minimum
MAT.o1AH
OP-02A
O.15mV
MAT.o1AH
OP.(I2A
O.27mV
MAT.o1GH
OP.o2
O.65mV
MAT.o1GH
OP.(12
1.2mV
D.6I1-Vlo O
,,,,vrc
2/AV/oC
4p.V/oC
O.8nA
a.lnA
3.2nA
O.32nA
20nA
2nA
40nA
4nA
800.000
2.000.000
2.000.000
800.000
CAUSE A POSITIVE CHANGE IN TeVAEF.
IS
2O.A
2.A
20p.A
2.A
NOTE: hFE OF 01 WILL BE REDUCED BV OPERATION OF BREAKDOWN
RL
100k{l
1MIl
100kn
lMn
A1 MAY BE ADJUSTED TO MINIMIZE TCVREF. INCREASING A1 WILL
MODE.
PAGE 8-10
MAT-01 ULTRA-MATCHED DUAL TRANSISTOR SERIES
COMPLETE SCHEMATIC - TEMPERATURE MEASUREMENT SYSTEM
I
SENSING
PAIR
,
2 (
"-
'H~
" •
{
UPTO
100 FEET
.
7
v!Q'.~
.....MAT..
"\
)
R,
R2
lOQkO
BOOn
"
d-
./
SHIELDED
PAIR
CABLE
r- ,...
R8
Ii
+15V
V
\.
"
./
,
"
2(
I "-
7
v.;A~'G:;-'"
'"
#'I
" •
R'
100kn
OFFSET ADJUST
~
I\,
R"
8011n
"
SOURCE
8
.J
,. r.-
~~
":'
,:RRENT
~,
A'A ......
•
>--
;/
,.
I
-15V
+15V
,"
DIFfERENTIAL
A'
OP·1DCY
7
1Q
AMPLIFIER
.-
"
f':',.
•
A'B
EO = 10
V1
5
C-'OV
R8
..
AS
180kO
,"
R6
'00k"
'"
..."
R7
~
RATIO
ADJUST
-16V
BASIC DIGITAL THERMOMETER READOUT IN
DEGREES KELVIN (oK)
DIGITAL THERMOMETER WITH READOUT IN
SENSING
PAIR
MAT·D1H
°c
OK
EO
-56°C· 21B"K" 2.18V
+2&OC '" ZB8"K '" 2.88V
+125°C • 388"K • 3.98V
NOTE:
For a complete discussion of the circuits above, see Application Note
12, "Temperature Measurement Method Based on Matched Transistor
Pair Requires No Reference",
PAGE 8-11
°c
II
VOLTAGE
REFERENCES
VOLTAGE REFERENCES
INDEX
PRODUCT
REF-01
REF-02
REF-OS
REF-10
PAGE
TITLE
+10V Precision Voltage Reference .......................................................... 9-3
+SV Precision Voltage Reference/Temperature Transducer .................................. 9-10
+SV Precision Voltage Reference With Guaranteed Long-Term Stability ...................... 9-19
+10V Precision Voltage Reference With Guaranteed Long-Term Stability ..................... 9-26
INTRODUCTION
Voltage references must provide a constant output voltage
irrespective of changes In Input voltage, output current or
temperature. References find applications In many design
situations: D to A's, power supplies, cold junction ther·
mistor compensation circuits, A to D's, panel meters,
calibration standards, precision current sources, and con·
trol set·point circuits.
Line regulation, load regulation (output impedance) and
temperature coefficient specifications Indicate how close a
reference resembles an Ideal voltage source. Line regula·
tion speCifies reference output voltage vs. input voltage
changes. Output voltage changes due to load current varia·
tions are reflected by load regulation specifications.
Temperature coefficient specifications Indicate output
voltage variation over temperature.
control of processing has enabled PMI to specify limits on
output change with time.
Present·day references are based on zener diodes or bandgap generated voltages. Zeners characteristically exhibit
high power dissipation and poor noise specifications. Bandgap voltage reference designs sum voltages with negative
and positive temperature coefficients to yield stable output
voltages over temperature. A transistor base emitter junction voltage (V BE ) exhibits a negatlYe temperature coefficient. Two transistors operating with unequal current densi·
ties will have different VBES and the difference, .:1VBE, exhibits a positive temperature coefficient. When .:1VBE Is
amplified and added to VBE, a voltage level of near zero
temperature coefficient results if the sum equals 1.23V. (See
AN-18 for bandgap reference theory.) The 1.23V level then Is
amplified to provide stable output voltages of +S.OO and
+10.00V.
The absolute difference between the maximum output
voltage and the minimum output voltage over the specified
temperature range expressed as a percentage of the typical
output voltage.
.:1VOT= VMAX - VMIN X 100
Vo (Typical)
PMI's exclusive "Zener Zapping" technique allows for trimming of the .:1VBE amplification factor to insure low output
voltage temperature coefficients. Additional zapping trims
the output's absolute value within specified limits.
The REF-01 and REF-02 are stable +10.00V and +S.OOV
monolithic bandgap Yoltage references. Output voltages are
adjustable for precision applications with small effect on
output voltage temperature coefficients. The REF-02 provides an additional output voltage that has a linear
temperature dependence. (See AN-18).
The REF-QS and REF-10 are premium versions of the REF-01
and REF-02 that have guaranteed long-term stability. Extensive testing over a long period of time, combined with tight
DEFINITIONS
LINE REGULATION
The ratio of the change in output voltage to the change in input (line) voltage producing it. It includes the effects of selfheating.
LOAD REGULATION
The ratio of the change in output voltage to the change in
load current. It Includes the effects of self-heating.
OUTPUT CHANGE WITH TEMPERATURE (.:1Vor)
OUTPUT TEMPERATURE COEFFICIENT (TCVo)
The ratio of the output change with temperature to the
specified temperature range expressed in ppm/'C. For ex·
ample, TCVo is defined as .:1VoT divided by the temperature
range; i.e.,
TCVo(O'to + 70'C) = .:1VOT(O'tO + 70'C
70'C
.:1VOT(-SS'to
+12S'C)
andTCVo(-SS'to +12S'C) =
180'C
OUTPUT TURN-ON SETTLING TIME (tON)
The time required for the output voltage to reach its final
value within a specified error band after application of VIN.
OUTPUT VOLTAGE NOISE (enpoP!
The peak-to-peak output noise voltage within a specified
frequency band.
QUIESCENT SUPPLY CURRENT (lSY)
The current required from the supply to operate the device
with no load.
PAGE 9-2
REF-Ol
PMI
+ lOV PRECISION VOLTAGE REFERENCE
®
FEATURES
GENERAL DESCRIPTION
•
•
•
•
•
•
•
•
•
•
The REF·Ol Precision Voltage Reference provides a stable
+ 10V output which can be adjusted over a ±3% range with
minimal effect on temperature stability. Single supply
operation over an input voltage range of l2V to 40V,Iow current drain of lmA, and excellent temperature stability are
achieved with an improved bandgap design. Low cost, low
nOise and low power make the REF·Ol an excellent choice
whenever a stable voltage reference is required. Applications include DIA and AID converters, portable instrumen·
tation, and digital voltmeters. Full miltary temperature
range devices with screening to MIL-STD-883 are available.
For guaranteed long term drift see REF-l0 data sheet.
10 Volt Output ..............•.......•....••... ±o.3%
Adjustment Range ••....•..•.•••..•..•.•.••...•. ±3%
Excellent Temperature Stability .....•.....•. 3ppm/oC
Low Noise ....•.......................••.••. 20I'Vp-p
Low Power .......•...•.....•••....•••••.••... 15mW
Wide Input Voltage Range ..........•....• 12V to 40V
High Load Driving Capability .......•.....•.... 20mA
No External Components
Short Circuit Proof
MIL-STD-883 Screening Available
ORDERING INFORMATIONt
PACKAGE
(mV)
TO-_
a-PIN
HERMETIC
DIP
8-PIN
± 30
± 30
± 50
± 50
± 100
± 150
REF01AJ'
REF01EJ
REF01J'
REF01HJ
REF01CJ
REF01DJ
REF01AZ'
REF01EZ
REF01Z'
REF01HZ
REF01CZ
REF01DZ
TA = 25°C
AVo MAX
II
PIN CONNECTIONS
PLASTIC
DIP
a-PIN
OPERATING
TEMP.
RANGE
REF01HP
REF01CP
REF01DP
MIL
COM
MIL
COM
COM
COM
N.C.
•
~IU
NOC·07N.CO
VIN 2
a:
6 VOUT
N.C. 3
II)
5 TRIM
EPOXY B MINI·DIP
(P·Sufflx)
4
GROUND
t All listed parts are available with 160 hour burn-in. See Ordering Information,
Z
IU
a:
IU
ICASE)
, Also available with Mil-STD-883B processing. To order add/883 as a suffix to
the part number.
IU
to)
8-PIN HERMETIC DIP
TO·99
(J·Sufllx)
(Z·Sufflx)
I&.
IU
a:
IU
CJ
c
Section 2.
!:i
o
>
SIMPLIFIED SCHEMATIC
~------~--------------~--~IN~T
2
R15
Ql.
OUTPUT
6
ft3
R12'" 16.7k
R9"" 50k
TRIM
5
ftl
Rll
ftl.
~
2k
ft2
4
--*-"---<> GftOUND
PAGE 9-3
REF·01 +10V PRECISION VOLTAGE REFERENCE
ABSOLUTE MAXIMUM RATINGS (Note 2)
DICE Junction Temperature (Tj) ••••••• -65· C to +150· C
Lead Temperature (Soldering, 60 sec.) •.•.•.••••• 300·C
Input Voltage
REF-01, A, E, H, All DICE except GR •..•..•..... 40V
REF-01C, D, GR DICE only ..................... 30V
Power Dissipation (Note 1) ••••...••••.••••••.•• 500mW
Output Short Circuit Duration •...••...•••.•.• Indefinite
(to ground or VIN)
Storage Temperature Range
J and Z Packages ................. , -65· C to 150· C
P Package ......................... -65· C to + 125· C
Operating Temperature Range
REF-01A, REF-01 .................. -55·C to + 125·C
REF-01E, REF-D1H
REF-01O, REF-01 C .................... O· C to + 70· C
NOTES:
1. See table for maximum ambient temperature rating and derating factor.
+
ELECTRICAL CHARACTERISTICS
at VIN
= + 15V, TA = 25 'C,
MAXIMUM AMBIENT
TEMPERATURE
FOR RATING
DERATE ABOVE
MAXIMUM AMBIENT
TEMPERATURE
eo'c
7.1mWI'C
6.7mW/'C
5.6mWI'C
TO'99 (J)
e Pin Hermetic Dip (Z)
e Pin Plastic Dip (P)
2.
75'C
36'C
Abaolute maximum ratings apply to both packaged parts and dice. unless
otherwise noted.
unless otherwise noted.
REF-01A/E
TYP
MAX
REF-01/H
PARAMETER
SYMBOL
CONDITIONS
MIN
Output Voltage
Vo
IL=OmA
9.97 10.00 10.03
9.95 10.00 10.05
Output Adjustment Range
.aVtrim
Rp=10kll
±3.0
±3.0
Output Voltage Noise
enp·p
O.IHz to 10Hz
(Note 5)
Input Voltage Range
VIN
±3.3
MIN
TYP
±3.3
30
20
12
40
MAX
UNITS
V
%
30
20
12
~Vp·p
40
V
Line Regulation
(Note 4)
VIN = 13 to 33V
0.006 0.010
0.006 0.010
%IV
Load Regulation
(Note 4)
IL=O to 10mA
0.005 0.008
0.006 0.010
%/mA
Turn·on Settling Time
ton
To ± 0.1 % of final value
5.0
Quiescent Supply Current
ISY
No Load
1.0
Load Current
IL
10
21
10
21
mA
Sink Current
Is
-0.3
-0.5
-0.3
-0.5
mA
Short Circuit Current
Isc
30
mA
at VIN
,.sec.
1.0
30
Vo=O
ELECTRICAL CHARACTERISTICS
5.0
1.4
1.4
mA
= + 15V, - 55'C sTA s + 125 'C and IL =OmA, unless otherwise noted.
REF-01/H
REF-01A/E
PARAMETER
SYMBOL
CONDITIONS
Output Voltage Change
with Temperature
(Notes 1 and 2)
AVOT
O'sTAs +70'C
-55'sTA s +125'C
Output Voltage
Temperature Coefficient
TCVo
MIN
TYP
MAX
0.02
0.06
MIN
TYP
MAX
UNITS
0.06
0.15
0.07
0.18
0.17
0.45
%
8.5
10.0
25.0
ppmf'C
(Note 3)
3.0
Change In Vo Temperature
Coefficient with Output
Adjustment
Rp=10kll
0.7
Line Regulation
(V IN = 13 to 33V)
(Note 4)
O'sTAS +70'C
-55'sTAs +125'C
0.007 0.012
0.009 0.Q15
0.007 0.012
0.009 0.015
%/V
Load Regulation
(IL =0 to 8mA)
(Note 4)
O'sTAs +70'C
-55'sTA ", +125'C
0.006 0.010
0.007 0.012
0.007 0.012
0.009 0.015
O/O/mA
0.7
ppmf%
NOTES:
1. AVOT Is defined as the absolute difference between the maximum out·
put voltage and the minimum output voltage over the specified
temperature range expressed as a percentage of 10V:
AVOT=
VMAX-VMIN
10V
TCVo(O'to +70'C)=
AVOT O· to + 70'C
70'C
and TCVo (-55' to +125'C)=
X 100
2. AVOT specification applies trimmed to +10.000V or untrimmed.
3. TCVo Is defined as AV OT divided by the temperature range; i.e.,
AVOT -55 to +125'C
180'C
4. Line and Load Regulation specifications Include the effects of self
heating.
5. Guaranteed by design.
PAGE 9....
REF..Il1 +10Y PRECISION YOL TAGE REFERENCE
ELECTRICAL CHARACTERISTICS
at Y'N
=
+ l5V, TA = 25 'C, unless otherwise noted.
REF·01C
REF·01D
PARAMETER
SYMBOL
CONDITIONS
MIN
Output Voltage
Vo
IL=OmA
9.90 10.00 10.10
Output Adjustment Range
L\Vtr1m
Rp=10kll
±2.7
Output Voltage Noise
snp·p
0.1Hz to 10Hz (Note 5)
Input Voltage Range
Y,N
TYP
MAX
MIN
±3.3
±2.0
25
35
12
TYP
MAX
9.850 10.0010.150
±3.3
pVp·p
12
30
V
%fV
Line Regulation (Note 4)
Y'N = 13 to 30V
0.009 0.015
0.012
0.04
Load Regulation (Note 4)
IL=O to 8mA
IL=O to 4mA
0.006 0.015
0.006 0.015
0.009
0.04
Turn-on Settling Time
ton
To ±0.1% of final value
5.0
Quiescent Supply Current
ISY
No Load
1.0
5.0
1.6
V
%
25
30
UNITS
%JmA
ps
1.0
2.0
mA
Load Current
IL
8
21
8
21
mA
Sink Current
Is
-0.2
-0.5
-0.2
-0.5
mA
Short Circuit Current
Isc
30
mA
30
Vo=O
ELECTRICAL CHARACTERISTICS
at Y'N
=
+15V, O'CsTA s + 70'C, unless otherwise noted.
REF·01C
PARAMETER
SYMBOL
CONDITIONS
MIN
Output Voltage Change
with Temperature
1!"vOT
(Notes 1 and 2)
Output Voltage
Temperature Coefficient
TCV o
(Note 3)
REF·01D
TYP
MAX
0.14
20
TYP
MAX
UNITS
0.45
0.49
1.7
%
65
70
250
ppmf'C
Change in Vo
Temperature Coefficient
With Output Adjustment
Rp=10kll
Line Regulation (Note 4)
Y,N = 13 to 30V
0.011
Load Regulation (Note 4)
IL=O to 5 mA
0.008 0.018
MIN
II
~
II.
UI
II:
(I)
0.7
0.7
0.Q18
UI
ppmf%
U
Z
0.020 0.025
%IV
II:
0.025
%fmA
0.020
UI
UI
II.
UI
II:
NOTES:
UI
1. t;.VOT is defined as the absolute difference between the maximum output voitage and the minimum output voltage over the specified
temperature range expressed as a percentage of 10V:
t;.VOT
VMAX-VMIN
10V
3. TCVo is defined as t;.VOT divided by the temperature range; i.e.,
t;.VOT
TCVo= 70'C
2. t;.VOT specification applies trimmed to +10.000V or untrimmed.
5. Guaranteed by design.
OUTPUT ADJUSTMENT
put can also be set to exactly 10.000V, or to 10.240V for
binary applications.
Adjustment of the output does not significantly affect the
temperature performance of the device. Typically the
temperature coefficient change is 0.7 ppm/'C for 100mV
of output adjustment.
12+15V
V'N
Vo
•
OUTPUT
REF-Ol
TRIM
5
BURN .. IN CIRCUIT
lOKI!
GND
l'
rw.,
>kn
±10%
'ZN
1
V'N
REF.Q1
The REF-Ol trim terminal can be used to adjust the output
voltage over a 10V ±300mV range. This feature allows the
system designer to trim system errors by setting the
reference to a voltage other than 1OV _Of course, the outPAGE 1 ..5
~
o
4. Line and Load Regulation specifications Include the effects of self
heating.
X 100
c:J
;.J
GND
Lav
>
REF·01 +10V PRECISION VOLTAGE RI:FERENCE
DICE CHARACTERISTICS
2.
4.
5.
8.
INPUT VOLTAGE (Y,,.)
GROUNO
TRIM
OUTPUTYOLTAGE (Y OUT)
OlE SIZE 0.083 X 0.040 Inch
Refer to Section 2 for additional DICE Information
ELECTRICAL CHARACTERISTICS at Vs
= + 15V. TA = + 25°C. unless otherwise noted.
REF-01N
PARAMETER
SYMBOL
CONDITIONS
REF-01G
LIMIT
LIMIT
UNITS
10.05
9.85
10.20
9.80
V MAX
VMIN
Output Voltage
Vo
IL =0
10.05
9.95
Output Adjustment
Range
Vtrlm
Rp = lOkn
±3.0
± 2.7
Input Voltage Range
VIN
40
12
40
12
0.Q1
0.01
Line Regulation
VIN = 13V to 33V
VIN = 13V to 30V
TYPICAL ELECTRICAL CHARACTERISTICS at Vs
PARAMETER
SYMBOL
Load Regulation
REF-01GR
LIMIT
%MIN
30
12
V MAX
VMIN
%IV MAX
0.015
= ± 15V. TA = 25°C, unless otherwise noted.
REF-G1N
REF-G1G
CONDITIONS
TYPICAL
TYPICAL
IL =0 to lOmA
IL=Ot08mA
0.006
0.006
REF-01GR
TYPICAL
UNITS
'IbImA
0.006
Output Voltage Noise
Snp-p
O.lHz to 10Hz
20
20
25
"Vp_p
Turn-on Settling
Time
tON
To ± 0.01% of
Final Value
5.0
6.0
5.0
lIS
Quiescent Current
ISY
No Load
1.0
1.0
1.0
mA
Load Current
IL
21
21
21
mA
Sink Current
Is
0.5
0.5
0.5
mA
Short Circuit Current
Isc
30
30
30
mA
Output Voltage
Temperature Coafficlent
TCVo
10
10
20
ppm'oC
Vo =0
PAGE 9-6
REF·01 +10V PRECISION VOLTAGE REFERENCE
TYPICAL PERFORMANCE CURVES
OUTPUT WIDEBAND
NOISE va BANDWIDTH (O.1Hz
TO FREQUENCY INDICATED)
LINE REGULATION
va FREQUENCY
.
0....,
78
OUTPUT CHANGE DUE
TO THERMAL SHOCK
1Q,ooo
••03&
TA·2ErC
0..,
0.031
"
..,
0.1'
,.
•
11111.
100Hz
1kHz
10kHz
FREQUENCY
/
I
:>
..:il
~
L.D2D
,..
1.
I
,
I
2&
3D
/
,..
V
~
,..
51
.....
to'
./
t: 0.'
.:il ...'"'
VIN- 1SV
;
0..
-80 -40 -20
0..
0 20 40 10 8D 100 120 140
TEMPERATURE rCI
/'
",
V
,.- ~ i-"'"
~
,-
............
lID
80
0.1
-80 -40 -20
80 100 120 , .
TEMPERATURE 'OC)
PAGE 1·7
~III
II:
fa
u
Z
III
II:
~
III
II:
III
;.,
0 20 40 to 10 100 120 140
TEMPERATURE leC)
QUIESCENT CURRENT
va TEMPERATURE
'.1
II
"o~
-80 -40 -20
......
ZO
V
0.8
0.1
VI~. '~V
0
V
V
./
0..
-8O-tO -20
eo
;;
••1
' .......
VIN" 1SV
&0
v
~ 1.0
V
MAXIMUM LOAD CURRENT
va TEMPERATURE
.........
,eo
30
'.1
/
INPUT VOLTAGE (VOLTS)
.......
20
NORMALIZED LINE REGULATION
va TEMPERATURE
V
1.0
0.8
10
1.4
E
&1 0••
9
~
V
TIME (SECONDS)
~
TA"'25"C
/
I
V
-,.
'M
=
" 1.1
.
!!
-
fEY ICE IMMERSED
IN 7S"C OIL BATH
~
NORMALIZED LOAD
REGULATION ~L 10mA)
va TEMPERATURE
,..
§
0.010
~ 0.006
...
,.
'Ok
FREQUENCY (Hzl
'DO
'.1
DISSIPATION
I"
!o
.
:'11
'DO
.
u
~
TA· TA·
2S·C 75°C
o
z
, ,.
_wL~
2D
g .....
!~
I'
;:; 0.015
0
/
,.
Ii
S >-~
SHORT CIRCUIT PROTECTION
V
i!
:s 'DDD E
z
,0..
'MHz
100kHz
VINI. '.V I
!:;
~
MAXIMUM LOAD CURRENT
VB INPUT VOLTAGE
/
,.
!:;
~
~
3.,
1111111I11
10Hz
..
,..
VIN-15Y
TA '"' +25°C
Ii .....
VIN-16V
0 20 40 80 80 '00 120
TEMPERATURE 'OC)
,eo
>
REF-Ol 'lOY PRECISION YOLTAGE REFERENCE
TYPICAL APPLICATIONS
AID CONVERTER REFERENCE
DIA CONVERTER REFERENCE
+15V
ANALOG
INPUT
Q
TO +lOV
+15V
'0''''
LSB
MSB
+15V
S.Okn
-15V
+16V
-15V
B1 B2 B3 B4 B5 B6 B7 BB
POS FULL SCALE -1 LSB
1
1
1
1
0
VERSIONS.
+4.960
0
0
0
0
0
0
NEG FULL SCALE + 1 LSB
0
0
0
0
0
0
0
-4.960
NEG FULL SCALE
0
0
0
0
0
0
0
0 -5.000
ZERO SCALE
CONNECT "START" TO
"CONVERSION COMPLETE"
FOR CONTINUOUS CON-
E
0.000
CONVERSION TTL CLOCK
COMPLETE
INPUT 2.25MHz
±10V REFERENCE
+lSV
PRECISION CALIBRATION STANDARD
V'N
---"11mA
+10V
REF-01
1
V'N
,
6
Va
-9V
10k"
GNO
12
{
10kn
+1SV
REf·01
1
rv
-10V
10.000V
S
TRIM
GND
5""
lOOK
r
-
CURRENT SOURCE
CURRENT SINK
VOLTAGE COMPLIANCE:
12+15V
V'N
Va
+~OUT
-25V TO +3\1
V'N
fL--
REf·01
TRIM
VOLTAGE COMPLIANCE: -3V TO +25V
Va~
REF·01
f-o
R
TRIM
lOUT = 10":, +lmA
GND
GND
l'
l'
6
+'OUT
-15V
PAGE 9-8
f-o
R
lOUT = 10.:' +lmA
REF-01 +10V PRECISION VOLTAGE REFERENCE
PRECISION CURRENT SOURCE
REFERENCE STACK WITH EXCELLENT LINE REGULATION
A current source with 25V output compliance and excellent
output impedance can be obtained using this circuit. REF-01
®keeps the line voltage and power dissipation constant in
device CD; the only important error consideration at room
temperature is the negative supply rejection of the op amp.
The typical 3,N IV PSRR of the OP-02E will create an 8ppm
change (3,N IV x 25V J1OV) in output current over a 25V range;
for example, a 10mA current source can be built (R = 1kO) with
300MO output impedance.
R 25V
o - 8x10 6x10mA
Three REF-01's can be stacked to yield 10.000, 20.000 and
3O.OOOV outputs. An additional advantage is near·perfect line
regulation of the 10.000 and 20.000 output voltages. A 32V to
60V input change produces an output change which is less
than the noise voltage of the devices. A load bypass resistor
(R B) provides a path for the supply current (ISY) of the 20.OOOV
regulator.
In general, any number of REF·01's can be stacked this way.
For example, ten devices will yield outputs of 10, 20, 30 ...
1OOV. The line voltage can range from 105V to 130V. However,
care must be taken to ensure that the total load currents do
not exceed the maximum usable current (typically 21mA).
j;5OV
1232VT060V
V ,N
TRIMM EO
6 Va
QUTPU
V ,N
REF-OT
Va
CD
REF-OT
GND
TRIM
4
2
T'
30.00OY
6
5
~W
10kn
GNO
V,N
Va
4
6
REF~01
:
CD
2
V ,N
"
(TRIM FOR
CALIBRATION)
Va
6
20.•oov
tn
W
U
Z
W
II:
REF-OT
...
W
"
~cJ
6
RC = 10-SSEC
II:
'---
GND
4
c
II
TRIM 5
GND
2
V ,N
Va
~f--
t'
-5V
6
4
II:
.V
10.00
TRIM
4
h=!ff'
PAGE 9-9
CJ
~
~
Vo" 0
GND
W
o
REF-01
TO +25V
W
10kn
5
10kn
"s
6.Sku
>
REF-02
PMI
+5V PRECISION VOLTAGE
REFERENCE/TEMPERATURE
TRANSDUCER
FEATURES
• 5 Volt Output.. . .. ..•..•.. .. .. .. . ... ... ... :to.3%
• Temperature Voltage Output ............ ,. 2.1mV/'C
• Adluatment Range .......................... :t6%
• Excellant Temperature Stability ............ 3ppm/'C
• Low Nolle ...................•........... 10,NP1I
• Low Power. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 15mW
• Wlda Input Voltage Range . . . . . . . . . . . . . . .. 7V to 40V
• High Load Driving Capability •................ 20mA
• No Extemal Componenta
• Short Circuit Proof
• MIL·STD-883 Screening Available
ORDERING INFORMATIONt
GENERAL DESCRIPTION
The REF-02 Precision Voltage Reference provides a stable
+5V output which can be adjusted over a ±6% range with
minimal effect on temperature stability. Single supply
operation over an Input voltage range of 7V to 4OV, low current
drain of 1mA, and.excellent temperature stability are achieved
with an improved bandgap deSign. Low cost, low noise and
low power make the REF-02 an excellent choice whenever a
stable voltage reference Is required. Applications include
D/A and AID converters, portable instrumentation, and
digital voltmeters. The versatility of the REF·02 Is enhanced
by Its use as a monolithic temperature transducer. (See
AN·18 "Thermometer Applications of the REF-02.") For
+ 10V Precision Voltage References see the REF-01 and REF10 data sheets. Forguaranteed long term drift see the REF·05
data sheet.
PACKAGE
T A =2S'C
AVO MAX
(mV)
'·PIN
±15
±15
±25
±25
±50
+100
REF02AJ'
REF02EJ
REF02J'
REF02HJ
REF02CJ
REF02DJ
TO·.
HERMETIC
OIP
'·PIN
REF02AZ'
REF02EZ
REF02Z'
REF92HZ
REF02CZ
REF02DZ
PLAlnC
DIP
8-PIN
REF02HP
REF02CP
REF02DP
OPERATING
TEMPERATURE
RANOE
PIN CONNECTIONS
MIL
COM
MIL
COM
COM
COM
'.
N,C,07N.C.
N.C.
VIN 2
8 VOUT
TEMP 3
• Also available with MIL·STD-883 processing. To order add 1983 aa a suffix to
the part number.
t All listed parts are available with 160 hour burn·in. See Ordering Informallon.
Section 2.
5 TRIM
6·PIN HERMETIC DIP
(Z·Sufflx)
EPOXY B MINI·DIP
(P-Sufflx)
•
GROUND
CASE
TO·99 (J·Sufflx)
SIMPLIFIED SCHEMATIC
r---------~--~------~--------------r---~~~T
.,.
Q'I
OUTPUT
•
•3
R12" 7.11k
Re .... 1.
TRIM
•
A'
TEMP
0--+-------'
.z
Rn.a. 2k
_ _ _ _ _ _ _ _ _ _ _ _-4_ _ _ _+--_-<>:ROUND
PAGE 1·10
REF·02 +5V PRECISION VOLTAGE REFERENCEITEMPERATURE TRANSDUCER
ABSOLUTE MAXIMUM RATINGS (Note 2)
Input Voltage
REF·02, A, E, H • . • • • • • . • • • • • • • • • • • • • • • • • • • . • •• 40V
REF·02C, D • • • • • • • . • • • • • • • • • • • • • • . • • • . • • • . • •• 30V
Power Dissipation (Note 1) •••..••••......... 500mW
Output Short Circuit Duration
(to Ground or VIN) • • . • • • • • . • • • • • • • . • . . • .• Indefinite
Storage Temperature Range
J and Z Packages. .. .. • • • .. • .. .. • ... -65' C to + 150° C
P Package ......................... -65' C to + 125° C
Operating Temperature Range
REF·02A, REF·02 ••• . • . •• • ••• •••• -55°C to +125°C
REF·02E, REF·02H .................. O°C to + 70°C
REF·02C, REF-02D .................. O°Cto +70·C
Lead Temperature (Soldering, 60 sec) ••••.•.•••• 300·C
DICE Junction Temperature (T i ) ....... -65'C to +150'C
NOTES:
1. See table for maximum ambient temperature rating and derating factor.
8
MAXIMUM AMBIENT
TEMPERATURE
FOR RATING
DERATE ABOVE
MAXIMUM AMBIENT
TEMPERTURE
80·C
75·C
36'C
7.1 mWI· C
6.7mWI·C
5.6mWI·C
TO-99 (J)
Pin Hermetic Dip (Z)
8 Pin Plastic Dip (P)
2. Absolute ratings apply to both DICE and packaged parts. unless otherwise
noted.
ELECTRICAL CHARACTERISTICS at VIN = + 15V, TA = + 25' C, unless otherwise noted.
PARAMETER
SYMBOL
CONDITIONS
Output Voltage
Vo
IL=OmA
Output Adjustment Range
Rp=10k!l
Output Voltage Noise
~Vtrlm
8 np _p
Input Voltage Range
VIN
REF-02A1E
MIN
TYP
MAX
MIN
4.985
5.000
4.975
5.000
±3.0
±6.0
±3.0
±6.0
O.IHz to 10Hz (Note 1)
5.015
10
15
REF-02IH
MAX
TYP
10
40
7
UNITS
5.025
V
%
15
~Vp-p
40
V
Line Regulation (Note 2)
VIN =8 to 33V
0.006
0.010
0.006
0.010
%N
Load Regulation (Note 2)
IL=O to 10mA
0.005
0.010
0.006
0.010
%/mA
Turn..,n Settling Time
ton
To :!:O.1 % of final value
Quiescent Supply Current
ISY
No Load
Load Current
IL
Sink Current
Is
Short Circuit Current
Ise
Vo=O
Temperature Voltage Output
VT
(Note 3)
5.0
1.0
5.0
1.4
1.0
pS
1.4
mA
10
21
10
21
rnA
-0.3
-0.5
-0.3
-0.5
mA
30
30
mA
630
630
mV
II
~
UI
II:
en
UI
U
Z
UI
II:
UI
Yo
UI
II:
UI
CJ
ELECTRICAL CHARACTERISTICS at VIN=+15V,-55'C~TA~+125'Cfor REF-02Aand REF-02, O'C ~TA~+70'Cfor
REF-02E and REF-02H, IL = OmA, unless otherwise noted.
PARAMETER
SYMBOL
Output Voltage
Temperature Coefficient
Change In Vo Temperature
Coefficient with Output
Adjustment
CONDITIONS
O°C~TA~
Output Voltage Change with
Temperature (Notes 4 and 5)
REF-02A1E
MIN
TYP
MAX
REF-02IH
MIN
TYP
MAX
0.02
0.06
0.07
0.17
%
0.06
0.15
0.18
0.45
%
8.5
10
25
ppm/·C
+70°C
-55·C",TA'" +125·C
TCVo
(Note 6)
0.7
Rp=10k!l
UNITS
ppm/%
0.7
Line Regulation
(VIN = 8 to 33V) (Note 2)
O'C"TA ", + 70'C
0.007
0.012
0.007
0.012
%/V
-55'C"TA" +125'C
0.009
0.Q15
0.009
0.Q15
%N
Load Regulation
(IL = 0 to 8mA) (Note 2)
O°CsTA:S +70°C
0.006
0.010
0.007
0.012
%/mA
-55'C"TA" +125'C
0.007
0.012
0.009
0.Q15
Temperature Voltage Output
Temperature Co
'l
'l
Load Regulation
Output Voltage Noise
...
= OmA to 10mA
=OmAt08mA
0.006
%/mA
e neMe
0.1 Hz to 10Hz
20
25
25
tON
To ±O.I% of Final
Value
5.0
5.0
5.0
,.s
ISY
No Load
1.0
1.0
1.0
mA
,.Vp-p
Load Current
'l
21
21
21
mA
Sink Current
Is
-0.5
-0.5
-0.5
mA
Short Circuit Current
I_e
30
30
30
mA
Vo=O
NOTES:
1. See AN-IS for detailed REF-02 thermometer applications information.
2. Limit current in or out of pin 3 to SOnA and capacitance on pin 3 to 30pF.
PAGE 9-13
REF·02 +5V PRECISION VOLTAGE REFERENCEITEMPERATURE TRANSDUCER
OUTPUT ADJUSTMENT
The REF.Q2 trim terminal can be used to adjust the output
voltage over a 5V ±300mV range. This feature allows the system designer to trim system errors by setting the reference
to a voltage other than 5V. Of course, the output can also be
set to exactly 5.000V or to 5.12V for binary applications.
Adjustment of the output does not significantly affect the
temperature performance of the device. Typically the
temperature coefficient change Is O.7ppm/oC for 100mV of
output adjustment.
BURN·IN CIRCUIT
r:
r=
'6V
RT = 2kO
±10%.2W
2
V ,N
6
Vo
OUTPUT
VIN
REF-02
o----!-
TEMP
TRIM 5
REF-02
10Kn
GND
l'
GND
tsv
J-
TYPICAL PERFORMANCE CURVES
OUTPUT WIDEBAND NOISE
VB BANDWIDTH
(0.1 Hz TO FREQUENCY INDICATED)
10,000
OUTPUT CHANGE DUE TO
THERMAL SHOCK
LINE REGULATION
VB FREQUENCY
E
0.'"
0.0031
0.01
56
•
~
5
.
0.031
36
0.31
56
0.1
1.0
26
~
~
0.020
:0
Sla:
.
z
I
0.030
g 0,025
::;
3.1
..
S
~
o
25~C
10Hz
100Hz
1kHz
10kHz
FREQUENCY (Hz)
100kHz
1MHz
6LL~~~~~WL~~-W~. 10.0
1MHz
10Hz
100Hz
1kHz
10kKz 100kHz
FREQUENCY (Hz)
PAGE 9-14
=
75°C
2
:; 0,016
~
0.010
IE
~ 0,005
a:
10
T
VIN = 15V
TA· TA
it!
-10
7
/'
-
I
r/
~EVICE IMMERSED
IN 7SoC OIL BATH
102030406060
TIME (SECONDS)
REF·Q2 +5V PRECISION VOLTAGE REFERENCEITEMPERATURE TRANSDUCER
TYPICAL PERFORMANCE CURVES
..
NORMALIZED LOAD REGULATION
(.6.IL = 10mA) vs TEMPERATURE
MAXIMUM LOAD CURRENT
va INPUT VOLTAGE
...
1.'
SHORT CIRCUIT PROTECTION
1.3
30
/' 5OOmWML~
V
/
I
/
V
u
19 I.'
~ I.'
/
" tot
DISSIPATION
fB
~
!1.0
/
/
Eo..
1l!rr:
~
TA" 25"C
rr:
V
10
16
!5 1.0
1l!rr:
VIN= 11V
0.03
w 0.8
z
0.7
i!i
\
0.02
:>
1l!
0.01
::;
............
0.0
r-.... ......
•
10
I.
20
INPUT VOLTAGE (VOLTS)
.5
-
......
QUIESCENT CURRENT
vs TEMPERATURE
V
i
1.1
i3
1.0
/V
rr:
........
r'--I'
~
........ ........
5V
VO~I~----.--------------+-o~
1&1
.... -40_
v!
+2.6V
.,
6.8K
REF-02
REF·02
'Oka
TRIM 6
••
IOko
GND
15
a:
a:
0.1
±2.5V REFERENCE
+15V
6.aK
-5V
5kO
Vo
-2.IV
PAGE 9-15
a:
~
TYPICAL APLICATIONS
±5V REFERENCE
~
1&1
u
VI~= '~V
0.7
2D 40 10 80 100 120 140
TEMPERATURE I-CI
•
IS
V
.;' V"
~ 0..
~
a
30
20 40 eo 80 100 120 '40
TEMPERATURE I·CI
i ,·2
_-40_
o
0
1.3
VIN = 15V
" -
0.8
-10 -40 -20
0 20 40 10 80 100 120 140
TEMPERATURE lOCI
... r-....
\
3
;
-40 -20
MAXIMUM LOAD CURRENT
va TEMPERATURE
TA.Lc
V
~
::;
.;'
LINE REGULATION
va SUPPLY VOLTAGE
....;'
Eo.•
0.8
-eo
. . .V
~
V
0.8
••
20
INPUT VOLTAGE IVOL TS)
/
1.1
w
0.7
~
NORMALIZED
LINE REGULATION
va TEMPERATURE
o 20 40 80 80 100 120 140
TEMPERATURE ,-C)
1&1
CJ
~
;..!
g
REF·02 +5V PRECISION VOLTAGE REFERENCEITEMPERATURE TRANSDUCER
PRECISION TEMPERATURE TRANSDUCER WITH REMOTE SENSOR
RESISTOR VALUES
+15V
--l__-,
VIN VO.,·'----_ _+-_+_VR.:;Ep.-F---",R/V."v-.....__
TRIMI-"----+--i--I~
REF-02
Rs
1.Sk ±5%
TEMPr-W"v---t--t-+---t-"l
GNO
TCVOUT SLOPE (S)
TEMPERATURE
RANGE
10mV/'C
-5S'C to
+125°C
100mV/'C
-55°C to
+125'C
10mV/OF
-67°F to
+257'C
OUTPUT VOLTAGE
RANGE
ZERO SCALE
-0.55V to
+1.25V
OV@O'C
9.09k!l
1.5kO
2000
5.11kO
-5.5V to
+12.5V·
OV@O'C
15k!l
1.82kll
5000
84.5kll
-0.67V to
+2.57V
OV@O'F
7.5kll
1.21kll
20011
8.25k!l
Ra (±1%
resisto~)
Rb1 (± 1% resistor)
Rbp (Potentiometer)
'780
~
~
V
V
730
5w 680
g 580
~
~ 530
>48D
In general any number of REF·01's and REF·02's can be
stacked this way. For example, ten devices will yield ten out·
puts in 5 or 10V steps. The line voltage can range from 100
to 130V. However, care must be taken to ensure that the
total load currents do not exceed the maximum usable cur·
rent (typically 21mA)_
/
~B30
c;
V
V
• For 125'C operation, the op amp output must be able to swing to +12.5V,
increase VIN to +18V from +15V if this is a problem.
1/
1/
43D
-GO -40 -20
0
20
40
60
80
100 120 140
TEMPERATURE (OC)
_I?27V TO 55V
VIN
Vo
TEMPERATURE CONTROLLER
25. OOOV
6
REF-Ot
v+ (12 TO 32V)
,-----+---------~
---,
TRIM
S
~27k,Q
4
r-----------,
I
10kn
GNO
.~ R7
2
V,N
R1
VIN
1
I HEATING
I ELEMENT
I
I
6
I
(9.2knl
vol-"-IC--v."v----
V O =OT035V
D/A CONVERTER REFERENCE
RC = lcrSsEC
+15V
MSB
LS8
CURRENT SOURCE
+15V
-'sv
-16V
REF-02
TRIM
R
pas FULL SCALE
lOUT '" 5.~V +lmA
GND
-1 LSB B1
B2 B3 B4 B5 B6 B7 B8
ZERO SCALE
NEG FULL SCALE + 1 LSB
NEG FULL SCALE
'OUT
VOLTAGE COMPLIANCE: -25V TO +8V
PAGE 9·17
E
+4.960
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-4.960
0.000
0
0
0
0
0
0
0
0 -5.000
REF·02 +5V PRECISION VOLTAGE REFERENCE/TEMPERATURE TRANSDUCER
±3V REFERENCE
PRECISION CALIBRATION STANDARD
+7.5V
1"----<~-oVOI-1
" -S.DV
PAGE 1-18
I.
V,N
Vo
•
+
REF~2
o------.!.
TRIM
•
,OOK
••OOOV
OND
r
-
REF-05
PMI
+5V PRECISION VOLTAGE REFERENCE
WITH GUARANTEED LONG-TERM STABILITY
FEATURES
GENERAL DESCRIPTION
•
•
The REF-05 Precision Voltage Reference provides a stable
+5V output which can be adjusted over a ±6% range with
minimal effect on temperature stability. Single supply operation over an input voltage range of 7V to 40V, low current
drain of 1 mA, and excellent temperature stability are achieved
with an improved bandgap deSign. Low cost, low noise, and
low power make the REF-05 an excellent choice whenever a
stable voltage reference is required. Applications include
D/A and AID converters, portable instrumentation, and digital voltmeters. The versatility of the REF-05 is enhanced by
its use as a monolithic temperature transduce(. (See AN-18
"Thermometer Applications of the REF-02.") For + 10V Precision Voltage References see the REF-10 data sheet.
•
•
•
•
•
•
•
5 Volt Output
Guaranteed Long-Term Stability
. . . . . . . . . .. 100ppm/1000 Hrs Max
Excellent Temperature Stability . . . . . . . . . . .. 3ppml" C
Low Noise ............................. 10l'V pop
Low Power Drain . . . . . . . . . . . . . . . . . . . . . . . . . .. 15mW
Wide Input Voltage Range .............. 7V to 40V
High Load Driving Capability . . . . . . . . . . . . . . . .. 20mA
Short Circuit Proof
Processed Per MIL-STD-883
LONG TERM DRIFT PLOT (Average of 20 Devices)
PIN CONNECTIONS
•
1\
. . . r--. I---
-8.
VIN 2
.
II:
TO-99 (J-Sulfix)
REF05AJ
REF05BJ
6 VOUT
TEMP 3
.,...
IU
N,CO·7N.C.
'f.J1'-
80
100
120
140
160
:aU
Z
W
II:
...
5 TRIM
IU
4
GROUND
CASE
110
•
...9
N.C.
W
II:
180
IU
CI
DAYS ELAPSED
~
;",I
~
SIMPLIFIED SCHEMATIC
,------------.--~---___"4r_-------.,....---< ~PUT
R,.
Q1.
OUTPUT
•
•3
R12"" 7,11K
R9'" 18k
.,
3
TEMP <>-+-----'
Rll'" 2k
.2
~
_________
TRIM
6
~
____________
PAGE 9-19
~
____
+-_~~ROUND
REF-OS +5V PRECISION VOLTAGE REFERENCE/TEMPERATURE TRANSDUCER
ABSOLUTE MAXIMUM RATINGS
Input Voltage
REF-Q5A, B .............................•........ 40V
Power Dissipation (see note) •••••••••••••••••••• 500mW
Output Short Circuit Duration
(to Ground or VIN) •••••••••••••••••••••••••• Indefinite
ELECTRICAL CHARACTERISTICS
Storage Temperature Range. • • • • • • • • •• -65· C to + 150· C
Lead Temperature (Soldering, 60 sec) ••••••••••••• 300·C
Operating Temperature Range
REF-05A, REF-058 ••••••••••••••••• -55·C to +125·C
NOTE: Derate at 7.1 mW/Q C above 80°C ambient temperature for TO-99 (J)
package.
at VIN = +15V, TA =2S'C unless otherwise noted.
REF-GSA
PARAMETER
SYMBOL
CONDITIONS
Output Voltage
Vo
Output Adjustment Range
4Vtr1m
e np _p
Output Voltage Noise
Long Term Stability
Input Voltage Range
TYP
MAX
MIN
TYP
MAX
IL=OmA
4.985
5.000
5.015
4.975
5.000
5.025
Rp=10kll
±3.0
±6.0
±3.0
±6.0
Load Reglliation (Note 2)
UNITS
V
%
0.1Hz to 10Hz (Note 1)
10
15
10
(Note 1)
65
100
65
40
V
VIN =8 to 33V
0.006
0.010
0.006
0.010
%IV
IL=O to 10mA
0.005
0.010
0.006
0.010
%JmA
1.4
mA
VIN
Line Regulation (Note 2)
REF-OS8
MIN
40
Turn·on Settling Time
ton
To ±0.1% of final value
5.0
Quiescent Supply Current
ISY
No Load
1.0
15
pVp.p
100 ppm/1kHrs
5.0
1.4
1.0
ps
Load Current
IL
10
21
10
21
mA
Sink Current
Is
-0.3
-0.5
-0.3
-0.5
mA
Short Circuit Current
Ise
Vo=O
30
30
mA
Temperature Voltage Output
VT
(Note 3)
630
630
mV
ELECTRICAL CHARACTERISTICS
at VIN = +15V, -55'CsTA s +125'C and IL =OmA unless otherwise noted.
REF-OSA
PARAMETER
SYMBOL
CONDITIONS
Output Voltage Change with
Temperature (Notes 4 and 5)
t>.VOT
Output Voltage
Temperature Coefficient
REF-OS8
TYP
MAX
TYP
MAX
UNITS
O"CsTA " + 70'C
0.02
0.06
0.07
0.17
%
t>.VOT
-55"C"TA" +125"C
0.06
0.15
0.18
0.45
%
TCVo
(Note 6)
3
8.5
10
25
ppm/"C
Change in Vo Temperature
Coefllcient with Output
Adjustment
MIN
Rp= 10kll
MIN
0.7
0.7
ppm/%
%N
Line Regulation
(VIN = 8 to 33V) (Note 2)
O"C"TA " + 70"C
0.007
0.012
0.007
0.012
-55"C"TA" +125'C
0.009
0.015
0.009
0.015
%IV
Load Regulation
(IL = 0 to 8mA) (Note 2)
O"C"TAs +70"C
0.006
0.010
0.007
0.012
%/mA
-55"CsTA " +125"C
0.007
0.012
0.009
0.D15
Temperature Voltage Output
Temperature Coefficient
TCVT
(Note 3)
2.1
NOTES:
1. Sample tested.
2. Line and load Regulation specifications Include the effect of self
heating.
3. Limit current in or out of pin 3 to SOnA and capacitance on pin 3 to 3OpF.
4. t>.VOT is defined as the absolute difference between the maximum output voltage and the minimum output voltage over the specified
temperature range expressed as a percentage of 5V.
t>.V OT-
2.1
VMAX -VMIN
5V
%/mA
mV/"C
x 100
5. t>.VOT specification applied trimmed to +5.000V or untrimmed.
6. TCVo Is defined as t>.VOT divided by the temperature range, i.e.,
PAGE 9-20
TCVo=
t>.VOT
180'C
REF-OS +SV PRECISION VOLTAGE REFERENCE/TEMPERATURE TRANSDUCER
OUTPUT ADJUSTMENT
The REF-05 trim terminal can be used to adjust the output
voltage over a 5V ±300mV range. This feature allows the
system designer to trim system errors by setting the reference to a voltage other than 5V. Of course, the output can
also be set to exactly 5.000Vorto 5.12V for binary applications.
Adjustment of the output does not significantly affect the
temperature performance of the device. Typically the
temperature coefficient change is O.7ppm/oC for 100mV of
output adjustment.
BURN·IN CIRCUIT
t+'5V
fnY
t
Rl·2kn
o",2W
V,N
Vo
6
OUTPUT
V,N
REF-OS
o----!
TEMP
TRIM
5
REF-05
10K!!
GND
-
GND
1"
tav
.,1
~
W
II:
TYPICAL PERFORMANCE CURVES
en
W
CJ
OUTPUT WIDEBAND NOISE
vs BANDWIDTH
(0.1 Hz TO FREQUENCY INDICATED)
..
'D.OOD~_
_
~
5
..
&136
'00 _ _
10Hz
100Hz
1kHz
10kHz
FREQUENCY
100kHz
'MHz
z28
::;
,.
"""
• IIIII~~
10Hz
III
100Hz
O·03'l
D.' 2z
0.3'
;;; 0.015
5::>
.
lli
3., ~
1kHz
10kHz
FREQUENCY
PAGE 9-21
100kHz
10.0
'MHz
W
II:
~ 0.030
g 0.025
,."
Vs = 15V
TA .. +2S'C
I&.
w
0.01
z
246
W
II:
W
~ 0,036
0.0031
~56
'000 _
OUTPUT CHANGE DUE TO
THERMAL SHOCK
LINE REGULATION
vs FREQUENCY
76
Z
~
W
VINI. , . )
TA =
TA·
2S'C
75~C
~ 0.020
o
z
~
0.010
!;;
..
~ 0.005
~
o
-'0
/
II
V
c:J
-
~
;.J
o
>
V IN 15'C Oil BATH
DEVICE IMMERSED
10
20
30
TIME (SECONDSI
40
60
60
REF-OS +SV PRECISION VOLTAGE REFERENCE/TEMPERATURE TRANSDUCER
TYPICAL PERFORMANCE CURVES
MAXIMUM LOAD CURRENT
vs INPUT VOLTAGE
NORMALIZED
LINE REGULATION
vs TEMPERATURE
NORMALIZED LOAD REGULATION
(AIL = 10mA) vs TEMPERATURE
t.4
35
SHORT CIRCUIT PROTECTION
t. 3
/' 5OOmwLI~
V
u
lq
~
!
/
1.0
to
t5
~ 0.8
25
20
0.02
0.01
LINE REGULATION
vs SUPPLY VOLTAGE
i
TA.L
\
... 25
~
\
I'-.
0.0
to
t.
20
25
-
t.
~
!
10
1.0
./
m
VIN'" 16V
V'
~
.. 0.8
0..
-60 ~ -20
0
20 40 60 80 100 120 140
TEMPERATURE (OCI
........
t.3
i
'I'-.
",
V
t.2
,.. ~ ,..
~ t.t
~
u 1.0
1'- .....
VIN '" 16V
~
V .....
",,"""
~
M0.8
i
0 20 40 60 80 100 1m 140
TEMPERATURE ,OC)
QUIESCENT CURRENT
vs TEMPERATURE
0..
VIN = 16V
--eo-tO -20
30
0
20
40
80
80 100 120 140
0.7
-80.....a -20
TEMPERATURE c·el
0 20 40 eo 80 100 120 140
TEMPERATURE C-CI
TYPICAL APLICATIONS
±2.SV REFERENCE
± SV REFERENCE
+15v
5V
V IN
-r.
+2.6V
+5V
6
.t
UK
REF-05
REF-05
tOkn
TRIM 5
R2
tOkn
GND
V
~
-
INPUT VOLTAGE (VOLTS)
Vo
V
0.7
!i2O
u
~
./
~
~
""- ...........
!
MAXIMUM LOAD CURRENT
vs TEMPERATURE
30
\
1,1
E 0.9
""
0.6
-60 -40 -20
30
INPUT VOLTAGE (VOL TSI
fB
v
'180
5000
84.Skll
• For 12S"C operation, the op amp output must be able to swing to + 12.SV,
increase VIN to +18V from +15V If this is a problem.
APPLICATION NOTE 18, "THERMOMETER APPLICATIONS OF THE REF-02",
83D
2000
S.11kll
/
0
20
40
60
V,N
Vo
•
25. OOOV
REF-10
V+ (12 TO 32V1
TRIM
GND
y-----t---------..---,
..... R7
6
~27kn
2
GNO
I
L ___
.J~~T!...'I
.6
4
V ,N
I .1
(1.2kn)
Vo
•
15.0OOV
.1
vot=-;I~W.r_+"I
REF-OS
10kn
4
r-----------,
ELEMENT
REF-10
I 1.~n
t"-1..."""'I'v---H
.2
I
1.6kl1
___
13u
zW
II:
...
W
W
II:
W
CI
>
1227V TO 66V
TEMPERATURE CONTROLLER
HEATING
w
II:
o
80 100 120 140
TEMPERATURE lOci
V,N
!
~
;..I
43D
-60 -40 -20
•
3
TRIM 5
GNO
2
V ,N
Vo
.J
2.2kn
•
4
10kn
5.D OOV
REF-05
.4
TRIM
GNO
2.7kn
4
NOTES:
1.
SHOULD BE'THERMALLY CONNECTED
TO SUBSTANCE BEING HEATED.
2. NUMBERS IN PARENTHESES ARE FOR A
SETPOINT TEMPERATURE OF acre.
3. R3- R111R2uR8
PAGE 9-23
"
10kn
R.
6.ak!!
REF-05 +5V PRECISION VOLTAGE REFERENCE/TEMPERATURE TRANSDUCER
PRECISION CURRENT SOURCE
A current source with 35V output compliance and excellent
output impedance can be obtained using this circuit. REF-05
2 keeps the line voltage and power dissipation constant in
device 1 ; the only important error consideration at room
temperature is the negative supply rejection of the op amp.
The typical 3/lV/V PSRR of the OP-02E will create a 20ppm
change (3/lV/v x 35V/5V) in output current over a 35v range.
For example, a 5mA current source can be built (R = 1kO)
with 350MO output impedance.
CURRENT SINK
lOUT
2
REF-06
TRIM
R
lOUT" 5,:V +1mA
GNO
35V
Ro=
20
X
-15V
10-6 x 5mA
VOLTAGE COMPLIANCE: -8V TO 25V
+5OV
BATTERY-OPERATED D/A CONVERTER REFERENCE
V,N
, - - - - . . . . . . , . Vo
REF-06
MOO
LSB
S.OOku
S.OOkn
GNO
E02
VO~--------~--------~---'
REF-05
(TRIM FOR
CALIBRATION)
GNO
D/A CONVERTER REFERENCE
..Okn
+16V
MOO
LOO
B.Okn
CURRENT SOURCE
_ 1~+15V
V ,N
Vo ~
+16V
-1SV
-15V
REF~
3
TRIM
~
R
POS FULL SCALE -1 LSB B1 B2 B3 B4 B5 B8 B7 B8
lOUT '" 5,:' +1mA
ZERO SCALE
GND
1"
~
lOUT
VOLTAGE COMPLIANCE: -25V TO +IV
PAGE 9-24
1
1
E
+4.960
NEG FULL SCALE +1 LSB
1
0
0
0
0
0
0
0
NEG FULL SCALE
0
0
0
0
0
0
0
1 -4.960
0
0
0
0
0
0
0
0 -5.000
0.000
REF-OS +SV PRECISION VOLTAGE REFERENCE/TEMPERATURE TRANSDUCER
±3V REFERENCE
PRECISION CALIBRATION STANDARD
+7.6V 1±10%1
2
+l.SV
V,N
VOUTr-1-----+-----o
REF...Q5
.,
VOI+) = +3.OV
--'1.1mA
211kO
GNO
r
.2
13.3kn
-=-9V
Vor------.----O
REF-06
TRIMI"--------.,~,IIOK
5.000v
GNO
>----1r--OVOH = -aov
II
~
III
II:
II)
III
(J
Z
III
II:
III
Ii.
III
II:
III
CJ
:!
;..(
o
>
PAGE9-2S
REF-10
PMI
+lOV PRECISION VOLTAGE REFERENCE
WITH GUARANTEED LONG TERM STABILITY
FEATURES
GENERAL DESCRIPTION
• 10 Volt Output
• Guaranteed Long-Term Stability
• • . . • .. • . .. .. 50ppm/1000 Hrs Max
• Excellent Temperature Stability •.••..•.•••.. 3ppml° C
• Low Noise ......•.•....••...•....••..••.... 20"V pop
• Low Power Drain ............................. 15mW
• Wide Input Voltage Range ................. 12V to 40V
• High Load Driving Capability ...••...••...••.••. 20mA
• Short Circuit Proof
• Processed Per MIL-STD-883
The REF-10 Precision Voltage Reference provides a stable
+10V output which can be adjusted over a ±3% range with
minimal effect on temperature stability. Single supply operation over an input voltage range of 12V to 40V, low current
drain of 1 mA, and excellent temperature stability are achieved
with an improved bandgap design. Low cost, low noise, and
low power make the REF-10 an excellent choice whenever a
stable voltage reference is required. Applications include
DI A and AID converters, portable instrumentation, and digital voltmeters. For +5V Precision Voltage References see the
REF-05 data sheet
LONG TERM DRIFT PLOT (Average of 20 Devices)
PIN CONNECTIONS
0
N.C•
..
t ...
~
t
o
'-
~ l- I--
"
•
-
N'C'07N'C'
t-
VIN 2
8 Your
0
N.C. 3
·'20
20
40
60
TO-99 (J-Sufflx)
REF10AJ
REF10BJ
5 TRIM
4
GROUND
80 100 120
CAYS ELAPSED
ICASEI
SIMPLIFIED SCHEMATIC
,------_-_----.---------.-----<>IN.UT
2
R,.
018
OUTPUT
•
R3
R12"" 14.2k
R9"" 50k
R'
Rl1 :::. 2k
R2
4
L---------+------------~---~~-_oORO~D
PAGEI-2S
REF-1D +lDV PRECISION VOLTAGE REFERENCE
ABSOLUTE MAXIMUM RATINGS
Input Voltage
REF-1OA, B
Storage Temperature Range. • • • • • • • • ••
-65 0 C to
•••••••••••••••••••••••••••.•••••••••
40V
Output Short Circuit Duration
(to Ground or V IN ) •••••••••••••.•••••••••••• Indefinite
ELECTRICAL CHARACTERISTICS
REF-1OA, REF-1OB ••••••••••••••••••
NOTE: Derate at 7.1mW/oC above
package.
-55 0 C to
CONDITIONS
REF-10A
MIN TYP MAX
REF-10B
MIN TYP MAX
Output Voltage
Vo
IL=OmA
9.97 10.00 10.03
9.95 10.00 10.05
Output Adiustment Range
t1V trim
Rp= 10kll
±3.0
Bnp _p
O.IHz to 10Hz
(NoteS)
Long Term Stability
±3.0
±3.3
20
C
(J)
20
30
40
UNITS
V
±3.3
50
(NoteS)
Input Voltage Range
0
at VIN = +15V, TA =25'C, unless otherwise noted.
SYMBOL
Noise
+125
sooe ambient temperature for TO-99
PARAMETER
V~ltage
C
Operating Temperature Range
Power Dissipation (see note) •••••••.•••.•.•••••• 500mW
Output
+ 1500
Lead Temperature (Soldering, 60 sec) ••••••••••••. 300 0 C
%
30
pVp·p
50 ppm/l000 Hrs
40
V
VIN = 13 to 33V
0.006 0.010
0.006 0.010
%IV
Load Regulation
(Note 4)
IL=O to 10mA
0.005 0.008
0.006 0.010
%/mA
Turn·on Settling Time
to.n
To .:!:O.1% of final value
5.0
Quiescent Supply Current
ISY
No Load
1.0
Load Current
IL
10
21
10
21
mA
Sink Current
Is
-0.3
-0.5
-0.3
-0.5
mA
Short Circuit Current
Ise
30
mA
12
VIN
Line Regulation
(Note 4)
12
1.4
1.0
30
VO=O
I'sec.
5.0
mA
1.4
III
co
~
w
a:
til
W
(J
ELECTRICAL CHARACTERISTICS
Z
w
a:
w
at VIN = +15V, -55'CsTA s +125'C and IL=OmA, unless otherwise noted.
PARAMETER
SYMBOL
CONDITIONS
Output Voltage Change
with Temperature
(Notes 1 and 2)
AVOT
OOsTAs +70°C
-SS'sTAs +12S'C
Output Voltage
Temperature Coefficient
TCVo
REF-10A
MIN TYP MAX
REF-10B
MIN TYP MAX
0.02
0.06
0.07
0.18
0.06
0.15
UNITS
0.17
0.45
%
...w
a:
w
CJ
ooC
~
o
(Note 3)
3.0
Change in Vo Temperature
Coefficient with Output
Adiustment
Rp= 10k!l
0.7
Line Regulation
(VIN = 13 to 33V)
(Note 4)
O'sTAs +70'C
-55°sTAs +125°C
Load Regulation
(IL =0 to 8mA)
(Note 4)
O'sTAs +70'C
-SS'sTAs +12S'C
8.5
0.007 0.012
0.009 O.Q1S
10.0
25.0
ppm/'C
0.7
ppm/%
0.007 0.012
0.009 0.015
%IV
.. _ - - - -
NOTES:
1. AVOT is defined as the absolute difference between the maximum out·
put voltage and the minimum output voltage over the specified
temperature range expressed as a percentage of 10V:
AVOT -
VMAX-VMIN
10V
X 100
2. AVOT specification applies trimmed to +10.000V or untrimmed.
0.006 0.010
0.007 0.012
0.007 0.012
0.009 O.Q1S
%/mA
3. TCVo Is defined as AVOT divided by the temperature range; i.e.,
AVOT (-55 to +125'C)
TCVo (-55'to +125'C)=
180'C
4. Line and Load Regulation specifications Include the effects of self
heating.
5. Sample tested.
PAGE 9-27
>
REF·1Q +10V PRECISION VOLTAGE REFERENCE
OUTPUT ADJUSTMENT
Adjustment of the output does not significantly affect the
temperature performance of the device. Typically the
temperature coefficient change is 0.7ppm/'C for IOOmV of
output adjustment.
The REF-IO trim terminal can be used to adjust the output
voltage over a 10V ±300mV range. This feature allows the
system designer to trim system errors by setting the reference to a voltage other than lOY. Of course, the output can
also be set to exactly 10.000V or to 10.240V for binary
applications.
BURN·IN CIRCUIT
r
1:'5V
V'N
Vo
6
Rl2V= 2M2
110%,2W
2
OUTPUT
V'N
REF-10
TRIM
5
REF-l0
10Kll
GND
14
GND
1
r-'8V
TYPICAL PERFORMANCE CURVES
OUTPUT WIDEBAND
NOISE vs BANDWIDTH (0.1 Hz
TO FREQUENCY INDICATED)
LINE REGULATION
vs FREQUENCY
76
0.0031
66
0.01
OUTPUT CHANGE DUE
TO THERMAL SHOCK
0.035
10,000
0.030
. -t-, "
56
0,Q31
0.1
1.0
46
36
Vs " 15V
TA = +2S'C
16
''''''
10
I"
I
!"
lkL
10k
FREOUENCY (Hz)
lOOk
10.0
1M
V'N
0.025
TA"
25°C
I•
ISv'
TA"
75"C
0.020
vr
I
--l-t
~
;:
0.010
0.005
10
100
lk
10k
FREQUENCY (Hz)
PAGE 9-28
tOOk
1/
0.015
3.1
I1111111111
100
I
I 'I
0.31
26
6
1000_,,_
il
,H1tH±7H"Pfft!I
1M
-10
/
II
V
-
DEVICE IMMERSED
IN 75'C OIL BATH
10
20
30
TIME (SECONDS)
40
50
80
REF-10 +10V PRECISION VOLTAGE REFERENCE
TYPICAL PERFORMANCE CURVES
3.
NORMALIZED LOAD
REGULATION (all 10mA)
VI TEMPERATURE
=
MAXIMUM LOAD CURRENT
VI INPUT VOLTAGE
NORMALIZED LINE REGULATION
VI TEMPERATURE
1.4
1.4
1.3
1.3
SHOAT CIRCUIT PROTECTION
3.
~
~ 25
/' 500mwL~
/
"~
9
15
;!!i
"X 1.
~
/
I
'/'
" 1.1
DISSIPATION
~ 20
~
~
/
/
1.0
...
...
V
~ 0.8
1.
..
zo
30
-&0
to
illII:
-
...
.-41)
-20
"~
9
I'-...
........
V ......
1.1
r-.-
...
//
1••
1'-,
VIN" 15V
20
40
60
80 100 120 140
TEMPERATURE (OCI
1.2
........
0
II
QUIESCENT CURRENT
VI TEMPERATURE
r-.....
15
"~ ,.
-60 -40 -20
0 20 40 60 80 100 120 140
TEMPERATURE f"CI
1.3
~ZO
V
•.7
MAXIMUM LOAD CURRENT
VI TEMPERATURE
1 2.
./
"8
;'
INPUT VOLTAGE (VOL TSI
30
_f-'"
VIN = 15V
0.7
•1.
/V
1.•
/
II:
9
,/
1.1
E
&3 0.9
TA = 25°C
v
,/
u
l§ 1.2
i
v
o
:L1&1
II:
fa
ifi
II:
V
u
;'
1&1
II.
1&1
••8
II:
VI~ .'~V
--80-40 -20
•. 7
-60 -40 -20
0 20 40 80 80 100 120 140
TEMPERATURE I·CI
0
20
40
eo
1&1
ClI
~
;.J
80 100 120 140
TEMPERATURE ("C)
o
>
TYPICAL APPLICATIONS
D/A CONVERTER REFERENCE
tOkO
+15V
MSB
LSB
Bl B2 B3 B4 B5 B6 B7 B8
pos FU Ll SCALE
-1 lSB
1
ZERO SCALE
+15V
-15V
0
0
0
0
0
0
0.000
NEG FULL SCALE +1 lSB
0
0
0
0
0
0
1
-4.960
NEG FULL SCALE
0
0
0
0
0
0
0
-5.000
-15V
PAGE9-zg
0
E
+4.960
REF-10 +10V PRECISION VOLTAGE REFERENCE
TYPICAL APPLICATIONS
AID CONVERTER REFERENCE
PRECISION CALIBRATION STANDARD
+15V
ANALOG
INPUT
o TO +1OV
---"1mA
1
12
{
-
1-
V ,N
Vo
9V
+15V
,
•
REF·10
TRIM
GNO
9V
10.000v
5
lOOK
r
1
-15V
-
SERIAL
OUTPUT
CURRENT SOURCE
!2+
VOLTAGE COMPLIANCE:
15V
V ,N
Va
CONNECT "START" TO
"CONVERSION COMPLETE"
FOR CONTINUOUS CONVERSIONS.
START
CONVERSION TTL CLOCK
COMPLETE
INPUT 2,26MHz
-25V TO +3V
r!---
REF·1O
TRIM
~
lOUT" '0:' +lmA
R
±10V REFERENCE
GNO
l'
+15V
+
lOUT
"ov
REF·l0
10kO
CURRENT SINK
10ka
GNO
1~OUT
V ,N
Vo
VOLTAGE COMPLIANCE: -3V TO +25V
+15V
r!---lOV
REF-1O
TRIM
~
SkU
R
lOUT '" '0:' +lmA
GNO
l'
6
-15V
-15V
PAGE 9-30
REF·10 +10V PRECISION VOLTAGE REFERENCE
PRECISION CURRENT SOURCE
REFERENCE STACK WITH EXCELLENT LINE REGULATION
A currenl source with 25V output compliance and excellent
output Impedance can be obtained using this circuit. AEF-10
®keeps the line voltage and power dissipation constant In
device CD; the only Important error conSideration at room
temperature is the negative supply rejection of the op amp.
The typical 3p.V/V PSAA of the OP-02E will create an 8ppm
change (3p.V/V x 25V/10V) In output current over a 25V
range. For Example, a 10mA current source can be built (A =
1kO) with 300MO output Impedance.
A 25V
0 - 8x10- 6x10mA
Three AEF-10's can be stacked to yield 10.000, 20.000 and
30.000V outputs. An additional advantage Is near-perfect line
regulation of the 10.000 and 20.000 output voltages. A 32V to
60V input change produces an output change which is less
than the noise voltage of the devices. A load bypass resistor
(As) provides a path for the supply current (Isy) of the
20.000V regulator.
In general, any number of AEF-10's can be stacked this way.
For example, ten devices will yield outputs of 10, 20, 30 ...
100V. The line voltage can range from 105V to 130V. However,
care must be taken to ensure that the total load currents do
not exceed the maximum usable current (typically 21mA).
+&OV
1232VTO 60V
TRIMM ED
OUTPUTS
REF·1D
V,N
®
REF·l0
VD
aND
TRIM
GND
V,N
REF·10
...
•
•
DOOV
1Dk!!
•
vo~·~------~,--------~---;
2
V ,N
"
(TRIM FOR
CALIBRATION)
Va
•
20.•oov
REF·1D
GNO
TRIM 5
GND
2
V,N
Va
•
•
10kU
10,0DOV
REF·1D
Vo" 0
TO +26V
TRIM
OND
•
IO"W'
PAGE 9-31
5
',",11
".
s.SkU
II
D/A
CONVERTERS
D/A CONVERTERS
INDEX
PAGE
PRODUCT
TITLE
DAC-01
DAC-02
DAC-oS
DAC-04
DAC-05
DAC-06
DAC-08
DAC-10
DAC-20
DAC-76
DAC-78
DAC-100
DAC-101
DAC-206
DAC-208
DAC-210
DAC-312
DAC-808
DAC-888
DAC-1508A11408A
JM38510/11301111302
8-Blt Voltage Output D/A Converter .......................................................... 10-12
10-Blt Plus Sign Voltage Output D/A Converter .•..............•.•.•••••••.•......•....•••• 10-16
10-Bit Plus Sign Voltage Output D/A Converter (See DAC-02) ••....••.•....•.....•.••.••••• 10-16
Two's Complement 10-Blt 01 A Converter ...•.•.•..•...•.•.•...•••.•..••...•...•..•...•.••• 10-21
10-Bit Plus Sign Voltage Output D/A Converter (See DAC-02) .•..•••.••....•......•••.••.•• 10-16
Two's Complement 10-Blt D/A Converter (See DAC-04) ...•......•.•..•....•......•...•..•. 10-21
8-Bit High-Speed Multiplying D/A Converter .•.•..•........•....•.•..•....•.....••.•....•• 10-26
10-Blt High-Speed Multiplying D/A Converter ...........•...•..••...•.•.•.•.••..•.•..•.•.. 10-36
2-Dlglt BCD High-Speed Multiplying D/A Converter .....•.......•.....••..•............•.. 10-44
COMDAce Companding D/A Converter ................................................. , 10-52
COMDAce Companding D/A Converter ........... , ............................... , ...... 10-69
10-Bit 01A Converter .... , ...........•...•.......•...•..•.•....•....•.•...•.•............. 10-79
10-Bit 01A Converter .........•.............•....•......•.•....•....•..................... 10-79
6-Bit Voltage Output D/A Converter ....................................................... 10-87
9-Bit Digital-to-Analog Converter (8 Bits Plus Sign) ........•............ , ....••............ 10-91
11-Bit Dlgltal-to-Analog Converter (10 Bits Plus Sign) ..................•.....•............. 10-94
12-Bit High-Speed Multiplying D/A Converter ...••........................................ 10-99
8-Bit High-Speed "Microprocessor Compatible" Multiplying D/A Converter ....•............ 10-111
8-Bit High-Speed "Microprocessor Compatible" Multiplying D/A Converter ..........•...... 10-122
8-Bit Multiplying D/A Converter •......................•................................ , 10-134
JAN 8-Bit Dlgital-to-Analog Converter ........................•.......•.....•............ 10-140
INTRODUCTION
A D/A converter accepts a digital input and produces an
analog output. The basic DAC consists ofa voltage or current reference, binary weighted precision resistors, a set of
electronic switches and a means of summing the weighted
currents.
Three Important criteria for selecting a good DAC are accuracy, speed and resolution. Other essential requirements
to be considered are temperature stability, Input coding, out·
put format, reference requirements and power consumption.
4. The bipolar transistor switches provided on PMI DACs
have faster settling times than their FET counterparts.
DACs can be categorized by the type of analog output - a
current or a voltage. "Complete" DACs have an on-board
reference source, R-2R ladder network and current-to-voltage
converting op amp on one monolithic IC. "Multiplying" DACs
have access to the reference Input pin allowing the user to
multiply an analog quantity by a digital number.
2. Reference servoed NPN current source transistors give
high compliance, temperature stable outputs.
Since Introducing the first monolithic D/A converter in 1970,
PMI has continually Improved and updated its DAC series.
PMI offers an extensive choice of DAC resolutions, coding
formats, output configurations and temperature ranges. All
of these products are characterized by high speed and
temperature stable performance. Wide dynamic range and
good zero resolution are offered by PMI's "companding"
(compressing/expanding) D/A converter, the COMDA~ , in
applications where a hlgh·resolution linear DAC Is not needed.
3. Stable low-offset op amps are also difficult to fabricate
with CMOS devices.
The selection guides following the definition pages will aid
you in quickly locating the appropriate DAC.
PMI DACs use bipolar transistor technology. Some of the
advantages these DACs offer over CMOS-FET types are:
1. Bipolar technology allows a stable Internal zener
reference to be fabricated monolithically. Adequate
references are not available in CMOS devices.
PAGE 10-2
DISCUSSION OF ERRORS
COMPANDING DAC DEFINITIONS
CHORDS
Groups of linearly-related steps in the transfer function.
Also known as segments.
CHORD ENDPOINTS
The maximum code in each chord. Used to specify accuracy.
DYNAMIC RANGE
Ratio of the largest output (1 715) to the smallest output excluding zero (Io,o)expressed In dB. This can be measured
peak or peak-to-peak with the same result.
ENCODE CURRENT
The difference between 10E( +) and loot +) or the difference
between 10E( - ) and loot - ) at any code.
FULL SCALE SYMMETRY ERROR
The difference between 100 (-) and I (+) or the difference
between 10E (+) and 10E (-) at full-scale output.
Transfer accuracy in a D/A Converter is generally determined by measuring deviation of the actual analog output
from the ideal expected output. In general, the adjustable
analog output errors of a D/A Converter are full-scale or gain
error and offset or zero-scale error. Nonadjustable D/A Converter errors include nonlinearity, differential nonlinearity,
zero-scale symmetry, zero and full-scale temperature drift
coefficients and power-supply sensitivity. The most meaningful nonadjustable error term in a D/A Converter is
NONLINEARITY. The next most important nonadjustable
error terms are full-scale drift and differential-nonlinearity. A
D/A Converter that has a specified maximum nonlinearity of
± 1/2 LSB over temperature will also be guaranteed to be
monotonic. PMI specifies maximum nonlinearity over
tem peratu re for every Df A converter (except the DAC-03 and
DAC-1 01) to assure the designer of precision performance
for the most demanding applications,
BIPOLAR D/A CONVERTERS
ANALci: r- - ~~.
OUTPUT LEVEL NOTATION
Each output current level may be designated by the code
Ic s where C = chord number and S = step number. For example, 100 = zero scale current; 101 = first step from zero;
10 ,15 = endpoint of first chord (Co); 17,15 = full scale current.
.
/
ANALOG
OUTPUT
STEPS
Increments in each chord which divide it into 16 equal
levels.
/.
.
/ •• /
/
•• /
/
GAIN ERROR
/
ZERO_-::z. • • / DIGITAL INPUT
• /
-FS
DIGITAL
'/.,;/
/.
LSB
STEP NONLINEARITY
Step size deviation from ideal within a chord.
/
~
/
~~~Tt.~~~
+FS
DIGITAL
"-
U)
I" IDEAL ANALOG OUTPUT
•/
RESOLUTION~ / ..
/. -/ :=:6~G
<_- .t. _ ~O~R~N~
UNIPOLAR D/A CONVERTERS
a:
ANALOG
I- -
-
-
-
-
-
IDEAL
ANALOG~
OUTPUT
-e
) \
/
.
/.
/
/ •• /
ANALOG
OUTPUT
/
• /
/
•
~
••
/
•
••
•
/
•
/
GA:=O~A~~:
/
,,---
/
/
/
/
-
THE LINE)
RESOLUTION
~~~~~~NT
BIT (LSB)
IDEAL
~
/
ANALOG ERROR
/T -TOLERANCE
DIGITAL
INPUT
FS
DIGITAL
o
~
DIGITAL·TO-ANALOG CONVERTER
A circuit for converting a digital code word into discrete
analog quantities according to a prescribed relationship.
FULL SCALE
Essentially a digitally controlled attenuator, a DAC can only
provide fractional multiples of the analog input. The maximum analog output is 2" -1 times the "scaled" (a possible
gain factor) analog input. An output that equals the
"scaled" analog input would be considered Full-Scale. Note
that a D/A converter can only achieve a full-range output
that is less than Full-Scale (by an LSB).
Offsetting the DAC output with a value equal to minus onehalf of full-scale will give an analog output range that goes
from an offset zero scale which Is renamed "negative FullScale" to a positive fUll-range output that is 1 LSB less than
"positive FUll-Scale". Sign magnitude DAC's have symmetrical output ranges that are one LSB less than FullScale. For both positive and negative outputs.
~~~~,;r L:..._~_ _ _ _ _ _ _ __
(SHIFTS THE LINE
FROM ZERO)
~
CJ
2"
+FS
ANALOG
a:
1&1
t-
1&1
-FS
LINEAR DIGITAL·TO·ANALOG CONVERTER TERMS
AND DEFINITIONS
D/A Converters accept a digital input code and convert this
input into an equivalent analog voltage or current output.
PMI's D/A Converters utilize the current-switched ladder network design principle which provides fast settling and
reduced switching transients. D/A Converters are classified
according to the type of analog output, the input code and
multiplying capability.
II
FULL OUTPUT RANGE (FR)
The output analog signal span expressed in units of voltage
or current.
PAGE 10·3
BIT
A binary unit (0 or 1) that provides the weighting for each
power of 2 in a digital word. For an n-Bit DAC, the Mose
Significant Bit (MSB) gives an output equal to 2- 1 (FS) and
the Least Significant Bit (LSB) gives an output equal to 2- n
(FS).
DIGIT
A numeric unit in a decimal system that identifies the weight
of each power of ten in a digital word. A digit can have any
value from 0 to 9. For an n-Digit DAC, the Most Significant
Digit (MSD) gives an output equal to (0 to 9) (10- 1) and the
Least Significant Digit (LSD) gives an output equal to (0 to 9)
(lO- n ). A digit in a Binary-Coded-Decimal (BCD) DAC is
represented by four bit binary word that can take on values
from 0000 to 1001 (0 to 9).
LEAST SIGNIFICANT BIT (LSB)
The smallest incremental analog output change obtainable
and equal to the full scale output range divided by
2n where n = number of bits.
LSB = FS
the output step size for adjacent digital Input codes is 1
± 1/2 LSB or 1/2 to 3/2 LSB.
RELATIVE ACCURACY
Relative accuracy defines the deviation in % of full-scale or
LSBs, from an ideal straight line drawn between the ideal
zero output and the full range output. Thus the relative accuracy specification includes the zero scale offset error as well
as non-linearity, and gain error. Relative accuracy defines
how well "relative" proportions will be maintained over the
full analog output range.
ABSOLUTE ACCURACY
Absolute accuracy defines how closely the output of a DAC
approximates the ideal straight line drawn from the ideal
zero output to the full-scale output. Absolute accuracy is inclusive of all error terms. The relative accuracy specification
will be the absolute accuracy spec at the moment of gain error correction. Time, temperature and supply voltage
changes will degrade the absolute accuracy specification.
ACCURACY DEFINED
2n
MOST SIGNIFICANT BIT (MSB)
The largest incremental analog output change obtainable
by switching a single logic bit input. It is ideally equal to:
MSB
/'
/
/
FS
=2
LINEAR
/
/
/
ZERO SCALE OFFSET ERROR (ZS)
IOEAL/
The measured analog output when the digital input code
corresponds to an analog value of zero. Usually expressed
as a percentage of nominal Full-Scale Range but also expressed in ppm, LSBs, or given in units of current or voltage.
LINEAR
/
ZERO
OFFSET
(2S)
/
/
T
A. LINEARITY
ZERO SCALE SYMMETRY ERROR
For a Sign-Magnitude DIA Converter, zero scale symmetry is
the change in the analog output produced by switching the
sign bit with a zero code input to the magnitude bits. This
quantity is expressed in units of current, voltage, or in fractions of an LSB.
/
-........./
IDEAl.
,...
/
\t
OAC WITH
Zs *
Z
o
QUADRANT IV
- ANALOG
OUTPUT
(J
~
MULTIPLYING DAC's
The D/A function involves multiplying an analog reference
byadigital word (VO=VREF.X). Depending on design, some
DAC's can multiply only positive digital words. This is known
as single Quadrant (Quadrant 1) operation, Two Quadrant
operation, involving Quadrants I and III, is achieved by offsetting a single Quadrant DAC by a negative MSB (1/2 of fullscale) so that a bipolar digital code, in which the MSB
becomes the sign bit, can multiply a unipolar reference (positive slope), for example, Quadrants I and III. Full four Quadrant multiplication requires a DAC that can accept a reference of either polarity, and positive and negative values of
digital input.
GAIN ERROR
The difference between the actual analog output range
and the Ideal analog output range expressed as a percent
of Full-Scale or in terms of LSB value.
SETTLING TIME
The elapsed time for the analog output to reach its final
value within a specified error band after the corresponding
digital input code has been changed. Usually specified for
a Full-Scale Range change and measured from the 50%
FEED THROUGH
An AC specification on a multiplying DAC which defines the
frequency at which a 1/2 LSB (pk-pk) AC signal is seen althe
DAC output with all bits in the "OFF" state (zero output code).
POWER SUPPLY SENSITIVITY
The change In the output of the converter due to a change in
the power supply value. This may be expressed as a percent
of Full-Scale Range per one percent change in the power
supply or as a percent of Full Scale per volt of power supply
change. Normally this Is specified at DC, but is sometimes
specified over a given frequency range.
FULL SCALE TEMPERATURE COEFFICIENT
OR GAIN DRIFT
This Is the change In the Full Analog Range from the 25°C
value and either temperature extreme divided by the corresponding change in temperature and is expressed in
ppm/oC.
PAGE 10-5
MISCELLANEOUS TEMPERATURE COEFFICIENTS
Although nonlinearity and differential nonlinearity should
be specified as a worst case error over temperature, some
manufacturers do specify a drift component on these terms.
As In gain drift, they are specified as the change from the
25'C values to either temperature extreme divided by the
corresponding change In temperature and expressed in
ppm of FSRI 'C.
a voltage compliance within which the converter meets the
specified error limits.
RESISTIVE OUTPUT D/A CONVERTER
The output of the converter Is a current, but has a low output
resistance (typically 1·20k Ohm) and nearly zero output
voltage compliance.
D/A CONVERTERS BY OUTPUT TYPE
VOLTAGE OUTPUT D/A CONVERTER
CURRENT OUTPUT DlA CONVERTERS
The output of the converter Is a true digitally controlled current source or sink which has a high output Impedance and
The output of the converter Is a voltage source, and Is
characterized by low output Impedance and a specified load
driving capability.
!;lAC SELECTION GUIDE. Voltage Output. Commercial Temperatura Rangt (0· to 70'C)
Reaolutlon
B-Blt
Linear
PMI
Part Number
Nonlinearity
Z8roScale
0I18et (% F.S.)
ZS·C
70·C
2S·C
:1:0.45
:1:0.25 typo :1:0.25 Iyp.
6
6
:1:160 max.
3.0 max.
:1:0.45
:1:0.40 typo
6
6
:1:160 max.
3.0 max.
(% F.s~
25·C
O·to
7O·C
DAc.olCY
:1:0.40
DAC.Q1HY
:1:0.40
Monotonlclty
(Blla)
O·to
70·C
:1:0.40
GalnT.C.
(PPW·C)
Ext.
Inl.
ReI.
Rei
Settling
TIme
(pa)
Output
Vollage
Range
Power Codes
DI••lpa.
lion
(mW)
:l:l0Vto
:l:ll.89V
250 Compl ...
ment
Binary
:l:l0Vto
250
Oompl ...
ment
Binary
250
:I: 11.89V
Compl ...
ment
Binary
:I: 11.89V
DAc.o1DY
8-Blt
+Slgn
Linear
I()'Blt
Unear
:1:0.76
:1:0.78
:l:O.50typ.
:1:0.50
6
6
:1:160 max.
3.0 max.
:l:l0Vto
DAC-206EY
:1:0.4
:1:0.78
:1:0.25
:1:0.25
6
6
:1:120 max.
3.0 max.
:l:5V,
+10Vor
:l:l0V
270 Oompl ...
ment
Binary
DAC-206FY
:1:0.80
:1:1.2
:1:0.5
:1:0.5
6
6
::1:160
max.
3.0 max.
:l:5V,
+10Vor
:l:l0V
270 Oompl ...
ment
Binary
DAC·208EX
:1:0.1
:1:0.1
:1:0.1
±0.15
8
8
:1:40 max.
:l:15typ.
0.75 typo
:l:5Vor
:l:l0V
290
Sign
Magnl·
tude
DAC-208FX
:1:0.2
:1:0.2
:1:0.1
:1:0.1
8
8
:t60 max.
:1:30 typo
0.75 typo
:l:5Vor
:l:l0V
290
Sign
Magnl·
tude
DAc.o2ACXl
:1:0.10
:1:0.10
:1:0.10
:1:0.10
10
10
:1:60 max.
:1:30 typo
2.0typ.
:l:l0Vto
:I: 11.5V
300
Sign
Magnl·
tude
DAC-02BCXl
:1:0.10
:1:0.10
:1:0.10
:1:0.10
9
9
:1:60 max.
:1:30 typo
2.0typ.
:l:l0V to
:I: 11.5V
300
Sign
Magnl·
tude
DAC.Q2CCXl
:1:0.20
:1:0.20
:1:0.10
:1:0.10
8
8
:1:60 max.
:1:30 typo
2.0typ.
:l:l0Vto
:I: 11.5V
300
Sign
Magn;:
tude
DAC-02DDXl
:1:0.40
:1:0.40
:1:0.10
:1:0.10
7
:1:150 max. ·:1:30 typo
2.0typ.
:l:l0V
350
Sign
Magnl·
tude
·DAC.Q3ADXl
:1:0.10
:1:0.10
10
:l:60"typ.
:1:40 typo
2.0typ.
+10Vto
+11.5V
350
Natural
Binary
°DAC-03BDXl
:1:0.10
:1:0.10
9
:1:60 typo
:l:4Otyp.
2.0typ.
+10Vto
+11.5V
350
Natural
Binary
°DAC-03CDXl
:1:0.20
:1:0.10
8
:1:60 typo
:1:40 typo
2.0 typo
+10Vto
+11.5V
350
Natural
Binary
° DAC-03DDXl
:1:0.4
:1:0.1
7
:1:60 typo
:l:4Otyp.
2.0 typo
+10V
+11.5V
350
Natural
Binary
° DAC-03 available all grades with +5V output - use X2 sufllx.
PAGE 10-8
DAC SELECTION GUIDE. Volta"e Output. Commercial Temperature Range (0' to 70 'C)
Reeo·
lutlon
I()'BI!
Unear
PMI
Part Number
DAc-04BCXl
Nonlinearity
(% F.S.)
25'C
0' to
70'C
:1:0.10
Zero Scale
Oil." (% F.S.)
70'C
25'C
:1:0.10
:l:O.ltyp.
Monotonlclty
(Bltl)
0' to
70'C
25'C
9
9
Gain T.C.
(PPM/'C)
Int.
Ext.
Ret.
R.t
:l:50typ.
:l:3Otyp.
(,AI)
Output
Volta"e
Range
1.5typ.
:l:5Vtyp.
Sattlln"
Time
P_er Cod••
Dllllp.·
tlon
(mW)
300
Two's
Comple·
ment
DAC.Q4CCXl
:1:0.20
:1:0.20
:l:O.ltyp.
8
8
:1:90 max.
:l:3Otyp.
1.5typ.
:l:5Vtyp.
300
DAc-04DDXl
:1:0.40
:1:0.40
:l:O.ltyp.
7
7
:1:150 max. :1:50 typo
2.5typ.
:l:5Vtyp.
350
Two'.
Comple·
ment
Two's
Comple-
ment
"DAC05EX
:1:0.10
:1:0.20
:1:0.05
:1:0.10
10
10
:1:100
:1:30 typo
2.0 typo
:l:l0Vto
:I: 1'.5V
300
Sign
Magnl·
tude
"DAC-OSFX
:1:0.20
:1:0.30
:1:0.05
:1:0.10
9
9
:1:100
:l:3Otyp.
2.0typ.
:l:l0Vto
:I:".5V
300
Sign
Magnl·
tude
"DAC-05GX
:1:0.40
:1:0.50
:1:0.05
:1:0.10
8
8
:1:100
:l:3Otyp.
2.0 typo
:l:l0Vto
:I: 1'.5V
300
Sign
Magnl·
tude
DAC-06EX
:1:0.10
:1:0.20
:1:0.05
:1:0.10
10
10
:1:100
:l:3Otyp.
1.5typ.
:l:l0Vto
:I: 1'.5V
300
Two's
Complement
DAC-06FX
:1:0.20
:1:0.30
:1:0.05
:1:0.10
9
9
:1:100
:l:3Otyp.
1.5typ.
:l:l0V to
:I: 1'.5V
300
300
Two's
Complement
290
Sign
Magnl·
tude
DAC-06GX
:1:0.40
:1:0.40
:1:0.05
:1:0.10
8
8
:1:100
:l:3Otyp.
1.5typ.
:l:l0Vto
:l:l'.5V
"DAC·210EX
:1:0.05
:1:0.05
:1:0.05
:1:0.08
10
10
:1:40 max.
:l:15typ.
1.5typ.
:l:l0Vto
:I: 1'.5V
"DAC·210FX
:1:0.05
"DAC·210GX
:1:0.1
:1:0.1
:1:0.1
:1:0.1
Two's
Complement
10
10
:1:50 max.
:l:3Otyp.
1.5typ.
:l:l0Vto
:I:".5V
290
Sign
Magnl·
tude
9
9
:l:3Otyp.
:l:3Otyp.
1.5typ.
:l:l0Vto
:I:".5V
290
Sign
Magnl·
tude
•• Sign and magnitude coding (11·Blt).
PAGE10·j
II
1/1
a:
...a:
UI
UI
>
Z
0
U
0(
C
DAC SELECTION GUIDE· Voltage Outpul • Military Temperalure Range (-5S"C 10 +126"C) THESE PRODUCTS AVAILABLE IN 883B
GalnT.C.
(PPM/·C)
Inl.
Exl.
Rei.
R.I
BeHling
Time
11<8)
Output
Vollage
Range
Power Code.
DI ••
lion
(Pel)
6
±80
3.0 max.
±10Vto
±11.75V
250mW Complement
Binary
6
6
±80
3.0 max.
±10Vto
±11.75V
250mWComplement
Binary
±0.25
6
6
±120
3.0 max.
±10Vto
±11.75V
250mWComplement
Binary
:0:0.40
±0.40
6
6
±80
3.0 max.
±10Vlo
±11.75V
250mW Comple·
ment
Binary
±0.80
0.25
0.25
6
6
±80
3.0 max.
±10V
270mW Bipolar
±0.80
±1.2
0.5
0.5
6
6
±160
3.0 max.
±11.75V
270mW Bipolar
:to.l
±0.1
±0.1
8
8
±4O
±15typ. 0.75 max.
±10V
290mW Sign
Magni·
tude
DAC·208BX
±0.2
±0.2
±0.15
8
8
±80
±30 typo 0.75 max. ±11.75V
290mW Sign
Magnl·
tude
DAC-05AXI
±0.10
:0:0.20
±0.05
±0.10
10
10
±80
±30 typo
2.0 typo
±10Vto
±11.75V
300mW Sign
Magnl·
tude
DAC-05BXl
±0.20
±0.30
±0.05
±0.10
9
9
±9O
±30 typo
2.0 typo
±10Vto
±11.75V
300mW Sign
Magnl·
tude
DAC·05CXl
±0.40
:to.50
±0.05
±0.10
8
8
±120
:030 typo
2.0 typo
±10V to
±11.75V
300mW Sign
Magni·
tude
DAC·06BX
±0.20
±0.30
±0.05
±0.10
9
9
±9O
±30 typo
1.5 typo
±10V to
±11.5V
300mW Two's
Comple·
DAC·06CX
:to.4O
±0.50
±0.05
±0.10
8
8
±120
±30 typo
1.5typ.
±10Vto
±11.5V
300mW Two's
Complement
DAC·210AX
±0.05
±0.075
:0:0.05
±0.06
10
10
±4O
±15 typo
1.5 typo
±10Vto
±11.5V
325mW Sign
Magnl·
tude
DAC·210BX
±0.05
:to.l0
±0.1
:to.l
10
10
:0:80
:t30 typo
1.5 typo
±10V to
±11.5V
325mW Sign
Magni·
tude
Nonllnearlly
(% F.S.)
2S·C
-55·Cto
+12S"C
Zero Scale
Oll.el (% F.S.)
26·C
-55"C 10
+12S·C
DAC-OIAY
±0.20
±0.30
±0.25
±0.25
6
DAC·01Y
±0.40
±0.45
±0.25
±0.25
DAC-OIBY
±0.40
±0.45
±0.25
DAC·01FY
±0.40
±0.45
DAC·206AY
±0.4O
DAC·206BY
DAC·208AX
ResOlullon
PMI
Part Number
6·Bit
Linear
8·Bit
Linear
100Bit
Linear
Monotonlclty
(Blls)
-SS·C 10
2S"C
+12S"C
,ps·
ment
PAGE 10-8
DAC SELECTION GUIDE. Current Output. Commercial Temperature Range (00 to 70°C)
Reealutlon
PMI
Part Number
Nonlinearity
(% F.S.)
OOID
25°C
Zero Seale
Oflset (% F.S.)
25°C
DoC
70~
8-BII
Linear
8-BII
Lalched
10·BII
Linear
8/12
Com·
pandlng
Monotonlclty
(Blta)
0° to
25°C
70~
70~
GalnT.C.
(PPM/oC)
Int.
Ext.
Rei.
Rei
Settling
Time
(PS)
Output
Compll·
ance
(Volts)
Power Output
Dlsslpa· Imped.
anca
tlon
(mW)
(MD)
oAC'()8HO(HP)
:0.10
:0.10
O.OS
O.OS
8
8
:SO max.
0.13S
-10Vlo
+18V
174
>20
oAC-08EQ(Ep)
:0.19
:0.19
0.10
0.10
8
8
:SO max.
0.150
-10V 10
+18V
174
>20
oAC.()8CO(CP)
: 0.39
:0.39
0.20
0.20
8
8
:80 max.
0.150
-10V 10
+18V
174
>20
oAC·l408A·
80(7P)
:0.19
:0.19
8
8
:20 Iyp.
0.250
-SV 10
+O.SV
265
oAC·l408A·
70(7P)
:0.39
:0.39
7
:20Iyp.
0.250
-O.SV 10
+O.SV
265
oAC·1408A·
60
:0.78
:0.78
6
6
:20Iyp.
0.250
-O.SV 10
+O.SV
265
oAC·20CO(CP)
:O.SO
:0.50
0.250
0.250
2 olglls
2 olglls
:80 max
0.lS0
-10V 10
+18V
200
>20
oAC-808EX
:0.1
:0.1
0.1
0.1
9
8
:50
O.S
-SVto
+8V
170
>20
oAC-808FX
:0.19
:0.19
0.1
0.1
8
8
:80
O.S
-SVto
+8V
170
>20
oAG-808GX
:0.39
:0.39
0.1
0.1
8
8
:80
0.5
-SVto
+8V
170
>20
oAC-8BBEX
±0.1
±0.1
±0.1
±0.1
8
±50
0.2S
-SVto
+8V
190
oAC-888FX
±0.19
±0.19
±0.1
±0.1
±80
0.25
-5Vto
+8V
190
III
lie
~
lie
oAG-l0FX
:O.OS
:O.OS
0.01
0.01
10
10
:2S max.
0.13S
-S.SV 10
+10V
460
oAC·l0GX
:0.1
:0.1
:0.01
:0.1
10
10
:50 max.
lS0
-S.SV 10
+10V
460
oAGl00AC03/04
:0.05
:O.OS
0.013
0.013
10
10
:60
0.37S
300
oAC·
l00BC03/Q4
:0.10
:0.10
0.013
0.013
9
9
:60
0.300
300
oAC·
100CC03/04
:0.20
:0.20
0.013
0.013
8
8
:60
0.22S
300
oAC·
1000003/04
:0.30
:0.30
0.013
0.013
8
8
:120
0.150
300
~
Z
o
U
~
oAC·l01EO
:0.1
0.013
10
:120
0.2
360
oAC·l01FO
:0.2
0.013
9
:120
0.2
360
oAG-l01GO
:0.3
:120
360
0.2
0.02
8
oAG-76EX:'Iz Slep
'I. Slep
128 Sleps
0.500 Iyp.
-SV 10
+18V
207
oAG-76CX
:1 Slep
'Iz Slep
128 Sleps
0.500 Iyp.
-SV 10
+18V
207
oAC·76oX
: 1 'Iz Slep
'Iz Step
128 Steps
O.SOO typo
- SV to
+18V
207
-5Vto
+10V
37S
oAC-312FR ±0.02S'
±0.025
±0.003
±0.003
12
12
·Differential Non-Linearity
PAGE 10-9
±40
0.2S
II
>10
DAC SELECTION GUIDE. Current Output. Indualrlal Temperalure Range (25" to +85·C)
ReaD·
lullon
PMI
Part Numb.r
Nonlln.arlly
("Ie F.S.)
O· 10
25"C
Zero Seale
Ollset ("Ie F.S.)
25"C
7O"C
+U~
lo-llt
Linear
811().8lt
Companding
Monolqnlclty
(BIIs)
25"C
0" 10
+U~
+U~
DAC·
l00AA07/08
:1:0.05
±0.05
0.013
0.013
10
10
DAC·
l00AI07/08
:1:0.05
:1:0.05
0.013
0.013
10
10
DAC·
l00AC07/08
:1:0.05
±0.05
0.013
0.013
10
OAC·
1001107/08
±0.10
:1:0.10
0.013
0.013
DAC·
l008C07/08
:1:0.10
0.10
0.013
OAC·
l00CC07/08
:1:0.20
:1:0.20
OAC·
1000007/08
:1:0.30
±0.3O
GalnT.C.
(PPM/·C)
Inl.
Exl.
R.I.
Rei
Settling
Time
(pa)
OulpUI
Compll·
ance
(Volta)
Oulpul Power
Impedo DI.alpe·
ance
lion
(KII)
(Pd)
0.375
500 typo 250mW
±30
0.375
500 typo 250mW
10
:1:60
0.375
500 typo 250mW
9
9
±3O
0.300
500 Iyp. 250mW
0.013
9
9
:1:60
0.300
500 typo 250mW
0.013
0.013
8
:l:eo
0.225
500 typo 250mW
0.013
0.013
8
:1:120
0.150
500 typo 250mW
CAe-78E
±1/2 Step
1/6 Slep 128 Steps
0.5
-5Vlo
+18V
262
>10
CAe-78F
±1 Slep
1/4 Slep 128 Sleps
0.5
-5Vto
+16V
262
>10
CAe-78G
±11/2 Slep
1/2 Slep 128 Sleps
0.5
-5VIO
+18V
262
>10
Settling
Time
Output
Compll·
ance
(Volta)
Output Power
Impedo DI.alpe·
ance
tlon
(Mil)
(Pd)
DAC SELECTION GUIDE· Currenl Outpul • Mllliary Temperalure Range (-66" 10 +125"C)
R.ao·
lutlon
8-811
Linear
8-llt
Latched
10·llt
Linear
Nonllnearlly
("Ie F.S.)
-55"C to
25"C
+125·C
Zero Scale
Oll8et ("Ie F.S.)
25·C
-55"C 10
+t25·C
CAC-OeAO
:1:0.10
:1:0.10
0.05
0.05
8
8
±50
0.135
-10V to
+18V
>2OMO 174mW
typo
CAC.oaO
:1:0.19
±0.19
0.10
0.10
8
8
:1:80
0.150
-10V to
+18V
>2OMO 174mW
typo
SSS·I508A·
080
:1:0.19
:1:0.19
0.2
0.2
8
8
0.250 typo
- 5V to
+0.05V
265mW
CAC-a08AX
:1:0.1
0.1
0.1
8
8
:1:50
0.500
-5Vto
+8V
>20
170mW
CAC-a08IX
:1:0.19
0.1
0.1
8
8
:1:60
0.500
-5Vto
+8V
>20
170mW
CAC-888AX
0.1
0.1
0.1
8
8
±50
0.250
-5Vlo
+8V
>20
190mW
CAC-888BX
0.19
0.1
0.1
8
8
±60
0.250
-5Vto
+8V
>20
190mW
PMI
Part Number
Monotonlclty
(11t8)
-66"C to
+125·C
25"C
Gain T.C.
(PPM/"C)
Ext.
Int.
Rei.
Rei
(pa)
CACl00AC05l0e
:1:0.05
:1:0.05
0.013
0.013
10
10
:1:16
0.375
SOOkO 300mW
typo
OACl001105l0e
:1:0.10
:1:0.12
0.013
0.013
9
9
:1:30
0.300
500kll 300mW
typo
CAC·
l00BC05l06
:1:0.10
:1:0.10
0.013
0.013
9
9
:1:30
0.300
600kll 300mW
typo
CAC100CC05l06
:1:0.20
:1:0.20
0.013
0.013
8
8
:1:60
0.225
500kll 300mW
typo
CAC-l0IX
0.05
0.05
0.013
0.013
10
10
:1:25
0.135
-5.5V to
+10V
460mW
CAC·l0CX
0.1
0.1
0.013
0.013
10
10
:1:50
0.150
-5Vto
+10V
460mW
PAGE 10-10
DAC SELECTION GUIDE. Currenl Oulpul • Mllliary Temparalure Range (-55" to +125"C)
Roao·
lullon
PMI
Part Number
Nonllnearlly
(OJ. F.S.)
-55"C 10
25"C
+125"C
±0.25
zero Scale
Ollset (OJ. F.S.)
25"C
-55"C to
+125"C
Monotonlclly
(Blls)
25"C
-55"C to
+125"C
GalnT.C.
(PPM/"C)
Inl.
Exl.
Ral.
Rei
±40
Settling
Time
(jds)
Oulpul
Compll·
ance
(Volls)
Oulpul Power
Imped· Ol.slpa·
ance
lion
(Mil)
(Pel)
DAC-312BR
±0.025
DAC·76BX
V. Step
'I. Step
128 Steps
0.500 typo
-5Vto
+tBV
192mW
DAC·76X
1 Step
V. Step
128 Steps
0.500 typo
-5Vto
+IBV
192mW
±0.OO3
±0.OO3
12
12
0.25
-10Vto
+8V
375
>10
en
II:
W
~
W
>
Z
o(,)
~
PAGE 10-11
PMI
DAC-Ol
6-81T VOLTAGE OUTPUT D/A CONVERTER
®
FEATURES
GENERAL DESCRIPTION
•
•
•
•
•
•
The DAC-01 Is a complete monolithic 6-bit digital-to-analog
converter, Incorporating current steering logic, current
sources, diffused resistor ladder network, precision voltage
reference and fast summing op amp on one chip_ Monolithic
construction provides small size, light weight, low power
consumption and very high rellabllity_ Wide power s.upply
range, three output voltage options, and three input code
options assure flexibility for a wide variety of applications.
A seventh bit may also be added for greater resolution. The
DAC-01 is ideal for CRT deflection circuits, servo positioning controls, digitally programmed power supplies and
pulse generators, modem and telephone system digitizing
and demodulation circuits, digital filters, and 6-bit AID converters. Introduced in 1970, the DAC-01 is still the fastest,
lowest power, most accurate 6-blt complete monolithic DAC
ever made.
Fast .................. 3JLS SeHling Time (Maximum)
Complete. . . . . . .. Includes Reference, Ladder, Op Amp
Low Power Consumption ......... 250mW (Maximum)
6-Blt Resolution. . . . . . . . . . . . . . . . . . . .. 7·Blt Accuracy
30utputOptions ................ +10V, ±SV, ±10V
Standard Power Supplies. . . . . . . . . . . .. ± 12V to ± 18V
-Sso/+125°C or oono°c Ranges Available
• TTL, Compatible Logic Levels
• Models with MIL·STD·883 Class B Processing
Available From Stock
ORDERING INFORMATIONtt
14 PIN DIP-HERMETIC
FULL TEMP_
N.L. LSB
MILITARY
TEMP.
±1/8
DAC01AY"
±1I4
DAC01Y"
DAC01BY"
DAC01FY"t
COMMERCIAL
TEMP.
PIN CONNECTIONS
MSBA1
DAC01CY
DAC01HYt
DAC01DY
±1/2
"Available with MIL-STD-8B3B processing. To order add suffix/BB3.
tUnipolar only - all others unipolar or bipolar.
ttAlllisted parts are available with 160 hour burn·in. See Ordering Information.
Section 2.
14-PIN HERMETIC DIP (V-Suffix)
SIMPLIFIED SCHEMATIC
, - - - - - - - DIGITAL LOGIC INPUTS - - - - - - - . . .
LSB
MSB
SUM
MODE
v+
7
11
10
SCALE
FACTOR
5.4k
S.4k
ANALOG
OUTPUT
14
FULL
SCALE
ADJUST
13
v-
PAGE 10-12
BIPOLARI
UNIPOLAR
12
GROUND
DAC·01 6·BIT VOLTAGE OUTPUT D/A CONVERTER
ABSOLUTE MAXIMUM RATINGS (See Note 3)
Storage Temperature ............... -65·Cto +150·C
Lead Soldering Temperature (60 sec.) . . . . . . . . . . . .. 300·C
Output Short Circuit Duration (Note 2) ......... Indefinite
Operating Temperature
DAC·01A, DAC·01, DAC"()1B,
DAC·01F ..................... -55·Cto +125·C
DAC-01C,DAC·01H,DAc"()1D .......... O·Cto +70·C
DICE Junction Temperature (T j ) ••••••• -65 0 C to + 1500 C
V + Supply Voltage to Ground ............... 0 to + 18V
V - Supply Voltage to Ground ............... 0 to -18V
Logic Input to Ground. . . . . . . . . . . . . . . . . . .. -0.7 to +6V
Internal Power Dissipation (Note 1) .............. 500mW
ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
Output Options
NOTES:
1. Rating applies to ambient temperatures of 100 °C. For temperatures above
100·C. derate linearly at 10mW/·C.
2. Short circuit may be to ground or either supply. Rating applies to +125'C
case temperature or + 75 °C ambient temperature.
3. Absolute maximum ratings apply to both DICE and packaged parts. unless
otherwise noted.
at Vs = ±15V and over the rated operating temperature range unless otherwise noted.
DAC'()1A
DAC·01
DAC'()1B
DAC'01F
DAC·01C
DAC'()1H
DAC'()1D
Unipolar
Bipolar
Unipolar
Bipolar
Unipolar
Bipolar
Unipolar
Unipolar
Bipolar
Unipolar
Unipolar
Bipolar
UNITS
Temperature Range
TA
-55/+125
-55/+125
-55/+125
-55/+125
0/+70
0/+70
0/+70
'C
Nonlinearity 25 'C/Maximum
NL
±.0.20
±0.40
±O.40
±0.40
±0.40
±0.40
±0.78
%FS
Nonlinearity Over
Temperature - Maximum
NL
±0.30
±0.45
±0.45
±0.45
±0.45
±0.45
±0.78
%FS
Full Scale Tempco Maximum
To
±80
±80
±120
±80
±160
±160
±160
ppm/'C
Unipolar Zero Scale Output
Voltage - Maximum (Note 1, 2)
Vzs
25
25
25
40
25
40
50
mV
ELECTRICAL CHARACTERISTICS
for all DAC·01 grades, Vs = ±15V and over the rated operating temperature range unless
otherwise noted.
DAC·01
PARAMETER
SYMBOL
CONDITIONS
Unipolar Full Range
Output Voltage (Note 3)
VFR
2kD load, logic,,0.8V, short pin 13 to pin 14.
Short pin 12 to Ground and pin 10 to pin 11.
Bipolar Output Voltage (Note 3)
±5 Volt Range
VFR+
VFR _
± 10 Volt Range
VFR+
VFR Bipolar Offset Voltage (Note 1)
±1I2 (I VFR + 1-IVFs·l)
MAX
UNITS
+10.0
+11.75
V
+4.93
-5.94
+5.94
-4.93
V
+9.86
-11.89
+11.89
-9.86
V
MIN
2kD load, short pin 11 to pin 12.
Short pin 13 to pin 14, short pin 10 to pin 11.
Logic Inputs,; 0.8V
Logic Inputs >:2.0V
Open pin 10
Logic InputssO.8V
Logic Inputs2:2.0V
±5 Volt Range
±10 Volt Range
TVP
±40
±80
Resolution
Logic Input "0"
V'NL
logic Input "1"
V'NH
logic Input Current, Each Input
I'N
Pss
Power Supply Sensitivity
±70
±140
mV
6
Bits
0.8
2.0
±12VsVss ±18V VFS*10.0V
Power Consumption
Pd
Supply Current
1+
1-
V+ = +15V
V-= -15V
No Load
Settling Time to ± 112 LSB
(Note 4)
t.
2.0Vsloglc levelsO.8V TA =25'C
V
V
±2.0
±8
p.A
±0.01
±0.15
'IoV Fs!V
200
250
mW
7.3
9.3
mA
1.5
ps
NOTES:
1. Zero scale or bipolar offset voltage can be trimmed to zero volts or to the
exact one's or two's complement condition with an external resistor network to pin 11.
3. Full scale is adjustable to precisely 10 volts for unipolar operation and
10 volt or 20 volt peak·to·peak bipolar operation with an external 500
ohm potentiometer from pin 14 to V -.
2. Logic input vollage>:2.0 volls.
4. Guaranteed by design.
PAGE 10-13
II
DAC-G1 a-BIT VOLTAGE OUTPUT DlA CONVERTER
DICE CHARACTERISTICS
1. Bl (MSB)
2. B2
3. B3
4. B4
5. B5
8. B8 (LSB)
7. V+
8. ANALOG OUTPUT (VOLTAGE)
9. GROUND
10. SCALE FACTOR
11. SUM NODE
12. BIPOLAR/UNIPOLAR
13. V14. FULL SCALE TRIM
DIE SIZE 0.092 x 0.054 Inch
Refer to Section 2 for additional DICE Information.
ELECTRICAL CHARACTERISTICS at 25° C.
DAC-G1N
BIPOLAR AND
UNIPOLAR
DAC-01G
BIPOLAR AND
UNIPOLAR
PARAMETER
SYMBOL CONDITIONS
LIMIT
LIMIT
UNITS
Nonlinearity
NL
Vs =±15V
114
1/2
% MAX
Zero Scale Voltage
Vzs
Vs =±15V
25
35
V MAX
ELECTRICAL CHARACTERISTICS at 25° C for all grades; Vs = ±15V, unless otherwise noted.
DAC-G1
PARAMETER
Unipolar Full Scale Output
Voltage (All Models)
Bipolar Output Voltage
± 5 Volt Range
± 10 Volt Range
SYMBOL
CONDITIONS
LIMIT
UNITS
VFR
2kO Load, Logic:;; 0.8V, Short V- to Full Scale Trim, Unipolar/
Bipolar to Ground, and Scale Factor to Sum Node
10.00
11.75
VMIN
V MAX
2kO Load, Short Sum Node to Unipolar/Bipolar.
Short V- to Full Scale Trim and Scale Factor to Sum Node.
Logic Inputs:;; 0.8V
Logic Inputs" 2.0V
Open Scale Factor
Logic Inputs:;; 0.8V
+4.93
-5.94
VMIN
V MAX
VFR +
VFRVFR +
V FA -
Bipolar Offset Voltage
±1/2 (IVFR+I-IVFR-I)
Logic Inputs;:;: 2.0V
± 5 Volt Range
±10 Volt Range
+9.78
VMIN
-11.89
V MAX
±1/2
LSB MAX
6
Bits MAX
Logic Input "0"
V1NL
0.8
V MAX
Logic Input "1"
V1NH
2.0
VMIN
Vov
±8.0
/loA MAX
0.15
%FSNMAX
250
mWMAX
Resolution
. Logic Input Current, Each Input
Power Supply Rejection
PSR
±12V:;; Vs:;; ±18V. Vs= 10.0V
Power Consumption
Pd
No Load
TYPICAL ELECTRICAL CHARACTERISTICS at 25°C.
DAC-01N
TYP
DAC-01G
TYP
PARAMETER
SYMBOL
CONDITIONS
Settling Time
ts
To ±1/2 LSB
1.5
1.5
Vs = ±15V
60
90
Full Scale Tempco
PAGE 10-14
UNITS
ppm/'C
DAC·01 6·BIT VOLTAGE OUTPUT D/A CONVERTER
BASIC CIRCUIT CONNECTIONS
APPLICATIONS INFORMATION
FULL SCALE ADJUSTMENT TECHNIQUE_
-1SV
FULL SCALE ADJUST
OPTIONAL ZERO SCALE· OR
BIPOLAR OFFSET ADJUSTMENT
100k"
v-
INPUT CODES
The DAC"()1 utilizes standard complementary binary coding
for unipolar mode operation (all inputs high produces zero
output voltage). One's complement coding may be imple·
mented by shorting pin 11 to pin 12 and inverting the MSB
before entering pin 1 (all other bits are not inverted). Com·
plementary offset binary coding may be implemented by
shorting pin 11 to pin 12, and injecting approximately SpA into
pin 11 (which isat ground potential) by using the "zero scale
or bipolar offset adjustment" circuit. Two's complement
code is achieved when the MSB for complementary offset
binary Is complemented.
v+
A 5000 pot from pin 14 to V - can be used to adjust the full
range output voltage to exactly 10 volts in unipolar mode or
10 to 20 volts peak·ta-peak in bipolar mode. If no pot is used,
tie pin 14 to V-.
47OkO
I
"
SCALE FACTOR
DAC~1
For + 10 volts or ±S volt outputs, short pin 10 to pin 11 (ad·
justs the feedback resistor around the output amplifier). For
±10 volt output, leave pin 10 open. Intermediate output
voltages may be obtained by placing a pot between pin 10
and pin 11, but this will seriously degrade the full scale
temperature coefficient due to the mismatch between the
+ 11S0ppm/·C tempco of the diffus!3d resistors and the pot
tempco.
ADDITION OF 7TH BIT
-15V
100kn
IN4148
2.1Mn
CAPACITIVE LOADS
When driving capacitive loads greater than 50pF in Unipolar
mode or 30pF in Bipolar mode a 100pF capacitor may be
placed from pin 11 to ground for added stability.
LOWER RESOLUTION APPLICATIONS
LSB
When less than 6 bits of resolution is required, tie off unused
bits to a voltage level greater than +2.0 volts. The +S volt
logiC supply is usually convenient.
PAGE 10·15
•
PMI
.DAC~02/DAC-03/DAC-05
10-BIT PLUS SIGN
VOLTAGE OUTPUT DlA CONVERTERS
®
FEATURES
• Complete ............. Includes Reference and Op Amp
• Compact ...•............... Single 18-Pln DIP Package
• Bloplar Output ................ Sign/Magnitude Coding
(DAC-03 - Unipolar Only)
• Monotonlclty Guaranteed
• Nonlinearity.................................. ±1 LSB
• Fast ............•................. 2.0jls Settling Time
• Stable .................. Full Scale Tempco 60ppm/oC
• Low Power Consumption ............ 300mW Maximum
• TTL, CMOS Compatible Inputs
• MIL-STD-883 Class B Processing Available on DAC-05
GENERAL DESCRIPTION
preCision voltage reference, current steering logic, current
sources, R-2R resistor network, logic-controlled polarity
switch, and high speed internally-compensated output op
amp. Monotonicity guaranteed over the entire temperature
range is achieved using an untrimmed diffused R-2R resistor
network. The buffered reference input is capable of tracking
over a wide range of voltages, increasing application flexibility. The wide power supply range, low power consumption,
wide logic input compatibility and sign/magnitude coding
assures utility in a wide range of applications including CRT
displays, data acquisition systems, AID converters, servo
positioning controls, and audio digitizing/reconstruction
systems.
The DAC-02 and DAC-OS are complete 10-bit plus sign DlA
converters on a Single 90 x 163 mil monolithic chip. All elements of a complete Sign/magnitude DAC are included -
The DAC-03 is similar in construction to the DAC-02/DAC-DS
except for a unipolar only output. This device is intended for
low cost, limited temperature range applications, with the
same general specifications as its premium counterparts.
ORDERING INFORMATIONt
PIN CONNECTIONS
PACKAGE: 18 PIN HERMETIC DIP
MONOTONICITY
MILITARY
TEMP."
10
9
DAC05AX
DAC05BX
DAC05CX
8
7
COMMERCIAL TEMP
DAC02ACX
DAC02BCX
DAC02CCX
DAC02DDX
DAC03ADX DAC05EX
DAC03BDX DAC05FX
DAC03CDX DAC05GX
DAC03DDX
l8·PIN DIP
(X·Suffix)
• Also available with MIL-STD-883B processing. To order add/883 as asuffix to
the part number.
t All listed parts are available with 160 hour burn-in. See Ordering Information,
Section 2.
SIMPLIFIED SCHEMATIC
_ _- - - - - - - - D I G I T A L L O G I C I N P U T S - - - - - - - - - - ,
BIT 6
SIGN BIT
ANALOG
> __1-+0::;;""'"
PAGE 10-16
DAC-02lDAC-03/DAC-GS 10-BIT PLUS SIGN VOLTAGE OUTPUT DlA CONVERTERS
ABSOLUTE MAXIMUM RATINGS (Note)
Operating Temperature Range
DAC-05A.B.C ........................ -55·C to +125·C
DAC-Q2 and DAC-03. All
DAC-05E.F.G ........................... O·C to +70·C
DICE Junction Temperature (T j ) ••••••• -65·C to +150·C
Storage Temperature Range ...•.••.•... -65·C to + 150· C
V+ Supply to Analog Ground .................. 0 to +18V
V- Supply to Analog Ground ............•.•.. , .. 0 to -18V
Analog Ground to Digital Ground •......•.•••.. 0 to ±0.5V
Logic Inputs to Digital Ground •......•.. -5V to (V + -0.7V)
Internal Reference Output Current ..•••••••••....•• 300pA
Reference Input Voltage ....................... 0 to +10V
Internal Power Dissipation •••••••.••••..•••••...•. 500mW
Lead Soldering Temperature (60 sec) •...•••.......• 300·C
Output Short Circuit Duration ..•................ Indefinite
(Short circuit may be to ground or either supply.)
NOTE: Absolule ratings apply to both DICE and packaged parts unless
otherwise noted.
ELECTRICAL CHARACTERISTICS at Vs =± 15V. 0:5 TA:5 + 70· C for DAC-02. and DAC-05E. F & G. TA =25· C for DAC-03
and -55·C:5 TA :5 +125·C for DAC-05A. B & C. unless otherwise noted.
PARAMETER
SYMBOL CONDITIONS
Monolonlcily
Non-linearity
DAC-02
DAC-03
DAC-OS
AC
BC
CC
DO
AD
BD
CD
DO
AlE
BIF
AC/BC
CC
AD/BD
CD
DO
DO
INL
C/G
MIN
TVP
AlE
BIF
A
ALL
INT REF
Full Scale Tempco
To 112 LSB. 10V Step (Note 4)
ALL
Full Range Oulput
Voltage (Note 1)
VFR+ (SB High)
VFA-(SB Low)
DAC-03+10V
+5V
ALL
ALL
Zero Scale Offset
Vzs
±90
±100
±120
±150
ALL
±30
±40
ppml"C
ppm/oC
ALL
2
~s
+11.5
- 10
+11.5
+5.75
Volts
Volts
Volis
Volts
±1
±1
±5
±5
±10
±10
mV
mV
mV
ALL
±2
±10
mV
ALL
±1
±1
±4
±5
±10
±10
mV
mV
mV
±30
±30
±60
±80
mV
mV
±20
±10
±70
±50
mV
mV
ALL
(Note 2)
VFA + -IVFA-I
(Note 3).
Fijll Range Bipolar Symmetry
ALL
ALL
ALL
AC/BC/CC
DO
N/A
N/A
N/A
N/A
T.. = Min-Max
ALL
ALL
T.. =25°C
ppm/°C
ppm/oC
ppml"C
ppm/oC
±45
ALL
AC/BC/CC
DO
ppm/OC
ppm/oC
±45
±60
ALL
SB High. All olher logic
inputs low. TA = 25°C
±60
B
ALL
ALL
TA = Min or Max
Zero Scale Symmetry
ALL
%FS
%FS
%FS
%FS
%FS
ElF/G
C
ALL
SelllingTime
±0.1
±0.2
±0.3
±0.4
±0.5
±60
DO
ALL
EXT REF
UNITS
Bils
Bils
Bits
Bits
9
8
C/G
AC/BC/CC
MAX
10
+10
-11.5
+10
+5.00
Reference Inpul Bles Currenl
ALL
ALL
ALL
100
nA
Reference Inpullmpedance
ALL
ALL
ALL
200
MO
ALL
ALL
ElF/G
AlBIC
1.5
2.0
VIlAS
ALL
6.7
Volts
Reference Input Slew Rale
SR
ALL
Reference Output Voltage
ALL
NOTES:
1. Reference Output terminal connected directly to Reference Inputterminal.
RL = 2kO. all logic inputs" 2.0V.
2. Zero Scale Symmetry i8 the change in the output voltage produced by
switching the Sign Bit with all logic bits low (Vzs+- Vzs-).
3.
Fyll Scale Bipolar Symmetry is the magnitude of the difference between
VFA+ and I V FA-I.
4. Guaranteed by design.
PAGE 10-17
II
!
I
II)
a::
UI
I-
a::
UI
>
Z
o
CJ
or:
C
DAC-02lDAC-03/DAC-OS 10-BIT PLUS SIGN VOLTAGE OUTPUT DlA CONVERTERS
ELECTRICAL CHARACTERISTICS at Vs =± 15V, O:S TA:S +70 0 C for DAC-02, and DAC-05E, F & G, TA =25 0 C for DAC-03
and -55 0 C :S TA:S +1250 C for DAC-05A, B & C, unless otherwise noted.
PARAMETER
SYMBOL CONDITIONS
Logic Input Current
l,N
Logic Input 0
Logic Input 1
V,NL
V,NH
Positive Supply Current
1+
Negative Supply Current
1-
Each input
-5Vto (V+-0.7)V
DAC-02
DAC-03
ALL
ALL
ALL
ALL
ALL
ALL
DAC-OS
AC/BC/CC
DD
ALL
ALL
ALL
ALL
AC/BC/CC
DD
Vs =±12 to ±18V
PSS
ALL
10UT=0
Power Dissipation
Pd
Output Drive Current
10
AC/BC/CC
DD
N/A
PAGE 10-18
ALL
"A
0.8
Volts
Volts
+10
mA
mA
2.0
+7
UNITS
-9
-10
-9 -11.6
mA
mA
mA
-±0.015 ±0.05
% VFfIIV
ALL
ALL
-±0.015
- ±0.05
±.02
±0.1
±0.1
±.O5
% VFfIIV
% VFfIIV
% VFfIIV
300
350
ALL
ALL
225
225
200
250
mW
mW
mW
mW
ALL
TA =25'C
TA = Min to Max
±10.0
-10 -11.6
ALL
TA = Min to Max
TA =25'C
MAx
+7 +11.6
AC/BC/CC
DD
TVP
±1.0
±1.0
ALL
ALL
Power Supply Sensitivity
MIN
N/A
300
350
mA
DAC-02/DAC-03/DAC-05 10-BIT PLUS SIGN VOLTAGE OUTPUT D/A CONVERTERS
DICE CHARACTERISTICS
1.
2.
3.
4.
5.
8.
7.
8.
9.
10.
11.
12.
13.
14.
15.
18.
17.
18.
BIT l-MSB
BIT2
BIT3
BIT4
BITS
BIT8
BIT7
BIT8
BIT9
BIT 10
DIGITAL GROUND
VANALOG GROUND
ANALOG OUTPUT
REF IN
V+
REF OUT
SIGN BIT
Refer to Section 2 for additional DICE Information.
tBits II & 12 (not normally used)
NOTE: Voltage output range programmable by connecting '( 10V) to analog
outputfor 10 volt range. Jumps from U(SV) to analog outputforSvolt range.
DIE SIZE 0.183 X 0.090 Inch
ELECTRICAL CHARACTERISTICS at
PARAMETER
CONDITIONS
Resolution
(Bits II and 12
Not Normally Used)
Bipolar Output
Unipolar Output
VS= ±15V, 25°C,
and
+10V
DAC-02-N
DAC-02-G
LIMIT
LIMIT
LIMIT
UNITS
13
12
13
12
13
12
Bits MAX
Monotonicity
Nonlinearity
Zero Scale Offset
Sign Bit High, All Other
Inputs Low
Zero Scale Symmetry
± 10V Full Scale
Full Scale Output unless otherwise noted.
DAC-02-GR
9
8
7
Bits MIN
±O.I
±0.2
±0.4
% FS MAX
±IO
±IO
±IO
mVMAX
±5.0
±S.O
±IO
mVMAX
•
'";;:sc
CI
......
N
'i'
U
C
0
Full Scale Bipolar Symmetry
± 10V Full Scale
±60
±60
±60
mVMAX
Power Supply Rejection
Vs =±12Vto±18V
O.OS
O.OS
0.1
%VFs/V MAX
Power Dissipation
10UT= 0
300
300
3S0
mWMAX
Logic Input "0"
0.8
0.8
0.8
VMAX
Logic Input "I"
2.0
2.0
2.0
VMIN
>
Z
±11.S
±IO
±II.S
±'IO
±II.S
±IO
VMAX
VMIN
U
C
Output Voltage Analog
(All Bits High)
VFR + (Sign Bit High)
VFR - (Sign Bit Low)
en
II:
W
III:
W
0
0
TYPICAL ELECTRICAL CHARACTERISTICS at
Vs = ±15V
PARAMETER
SYMBOL CONDITIONS
Full Scale Tempco
TCVFS
Internal Reference
Settling Time (TA = 2S' C)
t,
To ± 112 LSB 10 Volt Step
and +10V Full Scale Output, unless otherwise noted.
DAC-02-N
TYP
Logic Input Current
NOTE:
When ordering DICE in this series, use DAC-02 number. and
grades above.
PAGE 10-19
DAC-02-G
DAC-02-GR
TYP
TYP
UNITS
60
60
90
ppml"C
2.0
2.0
2.0
~s
1.0
1.0
1.0
~A
DAC-02lDAC-03/DAC-II5 10-BIT PLUS SIGN VOLTAGE OUTPUT D/A CONVERTERS
TYPICAL APPLICATIONS
The DAC-02's, DAC-03's and DAC-05's logic input stages
require about 1,.A and are capable of operation with inputs
between -5 volts and V+ less 0.7 vol!. This wide input voltage
range allows direct CMOS interfacing in most applications,
the exception being where the CMOS logic and D/A converter
must use the same positive power supply.
In this special case, a diode should be placed in series with
the CMOS driving device's Voo lead as shown in Figure 1. The
diode limits Vo to V+ less 0.7 volt - since the output from the
CMOS device cannot exceed this value, the DAC's maximum
input voltage rule is satisfied. Summarizing: in all applications, the DAC-02, DAC-03 and DAC-05 require either no
interfacing components, or at most a single inexpensive
diode for full CMOS compatibility.
will be obtained if a low tempco resistor is used or if pot and
resistor tempcos match. Alternatively, a single pot of :S:72kll
may be used.
REFERENCE INPUT BYPASS
Lowest noisea.nd fastest settling operation will be obtained
by bypassing the Reference Input to Analog Ground with a
O.o1,.F disk capacitor.
.
GROUNDING
For optimum noise rejection, separate digital and analog
grounds have been brought ou!. Best results will be obtained
if these grounds are connected together at one pOint only,
preferably near the DAcc02, DAC-03 and DAC-05 package,
so that the large digital currents do not flow through the
analog ground path.
APPLICATIONS INFORMATION
CMOS LOGIC INTERFACE CIRCUIT
v+
LOWER RESOLUTION APPLICATIONS
For applications not requiring full10-bit resolution, unused
logic inputs should be tied to ground.
v-
UNIPOLAR OPERATION
Operation as a 10-bit straight binary converter may be
implemented by permanently tying the Sign Bit to +5V (for
positive Full Scale output) or to ground (for negative Full
Scale output). In the DAC-03 only, Pin 18 unipolar enable is
tied to Pin 17.
VOLTAGE
OUTPUT
INPUTS 0;;;; V+ LESS
0.7 VOLTS
IN4148
POWER SUPPLIES
The DAC-02, DAC-03 and DAC-05 will operate within specifications for power supplies ranging from ± 12V to ± 18V. Power
supplies should be bypassed near the package with a 0.1,.F
disk capacitor.
~--;voo
CMOS DRIVING
DEVICE
CAPACITIVE LOADING
The output operational amplifier provides stable operation
with capacitive loads up to 100pF.
CONNECTION INFORMATION
REFERENCE OUTPUT
For best results, Reference Output current should not exceed
100,.A.
FULL SCALE ADJUSTMENT CIRCUIT
, - - - DIGITAL INPUTS
Msa
USE WITH EXTERNAL REFERENCES
Positive-polarity external reference voltages referred to
Analog Ground may be applied to the Reference Input terminal to improve Full Scale Tempco, to provide tracking to other
system elements, or to slave a number of DAC-02s, DAC-03s
and DAC-05s to the Reference Output of anyone of them.
This reference voltage should be between +5V to +7V for
optimum performance.
~
SIGN *
LSB BIT V+
FULL
~~~~ >0-0""'-+--1--"""
POT
SIGN PLUS MAGNITUDE CODING TABLE
(DAC-02 and DAC-OS)
SIGN BIT MSB
+ FULL RANGE
+ HALF SCALE
ZERO SCALE (+)
FULL SCALE ADJUSTMENT
Full Range output voltage may be trimmed by use of a potentiometer and series resistor as shown; however, best results
ZERO SCALE (-)
-HALF SCALE
-FULL SCALE
PAGE 10-20
LSB
1 1 1 1 1 1 1 1 1
o
o
o
o
o
000 0 0 0 0 0 0
000 0 0 0 0 0 0
000 0 0 0 0 0 0
000 0 0 0 0 0 0
1
1
DAC-04/DAC-06
PMI
TWO'S COMPLEMENT
lO-BIT DlA CONVERTER
FEATURES
•
•
•
•
•
•
•
•
•
Complete ............. Includes Reference and Op Amp
Compact ................... Single 18-Pin DIP Package
Bipolar Output ............. Two's Complement Coding
Monotonicity Guaranteed
Nonlinearity ........... , ...................... ±1 LSB
Fast............................. 1.51's Settling Time
Low Power Consumption ........... 300mW Maximum
TTL, CMOS Compatible Inputs
125°C Tested Dice Available
GENERAL DESCRIPTION
The DAC-04 and DAC-06 are complete 10-Bit Two's Complement D/A Converters on a single 90 x 163 mil monolithic
chip. All elements of a complete bipolar output Two's Com-
plement DAC are included - precision voltage reference,
current steering logic, current sources, R-2R resistor network, bipolar offset circuit and high speed internally compensated output op amp. Monotonicity guaranteed over the
entire O°C to +70° C temperature range is achieved using an
untrimmed diffused R-2R resistor network. The buffered reference input is capable of tracking over a wide range of
voltages, increasing application flexibility. The user may also
easily implement One's Complement, Straight Offset Binary,
or unipolar operation. The ± 12V to ± 18V power supply range,
low power consumption, TTL and CMOS compatibility, wide
logic input compatibility, and adaptable logic coding capability assure utility in a wide range of applications.
PIN CONNECTIONS
ORDERING INFORMATIONt
18
PACKAGE 18 PIN HERMETIC DIP
MONOTONICITY
MILITARY
TEMp·
10
9
8
7
DAC-06BX
DAC-06CX
COMMERCIAL
TEMP
DAC-06EX
DAC-04BCX
DAC-04CCX
DAC-04DDX
DAC-06FX
DAC-06GX
BIT 7
7
BIPOLAR ADJUST
17
REFERENCE OUTPUT
16
POSITIVE POWER SUPPLY
•
II>
15
REFERENCE INPUT
14
ANALOG OUTPUT
13
ANALOG GROUND
12
NEGATIVE POWER SUPPLY
11
DIGITAL GROUND
*
CJ
cc
o
en
• Also available with MIL-STD-883B processing. To order add/883 as asuffix to
the part number.
t All listed partsareavailablewith 160 hour burn-in. See Ordering Information,
Section 2.
a:
w
Ia:
w
>
18-PIN DIP (X-Suffix)
Z
o
CJ
CC
SIMPLIFIED SCHEMATIC
Q
, _ - - - - - - - - DIGITAL LOGIC INPUTS - - - - - - - _ ,
REF
OUTPUT
SIGN
BIT
1
BIT
2
2
BIT
BIT
BIT
BIT
BIT
BIT
BIT
3456789
3
4
5
6
8
9
BIT
10
10
v+
BIPOLAR
ADJUST
18
,.
o-+-...-{
REF
INPUT
,.
0;-1----1
DIGITAL
GNO
~,,~~rtI~~~~~~~~~
ANALOG
OUTPUT
....--o
'4
~-+-
'3
ANALOG GROUND
PAGE 10-21
'2
v-
DAC-04/DAC-06 TWO'S COMPLEMENT 1o-BIT D/A CONVERTERS
ABSOLUTE MAXIMUM RATINGS (Note)
Operating Temperature Range
DAC-OBB,C ..•......•................ -55°C to +125°C
DAC-04B,C,D, DAC-OBE,F,G ............. O°C to +70°C
DICE Junction Temperature (T j ) ••••••• -B5°C'to +150°C
Storage Temperature Range ......•...•. -B5°C to +150°C
V+ Supply to Analog Ground ..............••.. 0 to +18V
V- Supply to Analog Ground ...............•.... 0 to -18V
Analog Ground to Digital Ground .............• 0 to ±0.5V
Logic Inputs to Digital Ground .......... -5V to (V+ -0.7)V
Internal Reference Output Current .....•........... 300!,A
Reference Input Voltage ..••...•.•....•••...... 0 to +10V
Bipolar Offset Input Voltage ......•.•........•.. 0 to +10V
Internal Power Dissipation ..•......••.......•..... 500mW
Lead Soldering Temperature (60 sec) ••..••......••• 300°C
Output Short Circuit Duration .......•........•.. Indefinite
(Short circuit may be to ground or either supply)
NOTE: Ratings apply to both DICE and packaged devices unless otherwise
noted.
ELECTRICAL CHARACTERISTICS at Vs =±15V; -55°C", T A ", +125°C for DAC-OBB & C; and OOG", T A ", +70°C for
DAC-04B, C & D and DAC-OBE, F & G, unless otherwise noted.
PARAMETER
SYMBOL
CONDITIONS
Resolution
DAC-04
DAC-OS
All
All
10
E
B/F
C/G
10
BC
CC
DO
Monotonicity
Nonlinearity
BC
CC
NL
TA = Full Temp
E
B/F
DO
C/G
BC/CC
Full Scale Tampeo
TC vFS
Settling Time
Ts
Unipolar Zero Scale Output
Vzs
Total Internal
Ref Connected
TYP
MAX
UNITS
10
Bits
Bits
Bits
9
Bits
Bits
E
B/F
C/G
TA = 25'C
MIN
±0.1
±0.2
±0.4
%FS
%FS
%FS
±0.1
±0.2
±0.3
±0.4
±0.5
%FS
%FS
%FS
%FS
% FS
B
ElF/G
C
±45
±45
±60
±60
±30
±50
DO
±90
±100
±120
±150
Zero Drift Ext
Ref Applied.
BC/CC
DO
All
To ± 1/2 LSB, 10V Step
BC/CC
DO
All
1.5
2.5
TA -25'C
All
±1
±5
TA = Full Temp
All
±2
±5
±10
Short Pin 18 to
Ground (Note 11
All
ppm/'C
ppm/'C
ppm/'C
ppm/'C
ppm/oC
ppm/'C
"s
"s
mV
mV
mV
% Range
BPOII
Connect Pins 15,17 & 18 (Note 21
All
All
5.0
+2.5
Full Range Output Voltage
V FR
Connect Pin 15 to 17 (Note 21
RL = 2kll
All
All
10
11.5
Reference Input Bias Current
I.
All
All
100
Reference Input Impedance
Z,N
All
All
200
Mil
Reference Input Slew Rate
SR
All
All
1.5
VI"s
Reference Output Voltage
VREF
All
Logic Input Current
liN
6.7
1.0
Logic Input "0"
V 1NL
All
All
Logic Input "1"
V1NH
All
All
Bipolar Offset Voltage
All
All
Each Input
-5V to (V+ -0.7IV
Power Supply Sensitivity
Pss
Vs = ±12 to ±18V
1+
TA = 25'C
I-
TA = 25'C
All
BC/CC
TA = Full Temp
DO
BC/CC
DO
BC,CC
DO
Supply Current
Power Dissipation
Po
All
BC,CC
DO
TA = 25'C
TA
Full Temp
All
V
0.8
"A
"A
V
±0.02
±0.05
V
%FSIV
±0.015
±0.02
+O.ot5
7
7
±0.1
±0.1
All
TA -25'C
V
nA
10
2.0
%FSIV
%FSIV
'IIoFSIV
mA
mA
mA
mA
All
-9
-9
10
11.6
-10
-11.6
All
250
250
300
350
mW
mW
350
mW
All
NOTES:
1.
May be operated in the 0 to +10V unipolar mode by shorting Pin 18 to
Ground.
2. VFR = IVFR+I + I VFR-I and is trimmable to exactly 10V range with the circuit
3.
PAGE 10-22
shown in typical applications.
Bipolar offset voltage is trimmable to exact two's or one's complement
condition with the circuit shown in typical applications.
DAC-04/DAC-06 TWO'S COMPLEMENT 10-BIT DlA CONVERTERS
DICE CHARACTERISTICS (125° C TESTED DICE AVAILABLE)
1.
2.
3.
4.
5.
BIT 1 MSB (SIGN BIT)
BIT2
BIT3
BIT4
BITS
8. BITS
7. BIT7
a. BITa
9. BIT9
10.
11.
12.
13.
14.
15.
16.
17.
18.
BIT 10 LSB
DIGITAL GROUND
VANALOG GROUND
ANALOG OUTPUT
REF IN
V+
REF OUT
BIPOLAR ADJUST
DIE SIZE 0.163 X 0.090 Inch
NOTE:
Voltage Output Range programmable by connecting "(10V) to Analog Output for 10 volt range. Jumper from ··(5V) to Analog Output sets device to 5
volt range.
Refer to Section 2 for additional DICE Information.
t Two additional least significant bits are provided.
ELECTRICAL CHARACTERISTICS at Vs= ±15V, TA = 125°C for DAC-04NT, GT and TA = 25°C for DAC-04N, G, GR,
unless otherwise noted.
PARAMETER
CONDITIONS
Resolution
Bipolar Output
Monotonicity
Nonlinearity
Short Ref Input to Reference
Bipolar Offset Voltage
Output and Bipolar Adjust
Power Supply Rejection
Vs= ±12V to ±18V
DAC-04NT
LIMIT
DAC-04N
LIMIT
12
12
DAC-04GT
LIMIT
DAC-04G
LIMIT
DAC-04GR
LIMIT
UNITS
12
12
12
Bits Min
10
9
±0.2
±0.2
±0.4
±0.2
±0.4
% FS Min
+2.S
-S.O
+2.S
+2.S
-s.o
-s.o
+2.S
-S.O
+2.S
-S.O
V MAX
VMin
0.1
0.1
0.1
0.1
O.IS
%VFsMax
a:
>
Z
Bits Min
350
300
350
300
3S0
mWMax
Logic Input "0"
0.8
0.8
0.8
0.8
0.8
V Max
Logic Input "1"
2.0
2.0
2.0
2.0
2.0
VMin
II.S
10.0
II.S
10.0
II.S
10.0
II.S
10.0
II.S
10.0
VMax
Power Dissipation
10UT= 0
Short Reference Input
Analog Output Voltage
to Reference Output
V Min
NOTE: For 2S' C characteristics of DAC-04NT & GT. see DAC-04N & G
characteristics respectively.
TYPICAL ELECTRICAL CHARACTERISTICS at Vs = ±15V, and ±5V Full Scale Output, unless otherwise noted.
DAC-04NT
TYP
DAC-04N
TYP
DAC-04GT
TYP
±60
±60
±60
DAC-04G
TYP
DAC-04GR
TYP
UNITS
PARAMETER
SYMBOL CONDITIONS
Full Scale TempeD
TCVFS
Internal Reference
ts
To ±1I2 LSB
10 Volt Step
I.S
1.5
I.S
I.S
I.S
p.s
TA =2S'C
1.0
1.0
1.0
1.0
1.0
nA
Settling Time
(TA = 2S'C)
Logic Input Current
•
PAGE 10-23
±60
±90
ppm/'C
til
a:
w
~
w
o
o
~
DAC·04/DAC·06 TWO'S COMPLEMENT 10·BIT D/A CONVERTERS
TYPICAL APPLICATIONS
REFERENCE OUTPUT
ADJUSTNG FOR TWO'S COMPLEMENT CODING
For best results, Reference Output current should not exceed
100"A.
1. Connect Full Scale Adjust and Bipolar Adjust Circuitry as
shown in figure.
2. Turn all bits OFF (V FS-) = 1000000000
3. Adjust Bipolar Pot for VFS at output ............ -S.OOOV
4. Turn all bits ON (V FR +) - 0111111111
5. Adjust Full Scale Pot for desired
VFR+ value ........................•....•...•• +4.990V
6. Check Zero Scale Reading (Vzs) - 0000000000
If this reading is outside desired Vzs range, readjust Bipolar Pot until the output reads O.OOOOV.
TWO'S COMPLEMENT CODING TABLE
LSB
IDEAL
OUTPUT
1
+4.990V
1 1 1 1 1 0
+4.980V
·VFs+-1LSB
VFs+-2LSB
0
+lLSB
0 0 0 0 0 0 0 0 0
+0.010V
Zero
0 0 0 0 0 0 0 0 0 0
1 1 1 1 1 1 1
O.OOOV
-0.010V
VFs-+LSB
0 0 0 0 0 0 0 0 1
-4.990V
VFS-
0 0 0 0 0 0 0 0 0
-S.OOOV
0
1
~ILSB
The DAC-04 and DAC-06 will operate within specifications
for power supplies ranging from±12V to±18V. Power supplies should be bypassed near the package with a 0.1"F disk
capacitor. Chip users should connect the substrate to V-.
GROUNDING
For optimum noise rejection, separate digital and analog
grounds have been brought out. Best results will be obtained
if these grounds are connected together at one point only,
preferably at the DAC-04 and DAC-06 package, so that large
degital currents do not flow through the analog ground path.
CAPACITIVE LOADING
INPUT
MSB
POWER SUPPLIES
The output operational amplifier provides stable operation
with capacitive loads up to 100pF.
FULL SCALE OUTPUT RANGE AND
BIPOLAR OFFSET ADJUSTMENT CIRCUIT
,---OIGITAL INPUTS ~
Msa
LSB
V+
. ADJUSTING FOR ONE'S COMPLEMENT CODING
1. Connect Full Scale Adjust and Bipolar Adjust Circuitry as
shown in above figure.
2. Turn all bits OFF (VFR-) - 1000000000
ANALOG
13
GND···
3. Adjust Bipolar Pot for VFR- at output .......... -S.OOOOV
4. Turn all bits ON (V FR+) - 0111111111
5. Adjust Full Scale Pot for desired
VFR+value .................................. +S.OOOOV
·SEE APPLICATION NOTES FOR DETAILS.
··TIE TO GROUND FOR UNIPOLAR OPERATION •
..··GROUNDING - FOR OPTIMUM NOISE RE·
JECTION, SEPARATE DIGITAL AND ANA·
LOG GROUNDS HAVE BEEN BROUGHT
OUT. BEST RESULTS WILL BE OBTAINED
IF THESE GROUNDS ARE CONNECTED
TOGETHER AT ONE POINT ONLY, PREF·
ERABLY NEAR DAC.(J4 PACKAGE,
THAT THE LARGE DIGITAL CURRENTS
DO NOT FLOW THROUGH THE ANALOG
GROUND PATH.
ONE'S COMPLEMENT CODING TABLE
INPUT
MSB
VFs+-1LSB
VFs+-2LSB
+0
-0
VFs-+2LSB
VFs_+1LSB
LSB
so
IDEAL
OUTPUT
0 1 1
1
+S.OOOV
0 1 1
0
+4.990V
0 0 0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
+O.OOSV
-O.OOSV
0 0 0 0 0 0 0 0 1
-4.990V
0 0 0 0 0 0 0 0 0
-S.OOOV
EXTERNAL ADJUSTMENT NETWORK
Note that two zero states will straddle (± 1/2 LSB) the true zero. Therefore the
DAC will give symmetrical outputs for both positive and negative full scale.
Full Scale Output Range and Bipolar Offset may be adjusted
by using the circuit shown in the figure above. Best results
will be obtained when low tempco pots and resistors are
used, or if pot and resistor tempcos match.
PAGE 10-24
DAC-04/DAC-06 TWO'S COMPLEMENT 10-BIT D/A CONVERTERS
IMPLEMENTING
allows direct CMOS interfacing in most applications, the
exception being where the CMOS logic and D/A converter
must use the same positive power supply.
Offset Binary coding is exactly the same as Two's Complement coding except that the most significant bit occurs in
true, rather than inverted form and the output states are
relabeled. To convert the DAC-04 and DAC-06 to Offset
Binary code operation, simply place a logic inverter in series
with the MSB input (Pin 1) and invert the MSB value shown in
steps 2, 4 and 6 of the Two's Complement adjustment procedure shown above.
In this special case, a diode should be placed in series with
the CMOS driving device's Voo lead as shown in Figure 1. The
diode limits Vo to V+ less 0.7 volt - since the output from the
CMOS device cannot exceed this value, the DAC's maximum
input voltage rule is satisfied. Summarizing: in all applications, the DAC-06 requires either no interfacing components,
or at most a single inexpensive diode for full CMOS
compatibility.
TYPICAL APPLICATIONS
OFFSET BINARY CODING TABLE
CMOS LOGIC INTERFACE CIRCUIT
INPUT
MSB
LSB
IDEAL
OUTPUT
1 1
ZERO
0 0 0 0 0 0 0 0 0
1 1 1 1
0
V-
V+
+4.990V
VFs+-1LSB
VFs+-2LSB
+4.980V
0.00
VOLTAGE
OUTPUT
ZERO
1LSB
0
-0.005V
VFS-+1LSB
0 0 0 0 0 0 (j 0 0
-4.990V
VFS-
0 0 0 0 0 0 0 0 0 0
-5.000V
INPUTS ",V+ LESS
0.7 VOLTS
IN4148
L-----1VDD
CMOS DRIVING
DEVICE
Vss
INTERFACING WITH CMOS LOGIC
The DAC-04 and DAC-06 logic input stages require about
1,.A and are capable of operation with inputs between -5
volts and V+ less 0.7 volt. This wide input voltage range
UI
!
cQ
II)
a:
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a:
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z
I-
ou
c
C
PAGE 10-25
DAC-OB
PMI
8-BIT HIGH-SPEED MULTIPLYING
utA CONVERTER
®
UNIVERSAL DIGITAL LOGIC INTERFACE
FEATURES
•
•
•
•
•
•
•
•
•
•
•
popular logic families with full noise immunity is provided
by the high swing, adjustable threshold logic inputs.
Fast Settling Output Current. . . . . . . . . . . . . . . . . .. 8Sns
Full Scale Current Prematched to ± 1 LSB
Direct Interface to TTL, CMOS, ECL, HTL, PMOS
Nonlinearity to ±O.1% Maximum Over
Temperature Range
High Output Impedance and
Compliance ........................ -10Vto +18V
Differential Current Outputs
Wide Range Multiplying Capability. .. 1MHz Bandwidth
Low FSCurrent Drift ................... ±10ppm/·C
Wide Power Supply Range ............ ±4.SVto ±18V
Low Power Consumption. . . . . . . . . . . . .. 33mW @ ± SV
Low Cost
GENERAL DESCRIPTION
The DAC·08 series of a·bit monolithic Digital-to-Analog Converters provide very high-speed performance coupled with
low cost and outstanding applications flexibility.
Advanced circuit design achieves 85n5 settling times with
very low "glitch" and at low power consumption. Monotonic
multiplying performance is attained over a wide 40 to 1
reference current range. Matching to within 1 L5B between
reference and full scale currents eliminates the need for full
scale trimming in most applications. Direct interface to all
High-voltage compliance dual-complementary current outputs are provided, increasing versatility and enabling differential operation to effectively double the peak-to-peak
output swing. In many applications, the outputs can be
direclly converted to voltage without the need for an external op amp.
All DAC-08 series models guarantee full 8-bit monotonicity,
and nonlinearities as tight as ±0.1 % over the entire
operating temperature range are available. Device performance is essentially unchanged over the ±4.5 to ±18V
power supply range, with 33mW power consumption attainable at ±5V supplies.
The compact size and low power consumption make the
DAC-08 attractive for portable and military/aerospace applications; devices processed to MIL-5TD-883, Level Bare
available.
DAC-08 applications include 8-bit, 11'5 AID converters, servo
motor and pen drivers, waveform generators, audio encoders and attenuators, analog meter drivers, programmable power supplies, CRT display drivers, high-speed
modems and other applications where low cost, high speed
and complete input/output versatility are required.
EQUIVALENT CIRCUIT
VREF 1+)o-"'4'-t-~-t_ _...,
16
COMP
3
v-
PAGE 10-26
DAC·OB B·BIT HIGH·SPEED MULTIPLYING D/A CONVERTER
ABSOLUTE MAXIMUM RATINGS
v+
Operating Temperature
-55"C to + 125"C
DAC·08AO, Q .
.. O"C to + 70"
DAC·08HO, EO, CO .
DICE Junction Temperature (Ti)
-65°C to +150°C
Storage Temperature. . . . . . . . . . .
-65"C to 150"C
Power Dissipation· .......................... 500mW
Derate above 100"C ...................... 10mW/"C
Lead Soldering Temperature (60 sec.) ............ 300"C
Supply to V - Supply ........................ 36V
Logic Inputs. . . . . . . . . . . . . . . . . . . . .. V - to V - plus 36V
VLC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V~ to V+
Analog Current Outputs (at Vs- = 15V) ........... 4.25mA
Reference Inputs (V ,4 to V,5) ... . . . . . .
V - to V +
Reference Input Differential Voltage
(V ,4 to V,5 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 18V
Reference Input Current (1 ,4)
5.0mA
·Over full operating range
NOTE: Absolute ratings apply to both DICE and packaged parts unless
otherwise noted.
ELECTRICAL CHARACTERISTICS
at Vs = ±15V, IREF =2.0mA, TA =O"C to + 70"C unless otherwise noted. Output characteristics
refer to both lOUT and lOUT'
DAC-08/E
DAC-OBA/H
SYMBOL
PARAMETER
MIN
CONDITIONS
TYP
MAX
MIN
TYP
DAC·OBC
MAX
MIN
TYP
MAX
UNITS
Bits
ResolutIon
----
Bits
Monotonicity
Nonlinearity
Settling Time
TA=OGC to 70·C
±O.19
±O.1
.. _ - - - - - - ' - ' - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - To ± 1/2 LSB, all bits switched
150
85
85
150
85
135
ON or OFF, TA =25'C (See Note)
Propagation Delay
Each bit
All bits switched
TA =25°C
(See Note)
35
35
Full Scale Tempeo
±10
60
60
35
35
60
60
35
35
60
60
±50
±10
±80
±50
±10
±BO
DAC-08E
%FS
ppml"C
•
---------.-.------------------~-----------------
Output Voltag~ Compliance V
(True Compliance)
OC
FuIJ scale current change
< % LSB, RO UT>20MIl typical
-10
+18
-10
+18
-18
-10
Volts
Full Range Current
Full Range Symmetry
IFR4
_
Zero Scale Current
1.984
R 14 , R15 == 5.000kll
TA==+25°C
IZS
0.1
=
Output Current Range
Logic Input Levels
Logic "0"
Logic Input "I"
1.94
1.99
1.0
0.2
2.04
1.94
IlL
IIH
Logic Input Swing
VIS
V- = -15V
±15V
Logic Threshold Range _ _V_,_T"H"R_ _VS==
..::.._
_
1.99
2.1
2.1
4.2
4.2
4.2
2.04
mA
Reference Input Slew Rate
dlldt
REQ",200n
RL = 10011
Cc = OpF
PSSIFS +
V+ =4.5V to lBV
V- = -4.5V to -18V
See fast pulsed
ref. info.
following.
IREF=1.0mA
VS= +5V, -15V, IREF=2.0mA
11+
Vs = ± 15V, IREF =2.0mA
1Power Dissipation
±5V,IREF=1.0mA
+5V, -5V, IREF=2.0mA
± 15V, IREF == 2.0mA
4.0
IIA
mA
-2.0
0.002
-10
10
0.8
2.0
-2.0
0.002
-2.0
0.002
-10
10
Volts
-10
10
-10
+18
-10
+18
-10
+18
Volts
-10
+13.5
-10
+13.5
-10
+13.5
Volts
4.0
-
-3.0
8.0
-1.0
4.0
-
4.0
8.0
±0.0003
±O.Ol
±0.OO03
±0.01
±0.002
±0.01
±0.002
±0.01
2.3
3.B
-4.3
-5.B
2.4
-6.4
2.5
-6.5
3.B
-7.8
3.8
-7.8
2.3
-4.3
2.4
-6.4
2.5
-6.5
33
108
135
48
136
174
33
103
135
NOTE: Guaranteed by design.
PAGE 10-27
-1.0
-3.0
-
-3.0
8.0
±0.0003
±0.01
%h.tol%h.V+
± 0.002
± 0.01
%h.IO/%h.V-
3.8
2.3
3.8
-5.8
-4.3
3.8
- 7.8
-5.B
3.8
-7.8
2.4
-6.4
2.5
6.5
-7.8
3.8
7.8
48
136
174
33
108
135
48
136
174
3.8
~
o
III
a:
w
a:
W
>
I-
Z
0.8
2.0
-1.0
115
1+
11+
0.2
-------------------------------------------------
Reference Bias Current
PSSIFS _
2.0
2.1
0.8
VLC=OV
VIN= -10V to +O.8V
VIN = 2.0V to 18V
Power Supply Current
2.000
2.0
Logic Input Current
Logic "0"
Logic Input "1"
Power Supply Sensitivity
1.992
_'_IFc.R~S_ __'IF_'_R'_'4_-__"F_'_R=2_ _ _ _ _ _ _ _ _ _±_0_.5_ _±_4_.0_ _ _ _ _ _ _±_'_.0_ _±_8_.0_ _ _ _ _ _ _ _
±_2._0_±_'6_.0
_ _ _ _ _ "A
R 14, R15 == 5.000kn
VREF== +15.0V, V-10V
VREF== +25.0V, V-:::: -12V
CD
C
o
VREF == 10.000V
mA
mW
o
o
~
o
DAC·08 8·BIT HIGH·SPEED MULTIPLYING D/A CONVERTER
DICE CHARACTERISTICS (125° C
TESTED DICE AVAILABLE)
1. VLe
2. lOUr
9. BITS
10. BITa
3. V4. lOUT
5. BIT 1 (MSB)
11. BIT 7
12. BIT 8 (LSB)
13. v+
14. VA.F (+)
15. VA.F (-)
a. BIT2
7. BIT3
8. BIT4
16. COMP
DIE SIZE 0.085 X 0.082 Inch
ELECTRICAL CHARACTERISTICS
Refer to Section 2 for additional
DICE Information.
at Vs =±15V, TA = 125°C for DAC-OBNT, GT and TA = 25°C for DAC-OBN, G, GR,
IREF = 2.0mA, unless otherwise noted. Output characteristics apply to both lOUT and lOOT'
PARAMETER
SYMBOL CONDITIONS
DAC·08NT
LIMIT
DAC-08N
LIMIT
8
8
8
±0.1
±0.1
±0.19
Full Scale Current
Change < 112 LSB
+18
-10
+18
-10
Full Scale Current
'FS4 or
'FS2
VAEF = 10.000V
R'4' R,. = 5.000kn
2.04
1.94
Full Scale Symmetry
'FSS
Zero Scale Current
I zs
I FS1 0r
Output Current Range
'FS2
V-=-5.0V.
VAEF =+15V
V-=-7.0V.
V REF =+25V
R'4' R,. = 5.000kn
8
DAC·08GR
LIMIT
UNITS
8
Bits MIN
±0.19
±0.39
Bits MIN
+18
-10
+18
-10
+18
-10
Volts MAX
Volts MIN
2.04
1.94
2.04
1.94
2.04
1.94
2.04
1.94
mAMAX
mAMIN
±8.0
±8.0
±8.0
±8.0
±16
nAMAX
2.0
2.0
4.0
4.0
4.0
nAMAX
2.1
2.1
2.1
2.1
2.1
mAMAX
4.2
4.2
4.2
4.2
4.2
mAMAX
8
Monotonicity
Nonlinearity
Vac
DAC-08G
LIMIT
8
Resolution
Output Voltage
Compliance
DAC-08GT
LIMIT
Bits MIN
Logic Input "0"
VIL
0.8
0.8
0.8
0.8
0.8
V MAX
Logic Input "1"
V IH
2.0
2.0
2.0
2.0
2.0
VMIN
±10
±10
±10
±10
±10
±10
±10
±10
±10
±10
~AMAX
+18
-10
+18
-10
+18
-10
+18
-10
+18
-10
V MAX
VMIN
3.0
3.0
3.0
3.0
3.0
~AMAX
0.01
0.01
0.01
0.01
0.01
%FS/%V MAX
Vs =±15V
IAEF $2.0mA
3.8
-7.8
3.8
-7.8
3.8
-7.8
3.8
-7.8
3.8
-7.8
mAMAX
V s =±15V
I REF ,,2.0mA
174
174
174
174
174
mWMAX
Logic Input Current
Logic "0"
Logic "1"
VIL
IIH
VLC=OV
VIN = -10V to +0.8V
VIN = 2.0V to 18V
Logic Input Swing
VIS
V-=-15V
Reference Bias
Current
I,.
Power Supply
Sensitivity
Power Supply Current
Power Dissipation
PSSI FS +
PSSI FS1+
Pd
V+ = 4.5V to 18V
V- = -4.5V to -18V
IREF= 1.0mA
ELECTRICAL CHARACTERISTICS at V s =± 15V, and IREF= 2.0mA, unless otherwise noted. Output characteristics apply
to both IOUTand lOUT'
PARAMETER
SYMBOL
Reference Input
Slew Rate
dl/dt
Propagation Delay
t pLH , tpHL
ts
Settling Time
ALL GRADES
TYPICAL
CONDITIONS
UNITS
8.0
mAins
TA = 25°C. Any Bit
35
ns
To ±1/2 LSB. All Bits
Switched ON or OFF,
TA = 25°C
85
ns
NOTE:
For DAC08NT & GT 25° C characteristics. see DAC08N & G characteristics
respectively.
PAGE 10-28
DAC·08 8·BIT HIGH·SPEED MULTIPLYING D/A CONVERTER
ORDERING INFORMATIONt ..
DUAL INLINE PACKAGE
HERMETIC
16 PIN
NL
DACOBAQ·
DACOBHQ
DACOBQ·
0.1%
0.1%
DACOBEY
DACOBCQ
0.39%
PLASTIC
18 PIN
PIN CONNECTION
OPERATING
TEMPERATURE
RANGE
VLe
MIL
COM
MIL
COM
COM
DACOBHP
DAC08EP
DACOBCP
* Also available with MIL-STD-8838 Processing. To order add 1883 as a suffix
to the part number.
tAil listed parts areavailable with 160 hour burn-in. See Ordering Information,
Section 2.
··See JM3B510/1130t/11302, this section, for JAN qualified DAC-OB.
PULSED REFERENCE OPERATION
16·PIN DUAL·IN·L1NE
FAST PULSED
REFERENCE OPERATION
'I: +VREF
l
IOPTIONAL RESISTOR
~ RREF FOR OFFSET INPUTS
RIN
1
ovJL
TYPICAL VALUES:
RIN = 5k
+VIN = 10V
REa'" 200n
RL '" 100n
200NSEC/DIVISION
Cc = 0
~
~
II)
a:
TRUE AND COMPLEMENTARY
OUTPUT OPERATION
LSB SWITCHING
FULL SCALE SETTLING TIME
ALL BITS SWITCHED ON
III
I-
a:
III
>
Z
oU
2.4V-
4(
a
D.4V-
ov-
"""0-
5ONSEC/DIVISION
SETTLING TIME FIXTURE
IFS ., 2mA, RL '" lkO
1/2LSB" 4/.IA
PAGE 10·2£
SUNSEC/DIVISION
DAC·oB 8-81T HIGH·SPEED MULTIPLYING D/A CONVERTER
TYPICAL PERFORMANCE CURVES
LSB PROPAGATION
DELAY vs IFS
FULL SCALE CURRENT vs
REFERENCE CURRENT
5.D
REFERENCE INPUT
FREQUENCY RESPONSE
lD
BOD
LIMIT FOR
ALL BITS "HIGH"
R'4- R'S-1kn
RL"' 5OO.n
V
1...
"I!:
1/
1/ -51
1LS" • 8; 1111
I--
12.•
ffi
v-= -15V
G 2.0
~
I
I
ALL
0.06
0.02
0.1
0.5
2.0
10
0.01
0.05
0.2
1.0
5.0
If5. OUTPUT fULL SCALE CURRENT (mAl
6.D
I
-10
-6
-2
6
10
VTH
-
...........
-12.0 -8.0 -4.0
4.0
8.0 12.0
LOBIC INPUT VOLTAGE {VI
-60
16.0
OUTPUT VOLTAGE
COMPLIANCE vs TEMPERATURE
1.8
+24.0
1.8
+20.0
+16.0
1',2
+12.0
~
fA = TMIN TO TMAX
3.2
~
1 2•8
w
;: 2.4
I
"5(,) 1.6
V-" -5V
II
~ 1.2
00.8
'REF = 2mA
I
I~EF .1'mA
~...
~
1.4
1.0
IR~F
D.4
o
+50
+100
TEMPERATURE·loCI
+160
~I~~~E g~::A:HT:Egp~A'=:~N~E~~~~::T~:~
RANGj IVLC = o.OVI.
1
IREf '" 2.0mA
-+.....4-_.j..:".;.'4-_01-1
~~8~-4---+--~~~-4--~--~
.....D
~
0
-4.D
O!:!mA
r--...
NOTE: B1 THROUGH B8 HAVE IDENTICAL TRANSFER
CHARACTERISTICS. BITS ARE FULLY SWITCHED, WITH
LESS THAN 1/2 LSB ERROR, AT LESS THAN ±100mV
FROM ACTUAL THRESHOLD. THESE SWITCHING
a:
+8.0
0.6
00.4
I
...........
BIT TRANSFER
CHARACTERISTICS
+28.0
ALL BITS ON
3 .•
v-"" -15V
~
D.4
l
18
10
6.0
VLC vs TEMPERATURE
:t' 0.8
I
OUTPUT CURRENT vs
OUTPUT VOLTAGE
(OUTPUT VOLTAGE COMPLIANCE)
I
0.5
1.0
2.0
fREQUENCY IMHz)
:I:
,
V1S. REFERENCE ,?OMMON MODE VOL rAGE (VI
4.D
0.2
I
~mA
14
0.1
~ 1.2
IREF - D'~lmA
~ 2.0
\
CENTERED AT +200mV
SMALL SIGNAL
~
I I
IREF -'
D.4
~
nov
2. Cc '" 16pF. VIN = 60mYp-p
1.6
'REF" 2mA
I
-14
15pF, VIN = 2.OVp-p
LARGE
2.D
10.0
"'TS ON
V+" +15V
V-"'-5.V
6 ' .2
D.8
r\,
LARG.E SIGNAL
LOGIC INPUT CURRENT vs
INPUT VOLTAGE
I I
I I
I
1.6
Cc"
CENTERED AT
-12
NO~E:
PrislTlvk COJMON ~ODEI_
RANGE IS ALWAYS (V+) -1.6V
I
2.4
a:
a:
I
fA = TMIN TO TMAX
3.6
1.
1\
-14
1.0
2.0
3.0
4.0
IREF. REFERENCE CURRENT {mAl
I
3.2
....
-lD
REFERENCE AMP
COMMON MODE RANGE
4.D
r-..
-2
~a:
1\
,
,,\2
D
~
lLSB"' 7.8,uA
v- =
V
ALL BITS "ON"
VR16" OV
2
<:-4
-
LIMIT FOR
1.D
TT
V-)'6V
T A = TMIN TO TMAX
t=t=tjl±::t:":2j:f--::jj
"".D
-12.0
-14 -10
-6
-2
lD
OUTPUT VOLTAGE (VI
14
18
-60
+50
+100
TEMPERATURE (OCI
PAGE 10-30
+160
-12.0 -B.O
-4.0
4.0
8.0 12.0
LOOIC INPUT VOLTAGE IV)
16.0
DAC·08 8·BIT HIGH·SPEED MULTIPLYING D/A CONVERTER
TYPICAL PERFORMANCE CURVES
...
POWER SUPPLY CURRENT vs V+
10..
...
AL~ B','. "H:OH"[OR \~.
,-
i ...
I--
B'~S Mlv B~ "HI~H"~R +W.;
~ 1.•
11
il
1-
.....
1••
a:
o
~ITH \REFI .. 21-
Ci
a:
§
7,0
r- r-- vJ. -15V
:=i
II:
&,0
u
8.0
a:
1- WITH 'REF'" O.2mA _
L..
2.0 4.0 6.0 aD 10.0 12.0 14.0 16.0 18.0 20.0
V+, POSITIVE POWER SUPPLY (Vdc)
A~L BITS "~'OH"
~ 4.0
a.
•o
..•
i... 8..
1-JITH I'REJ .. ,JA
~ aD
12
1 I'+r I
I I I I
1••
•
tt
10.0
8.0
~ 4..
,+ - I -
POWER SUPPLY CURRENT
vs TEMPERATURE
POWER SUPPLY CURRENT VI V-
10.0
2..
1.•
T
I
+--
1--
-
1+-
r-
'REF" 2.OmA
I
r- r---- v+ ~
I
I
+16V
f--
o
-4.0
-8.0
-12.0
-16.0
-20.0
-2.0
-8.0
-10,0
-14.0
-1B.O
V-, NEGATIVE POWER SUPPl V tVdc)
BASIC CONNECTIONS
OR ["LOW"
-t5O
+100
TEMPERATURE (OC)
+160
BASIC POSITIVE REFERENCE OPERATION
ACCOMODATING BIPOLAR REFERENCES
MBa
LSB
81 B2 B3 84 B6 Be 87 B8
+VREF
RREF
liN
~
RREF
IR141
~IREF
R15
,.
VREF(-)
RIN
15
'REF
RREF"" R15
~
;;to
VREF .. +10.00llV
RREF .. S.OOOk
R15" RREF
Cc = O.01~F
VLC .. OV (GROUNO)
PEAK NEGATIVE SWING OF liN
+VREF RREF
"
Rl.
(OPTIONAL)
,.
VIN~_
HIGH INPUT
IMPEDANCE
IFR'~
10
+ iQ=
v-
-It
V+
VLC
IFR FOR
ALL LOGIC STATES
+VREF MUST BE ABOVE PEAK POSITIVE SWING OF VIN
BASIC UNIPOLAR NEGATIVE OPERATION
MSB
LBB
81 B2 B3 B4 B5 B6 87 B8
B1
EO
B2 B3 B4 B5 B6 B7 B8
1
FULL RANGE
HALF SCALE
IREF ..
2.000mA
+ LSB
HALF SCALE
1.
i0
2
0
0
0
0
0
0
0
0
0
0
0
0
0
lomA
lomA
Eo
Eo
1.992
.000
-9.960
- .000
1.006
.984
-5.040
-4.920
1.000
.992
-5.000
-4.980
.992
1.000
-4.960
-5.000
HALF SCALE -LSB
0
+ LSB
0
0
0
0
0
0
0
.006
1.984
- .040
-9.920
0
0
0
0
0
0
0
.000
1.992
.000
-9.960
ZERO SCALE
PAGE 10-31
DAC·08 8-81T HIGH·SPEED MULTIPLYING DlA CONVERTER
BASIC CONNECTIONS
BASIC BIPOLAR OUTPUT OPERATION
B1 B2 B3 B4 B5 B8 B7 B8
POS FULL RANGE
MSB
LSB
POS FULL RANGE -LSB
81 B2 83 04 B5 8& 87 B8
10.000kn
IREFI+)"
2.000mA
1.
i0
2
RECOMMENDED FULL SCALE ADJUSTMENT CIRCUIT
...."
ZERO SCALE +LSB
Eo
Eo
1
-9.920 + 10.000
1
1
0
-9.840 + 9.920
0
0
0
0
0
0
1
-0.080 + 0.160
0
0
0
0
0
0
0
ZERO SCALE
1
ZERO SCALE - LSB
0
0.000 + 0.060
NEG FULL SCALE + LSB
0
0
0
0
0
0
0
+9.920 - 9.840
NEG FULL SCALE
0
0
0
0
0
0
0
0 + 10.000 - 9.920
1
+0.060
0.000
BASIC NEGATIVE REFERENCE OPERATION
LOWT.C.
VREF
+1OV
an
-
RREF
_l14
r----~""'---I1.
IAEF(+) ... 2mA
APp~OX
..U
POT
.".
":" -VREF
R15
,.
~1V
1111dl
,.
NOTE. RREF SETS IFS: Fl15 IS FOR
BIAS CURRENT CANCELLATION•
•
OFFSET BINARY OPERATION
lOkI}
MSB
B1 8283 B485 S6B7
LSB
as
...."
Bl B2 B3 B4 B5 B8 B7 B8
POS FULL RANGE
ZERO SCALE
.".
.".
+15V -15V
Eo
+4.960
0
0
0
0
0
0
0
0.00
NEG FULL SCALE +1 LSB
0
0
0
0
0
0
0
1
-4.960
NEG FULL SCALE
0
0
0
0
0
0
0
0
-5.000
-16V
PAGE 10·32
DAc·oa a·BIT HIGH·SPEED MULTIPLYING D/A CONVERTER
BASIC CONNECTIONS
POSITIVE LOW IMPEDANCE OUTPUT OPERATION
NEGATIVE LOW IMPEDANCE OUTPUT OPERATION
RL
IFR"
RL
IFR"~
~
'REF
IREF
FOR COMPLEMENTARV OUTPUT (OPERATION AS A NEGATIVE LOGIC DACI,
CONNECT INVERTING INPUT OF OP·AMP TO iQ (PIN 21: CONNECT 10 (PIN 41
TO GROUND.
FOR COMPLEMENTARY OUTPUT (OPERATION AS A NEGATIVE LOGIC DAel.
(PIN 21; CONNECT 10 (PIN
CONNECT NON·INVERTING INPUT OF OP-AMP TO
10
41 TO GROuND.
INTERFACING WITH VARIOUS LOGIC FAMILIES
CMOS, PMOS/NMOS
ECl
V+
TTL
VTH = +1,4V
VTH = VLC +1.4V
+15V CMOS
\lTH - +7.6V
II
+15V
9.1kU
~
VLe
TO PIN 1
TO PIN 1
VLe
VLe
R3
..."...
~
-6.2V
":"
TEMPERATURE COMPENSATING VLC CIRCUITS
~
(I)
II:
1&1
...
II:
1&1
>
Z
o
U
~
APPLICATIONS INFORMATION
REFERENCE AMPLIFIER SETUP
The DAC·08 is a multiplying D/A converter in which the out·
put current is the product of a digital number and the input
reference current. The reference current may be fixed or
may vary from nearly zero to +4.0mA. The full scale output
current Is a linear function of the reference current and is
given by:
255
IFR =--X IREF where IREF = 114,
256
In positive reference applications, an external positive
reference voltage forces current through R14 into the VREF(+)
terminal (pin 14) of the reference amplifier. Alternatively, a
negative reference may be applied to VREF(-) at pin 15;
reference current flows from ground through R14 into VREF(+)
as in the positive reference case. This negative reference
connection has the advantage of a very high impedance
presented at pin 15. The voltage at pin 14 is equal to and
tracks the voltage at pin 15 due to the high gain of the inter·
nal reference amplifier. R 15 (nominally equal to R 14) is used
to cancel bias current errors; R 15 may be eliminated with only
a minor increase in error.
Bipolar references may be accomodated by offsetting VREF
or pin 15. The negative common mode range. of the ref·
erence amplifier is given by: VCM - = V - plus (lREF x 1kll) plus
2.5V. The positive common mode range Is V+ less 1.5V.
When a DC reference is used, a reference bypass capacitor
is recommended. A 5.0V TTL logic supply is not recommended
as a reference. If a regulated power supply is used as a
reference, R14 should be split into two resistors with the
junction bypassed to ground with a O.1"F capaCitor.
For most applications the tight relationship between IREF
and IFS will eliminate the need for trimming IREF' If reo
quired, full scale trimming may be accomplished by
adjusting the value of R14 , or by using a potentiometer for
R14' An improved method of full scale trimming which
PAGE 10-33
DAC-08 8-BIT HIGH·SPEED MULTIPLYING D/A CONVERTER
eliminates potentiometer T.C. effects is shown In the
recommended full scale adjustment circuit.
Using lower values of reference current reduces negative
power supply currenl and increases reference amplifier
negative common mode range. The recommended range for
operation with a DC reference current is +0.2mA to
+4.0mA.
REFERENCE AMPLIFIER COMPENSATION FOR
MULTIPLYING APPLICATIONS
AC reference applications will require the reference
ampllfer to be compensated using a capacitor from pin 16 to
V -. The value of this capacitor depends on the the im·
pedance presented to pin 14: for R14 values of 1.0, 2.5 and
5.0kO, minimum values of Cc are 15, 37, and 75pF. Larger
values of R14 require proportionately increased values of Cc
for proper phase margin.
For fastest response to a pulse, low values of R14 enabling
small Cc values should be used. If pin 14 Is driven by a high
impedance such as a transistor current source, none of the
above values will suffice and the amplifier must be heavily
compensated which will decrease overall bandwidth and
slew rate. For R14 = 1kO and Cc = 15pF, the reference
amplifier slews at 4mAl,.s enabling a transition from IREF = 0
to IREF = 2mA In 500ns.
Operation with pulse inputs to the reference amplifier may
be accomodated by an alternate compensation scheme.
This technique provides lowest full scale transition times.
An internal clamp allows quick recovery of the reference
amplifier from a cutoff (IREF = 0) condition. Full scale transition (0 to 2mA) occurs in 120ns when the equivalent impedance at pin 14 is 2000 and Cc = O. This yields a reference
slew rate of 16mA/,.s which is relatively independent of RIN
and VIN values.
LOGIC INPUTS
The DAC-OB design incorporates a unique logic input circuit
which enables direct Interface to all popular logic families
and provides maximum noise immunity. This feature is
made possible by the large input swing capability, 2pA logic
input current and completely adjustable logic threshold
voltage. For V- = -15V, the logiC Inputs may swing between -10V and +1BV. This enables direct interface with
+ 15V CMOS logiC, even when the DAC-OO is powered from a
+5V supply. Minimum input logic swing and minimum logic
threshold voltage are given by: V- plus (lREF x 1kO) plus
2.5V. The logic threshold may be adjusted over a wide range
by placing an appropriate voltage at the logic threshold control pin'(pin 1, VLcl. The appropriate graph shows the relationship between VLC and VTH over the temperature range,
with VTH nominally 1.4 above VLC. For TTL and DTL interface, simply ground pin 1.. When interfacing ECl, an
IREF = 1mA Is recommended. For interfacing other logic
families, see previous page. For general setup of the logic
control circuit, it should be noted that pin 1 will source
100pA typical; external circuitry should be designed to accomodate this current.
Fastest settling times are obtained when pin 1 sees a low
impedance. If pin 1 is connected to a 1kO divider, for example, it should be bypassed to. ground by a O.D1J.1F capacitor.
ANALOG OUTPUT CURRENTS
Both true and complemented output sink currents are provided where 10 + TO = IFS' Current appears at the "true" output when a "1" Is applied to each logic Input. As the binary
count Increases, the sink current at pin 4 increases proportionally, in the fashion of a "positive logic" D/A converter.
When a "0" Is applied to any input bit, that current is turned
off at pin 4 and turned on at pin 2. A decreaSing logic count
increases 10 as in a negative or inverted logic D/A converter.
Both outputs may be used simultaneously. If one of the outputs is not required it must still be connected to ground or
to a point capable of sourcing IFs; do not leave an unused
output pin open.
Both outputs have an extremely wide voltage compliance
enabling fast direct current·to-voltage conversion through a
resistor tied to ground or other voltage source. Positive
compliance is 36V above V- and is Independent of the
positive supply. Negative compliance is given by V - plus
(lREF x 1kO) plus 2.5V.
The dual outputs enable double the usual peak-Io-peak load
swing when driving loads in quasi-differential fashion. This
feature Is especially useful In cable driving, CRT deflection
and in other balanced applications such as driving centertapped coils and transformers.
POWER SUPPLIES
The DAC-OB operates over a wide range of power supply
voltages from a total supply of 9V to 36V. When operating at
supplies of ±5V or less, IREF s1mA is recommended. low
reference current operation decreases power consumption
and increases negative compliance, reference amplifer
negative common mode range, negative logic input range,
and negative logic threshold range; consult the various
figllres for guidance. For example, operation at -4.5V with
IREF = 2mA is not recommended because negative Olltput
compliance would be reduced to near zero. Operation from
lower supplies is possible, however at least BV total must be
aplled to insure turn-on of the internal bias network.
Symetrical supplies are not required, as the DAC-OB is quite
insensitive to variations in supply voltage. Battery operation
is feaSible as no ground cormectlonls required: however, an
artificial ground may be used to insure logic swings, etc. remain between acceptable limits.
Power consumption may be calculated as follows:
Pd=(1 +) (V +)+(I-)(V -)+(2 IREF)(V-). A useful feature of
the DAC-OB design is that supply current is constant and In·
dependent of input logic states; this is useful in cryptographic applications and further serves to reduce the size
of the power supply bypass capaCitors.
PAGE 10·34
DAC·08 8·BIT HIGH·SPEED MULTIPLYING D/A CONVERTER
TEMPERATURE PERFORMANCE
The nonlinearity and monotonicity specifications of the
DAC-08 are guaranteed to apply over the entire rated
operating temperature range. Full scale output current drift
Is tight, typically:!: 10ppm/ DC, with zero scale output current
and drift essentially negligible compared to 1/2 LSB.
The temperature coefficient of the reference resistor R14
should match and track that of the output resistor for
minimum overall full scale drift. Settling times of the
DAC·08 decrease approximately 10% at -55 DC; at
+125 DC an increase of about 15% is typical.
The reference amplifier must be compensated by using a
capacitor from pin 16 to V-. For fixed reference operation,
a 0.011'F capacitor is recommended. For variable reference
applications, see section entitled "Reference Amplifer Com·
pensation for Multiplying Applications".
MULTIPLYING OPERATION
The DAC-08 provides excellent multiplying performance
with an extremely linear relationship between IFS and IREF
over a range of 4mA to 4~. Monotonic operation is main·
tained over a typical range of IREF from 100~ to 4.0mA
SETTLING TIME
The DAC·08 is capable of extremely fast settling times,
typically 85ns at IREF= 2.0mA. Judicious circuit design and
careful board layout must be employed to obtain full perfor·
mance potential during testing and application. The logic
switch design enables propagation delays of only 35ns for
each of the 8 bits. Settling time to within 1/2 LSB of the LSB
is therefore 35ns, with each progressively larger bit taking
successively longer. The MSB settles In 85ns, thus deter·
mining the overall settling time of 85ns. Settling to 6-bit ac·
curacy requires about 65 to 70ns. The output capacitance of
the DAC·08 including the package is approximately 15pF,
therefore the output RC time constant dominates settling
time if RL >5000.
Settling time and propagation delay are relatively insen·
sitive to logic input amplitude and rise and fall times, due to
the high gain of the logic switches. Settling time also reo
mains essentially constant for IREF values down to 1.0mA,
with gradual increases for lower IREF values. The principal
advantage of higher IREF values lies in the ability to attain a
given output level with lower load resistors, thus reducing
the output RC time constant.
Measurement of settling time requires the ability to ac·
curately resolve :!:4~, therefore a 1kO load is needed to
provide adequate drive for most-oscilloscopes. The settling
time fixture shown in schematic labelled "Settling Time
Measurement" uses a cascode design to permit driving a 1kO
load with less than 5pF of parasitic capacitance at the
measurement node. At IREF values of less than 1.0mA,
excessive RC damping of the output is difficult to prevent
while maintaining adequate sensitivity. However, the major
carry from 011.11111 to 10000000 provides an accurate indicator of se!tlmg time. This code change does not require the
normal 6.2 time constants to settle to within ±0.2% of the final
value, and thus settling times may be observed at lower
values of I REF.
DAC-08 switching transients or "glitches" are very low and
may be further reduced by small capacitive loads at the out·
put at a minor sacrifice in settling time.
Fastest operation can be obtained by using short leads,
minimizing output capacitance and load resistor values,
and by adequate bypassing at the supply, reference and VLc
terminals. Supplies do not require large electrolytic bypass
capacitors as the supply current drain is independent of in·
put logic states; 0.11'F capacitors at the supply pins provide
full transient protection.
SETTLING TIME MEASUREMENT
+5V
FOR TURN-ON, VL = 2.7V
FOR TURN·OFF, VL" O.7V
Ikn
VOUT lX
PROBE
~~o---......_ _....._ _....J
+O.4V
~
OV
--.r
-O.4V
15kn
+VREF
A15 15
O.Olp.F
-15V,:"
TO D.U.T.
PAGE 10-35
II
~
CJ
C
'0
til
a:
w
~
a:
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>
Z
o
CJ
~
DAC-l0
rMI
10-81T HIGH SPEED MULTIPLYING
DtA CONVERTER
®
UNIVERSAL DIGITAL LOGIC INTERFACE
FEATURES
•
•
•
•
•
•
•
Fast Settling ................................ 85ns
low Full Scale Drift ...................... 10ppml°C
Nonlinearity to 0.05% Max Over Temp Range
Differential Current Outputs ................ 0 to 4mA
Wide Range Multiplying Capability ... 1MHz Bandwidth
Wide Power Supply Range ... +5, -7.5 Minto ±18VMax
Direct Interface to TTL, CMOS, ECl, PMOS, NMOS
GENERAL DESCRIPTION
The DAC·10 series of 1()'bit monolithic multiplying Digital·to·
Analog Converters provide hlgh·speed performance and full·
scale accuracy.
Advanced circuit design achieves 85ns settling times with
very low 'glitch' and low power consumption. Direct interface to all-popular logic families with full noise immunity is
provided by the high-swing, adjustable threshold logic
inputs.
All DAC·10 series models guarantee full1()'bit monotonicity,
and nonlinearities as tight as ± 0.05% over the entire oper·
ating temperature range are available. Device performance
is essentially unchanged over the ±18V power supply
range, with 85mW power consumption attainable at lower
supplies.
A highly stable, unique trim method is used, which selec·
tively shorts zener diodes, to provide V. lSB full scale ac·
curacy without the need for laser trimming.
Single·chip reliability coupled with low cost and outstanding
flexibility make the DAC·10 device an ideal building block
for AID converters, Data Acquisition systems, CRT display,
programmable test eqUipment, and other applications
where low power consumption, inputloutput versatility, and
long·term stability are required.
PIN CONNECTIONS
ORDERING INFORMATIONt
DUAl-IN-LiNE PACKAGE
18 PI!,! HERMETIC
I.N.L.
l.S.B.
±1/2
±1
MILITARY TEMP.'
COMMERCIAL TEMP.
DAC10BX'
DAC10CX'
DAC10FX
DAC10GX
• Also available wilh MIL·STD·8B38 processing. To order add/B83 asa suffix to
the part number.
tAil listed partsareavailable with 160 hour burn-in. See Ordering Information,
Section 2.
SIMPLIFIED SCHEMATIC
VREF(+)
VREF(-I
Manufactured under one or more of the following patents:
4.055.770; 4.056.740; 4.092.639
PAGE 10-36
18·PIN HERMETIC DUAl·IN·LlNE
(X Suffix)
DAC·10 10·81T HIGH·SPEED MULTIPLYING D/A CONVERTER
ABSOLUTE MAXIMUM RATINGS
Operating Temperature
DAC-10BX, CX •.•..••.•..•..•.•...... -55°C to +125°C
DAC-10FX, GX .......................... O°C to +70°C
DICE Junction Temperature (T j ) ••••••• -65°C to +150°C
Storage Temperature ••...•...•.....•.•. -65° C to + 150° C
Power Dissipation' •.••.............•............. 500mW
Derate above 100°C ......•.............••..•.. 10mW/oC
Lead Soldering Temperature (60 sec.) ....•..••...•. 300°C
V+ Supply to V- Supply •.....•.....•.....•.••.•.•.•• 36V
ELECTRICAL CHARACTERISTICS at Vs=±15V;
Logic Inputs •............•.•...•.•.•... V- to V- plus 36V
VLC ....•.....................•.................. V-to V+
Analog Current Outputs ..•.•.•....•..•....... +18 to -18V
Reference Inputs (V 14 to VIS) •.•....•..••..•••.... V- to V+
Reference Input Differential Voltage
(V 14 to VIS) ...•..•••.•.•.•.....••.•............•.. ±18V
Reference Input Current (1 14) ......•.•............. 2.5mA
NOTE: Ratings apply to both packaged parts and DICE unless otherwise
noted.
·Over full operating range
IREF=2.0mA;-55°C~TA~ 125°CforDAC-10Band DAC-10C, O°C~TA
~ 70° C for DAC-10F and G, unless otherwise noted. Output characteristics apply to both lOUT and lOUT'
DAC·10C/G
DAC·10B/F
PARAMETER
SYMBOL
CONDITIONS
MIN
Monotonicity
Nonlinearity
TYP
MAX
Differential Nonlinearity
DNL
Settling Time
ts
Output Capacitance
Co
Propagation Delay
tpLH
tpHL
0.3
All Bits Switched ON or OFF
Settle to 0.05% of FS (See Note)
All Bits Switched
Output Voltage
Compliance
Voc
Full Scale Current
Change
Gain Tempco
TCIFS
(See Note)
Full Scale Symmetry
I FSS
IFR-I FR
Zero Scale Current
Izs
Full Scale Current
IFR
RL =5k!l
RL=O
<1 LSB
(See Note)
3.968
Aeference Input Slew Aate
dl/dt
Reference Bias
Current
Ie
Power Supply Sensitivity
FSSIFS+
PSSI FS _
4.5VsV + s18V
-18VsV - s -10V
Power Supply Current
1+
11+
1-
Power Dissipation
TYP
MAX
10
10
NL
MIN
UNITS
Bits
0.5
0.6
0.3
1.0
0.7
85
135
85
LSB
LSB
150
ns
18
18
pF
50
50
50
50
ns
-5.5
+10
-5.5
+10
V
±25
±10
±5O
ppm/'C
0.1
4.0
0.1
4.0
p.A
~
0.01
0.5
0.01
0.5
p.A
Q
3.996
4.024
3.996
4.056
mA
III
II:
W
3.936
6
6
mAl.s
-1
-3
-1
-3
nA
0.001
0.0012
0.01
0.01
0.001
0.0012
O.ot
0.01
%..::11 Fsl%..::1V
Vs = + 5V/- 7.5V; IREF = 1.0mA
2.3
9.0
1.8
5.9
4.0
15
4.0
9
2.3
9.0
1.8
5.9
4.0
15
4.0
9
mA
Pd
Vs= +5V/-7.5V; IREF=I.0mA
231
85
276
107
231
85
276
107
mW
Logic Input Levels
VIL
VIH
VLC=O
0.8
V
Logic Input Currents
IlL
IIH
VLc=O; -5VsVINsO.8V
2.0VsVINsI8V
ELECTRICAL CHARACTERISTICS at Vs =
0.8
2.0
-10
2.0
-5
0.001
-10
10
-5
0.001
10
p.A
± 15V; IAEF = 2.0mA; TA =25°'C, unless otherwise noted. Output characteristics
DAC·10B/C/F
SYMBOL
CONDITIONS
MIN
Monotonlclty
NL
Differential Nonlinearity
DNL
Compliance
DAC·10G
MAX
10
Nonlinearity
Output Voltage
TYP
Full Scale Current
Change
Full Scale Current
IFS
VREF = 10.000V,
A14 = A15 = 5.000k!l
Full Scale Symmetry
IFSS
IFR-IFR
Zero Scale Current
Izs
<1 LSB
PAGE 10-37
0.5
MAX
0.3
1.0
0.7
+10
-5 -61+15
3.996
4.014
3.956
UNITS
Bits
0.6
-5 -6/+18
3.978
NOTE: Guaranteed by design.
TYP
10
0.3
Voc
MIN
3.996
0
-C
~
II:
W
~
0
0
-C
a
apply to both lOUT and lOUT.
PARAMETER
II
±10
LSB
LSB
+10
V
4.036
mA
0.1
4.0
0.1
4.0
.A
0.01
0.5
0.01
0.5
p.A
DAC-10 10 BIT HIGH-SPEED MULTIPLYING D/A CONVERTER
DICE CHARACTERISTICS
1. VLC (LOGIC)
THRESHOLD CONTROL
2. 10
3. V4.10
5. B1 (MSB)
6. B2
7. B3
8. B4
9. B5
10. B6
11. B7
12. B8
13. B9
14. B10 (LSB)
15. V+
16. VREF(+)
17. VREF (-)
18. COMPENSATION
Refer to Section
2 for additional DICE Information.
DIE SIZE 0.086 X 0.090 Inch
ELECTRICAL CHARACTERISTICS at Vs
characteristics refer to both lOUT and lOUT'
= ±1SV,
IREF
= O.SmA,
and
TA
= 2SoC,
DAC-10-N
PARAMETER
SYMBOL
CONDITIONS
LIMIT
UNITS
10
10
Bits MIN
10
10
Bits MIN
±0.5
±1.0
LSB MAX
+10.0
-5.0
+10.0
-5.0
V MAX
VMIN
+18
±40
~AMAX
0.5
0.5
~AMAX
2.0
2.0
VMIN
Monotonicity
NL
Output Voltage Compliance
Voc
True 1/2 LSB
I zs
All Bits OFF
V'H
I'N~
Output Current Range
Zero Scale Current
Logic Input "1"
IFS ± 3.996 MA
100nA
VLc@Ground
Logic Input "0"
V'L
I'N~-100~
Positive Supply Current
1+
V+~
Negative Supply Current
1-
V-~.-15V
DAC-10-G
LIMIT
Resolution
Nonlinearity
unless otherwise specified. Output
15V
TYPICAL ELECTRICAL CHARACTERISTICS at Vs ± 1SVand IREF
0.8
0.8
V MAX
14.0
14.0
mAMAX
15.0
15.0
mAMAX
= O.SmA, unless otherwise specified. Output
characteristics refer to both lOUT and lOUT'
PARAMETER
Settling Time
Gain Temperature Coefficient
(TCI
SYMBOL
CONDITIONS
ts
To ±112 LSB When Output is
Switched from 0 to FS
DAC-10-N
DAC-10-G
TYP
TYP
UNITS
85
85
ns
ppm FS/oC
±10
±10
Output Capacitance
18
18
pF
Output Resistance
10
10
MO
VREF TampeD Excluded
PAGE 10-38
DAC-10 10-BIT HIGH-SPEED MULTIPLYING D/A CONVERTER
TYPICAL PERFORMANCE CURVES
OUTPUT CURRENT vs
OUTPUT VOLTAGE
(OUTPUT VOLTAGE COMPLIANCE)
TRUE AND COMPLEMENTARY
OUTPUT OPERATIONS
•.0
OUTPUT VOLTAGE
COMPLIANCE vs TEMPERATURE
r--,-"'T"-'--'--'--'----'--'
+28.0
ALL BITS ON
I---+-+-+---+-+-+---+---j
•. 4 =rT1"-~r-T-MA--Xt--I--+--t---1
5 .• ---r---j---I--I--+-I--t--I
4.8 1--+--+--+--+--+--t---1--I
+24.0
7.2
OmA-
.,
E
2.0mA-
;:
i:l
v-
= -15V V- = -lOV
+20.0
~ 4.0
4.0mA-
"3.2
--_
.. -
--
t--t-rt--+--t--t---
~ ':=l=If::::E=-i::::f=)iR:EF~-I,~m:A~
~
o
2.4
1.•
I
~
+16.0
"
+12.0
~
IREF '" 2mA
g
+8.0
>~
+4.0
o
,,-
-4.0
IR~F = O~2mA
0.8 - -
--11.0
-12.0 '---'--_ _~_--'-_ _--'--_ _~..J
-14
POWER SUPPLY CURRENT vs V+
10.0
t--t-"*~F-+--+-t-+:---r--t--j
9.0
1
5.0
4.0
1--+-+-1--+-+-+-+-+-+----1
~ 4.0
3.0
I-+-+-I-+--+-I-+-+-I---!
ffi
2.0
l-+~=~-F--I--::j=t;;"i:-=!-~
1.0
1-+-+-l-r-l---1-r-+---1---!
7.0
•. 0
o
2.0
14
-2
10
OUTPUT VOLTAGE (VI
BrTS MAY BE "HIGH" OR "LOW"
8 .0
~
7.0
0::
6.0
- j - WITH
i
2.0
I
WITH IREF
1.0
r---r--,---,----r--,-,
9.0
t-t=:~=~+-__t--+-i
a,02mA
-4.0
-2.0
-8.0
-6.0
r--
I--+---+---+--+-'-+--I
f--+----+----II--f---+---l
•. 0
r-t---+----+--I-+----t---t
ALL BITS
5.0
"H~.~'r_~~~.~+W_"--+_I
2.0
1--t==F=---I"==:j:-:;"---l-....j
~
1.0
--~-----t----+---+--I
-50
0
+50
+100
TEMPERATURE (OC)
iO '"
ACCOMMODATING BIPOLAR REFERENCES
RREF
MSB
LSB
Bl B2B3B4B5B6B7B8B9B10
VAEF{+} e--y(R",'.",}_-<>,,'."-I
~
VIN~
AAEF
~ 'AEF
,.
RIN
10
17
IREF
+VREF
AAEF"" R17
AAEF
PEAK NEGATIVE SWING OF liN
,.
A17
VREF '" +10.000V
RREF '" 5.000k
R15 =0 RAEF
Cc =0 O.Ol/lF
VLC '" OV (GROUND)
C::,._______
(OPTIONAU
VIN~_. __
HIGH INPUT
IMPEDANCE
17
'--------j
+VREF MUST BE ABOVE PEAK POSITIVE SWING OF VIN
PAGE 10-39
W
II:
W
>
+150
o
o
~
+~:~~ x ~~~! x 2
10 +
IFA FOA
ALL LOGIC STATES
I/)
Z
-12.0
-16.0
-20.0
-14.0
-1a,O
·-10,0
+VREF
:<
~
c(
Q
II:
BASIC CONNECTIONS
IFA
o
I--t-----t---r
I-----i--- I-+----i- V+ '" 115v -+----1----1
V-, NEGATIVE POWER SUPPLY (Vdc)
BASIC POSITIVE REFERENCE OPERATION
II
3.0
4.0
r-
1-
IREF '" 2.0mA
7.0
•.0
I I I
4.0 6.0 8.0 10.012.0 14.0 16,0 18.0 20.0
V+, POSITIVE POWER SUPPL V (Vdc)
+150
10.0
V- '" -15V
IREF '" lmA-
I I I
I I I
.~
2
I
1- WITH IREF = .2mA
3.0
+100
POWER SUPPLY CURRENT
vs TEMPERATURE
I I T I
5,0
+50
TEMPERATURE ICC)
I I I
i3
o
-50
18
1- WITH IREF = 2mA
1-+-+-l-r-l---1-r-+---1----1
1-+-+-l-r-l---1-r-+---1---!
1-+-+-l-r-l---1-r-+---1---!
I-+-+-I-+--+-I-+-+-I---!
B.O
-6
POWER SUPPLY CURRENT vs V-
10.0 rA-L~L"'B='T""S"'''H'''IG'''H-''-O'''R''''''-LO-W~'-'-,-,-.----,
9.0
-10
DAC-1o 10-81T HIGH-SPEED MULTIPLYING D/A CONVERTER
BASIC NEGATIVE REFERENCE OPERATION
RECOMMENDED FULL SCALE ADJUSTMENT CIRCUIT
RREF 1
":'" -VREF
LOWT.C.
4.SIdl
.,OY
VREF
-.l!!.
39kn
RT7 11
IREF(+) .... 2mA
...J
--'<>---"""r~ _ _
10kn
~1V
17
POT
NOTE. RREF seTS IFS; R15 IS FOR
BIAS CURRENT CANCELLATION.
; APPROX
61500n.
Settling time and propagation delay are relatively insensitive
to logic input amplitude and rise and fall times, due to the high
gain of the logic switches. Settling time also remains essentially
constant for IREF values down to 1.0mA, with gradual increases for lower IREF values. The principal advantage of
higher IREF values lies in the ability to attain a given output
level with lower load resistors, thus reducing the output RC
time constant.
The nonlinearity and monotonicity specifications of the
DAC-10 are guaranteed to apply over the enti re rated operati ng
temperature range. Full scale output current drift is tight,
typically ±10ppm/o C, with zero scale output current and drift
essentially negligible compared to 'h LSB.
The temperature coefficient of the reference resistor R14
should match and track that of the output resistor lor minimum
o
~
Q
I/)
Measurement of settling time requires the ability to accurately
resolve ±2/LA, therefore a 2.SKO load is needed to provide
adequate drive for most oscilloscopes. The settling time
fixture of schematic titled "Settling Time Measurement" uses
a cascode design to permit driving a 2.SkO load with less than
SpF of parasitic capacitance at the measurement node. At
I REF values of less than 1.0mA, excessive RC damping of the
output is difficult to prevent while maintaining adequate
sensitivity. However, the major carry from 0111111111 to
1000000000 provides an accurate indicator of settling time.
This code changes does not require the normal 6.2 tim,e
constants to settle to within ±0.2% of the final value, and thus
settling times may be obse~ved at lower values of IREF.
l
DAC-10 switching transients or "glitches" are very low and
may be further reduced by small capacitive loads at the output
at a minor sacrifice in settling time.
TEMPERATURE PERFORMANCE
II
Fastest operation can be obtained by using short leads,
minimizing output capacitance and load resistor values, and
by adequate bypassing at the supply, reference and VLC
terminals. Supplies do not require large electrolytic bypass
capacitors as the supply current drain is independent of input
logic states; 0.1 ",F capacitors at the supply pins provide full
transient protection.
PAGE 10-43
a:
w
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~
DAC-20
PMI
2-DlGlT BCD HIGH-SPEED
MULTIPLYING D/A CONVERTER
®
UNIVERSAL DIGITAL LOGIC INTERFACE
FEATURES
•
•
•
•
•
•
•
•
•
•
•
Fast Settling Output Current. . . . . . . . . . . . . . . . . .. 85ns
Full Scale Current Prematched to ± 1 lSB
Direct Interface to TTL, CMOS, ECl,PMOS, NMOS
Nonlinearity to ± 1/4 lSB Maximum Over
Temperature Range
High Output Impedance and Compliance -10V to + 18V
Complementary Current Outputs
Wide Range Multiplying Capability. .. 1MHz Bandwidth
low FS Current Drift .................. , ± 10ppm/oC
Wide Power Supply Range ............ ±4.5Vto ±18V
low Power Consumption .............. 37mW @ ±5V
low Cost
Dual complementary current outputs with -10V to +18V
voltage compliance enable resistive termination, a voltage
output without an external op amp.
All DAC·20 series models guarantee full2·digit monotonicity,
and nonlinearities as tight as ±1/2 LSB over the entire
operating temperatUfe range are available. Nonlinearity is
unchanged over the ±4.5V to ±18V power supply range,
with 37mW power consumption attainable at ±5V supplies.
The compact size and low power consumption make the
DAC-20 attractive for portable applications.
GENERAL DESCRIPTION
The DAC·20 series of 2·digit BCD monolithic multiplying
digital·to·analog conv.erters provide very high·speed perform·
ance coupled with low cost and outstanding applications
flexibility.
Advanced circuit design achieves 85ns settling times with
very low "glitch" and at low power consumption. Monotonic
multiplying performance is attained over a wide 40 to 1
ORDERING INFORMATION
reference current range. Matching to within 1 LSB between
reference and full scale currents eliminates the need for full
scale trimming in most applications. Direct interface to all
popular logiC families with full noise immunity is provided
by the high swing, adjustable threshold logiC inputs.
DAC-20 applications include AID converters, audio attenuators, analog meter drivers, programmable power supplies, high-speed modems and other applications where low
cost, high speed and complete input/output versatility are
required.
PIN CONNECTIONS
t
16 PIN DUAL INLINE PACKAGE
COMMERCIAL TEMPERATURE RANGE
INL
LSB
1/2
HERMETIC
PLASTIC
DAC20CQ
DAC20CP
tAil listed parts are available with 160 hour burn-in. See Ordering Information,
Section 2.
EQUIVALENT CIRCUIT
16
COMPo
3
v-
Manufactured under one or more of the following patents:
4,055,773; 4,056,740; 4,092,639
PAGE 10-44
16-PIN HERMETIC
DUAL-IN-LiNE
DAC-20 2-DIGIT BCD HIGH-SPEED MULTIPLYING D/A CONVERTER
ABSOLUTE MAXIMUM RATINGS
(TA = 25'C unless otherwise noted)
v+
Operating Temperature Range
DAC-20
CP _..... . . . . . . . . . . . . . .. O'C to + 70'C
ca,
DICE Junction Temperature (Tj) •••••••
Storage Temperature Range. . . • . • . •.
-65' C to
+ 150' C
Reference Input Current (1 14) .•..•..•..•..••...• 5.0mA
NOTE: Absolute ratings apply to both DICE and packaged parts unless
otherwise noted.
Derateabove100'C ....•.......•.••...... 10mW/'C
Lead Soldering Temperature (60 sec) ...........• 300'C
at Vs = ±15V, IREF
Supply ••.•••••.•.. . . . • • . • . . • •. 36V
Reference Inputs (V14' V 1S) ••.••..••.•.•..•.. V - to V +
Reference Input Differential Voltage (V14 to V 1S). • .. ± 18V
-65'C to + 150'C
Power Dissipation . • . . . . . . . . . . . . . . . . . . . . . . . • . 500mW
ELECTRICAL CHARACTERISTICS
Supply to V -
Logic Inputs •..•..........•..•.•.. V-to V - plus 36V
V LC .............•••••••••.••....•••.•..• V- toV+
= 2.0mA, O'C :5 T A :5 70'C, unless otherwise noted. Output
characteristics refer to both lOUT and 'OUT.
DAC-20C
PARAMETER
SYMBOL
CONDITIONS
MIN
Resolution
BCD 0 to 99 steps
2
Monotonicity
BCD 99 steps
2
Nonlinearity
Settling Time (Note 1)
NL
0000 0000 to 1001 1001
ts
To ±1/2 LSB (±0.5% FS)
all bits switched ON or
OFF, TA = 25'C
TYP
MAX
UNITS
2
Digits
Digits
±1I2
LSB
85
150
ns
35
60
ns
±10
±80
ppm/'C
+18
V
Propagation Delay
Each Bit
All bits switched
(Note 1)
Full Tempco
Output Voltage Compliance
(True Compliance)
t pLH •
tpHL
TCI FS
Voc
(Note 1)
Full scale current change
< 1/2 LSB « 0.5% FS)
ROUT> 20Mn typical
'REF= 1.0mA
-10
'FR4
Zero Scale Current
Izs
Output Current Range
lOR
T A = 25'C, 'REF= 2mA
a:
V-=-S.OV
V-=-7.0Vto-18V
1.92
2.2
4.2
1.98
2.04
mA
0.2
5.0
}loA
2.0
2.0
mA
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0'
0
c(
V'L
V,H
2.0
I'H
VLC=OV
Y,N = -10V to +0.8V
Y'N = 2.0V to 18V
I,L
0.8
VLC=OV
-2.0
0.002
V
±10
±10
}loA
V
Logic Input Swing
V's
V-=-15V
-10
.+18
V THA
VS =±15V
-10
+13.5
V
Reference Bias Current
',5
-3.0
}loA
-1.0
4.0
dlldt
Power Supply Sensitivity
PSSIFs+
PSSI FS_
Power Supply Current
1+
11+
1-
Power Dissipation
t-
C
Logie Threshold Range
Rate (Note 1)
C
......
Logic Input Current
Reference Input Slew
~c(
UI
Logic Input Levels
Logic "0"
Logic "1"
CO
W
Full Range Output
(Digital Input 10011001)
Logic "0"
Logic "1"
II
Pd
V+ = 4.5V to 18V
V- = -4.5V to -18V
'REF= 1.0mA
VS =±5V,I REF =1.0mA
Vs = ±15V, 'REF = 2.0mA
VS =±5V,I REF =1.0mA
Vs =±15V,I REF =2.0mA
NOTE:
1. Guaranteed by design.
PAGE 10-45
8.0
mAllJ.s
±0.0003
±0.03
±0.002
±0.03
2.3
-5.0
2.5
-7.8
3.8
-6.5
3.8
-9.1
mA
37
152
52
194
mW
%Ll.IFS
%Ll.V
DAC-20 2-DIGIT BCD HIGH-SPEED MULTIPLYING D/A CONVERTER
DICE CHARACTERISTICS
1. VLe
2. lOUT
3. V4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
DIE SIZE 0.085 X 0.065 Inch
ELECTRICAL CHARACTERISTICS at Vs = ±15V,
characteristics refer to both 'OUT and 'OUT'
lOUT
BIT 1 (MSB)
BIT2
BIT3
BIT4
BITS
BIT6
BIT7
BIT 8 (LSB)
V+
VREF(+)
VREF(-)
COMP
Reier 10 Section 2 lor additional DICE Inlormallon.
'REF
= 2.0mA, and TA = 25°C, un'ess otherwise specified. Output
DAC-20-G
PARAMETER
SYMBOL
BCD 0 to 99 Steps
Resolution
Monolonicity
Nonlinearity
LIMIT
CONDITIONS
BCD 99 Steps
NL
FS = 1001 1001
Output Voltage Compliance
UNITS
Digits MIN
Digits MIN
±1/2
LSB MAX
Voe
Full Scale Current Change
< 1/2 LSB
+18
-10
V MAX
VMIN
Full Scale Current
IFS4
V REF = 10.000V
R'4' R'5 = 5.000kn
2.04
1.92
mAMAX
mAMIN
Zero Scale Current
Izs
5.0
p.AMAX
2.1
4.2
mAMIN
mAMIN
V-=-5.0V
V- = -7.0V to -18V
Output Current Range
lOR
Logic "0" Input Level
V'L
0.8
V MAX
Logic "1"lnput Level
V'H
2.0
VMIN
Logic Input Current
Logic "0"
Logic "1"
I'L
I'H
V'N = -10V to +0.8V
V'N = 2.0V to 18V
±10
±10
p.A MAX
Logic Input Swing
V's
V-=-15V
+18
-10
V MAX
VMIN
Power Supply Sensitivity
PSSIFS +
PSSI FS _
V+ = 4.5V to 18V
V- = -4.5V to -18V
IREF= 1.0mA
Power Supply Current
1+
1-
VS =±18V
IREF ,,2.0mA
3.8
-7.8
mAMAX
Power Dissipation
Pd
VS =±18V
IREF ,,2.0mA
194
mWMAX
±0.03
±0.03
TYPICAL ELECTRICAL CHARACTERISTICS at Vs = ± 15V and
characteristics refer to both 'OUT and 'OUT'
'REF
~~CS
MAX
= 2.0mA, unless otherwise specified. Output
DAC-20-G
PARAMETER
SYMBOL
Reference I "put Slew Rate
dl/dt
Propagation Delay
t pLH• tpHl
ts
Settling Time
TYPICAL
CONDITIONS
UNITS
8.0
mNp.S
TA = 25'C, Any Bit
35
ns
To ±1/2 LSB, All Bits Switched
ON or OFF, TA = 25'C
85
~s
PAGE 10-46
DAC·20 2·DIGIT BCD HIGH·SPEED MULTIPLYING DIA CONVERTER
TYPICAL REFERENCE PERFORMANCE CURVES
FULL SCALE CURRENT vs
REFERENCE CURRENT
(DIGITAL INPUT 1001 1001)
REFERENCE AMP COMMON
MODE RANGE (DIGITAL INPUT
1001 1001)
2.8
5.0
1
.
~
v~. ,'~V
2.0
V-.I...V
I
1.6
IV+ ..
1,5V
1
.
'iEF - tmA
I
illII:
.""
"I!:
"0
.L1A
1.2
4.0
"I!:
2.0
"
0
0.8
I
IRL . .l2mA
0.4
0.0
-16
~
1.0
V
-12
-4
-8
12
0.0
16
1.0
'/
.
""
- f--
LIMIT FOR
V-I· ...~
3.0
2.0
4.0
~
1.2
g
NOTE:
POSITIVE COMMON MODE IS ALWAYS (v+J -1.6V;
NEGATIVE COMMON MODE RANGE IS V- PLUS
(lREF x 8000) PLUS 2.5V.
!
~
~
II:
0.4
R'4 = R,S .. 1kO
RL os;;; 600n
VRtS = ov
-10
I
-12
100 125 160 176
0.1
0.2
,
iiiII:
1.6
V-'~6V
II
I
II:
.""
~
1\
"
1.2
0.8
I
0.4
5,0
2.0
10
..a
OUTPUT VOLTAGE (VOLTS)
POWER SUPPLY CURRENT vs V-
POWER SUPPLY CURRENT vs V+
...--r-,--...--r--r-,-,....--,--,--,
8.0
ALL BITS "HIGH" OR "LOW"
BITS MAY BE "HIGH" OR "LOW"
I - WITH IREF" 2mA
~
...sill
6.0
.I-
III I
a:
a:
""~
I- WITH IREF '" 1mA
4.0
~
1- WI~H I~EF 10.2~A_
II:
~
it
0.0
'--'-....J...-,_,---,-...o....-'--'_-'--'
0.0
2.0 4.0
6.0 8.0
10
12
14
16
18
2.0
20
1+
PAGE 10-47
t--
0.0 -2.0 -4.0 -6.0 -8.0 -10 -12 -14 -18 -18 -20
V-, NEGATIVE POWER SUPPLY (Vdcl
V+, POSITIVE POWER SUPPLY (Vdcl
c
(I)
I!:
W
lI!:
I J
-4
+1.OV, LARGE SIGNAL.
CURVE 2: Cc = 15pF, V IN = 5OmVp_p CENTERED AT
+200mV, SMALL SIGNAL.
1-
I I
j I
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-16 -12
CURVE 1: Cc· 15pF, VIN .. 2.OVp-p CENTERED AT
8.0
•
~
:REF .12mA
IREF" 0.2mA
0.0
1.0
I I
IREF'" 1mA
0
I IIII
0.5
2.0
L-l~V
FREQUENCY (MHzl
TEMPERATURE (OC)
0.0
16
2.6
1
.
II
-14
75
12
-4
OUTPUT CURRENT vs OUTPUT
VOLTAGE (OUTPUT VOLTAGE
COMPLIANCE) (DIGITAL
INPUT 1001 1001)
2.4
1\
.
-6
w
>
50
-8
LOGIC INPUT VOLTAGE (VOL TSI
112'
./
i\.0
\
-2
0
25
I
-12
THE RECOMMENDED RANGE FOR OPERATION WITH
WITH A DC REFERENCE CURRENT IS +D.2mA
TO +4.0mA.
.
"
0.8
0
I
TAsTMINTOTMAX
, ,
,
0.0
-75 -SO -25
2.0
0.0
-16
6.0
REFERENCE INPUT FREQUENCY
RESPONSE (DIGITAL INPUT
1001 1001)
>
>-"
II
~
"g
'REF, REFERENCE CURRENT (mAl
VTH - VLC vs TEMPERATURE
~
4.0
~
0;
2.0
1.6
6.0
II:
II:
'/
0.0
V ts. REFERENCE COMMON MODE VOLTAGE (VOLTS)
NOTE:
'/
V
/ r--.,
~
"".ill
V
V
3.0
II:
.a
II:
8.0
FOR
T~' iMIN ITO ~MA~- f-- f-,LlMIT
v.; ·15V
I I
TA = TMIN TO TMAX
2.4
LOGIC INPUT CURRENT
vs INPUT VOLTAGE
12
16
~
PAC·2o 2·PIGIT BCP HIGH·SPEEP MULTIPLYING PIA CONVERTER
TYPICAL REFERENCE PERFORMANCE CURVES
POWER SUPPLY CURRENT
vs TEMPERATURE
OUTPUT VOLTAGE
COMPLIANCE vs TEMPERATURE
""r--r--r.,--,-,-....-r--r---,
ALL BITS "HIGH" OR "LOW"
16
100 125
0.0 '--'---I..---''--'-...J..---'_-'-.............
-76 -SO -26
0
25 50 75 100 125 160
150
TEMPERATURE (OCI
TEMPERATURE (OCI
BASIC OUTPUT CONNECTIONS
With complementary current outputs, the DAC·20 may be
used with either positive true or negative true (complemen'
tary) logic. Current appears at the "true" output (Io)when a
"1" is applied to a logic input. As the BCl).coded input in·
creases, the sink current at Pin 4 increases proportionately,
in the fashion of a "positive logic" D/A converter. When a
"0" is applied to a logic input, that current is turned OFF at
Pin 4 and ON at Pin 2 (i~) which is used for negative true or
"negative logic" D/A converters.
The unused output must be connected to ground or some
voltage source capable of sourcing 1.65 times IREF.A detailed
discussion of reference input operation begins on the next
page.
Both outputs have an extremely wide voltage compliance
enabling fast direct current·to·voltage conversion through a
resistor tied to ground or other voltage source. Positive
compliance is 36V above V - and is independent of the
positive supply. Negative compliance is given by V- plus
(l REFX800Il) plus 2.5V.
POSITIVE VOLTAGE OUTPUT
NEGATIVE TRUE LOGIC INPUTS
POSITIVE TRUE LOGIC INPUTS
MSD
MSD
LSD
,...-..,...-..
+15V -15V
DECIMAL
INPUT
+15V -15V
-15V
BCD INPUT
MSD
LSD
10
------LSD
,...-..
Eo
0
0000
0000
0
10
0001
0000
0.20mA
+1.0V
0
BCD INPUT
DECIMAL
INPUT
MSD
LSD
10
0
1111
1111
0
10
1110
1111
0.20mA
Eo
0
+1.0V
20
0010
0000
0.40mA
+2.0V
20
1101
1111
0.40mA
+2.0V
30
0011
0000
O.BOmA
+3.0V
30
1100
1111
O.60mA
+3.0V
40
0100
0000
0.80mA
+4.0V
40
1011
1111
O.60mA
+4.0V
80
1000
0000
1.60mA
+8.0V
80
0111
1111
1.60mA
+8.0V
99
1001
1001
1.98mA
+9.9V
99
0110
0110
1.98mA
+9.9V
PAGE 10-48
DAC·20 2·DIGIT BCD HIGH·SPEED MULTIPLYING D/A CONVERTER
NEGATIVE VOLTAGE OUTPUT
NEGATIVE TRUE LOGIC INPUTS
POSITIVE TRUE LOGIC INPUTS
EO
(HIGH Zl
S.DOkU
+15V -15V
BCD INPUT
DECIMAL
INPUT
MSD
10
LSD
-15V
+15V -15V
-1SV
BCD INPUT
Eo
DECIMAL
INPUT
1111
1111
0
10
1110
1111
O.20mA
-1.0V
0000
0000
0
10
0001
0000
0.20mA
-1.0V
MSD
10
LSD
Eo
0
20
0010
0000
0.40mA
-2.0V
20
1101
1111
0.40mA
-2.0V
30
0011
0000
O.60mA
-3.0V
30
1100
1111
O.60mA
-3.0V
40
0100
0000
O.60mA
-4.0V
40
1011
1111
O.60mA
-4.0V
80
1000
0000
1.60mA
-B.OV
80
0111
1111
1.60mA
-B.OV
99
1001
1001
1.9BmA
-9.9V
99
0110
0110
1.9BmA
-9.9V
REFERENCE OPERATION
POSITIVE
NEGATIVE
1/1
a:
------ -----MSD
~~
LSD
81 82 63 84 65 B6 B7 88
B1 82 B3 84 85 66 87 B8
MSB
MSB
lSB
-
RREF
VREF(+)
VREF(+)
(R141'4
~
VREF/-)
R1S 15
VLC = QV (GROUND)
V REF (+)
c(
Q
R15 '5
TTL OPERATION,
TYPICAL VALUES ARE:
VREF '" +10.000V
RREF '" S.OOOk
R,S "'" RREF
R,S"'" RAEF
Cc = O.OlJ.[F
Cc
v-
= Q.Ql~F
VlC = OV (GROUND)
V+
vLC
IFS = RREF
'0 +
(R141'4
FOR FIXED REFERENCE,
FOR fiXED REFERENCE,
TIL OPERATION,
TYPICAL VALUES ARE:
VREF '= +10.000V
RREF '" 5.000k
IQ ""
'REF x 1.65
FOR ALL LOGIC INPUT STATES
v-
v+
VLC
VREFH
l FS '" AREF
IQ ""
+
'REF x 1.65
FOR ALL LOGIC INPUT STATES
10
REFERENCE AMPLIFIER SETUP
The DAC·20 is a multiplying converter in which the output
current is the product of a digital number and the input
reference current. The reference current may be fixed or
may vary from nearly zero to +4.0mA. The full range output
current is a linear function of the reference current and is
given by:
IFR = 991100 X IREF, where IREF = 114,
In positive reference applications an external positive
reference voltage forces current through R14 into the
a:
W
>
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o
o
RREF
I ReF
VREF{-)
w
f-
VREF( +) terminal (Pin 14) of the reference amplifier. Alternatively, a negative reference may be applied to VREF( -) at
Pin 15; reference current flows from ground through R14 into
VREF( +) as in the positive reference case. This negative
reference connection has the advantage of a very high im·
pedance presented at Pin 15. The voltage at Pin 14 is equal
to and tracks the voltage at Pin 15 due to the high gain of
the internal reference amplifier. R 15 (nominally equal to R 14)
is used to cancel bias current errors and may be eliminated
with only a minor increase in error.
DAC·20 2·DIGIT BCD HIGH·SPEED MULTIPLYING D/A CONVERTER
When a DC reference is used, a reference bypass capacitor
is recommended. A 5.0V TTL logic supply is not recommend·
ed as a reference. If a regulated power supply is used as a
reference, R14 should be split into two resistors with the
Junction bypassed to ground with a 0.1/LF capacitor.
For most applications the tight relationship between IREF
and IFR wili eliminate the need for trimming IREF . If reo
qulred, full·scale trimming may be accomplished by ad·
Justing the value of R14.
The reference amplifier must be compensated by using a
capacitor from Pin 16 to Y -. For fixed reference operation,
a O.01/LF capacitor is recommended. For variable reference
applications, see section entitled "Multiplying Operation."
LOGIC INPUT OPERATION AND INTERFACING
VTH = VLC +1.4V
VTH" +1.6V
VTH '" +1.4V
+15V
9.1kO
VLe
MULTIPLYING OPERATION
The DAC·20 provides excellent multiplying performance
with an extremely linear relationship between IFS and IREF
over a range of 4mA to 4jtA. Monotonic operation is main·
tained over a typical range of IREF from 100jtA to 4.0mA.
AC reference applications will require the reference
amplifier to be compensated using a capacitor from Pin 16
to V -. The value of this capaCitor depends on the im·
pedance presented to Pin 14: for R14 values of 1.0, 2.5 and
5.0kO, minimum values of Cc are 15, 37, and 75pF. Larger
values of R14 require proportionately increased values of Cc
for proper phase margin.
&."'"
ECl
Fastest settling times are obtained when Pin 1 sees a low
impedance. If Pin 1 is connected to a 1kO divider, for exam·
pie, it should be bypassed to ground by a 0.01/LF capacitor.
Bipolar references may be accommodated by offsetting
VREF or Pin 15. The negative common mode range of the
reference amplifier is given by: VCM - = V-plus (I REF X
8000) plus 2.5V. The positive common mode range is V + less
1.5V.
+1SV CMOS
TTL
IREF = 1mA is recommended. For interfacing other logic
families, see the figure above. Pin 1 will source 100jtA
typically, so the external circuitry must be designed to accommodate this current. Note that the threshold voltage
has the temperature dependence of two forward biased
diodes. The two VLC setting circuits shown above Include
temperature compensation.
CMOS, NMOS, PMOS
V+
For fastest response to a pulse, low values of R14 enabling
small Cc values should be used. If Pin 14 Is driven by a high
impedance such as a transistor current source, none of the
above values will suffice and the amplifier must be heavily
compensated which will decrease overall bandwidth and
slew rate. For R 14 =1kO and Cc=15pF, the reference
TO PIN 1
VLe
&.2k!l
"'"
TO PIN 1
'---t--o VLe
••-.A
ACCOMMODATING BIPOLAR REFERENCES
~
-S.2V
"
LOGIC THRESHOLD CONTROL
The DAC-20 design Incorporates a unique logic Input circuit
which enables direct interface to all popular logic families
and provides maximum noise immunity. This feature is
made possible by the large Input swing capability, 2jtA logic
input current and completely adjustable logic threshold
voltage. For V- = -15V, the logic inputs may swing between -10V and + 18V. This enables direct interface with a
+ 15V CMOS logic, even when the DAC-20 is powered from a
+5V supply. Minimum logic threshold voltage are given by:
V- plus (I REF X 8000) plus 2.5V. The logic threshold may be
adjusted over a wide range by placing an appropriate
voltage at the logic threshold control pin (Pin 1, VLcl.
The logic input threshold Is 1.4V above VLC. For TTL and DTL
interface, simply ground Pin 1. When Interfacing ECL, an
PAGE 10-50
OAC-20
'REF> PEAK NEGATIVE SWING OF liN
"
R15 (OPTIONAL) 15
VREF(+) MUST BE ABOVE PEAK POSITIVE
SWING OF VIN
DAC-20
DAC-20 2-DIGIT BCD HIGH-SPEED MULTIPLYING DIA CONVERTER
amplifier slews at 4mA/I's enabling a transition from IREF =0
to IREF = 2mA In 500ns.
Operation with pulse inputs to the reference amplifier may
be accommodated by the alternate compensation scheme
shown above. This technique provides lowest full·scale tran·
sition times. An internal clamp allows quick recovery of the
reference amplifier from a cutoff (lREF = 0) condition. Fullscale transition (0 to 2mA) occurs in 120ns when the equivalent impedance at Pin 14 is 2000 and Cc = O. This yields a
reference slew rate of 16mAll's which is relatively independent of RIN and V1N values.
compliance would be reduced to near zero. Operation from
lower supplies is possible. However, at least BV total must
be applied to insure turn-on of the internal bias network.
Symmetrical supplies are not required, as the DAC-20 is
quite insensitive to variations in supply voltage. Battery
operation is feasible as no ground connection is required:
however, an artificial ground may be useful to insure logic
swings, etc., remain between acceptable limits.
Power consumption may be calculated as follows:
Pd = (1+) (V+) + (1-) (V-) + (2 I REF ) (V-). A useful feature of
the DAC-20 design is that supply current is constant and independent of input logic states; this reduces the size of the
power supply bypass capacitors.
PULSED REFERENCE OPERATION
TEMPERATURE PERFORMANCE
The nonlinearity and monotonicity specifications of the
DAC-20 are guaranteed to apply over the entire rated
operating temperature range. Full-scale output current drift
is tight, typically ± 10ppm/oC, with zero-scale output current
and drift essentially negligible compared to 1/2 LSB.
The temperature coefficient of the reference resistor R14
should match and track that of the output resistor for
minimum overall full-scale drift.
TYPICAL VALUES:
RIN = 5k
VIN(+) = 10V
SETTLING TIME OPTIMIZATION
POWER SUPPLY CONSIDERATIONS
The DAC-20 operates over a wide range of power supply
voltages from a total supply of 9V to 36V. When operating at
supplies of ±5V or less, IREF:s1mA is recommended. Low
reference current operation decreases power consumption
and increases negative compliance, reference amplifier
negative common mode range, negative logic input range,
and negative logic threshold range; consult the various
figures for guidance. For example, operation at -4.5V with
IREF = 2mA is not recommended because negative output
The DAC-20 is capable of extremely fast settling times,
typically 85ns at IREF = 2.0mA. Judicious circuit design and
careful board layout must be employed to obtain full performance potential during testing and application. The output
capacitance of the DAC-20 including the package is approximately 15pF, therefore the output RC time constant
dominates settling time if RL > 5000.
Fastest operation can be obtained by using short leads,
minimizing output capacitance and load resistor values,
and by adequate bypassing at the supply, reference and VLC
terminals. Supplies do not require large electrolytic bypass
capacitors as the supply current drain is independent of input logic states; 0.11'F capacitors at the supply pins provide
full transient protection.
PAGE 10-51
•
~c
II)
II:
W
l-
II:
W
>
Z
o
o
0(
Q
DAC-76
PMI
COMDAC® COMPANDING
D/A CONVERTER
MONOLITHIC LOGARITHMIC OAC
FEATURES
•
•
•
•
•
•
•
•
•
•
•
COMDAC® TRANSFER CHARACTERISTIC
Sign Plus 12-Bit Range with Sign Plus 7-Blt Coding
12-Bit Accuracy and Resolution Around Zero
Sign Plus 72dB Dynamic Range
True Current Outputs: -5V to +1BV Compliance
Tight Full Scale Tolerance Eliminates Calibration
Low Full Scale Drift Over Temperature
Conforms with Bell System ,...255 Companding Law
Multiplying Reference Inputs
Low Power Consumption and Low Cost
Ideal for PCM, Audio, and B-Bit JLP Applications
Outputs Multiplexed for Time Shared Applications
x 000 0000
11111111
DIGITAL INPUT
GENERAL DESCRIPTION
The DAC-76 monolithic COMDAC@ D/A Converter provides
the dynamic range of a sign + 12-bit DAC in a sign + 7-bit for-
ORDERING INFORMATIONt
18 PIN DUAL INLINE PACKAGE HERMETIC
MILITARY
TEMPERATURE
ACCURACY
COMMERCIAL
TEMPERATURE
DAC76BX·
DAC76X·
112 STEP
1 STEP
1112 STEP
DAC76EX
DAC76CX
DAC76DX
• Also available with MIL-STD-B83B processing. To order add 1883 as a suffix to
the part nu mber.
t All listed parts are available with 160 hour burn-in. See Ordering Information,
Section 2.
EQUIVALENT CIRCUIT
STEP
INPUTS
87 86 B5 B4
CHORD
INPUTS
sa
B3 B2 B1
Elo
mat. A companding (compression/expansion) transfer function is implemented by using three bits to select one of
eight binarily-related chords (or segments) and four bits to
select one of sixteen linearly-related steps within each
chord. Accuracy is assured by specifying chord end point
values,chord nonlinearity, and monotonicity over the full
operating temperature range.
The B-bit format with a sign + 72dB dynamic range is
especially useful in control systems using B-bit microprocessors, RAMs and ROMs. Low distortion multiplying
capability and conformance with the Bell System w255
logarithmic law for PCM transmission make the DAC-76
ideal for use in audio applications. Other applications include servo controls, stress and vibration analYSiS, digital
recording and speech synthesis. Additional applications are
listed on the last page.
PIN CONNECTIONS
ENCODE/DECODE SELECT: .......-~-.-'1- ENCODE
SIGN BIT INPUT:
1 = POSITIVE
MOST SIGNIFICANT CHORD
BIT INPUT
SECOND CHORD BIT INPUT
1
POSITIVE POWER SUPPLY
2
DECODE OUT: E/O SB'" 00
DECODE OUT: EIO S8" 01
4
ENCODE OUT: EIO
CHORD BIT INPUT 5
ENCODE OUT: EIO
LEAST SIGNIFICANT
MOST SIGNIFICANT STEP
BIT INPUT
SECOND STEP BIT INPUT
THIRD STEP BIT INPUT
LEAST SIGNIFICANT STEP
BIT INPUT
13
v-
V+
VLC
PAGE 10-52
sa = 10
sa = 11
NEGATIVE POWER SUPPLY
NEGATIVE REFERENCE
INPUT
POSITIVE REFERENCE
INPUT
THRESHOLD CONTROL
DAC-76 COMDAC" COMPANDING D/A CONVERTER
ABSOLUTE MAXIMUM RATINGS
v+
Supply to V - Supply ........................ 36V
VLC Swing. . . . . . • . . . . • . . . . . • . . . . . .. V - plus 8V to V +
Analog Current Outputs ..... V - plus 8V to V - plus 36V
Reference Inputs. . . . . . . . . . . . . . . . . . . . . . . . .. V - to V +
Reference Input Differential Voltage ............. ± 18V
Reference Input Current. . . . . . . . . . . . . . . . . . . . .. 1.25mA
Logic Inputs •.....•.•...... V - plus 8V to V - plus 36V
Operating Temperature
DAC·76B, DAC-76 . . . . . . . . . . . . . . .. -55·C to + 125·C
DAC-76E, DAC-76C, DAC-76D .......... O·C to + 70·C
DICE Junction Temperature (Tjl .•..••• -65·C to +150°C
Storage Temperature ............... -65·Cto +150·C
Power Dissipation .....•..................... 500mW
Derate above 100·C ........................ 10mW'·C
Lead Soldering Temperature (60 sec.) ............ 300·C
NOTE: Absolute ratings apply to both DICE and packaged parts unless
otherwise noted.
ELECTRICAL CHARACTERISTICS at V s =± 15V, I REF =528I'A-55° C~TA:O;+ 125°C for DAC-76B and DAC-76, 0° C~TA~
4 outputs, unless otherwise noted.
+70°C for DAC-76E, C, 0 and for all
PARAMETER
SYMBOL CONDITIONS
8 chords with
Resolution
16 steps each
DAC-76B/E
MIN
TYP MAX
±128
±128
±128
±128
±128
±128
72
72
72
72
72
72
72
72
Monotoniclty
Sign Bit + or -
128
Chord Endpoint
Error relative to
ideal values at
Step error within
chord
Nonlinearity
Additional Output
Encode Current
Encode/Decode ::;: 1
Settling Time
Is
To within ±112 step
Full Scale Drift
Z
±1
Step
c(
.....
0
±1140
±118
±1120
±114
±1120
±112
Step
1140
114
1120
112
1120
1/2
Step
S.O
SO
S.O
SO
S.O
100
nA
2.0
4.2
2.0
4.2
2.0
4.2
rnA
0.8
V
40
,.A
+18
V
0
0.8
2.0
Logic Input Current liN
Logic Input Swing
V- = -lSV
VIS
W
J-
a:
U
±1
±1/2
0
VIN = -SV to
+18V
a:
Step
VLC=OV
VIL
VIH
C
UI
±1/2
Measured at
100(+) or 100(-)
with 000 0000 Input
c(
W
-S
Decode or
Encode Pair
Izs
CCI
":'
U
VREF = 10.000V
TA=2S"C
Rll = 18.94kll,
R12=20kll
Zero Scale Current
III
0.8
40
40
-S
2.0
2.0
+18
PAGE 10-53
-S
+18
-5
C
DAC·76 COMDACI!> COMPANDING D/A CONVERTER
ELECTRICAL CHARACTERISTICS al Vs= ± 15V, IREF= 528"A -55° C:5T A:5 + 125° C for DAC76B and DAC76, DO C:5T A:5
for DAC76E, C, D and for all 4 outputs, unless otherwise noted. (CONTINUED)
+7DoC
DAC·768/E
TYP
MAX
MIN
DAC·76/C
MIN
TYP
MAX
112
-1.0
-1.0
dl/dt
0.25
PARAMETER
SYMBOL CONDITIONS
Reference Bias
Current
Reference Input
Slew Rate
V+ =4.510 18V,
Power Supply
PSSIFs+
Sensitivity Over
V- = -15V
Supply Range
V- = -10.8V to
PSSI
_
(Refer to Charac-18V,
FS
teristic Curves)
V+ = 15V
1+
Power Supply
Current
11+
Vs= +5V, -15V,
IFS=2.0mA
Vs= ±15V,
IFS=2.0mA
1-
Power Dissipation
Pd
Vs= +5V, -15V,
IFS=2.0mA
Vs= ±15V,
IFS=2.0mA
-4.0
-4.0
0.25
MIN
DAC·76D
TYP
MAX
-1.0
-6.0
0.25
UNITS
pA
mA/ps
±1I20
±1/2
±1I20
±1/2
±1I20
±3/4
±1I10
:!:1/2
±1/10
±1/2
±1I0
±3J4
Step
2.7
4.0
2.7
4.0
2.7
4.5
-6.7
-8.8
-6.7
-8.8
-6.7
-9.3
2.7
4.0
2.7
4.0
2.7
4.5
-6.7
-8.8
-6.7
-8.8
-6.7
-9.3
114
152
114
152
114
167
141
192
141
192
141
207
mA
mW
NOTE:
1. In a companding DAC the term LSB is not used because the step size
within each chord is different. For example, in the first chord around
zero (Col step size is 0.5pA, while in the last chord near full scale (C 7)
step size is 641'A.
DICE CHARACTERISTICS
1. EJD
S.B.
BIT 1 (MSB)
BIT2
BIT3
BIT4
BITS
BIT8
BIT 7 (LSB)
VLC
11. VR(+)
12. VR(-)
2.
3.
4.
5.
8.
7.
8.
9.
10.
13. V-
14.IOE(+)
15.IOE(-)
18.IOD(+)
17. 10D(-)
18. V+
Refer to Secllon 2 for additional
DICE Information.
DIE SIZE 0.119 x O.OB4lnch
PAGE 10·54
DAC-76 COMDAC@> COMPANDING D/A CONVERTER
ELECTRICAL CHARACTERISTICS for V s =±15V,I REF =
528pA, TA = 25°C,
and all 4 outputs, unless otherwise noted.
DAC-78N
(Note 1)
PARAMETER
SYMBOL
Resolution
CONDITIONS
8 chords with 16 steps each
DAC-78G
(Note 2)
LIMIT
LIMIT
UNITS
±128
±128
Steps MIN
Dynamic Range
20 log (I •. ,sll •. ,)
72
72
dB MIN
Monotonicity
Sign Bit + or -
128
128
Steps MIN
Chord Endpoint Accuracy
Error relative to ideal values
at I FS = 2oo7.75jlA
±1
±1112
Step MAX
Step Nonlinearity
Step error within chord
±
±11/2
Step MAX
Encode Current
Additional Output
Encode/Decode = 1
114
3/4
114
3/4
Step MIN
Step MAX
-5
+18
-5
+18
Volts MIN
Volts MAX
±1
±1
±1
±1
Step MAX
Step MAX
±1/4
±1/2
Step MAX
Output Voltage Compliance
VOC
Full scale current change
< 1/2 step
Full Scale Current
Deviation from Ideal
I See Tables)
IFSID)
I FS IE)
VREF = 10.OOOV T A = 25" C
R11 = 18.94kO
R,.=20kO
Full Scale Symmetry
Error
10 1+)-1 0 1-) Decode or Encode Pair
Zero Scale Current
I zs
Measured at Selected
Output with 000 0000
Input
112
112
Step MAX
Disable Current
lo,s
Leakage of output
d.isabled by EtD and SB
50
100
nAMAX
Output Current Range
I FSR
0
42
0
42
mAMIN
mAMAX
Logic Input Levels
Logic "0"
Logic "1"
V'l
V'H
VlC=OV
0.8
2.0
0.8
2.0
Volts MAX
Volts MIN
Logic Input current
I'N
V'N=-5Vto+18V
40
40
jlAMAX
Logic Input Swing
V's
V-=-15V
Reference Bias Current
I,.
Power Supply Sensitivity
Over Supply Range IRefer
to Characteristic Curves)
PSSI FS +
PSSI FS-
-S
-5
+18
+18
Volts MIN
Volts MAX
4.0
6.0
jlAMAX
V+=4.SVto 18V. V-=-1SV
V-= -10.8V to -18V. V+ = 15V
±112
±3/4
±112
±3I4
Step MAX
Step MAX
Power Supply Current
1+
1-
Vs = +Sv. -15V,
IFS= 2.0mA
4.0
-8.8
4.5
-9.3
mAMAX
mAMAX
Power Supply Current
1+
1-
Vs =±15V,I FS =2.0mA
4.0
-8.8
4.S
-9.3
mAMAX
mAMAX
TYPICAL ELECTRICAL CHARACTERISTICS at Vs =
PARAMETER
SYMBOL
CONDITIONS
Settling Time
ts
To within ± 112 Step
Full Scale Drill
dl FS
Full Temperature Range
Reference Input
Slew Rate
dl/dt
Power Dissipation
NOTES:
1. See DAC-76C for typical values.
Po
± 15V,
and T A = 2S"C, unless otherwise noted.
Vs = +5V. -1SV,I FS = 2.0mA
Vs = ±1SV, I FS = 2.0mA
DAC-78N
DAC-78G
TYPICAL
TYPICAL
500
SOO
ns
±1I10
±1I10
Step
0.2S
0.25
AljlS
114
141
114
141
mW
mW
2. See DAC-76D for typical values.
PAGE 10-55
UNITS
•
III
':'
U
oC
1:1
II)
II:
IU
...II:
IU
>
Z
0
U
oC
.....
1:1
DAC-76 COMDAC8 COMPANDING D/A CONVERTER
TRANSFER CHARACTERISTICS
Note that each chord endpoint is approximately 6dB down
from the next higher chord's endpoint and that the chord
slopes are binarily-related.
ENCODE TRANSFER CHARACTERISTIC
(AID CONVERSION)
The table below relates step size in each chord to other
commonly-encountered measurements and to the equivalent, conventional, binary-coded DAC. Step size (except in
Chord 0) is about 0.3dB and is an almost constant percentage of reading. In addition, there is a 1-1/2 step change between the maximum code in each chord and the minimum
code in the next chord to smooth the chord transitions and
to conform with existing telecommunication specifications.
The following three pages contain electrical specifications,
the DC test circuit, tables of ideal chord endpoint currents
for both encode and decode modes, and parameter definitions.
COMPANDING PRINCIPLES
BACKGROUND
Companding or signal compression and signal expansion is
widely used. In FM broadcasting companding is performed
by de-emphasis and pre-emphasis. In analog systems companding is performed by log and antilog amplifiers. But in
data conversion and transmission, companding has been
limited to the telecommunications industry. They recognized
the need to efficiently represent analog signals with the
fewest possible number of digital bits. With just 8 bits, the
standard format of microprocessors, RAMs, ROMs and
registers, telecommunications companding systems achieve
very low signal-to-quantizing distortion over a 40dB range of
speech amplitudes by using the Bell System 1'"255 logarithmic
companding law.
DECODE TRANSFER CHARACTERISTIC
(D/A CONVERSION)
BELL 1'"255 LOGARITHMIC CHARACTERISTIC
The output of the DAC-76 is an approximation to the 1'"255
law which can be expressed as:
Y = 0.18 In (1 +JLl<) where:
The system transfer characteristics above result when the
DAC-76 is used for signal compression (AID conversion) and
for signal expansion (D/A conversion). As one would expect,
when the curves are superimposed their average is a
straight line because compression and expansion must be
equal and opposite.
Both transfer characteristics show outputs divided into 8
chords in both polarities with 16 equal steps in each chord.
X = Normalized input signal level of the compressor
(encoder), VINIVFs with values from -1 to +1.
Y = Output signal level of the encoder
J.t
= 255
This law is implemented by the DAC-76 with an eight chord
(or segment) piecewise linear approximation for each polarity
with sixteen linear steps in each chord. A dynamic range of
72dB in both polarities is achieved with 8-bit coding.
STEP SIZE SUMMARY TABLE DECODE OUTPUT (SIGN BIT EXCLUDED)
CHORD
STEP SIZE
NORMALIZED
TO FULL SCALE
STEP SIZE
IN,.A WITH
2007.75 ,.A F.S.
STEP SIZE
ASA%OF
FULL SCALE
STEP SIZE
IN dB AT
CHORD
ENDPOINTS
STEP SIZE AS
A % OF READING
AT CHORD
ENDPOINTS
RESOLUTION
& ACCURACY
OF EQUIVALENT
BINARY DAC
2
0.5
0.025%
0.60
6.67%
SIGN +12 BITS
4
1.0
0.05%
0.38
4.30%
SIGN+11 BITS
2
8
2.0
0.1%
0.32
3.65%
SIGN +10 BITS
3
16
4.0
0.2%
0.31
3.40%
SIGN +9 BITS
32
8.0
0.4%
0.29
3.28%
SIGN +8 BITS
5
64
16
0.8%
0.28
3.23%
SIGN+7 BITS
6
128
32
1.6%
0.28
3.20%
SIGN+6 BITS
258
64
3.2%
0.28
3.19%
SIGN+5 BITS
PAGE 10-56
DAC-76 COMDAC® COMPANDING D/A CONVERTER
OUTPUT CURRENT DC TEST CIRCUIT
0'
LINE SELECTION TABLE
R1l·
lB.94kn
TEST
GROUP
fRREFI
~~~=~~
ENCODEI
DECODE
SIGN
BIT
OUTPUT
MEASUREMENT
10E(+)
11
a
4
012
201<"
(Eo,/R1)
10E(-)
(Eo,/R2)
100(+)
(E 02/R3)
100(-)
(Eo~R4)
NOTE: Accuracy is specified in the test circuit using the tables below to be
within the specified proportion of a step at the maximum value in each
chord. Monotonic operation is guaranteed for all input codes.
*V REF IS ADJUSTED BEFORE TESTING EACH DEVICE
TO PROVIDE IDEAL FULL SCALE OUTPUT CURRENT. ":"
Rl" R2" R3 = R4 = 2.5kn
CONDENSED CURRENT OUTPUT TABLES
IDEAL DECODE OUTPUT CURRENT IN MICROAMPS AT CHORD ENDPOINTS
CHORD
o
2
3
4
5
6
001
010
011
100
101
110
111
8.25
24.75
57.75
123.75
255.75
519.75
1047.75
23.25
54.75
117.75
243.75
495.75
999.75
2007.75
8
16
32
64
000
STEP
0000
15
1111
7.5
0.50
STEP SIZE
fI)
a:
IDEAL ENCODE OUTPUT CURRENT IN MICROAMPS AT CHORD ENDPOINTS
15
a
000
001
010
all
100
101
110
111
0000
0.25
8.75
25.75
59.75
127.75
263.75
535.75
1079.75
7.75
23.75
55.75
119.75
247.75
503.75
1015.75
2039.75
8
16
32
64
1111
STEP SIZE
~
a:
CHORD
STEP
a
1&1
6
0.50
BASIC ENCODE OPERATION
(COMPRESSING AID CONVERSION)
ENCODE TRANSFER CHARACTERISTIC
(AID CONVERSION)
DIGITAL
OUTPUT (+1
1&1
ENCODE DECISION LEVELS
Compressing AID conversion with the DAC-76 requires a
comparator, an exclusive-OR gate, and a successive
approximation register - the usual elements in any signplus-magnitude AID converter. However, a compressing
ADC has one signficant difference from regular AID converters.
In a conventional (linear) converter, the step size is a constant
percentage of full scale, but in a compressing AID converter,
the step size increases as the output changes from zero
scale to full scale. The standard 1/2 sfep bias used in conventional ADCs to keep quantizing error below ±1/2 step
cannot be easily furnished by the user of a compressing
ADC. For this reason, the DAC has a 1/2 step greater output
in the encode mode that it has in the decode mode. This
may be seen clearly by comparing the normalized encode
and decode output tables at any code point.
ENCODING SEQUENCE
DIGITAL
OUTPUT (-I
An encoding sequence begins with the Sign Bit comparison
and decision. During this time the comparator is a polarity
PAGE 10-57
>
Z
o(,)
CC
Q
DAC·76 COMDAC8 COMPANDING DfA CONVERTER
C = chord no. (0 through 7)
5 = step no. (0 through 15)
NORMALIZED ENCODE LEVEL (SIGN BIT EXCLUDED) Ic. s = 212C (5 + 17) -16.51
CHORD
STEP
0
000
001
010
3
4
011
100
6
7
101
110
111
4319
0
0000
35
103
239
511
1055
2143
1
0001
39
111
255
543
1119
2271
4575
2
0010
43
119
271
575
1183
2399
4831
3
0011
7
47
127
287
607
1247
2527
5087
4
0100
9
51
135
303
639
1311
2655
5343
5
0101
11
55
143
319
671
1375
2783
5599
6
0110
13
59
151
335
703
1439
2911
5855
7
0111
15
83
159
351
735
1503
3039
6111
8
1000
17
67
167
367
767
1567
3167
6367
5
9
1001
19
71
175
383
799
1631
3295
6623
10
1010
21
75
183
399
831
1695
3423
6879
11
1011
23
79
191
415
863
1759
3551
7135
12
1100
25
83
199
431
895
1823
3679
7391
13
1101
27
87
207
447
927
1867
3807
7647
14
1110
29
91
215
463
959
1951
3935
7903
15
1111
31
95
223
479
991
2015
4083
8159
8
16
32
64
128
256
STEP SIZE
2
BASIC ENCODE CONNECTIONS
flows into 10E(-) through R2 developing a negative voltage
which is compared with the analog input. An exclusive·OR
gate inverts the comparator's output during negative trials
to maintain the proper logic coding, all ones for full scale
and all zeros for zero scale. (A more complete schematic is
shown in the applications section).
r-I
~
FOR
GROUND
SINGLE
ENDED
INPUTS
ANALOQ·TO-
DIGITAL
CONVERSION
The bits are converted with a successive removal technique,
starting with a decision at the code 011 1111 and turning off
bits sequentially until all decisions have been made. Sue·
cessive removal is necessary because the 1/2 step encode
decision level current Is drawn from the sum node, rather
than sourced into it.
DIGITAL
OUTPUTS
LOGIC
SIGN
BIT
~a]CHORD
I rf
BITS
STE'
] BITS
BASIC DECODE OPERATION
(EXPANDING D/A CONVERSION)
DECODE TRANSFER CHARACTERISTIC
(D/A CONVERSION)
ANALOG
OUTPUT (+1
detector only. The Encode/Decode (ElD) input Is held at a
logic "0". Therefore, no current flows into the encode out·
puts, and the comparator is effectively disconnected from
the DAC. Once the Input polarity has been determined, the
E/D Input is changed to a logic "1" allowing current to flow
into 10E( +) or 10E( -) depending upon the Sign Bit Answer.
For positive inputs, current flows Into 10E( +) through R1,
and the comparator's output will be entered as the answer
for each successive decision. For negative inputs, current
PAGE 10-58
ANALOG
OUTPUTI-)
DAC-76 COMDAC® COMPANDING D/A CONVERTER
BASIC DECODE CONNECTIONS
REF-Ol
+10V
E/D SB B1 B2 B3 B4 B5 B6 B7
R11
18.94kU
IRREFlr~~~~~~:--.
11
IREF
-
12
R12
20kn:
EO
1
1
1
0
0 0
0
0
1
0.0012
1
0
0 0
0
0
0
0
OV
( - ) ZERO SCALE
0
0
0 0
0
0
0
0
OV
( - ) ZERO SCALE + 1 STEP 0
0
0
0 0
0
0
0
1
-0.0012
NEG FULL SCALE
0
1
1
1
1
POS FULL SCALE
0
1
( + ) ZERO SCALE + 1 STEP 0
1
( + ) ZERO SCALE
0
0
1
1
5.019V
-5.019V
DECODE OPERATION
NORMALIZED TABLES
D/A conversion with the DAC·76 may be illustrated by using
The encode and decode tables may be used to calculate
ideal output current at any code point. For example, in
decode mode at 13,7 (011 0111) find 343. 343/8031 times IFS of
2007.75!,A equals 85.75~. Alternatively, use the condensed
current tables and add up the number of steps.
an operational amplifier connected to the decode outputs
as a balanced load. The decode mode of operation is
selected by applying a logic "0" to the Encode/Decode input.
This enables the 100 outputs, disables the 10E outputs, and
allows 100< +) or loot -) to be selected by the Sign Bit input.
When the Sign Bit input is high, a logic "1", all of the output
current flows into 100 (+) forcing a positive voltage at the
operational amplifier's output. When the Sign Bit input is
low, a logic "0", all of the output current flows into 100 (-)
through R2 forcing a negative voltage output. Since the Sign
Bit only steers current into 100 (+) or 100 (-), the output will
always be symmetrical, limited only by the matching of R1
and R2.
BASIC REFERENCE CONSIDERATIONS
Full scale output current is ideally 2007.75~ when the
reference current is 528~ in the decode mode. In the en·
code mode it is 2039.75~ because the additional 1/2 step
adds 32~ to the output. A percentage change in IREF caused
by changes in VREF or RREF will produce the same percen·
tage change in output current.
Ie
oC
Q
UI
a::
w
I-
a::
>
Z
w
o
u
NORMALIZED DECODE OUTPUT (SIGN BIT EXCLUDED) Ic. s
CHORD
STEP
0
6
0
C =chord no. (0 through 7)
5 =step no. (0 through 15)
=212C (5 + 16.5) -16.5)
2
6
000
001
010
011
100
101
110
111
0000
0
33
99
231
495
1023
2079
4191
0001
2
37
107
247
527
1087
2207
4447
0010
4
41
115
263
559
1151
2335
4703
0011
6
45
123
279
591
1215
2463
4959
0100
8
49
131
295
623
1279
2591
5215
0101
10
53
139
311
655
1343
2719
5471
0110
12
57
147
327
687
1407
2847
5727
0111
14
61
155
343
719
1471
2975
5983
8
1000
16
65
163
359
751
1535
3103
6239
9
1001
18
69
171
375
783
1599
3231
6495
10
1010
20
73
179
391
815
1663
3359
6751
11
1011
22
77
187
407
847
1727
3487
7007
12
1100
24
81
195
423
879
1791
3615
7263
13
1101
26
85
203
439
911
1855
3743
7519
14
1110
28
89
211
455
943
1919
3871
7775
15
1111
30
93
219
471
975
1983
3999
8031
16
32
64
128
256
STEP SIZE
8
PAGE 10-59
~
DAC-76 COMDAC@ COMPANDING D/A CONVERTER
The large step size at full scale allOws the use of inexpensive references in many applications_ In some situations
VREF may even be the positive power supply_ For example,
with V+ =15V, RREF=15V/528~ or 28.4kll. When using a
power supply as a reference, R11 should be two resistors,
R11 A and R11 B, and the junction should be bypassed to
ground to provide decoupling.
REFERENCE AMPLIFIER OPERATION
POSITIVE REFERENCE OPERATION
In positive reference applications an external positive
reference voltage forces current through R11 into the VR( +)
terminal (Pin 11) of the reference amplifier. Alternatively, a
negative reference may be applied to VR(-) at Pin 12;
reference current flows from ground through R11 into VR( +),
as in the positive reference case. This negative reference
connection has the advantage of a very high impedance
presented at Pin 12. The voltage at Pin 11 is equal to and
tracks the voltage at Pin 12 due to the high gain of the inter·
nal reference amplifier. R12 (nominally equal to R11) is used
to cancel bias current errors and may be eliminated with only
a minor increase in error.
REFERENCE RECOMMENDATIONS
For most applications a +10.0V reference, such as the PMi
REF-01, is recommended for optimum full scale temperature coefficient performance. (This also minimizes the con·
tributions of reference amplifier Vos and TCVos.) For most
TYPICAL PERFORMANCE CURVES
OUTPUT FULL SCALE CURRENT vs
REFERENCE INPUT CURRENT
ENCODE OUTPUTS
IDEAL VALUES:
'REf =
5.0
52B~A
r-
IFS = 2039.75pA
NOTES:
1. RECOMMENDED WHEN VREF IS V+ OR THE LOGIC POWER SUPPLY.
2.
1
PINS 11 AND 12 ARE eQUAL IN VOLTAGE. VREF IS IMPRESSED
ACROSS R1l (RREF).
TA " TMIN TO TMAX
ALL BITS "HIGH"
4.0
0-
il:
~
""
3.0
V
0-
"15
NEGATIVE REFERENCE OPERATION
2.0
~
DIGITAL INPUTS
-
NOTE 1.
JREF
IS ALWAYS IV+) -1.5V
r-:!:~~~~~
11
0.00
0.25
ENCODE
OUTPUTS
0.50
I I
1.00
0.75
1.25
'REF- REFERENCE CURRENT (mAl
12
VR(-l
DECODE
OUTPUTS
REFERENCE AMPLIFIER INPUT
COMMON MODE RANGE
R12
-15V
-VREF
~YRW
V.OTE:
rrz
V
f-
POSITIVE COMMON MODE RANGE
0.0
20kn
IREF=-
1.0
/
1/
0
Rll·
18.94kn
(RREFI
1/
1/
+15V
DeCODe OUTPUTS
IDEAL VALUES:
ENCODE OUTPUTS
IDEAL VALUES:
2.8
'REF = 528j.1A
IFS = 2007.75,uA
'REF'" 528pA
I FS '" 2039.75,uA
2.'
I
TA = TMIN TO TMAX
NOTE:
;;:
.5
PINS" AND 12 ARE EQUAL IN VOLTAGE. VAEF IS IMPRESSED
ACROSS R1l (A REF).
L-l~V
2.0
I
0-
il:0:
v+.1 +15V
1.6
""
"15
0-
REFERENCE AMPLIFIER SETUP
0
I
The DAC·76 is a multiplying D/A converter in which the out·
put current is the product of the normalized digital input and
the input reference current. The reference current may be
fixed or may vary from nearly zero to + 1.0mA. The full scale
output current is a linear function of the reference current
and is given for all four outputs in the figures above.
PAGE 10-60
1.2
0.8
'REF
II
-12
=
O,25mA:
l-
I I I
I
0.4
0.0
-16
I
'REF'" O.6mA
0:
-8
-4
12
REFERENCE COMMON MODe VOLTAGE
AT VREF PIN (VOLTS)
18
DAC-76 COMDAC'" COMPANDING D/A CONVERTER
applications the tight relationship between IREF and IFS
eliminates the need for trimming IREF ; but if desired, full
scale trimming may be accomplished by selecting R11 or by
using a potentiometer for R11.
BALANCED LOAD CONNECTIONS
REF-Ol
+10V
DIGITAL INPUTS
All·
lB.94kH
Using lower values of reference current reduces negative
power supply current and increases reference amplifier
negative common mode range. While the recommended
operating range of DC reference currents is 0.1 mA to 1.0mA,
monotonic operation is maintained over an even wider
range allowing the DAC·76 to be used in many multiplying
applications. For variable reference applications, see sec·
tion entitled "Multiplying Operation."
(AREF)
r-:!:i~~=~+';'"
11
'2
"'2
20kH
-15V
+15V
TRUE CURRENT OUTPUT OPERATION
TYPICAL BALANCED LOADS
RESISTIVE OUTPUT CONNECTIONS
•
•
•
•
•
•
V REF
REF-02
+5V
REF-Ol
+10V
+10V
DIGITAL INPUTS
Rll·
TRANSFORMER
TRANSDUCER
EARPHONE
SAMPLE AND HOLD
CURRENT INPUT FILTER
TRANSMISSION LINE
•
•
•
•
•
DATA REFERENCE INPUT
BRIDGE
OP AMP
CAT
SERVO
NOTE; THE SUM OF THE COMMON MODE VOL rAGE AND THE
DIFFERENTIAL VOLTAGE ACROSS THE LOAD SHOULO BE WITHIN
THE -5V TO +18V OUTPUT VOLTAGE COMPLIANCE SPECIFICATION.
18.94kr2
!RREF)
~~~~~,;".
4.9
4.98
4.98
kn
kn
kn
11
---
"8" and "C". The differential output voltage is independent
of the +5.00 nominal voltage source as long as the Vod-)
minimum values are observed.
V"+-.+--+-f----o"A"
r"-f---4~-+-O"B"
'/-'''----+-----+---O''c''
"'2
High common mode output range is possible due to the
wide output voltage compliance and allows use with
transformers or other balanced loads. The terminating impedances may be located a distance away from the DAC·76
allowing transmission of analog quantities as currents
rather than voltages and elimination of ground loop errors.
Capacitive termination is also possible, performing an
"integrate·and-hold" process which is a function of VREF ,
RREF, the digital input code, and the selection time for a
given current output. Resetting of the integrating capacitor
may be accomplished with a CMOS switch in parallel with
the capacitor. Thus, many applications traditionally requiring
op amps may be performed with a high voltage compliance,
current output DAC.
20kH
-15V
+15V
OUTPUT VOLTAGE (V)
----INPUT CODE
"A"
111111111
111101111
11 0000000
011111111
011101111
010000000
000000000
001101111
001111111
"8"
"c"
DIFF
0
+ 5.02
+10.00
N/A
N/A
N/A
N/A
-5.00
+0.02
+5.00
+5.00
+5.00
+5.00
+5.00
+5.00
+5.00
+5.00
+0.02
-5.00
-10
- 4.98
0
+ 4.9B
+10
NEGATIVE OUTPUT VOLTAGE
COMPLIANCE Voc(-)
IFS
TYPICAL PERFORMANCE CURVES
1.0mA
2.0mA
4.0mA
-12V
-2.BV
-2.0V
-0.4V
-15V
-5.BV
-5.0V
-3.4V
-1BV
-B.BV
-B.OV
-6.4V
2.•
MINIMUM NEGATIVE COMPLIANCE
Voc(-) MIN =(V-) +(2I REF "1.6kll)+B.4V
2.'
V-
OUTPUT CURRENT vs OUTPUT VOLTAGE
(OUTPUT VOLTAGE COMPLIANCE)
1
>-
2.D
PAGE 10-61
a:
I!:
::>
0
I~EF ='D.5m~
.1
::>
"::>>-
I
I
illa: '.B
The DAC·76 has true current outputs with wide voltage com·
pliance enabling fast drive of a variety of single'ended and
balanced loads. Positive voltage compliance is +18V, and
negative voltage compliance is -5.0V with IREF = 528pA and
V- = -15V. Negative voltage compliance for other values
of IREF and V- may be calculated using the table above.
Typical connections, both single-ended and differential, are
shown in the figure above with output voltage tables. Note
the differential sign-plus·magnitude relationship between
J
.II
T A '" TMIN TOTMAX
-V-=-15V
'.2
1_
I.
'REF '" O.25mA -
D.•
I
D.'
D.D
-16
-12
-8
-4
OUTPUT VOLTAGE (VOLTS)
12
16
..
, .
_
rn
II:
W
lII:
W
>
Z
o
u
~
DAC-76 COMDAC® COMPANDING D/A CONVERTER
OUTPUT VOLTAGE COMPLIANCE vs TEMPERATURE
HIGH INPUT IMPEDANCE CONNECTION
REF-Ol
+10V
DIGITAL INPUTS
VREF
> VIN
~
V'N
V REF - VIN
IREF=~
IFS"" 4 IREF
-75 -50 -25
0
25
50
75
100 125 150 175
TEMPERATURE (OC)
LOGARITHMIC DIGITAL GAIN CONTROL
MULTIPLYING OPERATION
REF-Ol
+10V
LOW INPUT IMPEDANCE CONNECTION
2.5kn
20kfl
(RREF)
1-0
r-;!;=~=~~
REF-Ol
+10V
11
+5V
INPUT
DIGITAL INPUTS
o--j
----
tREF
=
~ + V REF
RIN
_ "N
11
RIN
-....
IREF 12
12
""'"
NOTE 1: lOW DISTORTION OUTPUTS ARE PROVIDED OVER A 72dB RANGE.
RREF
NOTE 2: UP TO 4 CHANNELS OF OUTPUT MAY BE SELECTED BY Eta AND
S8 LOGIC INPUTS.
IFS"" 41AEF
-15V
+15V
TYPICAL PERFORMANCE CURVES
REFERENCE AMPLIFIER DYNAMIC TEST CIRCUIT
REFERENCE AMPLIFIER TOTAL HARMONIC
DISTORTION vs FREQUENCY (80kHz FILTER)
REf-Ol
1.0
+10V
20k,Q
(RREF)
LARGE SIGNAL
INPUT 5V PEAK
(50% MODULATION)
~
z
see NOTE 3,
0
~
11
~
0.1
is
u
12
Z
0
~
~
0.01
~
~
0.001
1.0kHl
"N
10kHz
100kHz
FREQUENCY
1.
2.
fREQUENCY
RESPONSE
TESTS
3.
PAGE 10-62
THO IS NEARLY INDEPENDENT OF LOGIC INPUT CODE.
SIMILAR AESUL TS ARE OBTAINED FOR A HIGH INPUT
IMPEDANCE CONNECTION USING PIN 12 AS AN INPUT.
INCREASED DISTORTION ABOVE 50kHz IS DUE TO SLEW
RATE LIMITING WHICH DETERMINED LARGE SIGNAL
BANDWIDTH. FOR AN INPUT OF ±2.5V PEAK (25% MOD·
ULATION). BANDWIDTH IS 100kHz.
DAC-76 COMDACIS COMPANDING D/A CONVERTER
When operating with V- between -15V and -11V, output
negative voltage compliance, Voc(-), reference input
amplifier common mode voltage range, and logic input
negative voltage range are reduced by an amount equivalent
to the difference between -15V and the V- supply in use.
Operation with V + between +5Vand + 15V affects VLC and
the reference amplifier common mode positive voltage
range in the same manner.
REFERENCE AMPLIFIER INPUT
FREQUENCY RESPONSE
SMALL SIGNAL
±lIXJMVPEAK
(1% MODULATION)
r-
j
....
~
"
0
w
>
~
a:
-4
..
-12
t-
1\
r\
~~~ERs.!~~~~ITEDI
L
TYPICAL PERFORMANCE CURVES
±5V PEAK
-,'~~ ~~OU~~~',~~:,
IIIIIII~
BIT TRANSFER CHARACTERISTICS
II 111111
111111111 11111111
-16
1.OkHz
10kHz
100kHz
1.DMHz
10MHz
0.35
IRE~ = 0.5~A
fREQUENCY
0.30
'"
iii
.s....
LOGIC INPUT & POWER SUPPLY CONSIDERATIONS
0.244
a: 0.20
a:
""
~
"
INTERFACING CIRCUIT FOR
ECl, CMOS, " NMOS lOGIC INPUTS
0
CMOS, NMOS, PMOS
ECl
81
0.25
0.16
0.10
0.055
83
II V-I" -1";
0.00
-12
13Kn
82
V-=-15V
0.05
V'
-8
0.023
-4
12
16
LOGIC INPUT VOLTAGE (VOL TSI
20KU
NOTE: ALL BITS ARE FULLY SWITCHED WITH LESS THAN
1/2 STEP ERROR AT SWITCHING POINTS WHICH ARE
GUARANTEED TO LIE BETWEEN D.BY AND 2.0V OVER
THE OPERATING TEMPERATURE RANGE.
39Kn
3KU
TO
PIN 1
L_-'-oV LC
6.2KSZ
20KU
3KH
TO
PIN 1
' - -.....-oVLC
R3
40ClpA
'---_-.-_-----.J!
-<;.2V
lOGIC INPUT CURRENT vs INPUT
VOLTAGE AND lOGIC INPUT RANGE
NOTES:
1.
2.
SET THE V,OL TAGE "A" TO BE AT THRE DESIRED lOGIC INPUT SWITCHING
THRESHOLD.
ALLOWABLE RANGE OF LOGIC THRESHOLD IS TYPICALLY -5V TO +13V
WHEN OPERATING THE DAC-76 ON ±15V SUPPLIES.
20
IREF· O•6mA
t- V-" -16V
1.
1
....
lOGIC INPUTS
The DAG-76 may be interfaced with other-than-TTl logic by
placing VLC (Pin 10) at a potential which is 1.4V below the
desired logic input switching threshold. However, this
voltage source must be capable of sourcing and sinking a
changing current at Pin 10.
The negative voltage at the logic inputs must be limited to
+10V with respect to V- (Pin 13).
VLC • DV
iiia:
a:
""....
~
10
L
~
"9
5
I
I
o
-12
-8
-4
12
16
LOGIC INPUT VOLTAGE (VOL TSI
NOTE; LOGIC INPUT VOLTAGE RANGE IS INDEPENDENT OF
THE POSITIVE POWER SUPPLY, AND LOGIC INPUTS
MAY SWING ABOVE THE SUPPLY.
POWER SUPPLIES
As shown in the curves on the next page, power supply
current drain is relatively independent of voltage and temperature and completely independent of the logic input states.
PAGE 10-63
DAC-76 COMDAC@ COMPANDING D/A CONVERTER
POWER SUPPLY CURRENTS vs
POWER SUPPLY VOLTAGES
POWER SUPPLY CURRENTS vs TEMPERATURE
8.0
ILL -
7.0
1
1-
Ht1:=j:=+::j:::~rHI
1 6.0 1--+----1-+--+-+-+---+---1-t--I
~ 5.0 ALL BITS "HIGH" OR "LOW" +--+-t--J
a:
7.0
6.0
0-
15
~
ALL BITS "HIGH" OR "LOW"
'FS = 2.0mA
5.0
">
t
~
4.0
iil
3.0
~
2.0
1+
V"':...=
'IS.
~
4.0
'FS = 2,OmA
! 10~1::t:j~+=:t~::~1+~-r--
-
a:
!<
Vs = ±15V
a:
::>
~
2.0
1-+-+--1f-+--+-t-+-+--t--l
1.0
1.0
0.0
0.0
0.0 L-..L-L---.JL-..L-L......l_.l-...I.........I.---I
-75 -50 -25 0
25 50 75 100 125 150 176
4.0
8.0
16
12
20
POSITIVE OR NEGATIVE POWER SUPPL V IVdc)
TEMPERATURE (OCI
DETAILED ENCODE CONNECTIONS
CLOCK START
.r
+6V ANALOG INPUT
L
+16V
r-I
-F
GROUND
FOR
SINGLE
ENDED
INPUTS
+5V
2.S
k!!
10
9 OP
7 0
S
Vee
GNDOO 1
1-'-_______--<> SERIAL DATA OUT
SUCCESSIVE CC 2
APPROXIMATION
REGISTER _
15
AM2S02
MSB
END OF CONV.
:Mf~~~~~~L~~~~~~~~~~~~~
431216543
L---f-'"
"l...
SIGN BIT
}
CHORD BITS
PARALLEL
ti~~==~==============~·}:~:S
+15V
NOTES:
1. CONNECT END OF CONY. TO START FOR
CONTINUOUS OPERATION.
2. FOR NON-CONTINUOUS OPERATION, HOLD START
LOW FOR ONE CLOCK CYCLE, CONVERSIONS
BEGIN ON THE NEXT LOW TO HIGH TRANSITION
OF THE CLOCK AFTER START GOES HIGH.
3. CONVERSION IS COMPLETED IN 9 CLOCK
-15V
+15V
CYCLES.
TRANSCEIVING CONVERTER - TWO WAY DATA TRANSMISSION
ANALOG
INPUT
TO
PROCESSOR
AID
ANALOG
OUTPUT
(ENCODE)
DAC-76
DIGITAL
INTERFACE
DIGITAL
INTERFACE
DATA BUS
SERIAL OR
PARALLEL
ANALOG
OUTPUT
DAC-76
AID
(ENCODE)
TRANSCEIVING CONVERTER
TRANSCEIVING CONVERTER
PAGE 10-64
ANALOG
INPUT
DAC-76 COMDAC" COMPANDING D/A CONVERTER
SERIAL DATA TRANSCEIVING CONVERTER
SEND/RECEIVE
COMMAND
HIGH-SPEED
LOW-RECEIVE
(1/2 OF SYSTEM SHOWN)
TRANSMIT INPUT
±5V ANALOG IN
GROUND FOR
NON-DIFFERENTIAL
INPUTS
+1SV
r--
I+---,~--+-t----+-------------=-'-O ~:~~:~~:'~~AL
I
~
2.Skn
2.5kO
SERIAL DATA
BUS
SUCCESSIVE
APPROXIMATION
REGISTER
CCr--.----o END OF CONY. ' -
AMZ502
(SAR)
MSB
LSB
14 1312 " 6 5 4 3
REF-Ol
HOV
NOTES:
123456789
1. COMPLEMENTARY SEND/RECEiVe COMMANDS ARE
REaUIRED FOR THE TWO ENOS.
18.94kn
2. START MUST BE HELD LOW FOR ONE CLOCK CYCLE
TO BEGIN A SEND OR RECEIVE CYCLE.
3. THE SAR IS useD AS A SERIAL-IN/PARALLEL OUT
REGESITER IN THE RECEIVE MODE.
4. CLOCK AND START MAY BE CONNECTED IN
PARALLEL AT BOTH ENDS.
5. CONVERSION IS COMPLETED IN 9 CLOCK CYCLES.
OAC-76
DIFFERENTIAL
ANALOG o-"'-----"~
12
VREF(-I
C~~~~~i <>:::=:-----'-'--'\._-;.:;-_Vr;+:;---=r.::-...
III
~
20kn
RECEIVE OUTPUT
6. RECEIVE OUTPUT IS AVAILABLE FOR ONE FUll
CLOCK CYCLE.
-15V
+15V
TYPICAL SIGNAL TO QUANTIZING DISTORTION CURVES
SIGNAL TO QUANTIZING DISTORTION vs INPUT LEVEL
(3kHz FLAT FILTER)
44
~
~
40
SIGNAL TO QUANTIZING DISTORTION vs INPUT LEVEL
(C·MESSAGE WEIGHTING FILTER & BELL SPEC)
44
I-~A=~·~
~
I- Vs = ±15V
V
36
~ 32
/
~
~
:/
J-.I.....lBELL 03 SYSTEM
SPECIFICATION
1/
C 2B
~ 24
N
I- bAC~76
t,...-I-"'"
TA=25Q C
VS=±15V -
J
V
f-
12
~
~
8
in
4
o
-60
-50
-40
-30
-20
-60
-10
-60
-40
-30
-20
-10
INPUT LEVEL (dB)
NOTES;
1. Ode IS ±3.5V, +3d8 IS ±S.OV OR FULL SCALE CODE
INPUT LEVEL (dB)
(11111111.
2.
PAGE 10-65
C-MESSAGE WEIGHING FILTER PROVIDES A FRE·
QUENCY RESPONSE CHARACTERISTIC WHICH SIM·
ULATES THE PRECEIVEO RESPONSE OF THE HUMAN EAR TO TELEPHONE NOISE.
en
II:
1&1
lII:
1&1
>
Z
o
U
~
DAC-78 COMDAC® COMPANDING D/A CONVERTER
SIGNAL TO QUANTIZING DISTORTION TEST CIRCUIT
EXTENSION TO SIGN PLUS 78dB DYNAMIC RANGE
EXTENDED RANGE OPERATION
When used as a D/A converter only, the DAC·76 range may
be extended from sign + 72dB to sign + 78dB by using the
encode output current to Insert additional levels halfway
between each step. By connecting 100 (+) to 10E(+) and
loo( -) to 10E( -), the ElD logic input functions as a fifth step
bit input. Full scale positive now becomes 111111111; full
scale negative is 0 111 11111. Each chord is divided into 32
steps instead of the former 16 steps, effectively increasing
dynamic range by 6dB.
OPEN fOR NOISE TEST
CLOSE fOR SIGNAL TEST
1. 8kHz SAMPLING CONDITIONS: 62p.SEC SAMPLE PERIOD,
62.6J,tSEC AID CONVERSION TIME.
2. AUDIO TEST ANALYZER CONTAINS A C-MESSAGE FILTER
AND A 3kHz FLAT FILTER.
OUTPUT COMPLIANCE EXTENSION CONNECTIONS
EXTENDED RANGE CONNECTIONS
±10V RANGE ENCODE/DECODE CONNECTIONS
REF-Ol
+IOV
±10V INPUT
~~.~n
IRREF)
DIGITAL INPUTS
:~~CT
~~ER&
Rl
2.5kn
---------- ~
REF-O'
±10V
Rn·
18.94kS!
IRREF'
--
ANALOG
OUTPUT
~-==~=~':::'I
±ov
11
'REF 12
R2
2.Skn
R12
R12
20Idl
20kI!
-15V
+'5V
IDEAL VALUES:
'REF'" 528pA
'FS = 2039.75,uA
COMPLIANCE EXTENSION USING AC COUPLED OUTPUT
SUMMARY TABLE FOR 3·CHORD BITS AND 5·STEP BITS
REF-01
+IOV
CHORD
R1118.9411:a
(RREf)
0
r-:!::~~~~~
11
2
4
1-0
R12
ZOkn
5
6
STEP
RANGE
(pA)
(pA)
STEP
(mY)
0.25
o to 7.75
0.625
o to 0.019
0.5
B.25 to 23.75
1.25
0.021 to 0.059
0.062 to 0.139
1.0
24.75 to 55.75
2.5
2.0
57.75 to 119.75
5.0
4.0
123.75 to 247.75
RANGE
(V)
0.144 to 0.299
10
0.309 to 0.619
0.639 to 1.259
255.75 to 503.75
20
16
519.75 to 1015.75
40
1.299 to 2.539
32
1047.75 to 2039.75
BO
2.619 to 5.099
B.O
-12V +12V
IDEAL VALUES:
'REF = 528~A
IFS = 2007.75pA
The accompanying table summarizes the new chord and
step characteristics obtained in the extended connection
shown above.
PAGE 10-86
DAC-76 COMDAC® COMPANDING D/A CONVERTER
CHORD
5
STEP
100
101
110
111
123.75
255.75
519.75
1047.75
_ _ _ _ _ _ .~~:._. _ _ _ _
0._5 ______
9._25_ _ _ ~~,__:.7=5---_:6=1"".7=5--=__1=31=_.7=5
0010
10.25
28.75
65.75
139.75
271.75
287.75
551.75
583.75
1111.75
1175.75
o
0000
3
0011
0100
000
001
0
8.25
010
011
24.75
1.5
11.25
·-----12.25
57.75
----
30.75
69.75 ---14-7-.7-5
303.75
615.75
1239.75
32.7=5---:::73=.7=5----1=5-=-5.=75:-----:c
3-:
19"'.7=5---6=-4=7.=75:-----:-:13"'03=-=.75
-~----~~--~~--~~----
_ _ _ _ _ _ 0101______ ~~_ _ _ _ _1_3.25 _ _ _ _3~?_5_____ 77.7~ _ _ 163.~.
6
0110
3
14.25
36.75
81.75
171.75
7
0111
3.5
15.25
38.75
85.75
4 ----16-.2-5---4-0.·7-5----89-.7-5--
------
1000
9
1001
10
1010
4.5
5
179.75
187.75
335.75
679.75
1367.75
351.75
711.75
1431.75
367.75
383.75
743.75
1495.75
775.7=5---1""5""59-.75
17.25
42.75
93.75
195.75
399.75
807.75
1623.75
·-18-.2-5--- 44.75'---""9=7=.7=5----:2=03-=-.=75:-----:41-=5-::.7'"'"5----=8"'"39=-.7=5=--- 1687.75
11
1011
5.5
19.25
46.75
101.75
211.75
431.75
871.7-5---17-51.75
12
1100
6
20.25
48.75
105.75
219.75
447.75
903.75
1815.75
13
1101
6.5
21.25
50.75
109.75
227.75
463.75
935.75
1879.75
14
1110
7
22.25
52.75
113.75----=2-=-35=-.7=5-
7.5
.50
23.25
54.75
2
117.75
._---15
1111
------STEP SIZE
479.75 ---9-=-6-::7.-=7""5---194-3.75
243.75
495.75
----,:-----16
999.75
32
2007.75
64
CHORD SIZE SUMMARY TABLE DECODE OUTPUT (SIGN BIT EXCLUDED)
CHORD ENDPOINTS
NORMALIZED
TO FULL SCALE
CHORD
o
2
CHORD ENPOINTS
IN.AWITH
2007.75pA F.S.
CHORD ENDPOINTS
AS A PERCENTAGE
OF FULL SCALE
CORD ENDPOINTS
INdB DOWN
FROM FULL SCALE
30
7.5
0.37%
-48.55
93
23.25
1.16%
-38.73
219
54.75
2.73%
-31.29
5.86%
-24.63
3
471
117.75
4
975
243.75
12.1%
-18.32
5
1983
495.75
24.7%
-12.15
49.8%
- 6.06
6
3999
999.75
8031
2007.75
~
U
C
C
II)
a:
III
I-
a:
>
III
Z
o
U
~
o
100%
DECODE OUTPUT EXPRESSED IN dB DOWN FROM FULL SCALE (SIGN BIT EXCLUDED)
CHORD
STEP
o
000
0000
3 4 5
6
001
010
011
100
101
110
111
-47.73
-38.18
-30.82
-24.20
-17.90
-11.74
-5.65
-5.13
0001
-72.07
-46.73
-37.51
-30.24
-23.66
-17.37
-11.22
2
0010
-66.05
-45.84
-38.88
-29.70
-23.15
-16.87
-10.73
-4.65
3
0011
-62.53
-45.03
-38.30
-29.18
-22.66
-16.40
-10.27
-4.19
4
0100
-60.03
-44.29
-35.75
-28.70
-22.21
-15.96
- 9.83
-3.75
0101
-58.10
-43.61
-35.24
-28.24
-21.77
-15.53
- 9.41
-3.33
6
0110
-56.51
-42.98
-34.75
-27.80
-21.38
-15.13
- 9.01
-2.94
7
0111
-55.17
-42.39
-34.29
-27.39
-20.96
-14.74
- 8.63
-2.58
8
1000
-54.01
-41.84
-33.85
-26.99
-20.58
-14.37
- 8.26
-2.19
9
1001
-52.99
-41.32
-33.44
-26.61
-20.22
-14.02
- 7.91
-1.84
10
1010
-52.07
-40.83
-33.04
-26.25
-19.87
-13.66
- 7.57
-1.51
11
12
1011
-51.25
-40.37
-32.66
-25.90
-19.54
-13.35
- 7.25
-1.18
1100------5-0.-49------3-9-.9-3-----32-.-29-----2-5-.5-7------19-.2-2-----1-3-.0-3-----=--6=-.9=3------0=-.8=7=---
13
1101
-49.80
-39.51
-31.95
-25.25
-18.91
-12.73
- 6.63
-0.57
14
1110
-49.15
-39.11
-31.61
-24.94
-18.61
-12.43
- 6.34
-0.28
15
1111
-48.55
-38.73
-31.29
-24.63
-18.32
-12.15
- 6.06
0
PAGE 10-67
II
DAC·78 COMDACiII COMPANDING D/A CONVERTER
DECODE OUTPUT EXPRESSED IN PERCENT OF FULL SCALE (SIGN BIT EXCLUDED)
CHORD
STEP
0
3
5
2
3
4
5
6
7
001
010
011
100
101
110
111
52.2
0
000
0000
0
0.411
1.23
2.88
6.18
12.7
25.9
0001
0.Q25
0.461
1.33
3.08
6.56
13.5
27.5
55.4
0010
0.050
0.511
1.43
3.27
6.96
14.3
29.1
58.6
0011
0.Q75
0.560
1.53
3.47
7.36
15.1
30.7
61.7
0100
0.100
0.610
1.63
3.67
7.76
15.9
32.3
64.9
0101
0.125
0.660
1.73
3.87
8.16
16.7
33.9
68.1
0110
0.149
0.710
1.83
4.07
8.55
17.5
35.5
71.3
0111
0.174
0.760
1.93
4.27
8.95
18.3
37.0
74.5
1000
0.199
0.809
2.03
4.47
9.35
19.1
38.6
77.7
80.9
1001
0.224
0.859
2.13
4.67
19.9
40.2
10
1010
0.249
0.909
2.23
4.87
10.1
20.7
41.8
84.1
11
1011
0.274
0.959
2.33
5.07
10.5
21.5
43.4
87.2
12
1100
0.299
1.01
2.43
5.27
10.9
22.3
45.0
90.4
13
1101
0.324
1.06
2.53
5.47
11.3
23.1
46.6
93.6
14
1110
0.349
1.11
2.63
5.67
11.7
23.9
48.2
15
1111
0.374
1.16
2.73
5.86
12.1
24.7
49.9
0.025
0.050
0.100
0.199
STEP SIZE
PAGE 10-88
9.75
0.398
0.797
1.59
96.8
100
3.19
DAC-7B
PMI
COMDAC®'COMPANDING D/A CONVERTER
®
FEATURES
DAC-78 TRANSFER FUNCTION
• Log Response Gives 12 Bit Accuracy Near Zero
The OAC-78 was originally designed for use in companding
telecommunications applications. It was noted that the
transfer function thus generated could also be used in a
large number of industrial control, attenuator or data
compression applications. The transfer function is in the
form X = k ("mY-1 ) where:
• Sign Magnitude Coding
• Multiple Outputs Allow Shared AID - D/A Conversion
• Tight Full Scale Tolerance Eliminates Calibration
• Low Full Scale Drift
• Multiplying Reference Inputs
X = analog output
k, m = scale factors
y = normalized digital input
• High Reliability
• Low Power Consumption
This was derived from a Bell system specification which has
the following function:
• Low Cost
y
GENERAL DESCRIPTION
The OAC-78 monolithic O/A converter provides a linear
approximation to logarithmic response curve of the form:
K (e my - 1) where K and m are scale factors and y is the
normalized digital input. The curve is implemented by using
3 bits to select one of 8 straight line segments (chords) and
4 bits to select one of 16 binary steps within each chord.
A sign bit is provided to select output signal polarity and
an encode/decode operation. Accuracy is assured by specifying chord endpoint values, step nonlinearity and monotonicity over the full operating temperature range. Typical applications include: data compression, transducer linearization (e.g.,
photo and pin diodes), light and audio attenuators, and servo
positioning systems. For telecommunications applications
please refer to the OAC-88 data sheet.
EQUIVALENT CIRCUIT AND PIN CONNECTION
DIAGRAM
STEP
INPUTS
CHORD
INPUTS
87 86 8584
8382 81
sa
= In(1 + /LX)
In(1
where /L
= 255
+ /L)
Solving for D/A converter operations gives:
5.55 ... Y
X=E~ -1
256
which after adjustment for the linear approximation effects
yields
PIN CONNECTIONS
E/D
& ORDERING INFORMATION
ENCODE/DECODE SELECT"
1'- ENCODE
SIGN BIT INPUT:
1 = POSITIVE
DECODe OUT E 0 S8
MOST SIGNIFICANT CHORD
BIT INPUT
DeCODE OUT E '0 sa
01
ENCODE OUT: E"D S8
10
ENCODE OUT. E '0 S8
11
SECOND STEP BIT INPUT
THIRD STEP BIT INPUT
LEAST SIGNIFICANT STEP
BIT INPUT
POSITIVE POWER SUPPl Y
VLe
{10
NEGATIVE POWER SUPPLY
NEGATIVE REFERENCE
INPUT
POSITIVE REFE:.RENCE
INPUT
THRESHOLD CONTROL
18-PIN HERMETIC DUAL·IN·LINE
(X·Suffix)
CHORD
ACCURACY (STEP)
±1/4
OAC-78EX
±1/2
OAC-78FX
±1
OAC-78GX
v·,
a:
This equation gives a normalized number which when
multiplied by the smallest step current (.25/LA for 528/LA IREF)
will give a good approximation of the input. Tables are
given in the data sheet with which the exact output may be
calculated.
SECOND CHORD BIT INPUT 4
LEAST SIGNIFICANT
CHORD BIT INPUT ~
MOST SIGNIFICANT STep
sir INPUT
v-
1/1
X = O.00365(EO.0425Y -1 )(Sign Y)
TEMP
INO
INO
INO
t All listed partsareavailable with 160 hour burn-in. See Ordering Information,
Section 2.
PAGE 10-69
....a:11/
11/
~
o
(J
c(
c
DAC-7B COMDAC@COMPANDING D/A CONVERTER
ABSOLUTE MAXIMUM RATINGS
V+ Supply to V- Supply .••...........•....•........ 36V
VLC Swing ••....•.•...............•.. '" V- plus 8V to V+
Analog Current Outputs •....••. V- plus 8V to V- plus 36V
Reference Inputs ......•..•.•....•••........... V- to V+
Reference Input Differential Voltage ..............•. ±18V
Reference Input Current .•...•..•...........•.... 1.25mA
Logic Inputs •...........•...... V- plus 8V to V- plus 36V
Operating Temperature ..............•... -25°(; to +85°C
Storage Temperature ..•........•....... -65°Cto+150°C
Dice Junction Temperature ....•...•.... -65°C to +150°C
Power Dissipation ...... . . . . . . . . • • • . • • • • • . . . . . . .. 500mW
Derate above 100°C ...•.....•......•....•..... 10mW/oC
Lead Soldering Temperature .•...•.....•... 3DO°C (60 nS)
NOTE: Absolute ratings apply to both DICE and packaged parts unless
otherwise noted.
ELECTRICAL CHARACTERISTICS at Vs = ±15V, IREF = 528/LA, -25°C
~ TA ~ TA:S +85°C, and all 4 outputs, unJess
otherwise noted.
DAC-7B-E
PARAMETER
SYMBOL
Resolution
CONDITIONS
DAC-7B-G
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
72
72
72
72
72
72
72
72
72
Monotonicity
Sign Bit + or-
Chord Endpoint Accuracy
Chord Zero
at IFS =
1~
1~
1~
Step
2007.75~A
Error relative to ideal values
at IFS =
±1/2
2007.75~
Additional output
Encode Offset Current
3/B
encode/decode = 1
Settling Time (Note 1)
t,
To within ±1/2 step
Settling Time in Chord Zero
Tsco
To within ±1/2 step
Full Scale Drift (C,)
Full scale current change
10 (+) -10 (-)
Input Code 1111111
Zero Scale Current (Note 2)
IzS
000 0000 input
Measured at selected output
Leakage of output disabled
by ElD and SB
Step Accuracy
Error relative to ideal values
at IFS = 2007.75~A
Step Accuracy
All Chords Other Than Zero
500
see
note 1
-5
Decode or encode pair
Disable Current (All bits high)
(Note 2)
Chord Zero
5/B
1/4
500
:51/2 step
Full Scale Symmetry Error
(Note 2)
1/2
±1
1/2
3/4
114
500
±1/16 ±1/10
Full temperature range
Voc
dB
Steps
Error relative to ideal values
Chord Endpoint Accuracy
All Chords Other Than Zero
UNITS
Steps
8 chords with 16 steps each
Dynamic Range
Output Voltage Compliance
DAC-78-F
MIN
+IB
±1/10
-5
±1'h
Step
1/2
3/4
Step
500
see
note 1
ns
±1/2
Step
+IB
Volts
500
±1/4
+IB
±1/10
-5
ns
±1/40
±I/B
±1/40
±1/4
±1/20
±1/2
Step
1/40
liB
1/40
1/4
1120
112
Step
5.0
100
5.0
100
5.0
100
nA
±1
Step
±1'h
Step
±1/4
Error relative to ideal values
at IFS = 2016~A
±1/2
±1/2
Output Current Range
IFSR
Logic Input Levels, Logic "0"
V'L
VLC = OV
Logic Input Levels, Logic "1"
V1H
VLC ;;= OV
Logic Input Current
I'N
V,N=-5Vto+1BV
Logic Input Swing
V,s
V-=-15V
Reference Bias Current
1'2
-3.0
Reference Input Slew Rate
dl/dt
0.25
2.0
4.2
±1
o
2.0
O.S
2.0
4.2
O.B
2.0
+IB
-12.0
4.2
rnA
O.B
Volts
Volts
2.0
120
-5
2.0
120
-5
+IB
-3.0
-12.0
0.25
120
-5
+IB
-3.0
-12.0
~A'
Volts
~A
mAl~s
0.25
Power Supply Sensitivity Over
PSSIFs+
V+ = 4.5 to ISV
±1/20 ±1/2
±1/20 ±112
±1/20 ±1/2
Step
Supply Range (Refer to
---P-S-S-'-I=---v---=---10-.-BV-to---l-SV--------±-1/-1-0-±-I-I-2---±-I-I-l0--±-1-/2----±-I-/l-0--+_-1/-2---S-te-'pCharacteristic Curves)
F51+
Power Supply Current
1-
1+
1-
Vs = +5V, -15V, IFS = 2.0mA
2.7
-6.7
5.5
-12
2.7
-6.7
5.5
-12
2.7
-6.7
5.5
-12
rnA
Vs = ±15V,IFS = 2.0mA
2.7
-6.7
5.75
-12
2.7
-6.7
5.75
-12
2.7
-6.7
5.75
-12
rnA
NOTES:
1. In a companding DAC the term LSB is not used because the step size
within each chord is different. For example, in the first chord around
zero (Col step size is O.5",A, while in the last chord near full scale {C71
step size is 64",A. Settling time varies for each of the chord bits and step
bits and a maximum specification in misleading.
2.
Current specifications relate to differential currents between (+) and
{-I output leads. At the selected outputs, equal idle currents are present
simultaneously on both current output leads.
PAGE 10-70
DAC-78 COMDAC@ COMPANDING DlA CONVERTER
ELECTRICAL CHARACTERISTICS at Vs
= ±15V,
IREF
= 528/lA, -25°C :5 TA :5 +85°C,
and for all 4 outputs, unless
otherwise noted. (Continued)
PARAMETER
SYMBOL
Power Dissipation
Full Scale Current Deviation
From Ideal Deviation
(See Tables)(Note 2)
DAC-78-E
MIN TYP MAX
CONDITIONS
DAC-78-F
MIN TYP MAX
DAC-78-G
MIN TYP MAX
UNITS
PD
Vs +5V. -15V
114
207
114
207
114
207
mW
PD
Vs =±15V
141
262
141
262
141
262
mW
IFS(D)
VREF 10.000V. TA = 25'C
±1/2
±1
±1'h
Step
IFS(E)
Rll = 19.53kO
R12 = 20kn
±1/2
±1
±11h
Step
Idle Current (Note 2)
10
NOTES:
1. In a companding DAC the term LSB is not used because the step size
within each chord is different. For example, in the first chord around
zero (Co) step size is 0.5p.A, while in the last chord near full scale (G,)
10
10
p.A
2. Current specifications relate to differential currents between (+) and
(-) output leads. At the selected outputs, equal idle currents are present
simultaneously on both current output leads.
step size is 641LA. Settling time varies for each of the chord bits and step
bits and a maximum specification in misleading.
DICE CHARACTERISTICS
1. E/D
2.S.B.
3. BIT 1 (MSB)
4. BIT2
5. BIT3
6. BIT4
7. BITS
8. BIT6
9. BIT 7 (LSB)
10. VLC
11. VR (+)
12.
13.
14.
15.
16.
17.
18.
VR (-)
VIOE(+)
10E (-)
100(+)
100(-)
V +
~
U
c
c
til
DIE SIZE 0.123 X 0.085 inch
Reier to Secllon 2 lor addiliona' DICE Inlormatlon.
a:
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PAGE 10-71
DAC-78 COMDAce COMPANDING DlA CONVERTER
ELECTRICAL CHARACTERISTICS at Vs
= ±15V.
IREF
= 528"A.
TA
= 25°C and
all 4 outputs. unless otherwise noted.
DAC-78-N
PARAMETER
SYMBOL
(NOTE 3)
LIMIT
CONDITIONS
±128
8 chords with 16 steps each
Resolution
±128
UNITS
Steps MIN
72
72
dBMIN
128
Steps MIN
±1I2
±1
Step MAX
±1
±1V2
Step MAX
Additional output
encode/decode = 1
114
3/4
114
3/4
Step MIN
Step MAX
-5
-5
+18
+18
Volts MIN
Volts MAX
20 log (1 7. ,,;110. ,)
Sign Bit + or -
Chord Endpoint Accuracy
Chord Zero
Error relative to ideal values
at I FS = 2007.75,.A
Error relative to ideal values
at I FS = 2007.751'A
Encode Current
(NOTE 4)
LIMIT
128
Dynamic Range
Monotonlclty
Chord Endpoint Accuracy
All Chords Other Than Zero
DAC-78-G
Output Voltage Compliance
Voc
Full scale current change
0;112 step
Full Scale Symmetry Error
(Note 2)
10 +-1 0 -
Decode or encode pair
Input Code 111 1111
±1I4
±1/2
Step MAX
Zero Scale Current (Note 2)
Izs
Measured at selected output
0000000 input
114
1/2
Step MAX
Disable Current (All bits high)
(Note 2)
lOIS
Leakage of output disabled
by E/Dand SB
100
100
nAMAX
±1I2
±1
Step MAX
±1
±1Y2
Step MAX
Step Accuracy
Chord Zero
Error relative to ideal values
at I FS = 2007.751'A
Step Accuracy
All Chords Other Than Zero
Error relative to Ideal values
at I FS = 20161'A
Output Current Range
'FSR
Logic Input Levels. Logic "0"
V,L
VLC=OV
Logic Input Levels, Logic "1"
V ,H
VLC=OV
Logic Input Current
liN
V,N = -5V to +18V
-5
Logic Input Swing
V'S
Reference Bias Current
I,.
Power Supply Sensitivity Over
Supply Range (Refer to
Characteristic Curves)
PSSI F8PSSI F81+
Power Supply Current
Full Scale Current Deviation
From Ideal Deviation
(See Tables) (Note 2)
V-=-15V
4.2
4.2
mAMAX
0.8
0.8
Volts MAX
2.0
2.0
Volts MIN
120
120
I'AMAX
-5
Volts MIN
Volts MAX
+18
+18
-12.0
-12.0
I'A
V+ = 4.5 to 18V
±1I2
±1/2
Step MAX
V-=-10.8Vto-18V
±1I2
±1/2
Step MAX
5.5
-12
mAMAX
Vs =+5V.-15V.I FS =2.0mA
5.5
-12
1+
1-
Vs= ±15V,I FS = 2.0mA
5.75
-12
5.75
-12
mAMAX
IFSD
VAEF 10.000V. TA = 25° C
±1
±1V2
Step MAX
IFSE
R11 = 19.53kO
R12 =20kO
±1
±1V2
Step MAX
1-
TYPICAL CHARACTERISTICS at Vs = ± 15V. and TA = 25° C. unless otherwise noted.
DAC-78-N
DAC-78-G
TYP
TYP
UNITS
To within ±1/2 step
500
500
nS
TSCD
To within ± 112 step
500
500
nS
Full Scale Drift (C 7)
~IFS
Full temperature range
±1I10
±1I10
Step
-Reference Input Slew Rate
dl/dt
PARAMETER
SYMBOL
CONDITIONS
Settling Time (Note 1)
ts
Settling Time in Chord Zero
Power Dissipation
0.25
0.25
mA/I'S
Po
Vs +5V. -15V
114
114
mW
Po
V s =±15V
141
141
mW
10
10
I'A
Idle Current (Note 2)
NOTES:
1. In a companding DAC the term LSB is not used because the step size within
each chord· is different. ·For example, in the first chord around zero (Col
step size Is 0.51'A, while in the last chord near full scale (C 7 ) step size Is
64p.A. Setting time varies for each of the chord bits and step bits and a
maximum specification is misleading.
2. Current specifications relate to differential currents between (+) and (-)
output leads. At the selected outputs, equal idle currents are present
simultaneously on both current output leads.
3. See CAC-78F for typical values.
4. See CAC-78G for typical values.
PAGE 10-72
DAC-78
COMDAC~
COMPANDING DlA CONVERTER
OUTPUT CURRENT DC TEST CIRCUIT
Rl
LINE SELECTION TABLE
TEST
GROUP
+VREF
Rll
18.94k~!
(RREF)
"
OUTPUT
MEASUREMENT
1
1
10E[+1
[E01/R11
a
10E[-1
IEol/R21
4
R1 = R2 = R3 = R4 = 2.5k!l
SIGN
BIT
2
3
R12
20k~,
ENCODE!
DECODE
a
a
a
10D[+1
[E02/R31
10D[-)
I E02/R4)
NOTE: Accuracy is specified in the test circuit using the tables below
to be within the specified proportion of a step at the maximum value
in each chord. Monotonic operation is guaranteed forall input codes.
·VREF [5 ADJUSTED BEFORE TESTING EACH DEVICE
TO PROVIDE IDEAL FULL SCALE OUTPUT CURAENT.
CONDENSED CURRENT OUTPUT TABLES (IREF= 5281'A)
IDEAL DECODE (DAC) OUTPUT CURRENT IN MICROAMPS AT CHORD ENDPOINTS
CHORD
STEP
o
0000
15
1111
o
3
4
000
001
010
011
100
101
110
111
o
8.25
24.75
57.75
123.75
255.75
519.75
1047.75
7.5
23.25
54.75
117.75
243.75
495.75
999.75
2007.75
4
8
16
32
64
0.50
STEP SIZE
6
IDEAL DECODE (ADC) OUTPUT CURRENT IN MICROAMPS AT CHORD ENDPOINTS
CHORD
STEP
3
en
4
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w
6
000
001
010
011
100
101
110
111
o
0000
0.25
8.75
25.75
59.75
127.75
263.75
535.75
1079.75
15
1111
7.75
23.75
55.75
119.75
247.75
503.75
1015.75
2039.75
4
8
16
32
64
STEP SIZE
0.50
These tables may be extended to include all of the encode/decode currents (ideal with IREF = 5281'A) by multiplying any of the numbers in the normalized tables by O.251'A.
FULL SCALE SYMMETRY ERROR
The difference between loo( -) and loo( +) or the difference
between 10E( -) and 10E( +) at full scale output.
SPECIFICATION PARAMETER DEFINITIONS
OUTPUT VOLTAGE COMPLIANCE
FULL SCALE DRIFT
The maximum output voltage swing at any current level
which causes < '12 step change in output current.
The change in output current over the full operating
temperature with VREF = 10.000V, R11 = 18.94kO, and
R12=20kO.
IDEAL OUTPUT CURRENT
The difference between the ( + ) and ( - ) currents (encode or
decode) at any code.'
ENCODE OFFSET CURRENT (AID CONVERSION)
An offset current added to the DAC output to move the
encode decision point to mid-value (I.e., the 0 - 1 transition
should occur at the 1/2 I step point).
CHORDS
Groups of linearly-related steps in the transfer function.
Also known as segments.
PAGE 10-73
Ii:w
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oo
c
C
DAC-78 COMDAC"' COMPANDING DlA CONVERTER
CHORD ENDPOINTS
The maximum code in each chord. Used to specify accuracy.
STEPS
Increments in each chord which divides it into 16 equal
levels.
OUTPUT LEVEL NOTATION
Each output current level may be designated by the code
Ic,s where C = chord number and S = step number. For
example. 10•0 = zero scale current; 10,1 = first step from zero;
10,15= endpoint offirst chord (Co); 17,15=full scale current. For
encode operation Ic,s = 0.5 [2 c (S + 17) -16.5]. For decode
operation Ic,s = 0.5 [S + 16.5) -16.5] based on IREF = 528/'A.
When the DAC is used in the feedback loop of a successive approximation ADC the DAC outputs are used as
decision levels to determine the edges of the quantizing
bands. When the DAC is used in the decode mode it
follows that the outputs must correspond to the center of
the quantizing bands. Thus the encode mode output must
exceed the decode mode output by one-half step. See AN
39 for further explanation.
-
BASIC ENCODE (ADC) CONNECTIONS
.!:5V ANALOG INPUT
r--
*'
G~~~ND
I
~.~k
R1
2.5k
SINGLE
DYNAMIC RANGE
ENDED
Ratio of full scale current to step size in chord zero expressed in dB.
INPUTS
ANALOG-TO·
DIGITAL
CONVERSION
DIGITAL
OUTPUTS
lOGIC
SIGN
BIT
~~lcHORO
I r-.=
BASIC ENCODE OPERATION
(COMPRESSING AID CONVERSION)
BITS
1
STEP
BITS
ENCODE DECISION LEVELS
Compressing AID conversion with the DAC-78 requires a
comparator, an exclusive-or gate, and a successive
approximation register - the usual elements in any sign·
plus-magnitude AID converter. However, a compressing
ADC has one signficant difference from regular AID con·
verters.
VnEF
123456789
',OV
R12
20ku
In a conventional (linear converter), the step size is a constant percentage of full scale, but in a compressing AID
converter, the step size increases as the output changes
from zero scale to full scale.
-15V
+15V
IDEAL ENCODE (AID) LEVEL (SIGN BIT EXCLUDED) IN MICROAMPS (IREF = 528!
Z
o
U
IDEAL DECODE OUTPUT CURRENT IN MICROAMPS (SIGN BIT EXCLUDED)
CHORD
STEP
5
000
0000
0001
0.5
001
010
011
100
101
110
111
8.25
24.75
57.75
123.75
255.75
519.75
1047.75
1111.75
9.25
26.75
61.75
131.75
271.75
551.75
10.25
28.75
65.75
139.75
287.75
583.75
1175.75
1.5
11.25
30.75
69.75
147.75
303.75
615.75
1239.75
12.25
32.75
73.75
155.75
319.75
647.75
1303.75
0101
2.5
13.25
34.75
77.75
163.75
335.75
679.75
1367.75
0110
3
14.25
36.75
81.75
171.75
351.75
711.75
1431.75
0111
3.5
15.25
38.75
85.75
179.75
367.75
743.75
1495.75
16.25
40.75
89.75
187.75
383.75
775.75·
1559.75
1623.75
0010
0011
4
~
ilREF~528~A)
0100
1000
1001
4.5
17.25
42.75
93.75
195.75
399.75
607.75
10
1010
5
18.25
44.75
97.75
203.75
415.75
839.75
1687.75
11
1011
5.5
19.25
46.75
101.75
211.75
431.75
871.75
1751.75
12
1100
6
20.25
48.75
105.75
219.75
447.75
903.75
1815.75
13
1101
6.5
21.25
50.75
109.75
227.75
463.75
935.75
1879.75
22.25
52.75
113.75
235.75
479.75
967.75
1943.75
7.5
23.25
54.75
117.75
243.75
495.75
999.75
2007.75
2
4
8
16
32
84
14
1110
15
1111
STEP SIZE
.50
PAGE 10-75
DAC-78 COMDAC"'COMPANDING D/A CONVERTER
with V+ = 15V, RREF = 15V1528j.1A, or 28.4kn. When using a
power supply as a reference, R11 should be two resistors,
R11A and R11B, and the junction should be bypassed to
ground to provide decoupling.
DECODE TRANSFER CHARACTERISTIC
(D/A CONVERSION)
ANALOG
OUTPUT 1+)
ElO 58 81 82 83 84 85 86 87
pos FULL SCALE
(+ ) ZERO SCALE + 1 STEP
(+ ) ZERO SCALE
( - ) ZERO SCALE
(- ) ZERO SCALE + 1 STEP
NEG FULL SCALE
DIGITAL
INPUT t+)
DIGITAL
INPUT (-)
ANALOG
OUTPUT 1-)
0
5.019V
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VAEF
DIGITAL INPUTS
BASIC REFERENCE CONSIDERATIONS
Full scale output current is ideally 2007.75j.1A when the
reference current is 528j.1A in the decode mode, due to a
multiplier of 3.803. In the encode mode it is 2039.75j.1A
because the additional 1/2 step adds 32j.1A to the output. A percentage change in IREF caused by changes in VREF or RREF
will produce the same percentage change in output current.
The large step size at full scale allows the use of inexpensive references in many applications. In some situations
VREF may even be the positive power supply. For example,
VREF
IREF = RREF
IDEAL VALUES:
'REF = 528pA
IFS = 2007.75iJA,
NOTE: THIS CONfiGURATION WILL DECODE 24 CHANNELS
PHOTODIODE LINEARIZING CIRCUIT
L-__________~r-~~-.,~====!:CM~
CMP-
PAGE 10-76
0.0012
ov
ov
-0.0012
-5.019V
BASIC DECODE CONNECTIONS
+'ov
Eo
DAC-78 COMDAC"COMPANDING D/A CONVERTER
REFERENCE AMPLIFIER OPERATION
REFERENCE AMPLIFIER SETUP
The DAC-78 is a multiplying D/A converter in which the output current is the product of the normalized digital input and
the input reference current. The reference current may be
fixed or may vary from nearly zero to + 1.OmA. The fu II scale
output current is a linear function of the reference current
and is given for all four outputs in the figures above.
REFERENCE RECOMMENDATIONS
For most applications a +10.OV reference, such as the PMI
REF-01, is recommended for optimum full scale
temperature coefficient performance.
negative voltage range are reduced by an amount equivalent
to the difference between -15V and the V - supply in use.
Operation with V + between + 5V and + 15V affects VLC and
the reference amplifier common mode positive voltage
range in the same manner.
OUTPUT VOLTAGE COMPLIANCE
The DAC-78 has true current outputs with wide voltage compliance enabling fast drive of a variety of single ended and
balanced loads. Positive voltage compliance is +18V and
negative voltage compliance is -5.0V with IREF = 5281'A
and V = -15V. Negative voltage compliance Voe( -) for
other values of IREF and V-may be obtained from the table,
or calculated as follows:
Voe( -) min =(V-) + (2 'REF X 1.6k{l) +8.4V
Output voltage compliance can be extended in both encode
and decode modes using the connections shown below.
POWER SUPPLY CONSIDERATIONS
POWER SUPPLIES
NEGATIVE OUTPUT VOLTAGE COMPLIANCE Vee< - )
Power supply current drain is relatively independent of
voltage and temperature and completely independent of the
logic input states.
v-
When operating with V- between -15Vand -11V, output
negative voltage compliance, Voe( -), reference input
amplifier common mode voltage range, and logic input
1_0mA
2_0mA
4.0mA
-12V
-2.BV
-2.0V
-O.4V
-1SV
-S.BV
-S.OV
-3.4V
-1BV
-B.BV
-B.OV
-6.4V
II
~
STANDARD OUTPUT CONNECTIONS
Q
II)
a:
UI
~
2.5kn
VREF
UI
+1OV
TOA/D
"---~CONVERSION
LOGIC
~
o
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~
"2
2Ok!l
,sv
>-----oOUTPUT
STANDARD ENCODE/DECODE CONNECTIONS REQUIRE
IVoc(-)';;;;; IVAmaxl
PAGE 10-77
DAC-78 COMDAC"COMPANDING D/A CONVERTER
COMPLIANCE EXTENSION CONNECTIONS
6kn
R1
SERVO POSITIONING SYSTEM
.p
I/O
PAGE 10-78
DAC-l00/DAC-lm
PMI
lO-BIT D/A CONVERTERS
FEATURES
choice of linearity and tempco options is provided to allow
price/performance optimization.
• Complete ........................ Internal Reference
• Flexible ............................ 0 to 2mA Output
• Fast Settling ....... 225nsec (8 Bits), 375nsec (10 Bits)
• Stable . . . . . . . . . . . .. Tempcos to ± 15ppm/o C Maximum
• O°C/ +70°C, -25°C/ +85°C, -55°C/ +125°C Models
Available
• TTL Compatible Logic Inputs
• Wide Supply Range ..................... ±6V to ±18V
• 8 and 10 Bit Versions Available
• MIL-STD-883 Class B Processing Models Available
• Low Cost 03, 04 Series
The small size. wide operating temperature range. low power
consumption and high reliability construction make the
DAC-100 ideal for aerospace applications .. Other applications include use in servo-positioning systems. X-V plotters.
CRT displays. programmable power supplies. analog meter
movement drivers. waveform generators and high speed
analog-to-digital converters. The DAC-101 is used in similar
applications with limited temperature range requirements.
PIN CONNECTIONS
GENERAL DESCRIPTION
The DAC-100/DAC-101 are complete 10-bit resolution digitalto-analog converters constructed on two monolithic chips in
a single 16-pin DIP. Featuring excellent linearityvs. temperature performance. the DAC-100/DAC-101 include a low
tempco voltage reference. ten current source/switches and a
high stability thin-filmR-2R ladder network. Maximum application flexibility is provided by the fast current output and by
matched bipolar offset and feedback resistors which are
included for use with an external op amp for voltage output
applications. Although all units have 10-bit resolution. a wide
16 PIN HERMETIC
DUAL·IN·LINE
(Q·Suffix)
•
...Iii
8
~
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c
(I)
SIMPLIFIED SCHEMATIC
II:
W
m. m7 mB m9
, - - - - - - - - - OIGITAL LOGIC INPUTS
~I
V+
~2
~3
~4
~5
lII:
W
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O~f=r=i=13~~~12~~I~I~~~'O~~~~~~rt~~~~~~~~==~~~
3
v-
RB
6.12kH
I.
"FOR lOV OR ;!.5V OPERATION,
RS
BIPOLAR REF
RS = 4.88kS"l (PACKAGE Q3,
06, a7t
FOR 5V OR !:2.5V OPERATION,
Rs '" 2.4411.0 (PACKAGE Q4,
06, as)
PAGE 10-79
RB
Z
o
ANALOG
OUTPUT
U
~
DAC-100/DAC-10110-BIT D/A CONVERTERS
ELECTRICAL CHARACTERISTICS at Vs = ± 15V, -25° C:::; T A :::; +85° C for 07, 08 devices; 0° C:::; T A :::; +70° C; for 03 and
04, -55°C:::; T A :::; +125°C for 05 and 06 devices and TA = 25°C for DAC-100 (All), unless otherwise noted.
PARAMETER
SYMBOL
DAC-l00
CONDITIONS
DAC-l0l
Resolution
Nonlinearity
(For nonlinearity/tempeD
combinations, see Ordering
Information.)
NL
NL
NL
NL
(±1/2LSB-l0 bits)
(±1/2LSB - 9 bits)
(±1/2LSB - 8 bits)
(±3/4LSB - 8 bits)
ABC-
0-
Tc
Full Scale Tempco
(See Full Scale Test Circuit)
MIN
TYP
MAX
10
10
10
Bits
±0.05
±0.1
±0.2
±0.3
%FS
%FS
%FS
%FS
±15
±30
±60
±120
ppm/'C
ppml"C
ppm/'C
ppml"C
ppml"C
375
300
225
150
100
ns
ns
ns
ns
ns
ns
10
11.1
V
5
5.55
V
0.013
0.02
%FS
EO
FO
GO
-A
-B
-C
Tc
Tc
Tc
-0
ALL
Settling Time TA = 25' C
±120
ALL
ALL
ALL
ALL
ALL
ts
ts
ts
ts
ts
to±0.05% FS
to±O.I% FS
to±0.2% FS
to±0.4% FS
to±0.8% FS
FFR
Connect FS Adjust to V10V Models (03, 05, 07)
(See Full Scale Test Circuit)
5V Models (04, 06, 08)
Y,N = O.OV
(See Full Scale Test Circuit)
ALL
Full Range Output Voltage
(Limits guarangee adjustability
to exact 10.0 (5.0)V with a
2000 Trimpot@! between
Adjust and V-
Zero Scale Output Voltage
Vzs
Logic Inputs: High
V 1NH
Logic Inputs: Low
V 1NL
ALL
V,N = 2.1V
Measured with respect to
output pin
Measured with respect to
output pin
ALL
EO/FO
GO
ALL
ALL
ALL
ALL
Logic Input Current, Each Input
liN
Y,N = 0 to +6V
ALL
ALL
Logic Input Resistance
R'N
V,N =Oto+6V
ALL
ALL
Logic Input Capacitance
C 'N
ALL
ALL
Output Resistance
Ro
ALL
ALL
Output Capacitance
Co
200
2.1
UNITS
V
0.7
V
~A
3
mO
500
kO
pF
13
ALL
ALL
Applied Power Supplies: V+
Linearity within specification
ALL
ALL
+6
+18
Applied Power Supplies: V-
Linearity within specification
ALL
ALL
-6
-IB
V
ALL
ALL
±0.10
% perVoJt
EO
200
300
BO
100
250
350
rnW
mW
rnW
mW
EO
FO/GO
10.0
12
B.33
rnA
rnA
rnA
EO
-10.0
-B.33
-12
mA
rnA
mA
Power Supply Sensitivity
Pss
Vs +±6Vto±18V
Power Consumption
Po
Po
Po
Po
Vs =±15V
Vs= ±6V
Vs =±15V
Vs= ±15V
03,04
03,04
05, 06, 07, OB
J+
J+
1+
Vs =+15V
Vs =+15V
Vs =+15V
03,04
Positive Supply Current
Negative Supply Current
1JJ-
Vs =-15V
Vs =-15V
Vs =-15V
FO/GO
05, 06, 07, OB
03,04
05,06,07,08
FO/GO
PAGE10-BO
200
250
pF
V
DAC-100/DAC-10110-BIT D/A CONVERTERS
ABSOLUTE MAXIMUM RATINGS (Note 2)
V+ Supply to V- Supply ...................... 0 to +36V
V+ Supply to Output .......................... 0 to + 18V
V- Supply to Output .......................... 0 to -18V
Logic Inputs to Output ...................... -1V to +6V
Power Dissipation (Note 1) ...................... 500mW
Operating Temperature Range
03,04 & All DAC-101 ................... O°C to +70°C
All others .......................... -55° C to + 125° C
DICE Junction Temperature. . . .. . . . . .. -25° C to + 150° C
Storage Temperature Range. . . . . . . . . .. -65° C to + 150° C
Lead Temperature (Soldering) .......... +300° C (60 sec)
NOTES:
1. Rating applies to ambient temperature of 1000 C. Above 1000 C, derate at
10mWI"C.
2. Ratings apply to DICE and packaged parts, unless otherwise noted.
ORDERING INFORMATIONt
N.L.**
%FS
MAX.
TEMPCO"
ppm/oC
MAX.
MILITARY TEMPERATURE
Vo = ±SV/10V
VO=±2.SV/SV
INDUSTRIAL TEMPERATURE
VO=±SV/10V
Vo = ±2.SV/SV
±O.OS
±1S
DAC100AA07'
DAC100AAOS'
±O.OS
±30
DAC100AB07'
DAC100ABOS'
±O.OS
±60
DAC100ACOS'
DAC100AC06'
DAC100AC07'
DAC100ACOS'
±O.10
±30
DAC100BBOS'
DAC100BB06'
DAC100BB07'
DAC100BBOS'
DAC100BCOS'
DAC100BC06'
DAC100BCQ7'
DAC100BCOS'
±O.10
±60
±O.10
±120
±O.20
±60
±O.20
±120
±O.30
±120
COMMERCIAL TEMPERATURE
VO=±SV/10V
Vo = ±2.SV/SV
DAC100AC03
DAC100AC04
DAC100BC03
DAC100BC04
DAC101EO
DAC100CCOS'
DAC100CC06'
DAC100CCQ7'
DAC100CCOS'
DAC100CCQ3
DAC100CCQ4
DAC101EO
DAC100DD07'
DAC100DDOS'
DAC100DD03
DAC100DD04
DAC101FO
t All
c
i
*These devices supplied with MfL-STO-883 Class-B Processing as standard - No suffix necessary.
listed parts are available with 160 hour burn-in. See Ordering Information, Section 2.
** Part number construction: The 1st
II
ietter following DAC-100 (A-D) refers to the non-linearity specification; the 2nd letter (A-D) refers to the full-scale tempeo; the
letter Q refers to the package; and the end numeral indicates the output voltage and temperature.
~
c
II)
I!:
1&1
lI!:
DICE CHARACTERISTICS
1&1
>
Z
o
U
~
DIE SIZE 0.090
x 0.057 Inch
DIE SIZE 0.080 x 0.067 Inch
2.
3.
4.
5.
6.
1.
a.
9.
10.
11.
12.
1. Aa
2.
3.
15.
1s.
VOUTPUT
FULL SCALE ADd
A.
R - Pad, are connected to Ilmllarly
marked padl on DAI-01
NOTE: Pads 4 - 14. See CAI-01
Refer 10 Secllon 2 for additional DICE Informallon
PAGE 10-81
VOUTPUT
BIT 10 (LSB)
BIT9
BITa
BIT 1
BITs
BITS
BIT4
BIT3
BIT2
13. BIT 1 (MSB)
14. V+
R - Pad, are connected to
Ilmllarly marked padl
on DAR-01
NOTE:
Pads 1, 2,15,16, See DAR-01
DAC-100/DAC-10110-BIT D/A CONVERTERS
ELECTRICAL CHARACTERISTICS at 25° C; forthe R2R Ladder Network comprised of Rl-R8, R12, R34, R23, R45 and R5S
when connected to an ideal DAI-01.
DAR·01·N
PARAMETER
CONDITIONS
Nonlinearity
VRI =3.2V
MIN
TYP
-
ELECTRICAL CHARACTERISTICS
MAX
DAR·01·G
MIN
±0.035
TVP
DAR·01·GR
MAX
-
MIN
TVP
±0.05
MAX
UNITS
±0.1
%
at 25"C in common to all grades; VRl =3.2V, unless otherwise noted.
DAR·01
PARAMETER
CONDITIONS
MIN
MAX
UNITS
Aeslstance AI
Absolute Measurement
2.56
3.84
kO
Aatlo RCI to AI
Ideal = 1 to 1
-1.0
+1.0
%
Aatio AI to ASI
Ideal = 1.31147 to 1
-1.0
+1.0
%
Aatio AI to AS2
Ideal = 1.31147 to 1
-1.0
+1.0
%
Aatlo AB to AI
Ideal = 1.9125 to 1
-1.0
+1.0
%
TYPICAL ELECTRICAL CHARACTERISTICS
TVP
in common to all grades.
DAR·01
PARAMETER
CONDITIONS
Absolute Temperature Coefficient
All Aesistors
Tracking Temperature Coefficient
All Aesistors with Aespect to AI
ELECTRICAL CHARACTERISTICS
MIN
SYMBOL CONDITIONS
Nonlinearity
MIN
TVP
YMCA
Vs= ±15V
ELECTRICAL CHARACTERISTICS
UNITS
ppm/'C
3.0
ppm/'C
DAI·01·G
MAX
MIN
TVP
6.600
6.825
DAI·01·GR
MIN
MAX
TVP
±0.10
±0.05
Vs= ±15V
Internal Aeference
Voltage
MAX
at 25"C when connected to an ideal DAR-Ol.
DAI'()1·N
PARAMETER
TYP
±120
6.6
6.625
MAX
UNITS
±0.2
%
6.90
V
6.45
at 25"C in common to all grades; Vs= +t5V and when connected to an Ideal DAR·Ot, unless
otherwise noted.
DAI'()1
PARAMETER
CONDITIONS
MAX
UNITS
10
10
Bits
1840
2274
p.A
±0.25
p.A
0.7
V
8.33
mA
0.1
%IFSIV
MIN
Aesolutlon
Analog Output Current
All Bits Low, V - Connected to FS Adjust
Zero Scale Output Current
All Bits High, V - Connected to FS Adjust
Logic Input "0"
Measured with Aespect to Output
logic Input "I"
Measured with Aespect to Output
Supply Current
All Bits High, V - Connected to FS Adjust
Power Supply Aejectlon
Vs= ±6V to ±18V
TYPICAL ELECTRICAL CHARACTERISTICS
2.1
CONDITIONS
Full Scale Tempco
(Note)
MIN
V
at Vs= ±15V, and when connected to an ideal DAR·Ot, unless otherwise noted.
DAI'()1·N
PARAMETER
TVP
TVP
DAI·01·GR
DAI·01·G
MAX
±60
MIN
TVP
±60
NOTE:
Full Scale Tempco Is defined as the change In output voltage measured in the
test circuit shown on the DAC·l00 data sheet and Is expressed in ppm between 25'C and either temperature extreme divided by the corresponding
temperature change.
PAGE1D-B2
MAX
MIN
TVP
-
±120
MAX
UNITS
ppm/'C
DAC-100/DAC-10110-BIT D/A CONVERTERS
REDUCED RESOLUTION APPLICATION
BASIC CONNECTIONS
BASIC UNIPOLAR VOLTAGE OUTPUT CIRCUIT
TYPICAL SETTLING TIME
FOR 1/2 SCALE CHANGE
, -I
""
1.0~SEC
}------r----oIOUT
}--
Z
oo
cc
C
DAC-100/DAC-10110-BIT D/A CONVERTERS
TYPICAL APPLICATIONS
BINARY-COOED-DECIMAL D/A CONVERSION
EXTERNAL REFERENCE CONNECTION
+15V
+15V
V-
ANALOG SUM OF TWO DIGITAL NUMBERS
"CAN BE EXPANDED TO 3 DIGITS BY ADDITION OF A THIRD OAC AND
99 TO CURRENT DIVIDER.
INTERFACING WITH CMOS LOGIC
The DAC-100/DAC-101 requires only about 1p.A of input current into each logic stage. This enables use with CMOS
inputs as long as one rule is observed; logic input voltages
should not exceed 6.5 volts or V+, whichever is smaller. To
provide an understanding of this rule, it is necessary to discuss the logic input stage design.
LOGIC INPUT STAGE DESIGN
For simplicity, only one of the ten identical input circuits is
shown below. The DAC-100/DAC-101 uses a fast currentsteering technique that switches a bit-weighted current
DAC-100 -
DIGITALLY PROGRAMMED LEVEL DETECTOR
LOGIC INPUT STAGE
ANALOG
OUTPUT
ZERO
VOLTS
"I"-VIN>REF
"O"-V1N
Z
o
CJ
c
Q
PAGE 10-85
DAC-1oo/DAC-10110-BIT D/A CONVERTERS
SUCCESSIVE APPROXIMATION AID CONVERTER
+16V
FULL
SCALE
ADJUST
t:;-4~6;;~'T':'!~~~
lSB BIT 8 ..._---+H++H~
BIT 7
BITO
...----+H++H
...----+H+-H
..._---+H+..
...----+H-;
81T 3 ..._---+H
BIT 5
BIT 4
+15V ill O.Ol#<1F
BIT2_---H
rl7
MSB BIT 1 _ - - -. .
MSBBIT ,
-15V
SOV
01
.5OVT
1
T
O.01pF
SERIAL
OUTPUT
::l,j.!~
:J±:
T
35V
ANALOG
l/J. F
•
GROUND
35V
•
-1SV
1t:
T'0V •
4.7pF
START __- - - . . J
~~:~~;~~ON
...._______'
+15V
T
.. +5V
~~~~D
~~~:------------'
NOTE
FOR A COMPLETE TREATMENT OF SA ADe's CONSTRUCTED WITH THE OAe-l00,
REFER TO AN-11, "A LOW COST. EASY-TO-BUILD SUCCESSIVE APPROXIMATION
AlD CONVERTER".
TRACKING (SERVO-TYPE) AID CONVERTER
CLOCK IN
MAXIMUM CLOCK RATE-= 3.5MHz
+5V TRACK HOLD
~
27
2.""
02
.r
fO.02
16
,;j:.,0.02
~LOCK
*
15
1+
*1/47400
•
1+
TO.,.
DIGITAL
OUTPUT
OUT
~+16
C
;J,
""
FOR CLOCK RATE"'" 3.5MHz C = 470pF
J-
POWER
GROUND
VIN
AIN
ANALOG
INPUT
=
3!.
J,
0 TO +10V
4.8kf2
ANALOG
GROUND
o-------------t---+------'
MAXIMUM FULL SCALE
SINE WAVE INPUT
IS 4500Hz
-15V
NOTE:
FOR A COMPLETE TREATMENT OF TRACKING AOC'S CONSTRUCTED
WITH THE DAC-101, REFER TO AN-6, "A LOW COST, HIGH PERFORMANCE TRACKING AID CONVERTER"_
PAGE 10-86
DAC-206
PMI
6-81T VOLTAGE OUTPUT D/A CONVERTER
®
FEATURES
•
•
•
•
•
•
•
Complete . . . . . . . . . . . . . .. Includes Internal Reference
6·Blt Resolution. . . . . . . . . . . . . . . . . . . .. 7·Bit Accuracy
30utputOptions ................ +10V, ±5V, ±10V
Fast .... . . . . . . . . . . . . . . . . . . . . . . .. 3!'l1 Settling Time
Low Power Consumption .......... 250mW Maximum
Standard Power Supplies ............. ±12Vto ±18V
TTL. Compatible Logic Levels
an internal reference and output amplifier that complement
a fast 6-bit DAC. Wide applications flexibility is offered by
the jumper selectable unipolar and bipolar binary coding
format and output voltage range options. The addition of a
seventh bit allows the resolution of this DAC to be brought
in line with its accuracy. The DAC-206 offers high-speed
operation in a highly accurate "complete" converter.
PIN CONNECTIONS
GENERAL DESCRIPTION
The DAC-206 is a monolithic 6·bit digital·to-analog converter
that can be considered a complete D/A system. It features
ORDERING INFORMATIONt
14 PIN DIP-HERMETIC
FULL TEMP.
N.L. LSB
MILITARY
TEMP.
COMMERCIAL
TEMP.
±1/2
DAC206AY'
DAC206EY
±3/4
DAC206BY'
DAC206FY
14·PIN HERMETIC DIP (V·Suffix)
• Also available with MIL-STO-8838 processing. To order add/883 as a suffix to
•
the part number.
t All listed parts are available with 160 hour burn·in. See Ordering Information,
Section 2.
UI
II:
W
lII:
SIMPLIFIED SCHEMATIC
W
>
Z
o(J
"'-M-S-.- - - - DIGITAL LOGIC INPUTS
-------,'LSB
6
SUM"
NODE
11
V+
7
1(1
SCALE
FACTOR
5.4k
5.4k
ANALOG
OUTPUT
>-.......---jf-::---O
I.
FULL
SCALE
ADJUST
·CONNECT TO SUM NODE FOR BIPOLAR CODING
(COMPLEMENTARY OFFSET BINARV)
13
v_
PAGE 10-87
*BIPOLAR/
UNIPOLAR
12
GROUND
~
OAC·206 6·BIT VOLTAGE. OUTPUT 01 A CONVERTER
ABSOLUTE MAXIMUM RATINGS (See
Note 3)
Operating Temperature
DAC-206A, DAC·206B ••.•...••..•• -55·C to + 125 ·C
DAC·206E, DAC·206F ................. O·C to + 70·C
DICE Junction Temperature (T j ) ••••••• -6S·C to +150·C
V + Supply Voltage to Ground •..•••..•••...• 0 to + 18V
V - Supply Voltage to Ground •.•••...••••..• 0 to -18V
Logic Input to Ground.. . . • . . . • . . . . . . . . • •• -0.7 to +6V
Internal Power Dissipation (Note 1) .....•••••••.• 500mW
Storage Temperature •....••...•.••• -65·C to +150·C
ELECTRICAL CHARACTERISTICS
PARAMETER
Nonlinearity
Full·Scale Tempco
A·Suffix
E·Suffix
B· and F·Suffix
Unipolar Zero Scale Output
(Notes 1, 2)
Unipolar Full Range Output
(Note 3)
Bipolar Output Voltage
(Note 3)
Settling Time (Note 4)
Lead Soldering Temperature (60 sec.) . . . . • • • . • • • .. 300·C
Output Short Circuit Duration (Note 2) ....••... Indefinite
NOTES:
1. Rating applies up to ambient temperatures of 100 'C. For temperatures
above 100'C, derate linearly at 10mW/'C.
2. Short circuit may be to ground or either supply. Rating applies to + 125 'C
case temperature or + 75 'C ambient temperature.
3. Absolute maximum ratings apply to both DICE and packaged parts. unless
otherwise noted.
at Vs= ±15V, TA = full operating range, unless otherwise noted.
SYMBOL
CONDITIONS
NL
TA =2S'C
TA = Full Operating Range
DAC206A1E
MIN
TYP MAX
DAC206B/F
MIN
TYP MAX
±1/4
±1I2
±1I2
±3/4
80
120
TC VFS
UNITS
LSB
ppm/'C
160
.,'?
Vzs
'Y
VFA
RL = 2kll, Pin 13 to 14
10 to 11, 12 to Ground
VFA
±SV Range
+10.00
-
+11.75
+10.00
-
±10%
±11
±10%
VFA
±10V Range
t.
To ±1/2 LSB
1.S
Logic "0" Input Voltage
VINL
Logic "1" Input Voltage
VINH
logic Input Current
liN
Power Supply Sensitivity
Pss
±12V" Vs " ;t18V, VFR ~ 10V
Power Supply Current
1+
I-
V+ = +15V
V- = -15V
1.5
3
Bit 1 ="0", Pin 11 shorted to 12
Pin 13 shorted to 14
+11.75
V
pS
LSB
0.8
V
10
10
p.A
0.15
0.2
%1%
8
10
8
10
rnA
2.0
V 1N = OV, each input
NOTES:
1. Zero scale or bipolar offset voltage can be trimmed to zero volts or to the
exact one's or two's complement condition with an external resistor net-
V
3
0.8
V
3. Full scale is adjustable to precisely 10 volts for unipolar operation and
10 volt or 20 volt peak·to·peak bipolar operation with an external SOOIl
potentiometer from Pin 14 to V - .
4. Guaranteed by design.
BASIC CIRCUIT CONNECTIONS
OPTIONAL ZERO SCALE OR BIPOLAR
FULL SCALE ADJUSTMENT TECHNIQUE
mV
±1.S
±1
2.0
work to Pin 11.
2. Logic Input voltage "'2.0 volts.
SO
±5.5
±10%
±11
±10%
Bipolar Offset Voltage (Note 1)
±1/2 (IVFR + I - IVFS-I)
25
OFFSET ADJUSTMENT
lDOkH
v-
v+
470kn
11
I
-1SV
PAGE 10-88
OAC·20B
DAC-206 6-BIT VOLTAGE OUTPUT D/A CONVERTER
DICE CHARACTERISTICS
1.
2.
3.
4.
5.
6.
7.
6.
9.
10.
11.
12.
13.
14.
B1 (MSB)
B2
B3
B4
BS
B6(lSB)
V+
ANALOG OUTPUT
GROUND
SCALE FACTOR
SUM NODE
BIPOLAR/UNIPOLAR
VFUll SCALE ADJUST
Refer to Section 2 for additional DICE Information.
DIE SIZE 0.092 X 0.054 Inch
ELECTRICAL CHARACTERISTICS at 25° C.
DAC-206N
BIPOLAR AND
UNIPOLAR
DAC-206G
BIPOLAR AND
UNIPOLAR
PARAMETER
SYMBOL CONDITIONS
LIMIT
liMIT
Nonlinearity
NL
Vs= ±15V
1/4
1/2
LSB MAX
Zero Scale Voltage
VZS
Vs =±15V
25
50
mVMAX
UNITS
II
ELECTRICAL CHARACTERISTICS at 25° C for all grades; Vs = ±15V. unless otherwise noted.
DAC-206
PARAMETER
SYMBOL CONDITIONS
Unipolar Full Scale Output
Voltage (All Models)
Bipolar Output Voltage
±5 Volt Range
± 10 Volt Range
LIMIT
UNITS
VFR
2kn Load, Logic" 0.8V. Short V- to Full Scale Trim, Unipolarl
Bipolar to Ground, and Scale Factor to Sum Node
10.00
11.75
VMIN
V MAX
VFR+
V FR-
2kn Load, Short Sum Node to Unipolar/Bipolar.
Short V- to Full Scale Trim and Scale Factor to Sum Node.
Logic Inputs :S O.BV
Logic Inputs" 2.0V
Open Scale Factor
Logic Inputs :5 O.BV
+4.93
-5.94
VMIN
V MAX
+9.78
VMIN
-11.89
V MAX
±1.5
LSB MAX
V FR +
V FRBipolar Offset Voltage
±1/2 (IVFR+I-IVFR_I)
..,
II:
Ii:..,
>
Z
o
U
c
Q
Logic Inputs 2: 2.0V
±5 Volt Range
± 10 Volt Range
Resolution
6
Bits MAX
Logic Input "0"
V1NL
0.8
V MAX
Logic Input "I"
V 1NH
2.0
VMIN
Logic Input Current, Each Input
V'N = OV
±8.0
~AMAX
Power Supply Rejection
PSR
±12V" Vs " ±18V, VFR " 10.OV
0.15
%FSNMAX
Power Consumption
Pd
No Load
250
mWMAX
TYPICAL ELECTRICAL CHARACTERISTICS at 25° C.
DAC-206N
DAC-206G
TYPICAL
TYPICAL
PARAMETER
SYMBOL CONDITIONS
Settling Time
ts
To ±1/2 LSB
1.5
1.5
~s
Full Scale Tempco
TCV FS
Vs =±15V
60
90
ppm/"C
PAGE 10-89
en
UNITS
DAC·206 6·BIT VOLTAGE OUTPUT D/A CONVERTER
ADDITION OF 7TH BIT
-,5V
FULL SCALE ADJUST
A 500{l pot from Pin 14 to V-can be used to adjust the full
range output voltage to exactly 10 volts in unipolar mode or
10 to 20 volts peak·to·peak in bipolar mode. If no pot is used,
tie Pin 14 to V-.
0--....-------,
100kn
IN4148
2.7M!!
SCALE FACTOR
For + 10 volt or ±5 volt outputs, short Pin 10 to Pin 11 (ad·
justs the feedback resistor around the output amplifier). For
±10 volt output, leave Pin 10 open. Intermediate output
voltages may be obtained by placing a pot between Pin 10
and Pin 11, but this will seriously degrade the full·scale
temperature coefficient due to the mismatch between the
+1150ppm/oC tempco of the difussed resistors and the pot
tempco.
LSB
CAPACITIVE LOADS
When driving capacitive loads greater than 50pF in unipolar
mode or 30pF in bipolar mode a 100pF capacitor may be
placed from Pin 11 to ground for added stability.
APPLICATIONS INFORMATION
INPUT CODES
The DAC·206 utilizes standard complementary binary
coding for unipolar mode operation (all inputs high pro·
duces zero output voltage). Complementary offset binary
coding may be implemented by shorting Pin 11 to Pin 12.
LOWER RESOLUTION APPLICATIONS
When less than 6 bits of resolution is required, tie off unused
bits to a voltage level greater than +2.0 volts. The +5 volt
logic supply is usually convenient.
PAGE 10-90
DAC-20B
PMI
9-BIT DlGlTAL-TO-ANALOG CONVERTER
(8 BITS PLUS SIGN)
FEATURES
GENERAL DESCRIPTION
•
•
•
•
•
The DAC-208 is a complete, monolithic, 8-Bit Plus Sign DAC
with a voltage output. A precision voltage reference, a logiccontrolled polarity switch, and a high-speed (750ns settling
time) output op amp are included. Non-linearity, monotonicity,
and full-scale temperature coefficient are guaranteed over
the full operating temperature range. Reliability is enhanced
by a monolithic design and a hermetic DIP package. Two
low-cost OO'70°C and two -55°'+125°C models are
available plus two models with MIL-STD-883 Class B precessing. All bits are guaranteed monotonic.
•
•
•
•
Complete . . . . . . . . . .. Includes Reference and Op Amp
Bipolar Output . . . . . . . . . . . . .. Sign/Magnitude Coding
User Selected + 5V or ± 1OV Output
No Bipolar Offset Adjustment Required
8·Bit Non·Linearity Maintained over Full Temperature
(0.1%)
Multiplying Operation
Fast. . . . . . . . . . . . . . . . . . . . . . . . .. 750ns Settling Time
Monotonicity Guaranteed
Models with MIL·STD·883 Class B Processing Available
ORDERING INFORMATIONt
PIN CONNECTIONS
18 PIN HERMETIC DUAL-IN-LiNE
INL
%FS
MILITARY
TEMP
COMMERCIAL
TEMP
0.1
0.2
DAC208AX'
DAC208BX'
DAC208EX
DAC208FX
MSB BIT 1
* Also available with MIL-STO-8838 orocessing. To order add/883 as asuffix to
the part number.
t All listed parts are available with 160 hour burn-in. See Ordering Information,
Section 2.
(/)
a:
l8-PIN DIP (X-Suffix)
w
I-
a:
w
>
Z
o
o
SIMPLIFIED SCHEMATIC
g
,
MSB
10
v-
BIT
BIT
BIT
2
3
4
DIGITAL LOGIC INPUTS
BIT
BIT
S
12
ANALOG
GROUND
PAGE 10-91
6
BIT
7
BIT
8
SIGN
BIT
5 VOLT
18
OPTION
DAC·208 9·BIT DIGITAL·TO·ANALOG CONVERTER
ABSOLUTE MAXIMUM RATINGS
Operating Temperature Range
DAC·208A,B ......... , .. , ....... -55'C to +125'C
DAC·208E, F. . . . . . . .. . . . . . . . . . . . . . .. O'C to + 70'C
Storage Temperature Range. . . . . . . .. -65'C to + 150'C
V + Supply to Analog Ground ............... 0 to + 18V
V - Supply to Analog Ground ............... 0 to -18V
Analog Ground to Digital Ground . . . . . . . . . .. 0 to ±0.5V
Logic Inputs to Digital Ground. . . . .. -5V to (V + -0.7V)
Internal Reference Output Current ............. , 300l'A
Reference Input Voltage. . . . . . . . . . . . . . . . . .. 0 to + 1OV
Internal Power Dissipation ............. . . . . .. 500mW
Lead Soldering Temperature. . . . . . . . . . .. 300'C (60 sec)
Output Short Circuit Duration. . . . . . . . . . . . . .. Indefinite
(Short circuit may be to ground or either supply.)
ELECTRICAL CHARACTERISTICS - MILITARY AND COMMERCIAL GRADES at Vs: ± 15V, TA :-55' C to + 125' C
for A and B grades, TA : O· C to + 70· C for E and F grades.
DAC·208A, E
PARAMETER
SYMBOL
CONDITIONS
Including Sign
Resolution
TYP
MAX
MIN
TYP
MAX
UNITS
9
9
9
9
9
9
Bits
Monotonicity
8
Non-Linearity
TA =25'C
TA =O'C - 70'C IE and F onlyl-55'CsTA" +125'C
(A+ B Sullix Only)
Zero Scale
Ollset Voltage
NL
8
Vzs
TA =25'C IVFR+-VFR-I
TA = Full Range
Bipolar Full Range
Voltage Symmetry
Zero Scale
Voltage Symmetry
Vzss
Gain Tempeo
TC
Bits
±O.1
±0.1
±0.2
±0.2
±0.1
±0.2
±0.1
±0.15
60
70
70
70
IVzs+ - Vzs-I
TA = Full Range
60
40
15
+10.0
+5.0
-11.5
30
+11.5
+5.75
-10.0
DNL
+10.0
+5.0
-11.5
+11.5
+5.75
-10.0
±1/2
750
750
1.5
1.5
Reference Input
Impedance
200
200
Reference Amplifier
Bandwidth
For 0.1 % Typical
Non-Linearity
10
v
v
MHz
For Stated
Non-Linearity
o
Reference Output
Current
Output Slew Rate
ppm/'C
Mil
10
3
7.6
10
mV
ns
BW
Reference Output
Voltage
DAC Output
Current
%FS
LSB
Reference Input
Slew Rate
Settling Time
Reference Input
Multiplying Range
%FS
mV
Internal Reference
External Reference
Output Voltage
Range
Dillerential
Non-Linearity
DAC·208B, F
MIN
V
7.6
10
10
rnA
100
100
SRO
_Lo_g~i_c_ln~p_u_t_C_ur_re_n_t__~IIN~_______-_5_V
__
S_V~I_S_V_+_-_0_.7_V______________
±_2_.0____±_1_0._0__________________±
__
2._0____
±_10_.0
____________--'"A
0.8
Logic "0" Voltage
VINL
Logic "1" Voltage
VINH
2.0
Power Supply
Sensitivity
Pss
0.03
Positive Supply
Current
1+
Negative Supply
Current
1-
0.8
2.0
0.15
V
0.15
0.03
9
10
PAGE 10·92
12
V
10
9
rnA
12
rnA
DAC·208 9·BIT DIGITAL·TO·ANALOG CONVERTER
The 5V option is unipolar only and will not function for
negative outputs.
CONNECTION INFORMATION
FULL SCALE ADJUSTMENT CIRCUIT
MSB
POWER SUPPLIES
The DAC·20S will operate within specifications for power
supplies ranging from ±12V to ±1SV for unipolar positive
operation; and from ±13V to ±1SV for bipolar. Power supplies should be bypassed near the package with a O.1/tF disk
capacitor.
DIGITAL. INPUTS
SIGN
LSS BIT
REFERENCE
OUTPUT
FULL
SCALE
ADJUST
POT
10krl
}o-ooK>---+--+----{,
REFERENCE
INPUT
CAPACITIVE LOADING
LOW T C
The output operational amplifier provides stable operation
with capacitive loads up to 100pF.
ANALOG
GROUND
REFERENCE OUTPUT
For best results, Reference Output current should not ex·
ceed 100~.
FULL SCALE ADJUSTMENT
Full Scale output voltage may be trimmed by use of a poten·
tiometer and series resistor as shown; however, best results
will be obtained if a low tempco resistor is used or if pot and
resistor tempcos match. Alternatively, a single pot of
2: 75kO may be used.
REFERENCE INPUT BYPASS
Lowest noise and fastest settling operation will be obtained
by bypassing the Reference Input to Analog Ground with a
O.01I'F disk capacitor.
GROUNDING
For optimum noise rejection, separate digital and analog
grounds have been brought out. Best results will be obtained
if these grounds are connected together at one point only,
preferably at the power supply, so that the large digital cur·
rents do not flow through the analog ground path.
INTERFACING WITH CMOS LOGIC
The DAC-20S's logic input stages require about 1/tA and are
capable of operation with inputs between -5 volts and V+-.7V.
This wide input voltage range allows direct CMOS interface
with no additional components.
USE WITH EXTERNAL REFERENCES
Positive·polarity external reference voltages referred to
Analog Ground may be applied to the Reference Input ter·
minal to improve full scale tempco, to provide tracking to
other system elements, or to slave a number of DAC·20S's to
the Reference Output of anyone of them.
f/)
VARIABLE REFERENCES
APPLICATIONS INFORMATION
Operation as a two·quadrant multiplying DAC is achieved by
applying an analog input varying between 0 and + 10V to the
Reference Input terminal. The DAC output is then the scaled
product of this voltage and the digital input.
LOWER RESOLUTION APPLICATIONS
SIGN PLUS MAGNITUDE CODING TABLE
For applications not requiring full S·blt resolution, unused
logic inputs should be tied to ground.
SIGN BIT
MSB
LSB
+ FULL SCALE
-1LSB
UNIPOLAR OPERATION
Operation as a S·bit straight binary converter may be im·
plemented by permanently tying the Sign Bit to +5V (for
positive Full Scale output).
+ 5 VOLT OUTPUT
The output voltage range can be changed to+5V by connecting the 5V option pin [pin 131 to the analog output [pin 141.
~
C
C
+HALF SCALE
0 0 0 0 0 0 0
ZERO SCALE ( + )
1
0 0 0 0 0 0 0 0
ZERO SCALE ( - )
0
0 0 0 0 0 0 0 0
-HALF SCALE
0
0 0 0 0 0 0 0
- FULL SCALE
+1LSB
0
PAGE 10-93
a:
w
a:
w
...
~
8
c
c
PMI
DAC-210
ll-BIT DlGITAL-TO-ANALOG CONVERTER
(10 BITS PLUS SIGN)
®
FEATURES
GENERAL DESCRIPTION
•
•
•
•
•
The DAC-210 is a complete, monolithic 10 Bit plus sign DAC
with a ±10V Voltage output. A precision voltage reference,
a logic controlled polarity switch and output amplifier are
included. Non-linearity, monotonicity, and full-scale
temperature coefficient are guaranteed over the full
operating temperature range. Ease of application is achieved
by the total D/A system specs given for non-linearity and
zero-scale offset. System specs eliminate the complex error
budget analysis required by less "complete" DACs. Sign
Magnitude Coding minimizes the "Major-Carry" zero code
errors inherent in offset coding schemes. Reliability is
enhanced by a monolithic design, 100% burn-in, and a
hermetic DIP package. MIL-STD-883 Class B processing Is
available on -55°C to +125°C grades. Also offered are
models with a ±1 LSB Maximum Full Range Symmetry error.
•
•
•
•
•
•
Complete ........... Includes Reference and Op Amp
Bipolar Output ................................. ±10V
Sign-Magnitude Coding
No Bipolar Offset Adjustment Required
10-Bit Non-Linearity Maintained over Full Temperature
(0.075%)
Multiplying Operation
Fast .............................. 1.51's Setlling Time
Monotonicity Guaranteed
Reliable ............ 100% Burned-in 72 hrs. at +125°C
Models with MIL-STO-883 Class B Processing Available
Models with Guaranteed ±1 LSB Full Range Symmetry
Available
ORDERING INFORMATION t
18 PIN HERMETIC DUAL INLINE PACKAGE
TEMPCO
INL
±40
±0.05
±60
±0.05
±30Typ
±0.10
PIN CONNECTIONS
MILITARY'
COMMERCIAL
DAC210AX
"DAC210ASX
DAC210BX
'"DAC210BSX
DAC210EX
"DAC210ESX
DAC210FX
"DAC210FSX
DAC210GX
la-PIN DIP
(X-Suffix)
"Also available with MIL-STD-8838 Processing. To order add 1883 as a suffix to
the part number.
tAil listed parts are available with 160 hour burn-in. See Ordering Information.
Section 2.
*"These parts are selected for± 1OmV Full Range Voltage Symmetry error max.
SIMPLIFIED SCHEMATIC
r~-----~
m
m
DIGITAL lOGIC I N P U T S ' - - - - - -
m
m
m
m
m
m
m
BIT
2
345678910
12345678910
R'F
SIGN
BIT
OUTPUT
REF
INPUT
DIGITAL
GROUND
R2
v-
ANALOG
GROUND
Manufactured under one or more of the following patents:
4,055,753; 4,056,740; 4,092,639
PAGE 10-94
DAC·210 11·81T DIGITAL·TO·ANALOG CONVERTER
ELECTRICAL CHARACTERISTICS - MILITARY AND COMMERCIAL GRADES at VS =±15V, -55 0 C:s T A:S +125 0 C, for A
and B grades. 00 C :s T A:S +70 0 C for E, F and G grades, unless otherwise noted.
DAC·210A,E
PARAMETER
SYMBOL CONDITIONS
Resolution
Including Sign
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
11
11
11
11
11
11
11
11
11
Bits
TA =25'C
TA = Full Range
Non·Llnearlty
Vzs
-
TA =25'C
TA = Full Range
TA=25'C (Note 21
TA = Full Range
Zero Scale
Voltage Symmetry Vzss
(Vzs+ -Vzs_l
TA = Full Range
Gain Tempco
Tc
Output Voltage
Range
+VOR
-VOR
Non·Unearity
±O.05
±0.10
±0.O75
±0.10
±0.05
±0.06
±0.1
±.0.1
40
50
60
70
Bits
±0.10
%FS
Bipolar Full Range
Voltage Symmetry VFRS
(V'A+ - I V,A-II
Differential
±0.05
±O.05
NL
T A = Full Range
(A or B onlYI
Zero Scale
Offset Voltage
9
10
10
Monotonicity
DAC·210G
DAC·210B,F
MIN
DNL
%FS
80
50
2
Internal Reference
±40
External Reference
+10.0
-11.5
+11.5
-10.0
TA =25'C
±30
±30
±60
±30
±15
+10.0
-11.5
+11.5
-10.0
±1
+10.0
-11.5
mV
ppm/'C
+11.5
-10.0
V
LSB
±1
±1
mV
Settling Time
Ts
1.5
1.5
1.5
"s
Reference Input
Slew Rate
SRREF
1.5
1.5
1.5
VI"s
ZIN
200
200
200
Mil
Reference Input
Impedance
Reference Input
Multiplying Range
IVRm
For 0.1 % Typical
Non·Llnearlty (Note 11
VREF
DAC Output
Current
10
For Stated
Non·Linearlty (Note 11
IREF
(Note 11
Current
10
3
Logic "0" Input
Voltage
VINL
Logic "I" Input
Voltage
VINH
Power Supply
Sensitivity
Pss
Positive Supply
Current
Negative Supply
Current
7.6
10
3
10
V
7.6
II)
II:
W
lII:
W
V
>
Z
10
mA
U
100
"A
7.6
0
0
10
0
10
100
-5V",V I ",V+
±2.0
0
100
10
SRo
Lagle Input Current liN
U
00(
Q
3
MHz
Reference Output
Voltage
Output Slew Rate
CI
~
Reference Amplifier BW
Bandwidth
Reference Output
II
10
±10.0
±2.0
0.8
2.0
10
±10.0
±2.0
0.8
2.0
V/"s
±10.0
~
0.8
V
2.0
V
TA=25'C
O.ot5
0.05
O.ot5
0.05
O.ot5
0.1
%VFF,N
TA = Full Range
0.015
0.1
O.ot5
0.1
O.ot5
0.1
'IoVFsiV
1+
7
9
9
mA
1-
-10
-12
-12
mA
NOTES:
1. Guaranteed by design.
2. The DAC-210A. B. E. & F grades are available with ± 10mV (± 1 LSB or
PAGE 10-95
9
-10
-12
-10
±0.10%FSI Bipolar Full Range Voltage Symmetry. Part numbers for this
option are DAC-210ASX. DAC-210BSX. DAC-210ESX and DAC-210FSX.
respectively.
00(
is
DAC·210 11·BIT DIGITAL·TO·ANALOG CONVERTER
ABSOLUTE MAXIMUM RATINGS
Operating Temperature Range
DAC·210A,B .................... -55'C to +125'C
DAC·210E,F,G ...................... O'C to +70'C
DICE Junction Temperature (T j ) ••••••• -65' C to + 150' C
Storage Temperature Range. . . . . . . .. -65'C to + 150'C
V + Supply to Analog Ground. . . . . . . . . . . . . .. 0 to + 18V
V - Supply to Analog Ground. . . . . . . . . . . . . .. 0 to -18V
Analog Ground to Digital Ground ........... 0 to ±0.5V
Logic Inputs to Digital Ground. . . . .. -5V to (V + -0.7V)
Internal Reference Output Current .............. 300pA
Reference Input Voltage ................... 0 to + 10V
Internal Power Dissipation ............... . . .. 500mW
Lead Soldering Temperature ............ 300'C (60 sec)
Output Short Circuit Duration. . . . . . . . . . . . . .. Indefinite
(Short circuit may be to ground or either supply.)
NOTE: Absolute ratings apply to both DICE and packaged parts unless
otherwise noted.
DICE CHARACTERISTICS
DIE SIZE 0.117 x 0.088 Inch
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
Bl (MSB)
B2
B3
B4
B5
B6
B7
B8
B9
Bl0 (LSB)
DIGITAL GROUND
12. V13.
14.
15.
16.
17.
18.
Refer to Secllon 2 for addilional DICE Informallon.
ANALOG GROUND
ANALOG OUPUT
REFERENCE INPUT
NOTE:
V+
For 5 volt output option (+5V only) * is
REFERENCE OUTPUT
SIGN BIT
connected to analog output.
to analog ground.
** is connected
ELECTRICAL CHARACTERISTICS at 25' C; Vs = ± 15V + 10V Full Scale Output, unless otherwise noted.
DAC-210N
PARAMETER
CONDITIONS
Resolution
Bipolar Output
Unipolar Output
DAC-210G
DAC-210GR
LIMIT
LIMIT
LIMIT
UNITS
11
10
11
10
11
110
Bits MAX
±0.1
±0.2
'%FSMAX
10
Monotonicity
Nonlinearity
Bits MIN
±0.05
Zero Scale Offset
Sign Bit High, All Other
Inputs Low
±5
±10
±10
mVMAX
Zero Scale Symmetry
± 10V Full Scale
±1.0
±2.0
±2.0
mVMAX
Full Scale Bipolar
Symmetry
± 10V Full Scale
±40
±80
±80
mVMAX
Power Supply
Rejeclion
Vs
0.05
0.05
0.1
%VFsNMAX
300
300
300
mWMAX
Logic Inpul "0"
0.8
0.8
0.8
V MAX
Logic Input "1"
2.0
2.0
2.0
VMIN
11.5
10
-10
-11.5
11.5
10
-10
-11.5
11.5
10
-10
-11.5
V MAX
VMIN
V MAX
VMIN
±1
±1
±1
LSB MAX
Power Consumption
~
±12V 10 ±18V
IOUT~O
V+ (Sign Bit High)
V- (Sign Bit Low)
Outpul Voltage Analog
(All Bits High)
Differential Nonlinearity
TYPICAL ELECTRICAL CHARACTERISTICS at Vs =
± 15V and + 10V Full Scale Output, unless otherwise noted.
DAC-210N
DAC-210G
TYPICAL
TYPICAL
TYPfCAL
15
30
30
ppm/'C
To±1I2 LSB
10 VoltSlep
1.5
1.5
1.5
~s
1.0
1.0
1.0
1.0
~
PARAMETER
SYMBOL
CONDITIONS
Full Scale Tempco
TCVFS
Internal Reference
Settling Time
(T A ~25'C)
Is
Logic Input Current
TA~25'C
PAGE 10-96
DAC-210GR
UNITS
DAC·210 11·BIT DIGITAL·TO·ANALOG CONVERTER
CONNECTION INFORMATION
10-BIT SIGN-MAGNITUDE ADC
FULL SCALE ADJUSTMENT - Full Scale output voltage
may be trimmed by use of a potentiometer and series
resistor as shown; however, best results will be obtained if a
low tempco resistor is used or if pot and resistor tempcos
match. Alternatively, a single pot of 2: 75kO may be used.
ANALOG
INPUT
±10V
+16V
CLOCK START -+5V
SERIAL
DATA
END OF
CONVERSION
FULL SCALE ADJUSTMENT CIRCUIT
SIGN BIT
DIGITAL INPUTS
rr---
,
1
LSB SIGN BIT V+
MSB
BINARY
MAGNITUDE
PARALLEL
DIGITAL
OUTPUTS
REFERENCE
OUTPUT
FULL
SCALE
ADJUST
REFE ENCE
INPUT
10Kn
POT62KO
lOW 1: C,
ANALOG
GROUND
vNOTES:
1. CONNECT END OF CONY. TO START
FOR CONTINUOUS OPERATION.
2. FOR NON-CONTINUQUS OPERATION,
HOLD START LOW FOR ONE CLOCK
CYCLE. CONVERSIONS BeGIN ON THE
NEXT LOW TO HIGH TRANSITION.
3. CONVEASION IS COMPLETED IN 12
CLOCK CYCLES.
REFERENCE INPUT BYPASS - Lowest noise and fastest
settling operation will be obtained by bypassing the
Reference Input to Analog Ground with a O.01JLF disk
capacitor.
GROUNDING - For optimum noise rejection, separate
digital and analog grounds have been brought out. Best
results will be obtained if these grounds are connected
together at one point only, preferably at the power supply,
so that the large digital currents do not flow through the
analog ground path.
APPLICATIONS INFORMATION
TIME MULTIPLEXED AID CONVERTER
POWER SUPPLIES - The DAC·210 will operate within
specifications for power supplies ranging from ±12V to
±18V. Power supplies should be bypassed near the
package with a O.1JLF disk capaCitor.
+-+-__
V",(+)
v(-)
en
II:
W
LOWER RESOLUTION APPLICATIONS - For applications
not requiring full 10-bit resolution, unused logic inputs
should be tied to ground.
UNIPOLAR OPERATION - Operation as a 10·bit straight
binary converter may be implemented by permanently tying
the Sign Bit to +5V (for positive Full Scale output) or to
ground (for negative Full Scale output).
TYPICAL APPLICATIONS
II
CAPACITIVE LOADING - The output operational amplifier
provides stable operation with capacitive loads up to 100pF.
REFERENCE OUTPUT - For best results, Reference Out·
put current should not exceed 100JLA.
INTERFACING WITH CMOS LOGIC - The DAC-210's logic
input stages require about 1JLA and are capable of operation
with inputs between -5 volts and V +. This wide input
voltage range allows direct CMOS interface with no addi·
tional components.
SiH
USE WITH EXTERNAL REFERENCES - Positive·polarity
external reference voltages referred to Analog Ground may
be applied to the Reference Input terminal to improve full
PAGE 10-97
lII:
W
>
Z
o(,)
c
Q
DAC·210 11·81T DIGITAl·TO·ANALOG CONVERTER
scale tempco, to provide tracking to other system elements,
or to slave a number of DAC·210's to the Reference Output
of anyone of them.
VARIABLE REFERENCES - Operation as a two·quadrant
multiplying DAC is achieved by applying an analog input
varying between 0 and +10V to the Reference Input ter·
minal. The DAC output is then the scaled product of this
voltage and the digital input.
SIGN·MAGNITUDE CODING TABLE
SIGN BIT
+ FULL SCALE
-1LSB
LSB
1 1 1 1 1 1 1 1 1
+HALF SCALE
ZERO SCALE ( + )
ZERO SCALE ( - )
0
-HALF SCALE
0
- FULL SCALE
+1LSB
0
PAGE 10-98
MSB
o0 0
o 000
o0 0 0
o0 0
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 000
0 0 0 0 0 0
1 1 1 1 1 1 1 1 1
PMI
DAC-312
12-81T HIGH SPEED
MULTIPLYING D/A CONVERTER
®
excellent power supply rejection ratio of ±.001% FS/%
z
oCJ
DNL
±1 LSB
t All listed parts are available with 160 hour burn-in. See Ordering Information,
r-----~~~~~~~~~++~~~~~~~~~~
16
DNL
± 1 LSB
± 1 LSB
Military Temperature Range Devices
With MIL-STO-883 Class B Processing
r-----~~-+~~~~--~~~-r~~~~--~--oIO
COMP
u
C
Q
FUNCTIONAL DIAGRAM
B2
...
;;
III
The 250 ns settling time with low glitch energy and low power
consumption are achieved by careful attention to the circuit
design and stringent process controls. Direct interface with
all popular logic families is achieved through the logic threshold terminal.
High compliance and low drift characteristics (as low as
10ppm/' C) are also features of the DAC-312 along with an
V(+)
II
c
Q
DAC·31212·BIT HIGH SPEED MULTIPLYING D/A CONVERTER
ABSOLUTE MAXIMUM RATINGS
Operating Temperature
DAC-312B ••••••••••••••••••••••••.•• -55·C to +125·C
DAC312F ............................... O·C to +70·C
DICE Junction Temperature (Ti ) ••.•.•. -65·C to +150·C
Storage Temperature •••••••••••••••••• -65·C to +125·C
Lead Temperature (Soldering, 60 sec) •••••••••.••• 300·C
ELECTRICAL CHARACTERISTICS at Vs = ±
15V, IREF
Power Supply Voltage. • • . . • • • • • • • • • • • • • • • • •• • • • • •• ±18V
Logic Inputs •••••••.••••••••.•••••••••••••• -5V to +18V
Analog Current Outputs ••••••••••.••••••..• -8V to +12V
Reference Inputs V 14, V 15 ...................... V-to V+
Reference Input Differential Voltage (V 14, to V 15) .••• ±18V
Reference Input Current (114) •••••.••••••••••••• 1.25mA
NOTE: Absolute ratings apply to both DICE and packaged parts unless
otherwise noted.
= 1.0mA, -55· CST A S 125· C for DAC-312B, O· CST AS 70· C for
DAC-312F, unless otherwise noted. Output characteristics refer to both lOUT and lOUT.
DAC-312B/F
PARAMETER
SYMBOL
CONDITIONS
MIN
Resolution
12
Monotonlcity
12
Differential
Nonlinearity
D.N.L.
Deviation from ideal straight line
Full Scale Current
IFS
VREF = 10.000V
R14 = R15 = 10.000kO
Full Scale Tempco
TCI FS
Output Voltage
Compliance
Voc
Full Scale
Symmetry
I FSS
Zero Scale Current
Izs
3.935
(See Note)
D.N.L. Specification guaranteed
over compliance range
ts
Propagation
Delay - all bits
tpLH
tpHL
All bits switched
50% point logic swing to
50% point output (See Note)
Output Resistance
Ro
Output Capacitance
COUT
Logic Input Levels "0"
VIL
VLc=GND
Logic Input Levels "1"
V IH
VLC = GND
Logic Input Current
liN
VIN = -5 to +18V
Logic Input Swing
VIS
-5
IREF
0.2
Settling Time
Reference Current
Range
Reference Bias
Current
Reference I "put
115
Power Supply
Range
V+
V-
VOUT=OV
Power Supply
1+
11+
1-
Power
Dissipation
Po
mA
±10
±.001
±4O
±.004
ppm/'C
%FS/'C
+10
Volts
±2.0
I'A
0.10
JlA
250
500
ns
25
50
ns
MO
pF
2.0
PSSI FS+
PSSIFs-
Current
4.063
0.8
V+ = +13.5V to +16.5V. V-=-15V
V-=-13.5V to -16.5V, V+ = +15V
Sensitivity
%FS
3.999
20
RI4 (eq) = 8000
Cc = OpF (See Note)
Power Supply
±.05
,.10
dl/dt
Slew Rate
Bits
%FS
LSB
±O.4
To ±1/2 LSB, all bits
switched ON or OFF (See Note)
UNITS
±.025
±1.0
-5
IIFSI-IIFsl
MAX
Bits
-
Deviation from ideal step size
N.L.
Nonlinearity
TYP
Volts
Volts
40
I'A
+18
Volts
1.0
1.1
mA
-0.5
-2.0
I'A
4.0
8.0
-
±0.0005
±.OO025
±.OOI
±.OOI
%FSl%aV
4.5
-18
-
18
-10.8
Volts
V+=+5V, V-=-15V
3.3
-13.9
7.0
-18.0
V+=+15V, V-=-15V
3.9
-13.9
7.0
-18.0
V+=+5V, V-=-15V
V+ = +15V, V- = -15V
225
267
305
375
NOTE: Guaranteed by design.
PAGE 10·100
mAljjs
mA
mW
DAC·31212·BIT HIGH SPEED MULTIPLYING D/A CDNVERTER
DICE CHARACTERISTICS
1. B1 (MSB)
2. B2
11. B11
12. (LSB) B12
3. B3
4. B4
5. B5
13.
14.
15.
16.
17.
18.
19.
20.
6. B6
7. B7
8. B8
9. B9
10. B10
DIE SIZE 0.140 )( 0.095
V LC/AGND
VREF (+)
VREF (-)
COMP
V10
ro
V+
Refer to Section 2 for additional DICE Information.
ELECTRICAL CHARACTERISTICS at 25° C; Vs =± 15V, and IAEF= 1.0mA, unless otherwise noted. OutPl,lt characteristics
refer to both lOUT and lOUT'
PARAMETER
SYMBOL
CONDITIONS
DAC·312N
DAC·312G
LIMIT
LIMIT
UNITS
12
12
Bits MIN
Resolution
12
12
Bits MIN
±0.05
±0.05
%FS MAX
+10
-5
+10
-5
V MAX
VMIN
4.031
3.967
4.063
3.935
mAMAX
mAMIN
Monotonicity
Nonlinearity
Output Voltage
Compliance
VOC
Full Scale Current
Change <112 LSB
VAEF = 10.000V
A'4' A,. = 10.000kO
Full Scale
Current
Full Scale Symmetry
I FSS
±1.0
±2.0
"A MAX
Zero Scale Current
IzS
0.1
0.1
"A MAX
±O.012
±1/2
±0.025
±1
%FSMAX
Bits (LSB) MAX
Differential
Nonlinearity
DNL
Deviation from
ideal step size
Logic Input Levels "0"
V IL
VLc=GND
0.8
0.8
V MAX
Logic Input Levels "1"
V IH
VLC= GND
2.0
2.0
VMIN
+18
-5
+18
-5
V MAX
VMIN
Logic Input Swing
VIS
Reference Bias
Current
I,.
-2.0
-2.0
"A MAX
PSSI FS+
PSSIFS-
V+ = +13.5V to +16.5V, V- = -15V
V- = -13.5V to -16.5V, V+ = +15V
±.001
±.001
±.001
±.001
%1% MAX
%1% MAX
Power Supply
Current
1+
1-
Vs =±15V
I AE F,,1.0mA
7
-18.0
-18.0
mAMAX
mAMAX
Power
Dissipation
Po
Vs =+15V
I AEF ,,1.0mA
375
375
mWMAX
Power Supply
Sensitivity
ELECTRICAL CHARACTERISTICS at 25° C; Vs =
±
15V, and IAEF= 1.0mA,
unless otherwise noted. Output characteristics
refer to both lOUT and lOUT.
CONDITIONS
PARAMETER
SYMBOL
Reference Input
Slew Aate
dl/dt
Propagation Delay
tpLH, tpHL
Any Bit
ts
To ±112 LSB, All
Bits Switched ON
or OFF.
Settling Time
Full Scale
TC IFS
PAGE 10·101
DAC·312N
DAC-312G
TYP
TYP
UNITS
8.0
8.0
mA/"s
25
25
ns
250
250
ns
±10
±10
ppm/'C
II
N
l?
U
C
C
III
a:
III
I-
a:
>
III
Z
0
U
C
......
C
DAC-31212-BIT HIGH SPEED MULTIPLYING D/A CONVERTER
TYPICAL PERFORMANCE CURVES
OUTPUT CURRENT VB
OUTPUT VOLTAGE
(OUTPUT VOLTAGE COMPLIANCE)
6.0
4.0
3.6 VI-I. 1_15V
;;
oS
...
illa:
32
a:
"...
2.0
::>
~
1.6
0
1.2
::>
I
'REF = 1.0mA
4.0
I)
Hrl-l=-;0.8V
I
2.8
2.'
I
'REF -1.0mA
t
3.6
3.2
TA =TM1N TOTMAX
I ALll
BITS ON
2.6
'REF = a.SmA
I
I
I
0.8
0.0
-14
-10
-6
1.2
I
I
-2
10
0.4
-14
14
I
-10
-14
-1'
_13.6
~ -13.4
o
'~EF ~ ,.O~A
1(-)
8
10
12
14
16
12
~
I
:;
o
>
I
':;
I!:
I
ALL BITS ON
I I
I
-6
-2
I I
I j
8
6
4
2
15
~r
-2
I
-4
I
10
14
-50
18
50
,L-
I
~
~HtH<11 J
-100
20
-50
0
BASIC POSITIVE REFERENCE OPERATION
50
100
150
200
{OOOO 0000 COOO}
IREF = 1.0mA
250
PULSED REFERENCE OPERATION
MSB
LSB
8182 B3 B4 B5 B6 B7 B8 89 810 811812
V REF (+}
9
J
RREF
(RlS) 14 r-'..:..J.:...L;:...&.::;.J.:;.J.::..L:-I.:...JL:..J':'::"'J.:.:...L.::" 18 _
::
'0
ovJL
FDA FIXED REFERENCE,
TTL OPERATION,
TYPICAL VALUES ARE:
V REF = +10.000V
V REF (+)
4095
IFA = RREF
x 4096 x 4
R
REF
RIN'
DAC-312
VI-)
200
VS=±15V
I--IREF = 1.0mA-
BASIC CONNECTIONS
IREF----n:i5'" 15
150
TRUE AND COMPLEMENTARY
OUTPUT OPERATION
POWER SUPPLY VOLTAGE (V)
VREF (+)
100
TEMPERATURE rOC)
a:
a: -13.2
~
,
1\
~ 10
I TA=~M'N iOTMA~_
/ ' --'I'-..
-13.8
1
~
-13
1
1
-14.2
-14.0
a
~ "-1 1
~
1
POWER SUPPLY CURRENT
VB TEMPERATURE
!~11 UJHfffi
a: -12
14
V 15 REFERENCE COMMON MODE (VOLTS)
POWER SUPPLY CURRENT VB
POWER SUPPLY VOLTAGE
~
-10
I
I
I
'REF =O.2mA
0.8
OUTPUT VOLTAGE (VOLTS)
a
II
I
J
1.6
I I
I I
x Jkm.
2.0
-
16r-~~---r--~---'----r---,
POSITIVE COMMON MODE VOLTAGE
IS ALWAYS (V+) -1.25V.
NEGATIVE COMMON MODE VOLTAGE
IS ALWAYS IV-J +1.B +IIREF
r-- r--
'REF - a.SmA
I
I
I
0.4
I II I
r-- I--N~TES 1
2.4
'RE~=o.21A -
OUTPUT COMPLIANCE
VB TEMPERATURE
REFERENCE AMPLIFIER
COMMON MODE RANGE
4.2
TYPICAL VALUES:
RIN = lkn
{OPTIONAL RESISTOR
FOR OFFSET INPUTS
14
Rp
OAC-3l2
15
,.
Rp = 4kH
V 1N {+} '" lV
V(+) VLC AREF = 10.000k
R15 = RREF
__
1 __
1
1
1
REa'"
+
+ RREF
A; R;
Cc = 0.01#<1F
V LC = OV (GROUND)
iQ
10 +
= IFR FOR ALL
LOGIC STATES.
PAGE 10-102
NO CAP
{ll1111l111l1}
DAC-312 12-BIT HIGH SPEED MULTIPLYING D/A CONVERTER
BASIC CONNECTIONS
NEGATIVE LOW IMPEDANCE OUTPUT OPERATION
POSITIVE LOW IMPEDANCE OUTPUT OPERATION
OAe-3l2
DAC-312
4095
IFR = 4096 )( 4
x
'REF
4095
'FA = 4096 X 4 X 'REF
FOR COMPLEMENTARY OUTPUT (OPERATION AS A NEGATIVE LOGIC DAel.
(PIN 191; CONNECT 10 (PIN 181
~gN::g~~~~ERTING INPUT OF OP-AMP TO
FOR COMPLEMENTARY OUTPUT (OPERATION AS A NEGATIVE LOGIC DAC),
CONNECT NON-INVERTING INPUT OF OP-AMP TO
(PIN 191: CONNECT
10 (PIN lBI TO GROUND.
iQ
iQ
ACCOMODATING BIPOLAR REFERENCES
BASIC NEGATIVE REFERENCE OPERATION
II
N
Z;
U
C
Q
NOTE:
RREF SETS I FS ; R1S IS FOR A
BIAS CURRENT CANCELLATION.
OAe-3l2
II)
a::
w
I-
-=-
a::
W
>
Z
'REF;;;' PEAK NEGATIVE SWING OF liN
o
RECOMMENDED FULL SCALE
ADJUSTMENT CIRCUIT
U
c
Q
14
R15
(OPTIONAL)
-
VREFo--~_~~~r------'
+5.000V
OAe -312
16
DAC-312
HIGH INPUT
IMPEDANCE
VREFI+I MUST BE ABOVE PEAK POSITIVE SWING OF V IN
10kn
POT
PAGE 10-103
t
APPROX.
6kn
DAC-312 12-BIT HIGH SPEED MULTIPLYING 01 A CONVERTER
BASIC CONNECTIONS
INTERFACING WITH VARIOUS LOGIC FAMILIES
TTL
V TH = +1.4V
HTl
Eel
V(+I
20kn
13kT!
-=V TH ;; V LC
+15V
+ 1.4V
TO PIN 13
Vle
V le
R
2Dkfl:
FOR +15V CMOS
TO PIN 13
30kn
!4DO,uA
V TH .. +7.6V
6.2kn
9.1kn
Vle
-S.2V
NOTES:
6.2kfl:
ro.'.F
1. SET THE VOLTAGE "A" TO THE DESIRED LOGIC
INPUT SWITCHING THRESHOLD.
2. ALLOWABLE RANGE OF lOGIC THRESHOLD IS
TYPICALLY -SV TO +13.5V WHEN OPERATING
THE OAC ON ±15V SUPPLIES.
-=-
BIPOLAR OFFSET (TRUE ZERO)
ROFF
R'5.
2.000mA
5.000kn
Your
OAe-3lZ
VREF
R14=- .. R'S
1.0mA
VREF
R'5
TDkn
ROFF =2.OmA
OPTIONAL FOR
2's COMPLEMENT
OPERATION
MSB
NOTE:
CODE MAY BE COMPLEMENTED BY REVERSING '0 &
COOEFORMAT
Offset binary;
true zero output.
OUTPUT SCALE
LSB
iQ
MSB
Bl B2
B3
B4
B5
B8
B7
B8
Positive full scale
Positive full scale - LSB
2's complement;
true zero output
MSB complemented
(need inverter at B1).
Bl0
Bll
LSB
B12
1
a
+LSB
Zero scale
1
-LSB
a
Negative full scale + LSB
Negative full scale
BI
a
1
1
a
a
a
Positive full scale
Positive full scale - LSB
a
a
+1 LSB
Zero scale
a
-1 LSB
a
a
Negative full scale + LSB
Negative full scale
PAGE 10-104
10
10
(mAl
(mAl
VOUT
3.999
3.998
2.001
2.000
1.999
0.001
0.000
0.000
0.001
1.999
1.999
2.000
3.999
3.999
9.9951
9.9902
0.0049
0.000
-0.0049
-9.9951
-10.000
3.999
3.998
0.000
0.001
1.998
1.999
2.000
3.998
3.999
9.9951
9.9902
0.0049
0.000
-0.0049
-9.9951
-10.000
2.001
1
1
a
2.000
1.999
0.001
0.000
DAC-312 12-BIT HIGH SPEED MULTIPLYING D/A CONVERTER
BASIC CONNECTIONS
BASIC UNIPOLAR OPERATION
A'
2.5k
REF-Ol
+10V
V OUT
OAe-3l2
B'2
A'.
V REF
R14=-- =R15
1.0mA
A2
2.5k
10kn
MSB
LSB
NOTE:
CODE MAY BE COMPLEMENTED BY REVERSING 10 &
CODE FORMAT
OUTPUT SCALE
iQ
MSB
B1 B2
B3
B4
B5
Be
B7
BI
Be
B10
B11
LSB
B12
Straight binB' Y;
Positive full scale
unipolar with true input Positive full scale - LSB
code, true zero output.
LSB
0
leroSeale
Complementary binary;
unipola, with
complementary input
code, true zero output.
0
0
0
Positive full scale
Positive full scale -
0
0
0
0
O·
LSB
LSB
Zero scale
10
i;
(mAl
(mAl
VOUT
3.999
3.999
0.001
0.000
0.000
0.001
3.999
3.999
9.8876
9.9951
0.0024
0.0000
0.000
0.001
3.999
3.999
3.999
3.999
0.001
0.000
9.8876
9.8851
0.0024
0.0000
II
In
a:
SYMMETRICAL OFFSET OPERATION
w
I-
a:
W
>
A'
2.5k
A"
'Ok"
Z
VREF(+)
REF-Ol
+lOV
r--
VREFH
Bl
VREF
R14=- osR15
1.0mA
Al'
10kn
~
B12
±-~'
.".
OUTPUT SCALE
Straight offset binary;
Positive full scale
symmetrical about zero, Positive full scale - LSB
(+) Zero scale
no true zero output.
Negative full scale - LSB
Negative full scale
0
0
0
1
1
0
1
0
0
Positive full scale
Positive full scale - LSB
(+) Zero scale
(-) Zero scale
Negative full scale - LSB
Negative full scale
0
0
0
1
1
1
1
1
0
1
0
0
(-) Zero scale
1's complement;
symmetrical about zero,
no true zero output
MSB complemented
(need inverter at B1).
MSB
111 112
1
1
1
U
V OUT
~
R2
1.25k
A3
2.5k
MSB
NOTE:
CODE MAY BE COMPLEMENTED BY REVERSING 10 &
COD! FORMAT
~
;>-
DAC-312
o
.".
LSB
iQ
10
114
115
116
117
116
118
1110
1111
LSB
1112
10
113
(mAl
(mAl
VOUT
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
0
0
1
1
0
3.999
3.998
2.000
1.999
0.001
0.000
0.000
0.001
1.999
2.000
3.999
3.999
9.8876
9.8827
0.0024
-0.0024
-11.8827
-11.8876
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
0
0
1
1
0
3.889
3.996
2.000
1.999
0.001
0.000
0.000
0.001
1.999
2.000
3.999
3.999
9.8876
9.8827
0.0024
-0.0024
-11.8827
-11.8876
PAGE 10-105
DAC-31212-BIT HIGH SPEED MULTIPLYING D/A CONVERTER
APPLICATIONS INFORMATION
REFERENCE AMPLIFIER COMPENSATION FOR
MULTIPLYING APPLICATIONS
REFERENCE AMPLIFIER SETUP
The DAC-312 is a multiplying D/A converter in which the
output current is the product of a digital number and the
input reference current. The reference current may be fixed
or may vary from nearly zero to +1.0mA. The full range output
current is a linear function of the reference current and is
given by:
AC reference applications will require the reference amplifier to be compensated using a capacitor from pin 16 to V-.
The value of this capacitor depends on the impedance presented to pin 14. For R14values of 1.0, 2.5 and 5.0kO; minimum
values of Ccare 5,10, and 25pF. Larger values of R14 require
proportionately increased values of Cc for proper phase
margin.
where IREF = 114
I n positive reference applications, an external positive reference voltage forces current through R14 into the VREF (+)
terminal (pin 14) of the reference amplifier. Alternatively, a
negative reference may be applied to V REF(-) at pin 15. Reference current flows from ground through R14 into VREF(+) as
in the positive reference case. This negative reference connection has the advantage of a very high impedance presented at pin 15. The voltage at pin 14 is equal to and tracks
the voltage at pin 15 due to the high gain of the internal
reference amplifier. R15 (nominally equal to R14) is used to
cancel bias current errors.
For fastest response to a pulse, low values of R14 enabling
small C c values should be used. I! pin 14 is driven by a high
impedance such as a transistor current source, none of the
above values will suffice and the amplifier must be heavily
compensated which will decrease overall bandwidth and
slew rate. For R14 = lkO and Cc= 5pF, the reference amplifier slews at 4mA!ms enabling a transition from IREF = 0 to
IREF = 1mA in 250ns.
Bipolar references may be accomodated by offsetting VREF
or pin 15. The negative common-mode range of the reference
amplifier is given by: VCM~V-plus (IREFX 3kO) plus 1.SV.
The positive common-mode range is V+ less 1.23V.
Operation with pulse inputs to the reference amplifier may
be accommodated by an alternate compensation scheme.
This technique provides lowest full scale transition times. An
internal clamp allows quick recovery of the reference amplifier from a cutoff (IREF= 0) condition. Full scale transition (0
to 1mAl occurs in 62.5ns when the equivalent impedance at
pin 14 is soon and Cc= O. This yields a reference slew rate of
SmA!!,s which is relatively independent of RINand V IN values.
When a DC reference is used, a reference bypass capacitor is
recommended. A 5.0V TTL logic supply is not recommended
as a reference. I! a regulated power supply is used as a
reference, R14 should be split into two resistors with the
junction bypassed to ground with a O.l!'F capacitor.
LOGIC INPUTS
For most applications the tight relationship between IREFand
I FS will eliminate the need for trimming IREF.I! required, full
scale trimming may be accomplished by adjusting the value
of R14, or by.using a potentiometer for R14. An improved
method of full scale trimming which eliminates potentiometer T.C. effects is shown in the Recommended Full Scale
Adjustment circuit.
The reference amplifier must be compensated by using a
capacitor from pin 16 to V-. For fixed reference operation, a
O.Ol!,F capacitor is recommended. For variable reference
applications, see section entitled "Reference Amplifier Compensation for Multiplying Applications."
MULTIPLYING OPERATION
The DAC-312 provides excellent multiplying performance
with an extremely linear relationship between I FS and IREF
over a range of 1mA to l!,A. Monotonic operation is maintained over a typical range of IREFfrom 100!,A to 1.0mA.
The DAC-312 design incorporates a unique logic input circuit which enables direct interface to all popular logic families and provides maximum noise immunity. This feature is
made possible by the large input swing capability, 40!,A logic
input current, and completely adjustable logic threshold voltage. For V- = -15V, the logic inputs may swing between-5
and +10V. This enables direct interlace with +15V CMOS
logic, even when the DAC-312 is powered from a +5V supply.
Minimum input logic swing and minimum logic threshold
voltage are given by: V-plus (lREFX3kO) plus 1.SV. The logic
threshold may be adjusted over a wide range by placing an
appropriate voltage at the logic threshold control pin (pin 13,
VLC). The appropriate graph shows the relationship between
VLC and VTH over the temperature range, with VTH nominally
1.4 above V LC. For TTL interface, simply ground pin 13.
When interlacing ECL, an IREF:S 1mA is recommended. For
interfacing other logic families, see block titled "Interlacing
With Various Logic Families". For general setup of the logic
control circuit, it should be noted that pin 13 will sink 1. 1mA
typical; external circuitry should be designed to accommodate this current.
PAGE 10-106
DAC-31212-BIT HIGH SPEED MULTIPLYING D/A CONVERTER
tight, typically ±10ppm/oC, with zero scale output current
and drift essentially negligible compared to 1/2 LSB.
ANALOG OUTPUT CURRENTS
Both true and complemented output sink currents are provided where 10 +
= ' FR. Current appears at the "true"
output when a "1" is applied to each logic input. As the binary
count increases, the sink current at pin 18 increases proportionally, in the fashion of a "positive logic" D/A converter.
When a "0" is applied to any input bit, that current is turned
off at pin 18 and turned on at pin 19. A decreasing logic count
increases as in a negative or inverted logic DIA converter.
Both outputs may be used simultaneously. If one of the
outputs is not required it must still be connected to ground or
to a point capable of sourcing IFR; do not leave an unused
output pin open.
ro
The temperature coefficient of the reference resistor R14
should match and track that of the output resistor for minimum overall full scale drift. Settling times of the DAC-312
decrease approxi mately 10% at -5So C; at +12So C an increase
of about 1S% is typical.
fO
Both outputs have an extremely wide voltage compliance
enabling fast direct current-to-voltage conversion through a
resistor tied to ground or other voltage source. Positive
compliance is 2SV above V- and is independent of the positive supply. Negative compliance is +10V above V-.
The dual outputs enable double the usual peak-to-peak load
swing when driving loads in quasi-differential fashion. This
feature is especially useful in cable driving, CRT deflection
and in other balanced applications such as driving centertapped coi Is and transformers.
POWER SUPPLIES
The DAC-312 operates over a wide range of power supply
voltages from a total supply of 20V to 36V. When operating
with V-supplies of-10Vor less, I REF 51 mA is recommended.
Low reference current operation decreases powerconsumption and increases negative compliance, reference amplifier
negative common mode range, negative logic input range,
and negative logic threshold range; consult the various figures for guidance. For example, operation at -9V with 'REF=
1mA is not recommended because negative output compliance would be reduced to near zero. Operation from lower
supplies is possible, however at least BV total must be applied to insure turn-on of the internal bias network.
Symmetrical supplies are not required, as the DAC-312 is
quite insensitive to variations in supply voltage. Battery
operation is feasible as no ground connection is required;
however, an artificial ground may be used to insure logic
swings, etc. remain between acceptable limits.
TEMPERATURE PERFORMANCE
The nonlinearity and monotonicity specifications of the
DAC-312 are guaranteed to apply over the entire rated operating temperature range. Full scale output current drift is
SETTLING TIME
The DAC-312 is capable of extremely fast settling times,
typically 2S0ns at IREF = 1.0mA. JUdicious circuit design and
careful board layout must be employed to obtain full performance potential during testing and application. The logic
switch design enables propagation delays of only 2Sns for
each of the 12 bits. Settling time to within 112 LSB olthe LSB
is therefore 2Sns, with each progressively larger bit taking
successively longer. The MSB settles in 2S0ns, thus determining the overall settling time of 2S0ns. Settling to 10-bit
accuracy requires about 90 to 130ns. The output capacitance of the DAC-312 including the package is approximately 20pF; therefore, the output RC time constant
dominates settling time if RL> soon.
Settling time and propagation delay are relatively insensitive
to logic input amplitude and rise and fall times, due to the
high gain of the logic switches. Settling time also remains
essentially constant for IREF values down to O.SmA, with
gradual increases for lower IREFvalues. The principal advantage of higher IREF values lies in the ability to attain a given
output level with lower load resistors, thus reducing the
output RC time constant.
Measurement of settling time requires the ability to accurately resolve ±2/LA, therefore a 2.SkO load is needed to
provide adequate drive for most oscilloscopes. At IREFvalues
of less than O.SmA, excessive RC damping of the output is
difficult to prevent while maintaining adequate sensitivity.
However, the major carry from 011111111111 to 100000000000
provides an accurate indicator of settling time. This code
change does not require the normal 6.2 time constants to
settle to within ±0.1% of the final value, and thus settling
times may be observed at lower values of ' REF.
DAC-312 switching transients or "glitches" are very low and
may be further reduced by small capacitive loads at the
output at a minor sacrifice in settling time.
Fastest operation can be obtained by using short leads,
minimizing output capacitance and load resistor values,
and by adequate bypassing at the supply, reference, and VLC
terminals. Supplies do not require large electrolytic bypass
capaCitors as the supply current drain is independent of
input logic states; 0.1/LF capacitors althe supply pins provide
full transient protection.
PAGE 10-107
N
l?u
c
c
UI
a:
w
~
a:
w
>
Z
o
U
c
C
DAC-312 12-BIT HIGH SPEED MULTIPLYING DI A CONVERTER
DIFFERENTIAL VI INTEGRAL NONLINEARITY
Integral nonlinearity, for the purposes of the discussion,
refers to the "straightness" of the line drawn through the
individual response points of a data converter. Differential
nonlinearity, on the other hand, refers to the deviation of the
spacing of the adjacent pOints from a 1 LSB ideal spacing.
Both may be expressed as either a percentage of full scale
output or as fractional LSBs or both. The following figures
define the manner in which these parameters are specified.
The leftfigure shows a portion ofthe transfer curve of a DAC
with 1/2 LSB INL and the (implied) DNL spec of 1LSB.
Below this is a graphic representation of the way this would
appear on a CRT, for example, if the D/A Converter output
were to be applied to the Y input of a CRT as shown in the
application schematic titled "CRT Display Driver". On the
right is a portion of the transfer curve of a DAC specified for
2LSB INL with 1/2 LSB DNL specified and the graphic
display below it.
One of the characteristics of an R-2R DAC in standard form
is that any transition which causes a zero LSB change (i.e.
the same output for two different codes) will exhibit the same
output each.time that transition occurs. The same holds true
for transitions causing a 2LSB change. These two problem
transitions are allowable for the standard definition of
monotonicity and also allow the device to be specified very
tightly for INL. The major problem arising from this error
type is in AID converter implementations. Inputs producing
the same output are now represented by ambiguous output
codes for an identical input. Also, 2LSB gaps can cause large
errors at those input levels (assuming 1/2 LSB quantizing
levels). It can be seen from the two figures that the DNL
specified D/A converter will yield much finer grained data
than the INL specified part, thus improving the ability of the
AID to resolve changes in the analog input.
DIFFERENTIAL LINEARITY COMPARISON
D/A CONVERTER WITH
DlA CONVERTER WITH
±2 LSB INL. ±1/2 LSB DNL
±1/2 LSB INL, ±1 LSB DNL
" IDEAL OUTPUTS
• ACTUAL OUTPUTS
1;1 IDEAL OUTPUTS
• ACTUAL OUTPUTS
SEGMENT OF 12~BIT OAC
TRANSFER CURVE FOR:
INL- +2LSB"
DNl- ±1/2LSB
0010 0100 0110 1000 1010 1100 1110 0000
0011 0101 0111 1001 1011 "01 1111 0001
DIGITAL INPUTS
.-...
------
VIDEO DEFLECTION BY DAC's
VIDEO DEFLECTION BY DAC's
1""'----...
- -----
-------.....-
-)I
".
---..
-
ENLARGED "POSITIONAL" OUTPUTS
ENLARGED "POSITIONAL" OUTPUTS
PAGE 10-108
DAC-31212-BIT HIGH SPEED MULTIPLYING D/A CONVERTER
DESCRIPTION OF OPERATION
EXPANDED TRANSFER CHARACTERISTIC
SEGMENT (001 010011)
The OAC-312 is divided into two major sections, an 8segment generator and a 9-Bit master/slave 0/A Converter.
In operation the device performs as follows (See Simplified
Schematic ):
The three most significant bits (MSB's) are inputs to a 3-to-8
line decoder. The selected resistor (R5 in the figure) is
connected to the master/slave 9-Bit 0/A Converter. All lower
order resistors (R1 through R4) are summed into the 10 line,
while all higher order resistors (R6 through R8) are summed
into the TO line. The R5 current supplies 512 steps of current
(0 to 0.499mA for a 1mA reference current) which are also
summed into the 10 or TO lines depending on the bits
selected. In the figure,the code selected is: 100110000000.
Therefore, 2mA (4 X 0.5mA/segment) +0.375mA (from
master/slave 0/A Converter) are summed into 10 giving an 10
of 2.375mA. 10 has a current of 1.625mA with this code. As
the three MSB's are incremented, each successively higher
code adds 0.5mA to 10 and subtracts 0.5mA from TO, with the
selected resistor feeding its current to the master/slave 0/A
Converter; thus each increment of the 3 MSB's allows the
current in the 9-Bit 0/ A Converter to be added to a pedestal
consisting of the sum of all lower order currents from the
segment generator. This configuration guarantees monotonicity.
1,501
1.500
1.499
512 STEPS
1,001
1.000
0.999
(OOl111111111)!
t(0100000000~~)-~010 111111111'!
t(Oll 000000000)
DIGITAL INPUT
II
SIMPLIFIED SCHEMATIC
B2
V(+I
.3
B4
85
86
87
B8
89
810
II)
Bl1
a:
w
a:
w
>
I-
Z
o
U
~
19
,.
COMP
17
vH
PAGE 10-109
10
DAC-31212-BIT HIGH SPEED MULTIPLYING D/A CONVERTER
12-BIT FAST AID CONVERTER
12-8IT FAST AID CONVERTER
SERIAL
DATA OUT
CONVERSION TIME
1.25
liS
I
CLOCK
\
LSB
1.00
~
+15V
::> 0.50
~
REF-Ol
(W06'~~~E'\
CMP-06
0.75
>
~
a:
ACCURACY
r--
DAC-3l
CMP-05
(TVI'
0.26
0.00
100
200
300
"
400
500
\\
600
700
CONVERSION TIME PER TRIAL
800
(nS)
O,l,uF
10.000kn
CONVERSION
TIMElnSI
OAR
CMP..os
TOTAL
NOTE:
DEVICE(S) CONNECTED TO ANALOG INPUT MUST BE CAPABLE OF SOURCING 4.0mA.
A BUFFER (eg. BUF-02) MAY BE REQUIRED.
PAGE 10-110
Xl.
TYP
..
33
WORST
CASE
..
125
375n8
680nS
4.9/.'8
8.81'$
DAC-808
PMI
8-BIT HIGH-SPEED
"MICROPROCESSOR COMPATIBLE"
MULTIPLYING D/A CONVERTER
®
ing existing data in the slave latch which controls the
analog output. The DAC·808 operates in five modes which
are selected by the user under processor control. Data
transfer is accomplished in two 4·bit nibbles, one 4-bit nibble, or one 8·bit byte.
FEATURES
•
•
•
•
•
•
•
•
•
Dual 4·Bit Input Latch Coupled to 8·Blt Latched DAC
8 and 4-Bit ",p Compatible
Easily Interfaced to 8080, and Z·80 Processors
TTL Logic Compatible
Programmable Mode Control
High Output Impedance and Compliance
Proven DAC·08 Analog Flexibility
Nonlinearity to ±0.1% Maximum
Low Power Dissipation ..................... 150mW
The Analog section consists of a "Field·Proven" DAC·08 D/A
Converter. Monotonic multiplying performance is attained
over a wide 40 to 1 reference current range. Matching to
within 1 LSB between reference and full·scale currents
eliminates full·scale adjustments In most applications.
DAC-808 applications include graphic display drivers, high·
speed modems, AID converters, programmable waveform
generators and power supplies, analog meter drivers, audio
encoders and programmable attenuators, and other applica·
tions where low cost, high speed and double·buffering flex·
ibllity are required.
GENERAL DESCRIPTION
The BYTEDACTM DAC-808 is a Double·Buffered Latch Input
Digital·to·Analog Converter designed specifically for 8· and
4·bit microprocessors. The double latch concept allows the
processor to load data in the master latch without disturb-
PIN CONNECTIONS
ORDERING INFORMATIONt
INL
%FS
± 0.1
±
.±
0.19
0.39
MILITARY
INDUSTRIAL
DAC-808A'
DAC-808BX'
DAC-808EX
DAC-808FX
COMMERCIAL
1I1·PIN HERMETiC
DUAL·iN·L1NE
(X·Suffix)
DAC-808GX
Z
I, 12 I, I.
lOB,
.-L
DIGITAL SWITCH
J
1/2 MASTER
LATCH 4-81T
l
CONTROL
LOGIC
16
--r
~
AMP,.......-
V
'2
COMPo
DB,
'V
I
-'I
I
LSB
8
DB,
OBO
~
I
0
I
I
1/2 MASTER
LATCH 4·BIT
.1:)-
I
SLAVE 8-BIT LATCH
I
I
0
8-BIT MULTIPLYING OAe
!"v-
Manufactured under one or more of the following patents:
4.055.773; 4.056,740; 4.092.639
, • ,
os,
lOB. 108, IOB4
J
17
FH'1
w
g
MSB
Y _
R
a:
o
o
EQUIVALENT CIRCUIT
F(+) 10
c
III
a:
w
>
Section 2.
Me
o
cc
I-
• Also available with MIL-STO-8838 processing. To order add/883 as a suffix to
the part number.
tAil listed parts are available with 160 hour burn-In. See Ordering Information,
CE
•
~
18 PIN HERMETIC DUAL INLINE PACKAGE
PAGE 10-111
-¥GNO
2..
!'~Y+
'4
13
'0 UT
'0UT
DAC·808 8-BIT HIGH·SPEED "MICROPROCESSOR COMPATIBLE" MULTIPLYING DIA CONVERTER
ABSOLUTE MAXIMUM RATINGS
v+
Operating Temperature
DAC·808A1B .....................- 55°C to + 125°C
DAC-808E1F . . . . . . . . . . . . . . . . . . . .. - 25 DC to + 85 DC
DAC-B08G .......................... 0De to + 70°C
Dice Junction Temperature ....•....... -65 DC to +150·C
Storage Temperature. . . . . . . . . . . . .. - 65 DC to + 150 °C
Power Dissipation .......................... 300mW
Derate above 100 DC ....................... 10mW/oC
Lead Soldering Temperature ............ 300 DC (60 sec)
Supply to V - Supply ...................... 18.1V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . .. OV to 5.5V
Analog Current Outputs ....................... - 5mA
Reference Inputs (V14' V1S) . . . . . . . . . . . . . . . .. V - to V +
Reference Input Differential Voltage
(V14 to V1S) ................................ ± 15V
Reference Input Current ...................... 5.0mA
NOTE: Absolute ratings apply to both DICE and packaged parts unless
otherwise noted.
_55 D C to +125 DC for DAC·B08A1B, unless otherwise
noted. TA = - 25 DC to + B5 DC apply for DAc..aoaElF; T = 0 DC to + 70 DC apply for DAC-B08G. Output characteristics refer to both 1001 and
ELECTRICAL CHARACTERISTICS at V+ = +5V, V- = -12V, IREF =2.0mA, TA =
DAC·808A1E
PARAMETER
SYMBOL
CONDITIONS
MIN
TVP
iOuT.
DAC.8Q88/F
MAX
MIN
TVP
DAC·808G
MAX
MIN
Resolution
8
Monotonlclty
8
Nonlinearity
Output Voltage
Compliance
±10
See Note
Voe
Full Scale Current
Change < VJ: LSB
-5
±10
±50
+8
-5
±10
±80
+8
MAX
UNITS
Bits
:1:0.19
::to.l
Full Scale Tempco
TVP
-5
±O.39
%FS
±80
ppm/DC
v
+8
_O_m~pm
__lm~~
__M
__
c.____~RO~U~T__________________________>_~____________________
>_~__~_______________>_~
______________
VREF=5.ODV
Rll.Rl0=2.500kO
TA=25'C
Full Range CUrrent
1.94
FUll Range
Symmetry
Zero Scale Current
IZS
Output Current
V- = -12V
Range
Reference Bias
Current
Reference Input
Slew Rate
dlldt
V+ =4.5V to 5.5V
Power Supply
Current
Power Dissipation
4.0
-
V- = -4.5V to -12V
Sensitivity
Power Supply
See Note
IREF=lmA
1+
1-
Vs= +5V. -12V
IREF=2.0mA
+5V. -12V.
IREF=2.0mA
logic Input Levels
logic Input ''0''
logic Input "1"
1.99
2.04
±8.0
±1.0
2.0
0.2
2.0
2.1
-1.0
-3.0
1.99
2.04
%1.0
0.2
8.0
1.94
4.0
1.99
2.04
±8.0
±1.0
±8.0
2.0
0.2
. 2.0
2.0
2.1
2.0
2.1
-1.0
-3.0
-1.0
-3.0
8.0
1.94
4.0
8.0
Mn
mA
mA
mAl..
%AIFS
%AV+
%AIFS
%AV-
±0.0003
±O.01
0.0003
±O.01
±O.OOO3
±O.01
±O.OO2
±O.01
±O.OO2
±O.01
±O.OO2
±O.01
12
6
16
9
12
16
9
12
6
16
1~
170
1~
170
1~
170
mW
0.8
v
0.8
0.8
2.0
2.0
NOTE: Not 100% tested, guaranteed by design.
PAGE 10-112
-
2.0
mA
DAC·808 8·BIT HIGH·SPEED "MICROPROCESSOR COMPATIBLE" MULTIPLYING D/A CONVERTER
ELECTRICAL CHARACTERISTICS -
A.C. PARAMETERS Vs= +5V, -10V, IREF= 2.0mA, TA = 25°C, unless otherwise
noted.
DAC-808A1E
PARAMETER
SYMBOL
CONDITIONS
ts
From CE Negative Edge to
± V. LSB, All Bits Switched ON
or OFF, See Note
Data Input Setup Time
tos
See Note
Data Input Hold Time
tOH
See Note
Address Input Setup Time
(Bits 7 and 6)
tAS
4·Bit Mode, See Note
Settling Time
MIN
50
TYP
MAX
300
500
DAC-808B/F
MIN
30
30
150
100
50
100
TYP
MAX
UNITS
300
500
ns
100
ns
30
30
150
100
ns
ns
Address Hold Time
tAH
4·Bit Mode, See Note
Chip Enable Negative Hold Time
tENH
See Note
250
100
250
100
ns
Chip Enable Positive Hold Time
tEPH
See Note
350
200
350
200
ns
0
10
10
ns
NOTE:
Guaranteed by design.
DAC·808 PIN DESCRIPTION
SYMBOL
DESCRIPTION
DBO·DB?
DATA BIT -
CE
CHIP ENABLE -
MC
MODE CONTROL -
lourlOUT
CURRENT OUTPUT -
VREF-, VREF+
VOLTAGE REFERENCE -
COMP
COMPENSATION -
Bits 0·7 are digital, active·hlgh Inputs that have DB7 assigned the MSB.
An actlve·low input control serving a dual purpose in that it's both the device enable and chip write input terminal.
A control that places the DAC In a·bit operation when low and 4·bit operation when high.
Complementary current outputs when added equal IFS'
Differential inputs that accept a negative, positive, or bipolar input and are used to adjust IFS'
The reference amplifier frequency compensating terminal.
FUNCTIONAL DIAGRAM AND TIMING DIAGRAM FOR 8·BIT OPERATION
I/)
TO 8-BIT DATA BUS
a::
...wa::
DATA
w
INPUT
>
Z
o
u
CHIP
ENABLE
,.
+5.DOOV
VREF+
lOUT
OAC
11
lOUT
-
,.
lOUT
.-.
tos.
MASTER
LATCH
OUTPUT
13
,.
2."
-::-
lOUT
'OUT
-lOY
+5V
PAGE 10-113
X
'=1
'C..
a
DAC-808 8-BIT HIGH-SPEED "MICROPROCESSOR COMPATIBLE"MULTIPLYING D/A CONVERTER
DICE CHARACTERISTICS
1. DB7(MSB)
12.DB8
3.DB5
4.DB4
5.DB3
8.DB2
7.DB1
8. DBO(LSB)
9. GROUND
10.
11.
12.
13.
14.
15.
16.
17.
18.
VREF(+)
VREF(-)
COMP
lOUT
lOUT
V
MODE CONTROL
CE
V+
DIE SIZE 0.138 X 0.125 Inch
Refer to Section 2 for additional DICE Information.
ELECTRICAL CHARACTERISTICS
characteristics refer to both lOUT and
PARAMETER
SYMBOL
at
lOUr.
25°C; Vs = +5V, -12V
and IREF
= 2.OmA,
unless otherwise noted. Output
DAC-SOSN
DAC-SOSG
LIMIT
LIMIT
LIMIT
UNITS
8
8
Bits MIN
CONDITIONS
Resolution
Monotoniclty
Nonlinearity
DAC-S08GR
8
8
±0.1
±o.19
±0.39
%FSMAX
Bits MIN
Output Voltage
Compliance
Voe
Full Scale Current
Change < 1/2 LSB
ROUT> 20 MO Typ.
+8
-5
+8
-S
+8
-5
V MAX
VMIN
Full Range Current
IFR14
VREF=S,OOV
R 11 , R,o = 2.SookO
T A =2S'C
2.04
1.94
2.04
1.94
2.04
1.94
mAMAX
mAMIN
Full Range Symmetry
I FRS
IFRI4-IFRI3
±8.0
±8.0
±8.0
~AMAX
Zero Scale Current
Izs
2.0
2.0
2.0
~MAX
Output Current
Range
I FSR
2.1
0
2.1
0
2.1
0
mAMAX
mAMIN
Reference Bias Current
Ie
-3.0
-3.0
-3.0
~AMAX
±0.01
±O.Ol
±0.01
±o.01
±o.01
±0.Q1
%AIFsI%AV+ MAX
%
Z
0
(J
c(
.....
C
DAC·808 8-BIT HIGH·SPEED "MICROPROCESSOR COMPATIBLE" MULTIPLYING D/A CONVERTER
DIGITAL INFORMATION
bles which are assembled at the slave latch into an 8-bit
byte (refer to Function Table). Modes 4 and 5 transfer a
single 4-bit nibble only.
The DAC·808 is a monolithic microprocessor compatible
device consisting of a quad digital switch, two 4·bit master
latches, one 8·bit slave latch, control circuitry, and one 8·bit
multiplying DAC; all housed in an 18'pin Dual In·line
Package.
LOADING LSB NIBBLE FIRST, MODE #2
For all 4-bit operations the MC pin must be high. A low must
be applied to Data Bit 6 (DB6) which now acts as an address
pin. Data is brought in at DBO through DB3 and clocked into
the LSB master latch on the negative transition of CEo
Nothing occurs on the positive transition of the CE's first
cycle. DB6 must now go high to enable the second master
latch which is loaded through the digital switch on the next
negative transition at CEo Both the MSB and LSB nibbles are
then loaded in the slave latch on the positive transition at
CEo Data Bit 7 (DB7) must remain low in this mode.
The DAC-808 can be thought of, in the 4·bit mode, as a quad
1 to 2·line digital demultiplexer which selects a 4·bit input
and transfers this data to one of two 4·bit master latches.
The BYTEDACTM accepts a straight binary digital byte at the
master latch which is a fast edge·trlggered device. Two 4·bit
independent latches make up the master latch and are
clocked separately depending on the state of the Mode Con·
trol (MC). The second latch, or slave latch, is 8 bits and con·
nects directly with the DAC. The Chip Enable (CE) is used to
clock data to and from both latches. When CE is high, the
DAC will output a current equal to the last digital value
entered (refer to the Equivalent Circuit).
LOADING MSB NIBBLE FIRST, MODE #3
This mode is identical to Mode 2 except DB7 remains high
and DB6 is high during the first cycle and low during the
second cycle. The MSB nibble is loaded into the master
latch through the digital switch during the first CE cycle.
The second CE cycle loads LSB nibble and transfers all 8
bits to slave latch and DAC.
8·BIT TRANSFER MODE #1
To load 8·bit parallel data, a low must be present at MC
which sets both master latches in a condition for simul·
taneous clocking. The negative transition on CE will now
transfer data to the master latch while the positive transac·
tion clocks data to the slave latch and input to the DAC (see
the Timing Diagram). The CE line can be held low for an indefinite period to prevent data transfer.
LOADING 4 BITS (DBO THROUGH DB3), MODE #4
By applying a low at MC and entering data at DBO through
DB3, 4 bits of data can be loaded. Again, the nibble is latched
into the LSB master latch on negative CE and clocked to the
lower slave inputs at CE positive. DB7 must be high and DB6
must be low. The MSB nibble will contain and hold the last
data entered into it. If four LSBs of resolution are all that will
be required, the data may be entered in the 8-bit mode with
MC low and DB4 through DB7 tied high or low.
INTERFACE TO 4·BIT BUS
The DAC-808 is able to handle 4-bit data in four ways, which
will be discussed here. Modes 2 and 3 transfer two 4-bit nib-
DAC·808 EQUIVALENT CIRCUIT
MSB
I, I,
I DB7
~
CE
J
I
DIGITAL SWITCH
J
1/2 MASTER
lOGIC
MC
,.
-rF(+) 10
FH 11
~
AMP
VFIGURE 1.
~')
I
I
I
•
I
LATCH 4-BIT
I
I
S
6
7
8
DB3
DB,
DB,
DBO
1/2 MASTER
LATCH 4-81T
0
~)
I
8-BIT MULTIPLYING OAC
),',v-"
PAGE 10-116
~GND
I
J
SLAVE 8-81T LATCH
I
"COMPo
LSB
0
17
CONTROL
I.
13
I DB6 IDB5 IDB.
)
),'.8v+
,.
'0UT
'3
'0UT
DAC·808 8·BIT HIGH·SPEED "MICROPROCESSOR COMPATIBLE" MULTIPLYING D/A CONVERTER
LOADING 4 BITS (DB4 THROUGH DB7), MODE #5
This is the same as Mode 4 except that DB7 is now low and
DB6 is now high. The data is still entered into DBO through
DB3, but the data is now loaded into the MSB nibble. The
LSB nibble will contain and hold the last data entered into it.
If 4 MSBs of resolution are all that will be required, the data
may be entered in the B·bit mode with MC low and DBO
through DB3 tied high or low.
ANALOG INFORMATION
BASIC POSITIVE REFERENCE OPERATION
Msa
LSB
DB7 DBS DBs 084 DB3 DB2 DB1 DBo
,.-
RREF
+5.000V
Rl0 10
DAC
IREF-.
255
IFR = 256 X IREF where IREF = 110
In positive reference applications, an external positive
reference voltage current flows through R1Q into the VREF( +)
terminal of the reference amplifier. Alternatively, a negative
reference may be applied to VREF (_); reference current flows
from ground through RlO into VREF(+) as in the positive
reference case. This negative reference connection has the
advantage of a very high impedance presented at pin 11.
The voltage at pin 10 is equal to and tracks the voltage at
pin 11 due to the high gain of the internal reference
amplifier. R11 (nominally equal to R1Q) is used to cancel bias
current errors; Rn may be eliminated with only a minor in·
crease in error.
For most applications the tight relationship between IREF
and IFR will eliminate the need for trimming ' REF . If required,
full·scale trimming may be accomplished by adjusting the
value of RlO or by using a potentiometer for RlO • An improved
method of full·scale trimming which eliminates pot en·
lOUT
lOUT
REF
may vary from nearly 0 to + 4.0mA. The full range output
current is a linear function of the reference current and is
given by:
~'1'~--~~~~__~G~ND~~~~T'~----~'3~~
BASIC NEGATIVE REFERENCE OPERATION
Msa
•
LSB
~
OB7 DBe DBs 084 DBa DB2 DBl DBO
R"
o
CC
~O.'.F
Q
VREF .~
1REF:II 256
FOR FIXED REFERENCE, TTL OPERATION TYPICAL
VALUES ARE:
,- _
FF -
RREF = 2.5000k
Rl1 = RREF
VLC" OV (GROUND)
lOUT + lOUT'" IFR
FOR ALL LOGIC STATES
0-
en
II:
W
l-
II:
RREF
____~" lOUT
r~R~'O~,o4-__~~~----~~~\VREF+
lOUT
DAC
-VREF o-"'R"''',..,''I,I----I
REFERENCE AMPLIFIER SETUP
'FR ..
BASIC UNIPOLAR NEGATIVE OPERATION
MSS
LSB
DB7 DBS DB5 DB4 DB3 DB2 DBl oBO
DB7 DB6 DBS DB4 DB3 DB2 DB1 DBO lomA lomA
FULL SCALE -1 LSB 1
FULL SCALE -2 LSB 1
IREF ""
2.000mA
HALF SCALE + LSB
HALF SCALE
HALF SCALE - LSB
ZERO SCALE
ZERO SCALE
1
+ LSB 0
PAGE 10-117
0
Z
oo
~
=YBff xm
RREF
256
NOTE: RREF sers IFS: R11 IS FOR BIAS CURRENT CANCELLATION.
The DAC-808 is a multiplying D/A converter in which the out·
put current is the product of a digital number and the input
reference current. The reference current may be fixed or
W
>
Eo
EO
1.992 0.000 - 4.980 0.000
1.984 0.008 - 4.960 - 0.020
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
1.008 0.984 - 2.520 - 2.460
1.000 0.992 - 2.500 - 2.480
0.992 1.000 - 2.480 - 2.500
0.008 1.984 - 0.020 - 4.960
0.000 1.992 - 0.000 - 4.980
DAC·aoa 8-BIT HIGH·SPEED "MICROPROCESSOR COMPATIBLE" MULTIPLYING DlA CONVERTER
TABLE 1. REFERENCE AMPLIFIER COMPENSATION
RECOMMENDED FULL SCALE ADJUSTMENT CIRCUIT
REF. INPUT RESISTANCE
Msa
LSB
SUGGESTED Cc
lSpF
lkO
2.SkO
Sk!l
DB7 DEI& DBs OB4 DB3 DB2 DB1 DBo
37pF
75pF
NOTE: A O.Q1~F capacitor is suggested for fixed
references.
For fastest response to a pulse, low values of Rl0, enabling
small Cc values, should be used. If pin 10 Is driven by a high
current source, none of the above values will suffice and the
amplifier must be heavily compensated which will decrease
overall bandwidth and slew rate. For Rl0 = 1kO and
Cc=15pF, the reference amplifier slews at 4mAlj£S, enabl·
ing a transition from IREF = 0 to IREF = 2mA in 500ns (see
Figure 6).
IREF+ "" C>"2m~A~~~_-I-;,;;;--....I."--:~.--_-I--o
+6.ooov
REF
60k
POT
tiometer TC effects is shown in the Recommended Full
Scale Adjustment Circuit.
Using lower values of reference current reduces negative
power supply current and increases reference amplifier
negative common mode range. The recommended range for
operation with a DC reference current is + 0.2mA to
+4.0mA.
The reference amplifier must be compensated by using a
capacitor from pin 12 to V -. For fixed reference operation,
a 0.011£F capacitor is recommended. For variable reference
applications, see "Reference Amplifier Compensation for
Multiplying Applications" section.
REFERENCE AMPLIFIER COMPENSATION FOR
MULTIPLYING APPLICATIONS
AC reference applications will require the reference amplifier
to be compensated using a capacitor from pin 12 to V -.
The value of this capacitor depends on the Impedance
presented to pin 10 (see Table 1).
Bipolar references may be accommodated by offsetting
VREF or pin 11, as shown in Figure 5. The negative common
mode range of the reference amplifier is given by VCM = Vplus (I REF x 1kO) plus 2.5V. The positive common mode
range is V + less 1.5V.
When a DC reference Is used, a reference bypass capacitor
is recommended. A 5.0V TIL Logic supply is not recom·
mended as a reference. If a regulated power supply is used
as a reference, Rl o should be split Into two resistors with
the junction bypassed to ground with a 0.1"F capacitor.
ANALOG OUTPUT CURRENTS
Both true and complemented output sink currents are pro·
vided, where 10 +10= IFR. Current appears at the "true" out·
put when a "1" Is applied to each logic Input. As the binary
count increases, the sink current at pin 14 Increases propor·
tionally in the faShion of a "positive logic" D/A converter.
When a "0" Is applied to any input bit, that current is turned
off at pin 14 and turned on at pin 13. A decreasing logic
count Increases TO as In a negative or inverted logic D/A con·
verter. Both outputs may be used simultaneously. If one of
the outputs Is not required It must stili be connected to
ground or to a point capable of sourcing IFs; do not leave an
unused output pin open.
AC.COMMODATING BIPOLAR REFERENCES
lisa
DB7 DBa DBs DB4 DB3 DB2 DB1
LSB
Msa
DBo
087 CBe DDs 084 DB3 DB2 DB1 DBO
LBB
RREF
lIN
~~IN~~~~~~_-I-;,;;;--~"--:~.--_-I-o
RREF 10
VREF+
+VREF
RIN
lOUT
DAC
-
VIN""o
Rll 11
VREF-
(OPTIONALI
HIGH INPUT
IMPEDANCE
RREF'" R11
+VREF MUST BE ABOVE PEAK POSITIVE SWING OF VIN
PAGE 10-118
lOUT
DAC·808 II-BIT HIGH·SPEED "MICROPROCESSOR COMPATIBLE" MULTIPLYING D/A CONVERTER
ALTERNATE PULSED REFERENCE OPERATION
MSB
LaB
DB7 DBs DB5 DB4 083 DB2 DB1 DBO
+VREF
'i'
OPTIONAL RESISTOR
:S.
FOR OfFSET INPUTS ~~
ovJL
RIN
10
TVPICAL VALUES:
RIN-5k
+VIN= lOV
NO CAP
POSITIVE LOW IMPEDANCE OUTPUT OPERATION
MSB
•
LSB
DB7 DBS DBS DB4 DB3 DB2 DBl DBo
RL
EOUT
'FR "" : : 'REF
FOR COMPLEMENTARV OUTPUT (OPERATION AS NEGATIVE LOGIC DACI.
CONNECT INVERTING INPUT OF OP·AMP TO 'OUT. CONNECT lOUT TO
GROUND.
NEGATIVE LOW IMPEDANCE OUTPUT OPERATION
lisa
LS8
DB7 DBa CBs 084 DB3 DB2 DBl DBo
>-+--oEOUT
·-IFS' RL
IFR",,::IREF
RL
FOR COMPLEMENTARY OUTPUT (OPERATION AS NEGATIVE LOGIC DAe),
CONNECT INVERTING INPUT OF OP-AMP TO lOUT. CONNECT lOUT TO
GROUND.
PAGE 10-119
DAC-808 8-BIT HIG.H·SPEED "MICROPROCESSOR COMPATIBLE" MULTIPLYING D/A CONVERTER
BASIC BIPOLAR OUTPUT OPERATION
Msa
Lsa
087 DB6 DBs D84 DB3 DB2 DB, DBO
s.ooov
"=t----(VREF+
_'0
DB7
IOUTrr---t'-'o---'
OAe
DBS
DB6
DB4
DB3
DB2
POSITIVE FUll SCALE
POSITIVE FUll SCALE - lSB
DBl
1
DBO
EO
1
-4.960
-4.920
5.000
4.960
-0.040
0.000
0.040
0.080
0.040
0.000
4.900
5.000
-4.920
-4.960
0
ZERO SCALE + LSB
ZERO SCALE
ZERO SCALE - lSB
0
NEGATIVE FUll SCALE + lSB
NEGATIVE FUll SCALE
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
Both outputs have an extremely wide voltage compliance,
enabling fast direct current·to·voltage conversion through a
resistor tied to ground or other voltage source. Positive
0
0
0
0
0
0
0
1
1
1
0
0
Eo
compliance is 18V above V - and is independent of the
positive supply. Negative compliance is given by V - plus
(IREF x 1kO) plus 2.5V.
OFFSET BINARY OPERATION
MSB
LSB
DB7 DB6 DBs DB4 DBa DB2 DBt DBO
+10V
s.ooov
5k
5.Ok
+5V
VOUT·~·~~~t--~r-V;R;'EF:+----~--~'O;U;T"---4~L-~,
REf-02
OAC
EOUT
lOUT
2.Sk
+5V
DB7
DB6
DBS
DB4
-::-
DB3
DB2
DBl
POSITIVE FUll SCALE -1 lSB
POSITIVE FUll SCALE - 2 lSB
DBO
0
ZERO SCALE
0
0
0
0
0
NEGATIVE ZERO SCALE +2 LSB
NEGATIVE FUll SCALE + 1 lSB
0
0
0
0
0
0
0
0
0
0
0
PAGE 10-120
0
0
Eo
4.960
4.920
0
0.000
1
0
-4.960
-S.OO
DAC·808 II-BIT HIGH·SPEED "MICROPROCESSOR COMPATIBLE" MULTIPLYING D/A CONVERTER
The dual outputs enable double the usual peak·to·peak load
swing when driving loads in quasi·dlfferential fashion. This
feature is especially useful in cable driving, CRT deflection
and in other balanced applications such as driving center·
tapped colis and transformers.
Symmetrical supplies are not required, as the DAC-808 is
quite insensitive to variations in supply voltage.
Power consumption may be calculated as follows:
Pd=(1 +) (V +)+(1-) (V -)+(2IREF) (V -).
TEMPERATURE PERFORMANCE
POWER SUPPLIES
The DAC·808 operates over a wide range of power supply
voltages from a total supply of 9V to 15V. When operating at
supplies of ± 5V or less, IREF s 1rnA is recommended. Low
reference current operation decreases power consumption
and Increases negative compliance, reference amplifier
negative common mode range, negative logic input range,
and negative logic threshold range; consult the various
figures for guidance. For example, operation at - 4.5V with
IREF = 2mA is not recommended because negative output
compliance would be reduced to near zero. Operation from
lower supplies is possible. However, at least 8V must be ap·
plied to Insure turn·on of the internal bias network.
The nonlinearity and monotonicity specifications of the
DAC-808 are guaranteed to apply over the entire rated
operating temperature range. FulI·scale output current drift
is tight, typically ± 1Oppm/DC, with zero scale output current
and drift essentially negligible compared to 1/2 LSB.
Full·scale output drive performance will be best with + 5.0V
reference, as Vos and TCVos of the reference amplifier will
be very small compared to 10.0V. The temperature coeffi·
cient of the reference resistor R10 should match and track
that of the output resistor for minimum overall full·scale
drift. Settling times of the DAC-808 decrease approximately
10% at -55 DC; at +125 DC an increase of about 15% is
typical.
APPLICATIONS
II
8080 MICROPROCESSOR INTERFACE - a·BIT TRANSFER
!
"I'
CJ
cc
c
822.
BOB.
MICROPROCESSOR
SYSTEM
CONTROL
AI51---r),_~t--fci;---Dai~iB1-----'
fI)
II:
11/
lII:
11/
~---fv:VR;:.E::F+--.L-=..--;':;;;OU:;;T\----0'--oIOUT
LXI H, 8000 - SETS MEMORY MICROPROCESSOR
MOV M, A - WRITES DATA FROM ACCUMULATOR
TO OAe.
DAC
PAGE 10·121
>
Z
o
CJ
~
PMI
DAC-BBB
8·BIT HIGH·SPEED
"MICROPROCESSOR COMPATIBLE"
MULTIPLYING D/A CONVERTER
®
FEATURES
•
•
•
•
•
•
•
•
•
interface to virtually all available microprocessors. The
latches may also be operated in a transparent mode by holding both control pins low. Additionally, the DAC-888 has a
data hold time requirement of zero nanoseconds.
The Analog section consists of a "Field-Proven" DAC-08 OfA
Converter. Monotonic multiplying performance Is attained
over a wide 40 to 1 reference current range. Matching to
within 1 LSB between reference and full-scale currents
eliminates full-scale adjustment in most applications.
8-BII Levei Triggered Lelch
8-BII pP Compellble
Easily Inlerfaced 10 All 8-BII Proceslors
TTL Logic Compallble
CE andWR Inpull
High Oulpullmpedance and Compliance
Proven DAC-08 Analog Flexibility
Nonlinearity 10 ±O.1% Maximum
Low Power Dlilipalion ..................... 134mW
DAC-888 applications Include graphic display drivers, highspeed modems, AID converters, programmable waveform
generators and power supplies, analog meter drivers, audio
encoders and programmable attenuators; and other applications where low cost, high speed and buffered flexibility are
required.
GENERAL DESCRIPTION
The BYTEDAC" DAC-888 is a buffered 8-bit digltal-to-analog
converter designed specifically for 8-blt bus oriented syslems. The data inputs are connected to level-triggered
latches. Two active-low control pins are provided for ease of
PIN CONNECTIONS
ORDERING INFORMATIONt
11·PIN HERMETIC DUAL INLINE
INL
"!oFS
MILITARY
TEMP.
COMMERCIAL
TEMP.
0.1
0.19
DAC888AX'
DAC888BX'
DAC888EX
DAC888FX
111-PIN HERMETIC
DUAL·IN·LINE
(X Suffix)
• Also available with MIL-ST0-883B processing. To order add/883 as asufflxto
the part number.
t All listed parts are available with 160 hour burn-in. See Ordering Information,
Section 2.
OB,
7
lSB DBa
8
FUNCTIONAL DIAGRAM
Da, D" D" DB, DB3
DB:!
DB, DIIo
MSB
7 f--...q
liE 0---='''-1
8-8IT LATCH
8 f--...q
iiii 0---=''''1
'r------+';;.'--oIOUT
8-8IT MULTIPL VING OAC
f------+'~3--oI00T
COMP
Manufactured under one or more· of the following patents:
4,055,773; 4,056,740; 4,092,639
v-
PAGE 10·122
GND
v+
DAC-888 8-BIT HIGH-SPEED "MICROPROCESSOR COMPATIBLE" MULTIPLYING DIA CONVERTER
ABSOLUTE MAXIMUM RATINGS
Operating Temperature
DAC-888 AlB ...•.•••••.•...•......•• -55°C to +125°C
DAC-888 ElF ..................•....•. -25°C to +85°C
DICE Junction Temperature (T j ) ••••••• -65°C to +150°C
Storage Temperature .................. -65°C to +150°C
Power Dissipation ..•...................•.••.... 300mW
Derate above 100°C ......•..................• 10mW/oC
Lead Soldering Temperature ............. 300° C (60 sec)
V+ Supply to V- Supply •.........•••..•....•...•.. 18.1V
Logic Inputs ..............•••......•.•...... OV to 5.5V
Analog Current Outputs .............••........... -5mA
Reference Inputs (V 14 to V IS) ..........•...... .. V- to V+
Reference Input Differential Voltage
(V I4 tOV ,S ) ....•.•.•....•.•••••••••••••••••••••• ±15V
Reference Input Current .......................•. 5.0mA
NOTE: Absolute ratings apply to both DICE and packaged parts unless
otherwise noted.
ELECTRICAL CHARACTERISTICS at V+ = +5V, V-= -12V, IREF= 2.0mA, TA = -55°C to +125°C for DAC-888A/B,
unless otherwise noted. T A = -25° C to +85° C apply for DAC-888E/F; Output characteristics refer to both lOUT and lOUT'
DAC-888A1E
PARAMETER
SYMBOL
MIN
CONDITIONS
Resolution
8
Monotonicity
8
TVP
8
Nonlinearity
Full Scale Tompco
Output Impedance
MIN
TVP
MAX
UNITS
8
8
8
8
Bits
8
8
±0.1
TCI FS
(Seo noto)
Vee
Full Scale Current
Chango < 112 LSB
Output Voltage
Compliance
DAC-888B/F
MAX
±10
-5
±50
+8
Bits
-
±O.19
%FS
±10
±80
ppm/"C
+8
V
-5
>20
ROUT
8
Mil
>20
V REF =5.00V
Full Range Current
IFA
Full Range
Symmetry
'FRS
Zero Scale Current
IZS
Output Currenl
Range
Reference Bias
Current
0
'FSR
2.04
mA
±8.0
±1.0
±8.0
I'A
2.0
0.2
2.0
p.A
2.04
±1.0
0.2
1.94
II
2.0
2.1
0
2.0
2.1
mA
6c
C
U)
a:
W
I-1.0
-3.0
-1.0
-3.0
p.A
-±0.0003
-±0.0002
±O.OI
0.Q1
-±0.OO03
-±0.OOO2
±0.01
0.Q1
%
'REF=2.0mA
C
Logic Input Levels
Logic Input "0"
Logic Input "1"
vll
Logic Input Current
Logic Input "0"
Logic Input "1"
III
-S
-S
IIH
+0.1
+0.1
0.8
2.0
VIH
NOTE: Guaranteed by design
PAGE 10-123
0.8
2.0
V
p.A
DAC-BBB B-BIT HIGH-SPEED "MICROPROCESSOR COMPATIBLE" MULTIPLYING 0/A CONVERTER
ELECTRICAL CHARACTERISTICS- A.C. PARAMETERS Vs
= + 5V, -
12V, IREF
= 2.0mA, TA = 25°C
DAC-888A1E
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
100
250
DAC-888B/F
MIN
TYP
MAX
UNITS
100
250
ns
From CE & WR Negative Level to
SeHllng Time
±1/2LSB, All Bits Switched ON
IS
or OFF, (See note)
Reference Input
dl/dt
(See Note)
4.0
Data Input Setup Time
tos
(See note)
150
150
Data Input Hold Time
tOH
(See note)
10
10
ns
Chip Enable/Write Pulse Width
tENW
(See note)
250
250
ns
Slew Rate
8.0
4.0
8.0
mA/p.s
ns
NOTE: Guaranteed by design
DAC-888 PIN DESCRIPTION
SYMBOL
DESCRIPTION
PINS 1·8
DBO~DB7
DATA BIT - Bits 0·7 are digital, active-high inputs. DB7 is assigned as the MSB.
CE
WR
CHIP ENABLE - An active-low Input control which Is the device enable input terminal.
PIN 17
WRITE CONTROL - An active low control which enables the microprocessor to write data to the CAe.
PIN 16
lOUT. lOUT
CURRENT OUTPUT - Complementary current outputs when added equallFS'
VRER ,VREF- VOLTAGE REFEREN9E -
COMP
COMPENSATION -
PINS 13·14
PINS 10·11
Differential inputs that accept a negative, positive, or bipolar input and are used to adjust IFS'
PIN 12
The reference amplifier frequency compensating terminal.
FUNCTIONAL DIAGRAM AND TIMING DIAGRAM FOR 8-BIT OPERATION
'~
TO 8·BIT DATA BUS
DATA
INPUT - - - - - - - - - - -
I
VAL'O
~tOH
iiiR:cE - - - - - - - - -...
+5.000Vo-~~!_--.r;;V:R;,EF;:+---"'--;'O~U~T~---t;:-~
lOUT
W
M
OAe
'OUT
-----------:;~.,...,'7"l
'OUT
---------r::~~~
10U~
"
13
2.5k!----:::I--:-:-:-:-I:::--t--+.::----..I
-12V
NOTE: If input data changes after WR. CE low. lOUT/lOUT will change.
The last data input before WR + CE high will be latched. It Is suggested, but
not mandatory, that data be valid from WR • BE low to WR + CE high.
+5V
OPERATION TABLE
OUTPUT
o
o
x
NO CHANGE
o
UPDATE LATCHES (TRANSPARENT)
NO CHANGE
PAGE 10-124
DAC-888 8-BIT HIGH SPEED "MICROPROCESSOR COMPATIBLE" MULTIPLYING D/A CONVERTER
DICE CHARACTERISTICS
1. DB7(MSB)
2. DB6
3. DB5
4.,DB4
5. DB3
6. DB2
7. DB1
8. DBO (LSB)
9. GROUND
10. VREF (+)
11. VREF (-)
12. COMP
13.
14.
15.
16.
17.
18.
lOUT
lOUT
VWR
CE
V +
DIE SIZE 0.138 X 0.125 inch
Refer to Section 2 for additional DICE information.
ELECTRICAL CHARACTERISTICS
at 25°C; Vs = +5V, -12V and IREF = 2,0 mA, unless otherwise noted. Output
characteristics refer to both lOUT and lOUT'
PARAMETER
CAC-888N
CAC-888G
LIMIT
LIMIT
SYMBOL CONDITIONS
Resolution
8
Monotonicity
Nonlinearity
Output Voltage
Compliance
Voc
Full Scale Current
Change < 1!2 LSB
ROUT> 20 MO Typ.
UNITS
Bits MIN
8
Bits MIN
±O,1
±O,19
%FSMAX
+8
-5
+8
-5
2,04
1,94
2,04
1,94
VMAX
VMIN
IFR14
5,00V
Rl1 , R'0 ~ 2,500kO
TA~25°C
Full Range Symmetry
I FRS
Zero Scale Current
I zs
Output Current
Range
I FSR
Reference Bias Current
Ie
Power Supply
Sensitivity
PSSI FR +
PSSI FR -
Power Supply
Current
1+
1-
Power Dissipation
Pd
Logic Input Levels
Logic Input "0"
Logic Input "1"
VIL
V IH
'FR14- I FR13
V-~-12V
IREF~
~
1mA
+5V, -12V
+5V, -12V,
IREF~2,OmA
SYMBOL CONDITIONS
Reference Input Slew Rate
dl!dt
Settling Time
ts
0
II)
±8,0
~AMAX
2.0
2,0
~AMAX
lII:
2.1
0
2,1
0
mAMAX
mAMIN
>
Z
-3,0
-3,0
~AMAX
±om
±om
±O,01
±0,01
%al FsI%av+ MAX
%aIFsI%aV- MAX
16
16
9
mAMAX
mAMAX
170
170
mWMAX
0,8
2.0
0.8
2.0
V MAX
VMIN
II:
W
Vs
=+
5V, - 12V, IREF
= 2.OmA, TA = 25°C, unless otherwise noted.
CAC-888
PARAMETER
c(
±8,0
IREF~2,OmA
TYPICAL ELECTRICAL CHARACTERISTICS
mAMAX
mAMIN
W
0
0
c(
V+ ~ 4,5V to 5,5V
V-~-4,5V to -12V
Vs
CD
CD
"P
0
VREF~
Full Range Current
III
From CE Negative Edge to
±1!2 LSB, All bits Switched
ON or OFF
TYPICAL
UNITS
8,0
mA/~s
100
ns
Data Input Setup Time
tos
100
ns
Data Input Hold Time
tOH
0
ns
Chip Enable!
Write Pulse Width
tENW
200
ns
PAGE 10-125
C
DAC-888 8-BIT HIGH-SPEED "MICROPROCESSOR COMPATIBLE" MULTIPLYING D/A CONVERTER
DIGITAL INFORMATION
The DAC-888 (BYTEDAC'") is a monolithic microprocessor
compatible 01 A converter .conslsting of an 8-bit level trlg~
gered latch, control circuitry and one 8-bit multiplying DIA
converter housed in an 18 pin dual in line package (DIP).
The DAC-888 accepts 8-bit binary bytes at the data inputs.
Data access is accomplished when WR and CE are low.
During the low state of CE and WR, the latches are transparent, therefore, data should be valid from lOOns prior to WR
and CE low until CE or WR high. When CE or WR goes
high, the data stored in the latches will hold the selected
output indefinitely.
ANALOG INFORMATION
BASIC POSITIVE REFERENCE OPERATION
MSB
087 086 OBS DB4 DB3 DB2
LSB
DBo
os,
255
_
IFR= 256 X IREFwhere IREF - 110
In positive reference applications, an external positive reference voltage current flows through R 10 into the V REF(+) terminal of the reference amplifier. Alternatively, a negative
reference maybe applied to V REF (-); reference current flows
from ground through R10 into VREF(+) as in the positive reference case. This negative reference connection has the
advantage of a very high impedance presented at pin 11. The
voltage at pin lOis equal to and tracks the voltage at pin 11
due to the high gain of the internal reference ampliiier. R11
(nominally equal to R 10) is used to cancel bias current errors;
R11 may be eliminated with only a minor increase in error.
For most applications the tight relationship between I REF and
IFR will eliminate the need for trimming 'REF' If required,
full-scale trimming may be accomplished by adjusting the
value of R 10 0r by using a potentiometer for R 10. An improved
method of full-scale trimming which eliminates potentio-
17
I.
AREF
+5,OOOV
REF
or may vary from nearly 0 to +4.0mA. The full range output
currrent is a linear function of the reference current and is
given by:
1'lOUT
R10 10
'OlIT
BASIC NEGATIVE REFERENCE OPERATION
DAC
'REF ---..
MSB
LSB
OB7 DBs DBS DB4 DB3 082 DB1 DBo
RI1
O _ _'~
FOR FIXED REFERENCE, TTL OPERATION TYPICAL
VALUESAAE:
'FR'"
+::e
E: x
~
0--
I.
lOUT + lOUT = 'FR
fOR ALL LOGIC STATES
RREF = 2.5000k
Rll = RREF
lOUT ~_ _-+-'4:o lOUT
DAC
Rl1 11
-VREF
REFERENCE AMPLIFIER SETUP
The DAC-888 Is a multiplying DIA converter in which the
'FA
output current is the product of a digital number and the
input reference current. The reference current may be fixed
VREF-
13 -
o-M'II---t~:""":!F-......!l~"":~f----r'oIOUT
= ::Y.H§:
x .2§§.
RREF
256
,.
NOTE: RREF SETS IFS: R11 IS FOR BIAS CURRENT CANCELLATION,
AND IS eQUAL TO RREF.
BASIC UNIPOLAR NEGATIVE OPERATION
DB7 DBS CBs DB4 DB3 DB2 OBl DBo
EOUT
0
FULL SCALE -1 LSB
FULL SCALE - 2 LSB
HALF SCALE + LSB
HALF SCALE
HALF SCALE - LSB
ZERO SCALE + LSB
ZERO SCALE
PAGE 10-126
DB7 DB6 DBS DB4 DB3 DB2 DB1 DBO
1
0
1 0 0 0 0 0 0 1
1 0 0 0 0 0 0 0
0
1
0 0 0
0 0 0 1
0 0
0 0 0 0 0
lomA lomA Eo
Eo
1.992 0.000 - 4.980 0.000
1.9840.008 -4.960 -0.020
1.008 0.984 - 2.520 - 2.460
1.000 0.992 - 2.500 - 2.460
0.992 1.000 - 2.460 - 2.500
0.008 1.984 - 0.020 - 4.980
0.000 1.992 - 0.000 - 4.960
DAC-888 a-BIT HIGH-SPEED "MICROPROCESSOR COMPATIBLE" MULTIPLYING D/A CONVERTER
RECOMMENDED FULL SCALE ADJUSTMENT CIRCUIT
TABLE 1. REFERENCE AMPLIFIER COMPENSATION
REF. INPUT RESISTANCE
SUGGESTED Cc
1kl!
2.5kl!
5kl!
15pF
37pF
75pF
DB7 DBs OB5 DB4 OB3 082 DBl DBo
NOTE: A O.01/IF capacitor is suggested for fixed references.
For fastest response to a pulse, low values of R1o, enabling
small Cc values, should be used. If pin 10 is driven by a high
current source, none of the above values will suffice and the
amplifier must be heavily compensated which will decrease
overall bandwidth and slew rate. For R10 = 1k!l and Cc =
15pF, the reference amplifier slews at 4mA/l's, enabling a
transition from IREF= 0 to IREF= 2mA in 500ns (see Figure,
pulsed reference operation).
RID
LOWT.C.
'REF+ '" 2mA
+s.ooov
REF
4.Sk 1
lOUT
...
OAC
POT
meter TC effects is shown in the Recommended Full Scale
Adjustment Circuit.
Using lower values of reference current reduces negative
power supply current and increases reference amplifier negative common mode range. The recommended range for
operation with a DC reference current is +0.2mA to +4.0mA.
The reference amplifier must be compensated by using a
capacitor from pi n 12 to V-. For fixed reference operation a
0.011'F capacitor is recommended. For variable reference
applications, see "Reference Amplifier Compensation for
Multiplying Applications" section.
REFERENCE AMPLIFIER COMPENSATION FOR
MULTIPLYING APPLICATIONS
AC reference applications will require the reference amplifier to be compensated using a capacitor from pin 12to V-.
The value of this capacitor depends on the impedance presented to pin 10 (see Table 1).
Bipolar references may be accommodated by offsetting VREF
or pin 11 ,as shown in Figure below. The negative common mode
range of the reference amplifier is given by V CM = V- plus
(IREF X 1k!l) plus 2.5V. The positive common mode range is
V+ less 1.5V.
When a DC reference is used, a reference bypass capacitor is
recommended. A 5.0V TTL Logic supply is not recommended as a reference. If a regulated power supply is used as
a reference, R10 should be split into two resistors with the
junction bypassed to ground with a 0.11'F capacitor.
ANALOG OUTPUT CURRENTS
Both true and complemented output sink currents are provided, where 10 + iO = I FR. Current appears at the "true"
output when a "1" is applied to each logic input. As the binary
count Increases, the sink current at pin 14 increases proportionally in the fashion of a "positive logic" D/A converter.
When a "0" is applied to any input bit, that current is turned
off at pin 14 and turned on at pin 13. A decreasing logic count
increases iOas in a negative or inverted logic D/A converter.
Both outputs may be used simultaneously. If one of the
outputs is not required it must still be connected to ground or
to a point capable of sourcing I FS; do not leave an unused
output pin open.
ACCOMMODATING BIPOLAR REFERENCES
DB7 DBs DBS DB4 DB3 DB2 DBl DBO
DB7 DBs DBS DB4 DB3 DB2 DB lOBO
RREF
"N
~'~N~~~~~~__rv;;;;:---""'-:;;;\-__---!--o
RREF 10
+VREF
VREF""
lOUT
R'N
OAC
---
R1l 11
V'N""o
(OPTIONAL)
VREFCQMP
lOUT
V-
GNO
HIGH INPUT
IMPEDANCE
RREF '" Rll
+VREF MUST BE ABOVE PEAK POSITIVE SWING OF VIN
PAGE 10-127
V.
DAC-888 8-BIT HIGH-SPEED "MICROPROCESSOR COMPATIBLE" MULTIPLYING D/A CONVERTER
8080 INTERFACE
IREF
~AD~D~R~E~~__________________________~><::::
808.
~~-------------'I'
8228
'".
~DA~T~A
v·
><::::
_______________________________
V+
;r~'O~U~T:::::::=>C~
,:::::::::::::::::::::::::::
74LSl38
lOUT
TIMING
6800,6801,6809 INTERFACE
/12
ADDRESS
..XX
'".
RtW
R/W
"-
VMA
/
DATA
CE
.
ADDRESS
BUS
/
"~
'----../
X
lOUT
lOUT
VMA
TIMING
8085 INTERFACE
>C
Wii
8005
,"p
Wii
rv
DATA
~
"o
::::
Ce
~
'\
X
"-r
"
lOUT
lOUT
I/O/MEM
TIMING
PAGE 10-128
x:
JOOC
DAC-888 8-BIT HIGH-SPEED "MICROPROCESSOR COMPATIBLE" MULTIPLYING D/A CONVERTER
PULSED REFERENCE OPERATION
DB7 DBS DBS DB4 DB3 DB2 DBl DBa
+VREF
1,.
'i'
OPTIONAL RESISTOR
FOR OFFSET INPUTS
.vJ""l.
:-RIN
TVPICAL
AIN" 5k VALUES:
+VIN" lOV
<;:$.
R~
Reo
:;0
Rp 200H
,''-''I~~.~~--':'F---l~_~7~~~fl-.lW'-i
L---~~~-r--~--~
NOCAP
POSITIVE LOW IMPEDANCE OUTPUT OPERATION
DB7 DBS DBS DB4 DB3 DB2 DBl DBO
•
;o
~
IIJ
II:
W
lII:
W
FOR COMPLEMENTARY OUTPUT (OPERATION AS NEGATIVE lOGIC DAe),
CONNECT INVERTING INPUT OF OP·AMP TO lOUT. CONNECT lOUT TO
GROUND.
>
Z
oo
~
NEGATIVE LOW IMPEDANCE OUTPUT OPERATION
DB7 DBS DBS DB4 DBa DB2 DBl DBO
FOR COMPLEMENTARY OUTPUT (OPERATION AS NEGATIVE LOGIC DAe),
CONNECT INVERTING INPUT OF OP-AMP TO TOi.TT~ CONNECT lOUT TO
GROUND.
PAGE 10-129
DAC-88a a-BIT HIGH-SPEED "MICROPROCESSOR COMPATIBLE" MULTIPLYING D/A CONVERTER
BASIC BIPOLAR OUTPUT OPERATION
DBo
DB7 DBe DB5 084 DB3 DB2 DBl
+5.000V
-'.
~~---f,V~R~EF;'----~--~'O:UT~~---1~J
DAC
DB7
DB6
DB3
DB4
DB5
DB2
DBl
DBO
Eo
1
0
-4.960
-4.920
5.000
4-960
1
0
-0.040
0.000
0.040
0.080
0.040
0.000
4.900
5.000
-4.920
-4.960
POSITIVE FULL SCALE
POSITIVE FULL SCALE -1 LSB
Z~H() SCALE + LSB
ZERO SCALE
ZERO SCALE - LSB
0
0
1
NEGATIVE FULL SCALE + 1 LSB
NEGATIVE FULL SCALE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Eo
OFFSET BINARY OPERATION
MSB
LSB
DB7 DBe DB5 094 DB3 DB2 DB, DBO
+10TO +15V
5.000V
'5V
VOUT
•
REF·02
EOUT
2."
':'
-15V
'5V
':'
DB7
DB6
DB5
DB4
DB3
DB2
DBl
DBO
1
0
POSITIVE FULL SCALE -1 LSB
POSITIVE FULL SCALE - 2 LSB
ZERO SCALE
1
0
0
0
0
0
NEGATIVE ZERO SCALE + 1 LSB
NEGATIVE FULL SCALE
0
0
0
0
0
0
0
0
0
0
0
0
PAGE 10-130
0
0
Eo
4.960
4.920
0
0.000
1
0
- 4.960
- 5.000
DAC-888 8-BIT HIGH-SPEED "MICROPROCESSOR COMPATIBLE" MULTIPLYING D/A CONVERTER
supplies is possible. However, at least av must be applied to
insure turn-on of the internal bias network.
BASIC BIPOLAR OUTPUT OPERATION
Both outputs have an extremely wide voltage compliance,
enabling fast direct current-to-voltage conversion through a
resistor tied to ground or other voltage source. Positive
compliance is 1aV above V- and is independent of the
positive supply. Negative compliance is given by V- plus
(IREF X 1kO) plus 2.5V.
Symmetrical supplies are not required, as the CAC-aaa is
quite insensitive to variations in supply voltage.
Power consumption may be calculated as follows:
Pd
= (1
+) (V +) + (I -) (V -) + (2 IREF) (V -).
POWER SUPPLIES
TEMPERATURE PERFORMANCE
The CAC-aaa operates over a wide range of power supply
voltages from a total supply of 9V to 17V. When operating at
supplies of ±5V or less, IREF:S 1mA is recommended. Low
reference current operation decreases power consumption
and increases negative compliance, reference amplifier
negative common mode range, negative logic input range,
and negative logic threshold range; consult the various figures for guidance. For example, operation at -4.5V with IREF
= 2mA is not recommended because negative output compliance would be reduced to near zero. Operation from lower
The nonlinearity and monotonicity specifications of the
CAC-aaa are guaranteed to apply overtheentire rated operating temperature range. Full-scale output current drift is
tight, typically ±1 Oppm/o C, with zero scale output current
and drift essentially negligible compared to 1/2 LSB.
The temperature coefficient of the reference resistor RlO
should match and track that of the output resistor for minimum overall full-scale drift. Settling times of the CAC-aaa
decrease approximately 10% at -65° C; at +125° C an increase
of about 15% is typical.
II
Z-80 INTERFACE
III
III
~
c(
MREO
zso
~p
WI!
II)
II:
/
'\
WR
~~-------------
C
/
'\
III
.....
X
§:)<
,I
IT"'"""\
c(
TIMING
6502 INTERFACE
ADDRESS
"
~p
/
CE
~IO~U~T____________~~~
________________
lOUT
TIMING
PAGE 10-131
0
Q
lOUT
6502
>
z
U
X
lOUT
II:
III
DAC-888 8·BIT HIGH·SPEED "MICROPROCESSOR COMPATIBLE" MULTIPLYING D/A CONVERTER
8048 INTERFACE
~
\.,------------------------
~
ADDRESS
X
FLOATING
X
DATA
>E!!EG
IREF
lOUT
DATA
..._ _ _ _ _ _ _ _ _ _ _ _ _ _ ___
~
OAC BBB
Ce
\in
WR
I/O PORT 2
='O=UT~---------....XJ()CK-----------lOUT
OUTPUT MAY CHANGE UNTIL DATA VALID
TIMING
'SOFTWARE SAR'AID CONVERTER (WITH 6502 MICRO PROCESSOR)
y8
12
7
6
5
4
3
2
1 10
CEW
+15V
WRITE
STROBE
5.1Mn
+15V
5.0Kn
1 3 +5V
GND
234567816
VOUT 6
+5V
REF-02
2.4Kn
10
39.
n
..¢.
=DIGITAL GROUND
~
=ANALOG GROUND
10Kn
PAGE 10·132
DAc-aaa a-BIT HIGH-SPEED "MICROPROCESSOR COMPATIBLE" MULTIPLYING D/A CONVERTER
SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERSION
PROGRAM LISTING USING DAC-888 AND SYM 1 PCB WITH 65021lP
LOCATION
500
502
504
506
508
508
50C
50F
511
513
514
515
517
519
51A
51B
51C
51E
520
DATA
A900
A208
9500
AlSO
AI
'00010
AD 00 lC
2901
FOOl
98
18
7500
9500
98
4A
A8
1500
90 E9
4C 00 05
COMMENTS
MNEMONIC
LOA #00
LOX #08
STA,X
LOA#SO
TAY
STA 1000 (CONT.)
LOA lCOO
ANDA,#Ol
BEQ' +1
TYA
CLC
AOC,X
STA,X
TYA
LSR
TAY
ORA,lI
BCC'-23
JMP500
CLEAR
SET INDEX REGISTER
CLEAR MEMORY AT 08 H
TRIAL BIT
TOY
OUTPUT
READCOMP.
MASK IT
BRANCH IF CMP ~ 0
GET TRIAL BIT
CLEAR CARRY
RESULT SUMMED WITH PREVIOUS TEST
SAVE IT
GET TRIAL VALUE
NEXT BIT
SAVE IT
NEXT DATA
CONTINUE FOR 8 TRIALS NOTE:
DO OVER
32 BYTES
260~.
II
FLOW CHART 'SOFTWARE SAR' AID CONVERTER
:g
"I'
u
Z
o
u
~
DAC-1508A/1408A
PMI
8-BIT MULTIPLYING D/A CONVERTER
FEATURES
The R-2R ladder divides the reference current into eight
binarily-related components which are fed to the switches. A
remainder current equal to the least significant bit is always
shunted to ground, therefore the maximum output current is
255/256 of the reference amplifier input current. For example, a full-scale output current of 1.992mA would result from
a reference input current of 2.0mA.
• Improved Direct Replacement for MC1S08/MC1408
• 0.19% Nonlinearity Maximum Over Temperature Range
• Improved SetUlng Time .••.......•...... 2S0ns, Typical
• Improved Power Consumption ......... 1S7mW, Typical
• Compatible with TTL, CMOS Logic
• Standard Supply Voltages ..... +S.OV and -S.OV to -1SV
• Output Voltage Swing .................. +O.SV to -S.OV
• High·Speed Multiplying Input •.............. 4.0mAl!Ls
The DAC-1508A11408A is useful in a wide variety of applications, including waveform synthesizers, digitally programmable gain and attenuation blocks, CRT character generation, audio digitizing and decoding, stepping motor drives,
programmable power supplies and in building tracking and
successive approximation analog-to-digital converters.
GENERAL DESCRIPTION
The DAC-1508A11408A are 8-bit monolithic multiplying
digital-to-analog converters consisting of a reference current2R ladder, and eight high-speed current switches. For many
applications, only a reference resistor and reference voltage
need be added. Improvements in design and processing
techniques provide faster settling times combined with lower
power consumption while retaining direct interchangeability
with MC1508/1408 devices.
For significantly improved speed and applications flexibility
the user's attention is directed to the DAC-08 8-bit highspeed multiplying D/A converter data sheet. For D/A converters which include precision voltage references on the
chip please refer to the DAC-02, DAC-04 and DAC-100 data
sheets.
PIN CONNECTIONS
ORDERING INFORMATIONt
16-PIN DUAL-IN-LiNE PACKAGE
RELATIVE
ACCURACY
'!oFS
±0.19'!o
±0.39'!o
±0.78'!o
HERMETIC
MILITARY
DAC1508A-80'
PLASTIC
COMMERCIAL
DAC1408A-8P
DAC1408A-7P
DAC1408A-6P
COMMERCIAL
DAC1408A-80
DAC1408A-70
DAC1408A-60
16·PIN DUAL·IN-LiNE
HERMETIC (0)
EPOXY B (P)
'Also available with MIL-STD-883B Processing. To order add /883 asa suffix
to the part number.
t All listed parts are available with 160 hour burn~in. See Ordering Information,
Section 2.
SIMPLIFIED SCHEMATIC
MSB
A1
A2
A3
Manufactured under one or more of the following patents: 4,055,773;
4,056,740; 4,092,639.
A4
A5
A6
PAGE 10·134
A7
LSB
A8
DAC-1508A11408A 8-BIT MULTIPLYING D/A CONVERTER
ABSOLUTE MAXIMUM RATINGS
Power Supply Voltage
VCC ••••••••••.••.•.••••••••.••.•••.•..••••.• +5.5Vdc
VEE" .' •.•.•••••••••.••.•••••••••.•..•.••.•• -16.5Vdc
Digital Input Voltage, V5 through V 12 ••••••.•.. +5.5,OVdc
Applied Input Voltage •.••••••••.••..••.•.• +0.5, -5.2Vdc
Reference Current, ',4 •••.•.•••.•••.••.••••.••... 5.0mA
Power Dissipation (Package Limitation), Pd
Ceramic Package (or Expoxy B Package) •..•.• 100mW
DerateaboveTA =+25°C •.•.•.•...••.•..•. 6.7mW/oC
Derate above T A = + 100° C for
Epoxy B Package. . • • • • . • . • • • • • • • • • • • . • • . •• 5.3mW/o C
Operating Temperature Range, TA
DAC-1508A •••..•.••••••••••••••••• -55° C to + 125° C
DAC-1408A •.•••••.•••••••.••••..••••.• 0°Cto+75°C
DICE Junction Temperature (Ti ) •••.••••• -65°C to 150°C
Storage Temperature Range, T stg ..•..• -65° C to + 150° C
Plastic Package Only •.••••.•••••••• -65° C to + 125° C
NOTE: Ratings apply to both DICE and packaged parts, unless otherwise
noted.
ELECTRICAL CHARACTERISTICS
at Vcc= +5.0Vdc, V EE =-15Vdc, VREplR14 = 2.0mA, -55°C:5 T A :5 +125°C for
DAC-1508A-8, O°C:5 T A :5 +75°C for DAC-1408A, unless otherwise noted. All digital inputs at high logic level.
DAC-1508A11408A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
±0.19
±0.39
±0.7S
%IFS
Relative Accuracy (error relative to
full-scale 10 )
DAC-1S0SA-S, DAC-140SA-S
DAC-1408A-7
DAC-1408A-6
Settling Time to within 1/2 LSB
(includes t plHJ
E,
ts
TA= +25°C, Note 1
Propagation Delay Time
t pLH• tpHL
TA =+2SoC. Note 1
Output Full-Scale Current Drift
TCl o
Digital Input Logic Levels (MSB)
High Level, Logic "I"
Low Level, Logic "1"
250
30
ns
100
ns
ppm/oC
±20
C
IIH
IlL
Reference Input Bias Current (Pin 15)
I,.
0
2.0
O.S
High Level, VIH = 5.0V
Low Level, VIL = 0.8V
0.04
Vdc
rnA
-1.0
-3.0
I'A
0
0
2.0
2.0
2.1
4.2
rnA
1.9
1.99
2.1
rnA
0
4.0
I'A
-0.6. +0.5
-S.O, +O.S
Vdc
lOR
VEE = -S.OV
VEE = -6.0V to -ISV
Output Current
10
VREF = 2.000V, R14 = 10000
Output Current
'O{min)
All bits low
Output Voltage Compliance
(E," 0.19% alTA = +2S0C)
Va
VEE=-S
VEE below -IOV
Reference Current Slew Rate
SRI REF
4.0
PSSl a_
0.5
2.7
I'A/V
+9
-7.5
+14
-13
rnA
+5.0
-15
+5.S
-16.5
Vdc
82
157
13S
265
Power Supply Current
Power Supply Voltage
VeCR
All bits low
TA =+25°C
VEER
Power Dissipation
Pd
All bits low
VEE = -5.0Vdc
VEE = -ISVdc
All bits high
VEE = -S.OVdc
VEE =-15Vdc
NOTE: Guaranteed by design.
PAGE 10-135
+4.5
-4.5
70
132
II)
C
UI
a::
'AEF= 1mA
Icc
lEE
~
!
~
Q
Output Current Range
Sensitivity
..,...
00
VIH
VIL
Digital Input Current (MSB)
Output Current Power Supply
II
mAIl's
mW
W
I-
a::
W
>
Z
0
0
C
-...
Q
DAC-1508A11408A 8-BIT MULTIPLYING D/A CONVERTER
2. GROUND
3. VEE
4.10
5. Al (MSa)
6. A2
7. AS
•. A4
9. A5
10. A6
11. A7
12. AB(lSa)
13. Vee
14. VAEF(+)
15. VAEF(-)
16. COMP
Refer 10 Seellon 2 for addilional DICE Informallon
DIE SIZE O.ll85 X 0.062 Inch
ELECTRICAL CHARACTERISTICS
at
25° C;
V+ = 5V, V- = 15V, IREF = 2.0mA, unless otherwise noted.
DAC-1408A-G
PARAMETER
SYMBOL
CONDITIONS
LIMIT
Resolution
Monotonicity
Nonlinearity
Output Voltage Compliance
UNITS
Bits MIN
Vos
Full Scale Current Change
V-=-5V
< 1/2 LSB
V- below +10V
8
Bits MIN
±0.9
%FS MAX
+0.5
V MAX
+0.6
0.5
VMIN
VMIN
full Scale Current
I FS
V REF = 2.000V, R,., R'5 = 1.000kfl
2.0,±0.1
rnA MAX
Zero Scale Current
I zs
(All Bits Low)
4.0
"A MAX
lOR
V-=-5.0V
V-=-7.0Vto-15V
2.1
4.2
mAMIN
Output Current Range
Logic "0" Input Level
V,L
0.8
V MAX
Logic "I" Input Level
V ,H
2.0
VMIN
Logic Input Current
Logic "0"
Logic "1"
I'L
I'H
±10
±10
"A MAX
Reference Bias Current
1'5
Output Current Power Supply Sensitivity
PSSlo_
Power Supply Current (All Bits Low)
1+
1-
-13
VeeR
-16.5
Power Supply Voltage Range
Low Level, V ,L = -0.8V
High Level, V ,H =5.0V
Pd
"A MAX
2.7
"NV MAX
+14
VEER
Power Dissipation (All Bits Low)
-3.0
V-=-5.0V
V-=-15V
TYPICAL ELECTRICAL CHARACTERISTICS
rnA MAX
+5.0, ±0.5
rnA MAX
-4.5
rnA MAX
mAMIN
135
265
mWMAX
at V+ = +5V, V-=-15V, TA = 25°C, VLcand lOUT connected to ground,
and IREF = 2.0mA, unless otherwise noted. Output characteristics refer to lOUT only.
DAC-1408G
PARAMETER
SYMBOL
Reference Input Slew Rate
dlldt
Propagation Delay
t pLH• tpHL
Any Bit
ts
To ± 1/2 LSB, All Bits Switched
ON or OFF
Settling Time
CONDITIONS
PAGE 10-136
TYPICAL
UNITS
4.0
mA/"s
30
ns
250
ns
DAC-1508A11408A a-BIT MULTIPLYING D/A CONVERTER
APPLICATIONS
RELATIVE ACCURACY TEST CIRCUIT
MSB
A'
A2
12·BIT
A3
D-TOA-
o TO +10V OUTPUT
r-o-
CONVERTER
(-+.0.01%
ERROR MAX)
A4
AS
A6
A7
~
5k
LSB A"f'
At Al2
50k
VREF
i1'!
I~-=i:
2V
~
Vee
r
R,'
950
-
1
ERR OR
b
I1V
'" 1%)
13
'4
MSB
S
1
II
6
7
•
8-BIT
COUNTER
DAC-1508Af
DAC-1408A
9
'0
~
"
'2
-
:~6
3 2
:"L
1k
-
!II
a:
-
w
VEE-
I-
a:
W
>
Z
USE WITH NEGATIVE V REF
o(J
«
US.E WITH POSITIVE V REF
C
Vee
13
A'
~
R15
A'
A2
A3
R14
A2
I-"'-o---'\M~" VREF(-)
A3
L.r
A4
AS
A4
AS
RL
A6
A6
A7
A7
AS
AS
SEE
TEXT
FOR
SEE
TEXT
FOR
VALUES
OF
e
VALUES
OF
PAGE 10-137
e
DAC-1508A11408A 8-BIT MULTIPLYING D/A CONVERTER
TRANSIENT RESPONSE AND SETTLING
TIME TEST CIRCUIT
polarity. Connections for a positive voltage are shown on the
preceeding page. The reference voltage source supplies the
full current 1'4. The Preceeding bipolar reference signals, as
in the multiplying mode, R15 can be tied toa negative voltage
corresponding to the minimum input level. It is possible to
eliminate R15 with only a small sacrifice in accuracy and
temperature drift.
+2.0Vdc
'3
The compensation capacitor value must be increased with
increases in R14 to maintain proper phase margin; for R14
values of 1.0, 2.5 and 5.0kO, minimum capacitor values are 15,
37, and 75pF. The capacitor may be tied to either VEE or
ground, but using VEE increases negative supply rejection.
'k
5'
A negative reference voltage may be used if R14 is grounded
and the reference voltage is applied to R15 as shown. A high
input impedance is the main advantage ofthis method. Compensation involves a capacitor to VEE on Pin 16, using the
values of the previous paragraph. The negative reference
voltage must be at least 4.0V above the VEE supply. Bipolar
input signals may be handled by connecting R14 to a positive
reference voltage equal to the peak positive input level at Pin
15.
I 10.'"'
..:;co
25pF
O.lpF
.,r
EO FOR SETILING TIME MEASUREMENT
(ALL BITS SWITCHED LOW TO HIGH)
USE WITH CURRENT-TO-VOLTAGE CONVERTING OP AMP
Vee
VREF .. 2.0Vdc
R14 = R16 ... 1.0kO:
RO • 5.Ok"
,---.,
'3
..,'4::'O-----"J>,IV---i--_4VREF
A2
'5
A3
R'5
If Pin 14 is driven by a high impedance such as a transistor
current source, none of the above compensation methods
apply and the amplifier must be heavily compensated,
decreasing the overall bandwidth.
A4
A5
RO
A6
When a DC reference voltage is used, capacitive bypass to
ground is recommended. The 5.0V logic supply is not
recommended as a reference voltage. If a well regulated 5.0V
supply which drives logiC is to be used as the reference, R14
should be decoupled by connecting it to +5.0V through
another resistor and bypassing the junction of the two resistors with 0.11'F to ground. For reference voltages greater than
5.0V, a clamp diode is recommended between Pin 14 and
ground.
A7
AS
Va
OUTPUT VOLTAGE RANGE
The voltage on Pin 4 is restricted to a range of -0.6V to +0.5V
when VEE = -5V due to the current switching methods
employed in the DAC-150SA-S.
GENERAL INFORMATION AND APPLICATION NOTES
The negative output voltage compliance of the DAC-150SA-S
is extended to -5.0V where the negative supply voltage is
more negative than -10V. Using a full-scale current of
1.992mA and load resistor of 2.5kO between Pin 4 and ground
will yield a voltage output of 256 levels between 0 and
-4.9S0V. The value of the load resistor determines the switching time due to increased voltage swing. Values of RL up to
5000 do not significantly affect performance but a 2.5kO load
increases "worst case" settling time to 1.21's (when all bits are
switched on). Refer to the subsequenttext section of Settling
Time for more details on output loading.
REFERENCE AMPLIFIER DRIVE AND COMPENSATION
The reference amplifier provides a voltage at Pin 14 for
converting the reference voltage to a current, and a turnaround circuit or current mirror for feeding the ladder. The
reference amplifier input current, 114, must always flow into
Pin 14 regardless of the setup method or reference voltage
OUTPUT CURRENT RANGE
The output current maximum rating of 4.2mA may be used
only for negative supply voltages more negative than -0.7V,
due to the increased voltage drop across the resistors in the
reference current amplifier.
THEORETICAL Vo
Va
=
~
IRol
[¥ . ¥ . ~ . ~ . ~ . eI·
~. ~]
ADJUST VREF R15 OR Ro so THAT Vo WITH ALL DIGITAL
INPUTS AT HIGH LEVEL IS EQUAL TO 9.981 VOL T8.
vo ..
~ f6kl[i'~'il'
'" 10V [
~J = 9.961V
to·i·O\· do '~J
PAGE 10-138
DAC-1508A11408A a-BIT MULTIPLYING D/A CONVERTER
ACCURACY
Absolute accuracy is the measure of each output current
level with respect to its intended value, and is dependent
upon relative accuracy and full-scale current drift. Relative
accuracy is the measure of each output current level as a
fraction of the full-scale current. The relative accuracy of the
OAC-150BA-B is essentially constant with temperature due to
the excellent temperature tracking of the monolithic resistor
ladder. The reference current may drift with temperature,
causing a change in the absolute accuracy of output current.
However, the OAC-150BA-B has a very low full-scale current
drift with temperature.
MULTIPLYING ACCURACY
The OAC-150BA-B may be used in the multiplying mode with
eight-bit accuracy when the reference current is varied over a
range of 256:1. If the reference current in the multiplying
mode ranges from 16/LA to 4.OmA. the additional error contributions are less than 1.6/LA. This is well within eight-bit accuracy when referred to full scale.
A monotonic converter is one which supplies an increase in
current for each increment in the binary word. Typically, the
OAC-150BA-B is monotonic for all values of reference current
above 0.5mA. The recommended range for operation with a
DC reference current is 0.5 to 4.OmA.
The OAC-150BA-B/OAC-140BA Series is guaranteed accurate to within ± 1/2 LSB at a full-scale output current of
1.992mA. This corresponds to a reference amplifier output
current drive to the ladder network of 2.0mA, with the loss of
one LSB (B.O/LA) which is the ladder remainder shunted to
ground. The input current to Pin 14 has a guaranteed value'of
between 1.9 and 2.1 mA, allowing some mismatch in the NPN
current source pair. Testing relative accuracy is accomplished by the circuit labelled "Relative Accuracy Test Circuit". The 12-bit converter is calibrated fora full-scale output
current of 1.992mA. This is an optional step since the OAC150BA-B accuracy is essentially the same between 1.5 and
2.5mA. Then the OAC-150BA-8 circuit's full-scale current is
trimmed to the same value with R14 so that a zero value
appears at the error amplifier output. The counter is activated
and the error band may be displayed on an oscilloscope,
detected by comparators, or stored in a peak detector.
SETTLING TIME
The "worst case" switching condition occurs when all bits are
switched "ON", which corresponds to a low-to-high transition for all bits. This time is typically 250ns for settling to
within ± 1/2 LSB, forB-bit accuracy, and 200ns to 1/2 LSB for
7 and 6-bit accuracy. The turn off is typically under 100ns.
These times apply when RL:S 500n and Co:S 25pF.
Two B-bit 01 A converters may not be used to construct a
16-bit accuracy 01 A converter. 16-bitaccuracy implies a total
error of ± 1/2 of one part in 65, 536, or ±0.000760/0 which is
much more accurate than the ±0.190/0 specification provided
by the OAC-150BA-B.
Extra care must be taken in board layout since this is usually
the cominant factor in satisfactory test results when measuring settling time. Short leads, 100/LF supply bypassing for low
frequencies, and minimum scope lead length are all
mandatory.
The slowest single switch is the least significant bit. In applications where the 01 A converter functions in a positivegoing ramp mode, the "worst case" switching condition does
not occur, and a settling time of less than 250ns may be
realized.
II
II)
a::
I!!a::
w
rzo
(,)
~
PAGE 10-139
JM38510/11301/11302
PMI
JAN 8-81T
DlGITAL-TO-ANALOG CONVERTER
GENERAL DESCRIPTION
POWER AND THERMAL CHARACTERISTICS
This data sheet covers the electrical requirements of the
monolithic 8-bit Dlgital-to-Analog Converters found in MILM-38510/113. Devices supplied to this data sheet are
manufactured and tested at PMI's MIL-M-38510 certified
facility and are listed In QPL-38510.
Package
Case oulline
Dual·in·line
E
Maximum allowable
power dissipation
400mW at TA -125'C
Maximum
9J-C
35'C/W
Maximum
9J-A
120'CIW
PIN CONNECTIONS & ORDERING INFORMATION
Complete device requirements will be found in MIL-M-38510
and MIL-M-38510/113 for Class B processed devices.
Device types shall be as follows:
01
D/A Converter, 8 bit, 0.19% linearity
02
D/A Converter, 8 bit, 0.10% linearity
GENERIC CROSS·REFERENCE INFORMATION
This cross-reference information is presented for the con·
venlence of the user. The Generic-Industry types listed may
not have identical operational performance characteristics
across the military temperature range or the reliability fac·
tor equivalent to the MIL-M-38510/113 devices.
Military Device Type
01
02
Generic Industry Type
DAC·OS
DAC-08A
Jan Device
JM3851 0111301 BEC
JM38510/11302BEC
JM38510/11301 BEB
JM38510/11302BEB
CASE OUTLINE
Per MIL-M·38510, Appendix C, Case Outline D-2 (16 Lead
1/4"x 7/8", dual·in-line). Package type designator "E".
VREF
DAC08Q2/38510
DAC08AQ2/38510
NOTE: Lead finish as follows
BEC: Gold Plate. side braze package
BEB: Tin Plate, CERDIP package
SIMPLIFIED SCHEMATIC
VREF
PMI Device Type
DACOSQ1/38510
DACOSAQ1/38510
1+)o--'-"4't-~-:-t_ _-,
(_I ~15-'--_=r
Manufactured under one or more of the following patents:
4,055,773; 4,056,740; 4,092.639
PAGE 10-140
linearity
0.19%
0.10%
0.19%
0.10%
JM38510111301111302 JAN 8·BIT DIGITAL·TO·ANALOG CONVERTER
ABSOLUTE MAXIMUM RATING
Supply Voltage [ + VCC - (- Vcdl ................. 36Vdc
Voltage, Digital Input to Negative Supply
[Vl09lc - ( - Vcdl . . . . . . . . . . . . . . . . . . . . . . . .. 0 to 36Vdc
Voltage, Logic Control (VLd . . . . . . . . . . . .. -Vcc to +Vcc
Reference Voltage Input [(VI4' V15)1 ......• -Vccto +Vcc
Reference Input Current (1 14) . . . . . . . . . . . . . . . . . . .. 5.0mA
Reference Input Differential Voltage [(V 14 - V15)] .. ± 18Vdc
Lead Temperature (Soldering, 60 sec.) ... . . . . . . . .. 300·C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . .. 175·C
Storage Temperature ............... -65·Cto +150·C
RECOMMENDED OPERATING CONDITIONS
Supply Voltage Range. . .. . . . . . . . . .. ±5Vdc to ±15Vdc·
ELECTRICAL CHARACTERISTICS
range
Ambient Temperature Range. . . . . . . .. -55·C to + 125·C
at ±Vcc = ±15Vdc; Source resistance = 50 ohms; IREF = 2.0mA; Figure 1; Ambient temperature
= -55·C to +125·C, unless otherwise noted.
PARAMETER
01 limits
02 limits
MIN
MAX
MIN
MAX
.1(i)
Measure 10, (ION -ION _1),,0 at
each major carry point
0
16.0
0
16.0
d(i)
Measure 10 , (ION -ION _1),,0 at
each major carry point
0
16.0
0
16.0
-8.0
8.0
-4.0
4.0
p.A
-50.0
50.0
-50.0
50.0
ppm/oC
SYMBOL
CONDITIONS
Monotonicity
-
-
.1IFS
IFS-IFS
Full Scale Current
Temperature Coefficient
TdIFS)
All input bits high, Measure 10
TC(lFsl
All input bits low, Measure
IFS
All input bits high, TA = 25°C
Measure 10
Full Scale Current
IFS
Negative Bit Errors
Positive and Negative
Bit Error Difference
All input bits high,
Measure
ENL+
Measure 10
(EPositive bit errorsVI FS
ENL+
Measure 10
(EPositive bit errorsVI FS
ENL-
Measure 10
(ENegative bit errorsVIFS
ENL-
Measure
(ENegatlve bit errorsVIFS
AENL
Measure 10
IENL+ I-IENL-I
1.984
2.000
mA
-2.0
2.0
-1.0
1.0
p.A
Measure 10
IENL + 1 + I.1ENLI
NL+
MB..!.sure TO
IENL + 1 + 1.1ENL 1
NL-
Measure 10
IENL -I + IENLI
N'L-
M~~sure TO
~
on
CIO
...::!!
en
0
0.19
0
0.10
%
a:
W
I-
a:
W
>
Z
-0.19
0
-0.10
0
%
0
0
c(
.....
0
10
NL+
...
C')
10
M'!!sure
IENL + I-IENL-I
~
0
10
.1EiiiL
Negative Relative Accuracy
2.04
C')
Izs
Positive Relative Accuracy
C')
1.94
:=:
Izs
Positive Bit Errors
II
N
0
iO
All input bits low,
Measure 10
Zero Scale Current
iO
All Input bits low, TA=25°C
Measure
p.A
-
Output Symmetry
UNITS
IENL -I + 1.1ENL 1
PAGE 10-141
-0.05
0.05
-0.03
0.03
%
0
0.19
0
0.10
%
0
0.19
0
0.10
%
JM38510111301/11302 JAN 8-BIT DIGITAL·TO·ANALOG CONVERTER
ELECTRICAL CHARACTERISTICS at
±Vee = ± 15Vde; Source resistance = 50 ohms; IREF = 2.0mA; Figure 1; Ambient temperature
range= -55°C to +125°C, unless otherwise noted.
PARAMETER
SYMBOL
CONDITIONS
IFSR1
All Input bits high. Measure 10.
-Vee = -10V. VREF=15V
IFSR1
All input bits low. Measure
-Vee = -10V. VREF ,,15V
IFSR2
All Input bits high. Measure 10
-Vee= -12V, VREF= 25V
Output Current Range
IFSR2
Reference Bias Current
High Level Input Current
Low Level Input Current
Full Scale Current
At + 1BV Compliance
Full Scale Current
At -10V Compliance
MIN
MAX
2.1
MAX
UNITS
2.1
mA
4.2
4.2
All Input bits low, Measure '0,
-Vee = -12V. VREF=25V
All input bits low
IIH
All Input bits VIN = lBV. each
Input measured separately
-0.05
IlL
All input bits VIN = -10V. each
Input measured separately
-10.0
IFS+
All Input bits high. Measure 10.
Vlo =IBV
IFS+
All input bits low. Measure
Vj(j=IBV
IFS-
All Input bits high. Measure 10.
VIO= -10V
IFS-
All Input bits low. Measure 10.
Via= -10V
.:loIFSC
All input bits high. Measure 10 •
25°C",TA"'125°C
TA = -55°C
Vlo =IBVto -10V
.:loIFSC
All Input bits low. Measure
25°C"TA sI25°C
TA = -55°C
Vj(j=IBV to -10V
PSSIFS+l
All Input bits high. Measure 10 •
+Vee= 4.5V to +5.5V. -Vee = -IBV
PssIFS+l
All Input bits low. MeasurA 1Q.
+Vee=4.5V to +5.5V. -Vee= -IBV
PssIFS+2
All Input bits high. Measure 10 •
+Vee=12V to lBV. -Vee= -IBV
PssIFS+2
All Input bits low. Measure "iQ:
+ Vee = 12V to lBV. -Vee = -IBV
PssiFS-l
All Input bits high. Measure 10.
+ Vee = lBV. -Vee= -12V to -IBV
PssiFS-l
Power Supply Sensitivity
From -Vee
02 limits
IREF-
Change In Full Scale Current
Due to Voltage Compliance
Power Supply Sensitivity
From +Vee
iQ:
01 limits
MIN
-3.0
iQ:
0
-3.0
0
pA
10.0
-0.05
10.0
pA
-10.0
1.90
2.08
1.90
2.08
-4.0
-B.O
pA
2.04
mA
1.94
2.04
mA
4.0
B.O
-4.0
-B.O
4.0
B.O
-4.0
-8.0
4.0
B.O
-4.0
-B.O
4.0
B.O
-4.0
4.0
-4.0
4.0
-B.O
B.O
-8.0
B.O
-B.O
B.O
-B.O
B.O
-2.0
2.0
-2.0
2.0
1.94
iQ.
All Input bits low, Measure IQ.
+Vee=IBV. -Vee= -12V to -IBV
PssIFS-2
All Input bits high. Measure 10 •
+Vee=IBV, -Vee= -4.5Vto -5.5V
IREF=lmA
PssIFS-2
All input bits low. Measure 1Q.
+ Vee = lBV. -Vee= -4.5Vto -5.5V
IREF =lmA
PAGE 10-142
JM38510111301/11302 JAN 8·BIT DIGITAL·TO·ANALOG CONVERTER
ELECTRICAL CHARACTERISTICS
at ±Vcc = ±1SVdc; Source resistance = SO ohms; IREF =2.0mA; Figure 1; Ambient temperature
range = -SS"C to +12S"C, unless otherwise noted.
02 limits
01 limits
MIN
MAX
MIN
MAX
All input bits high
0.4
3.B
0.4
3.B
rnA
Icc
All Input bits high
-7.B
-O.B
-7.B
-O.B
rnA
Propagation Delay Time,
High·to·Low Level
tpHL
Figure 2, Measure Vo
6.0
60.0
6.0
60.0
ns
Propagation Delay Time,
Low-to·Hlgh Level
tpLH
Figure 2, Measure Va
6.0
60.0
6.0
60.0
ns
Reference Amplifer Input
Slew Rate
dloldt
TA=25"C
Figure 3, Measure Va
1.5
Settling Time
H Igh-to-Low Level
tSHL
TA =25'C
Figure 2, Output within Yo
LSB of final value of 10
10
135
10
135
ns
Settling Time
Low·ta·High Level
tSLH
TA =25'C
Figure 2, Output within Y2
LSB of final value of 10
10
135
10
135
ns
PARAMETER
SYMBOL
CONDITIONS
Supply Current From +Vcc
Icc+
Supply Current from -Vcc
1
UNITS
mAIp.S
1.5
, • •, ,
1
3
+15V
MS.
•
N
0'
t
7 •
Z5
10k
0.01%
200k
1%
........~...
............
C>
lft
...
.,::Ii!
0
CD
9
C.U,T.
In
a:
III
50
5%
I-
a:
NOTES:
D,1pF
1.
III
THE REFERENCE a/A CONVER·
TER SELECTED SHOULD HAVE
>
Z
A RESOLUTION OF 8 BITS OR
2.
3.
~
-::-
MORE, AND A LINEARITY OF
0.015% OR BETTER.
THE VOLTAGE REFERENCE
SHOULD HAVE AN ACCURACY
OF ±O.02% OR BETTER.
ALL RELAYS ARE SHOWN IN
THEIR NON-ACTUATED STATE.
Figure 1. Test Circuit For Static Tests
PAGE 10-143
0
10k
0,01%
U
C
.....
C
JM38510111301/11302 JAN a·BIT DIGITAL·TO·ANALOG CONVERTER
1"------,.----.,
OPTIONAL WITH FET PROBE
VL
(see
NorE 1)
,."
I
I
I
I
I
I
I
I
I
.-----~~----~~~----------~~-£
I
I
I
•• 7V
15k!l
..JI
L __________
NOTES:
1. FOR TURN-ON VL = 2.7V; FOR TURN-OFF VL = O.7V
2. MINIMIZE CAPACITANCE AT THIS NODE BY USING
SHORT RUNS AND ADEQUATE SPACING BETWEEN
RUNS.
3. DIODES MUST BE SCHOTTKY TYPE (MBD 501 OR
eQUIVALENT).
-15V
4.
BANDWIDTH OF OSCILLOSCOPE USED FOR WAVE·
FORM MEASUREMENT SHOULD BE 50MHz MINIMUM;SATURATION OF PREAMP MUST BE AVOIDED.
I
_I I_
--.,'f
~r~~=.%~--------------=::=%~~,
_I
tr=tf<1Qns
~,,_
I
I ------
I
1
VOUT~
l
P7 rrl
~~
-----t--\'
±1/2LSB
:
I
: 'PLH
T,'I2LS~ 4mV
~
\-.-tSLH .....
=
TURN-ON
TURN·OFF
Figure 2. Test Circuit For Propagation Delay and Settling Time, Device Types 01 and 02.
+5V FOR Your
ov
FOR\i'OiJT
Your
-1"1---__ _
'.V~---
tr< lOns
V,N
- -
-
10%
ov
ov----....,
VourOR
-2V
Figure 3. Test Circuit For Slew Rate, Device Types 01, 02.
PAGE 10-144
Your
I>V \
-
-
-
+\.- -
-----~::;tfc_
••5V
1.GV
JM38510/11301/11302 JAN II-BIT DIGITAL·TO·ANALOG CONVERTER
BURN·IN
Devices supplied by PMI have been subjected to burn·in per
method 1015 of MIL·STD-883 using test condition C or test
condition F with the circuit shown in Figure 4.
+,sv
t-,.
R,
,.
,.
'3
'2
"
5
6
,. •
D.U.T.
f
~
2
3
-,sv
4
7
•
R1 = 9k ±5%
Cl = O.OOlp.F, 50V
Figure 4. Test Circuit, Burn·ln and Operating Life Test .
•
II)
~
w
I-
~
w
>
Z
o
(J
~
PAGE 10·145
MULTIPLEXERS
ANALOG SWITCHES
MULTIPLEXERS!ANALOG SWITCHES
INDEX
PRODUCT
TITLE
MUX-08
MUX-16
MUX-24
MUX-28
SW01/02
SW03/04
SW06
SW201
SW202
SW7510/7511
8 Channel BI-FET Analog Multiplexer ........ " ...... ," .. " ................. " .............. 11-5
16 Channel BI-FET Analog Multiplexer ....... " .. , ...... '.' ....... ; ......... , . .. .. . . . . . .. .. 11-14
Dual4-Channel BI-FET Analog Multiplexer ......................................•.......... 11-5
Dual 8-Channel BI-FET Analog Multiplexer ................•.•.•..... , .. . . . . .. . . .. .•. .. .. .. 11-14
Quad SPST BI-FET Analog Switches ...................................... ; ............... 11-24
Quad SPST BI-FET Analog Switches ...................................................... 11-24
Quad SPST BI-FET Analog Switch ........................................................ 11-30
Quad SPST BI-FET Analog Switches .... , ., ................................ " ............. 11-40
Quad SPST BI-FET Analog Switches .............................•......... , . . . . . . . . . . . . .. 11-40
Quad SPST BI-FET Analog Switches ...................................................... 11-47
PAGE
INTRODUCTION
Analog multiplexers and switches find applications in data
acquisition, metrology, telemetry, process control and telephony systems. Multiplexers are multiple analog switches
which share a common output. An on-chip address decoder
selects the appropriate input by means of a binary code. All
channels may be deactivated by an enable/disable control
pin.
In the past multiplexers/switches have been manufactured
with hybrid, monolithic CMOS or dielectrically isolated
CMOS technologies. The merging of ion implant techniques
with the standard bipolar process creates a fourth technological alternative - The BIFET process. High-quality ion Implanted p~channel FET's can now be compatibly processed
with bipolar devices.
The cost of hybrid devices limits their use to applications
which require the extremely low "RON" resistance made
possible by discrete FET's. MOS technologies are inherently
plagued by SCR "latch up" problems and analog signal
overvoltage destruction. The use of buried layers and expensive dielectric isolation processing can eliminate the SCR
failure mode, but the overvoltage blowout problems can be
solved only by adding large series input resistance with each
switch. This increases system errors since the equivalent
"RON" may typically be over 1000 ohms.
BIFET switches have no SCR "latch up" tendency and can
withstand analog input overvoltages while maintaining low
"RON" resistance. In addition, the special handling required
with CMOS devices is not necessary with BIFET switches.
In selecting analog multiplexers allentlon must be paid to
several key specs. Break-before-make switching insures no
two-channel .. inputs are simultaneously connected. This
prevents input sensor damage and misoperatlon. Acquiring
analog input signals within a specified time and error band
are primary concerns affected by "RON" resistance and
"Cour" capacitance specifications. A low "RON" insures
minimum signal allenuation and maximum accuracy. The
"Cour" capacitance forms on R-C time constant with "RON"
placing fundamental limits on signal acquisition time. Low
"RON" and "Cour" insures minimum elapsed time between
the channel select command and the ac'qulsltlon of data to
within a specified error band. High cross talk and off isolation specifications prevent unselected input signals from affecting the signal path.
PMI offers a wide selection of single-ended and differential
multiplexers and switches. Sixteen and eight-channel multiplexers as well as differential eight and four-channel devices
are available. Dual and Quad SPST switches in normally
closed and open configurations are also available. All devices
are pin-for-pin replacements for many industry standard
CMOS devices.
PAGE 11·2
ANALOG MULTIPLEXER AND SWITCH DEFINITIONS
ANALOG INPUT LEAKAGE CURRENT (IS(OFF)l
The algebraic sum of diode current losses from an
"OFF"-channel source input to the power supplies, ground
and through the channel. Specified as an absolute value, as
the direction of current flow is not predictable_
ANALOG OUTPUT LEAKAGE CURRENT (ID(OFF)l
The algebraic sum of diode current losses from an
"OFF"-channel "0" output to the power supplies, ground
and through the channel_ Specified as an absolute value, as
the direction of current flow is not predictable_
lo(OFF), Is(OFF) TEST CONDITION DEFINITIONS
CHANNEL CAPACITANCE (Css(OFF), Coo(OFF)
The capacitance between the D(S) teminals of any two
channels.
CROSSTALK (CT)
The proportionate amount of cross-coupling from an "OFF"
analog input channel to the output of another "ON" output
channel. expressed in dB.
DIGITAL INPUT CAPACITANCE (Co IG)
The capacitance between a digital input and ground.
LOGIC "0" INPUT CURRENT (liNt>
The current flowing Into a digital input when a specified lowlevel voltage is applied to that input.
LOGIC "0" INPUT VOLTAGE LEVEL (VINt>
The maximum (or most-positive) digital low-level input
voltage for which proper operation of the device is
guaranteed.
LOGIC "1" INPUT VOLTAGE LEVEL (VINH)
The minimum (or least-positive) digital high-level input
voltage for which proper operation of the device is
guaranteed.
NEGATIVE VOLTAGE SUPPLY (V -)
The most negative voltage supply with respect to ground .
POSITIVE VOLTAGE SUPPLY (V +)
The most positive voltage supply with respect to ground.
NOTES:
1.
SWITCHES TURNED "OFF" VIA ENABLE PIN OF DECODER
LOGIC FOR 10 (OFF), IS (OFF) MEASUREMENTS.
2.
IS (OFF) IS TESTED AT EACH INPUT (SOURCe) TERMINAL.
ANALOG INPUT-TO-INPUT CAPACITANCE (COS(OFF)l
The equivalent capacitance which shunts as open switch
effectively between "S" and "0" output.
ANALOG INPUT CAPACITANCE (Cs(ON))
The capacitance between an analog "S" input and ground
with the channel "ON"_
ANALOG INPUT CAPACITANCE (CS(OFF)l
The capacitance between an analog (S) input and ground
with the channel "OFF."
ANALOG OUTPUT CAPACITANCE (CD(OFF)l
The capacitance between the analog (DRAIN) output and
ground with the channel "OFF_" High-frequency transmission and output settling time characteristics are highly influenced by this parameter In conjunction with RON.
"OFF" ISOLATION (ISOOFF)
The proportionate amount of a high-frequency analog input
Signal which is coupled through the channel of an "OFF"
device. This feedthrough is transmitted through COS(OFF) to
a load comprised of CO(OFF) in parallel with an external load.
Isolation generally decreases by 6dB/octave with increasing
frequency.
"ON" RESISTANCE (RON)
The series "ON" - channel resistance measured between
addressed "S" input and "0" output terminals under
specified conditions.
"ON" RESISTANCE MATCH (RON MATCH)
The channel-to-channel matching of "ON" resistance when
channels are operated under identical conditions.
RON MATCH = Ri - RAVG X 100%
RAVG
where
N
= # of channels in package (i.e., for MUX-08 N = 8,
for MUX-16 N=16, etc.)
= Each channel's "ON" resistance
N
~ Ri
i=1
RAVG = "":""'-::N':--
ANALOG OUTPUT CAPACITANCE (Co(ON»
The capacitance between the analog "0" output and ground
with the channel "ON".
BREAK-BEFORE-MAKE DELAY (IOLY)
The elapsed time between the turn-off of one analog input
and the subsequent turn-on of another Input as determined
by the appropriate instantaneous change in the digital input
code for both inputs measured between the outputs' 50%
transition pOints.
"ON" RESISTANCE VARIATION (aRoN)
The variation of "ON" resistance produced by the specified
analog input voltage change with a constant load current.
Ll.R ON
(%) =
R ON
lv A
=-10V -
R_~~~=+10V x 100%
RON IVA
PAGE 11-3
=
OV
•
"ON" CHANNEL ANALOG LEAKAGE CURRENT
(ID(ON) + IS(ON~
.
.
Current 1055 (or gain) through an "ON"-channel creating a
voltage offset across the device_ As the direction of current
flow Is not predictable, only the magnitude is specified at
various temperature ranges.
OUTPUT ENABLE DELAY TIME "ON" (ION(EN~
MULTIPLEXERS
The time required to connect the analog output to the
analog Input determined by the digital address Input code. It
is measured from the 50% pOint of the ENABLE Input logic
change to the time the output Is within 90% of final value.
I(ON) TEST CONDITION DEFINITIONS
OUTPUT "ON" SWITCHING TIME (ION)
The time required to connect the analog output to the
analog input. The time Is measured from the 50% point of
the logic input change to the time the output reaches 90%
of the final value.
S20---+-~
830---+--<
W
....I
PLASTIC
DIP
TEMPERATURE
RANGE
MUX08EP
MIL
INO
COM
MUX08FP
MIL
INO
COM
MUX24EP
MIL
INO
COM
MUX24FP
MIL
INO
COM
MUX24BO"
MUX24FO
III
a..
5
:;)
:IE
1S-PIN DUAL-IN-LiNE PACKAGE
(Q or P Package)
• Also available with MIL-STD-8838 processing. To order add/883 as a suffix to
the part number.
t All listed parts are available with 160 hour burn-in. See Ordering Information,
Section 2.
PAGE 11-7
MUX-08/24 8-CHANNEL/DUAL 4-CHANNEL BI-FET ANALOG MULTIPLEXERS
DICE CHARACTERISTICS
1.
2.
3.
4.
5.
6.
7.
8.
(125° C TESTED DICE AVAILABLE)
MUX-08
MUX-24
DIE SIZE 0.090 X 0.061 Inch
DIE SIZE 0.090 x 0.061 i'rich
ADDRESS BIT ZERO (Ao)
ENABLE
NEGATIVE SUPPLY VSOURCE ONE (S1)
SOURCE TWO (S2)
SOURCE THREE (S3)
SOURCE F.OUR (S4)
DRAIN
9.
10.
11.
12.
13.
14.
15.
16.
SOURCE EIGHT (S8)
SOURCE SEVEN (S7)
SOURCE SIX (S6)
SOURCE FIVE (S5)
POSITIVE SOPPLY V+
GROUND (GND)
ADDRESS BIT TWO (A 2 )
ADDRESS BIT ONE '(A,)
1.
2.
3.
4.
5.
6.
7.
8.
ADDRESS BIT ZERO (AO)
ENABLE
NEGATIVE SUPPLY
SOURCE 1A (S1A)
SOURCE 2A (S2A)
SOURCE 3A (S3A)
SOURCE 4A (S4A)
DRAIN A
9.
10.
11.
12.
13.
14.
15.
16.
DRAINB
SOURCE 4B (S4B)
SOURCE 3B (S3B)
SOURCE 2B (S2B)
SOURCE 1B (S1B)
POSITIVE SUPPLY
GROUND
ADDRESS BIT 1 (A1)
Refer to Section 2 for additional DICE Information.
ELECTRICAL CHARACTERISTICS
PARAMETER
at 25° C for V+ = 15V. V- = -15V and TA = 25° C. unless otherwise noted.
MUX-OS/
24-NT
LIMIT
MUX-OS/
24N
LIMIT
MUX-OS/
24GT
LIMIT
MUX-OS/
24G
LIMIT
SYMBOL
CONDITIONS
"ON" Resistance
RON
Vo=OV,
Is = 2OOl'A
Digital "1" Input Voltage
V1NH
2.0
2.0
2.0
2.0
VMIN
Digital "0" Input Voltage
V1Nl
0.8
0.8
0.8
0.8
V MAX
Digital "0" Input Current
V1N =0.4V
10
20
10
TA = 125°C
10
20
10
IINl
I'AMAX
I'AMAX
Digital "0" Enable Current
VEN = O.4V
10
10
TA = 125°C
10
20
10
IINllENI
I'AMAX
I'AMAX
Positive Supply Current
(All Digital Inputs Logic "0")
1+
12
15
12
12
15
12
TA = 125°C
mAMAX
mAMAX
Negative Supply Current
(All Digital Inputs Logic "0")
1-
3.8
5
3.B
3.B
5
3.B
TA = 125°C
mAMAX
mAMAX
Analog Input Range
VA
±10
±10
±10
±10
VMIN
TYPICAL ELECTRICAL CHARACTERISTICS
for MUX-OB/24NT
300
400
TA = 125°C
300
400
400
520
20
at V+ = 15V, V-=-15V and TA = 25°C for MUX-OB/24N
UNITS
fiMAX
fiMAX
& G, TA = 125°C
& GT, unless otherwise noted.
MUX-OSN MUX-24N MUX-OSG MUX-24G
MUX-OSNT MUX-24NT MUX-OSGTMUX-24GT
TVP
TVP
TYP
TVP
PARAMETER
SYMBOL
CONDITIONS
Switching Time
tTRAN
(Note 1)
1.3
1.3
2.1
2.1
I'S
Output Settling Time
ts
10V Step to 0.1% (Note 1)
1.5
1.5
1.9
1.9
I'S
UNITS
Break-Belore-Make Delay
t OlY
(Note 1)
0.8
O.B
1.0
1.0
I'S
Crosstalk
CT
(Note 1)
70
70
70
70
dB
.1RON With Applied Voltage
.1RON
-10V" Vo " 10V, Is = 2ool'A
2.0
2.0
6.0
8.0
%
Leakage Current (Switch "ON")
IOIONI
Vo= 10V (Note 1)
1.0
0.5
1.0
0.5
nA
Analog Input Range
VA
+111
-15
+111
-15
+111
-15
+111
NOTES:
1. The data shown is extrapolated from measurements made on the
packaged devices.
-15
V
2. The ground (GND) pin must be 2:4V above the V- pin to include -4V
PAGE 11-8
logiC levels.
MUX-OB/24 B-CHANNEL/DUAL 4-CHANNEL BI-FET ANALOG MULTIPLEXERS
TYPICAL PERFORMANCE CHARACTERISTICS (Applies to all grades unless otherwise noted.)
MUX-08
BREAK-BEFORE-MAKE
SWITCHING
·AL'" lk!!, C,- '" 10pF,
VOLTAGE = 2V/DIV
TIME - 500nS/DIV
v,
B
~
MUX-08
SMALL SIGNAL SWITCHING
MUX-08
LARGE SIGNAL SWITCHING
·RL = lMn, CL = 10pF.
lOV
v, = -lOV, Va = +lOV
*RL = 1M!!, CL '" 10pF, Vl = -SOOmV, Va '" tSOOmV
VOLTAGE = SOOmV!DIV
TIME'" 1jJS!DIV
VOL lAGE = 5V!DIV
.
TIME = l$'S!DIV
MUX-08
SMALL SIGNAL SWITCHING
WITH FILTERING AND
2.5j.1s SAMPLE TIME
MUX-08
SMALL SIGNAL SWITCHING
WITH 21'1 SAMPLE TIME
MUX-08
SMALL SIGNAL SWITCHING
WITH FILTERING
III
·AL = lMfl, CL = 10pF.
-At. = lMH, CL '" 500pF, V, = 500mV, Va '" +50OmV
VOL lAGE '" SOOmV/DIV
TIME = l~S/DIV
v, = -500mV, V8 = +500mV
"RL'" 1Mn, CL '" SOOpF, Vl '" -500mV, Va '" +500mV
VOLTAGE'" 5OOmV!DIV
TIME'" 500nS!DIV
VOLTAGE = 500mV/DIV
TIME = SoonS/DIV
"Top Waveforms: Digital Input -5V/DIV
II)
a:
><
III
III
...I
Bottom Waveforms: Multiplexer Output
Do
5
~
::E
MUX-08
CROSSTALK AND OFF ISOLATION
PERFORMANCE OF CHANNEL 8
~
"~
~
"'"0
2
0
"~"
~
~
0
:,
.,.>
>'"
140
MUX-08
CROSSTALK AND OFF ISOLATION
PERFORMANCE OF CHANNEL 8
~ 140
CERAMIC'lcl PACKAGj;
120
i'20
100
so
.
'"o
so
~
TA = 25°C
o
CROSSTALK:
RL = lMfl, CL = 10pF. Vs = +5V RMS
20
100
is
~
V(+) = +15V
Vf-I = -15V
40
5
OFF ISOLATION:
AL " lkS1. CL = 10pF. VS" +5V AMS
~
VH = -15V
40
TA = 25"C
.
10k
lOOk
FREQUENCY (Hz)
1M
10M
~-
I r!-~-·["'-'~~i~:i~--_:M~U~X~·"tA~.
Et"".,;2~
.....
i Illiil I II
:d W~~TLlI
1tll:
""'"
~
"to
OFF
'''"''
lOOk
FREQUENCY (Hz)
PAGE 11-9
1M
-.
-
~-
--i'""'"'"
r-f--"=:~-
ISOLATION
...-
-~--
__
,-
CROSSTALK:
RL '" lMH, C L '" 10pF, Vs '" +5V RMS
OFF-ISOLATION:
RL '" lkH, CL '" 10pF, Vs '" +SV RMS
10k
r--------r--- MUX.08B, F ~
RL = 10Mn-· -i.....t'"
C L "'10pF
I
0
1k
~~: ~~5V
2,0
~
V(+) = +15V
I --t+---. -_.-
2.5~,
~:.tVD
t'-
60
TRANSITION TIMES
vs TEMPERATURE
10M
-so
-25
---= _ __ _
-::.~==
- - -
-
25
50
TEMPERATURE (OC)
75
100
125
MUX-08l24 a-CHANNELIDUAL 4-CHANNEL BI-FET ANALOG MULTIPLEXERS
TYPICAL PERFORMANCE CHARACTERISTICS (Applies to all grades unless otherwise noted.)
"ON" RESISTANCE (Row
ANALOG VOLTAGE (V N
ENABLE DELAY TIMES
VI TEMPERATURE
2,5 , . . . . . - - - - - ; - . , . - - , - - . - - ,
v+
2,0
i
=
-
~ 1.0
50
75
100
-10
125
IV+ .I
,5}
--
I-- v- = -15V
~ 500
TA = 2SoC
Q
~i
w
~4OD
~
f
ij300
,
MJX*¥
-..:+
'
/ ' "'t -+-:
-- --
MUX-OBA, E
ii
'" 200
-6
I--1200
--400
-1600
-BOO
0
400
; 300
'" 200
400
800
1200
1600
2000
0
SWITCH LEAKAGE CURRENTS
VB TEMPERATURE
12.5
12
= +15V
-r---= r-----ID{OFF)I~
VO =IOV
y l=k
i.--'"' ~
IsiON) + 'ofON} I
V-
I.
1
0
~
~-
125
f:!~ 0,01
>-
z
:J!
!58
7
l1
6
~ 4~~~U~X~'~~A~'~E~~~:1:::t==!:~
IJ,L I
V-=-15V -
l-
;: 6
~-
~
-. -,- IS(OFF)
°c
> 5
ISIOFF)
0.01
50
600
I
1--.;;;.,
11
E: V- '" -16V
F
~
SUPPLY CURRENTS
VB TEMPERATURE
100
E VS =10V
25
TEMPERATURE
r---
F
'"a:
H.-£-f-=--I"'=-+--+-+-t---+
-25
400
~A:;; 2~o5~ r-·-
ffi
H--+--I---~j£---1
-50
200
10~~
~;-f=~
1.0
,,0.10
ii,
0
SWITCH LEAKAGE CURRENTS
VB ANALOG INPUT VOLTAGE
!
IS - SWITCH CURRENT btAl
:-- v+
-800 -600 -400 -200
RON VI TEMPERATURE
1
i
-- -I-I-- - Vs - SWITCH VOLTAGE (mV)
~100~--+-+--+--+-+-+--1
100
-2000
100
10
--i+++-f-
0
-8
VA - ANALOG INPUT VOLTAGE (VOLTSj
RON VB SWITCH CURRENT (Is)
;;;
vt1-~
MUX-OBA, E
TEMPERATURE 1°C)
600
,/
1---
MUX-08A, E - toFF
25
MUX-oBB F
0
-- MUX..()8B, F
toFF
0
TA"~OC
~t~
MUX-08A, E
tON
-25
v- =- -1SV
-
iVjS!'l'j'°iV~l'~I1~~;j~~:-j
-50
V+ - +lSV
-
--I----+---+-01'''''I---j
MUX-08B, F
VS1=2V
~
600
400
+1SV
V-'= -15V
VS2 - VS8 co OV
RL"= 1kG
MUX·08A. E
RON VI SWITCH VOLTAGE (V so)
VB
-12
-8
1---
-
-4
V~ - ANALOG INPUT VOLTAGE (VOLTS)
12
MUX-08/24 8-CHANNEL/DUAL 4-CHANNEL BI-FET ANALOG MULTIPLEXERS
TYPICAL PERFORMANCE CHARACTERISTICS (Applies to all grades unless otherwise noted.)
MUX-24
SMALL SIGNAL SWITCHING
WITH 2p.s SAMPLE TIME
MUX-24
SMALL SIGNAL SWITCHING
WITH FILTERING
MUX-24
SMALL SIGNAL SWITCHING
v,
v,
"RL = 1M.a, CL" 10pF,
= -SOOmV,
V4 = +5OOmV
VOLTAGE = SOOmV!DIV, TIME = l$LS/DIV
"RL = lMn, CL = 500pF,
= -500mV,
V4'" +500mV
VOLTAGE = 500mVfOlV, TIME = l~S/DlV
MUX-24
SMALL SIGNAL SWITCHING
WITH FILTERING
AND 2.5¢1 SAMPLE TIME
"RL = lMn, CL = 10pF.
v,
v,
*RL
= -500mV,
MUX-24
LARGE SIGNAL SWITCHING
MUX-24
BREAK·BEFORE·MAKE SWITCHING
·RL = 1Mil. CL =- 500pF,
= -soOmv,
V4" +900mV
VOLTAGE = 500~V/DIV. TIME = SOOnS/DIV
v,
V4 = +9OOmv
VOLTAGE = SOOmV/DIV. TIME = SOOnS/DIV
•
V, ..
= lkil, CL = 10pF,
4 = lOV
VOLTAGE = 500mV/DIV •
"Rt. = lM.a, CL = 10pF,
-TDV, V4 = +lOV
VOLTAGE = SOOV/DIV, TIME = tlLS/DIV
UI
a::
w
:
...I
A-
12
L=,L
I
v- = -15V
10
ALL DIGITAL
INPUTS ARE
lOGIC "0"
LU
v- =
m140~-n~r-rn~~~-m~~~
3
i"
-15V
5
ColON}
........
r- ........
IV.
-~
r-H="NL -
o
-55
MUX-24
CROSSTALK AND OFF
ISOLATION PERFORMANCE
OF CHANNEL 3A
MUX-24
SWITCH CAPACITANCES VB
ANALOG INPUT VOLTAGE
DIGITAL INPUT BIAS CURRENTS
VB TEMPERATURE
CS(OFFI
15~
60
is
40
0256075
TEMPERATURE
°c
100
126
-12
....
-4
VA - ANALOG INPUT VOLTAGE (VOLTS)
PAGE 11-11
12
v+ '" 1SV
V- '" -15V
~~;~;lK: -t++m-II-i--HIt--t+'-tlII
AL = 1MD, CL '" 10pF, Vs '" 5V RMS
RON (SWITCH NO.4) = 300n
I
~
.,.
't
-26
t-H-t+tll!k-''''krn
8°r-rH~t-~~~~H-
5
~
-~
120
100
20
OFF ISOLATION:
RL = lkil. CL = 10pF. Vs '" 5V RMS
1k
10k
lOOk
FREQUENCY (Hz)
1M
'OM
S
:::I
:::I!
MUX-08/24 8-CHANNEL/DUAL 4-CHANNEL BI-FET ANALOG MULTIPLEXERS
A.C. TEST CIRCUITS
OFF-ISOLATION MEASUREMENT CIRCUIT
TRANSITION TIME TEST CIRCUIT
FIGURE 1.
FIGURE 6.
+16V
ALl. CHANNeLS
ARE OFf
LOGI
INPUT
1-..-......-oVD
( I DENOTES MUX-24
( ) DENOTES MUX-24
ENABLE DELAY TIME TEST CIRCUIT
SWITCHING TIME WAVEFORMS
SWITCH
OUTPUT
Vo
(SEE FIG.1)
( ) DENOTES MUX-24
SWITCH
OUTPUT
Vo
BREAK-BEFORE-MAKE TEST CIRCUIT
(SEE FIG. 21
Vo
SWITCH
OUTPUT
60%
Vo
(SEE FIG. 3)
3.5V
LOGIC INPUT
( ) DENOTES MUX-24
50%
CROSSTALK MEASUREMENT CIRCUIT
FIGURE 4.
APPLICATIONS INFORMATION
son
( ) DENOTES MUX-24
These analog multiplexers employ ion-implantedJFETs in a
switch configuration designed to assure break-before-make
action. The turn-off time Is much faster than the turn-on
time to guarantee this feature over the full operating
temperature and input voltage range. Fabricated with BIFET processing, special handling as required with CMOS
devices, Is not necessary to prevent damage to this multiplexer. Because the digital inputs only require a 2.0V logic
"1" input level, power-consuming pullup resistors are not
PAGE 11-12
MUX-08/24 8-CHANNEL/DUAL 4-CHANNEL BI-FET ANALOG MULTIPLEXERS
The positive-going slew rate was 0.3V1"s which Is equivalent
to a normal loss of 3mA. The negative-going slew rate was
O.7V1"s which is equivalent to a "reverse" lossof 7mA. Note
that when switch 1 is first turned "ON" it has a drop of -20V
across its terminals. In spite of that fact, the current is
limited to approximately twice Its normal loss.
required for TTL compatibility to insure break-make switching as is most often the case with CMOS multiplexers. The
digital inputs utilize PNP input transistors where input
current is maximum at the logic "0" level and drops to that of
a reverse-biased diode (about 10nA) as the input voltage is
raised above'" 1.4V.
The "ON" resistance, RON, of the analog switches is constant over the wide input voltage range of -15V to +11V
with VSUPPLY = ±15V. Higher input voltage is tolerable provided that some form of current limiting Is employed (such
as that of an op-amp output stage) to avoid exceeding junction temperature and power dissipation requirements. For
normal operation, however, positive Input voltages should be
restricted to 11V (or 4V less than the positive supply). This
assures that the VGS of an "OFF" switch remains greater than
its Vp, and prevents that channel from being falsely turned
"ON". When operating with negative Input voltages, the gateto-channel diode will be turned on if the voltage drop across
an "ON" switch exceeds -{).6V. While this condition will
cause an error in the output, it will not damage the switch. In
lab tests, the multiplexer output has been loaded with a
0.01"F capacitor in the circuit of Figure 1. With V 1 = -10V
and Va = +10V, the logic input was driven at a 1kHz rate.
CROSSTALK AND OFF-ISOLATION
Crosstalk and off-isolation performance is influenced by the
type of package selected. Epoxy (P) packaged devices typicallyexhlbit a 12dB improvement in off-isolation (f =500kHz)
performance when compared to ceramic (Q) packaged devices. Epoxy packaged devices typically exhibit a 15dB
improvement in crosstalk (f = 500kHz) performance when
compared to ceramic (Q) packaged devices.
SINGLE SUPPLY OPERATION OF
BIFET MULTIPLEXERS
PMI's BI FET multiplexers will operate from a single positive
supply voltage with the negative supply pin at ground potential. The analog signal range will include ground.
For complete information refer to application note, AN-32.
TYPICAL PERFORMANCE CHARACTERISTICS
OYERYOLTAGE Y-I
CHARACTERISTIC
OYERYOLTAGE Y-I
CHARACTERISTIC
30
30
20
MUX-OB
T A =25"C
TA = 25 C
Vsl+J = 15V
20
E = ·15V FOR VA> 0
E = +10V FOR VA
<0
I
II
,---r---r-,--r-,..--,---r---,
MUX-OB
Vs = '15V
V N " +6V
POWER-LOSS Y-I
CHARACTERISTIC
VsH = OV (GROUND)
V N = +5V
....-
MUX-08
TA = 25 C
Vs(+J = OV (GROUND)
-1_+-+-1
20
V N = OV
E = -lOY
-+--+-I--j
E '" -lOY
III
II:
W
>C
I
11
/
~
IL
5
::;)
...
-10
:&
20
-20
-10 '---'---'_-'--1._"'---'---'---'
-40
-20
20
40
40
VAIVOLTSI
-1~"'---'--_""20--'--'--'----:'20"--'--'40
VAIVOL lS)
VAIVOLTSJ
OYERYOLTAGE/POWER-LOSS
MEASUREMENT TEST CIRCUIT
VI+J· +15V
0----1 EN
0----\ NC{DB)
+s.ov
V{+I
"{S4AI
-'F
• S1A-S3A
S1B-S4B
A2 INe)
0--+--\ A,
Ao
aND
MUX-OB 8 , - 5 7 \ - - - - '
MUX-24
(.)
OIDA)
~ VE
V(-) '" -15V
{ I DENOTES MUX-24
PAGE 11-13
~ VA
MUX-16/MUX-28
PMI
16 CHANNEL/DUAL 8 CHANNEL BI-FET
ANALOG MULTIPLEXERS
®
OVERVOLTAGE PROTECTED
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
The MUX-28 is a monolithic 8-channel differential analog
multiplexer configured in a double pole, 8-position (pius
OFF) electronic switch array. For single 8-channel and dual
4 channel models, refer to the MUX-08/MUX-24 data sheet. A
3-bit binary input address connects a pair of independent
analog inputs from each 8-channel input section to the
corresponding pair of independent analog outputs. Disconnection of both inputs is provided by a logical "0" at the
ENABLE input, thereby offering a package select funciton.
MUX-16 Pin Compatible With DG506, HI-506A, AD7506
MUX-28 Compatible With DG507, HI-507A, AD7507
JFET Switches Rather Than CMOS
No SCR Latch-up Problems
Low "ON" Resistance - 290!lTyplcal
Digital Inputs Compatible With TTL and CMOS
Low Leakage Current
Break-Before-Make Action
Overvoltage Protected
Supply Loss Protection
125 0 C Temperature-Tested Ole Available
Highly Resistant To Static Discharge Damage
GENERAL DESCRIPTION
The MUX-16 is a monolithic 16-channel analog multiplexer
which connects a single output to 1 of the 16 analog inputs
depending upon the state of a 4-bit binary address. Disconnection of the output is provided by a logical "0" at the
ENABLE input, thereby providing a package selection
function.
Fabricated with Precision Monolithics' high performance BIFET technology, these devices offer low, constant "ON" resistance. Performance advantages include low leakage currents and fast settling time with low crosstalk to satisfy a wide
variety of applications. These multiplexers do not suffer from
latch-up or static discharge blow-out problems associated
with similar CMOS parts. The digital inputs are designed to
operate from both TTL and CMOS levels while always providing a definite break-before-make action without the need for
external pull-up resistors.
FUNCTIONAL DIAGRAM
51
52
53
S4
55
56
57
88
DRAIN
A
SlA S2A S3A S4A SSA S6A
S7A SSA
EN
A3~c=J
A2
A1
v+
GND
EN
v+
A2
GND
A1
v·
AO
v·
AD
DRAIN SlB S2B S3B S4B SSB
o
DRAIN
B
59 510 511 512 813 514 815 516
MUX-16
MUX-28
PAGE 11-14
S6B S7B saB
MUX-16/28 16-CHANNELIDUAL 8-CHANNEL BI-FET ANALOG MULTIPLEXERS
ABSOLUTE MAXIMUM RATINGS(Ratings apply to both DICE and packaged parts, unless otherwise noted.)
Operating Temperature Range,
MUX-16/28-AT, BT •••••••••••••••••• -SS·C to +12S·C
MUX-16/28-ET, FT .................... -2S·C to +8S·C
Lead Soldering Temperature
•••••••••••• 300·C (60 SEC)
Maximum Junction Temperature •••••••••••••••••• 1S0·C
V+ Supply to V- Supply ••••••••••••••••••••••••••••
36V
Dice Junction Temperature (Ti ) ••••••• --6S·C to +1S0·C
Storage Temperature Range •••••••••••• --6S· C to +1S0· C
Analog Input Voltage •.•. V-Supply-20V to V+ Supply+20V
Power Dissipation ............................. 1000mW
Maximum Current Through Any Pin
ELECTRICAL CHARACTERISTICS at Vs
Logic Input Voltage (Note S) •••••••••••• -4V to V+ Supply
••••••••••••••• 2SmA
= ±1SV and TA = 2S·C, unless otherwise noted.
PARAMETER
SYMBOL
CONDITIONS
"ON" Resistance
RON
V o "10V.l o ,,200,,A
.!.RON With Applied Voltage
.!.RON
-10V " Vo " 10V, Is = 200"A
RON Match Between Switches
RON Match
Vo = OV. Is = 200"A
Analog Voltage Range
VA
Is= 100"A
Is= 100"A
Source Current (Switch "OFF")
MUX-16A/E
MUX-28A/E
MUX-16B/F
MUX-28B/F
MIN
MIN
+10
-10
TYP
MAX
TYP
MAX
290
380
400
580
n
1.5
7.5
4.0
4.5
%
7
15
9
20
+11
-15
+10
-10
+11
-15
UNITS
%
Volts
Is(OFF}
Vs = 10V, Vo = -10V (Note I)
0.01
1.0
0.01
2.0
nA
Drain Current (Switch "OFF")
lo(OFF}
Vs= 10V. V o =-10V (Note I)
MUX-16
MUX-2S
0.2
0.1
1.0
1.0
0.2
0.1
2.0
2.0
nA
nA
Leakage Current (Switch "ON")
lo(ON}
+ls(ON}
Vo= 10V (Note 1)
MUX-16
MUX-2S
0.2
0.1
1.0
0.5
0.2
0.1
1.0
0.5
nA
nA
Digital Input Current
liN
Y'N = O.4V to 15V
1.0
10
1.0
10
"A
Digital "0" Enable Current
I'Nl(EN}
VEN =0.4V
4.0
10
4.0
10
p.A
Digital Input Capacitance
C OIG
Switching Time
tTRAN
(Note2)
1.0
2.1
"Sec
Output Settling Time
ts
1(iV Step to 0.10% Accuracy
10V Step to 0.05% Accuracy
10V Step to 0.02% Accuracy
1.5
1.7
2.5
1.9
1.9
1.9
0.7
1.0
3.0
3.0
1.5
1.5
pF
GO
~Sec
Enable Delay "ON"
tON (EN)
(Note 6)
1.0
2.0
1.2
Enable Delay "OFF"
tOFF (EN)
(Note 6)
0.25
0.5
0.25
"OFF" Isolation
ISO OFF
(Note4)
66
66
dB
Crosstalk
CT
(Note3)
75
75
dB
Source Capacitance
CS(OFF)
Switch "OFF",
Vs = OV. Vo = OV
2.5
2.5
pF
Drain Capacitance
Co(OFF}
Switch "OFF",
Vs+OV, Vo=OV
MUX-16
MUX-2B
13
B.O
13
8.0
pF
pF
Positive Supply Current
(All Digital Inputs
Logie "0" or "I")
1+
MUX-16
MUX-2B
MUX-16
MUX-2B
15
15
12
12
19
19
9.0
S.O
S.O
7.0
19
19
mA
mA
mA
mA
Negative Supply Current
(All Digital Inputs
Logic "0" or "I")
1-
MUX-16
MUX-2B
MUX-16
MUX-2S
5.0
5.0
4.0
4.0
7.0
7.0
3.5
3.0
3.0
2.5
7.0
7.0
mA
mA
mA
mA
V-=-15V
V-=-5V
NOTES:
1. Conditions applied to leakage tests insure worst case leakages. Exceeding
l1V on the analog input may cause an "OFF" channel to turn "ON."
2. Rl = 10Mn, C l = 10pF.
3. Crosstalk is measured by driving channel S (SB') with channel 7 (7B') ON.
Rl = lMn, C l = 10pF, Vs = 5V RMS, I = 500kHz.
4. OFF isolation Is measured by driving channelS (SB') with ALL channels
OFF.
"Sec
::I!
2.5
"Sec
0.5
IlSee
III
II:
Rl =lkn, C l =10pF, Vs =5VRMS, F=500kHz. Coslscomputedlromthe
OFF isolation measurement.
5. The ground (GND) pin must be ;"4V above the V- pin to include-4V logic
levels.
6.
PAGE 11-15
Sample tested.
'"0;><
tOLV
V+=5V
N
"-
:;)
Break-Belore-Make Delay
V+= 15V
II
III
><
III
....
Q.
5
:;)
::I!
MUX-18128 18-CHANNELIDUAL a-CHANNEL BI-FET ANALOG MULTIPLEXERS
ELECTRICAL CHARACTERISTICS at Vs = ±15V, -55°C S TA S +125°C; for MUX-16AT/BT and MUX-28AT/BT and
-25°C S T AS +85° C for MUX-16ET/FT and MUX-28ET/FT, unless otherwise noted.
PARAMETER
SYMBOL
CONDITIONS
"ON" Resistance
RON
VoS 10, IDS 200pA
~RON
~RON
-10V S Vo S 10V, Is = 200,.A
RON Match
Vo=OV,ls=200pA
With Applied Voltage
RON Match Between Switches
MUX-18A/E
MUX-2SAlE
MIN TYP MAX
MUX-18B/F
MUX-28B/F
MIN TVP MAX
UNITS
500
soo
n
2.0
5.5
10
+10
-10
15
+11
-15
+10
-10
+11
-15
Analog Voltage Range
VA
Is = 200pA
Source Current (Switch "OFF")
IS (OFF)
Vs = 10V, Vo = -1011 (Note 1)
10
10
nA
Drain Current (Switch "OFF")
10 (OFF)
Vs = 10V, Vo = -10V (Note 1)
75
75
nA
Leakage Current (Switch "ON")
10(ON)
+IS(ON)
Vo= 10V (Note 1)
75
75
nA
Digital "1" Input Voltage
V(NH
Digital "0" Input Voltage
V(NL
Digital I nput Currant
liN
Digital "0" Enable Currant
I'NL(EN)
2.0
Volts
2.0
Volts
0.8
0.8
Volts
V,N = 0.4V to 15.0V
20
20
,.A
VEN = 0.4V
20
20
Positive Supply Currant
1+
All Digital Inputs Logic "0" or "1"
24
24
mA
Negative Supply Currant
1-
All Digital Inputs Logic "0" or "1"
8.2
8.2
mA
PIN CONNECTIONS
ORDERING INFORMATIONt
25°C
RESISTANCE
PACKAGE
HERMETIC DIP
2900'
2900
4000"
4000
290n"
290n
MUX16AT
MUX16ET
MUX16BT
MUX16FT
MUX28AT
MUX28ET
MUX28BT
MUX28FT
4000"
400n
TEMPERATURE
RANGE
v+
MIL
INO
MIL
INO
MIL
INO
MIL
INO
"Also available with MIL-STD-883B Processing. To order add 1883 as a suffix
to the pari number.
t All listed parts are available with 160 hour burn-In. See Ordering Information,
Section 2.
28-PIN HERMETIC DUAL-IN-LiNE
(T Sulflx)
PAGE 11-18
MUX-16/28 16-CHANNELIDUAL 8-CHANNEL BI-FET ANALOG MULTIPLEXERS
DICE CHARACTERISTICS (125° C TESTED DICE AVAILABLE)
MUX-16
MUX-28
DIE SIZE 0.108 X 0.075 Inch
DIE SIZE 0.108 X 0.075
1.
4.
5.
6.
7.
B.
8.
10.
11.
12.
14.
15.
1B.
POSITIVE SUPPLY
SOURCE 18 (518)
SOURCE 15 (515)
SOURCE 14 (514)
SOURCE 13 (513)
SOURCE 12 (512)
SOURCE 11 (S11)
SOURCE 10 (510)
SOURCE 9 (58)
GROUND
ADDRESS BIT 3 (A3)
ADDRESS BIT 2 (A2)
ADDRESS BIT 1 (A1)
17.
1B.
19.
20.
21.
22.
23.
24.
25.
2B.
27.
2B.
ADDRESS BIT 0 (AO)
ENABLE
SOURCE 1 (51)
SOURCE 2 (S2)
SOURCE 3 (S3)
SOURCE 4 (54)
SOURCE 5 (S5)
SOURCE B (88)
SOURCE 7 (S7)
SOURCE B (SB)
NEGATIVE SUPPLY
DRAIN
1.
2.
4.
5.
6.
7.
B.
9.
10.
11.
12.
15.
1B.
POSITIVE SUPPLY
DRAIN B
SOURCE B (SBB)
SOURCE 7 (S7B)
SOURCE 6 (SBB)
SOURCE 5 (S5B)
SOURCE 4 (S4B)
SOURCE 3 (S3B)
SOURCE 2 (S2B)
SOURCE 1 (S1B)
GROUND
ADDRESS BIT 2 (A2)
ADDRESS BIT 1 (A1)
17.
1B.
19.
20.
21.
22.
23.
24.
25.
26.
27.
2B.
ADDRESS BIT 0 (AO)
ENABLE
SOURCE 1 (S1A)
SOURCE 2 (S2A)
SOURCE 3 (S3A)
SOURCE 4 (S4A)
SOURCE 5 (S5A)
SOURCE 6 (SBA)
SOURCE 7 (S7A)
SOURCE B (SBA)
NEGATIVE SUPPLY
DRAIN A
Refer to Section 2 for addilional DICE Inlormatlon.
ELECTRICAL CHARACTERISTICS at 25° C for V+ = 15V, V- = -15V and
TA =
25° C, unless otherwise noted.
MUX-16!
28NT
MUX-16!
28N
MUX-16!
28GT
MUX-16!
28G
LIMIT
LIMIT
LIMIT
LIMIT
UNITS
380
380
580
800
580
OMAX
OMAX
PARAMETER
SYMBOL
"ON" Resistance
RON
Digital "1" Input Voltage
VINH
2.0
2.0
2.0
2.0
VMIN
Digital "0" Input Voltage
VINl
0.8
0.8
0.8
0.8
V MAX
Digital "0" Input Current
IINl
V 1N =0.4V
10
10
10
10
"A MAX
Digital "0" Enable Current
IINL(EN)
V EN = O.4V
10
10
10
10
"A MAX
Positive Supply Current
(All Digital Inputs Logic "0")
1+
19
19
19
19
mAMAX
Negative Supply Current
(Alt Digital Inputs Logic "0")
1-
7
Analog Input Range
VA
CONDITIONS
Vo=OV
Is= l00"A
TA = 25°C
TA = 125°C
540
mAMAX
II
CD
N
i&i
":'
><
::I
:::E
til
IX
W
><
W
...IL
5::I
:::E
±10
±10
±10
±10
VMIN
TYPICAL ELECTRICAL CHARACTERISTICS for V+ = 15V, V- = -15V and T A = 25°C, unless otherwise noted.
MUX-16!
28NT
MUX-16!
28N
MUX-16!
28GT
MUX-16!
28G
PARAMETER
SYMBOL
CONDITIONS
TYP
TYP
TYP
TYP
Switching Time
tTRAN
(Note 2)
1.5
1.5
2.1
2.1
"s
Output Settling Time
ts
10V Step to 0.1% (Note 2)
1.5
1.5
1.9
1.9
"s
Break-Before-Make Delay
tolY
(Note 2)
0.8
0.8
1.0
1.0
"s
Crosstalk
CT
(Note 2)
70
70
70
70
dB
<1RON With Applied Voltage
<1RON
-10V'; Vo ';10V, Is = 200"A
2.0
2.0
6.0
6.0
%
Leakage Current (SWitch "ON")
IOIONI
Vo = 10V (Note 2)
1.0
1.0
1.0
1.0
nA
Analog Input Range
VA
+111
+111
+111
-15
-15
-15
+11/
-15
V
NOTES:
1. For MUX-16/28NT and MUX-16/28GT electrical characteristics apply at
25° C and 1250 C, unless otherwise noted.
UNITS
2. The data shown is extrapolated from measurements made on the packaged
devices.
PAGE 11-17
MUX-16/28 16-CHANNELIOUAL 8-CHANNEL BI-FET ANALOG MULTIPLEXERS
TRUTH TABLE
EN
"ON"
CHANNEL
PAIR
X
L
NONE
L
H
L
H
H
H
L
H
A2
A,
Ao
X
X
L
L
L
L
uON"
"ON"
A3 A2 A, Ao EN CHANNEL A3 A2 A, Ao EN CHANNEL
X
X
X
X
L
NONE
H
L
L
L
H
9
L
L
L
L
H
1
H
L
L
H
H
10
2
L
L
L
H
H
2
H
L
H
L H
11
3
L
L
H
L
H
3
H
L
H
H
H
12
L
H
H
H
4
L
L
H
H
H
4
H
H
L
L
H
13
H
L
L
H
5
L
H
L
L
H
5
H
H
L
H
H
14
H
L
H
H
6
L
H
L
H
H
6
H
H
H
L
H
15
H
H
L
H
7
L
H
H
L
H
7
H
H
H
H
H
16
H
H
H
H
8
L
H
H
H
H
8
STATIC CHARACTERISTIC CURVES (apply to aI/ grades unless otherwise noted.)
"ON" RESISTANCE (RON)
VB ANALOG VOLTAGE (V A)
RONVI SWITCH VOLTAGE (V SD )
50.
600
IS = +200,uA MUX·16/28 B. F
4OO~+-~-r-+~~~~~-T~
500
vt= +~5V
v-= -16V
TA=25°C
MUX·16/28 B. F
.vr
V
IS = +200,uA MUX·16/28 A, E
~.~+-~-r-+~--+-~~-T~
RON VB SWITCH CURRENT (Is)
600
500
r- vl"
+,Jv
V_=_lSV
I- TA· 25'C
........
... V V .....
MUX"!f8 A, E
300
I-+-+--t--t--+--+ ~;= 26!~V-r-
~1~.~-_~6~~_~2~.~~2~~~L-~,.
~
I-
vi
=
+~5V
~UX.J6/28IB.F
V-=-15V
500 I- TA = 2S'C
.,
g"
"z
.P
~
/'
/'
...... V
200
600
-1000
2000
~
'OIOFFI
O. 1
II:
w
MUX-16/28 A,E
~
"~
60
1000
v+ - +15V
-15V
V
TA = 2SoC
.......
0.0 1
~
20
---
10-
il
,/
0
MUX-16128 A, E
MUX-28
SWITCH LEAKAGE CURRENTS
VI ANALOG INPUT VOLTAGE (V A>
<
So
L
TEMPERATURE (DCI
1/
1.•
V
-20
100
-2000
1200
r-
100
-6.
400
V
V
I.......
-000
V"
V
400
200
MUX-16
SWITCH LEAKAGE CURRENTS VI
ANALOG INPUT VOLTAGE (V A>
RON VI TEMPERATURE (T)
600
100
-800
-I--
200
Vso (mV)
VA (VOLTS)
.............
........
V+=+15V
100
MUX·16/28 B, F
100
140
•.001 L.....l.._L-.....!_--'-_L-~_..J
-15 -10
-5
10
15
20
VA (VOLTS)
PAGE 11-18
-
'SIOFF)
'OIONI_
0.00 1
-15
I
-10
-5
0
5
10
15
ANALOG INPUT VOLTAGE (VA)
20
MUX-16/28 16-CHANNEL/DUAL 8-CHANNEL BI-FET ANALOG MULTIPLEXERS
STATIC CHARACTERISTIC CURVES (apply to all grades unless otherwise noted)
SWITCH LEAKAGE CURRENTS
VB TEMPERATURE
,oo~~~~==!==~~~~~~
~ v+ = +1SV
V-"'-15V
Vs = +10V, Vo = -10V
1:
10
ii:
a
. . . r!:..
'0
,.
w
a! 1.0§~~~=f::::t~~~~~
~
...... .........
J,.LL
-kJ '
~
-50
-25
25
50
75
TEMPERATURE 1°C)
100
o
-.0
2
iii'130
!>
~
-20
02060
II
I
300n:, VN = +Q.SV
~ 20 OF;L l~l~~~:O:s ~L5~ ~~s.
~ 07.-~VwN~'~+~0.~4V~~~~~~~~~
lk
10k
'00
'40
I
0
-10 -8
--
-6
:3
I"'-
i
~
I
Q
>
v- = -15V
I'
......
-~~: ~~~v
0
4
OFF ISOLATION (PIN #3 FLOATING)
r.......
......
........
NOTE: INL (EN) PLOTTED SINCE OTHER DIGITAL INPUT CURRENTS ABE _
j-t,C"OSSTALK' "L,'M", CL"Op', Ys'SY
RMS, RON(SWITCHlII7B)=300n, VN=+5V
OFF ISOLATION: RL=1KIl, CL=10pF,
VS=5V RMS, VN"" +O.4V
10K
lOOk
(FREQUENCY (Hz)
II
I'-..
........
60
20
vJ. +\5V
GROUNDED)
CROSSTALK (PIN #3
FLOAnNG)-
TA = 25°C
• '0
-2
--4
DIGITAL INPUT BIAS
CURRENTS
VB TEMPERATURE (T)
I I II
0
CsfOFF)
I
VA (VOLTS)
OFF ISOLATION (PIN #3
......
~ 100
II I I I, I I: I
15 40 CR~Ss.:T:~KR=~. ~~:~w~ic~ ~:~ I
MU~
Col FFI
4
CROSIS~~LK (PIN ~~, G~O,u~,?,~~) .. U.J.) !.I11
o
~
•
MUX-2S
OFF PERFORMANCE OF
CHANNELS
"~ 120
~ ro~H1ffffir-rH~r-~~~~H*m
t2
lJ.L,l
;::.t-: ;;7' ~ONI
jUX"16/28IB,F
126
r-H-t++tItl-++f1+~"Io.H+ttttt-+++~
.L-t- fli
I-
MUX-16
OFF PERFORMANCE OF
CHANNELS
80
cotL
-1.,1
•
I I~ ....... r--.
r- ~ r- r-~
I
TEMPERATURE ('C)
~
f--
f-- I--
1-
~o.'=."*~
V+ = +15V
v- '" -15V
TA '" 25°C
'4
MUX-16/28 B,F
~
~
•
II
v+l. +,15V
'4 v- = -15V
-- lolON) + IsION)
FOR IS(OFF) ANO IOIOFF) -~}-,---1=~
VO=VS=+10VFOR
jOlON) + IsION)
....
§
SWITCH CAPACITANCES VB
ANALOG INPUT VOLTAGE (VIII
SUPPLY CURRENTS VB
TEMPERATURE (T)
26
100K
1 MEG
FREQUENCY (Hz)
10MEG
o
I
....0
ILES'i'
-'0 o
I
20
I
I
I
60
TEMPERATURE 1°C)
I
'00
UI
I
'40
a:
w
><
W
...I
A.
5
;:)
:::i!
DYNAMIC CHARACTERISTIC CURVES (MUX-16)
SMALL SIGNAL SWITCHING
RL = lMn. CL = 1OpF. V1 = -500mV,
V16 = +500mV
SMALL SIGNAL SWITCHING
WITH FILTERING
RL = 1Mn. CL = 500pF. Vl = -500mV,
V16 = +500mV
PAGE 11-19
RL = lMR CL = lOpF, Vl '" -70OmV.
V16'" +700mV
MUX-16/2816-CHANNELIDUAL 8-CHANNEL BI-FET ANALOG MULTIPLEXERS
DYNAMIC CHARACTERISTIC CURVES (MUX-16)
SMALL SIGNAL SWITCHING
WITH FILTERING AND
2.0pS SAMPLE TIME
RL = lMn, CL '" 5OOpF,
V,6 = +700mV
v, ..
BREAK-BEFORE-MAKE
SWITCHING
-7OOmV,
RL = 1kil. CL = 10pF,
V,. 16 = tOv
LARGE SIGNAL SWITCHING
RL" lMn, Cl = 10pF,
v, = -tOV, V,6 = +lDV
DYNAMIC CHARACTERISTIC CURVES (MUX-28)
SMALL SIGNAL SWITCHING
RL
=
'MIl, CL"'" 1OpF,
v, = -5OOmV. Va = +5OOmV
SMALL SIGNAL SWITCHING
WITH FILTERING
AND 2.5pS SAMPLE TIME
RL = 1Mn, CL = 5OOpf,
SMALL SIGNAL SWITCHING
WITH FILTERING
RL'" ,Mn, CL" 500pF, v, = -600mV, Va = +SOOmV
BREAK-BEFORE-MAKE
SWITCHING
v, .. -700mV, Va =·+7DOmV
RL'" tkO, CL" 1OpF, V" 8 = tOV
"Top Waveforms: Digital Input -5V/DIV
Bottom Waveforms: Multiplexer Output
PAGE 11-20
RL" 'MO, CL" 1DpF,
v, .. -700mV, V8'" +JOOmV
LARGE SIGNAL SWITCHING
RL" 1Mil, CL = tOpf,
v, .. -tOY, Va '" +1OV
MUX-16/28 16-CHANNELIDUAL B-CHANNEL BI-FET ANALOG MULTIPLEXERS
DYNAMIC CHARACTERISTIC CURVES (MUX-28) (apply to all grades unless otherwise noted)
SWITCH CAPACITANCES VB
ANALOG INPUT VOLTAGE (VAl
SUPPLY CURRENTS VB
TEMPERATURE (T)
,.
""-
,.
r.- ~
f-=
I-
•
MuLl.
N:::4':j
I I r--.. ........
1+
I .....
o
•
II
v+1 = +1lsv
2. v- = -15V
tI--
0
-20
0
20
60
TEMPERATURE (OC)
CDI~
hD(O~F)
•
MUX-28 A,F
ft:
4
jUxtr
-60
1
-15V
= 25°C
2
I
o
=
•
~
I-
vi i+ .l
v- =
TA
C.(OFF)
0
'DO
-10
140
-8
6
2
0
2
4
•
10
VA (VOLTS)
A.C. TEST CIRCUITS
TRANSITION TIME TEST CIRCUIT
ENABLE DELAY TIME TEST CIRCUIT
+15V
FIGURE 1.
v+
(~~~~~I
V+
+5V
EN
MUX-16
(MUX·2S)
,----------1 EN
NejDB)
S,(SlAI
NelDal
Al(Ne)
52-5'5
A3INe)
~
~~~=~~"~~r-----,
S16(SsAI
A1
,---<>---1 AD
OIOAI
AO
RL
10
-::-
l
RL
'O
M!l
":- -= ':'"
+15V
'D
+15V
FIGURE 4.
ALL CHANNELS
ARE OFF
EN (~~~:~:I 5,
---OVl,16
NeIDB)
Ne(DA) V+S:.!.~it------------,
EN
S16(SSAI
(W~~~)
A3
A3{Ne)
A2
A2
MUX·16
(MUX·2B)
A1
A1
AD
AD
,----1r-----ISaISa.,
1
RL
n"5Dn
INPUT~
CL
pF
Off ISOLATION TEST CIRCUIT
V+
LOGIC
I
( J DENOTES MUX-28 CONNECTIONS
BREAK-BEfORE-MAKE TEST CIRCUIT
+5V
D(DB}
CL
10
PF
(I DENOTES MUX·28 CONNECTIONS
FIGURE 3.
S'(SlAI
A2
A1
Mn
II
+15V
FIGURE 2.
1
kn
-:-
CL
l
1D
PF
{ I DENOTES MUX-28 CONNECTIONS
( , DENOTES MUX·28 CONNECTIONS
PAGE 11-21
Vo
MUX-18/28 18-CHANNELJDUAL a-CHANNEL BI-FET ANALOG MULTIPLEXERS
APPLICATIONS INFORMATION
CROSSTALK MEASUREMENT CIRCUIT
FIGURE 5.
+15V
CHANNEL
718 ON
V+
s:~I-------,
EN
I'I,~I (~\~~)
A3INe)
A2
AI
MUX·16
(MUX·281
AD
;--.-----1 ..1..61
( I DENOTES MUX·28 CONNECTIONS
SWITCHING TIME WAVEFORMS
SWITCH
OUTPUT
Vo
(SEE
FIGURE
11
O.8VS16I
VS1et:
SWITCH
OUTPUT
Vo
(SEE
FIGURE
Vo
These analog multiplexers employ ion-implanted JFETs In a
switch configuration designed to assure break-before-make
action. The turn-off ti me is much faster than the tu rn-on ti me
to guarantee this feature over the full operating temperature
and input voltage range. Fabricated with BI-FET processing
rather than CMOS, special handling is not necessary to prevent damage to this multiplexer. Because the digital inputs
only require a 2.0V logic "1" input level, power-consuming
pullup resistors are not required for TTL compatibility to
insure break-before-make switching as is most often the case
with CMOS multiplexers. The digital inputs utilize PNP input
transistors where input current is maximum at the logic "0"
level and drops to that of a reverse-biased diode (about 10nA)
as the input voltage is raised about .. 1.4V.
The "ON" resistance, RON of the analog switches is constant
over the wide input voltage range of -15V to +11V with
VSUPPLy=±15V. The overvoltage and supply-loss V-I characteristics shown above indicate typical performance when the
multiplexer is subjected to abnormal signals. For normal
operation, however, positive input voltages should be restricted to 11V (or 4V less than the positive supply). This
assures that the V GS of an OFF switch remains greater than
its Vp, and prevents that channel from being falsely turned
ON. When operating with negative input voltages, the gateto-channel diode will be turned on if the voltage drop acrross
an ON switch exceeds -0.6V. While this condition will cause
an error in the output, it will not damage the switch. In lab
tests, the multiplexer output has been loaded with a O.D1"F
capacitor in the circuit of Figure 1. With V, = -10V and V'6 =
+ 10V, the logic input was driven as a 1kHz rate. The positivegOing slew rate was 0.3V1"Sec which is equivalent to a normal
loss of 3mA. The negative-going slew rate was 0.7V1"Sec
which is equivalent to a "reverse" loss of 7mA. Note that
when switch one (1) if first turned ON it has a drop of -20V
across its terminals. In spite ofthatfact, the current is limited
to approximately twice its normal loss.
21
OVERVOLTAGE MEASUREMENT TEST CIRCUIT
V+
VOr---I-",
SWITCH
OUTPUT
Vo
(SEE
FIGURE
50%
r------INcI061
31
A3INe)
.,-S,6r-----,
(~~;::::~~
A2
A1
3.5V
DIDA)
AD
LOGIC INPUT
1M[l
50%
1M[l
PAGE 11-22
MUX-16/28 16-CHANNEUDUAL 8-CHANNEL BI-FET ANALOG MULTIPLEXERS
OVERVOLTAGE V-I CHARACTERISTIC
2.
SUPPLY-LOSS V-I CHARACTERISTIC
20
VL,~V
,.
,.
v-= -15V
15
,.
VN= +5V
TA = 25'C
I
~
I
-
/
-50
VN= OV
TA '" 2S'C
E=-lOV
-
,..
/
J
-s
LL.t
,..,.. 1/
•
POSITIVE VA CURVE: E" -15V
NEGATIVE VA CURVE: E = +10V
-30
-10
0
10
30
-6
-10 -8
so
-6
-4 -2
0
2
4
6
8
10
VA (VOLTS)
VA (VOLTS)
•
til
a:
w
><
W
...I
IL
5
;:)
:Ii
PAGE 11-23
SW-Ol /02, SW-03/04
PMI
QUAD SPST BIFET ANALOG SWITCHES
WITH TEMPERATURE COMPENSATED RON
AND DISABLE FUNCTION
FEATURES
teristics unavailable in other JFET or CMOS devices. A
unique circuit deSign provides a nearly constant RON over the
full operating temperatu're span. RON drift typically runs
under 300ppm/o C.
•
•
•
•
•
•
•
Low RON Y8 Temperature ................... 0.03%'OC
Low Ablolute RON ..••••..••.•.••••.•••.••••••.• 850
Low RON Variation va Analog Signal .........•..... 4%
High Speed ....•....•.................•.. . . . .. 300nS
Low Leakage Current ....•..................... 0.2nA
Over Voltage and Supply Lo.. Protected
SW-01 I. Improved Pin Compatible Device for DG201,
ADG201, LF11201
• SW-02 la Improved Pin Compatible Device for LF11202,
IH202
• SW-03 - Normally Closed, WlthDlaable. Functional
Equivalent to LF11332.
• SW-04 - Normally Open, With Disable. Functional Equivalent to LF11331.
The SW-01/02 are pin compatiblt;l with the DG201/202. while
the SW-03/04 incorporate a chip disable pin which allows
switch ganging for multiple switch systems. An Ion Implanted
FET switch inherently exhibits low RON variations vs analog
input signals. The junction FET construction also eliminates
static discharge destruction prevalent in CMOS devices.
GENERAL DESCRIPTION
Low RON sensitivity to temperature and voltage is complemented by guaranteed high-speed operation and low-leakage
currents. Address inputs may operate directly from either
CMOS or TTL logic levels and are supply voltage independent. The SW-01 through SW-04 are protected during supply
voltage power loss and against input Signal overvoltages.
The SW-Ol through SW-04 are four-channel single-pole.
single-throw analog switches which offer operating charac-
PIN CONNECTIONS
ORDERING INFORMATIONt
FUNCTION
MILITARY'
INDUSTRIAL
Dy
N.C.
N.C. (Disable)
N.O.
N.O. (Disable)
SW01BO
SW03BO
SW02BO
SW04BO
SW01FO
SW03FO
SW02FO
SW04FO
0
X
0
• Also available with MIL-STD-883B processing. To order add/883 as asuffix to
(SW-03!04 aNL V)
the part number.
t All listed part. are available with 160 hour burn-in. See Ordering Information,
Section 2.
SCHEMATIC DIAGRAM
V+
.,
IN
CONTROL LOGIC
SWITCH STATE
SW SW SW SW
INy 01
D2
03
04
LOGIC
18 PIN HERMETIC DUAL INLINE PACKAGE
Q1
THRESHOLD
CONTROL
PAGE 11-24
NA
ON
OFF
NA OFF
OF'F ON
ON OFF
NOTES: Dy = DISABLE HI
INy = INPUT 1-4
X = DON'T CARE
NA = NOT APPLICABLE
OFF
OFF
ON
SW-01/02/03/04 QUAD SPST BIFET ANALOG SWITCHES
ELECTRICAL CHARACTERISTICS at Vs = ±15V and T A = 25·C, unless otherwise noted.
SW-01-04B
PARAMETER
SYMBOL
"ON" Resistance
RoN
CONDITIONS
MIN
MAX
TYP
MAX
85
100
85
120
II
10
4
10
%
10
%
Note 1
RON Match
RL",2kll
Analog Voltage Range
+10
-10
Full Temperature Range
SW-01-04F
TYP
MIN
+10
-10
+11
-15
+11
-15
UNITS
V
10
Analog Current Range
mA
Source Current in "OFF" Condition
VS =10V, Vo= -10V
0.2
1.0
0.2
2.0
nA
Drain Current In "OFF" Condition
Vs= 10V, VO= -10V
0.2
1.0
0.2
2.0
nA
Leakage Current in "ON" Condition
VS= ±10V, Note 2
1.0
nA
"OFF" Isolation
Test Figure 2
58
58
Crosstalk
Test Figure 3
70
70
Turn-Dn-Time
Test Figure 1; Note 3
300
400
300
400
ns
Test Figure 1; Note 3
200
300
200
300
ns
Test Figure 1; Notes 3, 7
100
100
ns
7.0
7.0
pF
5.5
pF
IS(OFF)
ISO(OFF)
Turn·OII·Tlme
TOFF
Break·Belor..Make Time
Source Capacitance
CSIOFF)
Drain Capacitance
CO(OFF)
1.0
5.5
Logical "1" Input Voltage
Full Temperature Range
Logical "0" Input Vollage
Full Temperature Range
logical "1" Input Currerit
2.0 !SV 1N !S 15.0V, Note 3
1.0'
dB
V
2.0
2.0
0.8
Logical "0" Input Current
dB
3.0
1.0
0.8
V
3.0
mA
1.0
3.0
1.0
3.0
Positive Supply Current
1+
Note 5
6.3
8.0
6.3
9.0
mA
Negative Supply Current
1-
Note 5
3.2
4.5
3.2
5.5
mA
NoteS
3.0
4.0
3.0
4.5
mA
Ground Current
ELECTRICAL CHARACTERISTICS at Vs =
SW-01-04F.
±15V and -55· C ::; T A::; + 125· C for SW-01-04Band -25· C::; T A::; +85· C for
SW-01-04F
SW-01-04B
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
"ON" Resistance
MAX
MIN
TYP
120
RON Match
Note 1
RON Temperature
Coefficient - Average
VA = OV, 10 =
100~A;
Notes 3, 6
MAX
UNITS
140
II
%
10
15
10
15
0.03
0.20
0.03
0.15
Source Current in "OFF" Condition
IS{OFF)
Vs = 10V, Vo = -10V; Note 4
10
10
nA
Drain Current in "OFF" Condition
IOIOFF)
Vs = 10V, Vo = -10V; Note 4
10
10
nA
Vs = ± 10V; Note 2, 4
10
10
nA
Leakage Current in
"ON" Condition
Turn-Cn-Time
Test Figure 1; Note 3
500
600
500
600
ns
Test Figure 1; Note 3
400
500
400
500
ns
Test Figure 1; Notes 3, 7
100
IINH
2.0"V 1N ,,15.0V; Note 3
1.0
Positive Supply Current
1+
Note 5
11
12.0
mA
Negative Supply Current
1-
Note 5
6.0
7.0
mA
Turn·Off·Time
TOFF
Break·Belore·Make Time
Logical "1" Input Current
5
100
ns
1.0
mA
Logical "0" Input Current
Ground Current
____________________________
~IG~.________N_o_t_e_5_______________________________5_.0__________________6_,_0__________m_A
NOTES:
1. VA =
av. 10 = 1001l A. Specified 85 a percentage of RAVERAGE where:
RON1
4.
Parameter tested at TA = 125"C for military temperature range device.
5. Power supply and ground currents specified for switch "ON" or "OFF"
+ RON2 + RON3 + RON4
The "OFF" state gives highest power consumption.
4
2. The conditions listed specify the worst case leakage current. The
leakage currents apply equally to source or drain.
6, TC R = RON@T,-RoN@25°C
RON @25°C IT, -251
3.
7. Switching is guaranteed to be break-before-make.
Guaranteed by design.
PAGE 11-25
x 100
III
SW-01/02l03/04 QUAD SPST BIFET ANALOG SWITCHES
DICE CHARACTERISTICS (125° C TESTED DICE AVAILABLE)
SW01/03
SW02/04
DIE SIZE 0.100 X 0.098 Inch
1.
2.
3.
4.
5.
8.
7.
SWITCH (1) ADDRESS (IN1)
SWITCH (1) DRAIN (Dl)
SWITCH (1) SOURCE (51)
NEGATIVE SUPPLY
GROUND
SWITCH (4) SOURCE (54)
SWITCH (4) DRAIN (D4)
8. SWITCH (4) ADDRESS (IN4)
DIE SIZE 0.100 X 0.098 Inch
9.
10.
11.
12.
13.
14.
15.
18.
SWITCH (3) ADDRESS (IN3)
SWITCH (3) DRAIN (D3)
SWITCH (3) SOURCE (S3)
DISABLE (NO CONNECTION SW01)
POSITIVE SUPPLY
SWITCH (2) SOURCE (52)
SWITCH (2) DRAIN (D2)
SWITCH (2) ADDRESS (IN2)
1.
2.
3.
4.
5.
8.
7.
8.
SWITCH (1) ADDRESS (IN1)
SWITCH (1) DRAIN (Dl)
SWITCH (1) SOURCE (51)
NEGATIVE SUPPLY
GROUND
SWITCH (4) SOURCE (S4)
SWITCH (4) DRAIN (D4)
SWITCH (4) ADDRESS (IN4)
9.
10.
11.
12.
13.
14.
15.
18.
SWITCH (3) ADDRESS (IN3)
SWITCH (3) DRAIN (D3)
SWITCH (3) SOURCE (S3)
DISABLE (NO CONNECTION SW02)
POSITIVE SUPPLY
SWITCH (2) SOURCE (S2)
SWITCH (2) DRAIN (D2)
SWITCH (2) ADDRESS (IN2)
Refer to Section 2 for additional DICE Information.
ELECTRICAL CHARACTERISTICS at VS = ±15V and T A = 25° C, unless otherwise noted.
PARAMETER
SYMBOL CONDITIONS
"ON" Resistance
RON
-IOV"V A "IOV,I O ,,'mA
SW-01-04N
SW-01-04G
LIMIT
LIMIT
UNITS
100
120
nMAX
% MAX
RON Match
V A =OV,10",00"A
10
10
aRONvs VA
VA"IOV,l o ,,'mA
10
10
% MAX
Positive Supply Current
1+
Note 1
8.0
9.0
mAMAX
Negative Supply Current
1-
Note 1
4.5
5.5
mAMAX
Ground Current
IG
4.0
4.5
mAMAX
Analog Voltage Range
VA
±10
±10
VMIN
Logical "'" Input Voltage
V'NH
2.0
2.0
VMIN
Logical "0" Input Voltage
V'NL
0.8
0.8
V MAX
Logical "0" Input Current
"NL
0"V,N:50.8V
3.0
3.0
"A MAX
Logical "1" Input Current
"NH
2.0:5V'N",5V
1.0
'.0
"A MAX
RL " 2kO
TYPICAL ELECTRICAL CHARACTERISTICS at VS = ±15V and T A = 25° C, unless otherwise noted.
SW-01-04N
SW-01-04G
TYPICAL
TYPICAL
90
90
V A = 0,10 = 100"A
0.03
0.03
%I"C
PARAMETER
SYMBOL CONDITIONS
"ON" Resistance
RON
-55°C:5T A ",25°C
RON Temperature Coefficient
TC R
UNITS
n
Turn-On-Time
TON
RL = lk, C L = 13pF
300
300
nS
Turn-Off-Time
TOFF
RL = lk, C L = '3pF
200
200
nS
Drain Current in "OFF"
Condition
10 (OFF)
Vs= 10V, V o =-10V
0.2
0.2
nA'
"OFF" Isolation
Iso (OFF) f = 500kHz, RL = 680n
58
58
dB
Crosstalk
CT
f = 500kHz, RL = 680n
70
70
dB
NOTE:
1. Power Supply and ground current specified for switch "ON" or "OFF".
PAGE 11-26
SW-01/02/03/04 QUAD SPST BIFET ANALOG SWITCHES
ABSOLUTE MAXIMUM RATINGS (TA = 25·C unless otherwise stated).
Operating Temperature Range
SW-01-04BQ .................... -55·Cto +125·C
SW-01-04FQ . . . . . . . . . . . . . . . . . . . .. - 25 ·C to + 85 ·C
DICE Junction Temperature (T j ) ••••••• -65 0 C to + 1500 C
Storage Temperature Range. . . . . . .. -65·C to + 150·C
Power Dissipation (Q Package) . . . . . . . . . . . . . . .. 900mW
Lead Soldering Temperature ............ 300·C (60 sec)
Maximum Junction Temperature ............... 150·C
V + Supply to V - Supply. . . . . . . . . . . . . . . . . . . . . . .. 36V
TEST CIRCUITS
LOGIC 0 =
sw ON
3.5V
tr 0;;; 20n5
tfo;;; 20nl
50%
SWITCH
INPUT
SWITCH
OUTPUT
+15V
SWITCH
SWITCH
INPUT
S,
VS=-5V
0-1------0'": ..- k.......- -....-ovO
OUTPUT
This analog switch employs ion-implanted JFETs in a
switch configuration designed to assure break-before'make
action. The turn-off time is much faster than the turn-on
time to guarantee this feature over the full operating
temperature and input voltage range. Fabricated with BIFET 'processing rather than CMOS, special handling is not
necessary to prevent damage to these switches. Because
the digital inputs only require a 2.0V logic "1" input level,
power-consuming pullup resistors are not required for TTL
compatibility to insure break-before-make switching as is
most often the case with CMOS switches. The digital inputs
utilize PNP input transistors where input current is maximum at the logic "0" level and drops to that of a reversebiased diode (about 10nA) as the input voltage is raised
above =1.4V.
The "ON" resistance, RON, of the analog switches is constant over the wide input voltage range of -15V to +11V
with VSUPPLY = ± 15V. For normal operation, however,
positive input voltages should be restricted to 11V (or 4V
less than the positive supply). This assures that the VGS of
an OFF switch remains greater than its Vp, and prevents
that channel from being falsely turned ON. Individual switches
are "ON" without power applied.
RL
lku
GND
NOTE: Absolute ratings apply to both DICE and packaged parts unless
otherwise noted.
APPLICATIONS INFORMATION
TEST FIGURE 1
LOGIC
INPUT
V + Supply to Ground. . . . . . . . . . . . . . . . . . . . . . . . . .. 36V
Logic Input Voltage. . . . . . . . . . . . . . .. -4V to V + Supply
Analog Input Voltage
Continuous .... V - Supply - 25V to V + Supply + 25V
For V+ =V- =0 ........................... ±15V
Maximum Current Through Any Pin ............. 30mA
Peak Current,
(Pulsed at 1ms, 10% Duty Cycle) .............. 70mA
-15V
(REPEAT TEST FOR IN2, 1N3 AND IN4J
LOGIC 0 = SWITCH ON FOR SW-Ol. INVERT LOGIC FOR SW-02.
III
I
9
3t
I/)
I/)
w
TEST FIGURE 2
Proper switching requires the "Source" terminal to be connected to the input driving signal. If the DISABLE pin
switches are controlled by the logic select pins.
VA = 1.OVAMS
Aff- 5OIIttft:
"'"
0 q=L=_5mA) or where the switch is driven from high source im·
pedances (> 1000) should use the SW-201 (Pin Compatible
to SW-01) or the SW·202 (Pin Compatible to SW·02) high·
current Quad Switches.
Although the SW·201/SW·202 do not offer the same "ON"
resistance temperature coefficient, many other premium
characteristics are similar. In addition, the SW·201/SW·202
offer exceptionally low signal distortion over a wide signal
voltage and frequency range.
TYPICAL APPLICATIONS
DUAL SLOPE AID CONVERSION
V,N1 o---II-----CT' "'---I-~
r----...1
I
V,N. o---I-.-----<-:r'I
A..__+~
I
r - - J
I
V,N3 o---I-..;..-t----<:Y"11
A..--+--<>---.v.Jo-___--I
I
+15V
r
J
I
•
til
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()
-TEMPERATURE COMPENSATED SWITCHES
MINIMIZE GAIN ERROR DRIFT OVER
TEMPERATURE
~
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Z
<
PAGE 11-29
PMI
SW06
QUAD SPST BI-FET ANALOG SWITCH
FEATURES
• Highly Reslltant to Static Discharge Deltructlon
• Guaranteed RON Matching .•••..•...••..••••• 15% Max.
• Guaranteed Switching Speeds •••.... TON = 500nl Max.
TOFF = 400ns Max.
• Guaranteed Break-Before-Make Switching
• Low "ON" Resistance ..••..•.•••..•.••......• 800 Mail.
• Low RON Variation from Analog Input Voltage ••.•..• 5%
• High Analog Current Operation .•..........• 10mA Min.
• Low Leakage Currents at High Temperature:
TA = 125°C •..•.•......•....• 60nA Max.
TA = 85°C .•.....••....•.•... 30nA Max.
• Digital Inputs TTL/CMOS Compatible
• Improved Specifications and Pin Compatible to LF-11333/
13333
• Dual or Single Power Supply Operation
GENERAL DESCRIPTION
The SW06 is a four channel single-pole, single throw analog
switch that employs both bipolar and ion-implanted FET
devices. The SW06 FET switches are bipolar digital logic
inputs are immune to static electricity that can catastrophically destroy devices based on CMOS technology. OEM
manufacturers using CMOS devices must often establish
costly special handling procedures in production to prevent
static electric switch destruction. Ruggedness an~ reliability
are inherent in the SW06 design and construction technology. No special handling, as required with CMOS devices, is
necessary to maintain the SW06 reliability.
Increased reliability is complemented by excellent electrical
specifications. Potential error sources are reduced by minimizing "ON" resistance and controlling leakage currents at
high temperatures. The switching FET exhibits minimal RON
variation over a 20V analog signal range and with power
supply voltage changes. Operation from a single positive
power supply voltage is possible. With V+ = 36V, V- = OV, the
analog signal range will extend from ground to +32V.
PNP logic inputs are TTL and CMOS compatible to allow the
SW06 to upgrade existing designs. The logic "0" and logic "1"
input currents are at micro-ampere levels for logic levels
between 0 and 15V.
SIMPLIFIED SCHEMATIC DIAGRAM
DIGITAL
INPUT
Q1
PAGE 11-30
SW06 QUAD SPST BI-FET ANALOG SWITCH
ELECTRICAL CHARACTERISTICS at V+ = 15V, V-= -15V and
TA
PARAMETER
MIN
= 25°C, unless otherwise specified.
SW06B
SYMBOL
"ON" Resistance
RON
RON Match Between Switches
RON Match
Analog VOitage Range
VA
CONDITIONS
VS~OV.IS~1rnA
VS~±10V, IS~
Vs
~
OV, Is ~
1rnA
100~A;
1rnA~ls
Analog Current Range
IA
VS~
ARON vs Applied Voltage
ARON
-10V"V s " 10V, Is~ 1.0rnA
'S(OFF)
Vs
~
10V, Vo
~
-10V, V,N ~ 0.8V
"OFF" Condition
'O(OFF)
Vs
~
10V, Vo
~
Source Current in
'S(ON)+
"ON" Condition
Vs
~
10V, Vo
~
IOION)
Source Current in
"OFF" Condition
Drain Current in
MAX
60
65
80
80
MIN
MAX
60
65
100
100
-15
10
15
MIN
TYP
MAX
UNITS
100
100
150
150
Il
20
%
20
+11
+11
-11
±10V
SW06G
TYP
15
Note 1
1mA~ls
SW06F
TYP
-11
+10
-10
-15
12
+11
-15
V
10
rnA
15
10
20
10
20
%
0.3
2.0
0.3
2.0
0.3
10
nA
-10V, V ,N ~ 0.8V
0.3
2.0
0.3
2.0
0.3
10
nA
-10V, V ,N ~ 2.0V
0.3
2.0
0.3
2.0
0.3
10
nA
Logical "1" Input Voltage
V ,NH
Full Temperature Range
Logical "0" Input Voltage
V 1NL
Full Temperature Range
0.8
0.8
0.8
V
Logical "1" Input Current
IINH
V ,N ~ 2.0V to 15.0V, Note 4
0.1
0.1
0.1
~A
Logical "0" Input Current
I'NL
V ,N
2.0
~0.8V
See Switching Time
Turn-On-Time
tON
Test Circuit; Note 2
See Switching Time
Turn-Off-Time
tOFF
Test Circuit; Note 2
2.0
2.0
V
1.5
5.0
1.5
5.0
1.5
10.0
~A
340
500
340
600
340
700
ns
200
400
200
400
200
500
ns
Break-Before-Make Time
tON-tOFF
Note 2, 3
140
ns
Source Capacitance
CS(OFF}
Vs ~ OV, V ,N ~ 0.8V
7.0
7.0
7.0
pF
Drain Capacitance
CO(OFF}
Vs ~ OV, V ,N ~ 0.8V
50
140
50
140
50
II
'"'i'
5.5
5.5
5.5
pF
Vs~VO~OV
15
15
15
pF
3t
CI)
ISOIOFF}
Vs ~ 1VRMS' RL ~ 6801l,
C L ~ 7pF, 1 ~ 500kHz
58
58
58
dB
CI)
CT
Vs ~ 1V RMS' RL ~ 6800,
C L ~ 7pF, 1 ~ 500kHz
Positive Supply Current
1+
Two Channels "ON"
Two Channels "OFF"
4.0
9.0
4.0
10.5
4.0
12.0
rnA
CI)
Negative Supply Current
1-
Two Channels "ON"
Two Channels "OFF"
1.0
5.0
1.0
6.0
1.0
6.5
rnA
...I
Positive Supply Current
1+
All Channels "OFF", VIN ~ O.SV
5.0
9.0
5.0
10.5
6.0
12.0
rnA
Negative Supply Current
1-
All Channels "OFF", V ,N
4.0
6.0
4.0
7.0
4.0
8.0
rnA
Ground Current
IG
All Channels "ON" or "OFF"
3.0
4.0
3.0
4.0
3.0
6.0
mA
Channel "ON" Capacitance
"OFF" Isolation
Crosstalk
W
70
70
70
dB
RAVERAGE
RON1 + RON2 + RON3 + RON'
4
2. Guaranteed by design.
I-
j
"
0
~
0.8V
NOTES:
1. Vs ~ OV, Is ~ 100~A. Specilied as a percentage 01 RAVERAGE where:
%
0
3. Switch is guaranteed to provide break~before~make operation.
4. Current tested at V 1N = 2.0V. This is worst case condition.
5. The ground pin (GND) must be ~4V above the V- pin to include -4V logic
levels.
PAGE 11-31
CI:
Z
CI:
SWOI QUAD SPST BI-FET ANALOG SWITCH
ABSOLUTE MAXIMUM RATINGS (Note 2)
Operating Temperature Range
SW06BO .......................... -5S·C to +12S·C
SW06FO ........................... -2S·C to +8S·C
SW06GP ..............•.............. O·C to +70·C
Storage Temperature Range .••••.••.•. -6S· C to +1S0· C
Power Dissipation (Note 1) •....•••••••.•.•....•. 900mW
Lead Soldering Temperature (60 sec) .••..•..••.•• 300· C
Maximt:lm Junction Temperature .••....••.•..•••• 1S0·C
V+ Supply to V- Supply. . . . . . . . . . . • . . . . . . . . . . . • . • •. 36V
V+ Supply to Ground .............................. 36V
Logic Input Voltage (Note S) •....•..•.. -4V to V+ Supply
Analog Input Voltage' Range
Continuous .....••.••... V- Supply to V+ Supply +20V
1% Duty Cycle and Driving
all 4 Inputs with
SOO!,sec pulse .....• V- Supply -1SV to V+ Supply +20V
Maximum Current Through Any Pin ............... 30mA
NOTES:
1.
Derated 12mW/oC above 75°C.
2. Absolute ratings apply to both DICE and packaged parts unless otherwise
noted.
ELECTRICAL CHARACTERISTICS at V+ = 1SV, V-=-1SV, -SS·C:5 TA :5+12b·C for SW06BO, -2S·C:5 TA :5+8S·C for
SW06FO and O· C :5 TA :5 70· C for SW06GP.
SW06B
PARAMETER
SW06F
MAX
75
80
110
110
MIN
SW06G
CONDITIONS
RON
Vs = OV.lo = 1.0mA
Vs = ±10V.l o = 1.0mA
RON Match Between Switches
RON Match
Vs = OV.ls = 100pA; Note 1
Analog Voltage Range
VA
15= 1.0mA
Is = 1.0mA
Analog Current Range
IA
Vs = ±10.0V
12
..I.RON With Applied Voltage
..I.RON
-10V" Vs" +10V. Is = 100pA
30
Source Current in
"OFF" Condition
'SrOFF)
Vs= 10V. V o =-10V, V IN =0.8V
T A = Max. Operating Temp.
60
30
60
nA
Drain Current in
"OFF" Condition
'OIOFFI
Vs= 10V, V o =-10V, V IN =0.8V
T A = Max. Operating Temp.
60
30
60
nA
60
30
60
nA
10
10
15
pA
1000
ns
500
ns
"ON" Resistance
MIN
TYP
SYMBOL
20
+11
-11
+11
-11
-15
TYP
MAX
75
80
125
125
6
25
TYP
MAX
UNITS
75
80
175
175
n
10
%
+11
-15
V
11
11
mA
30
30
+10
-10
-15
Leakage Current in
"ON" Condition
'SIO N1+
JOlON)
Vs = Vo = ±10V, VIN = 2.0V
T A = Max. Operating Temp.
Logical "1" Input Current
IINH
VIN = 2.0V to 15.0V, Note 4
Logical "0" Input Current
IINL
VIN = 0.8V
Turn-On-Time
tON
See Switching Time
Test Circuit; Note 2
440
900
500
900
Turn-Off-Time
tOFF
See Switching Time
Test Circuit; Note 2
300
500
330
500
Break-Bafore-Make Time
MIN
%
I'A
70
tON-tOFF
70
-
ns
50
1+
Two Channels "ON"
Two Channels "OFF"
13.5
14.0
15.8
mA
1-
Two Channels "ON"
Two Channels "OFF"
8.5
11.0
14.5
mA
Positive Supply Current
1+
All Channels "OFF", VIN = 0.8V
13.5
14.0
18.0
mA
Negative Supply Current
1-
All Channels "OFF", VIN = 0.8V
8.5
11.0
14.5
mA
Ground Current
IG
All Channels "ON" or "OFF"
6.0
7.8
10.0
mA
Positi~e
Supply Current
Negative Supply Current
NOTES:
1. Vs = OV, Is = 100~A. Specified as a percentage of RAVERAGE where:
RAVERAGE
2.
RON! + RON2 + RON3 + RON4
4
Guaranteed by deSign.
3. Switch is guaranteed to provide break-before-make operation.
4. Current tested at V1N
= 2.0V. This is worst case condition.
5. The ground IGNDl pin must be? 4V above the V- pin to include -4V
logic levels.
PAGE 11-32
SW06 QUAD SPST BI-FET ANALOG SWITCH
DICE CHARACTERISTICS
1. IN (1)
2.0(1)
3. S (1)
4. GND
5. V6. S(2)
7.0(2)
S. IN (2)
9. IN (3)
10. 0 (3)
11. S(3)
12. V+
13. DISABLE
14. S (4)
15. 0 (4)
16. IN (4)
DIE SIZE 0.100 X 0.096 Inch
Refer to Section 2 for additional DICE Information.
ELECTRICAL CHARACTERISTICS V+ = 15V. V- = -15V and T A = 25°C. unless otherwise noted.
SW06N
MIN
PARAMETER
SYMBOL
CONDITIONS
"ON" Resistance
RON
-10V S VAS 10V.lsS lmA
RON Mismatch
RON Match
V A = OV. Is S 100,,",
TYP
5
5
SW06G
MAX
MIN
TYP
MAX
UNITS
80
100
0
15
20
%
•
<0
Cj'
~
II)
ARONVs VA
ARON
-10VSVAS 10V.lsS lmA
15
20
%
Positive Supply Current
1+
Note 1
9.0
10.5
mA
II)
Negative Supply Current
1-
Notel
6.0
7.0
mA
0
Ground Current
IG
4.0
4.0
mA
Analog Voltage Range
i
VA
Logic "1" Input Voltage
V'NH
Logic "0" Input Voltage
V'NL
Logic "0" Input Current
I'NL
OV S V'N S O.BV
Logic "1" Input Current
'INH
2.0V S V'N S 15V, Note 2
Analog Current Range
IA
V s =±10V
R L ,,2kO
±10.0
±10.0
V
2.0
2.0
V
0.8
0.8
V
5.0
5.0
"A
0.1
0.1
10
"A
mA
TYPICAL ELECTRICAL CHARACTERISTICS V+ = 15V. V-=-15V. and TA = 25°C. unless otherwise noted.
SW06G
SW06N
PARAMETER
SYMBOL
"ON" Resistance
RON
Turn-On-Time
Tum-Olf-Time
CONDITIONS
MIN
-10VSV A S10V,
TYP
MAX
MIN
TYP
MAX
UNITS
60
60
0
TON
340
340
ns
TOFF
200
200
ns
0.3
0.3
nA
Drain Current in
Is$.1mA
'OIOFFI
Vs = 10V, Vo = -10V
"OFF" Isolation
Iso (OFF)
f = 500kHz, RL = 6600
58
58
dB
Cros.talk
CT
f
= 500kHz, RL = 6800
70
70
dB
"OFF" Condition
NOTES:
1. Power supply and ground current specified for switch "ON" or "OFF".
2. Current tested at V 1N = 2.0V This is worst case condition.
3. The ground pin (GND) must be ,,4V above the V- pin to include -4V logic
levels.
PAGE 11-33
W
z:
lII)
"
0
-'
C
Z
C
SWOS QUAD SPST BI-FET ANALOG SWITCH
PIN CONNECTIONS
ORDERING INFORMATIONt
PACKAGE IS
1SPIN DIP
ORDER
PART
NUMBER
OPERATING
TEMPERATURE
RANGE
HERMETIC
HERMETIC
EPOXY
SW06BO"
SW06FO
SW06GP
MIL
INO
COM
"Also available with MIL-STD-883B processing. To order add/883 as asulflx to
the part number.
t All listed parts are available with 160 hour burn-in. See Ordering Information,
Section 2.
SWITCH STATE
DISABLE
INPUT
LOGIC
INPUT
CHANNELS
1&2
CHANNELS
3&4
0
1
1
X
0
OFF
OFF
ON
OFF
ON
OI7F
16-PIN DUAL-IN-LiNE PACKAGE
(Q or P Package)
TYPICAL PERFORMANCE CHARACTERISTICS
"ON" RESISTANCE VI.
ANALOG VOLTAGE (V s)
v+ = +15V
~~: 2~"'CV --+---t----I
Is"'lmA
!
360
in 60
F::::r~+;o;;;;;;;;;;4:::::=1
56
f----+----+----t------j
50 1 _ - _ 4 - - _ + - - _ t _ - - _ j
~1_-_4--_+--_t_--_j
~~--~----~----~--~
-10
-5
10
ANALOG INPUT VOLTAGE -VA (V)
200
~
" ---
-,.
'50
75
200
TOFF
"-
-5
0
5
ANALOG INPUT VOLTAGE (V)
10
~(.q_1~/'lz,
~/r
'"
"
.........
40
-26
0
25
50
75
TEMPERATURE (GC)
-25
0
25
50
15
100
126
LEAKAGE CURRENT
VI. TEMPERATURE
~~"(ot
,/
40
-56
f..- r-
100nA . - - - , - . . . . , . . . - , . . - - - , . - , - - . . , -....
~
~
V
..
-55
V
V
fA" 26°C
. . .V
~60
TOFF
TEMPERATURE PC}
'00
in
•
V V
V
- -
V .....
'00
./
70
50
;...., TON
300
Y
-'
RL = 1kO
CL = lOpF
400
CROSSTALK AND "OFF"
ISOLATION VI. FREQUENCY
RON VI. TEMPERATURE
~
--
Vs" ±15V
CL" 10pF
300
250
.00
VS= ±1SV
RL = 1kO
~
oo~---+----~----+-----I
e
SWITCHING TIME
VI. TEMPERATURE
400
75
70
~
SWITCHING TIME
VI. ANALOG VOLTAGE
100
125
'OOk
......
'M
FREQUENCV (Hz)
PAGE 11-34
'OM
=--==..
TOpA-55'--_-'25'--'--..
:---:':7.:--...
'00-....
'2.
TEMPERATURE (ge)
SW06 QUAD SPST BI-FET ANALOG SWITCH
TYPICAL PERFRMANCE CHARACTERISTICS
"ON" RESISTANCE
vs POWER SUPPLY VOLTAGE
16
::: TA! 2SOC +_--1--+-+-+------1
1001---1--+-+-+--+---1----1
Cs
'100
8O~~=*==F=~=*==F=~
r-- t--
~-+-~-1_-+_-~-+--i
-
Cs (OFF)
70~'
~~-+-~-1_-+_-~-+--i
~~-+-~-1_-+_-~-+--i
..,../
.....V
±15
±16
±17
±18
>
TA" 2SoC
-10 -8 -6 -4 -2
±19
0
2
~A "'250~
I
Vs = ~15V
CURRENT INTO
II
SOURCE
/
4
6
8
/'
200
100
i-""
/'
o 1
10
ANALOG INPUT VOLTAGE -VA (VI
V
V
~ 300
0
101--+-+-+-+_-1-~--i
±14
SWITCH CURRENT
vs. VOLTAGE
~ 400
"
I
I
201--+-+-+-+_-1-~--i
±13
1000
.s 900
'"f! 800
~ 700
il 600
0
a:
:;l 500
;;
12
10
801-----1--+-+-+--+-----1--1
70 I-----I--+-+-+--+_ RON -
±12
1200
(ON)
14
OOI-~-+--+_--1---r--+_---l
..
SWITCH CAPACITANCE
vs. ANALOG VOLTAGE
2
3
4
5
6
7
8
9
10
11 12
SWITCH CURRENT (mAl
POWER SUPPLY VOLTAGE (VI
T oN-'T OFF SWITCHING RESPONSE
--
ov
U)
'i'
~
UI
UI
TOP TRACE: LOGIC INPUT (5V/DIVI
W
BOTTOM TRACE: SWITCH OUTPUT (1V/DIV)
:J:
U
l-
iUI
CI
o....
c
z
c
OFF ISOLATION TEST CIRCUIT
VA=1.0VRMS
ATf= 500kHz
5
D
Your
~VA
son
+--~
AL = 680.11
-=
CL = 7pF
'----
"OFF" ISOLATION = 20 LOG
[~J
PAGE 11-35
,\7
SW08 QUAD SPST BI-FET ANALOG SWITCH
CROSSTALK TEST CIRCUIT
VA-1.OVRMS
ATf"'SOOkHz
81
~VA
01
~
VD1
son
RL .. 6800
=:CL"'OF
D2
SO
\!
VD2
LOG~
U
RL '" 680n
tCL"OF
CROSSTALK = 20
-
~
SWITCHING TIME TEST CIRCUIT
LOGIC
INPUT
+16V
RL
~
VO=VS~
q
:~~iH 81 VREF
=~~
VS" ±1OV o-I-------
I
GAIN,
,
,~
15
......
9
....
•
to.
8
.....
__ J
GAIN2
10
I
I
I
,
__ J
,,
......
16
9
•
7
I
I
GAIN4
-
.....
,I
-I>to.
8
.....
-
_I
_
,,
J
v-
V-
IX
15
15
-15V
-15V
lOX
10
100X
7
1000X
2kn
-=
4-CHANNEL SAMPLE HOLD AMPLIFIER
SW06
VI
+15V
V2
14
15
VJ
11
10
V4
VOUT
IH
PAGE 11-37
99.9kn
g,9kn
1SkU
15
J
11
GA1N 3
2
...... ---'
......
1
14
..... ---II
.....
OND
= l000,F
100kfl
-=
100kll
-=
•
SW06 QUAD SPST BI-FET ANALOG SWITCH
OPERATION FROM SINGLE POSITIVE POWER SUPPLY
V+rOV
13
V+
1/4SWOS
o ~ VANALOG ;;;.. V+ -4V
3
I
I
I
r------,
1
I TTL OR CMOS I
IL
GATE
______
Your
2
I
J
-f'>.J
.....
V-
GNO
f-J4
PROGRAMMABLE VOLTAGE SUPPLY
lN4002
IA
I~
VIN = 24V
TL317T
V,N
r""
AOJ
1.87kn
86&l
Your
Vo
{.oP'
1N4002
:z;;;:
15kn
5.76kfZ
RA
24an
:. t
3.24kn
,3
11
6
14
12
r
r
1O. ,
SWOO
---,
---,
~l
H
2
1
7
V1
---,
---,
•
V2
*SETS
MAXIMUM
OUTPUT
.
~l
~l.
,.
, •
10
V4
V3
(5.0V SELECT, (7.5V SELECT) (12.0V SELECT) (1S.0V SELECT)
Vo
R,
5.0
7.5
12.0
15.0
B66ll
1.87 kll
5.76 kll
15.0 kll
SWITCH
RON =
NOTE
Vo =1.25
60n
Rs ; 3.24 kll
PAGE 11-38
(
Rs II R; )
1+~
PMI
SW-201/SW-202
QUAD SPST BI-FET ANALOG SWITCHES
®
FEATURES
SW-201
• Normally "ON" for Logic 0 Input
• Improved Performance and Pin Compatible With DG-201,
LF11201113201, H1201, and IH201.
SW-202
• Normally "OFF" For Logic 0 tnput
• Improved Performance and Pin Compatible With
LF11202/12202/13202 and IH202
Both SW-201 and SW-202
• Highly Resistant to Static Discharge Destruction .
• Guaranteed Break-Before-Make Switching (tOFF < tON)
• Low "ON" Resistance ...................... 80n Max.
• Guaranteed RON Matching ................. 15% Max.
• Low RON Variation from Analog Input Voltage ..... 5%
• High Analog Current Operation ...•....••.• 10mA Min.
• Low Leakage Currents at High Temperatures:
TA = 125°C ................. 60nA Max.
TA = 85°C ................. 30nA Max.
• Guaranteed Switching Speeds:
tON = 500ns Max.
tOFF = 400ns Max.
• Digital Inputs are TTL/CMOS Compatible and are Low
Current PNP Transistors.
input is a zero. The SW-201 and SW-202 are otherwise
identical.
The judicious combination of bipolar and FET devices in a
single monolithic IC results in a product with performance
characteristics and ruggedness that are superior to those of a
similar circuit fabricated using CMOS technology. No
special handling requirements are necessary to maintain the
SW-201/SW-202 reliability.
Increased reliability is complemented by excellent electrical
specifications. Potential error sources are reduced by minimizing "ON" resistance and controlling leakage currents at
high temperatures. The switching FET exhibits minimal RON
variation over a 20V analog signal range and with power
supply voltage changes. Operation from a single positive
power supply voltage is possible. With V+ = 36V, V-= OV, the
analog signal range will extend from ground to +32V.
The PNP logic inputs are TTL and CMOS compatible and
require input currents at the micro-ampre level for logic levels between OV and 15V.
II
PIN CONNECTIONS
GENERAL DESCRIPTION
The SW-201 and SW-202 each consist of four independent,
single-pole, single-throw (SPST) analog switches, which
may be independently digitally controlled. Each SW-201
switch is normally closed (NC), whereas each SW-202 is
normally open (NO) when the corresponding digital control
16-PIN DUAL-IN-LINE PACKAGE
(Q or P Package)
N
~
~
~
I/)
ORDERING INFORMATIONt
DIP
PACKAGE
SWITCH CONFIGURATION
NC
NO
16 PIN HERMETIC
16 PIN HERMETIC
16 PIN EPOXY
SW201BO·
SW201FO
SW201GP
SW202BO'
SW202FO
SW202GP
OPERATING
TEMPERATURE
RANGE
MIL
IND
COM
• Also available with MIL-STD-8838 processing. To order add 1883 as a suffix to
the part number.
tAil listed parts are available with 160 hour burn-in. See Ordering Information.
SIMPLIFIED SCHEMATIC DIAGRAM (ONE SWITCH)
DIGITAL
INPUT
Q1
Manufactured under the following patent: 4,228,367
PAGE 11-38
I/)
w
::t:
(,)
SW-20.1
CONTROL LOGIC
LOGIC
SWITCH
ON
OFF
SW-202
CONTROL LOGIC
LOGIC
SWITCH
OFF
ON
I-
~
CJ
o
«
z
«
...I
SW-201/SW-202 QUAD SPST BI-FET ANALOG SWITCHES
ABSOLUTE MAXIMUM RATINGS (Note 1)
V+ Supply to Ground •....••......•...•••..••.••••• 36V
Logic Input Voltage •••....•..•...•.•.. -4V to V+ Supply
Analog Input Voltage Range
Continuous •.••.••....• V- Supply to V+ Supply +20V
1% Duty Cycle and Driving
aI/ 4 Inputs with
SOOl'5eC pulse ..... V- Supply -1SV to V+ Supply +20V
Maximum Current Through Any Pin .•••.•.....•..• 30mA
Operating Temperature Range
SW-201BQ, SW-202BQ •..•...•.••..• -SS'Cto+12S'C
SW-201 FQ, SW-202FQ •.••.•..•...... -2S' C to +85' C
SW-201GP, SW-202GP .....••......•...• O'C to +70'C
DICE Junction Temperature (Tj ) ••••••• -65'C to +1S0'C
Storage Temperature Range •..••..•.•. -6S'C to +1S0'C
Power DissIpation (Note 2) .........•....••.•..•. 900mW
Lead Soldering Temperature (60 sec) •............ 3OO'C
Maximum Junction Temperature ...•••...••.....•. 1S0'C
V+ Supply to V- Supply. .•.. . .. .. .. .•.. .. •. .. . .. . .• 36V
NOTES:
1. Absolule rallngsapplylo bolh DICE and packaged parts, unlessolherwlse
nOled.
2. Deraled 12mW/' C ebove 75' C.
ELECTRICAL CHARACTERISTICS at V± = ± 1SV and T A = 2S' C, unless otherwise noted.
SW-201F
SW-202F
SW-201B
SW-202B
PARAMETER
SYMBOL
CONDITIONS
"ON" Resllllnce
VA =OV,I S =lmA
VA =±10V,ls=lmA
RON Match Between
VA = OV. Ie = 100"A;
Switches
MIN
TVP
MAX
60
60
80
65
15
Note 1
Analog VOltage Range
IS=1.0mA
Is=1.0mA
+10
-10
+11
-15
10
15
Analog Currenl Range
VS =±10V
4RON VI Applied VOltage
-10VSV S S 10, Is= 1.0mA
Source Current In
Vs= 10V, VD =-10V,
V,N = 2.0V
Vs= 10V, VD=~10V,
V,N =2.0V
"OFF" Condition
Drain Current In
"OFF" Condition
Leakage Current in
"ON" Condition
Logical "l"lnpul Voltaga
VINH
Full Temperature Range
Loglcel "0" Inpul Voltage
Full Temperature Range
Loglcal"l"lnpul Current
Y,N = 2V to 15V; Note 4
tOFF
Ses Swilching Time
Test Circuit; Note 2
Note. 2, 3
Break-Befora-Make Time
MAX
60
65
100
100
5
20
+11
-15
50
MIN
TVP
MAX
UNITS
100
100
150
150
o
20
+10
-10
12
+11
-15
v
10
mA
15
10
20
0.3
2.0
0.3
2.0
10
nA
0.3
2.0
0.3
2.0
10
nA
0.3
2.0
0.3
2.0
10
nA
0.8
v
v
2.0
10
20
2.0
0.8
0.1
TaBt Circuit; Note 2
SW-201G
SW-202G
TVP
0.8
See Switching Time
Turn-Olf-Time
+10
-10
2.0
Logical "0" Input Current
Turn-On-Time
MIN
0.1
0.1
1.5
5.0
1.5
5.0
1.5
10.0
340
500
340
800
340
700
200
400
200
400
200
500
50
140
140
50
ns
ns
140
nl
Source CapaCitance
CS(OFF)
7.0
7.0
7.0
pF
Dreln Capacllanos
CD (OFF)
5.5
5.5
5.5
pF
15.0
15.0
15.0
pF
Channel "ON" Capacitance
VS= VD = OV
"OFF" Isolation
Vs = WRMS, RL = 8800.
CL = 7pF, ,= 500kHz
58
58
58
dB
Vs= WRMS, RL =8800,
CL = 7pF.1 = 500kHz
70
70
70
dB
ISO (OFF)
Crosstalk
POlltlve Supply Current
1=
All Chennels "ON", Y,N = 0
4.0
9.0
4.0
10.5
4.0
12.0
mA
Negallve Supply Current
1-
All Channels "ON", Y,N = 0
1.0
5.0
1.0
8.0
1.0
8.5
mA
POlltlve Supply Current
1+
All Chennels "OFF".
V,N =2.0
5.0
9.0
5.0
10.5
8.0
12.0
mA
Negative Supply Current
1-
All Channels "OFF",
V,N =2.0
4.0
6.0
4.0
7.0
4.0
8.0
mA
All Channels. "ON"
or "OFF"
3.0
4.0
3.0
4.0
3.0
8.0
mA
Ground Current
NOTES:
1. VA OV, ID
=
=100,.A. Specified as a perosntage 01 RAVERAGE where:
RONl + RON2 + RON. + RON.
RAVERAGE=
4
2. Guaranleed by deSign.
3. Switch Is guarenloed to provide break-belora-make operation.
4. Currenllesled at V ,N = 2.0V. This Is worsl case condition.
PAGE 11-40
SW-201/SW-202 QUAD SPST BI-FET ANALOG SWITCHES
ELECTRICAL CHARACTERISTICS at Vs= ±15V; -55°C :5T A :5+125°C for SW-201/202-BO;
SW-201/202-BO; O· C :5 T A:5 70· C for SW-201/202-GP.
SW-201B
SW-202B
PARAMETER
SYMBOL
"ON" Resistance
RON
RON Match Between
Switches
RON Match
Analog Voltage Range
VA
Analog Current Range
IA
ARoN With Applied Voltage
ARoN
CONDITIONS
TYP
MAX
VA~OV.lo~lrnA
75
VA~±10V.lo~lrnA
80
110
110
6
20
VA ~ OV, 10 ~
MIN
SW-201F
SW-202F
100~A,
Note 1
Is~I.0rnA
Is~
+10
-10
1.0rnA
Vs~±10.0V
-10V" Vs " +10,
Is~l00rnA
MIN
MAX
75
125
125
MIN
+11
-15
TYP
MAX
175
175
25
+10
-10
+11
-15
for
SW-201G
SW-202G
TYP
80
-25°C:5 T A :5 +85°C
10
+10
-10
UNITS
0
%
+11
-15
V
12
11
11
rnA
30
30
30
%
Vs ~ 10V, Vo ~ -10V,
Source Current in
V'N~2.0V
IS (OFF)
"OFF" Condition
60
30
60
nA
80
30
80
nA
2.0
10
nA
5.0
~A
15
~A
T A = Max. Operating Temp.
Vs ~ 10V, Vo ~ -10V,
Drain Current In
"OFF" Condition
V'N~2.0V
IO(OFF)
TA = Max. Operating Temp.
Leakage Current in
"ON" Condition
IS(ON)+
Vs~Vo~±10V, V'N~0.8
10 (ON)
T A = Max. Operating Temp.
0.3
2.0
0.3
5.0
5.0
Logical "1" Input Current
IINH
V'N ~ 2.0V to 15.0V, Not. 4
Logical "0" Input Current
IINL
V'N~0.8
4.0
10
4.0
10
Turn~On·Tlme
tON
See Test Circuit. Note 2
440
900
500
BOO
1000
ns
Turn-Off-Time
tOFF
See Test Circuit, Note 2
300
500
330
500
500
ns
5.0
Test Circuit; Note 2
70
70
•
N
C
N
Break-Before-Make Time
·ON-tOFF
Notes 2, 3
Positive Supply Current
I~
All Channels "ON", VIN = 0
13.5
14.0
15.8
rnA
Negative Supply Current
1-
All Channels "ON", VIN = 0
8.5
11.0
14.5
rnA
i
Positive Supply Current
1+
13.5
14.0
18
rnA
III
Negative Supply Current
1-
8.5
11.0
14.5
rnA
Ground Current
All Channels "OFF",
V'N~2.0
V'N~2.0
NOTES:
1. VA ~ OV, 10 = lOOIOA. Specilied as a percentage 01 RAVERAGE where,
+ RON2 + RONa +
RAVERAGE"'"
......
;i:
1&1
:z:
U
All Channelse "ON"
or "OFF"
RON1
ns
III
All Channels "OFF",
la
50
RON4
8.0
7.8
10.0
2. Guaranteed by design.
3. Switch is guaranteed to provide break-before-make operation.
4. Current tested at V 1N = 2.0V. This is worst case condition.
4
PAGE 11-41
rnA
....
iIII
"
0
...I
0(
Z
0(
SW-201/SW-202 QUAD SPST BI·FET ANALOG SWITCHES
DICE CHARACTERISTICS
1.
2.
3.
4.
5.
6.
7.
SWITCH 1 ADDRESS (IN1)
SWITCH 1 DRAIN (D1)
SWITCH 1 SOURCE (S1)
NEGATIVE SUPPLY VGROUND (GND)
SWITCH 4 SOURCE (S4)
SWITCH 4 DRAIN (D4)
DIE SIZE 0.100 X 0.096 Inch
••
9.
10.
11.
13.
14.
15.
16.
SWITCH 4 ADDRESS (IN4)
SWITCH 3 ADDRESS (IN3)
SWITCH 3 DRAIN (D3)
SWITCH 3 SOURCE (S3)
POSITIVE SUPPLY V+
SWITCH 2 SOURCE (S2)
SWITCH 2 DRAIN (D2)
SWITCH 2 ADDRESS (IN2)
Refer to Section 2 for additional DICE Information.
ELECTRICAL CHARACTERISTICS V+ = 15V, V-=-15V and TA = 25°C, unless otherwise noted.
SW-201N
SW-202N
SW-201G
SW-202G
LIMIT
LIMIT
UNITS
80
100
nMAX
V A = OV, Is"IOOI'A
15
20
% MAX
-IOV"VA"IOV.ls"lmA
15
20
% MAX
Note I
9.0
10.5
mAMAX
Note I
6.0
7.0
mAMAX
4.0
4.0
mAMAX
±IO.O
±IO.O
VMIN
V 1NH
2.0
2.0
VMIN
V1NL
0.8
0.8
V MAX
I'AMAX
PARAMETER
SYMBOL
CONDITIONS
"ON" Resistance
RON
-10V"VA " 10V, Is"lmA
RON Mismatch
RON Match
aRONvs VA
aR ON
Positive Supply
1+
Negative Supply Current
1-
Ground Current
IG
Analog Voltage Range
VA
Lagle "I" Input Voltage
Logic "0" Input Voltage
Rl 2:2kn
Logic "0" Input Current
IINL
OV" V'N" 0.8V
5.0
5.0
logic "1" Input Current
I'NH
2.0V" V'N ,,15V, Note 2
0.1
0.1
~MAX
Analog Current Range
IA
Vs=±IOV
10
7
mAMIN
TYPICAL ELECTRICAL CHARACTERISTICS V+ = 15V, V- = -15V and
CONDITIONS
TA =
25°C, unless otherwise noted.
SW-201N
SW-202N
SW-201G
SW-202G
PARAMETER
SYMBOL
TYP
TYP
"ON" Resistance
RON
60
60
n
Turn-On-Time
tON
340
340
ns
Turn-Olf-Time
ns
UNITS
tOFF
200
200
Drain Current in
"OFF" Condition
10 (OFF,
Vs= 10V, Vo=-IOV
0.3
0.3
nA
"OFF" Isolation
Iso (OFF)
f = 500kHz, Rl = 660n
58
58
dB
Crosstalk
CT
f = 500kHz, Rl = 660n
70
70
dB
NOTES:
1. Power supply and ground current specified for switch "ON" or "OFF".
2. Current tested at V1N = 2.0V. This is worst case condition.
3. The ground (GND) pin must be 2: 4V above V- pin to include -4V logic
levels.
PAGE 11-42
SW-201/SW-202 QUAD SPST BI-FET ANALOG SWITCHES
TYPICAL PERFORMANCE CURVES
"ON" RESISTANCE VS.
ANALOG VOLTAGE (VA)
SWITCHING TIME VS.
TEMPERATURE
...
nr-----~-----r----_.----_,
RL ~ 1k!!
CL =tOpF
.5~----+-----~-----t----~
I
}
I--
f==::::r=-+-=~:::::::_=l
80
V
·
55~----+-Y-.-,.-,.-V~-----+----~
50 r-------
V
V V
3DO
l -I--
~~: ;~!~+-----+-----t
~
,.....
'00
.::k:
v,: !-15Y
7.~----+-----~-----t----~
35'
L
-----_-1,------'-------:------:.10
4~,L.
25.
55
25
,
/
•
V
,
/
15.
'25
75
-10
---
r--
To~"
ANALOG INPUT VOLTAGE IV)
CROSSTALK AND "OFF"
ISOLATION VS. FREQUENCY
V
V
I
LEAKAGE CURRENT VS.
TEMPERATURE
1/
-55
~
..~
7
~
25
50
TEMPERATURE
7S
100
8
It
o
,
125
.~~~
o
•
•
........
IJ 8o~~===i===F==~==*==·=oF·==~
~r-~---+--+--+---+---r-~
2Or-~---+--+--+---+---r-~
:,~.~±~13~~±'~'--±~,~.~±~,.~~±'~7--±~'~.~±~18
POWER SUPPLY VOLTAGE IV)
1"-
'M
tOOk
10PA-5_~,~---=..;--7--~25;--'=.:--:7:-.--,:!.:-.-7.'26
10M
FFiEQUENCY (Hz)
"ON" RESISTANCE VS.
POWER SUPPLY VOLTAGE
.r-~---t--+--+---+---r-~
r-.....
1'0",
(~C)
I
I
T.:25"C
:'<",
5
~
-25
90
tl
V
III
I
U
~
V
•
,•
'20
To.
'00
0
50
50
TEMPERATURE C·C)
RON VS. TEMPERATURE
r-- t:------
~
20.
ANALOG INPUT VOLTAGE - VA (V)
RL = lk!l
CL =10pF-
V
V
4'~----+------~-----+-----4
•
Vs -"'5V
""-
300
'00
Is=1mA
SWITCHING TIME VS.
ANALOG VOLTAGE
TEMPERATURE (OCI
SWITCH CAPACITANCE VS,
ANALOG VOLTAGE
SWITCH CURRENT VS.
VOLTAGE
'20'
I
'00' _ !:::~~~ ..1
. ..
~
1
CURRENT INTO SOURCE
~
V
V
'DO
CslONI
TA'25'!:
12
i
~
.00
I
14
g
I
18
,1
,1
V
!Iz
10
~
u
CslOfFl
§
Col~
t"::
--
"..
,/
.....
/
.00
,/
o 1/
•
o
-10
SWITCH CURRENT (mAl
PAGE 11-43
-8
-6
-4
-2
ANALOG INPUT VOLTAGE -VA (V)
. ,.
SW-201ISW-202 QUAD SPST' BI-FET ANALOG SWITCHES
TYPICAL PERFORMANCE CURVES
SW·201
towtOFF SWITCHING RESPONSE
SW·202
towtOFF SWITCHING RESPONSE
OV
OV
TOP TRACE: LOGIC INPUT (Sy/DIV)
BOTTOM TRACE: SWITCH OUTPUT (1V/DIV)
OFF ISOLATION TEST CIRCUIT
SWITCHING TIME TEST CIRCUIT
+15V
YO
SWITCH
INPUT
Vs
-SV
~
A,
Vs RL + roS(ON)
SWITCH
OUTPUT
Y>
s,
0,
0--+-----<>1 ""'-+-<>-..--....- 0
A,
1KIt
YO
C,
J13..P.
LOGIC
INPUT
~OFF"
ISOLATION'" 20 LOG
[~J
YOUT
REPEAT TEST fOR IN2.IM3. AND IN4
CROSSTALK TEST CIRCUIT
VA = 1.DVRMS
@1=500kHz
VD'
D,
8,
son
CL=7pF
VD'
RL = 880n
CROSSTALK = 20 LOG
VD2
VD'
SW-201 WAVEFORMS
*
3 . 5 V - - - - - -.........
lOGIC INPUT
tr,tf<201l$
SW-202 WAVEFORMS
* 3.5V
50%
DV
OV============~~~====~----~.,~VO====
tr,tf<20ns
'\
5D%
.Wo
SW-201 OIJTPUT
SW-201 OUTPUT
'0'
Switch output waveform shown for Vs
JNo
Vo
-<;V
~==========~====~==~~~~---*
LOGIC INPUT
r-= constant with logic input waveform
tON -
j
Ii---t OFF--
8S shown. Va is the steady state output with switch on.
PAGE 11-44
SW-201/SW-202 QUAD SPST BI-FET ANALOG SWITCHES
APPLICATIONS INFORMATION
utilize PNP input transistors where input current Is max·
Imum at the logiC "0" level and drops to that of a reverse·
biased diode as the Input voltage Is raised above .. 1.4V.
This analog switch employs lon-Implanted JFETs In a
switch configuration designed to assure break-before-make
action. The turn-off time Is much faster than the turn·on
time to guarantee this feature over the full operating
temperature and input voltage range. Fabricated with BIFET processing rather than CMOS, special handling is not
necessary to prevent damage to these switches. Because
the digital Inputs only require a 2.0V logic "1" Input level,
power-consuming pullup resistors are not required for TTL
compatibility to Insure break·before·make switching as is
most often the case with CMOS switches. The digital inputs
The "ON" reSistance, RON, of the analog switches is con·
stant over the wide input voltage range of -15V to +11V
with VSUPPLY = ±15V. For normal operation, however,
positive input voltages should be restricted to 11V (or 4V
less than the positive supply). This assures that the VGS of
an OFF switch remains greater than Its Vp• and prevents
that channel from being falsely turned ON. Individual switches
are "ON" without power applied.
TYPICAL APPLICATIONS
PROGRAMMABLE GAIN NON·INVERTING AMPLIFIER WITH SELECTABLE INPUTS
+15V -15V
>-=------__~-_--_._--~--a VOUT
lX
18K!!
9.9KH
99.9kH
II
N
lOX
~
....
~
l00X
III
III
III
l000X
%
(.)
I-
loon
2KH
1000
~
CI
0
"':"
OPERATION FROM SINGLE POSITIVE POWER SUPPLY
f:,~'''V
V'
1/4SW201
0::; VAH.lOG:S V+ --4Y
3
VOUT
I
I
I
r------,
I TTL OR CMOS
I
I ______
GATE
I
L
~
I
"... j
v~
PAGE 11-45
GND
"':"
"':"
.....
oC
Z
oC
SW7510/7511
PMI
QUAD SPST BI-FET ANALOG SWITCHES
FEATURES
GENERAL DESCRIPTION
•
•
•
•
•
•
•
•
The SW751017511 are monolithic linear devices, each containing four independently selectable SPST analog switches.
Offering both normally open (SW7510), and normally closed
operation (SW7511), these units are fabricated with Precision Monolithic's high-performance BI-FET technology.
Because JFET switches are used, specIal handling, as
required with CMOS, Is not necessary to avoId damagIng
these unIts.
PIn Compallble wIth AD7510 01, AD7511 01
JFET SwItches Rather than CMOS
HIghly ResIstant to Stallc DIscharge Damage
No SCR Latch-up Problems
Low "ON" ResIstance - 750 MaxImum
SuperIor "OFF" IsolatIon and Crosstalk
DIgItal Inputs CompatIble wIth TTL and CMOS
No Pull-up ResIstors RequIred to Inlure
Break-Before-Make Action WIth TTL Inputl
Performance advantages include exceptionally high "OFF"
isolation and low crosstalk. Low leakage currents enable
high transfer accuracy applications which include program·
mabie gain amplifiers and active filters. Data conversion,
position controllers, choppers, demodulators, and general
purpose switching and multiplexing are among other ap·
plications for which these devices are well suited.
ORDERING INFORMATIONt
PACKAGE
HERMETIC
DIP
TEMPERATURE
RANGE
SOil
SW7510AO'
SW7510EO
MIL
INO
7511
SW7510BO'
SW7510FO
MIL
INO
6011
SW7511AO'
SW7511EO
MIL
INO
7511
SW7511BO'
SW7511FO
MIL
INO
25°C
RESISTANCE
PIN CONNECTIONS
16-PIN HERMETIC DUAL-IN-LINE
(Q-Sufflx)
CONTROL LOGIC:
SW7510: Switch "ON"
for Address "HIGH"
SW7511: Switch "ON"
for Address "LOW"
• Also available with MIL-STD-883B processing. To order add/883 as a sullixto
the part number.
tAil listed partsareavailable with 160 hour burn-in. See Ordering Information,
Section 2.
SCHEMATIC DIAGRAM
o
GNO
v-
PAGE 11-46
SW7510/7511 QUAD SPST BI·FET ANALOG SWITCHES
ABSOLUTE MAXIMUM RATINGS (TA =25·C unless otherwise noted)
Operating Temperature Range,
V + Supply to Ground ........................... 35V
SW7510/7511 AO, BO . . . . . . . . . . ... -55·C to + 125·C
Logic Input Voltage. . . . . . . . . .. . . . . . . . . . . . . . . .. Note 3
SW7510/7511 EO, Fa . . . . . . . . . . . . .. -25·C to +85·C
Analog Input Voltage
Continuous .......... V- Supply to V+ Supply +20V
DICE Junction Temperature (T j ) •••••.• -55°C to +150°C
Storage Temperature Range. . . . . . . .. -55·C to + 150·C
1 % Duty Cycle and Driving
all 4 Inputs with
Power Dissipation ........................... 500mW
Derateabove100·C ...................... 10mW/·C
500l'spuise .... V- Supply -15VtoV+ Supply +20V
Lead Soldering Temperature (50 sec) ............ 300·C
Maximum Current through Any Pin .............. 25mA
Maximum Junction Temperature. . . . . . . . . . . . . . .. 150·C
NOTE: Absolute ratings apply to both DICE and packaged parts unless
V + Supply to V - Supply . . . . . . . . . . . . . . . . . . . . . . .. 36V
otherwise noted.
ELECTRICAL CHARACTERISTICS at Vs= ±15V and T A = +25°C, unless otherwise noted.
SW7510AlE
SW7511A1E
PARAMETER
SYMBOL
CONDITIONS
"ON" Resistance
RON
Vo=OV.IOS=lmA
<1RON vs. Vo (V s)
<1RON
-10V"VO" +10V,l oS=lmA
RON Match 01 Switches
RON Match
Vo=OV,los=lmA
MIN
+10
-10
SW7510B/F
SW7511B/F
MAX
TYP
MAX
60
75
80
100
Il
6
10
10
10
%
1.5
10
1.5
10
+11
-15
MIN
UNITS
TYP
+10
-10
+11
-15
%
Analog Voltage Range
VA
Is=lmA
"OFF" Leakage Current
IS(OFF)' IO(OFF)
Vs= +10V, Vo= -10V (Note 1)
1.0
3.0
"ON" Leakage Current
ISlON) + IO(ON)
Vs = Vo = + 10V (Note 1)
1.0
3.0
Logic "I" Voltage
VINH
Logic "0" Voltage
VINL
Logic "0" Current
IINL
VIN= +O.4V
1.5
Logic Input Capacitance
C OIG
VIN= +O.4V
1.5
"ON" Switching Time
tON
Vs= -5V, RL=lkll, CL=7pF (Note 5)-
350
450
450
550
ns
tOFF
Vs= -5V, RL=lkll, C L =7pF(Note5)-
260
300
350
450
ns
"OFF" Isolation
ISO OFF
(Note 2)
66
66
dB
Crosstalk
CT
(Note 4)
70
70
dB
Analog "OFF" Capacitance
CSlOFF)' CO(OFF) VS=OV, Vo=O
6.5
6.5
pF
"OFF" Switching Time
2.0
Volts
2.0
nA
Volts
0.8
0.8
3.5
nA
1.5
3.5
1.5
Volts
"A
pF
Analog "ON" Capacitance
CS(ON), COlON)
VS=OV, Vo=O
14
14
pF
Feedthrough Capacitance
COSIOFF)
Vs=OV
0.8
0.8
pF
CSS(OFF)'
Vs=OV
0.4
0.4
pF
COO(OFF)
VS=OV
0.4
0.4
pF
Positive Supply Current
1+
Logic Inputs at "0" or "I"
5.0
9.0
3.0
9.0
mA
Negative Supply Current
1-
Logic Inputs at "0" or "I"
2.8
5.0
1.7
5.0
mA
Channel Capacitance
NOTES:
(pin 2) terminal; however it may not be lower than the V- terminal (pin 1l.
The maximum logic Input voltage may be as much as 36V above the
V- terminal.
1. The conditions listed speciftythe worst case leakage currents. The leakage
currents apply equally to source (S) or drain (D).
2. OFF isolation is measured by driving the source of any OFF switch, and
observlr:-g the voltage which appears on the drain. TheconditiOriS are: R_ =
6800, C L = 7pF, Vs = IV, RMS, f = 100kHz.
3. The minimum logic input voltage may be as much as 2V below the GNO
4. Crosstalk is measured by driving source of any OFF switch and observing
voltage which appears on any other"ON" output drain. The conditions are:
RL = 6800, C L = 7pF, Vs = IV, 1 = 100kHz.
5. Sample tested.
PAGE 11-47
III...
...
...C;
...
...~
II>
II>
UI
UI
1&1
J:
0
l-
iUI
CJ
0
....
ee
z
ee
SW7510/7511 QUAD SPST BI,FET ANALOG SWITCH
ELECTRICAL CHARACTERISTICS at Vs = ±1SV, -SsoC S TA S +12SoC for SW7S10AO, BO and SW7S11AO, SO and
-2SoC S T AS +8SoC for SW7S10EO, Fa and SW7S11 EO, Fa, unless otherwise noted,
.
SW7510B/F
SW7511B/F
SW7510AlE
SW7511A1E
PARAMETER
SYMBOL
CONDITIONS
"ON" Resistance
RON
Vo=OV,los=lmA
RON vs. Temperature
RON Drllt
Vo=OV,los=lmA
Analog Voltage Range
VA
Is=lmA
MIN
TVP
MIN
MAX
TVP
100
+11
-15
+10
-10
%,"C
+11
-15
Volts
"OFF" Leakage Current
IS(OFF), ID(OFF)
Vs= +10V, Vo= -10V (Note 1)
90
100
IS(ON) + ID(ON)
Vs=vo= +10V (Note 1)
90
100
logic "I" Voltage
VINH
VINL
IINL
VIN = +O.4V
"ON" Switching Time
tON
"OFF" Switching Time
tOFF
Positive Supply Current
1+
Negative Supply Current
1-
nA
nA
2.0
2.0
Logic "0" Current
Il
0.5
liON" Leakage Current
logic "0" Voltage
UNITS
150
0.4
+10
-10
MAX
Volts
0.8
0.8
5.0
7.0
Vs= -5V, RL=lkll, CL=7pF
800
1000
Vs = -5V, RL = lkll, CL = 7pF
500
750
ns
Logic Inputs at "0" or "I"
13
13
mA
logic Inputs at "0" or "I"
7.5
7.5
mA
Volts
ns
NOTE:
1. The conditions listed specify the worst case leakage currents. The leakage
currents apply equally to source (S) or drain (0).
AC TEST CIRCUITS
CROSSTALK MEASUREMENT CIRCUIT
ISOLATION MEASUREMENT CIRCUIT
-15V
CROSSTALK = 20 LOG
+15V
~
1V RMS
son
.,
7,F
v+
son
-15V
OFF ISOLATION. 20 lOG
~,'
v-
D,
7,F
A,
7,F
SWITCHING TIME TEST CIRCUIT
TYPICAL PERFORMANCE CHARACTERISTICS
LARGE SIGNAL SWITCHING
LARGE SIGNAL SWITCHING
&.ov
ov...n..rt.
+16V -1&V
..
V+
vOND
SW7611
VA
VAD---I
PAGE 11-48
= -10V, RL =
lkn, CL
= 100pF
SW7510/7511 QUAD SPST BI·FET ANALOG SWITCH
DICE CHARACTERISTICS (125° C TESTED DICE AVAILABLE)
DIE SIZE 0.091 " 0.093 Inch
SW·7510 (SWITCH ON FOR ADDRESS HIGH)
SW·7511 (SWITCH ON FOR ADDRESS LOW)
1. NEGATIVE SUPPLY
Z. GROUND
3. SWITCH (1) ADDRESS (A1)
4. SWITCH (Z) ADDRESS (AZ)
5. SWITCH (3) ADDRESS (A3)
8. SWITCH (4) ADDRESS (A4)
7. DISABLE
•• POSITIVE SUPPLY
1.
Z.
3.
4.
5.
8.
7.
••
9. SWITCH (4) DRAIN (D4)
10. SWITCH (4) SOURCE (84)
11. SWITCH (3) DRAIN (D3)
1Z.
13.
14.
15.
18.
SWITCH
SWITCH
SWITCH
SWITCH
SWITCH
(3) SOURCE (S3)
(2) DRAIN (02)
(2) SOURCE (S2)
(1) DRAIN (01)
(1) SOURCE (S1)
NEGATIVE SUPPLY
GROUND
SWITCH (1) ADDRESS (A1)
SWITCH (2) ADDRESS (A2)
SWITCH (3) ADDRESS (A3)
SWITCH (4) ADDRESS (A4)
DISABLE
POSITIVE SUPPLY
9.
10.
11.
12.
13.
14.
15.
18.
SWITCH (4) DRAIN (04)
SWITCH (4) SOURCE (84)
SWITCH (3) DRAIN (03)
SWITCH (3) SOURCE (S3)
SWITCH (2) DRAIN (D2)
SWITCH (2) SOURCE (SZ)
SWITCH (1) DRAIN (01)
SWITCH (1) SOURCE (S1)
II
...
Refer to Section 2 for additional DICE Information.
Iii
....
....
0
Iii
....
:.UI
ELECTRICAL CHARACTERISTICS at 25°C for V+ = +15V. V- = -15V and T A = 25°C. unless otherwise noted.
SW7510/7511N
PARAMETER
SYMBOL
CONDITIONS
"ON" ReSistance
RON
Vo=OV,los=1mA
SW7510n511G
LIMIT
LIMIT
UNITS
75
100
IlMAX
Lagle "1" Voltage
V 1NH
2.0
2.0
VMIN
Logic "0" Vollage
V ,NL
0.8
0.8
V MAX
Logic "0" Current
I'NL
V,N =+0.4V
3.5
3.5
,J. MAX
Positive Supply Current
1+
Logic Inputs at "0"
7.5
7.5
mAMAX
Negative Supply Current
1-
Logic Inputs at "0"
4.0
4.0
mAMAX
TYPICAL ELECTRICAL CHARACTERISTICS at V+ = +15V. V- = -15V and T A = 25°C. unless otherwise noted.
PARAMETER
SYMBOL
CONDITIONS
Vo=OV,los= 1mA,
SW7510n511N
SW7510n511G
TYP
TYP
100
150
II
%.I'C
UNITS
"ON" Resistance
RON
RON VS. Temperature
RON Drift
Vo=OV,los= 1mA
0.4
0.5
"ON" Switching Time
tON
Vs =-5V, RL = 1kll, C L = 7pF
800
1000
ns
"OFF" Switching Time
tOFF
500
750
ns
-55'C" T A " +125'C
NOTE:
The minimum logic input vollage may be as much as 2V below the GND pad;
however. it may not be lower than the V- pad. The maximum logic input voltage may be as much as 38V above V- pad.
PAGE 11·49
UI
W
:E:
U
I-
iUI
"
0
...I
C
Z
C
SW7510/7511 QUAD SPST BI·FET ANALOG SWITCH
TYPICAL PERFORMANCE CHARACTERISTICS (Apply to all models, unless otherwise noted)
SMALL SIGNAL SWITCHING
WITH FILTERING
SMALL SIGNAL SWITCHING
SMALL SIGNAL SWITCHING
VA = -500mV. RL
CL = 13pF
SMALL SIGNAL SWITCHING
WITH FILTERING
VA
= lkn.
SMALL SIGNAL SWITCHING
= -500mV. RL = lkn. CL = 100pF
VA
= 500mV. RL = lkn. CL = 13pF
VA = 500mV. RL
CL = 100pF
= lkn.
CHARACTERISTIC CURVES
"ON" RESISTANCE (RON) vs
ANALOG VOLTAGE (VA)
NORMALIZED RON vs
SWITCH CURRENT (Is)
120 ...-,.--r-..,--r-r-r--r-:""::::"r--l
110
~- ~~: ~~:~ -+-+-+-+-+--1--1
TA "'25"C
100 ~ lOS = ±lmA
90
oo
70
1.3
1.2
-+-+-+-+-+-+--1
SW7510/11B, F
Sl7511/1'~.
E
r-
so
_J)'0VI~
-
~ 1.0
::;
~
o.9
/~ -
,/
/'
VA - ANALOG INPUT VOLTAGE (V)
r-- .~+. ~'5VI
v-", -lSV
16o _,IOS= 1 rnA
VA =OV
0
--
V
SW7510/11; B, F
YT
f- --:!-V A =-1.0V
0
40
--- r--
0. 7
~r-r-+-+-~-+-+-+-+-~
~1~0--~8--~.-~~-~2-0~~2~4~6~8~'0
180
1/
~
z O.8
~~r-+-+-4--+-+-+-+--I~
--
V-= -15V
1r----- TA =25"C
:!i
50
r-LLJ-
RON vs TEMPERATURE
200
,.-
1.-::: :::::. ,-
..,., J-+SW7510/11; A, E
20
0.
•
-5 --4. -3
-2 -1
0
1
IS (mA)
PAGE 11-50
2
3
4
5
0
-60 --40 -20
0
20
40
60
TEMPERATURE
80
rei
100 120 140
SW7510/7511 QUAD SPST BI·FET ANALOG SWITCH
CHARACTERISTICS CURVES (Apply to all models, unless otherwise noted)
SWITCH LEAKAGE CURRENTS
vs ANALOG INPUT VOLTAGE
30.
vi
27.
240
,. r- v-=
,. .......
I I
= +15V'
= -16V
T A .. 25"C
v-
0
-15V
T A =25"C
,I (olF)
IS
v+~ +,L
I- v-=
-15V
V+=+15V
I
21.
'80
SUPPLY CURRENTS
vs TEMPERATURE
SWITCH CAPACITANCES
vs ANALOG VOLTAGE (VA)
20
•
Cs
'/
ION) I-
I ....
I I
'5.
'20
9.
'0 (ON( + IS
(~
If-
~
30
•
-6
-4
2
0
2
4
6
8
10
-10 -8
--6 --4
-2
... r- .~+.
ODD
1+'5J
I
...
600
-20
"
;:-4D
r--.. ~NL- f-
r--
400
300
o
20
40
8
--60 -40 -20
10
0
J+~l,~UIII
600
-15V
TA = 2SoC
650
80
TEMPERATURE
80 100 120 140
rei
,
/
r:;::/:
I
~
!!l-70
t:?lli
'Ok
60
80 100 120 140
"i=
or---
TON
v 7 ....
350
I I
1M
200
FREQUENCY (Hz)
'OM
V
~
..."
250
III
TON
I.
.,.. ---
V
300
,,
111111
SW7510/11; B, F
0
!
Ciililill
lOOk
60
v~. ,~,o
145
I
I
Y
~/
40
V- = -15.0
Vs = -5V
I
I
I
I_
SW7610/11; A, ~_
;:; 400
OFF ISOLATION
~
-90
I
20
SWITCHING TIMES
vs TEMPERATURE
650
r-CIRII'IIIIII
'"o -60
0-80
200
'00
-80-40 -20
6
TEMPERATURE (' C)
SEE AC TEST
~
~
5 -50
........ ........
4
~ -30 I-- V- =
r- ~Lp~~~~~LL~~7~~.o"
r-
2
CROSSTALK AND "OFF"
ISOLATION vs FREQUENCY
I
V-"'-15V
.DD
70.
0
VA (VOLTS)
DIGITAL INPUT BIAS CURRENT
(INd vs TEMPERATURE
,
I
o
o
VA !V)
1100
IJ sw)slo,i,."7E
r- r- t-t-.J..
,
10 (OFF)
-10 -B
"-t--I-l I
I ..... ........
VI
/A
60
.............
1+ SW1S10/1'; A, E
Cs (OFF)
l-
1 ..... [ '
1~
I
~F""
./
i
SW7510/11; A, E
SW7510/11; B, F
TOFF
TOFF
'50-60 -40 -20
0
20
40
60
80
1T
II
..Ii
!::
c
Ii
3i
u
100 120 140
TEMPERATURE tGCI
U
II
::I
..
(.
~
C
C
APPLICATIONS INFORMATION
This analog switch employs ion-implanted JFETs in a switch
configuration designed to assure break-before-make action.
The turn-off time is much faster than the turn-on time to
guarantee this feature over the full operating temperature
and input voltage range. Fabricated with BIFET processing,
special handling, as required with CMOS, is not necessary to
prevent damage to these switches. Because the digital inputs
only require a 2.0V logic "1" input level, power-consuming
pullup resistors are not required for TTL compatibility to
insure break-before-make switching as is most often the
case with CMOS switches. The digital inputs utilize PNP
input transistors where input current is maximum at the logic
"0" level and drops to that of a reverse-biased diode (about
10nA) as the input voltage is raised above ~ 1.4V.
The "ON" resistance, RON, of the analog switches is con·
stant over the wide input voltage range of -15V to + 11V
with VSUPPLY = ± 15V, Higher input voltage is tolerable pro·
vided that some form of current limiting is employed (such
as that of an op·amp output stage) to avoid exceeding
junction temperature and power dissipation requirements,
For normal operation, however, positive input voltages
should be restricted to 11V (or 4V less than the positive
supply). This assures that the VGS of an OFF switch remains greater than its Vp , and prevents that channel from
being falsely turned ON. Individual switches are "ON"
without power applied.
Proper switching requires the "Source" terminal be con·
nected to the input driving signal.
PAGE 11-51
:;;
:iI
011
SW7510/7511 QUAD SPST BI·FET ANALOG SWITCH
TYPICAL APPLICATIONS
ACTIVE LOW·PASS FILTER WITH DIGITALLY
SELECTED BREAK FREQUENCY
LATCHING DPDT SWITCH
+15V
Ao
•
feo
v+
PR
INPUT 1
Q'
,/2
r=
fC'
SN7474
SELECT
OUT 1
Q
TTL
CONTROL
•
INPUT 2
CLR
fe2
SELECT
INPUT 3
A,
fe,
SELECT
OUT 2
INPUT 4
Rl = 10k
Your
Truth Table
A1
1
1
0
State of Swltche.
After Command
52 and S3
51 and 53
same
same
on
off
off
on
0
INDETERMINATE
Command
Ao
1
o
1
o
'60
'20
.......
Op·020PEN
.... ,LOOPGAIN
....
'c,
INTEGRATOR WITH ANALOG RESET AND
START/STOP CAPABILITY
'C3
'C2
......... '-...
0
-,
"
""-...
""-... -~
VAL
~,
,
............
~~
............
....,
""-... ............
""-... ........... ............
10
100
lK
10K
100K
1M
FREQUENCY - Hz
"0
AL (VOLTAGE GAIN BELOW BREAK FREQUENCY) =
SW1510FQ
~
~ = 100 (40dB)
'6
'5 R
V,N o--"'-o""I"""",,M~'"'-I
I
Ie (BREAK FREQUENCY) = 2"R~CX
START~~
fL (UNITY GAIN FREQUENCY) = 2 R1 C
.
NOTE: Applications show SW7510. For SW7511 applications the logic is
inverted.
PAGE 11-52
" 1 X
SAMPLE
AND HOLD
AMPLIFIERS
SAMPLE AND HOLD AMPLIFIERS
INDEX
PAGE
PRODUCT
TITLE
SMP-10/11
GAP-D1
PKD-D1
Low Droop Rate/Accurate Sample and Hold Amplifiers .•..•••...•..••••...........•••.•••.•• 12-5
Analog Signal Processing Subsystem .............•. ~ ..•.•••....•....••.....•....•••••••.. 12-14
Monolithic Peak Detector ........•••..••.•......•••........••••••.....••••••••••......... 12-29
INTRODUCTION
Sample-and-hold amplifiers"Sample" an analog input signal
and then "Hold" the instantaneous input value upon the
command of a logic control signal. Basically the sampleand-hold is an "analog memory" where an external capacitor
serves as the storage element. Applications in which a time
varying input cannot be tolerated require sample-and-hold
circuits. A fast successive-approximation analog-to-digital
converter is one application. Data acquisition, data distribution, analog delay and telephony requirements dictate the
use of sample-hold circuits to "freeze" the analog signal for
further signal processing.
A sample-and-hold circuit is conceptually an amplifier, .
switch, and capacitor. Many specifications are similar to
those of switches and operational amplifiers - bias currents,
voltage gain, and charge injection are examples. These and
other specifications pertaining uniquely to sample-and-hold
circuits are defined below.
The SMP-10 and SMP-11 are precision sample-and-hold
amplifiers with high accuracy, low droop rate, and fast signal
acquisition time. These Circuits contain a high input impedance input buffer amplifier, a diode bridge sample hold
switch, a transconductance or "Super-Charger" circuit to
enhance slewing and' a high speed output amplifier. The
"Super-Charger" is capable of supplementing the diode
bridge capacitor charging current whenever the difference
between input and output levels exceeds a given threshold.
Settling to final value is under control of currents from the
diode bridge, thus minimizing the chances of overshoot and
instability. The low zero scale error is achieved by precision
current matching techniques employed in the biasing of both
input and output amplifiers and the diode bridge. The inherent low offset voltage errors and low charge injection made
possible by precise circuit design and layout allows the
residual zero scale errors to be actively trimmed using PMl's
"Zener Zapping" technology without degrading temperature
performance. "Super Beta" transistors made possible by ion
implant processing create the high input impedance amplifiers needed for low droop rate and minimal signal loading.
The SMP-10 and SMP-11 differ from each other in droop rate
and settling time in the hold mode.
In addition to Precision Sample and Hold Amplifiers, two
products with related capabilities are also available. The
GAP-01 General Purpose Analog Processor provides the user
with two independent switched transconductance amplifiers,
a unity gain buffer and an uncommitted voltage comparator.
This is a non-dedicated functional block which has a wide
variety of applications. Thp. second device is the PKD-Ol Monolithic Peak Detector. This device performs the peak detector
function with accuracies approaching those obtainable with
high cost hybrid modules at a cost approaching the low cost,
low performance discrete designs.
PAGE 12-2
DEFINITIONS OF TERMS
ACQUISITION TIME
The minimum time for the output voltage to begin tracking
the input voltage, to within a specified error band, after the
inception of the sample command. By convention, acquisi·
tion time is defined for sampling of a DC level. For instance
a circuit which is "holding" a 10V output signal, and
operating with zero input volts, is switched to the sample
mode. The acquisition time is then the time required for the
output to decrease to within a ±10mV band about ground
potential.
APERTURE TIME
The time between the inception of the hold command and
the time the circuit output ceases tracking the input signal.
When the holding capacitor charging current is less than
O.3mA the aperture time is nomlna"y 5Ons. The aperture
time Is a function of the holding capacitor charging current
'CH. The changing current is in turn a function of the rate of
change of the input signal voltage. This relationship holds
true up to a maximum of 50mA which is the maximum
current available from the SMP·11 to charge holding capaci·
tor CH. Charging current can be calculated from the rate of
change of the input analog signal and the size of CH by the
equation:
ICH = CH
~~ (ICH = 50mA Max.)
CHANGE IN HOLD STEP
Actual hold step less the hold step measured after sampling
V = O. A change in hold step has two components: the first is
a function of input voltage, the second is a function of the
rise time of the 5tH voltage. Note that rise time of 5tH
voltage also effects ZERO·SCALE·ERROR.
CHARGE TRANSFER
The amount of charge transferred to the holding capacitor
due to the action of the switch. Charge is transferred to CH
when the circuit is switched to the hold mode. Charge
transfer causes a change In output voltage tNzs as defined
by the equation:
tN (V) = at(pC)
zs
CH (pF)
FEEDTHROUGH ATIENUATION RATIO
The change of voltage applied to the input as a ratio of the
change of voltage observed at the output, caused by the
input disturbance, while the circuit is in the hold mode.
FULL POWER BANDWIDTH
The maximum frequency at which rated output voltage Eor
can be supplied without significant distortion. Fu" power
bandwidth Fp is related to slew rate SR by the following
equation:
F _..§B....
p-
21rEor
Using this equation Fp of 160kHz can be computed. This is
applicable only for pulsed conditions. Power dissipation
limits Fp to 100kHz for C.W. operation.
GAIN ERROR
Voltage difference between input and output voltage minus
the output voltage measured over specified range.
HOLD CAPACITOR CHARGING CURRENT
The current ICH which charges, or discharges, the capacitor
while the circuit is in the sample mode.
HOLD MODE SETILING TIME
The time for a" transients to settle within a specified error
band. Measured from the inception of the hold command.
HOLD STEP
Magnitude of step caused In the output voltage by switch·
ing the circuit from sample mode to hold mode.
INPUT BIAS CURRENT
The current into the input terminal with input voltage held at
zero volts.
The current which flows out of holding capacitor CH while
the circuit Is operating In the hold mode. In general droop
current lOR is defined positive when its direction is into the
CH pin.
at
~VZS(V)=CH -1mV
OUTPUT RESISTANCE
An AC change in output voltage as a result of an AC change
in load current.
DROOP RATE
Droop rate dVdtdt is the rate of change of output voltage while
the circuit is operated in the hold mode. dVdtdt is a direct
function of droop current lOR and related by the equation:
dVd =~ 1""
dt
CH x U·
where dVdtdt is expressed in ,.Vtms with lOR in nanoamperes
and CH in picofarads.
In
a:
III
ii:
:::i
IL
INPUT RESISTANCE
The ratio of the AC change in the input current as a result of
the change in the input voltage.
LEAKAGE(DROO~CURRENT
Note that for at = 5pC and CH= 5000pF offset error = 1mY.
The 5MP-11 has been factory nulled for CH = 5000pF. For
other values of CH the zero scale shift can be calculated
from the equation:
II
POWER SUPPLY REJECTION RATIO
The change in output voltage for a change in power supply
voltage when the circuit is maintained in the sample mode.
The best power supply rejection ratio PSRR is obtained with
the power supply voltage changing at a very low rate (DC).
For essentially DC conditions PSRR for the hold mode of
operation is essentially the same as the PSRR for the
PAGE 12-3
:::E
ct:
C
..J
o
J:
C
Z
ct:
III
..J
IL
:::E
ct:
In
sample mode. PSRR Is degraded as the frequency of the
disturbance Increases. PSRR for both sample and hold
modes Is shown graphically as a function of frequency.
Input voltage which differs from the output voltage, with the
circuit in the hold mode, then switching to the sample mode
and observing the rate of change of the output voltage.
SAMPLE/HOLD CURRENT RATIO
TOTAL ERROR
The ratio of the peak charging current available to the droop
current.
.
The algebraic sum of the following factors:
I. ZERO·SCALE ERROR
Ii. Gain Error
SIGNAL TRANSFER NONLINEARITY
The total input to output, nonadjustable, hold mode error
caused by gain nonlinearity, feedthrough, thermal transient,
charge transfer and droop rate. These error terms cannot be
corrected by offset and gain adjustments. Signal transfer
nonlinearity is tested for a specified holding capacitor, input
voltage change and hold period.
iii. Hold Step Change versus
dV~~H)
Iv. Hold Step Change versus VIN
VOLTAGE GAIN
The ratio of the output voltage to the Input voltage with the
circuit operating In the sample mode.
SLEW RATE
ZERO SCALE ERROR
The maximum possible rate of change of the output voltage
when supplying the rated output. For a sample and hold
circuit, slew rate must be defined with a specified value of
holding capacitor C H• For the SMP·11, slew rate can either
be measured by operating the circuit In the sample mode
and applying a step function to the Input, or by applying an
The magnitude of the output voltage when the circuit is
switched from sample to hold mode while holding the input
at zero volts. ZERO SCALE ERROR Vzs Is the algebraic sum
of the offset voltage and the charge transfer step voltage.
Vzs can be adjusted to zero (see ZERO SCALE ERROR pull
adjustment).
PAGE 12-4
SMP-l0/SMP-ll
PMI
LOW DROOP RATE/ACCURATE
SAMPLE AND HOLD AMPLIFIERS
®
FEATURES
GENERAL DESCRIPTION
SMP-10
• Low Droop Rate •...•.............•.........• 5.01'VlmS
• Low Signal Transfer Non-Linearity ••.......•.... 0.005%
• High Sample Current/Hold Ratio ..•..•.•.•.••... 2x10 9
The SMP-10/11 are precision sample and hold amplifiers that
provide the high accuracy, the low droop rate and the fast
acquisition time required in data acquisition and signal pro·
cessing systems. Both devices are essentially non-inverting
unity gain circuits conSisting of two very high input impedance buffer amplifiers connected together by a diode bridge
switch.
SMP-11
• Low Droop Rate over Temperature •••••....• , 120l'VlmS
• High Sample Current/Hold Ratio ..........•.... 1.7x10B
BOTH SMP-10 AND SMP-11
• Fast Acquisition Time, 10V Step to 0.1% .......... 3.51'S
• High Slew Rate ••........•.......•............. 10Vll'S
• Low Aperture Time ......•.•.•.........•.......•• 50nS
• Trimmed for Minimum Zero Scale Error ......... 0.45mV
• Feedtrhough Attenuation Rallo .•................. 96dB
• Low Power Dissipation .......•••.•.••..•...... 160mW
• DTL, TTL & CMOS Compatible Logic Input
• HA-2420, HA-2425, DATEL, SHM-IC-1, and AD583 Socket
Compatible"
PIN CONNECTIONS
14·PIN DIP
HIGH ACCURACY AND LOW DROOP RATE
The high input impedance and the low droop rates of the
SMP-10 and the SMP-11 are achieved by using bipolar darlington circuits and an ion implant process that creates
"super beta" transistors.
The output buffer's input stage converts to a super beta
darlington configuration during the hold mode, which results
in a very low droop rate with no penalty in acquisition time.
The use of bipolar transistors achieves a low change in droop
rate over the operating temperature range.
FAST ACQUISITION
A unique super charger provides up to SOmA of charging
current to the hold capacitor, which results in smooth, fast
charging with minimum noise. As the hold capacitor voltage
nears its final value, the low current diode bridge controls the
final settling time. This unique combination of linear functions in a monolithic circuit enables the system designer to
achieve superior performance.
(V·SUFFIX)
-
iii
......
Ct
0;Il.
FUNCTIONAL DIAGRAM
:E
en
en
• Pins 1 and 8 are not internally connected, in unity gain applications,
SMp-10 and SMp-11 can replace HA-2425, HA-2420, SHM·IC-1 and
AD-583 directly.
•• Sample/Hold Control
(High = Hold Low = Track)
II:
w
ii:
::::i
II.
:E
C
Q
....
0
:z:
LOW DROOP RATE OVER TEMPERATURE
Q
Z
C
OUTPUT
+0.4
1---f""r-I--l--"""''::'':'---j,......-t--l-80
1 +0.2 k:--+-"'-""'I.:,--+-
C
en
is
+401
~
2i
:E
.."
::>
u -0.2
1-+-\1\-+--1 +80 ~
-0.4
-0.6
"
ARROW INDICATES POSITIVE
3 4
~
-1~rl--l
+120
,-va.;..,L..TA_G_E..PO_L_A..
R'_TV
...._L-....L..---''--....I
+160
NULL
lOR REGARDLESS OF CH
-0.8
-55 -25
0
+25
+50
+75 +100 +126 +160
Manufactured under one or more of the following patents: 4,109,215;
4,142,117.
....
II.
-l-----1I--l-40i
..i5
...
W
PAGE 12-5
SMP-10/SMP-11 LOW DROOP RATElA,CCURATE SAMPLE AND HOLD AMPLIFIERS
ELECTRICAL CHARACTERISTICS at V S =± 15V, CH=O.005I'F, VLcconnected toground, TA =
25° C, device fully warmed
up, unless otherwise noted.
SMP-10AlE
SMP-11AlE
PARAMETER
Zero Scale Error
(Hold Mode)
Input Bias Current
Leakage
(Droop) Current
Droop Aate
Input Resistance
Voltage Gain
Vzs
Hold Mode
Settling Time
Charge Transfer
Slew Rate
Hold Capacitor
Charging Current
Sample/Hold
Current Ratio
V,N=O
lOR
.
SMP-l0
Device Warmed Up SMP-ll
dVm/dt
.
SMP-l0
Device Warmed Up SMP-ll
A'N
See Note 1
Av
Sample Mode
Y,N = ±10V. AL = 5kn
or Y'N = ±5V, AL = 2.5kn
t Hm
at
V,N=O
VLOG = 3.5V
SA
V,N =±10V
AL =2.5kn
ICH
V1N - VOUT ~ ±3V
Input Voltage Aange
and/or Output
Voltage Swing
Output Resistance
Power Supply
Rejection Ratio
Power
Consumption (DC)
MAX
1.5
0.60
3.0
50
30
90
20
200
5
70
Hold Step
Signal Transfer
Nonlinearity
V,N=O
Sample Time = 10~s
mV
160
nA
4.5
50
500
60
900
nA
"Vlms
0.99940 0.99975
V/V
3.5
3.5
3.5
,,5
5.0
5.0
5.0
"s
50
50
50
ns
1.5
7
1.5
1.5
"s
5
5
pC
10
10
VI"s
50
50
mA
20
50
3Xl0 e 2Xl0·
- 1.7Xl08
86
8Xl0 7 8Xl0 8
- 1.5Xl08
60
96
100
±11
±11.5
±10.5
82
-
160
180
mA/mA
1.5Xl08
90
90
dB
100
100
kHz
±11.5
±10.5
0.15
77
92
92
72
170
SMP-10AlE
SYMBOL CONDITIONS
7.0
40
0.25
2.50
0.15
Sample Mode Y,N = 0
1.5
0.99953 0.99978
Ao
Po
UNITS
0.99963 0.99963
(Dissipation Limited)
Sample Mode
Vs= ±9V to±18V
MAX
n
±10Vp-p
PSAA
TYP
4Xl0'o
30
AL = 2.5kn
MIN
1.5Xl0'o 5Xl0'o
SMP-10 ONLY
PARAMETER
25
SMP-11G
TYP
10
Input = 20Vp-p 1kHz
Note 1
Fp
0.45
MIN
3Xl0'o 6Xl0'o
SMP-l0
SMP-ll
SMP-l0
SMP-ll
Im/lDR
Attenuation Ratio
Bandwidth
of final value.
MAX
5
60
t.
Settling to 1mV
TYP
0.10
1.00
10V step to within 10mV
of final value (0.1%)
10V step to within 1.0mV
offinal value (0.01%)
Feedthrough
Full Power
V,N=O
VLOG = 3.5V
18
Acquisition Time
Aperture Time
MIN
SYMBOL CONDITIONS
SMP-10B/F
SMP-11B/F
210
±11.5
0.15
n
92
dB
180
240
mW
SMP-10B/F
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
-1.0
+1.5
+4.0
-3.0
+1.5
+6.0
mV
0.005
0.010
0.007
O.ot5
% of 20V
± 10V Input. AL = 5K
Sample Time = 10"s
Hold Time = lms (See Note)
Output Noise
Wideband Noise 100Hz
to 100kHz Sample Mode
40
50
"VAMS
Hold Mode
Settling Time
Settling to 1.0mV of Final
Value. Y,N = OV
7.0
7.0
"s
NOTES:
1.
2. These measu rements are made with the devices warmed up. It can be seen
that there is a selection trade off between Droop Rate and Hold Mode
Guaranteed by design.
settling time.
PAGE 12-6
SMP-10/SMP-11 LOW DROOP RATE/ACCURATE SAMPLE AND HOLD AMPLIFIERS
ABSOLUTE MAXIMUM RATINGS (Note)
Supply Voltage (V + minus V -) ................... 36V
Power Dissipation .......................... 500mW
Input Voltage . . . . . . . . . . . . . . .. Equal to Supply Voltage
Logic and Logic Reference
Voltage . . . . . . . . . . . . . . . . . .. Equal to Supply Voltage
Output Short Circuit Duration. . . . . . . . . . . . . .. Indefinite
Hold Capacitor Short Circuit Duration .......... " 60 sec
Storage Temperature Range ......... -65·Cto +150·C
Lead Temperature (Soldering 60 sec) . . . . . . . . . . . .. 300·C
Operating Temperature Range
SMP-10AY,BY ................... -55·Cto+125·C
SMP-10EY,FY ....................... O·Cto +70·C
SMP·11AY, BY .................... -55·C to 125·C
SMP-11EY, FY,GY ..................... 0·Cto70·C
DICE Junction Temperature (T i ) ..•.... -6SoC to +1S0°C
NOTE: Absolute ratings apply to both DICE and packaged parts unless
otherwise noted.
ELECTRICAL CHARACTERISTICS VS = ± 1SV, C H = O.OOS"F, VLC connected to ground. 0° C::; TA ::; +70° C, device fully
warmed up, unless otherwise noted.
SMP-10E
SMP-11E
SMP-10F
SMP-11F
SMP-11G
TYP
MAX
TYP
MAX
UNITS
2.0
1.0
4.0
2.7
10
mV
35
75
40
140
50
250
nA
IDR
Device Warmed Up SMP-10
See Note 2
SMP-11
0.05
0.5
0.25
1.S
O.OBO
0.6
0.65
2.S
0.7
dVm/dt
Device Warmed UpSMP-10
SMP-11
See Note 2
10
100
50
360
16
120
130
560
140
PARAMETER
SYMBOL CONDITIONS
Zero Scale Error
Vzs
V'N
Input Bias Current
Ie
V'N~ OV
Leakage
(Droop) Current
Droop Rate
~
MIN
O. VLOG ~ 3.5V
TYP
MAX
0.75
MIN
MIN
nA
1000
~V1ms
Sample Mode
Voltage Gain
Av
Power Supply
Rejection Ratio
PSRR
Logic. Control
Input Current
ILC
Logic Input
Is/H
V'N~±10V, RL ~5k!l
or V'N ~ ±5V, RL ~ 2.5k!l
0.99955 0.99976
Sample Mode
BO
Vs~±9Vto±1SV
VLC~
90
OV
Sample Mode
Vs/H~ 0.5V
Hold Mode
VSIH~
0.99950 0.99972
75
0.99930 0.99970
SO
70
VIV
90
dB
-1
-2
-1
-3
-1
-4
p.A
-5
-15
-5
-15
-5
-15
p.A
•
~
~
Ci
0.2
5.0V
0.2
0.2
nA
:L::IE
III
Differential Logic
Threshold
1.3
O.S
2.0
O.S
1.3
2.0
O.S
1.3
2.0
V
III
a:
III
ii:
::::i
ORDERING INFORMATIONt
Q.
::IE
c(
TA = +25°C
VZS
(mV)
1.5"
3.0"
1.5
3.0
1.5"
3.0"
1.5
3.0
7.0
PACKAGE IS
DROOP
14 PIN DIP
RATE IN
JtVlmS HERMETIC
PLASTIC
20
50
20
50
200
500
200
500
900
SMP10AY
SMP10BY
SMP10EP
SMP10FP
SMP11Y
SMP11Y
SMP11EP
SMP11FP
SMP11GP
OPERATING
TEMPERATURE
RANGE
MIL
MIL
COM
COM
MIL
MIL
COM
COM
COM
0
...I
0
:I:
C
Z
c(
III
...I
Q.
::IE
c(
III
• Also available with MIL-STD-SB3B processing. To order add/BS3 as a suffix to
the part number.
tAil listed parts are available with 160 hour burn-in. See Ordering Information.
Section 2.
PAGE 12-7
SMP·10/SMp·11 LOW DROOP RATE/ACCURATE SAMPLE AND HOLD AMPLIFIERS
ELECTRICAL CHARACTERISTICS VS = ± 15V, CH = O.005I'F, VLC connected
to ground, -55 0 C:5 TA:5
+125
0
C,device
fUlly warmed up, unless otherwise noted.
SMP·10A
SMP-11A
PARAMETER
SYMBOL
CONDITIONS
Zero Scale Error
Vzs
Y,N = 0, VLOG = 3.SV
Input Bias Current
18
V,N=OV
Leakage (Droop) Current
lOR
TA=-SS"C
TA =+12S"C
TA = Full Range
See Note 2
Droop Rate
Voltage Gain
Power Supply
Rejection Ratio
Logic Control Input Current
Logic Input
dVm/dt
TA=-SS"C
TA =+12S"C
TA = Full Range
See Note 2
MIN
1.60
5.5
mV
70
260
nA
O.SO
1:50
o.oeo
0.90
1.22
4.00
0.60
4.0
0.90
10.0
SMP-l0
10
120
100
300
16
160
2S0
600
SMP-ll
120
eoo
160
2000
3.0
60
150
SMP-l0
0;050
0.60
SMP-ll
Sample Mode
Vs = ±9V to ±1eV
ISJH
0.999S0 0.99972
78
I.
0.99940 0.99968
88
72
0.8
nA
,..Vlma
VIV
90
dB
-1
-3
-1
-5
"A
-5
-15
-5
-15
p.A
0.2
Differential Logic
Threshold
NOTES:
TYP
UNITS
PSRR
VLC=OV
MIN
MAX
Sample Mode
V,N =±10V. RL = Skn
or Y,N = ±SV. RL = 2.Skll
Sample Mode
VSJH = 0.6V
Hold Mode
VSJH = 5.0V
MAX
1.25
Av
ILC
TYP
SMP·10B
SMP-11B
1.3
0.2
2.0
0.8
1.3
nA
2.0
·V
2. These measurements are made with the devices warmed up. It cao be seen
that there is a selection trade off between Droop Rate and Hold Mode
settling time.
Guaranteed by design.
PAGE 12-8
SMP-10/SMP-11 LOW DROOP RATE/ACCURATE SAMPLE AND HOLD AMPLIFIERS
2.
3.
4.
5.
7.
9.
11.
13.
INPUT
NULL
NULL
NEGATIVE SUPPLY
OUTPUT
POSITIVE SUPPLY
HOLD CAPACITOR (CHI
LOGIC THRESHOLD
CONTROL (VLcI
14. SAMPLE/HOLD COMMAND
2.
3.
4.
5.
7.
9.
11.
13.
INPUT
NULL
NULL
NEGATIVE SUPPLY
OUTPUT
POSITIVE SUPPLY
HOLD CAPACITOR (CHI
LOGIC THRESHOLD
CONTROL (VLcl
14. SAMPLE/HOLD COMMAND
DIE SIZE 0.081 x 0.088 Inch
DIE SIZE 0.081 x 0.088 Inch
ELECTRICAL CHARACTERISTICS
Refer to Section 2 for additional
DICE Informallon
Vs = ± 1SV. C H = O.OOSI'F. V LC connected to ground. TA
= 2So C. device fully
warmed uP. unless otherwise noted.
SMP-10N
SMP-11N
LIMIT
SMP-10G
SMP-11G
LIMIT
PARAMETER
SYMBOL
CONDITIONS
Zero Scale Error
Vzs
Y'N = O. VLOG = 3.5V
Hold Mode
1.5
Input Bias Current
I.
V,N = OV
50
90
nAMAX
Leakage (Droop) Current
lOR
.
SMP-l0
Device Warmed Up SMP-ll
0.10
0.25
2.5
nAMAX
Droop Rate
lOR
.
SMP-l0
Device Warmed Up SMP-ll
20
200
500
Voltage Gain
Av
Sample Mode
V,N = ±10V
orV,N =±5V
0.99963
0.99953
VIVMIN
II
Hold Capacitor
Charging Current
ICH
V1N - VOUT ~ ±3V
30
20
mAMIN
5"i
±11
±10.5
VMIN
CI)
82
77
dBMIN
...u::
180
210
mWMAX
-2
-3
p.AMAX
-15
-15
p.AMAX
0
0
nAMAX
3.0
50
UNITS
mVMAX
p.Vlms MAX
...
Q.
:&
Input Voltage Range and/or
RL = 2.5kO
Output Voltage Swing
CI)
Power Supply
Rejection Ratio
PSRR
Sample Mode
Vs = ±9V to ±18V
Power Consumption
Po
Sample Mode Y,N = 0
Logic Reference Input Current
Logic Input
ISIH
Differential Logic
Threshold
Sample Mode
VSlH = 0.6V
Hold Mode
VSlH = 5V
2.0
0.8
VLC=O
2.0
0.8
V MAX
VMIN
II:
::::i
Q.
~
CI
....
o
:E:
CI
Z
C
.......
Q.
TYPICAL ELECTRICAL CHARACTERISTICS
Vs
!
= ± 1SV. CH = O.OOSI'F. VLC connected to ground. TA = 2SoC. devjce
fully warmed uP. unless otherwise noted.
PARAMETER
SYMBOL
10V step to 0.1% of final value
Acquisition Time
Aperture Time
CONDITIONS
t.
Charge Transfer
0,
V,N=O. VLOO -3.5V
Slew Rate
SR
V,N =
±10V. RL = 2kO
PAGE 12-9
SMP-10N
SMP-11N
TYP
SMP-10G
SMP-11G
TYP
3.5
3.5
p.s
50
50
ns
UNITS
5
5
pC
10
10
VII'S
SMP-10/SMP-11 LOW DROOP RATE/ACCURATE SAMPLE AND HOLD AMPLIFIERS
TYPICAL PERFORMANCE CURVES
CHANGE IN HOLD STEP vs S/H dV
AMPLITUDE CHANGE 1N
HOLD STEP vs INPUT VOLTAGE
dt
~
LloV OUT -
">
f=
9
'"
i
-1.0
!
ill
in
dV/dt (V/JiS)
~
3.0
dV7dt
=t=,LloVQUT '"
o
;I!I .
!
~ -0.1
I'
START WITH
- 0 VOLTS (30,.V) AT
100V!.uS
CH '" O.OO5.u f
1-0.01
8tH dV/dt (VOLTS/.uS)
0.1
1.0
10
8tH dV/dt (VOLTS/pS)
-~,L5~~----L---L---~---L---J+15
100
SMP-10
DROOP RATE
vs TEMPERATURE
SMP-11
DROOP RATE
vs TEMPERATURE
-90 0
-70 0
CH '" 5000 pF
-80 0
~
-700
~ -60
>
.3
w
~
r-~
II
+11110F\
o~
c:: -400
J;
"
ARROW INDICATES POSITIVE
II
IDA REGARDLESS OF CH
VOLTAGE POLARITY
1;
o
~
I
'"' -50
E
~
I
I
O~~
t
+11
-40
J;
0-
~ -30o
~ -20o
lOR
'"
80
60
ARROW INDICATES POSITIVE
lOR REGARDLESS OF CH
VOLTAGE POLARITY
1\
/
40
a -100
-5
- - I-
+5
-60 -40 -20
-
0
+10 0
40
60
80 100 120 140
+20 0
-60
40
20
0
20
-1
RECOMMENDED HOLD
CAPACITOA IS 5000pF
I-
"'
0
-100
80 100 120 140
-so
0
50
100
lSO
TEMPERATURE (OC)
GAIN ERROR
_ +3
~
HOLD
>
TA = 25°C
w
SAMPLE MODE
!
_5~oC
'" +2
~
0
"- "-
"'"
I
10V STep TO WITHIN ±10mV
OF fiNAL VALUE jO.l%)
14
60
LOGIC INPUT CURRENT
({
\
40
AMBIENT TEMPERATURE lOCI
ACQUISITION TIME
16
"\
f-
20
vs HOLD CAPACITOR
J J
_.
20
f..-'"
12
'\
-
V
0
/
AMBIENT TEMPERATURE
18
100
CH = 5000 pF
:i1
-1 0
10
INPUT BIAS CURRENT
vs TEMPERATURE
-60 0
-500
HOLD MODE
POWER SUPPLY REJECTION
+.
-10
[
[
12
10
~-
I
CH (nF, lnF '" 1000pF)
12~OC
0
I
~
6
-7
I
0
w
'~"
~
SAMPLE
+1
~
)l)
~ r--
C - - f---
25°C
~
VLC
=
O.OV (pIN 13)
{PI~ 14)1 V~L TAGE
LOGIC INPUT VOLTAGE
PAGE 12-10
-1
0
>
~
-2
~
RL'" 2.5k
-3
-10
-5
0
+5
INPUT VOLTAGE (VOLTS)
+1.
SMP-10/SMP-11 LOW DROOP RATE/ACCURATE SAMPLE AND HOLD AMPLIFIERS
TYPICAL PERFORMANCE CURVES
APERTURE TIME
vs CAPACITOR CHARGING
CURRENT DURING SAMPLING
250
lLUG
i
I
150
!
1/
V
60 0
mW
U
I
CURRENT
~
POWER DISSIPATION vs
FREQUENCY INPUT = Vpf< Sin ",t
500
mW
11K'
I
, I IIII
i~,rp"p~
I
lJJLJ{
•
-I SINK~NG
CURRENT
,
Ii
11
;
I111
V,N
10V Pk
(20V Pk·PkJ
~W-I
5V Pk
III
I I
I'
/
111I
I.V
APERTURE TIME
(TURN OFF DELAV
TO 50% CURRENT)
AS A FUNCTION OF
CURRENT
Pk
III
V
V[
1.0V Pk
(2V Pk-Pkl
TEST CONDITIONS
SAMPLE MODE
V+ = 15V
v- = -15V
VLC = GND
CH = O.OO5pF
INPUT CENTERED AROUND GROUND
11'1I1
I
~
2.5V
Pk
0
I'V
Pk·Pk)
0.3
1.0
10.0
50
1kHz
1MHz
100kHz
10,000
l!!
~
g 10.0
~
w
~ a
~
0
II
8.0
! ~o
2.0
f-
o
o2
~
HOLD M OOE
17
i",
•
10
SAMPLE MODE
T
IIIIIIII 1I,1111~ III 1m
100Hz
1kHz
10kHz
INPUT FREQUENCY
.-..-:: :::.r
100kHz
I
III
I
11111111
POWER DISSIPATION
,.
LIMITED BY
INPUT
FREQ
CIRCUIT RESPONSE
100
500
1
2
kHz
kHz MHz MHz
INPUT FREQUENCY
HOLD CAPACITOR
CHARGING CURRENT vs
INPUT OUTPUT VOLTAGE
=;+20
1000
w
L!lUIUI i~i'I~U"li mill
10Hz
10V Pk·Pk
kH,
12.0
u
PI<
OV
OUTPUT WIDEBAND NOISE vs
BANDWIDTH (0.1 Hz TO
FREQUENCY INDICATED)
Ro~~j~~LD ~6~J~ R~I~:MPLE ~~IDE
5V
2
POWER> 500mW
INPUT FREQUENCY
OUTPUT RESISTANCE
vs FREQUENCY
14,0
10kHz
2:
>"
II
0
CAPACITOR CHARGING CURRENT (mAl
MAXIMUM INPUT SIGNAL
AMPLITUDE vs FREQUENCY
10kHz
'MHz
100kHz
t
~·tttffij
1MHz
10MHz
BANDWIDTH
SAMPLE MODE
POWER SUPPLY REJECTION
~
~ ~f-t+H~~+*~~~k+~~~~~
15
§ 40 H+++IlIII-...w.ll4fU-4l.(WIJH~I1lII.d-l.l+!l~
~
PAGE 12-11
•
SMP·10/SMP·11 LOW DROOP RATE/ACCURATE SAMPLE AND HOLD AMPLIFIERS
SMP-10/SMP-11 ACQUISITION TIMES
ACQUISITION TIME
+10V to OV
ACQUISITION TIME
:"'10V to OV
ACQUISITION TIME
+1.0V to OV
ACQUISITION TIME
-100mV to bv
v
~
~~
ACQUISITION TIM.E
-1.0V to OV
I
I_
I
I
I
lp
000
APPLICATIONS INFORMATION
LOGIC CONTROL
ZERO SCALE NULL ADJUSTMENT
v+
v-
,-----.------'---0 OUTPUT
CURRENT TO CONTROL
SAMPLE/HOLD MODES
VLC = OV FOR TTL COMPATIBILITY
During the null adjustment, the amplifier should be switched
continuously between the "sample" and "hold" mode. The
error should be adjusted to read zero when the unit is in the
"hold" mode. In this way, both offset voltage errors and
charge transfer errors are adjusted to zero.
As shown in the Figure, the sample/hold mode control is ac·
compllshed by steering the current (11) through 01 or 02,
thus providing high-speed switching and a predictable logic
PAGE 12·12
SMP-10/SMP-11 LOW DROOP RATE/ACCURATE SAMPLE AND HOLD AMPLIFIERS
threshold. For TIL and DTL interface, simply ground VLC
(Pin 13). For CMOS, HTL and HNIL interface, the appropriate
threshold voltage, allowing for 2 diode drops for D1 and VSE
of Q3, should be applied to VLC .
For proper operation, the VLc (logic control) must always be
at least 3.5V below the positive supply and 2.0V above the
negative supply.
cN ( V)= 5 (pC) x 103
zs m
CH (pF)
-1
The hold capacitor should have very high inSUlation
resistance and low dielectric absorption. For temperatures
below 85 ·C, polystyrene capacitors are recommended,
while teflon capacitors are recomended for higher
temperature applications.
Sample and hold control voltage (S/H) must always be at
least 2.8V above the negative supply.
SIGNAL TRANSFER NONLINEARITY TEST CIRCUIT
GUARDING AND GROUNDING LAYOUT
The use of a ground plane is strongly recommended to
minimize ground path resistances. Separate analog and
digital grounds should be used, and it is advisable to keep
these two ground systems isolated until they are tied back
to the common system ground. Digital currents should not
flow back to the system ground through the analog ground
path.
3.5V~
LOCAL
ANALOG
GROUND
PULSE
GENERATOR
0
H
5I,.!SEC
L
I
~~SEC---l
•
......
Co
'7
Do
:IE
U)
HOLD CAPACITOR RECOMMENDATIONS
U)
The hold capacitor (C H) acts as a memory element and also
as a compensating capacitor for the sample and hold
amplifier. For stable operation, a minimum value of 2000pF
is recommended, with no limit set for the maximum value.
The devices have been internally trimmed for C H = 5000 pF.
Other values of C H will cause a zero scale shift, which can be
calculated from the following equation:
IE:
W
ii:
GAIN
:;
ERROR
fVourVIN)
Do
:IE
DIVERGENCE FROM STRAIGHT
LINE IS SIGNAL NONLINEARITY
"'
c
....
o
:z:
c
~
w
....
Do
:IE
"'
U)
PAGE 12-13
PMI
GAP-Ol
ANALOG SIGNAL PROCESSING
SUBSYSTEM
®
FEATURES
•
•
•
•
•
•
Low Zero Scale Error . . . . . . . . . . . . . . . . . . . . . .. 3.0mV
Low Droop Rate ........................ O.1mV/ms
Wide Bandwidth .......... . . . . . . . . . . . . . . .. 400kHz
Digitally Selected Signal Path
Uncommitted Comparator On Chip
Wide Application Versatility
• Synchronous Demodulator
• Absolute Value Amplifier
• Two-Channel s/H Amplifier
• Two-Channel Multiplexer with Gain
through the "MUX" is also possible. The GAP-01 operates
as a sample/hold amplifier in the hold mode when both input amplifiers are unselected. With the on-board comparator, a two-channel successive approximation analog-todigital conversion (ADC) system may be constructed. Combining a sign-magn'itude, digital-to-analog (DAC) converter
with the GAP-01 results in a four-quadrant multiplying DAC.
The GAP-01 contains all the functional devices needed to
perform synchronous demodulation or implement the absolute value function.
FUNCTIONAL DIAGRAM
GENERAL DESCRIPTION
Designed as a general-purpose analog processing subsystem, the GAP-01 combines many commonly used system
building blocks within a single integrated circuit. Being a
monolithic design, the GAP-01 offers significant performance and package density advantages over discrete
designs without sacrificing system versatility.
AMPLIFIER 14 NULL
The basic circuit versatility stems from the GAP-01's architecture. The circuit features two differential input transconductance amplifiers, two low-glitch current mode switches,
an output voltage buffer amplifier and a preciSion comparator.
COMPARATOR
V'
OUTPUT
.INPUT -INPUT
-INPUT
~_+!--o Yout
_INPUT
·INPUT
Both transconductance input amplifier outputs are switched
by current mode switches into the voltage follower output
stage, thus providing two digitally selectable signal paths
through the device. Gain through the two channels may be
different in both sign and magnitude with proper feedback
selection. An external capacitor provides loop compensation and doubles as a hold or "memory" capacitor when the
GAP-01 functions as a dual-channel sample/hold amplifier.
Offset voltage and charge transfer errors are actively trimmed
by using the "Zener Zap" trim technique. The output buffer
features an FET input stage to reduce droop rate error in S/H
applications. A bias current cancellation circuit minimizes
droop' error at high ambient temperature.
CHANNEL 8 0 - 4 - - - - 1
SWITCHES SHOWN FOR:
~o
CHANNELB 0
AMPLIFIER 8 NULL
CONTROL LOGIC
The inclusion of a precision comparator on chip increases
the GAP-01 's versatility and cost effectiveness in non-linear
or data conversion applications. The output high voltage
level is set by external resistors. This scheme maximizes
noise immunity and permits interface to all standard logic
families - TTL, DTL, and CMOS.
Several applications exploit the ability to select the signal
path through the GAP-01. As a two-channel multiplexer or
analog switch, the GAP-01 high input impedance offers advantages when switching high impedance signals. Gain
Manufactured under the following patent: 4,285,051
PAGE 12-14
ChA
ChB
OUTPUT
toC
0
0
1
1
0
1
0
1
Channel A
Indeterminate"
Hold Last Input
Channel B
"This condition will not damage the GAP-ol.
It will merely cause an unpredictable output.
GAp·01 ANALOG SIGNAL PROCESSING SUBSYSTEM
ELECTRICAL CHARACTERISTICS at Vs = ±15V, C H = 1000pF, T A = 25°C.
GAP01A1E
PARAMETER
SYMBOL
MIN
CONDITIONS
TVP
GAP01B/F
MAX
MIN
TYP
MAX
UNITS
"am" AMPLIFIERS A, B
Zero Scale Error
Vzs
2.0
3.0
3.0
6.0
mV
Input Offset Voltage
Vos
2.0
4.0
3.0
7.0
mV
Input Bias Current
18
so
150
80
250
nA
Input Offset Current
lOS
20
40
50
100
Voltage Gain
AV
18
25
10
25
V/mV
Common Mode
Rejection Ratio
CMRR
80
90
74
90
dB
Power Supply
Rejection Ratio
PSRR
dB
Slew Rate
±9V'; Vs'; ±18V
(Note 2)
Input Voltage Range
nA
86
96
76
96
±11.5
±12.0
±11.5
±12.0
V
0.5
Vips
80
dB
0.5
SR
Feedthrough Error
&V'N = 201/, DET = I, RST = 0
Acquisition Time to
0.1% Accuracy
ts
20V Step. AVCL = +1
41
Acquisition Time to
0.01% Accuracy
ts
20V Step, AVCL = +1
45
66
80
76
70
41
70
ps
pS
45
COMPARATOR
Input Offset Voltage
Vos
0.5
1.5
1.0
3.0
mV
Input Bias Current
18
700
1000
700
1000
nA
Input Offset Current
lOS
75
300
75
300
Voltage Gain
AV
Common Mode
Rejection Ratio
CMRR
Power Supply
Rejection Ratio
PSRR
2.0kn Pull·up Resistor to 5.0V (Note 2)
±9V'; Vs'; ±18V
Input Voltage Range
(Note 2)
Low Output Voltage
I sink '; 5.0mA, Logic GND = OV
7.5
3.5
7.0
V/mV
82
106
82
106
dB
dB
76
90
76
90
±11.5
±12.5
±11.5
±12.5
-0.2
0.15
0.4
-0.2
0.15
0.4
V
25
80
25
80
pA
12
45
12
45
mA
"OFF" Output
Leakage Current
Output Short
Circuit Current
Response Time
7.0
ISC
ts
nA
5
7.0
V
VH
Logic "0" Input Voltage
VL
150
150
2.0
ns
2.0
V
0.8
Logic "1"lnput Current
Logic "0" Input Current
V L = 0.4V
0.8
V
pA
0.02
1.0
0.02
1.0
1.6
10
2.0
10
0.02
0.07
T J = +25·C (Note 1)
Output Voltage Swing:
AmplifierC
RL = 2.5k
7.0
15
40
75
75-
nS
50
50
ns
RL = 2.5k
2.5
2.5
Vips
No Load
5.0
ts
Slew Rate: Amplifier C
ISY
NOTES:
1. Due to limited production test times the droop current corresponds to
junction temperature (Tjl. The droop current vs. time (after power-on)
curve clarifies this paint. Since most peak detectors (in usel are on for more
±12.5
7.0
15
mVims
±12.0
ISC
±11.5
0.1
±11.0
Switch Aperture Ti me
Power Supply Current
C
...I
o
:c
c
z
IU
Droop Rate
Switch Switching Time
ii:
~
~
C
MISCELLANEOUS
Short Circuit Current:
AmplifierC
en
a:
IU
5mV Overdrive, (Note 3)
2.0kn Pull-up Resistor to 5.0V
DIGITAL -INPUTS-RST, DET (See Note 3)
Logic "1" Input Voltage
•
40
7.0
5.5
V
8.0
than 1 second. PMI specifies droop rate for ambient temperature.
2. Guaranteed by design.
3. Channel A = "I", Channel B= "0".
PAGE 12-15
mA
mA
...I
!
GAP·01 ANALOG SIGNAL PROCESSING SUBSYSTEM
ELECTRICAL CHARACTERISTICS (V S =± 15V, eH = 1000pF, -55· e:5 TA:5 125· e for GAP01A & ~
T A:5 70·e for GAP01EP & FP.
GAP01 EX
& FJ(, and
o·e:5
PARAMETER
SYMBOL
GAP01A/E
MIN
TVP
MAX
CONDITIONS
MIN
GAP01B/F
TYP
MAX
UNITS
"gm" AMPLIFIERS A, B
Zero Scale Error
V zs
3.0
6.0
5.0
10
mV
Inpul Offset Voltage
Vos
4.0
7.0
6.0
12
mV
Input Bias Current
Ie
160
250
160
550
nA
Input Offset Current
los
30
100
30
150
Voltage Gain
Av
Common Mode
Rejection Ratio
CMRR
Power Supply
Rejection Ratio
nA
7.5
9.0
5.0
9.0
VlmV
10V" VCM " +10V
74
82
72
60
dB
PSRR
±9V" Vs" ±18V
80
90
70
90
dB
Input Voltage Range
VCM
(Note 2)
±11.0
±12.0
±10.5
±12.0
V
Slew Rate
SR
0.4
0.4
Vlp.s
Acquisition Time to
0.1% Accuracy
t.
60
60
p.s
20V Step, AVCL = +1:0
COMPARATOR
Input Offset Voltage
Vos
Input Bias Current
Ie
Input Offset Current
los
Voltage Gain
Av
2.0kn Pull-up Resistor to 5.0V (Note 2)
Common Mode
Rejection Ratio
CMRR
-10V " VCM" +10V
Power Supply
Rejection Ratio
PSRR
±9V" Vs " ±18V
Input Voltage Range
V CM
(Note 2)
Low Output Voltage
VOL
I sink " 5.0mA, Logic GND = 5.0V
"OFF" Output
Leakage Current
IL
VO UT=5V
Output Short
Circuit Current
Isc
VOUT= 5V
ts
5mV Overdrive. (Note 3)
2.0kn Pull-up Resistor to 5.0V
Response Time
2.0
2.5
2.0
5.0
mV
1000
2000
1100
2000
nA
100
600
100
600
nA
4.0
6.5
2.5
6.5
V/mV
80
100
80
92
dB
72
82
72
86
dB
±11.0
-0.2
6.0
±11.0
0.15
0.4
25
100
10
45
-0.2
6.0
200
V
0.15
0.4
V
100
160
p.A
10
45
mA
ns
200
DIGITAL INPUTS·RST, DET (See Note 3)
Logic "I" Input Voltage
VH
Logic "0" Input Voltage
VL
2.0
2.0
Logic "1" Input Current
IINH
VH =3.5V
0.02
1.0
LogiC "0" Input Current
IINL
V L = 0.4V
2.5
15
Droop Rate
VOR
T J = Max. Operating Temp. (Note 1)
1.0
10
Output Voltage Swing:
AmplifierC
VOP
RL =2.5k
Short Circuit Current:
AmplifierC
Isc
Switch Aperture Time
taE!:
75
75
ns
Slew Rate: Amplifier C
SR
RL = 2.5k
2.0
2.0
Vlp.s
Power Supply Current
ISY
No Load
5.5
V
0.8
0.8
V
0.02
1.0
p.A
2.5
15
p.A
1.0
10
MISCELLANEOUS
NOTES:
1. Due to limited production test times the droop current corresponds to
junction temperature (T j ). The droop current vs. time (after power-on)
curve clarifies this point. Since most peak detectors (in use) are on for more
±11.0
±12.0
6.0
12
40
8.0
±10.5
±12.0
6.0
12
6.5
V
40
10.0
than 1 second. PMI specifies droop rate for ambient temperature.
2. Guaranteed by deSign.
3. Channel A = "1", Channel B = "0".
PAGE 12-18
mA
mA
GAP-Ol ANALOG SIGNAL PROCESSING SU8SYSTEM
ABSOLUTE MAXIMUM RATINGS (Note 2)
Supply Voltage ................................... ± l8V
Power Dissipation .............................. 500mW
Input Voltage ................... Equal to Supply Voltage
Logie and Logic Ground
Voltage ...................... Equal to Supply Voltage
Output Short Circuit Duration ................. Indefinite
Amplifier A or B Differential Input Voltage .......... ±24V
Cmparator Differential Input Voltage
Input Voltage ......................... ±6.0V Indefinite
Input Voltage .......................... ±24.0V Pulsed
(Input Bias Current may degrade from large continuous
differential voltages)
Comparator Output Voltage ... Equal to Positive Supply Voltage
Hold Capacitor Short Circuit Duration ......... Indefinite
Storage Temperature ................. -65'C to +150'C
ORDERING INFORMATIONt
Vzs
(mV)
3.0
6.0
HERMETIC
MILITARY
INDUSTRIAL
GAP01AX'
GAP01BX'
GAP01EX
GAP01FX
Lead Temperature (Soldering 60 sec) ...•........• 300'C
Operating Temperature Range
GAP01 BX .......................... -55' C to + 125' C
GAP01FX ........................... -25'Cto+85'C
GAPOl EP .............................. O'C to +70'C
DICE Junction Temperature (T j ) ••••••• -65'C to +150'C
lEl·Pln DIP IXI
MAXIMUM AMBIENT
TEMPERATURE
FOR RATING
l00'C
l8-Pin DIP(P)
50'C
DERATE ABOVE
MAXIMUM AMBIENT
TEMPERATURE
10mW/'C
NOTES:
1. Maximum package power dissipation VB. ambient temperature.
2. Absolute ratings apply to both DICE and packaged parts. unless otherwise
noted.
PIN CONNECTIONS
PLASTIC
COMMERCIAL
CHANNELl
t
GAP01EP
GAP01FP
t.
CHANNa A
17
LOGIC GROUND
• Also available with MIL-STD-8838 processing. To order add 1883 as a suffix to
the part number.
t Ail listed parts are available with 160 hour burn-In. See Ordering Information.
Section 2.
NON·INVERTING
INPUT
II
INYI!IITING
INPUT(.\)
,---..r:=:-t..=
NON-INVERTING
INPUT(.\)
INVERTING
INPUTC"
DICE CHARACTERISTICS
1.
2.
3.
4.
5.
6.
7.
8.
9.
CHANNEL (8)
V+
OUTPUT
CH
(A) NULL
(A) NULL
INVERTING INPUT (A)
NON-INVERTING INPUT (A)
V-
10.
11.
12.
13.
14.
15.
16.
17.
18.
NON-INVERTING INPUT (8)
INVERTING INPUT (8)
(8) NULL
(8) NULL
COMPARATOR NON-INVERTING INPUT
COMPARATOR INVERTING INPUT
COMPARATOR OUT
LOGIC GND
CHANNEL (A)
DIE SIZE 0.090 X 0.095 Inch
Refer 10 Section 2 for additional DICE Informalton
PAGE 12-17
GAP-01 ANALOG SIGNAL PROCESSING SUBSYSTEM
--------------------------------
--------------------------
ELECTRICAL CHARACTERISTICS at Vs = ±15V. CH = 1000pF. T A = 25°C.
GAP-01N
PARAMETER
SYMBOL
CONDITIONS
LIMIT
UNITS
"gm" AMPLIFIERS A. B
Zero Scale Error
Vzs
6.0
mVMAX
Input Offset Voltage
Vos
7.0
mVMAX
Input Bias Current
18
250
nAMAX
Input Offset Current
lOS
75
nAMAX
Voltage Gain
Av
10
V/mVMIN
Common Mode
Rejection Ratio
CMRR
74
dBMIN
Power Supply
Rejection Ratio
PSRR
76
dBMIN
±9V';VS ±18V
Inpct Voltage Range
(Note1)
Feedthrough Error
~V'N ~
±11.5
20V. DET ~ 1. RST
~
0
VMIN
66
dB MIN
3.0
mVMAX
1000
nAMAX
COMPARATOR
Input Offset Voltage
Vos
Input Bias Current
'B
Input Offset Curren_t_ _ _ _ _ _ _I~o"'s_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
300
_ _ _ _ _ _ _ _ _nAMAX
_ __
Voltage Gain
Av
Common Mode
Rejection Ratio
CMRR
Power Supply
Rejection Ratio
PSRR
2.0kll Pull-up Resistor to 5.0V (Note 1)
±9V';V S ';±18V
Input Voltage Range
(Note 1)
Low Output Voltage
I SINK '; 5.0mA. Logic GND
~
5.0V
"OFF" Output
Leakage Current
Output Short
Circuit Current
Ise
3.5
V/mVMIN
82
dB MIN
76
dB MIN
±11.5
VMIN
0.4
-0.2
V MAX
VMIN
80
I'AMAX
45
7.0
mAMAX
mAMIN
DIGITAL INPUTS-RST. DET (See Note 3)
Logic "1" Input Voltage
VH
2.0
VMIN
Logic "0" Input Voltage
VL
0.8
V MAX
Logic "1" Input Current
'INH
VH~3.5V
1.0
I'AMAX
'INL
V L ~ 0.4V
10
I'AMAX
Droop Rate
VOR
TA ~ 25"C (See Note 2)
FJ~25"C
0.1
0.20
Output Voltage Swing:
AmplifierC
VOP
RL ~ 2.5k
±11.0
Short Circuit Current:
AmplifierC
Ise
Power Supply Current
ISY
Logic "0" Input Current
MISCELLANEOUS
40
No Load
NOTES:
1. Guaranteed by design.
2. Due to limited production test times the droop current corresponds to
junction tempe~ature (T J). The droop cu(rent VS. time (after power-on)
curve clarifies tHis point. Since most peak detectors (in use) are on for more
than 1 second. PMI specifies droop rate for ambient temperature (T A) also.
mV/ms MAX
mV/ms MAX
VMIN
7.0
mAMAX
mAMIN
9.0
mAMAX
The warmed-up (T A) droop current specification is correlated to the junction temperature (T J) value. PMI has a droop current cancellation circuit
which minimizes droop current at high temperatures.
3.
PAGE 12-18
DET~1.RST~O.
GAP·01 ANALOG SIGNAL PROCESSING SUBSYSTEM
TYPICAL ELECTRICAL CHARACTERISTICS at Vs = ±15V, CH = 1000pF, and T A = 25° C, unless otherwise noted.
GAP-01N
PARAMETER
SYMBOL
CONDITIONS
TYPICAL
UNITS
"gm AMPLIFIERS A, B
0.5
Slew Rate
SR
Acquisition Time
t.
0.1 % Accuracy, 20V step, AYCL = 1
41
I'S
Acquisition Time
t.
0.01 % Accuracy, 20V step, A YCL = 1
45
1'8
5mV Overdrive
2kO Pull-up Resistor to +5.0V
150
ns
ns
VII's
COMPARATOR
Response Time
MISCELLANEOUS
Switch Aperture Time
tae
75
Switching Time
ts
50
ns
Buffer Slew Rate
SRc
2.5
VII's
RL = 2.5kO
TYPICAL CHARACTERISTIC
SMALL SIGNAL OPEN LOOP
GAIN/PHASE vs FREQUENCY
ACQUISITION TIME vs
INPUT VOLTAGE STEP SIZE
90
DROOP CURRENT
vs TEMPERATURE
6O'---~-----r---r----'
TA = 25°C
'0
RL = 10kS1
UNITS AT OPERATING TEMPERATURE
cl '" 30pF
60
a
j
45
:""..............\k--,...;;;;:-t---I 90
z30
;;:
ffi
~
e.
"::;z
135 ~
'"
30
~ 20
«
180
J----+--
I
t----+..~"7IL...--t----I
I
w
a:
1;1
:Jl
it
I
'°r-~~~---+---t---1
-30
10
100
lk
10k
lOOk
1M
10M
10
FREQUENCY (Hz)
20
-75 -50 -25
25
50
100 125 150
en
a:
IU
u::
Go
LOGIC INPUT CURRENT vs
LOGIC INPUT VOLTAGE
HOLD MODE POWER SUPPLY
REJECTION vs FREQUENCY
POLARITY OF ERROR
MAY BE POSITIVE OR
NEGATIVE
..
+0$
ERROR (mV)
'"-
+5V
Q
+10V
80
r--....,.--.,.---,---....,.--...
r---+--+--l-
i-
60 ~=~I+;-;';5V;:;+1;;;V:-;S;;;,N;-;:;WTn)"':::~.t--~
:
Q
Z
lOGIC 1 _
CH = 1000pF
«
IU
....
Go
-5~'c
r- +2SOC
NEGATIVE SUPPLY
is
~
+12SOC
FREQUENCY 1Hz)
PAGE 12·19
I
LOGIC 0
CHANNELA = 1
CHANNEL B '" I)
o,':-o--=,-!,oO,---.l'-k--'L..Ok--,.!.OO-k-....'M
j
-
-2
20r-.--t--~--~--t-~~
I
-3
-2
I
LOGIC GROUND'" OV
I
I
«
Q
....
o
::t:
I I
TA = 2S C C
VIN = OV
!40
-1.0
75
::::i
'00
f-++-H-+-H-+-e-f-+-H-+-H-+-H--l
0
LEAKAGE CURRENT (nA)
:t!
+, 0
-5V
15
INPUT STEP (VOLTS)
AMPLIFIER CHARGE INJECTION
ERROR vs INPUT VOLTAGE
AND TEMPERATURE
-lOV
j
,/
L....-L_...L_.L.-l._..L_~W
1
II
I
I
-1
LOGIC INPUT VOLTAGE (VOLTS)
GAp·01 ANALOG SIGNAL PROCESSING SUBSYSTEM
TYPICAL CHARACTERISTICS
COMPARATOR INPUT BIAS CURRENT
VI DIFFERENTIAL INPUT VOLTAGE
+3
I
i... +.
Vs .1"6V
TA '" 25°C
I
1.0
I
INPUT CURRISNT
~rE:~~~~A
..
OTHER
.-'NPUT
AT -1OV
~
__ ?N~~R
AT OV
RL .. 2.kO
TO +5V
.........:
~
i
INPUT
AT +lOV
-16
-10
-6
0
+6
+10
INPUT VOLTAGE (VOLTS)
1.5
1.0
0.6
I
;;
z
TEST CONDITION:
CH .. lDODpF
AMPLIFIER A AND B
CONNECTED IN
GAIN
illz eo
~
+'
...
.1!
..gg
"
5
~
w
~
AMPLIFER A (BI OFF. INPUT. 20V Pk.pk
AMPUFIER B (BI ON, INPUT = OV
1.5
2.0
1
10
100
1k
10k 'OOk
FREQUENCY (Hz)
2.0
1M
10M
6.0
w 4V
8.0
10.0
12.0
1--+--l-4't'1.,--t---
1--1--+-
2V
1---+--+
!;
I!:
IV
I---t--.,.. I-+++---+--t---I
5 IV I--+-+---r-\
~~I--+---t--~~r--I---t--~
g
OV~-+--~~--r--r--+~
+6mV
I--j.,...-t-+-+-~r--t--i
~~~~o--U--~~~IOO~-'~~-~200~~260~-3W~
!oiw
i.
~
-
2V
I--+-+---t-\;
OV J-I-::j==t=t~~~~~::~
+5mV
!:--:,:"--:!:_~"""":=--:l::--=:-~
50
100
150
200
250 300
-.mV
-50
TIME (NANOSECONDS)
LARGE SIGNAL NON·INVERTING
RESPONSE
COMPARATOR OUTPUT
RESPONSE TIME
(2KII PULL·UP RESISTOR, TA = 25'C)
6V
OV
OV
TIME
(20~S/DIV.)
PAGE 12·20
-t5mV
III
~
IImV
>
.
-smvi;
OV
TIME (2OinIDIV.1
14.0
~
3V
TIME (NANOSECONDS)
LARGE SIGNAL NON·INVERTING
RESPONSE
4.0
5V , . . - - . _ . . . : : - , - - , . . . - - - , - - , - - ,
,.......,-..,.-..,..-"7",.,..-...,,~
J:;
o
V
10 - OUTPUT SINK CURRENT (mAl
g
20
,.,~ ~
..... ~"
w ·4V
'~
so
1.0
u
~
COMPARATOR RESPONSE TIME vs TEMPERATURE
6V
I
TA·25"C
~'00
"
0,5
0
INPUT VOLTAGE (mV)
CHANNEL TO CHANNEL ISOLATION
vs FREQUENCY
120
0
~
I
\
+16
-
1!g0.2
o
>
u
J /
00.4
\
I
-I
!;
TO +5V
2
,.
~
\-~L = 1.0kn
o
OTHER
~ ~
~ 0.6
I I
~ 0
;
0.8
'OV
iil
~
TA = 25°C
INVERTING INPUT" VIN
NON·INVERTING INPUT
~
~
VS" ±15V
I
\
!!!
1
i +'
;
COMPARATOR OUTPUT VOLTAGE
vs OUTPUT CURRENT
AND TEMPERATURE
COMPARATOR TRANSFER
CHARACTERISTIC
TIME l50ns/DIV,J
GAP-01 ANALOG SIGNAL PROCESSING SUBSYSTEM
TYPICAL CHARACTERISTICS
COMPARATOR OUTPUT
RESPONSE TIME
SETTLING TIME FOR
+ 10V TO OV STEP INPUT
SETTLING TIME FOR
-10V TO OV STEP INPUT
(2KO PULL·UP RESISTOR, TA = 2S'C
0\1
5V
~ 4V
+5mV
~3V
OmV
0
>
~2V
-5mV
~1V
0
ov
TIME
TIME (SOns/OIV,)
OUTPUT SWING OF
COMPARATOR VI
SUPPLY VOLTAGE
I.
~0 I.
""g
10
~
~
8
l5
I-
::>
-6
~~
Q
I
~-14
-I.
~
_.
5
iO
15
+--
12
SUPPLY VOLTAGE +V AND -V (VOLTS)
INPUT LOGIC RANGE
SUPPLY VOLTAGE
I.
15
12
SUPPLY CURRENT VI
SUPPLY VOLTAGE
VB
f------j-----+---- ~IN ~ V+ FOR
-6SoC .;; TA
0.;;:
+l25"C
~~ 6~=i~~==1====l====~==~
~~----.__t--.-_+_
V
2
g
-55~C
~_ -61---~":~,L
,
,
~~
~ -10
f--
V
_
-
12
15
SUPPLY VOLTAGE +V AND -V (VOLTS)
RL = 10k ,-
,}
-
I
12
SUPPLY +V AND -V (VOLTS)
PAGE 12-21
15
I.
/'
/X
= 2k
III
II:
W
ii:
::;
a..
::i!
<
....c
o
::J:
C
Z
~o"'~/ /
~..
- ""V
//'
" /'
II
I.
15
(VOLTS)
OUTPUT VOLTAGE SWING VI
SUPPLY VOLTAGE (SINGLE
SUPPLY OPERATION)
,"/
18
-v
.."
--55"C
+2SoC
+12S"C
+l25"C -
~
4
12
SUPPLY VOLTAGE +V AND
",1/,," " / RL
_~
I
-18
+12S"C~
~
-I.
'"
f-o
~
-14
f--- f----- 1----
RL CONNECTOR TO V = %V+
j----------
+25'C
+2S"C
-=
32
~~~~~----~----+_----r---_1
~
-5S"C
~
--6
,.
.I'
14~~-----+-----+--~~-----1
u
.---- r-------
t-....
SUPPLY VOLTAGE +V AND -V (VOLTS)
I. r:::::::r:==1=-T""=-""T~:::::Zl
~ 10
-2
-14
~
15
I.
+25"C
5S"C
-10
I--.--....~
4
~.
po""
2
-}
+25'C---- -
-
..&:J!P'
"
+l25"C
f--
~
~
+2S C
-'
...--:
~
~>;ii<""+I25'C-
~
- ......~~-55<>C
-10
-RL-l0k
10
-
-
I---
0
I.
~~
14
-55'C .-
r-
-2
w
":::z
'~
';.,,;e ~
~ +125~C
OUTPUT VOLTAGE SWING VI
SUPPLY VOLTAGE (DUAL
SUPPLY OPERATION)
A AND B INPUT RANGE VI
SUPPLY VOLTAGE
,
,
,
- - - - - f--
~
0\1
(20~/DIV.)
<
....a..W
::i!
AL
=
<
10k
RL=2k~
12
16
20
24
28
32
SUPPLY VOLTAGE +V AND -V (VOLTS)
36
III
GAP·01 ANALOG SIGNAL PROCESSING SUBSYSTEM
TYPICAL CHARACTERISTICS
AMPLIFIER "A" OR "a"
VOLTAGE TO CURRENT
TRANSFER FUNCTION
(VIN valCH)
INPUT RANGE OF LOGIC
GROUND va SUPPLY VOLTAGE
18
~0 I.
~
e
12
z
0
""uc;
~
0
w
,...F--H-t--j----j-
I--l--H--+-++
-2
...
+_
--y+~,~~~~~~~-~~
..v
~r
1--b-i'9i11111L..o,,!!,,+- +26'C-55'C
,"'g."'F-f--- +125'C
:>
g
600
--1
-++--+-- 1-'-----
'y
:>
~ -14
'----r
" -200
-400
-18
12
SUPPL V VOLTAGE +V AND
16
-v
A
.Y
-_
vII
>=1==
-600
-0.6
18
1
J
~I-
Ki.o""
~
t
ttill;;;;b::j=t:-1:±'
~E1WE~N ~~E ~IN~S
+l25°C~I- ~
I
(55th
1 HI
1
ACCEPTABLE GROUND
PIN POTENTIAL IS
I
+25°C
200
+25'C+-I+1_ ~--j--+--I
"zcc -10 l--f""!I!!""h.b-I-'§ ~ -55'~
">--6
+125°C
(VOLTS)
1/
-0.4
L.... lIP
ft1
I
OIIP.m
''''It
10lIl1
..
-0.2
0.0
0.2
VIN - - . (VOL TSI
'OUT
iour"iOOii"
D••
D••
APPLICATION CIRCUITS
GAP·01 WITH POSITIVE AND NEGATIVE GAINS
GAp·01 IN UNITY GAIN (+ 1) CONFIGURATION
CHANNElAJ
CHANNEL B
v+
v+
v-
v-
".
CHANNEL A
INPUT
CHANNEL A
INPUT
OUTPUT
",
CHANNEl. B
INPUT
".
CHANNEL B
INPUT
CHANNEL B
PAGE 12-22
OUTPUT
~~I-4-o
".
GAp·01 ANALOG SIGNAL PROCESSING SUBSYSTEM
ALTERNATE GAIN CONFIGURATION
R,
GAP·01
CHANNEL A
OUTPUT
INPUT
>-,,-+--+--0
R,
IF BOTH CHANNEL A AND CHANNEl B HAVE THE SAME POSITIVE VOLTAGE
GAIN, A SINGLE VOLTAGE DIVIDER SETS THE GAIN FOR BOTH CHANNELS.
CHANNEL B
INPUT
R.
R,
c,
CHANNEL B
I1000PF
ABSOLUTE VALUE CIRCUIT WITH POLARITY PROGRAMMABLE OUTPUT
ABSOLUTe VALUE AMPLIFIER
INPUT
~ o-~-------------------------------,
.,v
OUTPUT
II
III
II:
POLARITY
W
CONTROL
*
ii:
:::i
IL
::Ii
CHANNEL B
SIGNAL
TRANSISTOR INCREASES COMPARATOR GAIN
c
o
o
:c
o
z
c
...I
TRACE 1:
TRACE 1:
INPUT SIGNAL
TRACE 2: CHANNEL A/CHANNEL B
CONTROL SIGNAL
INPUT SIGNAL
TRACE 2: CHANNELAlCHANNEL B
CONTROL SIGNAL
W
...I
IL
TRACE 3: OUTPUT. POLARITY CONTROL
SIGNAL'" 1
PAGE 12-23
TRACE 3: OUTPUT. POLARITY CONTROL
SIGNAL'" 0
::Ii
C
III
GAP,01 ANALOG SIGNAL PROCESSING SUBSYSTEM
APPLICATION CIRCUITS
TWO·CHANNEL SAMPLE/HOLD AMPLIFIER
5
'00
6
+15V
-15V
18
10K
GAP·01
A,
INPUT A
0-"'''''+-.....-1-1
1K
A,
1K
A,
11
1K
INPUTB
15
10
0------......:-=+-1
14
CHANNEL A GAIN =
- ~=
A,
-10
16
CH
CHANNEL 8 GAIN =1 + ~ =2
500PFl
CHANNEL BJ CHANNEL A
SAMPLE/HOLD
0------1,..;.:-L.:;.;./
TRACE 1: INPUT SIGNAL B ItV/DIV.1
TRACE 2: INPUT SIGNAL A (O.5V/DIV.)
TRACE 1: INPUT SIGNAL B (lV/DIV.)
TRACE 3: CHANNEL A/CHANNEL B
CONTROL SIGNAL (5V/DIV.J
TRACE 2: SAMPLE/HOLD (5V/DlV.J
CONTROL SIGNAL
TRACE 4: OUTPUT WITH SAMPLE/HOLD
TRACE 3: PUTPUl SIGNAL 12V/DIV.J
CHANNEL AlCHANNEL B '" "'"
= "'" (5V/DIV.)
DIGITAL GROUND CONNECTION FOR
SINGLE SUPPLY OPERATION
LOGIC LEVEL TRANSLATION FOR
GAP-01 SINGLE SUPPLY OPERATION
V+ = 15V
V+"' 15V
A1 .. 3.3kSl
TO GAP"()l
R = 5.1kn
t-----. CONTROL.
LOGIC
17
DIG
GND
1...-_ _ _---1
GAP·01
~
R2=390n
ITT~
~
OPEN
COLLECTOR
R3
z
V
LOGIC HIGH VOLTAGE = 4.4V
LOGIC LOW VOLTAGE = l.58V
PAGE 12-24
1kn
GAP-01 ANALOG SIGNAL PROCESSING SUBSYSTEM
APPLICATION CIRCUITS
FOUR QUADRANT MULTIPLYING DAC
A INPUT o-.,...-,~-I--+-I-IY
REF
INPUT
DAC·210
OUTPUT
AX.
SIGN
BIT
B1
810
..!!..- 810
B INPUT
III
PAGE 12-25
GAP·01 ANALOG SIGNAL PROCESSING SUBSYSTEM
APPLICATION CIRCUITS
SYNCHRONOUS DEMODULATION OF LVDT SIGNAL
2K
DISPLACEMENT
10K
t~E~~~:::~T~G
BUFfEReD
Lvar
SIGNAL
MODEL E1000
r - - -----.
IL.YDT
R1
. .~''----""",IV'----H
I
TEST)
( POINT
I
(j)
1
i
I
I
I
I
I
I
(
TEST)
P@T
r--------;
i
~----~~-+----~i~
L _____ .....J
1
+15V
SYNCHRONOUS
DEMODULATOR
OUTPUT
I
13
i---~;;ll
11&
I
I
4.7K
16 1
1
1
10K
,%
'---/-/-/-/--:!/)
10K
1.5K
/ / / SYNCHRONOUS
1.5K
SQUARED
lVDT
EXCITATION
(TEST~OINT)
O.l"F
10
20K
C
,%
5V
;tV
-
~
EST
POINT
@
)
I
---~-
lA
I.
ov
.1
I
-
3A
3B
FILTERED
DC
OUTPUT
•
,
-
-l
~
I ov
I
~V
I
LVDr SINEWAVE EXCITATION (TEST POINT 11 -2V/DIV.
GAP..Ql COMPARATOR OUTPUT (TEST POINT 3) -5V!DIV.
TRACE 2:
BUFFERED LVDr OUTPUT AT GAP..(Il INPUT (TEST POINT 2)
O.5V/DIV.
TRACE 3A:
LVDT SIGNAL AFTER GAP-Ol SYNCHRONOUS DEMODULATION
(TEST POINT 4) -D.5V/DIV.
DC OUTPUT LEVEL INDICATING LVDT CORE POSITION (TEST
POINT 5) O.5V/DIV.
-
-~
I
"
,
TRACE lA:
TRACE 18:
~pSl
OV
1
_
I
'
TRACE 3B:
PAGE 12-26
GAp·01 ANALOG SIGNAL PROCESSING SUBSYSTEM
APPLICATION INFORMATION
CAPACITOR GUARDING AND GROUND LAYOUT
CAPACITOR RECOMMENDATIONS
The external capacitor (CH) serves as the compensation
capacitor and hold capacitor in sample/hold applications.
Stable operation requires a minimum value of 500pF. Larger
capacitors may be used to lower droop rate errors, but acquisition time will increase and bandwidth decrease.
The capacitor should have very high insulation resistance
and low dielectric absorption. For temperatures below
85·C, a polystyrene capacitor is recommended, while a
Teflon capacitor is recommended for high temperature en·
vironments.
Ground planes are recommended to minimize ground path
resistance. Separate analog and digital grounds should be
used. The two ground systems are tied together only at the
common system ground. Avoid digital currents returning to
the system ground through the analog ground path.
The CH terminal (Pin 4) is a high-impedance point since a
transconductance amplifier is used as the input amplifier.
To minimize gain errors and maintain the GAp·01 's inherently low droop rate, guarding Pin 4 is recommended.
COMPARATOR
The comparator output high level (YOH) is set by external
resistors. It's possible to optimize noise immunity while interfacing to all standard logic families - TTL, DTL, and
CMOS. Figure 1 shows the comparator output with external
and
values
'evel setting resistors. Table I gives typical
for common circuit conditions.
R1 R2
With the comparator in the low state (VoLl, the output stage
will be required to sink a current approximately equal to
Ve/R1'
NON·INVERTING
COMPARATOR INPUT
Vc
LOGIC CONTROL
The input transconductance amplifier outputs are switched
by the digital logic signals channel A and channel B. Two
signal paths through the GAP-01 are possible.
The logic threshold voltage is 1.4 volts when digital ground
is at zero volts. Other threshold voltages (VTH ) may be
selected by applying the formula:
VTH ~ 1.4V + Digital Ground Potential.
INVERTING
COMPARATOR INPUT
DIGITAL
Figure 1.
GND
Table I.
5
R2
VOH R,
3.5 2.7K 6.2K
5
5.0 2.7K
15
3.5 4.7K 1.5K
15
5.0 4.7K 2.4K
Vc
Operating the digital ground at other than zero volts does in·
fluence the comparator output low voltage. The VOL level is
Ve
7.5 7.5K 7.5K
15
10.0 7.5K 15K
:E
cC
C
...J
o
:t
C
Z
cC
W
...J
a.
R1~-
Isink
:E
cC
en
00
15
W
ii:
:::i
a.
For proper operation, digital ground must always be at least
3.5V below the positive supply and 2.5V above the negative
supply. The logic signals must always be at least 2.8V above
the negative supply.
v-
en
II:
r-------~----ov+
R2~R1(~)
---1
VO H
OR
CHANNEL B
DIGITAL
GROUND
The maximum comparator high output voltage (VOH ) should
be constrained to:
VoH(max) < V + -2V
PAGE 12-27
--------------
CURRENT 10
CONTROL MODES
GA...·01 ANALOG SIGNAL PROCESSING SUBSYSTEM
APPLICATION INFORMATION
OFFSET VOLTAGE ERROR ADJUSTMENT
reference to digital ground and will follow any changes in
digital ground potential:
Offset voltage through either channel A or channel B may be
nulled with an externall00kO potentiometer.
VOL .. 0.2V + Digital Ground Potential.
ZERO SCALE ERROR ADJUSTMENT
For sample/hold applications the zero scale error (Vos plus
charge injection error) can be adjusted to zero. With the in·
put to each channel equal to zero, the GAP'()l is switched
between the sample mode (either channel A or channel B
active) and the hold mode (channel A - 1, channel B = 0).
The output is adjusted to read zero when the unit is in the
hold mode.
The Vzs trim circuit is identical to the Vos trim circuit.
PAGE 12-28
ANULL
B NULL
BAP'()1
PKO-Ol
PMI
MONOLITHIC PEAK DETECTOR
WITH RESET AND HOLD MODE
FEATURES
• Monolithic Design for Reliability and Low Cost
• Settling Time
20V Step to 0.1% ............................. 411'S
• High Slew Rate .............................. 0.5v/I'S
• Low Droop Rate
T A = 25 0 C ............................... 0.1mVlmS
T A = 125 0 C .............................. 10mVlmS
• Low Zero Scale Error .......................... 3.0mV
• Digitally Selected Hold and Reset Modes
• Reset Voltage Buffer Amplifier
• Reset to Posilive or Negative Voltage Levels
• Logic Signals TTL and CMOS Compatible
• Uncommitted Comparator on Chip
• Wide Differential Input Voltage Range ........... ±24V
• Convenient 2 Supply Operallon ................. ±15V
Many system functions are included in the PKD-01. The
external hold capacitor is resettable to any voltage within the
output buffer input voltage range. The analog reset voltage is
applied through a high impedance, switched "gm" amplifier.
The reset buffer amplifier, B, may operate as a inverting or
non-inverting gain stage.
Through the DET control pin, new peaks may either be
detected or ignored. Detected peaks are presented as positive output levels. Positive or negative peaks may be detected
without additional active circuits since amplifier A can operate as an inverting or non-inverting gain stage.
An uncommitted comparator provides many application
options. Status indication and logic shaping/shifting are typical examples.
FUNCTIONAL DIAGRAM
+IN
L~~~
-IN
OUTPUT
V+
v-
III
0-"'+--1)1-----'
9c
Innovative design techniques were developed to maximize
the advantages monolithic technology presented. Transconductance (gm) amplifiers were chosen over conventional
voltage amplifier circuit building blocks. The "gm amplifiers
simplify internal frequency compensation, minimize acquisition time and maximize circuit accuracy. The gm amplifier
outputs are easily switched by low glitch current steering
circuits. The steered outputs are clamped to reduce charge
injection errors upon entering the peak hold mode or exiting
the reset mode. The inherently low zero scale error, is
reduced further by active "Zener-Zap" trimming to optimize
overall accuracy.
~
OUTPUT
-IN
+1.
W
ii:
::::i
II.
:::E
-IN
CC
+IN
RST
c
Manufactured under the following patent: 4,285,051
PAGE 12-29
o-'
:l:
C
Z
CC
o--'-!---I
RST
The output buffer amplifier features an FET input stage to
reduce droop rate error during lengthy peak hold periods. A
bias current cancellation circuit minimizes droop error at
high ambient temperatures.
II.
UI
II:
o
o
w
DEI OPERATIONAL MODE
0
1
PEAK DETECT
PEAK HOLD
-,--,-~-"".
o
Ifldelerminate
-'
:::E
II.
SWITCHES SHOWN FOR:
RST = "0", DET="O"
CC
UI
PKD·01 MONOLITHIC PEAK DETECTOR WITH RESET AND HOLD MODE
ABSOLUTE MAXIMUM RATINGS (Note 2)
Supply Voltage ....•...........•.•.•...••••.•••••. ±18V
Power Dissipation .............................. 500mW
Input Voltage... •••• • ••• •• • •• • •• Equal to Supply Voltage
Logic and Logic Ground
Voltage ••••••••••••••••••..•• Equal to Supply Voltage
Output Short Circuit Duration ••.......•....... Indefinite
Amplifier A or B Differential Input Voltage .....••••• ±24V
Comparator Differential Input Voltage
Input Voltage ...•..•.......••.....•... ±6.0V Indefinite
Input Voltage •.....•....•••••••..••.••• ±24.0V Pulsed
(Input Bias Current may degrade from large continuous differential voltages)
Comparator Output Voltage .. Equal to Positive Supply Votage
Hold Capacitor Short Circuit Duration •.•.•..•.. Indefinite
Storage Temperature ••••.•...•..•....•. -65'C to +150'C
Lead Temperature (Soldering 60 sec) .•.•••.•••.••• 300'C
Operating Temperature Range
PKD01AY, PKD01BY ..•............•.. -55'C to +125'C
PKD01EY, PKD01FY ................... -25'C to +85'C
PKD01EP, PKD01FP ..................... O'C to +70'C
Dice Junction Temperature ..•.•.•••.•.. -65'C to +150'C
MAXIMUM AMBIENT
TEMPERATURE
FOR RATING
DERATE ABOVE
MAXIMUM AMBIENT
TEMPERATURE
14-Pin DIP (V)
8O"C
10mW/"C
14-Pin DIP (P)
5O"C
6mW/"C
NOTES:
1.
2.
Maximum package power dissipation VB. ambient temperature.
Absolute ratings apply to both DICE and packaged parts unless
otherwise noted.
ELECTRICAL CHARACTERISTICS at Vs = ±15V, C H = 1000pF, T A = 25·C.
PKD01AiE
PARAMETER
SYMBOL
MIN
CONDITIONS
PKD01B/F
TVP
MAX
MIN
TVP
MAX
UNITS
"gm" AMPLIFIERS A, B
Zero Scale Error
Vzs
2.0
3.0
3.0
6.0
mV
Input Ollset Voltage
Vos
2.0
4.0
3.0
7.0
mV
Input Bias Current
Ie
80
150
60
250
nA
Input Ollset Current
los
20
40
20
75
Voltage Gain
Av
Common Mode
Rejection Ratio
CMRR
Power Supply
Rejection Ratio
nA
18
25
10
25
V/mV
10V" VCM ,,+10V
80
90
74
90
dB
PSRR
±9V" VS" ±18V
86
96
76
96
dB
Input Voltage Range
VCM
(Note 1)
±11.5
±12.0
±1'.5
±12.0
V
Slew Rate
SR
0.5
VIps
Feedthrough Error
0.5
66
aV IN = 20V. DET = 1. RST = 0
80
Acquisition Time to
0.1 % Accuracy
ta
20V Step. AVCL = +1
41
Acquisition Time to
0.01% Accuracy
ta
20V Step. AVCL = +1
45
66
70
80
41
dB
70
p.s
p's
45
COMPARATOR
Input Ollset Voltage
Vos
0.5
1.5
1.0
3.0
mV
Input Bias Current
Ie
700
1000
700
1000
nA
Input Ollset Current
los
75
300
75
300
Voltage Gain
Av
2.0kfl Pull-up Resistor to 5.0V (Note 1)
Common Mode
Rejection Ratio
CMRR
-10V " VCM" +10V
Power Supply
Rejection Ratio
PSRR
±9V" Vs" ±18V
Input Voltage Range
VCM
(Note 1)
Low Output Voltage
VOL
I sink " 5.0mA. Logic GND = 5.0V
NOTES:
1.
Notes guaranteed by design.
2.
Due to limited production test times the droop current corresponds to
junction temperature (TJ)' The droop current vs. time (after power-on)
curve clarifies this point. Since most peak detectors (in use) are on for
more than 1 second. PMI specifies droop rate for ambient temperature
3.
PAGE 12-30
nA
5
7.5
3.5
7.5
VlmV
82
106
82
106
dB
dB
76
90
76
90
±11.5
±12.5
±".5
±12.5
-0.2
0.15
-0.2
0.15
0.4
V
0.4
V
(T A) also. The warmed-up (T A) droop current specification is correlated to the junction temperature (TJ) value. PMI has a droop current
cancellation circuit which minimizes droop current at high temperature. Ambient (T A) temperature specifications are not subject to production testing.
DET = 1. RST = O.
PKD·01 MONOLITHIC PEAK DETECTOR WITH RESET AND HOLD MODE
ELECTRICAL CHARACTERISTICS
at VS= ±15V, C H = 1000pF, TA = 25°C. (Continued)
PKD01A1E
PARAMETER
SYMBOL
MIN
CONDITIONS
"OFF" Output
Leakage Current
IL
VOUT=SV
Output Short
Circuit Current
Isc
VOUT=SV
Response Time
t,
SmV Overdrive, (Note 3)
2.0kO Pull·up Resistor to S.OV
7.0
PKD01B/F
TVP
MAX
2S
80
12
4S
MIN
7.0
1S0
TVP
MAX
2S
80
I'A
12
4S
mA
UNITS
ns
150
DIGITAL INPUTS·RST. DET (See Note 3)
Logic "1" Input Voltage
VH
"a" Input Voltage
VL
Logic
2.0
2.0
V
0.8
0.8
V
/loA
/loA
Logic "1" Input Current
IINH
VH =3.SV
0.02
1.0
0.02
1.0
"a" Input Current
IINL
VL = 0.4V
1.6
10
1.6
10
Droop Rate
VOR
T J =2So C
(See Note 2)
T A =2S o C
0.01
0.02
0.07
0.15
0.01
0.03
0.1
0.20
Output Voltage Swing:
AmplifierC
vOP
RL = 2.5k
Logic
MISCELLANEOUS
±11.5
±12.5
±11.0
mV/ms
±12.0
V
Short Circuit Current:
AmpliflerC
ISC
Switch Aperture Time
taE!
75
75
Switch Switching Time
ts
SO
50
ns
Slew Rate: Amplifier C
SR
RL = 2.5k
2.5
2.5
VII's
Power Supply Current
ISY
No Load
5.0
7.0
ELECTRICAL CHARACTERISTICS
(V S
15
40
7.0
7.0
15
40
mA
ps
6.0
9.0
= ±15V, CH = 1000pF, -55° C:5 T A:5 125° C for PKD01AY, PKD01 BY, -25
mA
0
C:5 T A:5
II
85° C for PKD01 EY, PKD01 FY and 0° C :5 T A:5 70° C for PKD01 EP, PKD01 FP).
PKD01A1E
PARAMETER
SYMBOL
CONDITIONS
MIN
PKD01B/F
TVP
MAX
MIN
TVP
MAX
UNITS
"gm" AMPLIFIERS A, B
Zero Scale Error
VZS
3.0
6.0
5.0
10
mV
Input Offset Voltage
Vos
4.0
7.0
6.0
12
mV
Input Bias Current
Ie
160
250
160
550
nA
Input Offset Current
los
30
100
30
150
nA
Voltage Gain
Av
Common Mode
Rejection Ratio
Power Supply
Rejection Ratio
CMRR
10V:S VCM :S+10V
7.5
9.0
5.0
9.0
V/mV
74
82
72
60
dB
til
a:
W
ii:
::::i
A.
:E
00(
C
..I
PSRR
±9V:S Vs:S ±18V
(Note 1)
Input Voltage Range
VCM
Slew Rate
SR
Acquisition Time to
0.1'110 Accuracy
t.
60
90
70
90
±11.0
±12.0
±10.5
20V Step, AVCL = +1
0
dB
%:
C
Z
±12.0
V
0.4
0.4
VII'S
60
60
I'S
00(
W
..I
A.
:E
00(
til
COMPARATOR
Input Offset Voltage
Vos
Input Bias Current
Ie
Input Offset Current
los
2.0
2.5
2.0
5.0
1000
2000
1100
2000
nA
100
600
100
600
nA
mV
Voltage Gain
Av
2.0kO Pull-up Resistor to 5.0V
4.0
6.5
2.5
6.5
V/mV
Common Mode
Rejection Ratio
CMRR
-10V:S V CM:S +10V
80
100
80
92
dB
Power Supply
Rejection Ratio
PSRR
±9V:S Vs:S ±18V
72
82
72
88
dB
Input Voltage Range
V CM
(Note 1)
Low Output Voltage
VOL
Isink:S 5.0mA, Logic GND = 5.0V
±11.0
PAGE 12-31
-0.2
±11.0
0.15
0.4
-0.2
V
0.15
0.4
V
PKD·01 MONOLITHIC PEAK DETECTOR WITH RESET AND HOLD MODE
ELECTRICAL CHARACTERISTICS (Vs = ±15V, C H = 1000pF, -55°C S T AS 125°C for PKD01AY, PKD01BY, -25°C ST AS
85°C for PKD01EY, PKD01FY and O°C S T A S 70°C for PKD01EP, PKD01FP). (Continued)
PKD01A1E
PARAMETER
SYMBOL
MIN
CONDITIONS
"OFF" Output
Leakage Current
Output Short
Circuit Current
6.0
ISC
5mV Overdrive.
2.0kn Pull-up ReSistor to 5.0V
t,
Response Time
TYP
PKD01B/F
MAX
25
100
10
45
MIN
TYP
6.0
200
MAX
UNITS
100
180
p.A
10
45
mA
ns
200
DIGITAL INPUTS-RST. DET (See Note 3)
Logic "I" Input Voltage
VH
Logic "0" Input Voltage
VL
Logic "I" Input Current
IINH
Logic "0" Input Current
IINL
Droop Rate
2.0
2.0
V
0.8
0.8
V
0.02
1.0
0.02
1.0
p.A
V L = 0.4V
2.5
15
2.5
15
p.A
VOR
T J = Max. Operating Temp
T A = Max. Operating Temp.
DET = 1, Note 2
1.2
2.4
10
20
3.0
6.0
15
20
mV/ms
Output Voltage Swing:
AmpliflerC
VoP
RL =2.5k
Short Circuit Current:
AmplifierC
Isc
MISCELLANEOUS
Switch Aperture Time
tap
Slew Rate: Amplifier C
SR
Power Supply Current
ISY
±11.0
6.0
±12.0
12
±10.5
40
12
V
40
mA
75
75
ns
RL = 2.5k
2.0
2.0
VII'S
No Load
5.5
8.0
NOTES:
1.
Guaranteed by design.
2.
Due to limited production test times the droop current corresponds to
iunction temperature (T JI. The droop current vs. time (after power-onl
curve clarifies this point. Since most peak detectors (in use) are on for
more than 1 second. PMI specifies droop rate for ambient temperature
3.
ORDERING INFORMATIONt
PIN CONNECTIONS
25°C
Yzs
(mY)
6.0
±12.0
PACKAGE
14 PIN DIP
HERMETIC
PLASTIC
OPERATING
TEMPERATURE
RANGE
6.5
10.0
mA
(TAl also. The warmed-up (TAl droop current specification is correlated
to the junction temperature (T J) value. PMI has a droop current cancel Is·
tlon circuit which minimizes droop current at high temperature. Ambient
(T A) temperature specifications are not subject to production testing.
DET=I,RST=O.
DET
LOGICGND
3
6
3
6
3
6
PKOO1AY'
PKOO1BY'
PKOO1EY
PKOO1FY
PKOO1EP
PKOO1FP
MIL
MIL
INO
INO
COM
COM
COMP.OUT
-INC
+IN
c
14-PIN HERMETIC DIP
(V-Suffix)
EPOXVB-DIP
• Also available with MIL-STD-883B Processing. To order add 1883 as a suffix
to the part number.
t All listed partsar. available with 160 hour burn-in. See Ordering Information,
Section 2.
PAGE 12-32
(P-Sufflx)
PKD·01 MONOLITHIC PEAK DETECTOR WITH RESET AND HOLD MODE
DICE CHARACTERISTICS
1.
2.
3.
4.
5.
8.
7.
8.
RST (RESET CONTROL)
V+
OUTPUT
CH (HOLD CAPACITOR)
INVERTING INPUT (A)
NON-INVERTING INPUT (S)
VNON-INVERTING INPUT (S)
9.
10.
11.
12.
13.
14.
INVERTING INPUT (S)
COMPARATOR NON-INVERTING INPUT
COMPARATOR INVERTING INPUT
COMPARATOR OUTPUT
LOGIC GROUND
DET (PEAK DETECT CONTROL)
A.S (A) NULL
C.D(S) NULL
0.090 Inch x 0.095 Inch
Reier to Section 2 lor additional DICE Information.
ELECTRICAL CHARACTERISTICS at Vs = ±15V, CH = 1000pF, T A = 25°C.
PKD-01N
PARAMETER
SYMBOL
CONDITIONS
LIMIT
UNITS
"11m" AMPLIFIERS A, B
Zero Scale Error
Vzs
6.0
mVMAX
Inpul Ollsel Voltage
Vos
7.0
mVMAX
Input Bias Current
Ie
250
nAMAX
Input Oll.et Current
lOS
75
nAMAX
Voltage Gain
Av
10
VlmVMIN
Common Mode
Rejection Ratio
CMRR
74
dBMIN
Power Supply
Rejection Ratio
PSRR
76
dBMIN
±9VSVS ±18V
Input Voltage Range
(Note I)
±11.5
Feedthrough Error
.1V ,N = 2OV, DET = I, RST = 0
VMIN
66
dBMIN
3.0
mVMAX
1000
nAMAX
COMPARATOR
Input Oll.et Voltage
Vos
Input Bias Current
Input Offset Current
lOS
Voltage Gain
Av
Common Mode
Rejection Ratio
CMRR
Power Supply
Rejection Ratio
PSRR
Input Voltage Range
±9V S VsS ±18V
(Note I)
Low Output Voltage
ISINK S 5.0mA, Logic GND = 5.0V
...
6
lIiI:
Do.
II)
300
nAMAX
3.5
VlmV MIN
62
dBMIN
76
dBMIN
±11.5
VMIN
0.4
-0.2
V MAX
VMIN
a::
w
ii:
::::i
Do.
:II!
C
C
....
0
:E:
C
Z
C
w
....
Do.
:II!
C
II)
"OFF" Output
Leakage Current
Output Short
Circuit Current
2.0kn Pull-up Resistor to 5.0V (Note 1)
111
VOUT=5V
Ise
60
,.A MAX
45
rnA MAX
rnA MIN
7.0
NOTES:
I.
Guaranteed by design.
2.
Due to limited production test times the droop current corresponds to
junction temperature (TJ)' The droop current VS. time (after power-on)
curve clarifies this point. Since most peak detectors (in use) are on for
more than 1 second. PMI specifies droop rate for ambient temperature
3.
PAQE12-33
(T A) also. The warmed-up (T AJ droop current specification is correlated
to the junction temperature (TJ) value. PMI has a droop current cancellation Circuit which minimizes droop current at high temperature. Ambient
(T AJ temperature specifications are not subject to production testing.
DET=I,RST=O.
PKD·01 MONOLITHIC PEAK DETECTOR WITH RESET AND HOLD MODE
DICE CHARACTERISTICS
ELECTRICAL CHARACTERISTICS at Vs = ±15V, C H = 1000pF, T A = 25°C. (Continued)
PKD-01N
PARAMETER
SYMBOL
CONDITIONS
LIMIT
UNITS
DIGITAL INPUTS-RST, DET (See Note 3)
Logic "1" Inpul Vollage
VH
2.0
VMIN
Logie "0" Inpul Vollage
Vl
0.8
V MAX
Logic "1" Inpul Current
I'NH
V H =3.5V
1.0
lOA MAX
Logic "0" Input Current
I'Nl
V l =0.4V
10
lOA MAX
Droop Rate
V OR
F J =25"C
T A = 25"C (See Nole 21
Output Voltage Swing:
AmpliflerC
VOP
Rl = 2.5k
MISCELLANEOUS
Short Circuit Current:
AmplifierC
Isc
Power Supply Current
ISY
0.1
0.20
mVlms MAX
mVims MAX
±11.0
No Load
NOTES:
1. Guaranteed by deSign.
2. Due to limited production test times the droop current corresponds to
junction temperature (T J)' The droop current VS. time (after power~on)
curve clarifies this point. Since most peak detectors (in use) are on for mora
VMIN
40
7.0
mAMAX
mAMIN
9.0
mAMAX
than 1 second. PMI specifies droop rate for ambient temperature (T A) also.
The warmed-up (TAl droop current specification Is correlated to the junction temperature (TJ) value. PMI has a droop current cancellation circuit
which minimizes droop current at high temperatures.
3. DET=I,RST=O.
TYPICAL ELECTRICAL CHARACTERISTICS at Vs = ±15V, C H = 1000pF, and T A = 25°C, unless otherwise noted.
PKD-01N
PARAMETER
SYMBOL
CONDITIONS
TYPICAL
UNITS
"gm AMPLIFIERS A, B
0.5
Slew Rate
SR
Acquisition Time
I.
0.1% Accuracy, 20V step, AVCl = 1
41
~s
Acquisition Time
I.
0.01% Accuracy, 20V slep, AVCl = 1
45
~s
SmV Overdrive
2kO P\.~II-up Resistor to +5.0V
150
ns
ns
ViI'S
COMPARATOR
Response Time
MISCELLANEOUS
Switch Aperture Time
tae
75
Switching Time
ts
50
ns
Buffer Slew Rate
SRc
2.5
VII'S
Rl = 2.5kD
PAGE 12-34
PKD·01 MONOLITHIC PEAK DETECTOR WITH RESET AND HOLD MODE
TYPICAL PERFORMANCE CHARACTERISTICS
A AND B INPUT RANGE vs
SUPPLY VOLTAGE
.40
Vzs vs TEMPERATURE
A AND B AMPLIFIERS
A, BioS vs TEMPERATURE
35
30
"'- .......
V
V"
V I
/
~
25
:.
20
.§
1.) UNITS TRIMMED
>NJ1{FOR MIN. VZS
AT 25°C
I
-50
-25
0
25
50
75
laO
125
-50
-75
150
-25
0
TEMPERATURE (OC)
INPUT SPOT NOISE
FREQUENCY
r--....
..........
'0
o
-75
........
15
UNIT CAN HAVE EITHER
./
\'-.,
25
-
r-
50
75
100
VB
WIDEBAND NOISE
VB
BANDWIDTH
A AND B Vos vs TEMPERATURE
10
~l00~1111~1
~
o
~
0
fffll"-.....±-I'fR'It1
~10~
~
.... ~
RS -10Kn
I-+Htttttt--t"'"
10
_3
.s>
J
w
~
0z
~
.....- ./'
.
,.
100
o
10
0.1
FREQUENCY 1Hz)
100
-50
-25
/
/
"'/'- ./
0
/
1.) UNITS TRIMMED FOR
MIN. VZSAT25"C2.) UNtTSCAN HAVE
"'- ,IHER
25
50
JOR -lev z
l'
75
100
~
150
OUTPUT VOLTAGE SWING vs
SUPPLY VOLTAGE (DUAL
SUPPLY OPERATION)
+1.0
18
POLARITY OF ERROR
MAY BE POSITIVE OR
NEGATIVE
,. r--
CH = 1000pF
TA = 25 c C
25"C
10
+0.5
-55'C
~0
ERROR (mV)
~
--5V
10
-lOV
RL '" 10k
+5V
f-+-+--H-+-<>-+-+--r++--H-+--I--+-+--H--j
VIN (VOLTS)
+10V
'"
...::>~
eo::>
~
-2
-6
0
-0.5
-10
-,.
-1.0
t-...
~
-~
~
,..-,:::::
~
~:s<'"+125'C-'.
+25°C
-55G C
-5S"C
:s:
+25 C
~
Q
+l25 QC ~
~
--s;s:"
-18
1.0
PAGE 12-35
II
9o
125
TEMPERATURE (OC)
AMPLIFIER CHARGE INJECTION
ERROR vs INPUT VOLTAGE
AND TEMPERATURE
1.0
10
-75
1000
BANDWIDTH (KHz)
AMPLIFIER B CHARGE INJECTION
ERROR VB INPUT VOLTAGE
AND TEMPERATURE
0.5
"-
'"
.
I=m
125 150
TEMPERATURE fOCI
12
15
SUPPLY VOLTAGE +V AND -V (VOLTS)
18
Do.
PKD·01 MONOLITHIC PEAK DETECTOR WITH RESET AND HOLD MODE
TYPICAL PERFORMANCE CHARACTERISTICS
..
OUTPUT VOLTAGE SWING vs
SUPPLY VOLTAGE (SINGLE
SUPPLY OPERATION)
OUTPUT VOLTAGE vs
LOAD RESISTANCE
OUTPUT ERROR FOR
FREQUENCY vs INPUT VOLTAGE
12
38
RL "10k ~;
RL CONNECTOR TO V .. %V+
rc. 1 ........
~rs
V
....X
12.
~
RL =21<
-4,0""">" V
f-- f--
,,'"
~//
~
7.
5.0
~
2.5
~
a
is
25~C
-66'C
\~
JJIl
I J~!c
...
-12.5
-55'C
1.0
0.1
a
1111\
IIU.JmV
ERROR
100Hz
10.0
1KHz
10KHz
100KHz
(" RESET TO ZERO VOLTS) FREQUENCY
LOAD RESISTOR TO GROUND {KnI
PKD-01 SETTLING RESPO.NSE
l~lI
2
'f'cH-
-15
1\
2DOmVERROR
4
•
SUPPLY VOLTAGE +V AND -V (VOL TSJ
•
•
125~C
-7.
812162024283238
10
17"
-10.0
RL" 2k
o
•
•
10.a
~ ~::•a
.... V
....
.... V
V
=umL~
I•
LARGE SIGNAL
NON-INVERTING RESPONSE
PKD-01 SETTLING RESPONSE
+IOV
OV
TIME (2O,.oIDIV.)
LARGE SIGNAL NON·INVERTING
RESPONSE
ov
~
~
~
w
~
OV
~
lw
~
!!
~
!!
0
"0
!!l
w
~
!!
~
~
!;
.TIME (2OpolDIV.)
~
Q
S
!!l
SETTLING TIME FOR +10V
TO OV STEP INPUT
SETTLING TIME FOR -10V
TO OV STEP INPUT
!;
ov
0
TIME C20,.aIDIV.)
PAGE 12-38
TIME (2Ol'alDIV.)
PKD·01 MONOLITHIC PEAK DETECTOR WITH RESET AND HOLD MODE
TYPICAL PERFORMANCE CHARACTERISTICS
SMALL SIGNAL OPEN LOOP
GAIN/PHASE VB FREQUENCY
'20
CHANNEL TO CHANNEL
ISOLATION VB FREQUENCY
~
T,,_!IiOC
80
o
~
i'--.
::<----+4d---+-",""""1--t 90 ~
TEST CONDITION:
CH .. 1000pF
AMPliFIER A AND B CONNECTED IN
'35w
180
-~~~--~--~~--~--~~
100
lk
10k
lOOk
FREQUENCY (Hz)
'D. rTTnnr-mIlllll"T
'\.
45 ~
10
OFF ISOLATION VI FREQUENCY
...
TA = 2S"C
RL '" lOkn
CL = 30pF
1M
~
r
f
~
401+HII-ftHllllI-tI&-tHtl!l-tfflllH
+ 1 GAIN
AMPLIFIER AlB) OFF,INPUT_IOY PKjK
AMiUFIER
ON'I'NPUT_1OY
20 I-HfIIII-+H!IIIII-+HHIII-+
0
10M
10
100
1K
10K
lOOK
1M
. ,L.J.JJJJ",...I.U:W''''OO:-'''III'":K.J.
10M
FREQUENCY (Hz)
AQUISITION TIME VI EXTERNAL
HOLD CAPACITOR AND
AQUISITION STEP
DROOP RATE VB TIME AFTER
POWER ON
lOOK
1M
10M
AQUISITION TIME VI INPUT
VOLTAGE STEP SIZE
500.----r---,----,r----r---,
~~~~!5°cl
10K
FREQUENCY 1Hz)
50r-----~----,------r----~
CH = l00DpF
40~--~---+---1-~~~
V
j
V
!30/---~-
V
"z
~20/---~~~~~--/---1
llJ
'O/-~~~---+---I---1
0L-____L-__
• '0
o
TIME AFTER POINER APPLIED (MINUTES)
HOLD CAPACITANCE IpF)
6
~~
__
~
____
10
15
INPUT STEP (VOL TSI
~
20
9c
liIi:
A-
U)
a:
w
u::
DROOP RATE
VB
TEMPERATURE
AQUISITION OF STEP INPUT
~
A-
AQUISITION OF SINEWAVE PEAK
::E
'0000
~
§
C
C
...I
."
+1OV
"
10DD
'"!
"~
~
-IOV
'00
AMBIENT
TEMPERATURE
OV
0:
0
,
J::::
~
JUNeTlONTEMPERATURE.::::::::
50
'00
-10V
'50
TEMPERATURE (Cl
PAGE 12-37
o
:z:
c
OV
z
c
W
...I
+10V
~
"'
8!3 '
+10V
OV
-IOV
A-
!
PKD·01 MONOLITHIC PEAK DETECTOR WITH RESET AND HOLD MODE
TYPICAL PERFORMANCE CHARACTERISTICS
COMPARATOR INPUT BIAS
CURRENT VB DIFFERENTIAL
INPUT VOLTAGE
+3
i
COMPARATOR VOS
VB TEMPERATURE
COMPARATOR lOS
TEMPERATURE
VB
110
I~PUT C~RRENT I
Vs • '''5V
TA" 26"C
:SLTE: i~~~T~~A ..
a:
100
\
w +2
j!:
i!i
UNITS CAN HAVE
1+1
r-....
I-
i5
a:
OTHER
_OTHER
INPUT
f-"INPUT
AT -1OY
a:
a
AT IN
iD
OTHER
i
INPUT
AT +lOV
,
-15
-10
-5
+10
+5
"r-.... . . . .V
.,., ~ v .........
:/ 0
-1
±Tcvos
o
-76 -60
+15
-25
0
INPUT VOLTAGE (VOLTS)
25
V
:;! 80
"a:~
'"
70
~
""'-
.........
80
....... r-...
........
60
100 126
160
-75 -60
rei
-25
0
25
50
75
100
126 150
TEMPERATURE (OCI
OUTPUT SWING OF
COMPARATOR VB
SUPPLY VOLTAGE
COMPARATOR la
VB TEMPERATURE
~
u
75
TEMPERATURE
90
-a:
0
"
50
1
/
COMPARATOR RESPONSE
TIME VB TEMPERATURE
1200
w ·4V
1000
" " r-....
g~
I,
"
:s
......
~
26, 50
75
100 125 160
~
w
~
.
......
~
2
INVERTING INPUT" VIN
-ov
\
\
1.5
1.0
~
~
=
15
18
(VOLTS)
'iQ
w
IN
~ +5mV
·I-:::j;:::t~t=t:::;~::t=~
I-
•
~
J /
0.2
I
o
>
i
-
-6mV
~~~~-60=--=10~0~'=60~7~~0~2=50~300~
TIME (NANOSECONDS)
COMPARATOR RESPONSE
TIME vs TEMPERATURE
0
~
~~
~
~
P'"
2.0
5V
r-....,_m::~...--..---,,--r--,
IN
+6mV
r::j=::t=+~~~~~::~
I-
~
~ "/
w
~
~
-4.2
1.5
~
u
~
~ 0.6
~~
+5V
"
-v
u
00.4
1.Dka
0.5
0
0.6
1.0
INPUT VOLTAGE (mV)
L-~~
12
SUPPLY VOLTAGE +V AND
0.8
I I
5
----r--r--
1.0
Vs to ±15V
TA '" 26"C
~~ ;5~.kn ..... \-,RL
TO
I-
+26'C
COMPARATOR OUTPUT VOLTAGE
VB OUTPUT CURRENT AND
TEMPERATURE
NON-INVERTING INPUT
~ 3
g
i---i---, t-.hH--+--+--;
.__ .. _
~--~------ t---~~
____
____
____
4
COMPARATOR TRANSFER
CHARACTERISTIC
I
~_.
.......... ~
_18L-~
\
1---+--+
IV
o
~ -'~~- -56"C
~-10
TEMPERATURE (OC)
~o
__ .__ +l26"C
,I!!!!..
-6
~
........
~
-2
~-14
o
0
2V
~
200
-25
1--1---+-
::>
400
-75 -60
3V
I-
2.0
4.0
6.0
8.0
10,0
12.0
10 - OUTPUT SINK CURRENT (mAl
PAGE 12-38
14.0
~-6mv<~o--~~~~~~~~~~~·
50
100
150
200
260 300
-u
TIME (NANOSECONDS)
PKD·01 MONOLITHIC PEAK DETECTOR WITH RESET AND HOLD MODE
TYPICAL PERFORMANCE CHARACTERISTICS
COMPARATOR OUTPUT
RESPONSE TIME
COMPARATOR OUTPUT
RESPONSE TIME
INPUT LOGIC RANGE
SUPPLY VOLTAGE
(2kO PULL-UP RESISTOR, T A = 25° C)
V8
1.9=~==+~-V---~"
14~
4V
.5mV
3V
OmV
~
I---J----t-----:.J.....-.
+VIN
~ V+
FOR
~50C +;ITA';;; +125°C
10
~ 61:;;;~~-==t==t===t==~
'"
~
2V
2 r---J----t---+--~_+---I
o ~2~
.~~--4---+---+--~
.
1V
~
OV
5
~
TIME (SOns/DIV.)
TIME (SOnsIDIV.1
--6
~.....
-55°C - - - -
....~./'
+25°C
V~.,....,
-10
-+----1
+125°C-
~14 t::±==:t==±:":-~!~~
-18 [
6
12
9
15
18
SUPPLY VOLTAGE +V AND -V (VOLTS)
,.
c-~~
14
12
r-~
_
v+
~
....
.
...
,
-
~
~
-~-
-55°C
+25°C
--+--+--
+126°C
ACCEPTABLE GROUND
BETWEEN SLIDE LINES
~10
r-r-
I-f~14
~1.
+12~QCI~
III!o
~.
"
~t
!O.
+25'C
I
I
I
I-
~
I
~
a
_+25°C
a:
-1
k'
10'"
10'"
--56'C
+26°C
+125°C
+l25°C
9
I
-2
...'i'
I
LOGIC 0
-3
II
I
-
~2
-~
46
121518
SUPPLY VOLTAGE +V AND -V (VOLTS)
V~
_ _ ~oC
r-
"
......
I
LOGIC 1 _
11
~~55'C
SUPPLY CURRENT VB
SUPPLY VOLTAGE
1
+-
~
PIN POTENTIAL IS
~2
LOGIC INPUT CURRENT VI
LOGIC INPUT VOLTAGE
INPUT RANGE OF LOGIC
GROUND V8 SUPPLY VOLTAGE
I
LOGIC GROUND = OV
I
I
i
I
-1
SUPPLY +V AND
lOGIC INPUT VOLTAGE (VOLTS)
-v
12
15
(VOL TSI
1.
Q
~
Q,.
en
II:
W
HOLD MODE POWER SUPPLY
REJECTION VI FREQUENCY
100
ii:
::::i
Q,.
::Ii
CC
...
0
TA = 25°C
I
80
I
I
Q
VIN • OV
CH .. 1000pF
:z:
I
POSITIVE SUPPL v
Q
Z
CC
r---- (+15V +1V SIN wTI
...
w
NEGATIVE SUPPLY
f---- (~15V
+'1
SIN wi
I .... t\
20
Q,.
~
CHANNEL A = 1
CHANNEL B '" 0
o
10
100
lk
10k
FREQUENCY (Hz)
PAGE 12-39
lOOk
1M
::Ii
CC
en
PKD·01 MONOLITHIC PEAK DETECTOR WITH RESET AND HOLD MODE
THEORY OF OPERATION
The typical peak detector uses voltage amplifiers and a
diode or an emitter follower to charge the hold capacitor,
CH, unidirectionally (Figure 1). The output impedance of A
plus D1.'s dynamic impedance, rd, make up the resistance
which determines the feedback loop pole. The dynamic
impedance is rd = RI . Id is the capacitor charging current.
q d
The pole moves toward the origin of the S plane as Id goes
to zero. The pole movement in itself will not significantly
lengthen the acquisition time since the pole is enclosed in
.
the system feedback loop.
When the moving pole is considered with the typical fre·
quency compensation of voltage amplifiers there is, how·
ever, a loop stability problem. The necessary compensation
can increase the required acquisition time. PMI's approach
replaces the input voltage amplifier with a transconduc·
tance amplifier; Figure 2.
The PKD·01 transfer function can be reduced to:
1
1
Vout
"V;"N = 1 + SCH + 1
~ 1 + SCH
gm gmRout
9m
Where: gm~1I'A/mV, Rout~20MI!.
The diode in series with A's output (Figure 2) has no effect
because it is a resistance in series with a current source. In
addition to simplifying the system compensation, the input
transconductance amplifier output current is switched by
current steering. The steered output is clamped to reduce
and match any charge injection.
Fig. 3 shows a simplified schematic of the reset "gm" amplifier, 8. In the track mode, 01 &04are ON and 02&03are OFF.
A current of 21 passes through D 1, I is summed at "8" and
passes through 0 1, and is summed with gmVIN' The current
sink can absorb only31, thus, the current passing through O2
can only be: 21- gmVIN' The net current into the hold capacitor node then, is gmVIN (ICH = 21 - (21 - gmVIN). The hold
mode, 02&03are ON while 01 & 04are OFF. The net current
into the top of 0 1 is -I until 0 3 turns ON. With 01 OFF, the
bottom of O2 is pulled up with a current I until 0 4 turns ON,
thus 0 1& 02are reverse biased by~O.6Vand charge injection
is independent of input level.
The monolithic layout results in points A and B having equal
nodal capacitance. In addition, matched diodes D1 and D2
have equal diffusion capacitance. When the transconduc·
tance amplifier outputs are switched open, pOints A and B
are ramped equally but in opposite phase. Diode clamps D3
and D4 cause the swings to have equal amplitudes. The net
charge injection (voltage change) at node C is therefore
zero.
The peak transconductance amplifier, A, is shown in Figure
4. Unidirectional hold capacitor charging requires diode 0 1
to be connected in series with the output. Upon entering the
peak hold mode D1 is reverse biased. The voltage clamp
limits charge injection to approximately 1pC and the hold
step to O.6mV.
Minimizing acquisition time dictated a small CH capaci·
tance. A 1000pF value was selected. Droop rate was also
minimized by providing the output buffer with an FET input
stage. A current cancellation circuit further reduces droop
current and minimizes the gate current's tendency to double
for every 10·C temperature change.
Figure 1. Conventional Voltage Amplifier Peak Detector.
Figure 2. Transconductance Amplifier Peak Detector.
A
'--_-+_____ !
_~----_+-v-
}
~~:';ROL
A::> B "" PEAK DETECT
A< B "" PEAK HOLD
Figure 3. Transconductance Amplifier With Low Glitch Current Switch
A
'----t-----!} ~~:~ROL
- ......----~
v-
A>B",PEAK DETECT
A< B == PEAK HOLD
Figure 4. Peak Detecting Transconductance Amplifier With
Switched Output.
PAOE12-40
PKD·01 MONOLITHIC PEAK DETECTOR WITH RESET AND HOLD MODE
APPLICATION INFORMATION
OPTIONAL OFFSET VOLTAGE ADJUSTMENT
Offset voltage is the primary zero scale error component
since a variable voltage clamp limits voltage excursions at
D1'S anode and reduces charge injection. The PKD·01 circuit
gain and operational mode (positive or negative peak detec·
tion) determine the applicable null circuit. Figures A through
D are suggested circuits. Each circuit corrects amplifier C
offset voltage error also.
A. NULLING GATED OUTPUT gm AMPLIFIER A. Diode D1
must be conducting to close the feedback circuit during
amplifier A Vos adjustment. Resistor network RA·Rc cause
D1 to conduct slightly. With DET = 0 and V1N = OV monitor
the PKD·01 output. Adjust the null potentiometer until
VOUT OV. After adjustment, disconnect Rc from CH.
=
B. NULLING GATED gm AMPLIFIER B. Set amplifier B
Signal input to VIN = OV and monitor the PKD·01 output. Set
DET = 1, RST = 1 and adjust the null potentiometer for
VOUT = OV. The circuit gain - inverting or noninverting will determine which null circuit illustrated in Figures A
through D is applicable.
100kll
R,
1kll
R,
>t+......-OVOUT
Vo.o---"""","I'---+-I
VIN+
1kll
v,-
POD·"
4
v,.
NOrES:
I
:;'k"
C
2MII
eM'" 1000pF
":"
R,
250"
-15V
1.NULlAANGE"'~Vs(';;)
R,
v.. -
.,
AI
1kO
-15V
r·'"
R,
20"
-=-
NOTES:
1. NULL RANGE = :tV. (~)(A1:'AI)
":"
2. DISCONNECT He FROM eN AFTER AMPLIFIER A ADJUSTMENT.
2. DISCONNECT Rc FROM eN AFTER AMPLIFIER A ADJUSTMENT.
3. REPEAT NULL CIRCUIT FOR RESET BUFFER AMPLlF1ER B IF REQUIRED.
3. REPEAT NULL CIRCUIT FOR RESET BUFFER AMPLIFIER 8 IF REQUIRED.
RAt AI AND ftc NOT NECESSARY FOR AMPLIFIER 8 ADJUSTMENT,
Figure A. Vos Null Circuit for Unity Gain Positive Peak
Detector.
R,
v,.
Figure B. Vos Null Circuit for Differential Peak Detector.
en
lie
W
..
v,R,
GAIN:::1-+ R1 -+ R3
R,
25110
u::
~
~
...
Q
V,.
o:E:
v,-
Q
V""T
25k1l
R,
>-,+-+-0 VOUT
V"
Z
~
w
~
:Ii
:i
-15V
POD..,'
NOTES:
,.NULLRANGE=:tVs(~)
I
eM =< 1000pF
-15V
~c:;'k"
2MII
":"
POD..,'
Ae
1kll
NOTES:
1.NULLRANGE=:!Vs(~)
":'"
2. DtSCONNECT ftc FADM eN AFTER AMPLIFIER A ADJUSTMENT.
3. REPEAT NULL CIRCUIT FDA RESET BUFFER AMPLIFIER 8 IF REQUIRED.
Figure C. Vos Null Circuit for Negative Peak Detector.
I
~c.
2M!!
R
eM:: 1000pF
":'"
::'kll
8
1kll
":'"
2. DISCONNECT Re FROM eM AnER AMPLIFIER A ADJUSTMENT.
3. REPEAT NULL CIRCUIT FOR RESET IUFFER AMPLIFIER B IF REQUIRED.
Figure D. Vos Null Circuit for Positive Peak Detector With
Gain.
PAGE 12-41
PKD-01 MONOLITHIC PEAK DETECTOR WITH RESET AND HOLD MODE
PEAK HOLD CAPACITOR RECOMMENDATIONS
The hold capacitor (CH) serves as the peak memory element
and compensating capacitor. Stable operation requires a
minimum value of 1000pF. Larger capacitors may be used
to lower droop rate errors, but acquisition time will increase.
With the comparator in the low state (Vall, the output stage
will be required to sink a current approximately equal 10
Vc lR l·
Zero scale error is internally trimmed for CH = 1000pF. Other
CH values will cause a zero scale shift which can be approximated with the following equation.
NON·INVERTING
COMPARATOR INPUT
R,
cNzs(mV) = 1 X 103(pC) _ 0.6mV
CH(nF)
The peak hold capacitor should have very high insulation
resistance and low dielectric absorption. For temperatures
below 85 ·C, a polystyrene capacitor is recommended, while
a Teflon capacitor is recommended for high temperature environments.
R,
CAPACITOR GUARDING AND GROUND LAYOUT
Ground planes are recommended to minimize ground path
resistance. Separate analog and digital grounds should be
used. The two ground systems are tied together only at the
common system ground. Avoid digital currents returning to
the system ground through the analog ground path.
The CH terminal (Pin 4) is a high-impedance point since a
transconductance amplifier is·used as the input amplifier.
To minimize gain errors and maintain the PKD-01's inherently low droop rate, guarding Pin 4 is recommended.
INVERTING
COMPARATOR INPUT
DIGITAL
GND
Figure 1_
Table 1.
5
R2
VOH Rl
3.5 2.7K 6.2K
Vc
5
5.0 2.7K
15
3.5 4.7K 1.5K
15
5.0 4.7K 2.4K
00
15
7.5 7.5K 7.5K
15
10.0 7.5K 15K
PEAK DETECTOR LOGIC CONTROL (RST, DET)
COMPARATOR OUTPUT
The comparator output high level (VOH ) is set by external
resistors. It's possible to optimize noise immunity while interfacing to all standard logic families - TIL, DTL, and
CMOS. Figure 1 shows the comparator output with external
level setting resistors. Table I gives typical Rl and R2 values
for common circuit conditions.
The maximum comparator high output voltage (VOH ) should
be limited to:
VoH(maximum) < V +
- 2.0V
The transconductance amplifier outputs are controlled by
the digital logic signals RST and DET. The PKD-01 operational mode is selected by steering the current (1 1) through
0 1 and O2, thus providing high-speed switching and a
predictable logiC threshold. The logic threshold voltage is
1.4 volts when digital ground is at zero volts.
Other threshold voltages (VTH ) may be selected by applying
the formula:
VTH "'1.4V + Digital Ground Potential.
For proper operation, digital ground must always be at least
3.5V below the positive supply and 2.5V above the negative
supply. The RST or DET signal must always be at least 2.8V
above the negative supply.
Operating the digital ground at other than zero volts does influence the comparator output low voltage. The VOL level is
reference to digital ground and will follow any changes in
digital ground potential:
VOL ",O.2V + Digital Ground Potential.
PAGE 12-42
PKD·01 MONOLITHIC PEAK DETECTOR WITH RESET AND HOLD MODE
BURN-IN CIRCUIT
PKD-01 LOGIC CONTROL
L
56K!l
"
r---------~----Qv.
14
~
,
DET
18K!!
,"v
O.
AST
GROUND
12
-f-<
4
36KI!
5%
13
-f-<
3
1 ""
DIGITAL
PKO·Ol
-'-'--<
"
5
c-()
~
9
rr-
}
7
CURRENT TO
CONTROL MODES
TYPICAL CIRCUIT CONFIGURATIONS
UNITY GAIN POSITIVE PEAK DETECTOR
v.
iiEf/RST
v-
,.
+10V
OUTPUT
INPUT
DV
II
....
+'DV
'i'
a
~
a.
DV
In
II:
W
c.
~1000PF
ii:
::::i
a.
:E
ct:
a
POSITIVE PEAK DETECTOR WITH GAIN
..I
0
:z::
v.
iffi
a
z
v-
ct:
W
..I
a.
:E
ct:
+5V
Y,N
DV
-2V
+10V
In
OUTPUT
INPUT
(GAIN; +2)
.%
Your
DV
-4V
RESET
VOLTAGE: + 1V
(RESETS TO -.tv)
AST
PAGE 12-43
C.
~1000PF
PKD·01 MONOLITHIC PEAK DETECTOR WITH RESET AND HOLD MODE
NEGATIVE PEAK DETECTOR WITH GAIN
v+
v-
INPUT
OUTPUT
>-,....,."-+--O
OUTPUT
AST
UNITY GAIN NEGATIVE PEAK DETECTOR
v+
v-
v,. ""'MH--+-......:.j--f
>"",+""-0 V...
ALTERNATE GAIN CONFIGURATION
A,
>""'I-~-o OUTPUT
A,
INPUT
IF 80TH INPUT SIGNAL (AMPLIFIER A INPUT) AND THE RESET
VOLTAGE (AMPLIFIER B INPUT) HAVE THE SAME POSITIVE·VOLT·
AGE GAIN THE GAIN CAN BE SET BY A SINGLE VOLTAGE DIVIDER
fOR BOTH INPUT AMPLIFIERS•.
RESET
VOLTAGE
A,
A,
*
=1+~
A,
Cw=1000pF
"':"
PAGE 12·44
PKD·01 MONOLITHIC PEAK DETECTOR WITH RESET AND HOLD MODE
PEAK· TO· PEAK DETECTOR
PKD·01
POSITIVE
PEAK
DETECTOR
10k!!
v,.
10k!l
PKD·01
NEGATIVE
PEAK
DETECTOR
10k!)
LOGIC SELECTABLE POSITIVE OR NEGATIVE PEAK DETECTOR
3R
-15V
INPUTo---~----------~~~--------4-~~~i
OUTPUT
•
POSIT~:~~E~Ei-T~~~ 0 - - - - - - - - '
PEAK DETECT/RESET
9Q
GND
0-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _-'
4
~
a.
13
CH
~ 1000pF
NOTES: 1. DEVICE IS RESET TO 0 VOLTS.
1/1
a:
2. DETECTED PEAKS ARE PRESENTED AS POSITIVE OUTPUT LEVELS.
IU
3. R = 10kn.
ii:
::::i
4. 5, IS ALWAYS CLOSED TO COMPENSATE FOR VOLTAGE DIVIDER ERROR WHEN 5, IS CLOSED.
a.
~
c(
DIGITAL GROUND CONNECTION FOR
SINGLE SUPPLY OPERATION
LOGIC LEVEL TRANSLATION FOR PKD·01
SINGLE SUPPLY OPERATION
Q
..I
o
:t:
Q
Z
V+= 15V
c(
Rl '" 3.3Kn
IU
..I
.-----0 V+=15V
a.
R = 5.1Kil
PKD-Ol
TO PKD-Ol
..':::3-:-:=_ _-. '\..'.4V
R2 '" 390n
DIG. GND
R2
Digital ground connection
for single supply operation.
R3= lKn
Logic High Voltage ~ 4.4V
Logic Low Voltage = 1.58V
Lavel Translation For
PKD-Ol Singfe SupplV Operation.
PAGE 12-45
LOGIC CONTROL
IDet, RST)
~
c(
1/1
PKD·01 MONOLITHIC PEAK DETECTOR WITH RESET AND HOLD MODE
PEAK READING AID CONVERTER
S.OV
PORTO
41-----1
51-_ _ _---1
2.7K
PKD·01
R
INPUT
SIGNAL
BIT 10
PORT 1
RST
RESET
VOLTAGE
POSITIVE PEAK DETECTOR WITH SELECTABLE RESET VOLTAGE
PKD·Ol
VIN
<>----------+-=-+-1
>-.-t~-<>
Your
~/"
~-~
maD
-'
;--"
ov
ov
13
PK DET/RST 0 - - · 0 0 0 _ - - - - '
+15V
L~
-15V ":" GND
NOTE; RESET VOLTAGE = -l.OV
TRACE 1 = 2V/OIV
TRACE 2 = 5V/DIV
TRACE 3'" 2V/OIV
LOGIC
GND
PAGE 12-46
PKD·01 MONOLITHIC PEAK DETECTOR WITH RESET AND HOLD MODE
PROGRAMMABLE LOW FREQUENCY RAMP GENERATOR
AMPLITUDE {
SELECTION
LOGIC
0---.....,
CH1
CH2
~~~~-~--o
CH3
BUFFERED
RAMP
OUTPUT
CH4
MUX·oa
CH5
RAMP
AMPLITUDE
CH6
CH7
RAMP SLOPE
SELECTION
CH6
+15Y
RST
RAMP
START
PULSE
Jl
o--___
...J
SLOPE=~
SLOPE=
...!!.
C
C
-O.SVlJts
•
9c
~
Go
UI
II:
RAMP
START
PULSE
W
iL
:::;
Go
::E
NOTES:. 1. NEGATIVE SLOPE OF RAMP IS SET BY DAC·oa OUTPUT CURRENT.
2. DAC·08IS DIGITALLY CONTROLLED CURRENT GENERATOR. THE MAXIMUM FULL SCALE CURRENT MUST BE LESS THAN O.5mA.
0(
C
....I
o
l:
C
Z
0(
W
....I
Go
::E
0(
UI
PAOE12-47
TELECOMMUNICATIONS
TELECOMMUNICATIONS
INDEX
PRODUCT
TITLE
OAC-8S
DAC-87
DAC-88
DAC-89
DMX-88
MUX-88
RPT8i/82
SMP-81
COMDAC8 Companding 01 A Converter ..•..•......... ~ ..•....... , .•... , .• . • . . . . . . . . . . . • .. 13-3
COMDAC8Companding DIA Converter ..•.........•..•.•...•.....•...................•.. 13-11
COMDAC8 CompandingD/A Converter ...........•........•................•.•..•..•.... 13-18
COMDAC8 Companding D/A.Gomierter .................................................. 13-25
8-Channel Analog De-Multiplexer for PCM Codecs ............. : ....•.....•.•......•.•...• 13-32
8-Channel Analog Multiplexer for PCM Codecs •..•.............•.... ,..................... 13-37
PCM Carrier Repeaters .•...•.....•.............•.......•.................•.............. 13-42
Telecommuriications Sample and Hold Amplifier ..•....•..•.....•.•...•... ; ................ 13-52
PAGE
INTRODUCTION
The circuits described in this section are intended for, but
not limited to, Telecommllnication Applications. These circuits fill such applications asPCM CODECs, Repeaters,
switching systems, etc. The components include: D/A
Converters, Sample-and-Hold Amplifiers, Multiplexersl
Demultiplexers and Repeaters. When used with references,
comparators,· operational amplifiers and other components
in. this catalog, they comprise the analog portion of many
Telecommunications systems.Some components will bear a
great reseinblance to Devices listed elsewhere; e.g., the
DAC-88 resembles the DAC-78. In fact, they are the same
device with the exception that Telecommunications devices
are selected and tested to parameters of i ntarest to Telecommunications users and the industrial counterparts are
specified .for those parameters of interest to users in other
industries.
Included in this section are a series of D/A converters: the
DAC-86, DAC-87,DAC-88 and DAC-89. These devices are
intended for use in Bell "255" companding law (DAC-aS/88)
Codec systems (U.S.) or "A" companding law (DAC-87/89)
response for use in European systems. In conjunction with
these systems, other devices available for use in codecs are:
the SMP81 Sample-and-Hold Amplifier, the MUX88 Schannel Analog Multiplexer, and the DMX-88 S-channel
Demultiplexer. Standard industrial devices which may be
used with these specialized devices are: CMP01/CMP05
Comparators, REFOllREF02 Voltage Reference, and OP01,
OP15, OP 37 operational amplifiers (to name it few).
Also included in this section are the RPT81 and RPT82 PCM
Carrier Repeater. These devices can also be used as clock
regeneration circuits in non-telephony applications.
Complete data, as well as applications ideas are given for all
devices.
.
PAGE 13-2
DAC-S6
PMI
COMDAC® COMPANDING DlA CONVERTER
JL - 255
FEATURES
LAW DAC
iiiiiiiiii
+VFS - • • • • •
• Conforms With Bell System 1'"255 Companding Law
•
Meets D3 Compandor Tracking Specifications
• Both Encode and Decode Capability
• Tight Full Scale Tolerance Eliminates Calibration
o
• Low Full Scale Drift Over Temperature
•
COMDAC@
Extremely Low Noise Contribution
TRANSFER
CHARACTERISTIC
• Multiplying Reference Inputs
• Simplifies PCM System Design
• High Reliability
•
o 111
Low Power Consumption and Low Cost
GENERAL DESCRIPTION
1111
x 000 0000
DIGITAL INPUT
1 111 1111
BELL ,...255 LAW TRANSFER CHARACTERISTIC
The DAC-86 monolithic COMDAC® D/A Converter provides
a 15 segment linear approximation to the Bell System
1'"255 companding law. The law is implemented by using
three bits to select one of eight binarily-related chords (or
segments) and four bits to select one of sixteen linearlyrelated steps within each chord. A sign bit determines
signal polarity, and an encode/decode select bit determines encode or decode operation.
The transfer characteristic of the DAC-86 is a piecewise linear
approximation to the Bell System ,...25 law expressed by:
Y(x)
=sgn(x) In(1 +l-'lxD
In(1 + i4
-1 :5 X:51
Accuracy is assured by speCifying chord end pOint values,
step nonlinearity, and monotonicity over the full operating
temperature range. Typical applications include PCM carrier systems, digital PBX's, intercom systems, and PCM
recording. For CCITT"A" Law models, refer to the DAC-87/89
data sheet.
for a normalized coding range of ±1
where: x = input signal level
Y = output compressed signal level
1-'=255
This law is implemented by the DAC-86 with an eight chord
(or segment) piecewise linear approximation with 16 linear
steps in each chord for both polarities. Dynamic range of
72dB in both polarities is achieved with eight-bit coding.
i:QUIVALENT CIRCUIT AND PIN CONNECTION
DIAGRAM
PIN CONNECTIONS& ORDERING INFORMATION
1 = ENCODE
1 "'POSITIVE
MOST SIGNIFICANT CHORD
BIT INPUT
SECOND CHORD BIT INPUT
1
POSITIVE POWER SUPPLY
2
DECQ[)E OUT: E/D SB
4
ENCODE OUT: E/O 88 =-10
MOST SIGNIFICANT STEP
BIT INPUT
VRI+'
11
SECOND STEP BIT INPUT
THIRD STEP BIT INPUT
VRI-I
12
LEAST SIGNIFICANT STEP
BIT INPUT
REFERENCE
AMPLIFIER
ENCODE OUT: E/D
VLe
PAGE 13-3
00
sa .. 11
NEGATIVE POWER SUPPLY
NEGATIVE REFERENCE
INPUT
POSITIVE REFERENCE
INPUT
THRESHOLD CONTROL
18 PIN HERMETIC DUAL-IN-LiNE
(X-Suffix)
ACCURACY
±1I2 STEP
DAC-86EX
DAC-86CX
±1 STEP
13
~
DECODE OUT: E/D S8 = 01
LEAST SIGNifiCANT
CHORD BIT INPUT 5
z
o
~
u
Z
ENCODE/DECODE SELECT: . . . 4 - L J - 1 SIGN'BIT INPUT:
V+
;
II)
STEP
INPUTS
87 Be B5 B4
V-
II
::;)
:I
:I
8
-'
...
III
III
DAC·86 COMPANDING D/A CONVERTER
OUTPUT CURRENT DC TEST CIRCUIT
R.
+VREF
LINE SELECTION TABLE
ENCODE!
SIGN
OUTPUT
DECODE
BIT
MEASUREMENT
TEST
GROUP
Rl1
18.94k!!
IRREFI
10E(+)
(Eo./R1)
0
10E(-)
(Eo, /R2)
100(+)
0
100(-)
(Eo2/R3)
(EoiR4)
11
3
R.2
20ku
NOTE: Accuracy Is specified In Ihe lesl circuli using the tables below 10 be
In each
,R1 = R2=R3=R4'"2.6k!!
·VREF IS At;lJUSTED BEFORE TESTING EACH DEVICE
TO PROVIDE IDEAL FULL SCALE OUTPUT CURRENT.
0
0
~~~~ l.\'~n~~~;I~I~~.fr~r~~II~~~~r:n~!'i£ r~/~~ I~:~i~~:re;alue
-=-
CONDENSED CURRENT OUTPUT TABLES (IREF = 528/tA)
IDEAL DECODE OUTPUT CURRENT IN MICROAMPS AT CHORD ENDPOINTS
~
STEP
0
15
0000
1111
STEP SIZE
0
000
001
010
011
0
7.5
8.25
23.25
24.75
54.75
2
57.75
117.75
4
0.50
4
100
101
6
110
7
111
519.75
999.75
32
1047.75
2007.75
8
255.75
495.75
16
123.75
243.75
64
IDEAL ENCODE OUTPUT CURRENT IN MICROAMPS AT CHORD ENDPOINTS
STEP
~
0
15
0000
1111
STEP SIZE
0
000
001
010
011
100
5
101
110
111
8.75
25.75
55.75
59.75
119.75
127.75
247.75
263.75
503.75
535.75
1015.75
1079.75
2039.75
8
16
32
64
3
0.25
7.75
23.75
0.50
These tables may be extended to include all of the encode/decode currents (ideal with SI REF 528jtA) by multiplying any of the numbers in the normalized tables by O.5jtA_
=
6
CHORDS
Groups of linearly-related steps in the transfer function.
Also known as segments.
CHORD ENDPOINTS
SPECIFICATION PARAMETER DEFINITIONS
The maximum code in each chord. Used to specify accuracy.
FULL SCALE DRIFT
STEPS
The change in output current over the full operating
temperature with V REF = 10.000V, R11 = 18.94kO, and
R12=20kO.
Increments in each chord which divides it into 16 equal
levels.
FULL SCALE SYMMETRY ERROR
The difference between 10D( -) and loo( +) or the difference between 10 ;:(-) and 10E( +) at full scale output.
OUTPUT LEVEL NOTATION
Each output current level may be deSignated by the code
Ic,s where C = chord number and S = step number. For example, 100= zero scale current; 101 = first step from zero;
10,15 = endpoint of first chord (Col; i7,15 = full scale current.
DYNAMIC RANGE
OUTPUT VOLTAGE COMPLIANCE
The maximum output voltage swing at any current level
which causes < Yo step change in output current.
Ratio of the largest output (1 7,151 to the smallest output excluding zero (1 0,1) expressed in dB. This can be measured
peak or peak-te-peak with the same result.
PAGE 13-4
DAC·S6 COMPANDING D/A CONVERTER
ABSOLUTE MAXIMUM RATINGS
V + Supply to V - Supply. . . . . . . . . . . . . . . . . . . . . . . .. 36V
VLC SWing ......................... V-plus BV to V +
Analog Current Outputs ...... V- plusBVtoV- plus36V
Reference Inputs .......................... V- to V+
Reference Input Differential Voltage. . . . . . . . . . . . .. ± 1BV
Reference Input Current ...................... 1.25mA
ELECTRICAL CHARACTERISTICS at Vs =
Logic Inputs ................ V-plus BV to V-plus 36V
OperatingTemperature ............... -25°Cto +B5°C
Storage Temperature ............... -65°C to + 150 °C
Power Dissipation ........................... 500mW
Derate above 100°C ........................ 10mW/oC
Lead Soldering Temperature . . . . . . . . . . . .. 300°C (60 sec)
±15V, IAEF= 52BpA, -25 "C",TA ", +B5"C, and for all 4 outputs, unless otherwise noted.
DAC·86·E
PARAMETER
SYMBOL
CONDITIONS
MIN
Resolution
8 chords with 16 steps each
Dynamic Range
20 log (17, ,silo, ,)
Monotonicity
Sign Bit + or-
Chord Endpoint Accuracy
All Chords
Error relative to ideal values
at IFS = 2007.75"A
Encode Decision Level Current
Additional output
encode/decode = 1
DAC·86·C
MAX
±128 ±128 ±128
72
72
72
128
MIN
TYP
MAX
UNITS
±12B ±128
±128
Steps
72
72
3/8
ts
To within ±1/2 step
Full Scale Drift (C 7)
LlI FS
Full temperature range
Output Voltage Compliance
VOC
Full scale current change
051/2 step
Full Scale Symmetry Error
10 (+)'loH
Decode or encode pai r
Input Code 1111111
Zero Scale Current (Co)
Izs
Measured at selected output with
000 0000 input
Disable Current (All bits high)
IDIS
Leakage of output disabled by
ElO and SB
±1
Step
1/2
3/4
Step
5/8
1.0
see
note
1.0
see
note
pOec
±1/16 ±1/10
±1/10
±1/4
Step
+18
Volts
+18
1/4
-5
±1/40
±118
±1/40
±1/4
Step
1/40
1/8
1/40
1/4
Step
5.0
75
5.0
75
nA
±1
Step
2.0
4.2
rnA
0.8
Volts
Error relative to ideal values
at IFS = 2007.75"A
±1/2
Output Current Range
IFSA
Logic Input Levels, Logic "0"
VIL
VLC=OV
Logic Input Levels, Logic "1"
VIH
VLC=OV
Logic Input Current
liN
VIN = -5V to +18V
Logic Input Swing
VIS
V- = -15V
Reference Bias Current
1'2
-3.0 -12.0
Reference Input Slew Rate
dlfdt
0.25
0.25
Power Supply Sensitivity Over
Supply Range (Refer to
Characteristic Curves)
Power Supply Current
Power Dissipation
dB
Steps
1/2
-5
0
72
128
±1/2
Settling Time
Step Accuracy
All Chords
TYP
2.0
4.2
0
0.8
2.0
2.0
Volts
120
-5
+18
120
"A
+18
Volts
-3.0 -12.0
"A
-5
mA/pO
II
'"
~c
Q
III
PSSIFs+
V+ =4.5 to 18V, V- = -15V
±1/20
±1/2
±1/20
±1/2
Step
PSSIFS_
V- = -10.8Vto -18V, V+ =15V
±1110
±112
±1/10
±1/2
Step
1+
Vs= +5V, -15V, IFS=2.0mA
2.7
4.5
2.7
4.5
rnA
(,)
1-
VS= +5V, -15V, I FS =2.0mA
-6.7
-9.3
-6.7
-9.3
rnA
Z
;:)
1+
Vs= ±15V, IFS=2.0mA
2.7
4.5
2.7
4.5
rnA
1-
Vs= ±15V, IFS =2.0mA
-6.7
-9.3
-6.7
-9.3
rnA
:::E
:::E
PD
VS= +5V, -15V, IFS=2.0mA
114
167
114
167
mW
Po
VS= ±15V, IFS=2.0mA
141
207
141
207
mW
Z
0
~
0
(,)
W
...I
W
~
NOTE:
In a companding DAC the term LSB is not used because the step size within
each chord Is different. For example, In the first chord around zero (C~) step
size is 0.5"A, while in the last chord near full scale (C 7) step size is 4"A.
Settling time varies for each of the chord bits and step bits and a maximum
specification is misleading. In decode operation, the DAC-86 and OP-16
combination will decode eight channels. In the encode mode, the DAC-86
and CMp·01 combination will encode eight channels. Both encode and
decode statements assume a 5.2p.sec channel time.
PAGE 13-5
DAC-86 COMPANDING D/A CONVERTER
BASIC ENCODE OPERATION
(COMPRESSING AID CONVERSION)
approximation register - the usual elements in any slgnplus-magnitude AID converter. However, a compressing
ADC has one signficant difference from regular AID converters.
BASIC ENCODE CONNECTIONS
:,
In a conventional (linear converter), the step size Is a constant percentage of full scale, but In a compressing AID
converter, the step size increases as the output changes
from zero scale to full scale.
t5V ANALOG INPUT
r~l
'='2.5K
(GROUND FOR
SINGLE-ENDEO
INPUTS)
2.SK
+15
DIGITAL
OUTPUTS
tH1a!=:ID
SIGN
BIT
CHORD
BIT
STEP
When the DAC is used in the feedback loop of a successive approximation ADC the DAC outputs are used as
decision levels to determine the edges of the quantizing
bands. When the DAC is used in the decode mode it
follows that the outputs must correspond to the center of
the quantizing bands. Thus the encode mode output must
exceed the decode mode output by one-half step. See AN
39 for further explanation.
BITS
ENCODING SEQUENCE
An encoding sequence begins with the sign bit decision.
During this time the comparator is a polarity detector only.
The EncodelDecode (E/D) input is held at a logic "0", so that
no current flows into the encode outputs, and the comparator Is effectively disconnected from the DAC. Once the
input polarity has been determined, the EID input is changed
toa logic "1" allowing current to flow into IOE( +) or IOE( -)
depending upon the Sign Bit Answer.
R'2
2OK11
-15V
NOTE: THIS CONFIGURATION
Will
+15V
ENCODE 8 CHANNELS.
ENCODE DECISION LEVELS
Compressing AID conversion with the DAC-86 requires a
comparator, an exclusive-or gate, and a successive
For positive inputs, current flows into IOE( +) through R1,
and the comparator's output will be entered as the answer
for each successive decision. For negative inputs, current
flows into IOE( -) through R2 developing a negative voltage
which is compared with the analog input. An exclusive-OR
gate Inverts the comparator's output during negative trials
C = chord no. (0 through 7)
8 = step no. (0 through 15)
NORMALIZED ENCODE LEVEL (SIGN BIT EXCLUDED) Ie. s=2[2C (8+ 17) -16.51
STEP
~
0
1
2
3
4
5
6
7
000
001
010
011
100
101
110
111
0
0000
1
35
103
239
511
1055
2143
4319
1
0001
3
39
111
255
543
1119
2271
4575
2
0010
5
43
119
271
575
1183
2399
4831
3
0011
7
47
127
287
607
1247
2527
5087
4
0100
9
51
135
303
639
1311
2655
5343
5
0101
11
55
143
319
671
1375
2783
5599
6
0110
13
59
151
335
703
1439
2911
5855
7
0111
15
63
159
351
735
1503
3039
6111
8
1000
17
67
167
367
767
1567
3167
6367
9
1001
19
71
175
363
799
1631
3295
6623
10
1010
21
75
183
399
631
1695
3423
6879
11
1011
23
79
191
415
863
1759
3551
7135
12
1100
25
83
199
431
895
1823
3679
7391
7647
13
1101
27
87
207
447
927
1667
3807
14
1110
29
91
215
463
959
1951
3935
7903
15
1111
31
95
223
479
991
2015
4063
8159
2
4
8
16
32
64
128
256
STEP SIZE
PAGE 13-6
DAC·86 COMPANDING D/A CONVERTER
to maintain the proper logic coding, all ones for full scale
and all zeros for zero scale. (A more complete schematic is
shown in the applications section).
The bits are converted with a successive removal technique,
starting with a decision at the code 011 1111 and turning off
bits sequentially until all decisions have been made.
ENCODE TRANSFER CHARACTERISTICS
(AID CONVERSION)
DIGITAL
OUTPUT 1+)
The decode mode of operation is selected by applying a
logic "0" to the Encode/Decode input. This enables the 100
outputs, disables the 10E outputs and, allows loo( +) or
loo( -) to be selected by the Sign Bit input. When the Sign
Bit input is high, a logic "1", all of the output current flows
into loo( +) forcing a positive voltage at the operational
amplifier's output. When the Sign Bit input is low, a logic
"0", all of the output current flows into loo( -) through R2
forcing a negative voltage output. Since the Sign Bit only
steers current into loo( +) or loo( -), the output will always
be symmetrical, limited only by the matching of R1 and R2.
DECODE TRANSFER CHARACTERISTIC
(O/A CONVERSION)
ANALOG
OUTPUT 1+)
DIGITAL
OUTPUT 1-)
BASIC DECODE OPERATION
(EXPANDING D/A CONVERSION)
ANALOG
OUTPUT (-I
DECODE OPERATION
D/A conversion with the DAC·86 may be illustrated by using
an operational amplifier connected to the decode outputs.
II
U)
0
1
2
3
4
5
6
7
~
000
001
010
011
100
101
110
111
III
2079
4191
C = chord no. (0 through 7)
5 = step no. (0 through 15)
NORMALIZED DECODE OUTPUT (SIGN BIT EXCLUDED) Ie, s = 2[2C (5 + 16.5) -16.5]
~
STEP
0
0000
0
33
99
231
495
1023
1
0001
2
37
107
247
527
1087
2207
4447
2
0010
4
41
115
263
559
1151
2335
4703
3
0011
6
45
123
279
591
1215
2463
4959
4
0100
8
49
131
295
623
1279
2591
5215
5
0101
10
53
139
311
655
1343
2719
5471
6
0110
12
57
147
327
687
1407
2847
5727
7
0111
14
61
155
343
719
1471
2975
5983
8
1000
16
65
163
359
751
1535
3103
6239
9
1001
18
69
171
375
783
1599
3231
6495
10
1010
20
73
179
391
815
1663
3359
6751
7007
11
1011
22
77
187
407
847
1727
3487
12
1100
24
81
195
423
879
1791
3615
7263
13
1101
26
85
203
439
911
1855
3743
7519
14
1110
28
89
211
455
943
1919
3871
7775
15
1111
30
93
219
471
975
1983
3999
8031
2
4
8
16
32
64
128
256
STEP SIZE
PAGE 13-7
Z
o
~
u
Z
:)
:Ii
:Ii
o
U
IU
..I
IU
....
DAC·86 COMPANDING D/A CONVERTER
NORMALIZED TABLES
BASIC Di:CODE CONNECTIONS
The encode and decode tabl.es may be used to calculate
ideal output current at any point. For example, in decode
mode at 13,7 (011 0111) find 343. 343/8031 times IFS of
2007.75pA equals 85.75pA. Alternatively, use the condensed
current tables and add up the number of steps.
Rl1
18.94k!l
(RREFI
BASIC REFERENCE CONSIDERATIONS
R,2
Full scale output current is ideally 2007.75pA when the
reference current is 528pA in the decode mode. In the en·
code mode it is 2039.75pA because the additional 1/2 step
adds 32pA to the output. A percentage change in IREF caused
by changes in VREF or RREF will produce the same percent·
age change in output current.
2Ok.ll
'REf '"
The large step size at full scale allows the use of Inexpen·
sive references in many applications. In some situations
VREF may even be the positive power supply. For example,
with V+ = 15V, RREF= 15V/528pA or 28.4kO. When using a
power supply as a reference, R11 should be two resistors,
R11A and R11B, and the junction should be bypassed to
ground to provide decoupling.
ElD SB B1 B2 B3 B4 B5 B6 B7
POS FULL SCALE
NOTE: THIS CONFIGURATION WILL DECODE 24 CHANNELS.
REFERENCE AMPLIFIER SETUP
The DAC-86 is a multiplying D/A converter in which the out·
put current is the product of the normalized digital Input and
the input reference current. The reference current m"y be
fixed or may vary from nearly zero to + 1.0mA. The full scale
output current is a linear function of the reference current
and is given for all four outputs in the figures above.
EO
5.019V
(+) ZERO SCALE + 1 STEP
0
( + ) ZERO SCALE
0
( - ) ZERO SCALE
0
0
0
( -) ZERO SCALE + 1 STEP
0
0
NEG FULL SCALE
0
0
0
0
0
0
0
In positive reference applications an external positive
reference voltage forces current through R11 into the VFd +)
terminal (pin 11) of the reference amplifier. Alternatively, a
negative reference may be applied to V~ -) at pin 12;
reference current flows from ground through R11 Into V~ +),
as in the positive reference case. This negative reference
connection has the advantage of a very high impedance
0.0012
ov
0
0
0
0
1
~=:;
IDEAL VALUES:
'REF'" 528.uA
/FS'" 2016,.-.Id-I-HllI1I--t
z
030
SO
is
5~ ~~-H~~h4~~~~~~H4m
~ ~~~~~~~~~~~~~~
I
~20
~
r--;:
~~
........ ........
~
W20
I
I RS
~ 10kb
:::::::::--- J
T~r-- :::::
i'-
RS = 2.skn ..........
~~
+
10k
lOOk
lMEG
10MEG
......
~t--
I
'tOL..J...J...J..wJ!L..JLll.wJ!l.-Lll.wJ!l.-LlJ..lJJJJI
lk
i'-r-,.
10
-10 -8 -6 -4 -2
FREQUENCY (Hz)
0
2
100 ~.t--
4
6
8
-2000
10
-
-1200
~---
-400
0
400
1200
2000
IS - SWITCH CURRENT (pAl
ANALOG VOLTAGE (V)
TYPICAL APPLICATION
FOUR-CHANNEL SHARED CHANNEL PCM CODEC
MULTIPLEXER
DE·MULTIPlEXER
I•
D/A
IN
~GITALt
ENCODE
SECTION
SECTION
ANALOG
CHANNELS'
OAC·
86/87
8-8IT
8-81T
DATA
LATCH
ANALOG
CHANNELS
OUT
BUS
en
z
DeCODe
o
~
o
Z
;:)
CHARGE TRANSFER
TEST CIRCUIT
TYPICAL CHARGE TRANSFER
OF OMX-88
TYPICAL CHARGE TRANSFER
OF CONVENTIONAL BI-FET
SWITCH·
::E
::E
o
oW
..J
W
I-
RL = lmfi
CL .1000pF
TOP TRACE: ADDRESS INPUT
BOTTOM TRACE: DRAIN OUTPUT
PAGE 13-35
TOP TRACE: ADDRESS INPUT
BOTTOM TRACE; DRAIN OUTPUT
DMX·88 8·CHANNEL ANALOG DE·MULTIPLEXER FOR PCM CODECs
A.C. TEST CIRCUITS
SWITCHING TIME - TON AND TENABLE
BREAK·BEFORE·MAKE DELAY
INPUT
(SEE
INPUT5V-~
DRIVEov~
-,---
{
BELOW)
+lSV
V+
D81-......_~<> VOUT
FOR SWITCHING TIME:
EN = +5Vdc
AO, " 2 SWITCHED FROM OVdc to +5Vdc
CL
LOGIC
CL·,0pf
INPUT
OR l00pF
FOR ENABLE DELAY
AO. 1.2 = +5Vdc
EN SWITCHED FROM OVdc TO +5Vdc
FIGUAE 3.
fiGURE 1.
OFF ISOLATION MEASUREMENT CIRCUIT
CROSSTALK MEASUREMENT CIRCUIT
+15V
ALL CHANNELS ARE OFF
CHANNEL 4 IS ON
+5V
":'"
0----1...-;;:""00--.----,
EN
CL
10pf
+O.4V
OfF ISOLATION .. 2OLOG
~
Vo
V+
A2
AI
+5V
AD
t -.......--.Vo
t--..-_--oVo
'-="--=.1
RL
"" -=
fiGURE 4.
FIGURE 2.
"':'"
r
CL
lOp'
APPLICATIONS INFORMATION
These de-multiplexers employ ion·implanted JFETs in a
switch configuration designed to assure break-before-make
action. The turn-off time is much faster than the turn·on
time to guarantee this feature over the full operating
temperature and input voltage range. Fabricated with BIFET processing rather than CMOS, special handling Is not
necessary to prevent damage to this multiplexer. Because
the digital inputs only require a 2.0V logic "1" input level,
power-consuming pullup resistors are not required for TTL
compatibility to insure break-before-make switching as is
most often the case with CMOS devices. The digital inputs
utilize PNP input transistors where Input current is maximum at the logic "0" level and drops to that of a reversebiased diode (about 10nA) as the input voltage is raised
about ",1.4V.
The ON resistance, RON, of the analog switches is constant
over the wide input voltage range of -15V to +11V with
VSUPPLY ±15V. Higher input voltage is tolerable provided
that some form of current limiting Is employed (such as that
of an op-amp output stage) to avoid exceeding Junction
temperature and power dissipation requirements. For normal operation, however, positive Input voltages should be
restricted to 11V (or 4V less than the positive supply). This
assures that the VGS of an OFF switch remains greater than
=
its Vp, and prevents that channel from being falsely turned
ON. When operating with negative input voltages, the gateto-channel diode will be turned on if the voltage drop across
an ON switch exceeds -0.6V. While this condition will
cause an error in the output, it will not damage the switch.
CROSSTALK IN PCM SYSTEMS
In PAM .or PCM systems crosstalk specifications for components, such as multiplexers or de-multiplexers, are
related to overall system crosstalk specifications in a complex manner. Component specification must, of necessity,
refer to the operation of the multiplexer In a non-sampling
mode of operation. When rapid sequential sampling takes
place, such as would be the case with a typical sharedchannel COOEC, crosstalk will be caused by the off Isolation properties of the multiplexer as well as by storage
elements on chip and PC card stray capacitance. For example, the capacitance has the effect of conferencing the
channels and increasing crosstalk. Thus, system crosstalk
In a shared-channel PCM COOEC is influenced by multiplexed
characteristics as well as PC card layout and the timing
relationship between the multiplexer and the sample-hold
circuit.
PAGE 13-38
MUX-88
PMI
a-CHANNEL ANALOG MULTIPLEXER
FOR PCM CODECs
OVERVOLTAGE PROTECTED
FEATURES
•
Compatible with Standards for Noise and Crosstalk In
Telephony Systems
•
Pin Compatible with OG508, HI-508A, LF11508
•
JFET Switches Rather Than CMOS
•
Low "ON" Resistance - 2200 1}tplcal
•
Low Output Leakage Current - 100nA Maximum
•
Digital Inputs Compatible with TTL and CMOS
•
No Pullup Resistors Required to Ensure Break-Before-Make
Action with TTL Inputs
systems. Typical crosstalk at 20kHz is 98dB. Monolithic
construction makes possible this kind of performance while
keeping the price reasonable. The MUX-88 makes use of
digital logic to select the one-of-eight channels to be
presented to the multiplexer output. In addition, there is an
ENABLE input which permits turning OFF all channels. Using
this function permits selection of any given multiplexer in a
system employing multiple devices.
The MUX-88 is a 8-channel analog multiplexer which is
ideally suited for use in shared-channel PCM CODEC
Fabricated with Precision Monolithics' high performance
SI/FET technology, this device offers low, constant "ON"
resistance. In addition the multiplexer has fast settling
times and low leakage currents necessary to satisfy the requirements of a 8-channel PCM CODEC. This multiplexer
does not suffer from latch-up and is highly resistant to static
charge blow-out problems associated with similar CMOS
parts. The digital inputs are designed to operate from both
TTL and CMOS levels while always providing a definite
break-belore-make action without the need lor external pullup resistors.
FUNCTIONAL DIAGRAM
PIN CONNECTIONS &
ORDERING INFORMATION
GENERAL DESCRIPTION
ENABLE
A2
AO
A1
•
v+
GND
v-
III
Z
DRAIN
sa
IrI
SO
S6
S4
S3
S2
o
.,
TOP ViEW
16·PIN HERMETiC DUAL·iN-liNE
(Q·Suffix)
TRUTH TABLE
A.,
A,
Ao
EN
"ON"
CHANNEL
X
X
X
L
NONE
L
H
L
L
L
H
H
L
H
L
H
L
H
H
H
H
L
H
L
H
H
H
H
H
U
W
....I
W
I-
RON
3
4000
5200
6
H
H
H
:i!
:i!
o
H
H
~
Z
::I
8
PAGE 13-37
MODEL
MUX-88EQ
MUX·88FQ
TEMP RANGE
INO
INO
MUX-88 8·CHANNEL ANALOG MULTIPLEXER FOR PCM CODECs
ABSOLUTE MAXIMUM RATINGS (TA=25°C unless otherwise noted)
Operating Temperature Range,
V + Supply to V - Supply ................... '. . . . .. 36V
MUX-88EO, FO .................... -25·e to +85·e
V+ Supply to Ground ............................. 18V
Storage Temperature Range ..... " . .. -65·eto +150·e
Logic Input Voltage ................ , ......... -4Vto V+
Power Dissipation ........................... 500mW
Analog Input Voltage ............... V- Supply -20VtoV+
Derate about 100·e ...................... 10mW/·e
Maximum Current Through Any Pin ............... 25mA
Lead Soldering Temperature . . . . . . . . . . . .. 300·e (60 sec)
ELECTRICAL CHARACTERISTICS These specifications apply for V+ = 15V, V- = -15V and -25·C sTA s85·C unless otherwise
specified.
MUX-88F
MUX-88E
PARAMETER
SYMBOL
CONDITIONS
MIN
"ON" Resistance
RoN
Vo=OV.ls=100pA
..lRON With Applied Voltage
..lRON
-10V",Vosl0V,ls=100pA
1.5
25
TYP
MAX
MIN
TYP
MAX
520
400
4.5
UNITS
11
%
11
RON Match Between Switches
RON Match
V o =OV,ls=l00pA
Source Current (Switch "OFF")
ISIOFF)
Vs= 10V, Vo= -10V (Note 1)
10
30
10
nA
Dra)n Currenl (SWitch "OFF")
IOIOFF)
Vs =10V, Vo= -10V(Note 1)
100
100
nA
Leakage Current (Switch "ON")
IOION)
Vo = 10V (Note 1)
100
100
Digital "1" Inpul Voltage
VINH
2.0
2.0
nA
Volts
Digital "0" Input Voltage
VINL
0.8
0.8
Volts
Digital Input Current
liN
V'N = 0.7V to +5V
20
20
pA
Digital "0" Enable Current
I'NLIEN)
VEN=0.7V
20
20
pA
Positive Supply Current
1+
All Digital Inputs Logic "0"
15
15
mA
Negative Supply Current
1-
All Digital Inputs Logic "0"
Switching Time
tTRAN
Figure 1 (Note 2)
ts
10V Step 0.10%
1.3
1.7
Output Settling Time
ts
10V Step 0.05%
1.5
1.7
,..ec
Is
10V Step 0.02%
2.3
1.7
,..ec
Figure 3
0.8
1.0
,..ec
1.0
1.2
,..ec
5.0
1.0
1.3
5.0
1.5
2.1
mA
,..ec
,..ec
Break·Belore·Make Delay
tOLY
Enable Delay "ON"
IONIEN)
Enable Delay "OFF"
tOFFIEN)
0.2
0.2
,..ec
"OFF" Isolation
ISOOFF
(Note 4)
88
88
dB
Crosstalk
CT
(Note 3)
98
98
dB
Source Capacitance
CS(OFF)
Switch "OFF", Vs=OV, VO=OV
2.5
2.5
pF
Drain Capacitance
CD(OFF)
Switch "OFF", Vs=OV, Vo=OV
7
pF
Input 10 Output Capacitance
COSIOFF)
(Note 4)
0.3
pF
0.3
NOTES:
1.
~~~3;i~~O~~ /g~I:~~ ~~~ro":f~~u:e~~y i~~~~: :~~~t~'~~~:~~:~~~'t~:~
"ON."
2. Sample tested. The measurement conditions of FIGURE 1 Insure worst
case transition time.
3. Crosstalk Is measured by drivi'l9 channel 8 with channel 4 ON.
RL =lMO, C L =10pF, Vs=5V R S,I=20kHz.
4. OFF Isolation Is measured by driving channelS with ALL channels OFF.
RL = lkll, CL= 10pF, Vs=5V RMS, f=20kHz. Cos Is computed from the
OFF isolation measurement.
PAGE 13-38
MUX-8a a·CHANNEL ANALOG MULTIPLEXER FOR PCM CODECs
TYPICAL PERFORMANCE CURVES
SWITCH LEAKAGE CURRENTS
VB ANALOG INPUT VOLTAGE
v~
II
15V
15V
TA
2.5"C
SWITCH LEAKAGE
CURRENTS VB TEMPERATURE
y. ,~v"
~. ,1~v
I
1.0
i1 !=-=-~r=~"",,~~ . . . +
IOIOFF)
I
VD •.
- _ .,-.:==
.
--
---.-~~
0 10
.
i
IS(OFF)
0.01
~~~~==~~~~
VA -
"RL = lMn, CL = 10pF, VI = -500mV
VOLTAGE = 500mV/DIV, TIME = I"S/DIV
SEE TRANSISTION TIME CIRCUIT
-
..;i
'ii'
I--
..-1--
~~
f--" ......
COIOFF)
f--"
crOT
-
o.o.~L.c:-c,L:c--,J''''::--:':':''':-5:::''':':'C-::''"::'':-::':::,-,:'
TEMPERATURE (CI
ANALOG INPUT VOlToIUlE (V)
LARGE SIGNAL SWITCHING
"'":-1IV
TA:26"C
ISIOFF)
, / IDION)
0.001+-,,--,+-,--.,+---,+---,"--,,1-'---1
V.L.J
.. t-== ='i==:f::=r==l
r~: :=-~~::--
-i·
SWITCH CAPACITANCE
VB ANALOG INPUT VOLTAGE
BREAK·BEFORE·MAKE SWITCHING
~
~
~
~
0
2
4
6
8
IIA _ ANALOG INPUT VOL rAGE (VOLTSI
TRANSITION
TIMES VB TEMPERATURE
•
"VOLTAGE = 500mV/DIV, TIME = 500nS/DIV
SEE BREAK·BEFORE·MAKE CIRCUIT
"TOP WAVEFORMS: DIGITAL INPUT -5V/DIV
BOTTOM WAVEFORMS: MULTIPLEX OUTPUT - SEE PHOTO
fI)
Z
SMALL SIGNAL SWITCHING
SMALL SIGNAL SWITCHING
WITH FILTERING
ENABLE DELAY
TIME VB TEMPERATURE
o
V52-vse =ov
u
W
AZ:1IC.U
MUXB8E
V51 :lOV
MUKalF
...I
W
VSl =2V
MUX88E
'ON
r----
M:::F~~
M~~:~
va = +500mV VOLTAGE = 500mV/DIV,
TIME = I"S/DIV
*RL = lMn, CL = IOpF, Vs = +10V
VOLTAGE = 5V/DIV, TIME = I"S/DIV
SEE TRANSISTION TIME CIRCUIT
SEE TRANSITION CIRCUIT
PAGE 13-39
Z
;:)
2
2
y. -'16V
Y-=-16V
*RL = lMn, CL = 500pF, vI = -500mV,
o
~u
26
60
76
TEMPERATURE "C
I-
MUX·88 II-CHANNEL ANALOG MULTIPLEXER FOR PCM CODECs
TYPICAL PERFORMANCE CURVES (continued)
OFF PERFORMANCE
OF CHANNEL 8
RON vs SWITCH VOLTAGE (VsC>
RON vs SWITCH CURRENT (lsl
MUX-88
...
I~4oo_~ST
«
~
-
= 15\1
= %SC
TA
~ ~sI"
1
r
0
- 1!iV
".
MUxa7
r
MUX.aF
v"
.
~300-
v·
D
MUX-88E_
MUX88E
I
;
OFF ISOLATION: RL'" 1KII. Cl '" 10pF. Vs '" 5\1 RMS
lOOK
FREQUENCY IHtl
1 MEG
~.
- -- --- - ,.
Vs -
,
SWITCH VOlTAGE ImV)
I--
-2000-1600-1200 -800 -400
Is -
0
400
800 1200 1600 2000
SWITCH CURRENT ,,,,AI
TYPICAL APPLICATION
EIGHT·CHANNEL SHARED CODEC PCM ENCODER
ANALOG-TO-
DIGITAL
CONVERSION
2.5ku
DIGITAL
OUTPUTS
L----l~~~~~LO~G~IC~r_r_~
.-t-t-HH-l-t---- Vpln 2= 2.5V, Vp ln 3
=2.7V
3.25
3.46
3.75
3.4
3.5
3.75
V
12. Preamplifier Output Low Voltage
VOHL
TA = 25-C. Vpln4' Vptn 2= 2.5V. Vpjn3 = 2.3V
1.25
1.4
1.55
1.2
1.4
1.5
V
13. Preamplifier Input Bias Current
'9
Iptn 2 0r 'pin 3. Note 1
14. Preamplifier Input Offset Current
lOS
Ieln 2" leln 30 Now 1
16. Low Level Output VOltage
VOL
TA ~ 25'C, ILOAD = 15mA, Now 2
17. Differential Output Voltage (Low Level)
YOLO
TA = 25-C.ILQAD
IOH
Vpln 14 = 4.BV, Note 1, Vpin 8 = Vptn 9
TA=25-C
Toe
AC Test Circuit
15.
~ 18. High Level Output Leakage Current
S
O
18. Output Pulse Aise Time
!
0.05
v
0.65
=15mA. Note 2
=2OV.
0.8
0.95
0.02
0.05
0.65
0.8
0.95
V
0.15
0.02
0.15
v
50
0.05
50
30
21.
Output Pulse Width
Pw
AC Test Orcult
22.
Pulse Width Differential
Pwo
AC Test Circuit
23.
Bipolar Vlolatlona at Muimum Density
BV1 MAX
Repeater Test Circuit Line Atten. "" 6-38dB
Input Pattern
U
0.05
30
ns
~2~0.~O~U~IP~U~IP~U=IH~F=81~IT~I=m~.____________~T~~~_____A~C~Tu~tC~I=ro=u~lt________________________~10~______________='0~__________~M~
24. Bipolar Violations with Quasl·Random
~-
1.0
Output VOltage Swing
:
$
1.0
BVRMAX
324
ns
324
na
Repeater Teat Circuit Une Atten. = 8-38dB
15
25. Tank Emitter Follower Ba.. Current
Ipin 14' Note 1, Vpln 14 = 4.9V
28. Tank Input Impedance
Measured from pin 14 to pin 15
27. Oscillator Bias Current
NoW " Vpln 14 = 3.9V (10sc-1T81
10
30
50
10
30
50
Set Vpln ~pln 5 = ±1.4V. Vpln 14 = 3.BV
75
120
160
75
120
100
3.2
4.0
4.8
3.2
4.0
4.8
kO
1.35
1.5
1.65
1.35
1.5
1.65
V
0.85
1.0
1.2
0.9
1.06
1.25
V
0.65
0.75
0.65
0.65
0.75
0.65
V
28. Oscillator Injection Current
29.
(lIN.IOSC I
Measured from pin 11 or pin 12 to pin 15.
Delay Circuit Resistor
TA=25'C
Differential voltage, meuured between pins
4 and 5, required to trip Peak Detector.
TA =2S-C
30. ALBO Threshold
Differential yoltage. measured between pins
4 and 5, required to drive Fullwave Rectifier.
31. Clock Threshold
15
300
kO
300
TA=25'C
!I
Differential Yoltage, measured between pins
4 and 5. required to trip Logic Threshold.
TA=2S-C
32. Logic Threshold
I
33. Clock Threshold as '" of ALBO VOltage
TA=25-C
34. Logic Threshold as .. of ALBO VOltage
Measured at pin 16.
35. ALBO ON ~IWg.
IVp4-YpSl = ALBO Threahold
66
70
85
72
76
47
50
53
46
49
52
1.0
1.7
2.5
1.0
1.7
2.5
V
75
mV
Measured at pin 16 and pin 1
Note 1. TA =2S-C
36. ALBO OFF Voltage
Minimum ALBO Diode Resistance
RoMln
38. Maximum ALSO Diode Resistance
RoMax
37.
62
75
o
30
30
kO
NOTI!8:
1. Vpln 2 = 2.5V, adjust Vpl n 3 untn Vpln 4 = Vpln 5-
2. A dynamic test, pin 2 = 2.5V, ·pln 3 pulsed at 100Hz rate. pin 14 pulsed at 200Hz rate.
PAGE 13-46
XI
~
-I
I
CO
.....
en
i:
~
!:
~~
T~NK
D~~AV
G,:OUND
DE1~AY
4{04'
R42
4K
+--t--H~'023
027A
~Q27B
D1
f--t::
2A "-}~D5
D2
D4
~ =
Q228"
024A
Q2SB
Q24B
~Q268"
Q26A
~
~
1"11
~
;~BO
FI~TER
~
rh
h
H
Q20
I
R3
!~kKR2
;F
UK T.OK
P:EAMP
A5
.
Q3A
~Q2AT ~ 'I~'-R6
16K
R4
t~K gK
f8iB h..)"
~ 1-....
INPUT - ,
P:EAMP
INPUT +
Q2BA
Q4
1:
RB
200
R7
16K
Q8A
JJf
:
R12
¥11B
l1A
rj) rj)
Y 'T
~
____ .. _ -
TELECOMMUNICATIONS
I
___ ... _
RPT-81/82
~
ff '
07A s:nn
R11
~
---1""
m
T
QFS 010
OH~<-=-=--I>I-"1(0-F-9-H
~052
f
~
DRIVER
OUTPUT
I
-;4
'V
I
-
~
~
:R16",
~;0l-'OB_+ ~
__
437n
Nl2A
I
OF17
&,r
~I
::II
::II
DRIVER
OUTPUT
I~
::II
1"11
'B
'V
1"11
~~n
~Q8A
I
II
n
I:
n
r;TS0
047
R18
1733n
I::II
IS
Q128
R14
1733n
0
~'V
rh
j01DA
s:
>
Ij
~
r~
437n
05
R9
200
~Q3OB_
Q30A
~'
loOA ~
~~
R10
7DOn
~~
D14
~Q48
Q7B
0 68
JQ31
I
i
0
:I:
r;;-S
D1~
~Q28_B
Q50
=
OUTPUT
~Q29B
J,
<;;'
0
Q32
Q29A
I~
en
------
011
H
OUTPUT
8
am
DIGITAL
GROUND
L -_ _ _ _ _ _ _ _-j 7
PREAMP
4
PREAMP
OUTPUT + 5 OUTPUT-
lSUBSTAATE
TEST CIRCUIT
+4.4V
o
O.1,..F
68.
BOURNS PIN
4265-1199
lOp'
.. 8V
Vo
RPHI1/RPHI2 ARE TESTED IN A MODIFIED
T1 CARRIER REPEATER CIRCUIT. THE OUTPUT
-THE
400
REG
our·
400
TRANSFORMER IS REPLACED BY RESISTORS IN
ORDER TO MEASURE THE OUTPUT AC PARAME·
TERS OF THE CHIPS.
L-------------------~--o ~.w
PAGE 13-48
RPT-81/RPT-82 PCM CARRIER REPEATERS
TYPICAL REPEATER POWERING ARRANGEMENT
GROUND PIN
Vee,
(4.4V!
VCC2
16.BV)
RPT·Sl/RPT·82
primary (50% d.f.) for the U.S. or a 6.0 volt pulse
across a 4800 transformer primary (50% d.f.) for
CCID. These currents compute to 15mA and 12.5mA
respectively (for both sides).
REPEATER CURRENT REQUIREMENTS
For comparison to CCIT or AD specifications it is convenient to estimate total repeater current requirements.
Repeater current is typically calculated in the following
manner:
iv. ALBO diode current is 26mV divided by the minimum;
required ALBO resistance (approximately 80).
Typically worst case is 6.5mA (for both sides).
i. Each of the two zeners used as regulators have idle
current requirements of approximately 1.0mA (2mA).
ii. Total no-signal supply current, from the electrical
characteristics table, is 13.0mA (guaranteed maximum) for each side.
Adding the currents calculated into the currents calculated
in ii, iii, and iv gives the following typical repeater current requirements:
i. U.S. . ......... 49.5mA (worst case all ones output)
iii. To compute worst case (all ones) output current
assumes a 6.0 volt pulse across a 4000 transformer
ii. Europe ....... 47.0mA (worst case all ones output)
II
N
APPLICATIONS INFORMATION
In a typical repeater system extensive external circuitry is
required. The regulator network, assembled from zener
diodes and resistors is used to power the integrated circuit.
Normally one common circuit is provided for the two ICs
operating in opposite directions. Input and output transformers are used to couple the transmission lines. The input
one-to-one transformer has secondary loaded with a line
matching resistor to avoid reflections on the input lines. An
attenuator network may be installed after this input transformer as a fixed line-build-out pad. Feedback resistors are
used to set the DC bias of the circuit. Additionally the bias
network is connected to a fixed resistive voltage divider to tie
the biasing network to a fixed potential. The ALBO network
consists of a series impedance and a shunt impedance where
the shunt impedance is AC terminated to the ALBO diode.
The shunt impedance has both resistive and reactive components to assist in line equalization. The equalizing network is
basically a series tuned circuit in one of the input legs of the
preamplifier whose function is to give the preamplifier a frequency response which corrects for the amplitude and phase
response of the input line. The design of the equalizing network is very important to the system performance. A lag
capacitor across the preamplifier input stabilizes the preamplifier. The output transformer normally incorporates a fault
locating winding which is used, in conjunction with appro-
priate filters, to detect defective repeaters. The input transformer has a center tapped primary to allow for a simplex
powering system.
The RPT-811RPT-82 oscillator allows two modes of operation
controllable by pin 13 (Oscillator Control). When grounded
the oscillator is in a free-running mode. With pin 13 open the
oscillator works in a pulsed, ringing mode. In both cases the
external L-C tank circuit determines the oscillation frequency.
The external delay capacitor (across pins 11 and 12) provides
90· of phase shift through the clock amplifier. For best performance a 10pF silver mica capacitor is suggested.
Oscillator tank circuit a directly affects the clock regeneration circuitry. The effective a of the L-C oscillator tank circuit
must be high enough that ringing will be maintained with
minimum pulse densities. The resonant a cannot, however,
be arbitrarily large, or operating temperature changes and
component aging will cause resonant frequency shifts. The
RPT-81/RPT-82 will operate with a's as low as 75.
In order to provide noise rejection, the analog and digital
grounds have been isolated on chip. Low noise/distortion
operation can be enhanced if the high power output leads
and external circuitry are physically located as far as possible
from the preamplifier inputs. Supply bypassing of V CC1 and
V CC2 close to device pins is encouraged.
PAGE 13-49
E!!
lip
t;:
a:
U)
Z
o
5
(.)
z
~
::!i
::!i
o(.)
W
....I
W
I-
RPT-81/RPT-82 PCM CARRIER REPEATERS
PREAMPLIFIER BIASING SCHEMES
mally occurring common mode output voltage. The best
noise performance is obtained with this system but some
problems are encountered at low temperatures where the
circuittends to turn itself oft In a fixed biased scheme one of
the inputs is biased to a fixed DC level while the other input is
biased to the opposite output in the same manner as with self
bias. Note that with fixed bias a differential output offset will
be caused if the fixed bias is not matched to the normally
occuring output level. If the fixed level is very close to the
normally occuring output level then there is an improvement
in performance at low temperature.
Both inverting and non-inverting outputs of the RPT-811
RPT-82 preamplifier are available so that either self-biasing
or fixed-biasing techniques may be employed. The effect of
the DC biasing is to setthe thresholds ofthe detectors. All the
thresholds move together, the relative threshold which is
defined in terms of a percentage of the peak detector threshold is determined by the resistor string. In a self-biased
scheme the non-inverting output is returned to the inverting
input and the inverting output is returned to the non-inverting
input. In this manner the input leads are biased to the nor-
PREAMPLIFIER BIASING SCHEMES
SELF BIAS
r -::- - -;- - - - - - - - - - - - - INPUT
~~~'6'u~~:~N
0-+-<,......,1",3-1
+2.5Vd,
12 + +
I ~~-r------~--------~------~
I
I.
T+
T-
'l..r
fiXED BIAS
4.4V
':--";;::---11-..--0 TO COMPARATORS
AND RESISTOR
......."---<~+--o STRINGS
3.61k
.. 2.DV
5.11k
PAGE 13-50
:D
~
do
....
......
:D
"....
REGULATOR NETWORK
I
GO
N
Z
~
VCC2
B.BV
"
(;
r-
•....
Vee1
4.4V
~
~
I:
%
N
....
....
:D
"'"'"~
'"
~
:D
I:)
"'...w
(I)
-<
RPT-Bl/
~
RPT-B2
4kn
VCC1~
"'"
3Kg
,
+
5.11k
BIAS FEEDBACK
,..
1''---
/
!a~F
PREAMPLIFIER
INPUT (+)
100pF
5.6k
6.6k
INPUT LAG CAPACITOR
5.1n
BIAS FEEDBACK
RESISTOR
1:1On
566n
4k
VCC1~
"::"
TELECOMMUNICATIONS
RPT-81/82
II
1
EQUALIZING
NETWORK
NOTE:
Tl: BOURNS PIN
OR
T2: BOURNS PIN
OR
Ll: BOURNS PIN
~
!!I
ii
"V
;t
III
'""V
n
iii:
n
»
(I)
....
:D
I:
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iii
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en
I,
RESISTOR
:D
4260-.1520
4285-1153
4285-2007
4285-1152
4265-1199
SMP-81
PMI
TELECOMMUNICATIONS SAMPLE AND
HOLD AMPLIFIER
FEATURES
• Meets System Performance Requirements in
CODECs
Mult~hannel
• Trimmed for Minimum Zero Scale Error ........... 0.6mV
•
Low Droop Rate Over Temperature ............. 0.1,.V/,..s
• Low Aperture Time ............................ SOns
• Fast Acquisition Time 10V Step to 0.1 % •..••.•..•. 3.S,..s
• High Slew Rate .............................. 10V/,..s
• High Sample Current/Hold Current Ratio ........ 1.7 X 108
• DTL, TTL & CMOS Compatible Logic Input
• HA-242S, DATEL SHM·IC-1, and AD-S83 Socket Compatible"
• Low Dissipation
:
unity gain circuit consisting of two buffer amplifiers of very
high input impedance connected by a diode bridge switch.
HIGH ACCURACY AND LOW DROOP RATE
The high input impedance and low droop rate of the SMp·81
are achieved by PMI's ion implant super beta process. The
high input impedance permits high impedance source ap·
plications without degrading accuracy, and low droop rate.
Other features of the SMp·81 include high accuracy, O.6mV
of combined offset voltage and step transfer error, and very
low feedthrough. A diode bridge switch design allows
minimum charge transfer step. On·chip Zener·Zap trimming
eliminates nulling for most applications.
FAST ACQUISITION
• Low Cost
• Feedthrough Attenuation Ratio 96dB
The SMp·81 precision sample and hold amplifier provides
the high accuracy, low droop rate and fast acquisition ideally
required for PCM encoders. The SMp·81 is a non·inverting
A unique super charger or transconductance amplifier provides up to 50mA charging current to the hold capacitor. As
a result, smooth charging of the hold capacitor is achieved
with minimum noise. The super charger, in conjunction with
the high slewing rate input and output buffer amplifiers, per·
mits fast acquisition operation. The adjustable logic input
threshold makes the SMP-81 compatible to all logic families.
FUNCTIONAL DIAGRAM
PIN CONNECTIONS & ORDERING INFORMATION
GENERAL DESCRIPTION
N.C."
OUTPUT
14 PIN DIp· HERMETIC
(Y SUFFIX)
Vzs(mV)
1.6
3.5
3
4
NULL
SMp·81EY
SMp·81FY
• Pins 1 and 8 are not internally connected. In unity gain
applications, the SMP-81 can replace HA·2425, SHM·IC·1
and AD-583 directly.
'SAMPLE/HOLD CONTROL
HIGH = HOLD
LOW = TRACK
PAGE 13-52
SMP-81 TELECOMMUNICATIONS SAMPLE AND HOLD AMPLIFIER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (V + minus V -) .................... 36V
Power Dissipation ............................ 500mW
Input Voltage .................. Equal to Supply Voltage
Logic and Logic Control Voltage .. Equal to Supply Voltage
Output Short Circuit Duration ................. Indefinite
Hold Capacitor Short Circuit Duration ............. 60sec
Operating Temperature Range ......... - 25·C to + 85·C
Storage Temperature Range .......... - 65·C to + 150·C
Lead Temperature (Soldering 60 sec) .............. 300·C
ELECTRICAL CHARACTERISTICS a1 Vs ± 15V, CH= O.005I'F, VLC connected to ground, - 25·C:5TA :5 + 85·C, device fully warmed up,
unless otherwise noted.
PARAMETER
SYMBOL
CONDITIONS
Zero Scale Error (Hold Mode)
VZf3
VIN = OVLOG = 3.5V (500"sec aiter
Hold Command)
Input Bias Current
16
Leakage (Droop) Current
Droop Rate
lOR
dVCH/dt
Input Resistance
RIN
Voltage Gain
Av
Av
Acquisition Time
Aperture Time
Charge Transfer
Slew Rate
Hold CapaCitor Charging Currenl
Feedthrough Attenuation Ratio
Full Power Bandwidth
Input Voltage Range and/or
Output Voltage Swing
Output Resistance
Power Supply Reiection Ratio
Power Consumption (DC)
Logic Control Input Current
Logic Input Current
Differential Logic Threshold
Hold Mode Settling Time
Not.: Guaranteed by design.
t.
Ot
SR
ICH
Fp
Ro
PSRR
Po
ILC
ISiH
ISiH
MIN
VIN = OVLOG = 3.5V
VIN = ±10V RL=2.5KO
VIN - VOUT'" ±3 volts
Input -2OVp.p 1kHz (See note)
± 10Vp-p (Dissipation Limited)
RL=2.5KO
RL=2.5KO
3.5
225
10
2.0
120
0.5
0.1
5xlO'O
450
nA
20
4.0
nA
3xl0 '0
105
0.5
0.1
6xl0 '0
0.99960
0.99960
0.99980
0.99960
0
0.99978
0.99976
VN
VN
3.5
"s
50
nsec
5
10
5
10
50
90
1.00
±11.5
±11.5
0.15
50
96
Sample Mode VSlH = 0.6V
Hold Mode VSlH = 5.0V
0.99955
mVlmsec
50
30
60
1.5xl0'0
mV
3.5
86
-6
5V step to within lmV of final value
UNITS
0.9
0.8
tHM
SMP-81F
TYP MAX
1.6
±10
±10
Sample Mode Vs= ±9V to ±laV
Sample Mode VIN = 0
MIN
0.6
VIN=O
Device Warmed Up
Sample Mode
VIN= ±10V RL=5KD
orVIN= ±5V RL=2.5KD
10V step to within 10mV of
final value (0.1 %)
SMP-81E
TYP MAX
100
±11.5
±11.5
0.15
90
160
-3
-15
0.6
1.3
1.5
20
60
±10
±10
75
160
-9
-45
2.0
0.8
pC
V/"s
mA
dB
kHz
V
V.
n
90
170
-3
-15
0.6
1.3
1.5
210
dB
mW
~
-45
~
2.0
nA
V
I ...
ap
Go
~
II)
II)
"s
Z
0
~
DEFINITION OF TERMS
ZERO SCALE ERROR
current IDR Is defined positive when its direction is into the
C H pin.
The magnitude of the output voltage when the circuit is
switched from sample to hold mode while holding the input
at zero volts. Zero Scale Error Vzs is the algebraic sum of the
offset voltage and the charge transfer step Voltage. Vzs can
be adjusted to zero (see Zero Scale Error null adjustment).
INPUT BIAS CURRENT
The current into the input terminal with input voltage held at
zero volts.
DROOP RATE
Droop rate dVcHldt is the rate of change of output voltage
while the circuit is operated in the hold mode dVm/dt is a
direct function of droop current IDR and related by the equation
dVCH
IDR
- - = - x 1 03
dt
CH
where dVci/dt is expressed in p.V/ms with IDR in microamperes and C H in microfarads.
LEAKAGE (DROOP) CURRENT
INPUT RESISTANCE
The current which flows out of holding capacitor C H while
the circuit is operating in the hold mode. In general droop
The ratio of the AC change in the input current as a result of
the change in the input voltage.
PAGE 13-53
0
Z
:::l
~
~
0
0
w
...I
w
t-
SMP-81 TELECOMMUNICATIONS SAMPLE AND HOLD AMPLIFIER
VOLTAGE GAIN
The ratio of the output voltage to the input voltage with the
circuit operating in the sample mode.
ACQUISITION TIME
The minimum time for the output voltage to begin tracking
the Input voltage, to within a specified error band, after the
Inception of the sample command. By convention, acquisition time is defined for sampling of a DC level. For instance,
a circuit which is "holding" a 10V output signal, and
operating with zero input volts, is switched to the sample
mode. The acquisition time is then the time required for the
output to decrease to within a ± 10mV band about ground
potential.
cuit, slew rate must be defined with a specified value of
holding capaCitor CH. For the SMP-81, slew rate can either
be measured by operating the circuit in the sample mode
and applying a step function to the input, or by applying an
input voltage which differs from the output voltage, with the
circuit in the hold mode, then switching to the sample mode
and observing the rate of change of the output voltage.
HOLD CAPACITOR CHARGING CURRENT
The current ICH which charges, or discharges, the capaCitor
while the circuit is in the sample mode.
SAMPLE/HOLD CURRENT RATIO
The ratio of the peak charging current available to the droop
current.
APERTURE TIME
The time between the inception of the hold command and
the time the circuit output ceases tracking the input signal.
When the holding capacitor charging current is less than
O.3ma the aperture time is nominally 5Ons. The aperture time
is a function of the holding capaCitor charging current ICH.
The charging current is in turn a function of the rate of
change of the Input signal voltage. This relationship holds
true up to a maximum of 50mA which is the maximum current available from the SMP-81 to charge holding capaCitor
CH. Charging current can be calculated from the rate of
change of the input analog and the size of CH by the equa·
tion:
dv
ICH=C-(lcH= 50mA Max.)
dt
FEEDTHROUGH ATTENUATION RATIO
The change of voltage applied to the input as a ratio of the
change of voltage observed at the output, caused by the input disturbance, while the circuit is in the hold mode.
FULL POWER BANDWIDTH
The maximum frequency at which rated output voltage Eor
can be supplied without significant distortion. Full power
bandwidth Fp is related to slew rate SR by the following
equation:
F _
p-
SR
2...Eor
Using this equation, Fp of 160kHz can be computed. This is
applicable only for pulsed conditions. Power dissipation
limits Fp to 100kHz for C.W. operation.
GAIN-ERROR
Voltage difference between input and output voltage minus
the output voltage measured with input at zero volts.
OUTPUT RESISTANCE
CIRCUIT IN SAMPLE MODE
An AC change in output voltage as a result of an AC change
In load current.
HOLD STEP
POWER SUPPLY REJECTION RATIO
Magnitude of step caused in the output voltage by switching
the circuit from sample mode to hold mode.
CHARGE TRANSFER
The amount of charge transferred to the holding capaCitor
due to the action of the switch. Charge is transferred to CH
when the circuit is switched to the hold mode. Charge
transfer causes a change in output voltage AVzs as defin8cJ
by the equation:
0 1 (pC)
AV~V)=--
The change in output voltage for a change in power supply
voltage when the circuit is maintained in the sample mode.
The best power supply rejection ratio PSRR is obtained with
the power supply voltage changing at a very low rate (DC).
For essentially DC conditions PSRR for the hoid mode of
operation is essentially the same as the PSRR for the sam·
pie mode. PSRR is degraded as the frequency of the distur·
bance increases. PSRR for both sample and hold modes is
shown graphically as a function of frequency.
CHANGE IN HOLD STEP
C H (pF)
Note that for 0 1= 5pC and C H= 5000pF offset error = 1mY.
The SMP-81 has been factory nulled for CH= 5OOOpF. For
other values of CH, the zero scale shift can be calculated
from the equation:
01
CH
t:Nzs(V)=- -1mV
Actual hold step less the hold step measured after sampling
V = O. A change in hold step has two components: the first Is
a function of Input voltage; the second Is a function of the
rise time of the S/H voltage. Note that rise time of s/H
voltage also effects ZERO·SCALE-ERROR.
TOTAL ERROR
The algebraic sum of the following factors:
SLEW RATE
The maximum possible rate of change of the output voltage
when supplying the rated output. For a sample. and hold cir-
i. ZERO·SCALE-ERROR
il. Gain Error
PAGE 13-54
SMP-81 TELECOMMUNICATIONS SAMPLE AND HOLD AMPLIFIER
iii. Hold Step Change versus
For proper operation, the VLC (logic control) must always be
at least 3.5V below the positive supply and 2.0V above the
negative supply.
dV(SlH)
dt
vi. Hold Step Change versus Vln
Sample and hold control voltage (S/H) must always be at
least 2.8V above the negative supply.
HOLD MODE SETTLING TIME
The time for all transients to settle to within a specified error
band measured from the inception of the hold command.
HOLD CAPACITOR RECOMMENDATIONS
The hold capacitor (C H) acts as a memory element and
also as a compensating capacitor for the sample and hold
amplifier. For stable operation, a minimum value of 2000pF
is recommended, with no limit set for the maximum value.
The SMP-81 is internally trimmed for CH 5000pF. Other
values of C H will cause a zero scale shift, which can be
calculated from the following equation: a CH of 5000pF has
been empirically determined to be an optimum value for
8-channel shared CODEC operation.
ZERO SCALE ERROR NULL ADJUSTMENT
During the null adjustment, the amplifier should be switched
continuously between the "sample" and "hold" mode. The
error should be adjusted to read zero when the unit is in the
"hold" mode. In this way, both offset voltage errors and
charge transfer errors are adjusted to zero.
=
.1Vzs (mV)
V+
v-
5 (pC) x 103 -1
CH (pF)
=
The hold capaCitor should have very high insulation
resistance and low dielectric absorption. For temperatures
below 85·C, polystyrene capaCitors are recommended,
while teflon capacitors are recommended for higher
temperature applications.
INPUT ~-------'-l
SMP-81 LOGIC CONTROL
SIN 0 - - - - - - - - - - '
The sample/hold mode control of the SMP-81 incorporates a
unique logic input circuit, which enables direct Interlace to
all popular logic families and provides maximum noise immunity. As shown in the figure, the mode control is accomplished by steering the current (1 1) through 01 or 02,
thus providing high speed switching and a predictable logic
threshold. For TTL and DTL interface, simply ground VLC (pin
13). For CMOS, HTL and HNIL interface, the appropriate
threshold voltage, allowing for 2 diode drops for 01 and VBE
of 03, should be applied to VLc.
r-------------~--~V+
V Le
>-''-------0 OUTPUT
I
eH -
&OOOpF
0 -_ _ _ _ _ _ _ _ _ _---"
II
;p
II.
::E
GUARDING AND GROUNDING LAYOUT
UJ
The use of a ground plane is strongly recommended to
minimize ground path resistances. Separate analog and
digital grounds should be used, and it is advisable to keep
these two ground systems isolated until they are tied back
to the common system ground. Digital currents should not
flow back to the system ground through the analog ground
path.
UJ
Z
o
~
o
Z
;:)
::E
::E
o
o
~
W
SlH
(PIN.")
FROM
LOGIC
CONTROL
Q21-----~
Q1
I-
{S/H CONTROL
DIGITAL
GROUND
ANALOG
INPUT
LOCAL
ANALOG
Q3
'-----.----'
CURRENT
VLe
(PIN 131
GROUND
V-
TO CONTROL
SAMPLEI
HOLD MODES
PAGE 13-55
SMP-81 TELECOMMUNICATIONS SAMPLE AND HOLD AMPLIFIER
SMP-81 ACQUISITION TIMES
ACQUISITION TIME
+10V TO OV
ACQUISITION TIME
-10V TO OV
--V-
Ii V
~J,I
I
I
~ - liliiii1
I
I
I
~,
U
,
,
1)1
V
V
1)1
ACQUISITION TIME
-1.0V TO OV
ACQUISITION TIME
+ 1.0V TO OV
V
V
:!!!
II
00.
II
l)1S
1)1
00.
ACQUISITION TIME
+100mV TO OV
ACQUISITION TIME
-100mV TO OV
=-
1- -
.. -1=
--..- ,.- I
1-
=
-
~--
riiii
I
=
1-
1-
,
II,
V
-ii
-
o.V
-~~
~~
:~0I1
-----
V
~1
l'I
:=
I
-liii
~~
--~
I
:lIIIIIi
'
,
II i::!II
o.V
1)1
1)1
HOLD
SAMPLE
PAGE 13-56
SMP-81 TELECOMMUNICATIONS SAMPLE AND HOLD AMPLIFIER
TYPICAL PERFORMANCE CURVES.
100
ar---~--'----r---r--~---'
1
~
+2
TYPICAL D.C. NEGATIVE POWER SUPPL v
REJECTION RATIO = 86dB
r------k~+-____j
811
~SITIVE'~UPPLY'''!
~
~
I
80 I""t'i+lM~,##*(+;;;I';j;VI'I+;I!'VI!IFSI:j:N:tw~T)IlIt:-t+ttttII
Q
w .~-+--4-~~
:::r '~';~'~A~ '~.~:";O~'~;~~'~O;"E~'~~PPLY
REJECTION RATIO = 84dB
I
i +1~-+-~~.-~--+--+-~
~
u
SAMPLE MODE
POWER SUPPLY REJECTION
HOLD MODE
POWER SUPPLY REJECTION
AMPLITUDE CHANGE IN
HOLD STEP vs INPUT VOLTAGE
ti~ .. H-ttIltttf--t1itt1l-HI---f+I-J
-1
;J
~-2~-+--4----+----+-~~--l
i
0:
20
10
LEAKAGE (DROOP)
CURRENT vs TEMPERATURE
0.10
190
180
180
•.9
0.8
"-
~O.7
POSITIVE
DIRECTION
0:
OF lOR
~ 0.6
B 0.4
~
~ 0,3
00.2
•. 1
D••
120
"
I'-...
"
I1t l OR
I'-...
CH
ARROW INDICATES POSITIVE
lOR REGARDLESS OF CH
"-
"
I I
o
+20
+40
TEMPERATURE
rei
....0 !>
-60 -"
....0 0:
c
-20
•.0
+20
+10
g
VOLTAGE POLARITY
-0.1
II
:I:
U
-1oofii
~
:+;
......2
-30 -20
so
-140 ~
;: 0.6
+60
+80 +90
SAMPLE MODE SUPPLY
CURRENT vs TEMPERATURE
INPUT BIAS CURRENT
vs TEMPERATURE
7.0
..
!
.--
_+__
~
~ 5.0 1--f--
30
-f--
~
a
---
~
~
~
CURRENT =
__+__ ...' r--I---.. .. i-::_SUPPLY
TEMPERATURE _
~ r=--::
§
VI
~ ~~E~~=::Ell~V;'S~'~I~.~j
20
~
~
--
I-- .. ---- ...:..
0:
~
.. __ _
_ 6.0 1
I-
~
1-.. ___
to')
4.0
3.0
I.
-40
-20
o
+20
+40
--
SAMPLE MODE
VIN '" o VOLTS
+---+-
2.0
+80
+60
_
I--r--f--. f---I---
+20
-20
TEMPERATURE (OC)
+40
TEMPERATURE rei
+tIO
+811
II
:
:::E
U)
U)
Z
.
GAIN ERROR
_ +3
!w
POWER DISSIPATION vs
FREQUENCY INPUT = Vp sin
0
mW
T A =25'C
SAMPLE MODe
IIII
SOD
mW
" +2
~
IIII
-
0
> +1
V ,N
10V Pk
(20V Pk·Pk)
.v
Pk
(1ov Pk·Pk)
//
~
~
0
w
"~
1.0V Pk
(2V Pk·Pk)
-1
>
~ -2
!
RL = 2.5k
-3
-10
-6
+5
INPUT VOLTAGE (VOLTS)
+1.
1kHz
10kHz
100kHz
INPUT FREQUENCV
o(,)
W
~
2.5V
~
Pk
('V
z
Pk-Pk)
,;-
...I
,~
5V
Pk
lOV Ptt·Pk
1111
POWER> 5DOmW
TEST CONDITIONS
SAMPLE MODE
V+ = 15V
V- = -15V
V LC = O.OO~F
INPUT CENTERED AROUND GROUND
0
:::E
:::E
IOV
Pk
/
[/
111111111
ov
lMHz
POWER DISSIPATION
LIMITED BY
CIRCUIT RESPONSE
10
kH,
100
kHz
500 1
2
kHz MHz MHz
INPUT FREQUENCY
PAGE 13-57
5z
::;)
I
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MAXIMUM INPUT SIGNAL
AMPLITUDE vs FREQUENCY
wt
o
SMP-81 TELECOMMUNICATIONS SAMPLE AND HOLD AMPLIFIER
TYPICAL PERFORMANCE CURVES
OUTPUT WIDEBAND NOISE
vs BANDWIDTH
(0.1 Hz TO FREQUENCY INDICATED)
OUTPUT RESISTANCE vs FREQ
14.0
ROU~ I~1~LD I~~~I~
S!
Ro :"PLE
HOLD CAPACITOR CHARGING
CURRENT vs
INPUT OUTPUT VOLTAGE
,0_
~~~E
12.0
~
!
§. 10.0
~
~
~
>'000
...
i !
8.0
!
6.0
i
,
II
!;
~
-
i
I
4.0
I·
,
;
I
!
i
HOLDMODE --::::
fTim~
~c:' ~
OUTPUT RESISTANCE {nl
0
1'1111111111':11111111111'
2.0
o
111111111 IlUll1 II Ill-
10Hz
100Hz
1kHz
10kHz
INPUT FREQUENCY
'0
100kHz
~
t·
'00
1MHz
.....-:
100kHz
1MHz
BANDWIDTH
'OkHz
10MHz
TYPICAL APPLICATION
EIGHT CHANNEL SHARED CODEC PCM ENCODER'
+-+-+-+-+-+---o}
CH'
~~T~RD
MUX-88
CH20-,---,
:::~~~
CH5O-~
CH6
o--t----'
CH70--+----'
1
2
3
4
5
6
7
8
9
~4
I
15
16
17
o----t:::;:;:;;;:~,.J
lAO JA1JA2JEn
CH~~EL~E~CT
•
+1OV
R11
EIO 58 61 B2 83 54 85 B6 B7
18.94kn
10£(+)
11 +- (RREFI
V R(+)
100(+)
DACo-S8
VRH 1112
IRe
10EI-I
100(-)
vCH6
J
VRE
I
6'3
-15V
V+
6'•
R12
20kU
VLC
~ 10
•
+1SV
lOGIC
SAMPLE}
HOLD CONTROL
WAVEFORMS
CHANNEL INPUT ANALOG
MUX OUTPUT SIGNAL
SAMPLE/HOLD SiHCOMMAND ~
SAMPLE/HOLD OUTPUT
3 4
NULL
PAGE 13-58
SMP-81 TELECOMMUNICATIONS SAMPLE AND HOLD AMPLIFIER
ACQUISITION TIME TEST CIRCUIT
+1OV---,
INPUT
ov ____
J.._______
81;3.: -ll"----i._____
I
OUTPUT
INPUT
+lOV~
OUTPUT
2k!!
ov ________ l~
I
TO SCOPE
5iH
FET
PROBE
0------'
V Le
DIGITAL
ONO
REFERENCE OV - - - - - . . . . . . , - - - - I
I
2ku
ERROR
VOLTAGE
REFERENCE
~'
r--
OV - - - - - -
+- - ~
- -
FINAL VALUE
ACQUISITION TIME
DICE
For applicable DICE information see SMP-11 Data Sheet.
III
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z
o
5z
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:IE
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....
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I-
PAGE 13-59
CUSTOM WAFER
FAB
Custom Wafer Fabrication
INTRODUCTION
CUSTOM PRODUCTS
Since its beginning, PMI has placed emphasis
on precision performance and high quality. At
PMI, high-reliability business is no peripheral
affair; rather it is a fundamental element in the
company's growth plan. As a result of PMI's
stress on quality and reliability, our integrated
circuits have been used in controlling, monitoring and sensing system designs in many
military and aerospace programs including
Viking, Trident, Cruise Missile, Minuteman,
Aerosat, Sparrow Missile, Harm Missile System, Spacelab, Satcom, Voyager, Roland,
Exosat, Stinger Missile, DSCS-3, TDRSS,
AMRAAN, ARIANE, ISPM, SBS, METRO-2,
TIROS-N, IUS, GBU-15, GPS, Intelsat-5, the
Delta launch vehicle, Pathfinder Radar,
Columbia Space Shuttle and many more.
Contributing to the high-reliability capabilities of PMI devices is the use of proprietary
processing techniques including triple passivation. These techniques have made it possible for PMI to develop the world's lowest
noise family of IC op-amps (OP-27/37), featured on the cover of the December 20,1980
issue of Electronic Design Magazine and have
improved the radiation resistance characteristics exhibited by many PMI products.
There is a marked trend toward increased
end-user involvement in the design of integrated circuits. Frequently, an end-user will
have the design accomplished by either inhouse engineering or by an outside custom
design facility. Manufacturing can then be
done by an outside facility. The advantages to
this system are:
1. The user gets precisely the required part.
2. The mask set is owned by the user.
3. Inherent protection of proprietary designs.
4. The user is not tied to one vendor.
S. Control over design and manufacturing
remains with the user.
Additional advantages of dealing with PMI are:
1. Absolute commitment to quality.
2. Technical assistance with mask design.
3. Wide range of available processes.
4. Non-disclosure agreements for particularly
market sensitive products.
S. MIL-M-38510 qualified fab area.
6. Nitride passivation available.
SEPARATE STAFF AND FACILITY
PMl's custom wafer fabrication group occupies a completely self-contained facility for
servicing its customers. The staff of the facility provides customers with high-quality wafer
processing, assurance of a long-term commitment to service-oriented dependable wafer
processing, and access to high-performance
processes not normally available for custom
circuits.
PAOE14-3
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PROCESS TECHNOLOGY
Processes offered by PMI include:
• Linear Bipolar. The entire range of linear
processing, including FET-input op-amps, is
available.
• Transistor Transistor Logic. Aluminum and
PtSiTiW Schottky processes.
• 12 L,ISL. PMI has gained exceptional expertise through processing thousands of highquality wafers.
• Emitter Coupled Logic. PtSiTiW washed
emitter process.
• Complementary Metal-Oxlde.
Semiconductors. PMl's selective-oxideisolated, silicon-gate CMOS process can provide gate delays under 10nsec.
All of the processes mentioned above can be
enhanced with ion implanted resistors and
bases, dual layer metalization, nitride passivation, and thin film resistors. PMl's processes
are compatible with the design rules followed
by leading independent custom IC design
houses whose names can be furnished on
request.
Continuous investigation and implementation
of the latest wafer processing technologies
has helped PMI maintain a position at the
leading edge of integrated circuit development.
Thin film capabilities include AI, AISi, and
PtSiTiW metalization; silicon and nitride passivation; and CrSi reSistors (2kfl/sq.) with
positive TC's of less than 200ppm and matching to 5ppm. An in-house scanning electron
microscope (S.E.M.) routinely monitors
metalization and other processes.
PROCESS CONTROL
As has been previously mentioned, the PMI
custom wafer fabrication facility is qualified
to Military MIL-M-38510. This qualification
requires that all areas be monitored for particulate levels, all diffusion and evaporation
processes are CV plotted for contamination
control, and all in-process parameters are
recorded and retained by lot numbers. (Oxide
thicknesses on actual devices are measured
on NANOMETRIC's non-destructive thin-film
monitor.)
Electrical evaluation on dropped-in die is
recorded and retained using a LOMAC LM-80
System (engineering lots are manually
probed). All incoming materials (wafers,
chemicals, masks) are checked for compliance
to PMI standards.
DESIGN RULES
Design rules and electrical process parameter specifications may be made available for
most linear and digital processes run at PMI.
PROCESS CAPABILITY
PMl's masking operation uses negative resist,
contact printing. Emulsion working plates are
either printed from the customer's sub masters or chrome working plates are obtained
from mask vendors.
PMI uses low temperature techniques for its
epitaxial layer deposition to minimize crystal
defects. Other capabilities include Antimony
buried layer, Boron diffusion (100 to 300
ohms/sq.), ion implanted resistors and bases
(B11), with resistor values from 1000 to 2000
ohms/sq., and ion implanted BiFETand super
beta devices on PMl's Extrion DF4 200keV Ion
Implanter.
FAB PROCEDURE
PMI will evaluate a customer's mask set to
ensure its compatibility with PMl's processing capabilities; a nominal fee is charged for
this service. Following the acceptance of
PMl's quote to manufacture the desired wafers, prototype runs are begun. Delivery is
normally four to six weeks for single-layer
metalization, and six to eight weeks for duallayer metalization devices.
Wafers, both prototype and production lots,
are accepted by the customer based on
PAGE 14-4
parametric data obtained from drop-in test
dice on the wafers.
After the customer completes evaluation of
the prototype-runs, processing adjustments
are made, if required, and volume production
is initiated. On an ongoing basis, the customer receives consultation on the proper selection of a process for the customer's specific
application, electrical parameters to be expected from the process selected, parameters
for computer simulation (CAD), and assistance to maximize wafer circuit yields.
The chart shown on this page reveals the
approximate number of die that a wafer will
provide as a function of the die size. The
actual useful number of dice may be obtained
by multiplying the unyielded quantity by the
expected probed dice yield percentage.
CAPACITY
Three-inch or four-inch diameter wafers are
supplied depending on the desired volume.
Three-inch wafers are 15 ±1 mil thick; fourinch wafers are 20 ±1 mil thick.
ASSEMBLED/TESTED PARTS
Custom products are available from PMI as
wafers, die or assembled-and-tested parts.
Assembled and tested devices can be supplied in a variety of packages including 12 to 40
pin DIPs (ceramic, Cerdip, or plastic), flatpacks, TO cans, and lead less chip carriers.
The assembled parts undergo final electrical
testing and screening. If die fabrication alone
is desired, the processed wafers are electrically probed by PMI and bad die are marked
on the wafer. Test parameters or test tapes are
to be supplied by the customer.
DIE COUNT VI DIE SIZE
DIE SIZE
(mill)
DIE AREA
(Iq. mill)
APPROXIMATE UNYIELDED*
NUMBER OF WHOLE DIE
PER WAFER
l00mm
x
10
20
30
40
50
60
70
80
90
100
110
120
130
140
150
160
170
180
190
200
210
220
230
240
250
260
270
280
290
300
310
320
330
340
350
y
10
20
30
40
50
60
70
80
90
100
110
120
130
140
150
160
170
180
190
200
210
220
230
240
250
260
270
280
290
300
310
320
330
340
350
IN 1000.
0.1
0.4
0.9
1.6
2.5
3.6
4.9
6.4
8.1
10.0
12.1
14.4
16.9
19.6
22.5
25.6
28.9
32.4
36.1
40.0
44.1
48.8
52.9
57.6
62.5
67.6
72.9
78.4
84.1
90.0
96.1
102.4
108.9
115.6
122.5
2.0··
30116
7438
3262
1835
1148
790
570
424
330
268
214
184
150
130
108
94
88
72
66
60
52
48
42
38
32
32
32
24
22
22
22
16
16
16
16
3.0"
68968
17106
7526
4214
2666
1828
1342
1018
804
638
532
434
370
310
276
236
208
184
164
144
130
120
108
95
88
80
76
66
66
60
52
52
52
44
42
(4.0",
123946
31000
13618
7598
4824
3346
2438
1846
1470
1164
964
804
682
580
496
434
392
336
302
276
256
222
208
184
164
156
148
130
120
112
112
94
88
88
80
'To calculate the number of good dice or parts multiply by
the expected yield percentages.
PAGE 14-5
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PRECISION MONOLITHICS INC.
CUSTOMER
IPRODUCT DEFINITION I
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DESIGN
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LAYOUT
I
DATA BASE TAPE
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MASK GENERATION
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NEW PRODUCT
l
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CREATE TEST PROGRAM
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WAFER SORT
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EXISTING{RODUCT
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FABRICATION
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FINAL TEST
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DEVICE VERIFICATION
START QUAL. LOTS
~
WAFER SORT
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FINAL TEST
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QUALITY ASSURANCE
I CHARACTERIZATION
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PAGE 14-6
PRODUCTION
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APPLICATION
INFORMATION
APPLICATION NOTES
INDEX
PRODUCT
TITLE
AB-1
AB-2
AB-3
AB-4
AB-5
AB-6
AB-7
AB-8
AN-6
AN-10
AN-11
Strobing the DAC-08 Under Logic Control .•••.•.••••••..•••••••••••••••••...•••.••••••••••• 15-3
OP-10 Instrumentation Amplifier CMRR vs Frequency Improvemant ••••..••••••••••••••••••.• 15-4
Digital Nulling of OP-05, OP-07 and OP-07 ••••••••••••••••••••••.••••.•••••••••••••••.•.••• 15-5
REF-02 Temperature Controller .•••....•••••....•••••.•• ,.... ..• • • • • • • • • • • • . • • • •• . • • . • • • • • •. 15-6
The DAC-031'P Controlled D/A •••••....••.•.....•••.•..•••••..••••••.•••••.••..•••••••••••• 15-7
Single Supply Operation of the DAC-08 and DAC-20 ...•...••••••.•.••••.••••.•••••••••••••• 15-6
Negative Supply Loss Protection for PMI Multiplexers .••.••••••..•••••..•••••••••...••••.••• 15-9
3-Digit BCD D/A Converter ............................................................... 15-10
A Low Cost, High-Performance Tracking AID Converter .•.••...••••.•.••.••••••••••••••••.• 15-11
Simple Precision Millivolt Reference Uses No Zeners •.•••....•.•...••••.••••••••.••.•••..•• 15-16
A Low Cost, Easy-to-BuildSuccessive Approximation
Analog-to-Digltal Converter ••....•••.••.••••••••••••••.••••••••••••••••••..••....•..••••• 15-17
Temperature Measurement Method Based On Matched Transistor
Pair Requires No Reference •••••••...•.••.....••...••••.....•.••...••...••••••••.•.•••..•• 15-24
The OP-07 Ultra-Low Offset Voltage OP AMP - A Bipolar OP AMP
that Challenges Choppers, Eliminates Nulling •••...•••••..•••••..•••••••••..••.....••..•••• 15-29
Interfacing Precision Monolithics Digital-to-Analog Converters with CMOS Logic •.•••..••••• 15-39
Minimization of Noise in Operational Amplifier Applications ••..•••.•..••••..•.•..•••••••••• 15-43
Low Cost, High Speed Analog-to-Digital Conversion with the DAC-08 •.•...••••••••..•••..•. 15-52
DAC-08 Applications Collection ...••••.•.••••••••.•••••••••••.•••••••••••.•.•.•.••••.••••• 15-59
Thermometer Applications of the REF-02 •••••.•.••••••••••••.•••••••.•••..••..•••••••••••• 15-70
Differential and Multiplying Digital-to-Analog Converter Applications ••.•..•.•••.••••.••••••. 15-73
Exponential Digitally Controlled Oscillator Using DAC-76 •....•••...•••.•.•••.••••••••••.•. 15-81
3 IC 8-Bit Binary Digital-to-Process Current Converter with 4-20mA Output ••••••••••.••••.•. 15-85
Software Controlled Analog-to-Digital Conversion Using DAC-08
and the 808A Microprocessor ...•.•••.•.••••••••••••••••.•••.••••••.•••••••.•••..••.•••••• 15-87
Digital-to-Analog Converter Generates Hyperbolic Functions •••••••••.••...•••...•••••••.•• 15-91
The OP-17, OP-16, OP-15 as Output Amplifiers for High-Speed D/A Converters •••••••.••.•... 15-93
The 725 OP AMP as a Low Level Comparator .............................................. 15-95
Low Cost Four Channel DAC Gives BCD or Binary Coding .•••••..••••••••.•••....•••.••••• 15-99
Polarity Programmable Peak Detector ...•••...•.•••••.•••••..•••••.•.•••..•......•••.•••• 15-103
Audio Applications for the DAC-76 Companding D/A Converter •....•••.•••••••••...••....• 15-105
Getting Started In Active Filters ...••••••.•••••.•...••••....••••.•.••••••••••••..•.••....• 15-112
Data Conversion Interfacing with the 8080 Microprocessor. . . • • • • . . • • • . . • • • . . . • . . . • . • • . • . •• 15-119
Successive Approximation Register Design for Multi-Channel CODECs ••••.••.....•••.•••• 15-130
Single Supply Operation of PMI Multiplexers ......•.....•••.•..••••••.•.•........••••••••. 15-134
A Guide to Hybrid Integrated Circuit Design ...••...•..•......••.•...•...•••••••••..••..•• 15-136
BCD DAC's Simplify Intelligent Instrument Design •••••.••••••.••••••.••••.••••...••..•••• 15-140
Understanding Crosstalk in Analog Multiplexers .......................................... 15-149
DAC-08 Control of 555 Timers ........................................................... 15-157
Eight-ChannEil CODEC Demonstrator ••••...•.••..•••••....•.•.•...••.••••.•••••.•...•..• 15-161
Four-Channel Shared Codec .....••••••...•••.•••..••••...••••..•••••.•••.•••..•.••.••••• 15-168
Companding Digital-to-Analog Converter •••.••..••••.•.•••••..••••...•••..••..••••••••••• 15-174
A Buffer Applications Collection ......................................................... 15-186
Improved Shared-Channel CODEC Design with PMI's New Companding DACs ....•••.••••• 15-190
A 1kHz, 0 dBmO Standard Signal Generator .............................................. 15-198
The DAC-76 in Control Applications ...•.••.••...•.••...•••....••••.•.•••..••.•.••••••••.• 15-200
Composite Buffer Provides Speed, Accuracy ••..........•••......•..••.•.•••••••••..••..•. 15-204
Time Sharing Permits Design of Controller with Single DAC ....•.•..••...••.•••.•..•.•...• 15-206
BCD DAC Makes Programming of Function Generator Simple ••••••...••.•.......•••.••••. 15-210
Designing Digital Repeaters with IC's • . • • . • • . • . . . • • • . . . .• • • . • . • • • • • . . • . • • • • • • . • • • • • . • • • • •. 15-214
DeSigning a Multiple-Channel Coder/Decoder with Bipolar Devices •.••...••••••••••••••..• 15-221
A Variable-Frequency, Clock Recovery Circuit Using the RPT-81 or RPT-82 •••••••....•••.•• 15-230
Sample/Hold Circuit Monitors Two Input Signals and Tracks the Smaller or Larger Signal ..•• 15-232
AN-12
AN-13
AN-14
AN-15
AN-16
AN-17
AN-18
AN-19
AN-20
AN-21
AN-22
AN-23
AN-24
AN-25
AN-26
AN-27
AN-28
AN-29
AN-30
AN-31
AN-32
AN-33
AN-34
AN-35
AN-36
AN-37
AN-38
AN-39
AN-40
AN-41
AN-42
AN-43
AN-44
AN-45
AN-47
AN-48
AN-49
AN-50
AN-53
PAGE
PAGE 15-2
APPLICATION BRIEF NO. 1
PMI
STROBING THE DAC-OS UNDER
LOGIC CONTROL
by Bob Blair and Donn Soderquist
FEATURES
GENERAL DESCRIPTION
•
Digital inputs are treated as all zeros by increasing the
logic threshold to +6.4V.
•
Single Line Logic Control
•
Handy in Multiplying Applications
•
When more than one DAC is connected to point "A"
-party line connection - strobing is simple.
Since the PMI DAC·08 has a variable logic input threshold,
strobing the output is easily accomplished using the circuit
below. Normally, for TTL thresholds, Pin 1 (VLe) is grounded;
but if it is connected instead to a hex inverter with a pullup
resistor to +5V, all Digital inputs effectively become zeros.
All current flows in 10 ; no current flows in 10 no matter what
the digital input code may be. When the hex inverter's out·
put is low, normal TTL input logic threshold and operation is
restored.
•
Higher speed and greater simplicity when compared to
the alternative method of disabling which is accomplished by reducing V REF to zero.
Recovery when logiC inputs are enabled may be slower when DAC is on
±5V supply due to bias line saturation. This should be checked in the
actual application.
NOTE:
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TTL DIGITAL INPUTS
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HEX INVERTER
7404
PAGE 15-3
PMI
APPLICATION BRIEF NO.2
OP.. 10 INSTRUMENTATION AMPLIFIER
CMRR vs FREQUENCY IMPROVEMENT
By Donn Soderquist and George Erdi
FEATURES
3. Permanently install the selected capadtor.
•
Addition of one selected capacitor improves CMRR at
400Hz to >95d6.
•
OP-10 Side "A" and Side "6" bandwidths are matched.
•
Circuit uses existing nulling pinsas frequency compensation connections.
•
Added capacitor is in the range of 5pF to 100pF.
GENERAL DESCRIPTION
Common mode rejection ratio (CMRR) versus frequency of
the familiar three op-amp instrumentation amplifier can be
optimized by matching the frequency responses of the input
differentially-connected pair of op amps. The circuit shown
uses one selected capacitor (to reduce the frequency response ofthe faster op amp) which is connected between an
output and one of the pins usually used for nulling f1Vos.
CAPACITOR SELECTION PROCEDURE
Eight devices were tested in this connection. I mprovement to
greater than 95d6 @ 400Hz was achieved on all devices, an
improvement of 1 to 20dB over performance without the
selected capacitor.
1. Connect EIN1 to E1N2and to a 400Hz ±10V signal source.
2. While observing Eo with an oscilloscope, try different
values of C1 or C2 until Eo is at a minimum.
TRIPLE OP-AMP INSTRUMENTATION AMPLIFIER CIRCUIT
R6 .
10kn
NOTES:
1.
Eo =
2.
AVCL=(1+R1~:2)(~) =1000
(EIN1 - EIN2) AVCL
3,
CMRR=20LOG~
4.
IF-Qi=Ws.CMRR@DCG!12OdB
5.
AT 400Hz, CMRR IS A FUNCTION OF THE DIFFER·
ENCE IN FREQUENCY RESPONSE OF SIDE "A" AND
SIDE "S",
@DC
400,,,
6.
USE OF Cl OR C2. SELECTED USING THE PROCEDURE
DESCRIBED, MATCHES THE FREQUENCY RESPONSE
OF SIDE "A" AND SIDE "8", THEREBY MAXIMIZING
CMRR AT 400Hz.
R7
10k,Q
*SELECTED SpF TO 100pF.
PAGE 15-4
APPLICATION BRIEF NO. 3
PMI
DIGITAL NULLING OF OP05,
OP06, AND OP07
By Charles Vinn
FEATURES
•
Digitally-controlled offset nulling is achieved by imbalancing the first stage collector currents of a precision
opamp.
•
Greater than 1.5mV of offset voltage may be nulled to zero
with 5p.V resolution at 25°C.
•
This application is especially useful in microprocessorcontrolled systems where stringent error budgets exist.
•
Circuit uses the nulling terminals with a DAC-08 substituted for the conventional nulling potentiometer.
GENERAL DESCRIPTION
The input offset voltage of a precision op amp (OP-05 or
OP-07) may be nulled to <5p.V using the complementary
current outputs of a DAC-08 to change the ratio of collector
currents in the first stage. With Vos being defined as the
voltage which must be applied between the input terminals
to force VO UT to zero and assuming all errors to be in the first
stage, Vos may be expressed as:
kT
IC1 IS2
1) Vos=-q log.-I .-1. where
C2
S1
k = Boltzmann's constant = 1.38 x 10-23 joules/oK
T = Absolute temperature, ° K
q = Charge of an electron = 1.6 x 10-19 coulomb
Is = Theoretical reverse-saturation current
I C = Collector Current
Changing the ratio IC1/lc2 over a ±3% range results in an
input offset voltage nulling range of greater than 1.5mV at
25°C.
CIRCUIT
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IC2 2:= SpA ±O.23,uA
Vas = VBE 1 - VBE2
10 + 10" IFS
10 = IAIIRE' WHERE jAI.
THE DIGITAL INPUT WORD
NOTE:
Tevos MAY BE DEGRADED.
EXPRESSED AS A FRACTION
PAGE 15-5
APPLICATION BRIEF NO. 4
PMI
REF·02 TEMPERATURE CONTROLLER
By Bob Blair
FEATURES
DESCRIPTION
•
Variable Temperature Control
•
Adjustable Hysteresis
•
12V To 32V Power Supply
•
•
21C Design
Low Cost
In the circuit below, temperature control is achieved using
the REF-02 +5V ReferencelThermometer and a CMP-02
Precision Low Input Current Comparator. The CMP-02 turns
on a heating element driver (01) whenever the present
temperature drops below a set point temperature determined by the ratio of Rl to R2. The circuit also provides adjustable hysteresis and single supply operation.
SETPOINT DETERMINATION
HYSTERESIS DETERMINATION
With R2 = 1.5k!l, the value of Rl may be found for any
desired temperature using the following procedure:
R6 and R7 set hysteresis. With R7 = 27k!l, R6 may be
calculated:
E1 =(Desired Temp -25°C) (2.1mV/°C) + 630mV
Rl = R2(5
~1E1)
R6 '"
[(V+I - 4Vj
- (2.1 mV /"CI (Hysteresis width in °CI
CIRCUIT
V+ (12V TO 32V)
------,
t
-------+
R7
21Kl1
R6
------ -
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REF-02
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R2
1.5Kn
RS
2.2Kn
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NOTES:
REF-02 SHOULD BE THERMALLY
CONNECTED TO SU BSTANCE BEFORE
BEING HEATEO.
2.
3.
PAGE 15-6
NUMBERS IN PAREN THESES ARE
FOR A SETPOINT TE MPERATURE
OF6O"C.
R3 .. Rl11R211R6
APPLICATION BRIEF NO.5
PMI
THE DAC-03 p.P CONTROLLED DIA
by Mike Parsln
FEATURES
1 Ramp Cycle = 20"sec + (16l'sec X 256 steps) = 4.116msec
•
•
•
Software Control of Digital to Analog Converter.
Expandable Analog Outputs
Self-Contained DACs Include Reference and
The software shown here was designed to demonstrate the
ease of programming a DAC and exercising its capabilities.
•
Low Cost
For Two's Complement Coding replace the DAC-03 with the
DAC-06, and a DAC-210 Is ideal when Sign - Magnitude
Coding is required.
Output Amps
GENERAL DESCRIPTION
This brief describes a lIP controlled digital-to-analog conversion. By simply placing a digital word on the data bus and
selecting 1 of 3 output ports on the PPI, a Ramp signal is
generated at the output of DAC #1. The software can be
modified to expand the number of analog outputs. Complex
waveforms also can be created through software control.
The following expression is used to determine a single Ramp
Cycle Time when the clock is 2MHz.
APPLICATIONS
.. Programmable voltage reference.
.. Waveform generation:
A. Sawtooth
B. Triangular
C. Pulse
D. Complex
HARDWARE AND SOFTWARE
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1
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DAC-43CD
NOR.'
.... 'I
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I I
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L _ _ _ .J
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_ _ _ _ _ _ _ ~-.:_..1
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ..1I
BEGIN
MVI C, FFH
ALL "1'S" TO C REGISTER
LXI M. 8OO3H
DCR C
LOAD CONTROL WORLD ADORESS
INITIALIZE PIA
MOVE DAC INPUT
WRITE TO OAC 1
START COUNT DOWN
MOYA.C
MOVE OAe INPUT
JNZSTART
GO TO START ON NOT ZERO
MYI M, 80H
MOVA,C
START SfA 8000H
JMPBEGIN
+6V
NOTE: OAC'S ARE WIRED FOR 8 BIT OPERATION.
PAGE 15-7
START NEW CYCLE
"
,,"',
DAC-03CD
NBR.I
.... 1
I
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I
APPLICATION BRIEF NO.6
PMI
SINGLE SUPPLY OPERATION
OF THE OAC-OB AND OAC-20
By Dennis Van Dalsen
FEATURES
GENERAL DESCRIPTION
The DAC-08 may be operated from a single supply when
properly biased. This circuit will allow the use of a single
power supply, or battery, and still realize the premium performance of these high speed DACs.
•
Simple Interface
•
Compatible with CMOS and Open Collector TTL
•
No Degradation in Performance
The resistive voltage divider inputs to VLC and logic inputs
provide the necessary voltage levels for operation from
CMOS and Open Collector TTL logic.
CIRCUIT
ONO
vRL
DAC-oa/20
10.OkO
10kn
v+
PAGE 15-8
< V+ -I~~FOLTS
APPLICATION BRIEF NO. 7
PMI
NEGATIVE SUPPLY LOSS PROTECTION
FOR PMI MULTIPLEXERS
By Shelby D. Givens
DESCRIPTION
Like most ICs, PMI BIFET multiplexers do strange things
when the substrate is left floating. Removal of the -15V
supply lead causes the substrate (V - ) to float up past the
potential on the GND terminal, and the substrate diode will
turn on. If the ENABLE line is held low (the multiplexer is in·
operative), nothing bad will happen. However, if the
ENABLE line is high, the above condition (V- pin positive
with respect to GND pin) could be catastrophic.
MUX-16/86
MUX-08188
14
v-
GND
12
V-
MUX-24
The solution to this potential problem is the same for all
PMI multiplexers as shown in the figure: a small signal
diode connected between V- and GND. The table shows
data taken with and without the diode.
MUX-28
15
v-
Z1
GND
12
GND
GND
27
V-
Note: All diodes are 1N914 or equivalent
MUX·08 NEGATIVE SUPPLY LOSS
MEASUREMENTS
WITHOUT DIODE
EN
V1+
4.8V
-15V
OV
9.8mA
SOLVING MULTIPLEXER SUBSTRATE FLOTATION
0(
WITH DIODE
EN
V1+
oZ
~u
- 15V
-15V 10.6mA
OV
-15V 10.6mA
OV
OPEN 11.3mA
OV
OPEN 10.8mA
TEST CONDITIONS
4.8V
OPEN
4.8V
OPEN
A power supply current limited to 70mA was used to make
the measurements allowing non·destructive testing. Note
that the excessive current problem is solved when the diode
is attached as shown in the figure.
(V+ = +15V)
*See Test Conditions
(V+5+15V)
9.8mA
9.7mA
en
w
Note: If the negative power supply simply shorts out to
ground, then with or without the diode, the multiplexer will
continue to function with no catastrophic failure
mechanisms.
4.8V
70mA'
t;-
ra
PAGE 15·9
I-
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0(
III
APPLICATION BRIEF NO.8
PMI
3-DIGIT BCD 01A CONVERTER
by Vic Spiler
FEATURES
•
•
•
•
•
IREF2= 16to 1 current ratio to IREF1
IREF2 = 16 (0.1428mA)
Monotonic
Linear to 2 LSBs
Compatible with CMOS and TTL
Excellent Voltage Compliance
Low Cost
.
I REF2 = 2.28mA
FULL SCALE CURRENT
99
99
I FS1 = 100 • IREF1 = 100 0.1428mA
GENERAL DESCRIPTION
CALIBRATION PROCEDURES
IFS1 = 0.1413mA
144
144
I FS2 = 256 .1 REF1 = 256 (2.2B4mA)
With bits 1 through 4 turned off (DAC-OBH). and bits 1
through B turned on (DAC-20E). code 099. adjust potentiometer 2 until the voltage out equals 0.990V.
I FS2 = 1.2B4mA
With bits 1 through B turned off (DAC-20E). and with bits 1
through 4 turned on. code 900. adjust potentiometer 1 until
the voltage out equals 9.000V.
I FST = IFS1 + I FS2
I FST = 1.425mA
REFERENCE CURRENTS IN BOTH DACs
FULL SCALE VOLTAGE
VFS = 9.990V
VREF
5V
IREF1 = -R-- = 35k = 0.142BmA
REF1
IREF1 = 0.1428mA
V01 = 0.990V
V02 = 9.000V
HUNDRED'S DIGIT
loWlT'S DIGIT TEN'8 DlGtT
,..-.-.... ,..-.-....
~B
. . 17 . . . . . . 13828'
,..-.-....
MR
A.
IK
11
....F
.'IV
12n10187
RREF,
AEF02C
ta ,.
1"-4-.J_w,.-=I
A3
1&
DAC-2IIE
:.IK
TRIMPOT.1 • 2: BOURNS Mn MODEL 7128C-279-603
PACKAGE: '4 PIN DUAL IN-LINE
t REIISI'ORIIN MFT NETWORK
PAGE 15·10
-.IV
r
APPLICATION NOTE 6
PMI
A LOW-COST, HIGH-PERFORMANCE
TRACKING AID CONVERTER
INTRODUCTION
The availability of low-cost IC D/A converters, comparators
and up/down counters makes possible construction of tracking AID converters having high performance and reliability
despite their small size and low cost. These AID converters
are suitable for a wide range of applications such as transducer and audio digitizing, infinite sample and holds, and
servo-control loops. This paper describes an 8-bit tracking
A/D converter that can be built using Precision Monolithics,
Inc., DAC-100 CC03 D/A converter, CMP-01CJ Fast Precision Comparator and 4-bit MSI up/down counters.
TYPES OF AID CONVERTERS
There are several popular styles of A/D converters (ADC)
based on using a D/ A converter in a feedback configuration.
The three most common are: ramp or count-up, tracking or
servo, and successive approximation.
Ramp types produce one conversion per each 2N clock
counts for an "N" bit converter and are suitable only for very
slowly changing analog data; additionally, the data can be
taken out only at the end of the conversion period. Successive approximation types are quite fast, requiring only "N + 1"
clock counts for conversion. They are capable of encoding
fast-moving analog signals if an external sample-and-hold
circuit is used to stop the analog data; again, the digital
output is true only at the end of the conversion period.
For many applications, tracking ADCs can provide adequate
speed while costing approximately the same as simple ramp
types. Additional advantages are that no sample-and-hold
circuit is required and that the digital data is continuously
available at the output.
BASIC OPERATION
The tracking A/D is a relatively simple system, both in concept and in practice. The basic design requires three major
elements: an up/down counter, a current output D/ A converter, and a voltage comparator (see Figure 1). The voltage at
the comparator's input will be the result of the analog input
voltage minus the DAC output sink current times RIN (Vo =
V 1N - 11 • RIN). Assuming a perfect comparator, if the output
voltage (Vo) is above ground, the comparator's output will be
low, causing the up/down counter to increase the DAC's
output sink current by one LSB. (The counter actually
counts down one count; this results from the DAC's utilization of complementary logic, I.e., an all-zero input produces
maximum DAC output current.) The comparator continues
to examine the voltage for polarity, and always drives the
counter's code in the direction which causes the output
voltage to approach zero. Once a balance is achieved, the
loop is "locked," and tracks the analog input signal so long as
the loop slew rate is not exceeded. When the loop is balanced, the converter's output is the binary-coded equivalent
of the analog input.
When encoding a DC input signal, the digital output will
"dither" or alternate between the two adjacent states which
span the theoretically correct output value. This is of little
consequence as all A/D converters have a similar error,
known as the "quantizing" error.
II)
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II
- .... DIGITAL
OUTPUT
_._ ...... __._. - . -+-++-+-+- J
+--+-+-++--MSii
ANALOG
INPUT
RIN
o--'II"IV-+--------------(
VIN
Figure 1. Basic Tracking AID Block Diagram
PAGE 15-11
CURRENT OUTPUT
D/A CONVERTER
In the actual circuit design, a "type-D" flip-flop is inserted
between the comparator and the counter's up/down input.
This is to insure adequate set-uptime between the comparator'$ output change and the counter's next stage change.
the DAC-100 utilizes complementary logic. Diode clamps
insure the DAC output remains near zero despite input and
turn-on transients. Forthis 8-bit design, the two least significant digital inputs of the 10-bit DAC are not required and are
connected to +5V, thus turning them off. Diodes are also
used to insure that a positive voltage is applied to the V+ pin
(Pin 14) as soon as the +5V supply comes up; The clock,
although extremely simple, is.quite stable over a wide range
of temperatures and supply voltages. Several layouts were
tried, with no perceptible differences in performance. (See
Figure 4.)
Loop timing can be seen in Figure 2. After the positive clock
transition, the counter changes to its next state and drives
the DAC to its new output. After the DAC has settled and the
comparator has come to its final state, the next positive clock
transition loads the comparator's new state into the flip-flop
and the cycle repeats.
TRIMMING
The circuit requires only one trimming operation. The fullscale output current of the DAC is adjusted to produce
proper encoding atfull scale input. Although several schemes
are possible, the simplest is to place +10.0V at the input, and
trim the 2000 Full Scale Adjust pot to produce a low output at
the seven most significant bits with the LSB alternating
states (dithering) at the clock frequency.
CLOCK
"0" - FF OUTPUT - - , L_ _ _ _ _ _ _ _ _..I
I
COUNTER OUTPUT
STATES (TYPICAL)
1
~I
I
I
VOLTAGE OUTPUT APPLICATIONS
1 1,.--_ _ _ _ __
COMPARATOR
OUTPUT
----tll.-J'I
~
The basic tracking A/D uses a "current-comparison" technique; the analog voltage is not reconstructed at the comparator's input, thus eliminating the need for an op amp to
convert the DAC-100's current output to a voltage. For applications such as infinite (no-droop) analog sample-and-hold
circuits, the OP-01 CJ, a low-cost, fast slewing, fast settling
op amp with internal compensation can be added as in Figure 5. This configuration also provides very high input impedances, without requiring an extra buffer amplifier. The
reconstructed analog voltage is available at the output of the
op amp; gating the counter "off" stores the data in analog
form.
OAe SETTLING TIME
~ :~~:oc~s~P~t~~TOR
Figure 2. System Timing Diagram
FINAL CIRCUIT DESIGN
The completed 8-bit tracking AID design is shown in Figure
3. The digital output is available in complemented form, as
----1>--------.()
CLOCK IN
MAXIMUM CLOCK RATE = 3.0MHz
1+
1-,.
15
+5V TRACK
HOLD
-Ir
27
*1/47400
240n
LaCK
.
.
~
DIGITAL
OUT
0.02
OUTPUT
D D2
.
1-"
lD.02
f"
lo,o2
C
f--T = 3RC
131211 10
9 8 7 6 5 4
LSB
mI
4.88kH
VIN '" 0 TO +10V
RIN ' 4.BkU
ANALOG I N P u r c r - - - - - · - - ·
MAXIMUM FULL SCALE
SINE WAVE INPUT
L....+-----~-'5V
IS 4000Hz.
Figure 3. Complete Schematic - 8-Bit Tracking AID Converter
PAGE 15-12
.1 POWER
":'" GROUND
DAC·l0OCC03
10·BIT D/A CONVERTER
ANALOG
GROUND
BACK
FRONT
CONNECTOR
FRONT
BACK
ANALOG GND
ANALOG GND
.j.5V
ANALOG IN
DIGITAL GND
CLOCK
DIGITAL
OUTPUT
N.C.
N.C.
Ul
+15V
o
z
z
o
W
~
-15V
~
FRONT
(.)
8-BIT TRACKING AID PARTS LIST
Quantity
Description
Quantity
Description
1
1
DAC-100CCQ3 D/A Converter
CMP-01 CJ Comparator
8284 Up/Down Counters
7474 Dual D-Type Flip-Flop
7400 Quad Gate
1
4
5
2000 Trimpot, Bourns 3359P
IN4148 Diodes
Ceramic Capacitors
Carbon Composition Resistor
PC Board
Figure 4. Actual Size Printed Circuit Layout -
Circuit of Figure 3
BIPOLAR OPERATION
0.05% APPLICATIONS
Bipolar operation (±5V) can be obtained by injecting a current equal to 1/2 the full scale current into the DAC-100 sum
line. This can be accomplished by applying +6.4V to the
internal bipolar resistor of the DAC-100 (pin 1) - a 500n
symmetry-trimpot to produce a high output at all bits, with
the normal "dither" in the LSB only. Next, ground the input
and adjust the Full Scale trimpot to produce an output which
alternates between 10000000 and 01111111.
Applications requiring 10 bits of resolution with 0.05% linearity can be implemented by adding a third up/down counter
and utilizing all 10 inputs of a DAC-100ACQ3 (or Q4). See
Figure 5.
o TO +5V OPERATION
Operation with 5 volt full scale inputs (OV to +5V or ±2.5V)
can be obtained by specifying the DAC-100CCQ4.
Z
TRACK & HOLD
N.C.
2
CD
c
TRACKING AID CONVERTER WAVEFORMS
These scope photos were taken to indicate the waveforms
observed at the comparator input during normal and abnormal operation of the converter. The output analog voltage
trace was generated by applying the elJcoded digital output
to a second D/ A converter.
PAGE 15-13
::::i
a.
a.
C
II
NORMAL OPERATION
SLEW RATE LIMITING
COMPARATOR INPUT
COMPARATOR INPUT
ANALOG INPUT
ANALOG INPUT
RECONSTRUCTED
RECONSTRUCTED
ANALOG INPUT
ANALOG INPUT
PERFORMANCE
INPUT OVER-RANGE
Performance of the completed converter is quite impressive
despite the low cost and small size. Using clock rates of
3.0MHz, 10 Vp _p signals can be accurately tracked to frequencies of about 4.0kHz; higher frequencies can be accommodated by reducing the peak-to-peak amplitude.
COMPARATOR INPUT
Fully monotonic operation is obtained from 0° to 70°C; this
is achieved because the DAC-1 00CQ3 is guaranteed to have
±1/2 LSB linearity to 8 bits (0.2%) over this temperature
range, and the DAC-100ACQ3 has ±1/2 LSB linearity to 10
bits (0.05%).
ANALOG INPUT
RECONSTRUCTED
ANALOG INPUT
All D.C. static errors can be attributed to the analog components only; the comparator makes no contribution to linearity errors, but its Vos and Vos drift with temperature are a
+5V
CLOCK IN
DIGITAL
'-------1>++-Ir-t+--~
OUTPUT
NOT
USED
LSB
ANALOG IN
(HIGH RINI
ANALOG
OUTPUT
Figure 5. 10-BII Voltage Oulput AID Converter Block Diagram
PAGE 15-14
consideration in the zero scale and full scale performance,
and especially so in bipolar applications. The worst case
DAC-100 zero error over O· C to 70· Cis 0.6mV; adding to this
the 3.5mV maximum Vosof the CMP-01C results in a worst
case zero scale error of 4.1mV, which is acceptably small
compared to the value of 1/2 LSB (19.5mV) forthe 8-bit AID.
Because the Vos drift of the CMP-01C is typically only
1.8/LV/oC even without offset triming, the full scale drift will
be almost entirely a function of the DAC-100CC tempco
-60ppm/oC maximum.
For 1O-bit applications, the comparator Vos becomes significant; the CMP-01 C can be nulled, or the 0.8V maximum Vos
CMP-01 E can be utilized without nulling. Nulling ofthe comparator is not required in bipolar applications; this is accomplished by the bipolar symmetry trimming.
Other performance characteristics of the completed converter are listed in Table 1.
MILITARY TEMPERATURE RANGE OPERATION
Operation over wider temperature ranges can be obtained by
simply specifying appropriate temperature range components. The simplicity of the all IC design coupled with the
compatibility with MIL-M-38510 processing assures high
reliability in military applications.
CONCLUSION
Extremely compact, low power consumption, all IC tracking
AID converters are made possible by combining Precision
Monolithics,lnc. DAC-100series 10-bit D/Aconverter, CMP01 series comparator, and commerically available MSI upl
down counters. Layout, construction and adjustment are
noncritical. The simplicity and low cost of the tracking AID
converter invites usage in many new applications, including
single channel digitizing at remote transducer locations.
TABLE 1. PERFORMANCE DATA
8-BIT
Nonlinearity
(O·C to +70·C)
Full Scale Tempeo
(O·C to +70· C)
Zero Scale Error
(O·C to +70· C)
0.2% Maximum
APPENDIX - USEFUL DATA AND FORMULAE
10-BIT
0.05% Maximum
LSB -
60ppm Maximum
60ppm Maximum
0.10 LSB Maximum
0.20 LSB Maximum'
0.02 LSB
0.08 LSB
Full Scale Voltages
Power Supply Rejection
(O·C to +70· C)
Power Consumption
(Vs = ±15V. +5V)
'Untrimmed CMP-OIE
10V Full Scale
5V Full Scale
39.1mV
9.85mV
19.5mV
4.92mV
Loop Slew Rate = Clock Frequency X VLSB = f e X VLSB
Maximum Clock Frequency = I/(TA + TB + T C + To + TEl
Zero Scale Error
Comparator Trimmed
(O·C to +70· C)
8 Bits
10 Bits
WHERE:
T A = Flip-Flop Propagation Delay
TB = Minimum Counter Set-Up Time
OV to +10V, ±5V
OV to +5V, ±2.5V
OV to +10V, ±5V
OV to +5V, ±2.5V
T C = Counter Propagation Delay
0.02% per %Maximum
0.02% per % Maximum
1.4W Maximum
1.77W Maximum
To = DIA converter Settline Time (to n-bits)
T E = Comparator Response Time
Minimum Clock Frequency
=
1T •
VINe-e' fiN max
VLSB
•
PAGE 15-15
PMI
APPLICATION NOTE 10
SIMPLE PRECISION MILLIVOLT
REFERENCE USES NO ZENERS
by Donn Soderquist
GENERAL DESCRIPTION
A low output impedance millivolt source is frequently required in test systems, for generating small currents with
moderate resistance values, and for general laboratory use.
An excellent millivolt source can be built using only two
parts; an Instrumentation op amp and a potentiometer. The
op amp is connected as a unity-gain buffer (Figure 1) and
the output is adjusted to the required voltage using the offset nulling terminals. The amplifier must have suitable
characteristics such as low long term drift, freedom from
chopper and "popcorn" noise, good power supply rejection
and low offset voltage drift with temperature. To achieve
low output impedance the op amp must have high gain
around zero output voltages, and should have negligible
thermal-induced drift for stable performance under varying
load conditions. Use of a high performance bipolar input op
amp such as the Precision Monolithics OP-OSCJ provides
low drift without chopper noise. With a typical initial offset
voltage of O.3mV, outputs from about -3.SmV to +3.SmV
can be achieved. Adjusting the offset of the OP-OSCJ to a
value other than zero will create a drift equal to 3.3,.V/oC per
millivolt of output setting. The circuit's low frequency noise
will be less than O.6S,.V peak-to-peak with an output impedance of less than one milliohm. Long term drift will be
much less than 3.S,.V per month and power supply rejection
is about 101'V1V01t.
.,OY
~~----~-----oYmrr
-15V
Figure 1_ Zenerless Precision Millivolt Source
PAGE 15-16
APPLICATION NOTE 11
PMI
A LOW-COST, EASY-TO-BUILD
SUCCESSIVE APPROXIMATION
ANALOG-TO-DIGITAL CONVERTER
®
By Donn Soderquist
Successive Approximation Analog-to-Digital Converters
have often been considered to be complex, expensive and
troublesome circuits to produce. This application note describes a high-speed 8-bit successive approximation ND easily constructed using only three readily available ICs. Precision Monolithics' DAC-100 Digital-to-Analog Converter,
CMP-01 Fast Precision Voltage Comparator, a Successive
Approximation Register plus a handful of discrete components complete the design. Despite the simplicity, the ND is
capable of 8-bit conversions in 6"sec, and can easily be
expanded to 1O-bit resolution operation.
FEEDBACK AID CONVERTERS
Most popular AID converters built today use a digital-toanalog converter as part of a feedback or servo loop. Th ree of
the most common types are the Ramp, Tracking, and
Successive-Approximation; these differ primarily in the type
of programming logic circuitry used to drive the DI A converter. All three types perform a comparison between the analog
input and the output of a DI A converter; the logic changes
the DI A output so that it approaches the analog input -when
they are equal, the input to the DAC is the correct digitally
encoded number (Figure 1).
Tracking AID converters use upldown counters for the programming logic; the comparator output forces the counters
to "track" the changes in the analog input. Once initial "lock"
is acquired the correct digital output is continuously available, and the converter may be capable of encoding fairly
fast-moving input signals without requiring a sample and
hold circuit. (Complete details on the construction of this
type of converter are available in Precision Monolithics
Application Note 6, "A Low-Cost, High-Performance Tracking ND Converter.")
Tracking ADCs are at their best when used to encode a
single signal with a well-behaved maximum slew rate; multiplexed or video signals have large discontinuities which
cause large errors while the tracking loop moves to acquire a
new "lock" on the signal.
Successive Approxi mation AID Converters are attractive for
their rapid conversion rates and have found wide acceptance
in video and multiplexed data systems. Recently-announced
ICs provide the three basic converter building blocks in integrated form, reducing the cost and complexity of this
approach to a figure at or below that of the ramp and tracking
types. The great advantage of the SA ADC is that complete
"N"-bit conversions can be accomplished typically in N+1
clock periods - for a 1O-bit converter this would be a speed
improvement of about 100 times over the ramp type.
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Q.
Q.
CC
BASIC SUCCESSIVE APPROXIMATION AID
CONVERSION
END-OF ENCODF.
'0 START
.('I
LOGIC
CLOCK INPUT
An SA ADC operates by comparing the analog input to a
series of "trial" conversions; the first trial compares the input
to the value of the most significant bit (MSB) or half of full
scale. Figure 2 shows the progression of trials for a 3-bit
converter. If the input is greater than the MSB value, the MSB
is retained and the converter moves on to "trying" the next
most significant bit, or three-quarters full scale. If the input
had been less than the MSB, the logic would have turned the
MSB off before going on to the next most significant bit, or
one-quarter full scale. This "branching" continues until each
successively smaller bit has been tried, with the entire process taking "N+1" trials.
~+----f-f--oMSB
--{)
--0LSB
MSB
LSB
D/A
Figure 1. Basic Feedback AID Converter
The Ramp or Count-up type ADC uses up-counters for the
programming logic. A start command clears the counters
which then count up until the comparator output changes.
The user must allow 2 n clock periods to insure a complete
conversion; therefore only very slowly varying data may be
converted.
To implement the logic for the successive approximation
algorithm, a configuration similar to Figure 3 may be employed wherein a start command places a "one" in the first bit
of a shift register. This sets the first latch to "one," and turns
on the DAC's MSB. If the comparator output remains slow,
the "one" will remain in the latch; if not, the latch will be reset
to zero before the next bit trial begins. The next clock cycle
causes the shift register to place a "one" in the second bit and
PAGE 15-17
II
TRIAL 1
VIN
~
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TRIAL 2
<
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.
'.
IVN SHOWN IN PARENTHESIS)
I TRIAL 3
IL111
INPUT {
IL"°I~
.00
000
!~.oo i~:::
I
I
BIT 1·?ZZZ2I
BIT2~
I~'OO
IL011
OUTPUT
I1«0'01~
0.0)
I
010
I I~oo.
I
000 I 10011
!
~~~~
co"p~~~~~
!
BIT 3
22221
BIT 4
BIT 6
2Z?Za
2Z?2l
BIT 6
azza
BIT 7
22Z2J
BIT 8
2222J
'---I
CONCC:;~~~~ !Z?2J
L....I:=::
L-
C:~~~
000
"NOTE: NEGATIVE TRUE LOGIC USED.
SHADED AREAS INDICATE LEVEL DEPENDS UPON PRE·
VIOUS STATE.
INPUT = +6.66 VOL lS, FULL SCALE = +10 VOL T8.
Figure 2. Flow Diagram for 3-Blt Successive Approximation
AID Conversion
Figure 4. Timing Diagram
analog input voltage and the output voltage of the 01 A converter. Higher speed conversions may be achieved by using
the output of a fast current output OAC directly. This may be
implemented as shown in Figure 5, where the comparator
examines the polarity of (VIN - liN R1N). The "current comparison" method eliminates the need for a current-to-voltage
converting op amp which is by far the slowest element in
most 01 A converters.
VIN INPUT
VOLTAGE
"IN
Figure 3. Successive Approximation AID Converter
a similar process continues until all bits have been tried.
After the last bit's trial, the end-of-encode output changes
state indicating the parallel data is ready to be used. A useful
feature of successive approximation conversion is that the
correctly converted data is also available in serial form; this is
handy for transmission of data on a single bus.
The complete sequence of events is demonstrated in the
timing diagram of Figure 4. Note that "negative true"logic is
shown; the OAC-100employsa complementary binary code
and the AM2502 produces a "low" output during each bit's
trial, thus producing the standard successive approximation
routine starting with the MSB trial and working towards the
LSB trial. All events are initiated during positive-going clock
transitions; the conversion process starts when the S input is
held low, which also causes the CC (Conversion Completed)
output to go high. After all bits have been tried, the last
positive clock transition returns the CC to a low state, indicating the conversion has completed.
"CURRENT" COMPARISON
The previous discussion has indicated that the function of
the comparator was to perform a comparison between the
Figure 5. "Current Comparison" AID Input
COMPLETE CIRCUIT
The schematic for the complete 8-bit AID converter is shown
in Figure 6. It is seen that the complete circuit adds very few
components to the basic three ICs of the block diagram. A
2000 potentiometer is used to adjust the full scale output and
R1 is used to inject a +1/2 LSB value current into the sum
node. This insures that adjacent code point transitions occur
at 1/2 LSB points for minimum overall error. The clamp
diodes minimize settling time and prevent large inputs from
damaging the OAC output. For an 8-bit, 10 volt system the
CMP-01CJ's maximum offset voltage is less than 1/10 LSB
and should not require nulling.
PAGE1S-1.
FULL
SCALE
ADJUST
LS8
BITS
BIT7
BIT6
BIT5
+15V ~"I--I-'----~~"~+15V
O.01j.1F J!. lj.1F
50V I36V
I
ANALOG
BIT4
J I 50V -,-J!I35V . .
BIT3
BIT 2
MSB
MSii
O.Olj.1F
BIT 1
BIT 1
-15V III
+5V
SERIAL
OUTPUT
1j.1F
I
GROUND
II -15V
+5V ~.I--I'---~-'---l"~ +5V
O.Olj.1F~4.7j.1F
lSOV
I
'OV
J-r--~--+---l"~ ~~~~D
START . . . _ - - - - - '
~g:~~;~~ON
CLOCK INPUT
..._-------'
..._-----------J
Figure 6. Complete 8-Blt AID Schematic
..
GROUNDING
For optimum noise rejection, digital (power) ground currents should not flow in signal input ground return lines.
Analog and power grounds should be connected as close as
possible to the NO converter input connector. Figure 7 illustrates a typical system installation showing the ground
connections.
possible and is separated from digital lines; the OAC output
trace is especially short and directly connected to the comparator input and clamping diodes. Generous power supply
bypassing has been employed using both disc and electrolytic capacitors. Other layouts can be easily designed because of the extreme simplicity of this circuit.
The digital output is available in serial NRZ (non-return-tozero) format at the data output (00) shortly after each
positive-going clock transition. Serial output is especially
convenient in applications where system wiring must be
minimized. such as in one NO per channel systems. Performing the ND conversion process in close proximity to the
signal source has the advantage of reducing errors associated with transmission of low level analog signals; instead,
digitally encoded signals are transmitted with their inherent
low error rates and ease of multiplexing.
16 -15VOLTS
15 +5VOLTS
L..:..::::.::....:r-t-----:t'' I3
POWER
GROUND
12 ANALOG
L ANALOG
r-;.;~~:J------Lb,lGROUND
INPUT
'------'
BIPOLAR OPERATION
SUGGESTED CLOCK CIRCUIT Fa= 1.4MHz.
1/3 SN7404N HEX INVERTER.
Bipolar operation can be obtained by injecting a current
equal to 1/2 full scale into the sum node. This can be accomplished by applyi ng +6.4 volts through a SOO oh m potentiometer to the internal bipolar resistor of the OAC-100. Both Bit 1
and Bit 1 are available so 2's complement or offset binary
coding may be obtained as desired.
NOTE: PIN NUMBERS SHOWN REFER TO PC CARD TERMINALS.
·COMMON GROUNDING POINT - REFER TO TEXT.
Figure 7. Grounding and Supply Hookup
LAYOUT
A suggested layout for an 8-bit converter is shown in Figure
8. This layout demonstrates some of the basic rules of good
NO converter practice: analog wiring is kept as short as
Z
C
fa
I-
o
Z
z
o
SERIAL OUTPUT
17 +15VOLTS
";'
o TO +5V, ±2.5V OPERATION
Operation with SV full scale inputs (0 to +SV, ±2.SV) may be
obtained by specifying DAC-100 models with a Q4 suffix.
PAGE 15-19
iiiu
::::i
IL
~
II
TRACE SIDE
COMPONENT SIDE
CONNECTOR PIN CONNECTIONS
COMPONENT SlOE
1N4148
18
N.C.
V
N.C.
17
+15 VOLTS
U
+15 VOLTS
16
-15 VOLTS
T
-15 VOLTS
15
+5 VOLTS
S
+5 VOLTS
...l..
...l..
14
POWER GROUND "::"
POWER GROUND
P
POWER GROUND "::"
...I..
POWER GROUND ":"
12
*rfl
R
13
ANALOG GROUND
N
ANALOG GROUNO!h
11
ANALOG GROUNDm
M
ANALOG GROUNDm
10
N.C.
L
ANALOG INPUT
9
BIPOLAR REFERENCE VOLTAGE INPUT
K
N.C.
8
N.C.
J
N.C.
7
BIT 1
H
N.C.
6
BIT 1
F
BIT 5
5
BIT 2
E
BIT 6
4
BIT 3
OBIT 7
3
BIT 4
C
BIT 8
2
S START
B
CC CONVERSION COMPLETED
1
CLOCK INPUT
A
00 SERIAL OUTPUT
Figure 8. 8-Bit AID Layout
CALIBRATION
PERFORMANCE
For unipolar, 8-bit, 10 volt full scale calibration apply +9.941
volts (full scale -3/2 LSB) to the input. Adjust the gain potentiometer until the digital output is alternating between "0000
0000" and "0000 0001". This calibrates the converter at a
transition point insuring correct outputs over the analog
input range. No zero adjust is necessary due to the low
comparator input offset voltage (Vos). virtually zero output
offset of the DAC and the correct +1/2 LSB bias established
by R1.
Performance of the completed converter for 6, 7 and 8-bit
resolution applications is shown in Table 2. To assure fully
monotonic operation in 8-bit applications the DAC-100CC
grade with its maximum nonlinearity of 0.2% from 0° to 70°C
should be specified. Applications requiring 8-bit resolution
with 0.3% or less linearity may utilize the lower cost DAC10000 types.
For 8-bit, ±5 volt full scale offset binary operation, first perform the unipolar calibration as described above with the
bipolar reference removed. Next connect the +6.4 volt bipolar reference through the 500 ohm potentiometer to the bipolar input resistor. With -5.000 volts as an analog input, adjust
the 500 ohm potentiometer until the digital output is alternating between "1111 1111" and "1111 1110". For calibration at
lower bit resolutions refer to Table 1.
All D.C. static errors can be attributed to the analog components only; the comparator makes no contribution to nonlinearity, but its 25° C Vosand Vosdrift with temperature are a
consideration in the zero scale and full scale performance,
and especially so in bipolar applications. The worst case
DAC-1 00 zero error over 0° to 70° Cis 0.6mV; adding to this
the 3.5mV maximum Vos of the CMP-01 C results in a worst
case zero scale error of 4.1 mV, which is acceptably small
compared to the value of 1/2 LSB (19.5mV) forthe 8-bitA/D.
PAGE 15-20
Table 1. Reduced Resolution Application Data
Resolution
Desired
Offset Current
Value (1/2 LSB)
Conversion
Complete
Indicator
Full Scale
Calibration
Point
LSB
(10VFS)
8 Bits
3.9MO
3.91'A
CC
9.941V
39mV
7 Bits
2MO
7.81'A
Bit8
9.883V
78mV
6 Bits
1MO
15.61'A
Bit7
9.766V
156mV
5 Bits
470kO
31.31'A
Bit6
9.531V
313mV
4 Bits
240k!1
62.51'A
Bit5
9.163V
625mV
Table 2. Performance Data
Resolution
D/A
6 Bits
DAC-100DD03
7 Bits
DAC-100DD03
8 Bits
DAC-100CC03
0° to 70°C Maximum
Nonlinearity
±0.3%
±0.3%
±0.2%
0° to 70° C Full Scale
Tempco Maximum
120ppm/O C
120ppm/OC
60ppmfOC
Zero Scale
Error Maximum
±0.05 LSB
±0.1 LSB
±0.2 LSB
Conversion Time
1.5MHz Clock
6.01's
Unipolar Reference
Internal
Bipolar Reference
External +6.4 Volts
Input Impedance (+10V or ±5V Scale)
5kO Nominal
Input Impedance (+5V or ±2.5V Scale)
2.5kO Nominal
Quantizing Error
±1/2 LSB
III
Output Code Unipolar
Complementary Binary
Output Code Bipolar
Complementary Offset Binary
o
z
z
W
~
o
Clock
External
Logic Output Drive Capability
6 TTL Loads
Analog Power Supply Range
±6V to ±18V
:::i
Digital Power Supply Range
+5V ±5%
ec
Power Consumption ±15V and +5V Supplies
935mW Maximum
Because the Vas drift of the CMP-01 C is ty·pically only
1.8I'V/o C even without offset trimming, the full scale drift will
be almost entirely a function of the DAC-100CC tempco
-60ppm/oC maximum. (Tempco of DAC-100DD models is
120ppmfOC.)
creases the size of the LSB, the value of R1 and the full scale
calibration point should be changed accordingly, as shown
in Table 1. Additional speed in reduced resolution applications may be achieved by increasing the clock frequency.
REDUCED RESOLUTION APPLICATIONS
Encoding time may be reduced in applications not requiring
the full 8-bit resolution. In convert-on-command applications, the negative-going transition of the (N+1) bit may be
used as the Conversion Completed (CC) signal; the register
will continue to step through the remaining bits so the CC
level will be present for one clock period only. For continuous conversion applications, the register may be truncated
by applying a low level to the S input; however, caution must
be observed to prevent possible stalling on power-up: the S
input should be generated by either the CC or bit (N+1)
going to a low state. Figure 9 demonstrates a 6-bit, continuous-encoding application. Since reducing the resolution in-
Figure 9A. Short-Cycled Continuous Coding (6 Bits Shown)
PAGE 15-21
~
o
DD-
II
This can be eliminated in unipolar applications by nulling the
CMP-01CJ or specifying the 0.8mV offset CMP-01EJ. No
initial Vosimprovement is required in bipolar applications, as
this error will be eliminated during the bipolar calibration
procedure. The offsetting resistor (R1) should be 15MO for
10-bit applications, with the full scale calibration voltage of
+9.985 for unipolar applications.
SYSTEM CONSIDERATIONS
Figure 9B. Short-Cycled Continuous Encoding (Alternate
Method Including Clock)
10-BIT APPLICATIONS
The basic 8-bit converter may easily be expanded to 10 bits
by using a 250412-bit Successive Approximation Register; it
may be allowed to step through all 12 bits or short-cycled as
described above (Figures 9A, 9B). All DAC-100 Series devices have 1O-bit resolution; for applications requiring 10-bit
monotonic performance the DAC-100AC03 or 04 grades
with maximum nonlinearity of ±0.05% (0° to 70° C) should be
specified; for less demanding applications the ±0.1% DAC100BC03 (04) grades are recommended. Due to the 10mV
LSB size, comparator Vos can provide significant zero error.
When integrating the AID Converter into a system, consideration must be given to several factors to assure best performance. First, the analog signal to be encoded should not
change more than 1/2 LSB during the encoding process; a
sample-and-hold circuit should be used if required to hold
changes to.1/2 LSB or preferably, much less (Figure 11).
Second, proper grounding of the system is essential to prevent errors due to system noise. The preferred method is to
connect the analog signal ground and digital power ground
together at only one point, right atthe AID's connector. This
will insure that digital ground currents do not flow in the
analog ground line.
LOWER POWER CONSUMPTION
Power consumption may easily be reduced from 935mW
maximum to about 310mW with two minor design changes.
The DIA and comparator power supplies can be reduced
from ±15 volts to ±6 volts and low power TTL AM25L02PC
logic function may be specified. Digital output fanout is
reduced to three standard TTL loads. The value of R1 must
also be lowered accordingly to maintain the same +1/2 LSB
bias current to the sum node.
FULL
SCALE
ADJUST
BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
+15V :II
BIT 4
BIT 3
BIT 2
MSB
BIT 1
MSi iIT1
'5V
+5V
~ ..
.- - , - - ...... +5V
-L0.o1;.!F..L4.7pF
I 50V I'oV
.,r--.
----~~t~D
START
INPUT __- - - - - - '
=~E:~~ON
__--------'
SERIAL OUTPUT . . . . . - - - - - - - - - - - - - '
~-.-
........... CLOCK INPUT
Figure 10. Complete 10-Bit AID Schematic
PAGE 15-22
Figure 11. Typical Multiplexed Data Acquisition System
MILITARY TEMPERATURE RANGE OPERATION
CONCLUSION
Operation over wider temperature ranges can be obtained by
simply specifying appropriate temperature range components. The simplicity of the three IC designs coupled with the
compatibility of the devices with MIL-STD-883A processing
assures high reliability in military applications.
Extremely compact, rugged, low power consumption successive approximation AID converters are made possible by
combining three ICs: PM!'s DAC-l00 Series 10-bit D/A,
CMP-Ol comparator, and a Successive Approximation Register. This simple, low cost design opens up new applications
such as one AID per channel operation in data acquisition
systems.
PARTS LIST FOR 8-BIT AID CONVERTER
PARTS LIST FOR 10-BIT AID CONVERTER
±O.3% maximum nonlinearity, FS tempco 120ppm/oC
1
±O.l % maximum nonlinearity, FS tempco 60ppm/o C
DAC-l00DD03 (or 04)
1
DAC-l00BC03 (or 04)
CMP-01CJ
1
CMP-01EJ
AM2504PC (Advanced Micro Devices) or Equivalent
AMP2502PC (Advanced Micro Devices) or Equivalent
Pot-2000 Bourns #3006P-1-201
Pot-200!} Bourns #3006P-1-201
1
4.7!,F CAP-Mallory #TDC475M010EL
1
4.7!,F CAP-Mallory #TDC475M010EL
2
1.0!,F CAP-Mallory #TDC105M035EL
2
1.0!,F CAP-Mallory #TDC105M035EL
2
Diode,lN4148
2
Diode,lN4148
3
.Ol!,F CAP-Centralab #CK-l03
3
.Ol!,F CAP-Centralab #CK-l03
PC Board
PC Board
Resistor 15M!} 5% 1I4W
Resistor 3.9MO 5% 1/4W
For ±O.2% maximum nonlinearity, FS tempco 60ppm/oC
use DAC-l00CC03 (or 04)
For ±O.05% maximum nonlinearity, FS tempco 60ppm/oC
use DAC-l00AC03 (or 04)
PAGE 15-23
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!
APPLICATION NOTE 12
PMI
TEMPERATURE MEASUREMENT METHOD
BASED ON MATCHED TRANSISTOR PAIR
REQUIRES NO REFERENCE
®
By Jim Simmons and Donn Soderquist
Most remote temperature measurements are made with
thermistors or thermocouples as the sensing elements. This
article shows how the function can be accomplished by us·
ing the intrinsic properties of a well·matched monolithic
transistor pair. The method is attractive for its simplicity,
accuracy, and long·term stability. Of particular utility is the
fact the output is inherently linear and is directly useable
without special linearizing circuitry.
Thermocouples can require both linearizing circuitry and
reference junction making them difficult to apply. Linear
outputs may be achieved with composite thermistor·
resistor networks but long·term stability is diffult to predict.
Ordinary silicon diodes, when operated as temperature sen·
sors, require constant current drive and extensive calibra·
tion. The matched transistor pair method has none of these
drawbacks.
4. .1V BE =
kT loge (£)
q
IC2
Note that if the ratio of collector currents IC1 to IC2 is made
constant, .1V BE will be proportional to absolute temperature
alone. No absolute values of current are required because
only a stable current ratio must be maintained. For a fixed
ratio of 2 to 1 the expression is:
.1V BE
5. .1T = 5.973 x 10- 5 = 59.73,N1°K
This predictable differential base-emitter voltage relationship allows a matched transistor pair to be used as a temperature sensor. A complete temperature measuring system
can be built with a matched pair, two constant current
sources, and a differential amplifier as shown in Figure 1.
BASIC THEORY
Matched transistor pairs have predictable relationships
which make temperature measurements possible. To
develop these relationships, let us consider the fundamental properties of a single transistor. The well known relationship between collector current and base-emitter voltage for
a Single transistor is:
1. VBE = kT loge (
q
where
$) provided Iells> >
's
EO = 10mVrK
1
°c
Boltzmann's constant = 1.38 x 10- 23 joules/OK
absolute temperature, OK
charge of an electron = 1.6 x 10- 19 coulomb
theoretical reverse-saturation current "" 1.87 x
10-14A
Ic = collector current
k
T
q
Is
=
=
=
=
v-
BE
= ~ log (~) _ kT log
q
e
IS1
q
(IC2)
e
IS2
This expression may be rewritten to:
3. .1V BE = kT loge ( I C1 ) q
C2
~ loge (!§t)
q
EO
Figure 1. Basic Temperature Sensor
Consider the difference in base-emitter voltages, .1V BE , of
two transistors operated at the same temperature:
2. .1V
OK
-55"C = 21B"K = +2.180V
+25"C = 298"K = +2.98OV
+l25"C = 398"K = +3.98OV
IS2
The values of IS1 and IS2 are a strong function of processing
and geometry variables, and are very nearly identical in a
well-matched monolithic transistor pair. As IS1 and 152 approach equality (loge 1 = 0), the second term can be
eliminated. For an ideal pair the expression becomes:
SYSTEM DESIGN CONSIDERATIONS
To illustrate this concept, let us design a system to provide
accurate temperature mesurement over the range of -55 DC
to + 125°C (218 OK to 398 OK). Other goals are: ease of calibration, long-term stability, standard resistor values, and small
physical size. In addition, the system should be capable of
operation with the senSing matched pair located up to 100
feet from the current sources and differential amplifier. A
system achieving these goals is detailed below.
SENSING MATCHED PAIR
Any mismatch will cause performance to deviate from the
ideal case shown in Equation 4, the most critical parameter
PAGE 15-24
being average offset voltage drift (TCVos). This quantity,
multiplied by the largest temperature excursion (100 OK) and
the differential amplifier gain (167.4), will be the output error
and is shown in Table 1 for typical TCVos specifications.
Clearly, system accuracy is directly related to the degree of
matching of the sensing pair. A Precision Monolithics
MAT-01H with its typical TCVos of 0.15V/oC was specified in
order to minimize this error factor.
EO -, 10mV! K
Table 1_
EO
Tevos
-55 C "" 218 K = +2.180V
+25 C = 298 K = +2.980V
+125 C 398 II. -- +3.980V
Error in oK
over 100 °
0.251 oK
lOOk
15k
v~
Figure 2_ Basic Temperature Sensor
16.7"K
CONSTANT CURRENT SOURCES
R1
100kH
R2
600n
R3
R4
100kH
600n
Two currents of a precise 2 to 1 ratio are provided by this
section. Several considerations make 5"A and 10"A good
choices as nominal operating currents for IC2 and IC1
respectively. Most monolithic matched transistor pairs are
specified at Ic = 10"A. Input bias currents associated with
the differential amplifier can be ignored because 5"A is
three orders of magnitude larger. Resistor values are small
enough to keep physical size and cost reasonable. Finally,
the quiescent currents do not develop significant voltage
drops in 100 feet of ordinary shielded-pair cable.
The two most important current source transistor matching
characteristics required are hFE and Vos long-term stability,
assuming that this part of the circuit is not subjected to
wide temperature variations. If the system is to have good
power supply and ripple rejection, the hFE match must be
maintained over a range of operating currents. These
characteristics will insure a constant 2 to 1 ratio of IC1 to IC2
is maintained.
With the circuit as shown in Figure 2, the total system has
measured power supply rejection of 1°Klvolt. Once
calibrated, long-term changes in Vos will change the current
ratio, and, in turn, the output. A Precision Monlithics MAT01GH ws selected for Q2 because it has the desired combination of specified long-term stability (0.2!,V/month) and
close hFE matching, typically 1 %.
III
W
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z
z
o
~
(,)
:J
II.
II.
ct
II
Figure 3. Differential Amplifier Design
The two op-amp differential amplifier configuration is widely used wherever high input impedance and fixed gain are
required. This amplifier uses a dual matched instrumentation operational amplifier designed and specified for differential applications, the Precision Monolithics OP-01CY.
GENERAL DESIGN CONSIDERATIONS
Assuming ideal amplifiers, the expression for output
voltage is:
DIFFERENTIAL AMPLIFIER
The sensing pair and constant current sources provide a differential voltage (t.v BE ) which is directly proportional to absolute temperature. The amplifier must acquire this voltage
difference in the presence of common mode voltages,
amplify it by 167.4, and change it from a differential to a
single-ended signal. Excellent performance is obtained using the circuit of Figure 3.
6. Eo =[E 1N1 (1+ R2)' R4)
R1
R3
With ideal resistors this simplifies to:
7. Eo= (EIN2-EIN1)
(~~
+1) provided
~~
R4
R3
In this system, (EIN1 - E1N2) has been previously defined as
Il.V BE . The actual expression for Eo may be written as:
PAGE 15-25
8. Eo
= .:lV BE
(=~ +
.:l~fE
1) but
amp selections In this stringent differential amplifier application.
= 5.973 X 10- 5 (Eq. 5)
Resistor selections can be avoided by using readily
available 0.01 % tolerance precision resistors, resulting In a
worst-case ratio match of 0.04%. This ratio match, a combination with the dual op amp's performance, results in
greater than 100dB common mode rejection at the
amplifier's input.
Therefore, the ideal overall system output expression is:
9.
Eo = (5.973 x 10 -5)
+ 1) T
(R4
R3
COMMON MODE REJECTION
Long term stability of the resistors must approach the initial
ratio match or degradation of common mode rejection can
occur over time. The resistors chosen are specified at
±50ppm/3 years and ±5ppm/oC thereby assuring stability
versus time and temperature.
At 25°C (298°K), .:lVBE Is 17.8mV while the individual sens·
ing pair base·emitter voltages are about 520mV. There is a
need to reject the 520mV common mode input voltage while
accurately amplifying the differential input voltage, .:lV BE • At
-55°C (218°K), the situation becomes more difficult with
.:lVBe of 13mV and 396mV of common mode voltage. KeepIng in mind that this Is a best case disregarding any extraneous cable pickup, it can be observed that the requirement for high common mode rejection Is very real.
DIFFERENTIAL OFFSET VOLTAGE
The amplifier'S differential input offset voltage (EOS1
EOS2) will be the major error factor. If the individual input off·
set voltages are of equal magnitude and polarity they appear as a common mode input and are rejected. The op10CY provides the additional convenience that only a single
Because the dual op amp has a specified 117dB common
mode rejection ratio match, the ability to reject common
mode inputs becomes primarily a function of resistor ratio
matching. This device eliminates the need for special op
SENSING
PAIR
I
1
2(
7
~A~1,~
\. '"
~
)
I'
"\ >-
"-
./
/"
"'
OFFSET ADJUST
cl-
PAIR
.r
3
.J
'1,
14.
L.-....2~
-=
AlA .......
1331<
I
1
2(
\.
7
~ MATQ~'G~
'"
YI
3
,:URRENT
SOURCE
6
)
I
Al
OP·1OCY
A5
'.IlI<
A7
~50k
RATIO
ADJUST
-15V
Figure 4. Complete Schematic
PAGE 15-26
r11
7
~
•
AlB
/1
5
(-16V
--
5
"
-
DIFFERENTIAL
AMPLIFIER
12
-15V
A6
1I1IlI<
A.
15k
+15V
1.
13
>---
4;/
R8
R4
l00ka
ooon
600n
CABLE
\..
R3
R2
Rl
11l1lka
5
3
UP TO
100 FEET
SHIELDED
\6
EO = 10mvrK
offset adjustment Is necessary to provide the required AVos
match; this adjustment at the same time provides a
minimum TCAVos of the differential amplifier.
INSTALLATION
Ordinary shielded pair cable, with #22 or larger conductors,
is satisfactory for most remote temperature measuring applications. Good thermal conductivity from the sensing
pair's case to the environment being measured is essential
to avoid incorrect readings. When this circuit is used for
temperature control, thermally·conductive epoxy works
especially well in attaching the sensing pair to the device
being controlled.
CONCLUSIONS
Accurate temperature measurement and control syserns are
easily and economically buill using the predictable
characteristics of modern monolithic matched transistor
pairs. This method offers long-term stability, excellent
linearity, simple calibration, and high performance in severe
environments.
CALIBRATION PROCEDURE
This is an easy two·step procedure. First, short the differential amplifier inputs and adjust the offset potentiometer until the output reads zero volts. Remove the input short. Second, with the senSing pair at a known temperature (room
temperature is suitable), adjust the ratio potentiometer for a
correct differential amplifier output reading. Having the
capability of room temperature calibration makes this cir·
cuit much more convenient to calibrate than other types.
Figure 6. Digital Thermometer with Readout in DC
OVERALL ACCURACY
N
;;;
This circuit, with the components as specified, is capable of
± 1 Ok accuracy over the full military temperature range of
-SSoC to +12S oC (21S 0 k to 39S 0 k). Optimum accuracy is
obtained with the differential amplifier and constant current
sources in a controlled environment remote from the sensing pair. Maintenance of high accuracy over long periods of
time is achieved because all components used in this
design have long·term stability specified.
ec
II)
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z
o
SENSING
PAIR
MAT.Q1H
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ac
APPLICATIONS
The circuit's output, as measured by a 10-volt full scale
digital panel meter, makes a digital thermometer. DPMs
with BCD outputs may be used in applications requiring
simultaneous direct readout and digital outputs for control
purposes.
~K
a.
a.
EO
ec
-55"C'" 218"K = 2.18V
+25 C = 298 K .. 2.9SV
Q
Q
+12SoC = 398 K .. 3.9SV
Q
Figure 7. Binary-Coded Temperature Readings with
2 ° Resolution
UP TO
UP TO
100 FT.
100 FT.
CABLE
CABLE
SENSING
PAIR
MAT·01H
ac
~K
EO
aC
EO
Q
+25 Q C '" 298 0 K = 2.98V
+125 Q C '" 398Q K = 3.SSV
Figure 5. Basic Digital Thermometer with Readout in
Degrees Kelvin (Ok)
OK
_55°C = 21S K = 2.18V
+25 C .. 298 K = 2.98V
+l25 C;z 398°K = 3.98V
_55°C = 218 0 K = 2.18V
Q
Q
Q
Figure 8. Binary-Coded Temparature Readings with
5 ° Resolution
PAGE 15-27
•
>5V
°c
oK
EO
-55°C'" 21SoK '" 2.18V
+25°C = 298"K = 2.98V
+125°C = 398°K" 3.98V
NOTE:
blAL READS WITHIN 0.1% OF APPLIED VOLTAGE =
10mVrK.
REPEATABILITY 0.05%
READABILITY 1 PART IN 10,000.
A>B=COOL
A = B = DEAD ZONE
A < B = HEAT
°c
oK
EO
_55°C = 218°K = 2.1BV
+2SoC = 298°K = 2.98V ....- - - - - - - - - - - - - -...
+12SoC = 398°K = 3.98V
Figure 9. Temperature Controller -
Digital Dial Controlled
Figure 10. Temperature Controller -
Digital Thermometer
PARTS LIST
1.
01
MAT·01H, Matched Transistor Pair
Precision Monolithics, Inc.
7.
R6
2.
02
MAT·01GH, Matched Transistor Pair
Precision Monolithics, Inc.
Resistor, 180kO, 0.1 %
General Resistance Econistor
8.
R7
3.
A1
OP·10CY, Dual Instrumentation Op Amp
Precision Monolithics, Inc.
Potentiometer, 50kO, 10%
Bourns H3006p·1·503
4.
R1, R4
Resistor, 6000, 0.01 %
General Resistance Econister
9.
R8
Resistor, 133kO, 1 %
RN55C1333F
5.
R2, R3
Resistor, 100kO, 0.01 %
General Resistance Econister
10.
R9
Resistor, 15kO, 1 %
RN55C1502F
6.
R5
Resistor, 100kO, 0.1 %
General Resistance Econistor
11.
R10
Potentiometer, 20kO, 10%
Bourns H3006p·1·203
PAGE 15-28
PMI
APPLICATION NOTE 13
THE OP-07 ULTRA-LOW OFFSET
VOLTAGE OP AMP A BIPOLAR OP AMP THAT
CHALLENGES CHOPPERS,
ELIMINATES NULLING
By Donn Soderquist and George Erdi
The OP-07, a new bipolar-input monolithic operational
amplifier, provides chopper-stabilized amplifier performance
at bipolar prices. Input offset voltage, the major error contribution in most designs, is reduced to a maximum of 2Sp,V by
a new computer-controlled on-chip trimming technique.
Such low Vos eliminates the nulling potentiometer requirement of most op amp circuits, greatly reducing system complexity while improving reliability. A description of this
amplifier's design and performance is given, followed by an
applications section showing how superior input specifications can simplify high-accuracy analog design.
IMPORTANCE OF LOW INPUT OFFSET VOLTAGE
In many applications, the initial input offset voltage of operational amplifiers causes more inaccuracy than all other error
factors combined. The other significant error parameters,
such as bias and offset currents, open-loop gain, and common mode rejection, have come closer to theoretically ideal
performance than has Vos. Forthis reason, most operational
amplifiers, monolithic and modular, are provided with terminals to allow the user to adjust this offset voltage to zero - a
costly and potentially unreliable procedure, which in many
cases degrades performance of TCVos. Monolithic op amp
manufacturers have constantly strived for improvement in
Vos from p,A709 and p,A741 at SOOOp,V, to the p,A72S at
1000p,V in 1969, tothe OP-OSA at 1S0p,V in 1972. TheOP-07A
at 2Sp,V maximum Vos is a significant milestone in monolithic
bipolar operational amplifier design.
Temperature stability is also important since the benefits of
low initial Vas are quickly lost If a small change in operating
temperature causes substantial Vos drift. Good long-term
Vos stability is required to avoid periodic re-calibrations and
degradation of system performance over time. Until now,
chopper-stabilized or externally-nulled monolithic op amps
have been the usual choices despite the disadvantages of
high noise and/or external components. The OP-07 design
achieves the desired combination of low Vos, low TCVos,
long-term Vos stability, low bias current, and low noise. It
provides performance comparable to chopper-stabilized
amplifiers with the further advantages of freedom from
chopper-frequency noise and external component requirements.
LOW Vos AMPLIFIERS
Some of the more common methods for optimizing Vos performance have been chopper-stabilized amplifiers, bipolar
amplifiers nulled to zero initial Vas, and combinational
amplifiers constructed with a matched transistor pair followed by a standard bipolar op amp. Each approach to the
Vosproblem isa compromise between allowable error, reliability and price. The purpose of this discussion is to show
how the OP-07 provides superior performance, higher reliability, and reduced size at a lower overall cost.
CHOPPER-STABILIZED AMPLIFIERS
In the past, designers have been forced to use chopperstabilized amplifiers in applications requiring less than
100p,V initial Vos. The OP-07 is a cost-effective alternative,
providing chopper-type performance with 741 ease-ofapplication. Use of a bipolar input op amp eliminates the
usual chopper problems of high noise, large physical size,
and limited common-mode input voltage range.
Low initial offset voltage specifications lose their significance if noise and long-term drift are of the same magnitude.
Although the monolithic choppers have lower average input
bias currents, the chopping action produces very large
spikes in the input currents and prevents their use with large
or unbalanced source resistors. For this reason, most chopper
manufacturers carefully avoid specifying noise currents
above 10Hz. The input bias current, remains below 4nA over
the full military temperature range, and being free from
chopper spikes, enables use in high impedance circuitry.
Another chopper-related problem is that input signals often
interact with chopping frequency components and their
harmonics. This interaction can cause errors due to intermodulation, producing slowly varying offset voltages usually below 20Hz. Chopper frequency switching transients
can also cause electromagnetic interference frequently requiring special shielding and input guarding methods to
protect adjacent circuitry. Modular choppers can have input
overload recovery times as high as five seconds and require
up to ten external components to effectively eliminate this
problem. Monolithic choppers require expensive, large external components, such as two 0.1 p,F teflon dielectric
capacitors, for wide temperature range operation. These
problems are eliminated by the OP-07.
NULLED BIPOLAR AMPLIFIERS
The major disadvantage of most high performance bipolar
op amps is that their high initial Vas must be adjusted to zero
with a nulling potentiometer or trimming resistors. In certain
amplifiers, this is also a requirement in order to optimize
TCV as performance. Selected or adjusted components re-
PAGE 15-29
...":"
Z
CC
I/)
w
l-
e
z
z
e
~
u
::::i
a..
a..
cc
III
quire special test labor, take up much-needed space, decrease reliability, and add to system complexity. "Maintainability" is poor - field replacements or renulling due to longterm Vos and resistance changes must be performed by a
skilled technician with sophisticated test equipment. Use of
an internally-nulled OP-07 avoids all of these problems since
it is a complete, fully-interchangeable device, and does not
require zeroing to optimize TeVos.
COMBINATIONAL AMPLIFIERS
This is one of the oldest methods, usually implemented with
a heated-substrate matched transistor pair in a differentialinput gain stage followed by a conventional op amp. This
method requires four precision resistors, a nulling potentiometer, external frequency compensation, and up to 360mW
of heater power. TeVos is only about 2p.VloC despite the
temperature control for the input pair. The OP-07 provides
improved performance in all parameters as well as lower
cost, elimination of calibration labor, lower noise and a tremendous reduction in total power consumption.
The symmetry of the Input stage allows examination of only
one side to demonstrate bias current cancellation. Base
drive for the input transistor, Q1, is provided by Q5 and the
external circuitry; the difference between Q5's collector current and Q1's base current being the input bias current. Q1
and Q3 are h FE-matched transistors operating at similar collector currents and, therefore, the base current of Q1 is
approximately equal to the base current of Q3. Q3's base
current is supplied by Q7, a diode-connected PNPtransistor
closely matched to Q5. Together Q5 and Q7 form a current
mirror (turnaround) and the collector current of Q5 will equal
the base current of Q3. In this manner almost all base current
for Q1 is provided by Q5 and precise bias current cancellation is achieved. Careful design has enabled this cancellation to be effective over a wide temperature range. (Figure 2.)
VS~"5V
I--- -
r-
CIRCUIT DESCRIPTION
The three-stage design concept of previous Precision Monolithics' instrumentation quality op amps was retained for the
OP-07 because, using this deSign, nulling of Vossimultaneously optimizes TeVos. (This relationship is not the case for
the more commonly used two-stage "741 "-type amplifier.)
There are additional advantages of high gain,low noise, and
predictable long-term stability. Low input bias current is
achieved by bias current cancellation; I.e., currents are generated equal in magnitude but opposite in direction to the
base currents of the input transistors Q1 and Q2 in the simplified schematic of Figure 1.
-
--- f--- 1 -c--
-
~~
r-.... ~ ~~
Of'·07
OP·07A
r-- t-l
V
----
V V
I
-50
50
TEMPERATURE
100
rc)
Figure 2. Input Bias Current V8 Temperature
V+7O---~--
.7
*NOTE:
R2A AND A2B ARE
ELECTRONICALLY
19
ADJUSTED ON CHIP
AT FACTOR V FOR
MINIMUM INPUT
••
OFFSET VOLTAGE.
NON
.,.
3
INVERTING
INPUT
OUTPUT
•
+---+--t:iozo
Figure 1. OP-07 Simplified Schematic
INPUT STAGE
FOLLOWING STAGES
To achieve lowest initial Vos. TeVos and noise, a simple
differential input pair, Q1 and Q2, was chosen. Vos nulling
resistors R2A and R2B are electronically adjusted and will be
covered separately in the trimming discussion. R3 and R4, in
conjunction with Q21-Q24, provide input differential overvoltage protection.
The first stage output is buffered by emitter followers Q9 and
Q10, and applied to a high-gain differential stage, Q11 and
Q12. Its output, the junction of Q12, Q14, Q15, and R5, drives
a short-circuit-protected complementary emitter follower
power output stage.
PAGE 15-30
COMPENSATION
Frequency compensation of the OP-07 is accompished
using three capacitors. Feedforward capacitor C3 bypasses
the second stage lateral pnp's at high frequencies and, therefore, the excessive phase-shift normally associated with
these transistors is circumvented. The dominant pole of the
amplifier is set by C 2which feed back around the second and
driver stages and rolls off the open loop response at 20dB
decade. The presence of C 1ensures that the high frequency
signal path is single-ended by rolling off the response of one
side of the input stage. The total internal capacitance on the
100 X 53 mil chip is 21 OpF, a remarkable amount for a monolithic device.
LAYOUT
The circuit layout has thermal symmetry, a concept which
has been used quite extensively on precision amplifier
designs since its inception in 1969. 1 Variations in power
dissipation in the driver and output stages, and the resultant
thermal gradients affect the critical input transistors identically, thereby preventing offset voltage changes at the input.
With an error free second stage it may be assumed that the
input transistor collectors are equal in potential.
IC1 RR
2.IC1RL=IC2RRandIC2=RL
kT
IC1
kT
(IC2)
3. Vbe= - log. ( - ) , V be2 =-log. -1q
151
q
52 '
Provided Idls»
Substituting in Equation 1:
kT
IC1
kT
IC2
4. Vos= -log. ( - I ) - - 10ge ( - I )
~
q
~
q
Rewriting:
IC1 152
kT
5. Vos=-Iog e( - . - )
q
IC1 151
Substituting from Equation 2:
kT
RR 152
6. Vos= - log.(- . - )
q
RL 151
For Vos = zero:
RR ~
7. RL '151 = 1
INTERNAL NULLING TECHNIQUE
To understand the nulling technique some fundamental relationships should be examined using the equivalent circuit of
Figure 3. (Errors caused by the second stage are effectively
divided by the first stage gain and will be neglected in this
discussion.) Vos is defined as the voltage which must be
applied between the input terminals to obtain zero voltage at
the amplifier's output. Referring to Figure 3:
Where:
k = Boltzmann's constant = 1.38 X 10-23 joulesl o K
T = Absolute temperature, 0 K
q = Charge of an electron = 1.6 X 10- 19 coulomb
Is = Theoretical reverse-saturation current
1. Vos = Vbe1 - Vbe2 , VOUT = zero
Ie = Collector Current
v+
7
R2E
r
R2C
Zl
Z3
Z2
Z,
·'1
RR
--j
R2A
1
-------<>
R1A
f
SUCCEEDING
STAGES
R18
C1
IC2
+
V+
7
Therefore, by adjusting the ratio of ~ the inherent proces-
o
IlL
IlL
Through this technique, Vosof the entire "raw" OP-07 distribution can be nulled to less than 150/-,V, with the majority
being under 75/-,V. Prime grade yields are high, providing
adequate numbers of OP-07A devices with a Vos maximum
of 25/-,V.
PERFORMANCE
Figure 3. Offset Nulling Circuit
1Editor'. note: This concept was originally introduced by George Erdi during
employment at FairChild Semiconductor Research and Development.
~
Z
Z
sing-related differences in 151 and Is2 which cause Vbedifferentials may be cancelled. Earlier amplifier designs achieved
the adjustment of collector resistance by an external nulling
potentiometer between Pin 1 and Pin 8 with its wiper connected to Pin 7 (Figure 1).
In the OP-07, permanent nulling is accomplished by shorting
out a small percentage of RRor RLas determined by a computer programmed with Equation 6 and a lookup table. This
is done by reading Vos before trimming, comparing its magnitude and polarity with a lookup table value, and shorting
out one of the normally nonconducting zener diodes. The
short is created by passing a high current pulse through the
selected zener, fusing its metal contacts into the silicon as
shown in Figure 4. High volume production is achiAved
through automation, with initial device testing at wafer probe
including Vos trimming requiring less than one second.
R20
RI.
I
1.
The specifications in Table 1 and curves of Figure 5 show
noise, initial Vos, and long-term stability performance unsurpassed by any other monolithic op amp. This device is free of
PAGE 15-31
~u
::::i
0(
SILICON
SILICON
OXIDE
NITRIDE
~w~ 8&76 1---1---"--1--+
VS·'t16V
METAL
o
P
DIFFUSION
DIFFustON
R=lOGn
~
N+
l--m~"~tl_METAl
FUSED
i
INTO
SiliCON
50
I----t----jl--j----+-
~
METAL
SiliCON /-)'----,-'''-='--0_'''''';-.1'-,NITRIDE
METAL
METAL FUSED
INTO 51 LICON
Ib) SIDE VIEW
tal TOPVIEW
.....
0
..
TEMPERATURE rCI
Figure 4. Short-Circuiting of Zener Diodes
rable 1. OP-07A Performance
Figure SA. Untrimmed Offset Voltage vs Temperature
OP-07 Performance@ Vs =±1SV, TA = 2S·C
Pare",.",
Offset Voltage. vos
Drift with Temperature
Drift with Time
Offset Current. los
Drift with Temperature
~put
bias current, I B
Noise Voltage O.IHz to 10Hz
Typical
MIniM••
25
to
0.2
Units
"V
0.6
"VI'C
0.2
1.0
"Vlmo
0.3
5
2.0
25
nA
pAl'C
±0.7
±2.0
nA
0.6
"Vp-p
0.35
Noise Current O.IHz to 10Hz
14
30
pAp-p
I nput Resistance - Differential
80
30
MO
Input Resistance - Common Mode
200
Common-Mode Rejection
126
110
Power Supply Rejection
110
100
dB
Voltage Gain
500
300
VlmV
G1l
dB
Slew Rate
0.25
VI"s
Unify Gain Bandwidth
1.2
MHz
-12
1-1-1-+-+-+-+-+-+-+-+-+-1
1
the common problems of latchup, noise, compensation
capacitors, and narrow power supply limitations. Power
supply rejection ratio (PSRR) exceeds 100dBoverthe unusually wide range of ±3 to ±1B volts. Common-mode rejection
is specified over a full ±13 volt input range allowing small
signal amplification in high nOise environments and use in
Inverting. non-inverting. and differential applications. The
amplifier is completely self-contained - no external compensation or protection components are required. It is an
excellent replacement for, chopper-stabilized amplifiers
where reductions in cost. noise, size, and power consumption are desired. and for monolithic op amps where elimination of the offset nulling potentiometer is desirable.
3
4
5 6
7 8
TIME-MONTHS
9
10 11 12
Figure SB. Offset Voltage Stability vs Time
The pinout of the OP-07 allows direct replacement of 725.
10B, and OP-05 types without circuit changes while 741 devices may be replaced by removal of the nulling potentiometer.HA-2900 series chopper-stabilized amplifiers may be
'replaced by removing the two 0.1~F'capacitors and the
1500pF capacitor whimever cost or noise reductions are
required. Table 2 is included to show comparative performance in wide temperature range applications.
Table 3 compares various OP-07 versions with competitive
op amps and over the 0·170·C temperature range. An
absence of noise and long-term stability specifications for
2
BANDWIDTH (kHzl
Figure SC. Input Wldeband Noise VI Bandwidth (0.1 Hz to
Frequency Indicated)
PAGE 15-32
graph (Figure 7A) shows relative performance of a OP-07
and a monolithic chopper in the same X100 configuration;
the chopper is seen to have at least 200I'Vp_pnoise referred to
the input. Clearly,low Vosspecifications are not very meaningful if input voltage noise is the predominant error factor.
some amplifiers should caution potential users of possible
deficiencies in those areas. This same comment would apply
to "typical-only" specifications since accurate predictions of
circuit performance can only be made with a fully specified
device.
Chopper-frequency noise is a common mode current noise
occurring at the chopping frequency due to switching transients. The effect of a 500kO source mismatch is shown in the
wideband curent noise photograph comparing a OP-07 with
a monolithic chopper in the non-inverting buffer application
(Figure 78). High source impedance circuits require low
PERFORMANCE
The low frequency noise photograph in Figure 6A shows
O.35I'Vp_p input voltage noise (O.1Hz to 10Hz), the best performance available in an instrumentation op amp at this
writing. The wideband voltage noise comparison photo-
Table 2. Military Temperature Range Performance Comparison
Manufacturer'S
Part
Number
VosMaximum
-55° 1+125° C
TCVos Maximum
-55° 1+125° C
(Unnulled)
6Ol'V
O.6I'V/oC
2OOl'V
1.31'VloC
HA-2900
6Ol'V
O.6I'VloC
OP-05A
24Ol'V
O.9I'V/oC
OP-05
7OOl'V
2.01'V/oC
I'A725
15OOl'V
5.01'V/oC
OP-07A
OP-07
LM108A
5.01'VloC
1OOOl'V
Voltage
Noise
Typical
F = 10Hz
Current
Noise
Typical
F = 10Hz
10.3nVI
O.32pAl
JHz
".!""Hz"
10.3nVI
O.32pAl
JHz
JHz
Not
Specified
(Chopper)
900nVI
JHz
10.3nVI
O.32pA
JHz
".!""Hz"
10.3nVI
O.32pAI
JHz
JHz
1.0pAl
15mVI
JHz
43nVI
JHz
".!""Hz"
Not
Specified
I Bla8
Maximum
-55° 1+ 125° C
Long-Term
Drift
Typical
4nA
O.21'Vlmo
6nA
O.21'V/mo
1nA
Not
Specified
4nA
O.21'Vlmo
6nA
O.21'Vlmo
200nA
Not
Specified
3nA
Not
Specified
...ofa
z
z
o
~
(.)
~
II.
.oC
Table 3. Commercial Temperature Range Performance Comparison
Manufacturer's
Part Number
VosMaximum
OOI70°C
Long Term
Drift
Typical
Long Term
Typical
Maximum
Voltage Noise
Maximum
O.lHz to 10Hz
Voltage Noise
Maximum
O.lHz to 10Hz
OP-07A
(M)
451'V
O.21'Vlmo
1.01'V/mo
O.35I'Vp_p
OP-07
(M)
13Ol'V
O.21'V/mo
1.01'V/mo
O.35I'Vp _p
O.6I'Vp _p
OP-07E
(C)
13Ol'V
O.31'Vlmo
1.51'Vlmo
O.35I'V p _p
O.6I'Vp _p
O.6I'Vp_p
OP-07C
(C)
25Ol'V
O.4I'V/mo
2.01'Vlmo
O.38I'Vp _p
LM108A
(M)
7251'V
Not Specified
Not Specified
Not Specified
Not Specified
HA-2900
Chopper-Stabilized
(M)
6Ol'V
Not Specified
Not Specified
351'Vp _p
Not Specified
HA-2905
Chopper-Stabilized
(C)
8Ol'V
Not Specified
Not Specified
351'Vp _p
Not Specified
AD504M
(C)
5451'V
1Ol'Vlmo
Not Specified
Not Specified
AD50BL
(C)
6121'V
Not Specified
1Ol'Vlmo
1.0I'Vp _p
Not Specified
Typical
Inverting-Only
Chopper Module
(C)
951'V
2.01'Vlmo
Not Specified
1.7I'Vp _p
Not Specified
M = 55° /+125°C Range Device
C = 0° /+ 70° C Range Device
PAGE 15-33
O.65I'Vp_p
O.6I'Vp _p
II
500kn
Figure SA. Low Frequency Noise
(x1)
lOon
lOon
INPUT REFERRED
Figure 7B. Wldeband Current Noise vs Chopper
NOISE"~ = ~=
power using automated test equipment. The pass limits are
"guard banded" or made small enough with respect to Vos
maximum specification to compensate for not having directly observed warmup drift.
200mV/cm
Figure 6B. Low Frequency Noise Test Circuit
The first month stabaility, defined as changes in Vos from
one hour to 30 days, is typically 2.5p.V. Even with closely
maintained equipment, individual measurements with time
can suffer from inaccuracies on the order ofa half-microvolt
due to low frequency noise and slight temperature variations. Fortunately, over a large number of measurements
these errors tend to integrate out, and an accurate trend line
can be defined.
Thetrend line is defined as the drift per month averaged over
the month one to month twelve period, and is generally an
order of magnitude better than the first month drift (Figure
56). Over 1.7 million device hours of testing and characterization have been logged in order to accurately specify longterm Vosstability. Results indicate an average trend line drift
of O.2p.V/month-outstanding stability performance for any
amplifier, regardless of its technological approach.
10DkH
LONG-TERM Vos TESTING CONDITIONS
The deceptively simple circuit of Figure 8 is used for longterm Vos stability testing. Three absolutely essential conditions must exist for accurate measurements: still air, power
supply accuracy, and long-term temperature control
(11:1001
Figure 7A. Wldeband Voltage Noise vs Chopper
input noise currents, which as the photograph illustrates,
can be larger than input bias current with certain operational
amplifiers.
2OOk!)
LONG-TERM Vos DRIFT
>--_-ovo
Input offset voltage drift over time has three components:
warmup drift, first month drift, and trend line stability.
Warmup drift is a change in Vos occurring in the first few
minutes of operation. In order to produce high volumes of
OP-07s, Vos is measured 0.5 seconds after application of
Figure 8. Long-Term Offset Voltage Test Circuit
PAGE 15-34
the regulated output. Accuracy is primarily determined by
three factors: the 5ppm/o C temperature coefficient of 01,
1ppm/o C ratio tracking of R2 and R3, and operational amplifier Vas errors.
All components, including sockets and solder joints, are
enclosed in a metal box to eliminate air movement and
temperature gradients. Thermoelectric error voltages may
be generated if the dissimilar metal junctions formed by
solder joints and socket contacts are at different temperatures. This effect is minimized by using "low thermal" solder
(70% Cadmium, 30% Tin) and nonmetallic flux, such as Kester #1544, to avoid ionic contamination.
Vas errors, amplified by 1.6 (Aved, appear at the output and
can be significant with most monolithic amplifiers. For
example: an ordinary amplifier with TCVas of 51'Vlo C contributes 0.8ppml" C of output error while the OP-07 at
0.31'VloC (0.5ppm/oC) effectively eliminates TCVas as an
error consideration.
Although the power supply rejection ratio (PSRR) of the
OP-07 is extremely high, nevertheless it should be considered asa potential error factor in long-term Vas testing. The
power supplies are verified to be at ±10mV before each set of
weekly readings. This removes any possible significant
errors due to the PSRR specification of 110dB (3I'VIV01t).
Perhaps the most easily overlooked accuracy requirement in
this and many other critical circuits is long-term Vas stabil ity.
In this circuit, a 741 drifting at 100l'Vlmo would cause
200ppm/year of output drift - a very large amount. This type
of problem is particularly troublesome in potted subassemblies where periodic recalibration is impossible. Use of the
OP-07 at 11'Vlmo maximum avoids this potentialiy troublesome condition.
All long-term Vastesting is performed in a controlled laboratory environment of 30·C to eliminate TCVas, 0.2I'VI·C, as
an error possibility.
APPLICATIONS OF OP-07
LARGE SIGNAL BUFFER - 0.005% WORST-CASE
ACCURACY
HIGH STABILITY VOLTAGE REFERENCE
The simple bootstrapped voltage reference of Figure 9 provides a precise 10 volts virtually independent of changes in
power supply voltage, ambient temperature, and output
loading. Correct zener operating current of exactly 2mA is
maintained by R1, a selected 5ppm/o C resistor, connected to
Unity gain large-signal buffers are one of the most common
applications of operational amplifiers. The low Vas and high
CMRR of the OP-07 provide high accuracy, and small physical size is achieved due to the complete absence of external
components. Performance over the appropriate temperature
range is shown for the various OP-07 selections. Note that
the errors on Table 4 are absolute worst-case numbers, a
combination that would be extremely unlikely in actual practice. A figure closer to expected overall performance based
on the RMS sum of typical errors is also included. Typical
.,
>"--+--<>
1N4579A
6.4V ±5%
±6ppmrc
EO = tOV
01
R1
=;: ~o~~
R2 '"
1'~ ;o~~
R3 = 1
o TO
20kn
~-_-{) EO
SOURCE
x~~-3
= 'lOV
EIN
tlOV
AVCL -. 1.6
Figure 9. High Stability Voltage Reference
II
Figure 10. Large Signal Voltage Buffer
Table 4. Large Signal Voltage Buffer Error Analysis
OP-07A -55° /+125°
Error
Source
Vas l
OP-07 -55° 1+125·
MinIMax
Typical
MinIMax
Typical
OP-G7E 0°/+70·
Min/Max
OP-07C 0° /+ 70·
Typical
MinIMax
Typical
60p.V
25p.V
200p.V
60p.V
13Ol'V
451'V
25Ol'V
851'V
80p.V
20p.V
120p.V
4Ol'V
11Ol'V
3Ol'V
18Ol'V
441'V
CMRRl
50p.V
7p.V
50p.V
7p.V
7Ol'V
71'V
1411'V
1Ol'V
PSRRl
40p.V
10p.V
40p.V
10p.V
631'V
131'V
1OOl'V
2Ol'V
Gain l
50p.V
25p.V
67p.V
25p.V
56p.V
22p.V
100p.V
251'V
AVas5 Years
60p.V
12p.V
60p.V
12p.V
90p.V
18p.V
120p.V
24p.V
340p.V
44p.V·
537p.V
78p.V·
519p.V
63p.V·
891p.V
104p.V·
0.0034%
0.0005%'
0.0054%
0.0008%"
0.0052%
0.0006%'
0.009%
0.001%'
ISlas
1
Total
Percent Full
Scale
·RMS Calculation
1Full operating temperature range specification.
PAGE 15-35
1.25kf2
14-BIT 0.003%
LINEARITY
REFERENCE
CAe
IFS'" -8mA
lkn
, EO
>~O---<: TO PEAK DETECTOR
-15V
EOUT
o TO 10 VOLTS
EO = 10 (EREF - EOUT) '" % NONLINEARITY
Figure 11. D/A Converter Test System
military temperature range errorforthe OP-07A is 44/LV -far
smaller than most other amplifiers' input offset voltage error
alone.
Another OP-07 is used in the dfference amplifier for high
common mode rejection and Vos stability. This op amp is
well-suited for critical test system circuits, providing accurate measurements, high reliability, and calibration-free
operation.
CALIBRATION-FREE DAC SYSTEM
The circuit of Figure 11 is part of an automated test system
used for measuring 6-bit to 10-bit OAC nonlinearity at each
possible digital input code combination. It detects the largest difference between a 14-bit linear reference OAC and a
unit under test, and generates an output voltage that is
directly proportional to nonlinearity as a percentage of full
scale.
Reference OACs are frequently supplied having currentoutput only, with selection of a summing amplifier left up to
the user. Summing amplifier characteristics must not cause
degradation of reference OAC linearity, full-scale, or zero
scale performance or erroneous testing could occur. In addition, Vos errors are direct zero scale output errors, so both
long-term Vosstability and drift overtemperature are important. Using a OP-07, total EREFerrors due to op amp performance are estimated at less than 100/LVorO.2 LSB on a 14-bit
base, permanently eliminating zero calibration while maintaining test system accuracy. Summing amplifier applications requiring higher speed should use the composite
amplifier of Figure 12
RF
EIN
RI
EO
ED = -EIN
M+ IBIAS RF
Figure 12. High Speed, Low Vos Composite Amplifier
COMPOSITE SUMMING AND AMPLIFIER WITH
HIGH SLEW RATE AND LOW Vos
The circuit configuration of Figure 12 is a method for obtaining a 18V1/Ls slew rate with OP-07 Voscharacteristics. Vosof
A2 (3mV) is continuously nulled by forcing the sum node to
equal Vos of Al through a secondary feedback loop formed
by Rl, R2, A2's input stage, and R3. An error due to I Biasof A2
limits practical values of feedback resistances to a maximum
of 5kO in most applications; a fast FET input op amp could be
used as A2 to reduce the circuit's bias current to approximately 2nA. The circuit is also good as a current-output OAC
summing amplifier because zero scale offset adjustments
are not required and high speed is preserved. Composite
connections such as this are generally quite cost-effective
compared to Single op amps having both high slew rate and
good Vos specifications.
ABSOLUTE VALUE CIRCUIT WITH MINIMUM ERROR
This circuit provides precise full-wave rectification by inverting negative-polarity input voltages and operating as a unitygain buffer for positive-polarity inputs. It is useful for conditioning inputs to unipolar A to D's, positive peak detectors,
Single quadrant multipliers, and magnitude-only measurement systems. A polarity indication for sign plus magnitude
applications is present at the output of A 1.
For·a positive input, the circuit operates as two stages of
inverting unity-gain amplification. As the input goes positive,
the output of Al becomes negative, turning 02 off and 01 on,
placing the junction of R3 and R4 at -E 1N • VA is at zero volts
because 02 is off and only insignificant A2 bias current flows
in R2. A2 operates as a second inverting unity-gain stage and
Eo equals E 1N •
For negative inputs, the first stage gain to point VA is -2/3
because 02 is on, 01 is off, and 1/3 of the input current,
E 1N/Rl, flows in R3 and R4. Thesecond stage is operated in a
PAGE 15-36
non-inverting gain of 1.S configuration with VA as its input,
giving an over-all circuit gain of -1.
Using conventional op amps, input offset voltage is usually
the predominent error factor because it is doubled and
added to E 1N. For example, with EIN of 100mV, only O.SmV of
Vos will cause 1% output error. Clearly, A1 and A2 must be
low Vosop amps to achieve high accuracy over the full input
voltage range. By using a OP-07, performance is mainly a
function of resistor ratio matching and diode leakages. Gain
errors due to resistor matching will typically be less than
0.3% when R2-R4 are within 0.01% of R1 's value. Low leakage
diodes should be used to prevent errors from reverse current
flow in R2 or R3 which would appear as Vos error of A2.
R3
lOOkS!
10k!!
Single-stage maximum full scale errors contributed by the
op amp range from 0.001% for a OP-07A to 0.004% for a
OP-07C. This makes resistor-related errors of ratio matching
and temperature tracking the major accuracy considerations. Instrumentation quality operational amplifiers with
ultra-low Vos allow simple construction of high performance
summing and differencing amplifiers.
INSTRUMENTATION AMPLIFIERS FOR
THERMOCOUPLES
Thermocouples are very low voltage output temperature
transducers requiring differential DC amplification before
linearization and display. Typical full scale outputs are under
SOmV with some types having as low as sjJ.vrc sensitivity.
R5
10k!!
R4
stage at weekly or monthly intervals to compensate for longterm Vosdrift. This circuit, with 1!N to 2jJ.V per month maximum change in Vos. completely eliminates periodic calibration while insuring long-term accuracy.
R1
10kU
'IN
These very small input signals often have sizable common
mode voltages present because the thermocouples are frequently located in high-noise industrial environments. The
single op-amp instrumentation amplifier of Figure 1S has the
high common mode rejection and long-term accuracy required for this stringent application.
o---"NI,.......,__--"-l
+10V
POSITIVE INPUT
1.
VA
2.
EO -
3.
WITH Rl = R3
4.
Vas ERROR INCLUDED:
EO = EIN + 2VOS2
=
0,02 OFF, 01 ON
_(-EINAlR3). (-R5)
R4
=
= e'N
R4 = R5'
NEGATIVE INPUT
1.
D1 OFF, D2 ON
2.
-:~N=~+R3~~4
EO
R3 A5
R'fR4
=
E'N
3
EO
=
VA (1 + R3
~
4.
WITH R3" R4 '" R5:
5.
EO" _ (R2) ~~~R+2 R+4~~\5)R~:N
6.
WITH Rl
7.
Vas ERROR INCLUDED
EO
B.
=
=
The amplifier achieves about 100dB of common mode voltage rejection over a full ±13 volt range when the ratios of
R2/R1 and R4/R3 are matched within 0.01%. R1 Band R3B
are usually around 1k!1, a value large in respect to line resistance but small enough to make voltage drops from input bias
currents negligible. Input voltages and Vos are both amplified by 200 so Vos changes, either long-term or due to
temperature, can cause direct output error. For example,
with a sjJ.vrc thermocouple, the OP-07A holds this error
factor to O.OSo C/year and 1 ° C for an amplifier operating
temperature range of 100° C (-2S0 C to + 7So C) - a typical
industrial environment. For 0° C to 70° C applications. the
low-cost OP-07C holds output error due to a change in Vos
below 1° C/year and 2° C over the full commercial operating
temperature range.
+R~4)
R2 '" R3
EO
R4.
=
1.5VA
EO'" -EIN
-EIN + 1.5VOS2 - O.5VOSl
FOR BOTH INPUTS
EO
=
+ 'E'N
Figure 13. Precision Absolute Value Circuit
PRECISION SUMMING AMPLIFIER WITH
NO ADJUSTMENTS
Figure 14 shows the basic op amp connection for analog
computation, a precision summing amplifier. Analog computers use several of these stages connected in combinations to produce continuous outputs that are a function of
multiple input variables. Single-stage accuracy is important
because errors accumulate throughout a system and determine its over-all performance. Some analog computers
require time-consuming and annoying recalibration of each
The circuit is useful whenever small differential signals from
low-impedance sources must be accurately amplified in the
presence of large common mode voltages.
R1
':O:lkn
SENSING JUNCTION
R1A
R1B
LINE RESISTANCE
R4
10kSl.
'1
R1
10k.Q
'1
R'
10kn
"
'3
R3
10kn
EO"' 200 (E2 - El)
R3
:::lkn
LINE
RESISTANCE R3A
COLD
REFERENCE
JUNCTION
"
'0
EOS - Vas
R4
w,=~
-15V
Figure 14. Adjustment-Free Precision Summing Amplifier
Figure 15. High Stability Thermocouple Amplifier
PAGE 15-37
fL~ ~tl
R3B
200
Ul
W
~
o
z
z
o
~
u
:::i
11.
11.
>C(
CONCLUSIONS
The OP-07 Ultra-Low Offset Voltage Operational Amplifier is
a cost-effective monolithic alternative to the chopperstabilized amplifier and is suitable for a wide variety of critical applications. An internal trimming procedure achieves
significant improvements over previous bipolar designs in
offset voltage, noise levels, and long-term stability at a moderate cost. For the firsttime, a complete precision IC op amp
is available requiring no external components whatsoever
for general application, thus increasing reliability by decreasing system complexity. The adjustment-free, fully interchangeable device allows tremendous simplification of cali-
bration and field servIcing procedures. This is a most
powerful and cost-effective design tool- chopper-type performance and bipolar prices with 741 ease-of-operation.
REFERENCES
1. Minimizing Offset Voltage Drift with Temperature in
Monolithic Operational Amplifiers, G. Erdi, Proceedings
of the National Electronic Conference, Volume 25,1969
2. A Low Drift, Low Noise Monolithic Operational Amplifier
for Low Level Signal Processing, G. Erdi, Fairchild Semiconductor Application Brief #136, July 1969
PAGE 15-38
APPLICATION NOTE 14
PMI
INTERFACING PRECISION MONOLITHIC'S
DIGITAL· TO·ANALOG CONVERTERS
WITH CMOS LOGIC
By Donn Soderquist
The rise in popularity of CMOS logic has created a demand
for digital-to-analog converters with CMOS-compatible logic
inputs_ PMI DACs allow simple CMOS interfacing in most
applications. Since interfacing is easily achieved, the proven advantages of low-cost and high speed are available to
both TTL and CMOS system designers. This application
note discusses interfacing methods and rules for both
voltage and current output types and describes several
typical CMOS system applications.
INTERFACING THE DAC-08l20
The DAC-OB design incorporates a unique logic input circuit
which enables direct interface to all popular families and
provides maximum noise immunity. This feature is made
possible by the large input swing capability, 2p.A logic input
current and completely adjustable logic threshold voltage.
ForV- = -15V, the logic inputs may swing between -10V
and +1BV. This enables direct Interface with +15V CMOS
logic, even when the DAC-OB is powered from a +5V supply.
Minimum input logic swing and minimum logic threshold
voltage are given by: V- plus (lAEF • 1kO) plus 2.5V. The
logic threshold may be adjusted over a wide range by placing an appropriate voltage at the logic control pin (Pin 1,
VLcl. It should be noted that Pin 1 will source approximately
100p.A; external circuitry should be designed to accommodate this current.
INTERFACING THE DAC-76/86/87/88189
These companding D/A converters are similar to the DAC-OB
in that the input logic threshold is two diode drops positive
with respect to the logic control pin. However, more current
flows into the logic control pin requiring active current
sourcing as shown below.
VLC (Pin 10) is placed as a potential which is 1.4V below the
desired logic input switching threshold. However, this
voltage source must be capable of sourcing and sinking a
changing current at Pin 10. The negative voltage at the logic
inputs must be limited to +10V with respect to V- (Pin 13).
INTERFACING THE DAC-210
....
Use the same circuit as in Figure 2 except connect to Digital
Ground, Pin 11. Input logic threshold will be 1.4V above the
potential at Pin 11.
z
c(
z
o
5
::::i
A.
A.
c(
A
3kn
TO PIN 10
VLe
21lkn
'-------'.
R3
..... A
VTH .. VLC + 1.4V
+lOV CMOS
VTH = +5.0V
+15V CMOS
VTH = +1.6V
+15V
+10V
lOkn
9,1kr!
6.2kn
VLe
NOTES:
1. SET THE VOLTAGE "A" TO BE AT THE DESIRED LOGIC INPUT SWITCHING
THESHOLD.
2. ALLOWABLE RANGE OF LOGIC THRESHOLD IS TYPICALLY -5V TO +13.5V
+5V CMOS
VTH = +2.8V
WHEN OPERATING ON ±16V SUPPLIES.
VLe
VLe
Figure 2. Interfacing Circuit For CMOS Logic Inputs
6.2V
ZENER
;rD.'"
62kl
;;r
16kl
O."F
Figure 1_ DAC-08/20 CMOS Interfacing with True
CMOS Threshold
III
W
b
z
Fastest settling times are obtained when Pin 1 sees a low
impedance. If Pin 1 is connected to a resistive divider, as in
Figure 1, it should be bypassed to ground by a 0.1JLF
capacitor.
+12V TO +15V
'7
INTERFACING THE DAC-02l03l04l05/06
Five complete voltage output monolithic DACs are described in this section: the DAC-02I5 and DAC-03, 10-bit plus
sign devices, and the DAC-04/06 10-bit two's complement
coded converters. These DACs are well-suited to use in
Ravlsad January 1980
PAGE 15-39
I
CMOS systems as their complete, internal temperature-.
compensated references eliminate the external reference
voltage requirement, a major source of power dissipation,
drift, and cost in some CMOS compatible designs.
ANALOG
OUTPUT
--0 ZERO
VOLTS
These DACs have logiC input stages which require about
1pA and are capable of operation with inputs between - 5
volts and. V+ less 0.7 volt This wide input voltage range
allows direct CMOS interfacing in many applications, the
exception being where the CMOS logic and D/A converter
must use the same power supply.
In this special case, the diode should be placed in series
with the CMOS driving device's Voo lead as shown in Figure
3. The diode limits Voo to V + less 0.7 volt - since the output from the CMOS device cannot exceed this value, the
DAC's maximum input voltage rule is satisfied. Summarizing: in all applications, these high-speed DACs require
either no interfacing components, or, at most, a single inexpensive diode for full CMOS compatibility.
-0.7 VOLTS
"ON" CONDITION
ONLY
BIT-WEIGHTED
CURRENT
SOURCE
Figure 4. DAC-100 Logic Input Stage
biasing Q4 in the "OFF" condition. For the "ON" condition
(V 1N ",,0.7 volts), Q3 is "OFF" - all of the bit-weighted current, I" flows from the analog output through Q4 and
ultimately to V- .In the "OFF" condition (V IN ",,2.1 volts), Q3
is "ON", Q4 is back biased, and the bit-weighted current is
sourced from the positive power supply instead of the
analog output.
VOLTAGE
OUTPUT
1N4148
If V1N is too high, Q4's emitter-base junction will experience
reverse breakdown and a fault condition will occur. Equation 1 describes this condition:
1. BV 1H = VBE1 + VBE2 + VBE3 + BV EB4 == 7.7 volts
INPUTS 0;:;; V+ LESS O.7V
Using this relationship, it can be seen that a conservative input voltage limit would be around 6.5 volts. When the 6.5V
input limited is observed, DAC-100 operation with CMOS inputs is easily achieved as demonstrated in the following applications section.
Figure 3_ DAC-02/03/04/05/06 CMOS Interfacing
CMOS COMPATIBLE OPERATION OF DAC-100 WITH
±6 VOLT POWER SUPPLIES
INTERFACING THE DAC·100 AND DAC·01
The DAC·100, a complete 10-bit monolithic fast current output DAC is available in a wide range of electrical grades and
packages. This device requires only about 1pA of input current into each logic stage. Similar logic input stages are
used In the DAC-01, a complete voltage output 6-bit DAC.
One rule must be observed when interfacing these DACs
with CMOS inputs: logiC input voltages should not exceed
6.5 volts or V + , whichever is smaller. To provide an understanding of this rule, it is necessary to discuss the logic input stage design.
This is the most convenient method of interfacing a
DAC-100 with CMOS logic. At ±6 volts, DAC-100 power
dissipation is only 80mW, which is very small considering
the inclusion of a complete internal reference. No interfacing components are required with ±5% power supplies,
and the CMOS logic and DAC-100 can use the same +6 volt
power supply. In this application the device is directly
CMOS compatible.
DAC·100 LOGIC INPUT STAGE DESIGN
The block diagram in Figure 5 illustrates a convenient
method for interfacing CMOS input levels between 6.5 volts
and 15 volts with a DAC-100. Inexpensive and readily available CMOS hex buffer/converters step down the high-level
inputs to TIL levels that cannot exceed 5 volts - clearly
satisfying the input stage voltage rule.
HIGH LEVEL CMOS INTERFACING
For simplicity, only one of the ten identical input circuits is
shown in Figure 4. The DAC-100 uses a fast current-steering
technique that switches a bit-weighted current between the
positive supply (V +) and the analog output, which is usually
constrained to be at zero volts (virtual ground) by an external
summing amplifier.
Switching is accomplished by forward biasing Q4, a diodeconnected transistor, for the bit "ON" condition and back
In addition to level shifting, buffer/converters provide input
coding flexibility since they are available as inverting
(CD4049A) or noninverting (CD4050A) devices. This gives the
PAGE 15-40
Since buffer/converter power consumption is very low, the
required + 5 volts can be provided by a simple regulator or
even a resistive divider in some applications. In a multi·DAC
system, one central, inexpensive 3-terminal IC regulator can
supply several level shifting devices. Next, we will examine
a complete circuit using all of these concepts in a high·
speed CMOS compatible DAC.
COMPLETE CMOS COMPATIBLE DAC
The complete, 10·bit, voltage output DAC in Figure 6 has
CMOS input compatibility, high speed, and low·cost. Cur·
rent output from the DAC·10 is accurately converted to a
voltage by the Precision Monolithics OP'()1, a high speed op
amp which has been specifically designed for the DAC summing amplifier application. Input offset voltage of this op
amp is typically 2mV, eliminating the requirement for zero
scale adjustment.
LEVEL
SHIFTING
BUFFERI
CONVERTERS
LOW LEVEL
TTL OUTPUTS
Voo
Figure 5. Block Diagram -
CMOS to DAC·100 Interface
COMPLETE CMOS COMPATIBLE
·DAC DYNAMIC PERFORMANCE
user a choice between negative·true and positive·true binary
coding and allows the same basic DAC·100·to·CMOS inter·
facing method to be used in either type of application.
The dynamic performance, as shown in the photograph, is
quite good. Slew rate is 18V/,..s while settling time to ±O.5%
of full scale requires less than 1.5,..s. DC performance is also
+15V
.t10%
BIPOLAR
ADJUST
U)
W
FULL
SCALE
ADJUST
t-
O
Z
'5r-~-----t-----t~
Z
>-"--.....o
OI'.(),
--{)EO
TO +10V
o
u~
:::i
IL
IL
cc
NOTE:
L 1 AND L2 ARE CD4049A FOR POSITIVE-TRUE
CODING, DC4050A FOR NEGATIVE-TRUE CODING.
Figure 6. Interfacing DAC·100 with ± 15 Volt CMOS Systems
PAGE 15-41
LOW COST THREE IC CMOS COMPATIBLE
AID CONVERTER
The diagram in Figure 7 is a modification of a previously
published application note circuit substituting CMOS logic
for TIL. All necessary logic for A to D conversion Is con·
tained in L1, a MC14559 CMOS successive approximation
register. A conversion sequence Is initiated by applying a
positive pulse, with a width greater than one clock cycle, to
the "Start Conversion" input. The analog input, applied to
Rs and converted to a current, is compared successively to
1/2 scale, then 1/4 scale, and the remaining blnarily·
decreasing bit weights until it has been resolved within
±1/2LSB. At this time, "End of Conversion" changes to a
logic "1" and the parallel answer is present in negative·true,
binary·coded format at the register outputs.
Tracking A/D's may be similarly constructed using CD4029A
up/down counters, a DAC·100, and a CMP·01 fast precision
comparator.
CONCLUSION
good since DAC·100 nonlinearity is specified over the entire
temperature range. In addition, the internal temperature·
compensated voltage reference provides minimum full scale
drift and decreases overall circuit complexity.
Precision Monolithics D/A converters may be easily incor·
porated into CMOS systems. Low current logic input stage
designs allow simple Interfacing with a minimum of exter·
nal components. The low power dissipation, high speed out·
put and low cost make this line of monolithic DACs attrac·
tive in CMOS system designs.
OPTIONAL
BIPOLAR
REFERENCE
INPUT
+6V
10kH
+6V
Voo
CLOCK
CP
INPUT
CD
01
Q2
sc
START
CONVERSION
03
Q4
FF
as
as
07
Vss
.,..
0
MSB
LSB
NEGATIVE·TRUE LOGIC OUTPUTS
Figure 7. 8·Bit CMOS Compatible Three IC Successive Approximation AID Converter
PAGE 15-42
PMI
APPLICATION NOTE 15
MINIMIZATION OF NOISE IN OPERATIONAL
AMPLIFIER APPLICATIONS
®
by Donn Soderquist
INTRODUCTION
can be found at a definite frequency. Noise effects from external sources must be reduced to insignificant levels to
realize the full performance available from a low noise op
amp.
Since operational amplifier specifications such as Input
Offset Voltage and Input Bias Current have improved
tremendously in the past few years, noise is becoming an increasingly important error consideration. To take advantage
of today's high performance op amps, an understanding of
the noise mechanisms affecting op amps is required. This
paper examines noise contributions, both internal and external to an op amp, and provides practical methods for
minimizing their effects.
EXTERNAL NOISE SOURCES
Since noise is a composite Signal, the individual sources
must be identified to minimize their effects. For example,
60Hz power line pickup is a common interference noise appearing at an op amp's output as a 16ms sine wave. In this
and most other situations, the basic tool for external noise
source frequency characterization is the oscilloscope
sweep rate setting. Recognizing the oscilloscope's potential in this area, Tektronix@ manufactures several preamplifiers with variable bandwidth and frequency which allow
quick noise source frequency identification. Another basic
identification tool is the simple low pass filter as shown in
Figure 2, where the bandpass is calculated by:
BASIC NOISE PROPERTIES
Noise, for purposes of this discussion, is defined as any
signal appearing in an op amp's output that could not have
been predicted by DC and AC input error analysis. Noise
can be random or repetitive, internally or externally
generated, current or voltage type, narrowband or wideband,
high frequency or low frequency; whatever its nature, it can
be minimized.
The first step in minimizing noise is source identification in
terms of bandwidth and location in the frequency spectrum;
some of the more common sou res are shown in Figure 1, an
11-decade frequency spectrum chart. Some preliminary
observations can be made: noise is present from DC to VHF
from sources which may be identified in terms of bandwidth
and frequency. Noise source bandwidths overlap, making
noise a composite quantity at any given frequency. Most externally caused noise is repetitive rather than random and
1Hz
I
I
1)
With such a filter, measurement bandpass can be changed
from 10Hz to 100kHz (C=4.7"F to 470pF), attenuating
higher frequency components while passing frequencies of
interest. Once identified, noise from an external source may
be minimized by the methods outlined in Table 1 - the external noise source chart.
1300kHz
RADAR PULSE REPETITION FREaUENCY . __ ~_.
I
DOMINANT REGION IIF (FLICKER) NOISE - PINK NOise
aoMI~~."'.' ~~ION O~."':"TE N91S:"~OHNSON •
SCHOTT:=-j
I
SCR SWITCHING
LARGE LOADS
MECHANICAL VIBRATION
DC TO DC
SUPPLY
POWER
SUPPLY
0.1
'iT)
EMI
FREQ
I:'NE
PICKUP
0.01
~':'~
RIPPLE 60Hz
XFMR
PRINTED CIRCUIT BOARD
CONTAMINATION
0.001
RADIO STATION
PICKUP
INVERTING
POPCORN NOISE REGION
10
I I
60 100 120
RELAY & SWITCH
ARCING
CHOPPER AMP
COMMON MaDE
CURRENTSPIKES
AT CHOPPING
FREQU~N~
180 Tk
10k
_______ L ________
TOOk
O.SSM 1M
10M
FREQUENCY IN Hz
Figure 1_ Frequency Spectrum of Noise Sources Affecting Operational Amplifier Performance
NOVEMBER 1979
©PM!1979
PAGE 15-43
...ofa
z
z
o
~
(.)
:i
Do
~
III
Table 1. External Noise Source Chart
Nature
Source
Minimization Methods
Causes
60Hz
Repetitive Interference
Powerlines physically close to op amp
Inputs. Poor CMRR at 60Hz. Power
Transformer prlmary·to·secondary capacitive coupling.
120Hz Ripple
Repetitive
Full wave rectifier ripple on op amp's
supply terminals. Inadequate ripple consideration. Poor PSRR at 120Hz.
Thorough design to minimize ripple. RC
decoupling at the op amp. Battery
power.
180Hz
Repetitive EMI
180Hz radiated from saturated 60Hz
transformers.
Physical reorientation of components.
Shielding. Battery power.
Radio Stations
Standard AM Broadcast Through FM
Antenna action anyplace in system.
Shielding. Output filtering. Limited circuit bandwidth.
Relay and Switch
Arcing
High frequency burst
at switching rate
Proximity to amplifier inputs, power
lines, compensation terminals, or nUlling terminals.
Filtering of HF components_ Shielding.
Avoidance of ground loops. Arc suppressors at switching source.
Printed Circuit
Board
Contamination
Random Low
Frequency
Dirty boards or sockets.
Thorough cleaning at time of soldering
followed by a bakeout and humidity
sealant.
Radar
Transmitters
High Frequency Gated
At Radar Pulse
Repetition Rate
Radar transmitters from long range surface search to short range navigational
- especially near airports.
Shielding.
Output filtering of frequencies > > PRR.
Mechanical
Vibration
Random < 100Hz
Loose connections, intermittent
contact in mobile equipment.
Attention to connectors and cable conditions. Shock mounting in severe
environments.
Chopper
Frequency
Noise
Common Mode Input
Current At Chopping
Frequency
Abnormally high noise chopper amplifier in system.
Balanced source resistors. Use bipolar
input op amps Instead. Use premium
low noise chopper.
12.
11.
3.Jkn
OSCILLOSCOPE
J
Reorientation of power wiring. Shielded
transformers. Single point grounding.
Battery power.
~
TA
90
.
I
25 C
i
~
i
.! I
.: I
~
~ 8.
I
70
Figure 2. Noise Frequency Analysis RC Low Pass Filter
~
lllilI
100 : - OP·07C
4.7,1.1F TO 470pF
10Hz TO 100kHz
~ II i1;11. ~
I ~~I~~I
80
.
11
~li
50
0.1
1.0
10
100
1000
10,000
FREQUENCY (Hz)
POWER SUPPLY RIPPLE
Power supply ripple at 120Hz is not usually thought of as a
noise, but it should be. In an actual op amp application, it is
quite possible to have a 120Hz noise component that is
equal in magnitude to all other noise sources combined,
and, for this reason, it deserves a special discussion.
To be negligible, 120Hz ripple noise should be between 10nV
and 100nV referred to the input of an op amp_ Achieving
these low levels requires consideration of three factors: the
op amp's 120Hz power supply rejection ratio (PSRR), the
regulator's ripple rejection ratio, and finally, the regulator's
input capacitor size_
PSRR at 120Hz for a given op amp may be found in the
manufacturer's data sheet curves of PSRR versus frequency
as shown in Figure 3_ For the amplifier shown, 120Hz PSRR
is about 74dB, and to attain a goal of 100nV referred to the
input, ripple at the power terminals must be less than
0_5mV. Today's Ie regulators provide about 60dB of ripple
Figure 3_ PSRR vs Frequency (OP-07, OP·07C)
rejection; in this case the regulator input capacitor must be
made large enough to limit input ripple to 0.5V.
Externally-compensated low noise op amps can provide improved 120Hz PSRR in high closed-loop gain configurations.
The PSRR versus frequency curves of such an op amp are
shown in Figure 4. When compensated for a closed-loop
gain of 1000, 120Hz PSRR is 115dB. PSRR is still excellent at
much higher frequencies allowing low ripple-noise operation in exceptionally severe environments.
POWER SUPPLY DECOUPLING
Usually, 120Hz ripple is not the only power supply associated noise. Series regulator outputs typically contain at
PAGE 15-44
OPERATIONAL AMPLIFIER INTERNAL NOISE
OP AMP NOISE SPECIFICATIONS
Most completely specified low noise op amp data sheets
specify current and voltage noises in a 1Hz bandwidth and
low frequency noise over a range of O.1Hz to 10Hz. To
minimize total noise, a knowledge of the deviation of these
specifications is useful. In this section, the reader is pro·
vided with an explanation of basic op amp·associated ran·
dom noise mechanisms and introduced to a simplified
method for calculating total input·referred noise in typical
applications.
1.0
10
RANDOM NOISE CHARACTERISTICS
100
FREQUENCY (kHz)
Figure 4. PSRR vs Frequency (OP·06)
least 150,N of noise in the 100Hz to 10kHz range; switching
types contain even more. Unpredictable amounts of induced
noise can also be present on power leads from many
sources. Since high frequency PSRR decreases at 20dBI
decade, these higher frequency supply noise components
must not be allowed to reach the op amp's power terminals.
RC decoupling, as shown in Figure 5, will adequately filter
most wideband noise. Some caution must be exercised with
this type of decoupling, as load current changes will
modulate the voltage at the op amp's supply pins.
v+
Op amp·assoclated noise currents and voltages are ran·
dom. They are aperiodic and uncorrelated to each other and
have Gaussian amplitude distributions, the highest noise
amplitudes having the lowest probability. Gaussian ampli·
tude distribution allows random noises to be expressed as
rms quantities; multiplying a Gaussian rms quantity by six
results in a peak·to·peak value that will not be exceeded
99.73% of the time (this is a handy rule·of·thumb for noise
calculations).
The two basic types of op amp·associated noises are white
noise and flicker noise (lIf). White noise contains equal
amounts of power in each Hertz of bandwidth. Flicker noise
is different in that it contains equal amounts of power in
each decade of bandwidth. This is best illustrated by spec·
tral noise density plots such as in Figures 6 and 7. Above a
certain corner frequency, white noise dominates; below that
frequency flicker (1/f) noise is dominant. Low noise corner
frequencies distinquish low noise op amps from general
purpose devices.
SPECTRAL NOISE DENSITY
To utilize Figures 6 and 7, let us consider the definition of
spectral noise density: the square root of the rate of change
of mean·square noise voltage (or current) with frequency
(Equation 2).
2A.
3A.
e 2= ....Q. (E )2
n
df n
En=
~/fHen2df
2B.
in2=
3B.
In =
.! (In)2
df
J
fL f fH i n2 df
Figure 5. RC Decoupling
POWER SUPPLY REGULATION
Any change in power supply voltage will have a resultant ef·
fect referred to an op amp's inputs. For the op amp of Figure
3, PSRR at DC is 110dB (3p.VN) which may be considered as
a potential low frequency noise source. Power supplies for
low noise op amp applications should, therefore, be both
low in ripple and well·regulated. Inadequate supply regula·
tion is often mistaken to be low frequency op amp noise.
When noise from external sources has been effectively
minimized, further improvements in low noise performance
are obtained by specifying the right op amp and through
careful selection and application of the associated com·
ponents.
1.0
10
FREQUENCY (Hz)
Figure 6. OP'()6 Noise Voltage
PAGE 15-45
100
1000
11)
'7
Z
C
f/)
w
I-
o
Z
z
o
~u
::::i
II.
II.
C
II
12.
EN (fH-fLl = enJfeeln
13.
'N(fH-fLl=inJfelln
(~)+fH-fl
(t)
+fH-fl
Where: en
= White nOise voltage in a 1Hz bandwidth
in
= White noise current In a 1Hz bandwidth
foe = Voltage noise corner frequency
fol
0.01
0.10
1.0
10
FREQUENCV 1Hz)
,.0
fH
= Current noise corner frequency
= Upper frequency limit
fl
= Lower frequency limit
The two most important Internally generated noise mlniml·
zation rules are derived from Equation 12 and 13: limit the
circuit bandwidth and use operational amplifiers with low
corner frequencies.
1000
Figure 7. OP·06 Noise Current
= Spectral noise density
NOISE SUMMATION
= Total rms noise
= Upper frequency limit
= Lower frequency limit
Conversely, the rms noise value within a given frequency
band is the square root of the definite integral of the spec·
tral noise density over that frequency band (Equation 3).
This means that three things must be known to evaluate
total voltage noise (En) or current noise (In): f H; fl' and a
knowledge of noise behavior over frequency.
In the spectral density discussion, the concepts of white
noise and flicker noise were introduced. In Figure 8, the
complete input-referred op amp noise model, internal white
and flicker noise sources are combined into three
equivalent input noise generators, EN, INl and IN2. The noise
current generators produce noise voltage drops across their
respective source resistors, RSl and RS2. The source
resistors themselves generate thermal noise voltages, En,
and E12. Total rms input·referred voltage noise, over a given
bandwidth, is the square root of the sum of the squares of
the five noise voltage sources over that bandwidth.
WHITE NOISE
14.ENr{fH - fLl =
Where: en, in
En> In
fH
fL
White noise sources are defined to have a noise content
that is equal in each Hertz of bandwidth, and Equation 3
may be rewritten for white noise sources as:
En (w) = en..J1H-1L
5. In (w) = in ~
It is therefore convenient to express spectral noise density
in V/..{Hz or AI...{Hi where fH - fl = 1Hz. When fH~10fl'
the white noise expressions may be further reduced to:
4.
6.
En (w) = en..;t;:;
7.
In (w) = in..;t;:;
FLICKER NOISE
Since flicker noise content Is equal in each decade of band·
width, total flicker noise may be calculated if noise In one
decade is known. The 0.1 Hz to 1Hz decade noise content (K)
Is widely used for this purpose because the white noise con·
tribution below 10Hz Is usually negligible.
8.
En (f) :; Kif
9.
..J EN2 + (IN1,Rsl )2 + (I N2,RS2)2 + Et1 2 + EI22
Minimization of total noise requires an understanding of the
mechanisms involved In each of the five generators. First,
the white noise mechanisms, thermal and shot, are dis·
cussed, followed by the low frequency noise mechanisms,
flicker and popcorn.
THERMAL NOISE
Thermal (Johnson) noise is a white noise voltage generated
by random movement of thermally·charged carriers in a
resistance; in op amp circuits this is the type of noise pro·
duced by the source resistances In series with each Input.
Its rms value over a given bandwidth is calculated by:
15.
EI =
..J 4kTR (fH
- fLl
In (f) KJf
When substituted in Equation 3, the expressions may be
rewritten to:
10.
En(f) = KJln
~
11.
'n(f) = KJln
~
FLICKER NOISE AND WHITE NOISE
When corner frequencies are known, simplified expressions
for total voltage and current noise (EN and 'N) may be
written:
Figure 8. Op Amp Noise Model
PAGE 15-46
Where: k
= Boltzmann's constant =1.38 x
10 -23joules/oK
T
= Absolute temperature, °Kelvin
= Aesistance in ohms
= Upper frequency limit in Hertz
= Lower frequency limit In Hertz
A
fH
OP-07. This device demonstrates proper attention to low
noise circuit design and wafer processing and achieves a
remarkable 0.35!,V peak-to-peak Input voltage noise in the
0.1Hz to 10Hz bandwidth.
fL
At room temperature Equation 15 simplifies to:
16.
Et = 1.28 x 10- 10
,j A (fH -
fLl
To minimize thermal noise (Et1 and Et 2) from ASI and AS2,
large source resistors and excessive system bandwidth
should be avoided.
Thermal noise is also generated inside the op amp, prin·
cipally from rbb" the base·spreading resistances in the input
stage transistors. These noises are included in EN, the total
equivalent input voltage noise generator.
0.Q1
0.10
SHOT NOISE
Shot noise (Schottky noise) is a white noise current associated with the fact that current flow is actually a movement
of discrete charged particles (electrons). In Figure 8, INI and
IN2' above the 1/f frequency, are shot noise currents which
are related to the amplifier's DC input bias currents:
17.
ISh =
Where: ISh
q
1.0
,.
100
1000
FREQUENCY (Hz)
,j 2qlBIAs (fH -
Figure 9. Noise Voltage Comparison
fLl
= AMS shot noise value in amps
= Charge of an electron = 1.59 x 10- 19
IBIAS = Bias current in amps
fH
fL
= Upper frequency limit in Hertz
= Lower frequency limit In Hertz
At room temperature Equation 17 simplifies to:
18.
Ish = 5.64
X
10- 10 ,j IBIAS (fH - fLl
Figure 10. OP·07 Low Frequency Noise
Shot noise currents also flow In the input stage emitter
dynamic resistances (re), producing input noise voltages.
These voltages, along with the rbb' thermal noise, make up
the white noise portion of EN, the total equivalent input
noise voltage generator.
'00"
3.3kn
OUTPUT
'DOn
FLICKER NOISE
In limited bandwidth applications, flicker (1/f) noise is the
most critical noise source. An op amp designer minimizes
flicker noise by keeping current noise components in the input and second stages from contributing to input voltage
noise. Equation 19 illustrates this relationship:
in second stage
19.
g
m first stage
=
2.5Mn
("'10Hz FIL TERI
INPUT REFERENCE NOISE =
25~O = '5~60W
.
2oonV/em
Figure 11. Low Frequency Noise Test Circuit
en input
POPCORN NOISE
Another critical factor is corner frequency. For minimum
noise the current and voltage noise corner frequencies must
be low; this is crucial. As shown in Figure 9, low noise corner frequencies distinquish low noise op amps from ordinary industry-standard 741 types.
The photograph in Figure 10, taken using the test circuit of
Figure 11, illustrates the flicker noise performance of the
Popcorn noise (burst noise) is a momentary change in Input
bias current usually occurring below 100Hz, and is caused
by imperfect semiconductor surface conditions incurred
during wafer processing. Precision Monolithics minimizes
this problem through careful surface treatment, general
cleanliness, and a special three-step process known as "Triple Passivation."
PAGE 15-47
II
TOTAL NOISE CALCULATION
To begin the process, a specially treated thermal silicon
dioxide layer is grown. This protects the junctions and also
attracts any residual ionic impurities to the top surface of
the oxide, where they are held fixed. Next, a layer of silicon
nitride is applied to prevent the entry of any potential contamination or impurities. The third step is the thick glass
overcoat which leaves only the bonding pads exposed. A
cutaway view of a finished device is shown in Figure 12.
With data sheet curves and specifications, and a knowledge
of source resistance values, total input-referred noise may
be calculated for a given application. To illustrate the
method, noise information from the Precision Monolithics
OP-07 data sheet is reproduced in Figure 13. The first step is
to determine the current and voltage noise corner frequencies so that the EN and IN terms of Equation 14 may be
calculated using Equation 12 and 13.
CORNER FREQUENCY DETERMINATION
EMITTER
In the input spot noise versus frequency curves of Figure 13,
it may be seen that voltage noise (Rs = 0) begins to rise at
about 10Hz. Lines projected from the horizontal (white
noise) portion and sloped (flicker noise) portion intersect at
6Hz, the voltage noise corner frequency (fee). In the center
curve, excluding thermal noise from the source resistance,
COLLECTOR
BASE
Figure 12. Triple Passivated™ Integrated Circuit Process
Op amp manufacturers face a difficult decision in dealing
with popcorn noise. Through careful low noise processing,
it can be eliminated from almost all devices; alternatively,
the processing may be relaxed, and finished devices must
be individually tested for this parameter. Special noise
testing takes valuable labor time, adds significant amounts
to manufacturing cost, and ultimately increases the price a
customer has to pay. At Precision Monolithics the low noise
process alternative is used to manufacture high volumes of
cost-effective low noise op amps.
ELECTRICAL CHARACTERISTICS at Vs = ±15V and TA
1.0 L..l..J.....J.llC.'-Ll..L..Wi.l:-L..l."!""'u::'
1.0
FREQUENCY (Hz)
Figure 13A. Input Spot Noise Voltage vs Frequency
= 25°C, unless otherwise noted.
OP·07A
PARAMETER
SYMBOL
CONDITIONS
Input Noise Voltage
e np _p
Input Noise
Voltage Density
Input Noise Current
OP·07
TYP
MAX
TYP
MAX
O.IHz to 10Hz
0.35
0.6
0.35
0.6
"Vp.p
en
= 10Hz
10 = 100Hz
fo = 1000Hz
10.3
10.0
9.6
18.0
13.0
11.0
10.3
10.0
9.6
18.0
13.0
11.0
nVl,jHz
MIN
fo
i np _p
O.IHz to 10Hz
Input Noise
Current Density
in
fa = 10Hz
fo = 100Hz
fo = 1000Hz
Input Offset Voltage
Long Term Input Offset
Voltage Stability
Input Offset Current
los
Input Bias Current
18
MIN
UNITS
14
30
14
30
pA p.p
0.32
0.14
0.12
0.80
0.23
0.17
0.32
0.14
0.12
0.80
0.23
0.17
pAI,jHz
Vas
10
25
30
75
"V
Vos/Time
0.2
1.0
0.2
1.0
"VIMo
0.3
2.0
0.4
2.8
nA
±O.7
±2.0
±1.0
±3.0
nA
INPUT NOISE VOLTAGE (enp..,)
INPUT NOISE CURRENT (Inp..,)
The peak-to-peak noise voltage in a specified frequency band.
The peak-to-peak noise current in a specified frequency band.
INPUT NOISE VOLTAGE DENSITY (en)
INPUT NOISE CURRENT DENSITY (in)
The rrns noise voltage in a 1 Hz band surrounding a specified value of frequency_
The rms noise current in a 1Hz band surrounding a specified value of frequency.
Figure 13B. OP·07 Ultra· Low Offset Voltage Op·Amp
PAGE 15·48
current noise multiplied by 200kO is plotted as a voltage
noise. Lines projected from the horizontal portion and
sloped portions intersect at 60Hz, the current noise corner
frequency (fei ).
= 0.12pA
Equations 12 and 13 also require en and in for calculation of
EN and IN. To find en and In, use the data sheet specification
a decade or more above the respective corner frequencies;
in this case en is 9.6nV/..jHz (1000Hz), and in is 0.12pAJ..j""AZ
(1000Hz).
BANDWIDTH OF INTEREST
To be summed correctly, each of the five noise quantities
must be expressed over the same bandwidth, fH - fL' At
this time, assume fH to be the highest frequency component that must be amplified without distortion. Note that
em in, corner frequencies and bandwidth are independent
of actual circuit component values. When doing noise
calculations for a large number of circuits using the same
op amp, these numbers only have to be calculated once.
100Hz
J60 In o:ooo:iHZ
+ 100 -
0.0001
= 3.66pArms
and:
IN1 oRs1 = 3.66pA (9000) = 0.00331'Vrms
IN2 oRs2 = 3.66pA (10kO) = O.0366I'Vrms
Finally, EN from Equation 12:
= 9.6nV
J6 In
o.b~~~z
+ 100 -
0.0001
= 0.130I'Vrms
Substituting in Equation 14:
TYPICAL APPLICATION EXAMPLE
Figure 14A shows a typical X10 gain stage with a 10kO
source resistance. In Figure 148, the circuit is redrawn to
show five noise voltage sources. To evaluate total inputreferred noise, the values of each of the five sources must
be determined.
R2
Ok!l
>--......- - - 0 ' 0
Figure 14A. Noise Analysis Circuit
=
..J (.130I'V)2 + (.0033I'V)2 + (.0366I'V)2 + (.04I'V)2 + (.128I'V)2
= 0.191'Vrms
Total input-referred noise = 1.14,N peak-to-peak (0.0001Hz
to 100Hz).
741 CALCULATION EXAMPLE
CI)
The preceding calculation determined total noise in a given
bandwidth using a low noise op amp. To place this level of
performance into perspective, a calculation using the
industry-standard 741 op amp in the circuit of Figure 14 is
useful. Once again the starting point is corner frequency
determination, using the data sheet curves of Figure 15: fee
= 200Hz; fei = 2kHz; en == 20nVl..jHz; in = 0.5pAJ..j"HZ:
o
z
z
o
Using these corner frequencies and noise magnitudes, EN
and IN are calculated to be 11'Vrms and 83pArms respectively. Multiplying this noise current by the source
resistance gives terms 2 and 3 of Equation 14 as shown
below:
14. ENT(fH - fLl=..J EN 2 + IN12 RS12 + IN22 RS22 + E+12+ E+22
Substituting in Equation 14:
=
..J (1!'V)2+ (0.075!,V)2 + (0.83!,V)2 + (0.04!,V)2+ (0.128!,V)2
= 1.3!,Vrms
Figure 14B. Noise Analysis Equivalent Circuit
Using Equation 16: Et = ~
Et1 = 1.28 X 10- 10 ..J (9000) (100Hz) = 0.041'Vrms
Et2
= 1.28 X 10- 10 ..J (10kO)(1ooHz) = 0.1281'Vrms
Next, calculate IN using Equation 13:
Total input-referred noise = 7.8!,V peak-to-peak (0.0001 Hz to
100Hz).
This is 6.8 times that of the low noise op amp example.
The calculation examples illustrate three rules for minimizing noise in operational amplifier applications:
Rule 1. Use an op amp with low corneffrequencies.
Rule 2. Keep source resistances as low as possible.
Rule 3. Limit circuit bandwidth to signal bandwidth.
PAGE 15....9
...w
~
u
:::i
AAC
II
10-13
. ~ rt
~ '0-"
'=
w
~g
-
so
f-
f=
C-~
10-15
::!
~
120
Vs = ±15V .
TA = 25°C
1=
"
"\.
VSI="5t - -
TA" +2S"C
~
tnr=
11
~ 10-17
" 1"~
f10-16
UA 741
'0
100
1k
10k
FREQUENCY 1Hz)
lOOk
0.1
Figure 15A. Input Noise Voltage as a Function of
Frequency
1
10
100
1k
10k 100k
fREQUENCV (HzI
..
,
8.
- '0-22
H-ttI--+-++++-+-+Itt--+ -Y-r---I
i3
10-23
H-+fl"d-++t+-+-+t-t+--+--H+--i
w 10-24
H-ttI---+-+m~,.c:~:+Itt--+++-+t---I
I
I
a
~ '0-25
~~~=f::ffi:~-+
~
tJ
60
'"
"'
.
f5
20
;;
§
~
~
UA 741
-20
,.-26 L....!..llJ--L-L.LU.-L-l..ll.!..-l.....J..J.J.J....J
,.
'00
1k
10k
fREQUENCY 1Hz)
10M
L,..ITA" 25 C
~
~
~
H+H---t-++t+-+-+t-t+--+--H-+t---i
~
1M
Figure 16A. Open Loop Frequency Response
Vs'" ±15V
TA = 2S"C
~
1\
,.
'00
lk
10k
lOOk
fREQUENCY 1Hz)
lOOk
Figure 15B. Input Noise Current as a Function of Frequency
1\
'M
'OM
Figure 168. Closed Loop Response for Various Gain
Configurations
,.""
BANDWIDTH
,....
Effective circuit bandwidth must not be much greater than
signal bandwidth or amplification of undesirable high fre·
quency noise components will occur. Throughout the
preceding calculations, an assumption of "bandwidth·of·
interest" was made, while in actual application the
amplifier's bandwidth must be considered.
In Figure 16, the OP"()7 frequency response curves show a
rolloff of 20dB/decade; integration of the area under the
curve will show the effective circuit noise bandwidth .to be
1.57 times the 3dB bandwidth. In most closed·loop gain con·
figurations, the amplifier's bandwidth may be greater than
required, and output filtering, such as in Figure 17, could be
used. As an alternate to output filtering, an integrating
capacitor may be connected across the feedback resistor.
Bandwidth may also be limited in some applications by
overcompensating an externallY'compensated low noise op
amp, such as the 888725.
"N O--'lNV-.......---1
c
fCO
=2rl1c 1_
Figure 17. Output Filtering
MISCELLANEOUS NOISE MINIMIZATION METHODS
Certain other noise mechanisms merit consideration: us.e
metal film resistors; carbon resistors exhibit "excess
noise", with both 11f and white noise content being related
PAGE 15-50
to DC applied voltage. The use of balanced source resistors,
while sometimes good for DC error purposes, will Increase
noise; the balancing resistor is not required for op amps
such as the OP-07, since 10s=le. Keep noise in its proper
perspective; minimize it without introducing additional DC
errors. Use low noise op amps with overall DC specifications that will satisfy the application.
SUMMARY
ACKNOWLEDGEMENTS
The author wishes to express his thanks to George Erdl, the
designer of the OP-06 and OP-07, for his patient technical
assistance.
NOISE BIBLIOGRAPHY
1.
The OP-07 Ultra-Low Offset Voltage Op Amp - A
Bipolar Op Amp That Challenges Choppers, Eliminates
Nulling, AN-13, D. Soderquist and G. Erdi, Precision
Monolithics Inc., Application Note 1974
2.
Noise Performance of the Precision Monolithics
SSS725 Instrumentation Operational Applifier, G. Erdi,
Precision Monolithics Inc., Application Note 1971
3.
Instrumentation Operational Amplifier with Low Noise,
Drift, Bias Current, G. Erdi, Precision Monolithics Inc.,
Application Note 1973
4.
Low Noise Electronic DeSign, C. D. Motchenbacher and
F. C. Fitchen, John Wiley and Sons, 1973
5.
Low-Frequency Noise Predicts When a Transistor Will
Fail, A. Van der Ziel and H. Tong, Electronics, 39,
November 28, 1966
6.
Bistable Noise in Operational Amplifiers, S. Hsu, IEEE
J. Solid-State Circuit SC-6, December 1971
7.
Low-Noise Transistor Amplifiers, E. Chenette, Solid
State DeSign, 5, February, 1964
A summary of the major points to consider is as follows:
1.
Minimize externally generated noise.
2.
Choose an amplifier with low 1If noise corner
requencies.
3.
Limit the circuit bandwidth to signal bandwidth.
4.
Eliminate excessive resistance in the input circuit.
CONCLUSION
Recent improvements in IC op amp DC specifications have
made noise an important error consideration. From data
sheet information and source resistance values, total input·
referred noise over a given bandwidth can be easily
calculated. Total noise can be minimized by a thorough
understanding of the various nOise-generation mechanisms.
8.
Electrical Noise, A. Bennett, McGraw-Hili, 1960
9.
Noise, A. Van der Ziel, Prentice-Hall, 1954
II
PAGE 15-51
PMI
APPLICATION NOTE 16
®
LOW-COST, HIGH-SPEED
ANALOG-TO-DIGITAL CONVERSION WITH
THE DAC-OB
By Donn Soderquist and John Schoeff
Today's fast computer and microprocessor-controlled
systems frequently require AiD converters which will complete a conversion in one cycle time.
Until now, these high speed AiD converters have been expensive and difficult to build. Most designers have therefore
chosen to purchase modular AiD converters typically ranging in price from $100 to $400. This application note
describes three less costly AiD designs, with total conversion times of 41's, 21's, and 11's. These designs are implemented with the DAC-08, a recently announced high
speed monolithic digital-to·analog converter. A discussion
of basic successive approximation is given, followed by
practical circuit designs.
SUCCESSIVE APPROXIMATION AID ADVANTAGES
Successive approximation AiD conversion is the most
popular choice in many systems today because it achieves
high conversion rates at very low cost..Other methods, such
as Tracking (Servo) or Staircase (Ramp), require up to "2n "
clock cycles per conversion, where "n" is the number of bits
of resolution, while successive approximation requires only
"n + 1" clock cycles. Finally, a deSigner can easily construct
his AiD with readily available standard ICs.
BASIC SUCCESSIVE APPROXIMATION
AID CONVERSION
A successive approximation AID converter operates by com·
paring the analog input to a series of "trial" conversions;
the first trial compares the input to the value of the most
significant bit (MSB) or half of full scale. Figure 1 shows the
progression of trials for a 3·bit converter. If the input is
greater than the MSB value, the MSB is retained and the
converter moves on to "trying" the next most significant bit,
or three·quarters full scale. If the input had been less than
the MSB, the logic would have turned the MSB off before go·
ing on to the next most significant bit, or one·quarter full
scale. This "branching" continues until each successively
smaller bit has been tried, with the entire process taking "n"
trials.
To implement the logic for the successive approximation
algorithm, a configuration similar to Figure 2 may be
employed, wherein a start command places a "one" in the
first bit of a shift register. This sets the first latch to "one"
and turns on the DAC's MSB. If the comparator output reo
mains low, the "one" will remain in the latch; if not, the latch
SUCCESSIVE APPROXIMATION REGISTER
END OF
CONVERSION
SERIAL
OUTPUT
MSB
11==t=:4=1=~
llLO~LSB
MSB
LSD
VOLTAGE OUTPUT D/A
Figure 1. Flow Diagram for 3·Bit Successive
Approximation AID Conversion
Figure 2. Successive Approximation AID Converter
PAGE 15-52
will be reset to zero before the next bit trial begins. The next
clock cycle causes the shift register to place a "one" in the
second bit, and a similar process continues until all bits
have been tried. After the last bit's trial, the end·of·conver·
sion output changes state indicating the parallel data is
ready to be used.
speed AID converter designs. The internal logic switch
design enables propagation delays of 35ns for each of the 8
bits. Settling time of the LSB to within ±1/2LSB of final
value is therefore 35ns, with each successively more signifi·
cant bit taking progressively longer. The MSB settles in
85ns; it is the dominant factor of full scale settling time.
This performance is illustrated in the scope photo of Figure
4, taken at the output of the test circuit of Figure 5.
CURRENT COMPARISON
The previous discussion indicated that the function of the
comparator was to perform a comparison between the
analog input voltage and the output voltage of the DAC.
Higher speed conversions may be achieved by using the
output of a fast current output DAC directly. This may be im·
plemented as shown in Figure 3, where the comparator ex·
amines the polarity of (V 1N - IOAcRIN)' Current comparison
eliminates the need for a current·to·voltage converting op
amp which is by far the slowest element in most DIA con·
verters.
ALL BITS SWitCHED ON
2.4V-
LOGIC
INPUT
O.4V-
LS~
OUTPUT
-1/2
SETTLING
+1/2 LSB-
5OnSEC!DIVISION
SETTLING TIME FIXTURE OF FIGURE 5.
IFS = 2mA. RL = 1kn, 1/2 LSB = 4jJA
Figure 4. Output Settling Time
co
";'
z
ce
III
W
l-
e
z
z
e
FOR TURN..()N, VL = 2.7V
FOR TURN-OFF, VL '" O.7V
VL
+5V
~u
:::i
AA-
ce
Figure 3. Current Comparison AID Input
II
DYNAMIC CONSIDERATIONS
The time required to complete an 8·bit successive approx·
imation AID conversion is determined by the length of 8
trials and their associated comparator decisions, plus one
clock cycle. To minimize these periods, three dynamic con·
siderations must be made:
1.
2.
3.
DAC output current settling time to ±112LSB.
Comparator propagation delay with the available over·
drive.
Logic propagation delay and setup time requirements.
For example, with a 500ns DAC, a 500ns comparator, and
100nsec of logic delay, each of these cycles would require
1.1j.ts. An 8·bit conversion would take nine clock periods, or
10j.ts. To design a fast AID, each of these delays must be
made as short as possible. In the next few paragraphs, prac·
tical methods of minimizing these delays are discussed.
DAC CURRENT SETTLING TIME
The DAC-08 is a low cost monolithic current output DAC
with 85ns full scale settling time and is ideal for use in high
+VREF
R15
15
I··1P'
-= +15V
-15V
TO O.U.T.
Figure 5. Settling Time Measurement
A major factor affecting settling time is the RC time con·
stant formed by the load resistance (Rd and the DAC output
capacitance (Co) plus any stray capacitance present at the
PAGE 15-53
summing node. Settling to within ± 1/2LSB at 8 bits (±0.2%
full scale) requires 6.2 RC time constants. For the DAC'()8,
the output capacitance is 1SpF; as a result the output RC
time constant is a major factor influencing settling time
when RL is greater than SOOO and dominates when RL exceeds 9000.
This situation produces difficult requirements. Optimum
DAC settling time occurs when RL ,;; SOOO, but for full scale
currents of 2mA, 1I2LSB is only 4,..A. Thus, with a 5000
equivalent resistance, the voltage at the DAC output corresponding to 1/2LSB is only 2mV and is inadquate for high
speed operation of many comparators. For this reason, RL is
usually la~ger than SOOO, which is a necessary compromise
between DAC settling time and comparator input overdrive
requirements.
available upon request.) A 1,.s AID requires special logic
design using Schottky TTL and will be described in the
detailed circuit description.
PRACTICAL 3 IC AIDs
When the required conversion time is ;;,:2,.s, the DAC-08's
fast settling time enables very simple and low cost designs.
A 4pS design is shown in Figure 7. At additional cost and increased power dissipation, changing the comparator to an
AM686 results In a 2,.s AID. Every nanosecond counts in a
1,.s AID, and the circuit necessarily increases in complexity.
However, with the DAC.()8, Schottky TTL logic, and attention
to layout, a 1,.s AID can be constructed at low cost.
COMPARATOR CONSIDERATIONS
All comparators respond fastest to large differential input
voltages (high overdrive). This phenomenon is shown in
Figure 6, a graph of response time vs input voltage for the
Precision Monolithics' CMP-01. This low cost comparator
provides DC characteristics compatible with 10 and 12-bit
AID converters and has adequate speed for 4pS 8-bit converters.
~
\
3
~
0.'0
~
0.06
i
~
!:
I
2
2mV
_\ .1?
\.4) 20~V-
~
\
.\.
.'-'Z
NO LOAD
VS".i16V
TA =25"C
RS = son
CONVERSION TTL CLOCK
COMPLETE
0.00
-0.05
-GO
+16V
6mV
I
~
INPUT
, 'm~_
\I
~
ANALOG
o TO +1OV
+15V
0
60
120
180
240
320
360
INPUT 2.25MHz
CONNECT "START" TO
"CONVERSION COMPLETE"
FOR CONTINUOUS CONVERSIONS.
420
OUTPUT VOLTAGE (VOLTS)
Figure 6_ Response Time For 100mV Step and
Various Input Overdrives
Figure 7_ 3 IC Low Cost AID Converter
For 2pS and 1pS deSigns, the AM686 was selected. It povides
12ns propagation with 2.SmV overdrive, Schottky TTL outputs, and DC input specifications adequate for an 8-bit AID.
Ultra-high speed requires considerable power. Maximum
supply currents are 42mA from the +SV supply and 34mA
from the -SV supply.
LOGIC CONSIDERATIONS
A single DIP package, the AM2S02 Successive Approximation Register, contains the logic for 8-bit AID converters
operating at 2,.s or greater conversion times. (Detailed
descriptions of AIDs constructed with the AM2S02 and
Precision Monolithics DACs are contained in AN-11,
ANALOG DESIGN
The DAC-08AQ is useful in this design for several reasons.
Its output full scale current Is guaranteed to be 1.992mA
±8,..A, when a 10.00DV reference is connected to a S.OOOkll
resistor in series with Pin 14. In this deSign, the Skll is split
to allow bypassing without capacitively loading the 10 volt
source. For slightly higher speed, the total resistance may
be reduced to 2.Skll, thereby increasing 10 full scale to
3.984mA, allowing a lower sum node resistance and lower
RC time constant. (The DAC itself does not settle faster at
4mA full scale current.) The DAC-08A maximum nonlinearity
of ±0.1% full scale enables faster settling time to within
±1/2LSB (±0.2% full scale) for each bit trial than would be
the case using a DAC with ±0.2% nonlinearity. USing the
PAGE 15-54
~
c::
+5V
+15V
iil
!»
~
I
+10V REFERENCE
REF-Ol
~
!n"
:~
~
II"
III
::;
~+5V
N.C.
i
~
c
:1:1
......
L...-...-.,
m
L-
:i:
6D 6D -
USEe AS
PUlLUP
NOTES: 1.
2.
3.
4.
5.
5C6A-
6.
7.
8.
1, 2, 3, 4, 7.8. SN74S74N
5.6. SN74S175N
9 SN74S00N
10 SN74S04N
11 SN74S3ON
A 1 DAC-08AQ
A2 AM 6B6HC
·OPTIONAL BYPASS
CAPACITORS
9.
OPTIONAL SUM NODE
BIASING RESISTOR
STROBE
PROVIDES +1/2 lSB (4pA)
APPLICATION NOTES
AN-16
± 0.2% nonlinearity OAC.()8 or OAC·08E provides cost sav·
ings at an overall increase In conversion time. Both true and
complementary current outputs are provided, and their sum·
matlon Is always Ilull scale. In this design, 10 is connected to
the analog input. Since 10 + 10 is constant, and 10 flows in
R3, the DC input current Is constant. Holding the AID input
current constant reduces buffer amplifier output impedance
requirements. The buffer amplifier used in this application
must have sufficient bandwidth to hold VIN constant during
a 1,.,s AID conversion.
CALIBRATION AND ACCURACY
In many applications calibration is not required. With a
10.000V reference and ±0.05% tolerance resistors, the
worst case full scale error is ±0.15%. The zero scale error is
totally dependent upon comparator input offset voltage and
input bias current, and, in most cases, it may be tolerated. If
the errors are not tolerable, then the following calibration
procedure may be used.
Calibration of the AID is done first at zero scale, then at full
scale. The zero transition is set by R4, a resistor connected
to the + 10 volt reference. For 10V full scale, the desired
transition point between a code of 0000 0000 and 0000 0001
is at +20mV (+ 1/2LSB). With an ideal comparator, R4 would
be 2.56mO (10 volts/3.9~). Since comparators are less than
ideal, R4 must also cancel out the comparator's input offset
errors. With +20mV applied at the analog input and using a
low clock rate, select R4 to cause th.e output code to fluc·
tuate between 00000000 and 0000 0001. (Do notinstall a pot
for R2 or R4 since it will increase capacitance and induct·
ance at the sum node.) Full scale is calibrated by applying
+9.940V to the analog input and trimming R2 until the out·
put code fluctuates between 1111 1110 and 11111111. Alter·
natively, the reference voltage source may be adjusted for
the same effect. This will be a small adjustment due to the
OAC·08A's tight output full scale current relationship with
the reference voltage. Once calibrated, accuracy is a func·
tion of temperature·induced drifts only.
flip·flops do nothing, because they are not clocked. Bit 1's
answer is now latched, and Bit 2, 1/4 full scale, is being
tried. The process continues with the shift register causing
each bit to be tried from Bit 2 to Bit 8. After the Bit 8 decl·
sion, the EOC output goes high, indicating that the answer
in parallel format is available at the 8-bit outputs.
OUTPUT INTERFACING
In continuous conversion operation, the most common con·
nection, EOC is connected to the Start input. While the
answer is available whenever EOC is high, it is convenient
to use the positive-going edge of the Strobe output as a
clock for two 74S175 quad "0" flip·flops used as an 8-bit
storage latch. Since Strobe goes high before another con·
version cycle begins, there is ample setup time for the latch;
the answer has been steady for over 35ns.
OVERALL DESIGN
Due to the bit settling time range of the OAC·08 from 85ns
for Bit 1 to 35ns for Bit 8, progressively decreasing trial·and·
decision periods would be ideal. Practically, such a timing
sequence is difficult to generate at low cost, so a com·
promise was made: The first four bits allow 160ns for each
trial·and·decision, while the last four bits allow 80ns. This
may be seen in the waveforms of Figure 9. The timing sequence is generated by shifting a "one" through two shift
registers with in·phase clocks, one at 6.5mHz derived from
the other at 13mHz.
Standard 74 Schottky TTL logic was selected for speed,
compatibility with the AM686 comparator, ready availability,
and price.
13 MH:i
INPUT
,77nSEC
cP,
A TYPICAL CONVERSION CYCLE
CPZ
A conversion is initiated by a high level at the Start input
when the input 13mHz clock makes a low to high transition.
Approximately 9ns later, the control logic generates a clear
and reset pulse (Strobe) which causes several events: the8
output flip·flops are cleared except for the MSB flip·flop 1
which is set to a "one"; both shift registers are cleared; the
OAC has Bit 1 turned on, all others are off. The conditions
for the first trial at half scale are now established.
BIT 2
.....,.._-+____-1~....- - - - -
BIT4 .....
"l......C'---+_-'-__-+': _---;r=;:,~---80nSEC
BIT ' ' ' '
"--_-+____-;-'-'-_ _
BIT 6 ...
"'
As the DAC output settles, the comparator continuously ex·
amlnes the polarity at its noninverting input. For this case,
with zero volts at the analog input, the comparator finds a
negative voltage present; its output therefore is low. This
I.ow is applied to the "0" inputs of all 8 output flip·flops.
Recall that 74S74 flip·flop outputs won't change until they
are clocked by a positive transition at their CP inputs. At the
time labeled 1 on the CP1 waveform, the reset and clear
pulse, Strobe, returns high.
Shift Register Number 1 waits for a positive·going transition
of CP2. At 2 time CP2 goes high, transferring a "one" from
9A·Q to 9B·Q; 9B·Q goes low, setting 2·Q high and clocking
the comparator's "zero" into the Bit 1 flip-flop. The other six
~
l......C_-+____-+,.-'-____ r - ' L -
BIT7 "...
!L
BITSR
~ROBE~r-~----+--------~
~Ocl...._ _+_----r_------~r
STROBE
....rtL.--t,-----+--------
~-ij~-----+-------9D.Q _ _ _ _ _ _ _ _
_____
-"r---.~
'OA-D
....______
-o4-_ _ _ _ _ _ _ _ _ _~ro
Figure 9. Timing Waveforms with Zero Volts Input
PAGE 15-56
A useful characteristic of the OAC-08 is its capability to
directly Interface with all popular logic families including
TTL, CMOS, and ECL. For this design the OAC-08's logic
control pin (Pin 1) is grounded to provide the proper TTL
logic threshold. A design utilizing ECL could provide slightly faster conversion time at increased power consumption.
LOGIC DESIGN
The primary logic design element is the 74S series positiveedge-triggered "0" flip-flop. This type of flip-flop is useful in
AID designs because of several properties:
1.
The propagation delay from Set to Q going high is only
3ns.
2.
The information on the 0 input is transferred to the Q
output only at a positive-going edge of CPo
3.
Changes at the 0 input (comparator settling changes)
are ignored when CP Is In a steady state.
74S74 dual "0" flip-flops are used for the 8 output latches
and for the control logic, and 745175 quad "0" flip-flops are
used for the two shift registers.
Flip-flops 2 through 8 in the simplified schematic (Figure 10)
perform two functions. Typical operation can be understood
by examining the operation of Flip-Flop 2. When set by an
input from Shift Register Number 1, the Q output of FlipFlop Number 2 goes high, which starts the trial of Bit 2 and
acts as a clock which is the result of Trial 1, to Q of Flip-Flop
1. This basic connection, using the beginning of a new trial
to clock the previous bit trial, is used on all eight output flipflops. The start of each bit trial is precisely coincident with
clocking of the previous bit answer; so no time is wasted,
and logic delays are reduced to setup times only.
~
MSB
Z
-5V
""
III
W
....
0
z
Z
0
'~
CJ
LSB
::::i
A.
A.
""
II
CLEAR
AND
RESET
ISTROBE)
CP2 GATED
1-......- - 0 6.5MHz
CLOCK
Figure 10. Simplified Schematic 1,..s AID
PAGE 15-57
PRINTED CIRCUIT BOARD LAYOUT RULES
6.
For AID designs generally, and high speed designs in par·
ticular, layout Is Important. Some of the more important
rules are listed below:
The comparator's outputs should be routed away from
its Inputs, to minimize capacitive coupling and possible
oscillation.
SYSTEM CONSIDERATIONS
1.
Digital ground must be separated from analog ground;
they must meet at only one common point.
2.
Digital traces should not cross or be routed near sensi·
tive analog areas; this is especially Important near the
sum node.
3.
With Schottky TIL logic, the digital ground and Vee
traces should be large and contain provisions for
generous bypassing.
4.
The trace from the DAC output to comparator input(sum node) should be short, and it should be guarded by
analog ground.
5.
All analog components should be located as close as
possible to the edge connector so that the input analog
traces will be short.
Typical system connections ar shown in Figure 11. Digital
grounds and analog grounds meet at one pOint only keeping
large power supply return currents away from the sensitive
analog ground portion of the AID system. Start is connected
to EOC for continuous conversions, and Strobe Is used to
clock the parallel answer into an output register at the end
of each conversion.
CONCLUSION
The DAC·08 High Speed Monolithic D/A Converter greatly
simplifies construction of high speed AID converters.
Designs using only three ICs achieve 2pS conversions, and
1pS conversion can be attained with additional logic.
Techniques have been presented which allow the user to
construct low cost, high speed AID converters.
13MHz
CLOCK 0 - - CLOCK
INPUT
~
g
lQ
10
2Q
c:
CP
lD
2D
3D
4D
30
BIT
BIT
BIT
BIT
4Q
BIT 6
20
3Q
148175
0....- .a
,--
GNO-
r--
~
~
~
lQ
111
2Q
CP - r 1020
20 748175
3Q
4Q
3Q
~
-15V
START
EOC
STROBE
BIT 1
2
3
4
5
~~,OG
+ ANALOG
INPUT
ali~b~\',
JUMPER I
POWER
GROUND
I
BIT 7
BIT 8
-6V
REFERENCE IN
+ 10.oDOV
REFERENCE-
- - - 0 -REF·..()1
1pSEC AID
aQ
+5V
4Q
4Q
GND
OUTPUT REGISTER
(OPTIONAL)
AID CONVERTER
Figure 11. Typical System Connection
PAGE 15-58
FORCING
FUNCTIONS
APPLICATION NOTE 17
PMI
OAC-OB APPLICATIONS COLLECTION
By John Schoeff and Donn Soderquist
GENERAL DESCRIPTION
3. Analog meter movement driving.
There has been a trend in recent years toward providing
totally dedicated digital;to-analog converters with limited
applications versatility. This application note describes a
new type of monolithic DAC designed for an extremely
broad range of applications, the Precision Monolithics
DAC-OS.
4. Resistive termination for a voltage output without an op
amp.
Several unique design features of this low-cost DAC combine to provide total applications flexibility. Principal
among them are: dual complementary, true current outputs; universal logic inputs capable of interfacing with any
logic family; 85ns settling time; high-speed multiplying
capability; and finally, the ability to use any standard
system power supply voltages. A description of these
features is given followed by specific applications using
each feature.
• CMOS, TTL. DTL, HTL, Eel, PMOS
COMPATIBLE 2JJA LOGIC INPUTS
5. Capacitive termination for digitally-controlled
tegrators.
in-
6. Inductive termination with balanced transformers,
transducers and headsets.
• 86NSEC SETTLING
TIME TO ~lI2LSB
Bl B2 B3 B4 B5 B6 B7 B8 10 mA 10 mA
EO
EO
FULL SCALE -ILSB 1 1 1 1 1 1 1 1
1.992
0.000
-9.960
0.000
FULL SCALE -2LSB 1 1 1 1 1 1 1 0
1.984
0.008
-9.920 - 0.40
HALF SCALE +LSB
1.008
0.984
-5.040
-4.920
81 B2 B3 B4 B5 B6 87 88
-
IREF
• HIGH SPEED
MUL TIPL VING
REFERENCE
INPUT
• DUAL
COMPLEMENTARY
OUTPUTS WITH
-lOV TO +18V
1 0 0 0 0 0 0 1
HALF SCALE
1 0 0 0 0 0 0 0
1.000
0.992
-5.000
-4.960
HALF SCALE -LSB
0 1 1 1 1 1 1 1
0.992
1.000
-4.960
-5.000
ZERO SCALE +LSB
0 0 0 0 0 0 0 1
0.008
1.984
-0.040
-9.920
ZERO SCALE
o
0.000
1.992
0.000
-9.960
0 0 0 0 0 0 0
VOLTAGE
• EXTERNAL
COMPENSATION
FOR MAXIMUM
BANDWIDTH
• ADJUSTABLE lOGIC
INPUT THRESHOLD
VTH = VLC + 1.4V
Figure 2_ Basic Unipolar Negative Operation
Figure 1. The Flexible D/A Converter
+28.0
OUTPUT
+20.0
+24.0
~
+1&.0
HIGH VOLTAGE COMPLIANCE CURRENT OUTPUTS
~
Many older current-output DACs actually have resistive
outputs which must be terminated in a virtual ground. The
DAC-08, however, is a true digitally·controlled current
source with an output impedance typically exceeding
20MO.
g
+12.0 t--IHADID AREA I~DtCATES PER· _
• • •ILE OUTPUT VOLTAGE
+8.0
RANGE FOR V- • -1IV, IREF '" -
~
§
1. Precise current transmission over long distances.
t---
+4.0
. -.
i--
FOR OTHER V- OR IREF. SEE -
~
OUTPUT CURRENT
VOLTAGE CURl/I.
va
OUTPUT -
t--
"-~
-4.0
--8.0
Its outputs can swing between -10Vand +18V with little
or no effect on full-scale current or linearity. Some of the
applications that require high output voltage compliance
include:
2_ Programmable current sources.
w
o
z
z
o
~
o
:::i
II.
II.
-c
COMPLIANCE
• ±4.5V TO ±lBV
33rnW AT ±5V
(I)
~
-12.0
+50
TEMPERATURE
+100
rei
Figure 3. Output Voltage Compliance vs
Temperature
©1979PMI
PAGE 15-58
+150
•
4-0
r:~-
ALL BITS ON
10.000kn
3.6
TA" TMIN TO TMAX
IREFI+) =
2.0~'4
2.8
V- = -15V
2.0
V- '" _6V
I
'.6
I
IREF '" 2mA
I
I
IR~F
0.4
-14 -10
-6
-2
10
OUTPUT VOLTAGE (V)
EO
B1 B2 B3 B4 B5 88 87 B8
I~'F _I'mA
'.2
:)-
OAC·OB
---..
Z4
0.8
10000kn
EO
~2
POSFULL SCALE -LSB
1
1 1
POS FULL SCALE 2LSB
1
D:2mA
14
1 1
EO
EO
1 1 1
- 9.920
+10.000
+ 9.920
-
1 1
1 1
1 1 0
- 9.B40
ZERO SCALE +LSB
1 0 0
0 0
o 0
1
- o.oBo
+ 0.1Bo
ZERO SCALE
1 0 0
0 0 0 0 0
0.000
+ 0.080
1 1 1 1 1
18
ZERO SCALE - LSB
0
1 1
+ LSB
0
0 0 0
NEG FULL SCALE
NEG FULL SCALE
Figure 4. Output Current vs Output Voltage
(Output Voltage Compliance)
0 0
+ 0.080
0.000
1
+ 9.920
- 9.B40
0 0 0 0
+10.000
- 9.920
0 0 0
0 0
Figure 5. Basic Bipolar Output Operation
5k"
81 82,83 B4 85 8687 B8
>-......--000
(REFERRED TO
LOCAL GROUND)
5k"
'eM
8182838485888788
POS FULL SCALE - LSB
1 1
1 1 1 1 1 1
+9.920
POS FULL SCALE 2LSB
1 1
1 1 1 1
+9.840
1 0
( +) ZERO SCALE
10000000
+0.040
(-) ZERO SCALE
o
-0.040
1 1
1 1 1 1 1
NEG FULL SCALE +2LSB
00000001
-9.840
NEG FULL SCALE +1LSB
00000000
-9.920
Figure 6. High Noise Immunity Current to Voltage Conversion
DUAL COMPLEMENTARY OUTPUTS
Convertional DACs have a single output, so they cannot
drive balanced loads and are limited to a single input code
polarity. The DAC·OB was designed to overcome these
limitations.
OmA -
Input coding of positive binary or complementary binary is
obtained by a choice of outputs, 10 for positive·true or 10 for
negative·true. In many applications both are used either in·
dependently or in combination. Dual comlementary outputs
allow some very unusual and useful DAC applications:
1.0mA-
2.0mA -
1. CRT display driving without transformers.
2. Differential transducer control systems.
(000010000)
3. Differential line driving.
(1111 1'111)
4. High-speed waveform generation.
5. Digitally controlled offset nulling of op amps.
Figure 7. True and Complementary Output Operation
PAGE 15·60
+1ZOVDC
L-------r--:.~F~U:LL:O~,~FF~E~R~EN~TIAL DRIVE LOWERS POWER ~SU~P;PL~Y~V~O~L;TA~G~E---''''''------.J
• ELIMINATES INVERTING AMPLIFIERS AND TRANSFORMERS
• INDEPENDENT BEAM CENTERING CONTROLS
Figure 8. CRT Display Driver
V+
•
•
•
•
•
L~ 1
til
W
FULLY DIFFERENTIAL INPUT
ELIMINATES INSTRUMENTATION AMPLIfiER - LOW COST
DIGITALLY CONTROLLED SYSTEM ZEROING
HIGH CONVERSION SPEED
EXCELLENT COMMON MODE REJECTION
l-
e
z
z
e
~
V
TRANSDUCER
STRAIN
PRESSURE
TEMPERATURE
::::i
L~
II.
II.
LV
OP-03
10
10
••
OAe-os
,-10
)~
DAe-OB
~
+
11.111111
SERIAL TO
PARAllEL
REGISTER
I
NULL
CONTROL
t-----o SERIAL
INPUT
•
c(
SUCCESSIVE
APPROXIMATION
REGISTER
t-
CLOCK 0 - INPUT
I
PARAllEL OUTPUT
Figure 9. Bridge Transducer Control System with Full Differential Input
PAGE 15-61
SERIAL
OUTPUT
FOR TURN.QN. VL = 2_7V
Fa" TURN-OFF. VL" D.7V
DIGITAL INPUTS
B1 B2 83 B4 85 B6 87 88
VL
..v
256nA
VREF-----
+15V -15V
•
•
•
•
DAC OUTPUT IN 1nA PER STEP
REPLACES NULLING POTENTIOMETER
WORKS WITH OP-07. OP-05, SSS725
Vos NULLED BELOW NOISE LEVEL
RREF
+VREF
R15
Figure 10. Digitally Controlled Offset Nulling
-15V
TO O.U.T.
VReF
Figure 12. Settling Time Measurement Circuit
DIGITAL INPUT
B1 B2 B3 B4 85 86 B7 B8
ALL BITS SWITCHED ON
EIN
2.4V LOGIC
INPUT
D.4V •
•
•
•
•
BIPOLAR OUTPUT WITH OFFSET BINARY CODING
PROVIDES DC ISOLATION BETWEEN SOURCE AND LOAD
HIGH VOLTAGE OUTPUT CAPABILITY
USEFUL WITH PULSE OR SINE WAVE REFERENCE INPUT
USEFUL WITH PULSE OR SINE FUNCTION DIGITAL INPUT
-1I2LSB OUTPUT
SETTLING
0+lI2LSB -
Figure 11. Balanced Transformer Drive
&OnSEClDlVISION
IFS· 2mA. RL· lW
1/2LSB = 4,JA
HIGH SPEED
Figure 13. Full Scale Settling Time
Sub-microsecond settling times are common In current·
output DACs. Many DACs settle in 500ns; 300ns is not
unusual. But 85ns settling time for a low·cost DAC is excep·
tional, and this characteristic allows the use of the DAC·08
in formerly difficult and expensive·to·build applications:
1. 1,..s, 2,..s and 4,..s AIDs. (These are completely described in
AN·16, available upon request.)
2. 15MHz Tracking AIDs.
3. ECl compatible applications.
4. Video displays requiring a low·glitch DAC.
5. Radar pulse height analysis system.
LOGIC INPUTS
ADJUSTABLE INPUT LOGIC THRESHOLD
Most DACs have TTL or CMOS compatible inputs which require complicated interfaces for use with ECl, PMOS,
NMOS or HTl logic. By contrast, the DAC·08, with typical
logic input current of 2"A and an adjustable input logic
threshold, interfaces easily with any logic family in use to·
day. The logic input threshold is 1.4V positive with respect
to Pin 1; for TTL Pin 1 is therefore grounded; for other
families Pin 1 Is connected as shown in the interfacing
figure. An adjustable threshold and a -10V to + 18V Input
range greatly simplify system design especially with other·
than·TTl logic. The circuits shown in c and d provide a 2VSE
VLC compensation to minimize temperature drift.
PAGE 15-6Z
1. ECl applications without level translators.
2. Direct interfaces with Hi·Z RAM outputs.
3. CMOS applications without static discharge considera·
tions.
2.4V -
4. HTl or HNll applications without level translators.
BIT 8
LOGIC
INPUT
5. System size, weight, and cost reduction.
O.4V -
OV BJ.lA lOUT
0-
5OIlSEC!DIVISION
VTH = VLC +1.4V
+15V CMOS, HTL. HNIL
VTH = +7.6V
TTL.OTL
VTH '" +1.4V
+lSV
Figure 16. lSB Switching
9.1kn
Vle
6.2ka
,el
CMOS, HTl, NMOS
13k[/.
1.8
NOTE: B1 THROUGH B8 HAVE IDENTICAL TRANSFER
1.6
CHARACTERISTICS. BITS ARE FULLY SWITCHED, WITH
LESS THAN 112 LSB ERROR, AT LESS THAN ±lOOmV
FROM ACTUAL THRESHOLD. THESE SWITCHING
1.4
~~INJ~tT~E g~::,\N:EEEgp~~ALi~N~ETT~~~~~:T~~~
11.2 r-R_A_NG,'[_'_VL_Cr["_o.o,v_'-r---r-B-,--r---H
ffi
3k12
1.0
-+-'-+-+---1--+-i
III
1--+-+-+-f----1f--+-+--H
I-
IAEF = 2.0mA
a:
a...
TO PIN 1
0.8
VLe
~ t=t:t1E:t=t:B2~r-=3=~
R3
6.2Id!
0.6
00.4
W
o
Z
z
o
~
o
-5.2V
TEMPERATURE COMPENSATING VLC CIRCUITS
-12.0 -8.0
4.0
-4.0
8.0
12.0
LOGIC INPUT VOLTAGE (V)
Figure 14. Interfacing with Various logic Families
(VTH = VLC + 1.4V)
V+
v-
Figure 17. Bit Transfer Characteristics
V+
VlC
20k.l1
DATA OUTPUT
200n
CMOS DATA INPUT
V-_
Figure 15. CMOS Differential Line Driver/Receiver
PAGE 15-63
16.0
::::i
0..
0..
«
II
REFERENCE INPUTS
MULTIPLYING CAPABILITY
Fixed internal references are included in many DACs, but
they limit the user to non-multiplying, single-polarity
reference applications and do not allow a single-system
reference. To achieve the design goals of low cost and total
applications flexibility, the DAC'()8 uses an external
reference. Positive or negative references may be applied
over a wide common-mode voltage range. In addition, the
full-scale current is matched to the reference current
eliminating calibration in most applications.
2.0
1.•
...........
............
............
........
1. Digitally controlled full-scale calibration.
0.4
2. 8 x 8 multiplication of two digital words.
+50
+100
TEMPERATURE CI
r
+150
3. Digital Attenuators/Programmable gain amplifiers.
4. Modem transmitters to 1MHz.
5. Remote shutdown and party line DAC applications.
Figure 18. VTH - VLC vs Temperature
MSB
LSB
B1 B2 83 84 85 B6 87 88
500
+ VREF .....-Jw.------+----0 EO
R2
.kn
+15V
-15V
NOTES:
1.
2.
3.
4.
5.
6.
BIPOLAR OUTPUT IS SYMMETRICAL AROUND ZERO. ADJUSTABLE PEAK-TOPEAK AMPLITUDE.
FOR TRIANGLE WAVE, COUNT UP TO FULL REVERSE AND COUNT DOWN.
FOR POSITIVE-GOING SAWTOOTH, COUNT UP TO FULL CLEAR, REPEAT.
FOR NEGATIVE-GOING SAWTOOTH, COUNT QOWN. CLEAR REPEAT.
FOR OTHER WAVEFORMS, USE A ROM PROGRAMMED WITH THE DESIRED
FUNCTION.
86nSEC SETTLING TIME PERMITS WAVEFORM PERIOD OF 25.&pSEC OR 39kHz
REPETITION RATE IN THE UNIPOLAR POSITIVE MODE.
Figure 26. Hlgh·Speed Waveform Generator
-15V
ANALOG
INPUT
o TO +10V
+15V
3.9
Cc
VIN
Mn
+15V
5.000kn
13
REF-01 vOlf6'-____....
5k"'n'lr---I,416
DAC-OSE
GND
r--'lM
-=
r----i 156
6
7 8 9 10111213
B1
B'
B3
BO
B6
NOTES:
B6
1.
B7
2.
B8
SERIAL
OUTPUT
~!:-:I::-+:-!:-:!-~-':-.,
START
CONVERSION
COMPLETE
TIL
CONNECT "START" TO "CONVERSION COMPLETE"
FOR CONTINUOUS CONVERSIONS.
FOR DETAILED lOW-COST DESIGNS REQUEST AN-11
AND AN-G.
CI~~~~ O>-~---------J
2_25MHz
Figure 27. Four IC Low·Cost AID Converter
PAGE 15-66
+VREF
RREF
VIN~
~
+VREF
RREF"" R15
tlREF
~t--14
R'N
VIN
.cu-
RREF
I.
Rl.
(OPTIONAL)
___
I.
HIGH INPUT
IMPEDANCE
• +VREF MUST BE ABOVE PEAK POSITIVE SWING OF VIN
.,r- "
• IREF ;.. PEAK NEGATIVE SWING OF liN
Figure 28. Accommodating Bipolar References
WORD "A" INPUT
EO
...":'
Z
ec
II)
w
l-
e
z
z
e
•
•
•
•
~
FAST - 85nSEC PLUS OP AMP SETTLING TIME
ANY LOGIC FAMILY FOR WORD "A" OR "B"
BIPOLAR OUTPUT
ELIMINATES SEVERAL LOGIC PACKAGES
()
::i
D.
D.
ec
Figure 29. Digital Addition or Subtraction with Analog Output
WORD "8"
DIGITAL INPUTS
WORD "A" FULL SCALE
DIGITAL INPUT
VREF
Rl
VREFI-I
V+
R2
•
•
•
•
•
Figure 30.
IFS ISTHE PRODUCT OF TWO DIGITAL INPUT WORDS
MAY BE USED AS AN 8 x 8 DIGITAL MULTIPLIER WITH ANALOG OUTPUT
ELIMINATES DAC AFTER DIGITAL MULTIPLICATION
FUNCTIONS WITH ANY LOGIC FAMILY
NOTE: LIMIT WORD "8" INPUT RISE AND FALL TIMES TO 200nSEC MINIMUM
Digitally Controlled Full-Scale Calibration (Multiplier)
PAGE 15·67
•
VREF
DIGITAL
CONTROL
1MHz
MAX
• At VOLTAGE TO DIFFERENTIAL CURRENT CONVERSION
• DC TO lMHZ INPUT RANGE
• OUTPUT DRIVES TWISTEO PAIR DIRECTLV
• CMOS COMPATIBLE
"::"
Figure 31. Modem Transmitter
1. Battery operation.
+15V
'5%
-15V
2. Use of unregulated or poorly regulated power supplies.
. F,:l'rf"l ".
+10V
3. Use in space-limited areas due to small bypass
capacitors.
-OcrOV
-tOY
,
14kn
lOOk!!
" "·t
-
'4
.7
1
"':'"
~9k"
-
4. Use in constant power dissipation applications .
4
5. Common digital and analog power supplies.
.2
DAC·OS
",
6
'OkG
7 8 91011 12 1 2
MSB
81
1.,1.
"::"
B2
~
....2 -
B3
7
'OP-02B
---1V
B4
•
EO
10,0
>------0
9 .•
B'
.6
ffi
7.0
B7
~
6.0
LSB BS
.,
,
'4kG
6 7 8 910 11 12
'4
.6
14kn
-4-
" 13
,.
DAC·OS
3
,:r
~~ n-==-
Al~ BI;' "H:GH"I OR !'lO~"
18.0
4
~
5.0
~
4.0
,.ffi
3.0
-15V
BIPOLAR INPUT} PERFORMS TWO QUADRANT
OFFSET BINARY MULTIPLICATION - AC INPUT
OUTPUT
CONTROLS OUTPUT POLARITY
l-
1+ -
I-
~ 2.0
,..
•o
'3
10kH
2.0
4.0 6.0
ao
10,0 12.0 14.0 16,0 18,0 20.0
V+, POSITIVE POWER SUPPLY (Vdcl
O.Ol,u r
+15V
I-
"::"
"::"
-15V
,.
NOTES:
Rl=R2=R3
2.
R4= R5
3. EO DC TO 20ltHz ,. '5V
4. Eo DC TO 10kHz'" '10V
Figure 33. Power Supply Current vs V +
Figure 32. DC·Coupled Digital Attenuatorl
Programmable Gain Amplifier
10.0
., ...
A~L BITS "~IGH" OR I"LOW"
I
.§ 8.0
>-
ffi
a:
POWER SUPPLIES
7.0
~ 6.0
-
r- vJ
The DAC-08 works with ±4.5V to ±18V supplies allowing
use with all standard digital and analog system supply
voltages plus most battery voltages. With only 33mW of
power dissipation at ±5V and 85ns settling time, it has a
lower speed power product than CMOS DACs. Power
dissipation is almost constant over temperature, and
bypassing is accomplished with O.D1I'F capacitors - no
large electrolytics are required. These power supply requirements allow:
a:
~ 3.0
Ii!
t-
I--
I-
I
8:
~ 4.0
-"V
IREF = 2.0mA
"~ 5,0
POWER SUPPLY REQUIREMENTS
=
I
- r--- V+ ~ +15V
I---
1 + - I--
2.•
I
I
I..
-50
+50
+100
+, ..
TEMPERATURE eCI
Figure 34. Power Supply Current vs Temperature
PAGE 15-68
10.0
•. 0
BI~S Mlv "HI~H" ~R +w·i
BJ
*
OTHER APPLICATIONS
MICROPROCESSOR APPLICATIONS
The ability to use!'P power supply voltages and the ability to
interface with any logic family make the DAC-08 especially
useful in !,P applications:
I-liTH !REFI", 2JA
1. Tracking AID converters.
I-liTH IIREJ = 1JA
2. Successive approximation AID converters.
I-WITH IREF - 0.2mA
1 II+T T
1 1 1 1
1.0
3. Direct drive from Hi-Z MaS RAM outputs.
By programming the ROMs with the successive approximation or the tracking AID algorithm, all of the logic for AID
conversion is contained in the !,P. This is a very inexpensive
approach, since there is no need for the usual AID conversion logic packages.
--4.0
-B.O
-12.0
-16.0
-20.0
-2.0
-6.0
-10.0
-14.0
-'8.0
V-. NEGATIVE POWER SUPPLY (Vdc)
Figure 35. Power Supply Current vs "-.
"'" COUNT UP, "0" COUNT DOWN
DATA
BUS
--
DIGITAL OUTPUT
--
III
W
I-
OTO -lOY
ANALOG
INPUT
o
Z
z
o
1-2
...5"kn'v--O---fV:~F~:) 8384 B5 86 B7 58
~
u
2.5kn
::::i
0.
0.
•
C
-15V
•
•
•
•
•
•
Figure 36_
USEFUL FOR ENCODING DC INPUTS
ELIMINATES UP/DOWN COUNTERS
ANSWER CONTINUOUSLY AVAILABLE
LOW POWER CONSUMPTION
HI·Z INPUT
RAM OUTPUTS MAY BE USED IN PLACE OF TTL 1/0
Microprocessor Controlled Tracking AID Converter
CONCLUSION
High voltage compliance complementary current outputs,
universal logic inputs and multiplying capability make the
Precision Monolithics DAC-08 the most versatile monolithic
high-speed DAC available today_
PAGE 15-69
APPLICATION NOTE 18
PMI
THERMOMETER APPLICATIONS
OF THE REF·02
®
By George Erdi
INTRODUCTION
This application note describes electronic thermometer applications of the REF-02 +5V Voltage Reference where the
voltage output is a direct measurement of temperature in °C
or in OF. These applications use the predictable 2.1mVloC
TEMP output voltage temperature coefficient of the REF-02,
a byproduct of a bandgap voltage reference design. Thermometer applications are described first followed by a
discussion of bandgap voltage reference theory.
THERMOMETER ESSENTIALS
In addition to a highly linear temperature sensitive component, electronic thermometers should have the following
characteristics:
1.
Convenient scaling such as 10mVloC, 100mVloC, or
10mVloF.
2.
Direct voltage readings such as -O.55Vat -55°C, OV
at O°C, and +1.25V at +125°C.
3.
Room temperature calibration.
BASIC CIRCUIT IMPLEMENTATION
The simplified schematic in Figure 1 shows the basic thermometer connections. An operational amplifier, three
resistors, and the +5.000V output of the REF-02 function
together to level shift and amplify VTEMP allowing VOUT to
read in the desired manner. The expression for VOUT is:
(
1. VOUT = 1 +
Rc)
Ra II Rb
VTEMP -
Rc
Ra (VREF)
The first term is the gain of the circuit with VREF equal to OV;
the second term is the gain of the circuit with VrEMP equal to
Vo
+5.000V
R,
R,
VREF
REF·02
TEMP
GNO
2. dVOUT =S=m (1 +
dT
.......&-.)
RaliRb
=2.1mVloC (1 +
Ra~~b)
where m = TCVTEMP
Thus, the ratio of Rc to Rail Rb sets the slope of Your, and the
ratio of Rc to Ra and VREF set the initial output value at 25°C.
Table 1 lists typical scaling ratios for different output
scales.
Table 1_ Temperature Scaling Ratios
VREF = 5.000V,VTEMP = 630mV@25'C,TCvTEMP =2.1mVI'C
VOUT @25'C
rcvOUT
Rc
(77'F)
(Slope)
Fa
250mV
0.55
10mVI'C
2.5V
100mVI'C
5.50
770mV
10mVI'F
0.926
~
R.IRb
3.76
46.6
7.57
COMPLETE CIRCUIT
Two potentiometers, Rp and RbP ' have been added to the circuit for precise calibration and to allow for the ±1 %
resistor tolerances. VREF is adjusted by Rp to set the Your
value at +25°C (77°F); the ratio of Rc to Ra II Rb is adjusted
by Rbp to set the slope of VOUT versus temperature. Resistor
values for typical output scales are shown in Table 2.
Table 2. Resistor Values
+15V
V,N
OV. Differentiating Equation 1 with respect to temperature
gives the slope, S, of the output-versus-temperature curve:
+630mV@+2Soc
>--~--o VOUT
VTEMP 2.1mVrC
TCVOUT SLOPE(S)
TEMPERATURE
RANGE
OUTPUT
VOLTAGE
RANGE
ZERO SCALE
I~~J VOUT '" (1+ Ra ~~b) VreMP = ~(VAEF)
Figure 1_ Simplified Schematic
100mVI'C
_55' to
+125'C
10mVI'F
-67'F to
+257'F
-0.55V to
+1.25V
-5.5V to
+12.5V'
-0.67V to
+2.57V
OV@O'C
OV@O'C
OV@O'F
9.09kO
15kO
8.25kO
1.5kO
1.82kO
1.0kO
Rb1 (± 1 % resistor)
Rbp (potentiometer)
2000
5001l
2001l
Rc( ± 1% reSistor)
5. t 1kll
84.5kll
7.5kll
'For 125'C operation, the op amp output must be able to swing to + 12.5V; in·
crease VIN to + 18V from + 15V if this is a problem.
Ra (± 1 % resistor)
TCVOUT = 2.1mVrC (1+ Ra
10mVl'C
_55' to
+125'C
PAGE 15-70
Step 5:
+15V
2
VIN
Vo 6
VREF
Turn power on and adjust Rp so that VO UT
equals +0.25V.
The system is now calibrated.
R.
REF·02
TRIMf=--~;&kn
3
v.
TRANSDUCER ERROR FACTORS
VOUT
Error terms are threefoid:
VTEMP
Rb1
1. Slope errors - Deviations from nominal slope. For example, if the slope Is 10.04mV/'C instead of 10.00mV/'C, the
accuracy due to the slope error is 0.4 %.
Rbp
2. Linearity errors - Deviations in VTEMP versus temperature from straight line performance, a change in VTEMP
slope with temperature.
GND
-15V
3. Offset error - VOUT deviations due to changes in VREF
with temperature.
Figure 2. Complete Schematic
CALIBRATION CONDITIONS
All calibration is conducted in free air. Heatsinking of the
REF'()2 Is unnecessary and is undesirable. The small (2 'C)
rise in chip temperature of the REF·02 above ambient tem·
perature serves as an error·cancelling factor of some sec·
ond order effects internal to the REF·02 design. The calibra·
tion procedure which follows assumes free air - no heat·
sinking - calibration.
CALIBRATION PROCEDURE
Calibration is performed at ambient temperature with two
adjustments using the fOllowing procedure:
Step 1:
Step 2:
Measure and record VTEMP and TA in 'C.
Calculate the calibration ratio "r" using
Equation 3:
_
Ra~Rb
VTEMplnmV
3. r= Rc+RalIRb = S(TA+273)
Where S = TCV ouT, TA = ambient temperature in 'C
Step 3:
Turn power off, short VREF terminal to ground,
and apply a precise 100mV to the VOUT term·
inal.
Step 4:
Adjust RbP so that VB = r(100mV); remove short.
Step 5:
Turn power on; adjust Rp so that VOUT equals
the correct value at ambient temperature.
The system is now calibrated.
CALIBRATION EXAMPLE
Here is an example at T A =25'C, S=10mV/'C, and
VTEMP =632mV:
Step 1:
VTEMP = 632mV, TA = 25 'C.
Using Equation 3:
VTEMP
632
632
r = S(TA + 273) = 10(25 + 273) = 29SO = 0.2121
Step 2:
Since these errors are grade dependent, Table 3 is provided
as an aid in specifying the correct combination of components for a given application. Offset error can be eliminated by using one REF-02 as a temperature sensor only
and another REF-02 (operated at a constant temperature) as
VREF'
Table 3. Typical Transducer Performance vs Grade
GRADE
REF·02A
PARAMETER
TEMPERATURE
-55' 10
RANGE
+125'C
SLOPE ERROR
±0.3O%
TCVTEMP
±0.10%
ERROR
OFFSET ERROR ±0.15%
RMS ERROR
:to.35%
SUM
TYPICAL
0.50%
ACCURACY
OP·02 GRADE
OP-02A
RECOMMENDED
REF·02
REF-02E
REF·02H
REF·02C
-55' 10
+125'C
0'10
+70'C
0' 10
+70'C
:1:0.40%
±0.25%
±0.35%
0' 10
+70'C
±0.45%
:1:0.12%
±0.08%
::to.10%
±0.15%
±0.4O%
±0.10%
±0.30%
±0.60%
::to.58%
±0.28%
±0.47%
::t 0.76 %
0.75%
0.40%
0.60%
0.90%
Apply 100.00mV to VOUT with power off and
VREF connected to ground.
Step 4:
Adjust RbP so that VB = r(100mV) = 21.21mV.
OP'()2E
OP·02C
4(
I/)
...0
W
Z
Z
0
~
U
::::i
IL
IL
OP·02C
TRANSDUCER PERFORMANCE
Typicai system accuracy is ±O.5% over the -55' to
+ 125 'C range of a REF'()2A. For example, when calibrated
at +25'C, the reading of VOUT at +105'C may be 105.4'C, a
deviation of 0.5% of the SO' temperature change (+25'C to
+105'C).
Although the REF'()2 is guaranteed to perform over the
-55' to +125'C range only, operation beyond those limits
is possible. A large number of devices were measured and
found to be functioning satisfactorily over the -150 'C to
+170'C range, and there was only a slight degradation in
accuracy.
In many applications, the sensor must be located some
distance away from the measurement circuitry. One precaution must be taken with the REF·02: a 1.5kll resistor should
be connected between Pin 3 (TEMP) and its associated
cable conductor to isolate this pin from cable capacitances.
PAGE 15-71
Z
4(
OP·02
REMOTE APPLICATIONS
Step 3:
GO
";"
I
,---.....--_._------0
+15V
I
12
,VIN
Vo
r---.
6
TEMP
..."
A.
R,
3 1.5k,±5%
GND
'I
14
• U P TQ
VIN
41'
4113.
R3
VREF
REF·02
TRIM 5
+
R,
R.
VREF "" +5.00V
Rb
Ic
10 FEET OF SHIELDED 4-CONOUCTOR CABLE.
:-h~7
O'-O~-:---o
V+
3
3.00R4
VOUT
4
+--'VV'r--o
::t-''''--..--:-31-'02''-.----; Vz
Ab1
1kO
_
TRIM
1.23V
TEMP"" 630mV
@+25°C
41
A1
-
;0:,
I
TCVTEMP "" 2.1mVrC
,
-16V
R4
t
51
Figure 3. Precision Temperature Transducer with Remote
Sensor
Remote application of the transducer is illustrated in Figure
3 with Rs , the isolation resistor.
~.~5kn
5.6VBE
~ '" 8.75.6VBE
'---------'.'-----_---0
GNO
Figure 4. REF·02 Simplified Schematic
Table 4. REF·02 Typical Nodal Voltages
TEMPERATURE
TRANSDUCER SUMMARY
VOLTAGE
The accuracies indicated compare quite favorably to traditional temperature measurement methods such as thermocouples and thermistors. Ease-of-use, low cost, and high accuracy make this new bandgap method of temperature
measurement attractive in a wide range of applications.
The following section describes the bandgap principle in
theory and its use in the internal REF-02 design.
-'If log. 16
TA = -7S'C
(TJ= 200'K)
T A = +2S'C
(TJ = 300'K)
TA= +12S'C
(TJ =400'K)
48mV
72mV
9SmV
VTEMP =8.75 <1V BE
420mV
630mV
840mV
VBE(Q2)
<1V BE =
810mV
SOOmV
390mV
VREF~VBE+VTEMP
1.23V
1.23V
1.23V
VREF~l +
5.00V
5.00V
5.00V
3'O:4R4
~4.06Vz
BANDGAP REFERENCE THEORY
Bandgap voltage references (1), (2), (3), use predictable relationships from semiconductor physics to generate a constant voltage. The base-emitter voltage of a transistor (V BE)
has a processing and current density dependent negative
temperature coefficient of about -2.1mV/oC. Another wellknown relationship with a positive temperature coefficient
is the difference between base-emitter voltages of two
transistors operated at different current densities:
kT
Ii
4.
k
loge (J2)'
J1 ,where
absolute temperature, OK
q
charge of an electron = 1.6 x 10- 19
coulomb
J
current density
CONCLUSION
The REF-02, by using a bandgap design, provides both a
stable +5V reference voltage output and an additional output voltage directly proportional to temperature. Accurate
electronic thermometers reading in °C or in OF can be constructed at low cost for a wide variety of temperature
monitoring and controlling applications.
Boltzmann's constant = 1.38 x 10 -23
joules/oK
T
the emitter area of 02. A AVBE of 72mV appears across R1
and is amplified by 8.75 (becoming the TEMP output) and is
added to VBE (02) to produce a nearly constant Vz of 1.23V.
The -2.1mV/oC of TCV BE is cancelled by the +2.1mV/oC of
TCVTEMP ; and Vz is amplified by 4.06 to produce an output
of VREF of 5.000V.
REFERENCES
When AV BE is amplified and added to VBE, a voltage
reference with zero temperature coefficient results if ·the
sum (Vz) of these two terms equals the linearly·extrapolated
bandgap voltage of silicon (Vgo ) at OOK or -273°C, Vgo
= 1.205V. A more exact calculation, see reference 2, will
show that Vz will have zero temperature coefficient if:
5. Vz=Vgo+ kT =1.230V@+25°C
q
The circuit in Figure 4 generates a AV BE of 72mV at 25°C by
making the current density of Q216 times greater than 01.
02 has .four times the current of 01, and 01 has four times
1. "New Developments in IC Voltage Regulators"
R.J. Widlar
IEEE Journal of Solid-State Circuits
Volume sc·6, Number 1, February 1971.
2. "A Precision Reference Voltage Source".
K.E. Kuijk
IEEE Journal of SOlid-State Circuits
Volume sc-8, Number 3, June 1973.
3. "A Simple Three-TerminallC Bandgap Reference"
A.P. Brokaw
1974 IEEE International Solid-State Circuits
Conference Digest of Technical Papers.
PAGE 15-72
APPLICATION NOTE 19
PMI
DIFFERENTIAL AND MULTIPLYING
DIGITAL·TO·ANALOG
CONVERTER APPLICATIONS
By John Schoeff and Donn Soderquist
INTRODUCTION
3. 10 = IFs - 10 for all input logic states.
The introduction of low-cost monolithic D/A converters has
simplified data acquisition and control system design. This
application note describes several n.ew applications using
the multiplying capability and dual complementary current
outputs of the Precision Monolithics DAC-08.
The relationship of IREF to 10 and 10 Is illustrated in Figure 2
and in Figure 3, the basic DC reference connections. References may be either positive or negative, and a bipolar output
voltage may be aChieved using the high compliance current
outputs alone or with an output operational amplifier. The
simplest form of a multiplying DAC accepts a unipolar varying reference input.
• CMOS, TTL. OTL
HTL. EeL, PMOS
COMPATIBLE 2p.A
LOGIC INPUTS
•
85NSEC SeTILING
TIME TO :t1/2LSB
•
DUAL
COMPLEMENTARY
OUTPUTS
WITH
HIGH IMPEDANCE
+VREF
AND -1DVTO+18V
VOLTAGE COMPLI-
IFS '"" RREF
255
MSB
x 256
LSB
81 B2 83 B4 85 86 87 B8
10 +
ANCE
RREF
+VREF
• HIGH SPEED
MULTIPLYING
iO
c
'FS FOR ALL
LOGIC STATES
IREF
R14
VREF(+)
~
-----.-
.,5
REFERENCE
INPUT
V14
r-......- '.....-'--'--'-~
eft
1456
"';"
Z
C
FOR FIXED REFERENCE,
v+
• ±4.SV TO ±lBV
33mW AT ±5V
_ EXTERNAL COMPENSATION
FOR MAXIMUM BANDWIDTH
TTL OPERATION, TYPICAL
VALUES ARE:
+VREF = +10.DIlOV
RREF = 5.000kn
R'5 <:: RREF
Cc = O.01pF
V LC .. OV (GROUND)
• ADJUSTABLE LOGIC INPUT
THRESHOLDVYH"'VLC+l.4V
V+
0mA-
VLC
NOTES:
1. RREF SETS IFS. R15 IS FOR BIAS CURRENT CANCELLATION
2. PINS 14 AND 15 ARE OP AMP INPUTS, SO V14 "" V1S
lOUT
2.0mA-
.Figure 2_ Positive Reference Connection
lOUT
The Universal DAC
IFS""
-VREF
255
MSB
LSB
B1 B2 B3 84 85 B6 87 88
'A"R'EF X2si
RREF
R14
VREF(+)
~
MULTIPLYING DAC BASICS
..l..
A multiplying DAC has an analog output which is the product of a digital input word and a reference voltage and can
be expressed as:
r-~L-I~~~~~'
14 56
IREF'" V,4
-= R1S VREF(-)
-VREF~
15
V16L.3r-_....:r~..:;:._.;-.1
FOR FIXED REFERENCE,
TTL OPERATION, TYPICAL
VALUES ARE:
A1 A2 A3 A4 A5 A6 A7
A8
1.1 Eo=EREF 2+4"+8+16+32+64+128+256
For a current reference, current output DAC, the expression
becomes:
2. 110=IREF
O
Z
Z
o
~
CJ
:::i
AA-
•
C
1.0mA-
Figure 1_
13t-
O.'J.1F
V-
r
~
-VREF = -to.DIlOV
RREF = 5.000kn
R,S"" RREF
Cc '" O.01pF
VLC to OV (GROUND)
V+
VLe
NOTES:
A1 A2 A3 A4 A5 A6 A7
A8
2 +"4+8+16+"32 +64 + 128 + 256
1.
2.
The DAC-08 has complementary/differential current outputs, and 10 has a complement expressed as:
RREF SETS IFS. R1S IS FOR BIAS CURRENT CANCELLATION.
PINS 14 AND 15 ARE OP AMP INPUTS, so V14 "" V1S.
Figure 3_ Negative Reference Connection
PAGE 15-73
BIPOLAR REFERENCES
Operation with bipolar references Is achieved by
modulating IREF as shown In Figure 5. To aid in understanding bipolar operation, see the equivalent circuit in Figure 4.
The reference inputs of the DAC-08 are op amp inputs VREF (+) being the inverting input and VREF (-) being the
noninverting input. Excellent gain linearity of the reference
amplifier allows multiplying operation over a range of IREF
of 4pA to 4mA with monotonic operation from less than
100pA to 4mA.
VREF (+1
Cc = 15pF, the reference amplifier slews at 4mA/I's enabl,
ing a transition from IREF = 0 to IREF = 2mA In 500ns. If R14 or
the parallel equivalent resistance at Pin 14 Is less than
2000, no compensation capacitor is necessary, and a fullscale transition requires only 16ns.
TWO-QUADRANT MULTIPLICATION
There are two forms of two-quadrant multiplication: bipolar
digital, where the digital input word controls output polarity,
o-c-14'-t--,--t--,
16
3
v~
CQMP
Figure 4. DAC-08 Equivalent Circuit
LOW INPUT IMPEDANCE
MSB
+VREF
HIGH INPUT IMPEDANCE
lS8
81 82 83 84 65 B6 B7 B8
MSB
LSB
B1 82 B3 84 85 86 B7 88
+VREf
AREF
VIN
IREF;;' PEAK
NEGATIVE
~
-------
OR_'_5-'\'O"'T,,,'O_N_AL-jl
+VAEF MUST BE ABOVE
PEAK POSITIVE SWING
SWING OF liN
OF VIN
v.
r
VLe
v-
-=
O•1J.jF
VLe
Figure 5. Bipolar Reference Connections
REFERENCE AMPLIFIER COMPENSATION
AC reference applications will require the reference
amplifier to be compensated using a capacitor from Pin 16
to V -. The value of this capacitor depends on the impedance presented to Pin 14: for R14 values of 1.0, 2.5 and
5.0kO, minimum values of Cc are 15, 37, and 75pF. Larger
values of R14 require proportionately increased values of Cc
for proper phase margin.
FAST PULSED OPERATION
For fastest multiplying response, low values of R14 enabling
small Cc values should be used. For R14 = 1kO and
and bipolar analog, where the analog reference input controls output polarity.
Bipolar digital two-quadrant mutliplication is shown in
Figure 6 with the output polarity being controlled by an
offset-binary-coded digital input word.
Bipolar analog two-quadrant multiplication is shown in
Figure 7. A bipolar reference voltage is connected to the upper DAC-08 and modulates the reference current by ± 1.0mA
around a quiescent current of 1.1 mAo The lower DAC-08 also
has a reference current of 1.1mA; due to the parallel digital
inputs, the lower DAC-08 effectively subtracts out the quiescent 1.1mA of the upper DAC-08's reference current at all in-
PAGE 15-74
put codes, since the voltage across R3 varies between
-10V and OV. Thus, the output voltage, Eo, Is a product of a
digital input word and a bipolar analog reference voltage.
Msa
LSB
a1 82 B3 B4 85 88 B1 B8
FOUR·QUADRANT MUTLlPLICATION
Four·quadrant multiplication combines the two forms of
two-quadrant multiplication. Output analog polarity is controlled by either the analog input reference or by the offset
binary digital input word. One implementation of this function
with the DAC-08 is shown in Figure 8 with output current
values listed In Table 1.
6.00Okn
VREF O--~>NI,......-i
o TO +lOV
• .lIkn
Ai:
5.Okn
IF RL • RL WITHIN :to.05%. OUTPUT IS
SYMMETRICAL ABOUT GROUND.
B1 B2 B3 B4 B5 B6 B7 B8 10 mA
lomA
EO (V)
1
1.992
0.000
+9.96
1 0
1.984
0.008
+9.88
0 0 0
1.000
0.992
+0.040
-0.040
POS. FULL SCALE
1
1
1
1 1
1 1
POS. FULL SCALE - LSB
1
1
1
1 1
1
1 0 0
0 0
1 1
(+ I ZERO SCALE
H ZERO SCALE
10k!}
10kn
'REF
#2
IREF
#1
+"
+
OAC-OB #1
-
0
1
1
1 1
1
0.992
1.000
0
0
0 0
0
0 0
1
0.008
1.984
-9.88
NEG. FULL SCALE
0
0
0
0
0 0 0
0.000
1.992
-9.96
DIGITAL
INPUT
1
LS.
DAC-08 #2
--
,.,.
.••
14
.7
....n
~':
16
•
•
•
~
Z
o
~
(.)
C
0.",
~
L.....! _
.7
,.
,. ,.
66789101112
QAC·DB
13
3
~~
,:;:- .
.3
,"
-16Y
~
-::
~
The four·quadrant mutliplying DAC circuit shown accepts a
differential voltage input and produces a differential current
output. An output op amp is not shown because It is not
always required; many applications are more suited for high
output compliance (-10V to + 18V) differential current outputs. Typical balanced loads include transformers, transducers, transmission lines, bridges and servos.
Operation of the four-quadrant multiplier may be more easily
visualized by considering that if either VIN OV or the offset
binary digital input code is at midscale (corresponding to
zero), then a change in the other input will not affect the output. Zero multiplied by any number equals zero.
=
o.Ol~f~,:;-
+15V
Figure 8. Four·Quadrant Multiplying DAC with
with Impedance Input
7
~V4
as
-#
•
•
SWITCHED DAC'S
TRUE CURRENT OUTPUT - WIDE
COMPLIANCE
ADJUSTABLE LOGIC THRESHOLD
WIDE POWER SUPPLY RANGE
S
Z
7 8 9 10 l' 12 1 2
..
.
••
•
2 PACKAGES VS 3 fOR VOLTAGE
IL
IL
6
14kn
OVER ENTIRE RANGE
HIGH
IMPEDANCE DIFFERENTIAL
INPUTS
±10V DIFFERENTIAL INPUT RANGE
•
••
10k"
B3
.5
HIGH SPEED MONOTONIC OPERATION
II)
III
:::i
'~
1.,1.
14kn
10
•
"
DAC.Q8
B2
us sa
"~L
-16V
F,:l"r~It·..
.,
111<"
TO
LOAD
.. '0
+ .,
+15V
101
BA LANCED
MS8
Figure 6. Bipolar Digital Two-Quadrant Multiplication
(Symmetrical Offset Binary)
+1OV
-"'\;;:rOV
-lOV
-
:) ... '0.
lOUT = 101- 102
NEG. FULL SCALE +LSB
0
~ .,
+
_15V
PERfORMS TWO QUADRANT
MULTIPLICATION - AC INPUT
CONTROLS OUTPUT POLARITY
Figure 7. Bipolar Analog Two-Quadrant Multiplication
(DC·Coupled Digital Attenuator)
A common mode current will be present at the output and
must be accommodated by the balanced load. A pair of
matched resistors may be used at the outputs to shunt most
of the common mode current to ground, thus reducing the
common mode voltage swing at the output.
PAGE 15-75
II
Table 1. Four·Quadrant Multiplying Current Values In Figure 8.
DIGITAL
INPUT
VIN (+)
VIN (-)
VIN
DIFF.
10#1
(mA)
IREF
IREF
#1 (mA) #2 (mA)
10#2
(mA)
101
(mA)
10#2
(mA)
10#1
(mA)
102
(mA)
lOUT
DIFF.
0.996mA
1111 1111
+5V
-5V
+10V
2.000
1.000
1.992
0
1.992
0.996
0
0.996
1000 0000
+5V
-5V
+10V
2.000
1.000
1.000
0.496
1.496
0.500
0.992
1.49:01
0.004mA
0111 1111
+5V
-5V
+10V
2.000
1.000
0.992
0.500
1.492
0.496
1.000
1.496
-0.004mA
0000 0000
+5V
-5V
+10V
2.000
1.000
0
0.996
0.996
0
1.992
1.992
-0.996mA
11111111
OV
OV
OV
1.500
1.500
1.494
0
1.494
1.494
0
1.494
O.OOOmA
10000000
-10V
-10V
OV
2.500
2.500
1.250
1.240
2.490
1.250
1.240
2.490
O.OOOmA
0111 1111
+10V
+10V
OV
0.500
0.500
0.248
0.250
0.498
0.248
0.250
0.498
O.ooomA
0000 0000
OV
OV
OV
1.500
1.500
0
1.494
1.494
0
1.494
1.494
O.ooOmA
1111 1111
-5V
+5V
-10V
1.000
2.000
0.996
0
0.996
1.992
0
1.992
-0.996mA
10000000
-5V
+5V
-10V
1.000
2.000
0.500
0.992
1.492
1.000
0.496
1.496
-0.004mA
01111111
-5V
+5V
-10V
1.000
2.000
0.496
1.000
1.496
0.992
0.500
1.492
O.004mA
0000 0000
-5V
+5V
-10V
1.000
2.000
0
1.992
1.992
0
0.996
0.996
0.996mA
HIGHEST SPEED FOUR·QUADRANT
MULTIPLYING CONSIDERATIONS
+15V
The configuration shown in Figure 10 makes use of the
DAC-08's ability to operate in a fast-pulsed reference mode
without compensation capacitors. This technique provides
lowest full-scale transition times. An internal clamp allows
quick recovery of the reference amplifier from a cutoff
(lREF = 0) condition. This connection yields a reference slew
rate of 16mA/ftS which is relatively independent of RIN and
VIN values.
+10.0OV
REF·Q1
~
-=- RIN1
+
10kn
RIN2
-
Input resistances are not limited to 10kll. For example,
100kll resistors for RIN1 and RIN2 allow ±100V reference
voltage inputs making this ponnection especially useful in
high common mode voltage environments. Except for different reference treatment, operation and digital input
coding are identical in the circuits shown in Figure 8 and in
Figure 10; both have the transfer function shown in Figure 9.
V'N
10""
MSB/
~~
5kn
-=
lOUT = 101 - 102
5kU
,.
,t~,.
t
,,-
DAC'()8#1
+
';).
To"~
BB
-B1
'01
TO
BALANCED
LOAD
102
DIGITAL
, "INPUT
LSB
~
+ B1
DIFFERENTIAL
CURRENT OUT (+)
1mA
- •
01 FFERENTIAL
DifFERENTIAL
VREF = +lOV
VREF = -10V
•
f-
DAC·OS :/2
10
BB:t
lO
250n RESISTORS AND OMISSION OF COMPENSATION CAPACITORS ARE OP·
TlONAL FOR FAST PULSED REFERENCE OPERATION.
INPUT OIFFERENTIAL AND COMMON MODE RANGES ARE EXTENDABLE BY
INCREASING ,OkSl RESISTORS. EXAMPLE: 100kn FOR 'lOGV.
•
•
HIGH SPEED MULTIPLYING CONNECTION WITH MONOTONIC OPERATION
OVER ENTIRE RANGE.
NOT NECESSARY TO MODULATE BOTH OAe's WITH THE REFERENCE INPUT.
DIGITAL
DIGITAL
INPUT (-) 1++++lI+t++t~IEt-+++t+I+++-t-t INPUT (+J
0000 0000
1111 1111
Figure 10. Four·Quadrant Multiplying DAC with Extendable
Input Range and Highest Speed
AC·COUPLED MULTIPLICATION
1mA
DIFFERENTIAL
CURRENT OUT I-I
Figure 9. Four·Quadrant Multiplying DAC Transfer Function
Some multiplying DAC applications are more easily achieved
with AC coupling. At the same time, a high impedance input
is often required to avoid loading a relatively high source impedance. Both requirements are met by the circuits shown
in Figure 11 and Figure 12 which use the compensation
PAGE 15-76
-
VO(FS) = O.775Vrms '" OdB
DAC·DB
TO LOAD
Vo
DAC·DB
... 45OkHz I.F.
TRANSFORMER
j~~,
,,,,
,kn
'-----'
DIGITAL CONTROL INPUT
DIGITAL CONTROL INPUT
•
•
GREATER THAN 40dB DYNAMIC RANGE
2.DMn TYPICAL INPUT IMPEDANCE
•
•
•
Figure 11. High Input Impedance AC·Coupled Multiplication
(Audio Frequency Digital Attenutor)
OFFSET BINARY CODING ALLOWS PHASE INVERSION OR TWO·QUADRANT
MULTIPLICATION
85NSEC SETTLING TIME FOR DIGITAL INPUT CHANGE
LOW DISTORTION AND HIGH SPEED
Figure 12. High Input Impedance AC·Coupled Multiplication
(I.F. Amplifier/Digital Attenuator)
capacitor terminal (Cc) as an input. This is possible because
Cc is the base of a transistor whose emitter is one diode
drop (O.7V) away from the R·2R ladder network common
baseline internal to the DAC-OS.
DIFFERENTIAL AND RATIOMETRIC
AID CONVERSION
Complementary/differential current-source outputs and
multiplying capability allow the DAC-OS to be used in differential and ratiometric AID converter designs directly
without signal conditioning amplifiers. This group of applications begins with the basic differential A/D converter
and ratiometric AID conveter connections followed by more
specific applications.
With a full-scale input code the output, Vo, is flat to
> 200kHz and is 3dS down at approximately 1.0MHz making
this type of multiplying connection useful even beyond the
audio frequency range. Such a connection is illustrated in
Figure 12 operating at 455kHz, the highest recommended
operating frequency in this connection.
1/1
1&1
I-
o
Z
Z
o
~
o
::::i
a.
a.
,
DIGITAL OUTPUT lei '"
''}
•
•
•
HIGH SPEED WITH FULL ACCURACY OVER ENTIRE DYNAMIC RANGE
:l:5V DIFFERENTIAL INPUTS WITH ±5V COMMON MODE RANGE
DIODES ARE 1N4148'S
Figure 14_ Four-Quadrant Ratlometrlc AID Conversion Basic Connections
PAGE 15-78
~
Y+15V
+5.000v
+
RREF
I
~
IO-+-
10_< .,
+
BRIDGE
SUPPLY
(REF·02)
r--
DAC...
.8-~
1
f--o
f---o
·
·
··
DIGITAL
OUTPUT·
'--
t>-
UP/DOWN COUNTER
(BBITS)
r-----<>
CORRECTION CURRENT TRACKS BRIDGE SUPPL V SO
NULL IS MAINTAINED
DIGITAL OUTPUT INDICATES PREVIOUS NULLING
ERROR
CIRCUIT CAN ALSO MEASURE BRIDGE RESPONSE
TO INPUT VARIABLE - PROCESSOR CAN COMPUTE
DIFFERENCE WITH RESPECT TO ZERO ERROR
NO OPERA TIONAl AMPLIFIERS OR SUMMING RESIS·
TORS ARE REQUIRED
HIGH NOISE IMMUNITY LOGIC COMPATIBLE (HTL,
CMOS)
CLOCK
+
Figure 15. Bridge Transducer Null
~AC
u
+15V
POWER
• DETECTS AND DIGITIZES SPIKES AND FAULT CONDITIONS
• TRACKING AID CONVERTER UPDATE RATE: 200NSeC (6MHz MAX)
• RESOLUTION FOR 400Hz AT MAX CLOCK IS O. 028 DEGREES
6"':,08" 80 X 10-8 .. aoPPM
--
-ff
1Ok!l
REF·01
+
+1DV
DAC.()8
r- -
IO~
10V
MAX
104-
?>--
=
0.008% = o. 028 DEGREES
:ztO
Z
Z
UP/DOWN
COUNTER
CLOC
t--o
o
~
(J
~
~
~
":'
":'
II
":'
DIGITAL OUTPUT
Figure 16. Power Fault Monitor and Detector
ceed ±10V; and the differential voltage must not exceed
11V. Voltage·limiting resistors at the comparator's inputs
are recommended.
ALGEBRAIC DIGITAL COMPUTATION
Frequently, a digital arithmetic operation (addition, subtrac·
tion, multiplication, or division) must be performed, and an
analog output must be provided. Traditionally, the arith·
metic operations are performed with several ICs, and the
output drives a CIA converter. This section decribes applica·
tlons of the CAC-OS as an arithmetic building bloCk, new
design approaches that reduce the number of packages reo
quired in many applications. Today's low cost, versatile
DACs merit a designer's consideration as arithmetic
elements.
PAGE 15-79
One benefit is not immediately apparent and deserves
special mention. In all of these applications, the digital Input
words can be CMOS, TIL, OTL, NMOS, or MECL, because
the OAC-OB interfaces with all of those logic families. In
fact, the two input words may even be from different logic
families to eliminate special level translators or interface
circuitry. (See AN-17 "DAC-08 Applications Collection.")
FOUR·QUADRANT DIGITAL MULTIPLICATION
High-speed multiplication of two 8-bit digital words with an
analog output usually requires several logic packages and a
D/A converter. The circuit in Figure 18 performs this function using only three ICs.
In Figure 18 DAC-08 number 1 and number 2 are connected
as previously shown, and OAC-oa number 3 provides the
analog reference inputs to OAC-08 number 1 and number 2.
Those reference inputs are determined by digital Input word
"A." The circuit's output, 101 -102, is a differential current output which may be used to drive a balanced load.
The first arithmetic application is shown in Figure 17. Two
DAC-08s perform a fast algebraic summation with a direct
analog output. The circuit works by paralleling the outputs
of two DAC.Q8s and summing their currents while driving a
balanced load. The output is the algebraic sum of word "A"
and word "S" in all four quadrants.
Four-quadrant multiplication is thus performed by adding
one more DAC.Q8 to the basic four-quadrant multiplying
connection.
VREf +lOV
DIFFERENTIAL
CURRENT
OUTPUT
"""
RREF
101 -102
r-------------~
101
~
,0;\--......=--<>
EOUT
DAC-OB #1
,'OY
K =
-::WORO"A"
11111111
1100 0000
(B) DIGITAL INPUT WORD
~::~
AND "A" AND "8"
ARE POSITIVE OR NEGATIVE OfFSET
BINARY DIGITAL WORDS
WORO"B"
11111111
10]
3.984mA
3.000mA
2.000mA
1100 0000
1000 0001
1000 0000
0111 1111
0111 1111
0111 1111
01" 1110
1000 0000
1000 0000
1.92mA
l.992mA
1.984mA
0011 1111
0000 0000
0011 1111
0000 0000
0
O.984mA
IQ2
EOUT
+9.9BV
O.BB4mA
+5.04V
+O.04V
0
1.984mA
1.992mA
1.992mA
2.000mA
3JlOOmA
a98_
0
0
-O.04V
-6.D4V
-9.96V
Figure 17. Four-Quadrant Algebraic Digital Computation
I
VREF
+10.00V
[~
OAe-DB #3
ee
~6kn r
i--:- .,r ..-
'kn
--1+
I:l
10
"-,t
e.
DAc-CJ8~l
;)
10
.
.
.
'
.
1t
+
IBI DIGITAL INPUT WORD
DAC.Q8.1t2
2.on
-ec
HIGH SPEED MONOTONIC OPERATION OVER THE ENTIRE DV·
NAMICRANGE
FOR HIGHEST MULTIPLYING SPEED, USE 2500 RESISTORS
AND NO COMPENSATION AS SHOWN. (THIS ALSO LOWERS THE
RC PRODUCT AT DAC.os #3 OUTPUTS.)
-::-
-::-
Figure 18. Four-Quadrant 8-SIt x 8-Blt Digital Multiplier
PAGE 15-80
bN.e.
101
TO BALANCED LOAD
102
lOUT = 101- 102
v-
IA) DIGITAL INPUT WORD
-
:>
10
APPLICATION NOTE 20
PMI
EXPONENTIAL DIGITALLY CONTROLLED
OSCILLATOR USING DAC-76
By Donn Soderquist
Here is a 4-IC, microprocessor-controlled oscillator with a
8159 to 1 frequency range covering 2_5Hz to 20kHz. An exponential, current output IC DAC functioning as a programmable current source alternately charges and discharges a
capacitor between precisely-controlled upper and lower
limits. This circuit features instantaneous frequency
change, operates with +5V ±1V and -15V ±3V supplies,
and provides monotonic frequency changes over a 78dB
range - the dynamic range of a 13-bit DAC.
When 58 is low, lo( -) is selected, and the DAC's output current drives a current mirror which ramps the timing capacitor in a positive direction until an upper limit of OV is sensed
by A2. At this time the set-resist flip-flop (L1) is set, 58
becomes a "1", and the DAC's output current is switched to
the lo( +) output. Now the capacitor is charged to a lower
limit of -5V, the flip-flop is reset, and the cycle .repeats
itself.
REFERENCE SETUP
The multiplying relationship between the reference current,
IREF' and the full-scale output of the DAC is 3.863. IREF is set
by the voltage between V + and the lower limit divided by
R1 + R2. This is 50 because Pin 12, VREF(-), is a highimpedance input, namely the noninverting input of an op
amp internal to the DAC. Since both IREF and the upper and
lower limits are derived by dividing down the power supply
voltages, operation (frequency of oscillation) is independent
of power supply changes. (See Appendix for. a complete
derivation of the timing formula.)
BASIC OPERATION
Connected as shown below, the output of the exponential
DAC is an eight-chord (or segment) current ranging between
250nA and 2.0mA. The three most significant bits select 1 of
8 binarlly-related chords; and the five least significant bits
select 1 of 32 linear steps within each chord. This current is
switched between the lo( +) output and the lo( -) output
under the control of a pin labeled SB.
II
CURRENT MIRROR
+5V IV+I
R3
10""
'REF'""
+soo.A
R1
10""
01
1 -'.
DIGITAL INPUTS
CHORD
SELECT
STEP
SELECT
101+) '" 101-1
UL
R2
UL
10""
101+1
R4
10""
LL
,.
R.
1_
LL
UPPER LIMIT ... OV
R6
10ld'
LOWER LIMIT ... 6V
I
·ALL 10kn RESISTORS ARE PART OF 14-PIN DIP NETWORK
BOURNS #4114R·OO'-,03S.
-=-
Circuit Diagram Exponential Dlgitally·Controlied Oscillator
PAGE1S-81
C
••
A
--u-L
-15V
o.01P/
V
~ T --I
A
ov
'-5V
I
f--T--I
({~i ~~~ , WHERE
tA I '" NORMA~IZEO DIGITAL
T =
INPUT
CURRENT MIRROR
to#.
IREF'"'
+6V (V+)
O.
03
.111<0
'01<0
10 1-1+
DIGITI\L INPUTS
10(+1 • 101-1
STEP
UL
SELECT
R2
UL
'01<0
101+1
O.
'01<0
12
LL
•
AS
.01<0
LIL
-15V
RS
.01<0
LOWER LIMIT'" 5V
1-=-
·ALL 1Ok,o RESISTORS ARE PART OF 14.pIN DIP NETWORK
BOURNS #4114R·ocn·103S.
C
,~A
0.01#/
A
'-../"
ov
"
I---T----I
-5V
T =
('~i 'i~~
I--T-I
.WHERE
IA J '" NORMALIZED DIGITAL INPUT
Circuit Diagram Exponential Dlgltally·Controlied Oscillator
Table 1. Ideal Output Frequency
20tHz
CHORD
(SEG·
MENT)
OUTPUT
FREQUENCV
DIGITAL
INPUT
CODE
ii159
000 01000
ii159
5kHz
000 11111
2.5kHz
NORMALIZED
DIGITAL
./8
00100000
'NPUTIAI
5/8
Oscillator Transfer Function
ON
ON
ON
ON
"A"
.•.
:J
ii159
10100000
ii159
495
991
1023
2015
10111111
ii159
11000000
ii159
2079
4063
11011111
ii159
11100000
ii159
11111111
PAGE 15-82
479
100 11111
7
Waveforms
231
ii159
ii159
6
I
223
8159
ii159
5
r
99
100 00000
4
'y
95
01111111
-sv
ilO'i'
33
8159
ii159
01100000
OUT
ii159
ii159
3
RAMP
31
01000000
01011111
ov
8
00111111
2
1-'01-1+'01+1+'01-1+'0(+1--1
1
000 00001
10kHz
0
NORMAL·
IZED
DIGITAL
INPUTIAI
4191
~=FS
8159
OUTPUT
FRE·
QUENCY
AVERAGE
STEP
SIZE
2.45Hz
19.6Hz
2.3Hz
76.0Hz
8O.9Hz
4.8Hz
233Hz
243Hz
9.5Hz
547Hz
566Hz
19Hz
1.17kHz
1.21kHz
38Hz
2.43kHz
2.51kHz
76Hz
4.94kHz
5.09kHz
152Hz
9.96kHz
10.3kHz
303Hz
20.0kHz
FREQUENCY SELECTION
R5+R6
Equation 4. LL= R3+R4+R5+R6
Table 1 lists ideal output frequencies at the lowest and
highest codes of each chord and the average change in frequency produced by a one-step change (LSB change) within
each chord. For highest accuracy in Chord 0, especially between 2.5Hz and 19.6Hz, comparators with low input current
are recommended. The CMP-02CY comparators typically have
35nA of input current; at the lowest code pOint (000 00001)
the DAC output is 250nA; so low input current comparators
are essential for best operation. Above 000 01000 (4p.A or
19.6Hz) the comparator input currents become less critical.
LL- (V+)+(V-)
-
2
Substituting 3 and 4 into 2 and solving for E:
Equation 5. E= (V+)~(V-)
Rewriting Equation 1 and substituting 5:
Equation 6. 26
(V+)-(V-)
4
T
CONCLUSION
The expression for I is:
A mlcroprocessor-controlled oscillator has been shown
which achieves a 13-bit dynamic range with only 8 bits of
control. Monotonic frequency steps over 2.5Hz to 20kHz are
provided in a 4-IC low-cost design.
Equation 7. 1=3.863 IAIIREF
REFERENCE
(V+)-LL
.
Equation 8. IREF= R1 +R2
"Eight-bit Frequency Source Suited for p.P Control" by
Albert Helfrick, EON, September 20,1976, pp. 116-118.
[ (V+)-(V-) ] +(V-)
where: 3.863 is a constant derived from the ratio of
IREF to IFULL SCALE of the DAC
A = the normalized digital input code
IREF = the reference current
Substituting 4 into 8:
Equation 9. IREF =
APPENDIX
_(V+)-(V-)
- 2(R1 +R2)
TIMING EQUATION DERIVATIONS
One of the best features of this design is its insensitivity to
power supply changes. The equation derivations are shown
to explain how V + and V-drop out as timing determinations.
With a constant current drive the charge on C changes
linearly over a range (E) between an upper limit (UL) and a
lower limit (LL) dependent upon the DAC's digital input
code, the DAC's output current, and the value of the timing
capacitor (C).
Equation 1. T = 2 (CIE) where:
Substituting 9 and 7 into 6:
(V+)-(V-)
Equation 10. 26 =
3.8631AI
[1v2(R1
+)-(v-)]
+R2)
Multiplying by IAI 3.863:
(V+)-(V-)
4
E
t · 11 IAI 3.863T
2C
=(V+)-(V-)
qua Ion .
2(R1 +R2)
IAI3.863T
2C
=
C = timing capacitor value
E = upper limit -
(V+)- [(¥+)+(V-)]
R1 + R2 2
R1 +R2
2
lower limit
So V+ and V- have dropped out as timing considerations.
Solving for T:
I = DAC output current, lot +) or lot -)
T = period
Equation 12. T = C(R1 + R2) but: C = 0.01 p.F
3.863IAI
R1=R2=10kO
Equation 2. E = UL - LL where: UL = upper limit
LL = lower limit
.
R4+R5+R6
Equatron 3. UL= R3+R4+R5+R6
[
(V+)-(V-)
]
+(V-)
Finally, the simplified expressions:
where: v + = positive power supply and V - = negative
power supply
but:
:. UL=
Equation 14. T=
5~
R3=R4=R5=R6
3(V+)+(V-)
4
Equation 15. f (frequency) = __
IA_I_ == 20kHz full scale
50 X 10-6
PAGE 15-83
II
OTHER DAC APPLICATIONS
DATA TRANSMISSION
The combination of high voltage compliance complementary current outputs, universal logic inputs, and multiplying
capability in a low-cost DAC enables widespread application. Consider the following partial list:
Modem Transmitter
Differential Line Driver
Party Line Multiplexing of Analog Signals
Multi-Level 2-Wlre Data Transmission
Secure Communications (Constant Power Dissipation)
AID CONVERTERS
Tracking (Servo)
Successive Approximation
Ramp (Staircase)
Microprocessor Controlled
Ratiometric (Bridge Balancing)
CONTROL SYSTEMS
Reference Level Generator for Setpoint Controllers
Positive Peak Detector
Negative Peak Detector
Disc Drive Head Positioner
Microfilm Head Positioner
TEST SYSTEMS
Transistor Tester (Force 18 and Icl
Resistor Matching (Use both outputs)
Programmable Power Supplies
Programmable Pulse Generators
Programmable Current Source
Function Generators (ROM Drive)
AUDIO SYSTEMS
Digital AVC and Reverberation
Music Distribution
Organ Tone Generator
Audio Tracking AID
CONCLUSION
ARITHMETIC OPERATIONS
Analog Division by a Digital Word
Analog Quotient of Two Digital Words
Analog Product of Two Digital Words - Squaring
Addition and Subtraction with Analog Output
Magnitude Comparison of Two Digital Words
Digital Quotient of Two Analog Variables
Arithmetic Operations with Words from Different Logic
Families
Differential and multiplying applications have been described
which use the high-voltage compliance, complementarycurrent outputs and the high-speed multiplying inputs of the
Precision Monolithics DAC-OB.
BIBLIOGRAPHY
1.
"DAC-08 Applications Collection", John Schoeff and
Donn Soderquist, Precision Monolithics Application
Note 17, 1975
2.
"Low Cost, High-Speed Analog-to-Digital Conversion
with the DAC-08", Donn Soderquist and Joilln Schoeff,
Precision Monolithics Application Note 16, ;975
3.
"Differential and Multiplying Use of Digital-to-Analog
Converters", Donn Soderquist and John Schoeff, E.E.
Times article, June 21,1976, pp. 40-47
GRAPHICS AND DISPLAYS
Polar to Rectangular Conversion
CRT Character Generation
Chart Recorder Driver
CRT Display Driver
PAGE 15-84
APPLICATION NOTE 21
PMI
®
3 IC 8·BIT BINARY DIGITAL TO PROCESS
CURRENT CONVERTER
WITH 4·20mA OUTPUT
By Donn Soderquist
This application note describes a 3 IC, 4-20mA process current, digital-to-analog converter that can be constructed for
less than $20 at current 100+ prices_ It operates from a - 5V
±1V negative power supply and a +23V ±7V positive
power supply, has 24V output voltage compliance, and occupies less than 4 square inches of printed circuit board
space_ Other significant features include TTL logic input
compatibility, 8-bit binary coding, O· to + 70· C operation,
and 51's full scale settling time into a 500010ad_
through Q1, a high hFE transistor_ The same +10V is applied
to R3, the reference input resistor of a multiplying IC D/A
converter, the DAC-08_ Full scale output current of the DAC
will be the difference in voltage between the +10V
reference and Pin 14 of the DAC divided by R3; Pin 15 will be
at the same voltage as Pin 14 because it is a high impedance point, the noninverting input of an op amp internal
to the DAC_ After calibration a current of 0 to 2mA (depending on the digital input code) will flow into the DAC's output, Pin 4_
THEORY OF OPERATION
Both the DAC's output current and the fixed 0_5mA flow in
R5, a 8000 precision resistor_ The voltage developed by that
current is applied to the noninverting input of the other half
of A3 and will also appear across R6, a 1000 precision
resistor. Thus, eight times the 0_5 to 2_5mA current in R5
flows in R6, or 4 to 20mA_ Almost all of this current appears
at the output because the 2N6053 is a high hFE device, a
power darlington transistor_
A fixed current of 0_5mA is added to a DAC's output current
varying between 0 and 2_0mA and the resulting total current
is multiplied by a factor of 8 to produce an output current of
4_0 to 20mA_
In the schematic, first note the REF-01CJ, a +10V adjustable reference_ Its output goes to the noninverting input
of one half of A3, a dual precision op amp_ The inverting input is within a feedback loop forcing + 10V to appear at the
top of R4, a 20kO resistor; a 0_5mA current will flow in R4
Some other components need explanatlon_ C1 provides frequency compensation of the DAC's reference amplifier; C2
SCHEMATIC DIAGRAM
Tol
R6
RS
'Don
800Il
LSB
VIN vo I"6'----+'.OV'----+-_R"'2,----.N1I"-"I
4
~n
ZERO
~'i:t SCALE
}*AD:.:;.JU,-,S_T_ _',5 VREF(-)
V+
13
C,
C3
f
I~F
!o.smA
PF
-5V±1V
OUTPUT VOLTAGE
COMPLIANCE (Voe)
Vee
'6V
Voc
,ov
23V
'1V
30V
24V
·SETTLING TIME ~ s"tSEC
WITH Rl = soon
PAGE 15-85
AA-
C
III
TTL
ADJUST
~
±O.1%
±O.l%
DIGITAL INPUTS
MSB
TRIM 5
w
o
z
z
o
::::i
0.5
2.5mA ...
GND
c
II)
~u
Vee +16V TO +3DV
RE~~lCJ
liiz
1'TO
20mA
and C3 are power supply decoupling (bypass) capacitors; C4
prevents high frequency oscillations. 01 through 04 insure
at least 2.5V differential between the op amp's inputs and
its positive power supply under all conditions. R1 and R2 are
zero scale and full scale adjustments respectively.
design is tolerant of wide power supply variations, has high
voltage compliance, and is easily calibrated. Reliability and
cost are optimized by using only three integrated circuits,
the Precision Monolithics DAC-OS, REF,01, and OP·14, plus
a few readily available discrete components.
CALIBRATION PROCEDURE
Apply +23V ±7Vand -5V ±1V to the converter with a
current·measuring meter connected between the output and
ground. Make the digital inputs all zeros, < +O.SV. Adjust
R1 until the output current is 4.0mA. Now change the digital
inputs to all ones, > +2.0V. Adjust R2 until the output cur·
rent is 20mA. Calibration is now completed.
REFERENCE
Crowley, B., "Circuit Converts Voltages to 4-20mA For Industrial Control Loops," Electronic Design, Jan. 5, 1976,
page 116.
PARTS LIST
OUTPUT VOLTAGE COMPLIANCE
Output voltage compliance is Vce -6V. For example, at Vee
= +16V, the output may go to a maximum of +10V without
affecting output current. Thus, a 5000 resistor would be the
maximum load resistor at Vee = +30V, Voc = 24V, and RL
Maximum = 1.2kO.
Circuit
Symbol(s)
+ 10V Reference, PM I REF-01 CJ
A2
S-Bit DAC, PMI DAC-OSCO
A3
C1-C3
C4
SCALE MODIFICATION
Although the values shown are for the more common
4·20mA requirement, operation at 1-5mA or 10-50mA may be
achieved by changing some components. For 10·50mA,
change R6 to 400; this makes the multiplying factor 20 instead of S. For 1-5mA, replace the 2N6053 with a 2N50S7,
and change R6 to 4000.
D1-D4
PAGE 15-86
100pF ±5% Mica, DM100ED101J03
Power Diode, 1N4001
NPN Transistor, 2N3904
02
PNP Power Darlington, Motorola 2N6053
R3
A simple, low-cost process current converter has been
shown with wide application in the controls industry. The
Dual Op Amp, PMI OP-14CJ
0.1/LF +SO%/-20% 50V, Type CK-104
01
R1-R2
CONCLUSION
Description
A1
50kO Potentiometer, Bourns
#3006P-1-503
40200 ± 1 %, RN55C4021 F
R4
20kO ±1#, RN55C2002F
R5
SOOO ±0.1%, GR#SE16DSOO
R6
1000 ±0.1 %, GR#SE16D100
APPLICATION NOTE 22
PMI
SOFTWARE CONTROLLED ANALOG TO
DIGITAL CONVERSION USING DAC-OB
AND THE BOBOA MICROPROCESSOR
by Will Ritmanich and Wes Freeman
The microprocessor is generally regarded as a flexible
replacement for discrete logic devices. Yet most micro·
processor-based designs still use numerous isolation and
support packages for analog-to-digital (AID) conversion,
rather than using just software and the processor itself.
There are many applications where the minimum system ap·
proach is both desirable and feasible. This application note
describes a very simple, low·cost method of software con·
trolled 8-bit AID conversion using the Precision Monolithics
DAC-08 and the Intel 8080A. Innovative software eliminates
the need for peripheral isolation devices. Easily expandable
to 10-bit or 12-bit AID conversions, the technique may be
emulated using other microprocessors having separate address and data busses.
8080A 1/0 INTERFACE CONSIDERATIONS
plemented. By utilizing unused portions of memory address
space for 110 operations, the full instruction set used to control memory can also be used to operate on peripherals.
This creates a powerful "new" capability for dealing with
110. The major constraint, however, is that the peripheral
must now conform to memory bus signals and timing.
110 CONTROL USING MEMORY·MAPPING
The convention used in establishing memory· mapped 110 is
to assign address line A15 as the 110 control flag. Thus, if A15
is "zero," then memory is active, and if A15 is "one" then 110
is active. This creates a "map" of the memory as shown in
Figure 2. Although other address lines could be used for the
function, A15 1s normally used because it is easier to control
with software and allows full address capability for the
lower 32k of memory.
In order to communicate with any inputloutput peripheral
device, the 8080A must be able to distinguish between its
normal memory array and that particular 110 peripheral. Two
techniques exist for accomplishing this, each with its own
set of advantages and disadvantages.
The basic approach, used especially in large systems requiring greater than 32k memory, assigns the particular
peripheral to an 110 "Port." This has the effect of isolating
the 110 from the memory bus by the use of additional Interface devices (generally the 8255 Programmable Peripheral
Interface). Data transfers to and from the peripheral are then
enabled by special instructions IN or OUT. This method has
the advantage of allowing full65k memory usage (Figure 1),
but requires additional support circuits. Although concep·
tually simple, it restricts communications to the peripheral
through the 8080A Accumulator.
For simple applications or where the full memoryaddressing capability of the 8080A Is not needed, a powerful technique referred to as "Memory-mapped 110" can be im-
32.
66Jc
Ir------r-I-M-EM-O-RY----,I
l MEMORY
M~r;,EO
0
256
~
L::..J
Figure 2. Memory·Mapped 110
MEMORY·MAPPED 110 CONTROL SIGNALS
In order to manipulate memory·mapped 110, it is necessary
to generate the appropriate control signals. This is accomplished by gating MEMR and MEMW with A15 as shown
in Figure 3. System bus characteristics are preserved and
all Instructions normally used to operate on memory can
now be used on 110 as well.
SUCCESSIVE APPROXIMATION AID CONVERSION
.5k
MEMORY
Figure 1_ Isolated 110
o
B
256
Because it provides the best tradeoff between speed and
hardware/software complexity, the successive approxima·
tion method of AID conversion has been selected. Figure 4
shows a simple analogy of this approach based on the use
of a pan balance.
To measure some unknown weight, It Is placed on one pan
of the balance. By successively applying binarily-welghted
PAGE 15-87
•
I
r--"'--~--,-----MEMR MEMO~~
io--...---t----MEMW
SUCCESSive APPROXIMATION REGISTER
DEVICES
8228
SVSTEM
CON-TROL
SERIAL
OUTPUT
I/O R IMMI } MEMORY
MAPPED
I/O
DEVICES
Msa
I/OW(MM)
MSB
Figure 3. 1/0 Control Signal Generation
Lsa
Lsa
VOLTAGE OUTPUT O/A
Figure 5. Basic Successive Approximation Circuit
UNKNOWN
WEIGHT
FULL
~
2
fULL
~
Do
fULL
FULL
~~
c::::::J
=
ETC
BINARY WEIGHTED COUNTERWEIGHTS
Figure 4. Successive Approximations Analogy
counterweights to the other pan until the scale is balanced,
we can ascertain the portion of the unknown weight com·
pared to that of the known full scale weight. The number of
"trials" is made equal to the number of counterweights
available by starting with the heaviest counterweight first,
and either retaining it or rejecting it based on the com·
parison to the unknown. This process is repeated for the
next heaviest and so on until all weights have been tried.
Electrically, this can be simulated by sl'lquential com·
parisons between the output of a digital·ta-analog converter
and some unknown analog input. Figure 5 shows the basic
circuit cpflfiguration.
At the start of a conversion, the most significant bit (MSB)
of the DAC is turned on by the Successive Approximation
Register (SAR) producing an output from the DAC equal to
one·halffull scale. The DAC's output Is compared to the
analog input by a comparator, and if the DAC output is
greater than the unknown input voltage, the MSB is turned
off. If, however, the DAC output .is less than the unknown In·
put, the MSB is allowed to remain on, and the next most
significant bit is tried. Whether or not this second bit should
remain on or be turned off is subject to the same criteria as
before (Figure 6). This basic procedure is used to test all remaining DAC bit inputs.
110
Figure 6. Flow Diagram for 3-Blt Successive
Approximation AID Conversion
LOGIC REPLACEMENT BY THE 8080A
The circuit illustrated in Figure 5 can be simplified by utilizing the logic capability of the 8080A to replace the SAR. The
eight lowest order address bits control the data bit iriputs to
the DAC'()8 (Figure 7). Table 1 contains the software used to
accomplish this. Figure 8 depicts the corresponding flow
diagram.
PAGE 15-88
M3
M'
51u
51U
8,
510n
510n
M2
,---JVIII.--1 S ,A
88
1---"N1r--,
DEMUX
MUX
+
+
DECODE
DECODE
>-----<>-------1 IN
VIN
S,
S4A
OUT
83A
1----.-----1
DIGITAL
DIGITAL
lku
RL
510U
J
eL
o TO +3V
300mV
'51G
RM8
felK
KROHN-HITE
WAVETEK
MODEL 143
SQUARE WAVE
GENERATOR
MODEL 4200A
SINE WAVE
GENERATOR
M'
VARIABLE
DELAV
M.
HP-358OA
ClKD
IN
SPECTRUM
CIRCUIT
ANALYZER
M7
M8
Figure 9. Dynamic Crosstalk Measuring System
CHANNEL 1
REa = 1150H
VIN
0-----11---.---.---.---0 VOUT
O.13pF
fSIG = 40kHz
RON
RL
CL
32412
S.6k!!
18pF
CHANNEL 2
I
CHANNEL 1
L:
ADDRESS
CLOCK
OCT'" 89dB
OPEN
OPEN
NOTE: SWI is a time dependent switch. Its characteristic is shown in
Figure 10e.
III
1&1
a. TYPICAL DYNAMIC CROSSTALK ELEMENT VALUES
O
Z
Z
t-
SYSTEM DYNAMIC CROSSTALK
'SIG
'eLK
RL
REO
Hz
HZ
{I
{I
10K
10K
10K
10K
10K
lOOK
lOOK
lOOK
lOOK
lOOK
10K
22K
33K
47K
lOOK
1718
3463
5059
7090
14.78K
OCT
OCT
(C EO =0.13pF) (CEO = 0.5pF)
dB
dB
97.1
85.4
91.0
79.3
87.7
76.0
84.7
73.0
78.4
66.7
o
T=5JLsec
TBRK = 725nsec
REQ = 10890
~
(.)
:::i
T .. Period of Address Clock
T BRK" Break-Before-Make Time
I! RL~ RON, REQ
RON(T -2T BRK( + 2RLT BRKi
T
c_
b.
Figure 10. Computed Dynamic Crosstalk for Actual Multiplexer
The numbers shown in Figure 10 apply to the measurement
system, but are unlikely in a real multiplexer. To satisfy
sampling theory limitations, f SIG must be less than one-hal!
the sampling frequency. Assuming fCLK = 200kHz then each
channel in a multiplexer is addressed for 5JLsec. This means
that it takes 40JLSec to sample all channels of an eight channel multiplexer. In other words, each channel is sampled at
a 25kHz rate. Thus the maximum value of f SIG would be
12.5kHz. Figure 10b gives values of dynamic crosstalk (OCT)
which would be experienced if the values of RON and T BRK
shown in Figures 10a and 10b were used. The first OCT column lists the values for a CEQ of 0.13pF (measured value of
channel three). The second OCT column shows the perfor-
mance for CEQ = 0.5pF. The purpose for the second column
is to point out how critical minimizing stray capacitance is
to good crosstalk performance.
MEASUREMENT OF ADJACENT CHANNEL
CROSSTALK
The system shown in Figure 11 was used to measure adjacent channel crosstalk (ACCT). Ml drives the address lines
of the MUX system and the gating input of M 4. By setting the
period of M4 (T2l to 10JLSec, the pulse rate out of M4 is controlled by the pulse rate of Ml (40JLSec) coming into the gate
input of M4. The output of M4 is in the complement mode
PAGE 15-153
t
c
•
v
ANALOG IN
M,
M2
HP-8(J12B
GATING&:
MUX DRIVING
MUX
SVSTEM
JL
OUT
DRAIN
INORMAL}
SETTING:
T 1 = 4Op.SEC
P1 • StlSEC
SlH
DRIVING
LJ
HP-358OA
SPECTRUM
ANALYZER
INTECH
A·sal S/H
CONTROL
M.
a. VOLTAGE DECAY ON MUX OUTPUT
IN
(COMPLEMENT)
OUT
ANALOG
I
~
HP·80128
5
OUT
I----
IN
IN
SETTING:
T2= l~SEC
P2: 41SEC
TIMING:
ACTIVE CHANNEL
ADDRESS
----1
+1
"
GROUND CHANNEL
·2
r-r...-...,Ir-_--.:;H:::;OL=D___
b. SAMPLE/HOLD
~1Ej
EQUATIONS:
1. -Vo .. N = N H(T1- P21+S1+ S2 ; Where
o
VR
T1
Figure 11. Adjacent Channel Crosstalk Measuring System
because the control input to M3 causes the S/H to HOLD
when the input is high (1). Thus the sample period occurs
during the time P2. M4 also can delay its pulse relative to
the pulse out of M1• thereby allowing measurements of
crosstalk versus t1 (start of the sample time). This informa·
tion is valuable because in many systems, a sample/hold
is used with a successive approximation ADC to encode
the analog output of the MUX. As will be shown, the ACCT
can be made negligible if a sufficient time elapses before
going to the HOLD mode for encoding the data. Since
"time is money," the term "sufficient time" becomes im·
portant.
The nature cif sample/holds and the nature of spectrum
analyzers can cause some apparent discrepancies in the
data observed by this measurement system. It is important
to riote the spectrum analyzer "sees" the average of
everything that is presented to its input terminals. While it is
true the sample/hold holds the last value it "saw," the spec·
trum analyzer also looks at the signal present during the
sample/hold's sample time. Thus the equation which ex·
presses the signal level present as a function of time must
also account for the true averaging of the spectrum ana·
Iyzer. Figure 12 shows the equations (12c) and the defini·
tions of the terms used in the equations (12a and 12b). The
term No is the relative signal level which the spectrum ana·
Iyzer measures. If the model of the signal decay shown in
Figure 12a is the correct one to explain the ACCT, then the
computed value of No should correspond to the measured
values. As will be shown in Figure 14, the agreement does in
fact justify the model; however it was necessary to choose
the measurement conditions very carefully.
- TBRKl
= EXP [ ~ EXP
3.
~: "Sl =
4.
~:=S2= T2
T1
[T
[EXPC1t1) - EXP
EXP
t
BRK-~
-T-2-j' t~ TBRK
C
::RK)]
::RJt - EXP
(TBR;2-t2~
c.
Figure 12. Predicting the Measurement System Response
In order to get good correlation between lab data and
theoretical predictions, it was necessary to use fairly long
time constants (RL = 22kO and CL = 1000pF). With RL = 22kO
and CL = 50pF (RON = 3000), the theoretical plot of ACCT (as
measured on the spectrum analyzer) vs. t1 is shown in
Figure 13. Note that the data is plotted between 900nsec
and 1025nsec. The curve shows that a 10nsec error in'l can
cause a 6dB error in reading on the spectrum analyzer. The
results shown in Figure 14 confirm the necessity of using
large capacitances to obtain predictable results. The theo·
retical curve tracks the actual data well in both cases;
however the 1000pF curve is better than the 300pF curve.
Notice that there is good agreement both at DC and at 4kHz.
PAGE 15-154
A. Multiplexer-Demultiplexer System:
N H'" 0 Therefore
S, +S2
110
Rt
RON'" 300n
Cl
'" 50pF
100
1
1. N o = - - , Where T, = - - x (No. of Channels)
T,
fClK
'" 22kn
2. S, =
T1
[EXP
(~~,) - EXP (- :~RK)]
90
3.
so
S2=T2
EXp[T~~~t -EXpeB~2-t2)J
Where t, = To (Break-Before-Make Time-of DEMUX)
1
70
..
~
t2= -To
fClK
SLOPE > 0.6d8/n...
B. Multiplexer -
I
Sample/Hold System
S,=S2=P2",O
4. No = NH = EXPG-] t:STBRK
ACCT VS. t1 WITH SMALL CL
Figure 13. Measurement Errors Due To Small CL
= EXpe
~:J EXP [TB:: - J' t ~ TBRK
Where: t = tH (Hold Command for Sample/Hold as
measured from Address Change Time)
At" 22KH
80
Figure 15. Predicting Adjacent Channel Crosstalk
RON = JOD!!
T BRK .. 950nSEC
en
w
t-
O
70
Z
Z
o
so
~
120
u
:;
a;
'"
~
Q.
50
~
100
RL = 33KIl
40
RON'" lOOIl
80
C L '" SOpF
MUX·DEMUX
T 1 = 4O~SEC
T BR K = 95QnSEC
'elK = 200kHz
LEGEND:
0: MEASURED DATA WITH Cl = 300pF
t::..: MEASURED DATA WITH C l '" l000pF
SOliO CURVES ARE THEORETICAL
20
20
MUX_S!H
ACCT VS. SAMPLE TIME (t 1)
Figure 14.
0.'
0.•
1.2
1.•
2.0
t(pSEC)
Agreem~nt
Between Measured and
Computed ACCT
ADJACENT CHANNEL CROSSTALK VS. TIME
FOR MUX-DEMUX AND MUX-S/H SYSTEMS
DEVICE: MUX-08
PREDICTING AND CONTROLLING ADJACENT
CHANNEL CROSSTALK
The equations in Figure 12c can be used to predict how
much adjacent channel crosstalk one might expect in an actual system. An all analog system will follow the MUX with a
Figure 16. Computed ACCT vs Time for MUX-DEMUX
and MUX-S/H Systems
PAGE 15-155
•
demultiplexer, which will have its own break-before-make
delay. An analog to digital system will have a sample/hold
amplifier in front of the AID converter. Since the equations
which apply to these situations are different, they will be
discussed separately. Figure 15 summarizes the conditions
and the equations which apply to them.
Since there is no held voltage, then NH = 0 in the multiplexer-demultiplexer system. This reduces No to the simple
form shown in equation (1). Sl and S2 follow in equations (2)
and (3). Since t1 = T D (break·belore-make time of the DEMUX),
that time will have a significant effect on ACCT. The MUX·
sample/hold system imposes the condition S1 = S2 = P2 = 0;
thus No = N H. It will be instructive to compare the levels of
ACCT in these two systems versus their appropriate times.
Figure 16 looks at a "typical" system which will give approximately one percent transmission error (33kU RL and 3000
RON), and has 50pF CL. The value of CL is somewhat on the
high side (20pF being typical for MUX-OB connected to a buffer amp), but it does give a conservative value .lor. analysis.
What Figure 16 shows is rather startling. The adjacent chan·
nel crosstalk, while Inherent in the multiplexer itself, can be
eliminated in both systems by the proper timing. In the case
of the sample/hold it is only necessary to delay the hold
command for approximately 1.2!,sec to have the ACCT
vanish completely. This is no problem, since most sample/
holds need at least 2!,sec to accurately acquire the signal
(this is particularly true of monolithic devices). The plot for
the MUX-DEMUX system relates to TD, which is not adjustable for a given DEMUX. What is possible is to add some
delay to the address change for the DEMUX. In this way, the
DEMUX will not "look" at the MUX output until the charge
from the previous channel has had a chance to dissipate.
CONCLUSION
Table II summarizes the forms of crosstalk and lists ways 01
coping with them. Reduction of RON is helpful in all three
cases. While TBRK should be minimized as much as possible,
it is important that no two channels are ON at the same
time. In some cases, T BRK is chosen such that even over
temperature extremes, the break-before-make feature is
maintained. Since all three components of crosstalk are present in a dynamic multiplexer, the "careful circuit board
Table 2. How to Handle Crosstalk
Crosstalk
Component
Variation
with f SIG
Ways to Minimize Effects
Static
6dB/octave
• Minimize RON
• Reduce stray capacitance (CEO>
by careful circuit board layout.
Dynamic
6dB/octave
• Minimize RON
• Minimize fCLK
• Minimize T BRK, but T BRK > 0 Is
needed to prevent shorting
channels together.
• Minimize RL
• Reduce stray capacitance (CEO>
by careful circuit board layout.
Adjacent
Channel
NONE
• Minimize RON
• Minimize fCLK
• Minimize TBRK, but TBRK > 0 is
needed to prevent shorting
channels together.
• Minimize RL and CL
• WAIT before allowing samplel
hold or DEMUX to measure MUX
output.
layout" is important even though it is not listed in the ACCT
section.
This paper has painted out the fact that static crosstalk
(given on multiplexer data sheets) is only one of the three
components of crosstalk. The models for static and dynamic
crosstalk are relatively simple and were discussed to show
how they are related. The most troublesome compo"nent of
crosstalk (adjacent channel crosstalk) was shown not to be
quite so straight-forward. For one thing, adjacent channel
crosstalk (ACCT) is not signal frequency dependent as are
CT and DCT. The mechanism which governs this lorm of
crosstalk is stored charge on the MUX node. While CT and
DCT must be minimized by careful layout and once present
in the multiplexer cannot be reduced, such is not the case
with ACCT. Even though ACCT is present in the multiplexer,
the proper timing of demultiplexer or sample/hold commands
can effectively eliminate ACCT from the total system.
PAGE 15-156
APPLICATION NOTE 36
PMl
OAC-OB CONTROL OF 555 TIMERS
by Kishor Patel
I
INTRODUCTION
{ lOUT volts per second from approximately zero volts to
2 C
3' Vcc of the 555 timer.
This application note describes a digitally or microprocessor controlled one-shot and an astable multivibrator
using two of the industry's most widely used low cost
building blocks, the PMI DAC-08 8 bit DAC and the 555
timer. Digital control ranges of 255 to 1 and 510 to 1 are
shown for one-shot and astable applications allowing
periods of 181'sec to 1.4 seconds and frequencies of 1 Hz to
60 KHz.
The one-shot's period, T, is basically an RC product with
two other control factors. The R is fixed and represented by
RREF which sets up the correct IREF current for the DAC.
With the fixed RREF, the one-shot period is directly proportional to the value of the timing capacitor C (see Table 1).
The other two controlling factors are the DAC's digital
inputs and the ratio of the timer's Vee to the DAC's VREF.
The one-shot period is inversely proportional to the normalized digital input value and directly proportional to the
Vee to VREF ratio as illustrated in Fig. 2. When operated in
the linear mode, a 255 to 1 control range of the one-shot's
period is achieved.
ONE·SHOT LINEAR MODE OPERATION
In the one-shot mode of operation, the time delay or the
one-shot period is determined by a constant current source
and a capacitor. A digitally programmable constant current
source is made using the DAC-08 and two PNP transistors.
The DAC-08 is a current sink; the two PNP transistors are
used as a current mirror which reverses the direction of the
DAC's sink current forming a current source. The current
source charges the timing capacitor, causing the voltage
across the capacitor to increase linearly at the rate of
BASIC DESIGN
As shown in Fig. 1, this design involves a series of conversions from a digital input to an analog current to a
threshold voltage and finally to a time delay or a frequency.
A DAC-08 converts the digital input to an analog current
11z
c
U)
1&1
I-
oZ
z
o
~u
Vee
+t5V
::::i
••
D.
D.
,Kn
...,
11
12
DIGITAL INPUTS
83 84 85 .1 87
C
I lOUT
7.5OK.Q
••SET
Vee
7 DISCHARGE
I,,,
.5.
8 THRESHOLD
CONTROL
2 TRIGGER
GND
RREf1
7.50Kn
~LlNEAR
Ie
VC;JI 0--------------'
ONE-SHOT PERIOD, T
~ 1. R~EFle
3
ONE-SHOT PERIOD, T
lD
~ ~3 RREFe
Vee FOR LINEAR MODE
VREF
Vee
VREF
[2{-
Figure 1, Digitally Controlled One-Shot
PAGE 15·157
D
{IDIJFOR EXPANDED MODE
OUTPUJL:cc
i--T-j
III
Table 1. One-8hot Linear Mode Timing Table
ONE·SHOT PERIOD (msec)
Vcc = 15V
VREF = 15V
VCC = 5V
VREF = 15V
c = O.l/lF
Input Digital Code
11 11 11 11
5.2
0.505
0.049
1.72
0.160
0.0176
00000001
1440
134
13.8
455
43
4.8
which is then converted to a voltage by a two transistor
current source and a capacitor. The voltage Is then con·
verted to a time delay or frequency by a timing capacitor
and the 555 timer.
10,000.0 r-""'E-X-PA-N-DE-D-R-AN~GE-D~A-C""T-'-""
c
= 11'F
Vee" 15V
U
I
VREF'" 15V
~ 1000.0 I?-&....,_-+-~I~E~~ OAe
Vee .. 15V
VREF • 15V
~
~
~
I
ONE-SHOT EXPANDED MODE OPERATION
,.0.0 1--+---1....."""~...""d--+-+--I
Range is doubled to 510 to 1 by operating the DAC in the
expanded range mode with the DAC's lOUT fed forward
from the reference input node of the DAC. Expanded range
mode timing is shown in Table 2 and in the graph of Fig. 2.
1•.•
1.0
ASTABLE MODE OPERATION
L-...L.-.JL..--'--~_~....J.._.L--'
-L..L..!..-LJ.§....A.M.12B.
255
255
255
256
266
255
(LSB) NORMALIZED DIGITAL INPUT
255
FS
An astable multivibrator Is made in a similar fashion In Fig.
3. A DAC·08 and two PNP's form a current source driving
the timing capacitor (C) and a discharge resistor (RB). The
timing capacitor is charged linearly by the current source
and discharged exponentially through RB. Once again, the
256
lof (MSB)
Figure 2. One-Shot Period vs Digital Input
+,..
VREF
IRI!F
0'
,.n
j-
B'
"REf'
Vee
O.
,on
DIGITAL INPUTS
B' B. . . B. B. 17 I I
j'O'"
7.5OkO
Vee
RI!SET
DISCHARGe
- ,.
,.
I All"
O.
...
L..ILIL:
OUTPUT
2 TRIGGER
CONTROL
• THRESHOLD
,
OND
RRI!F1
7.SOKO
~LlNEAR
Ie
I~_'F
FOR LINEAR MODE
FOR EXPANDED MODE
Figure 3. Digitally Controlled Astable Multivibrator
PAGE 15-158
CC
digital DAC input and the ratio of the timer Vccto the DAC's
VREF provide additional control on the multivibrator's frequency. The digital input has directly proportional control
while the Vcc to VREF ratio has an inversely proportional
control of frequency.
Frequency range is not fully 255 to 1 as expected but
approximately 220 to 1, because the discharge time (output
low) of a cycle is invariable for any digital input being determined by the product of RB and C. Frequency is shown in
Table 3 and in Fig. 4. Expanded range operation doubles
frequency range as it did in the one-shot application.
Frequency is shown in Table 4.
10.0 /-.,.j.<'--,jo4h4-l-
1.01?"'+-+-4
~~~~~~15-Ns~:FS
(LSS) NORMALIZED DIGITAL INPUT
lol (MSBI
MICROPROCESSOR CONTROL
Figure 4. Multivibrator Frequency vs Digital Input
Both the one-shot and the astable multivibrator can be
microprocessor controlled. Fig. 5 shows the implementa'
tion of a microprocessor controlled one-shot. The eight bit
latch (74LS377) is used to interface between the data bus
and the DAC. Stable data is latched in by a positive gOing
edge of an address coincident pulse. After the data is latched, a buffered negative gOing address coincident pulse
can be used to trigger the one-shot. The astable multivibrator is implimented similarily except for elimination of
the buffer and the trigger pulses which are not required.
CONCLUSION
Digitally controlled one-shot and astable multivibrator with
a wide range of outputs have been implemented. The oneshot has a 255 to 1 (8 Bit dynamic) time period range and
the astable multivibrator a 220 to 1 frequency range. When
the DAC is operated in the expanded modes, these ranges
are doubled.
Table 2. One-Shot Expanded Mode Timing Table
ONE-SHOT PERIOD (msec)
VCC = 15V
Input Digital Code
11 11 11 11
00000001
UI
W
VCC = 5V
VREF = 15V
l-
VREF = 15V
C = O.lpF
C = O.OlILF
5.2
0.495
0.049
1.72
0.160
0.0176
2900
280
26
970
87
8.4
e
z
z
e
~
u
:::i
a.
~
Table 3. Astable Linear Mode Frequency Table
ASTABLE MULTIVIBRATOR FREQUENCY (Hz)
RB = lkn; VCC = 15V; VREF = 15V
Input Digital Code
RB = lkn; VCC = 5V; VREF = 15V
= O.OlILF
C = llLF
C=O.lILF
14.7
156
4.86
49.8
433
3,279
33,333
717
7,273
60,241
C = lpF
C = O.lILF
00000001
1.49
11 11 11 11
328
C
C = O.OlILF
Table 4. Astable Expanded Mode Frequency Table
ASTABLE MULTIVIBRATOR FREQUENCY (Hz)
RB = lkn; VCC = 15V; VREF = 15V
Input Digital Code
RB = lkn; VCC = 5V; VREF = 10V
C = llLF
C = 0.101LF
C = O.OlILF
C = llLF
00000001
0.74
7.69
79.9
2.42
24.7
11111111
328
3,279
33,333
714
7,299
PAGE 15-159
C = O.lILF
C = O.OlpF
217
60,241
•
.'IV
DATA BUS
Il§
••
••
eLK
14LSS71
ADDRESS
COINCIDENT
PULSE
(DATA LATCN)
V...
vee
'Kn
'Kn
RESET
....
Vee
DISCHARGE
.55
THRESHOLD
..."
VO U T n
-ITI-
CONTROL
2 TRIGGER
GND
+1SY
(-1SV)
"1
I1S
0 - - - - - / ~>-----+-----------'
ADDRESS
COINCIDENT
PULSE
(TRIGGER)
Figure 5. Microprocessor Controlled One·Shot
PAGE 15-160
lL~'F
APPLICATION NOTE 37
PMI
EIGHT CHANNEL CODEC
DEMONSTRATOR
by B. W. Berry
Precision Monoiithics, Inc. has developed a CODEC
demonstrator system in order to show the use of their line of
telecom devices in a shared-channel system. These circuits
provide a working digital transmission system incorporating
eight analog input channels digitally interfacing to eight output channels. The circuit design was completed so that a
single analog printed circuit board could be used either for
encoding eight channels or decoding eight channels. A
single digital timing and interface board is used to provide
system clocks and the parallel digital data bus from transmitter to receiver. All board layouts and schematics are
available from PMI. The design uses pluggable connections
so that, if desired, the encoding portion or the decoding portion of the system can be tested separately. The user need
only provide three voltage supplies (±15VDC, +5VDC), the
appropriate filters and any applicable transmission test
equipment.
HARDWARE
The entire eight-channel system consists of twenty-one integrated circuits mounted on three printed circuit boards.
Two of the boards, as mentioned, are a common layout
which is used for the analog functions of the system. The
analog board used for the encoder (analog-to·digital conv~r
sion) requires the addition of a COMDAC® (DAC-86, 87), a
MUX-88, a SMP-81, a CMP-01, and a REF-02. The other
analog board is used for the decoder (digital-to-analog conversion) with the addition of a DAC-86, MUX-88, REF-02, and
an OP-16. The general schematic and parts' list for the analog
boards is shown in Figures 1 and 2.
The control board is a T2L circuit of twelve devices designed
to provide three basic functions, a) the successive ,approximation register with interface to the DAC-86" b) the clock
for the encode portion of the demonstrator, and c) the digital
II)
V> --~:tt-c-,,- v>
~[
CHANNELS
.,
CHO
CH'
S,
C"'
CH'
CH4
CHS
CHI
v-_-T
___ v_
7
"
"'0
CH7
*"
sa
S,
.¢.
MUX-88
SS
.,
S.
S7
S'
MUX
[
DIGITAL GND.
ANALOG GND.
a.
~
A'
.'0
•
V>
MUXENABLE
SAMPLE PULSE
ENCODE/DECODE
v+
COMOAC
INPUT
,:>'---e10
R2 11
~C8
REF-02
C'.~
IDAC8B/l7
.,
l-::----~
-
BS
B.
87
Figure 1. COMDAC* Encoder/Decoder Analog Circuit Board
·COMDAC IS A REGISTERED TRADEMARK.
o
~
u
:::::i
A'
• .,
t-
Z
Z
AO
ADDRESS
W
O
PAGE 15-161
1---1>
e,.f-C>
VCMP
TRANSMIT
from a programmable read·only memory frequency divider.
The PROM was used to provide flexibility In changing the
clock waveforms if the user so wishes. The resultant clock
waveforms are also described later; the circuit schematic is
shown in Figures 3a and 3b. The PROM data is listed in
Figure 4. The digital interface is provided by using a stan·
dard a·blt, parallel.in, parallel·out latCh updated as the suc·
cesslve approximation process is completed for each Input
channel. The remainder of the circuit consists of t~e SAR
and the multiplexer address counters. A parts list for the clr·
cuit is shown In Figure 5. A complete circuit schematic for
the digital board Is shown In Appendix A.
RECEIVE
(Eight·Channel Encoder)
(Eight·Channel Decoder)
MUX-88
SMP-81FY
COMDACS>oAC-86EX
(87)
MUX-88
COMDACS>oAC-86EX
(87)
OP·16F
REF..Q2
RESISTORS
R1
R2
R3
R4
R5
-
20K
330
9.1K
10K
2.49K
R6 R7 R8 R9 R10 -
2.49K
2.49K
1.5K
2K (POT)
1.0K
The boards are interconnected by use of four mini·dip con·
nectors and cables, a 16·pin and 14-pin from each analog
board to the controller. The lead designations of the two
connectors are shown in Figure 6. The input and output
channels are accessible through "banana"·type plugs; this
allows optional connections from the transmission line in
order to try different types of filters and line interface cir·
cu its. The two analog boards requ ire ± 15VDC and "banana"
plugs are provided to interface to the appropriate supplies.
The control board requires +5VDC only. The entire system
layout is shown in block diagram in Figure 7.
CAPACITORS
0.1"f
C1, C2, C4, C7, C8, C9, C10,
C11, C12, C13, C15, C18, C19
C3, C6, C14, C16
10"f
C5
6000pf
C17
100pf
Figure 2. Parts List - Analog Board
SYSTEM OPERATION AND DESIGN
interface between the encode and decode sections. The en·
coder clock design is a multiple frequency clock, the
usefulness of which is treated in a later section, generated
To achieve a workable system configuration, the encoding
and decoding operations were approached as two separate
designs. The entire transmission link was then connected to
complete the end·ta-end tests.
TO
ENCODE DAC·86
C,
CL~:-------"""
.:.
VCMP
TO CMP·Ol ---<~,r--.
3
Q7 14
c,
06 ",':!.3_
05 12
CE
...el
DO
++++++""15 D'
e,
.....
7 02
Q4 11
02 8
e.
TO
05 17
e.
e.
DAC-8S
(e1)
OB 19
e.
Q7 21
e7
~06
9 03 74119 03
2502 Q3 6
16 04
Q4
5
18 D5
20 D6
HE - - - - 1 '___
22 07
DECODE
CP
·--;:::======-~C).!---..!~ Joo",'D'------i
ADDRESS
CLOCK
AD]
.
'"
+5V
TO
INPUT MUX ADDRESS
C'
2 eLK
OA 14
: DA
Qa 13
1K
DB 74183
S DC
+5V -"y'IIV--t-"I
:
DO
ac
12
.0] OUTPUT
TO
.
A1
~~RESS
co
CRY ,",'..
5 - -....r::)o---op--------....QjLD
._ r +IV
---N.t-L---
TO
INPUT M~: EN.eLE
TO
OUTPUT MUX ENABLE
C4
1--'-'--', ::::OO=--...,..-......:I~.,::..--- ' ....M...
Figure 3A. Encoder/Decode Controller
PAGE 15-162
..v
2 elK
l.544MHz
QA 14
10 ADA
OR 13
••v
74183
r
11 ADa
DO,
ac
12
12
7418M
DO,
ADe
OD 11
DO,
13 ADD
DO.
~
ADE _007
ClR
...
DO,
DO,
CE
..-
,f
... t
P.
4
D,
DA
2
•
• Do
6 DC
4
,.
c.
,.
D8.!!
7 DD 74111
~
~
DC
.
ClK
,
~.
l
r
.,. ...
Q~ f-
cue
7474
ADDRESS CLOCK
QD~ t- t-
~
V
'-:~
3DO
i-----..!
SAMPLE PULSE
.
Q
D
,•
."
6
SAR
CLOCK
4
8
Ii
;---
6
J.!
4
~2
I
11
5
•
Q
r!---
7474
•
8
ClK
4
cc
V
'2 0
ENCODE!
DECODE
fiE
C,
Q
R6T
13
too
'1
z
c
Figure 3B. Encode Clock
II)
III
l-
ADDRESS
DATA
(MSB-LSB)
20
28
20
21
39
2B
23
2B
23
2B
23
2F
00
01
02
03
04
05
06
07
08
09
OA
OB
ADDRESS
DATA
(MSB-LSB)
PIN
#
27
27
2F
6F
67
67
6F
6F
67
67
6E
OE
OC
00
OE
OF
10
11
12
13
14
15
16
17
e
z
Z
e
CONNECTORS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
MSB = 008
LSB = 001
Address 18 - 1 F - Unused.
Figure 4. PROM-Based Clock
C1 (C3)
+5
+5
+5
VCMP
+5Gnd
+5Gnd
+5Gnd
B7 - LSB
B6
B5
B4
B3
B2
B1
SB -MSB
Encode/Decode
C2 (C4)
+5Gnd
Sample Pulse
MUX Enable
AO - Address
+5Gnd
A2 - MUX Address
A1 - MUX Address
+5Gnd
+5Gnd
+5Gnd
+5Gnd
+5Gnd
+5Gnd
+5Gnd
+5Gnd
+5Gnd
·C2 is 14 Pin - C1 is 16 Pin
Figure 6. Pin Designations - System Connectors
PARTS
PARTS
7404
7408
7414
7432
7474
7486
2
Figure 5. Parts LiS1 - Controller
74163
3
74188A
74195
74199
2502
1.544MHz Crystal
The accuracy of the encoder, lIle analog-to-digital converter,
is dependent upon several factors. The first, and most
significant, is the speed (settling time) of the companding
DAC in conjunction with the comparator. Other factors are
switching time of the multiplexer, acquisition time of the
sample-and-hold, hold-step settling time of the sample-andhold, and output noise of the sample-and-hold and
PAGE 15-163
~
(,)
:::i
a.
a.
C
III
MULTIPLEXER
AID
SAR
CLOCK
ANALOG
CHANNELS
IN
SAMPLE ~r-~-----'H-:-::O-:LO------'L-
..
MUX·
E~iccg>DE~ "'L..£!DE~OO:!ED!!.EJ--"ENjC;COOCDiEEiilssi8i.i1,- - - i L CLOCK
INPUT
AD~~~~
MUX
--,L_______~I~~----------
I
3,~s
O,6Sps
I I
......
......
~_ _ _ SAMPLE. E~~:!c1 CHANNEL _____
MULTIPLEXER
Figure 8. Encoder Timing Waveforms
DIGITAL
B-BIT
TO
(
DATA
BUS
1
ANALOG
CHANNELS
OUT
Figure 7. Eight-Channel System Layout
multiplexer. All of these characteristics had to be considered while developing the encoder circuit.
In a companded AID conversion, using a successive approximation method, different digital bits require different settling times. There Is a constant increase in the settling time
required as one goes from the sign bit to the chord bits and
then to the step bits. This increase in settling time is partially
caused by the scaled current sources used to design a companding D/A and Is most affected by the magnitude of the
voltage level being converted. So as the output currents of
the DAC-86 become smaller (at smaller voltage levels), the
comparator is less responsive. Also as the less significant
bits are clocked in, the situation becomes more critical
since progressively smaller current changes are provided to
force the comparator to change output state. The encoder
clock waveforms, shown in Figure 8, depict a system approach to accommodate these timing characteristics. The
governing design criteria was that a limited amount of time
is available to complete the successive approximation of the
analog signal (for eight channels, with a sampling frequency
of 8kHz, this means 15.6J.1S) and the optimum clock must fit
within this period. All functions (including sampling, encoding, switching) must therefore be completed with an acceptable accuracy, within this time constraint. To achieve
accurate data acquisition with the sample-and-hold, a sample pulse of 3.2J.1S was used. Once the pulse goes from sample to hold, there is a waiting time required to allow the
sample-and-hold output to settle to the "held" value, 650ns
is the time added. Since the sign bit is the fastest transition,
the basic system clock (1.544MHz) is used for the first SAR
clock period. The clock frequency is then halved to clock In
the chord bits (B1, B2, B3), the next "slowest" transitions.
Finally, the clock frequency is halved again to allow for the
step bits (B4-B7), a frequency of 386kHz. The times required
for the different bit conversions are shown in Figure 8. The
SAR is reset during the sampling period and once the sample circuit has entered the hold mode, the input
multiplexer's address is changed. This provides ample time
for the MUX to switch to the next analog input with little effect on the adjacent waveforms. In addition, to further
minimize interchannel crosstalk, a 2OkO resistor to ground is
added to the multiplexer output.
To provide sufficient noise immunity from the sample-andhold to the comparator, a simple filtering circuit using a
100pF capacitor is added. A 4.9kO resistor to +5V from the
comparator output aids in increasing the DAC-86 and
comparator speed. In order to test the encoder without adding a decoder, a high-precision voltage source (DC levels)
was used as an input to one or more channels of the AID circuit. The data output (one byte every 15.6J.1S) was sampled
and stored in a logic analyzer. By reviewing the samples for
each channel, and comparing the data from all channels of
the eight channel system, the effects of changes in the
clock on the accuracy of the design could be observed. By
inputting a steady-state value, the data oui would not only
demonstrate the "consistency" of the AID conversion but
also make obvious any adjacent channel effects that were
produced.
The analyzer sampling also presents a method of initializing
the system components. By grounding all inputs and digitally
sampling the data bus output, the zero level can be set so as
to produce an alternating series of data bytes equivalent to 0
volts (10000000 and 00000000).
A similar design approach was used in developing an eightchannel decoder. In this case, the response time of the
DAC-86 and op amp offers little problem since an eightchannel decoder is relatively slow. However, the accuracy of
the devices does become important. The design considerations become, therefore, the nonlinearity of the DAC-86 in
PAGE 15-164
conjunction with the switching time and charge injection of
the multiplexer. The DAC·86 is manufactured to strict
linear specifications, which assures both excellent
decoding linearity and absolute accuracy. The multiplexer is
used both as a switch to demultiplex the output waveforms
and as a holding circuit by adding capacitance to the output
leads. One effect seen In the multiplexer is that as a channel
is switched off, there is a charge injected onto the output
This charge is not normally obvious in a MUX design,
however, when working into a high impedance (such as a
filter) and with capacitors on the source leads (outputs), the
charge can add an offset to the waveform. To minimize the
effect, a large capacitor (0.1I'F or greater) is added. Since the
charge pulse is a short duration signal, the signal on the
larger capacitor will be less affected by the charge than if a
smaller component was used.
SYSTEM TESTS
Once the encoder and decoder were functioning separately,
the entire system was connected with the appropriate interfacing to allow for full·system transmission tests. The
measurements taken were the standard set of PCM specifi·
cations observed in the majority of data sheets for telecom·
munication oriented products. These tests included signal·
to-total distortion, gain tracking, intelligible crosstalk, and
idle channel noise.
There are two different methods of performing the tests. For
the U.S. standards, a sinusoid signal is used as the channel
input and the measurements are taken around the base
(test) frequency. For the European tests, a pseudo-random
or "white" noise source is preferred as the input signal. The
test results discussed here were obtained with the U.S.
testing procedures; similar test results have been achieved
using European test methods.
In terms of a system decoder design, this circuit could be
used for more than eight channels. The op amp and DAC·
86 are both capable of responding to more output channels. An eight-channel system was incorporated to remain
compatible with the analog board that is used in the
demonstrator. In order to decode more channels (>12), the
output capacitance on the demultiplexer would need to be
reduced. The other circuit components would remain the
same.
The test set·up for signal-to-total distortion and gain tracking measurements Is shown in Figure 9. The results are
plotted in Figures 10 and 11. As is seen, each test was per·
formed with both the C-Message Weighting and the 3kHz
Flat response terminating configurations. The results using
the wlaw parts (DAC-86) are represented. In terms of signalto-total distortion, the system exceeds the recommended
standard at all input levels by 2dB or greater. The system is
also well within the recommended gain tracking limits for
both terminations.
The decoding Circuitry can be tested separately by adding a
series of data bytes and monitoring the output channels.
The CCITT recommendation for testing PCM systems includes a method of testing a decoder by introducing a standard sequence of digital data words in order to produce a
1kHz sinusoid at a nominal level of OdBmO.* This method
proved useful in "debugging" the circuit design prior to attempting the end-to-end tests.
I
AID
D/A
TO
DIGITAL
8 BIT
DATA
BUS
(AVERAGE CHANNEL. VALUE)
NOTES:
1.
1.8kHz SAMPLING CONDITIONS AID CONVERSION TIME
15.54jts.
AUDIO TEST ANALYZER CONTAINS AC MESSAGE FILTER
AND 3kHz FLAT FILTER.
Figure 9. Eight-Channel Test Configuration
"Reference -
e
o
z
z
o
~
(J
!
MULTIPLEXER
CROSSTALK . . . • . . . . .
. -75dB
IDLE CHANNEL NOISE . . . . . . 21dBnc
2.
I?z
oC
::::i
MULTIPLEXER
CHANNELS
ANALOG
IN
The crosstalk and idle channel noise measurements are
given in Figure 12. One consideration of the system design,
in terms of performance, was that the most difficult characteristic for a shared-channel system to minimize is the intelligible crosstalk specification. The design is directed
CCITI Sixth Plenaoy Assembly (1976), Orange Book Vol. 111·2
PAGE 15-165
ANALOG
1
CHANNELS
OUT
III
.
IDLE CHANNEL NOISE
!
..
--- -
./
~
--
-
.
NOISE
(dBmO)
CHANNEL
NOISE
(dBmO)
2
3
4
-66.9
-67.6
-67.0
-67.2
5
6
7
8
-62.6
-65.3
-67.0
-61.8
CROSSTALK
FREQUENCY
j. - / '
;;
CHANNEL
V
flLAW
==
300 - 2900Hz
2900 - 3400Hz
~::L:G
INTELLIGIBLE
CROSSTALK
....78dBmO
..-70dBmO
10
Figure 12. Idle Channel Noise and Crosstalk
.
,....
-..
-40
-10
.1.
-1.
development. It should be noted that in terms of transmis·
sion testing, the demonstrator is an erid·to-end system. The
configuration presents the users with a complete circuit
enabling them to observe the individual device characteris·
tics significant in producing a shared·channel design.
INPUT LEVEL (dIimO)
Figure 10. Signal.To·Quantizing Distortion vs. Input Level
The completed eight·channel CODEC demonstrator is shown
in Figure 13, mounted in its carrying case.
....
+1.5
,
I
I
'LAJ-- ~MSGWT~
I
I
I
I
- - - - 3KHz FLAT
+1.0
I
I
I
I
I
I
~,
'\V
~
-~
~
-
P< ~
-0.'
J
-1.0
-1.5
-10
-so
..
-3.
-
-1.
INPUT LEVEL (damO)
Figure 11. Gain Tracking
Figure 13. CODEC Eight·Channel Demonstrator
toward optimizing this measurement. The idle channel noise
is at the system recommended level when measured without output filtering. It is further reduced by adding a PCM
receive filter on the decoder multiplexer.
CONCLUSIONS
The circuitry just discussed is meant to represent one ap·
proach to designing an eight·channel, shared CODEC
system. It is not meant to be the only design, but provides a
working system upon which to base further engineering
The demonstrator provides a starting point from which most
characteristics important to both shared·channel and single·
channel designs can be manipulated to allow for im·
provements in transmission quality. To be able to develop a
realistic transmission design, the system engineer needs to
consider more than just the coder/decoder devices. A com·
plete multiple channel system, such as the PMI eight·
channel demonstrator, allows the user to observe the com·
plete system performance as it is affected by the individual·
system components.
PAGE 15-166
~
"V
m
Z
C
X
l>
TO ENCODE
DAC·86187
(el)
S8~ 82
54
B6'"
B1
83
85
87
TO CMP·Ol
)II!
74195
SAMPLE
I
PULSE
fe2)
TO
SMP-81
QC
~
I I IADDRESS CLOCK
•
:
. • 74'99
G)
,
D4
........
~
05
05
06
DB
07 cp Q7
m
.!.
..,,300
8'
sa]
82
B3
B4
85
.
TO
DECODE
DAC-86/87
(e31
87
~
...,300
At DECODE
"}TO
MUX-88
A2
IC4)
C1, C2 ENCODE BOARD
Cl, C4 DECODE BOARD
Figure A-1. Circuit Schematic
II
APPLICATION NOTES AN-37
APPLICATION NOTE 38
PMI
FOUR·CHANNEL SHARED CODEC
by B. W. Berry
FOUR-CHANNEL SHARED CODEC
A four-channel CODEC assembled from LSI components is
a cost-effective digital transmission system requiring a
relatively small number of devices_ The system makes use
of a single COMDAC®* companded DAC-86 or DAC-87 digitalto-analog converter for both encoding and decoding (see
Figure 1). The timing of the circuitry is compatible with ATT
and CCITT system specifications.
Each channel is sampled at the standard 8kHz rate. With
four channels this allows approximately 31.2,..s to encode
the sampled analog input and to decode the received digital
signal for the same channel. To simplify the timing system
requirements equal amounts of time were allowed for encoding and decoding, thus permitting 15.6,..s for the more
critical encode portion of the cycle. The encode/decode
clocking scheme for this CODEC was incorporated directly
from a successful eight-channel CODEC system which has
been published as PMI Application Note 37. One Qriginal
feature of the four-channel design was the use of dual eightchannel multiplexer ICs to switch the four channels. This
results in a system whose interchannel crosstalk is practically negligible. Crosstalk figures of -85d8 have been
observed. This article describes the design procedure and
reviews the transmission characteristics of the completed
system.
Figure 1_
Four~Channel
CODEC
CIRCUIT DESIGN
The analog circuitry required for a four-channel system is
shown in Figure 2. The circuit uses the same printed circuit
SIH
i[
4.9K
1.
1.SK
MUX·88
J
>-.......
--oVOUT
l00pF
2.49K
+sv
"
ElD
9.4K
AD,
REF·02
AD,
O.1K
I--N>I'-T--N>I'--I REF+
TO.
XI.
\7
I[
fIIl/lf7
01 /1F
10K
20.
IXIR .. HIGH FOR TRANSMIT (ENCODE)I
Figure 2.
COMDAC®
OAe-
0 - - - .. LEAD TO TIMING/CONTROL CIRCUIT
Four·Channel CODEC - Analog Board
·COMDAC® is a registered trademark of Precision Monolithics, Inc.
PAGE 15-168
~
'*
ANALOG GND
DIGITAL GND
card as the transmit or receive sections of the eight·channel
CODEC demonstrator (with the addition of a second
multiplexer). The analog inputs all connect at the input
multiplexer (MUX·88) using alternating inputs, the output
(drain) of the MUX drives the SMp·81 sample·and·hold
device. Once the input level is held, the COMDAC® (DAC·86
or87), in conjunction with the comparator (CMP-01), begins
the analog·to·digital conversion sequence. A successive ap·
proximation encode procedure is used; this generates,
within the allotted conversion time (15.6J
cc
.5YB'K
""Vo.~'K
330
33.
AST
(EID)
ii
~1.S44MHZ
•
01-----'
-*-
LEAD SHOWN ON TIMING DIAGRAM
PROM Based System Clock
again to allow for the step bits (64-67), a frequency of
386KHz. The SAR is reset during the sampling period and
once the sample circuit has entered the hold mode, the input multiplexer'S address is changed. This provides ample
time for the MUX to switch to the next analog input with little effect on the adjacent waveforms.
.AA
CLOCK
SAMPLE
D
" _ _..-_--1 74..
1.544MHz
Figure 4.
fiE
7474
~
ENCODEI
a - IIECODE
ClK
1
EJ4E~~~ '
SAMPLE
L
HOLD
.._D_EC_OD_E.......
L
ENCODE (SBE)
CLOCK
INPUT
MUX
~.6~I'S8C
5.2p5ec
6.5,,5ec
_ - - - - S A M P L E , ENCODE 1 CHANNEL _ _ _ __
15.&"Sec
Figure 5.
Four·Channel CODEC -
Encoder Timing
the fastest transition, the basic system clock (1.544MHz) is
used for the first SAR clock period. The clock frequency Is
then halved to clock in the chord bits (61, 62, 63), the next
"slowest" transitions. Finally, the clock frequency Is halved
USing this timing pattern as the starting point, the original
eight-channel system was converted to a four-channel bidirectional design. The only additional control functions to
be added were the timing Signals needed to switch the
DAC·86 between the encoding and decoding modes, to
operate the output multiplexer, and to select the proper data
inputs for the DAC-86. The QAC·S6 mode select and the
multiplexer address leads, as mentioned previously, are
generated from a single system transmit/receive control
(shown as X/R in Figure 6). The lead is the system monitor of
the mode in which the CODEC Is operating. When active
(logic "1"), the DAC·86 and associated parts are in the encode mode. In the encode mode: the successive approximation register clock is enabled, the encode/decode lead to the
DAC·86 (ElD) is enabled, the data input selector directs
the SAR output back toward the DAC-86 for the feedback
needed in succ~ssive approximation, and the output MUX
connectstheOP-16toagrounded (unused) channel. TheXlR
lead remains at logic "1" until encoding is completed,then
goes to ground (logic "0"), the decode state. To decode a
PAGE 15·170
EID
XlR
ElD'
OUT MUX
ADCLK
*
ADr
ill
K
3
11rD.
+5'
,.
2
ClK
DA
DA
QB
DB
DC
AD1] MUX
13
AD2
ADDRESS
74163
DD
" .......
CRY
'(lD
DATA SELECT
r---------------
,
----
SARCP
•
"
-------------...,
SUCCESSIVE APPROXIMATION REGISTER
-n.
• CP
:L
co
•I"
2
.•
~
111
,
~
121
2502
.BE
~u
7
61
•
• I
D
11
SEl
J
I
2
I
I
I
5
r!---- B8
r--.!!.,.
~ B7
iii
15
I
::T~~~::: !
~ B•
"13
f!--- B.
74157
!1z
CC
II)
-------------------~
Figure 6.
~ B3
,I
1
~
r!--- B2
DATA WORD
• 1
YOUT
B1
74157
11
,
~ SB
~
13
I
I
I
S
1
SEl
1&1
- ------------
bz
LEAD TO ANALOG CIRCUIT
""'*--
ON TIMING DIAGRAM
X/R
SV-EM CONTROL, HIGH FOR TRANSMIT (ENCODE)
Four·Channel CODEC -
DIGITAL DATA BUS
z
o
~u
Control Board
data byte, the DAC·B6 is held in the decode mode (EiD is
low), the output MUX is addressed to an active output port,
and the SAR clock is disabled (this register will hold the last
encoded data word throughout the decode cycle - it is not
cleared until a new input signal is to be encoded). The data
selector is directed to the digital system bus and the
'decoding of the byte on the bus begins. As described, the
address leads of the multiplexers are programmed such
that the input MUX will always be directed toward the next
active channel, once the previous analog sample has been
held. But the output MUX does not connect to an active
channel until the decode cycle begins; during the encode
cycle only unused (grounded) ports are addressed.
cleared until after the decode cycle, an external register is
not necessary to hold the data for the decoding process.
The transmission tests that were completed were the
typical telephone network tests as described in the eight-
INPUT [
MUX
ADDED FOR DEMO CIRCUIT
~::;;:;;:;::~~ ~}l: I
"1-_..L<>o-J
!
L - - - . . J r - - " , C>--~
SYSTEM TESTS
OUTPUT [
The system as configured in the block diagram (Figure 7) is
a complete four-channel CODEC. To perform the transmission tests, it was decided to use a single CODEC circuit and
transmit data in a "Ioopback" configuration. As was mentioned earlier, the only Signal required from an external controller is the XlR lead. This is generated for the test Circuit by
halving the inverted ADCLK lead from the prom-based clock.
The system waveforms that result are shown in Figure 8.
These clock patterns can be correlated to the encode clock
waveforms in Figure 5 by comparing the ADCLK or the StH
leads. Since the successive approximation register is not
MUX
t------'
ADClK o----{>>o,---r®l;ClK
DI----_ XlR
7474
D
Figure 7.
PAGE 15·171
Q
Four·Channel CODEC Layout
Demonstrator
~
~
II
+1.5
SfH
+1.0
ADCLK
II
+0.5
XI"
-
OUTMUX
ADCLK
-0.5
Figure 8.
-1.0
Four·Channel CODEC Timing
Demonstrator
---
..
t?" --. ..-
J
~
-3KHzFLAT
.. - - - - C MSG WTG
-1.5
-50
-40
-30
-20
-10
+10
INPUT LEVEL (dBmO)
-50
Figure 10. Gain Deviation (Four·Channel)
r-----
-45
~--
tZ ~r
-40
... ..
.....
'.
I
-35
~
-30
-25
l
Vii
-20
-50
IDLE CHANNEL NOISE
Channel
1
2
3
4
/1/
INTELLIGIBLE CROSSTALK
V
-40
no channel
had noise
level > 2dBrnc
lin "I
_
3KHzFLAT
.. ---- C MSGWTG
400-3400Hz
Level
s -85dBmO
Figure 11. Transmission Measurements
(Four· Channel)
-30
-20
-10
+10
INPUT LEVEL (dBmO)
Figure 9.
Signal·To·Total Distortion (Four·Channel)
channel application information. The tests include signalto-total distortion, gain tracking, intelligible crosstalk and
idle channel noise. Again the test method used for the first
two tests was based on a sinusoidal input signal, as is common in the AT&T specifications, at a frequency between 400
and 3400Hz using a frequency-selective wave analyser. The
results of all testing are shown In Figures 9 through 11.
It Is of some interest to compare this data with the test
results of the eight-channel CODEC design. In particular,
the idle channel noise and the crosstalk measurements are
improved. This can be partially explained by the different
manipulations of the output multiplexer. This does however,
tend to point to the fact that the output MUX can be a
significant source of noise and cross channel Interference.
Further data is certainly necessary, but these results do
point out an area of concentration for the system designer
wanting to improve system performance.
In terms of signal-to-total distortion and gain tracking, the
four-channel results compare favorably with the eight-
channel data and both systems exceed the AT&T requirements. Overall, the transmission tests point out that
using a Single DAC·86 for four-channel transmitting and
receiving is a realistic approach and can comply with all
" system" standards.
CONCLUSIONS
The testing described in the preceeding pages demonstrates the feasibility of encoding and decoding four channels with a single DAC.~6_· The system has several advantages: 1) a smaller number of devices are required to complete the CODEC function than were necessary for the
eight-channel design, 2) the clock circuitry (prom-based timing generator) is common to all encoders, so on)y a single
such circuit is needed for multiple CODECs. Both of these
factors contribute to reduced printed circuit board area for
multiple transmission channels. The devices needed for a
four-channel CODEC are listed In Figure 12. In terms of
package sizes only one device is larger than sixteen pins
(the DAC 86/87 is 18 pins) and three of the components are
only eight pins. This should make system layout fairly simple and allow relatively dense component packing. If channel monitoring is incorporated, then a single supervision circuit could administer several circuit packs in a system line-
PAGE 15-172
•
•
•
•
•
PARTS (CODEC + CLOCK)
Analog
MUX·88 E(2)
SMP-81 FY
DAC 86 EX
CMP'01 EJ
OP·16 FJ
REF-02 EJ
Digital
• 7404 (2)
• 7408 (2)
7414
7432
7474
• 7486
74157 (2)
• 74163 (2)
74188A
74195
• 2502
+ 1.544M Hz Crystal
up. The number of external leads is reduced in a four·
channel CODEC and the design is easily added to a bus·
structure data switching system.
The price per channel is still less than that being quoted by
single·channel CODEC designers although slightly more
than the eight·channel approach. (See pricing, Figure 13).
The sacrifice made in prlce·per·channel is offset by the
gains in system architecture and board layout offered by a
four·channel shared CODEC. The shared channel CODEC
approach is a viable solution to producing a digital
transmission system. AN-37 shows designs at even lower
per channel cost.
• parts for CODEC
Figure 12. Four·Channel CODEC -
Parts
ENCODE/DECODE
CLOCK
Digital
$ 3.82
$ 4.12
PMI
Total
$19.90
$23.72
$ 4.12
per channel
$ 5.93
NOTE: Pricing Based on 100,000 Parts
Figure 13. Four·Channel CODEC -
$ 1.03
($0.17, when
using clock for
24 channels)
Costs
~
Z
C
II)
...ow
z
z
o
~
CJ
::::i
AA-
C
I
PAGE 15-173
APPLICATION NOTE 39
PMI
COMPANDING DIGITAL·TO·ANALOG
CONVERTER
by Guido Pastorino
(FROM PMI DESIGN REVIEW NOTES -1975)
INTRODUCTION
A companding digital-to-analog converter (DAC) is the key
component in PCM CODEC systems. (CODEC is an acronym
for coder-decoder.) A CODEC performs the coding functions
which consist of an analog-to-digital conversion (ADC) of
the input analog (voice) signal and decoding, which consists
of a digital-to-analog conversion (DAC) of the received
digital input.
The DAC is used for both encoding and decoding; it is in a
feedback loop to generate the ADC furlcliOns. Voice signals
in telephony r~uire a system with a very large dynamic
range. The-dynamic range (DR) of a CODEC is defined as the
ra1ie of the largest resolvable signal to the smallest signal
which can be encoded. The dynamic range of the CODEC is
the same as that of the DAC used in either the decode mode
or in the feedback loop of the successive approximation
type ADC. The dynamic range of a DAC is simply the ratio of
its output for a linear input of one least significant bit (LSB)
to that of the largest, all "1s," input. This ratio is usually expressed in decibels using the equation:
IMAX.
DR=20 IOg10-ILSB
where for a current output DAC IMAX is the output current for
all "1s" input and ILSB is the output current for one LSB input. Using this equation a linear bit DAC can be shown to
resolve a ratio of 2n:1 therefore:
2n
DR=2010g 101
pair whose input amplitude range is divided into steps of unequal widths, such that the width of the quantizing steps increase in proportion to the amplitude of the signal. To
achieve uniform signal to distortion performance a logarithmic transfer function is required. The word compand, (compand is an acronym for compress - expand) was borrowed
from analog systems to describe this non-uniform coding
system where quantizing and coding is such that step size
depends on the input amplitude.
COMPANDING PRINCIPLES
Companding requirements differ for different signal
distributions. As mentioned above, voice signals require
constant SID performance over a wide dynamic range. In
order to accomplish this the distortion must be proportional
to the signal level. This feat is best achieved by the use of a
logarithmic compression law. However, a truly logarithmic
assignment of code words is not physically possible since
this implies an infinite number of codes. Two methods for
generating practical implementations of logarithmic
transfer functions have been derived which have become industry standards. These methods are generally known by
their transfer functions which are called wlaw and A-law
respectively. Both of these transfer functions are normally
implemented with eight-bit non-linear DACs to achieve a
72dB dynamic range. This is the equivalent dynamic range
of a twelve-bit linear DAC. The wlaw and the A-law transfer
functions are described by the following equations:
",6 n
The wide dynamic range requirements of a telephone
system require the equivalent dynamic range of a 12-bit
system or 72dB. However, this system would not be satisfactory for telephone voice transmission because of its excessive bandwidth requirements. With present day T1 type
transmission systems a 64kbits/sec data rate is required to
transmit each voice channel. The use of the linear system
would increase this bit rate to 96kbits/sec. This would provide more accuracy than is needed at the expense of excessive bandwidth.
For voice systems the most important criterion is the signalto-noise ratio. In a PCM system noise is due almost entirely
to quantizing distortion. Thus, a non-linear DAC has a nonlinear transfer characteristic to compress the analog signal
into a digital word and a complementary transfer characteristic to expand the digital words into analog Signals with a
wide dynamic range. For a telephone system a CODEC requires a fairly uniform signal-to-distortion ratio over its entire dynamic range. Achieving this uniform signal-to-distortion
ratio over a wide dynamic range requires the use of nonuniform coding. A non-uniform CODEC is a coder-decoder
1n(1+I'IXI)
w law
y=
A-law
y= 1+1nAIXI
1 +1nA
y=
1n (1 +1')
AIXI
1 +1n A
sgn X
sgn X
sgn X
for-1:sXs +1
for 1/AsXs1
for OsXs1/A
These laws have unique signal-to-distortion characteristics
for each value of I' and A respectively. At present ATT has
settled on a value of I' equal to 255 and CCITT specifications
use a value of A equal to 87.6. Substituting these constants
into the original equation above obtain:
wlaw
Y=O.181n (1 +I'IXI)
A-law
Y=O.181n(1+1nIXIl
Y=O.18 AIXI
sgn X for -1 sXs1
sgnXforllAsIXIs1
sgn X for OslXI = lIA
The wideband (unfiltered) signal-to-distortion ratio over the
useable dynamic range of voice transmissions is shown in
Figure 1. This plot does not represent actual system performance; it is instead, a measure of the distortion which
would be caused by an ideal quantizer.
PAGE 15-174
_ -
-
first two chords on either side of the origin have equal step
sizes, whereas, for the ,..-Iaw function, the second chord
after the origin has a step size which is double that of the
first. For all remaining chords the steps double in size for
each succeeding chord. This applies to both the wlaw and
A-law functions. For the A-law function the four chords
about the origin can be considered as a single segment so
that the A-law characteristic is sometimes referred to as being
a "13-segment" code. The A-law characteristic also differs
from the wlaw characteristic in the manner in which the
transfer function crosses the origin. The X-axis origin for the
,..-Iaw is at "mid-step" while the X-axis origin for the A-law is
coincident with a "riser". This can be understood better
from the "blow-ups" about the origin of Figures 2 and 3.
13-SEGMENT A LAW
- - 16-SEGMENT /01=265
40
-60
-40
-30
-20
INPUT SPEECH POWER RELATIVE
TO FULL LOAD SINUSOID (dB)
Figure 1.
Input Speech Power Relative to Full Load
Sinusoid (dB)
The practical implementation of the two transfer functions
is accomplished by standardized piece-wise linear approximations. The transfer functions are implemented in chords
or segments where the transfer function within anyone
chord is a linear staircase. Each chord has sixteen steps
and the size of the step In each succeeding chord is double
the size of the step in the preceeding chord. There are nor·
mally eight chords numbered zero through seven in both
,..-Iaw and A-law characteristics. For the A-law function the
In order to obtain the best implementations 'of the transfer
function, companded DACs are constructed such that encode and decode functions are offset by one-half step. With
this technique the quantizing band for the encode DAC will
be centered about the decode value. This can be seen in
Figure 4, where the wlaw characteristics about the origin
are shown. (The A-law characteristics would be identical except for the "mid-riser" phenomena at the origin.) As an example suppose that, for Figure 4, an analog input whose
amplitude lies between levels 2 and 4 is being encoded. The
best quantizing code to assign to this entire quantizing
band Is its mean value of 3. Thus the DAC used in the suc-
DIGITAL y
OUTPUT 1+)
ANALOG
INPUT(-)
II
ENCODE TRANSFER CHARACTERISTIC
(AID CONVERSION)
D '" __I!!!J!:t~.i.!n
Ln(1+jot)
jot= 255
BLOW UP ABOUT THE ORIGIN
Figure 2.
!-I-Law Transfer Function
PAGE 15-175
DIGITAL
OUTPUT(+)
1--ANALOG
INPUT(-)
{
0
\
\ 0'
ANALOG
INPUT (+)
",'-'~
.~".
OUTPUT (-)
ENCODE TRANSFER CHARACTERISTIC
(AID CONVERSION)
D = (1+LnIXI) SIGN X
~
FOR
--L
:S IXI:$1
A
D=~SIGNX
1+LnA
FORO:;;IX1:S+
A
= 87.6
BLOW UP ABOUT THE ORIGIN
Figure 3.
A·Law Transfer Function
110
sent the mean values of the quantizing bands which must,
of necessity, be centered about the decoder output values.
The end result Is that a DAC used for decoding must be offset one·half step from the DAC used for encoding. This
situation must exist over the entire range of the CODEC. A
transmission system implemented with companding DACs
is shown in Figure 5.
COMDAC® SYSTEM DESCRIPTION
A block diagram of PMI's companding DAC is shown in
Figure 6. A single current output DAC is used to generate
outputs for either the encode or decode mode of operation.
SUCESSIVE
APPROXIMATION
MUX
101
Figure 4.
tL·Law Encode/Decode Characteristics About
the Origin
MUX
cesslve approximation feedback loop of the encode has out·
put levels which represent the quantizing band edges.
These can be referred to as decision levels. On the other
hand the DAC for the decoder has output levels which repre·
TRANSMITTER
Figure 5.
PAGE 15-176
RECEIVER
Transmission System Implemented with
Companding DAC
STEP
INPUTS
B7 B6 B5 B4
negative switch which directs the output of the current out·
put DAC.
CHORD
INPUTS
B3 B2 B'
sa
v+
V-
Figure 6.
E/D
This output will eventually end up at the positive (IOE+ or
100+) outputs or the negative (IOE- or 100-) outputs depend·
ing on whether the S8 pin is programmed to a binary "1" or
a binary "0". The encode·decode switch ElD determines
whether the DAC output shall be directed to the encode or
decode terminations as shown in Figure 6. In addition, this
same switch introduces the one·half step of offset current
required during encode.
VLe
Equivalent Circuit and Pin Connection Diagram
Each companding DAC can be programmed to operate as
either an encoder or a decoder by properly programming thE!
ElD pin. The encode mode is offset one·half step from the
decode mode by means of the current generator which is
switched in during the encode mode. The reference
amplifier establishes the current reference for the current
output DAC. The sign bit pin (S8) controls the positive-
A better understanding of the COMDAC® circuitry is ob·
tained by reviewing the previously discussed piece-wise
linear approximation of the companding DAC transfer function to the desired wlaw or A·law transfer functions. Each
chord or segment consists of 16 steps numbered from 0 to
15. The size of the steps double in size from one chord to the
next as the number of the chord increases. The chords are
numbered 0 to 7. In order to smooth out the characteristics
during the transition from one chord to the next, the step
current for step 0 of each chord is 1·1/2 times larger than the
current of the highest step of the chord immediately
preceding it. The succeeding 15 steps (steps 1 to 15) are
then two times the size of the steps of this previous chord.
These characteristics can be examined in Figure 7.
To implement the transfer function, the first chord (N = 0)
uses 16 equal steps each of whose size, 10 is 1116 of chord
current source Ico for A·law, or 1/16.5 of current source Ico
'"'?
z
CC
U)
W
I-
A·LAW
o
Z
z
o
,II-LAW
~-r-----.,-IOUT = IPi + Sli
~
CJ
:::i
II.
~
II
lOUT
(DECODE)
,I2I
L ,.__+
'Tor
'·"~'~l
11210
1t
31
ICO" 16 10
IP3;;; Ico + IC, + IC2
lOUT
(DECODE)
'T:·,q··,
I,
= ' •• 6 I,
IPi = PEDESTAL CURRENT SIZE
WHERE i = CHORD NUMBER
o THRU 7
lOUT = IPi + Slj
WHERE S = STEP NUMBER
Ip1 " ICO
DIGITAL INPUT B1 THRU 87
Figure 7.
t'e,
Ii = STEP CURRENT SIZE
ICi = CHORD CURRENT SIZE
DIGITAL INPUT B1 THRU B7
Construction of the Companding DAC Transfer Function
PAGE 15-177
for wlaw. The next chord, N = 1, must begin at Ico + 1.51 0 for
both A-law or wlaw. Another way of saying this is that chord
N = 1 begins 16.5 steps from the origin. In order to accomplish this a pedestal current must be directed toward
the output whose magnitude is equal to Ico + 1.51 0. Chord C2
begins at Ico+ 1.51 0 + IC1 + 1.51 1 and ends at Ico+ 1.51 0 + IC1
+ 1.51 1 + IC2 + 1.51 2 and so forth. This process continues
with pedestal currents for each chord number N described
by the equation:
N-1
IPN=
E
into the chord selector from the step generator is equal to
16.5 step currents (16.0 steps for A·law) where a step current
is equal to the current step caused by changing the least
significant bit in the chord of interest. Note that this
satisfies the requirement of the equation for pedestal current IpN. The step generator has the ability to sum current IE
into the output mode to provide the one·half step offset required when the system is operating in the encode mode.
This one·half step offset current is controlled by the EID pin.
The system is in the encode mode when the E/D pin is biased
to a binary "1".
N-1
(ICI + 1.51;) = 16.5
i=O
E
I;
i=O
DETAILED CIRCUIT DESCRIPTION
note that Ipo = O.
All of the single pole double throw switches in Figure 8 are
constructed of bipolar emitter coupled transistors. One
such switch is shown as an example in Figure 9. When the
A functional diagram of a companding DAC which im·
plements the proper transfer function discussed above is
CONNECT TO Js FOR A·LAW
ENCODE CURRENT
(TO GND FOR ... -LAW I
IS
TO OUTPUT
CURRENT
SWITCH
MATRIX
,----+------
STEP
GENERATOR
leN = 16.5 STEPS IN CHORD N
FOR >I-LAW. 16.0 STEPS FOR
A·LAW
CHORD CURRENT GENERATOR
*
Figure 8. COMDAC®
FOR A·LAW IcO = lel = 1/32 IC6 = 1/32 IREF
FOR .u·LAW ICO = 1/64 IC6 = 1/64 IREF
Companding DAC Functional Diagram
shown in Figure 8, which operates in the following manner:
the reference amplifier sets the bias current for the chord
generator by means of IC7 which is a current mirror whose
output is equal to 2I REF . Next, due to the operation of an
R -2R ladder which is described in a following paragraph,
Ice is made equal to one-half IC7 and is therefore equal to
IREF· IC5 is made equal to one-half Ice and so forth. From IC3
down to Ico a slave ladder is used rather than an R -2R lad·
der but the results are the same. The chord currents double
in size progressing from Ico to IC7 respectively (for A·law
however IC1 Ico). The chord selector is programmed from
the 1 of 8 decoder so that the chord identified by binary
chord number N on leads 9 1 to 9 3 will switch ICN to the step
generator. All other chord currents are switched to the
pedestal selector. The pedestal selector is programmed
from the same 1 of 8 chord decoder such that chords 10 to
IN -1 are switched to the pedestal selector output in order to
generate pedestal current IpN. All other chord currents are
switched to ground so that a pedestal current equal to the
sum of the chord currents from Ico to IC(N -1) will be directed
to the output current switch matrix as IpN. The ICN flowing
--------~r---------v+
-----------:;Jf-------- BIAS
LOGIC
INPUT
,------+--IS
GND
=
BIAS --~.......- - - j - - - - _ + - - -
BIAS
Figure 9.
PAGE 15-178
-------:--JE-----c-------
Double Pole Double Throw Switch Implemented
with Emitter Coupled Transistors
logic input exceeds the logic level bias VLC 0 1 is turned off
and 02 is turned on. In turn 03 is turned off and 04 is turned
on thus effectively switching the current generator, shown
as an example, from the ground to Is. Conversely, lowering
the logic level input below VLC will switch the current from Is
to ground. The VLc Control permits the circuit to interface
with a large range of logic levels.
right sinks one-half the current of the transistor to its immediate left. For the wlaw chord current generator OSB is
simply diode connected such that the chord current for
chord Co is roughly one-half the current of chord C1. For the
A-law chord current generator, however, the collectors of
transistors OSA and OSB are tied together so that Ico is exactly equal to IC1 . The currents flow to the chord current
generator from an array of bipolar single pole double throw
switches labeled "chord selector" in Figure 8. The actual
switches are not shown in this paper.
The chord current generator circuit is shown in Figure 10.
This circuit is the implementation of the chord current
generator previously discussed. 0 0 is forced to operate at
the reference input current IREF and 0 1, with an emitter
resistor one-half the size of the emitter resistor of 0 0, will
then operate at 2I REF . 02 through 0 4 will operate at progressively smaller currents where each transistor operates
at one-half the current of the transistor to its immediate left.
To review this normal R -2R current-ladder function notice
that 04A and 04B operate at equal currents and that the sum
of their currents is equal to that of one transistor with an
emitter resistor equal to R. When the series resistor R is added
to the junction of the emitter resistors of 04A and 04B the
current of 0 3 will be forced to equal the sum of the 04A and
04B currents. Thus 04A current equals one-half the 03 current. Now the current from 04A, 04B and 0 3 must all flow
through the next series resistor R. This current is equal to
twice that of 0 3; therefore it is easy to compute that the O2
current is twice that of the 0 3. The same reasoning may be
used to proceed down the ladder to show that each transistor in the ladder sinks twice the current of the transistor
on its immediate right. The slave ladder consisting of Os
through OSA and OSB continues to halve currents for each
transistor proceeding to the right. However this part of the
chord current generator uses scaled resistors instead of the
R -2R ladder technique. Since 04B sinks constant current
from the slave ladder, and since all the current must flow
through the scaled emitter resistors, then the curent
through each transistor must be inversely proportional to
the size of its emitter resistor. By examination of the slave
ladder it can be seen that each transistor proceeding to the
The Step Current Generator is shown in Figure 11. Again the
single pole double throw switches which connect the step
generator to the output current matrix as shown in the companding DAC functional diagram are not represented. The
step generator is connected to the chord selector which
sinks ICN. Ratioed emitters are used to divide the current.
The largest emitter is 16 times the size of the smallest emitter and therefore sinks 16 times the current. The A-law step
generator differs from the wlaw step generator in that each
chord begins with a riser instead of a step. This also applies
to the origin, therefore one-half step of current flows
(decode mode) even when ihe binary input to the step
generator is "0". Step switches controlled directly by the
binary code connect the appropriate collectors of the step
current generator transistors to the output current matrix.
For both A-law and wlaw devices ICN is one of the pedestal
currents. The difference is that for the A-law device the
pedestal current is equal to 16 steps whereas, for the wlaw,
the pedestal current is equal to 16.5 steps.
'"'?
z
et
NORMALIZED COMPANDING DAC OUTPUTS
It is convenient to generate tables of normalized values
which correspond exactly to the CCITT (Consultive Committee for International Telephone and Telegraph) specifications. The following tables are normalized to the smallest
DAC output which is equivalent to one-half step.
UI
III
I-
o
Z
z
o
~
o
::i
Q.
Q.
et
VREF
~~'2 ___ A.LAW
I IREF
•
_
,.,.LAW
a.S28mA
IC7
IC6
IC5
IC4
IC3
IC2
'C1
1.024
mA
0.512
mA
0.256
mA
0.128
mA
64
,A
32
,A
16.0
,A
B.O
,A
BO
,A
- . - - A·LAW
1.056
mA
0.528
mA
0.264
mA
0.132
mA
56
,A
33
16.5
,A
8.25
,A
8.25
4 - - p,LAW
,A
~
~
~
~
~
~
~
~
as
06
07
ICO
OBA
CURRENTS
,A
OB"
1X
"R
NOTE:
2R
v-
Figure 10. Chord Current Generator Diagram
PAGE 15-179
FOR A·LAW QaB COLLECTOR IS
CONNECTED TO QSA COLLECTOR
AND NOT TO ITS OWN BASE.
II
"M--~--~--------~~--------~~--------~----------~----------~
~·LAW
--
STEP CURRENT GENERATOR
IS
.
TO STEP SWITCHES
•,M------E_--------~~--------_E----------~----------E_----------~
A·LAW STEP CURRENT GENERATOR
Figure 11. A·Law and ~·Law Step Current Generators
~·Law
Normalized Table
C = chord no. (0 through 7)
5 = step no. (0 through 15)
NORMALIZED DECODE OUTPUT (SIGN BIT EXCLUDED) Ic • s =2[2 C (5+ 16.5) -16.5]
~
STEP
0
1
2
3
4
5
6
7
000
001
010
011
100
101
110
111
0
0000
0
33
99
231
495
1023
2079
4191
1
0001
2
37
107
247
527
1087
2207
4447
2
0010
4
41
115
263
559
1151
2335
4703
3
0011
6
45
123
279
591
1215
2463
4959
5215
4
0100
8
49
131
295
623
1279
2591
5
0101
10
53
139
311
655
1343
2719
5471
6
0110
12
57
147
327
687
1407
2847
5727
7
0111
14
61
155
343
719
1471
2975
5983
8
1000
16
65
163
359
751
1535
3103
6239
9
1001
18
69
171
375
783
1599
3231
6495
10
1010
20
73
179
391
815
1663
3359
6751
11
1011
22
77
187
407
847
1727
3487
7007
12
1100
24
81
195
423
679
1791
3615
7263
13
1101
26
85
203
439
911
1855
3743
7519
14
1110
28
89
211
455
943
1919
3871
7775
15
1111
30
93
219
471
975
1983
3999
8031
2
4
8
16
32
84
128
256
STEP SIZE
PAGE 15·180
/l-Law Normalized Tables
NORMALIZED ENCODE LEVEL (SIGN BIT EXCLUDED) Ic ,s=2[2 C (5+ 17)
C = chord no. (0 through 7)
-16.5J
5 = step no. (0 through 15)
o
000
6
001
010
011
100
101
110
111
35
103
239
511
1055
2143
4319
39
111
255
543
1119
2271
4575
5
43
119
271
575
1183
2399
4831
47
127
287
607
1247
2527
5087
0100
9
51
135
303
639
1311
2655
5343
0101
11
55
143
319
671
1375
2783
5599
0110
13
59
151
335
703
1439
2911
5855
0111
15
63
159
351
735
1503
3039
6111
8
1000
17
67
167
367
767
1567
3167
6367
9
1001
19
71
175
363
799
1631
3295
6623
10
1010
21
75
183
399
831
1695
3423
6879
0001
0010
0011
6
11
1011
23
79
191
415
863
1759
3551
7135
12
1100
25
83
199
431
895
1823
3679
7391
13
1101
27
87
207
447
927
1887
3807
7647
14
1110
29
91
215
463
959
1951
3935
7903
15
1111
31
95
223
479
991
2015
4063
8159
4
8
16
32
64
128
256
STEP SIZE
A-Law Normalized Tables
NORMALIZED DECODE OUTPUT (SIGN BIT EXCLUDED)
o
000
o
~
ICS =2 N - 1 (33+2S) For N>O
Ics=2S+1 For N=O
Z
C
3
6
001
010
011
100
101
110
111
0000
33
66
132
264
528
1056
2112
0001
35
70
140
280
560
1120
2240
0010
37
74
148
296
592
1184
2368
2496
0011
39
78
156
312
624
1248
4
0100
41
82
164
328
656
1312
2624
5
0101
11
43
86
172
344
688
1376
2752
0110
13
45
90
180
360
720
1440
2880
0111
15
47
94
188
376
752
1504
3008
1000
17
49
98
196
392
784
1568
3136
1001
19
51
102
204
408
816
1632
3264
10
1010
21
53
106
212
424
848
1696
3392
11
1011
23
55
110
220
440
880
1760
3520
12
1100
25
57
114
228
456
912
1824
3648
13
1101
27
59
118
236
472
944
1888
3776
14
1110
29
61
122
244
488
976
1952
3904
-------------------------------------------------
9
---1~5~-------1-11~1--------3~1--------~6~3--------1-26--------2-5~2------~5-04--------1~00~8-------2~0-16------~4032
STEP SIZE
2
8
16
---------------------------------------------------------------
PAGE 15-181
32
64
128
:a
I-
o
Z
Z
o
~
(J
:::i
a.
~
III
A-Law Normalized Table
ICS=2N-l (34+2S) For N>O
Ics=2S+2 For S=tl
NORMALIZED ENCODE DECISION LEVELS (SIGN BIT EXCLUDED)
o
000
o
0000
0001
2
3
5
6
001
010
011
100
101
110
111
34
68
136
272
544
1088
2176
2304
36
72
144
288
576
1152
0010
6
38
76
152
304
608
1216
2432
0011
8
40
80
160
320
640
1280
2560
0100
10
42
84
168
336
672
1344
2688
0101
12
44
88
176
352
704
1408
2816
0110
14
46
92
184
368
736
1472
2944
--------------------------------------------------------------------------------0111
16
48
96
192
384
768
1536
3072
1000
18
50
100
200
400
800
1600
3200
1001
20
52
104
208
416
832
1664
3328
10
1010
22
54
108
216
432
864
1728
3456
11
1011
24
56
112
224
448
896
1792
3584
12
1100
26
58
116
232
464
928
1856
3712
13
1101
28
60
120
240
480
960
1920
3840
14
1110
30
62
124
248
496
992
1984
3968
15
1111
32
64
128
256
512
1024
2048
·4096
4
8
16
32
64
128
9
2
STEP SIZE
The numbers in these tables are directly proportional to the
Input reference current. However the exact relationship is
somewhat complicated_ A reference current of 528,.A for the
wlaw DAC will produce a step size of O_5,.A thus, for the
wlaw device driven by a reference current of 528,.A, it is only
necessary to multiply all the numbers In the normalized
tables by one-half step or O.25,.A to obtain the output in ,.AThe table tabulated below corresponds to a 528,.A
reference_
Il-Law Current Output Table
IDEAL DECODE OUTPUT CURRENT IN MICROAMPS (SIGN BIT EXCLUDED)
o
2
3
4
5
6
7
010
011
100
101
110
111
8.25
24.75
57.75
123.75
255.75
519.75
1047.75
9.25
26.75
61.75
131.75
271.75
551.75
1111.75
000
001
0000
o
0001
0.5
2
0010
10.25
28.75
65.75
139.75
287.75
583.75
1175.75
3
0011
1.5
11.25
30.75
69.75
147.75
303.75
615.75
1239.75
4
0100
2
12.25
32.75
73.75
155.75
319.75
647.75
1303.75
0101
2.5
13.25
34.75
77.75
163.75
335.75
679.75
1367.75
6
0110
3
14.25
36.75
81.75
171.75
351.75
711.75
1431.75
7
0111
3.5
15.25
36.75
85.75
179.75
367.75
743.75
1495.75
8
1000
4
16.25
40.75
89.75
187.75
383.75
775.75
1559.75
9
1001
4.5
17.25
42.75
93.75
195.75
399.75
807.75
1623.75
1687.75
10
1010
5
18.25
44.75
97.75
203.75
415.75
839.75
11
1011
5.5
19.25
46.75
101.75
211.75
431.75
871.75
1751.75
12
1100
6
20.25
48.75
105.75
219.75
447.75
903.75
1815.75
13
1101
6.5
21.25
50.75
109.75
227.75
.(63.75
935.75
1879.75
14
1110
7
22.25
52.75
113.75
235.75
f9.75
967.75
1943.75
1111
7.5
23.25
54.75
117.75
243.75
495.75
999.75
2007.75
2
4
8
32
64
15
STEP SIZE
.50
·Virtual Oecl810n Level
PAGE 15-182
A similar exercise will yield a corresponding table for the
A-law part. Multiplying all the numbers in the normalized
A-law table, for instance, will produce a table of currents for
a reference input of 512~. A table based on 512~
reference current will have a step size of 1.0~ and is
tabulated in the ,...Iaw current output table.
A-Law Current Output Table
IDEAL DECODE OUTPUT CURRENT IN MICROAMPS (SIGN BIT EXCLUDED)
0
2
3
6
8
9
10
11
12
13
14
15
STEP SIZE
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0
000
0.5
1.5
2.5
3.5
4.5
5.5
6.5
7.5
8.5
9.5
10.5
11.5
12.5
13.5
14.5
15.5
001
16.5
17.5
18.5
19.5
20.5
21.5
22.5
23.5
24.5
25.5
26.5
27.5
28.5
29.5
30.5
31.5
2
010
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
2
011
66
70
74
78
82
86
90
94
98
102
106
110
114
118
122
126
4
100
132
140
148
156
164
172
180
188
196
204
212
220
228
236
244
252
8
101
264
280
286
312
328
344
360
376
392
408
424
440
456
472
488
504
16
6
110
528
560
592
624
656
688
720
752
784
816
848
880
912
944
976
1008
32
111
1056
1120
1184
1248
1312
1376
1440
1504
1568
1632
1696
1760
1824
1868
1952
2016
64
III
1&1
I-
Reviewing the companding DAC functional diagram Figure
8 demonstrates the relationship between step size and IREF'
For a ,...Iaw device leo equals 16.5 chord zero steps and for
an A-law device leo equals 16 chord zero steps. Ice is always
equal to IREF in either system. IC6 Is then equal to 64 times
leo for a ,...Iaw system, and 32 times leo for an A-law system.
The step size can then be related to IREF by the following
equations:
step size
step size
=IREF/64 X 16.5 =IREF/1056 Vt-Iaw)
=IREF/32 X 16 =IREF/512 (A-law)
DAC ACCURACY
Companding DACs must be manufactured to satisfy a unique
set of parameters. The performance of a companded DAC
used for telephony must satisfy the requirements of a communication system on an end-to-end basis. A voice channel
is first encoded by one CODEC then decoded by a second
CODEC such that the system performance can be
measured on an audio-In-audio-out basis. The CODEC performance will be almost completely dominated by the Gain
Tracking requirement.
GAIN TRACKING
Now for a reference current of 528~ the step size for a ,...Iaw
system is 52811056 or 0.5~. For a reference current of
512~ the step size for an A-law system is 512/512 or 1.0~.
These values concur with those used to generate the tables.
In the design of the PMI DAC-87 the biasing resistors were
not scaled to exactly integer values. This was done
deliberately to standardize somewhat on 528~ input
reference current for both A-law and ,...Iaw parts. The performance of the device is not affected, however the actual
scaling Is somewhat complicated and will not be discussed
in this paper.
Finally if encode output tables were desired for current output they could be obtained by scaling to proper step size the
normalized encode tables or adding one-half step to each
value in the decode table, where the step size depends on
the chord number.
Gain Tracking refers to the ability of a system to track Its input power level. The test is normally made with a system
such as that shown in Figure 12.
Gain Tracking Is measured by monitoring the input and output levels In decibels. At an Input level of -10BmO the output Is recorded as the output reference level. For ideal Gain
Tracking, any change (In dB) of the input level must be
matched exactly by the same change in the output level.
COMPLETE CODec
COMPLETE caDec
SYSTEM INCLUDING
SYSTEM INCLUDING
FILTERS
FILTERS
Figure 12_ Gain Tracking or SIN Test
PAGE 15-183
HP
3661A
o
Z
z
o
~u
::::i
8:cc
•
This condition is monitored over all input power levels of interest_ The extent to which these power level changes differ
(again in dB) is a measure of Gain Tracking, also referred to
as gain deviation. The ATTID3 Gain Tracking specification is
show In Figure 13.
dB
+1.0
~
~
+0.6
+0.5
+0.4
g
z
+0.2
~
~
INPUT
LEVEL
-50
z
-0.2
"
-0.4
+.
-1.
-37
dBmO
~
-0.5
-0.6
~
SIGNAL·TO·DISTORTION MEASUREMENTS
-0.8
-1.0
POWER LEVELS
For PCM channel performance measurements, power levels
are characteristically expressed in dBmO. A reference level
of OdBmO is established by referencing to a code in the
digital transmission. The binary code pattern required to
establish a reference level of OdBmO can be found in the
CCITT publications. This pattern is reproduced in the PMI
Telecommunications Handbook for the readers convenience. The constant repetition of these binary numbers at
the normal sampling rate of 8kHz will produce a 1kHz
sinusoid at a OdBmO reference level. Starting with this
definition it can then be shown that a sinusoid whose peak
value is just at the system saturation level (all "1s" PCM
output) will have a power level of 3.14 and 3.17dBmO for
A-law and wlaw respectively.
+0.8
.
and an RMS reading voltmeter at the output. Gain Tracking
masks equivalent to those found in CCITT publications are
shown in Figure 14.
Signal-to-Distortion is a measure of the total distortion a
system will exhibit on an end-to-end basis. As with Gain
Tracking this measurement is normally performed on an
audio-ta-audio basis. A typical setup for measuring Signalto-Distortion is shown in Figure 15. A wideband (3kHz) filter
may be substituted for the C-Message filter shown for some
tests.
~
Figure 13. ATT/D3 Gain Tracking Specification
CCITT publishes two separate specifications for Gain Tracking. The apparatus used for making either of these tests is
basically the same as that used in Figure 13 except that for
the first part of the "method one" test the HP3551A would
be replaced with a suitable white noise source at the input
Figure 16 shows the ATT/D3 specification mask with the
performance of a PMI demonstration COMDAC@ based
shared CODEC system superimposed. This method of measuring Signal-to-Distortion is applicable to either CCITT or
ATT specifications.
dB
+3.0 I---f'~
dB
dB
..
+1.0
+1.0
~
S+0.5
+0.5
z
INPUT
LEVEL
INPUT
0
LEVEL
~
~
~
-0.5
c
'"
INPUT
LEVEL
-0.5
-1.0
(b)
(a)
METHOD 1: WHITE NOISE TEST SIGNAL
~
~
-0.5
"
-1.0
z
!2
+0.5
METHOD 1: SINUSOIDAL TEST SIGNAL
-3.0r--_~
METHOD 2: SINUSOIDAL TEST SIGNAL
Figure 14_ CCIT Gain Tracking Specification
PAGE 15-184
Table 2. Initialize and Load Software for 12·Bit Output Interface
BEGIN
LXI
LXI
LXI
MVI
START
MOV
STA
MOV
STA
MOV
STA
SUI
MOV
JNZ
DCR
DCR
MVI
MOV
JNZ
JMP
B,OFFH
D, OFH
H,8003H
M,7FH
Load Ports A and C in counters Band C.
Loads Port B in counter D
Initial ize PPI
Control Word sets PPI to output mode
A, B
Output MSB's to DAC #1
8000H
A, D
8001H
Output LSB's to DAC #1 and
A, C
Output MSB's to DAC
#2
#2
8002H
11H
C, A
START
B
D
C,OFFH
A, B
START
BEGIN
Decrement LSB's counter
Count down from 16
Decrement DAC #1 MSB counter
Decrement DAC #2 MSB counter
Restore LSB counter
Count down from 256
Start new cycle
P.P.I. PORT DESIGNATIONS FOR 12·BIT INTERFACE
UI
III
PORT A
(PAO thru PAl)
PORT B (PBO thru PBl)
PORT C
(PCO thru PC7)
I-
8 MSB's of DAC #1
8 MSB's of DAC
o
Z
Z
#2
o
4 LSB's of DAC's 1 and 2
5
:::l
Go
Go
ADRFI is the most significant address line and is used here
to select the PPI via the CS pin.
CC
Figure 5. 12·Bit ADC Block Diagram
Once the DAC interface program has initialized all software
counters and the PPI counter data is placed on the data bus
and latched into the PPI and DAC's. The third step in the
software development is to decrement the C register and loop
to START until the counter is at zero. The MSB registers (B
and D) are then decremented. The C counter is counted down
16 times for each single count down in the Band D register
(Table 2). Since the LSB counter starts with 16 and the (2)
MSB counters begin with 256, the total count is therefore: 16
X 256 = 4096 (or 12 Bits). Each output ramps from a to +10
volts in approximately 170 J1sec (at 2 MHz clockrate).
ADC 12·BIT INTERFACE
An ADC interface is vital for entering analog information into
an 8080. Because of its popularity the Successive
Approximation technique is discussed here. Successive
Approximation Conversion (SAC) can be performed with
either hardware or software. The software approach will be
described later.
Although some microprocessors now have ADC's on the chip,
a discrete Analog·to·Digital Function still out·performs on·
board versions in almost every department. Accuracy and
speed, the two crucial parameters in ADC design, lead de·
signers to circuits such as that shown in Figure 5.
To start the conversion a negative going pulse is applied at the
Successive Approximation Register (SAR) by the enable of the
SC gate. A low on ADRFI at the same time that the Memory
Write (MWTC/) line goes low, resets a Flip·Flop (F/F) to start
conversion. The F IF is synchronized by the system clock (re·
fer to Figure 6 and Table 3a).
Since the ADC looks like memory to the J1P it must be
assigned memory locations.
PAGE 15-121
8000H
8001H
8002H
8004H
Start Conversion (SC)
MSB Transfer
LSB Transfer
Conversion Complete (CC)
III
+5V
ClK
Mwrci
MDS
BUS
+5V
SAR 25104
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BITS
BIT 7
BIT 8
BIT 9
BIT 10 o---HI-++-H+H+H----\-----,
5K
II
BIT 12
11 O;::=+1t+t:l:::J:t1=+tt::t===:t==;-l
BIT
0
'--+----lIDAT71
'---+-----jDAT61
L~==:j~==~DAT~
DAT41
L~====t====~DAnl
DAT2I
4-------I-----1DAT11
'-+------~-----lDATOI
, . . - - 7 - - - - - - - - 1 ADRO
Figure 6. Complete 12·Bit Successive Approximation ADC Interface
Table 3A. Load Software for ADS Interface
START
CONVERSION
SITCON
After "start conversion" the /lP waits 20 /lsec for a conversion
complete CC signal. This delay is accomplished by a software
loop seen in Table 3b.
The software delay monitors the LSB data bus line which
becomes active when CC goes low signifying end of conver·
sian. The system clock period is about 1.6 /lsec. Therefore,
a 12·Bit conversion takes:
1.6/lsec X 12 = 19.2/lsec
LXI
MOV
H, 8000H
M,A
Start Conversion
Load Start Address
The use of an interrupt would be more efficient because the
/lP would not have to "Poll" or "Wait" for the CC signal.
However, interrupts can cause confusion and will not be
described at this time. After conversion is complete, the digital
result is stored in register pair Band C (Figure 7).
The ADC timing diagram (Figure 8) shows 12 clock cycles
starting on the first positive edge after SC comes up. Notice
PAGE 15-122
Table 3B. 20tlsec Software Delay
DELAY
LXI
MOV
ANA
JPO
H,8004H
A,M
A
DELAY
Load address
Check CC
Set parity
Jump to delay if CC high
Table 3C. Storage of 12-Bit Input Data
t
LXI
MOV
LXI
MOV
HLT
Load MSB Address
MSB to B Register
Load LSB Address
LSB to C Register
Halt
plications, in many instances, require multiple sensing of ana·
log signals, the need for the Data Acquisition System (DAS)
becomes very important. The DAS can be broken into five
elements. (Refer to Figure 9.)
1>101.1 0 "'01.1 0 1 Ixlxlxlxl·lol·lol
B register
H,8001H
B, M
H,8002H
C,M
C Register
Figure 7. 12 Bits Stored in Two Registers
the SOD data out waveform is low for the five MSB's and
l1igh for the seven LSB's. This hex number 7F corresponds
to an analog output of 310 mV.
DATA ACQUISITION 8-CHANNEL, 8-BIT INTERFACE
This discussion, so far, has progressed from a simple DAC
building block, to a DAC in an ADC. Now the DAC will be
described in a mUlti-input configuration_ Since industrial ap-
TRACE 1
CLOCK
TRACE 2
SC START CONVERSION
TRACE 3
CC CONVERSION COMPLETE
TRACE 4
SDO SERIAL DATA OUT
Basically, the tlP sends out four signals: (1) to select a chan·
nel in the Multiplexer, (2) select voltage range in the Amplifier, (3) a hold or sample command to the Sample/Hold, (4)
and a start conversion command to the ADC.
A unique type of Analog-to-Digital Conversion, using a software SAR technique, is illustrated in Figure 10. Many applications do not require very fast conversion times and for that
reason choosing software SAR, in place of a hardware SAR,
reduces system cost. This design with DAC, MUX, S/H and
SMP sells for less than $20 (excluding digital components).
Figure 8. 12-Bit ADC Interface Timing Diagram
PAGE 15-123
•
Store Data
In Memory
Loc.20012008
Address
MUX Channel
Select 1
018
Hold Input
and perform
software
SAC.
Figure 9_ Block Diagram for Data Acquisition
Figure 10. Flow Diagram for Software DAS
ADRFI
ADDRESS
BUS
DATA
BUS
14
ADRDI
ADR6/
ADR71
ADR41
ADR5/
ADR2I
ADR3/
ADROI
ADRll
DAT6/
DAT7f
DAT41
DAT5/
DAT2I
DAT3/
DATUI
DAT1I
CONTROL
BUS
MRDCI
MWTCI
ANALOG INPUTS .
Figure 11. 8-Bit, 8-Chanllel Data Acquisition System with Software ADC
PAGE 15-124
Throughput of a software DAS is approximately 2000 conversions per second (500 Jlsec per conversion).
Table 4. 8-Channel Data Acquisition Program
Register
System Description
Eight analog inputs ranging from 0 to 10 volts are connected
to the Multiplexer (MUX). The MUX is selected by activating
ADRF/. Once the Memory Write MWTC/ goes low, the MUX
address in the JlP accumulator is latched to the 8212 (Figure
11). The analog input selected is fed through the MUX and
sampled by the Sample and Hold Amplifier (S/H). Notice the
deletion of the Programmable Instrumentation Amplifier. If
ranging is required, a simple resistance programmable amplifier
can be used (Figure 12).
BEGIN:
START:
ADCON:
TEST:
10K!!
GAIN=1 + 1o~n
f>------ OUT
TOOHI:
Figure 12. Programmable Gain Amp
A NOP instruction is inserted in the program after the MUX
address selection to hold the processor for 2 Jlsec during the
MUX settling time (refer to Table 4). Acquisition time of the
S/H is 3.5 Jlsec and th is delay is provided by the software
during addressing. The analog signal is held while the program
goes to ADCON (or the start of conversion). Registers Band
C combine to act as a SAR during the software ADC portion
of the program."
Since the DAC-03's settling time is 1.5 Jlsec, the address bus
must stay active (low) for this time. This circuit operates off
the MDS Internal Acknowledge Signal. For faster throughputs a 2 Jlsec delay, once MRDC/ goes low, should be executed at the XACK/ (MDS Acknowledge) pin.
Register D stores the MUX address in the S/H Sample Mode,
while the E register simply contains the Hold Command and
MUX address. Both registers are decremented from eight to
zero. Channel S7 is converted first and the Digital Data stored
in Memory Location 2008. The program loops around eight
times. Each time the JNZ START instruction tests the MUX
counter for zero. After eight channels have been converted
and stored, the program halts. This results in channels S8
through 51 being stored in Memory Locations 2008 through
2001 respectively.
HIGH SPEED 8-CHANNEL, 12-BIT DAS
Applications requiring fast throughputs such as a High-Speed
Data Acquisition system, must resort to the hardware SAR
in place of software SAR. Though throughputs as high as
50,000 channels per second are possible, 15,000 channels per
second (to 12-Bit accuracy) is more realistic when processor
time is included.
**For more information on software controlled ADC, please see
Appendix II and contact Precision Monolithics for Application Note
AN-22.
B = SAR TRIAL
C = TEMPORARY SAR RESULT
D = MUX ADDRESS COUNTER IN SAMPMODE
E
MUX ADDRESS COUNTER IN HOLDMODE
LXI
LXI
MOV
MOV
NOP
MOV
MOV
LXI
MOV
MOV
ORA
CMA
MOV
MOV
CMA
ANA
JPO
MOV
ORA
MOV
MOV
RAR
MOV
JNC
LXI
MOV
MOV
DCR
DCR
MOV
JNZ
HLT
D,lBOBH
H,BOOOH
A,D
M,A
A,E
M,A
B,BOOOH
A,B
H,A
C
Load StH MUX Counter.
Set Memory Map.
Ready MUX Addre•••
Address MUX in Sample Mode.
Wait for MUX to Settle.
Addre•• MUX in Hold Mode.
Hold Input.
L,A
A,M
A
TOOHI
A,B
C
C,A
A,B
B,A
TEST
H,2000H
L,E
M,C
D
E
A,E
START
< ADC Conversion
Initialize Data Storage
Decrement Sample Counter.
Decrement Hold Counter.
II)
w
l-
As in the previous DAS, this system (Figure 13) utilizes a
preciSion MUX, SIH, DAC, comparator and digital components. For simplicity purposes, only an 8-channel system will
be described. This system is expandable to 40 channels using
five MUX-08's or to 64 channels using four MUX-16's. Further
expansion is possible by inserting a 1 of 8 decoder between
the latch and MUX as seen in Figure 14.
Since emphasis is on speed, consistent with 1 LSB accuracy
and 1/2 LSB linearity, the software has only 21 instructions
consuming 37 bytes of memory. It takes 83 Jlsec to complete
initialization, single-channel conversion and data storage in
memory (see Table 5).
SYSTEM SOFTWARE AND HARDWARE DESCRIPTION
Again, the MUX is addressed and an analog channel selected.
The analog signal is held by the S/H and sent to a 12-Bit ADC
for conversion. The label BEGIN starts initialization, setting
the D/E register pair and the Stack Pointer (SP). START
addresses the MUX and 5tH. Start conversion (STCON) in sofware) begins with a low at SC then loops in DELAY waiting
for conversion complete CC. The instruction LH LD 8001
loads both Hand L Registers with the 2-byte ADC word.
This word is pushed onto the stack by the instruction PUSH H.
MUX counters D and E are then decremented and the program loops back to START for the next analog channel. Eight
channels are stored in Memory at locations 2000 through
200F (see Figure 15).
PAGE 15-125
e
z
z
e
~
u
:::i
A.
~
III
MDS BUS
-12V
+5V
+5V
DATA
BUS OUT
elK
(MSS)
BIT 1
81T2
BIT.
BIT.
BIT 5
BIT 0
BIT 7
BIT 0
BIT.
TRI-
STATE
Buffers
BIT 10
BIT 11
BJT 12 ' - - - - - - ,
CClK
ADR"
ANALOG INPUT
ADDRESS
BUS
ADRBI
Figure 13A.
ADROI
~.OO5"1
MWTCI
DATA
BUS
IN
m
~
m
Ul
:Ii
DDRES
BUS
ENll EN21 ANG.IN
BIT 12
ADRFI
SCI
SEE
FIG.I3a
ClK IN
ADR21
MRDCI
BIT 1
CCI
CClK
12 BIT ADC
WI TRI/STATE
OUTPUTS
+5V
Figure 13. Complete. 12-Bit. 8-Channel High·Speed Data Acquisition System
128
CHANNElS_
Figure 14. Expanding to 128 Channels
The MUX channel is latched until the 8tH Amplifier has stored
the input signal on a Hold Capacitor (see Figure 16). This
diagram shows three channels with 88 and 86 at +5 volts
and 87 at ground.
Figure 15. Memory Map
PAGE 15-128
TRACE 1
MUX ADDRESS AO
TRACE 2
SAMPLE "O"/HOLD "'"
TRACE 3
START CONVERSION SC
TRACE 4
SERIAL OUT SDO
Figure 16. Timing Diagram for High·Speed 12·Bit DAS Showing Three Channels
hardware versus software trade·off is critical because software
development generally costs at least $10 per line of code. Of
course, large production quantities can amortize software costs
over a high volume of units.
Table 5. Program for 12·Bit, a·Channel DAS
BEGIN:
START:
STCON:
ORG
LXI
LXI
LXI
MOV
MOV
NOP
MOV
MOV
LXI
MOV
DELAY:
LXI
MOV
ANA
JPO
LHLO
PUSH
DCR
DCR
MOV
JNZ
HLT
1000H
D.l80BH
SP.200FH
H.BOOOH
A.D
M.A
A.E
M.A
H. BOO5H
M.A
H. B004H
A.M
A
DELAY
B001H
H
D
E
A.E
START
LOAD MUX COUNTERS
SET STACK POINTER
SET MEMORY MUX ENABLE
READYMUX
ADDRESS MUX AND SAMPLE
WAIT FOR MUX TO SETTLE
ADDRESS MUX AND HOLD
HOLD ANALOG INPUT
ADDRESS START CONVERT
START CONVERSION
WAIT FOR CONV COMPLETE
CHECK CC
SET PARITY
On the other hand, DAC requirements do not have software
trade·offs, but speed is again proportional to cost.
The DAS described here has shown only multiplexed
techniques. However, dedicated ADC·per·channel types can
also be implemented. Though the multiplexed DAS version is
slower, it is also less expensive.
Both the ADC and the DAS, when interfaced to transducers,
should be five to ten times more accurate than the sensor.
Transducers generally range in accuracy from 0.05% to 5%. As
an example, a 12 bit (0.012% or Yo LSB) converter should be
selected for a transducer exhibiting 0.1 % accuracy so as not to
introduce further error in the system.
In conclusion, the D/A converters flexibility in microprocessor
input and output applications was emphasized.
CCl
TRANSFER 2 BYTE DATA
STORE DATA IN STACK
COUNT DOWN SAMPLE COUNTER
COUNT DOWN HOLD COUNTER
TEST B CHANNE LS
START NEXT CHANNEL
CONCLUSION
The interface circuits discussed herein were designed around
the 8080 Microbus and MDS (also Single 80ard Computer SBC
80/10) bus. Memory Mapping was used exclusively to increase
software speed and add flexi bil ity to I/O control operations.
Many designers are under the impression that in Data
Converters speed is the sole figure of merit. But the
Speed·versus·Cost Trade·Off must be considered. Speed is
directly proportional to cost. The software SAR technique has
speed advantages over Integrating, Voltage·to·Frequency and
Tracking types of ADC, but prices are generally higher. The
BIBLIOGRAPHY
1.
"MCS·80 User's Manual", Intel Corporation, 10/77.
2.
AN·22, "Software Controlled Analog to Digital Con·
version Using DAC·08 and the 8080A Microprocessor"
Precision Monolithics, Inc., 1n7.
3.
"Intellec Microcomputer Development System, Hard·
ware Reference Manual", Intel Corporation, 1976.
PAGE 15-127
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oz
z
o
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u
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IL
IL
•
c(
APPENDIX I
There are many bus structures in use today. In the interest
of brevity and clarity only Intel's Microbus and Intellec MDS
or SBC 80 (also called MULTIBUS) will be described here.
Both the Microbus and MU L TI BUS structures are divided into
address, data and control. The MUL TlBUS, however, utilizes
inverted buffers throughout fo; ease of interface. On the
MULTIBUS, many extras are found in the control section to
provide "Handshake" functions. Eight lines of priority inter·
rupts are also added features that distinguish the MUL TlBUS.
In reality the Microbus is internal to a MUL TIBUS system.
Conversely, the Microbus can be expanded to duplicate the
MUL TIBUS if required. The following table and figure fur·
ther show these differences.
PIN ASSIGNMENT FOR SSC AND MDS INTELLEC BUS
PIN
MNEMONIC
DESCRIPTION
PIN
MNEMONIC
DESCRIPTION
POWER
SUPPLIES
1
3
5
7
9
11
GND
VCC
VCC
VDD
VXI
GND
Signal GND
+5 VDC
+5VDC
+12 VDC
Supply Spare 1
Signal GND
2
4
6
8
10
12
GND
VCC
VCe
VDD
VXI
GND
Signal GND
+!"VDC
+5VDC
+12 VDC
Supply Spare 1
Signal GND
BUS
CONTROLS
13
15
17
19
21
23
BCLK/
BPRN/
BUSY/
MRDC/
10RC/
XACK/
Bus Clock
Bus Pri. In
Bus Busy
Mem Read Cmd
I/O Read Cmd
XFER Acknow
14
16
18
20
22
24
26
INIT/
BPRO/
BREQ/
MWTC/
10WC/
INHI/
INH2/
Initialize
Bus Pri. Out
Bus Request
Mem Write Cmd
I/O Write Cmd
Inhibit 1 disable RAM
Inhibit 2 disable PROM or ROM
AACK/
Special
SPARES
25
27
29
31
33
CCLK/
INTR/
Constant Clock
Direct Int
26
28
30
32
34
35
37
39
41
INT6/
INT4/
INT2/
INTO/
Parallel
Interrupt
Requests
36
38
40
42
INT7/
INT5/
INT3/
INTI/
Parallel
Interrupt
Requests
43
45
47
49
51
53
55
57
ADRE/
ADRC/
ADRA/
ADR8/
ADR6/
ADR4/
ADR2/
ADRO/
44
46
48
50
52
ADRF/
ADRD/
ADRB/
ADR9/
ADR7/
ADR5/
ADR3/
ADRI/
59
61
63
65
67
69
71
73
DATE/
DATC/
DATA/
DAT8/
DAT6/
DAT4/
DAT2/
DATO/
75
GND
VBB
VX2
VCC
VCC
GND
INTERRUPTS
ADDRESS
DATA
77
POWER
SUPPLIES
79
81
83
85
Address
Bus
54
56
58
Data
Bus
60
62
64
66
68
70
72
74
Sign~1 GND
-10 VDC
-12 VDC
+5VDC
+5VDC
Signal GND
76
78
80
82
84
86
PAGE 15-128
DATF/
DATD/
DATB/
DAT9/
DAT7/
DAT5/
DAT3/
DAT1/
GND
VBB
VX2
VCC
VCC
GND
Address
Bus
Data
Bus
Signal GND
-10 VDC
-12 VDC
+5VDC
+5VDC
Signal GND
GND
+5V
-5V
+12V
2
Ao
20
25
Ao
A, 26
A2 27
29
A3
A. 30
AS 31
11
2B
A,
A2
A3
A.
A7 33
AS
AS
A7
Ae 34
A8
A.~_
BOBOA
CPU
Ag 35
SYSTEM DMA REO - - - - HOLD
SYSTEM
14
ENABL.E~
INT
--E
11
22
'0
15
2 (TTL)
---!
RDVIN
---2
RESIN
~
+12V
+5V
GND
B224
CLOCK
GENERATOR
DRIVER
----.i
----'i
~
~
23
INTE
A'2
A"
A,.
-,
A,s
2
"2
DO~~
WAIT
0,
~
D2~
READY
12
5
'9 SYNC
RESET
D.
-------.g
----.g
~
+-- -----4
D3+---
1
r
An
A14 39
A,s 36
18
WR
17
DBIN
HOLA 21
15
OSC ~
TANK
A,o
All 40
A13 38
INT. REO.---------"" INT
~D~~r
A.
Al0 1
A12 37
14
41
J
8228/8238
BI·DlRECTIONAL
BUS DRIVER
DS~~
DS~~
o-,rL-
-Ta
+ 5V------;:
22
BUSEN---(
~-- DBo
~-- DB,
f!:!- -- DB.
DB3
~- DB.
~-- DBs
DATA BUS
~--
F , - - DBs
-----------
GND---{!
STATUS STROBE
ADDRESS BUS
SYSTEM
CONTROL
~-- DB7
INTA
24
b-26
-
MEMR
MEMW CONTROL BUS
~ 1I0R
27
1I0W
filz
C
(II
W
Micro·Bus Pinout and Mnemonics
t-
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APPENDIX II
~u
Software controlled Analog·to·Digital Conversion offers a
medium·speed, low·cost way to convert analog signals with
less hardware. This technique applies the Successive Approx·
imation method, whereby the analog input is compared to
an analog output of the D/A converter one bit at a time. The
DAC is programmed by a microporcessor. This j,lP tests the
comparators output each ti me the DAC's output changes.
When the analog input and DAC output are equal, the digital
count at the DAC is stored in memory. The resultant digital
count is then the equivalent analog input (see the software
ADC flow diagram).
:::i
DD-
•
C
Software Controlled A/D Conversion
PAGE 15-129
APPLICATION NOTE 31
PMI
SUCCESSIVE APPROXIMATION REGISTER
DESIGN FOR MULTI·CHANNEL CODEC'S
by Guido Pastorino
INTRODUCTION
This Application Note describes a low cost, high speed
Successive Approximation Register (SAR) design for use
with 24-channel or 32-channel encoders. It is implemented
with standard MSI functions which are available in several
processes: T2L, Low Power Schottky, etc. The functions
are also available in CMOS, although CMOS is only fast
enough to encode 4 channels or less. The system is optimized for use with PMI COMDAC® DAC-86/87 D/A converter in conjunction with the CMP-01 precision voltage
comparator and REF-01 voltage reference. This design of
fers a low-cost alternative to the 2502 LSI SAR by sharing a
common system timing circuit over all the encoders (usually 2 or 3) used in a 24 or 32 channel system.
determined, the EID input is changed to a logic "1", allowing current to flow into IOE{ +) or IOE{ -) depending upon
the sign bit answer.
For positive inputs, current flows into IOE{ +) through Rl ,
and the comparator's output will be entered as the answer
for each successive decision. For negative inputs current
flows into IOE{ - ) through R2, developing a negative voltage
which is compared with the analog Input. An exclusive-OR
gate inverts the comparator output during negative trials to
maintain the proper logic coding, all ones for full scale and
all zeros for zero scale. However, the exclusive-OR gate
must not invert the signal during the sign bit decision,
hence the need for the second exclusive-OR gate and the
additional D flip flop in the 2502 LSI SAR encoder.
First, the traditional encoding procedure using the 2502
LSI SAR is explained. Next, the improved method described here will be discussed and compared with the 2502
method.
The successive removal technique requires the first decision to be made at the code 01111111, sequentially turning
off all bits until all decisions have been made.
TRADITIONAL ENCODING METHOD
Traditional encoding systems begin the encode cycle by
setting the binary input at 01111111. This is because LSI
SARs are not designed to accommodate a DAC that Is implemented in a sign-magnitude configuration.
An encoding sequence begins with the sign bit comparison and decision. During this time the comparator is a
polarity detector only. The Encode/Decode (E/D) input is
held at a logic "0". Therefore, no current flows into the encode outputs, and the comparator is effectively disconnected from the DAC. Once the input polarity has been
IMPROVED ENCODING METHOD
For the sign-magnitude configuration such as the
COMDAC® DAC-86/87 system, the Initial setting of
10111111 performed by the SAR described here allows the
LOCK
± 5V ANALOG INPUT
::t SV ANALOG INPUT
.r
START
'1..
++15V
r-, R'
.b:g
r--
, R'
+15V
1 2.5
-""
(GROUND
FOR
(GROUND
SINGLE·
SINGLE·
FOR
ANALOG TO DIGITAL
CONVERSION LOGIC
ENDED
INPUTS)
PARALLEL
DIGITAL
ENDED
INPUTS)
"~'T~~I~~OUTPUTS~~~RD
SIGN BIT
1
frfi~~§~~
STEP
BITS
} CHORD
SIGN
81TSBIT
STEP
} BITS
YREF
'--------;15;C14flI0~~~B 8, 82 83 84 Bs Be 87
16
17
:~~~:~
DAC-88187
+1DV
R11
18.941Kg
+15V
(RREF)
1001-)
'--iVr,;-;---;;-;--f,,;;-,12
R12
20KQ
-15V
+15Y
-15V
Figure 1. Basic Eight-Channel Encoder
+15Y
Figure 2_ Eight-Channel Encoder Using LSI SAR
PAGE 15-130
ESB
ESB
ESB BUFFERS
~
, .A'
,;,
....
• AS
7404
"
,
7432
~
,
~
~
~
'- ,
,
7430
'-F'
Cc
'-
12
,
.
~ r-
~
"
s
~11
13
1
y,A
aSB
0,
Q,
I •~p
Cp
Q,
Q,
Q,
Q,
Q,
74164
J
7404
\,1'
' .......
•
"
SYSTEM TIMING
(COMMON TO ALL
CHANNEL REGISTERS)
11
~
~
7432
.,
.,'3
ISB
Cp
~B~=+~~====:;======~~====;==+==~==l====;==+===~=J~==~~
o INPUT >
FROM
ENCODER
ARATOR
7474
---'------+
CHANNEL REGISTER
(ONE PER ENCODER)
l?z
c
.SB
.,
., .,
.2
.
,
t/)
1&1
~
o
z
z
o
.7
••
~
Figure 3. Successive Approximation Register
CJ
::::i
a..
DAC to settle for one additional clock cycle and requires
no logic circuitry to prevent the exclusive-OR gate from inverting during the sign bit trial. The theory of operation
follows.
~
r-I 02
I 2.5
The start conversion pulse S occurs just before positivegOing clock edge C as shown on the SAR waveforms. The
74164 shift register will have all outputs at the 1.0 level
so long as the circuit has been operating for eight or more
clock pulses. With S high the OR gate will continue to input a logic one into the shift register on every pulse. With
all inputs at logic one the 7430 eight input NAND gate will
have a zero output, thus the S signal going low will cause
the next clock pulse Cg to clock a zero into the shift
register output aS B which becomes the leading edge of
negative-going pulse ESB. Now one Input lead to the 7430 is
a zero and the output of the NAND gate goes to logic one.
The zero propagates down the shift register appearing on
outputs aSB to a 7 In succession, keeping the NAND gate
output at logic one. Because of the OR gate this logic one
is clocked repeatedly into the shift register outputs from
aSB to a7. The cycle will not repeat if S is not held low for
longer than 8 clock cycles; however, the actual duration of
the S pulse is not Important so long as It does not cause
s
a
L
r-~~~=;=~:)
-:!:-KQ
(GROUND
FOO
TO OTHER
CHANNEL
REGISTERS
SINGLE·
ENDED
INPUTS)
SIGN BIT
~S}CHOOD
I Tl=
BITS
}:r::
1
2 3 4 5
6 7 8
9
ElDSB 8, 82 8384 Bs Be 87
'------~_/IOE(+)
'--------!IOEI-)
100(+)
10D(-)
y-
VREF
+10V
0"
1B.94KQ
DAC-86I81
(AREF)
0"
2OKO
-15V
+15V
Figure 4. Eight-Channel Encoder with Improved Design SAR
PAGE 15-131
•
As ESB goes to zero it resets FF1 and sets FF2 through FF7;
When the circuit is used with the encoder circuit shown
here, ESB is used to keep the DAC in the decode mode for
the duration of ESB' 1'sB , which is logically E + Cp, occurs at
the leading edge of ESB and sets FFsB to SB 1. Thus, on
the first clock edge after S goes low the SAR is set to
10111111. The trailing edge of ESB is used as a clock for
FFsB so that the comparator output, which represents the
signJ!.i.! so long as the DAC is being held in the decode
mode, is clocked into FFsB' The Q output of FFsB becomes
the SB signal which drives the control input of the
exclusive-OR gate.
C1
I
Cp
=
LJ
12
------.U
1'3
------,U
By forcing this signal to a zero during the Sign Bit trial the
exciusive-OR gate is in the proper non-invert mode while
the sign bit is generated. E1 goes low just as ESB goes high.
No 1'1 signal is needed since FF1 was set low during the initial setting. The rising edge of ESB puts the DAC-86/87
back into the encode mode. The DAC internal circuit has
been settling to the X0111111 magnitude output since the
first clock after S went low, so the rising edge of E1 will
clock the most significant bit of the quantized signal into
FF1. The remainder of the conversion proceeds as follows:
1'2 resets FF2 and the rising edge of E2 clocks the second
most significant bit into FF2.1'3 resets FF3 and the rising
edge of E3 clocks t!!e sec~d most significant bit into FF3
and so on through T7 and E7.
LJ
LJ
E4
--------,U
LJ
E5
~,
--------------.U
LJ
E6
~
-------------,U
11
------------,~
u---
ESB BUFFERS
The implementation of this SAR requires a package count
of 4 for the system timing which can then be shared over
3 channel registers, provided the ESB buffers are properly
used to prevent excessive fan-out on the ESB line.
Figure 5. SAR Waveforms
CONCLUSION
the circuit to re-cycle. The S pulse need not be synchronized with the clock. CC stays high for 8 clock cycles.
A low cost, alternative method of successive approximation register design has been shown which is optimized for
use with multi-channel encoders for PCM systems.
PAGE 15-132
Ce
!~~.
P
7432
11
-
8
8
7430n
• ,
8
1211
OSB 3
7404
•
S
,
•
3
ESB
E,
E.
E,
E.
Es
0, •
7404
•
o. •
•
as
03 •
04 10
11
0& 12
Ee
07 13
E,
~
Cp
lOt
7432
±SVAN AlOGINPUT
,,
~
FOR
SINGLE·
ENDED
INPUTS
11
'W7i
..
~.
TSB
6 T2
.~'
3 Y3
'.,o~.
"
11_
.
TO
SECOND
CHANNEL
REGISTER
s~ • •~'
S _
T6
8_
T4
'
T5
TO
THIRD
CHANNEL
REGISTER
3_
T7
ZERO
r--
GROUND
, •
ESB BUFFERS
ADJUST
8
2
-
5
+
3
~
6
-, 4
CMp·01
7,
2
1141486
ESB
Efl 3
D
E,
~#B
20 S Q 13
- -1SV
FFSB
~CP61
ESB
R
+SW<
s.
14
I.
ElD
10Et+)
A'
E,
E.
+
~5V
S
B 0
S
Q 9
FF,
' Cp
20
Q 13
Q
•
FF,
, Cp
S
S
3 6 0 Q 9
DO'
FF.
FFs
, Cp
, Cp
E,
S
20
Ts
T.
I- .,~lO
., ., ••
17
.s
-15V
6
+15V
Figure 6. Improved Eight-Channel Encoder Complete Schematic
PAGE 15-133
::,;
Z
CC
., .,I.
8
VR(+)
VR(-) 12
6'3
T,
11
CAe·86/87
v+
., .,
8_
II)
100<-)
v-
FF,
, CP
R
. T,
••
s.
,Il~.
Q 1
FF,
, CP
t- ., Y, .,1- i .5 i
T,
T.
10D(+)
17
Eo
Es
r+ r-¥- I~ -+ r-?
~
~ 0S
FF.
, CP
i.SB .,
E.
VLe
r
t
.$
w
15z
z
o
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II.
II.
CC
':'
II
APPLICATION NOTE 32
PMI
SINGLE SUPPLY OPERATION
OF PMI MULTIPLEXERS
by Shelby D. Givens
INTRODUCTION
In addition to normal operation (+ /- supplies), the PMI
family of BIFET multiplexers (MUX-08/88, MUX-24, MUX-16,
and MUX-28) performs quite well in single supply systems.
This Application Note explains single supply operation as
it applies to BIFET and CMOS multiplexers. Common requirements are in battery-operated systems and in microprocessor-based, single supply data acquisition systems.
BIFET and CMOS devices are compared for RON variation
versus power supply voltage (Vs), then settling times.
CONNECTIONS FOR SINGLE SUPPLY
OPERATION
volts as a minimum. One important fact will be demonstrated in the performance photos to follow: THE MULTI·
PLEXERS OPERATE LINEARLY WITH SIGNALS LESS
THAN ZERO VOLTS!
BIFET VARIATION OF RON WITH Vs (MUX·08)
Figure 2 shows the test circuit and defines the test com;!itions (MUX"()8). Figure 3 shows the performance of a
MUX-OB driving a 1~n load. The positive voltage should be
1.10V and the negative voltage should be -O.4V. The
reason for the output voltages being less (magnitude) than
the above Is due to the RON of the multiplexer switches.
Curves 1 and 2 show that RON does not vary as Vs varies
from + 5V to + 15V.
Figure 1 shows single supply connections for the entire
PMI BIFET multiplexer family. Each multiplexer handles 0
to +10V signals with a +15V supply. The signal range is conservatively rated to be (Vs-4V) as a maximum, and zero
Vs
V+
vs
-O.4V
EN
Vs
A2
r -.......-+----I A1
$2-87
MUX·08
58
+1.1V
D
MUX-16/86
MUX-28
GROUND
Figure 2. Test Circuit
vs
Vs
13
MUX 08,88
14
=+ 5Y
CURVE 1: Vs
CURVE 2: Vs =
+ 15V
MUX-24
OV
v-
v-
Figure 1. BIFET Multiplexer Single Suppy Connections
Figure 3. BIFET Variation of RON with Vs
PAGE 15-134
CMOS VARIATION OF RON WITH Vs
(508 pin·compatible device)
+ 15V
The CMOS multiplexer (connected as shown in Figure 4)
DOES show a variation in RON as Vs is varied from + 6V to
+ 15V. This is evidenced by the curves shown in Figure 5.
Note that while the positive peak voltages in Figure 3 are
the same for both curves, the peaks differ in Figure 5.
One very important consideration when choosing a multi·
plexer is the non-linearity (or distortion) introduced by the
switch when it is ON. What is important is the CHANGE in
RON which occurs because of external variations such as
power supplies. In particular, the variation in RON shown in
Figure 3 is 148 ohms. The RON at Vs = + 6V is 1000 ohms,
Figure 6. Test Circuit
Vs
V+
EN
51
-O.4V
CMOS
A2
52-57
MUX
"--'--4~-I A1
+ 1.0V
fj~,
AD
:.
r,;:::iii. ~
.
~.
CURVE 1: MUX·08
CURVE 2: CMOS
.
..-
· 1:1. :;;;
~ iii
'/~.
I~
:_ .
++
.
Figure 4. Test Circuit
=
III
;;;;..
III
III
III
i fj :;;;:
I-
~
:~I~
Jlrn
I
= + 15Y
CURVE 1: Vs
CURVE 2: Vs =
:: ~
+ 6Y
!-++
Figure 7. CMOS vs BIFET Settling Time (Unloaded
Output Voltage)
ii=i\1
o
Z
z
o
~
CJ
::i
a.
a.
CC
Ii'
,111
~
...
RL is large enough so that the output voltages will reach
the input voltage levels. Note that MUX-08 does just that,
while the CMOS multiplexer does not reach the final value.
Jfm
Figure 5. CMOS Variation of RON with Vs
while its value at Vs = + 15V is only 852 ohms. A change of
148 ohms represents a 1.48% error if the load resistor is
10,000 ohms. In battery-operated systems (which is what a
lot of single supply applications are), distortion due to
power supply variations is generally not acceptable.
CMOS VS. BIFET - EFFECT OF RON
ON SETTLING TIME
Figure 6 defines the test conditions used for the BIFET and
CMOS multiplexer curves shown in Figure 7. In this case,
The problem is settling time, and occurs because the RON
of the CMOS device is considerably larger than the MUX-08
(852 ohms as opposed to 250 ohms). A final note concerns
the fact that the multiplexers are switching signals at 400
mV below ground with no distortion.
CONCLUSION
The information presented has shown how BIFET multiplexers handle analog inputs in single supply systems,
with RON independent of power supply variations, and with
fast settling time.
PAGE 15-135
III
rMI
APPLICATION NOTE 33
A GUIDE TO HYBRID INTEGRATED
CIRCUIT DESIGN
by Mike Parsin
INTRODUCTION
Conductive Epoxy
This application note is a guide to the design and development of thin and thick film hybrid microcircuits. To aid the
hybrid designer, emphasis is placed on assembly techniques
and general design rules to avoid common design problems.
When attaching die to the substrate, conductive silver-filled
epoxies are excellent choices for precision low drift circuit
applications. PMI recommends Ablebond 36-2, Ablefilm
ECF 550, EPO-TEK H31, or DuPont 5504 epoxies. Cure durations and temperatures are low, generally one hour at
125°C. Assembly temperatures are critical because Beta
degradation and film resistivity change are directly proportional to heat and duration. Film changes can be expected
when temperatures exceeding 3OQ°C are approached
(temperature at which films are heat treated). Heat treat is
very important to film stabilization. Monolithic dice are
susceptible to temperature, as previously mentioned. The
degree of susceptibility is dependent on lot and the
manufacturer's process. Common parameters affected
because of temperatures are gain, input offset voltage, and
input bias current.
The importance of choosing the proper assembly method,
for a particular application, is discussed. Assembly techniques include substrate and die attach methods, wire bond
alternative, and sealing practices. Common design pitfalls
associated with dice, films, conductors, and layout are also
discussed.
ASSEMBLY PROCEDURE
Hybrid assembly is divided into four steps:
1. Substrate attachment to the package.
2. Die attachment to the package.
3. Wire bonding die to substrate.
WIRE BONDING ALTERNATIVES
4. Package sealing.
There are four methods used in attaching die metalization
to the substrate conductor or package beam:
Correct selection of the methods used for the steps above is
essential for cost effectiveness, and, in some cases, proper
circuit operation. Although these operations may not seem
important on the surface, methods must be chosen to provide the required quality and meet the specifications.
1. Chip and Wire (most common)
2. Flip Chip Beam Tape
3. Beam Lead
4. Chip Carrier
ATIACHMENT PROCEDURES
Chip and Wire
Eutectic Attach
Eutectic-alloy bond is the method used by PMI for standard
IC products because it is more cost effective than epoxy. It
is a metal attach which is accomplished by heating the substrate and die until a "wetting" action takes place. The die
is then placed in contact with the substrate. This results in
an excellent shear strength attachment. Gold backing is
recommended for hybrid construction.
Both substrate to package and die to substrate attachment
can be performed by the eutectic method. Although less expenSive, this metal attach requires temperatures in excess
of 300°C to wet the gold for proper attachment. Eutectic
type of bonding is generally recommended for digital applications or low component count hybrid packaging.
Chip and wire is the most common method of bonding the
die to an electrical conductor (see Figure 1). Types of wire
bonders include thermocompression, thermosonic and
ultrasonic. Thermocompression bonding is fast, and usually
gold wire is used. Cutting through the oxide on the metalization is sometimes a problem though. Ultrasonic wire bonding solves the oxide problem by a scrubbing action that cuts
through it. The disadvantage of ultrasonic bonding is that
the angle of the machine's wedge to the bonding pad can
cause problems in multi-die packaging. UltrasoniC, however,
is ideal for monolithic IC manufacturers, where only one or
possibly two die are in a package. The thermosonic method
Non-Conductive Epoxy Attachment
Epoxy is recommended for high precision applications
because linear monolithic dice and film resistors can be affected by excessive temperatures. For substrate attach, a
non-conductive, low out-gassing, film type epoxy, such as
Ablefilm 517, is suggested. Film epoxies can also be used
for die attach.
E
SUBSTRATE
Figure 1_ Chip and Wire Attach
PAGE 15-136
}
is a combination of ultrasonic and thermocompression
bond which uses heat, pressure, and scrubbing to give the
best of both techniques.
Although PMI uses aluminum ultrasonic bonding on all of
its products, hybrid manufacturers have generally found
gold wire thermosonic to be more cost effective for hybrids.
Flip Chip Beam Tape
The flip chip on tape is another method of bonding die to a
substrate (Figure 2).
"Bumps," constructed of copper or other conductive
material, are deposited as part of the metalization. The die
is then flipped over and eutectically attached to conductors
on the tape. During hybrid assembly the tape is bonded to
the substrate in a single operation.
PACKAGE SEALING
Epoxy
Film precut epoxies such as ABLEFILM 517A and 550 are
commonly used for sealing hybrid packages. Although an
epoxy seal can be hermetic, this type of seal has been
known to leak after a period of time. PMI does not recommend epoxy for high reliability applications. Film epoxy is
an excellent low temperature (165·C cure) sealing method
suggested for thin film commercial data conversion applications. Epoxy seals are usually used with Epoxy Band
Ceramic packages.
Glass Seal
Used with ceramic and side-brazed packages, glass seal is
a high temperature operation, in excess of 400·C. As mentioned previously, heat treat for films occurs at this
temperature, and film change is possible. In applications
where absolute resistance is not nearly as critical as
resistor tracking, the problem is not as severe, since
resistors change together. PMI uses glass sealing and
recommends it for high reliability applications.
Braze and Welding Sealing
Braze sealing is performed on a welding machine using a
gold-tin or solder preform between the package and lid.
Sealing temperatures are restricted to the sealing rim only.
The pure weld seal (metal to metal) is another excellent seal
but requires much higher sealing temperatures. However,
as in brazing, the temperature is localized at the weld only.
Brazing and welding are used with all-metal Kovar packages
and are excellent for high reliability applications. Welding is
ideal for space applications because a braze seal can
possibly introduce contaminates into the package from the
preform.
TAPE
)
SUBSTRATE
Figure 2. Flip Chip Beam Tape Attach
Beam Lead Bonding
The beam lead technique basically has the lead (which is
approximately a 10·mil beam) connected to the metalization
at wafer fabrication. A single attach operation combines
both die and wire attach (Figure 3). This method is not used
much in industry today.
BEAMS
This section deals with typical problems that arise because
of improper design. Care must be taken in hybrid design
because problems such as ground noise, ground loops,
crosstalk, gain errors, and high temperature tracking errors
can result. These problems can be substantially reduced
with proper resistor placement, conductor or resistor line
widths, layout, and film selection.
SUMMING AMPLIFIER DESIGN EXAMPLE
SUBSTRATE
Figure 3. Beam Lead Attach
Chip Carrier
The chip carrier is a miniature, lead less package intended
mainly to increase package density. This carrier contains
the tested Ie attached usually with chip and wire and eutectic
or epoxy bond. The carrier can then be attached (or reflow
soldered) to a Dual·in-Line motherboard or Hybrid.
II)
W
I-
o
Z
z
o
AVOIDING PROBLEMS IN HYBRID CIRCUIT
DESIGN
Consider the summing amplifier circuit in Figure 4 where
RA , Rs, and Rc must track the feedback resistor R1. Layout
is critical, so R1 should be located as close as possible to
RA , Rs, and Rc for best TCR tracking and minimum gain error. The sum node is a high impedance point and is susceptible to crosstalk and noise pickup. This node should be
isolated with a ground ring if possible. A low TCR thin film
such as nickel-chromium or silicon-chrome is recommended
to reduce tracking errors between the resistors. The ground
should be an analog ground with no digital ground returns
on it which would introduce noise.
DIE
~
z
c
16·BIT DAC DESIGN EXAMPLE
High resolution D/A converters are ideal for thin film hybrid
designs. Figure 5 illustrates a 16·bit converter using four active
ICs for current output and five dice for the voltage version.
PAGE 15-137
u~
::::i
CL
~
I
FILMS AND CONDUCTORS
The hybrid designer should be aware of pitfalls where film
and conductors are concerned. The gold conductor, like the
film reSistor, can cause many problems and should be con·
sidered as a possible source of error.
AA
INPUTS
A8
OUTPUT
Films can be either thick or thin, but there are many other
characteristics that must be considered when selecting a
film (see Table 1).
The substrate material can also determine TCR tracking. A
smooth surface, such as silicon or glass, is excellent for
resistor tracking. Silicon substrates dissipate power better
than glass; however, stray capacitance Is higher on the
silicon surface. PMI uses silicon·chrome film sputtered on
silicon.
Thick film is an excellent choice for general purpose ap·
plications. This film varies with paste and firing temperatures however. The thick film process applies the "Inked"
resistance by silk-screening to a ceramic substrate. This
technique is advantageous in high power and in most circuits where TC is not critical.
Figure 4. Summing Amplifier Layout
Resistor placement is again very important. Reference
resistors RA and RA1 , must be adjacent to Re for proper
tracking. Also, Rlo R2, R3, R4 should be located close to
RSPAN for minimum gain TC error. Low TC films are used
(see Table 1).
MSB
~
Gold conductors introduce 0.01 ohms per square (aiD) to as
much as 0.1 III 0 resistivity. A long, narrow line width results
in a high resistance. Gold bonding wires, one mil In
diameter, can Introduce 2 milliohm per mil Ii-inch of resistance. Also, gold conductors typically have temperature
coefficients of about +30ooppm/·C which should not be
overlooked. It is recommended that the conductor be short
and as wide as possible.
DIGITAL INPUTS (COMPLEMENTARY BINARy)
LSB
~8
QUAD SWITCH
lOUT
RSPAN
~T
.~
·INDICATES CRITICAL GROUNDS. KEEP THIS GROUND SEPARATE FROM DIGITAL GROUND.
Figure 5. 16·81t Digital·to·Analog Converter IC
Table 1. Film Types and Uses
TYPE
DENSITY
(010)
TCR
(PPm/·C)
TRACKING
(ppm/·C)
APPLICATIONS
. Nickel-Chromium
50 to 500
±50
±1
Excellent tracking. Precision data conversion .
Tantalum-Nitride
27 to 120
-150
±2
Precision circuits. Excellent long term stability.
Silicon-Chrome
2000
±1oo
±1
Precison/high density.
Cermet
2000
±250
±50
±100
±10 to ±50
Thick
10 to 1 Meg
PAGE 15-138
High denSity/commercial.
General purpose/high power.
CAPACITANCE EFFECT
Conductors running parallel to each other can act as plates
of a capacitor. This capacitance is shown in the expression:
Cae -
L
D
(k)
where C
Capacitance
ae
Proportional To
L = Conductor Length
D = Distance Between Conductors
k = Dielectric Constant
= a) Air is 1.0006
b) Glass is 6·10
CONCLUSION
The parallel conductor "capacitor effect" should be considered when designing high speed circuits (see Figure 6).
This application note has described problems and solutions
associated with assembly as well as physical design. Proper circuit operation at the breadboard level does not
always guarantee hybrid operation. Layout, selection and
design of film resistors, and design of conductors can be
critical.
Wire bonding such as ultrasonic and thermosonic are
reliable bonding methods because they scrub through
metalization oxide. Epoxy die attach and package sealing
are useful where low temperature assembly is required.
Remember, temperatures in excess of 300·C can cause dice
and film electrical changes.
Ir-.-----L~-~----I
~____________~C~ON~D~U~CT~O~R____________~!_.
DIELECTRIC ISOLATION
Pressure or strain during die attachment or wire bond can
also cause parameter change which is usually catastrophic.
A punch-through problem is very common to thermocompression wire bonding. This problem occurs when the ball
bond pierces or pushes the aluminum metalization down
through the silicon or active portion of the die. Chips can
also be strained when eutectic or epoxy die attach causes
unbalanced stress effects.
o
I
CONDUCTOR
Figure 6. Conductor Capacitance
In conclusion, the hybrid designer must be aware that
hybrid operations and processes are not all the same. Selection of methods to be used is important.
MONOLITHIC INTEGRATED CIRCUIT
BIBLIOGRAPHY
The monolithic die can be damaged by excessive
temperature or pressure. Temperature can cause Beta
degradation, but also has some good effects. Low temperatures, around 125·C for long durations, can cause
parameter shifts evidenced by a power burn-in operation.
Power burn-in does stabilize active devices much in the
same way as a temperature bake reduces film change.
"Datel Microcircuits for Data Conversion," Datel Systems,
Inc., August 1978.
AN-2, "Monolithic Chip Assembly Information," Precision
Monolithics Inc., July 1975.
"Electronic Buyers' Handbook," Volume 2, Resistive Components, September 1977.
...+12V
+5V
+5Vo---------~------------+-~4-~-A~_4
~
ZERO
ADJUST
'OOk!l
C11200pF MICA
C3120pF
C4 1000pF
ALL RESISTORS :tR, 0.126 WATT
METAL FILM UNLESS NOTED
'OkIl
Rl
FULL
---,
.C
1
87
-1
6432~
INPUT
SILICONIX
SCALE
ADJUST
",2OO0F
, ,
L012D
R5 ~1·1'011'2'3"'5'.
.-W
'---VV~--~-+--+-~R'
O'.... F
lMn
.J
4.7kn
I= \""F
LJ'I-'*-1f-.,1''''wnw
~
MYLAR
R3
~R2
l00kn,±1%
+12Vo--_ _ _ _ _ _ _ _ _ _
GNDJ.
--4~-::!.~==i=~
' - - - - - - - - - - - - - - - - - - - - - - ....
Figure 7. Automatic Nulling DPM
_....... _--
PAGE 15-142
____I_--__,
2
Q
-
..,.
~
11
9
11
17
,.
LATCH
22
98671'C
,
'2
7
~ OM"'7 ~.----+-_-+-f-,."l
_.~.
~~AIRCHILD~ ~
5
5
2N3984
,:'2V
.J..nn
I~~ :;=o.o,.F
L!!..J
latch. The DAC will then supply a difference voltage to the
DPM to return the zero input reading to zero.
I.
+12V
Applications of this circuit are many and varied. They range
from auto-tare digital scales where the tare button is pushed
to subtract the weight of the empty container ("tare" weight)
from subsequent weighings to push-button zeroing to cancel non-ideal transducer and signal conditioning offsets.
The use of the circuit configuration depicted here allows the
2-digit DAC-20to null a4-1/2, 5-112, or6-1/2 digit instrument
since it operates on only the Least Significant Digits (LSDs).
12
11
TO
DISPLAY
10
10
,.
FOURBIT
11
LATCH
74116
17
18
I.
20
21
-12V
BCD
DAC·20
O.Ol~F
16
I.
The approach described in Figure 6 is implemented in the
circuit of Figure 7 which presents a DPM with differential
input capability to perform analog subtraction at the ADC.
The DAC-20 adds null correction to the last two LSDs of the
depicted 4-1/2 digit DPM. A latch stores the null "word"
which is loaded during the push button nulling phase (the
taring phase for scales). The DAC output, proportional to
this word, is subtracted atthe input ofthe DPM until the latch
is either cleared or a new null word is entered. No pot
adjustments are needed and the adjustment required is
simply reduced to the pushing of a single button.
5k!l
.".
The nulling circuit is able to handle bipolar offsets by providing an initial zero offset of 112 of the DAC·20's range. This
is achieved by biasing the current output of the DAC with a
positive constant current from the current regulator diode
CR430. Combined with the 100 resistor, the correction cir·
cult can null offsets of up to ±5mV in 100,..V steps.
Figure 9. Drive Circuitry for 4-1/2 DPM with Analog Meter
tinuous digital input to the BCD DAC and a continuous
analog output to the analog meter (0 to 1mAl.
In those applications where a sign-magnitude BCD code Is
required, an external switch can provide the sign-bit control
of the current. This Is shown In Figure 8.
The meter reads only magnitude, not sign. The sign of the
digital display must be viewed for polarity determination.
Although the DPM is a 4-112 digit Instrument (the 112 digit
gives 100% overranging), the analog meter only reads to the
4-digit range and then returns to zero for an output of 10,000.
Either the MSD can be read from the digital display, since it
should be the most slowly changing digit, or the analog
meter must be considered in error.
ANALOG METER
The demultlplexing circuit described In Figure 5 can be applied In an analog meter driver as shown in Figure 9. The
Most Significant Digits (MSDs) are latched to give a con-
Basically the circuit shown In Figure 9 is the same circuit
used for the auto-nulling circuit shown in Figure 7 except
~
Z
,-.-~____~____~~____~____~~____~______________________________________~_ T~~~~
9MI>
RX
900k
lkl>
l--,/\g.I\'k~"""'M------____-o(~~~
1kl>
10k
TO DVM
GAIN
SWITCH
+15V
lOkn
~---------------------------o~v
15
-
Ok
I
A
PUSH TO
CALIBRATE
f.tt=;=======i===========================~Bl ~B
:?z
c(
I-'
82
E7+-+-~----+----------------------------o83
r.;;.+-+-+~--+----------------------------o B4 MSB
MULTIPLEXED BCD
lOkI>
12~==t====;==t===~~====================~OOl
DSZ
lSB
2Okl>
II
Figure 14. Auto-Calibrate Resistance Measurement
throughout. The convenience, flexibility and intelligence
that BCD DACs provide BCD·based instruments such as
digital multimeters will spread to other applications.
PAGE 15-147
§.
"
I " • • •
ii"
I
r++-+-+>---;,..JoN>r-.I--l.I......r-.'::lr>l-+'........ '
~
r-r---j
>-- f---,';
•
.
I"~~:.~
::!'j). L-o~
~1
I,
;
"0"'"
•,
•
!
::iI 1-'-'-------"""'--+
!.....,.,..-
..
'=r.r-r.r'
.
"~I'
"I
u
•
t---"(tY---,j
H I
!
;0
iii
g
~I,f ·
I
I I
-
Figure 15. Complete Smart DMM
PAGE 15-148
'---
PMI
APPLICATION NOTE 35
UNDERSTANDING CROSSTALK IN
ANALOG MULTIPLEXERS
by Shelby D. Givens
INTRODUCTION
SOURCEO~----Tr----~o DRAIN
One of the most troublesome errors in analog multiplexers
is crosstalk. Various schemes have been devised to reduce
its effects. One designer will terminate the multiplexer in a
10kO resistive impedance. Another will short the multiplexer
node to ground between address changes with an analog
switch. A third engineer will terminate the multiplexer node
in 1 MO because he doesn't want to live with the attenuation
which comes about with any lower impedance. What is confounding about these three situations is that the solution is
correct in each case. THE CORRECT SOLUTION IS DICTATED BY THE APPLICATION.
To understand why the solution is application dependent, it
is necessary to dig rather deeply into what crosstalk really
is. When this is done, crosstalk is found to have not one, but
three components in a multiplexer. To differentiate the components one from the other, it is convenient to give them
names:
1. Static crosstalk (CT)
2. Dynamic crosstalk (OCT)
3. Adjacent Channel crosstalk (ACCT)
This .application note explains the three crosstalk components qualitatively and quantitatively. The qualitative
discussion tells what component(s) should be considered in
various applications. The quantitative discussion uses both
theoretical and empirical information to arrive at conclusions about what performance should be expected.
STATIC CROSSTALK (CT)
To introduce the concept of crosstalk, Figure 1 will be
helpful. A multiplexer is made up of several analog switches
connected as shown in Figure 1c. The basic analog switch
may be constructed of a FET (JFET or CMOS) and a suitable driver which switches it OFF and ON. This is shown in
Figure 1a. The equivalent circuit of an analog switch is
shown in Figure 1b. When the ideal switch (SW) is closed
the switch has an ON resistance RON, and when SW is open,
the OFF impedance is determined by CEQ. The two channel
multiplexer shown in Figure 1c shows how signals from one
channel can be coupled into the other channel. Theoretically,
VOUT should consist of e1 modified by the resistor divider
formed by RON1 and RL (assumes reactance of C L is ~ RJ.
However the capacitance of switch number two (CEQ2l does
couple some portion of e2 into V OUT' This is the simplest example of crosstalk.
The model which explains static crosstalk is relatively Simple
and may be derived from the OFF isolation model. Figure 2a
shows the OFF isolation model as capacitive coupling from
the input to the output of an OFF switch. This condition may
be duplicated in Figure 1c by opening SW 1 and setting e2=0.
Coupling from input to output is accomplished through CEQ,
DRIVER
CIRCUIT
a. FET ANALOG SWITCH + DRIVER
SOURCEO~------------tl t-~--.._--oVQUT
1
"L
4. Telemetry
CL
Each one of the above applications are a form of Time Division Multiplexing. In other words, these are sampled-data
a. OFF ISOLATION EQUIVALENT CIRCUIT
"OFF" ISOLATION (ISOOFF)
The proportionate amount of a high frequency analog input
signal which Is coupled through the channel of an "OFF"
device. This feedthrough is transmitted through CDS(OFF) to a
load comprised of CD(OFF) in parallel with an external load.
Isolation generally decreases by 6dB/octave with increasing
frequency.
sw,
a. DYNAMIC CROSSTALK EQUIVALENT CIRCUIT
NOTE: SWI is a time dependent switch. Its characteristic is shown in
Figure 3b.
CHANNEL 1
~
,
L:RE~
CLOCK
CHANNEL
OPEN
b.
I ,I
CHANNEL 1
OPEN
STATIC CROSSTALK EQUIVALENT CIRCUIT
CROSSTALK (CT)
it:T~
The proportionate amount of cross-coupling from an "OFF"
analog input channel to the output of another "ON" output
channel.
b.
Figure 2. Model for Static Crosstalk
T", Period of address clock
T BRK '" Break-Before-Make Time
DYNAMIC CROSSTALK (OCT)
The dynamic crosstalk model can be derived from Figure 3.
The switch SW l represents one condition on the multiplexer
node (SWl is open). Actually SW l Is continually switching
between OFF and ON. This is represented in Figure 3b. In
order to reduce crosstalk, multiplexers are designed to have
break·before·make switching so that no two channels are
addressed at the same time. The finite open time of SW l
(shown in Figure 3b) represents the break-before-make ac·
tion. There are two "open" conditions on the multiplexer
node per cycle of the clock; thus the equivalent nodal
resistance (REal may be computed as given in Figure 3b.
Table I shows some typical values of static and dynamic
crosstalk. Static crosstalk values are given In lines 1 and 12.
There is a change in crosstalk as the clock frequency (fCLlQ
is varied. Starting at line 4 notice the variation in crosstalk
as Rl is varied from 10kO to 100kO while fClK remains con·
stant at 100kHz. While Table I yields some theoretical
values which give inSight into the operation of dynamic
crosstalk, a working multiplexer will have different values of
fClK with respect to the maximum value of f slG. The real
world situation will be analyzed in a later section of this
paper.
Examples of multiplexer applications which are dynamic in
nature are:
If Rlil> RON, REO -
RON(T - 2T BRKl + 2RlT BRK
T
Figure 3. Model for Dynamic Crosstalk
Table 1. Computed Values of Static and Dynamic
Crosstalk
LINE
NO.
'SIG
Hz
10K
10K
3
5
10K
10K
10K
6
7
10K
10K
8
20K
9
10
11
12
4
PAGE 15-150
T TaRK RON
Rl
REO
l'8ec l'8ec OHMS OHMS OHMS
0
0.80 300
10K 291
20K 50
0.80 300
10K 602
0.80 300
40K 25
10K 913
lOOK 10
0.80 300
10K 1845
lOOK 10
0.80 300
20K 3448
0.80 300
40K 6650
lOOK 10
'ClK
Hz
lOOK
10
0.60
300
50K
50K
50K
20
20
0.60
0.60
0.60
300
20K
20K
20K
50K
20K
0
0.80
0.60
20
20
CEO
pF
0.30
0.30
0.30
0.30
0.30
0.30
lOOK 16.25K 0.30
300
10K
20K
40K
1068
1872
3474
0.30
0.30
0.30
300
300
lOOK
lOOK
8275
291
0.30
0.30
300
CROSS·
TALK
dB
105
99
95
89
84
78
70
88
83
78
70
99
systems where each channel is being continuously sampled
and the information for a given channel is contained in a
given time slot. In these applications, the static crosstalk is
almost meaningless, since the wrong choice of Rl (or fClK!
can be disastrous.
~"}
:
,
I
I
L-21
ADJACENT CHANNEL CROSSTALK (ACCT)
: ) ADDRESS
CODE
811
L"
CHANNEL
ADDRESSED
CH.1
Figure 4. Adjacent Channel Concept
The fact that information is "carried forward" from on'e
channel to the next (in time) suggests a storage mechanism
as causing ACCT. Thus the multiplexer nodal capacitance
becomes the prime suspect. Figure 5 illustrates how information is carried forward from one channel to the next as
the addresses are changed. The address code is shown in
Figure 5a, while Figure 5b shows the theoretical multiplexer
output. Note that the even numbered channels have zero
volts on them, while the odd channels have their channel
number in volts. This arrangement best illustrates how the
information is transferred to the adjacent channel (as
I
I
1
1
1
I
1
I
8.
1
,"
I
I
I
I
I
1
113V1
'v
1
CH.'
1
I
ov
CH.2
I
II
CH.3
11
I
I
I
1
I
1
1
I
I
I
THEORETICAL
MUX OUTPUT
ov
I b.
I
I
ADDRESS
CODE
5V
~
Adjacent channel crosstalk is the most confusing component of crosstalk. In addition to its confusing nature, in
some cases, it is the most dominant component. While both
static and dynamic crosstalk are capacitive in nature, i.e.,
they vary with frequency at SdB/octave, the adjacent channel crosstalk is invariant with frequency. In other words, it is
possible to have crosstalk when multiplexing DC signals
such as the outputs of thermocouples, pressure transducers, etc. The parameters which must be dealt with are
Rl , C lJ RON, and f ClK' In addition, the break-before-make
time (= T BRK! of the multiplexer is of importance. Before diving into the details of this component of crosstalk, it will be
helpful to define what is meant by ACCT.
The term "adjacent" refers to time only. In other words,
channel two is adjacent to channel one if channel two immediately follows channel one in time slots. Since the channel following is the "adjacent" channel, then channel one is
not adjacent to channel two, but rather the other way
around. Figure 4 illustrates the concept of adjacent channels. Assuming the multiplexer had, say, 1V on channel one,
2V on channel two, etc., then the output would look like the
curve labeled "channel addressed." What Is important
about the waveforms in Figure 4 is the way the adjacent
channel (in time) is shown. Note that while channel two is
adjacent to channel one, channel one is itself adjacent to
channel eight.
I
I
I CH.5
I
I
I
I
I
I
I
1
3V
I
CH.4
ACTUAL MUX
OUTPUT WITH
BREAK-BEFORE-MAKE
TIMES
I I
II
1 I
I CH.' I I CH.2
II
CH.3 I
1 CH.41
ICH.5
c.
Figure 5. Adjacent Channel Crosstalk
shown in Figure 5c). While the theoretical MUX output
switches from channel three (3 volts) to channel four (0
volts) at the moment of the address change, note the delay
in the actual MUX output caused by T BRK. During this time
the MUX node discharges along an RC curve determined by
the load capacitance (CJ, and the load resistance (RJ.
When the break-be fore-make time (TBRK! is over, channel
four is turned ON and the RC product is suddenly reduced to
RONC l . A curve which details how this all takes place is
shown in Figure S. Before leaving Figure 5, the arrangement
suggests a method of avoiding adjacent channel crosstalk.
In other words, the alternate grounding of channels
prevents channel one Signals from reaching channel three ...
channel three from reaching channel five, etc.
The curve in Figure Sa shows a typical nodal discharge for a
set of real world conditions. The curve is normalized and
TBRK is chosen to be 900nsec. An accepted method of
measuring TBRK is from the 50% point of the channel which
has been turned OFF to the 50% point of the channel which
is being turned ON. This concept is illustrated in Figure Sb.
In this case (Figure Sa) T BRK is measured from the moment
of the address change. While this is not totally correct, the
agreement between theoretical and actual results is good
enough to justify the simpler model which is derived. Since
most designers are interested in crosstalk which is less
than the resolution of the discharge curve, the ACCT vs.
time graph gives crosstalk down to 90dB. In other words, the
ACCT is down 90dB in less than 1.25JtSec.
Adjacent channel crosstalk is a problem in every application where dynamic crosstalk must be considered; however
there are techniques to minimize its effects. A popular way
to diminish adjacent channel crosstalk is to short the
multiplexer node to ground between address changes. This
requires an additional analog switch which should be fast
PAGE 15-151
ACCT(dB)
TIME (¢lee)
1.10
66.3
1.13
1.17
1"2 79.8
91.4
1.21
ACCT vs. TIME
'.0
..8
rf
V'N
o.......- - - - I I - - _ - - 1......-~VOUT
O.13pF
59.6
CL = 100pF
RL =47kll
RON =30011
1"1 =4.71'59C
72 =30nsec
0.&
...
"L
6.6kn
f SIG = 40kHz
1SOOFF = 75dB
0.2
Figure 7. Typical OFF Isolation Element Values
200
40D
80D
800
1000
TIME - nSEe
RELATIVE CHARGE (=ORl= Ott)
CEQ
00
00'" INITIAL CHARGE STORED FROM
VIN 0
PREVIOUS CHANNEL
REa = 306n
I
VOUT
o.13pF
8. STORED CHARGE ON MUX CODE
f SIG '" 40kHz
"ON
32."
"L lCL
..·,.nT'''F
CT = l00dB
CHANNEL 1
------,L-_---'C;;;H;.;AN;;;N;:;EL:..;2:....._ _ _ ADDRESS
CHANNEL 1
FINAL VALUE
50% POINT
Figure 8. Typical Static Crosstalk Element Values
BOTH CHANNELS
OFF
50% POINT
CHANNEL 2
FINAL VALUE
b. ACCEPTED METHOD OF MEASURING T BRK
Figure 6. Stored Charge Decay and Definition of TBRK
and have low RON' An alternative approach to reducing adjacent channel crosstalk is to ground every other channel in a
multiplexer. This technique was illustrated in Figure 5.
MEASUREMENT OF STATIC CROSSTALK
Figures 7 and 8 give the element values for a typical PMI
BIFET MUX-08 on channel three. In the case shown, the OFF
isolation was first measured and found to be 75dB. With RL
and f SIG known, then CEO was calculated. Once CEO is
known, then REO may be calculated from the static crosstalk measurement made in Figure 8. REO is the parallel combination of RL and RON; thus it is possible to compute RON
and this value is also shown in Figure 8. The measurements
thus far are relatively simple and only require a voltmeter
which is capable of measuring signals which are 100dB
below the reference signal. On the other hand, the measurement of dynamic crosstalk is a bit more involved, and requires a more complex system.
MEASUREMENT OF DYNAMIC CROSSTALK
The crosstalk measuring system shown in Figure 9 is to be
used for measuring dynamic crosstalk. The signal from M5
is fed into M1 where it is multiplexed onto the OUT terminal.
M1 contains the multiplexer under test and a decoding circuit. The decoding circuit allows the selection of any two
channels to be used as a two channel multiplexer. M2 is a
high-speed buffer used for driving the IN terminal of M3. M3
contains a multiplexer operated in a demultiplexer mode,
along with decoding circuitry to allow several combinations
of two channel demultiplexing. The signal which appears on
S3A is fed through M4 (high-speed buffer) to M8 for spectrum
analysis. In short, If no errors are introduced by the multiplexer-demultiplexer system, the output should be the same
as the input.
. Since the system in Figure 9 is capable of measuring
dynamic crosstalk, a good check of its performance is to
repeat the static crosstalk measurements. M3 is set to have
IN connected to S3A at all times. M1 is set to have S3 connected to OUT, and the signal thus measured is taken as the
reference signal. Static crosstalk is measured by connecting S1 (or Sa) to OUT, with VIN still applied to S3, and again
measuring VOUT' The relative signal levels represent static
crosstalk. This measuring technique was used to verify the
accuracy of the system.
The measurement of dynamic crosstalk leaves M3 exactly
as in the static case. With VIN connected to S30 M1 is switched
between S1 and S8' The signal frequency (fslGl was 40kHz
and fCLK was 100kHz (see Figure 10). From the crosstalk
measured, the equivalent resistance (REO) is computed to be
11500 (see Figure 10a). To verify the validity of this measurement, REO was calculated using the formula in Figure 10c
(T BRK was measured separately). Since there is very good
agreement between these two Independently derived
values, both the measurement technique and the dynamic
crosstalk model are valid.
PAGE 15-152
M'
51!!
M3
5111
S,
~
S.
+
V'N
S,
S4A
S'A
1~
~
DEMUX
+
DeCODe
'N
~
S,A
OUT
"to,
DIGITAL
1ku
\
o TO +3V
'SIG 300mV
RMS
L[2:>
~
MUX
DECODE
510n
510U
M2
V
'elK
''OJ?
DIGITAL
'7
elK
I
KROHN-HITE
MODEL 4200A
SINE WAVE
GENERATOR
WAVETEK
MODEL 143
SQUARE WAVE
GENERATOR
M6
M6
L
VARIABLE
DELAY
CIRCUIT
HP-358OA
ClKO
r--
SPECTRUM
ANALYZER
M7
YOUT
I
'N
r---
M8
Figure 9. Dynamic Crosstalk Measuring System
CHANNEL 1
Rea = 1150u
VIN O------jl---~-~-~-O VOUT
O.13pF
RON
324!1
fSIG = 40kHz
Rt
5.6kll
CHANNEl 2
CL
18pF
I
CHANNEL 1
L:
ADDRESS
CLOCK
OCT = 89dB
sw,
OPEN
~
OPEN
felK = 100kHz
Z
C
NOTE: SWI is a time dependent switch. Its characteristic is shown in
~
Figure 10e.
a.
I-
o
TYPICAL DYNAMIC CROSSTALK ELEMENT VALUES
Z
Z
SYSTEM DYNAMIC CROSSTALK
'SIG
'ClK
Rl
Hz
HZ
!l
10K
10K
10K
10K
10K
lOOK
lOOK
lOOK
lOOK
lOOK
10K
22K
33K
47K
lOOK
OCT
OCT
(C EO =0.13pF) (CEO = 0.5pF)
dB
dB
!l
1718
97.1
85.4
3463
91.0
79.3
5059
87.7
76.0
84.7
73.0
7090
14.78K
78.4
66.7
o
T=5pSec
TBRK = 725nsec
REO =10890
REO
~
u
::::i
T", Period of Address Clock
TBRK == Break-Belore-Make Time
c_
b.
Figure 10. Computed Dynamic Crosstalk for Actual Multiplexer
The numbers shown in Figure 10 apply to the measurement
system, but are unlikely in a real multiplexer. To satisfy
sampling theory limitations, fSIG must be less than one·half
the sampling frequency. Assuming fCLK = 200kHz then each
channel in a multiplexer is addressed for 5psec. This means
that it takes 40pSec to sample all channels of an eight chan·
nel multiplexer. In other words, each channel is sampled at
a 25kHz rate. Thus the maximum value of f SIG would be
12.5kHz. Figure 10b gives values of dynamic crosstalk (OCT)
which would be experienced if the values of RON and TBRK
shown in Figures 10a and 10b were used. The first DCT column lists the values for a CEO of 0.13pF (measured value of
channel three). The second DCT column shows the perfor-
mance for CEO = 0.5pF. The purpose for the second column
is to pOint out how critical minimizing stray capacitance is
to good crosstalk performance.
MEASUREMENT OF ADJACENT CHANNEL
CROSSTALK
The system shown in Figure 11 was used to measure adjacent channel crosstalk (ACCT). Ml drives the address lines
of the MUX system and the gating input of M4. By setting the
period of M4 (T2l to 10psec, the pulse rate out of M4 is controlled by the pulse rate of Ml (40,..sec) coming into the gate
input of M4. The output of M4 is in the complement mode
PAGE 15-153
IL
IL
C
•
v
ANALOG IN
M,
M.
HP-8012B
GATING 81
MUX DRIVING
MUX
SYSTEM
JL
OUT
SETTING:
T 1 .. 4O,.!SEC
P, = &$J.SEC
I
GATE
HP-8I)12B
SIH
DRIVING
a. VOLTAGE DECAY ON MUX OUTPUT
IN
--u-
INTECH
A.aBl SIH
(COMPLEMENT)
OUT
ANALOG
ORAIN~
(NORMAL)
CONTROL
HP-368OA
SPECTRUM
ANALYZER
OUT - I N
IN
M.
SETTING:
T2=1G,.!SEC
P2 = ~SEC
TIMING:
.,
ACTIVE CHANNEL
ADDRESS
---.J
GROUND CHANNEL
~ ~~~~I____~_LO_ __ _
b. SAMPLE/HOLD
~tEj
EQUATIONS:
1. -Vo .. N = N H(T1- P21+S1+ S2 ; Where
o
VR
T1
Figure 11. Adjacent Channel Crosstalk Measuring System
because the control input to M3 causes the S/H to HOLD
when the input is high (1). Thus the sample period occurs
during the time P2. M4 also can delay its pulse relative to
the pulse out of M 1, thereby allowing measurements of
crosstalk versus t1 (start of the sample time). This information is valuable because in many systems, a sample/hold
is used with a successive approximation ADC to encode
the analog output of the MUX. As will be shown, the ACCT
can be made negligible if a sufficient time elapses before
going to the HOLD mode for encoding the data. Since
"time is money," the term "sufficient time" becomes important.
The nature of sample/holds and the nature of spectrum
analyzers can cause some apparent discrepancies in the
data observed by this measurement system. It is important
to riote the spectrum analyzer "sees" the average of
everything that is presented to its input terminals. While it is
true the sample/hold holds the last value it "saw," the spectrum analyzer also looks at the signal present during the
sample/hold's sample time. Thus the equation which expresses the signal level present as a function of time must
also account for the true averaging of the spectrum analyzer. Figure 12 shows the equations (12c) and the definitions of the terms used in the equations (12a and 12b). The
term No is the relative Signal level which the spectrum analyzer measures. If the model of the signal decay shown in
Figure 12a is the correct one to explain the ACCT, then the
computed value of No should correspond to the measured
values. As will be shown in Figure 14, the agreement does in
fact justify the model; however it was necessary to choose
the measurement conditions very carefully.
= EXP [
3.
rT BRK -
J
~ EXP L-T-2-j' t ~ T BRK
A1"S1=T1rEXp(-t1)_EXP(-TBRK)~
VR
4.
J
- TBRKl
~:
[~
"S2 = T2 EXP [-
i
::R~f
~
_ EXP (T
~
BR~-t2~
c.
Figure 12. Predicting the Measurement System Response
In order to get good correlation between lab data and
theoretical predictions, it was necessary to use fairly long
time constants (RL = 22kO and C L = 1000pF). With RL = 22kO
and C L = 50pF (RON = 3000), the theoretical plot of ACCT (as
measured on the spectrum analyzer) vs. t1 is shown In
Figure 13. Note that the data is plotted between 900nsec
and 1025nsec. The curve shows that a 10nsec error In 11 can
cause a 6dB error in reading on the spectrum analyzer. The
results shown in Figure 14 confirm the necessity of using
large capacitances to obtain predictable results. The theoretical curve tracks the actual data well in both cases;
however the 1000pF curve is better than the 300pF curve.
Notice that there is good agreement both at DC and at 4kHz.
PAGE 15-154
A. Multiplexer·Demultiplexer System:
NH",O Therefore
S1 +S2
1
1. No=--, Where T1 = - - x (No. of Channels)
T1
fCLK
110
RL
100
= 22kn
RON
=
CL
= 50pf
lOOn
2. S1 =
;;
"
I-
~
T1
[EXP
(~~1) -EXP (- ~~RK)J
90
3. S2 = T2 EXP [T
80
~~~ ~ - EXP C-BR:2- 12)J
Where tl = To (Break·Before·Make Time-of DEMUX)
1
70
~
60
SLOPE
~
t2= -To
fCLK
O.&dB/mac
B. Multiplexer -
I
Sample/Hold System
Sl=S2=P 2=O
900
1000
960
1050
4. No=NH= EXPGJ tSTBRK
ACCT VS. t1 WITH SMALL CL
Figure 13. Measurement Errors Due To Small CL
= EXpe
:~J EXP [TB:: - J' t ~ TBRK
Where: t = tH (Hold Command for Sample/Hold as
measured from Address Change Time)
Rl = 22KH
Figure 15. Predicting Adjacent Channel Crosstalk
RON = 3Q(k!
80
T BR K = 950nSEC
I/)
W
I-
o
70
Z
Z
o
~
80
120
(.)
::::i
0.
0.
50
100
RL = 33KH
40
RON = 300H
80
C L = 50pF
MUX-DEMUX
T 1 = 4O/JSEC
T 8R K = 95QnSEC
'elK = 200kHz
LEGEND:
0: MEASURED DATA WITH CL = 300pF
tJ.: MEASURED DATA WITH CL '" l000pF
SOLID CURVES ARE THEORETICAL
20
'0L--L~
o
~
__~-L__L-~~__L-~~~~__- .
" " u u u u u ~ u
~
20
tll~SECI
MUX-5/H
ACCT VS. SAMPLE TIME 1t 1)
Figure 14.
0.4
0.8
1.2
1.6
2.0
tip-SEC)
Agreem~mt
Between Measured and
Computed ACCT
ADJACENT CHANNEL CROSSTALK VS. TIME
FOR MUX-DEMUX AND MUX-S/H SYSTEMS
DEVICE: MUX-08
PREDICTING AND CONTROLLING ADJACENT
CHANNEL CROSSTALK
The equations in Figure 12c can be used to predict how
much adjacent channel crosstalk one might expect in an ac·
tual system. An all analog system will follow the MUX with a
Figure 16. Computed ACCT vs Time for MUX-DEMUX
and MUX-S/H Systems
PAGE 15-155
•
•
demultiplexer, which will have its own break-bef6re-make
delay_ An analog to digitai system will have a sample/hold
amplifier in front of the AID converter_ Since the equations
which apply to these situations are different, they will be
discussed separately_ Figure 15 summarizes the conditions
and the equations which apply to them_
Since there is no held voltage, then NH = 0 in the multiplexer-demultiplexer system. This reduces No to the simple
form shown in equation (1). S1 and S2 follow in equations (2)
and (3). Since t1 = TD (break-before-make time of the DEMUX),
that time will have a significant effect on ACCT. The MUXsample/hold system imposes the condition S1 =S2 =P2 =0;
thus NO=.N H. It will be instructive to compare the levels of
ACCT in these two systems versus their appropriate times.
Figure 16 looks at a "typical" system which will give approximately one percent transmission error (33kn RL and 300n
RON)' and has 50pF CL. The value of CL is somewhat on the
high side (20pF being typical for MUX-08 connected to a buffer amp), but it does give a con.servative value for. analysis.
What Figure 16 shows is rather startling. The adjacent channel crosstalk, while inherent in the multiplexer itself, can be
eliminated in both systems by the proper timing. In the case
of the sample/hold it is only necessary to delay the hold
command for approximately 1.2!,sec to have the ACCT
vanish completely. This is no problem, since most sample/
holds need at least 2!,sec to accurately acquire the Signal
(this is particularly true of monolithic devices). The plot for
the MUX-DEMUX system relates to TD, which is not ad·
justable for a given DEMUX. What is possible is to add some
delay to the address change for the DEMUX. In this way, the
DEMUX will not "look" at the MUX output until the charge
from the previous channel has had a chance to dissipate.
CONCLUSION
Table II summarizes the forms of crosstalk and lists ways of
coping with them. Reduction of RON is helpful in all three
cases. While TBRK should be minimized as much as possible,
it is important that no two channels are ON at the same
time_ In some cases, T BRK is chosen such that even over
temperature extremes, the break-before-make feature is
maintained. Since all three components of crosstalk are pre·
sent in a dynamic multiplexer, the "careful circuit board
Table 2. How to Handle Crosstalk
Crosstalk
Component
Variation
with f SIG
Ways to Minimize Effects
Static
6dB/octave
• Minimize RON
• Reduce stray capacitance (CEO>
by careful circuit board layout.
Dynamic
6dB/octave
• Minimize RON
• Minimize fClK
• Minimize TBRK, but TBRK > 0 Is
needed to prevent shorting
channels together.
• Minimize Rl
• Reduce stray capacitance (CEO>
by careful circuit boerd layout.
Adjacent
Channal
NONE
• Minimize RON
• Minimize fClK
• Minimize TBRK, but TBRK>O Is
needed to prevent shorting
channels together.
• Minimize Rl and Cl
• WAIT before allowing sample!
hold or DEMUX to measure MUX
output.
layout" is important even though it is not listed in the ACCT
section.
This paper has pointed out the fact that static crosstalk
(given on multiplexer data sheets) is only one of the three
components of crosstalk. The models for static and dynamic
crosstalk are relatively Simple and were discussed to show
how they are related. The most troublesome compo'nent of
crosstalk (adjacent channel crosstalk) was shown not to be
quite so straight-forward_ For one thing, adjacent channel
crosstalk (ACCl) is not signal frequency dependent as are
CT and DCT. The mechanism which governs this form of
crosstalk is stored charge on the MUX node. While CT and
DCT must be minimized by careful layout and once present
in the multiplexer cannot be reduced, such Is not the case
with ACCT_ Even though ACCT is present in the multiplexer,
the proper timing of demultiplexer or sample/hold commands
can effectively eliminate ACCT from the total system_
PAGE 15·158
APPLICATION NOTE 36
PMI
OAC-OB CONTROL OF 555 TIMERS
by Kishor Patel
INTRODUCTION
{ lOUT} volts per second from approximately zero volts to
This application note describes a digitally or microprocessor controlled one-shot and an astable multivibrator
using two of the industry's most widely used low cost
building blocks, the PMI DAC-08 8 bit DAC and the 555
timer. Digital control ranges of 255 to 1 and 510 to 1 are
shown for one-shot and astable applications allowing
periods of 181'sec to 1.4 seconds and frequencies of 1 Hz to
60 KHz.
2 C
3" Vcc of the 555 timer.
The one-shot's period, T, is basically an RC product with
two other control factors. The R is fixed and represented by
RREF which sets up the correct IREF current for the DAC.
With the fixed RREF, the one-shot period is directly proportional to the value of the timing capaCitor C (see Table 1).
The other two controlling factors are the DAC's digital
inputs and the ratio of the timer's Vee to the DAC's VREF.
The one-shot period is inversely proportional to the normalized digital input value and directly proportional to the
Vee to VREF ratio as illustrated in Fig. 2. When operated in
the linear mode, a 255 to 1 control range of the one-shot's
period is achieved.
ONE-SHOT LINEAR MODE OPERATION
In the one-shot mode of operation, the time delay or the
one-shot period is determined by a constant current source
and a capaCitor. A digitally programmable constant current
source is made using the DAC-08 and two PNP transistors.
The DAC-08 is a current sink; the two PNP transistors are
used as a current mirror which reverses the direction of the
DAC's sink current forming a current source. The current
source charges the timing capaCitor, causing the voltage
across the capacitor to increase linearly at the rate of
BASIC DESIGN
As shown in Fig. 1, this design involves a series of conversions from a digital input to an analog current to a
threshold voltage and finally to a time delay or a frequency.
A DAC-08 converts the digital input to an analog current
II)
W
t-
O
Z
Z
+11Y
o
~CJ
Vee
...
1'
::i
.2
Do
,on
111
RRI!F
B2
~
DIGITAL INPUTS
83 14 81
RElET
7.50K.o
Vee
t-_ _...,7 DISCHARGE
...
...
'
3
IL
OUTPUT
I--T-I
t----=-j' THRESHOLD
CONTROL
:I TRIGGER
OND
RUF1
7.S0Kn
r
'.~'"F
~LINEAR
V:=tJI
o------------~
ONE-SHOT PERIOD, T
=1. RR,EF~
3
OJ
Vee FOR LINEAR MODE
VREF
ONE-SHOT PERIOD, T = 1. RREFe Vee
3
VREF
[2,-\
Figure 1_ Digitally Controlled One-Shot
PAGE 15-157
0
J
D}J FOR EXPANDED MODE
:CC
•
Table 1. One·Shot Linear Mode Timing Table
ONE-SHOT PERIOD (msec)
Vcc = 15V
Input Digital Code
VREF = 15V
Vcc = 5V
c = O.l)1F
0.0176
1440
134
13.S
455
43
4.S
which is then converted to a voltage by a two transistor
current source and a capacitor. The voltage is then converted to a time delay or frequency by a timing capacitor
and the 555 timer.
o
~
DAC
ONE-SHOT EXPANDED MODE OPERATION
Range is doubled to 510 to 1 by operating the DAe in the
expanded range mode with the DAe's lOUT fed forward
from the reference input node of the DAe. Expanded range
mode timing is shown in Table 2 and in the graph of Fig. 2.
f--t--'1'- ' - - - - VCMP
•
v.
REF-1)2
C18~
COM.AC
INPUT
o
u~
::i
01
CH7
MUX
[
ADDRESS
...ow
z
52
CH2
CHI
--~:tr-C-'.T
___ v.v_
v. _ _
v-
R3
R2 11
~C.
[-=-~4'
_ __
••
>_.....__
:~.~==============~..J
••
•7
Figure 1. COMDAC* Encoder/Decoder Analog Circuit Board
'COMDAC IS A REGISTERED TRADEMARK.
PAGE 15-181
g~~ODE
TRANSMIT
(Eight-Channel Encoder)
RECEIVE
(Eight-Channel Decoder)
MUX-88
SMP-81FY
COMDACIi'oAC-86EX
(87)
CMP-01EJ
REF-02
MUX-88
COMDACIi'oAC-86EX
(87)
OP-16F
REF-02
from a programmable read-only memory frequency divlder_
The PROM was used to provide flexibility in changing the
clock waveforms if the user so wishes_ The resultant clock
waveforms are also described later; the circuit schematic is
shown in Figures 3a and 3b_ The PROM data is listed in
Figure 4. The digital interface is provided by using a standard B-bit, parallel-in, parallel-out latch updated as the successive approximation process is completed for each input
channel. The remainder of the circuit consists of t/le SAR
and the multiplexer address counters. A parts list for the circuit is shown in Figure 5. A complete circuit schematic for
the digital board is shown in Appendix A.
RESISTORS
R1
R2
R3
R4
R5
-
R6 R7 R8 R9 R10 -
20K
330
9_1K
10K
2_49K
2_49K
2_49K
1_5K
2K (POT)
1_0K
The boards are interconnected by use of four mini-dip connectors and cables, a 16-pin and 14-pin from each analog
board to the controller. The lead designations of the two
connectors are shown in Figure 6. The input and output
channels are accessible through "banana"-type plugs; this
allows optional connections from the transmission line in
order to try different types of filters and line interface circuits. The two analog boards require ±15VDC and "banana"
plugs are provided to interface to the appropriate supplies.
The control board requires +5VDC only. The entire system
layout is shown in block diagram in Figure 7.
CAPACITORS
C1, C2, C4, C7, C8, C9, C10,
0_1"f
C11, C12, C13, C15, C18, C19
C3, C6, C14, C16
10"f
C5
5000pf
C17
100pf
Figure 2_ Parts List - Analog Board
SYSTEM OPERATION AND DESIGN
. interface between the encode and decode sections_ The encoder clock design is a multiple frequency clock, the
usefulness of which is treated in a later section, generated
To achieve a workable system configuration, the encoding
and decoding operations were approached as two separate
designs. The entire transmission link was then connected to
complete the end-ta-end tests.
TO
ENCODE OAC·86
C1
CL:~---------,
CE PEau
3
DO
5 D1
4
e1
01 •
-I..
7 D'
0' 10
•
9 0303
16 04 74198 04 15
18 05
05 17
2D D6
06 19
21
07
22 D7
B'
B.
B'
B.
TO
DECODe
DAC·86
(e11
B7
CP
f---~::::::::::=-~r:~-~~:~'O~----1
ADDRESS
CLOCK
AD]
A1
Al
TO
INPUT MUX ADDRESS
C'
'I
2 eLK
QA 14
:DA
aa13
1K
..V
6 DC
-'l,fVI.-+-"'I
.."
:
CAYt"'5"-----t
MUX
~DRESS
QC 12
DO
:>c>--.....- - - - - - - - " I L D
__ r -
,.
>5V
AD] OUTPUT
TO
:
DB 74183
-'lNv.....WIr-l
+5Y
~
TO
,NPUT M~~ ENABLE
OUTPUT
~~x ENABLE
C.
:>O=--,~-'~j)o'=---1.544MHI
Figure 3A_ Encoder/Decode Controller
PAGE 15-162
.s.
r2
1.544MHz
10
QA 14
CLK
OR 13
r
~
•5.
ac
12
13
r2!
300
... t
,.
4
2
PE
D.
OA
• Da
6 Dc
DO, 3
12
741"A
4
DO.
ADC
00 11
ADE_ 007
CE
~
..!!.
ac
13
QD
..!! t- t-
CLK
ADDRESS CLOCK
V
2
10
1. .
O~ I-
SAMPLE PULSE
c.
OS
7 DD 74195
f-DO,
r'!DO,
ADD
~.
CLK
(0
DO,
11 ADa
CLR
...
'5'
74183
DOt
AD.
1f
~
7474
Q
•
13
12
11
SAR
6
CLOCK
4
.•
,
9
i
• •
or-
;----- 9
..!.!CLK
• •
~2 •
7474
4
3
cc~
ENCODEI
DECODE
HE
Ct
RST
13
........
z
Figure 3B. Encode Clock
C
III
III
I-
ADDRESS
DATA
(MSB-LSBI
ADDRESS
DATA
(MSB-LSBI
20
28
20
21
39
2B
23
2B
23
2B
23
2F
OC
00
OE
OF
10
11
12
13
14
15
16
17
27
27
2F
6F
67
67
6F
6F
67
67
6E
OE
00
01
02
03
04
05
06
07
08
09
OA
OB
0
Z
Z
0
CONNECTORS
PIN
#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
MSB = 008
LSB = 001
Address 18 - 1F - Unused.
Figure 4. PROM-Based Clock
C1 (C31
+5
+5
+5
VCMP
+5Gnd
+5 Gnd
+5Gnd
B7 - LSB
B6
B5
B4
B3
B2
B1
SB -MSB
Encode/Decode
C2 (C41
+5 Gnd
Sample Pulse
MUX Enable
AO -Address
+5Gnd
A2 - MUX Address
A1 - MUX Address
+5 Gnd
+5 Gnd
+5 Gnd
+5Gnd
+5Gnd
+5 Gnd
+5 Gnd
+5 Gnd
+5 Gnd
*C2 is 14 Pin - C1 is 16 Pin
Figure 6. Pin Designations - System Connectors
PARTS
PARTS
7404
7408
7414
7432
7474
7486
2
Figure 5. Parts List - Controller
74163
3
74188A
74195
74199
2502
1.544MHz Crystal
The accuracy of the encoder, Llle analog-to-digital converter,
is dependent upon several factors. The first, and most
significant, is the speed (settling time) of the companding
DAC in conjunction with the comparator. Other factors are
switching time of the multiplexer, acquisition time of the
sample-and-hold, hold-step settling time of the sample-andhold, and output noise of the sample-and-hold and
PAGE 15-163
~
U
::::i
Do
Do
C
II
MULTIPLEXER
AlD
SAR
CLOCK
SAMPLE ~-~----;HO:::;-;LD:-------'LANALOG
CHANNELS
IN
E~C~C::i 'L...!!!DE~CD!!!D~EJ--EiENrocoii[DiEElilsiBiBE!i"1---:--LLCLOCK
INPUT
ADg~s:
MUX
--,L_____--.JIF'--------
6.5!I,s
~_ _ _ SAMPLE. E~~~s~cl CHANNEL _ _
MULTIPLEXER
Figure 8. Encoder Timing Waveforms
ANALOG
)
CHANNELS
OUT
Figure 7. Eight·Channel System Layout
multiplexer. All of these characteristics had to be con·
sidered while developing the encoder circuit.
In a companded AID conversion, using a successive approx·
imation method, different digital bits require different settl·
ing times. There is a constant increase in the settling time
required as one goes from the sign bit to the chord bits and
then to the step bits. This increase in settling time is partially
caused by the scaled current sources used to design a com·
panding DIA and is most affected by the magnitude of the
voltage level being converted. So as the output currents of
the DAC·86 become smaller (at smaller voltage levels), the
comparator is less responsive. Also as the less significant
bits are clocked in, the situation becomes more critical
since progressively smaller current changes are provided to
force the comparator to change output state. The encoder
clock waveforms, shown in Figure 8, depict a system ap·
proach to accommodate these timing characteristics. The
governing design criteria was that a limited amount of time
is available to complete the successive approximation of the
analog Signal (for eight channels, with a sampling frequency
of 8kHz, this means 15.6,..s) and the optimum clock must fit
within this period. All functions (including sampling, en·
coding, switching) must therefore be completed with an ac·
ceptable accuracy, within this time constraint. To achieve
accurate data acquisition with the sample-and·hold, a sam·
pie pulse of 3.2,..s was used. Once the pulse goes from sam·
pie to hold, there is a waiting time required to allow the
sample·and-hold output to settle to the "held" value, 650ns
is the time added. Since the sign bit is the fastest tranSition,
the basic system clock (1.544MHz) is used for the first SAR
clock period. The clock frequency is then halved to clock in
the chord bits (B1, B2, B3), the next "slowest" transitions.
Finally, the clock frequency is halved again to allow for the
step bits (B4·B7), a frequency of 386kHz. The times required
for the different bit conversions are shown in Figure 8. The
SAR is reset during the sampling period and once the sam·
pie circuit has entered the hold mode, the input
multiplexer'S address is changed. This provides ample time
for the MUX to switch to the next analog input with little ef·
fect on the adjacent waveforms. In addition, to further
minimize interchannel crosstalk, a 20kll resistor to ground is
added to the multiplexer output.
To provide sufficient noise immunity from the sample·and·
hold to the comparator, a simple filtering circuit using a
100pF capaCitor is added. A 4.9kll resistor to +5V from the
comparator output aids in increasing the DAC-86 and
comparator speed. In order to test the encoder without add·
ing a decoder, a high·precision voltage source (DC levels)
was used as an input to one or more channels of the AID cir·
cuit. The data output (one byte every 15.6,..s) was sampled
and stored in a logic analyzer. By reviewing the samples for
each channel, and comparing the data from all channels of
the eight channel system, the effects of changes in the
clock on the accuracy of the deSign could be observed. By
inputting a steady·state value, the data out would not only
demonstrate the "conSistency" of the AiD conversion but
also make obvious any adjacent channel effects that were
produced.
The anaiyzer sampling also presents a method of initializing
the system components. By grounding all inputs and digitally
sampling the data bus output, the zero level can be set so as
to produce an alternating series of data bytes equivalent to 0
volts (10000000 and 00000000).
A similar design approach was used in developing an eightchannel decoder. In this case, the response time of the
DAC-86 and op amp offers little problem since an eight·
channel decoder is relatively slow. However, the accuracy of
the devices does become important. The design considera·
tions become, therefore, the nonlinearity of the DAC-86 in
PAGE 15-164
conjunction with the switching time and charge injection of
the multiplexer. The DAC·86 is manufactured to strict
linear specifications, which assures both excellent
decoding linearity and absolute accuracy. The multiplexer is
used both as a switch to demultiplex the output waveforms
and as a holding circuit by adding capacitance to the output
leads. One effect seen in the multiplexer is that as a channel
is switched off, there is a charge injected onto the output.
This charge is not normally obvious in a MUX deSign,
however, when working into a high impedance (such as a
filter) and with capacitors on the source leads (outputs), the
charge can add an offset to the waveform. To minimize the
effect, a large capacitor (0.1jLF or greater) is added. Since the
charge pulse is a short duration signal, the signal on the
larger capacitor will be less affected by the charge than if a
smaller component was used.
SYSTEM TESTS
Once the encoder and decoder were functioning separately,
the entire system was connected with the appropriate inter·
facing to allow for full·system transmission tests. The
measurements taken were the standard set of PCM specifl·
cations observed in the majority of data sheets for telecommunication oriented products. These tests included signalto-total distortion, gain tracking, Intelligible crosstalk, and
idle channel noise.
There are two different methods of performing the tests. For
the U.S. standards, a sinusoid signal is used as the channel
input and the measurements are taken around the base
(test) frequency. For the European tests, a pseudo-random
or "white" noise source is preferred as the Input signal. The
test results discussed here were obtained with the U.S.
testing procedures; similar test results have been achieved
using European test methods.
In terms of a system decoder design, this circuit could be
used for more than eight channels. The op amp and DAC·
86 are both capable of responding to more output chan·
nels. An eight·channel system was incorporated to remain
compatible with the analog board that is used in the
demonstrator. In order to decode more channels (>12), the
output capacitance on the demultiplexer would need to be
reduced. The other circuit components would remain the
same.
The test set-up for signal-ta-total distortion and gain traCking measurements is shown in Figure 9. The results are
plotted in Figures 10 and 11. As is seen, each test was performed with both the C-Message Weighting and the 3kHz
Flat response terminating configurations. The results using
the jL-law parts (DAC-86) are represented. In terms of signalto-total distortion, the system exceeds the recommended
standard at all input levels by 2dB or greater. The system is
also well within the recommended gain tracking limits for
both terminations.
The decoding circuitry can be tested separately by adding a
series of data bytes and monitoring the output channels.
The CCITT recommendation for testing PCM systems in·
cludes a method of testing a decoder by introducing a stan·
dard sequence of digital data words in order to produce a
1kHz sinusoid at a nominal level of OdBmO.* This method
proved useful in "debugging" the circuit design prior to at·
tempting the end·ta-end tests.
I
MULTIPLEXER
MULTIPLEXER
D/A
TO
DIGITAL
8 BIT
DATA
BUS
CHANNELS
ANALOG
IN
The crosstalk and idle channel noise measurements are
given in Figure 12. One consideration of the system design,
in terms of performance, was that the most difficult characteristic for a shared-channel system to minimize is the Intelligible crosstalk specification. The design is directed
CROSSTALK .•..... . ..... -75dB
IDLE CHANNEL NOISE ...... 21dBnc
(AVERAGE CHANNEL VALUE)
NOTES:
1. 1,8kHz SAMPLING CONDITIONS AID CONVERSION TIME
16.~s.
2.
AUDIO TEST ANAL VZER CONTAINS AC MESSAGE FILTER
AND 3kHz FLAT FILTER.
Figure 9. Eight-Channel Test Configuration
"Reference -
CCITI Sixth Plenary Assembly (1976), Orange Book Vol. 111·2
PAGE 15-185
DAe
86/87
..
MUX·
ANALOG
1
CHANNELS
OUT
II
..
IDLE CHANNEL NOISE
!
CHANNEL
NOISE
(dBmOI
CHANNEL
NOISE
(dBmOI
2
3
4
-66.9
-67.6
-67.0
-67.2
5
6
7
8
-62.6
-65.3
-67.0
-61.8
50
;i
!!.
z
fij
0
i
~
e
/.
.-.
40
#'
-,,'
Ij /
,
.
.-
.A
4
CROSSTALK
,/
FREQUENCY
/"
30
z~
~
300 - 2900Hz
2900 - 3400Hz
--CMBGWTG
,.LAW _____ 8KHz FLAT
INTELLIGIBLE
CROSSTALK
.....78dBmO
"-7OdBmO
20
Figure 12. Idle Channel Noise and Crosstalk
development. It should be noted that in terms of transmis·
sion testing, the demonstrator is an end.ta-end system. The
configuration presents the users with a complete circuit
enabling them to observe the individual device characteris·
. tics significant in producing a shared·channel design.
10
-40
-SO
-10
-20
-30
.10
INPUT LEVEL (dBmO)
Figure 10. Signal·To·Quantizing Distortion vs. Input Level
The completed eight·channel COOEC demonstrator is shown
in Figure 13, mounted in its carrying case.
,,,
,,
+1.5
,,
,,
,,
,
+1.0
\
,LAW - -
~
I
......
~
-0.5
-1.0
~
~
-
~ '7
I
~-
-1.5
-60
~MSGWT~
- - - - 3KHz FLAT
-so
-40
-30
-20
INPUT LEVEL (dBmO)
Figure 11. Gain Tracking
Figure 13. CODEC Eight-Channel Demonstrator
toward optimizing this measurement. The idle channel noise
is at the system recommended level when measured without output filtering. It is further reduced by adding a PCM
receive filter on the decoder multiplexer.
CONCLUSIONS
The circuitry just discussed is meant to represent one approach t6 designing an eight·channel, shared COOEC
system. It is not meant to be the only design, but provides a
working system upon which to base further engineering
The demonstrator provides a starting point from which most
characteristics important to both shared-channel and singlechannel designs can be manipulated to allow for improvements in transmission quality. To be able to develop a
realistic transmission design, the system engineer needs to
consider more than just the coder/decoder devices. A complete multiple channel system, such as the PMI eightchannel demonstrator, allows the user to observe the complete system performance as it is affected by the individual .
system components.
PAGE 15-166
»"lI
"lI
m
Z
~
X
»
TO ENCODE
DAC-86f87
le1)
S8~B2
81
B3
TOCMP·Ol
B4
B5
86 .....
87
)II \
74195
SAMPLE
PULSE
I
(C2)
TO
74199
SMP-81
acl I IADDRESS CLOCK
~
G)
...
m
!:
. .V
300
..V
300
~
,
D2
03
D4
Q4
D5
05
DO
DE
D7Q>01
.,
B2
B3
TO
DECODE
1M
B6
DAe·86/87
1C31
SIll
...7
!!l
AO}
TO
A1 DECODE
MUX-88
A2
(C4J
Cl. C2 ENCODE BOARD
Cl. C4 DECODE BOARD
Figure A-1. Circuit Schematic
II
APPLICATION NOTES AN-37
APPLICATION NOTE 38
PMI
FOUR-CHANNEL SHARED CODEC
by B. W. Berry
FOUR-CHANNEL SHARED CODEC
A four-channel CODEC assembled from LSI components is
a cost-effective digital transmission system requiring a
relatively small number of devices. The system makes use
of a single COMDAC@* companded DAC-86 or DAC-87 dlgltalto-analog converter for both encoding and decoding (see
Figure 1). The timing of the circuitry is compatible with ATT
and CCITT system specifications.
Each channel is sampled at the standard 8kHz rate. With
four channels this allows approximately 31.2"s to encode
the sampled analog input and to decode the received digital
signal for the same channel. To simplify the timing system
requirements equal amounts of time were allowed for encoding and decoding, thus permitting 15.6"s for the more
critical encode portion of the cycle. The encode/decode
clocking scheme for this CODEC was incorporated directly
from a successful eight-channel CODEC system which has
been published as PMI Application Note 37. One Qriginal
feature of the four-channel design was the use of dual eightchannel multiplexer ICs to switch the four channels. This
results in a system whose interchannel crosstalk is practically negligible. Crosstalk figures of -85dB have been
observed. This article describes the design procedure and
reviews the transmission characteristics of the completed
system.
0
Figure 1.
o.oo""F
Four~Channel
CODEC
CIRCUIT DESIGN
The analog circuitry required for a four-channel system is
shown in Figure 2. The circuit uses the same printed circuit
S/1i
.sv
4.9K
![
+sv
MUX-88
1.SK
"
SMp·81
20.
VOUT
r100PF
,.
2.49K
EJD·
EJD
9.4K
AD,
COMDAC®
O.1K
REF+
AD,
OAe·
111;/87
~O.D1"F
Xi"
10K
I[
IXiR .. HIGH FOR TRANSMIT (ENCODE)1
0 - - "" lEAD TO TIMING/CONTROL CIRCUIT
~ ANALOG GND
-:!:
Figure 2.
Four·Channel CODEC - Analog Board
·COMDAC· is a registered trademark of Precision Monolithic., Inc.
PAGE 15-188
DIGITAL GND
card as the transmit or receive sections of the eight-channel
CODEC demonstrator (with the addition of a second
multiplexer). The analog inputs all connect at the input
multiplexer (MUX-88) using alternating inputs, the output
(drain) of the MUX drives the SMP-81 sample-and-hold
device. Once the input level is held, the COMDAC@ (DAC-86
or 87), in conj unction with the comparator (CMP-01 ), begins
the analog-to-digital conversion sequence. A successive approximation encode procedure is used; this generates,
within the allotted conversion time (15.6,..s), an eight-bit
digital approximation of the analog level. The data byte is
available at the successive approximation register output
for the next 15.6,..s time frame. During this time the CODEC
decodes the incoming digital Signals.
The decode cycle begins as soon as the encode cycle is
completed. The DAC·86 i is switched to the decode mode
and an eight-bit data word is presented at its input leads,
presumably from some distant analog-to digital converter
through a switching matrix. As the DAC-86. is switched to
decode, the operational amplifier (OP-16) converts the out
put current of the DAC-86 into the appropriate voltage
level. The output multiplexer is switched to the proper
analog port as the decode procedure is initiated. On the output leads of the "de"-multiplexer, a hold capacitor is used to
provide an output holding function. The "staircase"
waveform is then available for filtering and the final subcriber interface.
As shown in the Figure 2, several circuit precautions were
taken to reduce the internal noise levels. Foremost among
these is the ample use of grounding throughout the analog
circuit. All power supply inputs to the ICs are bypassed with
capacitance (0.1,..F) to ground. In addition, any spare land
area of the board is filled with ground paths. The various
voltage return paths are kept separate except for one common location on the board at the supply input leads. For further noise protection, a 20kll resistor to ground is connected
to the drain leads (the common output or input) of both
multiplexers. This reduces the multiplexer output noise and
any crosstalk voltage feedthroughs. Also, in terms of the
multiplexers, the output MUX is addressed to a grounded
terminal (source connection) in between the active channels. This aids in minimizing the mutiplexer injection
phenomena (discussed in detail in Application Note 37,
describing the eight-channel CODEC design) and helps to
further reduce the device crosstalk. The significance of using two multiplexers in this design is to allow unused channels of the output MUX to be connected to ground. The active channels are then alternated, in terms of addressing,
with the grounded terminals. Addressing the multiplexers
requires only two of the address leads to be controlled by a
binary counter for data selection. The third address input is
either held active (as in the input MUX), or can follow the
system transmit and receive control signal (lead XlR, as in
the output MUX). The address sequence for the input MUX is
repeated through ports 4 to 7 (100 to 111), the most significant bit is held high and the two lower bits are counter outputs. This scheme allows maximum settling time for the
MUX since the next channel to be encoded is selected more
than 16,..secprior to the conversion. For the output MUX, the
two most significant bits of the address are the counter output leads, the least significant bit is the transmit/receive
lead (XlR). As is shown in Figure 3, the address sequence
(!l
registered trademark
XlR
OUTPUT MUX ADDRESS
011
101
101
100
111
110
IZ7ZZZZZ2'ZlJ
SYSTEM IN DECODE MODE
~
SYSTEM IN ENCODE MODE
Figure 3.
101
Four·Channel CODEC Sequencing
110
111
111
001
000
100
Multiplexer
alternates from active output port (even addresses) to
grounded ports (odd addresses). The counter is changed
while the MUX is selecting an unused (grounded) channel.
This type of sequencing reduces the interchannel interference of the MUX and greatly adds to the system's
measured performance.
To minimize sample-and-hold noise, a simple filter circuit is
added to the output terminal of the device. A similar approach was used in the eight-channel design. Another
feature in common with the eight-channel system is the use
of a 4.9kll resistor pull-up from +5V to the output of the
comparator; this decreases the switching time of the device
for the encode procedure.
The timing waveforms generated for the four-channel
system are based on the encoder clock used in the eightchannel CODEC. This clock circuit is shown in Figure 4. In a
companded AID conversion, using a successive approximation method, different digital bits require different settling
times. There is a constant increase in the settling time required as one goes from the sign bit to the chord bits and
then to the step bits. This increase in settling time is partially caused by the scaled current sources used to design a
companding DIA and is most affected by the magnitude of
the voltage level bei ng converted. So that, as, the output currents of the DAC·86 become smaller (at smaller voltage
levels), the comparator is less responsive. As the less
significant bits are clocked in, the situation becomes more
critical since progressively smaller current changes are provided to drive the comparator. A multi-frequency clock will
take advantage of these timing variations; such a clocking
scheme is shown in Figure 5. The governing design criteria
is that a limited amount of time is available to complete the
successive approximation of the analog signal and the optimum clock must fit within this period. All functions (including sampling, encoding, switching) must be completed,
therefore, with an acceptable accuracy, within this time
constraint. To achieve accurate data acquisition with the
sample-and-hold, a sample pulse of 3.2,..s was used. Once
the pulse goes from sample to hold, there is a waiting time
required to allow the sample-and-hold output to settle to the
"held" value; 650ns is the time added. Since the sign bit is
PAGE 15·169
III
.,.
1.S44MHz
aA
CLK
a8
ADa
74183
r
~
_f
ac
AQc
aD
ADD
-
i
aGO
DO,
Da
DO,
Dc
00,
f--
DO,
,---
CE
aA
oafac
aD-
f-
a
,0
(S/H)
ADDRESS CLOCK
(ADCLK)
r-
CLK
V
~
CLK
SAMPLE PULSE
J
Do 741H
DO,
ADE_ 007
t
PE
D.
74188A
CLR
... ...
DO,
.0.
p-
'f. .
I-- c-
7474
SAR CLOCK
(SARCPI
ii
aGO
i
.5V
.----
r-...
I...-.
~
...
Figure 4.
"'"
B
cc
V
~'k".~
~...
0.1
HE
(EIO)
ii
RST
7414
--.,.--~
1.544MHz
1.544MHz
01------'
~ LEAD SHOWN ON TIMING DIAGRAM
PROM Based System Clock
again to allow for the step bits (84-87), a frequency of
386KHz_ The SAR is reset during the sampling period and
once the sample circuit has entered the hold mode, the input multiplexer's address is changed_ This provides ample
time for the MUX to switch to the next analog input with little effect on the adjacent waveforms.
SA.
CLOCK
SAMPLE
0
ENCODEI
ar--- UECODE
7474
r....
::1J
elk
1
SAMPLE
L
HOLD
e:E'b~~ 1L._DE;;;;C-,-OD;.;;E---I
L
ENCODE (SBE)
CLOCK
INPUT
MUX
A~~~~---'L.___________~
O.85/o-
CRY
1 K ( LD
DATA SELECT
,--------------
I
-,
SUCCESSIVE APPROXIMATION REGISTER
---~
-----------5
I
I
110
SARCP
~
9
:L
Your
SBE
~u
7
I
14 1
S
~
CP
,
I
I
I
I
I
I
I
6
2
I
4
I
~
14
DATA WORD
,
•
10
2
I
5
I
11
SEL
14157
------;;
I
1::T:~~::~ f
1
13
I
r
~ B2
11
, I
SB
~
74157
5
.1
5
~ SB
13
111
CO
1
SEL
10
~
2502
0
I
I
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ JI
~ B4
r:--CD
~ B.
"?
z
c(
~
II)
W
-,-----------0 - - - LEAD TO ANALOG CIRCUIT
\
~ ON TIMING DIAGRAM
X/R
Figure 6_
I-
o
I
Z
Z
DIGITAL DATA BUS
o
~
o
SY~-EM CONTROL, HIGH FOR TRANSMIT (ENCODE)
Four-Channel CODEC -
Control Board
::::i
data byte, the DAC·86 is held in the decode mode (EID is
low), the output MUX is addressed to an active output port,
and the SAR clock is disabled (this register will hold the last
encoded data word throughout the decode cycle - it is not
cleared until a new input signal is to be encoded). The data
selector is directed to the digital system bus and the
decoding of the byte on the bus begins. As described, the
address leads of the multiplexers are programmed such
that the input MUX will always be directed toward the next
active channel, once the previous analog sample has been
held. But the output MUX does not connect to an active
channel until the decode cycle begins; during the encode
cycle only unused (grounded) ports are addressed.
cleared until after the decode cycle, an external register is
not necessary to hold the data for the decoding process.
The transmission tests that were completed were the
typical telephone network tests as described in the eight-
MUX
ADDED FOR DEMO CIRCUIT
1----;--'-0
0-1.,
1----"'T+-rO 0-,
~
I
0--'
I
II
l
o--~
SYSTEM TESTS
OUTPUT [
The system as configured in the block diagram (Figure 7) is
a complete four-channel CODEC. To perform the transmis·
sion tests, it was decided to use a Single CODEC circuit and
transmit data in a "Ioopback" configuration. As was men·
tioned earlier, the only Signal required from an external con·
troller is the XlR lead. This is generated for the test circuit by
halving the inverted ADCLK lead from the prom·based clock.
The system waveforms that result are shown in Figure 8.
These clock patterns can be correlated to the encode clock
waveforms in Figure 5 by comparing the ADCLK or the StH
leads. Since the successive approximation register is not
MUX
ADeLK
1-------'
o-------{>o~--r®l-i
a~---_
7474
eLK
o
Figure 7.
PAGE 15·171
XlR
a
Four·Channel CODEC Layout
Demonstrator
D.
D.
c(
+1.5
s/H
+1.0
ADCLK
f
+G.5
XlA
lit
!!
z
:c
t?
\1
OUTMUX
-
-.
.'
-0.'
ADCLK
Figure 8.
Four·Channel CODEC Timing
I
-1.0
Demonstrator
-.
-1.5
-50
- 3 KHz FLAT
... - - - - C MSO WTO
-30
-4D
..,--V
.'
-20
-10
+10
INPUT LEVEL (dBmO)
-50
Figure 10. Gain Deviation (Four·Channel)
--
-45
;
,~ ~
-35
~
-3D
-25
-20
...
r
~.
-40
iVL
~V
IDLE CHANNEL NOISE
4
Channel
1
2
3
4
INTELLIGIBLE CROSSTALK
Ilnp~\.
3KHitFLAT
.. ---- C MSGWTG
4()()'34OUHz
~/
-so
-40
no channel
had noise
level > 2d Brnc
Level
:s -B5dBmO
Figure 11. Transmission Measurements
(Four·Channel)
-30
-20
-10
+10
INPUT LEVEL (dBmO)
Figure 9.
Signal·To·Total Distortion (Four·Channel)
channel application information. The tests include signalto-total distortion, gain tracking, intelligible crosstalk and
idle channel noise. Again the test method used for the first
two tests was based on a sinusoidal input signal, as is common in the AT&T specifications, at a frequency between 400
and 3400Hz using a frequency-selective wave analyser. The
results of all. testing are shown In Figures 9 through 11.
It is of some interest to compare this data with the test
results of the eight-channel CODEC design. In particular,
the idle channel noise and the crosstalk measurements are
improved. This can be partially explained by the different
manipulations of the output multiplexer. This does however,
tend to point to the fact that the output MUX can be a
significant source of noise and cross channel interference.
Further data is certainly necessary, but these results do
point out an area of concentration for the system designer
wanting to improve system performance.
In terms of slgnal-to-total distortion and gain tracking, the
four-channel results compare favorably with the eight-
channel data and both systems exceed the AT&T requirements. Overall, the transmission tests pOint out that
using a single DAC·86 for four-channel transmitting and
receiving is a realistic approach and can comply with all
" system" standards.
CONCLUSIONS
The testing described in the preceeding pages demonstrates the feasibility of encoding and decoding four channels with a single DAC-~6_· The system has several advantages: 1) a smaller number of devices are required to complete the CODEC function than were necessary for the
eight-channel deSign, 2) the clock circuitry (prom-based timing generator) is common to all encoders, so on.IY a single
such circuit is needed for multiple ·CODECs. Both of these
factors contribute to reduced printed circuit board area for
multiple transmission channels. The devices needed for a
four-channel CODEC are listed in Figure 12. In terms of
package sizes only one device is larger than sixteen pins
(the DAC 86/87 is 18 pins) and three of the components are
only eight pins. This should make system layout fairly simple and allow relatively dense component packing. If channel monitoring is incorporated, then a single supervision circuit could administer several circuit packs in a system line-
PAGE 15-172
•
•
•
•
PARTS (COOEC + CLOCK)
Analog
MUX-88 E (2)
SMP-81 FY
DAC86 EX
CMP-01 EJ
OP-16 FJ
REF-02 EJ
Digital
7404 (2)
• 7408 (2)
7414
7432
7474
• 7486
74157 (2)
• 74163 (2)
74188A
74195
• 2502
+1.544MHz Crystal
up. The number of external leads is reduced in a fourchannel CODEC and the design is easily added to a busstructure data switching system.
The price per channel is still less than that being quoted by
single·channel CODEC deSigners although slightly more
than the eight·channel approach. (See pricing, Figure 13).
The sacrifice made in prlce-per-channel Is offset by the
gains in system architecture and board layout offered by a
four-channel shared CODEC. The shared channel CODEC
approach is a viable solution to producing a digital
transmission system. AN-37 shows designs at even lower
per channel cost.
* parts for CODEC
Figure 12. Four·Channel CODEC -
Parts
ENCODE/DECODE
CLOCK
Digital
$ 3.82
$ 4.12
PMI
Total
$19.90
$23.72
$ 4.12
per channel
$ 5.93
NOTE: Pricing Based on 100,000 Parts
Figure 13. Four-Channel CODEC -
$ 1.03
($0.17, when
using clock for
24 chan nels)
Costs
~
c
rn
...o
1&1
z
z
o
~
(.)
:::i
A.
~
II
PAGE 15-173
APPLICATION NOTE 39
PMI
COMPANDING DIGITAL·TO·ANALOG
CONVERTER
by Guido Pastorino
(FROM PMI DESIGN REVIEW NOTES -1975)
INTRODUCTION
A companding digital-to-analog converter (DAC) is the key
component in PCM CODEC systems. (CODEC is an acronym
for coder-decoder.) A CODEC performs the coding functions
which consist of an analog-to-digital conversion (ADC) of
the input analog (voice) signal and decoding, which consists
of a digital-to-analog conversion (DAC) of the received
digital input.
The DAC is used for both encoding and decoding; it is in a
feedback loop to generate the ADC functions. Voice signals
in telephony rElQuire a system with a very large dynamic
range. The Uynamic range (DR) of a CODEC is defined as the
rane of the largest resolvable signal to the smallest signal
which can be encoded. The dynamic range of the CODEC is
the same as that of the DAC used in either the decode mode
or in the feedback loop of the successive approximation
type ADC. The dynamic range of a DAC is simply the ratio of
its output for a linear input of one least significant bit (LSB)
to that of the largest, all "1s," input. This ratio is usually expressed in decibels using the equation:
IMAX.
DR = 20 IOg10-ILSB
where for a current output DAC IMAX is the output current for
all "1s" input and ILSB is the output current for one LSB input. Using this equation a linear bit DAC can be shown to
resolve a ratio of 2":1 therefore:
DR = 2010g
2"
10"1
pair whose input amplitude range is divided into steps of unequal widths, such that the width of the quantizing steps increase in proportion to the amplitude of the signal. To
achieve uniform signal to distortion performance a logarithmic transfer function is required. The word compand, (compand is an acronym for compress - expand) was borrowed
from analog systems to describe this non-uniform coding
system where quantizing and coding is such that step size
depends on the input amplitude.
COMPANDING PRINCIPLES
Companding requirements differ for different signal
distributions. As mentioned above, voice signals require
constant SID performance over a wide dynamic range. In
order to accomplish this the distortion must be proportional
to the signal level. This feat is best achieved by the use of a
logarithmic compression law. However, a truly logarithmic
assignment of code words is not physically possible since
this implies an infinite number of codes. Two methods for
generating practical implementations of logarithmic
transfer functions have been derived which have become industry standards. These methods are generally known by
their transfer functions which are called wlaw and A-law
respectively. Both of these transfer functions are normally
implemented with eight-bit non-linear DACs to achieve a
72dB dynamic range. This is the equivalent dynamic range
of a twelve-bit linear DAC. The wlaw and the A-law transfer
functions are described by the following equations:
~6"
The wide dynamic range requirements of a telephone
system require the equivalent dynamic range of a 12-bit
system or 72dB. However, this system would not be satisfactory for telephone voice transmission because of its excessive bandwidth requirements. With present day T1 type
transmission systems a 64kbits/sec data rate is required to
transmit each voice channel. The use of the linear system
would increase this bit rate to 96kbits/sec. This would provide more accuracy than is needed at the expense of excessive bandwidth.
For voice systems the most important criterion is the signalto-noise ratio. In a PCM system noise is due almost entirely
to quantizing distortion. Thus, a non-linear DAC has a nonlinear transfer characteristic to compress the analog signal
into a digital word and a complementary transfer characteristic to expand the digital words into analog signals with a
wide dynamic range. For a telephone system a CODEC requires a fairly uniform signal-to-distortion ratio over its entire dynamic range. Achieving this uniform signal-to-distortion
ratio over a wide dynamic range requires the use of nonuniform coding. A non-uniform CODEC is a coder-decoder
1n (1 +I'IXI)
w law
Y=
A-law
Y= 1 +1nAIXI
1 + 1nA
Y=
1n (1 +1')
AIXI
1 +1n A
sgnX
sgn X
sgn X
for-1,;X,;+1
for 1/A,;X,;1
for 0,;X,;1/A
These laws have unique signal-to-distortion characteristics
for each value of I' and A respectively. At present AD has
settled on a value of I' equal to 255 and CCID specifications
use a value of A equal to 87.6. Substituting these constants
into the original equation above obtain:
wlaw
Y=0.181n(1+I'IXI)
A-law
Y=0.181n (1 +1nIXI)
Y=0.18AIXI
sgnXfor-1,;X,;1
sgn X for 1/A,;IXI,;1
sgnXforO,;IXI=1/A
The wideband (unfiltered) signal-to-distortion ratio over the
useable dynamic range of voice transmissions is shown in
Figure 1. This plot does not represent actual system performance; it is instead, a measure of the distortion which
would be caused by an ideal quantizer.
PAGE 15-174
first two chords on either side of the origin have equal step
sizes, whereas, for the wlaw function, the second chord
after the origin has a step size which is double that of the
first. For all remaining chords the steps double in size for
each succeeding chord. This applies to both the wlaw and
A·law functions. For the A·law function the four chords
about the origin can be considered as a single segment so
that the A·law characteristic is sometimes referred to as being
a "13·segment" code. The A-law characteristic also differs
from the wlaw characteristic in the manner in which the
transfer function crosses the origin. The X·axis origin for the
wlaw is at "mid·step" while the X·axis origin for the A·law is
coincident with a "riser". This can be understood better
from the "blow·ups" about the origin of Figures 2 and 3.
- - - l3-SEGMENT A LAW
- - 15-SEGMENT!l "'255
40
-50
-40
-30
-20
INPUT SPEECH POWER RELATIVE
TO FULL LOAD SINUSOID (dB)
Figure 1.
Input Speech Power Relative to Full Load
Sinusoid (dB)
The practical implementation of the two transfer functions
Is accomplished by standardized piece-wise linear approx·
imations. The transfer functions are implemented in chords
or segments where the transfer function within anyone
chord is a linear staircase. Each chord has sixteen steps
and the size of the step in each succeeding chord is double
the size of the step in the preceedlng chord. There are nor·
mally eight chords numbered zero through seven in both
wlaw and A·law characteristics. For the A·law function the
DIGITAL
In order to obtain the best implementations ·of the transfer
function, companded DACs are constructed such that en·
code and decode functions are offset by one·half step. With
this technique the quantizing band for the encode DAC will
be centered about the decode value. This can be seen In
Figure 4, where the wlaw characteristics about the origin
are shown. (The A-law characteristics would be identical ex·
cept for the "mid·riser" phenomena at the origin.) As an ex·
ample suppose that, for Figure 4, an analog input whose
amplitude lies between levels 2 and 4 is being encoded. The
best quantizing code to assign to this entire quantizing
band is its mean value of 3. Thus the DAC used in the suc-
Y
OUTPUT (+)
II)
W
I-
o
Z
z
o
ANALOG
INPUT(-)
\
0
I
~
I~~~~?~) x
""~
CJ
:::i
Ii.
'~~"
~
OUTPUT (-)
ENCODE TRANSFER CHARACTERISTIC
(AID CONVERSION)
p=
BLOW UP ABOUT THE ORIGIN
Figure 2.
JI·Law Transfer Function
PAGE 15-175
255
DIGITAL
OUTPUT(+)
1 '\
ANALOG
INPUT(-)
o
\
ANALOG
\;-~.'"
.~.
OUTPUT(-)
ENCODE TRANSFER CHARACTERISTIC
(AID CONVERSION)
D = (1+LnIXII SIGN X
1+LnA
FOR....L::s IXI s1
A
D=~SIGNX
1+LnA
FOR Os IXI:S....L
A
A = 87.6
BLOW UP ABOUT THE ORIGIN
Figure 3.
A·Law Transfer Function
11.
sent the mean values of the quantizing bands which must,
of necessity, be centered about the decoder output values.
The end result is that a DAC used for decoding must be off·
set one·half step from the DAC used for encoding. This
situation must exist over the entire range of the CODEC. A
transmission system implemented with companding DACs
is shown in Figure 5.
COMDAC® SYSTEM DESCRIPTION
A block diagram of PMI's companding DAC is shown in
Figure 6. A single current output DAC is used to generate
outputs for either the encode or decode mode of operation.
,.,
Figure 4.
Jl·Law Encode/Decode Characteristics About
the Origin
MUX
cesSlve approximation feedback loop of the encode has out·
put levels which represent the quantizing band edges.
These can be referred to as decision levels. On the other
hand the DAC for the decoder has output levels which repre-
TRANSMITTER
Figure 5.
PAGE 15·176
RECEIVER
Transmission System Implemented with
Companding DAC
STEP
INPUTS
87 B6 B5 B4
negative switch which directs the output of the current out·
put DAC.
CHORD
INPUTS
83 82 81
58
E/O
This output will eventually end up at the positive (I Off or
10D+) outputs or the negative (lOE- or 10D-) outputs depend·
ing on whether the 56 pin is programmed to a binary "1" or
a binary "0". The encode·decode switch ElD determines
whether the DAC output shall be directed to the encode or
decode terminations as shown in Figure 6. In addition, this
same switch introduces the one·half step of offset current
required during encode.
REFERENCE
AMPLIFIER
,.
V-
Figure 6.
V+
VLe
Equivalent Circuit and Pin Connection Diagram
Each companding DAC can be programmed to operate as
either an encoder or a decoder by properly programming tM
ElD pin. The encode mode is offset one·half step from the
decode mode by means of the current generator which is
switched in during the encode mode. The reference
amplifier establishes the current reference for the current
output DAC. The sign bit pin (56) controls the positive-
A better understanding of the COMDAC® circuitry is ob·
tained by reviewing the previously discussed piece-wise
linear approximation of the companding DAC transfer func·
tion to the desired !'"Iaw or A-law transfer functions. Each
chord or segment consists of 16 steps numbered from 0 to
15. The size of the steps double in size from one chord to the
next as the number of the chord Increases. The chords are
numbered 0 to 7. In order to smooth out the characteristics
during the transition from one chord to the next, the step
current for step 0 of each chord is 1·1/2 times larger than the
current of the highest step of the chord immediately
preceding it. The succeeding 15 steps (steps 1 to 15) are
then two times the size of the steps of this previous chord.
These characteristics can be examined in Figure 7.
To implement the transfer function, the first chord (N = 0)
uses 16 equal steps each of whose size, 10 is 1/16 of chord
current source Ico for A·law, or 1116.5 of current source Ico
en
~
A·LAW
o
z
z
o
~-lAW
.~-r------.-IOUT = IPi + Slj
1.512
~
o
::::i
~
c
II
lOUT
(DECODEI
'12'1..,.
2
17- __+
Ip3 = leo +I C1 +IC2
lOUT
(DECODEI
Ip3 = IS ... le1 ... IC2
"L
11
le1" 16.511
Ii = STEP CURRENT SIZE
lei = CHORD CURRENT SIZE
IPi = PEDESTAL CURRENT SIZE
WHERE i = CHORD NUMBER
o THRU 7
lOUT = IPi ... Slj
WHERE S = STEP NUMBER
DIGITAL INPUT 81 THRU 87
Figure 7.
DIGITAL INPUT 81 THRU B7
Construction of the Companding DAC Transfer Function
PAGE 15-177
into the chord selector from the step generator Is equal to
16.5 step currents (16.0 steps for A·law) where a step current
is equal to the current step caused by changing the least
significant bit in the chord of interest. Note that this
satisfies the requirement of the equation for pedestal cur·
rent IpN. The step generator has the ability to sum current IE
Into the output mode to provide the one·half step offset reo
qulred when the system is operating In the encode mode.
This one·half step offset current Is controlled by the ElD pin.
The system is In the encode mode when the E/D pin is biased
to a binary "1".
for ,..Iaw. The next chord, N = 1, must begin at Ico + 1.51 0 for
both A·law or wlaw. Another way of saying this is that chord
N = 1 begins 16.5 steps from the origin. In order to ac·
complish this a pedestal current must be directed toward
the output whose magnitude is equal to Ico + 1.510- Chord C2
begins at Ico+ 1.510+ IC1 + 1.511 and ends at Ico+ 1.51 0+ IC1
+ 1.511 + IC2+ 1.51 2 and so forth. This process continues
with pedestal currents for each chord number N described
by the equation:
N-1
IPN=
E
N-1
E
(ICi+1.5Ij}=16.5
i=O
Ii
i=O
DETAILED CIRCUIT DESCRIPTION
note that Ipo = O.
All of the single pole double throw switches in Figure 8 are
constructed of bipolar emitter coupled transistors. One
such switch is shown as an example in Figure 9. When the
A functional diagram of a companding DAC which Implements the proper transfer function discussed above is
CONNECT TO Js fOR A-LAW
(TO GND FOR p-LAWJ
ENCODE CURRENT
IS
~+--------:------.----,
85
IPN
TO OUTPUT
CURRENT
SWITCH
MATRIX
STEP
GENERATOR
leN = 16.5 STEPS IN CHORD N
fOR wLAW. 16.0 STEPS FOR
A-LAW
CHORD CURRENT GENERATOR
fOR A·LAW ICO = le1 = 1/32 IC6 '" 1/32 'REF
..
Figure 8. COMDAC®
FOR wLAW leo = 1/64 IC6 = 1/64 'REF
Companding DAC Functional Diagram
shown in Figure 8, which operates in the following manner:
the reference amplifier sets the bias current for the chord
generator by means of IC7 which is a current mirror whose
output Is equal to 2IREF. Next, due to the operation of an
R -2R ladder which is described in a following paragraph,
1C6 is made equal to one-half IC7 and is therefore equal to
IREF· IC5 is made equal to one·half IC6 and so forth. From IC3
down to Ico a slave ladder is used rather than an R -2R lad·
der but the results are the same. The chord currents double
in size progressing from Ico to IC7 respectively (for A·law
however IC1 = IcO>. The chord selector is programmed from
the 1 of 8 decoder so that the chord identified by binary
chord number N on leads 8 1 to 8 3 will switch ICN to the step
generator. All other chord currents are switched to the
pedestal selector. The pedestal selector is programmed
from the same 1 of 8 chord decoder such that chords 10 to
IN -1 are switched to the pedestal selector output in order to
generate pedestal current IpN. All other chord currents are
switched to ground so that a pedestal current equal to the
sum of the chord currents from Ico to IC(N -1) will be directed
to the output current switch matrix as IpN. The ICN flowing
-------~--------v+
-----------=:1-------- BIAS
LOGIC
1AV(VlC)
INPUT
.---+--IS
GND
Figure 9.
PAGE 15-178
BIAS
----4..---+----......-
BIAS
------He:--7-----""""CCC"
Double Pole Double Throw Switch Implemented
with Emitter Coupled Transistors
logic input exceeds the logic level bias V LC 01 is turned off
and 02 is turned on. In turn 03 is turned off and 04 is turned
on thus effectively switching the current generator, shown
as an example, from the ground to Is. Conversely, lowering
the logic level input below VLc will switch the current from Is
to ground. The VLC Control permits the circuit to interface
with a large range of logic levels.
The chord current generator circuit is shown in Figure 10.
This circuit is the implementation of the chord current
generator previously discussed. 0 0 is forced to operate at
the reference input current IREF and OJ, with an emitter
resistor one·half the size of the emitter resistor of 0 0, will
then operate at 2I REF. O2 through 0 4 will operate at progressively smaller currents where each transistor operates
at one·half the current of the transistor to its immediate left.
To review this normal R-2R current·ladder function notice
that 04A and 04B operate at equal currents and that the sum
of their currents is equal to that of one transistor with an
emitter resistor equal to R. When the series resistor R is added
to the junction of the emitter resistors of 04A and 04B the
current of 0 3 will be forced to equal the sum of the 04A and
04B currents. Thus 04A current equals one·half the 0 3 cur·
rent. Now the current from 04A, 04B and 03 must all flow
through the next series resistor R. This current is equal to
twice that of 0 3; therefore it is easy to compute that the 02
current is twice that of the 0 3. The same reasoning may be
used to proceed down the ladder to show that each transistor in the ladder Sinks twice the current of the transistor
on its immediate right. The slave ladder consisting of Os
through OaA and OaB continues to halve currents for each
transistor proceeding to the right. However this part of the
chord current generator uses scaled resistors instead of the
R -2R ladder technique. Since 04B sinks constant current
from the slave ladder, and since all the current must flow
through the scaled emitter resistors, then the curent
through each transistor must be inversely proportional to
the size of its emitter resistor. By examination of the slave
ladder it can be seen that each transistor proceedi ng to the
right sinks one-half the current of the transistor to its immediate left. For the wlaw chord current generator .0aB is
simply diode connected such that the chord current for
chord Co is roughly one-half the current of chord C1. For the
A-law chord current generator, however, the collectors of
tranSistors 08A and OaB are tied together so that leo is exactly equal to IC1 . The currents flow to the chord current
generator from an array of bipolar single pole double throw
switches labeled "chord selector" in Figure 8. The actual
switches are not shown in this paper.
The Step Current Generator is shown in Figure 11. Again the
Single pole double throw switches which connect the step
generator to the output current matrix as shown in the companding DAC functional diagram are not represented. The
step generator is connected to the chord selector which
Sinks ICN. Ratioed emitters are used to divide the current.
The largest emitter is 16 times the size of the smallest emitter and therefore sinks 16 times the current. The A-law step
generator differs from the wlaw step generator in that each
chord begins with a riser instead of a step. This also applies
to the origin, therefore one-half step of current flows
(decode mode) even when the binary Input to the step
generator is "0". Step switches controlled directly by the
binary code connect the appropriate collectors of the step
current generator transistors to the output current matrix.
For both A-law and wlaw devices ICN is one of the pedestal
currents. The difference is that for the A-law device the
pedestal current is equal to 16 steps whereas, for the wlaw,
the pedestal current is equal to 16.5 steps.
II;
Z
C
NORMALIZED COMPANDING DAC OUTPUTS
til
It is convenient to generate tables of normalized values
which correspond exactly to the CCITT (Consultive Committee for International Telephone and Telegraph) specifications. The following tables are normalized to the smallest
DAC output which is equivalent to one-half step.
S
z
W
z
o
~(J
::::i
0.
0.
C
~:'12
__ A-LAW
I IREF
• a.S28mA -
,u-LAW
IC7
IC6
IC5
1.024
mA
0.512
mA
1.056
mA
0.528
mA
~
~
~
ICO
1C4
IC3
IC2
'Cl
0.256
mA
0.128
mA
64
,A
32
,A
16.0
,A
0.0
,A
0.0
,A
0.264
mA
0.132
mA
56
,A
33
,A
16.5
,A
8.25
,A
8.25 4 - _ II-LAW
~
~
~
~
~
as
Q6
Q7
aoA
CURRENTS
-4--- A·LAW
,A
~
ao.
lX
OR
NOTE:
v-
Figure 10. Chord Current Generator Diagram
PAGE 15-179
FOR A-LAW 088 COLLECTOR IS
CONNECTED TO DBA COLLECTOR
AND NOT TO ITS OWN BASE.
II
--
TO STEP SWITCHES
IE
8IM-----1E---------~--------_I~--------E_--------_E~--------£
~-LAW
STEP CURRENT GENERATOR
...--IS
.
TO STEP SWITCHES
8IM-----1~--------~--------_I~--------~--------_E~--------i(.
A.LAW STEP CURRENT GENERATOR
Figure 11. A-Law and j.I-Law Step Current Generators
j.I·Law Normalized Table
NORMALIZED DECODE OUTPUT (SIGN BIT EXCLUDED)
~
STEP
=
C chord no. (0 through 7)
S = step no. (0 through 15)
Ie. s = 2[2 C (S + 16.5) -16.5)
0
1
2
3
4
5
6
7
000
001
010
011
100
101
110
111
0
0000
0
33
99
231
495
1023
2079
4191
1
0001
2
37
107
247
527
1067
2207
4447
2
0010
4
41
115
263
559
1151
2335
4703
3
0011
6
45
123
279
591
1215
2463
4959
4
0100
8
49
131
295
623
1279
2591
5215
5
0101
10
53
139
311
655
1343
2719
5471
6
0110
12
57
147
327
687
1407
2847
5727
7
0111
14
61
155
343
719
1471
2975
5983
8
1000
16
65
163
359
751
1535
3103
6239
9
1001
18
69
171
375
783
1599
3231
6495
10
1010
20
73
179
391
815
1663
3359
6751
11
1011
22
77
187
407
847
1727
3487
7007
12
1100
24
81
195
423
679
1791
3615
7263
13
1101
26
85
203
439
911
1855
3743
7519
14
1110
28
89
211
455
943
1919
3871
7775
15
1111
30
93
219
471
975
1983
3999
8031
2
4
8
16
32
64
128
256
STEP SIZE
PAGE 15-180
~-Law
Normalized Tables
C = chord no. (0 through 7)
8 = step no. (0 through 15)
NORMALIZED ENCODE LEVEL (SIGN BIT EXCLUDED) Ic. s =2[2C (8+ 17) -16.5]
000
0001
3
3
3
4
001
010
011
100
101
110
111
35
103
239
511
1055
2143
4319
4575
6
39
111
255
543
1119
2271
0010
43
119
271
575
1183
2399
4831
0011
47
127
287
607
1247
2527
5087
0100
9
51
135
303
639
1311
2655
5343
0101
11
55
143
319
671
1375
2783
5599
0110
13
59
151
335
703
1439
2911
5855
0111
15
63
159
351
735
1503
3039
6111
8
1000
17
67
167
367
767
1567
3167
6367
9
1001
19
71
175
383
799
1631
3295
6623
10
1010
21
75
183
399
831
1695
3423
6879
11
1011
23
79
191
415
863
1759
3551
7135
12
1100
25
63
199
431
895
1823
3679
7391
13
1101
27
87
207
447
927
1867
3807
7647
14
1110
29
91
215
463
959
1951
3935
7903
15
1111
31
95
223
479
991
2015
4063
8159
2
4
8
16
32
64
128
256
STEP SIZE
A-Law Normalized Tables
NORMALIZED 'DECODE OUTPUT (SIGN BIT EXCLUDED) Ics =2N- 1 (33 + 2S) For N>O
Ics=2S+1 For N=O
000
o
0000
3
4
001
010
011
100
101
33
66
132
264
528
6
110
111
1056
2112
-----_._--560
1120
2240
0001
35
70
140
280
0010
37
74
148
296
592
1184
2368
3
0011
39
78
156
312
624
1248
2496
4
0100
9
41
82
164
328
656
1312
2624
5
0101
11
43
86
172
344
688
1376
2752
0110
13
45
90
180
360
720
1440
2880
0111
15
47
94
188
376
752
1504
3008
8
1000
17
49
98
196
392
784
1568
3136
9
1001
19
51
102
204
408
816
1632
3264
10
1010
21
53
106
212
424
848
1696
3392
11
1011
23
55
110
220
440
880
1760
3520
12
1100
25
57
114
228
456
912
1824
3648
13
1101
27
59
118
236
472
944
1888
3776
14
1110
29
61
122
244
488
976
1952
3904
15
1111
31
63
126
252
504
1008
2016
4032
-----------------------------------------
---------------------------------------------------------STEP SIZE
4
8
16
32
64
128
----------------------------------
PAGE 15-181
~
o
z
z
o
~
u
~
•
A-Law Normalized Table
ICS =2 N - 1 (34+2S) For N>O
Ics =2S+2For S =G
NORMALIZED ENCODE DECISION LEVELS (SIGN BIT EXCLUDED)
o
000
o
0000
2
3
001
010
011
100
101
110
111
34
68
136
272
544
1088
2176
5
0001
4
36
72
144
288
576
1152
2304
2
0010
6
38
76
152
304
608
1216
2432
3
0011
8
40
80
160
320
640
1280
2560
4
0100
10
42
84
168
336
672
1344
2688
5
0101
12
44
88
176
352
704
1408
2816
________6____~0_11~0__________1_4________4~6________~9~2________1_84________3_6_8________7_36________1_47_2_______ 2944
0111
16
48
96
192
384
768
1536
3072
8
1000
18
50
100
200
400
800
1600
3200
9
1001
20
52
104
208
416
832
1664
3328
10
1010
22
54
108
216
432
864
1728
3456
3584
11
1011
24
56
112
224
448
896
1792
12
1100
26
58
116
232
464
928
1856
3712
13
1101
28
60
120
240
480
960
1920
3840
14
1110
30
62
124
248
496
992
1984
3968
15
1111
32
64
128
256
512
1024
2048
'4096
4
8
16
32
64
128
STEP SIZE
2
The numbers in these tables are directly proportional to the
input reference current. However the exact relationship is
somewhat complicated. A reference current of 528pA for the
JL-Iaw DAC will produce a step size of O.5pA thus, for the
wlaw device driven by a reference current of 528pA, it is only
necessary to multiply ali the numbers in the normalized
tables by one-half step or O.25pA to obtain the output in pA.
The table tabulated below corresponds to a 528pA
reference.
/.I-Law Current Output Table
IDEAL DECODE OUTPUT CURRENT IN MICROAMPS (SIGN BIT EXCLUDED)
o
o
2
3
4
5
6
7
010
011
100
101
110
111
123.75
255.75
519.75
1047.75
271.75
551.75
1111.75
139.75
287.75
583.75
1175.75
000
001
0000
o
8.25
24.75
57.75
0001
0.5
9.25
26.75
61.75
10.25
28.75
65.75
2
0010
3
0011
1.5
11.25
30.75
69.75
147.75
303.75
615.75
1239.75
4
0100
2
12.25
32.75
73.75
155.75
319.75
647.75
1303.75
5
0101
2.5
13.25
34.75
77.75
163.75
335.75
679.75
1367.75
6
0110
3
14.25
36.75
81.75
171.75
351.75
711.75
1431.75
7
0111
3.5
15.25
38.75
85.75
179.75
387.75
743.75
1495.75
8
1000
4
16.25
40.75
89.75
187.75
383.75
775.75
1559.75
9
1001
4.5
17.25
42.75
93.75
195.75
399.75
807.75
1623.75
10
1010
5
18.25
44.75
97.75
203.75
415.75
839.75
1687.75
11
1011
5.5
19.25
46.75
101.75
211.75
431.75
871.75
1751.75
12
1100
6
20.25
48.75
105.75
219.75
447.75
903.75
1815.75
13
1101
6.5
21.25
50.75
109.75
227.75
4,63.75
935.75
1879.75
14
1110
7
22.25
52.75
113.75
235.75
4"/'9.75
"
967.75
1943.75
15
1111
7.5
23.25
54.75
117.75
243.75
495.75
999.75
2007.75
2
4
8
32
64
STEP SIZE
.50
'Vlrtual Decision Level
PAGE 15-182
A similar exercise will yield a corresponding table for the
A·law part. Multiplying all the numbers in the normalized
A·law table, for instance, will produce a table of currents for
a reference input of 512pA. A table based on 512pA
reference current will have a step size of 1.0pA and is
tabulated in the ,...Iaw current output table.
A·Law Current Output Table
IDEAL DECODE OUTPUT CURRENT IN MICROAMPS (SIGN BIT EXCLUDED)
CHORD
STEP
0
0
000
0.5
1.5
2.5
3.5
4.5
5.5
6.5
7.5
8.5
9.5
10.5
11.5
12.5
13.5
14.5
15.5
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
6
8
9
10
11
12
13
14
15
STEP SIZE
001
16.5
17.5
18.5
19.5
20.5
21.5
22.5
23.5
24.5
25.5
26.5
27.5
28.5
29.5
30.5
31.5
010
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
011
66
70
74
78
82
86
90
94
96
102
106
110
114
118
122
126
4
100
132
140
148
156
164
172
180
188
196
204
212
220
228
236
244
252
8
101
264
280
286
312
328
344
360
376
~92
408
424
440
456
472
4BB
504
16
6
110
528
560
592
624
656
668
720
752
784
816
848
860
912
944
976
1008
32
7
111
1056
1120
1184
1248
1312
1376
1440
1504
1566
1632
1696
1760
1824
1668
1952
2016
64
!!;
~
en
w
Reviewing the companding OAC functional diagram Figure
8 demonstrates the relatio!1ship between step size and IREF .
For a ,...Iaw device Ico equals 16.5 chord zero steps and for
an A·law device Ico equals 16 chord zero steps.I C6 is always
equal to IREF in either system. IC6 is then equal to 64 times
leo for a ,...Iaw system, and 32 times leo for an A·law system.
The step size can then be related to IREF by the following
equations:
step size = IREF/64 X 16.5 = IREF/1056 (,...Iaw)
step size IREF/32 X 16 IREF/512 (A·law)
=
=
DAC ACCURACY
Companding OACs must be manufactured to satisfy a unique
set of parameters. The performance of a companded OAC
used for telephony must satisfy the requirements of a com·
munication system on an end·to-end basis. A voice channel
is first encoded by one COOEC then decoded by a second
COOEC such that the system performance can be
measured on an audio·in·audio·out basis. The COOEC performance will be almost completely dominated by the Gain
Tracking requirement.
GAIN TRACKING
Now for a reference current of 528pA the step size for a ,...Iaw
system is 528/1056 or 0.5pA. For a reference current of
512pA the step size for an A·law system is 512/512 or 1.0pA.
These values concur with those used to generate the tables.
In the design of the PMI OAC·87 the biasing resistors were
not scaled to exactly integer values. This was done
deliberately to standardize somewhat on 528pA input
reference current for both A-law and ,...Iaw parts. The performance of the device is not affected, however the actual
scaling is somewhat complicated and will not be discussed
in this paper.
Finally If encode output tables were desired for current output they could be obtained by scaling to proper step size the
normalized encode tables or adding one-half step to each
value in the decode table, where the step size depends on
the chord number.
Gain Tracking refers to the ability of a system to track Its Input power level. The test is normally made with a system
such as that shown in Figure 12.
Gain Tracking is measured by monitoring the input and output levels in decibels. At an input level of -10BmO the output is recorded as the output reference level. For ideal Gain
Tracking, any change (in dB) of the input level must be
matched exactly by the same change in the output level.
Figure 12. Gain Tracking or SIN Test
PAGE 15-183
t5
z
z
o
~
u
:::;
IL
IL
•
c(
This condition is monitored over all input power levels of interest. The extent to which these power level changes differ
(again In dB) is a measure of Gain Tracking, also referred to
as gain deviation. The ATT/D3 Gain Tracking specification Is
show in Figure 13.
dB
+0.8
"
"
g
z
+0.2
~
~
~
"
-so
+.
-10
-37
POWER LEVELS
For PCM channel performance measurements, power levels
are characteristically expressed in dBmO. A reference level
of OdBmO is established by referencing to a code in the
digital transmission. The binary code pattern required to
establish a reference level of OdBmO can be found in the
CCITT publications. This pattern is reproduced in the PMI
Telecommunications Handbook for the readers convenience. The constant repetition of these binary numbers at
the normal sampling rate of 8kHz will produce a 1kHz
sinusoid at a OdBmO reference level. Starting with this
definition it can then be shown that a sinusoid whose peak
value is just at the system saturation level (all "1s" PCM
output) will have a power level of 3.14 and 3.17dBmO for
A-law and wlaw respectively.
+1.0
+0.6
+0.5
+0.4
and an RMS reading voltmeter at the output. Gain Tracking
masks equivalent to those found In CCITT publications are
shown in Figure 14.
INPUT
lEVEL
dBmO
-0.2
-0.4
-0.5
-0.6
SIGNAL·TO·DISTORTION MEASUREMENTS
-0.8
Signal-to-Distortion is a measure of the total distortion a
system will exhibit on an end-to·end basis. As with Gain
Tracking this measurement is normally performed on an
audio-to-audio basis. A typical setup for measuring Signalto-Distortion is shown in Figure 15. A wideband (3kHz) filter
may be substituted for the C-Message filter shown for some
tests.
-1.0
Figure 13. ATT/D3 Gain Tracking Specification
CCITT publishes two separate specifications for Gain Tracking. The apparatus used for making either of these tests is
basically the same as that used in Figure 13 except that for
the first part of the "method one" test the HP3551A would
be replaced with a suitable white noise source at the input
Figure 16 shows the ATT/D3 specification mask with the
performance of a PMI demonstration COMDAC@ based
shared CODEC system superimposed. This method of measuring Signal-to-Distortion is applicable to either CCITT or
ATT specifications.
dB
+3.0
dB
~
~~
dB
+1.0
+1.0
+0.5
INPUT
LEVEL
";+0.5
i
-o.s
~
!
-1.0
"
~
~~-'-
-55-SO
~
-40
I
-10
+j
-0.5
-0.5
(a)
METHOD 1: WHITE NOISE TEST SIGNAL
~
+0.5
INPUT
lEVEL
0
-1.0
~
~
(b)
METHOD 1: SINUSOIDAL TEST SIGNAL
-3.0
~~
~
METHOD 2: SINUSOIDAL TEST SIGNAL
Figure 14. CCIT Gain Tracking Specification
PAGE 15-184
~
INPUT
lEVEL
dBmO
DAC ACCURACY VERSUS GAIN TRACKING AND
SIGNAL·TO·DISTORTION RATIO
The analog portions of a PCM system usually make only a
minor contribution to either Gain Tracking or Signal·toDistortion errors. Thus, the major contribution to error is the
inability of the companding DAC to accurately follow the encoding format. The process of quantizing and coding will
cause some deviation from the ideal, however the errors
made by the ideal CODEC system will be well within telephony
specifications. To conform to the required Gain Tracking
and Signal-to-Distortion specifications the DAC output currents must conform as closely as possible to the ideal transfer function as tabulatE!d in the normalized tables. This corresponds to a specification of absolute error on the DAC
output c'urrent with respect to its binary inputs. The
DAC-86I87 companded DACs are guaranteed to plus or minus
one-fourth step from ideal values in chord zero arid to plus
or minus one-half step elsewhere. This information can be
transformed into tabular form by adding the allowable error
to the DAC tables. Either the normalized tables or the cur·
rent output tables can be used as a basis for this exercise.
1.02 KHz
SINUSOID
INPUT
DECODER
LOW PASS
FILTER
Figure 15. Signal-to-Distortion Test Setup
50
PMI1CODEC
DEMONSTRATION
PERFORMANCE
45
iii
~
z
0
40
;:
a:
J
...0
II)
is
....
...«
.~
35
I,"~
0
~
«
z
30
CI
iii
25
l'j
----.
1/,.-- ---- ~lJ
.. ,.
~
II)
W
I-
,"
o
Z
Z
o
u~
MINIMUM SYSTEM SPECIFICATIONS
A"/
:::i
II.
II.
C
/
/ILAW
- - CMSGWTG
3 KHz,FLAT
----
20
-50
-40
-30
I?z
c
...........
-20
-10
INPUT LEVEL (dBmO)
Figure 16. ATT/D3 Signal-to-Distortion Mask
PAGE 15-185
+10
III
APPLICATION NOTE 40
PMI
A BUFFER APPLICATIONS COLLECTION
by Shelby D. Givens
INTRODUCTION
This Application Note consists of a collection of circuits
which apply buffers to the solutions of a variety of problems.
As will be shown, buffers may be used to make filters, cur·
rent sources, cable drivers, sample and holds, high speed
instrumentation amplifiers, line drivers for multiplexers, current boosters for voltage references, and high speed voltage
output DAGs.
+ 38dB at 103Hz. The Figure 3 response is + 2.5dB at 200Hz
and -10dB at 50Hz. On the other hand, the Figure 4
response is - 9dB at 200Hz and + 2.5dB at 50Hz.
40
RESPONSE FROM
E1 TO VOUT
Rl = 2.4 MEGn
R2 = lOOn
= 100nF
Cz = 100nF
f o = 103Hz
30
INDUCTORS AND FILTERS
c,
20
The active inductor in Figure 1 is realized with an eight·lead
IC, two carbon resistors, and a small capacitor. A commer·
cial inductor of 50 henries may occupy up to five cubic inches.
":¥
'0
\
'\ 1'-0.
-'0
1/
-20
-30
loon
/
,0
'DO
'000
1(Hz)
l_
VOUT
O.l,uF
E1 '" 1 _
A,
w2R,R2C,C2 + jwR2C, (1 +
~)
10Mn
Figure 3. Response from E1 to Vout
L == R,R2C '" 100 HENRIES
RS = R2 '" lOOn
Rp = Rl = 10MEGn
ASSUMING eSTRAY (ACROSS RlI OF 5 pF THE UPPER
40
FREQUENCY LIMIT IS APPRQXIAMTEL V 7kHz.
XL = loon AT f
RESPONSE FROM
O.159H:l
E2 TO VOUT
30
Rl = 2.4 MEGn
R2 = loon
c, = 100nF
20
Cz = lOOnF
Figure 1. Active Inductor
fo'" 103Hz
":¥
The tuned circuit shown in Figure 2 uses the simulated inductor of Figure 1 (R1' R 2, G1) and C2. Depending upon
whether the circuit is driven at E1 or E2 the responses of
Figures 3 or 4 result. The resonant response in both cases is
'0
\
\
-'0
1\
-20
-30
'0
'000
'00
f(Hz)
VOUT '"
A2
~
lOon
E, e>----jCz
C,
I-~_-jl-
100nF
1
2" .jR1RZC,CZ
Figure 4. Response from E2 to Vout
A,
E2
INPUTS MAY BE AT E1 OR E2_ GRAPHS OF THE TWO
RESPONSES WILL SHOW ADVANTAGES AND DISADVANTAGES.
Figure 2. Tuned Circuit
(1+~)
_ _ _-I
100nF
2.4Mn
fo =
1+jwR2C1
l-w2R1R2C1C2+jwR2C1 (1 +*)
Figure 5 shows a low pass filter realized for fo of 1MHz.
What is remarkable about this filter is most IGs do not have
the full power bandwidth to handle 1MHz signals in the 5 to
10 Volt range, while the BUF-03 has a greater than 4MHz full
power bandwidth for a 20Vp. p sinewave. Similar comments
apply to the filter in Figure 6. In other words, the extreme
bandwidth of the BUF-03 extends the bandwidth capability
of certain classes of active filters.
PAGE 15-186
HIGH SPEED CURRENT SOURCES
R,
VOUT
Wo '"
(R1R~C1C2) 'I..
IF R1 '" R2 '" R, THEN
Q=
The BUF·03 in combination with an OP·16 produces a bipolar
voltage·controlled current source. The circuits shown in
Figures 8 and 9 were breadboarded and found to have rise
times of approximately 1!'5ec. Since the waveforms had
definite RC characteristics, layout was suspected as con·
tributing primarily to the rise times observed. Figure 8
shows the inverting connection, while Figure 9 shows the
noninverting connection.
IC1~C21'h
'.
H,
n
1.OMEG
1.02K
C,
pF
220
C2
pF
Q
110
0.71
E(!2V)
R,
R2
10kU"
1Oku"
R,
Vo
4021l
IL'" >5mA
VL
..
..
Figure 5. Low Pass Filter (High Frequency)
R3
10kU·
RL
C,
"';1.6ku
C2
V.N o-----II----<~--H-----.--_I
VOUT
R,
"MATCHED
Wo '"
so THAT ~
= ~
R1
R3
IL~ -i5·~
(R1R~'C2) 'h
vu
COMPLIANCE OF ABOVE CIRCUIT l.l
IS ±8V
WHEN E = ±2V AND RL" 1.6kH. NOTE THAT
Vo is ± tOV UNDER THESE CONDITIONS.
IFC,=C2=C,THEN
Q = (R1/R21'h
2
'.
H,
500K
pF
220
",
R2
n
n
2.05K
1.02K
CIl
a
W
Figure 8. Inverting Bipolar Current Source (High Speed)
0.71
Figrue 6. High Pass Filter (High Frequency)
R,
R2
101en"
lOkn"
R,
Vo
40212
IL = lSmA
VL ..
II
R3
10k12 It
EI±2VI
VOUT
"MATCHED SO THAT
IL.e=
E
~=~
R.
As· Ai
COMPLIANCE OF ABOVE CIRCUIT (.l VU IS ±8V WHEN
E '" ±2V AND RL '" 1.6ku. NOTE THAT Vo IS ±10V
UNDER THESE CONDITIONS.
'OOpF
Figure 9. Noninverting Bipolar Current Source
R1 = RZ '" 2Ra
C1 =C2=¥
Figure 7. Notch Filter at 4.5MHz
Z
Z
o
~
CJ
:::;
IL
~
The BUF'()3 can be used to make a 4.5MHz trap for use in TV.
This circuit is shown in Figure 7, and the elements are
chosen such that no capacitor is less than 1OOpF.
100pF
I-
o
DATA ACQUISITION SYSTEM APPLICATIONS
Because of the speed of these devices, the BUF'()3 and
OP·17 allow the fabrication of a high speed instrumentation
amplifier as shown in Figure 10. The output of the in·
PAGE 15-187
III
E,
R,
R2
lkn
10kn
+'OY
VREF
"OY
DIGITAL
OUTPUT
14-BIT ADC
VOUT
• MAXIMUM ERROR FROM BUF-01 IS ~v.
• RESOLUTION OF 10V, 14·BIT ADC IS 610tJV.
• BUF·01 RESOLVES 1/2 LSB OF 14-81T SYSTEM.
NOTE:
~ = ~ FOR
GOOD COMMON MODE REJECTION.
Figure 13. High Resolution ADC Input Buffer
R4A IS ADJUSTED FOR BEST CMAR.
Figure 10. High Speed Instrumentation Amplifier
strumentation amplifier will likely be multiplexed onto a
common data line. Here the BUF.Q2 or BUF.Q3 can be used
as the data line drivers because of their speed and current
capabilities. The connection for this application is shown in
Figure 11. The realization of a high speed sample and hold is
tion involves the BUF.Q3 and the DAC.Q8 (digital·to·analog
converter). Figure 14 shows how it is possible to develop
both VOU! and Vout. The output capacitance of the DAC.Q8 is
approximately 15pF, thus as Ro increases in value, so does
the settling time for Vout (and Voutl.
VOUT
MUX-OB
VOUT
MUX
OUT
"OUT
RL
47.
NOTE 1:
NOTE 2;
1/2 LS8 SETTLING TIME
;, 100nsec
STRAV CAPACITANCE AT MULTIPLEXER OUTPUT
NODE SHOULD BE MINIMIZED TO REDUCE
CHANNEL-TO-CHANNEL CROSSTALK.
A BUFFER WHOSE SLEW RATE IS TOO SMALL WILL
SYSTEM WILL DRIVE CABLES OR TWISTED PAIRS.
INCREASE CHANNEL·TO·CHANNEL CROSSTALK.
Figure 11. High Speed Line Driver for Multiplexers
Figure 14. High Speed Voltage Output DAC
possible using the BUF.Q3 and suitable analog switches.
The circuit shown in Figure 12 provides the highest speed
because there are no feedback loops to slow down the set·
tling times. Typically the sample and hold is followed by a
successive approximation analog·to-digital converter (ADe).
LINE DRIVER APPLICATIONS
If your BIFET "line driver" has the speed but not the stability
or the current capability to drive coaxial cables, its output
may be buffered with a BUF.Q3 as shown in Figure 15. Figure
ICHARGE OF BUF-03 IS ±6OmA. THEREFORE THE SLEW
RATE INTO A 5DOpF HOLD CAPAC!TOR WILL BE
120VI~SEC.
TtIUS THE SLEW RATE OF THE SAMPLE AND HOLD
CIRCUIT IS LIMITED BY THE CAPACITOR CHARGING TIME.
CAPACITIVE LOAD STABILITY OF BUF·03 MAKES IT
AN IDEAL INTERFACE BETWEEN BIFET OP AMPS
AND SHIELDED CABLES'
NOTE:
Figure 12. High Speed Sample and Hold
The BUF.Q1 is shown in Figure 13 as the input buffer for a
14·bit ADC. Because of its extreme accuracy, the BUF.Q1
can resolve 'hLSB of a 10V, 14·bit system. The final applica·
TO MAINTAIN ACCURACY IN THE BUFFER
RL> 1kn IS RECOMMENDED.
Figure 15. Convert BI F ET Into Cable Driver
PAGE 15-188
16 shows an alternative connection when better accuracy
and more current capability is needed. Note that the limita·
tion on Rl being greater than 1K does not apply in this case
since the added error caused by lower impedances is imbedded inside the feedback loop of the op amp.
BUF-02) to a load using a BUF-01. Single supply applications
can be realized using either the BUF-02 or the BUF-03 as
shown in Figure 18.
+20V
O.22pF
VOUT
lMn
V,N
O.22pF
0-----11--4----1
R,
GAIN '"
V~~T
"',
RL
21m
lMn
;. zoon
+~
"NEEDED FOR LOW
IMPEDANCE AT HIGH
FREQUENCIES
MAXIMUM LOAD CURRENT'" ±60mA (lOV -:-.2oon)
flOW AT VIN = 1.45Hz ) -3dB
flOW AT VOUT = 1.59Hz
Figure 16. Current Booster
ASSUME Y'N = lOV p.p SINE WAVE (5V PEAK)
THEN FULL POWER BANDWIDTH IS:
MISCELLANEOUS USES OF BUFFERS
An accurate buffer can be useful for isolating a reference
zener from load fluctuations. In this way the same zener can
be used in a variety of reference situations. The circuit
shown in Figure 17 can supply up to 10mA (SmA for the
V+
796kHz FOR BUF-02, AND
9.55MHz FOR BUF-03
Figure 18. Single Supply AC Buffer (High Speed)
CONCLUSION
IL = +5mA MIN
VR=VZ~VE*
REFERENCE
ZENER
"Ve = 300pV MAX FOR BUF-01
VE = 1.5mV MAX FOR BUF-02
Figure 17. Buffered Voltage Reference
While the list is by no means all inclusive, this application
note has attempted to point out some of the myriad of uses
for the IC buffer. In particular, the BUF-03 makes possible a
whole new class of high frequency filters and high speed
current sources. Many problems in data acquisition systems
can be solved by the use of buffers. In addition, the BUF-03
is useful in providing increased drive current, as well as the
ability to drive long cables without instability. Finally, the
versatility of the reference zener can be increased by using
buffers, and for AC applications the buffer can be used on
Single power supplies.
UI
W
t-
O
Z
Z
o
~
o
::::i
Q.
Q.
oC
III
PAGE 15-189
APPLICATION NOTE 41
PM
IMPROVED SHARED-CHANNEL
CODEC DESIGN WITH PMI's
NEW COMPANDING DACs
®
by B.W. Berry
DESIGNERS FACE CHOICE
The degree of improvement offered by these devices and the
present capabilities of a shared-COOEC system can be
demonstrated using the circuit configuration shown in Figure 1. This configuration, an eight-channel digital transmission system, was designed and breadboarded by PMI as a
vehicle for measuring the analog-input to analog-output
transmission parameters commonly used to specify COOEC
performance regardless of the particular system configuration.
Designers of telecommunicetions systems are faced with a
fundamental design decision; they must base the design of
digital voice transmission systems on either the use of a
COOEC shared over several analog channels or on the use of
one COOEC per channel.
Since 1976, users of PMl's shared-channel approach pOintto
the economical advantages of a system that incorporates an
encoder and a decoder capable of accommodating multiple
voice channels. Proponents of single-COOEC-per-channel
systems generally cite the straight-forward techniques involved In implementing this concept as the motivation for Its
selection.
Two of the components employed in the transmission system shown in Figure 1, the companding digital-to-analog
converter and the analog multiplexer represent improved
versions of previously existing products and are key contributors to the superior performance the system demonstrates
over previous versions.
The use of the shared-CO DEC configuration is appealing
because fewer integrated circuits per channel are required
and less circuit board area per channel is needed. Because of
its lower cost per channel and lower total system cost, the
shared-channel COOEC concept looms as the logical choice
for designers provided it can meet the performance needs of
their systems.
In the redesign of the companding OAC, it was felt that the
best results would be achieved by improving the device's
response within chord O. Two design goals were set: to establish a reasonable settling time within chord 0 and to provide a
guaranteed better than ±1f4 step linearity within that chord.
Excellent results were obtained for both ,..-Iaw and A-law
devices.
Recently, new telecommunication components were introduced by Precision Monolithics Incorporated that improve
the performance that can be obtained from a shared-COOEC
system; the availability of these devices could influence
future design decisions in favor of the shared COOEC concept over the single-COOEC approach. These newly developed devices, including the OAC-88 and the OAC-89 COMOAC. companding OfA converters, and the OMX-88 demultiplexer, not only provide performance which is superior to
previously existing products, they are also easier to apply.
The new version of the companding OAC typically settles
within 500ns, thus overcoming a restriction that had previously reduced the maximum number of channels for
encoding. The IC's nominally settle to within ±1f8 step of the
theoretical level in chord 0 and are 100% tested to be no
worse than ±1f4 step.
Because of testing time restrictions, the settling time is given
as a nominal specification. The guaranteed linearity specifi-
MULTIPLEXER
MULTIPLEXER
ANALOG
CHANNELS
MUX-88
IN
AID
DIA
TO
DIGITAL
DMX-88
8-BIT
DATA
BUS
200
F'igure 1. Eight-Channel Test Configuration.
PAGE 15-190
ANALOG
CHANNELS
OUT
cation, in conjunction with the nominal settling time data,
can provide the designer with the data needed to determine il
the performance needs 01 his system can be satislied.
When the earlier version of the output multiplexer was used
as a sample-and-hold and switch, it was lound that certain
characteristics 01 the device caused idle channel noise and
transmission degradation. An analysis showed that reduction of the charge injected during the switch turn-off would
enhance the performance 01 the device. The eflect of the
The new version of the clocking circuitry still employs a
programmable read-only memory (PROM) lor flexibility in
performing luture modifications and experimentation. However, the clock pattern is markedly changed. The new SAR
clock timing diagram is shown In Figure 2. As can be seen, bit
clocking is accomplished with a set 772 kHz clock. This
ADDRESS
100
loa
104
charge injection becomes important because of the capacitance added to the MUX output. This output drives a highImpedance load (the PCM filter) and without a discharge
path, the charge adds to the analog output being switched
through the multiplexer. Because 01 the use of an improved
BiFET switch structure, the new multiplexer exhibits a discharged only 1/4 011/5 01 the value for the previous device.
Tests reveal that the idle channel noise is reduced by several
dB when the DMX-88 is used as the output switch and
sample-and-hold. In addition, the reduced amount 01 charge
permits the use of a smaller value capacitor and thus
increases the number of output channels that can be
decoded.
110
100
114
L
SAMPLE PULSE
INPUT MUX ADDRESS CLOCK
lL-_ _ _ _---'
L
---u
SAR RESET IS)
DMX ENABLE (CC)
I
L
DECODER LATCH eLK
DEMONSTRATOR MODIFICATIONS
The most obvious system improvement provided by the
eight-channel system depicted in Figure 1, compared to an
earlier demonstrator developed by PMI (described in the PMI
application note AN-37). is a simplified encoder clocking
scheme. In the original circuit, additional settling time was
required because of the slower changing bits.
loe
SAR CLOCK
~~
____________~r
......-4.66-....1 ...
95••_.___- - - - - - •.1 - - - - - - -....~~
aJ SAMPLE, ENCODE 1 CHANNEL = 16.8pS
b) PROM CLOCK OPERATES AT 1.544 MHz
Figure 2. Encode Timing: DMX Control.
Ul
~
o
z
z
o
TO
ENCODE OAe-8I
Cl
CL~~:----------'
~
u
::::i
YCMP
I.
TO CMp·Ol -~""'.-...
3
CE
DO
S Dl
07
13
0,
12
OS
11
Cl
.2
••
••
••.,
"I
9 D3
18 D4
03 •5
02
18 D5
20 D6
06
22 D7
CP
i---------------~
~
.,
00
7 D2
2502 Q4
21
07
TO
DECODE
DAC88
II
(ell
.7
10
ADDRESS
CLOCK
2 elK
TO
INPUT MUX ADDRESS
C2
+,.
Pi
+••
,.
OA
I.
AD]
AI
12
--'VVv-+-""I
A2
TO
OUTPUT
MUX
ADDRESS
C4
CRYP'~5_ _~~~-~--------~
._ r--+SV
.:>c,::....-t---'9~O::"'--- 1.!44MHz
Figure 2A. Encode/Decode Controller
PAGE 15-191
~
TO
,NPUT M~: EN•• LE
OUTPUT
:~x ENABLE
c•
+5V
74183
U44MHz
elK
QA
ClB
,.
13
ac
12
co
"
3DO
10
r--~.,
1
741BBA
001 2
ADA
12 ADc
4 DA
1-_-+-..,--t-"'1
!-=----..,--t-,. 0 8
D02 3
8 De
D03 !-=-----_--t-,
17_________'-1
7 DO
13
DO:
"
ADs
DO
ADD
QA
C2
SAMPLE
PULSE
•
QC 13
5
74195
14
,.
ClB ,.
DO. •
ADDRESS .
CLOCK'
COI~'2~________~i
ADEceoo, 7
elK
1.
+5V
3DO
10
":'
ENCODE
DECODE
IIIIE
el
+5Vo-~~r-~----------------------~
Figure 2B. Encode Clock.
allows 9.1 "s (eight-channel rate) for encoding; the remainIng cycle time (6,5 "s) is used for sampling the analog signal
and holding the level to be encoded. The remaining cycle
time Is divided as follows: sample period, 4.55 "s; transition
'time between the hold signal and the sign bit acquisition,
1.95 "s.
The'sampling time for the new clocking scheme is longer
than It was for the old design (4.5 "s as compared to 3.2 "s)
and the hold settling time has Increased from 0.65 to 1.95 "s.
As a result, the values measured for gain tracking differential
(linearity) at low input levels (-55 dBmO) provide an Indication of the improved response.
Since the clocking pattern has been simplified, the number
of TTL gates needed is less than had been required by the
original configuration. An even Simpler clocking scheme can
be designed by replacing the PROM, address counter and
data latch with a "0" flip-flop and some additional gates. The
use ofaprogrammable clock generator, however, was
advantageous in demonstrating the effects of various circuit
components on the overall transmission performance. For
example, by increasing the sample time and thereby reducing the hold settling time (keeping the SAR clock the same
frequency), the system tends to show different characteristics. The gain tracking stays within spec, but slgnal-to-total
distortion Increases at levels below -40dBmO. The crosstalk
performance (adjacent channel) also deteriorates. Apparently both of these effects are results of the output settling of
the sample-and-hold device. The pOint is that by designing
with a system consisting of Individual devices the user can
more precisely determine those components that have the
greatest effect on system characteristics. The design can
then be adapted to maximize certain performance attributes
in lieu of other,less-lmportant characteristics. The system as
finalized in these notes is a compromise system, one aimed
at providing adequate performance In various applicaltons.
The final design modifications are left up to the Individuals
responsible for the specific systems.
In terms of differences between using the older OAC-66/87
and the new designs (88/89), the requirements actually differ
only Slightly. Both new devices (88/89) now have idle currents present on the selected output leads; these currents are
equal on both the positive and negative outputs and are
normally around 10"A. However, since both leads have
equal values, the effect on the output device Is essentially
zero change. The power dissipation is slightly higher for
both parts, but less than SmW per channel In a eight-channel
design. The OAC-89EX is now specified at a lower reference
current than the OAC-8S/87 or OAC-66. The new reference is
16"A less than the original value. The tests described here
were performed with constant reference current for both the
OAC-SS and the OAC-89. The effect on the A-law measurements means the full-scale output is 2079"A instead of
201S"A, Although all steps are slightly expanded, for the
purpose of the data collected here the reference current
difference Is negligible,
The normal testing configuration used was to provide a test
signal input in one channel and monitor the output of that
channel (or adjacent channels for crosstalk) with a PCM
receive filter and the prescribed receiver. The test diagram Is
PAGE 15-182
shown in Figure 3. It becomes important to ground all
unused encoder inputs to provide the proper termination. It
also is very important when laying out system boards to
generate sufficient ground planes and proper isolation
between analog and digital ground areas. The common point
ofthese ground areas should be as close to the power supply
as possible. Also "daisy-chaining" of ground returns should
be avoided. Careful consideration of grounding can help
improve all system parameters.
The transmission test results collected with this system are
shown in Figures 4 through 6. An example of results with a
different clock pattern is also presented. The improvement in
the redesigned CAC's becomes evident in Figures 7 and 6,
which show the faster encoder clock driving the older CAC66 and 67 components.
RECEIVER
(MI2807A
HP·36Ii1A
HP-368OA1
• UNUSED INPUTS ARE GROUNDED
• A·LAW TESTING DONE WITH PSEUOO-RANDOM NOISE
TRANSMITTER
SOURCE AS INPUT SIGNAL
• p·LAW TESTING DONE WITH SINUSOIDAL INPUT SIGNAL
(MI2807AI
MUX.aa
SMP-81
DMX-BB
OP-16
CMP-01
8"
SAMPLEI
HOLD
INPUT
MUX
DAC·
DAC·
B8/89
B8/89
SAR
REF-02
REF-02
1
'/8
OUTPUT
D/A
MUX II HOLD
DIGITAL TRANSMISSION
(lS.. BIT PARALLEL)
Figure 3. Test Configuration.
80
,.
0
V
/
-,.
OAC"" EX
TESTED WITH _
~Ni'D
0
-50
0
V
,
-80
-
/
V/
/
i"""'-
-40
-30
-20
INPUT LEVEL (dBmO)
I
•
o.
V-
.........
0
I
•
I
-0.
'0
-40
-30
20
'0
II
INPUT LEVEL (dBmOl
Figure 4. DAC-88EX Tested with Sinusoid.
I
j
z~
V r--- r\
\\
/.V
10-36
Ci
~
~-25
L. A7
"
6
~/
Ii
T=:~TH- r-
I I
NOISE
-60
~
-40
-30
-20
INPUT LEVEL (dBmDI
-80
-10
Figure 5. DAC-89EX Tested with Noise Source.
PAGE 15-193
J
-50
"'
-40
-30
-20
INPUT LEVEL (dBmOl
'0
0
70
00
1.0
9t'
D.S
~
";;
'""
MODI
Z
10
-<0
-
-40
-30
-0.5
HOLD SETTLING TIME IS SHORTENED BY
-10
-60
INPUT LEVEL (dBmO)
-50
-40
-30
-20
~SEC
-10
MODIFIED CLOCK
INPUT LEVEL (dBmO)
Figure 6. DAC-88EX with Altered Encode Clock (Reduced Hold Settling Time) .
..
I
DACia EX
0- -
1.0
TESTED WITH
I
~.,I@ -60
SINUSOID
D.S
I'-.
0
~
0
0;
............
~
";;
I'-..
Z
/
"
'"
// /
/
10
-60
-0.5
V
I
-1.0
50
-40
-30
20
10
60
INPUT LEVEL (dBmO)
-50
40
30
20
10
INPUT LEVEL (dBrnO)
Figure 7. DAC-86EX Original JI-Law DAC with Faster Clock.
~
0;
~ -45
~
~
~
~
"
V
2S
-15
;;
"
~
\
z·
o
\\
lI'""
~
r
@" +0. S
....-
•
-3
is
~
~
NOISE
TTED~r-
g -0.S
r--
-S
-60
-50
1\
~
z
OAe·B7 EX
/
-40
30
00
I
-1,0
CljK
-20
14
I
0.650
50
10
SAA CLOCK
\
OAC-8S EX
I~~~~~~Of~'~H
liED
OC
l\-
0;
........
08
04
20
60
10
INPUT LEVEL (dBmO)
Figure 8. DAC-87EX Tested with Noise with Faster Clock.
PAGE 15-194
/
"J
- 50
\
40
30
20
INPUT LEVEL (demO)
10
Comparisons of Idle channel noise measurements using the
MUX-88 and the OMX-88 are shown in Figures 9 and 10. It is
important to notice that these measurements were made at
the input to the PCM outputfilter. Collecting data at the filter
output is not feasable because the noise values are too low
for the equipment being used. To show the difference
between the new and old components, a measurement was
made that yielded some data. However, for both devices the
idle channel noise is well within the normal system guidelines. The test data shows the difference due to reduced
device charge injection of the OMX. Using a 10,OOOpF hold
capacitor produces at least a 1OdS Improvement for the OMX
and when the hold capacitor is reduced, the improvement is
even more obvious. The smaller hold capacitor allows the
OfA circuit to drive more channels. Since the current capabilIty of the multiplexer switch is limited, a smaller capacitor
means less charge-up time is required and a faster settling
time is possible. The "demultiplexer" allows the user the
option of reducing the hold capacitance without affecting
the idle channel noise performance.
IDLE
CHANNEL
NOISE
CHANNEL
MEASURED
1
2
3
4
MUX-88
5
6
7
8
2
3
4
5
6
7
8
}
10000pl
10000pf
10000pf
10000pf
10000pl
10000pf
10000pf
10000pf
All
Values
10000pf
10000pf
10000pf
10000pf
10000pf
10000pf
10000pf
10000pf
<-70dB
IDLE
CHANNEL
NOISE
HOLD
CAP
2
3
4
5
6
7
8
-57.2
-57.2
-57.2
-57.2
-57.2
-57.2
-57.2
-57.2
1000pf
1000pf
1000pf
1000pf
1000pf
4300pf
4300pf
4300pf
2
3
4
5
6
7
8
-68.6
-68.6
-68.6
-68.6
-68.6
<-70
<-70
-69.9
1000pf
1000pf
1000pf
1000pf
1000pf
4300pf
4300pf
4300pf
MUX-88
DMX-88
NOTE: MEASURED AS SHOWN IN PREV"'OUS FIGURE.
HOLD
CAP
-60.8
-61.1
-60.3
-61.1
-60.9
-61.3
-61.2
-60.0
DMX-88
CHANNEL
MEASURED
Figure 10. Idle Channel Noise.
;:
INPUT
CHANNEL
MEASURED
CHANNELS
CROSSTALK
(1.02KHz)
4
-72
-60
-60
-65
-85
-85
-78
3
2
8
7
6
5
2
8
7
6
NOTE:
5
1
4
3
VALUES MEASURED BEFORE PCM OUTPUT FILTER
WITH HP-355tA (-7OdB IS LOWEST MEASUREMENT)
FILTER
GROUNDEO{
INPUTS
AID
3
D/A
~
2
8
7
6
1
4
NOISE MEASURED HERE
Figure 9. Idle Channel Noise.
4
Another demonstrator design change was added to show
how additional reduction of crosstalk is possible through
proper control ofthe output multiplexer. The first design did
not make use of the enable function ofthe output switch. As a
new digital word was latched to the decode circuit, the output MUX address was switched. The timing involved in these
two sequences is such that some signal feedthrough is seen
due to the data latch and Of A circuit (OAC-88f89 and OP-16)
settling more quickly than the MUX switch can open. Performance is Improved by the MUX being disabled priorto the
analog channel being switched. This assures, by using lead
CC, that the MUX is completely open while the new decoder
3
2
8
7
6
5
-72
-80
-85
-85
-85
-84
-85
-70
-80
-85
-85
-85
-74
-72
-78
-82
-65
-85
-80
-75
• CHANNEL NUMBERS AS SHOWN ON ENCODER &
DECODER BOARDS.
• INPUT LEVEL'" OdBmO
• MEASURED WITH HP3580A SPECTRUM ANAL VSER.
Figure 11. Crosstalk.
PAGE 15-195
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10
.:. it
"'00
::r>
Sl
13
7474
~o
M'
ENCODEI
DECODE
I.
(en
TO
lk
PIN NUMBERS ARE AS USED IN PMI 8-CHANNEL
CODEC DEMONSTRATION SYSTEM.
IC1) CONNECTOR NUMBER:
Ct, C2 ENCODE BOARD
C3, C4 DECODE BOARD
(REFER TO 16AND 14 PIN CONNECTORS AS SHOWN
IN PMI AN-37)
MUX..aa
(04)
12
~vo
AJll~CODE
A1
TO
+5V~ENCODE
MUXEN
1<2)
ENCODE
DAC-88/89
ac ..... A2
~JJ
'" n
-0'
=n
=
a;
"T17'C
cO' _,
<:
"T1
~cE'
,-<:a;
!'>
-I
::r
CD
n
o
!aI»
;<=
3
!ll
'"<:
iii
3
CD
'"
!iT
I»
Cil
CONCLUSIONS
Thanks to the use of newly developed components, the PMI
eight-channel CODEC demonstrator reveals the performance
possible with a multiple channel digital transmission system.
As illustrated by the test results, the transmission performance has been improved from that shown in AN-37.
Moreover, the design is simpler and even more economical.
Working with an eight-channel system allows the designer to
investigate additional improvements in and advantages of
the multiple-channel approach. Because of this, PMI makes
a set of boards available (encoder, decoder, controller) to
any customer interested in investigating the advantages to a
shared-channel design.
The system is still the basic design presented in AN-37 and
the work described in that note has aided in continuing
improvement of PMI components. A complete demonstration system schematic is shown in Figure 12.
PMI is committed to providing telecommunication components capable of meeting and exceeding all requirementsfor
digital switching and transmission systems. We feel the
shared-channel approach provides economic and space
advantages over the use of single-channel CODEC's in many
designs. It has also been seen by several of our customers,
that since our designs use individual components, by properly specifying these parts, the overall system performance
can be guaranteed. This can provide savings in component
and board-level testing costs. The system designer needs
only to evaluate the PMI approach to become aware of the
possibilities it holds in terms of digital transmission system
design.
v-
MUX
EN·
ABLE
1
,-----------0
A2
,--_ _ _-;A:;;'
-<:
~~~.
~A=O-<
RESS
,--__
v.
l
ANA.
LOG
CHAN·
NELS
COMDAi<>:,,-~1_INPUT
y
z
""'::'-_ _ _ _ _ _ _- - '
c(
V.
B.
NOTE:
CH VALUE DEPENDS ON OUTPUT SWITCH;
PRESENT ON ALL OUTPUT PORTS.
Ul
W
l-
e
z
z
e
Figure 12B. Demo System Decode Board.
v+
~
v-
o
V+"
...~ (
CHANNELS
:::;
1:
0..
0..
IrV+
v-..-I~v-
*
CH'
CH'
CH3
c(
DIGITAL GND
CH2
~
CH8
CH7
ANALOG GND
CH.
CH'
MUX
{
ADDRESS
AD
A'
A2
MUXENABLE
SAMPLE PULSE
ENCODEfoECODE
TO
CONTROL
BOARD
D.lk
v+O----....- 4
--I
INPUT
(TO SAR
AND 8 BIT
LATCH)
330
REF-Q2
S8
B'
B3
B4
B.
B.
B7
Figure 12C. Demo System Encode Board.
PAGE 15-197
III
APPLICATION NOTE 42
PMI
A 1kHz, OdBmO
Standard Signal Generator
by B.W. Berry
The CCITT standards concerning line transmission include
a specification demonstrating the relationship between the
encoding laws (A-law or !,-Iaw) and a standard audio signal
level. The relationship is such that when a specific periodic
sequence of character signals are applied to the appropriate
decoder, the output will be a sine-wave signal at 1kHz with a
nominal level of OdBmO. The prescribed digital characters
are those represented in Tables 1 and 2.
While developing the multiple-channel CODEC systems, it
became useful to test the encoder and decoder portions of
the circuit separately. To complete such tests, a CCITTstandard signal generator was produced. The generator
consists of five TTL packages and is driven by an 8kHz
signal. The required digital sequence is simple to implement
as fourofthe outputs are constant values. Forthe remaining
active bits, a four bit-binary counter was used to produce an
appropriate sequence. As is shown in the schematic (Figure
3), the counter clocks from 0101 to 1100 and then repeats.
This sequence directly provides the output for bits 4 and 6
and the inverted bit 8. With additional logic, the remaining
bit, bit 1, is also available.
The usefulness of such a generator is seen first of all in
troubleshooting any preliminary CODEC designs. Secondly,
for PMI, it provided a small, easily transportable signal
source to be used in PMl's eight-channel CODEC demonstration unit. Using the digital signal generator in conjunction with a PMI DAC-88 or 89 and an OP-16 provides a analog
driver capable of producing the CCITT standard transmis-
sion signal. The completed signal generator schematic is
shown in Figure 4.
Table 1. A-Law
Character Signals
Transmitted Characters·
Bl B2 B3 B4 B5 B6 B7 BS
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
1
0
0
1
1
0
Bl B2 B3 B4 B5 B6 B7 BS
0
0
0
0
0
1
1
0
0
1
0
0
0
0
0
0
0
0
0
ClK
IK
aA
'5
Table 2. w Law
Character Signals
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
Bl B2 B3 B4 BS B6 B7 BS
0
0
0
0
1
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
·Transmitted Characters for wlAW, all bits are inverted.
13
DB
DC
a c 12
DO
aD
11
lD
L-__________________~----------~------~.B.
L-______- . B6
L-~·~--------------.B8
I•
.. o--.NV''-----......-------: ::
TRANSMITTED CHARACTER
~
0
0
1
1
0
0
Transmitted Characters·
Bl B2 B3 B4 B5 B6 B7 BS
,.
aB
1
0
0
1
1
0
0
0
0
0
0
0
0
0
*Transmitted Characters for A-LAW are obtained by inverting even bits of
Character Signals.
74163
8KHZ
0
~
IMI~I~I~I~IMIIDIMI
L-______...:. ::
Figure 3. Charater Generator
PAGE1S-19S
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
IK
330
IK
330
'5~D~'"~F~~~~CL'
L,
74163
74163
2.048MHZ
10
15
10
CRY
15
8KHZ
,.
8KHZ
74163
'5
"
'5 o-lW~------71
QA
14
Q S 13
ac
12
-+____________
aD~'~I__'-~______
~
I.
"5
I/)
W
I-
o
SIGNAL
OUT
Z
Z
o
~u
::::i
Q.
Q.
c(
Figure 4. 1kHz, OdBmO Sine-Wave Generator
I
PAGE 15-199
APPLICATION NOTE 43
PMI
THE DAC-76IN CONTROL APPLICATIONS
by Mike Parsin
This note describes a companding D/A converter that is
ideally suited for industrial control applications using 8-bit
microprocessor bus structures. Features, such as 4-channel
demultiplexing, a reference amplifier that accepts various
levels of DC or AC for multiplying, and both encode or
decode capabilities are on-board the COMDAC®. Twelve-bit
accuracy can be obtained with a logrithmic 7-bit plus sign
microprocessor compatible D/A converter. .
The DAC-76 is at its best when measurement and control
become critical as the signal approaches zero volts. Not all
control systems that require precise control need the accuracy of a 12-bit digital-to-analog converter over their entire
range of operation. In fact, the non-linearity of a 7-bit companding D/A converter can be quite an advantage.
COMDAC® CONVERTER CHARACTERISTICS
The term "companding" comes from compression/expansion which is used extensively in the telecommunication
industry. Compression is performed in the encode or
analog-to-digital conversion mode, and expansion occurs
during decode or 0/A conversion. The AID transfer characteristic is seen in Figure 1. Eight points which are referred to
as chords or segments are selected by a 3-bit binary code.
Within each chord are 16 steps selected by a 4-bit binary
code. Each chord segment is linear to 1I2LSB. Step size
varies from 0.025% in chord 0 to 3.2% (offull scale) in chord 7
(see Table 1).
CHORD
STEP INPUTS
INPUTS
~,...-........-,
DIGITAL
OUTPtIT (+J
B7 86 B5 B4 83 82 B1
E/D
IOE(+)
IOE(-)
1001+)
100(-)
DIGITAL
OUTPUT (-I
Figure 1. Transfer Characteristic
Figure 2.
DAC-76 Equivalent Circuit
Table 1. Step Size Summary Table Decode Output (Sign Bil Excluded)
CHORD
STEP SIZE
NORMALIZED
TO FULL SCALE
STEP SIZE
IN"AWITH
2oo7.75"A F.S.
STEP SIZE
AS A "I. OF
FULL SCALE
STEP SIZE
IN dB AT
CHORD
ENDPOINTS
STEP SIZE AS
A % OF READING
AT CHORD
ENDPOINTS
RESOLUTION
a ACCURACY
OF EQUIVALENT
BINARYDAC
0
2
0.5
0.025%
0.60
6.67%
SIGN + 12 BITS
1
4
1.0
0.05%
0.38
4.30%
SIGN + 11 BITS
2
8
2.0
0.1%
0.32
3.65%
SIGN + 10 BITS
3
16
4.0
0.2%
0.31
3.40%
SIGN+9BITS
4
32
8.0
0.4%
0.29
3.28%
SIGN+8BITS
5
64
16
0.8%
0.28
3.23%
SIGN+7 BITS
6
128
32
1.6%
0.28
.3.20%
SIGN+6BITS
7
256
64
3.2%
0.28
3.19%
SIGN+5 BITS
PAGE 15-200
COMDAC® DESCRIPTION
The OAC-76 contains a logrithmic current output O/A converter, a 4-channel demux, and a reference amplifier. The
reference amplifier accepts bipolar inputs and sets the converter's full scale output range from 0 to 4.2ma. This output
current can then be adjusted by the digital input code described earlier. Inputs B1 through B3 select the chord while
B4 through B7 select the steps within the chord (see Figure
2). A unique switch is used in the demultiplexer section that
can be programmed for encode/decode (E/O) select, or
polarity of a bipolar signal selection with the sign bit (SB).
The combination of both ElO and SB results in the 4-channel
demultiplexing capabilities. The COMOAC® versatility becomes quite apparent in Figure 3.
Because the nature of O/A converters is to exhibit full scale
minus 1 lSB when all bits are on, 1I2lSB is added in the
encode mode to insure full scale accuracy. This corrects the
error in encode operations but also means there is a 1I2lSB
error between 100 and 10E (Figure 3a) in demultiplexer
applications.
sa
INPUTS
TO SERVO MOTORS,
CONTROL VALVES,
o-+'.::O::.D(...,+J~ ~:;~:~~R:6LD
o--I-''''''-'-I~ AMPLIFIERS, ETC.
£Ie
S8
STEP
INPUTS
Figure 3c. Nonlinear Coding
MICROPROCESSOR COMPATIBILITY
WITH 8-BIT /lP'S
Since the COMOAC@ has 8 digital inputs, all data transfers
can occur in 1 byte instead of 2 bytes required for 12-bit 0/ A
converters. Another bit provided for encode/decode is a
control function and does not affect data transfer speeds.
Figure 4 shows how simple it is to interface popular I'P I/O
adapters with 8-bit ports. Anotherfeature is the logic control
pin (VlC) which can be used to enable the device (logic "0")
or disable with a logic "1 n. The COMOAC@ accepts all popular logic levels by applying the logic threshold voltage at this
pin. The VlC is low for TTL applications.
E/D
o--V=~
CHORD
INPUTS
Settling time of the OAC-76 is typically 1 microsecond. This
is within the cycle time of most microprocessor's.
OUTPUT SELECTION
(I)
1001-1
100(+)
loe(-)
III
I-
o
Z
Z
loel+)
o
Figure 3a.
Demultlplexlng
~
MICROPROCESSORS
8080
650X
8085
6800
u
::::i
lao
!:i
III
P8l
...I
;
g
~
PBO
PA7
~------r-----~
§"
COMDAC«
DAC·76
~_ _.... OUTPUTS
VREF
NOTES:
1. 6820 SAME AS 6620.
.
2. 8266 IDENTICAL TO 8155 fOR PORTS A AND B IN MODE 0.
3. 6820 (66201 IDENTICAL TO 6622 PORTS A AND B FOR SIMPLE DATA TRANSFERS.
Figure 3b.
Encode/Decode for Measurement and Control
Figure 4.
PAGE 15-201
Microprocessor Interface
COMDAC® APPLICATIONS
This circuit is ideal when usually low signals are present at
the sensor. For example, when measurement of a process' is
typically+100·C+I-10· C, but can range from 75·Cto 1000·C.
The alarm is set to trip at 500· C. In this case the COMDAC®
accuracy should be greatest from 75·C to 110·C, a 35·C
range. The DAC must have a dynamic range equivalent to
925 degrees, but only the 35 degree range need be accurate.
When choosing between a linear or a logarithmic D/A converter, two factors should be considered. The first is that the
error signal in control applications is far more important than
the absolute value. The second is that low level signals are
more critical than large signals, although a wide dynamic
range is still a requirement.
----
~~
CH 1
VRI+)
10E( I
10D(+1
~
~
DAC·76
"
100H
+lOV
REF ..(n
VR( I
COMDAC~
B1 - 87
51<
+15V
V
2.5k .1
10el+1
1
1M
7
+5V
CH 2
5k
ANALOG INPU TS
(-5mVTO-5VI
2.5k
I
J
1M
V
r-l
N3904
51<
]
CH 4
'"
1
1M
I
7
2.51<
-
I
+
I
1M
I
t(".,. ,(').
~
w
'"
...
"' 11
+
1
PBl
I/OBl$
PORT
/'\..
'----2.51<
PBO
10k
"'7
CH 3
PAD - PA6
~
+
"a:
~
B085 .p
15
a:
...
z
",87-
I
NOTE:
2.5k RESISTORS SHOULD BE MATCHED
TO 0.01%.
L+
L-
"i7
":"
Figure 5. Four Channel Data Acqulstlon System
DATA ACQUISITION
A four-channel Data Acquisition System (DAS) is shown in
Figure 5 which is unique because only two linear chips are
needed. Initially, 1/0 port PA is reset and port PB is addressed
at PBO and PB1 to select 1 of 4 input channels. The computer
then counts up from zero at port PA until the COMDAC®'s
output is equal to the analog input voltage at the selected
comparator. Since the CMP-04 quad comparator has open
collector outputs, these outputs are OR'ed together and an
end-of-conversion is signaled when the selected comparator
output goes low (Figure 5a). The count latched in port PA is
then the digital equivalent of the analog input. All four channels can be selected this way with the resulting digital data
stored in memory.
Analog inputs ranging from -5 millivolts to -5 volts can be
measured. To guarantee that the CMP-04 output is normally
high, at least 5 millivolts is required at all channels.
RAMP VOLTAGE
OUTPUT
END·OFCONVERSION
Figure Sa.
PAGE 15-202
Data Acquisition Timing Diagram
processor which is periodically monitoring the sensor's
output through the DAS. The processor then determines the
error between the setpoint and sensor. This "offset" is then
sent to the COMDAC® for proper valve positioning. The
offset current is "summed" with the DAC-08 at the amplifier.
A logrithmic DAC will then trip the alarm at 500° C, measure
to 1000°C, and give a very accurate reading from 75°C to
110°C. Keep in mind the dynamic range of the COMDAC® is
4000:1 or 72db (excluding the sign bit).
VALVE CONTROLLERS
A "reset time", which is the time between valve repositioning,
is determined by the processor.
A programmable controller (PC) is shown in Figure 6. To
complete a "control loop", the data acquisition system just
described and the PC are required. Today's distributed
systems need mini or microcomputers at remote stations to
operate the control loop. The system described here uses
two DAC's to position the valve opening. A linear DAC-08
makes the gross setpoint adjustment while the COMDAC®
makes the fine adjustment to 0.025%.
PROGRAMMABLE MOTOR CONTROL
Another popular application is the motor controller. Here a
DC motor (Figure 7) is driven from the COMDAC® (requires
a power amp). Speed is directly proportional to the voltage
across the motor. The sign bit determines the direction of
rotation and the 7 magnitude bits determine motor speeds.
For servo applications a shaft encoder can be used to close
the loop.
The operation of this circuit (Figure 6) is straight forward.
When the process changes, it is detected by the micro-
FROM
COMPUTER
CAe·os
TO VALVE {
OFFSET
#2
....,.
Z
CC
CQMDAC,";
DAC·76
III
W
l-
e
z
z
e
DIGITAL INPUT
SIGN BIT
~
(J
FROM OTHER ,uP'S AND HOST COMPUTER
IN DISTRIBUTED SYSTEM
:::i
11.
11.
cc
Figure 6.
Programmable Controller In Distributed System
VREF
III
O----Nlt---I
I/O
~RT ~------~~--------~
FROM SHAFT ENCODER
Figure 7,
Programmable Servo Motor Controller
PAGE 15-203
PMI
APPLICATION NOTE 44
COMPOSITE BUFFER PROVIDES
SPEED, ACCURACY
by Scott Bernardi and George Erdi
INTRODUCTION
Suppose a particular operational amplifier Integrated circuit
satisfies all of the requirements for a voltage follower application except for speed. Instead of searching for a faster
op amp, a design engineer may be able to obtain the desired
speed by placing a fast buffer, such as the BUF-03, in the
feedback loop of the op amp. The resulting composite
amplifier maintains the op amp's accuracy while enhancing
its speed.
The BUF-03, possessing a bandwidth of 63MHz, is well
suited for this type of use. In Figure 1, it is shown in the
feedback loop of an OP-07, an industry standard for applications requiring high DC accuracy but also a device with
limited speed. The compOSite configuration is a fast and accurate noninverting unity-gain amplifier requiring only two
external resistors.
OP-07. The circuit in Figure 1, using an OP-07E (prime grade,
commercial-temperature version) and a BUF-03F (commercial grade, commercial-temperature version) boasts a Vos at
VIN = OV of +30,N, and a gain error (VIN - Your) with a
1,OOO-ohm load of five parts per million (50,N) at ±10V.
The AC performance of the composite amplifier is that of
the BUF-03. One of the main advantages provided by the circuit arrangement is that the BUF-03 remains stable with any
capacitive load whereas the OP-07 requires a 50-ohm
decoupling resistor with CL greater than 500pF. Also, the
BUF-03's 60-70mA driving current will slew large capacitances easily (1,OOOpF and 2k ohms at 60V/p,s for a ±5V
pulse). This is illustrated in the waveform shown in Figure 2.
The slew rate of the system with CL = 10pF (probe
capacitance) is 220V/p,s as revealed in Figure 3.
+5V
OV
V ,N
-5V
Figure 2. A Slew Rate of More Than 6OV/p.Sec Is Obtained
with an RL of 2kO, a CL of 1,OOOpF and SOmA of
Driving Current.
L-----''--o -15V
Figure 1. Use of the BUF-03 and the OP-07 as a
Composite Amplifier In a Noninverting Unity·
Gain Amplifier.
+5V
CIRCUIT OPERATION
In Figure 1, input signals of up to ± 10V are applied to both
the input of the BUF-03 and the non-inverting input of the
OP-07. The OP-07 reduces the VIN - Your error of the
BUF-03 by driving its null terminal, rather than the input of
another op amp as is commonly done. Resistors R1 and R2
form a voltage divider which enables the output of the OP-07
to remain in Its active region while modulating the BUF-03's
null terminals (nominally at + 14.3V).
The DC errors of the composite circuit, including input offset voltage (VOS), change of offset voltage with temperature
(TCVos), power supply rejection ratio (PSRR), and gain error
(output regulation with load) are reduced to those of the
OV
-5V
Figure 3. Very High Slew Rate Is Achieved with an RL of
2kO and a CL of 10pF.
PAGE 15-204
In a composite amplifier arrangement, each of the devices
dominates the characteristics at one of the two frequency
extremes and a smooth transition of characteristics takes
place in between.
the 2kHz to 10kHz region, depending on load conditions.
There will be a point (up to the transition frequency) where
the combined performance of both devices is better than
either device individually.
If only low·frequency signals are to be processed, an OP-07
connected as a voltage follower might as well be used
alone, unless of course, large capacitive load handling
capability and large load currents are required. At higher frequencies, the OP-07 cannot respond fast enough to drive the
BUF-03's null terminal correctly, resulting in improper gain
error cancellation. However, even the BUF-03 alone has a
typical gain error of onlyO.5% for a ±10V input with 2k-ohm
load (using the BUF-03F). The transition frequency occurs in
The BUF-03 can be used as described with virtually any op
amp in voltage follower applications to provide speed
enhancement without sacrificing DC accuracy. This Is true
even where a high-speed op amp is already being employed,
and still faster speed is desirable.
CONCLUSION
:;
z
cc
rn
w
I-
oZ
z
o
~u
:::;
a..
a..
CC
III
PAGE 15-205
PMI
APPLICATION NOTE 45
TIME SHARING PERMITS DESIGN OF
CONTROLLER WITH SINGLE DAC
®
by Mike Parsln
INTRODUCTION
CHORD
INPUTS
The DAC-76 COMDACG' Companding D/A Converter Is a
monolithic IC containing a multiplying logarithmic D/A converter with a demultlplexed output for encode/decode
switching.
sa
83 B2 81
Eto
This application note describes the use of a single DAC-76
In the deSign of a converter instead of the use of one IC for
analog-to-cllgital conversion at the Input and another IC for
digital-to-analog conversion at the output (the conventional
way of designing a controller).
In the controller to be described In ·the following
paragraphs, the DAC-76 not only multiplexes between encode and decode, It also compresses 12-bit accuracy Into a
7-bit format. Its seven bits plus sign make the DAC-76 an
ideal interface for 8-blt microprocessors.
13
v·,
v-
VLe
THE COMDAC
REGULATOR
OUTPUT
(DIE ONLY)
_
-
DIGITAL
GROUND
Figure 5: In PMI'. RPT-81 and RPT-82, equalization and amplification of the Incoming pulle train take. place through an
amplifier with an external network controlled by feedback.
~
~~
W\IVV
INPUT
PREAMP OUTPUT
(COMPARATOR
THRESHOLDS)
..flI1J1..JlJL
FULLWAVE REFTIFIER
PEAK DETECTOR
LOGIC THRESHOLD
L-J
LJ
----u--u~
OSCILLATOR
OUTPUT
LOCKED TO
FULLWAVE
RECTIFIER
REGENERATED
CLOCK
T+ OUTPUT
-y-y-y-y-y-
STROBE
LOGIC THRESHOLD
T- OUTPUT
---Il
FF+ Q
rL
FULLWAVE
RECTIFIER OUTPUT
-l1--v-
PEAK DETECTOR
OUTPUT
FF- Q
BIPOLAR
OUTPUT
Figure 5A: Voltage waveform. at the output. of the varlou. functional blocks within the RPT-81 Integrated circuit. The output
pul... of the amplifier trip some combination of the level-detecting comperetora.
PAGE 15-216
tlve or negative signal on the channel output pair. The design
is such that, in most instances (U.S. and European), the
generated signals are nominally square pulses. Different
theories as to improving performance by band-limiting the
output stage have been discussed and, in some instances,
implemented. However, the majority opinion still seems to
favor the square-wave components.
The repeater can be considered a combination of discrete
yet interrelated functions. The overall function of the repeater
is the shaping of incoming pulses, the retiming of these
pulses, and the generation of an equivalent output stream.
ICAPPROACH
In PMI's RPT-81 and RPT-82, the equalization and amplification of the incoming pulse train is achieved through a bipolar amplifier with an external equalization network controlled
by feedback from the amplifier outputs (Figure 5). The result
is that the pulses peak so the majority of the pulse amplitude
is restricted to its own time slot.
The automatic attenuation of the pulses is done by an ALBO
(automatic line build-out) circuit actuated through a buffer
circuit on chip. The output pulses of the amplifier will trip one
or all ofthe three level-detecting comparators. In terms of the
ALBO feature, if the incoming pulses exceed a specified
peak-reference value, the comparator generates current
pulses that flow into the ALBO filter external to the chip and
charge capacitor CF.
The voltage at the ALBO filter is applied, in turn, to the base
ofthe internal ALBO buffer transistor. The buffer will turn on
when its base voltage exceeds approximately 1.7 volts. This
'on voltage' is also specified in the electrical characteristics
of both the RPT-81 and RPT-82. The ALBO diode acts as a
series impedance, normally much larger, and therefore the
dominant factor; than the shunt impedance of the external
network. As the current increases at the buffer, the diode
impedance decreases and the shunt impedance becomes
dominant.
The overall effect is to increase the ALBO attenuation as the
filter voltage level increases. The result is that the feedback
loop will adjust itself until the pulses out of the preamplifier
are equal to the fixed reference. The references for the other
level detector and rectifier are set at fixed ratios of this peak
reference. Therefore, their thresholds are fixed with respect
to the pulse shape and relative amplitude.
On the RPT-81 (not the RPT-82), a clock shutdown circuit,
which is activated by the current levels from the ALBO
buffer, is also provided. This shutdown circuit turns off the
clock amplifier at low input levels, thus neither the regenerated clock nor the strobe outputs are enabled at the output
buffer flip-flops. The circuit was incorporated to prevent
random-noise pulses from being reproduced as valid output
pulses. The problem, however, can be that at long line
lengths the correct signals are too low in energy to activate
the clock circuit. Presently, PMI has customers using both
schemes in their repeater designs.
The timing of the circuit is based upon the pulsing of a
resonant tank circuit. The full-wave-rectifier comparator
output pulses the tank network. The pulses try to "force" the
oscillator circuit to phase lock to the incoming pulse waveform, while the tank attempts to resonate at its preset (with
external components) frequency. The result of the two factors is a clock circuit that runs at an average bit rate for the
incoming waveforms.
Again, the value of a for the tank circuit will help determine
the oscillator accuracy. If the a is high, the resonant frequency dominates and it is more difficultto phase-lock to the
incoming pulse rate. A high a circuit also changes considerably with the temperature and long-term component drift. A
a value that is too low will cause adverse affects on the
oscillator circuit by the jitter present in the pulse stream. This
means the jitter will then also be transferred to the output
pulse train as well. For both the RPT-81 and RPT-82, as of
greater than 75 are recommended.
The logic-threshold comparator provides the detection function for incoming pulses. For positive received pulses, a
negative pulse is generated on the T+ line; for incoming
negative pulses, a pulse is sent on the T- line. The clock
amplifier "squares" the timing waveform from the oscillation
circuit and produces a square clock signal and a negative
strobe pulse. The strobe pulses are 'anded' with the logic
outputs (T+ or T-) to set the output buffer flip-flops.
The strobe is coincident with the positive edge of the clock
signal generated by the tank circuit. Once the appropriate
flip-flop is set by the combination of the logic output and the
strobe pulse, the output driver stage causes current to flow
through the proper half of the output transformer, thus
regenerating the received bipolar pulse. The falling (negative) edge of the internal clock signal serves to reset the
output flip-flops and thereby terminate the output pulse.
This is important to prevent the regenerated waveform from
following the data threshold instead of the clocking circuit.
One option is made available to users of both the RPT-81 and
the RPT-82. The internal clock oscillator can operate in
either an injection-locked mode or a pulsed-tank mode. By
grounding a pin on the device, the oscillator is free-running
but is phase-locked to the full-wave rectified output. With the
pin open, the oscillator will only operate when pulsed by an
incoming signal. The circuit then "rings" until the next
incoming pulse is received from the rectifier. In both cases,
the overall effect is to phase-lock the resonant circuit to the
average frequency of the pulse train.
The completed T1 repeater may look something like Figure 6
in a typical configuration. The input transformer provides a
two-to-one step-up from the 100-ohm characteristic Impedance of the line. The matching impedance, in this case, is
doubled to approximately 400 ohms. A fixed attenuation is
added to provide a fixed line build-out of approximately 6dB.
The automatic build-out then provides a varying attenuation
for line lengths up to 36dB.
The equalization network is added to give the preamplifier
higher gains at higher frequencies. This compensates forthe
roll-off characteristics of the preamp and the transmission line.
The oscillator tank circuit provides the resonant frequency
for the oscillator. It is controlled by current pulses generated
as the incoming waveform is receiVed.
PAGE 15-217
T
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REGULATOR NETWORK
Vcc,
VCC2
6.8V
VCC1
4.4V
Vco,
ALBO FILTER
1DOIt!1
FAULT
LOCATING
WINOING
,,~,
VCC'O-~~~----~--------1---~~~--~---t~-------+------J
6.11k
BIAS FEEDBACK
RESISTOR
PREAMPLIFIER
INPUT 1+1
''''''
BIAS FEEDBACK
RESISTOR
INPUT LAG CAPACITOR
II '''"
NOTE:
T1: BOURNS PIN
OR
T2: BOURNS PIN
OR
11: BOURNS PIN
4260-1&20
4285-1163
o.D039pF
4286-2007
' ' 'j
EOUALIZING
NETWORK
4285-1152
4265-1199
Figure 6: The complete T1 repeater system (1.544MHz) using the RPT-81 Integrated circuit. The Input transformer provldel a
2:1 Itep-up from lhe1000hm line Impedance.
GROUND PIN
Vcc,
(4.4VI
VCC2
(6.8VI
RPT-81/82
Figure 7: The Ilmplex power .upply de.lgn conllstl of two zener diode. and a diode float connected to the center tapi of the line
tranlformers. Nominal voltage. are 4.4 and 8.8V.
PAGE 15-218
>5V
TANK CIRCUIT IS
TUNED TO 1.544Hz
1k"
L1'
RECOVERED
CLOCK
"8
..."
~:g~:~Lr-__-i_'3______~'~0-r'~.____~____-i~~____________________"
CLOCK
SHUTDOWN
CIRCUIT
VCC1
OSCILLATOR
STROBE
8 OC
5
PREAMP
OUTPUT
RPT-81 INTEGRATED CIRCUIT
RB
.,00
I
C8
D•1••
-=-
6 ANALOG
CLOCK RECOVERY CIRCUIT (T1 TVPE TRANSMISSION)
-=-
GROUND
Figure I: Integrated-circuit repeaters can allo be used In clock-recovery circuits, al Ihown. Thll circuit can work from a 81ngle
5V lupply.
~
The ALBO filter aids in integrating the pulse output of the
detector. As the voltage increases, more current flows
through the ALBO diode. and the line build-out is characteristic of longer line lengths.
-INPUT
~1~
~
CD ~
_=
L:~T~~ES~~-'-fr_-~~~LWAVE REFTIFIER
_
The power-supply current is available over the signal pair.
The simplex power design consists of two zener diodes and a
diode float connected to the center taps of the line transformers (Figure 7). The nominal voltage values required are
4.4 and 6.8V.
PREAMP OUTPUT
~c,.o"~:~~~1:
PEAK DETECTOR
This design meets the specifications called for in a T1 carrier
repeater. The integrated circuit uses less than 13mA total
current (both voltage supplies). This means the maximum
output current for the total repeater circuit will be under
50mA at worst-case conditions (all ones output signal).
FULLWAVE
RECTIFIER OUTPUT
PEAK DETECTOR
OUTPUT
REGENERATED
CLOCK
FIGURE IA: Showl the voltage waveforml within the circuit.
A final application of the integrated circuits is the use of the
repeater device in a clock recovery circuit. Data transmission
is becoming more important in areas other than longdistance digitized audio. In these instances, the capability of
recovering clocking from the data stream can be advantageous. This can mean single-pair connections that can transfer
data without additional wiring for timing and clock signals.
Using the RPT-81 in conjunction with a precision comparator, such as the PMI CMP-01, will provide a recovery scheme
capable of reproducing a clock waveform from input levels
as low as 35mV peak-to-peak. Any system that requires clock
retrieval from a data signal and synchronization to that signal
can use a circuit similar to this design shown in Figure 8.
PAGE 15-219
II
The test circuit was operated with an AMI incoming code at
frequencies from 64kHz up to 1.544MHz. In the published
design, the Incoming data waveform is capacltively coupled
to an input attenuator using fixed external components and
the internal ALBO diode. Since the impedance at pin 1 of the
device varies inversely with the amplitude ofthe input signal,
the voltage at the preamplifier input (through resistor R2) will
be held to less than 100mV peak-to-peak amplitude. This
gives the design an Input dynamics range of greater than
45dB while still producing a constant output waveform.
This circuit (Figure 8) can work from a single 5-Vdc supply,
and the tests that have been completed show none of the
external component values to have critical tolerances. The
design can be used to recover clocking from an incoming
data stream-again a capability that has proven advantageous for designers of data interfaces In many areas other th/ln
telecom carrier exchanges.
When considering new applications or new repeater designs,
several possibilities have already been approached. Since
the European line requirements are somewhat different from
those In the U.S., a modification in the repeater design has
been suggested. For example, providing a better line simulation and response over a longer Ii ne could require more than
one ALBO network. A chip providing multiple ALBO connections could prove important. In addition, again due to the
longer line lengths, the current requirements are even more
critical, a device requiring only a 5-V supply voltage could be
used in a lower current configuration.
In the U.S., work is presently being done with the use of a
duobinary coding design. This would require some modifications to the present RPT-81 and RPT-82 to provide the
accuracy necessary to reduce intersymbol interference.
I n ali design areas, higher data rates are being considered as
well as the basic 1.544MHz (or 2.045MHz).ln such designs,
monolithic devices could also be valuable to improve transmission and data retrieval.
PAGE 15-220
PMI
APPLICATION NOTE 49
®
DESIGNING A MULTIPLE-CHANNEL
CODER/DECODER WITH BIPOLAR DEVICES
(PRESENTED AT ELECTRONIC DESIGN TELECOM CONFERENCE)
by B. W. Berry
Encoding analog to digital signals and decoding the digital
words back to analog waveforms can be accomplished
through the use of several different systems configurations.
This note describes the building blocks needed to produce
an economical shared-channel coder/decoder circuit capable of meeting all necessary system performance requirements while costing less, on a per channel basis, than a
single-channel codec system.
A codec system in which coding and decoding is provided
for every channel is shown in Figure 1. In theory, when the
"digital transmission highway" reaches the individual phones,
per-channel codecs become the necessary architecture.
However, a shared-channel system, accomplished by multiplexing several analog channels and digitizing them via a
shared coder, offers many advantages. Besides cost savings,
these advantages include reduced circuit board area, reduced
die area, easier incoming device inspection and better component reliability guarantees.
The first "commercial" use of digital transmission within the
telephone network is normally attributed to the T1 Carrier,
initially used in 1962. The T1 Carrier incorporated shared-
channel coders and decoders implemented with discrete
components and situated on several circuit boards. The
co dec portion of the T1 Carrier was actually a linear device,
and compression or expansion of the analog signal was
carried out tlirough the use of a diode matrix. Later years
served to provide various improvements in the initial design.
In 1968, the 02 interface used the wlaw companding logarithm to replace the linear approximation involved in coding
and decoding. This design continued to evolve until 1975,
when, in the 03 interface. shared-channel coders and decoders were contained on 40-pin hybrid circuits. For every 24
channals. four of these hybrid circuits were needed to complete the analog-to-analog conversion. This design was used
up to 1978 when the 04 system further reduced the conversion circuitry to two hybrids (in DIPs) per 24 channels, a 40
pin coder and a 32 pin decoder.
European designs followed a similar pattern of improvement; the basic system was somewhat different in that 32
channels using a higher frequency clocking scheme were
employed. However, the most economical design approach
seemed to designate sharing the coders and decoders
among multiple channels.
y
z
CC
II)
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e
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SINGLE LINE CODEC SYSTEM
:J
a.
a.
•
cc
MUl.TI·
CHANNEL
DIGITAL
MUX
PCM
TRANSMISSION
LINE OR
PCM SYSTEM
MEMORY AND
SWITCHING
MATRIX
SHARED caDEC SYSTEM
PCM
MULTiCHANNEL
ANALOG
MUX
Figure 1: Block diagrams depict Ihared-channel and single
(per-channel) codec configurations.
PAGE 15-221
TRANSMISSION
LINE OR
PCM SYSTEM
MEMORY AND
SWITCHING
MATRIX
The "heart" of the shared-channel coder or decoder became
the companding D/A converter. All of the other components
needed are commonly used In digltal-to-analog conversion
designs throughout industry. The part unique to telecommunications designs· (unique as initially envisioned) is one
that supplies the non-linear transfer function DAC necessary
to provide a wide dynamic range while minimizing bandwidth requirements. Generally, the function required issimilartothat provided by linear converters (as shown in Figure 2).
The difference lies in the current output DAC; in a companding system the step current must increase as multiples ofthe
previous step size, not linearly. The step size is dependent
upon the chord, or essentially the distance from the zero
level. The reference amplifier sets the bias current for the
chord current generator. The value of the chord current is
selected by the digital, 1-out-of-8 selector and is fed to the
step generator. The step generator current is a function of
the chord pedestal current and the digital input value.
The restrictions encountered in producing and designing
such a part lie mainly in the speed and accuracy requirements. Bipolar technology allows the completed companding D/A converter to decode 24 or 32 channels (5.2 or 3.9
I'sec per channel) and encode, with the successive approximation technique, up to 8 channels.
This is the basic premise of the shared-channel "codec"
approach offered by PMI. Through the use of high-speed
bipolar conversion, multiple analog channels are digitized
using a single set of devices. The devices incorporated all
have die areas less than 10,000 square mils and are readily
manufacturable using PMI's bipolar processing techniques.
The cost savings provided by multiple-channel systems are
magnified as the systems incorporate more monolithic
devices.
Additional advantages are obtained; since the devices are all
relatively small, the required circuit board area is reduced oil
a per channel basis. The number of IC's required per channel
is less than one, and all ofthe integrated circuits have 18 pins
or less.
A SHARED EIGHT-CHANNEL DESIGN
One way to see the subtleties of a shared-channel design is
to construct one. PMI has had an eight-channel system
available for customer analysis for two years. In this time,
more than twenty customers have evaluated its performance.
V-
V'
Figure 2: In a companding DAC. step current Increa.e. as
multiples of the previoul step size.
As can be seen, the device provides a select mechanism to
allow either an encode or decode transfer. The difference is a
112 step to minimize quantization distortion between the
encoding and decoding circuits.
The encoder (shown in Figure 3) is comprised of the companding D/A converter (p-Iaw or A-law), an analog multiplexer, a monolithic sample-and-hold, a voltage comparator,
and a voltage reference. To complete the successive approximation technique, a special digital register is added. The
same analog components, with the substitution of a high
slew-rate operational amplifier for the comparator and discarding the sample-and-hold, will produce a multiple channel decoder. In this case, a digital latch is added to interface
from the digital data base to the digital-to-analog converter.
Before looking at performance on an analog input to analog
output basis, the individual AID and D/A circuits will be
discussed.
The encoder design is capable of generating an 8-bit digital
word every 15.6I'sec. This means 8 analog input channels
can be switched, sampled, and converted to digital representation by a Single such circuit. To describe the encoder's
MULTIPLEXER
MULTIPLEXER
AID
ANALOG
CHANNELS
IN
DIGITAL
MUX·
sa
B-BIT
TO
DATA
BUS
Figure 3: Componentl of encoders and decoders.
PAGE 15-222
!
D/A
COMDAC
88189
DMX·
aa
ANALOG
CHANNELS
OUT
function, it is helpful to begin with the clocking waveforms
used to time the successive approximation register, the multiplexer, and the sample-and-hold.
When allocating time to the individual components, the first
area to be considered is the successive approximation
sequence. Considerable time has been spent at PMI determining the most efficient method of minimizing the individual bit times while assuring adequate settling time as each
step in the conversion sequence is reached. Initially, as
shown in Figure 4, D/A converters in conjunction with the
comparator had a combined settling time related to the bit
being determined. As the approximation moved to lower
order bits, the settling time required for the DAC and comparator increased. This was caused by delays in the internal
switching of the DAC, and the fact that as lower order bits are
selected, less current is switched to the output to drive the
comparator. The result was that for the least significant bits
to be determined consistently for small magnitude input
signals, longer delay times between bits were necessary than
for the higher-order bits. This led to the original 8-channel
clocking scheme which provided increased 'bit' settling time
as the approxi mati on routine moved to the lower order bits. It
was realized that by improving some of the internal characteristics of the DAC, this restriction could be relaxed, thus
producing an easier system design. The results were the
redesigned companding DAC's, the DAC-88 and DAC-89.
SAR
CLOCK
SAMPLE ~------H-OL-O-------'L
ENCODE (SBE)
CLOCK
INPUT
AD~~:
--,L______Ji~u~x~------I
3.2,us
O.65!.100k In most
cases), any charge introduced onto the capacitor is not dissipated but is evident as a voltage level.
This phenomena can be measured as an increase in idle
channel noise forthe output channels. In terms of physically
observing the charge distribution, the "idle" channels with 0
input levels show a square wave output. The waveform oscillates from 0 volts (when the channel is selected) to a voltage
dependent upon the charge and the hold capacitor on the
output. The waveform at essentially 8kHz can affect the
noise level of the supposedly quiet channel even within the
audio frequency range.
One approach to reducing the output noise level is to increase
the output hold capacitor value. By using a larger capaCitor,
the charge Introduces a smaller voltage on the output, and
the measured idle channel noise is decreased. This change,
however, introduces another problem In that the larger the
output capaCitor, the longer It takes to generate the output
waveform for each sample. Since the sample time is fixed
(3.9 or 5.2I'sec), this results in fewer channels per dlgital-toanalog conversion circuit. After investigating the charge
Induced effect, it was decided that a modification in the
multiplexer design itself could also aid in reducing the
PAGE 15-224
charge amount. The measurements showning the improvements in system response are given in Tables 1 and 2.
TABLE 1: Idle channel noise for the MUX-88 and the DMX-88.
CHANNEL
MEASURED
IDLE
CHANNEL
NOISE
HOLD
CAP
2
3
4
5
6
7
8
-tl0.8
-tll.l
-tl0.3
-tll.l
-tl0.9
-tll.3
-tll.2
-tlO.O
l0000pf
l0000pf
l0000pf
l0000pf
l0000pf
10000pf
10000pf
10000pf
MUX-88
DMX-88
1
2
3
4
5
6
7
8
}
All
Values
<-70dB
switch to assure sufficient open time between channels. In
this design, the enable function of the analog de-multiplexer
is used to disable the output switches prior to incrementing
the address. The DAC. in conjunction with the op-amp. is
fast enough in some transitions to reach the following
channel output level prior to the previous switch being
opened. By disabling all switches, changing the digital Input
mode and the address selector, and then enabling the
switches, no inter-channel problems are displayed due to the
output de-multiplexer. This slightly reduces the "on"timefor
each output channel, however, the DAC and op-amp are still
more than fast enough to handle the required data rates.
TESTING
Final testing procedure is accomplished by comparing the
performance of the shared-channel codec to the system
requirements as put forward by Bell System and CCITT. The
most common tests for digitizing systems are often a series
of analog-to-analog measurements normally reserved for
installed transmission or switching systems. The first such
test is the signal-to-total distortion measurement, done by
adding a set frequency tone (10200r 1004Hz) to one channel
and measuring the output of that channel after removing the
tone by filtering.
l0000pf
l0000pf
l0000pf
l0000pf
l0000pf
l0000pf
l0000pf
l0000pf
TABLE 2: Idle channel nol8e with reduced hold capacitance.
MUX-88
CHANNEL
MEASURED
IDLE
CHANNEL
NOISE
HOLD
CAP
1
2
3
4
5
6
7
8
--57.2
-57.2
-57.2
--57.2
--57.2
--57.2
-57.2
-57.2
l000pf
1000pf
1000pf
1000pf
1000pf
4300pf
4300pf
4300pf
2
3
4
5
6
7
8
-tl8.6
-tl8.6
-tl8.6
-tl8.6
-tl8.6
<-70
<-70
-tl9.9
l000pf
1000pf
1000pf
l000pf
1000pf
4300pf
4300pf
4300pf
DMX-88
It is in this test (Figure 6) that the response of the companding conversion laws versus the linear-transfer laws becomes
obvious. The companding laws are designed to provide a
flatter signal-to-noise ratio at the higher input levels, while
approximating a higher order linear response curve at the
lower input values. There are presently two methods of generating input signals that are used, dependent upon whose
specifications are being met. The Bell System approach is to
provide a straight sinusoidal input waveform at the prescribed frequency. The CCITT recommendations, however,
also allow for a psuedo-random noise source to be used as
the input signal.
•
z
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II
60
iD
"oz
50
~
o
1;;40
C
, /r---.
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;!
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~
With a reduction in the charge value, the output voltage level
is decreased without an increase of capacitor values. Therefore, the system is able to manage the data rates required.
The redesigned device, designated the DMX-88, has achieved
a reduction in the output charge Injection of 114 to 1/5 the
value measured in the earlier analog multiplexers. This is
seen as an immediate reduction in the output voltage level
for common capacitor values. And, more importantly, it enables the user to reduce the hold capacitor, still achieve the
system required idle channel noise levels, and decode at a
higher output rate.
Concerning crosstalk In the decoder, the most Important
consideration would seem to be controlling the output
t5" 20
L
/ /f"
~
DAC·88 EX
TESTED WITH_
sT
in
OID
10
-60
-50
-40
......
-30
-20
I
-10
INPUT LEVEL (dBmO)
Figure 6: Signal-to-total distortion for the DAC-88EX.
Arguments are heard for both approaches; our measurements have been completed using both methods dependent
upon which DAC (A-law or wlaw) is being evaluated. An
interesting comparison can be made between the response
of the present companding D/A converter (DAC-88/89) and
PAGE 15-225
The next test results normally shown for "codec" performance are the gain linearity or tracking. As the Input signal is
reduced in magnitude, the output signal is measured to
determine its loss in comparison. Again the CCITT and the
Bell System standards differ in the type of input Signal being
used and the specifications for the measured output. The
results in Figure 8 with the 8-channel system show compliance at all input levels. By comparing the older DAC
design to the new version, another effect of the Improved
accuracy and settling time becomes evident. Expeclally at
the low input levels (-55 to --60dBmO), an obvious improvement is seen at the higher bit rate with the new DAC-89.
-45
-35
/,
-25
-15
-60
/
'/
~
....--I--\
V
\\
T~~~:~~TH- ' - -
I I
NOISE
-50
-40
-30
-20
INPUT LEVEL (dBmO)
-10
1.0
I
Figure SA: Signal-to-total distortion for the DAC-89EX.
0.5
the original designs (DAC-86/87) by measuring the systems
using constant bit clocking. As was mentioned earlier, the
original designs of the converters required a slightly modified clocking scheme to achieve the required system performance. By running each device set at the higher frequency
clock for the successive approximation sequence, the effect
of the slower settling times and slightly worse chord 0 accuracy can be seen in terms of the system parameters. In Figure
7 it can be seen that the signal-lo-distortion curves fall off
more rapidly for the older devices at lower input levels.
........
V"
-1. 0
I
-0.5
60
-30
-40
-50
- 20
10
INPUT lEVEL (dBmO)
Figure 8: Gain tracking for the DAC-88EX.
60
I
DAJ.. EX
o - f- TESTED WITH
~
SINUSOID
,............
I'-.
0
V/
~
'-"
/'
~
""-
z
<1
t::I -0.5
/
-50
-40
-30
-20
INPUT LEVEL (dBmO)
-6.
-10
J
50
-40
30
-20
INPUT lEVEL (dBmO!
10
Figure 8A: Gain tracking for the DAC-89EX.
\
iii
.:E -45
-35
C
-'
;!
J
~ -25
~
-15
;;
-s
-60
,/
V
r
1.0
1-,
is
g
Ii;
~
~
;;
,/
Figure 7: Signal-to-total distortion for the DAC-8SEX.
"
0.0
i<
10
-60
I
+0.5
~
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(602) 249-2232 TWX 910-951-4282
PHOENIX
DIPLOMAT WESTATES
18401 N. 25th Ave., Suite 8
Phoenix. AZ 85023
(602) 866-7525. (602) 242-2941
TEMPE
BELL INDUSTRIES
52'1 S. 48th St.. Bldg. #107
Tempe, AZ 85281
(602) 966-7800 TWX 910-ll50-D133
CALIFORNIA
CHATSWORTH
DIPLOMAT WESTATES
20151 Bahama 5t.
Chatsworth, CA 91311
CALIFORNIA
FLORIDA
MASSACHUSETTS
SAN DIEGO
DIPLOMAT WESTATES
9787 Aero Dr., Suite E
San Diego, CA 92123
(714) 292-5693
FT. LAUDERDALE
HALL-MARK ELECTRONICS
1671 W. McNab Rd.
Ft. Lauderdale, FL 33309
(305)971-11280 TWX510-ll58-11720
LEXINGTON
HARVEY ELECTRONICS
44 Hartwell Ave.
Lexington, MA 02173
(617) 861-11200 TWX 710-32S-8617
SAN DIEGO
WYLE DISTRIBUTION GROUP
9525 Chesapeake Dr.
San Diego, CA 92123
(714) 565-11171 TWX 910-335-1590
ORLANDO
HALL-MARK ELECTRONICS
7233 Lake Ellenor Or.
Orlando, FL 32809
(305) 855-4020 TWX 810-850-Dl05
SAN JOSE
ANTHEM ELECTRONICS
174 Component Or.
San Jose, CA 95131
(408) 946-11000 TWX 910-338-2038
ORLANDO
PIONEER ELECTRONICS
6220 S. Orange Blossom Trail,
Suite 412
Orlando, FL 32809
(305) 859-3600 TWX810-85O-D177
SANTA CLARA
WYLE DISTRIBUTION GROUP
3000 Bowers Ave.
Santa Clara, CA 95052
(408) 727-2500 TWX 910-338-D296
GEORGIA
NORCROSS
HALL-MARK ELECTRONICS
6410 Atlantic Blvd., Suite 115
Norcross, GA 30071
(404) 447-l1000 TWX 810-766-4510
SUNNYVALE
BELL INDUSTRIES
1161 N. Fairoaks Ave.
Sunnyvale, CA 94086
(408) 734-11570 TWX 910-339-11378
ILLINOIS
SUNNYVALE
DIPLOMAT WESTATES
1283-F Mountain View-Alviso Rd.
Sunnyvale, CA 94086
(408) 744-1555 TLX 352-D46
BENSENVILLE
HALL-MARK ELECTRONICS
1177 Industrial Dr.
Bensenville, IL 60106
(312) 860-3800 TWX 910-651-D185
TUSTIN
ANTHEM ELECTRONICS
2661 Dow Ave.
Tustin, CA 92680
(714) 730-l1000 TWX 910-895-1583
ELK GROVE VILLAGE
PIONEER ELECTRONICS
1551 carmen Or.
Elk Grove Village, IL 60007
(312) 437-9680 TWX 910-222-1834
COLORADO
INDIANA
DENVER
HALL-MARK ELECTRONICS
1820 S. Sheridan Blvd., Suite 206
Denver, CO 80226
(3031 934-8859
(8001 332-11326 (CO only)
INDIANAPOLIS
PIONEER ELECTRONICS
6408 Castle Place Or.
Indianapolis, IN 46250
1317) 849-7300 TWX 810-260-1794
(213) 341-4411 TLX 67·7069
CHATSWORTH
ANTHEM ELECTRONICS
21730 Nordhoff SI.
Chatsworth, CA 91311
(213) 700-1000 TWX 910-493-2083
COSTA MESA
DIPLOMAT WESTATES
3001 Redhill Ave., Bldg. 3, Suite 107
Costa Mesa. CA 92626
(714) 549-8401
ELSEGUNDD
WYLE DISTRIBUTION GROUP
124 Maryland St.
EI Segundo, CA 90245
(213) 322-8100 TWX 910-348-7111
GARDENA
BELL INDUSTRIES
306 E. Alondra Blvd.
Gardena, CA 90247
(213) 515-1800 TWX 910-348-8336
SAN DIEGO
ANTHEM ELECTRONICS
4125 Sorrento Valley Blvd.
San Diego, CA 92121
(714) 279-8200 TWX 910-335-1515
KANSAS
THORNTON
WYLE DISTRIBUTION GROUP
451 E. 124th Ave.
Thornton, CO 80241
(3031 457-WYLE
LENEXA
HALL-MARK ELECTRONICS
10816 Lakeview Dr.
Lenexa, KS 66219
(913) 886-4747 TWX910-'749-6620
WHEAT RIDGE
BELL INOUSTRIES
8155 W. 48th Ave.
Wheat Ridge, CO 80033
1303) 424-1985 TWX 910-ll38-D393
MARYLAND
CONNECTICUT
NORWALK
HARVEY ELECTRONICS
112 Main St.
Norwalk, CT 06851
(203) 853-1515 TWX 710-468-3373
PAGE 17-4
NORWOOD
GERBER ELECTRONICS
128 Carnegie Row
Norwood, MA 02062
(617) 769-8000 TWX 710-33&-1987
WESTBOROUGH
FUTURE ELECTRONICS
133 Flanders Rd.
Westborough, MA 01681
(617) 366-2400 TWX 710-390-0374
MICHIGAN
LIVONIA
PIONEER ELECTRONICS
13486 Stamford
Livonia. MI 48150
1313) 525-1800 TWX 810-242-3271
MINNESOTA
BLOOMINGTON
HALL-MARK ELECTRONICS
7838 12th Ave.
So. Bloomington, MN 55802
(612) 854-4747 TWX 910-576-3187
MINNETONKA
PIONEER ELECTRONICS
10203 Bren Road East
Minnetonka, MN 55343
(612) 935-8444 TWX 910-876-2738
MISSOURI
EARTH CITY
HALL-MARK ELECTRONICS
13789 Rider Trail
Earth City. MO 83045
(314) 291-8350 TWX 910-762-D872
NEW JERSEY
PINE BROOK
HARVEY ELECTRONICS
45 Route 46
Pine Brook, NJ 07058
(201 ) 575-3510 TWX 710-734-4382
CHERRY HILL
HALL-MARK ELECTRONICS
2091 Springdale Rd.
Cherry Hill, NJ 08003
(809) 424-7300 TWX 710-ll4D-D680
NEW MEXICO
BALTIMORE
HALL-MARK ELECTRONICS
6655 Amberton Or.
Baltimore, MO 21227
(301) 798-11300 TWX 710-1162-1942
ALBUQUERQUE
ALLIANCE ELECTRONICS. INC.
11030 Cochiti S.E.
Albuquerque, NM 87123
(505) 292-3360. (800) 545-8288
TWX 910-1189-1151
GAITHERSBURG
PIONEER ELECTRONICS
9100 Gaither Rd.
Gaithersburg, MO 20817
(301) 948-0710 TWX 710-ll28-D545
ALBUQUERQUE
BELL INDUSTRIES
11728 Linn N.E.
All,uquerque, NM 87123
(5051292-2700 TWX910-ll89-D625
NEW YORK
TEXAS
CANADA
BINGHAMTON
HARVEY ELECTRONICS
P.O. Box 1208. Vestal Parkway E.
Binghamton. NY 13902
(607)748-8211 TWX 510-252-0893
AUSTIN
HALL-MARK ELECTRONICS
12211 Technology Blvd.
Austin. TX 78759
(512)258-8848 TWX 910-874-2010
ONTARIO
FUTURE ELECTRONICS. INC.
Baxter Centre. 1050 Baxter Rd.
Ottawa. Ontario K2C 3P2
(613) 820-8313 TWX 610-563-1697
DALLAS
HALL-MARK ELECTRONICS
11333 Pagemill Dr.
Dallas. TX 75222
(214)343-5000 TWX 910-a67-4775
ONTARIO
FUTURE ELECTRONICS, INC.
4800 Duffer!n St.
Downsview. Ontario M3H 5$8
(416)663-5563 TWX 610-491-1470
FAIRPORT
HARVEY ELECTRONICS
840 fairport Park
Fairport, NY 14450
(718)381-7070 TWX 510-253-7001
WOODBURY
HARVEY ELECTRONICS
60 Crossway Park West
Woodbury, NV 11797
(516)921-8700 TWX 510-221-2184
NORTH CAROLINA
GREENSBORO
PIONEER ELECTRONICS
103 Industrial Ave.
Greensboro, Ne 27406
(919)273-4441 TWX 510-925-1114
RALEIGH
HALL-MARK ELECTRONICS
1208 Front St., Bldg. K
Raleigh, NC 27609
(919)832-4465 TWX 510-926-1831
OHIO
CLEVELAND
PIONEER ELECTRONICS
4800 E. 131 sl St.
Cleveland, OH 44105
(218)587-3600 TWX 810-422-2211
DAYTON
PIONEER ELECTRONICS
4433 Interpoinl Blvd.
Dayton, OH 45424
(513)236-9900 TWX 810-459-1822
HIGHLAND HEIGHTS
HALL-MARK ELECTRONICS
175 Alpha Park
Highland Heights, OH 44143
(216)473-2907
WESTERVILLE
HALL-MARK ELECTRONICS
6130 Sunburry Rd .• Suite 8
Westerville. OH 43081
(614)891-4555
OKLAHOMA
TULSA
HALL-MARK ELECTRONICS
5460 S. 103rd East Ave.
Tulsa, OK 74145
(918)835-8458 TWX 910-845-2290
PENNSYLVANIA
HORSHAM
PIONEER ELECTRONICS
261 Gibraltar Rd.
Horsham. PA 19044
(215)874-4000 TWX 510-865-8778
PITTSBURGH
PIONEER ELECTRONICS
259 Kappa Or.
Pittsburgh, PA 15238
(412)782-2300 TWX 710-795-3122
QUEBEC (MONTREAL)
FUTURE ELECTRONICS, INC.
237 Hymus Blvd.
Pointe Claire. Quebec HeR 5C7
(514)694-7710 TWX 610-421-3251
HOUSTON
HALL-MARK ELECTRONICS
8000 Westglen
Houston. TX 77063
(713)781-8100 TWX 910-881-2711
HOUSTON
PIONEER ELECTRONICS
5853 Point West Dr.
Houston, TX 77036
(713) 988-5555 TWX 910-881-1606
UTAH
SALT LAKE CITY
BELL INDUSTRIES
3639 W. 2150 South
Salt Lake City. UT 84120
(801) 972-6969 TWX 910-925-5686
WASHINGTON
BELLEVUE
WYLE DISTRIBUTION GROUP
1750 132nd Ave. N.E.
Bellevue, WA 98005
(206)453-11300 TWX 910-443-2526
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WISCONSIN
ID
DAKCREEK
HALL-MARK ELECTRON)CS
9667 S. 20th St.
Oak Creek. WI 53154
( 414)761-3000
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CANADA
ALBERTA
FUTURE ELECTRONICS INC.
5809 Macleod Trail South. Unit 109
Calgary. Alberta T2H OJ9
(403)259-8408 TWX 610-821-1927
ALBERTA
INTEK ELECTRONICS LTD.
461&-99th St.
Edmonton, Alberta T6E 5H5
(403)437-2755 TWX 610-831-1101
TLX 037-2970
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BRITISH COLUMBIA
FUTURE ELECTRONICS, INC.
3070 Kingsway
Vancouver. BC V5R 5J7
(604) 438-5545 TWX 610-922-1668
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BRITISH COLUMBIA
INTEK ELECTRONICS LTD.
8385 St. George St. #10
Vancouver, BC V5X 4P3
(604)324-8831 TWX 610-922-5032
TLX 04-507578
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II
PAGE 17-5
INTERNATIONAL
REPRESENTATIVES
EUROPEAN
HEADQUARTERS
BOURNSAG
--
FRANCE
KOREA
TAIWAN
Ohmic SA
21/23 rue des Ardennes
75019 Pario
Phone: 01-203 98 33
Samco International
342 Madison Avenue
New York, NY 10017
Phone: (212) 887-8929
Telex: 62559 WUI
Cable "SAMCOIN·· New York
Samco International
342 Madison Avenue
New York, NY 10017
Samco Affiliate
Hansun International
CPO Box 2983 Seoul
Telex: 28.()958
Mao Shing Enterprises Co., Ltd.
6-3 No.9 Nanking East Ad., S.e.c.
MeI·Lo Nanking Building
Taipei
Republic of China
Telex: 230008
Zugen,InI. . 7.
GERMANY
'wI_
--=
80umsGmbH
Pootfach 1155
042-33 33 33
ToIo.. 888722
AUSTRAUA
VSI Electronic. (Ply) Ltd.
21 Chandos Street
CroWl Nest HSW 2065
Tecnico Electronics
53 Carrington Road
Marrlckvlll., NSW 2204:
Tecnlco Electronics
2HlghStreat
Northcote
AUSTRIA
Ing. Otto Folger
Elektronische Garita
Eberhardstrasae 63
7000 Stuttgart t
Phone: 0711-24 29 36
Telex: 721 558
GREECE
GermanlsCo.
Trade of Electronic Gear
Aristotelous St. 47-49
P.O. Box 1209
Athens
Phone: Ot-ll21 58 25
Telex: 219 179
HONG KONG
Samco International
342 Madison Avenue
New York, NY 10017
Phone: (212) 887--8929
Telex: 62559 WUI
Cable "SAMCOIN" New York
1080 Vienna
INDIA
Phone: 0222....32639
Telex: 131 882
Hind Industrial & Mercantile Corp.
Private L.T.C.
205~A, Dr. Annie Beaant Ad.
Bombay 400 018
Bourna (Nederland) B. V.
Van Tuyl van Serooskerkestr. 85
P.O. Box 37
2270 AA Voorburg
Phone: 070.87 44 00
Telex: 32 023
Phone: 37354<1
Telegram: 'ADEK' Worll~Bombay
Fegu Electronics, Inc.
. 3308 Middlefield Rd.
Palo Alto, CA 9430G
Phone: 493-3480
Telectra S.A.A.L.
Aua Aodrlgo da Fonseca 103
Lisbon 1
Phone: 19-68 60 72
Telex: 12 598
SINGAPORE
Samco International
New York. NY 10017
Phone: (212) 887-8929
Telex: 62559 WUI
Cable "SAMCOIN" New York
SOUTH AFRICA
Associated Electronics (pty) Ltd.
P.O. Box 31094, Braamtonteln 2017
Assooiated House, 150 Caroline St
Brixton, Johannesburg
Phone: 839 18 24
Telex: 88432
ISRAEL
DENMARK
Tags Olaen A/S
Ballerup 8yvej 222
2750" Ballerup
Phone: 02-65 81 11
Telax: 35 293
EASTERN EUROPE
Ettrans
Handelsgesellschaft mbH
Stuwerstruse 1.-3
1020 Vienna
Phone: 0222·24 71 37
Tel.ex: ~31 487
Rapac Electronics Ltd.
Components Division
12 Kahllat Venezia Street
P.O. Box 18053
61 180 Tel Aviv
Phone: 03.0$771 15
Telex: 33528
ITALY
Technic S.r.L.
Via Brembo 21
21·20139 Milan
Phone: 02-669 57 46
Telex: 316651
SPAIN
Hispano Electronlca S.A.
Poligono industrial Urtinsa
Apartado de Correos 48
Alcorcon (Madrid)
Phone: 01-81941 08
Telex: 42 634
SWEDEN
"8exab Elektronik AS
P.O. Box 2101
18302 Taby
Phone: 08-768 05 60
Telex: 10 912
JAPAN
FINLAND
InaelaOy
Kurnpulantle 1
00520 Helsinki 52
Phone: 80-735774
Telex: 122 217
Nippon PMI Corporation
Haratetsu Building
.
4-1·11, Kudan Kite
Chiyodaku, Tokyo
Phone: (03) 234--1411
Telex: 781 J 27632
TURKEY
NEL, NUkleer Elaktronlk Ltd.
Silmer Sokak No. 42
Yanisehlr~Ankara
Phone: 041-30 15 to
Telex: 42229
UNITED KINGDOM
PORTUGAL
342 Madison Avenue
Bllndenga8se 38
BENELOX
NORWAY
AlS Kjell Bakke
Tekniake Agenturer
Nygt 48, P.O. Box 143
2011 StrCil mmen
Phone: 02-711872
Telex: 19 407
Phone: (2t2)68H1929
Telex: 62558 WUI
Cable "SAMCOIN" New York
SWITZERLAND
Bourns (Schweiz) AG
ZugeratrasS8 74
6340 Baar
Phone: 042-33 33 33
Telex: 888 722
PAGE 17-6
Boums Electronics Ltd.
Hodford House
t7127 High Street
Hounslow. Middlesex TW3 1TE
Phone: 0100572 85 31 "
Telex: 264 485
YUGOSLAVIA
Podravka~Unltrada
Sektor inozamna zaatupstva
P.O. Box 619
Mazuranicev t'll 3
4100t Zagreb
Phone: 041-41 92 84
Telex: 22235
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